diff --git a/APP_Framework/Applications/Kconfig b/APP_Framework/Applications/Kconfig new file mode 100644 index 0000000..7d66db5 --- /dev/null +++ b/APP_Framework/Applications/Kconfig @@ -0,0 +1,22 @@ +menu "Applications" + + menu "config stack size and priority of main task" + config MAIN_KTASK_STACK_SIZE + int "Set main task stack size" + default 1024 + config MAIN_KTASK_PRIORITY + int + default 4 if KTASK_PRIORITY_8 + default 16 if KTASK_PRIORITY_32 + default 85 if KTASK_PRIORITY_256 + endmenu + + source "$APP_DIR/Applications/ota/Kconfig" + + source "$APP_DIR/Applications/app_test/Kconfig" + source "$APP_DIR/Applications/connection_app/Kconfig" + source "$APP_DIR/Applications/control_app/Kconfig" + source "$APP_DIR/Applications/knowing_app/Kconfig" + source "$APP_DIR/Applications/sensor_app/Kconfig" + source "$APP_DIR/Applications/embedded_database_app/Kconfig" +endmenu diff --git a/APP_Framework/Applications/Make.defs b/APP_Framework/Applications/Make.defs new file mode 100644 index 0000000..581c8c1 --- /dev/null +++ b/APP_Framework/Applications/Make.defs @@ -0,0 +1,7 @@ +############################################################################ +# APP_Framework/Applications/Make.defs +############################################################################ +CONFIGURED_APPS += $(APPDIR)/../../../APP_Framework/Applications +CONFIGURED_APPS += $(APPDIR)/../../../APP_Framework/Applications/general_functions/list + +include $(wildcard $(APPDIR)/../../../APP_Framework/Applications/*/Make.defs) diff --git a/APP_Framework/Applications/Makefile b/APP_Framework/Applications/Makefile new file mode 100644 index 0000000..8c92833 --- /dev/null +++ b/APP_Framework/Applications/Makefile @@ -0,0 +1,39 @@ +include $(KERNEL_ROOT)/.config + +ifeq ($(CONFIG_ADD_NUTTX_FETURES),y) + include $(APPDIR)/Make.defs + CSRCS += framework_init.c + include $(APPDIR)/Application.mk +endif + + +ifeq ($(CONFIG_ADD_XIZI_FETURES),y) + SRC_DIR := general_functions app_test + + SRC_FILES := main.c framework_init.c + ifeq ($(CONFIG_LIB_LV),y) + SRC_DIR += lv_app + endif + + ifeq ($(CONFIG_APPLICATION_OTA),y) + SRC_DIR += ota + endif + + ifeq ($(CONFIG_APPLICATION_SENSOR),y) + SRC_DIR += sensor_app + endif + + ifeq ($(CONFIG_APPLICATION_CONNECTION),y) + SRC_DIR += connection_app + endif + + ifeq ($(CONFIG_APPLICATION_KNOWING),y) + SRC_DIR += knowing_app + endif + + ifeq ($(CONFIG_APPLICATION_CONTROL),y) + SRC_DIR += control_app + endif + + include $(KERNEL_ROOT)/compiler.mk +endif \ No newline at end of file diff --git a/APP_Framework/Applications/SConscript b/APP_Framework/Applications/SConscript new file mode 100644 index 0000000..e26d195 --- /dev/null +++ b/APP_Framework/Applications/SConscript @@ -0,0 +1,20 @@ +import os +Import('RTT_ROOT') +Import('rtconfig') +from building import * + +cwd = GetCurrentDir() + +SOURCES = ['framework_init.c'] +path = [cwd] +objs = [] +group = DefineGroup('sensor', SOURCES, depend = [], CPPPATH = [cwd]) +objs = objs + group +list = os.listdir(cwd) + +for d in list: + path = os.path.join(cwd, d) + if os.path.isfile(os.path.join(path, 'SConscript')): + objs = objs + SConscript(os.path.join(path, 'SConscript')) + +Return('objs') diff --git a/APP_Framework/Applications/app_test/Kconfig b/APP_Framework/Applications/app_test/Kconfig new file mode 100644 index 0000000..5c03889 --- /dev/null +++ b/APP_Framework/Applications/app_test/Kconfig @@ -0,0 +1,33 @@ +menu "test app" + menuconfig USER_TEST + bool "Enable application test function " + default n + + if USER_TEST + config USER_TEST_SPI_FLASH + bool "Config test spi flash" + default n + + menuconfig USER_TEST_ADC + bool "Config test adc" + default n + if USER_TEST_ADC + if ADD_XIZI_FETURES + config ADC_DEV_DRIVER + string "Set ADC dev path" + default "/dev/adc1_dev" + endif + endif + + menuconfig USER_TEST_DAC + bool "Config test dac" + default n + if USER_TEST_DAC + if ADD_XIZI_FETURES + config DAC_DEV_DRIVER + string "Set DAC dev path" + default "/dev/dac_dev" + endif + endif + endif +endmenu diff --git a/APP_Framework/Applications/app_test/Makefile b/APP_Framework/Applications/app_test/Makefile new file mode 100644 index 0000000..8a74e55 --- /dev/null +++ b/APP_Framework/Applications/app_test/Makefile @@ -0,0 +1,15 @@ +SRC_FILES := + +ifeq ($(CONFIG_USER_TEST_SPI_FLASH),y) + SRC_FILES += test_spi_flash.c +endif + +ifeq ($(CONFIG_USER_TEST_ADC),y) + SRC_FILES += test_adc.c +endif + +ifeq ($(CONFIG_USER_TEST_DAC),y) + SRC_FILES += test_dac.c +endif + +include $(KERNEL_ROOT)/compiler.mk diff --git a/APP_Framework/Applications/app_test/test_adc.c b/APP_Framework/Applications/app_test/test_adc.c new file mode 100644 index 0000000..e6ab38e --- /dev/null +++ b/APP_Framework/Applications/app_test/test_adc.c @@ -0,0 +1,61 @@ +/* +* Copyright (c) 2020 AIIT XUOS Lab +* XiUOS is licensed under Mulan PSL v2. +* You can use this software according to the terms and conditions of the Mulan PSL v2. +* You may obtain a copy of Mulan PSL v2 at: +* http://license.coscl.org.cn/MulanPSL2 +* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, +* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, +* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. +* See the Mulan PSL v2 for more details. +*/ + +/** +* @file: test_adc.c +* @brief: a application of adc function +* @version: 1.1 +* @author: AIIT XUOS Lab +* @date: 2022/1/7 +*/ + +#include +#include +#include + +void test_adc() +{ + int adc_fd; + uint8 adc_channel = 0x0; + uint16 adc_sample, adc_value_decimal = 0; + float adc_value; + + adc_fd = PrivOpen(ADC_DEV_DRIVER, O_RDWR); + if (adc_fd < 0) { + printf("open adc fd error %d\n", adc_fd); + return; + } + + struct PrivIoctlCfg ioctl_cfg; + ioctl_cfg.ioctl_driver_type = ADC_TYPE; + ioctl_cfg.args = &adc_channel; + if (0 != PrivIoctl(adc_fd, OPE_CFG, &ioctl_cfg)) { + printf("ioctl adc fd error %d\n", adc_fd); + PrivClose(adc_fd); + return; + } + + PrivRead(adc_fd, &adc_sample, 2); + + adc_value = (float)adc_sample * (3.3 / 4096); + + adc_value_decimal = (adc_value - (uint16)adc_value) * 1000; + + printf("adc sample %u value integer %u decimal %u\n", adc_sample, (uint16)adc_value, adc_value_decimal); + + PrivClose(adc_fd); + + return; +} + + SHELL_EXPORT_CMD(SHELL_CMD_PERMISSION(0)|SHELL_CMD_TYPE(SHELL_TYPE_CMD_MAIN), + adc, test_adc, read 3.3 voltage data from adc); diff --git a/APP_Framework/Applications/app_test/test_dac.c b/APP_Framework/Applications/app_test/test_dac.c new file mode 100644 index 0000000..60c2f8b --- /dev/null +++ b/APP_Framework/Applications/app_test/test_dac.c @@ -0,0 +1,60 @@ +/* +* Copyright (c) 2020 AIIT XUOS Lab +* XiUOS is licensed under Mulan PSL v2. +* You can use this software according to the terms and conditions of the Mulan PSL v2. +* You may obtain a copy of Mulan PSL v2 at: +* http://license.coscl.org.cn/MulanPSL2 +* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, +* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, +* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. +* See the Mulan PSL v2 for more details. +*/ + +/** +* @file: test_dac.c +* @brief: a application of dac function +* @version: 2.0 +* @author: AIIT XUOS Lab +* @date: 2022/1/11 +*/ + +#include +#include +#include + +void test_dac() +{ + int dac_fd; + uint16 dac_set_value = 800; + uint16 dac_sample, dac_value_decimal = 0; + float dac_value; + + dac_fd = PrivOpen(DAC_DEV_DRIVER, O_RDWR); + if (dac_fd < 0) { + KPrintf("open dac fd error %d\n", dac_fd); + return; + } + + struct PrivIoctlCfg ioctl_cfg; + ioctl_cfg.ioctl_driver_type = DAC_TYPE; + ioctl_cfg.args = &dac_set_value; + if (0 != PrivIoctl(dac_fd, OPE_CFG, &ioctl_cfg)) { + KPrintf("ioctl dac fd error %d\n", dac_fd); + PrivClose(dac_fd); + return; + } + + PrivRead(dac_fd, &dac_sample, 2); + + dac_value = (float)dac_sample * (3.3 / 4096);//Vref+ need to be 3.3V + + dac_value_decimal = (dac_value - (uint16)dac_value) * 1000; + + printf("dac sample %u value integer %u decimal %u\n", dac_sample, (uint16)dac_value, dac_value_decimal); + + PrivClose(dac_fd); + + return; +} +SHELL_EXPORT_CMD(SHELL_CMD_PERMISSION(0)|SHELL_CMD_TYPE(SHELL_TYPE_CMD_MAIN), + test_dac, test_dac, set digital data to dac); diff --git a/APP_Framework/Applications/app_test/test_spi_flash.c b/APP_Framework/Applications/app_test/test_spi_flash.c new file mode 100644 index 0000000..3a4a065 --- /dev/null +++ b/APP_Framework/Applications/app_test/test_spi_flash.c @@ -0,0 +1,161 @@ +/* + * Copyright (c) 2006-2021, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2016-09-28 armink first version. + */ + +/** +* @file test_spi_flash.c +* @brief support to test spi flash function +* @version 1.0 +* @author AIIT XUOS Lab +* @date 2021-05-17 +*/ + +/************************************************* +File name: test_spi_flash.c +Description: support spi flash function test +Others: add spi flash test cmd from SFUD/blob/master/demo/stm32f2xx_rtt/RT-Thread-2.1.0/components/drivers/spi/spi_flash_sfud.c + https://github.com/armink/SFUD/ +History: +1. Date: 2021-05-17 +Author: AIIT XUOS Lab +Modification: +1. support spi flash open, read and write function +*************************************************/ + +#include +#include +#include +#include + +#define SPI_FLASH_PATH "/dev/spi1_W25Q64" +#define FlashDataPrint(ch) ((unsigned int)((ch) - ' ') < 127u - ' ') + +static int spi_flash_fd; + +void FlashOpen(void) +{ + x_err_t ret = EOK; + + spi_flash_fd = open(SPI_FLASH_PATH, O_RDWR); + if (spi_flash_fd < 0) { + KPrintf("open spi flash fd error %d\n", spi_flash_fd); + } + + KPrintf("Spi Flash init succeed\n"); + + return; +} +SHELL_EXPORT_CMD(SHELL_CMD_PERMISSION(0)|SHELL_CMD_TYPE(SHELL_TYPE_CMD_MAIN), + FlashOpen, FlashOpen, open spi flash device); + +void FlashRead(int argc, char *argv[]) +{ + x_size_t i, j = 0; + uint32 addr; + uint32 size; + uint8 data[16]; + + struct BusBlockReadParam read_param; + memset(&read_param, 0, sizeof(struct BusBlockReadParam)); + + memset(data, 0, 16); + + if (3 != argc) { + KPrintf("FlashRead cmd format: FlashRead addr size.\n"); + return; + } else { + addr = strtol(argv[1], NULL, 0); + size = strtol(argv[2], NULL, 0); + + read_param.buffer = data; + read_param.pos = addr; + read_param.size = size; + + if (read_param.buffer) { + read(spi_flash_fd, &read_param, size); + if (size == read_param.read_length) { + KPrintf("Read the %s flash data success. Start from 0x%08X, size is %ld. The data is:\n", + SPI_FLASH_PATH, addr, size); + KPrintf("Offset (h) 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F\n"); + for (i = 0; i < size; i += 16) { + KPrintf("[%08X] ", addr + i); + /* dump hex */ + for (j = 0; j < 16; j++) { + if (i + j < size) { + KPrintf("%02X ", data[i + j]); + } else { + KPrintf(" "); + } + } + /* dump char for hex */ + for (j = 0; j < 16; j++) { + if (i + j < size) { + KPrintf("%c", FlashDataPrint(data[i + j]) ? data[i + j] : '.'); + } + } + KPrintf("\n"); + } + KPrintf("\n"); + } + } else { + KPrintf("SpiFlashRead alloc read buffer failed!\n"); + } + } + + return; +} +SHELL_EXPORT_CMD(SHELL_CMD_PERMISSION(0)|SHELL_CMD_TYPE(SHELL_TYPE_CMD_MAIN), + FlashRead, FlashRead, read data from spi flash device); + +void FlashWrite(int argc, char *argv[]) +{ + x_err_t ret = EOK; + x_size_t i, j = 0; + uint32 addr; + uint32 size; + uint8 data[16]; + + struct BusBlockWriteParam write_param; + memset(&write_param, 0, sizeof(struct BusBlockWriteParam)); + + memset(data, 0, 16); + + if (argc < 3) { + KPrintf("FlashWrite cmd format: FlashWrite addr data.\n"); + return; + } else { + addr = strtol(argv[1], NULL, 0); + size = argc - 2; + + write_param.buffer = data; + write_param.pos = addr; + write_param.size = size; + + if (data) { + for (i = 0; i < size; i++) { + data[i] = strtol(argv[2 + i], NULL, 0); + } + + ret = write(spi_flash_fd, &write_param, size); + if (EOK == ret) { + KPrintf("Write the %s flash data success. Start from 0x%08X, size is %ld.\n", + SPI_FLASH_PATH, addr, size); + KPrintf("Write data: "); + for (i = 0; i < size; i++) { + KPrintf("%d ", data[i]); + } + KPrintf(".\n"); + } + } else { + KPrintf("SpiFlashWrite alloc write buffer failed!\n"); + } + } +} +SHELL_EXPORT_CMD(SHELL_CMD_PERMISSION(0)|SHELL_CMD_TYPE(SHELL_TYPE_CMD_MAIN), + FlashWrite, FlashWrite, write data to spi flash device); diff --git a/APP_Framework/Applications/connection_app/Kconfig b/APP_Framework/Applications/connection_app/Kconfig new file mode 100755 index 0000000..338c7b3 --- /dev/null +++ b/APP_Framework/Applications/connection_app/Kconfig @@ -0,0 +1,7 @@ +menu "connection app" + + menuconfig APPLICATION_CONNECTION + bool "Using connection apps" + default n + +endmenu diff --git a/APP_Framework/Applications/connection_app/Makefile b/APP_Framework/Applications/connection_app/Makefile new file mode 100755 index 0000000..cb4403c --- /dev/null +++ b/APP_Framework/Applications/connection_app/Makefile @@ -0,0 +1,7 @@ +SRC_DIR := + +ifeq ($(CONFIG_RESOURCES_LWIP),y) + SRC_DIR += socket_demo +endif + +include $(KERNEL_ROOT)/compiler.mk \ No newline at end of file diff --git a/APP_Framework/Applications/connection_app/socket_demo/Makefile b/APP_Framework/Applications/connection_app/socket_demo/Makefile new file mode 100755 index 0000000..22a13f9 --- /dev/null +++ b/APP_Framework/Applications/connection_app/socket_demo/Makefile @@ -0,0 +1,3 @@ +SRC_FILES := lwip_tcp_socket_demo.c lwip_udp_socket_demo.c + +include $(KERNEL_ROOT)/compiler.mk diff --git a/APP_Framework/Applications/connection_app/socket_demo/lwip_tcp_socket_demo.c b/APP_Framework/Applications/connection_app/socket_demo/lwip_tcp_socket_demo.c new file mode 100755 index 0000000..18fcc9e --- /dev/null +++ b/APP_Framework/Applications/connection_app/socket_demo/lwip_tcp_socket_demo.c @@ -0,0 +1,186 @@ +/* +* Copyright (c) 2022 AIIT XUOS Lab +* XiUOS is licensed under Mulan PSL v2. +* You can use this software according to the terms and conditions of the Mulan PSL v2. +* You may obtain a copy of Mulan PSL v2 at: +* http://license.coscl.org.cn/MulanPSL2 +* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, +* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, +* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. +* See the Mulan PSL v2 for more details. +*/ + +/** +* @file lwip_tcp_socket_demo.c +* @brief TCP socket demo based on LwIP +* @version 1.0 +* @author AIIT XUOS Lab +* @date 2022-03-21 +*/ + +#include +#include "sys_arch.h" +#include +#include "lwip/sys.h" + +#define TCP_DEMO_BUF_SIZE 65535 + +char tcp_socket_ip[] = {192, 168, 250, 252}; +u16_t tcp_socket_port = LWIP_TARGET_PORT; + +/******************************************************************************/ + +static void TCPSocketRecvTask(void *arg) +{ + int fd = -1, clientfd; + int recv_len; + char *recv_buf; + struct sockaddr_in tcp_addr; + socklen_t addr_len; + + while(1) + { + recv_buf = (char *)malloc(TCP_DEMO_BUF_SIZE); + if (recv_buf == NULL) + { + lw_error("No memory\n"); + continue; + } + + fd = socket(AF_INET, SOCK_STREAM, 0); + if (fd < 0) + { + lw_error("Socket error\n"); + free(recv_buf); + continue; + } + + tcp_addr.sin_family = AF_INET; + tcp_addr.sin_addr.s_addr = INADDR_ANY; + tcp_addr.sin_port = htons(tcp_socket_port); + memset(&(tcp_addr.sin_zero), 0, sizeof(tcp_addr.sin_zero)); + + if (bind(fd, (struct sockaddr *)&tcp_addr, sizeof(struct sockaddr)) == -1) + { + lw_error("Unable to bind\n"); + closesocket(fd); + free(recv_buf); + continue; + } + + lw_print("tcp bind success, start to receive.\n"); + lw_notice("\n\nLocal Port:%d\n\n", tcp_socket_port); + + // setup socket fd as listening mode + if (listen(fd, 5) != 0 ) + { + lw_error("Unable to listen\n"); + closesocket(fd); + free(recv_buf); + continue; + } + + // accept client connection + clientfd = accept(fd, (struct sockaddr *)&tcp_addr, (socklen_t*)&addr_len); + lw_notice("client %s connected\n", inet_ntoa(tcp_addr.sin_addr)); + + while(1) + { + memset(recv_buf, 0, TCP_DEMO_BUF_SIZE); + recv_len = recvfrom(clientfd, recv_buf, TCP_DEMO_BUF_SIZE, 0, (struct sockaddr *)&tcp_addr, &addr_len); + if(recv_len > 0) + { + lw_notice("Receive from : %s\n", inet_ntoa(tcp_addr.sin_addr)); + lw_notice("Receive data : %d - %s\n\n", recv_len, recv_buf); + } + sendto(clientfd, recv_buf, recv_len, 0, (struct sockaddr*)&tcp_addr, addr_len); + } + } + + closesocket(fd); + free(recv_buf); +} + +void TCPSocketRecvTest(int argc, char *argv[]) +{ + int result = 0; + + if(argc >= 2) + { + lw_print("lw: [%s] target ip %s\n", __func__, argv[1]); + if(sscanf(argv[1], "%d.%d.%d.%d:%d", &tcp_socket_ip[0], &tcp_socket_ip[1], &tcp_socket_ip[2], &tcp_socket_ip[3], &tcp_socket_port) == EOK) + { + sscanf(argv[1], "%d.%d.%d.%d", &tcp_socket_ip[0], &tcp_socket_ip[1], &tcp_socket_ip[2], &tcp_socket_ip[3]); + } + } + + lwip_config_tcp(lwip_ipaddr, lwip_netmask, tcp_socket_ip); + sys_thread_new("TCPSocketRecvTask", TCPSocketRecvTask, NULL, LWIP_TASK_STACK_SIZE, LWIP_DEMO_TASK_PRIO); +} + +SHELL_EXPORT_CMD(SHELL_CMD_PERMISSION(0) | SHELL_CMD_TYPE(SHELL_TYPE_CMD_MAIN) | SHELL_CMD_PARAM_NUM(3), + TCPSocketRecv, TCPSocketRecvTest, TCP recv echo); + +static void TCPSocketSendTask(void *arg) +{ + int cnt = LWIP_DEMO_TIMES; + int fd = -1; + char send_msg[128]; + + lw_print("%s start\n", __func__); + + memset(send_msg, 0, sizeof(send_msg)); + fd = socket(AF_INET, SOCK_STREAM, 0); + if (fd < 0) + { + lw_print("Socket error\n"); + return; + } + + struct sockaddr_in tcp_sock; + tcp_sock.sin_family = AF_INET; + tcp_sock.sin_port = htons(tcp_socket_port); + tcp_sock.sin_addr.s_addr = PP_HTONL(LWIP_MAKEU32(tcp_socket_ip[0], tcp_socket_ip[1], tcp_socket_ip[2], tcp_socket_ip[3])); + memset(&(tcp_sock.sin_zero), 0, sizeof(tcp_sock.sin_zero)); + + if (connect(fd, (struct sockaddr *)&tcp_sock, sizeof(struct sockaddr))) + { + lw_print("Unable to connect\n"); + closesocket(fd); + return; + } + + lw_notice("\n\nTarget Port:%d\n\n", tcp_socket_port); + + while (cnt --) + { + lw_print("Lwip client is running.\n"); + snprintf(send_msg, sizeof(send_msg), "TCP test package times %d\r\n", cnt); + sendto(fd, send_msg, strlen(send_msg), 0, (struct sockaddr*)&tcp_sock, sizeof(struct sockaddr)); + lw_notice("Send tcp msg: %s ", send_msg); + MdelayKTask(1000); + } + + closesocket(fd); + return; +} + + +void TCPSocketSendTest(int argc, char *argv[]) +{ + if(argc >= 2) + { + lw_print("lw: [%s] target ip %s\n", __func__, argv[1]); + if(sscanf(argv[1], "%d.%d.%d.%d:%d", &tcp_socket_ip[0], &tcp_socket_ip[1], &tcp_socket_ip[2], &tcp_socket_ip[3], &tcp_socket_port) == EOK) + { + sscanf(argv[1], "%d.%d.%d.%d", &tcp_socket_ip[0], &tcp_socket_ip[1], &tcp_socket_ip[2], &tcp_socket_ip[3]); + } + } + + lwip_config_tcp(lwip_ipaddr, lwip_netmask, tcp_socket_ip); + sys_thread_new("TCP Socket Send", TCPSocketSendTask, NULL, LWIP_TASK_STACK_SIZE, LWIP_DEMO_TASK_PRIO); +} + +SHELL_EXPORT_CMD(SHELL_CMD_PERMISSION(0) | SHELL_CMD_TYPE(SHELL_TYPE_CMD_MAIN) | SHELL_CMD_PARAM_NUM(0), + TCPSocketSend, TCPSocketSendTest, TCP send demo); + diff --git a/APP_Framework/Applications/connection_app/socket_demo/lwip_udp_socket_demo.c b/APP_Framework/Applications/connection_app/socket_demo/lwip_udp_socket_demo.c new file mode 100755 index 0000000..fcc5be0 --- /dev/null +++ b/APP_Framework/Applications/connection_app/socket_demo/lwip_udp_socket_demo.c @@ -0,0 +1,167 @@ +/* +* Copyright (c) 2022 AIIT XUOS Lab +* XiUOS is licensed under Mulan PSL v2. +* You can use this software according to the terms and conditions of the Mulan PSL v2. +* You may obtain a copy of Mulan PSL v2 at: +* http://license.coscl.org.cn/MulanPSL2 +* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, +* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, +* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. +* See the Mulan PSL v2 for more details. +*/ + +/** +* @file lwip_udp_socket_demo.c +* @brief UDP demo based on LwIP +* @version 1.0 +* @author AIIT XUOS Lab +* @date 2022-03-21 +*/ +#include +#include "sys_arch.h" +#include "lwip/sockets.h" + +#define UDP_BUF_SIZE 65536 + +char udp_socket_ip[] = {192, 168, 250, 252}; +u16_t udp_socket_port = LWIP_LOCAL_PORT; + +/*****************************************************************************/ + +static void UdpSocketRecvTask(void *arg) +{ + int fd = -1; + char *recv_buf; + struct sockaddr_in udp_addr, server_addr; + int recv_len; + socklen_t addr_len; + + while(1) + { + recv_buf = (char *)malloc(UDP_BUF_SIZE); + if(recv_buf == NULL) + { + lw_error("No memory\n"); + continue; + } + + fd = socket(AF_INET, SOCK_DGRAM, 0); + if(fd < 0) + { + lw_error("Socket error\n"); + free(recv_buf); + continue; + } + + udp_addr.sin_family = AF_INET; + udp_addr.sin_addr.s_addr = INADDR_ANY; + udp_addr.sin_port = htons(udp_socket_port); + memset(&(udp_addr.sin_zero), 0, sizeof(udp_addr.sin_zero)); + + if(bind(fd, (struct sockaddr *)&udp_addr, sizeof(struct sockaddr)) == -1) + { + lw_error("Unable to bind\n"); + closesocket(fd); + free(recv_buf); + continue; + } + + lw_notice("UDP bind sucess, start to receive.\n"); + lw_notice("\n\nLocal Port:%d\n\n", udp_socket_port); + + while(1) + { + memset(recv_buf, 0, UDP_BUF_SIZE); + recv_len = recvfrom(fd, recv_buf, UDP_BUF_SIZE, 0, (struct sockaddr *)&server_addr, &addr_len); + if(recv_len > 0) + { + lw_notice("Receive from : %s\n", inet_ntoa(server_addr.sin_addr)); + lw_notice("Receive data : %s\n\n", recv_buf); + } + sendto(fd, recv_buf, recv_len, 0, (struct sockaddr*)&server_addr, addr_len); + } + + closesocket(fd); + free(recv_buf); + } +} + +void UdpSocketRecvTest(int argc, char *argv[]) +{ + if(argc >= 2) + { + lw_notice("lw: [%s] target ip %s\n", __func__, argv[1]); + if(sscanf(argv[1], "%d.%d.%d.%d:%d", &udp_socket_ip[0], &udp_socket_ip[1], &udp_socket_ip[2], &udp_socket_ip[3], &udp_socket_port) == EOK) + { + sscanf(argv[1], "%d.%d.%d.%d", &udp_socket_ip[0], &udp_socket_ip[1], &udp_socket_ip[2], &udp_socket_ip[3]); + } + } + + lwip_config_tcp(lwip_ipaddr, lwip_netmask, udp_socket_ip); + sys_thread_new("UdpSocketRecvTask", UdpSocketRecvTask, NULL, LWIP_TASK_STACK_SIZE, LWIP_DEMO_TASK_PRIO); +} + +SHELL_EXPORT_CMD(SHELL_CMD_PERMISSION(0) | SHELL_CMD_TYPE(SHELL_TYPE_CMD_MAIN) | SHELL_CMD_PARAM_NUM(3), + UDPSocketRecv, UdpSocketRecvTest, UDP Receive DEMO); + +static void UdpSocketSendTask(void *arg) +{ + int cnt = LWIP_DEMO_TIMES; + char send_str[128]; + int fd = -1; + + memset(send_str, 0, sizeof(send_str)); + + fd = socket(AF_INET, SOCK_DGRAM, 0); + if(fd < 0) + { + lw_error("Socket error\n"); + return; + } + + struct sockaddr_in udp_sock; + udp_sock.sin_family = AF_INET; + udp_sock.sin_port = htons(udp_socket_port); + udp_sock.sin_addr.s_addr = PP_HTONL(LWIP_MAKEU32(udp_socket_ip[0], udp_socket_ip[1], udp_socket_ip[2], udp_socket_ip[3])); + memset(&(udp_sock.sin_zero), 0, sizeof(udp_sock.sin_zero)); + + if(connect(fd, (struct sockaddr *)&udp_sock, sizeof(struct sockaddr))) + { + lw_error("Unable to connect\n"); + closesocket(fd); + return; + } + + lw_print("UDP connect success, start to send.\n"); + lw_notice("\n\nTarget Port:%d\n\n", udp_sock.sin_port); + + while (cnt --) + { + snprintf(send_str, sizeof(send_str), "UDP test package times %d\r\n", cnt); + sendto(fd, send_str, strlen(send_str), 0, (struct sockaddr*)&udp_sock, sizeof(struct sockaddr)); + lw_notice("Send UDP msg: %s ", send_str); + MdelayKTask(1000); + } + + closesocket(fd); + return; +} + +void UdpSocketSendTest(int argc, char *argv[]) +{ + if(argc >= 2) + { + lw_notice("lw: [%s] target ip %s\n", __func__, argv[1]); + if(sscanf(argv[1], "%d.%d.%d.%d:%d", &udp_socket_ip[0], &udp_socket_ip[1], &udp_socket_ip[2], &udp_socket_ip[3], &udp_socket_port) == EOK) + { + sscanf(argv[1], "%d.%d.%d.%d", &udp_socket_ip[0], &udp_socket_ip[1], &udp_socket_ip[2], &udp_socket_ip[3]); + } + } + + lwip_config_tcp(lwip_ipaddr, lwip_netmask, udp_socket_ip); + sys_thread_new("UdpSocketSendTask", UdpSocketSendTask, NULL, LWIP_TASK_STACK_SIZE, LWIP_DEMO_TASK_PRIO); +} + +SHELL_EXPORT_CMD(SHELL_CMD_PERMISSION(0) | SHELL_CMD_TYPE(SHELL_TYPE_CMD_MAIN) | SHELL_CMD_PARAM_NUM(3), + UDPSocketSend, UdpSocketSendTest, UDP send echo); + diff --git a/APP_Framework/Applications/control_app/Kconfig b/APP_Framework/Applications/control_app/Kconfig new file mode 100755 index 0000000..02ddbf1 --- /dev/null +++ b/APP_Framework/Applications/control_app/Kconfig @@ -0,0 +1,9 @@ +menu "control app" + + menuconfig APPLICATION_CONTROL + bool "Using control apps" + default n + depends on SUPPORT_CONTROL_FRAMEWORK + +endmenu + diff --git a/APP_Framework/Applications/control_app/Makefile b/APP_Framework/Applications/control_app/Makefile new file mode 100755 index 0000000..568e8b9 --- /dev/null +++ b/APP_Framework/Applications/control_app/Makefile @@ -0,0 +1,11 @@ +SRC_DIR := + +ifeq ($(CONFIG_RESOURCES_LWIP),y) + +ifeq ($(CONFIG_USING_CONTROL_PLC_OPCUA), y) + SRC_DIR += opcua_demo plc_demo +endif + +endif + +include $(KERNEL_ROOT)/compiler.mk diff --git a/APP_Framework/Applications/control_app/opcua_demo/Makefile b/APP_Framework/Applications/control_app/opcua_demo/Makefile new file mode 100755 index 0000000..b595ed0 --- /dev/null +++ b/APP_Framework/Applications/control_app/opcua_demo/Makefile @@ -0,0 +1,3 @@ +SRC_FILES :=opcua_demo.c + +include $(KERNEL_ROOT)/compiler.mk diff --git a/APP_Framework/Applications/control_app/opcua_demo/README.md b/APP_Framework/Applications/control_app/opcua_demo/README.md new file mode 100755 index 0000000..9b809af --- /dev/null +++ b/APP_Framework/Applications/control_app/opcua_demo/README.md @@ -0,0 +1,16 @@ +# OPCUA DEMO README + +## 文件说明 + +用于OPCUA 相关测试命令演示，需要开启LWIP和OPCUA协议. + +### 命令行 + +UaConnect [IP] + +用于测试与OPCUA服务器连接，连接成功应显示OK + +UaObject [IP] + +用于显示对应的OPCUA设备的节点信息 + diff --git a/APP_Framework/Applications/control_app/opcua_demo/opcua_demo.c b/APP_Framework/Applications/control_app/opcua_demo/opcua_demo.c new file mode 100755 index 0000000..6cabf18 --- /dev/null +++ b/APP_Framework/Applications/control_app/opcua_demo/opcua_demo.c @@ -0,0 +1,266 @@ +/* + * Copyright (c) 2021 AIIT XUOS Lab + * XiUOS is licensed under Mulan PSL v2. + * You can use this software according to the terms and conditions of the Mulan PSL v2. + * You may obtain a copy of Mulan PSL v2 at: + * http://license.coscl.org.cn/MulanPSL2 + * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, + * EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, + * MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. + * See the Mulan PSL v2 for more details. + */ + +/** + * @file opcua_demo.c + * @brief Demo for OpcUa function + * @version 1.0 + * @author AIIT XUOS Lab + * @date 2021.11.11 + */ + +#include +#include +#include "board.h" +#include "open62541.h" +#include "ua_api.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +#define UA_URL_SIZE 100 +#define UA_STACK_SIZE 4096 +#define UA_TASK_PRIO 15 + +/******************************************************************************* + * Prototypes + ******************************************************************************/ + +/******************************************************************************* + * Variables + ******************************************************************************/ +// to count test +static int test_cnt = 0; +static int fail_cnt = 0; // count failure times + +char test_ua_ip[] = {192, 168, 250, 2}; + +/******************************************************************************* + * Code + ******************************************************************************/ + +static void UaConnectTestTask(void* arg) +{ + struct netif net; + UA_StatusCode ret; + char url[UA_URL_SIZE]; + memset(url, 0, sizeof(url)); + + UA_Client* client = UA_Client_new(); + + if(client == NULL) + { + ua_error("ua: [%s] tcp client null\n", __func__); + return; + } + + UA_ClientConfig* config = UA_Client_getConfig(client); + + UA_ClientConfig_setDefault(config); + + snprintf(url, sizeof(url), "opc.tcp://%d.%d.%d.%d:4840", + test_ua_ip[0], test_ua_ip[1], test_ua_ip[2], test_ua_ip[3]); + + ua_notice("ua connect cnt %d fail %d\n", test_cnt++, fail_cnt ++); + ua_notice("ua connect uri: %.*s\n", strlen(url), url); + + ret = UA_Client_connect(client, url); + + if(ret != UA_STATUSCODE_GOOD) + { + ua_error("ua: [%s] connected failed %x\n", __func__, ret); + UA_Client_delete(client); + fail_cnt++; + return; + } + + ua_notice("ua connected ok!\n"); + UA_Client_delete(client); +} + +static void UaConnectTest(int argc, char *argv[]) +{ + if(argc == 2) + { + if(isdigit(argv[1][0])) + { + if(sscanf(argv[1], "%d.%d.%d.%d", &test_ua_ip[0], &test_ua_ip[1], &test_ua_ip[2], &test_ua_ip[3]) == EOF) + { + lw_notice("input wrong ip\n"); + return; + } + } + } + + lwip_config_tcp(lwip_ipaddr, lwip_netmask, test_ua_ip); + sys_thread_new("ua test", UaConnectTestTask, NULL, UA_STACK_SIZE, UA_TASK_PRIO); +} + +SHELL_EXPORT_CMD(SHELL_CMD_PERMISSION(0) | SHELL_CMD_TYPE(SHELL_TYPE_CMD_MAIN) | SHELL_CMD_PARAM_NUM(0), + UaConnect, UaConnectTest, Test Opc UA connection); + +void UaBrowserObjectsTestTask(void* param) +{ + ua_notice("ua: [%s] start %d ...\n", __func__, test_cnt++); + + UA_Client* client = UA_Client_new(); + + if(client == NULL) + { + ua_error("ua: [%s] tcp client NULL\n", __func__); + return; + } + + UA_ClientConfig* config = UA_Client_getConfig(client); + UA_ClientConfig_setDefault(config); + UA_StatusCode ret = UA_Client_connect(client, opc_server_url); + + if(ret != UA_STATUSCODE_GOOD) + { + ua_error("ua: [%s] connect failed %#x\n", __func__, ret); + UA_Client_delete(client); + return; + } + + ua_notice("--- start read time ---\n", __func__); + UaGetServerTime(client); + + ua_notice("--- get server info ---\n", __func__); + UaTestBrowserObjects(client); + + /* Clean up */ + UA_Client_delete(client); /* Disconnects the client internally */ +} + +static void* UaBrowserObjectsTest(int argc, char* argv[]) +{ + if(argc == 2) + { + if(isdigit(argv[1][0])) + { + if(sscanf(argv[1], "%d.%d.%d.%d", &test_ua_ip[0], &test_ua_ip[1], &test_ua_ip[2], &test_ua_ip[3]) == EOF) + { + lw_notice("input wrong ip\n"); + return NULL; + } + } + } + + lwip_config_tcp(lwip_ipaddr, lwip_netmask, test_ua_ip); + sys_thread_new("ua object", UaBrowserObjectsTestTask, NULL, UA_STACK_SIZE, UA_TASK_PRIO); + return NULL; +} + +SHELL_EXPORT_CMD(SHELL_CMD_PERMISSION(0) | SHELL_CMD_TYPE(SHELL_TYPE_CMD_MAIN) | SHELL_CMD_PARAM_NUM(3), + UaObject, UaBrowserObjectsTest, UaObject [IP]); + +void UaGetInfoTestTask(void* param) +{ + UA_Client* client = UA_Client_new(); + ua_notice("--- Get OPUCA objects ---\n", __func__); + + if(client == NULL) + { + ua_error("ua: [%s] tcp client null\n", __func__); + return; + } + + UA_ClientConfig* config = UA_Client_getConfig(client); + UA_ClientConfig_setDefault(config); + UA_StatusCode ret = UA_Client_connect(client, opc_server_url); + + if(ret != UA_STATUSCODE_GOOD) + { + ua_error("ua: [%s] connect failed %#x\n", __func__, ret); + UA_Client_delete(client); + return; + } + + ua_notice("--- interactive server ---\n", __func__); + UaTestInteractServer(client); + + UA_Client_delete(client); /* Disconnects the client internally */ +} + +void* UaGetInfoTest(int argc, char* argv[]) +{ + if(argc == 2) + { + if(isdigit(argv[1][0])) + { + if(sscanf(argv[1], "%d.%d.%d.%d", &test_ua_ip[0], &test_ua_ip[1], &test_ua_ip[2], &test_ua_ip[3]) == EOF) + { + lw_notice("input wrong ip\n"); + return NULL; + } + } + } + + lwip_config_tcp(lwip_ipaddr, lwip_netmask, test_ua_ip); + sys_thread_new("ua info", UaGetInfoTestTask, NULL, UA_STACK_SIZE, UA_TASK_PRIO); + return NULL; +} + +SHELL_EXPORT_CMD(SHELL_CMD_PERMISSION(0) | SHELL_CMD_TYPE(SHELL_TYPE_CMD_MAIN) | SHELL_CMD_PARAM_NUM(3), + UaInfo, UaGetInfoTest, UaInfo [IP]); + +void UaAddNodesTask(void* param) +{ + UA_Client* client = UA_Client_new(); + ua_notice("ua: [%s] start ...\n", __func__); + + if(client == NULL) + { + ua_error("ua: [%s] client null\n", __func__); + return; + } + + UA_ClientConfig* config = UA_Client_getConfig(client); + UA_ClientConfig_setDefault(config); + UA_StatusCode ret = UA_Client_connect(client, opc_server_url); + + if(ret != UA_STATUSCODE_GOOD) + { + ua_print("ua: [%s] connect failed %#x\n", __func__, ret); + UA_Client_delete(client); + return; + } + + ua_notice("--- add nodes ---\n", __func__); + UaAddNodes(client); + + UA_Client_delete(client); /* Disconnects the client internally */ +} + +void* UaAddNodesTest(int argc, char* argv[]) +{ + if(argc == 2) + { + if(isdigit(argv[1][0])) + { + if(sscanf(argv[1], "%d.%d.%d.%d", &test_ua_ip[0], &test_ua_ip[1], &test_ua_ip[2], &test_ua_ip[3]) == EOF) + { + lw_notice("input wrong ip\n"); + return NULL; + } + } + } + + lwip_config_tcp(lwip_ipaddr, lwip_netmask, test_ua_ip); + sys_thread_new("ua add nodes", UaAddNodesTask, NULL, UA_STACK_SIZE, UA_TASK_PRIO); + return NULL; +} + +SHELL_EXPORT_CMD(SHELL_CMD_PERMISSION(0) | SHELL_CMD_TYPE(SHELL_TYPE_CMD_MAIN) | SHELL_CMD_PARAM_NUM(3), + UaAdd, UaAddNodesTest, UA Add Nodes); + diff --git a/APP_Framework/Applications/control_app/plc_demo/Makefile b/APP_Framework/Applications/control_app/plc_demo/Makefile new file mode 100755 index 0000000..e732c37 --- /dev/null +++ b/APP_Framework/Applications/control_app/plc_demo/Makefile @@ -0,0 +1,3 @@ +SRC_FILES := plc_show_demo.c plc_control_demo.c + +include $(KERNEL_ROOT)/compiler.mk diff --git a/APP_Framework/Applications/control_app/plc_demo/README.md b/APP_Framework/Applications/control_app/plc_demo/README.md new file mode 100755 index 0000000..1d361b9 --- /dev/null +++ b/APP_Framework/Applications/control_app/plc_demo/README.md @@ -0,0 +1,48 @@ +# PLC DEMO README + +## 文件说明 + +用于PLC设备相关测试命令演示，目前支持OPCUA协议对PLC进行远程控制，该命令基于LWIP和OPCUA，需要开启相关开关。 + +多个PLC设备可以组成一个channel，用于一条相关业务线控制。 + +### 命令行 + +ShowChannel + +显示注册到channel上的PLC设备，范例如下： + + ch_type ch_name drv_name dev_name cnt +----------------------------------------------------------------- + PLC_Channel PLC OPCUA PLC Demo 4 1 + PLC Demo 3 2 + PLC Demo 2 3 + PLC Demo 1 4 + PLC Demo 0 5 + +ShowPLC + +用于显示PLC，范例如下： + + device vendor model product id +----------------------------------------------------------------- + PLC Demo 4 B&R X20 X20 CP1381 5 + PLC Demo 3 B&R X20 X20 CP1586 4 + PLC Demo 2 SIEMSNS S7-200 CPU SR60 3 + PLC Demo 1 SIEMENS S7-1200 CPU 1215C 2 + PLC Demo 0 SIEMENS S7-1500 CPU 1512SP-1PN 1 + + PlcRead [NodeID] + + 用于读取PLC节点信息 + + - [NodeID]: 如n4,1, 其中4代表namespace，1代表节点号 + + + PlcWrite + + 用于写入PLC节点数值 + + - [NodeID]: 如n4,1, 其中4代表namespace，1代表节点号 + + - [value]: 为写入数值，目前支持bool类型，和int类型。bool型应为0b(代表false), 1b(代表true) diff --git a/APP_Framework/Applications/control_app/plc_demo/plc_control_demo.c b/APP_Framework/Applications/control_app/plc_demo/plc_control_demo.c new file mode 100755 index 0000000..fed4063 --- /dev/null +++ b/APP_Framework/Applications/control_app/plc_demo/plc_control_demo.c @@ -0,0 +1,354 @@ +/* + * Copyright (c) 2022 AIIT XUOS Lab + * XiUOS is licensed under Mulan PSL v2. + * You can use this software according to the terms and conditions of the Mulan PSL v2. + * You may obtain a copy of Mulan PSL v2 at: + * http://license.coscl.org.cn/MulanPSL2 + * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, + * EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, + * MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. + * See the Mulan PSL v2 for more details. + */ + +/** + * @file plc_control_demo.c + * @brief Demo for PLC control + * @version 1.0 + * @author AIIT XUOS Lab + * @date 2022.2.22 + */ + +#include "transform.h" +#include "open62541.h" +#include "ua_api.h" +#include "sys_arch.h" +#include "plc_demo.h" + +#define PLC_NS_FORMAT "n%d,%s" + +struct PlcChannel plc_demo_ch; +struct PlcDriver plc_demo_drv; +struct PlcDevice plc_demo_dev; + +int plc_test_flag = 0; + +PlcCtrlParamType plc_ctrl_param; + +UA_NodeId test_nodeid = {4, UA_NODEIDTYPE_NUMERIC, 5}; + +/******************************************************************************/ + +void PlcDelay(int sec) +{ + volatile uint32_t i = 0; + for (i = 0; i < 100000000 * sec; ++i) + { + __asm("NOP"); /* delay */ + } +} + +// get NodeId from str +void PlcGetTestNodeId(char *str, UA_NodeId *id) +{ + static char node_str[UA_NODE_LEN]; + memset(node_str, 0, sizeof(node_str)); + + plc_print("plc: arg %s\n", str); + + if(sscanf(str, PLC_NS_FORMAT, &id->namespaceIndex, node_str) != EOF) + { + if(isdigit(node_str[0])) + { + id->identifierType = UA_NODEIDTYPE_NUMERIC; + id->identifier.numeric = atoi(node_str); + plc_print("ns %d num %d\n", id->namespaceIndex, id->identifier.numeric); + } + else + { + id->identifierType = UA_NODEIDTYPE_STRING; + id->identifier.string.length = strlen(node_str); + id->identifier.string.data = node_str; + plc_print("ns %d str %s\n", id->namespaceIndex, id->identifier.string.data); + } + } +} + +void PlcDemoChannelDrvInit(void) +{ + static uint8_t init_flag = 0; + if(init_flag) + return; + init_flag = 1; + + lwip_config_tcp(lwip_ipaddr, lwip_netmask, test_ua_ip); + PlcChannelInit(&plc_demo_ch, PLC_CH_NAME); + if(PlcDriverInit(&plc_demo_drv, PLC_DRV_NAME) == EOK) + { + PlcDriverAttachToChannel(PLC_DRV_NAME, PLC_CH_NAME); + } + memset(&plc_demo_dev, 0, sizeof(plc_demo_dev)); +} + +static void PlcGetDemoDev(PlcDeviceType *dev, UA_NodeId *id) +{ + // register plc device + dev->state = CHDEV_INIT; + strcpy(dev->name, "UA Demo"); + dev->info.product = "CPU 1215C"; + dev->info.vendor = "SIEMENS"; + dev->info.model = "S7-1200"; + dev->info.id = 123; + dev->net = PLC_IND_ENET_OPCUA; + + // register UA parameter + if(!dev->priv_data) + { + dev->priv_data = (UaParamType*)malloc(sizeof(UaParamType)); + } + UaParamType* ua_ptr = dev->priv_data; + memset(ua_ptr, 0, sizeof(UaParamType)); + strcpy(ua_ptr->ua_remote_ip, opc_server_url); + ua_ptr->act = UA_ACT_ATTR; + memcpy(&ua_ptr->ua_id, id, sizeof(*id)); +} + +static void PlcCtrlDemoInit(void) +{ + static uint8_t init_flag = 0; + + PlcDemoChannelDrvInit(); + + // register plc device + PlcGetDemoDev(&plc_demo_dev, &test_nodeid); + + if(init_flag) + { + return; + } + init_flag = 1; + + if(PlcDevRegister(&plc_demo_dev, NULL, plc_demo_dev.name) != EOK) + { + return; + } + PlcDeviceAttachToChannel(plc_demo_dev.name, PLC_CH_NAME); +} + +void PlcReadUATask(void* arg) +{ + int ret = 0; + struct PlcOps* ops = NULL; + char buf[PLC_BUF_SIZE]; + memset(buf, 0, sizeof(buf)); + PlcCtrlDemoInit(); + ops = plc_demo_dev.ops; + ret = ops->open(&plc_demo_dev); + + if(EOK != ret) + { + plc_print("plc: [%s] open failed %#x\n", __func__, ret); + return; + } + + ret = ops->read(&plc_demo_dev, buf, PLC_BUF_SIZE); + + if(EOK != ret) + { + plc_print("plc: [%s] read failed %x\n", __func__, ret); + } + + ops->close(&plc_demo_dev); +} + +void PlcReadTestShell(int argc, char* argv[]) +{ + static char node_str[UA_NODE_LEN]; + memset(node_str, 0, sizeof(node_str)); + + if(argc > 1) + { + PlcGetTestNodeId(argv[1], &test_nodeid); + } + + sys_thread_new("plc read", PlcReadUATask, NULL, PLC_STACK_SIZE, PLC_TASK_PRIO); +} + +SHELL_EXPORT_CMD(SHELL_CMD_PERMISSION(0) | SHELL_CMD_TYPE(SHELL_TYPE_CMD_MAIN) | SHELL_CMD_PARAM_NUM(3), + PlcRead, PlcReadTestShell, Read PLC); + +void PlcWriteUATask(void* arg) +{ + int ret = 0; + struct PlcOps* ops = NULL; + char buf[PLC_BUF_SIZE]; + memset(buf, 0, sizeof(buf)); + + PlcCtrlDemoInit(); + ops = plc_demo_dev.ops; + ret = ops->open(&plc_demo_dev); + + if(EOK != ret) + { + plc_print("plc: [%s] open failed %#x\n", __func__, ret); + return; + } + + ret = ops->write(&plc_demo_dev, arg, PLC_BUF_SIZE); + + if(EOK != ret) + { + plc_print("plc: [%s] write failed\n", __func__); + } + + ops->close(&plc_demo_dev); +} + +void PlcWriteTestShell(int argc, char* argv[]) +{ + static char node_str[UA_NODE_LEN]; + static char val_param[UA_NODE_LEN]; + memset(node_str, 0, sizeof(node_str)); + memset(val_param, 0, sizeof(val_param)); + + if(argc > 1) + { + PlcGetTestNodeId(argv[1], &test_nodeid); + } + + if(argc > 2) + { + strcpy(val_param, argv[2]); + plc_print("write value %s\n", val_param); + } + + sys_thread_new("plc write", PlcWriteUATask, val_param, PLC_STACK_SIZE, PLC_TASK_PRIO); +} + +SHELL_EXPORT_CMD(SHELL_CMD_PERMISSION(0) | SHELL_CMD_TYPE(SHELL_TYPE_CMD_MAIN) | SHELL_CMD_PARAM_NUM(3), + PlcWrite, PlcWriteTestShell, Read PLC); + +// test motor +// clear parameter +// PlcWrite n4,2 0b +// PlcWrite n4,3 0b +// PlcWrite n4,4 0b +// PlcWrite n4,5 0b +// +// enable +// PlcWrite n4,2 1b +// +// set rotate speed +// PlcWrite n4,3 50 +// +// positive turn +// PlcWrite n4,4 1b +// +// reversal turn +// PlcWrite n4,5 1b + +static int plc_test_speed = 50; +static int plc_test_dir = 1; // direction positive: 1 reversal: 0 + +void PlcMotorTestTask(void* arg) +{ + //support node id + char *test_nodeid[] = {"n4,2", "n4,3", "n4,4", "n4,5", "n4,7"}; + // enable -> speed -> positive dir or inversal dir -> stop -> enable + char test_sort[] = {0, 4, 2, 1, 0}; + char test_cmd[][4] = {"1b", "50", "1b", "1b", "0b"}; + char *test_notice[] = {"Enable Motor", "Set Speed", "Set Forward", "Set Reverse", "Stop Motor"}; + + int ret = 0; + struct PlcOps* ops = NULL; + char buf[PLC_BUF_SIZE]; + memset(buf, 0, sizeof(buf)); + + PlcCtrlDemoInit(); + ops = plc_demo_dev.ops; + ret = ops->open(&plc_demo_dev); + + if(EOK != ret) + { + plc_print("plc: [%s] open failed %#x\n", __func__, ret); + return; + } + + UaParamType* ua_ptr = plc_demo_dev.priv_data; + + // initialize step + for(int i = 0; i < 5; i++) + { + plc_print("###\n### Clear %s\n###\n", test_notice[i]); + PlcGetTestNodeId(test_nodeid[i], &ua_ptr->ua_id); + ret = ops->write(&plc_demo_dev, "0b", PLC_BUF_SIZE); + if(EOK != ret) + { + plc_print("plc: [%s] %d write failed\n", __func__, __LINE__); + } + PlcDelay(1); + } + + if(plc_test_speed != 50) + { + snprintf(test_cmd[1], 4, "%d", plc_test_speed); + } + + if(plc_test_dir == 0) // if not postive, next running + test_sort[2] = 3; + + for(int i = 0; i < sizeof(test_sort)/sizeof(test_sort[0]); i++) + { + PlcGetTestNodeId(test_nodeid[test_sort[i]], &ua_ptr->ua_id); + plc_print("###\n### %s\n###\n", test_notice[i]); + ret = ops->write(&plc_demo_dev, test_cmd[i], PLC_BUF_SIZE); + if(EOK != ret) + { + plc_print("plc: [%s] %d write failed\n", __func__, __LINE__); + } + PlcDelay(1); + if(i == 2) // postive + { + PlcDelay(10); + } + } + ops->close(&plc_demo_dev); + plc_test_flag = 0; +} + +// get parameter from +void PlcGetMotorParam(char *str) +{ + static char node_str[UA_NODE_LEN]; + memset(node_str, 0, sizeof(node_str)); + + plc_print("plc: arg %s\n", str); + + sscanf(str, "speed=%d", &plc_test_speed); + sscanf(str, "dir=%d", &plc_test_dir); + plc_print("speed is %d\n", plc_test_speed); + plc_print("dir is %d\n", plc_test_dir); +} + +void PlcMotorTestShell(int argc, char* argv[]) +{ + if(plc_test_flag) + { + plc_print("PLC Motor testing!\n"); + return; + } + plc_test_flag = 1; + + if(argc > 1) + { + for(int i = 0; i < argc; i++) + { + PlcGetMotorParam(argv[i]); + } + } + + sys_thread_new("plc motor", PlcMotorTestTask, NULL, PLC_STACK_SIZE, PLC_TASK_PRIO); +} + +SHELL_EXPORT_CMD(SHELL_CMD_PERMISSION(0) | SHELL_CMD_TYPE(SHELL_TYPE_CMD_MAIN) | SHELL_CMD_PARAM_NUM(3), + PlcMotorTest, PlcMotorTestShell, Run motor); + diff --git a/APP_Framework/Applications/control_app/plc_demo/plc_demo.h b/APP_Framework/Applications/control_app/plc_demo/plc_demo.h new file mode 100755 index 0000000..1209693 --- /dev/null +++ b/APP_Framework/Applications/control_app/plc_demo/plc_demo.h @@ -0,0 +1,41 @@ +/* + * Copyright (c) 2022 AIIT XUOS Lab + * XiUOS is licensed under Mulan PSL v2. + * You can use this software according to the terms and conditions of the Mulan PSL v2. + * You may obtain a copy of Mulan PSL v2 at: + * http://license.coscl.org.cn/MulanPSL2 + * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, + * EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, + * MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. + * See the Mulan PSL v2 for more details. + */ + +/** + * @file plc_show_demo.c + * @brief Demo for PLC information show + * @version 1.0 + * @author AIIT XUOS Lab + * @date 2022.02.24 + */ + +#ifndef __PLC_DEMO_H_ +#define __PLC_DEMO_H_ + +#include "plc_channel.h" +#include "plc_device.h" + +#define PLC_CH_NAME "PLC" +#define PLC_DRV_NAME "OPCUA" + +#define PLC_BUF_SIZE 128 + +#define PLC_STACK_SIZE 4096 +#define PLC_TASK_PRIO 15 + +extern struct PlcChannel plc_demo_ch; +extern struct PlcDriver plc_demo_drv; +extern struct PlcDevice plc_demo_dev; + +void PlcDemoChannelDrvInit(void); + +#endif diff --git a/APP_Framework/Applications/control_app/plc_demo/plc_show_demo.c b/APP_Framework/Applications/control_app/plc_demo/plc_show_demo.c new file mode 100755 index 0000000..71a15a2 --- /dev/null +++ b/APP_Framework/Applications/control_app/plc_demo/plc_show_demo.c @@ -0,0 +1,257 @@ +/* + * Copyright (c) 2022 AIIT XUOS Lab + * XiUOS is licensed under Mulan PSL v2. + * You can use this software according to the terms and conditions of the Mulan PSL v2. + * You may obtain a copy of Mulan PSL v2 at: + * http://license.coscl.org.cn/MulanPSL2 + * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, + * EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, + * MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. + * See the Mulan PSL v2 for more details. + */ + +/** + * @file plc_show_demo.c + * @brief Demo for PLC information show + * @version 1.0 + * @author AIIT XUOS Lab + * @date 2022.02.24 + */ + +#include "transform.h" +#include "list.h" + +#include "open62541.h" +#include "ua_api.h" +#include "sys_arch.h" +#include "plc_demo.h" + + +#define PLC_DEMO_NUM 5 + +struct PlcDevice plc_demo_array[PLC_DEMO_NUM]; + +typedef struct PlcShowParam +{ + int id; + char* vector; + char* model; + char* product; +} PlcShowParamType; + +PlcShowParamType plc_demo_param[PLC_NAME_SIZE] = +{ + {1, "SIEMENS", "S7-1500", "CPU 1512SP-1PN"}, + {2, "SIEMENS", "S7-1200", "CPU 1215C"}, + {3, "SIEMSNS", "S7-200", "CPU SR60"}, + {4, "B&R", "X20", "X20 CP1586"}, + {5, "B&R", "X20", "X20 CP1381"} +}; + +static char* const channel_type_str[] = +{ + "PLC_Channel", + "Unknown" +}; + +extern DoublelistType plcdev_list; +extern DoublelistType ch_linklist; + +/**********************************************************************************************************************/ + +void PlcShowTitle(const char* item_array[]) +{ + int i = 0, max_len = 65; + KPrintf(" %-15s%-15s%-15s%-15s%-20s\n", item_array[0], item_array[1], item_array[2], item_array[3], item_array[4]); + + while(i < max_len) + { + i++; + + if(max_len == i) + { + KPrintf("-\n"); + } + else + { + KPrintf("-"); + } + } +} + +static ChDrvType ShowChannelFindDriver(struct Channel* ch) +{ + struct ChDrv* driver = NONE; + DoublelistType* node = NONE; + DoublelistType* head = &ch->ch_drvlink; + + for(node = head->node_next; node != head; node = node->node_next) + { + driver = DOUBLE_LIST_ENTRY(node, struct ChDrv, driver_link); + return driver; + } + + return NONE; +} + +static void PlcShowDemoInit(void) +{ + static uint8_t init_flag = 0; + int i; + PlcDemoChannelDrvInit(); + + for(i = 0; i < PLC_DEMO_NUM; i++) + { + // register plc device + plc_demo_array[i].state = CHDEV_INIT; + snprintf(plc_demo_array[i].name, PLC_NAME_SIZE, "PLC Demo %d", i); + plc_demo_array[i].info.vendor = plc_demo_param[i].vector; + plc_demo_array[i].info.model = plc_demo_param[i].model; + plc_demo_array[i].info.id = plc_demo_param[i].id; + plc_demo_array[i].info.product = plc_demo_param[i].product; + plc_demo_array[i].net = PLC_IND_ENET_OPCUA; + } + + if(init_flag) + return; + init_flag = 1; + + for(i = 0; i < PLC_DEMO_NUM; i++) + { + if(PlcDevRegister(&plc_demo_array[i], NULL, plc_demo_array[i].name) == EOK) + { + PlcDeviceAttachToChannel(plc_demo_array[i].name, PLC_CH_NAME); + } + } +} + +void PlcShowChannel(void) +{ + ChannelType ch; + ChDrvType driver; + ChDevType device; + int dev_cnt; + DoublelistType* ch_node = NONE; + DoublelistType* ch_head = &ch_linklist; + const char* item_array[] = {"ch_type", "ch_name", "drv_name", "dev_name", "cnt"}; + PlcShowDemoInit(); + PlcShowTitle(item_array); + ch_node = ch_head->node_next; + + do + { + ch = DOUBLE_LIST_ENTRY(ch_node, struct Channel, ch_link); + + if((ch) && (ch->ch_type == CH_PLC_TYPE)) + { + KPrintf("%s", " "); + KPrintf("%-15s%-15s", + channel_type_str[ch->ch_type], + ch->ch_name); + + driver = ShowChannelFindDriver(ch); + + if(driver) + { + KPrintf("%-15s", driver->drv_name); + } + else + { + KPrintf("%-15s", "nil"); + } + + if(ch->haldev_cnt) + { + DoublelistType* dev_node = NONE; + DoublelistType* dev_head = &ch->ch_devlink; + dev_node = dev_head->node_next; + dev_cnt = 1; + + while(dev_node != dev_head) + { + device = DOUBLE_LIST_ENTRY(dev_node, struct ChDev, dev_link); + + if(1 == dev_cnt) + { + if(device) + { + KPrintf("%-16s%-4d\n", device->dev_name, dev_cnt); + } + else + { + KPrintf("%-16s%-4d\n", "nil", dev_cnt); + } + } + else + { + KPrintf("%46s", " "); + + if(device) + { + KPrintf("%-16s%-4d\n", device->dev_name, dev_cnt); + } + else + { + KPrintf("%-16s%-4d\n", "nil", dev_cnt); + } + } + + dev_cnt++; + dev_node = dev_node->node_next; + } + } + else + { + KPrintf("\n"); + } + } + + ch_node = ch_node->node_next; + } + while(ch_node != ch_head); + + return; +} + +SHELL_EXPORT_CMD(SHELL_CMD_PERMISSION(0) | SHELL_CMD_TYPE(SHELL_TYPE_CMD_MAIN) | SHELL_CMD_PARAM_NUM(3), + ShowChannel, PlcShowChannel, Show PLC information); + +void PlcShowDev(void) +{ + PlcDeviceType* plc_dev; + ChDrvType driver; + ChDevType device; + DoublelistType* plc_node = NONE; + DoublelistType* plc_head = &plcdev_list; + const char* item_array[] = {"device", "vendor", "model", "product", "id"}; + PlcShowDemoInit(); + PlcShowTitle(item_array); + plc_node = plc_head->node_next; + + do + { + plc_dev = DOUBLE_LIST_ENTRY(plc_node, struct PlcDevice, link); + + if(plc_dev) + { + KPrintf("%s", " "); + KPrintf("%-15s%-15s%-15s%-15s%-20d", + plc_dev->name, + plc_dev->info.vendor, + plc_dev->info.model, + plc_dev->info.product, + plc_dev->info.id); + KPrintf("\n"); + } + + plc_node = plc_node->node_next; + } + while(plc_node != plc_head); + + return; +} + + +SHELL_EXPORT_CMD(SHELL_CMD_PERMISSION(0) | SHELL_CMD_TYPE(SHELL_TYPE_CMD_MAIN) | SHELL_CMD_PARAM_NUM(3), + ShowPlc, PlcShowDev, Show PLC information); + diff --git a/APP_Framework/Applications/cppmain.cpp b/APP_Framework/Applications/cppmain.cpp new file mode 100644 index 0000000..d9e1653 --- /dev/null +++ b/APP_Framework/Applications/cppmain.cpp @@ -0,0 +1,116 @@ +/* +* Copyright (c) 2020 AIIT XUOS Lab +* XiUOS is licensed under Mulan PSL v2. +* You can use this software according to the terms and conditions of the Mulan PSL v2. +* You may obtain a copy of Mulan PSL v2 at: +* http://license.coscl.org.cn/MulanPSL2 +* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, +* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, +* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. +* See the Mulan PSL v2 for more details. +*/ + +#include +#include +#include +using namespace std; +extern "C" void KPrintf(const char *fmt, ...); + +class Animal //parent class + +{ + +public: + + virtual void Eat() + { + + KPrintf("eat\n"); + + } + + void Sleep() + { + KPrintf("sleep\n"); + } + + +}; + +class Fish :public Animal //subclass +{ + +public: + + void Eat() + { + KPrintf("fish eat\n"); + + + } +}; + +void Doeat(Animal& animal) +{ + animal.Eat(); +} + +void MemTest2() +{ + int i; + char *ptr = NULL; /* memory pointer */ + + for (i = 0; ; i++) { + /* allocate (1< +void MySwap(T& a, T& b) +{ + T temp = a; + a = b; + b = temp; +} + +extern "C" int cppmain(void) +{ + MemTest2(); + + class Fish fish; + Doeat(fish); + + int a = 3; + int b = 5; + void OverLoadTestDouble(int a, int b); + OverLoadTestDouble(a, b); + MySwap(a,b); + KPrintf("with template the output is: %d and %d\n", a,b); + + return 0; +} diff --git a/APP_Framework/Applications/embedded_database_app/Kconfig b/APP_Framework/Applications/embedded_database_app/Kconfig new file mode 100644 index 0000000..271aa01 --- /dev/null +++ b/APP_Framework/Applications/embedded_database_app/Kconfig @@ -0,0 +1,6 @@ +menuconfig USING_EMBEDDED_DATABASE_APP + bool "embedded database app" + default n +if USING_EMBEDDED_DATABASE_APP + source "$APP_DIR/Applications/embedded_database_app/flashdb_app/Kconfig" +endif diff --git a/APP_Framework/Applications/embedded_database_app/SConscript b/APP_Framework/Applications/embedded_database_app/SConscript new file mode 100644 index 0000000..f307e3f --- /dev/null +++ b/APP_Framework/Applications/embedded_database_app/SConscript @@ -0,0 +1,14 @@ +import os +Import('RTT_ROOT') +from building import * + +cwd = GetCurrentDir() +objs = [] +list = os.listdir(cwd) + +for d in list: + path = os.path.join(cwd, d) + if os.path.isfile(os.path.join(path, 'SConscript')): + objs = objs + SConscript(os.path.join(path, 'SConscript')) + +Return('objs') diff --git a/APP_Framework/Applications/framework_init.c b/APP_Framework/Applications/framework_init.c new file mode 100644 index 0000000..2d08c4b --- /dev/null +++ b/APP_Framework/Applications/framework_init.c @@ -0,0 +1,232 @@ +/* +* Copyright (c) 2020 AIIT XUOS Lab +* XiUOS is licensed under Mulan PSL v2. +* You can use this software according to the terms and conditions of the Mulan PSL v2. +* You may obtain a copy of Mulan PSL v2 at: +* http://license.coscl.org.cn/MulanPSL2 +* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, +* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, +* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. +* See the Mulan PSL v2 for more details. +*/ +#include +#include +#include + +extern int SensorFrameworkInit(void); +extern int AdapterFrameworkInit(void); + +extern int Adapter4GInit(void); +extern int AdapterNbiotInit(void); +extern int AdapterBlueToothInit(void); +extern int AdapterWifiInit(void); +extern int AdapterEthernetInit(void); +extern int AdapterEthercatInit(void); +extern int AdapterZigbeeInit(void); +extern int AdapterLoraInit(void); + +extern int D124VoiceInit(void); +extern int Hs300xTemperatureInit(void); +extern int Hs300xHumidityInit(void); +extern int Ps5308Pm1_0Init(void); +extern int Ps5308Pm2_5Init(void); +extern int Ps5308Pm10Init(void); +extern int Zg09Co2Init(void); +extern int As830Ch4Init(void); +extern int Tb600bIaq10IaqInit(void); +extern int Tb600bTvoc10TvocInit(void); +extern int Tb600bWqHcho1osInit(void); +extern int QsFxWindDirectionInit(void); +extern int QsFsWindSpeedInit(void); + +extern int lv_port_init(void); + +typedef int (*InitFunc)(void); +struct InitDesc +{ + const char* fn_name; + const InitFunc fn; +}; + +static int AppInitDesc(struct InitDesc sub_desc[]) +{ + int i = 0; + int ret = 0; + for( i = 0; sub_desc[i].fn != NULL; i++ ) { + ret = sub_desc[i].fn(); + printf("initialize %s %s\n",sub_desc[i].fn_name, ret == 0 ? "success" : "failed"); + if(0 != ret) { + break; + } + } + return ret; +} + +static struct InitDesc framework[] = +{ +#ifdef SUPPORT_SENSOR_FRAMEWORK + { "sensor_framework", SensorFrameworkInit }, +#endif + +#ifdef SUPPORT_CONNECTION_FRAMEWORK + { "connection_framework", AdapterFrameworkInit }, +#endif + + { "NULL", NULL }, +}; + +static struct InitDesc sensor_desc[] = +{ +#ifdef SENSOR_DEVICE_D124 + { "d124_voice", D124VoiceInit }, +#endif + +#ifdef SENSOR_DEVICE_HS300X +#ifdef SENSOR_QUANTITY_HS300X_TEMPERATURE + { "hs300x_temperature", Hs300xTemperatureInit }, +#endif +#ifdef SENSOR_QUANTITY_HS300X_HUMIDITY + { "hs300x_humidity", Hs300xHumidityInit }, +#endif +#endif + +#ifdef SENSOR_PS5308 +#ifdef SENSOR_QUANTITY_PS5308_PM1_0 + { "ps5308_pm1_0", Ps5308Pm1_0Init }, +#endif +#ifdef SENSOR_QUANTITY_PS5308_PM2_5 + { "ps5308_pm2_5", Ps5308Pm2_5Init }, +#endif +#ifdef SENSOR_QUANTITY_PS5308_PM10 + { "ps5308_pm10", Ps5308Pm10Init }, +#endif +#endif + +#ifdef SENSOR_ZG09 + { "zg09_co2", Zg09Co2Init }, +#endif + +#ifdef SENSOR_QS_FX + { "qs_fx_wind_direction", QsFxWindDirectionInit }, +#endif + +#ifdef SENSOR_QS_FS + { "qs_fs_wind_speed", QsFsWindSpeedInit }, +#endif + +#ifdef SENSOR_AS830 + { "ch4_as830", As830Ch4Init }, +#endif + +#ifdef SENSOR_TB600B_IAQ10 + { "iaq_tb600b_iaq10", Tb600bIaq10IaqInit }, +#endif + +#ifdef SENSOR_TB600B_TVOC10 + { "tvoc_tb600b_tvoc10", Tb600bTvoc10TvocInit }, +#endif + +#ifdef SENSOR_TB600B_WQ_HCHO1OS + { "tvoc_tb600b_wq_hcho1os", Tb600bWqHcho1osInit }, +#endif + + { "NULL", NULL }, +}; + +static struct InitDesc connection_desc[] = +{ +#ifdef CONNECTION_ADAPTER_4G + { "4G adapter", Adapter4GInit}, +#endif +#ifdef CONNECTION_ADAPTER_NB + { "NB adpter", AdapterNbiotInit}, +#endif +#ifdef CONNECTION_ADAPTER_ZIGBEE + { "zigbee adapter", AdapterZigbeeInit}, +#endif +#ifdef CONNECTION_ADAPTER_BLUETOOTH + { "bluetooth adapter", AdapterBlueToothInit}, +#endif +#ifdef CONNECTION_ADAPTER_WIFI + { "wifi adapter", AdapterWifiInit}, +#endif +#ifdef CONNECTION_ADAPTER_ETHERNET + { "ethernet adapter", AdapterEthernetInit}, +#endif +#ifdef CONNECTION_ADAPTER_ETHERCAT + { "ethercat adapter", AdapterEthercatInit}, +#endif +#ifdef CONNECTION_ADAPTER_LORA + { "lora adapter", AdapterLoraInit}, +#endif + { "NULL", NULL }, +}; + +/** + * This function will init sensor framework and all sub sensors + * @param sub_desc framework + * + */ +static int SensorDeviceFrameworkInit(struct InitDesc sub_desc[]) +{ + int i = 0; + int ret = 0; + for ( i = 0; sub_desc[i].fn != NULL; i++ ) { + if (0 == strncmp(sub_desc[i].fn_name, "sensor_framework", strlen("sensor_framework"))) { + ret = sub_desc[i].fn(); + break; + } + } + + if (0 == ret) { + printf("initialize sensor_framework success.\n"); + AppInitDesc(sensor_desc); + } + + return ret; +} + +/** + * This function will init connection framework and all sub components + * @param sub_desc framework + * + */ +static int ConnectionDeviceFrameworkInit(struct InitDesc sub_desc[]) +{ + int i = 0; + int ret = 0; + for ( i = 0; sub_desc[i].fn != NULL; i++ ) { + if (0 == strncmp(sub_desc[i].fn_name, "connection_framework", strlen("connection_framework"))) { + ret = sub_desc[i].fn(); + break; + } + } + + if (0 == ret) { + printf("initialize connection_framework success.\n"); + AppInitDesc(connection_desc); + } + + return ret; +} + +/** + * This function will init system framework + * + */ +int FrameworkInit(void) +{ +#ifdef SUPPORT_SENSOR_FRAMEWORK + SensorDeviceFrameworkInit(framework); +#endif + +#ifdef SUPPORT_CONNECTION_FRAMEWORK + ConnectionDeviceFrameworkInit(framework); +#endif + +#ifdef LIB_LV + lv_port_init(); +#endif + + return 0; +} \ No newline at end of file diff --git a/APP_Framework/Applications/general_functions/Makefile b/APP_Framework/Applications/general_functions/Makefile new file mode 100644 index 0000000..57265e8 --- /dev/null +++ b/APP_Framework/Applications/general_functions/Makefile @@ -0,0 +1,3 @@ +SRC_DIR := list + +include $(KERNEL_ROOT)/compiler.mk \ No newline at end of file diff --git a/APP_Framework/Applications/general_functions/SConscript b/APP_Framework/Applications/general_functions/SConscript new file mode 100644 index 0000000..f307e3f --- /dev/null +++ b/APP_Framework/Applications/general_functions/SConscript @@ -0,0 +1,14 @@ +import os +Import('RTT_ROOT') +from building import * + +cwd = GetCurrentDir() +objs = [] +list = os.listdir(cwd) + +for d in list: + path = os.path.join(cwd, d) + if os.path.isfile(os.path.join(path, 'SConscript')): + objs = objs + SConscript(os.path.join(path, 'SConscript')) + +Return('objs') diff --git a/APP_Framework/Applications/general_functions/list/Makefile b/APP_Framework/Applications/general_functions/list/Makefile new file mode 100644 index 0000000..acfac59 --- /dev/null +++ b/APP_Framework/Applications/general_functions/list/Makefile @@ -0,0 +1,11 @@ +include $(KERNEL_ROOT)/.config +ifeq ($(CONFIG_ADD_NUTTX_FETURES),y) + include $(APPDIR)/Make.defs + CSRCS += double_list.c single_list.c + include $(APPDIR)/Application.mk +endif + +ifeq ($(CONFIG_ADD_XIZI_FETURES),y) + SRC_FILES := double_list.c single_list.c + include $(KERNEL_ROOT)/compiler.mk +endif \ No newline at end of file diff --git a/APP_Framework/Applications/general_functions/list/SConscript b/APP_Framework/Applications/general_functions/list/SConscript new file mode 100644 index 0000000..e1ff73e --- /dev/null +++ b/APP_Framework/Applications/general_functions/list/SConscript @@ -0,0 +1,11 @@ +import os +from building import * +Import('RTT_ROOT') +Import('rtconfig') +cwd = GetCurrentDir() +DEPENDS = [""] + +SOURCES = ['double_list.c'] + ['single_list.c'] +path = [cwd] +objs = DefineGroup('list', src = SOURCES, depend = DEPENDS,CPPPATH = path) +Return("objs") \ No newline at end of file diff --git a/APP_Framework/Applications/general_functions/list/double_list.c b/APP_Framework/Applications/general_functions/list/double_list.c new file mode 100644 index 0000000..2f25b20 --- /dev/null +++ b/APP_Framework/Applications/general_functions/list/double_list.c @@ -0,0 +1,84 @@ +/* +* Copyright (c) 2020 AIIT XUOS Lab +* XiUOS is licensed under Mulan PSL v2. +* You can use this software according to the terms and conditions of the Mulan PSL v2. +* You may obtain a copy of Mulan PSL v2 at: +* http://license.coscl.org.cn/MulanPSL2 +* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, +* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, +* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. +* See the Mulan PSL v2 for more details. +*/ + +/** +* @file: double_link.c +* @brief: functions definition of double list for application +* @version: 1.0 +* @author: AIIT XUOS Lab +* @date: 2020/3/15 +* +*/ + +#include "list.h" + +void AppInitDoubleList(DoublelistType *list_head) +{ + list_head->node_next = list_head; + list_head->node_prev = list_head; +} + +void AppDoubleListInsertNodeAfter(DoublelistType *list, DoublelistType *list_node) +{ + list->node_next->node_prev = list_node; + list_node->node_next = list->node_next; + + list->node_next = list_node; + list_node->node_prev = list; +} + +void AppDoubleListInsertNodeBefore(DoublelistType *list, DoublelistType *list_node) +{ + list->node_prev->node_next = list_node; + list_node->node_prev = list->node_prev; + + list->node_prev = list_node; + list_node->node_next = list; +} + +void AppDoubleListRmNode(DoublelistType *list_node) +{ + list_node->node_next->node_prev = list_node->node_prev; + list_node->node_prev->node_next = list_node->node_next; + + list_node->node_next = list_node; + list_node->node_prev = list_node; +} + +int AppIsDoubleListEmpty(const DoublelistType *list) +{ + return list->node_next == list; +} + +struct DoublelistNode *AppDoubleListGetHead(const DoublelistType *list) +{ + return AppIsDoubleListEmpty(list) ? NULL : list->node_next; +} + +struct DoublelistNode *AppDoubleListGetNext(const DoublelistType *list, + const struct DoublelistNode *list_node) +{ + return list_node->node_next == list ? NULL : list_node->node_next; +} + +unsigned int AppDoubleListLenGet(const DoublelistType *list) +{ + unsigned int linklist_length = 0; + const DoublelistType *tmp_node = list; + while (tmp_node->node_next != list) + { + tmp_node = tmp_node->node_next; + linklist_length ++; + } + + return linklist_length; +} \ No newline at end of file diff --git a/APP_Framework/Applications/general_functions/list/list.h b/APP_Framework/Applications/general_functions/list/list.h new file mode 100644 index 0000000..98ed2cb --- /dev/null +++ b/APP_Framework/Applications/general_functions/list/list.h @@ -0,0 +1,120 @@ +/* +* Copyright (c) 2020 AIIT XUOS Lab +* XiUOS is licensed under Mulan PSL v2. +* You can use this software according to the terms and conditions of the Mulan PSL v2. +* You may obtain a copy of Mulan PSL v2 at: +* http://license.coscl.org.cn/MulanPSL2 +* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, +* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, +* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. +* See the Mulan PSL v2 for more details. +*/ + +/** +* @file: list.h +* @brief: function declaration and structure defintion of list +* @version: 1.0 +* @author: AIIT XUOS Lab +* @date: 2021/6/23 +* +*/ + +#ifndef __LIST_H__ +#define __LIST_H__ + +#include +#include +#include +#include +#ifdef __cplusplus +extern "C" { +#endif + + +typedef struct DoublelistNode +{ + struct DoublelistNode *node_next; + struct DoublelistNode *node_prev; +} DoublelistType; + +// Single List +typedef struct SinglelistNode +{ + struct SinglelistNode *node_next; +} SinglelistType; + + +#define CONTAINER_OF(item, type, member) \ + ((type *)((char *)(item) - (unsigned long)(&((type *)0)->member))) + + +#define DOUBLE_LIST_OBJ_INIT(obj) { &(obj), &(obj) } + +void AppInitDoubleList(DoublelistType *linklist_head); +void AppDoubleListInsertNodeAfter(DoublelistType *list, DoublelistType *list_node); +void AppDoubleListInsertNodeBefore(DoublelistType *list, DoublelistType *list_node); +void AppDoubleListRmNode(DoublelistType *list_node); +int AppIsDoubleListEmpty(const DoublelistType *list); +struct DoublelistNode *AppDoubleLinkListGetHead(const DoublelistType *list); +struct DoublelistNode *AppDoubleLinkListGetNext(const DoublelistType *list, + const struct DoublelistNode *list_node); +unsigned int AppDoubleListLenGet(const DoublelistType *list); + +#define DOUBLE_LIST_ENTRY(item, type, member) \ + CONTAINER_OF(item, type, member) + +#define DOUBLE_LIST_FOR_EACH(item, head) \ + for (item = (head)->node_next; item != (head); item = item->node_next) + +#define DOUBLE_LIST_FOR_EACH_SAFE(item, node_next, head) \ + for (item = (head)->node_next, node_next = item->node_next; item != (head); \ + item = node_next, node_next = item->node_next) + +#define DOUBLE_LIST_FOR_EACH_ENTRY(item, head, member) \ + for (item = DOUBLE_LIST_ENTRY((head)->node_next, typeof(*item), member); \ + &item->member != (head); \ + item = DOUBLE_LIST_ENTRY(item->member.node_next, typeof(*item), member)) + +#define DOUBLE_LIST_FOR_EACH_ENTRY_SAFE(item, node_next, head, member) \ + for (item = DOUBLE_LIST_ENTRY((head)->node_next, typeof(*item), member), \ + node_next = DOUBLE_LIST_ENTRY(item->member.node_next, typeof(*item), member); \ + &item->member != (head); \ + item = node_next, node_next = DOUBLE_LIST_ENTRY(node_next->member.node_next, typeof(*node_next), member)) + +#define DOUBLE_LIST_FIRST_ENTRY(ptr, type, member) \ + DOUBLE_LIST_ENTRY((ptr)->node_next, type, member) + +#define SINGLE_LIST_OBJ_INIT(obj) { NONE } + +void AppInitSingleList(SinglelistType *list); +void AppAppendSingleList(SinglelistType *list, SinglelistType *list_node); +void AppSingleListNodeInsert(SinglelistType *list, SinglelistType *list_node); +unsigned int AppSingleListGetLen(const SinglelistType *list); +SinglelistType *AppSingleListRmNode(SinglelistType *list, SinglelistType *list_node); +SinglelistType *AppSingleListGetFirstNode(SinglelistType *list); +SinglelistType *AppSingleListGetTailNode(SinglelistType *list); +SinglelistType *AppSingleListGetNextNode(SinglelistType *list_node); +int AppIsSingleListEmpty(SinglelistType *list); + +#define SINGLE_LIST_ENTRY(node, type, member) \ + CONTAINER_OF(node, type, member) + +#define SINGLE_LIST_FOR_EACH(item, head) \ + for (item = (head)->node_next; item != NONE; item = item->node_next) + +#define SINGLE_LIST_FOR_EACH_ENTRY(item, head, member) \ + for (item = SINGLE_LIST_ENTRY((head)->node_next, typeof(*item), member); \ + &item->member != (NONE); \ + item = SINGLE_LIST_ENTRY(item->member.node_next, typeof(*item), member)) + +#define SINGLE_LIST_FIRST_ENTRY(ptr, type, member) \ + SINGLE_LIST_ENTRY((ptr)->node_next, type, member) + +#define SINGLE_LIST_TAIL_ENTRY(ptr, type, member) \ + SINGLE_LIST_ENTRY(AppSingleListGetTailNode(ptr), type, member) + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/APP_Framework/Applications/general_functions/list/single_list.c b/APP_Framework/Applications/general_functions/list/single_list.c new file mode 100644 index 0000000..bfefbd2 --- /dev/null +++ b/APP_Framework/Applications/general_functions/list/single_list.c @@ -0,0 +1,91 @@ +/* +* Copyright (c) 2020 AIIT XUOS Lab +* XiUOS is licensed under Mulan PSL v2. +* You can use this software according to the terms and conditions of the Mulan PSL v2. +* You may obtain a copy of Mulan PSL v2 at: +* http://license.coscl.org.cn/MulanPSL2 +* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, +* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, +* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. +* See the Mulan PSL v2 for more details. +*/ + +/** +* @file: double_link.c +* @brief: functions definition of single list for application +* @version: 1.0 +* @author: AIIT XUOS Lab +* @date: 2020/3/15 +* +*/ + +#include "list.h" + +void AppInitSingleList(SinglelistType *list) +{ + list->node_next = NULL; +} + +void AppAppendSingleList(SinglelistType *list, SinglelistType *list_node) +{ + struct SinglelistNode *node; + + node = list; + while (node->node_next) node = node->node_next; + + node->node_next = list_node; + list_node->node_next = NULL; +} + +void AppSingleListNodeInsert(SinglelistType *list, SinglelistType *list_node) +{ + list_node->node_next = list->node_next; + list->node_next = list_node; +} + +unsigned int AppSingleListGetLen(const SinglelistType *list) +{ + unsigned int length = 0; + const SinglelistType *tmp_list = list->node_next; + while (tmp_list != NULL) + { + tmp_list = tmp_list->node_next; + length ++; + } + + return length; +} + +SinglelistType *AppSingleListRmNode(SinglelistType *list, SinglelistType *list_node) +{ + struct SinglelistNode *node = list; + while (node->node_next && node->node_next != list_node) node = node->node_next; + + if (node->node_next != (SinglelistType *)0){ + node->node_next = node->node_next->node_next; + } + + return list; +} + +SinglelistType *AppSingleListGetFirstNode(SinglelistType *list) +{ + return list->node_next; +} + +SinglelistType *AppSingleListGetTailNode(SinglelistType *list) +{ + while (list->node_next) list = list->node_next; + + return list; +} + +SinglelistType *AppSingleListGetNextNode(SinglelistType *list_node) +{ + return list_node->node_next; +} + +int AppIsSingleListEmpty(SinglelistType *list) +{ + return list->node_next == NULL; +} \ No newline at end of file diff --git a/APP_Framework/Applications/knowing_app/Kconfig b/APP_Framework/Applications/knowing_app/Kconfig new file mode 100755 index 0000000..5090c42 --- /dev/null +++ b/APP_Framework/Applications/knowing_app/Kconfig @@ -0,0 +1,16 @@ +menu "knowing app" + menuconfig APPLICATION_KNOWING + bool "Using knowing apps" + default n + + if APPLICATION_KNOWING + source "$APP_DIR/Applications/knowing_app/mnist/Kconfig" + source "$APP_DIR/Applications/knowing_app/k210_detect_entry/Kconfig" + source "$APP_DIR/Applications/knowing_app/iris_ml_demo/Kconfig" + source "$APP_DIR/Applications/knowing_app/k210_fft_test/Kconfig" + source "$APP_DIR/Applications/knowing_app/image_processing/Kconfig" + source "$APP_DIR/Applications/knowing_app/cmsis_5_demo/Kconfig" + source "$APP_DIR/Applications/knowing_app/nnom_demo/Kconfig" + + endif +endmenu diff --git a/APP_Framework/Applications/knowing_app/Make.defs b/APP_Framework/Applications/knowing_app/Make.defs new file mode 100644 index 0000000..cd8c87c --- /dev/null +++ b/APP_Framework/Applications/knowing_app/Make.defs @@ -0,0 +1,6 @@ +############################################################################ +# Applications/knowing_app/Make.defs +############################################################################ +ifneq ($(CONFIG_APPLICATION_KNOWING),) +include $(wildcard $(APPDIR)/../../../APP_Framework/Applications/knowing_app/*/Make.defs) +endif diff --git a/APP_Framework/Applications/knowing_app/Makefile b/APP_Framework/Applications/knowing_app/Makefile new file mode 100755 index 0000000..3357fbf --- /dev/null +++ b/APP_Framework/Applications/knowing_app/Makefile @@ -0,0 +1,3 @@ +SRC_DIR := mnist + +include $(KERNEL_ROOT)/compiler.mk \ No newline at end of file diff --git a/APP_Framework/Applications/knowing_app/SConscript b/APP_Framework/Applications/knowing_app/SConscript new file mode 100644 index 0000000..f307e3f --- /dev/null +++ b/APP_Framework/Applications/knowing_app/SConscript @@ -0,0 +1,14 @@ +import os +Import('RTT_ROOT') +from building import * + +cwd = GetCurrentDir() +objs = [] +list = os.listdir(cwd) + +for d in list: + path = os.path.join(cwd, d) + if os.path.isfile(os.path.join(path, 'SConscript')): + objs = objs + SConscript(os.path.join(path, 'SConscript')) + +Return('objs') diff --git a/APP_Framework/Applications/main.c b/APP_Framework/Applications/main.c new file mode 100644 index 0000000..b10557a --- /dev/null +++ b/APP_Framework/Applications/main.c @@ -0,0 +1,31 @@ +/* +* Copyright (c) 2020 AIIT XUOS Lab +* XiUOS is licensed under Mulan PSL v2. +* You can use this software according to the terms and conditions of the Mulan PSL v2. +* You may obtain a copy of Mulan PSL v2 at: +* http://license.coscl.org.cn/MulanPSL2 +* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, +* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, +* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. +* See the Mulan PSL v2 for more details. +*/ + +#include +#include +// #include +#include + +extern int FrameworkInit(); +extern void ApplicationOtaTaskInit(void); +int main(void) +{ + printf("Hello, world! \n"); + FrameworkInit(); +#ifdef APPLICATION_OTA + ApplicationOtaTaskInit(); +#endif + return 0; +} +// int cppmain(void); + + diff --git a/APP_Framework/Applications/ota/Kconfig b/APP_Framework/Applications/ota/Kconfig new file mode 100755 index 0000000..097519d --- /dev/null +++ b/APP_Framework/Applications/ota/Kconfig @@ -0,0 +1,7 @@ +menu "ota app " + menuconfig APPLICATION_OTA + bool "Using app bin ota" + default n + + +endmenu diff --git a/APP_Framework/Applications/ota/Makefile b/APP_Framework/Applications/ota/Makefile new file mode 100644 index 0000000..2f5316c --- /dev/null +++ b/APP_Framework/Applications/ota/Makefile @@ -0,0 +1,3 @@ +SRC_FILES := ota.c + +include $(KERNEL_ROOT)/compiler.mk diff --git a/APP_Framework/Applications/ota/README.md b/APP_Framework/Applications/ota/README.md new file mode 100644 index 0000000..a824345 --- /dev/null +++ b/APP_Framework/Applications/ota/README.md @@ -0,0 +1,19 @@ +# OTA README + +xiuos当前的ota功能允许应用bin文件可以通过4G实现远程的bin文件更新（限制：1、bin文件存放在设备SD卡并且应用从SD卡启动；2、暂且支持4G实现；3、暂时只支持aiit终端;4、只支持xiuos内核）。 + +## 文件说明 + +| 名称 | 说明 | +| -- | -- | +| ota.c| xiuos设备OTA代码 | +| ota_server.c | pc服务端的实例代码供参考 | + + +## 使用说明 +xiuos的应用bin文件更新依赖上层的adapter框架，因此需要在menuconfig同时配置以下选项： +1、ota开关APPLICATION_OTA打开； +2、adapter的4G功能开关； +3、拆分的应用启动SEPARATE_COMPILE开关从SD卡启动的配置开关APP_STARTUP_FROM_SDCARD。 + + diff --git a/APP_Framework/Applications/ota/ota.c b/APP_Framework/Applications/ota/ota.c new file mode 100644 index 0000000..d361a0f --- /dev/null +++ b/APP_Framework/Applications/ota/ota.c @@ -0,0 +1,411 @@ + +/* +* Copyright (c) 2020 AIIT XUOS Lab +* XiUOS is licensed under Mulan PSL v2. +* You can use this software according to the terms and conditions of the Mulan PSL v2. +* You may obtain a copy of Mulan PSL v2 at: +* http://license.coscl.org.cn/MulanPSL2 +* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, +* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, +* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. +* See the Mulan PSL v2 for more details. +*/ + +/** +* @file: ota.c +* @brief: a application ota task of system +* @version: 1.0 +* @author: AIIT XUOS Lab +* @date: 2021/11/3 +* +*/ +#include +#include + +extern int main(void); + +struct ota_header_t +{ + int16 frame_flag; ///< frame start flag 2 Bytes + uint8 dev_type; ///< device type + uint8 burn_mode; ///< data burn way + uint32 total_len; ///< send data total length caculated from each frame_len + uint32 dev_hid; ///< device hardware version + uint32 dev_sid; ///< device software version + char resv[8]; ///< reserve +}; + +struct ota_frame_t +{ + uint32 frame_id; ///< Current frame id + uint32 frame_len; ///< Current frame data length + char frame_data[64]; ///< Current frame data,max length 64 + uint32 crc; ///< Current frame data crc +}; + +struct ota_data +{ + struct ota_header_t header; + struct ota_frame_t frame; + char end[4]; +}; + +pthread_t ota_task; +pthread_t restart_main; + +/** + * @description: CRC16 check + * @param data data buffer + * @param length data length + * @return check code + */ +uint32_t OtaCrc16(uint8_t * data, uint32_t length) +{ + int j; + unsigned int reg_crc=0xFFFF; + printf("crc data length[%d] Bytes,",length); + + while (length--) { + reg_crc ^= *data++; + for (j=0;j<8;j++) { + if(reg_crc & 0x01) + reg_crc=reg_crc >>1 ^ 0xA001; + else + reg_crc=reg_crc >>1; + } + } + printf(" crc = [0x%x]\n",reg_crc); + return reg_crc; +} + +uint32_t FileCrc16(uint8_t * data, uint32_t length, unsigned int last_crc) +{ + int j; + //printf("crc data length[%d] Bytes,",length); + + while (length--) { + last_crc ^= *data++; + for (j=0;j<8;j++) { + if(last_crc & 0x01) + last_crc = last_crc >>1 ^ 0xA001; + else + last_crc = last_crc >>1; + } + } + + //printf(" crc = [0x%x]\n",last_crc); + + return last_crc; +} + + +static int SaveAppBin(int fd, char* buf, int len) +{ + int ret = 0; + int fd_t = 0; + fd_t = open( BOARD_APP_NAME, O_RDWR | O_APPEND); + ret = write(fd, buf, len); + if(ret < 0){ + printf("fd = %d write buf len[%d] failed.ret = %d\n",fd_t,len,ret); + } + else + { + printf("fd[%d] write buf length[%d] done.\n",fd_t,ret); + } + + close(fd_t); +} + +static int CrcFileCheck(uint32 crc_check, unsigned long total_len) +{ + int ret = 0; + int fd = 0; + int len = 0; + char *buf = NULL; + unsigned int last_crc = 0xffff; + unsigned long already_crc_length = 0; + + fd = open( BOARD_APP_NAME, O_RDONLY ); + if(fd < 0){ + printf("open %s bin failed.\n",BOARD_APP_NAME); + return -1; + } + + buf = PrivMalloc(128); + if(NULL == buf) + { + printf("malloc failed.\n"); + close(fd); + return 0; + } + + /* crc check every 1024 Bytes until crc all the total file */ + while(already_crc_length != total_len) + { + memset(buf , 0 , 128); + len = read(fd, buf, 128); + if(len < 0) + { + printf("file read failed.ret = %d\n",len); + ret = -1; + break; + } + + last_crc = FileCrc16(buf, len, last_crc); + already_crc_length += len; + printf("read len[%d] Bytes,already_crc_length[%d]\n",len,already_crc_length); + } + + + if (last_crc != crc_check) + { + printf("file crc error!!! last crc[%x] != check[%x]\n",last_crc,crc_check); + ret =-1; + } + + PrivFree(buf); + close(fd); + + return ret; +} + +static void RestartApplication(void) +{ + pthread_attr_t attr; + attr.schedparam.sched_priority = 10; + attr.stacksize = 2048; + + while(1) + { + unsigned long pid = PrivUserTaskSearch(); + if ((pid > 0) && (pid != pthread_self())) + { + printf("kill usertask pid[%d]\n",pid); + PrivTaskDelete(pid, 0); + PrivTaskDelay(1000); /* NOTE:this delay will make a schedule and recycle all user task */ + } + else + { + break; + } + } + printf("restart main.\n"); + PrivTaskCreate(&restart_main, &attr, (void *)main, NULL); +} +static int OtaDataRecv(struct Adapter* adapter) +{ + struct ota_data recv_msg; + char reply[16] = {0}; + int ret = 0; + int try_times = 10; + int fd = 0; + int frame_cnt = 0; + + fd = open( BOARD_APP_NAME, O_RDWR | O_CREAT | O_TRUNC, S_IRUSR | S_IWUSR); + if(fd < 0) + { + printf("open %s failed\n",BOARD_APP_NAME); + return -1; + } + close(fd); + + while(1) { + memset(&recv_msg, 0, sizeof(struct ota_data)); + printf("recv msg...\n"); + ret = AdapterDeviceRecv(adapter, &recv_msg, sizeof(struct ota_data)); + if(ret >= 0 && recv_msg.header.frame_flag == 0x5A5A) + { + if(0 == strncmp("aiit_ota_end",recv_msg.frame.frame_data, strlen("aiit_ota_end"))) + { + printf("total [%d]frames [%d]Bytes crc[%x],receive successful,\n",frame_cnt,recv_msg.header.total_len,recv_msg.frame.crc); + if(0 != CrcFileCheck(recv_msg.frame.crc, recv_msg.header.total_len)) + { + printf("crc check %s bin failed.please try again.\n", BOARD_APP_NAME); + ret = -1; + break; + } + PrivTaskDelay(500); + printf("tolal file crc done.send ok\n"); + memset(reply, 0, 16); + memcpy(reply, "ok", strlen("ok")); + + AdapterDeviceSend(adapter, reply, strlen(reply)); + ret = 0; + break; + } + frame_cnt = recv_msg.frame.frame_id; + + if(0 == strncmp("wait_ok_timeout",recv_msg.frame.frame_data, strlen("wait_ok_timeout"))) + { + printf("go to send ok again.\n"); + goto send_ok_again; + + } + + if (recv_msg.frame.crc == OtaCrc16(recv_msg.frame.frame_data,recv_msg.frame.frame_len)) + { + printf("save current [%d] frame,length[%d] Bytes.\n",frame_cnt,recv_msg.frame.frame_len); + for(int i = 0; i < recv_msg.frame.frame_len;i++ ){ + printf(" %x ",*((char *)&recv_msg.frame.frame_data + i)); + } + printf("\n"); + SaveAppBin(fd, recv_msg.frame.frame_data, recv_msg.frame.frame_len); + } + else + { + printf("current [%d] frame crc check failed,try again!\n",frame_cnt); + goto try_again; + } + +send_ok_again: + memset(reply, 0, 16); + memcpy(reply, "ok", strlen("ok")); + // PrivTaskDelay(100); + + ret = AdapterDeviceSend(adapter, reply, strlen(reply)); + if(ret < 0){ + printf("send ok failed.\n"); + goto send_ok_again; + } + printf("send reply[%s] done.\n",reply); + try_times = 10; + continue; + } + else + { +try_again: + if(try_times == 0) + { + printf("oops!!! current [%d] frame try 10 times failed,break out!\n",frame_cnt); + ret = -1; + break; + } + memset(reply, 0, 16); + memcpy(reply, "retry", strlen("retry")); + printf("[%d] frame receive failed. retry\n",frame_cnt); + AdapterDeviceSend(adapter, reply, strlen(reply)); + try_times--; + continue; + } + } + close(fd); + + if(0 == ret) { + printf("ota file done,start application.\n"); + RestartApplication(); + } + return ret; +} + +static void *OtaKTaskEntry(void *parameter) +{ + struct ota_data recv_msg; + char reply[16] = {0}; + int baud_rate = BAUD_RATE_115200; + int len = 0; + int ret = 0; + + struct Adapter* adapter = AdapterDeviceFindByName("4G"); + uint8 server_addr[64] = "115.238.53.61"; + uint8 server_port[64] = "9898"; + + adapter->socket.socket_id = 0; + + AdapterDeviceOpen(adapter); + AdapterDeviceControl(adapter, OPE_INT, &baud_rate); + AdapterDeviceConnect(adapter, CLIENT, server_addr, server_port, IPV4); + + /* using nbiot as connection way*/ + +// struct Adapter* adapter = AdapterDeviceFindByName("nbiot"); + +// while(1) +// { +// int connect_times = 5; +// ret = AdapterDeviceOpen(adapter); +// if(ret < 0) +// { +// printf("open adapter failed\n"); +// continue; +// } + +// connect_again: +// connect_times--; +// ret = AdapterDeviceConnect(adapter, 1, "115.238.53.61","9898",1); +// if(ret < 0) +// { +// if(connect_times > 0){ +// goto connect_again; +// } +// else +// { +// AdapterDeviceClose(adapter); +// continue; +// } +// } +// break; +// } + PrivTaskDelay(5000); + while(1) + { + memset(&recv_msg, 0, sizeof(struct ota_data)); + /* step1: Confirm the start signal of transmission*/ + printf("waiting for start msg...\n"); + ret = AdapterDeviceRecv(adapter, &recv_msg, sizeof(struct ota_data)); + for(int i = 0; i < sizeof(struct ota_data);i++ ){ + printf(" %x ",*((char *)&recv_msg + i)); + } + printf("\n"); + if(ret >= 0 && recv_msg.header.frame_flag == 0x5A5A) + { + if (0 == strncmp("aiit_ota_start",recv_msg.frame.frame_data, strlen("aiit_ota_start"))) + { + memset(reply, 0, 16); + memcpy(reply, "ready", strlen("ready")); + // PrivTaskDelay(3000); + printf("receive start signal,send [ready] signal to server\n"); +send_ready_again: + ret = AdapterDeviceSend(adapter, reply, strlen(reply)); + if(ret < 0) + { + goto send_ready_again; + } + PrivTaskDelay(3000); + printf("start receive ota file.\n"); + /* step2: start receive source bin file of application*/ + ret = OtaDataRecv(adapter); + if (0 != ret) + { + memset(reply, 0, 16); + memcpy(reply, "ota_restart", strlen("ota_restart")); + AdapterDeviceSend(adapter, reply, strlen(reply)); + continue; + } + else + { + break; + } + } + } + else + { + memset(reply, 0, 16); + memcpy(reply, "notready", strlen("notready")); + printf("ota status:not ready\n"); + ret = AdapterDeviceSend(adapter, reply, strlen(reply)); + } + PrivTaskDelay(3000); /* check ota signal every 5s */ + } + AdapterDeviceClose(adapter); + +} + +void ApplicationOtaTaskInit(void) +{ + pthread_attr_t attr; + attr.schedparam.sched_priority = 20; + attr.stacksize = 4096; + + PrivTaskCreate(&ota_task, &attr, OtaKTaskEntry, NULL); + +} \ No newline at end of file diff --git a/APP_Framework/Applications/ota/ota_server.c b/APP_Framework/Applications/ota/ota_server.c new file mode 100644 index 0000000..e5760f0 --- /dev/null +++ b/APP_Framework/Applications/ota/ota_server.c @@ -0,0 +1,364 @@ +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include + +#include +#include + +typedef int BOOL; +#define true 1 +#define false 0 + +int serverfd;//服务器socket +int clientfd[100000];//客户端的socketfd,100个元素，clientfd[0]~clientfd[99] +int size = 99999;//用来控制进入聊天室的人数为50以内 +int PORT = 9898;//端口号 +typedef struct sockaddr meng; + +struct ota_header_t +{ + int16_t frame_flag; ///< frame start flag 2 Bytes + uint8_t dev_type; ///< device type + uint8_t burn_mode; ///< data burn way + uint32_t total_len; ///< send data total length caculated from each frame_len + uint32_t dev_hid; ///< device hardware version + uint32_t dev_sid; ///< device software version + char resv[8]; ///< reserve +}; + +struct ota_frame_t +{ + uint32_t frame_id; ///< Current frame id + uint32_t frame_len; ///< Current frame data length + char frame_data[64]; ///< Current frame data,max length 224 + uint32_t crc; ///< Current frame data crc +}; + +struct ota_data +{ + struct ota_header_t header; + struct ota_frame_t frame; + char end[4]; +}; + +pthread_t ota_ktask; + +/** + * @description: CRC16 check + * @param data data buffer + * @param length data length + * @return check code + */ +uint32_t OtaCrc16(uint8_t * data, uint32_t length) +{ + int j; + unsigned int reg_crc=0xFFFF; + + printf("crc data length[%d] Bytes,",length); + + while (length--) { + reg_crc ^= *data++; + for (j=0;j<8;j++) { + if(reg_crc & 0x01) + reg_crc=reg_crc >>1 ^ 0xA001; + else + reg_crc=reg_crc >>1; + } + } + printf(" crc = [0x%x]\n",reg_crc); + return reg_crc; +} + +void init(void) +{ + serverfd = socket(PF_INET,SOCK_STREAM,0); + + if (serverfd == -1) + { + perror("创建socket失败"); + exit(-1); + } + +//为套接字设置ip协议 设置端口号 并自动获取本机ip转化为网络ip + + struct sockaddr_in addr;//存储套接字的信息 + addr.sin_family = AF_INET;//地址族 + addr.sin_port = htons(PORT);//设置server端端口号，你可以随便设置,当sin_port = 0时，系统随机选择一个未被使用的端口号 + addr.sin_addr.s_addr = htons(INADDR_ANY);//当sin_addr = INADDR_ANY时，表示从本机的任一网卡接收数据 + +//绑定套接字 + // int on = 1; + struct timeval timeout; + timeout.tv_sec = 5; + timeout.tv_usec = 0; + if(setsockopt(serverfd, SOL_SOCKET, SO_RCVTIMEO, &timeout, sizeof(struct timeval)) < 0) + { + perror("端口设置失败"); + exit(-1); + } + + if (bind(serverfd,(meng*)&addr,sizeof(addr)) == -1) + { + perror("绑定失败"); + exit(-1); + } + + if (listen(serverfd,100) == -1) + {//监听最大连接数 + perror("设置监听失败"); + exit(-1); + } +} +int OtaFileSend(int fd) +{ + unsigned char buf[32] = { 0 }; + struct ota_data data; + FILE *file_fd; + char ch; + int length = 0; + int try_times = 10; + int recv_end_times = 3; + int ret = 0; + int frame_cnt = 0; + int file_length = 0; + char * file_buf = NULL; + + file_fd = fopen("/home/aep04/wwg/XiUOS_aiit-arm32-board_app.bin", "r"); + if (NULL == file_fd){ + printf("open file failed.\n"); + return -1; + } + fseek(file_fd, 0, SEEK_SET); + printf("start send file.\n"); + while(!feof(file_fd)) + { + memset(&data, 0, sizeof(data)); + + data.header.frame_flag = 0x5A5A; + length = fread( data.frame.frame_data, 1, 64, file_fd ); + if(length > 0) + { + printf("read %d Bytes\n",length); + data.frame.frame_id = frame_cnt; + data.frame.frame_len = length; + data.frame.crc = OtaCrc16(data.frame.frame_data, length); + file_length += length; + } + +send_again: + usleep(50000); + printf("ota send current[%d] frame.\n",frame_cnt); + length = send(fd, &data, sizeof(data), MSG_NOSIGNAL); + if(length < 0){ + printf("send [%d] frame faile.go to send again\n",frame_cnt); + goto send_again; + } + +recv_again: + memset(buf, 0, 32); + length = recv(fd, buf, sizeof(buf), 0); + if(length < 0 ){ + printf("[%d] frame waiting for ok timeout,receive again.\n",frame_cnt); + goto recv_again; + } + + printf("receive buf[%s] length = %d\n",buf, length); + if(0 == strncmp(buf, "ok", length)) + { + try_times = 10; + printf("[%d]frame data send done.\n",frame_cnt); + frame_cnt++; + continue; + } + else + { + if(try_times > 0) + { + try_times--; + goto send_again; + } + else + { + printf("send frame[%d] 10 times failed.\n",frame_cnt); + ret = -1; + break; + } + } + } + + /* finally,crc check total bin file.*/ + if (ret == 0) + { + sleep(1); + printf("total send file length[%d] Bytes [%d] frames.\n",file_length,frame_cnt); + printf("now crc check total bin file.\n"); + file_buf = malloc(file_length); + memset(file_buf, 0, file_length); + memset(&data, 0, sizeof(data)); + + data.header.frame_flag = 0x5A5A; + + file_fd = fopen("/home/aep04/wwg/XiUOS_aiit-arm32-board_app.bin", "r"); + if (NULL == file_fd){ + printf("open file failed.\n"); + return -1; + } + fseek(file_fd, 0, SEEK_SET); + length = fread(file_buf,1, file_length, file_fd); + printf("read file length = %d\n",length); + if(length > 0) { + data.frame.frame_id = frame_cnt; + data.header.total_len = file_length; + data.frame.frame_len = strlen("aiit_ota_end"); + data.frame.crc = OtaCrc16(file_buf, length); + memcpy(data.frame.frame_data,"aiit_ota_end",strlen("aiit_ota_end")); + } + +send_end_signal: + printf("send aiit_ota_end signal.\n"); + length = send(fd, &data, sizeof(data), MSG_NOSIGNAL); + if(length < 0){ + printf("send end signal faile,send end signal again\n"); + goto send_end_signal; + } + +recv_end_signal: + memset(buf, 0, 32); + length = recv(fd, buf, sizeof(buf), 0); + if(length < 0 ) + { + recv_end_times--; + printf("end signal waiting for ok timeout,receive again.\n"); + if(recv_end_times > 0) + { + goto recv_end_signal; + } + else + { + ret = -1; + } + } + + if(0 != strncmp(buf, "ok", length)) + { + printf("error end !!!\n"); + ret = -1; + } + + free(file_buf); + } + + fclose(file_fd); + return ret; +} + +void* server_thread(void* p) +{ + int fd = *(int*)p; + unsigned char buf[32] = { 0 }; + struct ota_data data; + int ret = 0; + int length = 0; + + printf("pthread = %d\n",fd); + sleep(8); + while(1) + { + memset(&data, 0x0 , sizeof(struct ota_data)); + data.header.frame_flag = 0x5A5A; + memcpy(data.frame.frame_data,"aiit_ota_start",strlen("aiit_ota_start")); + data.frame.frame_len = strlen("aiit_ota_start"); + + printf("send start signal.\n"); + ret = send(fd, &data, sizeof(data), MSG_NOSIGNAL); + if (ret > 0){ + printf("send %s[%d] Bytes\n",data.frame.frame_data,ret); + } + // sleep(1); + memset(buf, 0, 32); + length = recv(fd, buf, sizeof(buf), 0); + if (length <= 0) + { + continue; + } + else + { + printf("recv buf %s length %d\n",buf,length); + if(0 == strncmp(buf, "ready", length)) + { + ret = OtaFileSend(fd); + if (ret == 0) { + printf("ota file send successful.\n"); + break; + } else { /* ota failed then restart the ota process */ + continue; + } + } + } + } + printf("exit fd = %d\n",fd); + close(fd); + pthread_exit(0); +} + +void server(void) +{ + printf("ota Server startup\n"); + while(1) + { + struct sockaddr_in fromaddr; + socklen_t len = sizeof(fromaddr); + int fd = accept(serverfd,(meng*)&fromaddr,&len); + +//调用accept进入堵塞状态，等待客户端的连接 + + if (fd == -1) + { + // printf("The client connection is wrong...\n"); + continue; + } + + int i = 0; + for (i = 0;i < size;i++) + { + if (clientfd[i] == 0) + { + //记录客户端的socket + clientfd[i] = fd; + + //有客户端连接之后，启动线程给此客户服务 + pthread_t tid; + pthread_create(&tid,0,server_thread,&fd); + break; + } + + if (size == i) + { + //发送给客户端说聊天室满了 + char* str = "Devices full"; + printf("%s", str); + send(fd,str,strlen(str),0); + close(fd); + } + } + } +} + +int main(void) +{ + init(); + server(); +} + diff --git a/APP_Framework/Applications/sensor_app/Kconfig b/APP_Framework/Applications/sensor_app/Kconfig new file mode 100755 index 0000000..fbab69a --- /dev/null +++ b/APP_Framework/Applications/sensor_app/Kconfig @@ -0,0 +1,161 @@ +menu "sensor app" + + menuconfig APPLICATION_SENSOR + bool "Using sensor apps" + default n + + if APPLICATION_SENSOR + menuconfig APPLICATION_SENSOR_HCHO + bool "Using sensor HCHO apps" + default n + + if APPLICATION_SENSOR_HCHO + config APPLICATION_SENSOR_HCHO_TB600B_WQ_HCHO1OS + bool "Using sensor TB600B_WQ_HCHO1OS apps" + default n + endif + + menuconfig APPLICATION_SENSOR_TVOC + bool "Using sensor TVOC apps" + default n + + if APPLICATION_SENSOR_TVOC + config APPLICATION_SENSOR_TVOC_TB600B_TVOC10 + bool "Using sensor TB600B_TVOC10 apps" + default n + endif + + menuconfig APPLICATION_SENSOR_IAQ + bool "Using sensor IAQ apps" + default n + + if APPLICATION_SENSOR_IAQ + config APPLICATION_SENSOR_IAQ_TB600B_IAQ10 + bool "Using sensor TB600B_IAQ10 apps" + default n + endif + + menuconfig APPLICATION_SENSOR_CH4 + bool "Using sensor CH4 apps" + default n + + if APPLICATION_SENSOR_CH4 + config APPLICATION_SENSOR_CH4_AS830 + bool "Using sensor AS830 apps" + default n + endif + + menuconfig APPLICATION_SENSOR_CO2 + bool "Using sensor CO2 apps" + default n + + if APPLICATION_SENSOR_CO2 + config APPLICATION_SENSOR_CO2_ZG09 + bool "Using sensor ZG09 apps" + default n + + config APPLICATION_SENSOR_CO2_G8S + bool "Using sensor G8S apps" + default n + endif + + menuconfig APPLICATION_SENSOR_PM1_0 + bool "Using sensor PM1.0 apps" + default n + + if APPLICATION_SENSOR_PM1_0 + config APPLICATION_SENSOR_PM1_0_PS5308 + bool "Using sensor PS5308 apps" + default n + endif + + menuconfig APPLICATION_SENSOR_PM2_5 + bool "Using sensor PM2.5 apps" + default n + + if APPLICATION_SENSOR_PM2_5 + config APPLICATION_SENSOR_PM2_5_PS5308 + bool "Using sensor PS5308 apps" + default n + endif + + menuconfig APPLICATION_SENSOR_PM10 + bool "Using sensor PM10 apps" + default n + + if APPLICATION_SENSOR_PM10 + config APPLICATION_SENSOR_PM10_PS5308 + bool "Using sensor PS5308 apps" + default n + endif + + menuconfig APPLICATION_SENSOR_VOICE + bool "Using sensor voice apps" + default n + + if APPLICATION_SENSOR_VOICE + config APPLICATION_SENSOR_VOICE_D124 + bool "Using sensor D124 apps" + default n + endif + + menuconfig APPLICATION_SENSOR_TEMPERATURE + bool "Using sensor temperature apps" + default n + + if APPLICATION_SENSOR_TEMPERATURE + config APPLICATION_SENSOR_TEMPERATURE_HS300X + bool "Using sensor HS300x apps" + default n + + if ADD_NUTTX_FETURES + endif + + endif + + menuconfig APPLICATION_SENSOR_HUMIDITY + bool "Using sensor humidity apps" + default n + + if APPLICATION_SENSOR_HUMIDITY + config APPLICATION_SENSOR_HUMIDITY_HS300X + bool "Using sensor HS300x apps" + default n + + if ADD_NUTTX_FETURES + endif + + endif + + menuconfig APPLICATION_SENSOR_WINDDIRECTION + bool "Using sensor wind direction apps" + default n + + if APPLICATION_SENSOR_WINDDIRECTION + config APPLICATION_SENSOR_WINDDIRECTION_QS_FX + bool "Using sensor QS-FX apps" + default n + endif + + menuconfig APPLICATION_SENSOR_WINDSPEED + bool "Using sensor wind speed apps" + default n + + if APPLICATION_SENSOR_WINDSPEED + config APPLICATION_SENSOR_WINDSPEED_QS_FS + bool "Using sensor QS-FS apps" + default n + endif + + menuconfig APPLICATION_SENSOR_ALTITUDE + bool "Using sensor altitude apps" + default n + + if APPLICATION_SENSOR_ALTITUDE + config APPLICATION_SENSOR_ALTITUDE_BMP180 + bool "Using sensor BMP180 apps" + default n + endif + endif + +endmenu diff --git a/APP_Framework/Applications/sensor_app/Make.defs b/APP_Framework/Applications/sensor_app/Make.defs new file mode 100644 index 0000000..be73b47 --- /dev/null +++ b/APP_Framework/Applications/sensor_app/Make.defs @@ -0,0 +1,6 @@ +############################################################################ +# APP_Framework/Applications/sensor_app/Make.defs +############################################################################ +ifneq ($(CONFIG_APPLICATION_SENSOR),) +CONFIGURED_APPS += $(APPDIR)/../../../APP_Framework/Applications/sensor_app +endif diff --git a/APP_Framework/Applications/sensor_app/Makefile b/APP_Framework/Applications/sensor_app/Makefile new file mode 100644 index 0000000..76fd4e1 --- /dev/null +++ b/APP_Framework/Applications/sensor_app/Makefile @@ -0,0 +1,127 @@ +include $(KERNEL_ROOT)/.config + +ifeq ($(CONFIG_ADD_NUTTX_FETURES),y) + include $(APPDIR)/Make.defs + + ifeq ($(CONFIG_APPLICATION_SENSOR_HCHO_TB600B_WQ_HCHO1OS), y) + CSRCS += hcho_tb600b_wq_hcho1os.c + endif + + ifeq ($(CONFIG_APPLICATION_SENSOR_TVOC_TB600B_TVOC10), y) + CSRCS += tvoc_tb600b_tvoc10.c + endif + + ifeq ($(CONFIG_APPLICATION_SENSOR_IAQ_TB600B_IAQ10), y) + CSRCS += iaq_tb600b_iaq10.c + endif + + ifeq ($(CONFIG_APPLICATION_SENSOR_CH4_AS830), y) + CSRCS += ch4_as830.c + endif + + ifeq ($(CONFIG_APPLICATION_SENSOR_CO2_ZG09), y) + CSRCS += co2_zg09.c + endif + + ifeq ($(CONFIG_APPLICATION_SENSOR_PM1_0_PS5308), y) + CSRCS += pm1_0_ps5308.c + endif + + ifeq ($(CONFIG_APPLICATION_SENSOR_PM2_5_PS5308), y) + CSRCS += pm2_5_ps5308.c + endif + + ifeq ($(CONFIG_APPLICATION_SENSOR_PM10_PS5308), y) + CSRCS += pm10_0_ps5308.c + endif + + ifeq ($(CONFIG_APPLICATION_SENSOR_VOICE_D124), y) + CSRCS += voice_d124.c + endif + + ifeq ($(CONFIG_APPLICATION_SENSOR_HUMIDITY_HS300X), y) + CSRCS += humidity_hs300x.c + endif + + ifeq ($(CONFIG_APPLICATION_SENSOR_TEMPERATURE_HS300X), y) + CSRCS += temperature_hs300x.c + endif + + ifeq ($(CONFIG_APPLICATION_SENSOR_WINDDIRECTION_QS_FX), y) + CSRCS += winddirection_qs_fx.c + endif + + ifeq ($(CONFIG_APPLICATION_SENSOR_WINDSPEED_QS_FS), y) + CSRCS += windspeed_qs_fs.c + endif + + include $(APPDIR)/Application.mk + +endif + +ifeq ($(CONFIG_ADD_XIZI_FETURES),y) + SRC_FILES := + + ifeq ($(CONFIG_APPLICATION_SENSOR_HCHO_TB600B_WQ_HCHO1OS), y) + SRC_FILES += hcho_tb600b_wq_hcho1os.c + endif + + ifeq ($(CONFIG_APPLICATION_SENSOR_TVOC_TB600B_TVOC10), y) + SRC_FILES += tvoc_tb600b_tvoc10.c + endif + + ifeq ($(CONFIG_APPLICATION_SENSOR_IAQ_TB600B_IAQ10), y) + SRC_FILES += iaq_tb600b_iaq10.c + endif + + ifeq ($(CONFIG_APPLICATION_SENSOR_CH4_AS830), y) + SRC_FILES += ch4_as830.c + endif + + ifeq ($(CONFIG_APPLICATION_SENSOR_CO2_ZG09), y) + SRC_FILES += co2_zg09.c + endif + + ifeq ($(CONFIG_APPLICATION_SENSOR_CO2_G8S), y) + SRC_FILES += co2_g8s.c + endif + + ifeq ($(CONFIG_APPLICATION_SENSOR_PM1_0_PS5308), y) + SRC_FILES += pm1_0_ps5308.c + endif + + ifeq ($(CONFIG_APPLICATION_SENSOR_PM2_5_PS5308), y) + SRC_FILES += pm2_5_ps5308.c + endif + + ifeq ($(CONFIG_APPLICATION_SENSOR_PM10_PS5308), y) + SRC_FILES += pm10_0_ps5308.c + endif + + ifeq ($(CONFIG_APPLICATION_SENSOR_VOICE_D124), y) + SRC_FILES += voice_d124.c + endif + + ifeq ($(CONFIG_APPLICATION_SENSOR_HUMIDITY_HS300X), y) + SRC_FILES += humidity_hs300x.c + endif + + ifeq ($(CONFIG_APPLICATION_SENSOR_TEMPERATURE_HS300X), y) + SRC_FILES += temperature_hs300x.c + endif + + ifeq ($(CONFIG_APPLICATION_SENSOR_WINDDIRECTION_QS_FX), y) + SRC_FILES += winddirection_qs_fx.c + endif + + ifeq ($(CONFIG_APPLICATION_SENSOR_WINDSPEED_QS_FS), y) + SRC_FILES += windspeed_qs_fs.c + endif + + ifeq ($(CONFIG_APPLICATION_SENSOR_ALTITUDE_BMP180), y) + SRC_FILES += altitude_bmp180.c + endif + + include $(KERNEL_ROOT)/compiler.mk + +endif diff --git a/APP_Framework/Applications/sensor_app/SConscript b/APP_Framework/Applications/sensor_app/SConscript new file mode 100644 index 0000000..d526a7b --- /dev/null +++ b/APP_Framework/Applications/sensor_app/SConscript @@ -0,0 +1,24 @@ +import os +from building import * +Import('RTT_ROOT') +Import('rtconfig') +cwd = GetCurrentDir() +DEPENDS = ["SUPPORT_SENSOR_FRAMEWORK"] +SOURCES = [] +if GetDepend(['APPLICATION_SENSOR_CO2_ZG09']): + SOURCES = ['co2_zg09.c'] + SOURCES +if GetDepend(['APPLICATION_SENSOR_PM1_0_PS5308']): + SOURCES = ['pm1_0_ps5308.c.c'] + SOURCES +if GetDepend(['APPLICATION_SENSOR_VOICE_D124']): + SOURCES = ['voice_d124.c'] + SOURCES +if GetDepend(['APPLICATION_SENSOR_HUMIDITY_HS300X']): + SOURCES = ['humidity_hs300x.c'] + SOURCES +if GetDepend(['APPLICATION_SENSOR_TEMPERATURE_HS300X']): + SOURCES = ['temperature_hs300x.c'] + SOURCES +if GetDepend(['APPLICATION_SENSOR_CH4_AS830']): + SOURCES = ['ch4_as830.c'] + SOURCES +if GetDepend(['APPLICATION_SENSOR_HCHO']): + SOURCES = ['hcho_tb600b_wq_hcho1os.c'] + SOURCES +path = [cwd] +objs = DefineGroup('sensor_app', src = SOURCES, depend = DEPENDS,CPPPATH = path) +Return("objs") \ No newline at end of file diff --git a/APP_Framework/Applications/sensor_app/altitude_bmp180.c b/APP_Framework/Applications/sensor_app/altitude_bmp180.c new file mode 100644 index 0000000..36fc811 --- /dev/null +++ b/APP_Framework/Applications/sensor_app/altitude_bmp180.c @@ -0,0 +1,39 @@ +/* +* Copyright (c) 2020 AIIT XUOS Lab +* XiUOS is licensed under Mulan PSL v2. +* You can use this software according to the terms and conditions of the Mulan PSL v2. +* You may obtain a copy of Mulan PSL v2 at: +* http://license.coscl.org.cn/MulanPSL2 +* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, +* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, +* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. +* See the Mulan PSL v2 for more details. +*/ + +/** + * @file altitude_bmp180.c + * @brief BMP180 altitude example + * @version 1.1 + * @author AIIT XUOS Lab + * @date 2021.12.23 + */ + +#include +#include + +/** + * @description: Read a altitude + * @return 0 + */ +void AltitudeBmp180(void) +{ + int32 altitude; + struct SensorQuantity *p_altitude = SensorQuantityFind(SENSOR_QUANTITY_BMP180_ALTITUDE, SENSOR_QUANTITY_ALTITUDE); + SensorQuantityOpen(p_altitude); + altitude = SensorQuantityRead(p_altitude); + + printf("Altitude Pressure : %d Pa\n", altitude); + + PrivTaskDelay(1000); + SensorQuantityClose(p_altitude); +} \ No newline at end of file diff --git a/APP_Framework/Applications/sensor_app/ch4_as830.c b/APP_Framework/Applications/sensor_app/ch4_as830.c new file mode 100644 index 0000000..b5b5e21 --- /dev/null +++ b/APP_Framework/Applications/sensor_app/ch4_as830.c @@ -0,0 +1,36 @@ +/* +* Copyright (c) 2020 AIIT XUOS Lab +* XiUOS is licensed under Mulan PSL v2. +* You can use this software according to the terms and conditions of the Mulan PSL v2. +* You may obtain a copy of Mulan PSL v2 at: +* http://license.coscl.org.cn/MulanPSL2 +* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, +* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, +* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. +* See the Mulan PSL v2 for more details. +*/ + +/** + * @file ch4_as830.c + * @brief CH4 AS830 example + * @version 1.0 + * @author AIIT XUOS Lab + * @date 2021.12.10 + */ + +#ifdef ADD_XIZI_FETURES +# include +#endif +#include + +/** + * @description: Read a ch4 + * @return 0 + */ +void Ch4As830(void) +{ + struct SensorQuantity *ch4 = SensorQuantityFind(SENSOR_QUANTITY_AS830_CH4, SENSOR_QUANTITY_CH4); + SensorQuantityOpen(ch4); + printf("CH4 : %d %%LTL\n", SensorQuantityRead(ch4)); + SensorQuantityClose(ch4); +} \ No newline at end of file diff --git a/APP_Framework/Applications/sensor_app/co2_g8s.c b/APP_Framework/Applications/sensor_app/co2_g8s.c new file mode 100644 index 0000000..684a63d --- /dev/null +++ b/APP_Framework/Applications/sensor_app/co2_g8s.c @@ -0,0 +1,34 @@ +/* +* Copyright (c) 2020 AIIT XUOS Lab +* XiUOS is licensed under Mulan PSL v2. +* You can use this software according to the terms and conditions of the Mulan PSL v2. +* You may obtain a copy of Mulan PSL v2 at: +* http://license.coscl.org.cn/MulanPSL2 +* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, +* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, +* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. +* See the Mulan PSL v2 for more details. +*/ + +/** + * @file co2_g8s.c + * @brief G8S CO2 example + * @version 1.1 + * @author AIIT XUOS Lab + * @date 2021.12.23 + */ + +#include +#include + +/** + * @description: Read a CO2 + * @return 0 + */ +void Co2G8s(void) +{ + struct SensorQuantity *co2 = SensorQuantityFind(SENSOR_QUANTITY_G8S_CO2, SENSOR_QUANTITY_CO2); + SensorQuantityOpen(co2); + printf("CO2 : %d ppm\n", SensorQuantityRead(co2)); + SensorQuantityClose(co2); +} \ No newline at end of file diff --git a/APP_Framework/Applications/sensor_app/co2_zg09.c b/APP_Framework/Applications/sensor_app/co2_zg09.c new file mode 100644 index 0000000..74e11d2 --- /dev/null +++ b/APP_Framework/Applications/sensor_app/co2_zg09.c @@ -0,0 +1,36 @@ +/* +* Copyright (c) 2020 AIIT XUOS Lab +* XiUOS is licensed under Mulan PSL v2. +* You can use this software according to the terms and conditions of the Mulan PSL v2. +* You may obtain a copy of Mulan PSL v2 at: +* http://license.coscl.org.cn/MulanPSL2 +* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, +* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, +* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. +* See the Mulan PSL v2 for more details. +*/ + +/** + * @file co2_zg09.c + * @brief ZG09 CO2 example + * @version 1.0 + * @author AIIT XUOS Lab + * @date 2021.04.23 + */ + +#ifdef ADD_XIZI_FETURES +# include +#endif +#include + +/** + * @description: Read a CO2 + * @return 0 + */ +void Co2Zg09(void) +{ + struct SensorQuantity *co2 = SensorQuantityFind(SENSOR_QUANTITY_ZG09_CO2, SENSOR_QUANTITY_CO2); + SensorQuantityOpen(co2); + printf("CO2 : %d ppm\n", SensorQuantityRead(co2)); + SensorQuantityClose(co2); +} \ No newline at end of file diff --git a/APP_Framework/Applications/sensor_app/hcho_tb600b_wq_hcho1os.c b/APP_Framework/Applications/sensor_app/hcho_tb600b_wq_hcho1os.c new file mode 100644 index 0000000..e0988ec --- /dev/null +++ b/APP_Framework/Applications/sensor_app/hcho_tb600b_wq_hcho1os.c @@ -0,0 +1,41 @@ +/* +* Copyright (c) 2020 AIIT XUOS Lab +* XiUOS is licensed under Mulan PSL v2. +* You can use this software according to the terms and conditions of the Mulan PSL v2. +* You may obtain a copy of Mulan PSL v2 at: +* http://license.coscl.org.cn/MulanPSL2 +* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, +* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, +* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. +* See the Mulan PSL v2 for more details. +*/ + +/** + * @file hcho_tb600b_wq_hcho1os.c + * @brief hcho example + * @version 1.0 + * @author AIIT XUOS Lab + * @date 2021.12.15 + */ + +#ifdef ADD_XIZI_FETURES +# include +#endif +#include + + +/** + * @description: Read a hcho + * @return 0 + */ +void HchoTb600bHcho1os(void) +{ + struct SensorQuantity *hcho = SensorQuantityFind(SENSOR_QUANTITY_TB600B_HCHO, SENSOR_QUANTITY_HCHO); + SensorQuantityOpen(hcho); + int32_t result = 0; + + result = SensorQuantityRead(hcho); + + printf("tvoc concentration is : %dppb\n", result); + SensorQuantityClose(hcho); +} \ No newline at end of file diff --git a/APP_Framework/Applications/sensor_app/humidity_hs300x.c b/APP_Framework/Applications/sensor_app/humidity_hs300x.c new file mode 100644 index 0000000..d582e39 --- /dev/null +++ b/APP_Framework/Applications/sensor_app/humidity_hs300x.c @@ -0,0 +1,43 @@ +/* +* Copyright (c) 2020 AIIT XUOS Lab +* XiUOS is licensed under Mulan PSL v2. +* You can use this software according to the terms and conditions of the Mulan PSL v2. +* You may obtain a copy of Mulan PSL v2 at: +* http://license.coscl.org.cn/MulanPSL2 +* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, +* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, +* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. +* See the Mulan PSL v2 for more details. +*/ + +/** + * @file humidity_hs300x.c + * @brief HS300x humidity example + * @version 1.0 + * @author AIIT XUOS Lab + * @date 2021.04.23 + */ + +#ifdef ADD_XIZI_FETURES +# include +#endif + +#include + +/** + * @description: Read a himidity + * @return 0 + */ +void HumiHs300x(void) +{ + int i = 0; + int32 humidity; + struct SensorQuantity *humi = SensorQuantityFind(SENSOR_QUANTITY_HS300X_HUMIDITY, SENSOR_QUANTITY_HUMI); + SensorQuantityOpen(humi); + for (i = 0; i < 100; i ++) { + humidity = SensorQuantityRead(humi); + printf("Humidity : %d.%d %%RH\n", humidity/10, humidity%10); + PrivTaskDelay(5000); + } + SensorQuantityClose(humi); +} \ No newline at end of file diff --git a/APP_Framework/Applications/sensor_app/iaq_tb600b_iaq10.c b/APP_Framework/Applications/sensor_app/iaq_tb600b_iaq10.c new file mode 100644 index 0000000..9f4a1dc --- /dev/null +++ b/APP_Framework/Applications/sensor_app/iaq_tb600b_iaq10.c @@ -0,0 +1,47 @@ +/* +* Copyright (c) 2020 AIIT XUOS Lab +* XiUOS is licensed under Mulan PSL v2. +* You can use this software according to the terms and conditions of the Mulan PSL v2. +* You may obtain a copy of Mulan PSL v2 at: +* http://license.coscl.org.cn/MulanPSL2 +* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, +* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, +* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. +* See the Mulan PSL v2 for more details. +*/ + +/** + * @file iaq_tb600b_iaq10.c + * @brief iaq10 example + * @version 1.0 + * @author AIIT XUOS Lab + * @date 2021.12.14 + */ + +#ifdef ADD_XIZI_FETURES +# include +#endif +#include + +// struct iaq_data { +// uint16_t gas; +// uint8_t TH; +// uint8_t TL; +// uint8_t RhH; +// uint8_t RhL; +// }; +/** + * @description: Read a iaq + * @return 0 + */ +void IaqTb600bIaq10(void) +{ + struct SensorQuantity *iaq = SensorQuantityFind(SENSOR_QUANTITY_TB600B_IAQ, SENSOR_QUANTITY_IAQ); + SensorQuantityOpen(iaq); + int32_t result = 0; + + result = SensorQuantityRead(iaq); + + printf("Gas concentration is : %dppb\n", result); + SensorQuantityClose(iaq); +} \ No newline at end of file diff --git a/APP_Framework/Applications/sensor_app/pm10_0_ps5308.c b/APP_Framework/Applications/sensor_app/pm10_0_ps5308.c new file mode 100644 index 0000000..5d64088 --- /dev/null +++ b/APP_Framework/Applications/sensor_app/pm10_0_ps5308.c @@ -0,0 +1,38 @@ +/* +* Copyright (c) 2020 AIIT XUOS Lab +* XiOS is licensed under Mulan PSL v2. +* You can use this software according to the terms and conditions of the Mulan PSL v2. +* You may obtain a copy of Mulan PSL v2 at: +* http://license.coscl.org.cn/MulanPSL2 +* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, +* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, +* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. +* See the Mulan PSL v2 for more details. +*/ + +/** + * @file pm10_0_ps5308.c + * @brief PS5308 PM10.0 example + * @version 1.0 + * @author AIIT XUOS Lab + * @date 2021.04.23 + */ + +#ifdef ADD_XIZI_FETURES +# include +#endif + +#include + +/** + * @description: Read a PM10 + * @return 0 + */ +void Pm100Ps5308(void) +{ + struct SensorQuantity *pm10_0 = SensorQuantityFind(SENSOR_QUANTITY_PS5308_PM10, SENSOR_QUANTITY_PM); + SensorQuantityOpen(pm10_0); + PrivTaskDelay(2000); + printf("PM10 : %d ug/m³\n", SensorQuantityRead(pm10_0)); + SensorQuantityClose(pm10_0); +} \ No newline at end of file diff --git a/APP_Framework/Applications/sensor_app/pm1_0_ps5308.c b/APP_Framework/Applications/sensor_app/pm1_0_ps5308.c new file mode 100644 index 0000000..e0c8068 --- /dev/null +++ b/APP_Framework/Applications/sensor_app/pm1_0_ps5308.c @@ -0,0 +1,38 @@ +/* +* Copyright (c) 2020 AIIT XUOS Lab +* XiOS is licensed under Mulan PSL v2. +* You can use this software according to the terms and conditions of the Mulan PSL v2. +* You may obtain a copy of Mulan PSL v2 at: +* http://license.coscl.org.cn/MulanPSL2 +* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, +* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, +* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. +* See the Mulan PSL v2 for more details. +*/ + +/** + * @file pm1_0_ps5308.c + * @brief PS5308 PM1.0 example + * @version 1.0 + * @author AIIT XUOS Lab + * @date 2021.04.23 + */ + +#ifdef ADD_XIZI_FETURES +# include +#endif + +#include + +/** + * @description: Read a PM1.0 + * @return 0 + */ +void Pm10Ps5308(void) +{ + struct SensorQuantity *pm1_0 = SensorQuantityFind(SENSOR_QUANTITY_PS5308_PM1_0, SENSOR_QUANTITY_PM); + SensorQuantityOpen(pm1_0); + PrivTaskDelay(2000); + printf("PM1.0 : %d ug/m³\n", SensorQuantityRead(pm1_0)); + SensorQuantityClose(pm1_0); +} \ No newline at end of file diff --git a/APP_Framework/Applications/sensor_app/pm2_5_ps5308.c b/APP_Framework/Applications/sensor_app/pm2_5_ps5308.c new file mode 100644 index 0000000..23aaca5 --- /dev/null +++ b/APP_Framework/Applications/sensor_app/pm2_5_ps5308.c @@ -0,0 +1,38 @@ +/* +* Copyright (c) 2020 AIIT XUOS Lab +* XiOS is licensed under Mulan PSL v2. +* You can use this software according to the terms and conditions of the Mulan PSL v2. +* You may obtain a copy of Mulan PSL v2 at: +* http://license.coscl.org.cn/MulanPSL2 +* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, +* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, +* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. +* See the Mulan PSL v2 for more details. +*/ + +/** + * @file pm2_5_ps5308.c + * @brief PS5308 PM2.5 example + * @version 1.0 + * @author AIIT XUOS Lab + * @date 2021.12.28 + */ + +#ifdef ADD_XIZI_FETURES +# include +#endif + +#include + +/** + * @description: Read a PM2.5 + * @return 0 + */ +void Pm25Ps5308(void) +{ + struct SensorQuantity *pm2_5 = SensorQuantityFind(SENSOR_QUANTITY_PS5308_PM2_5, SENSOR_QUANTITY_PM); + SensorQuantityOpen(pm2_5); + PrivTaskDelay(2000); + printf("PM2.5 : %d ug/m³\n", SensorQuantityRead(pm2_5)); + SensorQuantityClose(pm2_5); +} \ No newline at end of file diff --git a/APP_Framework/Applications/sensor_app/temperature_hs300x.c b/APP_Framework/Applications/sensor_app/temperature_hs300x.c new file mode 100644 index 0000000..f6e4614 --- /dev/null +++ b/APP_Framework/Applications/sensor_app/temperature_hs300x.c @@ -0,0 +1,48 @@ +/* +* Copyright (c) 2020 AIIT XUOS Lab +* XiUOS is licensed under Mulan PSL v2. +* You can use this software according to the terms and conditions of the Mulan PSL v2. +* You may obtain a copy of Mulan PSL v2 at: +* http://license.coscl.org.cn/MulanPSL2 +* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, +* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, +* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. +* See the Mulan PSL v2 for more details. +*/ + +/** + * @file temperature_hs300x.c + * @brief HS300x temperature example + * @version 1.0 + * @author AIIT XUOS Lab + * @date 2021.04.23 + */ + +#ifdef ADD_XIZI_FETURES +# include +#endif + +#include + +/** + * @description: Read a temperature + * @return 0 + */ +void TempHs300x(void) +{ + int i = 0; + int32 temperature; + struct SensorQuantity *temp = SensorQuantityFind(SENSOR_QUANTITY_HS300X_TEMPERATURE, SENSOR_QUANTITY_TEMP); + SensorQuantityOpen(temp); + for (i = 0; i < 100; i ++) { + temperature = SensorQuantityRead(temp); + if (temperature > 0) + printf("Temperature : %d.%d ℃\n", temperature/10, temperature%10); + else + printf("Temperature : %d.%d ℃\n", temperature/10, -temperature%10); + + PrivTaskDelay(5000); + } + + SensorQuantityClose(temp); +} diff --git a/APP_Framework/Applications/sensor_app/tvoc_tb600b_tvoc10.c b/APP_Framework/Applications/sensor_app/tvoc_tb600b_tvoc10.c new file mode 100644 index 0000000..81cb965 --- /dev/null +++ b/APP_Framework/Applications/sensor_app/tvoc_tb600b_tvoc10.c @@ -0,0 +1,41 @@ +/* +* Copyright (c) 2020 AIIT XUOS Lab +* XiUOS is licensed under Mulan PSL v2. +* You can use this software according to the terms and conditions of the Mulan PSL v2. +* You may obtain a copy of Mulan PSL v2 at: +* http://license.coscl.org.cn/MulanPSL2 +* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, +* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, +* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. +* See the Mulan PSL v2 for more details. +*/ + +/** + * @file tvoc_tb600b_tvoc10.c + * @brief tvoc10 example + * @version 1.0 + * @author AIIT XUOS Lab + * @date 2021.12.15 + */ + +#ifdef ADD_XIZI_FETURES +# include +#endif +#include + + +/** + * @description: Read a tvoc + * @return 0 + */ +void TvocTb600bTvoc10(void) +{ + struct SensorQuantity *tvoc = SensorQuantityFind(SENSOR_QUANTITY_TB600B_TVOC, SENSOR_QUANTITY_TVOC); + SensorQuantityOpen(tvoc); + int32_t result = 0; + + result = SensorQuantityRead(tvoc); + + printf("tvoc concentration is : %dppb\n", result); + SensorQuantityClose(tvoc); +} \ No newline at end of file diff --git a/APP_Framework/Applications/sensor_app/voice_d124.c b/APP_Framework/Applications/sensor_app/voice_d124.c new file mode 100644 index 0000000..b86bf23 --- /dev/null +++ b/APP_Framework/Applications/sensor_app/voice_d124.c @@ -0,0 +1,36 @@ +/* +* Copyright (c) 2020 AIIT XUOS Lab +* XiOS is licensed under Mulan PSL v2. +* You can use this software according to the terms and conditions of the Mulan PSL v2. +* You may obtain a copy of Mulan PSL v2 at: +* http://license.coscl.org.cn/MulanPSL2 +* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, +* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, +* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. +* See the Mulan PSL v2 for more details. +*/ + +/** + * @file voice_d124.c + * @brief D124 voice example + * @version 1.0 + * @author AIIT XUOS Lab + * @date 2021.04.23 + */ + +#include +#include + +/** + * @description: Read a voice + * @return 0 + */ +void VoiceD124(void) +{ + struct SensorQuantity *voice = SensorQuantityFind(SENSOR_QUANTITY_D124_VOICE, SENSOR_QUANTITY_VOICE); + SensorQuantityOpen(voice); + PrivTaskDelay(2000); + uint16 result = SensorQuantityRead(voice); + printf("voice : %d.%d dB\n", result/(10*voice->value.decimal_places), result%(10*voice->value.decimal_places)); + SensorQuantityClose(voice); +} \ No newline at end of file diff --git a/APP_Framework/Applications/sensor_app/winddirection_qs_fx.c b/APP_Framework/Applications/sensor_app/winddirection_qs_fx.c new file mode 100644 index 0000000..d503271 --- /dev/null +++ b/APP_Framework/Applications/sensor_app/winddirection_qs_fx.c @@ -0,0 +1,40 @@ +/* +* Copyright (c) 2020 AIIT XUOS Lab +* XiOS is licensed under Mulan PSL v2. +* You can use this software according to the terms and conditions of the Mulan PSL v2. +* You may obtain a copy of Mulan PSL v2 at: +* http://license.coscl.org.cn/MulanPSL2 +* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, +* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, +* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. +* See the Mulan PSL v2 for more details. +*/ + +/** + * @file winddirection_qs_fx.c + * @brief qs-fx wind direction example + * @version 1.1 + * @author AIIT XUOS Lab + * @date 2021.12.14 + */ + +#include +#include + +/** + * @description: Read a wind direction + * @return 0 + */ +void WindDirectionQsFx(void) +{ + struct SensorQuantity *wind_direction = SensorQuantityFind(SENSOR_QUANTITY_QS_FX_WINDDIRECTION, SENSOR_QUANTITY_WINDDIRECTION); + SensorQuantityOpen(wind_direction); + PrivTaskDelay(2000); + uint16 result = SensorQuantityRead(wind_direction); + printf("wind direction : %d degree\n", result); + SensorQuantityClose(wind_direction); +} +#ifdef ADD_XIZI_FETURES +SHELL_EXPORT_CMD(SHELL_CMD_PERMISSION(0)|SHELL_CMD_TYPE(SHELL_TYPE_CMD_FUNC)|SHELL_CMD_PARAM_NUM(0)|SHELL_CMD_DISABLE_RETURN, WindDirectionQsFx, WindDirectionQsFx, WindDirectionQsFx function); +#endif + diff --git a/APP_Framework/Applications/sensor_app/windspeed_qs_fs.c b/APP_Framework/Applications/sensor_app/windspeed_qs_fs.c new file mode 100644 index 0000000..72b91db --- /dev/null +++ b/APP_Framework/Applications/sensor_app/windspeed_qs_fs.c @@ -0,0 +1,40 @@ +/* +* Copyright (c) 2020 AIIT XUOS Lab +* XiOS is licensed under Mulan PSL v2. +* You can use this software according to the terms and conditions of the Mulan PSL v2. +* You may obtain a copy of Mulan PSL v2 at: +* http://license.coscl.org.cn/MulanPSL2 +* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, +* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, +* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. +* See the Mulan PSL v2 for more details. +*/ + +/** + * @file windspeed_qs_fs.c + * @brief qs-fx wind direction example + * @version 1.1 + * @author AIIT XUOS Lab + * @date 2021.12.14 + */ + +#include +#include + +/** + * @description: Read a wind speed + * @return 0 + */ +void WindSpeedQsFs(void) +{ + struct SensorQuantity *wind_speed = SensorQuantityFind(SENSOR_QUANTITY_QS_FS_WINDSPEED, SENSOR_QUANTITY_WINDSPEED); + SensorQuantityOpen(wind_speed); + PrivTaskDelay(2000); + uint16 result = SensorQuantityRead(wind_speed); + printf("wind speed : %d.%d m/s\n", result/10, result%10); + SensorQuantityClose(wind_speed); +} +#ifdef ADD_XIZI_FETURES +SHELL_EXPORT_CMD(SHELL_CMD_PERMISSION(0)|SHELL_CMD_TYPE(SHELL_TYPE_CMD_FUNC)|SHELL_CMD_PARAM_NUM(0)|SHELL_CMD_DISABLE_RETURN, WindSpeedQsFs, WindSpeedQsFs, WindSpeedQsFs function); +#endif + diff --git a/APP_Framework/Framework/Kconfig b/APP_Framework/Framework/Kconfig new file mode 100644 index 0000000..7934d20 --- /dev/null +++ b/APP_Framework/Framework/Kconfig @@ -0,0 +1,28 @@ +menu "Framework" + + config TRANSFORM_LAYER_ATTRIUBUTE + bool "support transform layer" + default y + choice + prompt "select os features" + default ADD_XIZI_FETURES + + config ADD_XIZI_FETURES + bool "add xizi fetures" + + config ADD_NUTTX_FETURES + bool "add nuttx fetures" + + config ADD_RTTHREAD_FETURES + bool "add rt_thread fetures" + endchoice + + + source "$APP_DIR/Framework/sensor/Kconfig" + source "$APP_DIR/Framework/connection/Kconfig" + source "$APP_DIR/Framework/knowing/Kconfig" + source "$APP_DIR/Framework/control/Kconfig" + source "$APP_DIR/Framework/security/Kconfig" + + +endmenu diff --git a/APP_Framework/Framework/Make.defs b/APP_Framework/Framework/Make.defs new file mode 100644 index 0000000..40d65f3 --- /dev/null +++ b/APP_Framework/Framework/Make.defs @@ -0,0 +1,5 @@ +############################################################################ +# APP_Framework/Framework/Make.defs +############################################################################ +CONFIGURED_APPS += $(APPDIR)/../../../APP_Framework/Framework/transform_layer/nuttx +include $(wildcard $(APPDIR)/../../../APP_Framework/Framework/*/Make.defs) diff --git a/APP_Framework/Framework/Makefile b/APP_Framework/Framework/Makefile new file mode 100644 index 0000000..a095e8a --- /dev/null +++ b/APP_Framework/Framework/Makefile @@ -0,0 +1,24 @@ +SRC_DIR := transform_layer + +ifeq ($(CONFIG_SUPPORT_SENSOR_FRAMEWORK),y) + SRC_DIR += sensor +endif + +ifeq ($(CONFIG_SUPPORT_CONNECTION_FRAMEWORK),y) + SRC_DIR += connection +endif + +ifeq ($(CONFIG_SUPPORT_KNOWING_FRAMEWORK),y) + SRC_DIR += knowing +endif + +ifeq ($(CONFIG_SUPPORT_CONTROL_FRAMEWORK),y) + SRC_DIR += control +endif + +ifeq ($(CONFIG_CRYPTO),y) + SRC_DIR += security +endif + +include $(KERNEL_ROOT)/compiler.mk + diff --git a/APP_Framework/Framework/SConscript b/APP_Framework/Framework/SConscript new file mode 100644 index 0000000..f307e3f --- /dev/null +++ b/APP_Framework/Framework/SConscript @@ -0,0 +1,14 @@ +import os +Import('RTT_ROOT') +from building import * + +cwd = GetCurrentDir() +objs = [] +list = os.listdir(cwd) + +for d in list: + path = os.path.join(cwd, d) + if os.path.isfile(os.path.join(path, 'SConscript')): + objs = objs + SConscript(os.path.join(path, 'SConscript')) + +Return('objs') diff --git a/APP_Framework/Framework/connection/4g/Kconfig b/APP_Framework/Framework/connection/4g/Kconfig new file mode 100644 index 0000000..17e05a9 --- /dev/null +++ b/APP_Framework/Framework/connection/4g/Kconfig @@ -0,0 +1,8 @@ +config ADAPTER_EC200T + bool "Using 4G adapter device EC200T" + default y + +if ADAPTER_EC200T + source "$APP_DIR/Framework/connection/4g/ec200t/Kconfig" +endif + diff --git a/APP_Framework/Framework/connection/4g/Make.defs b/APP_Framework/Framework/connection/4g/Make.defs new file mode 100644 index 0000000..c355d00 --- /dev/null +++ b/APP_Framework/Framework/connection/4g/Make.defs @@ -0,0 +1,7 @@ +############################################################################ +# APP_Framework/Framework/connection/4g/Make.defs +############################################################################ +ifneq ($(CONFIG_CONNECTION_ADAPTER_4G),) +CONFIGURED_APPS += $(APPDIR)/../../../APP_Framework/Framework/connection/4g +endif +include $(wildcard $(APPDIR)/../../../APP_Framework/Framework/connection/4g/*/Make.defs) diff --git a/APP_Framework/Framework/connection/4g/Makefile b/APP_Framework/Framework/connection/4g/Makefile new file mode 100644 index 0000000..f5c4a13 --- /dev/null +++ b/APP_Framework/Framework/connection/4g/Makefile @@ -0,0 +1,17 @@ +include $(KERNEL_ROOT)/.config +ifeq ($(CONFIG_ADD_NUTTX_FETURES),y) + include $(APPDIR)/Make.defs + CSRCS += adapter_4g.c + include $(APPDIR)/Application.mk + +endif + +ifeq ($(CONFIG_ADD_XIZI_FETURES),y) + SRC_FILES := adapter_4g.c + + ifeq ($(CONFIG_ADAPTER_EC200T),y) + SRC_DIR += ec200t + endif + + include $(KERNEL_ROOT)/compiler.mk +endif \ No newline at end of file diff --git a/APP_Framework/Framework/connection/4g/adapter_4g.c b/APP_Framework/Framework/connection/4g/adapter_4g.c new file mode 100644 index 0000000..9877e10 --- /dev/null +++ b/APP_Framework/Framework/connection/4g/adapter_4g.c @@ -0,0 +1,113 @@ +/* +* Copyright (c) 2020 AIIT XUOS Lab +* XiUOS is licensed under Mulan PSL v2. +* You can use this software according to the terms and conditions of the Mulan PSL v2. +* You may obtain a copy of Mulan PSL v2 at: +* http://license.coscl.org.cn/MulanPSL2 +* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, +* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, +* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. +* See the Mulan PSL v2 for more details. +*/ + +/** + * @file adapter_4G.c + * @brief Implement the connection 4G adapter function + * @version 1.1 + * @author AIIT XUOS Lab + * @date 2021.06.25 + */ + +#include + +#ifdef ADAPTER_EC200T +extern AdapterProductInfoType Ec200tAttach(struct Adapter *adapter); +#endif + +static int Adapter4GRegister(struct Adapter *adapter) +{ + int ret = 0; + + strncpy(adapter->name, ADAPTER_4G_NAME, NAME_NUM_MAX); + + adapter->net_protocol = IP_PROTOCOL; + adapter->net_role = CLIENT; + adapter->adapter_status = UNREGISTERED; + + ret = AdapterDeviceRegister(adapter); + if (ret < 0) { + printf("Adapter4G register error\n"); + return -1; + } + + return ret; +} + +int Adapter4GInit(void) +{ + int ret = 0; + + struct Adapter *adapter = PrivMalloc(sizeof(struct Adapter)); + if (!adapter) { + PrivFree(adapter); + return -1; + } + + memset(adapter, 0, sizeof(struct Adapter)); + + ret = Adapter4GRegister(adapter); + if (ret < 0) { + printf("Adapter4GInit register 4G adapter error\n"); + PrivFree(adapter); + return -1; + } + +#ifdef ADAPTER_EC200T + AdapterProductInfoType product_info = Ec200tAttach(adapter); + if (!product_info) { + printf("Adapter4GInit ec200t attach error\n"); + PrivFree(adapter); + return -1; + } + + adapter->product_info_flag = 1; + adapter->info = product_info; + adapter->done = product_info->model_done; + +#endif + + return ret; +} + +/******************4G TEST*********************/ +int Adapter4GTest(void) +{ + const char *send_msg = "Adapter_4G Test"; + char recv_msg[256] = {0}; + int baud_rate = BAUD_RATE_115200; + + struct Adapter* adapter = AdapterDeviceFindByName(ADAPTER_4G_NAME); + +#ifdef ADAPTER_EC200T + //Using Hang Xiao server to test 4G Socket connection + uint8 server_addr[64] = "120.76.100.197"; + uint8 server_port[64] = "10002"; + + adapter->socket.socket_id = 0; + + AdapterDeviceOpen(adapter); + AdapterDeviceControl(adapter, OPE_INT, &baud_rate); + + AdapterDeviceConnect(adapter, CLIENT, server_addr, server_port, IPV4); + + while (1) { + AdapterDeviceSend(adapter, send_msg, strlen(send_msg)); + AdapterDeviceRecv(adapter, recv_msg, 256); + printf("4G recv msg %s\n", recv_msg); + memset(recv_msg, 0, 256); + } +#endif + + return 0; +} +// SHELL_EXPORT_CMD(SHELL_CMD_PERMISSION(0)|SHELL_CMD_TYPE(SHELL_TYPE_CMD_FUNC)|SHELL_CMD_PARAM_NUM(0)|SHELL_CMD_DISABLE_RETURN, Adapter4GTest, Adapter4GTest, show adapter 4G information); diff --git a/APP_Framework/Framework/connection/4g/ec200t/Kconfig b/APP_Framework/Framework/connection/4g/ec200t/Kconfig new file mode 100644 index 0000000..71f692f --- /dev/null +++ b/APP_Framework/Framework/connection/4g/ec200t/Kconfig @@ -0,0 +1,43 @@ +config ADAPTER_4G_EC200T + string "EC200T adapter name" + default "ec200t" + +if ADD_XIZI_FETURES + config ADAPTER_EC200T_PWRKEY + int "EC200T PWRKEY pin number" + default "97" + + config ADAPTER_EC200T_PIN_DRIVER + string "EC200T device pin driver path" + default "/dev/pin_dev" + + config ADAPTER_EC200T_DRIVER_EXTUART + bool "Using extra uart to support 4G" + default n + + config ADAPTER_EC200T_DRIVER + string "EC200T device uart driver path" + default "/dev/usart2_dev2" + depends on !ADAPTER_EC200T_DRIVER_EXTUART + + if ADAPTER_EC200T_DRIVER_EXTUART + config ADAPTER_EC200T_DRIVER + string "EC200T device extra uart driver path" + default "/dev/extuart_dev5" + + config ADAPTER_EC200T_DRIVER_EXT_PORT + int "if EC200T device using extuart, choose port" + default "5" + endif +endif + +if ADD_NUTTX_FETURES + config ADAPTER_EC200T_DRIVER + string "EC200T device uart driver path" + default "/dev/ttyS8" + +endif + +if ADD_RTTHREAD_FETURES + +endif diff --git a/APP_Framework/Framework/connection/4g/ec200t/Make.defs b/APP_Framework/Framework/connection/4g/ec200t/Make.defs new file mode 100644 index 0000000..3bc3ea8 --- /dev/null +++ b/APP_Framework/Framework/connection/4g/ec200t/Make.defs @@ -0,0 +1,6 @@ +############################################################################ +# APP_Framework/Framework/connection/4g/ec200t/Make.defs +############################################################################ +ifneq ($(CONFIG_ADAPTER_4G_EC200T),) +CONFIGURED_APPS += $(APPDIR)/../../../APP_Framework/Framework/connection/4g/ec200t +endif diff --git a/APP_Framework/Framework/connection/4g/ec200t/Makefile b/APP_Framework/Framework/connection/4g/ec200t/Makefile new file mode 100644 index 0000000..5b2bff1 --- /dev/null +++ b/APP_Framework/Framework/connection/4g/ec200t/Makefile @@ -0,0 +1,14 @@ +include $(KERNEL_ROOT)/.config +ifeq ($(CONFIG_ADD_NUTTX_FETURES),y) + include $(APPDIR)/Make.defs + CSRCS += ec200t.c + include $(APPDIR)/Application.mk + +endif + +ifeq ($(CONFIG_ADD_XIZI_FETURES),y) + SRC_FILES := ec200t.c + + include $(KERNEL_ROOT)/compiler.mk + +endif diff --git a/APP_Framework/Framework/connection/4g/ec200t/ec200t.c b/APP_Framework/Framework/connection/4g/ec200t/ec200t.c new file mode 100644 index 0000000..cdf5570 --- /dev/null +++ b/APP_Framework/Framework/connection/4g/ec200t/ec200t.c @@ -0,0 +1,395 @@ +/* +* Copyright (c) 2020 AIIT XUOS Lab +* XiUOS is licensed under Mulan PSL v2. +* You can use this software according to the terms and conditions of the Mulan PSL v2. +* You may obtain a copy of Mulan PSL v2 at: +* http://license.coscl.org.cn/MulanPSL2 +* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, +* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, +* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. +* See the Mulan PSL v2 for more details. +*/ + +/** + * @file ec200t.c + * @brief Implement the connection 4G adapter function, using EC200T device + * @version 1.1 + * @author AIIT XUOS Lab + * @date 2021.07.08 + */ + +#include +#include + +#define EC200T_AT_MODE_CMD "+++" +#define EC200T_GET_CCID_CMD "AT+CCID\r\n" +#define EC200T_GET_CPIN_CMD "AT+CPIN?\r\n" +#define EC200T_GET_CREG_CMD "AT+CREG?\r\n" +#define EC200T_OPEN_SOCKET_CMD "AT+QIOPEN=1,%u" +#define EC200T_CLOSE_SOCKET_CMD "AT+QICLOSE=%u\r\n" +#define EC200T_ACTIVE_PDP_CMD "AT+QIACT=1\r\n" +#define EC200T_DEACTIVE_PDP_CMD "AT+QIDEACT=1\r\n" +#define EC200T_CFG_TCP_CMD "AT+QICSGP" + +#define EC200T_OK_REPLY "OK" +#define EC200T_READY_REPLY "READY" +#define EC200T_CREG_REPLY ",1" +#define EC200T_CONNECT_REPLY "CONNECT" + +#define TRY_TIMES 10 + +#ifdef ADD_NUTTX_FETURES +static void Ec200tPowerSet(void){ return; } +#else +static void Ec200tPowerSet(void) +{ + int pin_fd; + pin_fd = PrivOpen(ADAPTER_EC200T_PIN_DRIVER, O_RDWR); + if (pin_fd < 0) { + printf("open %s error\n", ADAPTER_EC200T_PIN_DRIVER); + return; + } + + struct PinParam pin_param; + pin_param.cmd = GPIO_CONFIG_MODE; + pin_param.mode = GPIO_CFG_OUTPUT; + pin_param.pin = ADAPTER_EC200T_PWRKEY; + + struct PrivIoctlCfg ioctl_cfg; + ioctl_cfg.ioctl_driver_type = PIN_TYPE; + ioctl_cfg.args = &pin_param; + PrivIoctl(pin_fd, OPE_CFG, &ioctl_cfg); + + struct PinStat pin_stat; + pin_stat.pin = ADAPTER_EC200T_PWRKEY; + pin_stat.val = GPIO_HIGH; + PrivWrite(pin_fd, &pin_stat, 1); + + PrivTaskDelay(600);//at least 500ms + + pin_stat.val = GPIO_LOW; + PrivWrite(pin_fd, &pin_stat, 1); + + PrivClose(pin_fd); + + PrivTaskDelay(10000); +} +#endif + +static int Ec200tOpen(struct Adapter *adapter) +{ + /*step1: open ec200t serial port*/ + adapter->fd = PrivOpen(ADAPTER_EC200T_DRIVER, O_RDWR); + if (adapter->fd < 0) { + printf("Ec200tOpen get serial %s fd error\n", ADAPTER_EC200T_DRIVER); + return -1; + } + + /*step2: init AT agent*/ + if (!adapter->agent) { + char *agent_name = "4G_uart_client"; + if (0 != InitATAgent(agent_name, adapter->fd, 512)) { + printf("at agent init failed !\n"); + return -1; + } + ATAgentType at_agent = GetATAgent(agent_name); + + adapter->agent = at_agent; + } + + PrivTaskDelay(2500); + + ADAPTER_DEBUG("Ec200t open done\n"); + + return 0; +} + +static int Ec200tClose(struct Adapter *adapter) +{ + int ret = 0; + uint8_t ec200t_cmd[64]; + + if (!adapter->agent) { + printf("Ec200tClose AT agent NULL\n"); + return -1; + } + + AtSetReplyEndChar(adapter->agent, 0x4F, 0x4B); + + /*step1: serial write "+++", quit transparent mode*/ + ATOrderSend(adapter->agent, REPLY_TIME_OUT, NULL, "+++"); + + /*step2: serial write "AT+QICLOSE", close socket connect before open socket*/ + memset(ec200t_cmd, 0, sizeof(ec200t_cmd)); + sprintf(ec200t_cmd, EC200T_CLOSE_SOCKET_CMD, adapter->socket.socket_id); + + ret = AtCmdConfigAndCheck(adapter->agent, ec200t_cmd, EC200T_OK_REPLY); + if (ret < 0) { + goto out; + } + + /*step3: serial write "AT+QIDEACT", close TCP net before open socket*/ + ret = AtCmdConfigAndCheck(adapter->agent, EC200T_DEACTIVE_PDP_CMD, EC200T_OK_REPLY); + if (ret < 0) { + goto out; + } + +out: + /*step4: close ec200t serial port*/ + PrivClose(adapter->fd); + + /*step5: power down ec200t*/ + Ec200tPowerSet(); + + return ret; +} + + +#ifdef ADD_NUTTX_FETURES +static int Ec200tIoctl(struct Adapter *adapter, int cmd, void *args){ return 0;} +#else +static int Ec200tIoctl(struct Adapter *adapter, int cmd, void *args) +{ + if (OPE_INT != cmd) { + printf("Ec200tIoctl only support OPE_INT, do not support %d\n", cmd); + return -1; + } + + uint32_t baud_rate = *((uint32_t *)args); + + struct SerialDataCfg serial_cfg; + memset(&serial_cfg, 0 ,sizeof(struct SerialDataCfg)); + serial_cfg.serial_baud_rate = baud_rate; + serial_cfg.serial_data_bits = DATA_BITS_8; + serial_cfg.serial_stop_bits = STOP_BITS_1; + serial_cfg.serial_buffer_size = SERIAL_RB_BUFSZ; + serial_cfg.serial_parity_mode = PARITY_NONE; + serial_cfg.serial_bit_order = STOP_BITS_1; + serial_cfg.serial_invert_mode = NRZ_NORMAL; +#ifdef ADAPTER_EC200T_DRIVER_EXT_PORT + serial_cfg.ext_uart_no = ADAPTER_EC200T_DRIVER_EXT_PORT; + serial_cfg.port_configure = PORT_CFG_INIT; +#endif + + struct PrivIoctlCfg ioctl_cfg; + ioctl_cfg.ioctl_driver_type = SERIAL_TYPE; + ioctl_cfg.args = &serial_cfg; + PrivIoctl(adapter->fd, OPE_INT, &ioctl_cfg); + + Ec200tPowerSet(); + + return 0; +} +#endif + +static int Ec200tConnect(struct Adapter *adapter, enum NetRoleType net_role, const char *ip, const char *port, enum IpType ip_type) +{ + int ret = 0; + int try = 0; + uint8_t ec200t_cmd[64]; + + AtSetReplyEndChar(adapter->agent, 0x4F, 0x4B); + + /*step1: serial write "+++", quit transparent mode*/ + ATOrderSend(adapter->agent, REPLY_TIME_OUT, NULL, "+++"); + + /*step2: serial write "AT+CCID", get SIM ID*/ + for(try = 0; try < TRY_TIMES; try++){ + ret = AtCmdConfigAndCheck(adapter->agent, EC200T_GET_CCID_CMD, EC200T_OK_REPLY); + if (ret == 0) { + break; + } + } + if (ret < 0) { + goto out; + } + + /*step3: serial write "AT+CPIN?", check SIM status*/ + for(try = 0; try < TRY_TIMES; try++){ + ret = AtCmdConfigAndCheck(adapter->agent, EC200T_GET_CPIN_CMD, EC200T_READY_REPLY); + if (ret == 0) { + break; + } + } + if (ret < 0) { + goto out; + } + + /*step4: serial write "AT+CREG?", check whether registered to GSM net*/ + for(try = 0; try < TRY_TIMES; try++){ + ret = AtCmdConfigAndCheck(adapter->agent, EC200T_GET_CREG_CMD, EC200T_CREG_REPLY); + if (ret == 0) { + break; + } + } + if (ret < 0) { + goto out; + } + + /*step5: serial write "AT+QICSGP", connect to China Mobile using ipv4 or ipv6*/ + memset(ec200t_cmd, 0, sizeof(ec200t_cmd)); + + if (IPV4 == ip_type) { + strcpy(ec200t_cmd, "AT+QICSGP=1,1,\"CMNET\",\"\",\"\",1\r\n"); + } else if (IPV6 == ip_type) { + strcpy(ec200t_cmd, "AT+QICSGP=1,2,\"CMNET\",\"\",\"\",1\r\n"); + } + + for(try = 0; try < TRY_TIMES; try++){ + ret = AtCmdConfigAndCheck(adapter->agent, ec200t_cmd, EC200T_OK_REPLY); + if (ret == 0) { + break; + } + } + if (ret < 0) { + goto out; + } + + /*step6: serial write "AT+QICLOSE", close socket connect before open socket*/ + memset(ec200t_cmd, 0, sizeof(ec200t_cmd)); + sprintf(ec200t_cmd, EC200T_CLOSE_SOCKET_CMD, adapter->socket.socket_id); + for(try = 0; try < TRY_TIMES; try++){ + ret = AtCmdConfigAndCheck(adapter->agent, ec200t_cmd, EC200T_OK_REPLY); + if (ret == 0) { + break; + } + } + if (ret < 0) { + goto out; + } + + /*step7: serial write "AT+QIDEACT", close TCP net before open socket*/ + for(try = 0; try < TRY_TIMES; try++){ + ret = AtCmdConfigAndCheck(adapter->agent, EC200T_DEACTIVE_PDP_CMD, EC200T_OK_REPLY); + if (ret == 0) { + break; + } + } + if (ret < 0) { + goto out; + } + + /*step8: serial write "AT+QIACT", open TCP net*/ + for(try = 0; try < TRY_TIMES; try++){ + ret = AtCmdConfigAndCheck(adapter->agent, EC200T_ACTIVE_PDP_CMD, EC200T_OK_REPLY); + if (ret == 0) { + break; + } + } + if (ret < 0) { + goto out; + } + + /*step9: serial write "AT+QIOPEN", connect socket using TCP*/ + memset(ec200t_cmd, 0, sizeof(ec200t_cmd)); + sprintf(ec200t_cmd, EC200T_OPEN_SOCKET_CMD, adapter->socket.socket_id); + strcat(ec200t_cmd, ",\"TCP\",\""); + strcat(ec200t_cmd, ip); + strcat(ec200t_cmd, "\","); + strcat(ec200t_cmd, port); + strcat(ec200t_cmd, ",0,2\r\n"); + + AtSetReplyEndChar(adapter->agent, 0x43, 0x54); + + for(try = 0; try < TRY_TIMES; try++){ + ret = AtCmdConfigAndCheck(adapter->agent, ec200t_cmd, EC200T_CONNECT_REPLY); + if (ret == 0) { + break; + } + } + if (ret < 0) { + goto out; + } + + ADAPTER_DEBUG("Ec200t connect TCP done\n"); + + return 0; + +out: + ADAPTER_DEBUG("Ec200t connect TCP failed. Power down\n"); + Ec200tPowerSet(); + return -1; +} + +static int Ec200tSend(struct Adapter *adapter, const void *buf, size_t len) +{ + if (adapter->agent) { + EntmSend(adapter->agent, (const char *)buf, len); + } else { + printf("Ec200tSend can not find agent\n"); + } + return 0; +} + +static int Ec200tRecv(struct Adapter *adapter, void *buf, size_t len) +{ + if (adapter->agent) { + return EntmRecv(adapter->agent, (char *)buf, len, 6); + } else { + printf("Ec200tRecv can not find agent\n"); + } + + return -1; +} + +static int Ec200tDisconnect(struct Adapter *adapter) +{ + int ret = 0; + uint8_t ec200t_cmd[64]; + + AtSetReplyEndChar(adapter->agent, 0x4F, 0x4B); + + /*step1: serial write "+++", quit transparent mode*/ + ATOrderSend(adapter->agent, REPLY_TIME_OUT, NULL, "+++"); + + /*step2: serial write "AT+QICLOSE", close socket connect before open socket*/ + memset(ec200t_cmd, 0, sizeof(ec200t_cmd)); + sprintf(ec200t_cmd, EC200T_CLOSE_SOCKET_CMD, adapter->socket.socket_id); + ret = AtCmdConfigAndCheck(adapter->agent, ec200t_cmd, EC200T_OK_REPLY); + if (ret < 0) { + goto out; + } + + ADAPTER_DEBUG("Ec200t disconnect TCP done\n"); + + return 0; + +out: + ADAPTER_DEBUG("Ec200t disconnect TCP failed. Power down\n"); + Ec200tPowerSet(); + return -1; +} + +static const struct IpProtocolDone ec200t_done = +{ + .open = Ec200tOpen, + .close = Ec200tClose, + .ioctl = Ec200tIoctl, + .setup = NULL, + .setdown = NULL, + .setaddr = NULL, + .setdns = NULL, + .setdhcp = NULL, + .ping = NULL, + .netstat = NULL, + .connect = Ec200tConnect, + .send = Ec200tSend, + .recv = Ec200tRecv, + .disconnect = Ec200tDisconnect, +}; + +AdapterProductInfoType Ec200tAttach(struct Adapter *adapter) +{ + struct AdapterProductInfo *product_info = PrivMalloc(sizeof(struct AdapterProductInfo)); + if (!product_info) { + printf("Ec200tAttach malloc product_info error\n"); + PrivFree(product_info); + return NULL; + } + + strcpy(product_info->model_name, ADAPTER_4G_EC200T); + + product_info->model_done = (void *)&ec200t_done; + + return product_info; +} diff --git a/APP_Framework/Framework/connection/5g/Kconfig b/APP_Framework/Framework/connection/5g/Kconfig new file mode 100644 index 0000000..e69de29 diff --git a/APP_Framework/Framework/connection/5g/Makefile b/APP_Framework/Framework/connection/5g/Makefile new file mode 100644 index 0000000..5b98645 --- /dev/null +++ b/APP_Framework/Framework/connection/5g/Makefile @@ -0,0 +1,3 @@ +SRC_FILES := adapter_5g.c + +include $(KERNEL_ROOT)/compiler.mk diff --git a/APP_Framework/Framework/connection/5g/adapter_5g.c b/APP_Framework/Framework/connection/5g/adapter_5g.c new file mode 100644 index 0000000..27485e1 --- /dev/null +++ b/APP_Framework/Framework/connection/5g/adapter_5g.c @@ -0,0 +1,20 @@ +/* +* Copyright (c) 2020 AIIT XUOS Lab +* XiUOS is licensed under Mulan PSL v2. +* You can use this software according to the terms and conditions of the Mulan PSL v2. +* You may obtain a copy of Mulan PSL v2 at: +* http://license.coscl.org.cn/MulanPSL2 +* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, +* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, +* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. +* See the Mulan PSL v2 for more details. +*/ + +/** + * @file adapter_5g.c + * @brief Implement the connection 5G adapter function + * @version 1.1 + * @author AIIT XUOS Lab + * @date 2021.06.25 + */ + diff --git a/APP_Framework/Framework/connection/Kconfig b/APP_Framework/Framework/connection/Kconfig new file mode 100644 index 0000000..43094d2 --- /dev/null +++ b/APP_Framework/Framework/connection/Kconfig @@ -0,0 +1,87 @@ +menuconfig SUPPORT_CONNECTION_FRAMEWORK + bool "support connection framework" + default n + select TRANSFORM_LAYER_ATTRIUBUTE + +if SUPPORT_CONNECTION_FRAMEWORK + config CONNECTION_FRAMEWORK_DEBUG + bool "Using connection framework debug log function" + default y + + menuconfig CONNECTION_INDUSTRIAL_ETHERNET + bool "Using industrial ethernet" + default n + if CONNECTION_INDUSTRIAL_ETHERNET + source "$APP_DIR/Framework/connection/industrial_ethernet/Kconfig" + endif + + menuconfig CONNECTION_INDUSTRIAL_FIELDBUS + bool "Using industrial fieldbus" + default n + if CONNECTION_INDUSTRIAL_FIELDBUS + source "$APP_DIR/Framework/connection/industrial_fieldbus/Kconfig" + endif + + menuconfig CONNECTION_INDUSTRIAL_WLAN + bool "Using industrial wlan" + default n + if CONNECTION_INDUSTRIAL_WLAN + source "$APP_DIR/Framework/connection/industrial_wlan/Kconfig" + endif + + menuconfig CONNECTION_ADAPTER_LORA + bool "Using lora adapter device" + default n + if CONNECTION_ADAPTER_LORA + source "$APP_DIR/Framework/connection/lora/Kconfig" + endif + + menuconfig CONNECTION_ADAPTER_4G + bool "Using 4G adapter device" + default n + if CONNECTION_ADAPTER_4G + source "$APP_DIR/Framework/connection/4g/Kconfig" + endif + + menuconfig CONNECTION_ADAPTER_NB + bool "Using nbiot adapter device" + default n + if CONNECTION_ADAPTER_NB + source "$APP_DIR/Framework/connection/nbiot/Kconfig" + endif + + menuconfig CONNECTION_ADAPTER_WIFI + bool "Using wifi adapter device" + default n + if CONNECTION_ADAPTER_WIFI + source "$APP_DIR/Framework/connection/wifi/Kconfig" + endif + + menuconfig CONNECTION_ADAPTER_ETHERNET + bool "Using ethernet adapter device" + default n + if CONNECTION_ADAPTER_ETHERNET + source "$APP_DIR/Framework/connection/ethernet/Kconfig" + endif + + menuconfig CONNECTION_ADAPTER_BLUETOOTH + bool "Using bluetooth adapter device" + default n + if CONNECTION_ADAPTER_BLUETOOTH + source "$APP_DIR/Framework/connection/bluetooth/Kconfig" + endif + + menuconfig CONNECTION_ADAPTER_ZIGBEE + bool "Using zigbee adapter device" + default n + if CONNECTION_ADAPTER_ZIGBEE + source "$APP_DIR/Framework/connection/zigbee/Kconfig" + endif + + menuconfig CONNECTION_ADAPTER_5G + bool "Using 5G adapter device" + default n + if CONNECTION_ADAPTER_5G + source "$APP_DIR/Framework/connection/5g/Kconfig" + endif +endif diff --git a/APP_Framework/Framework/connection/Make.defs b/APP_Framework/Framework/connection/Make.defs new file mode 100644 index 0000000..5be109e --- /dev/null +++ b/APP_Framework/Framework/connection/Make.defs @@ -0,0 +1,7 @@ +############################################################################ +# APP_Framework/Framework/connection/Make.defs +############################################################################ +ifneq ($(CONFIG_SUPPORT_CONNECTION_FRAMEWORK),) +CONFIGURED_APPS += $(APPDIR)/../../../APP_Framework/Framework/connection/ +endif +include $(wildcard $(APPDIR)/../../../APP_Framework/Framework/connection/*/Make.defs) diff --git a/APP_Framework/Framework/connection/Makefile b/APP_Framework/Framework/connection/Makefile new file mode 100644 index 0000000..01b5b6e --- /dev/null +++ b/APP_Framework/Framework/connection/Makefile @@ -0,0 +1,58 @@ +include $(KERNEL_ROOT)/.config +ifeq ($(CONFIG_ADD_NUTTX_FETURES),y) + include $(APPDIR)/Make.defs + CSRCS += adapter.c adapter_agent.c + include $(APPDIR)/Application.mk + +endif + +ifeq ($(CONFIG_ADD_XIZI_FETURES),y) + SRC_FILES := adapter.c adapter_agent.c + + ifeq ($(CONFIG_CONNECTION_INDUSTRIAL_ETHERNET),y) + SRC_DIR += industrial_ethernet + endif + + ifeq ($(CONFIG_CONNECTION_INDUSTRIAL_FIELDBUS),y) + SRC_DIR += industrial_fieldbus + endif + + ifeq ($(CONFIG_CONNECTION_INDUSTRIAL_WLAN),y) + SRC_DIR += industrial_wlan + endif + + ifeq ($(CONFIG_CONNECTION_ADAPTER_LORA),y) + SRC_DIR += lora + endif + + ifeq ($(CONFIG_CONNECTION_ADAPTER_4G),y) + SRC_DIR += 4g + endif + + ifeq ($(CONFIG_CONNECTION_ADAPTER_NB),y) + SRC_DIR += nbiot + endif + + ifeq ($(CONFIG_CONNECTION_ADAPTER_WIFI),y) + SRC_DIR += wifi + endif + + ifeq ($(CONFIG_CONNECTION_ADAPTER_ETHERNET),y) + SRC_DIR += ethernet + endif + + ifeq ($(CONFIG_CONNECTION_ADAPTER_BLUETOOTH),y) + SRC_DIR += bluetooth + endif + + ifeq ($(CONFIG_CONNECTION_ADAPTER_ZIGBEE),y) + SRC_DIR += zigbee + endif + + ifeq ($(CONFIG_CONNECTION_ADAPTER_5G),y) + SRC_DIR += 5g + endif + + include $(KERNEL_ROOT)/compiler.mk + +endif \ No newline at end of file diff --git a/APP_Framework/Framework/connection/adapter.c b/APP_Framework/Framework/connection/adapter.c new file mode 100644 index 0000000..6d3d8f2 --- /dev/null +++ b/APP_Framework/Framework/connection/adapter.c @@ -0,0 +1,903 @@ +/* +* Copyright (c) 2020 AIIT XUOS Lab +* XiUOS is licensed under Mulan PSL v2. +* You can use this software according to the terms and conditions of the Mulan PSL v2. +* You may obtain a copy of Mulan PSL v2 at: +* http://license.coscl.org.cn/MulanPSL2 +* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, +* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, +* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. +* See the Mulan PSL v2 for more details. +*/ + +/** + * @file adapter.c + * @brief Implement the connection adapter framework management and API + * @version 1.1 + * @author AIIT XUOS Lab + * @date 2021.05.10 + */ + +#include + +static DoublelistType adapter_list; + +static int adapter_list_lock; + +/** + * @description: Init adapter framework + * @return 0 + */ +int AdapterFrameworkInit(void) +{ + int ret = 0; + AppInitDoubleList(&adapter_list); + + ret = PrivMutexCreate(&adapter_list_lock, 0); + if(ret != 0) { + printf("AdapterFrameworkInit mutex create failed.\n"); + } + + return 0; +} + +/** + * @description: Find adapter device by name + * @param name - name string + * @return adapter device pointer + */ +AdapterType AdapterDeviceFindByName(const char *name) +{ + struct Adapter *ret = NULL; + struct DoublelistNode *node; + int status = 0; + + if (NULL == name) + return NULL; + + status = PrivMutexObtain(&adapter_list_lock); + if (status != 0){ + printf("%s:pthread_mutex_lock failed, status=%d\n",__func__,status); + } + + DOUBLE_LIST_FOR_EACH(node, &adapter_list) { + struct Adapter *adapter = CONTAINER_OF(node, + struct Adapter, link); + if (0 == strncmp(adapter->name, name, NAME_NUM_MAX)) { + ret = adapter; + break; + } + printf("PrivMutexObtain in loop\n"); + } + + status = PrivMutexAbandon(&adapter_list_lock); + if (status != 0){ + printf("%s:pthread_mutex_unlock failed, status=%d\n",__func__,status); + } + + return ret; +} + +/** + * @description: Register the adapter to the linked list + * @param adapter - adapter device pointer + * @return success: 0 , failure: -1 + */ +int AdapterDeviceRegister(struct Adapter *adapter) +{ + int status = 0; + if (NULL == adapter ) + return -1; + + if (NULL != AdapterDeviceFindByName(adapter->name)) { + printf("%s: sensor with the same name already registered\n", __func__); + return -1; + } + + status = PrivMutexObtain(&adapter_list_lock); + if (status != 0){ + printf("%s:pthread_mutex_lock failed, status=%d\n",__func__,status); + } + + AppDoubleListInsertNodeAfter(&adapter_list, &adapter->link); + + status = PrivMutexAbandon(&adapter_list_lock); + if (status != 0){ + printf("%s:pthread_mutex_unlock failed, status=%d\n",__func__,status); + } + + adapter->adapter_status = REGISTERED; + + return 0; +} + +/** + * @description: Unregister the adapter from the linked list + * @param adapter - adapter device pointer + * @return 0 + */ +int AdapterDeviceUnregister(struct Adapter *adapter) +{ + int status = 0; + if (!adapter) + return -1; + status = PrivMutexObtain(&adapter_list_lock); + if (status != 0){ + printf("%s:pthread_mutex_lock failed, status=%d\n",__func__,status); + } + + AppDoubleListRmNode(&adapter->link); + + status = PrivMutexAbandon(&adapter_list_lock); + if (status != 0){ + printf("%s:pthread_mutex_unlock failed, status=%d\n",__func__,status); + } + + adapter->adapter_status = UNREGISTERED; + + return 0; +} + +/** + * @description: Open adapter device + * @param name - adapter device name + * @return success: 0 , failure: other + */ +int AdapterDeviceOpen(struct Adapter *adapter) +{ + if (!adapter) + return -1; + + if (INSTALL == adapter->adapter_status) { + printf("Device %s has already been opened. Just return\n", adapter->name); + return 0; + } + + int result = 0; + + struct IpProtocolDone *ip_done = NULL; + struct PrivProtocolDone *priv_done = NULL; + + switch (adapter->net_protocol) + { + case PRIVATE_PROTOCOL: + priv_done = (struct PrivProtocolDone *)adapter->done; + if (NULL == priv_done->open) + return 0; + + result = priv_done->open(adapter); + if (0 == result) { + printf("Device %s open success.\n", adapter->name); + adapter->adapter_status = INSTALL; + } else { + if (adapter->fd) { + PrivClose(adapter->fd); + adapter->fd = 0; + } + printf("Device %s open failed(%d).\n", adapter->name, result); + } + break; + + case IP_PROTOCOL: + ip_done = (struct IpProtocolDone *)adapter->done; + if (NULL == ip_done->open) + return 0; + + result = ip_done->open(adapter); + if (0 == result) { + printf("Device %s open success.\n", adapter->name); + adapter->adapter_status = INSTALL; + } else { + if (adapter->fd) { + PrivClose(adapter->fd); + adapter->fd = 0; + } + printf("Device %s open failed(%d).\n", adapter->name, result); + } + break; + + default: + break; + } + + return result; +} + +/** + * @description: Close adapter device + * @param adapter - adapter device pointer + * @return success: 0 , failure: other + */ +int AdapterDeviceClose(struct Adapter *adapter) +{ + if (!adapter) + return -1; + + if (UNINSTALL == adapter->adapter_status) { + printf("Device %s has already been closed. Just return\n", adapter->name); + return 0; + } + + int result = 0; + + struct IpProtocolDone *ip_done = NULL; + struct PrivProtocolDone *priv_done = NULL; + + switch (adapter->net_protocol) + { + case PRIVATE_PROTOCOL: + priv_done = (struct PrivProtocolDone *)adapter->done; + if (NULL == priv_done->close) + return 0; + + result = priv_done->close(adapter); + if (0 == result) { + printf("%s successfully closed.\n", adapter->name); + adapter->adapter_status = UNINSTALL; + } else { + printf("Closed %s failure.\n", adapter->name); + } + + break; + + case IP_PROTOCOL: + ip_done = (struct IpProtocolDone *)adapter->done; + if (NULL == ip_done->close) + return 0; + + result = ip_done->close(adapter); + if (0 == result) { + printf("%s successfully closed.\n", adapter->name); + adapter->adapter_status = UNINSTALL; + } else { + printf("Closed %s failure.\n", adapter->name); + } + break; + + default: + break; + } + + return result; +} + +/** + * @description: Configure adapter device + * @param adapter - adapter device pointer + * @param cmd - command + * @param args - command parameter + * @return success: 0 , failure: other + */ +int AdapterDeviceControl(struct Adapter *adapter, int cmd, void *args) +{ + if (!adapter) + return -1; + + int result = 0; + + struct IpProtocolDone *ip_done = NULL; + struct PrivProtocolDone *priv_done = NULL; + + switch (adapter->net_protocol) + { + case PRIVATE_PROTOCOL: + priv_done = (struct PrivProtocolDone *)adapter->done; + if (NULL == priv_done->ioctl) + return 0; + + result = priv_done->ioctl(adapter, cmd, args); + if (0 == result) { + printf("Device %s ioctl success.\n", adapter->name); + adapter->adapter_status = INSTALL; + } else { + if (adapter->fd) { + PrivClose(adapter->fd); + adapter->fd = 0; + } + printf("Device %s ioctl failed(%d).\n", adapter->name, result); + } + break; + + case IP_PROTOCOL: + ip_done = (struct IpProtocolDone *)adapter->done; + if (NULL == ip_done->ioctl) + return 0; + + result = ip_done->ioctl(adapter, cmd, args); + if (0 == result) { + printf("Device %s ioctl success.\n", adapter->name); + adapter->adapter_status = INSTALL; + } else { + if (adapter->fd) { + PrivClose(adapter->fd); + adapter->fd = 0; + } + printf("Device %s ioctl failed(%d).\n", adapter->name, result); + } + break; + + default: + break; + } + + return result; +} + +/** + * @description: Receice data from adapter + * @param adapter - adapter device pointer + * @param dst - buffer to save data + * @param len - buffer length + * @return gotten data length + */ +ssize_t AdapterDeviceRecv(struct Adapter *adapter, void *dst, size_t len) +{ + if (!adapter) + return -1; + + if (PRIVATE_PROTOCOL == adapter->net_protocol) { + struct PrivProtocolDone *priv_done = (struct PrivProtocolDone *)adapter->done; + + if (NULL == priv_done->recv) + return -1; + + return priv_done->recv(adapter, dst, len); + } else if (IP_PROTOCOL == adapter->net_protocol) { + struct IpProtocolDone *ip_done = (struct IpProtocolDone *)adapter->done; + + if (NULL == ip_done->recv) + return -1; + + return ip_done->recv(adapter, dst, len); + } else { + printf("AdapterDeviceRecv net_protocol %d not support\n", adapter->net_protocol); + return -1; + } +} + +/** + * @description: Send data to adapter + * @param adapter - adapter device pointer + * @param src - data buffer + * @param len - data length + * @return length of data written + */ +ssize_t AdapterDeviceSend(struct Adapter *adapter, const void *src, size_t len) +{ + if (!adapter) + return -1; + + if (PRIVATE_PROTOCOL == adapter->net_protocol) { + struct PrivProtocolDone *priv_done = (struct PrivProtocolDone *)adapter->done; + + if (NULL == priv_done->send) + return -1; + + return priv_done->send(adapter, src, len); + } else if (IP_PROTOCOL == adapter->net_protocol) { + struct IpProtocolDone *ip_done = (struct IpProtocolDone *)adapter->done; + + if (NULL == ip_done->send) + return -1; + + return ip_done->send(adapter, src, len); + } else { + printf("AdapterDeviceSend net_protocol %d not support\n", adapter->net_protocol); + return -1; + } +} + +/** + * @description: Connect to a certain ip net, only support IP_PROTOCOL + * @param adapter - adapter device pointer + * @param ip - connect ip + * @param port - connect port + * @param ip_type - ip type, IPV4 or IPV6 + * @return success: 0 , failure: other + */ +int AdapterDeviceConnect(struct Adapter *adapter, enum NetRoleType net_role, const char *ip, const char *port, enum IpType ip_type) +{ + if (!adapter) + return -1; + + if (PRIVATE_PROTOCOL == adapter->net_protocol) { + printf("AdapterDeviceConnect not suuport private_protocol, please use join\n"); + return -1; + } else if (IP_PROTOCOL == adapter->net_protocol) { + struct IpProtocolDone *ip_done = (struct IpProtocolDone *)adapter->done; + + if (NULL == ip_done->connect) + return -1; + + return ip_done->connect(adapter, net_role, ip, port, ip_type); + } else { + printf("AdapterDeviceConnect net_protocol %d not support\n", adapter->net_protocol); + return -1; + } +} + +/** + * @description: Join to a certain private net, only support PRIVATE_PROTOCOL + * @param adapter - adapter device pointer + * @param priv_net_group - private net group + * @return success: 0 , failure: other + */ +int AdapterDeviceJoin(struct Adapter *adapter, unsigned char *priv_net_group) +{ + if (!adapter) + return -1; + + if (PRIVATE_PROTOCOL == adapter->net_protocol) { + struct PrivProtocolDone *priv_done = (struct PrivProtocolDone *)adapter->done; + + if (NULL == priv_done->join) + return -1; + + return priv_done->join(adapter, priv_net_group); + } else if (IP_PROTOCOL == adapter->net_protocol) { + printf("AdapterDeviceJoin not support ip_protocol, please use connect\n"); + return -1; + } else { + printf("AdapterDeviceJoin net_protocol %d not support\n", adapter->net_protocol); + return -1; + } +} + +/** + * @description: Adapter disconnect from ip net or private net group + * @param adapter - adapter device pointer + * @param priv_net_group - private net group for PRIVATE_PROTOCOL quit function + * @return success: 0 , failure: other + */ +int AdapterDeviceDisconnect(struct Adapter *adapter, unsigned char *priv_net_group) +{ + if (!adapter) + return -1; + + if (PRIVATE_PROTOCOL == adapter->net_protocol) { + struct PrivProtocolDone *priv_done = (struct PrivProtocolDone *)adapter->done; + + if (NULL == priv_done->quit) + return -1; + + return priv_done->quit(adapter, priv_net_group); + } else if (IP_PROTOCOL == adapter->net_protocol) { + struct IpProtocolDone *ip_done = (struct IpProtocolDone *)adapter->done; + + if (NULL == ip_done->disconnect) + return -1; + + return ip_done->disconnect(adapter); + } else { + printf("AdapterDeviceDisconnect net_protocol %d not support\n", adapter->net_protocol); + return -1; + } +} + +/** + * @description: Set up to net + * @param adapter - adapter device pointer + * @return success: 0 , failure: other + */ +int AdapterDeviceSetUp(struct Adapter *adapter) +{ + if (!adapter) + return -1; + + int result = 0; + + struct IpProtocolDone *ip_done = NULL; + struct PrivProtocolDone *priv_done = NULL; + + switch (adapter->net_protocol) + { + case PRIVATE_PROTOCOL: + priv_done = (struct PrivProtocolDone *)adapter->done; + if (NULL == priv_done->setup) + return 0; + + result = priv_done->setup(adapter); + if (0 == result) { + printf("Device %s setup success.\n", adapter->name); + adapter->adapter_status = INSTALL; + } else { + if (adapter->fd) { + PrivClose(adapter->fd); + adapter->fd = 0; + } + printf("Device %s setup failed(%d).\n", adapter->name, result); + } + break; + + case IP_PROTOCOL: + ip_done = (struct IpProtocolDone *)adapter->done; + if (NULL == ip_done->setup) + return 0; + + result = ip_done->setup(adapter); + if (0 == result) { + printf("Device %s setup success.\n", adapter->name); + adapter->adapter_status = INSTALL; + } else { + if (adapter->fd) { + PrivClose(adapter->fd); + adapter->fd = 0; + } + printf("Device %s setup failed(%d).\n", adapter->name, result); + } + break; + + default: + break; + } + + return result; +} + +/** + * @description: Set down from net + * @param adapter - adapter device pointer + * @return success: 0 , failure: other + */ +int AdapterDeviceSetDown(struct Adapter *adapter) +{ + if (!adapter) + return -1; + + int result = 0; + + struct IpProtocolDone *ip_done = NULL; + struct PrivProtocolDone *priv_done = NULL; + + switch (adapter->net_protocol) + { + case PRIVATE_PROTOCOL: + priv_done = (struct PrivProtocolDone *)adapter->done; + if (NULL == priv_done->setdown) + return 0; + + result = priv_done->setdown(adapter); + if (0 == result) { + printf("Device %s setdown success.\n", adapter->name); + adapter->adapter_status = INSTALL; + } else { + if (adapter->fd) { + PrivClose(adapter->fd); + adapter->fd = 0; + } + printf("Device %s setdown failed(%d).\n", adapter->name, result); + } + break; + + case IP_PROTOCOL: + ip_done = (struct IpProtocolDone *)adapter->done; + if (NULL == ip_done->setdown) + return 0; + + result = ip_done->setdown(adapter); + if (0 == result) { + printf("Device %s setdown success.\n", adapter->name); + adapter->adapter_status = INSTALL; + } else { + if (adapter->fd) { + PrivClose(adapter->fd); + adapter->fd = 0; + } + printf("Device %s setdown failed(%d).\n", adapter->name, result); + } + break; + + default: + break; + } + + return result; +} + +/** + * @description: Set ip/gateway/netmask address + * @param adapter - adapter device pointer + * @param ip - ip address + * @param gateway - gateway address + * @param netmast - netmast address + * @return success: 0 , failure: other + */ +int AdapterDeviceSetAddr(struct Adapter *adapter, const char *ip, const char *gateway, const char *netmask) +{ + if (!adapter) + return -1; + + int result = 0; + + struct IpProtocolDone *ip_done = NULL; + struct PrivProtocolDone *priv_done = NULL; + + switch (adapter->net_protocol) + { + case PRIVATE_PROTOCOL: + priv_done = (struct PrivProtocolDone *)adapter->done; + if (NULL == priv_done->setaddr) + return 0; + + result = priv_done->setaddr(adapter, ip, gateway, netmask); + if (0 == result) { + printf("Device %s setaddr success.\n", adapter->name); + adapter->adapter_status = INSTALL; + } else { + if (adapter->fd) { + PrivClose(adapter->fd); + adapter->fd = 0; + } + printf("Device %s setaddr failed(%d).\n", adapter->name, result); + } + break; + + case IP_PROTOCOL: + ip_done = (struct IpProtocolDone *)adapter->done; + if (NULL == ip_done->setaddr) + return 0; + + result = ip_done->setaddr(adapter, ip, gateway, netmask); + if (0 == result) { + printf("Device %s setaddr success.\n", adapter->name); + adapter->adapter_status = INSTALL; + } else { + if (adapter->fd) { + PrivClose(adapter->fd); + adapter->fd = 0; + } + printf("Device %s setaddr failed(%d).\n", adapter->name, result); + } + break; + + default: + break; + } + + return result; +} + +/** + * @description: Set dns function + * @param adapter - adapter device pointer + * @param dns_addr - dns address + * @param dns_count - dns count + * @return success: 0 , failure: other + */ +int AdapterDeviceSetDns(struct Adapter *adapter, const char *dns_addr, uint8 dns_count) +{ + if (!adapter) + return -1; + + int result = 0; + + struct IpProtocolDone *ip_done = NULL; + struct PrivProtocolDone *priv_done = NULL; + + switch (adapter->net_protocol) + { + case PRIVATE_PROTOCOL: + priv_done = (struct PrivProtocolDone *)adapter->done; + if (NULL == priv_done->setdns) + return 0; + + result = priv_done->setdns(adapter, dns_addr, dns_count); + if (0 == result) { + printf("Device %s setdns success.\n", adapter->name); + adapter->adapter_status = INSTALL; + } else { + if (adapter->fd) { + PrivClose(adapter->fd); + adapter->fd = 0; + } + printf("Device %s setdns failed(%d).\n", adapter->name, result); + } + break; + + case IP_PROTOCOL: + ip_done = (struct IpProtocolDone *)adapter->done; + if (NULL == ip_done->setdns) + return 0; + + result = ip_done->setdns(adapter, dns_addr, dns_count); + if (0 == result) { + printf("Device %s setdns success.\n", adapter->name); + adapter->adapter_status = INSTALL; + } else { + if (adapter->fd) { + PrivClose(adapter->fd); + adapter->fd = 0; + } + printf("Device %s setdns failed(%d).\n", adapter->name, result); + } + break; + + default: + break; + } + + return result; +} + +/** + * @description: Set DHCP function + * @param adapter - adapter device pointer + * @param enable - enable DHCP or not + * @return success: 0 , failure: other + */ +int AdapterDeviceSetDhcp(struct Adapter *adapter, int enable) +{ + if (!adapter) + return -1; + + int result = 0; + + struct IpProtocolDone *ip_done = NULL; + struct PrivProtocolDone *priv_done = NULL; + + switch (adapter->net_protocol) + { + case PRIVATE_PROTOCOL: + priv_done = (struct PrivProtocolDone *)adapter->done; + if (NULL == priv_done->setdhcp) + return 0; + + result = priv_done->setdhcp(adapter, enable); + if (0 == result) { + printf("Device %s setdhcp success.\n", adapter->name); + adapter->adapter_status = INSTALL; + } else { + if (adapter->fd) { + PrivClose(adapter->fd); + adapter->fd = 0; + } + printf("Device %s setdhcp failed(%d).\n", adapter->name, result); + } + break; + + case IP_PROTOCOL: + ip_done = (struct IpProtocolDone *)adapter->done; + if (NULL == ip_done->setdhcp) + return 0; + + result = ip_done->setdhcp(adapter, enable); + if (0 == result) { + printf("Device %s setdhcp success.\n", adapter->name); + adapter->adapter_status = INSTALL; + } else { + if (adapter->fd) { + PrivClose(adapter->fd); + adapter->fd = 0; + } + printf("Device %s setdhcp failed(%d).\n", adapter->name, result); + } + break; + + default: + break; + } + + return result; +} + +/** + * @description: ping function + * @param adapter - adapter device pointer + * @param destination - the destination ip address + * @return success: 0 , failure: other + */ +int AdapterDevicePing(struct Adapter *adapter, const char *destination) +{ + if (!adapter) + return -1; + + int result = 0; + + struct IpProtocolDone *ip_done = NULL; + struct PrivProtocolDone *priv_done = NULL; + + switch (adapter->net_protocol) + { + case PRIVATE_PROTOCOL: + priv_done = (struct PrivProtocolDone *)adapter->done; + if (NULL == priv_done->ping) + return 0; + + result = priv_done->ping(adapter, destination); + if (0 == result) { + printf("Device %s ping success.\n", adapter->name); + adapter->adapter_status = INSTALL; + } else { + if (adapter->fd) { + PrivClose(adapter->fd); + adapter->fd = 0; + } + printf("Device %s ping failed(%d).\n", adapter->name, result); + } + break; + + case IP_PROTOCOL: + ip_done = (struct IpProtocolDone *)adapter->done; + if (NULL == ip_done->ping) + return 0; + + result = ip_done->ping(adapter, destination); + if (0 == result) { + printf("Device %s ping success.\n", adapter->name); + adapter->adapter_status = INSTALL; + } else { + if (adapter->fd) { + PrivClose(adapter->fd); + adapter->fd = 0; + } + printf("Device %s ping failed(%d).\n", adapter->name, result); + } + break; + + default: + break; + } + + return result; +} + +/** + * @description: Show the net status + * @param adapter - adapter device pointer + * @return success: 0 , failure: other + */ +int AdapterDeviceNetstat(struct Adapter *adapter) +{ + if (!adapter) + return -1; + + int result = 0; + + struct IpProtocolDone *ip_done = NULL; + struct PrivProtocolDone *priv_done = NULL; + + switch (adapter->net_protocol) + { + case PRIVATE_PROTOCOL: + priv_done = (struct PrivProtocolDone *)adapter->done; + if (NULL == priv_done->netstat) + return 0; + + result = priv_done->netstat(adapter); + if (0 == result) { + printf("Device %s netstat success.\n", adapter->name); + adapter->adapter_status = INSTALL; + } else { + if (adapter->fd) { + PrivClose(adapter->fd); + adapter->fd = 0; + } + printf("Device %s netstat failed(%d).\n", adapter->name, result); + } + break; + + case IP_PROTOCOL: + ip_done = (struct IpProtocolDone *)adapter->done; + if (NULL == ip_done->netstat) + return 0; + + result = ip_done->netstat(adapter); + if (0 == result) { + printf("Device %s netstat success.\n", adapter->name); + adapter->adapter_status = INSTALL; + } else { + if (adapter->fd) { + PrivClose(adapter->fd); + adapter->fd = 0; + } + printf("Device %s netstat failed(%d).\n", adapter->name, result); + } + break; + + default: + break; + } + + return result; +} + diff --git a/APP_Framework/Framework/connection/adapter.h b/APP_Framework/Framework/connection/adapter.h new file mode 100644 index 0000000..aefb0df --- /dev/null +++ b/APP_Framework/Framework/connection/adapter.h @@ -0,0 +1,257 @@ +/* +* Copyright (c) 2020 AIIT XUOS Lab +* XiUOS is licensed under Mulan PSL v2. +* You can use this software according to the terms and conditions of the Mulan PSL v2. +* You may obtain a copy of Mulan PSL v2 at: +* http://license.coscl.org.cn/MulanPSL2 +* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, +* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, +* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. +* See the Mulan PSL v2 for more details. +*/ + +/** + * @file adapter.h + * @brief Structure and function declarations of the connection adapter framework + * @version 1.1 + * @author AIIT XUOS Lab + * @date 2021.05.10 + */ + +#ifndef ADAPTER_H +#define ADAPTER_H + +#include +#include +#include +#include +#include +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +#define ADAPTER_BUFFSIZE 64 + +#define ADAPTER_AT_OPERATION 1 +#define ADAPTER_LWIP_OPERATION 2 +#define ADAPTER_RAWIP_OPERATION 3 + +#ifdef CONNECTION_FRAMEWORK_DEBUG +#define ADAPTER_DEBUG printf +#else +#define ADAPTER_DEBUG +#endif + +#define ADAPTER_4G_NAME "4G" +#define ADAPTER_BLUETOOTH_NAME "bluetooth" +#define ADAPTER_ETHERNET_NAME "ethernet" +#define ADAPTER_ETHERCAT_NAME "ethercat" +#define ADAPTER_LORA_NAME "lora" +#define ADAPTER_NBIOT_NAME "nbiot" +#define ADAPTER_WIFI_NAME "wifi" +#define ADAPTER_ZIGBEE_NAME "zigbee" + +struct Adapter; +struct AdapterProductInfo; +typedef struct Adapter *AdapterType; +typedef struct AdapterProductInfo *AdapterProductInfoType; + +struct Socket +{ + uint8_t type; ///< socket type:DGRAM->UDP,STREAM->TCP + uint8_t protocal; ///< udp or tcp + unsigned short listen_port; ///< 0-65535 + uint8_t socket_id; ///< socket id + uint8_t recv_control; ///< receive control + uint8_t af_type; ///< IPv4 or IPv6 + char *src_ip_addr; ///< source P address + char *dst_ip_addr; ///< destination IP address +}; + +enum AdapterType +{ + ADAPTER_TYPE_LORA = 0, + ADAPTER_TYPE_4G , + ADAPTER_TYPE_NBIOT , + ADAPTER_TYPE_WIFI , + ADAPTER_TYPE_ETHERNET , + ADAPTER_TYPE_BLUETOOTH , + ADAPTER_TYPE_ZIGBEE , + ADAPTER_TYPE_5G , +}; + +enum NetProtocolType +{ + PRIVATE_PROTOCOL = 1, + IP_PROTOCOL, + PROTOCOL_NONE, +}; + +enum NetRoleType +{ + CLIENT = 1, + SERVER, + MASTER, + SLAVE, + COORDINATOR, + ROUTER, + END_DEVICE, + GATEWAY, + ROLE_NONE, +}; + +enum AdapterStatus +{ + REGISTERED = 1, + UNREGISTERED, + INSTALL, + UNINSTALL, +}; + +enum IpType +{ + IPV4 = 1, + IPV6, +}; + +struct AdapterData +{ + uint32 len; + uint8 *buffer; +}; + +struct AdapterProductInfo +{ + uint32_t functions; + char vendor_name[NAME_NUM_MAX]; + char model_name[NAME_NUM_MAX]; + uint32_t work_mode; + + void *model_done; +}; + +struct IpProtocolDone +{ + int (*open)(struct Adapter *adapter); + int (*close)(struct Adapter *adapter); + int (*ioctl)(struct Adapter *adapter, int cmd, void *args); + int (*setup)(struct Adapter *adapter); + int (*setdown)(struct Adapter *adapter); + int (*setaddr)(struct Adapter *adapter, const char *ip, const char *gateway, const char *netmask); + int (*setdns)(struct Adapter *adapter, const char *dns_addr, uint8 dns_count); + int (*setdhcp)(struct Adapter *adapter, int enable); + int (*ping)(struct Adapter *adapter, const char *destination); + int (*netstat)(struct Adapter *adapter); + int (*connect)(struct Adapter *adapter, enum NetRoleType net_role, const char *ip, const char *port, enum IpType ip_type); + int (*send)(struct Adapter *adapter, const void *buf, size_t len); + int (*recv)(struct Adapter *adapter, void *buf, size_t len); + int (*disconnect)(struct Adapter *adapter); +}; + +struct PrivProtocolDone +{ + int (*open)(struct Adapter *adapter); + int (*close)(struct Adapter *adapter); + int (*ioctl)(struct Adapter *adapter, int cmd, void *args); + int (*setup)(struct Adapter *adapter); + int (*setdown)(struct Adapter *adapter); + int (*setaddr)(struct Adapter *adapter, const char *ip, const char *gateway, const char *netmask); + int (*setdns)(struct Adapter *adapter, const char *dns_addr, uint8 dns_count); + int (*setdhcp)(struct Adapter *adapter, int enable); + int (*ping)(struct Adapter *adapter, const char *destination); + int (*netstat)(struct Adapter *adapter); + int (*join)(struct Adapter *adapter, unsigned char *priv_net_group); + int (*send)(struct Adapter *adapter, const void *buf, size_t len); + int (*recv)(struct Adapter *adapter, void *buf, size_t len); + int (*quit)(struct Adapter *adapter, unsigned char *priv_net_group); +}; + +struct Adapter +{ + char name[NAME_NUM_MAX]; + int fd; + + int product_info_flag; + struct AdapterProductInfo *info; + ATAgentType agent; + + struct Socket socket; + + int net_role_id; + enum NetProtocolType net_protocol; + enum NetRoleType net_role; + enum AdapterStatus adapter_status; + + char buffer[ADAPTER_BUFFSIZE]; + + void *done; + void *adapter_param; + + struct DoublelistNode link; +}; + +/*Init adapter framework*/ +int AdapterFrameworkInit(void); + +/*Find adapter device by name*/ +AdapterType AdapterDeviceFindByName(const char *name); + +/*Register the adapter to the linked list*/ +int AdapterDeviceRegister(struct Adapter *adapter); + +/*Unregister the adapter from the linked list*/ +int AdapterDeviceUnregister(struct Adapter *adapter); + +/*Open adapter device*/ +int AdapterDeviceOpen(struct Adapter *adapter); + +/*Close adapter device*/ +int AdapterDeviceClose(struct Adapter *adapter); + +/*Receice data from adapter*/ +ssize_t AdapterDeviceRecv(struct Adapter *adapter, void *dst, size_t len); + +/*Send data to adapter*/ +ssize_t AdapterDeviceSend(struct Adapter *adapter, const void *src, size_t len); + +/*Configure adapter device*/ +int AdapterDeviceControl(struct Adapter *adapter, int cmd, void *args); + +/*Connect to a certain ip net, only support IP_PROTOCOL*/ +int AdapterDeviceConnect(struct Adapter *adapter, enum NetRoleType net_role, const char *ip, const char *port, enum IpType ip_type); + +/*Join to a certain private net, only support PRIVATE_PROTOCOL*/ +int AdapterDeviceJoin(struct Adapter *adapter, unsigned char *priv_net_group); + +/*Adapter disconnect from ip net or private net group*/ +int AdapterDeviceDisconnect(struct Adapter *adapter, unsigned char *priv_net_group); + +/*Set up to net*/ +int AdapterDeviceSetUp(struct Adapter *adapter); + +/*Set down from net*/ +int AdapterDeviceSetDown(struct Adapter *adapter); + +/*Set ip/gateway/netmask address*/ +int AdapterDeviceSetAddr(struct Adapter *adapter, const char *ip, const char *gateway, const char *netmask); + +/*Set DNS function*/ +int AdapterDeviceSetDns(struct Adapter *adapter, const char *dns_addr, uint8 dns_count); + +/*Set DHCP function*/ +int AdapterDeviceSetDhcp(struct Adapter *adapter, int enable); + +/*ping function*/ +int AdapterDevicePing(struct Adapter *adapter, const char *destination); + +/*Show the net status*/ +int AdapterDeviceNetstat(struct Adapter *adapter); + +#ifdef __cplusplus +} +#endif + +#endif \ No newline at end of file diff --git a/APP_Framework/Framework/connection/adapter_agent.c b/APP_Framework/Framework/connection/adapter_agent.c new file mode 100755 index 0000000..29b4cae --- /dev/null +++ b/APP_Framework/Framework/connection/adapter_agent.c @@ -0,0 +1,624 @@ +/* +* Copyright (c) 2020 AIIT XUOS Lab +* XiUOS is licensed under Mulan PSL v2. +* You can use this software according to the terms and conditions of the Mulan PSL v2. +* You may obtain a copy of Mulan PSL v2 at: +* http://license.coscl.org.cn/MulanPSL2 +* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, +* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, +* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. +* See the Mulan PSL v2 for more details. +*/ + +/** + * @file xs_adapterAT_client.c + * @brief AT proxy, auto receive AT reply and transparency data + * @version 1.0 + * @author AIIT XUOS Lab + * @date 2021.04.22 + */ + + +#include +#include +#include +#include +#include +#include +#include +#ifdef ADD_XIZI_FETURES +# include +#endif + +#define AT_CMD_MAX_LEN 128 +#define AT_AGENT_MAX 2 +static char send_buf[AT_CMD_MAX_LEN]; +static uint32_t last_cmd_len = 0; + +static struct ATAgent at_agent_table[AT_AGENT_MAX] = {0}; + +unsigned int IpTint(char *ipstr) +{ + if (ipstr == NULL) + return 0; + + char *token; + unsigned int i = 3, total = 0, cur; + + token = strtok(ipstr, "."); + + while (token != NULL) { + cur = atoi(token); + if (cur >= 0 && cur <= 255) { + total += cur * pow(256, i); + } + i--; + token = strtok(NULL, "."); + } + + return total; +} + +void SwapStr(char *str, int begin, int end) +{ + int i, j; + + for (i = begin, j = end; i <= j; i++, j--) { + if (str[i] != str[j]) { + str[i] = str[i] ^ str[j]; + str[j] = str[i] ^ str[j]; + str[i] = str[i] ^ str[j]; + } + } +} + +char *IpTstr(unsigned int ipint) +{ + int LEN = 16; + char *new = (char *)PrivMalloc(LEN); + memset(new, '\0', LEN); + new[0] = '.'; + char token[4]; + int bt, ed, len, cur; + + while (ipint) { + cur = ipint % 256; + sprintf(token, "%d", cur); + strcat(new, token); + ipint /= 256; + if (ipint) + strcat(new, "."); + } + + len = strlen(new); + SwapStr(new, 0, len - 1); + + for (bt = ed = 0; ed < len;) { + while (ed < len && new[ed] != '.') { + ed++; + } + SwapStr(new, bt, ed - 1); + ed += 1; + bt = ed; + } + + new[len - 1] = '\0'; + + return new; +} + +int ParseATReply(char *str, const char *format, ...) +{ + va_list params; + int counts = 0; + + va_start(params, format); + counts = vsscanf(str, format, params); + va_end(params); + + return counts; +} + +void ATSprintf(int fd, const char *format, va_list params) +{ + last_cmd_len = vsnprintf(send_buf, sizeof(send_buf), format, params); + printf("AT send %s len %u\n",send_buf, last_cmd_len); + PrivWrite(fd, send_buf, last_cmd_len); +} + +int ATOrderSend(ATAgentType agent, uint32_t timeout_s, ATReplyType reply, const char *cmd_expr, ...) +{ + if (agent == NULL) { + printf("ATAgent is null"); + return -1; + } + + struct timespec abstime; + + abstime.tv_sec = timeout_s; + + PrivMutexObtain(&agent->lock); + agent->receive_mode = AT_MODE; + + memset(agent->maintain_buffer, 0x00, agent->maintain_max); + agent->maintain_len = 0; + + memset(agent->entm_recv_buf, 0, ENTM_RECV_MAX); + agent->entm_recv_len = 0; + + va_list params; + uint32_t cmd_size = 0; + uint32_t result = 0; + const char *cmd = NULL; + + agent->reply = reply; + PrivMutexAbandon(&agent->lock); + + if(agent->reply != NULL) { + PrivMutexObtain(&agent->lock); + reply->reply_len = 0; + va_start(params, cmd_expr); + ATSprintf(agent->fd, cmd_expr, params); + va_end(params); + PrivMutexAbandon(&agent->lock); + if (PrivSemaphoreObtainWait(&agent->rsp_sem, &abstime) != 0) { + printf("take sem %d timeout\n",agent->rsp_sem); + result = -2; + goto __out; + } + } else { + PrivMutexObtain(&agent->lock); + va_start(params, cmd_expr); + ATSprintf(agent->fd, cmd_expr, params); + va_end(params); + PrivMutexAbandon(&agent->lock); + goto __out; + } + +__out: + // agent->reply = NULL; + return result; +} + +int AtCmdConfigAndCheck(ATAgentType agent, char *cmd, char *check) +{ + int ret = 0; + char *result = NULL; + if (NULL == agent || NULL == cmd || NULL == check ) { + return -1; + } + + ATReplyType reply = CreateATReply(256); + if (NULL == reply) { + printf("%s %d at_create_resp failed!\n",__func__,__LINE__); + ret = -1; + goto __exit; + } + + ret = ATOrderSend(agent, REPLY_TIME_OUT, reply, cmd); + if(ret < 0){ + printf("%s %d ATOrderSend failed.\n",__func__,__LINE__); + ret = -1; + goto __exit; + } + + //PrivTaskDelay(3000); + + result = GetReplyText(reply); + if (!result) { + printf("%s %n get reply failed.\n",__func__,__LINE__); + ret = -1; + goto __exit; + } + printf("[reply result :\n"); + printf("%s]\n", result); + if(!strstr(result, check)) { + printf("%s %d check[%s] reply[%s] failed.\n",__func__,__LINE__,check,result); + ret = -1; + goto __exit; + } + +__exit: + DeleteATReply(reply); + return ret; +} + +char *GetReplyText(ATReplyType reply) +{ + return reply->reply_buffer; +} + +int AtSetReplyLrEnd(ATAgentType agent, char enable) +{ + if (!agent) { + return -1; + } + + agent->reply_lr_end = enable; + + return 0; +} + +int AtSetReplyEndChar(ATAgentType agent, char last_ch, char end_ch) +{ + if (!agent) { + return -1; + } + + agent->reply_end_last_char = last_ch; + agent->reply_end_char = end_ch; + + return 0; +} + +int AtSetReplyCharNum(ATAgentType agent, unsigned int num) +{ + if (!agent) { + return -1; + } + + agent->reply_char_num = num; + + return 0; +} + +int EntmSend(ATAgentType agent, const char *data, int len) +{ + char send_buf[128]; + if(len > 128){ + printf("send length %d more then max 128 Bytes.\n",len); + return -1; + } + + PrivMutexObtain(&agent->lock); + memset(send_buf, 0, 128); + + agent->receive_mode = ENTM_MODE; + + memcpy(send_buf, data, len); + // memcpy(send_buf + len, "!@", 2); + + PrivWrite(agent->fd, send_buf, len); + PrivMutexAbandon(&agent->lock); + printf("entm send %s length %d\n",send_buf, len); + return 0; +} + +int EntmRecv(ATAgentType agent, char *rev_buffer, int buffer_len, int timeout_s) +{ + struct timespec abstime; + + abstime.tv_sec = timeout_s; + if(buffer_len > ENTM_RECV_MAX){ + printf("read length more then max length[%d] Bytes",ENTM_RECV_MAX); + return -1; + } + PrivMutexObtain(&agent->lock); + agent->receive_mode = ENTM_MODE; + agent->read_len = buffer_len; + PrivMutexAbandon(&agent->lock); + //PrivTaskDelay(1000); + if (PrivSemaphoreObtainWait(&agent->entm_rx_notice, &abstime)) { + printf("wait sem[%d] timeout\n",agent->entm_rx_notice); + return -ERROR; + } + PrivMutexObtain(&agent->lock); + + + printf("EntmRecv once len %d.\n", agent->entm_recv_len); + + memcpy(rev_buffer, agent->entm_recv_buf, agent->entm_recv_len); + + memset(agent->entm_recv_buf, 0, ENTM_RECV_MAX); + agent->entm_recv_len = 0; + agent->read_len = 0; + PrivMutexAbandon(&agent->lock); + + return buffer_len; +} + +static int GetCompleteATReply(ATAgentType agent) +{ + uint32_t read_len = 0; + char ch = 0, last_ch = 0; + bool is_full = false; + + PrivMutexObtain(&agent->lock); + + memset(agent->maintain_buffer, 0x00, agent->maintain_max); + agent->maintain_len = 0; + + memset(agent->entm_recv_buf, 0x00, 256); + agent->entm_recv_len = 0; + + PrivMutexAbandon(&agent->lock); + + while (1) + { + PrivRead(agent->fd, &ch, 1); +#ifdef CONNECTION_FRAMEWORK_DEBUG + if(ch != 0){ + printf(" %c (0x%x)\n", ch, ch); + } +#endif + + PrivMutexObtain(&agent->lock); + if (agent->receive_mode == ENTM_MODE) + { + if (agent->entm_recv_len < ENTM_RECV_MAX) + { + agent->entm_recv_buf[agent->entm_recv_len] = ch; + agent->entm_recv_len++; + + if(agent->entm_recv_len < agent->read_len){ + PrivMutexAbandon(&agent->lock); + continue; + } + else + { + printf("ENTM_MODE recv %d Bytes done.\n",agent->entm_recv_len); + agent->receive_mode = DEFAULT_MODE; + PrivSemaphoreAbandon(&agent->entm_rx_notice); + } + + } else { + printf("entm_recv_buf is_full ...\n"); + } + } + else if (agent->receive_mode == AT_MODE) + { + if (read_len < agent->maintain_max) + { + if(ch != 0) ///< if the char is null then do not save it to the buff + { + agent->maintain_buffer[read_len] = ch; + read_len++; + agent->maintain_len = read_len; + } + + } else { + printf("maintain_len is_full ...\n"); + is_full = true; + } + + if (((ch == '\n') && (last_ch == '\r') && (agent->reply_lr_end)) || + ((ch == agent->reply_end_char) && (agent->reply_end_char) && + (last_ch == agent->reply_end_last_char) && (agent->reply_end_last_char)) || + ((read_len == agent->reply_char_num) && (agent->reply_char_num))){ + if (is_full) { + printf("read line failed. The line data length is out of buffer size(%d)!", agent->maintain_max); + memset(agent->maintain_buffer, 0x00, agent->maintain_max); + agent->maintain_len = 0; + PrivMutexAbandon(&agent->lock); + return -ERROR; + } + + printf("GetCompleteATReply done\n"); + agent->receive_mode = DEFAULT_MODE; + PrivMutexAbandon(&agent->lock); + break; + } + last_ch = ch; + } + + PrivMutexAbandon(&agent->lock); + } + + return read_len; +} + +ATAgentType GetATAgent(const char *agent_name) +{ + struct ATAgent* result = NULL; + for (int i = 0; i < AT_AGENT_MAX; i++) { + if (strcmp(at_agent_table[i].agent_name, agent_name) == 0) { + result = &at_agent_table[i]; + } + } + + return result; +} + + +int DeleteATAgent(ATAgentType agent) +{ + printf("delete agent->at_handler = %d\n",agent->at_handler); + if(agent->at_handler > 0){ + PrivTaskDelete(agent->at_handler, 0); + } + + if (agent->fd > 0) { + printf("close agent fd = %d\n",agent->fd); + PrivClose(agent->fd); + } + +#ifdef ADD_NUTTX_FETURES + if (agent->lock.sem.semcount > 0) { + printf("delete agent lock = %d\n",agent->lock.sem.semcount); + PrivMutexDelete(&agent->lock); + } +#else + if (agent->lock) { + printf("delete agent lock = %d\n",agent->lock); + PrivMutexDelete(&agent->lock); + } +#endif + + if (agent->entm_rx_notice) { + printf("delete agent entm_rx_notice = %d\n",agent->entm_rx_notice); + PrivSemaphoreDelete(&agent->entm_rx_notice); + } + + if (agent->rsp_sem) { + printf("delete agent rsp_sem = %d\n",agent->rsp_sem); + PrivSemaphoreDelete(&agent->rsp_sem); + } + + if (agent->maintain_buffer) { + PrivFree(agent->maintain_buffer); + } + + memset(agent, 0x00, sizeof(struct ATAgent)); + printf("delete ATagent\n"); +} + +static void *ATAgentReceiveProcess(void *param) +{ + ATAgentType agent = (ATAgentType)param; + const struct at_urc *urc; + + while (1) { + if (GetCompleteATReply(agent) > 0) + { + PrivMutexObtain(&agent->lock); + if (agent->reply != NULL){ + ATReplyType reply = agent->reply; + + agent->maintain_buffer[agent->maintain_len] = '\0'; + if (agent->maintain_len <= reply->reply_max_len) { + memset(reply->reply_buffer, 0 , reply->reply_max_len); + memcpy(reply->reply_buffer, agent->maintain_buffer, agent->maintain_len); + reply->reply_len = agent->maintain_len; + } else { + printf("out of memory (%d)!\n", reply->reply_max_len); + } + + // agent->reply = NULL; + PrivSemaphoreAbandon(&agent->rsp_sem); + } + PrivMutexAbandon(&agent->lock); + } + } +} + +static int ATAgentInit(ATAgentType agent) +{ + int result = 0; + + agent->maintain_len = 0; + agent->maintain_buffer = (char *)PrivMalloc(agent->maintain_max); + + if (agent->maintain_buffer == NULL) { + printf("ATAgentInit malloc maintain_buffer error\n"); + goto __out; + } + + memset(agent->maintain_buffer, 0, agent->maintain_max); + + result = PrivSemaphoreCreate(&agent->entm_rx_notice, 0, 0); + if (result < 0) { + printf("ATAgentInit create entm sem error\n"); + goto __out; + } + printf("create entm_rx_notice_sem %d\n ",agent->entm_rx_notice); + result = PrivSemaphoreCreate(&agent->rsp_sem, 0, 0); + if (result < 0) { + printf("ATAgentInit create rsp sem error\n"); + goto __out; + } + printf("create rsp_sem %d\n ",agent->rsp_sem); + if(PrivMutexCreate(&agent->lock, 0) < 0) { + printf("AdapterFrameworkInit mutex create failed.\n"); + goto __out; + } + + agent->receive_mode = DEFAULT_MODE; + +#ifdef ADD_NUTTX_FETURES + pthread_attr_t attr = PTHREAD_ATTR_INITIALIZER; + attr.priority = 18; + attr.stacksize = 4096; + +#else + pthread_attr_t attr; + attr.schedparam.sched_priority = 25; + attr.stacksize = 4096; +#endif + + PrivTaskCreate(&agent->at_handler, &attr, ATAgentReceiveProcess, agent); + printf("create agent->at_handler = %d\n",agent->at_handler); + return result; + +__out: + DeleteATAgent(agent); + result = -1; + + return result; +} + +int InitATAgent(const char *agent_name, int agent_fd, uint32 maintain_max) +{ + int i = 0; + int result = 0; + int open_result = 0; + struct ATAgent *agent = NULL; + + if (GetATAgent(agent_name) != NULL) { + return result; + } + + while (i < AT_AGENT_MAX && at_agent_table[i].fd > 0) { + i++; + } + + if (i >= AT_AGENT_MAX) { + printf("agent buffer(%d) is full.", AT_AGENT_MAX); + result = -1; + return result; + } + + agent = &at_agent_table[i]; + + agent->fd = agent_fd; + + strcpy(agent->agent_name, agent_name); + + agent->maintain_max = maintain_max; + + result = ATAgentInit(agent); + if (result == 0) { + PrivTaskStartup(&agent->at_handler); + } + + return result; +} + +ATReplyType CreateATReply(uint32 reply_max_len) +{ + ATReplyType reply = NULL; + + reply = (ATReplyType)PrivMalloc(sizeof(struct ATReply)); + if (reply == NULL) { + printf("no more memory\n"); + return NULL; + } + memset(reply, 0, sizeof(struct ATReply)); + + reply->reply_max_len = reply_max_len; + + reply->reply_buffer = (char *)PrivMalloc(reply_max_len); + if (reply->reply_buffer == NULL) { + printf("no more memory\n"); + PrivFree(reply); + return NULL; + } + + memset(reply->reply_buffer, 0, reply_max_len); + + return reply; +} + +void DeleteATReply(ATReplyType reply) +{ + if (reply) { + if (reply->reply_buffer) { + PrivFree(reply->reply_buffer); + reply->reply_buffer = NULL; + } + } + + if (reply) { + PrivFree(reply); + reply = NULL; + } +} diff --git a/APP_Framework/Framework/connection/at_agent.h b/APP_Framework/Framework/connection/at_agent.h new file mode 100755 index 0000000..c984285 --- /dev/null +++ b/APP_Framework/Framework/connection/at_agent.h @@ -0,0 +1,97 @@ +/* +* Copyright (c) 2020 AIIT XUOS Lab +* XiUOS is licensed under Mulan PSL v2. +* You can use this software according to the terms and conditions of the Mulan PSL v2. +* You may obtain a copy of Mulan PSL v2 at: +* http://license.coscl.org.cn/MulanPSL2 +* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, +* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, +* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. +* See the Mulan PSL v2 for more details. +*/ + +/** + * @file xs_adapter_at_agent.h + * @brief AT proxy, auto receive AT reply and transparency data + * @version 1.0 + * @author AIIT XUOS Lab + * @date 2021.04.22 + */ + +#ifndef XS_ADAPTER_AT_CLIENT_H +#define XS_ADAPTER_AT_CLIENT_H + +#include +#include +#include +#include + +#define REPLY_TIME_OUT 10 + +enum ReceiveMode +{ + DEFAULT_MODE = 0, + ENTM_MODE = 1, + AT_MODE = 2, +}; + +struct ATReply +{ + char *reply_buffer; + uint32 reply_max_len; + uint32 reply_len; +}; +typedef struct ATReply *ATReplyType; + +struct ATAgent +{ + char agent_name[64]; + int fd; + int read_len; ///< control data length of wanting reading + + char *maintain_buffer; + uint32 maintain_len; + uint32 maintain_max; + +#ifdef ADD_NUTTX_FETURES + pthread_mutex_t lock; +#else + int lock; +#endif + + ATReplyType reply; + char reply_lr_end; + char reply_end_last_char; + char reply_end_char; + uint32 reply_char_num; + int rsp_sem; + + pthread_t at_handler; + + #define ENTM_RECV_MAX 256 + char entm_recv_buf[ENTM_RECV_MAX]; + uint32 entm_recv_len; + enum ReceiveMode receive_mode; + int entm_rx_notice; +}; +typedef struct ATAgent *ATAgentType; + +int EntmSend(ATAgentType agent, const char *data, int len); +int EntmRecv(ATAgentType agent, char *rev_buffer, int buffer_len, int timeout_s); +char *GetReplyText(ATReplyType reply); +int AtSetReplyEndChar(ATAgentType agent, char last_ch, char end_ch); +int AtSetReplyCharNum(ATAgentType agent, unsigned int num); +int AtSetReplyLrEnd(ATAgentType agent, char enable); +ATReplyType CreateATReply(uint32 reply_max_len); +unsigned int IpTint(char *ipstr); +void SwapStr(char *str, int begin, int end); +char* IpTstr(unsigned int ipint); +ATAgentType GetATAgent(const char *agent_name); +int InitATAgent(const char *agent_name, int fd, uint32 maintain_max); +int DeleteATAgent(ATAgentType agent); +int ParseATReply(char* str, const char *format, ...); +void DeleteATReply(ATReplyType reply); +int ATOrderSend(ATAgentType agent, uint32_t timeout_s, ATReplyType reply, const char *cmd_expr, ...); +int AtCmdConfigAndCheck(ATAgentType agent, char *cmd, char *check); + +#endif \ No newline at end of file diff --git a/APP_Framework/Framework/connection/bluetooth/Kconfig b/APP_Framework/Framework/connection/bluetooth/Kconfig new file mode 100644 index 0000000..cb71df5 --- /dev/null +++ b/APP_Framework/Framework/connection/bluetooth/Kconfig @@ -0,0 +1,7 @@ +config ADAPTER_HC08 + bool "Using bluetooth adapter device HC08" + default y + +if ADAPTER_HC08 + source "$APP_DIR/Framework/connection/bluetooth/hc08/Kconfig" +endif diff --git a/APP_Framework/Framework/connection/bluetooth/Makefile b/APP_Framework/Framework/connection/bluetooth/Makefile new file mode 100644 index 0000000..bb36701 --- /dev/null +++ b/APP_Framework/Framework/connection/bluetooth/Makefile @@ -0,0 +1,7 @@ +SRC_FILES := adapter_bluetooth.c + +ifeq ($(CONFIG_ADAPTER_HC08),y) + SRC_DIR += hc08 +endif + +include $(KERNEL_ROOT)/compiler.mk diff --git a/APP_Framework/Framework/connection/bluetooth/adapter_bluetooth.c b/APP_Framework/Framework/connection/bluetooth/adapter_bluetooth.c new file mode 100644 index 0000000..b8cc069 --- /dev/null +++ b/APP_Framework/Framework/connection/bluetooth/adapter_bluetooth.c @@ -0,0 +1,110 @@ +/* +* Copyright (c) 2020 AIIT XUOS Lab +* XiUOS is licensed under Mulan PSL v2. +* You can use this software according to the terms and conditions of the Mulan PSL v2. +* You may obtain a copy of Mulan PSL v2 at: +* http://license.coscl.org.cn/MulanPSL2 +* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, +* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, +* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. +* See the Mulan PSL v2 for more details. +*/ + +/** + * @file adapter_bluetooth.c + * @brief Implement the connection bluetooth adapter function + * @version 1.1 + * @author AIIT XUOS Lab + * @date 2021.06.25 + */ + +#include + +#ifdef ADAPTER_HC08 +extern AdapterProductInfoType Hc08Attach(struct Adapter *adapter); +#endif + +static int AdapterBlueToothRegister(struct Adapter *adapter) +{ + int ret = 0; + + strncpy(adapter->name, ADAPTER_BLUETOOTH_NAME, NAME_NUM_MAX); + + adapter->net_protocol = IP_PROTOCOL; + adapter->adapter_status = UNREGISTERED; + + ret = AdapterDeviceRegister(adapter); + if (ret < 0) { + printf("AdapterBlueToothRegister register error\n"); + return -1; + } + + return ret; +} + +int AdapterBlueToothInit(void) +{ + int ret = 0; + + struct Adapter *adapter = PrivMalloc(sizeof(struct Adapter)); + if (!adapter) { + PrivFree(adapter); + return -1; + } + + memset(adapter, 0, sizeof(struct Adapter)); + + ret = AdapterBlueToothRegister(adapter); + if (ret < 0) { + printf("AdapterBlueToothInit register BT adapter error\n"); + PrivFree(adapter); + return -1; + } + +#ifdef ADAPTER_HC08 + AdapterProductInfoType product_info = Hc08Attach(adapter); + if (!product_info) { + printf("AdapterBlueToothInit hc08 attach error\n"); + PrivFree(adapter); + return -1; + } + + adapter->product_info_flag = 1; + adapter->info = product_info; + adapter->done = product_info->model_done; + +#endif + + return ret; +} + +/******************4G TEST*********************/ +int AdapterBlueToothTest(void) +{ + const char *bluetooth_msg = "BT Adapter Test"; + char bluetooth_recv_msg[128]; + int len; + int baud_rate = BAUD_RATE_115200; + + struct Adapter *adapter = AdapterDeviceFindByName(ADAPTER_BLUETOOTH_NAME); + +#ifdef ADAPTER_HC08 + AdapterDeviceOpen(adapter); + AdapterDeviceControl(adapter, OPE_INT, &baud_rate); + + len = strlen(bluetooth_msg); + + while (1) { + AdapterDeviceRecv(adapter, bluetooth_recv_msg, 128); + printf("bluetooth_recv_msg %s\n", bluetooth_recv_msg); + AdapterDeviceSend(adapter, bluetooth_msg, len); + printf("send %s after recv\n", bluetooth_msg); + PrivTaskDelay(100); + memset(bluetooth_recv_msg, 0, 128); + } + +#endif + + return 0; +} +SHELL_EXPORT_CMD(SHELL_CMD_PERMISSION(0)|SHELL_CMD_TYPE(SHELL_TYPE_CMD_FUNC)|SHELL_CMD_PARAM_NUM(0)|SHELL_CMD_DISABLE_RETURN, AdapterBlueToothTest, AdapterBlueToothTest, show adapter BT information); diff --git a/APP_Framework/Framework/connection/bluetooth/hc08/Kconfig b/APP_Framework/Framework/connection/bluetooth/hc08/Kconfig new file mode 100644 index 0000000..49a84ed --- /dev/null +++ b/APP_Framework/Framework/connection/bluetooth/hc08/Kconfig @@ -0,0 +1,40 @@ +config ADAPTER_BLUETOOTH_HC08 + string "HC08 adapter name" + default "hc08" + +if ADD_XIZI_FETURES + config ADAPTER_HC08_RECV_BUFFER_SIZE + int "HC08 recv data buffer size" + default "128" + + config ADAPTER_HC08_WORK_ROLE + string "HC08 work role M(MASTER) or S(SLAVER)" + default "M" + + config ADAPTER_HC08_DRIVER_EXTUART + bool "Using extra uart to support bluetooth" + default n + + config ADAPTER_HC08_DRIVER + string "HC08 device uart driver path" + default "/dev/uart4_dev4" + depends on !ADAPTER_HC08_DRIVER_EXTUART + + if ADAPTER_HC08_DRIVER_EXTUART + config ADAPTER_HC08_DRIVER + string "HC08 device extra uart driver path" + default "/dev/extuart_dev7" + + config ADAPTER_HC08_DRIVER_EXT_PORT + int "if HC08 device using extuart, choose port" + default "7" + endif +endif + +if ADD_NUTTX_FETURES + +endif + +if ADD_RTTHREAD_FETURES + +endif diff --git a/APP_Framework/Framework/connection/bluetooth/hc08/Makefile b/APP_Framework/Framework/connection/bluetooth/hc08/Makefile new file mode 100644 index 0000000..60932ce --- /dev/null +++ b/APP_Framework/Framework/connection/bluetooth/hc08/Makefile @@ -0,0 +1,3 @@ +SRC_FILES := hc08.c + +include $(KERNEL_ROOT)/compiler.mk diff --git a/APP_Framework/Framework/connection/bluetooth/hc08/hc08.c b/APP_Framework/Framework/connection/bluetooth/hc08/hc08.c new file mode 100644 index 0000000..ddba196 --- /dev/null +++ b/APP_Framework/Framework/connection/bluetooth/hc08/hc08.c @@ -0,0 +1,430 @@ +/* +* Copyright (c) 2020 AIIT XUOS Lab +* XiUOS is licensed under Mulan PSL v2. +* You can use this software according to the terms and conditions of the Mulan PSL v2. +* You may obtain a copy of Mulan PSL v2 at: +* http://license.coscl.org.cn/MulanPSL2 +* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, +* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, +* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. +* See the Mulan PSL v2 for more details. +*/ + +/** + * @file hc08.c + * @brief Implement the connection Bluetooth adapter function, using HC08 device + * @version 1.1 + * @author AIIT XUOS Lab + * @date 2021.07.12 + */ + +#include +#include + +#define HC08_DETECT_CMD "AT" +#define HC08_DEFAULT_CMD "AT+DEFAULT" +#define HC08_RESET_CMD "AT+RESET" +#define HC08_CLEAR_CMD "AT+CLEAR" +#define HC08_GET_DEVICE_INFO "AT+RX" + +#define HC08_GET_BAUDRATE_CMD "AT+BAUD=?" +#define HC08_SET_BAUDRATE_CMD "AT+BAUD=%u" +#define HC08_GET_CONNECTABLE "AT+CONT=?" +#define HC08_SET_CONNECTABLE "AT+CONT=%s" +#define HC08_GET_ROLE_CMD "AT+ROLE=?" +#define HC08_SET_ROLE_CMD "AT+ROLE=%s" +#define HC08_GET_ADDR_CMD "AT+ADDR=?" +#define HC08_SET_ADDR_CMD "AT+ADDR=%s" +#define HC08_GET_NAME_CMD "AT+NAME=%s" +#define HC08_SET_NAME_CMD "AT+NAME=?" + +#define HC08_OK_RESP "OK" + +#define HC08_CMD_STR_DEFAULT_SIZE 64 +#define HC08_RESP_DEFAULT_SIZE 64 + +enum Hc08AtCmd +{ + HC08_AT_CMD_DETECT = 0, + HC08_AT_CMD_DEFAULT, + HC08_AT_CMD_RESET, + HC08_AT_CMD_CLEAR, + HC08_AT_CMD_GET_DEVICE_INFO, + HC08_AT_CMD_GET_BAUDRATE, + HC08_AT_CMD_SET_BAUDRATE, + HC08_AT_CMD_SET_CONNECTABLE, + HC08_AT_CMD_GET_CONNECTABLE, + HC08_AT_CMD_SET_ROLE, + HC08_AT_CMD_GET_ROLE, + HC08_AT_CMD_SET_ADDR, + HC08_AT_CMD_GET_ADDR, + HC08_AT_CMD_SET_NAME, + HC08_AT_CMD_GET_NAME, + HC08_AT_CMD_END, +}; + +static int Hc08CheckMacHex(char *hex, int len) +{ + int i = 0; + while (i < len) + { + if ((hex[i] >= 'A' && hex[i] <= 'F') || + (hex[i] >= 'a' && hex[i] <= 'f') || + (hex[i] >= '0' && hex[i] <= '9')) + { + i++; + continue; + } + return -1; + } + return 0; +} + +//HC08 AT cmd function +static int Hc08AtConfigure(ATAgentType agent, enum Hc08AtCmd hc08_at_cmd, void *param, char *reply_info) +{ + const char *result_buf; + char *connectable, *role; + unsigned int baudrate; + char reply_ok_flag = 1; + char cmd_str[HC08_CMD_STR_DEFAULT_SIZE] = {0}; + + ATReplyType reply = CreateATReply(64); + if (NULL == reply) { + printf("Hc08AtConfigure CreateATReply failed !\n"); + return -ENOMEMORY; + } + + switch (hc08_at_cmd) + { + case HC08_AT_CMD_DETECT: + AtSetReplyEndChar(agent, 0x4F, 0x4B); + ATOrderSend(agent, REPLY_TIME_OUT, reply, HC08_DETECT_CMD); + break; + case HC08_AT_CMD_DEFAULT: + AtSetReplyEndChar(agent, 0x4F, 0x4B); + ATOrderSend(agent, REPLY_TIME_OUT, reply, HC08_DEFAULT_CMD); + break; + case HC08_AT_CMD_RESET: + AtSetReplyEndChar(agent, 0x4F, 0x4B); + ATOrderSend(agent, REPLY_TIME_OUT, reply, HC08_RESET_CMD); + break; + case HC08_AT_CMD_CLEAR: + AtSetReplyEndChar(agent, 0x4F, 0x4B); + ATOrderSend(agent, REPLY_TIME_OUT, reply, HC08_CLEAR_CMD); + break; + case HC08_AT_CMD_GET_DEVICE_INFO: + ATOrderSend(agent, REPLY_TIME_OUT, reply, HC08_GET_DEVICE_INFO); + reply_ok_flag = 0; + break; + case HC08_AT_CMD_SET_BAUDRATE: + baudrate = *(unsigned int *)param; + sprintf(cmd_str, HC08_SET_BAUDRATE_CMD, baudrate); + strcat(cmd_str, ",N"); + AtSetReplyEndChar(agent, 0x4E, 0x45); + ATOrderSend(agent, REPLY_TIME_OUT, reply, cmd_str); + reply_ok_flag = 0; + break; + case HC08_AT_CMD_GET_BAUDRATE: + AtSetReplyEndChar(agent, 0x2C, 0x4E); + ATOrderSend(agent, REPLY_TIME_OUT, reply, HC08_GET_BAUDRATE_CMD); + reply_ok_flag = 0; + break; + case HC08_AT_CMD_SET_CONNECTABLE: + connectable = (char *)param; + sprintf(cmd_str, HC08_SET_CONNECTABLE, connectable); + AtSetReplyEndChar(agent, 0x4F, 0x4B); + ATOrderSend(agent, REPLY_TIME_OUT, reply, cmd_str); + break; + case HC08_AT_CMD_GET_CONNECTABLE: + AtSetReplyEndChar(agent, 0x6C, 0x65); + ATOrderSend(agent, REPLY_TIME_OUT, reply, HC08_GET_CONNECTABLE); + reply_ok_flag = 0; + break; + case HC08_AT_CMD_SET_ROLE: + role = (char *)param; + sprintf(cmd_str, HC08_SET_ROLE_CMD, role); + AtSetReplyCharNum(agent, 1); + ATOrderSend(agent, REPLY_TIME_OUT, reply, cmd_str); + break; + case HC08_AT_CMD_GET_ROLE: + AtSetReplyCharNum(agent, 1); + ATOrderSend(agent, REPLY_TIME_OUT, reply, HC08_GET_ROLE_CMD); + reply_ok_flag = 0; + break; + // case HC08_AT_CMD_SET_ADDR: + // ATOrderSend(agent, REPLY_TIME_OUT, reply, HC08_SET_ROLE_CMD); + // break; + // case HC08_AT_CMD_GET_ADDR: + // ATOrderSend(agent, REPLY_TIME_OUT, reply, HC08_GET_ROLE_CMD); + // reply_ok_flag = 0; + // break; + // case HC08_AT_CMD_SET_NAME: + // ATOrderSend(agent, REPLY_TIME_OUT, reply, HC08_SET_NAME_CMD); + // break; + // case HC08_AT_CMD_GET_NAME: + // ATOrderSend(agent, REPLY_TIME_OUT, reply, HC08_GET_NAME_CMD); + // reply_ok_flag = 0; + // break; + default: + printf("hc08 do not support no.%d cmd\n", hc08_at_cmd); + DeleteATReply(reply); + return -1; + } + + PrivTaskDelay(200); + + result_buf = GetReplyText(reply); + + if (reply_ok_flag) { + if (!strstr(HC08_OK_RESP, result_buf)) { + printf("%u cmd get reply OK failed:get reply %s\n", hc08_at_cmd, result_buf); + } + } + + if (reply_info) { + strncpy(reply_info, result_buf, reply->reply_len); + } + + DeleteATReply(reply); + + return 0; +} + +static int Hc08Open(struct Adapter *adapter) +{ + if (INSTALL == adapter->adapter_status) { + printf("Hc08 has already been open\n"); + return 0; + } + + //step1: open hc08 serial port + adapter->fd = PrivOpen(ADAPTER_HC08_DRIVER, O_RDWR); + if (adapter->fd < 0) { + printf("Hc08Open get serial %s fd error\n", ADAPTER_HC08_DRIVER); + return -1; + } + + //step2: init AT agent + if (!adapter->agent) { + char *agent_name = "bluetooth_uart_client"; + printf("InitATAgent agent_name %s fd %u\n", agent_name, adapter->fd); + if (EOK != InitATAgent(agent_name, adapter->fd, 512)) { + printf("at agent init failed !\n"); + return -1; + } + ATAgentType at_agent = GetATAgent(agent_name); + + adapter->agent = at_agent; + + printf("Hc08Open adapter agent %p\n", adapter->agent); + } + + PrivTaskDelay(200); + + ADAPTER_DEBUG("Hc08 open done\n"); + + return 0; +} + +static int Hc08Close(struct Adapter *adapter) +{ + return 0; +} + +static int Hc08Ioctl(struct Adapter *adapter, int cmd, void *args) +{ + if (OPE_INT != cmd) { + printf("Hc08Ioctl only support OPE_INT, do not support %d\n", cmd); + return -1; + } + + char hc08_baudrate[HC08_RESP_DEFAULT_SIZE] = {0}; + uint32_t baud_rate = *((uint32_t *)args); + + struct SerialDataCfg serial_cfg; + memset(&serial_cfg, 0 ,sizeof(struct SerialDataCfg)); + serial_cfg.serial_baud_rate = baud_rate; + serial_cfg.serial_data_bits = DATA_BITS_8; + serial_cfg.serial_stop_bits = STOP_BITS_1; + serial_cfg.serial_buffer_size = SERIAL_RB_BUFSZ; + serial_cfg.serial_parity_mode = PARITY_NONE; + serial_cfg.serial_bit_order = STOP_BITS_1; + serial_cfg.serial_invert_mode = NRZ_NORMAL; +#ifdef ADAPTER_HC08_DRIVER_EXT_PORT + serial_cfg.ext_uart_no = ADAPTER_HC08_DRIVER_EXT_PORT; + serial_cfg.port_configure = PORT_CFG_INIT; +#endif + + struct PrivIoctlCfg ioctl_cfg; + ioctl_cfg.ioctl_driver_type = SERIAL_TYPE; + ioctl_cfg.args = &serial_cfg; + PrivIoctl(adapter->fd, OPE_INT, &ioctl_cfg); + + //Step1 : detect hc08 serial function + if (Hc08AtConfigure(adapter->agent, HC08_AT_CMD_DETECT, NULL, NULL) < 0) { + return -1; + } + + //Step2 : set hc08 device serial baud, hc08_set_baud send "AT+BAUD=%s" + if (Hc08AtConfigure(adapter->agent, HC08_AT_CMD_SET_BAUDRATE, args, NULL) < 0) { + return -1; + } + + PrivTaskDelay(200); + + //Step3 : show hc08 device info, hc08_get send "AT+RX" response device info + char device_info[HC08_RESP_DEFAULT_SIZE * 2] = {0}; + if (Hc08AtConfigure(adapter->agent, HC08_AT_CMD_GET_DEVICE_INFO, NULL, device_info) < 0) { + return -1; + } + + ADAPTER_DEBUG("Hc08 ioctl done\n"); + + return 0; +} + +static int Hc08SetAddr(struct Adapter *adapter, const char *ip, const char *gateway, const char *netmask) +{ + char mac_addr[HC08_RESP_DEFAULT_SIZE] = {0}; + + //Step1 : hc08_get_addr send "AT+ADDR=?" response mac "XX,XX,XX,XX,XX,XX" + if (Hc08AtConfigure(adapter->agent, HC08_AT_CMD_GET_ADDR, NULL, mac_addr) < 0) { + return -1; + } + + printf("HC08 old mac addr: %s\n", mac_addr); + + //Step2 : hc08_set_addr send "AT+ADDR=%s" response "OK" + if (!Hc08CheckMacHex((char *)gateway, 12)) { + if (Hc08AtConfigure(adapter->agent, HC08_AT_CMD_SET_ADDR, (void *)gateway, NULL) < 0) { + return -1; + } + } + + //Step3 : check mac addr, hc08_get_addr send "AT+ADDR=?" response mac "XX,XX,XX,XX,XX,XX" + if (Hc08AtConfigure(adapter->agent, HC08_AT_CMD_GET_ADDR, NULL, mac_addr) < 0) { + return -1; + } + + printf("HC08 new mac addr: %s\n", mac_addr); + + return 0; +} + +static int Hc08Connect(struct Adapter *adapter, enum NetRoleType net_role, const char *ip, const char *port, enum IpType ip_type) +{ + char connect_status[HC08_RESP_DEFAULT_SIZE] = {0}; + + //Step1 : hc08_detect send "AT" response "OK" + if (Hc08AtConfigure(adapter->agent, HC08_AT_CMD_DETECT, NULL, NULL) < 0) { + return -1; + } + + //Step2 : hc08_set_role send "AT+ROLE=%s" response "OK" + if (Hc08AtConfigure(adapter->agent, HC08_AT_CMD_SET_ROLE, ADAPTER_HC08_WORK_ROLE, NULL) < 0) { + return -1; + } + + //Step3 : hc08_connectable send "AT+CONT=0" response "OK" + if (Hc08AtConfigure(adapter->agent, HC08_AT_CMD_SET_CONNECTABLE, "0", NULL) < 0) { + return -1; + } + + //Step4 : check connectable status,hc08_connectable send "AT+CONT=?" response "Connectable" + if (Hc08AtConfigure(adapter->agent, HC08_AT_CMD_GET_CONNECTABLE, NULL, connect_status) < 0) { + return -1; + } + + printf("Hc08Connect status %s\n", connect_status); + + return 0; +} + +static int Hc08Send(struct Adapter *adapter, const void *buf, size_t len) +{ + x_err_t result = EOK; + if (adapter->agent) { + EntmSend(adapter->agent, (const char *)buf, len); + } else { + printf("Hc08Send can not find agent\n"); + } + return 0; +} + +static int Hc08Recv(struct Adapter *adapter, void *buf, size_t len) +{ + if (adapter->agent) { + return EntmRecv(adapter->agent, (char *)buf, len, 40); + } else { + printf("Hc08Recv can not find agent\n"); + } + + return -1; +} + +static int Hc08Disconnect(struct Adapter *adapter) +{ + char connect_status[HC08_RESP_DEFAULT_SIZE] = {0}; + + //Step1 : hc08_detect send "AT" response "OK" + if (Hc08AtConfigure(adapter->agent, HC08_AT_CMD_DETECT, NULL, NULL) < 0) { + return -1; + } + + //Step2 : hc08_connectable send "AT+CONT=1" response "OK" + if (Hc08AtConfigure(adapter->agent, HC08_AT_CMD_SET_CONNECTABLE, "1", NULL) < 0) { + return -1; + } + + //Step3 : check connectable status,hc08_connectable send "AT+CONT=?" response "Not-Connectable" + if (Hc08AtConfigure(adapter->agent, HC08_AT_CMD_GET_CONNECTABLE, NULL, connect_status) < 0) { + return -1; + } + + printf("Hc08Disconnect status %s\n", connect_status); + + return 0; +} + +static const struct IpProtocolDone hc08_done = +{ + .open = Hc08Open, + .close = Hc08Close, + .ioctl = Hc08Ioctl, + .setup = NULL, + .setdown = NULL, + .setaddr = Hc08SetAddr, + .setdns = NULL, + .setdhcp = NULL, + .ping = NULL, + .netstat = NULL, + .connect = Hc08Connect, + .send = Hc08Send, + .recv = Hc08Recv, + .disconnect = Hc08Disconnect, +}; + +AdapterProductInfoType Hc08Attach(struct Adapter *adapter) +{ + struct AdapterProductInfo *product_info = PrivMalloc(sizeof(struct AdapterProductInfo)); + if (!product_info) { + printf("Hc08Attach malloc product_info error\n"); + free(product_info); + return NULL; + } + + if ("M" == ADAPTER_HC08_WORK_ROLE) { + adapter->net_role = MASTER; + } else if ("S" == ADAPTER_HC08_WORK_ROLE) { + adapter->net_role = SLAVE; + } else { + adapter->net_role = ROLE_NONE; + } + + strcpy(product_info->model_name, ADAPTER_BLUETOOTH_HC08); + + product_info->model_done = (void *)&hc08_done; + + return product_info; +} \ No newline at end of file diff --git a/APP_Framework/Framework/connection/ethernet/Kconfig b/APP_Framework/Framework/connection/ethernet/Kconfig new file mode 100644 index 0000000..cfcffc9 --- /dev/null +++ b/APP_Framework/Framework/connection/ethernet/Kconfig @@ -0,0 +1,9 @@ +config ADAPTER_HFA21_ETHERNET + help + Please check HFA21 can only work for adapter_wifi or adapter_ethernet in the meantime! + bool "Using ethernet adapter device HFA21" + default n + +if ADAPTER_HFA21_ETHERNET + source "$APP_DIR/Framework/connection/ethernet/hfa21_ethernet/Kconfig" +endif diff --git a/APP_Framework/Framework/connection/ethernet/Makefile b/APP_Framework/Framework/connection/ethernet/Makefile new file mode 100644 index 0000000..cb71063 --- /dev/null +++ b/APP_Framework/Framework/connection/ethernet/Makefile @@ -0,0 +1,7 @@ +SRC_FILES := adapter_ethernet.c + +ifeq ($(CONFIG_ADAPTER_HFA21_ETHERNET),y) + SRC_DIR += hfa21_ethernet +endif + +include $(KERNEL_ROOT)/compiler.mk diff --git a/APP_Framework/Framework/connection/ethernet/adapter_ethernet.c b/APP_Framework/Framework/connection/ethernet/adapter_ethernet.c new file mode 100644 index 0000000..239472e --- /dev/null +++ b/APP_Framework/Framework/connection/ethernet/adapter_ethernet.c @@ -0,0 +1,124 @@ +/* +* Copyright (c) 2020 AIIT XUOS Lab +* XiUOS is licensed under Mulan PSL v2. +* You can use this software according to the terms and conditions of the Mulan PSL v2. +* You may obtain a copy of Mulan PSL v2 at: +* http://license.coscl.org.cn/MulanPSL2 +* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, +* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, +* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. +* See the Mulan PSL v2 for more details. +*/ + +/** + * @file adapter_ethernet.c + * @brief Implement the connection ethernet adapter function + * @version 1.1 + * @author AIIT XUOS Lab + * @date 2021.10.15 + */ + +#include + +#ifdef ADAPTER_HFA21_ETHERNET +extern AdapterProductInfoType Hfa21EthernetAttach(struct Adapter *adapter); +#endif + +static int AdapterEthernetRegister(struct Adapter *adapter) +{ + int ret = 0; + + strncpy(adapter->name, ADAPTER_ETHERNET_NAME, NAME_NUM_MAX); + + adapter->net_protocol = IP_PROTOCOL; + adapter->adapter_status = UNREGISTERED; + + ret = AdapterDeviceRegister(adapter); + if (ret < 0) { + printf("AdapterEthernet register error\n"); + return -1; + } + + return ret; +} + +int AdapterEthernetInit(void) +{ + int ret = 0; + + struct Adapter *adapter = PrivMalloc(sizeof(struct Adapter)); + if (!adapter) { + printf("AdapterEthernetInit malloc error\n"); + PrivFree(adapter); + return -1; + } + + memset(adapter, 0, sizeof(struct Adapter)); + + ret = AdapterEthernetRegister(adapter); + if (ret < 0) { + printf("AdapterEthernetInit register ethernet adapter error\n"); + PrivFree(adapter); + return -1; + } + +#ifdef ADAPTER_HFA21_ETHERNET + AdapterProductInfoType product_info = Hfa21EthernetAttach(adapter); + if (!product_info) { + printf("AdapterEthernetInit hfa21 attach error\n"); + PrivFree(adapter); + return -1; + } + + adapter->product_info_flag = 1; + adapter->info = product_info; + adapter->done = product_info->model_done; + +#endif + + return ret; +} + +/******************ethernet TEST*********************/ +int AdapterEthernetTest(void) +{ + int baud_rate = BAUD_RATE_57600; + + struct Adapter *adapter = AdapterDeviceFindByName(ADAPTER_ETHERNET_NAME); + +#ifdef ADAPTER_HFA21_ETHERNET + + char ethernet_recv_msg[128] = {0}; + int i, len = 0; + const char *ethernet_msg = "Adapter Ethernet Test"; + + AdapterDeviceOpen(adapter); + AdapterDeviceControl(adapter, OPE_INT, &baud_rate); + + AdapterDeviceSetUp(adapter); + + const char *ip = "10.10.100.50"; + const char *port = "12345"; + enum NetRoleType net_role = CLIENT;//SERVER + enum IpType ip_type = IPV4; + AdapterDeviceConnect(adapter, net_role, ip, port, ip_type); + + printf("ready to test data transfer\n"); + + len = strlen(ethernet_msg); + for (i = 0;i < 10; i ++) { + printf("AdapterEthernetTest send %s\n", ethernet_msg); + AdapterDeviceSend(adapter, ethernet_msg, len); + PrivTaskDelay(4000); + } + + while (1) { + AdapterDeviceRecv(adapter, ethernet_recv_msg, 128); + printf("AdapterEthernetTest recv %s\n", ethernet_recv_msg); + memset(ethernet_recv_msg, 0, 128); + } +#endif + + return 0; +} +SHELL_EXPORT_CMD(SHELL_CMD_PERMISSION(0)|SHELL_CMD_TYPE(SHELL_TYPE_CMD_FUNC)|SHELL_CMD_PARAM_NUM(0)|SHELL_CMD_DISABLE_RETURN, AdapterEthernetTest, AdapterEthernetTest, show adapter ethernet information); diff --git a/APP_Framework/Framework/connection/ethernet/hfa21_ethernet/Kconfig b/APP_Framework/Framework/connection/ethernet/hfa21_ethernet/Kconfig new file mode 100644 index 0000000..2efc7a0 --- /dev/null +++ b/APP_Framework/Framework/connection/ethernet/hfa21_ethernet/Kconfig @@ -0,0 +1,33 @@ +config ADAPTER_ETHERNET_HFA21 + string "HFA21 ETHERNET adapter name" + default "hfa21_ethernet" + +if ADD_XIZI_FETURES + + config ADAPTER_HFA21_DRIVER_EXTUART + bool "Using extra uart to support ethernet" + default n + + config ADAPTER_HFA21_DRIVER + string "HFA21 device uart driver path" + default "/dev/usart3_dev3" + depends on !ADAPTER_HFA21_DRIVER_EXTUART + + if ADAPTER_HFA21_DRIVER_EXTUART + config ADAPTER_HFA21_DRIVER + string "HFA21 device extra uart driver path" + default "/dev/extuart_dev6" + + config ADAPTER_HFA21_DRIVER_EXT_PORT + int "if HFA21 device using extuart, choose port" + default "6" + endif +endif + +if ADD_NUTTX_FETURES + +endif + +if ADD_RTTHREAD_FETURES + +endif diff --git a/APP_Framework/Framework/connection/ethernet/hfa21_ethernet/Makefile b/APP_Framework/Framework/connection/ethernet/hfa21_ethernet/Makefile new file mode 100644 index 0000000..336c07a --- /dev/null +++ b/APP_Framework/Framework/connection/ethernet/hfa21_ethernet/Makefile @@ -0,0 +1,3 @@ +SRC_FILES := hfa21_ethernet.c + +include $(KERNEL_ROOT)/compiler.mk diff --git a/APP_Framework/Framework/connection/ethernet/hfa21_ethernet/hfa21_ethernet.c b/APP_Framework/Framework/connection/ethernet/hfa21_ethernet/hfa21_ethernet.c new file mode 100644 index 0000000..07bc333 --- /dev/null +++ b/APP_Framework/Framework/connection/ethernet/hfa21_ethernet/hfa21_ethernet.c @@ -0,0 +1,453 @@ +/* +* Copyright (c) 2020 AIIT XUOS Lab +* XiUOS is licensed under Mulan PSL v2. +* You can use this software according to the terms and conditions of the Mulan PSL v2. +* You may obtain a copy of Mulan PSL v2 at: +* http://license.coscl.org.cn/MulanPSL2 +* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, +* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, +* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. +* See the Mulan PSL v2 for more details. +*/ + +/** + * @file hfa21_ethernet.c + * @brief Implement the connection ethernet adapter function, using HFA21 device + * @version 1.1 + * @author AIIT XUOS Lab + * @date 2021.10.15 + */ + +#include +#include + +#define HFA21_ETHERNET_AT_CMD "+++" +#define HFA21_ETHERNET_AT_CONFIRM_CMD "a" +#define HFA21_ETHERNET_AT_FCLR_CMD "AT+FCLR\r" +#define HFA21_ETHERNET_AT_FEPHY_CMD "AT+FEPHY=on\r" +#define HFA21_ETHERNET_AT_ENABLE_WANN_CMD "AT+FVEW=enable\r" +#define HFA21_ETHERNET_AT_DISABLE_WANN_CMD "AT+FVEW=disable\r" +#define HFA21_ETHERNET_AT_RELD_CMD "AT+RELD\r" +#define HFA21_ETHERNET_AT_WMODE_CMD "AT+WMODE\r" +#define HFA21_ETHERNET_AT_WANN_CMD "AT+WANN\r" +#define HFA21_ETHERNET_AT_SET_WANN_CMD "AT+WANN=%s,%s,%s,%s\r" +#define HFA21_ETHERNET_AT_PING_CMD "AT+PING=%s\r" +#define HFA21_ETHERNET_AT_NETP_CMD "AT+NETP=%s,%s,%s,%s\r" +#define HFA21_ETHERNET_AT_REBOOT_CMD "AT+Z\r" + +#define HFA21_ETHERNET_OK_REPLY "+ok" + +static int Hfa21EthernetSetDown(struct Adapter *adapter_at); + +/** + * @description: enter AT command mode + * @param at_agent - ethernet device agent pointer + * @return success: 0 + */ +static int Hfa21EthernetInitAtCmd(ATAgentType at_agent) +{ + ATOrderSend(at_agent, REPLY_TIME_OUT, NULL, HFA21_ETHERNET_AT_CMD); + PrivTaskDelay(100); + + ATOrderSend(at_agent, REPLY_TIME_OUT, NULL, HFA21_ETHERNET_AT_CONFIRM_CMD); + PrivTaskDelay(500); + + return 0; +} + +/** + * @description: Open HFA21 uart function + * @param adapter - ethernet device pointer + * @return success: 0, failure: -1 + */ +static int Hfa21EthernetOpen(struct Adapter *adapter) +{ + /*step1: open hfa21 serial port*/ + adapter->fd = PrivOpen(ADAPTER_HFA21_DRIVER, O_RDWR); + if (adapter->fd < 0) { + printf("Hfa21EthernetOpen get serial %s fd error\n", ADAPTER_HFA21_DRIVER); + return -1; + } + + /*step2: init AT agent*/ + if (!adapter->agent) { + char *agent_name = "ethernet_uart_client"; + if (EOK != InitATAgent(agent_name, adapter->fd, 512)) { + printf("at agent init failed !\n"); + return -1; + } + ATAgentType at_agent = GetATAgent(agent_name); + + adapter->agent = at_agent; + } + + ADAPTER_DEBUG("Hfa21Ethernet open done\n"); + + return 0; +} + +/** + * @description: Close HFA21 ethernet and uart function + * @param adapter - ethernet device pointer + * @return success: 0 + */ +static int Hfa21EthernetClose(struct Adapter *adapter) +{ + return Hfa21EthernetSetDown(adapter); +} + +/** + * @description: send data to adapter + * @param adapter - ethernet device pointer + * @param data - data buffer + * @param data - data length + * @return success: 0 + */ +static int Hfa21EthernetSend(struct Adapter *adapter, const void *data, size_t len) +{ + int result = 0; + if (adapter->agent) { + EntmSend(adapter->agent, (const char *)data, len); + }else { + printf("Hfa21EthernetSend can not find agent!\n"); + } + +__exit: + + return result; +} + +/** + * @description: receive data from adapter + * @param adapter - ethernet device pointer + * @param data - data buffer + * @param data - data length + * @return success: 0 + */ +static int Hfa21EthernetReceive(struct Adapter *adapter, void *rev_buffer, size_t buffer_len) +{ + int result = 0; + + if (adapter->agent) { + return EntmRecv(adapter->agent, (char *)rev_buffer, buffer_len, 40000); + } else { + printf("Hfa21EthernetReceive can not find agent!\n"); + } + +__exit: + + return result; +} + +/** + * @description: connnect Ethernet to internet + * @param adapter - Ethernet device pointer + * @return success: 0 + */ +static int Hfa21EthernetSetUp(struct Adapter *adapter) +{ + int ret = 0; + + AtSetReplyLrEnd(adapter->agent, 1); + + /* wait hfa21 device startup finish */ + PrivTaskDelay(5000); + + /*Step1 : enter AT mode*/ + Hfa21EthernetInitAtCmd(adapter->agent); + + PrivTaskDelay(1000); + + /*Step2 : FCLR reboot*/ + ret = AtCmdConfigAndCheck(adapter->agent, HFA21_ETHERNET_AT_FCLR_CMD, HFA21_ETHERNET_OK_REPLY); + if (ret < 0) { + goto __exit; + } + + PrivTaskDelay(10000); + + Hfa21EthernetInitAtCmd(adapter->agent); + + /*Step3 : FEPHY enable phy function*/ + ret = AtCmdConfigAndCheck(adapter->agent, HFA21_ETHERNET_AT_FEPHY_CMD, HFA21_ETHERNET_OK_REPLY); + if (ret < 0) { + goto __exit; + } + + /*Step4 : FVEW disable WANN function, ethernet work at LANN mode*/ + ret = AtCmdConfigAndCheck(adapter->agent, HFA21_ETHERNET_AT_DISABLE_WANN_CMD, HFA21_ETHERNET_OK_REPLY); + if (ret < 0) { + goto __exit; + } + + /*Step5 : RELD enable F-AT cmd*/ + ret = AtCmdConfigAndCheck(adapter->agent, HFA21_ETHERNET_AT_RELD_CMD, HFA21_ETHERNET_OK_REPLY); + if (ret < 0) { + goto __exit; + } + + PrivTaskDelay(10000); + + Hfa21EthernetInitAtCmd(adapter->agent); + + /*Step6 : AT+WMODE check work mode, AP or STA*/ + ret = AtCmdConfigAndCheck(adapter->agent, HFA21_ETHERNET_AT_WMODE_CMD, HFA21_ETHERNET_OK_REPLY); + if (ret < 0) { + goto __exit; + } + + /*Step7 : AT+WANN check if get ip、netmask、gateway*/ + ret = AtCmdConfigAndCheck(adapter->agent, HFA21_ETHERNET_AT_WANN_CMD, HFA21_ETHERNET_OK_REPLY); + if (ret < 0) { + goto __exit; + } + + /*Step8 : AT+Z reboot hfa21 device*/ + ret = AtCmdConfigAndCheck(adapter->agent, HFA21_ETHERNET_AT_REBOOT_CMD, HFA21_ETHERNET_OK_REPLY); + if (ret < 0) { + goto __exit; + } + + PrivTaskDelay(10000); + + return ret; + +__exit: + Hfa21EthernetSetDown(adapter); + + return -1; +} + +/** + * @description: disconnnect ethernet from internet + * @param adapter - ethernet device pointer + * @return success: 0 + */ +static int Hfa21EthernetSetDown(struct Adapter *adapter) +{ + Hfa21EthernetInitAtCmd(adapter->agent); + + ATOrderSend(adapter->agent, REPLY_TIME_OUT, NULL, HFA21_ETHERNET_AT_FCLR_CMD); + PrivTaskDelay(20000); + + return 0; +} + +/** + * @description: set ethernet ip/gateway/netmask address(in sta mode) working at WANN mode + * @param adapter - ethernet device pointer + * @param ip - ip address + * @param gateway - gateway address + * @param netmask - netmask address + * @return success: 0, failure: -ENOMEMORY or -1 + */ +static int Hfa21EthernetSetAddr(struct Adapter *adapter, const char *ip, const char *gateway, const char *netmask) +{ + int ret = 0; + uint8_t hfa21_ethernet_cmd[64]; + + /*Step1 : enter AT mode*/ + Hfa21EthernetInitAtCmd(adapter->agent); + + /*Step2 : set mode、ip、netmask and gateway*/ + memset(hfa21_ethernet_cmd, 0, sizeof(hfa21_ethernet_cmd)); + sprintf(hfa21_ethernet_cmd, HFA21_ETHERNET_AT_SET_WANN_CMD, "DHCP", ip, netmask, gateway); + ret = AtCmdConfigAndCheck(adapter->agent, hfa21_ethernet_cmd, HFA21_ETHERNET_OK_REPLY); + if (ret < 0) { + goto __exit; + } + + /*Step3 : AT+WANN check if set ip、netmask、gateway successfully*/ + ret = AtCmdConfigAndCheck(adapter->agent, HFA21_ETHERNET_AT_WANN_CMD, HFA21_ETHERNET_OK_REPLY); + if (ret < 0) { + goto __exit; + } + + /*Step4 : AT+Z reboot hfa21 device*/ + ret = AtCmdConfigAndCheck(adapter->agent, HFA21_ETHERNET_AT_REBOOT_CMD, HFA21_ETHERNET_OK_REPLY); + if (ret < 0) { + goto __exit; + } + + PrivTaskDelay(10000); + + return ret; + +__exit: + Hfa21EthernetSetDown(adapter); + + return -1; +} + +/** + * @description: ethernet ping function + * @param adapter - ethernet device pointer + * @param destination - domain name or ip address + * @return success: 0, failure: -1 + */ +static int Hfa21EthernetPing(struct Adapter *adapter, const char *destination) +{ + int ret = 0; + + char *ping_result = (char *) PrivCalloc(1, 17); + char *dst = (char *) PrivCalloc(1, 17); + + strcpy(dst, destination); + strcat(dst, "\r"); + + printf("Hfa21EthernetPing [%s]\n", dst); + + /*Step1 : enter AT mode*/ + Hfa21EthernetInitAtCmd(adapter->agent); + + /*Step2 : ping dst ip address*/ + ret = AtCmdConfigAndCheck(adapter->agent, HFA21_ETHERNET_AT_PING_CMD, HFA21_ETHERNET_OK_REPLY); + if (ret < 0) { + goto __exit; + } + + /*Step3 : AT+Z reboot hfa21 device*/ + ret = AtCmdConfigAndCheck(adapter->agent, HFA21_ETHERNET_AT_REBOOT_CMD, HFA21_ETHERNET_OK_REPLY); + if (ret < 0) { + goto __exit; + } + + return ret; + +__exit: + Hfa21EthernetSetDown(adapter); + + return -1; +} + +/** + * @description: ethernet connect function + * @param adapter - ethernet device pointer + * @param net_role - net role, CLIENT or SERVER + * @param ip - ip address + * @param port - port num + * @param ip_type - ip type, IPV4 or IPV6 + * @return success: 0, failure: -1 + */ +static int Hfa21EthernetConnect(struct Adapter *adapter, enum NetRoleType net_role, const char *ip, const char *port, enum IpType ip_type) +{ + int ret = 0; + char hfa21_ethernet_cmd[128]; + char net_role_string[7] = {0}; + + /*Step1 : enter AT mode*/ + Hfa21EthernetInitAtCmd(adapter->agent); + + if (CLIENT == net_role) { + strcpy(net_role_string, "CLIENT"); + } else if (SERVER == net_role) { + strcpy(net_role_string, "SERVER"); + } else { + printf("Hfa21EthernetConnect do not support %d net type\n", net_role); + return -1; + } + + if (IPV4 == ip_type) { + /*to do*/ + } else if (IPV6 == ip_type) { + /*to do*/ + } else { + printf("Hfa21EthernetConnect do not support %d ip type\n", ip_type); + return -1; + } + + /*Step2 : create tcp connect*/ + memset(hfa21_ethernet_cmd, 0, sizeof(hfa21_ethernet_cmd)); + sprintf(hfa21_ethernet_cmd, HFA21_ETHERNET_AT_NETP_CMD, "TCP", net_role_string, port, ip); + ret = AtCmdConfigAndCheck(adapter->agent, hfa21_ethernet_cmd, HFA21_ETHERNET_OK_REPLY); + if (ret < 0) { + goto __exit; + } + + adapter->net_role = net_role; + + /*Step3 : AT+Z reboot hfa21 device*/ + ret = AtCmdConfigAndCheck(adapter->agent, HFA21_ETHERNET_AT_REBOOT_CMD, HFA21_ETHERNET_OK_REPLY); + if (ret < 0) { + goto __exit; + } + + PrivTaskDelay(10000); + + return ret; + +__exit: + Hfa21EthernetSetDown(adapter); + + return -1; +} + +static int Hfa21EthernetIoctl(struct Adapter *adapter, int cmd, void *args) +{ + if (OPE_INT != cmd) { + printf("Hfa21EthernetIoctl only support OPE_INT, do not support %d\n", cmd); + return -1; + } + + uint32_t baud_rate = *((uint32_t *)args); + + struct SerialDataCfg serial_cfg; + memset(&serial_cfg, 0 ,sizeof(struct SerialDataCfg)); + serial_cfg.serial_baud_rate = baud_rate; + serial_cfg.serial_data_bits = DATA_BITS_8; + serial_cfg.serial_stop_bits = STOP_BITS_1; + serial_cfg.serial_buffer_size = SERIAL_RB_BUFSZ; + serial_cfg.serial_parity_mode = PARITY_NONE; + serial_cfg.serial_bit_order = BIT_ORDER_LSB; + serial_cfg.serial_invert_mode = NRZ_NORMAL; +#ifdef ADAPTER_HFA21_DRIVER_EXT_PORT + serial_cfg.ext_uart_no = ADAPTER_HFA21_DRIVER_EXT_PORT; + serial_cfg.port_configure = PORT_CFG_INIT; +#endif + + struct PrivIoctlCfg ioctl_cfg; + ioctl_cfg.ioctl_driver_type = SERIAL_TYPE; + ioctl_cfg.args = &serial_cfg; + PrivIoctl(adapter->fd, OPE_INT, &ioctl_cfg); + + printf("Hfa21EthernetIoctl success\n"); + return 0; +} + +static const struct IpProtocolDone hfa21_ethernet_done = +{ + .open = Hfa21EthernetOpen, + .close = Hfa21EthernetClose, + .ioctl = Hfa21EthernetIoctl, + .setup = Hfa21EthernetSetUp, + .setdown = Hfa21EthernetSetDown, + .setaddr = Hfa21EthernetSetAddr, + .setdns = NULL, + .setdhcp = NULL, + .ping = Hfa21EthernetPing, + .netstat = NULL, + .connect = Hfa21EthernetConnect, + .send = Hfa21EthernetSend, + .recv = Hfa21EthernetReceive, + .disconnect = NULL, +}; + +/** + * @description: Register ethernet device hfa21 + * @return success: product_info, failure: NULL + */ +AdapterProductInfoType Hfa21EthernetAttach(struct Adapter *adapter) +{ + struct AdapterProductInfo *product_info = PrivMalloc(sizeof(struct AdapterProductInfo)); + if (!product_info) { + printf("Hfa21EthernetAttach Attach malloc product_info error\n"); + PrivFree(product_info); + return NULL; + } + + strcpy(product_info->model_name, ADAPTER_ETHERNET_HFA21); + + product_info->model_done = (void *)&hfa21_ethernet_done; + + return product_info; +} diff --git a/APP_Framework/Framework/connection/industrial_ethernet/Kconfig b/APP_Framework/Framework/connection/industrial_ethernet/Kconfig new file mode 100644 index 0000000..0826acf --- /dev/null +++ b/APP_Framework/Framework/connection/industrial_ethernet/Kconfig @@ -0,0 +1,7 @@ +config CONNECTION_ADAPTER_ETHERCAT + bool "Using ethercat on industrial_ethernet adapter device" + default n + + if CONNECTION_ADAPTER_ETHERCAT + source "$APP_DIR/Framework/connection/industrial_ethernet/ethercat/Kconfig" + endif diff --git a/APP_Framework/Framework/connection/industrial_ethernet/Makefile b/APP_Framework/Framework/connection/industrial_ethernet/Makefile new file mode 100644 index 0000000..e9ec8be --- /dev/null +++ b/APP_Framework/Framework/connection/industrial_ethernet/Makefile @@ -0,0 +1,5 @@ +ifeq ($(CONFIG_CONNECTION_ADAPTER_ETHERCAT),y) + SRC_DIR += ethercat +endif + +include $(KERNEL_ROOT)/compiler.mk diff --git a/APP_Framework/Framework/connection/industrial_ethernet/ethercat/Kconfig b/APP_Framework/Framework/connection/industrial_ethernet/ethercat/Kconfig new file mode 100644 index 0000000..b294c33 --- /dev/null +++ b/APP_Framework/Framework/connection/industrial_ethernet/ethercat/Kconfig @@ -0,0 +1,11 @@ +config ADAPTER_HFA21_ETHERCAT + depends on ADAPTER_HFA21_ETHERNET # ADAPTER_HFA21_WIFI + help + Ethercat is dependant on Ethernet. Please enable hfa21 ethernet first. And this is a software-defined experiment module, without supports on ECS and on-the-fly. + bool "Using ethercat on ethernet adapter device HFA21" + default n + + if ADAPTER_HFA21_ETHERCAT + source "$APP_DIR/Framework/connection/industrial_ethernet/ethercat/hfa21_ethercat/Kconfig" + endif + diff --git a/APP_Framework/Framework/connection/industrial_ethernet/ethercat/Makefile b/APP_Framework/Framework/connection/industrial_ethernet/ethercat/Makefile new file mode 100644 index 0000000..4dc2429 --- /dev/null +++ b/APP_Framework/Framework/connection/industrial_ethernet/ethercat/Makefile @@ -0,0 +1,7 @@ +SRC_FILES := adapter_ethercat.c + +ifeq ($(CONFIG_ADAPTER_HFA21_ETHERCAT),y) + SRC_DIR += hfa21_ethercat +endif + +include $(KERNEL_ROOT)/compiler.mk diff --git a/APP_Framework/Framework/connection/industrial_ethernet/ethercat/adapter_ethercat.c b/APP_Framework/Framework/connection/industrial_ethernet/ethercat/adapter_ethercat.c new file mode 100644 index 0000000..05c4b3c --- /dev/null +++ b/APP_Framework/Framework/connection/industrial_ethernet/ethercat/adapter_ethercat.c @@ -0,0 +1,208 @@ +/* + * Copyright (c) 2020 AIIT XUOS Lab + * XiUOS is licensed under Mulan PSL v2. + * You can use this software according to the terms and conditions of the Mulan PSL v2. + * You may obtain a copy of Mulan PSL v2 at: + * http://license.coscl.org.cn/MulanPSL2 + * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, + * EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, + * MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. + * See the Mulan PSL v2 for more details. + */ + +/** + * @file adapter_ethercat.c + * @brief Implement the connection ethercat adapter function, reuse the ethernet implementations + * @version 1.1 + * @author AIIT XUOS Lab + * @date 2021.10.15 + */ + +#include +#include + +#ifdef ADAPTER_HFA21_ETHERCAT +extern AdapterProductInfoType Hfa21EthercatAttach(struct Adapter *adapter); +#endif + +/** + * @description: clear the datagram in ethercat frame, do not free the frame itself, since it may be a memory space on stack + * @param frame - ethercat frame pointer + */ +void EcatClear(EcatFramePtr frame) +{ + EcatDatagramPtr datagram = frame->datagram; + while (datagram) + { + EcatDatagramPtr temp = datagram->next; + PrivFree(datagram->data); + PrivFree(datagram); + datagram = temp; + } + memset(frame, 0, sizeof(EcatFrame)); + frame->header.length = 2; // 2 bytes for the ethercat header + frame->header.res = 1; + frame->header.type = 0b1001; +} + +/** + * @description: receive data from adapter + * @param frame - ethercat frame pointer + * @param address - ethercat address + * @param data - data to be carried inside frame + * @param data_len - length of provided `data` + * @return success: 0, else return error code. + */ +int EcatAppend(EcatFramePtr frame, EcatAddress address, uint8_t *data, uint16_t data_len) +{ + EcatDatagramPtr datagram = frame->datagram; + if (!datagram) + { + datagram = PrivMalloc(sizeof(EcatDatagram)); + if (!datagram) + { + printf("EcatAppend malloc error\n"); + return -1; + } + memset(datagram, 0, sizeof(EcatDatagram)); + frame->datagram = datagram; + } + else + { + while (datagram->next) + { + datagram = datagram->next; + } + datagram->header.m = 1; // indcate the datagram is not the last one + datagram->next = PrivMalloc(sizeof(EcatDatagram)); + if (!datagram->next) + { + printf("EcatAppend malloc error\n"); + return -1; + } + memset(datagram->next, 0, sizeof(EcatDatagram)); + datagram = datagram->next; + } + datagram->header.address = address; + datagram->header.length = data_len; + datagram->data = data; + datagram->work_counter++; + frame->header.length += sizeof(datagram->header) + data_len + sizeof(datagram->work_counter); + printf("EcatAppend change length to %d\n", frame->header.length); + return 0; +} + +/** + * @description: find datagram for self and update its content + * @param frame - ethercat frame pointer + * @param address - ethercat address + * @param data - data to be carried inside frame + * @param data_len - length of provided `data` + * @return success: 0, else return error code. + */ +int EcatUpdate(EcatFramePtr frame, uint8_t *data, uint16_t data_len) +{ + EcatDatagramPtr datagram = frame->datagram; + if (!datagram) + { + printf("EcatUpdate error: null datagram.\n"); + return -1; + } + while (datagram) + { + if (datagram->self) + { + datagram->header.length = data_len; + frame->header.length -= strlen(datagram->data); + datagram->data = data; + frame->header.length += data_len; + datagram->work_counter++; + return 0; + } + else + { + datagram = datagram->next; + } + } + printf("EcatUpdate error: cannot find datagram for node itself.\n"); + return -2; +} + +static int AdapterEthercatRegister(struct Adapter *adapter) +{ + int ret = 0; + + strncpy(adapter->name, ADAPTER_ETHERCAT_NAME, NAME_NUM_MAX); + + adapter->net_protocol = IP_PROTOCOL; + adapter->adapter_status = UNREGISTERED; + + ret = AdapterDeviceRegister(adapter); + if (ret < 0) + { + printf("AdapterEthercat register error\n"); + return -1; + } + + return ret; +} + +int AdapterEthercatInit(void) +{ + int ret = 0; + + struct Adapter *adapter = PrivMalloc(sizeof(struct Adapter)); + if (!adapter) + { + printf("AdapterEthercatInit malloc error\n"); + PrivFree(adapter); + return -1; + } + + memset(adapter, 0, sizeof(struct Adapter)); + + ret = AdapterEthercatRegister(adapter); + if (ret < 0) + { + printf("AdapterEthercatInit register ethercat adapter error\n"); + PrivFree(adapter); + return -1; + } + +#ifdef ADAPTER_HFA21_ETHERCAT + AdapterProductInfoType product_info = Hfa21EthercatAttach(adapter); + if (!product_info) + { + printf("AdapterEthercatInit hfa21 attach error\n"); + PrivFree(adapter); + return -1; + } + + adapter->product_info_flag = 1; + adapter->info = product_info; + adapter->done = product_info->model_done; + +#endif + + return ret; +} + +/******************ethercat TEST*********************/ +extern int Hfa21EthercatSlaveTest(struct Adapter *adapter); +extern int Hfa21EthercatMasterTest(struct Adapter *adapter); + +int AdapterEthercatTest(void) +{ + struct Adapter *adapter = AdapterDeviceFindByName(ADAPTER_ETHERCAT_NAME); + +#ifdef ADAPTER_HFA21_ETHERCAT +#ifdef AS_ETHERCAT_SLAVE_ROLE + Hfa21EthercatSlaveTest(adapter); +#else // AS_ETHERCAT_MASTER_ROLE + Hfa21EthercatMasterTest(adapter); +#endif +#endif + + return 0; +} +SHELL_EXPORT_CMD(SHELL_CMD_PERMISSION(0) | SHELL_CMD_TYPE(SHELL_TYPE_CMD_FUNC) | SHELL_CMD_PARAM_NUM(0) | SHELL_CMD_DISABLE_RETURN, AdapterEthercatTest, AdapterEthercatTest, show adapter ethercat information); diff --git a/APP_Framework/Framework/connection/industrial_ethernet/ethercat/ethercat.h b/APP_Framework/Framework/connection/industrial_ethernet/ethercat/ethercat.h new file mode 100644 index 0000000..77b6559 --- /dev/null +++ b/APP_Framework/Framework/connection/industrial_ethernet/ethercat/ethercat.h @@ -0,0 +1,103 @@ +#ifndef ETHERCAT_H +#define ETHERCAT_H + +#include + +#define BIG_ENDIAN_PACK __attribute__((packed, scalar_storage_order("big-endian"))) +#define LITTLE_ENDIAN_PACK __attribute__((packed, scalar_storage_order("little-endian"))) +#define ETHERCAT_PORT "34980" // 0x88A4 +#define MAX_FRAME_LEN 1500 +#define MIN_FRAME_LEN 14 + +typedef union BIG_ENDIAN_PACK +{ + struct BIG_ENDIAN_PACK + { + uint16_t length : 11; + uint16_t res : 1; + uint16_t type : 4; + }; + uint16_t header; +} EcatHeader, *EcatHeaderPtr; + +#define ECAT_HEADER_LENGTH 2 + +typedef union BIG_ENDIAN_PACK +{ + struct BIG_ENDIAN_PACK + { + uint16_t position; + uint16_t pos_offset; + }; // Position Addressing + struct BIG_ENDIAN_PACK + { + uint16_t address; + uint16_t addr_offset; + }; // Node Addressing + uint32_t logical; +} EcatAddress, *EcatAddressPtr; + +#define ECAT_ADDRESS_LENGTH 4 + +typedef struct +{ + uint8_t cmd; + uint8_t idx; + EcatAddress address; + union BIG_ENDIAN_PACK + { + struct BIG_ENDIAN_PACK + { + uint16_t length : 11; + uint16_t r : 3; + uint16_t c : 1; + uint16_t m : 1; // followed by more datagrams or not + }; + uint16_t suffix; // for easy parse + }; + uint16_t irq : 16; +} EcatDataHeader, *EcatDataHeaderPtr; + +#define ECAT_DATA_HEADER_LENGTH 10 + +typedef struct +{ + // frame data + EcatDataHeader header; // 10 bytes + uint8_t *data; // 0-1486 bytes + uint16_t work_counter; // 2bytes + // utilities + uint8_t self; // indicating this datagram is mine + void *next; // EcatDatagramPtr +} EcatDatagram, *EcatDatagramPtr; + +typedef struct +{ + EcatHeader header; // 2 bytes + EcatDatagramPtr datagram; // 12-1470 bytes +} EcatFrame, *EcatFramePtr; + +extern EcatFrame ecat_data; + +void EcatClear(EcatFramePtr frame); +int EcatAppend(EcatFramePtr frame, EcatAddress address, uint8_t *data, uint16_t data_len); +int EcatUpdate(EcatFramePtr frame, uint8_t *data, uint16_t data_len); + +#define READ8(buffer, offset) (((uint8_t *)buffer)[offset++]) +#define READ16(buffer, offset) ((uint16_t)((uint8_t *)buffer)[offset++] << 8 | (uint16_t)((uint8_t *)buffer)[offset++]) +#define READ32(buffer, offset) (uint32_t)((uint8_t *)buffer)[offset++] << 24 | \ + (uint32_t)((uint8_t *)buffer)[offset++] << 16 | \ + (uint32_t)((uint8_t *)buffer)[offset++] << 8 | \ + (uint32_t)((uint8_t *)buffer)[offset++] + +#define WRITE8(buffer, offset, value) ((uint8_t *)buffer)[offset++] = (uint8_t)(value & 0xFF); +#define WRITE16(buffer, offset, value) \ + ((uint8_t *)buffer)[offset++] = (uint8_t)(value >> 8 & 0xFF); \ + ((uint8_t *)buffer)[offset++] = (uint8_t)(value & 0xFF); +#define WRITE32(buffer, offset, value) \ + ((uint8_t *)buffer)[offset++] = (uint8_t)(value >> 24 & 0xFF); \ + ((uint8_t *)buffer)[offset++] = (uint8_t)(value >> 16 & 0xFF); \ + ((uint8_t *)buffer)[offset++] = (uint8_t)(value >> 8 & 0xFF); \ + ((uint8_t *)buffer)[offset++] = (uint8_t)(value & 0xFF); + +#endif \ No newline at end of file diff --git a/APP_Framework/Framework/connection/industrial_ethernet/ethercat/hfa21_ethercat/Kconfig b/APP_Framework/Framework/connection/industrial_ethernet/ethercat/hfa21_ethercat/Kconfig new file mode 100644 index 0000000..396cd43 --- /dev/null +++ b/APP_Framework/Framework/connection/industrial_ethernet/ethercat/hfa21_ethercat/Kconfig @@ -0,0 +1,43 @@ +config ADAPTER_ETHERCAT_HFA21 + string "HFA21 EtherCAT adapter name" + default "hfa21_ethercat" + +config ADAPTER_ETHERCAT_HFA21_ROLE + bool "support ethercat role configure" + default y + choice + prompt "EtherCAT adapter select net role type " + default AS_ETHERCAT_SLAVE_ROLE + + config AS_ETHERCAT_MASTER_ROLE + bool "config as a master" + + config AS_ETHERCAT_SLAVE_ROLE + bool "config as a slave" + endchoice + + +config ADAPTER_ETHERCAT_HFA21_NETMASK + string "Current EtherCAT adapter netmask" + default "255.255.255.0" + + +config ADAPTER_ETHERCAT_HFA21_GATEWAY + string "Current EtherCAT adapter gateway" + default "10.10.100.254" + +config ADAPTER_ETHERCAT_HFA21_IP_SELF + string "Current EtherCAT adapter IP" + default "10.10.100.254" + +config ADAPTER_ETHERCAT_ADDRESS_SELF + string "Current EtherCAT address" + default 0x12345678 + +config ADAPTER_ETHERCAT_HFA21_IP_FROM + string "Receive Packet from IP" + default "10.10.100.50" + +config ADAPTER_ETHERCAT_HFA21_IP_TO + string "Send Packet to IP" + default "10.10.100.50" diff --git a/APP_Framework/Framework/connection/industrial_ethernet/ethercat/hfa21_ethercat/Makefile b/APP_Framework/Framework/connection/industrial_ethernet/ethercat/hfa21_ethercat/Makefile new file mode 100644 index 0000000..b9178f0 --- /dev/null +++ b/APP_Framework/Framework/connection/industrial_ethernet/ethercat/hfa21_ethercat/Makefile @@ -0,0 +1,3 @@ +SRC_FILES := hfa21_ethercat.c + +include $(KERNEL_ROOT)/compiler.mk diff --git a/APP_Framework/Framework/connection/industrial_ethernet/ethercat/hfa21_ethercat/hfa21_ethercat.c b/APP_Framework/Framework/connection/industrial_ethernet/ethercat/hfa21_ethercat/hfa21_ethercat.c new file mode 100644 index 0000000..4e6cf11 --- /dev/null +++ b/APP_Framework/Framework/connection/industrial_ethernet/ethercat/hfa21_ethercat/hfa21_ethercat.c @@ -0,0 +1,485 @@ +/* + * Copyright (c) 2020 AIIT XUOS Lab + * XiUOS is licensed under Mulan PSL v2. + * You can use this software according to the terms and conditions of the Mulan PSL v2. + * You may obtain a copy of Mulan PSL v2 at: + * http://license.coscl.org.cn/MulanPSL2 + * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, + * EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, + * MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. + * See the Mulan PSL v2 for more details. + */ + +/** + * @file hfa21_ethercat.c + * @brief Implement the connection ethercat adapter function, using HFA21 device + * @version 1.1 + * @author AIIT XUOS Lab + * @date 2021.10.15 + */ + +#include +#include +#include + +// With HFA21, we use transparant transmission mode, +// therefore, only the TCP/UDP datagrams are considered, +// here EtherCAT is in fact an application layer protocol. + +// #define ADAPTER_ETHERNET_NAME "ethernet" //"wifi" +EcatFrame ecat_data; +static struct Adapter *ethernet; +uint32_t self_address; + +/** + * @description: Open HFA21 ethernet uart function for ethercat + * @param adapter - ethercat device pointer + * @return success: 0, failure: -1 + */ +static int Hfa21EthercatOpen(struct Adapter *adapter) +{ + ethernet = AdapterDeviceFindByName(ADAPTER_ETHERNET_NAME); + AdapterDeviceOpen(ethernet); + ADAPTER_DEBUG("Hfa21Ethercat open done\n"); + + return 0; +} + +/** + * @description: disconnnect ethercat from internet + * @param adapter - ethercat device pointer + * @return success: 0 + */ +static int Hfa21EthercatSetDown(struct Adapter *adapter) +{ + if (ethernet) + { + AdapterDeviceClose(ethernet); + ethernet = NULL; + } + return 0; +} + +/** + * @description: Close HFA21 ethercat and uart function + * @param adapter - ethercat device pointer + * @return success: 0 + */ +static int Hfa21EthercatClose(struct Adapter *adapter) +{ + return Hfa21EthercatSetDown(adapter); +} + +static int Hfa21EthercatBuildAndSend(struct Adapter *adapter) +{ + int result = 0; + // fill the frame according to the ecat_data + uint16_t frame_len = sizeof(EcatHeader); + EcatDatagramPtr cur_data = ecat_data.datagram; + while (cur_data) + { + frame_len += sizeof(EcatDataHeader); + frame_len += cur_data->header.length; + frame_len += sizeof(cur_data->work_counter); + cur_data = (EcatDatagramPtr)cur_data->next; + } + if (frame_len > MAX_FRAME_LEN) + { + ADAPTER_DEBUG("frame_len is too long\n"); + result = -2; + goto __exit; + } + if (frame_len < MIN_FRAME_LEN) + { + ADAPTER_DEBUG("frame_len is too short\n"); + result = -2; + goto __exit; + } + uint8_t *frame = PrivMalloc(sizeof(uint8_t) * frame_len); + if (frame == NULL) + { + ADAPTER_DEBUG("Hfa21EthercatBuildAndSend: malloc failed\n"); + result = -1; + goto __exit; + } + + size_t idx = 0; + WRITE16(frame, idx, ecat_data.header.header); + cur_data = ecat_data.datagram; + while (cur_data) + { + WRITE8(frame, idx, cur_data->header.cmd); + WRITE8(frame, idx, cur_data->header.idx); + WRITE32(frame, idx, cur_data->header.address.logical); + WRITE16(frame, idx, cur_data->header.suffix); + WRITE16(frame, idx, cur_data->header.irq); + memcpy(frame + idx, cur_data->data, cur_data->header.length); + idx += cur_data->header.length; + WRITE16(frame, idx, cur_data->work_counter); + cur_data = (EcatDatagramPtr)cur_data->next; + } + // send the frame + if (ethernet && ethernet->agent) + { + result = EntmSend(ethernet->agent, (const char *)frame, frame_len); + if (result == 0) + { + result = frame_len; + } + } + else + { + printf("Hfa21Ethercat Send can not find agent!\n"); + result = -1; + goto __exit; + } + +__exit: + return result; +} + +/** + * @description: send data to adapter + * @param adapter - ethercat device pointer + * @param data - data buffer, when it is NULL, it means to build frame according to `ecat_data`, + * otherwise, it means to replace datagram in `ecat_data` and make up a frame. Slave can use + * this function to update its data. Master have to construct frame according to `ecat_data` and + * pass NULL data to this function. + * @param data - data length + * @return success: sent frame len + */ +static int Hfa21EthercatSend(struct Adapter *adapter, const void *data, size_t len) +{ + if (data == NULL || len == 0) + { + return Hfa21EthercatBuildAndSend(adapter); + } + EcatDatagramPtr cur_data = ecat_data.datagram; + size_t cur_len = 0; + while (cur_data) + { + if (cur_data->self) + { + PrivFree(cur_data->data); + cur_data->data = PrivMalloc(sizeof(uint8_t) * len); + memcpy(cur_data->data, data, len); + cur_data->header.length = len; + break; + } + cur_data = (EcatDatagramPtr)cur_data->next; + } + + return Hfa21EthercatBuildAndSend(adapter); +} + +/** + * @description: receive data from adapter + * @param adapter - ethercat device pointer + * @param data_buffer - data buffer, the whole received frame + * @param buffer_len - whole frame length, set it to maximum 1500 if you don't know the length + * @return success: data length, the data can be visited via variable `ecat_data` + */ +static int Hfa21EthercatReceive(struct Adapter *adapter, void *data_buffer, size_t buffer_len) +{ + // in fact, the length of data must be less than buffer_len + int result = 0; + if (ethernet && ethernet->agent) + { + // + result = EntmRecv(ethernet->agent, data_buffer, buffer_len, 40000); + } + else + { + printf("Hfa21Ethercat::Receive can not find agent!\n"); + result = -1; + goto __exit; + } + // parse header + size_t data_len = 0; + size_t idx = 0; + ecat_data.header.header = READ16(data_buffer, idx); + buffer_len -= ECAT_HEADER_LENGTH; + if (ecat_data.header.length > buffer_len) + { + printf("buffer size is less than the frame length!\n"); + result = -2; + } + if (ecat_data.header.length <= ECAT_DATA_HEADER_LENGTH) + { + // the first datagram header is too short + printf("Datagram is empty!\n"); + result = -3; + goto __exit; + } + + // parse datagrams + ecat_data.datagram = (EcatDatagramPtr)PrivMalloc(sizeof(EcatDatagram)); + EcatDatagramPtr cur_data = ecat_data.datagram; + do + { + // parse datagram header + cur_data->header.cmd = READ8(data_buffer, idx); + cur_data->header.idx = READ8(data_buffer, idx); + cur_data->header.address.logical = READ32(data_buffer, idx); + if (cur_data->header.address.logical == self_address) + { + cur_data->self = 1; // this datagram is mine + } + else + { + cur_data->self = 0; + } + cur_data->header.suffix = READ16(data_buffer, idx); + cur_data->header.irq = READ16(data_buffer, idx); + if (idx + cur_data->header.length + sizeof(cur_data->work_counter) > buffer_len) + { + printf("buffer size is less than the frame length!\n"); + result = -2; + goto __exit; + } + // parse datagram data + if (cur_data->data) + { + PrivFree(cur_data->data); + } + cur_data->data = PrivMalloc(sizeof(char) * cur_data->header.length); + memcpy(cur_data->data, data_buffer + idx, cur_data->header.length); + idx += cur_data->header.length; + memcpy(data_buffer + data_len, cur_data->data, cur_data->header.length); + data_len += cur_data->header.length; + cur_data->work_counter = READ16(data_buffer, idx); + // check header flag `more` for next datagram, move to next datagram if exists + if (cur_data->header.m == 1 && buffer_len >= idx + ECAT_DATA_HEADER_LENGTH) + { + if (!cur_data->next) + { + cur_data->next = PrivMalloc(sizeof(EcatDatagram)); + } + cur_data = (EcatDatagramPtr)cur_data->next; + } + else + { + cur_data = cur_data->next; + while (cur_data) + { + EcatDatagramPtr temp = (EcatDatagramPtr)cur_data->next; + PrivFree(cur_data->data); + PrivFree(cur_data); + cur_data = temp; + } + break; + } + } while (1); + result = data_len; +__exit: + return result; +} + +/** + * @description: connnect Ethercat to internet + * @param adapter - Ethercat device pointer + * @return success: 0 + */ +static int Hfa21EthercatSetUp(struct Adapter *adapter) +{ + if (ethernet) + { + return AdapterDeviceSetUp(ethernet); + } + return -1; +} + +/** + * @description: set ethercat ip/gateway/netmask address(in sta mode) working at WANN mode + * @param adapter - ethercat device pointer + * @param ip - ip address + * @param gateway - gateway address + * @param netmask - netmask address + * @return success: 0, failure: -ENOMEMORY or -1 + */ +static int Hfa21EthercatSetAddr(struct Adapter *adapter, const char *ip, const char *gateway, const char *netmask) +{ + if (ethernet) + { + return AdapterDeviceSetAddr(ethernet, + ip == NULL ? ADAPTER_ETHERCAT_HFA21_IP_SELF : ip, + gateway == NULL ? ADAPTER_ETHERCAT_HFA21_GATEWAY : gateway, + netmask == NULL ? ADAPTER_ETHERCAT_HFA21_NETMASK : netmask); + } + return -1; +} + +/** + * @description: ethercat ping function + * @param adapter - ethercat device pointer + * @param destination - domain name or ip address + * @return success: 0, failure: -1 + */ +static int Hfa21EthercatPing(struct Adapter *adapter, const char *destination) +{ + if (ethernet) + { + return AdapterDevicePing(ethernet, destination); + } + return -1; +} + +/** + * @description: ethercat connect function + * @param adapter - ethercat device pointer + * @param net_role - net role, CLIENT or SERVER + * @param ip - ip address + * @param port - port num + * @param ip_type - ip type, IPV4 or IPV6 + * @return success: 0, failure: -1 + */ +static int Hfa21EthercatConnect(struct Adapter *adapter, enum NetRoleType net_role, const char *ip, const char *port, enum IpType ip_type) +{ + + if (ethernet) + { + return AdapterDeviceConnect(ethernet, net_role, ip, + port == NULL ? ETHERCAT_PORT : port, ip_type); + } + return -1; +} + +static int Hfa21EthercatIoctl(struct Adapter *adapter, int cmd, void *args) +{ + if (ethernet) + { + return AdapterDeviceControl(ethernet, cmd, args); + } + return -1; +} + +static const struct IpProtocolDone hfa21_ethercat_done = + { + .open = Hfa21EthercatOpen, + .close = Hfa21EthercatClose, + .ioctl = Hfa21EthercatIoctl, + .setup = Hfa21EthercatSetUp, + .setdown = Hfa21EthercatSetDown, + .setaddr = Hfa21EthercatSetAddr, + .setdns = NULL, + .setdhcp = NULL, + .ping = Hfa21EthercatPing, + .netstat = NULL, + .connect = Hfa21EthercatConnect, + .send = Hfa21EthercatSend, + .recv = Hfa21EthercatReceive, + .disconnect = NULL, +}; + +/** + * @description: Register ethercat device hfa21 + * @return success: product_info, failure: NULL + */ +AdapterProductInfoType Hfa21EthercatAttach(struct Adapter *adapter) +{ + struct AdapterProductInfo *product_info = PrivMalloc(sizeof(struct AdapterProductInfo)); + if (!product_info) + { + printf("Hfa21EthercatAttach Attach malloc product_info error\n"); + PrivFree(product_info); + return NULL; + } + strcpy(product_info->model_name, ADAPTER_ETHERCAT_HFA21); + product_info->model_done = (void *)&hfa21_ethercat_done; + printf("str address during init: %s\n", ADAPTER_ETHERCAT_ADDRESS_SELF); + self_address = strtoul(ADAPTER_ETHERCAT_ADDRESS_SELF, NULL, 16); + printf("self address during init: %x\n", self_address); + return product_info; +} + +/** + * @description: Test case for slave ethercat device for hfa21 + * @return success: 0, failure: -1 + */ +int Hfa21EthercatSlaveTest(struct Adapter *adapter) +{ + int baud_rate = BAUD_RATE_57600; + char ethercat_recv_msg[128] = {0}; + int i, len = 0; + AdapterDeviceOpen(adapter); + AdapterDeviceControl(adapter, OPE_INT, &baud_rate); + AdapterDeviceSetUp(adapter); + // AdapterDeviceSetAddr(adapter, NULL, NULL, NULL); + + enum IpType ip_type = IPV4; + + printf("ready to test data transfer\n"); + + // for slave nodes, receive first, change the contents and then send it to next node + len = 1500; + for (i = 0; i < 10; i++) + { + // wait for neighbor node to send data + const char *ip_from = ADAPTER_ETHERCAT_HFA21_IP_FROM; + AdapterDeviceConnect(adapter, SERVER, ip_from, NULL, ip_type); + PrivTaskDelay(200); + AdapterDeviceRecv(adapter, ethercat_recv_msg, 1500); + printf("AdapterEthercatTest recv %s\n", ethercat_recv_msg); + memset(ethercat_recv_msg, 0, 128); + PrivTaskDelay(1000); + // send processed data to next node + const char *ip_to = ADAPTER_ETHERCAT_HFA21_IP_TO; + AdapterDeviceConnect(adapter, CLIENT, ip_to, NULL, ip_type); + PrivTaskDelay(200); + printf("AdapterEthercatTest send\n"); + AdapterDeviceSend(adapter, NULL, len); + PrivTaskDelay(1000); + } +} + +/** + * @description: Test case for master ethercat device for hfa21 + * @return success: 0, failure: -1 + */ +int Hfa21EthercatMasterTest(struct Adapter *adapter) +{ + int baud_rate = BAUD_RATE_57600; + char ethercat_recv_msg[128] = {0}; + int i, len = 0; + AdapterDeviceOpen(adapter); + AdapterDeviceControl(adapter, OPE_INT, &baud_rate); + AdapterDeviceSetUp(adapter); + // AdapterDeviceSetAddr(adapter, NULL, NULL, NULL); + // printf("setup addr\n"); + + enum IpType ip_type = IPV4; + // for master, manually build ethercat frame + EcatClear(&ecat_data); + printf("start build first block\n"); + EcatAddress slave1; + slave1.logical = 0x01020304; + char data1[] = "cats"; + EcatAppend(&ecat_data, slave1, data1, sizeof(data1)); + printf("start build second block\n"); + EcatAddress slave2; + slave2.logical = 0x20304050; + char data2[] = "dog"; + EcatAppend(&ecat_data, slave2, data2, sizeof(data2)); + + printf("ready to test data transfer\n"); + + len = 1500; + for (i = 0; i < 10; i++) + { + // send a frame to a slave node + const char *ip_to = ADAPTER_ETHERCAT_HFA21_IP_TO; + AdapterDeviceConnect(adapter, CLIENT, ip_to, NULL, ip_type); + PrivTaskDelay(200); + printf("[AdapterEthercatTest send]\n"); + AdapterDeviceSend(adapter, NULL, len); + PrivTaskDelay(1000); + // wait for slaves' responses + const char *ip_from = ADAPTER_ETHERCAT_HFA21_IP_FROM; + AdapterDeviceConnect(adapter, SERVER, ip_from, NULL, ip_type); + PrivTaskDelay(200); + AdapterDeviceRecv(adapter, ethercat_recv_msg, 1500); + printf("[AdapterEthercatTest recv] %s\n", ethercat_recv_msg); + memset(ethercat_recv_msg, 0, 128); + PrivTaskDelay(1000); + } +} \ No newline at end of file diff --git a/APP_Framework/Framework/connection/industrial_fieldbus/Kconfig b/APP_Framework/Framework/connection/industrial_fieldbus/Kconfig new file mode 100644 index 0000000..e69de29 diff --git a/APP_Framework/Framework/connection/industrial_fieldbus/Makefile b/APP_Framework/Framework/connection/industrial_fieldbus/Makefile new file mode 100644 index 0000000..98aa92b --- /dev/null +++ b/APP_Framework/Framework/connection/industrial_fieldbus/Makefile @@ -0,0 +1,2 @@ + +include $(KERNEL_ROOT)/compiler.mk diff --git a/APP_Framework/Framework/connection/industrial_wlan/Kconfig b/APP_Framework/Framework/connection/industrial_wlan/Kconfig new file mode 100644 index 0000000..e69de29 diff --git a/APP_Framework/Framework/connection/industrial_wlan/Makefile b/APP_Framework/Framework/connection/industrial_wlan/Makefile new file mode 100644 index 0000000..98aa92b --- /dev/null +++ b/APP_Framework/Framework/connection/industrial_wlan/Makefile @@ -0,0 +1,2 @@ + +include $(KERNEL_ROOT)/compiler.mk diff --git a/APP_Framework/Framework/connection/lora/Kconfig b/APP_Framework/Framework/connection/lora/Kconfig new file mode 100644 index 0000000..7dd6b6c --- /dev/null +++ b/APP_Framework/Framework/connection/lora/Kconfig @@ -0,0 +1,38 @@ +config ADAPTER_SX1278 + bool "Using lora adapter device SX1278" + default n + +config ADAPTER_E220 + bool "Using lora adapter device E220-400T22S" + default n + +choice + prompt "Lora device adapter select net role type " + default AS_LORA_CLIENT_ROLE + + config AS_LORA_GATEWAY_ROLE + bool "config as a gateway" + + config AS_LORA_CLIENT_ROLE + bool "config as a client" +endchoice + +if AS_LORA_GATEWAY_ROLE + config ADAPTER_LORA_NET_ROLE_ID + hex "if Lora device config as a gateway, set gateway net id" + default "0xFF" +endif + +if AS_LORA_CLIENT_ROLE + config ADAPTER_LORA_NET_ROLE_ID + hex "if Lora device config as a client, set client net id" + default "0x01" +endif + +if ADAPTER_SX1278 + source "$APP_DIR/Framework/connection/lora/sx1278/Kconfig" +endif + +if ADAPTER_E220 + source "$APP_DIR/Framework/connection/lora/e220/Kconfig" +endif diff --git a/APP_Framework/Framework/connection/lora/Make.defs b/APP_Framework/Framework/connection/lora/Make.defs new file mode 100644 index 0000000..59f79c8 --- /dev/null +++ b/APP_Framework/Framework/connection/lora/Make.defs @@ -0,0 +1,7 @@ +############################################################################ +# APP_Framework/Framework/connection/lora/Make.defs +############################################################################ +ifneq ($(CONFIG_ADAPTER_SX1278),) +CONFIGURED_APPS += $(APPDIR)/../../../APP_Framework/Framework/connection/lora +endif +include $(wildcard $(APPDIR)/../../../APP_Framework/Framework/connection/lora/*/Make.defs) diff --git a/APP_Framework/Framework/connection/lora/Makefile b/APP_Framework/Framework/connection/lora/Makefile new file mode 100644 index 0000000..e1b0552 --- /dev/null +++ b/APP_Framework/Framework/connection/lora/Makefile @@ -0,0 +1,21 @@ +include $(KERNEL_ROOT)/.config +ifeq ($(CONFIG_ADD_NUTTX_FETURES),y) + include $(APPDIR)/Make.defs + CSRCS += adapter_lora.c + include $(APPDIR)/Application.mk + +endif + +ifeq ($(CONFIG_ADD_XIZI_FETURES),y) + SRC_FILES := adapter_lora.c + + ifeq ($(CONFIG_ADAPTER_SX1278),y) + SRC_DIR += sx1278 + endif + + ifeq ($(CONFIG_ADAPTER_E220),y) + SRC_DIR += e220 + endif + include $(KERNEL_ROOT)/compiler.mk + +endif diff --git a/APP_Framework/Framework/connection/lora/adapter_lora.c b/APP_Framework/Framework/connection/lora/adapter_lora.c new file mode 100644 index 0000000..397e89e --- /dev/null +++ b/APP_Framework/Framework/connection/lora/adapter_lora.c @@ -0,0 +1,863 @@ +/* +* Copyright (c) 2020 AIIT XUOS Lab +* XiUOS is licensed under Mulan PSL v2. +* You can use this software according to the terms and conditions of the Mulan PSL v2. +* You may obtain a copy of Mulan PSL v2 at: +* http://license.coscl.org.cn/MulanPSL2 +* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, +* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, +* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. +* See the Mulan PSL v2 for more details. +*/ + +/** + * @file adapter_lora.c + * @brief Implement the connection lora adapter function + * @version 1.1 + * @author AIIT XUOS Lab + * @date 2021.10.20 + */ + +#include + +#ifdef ADAPTER_SX1278 +extern AdapterProductInfoType Sx1278Attach(struct Adapter *adapter); +#endif + +#ifdef ADAPTER_E220 +extern AdapterProductInfoType E220Attach(struct Adapter *adapter); +#endif + +#define ADAPTER_LORA_CLIENT_NUM 255 +#define ADAPTER_LORA_DATA_LENGTH 256 +#define ADAPTER_LORA_RECV_DATA_LENGTH ADAPTER_LORA_DATA_LENGTH + 16 + +#define ADAPTER_LORA_DATA_HEAD 0x3C +#define ADAPTER_LORA_NET_PANID 0x0102 +#define ADAPTER_LORA_DATA_TYPE_JOIN 0x0A +#define ADAPTER_LORA_DATA_TYPE_QUIT 0x0B +#define ADAPTER_LORA_DATA_TYPE_JOIN_REPLY 0x0C +#define ADAPTER_LORA_DATA_TYPE_QUIT_REPLY 0x0D +#define ADAPTER_LORA_DATA_TYPE_USERDATA 0x0E +#define ADAPTER_LORA_DATA_TYPE_CMD 0x0F + +//need to change status if the lora client wants to quit the net when timeout or a certain event +//eg.can also use sem to trigger quit function +static int g_adapter_lora_quit_flag = 0; + +enum ClientState +{ + CLIENT_DISCONNECT = 0, + CLIENT_CONNECT, + CLIENT_DEFAULT, +}; + +enum DataType +{ + LORA_CLIENT_ACCESS = 0, + LORA_GATEWAY_REPLY, + LORA_USER_DATA, +}; + +enum LoraGatewayState { + LORA_STATE_IDLE = 0, + LORA_JOIN_NET, + LORA_QUIT_NET, + LORA_RECV_DATA, +}; + +static uint8 LoraGatewayState = LORA_STATE_IDLE; + +struct LoraGatewayParam +{ + uint8 gateway_id; + uint16 panid; + uint8 client_id[ADAPTER_LORA_CLIENT_NUM]; + int client_num; + int receive_data_sem; +}; + +struct LoraClientParam +{ + uint8 client_id; + uint16 panid; + enum ClientState client_state; + + uint8 gateway_id; +}; + +/*LoraDataFormat: +**flame_head : 0x3C +**length : sizeof(struct LoraDataFormat) +**panid : 0x0102 +**client_id : 0x01、0x02、0x03... +**gateway_id : 0x11、0x12、0x13... +**data_type : 0x0A(join net, client->gateway)、0x0B(join net reply, gateway->client)、 + 0x0C(user data, client->gateway)、0x0D(user data cmd, gateway->client) +**data : user data +**crc16 : CRC 16 check data +*/ +struct LoraDataFormat +{ + uint8 flame_head; + uint8 reserved[3]; + uint32 length; + uint16 panid; + uint8 client_id; + uint8 gateway_id; + + uint16 data_type; + uint8 data[ADAPTER_LORA_DATA_LENGTH]; + + uint16 crc16; +}; + +/*******************LORA MESH FUNCTION***********************/ + +/** + * @description: create CRC16 data + * @param data input data buffer + * @param length input data buffer minus check code + */ +static uint16 LoraCrc16(uint8 *data, uint16 length) +{ + int j; + uint16 crc_data = 0xFFFF; + + while (length--) { + crc_data ^= *data++; + for( j = 0 ; j < 8 ; j ++) { + if(crc_data & 0x01) /* LSB(b0)=1 */ + crc_data = crc_data >> 1 ^ 0xA001; + else + crc_data = crc_data >> 1; + } + } + + return crc_data; +} + +/** + * @description: CRC16 check + * @param data input data buffer + * @param length input data buffer minus check code + */ +static int LoraCrc16Check(uint8 *data, uint16 length) +{ + uint16 crc_data; + uint16 input_data = (((uint16)data[length - 1] << 8) & 0xFF00) | ((uint16)data[length - 2] & 0x00FF); + + crc_data = LoraCrc16(data, length - 2); + + if (crc_data == input_data) + return 0; + else + return -1; +} + +/** + * @description: Lora receive data check + * @param data receive data buffer + * @param length receive data length + * @param recv_data LoraDataFormat data + */ +static int LoraReceiveDataCheck(uint8 *data, uint16 length, struct LoraDataFormat *recv_data) +{ + int i; + uint32 recv_data_length = 0; + for ( i = 0; i < length; i ++) { + if (ADAPTER_LORA_DATA_HEAD == data[i]) { + recv_data_length = (data[i + 4] & 0xFF) | ((data[i + 5] & 0xFF) << 8) | ((data[i + 6] & 0xFF) << 16) | ((data[i + 7] & 0xFF) << 24); + if (sizeof(struct LoraDataFormat) == recv_data_length) { + memcpy(recv_data, (uint8 *)(data + i), sizeof(struct LoraDataFormat)); + return 0; + } + } + } + + return -1; +} + +/** + * @description: Lora Gateway reply connect request to Client + * @param adapter Lora adapter pointer + * @param gateway_recv_data Lora Client connect data + */ +static int LoraGatewayReply(struct Adapter *adapter, struct LoraDataFormat *gateway_recv_data) +{ + int i; + int client_join_flag = 0; + struct LoraGatewayParam *gateway = (struct LoraGatewayParam *)adapter->adapter_param; + struct LoraDataFormat gateway_reply_data; + + memset(&gateway_reply_data, 0, sizeof(struct LoraDataFormat)); + + if (ADAPTER_LORA_DATA_TYPE_JOIN == gateway_recv_data->data_type) { + + for (i = 0; i < gateway->client_num; i ++) { + if (gateway_recv_data->client_id == gateway->client_id[i]) { + printf("Lora client_%d 0x%x has already join net 0x%x\n", i, gateway_recv_data->client_id, gateway->gateway_id); + client_join_flag = 1; + break; + } + } + + if (!client_join_flag) { + if (gateway->client_num > 6) { + printf("Lora gateway only support 6(max) client\n"); + gateway->client_num = 0; + } + gateway->client_id[gateway->client_num] = gateway_recv_data->client_id; + gateway->client_num ++; + } + + gateway_reply_data.flame_head = ADAPTER_LORA_DATA_HEAD; + gateway_reply_data.length = sizeof(struct LoraDataFormat); + gateway_reply_data.panid = gateway->panid; + gateway_reply_data.data_type = ADAPTER_LORA_DATA_TYPE_JOIN_REPLY; + gateway_reply_data.client_id = gateway_recv_data->client_id; + gateway_reply_data.gateway_id = gateway->gateway_id; + gateway_reply_data.crc16 = LoraCrc16((uint8 *)&gateway_reply_data, sizeof(struct LoraDataFormat) - 2); + + if (AdapterDeviceSend(adapter, (uint8 *)&gateway_reply_data, gateway_reply_data.length) < 0) { + return -1; + } + + printf("Lora gateway 0x%x accept client 0x%x \n", gateway->gateway_id, gateway_recv_data->client_id); + } else if (ADAPTER_LORA_DATA_TYPE_QUIT == gateway_recv_data->data_type) { + for (i = 0; i < gateway->client_num; i ++) { + if (gateway->client_id[i] == gateway_recv_data->client_id) { + gateway->client_id[i] = 0; + gateway->client_num --; + break; + } + } + + gateway_reply_data.flame_head = ADAPTER_LORA_DATA_HEAD; + gateway_reply_data.length = sizeof(struct LoraDataFormat); + gateway_reply_data.panid = gateway->panid; + gateway_reply_data.data_type = ADAPTER_LORA_DATA_TYPE_QUIT_REPLY; + gateway_reply_data.client_id = gateway_recv_data->client_id; + gateway_reply_data.gateway_id = gateway->gateway_id; + gateway_reply_data.crc16 = LoraCrc16((uint8 *)&gateway_reply_data, sizeof(struct LoraDataFormat) - 2); + + if (AdapterDeviceSend(adapter, (uint8 *)&gateway_reply_data, gateway_reply_data.length) < 0) { + return -1; + } + + printf("Lora gateway 0x%x accept client 0x%x \n", gateway->gateway_id, gateway_recv_data->client_id); + } + + return 0; +} + +/** + * @description: Lora Gateway send cmd to Client + * @param adapter Lora adapter pointer + * @param client_id Lora Client id + * @param cmd Lora cmd + */ +static int LoraGatewaySendCmd(struct Adapter *adapter, unsigned char client_id, int cmd) +{ + struct LoraGatewayParam *gateway = (struct LoraGatewayParam *)adapter->adapter_param; + struct LoraDataFormat gateway_cmd_data; + + memset(&gateway_cmd_data, 0, sizeof(struct LoraDataFormat)); + + gateway_cmd_data.flame_head = ADAPTER_LORA_DATA_HEAD; + gateway_cmd_data.length = sizeof(struct LoraDataFormat); + gateway_cmd_data.panid = gateway->panid; + gateway_cmd_data.data_type = cmd; + gateway_cmd_data.client_id = client_id; + gateway_cmd_data.gateway_id = gateway->gateway_id; + gateway_cmd_data.crc16 = LoraCrc16((uint8 *)&gateway_cmd_data, sizeof(struct LoraDataFormat) - 2); + + if (AdapterDeviceSend(adapter, (uint8 *)&gateway_cmd_data, gateway_cmd_data.length) < 0) { + return -1; + } + + return 0; +} + +/** + * @description: Lora Gateway handle the user data from the client + * @param adapter Lora adapter pointer + * @param gateway_recv_data Lora Client user data + */ +static int LoraGatewayHandleData(struct Adapter *adapter, struct LoraDataFormat *gateway_recv_data) +{ + /*User needs to handle client data depends on the requirement*/ + printf("Lora Gateway receive Client %d data:\n", gateway_recv_data->client_id); + printf("%s\n", gateway_recv_data->data); + return 0; +} + +/** + * @description: Lora Client update status after join the net + * @param adapter Lora adapter pointer + * @param client_recv_data Lora Client recv data from Lora Gateway + */ +static int LoraClientUpdate(struct Adapter *adapter, struct LoraDataFormat *client_recv_data) +{ + struct LoraClientParam *client = (struct LoraClientParam *)adapter->adapter_param; + + if (ADAPTER_LORA_DATA_TYPE_JOIN_REPLY == client_recv_data->data_type) { + client->gateway_id = client_recv_data->gateway_id; + client->panid = client_recv_data->panid; + client->client_state = CLIENT_CONNECT; + printf("LoraClientUpdate client join panid 0x%x successfully\n", client->panid); + } else if (ADAPTER_LORA_DATA_TYPE_QUIT_REPLY == client_recv_data->data_type) { + client->gateway_id = 0; + client->panid = 0; + client->client_state = CLIENT_DISCONNECT; + printf("LoraClientUpdate client quit panid 0x%x successfully\n", client->panid); + } + + return 0; +} + +/** + * @description: Lora Client send the user data to the gateway + * @param adapter Lora adapter pointer + * @param send_buf Lora Client send user data buf + * @param length user data length (max size is ADAPTER_LORA_DATA_LENGTH) + */ +static int LoraClientSendData(struct Adapter *adapter, void *send_buf, int length) +{ + struct LoraClientParam *client = (struct LoraClientParam *)adapter->adapter_param; + + if (client->client_state != CLIENT_CONNECT) { + printf("Lora client %d do not connect to Lora gateway\n", client->client_id); + return 0; + } + + if (length > ADAPTER_LORA_DATA_LENGTH) { + printf("Lora client %d send data %d larger than max %d \n", client->client_id, length, ADAPTER_LORA_DATA_LENGTH); + return 0; + } + + struct LoraDataFormat client_user_data; + + memset(&client_user_data, 0, sizeof(struct LoraDataFormat)); + + client_user_data.flame_head = ADAPTER_LORA_DATA_HEAD; + client_user_data.length = sizeof(struct LoraDataFormat); + client_user_data.panid = client->panid; + client_user_data.data_type = ADAPTER_LORA_DATA_TYPE_USERDATA; + client_user_data.client_id = client->client_id; + client_user_data.gateway_id = client->gateway_id; + + memcpy(client_user_data.data, (uint8 *)send_buf, length); + + client_user_data.crc16 = LoraCrc16((uint8 *)&client_user_data, sizeof(struct LoraDataFormat) - 2); + + if (AdapterDeviceSend(adapter, (uint8 *)&client_user_data, client_user_data.length) < 0) { + return -1; + } + + return 0; +} + +/** + * @description: Lora Gateway receive data analyzing + * @param adapter Lora adapter pointer + * @param gateway_recv_data Lora gateway receive data pointer + */ +static int LoraGateWayDataAnalyze(struct Adapter *adapter, struct LoraDataFormat *gateway_recv_data) +{ + int ret = 0; + printf("%s:gateway_recv_data\n",__func__); + printf("head 0x%x length %d panid 0x%x data_type 0x%x client_id 0x%x gateway_id 0x%x crc 0x%x\n", + gateway_recv_data->flame_head, gateway_recv_data->length, gateway_recv_data->panid, gateway_recv_data->data_type, + gateway_recv_data->client_id, gateway_recv_data->gateway_id, gateway_recv_data->crc16); + + if (LoraCrc16Check((uint8 *)gateway_recv_data, sizeof(struct LoraDataFormat)) < 0) { + printf("LoraGateWayDataAnalyze CRC check error\n"); + return -1; + } + + if ((ADAPTER_LORA_DATA_HEAD == gateway_recv_data->flame_head) && + (ADAPTER_LORA_NET_PANID == gateway_recv_data->panid)) { + switch (gateway_recv_data->data_type) + { + case ADAPTER_LORA_DATA_TYPE_JOIN : + case ADAPTER_LORA_DATA_TYPE_QUIT : + ret = LoraGatewayReply(adapter, gateway_recv_data); + break; + case ADAPTER_LORA_DATA_TYPE_USERDATA : + ret = LoraGatewayHandleData(adapter, gateway_recv_data); + break; + default: + break; + } + } + + return ret; +} + +/** + * @description: Lora Client receive data analyzing + * @param adapter Lora adapter pointer + * @param send_buf Lora Client send user data buf + * @param length user data length (max size is ADAPTER_LORA_DATA_LENGTH) + */ +static int LoraClientDataAnalyze(struct Adapter *adapter, void *send_buf, int length) +{ + int ret = 0; + uint8 lora_recv_data[ADAPTER_LORA_RECV_DATA_LENGTH] = {0}; + + struct LoraDataFormat *client_recv_data = PrivMalloc(sizeof(struct LoraDataFormat)); + + memset(client_recv_data, 0, sizeof(struct LoraDataFormat)); + + ret = AdapterDeviceRecv(adapter, lora_recv_data, ADAPTER_LORA_RECV_DATA_LENGTH); + if (ret <= 0) { + printf("LoraClientDataAnalyze recv error.Just return\n"); + PrivFree(client_recv_data); + return -1; + } + + LoraReceiveDataCheck(lora_recv_data, ADAPTER_LORA_RECV_DATA_LENGTH, client_recv_data); + + printf("%s:client_recv_data\n", __func__); + printf("head 0x%x length %d panid 0x%x data_type 0x%x client_id 0x%x gateway_id 0x%x crc 0x%x\n", + client_recv_data->flame_head, client_recv_data->length, client_recv_data->panid, client_recv_data->data_type, + client_recv_data->client_id, client_recv_data->gateway_id, client_recv_data->crc16); + + if ((ADAPTER_LORA_DATA_HEAD == client_recv_data->flame_head) && + (ADAPTER_LORA_NET_PANID == client_recv_data->panid)) { + if (LoraCrc16Check((uint8 *)client_recv_data, sizeof(struct LoraDataFormat)) < 0) { + printf("LoraClientDataAnalyze CRC check error\n"); + PrivFree(client_recv_data); + return -1; + } + + //only handle this client_id information from gateway + if (client_recv_data->client_id == adapter->net_role_id) { + switch (client_recv_data->data_type) + { + case ADAPTER_LORA_DATA_TYPE_JOIN_REPLY : + case ADAPTER_LORA_DATA_TYPE_QUIT_REPLY : + ret = LoraClientUpdate(adapter, client_recv_data); + break; + case ADAPTER_LORA_DATA_TYPE_CMD : + if (send_buf) { + ret = LoraClientSendData(adapter, send_buf, length); + } + break; + default: + break; + } + } + } + + PrivFree(client_recv_data); + return ret; +} + +/** + * @description: Lora Client join net function + * @param adapter Lora adapter pointer + * @param panid Lora net panid + */ +static int LoraClientJoinNet(struct Adapter *adapter, unsigned short panid) +{ + struct LoraDataFormat client_join_data; + struct AdapterData priv_lora_net; + + memset(&client_join_data, 0, sizeof(struct LoraDataFormat)); + + client_join_data.flame_head = ADAPTER_LORA_DATA_HEAD; + client_join_data.length = sizeof(struct LoraDataFormat); + client_join_data.panid = panid; + client_join_data.data_type = ADAPTER_LORA_DATA_TYPE_JOIN; + client_join_data.client_id = adapter->net_role_id; + client_join_data.crc16 = LoraCrc16((uint8 *)&client_join_data, sizeof(struct LoraDataFormat) - 2); + + printf("%s:client_join_data\n", __func__); + printf("head 0x%x length %d panid 0x%x data_type 0x%x client_id 0x%x gateway_id 0x%x crc 0x%x\n", + client_join_data.flame_head, client_join_data.length, client_join_data.panid, client_join_data.data_type, + client_join_data.client_id, client_join_data.gateway_id, client_join_data.crc16); + + priv_lora_net.len = sizeof(struct LoraDataFormat); + priv_lora_net.buffer = (uint8 *)&client_join_data; + + if (AdapterDeviceJoin(adapter, (uint8 *)&priv_lora_net) < 0) { + return -1; + } + + return 0; +} + +/** + * @description: Lora Client quit net function + * @param adapter Lora adapter pointer + * @param panid Lora net panid + */ +static int LoraClientQuitNet(struct Adapter *adapter, unsigned short panid) +{ + struct LoraDataFormat client_quit_data; + struct AdapterData priv_lora_net; + + memset(&client_quit_data, 0, sizeof(struct LoraDataFormat)); + + client_quit_data.flame_head = ADAPTER_LORA_DATA_HEAD; + client_quit_data.length = sizeof(struct LoraDataFormat); + client_quit_data.panid = panid; + client_quit_data.data_type = ADAPTER_LORA_DATA_TYPE_QUIT; + client_quit_data.client_id = adapter->net_role_id; + client_quit_data.crc16 = LoraCrc16((uint8 *)&client_quit_data, sizeof(struct LoraDataFormat) - 2); + + priv_lora_net.len = sizeof(struct LoraDataFormat); + priv_lora_net.buffer = (uint8 *)&client_quit_data; + + if (AdapterDeviceDisconnect(adapter, (uint8 *)&priv_lora_net) < 0) { + return -1; + } + + return 0; +} + +/** + * @description: Lora Gateway Process function + * @param lora_adapter Lora adapter pointer + * @param gateway Lora gateway pointer + * @param gateway_recv_data Lora gateway receive data pointer + */ +int LoraGatewayProcess(struct Adapter *lora_adapter, struct LoraGatewayParam *gateway, struct LoraDataFormat *gateway_recv_data) +{ + int i, ret = 0; + uint8 lora_recv_data[ADAPTER_LORA_RECV_DATA_LENGTH]; + switch (LoraGatewayState) + { + case LORA_STATE_IDLE: + memset(lora_recv_data, 0, ADAPTER_LORA_RECV_DATA_LENGTH); + + ret = AdapterDeviceRecv(lora_adapter, lora_recv_data, ADAPTER_LORA_RECV_DATA_LENGTH); + if (ret <= 0) { + printf("LoraGatewayProcess IDLE recv error.Just return\n"); + break; + } + + LoraReceiveDataCheck(lora_recv_data, ADAPTER_LORA_RECV_DATA_LENGTH, gateway_recv_data); + + if (ADAPTER_LORA_DATA_TYPE_JOIN == gateway_recv_data->data_type) { + LoraGatewayState = LORA_JOIN_NET; + } else if (ADAPTER_LORA_DATA_TYPE_QUIT == gateway_recv_data->data_type) { + LoraGatewayState = LORA_QUIT_NET; + } else { + LoraGatewayState = LORA_STATE_IDLE; + } + break; + case LORA_JOIN_NET: + case LORA_QUIT_NET: + ret = LoraGateWayDataAnalyze(lora_adapter, gateway_recv_data); + if (ret < 0) { + printf("LoraGateWayDataAnalyze state %d error, re-send data cmd to client\n", LoraGatewayState); + PrivTaskDelay(500); + } + LoraGatewayState = LORA_RECV_DATA; + break; + case LORA_RECV_DATA: + for (i = 0; i < gateway->client_num; i ++) { + if (gateway->client_id[i]) { + printf("LoraGatewayProcess send to client %d for data\n", gateway->client_id[i]); + ret = LoraGatewaySendCmd(lora_adapter, gateway->client_id[i], ADAPTER_LORA_DATA_TYPE_CMD); + if (ret < 0) { + printf("LoraGatewaySendCmd client ID %d error\n", gateway->client_id[i]); + PrivTaskDelay(500); + continue; + } + + memset(lora_recv_data, 0, ADAPTER_LORA_RECV_DATA_LENGTH); + ret = AdapterDeviceRecv(lora_adapter, lora_recv_data, ADAPTER_LORA_RECV_DATA_LENGTH); + if (ret <= 0) { + printf("LoraGatewayProcess recv error.Just return\n"); + continue; + } + + LoraReceiveDataCheck(lora_recv_data, ADAPTER_LORA_RECV_DATA_LENGTH, gateway_recv_data); + + if (ADAPTER_LORA_DATA_TYPE_JOIN == gateway_recv_data->data_type) { + LoraGatewayState = LORA_JOIN_NET; + } else if (ADAPTER_LORA_DATA_TYPE_QUIT == gateway_recv_data->data_type) { + LoraGatewayState = LORA_QUIT_NET; + } else { + ret = LoraGateWayDataAnalyze(lora_adapter, gateway_recv_data); + if (ret < 0) { + printf("LoraGateWayDataAnalyze error, re-send data cmd to client\n"); + PrivTaskDelay(500); + } + } + } + } + break; + default: + break; + } + + return 0; +} + +/** + * @description: Lora Gateway task + * @param parameter - Lora adapter pointer + */ +static void *LoraGatewayTask(void *parameter) +{ + int i; + int ret = 0; + struct Adapter *lora_adapter = (struct Adapter *)parameter; + struct LoraGatewayParam *gateway = (struct LoraGatewayParam *)lora_adapter->adapter_param; + struct LoraDataFormat gateway_recv_data; + + while (1) { + LoraGatewayProcess(lora_adapter, gateway, &gateway_recv_data); + } + + return 0; +} + +/** + * @description: Lora Client data upload task + * @param parameter - Lora adapter pointer + */ +static void *LoraClientDataTask(void *parameter) +{ + int i, ret = 0; + struct Adapter *lora_adapter = (struct Adapter *)parameter; + struct LoraClientParam *client = (struct LoraClientParam *)lora_adapter->adapter_param; + + //set lora_send_buf for test + uint8 lora_send_buf[ADAPTER_LORA_DATA_LENGTH]; + memset(lora_send_buf, 0, ADAPTER_LORA_DATA_LENGTH); + sprintf(lora_send_buf, "Lora client %d adapter test\n", client->client_id); + + while (1) { + + PrivTaskDelay(100); + + if ((CLIENT_DISCONNECT == client->client_state) && (!g_adapter_lora_quit_flag)) { + ret = LoraClientJoinNet(lora_adapter, client->panid); + if (ret < 0) { + printf("LoraClientJoinNet error panid 0x%x\n", client->panid); + } + + ret = LoraClientDataAnalyze(lora_adapter, NULL, 0); + if (ret < 0) { + printf("LoraClientDataAnalyze error, reconnect to gateway\n"); + PrivTaskDelay(500); + continue; + } + } + + if (CLIENT_CONNECT == client->client_state) { + ret = LoraClientDataAnalyze(lora_adapter, (void *)lora_send_buf, strlen(lora_send_buf)); + if (ret < 0) { + printf("LoraClientDataAnalyze error, wait for next data cmd\n"); + PrivTaskDelay(500); + continue; + } + } + } + + return 0; +} + +/** + * @description: Lora Client quit task + * @param parameter - Lora adapter pointer + */ +static void *LoraClientQuitTask(void *parameter) +{ + int ret = 0; + struct Adapter *lora_adapter = (struct Adapter *)parameter; + struct LoraClientParam *client = (struct LoraClientParam *)lora_adapter->adapter_param; + + while (1) { + PrivTaskDelay(100); + + if ((CLIENT_CONNECT == client->client_state) && (g_adapter_lora_quit_flag)) { + ret = LoraClientQuitNet(lora_adapter, client->panid); + if (ret < 0) { + printf("LoraClientQuitNet error panid 0x%x, re-quit net\n", client->panid); + continue; + } + + ret = LoraClientDataAnalyze(lora_adapter, NULL, 0); + if (ret < 0) { + printf("LoraClientQuitTask LoraClientDataAnalyze error\n"); + PrivTaskDelay(500); + continue; + } + } + } + + return 0; +} + +/*******************LORA ADAPTER FUNCTION********************/ + +static int AdapterLoraRegister(struct Adapter *adapter) +{ + int ret = 0; + struct LoraGatewayParam *lora_gateway; + struct LoraClientParam *lora_client; + + strncpy(adapter->name, ADAPTER_LORA_NAME, NAME_NUM_MAX); + + adapter->net_protocol = PRIVATE_PROTOCOL; + +#ifdef AS_LORA_GATEWAY_ROLE + lora_gateway = PrivMalloc(sizeof(struct LoraGatewayParam)); + if (!lora_gateway) { + PrivFree(lora_gateway); + return -1; + } + + memset(lora_gateway, 0, sizeof(struct LoraGatewayParam)); + + lora_gateway->gateway_id = ADAPTER_LORA_NET_ROLE_ID; + lora_gateway->panid = ADAPTER_LORA_NET_PANID; + + adapter->net_role = GATEWAY; + adapter->adapter_param = (void *)lora_gateway; +#else //AS_LORA_CLIENT_ROLE + lora_client = PrivMalloc(sizeof(struct LoraClientParam)); + if (!lora_client) { + PrivFree(lora_client); + return -1; + } + + memset(lora_client, 0, sizeof(struct LoraClientParam)); + + lora_client->client_id = ADAPTER_LORA_NET_ROLE_ID; + lora_client->client_state = CLIENT_DISCONNECT; + lora_client->panid = ADAPTER_LORA_NET_PANID; + + adapter->net_role = CLIENT; + adapter->adapter_param = (void *)lora_client; +#endif + + adapter->net_role_id = ADAPTER_LORA_NET_ROLE_ID; + + adapter->adapter_status = UNREGISTERED; + + ret = AdapterDeviceRegister(adapter); + if (ret < 0) { + printf("Adapter4G register error\n"); + if (lora_gateway) + PrivFree(lora_gateway); + if (lora_client) + PrivFree(lora_client); + + return -1; + } + + return ret; +} + +int AdapterLoraInit(void) +{ + int ret = 0; + + struct Adapter *adapter = PrivMalloc(sizeof(struct Adapter)); + if (!adapter) { + PrivFree(adapter); + return -1; + } + + memset(adapter, 0, sizeof(struct Adapter)); + + ret = AdapterLoraRegister(adapter); + if (ret < 0) { + printf("AdapterLoraInit register lora adapter error\n"); + PrivFree(adapter); + return -1; + } + +#ifdef ADAPTER_SX1278 + AdapterProductInfoType product_info = Sx1278Attach(adapter); + if (!product_info) { + printf("AdapterLoraInit sx1278 attach error\n"); + PrivFree(adapter); + return -1; + } + + adapter->product_info_flag = 1; + adapter->info = product_info; + adapter->done = product_info->model_done; + +#endif + +#ifdef ADAPTER_E220 + AdapterProductInfoType product_info = E220Attach(adapter); + if (!product_info) { + printf("AdapterLoraInit e220 attach error\n"); + PrivFree(adapter); + return -1; + } + + adapter->product_info_flag = 1; + adapter->info = product_info; + adapter->done = product_info->model_done; +#endif + + return ret; +} + +/******************Lora TEST*********************/ +#ifdef AS_LORA_GATEWAY_ROLE +static pthread_t lora_gateway_task; +#else //AS_LORA_CLIENT_ROLE +static pthread_t lora_client_data_task; +static pthread_t lora_client_quit_task; +#endif + +int AdapterLoraTest(void) +{ + struct Adapter *adapter = AdapterDeviceFindByName(ADAPTER_LORA_NAME); + + AdapterDeviceOpen(adapter); + + //create lora gateway task +#ifdef AS_LORA_GATEWAY_ROLE +#ifdef ADD_NUTTX_FETURES + pthread_attr_t lora_gateway_attr = PTHREAD_ATTR_INITIALIZER; + lora_gateway_attr.priority = 20; + lora_gateway_attr.stacksize = 2048; +#else + pthread_attr_t lora_gateway_attr; + lora_gateway_attr.schedparam.sched_priority = 20; + lora_gateway_attr.stacksize = 2048; +#endif + + PrivTaskCreate(&lora_gateway_task, &lora_gateway_attr, &LoraGatewayTask, (void *)adapter); + PrivTaskStartup(&lora_gateway_task); + +#else //AS_LORA_CLIENT_ROLE +#ifdef ADD_NUTTX_FETURES + pthread_attr_t lora_client_attr = PTHREAD_ATTR_INITIALIZER; + lora_client_attr.priority = 20; + lora_client_attr.stacksize = 2048; +#else + pthread_attr_t lora_client_attr; + lora_client_attr.schedparam.sched_priority = 20; + lora_client_attr.stacksize = 2048; +#endif + //create lora client task + PrivTaskCreate(&lora_client_data_task, &lora_client_attr, &LoraClientDataTask, (void *)adapter); + PrivTaskStartup(&lora_client_data_task); + + lora_client_attr.stacksize = 1024; + + PrivTaskCreate(&lora_client_quit_task, &lora_client_attr, &LoraClientQuitTask, (void *)adapter); + PrivTaskStartup(&lora_client_quit_task); +#endif + + return 0; +} +#ifdef ADD_XIZI_FETURES +SHELL_EXPORT_CMD(SHELL_CMD_PERMISSION(0)|SHELL_CMD_TYPE(SHELL_TYPE_CMD_FUNC)|SHELL_CMD_PARAM_NUM(0)|SHELL_CMD_DISABLE_RETURN, AdapterLoraTest, AdapterLoraTest, show adapter lora information); +#endif + diff --git a/APP_Framework/Framework/connection/lora/e220/Kconfig b/APP_Framework/Framework/connection/lora/e220/Kconfig new file mode 100644 index 0000000..050a8ea --- /dev/null +++ b/APP_Framework/Framework/connection/lora/e220/Kconfig @@ -0,0 +1,44 @@ +config ADAPTER_LORA_E220 + string "E220-400T22S adapter name" + default "e220" + +if ADD_XIZI_FETURES + config ADAPTER_E220_M0 + int "E220 M0 pin number" + default "11" + + config ADAPTER_E220_M1 + int "E220 M1 pin number" + default "9" + + config ADAPTER_E220_PIN_DRIVER + string "E220 device pin driver path" + default "/dev/pin_dev" + + config ADAPTER_E220_DRIVER_EXTUART + bool "Using extra uart to support lora" + default y + + config ADAPTER_E220_DRIVER + string "E220 device uart driver path" + default "/dev/uart1_dev1" + depends on !ADAPTER_E220_DRIVER_EXTUART + + if ADAPTER_E220_DRIVER_EXTUART + config ADAPTER_E220_DRIVER + string "E220 device extra uart driver path" + default "/dev/extuart_dev3" + + config ADAPTER_E220_DRIVER_EXT_PORT + int "if E220 device using extuart, choose port" + default "3" + endif +endif + +if ADD_NUTTX_FETURES + +endif + +if ADD_RTTHREAD_FETURES + +endif diff --git a/APP_Framework/Framework/connection/lora/e220/Makefile b/APP_Framework/Framework/connection/lora/e220/Makefile new file mode 100644 index 0000000..7348056 --- /dev/null +++ b/APP_Framework/Framework/connection/lora/e220/Makefile @@ -0,0 +1,3 @@ +SRC_FILES := e220.c + +include $(KERNEL_ROOT)/compiler.mk diff --git a/APP_Framework/Framework/connection/lora/e220/e220.c b/APP_Framework/Framework/connection/lora/e220/e220.c new file mode 100644 index 0000000..3a02881 --- /dev/null +++ b/APP_Framework/Framework/connection/lora/e220/e220.c @@ -0,0 +1,536 @@ +/* +* Copyright (c) 2020 AIIT XUOS Lab +* XiUOS is licensed under Mulan PSL v2. +* You can use this software according to the terms and conditions of the Mulan PSL v2. +* You may obtain a copy of Mulan PSL v2 at: +* http://license.coscl.org.cn/MulanPSL2 +* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, +* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, +* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. +* See the Mulan PSL v2 for more details. +*/ + +/** + * @file e220.c + * @brief Implement the connection E220-400T22S lora adapter function + * @version 2.0 + * @author AIIT XUOS Lab + * @date 2022.4.20 + */ + +#include + +#define E220_GATEWAY_ADDRESS 0xFFFF +#define E220_CHANNEL 0x04 + +#ifdef AS_LORA_GATEWAY_ROLE +#define E220_ADDRESS E220_GATEWAY_ADDRESS +#endif + +#ifdef AS_LORA_CLIENT_ROLE +#define E220_ADDRESS 0xFFFF +#endif + +#define E220_UART_BAUD_RATE 9600 + +enum E220LoraMode +{ + DATA_TRANSFER_MODE = 0, //M1 : M0 = 0 : 0 + WOR_SEND_MODE, //M1 : M0 = 0 : 1 + WOR_RECEIVE_MODE, //M1 : M0 = 1 : 0 + CONFIGURE_MODE_MODE, //M1 : M0 = 1 : 1 +}; + +/** + * @description: Config E220 work mode by set M1/M0 pin + * @param mode Lora working mode + * @return NULL + */ +static void E220LoraModeConfig(enum E220LoraMode mode) +{ + //delay 1s , wait AUX ready + PrivTaskDelay(1000); + + int pin_fd; + pin_fd = PrivOpen(ADAPTER_E220_PIN_DRIVER, O_RDWR); + if (pin_fd < 0) { + printf("open %s error\n", ADAPTER_E220_PIN_DRIVER); + return; + } + + //Step1: config M0 and M1 GPIO + struct PinParam pin_param; + pin_param.cmd = GPIO_CONFIG_MODE; + pin_param.mode = GPIO_CFG_OUTPUT; + pin_param.pin = ADAPTER_E220_M0; + + struct PrivIoctlCfg ioctl_cfg; + ioctl_cfg.ioctl_driver_type = PIN_TYPE; + ioctl_cfg.args = &pin_param; + PrivIoctl(pin_fd, OPE_CFG, &ioctl_cfg); + + pin_param.pin = ADAPTER_E220_M1; + ioctl_cfg.args = &pin_param; + PrivIoctl(pin_fd, OPE_CFG, &ioctl_cfg); + + //Step2 : set M0 and M1 high or low + struct PinStat pin_stat; + + switch (mode) + { + case DATA_TRANSFER_MODE: + pin_stat.pin = ADAPTER_E220_M1; + pin_stat.val = GPIO_LOW; + PrivWrite(pin_fd, &pin_stat, 1); + + pin_stat.pin = ADAPTER_E220_M0; + pin_stat.val = GPIO_LOW; + PrivWrite(pin_fd, &pin_stat, 1); + break; + + case WOR_SEND_MODE: + pin_stat.pin = ADAPTER_E220_M1; + pin_stat.val = GPIO_LOW; + PrivWrite(pin_fd, &pin_stat, 1); + + pin_stat.pin = ADAPTER_E220_M0; + pin_stat.val = GPIO_HIGH; + PrivWrite(pin_fd, &pin_stat, 1); + break; + + case WOR_RECEIVE_MODE: + pin_stat.pin = ADAPTER_E220_M1; + pin_stat.val = GPIO_HIGH; + PrivWrite(pin_fd, &pin_stat, 1); + + pin_stat.pin = ADAPTER_E220_M0; + pin_stat.val = GPIO_LOW; + PrivWrite(pin_fd, &pin_stat, 1); + break; + + case CONFIGURE_MODE_MODE: + pin_stat.pin = ADAPTER_E220_M1; + pin_stat.val = GPIO_HIGH; + PrivWrite(pin_fd, &pin_stat, 1); + + pin_stat.pin = ADAPTER_E220_M0; + pin_stat.val = GPIO_HIGH; + PrivWrite(pin_fd, &pin_stat, 1); + break; + default: + break; + } + + PrivClose(pin_fd); + + //delay 20ms , wait mode switch done + PrivTaskDelay(20); +} + +/** + * @description: Switch baud rate to register bit + * @param baud_rate - baud_rate + * @return baud_rate_bit + */ +static uint8 E220BaudRateSwitch(uint32 baud_rate) +{ + uint8 baud_rate_bit; + + switch (baud_rate) + { + case 1200: + baud_rate_bit = 0x0; + break; + + case 2400: + baud_rate_bit = 0x1; + break; + + case 4800: + baud_rate_bit = 0x2; + break; + + case 9600: + baud_rate_bit = 0x3; + break; + + case 19200: + baud_rate_bit = 0x4; + break; + + case 38400: + baud_rate_bit = 0x5; + break; + + case 57600: + baud_rate_bit = 0x6; + break; + + case 115200: + baud_rate_bit = 0x7; + break; + + default: + break; + } + + return baud_rate_bit; +} + +/** + * @description: Set E220 register, such as address、channel、baud rate... + * @param adapter - lora adapter + * @param address - address + * @param channel - channel + * @param baud_rate - baud_rate + * @return success: 0, failure: -1 + */ +static int E220SetRegisterParam(struct Adapter *adapter, uint16 address, uint8 channel, uint32 baud_rate) +{ + int ret; + uint8 buffer[50] = {0}; + uint8 baud_rate_bit = E220BaudRateSwitch(baud_rate); + + E220LoraModeConfig(CONFIGURE_MODE_MODE); + PrivTaskDelay(30); + + buffer[0] = 0xC0; //write register order + buffer[1] = 0x00; //register start-address + buffer[2] = 0x08; //register length + + buffer[3] = (address >> 8) & 0xFF; //high address + buffer[4] = address & 0xFF; //low adderss + + buffer[5] = ((baud_rate_bit << 5) & 0xE0) | 0x04; + + buffer[6] = 0x00; + buffer[7] = channel; //channel + buffer[8] = 0x03; + buffer[9] = 0; //high-cipher + buffer[10] = 0; //low-cipher + + ret = PrivWrite(adapter->fd, (void *)buffer, 11); + if(ret < 0){ + printf("E220SetRegisterParam send failed %d!\n", ret); + } + + PrivRead(adapter->fd, buffer, 11); + + E220LoraModeConfig(DATA_TRANSFER_MODE); + PrivTaskDelay(1000); + + return 0; +} + +/** + * @description: Get E220 register, such as address、channel、baud rate... + * @param buf - data buf + * @return success: 0, failure: -1 + */ +static int E220GetRegisterParam(uint8 *buf) +{ + int ret; + uint8 buffer[3] = {0}; + + struct Adapter *adapter = AdapterDeviceFindByName(ADAPTER_LORA_NAME); + if (NULL == adapter) { + printf("E220GetRegisterParam find lora adapter error\n"); + return -1; + } + + E220LoraModeConfig(CONFIGURE_MODE_MODE); + PrivTaskDelay(30); + + buffer[0] = 0xC1; //read register order + buffer[1] = 0x00; //register start-address + buffer[2] = 0x08; //register length + + ret = PrivWrite(adapter->fd, (void *)buffer, 3); + if(ret < 0){ + printf("E220GetRegisterParam send failed %d!\n", ret); + } + + PrivRead(adapter->fd, buf, 11); + + E220LoraModeConfig(DATA_TRANSFER_MODE); + PrivTaskDelay(30); + + return 0; +} + +/** + * @description: Open E220 uart function + * @param adapter - Lora device pointer + * @return success: 0, failure: -1 + */ +static int E220Open(struct Adapter *adapter) +{ + /*step1: open e220 uart port*/ + adapter->fd = PrivOpen(ADAPTER_E220_DRIVER, O_RDWR); + if (adapter->fd < 0) { + printf("E220Open get uart %s fd error\n", ADAPTER_E220_DRIVER); + return -1; + } + + struct SerialDataCfg cfg; + memset(&cfg, 0 ,sizeof(struct SerialDataCfg)); + + cfg.serial_baud_rate = BAUD_RATE_9600; + cfg.serial_data_bits = DATA_BITS_8; + cfg.serial_stop_bits = STOP_BITS_1; + cfg.serial_parity_mode = PARITY_NONE; + cfg.serial_bit_order = BIT_ORDER_LSB; + cfg.serial_invert_mode = NRZ_NORMAL; + cfg.serial_buffer_size = SERIAL_RB_BUFSZ; + + /*aiit board use ch438, so it needs more serial configuration*/ +#ifdef ADAPTER_E220_DRIVER_EXTUART + cfg.ext_uart_no = ADAPTER_E220_DRIVER_EXT_PORT; + cfg.port_configure = PORT_CFG_INIT; +#endif + + struct PrivIoctlCfg ioctl_cfg; + ioctl_cfg.ioctl_driver_type = SERIAL_TYPE; + ioctl_cfg.args = &cfg; + + PrivIoctl(adapter->fd, OPE_INT, &ioctl_cfg); + + E220SetRegisterParam(adapter, E220_ADDRESS, E220_CHANNEL, E220_UART_BAUD_RATE); + + ADAPTER_DEBUG("E220Open done\n"); + + return 0; +} + +/** + * @description: Close E220 uart function + * @param adapter - Lora device pointer + * @return success: 0, failure: -1 + */ +static int E220Close(struct Adapter *adapter) +{ + /*step1: close e220 uart port*/ + int ret; + ret = PrivClose(adapter->fd); + if(ret < 0) { + printf("E220 close failed: %d!\n", ret); + return -1; + } + + ADAPTER_DEBUG("E220 Close done\n"); + + return 0; +} + +/** + * @description: E220 ioctl function + * @param adapter - Lora device pointer + * @param cmd - ioctl cmd + * @param args - iotl params + * @return success: 0, failure: -1 + */ +static int E220Ioctl(struct Adapter *adapter, int cmd, void *args) +{ + /*to do*/ + return 0; +} + +/** + * @description: E220 join lora net group function + * @param adapter - Lora device pointer + * @param priv_net_group - priv_net_group params + * @return success: 0, failure: -1 + */ +static int E220Join(struct Adapter *adapter, unsigned char *priv_net_group) +{ + int ret; + struct AdapterData *priv_net_group_data = (struct AdapterData *)priv_net_group; + + ret = PrivWrite(adapter->fd, (void *)priv_net_group_data->buffer, priv_net_group_data->len); + if(ret < 0) { + printf("E220 Join net group failed: %d!\n", ret); + } + + return ret; +} + +/** + * @description: E220 send data function + * @param adapter - Lora device pointer + * @param buf - data buffers + * @param len - data len + * @return success: 0, failure: -1 + */ +static int E220Send(struct Adapter *adapter, const void *buf, size_t len) +{ + int ret; + + ret = PrivWrite(adapter->fd, (void *)buf, len); + if(ret < 0){ + printf("send failed %d!\n", ret); + } + + return ret; +} + +/** + * @description: E220 receive data function + * @param adapter - Lora device pointer + * @param buf - data buffers + * @param len - data len + * @return success: 0, failure: -1 + */ +static int E220Recv(struct Adapter *adapter, void *buf, size_t len) +{ + int recv_len, recv_len_continue; + + uint8 *recv_buf = PrivMalloc(len); + + recv_len = PrivRead(adapter->fd, recv_buf, len); + while (recv_len < len) { + recv_len_continue = PrivRead(adapter->fd, recv_buf + recv_len, len - recv_len); + + recv_len += recv_len_continue; + } + + memcpy(buf, recv_buf, recv_len); + + PrivFree(recv_buf); + + return recv_len; +} + +/** + * @description: E220 quit lora net group function + * @param adapter - Lora device pointer + * @param priv_net_group - priv_net_group params + * @return success: 0, failure: -1 + */ +static int E220Quit(struct Adapter *adapter, unsigned char *priv_net_group) +{ + int ret; + + struct AdapterData *priv_net_group_data = (struct AdapterData *)priv_net_group; + + ret = PrivWrite(adapter->fd, (void *)priv_net_group_data->buffer, priv_net_group_data->len); + if(ret < 0){ + printf("E220 quit net group failed %d!\n", ret); + } + + return ret; +} + +static const struct PrivProtocolDone e220_done = +{ + .open = E220Open, + .close = E220Close, + .ioctl = E220Ioctl, + .setup = NULL, + .setdown = NULL, + .setaddr = NULL, + .setdns = NULL, + .setdhcp = NULL, + .ping = NULL, + .netstat = NULL, + .join = E220Join, + .send = E220Send, + .recv = E220Recv, + .quit = E220Quit, +}; + +AdapterProductInfoType E220Attach(struct Adapter *adapter) +{ + struct AdapterProductInfo *product_info = malloc(sizeof(struct AdapterProductInfo)); + if (!product_info) { + printf("E220Attach malloc product_info error\n"); + return NULL; + } + + strncpy(product_info->model_name, ADAPTER_LORA_E220,sizeof(product_info->model_name)); + product_info->model_done = (void *)&e220_done; + + return product_info; +} + +//###################TEST#################### +static void LoraOpen(void) +{ + struct Adapter *adapter = AdapterDeviceFindByName(ADAPTER_LORA_NAME); + if (NULL == adapter) { + printf("LoraReceive find lora adapter error\n"); + return; + } + + E220Open(adapter); +} + +static void LoraRead(void *parameter) +{ + int RevLen; + uint8 i, cnt = 0; + + uint8 buffer[256]; + + memset(buffer, 0, 256); + + struct Adapter *adapter = AdapterDeviceFindByName(ADAPTER_LORA_NAME); + if (NULL == adapter) { + printf("LoraRead find lora adapter error\n"); + return; + } + + while (1) + { + KPrintf("ready to read lora data\n"); + + RevLen = E220Recv(adapter, buffer, 256); + if (RevLen) { + KPrintf("lora get data %u\n", RevLen); + for (i = 0; i < RevLen; i ++) { + printf("i %u data 0x%x\n", i, buffer[i]); + } + + memset(buffer, 0, 256); + + PrivTaskDelay(1000); + + cnt ++; + E220Send(adapter, &cnt, 1); + } + } +} + +static void LoraTest(void) +{ + int ret; + + LoraOpen(); + + int task_lora_read = KTaskCreate("task_lora_read", LoraRead, NONE, 2048, 10); + ret = StartupKTask(task_lora_read); + if (ret != EOK) { + KPrintf("StartupKTask task_lora_read failed .\n"); + return; + } +} +SHELL_EXPORT_CMD(SHELL_CMD_PERMISSION(0)|SHELL_CMD_TYPE(SHELL_TYPE_CMD_MAIN), +LoraTest, LoraTest, lora send and receive message); + +static void LoraSend(int argc, char *argv[]) +{ + struct Adapter *adapter = AdapterDeviceFindByName(ADAPTER_LORA_NAME); + if (NULL == adapter) { + printf("LoraRead find lora adapter error\n"); + return; + } + + char Msg[256] = {0}; + + if (argc == 2) { + strncpy(Msg, argv[1], 256); + + E220Send(adapter, Msg, strlen(Msg)); + } +} +SHELL_EXPORT_CMD(SHELL_CMD_PERMISSION(0)|SHELL_CMD_TYPE(SHELL_TYPE_CMD_MAIN), +LoraSend, LoraSend, lora send message); diff --git a/APP_Framework/Framework/connection/lora/sx1278/Kconfig b/APP_Framework/Framework/connection/lora/sx1278/Kconfig new file mode 100644 index 0000000..4439c3f --- /dev/null +++ b/APP_Framework/Framework/connection/lora/sx1278/Kconfig @@ -0,0 +1,20 @@ +config ADAPTER_LORA_SX1278 + string "SX1278 adapter name" + default "sx1278" + +if ADD_XIZI_FETURES + config ADAPTER_SX1278_DRIVER + string "SX1278 device spi driver path" + default "/dev/spi2_lora" +endif + +if ADD_NUTTX_FETURES + config ADAPTER_SX1278_DRIVER + string "SX1278 device spi driver path" + default "/dev/spi2_lora" + +endif + +if ADD_RTTHREAD_FETURES + +endif diff --git a/APP_Framework/Framework/connection/lora/sx1278/Make.defs b/APP_Framework/Framework/connection/lora/sx1278/Make.defs new file mode 100644 index 0000000..c5279e9 --- /dev/null +++ b/APP_Framework/Framework/connection/lora/sx1278/Make.defs @@ -0,0 +1,6 @@ +############################################################################ +# APP_Framework/Framework/connection/lora/sx1278/Make.defs +############################################################################ +ifneq ($(CONFIG_ADAPTER_LORA_SX1278),) +CONFIGURED_APPS += $(APPDIR)/../../../APP_Framework/Framework/connection/lora/sx1278 +endif diff --git a/APP_Framework/Framework/connection/lora/sx1278/Makefile b/APP_Framework/Framework/connection/lora/sx1278/Makefile new file mode 100644 index 0000000..636fa52 --- /dev/null +++ b/APP_Framework/Framework/connection/lora/sx1278/Makefile @@ -0,0 +1,13 @@ +include $(KERNEL_ROOT)/.config +ifeq ($(CONFIG_ADD_NUTTX_FETURES),y) + include $(APPDIR)/Make.defs + CSRCS += sx1278.c + include $(APPDIR)/Application.mk + +endif + +ifeq ($(CONFIG_ADD_XIZI_FETURES),y) + SRC_FILES := sx1278.c + include $(KERNEL_ROOT)/compiler.mk + +endif diff --git a/APP_Framework/Framework/connection/lora/sx1278/sx1278.c b/APP_Framework/Framework/connection/lora/sx1278/sx1278.c new file mode 100644 index 0000000..dda8b54 --- /dev/null +++ b/APP_Framework/Framework/connection/lora/sx1278/sx1278.c @@ -0,0 +1,258 @@ +/* +* Copyright (c) 2020 AIIT XUOS Lab +* XiUOS is licensed under Mulan PSL v2. +* You can use this software according to the terms and conditions of the Mulan PSL v2. +* You may obtain a copy of Mulan PSL v2 at: +* http://license.coscl.org.cn/MulanPSL2 +* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, +* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, +* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. +* See the Mulan PSL v2 for more details. +*/ + +/** + * @file sx1278.c + * @brief Implement the connection lora adapter function + * @version 1.1 + * @author AIIT XUOS Lab + * @date 2021.10.20 + */ + +#include + +#ifdef ADD_NUTTX_FETURES + /** + * @description: Sx127x_Nuttx_Write function for nuttx + * @param fd - file descriptor to write to + * @param buf - Data to write + * @param buf - Length of data to write + * @return On success, the number of bytes written are returned (zero indicates nothing was written). On error, -1 is returned. + */ +static int Sx127x_Nuttx_Write(int fd, const void *buf, size_t len) +{ + int ret; + + unsigned char *buffer = (unsigned char*)PrivMalloc(256); + if (!buffer) + { + printf("failed to allocate buffer\n"); + } + memset(buffer, 0, 256); + memcpy(buffer,(unsigned char *)buf,len); + + ret = PrivWrite(fd, buffer, len); + PrivFree(buffer); + + return ret; +} +#endif +/** + * @description: Open SX1278 spi function + * @param adapter - Lora device pointer + * @return success: 0, failure: -1 + */ +static int Sx1278Open(struct Adapter *adapter) +{ + /*step1: open sx1278 spi port*/ + adapter->fd = PrivOpen(ADAPTER_SX1278_DRIVER, O_RDWR); + if (adapter->fd < 0) { + printf("Sx1278Open get spi %s fd error\n", ADAPTER_SX1278_DRIVER); + return -1; + } + + printf("Sx1278Open done\n"); + + return 0; +} + +/** + * @description: Close SX1278 spi function + * @param adapter - Lora device pointer + * @return success: 0, failure: -1 + */ +static int Sx1278Close(struct Adapter *adapter) +{ + /*step1: close sx1278 spi port*/ + int ret; + ret = PrivClose(adapter->fd); + if(ret < 0){ + printf("Sx1278 close failed: %d!\n", ret); + return -1; + } + + ADAPTER_DEBUG("Sx1278 Close done\n"); + + return 0; +} + +/** + * @description: SX1278 ioctl function + * @param adapter - Lora device pointer + * @param cmd - ioctl cmd + * @param args - iotl params + * @return success: 0, failure: -1 + */ +static int Sx1278Ioctl(struct Adapter *adapter, int cmd, void *args) +{ + /*to do*/ + return 0; +} + +/** + * @description: SX1278 join lora net group function + * @param adapter - Lora device pointer + * @param priv_net_group - priv_net_group params + * @return success: 0, failure: -1 + */ +#ifdef ADD_NUTTX_FETURES +static int Sx1278Join(struct Adapter *adapter, unsigned char *priv_net_group) +{ + int ret; + struct AdapterData *priv_net_group_data = (struct AdapterData *)priv_net_group; + + ret = Sx127x_Nuttx_Write(adapter->fd, (void *)priv_net_group_data->buffer, priv_net_group_data->len); + if(ret < 0){ + printf("Sx1278 Join net group failed: %d!\n", ret); + } + + return ret; +} +#else +static int Sx1278Join(struct Adapter *adapter, unsigned char *priv_net_group) +{ + int ret; + struct AdapterData *priv_net_group_data = (struct AdapterData *)priv_net_group; + + ret = PrivWrite(adapter->fd, (void *)priv_net_group_data->buffer, priv_net_group_data->len); + if(ret < 0){ + printf("Sx1278 Join net group failed: %d!\n", ret); + } + + return ret; +} +#endif + + +/** + * @description: SX1278 send data function + * @param adapter - Lora device pointer + * @param buf - data buffers + * @param len - data len + * @return success: 0, failure: -1 + */ +#ifdef ADD_NUTTX_FETURES +static int Sx1278Send(struct Adapter *adapter, const void *buf, size_t len) +{ + int ret; + ret = Sx127x_Nuttx_Write(adapter->fd, buf, len); + if(ret < 0){ + printf("send failed %d!\n", ret); + } + return ret; +} +#else +static int Sx1278Send(struct Adapter *adapter, const void *buf, size_t len) +{ + int ret; + ret = PrivWrite(adapter->fd, buf, len); + if(ret < 0){ + printf("send failed %d!\n", ret); + } + + return ret; +} +#endif + +/** + * @description: SX1278 receive data function + * @param adapter - Lora device pointer + * @param buf - data buffers + * @param len - data len + * @return success: 0, failure: -1 + */ +#ifdef ADD_NUTTX_FETURES +static int Sx1278Recv(struct Adapter *adapter, void *buf, size_t len) +{ + int ret; + struct sx127x_read_hdr_s recv_data; + ret = read(adapter->fd, &recv_data, sizeof(struct sx127x_read_hdr_s)); + if (ret <= 0){ + printf("Read failed %d!\n", ret); + return ret; + } + memcpy((uint8 *)buf, (uint8 *)(&recv_data), len); + return ret; +} +#else +static int Sx1278Recv(struct Adapter *adapter, void *buf, size_t len) +{ + return PrivRead(adapter->fd, buf, len); +} +#endif + +/** + * @description: SX1278 quit lora net group function + * @param adapter - Lora device pointer + * @param priv_net_group - priv_net_group params + * @return success: 0, failure: -1 + */ +#ifdef ADD_NUTTX_FETURES +static int Sx1278Quit(struct Adapter *adapter, unsigned char *priv_net_group) +{ + int ret; + struct AdapterData *priv_net_group_data = (struct AdapterData *)priv_net_group; + + ret = Sx127x_Nuttx_Write(adapter->fd, (void *)priv_net_group_data->buffer, priv_net_group_data->len); + if(ret < 0){ + printf("Sx1278 quit net group failed %d!\n", ret); + } + + return ret; +} +#else +static int Sx1278Quit(struct Adapter *adapter, unsigned char *priv_net_group) +{ + int ret; + struct AdapterData *priv_net_group_data = (struct AdapterData *)priv_net_group; + + ret = PrivWrite(adapter->fd, (void *)priv_net_group_data->buffer, priv_net_group_data->len); + if(ret < 0){ + printf("Sx1278 quit net group failed %d!\n", ret); + } + + return ret; +} + +#endif + +static const struct PrivProtocolDone sx1278_done = +{ + .open = Sx1278Open, + .close = Sx1278Close, + .ioctl = Sx1278Ioctl, + .setup = NULL, + .setdown = NULL, + .setaddr = NULL, + .setdns = NULL, + .setdhcp = NULL, + .ping = NULL, + .netstat = NULL, + .join = Sx1278Join, + .send = Sx1278Send, + .recv = Sx1278Recv, + .quit = Sx1278Quit, +}; + +AdapterProductInfoType Sx1278Attach(struct Adapter *adapter) +{ + struct AdapterProductInfo *product_info = malloc(sizeof(struct AdapterProductInfo)); + if (!product_info) { + printf("Sx1278Attach malloc product_info error\n"); + return NULL; + } + + strncpy(product_info->model_name, ADAPTER_LORA_SX1278,sizeof(product_info->model_name)); + product_info->model_done = (void *)&sx1278_done; + + return product_info; +} diff --git a/APP_Framework/Framework/connection/nbiot/Kconfig b/APP_Framework/Framework/connection/nbiot/Kconfig new file mode 100644 index 0000000..bf9a087 --- /dev/null +++ b/APP_Framework/Framework/connection/nbiot/Kconfig @@ -0,0 +1,10 @@ +if CONNECTION_ADAPTER_NB + config ADAPTER_BC28 + bool "Using nbiot adapter device BC28" + default y + + if ADAPTER_BC28 + source "$APP_DIR/Framework/connection/nbiot/bc28/Kconfig" + endif + +endif diff --git a/APP_Framework/Framework/connection/nbiot/Makefile b/APP_Framework/Framework/connection/nbiot/Makefile new file mode 100644 index 0000000..29f2e7d --- /dev/null +++ b/APP_Framework/Framework/connection/nbiot/Makefile @@ -0,0 +1,7 @@ +SRC_FILES := adapter_nbiot.c + +ifeq ($(CONFIG_ADAPTER_BC28),y) + SRC_DIR += bc28 +endif + +include $(KERNEL_ROOT)/compiler.mk diff --git a/APP_Framework/Framework/connection/nbiot/adapter_nbiot.c b/APP_Framework/Framework/connection/nbiot/adapter_nbiot.c new file mode 100644 index 0000000..873ff6d --- /dev/null +++ b/APP_Framework/Framework/connection/nbiot/adapter_nbiot.c @@ -0,0 +1,171 @@ +/* +* Copyright (c) 2020 AIIT XUOS Lab +* XiUOS is licensed under Mulan PSL v2. +* You can use this software according to the terms and conditions of the Mulan PSL v2. +* You may obtain a copy of Mulan PSL v2 at: +* http://license.coscl.org.cn/MulanPSL2 +* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, +* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, +* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. +* See the Mulan PSL v2 for more details. +*/ + +/** + * @file adapter_nbiot.c + * @brief Implement the connection nbiot adapter function + * @version 1.1 + * @author AIIT XUOS Lab + * @date 2021.06.25 + */ +#include +#include +#include + +#ifdef ADAPTER_BC28 +extern AdapterProductInfoType BC28Attach(struct Adapter *adapter); +#endif + +static int AdapterNbiotRegister(struct Adapter *adapter) +{ + int ret = 0; + + strncpy(adapter->name, ADAPTER_NBIOT_NAME, NAME_NUM_MAX); + + adapter->net_protocol = IP_PROTOCOL; + adapter->net_role = CLIENT; + + adapter->adapter_status = UNREGISTERED; + + ret = AdapterDeviceRegister(adapter); + if (ret < 0) { + printf("AdapterNbiot register error\n"); + return -1; + } + + return ret; +} + +int AdapterNbiotInit(void) +{ + int ret = 0; + + struct Adapter *adapter = PrivMalloc(sizeof(struct Adapter)); + if (!adapter) { + printf("malloc adapter failed.\n"); + return -1; + } + memset(adapter, 0, sizeof(struct Adapter)); + ret = AdapterNbiotRegister(adapter); + if (ret < 0) { + printf("register nbiot adapter error\n"); + PrivFree(adapter); + return -1; + } +#ifdef ADAPTER_BC28 + AdapterProductInfoType product_info = BC28Attach(adapter); + if (!product_info) { + printf("bc28 attach error\n"); + PrivFree(adapter); + return -1; + } + + adapter->product_info_flag = 1; + adapter->info = product_info; + adapter->done = product_info->model_done; +#endif + + return ret; +} + +/******************TEST*********************/ +int opennb(void) +{ + int ret = 0; + + struct Adapter* adapter = AdapterDeviceFindByName(ADAPTER_NBIOT_NAME); + +#ifdef ADAPTER_BC28 + ret = AdapterDeviceOpen(adapter); + if(ret < 0){ + printf("open adapter failed\n"); + return -1; + } + +#endif + + return 0; + } +// SHELL_EXPORT_CMD(SHELL_CMD_PERMISSION(0)|SHELL_CMD_TYPE(SHELL_TYPE_CMD_FUNC)|SHELL_CMD_PARAM_NUM(0)|SHELL_CMD_DISABLE_RETURN, opennb, opennb, show adapter nb information); +int closenb(void) +{ + int ret = 0; + + struct Adapter* adapter = AdapterDeviceFindByName(ADAPTER_NBIOT_NAME); + +#ifdef ADAPTER_BC28 + ret = AdapterDeviceClose(adapter); + if(ret < 0){ + printf("open adapter failed\n"); + return -1; + } + +#endif + + return 0; + } +// SHELL_EXPORT_CMD(SHELL_CMD_PERMISSION(0)|SHELL_CMD_TYPE(SHELL_TYPE_CMD_FUNC)|SHELL_CMD_PARAM_NUM(0)|SHELL_CMD_DISABLE_RETURN, closenb, closenb, show adapter nb information); + + int connectnb(int argc, char *argv[]) + { + const char *send_msg = argv[1]; + int ret = 0; + + struct Adapter* adapter = AdapterDeviceFindByName(ADAPTER_NBIOT_NAME); + + + ret = AdapterDeviceConnect(adapter, 1, "101.68.82.219","9898",1); + if(ret < 0){ + printf(" adapter send failed\n"); + return -1; + } + + + + return 0; + } +// SHELL_EXPORT_CMD(SHELL_CMD_PERMISSION(0)|SHELL_CMD_TYPE(SHELL_TYPE_CMD_MAIN)|SHELL_CMD_PARAM_NUM(2)|SHELL_CMD_DISABLE_RETURN, connectnb, connectnb, show adapter nb information); + + int sendnb(int argc, char *argv[]) + { + const char *send_msg = argv[1]; + int msg_len = atoi(argv[2]); + int ret = 0; + + struct Adapter* adapter = AdapterDeviceFindByName(ADAPTER_NBIOT_NAME); + + printf("send argv1 %s len = %d\n",argv[1],msg_len); + ret = AdapterDeviceSend(adapter, send_msg, msg_len); + if(ret < 0){ + printf(" adapter send failed\n"); + return -1; + } + printf("nb send msg %s\n", send_msg); + + + return 0; + } +// SHELL_EXPORT_CMD(SHELL_CMD_PERMISSION(0)|SHELL_CMD_TYPE(SHELL_TYPE_CMD_MAIN)|SHELL_CMD_PARAM_NUM(2)|SHELL_CMD_DISABLE_RETURN, sendnb, sendnb, show adapter nb information); + + int recvnb(void) + { + char recv_msg[128]; + struct Adapter* adapter = AdapterDeviceFindByName(ADAPTER_NBIOT_NAME); + memset(recv_msg,0,128); + AdapterDeviceRecv(adapter, recv_msg, 128); + PrivTaskDelay(2000); + printf("nb recv msg %s\n", recv_msg); + + return 0; + } +// SHELL_EXPORT_CMD(SHELL_CMD_PERMISSION(0)|SHELL_CMD_TYPE(SHELL_TYPE_CMD_FUNC)|SHELL_CMD_PARAM_NUM(0)|SHELL_CMD_DISABLE_RETURN, recvnb, recvnb, show adapter nb information); + diff --git a/APP_Framework/Framework/connection/nbiot/adapter_nbiot.h b/APP_Framework/Framework/connection/nbiot/adapter_nbiot.h new file mode 100644 index 0000000..97c6986 --- /dev/null +++ b/APP_Framework/Framework/connection/nbiot/adapter_nbiot.h @@ -0,0 +1,12 @@ +#ifndef ADAPTER_NBIOT_H +#define ADAPTER_NBIOT_H + +#define CONFIG_NBIOT_RESET (0) +#define CONFIG_NBIOT_CREATE_SOCKET (1) +#define CONFIG_NBIOT_DELETE_SOCKET (2) + +#define SOCKET_TYPE_DGRAM (0) +#define SOCKET_TYPE_STREAM (1) + + +#endif \ No newline at end of file diff --git a/APP_Framework/Framework/connection/nbiot/bc28/Kconfig b/APP_Framework/Framework/connection/nbiot/bc28/Kconfig new file mode 100644 index 0000000..ae773a1 --- /dev/null +++ b/APP_Framework/Framework/connection/nbiot/bc28/Kconfig @@ -0,0 +1,40 @@ +config ADAPTER_NBIOT_BC28 + string "BC28 adapter name" + default "bc28" + +if ADD_XIZI_FETURES + config ADAPTER_BC28_RESETPIN + int "BC28 RESET pin number" + default "100" + + config ADAPTER_BC28_PIN_DRIVER + string "BC28 device pin driver path" + default "/dev/pin_dev" + + config ADAPTER_BC28_DRIVER_EXTUART + bool "Using extra uart to support nbiot" + default n + + config ADAPTER_BC28_DRIVER + string "BC28 device uart driver path" + default "/dev/usart2_dev2" + depends on !ADAPTER_BC28_DRIVER_EXTUART + + if ADAPTER_BC28_DRIVER_EXTUART + config ADAPTER_BC28_DRIVER + string "BC28 device extra uart driver path" + default "/dev/extuart_dev5" + + config ADAPTER_BC28_DRIVER_EXT_PORT + int "if BC28 device using extuart, choose port" + default "5" + endif +endif + +if ADD_NUTTX_FETURES + +endif + +if ADD_RTTHREAD_FETURES + +endif diff --git a/APP_Framework/Framework/connection/nbiot/bc28/Makefile b/APP_Framework/Framework/connection/nbiot/bc28/Makefile new file mode 100644 index 0000000..3963d11 --- /dev/null +++ b/APP_Framework/Framework/connection/nbiot/bc28/Makefile @@ -0,0 +1,3 @@ +SRC_FILES := bc28.c + +include $(KERNEL_ROOT)/compiler.mk \ No newline at end of file diff --git a/APP_Framework/Framework/connection/nbiot/bc28/bc28.c b/APP_Framework/Framework/connection/nbiot/bc28/bc28.c new file mode 100644 index 0000000..e9c83ac --- /dev/null +++ b/APP_Framework/Framework/connection/nbiot/bc28/bc28.c @@ -0,0 +1,796 @@ +/* +* Copyright (c) 2020 AIIT XUOS Lab +* XiUOS is licensed under Mulan PSL v2. +* You can use this software according to the terms and conditions of the Mulan PSL v2. +* You may obtain a copy of Mulan PSL v2 at: +* http://license.coscl.org.cn/MulanPSL2 +* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, +* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, +* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. +* See the Mulan PSL v2 for more details. +*/ + +/** + * @file bc28.c + * @brief Implement the connection nbiot adapter function, using BC28 device + * @version 1.1 + * @author AIIT XUOS Lab + * @date 2021.09.15 + */ + +#include +#include +#include "../adapter_nbiot.h" +#include + +#define SOCKET_PROTOCOL_TCP (6) +#define SOCKET_PROTOCOL_UDP (17) + +#define NET_TYPE_AF_INET (0) +#define NET_TYPE_AF_INET6 (1) + +#define SOCKET_INVALID_ID (-1) +static int nbiot_lock; + +static int BC28UartOpen(struct Adapter *adapter) +{ + if (NULL == adapter) { + return -1; + } + + /* Open device in read-write mode */ + adapter->fd = PrivOpen(ADAPTER_BC28_DRIVER,O_RDWR); + if (adapter->fd < 0) { + printf("BC28UartOpen get serial %s fd error\n", ADAPTER_BC28_DRIVER); + return -1; + } + /* set serial config, serial_baud_rate = 9600 */ + + struct SerialDataCfg cfg; + memset(&cfg, 0 ,sizeof(struct SerialDataCfg)); + + cfg.serial_baud_rate = BAUD_RATE_9600; + cfg.serial_data_bits = DATA_BITS_8; + cfg.serial_stop_bits = STOP_BITS_1; + cfg.serial_parity_mode = PARITY_NONE; + cfg.serial_bit_order = BIT_ORDER_LSB; + cfg.serial_invert_mode = NRZ_NORMAL; + cfg.serial_buffer_size = SERIAL_RB_BUFSZ; + + /*aiit board use ch438, so it needs more serial configuration*/ +#ifdef ADAPTER_BC28_DRIVER_EXTUART + cfg.ext_uart_no = ADAPTER_BC28_DRIVER_EXT_PORT; + cfg.port_configure = PORT_CFG_INIT; +#endif + + struct PrivIoctlCfg ioctl_cfg; + ioctl_cfg.ioctl_driver_type = SERIAL_TYPE; + ioctl_cfg.args = &cfg; + + PrivIoctl(adapter->fd, OPE_INT, &ioctl_cfg); + PrivTaskDelay(1000); + + printf("NBIot uart config ready\n"); + return 0; +} + +static void BC28PowerSet(void) +{ + int pin_fd; + pin_fd = PrivOpen(ADAPTER_BC28_PIN_DRIVER, O_RDWR); + + struct PinParam pin_param; + pin_param.cmd = GPIO_CONFIG_MODE; + pin_param.mode = GPIO_CFG_OUTPUT; + pin_param.pin = ADAPTER_BC28_RESETPIN; + + struct PrivIoctlCfg ioctl_cfg; + ioctl_cfg.ioctl_driver_type = PIN_TYPE; + ioctl_cfg.args = &pin_param; + PrivIoctl(pin_fd, OPE_CFG, &ioctl_cfg); + + struct PinStat pin_stat; + pin_stat.pin = ADAPTER_BC28_RESETPIN; + pin_stat.val = GPIO_HIGH; + PrivWrite(pin_fd, &pin_stat, 1); + + PrivTaskDelay(200);//at least 200ms + + pin_stat.val = GPIO_LOW; + PrivWrite(pin_fd, &pin_stat, 1); + + PrivClose(pin_fd); +} + +int NBIoTStatusCheck(struct Adapter *adapter ) +{ + int32 result = 0; + + if (!adapter ){ + return -1; + } + + char at_cmd[64] = {0}; + + AtSetReplyEndChar(adapter->agent, 0x4F, 0x4B); /* set receive end flag as 'OK'*/ + memset(at_cmd, 0 ,64); + memcpy(at_cmd, "AT+NCONFIG=AUTOCONNECT,TRUE", 27); + strcat(at_cmd, "\n"); + printf("cmd : %s\n", at_cmd); + ATOrderSend(adapter->agent, 0, NULL, at_cmd); + + PrivTaskDelay(10000); + + // memset(at_cmd, 0 ,64); + // memcpy(at_cmd, "AT+NRB", 6); + // strcat(at_cmd, "\n"); + // printf("cmd : %s\n", at_cmd); + // result = AtCmdConfigAndCheck(adapter->agent, at_cmd, "OK"); + // if(result < 0) { + // printf("%s %d cmd[%s] config failed!\n",__func__,__LINE__,at_cmd); + // result = -1; + // goto out; + // } + // BC28PowerSet(); /* reset bc28 module by set reset pin */ + // PrivTaskDelay(6000); + + // memset(at_cmd, 0 ,64); + // memcpy(at_cmd, "AT+NBAND=5", 10); + // strcat(at_cmd, "\n"); + // printf("cmd : %s\n", at_cmd); + // result = AtCmdConfigAndCheck(adapter->agent, at_cmd, "OK"); + // if(result < 0) { + // printf("%s %d cmd[%s] config failed!\n",__func__,__LINE__,at_cmd); + // result = -1; + // goto out; + // } + + + // memset(at_cmd, 0 ,64); + // memcpy(at_cmd, "AT+CFUN=1", 10); + // strcat(at_cmd, "\n"); + // printf("cmd : %s\n", at_cmd); + // result = AtCmdConfigAndCheck(adapter->agent, at_cmd, "OK"); + // if(result < 0) { + // printf("%s %d cmd[%s] config failed!\n",__func__,__LINE__,at_cmd); + // result = -1; + // goto out; + // } + + AtSetReplyEndChar(adapter->agent, 0x4F, 0x4B); /* set receive end flag as 'OK'*/ + memset(at_cmd, 0 ,64); + memcpy(at_cmd, "AT+CFUN?", 8); + strcat(at_cmd, "\n"); + printf("cmd : %s\n", at_cmd); + result = AtCmdConfigAndCheck(adapter->agent, at_cmd, "OK"); + if(result < 0) { + printf("%s %d cmd[%s] config failed!\n",__func__,__LINE__,at_cmd); + result = -1; + goto out; + } + + memset(at_cmd, 0 ,64); + memcpy(at_cmd, "AT+CIMI", 7); + strcat(at_cmd, "\n"); + printf("cmd : %s\n", at_cmd); + result = AtCmdConfigAndCheck(adapter->agent, at_cmd, "OK"); + if(result < 0) { + printf("%s %d cmd[%s] config failed!\n",__func__,__LINE__,at_cmd); + result = -1; + goto out; + } + + memset(at_cmd, 0 ,64); + memcpy(at_cmd, "AT+CEREG?", 9); + strcat(at_cmd, "\n"); + printf("cmd : %s\n", at_cmd); + result = AtCmdConfigAndCheck(adapter->agent, at_cmd, ",1"); + if(result < 0) { + printf("%s %d cmd[%s] config failed!\n",__func__,__LINE__,at_cmd); + result = -1; + goto out; + } + + // memset(at_cmd, 0 ,64); + // memcpy(at_cmd, "AT+CGATT=1", 10); + // strcat(at_cmd, "\n"); + // printf("cmd : %s\n", at_cmd); + // result = AtCmdConfigAndCheck(adapter->agent, at_cmd, "OK"); + // if(result < 0) { + // printf("%s %d cmd[%s] config failed!\n",__func__,__LINE__,at_cmd); + // result = -1; + // goto out; + // } + + memset(at_cmd, 0 ,64); + memcpy(at_cmd, "AT+CGATT?", 9); + strcat(at_cmd, "\n"); + printf("cmd : %s\n", at_cmd); + result = AtCmdConfigAndCheck(adapter->agent, at_cmd, "OK"); + if(result < 0) { + printf("%s %d cmd[%s] config failed!\n",__func__,__LINE__,at_cmd); + result = -1; + goto out; + } + + memset(at_cmd, 0 ,64); + memcpy(at_cmd, "AT+CSQ", 6); + strcat(at_cmd, "\n"); + printf("cmd : %s\n", at_cmd); + result = AtCmdConfigAndCheck(adapter->agent, at_cmd, "OK"); + if(result < 0) { + printf("%s %d cmd[%s] config failed!\n",__func__,__LINE__,at_cmd); + result = -1; + goto out; + } + + memset(at_cmd, 0 ,64); + memcpy(at_cmd, "AT+CGPADDR", 10); + strcat(at_cmd, "\n"); + printf("cmd : %s\n", at_cmd); + result = AtCmdConfigAndCheck(adapter->agent, at_cmd, "OK"); + if(result < 0) { + printf("%s %d cmd[%s] config failed!\n",__func__,__LINE__,at_cmd); + result = -1; + } + + memset(at_cmd, 0 ,64); + memcpy(at_cmd, "AT+QREGSWT=2", 12); + strcat(at_cmd, "\n"); + printf("cmd : %s\n", at_cmd); + result = AtCmdConfigAndCheck(adapter->agent, at_cmd, "OK"); + if(result < 0) { + printf("%s %d cmd[%s] config failed!\n",__func__,__LINE__,at_cmd); + result = -1; + goto out; + } + +out: + return result; +} + +/** + * @description: NBIoT device create a socket connection + * @param adapter - NBIoT adapter AT + * @param socket_fd - socket file description + * @param type - socket type + * @param af_type - IPv4 or IPv6 + * @return success: EOK, failure: -ERROR + */ +int NBIoTSocketCreate(struct Adapter *adapter, struct Socket *socket ) +{ + int32 result = 0; + + if (!adapter || !socket){ + return -1; + } + + if ( socket->af_type == NET_TYPE_AF_INET6 ) { + printf("IPv6 not surport !\n"); + result = -1; + goto out; + } + + char *str_af_type = "AF_INET"; + char *str_type; + char str_fd[3] = {1}; + char *str_protocol ; + char at_cmd[64] = {0}; + char listen_port[] = {0}; + + if (socket->socket_id >= 0 && socket->socket_id < 7) { + itoa(socket->socket_id, str_fd, 10); + adapter->socket.socket_id = socket->socket_id; + } else { + printf("surport max 0-6, socket_id = [%d] is error!\n",socket->socket_id); + result = -1; + goto out; + } + + if( socket->listen_port >= 0 && socket->listen_port <= 65535){ + itoa(socket->listen_port, listen_port, 10); + } + + adapter->socket.af_type = NET_TYPE_AF_INET; + + if (socket->type == SOCKET_TYPE_STREAM) { //tcp = AT+NSOCR=STREAM,6,0,1,AF_INET + adapter->socket.protocal = SOCKET_PROTOCOL_TCP; + adapter->socket.type = SOCKET_TYPE_STREAM; + str_type = "STREAM"; + str_protocol = "6"; + + } else if ( socket->type == SOCKET_TYPE_DGRAM ){ //udp + adapter->socket.type = SOCKET_TYPE_DGRAM; + adapter->socket.protocal = SOCKET_PROTOCOL_UDP; + str_type = "DGRAM"; + str_protocol = "17"; + + } else { + printf("error socket type \n"); + result = -1; + goto out; + } + memset(at_cmd, 0 ,64); + memcpy(at_cmd, "AT+NSOCR=", 9); + strcat(at_cmd, str_type); + strcat(at_cmd, ","); + strcat(at_cmd, str_protocol); + strcat(at_cmd, ","); + strcat(at_cmd, listen_port); + strcat(at_cmd, ","); + strcat(at_cmd, str_fd); + strcat(at_cmd, ","); + strcat(at_cmd, str_af_type); + strcat(at_cmd, "\n"); + + printf("cmd : %s\n", at_cmd); + + AtSetReplyEndChar(adapter->agent, 0x4F, 0x4B); /* set receive end flag as 'OK'*/ + + result = AtCmdConfigAndCheck(adapter->agent, at_cmd, "OK"); + if(result < 0) { + printf("%s %d cmd[%s] config failed!\n",__func__,__LINE__,at_cmd); + result = -1; + } + +out: + return result; +} + +static int BC28ParseData(void *dst, ATReplyType reply) +{ + int nbdata_len = 0; + int check_cnt = 0; + int left = 0; + int right = 0; + int tag = 0; + char *nbdata = NULL; + char *result = NULL; + + if (NULL == reply) { + printf("at create failed ! \n"); + return -1; + } + + result = GetReplyText(reply); + if (!result) { + printf("%s %n get reply failed.\n",__func__,__LINE__); + return -1; + } + + /*the data style of BC28: eg.',,,,,,' ,its assic code*/ + + /*step1: get the section between the fourth and fifth ','*/ + for(int i = 0; i < reply->reply_len; i++) + { + if(',' == *(result + i)) + { + check_cnt++; + if(4 == check_cnt) /*the fourth ','*/ + { + left = i; + } + + if(5 == check_cnt) /*the fifth ',' */ + { + right = i; + break; + } + } + } + if(left > 0 && right > 0) + { + /*step2: transform assic code as hexadecimal*/ + for(int j = (left + 1);j <= (right - 1);j++) + { + if(*(result + j) >= 0x30 && *(result + j) <= 0x39){ + *(result + j) = (*(result + j) - 0x30); /* transform [0-9]*/ + } + else if(*(result + j) >= 0x41 && *(result + j) <= 0x46) + { + *(result + j) = (*(result + j) - 0x37); /* transform [A-F],NOTE!!! A-F can not be regarded as a char,only can be reagrded as a number*/ + } + + printf("0x%x ",*(result + j)); + } + + printf("\n"); + nbdata_len = (right - left - 1) / 2; /*caculate the data length */ + nbdata = PrivMalloc(nbdata_len); + if (!nbdata) { + printf("%s %n malloc failed.\n",__func__,__LINE__); + return -1; + } + + tag = left; + printf("left = %d right = %d nbdata_len = %d\n",left ,right ,nbdata_len); + + /*step3: transform hexadecimal as actual data */ + for(int k = 0; k < nbdata_len; k++ ) + { + *(nbdata + k) = (*(result + tag + 1) * 16 + *(result + tag + 2)); + tag = tag + 2; /* transform with two data*/ + printf("0x%x ",*(nbdata + k)); + } + printf("\n"); + + memcpy(dst, nbdata, nbdata_len); + + PrivFree(nbdata); + + return nbdata_len; + } + else + { + return 0; + } + +} + +/** + * @description: NBIoT device close a socket connection + * @param adapter - NBIoT adapter AT + * @param socket_fd - socket file description + * @return success: EOK, failure: -ERROR + */ +int NBIoTSocketDelete(struct Adapter *adapter ) +{ + + if (!adapter) { + return -1; + } + + if (adapter->socket.socket_id >= 7) { + printf("socket fd error \n"); + return -1; + } + + char str_fd[2] = {0}; + char at_cmd[32] = {0}; + printf("NBIOT close socket id = %d\n",adapter->socket.socket_id); + itoa(adapter->socket.socket_id, str_fd, 10); + + memset(at_cmd, 0 ,32); + memcpy(at_cmd, "AT+NSOCL=", 9); + strcat(at_cmd, str_fd); + strcat(at_cmd, "\n"); + + printf("cmd : %s\n", at_cmd); + AtSetReplyCharNum(adapter->agent, 1); + ATOrderSend(adapter->agent, REPLY_TIME_OUT, NULL, at_cmd); + PrivTaskDelay(300); + + adapter->socket.socket_id = SOCKET_INVALID_ID; + + return 0; +} + +static int BC28Open(struct Adapter *adapter) +{ + int ret = 0; + struct Socket create_socket; + + if (NULL == adapter) { + return -1; + } + + if(PrivMutexCreate(&nbiot_lock, 0) < 0) { + printf("nbiot_lock mutex create failed.\n"); + return -1; + } + + /*step1: open BC8 serial port*/ + ret = BC28UartOpen(adapter); + if (ret < 0) { + printf("bc18 setup failed.\n"); + PrivMutexDelete(&nbiot_lock); + return -1; + } + + /*step2: init AT agent*/ + if (!adapter->agent) { + char *agent_name = "niot_device"; + if (EOK != InitATAgent(agent_name, adapter->fd, 512)) { + PrivClose(adapter->fd); + PrivMutexDelete(&nbiot_lock); + printf("at agent init failed !\n"); + return -1; + } + ATAgentType at_agent = GetATAgent(agent_name); + adapter->agent = at_agent; + } + + // BC28PowerSet(); /* reset bc28 module by set reset pin */ + PrivTaskDelay(6000); + + ret = NBIoTStatusCheck(adapter); /* ask module status*/ + if(ret < 0){ + DeleteATAgent(adapter->agent); + adapter->agent = NULL; + PrivMutexDelete(&nbiot_lock); + printf("NBIot status check failed.\n"); + return -1; + } + + create_socket.type = SOCKET_TYPE_STREAM; + create_socket.listen_port = 0; + create_socket.socket_id = 1; + create_socket.af_type = NET_TYPE_AF_INET; + + /*step3: create a tcp socket default */ + ret = NBIoTSocketCreate(adapter, &create_socket); + if(ret < 0) { + DeleteATAgent(adapter->agent); + adapter->agent = NULL; + PrivMutexDelete(&nbiot_lock); + printf("NBIot create tcp socket failed.\n"); + return -1; + } + + printf("NBiot BC28 open successful\n"); + return 0; +} + +static int BC28Close(struct Adapter *adapter) +{ + + if(&adapter->socket){ + NBIoTSocketDelete(adapter); + } + + if(adapter->agent) + { + DeleteATAgent(adapter->agent); + adapter->agent = NULL; + } + + PrivMutexDelete(&nbiot_lock); + return 0; +} + +static int BC28Ioctl(struct Adapter *adapter, int cmd, void *args) +{ + int ret = 0; + PrivMutexObtain(&nbiot_lock); + switch (cmd) + { + case CONFIG_NBIOT_RESET: /* reset nbiot */ + BC28PowerSet(); + break; + case CONFIG_NBIOT_CREATE_SOCKET: /* create tcp/UDP socket */ + if(!args){ + return -1; + } + struct Socket *create_socket = ( struct Socket *) args; + ret = NBIoTSocketCreate(adapter, create_socket); + break; + case CONFIG_NBIOT_DELETE_SOCKET: /* close socket */ + ret = NBIoTSocketDelete(adapter); + break; + default: + ret = -1; + break; + } + PrivMutexAbandon(&nbiot_lock); + return ret; +} + +static int BC28Connect(struct Adapter *adapter, enum NetRoleType net_role, const char *ip, const char *port, enum IpType ip_type) +{ + int result = 0; + + if (adapter->socket.socket_id > 6) { + printf("socket fd error \n"); + result = -1; + goto __exit; + } + + if ( ip_type != SOCKET_TYPE_STREAM) { + printf("socket type error \n"); + result = -1; + goto __exit; + } + + char at_cmd[64] = {0}; + char str_fd[2] = {0}; + + PrivMutexObtain(&nbiot_lock); + itoa(adapter->socket.socket_id, str_fd, 10); + + memset(at_cmd, 0 ,64); + memcpy(at_cmd, "AT+NSOCO=", 9); + strcat(at_cmd, str_fd); + strcat(at_cmd, ","); + strcat(at_cmd, ip); + strcat(at_cmd, ","); + strcat(at_cmd, port); + strcat(at_cmd, "\n"); + + printf("cmd : %s\n", at_cmd); + AtSetReplyEndChar(adapter->agent, 0x4F, 0x4B); + result = AtCmdConfigAndCheck(adapter->agent, at_cmd, "OK"); + if(result < 0) { + printf("%s %d cmd[%s] config failed!\n",__func__,__LINE__,at_cmd); + result = -1; + } + PrivMutexAbandon(&nbiot_lock); +__exit: + return result; +} + +static int BC28Send(struct Adapter *adapter, const void *buf, size_t len) +{ + uint32_t result = 0; + char at_cmd[64] = {0}; + char str_fd[2] = {0}; + char assic_str[2] = {0}; + int assic_val = 0; + int length = 0; + + PrivMutexObtain(&nbiot_lock); + + char *nbdata = PrivMalloc(2 * len); + memset(nbdata, 0 ,2 * len); + + for(int i = 0; i < len; i++) + { + assic_val = 0; + for( ; assic_val <= 0x7f; assic_val++) + { + if(*(char*)(buf + i) == assic_val) + { + break; + } + } + itoa(assic_val, assic_str, 16); + memcpy(nbdata + length, assic_str, 2); + length = length + 2; + } + if (adapter->socket.type == SOCKET_TYPE_STREAM ) { + + char size[2] = {0}; + + itoa(adapter->socket.socket_id, str_fd, 10); + size[0] = len + '0'; + + memset(at_cmd, 0 ,64); + memcpy(at_cmd, "AT+NSOSD=", 9); + strcat(at_cmd, str_fd); + strcat(at_cmd, ","); + strcat(at_cmd, size); + strcat(at_cmd, ","); + strncat(at_cmd, nbdata,length); + strcat(at_cmd, "\n"); + + } else if(adapter->socket.type == SOCKET_TYPE_DGRAM ) { + + char listen_port[] = {0}; + + itoa(adapter->socket.socket_id, str_fd, 10); + + itoa(adapter->socket.listen_port, listen_port, 10); + + memset(at_cmd, 0 ,64); + memcpy(at_cmd, "AT+NSOST=", 9); + strcat(at_cmd, str_fd); + strcat(at_cmd, ","); + strcat(at_cmd, adapter->socket.dst_ip_addr); + strcat(at_cmd, ","); + strcat(at_cmd, listen_port); + strcat(at_cmd, ","); + strncat(at_cmd, nbdata,length); + strcat(at_cmd, "\n"); + + } + PrivFree(nbdata); + printf("cmd : %s\n", at_cmd); + AtSetReplyEndChar(adapter->agent, 0x4F, 0x4B); + result = AtCmdConfigAndCheck(adapter->agent, at_cmd, "OK"); + if(result < 0) { + printf("%s %d cmd[%s] config failed!\n",__func__,__LINE__,at_cmd); + result = -1; + } + PrivMutexAbandon(&nbiot_lock); + return result; +} + + +static int BC28Recv(struct Adapter *adapter, void *buf, size_t len) +{ + char at_cmd[64] = {0}; + char str_fd[2] = {0}; + char size[2] = {0}; + int ret = 0; + char *result = NULL; + + PrivMutexObtain(&nbiot_lock); + + ATReplyType reply = CreateATReply(512); + if (NULL == reply) { + printf("at create failed ! \n"); + PrivMutexAbandon(&nbiot_lock); + return -1; + } + + itoa(adapter->socket.socket_id, str_fd, 10); + itoa(len, size, 10); + + memset(at_cmd, 0 ,64); + memcpy(at_cmd, "AT+NSORF=", 9); + strcat(at_cmd, str_fd); + strcat(at_cmd, ","); + strcat(at_cmd, size); + strcat(at_cmd, "\n"); + + printf("cmd : %s\n", at_cmd); + ret = ATOrderSend(adapter->agent, REPLY_TIME_OUT, reply, at_cmd); + if(ret < 0) + { + printf("NBiot receive timeout\n"); + DeleteATReply(reply); + return -1; + } + + if(reply) + { + ret = BC28ParseData(buf, reply); + if (ret < 0) + { + PrivMutexAbandon(&nbiot_lock); + if (reply) + { + DeleteATReply(reply); + } + return ret; + } + DeleteATReply(reply); + } + + PrivMutexAbandon(&nbiot_lock); + return ret; +} + +static int BC28Disconnect(struct Adapter *adapter) +{ + if (!adapter) { + return -1; + } + + return NBIoTSocketDelete(adapter); +} + +static const struct IpProtocolDone BC28_done = +{ + .open = BC28Open, + .close = BC28Close, + .ioctl = BC28Ioctl, + .setup = NULL, + .setdown = NULL, + .setaddr = NULL, + .setdns = NULL, + .setdhcp = NULL, + .ping = NULL, + .netstat = NULL, + .connect = BC28Connect, + .send = BC28Send, + .recv = BC28Recv, + .disconnect = BC28Disconnect, +}; + +AdapterProductInfoType BC28Attach(struct Adapter *adapter) +{ + struct AdapterProductInfo *product_info = PrivMalloc(sizeof(struct AdapterProductInfo)); + if (!product_info) { + printf("BC28Attach malloc product_info error\n"); + return NULL; + } + memset(product_info, 0, sizeof(struct AdapterProductInfo)); + + strncpy(product_info->model_name, ADAPTER_NBIOT_BC28,sizeof(product_info->model_name)); + product_info->model_done = (void *)&BC28_done; + + return product_info; +} + + + diff --git a/APP_Framework/Framework/connection/wifi/Kconfig b/APP_Framework/Framework/connection/wifi/Kconfig new file mode 100644 index 0000000..9afa7bf --- /dev/null +++ b/APP_Framework/Framework/connection/wifi/Kconfig @@ -0,0 +1,17 @@ +config ADAPTER_HFA21_WIFI + help + Please check HFA21 can only work for adapter_wifi or adapter_ethernet in the meantime! + bool "Using wifi adapter device HFA21" + default n + +if ADAPTER_HFA21_WIFI + source "$APP_DIR/Framework/connection/wifi/hfa21_wifi/Kconfig" +endif + +config ADAPTER_ESP07S_WIFI + bool "Using wifi adapter device esp07s" + default n + +if ADAPTER_ESP07S_WIFI + source "$APP_DIR/Framework/connection/wifi/esp07s_wifi/Kconfig" +endif diff --git a/APP_Framework/Framework/connection/wifi/Makefile b/APP_Framework/Framework/connection/wifi/Makefile new file mode 100644 index 0000000..2930fd9 --- /dev/null +++ b/APP_Framework/Framework/connection/wifi/Makefile @@ -0,0 +1,11 @@ +SRC_FILES := adapter_wifi.c + +ifeq ($(CONFIG_ADAPTER_HFA21_WIFI),y) + SRC_DIR += hfa21_wifi +endif + +ifeq ($(CONFIG_ADAPTER_ESP07S_WIFI),y) + SRC_DIR += esp07s_wifi +endif + +include $(KERNEL_ROOT)/compiler.mk diff --git a/APP_Framework/Framework/connection/wifi/adapter_wifi.c b/APP_Framework/Framework/connection/wifi/adapter_wifi.c new file mode 100644 index 0000000..2b9dddc --- /dev/null +++ b/APP_Framework/Framework/connection/wifi/adapter_wifi.c @@ -0,0 +1,277 @@ +/* +* Copyright (c) 2020 AIIT XUOS Lab +* XiUOS is licensed under Mulan PSL v2. +* You can use this software according to the terms and conditions of the Mulan PSL v2. +* You may obtain a copy of Mulan PSL v2 at: +* http://license.coscl.org.cn/MulanPSL2 +* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, +* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, +* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. +* See the Mulan PSL v2 for more details. +*/ + +/** + * @file adapter_wifiiiii.c + * @brief Implement the connection wifi adapter function + * @version 1.1 + * @author AIIT XUOS Lab + * @date 2021.07.25 + */ + +#include +#include "adapter_wifi.h" +#include + +#ifdef ADAPTER_HFA21_WIFI +extern AdapterProductInfoType Hfa21WifiAttach(struct Adapter *adapter); +#endif +#ifdef ADAPTER_ESP07S_WIFI +extern AdapterProductInfoType Esp07sWifiAttach(struct Adapter *adapter); +#endif + +static int AdapterWifiRegister(struct Adapter *adapter) +{ + int ret = 0; + + strncpy(adapter->name, ADAPTER_WIFI_NAME, NAME_NUM_MAX); + + adapter->net_protocol = IP_PROTOCOL; + adapter->adapter_status = UNREGISTERED; + + ret = AdapterDeviceRegister(adapter); + if (ret < 0) { + printf("AdapterWifi register error\n"); + return -1; + } + + return ret; +} + +int AdapterWifiInit(void) +{ + int ret = 0; + + struct Adapter *adapter = PrivMalloc(sizeof(struct Adapter)); + if (!adapter) { + printf("AdapterWifiInit malloc error\n"); + PrivFree(adapter); + return -1; + } + + memset(adapter, 0, sizeof(struct Adapter)); + + ret = AdapterWifiRegister(adapter); + if (ret < 0) { + printf("AdapterWifiInit register wifi adapter error\n"); + PrivFree(adapter); + return -1; + } + +#ifdef ADAPTER_HFA21_WIFI + AdapterProductInfoType product_info = Hfa21WifiAttach(adapter); + if (!product_info) { + printf("AdapterWifiInit hfa21 attach error\n"); + PrivFree(adapter); + return -1; + } + + adapter->product_info_flag = 1; + adapter->info = product_info; + adapter->done = product_info->model_done; + +#endif +#ifdef ADAPTER_ESP07S_WIFI + AdapterProductInfoType product_info = Esp07sWifiAttach(adapter); + if (!product_info) { + printf("AdapterWifiInit ESP07S attach error\n"); + PrivFree(adapter); + return -1; + } + + adapter->product_info_flag = 1; + adapter->info = product_info; + adapter->done = product_info->model_done; + +#endif + + return ret; +} + +/******************wifi TEST*********************/ +int AdapterwifiTest(void) +{ + char cmd[64]; + int baud_rate = BAUD_RATE_57600; + + struct Adapter* adapter = AdapterDeviceFindByName(ADAPTER_WIFI_NAME); + + +#ifdef ADAPTER_HFA21_DRIVER_EXT_PORT + // static BusType ch438_pin; + // ch438_pin = PinBusInitGet(); + // struct PinParam pin_cfg; + // int ret = 0; + + // struct BusConfigureInfo configure_info; + // configure_info.configure_cmd = OPE_CFG; + // configure_info.private_data = (void *)&pin_cfg; + + // pin_cfg.cmd = GPIO_CONFIG_MODE; + // pin_cfg.pin = 22; + // pin_cfg.mode = GPIO_CFG_OUTPUT; + + // ret = BusDrvConfigure(ch438_pin->owner_driver, &configure_info); + + // struct PinStat pin_stat; + // struct BusBlockWriteParam write_param; + // struct BusBlockReadParam read_param; + // write_param.buffer = (void *)&pin_stat; + + // pin_stat.val = GPIO_HIGH; + + // pin_stat.pin = 22; + // BusDevWriteData(ch438_pin->owner_haldev, &write_param); + + int pin_fd; + pin_fd = PrivOpen("/dev/pin_dev", O_RDWR); + + struct PinParam pin_param; + pin_param.cmd = GPIO_CONFIG_MODE; + pin_param.mode = GPIO_CFG_OUTPUT; + pin_param.pin = 22; + + struct PrivIoctlCfg ioctl_cfg; + ioctl_cfg.ioctl_driver_type = PIN_TYPE; + ioctl_cfg.args = &pin_param; + PrivIoctl(pin_fd, OPE_CFG, &ioctl_cfg); + + struct PinStat pin_stat; + pin_stat.pin = 52; + pin_stat.val = GPIO_HIGH; + PrivWrite(pin_fd, &pin_stat, 1); + + PrivClose(pin_fd); +#endif + + + AdapterDeviceOpen(adapter); + // AdapterDeviceControl(adapter, OPE_INT, &baud_rate); + + AdapterDeviceSetUp(adapter); + AdapterDeviceSetAddr(adapter, "192.168.64.253", "192.168.66.1", "255.255.252.0"); + AdapterDevicePing(adapter, "36.152.44.95"); + AdapterDeviceNetstat(adapter); + + const char *ip = "192.168.64.60"; + const char *port = "12345"; + enum NetRoleType net_role = CLIENT; + enum IpType ip_type = IPV4; + AdapterDeviceConnect(adapter, net_role, ip, port, ip_type); + + const char *wifi_msg = "LiuKai Test"; + int len = strlen(wifi_msg); + for(int i = 0;i < 10; ++i) { + AdapterDeviceSend(adapter, wifi_msg, len); + PrivTaskDelay(4000); + } + + char wifi_recv_msg[128]; + while (1) { + AdapterDeviceRecv(adapter, wifi_recv_msg, 128); + } + +} +SHELL_EXPORT_CMD(SHELL_CMD_PERMISSION(0)|SHELL_CMD_TYPE(SHELL_TYPE_CMD_FUNC)|SHELL_CMD_PARAM_NUM(0)|SHELL_CMD_DISABLE_RETURN, AdapterwifiTest, AdapterwifiTest, show adapter wifi information); + +int wifiopen(void) +{ + struct Adapter* adapter = AdapterDeviceFindByName(ADAPTER_WIFI_NAME); + + AdapterDeviceOpen(adapter); +} +SHELL_EXPORT_CMD(SHELL_CMD_PERMISSION(0)|SHELL_CMD_TYPE(SHELL_TYPE_CMD_FUNC)|SHELL_CMD_PARAM_NUM(0)|SHELL_CMD_DISABLE_RETURN, wifiopen, wifiopen, open adapter wifi ); +int wificlose(void) +{ + struct Adapter* adapter = AdapterDeviceFindByName(ADAPTER_WIFI_NAME); + + AdapterDeviceClose(adapter); +} +SHELL_EXPORT_CMD(SHELL_CMD_PERMISSION(0)|SHELL_CMD_TYPE(SHELL_TYPE_CMD_FUNC)|SHELL_CMD_PARAM_NUM(0)|SHELL_CMD_DISABLE_RETURN, wificlose, wificlose, close adapter wifi ); + +int wifisetup(int argc, char *argv[]) +{ + struct Adapter* adapter = AdapterDeviceFindByName(ADAPTER_WIFI_NAME); + struct WifiParam param; + memset(¶m,0,sizeof(struct WifiParam)); + strncpy(param.wifi_ssid, argv[1], strlen(argv[1])); + strncpy(param.wifi_pwd, argv[2], strlen(argv[2])); + + adapter->adapter_param = ¶m; + + AdapterDeviceSetUp(adapter); +} +SHELL_EXPORT_CMD(SHELL_CMD_PERMISSION(0)|SHELL_CMD_TYPE(SHELL_TYPE_CMD_MAIN)|SHELL_CMD_PARAM_NUM(3)|SHELL_CMD_DISABLE_RETURN, wifisetup, wifisetup, setup adapter wifi ); +int wifiaddrset(int argc, char *argv[]) +{ + struct Adapter* adapter = AdapterDeviceFindByName(ADAPTER_WIFI_NAME); + char *ip = argv[1]; + char *gateway = argv[2]; + char *netmask = argv[3]; + + AdapterDeviceSetAddr(adapter, ip, gateway, netmask); + AdapterDevicePing(adapter, "36.152.44.95");///< ping www.baidu.com + AdapterDeviceNetstat(adapter); +} +SHELL_EXPORT_CMD(SHELL_CMD_PERMISSION(0)|SHELL_CMD_TYPE(SHELL_TYPE_CMD_MAIN)|SHELL_CMD_PARAM_NUM(4)|SHELL_CMD_DISABLE_RETURN, wifiaddrset, wifiaddrset, addrset adapter wifi); + +int wifiping(int argc, char *argv[]) +{ + struct Adapter* adapter = AdapterDeviceFindByName(ADAPTER_WIFI_NAME); + printf("ping %s\n",argv[1]); + AdapterDevicePing(adapter, argv[1]); +} +SHELL_EXPORT_CMD(SHELL_CMD_PERMISSION(0)|SHELL_CMD_TYPE(SHELL_TYPE_CMD_MAIN)|SHELL_CMD_PARAM_NUM(3), wifiping, wifiping, wifiping adapter ); + +int wificonnect(int argc, char *argv[]) +{ + struct Adapter* adapter = AdapterDeviceFindByName(ADAPTER_WIFI_NAME); + char *ip = argv[1]; + char *port = argv[2]; + enum NetRoleType net_role = CLIENT; + enum IpType ip_type = IPV4; + + if(0 == strncmp("tcp",argv[3],strlen("tcp"))) { + adapter->socket.protocal = SOCKET_PROTOCOL_TCP; + } + + if(0 == strncmp("udp",argv[3],strlen("udp"))) { + adapter->socket.protocal = SOCKET_PROTOCOL_UDP; + } + + AdapterDeviceConnect(adapter, net_role, ip, port, ip_type); +} +SHELL_EXPORT_CMD(SHELL_CMD_PERMISSION(0)|SHELL_CMD_TYPE(SHELL_TYPE_CMD_MAIN)|SHELL_CMD_PARAM_NUM(4)|SHELL_CMD_DISABLE_RETURN, wificonnect, wificonnect, wificonnect adapter); +int wifisend(int argc, char *argv[]) +{ + struct Adapter* adapter = AdapterDeviceFindByName(ADAPTER_WIFI_NAME); + + const char *wifi_msg = argv[1]; + int len = strlen(wifi_msg); + for(int i = 0;i < 10; ++i) { + AdapterDeviceSend(adapter, wifi_msg, len); + PrivTaskDelay(1000); + } +} +SHELL_EXPORT_CMD(SHELL_CMD_PERMISSION(0)|SHELL_CMD_TYPE(SHELL_TYPE_CMD_MAIN)|SHELL_CMD_PARAM_NUM(3)|SHELL_CMD_DISABLE_RETURN, wifisend, wifisend, wifisend adapter wifi information); +int wifirecv(int argc, char *argv[]) +{ + struct Adapter* adapter = AdapterDeviceFindByName(ADAPTER_WIFI_NAME); + + char wifi_recv_msg[128]; + while (1) { + AdapterDeviceRecv(adapter, wifi_recv_msg, 128); + PrivTaskDelay(1000); + printf("wifi recv [%s]\n",wifi_recv_msg); + } +} +SHELL_EXPORT_CMD(SHELL_CMD_PERMISSION(0)|SHELL_CMD_TYPE(SHELL_TYPE_CMD_MAIN)|SHELL_CMD_PARAM_NUM(3)|SHELL_CMD_DISABLE_RETURN, wifirecv, wifirecv, wifirecv adapter wifi information); diff --git a/APP_Framework/Framework/connection/wifi/adapter_wifi.h b/APP_Framework/Framework/connection/wifi/adapter_wifi.h new file mode 100644 index 0000000..e0ea7a9 --- /dev/null +++ b/APP_Framework/Framework/connection/wifi/adapter_wifi.h @@ -0,0 +1,19 @@ +#ifndef ADAPTER_WIFI_H +#define ADAPTER_WIFI_H + +#define CONFIG_WIFI_RESET (0) +#define CONFIG_WIFI_RESTORE (1) +#define CONFIG_WIFI_BAUDRATE (2) + + +#define SOCKET_PROTOCOL_TCP (6) +#define SOCKET_PROTOCOL_UDP (17) + +struct WifiParam +{ + uint8_t wifi_ssid[128]; + uint8_t wifi_pwd[128]; +}; + + +#endif \ No newline at end of file diff --git a/APP_Framework/Framework/connection/wifi/esp07s_wifi/Kconfig b/APP_Framework/Framework/connection/wifi/esp07s_wifi/Kconfig new file mode 100755 index 0000000..a54223b --- /dev/null +++ b/APP_Framework/Framework/connection/wifi/esp07s_wifi/Kconfig @@ -0,0 +1,33 @@ +config ADAPTER_WIFI_ESP07S + string "ESP07S WIFI adapter name" + default "esp07s_wifi" + +if ADD_XIZI_FETURES + + config ADAPTER_ESP07S_DRIVER_EXTUART + bool "Using extra uart to support wifi" + default n + + config ADAPTER_ESP07S_DRIVER + string "ESP07S device uart driver path" + default "/dev/uart2_dev2" + depends on !ADAPTER_ESP07S_DRIVER_EXTUART + + if ADAPTER_ESP07S_DRIVER_EXTUART + config ADAPTER_ESP07S_DRIVER + string "ESP07S device extra uart driver path" + default "/dev/extuart_dev6" + + config ADAPTER_ESP07S_DRIVER_EXT_PORT + int "if ESP07S device using extuart, choose port" + default "6" + endif +endif + +if ADD_NUTTX_FETURES + +endif + +if ADD_RTTHREAD_FETURES + +endif diff --git a/APP_Framework/Framework/connection/wifi/esp07s_wifi/Makefile b/APP_Framework/Framework/connection/wifi/esp07s_wifi/Makefile new file mode 100755 index 0000000..e0ce0a8 --- /dev/null +++ b/APP_Framework/Framework/connection/wifi/esp07s_wifi/Makefile @@ -0,0 +1,3 @@ +SRC_FILES := esp07s_wifi.c + +include $(KERNEL_ROOT)/compiler.mk diff --git a/APP_Framework/Framework/connection/wifi/esp07s_wifi/esp07s_wifi.c b/APP_Framework/Framework/connection/wifi/esp07s_wifi/esp07s_wifi.c new file mode 100755 index 0000000..b634f7d --- /dev/null +++ b/APP_Framework/Framework/connection/wifi/esp07s_wifi/esp07s_wifi.c @@ -0,0 +1,587 @@ +/* +* Copyright (c) 2020 AIIT XUOS Lab +* XiUOS is licensed under Mulan PSL v2. +* You can use this software according to the terms and conditions of the Mulan PSL v2. +* You may obtain a copy of Mulan PSL v2 at: +* http://license.coscl.org.cn/MulanPSL2 +* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, +* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, +* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. +* See the Mulan PSL v2 for more details. +*/ + +/** + * @file esp07_wifi.c + * @brief Implement the connection wifi adapter function, using ESP07S device + * @version 1.1 + * @author AIIT XUOS Lab + * @date 2022.04.08 + */ + +#include +#include +#include "../adapter_wifi.h" +#include + +#define LEN_PARA_BUF 128 + +static int Esp07sWifiSetDown(struct Adapter *adapter_at); + +/** + * @description: check AT startup status + * @param at_agent - wifi device agent pointer + * @return success: EOK + */ +static int Esp07sWifiTestAtCmd(ATAgentType at_agent) +{ + int ret = 0; + + ret = AtCmdConfigAndCheck(at_agent, "ATE0\r\n", "OK"); ///< close echo function + if(ret < 0) { + printf("%s %d cmd[ATE0] config failed!\n",__func__,__LINE__); + ret = -1; + } + + PrivTaskDelay(2000); + ret = AtCmdConfigAndCheck(at_agent, "AT\r\n", "OK"); + if(ret < 0) { + printf("%s %d cmd[AT] config failed!\n",__func__,__LINE__); + ret = -1; + } + return ret; +} + +static int Esp07sUartOpen(struct Adapter *adapter) +{ + if (NULL == adapter) { + return -1; + } + + /* Open device in read-write mode */ + adapter->fd = PrivOpen(ADAPTER_ESP07S_DRIVER, O_RDWR); + if (adapter->fd < 0) { + printf("Esp07sWifiOpen get serial %s fd error\n", ADAPTER_ESP07S_DRIVER); + return -1; + } + /* set serial config, serial_baud_rate = 115200 */ + + struct SerialDataCfg cfg; + memset(&cfg, 0 ,sizeof(struct SerialDataCfg)); + + cfg.serial_baud_rate = BAUD_RATE_115200; + cfg.serial_data_bits = DATA_BITS_8; + cfg.serial_stop_bits = STOP_BITS_1; + cfg.serial_parity_mode = PARITY_NONE; + cfg.serial_bit_order = BIT_ORDER_LSB; + cfg.serial_invert_mode = NRZ_NORMAL; + cfg.serial_buffer_size = SERIAL_RB_BUFSZ; + +#ifdef ADAPTER_ESP07S_DRIVER_EXT_PORT + cfg.ext_uart_no = ADAPTER_ESP07S_DRIVER_EXT_PORT; + cfg.port_configure = PORT_CFG_INIT; +#endif + + struct PrivIoctlCfg ioctl_cfg; + ioctl_cfg.ioctl_driver_type = SERIAL_TYPE; + ioctl_cfg.args = &cfg; + + PrivIoctl(adapter->fd, OPE_INT, &ioctl_cfg); + PrivTaskDelay(1000); + + printf("esp07s uart config ready\n"); + return 0; +} + +/** + * @description: Open wifi + * @param adapter - wifi device pointer + * @return success: EOK, failure: ENOMEMORY + */ +static int Esp07sWifiOpen(struct Adapter *adapter) +{ + /*step1: open esp07s serial port*/ + Esp07sUartOpen(adapter); + + /*step2: init AT agent*/ + if (!adapter->agent) { + char *agent_name = "wifi_uart_client"; + if (EOK != InitATAgent(agent_name, adapter->fd, 512)) { + printf("at agent init failed !\n"); + return -1; + } + ATAgentType at_agent = GetATAgent(agent_name); + + adapter->agent = at_agent; + } + + AtSetReplyEndChar(adapter->agent,'O','K'); + + ADAPTER_DEBUG("Esp07sWifi open done\n"); + + return 0; +} + +/** + * @description: Close wifi + * @param adapter - wifi device pointer + * @return success: EOK + */ +static int Esp07sWifiClose(struct Adapter *adapter) +{ + Esp07sWifiSetDown(adapter); + PrivClose(adapter->fd); + return 0; +} + +/** + * @description: send data to adapter + * @param adapter - wifi device pointer + * @param data - data buffer + * @param data - data length + * @return success: EOK + */ +static int Esp07sWifiSend(struct Adapter *adapter, const void *data, size_t len) +{ + x_err_t result = EOK; + if (adapter->agent) { + EntmSend(adapter->agent, (const char *)data, len); + }else { + printf("Esp07sWifiSend can not find agent!\n"); + } + + return result; +} + +/** + * @description: receive data from adapter + * @param adapter - wifi device pointer + * @param data - data buffer + * @param data - data length + * @return success: EOK + */ +static int Esp07sWifiReceive(struct Adapter *adapter, void *rev_buffer, size_t buffer_len) +{ + x_err_t result = EOK; + printf("esp07s receive waiting ... \n"); + + if (adapter->agent) { + return EntmRecv(adapter->agent, (char *)rev_buffer, buffer_len, 40); + } else { + printf("Esp07sWifiReceive can not find agent!\n"); + } + + return result; +} + +/** + * @description: connnect wifi to internet + * @param adapter - wifi device pointer + * @return success: EOK + */ +static int Esp07sWifiSetUp(struct Adapter *adapter) +{ + char cmd[LEN_PARA_BUF]; + int ret = 0; + char *result = NULL; + + struct WifiParam *param = (struct WifiParam *)adapter->adapter_param; + struct ATAgent *agent = adapter->agent; + + PrivTaskDelay(2000); + + if(Esp07sWifiTestAtCmd(agent) < 0) + { + printf("wifi at cmd startup failed.\n"); + return -1; + } + PrivTaskDelay(2000); + /* config as softAP+station mode */ + ret = AtCmdConfigAndCheck(agent, "AT+CWMODE=3\r\n", "OK"); + if(ret < 0) { + printf("%s %d cmd[AT+CWMODE=3] config failed!\n",__func__,__LINE__); + return -1; + } + PrivTaskDelay(2000); + /* connect the router */ + memset(cmd,0,sizeof(cmd)); + strncpy(cmd,"AT+CWJAP=",strlen("AT+CWJAP=")); + strncat(cmd,"\"",1); + strncat(cmd,param->wifi_ssid,strlen(param->wifi_ssid)); + + strncat(cmd,"\"",1); + strncat(cmd,",",1); + strncat(cmd,"\"",1); + strncat(cmd,param->wifi_pwd,strlen(param->wifi_pwd)); + + strncat(cmd,"\"",1); + strcat(cmd,"\r\n"); + + ret = AtCmdConfigAndCheck(agent, cmd, "OK"); + if(ret < 0) { + printf("%s %d cmd[%s] connect[%s] failed!\n",__func__,__LINE__,cmd,param->wifi_ssid); + return -1; + } + + /* check the wifi ip address */ + ATReplyType reply = CreateATReply(256); + if (NULL == reply) { + printf("%s %d at_create_resp failed!\n",__func__,__LINE__); + return -1; + } + ret = ATOrderSend(agent, REPLY_TIME_OUT, reply, "AT+CIFSR\r\n"); + if(ret < 0){ + printf("%s %d ATOrderSend AT+CIFSR failed.\n",__func__,__LINE__); + ret = -1; + goto __exit; + } + + result = GetReplyText(reply); + if (!result) { + printf("%s %n get reply failed.\n",__func__,__LINE__); + ret = -1; + goto __exit; + } + printf("[%s]\n", result); + +__exit: + DeleteATReply(reply); + + return ret; +} + +/** + * @description: disconnnect wifi from internet + * @param adapter - wifi device pointer + * @return success: EOK + */ +static int Esp07sWifiSetDown(struct Adapter *adapter) +{ + ATOrderSend(adapter->agent, REPLY_TIME_OUT, NULL, "AT+RESTORE\r\n"); + PrivTaskDelay(2000); + + return 0; +} + +/** + * @description: set wifi ip/gateway/netmask address(in sta mode) + * @param adapter - wifi device pointer + * @param ip - ip address + * @param gateway - gateway address + * @param netmask - netmask address + * @return success: EOK, failure: ENOMEMORY + */ +static int Esp07sWifiSetAddr(struct Adapter *adapter, const char *ip, const char *gateway, const char *netmask) +{ + int ret = 0; + char cmd[LEN_PARA_BUF]; + + /* e.g. AT+CIPSTA_DEF="192.168.6.100","192.168.6.1","255.255.255.0" */ + memset(cmd,0,sizeof(cmd)); + strncpy(cmd,"AT+CIPAP_DEF=",strlen(" AT+CIPAP_DEF=")); + strncat(cmd,"\"",1); + strncat(cmd,ip,strlen(ip)); + strncat(cmd,"\"",1); + strncat(cmd,",",1); + strncat(cmd,"\"",1); + strncat(cmd,gateway,strlen(gateway)); + strncat(cmd,"\"",1); + strncat(cmd,",",1); + strncat(cmd,"\"",1); + strncat(cmd,netmask,strlen(netmask)); + strncat(cmd,"\"",1); + strcat(cmd,"\r\n"); + + ret = AtCmdConfigAndCheck(adapter->agent, cmd, "OK"); + if(ret < 0) { + printf("%s %d cmd[%s] config ip failed!\n",__func__,__LINE__,cmd); + return -1; + } + + return 0; +} + +/** + * @description: wifi ping function + * @param adapter - wifi device pointer + * @param destination - domain name or ip address + * @return success: EOK, failure: ENOMEMORY + */ +static int Esp07sWifiPing(struct Adapter *adapter, const char *destination) +{ + char cmd[LEN_PARA_BUF]; + int ret = 0; + + memset(cmd,0,sizeof(cmd)); + strncpy(cmd,"AT+PING=",strlen("AT+PING=")); + strncat(cmd,"\"",1); + strncat(cmd,destination,strlen(destination)); + strncat(cmd,"\"",1); + strcat(cmd,"\r\n"); + + ret = AtCmdConfigAndCheck(adapter->agent, cmd, "OK"); ///< config as softAP+station mode + if(ret < 0) { + printf("%s %d ping [%s] failed!\n",__func__,__LINE__,destination); + return -1; + } + + printf("ping [%s] ok\n", destination); + + return 0; +} + +/** + * @description: display wifi network configuration + * @param adapter - wifi device pointer + * @return success: EOK, failure: ENOMEMORY + */ +static int Esp07sWifiNetstat(struct Adapter *adapter) +{ + int ret = 0; + char *result = NULL; + + /* check the wifi ip address */ + ATReplyType reply = CreateATReply(256); + if (NULL == reply) { + printf("%s %d at_create_resp failed!\n",__func__,__LINE__); + return -1; + } + ret = ATOrderSend(adapter->agent, REPLY_TIME_OUT, reply, "AT+CIFSR\r\n"); + if(ret < 0){ + printf("%s %d ATOrderSend AT+CIFSR failed.\n",__func__,__LINE__); + ret = -1; + goto __exit; + } + + result = GetReplyText(reply); + if (!result) { + printf("%s %n get reply failed.\n",__func__,__LINE__); + ret = -1; + goto __exit; + } + printf("[%s]\n", result); + +__exit: + DeleteATReply(reply); + + return ret; +} + +/** + * @description: wifi connect function + * @param adapter - wifi device pointer + * @param net_role - net role, CLIENT or SERVER + * @param ip - ip address + * @param port - port num + * @param ip_type - ip type, IPV4 or IPV6 + * @return success: 0, failure: -1 + */ +static int Esp07sWifiConnect(struct Adapter *adapter, enum NetRoleType net_role, const char *ip, const char *port, enum IpType ip_type) +{ + int ret = EOK; + char cmd[LEN_PARA_BUF]; + struct ATAgent *agent = adapter->agent; + + memset(cmd,0,sizeof(cmd)); + if(adapter->socket.protocal == SOCKET_PROTOCOL_TCP && net_role == CLIENT) //esp07s as tcp client to connect server + { + //e.g. AT+CIPSTART="TCP","192.168.3.116",8080 protocol, server IP and port + strncpy(cmd,"AT+CIPSTART=",strlen("AT+CIPSTART=")); + strncat(cmd,"\"",1); + strncat(cmd,"TCP",strlen("TCP")); + strncat(cmd,"\"",1); + strncat(cmd, ",", 1); + strncat(cmd,"\"",1); + strncat(cmd, ip, strlen(ip)); + strncat(cmd, "\"", 1); + strncat(cmd, ",", 1); + strncat(cmd, port, strlen(port)); + strcat(cmd,"\r\n"); + + ret = AtCmdConfigAndCheck(agent, cmd, "OK"); + if(ret < 0) { + printf("%s %d tcp connect [%s] failed!\n",__func__,__LINE__,ip); + return -1; + } + } + else if(adapter->socket.protocal == SOCKET_PROTOCOL_UDP) + { + //e.g. AT+CIPSTART="UDP","192.168.3.116",8080,2233,0 UDP protocol, server IP, port,local port,udp mode + strncpy(cmd,"AT+CIPSTART=",strlen("AT+CIPSTART=")); + strncat(cmd,"\"",1); + strncat(cmd,"UDP",strlen("UDP")); + strncat(cmd,"\"",1); + strncat(cmd, ",", 1); + strncat(cmd,"\"",1); + strncat(cmd, ip, strlen(ip)); + strncat(cmd, "\"", 1); + strncat(cmd, ",", 1); + strncat(cmd, port, strlen(port)); + strncat(cmd, ",", 1); + strncat(cmd, "2233", strlen("2233")); ///< local port + strncat(cmd, ",", 1); + strncat(cmd, "0", 1); ///< udp transparent transmission mode must be 0 + strcat(cmd,"\r\n"); + + ret = AtCmdConfigAndCheck(agent, cmd, "OK"); + if(ret < 0) { + printf("%s %d udp connect [%s] failed!\n",__func__,__LINE__,ip); + return -1; + } + } + + ret = AtCmdConfigAndCheck(agent, "AT+CIPMODE=1\r\n", "OK"); ///< config as transparent transmission + if(ret < 0) { + printf("%s %d cmd[%s] config as transparent transmission failed!\n",__func__,__LINE__,cmd); + return -1; + } + ATOrderSend(agent, REPLY_TIME_OUT, NULL, "AT+CIPSEND\r\n"); + + printf("[%s] connection config as transparent transmission\n",adapter->socket.protocal == SOCKET_PROTOCOL_UDP ? "udp" : "tcp"); + adapter->net_role = net_role; + + return 0; +} + +/** + * @description: wifi disconnect function + * @param adapter - wifi device pointer + * @return success: 0, failure: -1 + */ +static int Esp07sWifiDisconnect(struct Adapter *adapter) +{ + int ret = EOK; + char cmd[LEN_PARA_BUF]; + struct ATAgent *agent = adapter->agent; + memset(cmd,0,sizeof(cmd)); + + /* step1: stop transparent transmission mode */ + ATOrderSend(agent, REPLY_TIME_OUT, NULL, "+++\r\n"); + + /* step2: exit transparent transmission mode */ + ret = AtCmdConfigAndCheck(agent, "AT+CIPMODE=0\r\n", "OK"); + if(ret < 0) { + printf("%s %d cmd[AT+CIPMODE=0] exit failed!\n",__func__,__LINE__); + return -1; + } + + /* step3: disconnect */ + ret = AtCmdConfigAndCheck(agent, "AT+CIPCLOSE\r\n", "OK"); + if(ret < 0) { + printf("%s %d cmd [AT+CIPCLOSE] disconnect failed!\n",__func__,__LINE__); + return -1; + } + + return 0; +} + +static int Esp07sWifiIoctl(struct Adapter *adapter, int cmd, void *args) +{ + int32_t ret = 0; + char baud_str[LEN_PARA_BUF]; + struct SerialDataCfg cfg; + char at_cmd[LEN_PARA_BUF]; + uint32_t baud_rate = 0 ; + + switch (cmd) + { + case CONFIG_WIFI_RESET: /* reset wifi */ + ATOrderSend(adapter->agent, REPLY_TIME_OUT, NULL, "AT+RST\r\n"); + break; + case CONFIG_WIFI_RESTORE: /* resore wifi */ + ATOrderSend(adapter->agent, REPLY_TIME_OUT, NULL, "AT+RESTORE\r\n"); + break; + case CONFIG_WIFI_BAUDRATE: + /* step1: config mcu uart*/ + baud_rate = *((uint32_t *)args); + + memset(at_cmd, 0, sizeof(at_cmd)); + memset(baud_str, 0, sizeof(baud_str)); + memset(&cfg, 0 ,sizeof(struct SerialDataCfg)); + + cfg.serial_baud_rate = baud_rate; + cfg.serial_data_bits = DATA_BITS_8; + cfg.serial_stop_bits = STOP_BITS_1; + cfg.serial_parity_mode = PARITY_NONE; + cfg.serial_bit_order = BIT_ORDER_LSB; + cfg.serial_invert_mode = NRZ_NORMAL; + cfg.serial_buffer_size = SERIAL_RB_BUFSZ; + +#ifdef ADAPTER_ESP07S_DRIVER_EXT_PORT + cfg.ext_uart_no = ADAPTER_ESP07S_DRIVER_EXT_PORT; + cfg.port_configure = PORT_CFG_INIT; +#endif + + struct PrivIoctlCfg ioctl_cfg; + ioctl_cfg.ioctl_driver_type = SERIAL_TYPE; + ioctl_cfg.args = &cfg; + + PrivIoctl(adapter->fd, OPE_INT, &ioctl_cfg); + + /* step2: config wifi uart*/ + itoa(baud_rate, baud_str, 10); + + strncpy(at_cmd, "AT+UART_DEF=", strlen("AT+UART_DEF=")); + strncat(at_cmd, baud_str, strlen(baud_str)); + strncat(at_cmd, ",", 1); + strncat(at_cmd, "8", 1); + strncat(at_cmd, ",", 1); + strncat(at_cmd, "1", 1); + strncat(at_cmd, ",", 1); + strncat(at_cmd, "0", 1); + strncat(at_cmd, ",", 1); + strncat(at_cmd, "3", 1); + strcat(at_cmd,"\r\n"); + + ret = AtCmdConfigAndCheck(adapter->agent, at_cmd, "OK"); + if(ret < 0) { + printf("%s %d cmd [%s] config uart failed!\n",__func__,__LINE__,at_cmd); + ret = -1; + } + + break; + default: + ret = -1; + break; + } + + return ret; +} + +static const struct IpProtocolDone esp07s_wifi_done = +{ + .open = Esp07sWifiOpen, + .close = Esp07sWifiClose, + .ioctl = Esp07sWifiIoctl, + .setup = Esp07sWifiSetUp, + .setdown = Esp07sWifiSetDown, + .setaddr = Esp07sWifiSetAddr, + .setdns = NULL, + .setdhcp = NULL, + .ping = Esp07sWifiPing, + .netstat = Esp07sWifiNetstat, + .connect = Esp07sWifiConnect, + .send = Esp07sWifiSend, + .recv = Esp07sWifiReceive, + .disconnect = Esp07sWifiDisconnect, +}; + +/** + * @description: Register wifi device esp07s + * @return success: EOK, failure: ERROR + */ +AdapterProductInfoType Esp07sWifiAttach(struct Adapter *adapter) +{ + struct AdapterProductInfo *product_info = PrivMalloc(sizeof(struct AdapterProductInfo)); + if (!product_info) + { + printf("Esp07sWifiAttach Attach malloc product_info error\n"); + PrivFree(product_info); + return NULL; + } + + strncpy(product_info->model_name, ADAPTER_WIFI_ESP07S, strlen(ADAPTER_WIFI_ESP07S)); + + product_info->model_done = (void *)&esp07s_wifi_done; + + return product_info; +} \ No newline at end of file diff --git a/APP_Framework/Framework/connection/wifi/hfa21_wifi/Kconfig b/APP_Framework/Framework/connection/wifi/hfa21_wifi/Kconfig new file mode 100755 index 0000000..b4fff97 --- /dev/null +++ b/APP_Framework/Framework/connection/wifi/hfa21_wifi/Kconfig @@ -0,0 +1,33 @@ +config ADAPTER_WIFI_HFA21 + string "HFA21 WIFI adapter name" + default "hfa21_wifi" + +if ADD_XIZI_FETURES + + config ADAPTER_HFA21_DRIVER_EXTUART + bool "Using extra uart to support wifi" + default n + + config ADAPTER_HFA21_DRIVER + string "HFA21 device uart driver path" + default "/dev/usart3_dev3" + depends on !ADAPTER_HFA21_DRIVER_EXTUART + + if ADAPTER_HFA21_DRIVER_EXTUART + config ADAPTER_HFA21_DRIVER + string "HFA21 device extra uart driver path" + default "/dev/extuart_dev6" + + config ADAPTER_HFA21_DRIVER_EXT_PORT + int "if HFA21 device using extuart, choose port" + default "6" + endif +endif + +if ADD_NUTTX_FETURES + +endif + +if ADD_RTTHREAD_FETURES + +endif diff --git a/APP_Framework/Framework/connection/wifi/hfa21_wifi/Makefile b/APP_Framework/Framework/connection/wifi/hfa21_wifi/Makefile new file mode 100755 index 0000000..5304916 --- /dev/null +++ b/APP_Framework/Framework/connection/wifi/hfa21_wifi/Makefile @@ -0,0 +1,3 @@ +SRC_FILES := hfa21_wifi.c + +include $(KERNEL_ROOT)/compiler.mk diff --git a/APP_Framework/Framework/connection/wifi/hfa21_wifi/hfa21_wifi.c b/APP_Framework/Framework/connection/wifi/hfa21_wifi/hfa21_wifi.c new file mode 100755 index 0000000..1d1ad2d --- /dev/null +++ b/APP_Framework/Framework/connection/wifi/hfa21_wifi/hfa21_wifi.c @@ -0,0 +1,524 @@ +/* +* Copyright (c) 2020 AIIT XUOS Lab +* XiUOS is licensed under Mulan PSL v2. +* You can use this software according to the terms and conditions of the Mulan PSL v2. +* You may obtain a copy of Mulan PSL v2 at: +* http://license.coscl.org.cn/MulanPSL2 +* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, +* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, +* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. +* See the Mulan PSL v2 for more details. +*/ + +/** + * @file hfa21_wifi.c + * @brief Implement the connection wifi adapter function, using HFA21 device + * @version 1.1 + * @author AIIT XUOS Lab + * @date 2021.07.08 + */ + +#include +#include + +#define LEN_PARA_BUF 128 + +static int Hfa21WifiSetDown(struct Adapter *adapter_at); + +/** + * @description: enter AT command mode + * @param at_agent - wifi device agent pointer + * @return success: EOK + */ +static int Hfa21WifiInitAtCmd(ATAgentType at_agent) +{ + ATOrderSend(at_agent, REPLY_TIME_OUT, NULL, "+++"); + PrivTaskDelay(100); + + ATOrderSend(at_agent, REPLY_TIME_OUT, NULL, "a"); + PrivTaskDelay(500); + + return 0; +} + +/** + * @description: Open wifi + * @param adapter - wifi device pointer + * @return success: EOK, failure: ENOMEMORY + */ +static int Hfa21WifiOpen(struct Adapter *adapter) +{ + /*step1: open hfa21 serial port*/ + adapter->fd = PrivOpen(ADAPTER_HFA21_DRIVER, O_RDWR); + if (adapter->fd < 0) { + printf("Hfa21WifiOpen get serial %s fd error\n", ADAPTER_HFA21_DRIVER); + return -1; + } + + /*step2: init AT agent*/ + if (!adapter->agent) { + char *agent_name = "wifi_uart_client"; + if (EOK != InitATAgent(agent_name, adapter->fd, 512)) { + printf("at agent init failed !\n"); + return -1; + } + ATAgentType at_agent = GetATAgent(agent_name); + + adapter->agent = at_agent; + } + + ADAPTER_DEBUG("Hfa21Wifi open done\n"); + + return 0; +} + +/** + * @description: Close wifi + * @param adapter - wifi device pointer + * @return success: EOK + */ +static int Hfa21WifiClose(struct Adapter *adapter) +{ + return Hfa21WifiSetDown(adapter); +} + +/** + * @description: send data to adapter + * @param adapter - wifi device pointer + * @param data - data buffer + * @param data - data length + * @return success: EOK + */ +static int Hfa21WifiSend(struct Adapter *adapter, const void *data, size_t len) +{ + x_err_t result = EOK; + if (adapter->agent) { + EntmSend(adapter->agent, (const char *)data, len); + }else { + printf("Hfa21WifiSend can not find agent!\n"); + } + +__exit: + + return result; +} + +/** + * @description: receive data from adapter + * @param adapter - wifi device pointer + * @param data - data buffer + * @param data - data length + * @return success: EOK + */ +static int Hfa21WifiReceive(struct Adapter *adapter, void *rev_buffer, size_t buffer_len) +{ + x_err_t result = EOK; + printf("hfa21 receive waiting ... \n"); + + if (adapter->agent) { + return EntmRecv(adapter->agent, (char *)rev_buffer, buffer_len, 40); + } else { + printf("Hfa21WifiReceive can not find agent!\n"); + } + +__exit: + + return result; +} + +/** + * @description: connnect wifi to internet + * @param adapter - wifi device pointer + * @return success: EOK + */ +static int Hfa21WifiSetUp(struct Adapter *adapter) +{ + uint8 wifi_ssid[LEN_PARA_BUF] = "AIIT-Guest"; + uint8 wifi_pwd[LEN_PARA_BUF] = ""; + char cmd[LEN_PARA_BUF]; + + struct ATAgent *agent = adapter->agent; + + /* wait hfa21 device startup finish */ + PrivTaskDelay(5000); + + Hfa21WifiInitAtCmd(agent); + + memset(cmd,0,sizeof(cmd)); + strcpy(cmd,"AT+FCLR\r"); + ATOrderSend(agent, REPLY_TIME_OUT, NULL, cmd); + PrivTaskDelay(20000); + + Hfa21WifiInitAtCmd(agent); + + memset(cmd,0,sizeof(cmd)); + strcpy(cmd,"AT+WSSSID="); + strcat(cmd,wifi_ssid); + strcat(cmd,"\r"); + ATOrderSend(agent, REPLY_TIME_OUT, NULL, cmd); + PrivTaskDelay(2500); + + memset(cmd,0,sizeof(cmd)); + strcpy(cmd,"AT+WSKEY=OPEN,NONE,"); + strcat(cmd,wifi_pwd); + strcat(cmd,"\r"); + ATOrderSend(agent, REPLY_TIME_OUT, NULL, cmd); + PrivTaskDelay(2500); + + memset(cmd,0,sizeof(cmd)); + strcpy(cmd,"AT+WMODE=sta\r"); + ATOrderSend(agent, REPLY_TIME_OUT, NULL, cmd); + PrivTaskDelay(2500); + + memset(cmd,0,sizeof(cmd)); + strcat(cmd,"AT+Z\r"); + ATOrderSend(agent, REPLY_TIME_OUT, NULL, cmd); + PrivTaskDelay(10000); + + return 0; +} + +/** + * @description: disconnnect wifi from internet + * @param adapter - wifi device pointer + * @return success: EOK + */ +static int Hfa21WifiSetDown(struct Adapter *adapter) +{ + Hfa21WifiInitAtCmd(adapter->agent); + + ATOrderSend(adapter->agent, REPLY_TIME_OUT, NULL, "AT+FCLR\r"); + PrivTaskDelay(20000); + + return 0; +} + +/** + * @description: set wifi ip/gateway/netmask address(in sta mode) + * @param adapter - wifi device pointer + * @param ip - ip address + * @param gateway - gateway address + * @param netmask - netmask address + * @return success: EOK, failure: ENOMEMORY + */ +static int Hfa21WifiSetAddr(struct Adapter *adapter, const char *ip, const char *gateway, const char *netmask) +{ + #define HFA21_SET_ADDR_EXPRESSION "+ok=%[^,],%[^,],%[^,],%[^,]\r" + char *dhcp_mode =NULL; + char *ip_str = NULL; + char *gw_str = NULL; + char *mask_str = NULL; + + dhcp_mode = (char *) PrivCalloc(1, 8); + ip_str = (char *) PrivCalloc(1, 17); + gw_str = (char *) PrivCalloc(1, 17); + mask_str = (char *) PrivCalloc(1, 17); + + Hfa21WifiInitAtCmd(adapter->agent); + + x_err_t result = EOK; + + ATReplyType reply = CreateATReply(64); + if (NULL == reply) { + printf("at_create_resp failed ! \n"); + result = ENOMEMORY; + goto __exit; + } + + ATOrderSend(adapter->agent, REPLY_TIME_OUT, NULL, "AT+WANN=%s,%s,%s,%s\r", "dhcp", ip, netmask, gateway); + PrivTaskDelay(2500); + + ATOrderSend(adapter->agent, REPLY_TIME_OUT, reply, "AT+WANN\r"); + PrivTaskDelay(2500); + + ATOrderSend(adapter->agent, REPLY_TIME_OUT, NULL, "AT+Z\r"); + PrivTaskDelay(10000); + + const char * result_buf = GetReplyText(reply); + + char* str = strstr(result_buf, "+ok="); + + ParseATReply(str, HFA21_SET_ADDR_EXPRESSION, dhcp_mode,ip_str,mask_str,gw_str); + printf("after configure:\n mode:%s\n ip:%s\n netmask:%s\n gateway:%s\n", dhcp_mode, ip_str, mask_str, gw_str); + +__exit: + if (reply) { + DeleteATReply(reply); + } + + return result; +} + +/** + * @description: wifi ping function + * @param adapter - wifi device pointer + * @param destination - domain name or ip address + * @return success: EOK, failure: ENOMEMORY + */ +static int Hfa21WifiPing(struct Adapter *adapter, const char *destination) +{ + char *ping_result = NONE; + char *dst = NONE; + ping_result = (char *) PrivCalloc(1, 17); + dst = (char *) PrivCalloc(1, 17); + strcpy(dst, destination); + strcat(dst, "\r"); + + Hfa21WifiInitAtCmd(adapter->agent); + + uint32 result = EOK; + + ATReplyType reply = CreateATReply(64); + if (NULL == reply) { + printf("at_create_resp failed ! \n"); + result = ENOMEMORY; + goto __exit; + } + + //ping baidu.com + ATOrderSend(adapter->agent, REPLY_TIME_OUT, reply, "AT+PING=%s", dst); + + PrivTaskDelay(2500); + + ATOrderSend(adapter->agent, REPLY_TIME_OUT, NULL, "AT+Z\r"); + PrivTaskDelay(10000); + + const char * result_buf = GetReplyText(reply); + + char* str = strstr(result_buf, "+ok="); + + ParseATReply(str, "+ok=%s\r", ping_result); + + printf("ping www.baidu.com(36.152.44.95) result is:%s\n", ping_result); + +__exit: + if (reply) { + DeleteATReply(reply); + } + + return result; +} + +/** + * @description: display wifi network configuration + * @param adapter - wifi device pointer + * @return success: EOK, failure: ENOMEMORY + */ +static int Hfa21WifiNetstat(struct Adapter *adapter) +{ + #define HFA21_NETSTAT_RESP_SIZE 320 + #define HFA21_NETSTAT_TYPE_SIZE 10 + #define HFA21_NETSTAT_IPADDR_SIZE 17 + #define HFA21_WANN_EXPRESSION "+ok=%[^,],%[^,],%[^,],%[^,]\r" + #define HFA21_LANN_EXPRESSION "+ok=%[^,],%[^,]\r" + #define HFA21_WMODE_EXPRESSION "+ok=%s\r" + + ATReplyType reply = NULL; + struct ATAgent *agent = adapter->agent; + uint32 result; + char * result_buf = NULL; + char * str = NULL; + + /* sta/ap */ + char *work_mode = NULL; + /* dhcp/static */ + char *ip_mode = NULL; + char *local_ipaddr = NULL; + char *gateway = NULL; + char *netmask = NULL; + local_ipaddr = (char *) PrivCalloc(1, HFA21_NETSTAT_IPADDR_SIZE); + gateway = (char *) PrivCalloc(1, HFA21_NETSTAT_IPADDR_SIZE); + netmask = (char *) PrivCalloc(1, HFA21_NETSTAT_IPADDR_SIZE); + work_mode = (char *) PrivCalloc(1, HFA21_NETSTAT_IPADDR_SIZE); + ip_mode = (char *) PrivCalloc(1, HFA21_NETSTAT_IPADDR_SIZE); + + reply = CreateATReply(HFA21_NETSTAT_RESP_SIZE); + if (reply == NULL) { + result = ENOMEMORY; + goto __exit; + } + + ATOrderSend(agent, REPLY_TIME_OUT, NULL, "+++"); + PrivTaskDelay(100); + + ATOrderSend(agent, REPLY_TIME_OUT, NULL, "a"); + PrivTaskDelay(2500); + + ATOrderSend(agent, REPLY_TIME_OUT, reply, "AT+WMODE\r"); + PrivTaskDelay(2500); + + result_buf = GetReplyText(reply); + + str = strstr(result_buf, "+ok="); + /* parse the third line of response data, get the network connection information */ + ParseATReply(str, HFA21_WMODE_EXPRESSION, work_mode); + + if (work_mode[0]=='S') { + if (ATOrderSend(agent, REPLY_TIME_OUT, reply, "AT+WANN\r") < 0) { + goto __exit; + } + + PrivTaskDelay(2500); + + GetReplyText(reply); + str = strstr(result_buf, "+ok="); + /* parse the third line of response data, get the network connection information */ + ParseATReply(str, HFA21_WANN_EXPRESSION, ip_mode, local_ipaddr, netmask, gateway); + } else { + ATOrderSend(agent, REPLY_TIME_OUT, reply, "AT+LANN\r"); + PrivTaskDelay(2500); + + GetReplyText(reply); + + str = strstr(result_buf, "+ok="); + /* parse the third line of response data, get the network connection information */ + ParseATReply(str, HFA21_LANN_EXPRESSION, local_ipaddr, netmask); + } + + ATOrderSend(adapter->agent, REPLY_TIME_OUT, NULL, "AT+Z\r"); + PrivTaskDelay(10000); + + printf("work mode: %s\n", work_mode); + if (work_mode[0]=='S') + printf("ip mode: %s\nlocal ip: %s\nnetmask: %s\ngateway: %s\n", ip_mode, local_ipaddr, netmask, gateway); + else + printf("local ip: %s\nnetmask: %s\n", local_ipaddr, netmask); + + return EOK; + +__exit: + if (reply) + DeleteATReply(reply); + if (local_ipaddr) + PrivFree(local_ipaddr); + if (netmask) + PrivFree(netmask); + if (gateway) + PrivFree(gateway); + if (work_mode) + PrivFree(work_mode); +} + +/** + * @description: wifi connect function + * @param adapter - wifi device pointer + * @param net_role - net role, CLIENT or SERVER + * @param ip - ip address + * @param port - port num + * @param ip_type - ip type, IPV4 or IPV6 + * @return success: 0, failure: -1 + */ +static int Hfa21WifiConnect(struct Adapter *adapter, enum NetRoleType net_role, const char *ip, const char *port, enum IpType ip_type) +{ + int result = EOK; + ATReplyType reply = NONE; + char cmd[LEN_PARA_BUF]; + struct ATAgent *agent = adapter->agent; + + reply = CreateATReply(64); + if (reply == NONE) { + printf("no memory for reply struct."); + return ENOMEMORY; + } + + Hfa21WifiInitAtCmd(adapter->agent); + + memset(cmd,0,sizeof(cmd)); + strcpy(cmd,"AT+NETP=TCP,"); + if(net_role == CLIENT) + strcat(cmd,"CLIENT,"); + else if(net_role == SERVER) + strcat(cmd,"SERVER,"); + strcat(cmd,port); + strcat(cmd,","); + if(ip_type == IPV4) + strcat(cmd,ip); + else if(ip_type == IPV6) + { + + } + strcat(cmd,"\r"); + ATOrderSend(agent, REPLY_TIME_OUT, NULL, cmd); + PrivTaskDelay(2500); + + ATOrderSend(adapter->agent, REPLY_TIME_OUT, NULL, "AT+Z\r"); + PrivTaskDelay(10000); + + adapter->net_role = net_role; + +__exit: + if (reply) { + DeleteATReply(reply); + } + + return result; +} + +static int Hfa21WifiIoctl(struct Adapter *adapter, int cmd, void *args) +{ + if (OPE_INT != cmd) { + printf("Hfa21WifiIoctl only support OPE_INT, do not support %d\n", cmd); + return -1; + } + + uint32_t baud_rate = *((uint32_t *)args); + + struct SerialDataCfg serial_cfg; + memset(&serial_cfg, 0 ,sizeof(struct SerialDataCfg)); + serial_cfg.serial_baud_rate = baud_rate; + serial_cfg.serial_data_bits = DATA_BITS_8; + serial_cfg.serial_stop_bits = STOP_BITS_1; + serial_cfg.serial_buffer_size = SERIAL_RB_BUFSZ; + serial_cfg.serial_parity_mode = PARITY_NONE; + serial_cfg.serial_bit_order = BIT_ORDER_LSB; + serial_cfg.serial_invert_mode = NRZ_NORMAL; +#ifdef ADAPTER_HFA21_DRIVER_EXT_PORT + serial_cfg.ext_uart_no = ADAPTER_HFA21_DRIVER_EXT_PORT; + serial_cfg.port_configure = PORT_CFG_INIT; +#endif + + struct PrivIoctlCfg ioctl_cfg; + ioctl_cfg.ioctl_driver_type = SERIAL_TYPE; + ioctl_cfg.args = &serial_cfg; + PrivIoctl(adapter->fd, OPE_INT, &ioctl_cfg); + printf("Hfa21WifiIoctl success\n"); + return 0; +} + +static const struct IpProtocolDone hfa21_wifi_done = +{ + .open = Hfa21WifiOpen, + .close = Hfa21WifiClose, + .ioctl = Hfa21WifiIoctl, + .setup = Hfa21WifiSetUp, + .setdown = Hfa21WifiSetDown, + .setaddr = Hfa21WifiSetAddr, + .setdns = NULL, + .setdhcp = NULL, + .ping = Hfa21WifiPing, + .netstat = Hfa21WifiNetstat, + .connect = Hfa21WifiConnect, + .send = Hfa21WifiSend, + .recv = Hfa21WifiReceive, + .disconnect = NULL, +}; + +/** + * @description: Register wifi device hfa21 + * @return success: EOK, failure: ERROR + */ +AdapterProductInfoType Hfa21WifiAttach(struct Adapter *adapter) +{ + struct AdapterProductInfo *product_info = PrivMalloc(sizeof(struct AdapterProductInfo)); + if (!product_info) { + printf("Hfa21WifiAttach Attach malloc product_info error\n"); + PrivFree(product_info); + return NULL; + } + + strcpy(product_info->model_name, ADAPTER_WIFI_HFA21); + + product_info->model_done = (void *)&hfa21_wifi_done; + + return product_info; +} \ No newline at end of file diff --git a/APP_Framework/Framework/connection/zigbee/Kconfig b/APP_Framework/Framework/connection/zigbee/Kconfig new file mode 100644 index 0000000..4261900 --- /dev/null +++ b/APP_Framework/Framework/connection/zigbee/Kconfig @@ -0,0 +1,10 @@ +if CONNECTION_ADAPTER_ZIGBEE + config ADAPTER_E18 + bool "Using zigbee adapter device E18" + default y + + if ADAPTER_E18 + source "$APP_DIR/Framework/connection/zigbee/e18/Kconfig" + endif + +endif diff --git a/APP_Framework/Framework/connection/zigbee/Make.defs b/APP_Framework/Framework/connection/zigbee/Make.defs new file mode 100644 index 0000000..b4c1b03 --- /dev/null +++ b/APP_Framework/Framework/connection/zigbee/Make.defs @@ -0,0 +1,7 @@ +############################################################################ +# APP_Framework/Framework/connection/zigbee/Make.defs +############################################################################ +ifneq ($(CONFIG_CONNECTION_ADAPTER_ZIGBEE),) +CONFIGURED_APPS += $(APPDIR)/../../../APP_Framework/Framework/connection/zigbee +endif +include $(wildcard $(APPDIR)/../../../APP_Framework/Framework/connection/zigbee/*/Make.defs) diff --git a/APP_Framework/Framework/connection/zigbee/Makefile b/APP_Framework/Framework/connection/zigbee/Makefile new file mode 100644 index 0000000..cfd9f20 --- /dev/null +++ b/APP_Framework/Framework/connection/zigbee/Makefile @@ -0,0 +1,18 @@ +include $(KERNEL_ROOT)/.config +ifeq ($(CONFIG_ADD_NUTTX_FETURES),y) + include $(APPDIR)/Make.defs + CSRCS += adapter_zigbee.c + include $(APPDIR)/Application.mk + +endif + +ifeq ($(CONFIG_ADD_XIZI_FETURES),y) + SRC_FILES := adapter_zigbee.c + + ifeq ($(CONFIG_ADAPTER_E18),y) + SRC_DIR += e18 + endif + + include $(KERNEL_ROOT)/compiler.mk + +endif diff --git a/APP_Framework/Framework/connection/zigbee/adapter_zigbee.c b/APP_Framework/Framework/connection/zigbee/adapter_zigbee.c new file mode 100644 index 0000000..e3577cf --- /dev/null +++ b/APP_Framework/Framework/connection/zigbee/adapter_zigbee.c @@ -0,0 +1,162 @@ +/* +* Copyright (c) 2020 AIIT XUOS Lab +* XiUOS is licensed under Mulan PSL v2. +* You can use this software according to the terms and conditions of the Mulan PSL v2. +* You may obtain a copy of Mulan PSL v2 at: +* http://license.coscl.org.cn/MulanPSL2 +* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, +* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, +* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. +* See the Mulan PSL v2 for more details. +*/ + +/** + * @file adapter_zigbee.c + * @brief Implement the connection zigbee adapter function + * @version 1.1 + * @author AIIT XUOS Lab + * @date 2021.09.15 + */ + +#include +#include "adapter_zigbee.h" + + +#ifdef ADAPTER_E18 +extern AdapterProductInfoType E18Attach(struct Adapter *adapter); +#endif + +static int AdapterZigbeeRegister(struct Adapter *adapter) +{ + int ret = 0; + + strncpy(adapter->name, ADAPTER_ZIGBEE_NAME, NAME_NUM_MAX); + + /* config adapter net protocol as network mode */ + adapter->net_protocol = PRIVATE_PROTOCOL; + + /* config adapter net role as coordinator/router/end_device */ +#ifdef AS_COORDINATOR_ROLE + adapter->net_role = COORDINATOR; +#endif +#ifdef AS_ROUTER_ROLE + adapter->net_role = ROUTER; +#endif +#ifdef AS_END_DEVICE_ROLE + adapter->net_role = END_DEVICE; +#endif + + adapter->adapter_status = UNREGISTERED; + + ret = AdapterDeviceRegister(adapter); + if (ret < 0) { + printf("AdapterZigbee register error\n"); + return -1; + } + + return ret; +} + +int AdapterZigbeeInit(void) +{ + int ret = 0; + + struct Adapter *adapter = malloc(sizeof(struct Adapter)); + if (!adapter) { + printf("malloc adapter failed.\n"); + return -1; + } + memset(adapter, 0, sizeof(struct Adapter)); + ret = AdapterZigbeeRegister(adapter); + if (ret < 0) { + printf("AdapterZigbeeRegister register zigbee adapter error\n"); + PrivFree(adapter); + return -1; + } +#ifdef ADAPTER_E18 + AdapterProductInfoType product_info = E18Attach(adapter); + if (!product_info) { + printf("AdapterZigbeeRegister e18 attach error\n"); + PrivFree(adapter); + return -1; + } + + adapter->product_info_flag = 1; + adapter->info = product_info; + adapter->done = product_info->model_done; +#endif + + return ret; +} + +/******************TEST*********************/ +int openzigbee(void) +{ + int ret = 0; + + struct Adapter* adapter = AdapterDeviceFindByName(ADAPTER_ZIGBEE_NAME); + +#ifdef ADAPTER_E18 + ret = AdapterDeviceOpen(adapter); + if(ret < 0){ + printf("open adapter failed\n"); + return -1; + } + + adapter->info->work_mode = 1; + ret = AdapterDeviceControl(adapter, CONFIG_ZIGBEE_NET_MODE,NULL); + if(ret < 0){ + printf("control adapter failed\n"); + return -1; + } + ret = AdapterDeviceJoin(adapter, NULL); + if(ret < 0){ + printf("join adapter failed\n"); + return -1; + } +#endif + + return 0; +} + +#ifdef ADD_XIZI_FETURES +SHELL_EXPORT_CMD(SHELL_CMD_PERMISSION(0)|SHELL_CMD_TYPE(SHELL_TYPE_CMD_FUNC)|SHELL_CMD_PARAM_NUM(0)|SHELL_CMD_DISABLE_RETURN, openzigbee, openzigbee, show adapter zigbee information); +#endif + +int sendzigbee(int argc, char *argv[]) +{ + const char *send_msg = argv[1]; + int ret = 0; + + struct Adapter* adapter = AdapterDeviceFindByName(ADAPTER_ZIGBEE_NAME); + + printf("send argv1 %s\n",argv[1]); + ret = AdapterDeviceSend(adapter, send_msg, strlen(send_msg)); + if(ret < 0){ + printf(" adapter send failed\n"); + return -1; + } + printf("zigbee send msg %s\n", send_msg); + + + return 0; +} +#ifdef ADD_XIZI_FETURES +SHELL_EXPORT_CMD(SHELL_CMD_PERMISSION(0)|SHELL_CMD_TYPE(SHELL_TYPE_CMD_MAIN)|SHELL_CMD_PARAM_NUM(2)|SHELL_CMD_DISABLE_RETURN, sendzigbee, sendzigbee, show adapter zigbee information); +#endif + +int recvzigbee(void) +{ + char recv_msg[128]; + struct Adapter* adapter = AdapterDeviceFindByName(ADAPTER_ZIGBEE_NAME); + memset(recv_msg,0,128); + AdapterDeviceRecv(adapter, recv_msg, 128); + PrivTaskDelay(2000); + printf("zigbee recv msg %s\n", recv_msg); + + return 0; +} +#ifdef ADD_XIZI_FETURES +SHELL_EXPORT_CMD(SHELL_CMD_PERMISSION(0)|SHELL_CMD_TYPE(SHELL_TYPE_CMD_FUNC)|SHELL_CMD_PARAM_NUM(0)|SHELL_CMD_DISABLE_RETURN, recvzigbee, recvzigbee, show adapter zigbee information); +#endif + diff --git a/APP_Framework/Framework/connection/zigbee/adapter_zigbee.h b/APP_Framework/Framework/connection/zigbee/adapter_zigbee.h new file mode 100644 index 0000000..3e9200b --- /dev/null +++ b/APP_Framework/Framework/connection/zigbee/adapter_zigbee.h @@ -0,0 +1,9 @@ +#ifndef ADAPTER_ZIGBEE_H +#define ADAPTER_ZIGBEE_H + +#define CONFIG_ZIGBEE_NET_ROLE (1) +#define CONFIG_ZIGBEE_NET_MODE (2) + + + +#endif \ No newline at end of file diff --git a/APP_Framework/Framework/connection/zigbee/e18/Kconfig b/APP_Framework/Framework/connection/zigbee/e18/Kconfig new file mode 100644 index 0000000..643d07a --- /dev/null +++ b/APP_Framework/Framework/connection/zigbee/e18/Kconfig @@ -0,0 +1,59 @@ +config ADAPTER_ZIGBEE_E18 + string "E18 adapter name" + default "e18" + +choice + prompt "E18 adapter select net role type " + default AS_END_DEVICE_ROLE + + config AS_COORDINATOR_ROLE + bool "config as a coordinator" + + config AS_ROUTER_ROLE + bool "config as a router" + + config AS_END_DEVICE_ROLE + bool "config as an end device" +endchoice + + +if ADD_XIZI_FETURES + config ADAPTER_E18_MODEPIN + int "E18 MODE pin number" + default "61" + + config ADAPTER_BC28_PIN_DRIVER + string "BC28 device pin driver path" + default "/dev/pin_dev" + + config ADAPTER_E18_DRIVER_EXTUART + bool "Using extra uart to support zigbee" + default n + + config ADAPTER_E18_DRIVER + string "E18 device uart driver path" + default "/dev/uart2_dev2" + depends on !ADAPTER_E18_DRIVER_EXTUART + + if ADAPTER_E18_DRIVER_EXTUART + config ADAPTER_E18_DRIVER + string "E18 device extra uart driver path" + default "/dev/extuart_dev0" + + config ADAPTER_E18_DRIVER_EXT_PORT + int "if E18 device using extuart, choose port" + default "0" + endif +endif + +if ADD_NUTTX_FETURES + config ADAPTER_E18_DRIVER + string "E18 device uart driver path" + default "/dev/ttyS1" + ---help--- + If USART1 is selected, then fill in /dev/ttyS1 here. +endif + +if ADD_RTTHREAD_FETURES + +endif diff --git a/APP_Framework/Framework/connection/zigbee/e18/Make.defs b/APP_Framework/Framework/connection/zigbee/e18/Make.defs new file mode 100644 index 0000000..3097f8d --- /dev/null +++ b/APP_Framework/Framework/connection/zigbee/e18/Make.defs @@ -0,0 +1,6 @@ +############################################################################ +# APP_Framework/Framework/connection/zigbee/e18/Make.defs +############################################################################ +ifneq ($(CONFIG_ADAPTER_ZIGBEE_E18),) +CONFIGURED_APPS += $(APPDIR)/../../../APP_Framework/Framework/connection/zigbee/e18 +endif diff --git a/APP_Framework/Framework/connection/zigbee/e18/Makefile b/APP_Framework/Framework/connection/zigbee/e18/Makefile new file mode 100644 index 0000000..1ac35b4 --- /dev/null +++ b/APP_Framework/Framework/connection/zigbee/e18/Makefile @@ -0,0 +1,13 @@ +include $(KERNEL_ROOT)/.config +ifeq ($(CONFIG_ADD_NUTTX_FETURES),y) + include $(APPDIR)/Make.defs + CSRCS += e18.c + include $(APPDIR)/Application.mk + +endif + +ifeq ($(CONFIG_ADD_XIZI_FETURES),y) + SRC_FILES := e18.c + + include $(KERNEL_ROOT)/compiler.mk +endif \ No newline at end of file diff --git a/APP_Framework/Framework/connection/zigbee/e18/e18.c b/APP_Framework/Framework/connection/zigbee/e18/e18.c new file mode 100644 index 0000000..bd8d5ef --- /dev/null +++ b/APP_Framework/Framework/connection/zigbee/e18/e18.c @@ -0,0 +1,492 @@ +/* +* Copyright (c) 2020 AIIT XUOS Lab +* XiUOS is licensed under Mulan PSL v2. +* You can use this software according to the terms and conditions of the Mulan PSL v2. +* You may obtain a copy of Mulan PSL v2 at: +* http://license.coscl.org.cn/MulanPSL2 +* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, +* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, +* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. +* See the Mulan PSL v2 for more details. +*/ + +/** + * @file e18.c + * @brief Implement the connection zigbee adapter function, using E18 device + * @version 1.1 + * @author AIIT XUOS Lab + * @date 2021.09.15 + */ + +#include +#include +#include "../adapter_zigbee.h" +#include "e18.h" + +char *cmd_hex2at = "+++"; +char *cmd_exit = "AT+EXIT"; +char *cmd_ask_panid = "AT+PANID=?"; +char *cmd_set_panid = "AT+PANID=A1B2"; +char *cmd_ask_mode = "AT+MODE=?"; +char *cmd_mode_as_tt = "AT+MODE=1"; /*mode 1:transparent transmission*/ +char *cmd_mode_as_stt = "AT+MODE=2"; /*mode 2:Semi transparent transmission*/ +char *cmd_mode_as_protocol = "AT+MODE=3"; /*mode 3:Protocol mode*/ +char *cmd_ask_role = "AT+DEV=?"; +char *cmd_role_as_c = "AT+DEV=C"; /*set device type for coordinater*/ +char *cmd_role_as_e = "AT+DEV=E"; /*set device type for end device*/ +char *cmd_role_as_r = "AT+DEV=R"; /*set device type for router*/ +char *cmd_set_ch = "AT+CH=11"; /*set channel as 11*/ + +#define E18_AS_HEX_MODE 0 +#define E18_AS_AT_MODE 1 + +static int E18HardwareModeGet() +{ + int ret = 0; + int pin_fd; + + pin_fd = PrivOpen(ADAPTER_BC28_PIN_DRIVER, O_RDWR); + + struct PinStat pin_stat; + pin_stat.pin = ADAPTER_E18_MODEPIN; + + ret = PrivRead(pin_fd, &pin_stat, 1); + + PrivTaskDelay(200); + + PrivClose(pin_fd); + + if(pin_stat.val == GPIO_HIGH) { + printf(" E18 as AT mode\n"); + return E18_AS_AT_MODE; + } else { + printf(" E18 as HEX mode\n"); + return E18_AS_HEX_MODE; + } +} + +#ifdef ADD_NUTTX_FETURES +static int E18UartOpen(struct Adapter *adapter) +{ + adapter->fd = PrivOpen(ADAPTER_E18_DRIVER, O_RDWR); + if (adapter->fd < 0) { + printf("E18UartSetUp get serial %s fd error\n", ADAPTER_E18_DRIVER); + return -1; + } + + return adapter->fd; +} +#else +static int E18UartOpen(struct Adapter *adapter) +{ + if (NULL == adapter) { + return -1; + } + + /* Open device in read-write mode */ + adapter->fd = PrivOpen(ADAPTER_E18_DRIVER,O_RDWR); + if (adapter->fd < 0) { + printf("E18UartSetUp get serial %s fd error\n", ADAPTER_E18_DRIVER); + return -1; + } + /* set serial config, serial_baud_rate = 115200 */ + + struct SerialDataCfg cfg; + memset(&cfg, 0 ,sizeof(struct SerialDataCfg)); + + cfg.serial_baud_rate = BAUD_RATE_115200; + cfg.serial_data_bits = DATA_BITS_8; + cfg.serial_stop_bits = STOP_BITS_1; + cfg.serial_parity_mode = PARITY_NONE; + cfg.serial_bit_order = BIT_ORDER_LSB; + cfg.serial_invert_mode = NRZ_NORMAL; + cfg.serial_buffer_size = SERIAL_RB_BUFSZ; + + /*aiit board use ch438, so it needs more serial configuration*/ +#ifdef ADAPTER_E18_DRIVER_EXTUART + cfg.ext_uart_no = ADAPTER_E18_DRIVER_EXT_PORT; + cfg.port_configure = PORT_CFG_INIT; +#endif + + struct PrivIoctlCfg ioctl_cfg; + ioctl_cfg.ioctl_driver_type = SERIAL_TYPE; + ioctl_cfg.args = &cfg; + + PrivIoctl(adapter->fd, OPE_INT, &ioctl_cfg); + PrivTaskDelay(1000); + + printf("Zigbee uart config ready\n"); + return 0; +} +#endif + +static int E18NetworkModeConfig(struct Adapter *adapter) +{ + int ret = 0; + int mode = -1; + + if (NULL == adapter) { + return -1; + } + mode = E18HardwareModeGet(); + if(E18_AS_HEX_MODE == mode) + { + ret = AtCmdConfigAndCheck(adapter->agent, cmd_hex2at, "+OK"); + if(ret < 0) { + printf("%s %d cmd[%s] config failed!\n",__func__,__LINE__,cmd_hex2at); + ret = -1; + goto out; + } + } + + + switch (adapter->info->work_mode) + { + case TT_MODE1: + ret = AtCmdConfigAndCheck(adapter->agent, cmd_mode_as_tt, "+OK"); + ret |= AtCmdConfigAndCheck(adapter->agent, cmd_ask_mode, "MODE=1"); + if(ret < 0) { + printf("%s %d config net mode as transparent transmission failed!\n",__func__,__LINE__); + ret = -1; + goto out; + } + break; + case STT_MODE2: + ret = AtCmdConfigAndCheck(adapter->agent, cmd_mode_as_stt, "+OK"); + ret |= AtCmdConfigAndCheck(adapter->agent, cmd_ask_mode, "MODE=2"); + if(ret < 0) { + printf("%s %d config net mode as semi transparent transmission failed!\n",__func__,__LINE__); + ret = -1; + goto out; + } + break; + case PROTOCOL_MODE3: + ret = AtCmdConfigAndCheck(adapter->agent, cmd_mode_as_protocol, "+OK"); + ret |= AtCmdConfigAndCheck(adapter->agent, cmd_ask_mode, "MODE=3"); + if(ret < 0) { + printf("%s %d config net mode as protocol failed!\n",__func__,__LINE__); + ret = -1; + goto out; + } + break; + default : + ret = -1; + break; + } + +out: + if(E18_AS_HEX_MODE == mode){ + AtCmdConfigAndCheck(adapter->agent, cmd_exit, "+OK"); + } + + return ret; +} + +static int E18NetRoleConfig(struct Adapter *adapter) +{ + int ret = 0; + int mode = -1; + + + if (NULL == adapter) { + printf("%s %d adapter is null!\n",__func__,__LINE__); + ret = -1; + goto out; + } + mode = E18HardwareModeGet(); + if(E18_AS_HEX_MODE == mode) + { + ret = AtCmdConfigAndCheck(adapter->agent, cmd_hex2at, "+OK"); + if(ret < 0) { + printf("%s %d cmd[%s] config failed!\n",__func__,__LINE__,cmd_hex2at); + ret = -1; + goto out; + } + } + + + switch (adapter->net_role) + { + case COORDINATOR: + ret = AtCmdConfigAndCheck(adapter->agent, cmd_role_as_c, "+OK"); + ret |= AtCmdConfigAndCheck(adapter->agent, cmd_ask_role, "DEV=C"); + if(ret < 0) { + printf("%s %d config net role as coordinator failed!\n",__func__,__LINE__); + ret = -1; + goto out; + } + break; + case ROUTER: + ret = AtCmdConfigAndCheck(adapter->agent, cmd_role_as_r, "+OK"); + ret |= AtCmdConfigAndCheck(adapter->agent, cmd_role_as_r, "DEV=R"); + if(ret < 0) { + printf("%s %d config net role as router failed!\n",__func__,__LINE__); + ret = -1; + goto out; + } + break; + case END_DEVICE: + ret = AtCmdConfigAndCheck(adapter->agent, cmd_role_as_e, "+OK"); + ret |= AtCmdConfigAndCheck(adapter->agent, cmd_ask_role, "DEV=E"); + if(ret < 0) { + printf("%s %d config net role as device failed!\n",__func__,__LINE__); + ret = -1; + goto out; + } + break; + default : + ret = -1; + break; + } + +out: + if(E18_AS_HEX_MODE == mode) { + AtCmdConfigAndCheck(adapter->agent, cmd_exit, "+OK"); + } + + return ret; +} + +static int E18Open(struct Adapter *adapter) +{ + int ret = 0; + int try_times = 5; + int count = 0; + + if (NULL == adapter) { + return -1; + } + /*step1: open e18 serial port*/ + ret = E18UartOpen(adapter); + if (ret < 0) { + printf("e18 setup failed.\n"); + return -1; + } + /*step2: init AT agent*/ + if (!adapter->agent) { + char *agent_name = "zigbee_device"; + if (0 != InitATAgent(agent_name, adapter->fd, 512)) { + printf("at agent init failed !\n"); + return -1; + } + ATAgentType at_agent = GetATAgent(agent_name); + adapter->agent = at_agent; + } + + AtSetReplyLrEnd(adapter->agent, 1); + +try_again: + while(try_times--){ + ret = E18NetRoleConfig(adapter); + count++; + if(ret < 0){ + printf("E18NetRoleConfig failed [%d] times.\n",count); + continue; + } else { + break; + } + } + + if(ret < 0){ + printf("E18NetRoleConfig failed\n"); + return -1; + } + + printf("Zigbee E18 open successful\n"); + return 0; +} + +static int E18Close(struct Adapter *adapter) +{ + PrivClose(adapter->fd); + return 0; +} + +static int E18Ioctl(struct Adapter *adapter, int cmd, void *args) +{ + int ret = 0; + switch (cmd) + { + case CONFIG_ZIGBEE_NET_ROLE: /* config E18 net role */ + ret = E18NetRoleConfig(adapter); + break; + case CONFIG_ZIGBEE_NET_MODE: /* config E18 network mode */ + ret = E18NetworkModeConfig(adapter); + break; + default: + ret = -1; + break; + } + + return ret; +} + +static int E18Join(struct Adapter *adapter, unsigned char *priv_net_group) +{ + int ret = 0; + int mode = -1; + + mode = E18HardwareModeGet(); + if(E18_AS_HEX_MODE == mode) + { + ret = AtCmdConfigAndCheck(adapter->agent, cmd_hex2at, "+OK"); + if(ret < 0) { + printf("%s %d cmd[%s] config failed!\n",__func__,__LINE__,cmd_hex2at); + ret = -1; + goto out; + } + } + + switch (adapter->net_role) + { + case COORDINATOR: + case ROUTER: + case END_DEVICE: + /* config panid */ + ret = AtCmdConfigAndCheck(adapter->agent, cmd_set_panid, "+OK"); + ret |= AtCmdConfigAndCheck(adapter->agent, cmd_ask_panid, "PANID=A1B2"); + if(ret < 0) { + printf("%s %d cmd[%s] config failed!\n",__func__,__LINE__,cmd_set_panid); + ret = -1; + goto out; + } + + /* config channel*/ + ret = AtCmdConfigAndCheck(adapter->agent, cmd_set_ch, "+OK"); + if(ret < 0) { + printf("%s %d cmd[%s] config failed!\n",__func__,__LINE__,cmd_set_ch); + ret = -1; + goto out; + } + break; + default : + ret = -1; + break; + } + + // switch (adapter->info->work_mode) + // { + // case TT_MODE1: + // break; + // case STT_MODE2: + // /* need to do */ + // ret = 0; + // break; + // case PROTOCOL_MODE3: + // /* need to do */ + // ret = 0; + // break; + // default: + // ret = -1; + // break; + + // } + if(!ret){ + if(E18_AS_HEX_MODE == mode) { + ret = AtCmdConfigAndCheck(adapter->agent, cmd_exit, "+OK"); + if(ret < 0) { + printf("%s %d cmd[%s] config failed!\n",__func__,__LINE__,cmd_exit); + ret = -1; + } + } else { + ret = -1; + } + } + +out: + return ret; +} + +static int E18Send(struct Adapter *adapter, const void *buf, size_t len) +{ + int ret = 0; + switch (adapter->info->work_mode) + { + case TT_MODE1: + EntmSend(adapter->agent, buf, len); + break; + case STT_MODE2: + /* need to do */ + ret = 0; + break; + case PROTOCOL_MODE3: + /* need to do */ + ret = 0; + break; + default: + ret = -1; + break; + + } + return 0; +} + +static int E18Recv(struct Adapter *adapter, void *buf, size_t len) +{ + int ret = 0; + switch (adapter->info->work_mode) + { + case TT_MODE1: + if(!adapter->agent){ + PrivRead(adapter->fd, buf, len); + } else { + EntmRecv(adapter->agent, buf, len, 3);/* wait timeout 3000ms*/ + } + break; + case STT_MODE2: + /* need to do */ + ret = 0; + break; + case PROTOCOL_MODE3: + /* need to do */ + ret = 0; + break; + default: + ret = -1; + break; + } + + return 0; +} + +static int E18Quit(struct Adapter *adapter) +{ + + return 0; +} + +static const struct PrivProtocolDone E18_done = +{ + .open = E18Open, + .close = E18Close, + .ioctl = E18Ioctl, + .setup = NULL, + .setdown = NULL, + .setaddr = NULL, + .setdns = NULL, + .setdhcp = NULL, + .ping = NULL, + .netstat = NULL, + .join = E18Join, + .send = E18Send, + .recv = E18Recv, + .quit = E18Quit, +}; + +AdapterProductInfoType E18Attach(struct Adapter *adapter) +{ + struct AdapterProductInfo *product_info = malloc(sizeof(struct AdapterProductInfo)); + if (!product_info) { + printf("E18Attach malloc product_info error\n"); + return NULL; + } + memset(product_info, 0, sizeof(struct AdapterProductInfo)); + + strncpy(product_info->model_name, ADAPTER_ZIGBEE_E18,sizeof(product_info->model_name)); + product_info->model_done = (void *)&E18_done; + + return product_info; +} + + + diff --git a/APP_Framework/Framework/connection/zigbee/e18/e18.h b/APP_Framework/Framework/connection/zigbee/e18/e18.h new file mode 100644 index 0000000..b6047a1 --- /dev/null +++ b/APP_Framework/Framework/connection/zigbee/e18/e18.h @@ -0,0 +1,12 @@ +#ifndef E18_H +#define E18_H + +enum ZigbeeE18WorkModeType +{ + TT_MODE1 = 1, + STT_MODE2, + PROTOCOL_MODE3, + MODE_NONE, +}; + +#endif \ No newline at end of file diff --git a/APP_Framework/Framework/control/Kconfig b/APP_Framework/Framework/control/Kconfig new file mode 100755 index 0000000..9a4f5e4 --- /dev/null +++ b/APP_Framework/Framework/control/Kconfig @@ -0,0 +1,8 @@ +menuconfig SUPPORT_CONTROL_FRAMEWORK + bool "support control framework" + default n + select TRANSFORM_LAYER_ATTRIUBUTE + +if SUPPORT_CONTROL_FRAMEWORK + source "$APP_DIR/Framework/control/plc/interoperability/Kconfig" +endif diff --git a/APP_Framework/Framework/control/Makefile b/APP_Framework/Framework/control/Makefile new file mode 100755 index 0000000..3b00b03 --- /dev/null +++ b/APP_Framework/Framework/control/Makefile @@ -0,0 +1,3 @@ +SRC_DIR := shared plc + +include $(KERNEL_ROOT)/compiler.mk diff --git a/APP_Framework/Framework/control/plc/Makefile b/APP_Framework/Framework/control/plc/Makefile new file mode 100755 index 0000000..6c76af1 --- /dev/null +++ b/APP_Framework/Framework/control/plc/Makefile @@ -0,0 +1,4 @@ +SRC_DIR := shared interoperability + +include $(KERNEL_ROOT)/compiler.mk + diff --git a/APP_Framework/Framework/control/plc/interoperability/Kconfig b/APP_Framework/Framework/control/plc/interoperability/Kconfig new file mode 100755 index 0000000..6a7cb03 --- /dev/null +++ b/APP_Framework/Framework/control/plc/interoperability/Kconfig @@ -0,0 +1,10 @@ + +menuconfig USING_CONTROL_PLC_OPCUA + bool "PLC support OPCUA" + default y + depends on RESOURCES_LWIP + +menuconfig USING_CONTROL_PLC_SOCKET + bool "PLC support SOCKET" + default y + depends on RESOURCES_LWIP diff --git a/APP_Framework/Framework/control/plc/interoperability/Makefile b/APP_Framework/Framework/control/plc/interoperability/Makefile new file mode 100755 index 0000000..d329b91 --- /dev/null +++ b/APP_Framework/Framework/control/plc/interoperability/Makefile @@ -0,0 +1,17 @@ +SRC_DIR := + +ifeq ($(CONFIG_RESOURCES_LWIP),y) + +ifeq ($(CONFIG_USING_CONTROL_PLC_OPCUA), y) + SRC_DIR += opcua +endif + +ifeq ($(CONFIG_USING_CONTROL_PLC_SOCKET), y) + SRC_DIR += socket +endif + +endif + +SRC_FILES += interoperability.c + +include $(KERNEL_ROOT)/compiler.mk diff --git a/APP_Framework/Framework/control/plc/interoperability/interoperability.c b/APP_Framework/Framework/control/plc/interoperability/interoperability.c new file mode 100755 index 0000000..74c46fa --- /dev/null +++ b/APP_Framework/Framework/control/plc/interoperability/interoperability.c @@ -0,0 +1,30 @@ +/* +* Copyright (c) 2021 AIIT XUOS Lab +* XiUOS is licensed under Mulan PSL v2. +* You can use this software according to the terms and conditions of the Mulan PSL v2. +* You may obtain a copy of Mulan PSL v2 at: +* http://license.coscl.org.cn/MulanPSL2 +* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, +* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, +* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. +* See the Mulan PSL v2 for more details. +*/ + + +void ctrl_interop_init(void) +{ +} + +void ctrl_interop_connect(void) +{ +} + +void ctrl_interop_enable(void) +{ +} + +void ctrl_interop_disable(void) +{ +} + + diff --git a/APP_Framework/Framework/control/plc/interoperability/opcua/Kconfig b/APP_Framework/Framework/control/plc/interoperability/opcua/Kconfig new file mode 100755 index 0000000..e69de29 diff --git a/APP_Framework/Framework/control/plc/interoperability/opcua/Makefile b/APP_Framework/Framework/control/plc/interoperability/opcua/Makefile new file mode 100755 index 0000000..47d275f --- /dev/null +++ b/APP_Framework/Framework/control/plc/interoperability/opcua/Makefile @@ -0,0 +1,3 @@ +SRC_FILES := ua_data.c open62541.c ua_client.c ua_server.c ua_api.c ua_test.c + +include $(KERNEL_ROOT)/compiler.mk diff --git a/APP_Framework/Framework/control/plc/interoperability/opcua/ua_api.c b/APP_Framework/Framework/control/plc/interoperability/opcua/ua_api.c new file mode 100755 index 0000000..7115ca1 --- /dev/null +++ b/APP_Framework/Framework/control/plc/interoperability/opcua/ua_api.c @@ -0,0 +1,98 @@ +/* +* Copyright (c) 2021 AIIT XUOS Lab +* XiUOS is licensed under Mulan PSL v2. +* You can use this software according to the terms and conditions of the Mulan PSL v2. +* You may obtain a copy of Mulan PSL v2 at: +* http://license.coscl.org.cn/MulanPSL2 +* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, +* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, +* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. +* See the Mulan PSL v2 for more details. +*/ + +/** + * @file ua_api.c + * @brief Demo for OpcUa function + * @version 1.0 + * @author AIIT XUOS Lab + * @date 2021.11.11 + */ + +#include "open62541.h" +#include +#include "ua_api.h" + +int UaDevOpen(void *dev) +{ + UaParamType *param = (UaParamType *)dev; + + param->client = UA_Client_new(); + + ua_notice("ua: [%s] start ...\n", __func__); + + if (param->client == NULL) + { + ua_error("ua: [%s] tcp client null\n", __func__); + return EEMPTY; + } + + UA_ClientConfig *config = UA_Client_getConfig(param->client); + UA_ClientConfig_setDefault(config); + + ua_notice("ua: [%s] %d %s\n", __func__, strlen(param->ua_remote_ip), param->ua_remote_ip); + + UA_StatusCode retval = UA_Client_connect(param->client, param->ua_remote_ip); + if(retval != UA_STATUSCODE_GOOD) { + ua_error("ua: [%s] deleted ret %x!\n", __func__, retval); + return (int)retval; + } + return EOK; +} + +void UaDevClose(void *dev) +{ + UaParamType *param = (UaParamType *)dev; + ua_notice("ua: [%s] close %s!\n", __func__, param->ua_remote_ip); + UA_Client_delete(param->client); /* Disconnects the client internally */ +} + +int UaDevRead(void *dev, void *buf, size_t len) +{ + UaParamType *param = (UaParamType *)dev; + switch(param->act) + { + case UA_ACT_ATTR: + UaReadNodeValue(param->client, param->ua_id, buf); + break; + case UA_ACT_OBJ: + UaTestBrowserObjects(param->client); + break; + default: + break; + } + return EOK; +} + +int UaDevWrite(void *dev, const void *buf, size_t len) +{ + UaParamType *param = (UaParamType *)dev; + + switch(param->act) + { + case UA_ACT_ATTR: + UaWriteNodeValue(param->client, param->ua_id, (char *)buf); + break; + case UA_ACT_OBJ: + UaTestBrowserObjects(param->client); + break; + default: + break; + } + return EOK; +} + +int UaDevIoctl(void *dev, int cmd, void *arg) +{ + return EOK; +} + diff --git a/APP_Framework/Framework/control/plc/interoperability/opcua/ua_api.h b/APP_Framework/Framework/control/plc/interoperability/opcua/ua_api.h new file mode 100755 index 0000000..30c7855 --- /dev/null +++ b/APP_Framework/Framework/control/plc/interoperability/opcua/ua_api.h @@ -0,0 +1,72 @@ +/* +* Copyright (c) 2021 AIIT XUOS Lab +* XiUOS is licensed under Mulan PSL v2. +* You can use this software according to the terms and conditions of the Mulan PSL v2. +* You may obtain a copy of Mulan PSL v2 at: +* http://license.coscl.org.cn/MulanPSL2 +* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, +* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, +* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. +* See the Mulan PSL v2 for more details. +*/ + +/** + * @file ua_api.h + * @brief API for OpcUa function + * @version 1.0 + * @author AIIT XUOS Lab + * @date 2021.11.11 + */ + +#ifndef __UA_API_H__ +#define __UA_API_H__ + +#include "open62541.h" + +#define UA_DEV_IP_LEN 48 +#define UA_NODE_LEN 32 + +enum UaAction_e +{ + UA_ACT_ATTR, + UA_ACT_OBJ, +}; + +typedef struct UaParam +{ + enum UaAction_e act; + UA_NodeId ua_id; + char ua_remote_ip[UA_DEV_IP_LEN]; + char ua_node[UA_NODE_LEN]; + UA_Client *client; +}UaParamType; + +#define ua_print //KPrintf +#define ua_notice KPrintf +#define ua_error KPrintf + +extern const char *opc_server_url; +extern char test_ua_ip[]; + +int UaServerRun(void); +void UaBrowserNodes(UA_Client *client); +void UaBrowserNodeId(UA_Client *client, UA_NodeId id); +void UaGetServerTime(UA_Client *client); +void UaAddNodes(UA_Client *client); + +int UaDevOpen(void *dev); // open and connect PLC device +void UaDevClose(void* dev); // close and disconnect PLC device +int UaDevRead(void* dev, void *buf, size_t len); // read data from PLC +int UaDevWrite(void* dev, const void *buf, size_t len); // write data from PLC +int UaDevIoctl(void* dev, int cmd, void *arg); // send control command to PLC + +char *UaGetNodeIdString(UA_NodeId *node_id); +void UaReadNodeValue(UA_Client *client, UA_NodeId id, UA_Int32 *value); +void UaWriteNodeValue(UA_Client *client, UA_NodeId id, char* value); +UA_StatusCode UaReadArrayValue(UA_Client *client, int array_size, UA_ReadValueId *array); +int UaGetNodeIdArray(UA_Client* client, UA_NodeId id, int array_size, int *id_array); + +void UaTestBrowserObjects(UA_Client *client); +int UaTestInteractServer(UA_Client *client); + +#endif diff --git a/APP_Framework/Framework/control/plc/interoperability/opcua/ua_client.c b/APP_Framework/Framework/control/plc/interoperability/opcua/ua_client.c new file mode 100755 index 0000000..b903be8 --- /dev/null +++ b/APP_Framework/Framework/control/plc/interoperability/opcua/ua_client.c @@ -0,0 +1,557 @@ +/* +* Copyright (c) 2021 AIIT XUOS Lab +* XiUOS is licensed under Mulan PSL v2. +* You can use this software according to the terms and conditions of the Mulan PSL v2. +* You may obtain a copy of Mulan PSL v2 at: +* http://license.coscl.org.cn/MulanPSL2 +* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, +* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, +* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. +* See the Mulan PSL v2 for more details. +*/ + +/** + * @file ua_client.c + * @brief Client for OpcUa function + * @version 1.0 + * @author AIIT XUOS Lab + * @date 2021.11.11 + */ + +#include +#include "open62541.h" +#include "ua_api.h" + +#define UA_RESPONSE_TIMEOUT 10000 + +const char *opc_server_url = {"opc.tcp://192.168.250.2:4840"}; + +#ifdef UA_ENABLE_SUBSCRIPTIONS +static void UaAnswerChangedHandler(UA_Client* client, UA_UInt32 subId, void* subContext, + UA_UInt32 monId, void* monContext, UA_DataValue* value) +{ + ua_notice("Answer changed!\n"); +} +#endif + +static UA_StatusCode UaShowNodeIdIterate(UA_NodeId childId, UA_Boolean isInverse, UA_NodeId referenceTypeId, void* handle) +{ + if(isInverse) + { + return UA_STATUSCODE_GOOD; + } + + UA_NodeId* parent = (UA_NodeId*)handle; + ua_notice("%d, %d --- %d ---> NodeId %d, %d\n", + parent->namespaceIndex, parent->identifier.numeric, + referenceTypeId.identifier.numeric, childId.namespaceIndex, + childId.identifier.numeric); + return UA_STATUSCODE_GOOD; +} + +int UaGetEndPoints(UA_Client* client) +{ + /* Listing endpoints */ + UA_EndpointDescription* endpointArray = NULL; + size_t endpointArraySize = 0; + UA_StatusCode ret = UA_Client_getEndpoints(client, opc_server_url, + &endpointArraySize, &endpointArray); + + if(ret != UA_STATUSCODE_GOOD) + { + UA_Array_delete(endpointArray, endpointArraySize, &UA_TYPES[UA_TYPES_ENDPOINTDESCRIPTION]); + return EXIT_FAILURE; + } + + ua_print("%i endpoints found\n", (int)endpointArraySize); + + for(size_t i=0; itype == &UA_TYPES[UA_TYPES_LOCALIZEDTEXT]) + { + UA_LocalizedText* ptr = (UA_LocalizedText*)val->data; + ua_notice("%.*s (Text)\n", ptr->text.length, ptr->text.data); + } + else if(val->type == &UA_TYPES[UA_TYPES_UINT32]) + { + UA_UInt32* ptr = (UA_UInt32*)val->data; + ua_notice("%d (UInt32)\n", *ptr); + } + else if(val->type == &UA_TYPES[UA_TYPES_BOOLEAN]) + { + UA_Boolean* ptr = (UA_Boolean*)val->data; + ua_notice("%i (BOOL)\n", *ptr); + } + else if(val->type == &UA_TYPES[UA_TYPES_INT32]) + { + UA_Int32* ptr = (UA_Int32*)val->data; + ua_notice("%d (Int32)\n", *ptr); + } + else if(val->type == &UA_TYPES[UA_TYPES_INT16]) + { + UA_Int16* ptr = (UA_Int16*)val->data; + ua_notice("%d (Int16)\n", *ptr); + } + else if(val->type == &UA_TYPES[UA_TYPES_FLOAT]) + { + UA_Float* ptr = (UA_Float*)val->data; + printf("%f (Float)\n", *ptr); + } + else if(val->type == &UA_TYPES[UA_TYPES_DOUBLE]) + { + UA_Double* ptr = (UA_Double*)val->data; + printf("%f (Double)\n", *ptr); + } + else if(val->type == &UA_TYPES[UA_TYPES_STRING]) + { + UA_String* ptr = (UA_String*)val->data; + ua_notice("%*.s (String)\n", ptr->length, ptr->data); + } + else if(val->type == &UA_TYPES[UA_TYPES_DATETIME]) + { + UA_DateTime* ptr = (UA_DateTime*)val->data; + UA_DateTimeStruct dts = UA_DateTime_toStruct(*ptr); + ua_notice("%d-%d-%d %d:%d:%d.%03d (Time)\n", + dts.day, dts.month, dts.year, dts.hour, dts.min, dts.sec, dts.milliSec); + } +} + +char *UaGetNodeIdString(UA_NodeId *node_id) +{ + static char nodeid_str[UA_NODE_LEN] = {0}; + + switch(node_id->identifierType) + { + case UA_NODEIDTYPE_NUMERIC: + snprintf(nodeid_str, UA_NODE_LEN, "n%d,%d", node_id->namespaceIndex, node_id->identifier.numeric); + break; + case UA_NODEIDTYPE_STRING: + snprintf(nodeid_str, UA_NODE_LEN, "n%d,%.*s", node_id->namespaceIndex, node_id->identifier.string.length, + node_id->identifier.string.data); + break; + case UA_NODEIDTYPE_BYTESTRING: + snprintf(nodeid_str, UA_NODE_LEN, "n%d,%s", node_id->namespaceIndex, node_id->identifier.byteString.data); + break; + default: + break; + } + return nodeid_str; +} + +static void UaShowNodeId(UA_NodeId *node_id) +{ + switch(node_id->identifierType) + { + case UA_NODEIDTYPE_NUMERIC: + ua_notice(" NodeID n%d,%d ", node_id->namespaceIndex, node_id->identifier.numeric); + break; + case UA_NODEIDTYPE_STRING: + ua_notice(" NodeID n%d,%.*s ", node_id->namespaceIndex, node_id->identifier.string.length, + node_id->identifier.string.data); + break; + case UA_NODEIDTYPE_BYTESTRING: + ua_notice(" NodeID n%d,%s ", node_id->namespaceIndex, node_id->identifier.byteString.data); + break; + default: + break; + } +} + +static void UaShowObject(UA_BrowseResponse* res) +{ + ua_notice("%-9s %-16s %-16s %-16s\n", "NAMESPACE", "NODEID", "BROWSE NAME", "DISPLAY NAME"); + + for(size_t i = 0; i < res->resultsSize; ++i) + { + for(size_t j = 0; j < res->results[i].referencesSize; ++j) + { + UA_ReferenceDescription* ref = &(res->results[i].references[j]); + + if(ref->nodeId.nodeId.identifierType == UA_NODEIDTYPE_NUMERIC) + { + ua_notice("%-9d %-16d %-16.*s %-16.*s\n", ref->nodeId.nodeId.namespaceIndex, + ref->nodeId.nodeId.identifier.numeric, (int)ref->browseName.name.length, + ref->browseName.name.data, (int)ref->displayName.text.length, + ref->displayName.text.data); + } + else if(ref->nodeId.nodeId.identifierType == UA_NODEIDTYPE_STRING) + { + ua_notice("%-9d %-16.*s %-16.*s %-16.*s\n", ref->nodeId.nodeId.namespaceIndex, + (int)ref->nodeId.nodeId.identifier.string.length, + ref->nodeId.nodeId.identifier.string.data, + (int)ref->browseName.name.length, ref->browseName.name.data, + (int)ref->displayName.text.length, ref->displayName.text.data); + } + + /* TODO: distinguish further types */ + } + } + + ua_notice("\n"); +} + +UA_StatusCode UaReadArrayValue(UA_Client* client, int array_size, UA_ReadValueId* array) +{ + UA_ReadRequest request; + UA_ReadRequest_init(&request); + request.nodesToRead = array; + request.nodesToReadSize = array_size; + UA_ReadResponse response = UA_Client_Service_read(client, request); + + if((response.responseHeader.serviceResult != UA_STATUSCODE_GOOD) + || (response.resultsSize != array_size)) + { + UA_ReadResponse_clear(&response); + ua_notice("ua: [%s] read failed 0x%x\n", __func__, + response.responseHeader.serviceResult); + return UA_STATUSCODE_BADUNEXPECTEDERROR; + } + + UA_StatusCode* arr_ret = malloc(array_size * sizeof(UA_StatusCode)); + if(arr_ret == NULL) + { + ua_error("ua: [%s] malloc %d failed!\n", __func__, array_size * sizeof(UA_StatusCode)); + return UA_STATUSCODE_BADOUTOFMEMORY; + } + + for(int i = 0; i < array_size; ++i) + { + if((response.results[i].status == UA_STATUSCODE_GOOD) + && (response.results[i].hasValue)) + { + ua_notice("node %s: ", UaGetNodeIdString(&array[i].nodeId)); + UaShowNodeValue(&response.results[i].value); + } + } + ua_notice("\n"); + + free(arr_ret); + UA_ReadResponse_clear(&response); + return UA_STATUSCODE_GOOD; +} + +void UaBrowserNodeId(UA_Client* client, UA_NodeId id) +{ + UA_BrowseRequest ua_req; + UA_BrowseResponse ua_resp; + + /* Browse some objects */ + ua_notice("Browsing nodes in objects folder:\n"); + + UA_BrowseRequest_init(&ua_req); + + ua_req.requestedMaxReferencesPerNode = 0; + ua_req.nodesToBrowse = UA_BrowseDescription_new(); + ua_req.nodesToBrowseSize = 1; + ua_req.nodesToBrowse[0].nodeId = id; /* browse objects folder */ + ua_req.nodesToBrowse[0].resultMask = UA_BROWSERESULTMASK_ALL; /* return everything */ + + ua_resp = UA_Client_Service_browse(client, ua_req); + + UaShowObject(&ua_resp); + + UA_BrowseResponse_clear(&ua_resp); +} + + +int UaGetNodeIdArray(UA_Client* client, UA_NodeId id, int array_size, int *id_array) +{ + int i, j; + int array_cnt = 0;// return array number + UA_BrowseRequest ua_req; + UA_BrowseResponse ua_resp; + + /* Browse some objects */ + ua_notice("Browsing nodes in objects folder:\n"); + + UA_BrowseRequest_init(&ua_req); + + ua_req.requestedMaxReferencesPerNode = 0; + ua_req.nodesToBrowse = UA_BrowseDescription_new(); + ua_req.nodesToBrowseSize = 1; + ua_req.nodesToBrowse[0].nodeId = id; /* browse objects folder */ + ua_req.nodesToBrowse[0].resultMask = UA_BROWSERESULTMASK_ALL; /* return everything */ + + ua_resp = UA_Client_Service_browse(client, ua_req); + + for(i = 0; i < ua_resp.resultsSize; ++i) + { + for(j = 0; j < ua_resp.results[i].referencesSize; ++j) + { + UA_ReferenceDescription* ref = &(ua_resp.results[i].references[j]); + + if(ref->nodeId.nodeId.identifierType == UA_NODEIDTYPE_NUMERIC) + { + *(id_array + array_cnt) = ref->nodeId.nodeId.identifier.numeric; + array_cnt ++; + if(array_cnt >= array_size) + { + UA_BrowseResponse_clear(&ua_resp); + return array_cnt; + } + } + } + } + + UA_BrowseResponse_clear(&ua_resp); + return array_cnt; +} + +void UaBrowserNodes(UA_Client* client) +{ + UA_NodeId* parent = UA_NodeId_new(); + *parent = UA_NODEID_NUMERIC(0, UA_NS0ID_OBJECTSFOLDER); + UA_Client_forEachChildNodeCall(client, UA_NODEID_NUMERIC(0, UA_NS0ID_OBJECTSFOLDER), UaShowNodeIdIterate, (void*) parent); + UA_NodeId_delete(parent); +} + +UA_UInt32 UaStartSubscription(UA_Client* client, UA_NodeId node_id) +{ + /* Create a subscription */ + UA_CreateSubscriptionRequest request = UA_CreateSubscriptionRequest_default(); + UA_CreateSubscriptionResponse response = UA_Client_Subscriptions_create(client, request, + NULL, NULL, NULL); + UA_UInt32 subId = response.subscriptionId; + + if(response.responseHeader.serviceResult == UA_STATUSCODE_GOOD) + { + ua_print("Create subscription succeeded, id %u\n", subId); + } + else + { + ua_print("Create subscription failed, id %u\n", response.responseHeader.serviceResult); + return response.responseHeader.serviceResult; + } + + UA_MonitoredItemCreateRequest monRequest = + UA_MonitoredItemCreateRequest_default(node_id); + UA_MonitoredItemCreateResult monResponse = + UA_Client_MonitoredItems_createDataChange(client, response.subscriptionId, + UA_TIMESTAMPSTORETURN_BOTH, + monRequest, NULL, UaAnswerChangedHandler, NULL); + + if(monResponse.statusCode == UA_STATUSCODE_GOOD) + { + ua_print("Monitoring 'the.answer', id %u\n", monResponse.monitoredItemId); + } + else + { + ua_print("%s return 0x%x\n", __func__, monResponse.statusCode); + } + + /* The first publish request should return the initial value of the variable */ + UA_Client_run_iterate(client, UA_RESPONSE_TIMEOUT); + return subId; +} + +void UaWriteNodeValue(UA_Client* client, UA_NodeId id, char* value) +{ + UA_Boolean bool_val; + uint32_t integer_val; + UA_WriteRequest wReq; + UA_WriteRequest_init(&wReq); + + wReq.nodesToWrite = UA_WriteValue_new(); + wReq.nodesToWriteSize = 1; + + if(strncmp(value, "1b", 2) == 0) + { + wReq.nodesToWrite[0].value.value.type = &UA_TYPES[UA_TYPES_BOOLEAN]; + bool_val = 1; + wReq.nodesToWrite[0].value.value.data = &bool_val; + } + else if(strncmp(value, "0b", 2) == 0) + { + wReq.nodesToWrite[0].value.value.type = &UA_TYPES[UA_TYPES_BOOLEAN]; + bool_val = 0; + wReq.nodesToWrite[0].value.value.data = &bool_val; + } + else + { + wReq.nodesToWrite[0].value.value.type = &UA_TYPES[UA_TYPES_INT16]; + sscanf(value, "%d", &integer_val); + wReq.nodesToWrite[0].value.value.data = &integer_val; + } + + wReq.nodesToWrite[0].nodeId = id; + wReq.nodesToWrite[0].attributeId = UA_ATTRIBUTEID_VALUE; + wReq.nodesToWrite[0].value.hasValue = true; + wReq.nodesToWrite[0].value.value.storageType = UA_VARIANT_DATA_NODELETE; /* do not free the integer on deletion */ + UA_WriteResponse wResp = UA_Client_Service_write(client, wReq); + + if(wResp.responseHeader.serviceResult == UA_STATUSCODE_GOOD) + { + ua_notice("write new value is: %s\n", value); + } + + UA_WriteRequest_clear(&wReq); + UA_WriteResponse_clear(&wResp); +} + +/* Read attribute */ +void UaReadNodeValue(UA_Client* client, UA_NodeId id, UA_Int32 *value) +{ + UA_Variant* val = UA_Variant_new(); + UA_StatusCode ret = UA_Client_readValueAttribute(client, id, val); + + if(ret == UA_STATUSCODE_GOOD) + { + UaShowNodeValue(val); + if(UA_Variant_isScalar(val)) + { + if(val->type == &UA_TYPES[UA_TYPES_BOOLEAN]) + { + *value = *(UA_Boolean *)val->data; + } + else if(val->type == &UA_TYPES[UA_TYPES_INT32]) + { + *value = *(UA_Int32 *)val->data; + } + else if(val->type == &UA_TYPES[UA_TYPES_INT16]) + { + *value = *(UA_Int16 *)val->data; + } + } + } + + UA_Variant_delete(val); +} + +void UaCallRemote(UA_Client* client) +{ + /* Call a remote method */ + UA_Variant input; + UA_String argString = UA_STRING("Hello Server"); + UA_Variant_init(&input); + UA_Variant_setScalarCopy(&input, &argString, &UA_TYPES[UA_TYPES_STRING]); + size_t outputSize; + UA_Variant* output; + UA_StatusCode ret = UA_Client_call(client, UA_NODEID_NUMERIC(0, UA_NS0ID_OBJECTSFOLDER), + UA_NODEID_NUMERIC(1, 62541), 1, &input, &outputSize, &output); + + if(ret == UA_STATUSCODE_GOOD) + { + ua_print("Method call was successful, and %lu returned values available.\n", + (unsigned long)outputSize); + UA_Array_delete(output, outputSize, &UA_TYPES[UA_TYPES_VARIANT]); + } + else + { + ua_print("Method call was unsuccessful, and %x returned values available.\n", ret); + } + + UA_Variant_clear(&input); +} + + +void UaAddNodes(UA_Client* client) +{ + /* Add new nodes*/ + /* New ReferenceType */ + UA_NodeId ref_id; + UA_ReferenceTypeAttributes ref_attr = UA_ReferenceTypeAttributes_default; + ref_attr.displayName = UA_LOCALIZEDTEXT("en-US", "NewReference"); + ref_attr.description = UA_LOCALIZEDTEXT("en-US", "References something that might or might not exist"); + ref_attr.inverseName = UA_LOCALIZEDTEXT("en-US", "IsNewlyReferencedBy"); + UA_StatusCode ret = UA_Client_addReferenceTypeNode(client, + UA_NODEID_NUMERIC(1, 12133), + UA_NODEID_NUMERIC(0, UA_NS0ID_ORGANIZES), + UA_NODEID_NUMERIC(0, UA_NS0ID_HASSUBTYPE), + UA_QUALIFIEDNAME(1, "NewReference"), + ref_attr, &ref_id); + + if(ret == UA_STATUSCODE_GOOD) + { + ua_print("Created 'NewReference' with numeric NodeID %u\n", ref_id.identifier.numeric); + } + + /* New ObjectType */ + UA_NodeId objt_id; + UA_ObjectTypeAttributes objt_attr = UA_ObjectTypeAttributes_default; + objt_attr.displayName = UA_LOCALIZEDTEXT("en-US", "TheNewObjectType"); + objt_attr.description = UA_LOCALIZEDTEXT("en-US", "Put innovative description here"); + ret = UA_Client_addObjectTypeNode(client, + UA_NODEID_NUMERIC(1, 12134), + UA_NODEID_NUMERIC(0, UA_NS0ID_BASEOBJECTTYPE), + UA_NODEID_NUMERIC(0, UA_NS0ID_HASSUBTYPE), + UA_QUALIFIEDNAME(1, "NewObjectType"), + objt_attr, &objt_id); + + if(ret == UA_STATUSCODE_GOOD) + { + ua_print("Created 'NewObjectType' with numeric NodeID %u\n", objt_id.identifier.numeric); + } + + /* New Object */ + UA_NodeId obj_id; + UA_ObjectAttributes obj_attr = UA_ObjectAttributes_default; + obj_attr.displayName = UA_LOCALIZEDTEXT("en-US", "TheNewGreatNode"); + obj_attr.description = UA_LOCALIZEDTEXT("de-DE", "Hier koennte Ihre Webung stehen!"); + ret = UA_Client_addObjectNode(client, + UA_NODEID_NUMERIC(1, 0), + UA_NODEID_NUMERIC(0, UA_NS0ID_OBJECTSFOLDER), + UA_NODEID_NUMERIC(0, UA_NS0ID_ORGANIZES), + UA_QUALIFIEDNAME(1, "TheGreatNode"), + UA_NODEID_NUMERIC(1, 12134), + obj_attr, &obj_id); + + if(ret == UA_STATUSCODE_GOOD) + { + ua_print("Created 'NewObject' with numeric NodeID %u\n", obj_id.identifier.numeric); + } + + /* New Integer Variable */ + UA_NodeId var_id; + UA_VariableAttributes var_attr = UA_VariableAttributes_default; + var_attr.displayName = UA_LOCALIZEDTEXT("en-US", "TheNewVariableNode"); + var_attr.description = + UA_LOCALIZEDTEXT("en-US", "This integer is just amazing - it has digits and everything."); + UA_Int32 int_value = 1234; + /* This does not copy the value */ + UA_Variant_setScalar(&var_attr.value, &int_value, &UA_TYPES[UA_TYPES_INT32]); + var_attr.dataType = UA_TYPES[UA_TYPES_INT32].typeId; + ret = UA_Client_addVariableNode(client, + UA_NODEID_NUMERIC(1, 0), // Assign new/random NodeID + UA_NODEID_NUMERIC(0, UA_NS0ID_OBJECTSFOLDER), + UA_NODEID_NUMERIC(0, UA_NS0ID_ORGANIZES), + UA_QUALIFIEDNAME(0, "VariableNode"), + UA_NODEID_NULL, // no variable type + var_attr, &var_id); + + if(ret == UA_STATUSCODE_GOOD) + { + ua_print("Created 'NewVariable' with numeric NodeID %u\n", var_id.identifier.numeric); + } +} + +void UaGetServerTime(UA_Client* client) +{ + UA_Variant value; + UA_Variant_init(&value); + + const UA_NodeId nodeId = UA_NODEID_NUMERIC(0, UA_NS0ID_SERVER_SERVERSTATUS_CURRENTTIME); + UA_StatusCode ret = UA_Client_readValueAttribute(client, nodeId, &value); + + if(ret == UA_STATUSCODE_GOOD && UA_Variant_hasScalarType(&value, &UA_TYPES[UA_TYPES_DATETIME])) + { + UA_DateTime raw_date = *(UA_DateTime*) value.data; + UA_DateTimeStruct dts = UA_DateTime_toStruct(raw_date); + ua_notice("date is: %d-%d-%d %d:%d:%d.%03d\n", + dts.day, dts.month, dts.year, dts.hour, dts.min, dts.sec, dts.milliSec); + } + + /* Clean up */ + UA_Variant_clear(&value); +} + diff --git a/APP_Framework/Framework/control/plc/interoperability/opcua/ua_data.c b/APP_Framework/Framework/control/plc/interoperability/opcua/ua_data.c new file mode 100755 index 0000000..118598e --- /dev/null +++ b/APP_Framework/Framework/control/plc/interoperability/opcua/ua_data.c @@ -0,0 +1,201 @@ +#include "open62541.h" + +/* Opc.Ua - ns=0;i=7617 */ +const UA_Byte variablenode_ns_0_i_7617_variant_DataContents_byteArray[177218] = {60, 111, 112, 99, 58, 84, 121, 112, 101, 68, 105, 99, 116, 105, 111, 110, 97, 114, 121, 13, 10, 32, 32, 120, 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61, 34, 49, 34, 32, 47, 62, 13, 10, 32, 32, 32, 32, 60, 111, 112, 99, 58, 69, 110, 117, 109, 101, 114, 97, 116, 101, 100, 86, 97, 108, 117, 101, 32, 78, 97, 109, 101, 61, 34, 78, 117, 109, 101, 114, 105, 99, 34, 32, 86, 97, 108, 117, 101, 61, 34, 50, 34, 32, 47, 62, 13, 10, 32, 32, 32, 32, 60, 111, 112, 99, 58, 69, 110, 117, 109, 101, 114, 97, 116, 101, 100, 86, 97, 108, 117, 101, 32, 78, 97, 109, 101, 61, 34, 83, 116, 114, 105, 110, 103, 34, 32, 86, 97, 108, 117, 101, 61, 34, 51, 34, 32, 47, 62, 13, 10, 32, 32, 32, 32, 60, 111, 112, 99, 58, 69, 110, 117, 109, 101, 114, 97, 116, 101, 100, 86, 97, 108, 117, 101, 32, 78, 97, 109, 101, 61, 34, 71, 117, 105, 100, 34, 32, 86, 97, 108, 117, 101, 61, 34, 52, 34, 32, 47, 62, 13, 10, 32, 32, 32, 32, 60, 111, 112, 99, 58, 69, 110, 117, 109, 101, 114, 97, 116, 101, 100, 86, 97, 108, 117, 101, 32, 78, 97, 109, 101, 61, 34, 66, 121, 116, 101, 83, 116, 114, 105, 110, 103, 34, 32, 86, 97, 108, 117, 101, 61, 34, 53, 34, 32, 47, 62, 13, 10, 32, 32, 60, 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109, 101, 114, 97, 116, 101, 100, 86, 97, 108, 117, 101, 32, 78, 97, 109, 101, 61, 34, 85, 110, 107, 110, 111, 119, 110, 34, 32, 86, 97, 108, 117, +101, 61, 34, 52, 34, 32, 47, 62, 13, 10, 32, 32, 60, 47, 111, 112, 99, 58, 69, 110, 117, 109, 101, 114, 97, 116, 101, 100, 84, 121, 112, 101, 62, 13, 10, 13, 10, 60, 47, 111, 112, 99, 58, 84, 121, 112, 101, 68, 105, 99, 116, 105, 111, 110, 97, 114, 121, 62}; + + diff --git a/APP_Framework/Framework/control/plc/interoperability/opcua/ua_server.c b/APP_Framework/Framework/control/plc/interoperability/opcua/ua_server.c new file mode 100755 index 0000000..548a357 --- /dev/null +++ b/APP_Framework/Framework/control/plc/interoperability/opcua/ua_server.c @@ -0,0 +1,38 @@ +/* +* Copyright (c) 2021 AIIT XUOS Lab +* XiUOS is licensed under Mulan PSL v2. +* You can use this software according to the terms and conditions of the Mulan PSL v2. +* You may obtain a copy of Mulan PSL v2 at: +* http://license.coscl.org.cn/MulanPSL2 +* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, +* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, +* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. +* See the Mulan PSL v2 for more details. +*/ + +/** + * @file ua_server.c + * @brief Server for OpcUa function + * @version 1.0 + * @author AIIT XUOS Lab + * @date 2021.11.11 + */ + +#include "open62541.h" + +UA_Boolean ua_server_flag = true; + +int UaRunServer(void) +{ + UA_StatusCode ret; + + UA_Server *server = UA_Server_new(); + + UA_ServerConfig_setDefault(UA_Server_getConfig(server)); + + ret = UA_Server_run(server, &ua_server_flag); + + UA_Server_delete(server); + + return ret; +} diff --git a/APP_Framework/Framework/control/plc/interoperability/opcua/ua_test.c b/APP_Framework/Framework/control/plc/interoperability/opcua/ua_test.c new file mode 100755 index 0000000..1b9ed84 --- /dev/null +++ b/APP_Framework/Framework/control/plc/interoperability/opcua/ua_test.c @@ -0,0 +1,86 @@ +/* +* Copyright (c) 2021 AIIT XUOS Lab +* XiUOS is licensed under Mulan PSL v2. +* You can use this software according to the terms and conditions of the Mulan PSL v2. +* You may obtain a copy of Mulan PSL v2 at: +* http://license.coscl.org.cn/MulanPSL2 +* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, +* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, +* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. +* See the Mulan PSL v2 for more details. +*/ + +/** + * @file ua_test.c + * @brief Test for OpcUa function + * @version 1.0 + * @author AIIT XUOS Lab + * @date 2021.11.11 + */ + +#include +#include "open62541.h" +#include "ua_api.h" + +//for target NODEID +#define UA_TEST_BROWSER_NODEID UA_NODEID_STRING(3, "ServerInterfaces") +#define UA_TEST_BROWSER_NODEID1 UA_NODEID_NUMERIC(4, 1) +#define UA_TEST_WRITE_NODEID UA_NODEID_NUMERIC(4, 5) + +#define UA_TEST_NODE_ARRAY_NUM 10 + +static UA_StatusCode UaTestReadArrayValue(UA_Client *client, UA_NodeId id) +{ + int i; + int array_size = 0; + int test_id[UA_TEST_NODE_ARRAY_NUM]; + UA_ReadValueId test_array[UA_TEST_NODE_ARRAY_NUM]; + + for(i = 0; i < UA_TEST_NODE_ARRAY_NUM; i++) + { + UA_ReadValueId_init(&test_array[i]); + test_array[i].attributeId = UA_ATTRIBUTEID_VALUE; + } + + array_size = UaGetNodeIdArray(client, id, UA_TEST_NODE_ARRAY_NUM, test_id); + + for(i = 0; i < array_size; i++) + { + test_array[i].nodeId = UA_NODEID_NUMERIC(id.namespaceIndex, test_id[i]); + } + + return UaReadArrayValue(client, array_size, test_array); +} + +void UaTestBrowserObjects(UA_Client *client) +{ + UA_NodeId test_id; + UaBrowserNodeId(client, UA_TEST_BROWSER_NODEID); + UaBrowserNodeId(client, UA_TEST_BROWSER_NODEID1); + test_id = UA_TEST_BROWSER_NODEID1; + ua_notice("Show values in %s:\n", UaGetNodeIdString(&test_id)); + UaTestReadArrayValue(client, test_id); + return; +} + +static void UaTestWriteNodeValue(UA_Client *client) +{ + UA_Int32 value; + char val_str[UA_NODE_LEN]; + UA_NodeId id = UA_TEST_WRITE_NODEID; + + ua_notice("--- Test write %s ---\n", UaGetNodeIdString(&id)); + UaReadNodeValue(client, id, &value); + UaWriteNodeValue(client, id, itoa(value + 1, val_str, 10)); + UaReadNodeValue(client, id, &value); + ua_notice("\n"); +} + +int UaTestInteractServer(UA_Client *client) +{ + UaGetServerTime(client); + UaTestBrowserObjects(client); + UaTestWriteNodeValue(client); + return EXIT_SUCCESS; +} + diff --git a/APP_Framework/Framework/control/plc/interoperability/socket/Kconfig b/APP_Framework/Framework/control/plc/interoperability/socket/Kconfig new file mode 100755 index 0000000..d8325aa --- /dev/null +++ b/APP_Framework/Framework/control/plc/interoperability/socket/Kconfig @@ -0,0 +1,11 @@ + +menuconfig USING_CONTROL_PLC_OPCUA + bool "PLC support OPCUA" + default y + depends on RESOURCES_LWIP + +menuconfig USING_CONTROL_PLC_SOCKET + bool "PLC support SOCKET" + default y + depends on RESOURCES_LWIP + diff --git a/APP_Framework/Framework/control/plc/interoperability/socket/Makefile b/APP_Framework/Framework/control/plc/interoperability/socket/Makefile new file mode 100755 index 0000000..2c3e00b --- /dev/null +++ b/APP_Framework/Framework/control/plc/interoperability/socket/Makefile @@ -0,0 +1,4 @@ +SRC_FILES := plc_socket.c + +include $(KERNEL_ROOT)/compiler.mk + diff --git a/APP_Framework/Framework/control/plc/interoperability/socket/README.md b/APP_Framework/Framework/control/plc/interoperability/socket/README.md new file mode 100755 index 0000000..798e81e --- /dev/null +++ b/APP_Framework/Framework/control/plc/interoperability/socket/README.md @@ -0,0 +1,18 @@ +# PLC SOCKET README + +## 文件说明 + +用于测试PLC socket通信. 通过建立与制定IP的PLC设备的socket连接, 发送命令给PLC设备, 实现相关功能. 实现该功能需要开启LWIP, 同时需要扩大shell的栈大小和内存空间。 + +### 命令行 + +PLCSocket ip=[PLC IP] port=[PLC port] tcp=[1: TCP; 0: UDP] cmd=[相关命令] file=[制定配置文件] + +配置文件支持json格式, 默认文件名为socket_param.json, 放置于plc目录下, 文件内容如下： + +{ + "ip": "192.168.250.6", + "port": 102, + "tcp": 1, + "cmd": [x, x, x] +} \ No newline at end of file diff --git a/APP_Framework/Framework/control/plc/interoperability/socket/plc_socket.c b/APP_Framework/Framework/control/plc/interoperability/socket/plc_socket.c new file mode 100755 index 0000000..74eba30 --- /dev/null +++ b/APP_Framework/Framework/control/plc/interoperability/socket/plc_socket.c @@ -0,0 +1,364 @@ +/* + * Copyright (c) 2022 AIIT XUOS Lab + * XiUOS is licensed under Mulan PSL v2. + * You can use this software according to the terms and conditions of the Mulan PSL v2. + * You may obtain a copy of Mulan PSL v2 at: + * http://license.coscl.org.cn/MulanPSL2 + * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, + * EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, + * MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. + * See the Mulan PSL v2 for more details. + */ + +/** + * @file plc_socket.c + * @brief Demo for PLC socket communication function + * @version 1.0 + * @author AIIT XUOS Lab + * @date 2022.03.16 + */ + +#include "transform.h" +#include "plc_socket.h" +#include "sys_arch.h" +#include "lwip/sockets.h" +#include "control_file.h" + +// max support plc socket test commands number +#define PLC_SOCK_CMD_NUM CTL_CMD_NUM +#define PLC_SOCK_TIMEOUT 50000 + +// for saving PLC command index +int plc_cmd_index = 0; + +// only for test +#define SUPPORT_PLC_SIEMENS + +//siemens test +PlcBinCmdType TestPlcCmd[PLC_SOCK_CMD_NUM] = {0}; + +//Test information +//SIEMENS ip: 192.168.250.9 port: 102 +//S7-200 ip: 192.168.250.8 port: 102 +//S7-1200 ip: 192.168.250.6 port: 102 +//OML ip: 192.168.250.3 port: 9600 + +PlcSocketParamType plc_socket_demo_data = { +#ifdef SUPPORT_PLC_SIEMENS + .ip = {192, 168, 250, 6}, + .port = 102, + .device_type = PLC_DEV_TYPE_SIEMENS, + .socket_type = SOCK_STREAM, + .cmd_num = 3, +#else + .ip = {192, 168, 250, 3}, + .port = 9600, + .device_type = PLC_DEV_TYPE_OML, + .socket_type = SOCK_DGRAM, + .cmd_num = 1, +#endif + .recv_len = PLC_RECV_BUF_LEN, + .recv_buf = NULL, +}; + +#define OML_HEADER_LEN 78 +#define CHECK_OML_HEADER(_s) ((0xC0 == *(_s)) && (0x00 == *(_s + 1)) && (0x02 == *(_s + 2)) && (0x00 == *(_s + 3))) + +/******************************************************************************/ + +static void plc_print_array(char *title, int size, uint8_t *cmd) +{ + lw_notice("%s : %d - ", title, size); + for(int i = 0; i < size; i++) + { + lw_notice(" %#x", cmd[i]); + } + lw_notice("\n"); +} + +static void *PlcSocketStart(void *arg) +{ + int fd = -1; + int timeout, recv_len; + struct sockaddr_in sock_addr; + socklen_t addr_len = sizeof(struct sockaddr_in); + PlcSocketParamType *param = (PlcSocketParamType *)&plc_socket_demo_data; + + plc_print("start %d.%d.%d.%d:%d dev %d sock %d\n", + param->ip[0], + param->ip[1], + param->ip[2], + param->ip[3], + param->port, + param->device_type, + param->socket_type); + + param->recv_len = PLC_RECV_BUF_LEN; + + //malloc memory + param->recv_buf = (char *)malloc(param->recv_len); + if (param->recv_buf == NULL) + { + plc_error("No memory\n"); + return NULL; + } + + fd = socket(AF_INET, param->socket_type, 0); + if (fd < 0) + { + plc_error("Socket error %d\n", param->socket_type); + free(param->recv_buf); + return NULL; + } + + plc_print("start %d.%d.%d.%d:%d\n", param->ip[0], param->ip[1], param->ip[2], param->ip[3], param->port); + + sock_addr.sin_family = AF_INET; + sock_addr.sin_port = htons(param->port); + sock_addr.sin_addr.s_addr = PP_HTONL(LWIP_MAKEU32(param->ip[0], param->ip[1], param->ip[2], param->ip[3])); + memset(&(sock_addr.sin_zero), 0, sizeof(sock_addr.sin_zero)); + + if (connect(fd, (struct sockaddr *)&sock_addr, sizeof(struct sockaddr)) < 0) + { + plc_error("Unable to connect\n"); + closesocket(fd); + free(param->recv_buf); + return NULL; + } + + lw_notice("client %s connected\n", inet_ntoa(sock_addr.sin_addr)); + + for(int i = 0; i < param->cmd_num; i ++) + { + PlcBinCmdType *cmd = &TestPlcCmd[i]; + sendto(fd, cmd->cmd, cmd->cmd_len, 0, (struct sockaddr*)&sock_addr, addr_len); + plc_print_array("Send cmd", cmd->cmd_len, cmd->cmd); + + MdelayKTask(cmd->delay_ms); + timeout = PLC_SOCK_TIMEOUT; + memset(param->recv_buf, 0, param->recv_len); + while(timeout --) + { + recv_len = recvfrom(fd, param->recv_buf, param->recv_len, 0, (struct sockaddr *)&sock_addr, &addr_len); + if(recv_len > 0) + { + if(param->device_type == PLC_DEV_TYPE_OML) + { + if((recv_len == OML_HEADER_LEN) && (CHECK_OML_HEADER(param->recv_buf))) + { + lw_notice("This is Oml package!!!\n"); + } + } + lw_notice("Receive from : %s\n", inet_ntoa(sock_addr.sin_addr)); + plc_print_array("Receive data", recv_len, param->recv_buf); + break; + } + } + } + + closesocket(fd); + free(param->recv_buf); + return NULL; +} + +void PlcGetParamCmd(char *cmd) +{ + const char s[2] = ","; + char *token; + uint16_t cmd_index = 0; + char bin_cmd[PLC_BIN_CMD_LEN] = {0}; + token = strtok(cmd, s); + while(token != NULL) + { + sscanf(token, "%x", &bin_cmd[cmd_index]); + plc_print("%d - %s %d\n", cmd_index, token, bin_cmd[cmd_index]); + token = strtok(NULL, s); + cmd_index ++; + } + TestPlcCmd[plc_cmd_index].cmd_len = cmd_index; + memcpy(TestPlcCmd[plc_cmd_index].cmd, bin_cmd, cmd_index); + plc_print("get %d cmd len %d\n", plc_cmd_index, TestPlcCmd[plc_cmd_index].cmd_len); + plc_cmd_index ++; + plc_socket_demo_data.cmd_num = plc_cmd_index; +} + +void PlcShowUsage(void) +{ + plc_notice("------------------------------------\n"); + plc_notice("PlcSocket [ip].[ip].[ip].[ip]:[port]\n"); + plc_notice("PlcSocket support other param:\n"); + plc_notice("plc=[] 0: OML 1:SIEMENS\n"); + plc_notice("tcp=[] 0: udp 1:tcp\n"); + plc_notice("ip=[ip.ip.ip.ip]\n"); + plc_notice("port=port\n"); + plc_notice("file: use %s\n", PLC_SOCK_FILE_NAME); + plc_notice("------------------------------------\n"); +} + +#if defined(MOUNT_SDCARD) && defined(LIB_USING_CJSON) +void PlcGetParamFromFile(char *file_name) +{ + PlcSocketParamType *param = &plc_socket_demo_data; + + char *file_buf = malloc(CTL_FILE_LEN); + if(file_buf == NULL) + { + plc_error("No enough buffer %d\n", CTL_FILE_LEN); + return; + } + memset(file_buf, 0, CTL_FILE_LEN); + + if(CtlFileReadWithFilename(file_name, CTL_FILE_LEN, file_buf) != EOK) + { + plc_error("Can't open file %s\n", file_name); + //try again default file + if(strcmp(file_name, PLC_SOCK_FILE_NAME) != 0) + { + if(CtlFileReadWithFilename(PLC_SOCK_FILE_NAME, CTL_FILE_LEN, file_buf) != EOK) + { + plc_error("Can't open file %s\n", file_name); + return; + } + } + else + { + return; + } + } + CtlParseJsonData(file_buf); + + memcpy(param->ip, ctl_file_param.ip, 4); + param->port = ctl_file_param.port; + param->cmd_num = ctl_file_param.cmd_num; + param->socket_type = ctl_file_param.tcp ? SOCK_STREAM : SOCK_DGRAM; + + for(int i = 0; i < param->cmd_num; i++) + { + TestPlcCmd[i].cmd_len = ctl_file_param.cmd_len[i]; + memcpy(TestPlcCmd[i].cmd, ctl_file_param.cmd[i], TestPlcCmd[i].cmd_len); + } + + plc_print("ip: %d.%d.%d.%d\n", param->ip[0], param->ip[1], param->ip[2], param->ip[3]); + plc_print("port: %d", param->port); + plc_print("tcp: %d", param->socket_type); + plc_print("cmd number: %d\n", param->cmd_num); + + for(int i = 0; i < param->cmd_num; i++) + { + plc_print_array("cmd", TestPlcCmd[i].cmd_len, TestPlcCmd[i].cmd); + } + free(file_buf); +} + +#endif + +void PlcCheckParam(int argc, char *argv[]) +{ + int i; + PlcSocketParamType *param = &plc_socket_demo_data; + plc_cmd_index = 0; + + for(i = 0; i < argc; i++) + { + char *str = argv[i]; + int is_tcp = 0; + char cmd_str[PLC_BIN_CMD_LEN] = {0}; + + plc_print("check %d %s\n", i, str); + +#if defined(MOUNT_SDCARD) && defined(LIB_USING_CJSON) + if(strncmp(str, "file", 4) == 0) + { + char file_name[CTL_FILE_NAME_LEN] = {0}; + if(sscanf(str, "file=%s", file_name) == EOF) + { + strcpy(file_name, PLC_SOCK_FILE_NAME); + } + plc_notice("get %s parameter file %s\n", str, file_name); + PlcGetParamFromFile(file_name); + return; + } +#endif + if(sscanf(str, "ip=%d.%d.%d.%d", + ¶m->ip[0], + ¶m->ip[1], + ¶m->ip[2], + ¶m->ip[3]) == 4) + { + plc_print("find ip %d %d %d %d\n", param->ip[0], param->ip[1], param->ip[2], param->ip[3]); + continue; + } + + if(sscanf(str, "port=%d", ¶m->port) == 1) + { + plc_print("find port %d\n", param->port); + continue; + } + + if(sscanf(str, "tcp=%d", &is_tcp) == 1) + { + plc_print("find tcp %d\n", is_tcp); + param->socket_type = is_tcp ? SOCK_STREAM:SOCK_DGRAM; + continue; + } + + if(sscanf(str, "plc=%d", ¶m->device_type) == 1) + { + plc_print("find device %d\n", param->device_type); + continue; + } + + if(sscanf(str, "cmd=%s", cmd_str) == 1) + { + plc_print("find cmd %s\n", cmd_str); + PlcGetParamCmd(cmd_str); + continue; + } + } + + if(argc >= 2) + { + if(sscanf(argv[1], "%d.%d.%d.%d:%d", + ¶m->ip[0], + ¶m->ip[1], + ¶m->ip[2], + ¶m->ip[3], + ¶m->port) != EOF) + { + return; + } + + if(sscanf(argv[1], "%d.%d.%d.%d", + ¶m->ip[0], + ¶m->ip[1], + ¶m->ip[2], + ¶m->ip[3]) != EOF) + { + return; + } + } + else + { + PlcShowUsage(); + } +} + +void PlcSocketTask(int argc, char *argv[]) +{ + int result = 0; + pthread_t th_id; + + pthread_attr_t attr; + attr.schedparam.sched_priority = LWIP_DEMO_TASK_PRIO; + attr.stacksize = LWIP_TASK_STACK_SIZE; + PlcSocketParamType *param = &plc_socket_demo_data; + + PlcCheckParam(argc, argv); + + lwip_config_net(lwip_ipaddr, lwip_netmask, param->ip); + PrivTaskCreate(&th_id, &attr, PlcSocketStart, param); +} + +SHELL_EXPORT_CMD(SHELL_CMD_PERMISSION(0) | SHELL_CMD_TYPE(SHELL_TYPE_CMD_MAIN) | SHELL_CMD_PARAM_NUM(3), + PlcSocket, PlcSocketTask, Test PLC Socket); + diff --git a/APP_Framework/Framework/control/plc/interoperability/socket/plc_socket.h b/APP_Framework/Framework/control/plc/interoperability/socket/plc_socket.h new file mode 100755 index 0000000..6b4ec9b --- /dev/null +++ b/APP_Framework/Framework/control/plc/interoperability/socket/plc_socket.h @@ -0,0 +1,66 @@ +/* + * Copyright (c) 2022 AIIT XUOS Lab + * XiUOS is licensed under Mulan PSL v2. + * You can use this software according to the terms and conditions of the Mulan PSL v2. + * You may obtain a copy of Mulan PSL v2 at: + * http://license.coscl.org.cn/MulanPSL2 + * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, + * EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, + * MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. + * See the Mulan PSL v2 for more details. + */ + +/** + * @file plc_socket.h + * @brief Demo for PLC socket communication function + * @version 1.0 + * @author AIIT XUOS Lab + * @date 2022.03.16 + */ + +#ifndef __PLC_SOCKET_H_ +#define __PLC_SOCKET_H_ + +#define PLC_BIN_CMD_LEN 512 + +// for plc socket test bin commands +typedef struct +{ + uint16_t delay_ms; + uint8_t cmd_len; + uint8_t cmd[PLC_BIN_CMD_LEN]; +}PlcBinCmdType; + +enum PlcDeviceType { + PLC_DEV_TYPE_OML = 0, + PLC_DEV_TYPE_IPC, + PLC_DEV_TYPE_BRL, + PLC_DEV_TYPE_SIEMENS, + PLC_DEV_TYPE_SIEMENS_1200, + PLC_DEV_TYPE_JF_IPC, + PLC_DEV_TYPE_HG, + /* ...... */ + PLC_DEV_TYPE_END, +}; + +#define PLC_IP_LEN 16 +#define PLC_DEV_NAME_LEN 32 +#define PLC_RECV_BUF_LEN CTL_FILE_LEN + +typedef struct PlcSocketParamStruct{ + char ip[PLC_IP_LEN]; + uint32_t port; + uint32_t device_type; //PlcDeviceType + uint32_t socket_type; //UDP or TCP + char device[PLC_DEV_NAME_LEN]; + uint32_t cmd_num; // command number + uint32_t recv_len; // receive length + uint8_t *recv_buf; // receive buffer +}PlcSocketParamType; + +//debug command +#define plc_print //KPrintf +#define plc_error KPrintf +#define plc_notice KPrintf + +#endif diff --git a/APP_Framework/Framework/control/plc/shared/Kconfig b/APP_Framework/Framework/control/plc/shared/Kconfig new file mode 100755 index 0000000..1ad617c --- /dev/null +++ b/APP_Framework/Framework/control/plc/shared/Kconfig @@ -0,0 +1,4 @@ +menuconfig USING_CONTROL_PLC_COMMON + bool "PLC common" + default y + diff --git a/APP_Framework/Framework/control/plc/shared/Makefile b/APP_Framework/Framework/control/plc/shared/Makefile new file mode 100755 index 0000000..1a56440 --- /dev/null +++ b/APP_Framework/Framework/control/plc/shared/Makefile @@ -0,0 +1,4 @@ +SRC_FILES := plc_device.c plc_channel.c plc_driver.c + +include $(KERNEL_ROOT)/compiler.mk + diff --git a/APP_Framework/Framework/control/plc/shared/plc_channel.c b/APP_Framework/Framework/control/plc/shared/plc_channel.c new file mode 100755 index 0000000..7959a42 --- /dev/null +++ b/APP_Framework/Framework/control/plc/shared/plc_channel.c @@ -0,0 +1,538 @@ +/* +* Copyright (c) 2020 AIIT XUOS Lab +* XiUOS is licensed under Mulan PSL v2. +* You can use this software according to the terms and conditions of the Mulan PSL v2. +* You may obtain a copy of Mulan PSL v2 at: +* http://license.coscl.org.cn/MulanPSL2 +* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, +* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, +* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. +* See the Mulan PSL v2 for more details. +*/ + +/** +* @file plc_ch.c +* @brief Support channel driver framework provide ch API version 1.0 +* @author AIIT XUOS Lab +* @date 2021-04-24 +*/ + +#include "string.h" +#include "plc_channel.h" +#include "plc_device.h" +#include "transform.h" + +DoublelistType ch_linklist; + +/*Create the ch linklist*/ +static void ChannelLinkInit(struct Channel *ch) +{ + static uint8 ch_link_flag = RET_FALSE; + + if(!ch_link_flag) { + AppInitDoubleList(&ch_linklist); + ch_link_flag = RET_TRUE; + ch->ch_link_flag = RET_TRUE; + } + + /*Create the driver of the ch linklist*/ + if(!ch->ch_drvlink_flag) { + AppInitDoubleList(&ch->ch_drvlink); + ch->ch_drvlink_flag = RET_TRUE; + } + + /*Create the hardware device of the ch linklist*/ + if(!ch->ch_devlink_flag) { + AppInitDoubleList(&ch->ch_devlink); + ch->ch_devlink_flag = RET_TRUE; + } +} + +static int ChannelMatchDrvDev(struct ChDrv *driver, struct ChDev *device) +{ + CHECK_CH_PARAM(driver); + CHECK_CH_PARAM(device); + + if(!strncmp(driver->owner_ch->ch_name, device->owner_ch->ch_name, NAME_NUM_MAX)) { + KPrintf("ChannelMatchDrvDev match successfully, ch name %s\n", driver->owner_ch->ch_name); + + driver->private_data = device->private_data;//driver get the device param + device->owner_ch->owner_driver = driver; + driver->owner_ch->owner_haldev = device; + + return EOK; + } + + return ERROR; +} + +/** +* @Description: support to obtain ch for a certain dev if necessary, then configure and init its drv +* @param ch - ch pointer +* @param dev - dev pointer +* @param drv_name - drv name +* @param config - ChConfigInfo pointer +* @return successful:EOK,failed:ERROR +*/ +int DeviceObtainChannel(struct Channel *ch, struct ChDev *dev, const char *drv_name, struct ChConfigInfo *cfg) +{ + CHECK_CH_PARAM(ch); + CHECK_CH_PARAM(dev); + + int32 ret = EOK; + + ret = PrivMutexObtain(&ch->ch_lock); + if(EOK != ret) { + KPrintf("DevObtainChannel ch_lock error %d!\n", ret); + return ret; + } + + if(ch->owner_haldev != dev) { + struct ChDrv *drv = ChannelFindDriver(ch, drv_name); + + cfg->configure_cmd = OPE_CFG; + drv->configure(drv, cfg); + + cfg->configure_cmd = OPE_INT; + drv->configure(drv, cfg); + + ch->owner_haldev = dev; + } + + return ret; +} + +/** +* @Description: support to register ch pointer with linklist +* @param ch - ch pointer +* @return successful:EOK,failed:NONE +*/ +int ChannelRegister(struct Channel *ch) +{ + int ret = EOK; + CHECK_CH_PARAM(ch); + + ch->match = ChannelMatchDrvDev; + + ChannelLinkInit(ch); + + PrivMutexCreate(&ch->ch_lock, NULL); + + AppDoubleListInsertNodeAfter(&ch_linklist, &(ch->ch_link)); + + return ret; +} + +/** +* @Description: support to release ch pointer in linklist +* @param ch - ch pointer +* @return successful:EOK,failed:NONE +*/ +int ChannelRelease(struct Channel *ch) +{ + CHECK_CH_PARAM(ch); + + PrivMutexAbandon(&ch->ch_lock); + + ch->ch_cnt = 0; + ch->driver_cnt = 0; + ch->haldev_cnt = 0; + + ch->ch_link_flag = RET_FALSE; + ch->ch_drvlink_flag = RET_FALSE; + ch->ch_devlink_flag = RET_FALSE; + + return EOK; +} + +/** +* @Description: support to unregister ch pointer and delete its linklist node +* @param ch - ch pointer +* @return successful:EOK,failed:NONE +*/ +int ChannelUnregister(struct Channel *ch) +{ + CHECK_CH_PARAM(ch); + + ch->ch_cnt--; + + AppDoubleListRmNode(&(ch->ch_link)); + + return EOK; +} + +/** +* @Description: support to register driver pointer to ch pointer +* @param ch - ch pointer +* @param driver - driver pointer +* @return successful:EOK,failed:NONE +*/ +int DriverRegisterToChannel(struct Channel *ch, struct ChDrv *driver) +{ + CHECK_CH_PARAM(ch); + CHECK_CH_PARAM(driver); + + driver->owner_ch = ch; + ch->driver_cnt++; + + AppDoubleListInsertNodeAfter(&ch->ch_drvlink, &(driver->driver_link)); + + return EOK; +} + +/** +* @Description: support to register dev pointer to ch pointer +* @param ch - ch pointer +* @param device - device pointer +* @return successful:EOK,failed:NONE +*/ +int DeviceRegisterToChannel(struct Channel *ch, struct ChDev *device) +{ + CHECK_CH_PARAM(ch); + CHECK_CH_PARAM(device); + + device->owner_ch = ch; + ch->haldev_cnt++; + + AppDoubleListInsertNodeAfter(&ch->ch_devlink, &(device->dev_link)); + + return EOK; +} + +/** +* @Description: support to delete driver pointer from ch pointer +* @param ch - ch pointer +* @param driver - driver pointer +* @return successful:EOK,failed:NONE +*/ +int DriverDeleteFromChannel(struct Channel *ch, struct ChDrv *driver) +{ + CHECK_CH_PARAM(ch); + CHECK_CH_PARAM(driver); + + ch->driver_cnt--; + + AppDoubleListRmNode(&(driver->driver_link)); + + free(driver); + + return EOK; +} + +/** +* @Description: support to delete dev pointer from ch pointer +* @param ch - ch pointer +* @param device - device pointer +* @return successful:EOK,failed:NONE +*/ +int DeviceDeleteFromChannel(struct Channel *ch, struct ChDev *device) +{ + CHECK_CH_PARAM(ch); + CHECK_CH_PARAM(device); + + ch->haldev_cnt--; + + AppDoubleListRmNode(&(device->dev_link)); + + free(device); + + return EOK; +} + +/** +* @Description: support to find ch pointer by ch name +* @param ch_name - ch name +* @return successful:ch pointer,failed:NONE +*/ +ChannelType ChannelFind(const char *ch_name) +{ + struct Channel *ch = NONE; + + DoublelistType *node = NONE; + DoublelistType *head = &ch_linklist; + + for (node = head->node_next; node != head; node = node->node_next) + { + ch = DOUBLE_LIST_ENTRY(node, struct Channel, ch_link); + if(!strcmp(ch->ch_name, ch_name)) { + return ch; + } + } + + KPrintf("ChannelFind cannot find the %s ch.return NULL\n", ch_name); + return NONE; +} + +/** +* @Description: support to find driver pointer of certain ch by driver name +* @param ch - ch pointer +* @param driver_name - driver name +* @return successful:EOK,failed:NONE +*/ +ChDrvType ChannelFindDriver(struct Channel *ch, const char *driver_name) +{ + CHECK_CH_PARAM(ch); + struct ChDrv *driver = NONE; + + DoublelistType *node = NONE; + DoublelistType *head = &ch->ch_drvlink; + + for (node = head->node_next; node != head; node = node->node_next) + { + driver = DOUBLE_LIST_ENTRY(node, struct ChDrv, driver_link); + if(!strcmp(driver->drv_name, driver_name)) { + return driver; + } + } + + KPrintf("ChannelFindDriver cannot find the %s driver.return NULL\n", driver_name); + return NONE; +} + +/** +* @Description: support to find device pointer of certain ch by device name +* @param ch - ch pointer +* @param device_name - device name +* @return successful:EOK,failed:NONE +*/ +ChDevType ChannelFindDevice(struct Channel *ch, const char *device_name) +{ + CHECK_CH_PARAM(ch); + struct ChDev *device = NONE; + + DoublelistType *node = NONE; + DoublelistType *head = &ch->ch_devlink; + + for (node = head->node_next; node != head; node = node->node_next) + { + device = DOUBLE_LIST_ENTRY(node, struct ChDev, dev_link); + + if(!strcmp(device->dev_name, device_name)) { + return device; + } + } + + KPrintf("ChannelFindDevice cannot find the %s device.return NULL\n", device_name); + return NONE; +} + +/** +* @Description: support to set dev receive function callback +* @param dev - dev pointer +* @param dev_recv_callback - callback function +* @return successful:EOK,failed:ERROR +*/ +uint32 ChannelDevRecvCallback(struct ChDev *dev, int (*dev_recv_callback) (void *dev, size_t length)) +{ + CHECK_CH_PARAM(dev ); + + dev->dev_recv_callback = dev_recv_callback; + + return EOK; +} + +/** +* @Description: support to open dev +* @param dev - dev pointer +* @return successful:EOK,failed:ERROR +*/ +uint32 ChannelDevOpen(struct ChDev *dev) +{ + CHECK_CH_PARAM(dev); + + int ret = EOK; + + if (dev->dev_done->open) { + ret = dev->dev_done->open(dev); + if(ret) { + KPrintf("ChannelDevOpen error ret %u\n", ret); + return ERROR; + } + } + + return ret; +} + +/** +* @Description: support to close dev +* @param dev - dev pointer +* @return successful:EOK,failed:ERROR +*/ +uint32 ChannelDevClose(struct ChDev *dev) +{ + CHECK_CH_PARAM(dev); + + int ret = EOK; + + if (dev->dev_done->close) { + ret = dev->dev_done->close(dev); + if(ret) { + KPrintf("ChannelDevClose error ret %u\n", ret); + return ERROR; + } + } + + return ret; +} + +/** +* @Description: support to write data to dev +* @param dev - dev pointer +* @param write_param - ChWriteParam +* @return successful:EOK,failed:NONE +*/ +uint32 ChannelDevWriteData(struct ChDev *dev, struct ChWriteParam *write_param) +{ + CHECK_CH_PARAM(dev); + + if (dev->dev_done->write) { + return dev->dev_done->write(dev, write_param); + } + + return EOK; +} + +/** +* @Description: support to read data from dev +* @param dev - dev pointer +* @param read_param - ChReadParam +* @return successful:EOK,failed:NONE +*/ +uint32 ChannelDevReadData(struct ChDev *dev, struct ChReadParam *read_param) +{ + CHECK_CH_PARAM(dev); + + if (dev->dev_done->read) { + return dev->dev_done->read(dev, read_param); + } + + return EOK; +} + +/** +* @Description: support to configure drv, include OPE_CFG and OPE_INT +* @param drv - drv pointer +* @param config - ChConfigInfo +* @return successful:EOK,failed:NONE +*/ +uint32 ChannelDrvConfigure(struct ChDrv *drv, struct ChConfigInfo *config) +{ + CHECK_CH_PARAM(drv); + CHECK_CH_PARAM(config); + + int ret = EOK; + + if (drv->configure) { + ret = drv->configure(drv, config); + if(ret) { + KPrintf("ChannelDrvCfg error, ret %u\n", ret); + return ERROR; + } + } + + return ret; +} + +int PlcChannelInit(struct PlcChannel* plc_ch, const char* ch_name) +{ + CHECK_CH_PARAM(plc_ch); + CHECK_CH_PARAM(ch_name); + int ret = EOK; + + if(CHANNEL_INSTALL != plc_ch->ch.ch_state) + { + strncpy(plc_ch->ch.ch_name, ch_name, NAME_NUM_MAX); + plc_ch->ch.ch_type = CH_PLC_TYPE; + plc_ch->ch.ch_state = CHANNEL_INSTALL; + plc_ch->ch.private_data = plc_ch->private_data; + ret = ChannelRegister(&plc_ch->ch); + + if(EOK != ret) + { + KPrintf("PlcChannelInit ChannelRegister error %u\n", ret); + return ret; + } + } + else + { + KPrintf("PlcChannelInit ChannelRegister channel has been register state %u\n", + plc_ch->ch.ch_state); + } + + return ret; +} + +int PlcDriverInit(struct PlcDriver* plc_driver, const char* driver_name) +{ + CHECK_CH_PARAM(plc_driver); + CHECK_CH_PARAM(driver_name); + int ret = EOK; + + if(CHDRV_INSTALL != plc_driver->driver.driver_state) + { + plc_driver->driver.driver_type = CHDRV_PLC_TYPE; + plc_driver->driver.driver_state = CHDRV_INSTALL; + strncpy(plc_driver->driver.drv_name, driver_name, NAME_NUM_MAX); + plc_driver->driver.configure = plc_driver->configure; + ret = PlcDriverRegister(&plc_driver->driver); + + if(EOK != ret) + { + KPrintf("PlcDriverInit DriverRegister error %u\n", ret); + return ret; + } + } + else + { + KPrintf("PlcDriverInit Driver %s has been register state %u\n", + driver_name, plc_driver->driver.driver_state); + } + + return ret; +} + +int PlcReleaseChannel(struct PlcChannel* plc_ch) +{ + CHECK_CH_PARAM(plc_ch); + return ChannelRelease(&plc_ch->ch); +} + +int PlcDriverAttachToChannel(const char* drv_name, const char* ch_name) +{ + CHECK_CH_PARAM(drv_name); + CHECK_CH_PARAM(ch_name); + int ret = EOK; + struct Channel* ch; + struct ChDrv* driver; + ch = ChannelFind(ch_name); + + if(NONE == ch) + { + KPrintf("PlcDriverAttachToChannel find plc channel error!name %s\n", ch_name); + return ERROR; + } + + if(CH_PLC_TYPE == ch->ch_type) + { + driver = PlcDriverFind(drv_name, CHDRV_PLC_TYPE); + + if(NONE == driver) + { + KPrintf("PlcDriverAttachToChannel find plc driver error!name %s\n", drv_name); + return ERROR; + } + + if(CHDRV_PLC_TYPE == driver->driver_type) + { + ret = DriverRegisterToChannel(ch, driver); + + if(EOK != ret) + { + KPrintf("PlcDriverAttachToChannel DriverRegisterToBus error %u\n", ret); + return ERROR; + } + } + } + + return ret; +} diff --git a/APP_Framework/Framework/control/plc/shared/plc_channel.h b/APP_Framework/Framework/control/plc/shared/plc_channel.h new file mode 100755 index 0000000..9d00756 --- /dev/null +++ b/APP_Framework/Framework/control/plc/shared/plc_channel.h @@ -0,0 +1,266 @@ +/* +* Copyright (c) 2022 AIIT XUOS Lab +* XiUOS is licensed under Mulan PSL v2. +* You can use this software according to the terms and conditions of the Mulan PSL v2. +* You may obtain a copy of Mulan PSL v2 at: +* http://license.coscl.org.cn/MulanPSL2 +* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, +* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, +* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. +* See the Mulan PSL v2 for more details. +*/ + +/** +* @file plc_channel.h +* @brief define channel driver framework function and common API +* @version 1.0 +* @author AIIT XUOS Lab +* @date 2022-03-01 +*/ + +#ifndef __PLC_CHANNEL_H_ +#define __PLC_CHANNEL_H_ + +#include "list.h" + +#ifdef __cplusplus +extern "C" { +#endif + +#define OPE_INT 0x0000 +#define OPE_CFG 0x0001 + +#define OPER_WDT_SET_TIMEOUT 0x0002 +#define OPER_WDT_KEEPALIVE 0x0003 + +#define CHECK_CH_PARAM(param) \ +do \ +{ \ + if(param == NONE) { \ + KPrintf("PARAM CHECK FAILED ...%s %d %s is NULL.\n",__FUNCTION__,__LINE__,#param); \ + while(RET_TRUE); \ + } \ +}while (0) + +typedef struct Channel *ChannelType; +typedef struct ChDev *ChDevType; +typedef struct ChDrv *ChDrvType; + +/* need to add new ch type in ../tool/shell/letter-shell/cmd.c, ensure ShowBus cmd supported*/ +enum ChType_e +{ + CH_PLC_TYPE, + CH_END_TYPE, +}; + +enum ChState_e +{ + CHANNEL_INIT = 0, + CHANNEL_INSTALL, + CHANNEL_UNINSTALL, +}; + +enum ChDevType_e +{ + CHDEV_PLC_TYPE, + CHDEV_END_TYPE, +}; + +enum ChDevState_e +{ + CHDEV_INIT = 0, + CHDEV_INSTALL, + CHDEV_UNINSTALL, +}; + +enum ChDrvType_e +{ + CHDRV_PLC_TYPE, + CHDRV_END_TYPE, +}; + +enum ChDrvState_e +{ + CHDRV_INIT = 0, + CHDRV_INSTALL, + CHDRV_UNINSTALL, +}; + +struct ChConfigInfo +{ + int configure_cmd; + void *private_data; +}; + +struct ChReadParam +{ + uint32 pos; + void* buffer; + size_t size; + size_t read_length; +}; + +struct ChWriteParam +{ + uint32 pos; + const void* buffer; + size_t size; +}; + +struct ChHalDevDone +{ + uint32 (*open) (void *dev); + uint32 (*close) (void *dev); + uint32 (*write) (void *dev, struct ChWriteParam *write_param); + uint32 (*read) (void *dev, struct ChReadParam *read_param); +}; + +struct ChDev +{ + int8 dev_name[NAME_NUM_MAX]; + enum ChDevType_e dev_type; + enum ChDevState_e dev_state; + + const struct ChHalDevDone *dev_done; + + int (*dev_recv_callback) (void *dev, size_t length); + + struct Channel *owner_ch; + void *private_data; + + int32 dev_sem; + + DoublelistType dev_link; +}; + +struct ChDrv +{ + int8 drv_name[NAME_NUM_MAX]; + enum ChDrvType_e driver_type; + enum ChDrvState_e driver_state; + + uint32 (*configure)(void *drv, struct ChConfigInfo *config); + + struct Channel *owner_ch; + void *private_data; + + DoublelistType driver_link; +}; + +struct Channel +{ + int8 ch_name[NAME_NUM_MAX]; + enum ChType_e ch_type; + enum ChState_e ch_state; + + int32 (*match)(struct ChDrv *driver, struct ChDev *device); + + int ch_lock; + + struct ChDev *owner_haldev; + struct ChDrv *owner_driver; + + void *private_data; + + /*manage the drv of the channel*/ + uint8 driver_cnt; + uint8 ch_drvlink_flag; + DoublelistType ch_drvlink; + + /*manage the dev of the channel*/ + uint8 haldev_cnt; + uint8 ch_devlink_flag; + DoublelistType ch_devlink; + + uint8 ch_cnt; + uint8 ch_link_flag; + DoublelistType ch_link; +}; + +/*Register the BUS,manage with the double linklist*/ +int ChannelRegister(struct Channel *ch); + +/*Release the BUS framework*/ +int ChannelRelease(struct Channel *ch); + +/*Unregister a certain kind of BUS*/ +int ChannelUnregister(struct Channel *ch); + +/*Register the driver to the channel*/ +int DriverRegisterToChannel(struct Channel *ch, struct ChDrv *driver); + +/*Register the device to the channel*/ +int DeviceRegisterToChannel(struct Channel *ch, struct ChDev *device); + +/*Delete the driver from the channel*/ +int DriverDeleteFromChannel(struct Channel *ch, struct ChDrv *driver); + +/*Delete the device from the channel*/ +int DeviceDeleteFromChannel(struct Channel *ch, struct ChDev *device); + +/*Find the ch with ch name*/ +ChannelType ChannelFind(const char *ch_name); + +/*Find the driver of cetain channel*/ +ChDrvType ChannelFindDriver(struct Channel *ch, const char *driver_name); + +/*Find the device of certain channel*/ +ChDevType ChannelFindDevice(struct Channel *ch, const char *device_name); + +/*Dev receive data callback function*/ +uint32 ChannelDevRecvCallback(struct ChDev *dev, int (*dev_recv_callback) (void *dev, size_t length)); + +/*Open the device of the channel*/ +uint32 ChannelDevOpen(struct ChDev *dev); + +/*Close the device of the channel*/ +uint32 ChannelDevClose(struct ChDev *dev); + +/*Write data to the device*/ +uint32 ChannelDevWriteData(struct ChDev *dev, struct ChWriteParam *write_param); + +/*Read data from the device*/ +uint32 ChannelDevReadData(struct ChDev *dev, struct ChReadParam *read_param); + +/*Configure the driver of the channel*/ +uint32 ChannelDrvConfigure(struct ChDrv *drv, struct ChConfigInfo *config); + +/*Obtain the ch using a certain dev*/ +int DeviceObtainChannel(struct Channel *ch, struct ChDev *dev, const char *drv_name, struct ChConfigInfo *config); + + +struct PlcDriver +{ + struct ChDrv driver; + uint32 (*configure) (void *drv, struct ChConfigInfo *cfg); +}; + +struct PlcChannel +{ + struct Channel ch; + void *private_data; +}; + +/*Register the plc bus*/ +int PlcChannelInit(struct PlcChannel *plc_ch, const char *ch_name); + +/*Register the plc driver*/ +int PlcDriverInit(struct PlcDriver *plc_driver, const char *driver_name); + +/*Release the plc device*/ +int PlcReleaseChannel(struct PlcChannel *plc_ch); + +/*Register the plc driver to the plc bus*/ +int PlcDriverAttachToChannel(const char *drv_name, const char *ch_name); + +/*Register the driver, manage with the double linklist*/ +int PlcDriverRegister(struct ChDrv *driver); + +/*Find the register driver*/ +ChDrvType PlcDriverFind(const char *drv_name, enum ChDrvType_e drv_type); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/APP_Framework/Framework/control/plc/shared/plc_device.c b/APP_Framework/Framework/control/plc/shared/plc_device.c new file mode 100755 index 0000000..8860aea --- /dev/null +++ b/APP_Framework/Framework/control/plc/shared/plc_device.c @@ -0,0 +1,189 @@ +/* +* Copyright (c) 2021 AIIT XUOS Lab +* XiUOS is licensed under Mulan PSL v2. +* You can use this software according to the terms and conditions of the Mulan PSL v2. +* You may obtain a copy of Mulan PSL v2 at: +* http://license.coscl.org.cn/MulanPSL2 +* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, +* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, +* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. +* See the Mulan PSL v2 for more details. +*/ + +/** + * @file plc.c + * @brief plc relative activities + * @version 1.0 + * @author AIIT XUOS Lab + * @date 2021.12.15 + */ + +#include "ua_api.h" +#include "plc_channel.h" +#include "plc_device.h" + +DoublelistType plcdev_list; + +/******************************************************************************/ + +/*Create the plc device linklist*/ +static void PlcDeviceLinkInit() +{ + AppInitDoubleList(&plcdev_list); +} + +static int PlcDeviceOpen(void *dev) +{ + CHECK_CH_PARAM(dev); + + struct PlcDevice *plc_dev = (struct PlcDevice *)dev; + + if(plc_dev->net == PLC_IND_ENET_OPCUA) + { + return UaDevOpen(plc_dev->priv_data); + } + + return EOK; +} + +static void PlcDeviceClose(void *dev) +{ + CHECK_CH_PARAM(dev); + + struct PlcDevice *plc_dev = (struct PlcDevice *)dev; + + if(plc_dev->net == PLC_IND_ENET_OPCUA) + { + UaDevClose(plc_dev->priv_data); + } +} + +static int PlcDeviceWrite(void *dev, const void *buf, size_t len) +{ + CHECK_CH_PARAM(dev); + + int ret; + struct PlcDevice *plc_dev = (struct PlcDevice *)dev; + + if(plc_dev->net == PLC_IND_ENET_OPCUA) + { + ret = UaDevWrite(plc_dev->priv_data, buf, len); + } + + return ret; +} + +static int PlcDeviceRead(void *dev, void *buf, size_t len) +{ + CHECK_CH_PARAM(dev); + CHECK_CH_PARAM(buf); + + int ret; + struct PlcDevice *plc_dev = (struct PlcDevice *)dev; + + if(plc_dev->net == PLC_IND_ENET_OPCUA) + { + ret = UaDevRead(plc_dev->priv_data, buf, len); + } + + return ret; +} + +static struct PlcOps plc_done = +{ + .open = PlcDeviceOpen, + .close = PlcDeviceClose, + .write = PlcDeviceWrite, + .read = PlcDeviceRead, +}; + +/* find PLC device with device name */ +struct ChDev *PlcDevFind(const char *dev_name) +{ + CHECK_CH_PARAM(dev_name); + + struct PlcDevice *device = NONE; + struct ChDev *haldev = NONE; + + DoublelistType *node = NONE; + DoublelistType *head = &plcdev_list; + + for (node = head->node_next; node != head; node = node->node_next) { + device = DOUBLE_LIST_ENTRY(node, struct PlcDevice, link); + if (!strcmp(device->name, dev_name)) { + haldev = &device->haldev; + return haldev; + } + } + + plc_print("plc: [%s] cannot find the %s device\n", __func__, dev_name); + return NONE; +} + +int PlcDevRegister(struct PlcDevice *plc_device, void *plc_param, const char *device_name) +{ + CHECK_CH_PARAM(plc_device); + CHECK_CH_PARAM(device_name); + + int ret = EOK; + static uint8_t dev_link_flag = 0; + + if (!dev_link_flag) { + PlcDeviceLinkInit(); + dev_link_flag = 1; + } + + if (CHDEV_INSTALL != plc_device->state) { + strncpy(plc_device->haldev.dev_name, device_name, NAME_NUM_MAX); + plc_device->haldev.dev_type = CHDEV_PLC_TYPE; + plc_device->haldev.dev_state = CHDEV_INSTALL; + + strncpy(plc_device->name, device_name, strlen(device_name)); + plc_device->ops = &plc_done; + + AppDoubleListInsertNodeAfter(&plcdev_list, &(plc_device->link)); + plc_device->state = CHDEV_INSTALL; + + } else { + KPrintf("PlcDevRegister device %s has been register state%u\n", device_name, plc_device->state); + ret = ERROR; + } + + return ret; +} + +int PlcDeviceAttachToChannel(const char *dev_name, const char *ch_name) +{ + CHECK_CH_PARAM(dev_name); + CHECK_CH_PARAM(ch_name); + + int ret = EOK; + + struct Channel *ch; + struct ChDev *device; + + ch = ChannelFind(ch_name); + if (NONE == ch) { + KPrintf("PlcDeviceAttachToChannel find plc ch error!name %s\n", ch_name); + return ERROR; + } + + if (CH_PLC_TYPE == ch->ch_type) { + device = PlcDevFind(dev_name); + if (NONE == device) { + KPrintf("PlcDeviceAttachToChannel find plc device %s error!\n", dev_name); + return ERROR; + } + + if (CHDEV_PLC_TYPE == device->dev_type) { + ret = DeviceRegisterToChannel(ch, device); + if (EOK != ret) { + KPrintf("PlcDeviceAttachToChannel DeviceRegisterToChannel error %u\n", ret); + return ERROR; + } + } + } + + return EOK; +} + diff --git a/APP_Framework/Framework/control/plc/shared/plc_device.h b/APP_Framework/Framework/control/plc/shared/plc_device.h new file mode 100755 index 0000000..b8c57d4 --- /dev/null +++ b/APP_Framework/Framework/control/plc/shared/plc_device.h @@ -0,0 +1,153 @@ +/* +* Copyright (c) 2022 AIIT XUOS Lab +* XiUOS is licensed under Mulan PSL v2. +* You can use this software according to the terms and conditions of the Mulan PSL v2. +* You may obtain a copy of Mulan PSL v2 at: +* http://license.coscl.org.cn/MulanPSL2 +* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, +* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, +* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. +* See the Mulan PSL v2 for more details. +*/ + +/** + * @file plc_dev.h + * @brief plc relative definition and structure + * @version 1.0 + * @author AIIT XUOS Lab + * @date 2022-01-24 + */ + +#ifndef __PLC_DEV_H_ +#define __PLC_DEV_H_ + +#include "list.h" +#include "plc_channel.h" + +#undef open +#undef close +#undef read +#undef write + +#define IP_ADDR_SIZE 32 +#define PLC_NAME_SIZE 32 + +// PLC device information +typedef struct PlcInfo { + uint32_t ability; // PLC ability + uint32_t id; // PLC Device ID + uint32_t soft_version; // software version + uint32_t hard_version; // hardware version + uint32_t date; // manufact date + const char *vendor; // vendor + const char *model; // model + const char *product; // product +}PlcInfoType; + +enum PlcSerialType { + PLC_SERIAL_232, + PLC_SERIAL_485, + PLC_SERIAL_CAN +}; + +union PlcCfg { + struct { + char ip_addr[IP_ADDR_SIZE]; + uint32_t ip_port; + } PlcIpCfg; + struct { + enum PlcSerialType serial_type; + char station_id; + char serial_port; + } PlcSerialCfg; +}; + +struct PlcDevice; + +// operation API +typedef struct PlcOps { + int (*open)(void *dev); // open and connect PLC device + void (*close)(void* dev); // close and disconnect PLC device + int (*read)(void* dev, void *buf, size_t len); // read data from PLC + int (*write)(void* dev, const void *buf, size_t len); // write data from PLC + int (*ioctl)(void* dev, int cmd, void *arg); // send control command to PLC +}PlcOpsType; + +enum PlcCtlType { + PLC_CTRL_TYPE_HSC, + PLC_CTRL_TYPE_PID, + PLC_CTRL_TYPE_PHASING +}; + +#define PLC_ABILITY_HSC ((uint32_t)(1 << PLC_CTRL_TYPE_HSC)) +#define PLC_ABILITY_PID ((uint32_t)(1 << PLC_CTRL_TYPE_PID)) +#define PLC_ABILITY_PHASING ((uint32_t)(1 << PLC_CTRL_TYPE_PHASING)) + +enum PlcIndHybridNet +{ + // PLC Field Bus + PLC_IND_FIELD_MODBUS_485, + PLC_IND_FIELD_PROFIBUS, + PLC_IND_FIELD_CANOPEN, + PLC_IND_FIELD_DEVICENET, + PLC_IND_FIELD_CONTROLNET, + + // PLC ETHERNET + PLC_IND_ENET_ETHERNET_IP, + PLC_IND_ENET_PROFINET, + PLC_IND_ENET_ETHERCAT, + PLC_IND_ENET_SERCOS, + PLC_IND_ENET_OPCUA, + + // PLC wireless net + PLC_IND_WIRELESS +}; + +enum PlcTransType +{ + PLC_TRANS_TCP, + PLC_TRANS_UDP, + PLC_TRANS_SERIAL +}; + +//communication interface +typedef struct PlcInterface +{ + char ip_addr[IP_ADDR_SIZE]; + char attrib; +}PlcInterfaceType; + +// identify PLC device +typedef struct PlcDevice { + struct ChDev haldev; /* hardware device driver for channel */ + enum ChDevState_e state; + + char name[PLC_NAME_SIZE]; /* name of the device */ + enum PlcCtlType type; /* PLC Control Type */ + enum PlcIndHybridNet net; + enum PlcTransType trans; + + struct PlcInfo info;/* Plc info, such as vendor name and model name */ + union PlcCfg cfg; + struct PlcOps *ops; /* filesystem-like APIs for data transferring */ + struct PlcInterface interface; /* protocols used for transferring data from program to plc */ + + void *priv_data; /* private data for different PLC*/ + DoublelistType link;/* link list node */ +}PlcDeviceType; + +typedef struct PlcCtrlParam { + void *node_id; // for node ID + int value; +}PlcCtrlParamType; + +#define plc_print KPrintf + +/******************************************************************************/ + +int PlcDevRegister(struct PlcDevice *plc_device, void *plc_param, const char *device_name); +int PlcDeviceAttachToChannel(const char *dev_name, const char *ch_name); + +/******************************************************************************/ + +#endif diff --git a/APP_Framework/Framework/control/plc/shared/plc_driver.c b/APP_Framework/Framework/control/plc/shared/plc_driver.c new file mode 100755 index 0000000..358856b --- /dev/null +++ b/APP_Framework/Framework/control/plc/shared/plc_driver.c @@ -0,0 +1,71 @@ +/* +* Copyright (c) 2020 AIIT XUOS Lab +* XiUOS is licensed under Mulan PSL v2. +* You can use this software according to the terms and conditions of the Mulan PSL v2. +* You may obtain a copy of Mulan PSL v2 at: +* http://license.coscl.org.cn/MulanPSL2 +* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, +* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, +* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. +* See the Mulan PSL v2 for more details. +*/ + +/** +* @file drv_plc.c +* @brief register plc drv function using bus driver framework +* @version 1.0 +* @author AIIT XUOS Lab +* @date 2022-01-24 +*/ + +#include "transform.h" +#include "plc_channel.h" +#include "plc_device.h" + +static DoublelistType plcdrv_linklist; + +/******************************************************************************/ + +/*Create the driver linklist*/ +static void PlcDrvLinkInit() +{ + AppInitDoubleList(&plcdrv_linklist); +} + +ChDrvType PlcDriverFind(const char *drv_name, enum ChDrvType_e drv_type) +{ + CHECK_CH_PARAM(drv_name); + + struct ChDrv *driver = NONE; + + DoublelistType *node = NONE; + DoublelistType *head = &plcdrv_linklist; + + for (node = head->node_next; node != head; node = node->node_next) { + driver = DOUBLE_LIST_ENTRY(node, struct ChDrv, driver_link); + if ((!strcmp(driver->drv_name, drv_name)) && (drv_type == driver->driver_type)) { + return driver; + } + } + + KPrintf("PlcDriverFind cannot find the %s driver.return NULL\n", drv_name); + return NONE; +} + +int PlcDriverRegister(struct ChDrv *driver) +{ + CHECK_CH_PARAM(driver); + + int ret = EOK; + static uint8_t driver_link_flag = 0; + + if (!driver_link_flag) { + PlcDrvLinkInit(); + driver_link_flag = 1; + } + + AppDoubleListInsertNodeAfter(&plcdrv_linklist, &(driver->driver_link)); + + return ret; +} + diff --git a/APP_Framework/Framework/control/shared/Makefile b/APP_Framework/Framework/control/shared/Makefile new file mode 100755 index 0000000..633191b --- /dev/null +++ b/APP_Framework/Framework/control/shared/Makefile @@ -0,0 +1,8 @@ +SRC_FILES := control.c + +ifeq ($(CONFIG_MOUNT_SDCARD),y) + SRC_FILES += control_file.c +endif + +include $(KERNEL_ROOT)/compiler.mk + diff --git a/APP_Framework/Framework/control/shared/config.json b/APP_Framework/Framework/control/shared/config.json new file mode 100755 index 0000000..05b79a6 --- /dev/null +++ b/APP_Framework/Framework/control/shared/config.json @@ -0,0 +1,38 @@ +{ +"siemens plc": +{ + "device type": "PLC", + "control type": "HSC", + "info": + { + "plc ability" : 1, + "plc device id": 1, + "soft version" : 1, + "hardware version": 1, + "date": "2022-1-28", + "vendor": "siemens", + "model":"S300" + }, + + "serial config": + { + "serial type":"485", + "station id" : "station1", + "serial port" : 1 + }, + + "network config": + { + "ip addr" : "192.168.250.5", + "ip port" : 4840 + }, + + "interface": + { + "inhybridnet":"OPCUA", + "transport":"TCP", + "ip address": "192.168.250.5", + "attribute" : "1" + } +} +} diff --git a/APP_Framework/Framework/control/shared/control.c b/APP_Framework/Framework/control/shared/control.c new file mode 100755 index 0000000..2d86a2d --- /dev/null +++ b/APP_Framework/Framework/control/shared/control.c @@ -0,0 +1,21 @@ + +#include "cJSON.h" + + + +void control_init(void) +{ + +} + +void control_read_file() +{ + + + + +} + + + + diff --git a/APP_Framework/Framework/control/shared/control_file.c b/APP_Framework/Framework/control/shared/control_file.c new file mode 100755 index 0000000..3b383c7 --- /dev/null +++ b/APP_Framework/Framework/control/shared/control_file.c @@ -0,0 +1,213 @@ +/* +* Copyright (c) 2022 AIIT XUOS Lab +* XiUOS is licensed under Mulan PSL v2. +* You can use this software according to the terms and conditions of the Mulan PSL v2. +* You may obtain a copy of Mulan PSL v2 at: +* http://license.coscl.org.cn/MulanPSL2 +* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, +* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, +* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. +* See the Mulan PSL v2 for more details. +*/ + +/** + * @file control_file.c + * @brief control relative file operation + * @version 1.0 + * @author AIIT XUOS Lab + * @date 2022-03-17 + */ + +#include +#include "cJSON.h" +#include "transform.h" +#include "control_file.h" + +//json file parameter for PLC socket communication as below: +//{ +// "ip": "192.168.250.6", +// "port": 102, +// "cmd": [3, 0, 0, 22, 17, 224, 0, 0, 2, 200, 0, 193, 2, 2, 1, 194, 2, 2, 1, 192, 1, 10], +// "cmd1": [3, 0, 0, 25, 2, 240, 128, 50, 1, 0, 0, 0, 13, 0, 8, 0, 0, 240, 0, 0, 1, 0, 1, 0, 240], \r\n" \ +// "cmd2": [3, 0, 0, 31, 2, 240, 128, 50, 1, 0, 0, 51, 1, 0, 14, 0, 0, 4, 1, 18, 10, 16, 2, 0, 210, 0, 52, 132, 0, 0, 0]\r\n" \ +//}" + +#define TEST_PLC_JSON_TXT \ +"{ \r\n"\ +" \"ip\": \"192.168.250.6\", \r\n"\ +" \"port\": 102, \r\n"\ +" \"tcp\": 1, \r\n"\ +" \"cmd\": [3, 0, 0, 22, 17, 224, 0, 0, 2, 200, 0, 193, 2, 2, 1, 194, 2, 2, 1, 192, 1, 10], \r\n"\ +" \"cmd1\": [3, 0, 0, 25, 2, 240, 128, 50, 1, 0, 0, 0, 13, 0, 8, 0, 0, 240, 0, 0, 1, 0, 1, 0, 240], \r\n" \ +" \"cmd2\": [3, 0, 0, 31, 2, 240, 128, 50, 1, 0, 0, 51, 1, 0, 14, 0, 0, 4, 1, 18, 10, 16, 2, 0, 210, 0, 52, 132, 0, 0, 0]\r\n" \ +"}" + + +CtlPlcSockParamType ctl_file_param; + +FILE *CtlFileInit(char *file) +{ + FILE *fd = NULL; + +#ifdef MOUNT_SDCARD + // SD card mount flag 1: OK + if(sd_mount_flag == 0) + { + ctl_error("SD card mount failed\n"); + return NULL; + } + + fd = fopen(file, "a+"); + if(fd == NULL) + { + ctl_error("open file %s failed\n", file); + } + +#endif + return fd; +} + +void CtlFileClose(FILE *fd) +{ + fclose(fd); +} + +void CtlFileRead(FILE *fd, int size, char *buf) +{ + fseek(fd, 0, SEEK_SET); + fread(buf, size, 1, fd); + ctl_print("read file %d: %.100s\n", size, buf); +} + +void CtlFileWrite(FILE *fd, int size, char *buf) +{ + size_t write_size = 0; + write_size = fwrite(buf, strlen(buf) + 1, 1, fd); + ctl_print("write size %d: %s\n", size, buf); +} + +int CtlFileReadWithFilename(char *file, int size, char *buf) +{ + FILE *fd; + fd = fopen(file, "r"); + if(fd == NULL) + { + ctl_error("open file %s failed\n", file); + return EEMPTY; + } + + fseek(fd, 0, SEEK_SET); + fread(buf, size, 1, fd); + ctl_print("read file %d: %.100s\n", size, buf); + return EOK; +} + +void CtlCreateFileTest(void) +{ + FILE *fd = CtlFileInit(PLC_SOCK_FILE_NAME); + if(fd == NULL) + return; + char *file_buf = TEST_PLC_JSON_TXT; + CtlFileWrite(fd, strlen(file_buf), file_buf); + CtlFileClose(fd); +} + +SHELL_EXPORT_CMD(SHELL_CMD_PERMISSION(0) | SHELL_CMD_TYPE(SHELL_TYPE_CMD_MAIN) | SHELL_CMD_PARAM_NUM(0), + CtlCreateFile, CtlCreateFileTest, Test control file); + +#ifdef LIB_USING_CJSON + +void CtlParseJsonArray(cJSON *dat, int *cmd_len, char *cmd) +{ + int len, i; + if(cJSON_IsArray(dat)) + { + len = cJSON_GetArraySize(dat); + ctl_print("json cmd %d\n", len); + + for(i = 0; i < len; i++) + { + cJSON *cmd_val = cJSON_GetArrayItem(dat, i); + if(NULL == cmd_val) + continue; + ctl_print("0x%x ", cmd_val->valueint); + cmd[i] = cmd_val->valueint; + } + *cmd_len = len; + ctl_print("\n"); + } +} + +void CtlParseJsonData(char *buf) +{ + cJSON *file_dat = NULL; + cJSON *ip_dat = NULL; + cJSON *port_dat = NULL; + cJSON *tcp_dat = NULL; + cJSON *cmd_dat = NULL; + char cmd_title[10] = {"cmd"}; + CtlPlcSockParamType *file_param = &ctl_file_param; + + file_dat = cJSON_Parse(buf); + if(file_dat == NULL) + { + ctl_error("ctrl parse failed\n"); + return; + } + + ip_dat = cJSON_GetObjectItem(file_dat, "ip"); + port_dat = cJSON_GetObjectItem(file_dat, "port"); + tcp_dat = cJSON_GetObjectItem(file_dat, "tcp"); + + ctl_print(" ip : %s\n", ip_dat->valuestring); + sscanf(ip_dat->valuestring, "%d.%d.%d.%d", &file_param->ip[0], + &file_param->ip[1], + &file_param->ip[2], + &file_param->ip[3]); + + ctl_print(" port: %s %d\n", ip_dat->string, port_dat->valueint); + file_param->port = port_dat->valueint; + file_param->tcp = tcp_dat->valueint; + file_param->cmd_num = 0; + + for(int i = 0; i < CTL_CMD_NUM; i++) + { + cmd_dat = cJSON_GetObjectItem(file_dat, cmd_title); + if(!cmd_dat) + break; + CtlParseJsonArray(cmd_dat, &file_param->cmd_len[i], file_param->cmd[i]); + snprintf(cmd_title, sizeof(cmd_title), "cmd%d", ++file_param->cmd_num); + } + + cJSON_Delete(file_dat); +} + +void CtlParseFileTest(void) +{ + //for PLC socket parameter file + FILE *fd = CtlFileInit(PLC_SOCK_FILE_NAME); + if(fd == NULL) + { + ctl_error("ctl get file %s failed\n", PLC_SOCK_FILE_NAME); + return; + } + + char *file_buf = malloc(CTL_FILE_LEN); + + if(file_buf == NULL) + { + ctl_error("ctl malloc failed\n"); + return; + } + memset(file_buf, 0, CTL_FILE_LEN); + CtlFileRead(fd, CTL_FILE_LEN, file_buf); + CtlFileClose(fd); + CtlParseJsonData(file_buf); + free(file_buf); +} + +SHELL_EXPORT_CMD(SHELL_CMD_PERMISSION(0) | SHELL_CMD_TYPE(SHELL_TYPE_CMD_MAIN) | SHELL_CMD_PARAM_NUM(0), + CtlParseFile, CtlParseFileTest, Parse control file); + +#endif + diff --git a/APP_Framework/Framework/control/shared/control_file.h b/APP_Framework/Framework/control/shared/control_file.h new file mode 100755 index 0000000..9f8cda1 --- /dev/null +++ b/APP_Framework/Framework/control/shared/control_file.h @@ -0,0 +1,59 @@ +/* +* Copyright (c) 2022 AIIT XUOS Lab +* XiUOS is licensed under Mulan PSL v2. +* You can use this software according to the terms and conditions of the Mulan PSL v2. +* You may obtain a copy of Mulan PSL v2 at: +* http://license.coscl.org.cn/MulanPSL2 +* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, +* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, +* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. +* See the Mulan PSL v2 for more details. +*/ + +/** + * @file control_file.h + * @brief control relative API + * @version 1.0 + * @author AIIT XUOS Lab + * @date 2022-03-17 + */ + +#ifndef __CONTROL_FILE_H_ +#define __CONTROL_FILE_H_ + +#define CTL_FILE_LEN 1000 // control file size +#define CTL_CMD_NUM 10 // support command number +#define CTL_CMD_LEN 100 // control command length +#define CTL_IP_LEN 32 // IP address length +#define CTL_FILE_NAME_LEN 100 // file name length + +#define PLC_SOCK_FILE_NAME "/plc/socket_param.json" + +#define ctl_print //KPrintf +#define ctl_error KPrintf + +// for running plc socket +typedef struct CtlPlcSockParamStruct +{ + char ip[CTL_IP_LEN]; + int port; + int tcp; // 1: TCP 0: UDP + int cmd_num; //command number + int cmd_len[CTL_CMD_NUM]; // command length + char cmd[CTL_CMD_NUM][CTL_CMD_LEN]; +}CtlPlcSockParamType; + +extern CtlPlcSockParamType ctl_file_param; +extern int sd_mount_flag; + +FILE *CtlFileInit(char *file); +void CtlFileClose(FILE *fd); +void CtlFileRead(FILE *fd, int size, char *buf); +void CtlFileWrite(FILE *fd, int size, char *buf); +int CtlFileReadWithFilename(char *file_name, int size, char *buf); + +#ifdef LIB_USING_CJSON +void CtlParseJsonData(char *buf); +#endif +#endif + diff --git a/APP_Framework/Framework/knowing/Kconfig b/APP_Framework/Framework/knowing/Kconfig new file mode 100644 index 0000000..d4324bf --- /dev/null +++ b/APP_Framework/Framework/knowing/Kconfig @@ -0,0 +1,14 @@ +menuconfig SUPPORT_KNOWING_FRAMEWORK + bool "support knowing framework" + default n + select TRANSFORM_LAYER_ATTRIUBUTE + +if SUPPORT_KNOWING_FRAMEWORK + source "$APP_DIR/Framework/knowing/tensorflow-lite/Kconfig" + source "$APP_DIR/Framework/knowing/filter/Kconfig" + source "$APP_DIR/Framework/knowing/ota/Kconfig" + source "$APP_DIR/Framework/knowing/image_processing/Kconfig" + source "$APP_DIR/Framework/knowing/cmsis_5/Kconfig" + source "$APP_DIR/Framework/knowing/kpu/Kconfig" + source "$APP_DIR/Framework/knowing/nnom/Kconfig" +endif diff --git a/APP_Framework/Framework/knowing/Makefile b/APP_Framework/Framework/knowing/Makefile new file mode 100644 index 0000000..d12b243 --- /dev/null +++ b/APP_Framework/Framework/knowing/Makefile @@ -0,0 +1,4 @@ +SRC_DIR := tensorflow-lite + + +include $(KERNEL_ROOT)/compiler.mk diff --git a/APP_Framework/Framework/knowing/SConscript b/APP_Framework/Framework/knowing/SConscript new file mode 100644 index 0000000..f307e3f --- /dev/null +++ b/APP_Framework/Framework/knowing/SConscript @@ -0,0 +1,14 @@ +import os +Import('RTT_ROOT') +from building import * + +cwd = GetCurrentDir() +objs = [] +list = os.listdir(cwd) + +for d in list: + path = os.path.join(cwd, d) + if os.path.isfile(os.path.join(path, 'SConscript')): + objs = objs + SConscript(os.path.join(path, 'SConscript')) + +Return('objs') diff --git a/APP_Framework/Framework/security/Kconfig b/APP_Framework/Framework/security/Kconfig new file mode 100755 index 0000000..ddc089f --- /dev/null +++ b/APP_Framework/Framework/security/Kconfig @@ -0,0 +1,24 @@ +menu "Security" + +menuconfig CRYPTO + bool "using crypto" + default n + select TRANSFORM_LAYER_ATTRIUBUTE +if CRYPTO + menuconfig CRYPTO_SM3 + bool "using sm3" + default n + + menuconfig CRYPTO_SM4 + bool "using sm4" + default n + + menuconfig CRYPTO_SM9 + select CRYPTO_SM3 + select CRYPTO_SM4 + bool "using sm9" + + default n +endif + +endmenu diff --git a/APP_Framework/Framework/security/Makefile b/APP_Framework/Framework/security/Makefile new file mode 100755 index 0000000..8e49365 --- /dev/null +++ b/APP_Framework/Framework/security/Makefile @@ -0,0 +1,5 @@ +ifeq ($(CONFIG_CRYPTO), y) + SRC_DIR := crypto +endif + +include $(KERNEL_ROOT)/compiler.mk diff --git a/APP_Framework/Framework/sensor/Kconfig b/APP_Framework/Framework/sensor/Kconfig new file mode 100644 index 0000000..1187208 --- /dev/null +++ b/APP_Framework/Framework/sensor/Kconfig @@ -0,0 +1,90 @@ +menuconfig SUPPORT_SENSOR_FRAMEWORK + bool "support sensor framework" + default n + select TRANSFORM_LAYER_ATTRIUBUTE + +if SUPPORT_SENSOR_FRAMEWORK + menuconfig SENSOR_HCHO + bool "Using HCHO sensor device" + default n + if SENSOR_HCHO + source "$APP_DIR/Framework/sensor/hcho/Kconfig" + endif + + menuconfig SENSOR_TVOC + bool "Using TVOC sensor device" + default n + if SENSOR_TVOC + source "$APP_DIR/Framework/sensor/tvoc/Kconfig" + endif + + menuconfig SENSOR_IAQ + bool "Using IAQ sensor device" + default n + if SENSOR_IAQ + source "$APP_DIR/Framework/sensor/iaq/Kconfig" + endif + + menuconfig SENSOR_CH4 + bool "Using Ch4 sensor device" + default n + if SENSOR_CH4 + source "$APP_DIR/Framework/sensor/ch4/Kconfig" + endif + + menuconfig SENSOR_CO2 + bool "Using CO2 sensor device" + default n + if SENSOR_CO2 + source "$APP_DIR/Framework/sensor/co2/Kconfig" + endif + + menuconfig SENSOR_PM + bool "Using PM sensor device" + default n + if SENSOR_PM + source "$APP_DIR/Framework/sensor/pm/Kconfig" + endif + + menuconfig SENSOR_VOICE + bool "Using voice sensor device" + default n + if SENSOR_VOICE + source "$APP_DIR/Framework/sensor/voice/Kconfig" + endif + + menuconfig SENSOR_TEMPERATURE + bool "Using temperature sensor device" + default n + if SENSOR_TEMPERATURE + source "$APP_DIR/Framework/sensor/temperature/Kconfig" + endif + + menuconfig SENSOR_HUMIDITY + bool "Using humidity sensor device" + default n + if SENSOR_HUMIDITY + source "$APP_DIR/Framework/sensor/humidity/Kconfig" + endif + + menuconfig SENSOR_WINDSPEED + bool "Using wind speed sensor device" + default n + if SENSOR_WINDSPEED + source "$APP_DIR/Framework/sensor/windspeed/Kconfig" + endif + + menuconfig SENSOR_WINDDIRECTION + bool "Using wind direction sensor device" + default n + if SENSOR_WINDDIRECTION + source "$APP_DIR/Framework/sensor/winddirection/Kconfig" + endif + + menuconfig SENSOR_ALTITUDE + bool "Using altitude sensor device" + default n + if SENSOR_ALTITUDE + source "$APP_DIR/Framework/sensor/altitude/Kconfig" + endif +endif diff --git a/APP_Framework/Framework/sensor/Make.defs b/APP_Framework/Framework/sensor/Make.defs new file mode 100644 index 0000000..c06e310 --- /dev/null +++ b/APP_Framework/Framework/sensor/Make.defs @@ -0,0 +1,7 @@ +############################################################################ +# APP_Framework/Framework/sensor/Make.defs +############################################################################ +ifneq ($(CONFIG_SUPPORT_SENSOR_FRAMEWORK),) +CONFIGURED_APPS += $(APPDIR)/../../../APP_Framework/Framework/sensor +endif +include $(wildcard $(APPDIR)/../../../APP_Framework/Framework/sensor/*/Make.defs) diff --git a/APP_Framework/Framework/sensor/Makefile b/APP_Framework/Framework/sensor/Makefile new file mode 100644 index 0000000..1b0d114 --- /dev/null +++ b/APP_Framework/Framework/sensor/Makefile @@ -0,0 +1,61 @@ +include $(KERNEL_ROOT)/.config +ifeq ($(CONFIG_ADD_NUTTX_FETURES),y) + include $(APPDIR)/Make.defs + CSRCS += sensor.c + include $(APPDIR)/Application.mk + +endif + +ifeq ($(CONFIG_ADD_XIZI_FETURES),y) + SRC_FILES := sensor.c + + ifeq ($(CONFIG_SENSOR_HCHO),y) + SRC_DIR += hcho + endif + + ifeq ($(CONFIG_SENSOR_TVOC),y) + SRC_DIR += tvoc + endif + + ifeq ($(CONFIG_SENSOR_IAQ),y) + SRC_DIR += iaq + endif + + ifeq ($(CONFIG_SENSOR_CH4),y) + SRC_DIR += ch4 + endif + + ifeq ($(CONFIG_SENSOR_CO2),y) + SRC_DIR += co2 + endif + + ifeq ($(CONFIG_SENSOR_PM),y) + SRC_DIR += pm + endif + + ifeq ($(CONFIG_SENSOR_VOICE),y) + SRC_DIR += voice + endif + + ifeq ($(CONFIG_SENSOR_TEMPERATURE),y) + SRC_DIR += temperature + endif + + ifeq ($(CONFIG_SENSOR_HUMIDITY),y) + SRC_DIR += humidity + endif + + ifeq ($(CONFIG_SENSOR_WINDSPEED),y) + SRC_DIR += windspeed + endif + + ifeq ($(CONFIG_SENSOR_WINDDIRECTION),y) + SRC_DIR += winddirection + endif + + ifeq ($(CONFIG_SENSOR_ALTITUDE),y) + SRC_DIR += altitude + endif + + include $(KERNEL_ROOT)/compiler.mk +endif diff --git a/APP_Framework/Framework/sensor/SConscript b/APP_Framework/Framework/sensor/SConscript new file mode 100644 index 0000000..cf258f3 --- /dev/null +++ b/APP_Framework/Framework/sensor/SConscript @@ -0,0 +1,21 @@ +import os +Import('RTT_ROOT') +Import('rtconfig') +from building import * + +cwd = GetCurrentDir() +SOURCES = [] +if GetDepend(['SUPPORT_SENSOR_FRAMEWORK']): + SOURCES = ['sensor.c'] + SOURCES +path = [cwd] +objs = [] +group = DefineGroup('sensor', SOURCES, depend = [], CPPPATH = [cwd]) +objs = objs + group +list = os.listdir(cwd) + +for d in list: + path = os.path.join(cwd, d) + if os.path.isfile(os.path.join(path, 'SConscript')): + objs = objs + SConscript(os.path.join(path, 'SConscript')) + +Return('objs') diff --git a/APP_Framework/Framework/sensor/altitude/Kconfig b/APP_Framework/Framework/sensor/altitude/Kconfig new file mode 100644 index 0000000..afbbef1 --- /dev/null +++ b/APP_Framework/Framework/sensor/altitude/Kconfig @@ -0,0 +1,32 @@ + +config SENSOR_BMP180 + bool "Using BMP180" + default n + + if SENSOR_BMP180 + config SENSOR_DEVICE_BMP180 + string "BMP180 sensor name" + default "bmp180" + + config SENSOR_QUANTITY_BMP180_ALTITUDE + string "BMP180 quantity name" + default "altitude_1" + + if ADD_XIZI_FETURES + config SENSOR_DEVICE_BMP180_DEV + string "BMP180 device name" + default "/dev/i2c1_dev0" + + config SENSOR_DEVICE_BMP180_I2C_ADDR + hex "BMP180 device i2c address" + default 0x77 + endif + + if ADD_NUTTX_FETURES + + endif + + if ADD_RTTHREAD_FETURES + + endif + endif diff --git a/APP_Framework/Framework/sensor/altitude/Makefile b/APP_Framework/Framework/sensor/altitude/Makefile new file mode 100644 index 0000000..ee8bc8e --- /dev/null +++ b/APP_Framework/Framework/sensor/altitude/Makefile @@ -0,0 +1,5 @@ +ifeq ($(CONFIG_SENSOR_BMP180),y) + SRC_DIR += bmp180 +endif + +include $(KERNEL_ROOT)/compiler.mk diff --git a/APP_Framework/Framework/sensor/altitude/SConscript b/APP_Framework/Framework/sensor/altitude/SConscript new file mode 100644 index 0000000..f307e3f --- /dev/null +++ b/APP_Framework/Framework/sensor/altitude/SConscript @@ -0,0 +1,14 @@ +import os +Import('RTT_ROOT') +from building import * + +cwd = GetCurrentDir() +objs = [] +list = os.listdir(cwd) + +for d in list: + path = os.path.join(cwd, d) + if os.path.isfile(os.path.join(path, 'SConscript')): + objs = objs + SConscript(os.path.join(path, 'SConscript')) + +Return('objs') diff --git a/APP_Framework/Framework/sensor/altitude/bmp180/Makefile b/APP_Framework/Framework/sensor/altitude/bmp180/Makefile new file mode 100644 index 0000000..94710fa --- /dev/null +++ b/APP_Framework/Framework/sensor/altitude/bmp180/Makefile @@ -0,0 +1,3 @@ +SRC_FILES := bmp180.c + +include $(KERNEL_ROOT)/compiler.mk diff --git a/APP_Framework/Framework/sensor/altitude/bmp180/SConscript b/APP_Framework/Framework/sensor/altitude/bmp180/SConscript new file mode 100644 index 0000000..3f072a1 --- /dev/null +++ b/APP_Framework/Framework/sensor/altitude/bmp180/SConscript @@ -0,0 +1,10 @@ +from building import * +import os + +cwd = GetCurrentDir() +src = [] +if GetDepend(['SENSOR_BMP180']): + src += ['bmp180.c'] +group = DefineGroup('sensor altitude bmp180', src, depend = [], CPPPATH = [cwd]) + +Return('group') \ No newline at end of file diff --git a/APP_Framework/Framework/sensor/altitude/bmp180/bmp180.c b/APP_Framework/Framework/sensor/altitude/bmp180/bmp180.c new file mode 100644 index 0000000..a5c9da0 --- /dev/null +++ b/APP_Framework/Framework/sensor/altitude/bmp180/bmp180.c @@ -0,0 +1,322 @@ +/* +* Copyright (c) 2020 AIIT XUOS Lab +* XiUOS is licensed under Mulan PSL v2. +* You can use this software according to the terms and conditions of the Mulan PSL v2. +* You may obtain a copy of Mulan PSL v2 at: +* http://license.coscl.org.cn/MulanPSL2 +* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, +* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, +* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. +* See the Mulan PSL v2 for more details. +*/ + +/** + * @file bmp180.c + * @brief BMP180 altitude driver base sensor + * @version 1.1 + * @author AIIT XUOS Lab + * @date 2021.12.20 + */ + +#include +#include + +static struct SensorDevice bmp180; + +typedef struct { + int8_t ac_data[3]; + uint8_t unsigned_ac_data[3]; + int8_t b_data[2]; + int8_t m_data[3]; +}Bmp180RegData; + +static Bmp180RegData bmp180_reg_data; + +const static unsigned char OSS = 0; // Oversampling Setting +static long CalTemp_data = 0; + +static struct SensorProductInfo info = +{ + (SENSOR_ABILITY_ALTITUDE), + "BOSCH", + "BMP180", +}; + +/** + * @description: Open BMP180 sensor device + * @param sdev - sensor device pointer + * @return success : 0 error : -1 + */ +static int SensorDeviceOpen(struct SensorDevice *sdev) +{ + int result; + uint16_t i2c_dev_addr = SENSOR_DEVICE_BMP180_I2C_ADDR; + + sdev->fd = PrivOpen(SENSOR_DEVICE_BMP180_DEV, O_RDWR); + if (sdev->fd < 0) { + printf("open %s error\n", SENSOR_DEVICE_BMP180_DEV); + return -1; + } + + struct PrivIoctlCfg ioctl_cfg; + ioctl_cfg.ioctl_driver_type = I2C_TYPE; + ioctl_cfg.args = &i2c_dev_addr; + result = PrivIoctl(sdev->fd, OPE_INT, &ioctl_cfg); + + return result; +} + +/** + * @description: Write sensor device + * @param sdev - sensor device pointer + * @param len - the length of the read data + * @return success: 0 , failure: -1 + */ +static int SensorDeviceWrite(struct SensorDevice *sdev, const void *buf, size_t len) +{ + if (PrivWrite(sdev->fd, buf, len) < 0) + return -1; + + return 0; +} + +/** + * @description: Read sensor device + * @param sdev - sensor device pointer + * @param len - the length of the read data + * @return success: 0 , failure: -1 + */ +static int SensorDeviceRead(struct SensorDevice *sdev, size_t len) +{ + //Read i2c device data from i2c device address + if (PrivRead(sdev->fd, sdev->buffer, len) < 0) + return -1; + + return 0; +} + +static struct SensorDone done = +{ + SensorDeviceOpen, + NULL, + SensorDeviceRead, + SensorDeviceWrite, + NULL, +}; + +/** + * @description: Init BMP180 sensor and register + * @return void + */ +static void SensorDeviceBmp180Init(void) +{ + bmp180.name = SENSOR_DEVICE_BMP180; + bmp180.info = &info; + bmp180.done = &done; + bmp180.status = SENSOR_DEVICE_PASSIVE; + + SensorDeviceRegister(&bmp180); +} + +static struct SensorQuantity bmp180_altitude; + +/** + * @description: Stores all of the bmp180's calibration values into global variables + * @return uint16_t reg data + */ +static uint16_t SensorDeviceBmp180ReadRegs(struct SensorDevice *sdev, char reg_addr) +{ + uint8_t reg_data[2] = {0}; + + if (SensorDeviceWrite(sdev, ®_addr, 1) < 0) { + printf("SensorDeviceBmp180ReadRegs write reg 0x%x error. return 0x0\n", reg_addr); + return 0; + } + + if (SensorDeviceRead(sdev, 2) < 0) { + printf("SensorDeviceBmp180ReadRegs error. return 0x0\n"); + return 0; + } + + reg_data[0] = sdev->buffer[0]; + reg_data[1] = sdev->buffer[1]; + + return (uint16_t)(reg_data[0] << 8 | reg_data[1]); +} + +/** + * @description: Read the uncompensated temperature value(ut) + * @return uint16_t 0xF6 reg data + */ +static uint16_t SensorDeviceBmp180ReadUT(struct SensorDevice *sdev) +{ + uint8_t data[2]; + data[0] = 0xF4; + data[1] = 0x2E; + + if (SensorDeviceWrite(sdev, data, 2) < 0) { + printf("SensorDeviceBmp180ReadUT write reg 0xF4 error. return 0x0\n"); + return 0; + } + + return SensorDeviceBmp180ReadRegs(sdev, 0xF6); +} + +/** + * @description: Read the uncompensated pressure value(up) + * @return uint16_t 0xF6 reg data + */ +static uint16_t SensorDeviceBmp180ReadUP(struct SensorDevice *sdev) +{ + uint8_t data[2]; + data[0] = 0xF4; + data[1] = 0x34 + (OSS << 6); + + if (SensorDeviceWrite(sdev, data, 2) < 0) { + printf("SensorDeviceBmp180ReadUP write reg 0xF4 error. return 0x0\n"); + return 0; + } + + return SensorDeviceBmp180ReadRegs(sdev, 0xF6); +} + +/** + * @description: Calculate temperature + * @return uint16_t reg data + */ +static float SensorDeviceBmp180CalTemp(struct SensorDevice *sdev, uint16_t ut, Bmp180RegData *bmp180_reg_data) +{ + long x1, x2; + x1 = (((long)ut - (long)bmp180_reg_data->unsigned_ac_data[2]) * (long)bmp180_reg_data->unsigned_ac_data[1]) >> 15; + x2 = ((long)bmp180_reg_data->m_data[1] << 11) / (x1 + bmp180_reg_data->m_data[2]); + CalTemp_data = x1 + x2; + float temp = ((CalTemp_data + 8) >> 4); + temp = temp / 10; + return temp; +} + +/** + * @description: Calculate pressure + * @return float pressure + */ +static float SensorDeviceBmp180CalPressure(struct SensorDevice *sdev, uint16_t up, Bmp180RegData *bmp180_reg_data) +{ + long x1, x2, x3, y1, y2, pressure; + unsigned long z1, z2; + + y2 = CalTemp_data - 4000; + // Calculate y1 data + x1 = (bmp180_reg_data->b_data[1] * (y2 * y2) >> 12) >> 11; + x2 = (bmp180_reg_data->ac_data[1] * y2)>>11; + x3 = x1 + x2; + y1 = (((((long)bmp180_reg_data->ac_data[0]) * 4 + x3) << OSS) + 2) >> 2; + + // Calculate B4 + x1 = (bmp180_reg_data->ac_data[2] * y2) >> 13; + x2 = (bmp180_reg_data->b_data[0] * ((y2 * y2) >> 12)) >> 16; + x3 = ((x1 + x2) + 2) >> 2; + z1 = (bmp180_reg_data->unsigned_ac_data[0] * (unsigned long)(x3 + 32768)) >> 15; + + z2 = ((unsigned long)(up - y1) * (50000 >> OSS)); + if (z2 < 0x80000000) + pressure = (z2 << 1) / z1; + else + pressure = (z2 / z1) << 1; + + x1 = (pressure >> 8) * (pressure >> 8); + x1 = (x1 * 3038) >> 16; + x2 = (-7357 * pressure) >> 16; + pressure += (x1 + x2 + 3791) >> 4; + + return pressure; +} + +/** + * @description: Calculate altitude + * @return float Altitude + */ +static float SensorDeviceBmp180CalAltitude(float pressure) +{ + float A = pressure / 101325; + float B = 1 / 5.25588; + float altitude = pow(A, B); + altitude = 1 - altitude; + altitude = altitude / 0.0000225577; + + return altitude; +} + +/** + * @description: Analysis BMP180 temperature result + * @param quant - sensor quantity pointer + * @return quantity value + */ +static int32_t ReadAltitude(struct SensorQuantity *quant) +{ + if (!quant) + return -1; + + memset(&bmp180_reg_data, 0 , sizeof(Bmp180RegData)); + + uint16_t ut, up = 0; + float bmp180_temperature, bmp180_pressure, bmp180_aititude; + if (quant->sdev->done->read != NULL) { + if (quant->sdev->status == SENSOR_DEVICE_PASSIVE) { + + bmp180_reg_data.ac_data[0] = SensorDeviceBmp180ReadRegs(quant->sdev, 0xAA); + bmp180_reg_data.ac_data[1] = SensorDeviceBmp180ReadRegs(quant->sdev, 0xAC); + bmp180_reg_data.ac_data[2] = SensorDeviceBmp180ReadRegs(quant->sdev, 0xAE); + bmp180_reg_data.unsigned_ac_data[0] = SensorDeviceBmp180ReadRegs(quant->sdev, 0xB0); + bmp180_reg_data.unsigned_ac_data[1] = SensorDeviceBmp180ReadRegs(quant->sdev, 0xB2); + bmp180_reg_data.unsigned_ac_data[2] = SensorDeviceBmp180ReadRegs(quant->sdev, 0xB4); + bmp180_reg_data.b_data[0] = SensorDeviceBmp180ReadRegs(quant->sdev, 0xB6); + bmp180_reg_data.b_data[1] = SensorDeviceBmp180ReadRegs(quant->sdev, 0xB8); + bmp180_reg_data.m_data[0] = SensorDeviceBmp180ReadRegs(quant->sdev, 0xBA); + bmp180_reg_data.m_data[1] = SensorDeviceBmp180ReadRegs(quant->sdev, 0xBC); + bmp180_reg_data.m_data[2] = SensorDeviceBmp180ReadRegs(quant->sdev, 0xBE); + + ut = SensorDeviceBmp180ReadUT(quant->sdev); + up = SensorDeviceBmp180ReadUP(quant->sdev); + + bmp180_temperature = SensorDeviceBmp180CalTemp(quant->sdev, ut, &bmp180_reg_data); + bmp180_pressure = SensorDeviceBmp180CalPressure(quant->sdev, up, &bmp180_reg_data); + bmp180_aititude = SensorDeviceBmp180CalAltitude(bmp180_pressure); + + return (int32_t)bmp180_pressure; + } + if (quant->sdev->status == SENSOR_DEVICE_ACTIVE) { + printf("Please set passive mode.\n"); + } + }else{ + printf("%s don't have read done.\n", quant->name); + } + + return -1; +} + +/** + * @description: Init BMP180 temperature quantity and register + * @return 0 + */ +int Bmp180AltitudeInit(void) +{ + SensorDeviceBmp180Init(); + + bmp180_altitude.name = SENSOR_QUANTITY_BMP180_ALTITUDE; + bmp180_altitude.type = SENSOR_QUANTITY_ALTITUDE; + bmp180_altitude.value.decimal_places = 1; + bmp180_altitude.value.max_std = 1000; + bmp180_altitude.value.min_std = 0; + bmp180_altitude.value.last_value = SENSOR_QUANTITY_VALUE_ERROR; + bmp180_altitude.value.max_value = SENSOR_QUANTITY_VALUE_ERROR; + bmp180_altitude.value.min_value = SENSOR_QUANTITY_VALUE_ERROR; + bmp180_altitude.sdev = &bmp180; + bmp180_altitude.ReadValue = ReadAltitude; + + SensorQuantityRegister(&bmp180_altitude); + + return 0; +} + + + diff --git a/APP_Framework/Framework/sensor/ch4/Kconfig b/APP_Framework/Framework/sensor/ch4/Kconfig new file mode 100644 index 0000000..63011de --- /dev/null +++ b/APP_Framework/Framework/sensor/ch4/Kconfig @@ -0,0 +1,65 @@ + +config SENSOR_AS830 + bool "Using as830" + default n + + if SENSOR_AS830 + config SENSOR_DEVICE_AS830 + string "as830 sensor name" + default "as830_1" + + config SENSOR_QUANTITY_AS830_CH4 + string "as830 quantity name" + default "ch4_1" + + if ADD_XIZI_FETURES + config SENSOR_AS830_DRIVER_EXTUART + bool "Using extra uart to support as830" + default y + + config SENSOR_DEVICE_AS830_DEV + string "as830 device uart path" + default "/dev/uart2_dev2" + depends on !SENSOR_AS830_DRIVER_EXTUART + + if SENSOR_AS830_DRIVER_EXTUART + config SENSOR_DEVICE_AS830_DEV + string "as830 device extra uart path" + default "/dev/extuart_dev1" + + config SENSOR_DEVICE_AS830_DEV_EXT_PORT + int "if AS830 device using extuart, choose port" + default "1" + endif + endif + + if ADD_NUTTX_FETURES + config SENSOR_DEVICE_AS830_DEV + string "as830 device uart path" + default "/dev/ttyS1" + ---help--- + If USART1 is selected, then fill in /dev/ttyS1 here. + + endif + + if ADD_RTTHREAD_FETURES + config SENSOR_AS830_DRIVER_EXTUART + bool "Using extra uart to support as830" + default y + + config SENSOR_DEVICE_AS830_DEV + string "as830 device uart path" + default "/dev/uart2" + depends on !SENSOR_AS830_DRIVER_EXTUART + + if SENSOR_AS830_DRIVER_EXTUART + config SENSOR_DEVICE_AS830_DEV + string "as830 device extra uart path" + default "/dev/extuart_dev4" + + config SENSOR_DEVICE_AS830_DEV_EXT_PORT + int "if AS830 device using extuart, choose port" + default "4" + endif + endif + endif diff --git a/APP_Framework/Framework/sensor/ch4/Make.defs b/APP_Framework/Framework/sensor/ch4/Make.defs new file mode 100644 index 0000000..b0404bb --- /dev/null +++ b/APP_Framework/Framework/sensor/ch4/Make.defs @@ -0,0 +1,4 @@ +############################################################################ +# APP_Framework/Framework/sensor/ch4/Make.defs +############################################################################ +include $(wildcard $(APPDIR)/../../../APP_Framework/Framework/sensor/ch4/*/Make.defs) diff --git a/APP_Framework/Framework/sensor/ch4/Makefile b/APP_Framework/Framework/sensor/ch4/Makefile new file mode 100644 index 0000000..913dda1 --- /dev/null +++ b/APP_Framework/Framework/sensor/ch4/Makefile @@ -0,0 +1,5 @@ +ifeq ($(CONFIG_SENSOR_AS830),y) + SRC_DIR += as830 +endif + +include $(KERNEL_ROOT)/compiler.mk diff --git a/APP_Framework/Framework/sensor/ch4/SConscript b/APP_Framework/Framework/sensor/ch4/SConscript new file mode 100644 index 0000000..f307e3f --- /dev/null +++ b/APP_Framework/Framework/sensor/ch4/SConscript @@ -0,0 +1,14 @@ +import os +Import('RTT_ROOT') +from building import * + +cwd = GetCurrentDir() +objs = [] +list = os.listdir(cwd) + +for d in list: + path = os.path.join(cwd, d) + if os.path.isfile(os.path.join(path, 'SConscript')): + objs = objs + SConscript(os.path.join(path, 'SConscript')) + +Return('objs') diff --git a/APP_Framework/Framework/sensor/ch4/as830/Make.defs b/APP_Framework/Framework/sensor/ch4/as830/Make.defs new file mode 100644 index 0000000..e1bc8e4 --- /dev/null +++ b/APP_Framework/Framework/sensor/ch4/as830/Make.defs @@ -0,0 +1,6 @@ +############################################################################ +# APP_Framework/Framework/sensor/ch4/as830/Make.defs +############################################################################ +ifneq ($(CONFIG_SENSOR_AS830),) +CONFIGURED_APPS += $(APPDIR)/../../../APP_Framework/Framework/sensor/ch4/as830 +endif diff --git a/APP_Framework/Framework/sensor/ch4/as830/Makefile b/APP_Framework/Framework/sensor/ch4/as830/Makefile new file mode 100644 index 0000000..5d661e3 --- /dev/null +++ b/APP_Framework/Framework/sensor/ch4/as830/Makefile @@ -0,0 +1,11 @@ +include $(KERNEL_ROOT)/.config +ifeq ($(CONFIG_ADD_NUTTX_FETURES),y) + include $(APPDIR)/Make.defs + CSRCS += as830.c + include $(APPDIR)/Application.mk +endif + +ifeq ($(CONFIG_ADD_XIZI_FETURES),y) + SRC_FILES := as830.c + include $(KERNEL_ROOT)/compiler.mk +endif diff --git a/APP_Framework/Framework/sensor/ch4/as830/SConscript b/APP_Framework/Framework/sensor/ch4/as830/SConscript new file mode 100644 index 0000000..1e361ed --- /dev/null +++ b/APP_Framework/Framework/sensor/ch4/as830/SConscript @@ -0,0 +1,10 @@ +from building import * +import os + +cwd = GetCurrentDir() +src = [] +if GetDepend(['SENSOR_AS830']): + src += ['as830.c'] +group = DefineGroup('sensor ch4 as830', src, depend = [], CPPPATH = [cwd]) + +Return('group') \ No newline at end of file diff --git a/APP_Framework/Framework/sensor/ch4/as830/as830.c b/APP_Framework/Framework/sensor/ch4/as830/as830.c new file mode 100644 index 0000000..49ad1fc --- /dev/null +++ b/APP_Framework/Framework/sensor/ch4/as830/as830.c @@ -0,0 +1,238 @@ +/* +* Copyright (c) 2020 AIIT XUOS Lab +* XiUOS is licensed under Mulan PSL v2. +* You can use this software according to the terms and conditions of the Mulan PSL v2. +* You may obtain a copy of Mulan PSL v2 at: +* http://license.coscl.org.cn/MulanPSL2 +* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, +* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, +* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. +* See the Mulan PSL v2 for more details. +*/ + +/** + * @file as830.c + * @brief AS830 CH4 driver base sensor + * @version 1.0 + * @author AIIT XUOS Lab + * @date 2021.12.10 + */ + +#include + +static struct SensorDevice as830; + +static struct SensorProductInfo info = +{ + SENSOR_ABILITY_CH4, + "xxxxx", + "AS830", +}; + +/** + * @description: Open AS830 sensor device + * @param sdev - sensor device pointer + * @return success: 1 , failure: other + */ +#ifdef ADD_NUTTX_FETURES +static int SensorDeviceOpen(struct SensorDevice *sdev) +{ + sdev->fd = PrivOpen(SENSOR_DEVICE_AS830_DEV, O_RDWR); + if (sdev->fd < 0) { + printf("open %s error\n", SENSOR_DEVICE_AS830_DEV); + return -1; + } + + return sdev->fd; +} +#else +static int SensorDeviceOpen(struct SensorDevice *sdev) +{ + int result = 0; + + sdev->fd = PrivOpen(SENSOR_DEVICE_AS830_DEV, O_RDWR); + if (sdev->fd < 0) { + printf("open %s error\n", SENSOR_DEVICE_AS830_DEV); + return -1; + } + + struct SerialDataCfg cfg; + cfg.serial_baud_rate = BAUD_RATE_9600; + cfg.serial_data_bits = DATA_BITS_8; + cfg.serial_stop_bits = STOP_BITS_1; + cfg.serial_buffer_size = 128; + cfg.serial_parity_mode = PARITY_NONE; + cfg.serial_bit_order = 0; + cfg.serial_invert_mode = 0; +#ifdef SENSOR_AS830_DRIVER_EXTUART + cfg.ext_uart_no = SENSOR_DEVICE_AS830_DEV_EXT_PORT; + cfg.port_configure = PORT_CFG_INIT; +#endif + + struct PrivIoctlCfg ioctl_cfg; + ioctl_cfg.ioctl_driver_type = SERIAL_TYPE; + ioctl_cfg.args = &cfg; + result = PrivIoctl(sdev->fd, OPE_INT, &ioctl_cfg); + + return result; +} +#endif + +/** + * @description: Read sensor device + * @param sdev - sensor device pointer + * @param len - the length of the read data + * @return get data length + */ +static int SensorDeviceRead(struct SensorDevice *sdev, size_t len) +{ + uint8_t tmp = 0; + uint8_t idx = 0; + + while (1) { + if (PrivRead(sdev->fd, &tmp, 1) == 1) { + sdev->buffer[idx++] = tmp; + } + if(0xA == tmp){ + break; + } + } + + return idx; +} + +static struct SensorDone done = +{ + SensorDeviceOpen, + NULL, + SensorDeviceRead, + NULL, + NULL, +}; + +/** + * @description: Init AS830 sensor and register + * @return void + */ +static void SensorDeviceAs830Init(void) +{ + as830.name = SENSOR_DEVICE_AS830; + as830.info = &info; + as830.done = &done; + + SensorDeviceRegister(&as830); +} + + +/* check data*/ +static uint8_t CH4_check(uint8_t *packet) +{ + uint8_t i, high, low; + uint8_t checksum = 0; + for( i = 0; i < 10; i++) + { + if(packet[i] == 0x09) + break; + checksum += packet[i]; + } + checksum = (unsigned char)(-(signed char)checksum); + high = (checksum & 0xF0) >> 4; + if((high <= 0x0F) && (high >= 0x0A)) + high += 0x37; + else if((high <= 0x09) && (high >= 0x00)) + high += 0x30; + low = (checksum & 0x0F); + if((low <= 0x0F) && (low >= 0x0A)) + low += 0x37; + else if((low <= 0x09) && (low >= 0x00)) + low += 0x30; + if((high == packet[i + 1]) && (low == packet[i + 2])) + return 0; + + return -1; +} + + +static struct SensorQuantity as830_ch4; + +/** + * @description: Analysis AS830 CH4 result + * @param quant - sensor quantity pointer + * @return quantity value + */ +static int32_t QuantityRead(struct SensorQuantity *quant) +{ + if (!quant) + return -1; + + uint32_t result; + uint32_t len = 0; + if (quant->sdev->done->read != NULL) { + if(quant->sdev->status == SENSOR_DEVICE_PASSIVE) { + len = quant->sdev->done->read(quant->sdev, 7); + if (len == 0) + { + printf("error read data length = 0.\n"); + return -1; + } + + if(CH4_check(quant->sdev->buffer) == 0) + { + for(int i = 0; i < len; i++) + { + if(quant->sdev->buffer[i] == 0x09) + { + break; + } + result = result *10 + (quant->sdev->buffer[i] - 0x30); + } + + if (result > quant->value.max_value) + quant->value.max_value = result; + else if (result < quant->value.min_value) + quant->value.min_value = result; + quant->value.last_value = result; + + return result; + } + else + { + printf("This reading is wrong\n"); + result = SENSOR_QUANTITY_VALUE_ERROR; + return result; + } + } + if (quant->sdev->status == SENSOR_DEVICE_ACTIVE) + { + printf("Please set passive mode.\n"); + } + }else{ + printf("%s don't have read done.\n", quant->name); + } + + return -1; +} + +/** + * @description: Init AS830 CH4 quantity and register + * @return 0 + */ +int As830Ch4Init(void) +{ + SensorDeviceAs830Init(); + + as830_ch4.name = SENSOR_QUANTITY_AS830_CH4; + as830_ch4.type = SENSOR_QUANTITY_CH4; + as830_ch4.value.decimal_places = 0; + as830_ch4.value.max_std = 1000; + as830_ch4.value.min_std = 350; + as830_ch4.value.last_value = SENSOR_QUANTITY_VALUE_ERROR; + as830_ch4.value.max_value = SENSOR_QUANTITY_VALUE_ERROR; + as830_ch4.value.min_value = SENSOR_QUANTITY_VALUE_ERROR; + as830_ch4.sdev = &as830; + as830_ch4.ReadValue = QuantityRead; + + SensorQuantityRegister(&as830_ch4); + + return 0; +} \ No newline at end of file diff --git a/APP_Framework/Framework/sensor/co2/Kconfig b/APP_Framework/Framework/sensor/co2/Kconfig new file mode 100644 index 0000000..e4c4c43 --- /dev/null +++ b/APP_Framework/Framework/sensor/co2/Kconfig @@ -0,0 +1,108 @@ + +config SENSOR_ZG09 + bool "Using zg09" + default n + + if SENSOR_ZG09 + config SENSOR_DEVICE_ZG09 + string "zg09 sensor name" + default "zg09_1" + + config SENSOR_QUANTITY_ZG09_CO2 + string "zg09 quantity name" + default "co2_1" + + if ADD_XIZI_FETURES + config SENSOR_ZG09_DRIVER_EXTUART + bool "Using extra uart to support zg09" + default y + + config SENSOR_DEVICE_ZG09_DEV + string "zg09 device uart path" + default "/dev/uart2_dev2" + depends on !SENSOR_ZG09_DRIVER_EXTUART + + if SENSOR_ZG09_DRIVER_EXTUART + config SENSOR_DEVICE_ZG09_DEV + string "zg09 device extra uart path" + default "/dev/extuart_dev4" + + config SENSOR_DEVICE_ZG09_DEV_EXT_PORT + int "if ZG09 device using extuart, choose port" + default "4" + endif + endif + + if ADD_NUTTX_FETURES + config SENSOR_DEVICE_ZG09_DEV + string "CO2 device name" + default "/dev/ttyS1" + ---help--- + If USART1 is selected, then fill in /dev/ttyS1 here. + + endif + + if ADD_RTTHREAD_FETURES + config SENSOR_ZG09_DRIVER_EXTUART + bool "Using extra uart to support zg09" + default y + + config SENSOR_DEVICE_ZG09_DEV + string "zg09 device uart path" + default "/dev/uart2_dev2" + depends on !SENSOR_ZG09_DRIVER_EXTUART + + if SENSOR_ZG09_DRIVER_EXTUART + config SENSOR_DEVICE_ZG09_DEV + string "zg09 device extra uart path" + default "/dev/extuart_dev4" + + config SENSOR_DEVICE_ZG09_DEV_EXT_PORT + int "if ZG09 device using extuart, choose port" + default "4" + endif + endif + endif + +config SENSOR_G8S + bool "Using g8-s" + default n + + if SENSOR_G8S + config SENSOR_DEVICE_G8S + string "g8-s sensor name" + default "g8-s" + + config SENSOR_QUANTITY_G8S_CO2 + string "g8-s quantity name" + default "co2_2" + + if ADD_XIZI_FETURES + config SENSOR_G8S_DRIVER_EXTUART + bool "Using extra uart to support g8-s" + default n + + config SENSOR_DEVICE_G8S_DEV + string "g8-s device uart path" + default "/dev/uart2_dev2" + depends on !SENSOR_G8S_DRIVER_EXTUART + + if SENSOR_G8S_DRIVER_EXTUART + config SENSOR_DEVICE_G8S_DEV + string "g8-s device extra uart path" + default "/dev/extuart_dev4" + + config SENSOR_DEVICE_G8S_DEV_EXT_PORT + int "if g8-s device using extuart, choose port" + default "4" + endif + endif + + if ADD_NUTTX_FETURES + + endif + + if ADD_RTTHREAD_FETURES + + endif + endif diff --git a/APP_Framework/Framework/sensor/co2/Make.defs b/APP_Framework/Framework/sensor/co2/Make.defs new file mode 100644 index 0000000..23a5895 --- /dev/null +++ b/APP_Framework/Framework/sensor/co2/Make.defs @@ -0,0 +1,4 @@ +############################################################################ +# APP_Framework/Framework/sensor/co2/Make.defs +############################################################################ +include $(wildcard $(APPDIR)/../../../APP_Framework/Framework/sensor/co2/*/Make.defs) diff --git a/APP_Framework/Framework/sensor/co2/Makefile b/APP_Framework/Framework/sensor/co2/Makefile new file mode 100644 index 0000000..ba645d1 --- /dev/null +++ b/APP_Framework/Framework/sensor/co2/Makefile @@ -0,0 +1,9 @@ +ifeq ($(CONFIG_SENSOR_ZG09),y) + SRC_DIR += zg09 +endif + +ifeq ($(CONFIG_SENSOR_G8S),y) + SRC_DIR += g8s +endif + +include $(KERNEL_ROOT)/compiler.mk diff --git a/APP_Framework/Framework/sensor/co2/SConscript b/APP_Framework/Framework/sensor/co2/SConscript new file mode 100644 index 0000000..f307e3f --- /dev/null +++ b/APP_Framework/Framework/sensor/co2/SConscript @@ -0,0 +1,14 @@ +import os +Import('RTT_ROOT') +from building import * + +cwd = GetCurrentDir() +objs = [] +list = os.listdir(cwd) + +for d in list: + path = os.path.join(cwd, d) + if os.path.isfile(os.path.join(path, 'SConscript')): + objs = objs + SConscript(os.path.join(path, 'SConscript')) + +Return('objs') diff --git a/APP_Framework/Framework/sensor/co2/g8s/Makefile b/APP_Framework/Framework/sensor/co2/g8s/Makefile new file mode 100644 index 0000000..933351b --- /dev/null +++ b/APP_Framework/Framework/sensor/co2/g8s/Makefile @@ -0,0 +1,3 @@ +SRC_FILES := g8s.c + +include $(KERNEL_ROOT)/compiler.mk diff --git a/APP_Framework/Framework/sensor/co2/g8s/SConscript b/APP_Framework/Framework/sensor/co2/g8s/SConscript new file mode 100644 index 0000000..9e8be22 --- /dev/null +++ b/APP_Framework/Framework/sensor/co2/g8s/SConscript @@ -0,0 +1,10 @@ +from building import * +import os + +cwd = GetCurrentDir() +src = [] +if GetDepend(['SENSOR_G8S']): + src += ['g8s.c'] +group = DefineGroup('sensor co2 g8s', src, depend = [], CPPPATH = [cwd]) + +Return('group') \ No newline at end of file diff --git a/APP_Framework/Framework/sensor/co2/g8s/g8s.c b/APP_Framework/Framework/sensor/co2/g8s/g8s.c new file mode 100644 index 0000000..b46b549 --- /dev/null +++ b/APP_Framework/Framework/sensor/co2/g8s/g8s.c @@ -0,0 +1,187 @@ +/* +* Copyright (c) 2020 AIIT XUOS Lab +* XiUOS is licensed under Mulan PSL v2. +* You can use this software according to the terms and conditions of the Mulan PSL v2. +* You may obtain a copy of Mulan PSL v2 at: +* http://license.coscl.org.cn/MulanPSL2 +* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, +* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, +* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. +* See the Mulan PSL v2 for more details. +*/ + +/** + * @file g8s.c + * @brief G8S CO2 driver base sensor + * @version 1.1 + * @author AIIT XUOS Lab + * @date 2021.12.23 + */ + +#include +#include + +static uint8_t g8s_read_instruction[8] = {0x52, 0x36, 0x09, 0x37, 0x38, 0x0D, 0x0A}; + +static struct SensorDevice g8s; + +static struct SensorProductInfo info = +{ + SENSOR_ABILITY_CO2, + "senTec", + "G8S", +}; + +/** + * @description: Open G8S sensor device + * @param sdev - sensor device pointer + * @return success: 1 , failure: other + */ +static int SensorDeviceOpen(struct SensorDevice *sdev) +{ + int result = 0; + + sdev->fd = PrivOpen(SENSOR_DEVICE_G8S_DEV, O_RDWR); + if (sdev->fd < 0) { + printf("open %s error\n", SENSOR_DEVICE_G8S_DEV); + return -1; + } + + struct SerialDataCfg cfg; + cfg.serial_baud_rate = BAUD_RATE_9600; + cfg.serial_data_bits = DATA_BITS_8; + cfg.serial_stop_bits = STOP_BITS_1; + cfg.serial_buffer_size = 128; + cfg.serial_parity_mode = PARITY_NONE; + cfg.serial_bit_order = 0; + cfg.serial_invert_mode = 0; +#ifdef SENSOR_G8S_DRIVER_EXTUART + cfg.ext_uart_no = SENSOR_DEVICE_G8S_DEV_EXT_PORT; + cfg.port_configure = PORT_CFG_INIT; +#endif + + struct PrivIoctlCfg ioctl_cfg; + ioctl_cfg.ioctl_driver_type = SERIAL_TYPE; + ioctl_cfg.args = &cfg; + result = PrivIoctl(sdev->fd, OPE_INT, &ioctl_cfg); + + return result; +} + +/** + * @description: Read sensor device + * @param sdev - sensor device pointer + * @param len - the length of the read data + * @return get data length + */ +static int SensorDeviceRead(struct SensorDevice *sdev, size_t len) +{ + uint8_t tmp = 0; + + PrivWrite(sdev->fd, g8s_read_instruction, sizeof(g8s_read_instruction)); + + if (PrivRead(sdev->fd, sdev->buffer, len) < 0) + return -1; + + return 0; +} + +static struct SensorDone done = +{ + SensorDeviceOpen, + NULL, + SensorDeviceRead, + NULL, + NULL, +}; + +/** + * @description: Init G8S sensor and register + * @return void + */ +static void SensorDeviceG8sInit(void) +{ + g8s.name = SENSOR_DEVICE_G8S; + g8s.info = &info; + g8s.done = &done; + g8s.status = SENSOR_DEVICE_PASSIVE; + + SensorDeviceRegister(&g8s); +} + +static struct SensorQuantity g8s_co2; + +/** + * @description: Analysis G8S CO2 result + * @param quant - sensor quantity pointer + * @return quantity value + */ +static int32_t QuantityRead(struct SensorQuantity *quant) +{ + if (!quant) + return -1; + + int i, ascii_length; + int32_t result = 0; + uint8_t result_ascii[9], result_hex[9]; + + memset(result_ascii, 0, 9); + memset(result_hex, 0, 9); + + if (quant->sdev->done->read != NULL) { + if(quant->sdev->status == SENSOR_DEVICE_PASSIVE) { + quant->sdev->done->read(quant->sdev, 9); + + for (i = 0; i < 9; i ++) { + if (0x09 == quant->sdev->buffer[i]) { + ascii_length = i; + break; + } + result_ascii[i] = quant->sdev->buffer[i]; + } + + if (8 == ascii_length) { + for (i = 0; i < ascii_length; i ++) { + result_hex[i] = result_ascii[i] - 0x30; + result += result_hex[i] * pow(10, ascii_length - 1 - i); + } + return result; + } else { + printf("This reading is wrong\n"); + result = SENSOR_QUANTITY_VALUE_ERROR; + return result; + } + } + if (quant->sdev->status == SENSOR_DEVICE_ACTIVE) { + printf("Please set passive mode.\n"); + } + }else{ + printf("%s don't have read done.\n", quant->name); + } + + return -1; +} + +/** + * @description: Init G8S CO2 quantity and register + * @return 0 + */ +int G8sCo2Init(void) +{ + SensorDeviceG8sInit(); + + g8s_co2.name = SENSOR_QUANTITY_G8S_CO2; + g8s_co2.type = SENSOR_QUANTITY_CO2; + g8s_co2.value.decimal_places = 0; + g8s_co2.value.max_std = 2000; + g8s_co2.value.min_std = 0; + g8s_co2.value.last_value = SENSOR_QUANTITY_VALUE_ERROR; + g8s_co2.value.max_value = SENSOR_QUANTITY_VALUE_ERROR; + g8s_co2.value.min_value = SENSOR_QUANTITY_VALUE_ERROR; + g8s_co2.sdev = &g8s; + g8s_co2.ReadValue = QuantityRead; + + SensorQuantityRegister(&g8s_co2); + + return 0; +} \ No newline at end of file diff --git a/APP_Framework/Framework/sensor/co2/zg09/Make.defs b/APP_Framework/Framework/sensor/co2/zg09/Make.defs new file mode 100644 index 0000000..d3e2c2c --- /dev/null +++ b/APP_Framework/Framework/sensor/co2/zg09/Make.defs @@ -0,0 +1,6 @@ +############################################################################ +# APP_Framework/Framework/sensor/co2/zg09/Make.defs +############################################################################ +ifneq ($(CONFIG_SENSOR_ZG09),) +CONFIGURED_APPS += $(APPDIR)/../../../APP_Framework/Framework/sensor/co2/zg09 +endif diff --git a/APP_Framework/Framework/sensor/co2/zg09/Makefile b/APP_Framework/Framework/sensor/co2/zg09/Makefile new file mode 100644 index 0000000..1a3e79d --- /dev/null +++ b/APP_Framework/Framework/sensor/co2/zg09/Makefile @@ -0,0 +1,13 @@ +include $(KERNEL_ROOT)/.config + +ifeq ($(CONFIG_ADD_NUTTX_FETURES),y) + include $(APPDIR)/Make.defs + CSRCS += zg09.c + include $(APPDIR)/Application.mk +endif + +ifeq ($(CONFIG_ADD_XIZI_FETURES),y) + SRC_FILES := zg09.c + include $(KERNEL_ROOT)/compiler.mk +endif + diff --git a/APP_Framework/Framework/sensor/co2/zg09/SConscript b/APP_Framework/Framework/sensor/co2/zg09/SConscript new file mode 100644 index 0000000..084f101 --- /dev/null +++ b/APP_Framework/Framework/sensor/co2/zg09/SConscript @@ -0,0 +1,10 @@ +from building import * +import os + +cwd = GetCurrentDir() +src = [] +if GetDepend(['SENSOR_ZG09']): + src += ['zg09.c'] +group = DefineGroup('sensor co2 zg09', src, depend = [], CPPPATH = [cwd]) + +Return('group') \ No newline at end of file diff --git a/APP_Framework/Framework/sensor/co2/zg09/zg09.c b/APP_Framework/Framework/sensor/co2/zg09/zg09.c new file mode 100644 index 0000000..d18f96f --- /dev/null +++ b/APP_Framework/Framework/sensor/co2/zg09/zg09.c @@ -0,0 +1,253 @@ +/* +* Copyright (c) 2020 AIIT XUOS Lab +* XiUOS is licensed under Mulan PSL v2. +* You can use this software according to the terms and conditions of the Mulan PSL v2. +* You may obtain a copy of Mulan PSL v2 at: +* http://license.coscl.org.cn/MulanPSL2 +* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, +* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, +* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. +* See the Mulan PSL v2 for more details. +*/ + +/** + * @file zg09.c + * @brief ZG09 CO2 driver base sensor + * @version 1.0 + * @author AIIT XUOS Lab + * @date 2021.04.22 + */ + +#include + +static uint8_t zg09_set_passive[8]={0xFE, 0x06, 0x00, 0x05, 0x00, 0x00, 0x8D, 0xC4}; +static uint8_t zg09_set_active[8]={0xFE, 0x06, 0x00, 0x05, 0x00, 0x01, 0x4C, 0x04}; +static uint8_t zg09_read_instruction[8]={0xFE, 0x03, 0x00, 0x0B, 0x00, 0x01, 0xE1, 0xC7}; + +static struct SensorDevice zg09; + +static struct SensorProductInfo info = +{ + SENSOR_ABILITY_CO2, + "ZyAura", + "ZG09", +}; + +/** + * @description: Open ZG09 sensor device + * @param sdev - sensor device pointer + * @return success: 1 , failure: other + */ +#ifdef ADD_NUTTX_FETURES +static int SensorDeviceOpen(struct SensorDevice *sdev) +{ + int result = 0; + + sdev->fd = PrivOpen(SENSOR_DEVICE_ZG09_DEV, O_RDWR); + if (sdev->fd < 0) { + printf("open %s error\n", SENSOR_DEVICE_ZG09_DEV); + return -1; + } + + result = sdev->done->ioctl(sdev, SENSOR_DEVICE_PASSIVE); + if (result != 0){ + printf("SensorDeviceOpen:ioctl failed, status=%d\n", result); + } + + return result; +} +#else +static int SensorDeviceOpen(struct SensorDevice *sdev) +{ + int result = 0; + + sdev->fd = PrivOpen(SENSOR_DEVICE_ZG09_DEV, O_RDWR); + if (sdev->fd < 0) { + printf("open %s error\n", SENSOR_DEVICE_ZG09_DEV); + return -1; + } + + struct SerialDataCfg cfg; + cfg.serial_baud_rate = BAUD_RATE_9600; + cfg.serial_data_bits = DATA_BITS_8; + cfg.serial_stop_bits = STOP_BITS_1; + cfg.serial_buffer_size = 128; + cfg.serial_parity_mode = PARITY_NONE; + cfg.serial_bit_order = 0; + cfg.serial_invert_mode = 0; +#ifdef SENSOR_ZG09_DRIVER_EXTUART + cfg.ext_uart_no = SENSOR_DEVICE_ZG09_DEV_EXT_PORT; + cfg.port_configure = PORT_CFG_INIT; +#endif + + struct PrivIoctlCfg ioctl_cfg; + ioctl_cfg.ioctl_driver_type = SERIAL_TYPE; + ioctl_cfg.args = &cfg; + result = PrivIoctl(sdev->fd, OPE_INT, &ioctl_cfg); + + sdev->done->ioctl(sdev, SENSOR_DEVICE_PASSIVE); + + return result; +} +#endif + +/** + * @description: Read sensor device + * @param sdev - sensor device pointer + * @param len - the length of the read data + * @return get data length + */ +static int SensorDeviceRead(struct SensorDevice *sdev, size_t len) +{ + uint8_t tmp = 0; + int timeout = 0; + while (1) { + PrivRead(sdev->fd, &tmp, 1); + if ((tmp == 0xFE) || (timeout >= 1000)) + break; + PrivTaskDelay(10); + ++timeout; + } + + if(tmp != 0xFE) + return -1; + + uint8_t idx = 0; + sdev->buffer[idx++] = tmp; + + while ((idx < len) && (timeout < 1000)) { + if (PrivRead(sdev->fd, &tmp, 1) == 1) { + timeout = 0; + sdev->buffer[idx++] = tmp; + } + ++timeout; + } + + return idx; +} + +/** + * @description: set sensor work mode + * @param sdev - sensor device pointer + * @param cmd - mode command + * @return success: 1 , failure: -1 + */ +static int SensorDeviceIoctl(struct SensorDevice *sdev, int cmd) +{ + switch (cmd) + { + case SENSOR_DEVICE_PASSIVE: + PrivWrite(sdev->fd, zg09_set_passive, 8); + sdev->done->read(sdev, 8); + if (memcmp(sdev->buffer, zg09_set_passive, 8) == 0) { + sdev->status = SENSOR_DEVICE_PASSIVE; + return 0; + } + break; + + case SENSOR_DEVICE_ACTIVE: + PrivWrite(sdev->fd, zg09_set_active, 8); + sdev->done->read(sdev, 8); + if (memcmp(sdev->buffer, zg09_set_active, 8) == 0) { + sdev->status = SENSOR_DEVICE_ACTIVE; + return 0; + } + break; + + default: + printf("This device does not have this command!\n"); + break; + } + + return -1; +} + +static struct SensorDone done = +{ + SensorDeviceOpen, + NULL, + SensorDeviceRead, + NULL, + SensorDeviceIoctl, +}; + +/** + * @description: Init ZG09 sensor and register + * @return void + */ +static void SensorDeviceZg09Init(void) +{ + zg09.name = SENSOR_DEVICE_ZG09; + zg09.info = &info; + zg09.done = &done; + + SensorDeviceRegister(&zg09); +} + + + +static struct SensorQuantity zg09_co2; + +/** + * @description: Analysis ZG09 CO2 result + * @param quant - sensor quantity pointer + * @return quantity value + */ +static int32_t QuantityRead(struct SensorQuantity *quant) +{ + if (!quant) + return -1; + + uint32_t result; + if (quant->sdev->done->read != NULL) { + if(quant->sdev->status == SENSOR_DEVICE_PASSIVE) { + PrivWrite(quant->sdev->fd, zg09_read_instruction, 8); + quant->sdev->done->read(quant->sdev, 7); + if(Crc16(quant->sdev->buffer, 5) == ((uint32_t)quant->sdev->buffer[6] << 8) + ((uint32_t)quant->sdev->buffer[5])) { + result = (uint32_t)quant->sdev->buffer[3] * 256 + (uint32_t)quant->sdev->buffer[4]; + if (result > quant->value.max_value) + quant->value.max_value = result; + else if (result < quant->value.min_value) + quant->value.min_value = result; + quant->value.last_value = result; + + return result; + }else{ + printf("This reading is wrong\n"); + result = SENSOR_QUANTITY_VALUE_ERROR; + return result; + } + } + if (quant->sdev->status == SENSOR_DEVICE_ACTIVE) { + printf("Please set passive mode.\n"); + } + }else{ + printf("%s don't have read done.\n", quant->name); + } + + return -1; +} + +/** + * @description: Init ZG09 CO2 quantity and register + * @return 0 + */ +int Zg09Co2Init(void) +{ + SensorDeviceZg09Init(); + + zg09_co2.name = SENSOR_QUANTITY_ZG09_CO2; + zg09_co2.type = SENSOR_QUANTITY_CO2; + zg09_co2.value.decimal_places = 0; + zg09_co2.value.max_std = 1000; + zg09_co2.value.min_std = 350; + zg09_co2.value.last_value = SENSOR_QUANTITY_VALUE_ERROR; + zg09_co2.value.max_value = SENSOR_QUANTITY_VALUE_ERROR; + zg09_co2.value.min_value = SENSOR_QUANTITY_VALUE_ERROR; + zg09_co2.sdev = &zg09; + zg09_co2.ReadValue = QuantityRead; + + SensorQuantityRegister(&zg09_co2); + + return 0; +} \ No newline at end of file diff --git a/APP_Framework/Framework/sensor/hcho/Kconfig b/APP_Framework/Framework/sensor/hcho/Kconfig new file mode 100644 index 0000000..cd87003 --- /dev/null +++ b/APP_Framework/Framework/sensor/hcho/Kconfig @@ -0,0 +1,65 @@ + +config SENSOR_TB600B_WQ_HCHO1OS + bool "Using TB600B WQ_HCHO1OS" + default n + + if SENSOR_TB600B_WQ_HCHO1OS + config SENSOR_DEVICE_TB600B_WQ_HCHO1OS + string "tb600b wq_hcho1os sensor name" + default "tb600b_wq_hcho1os_1" + + config SENSOR_QUANTITY_TB600B_HCHO + string "tb600b wq_hcho1os quantity name" + default "hcho_1" + + if ADD_XIZI_FETURES + config SENSOR_TB600B_WQ_HCHO1OS_DRIVER_EXTUART + bool "Using extra uart to support tb600b wq_hcho1os" + default y + + config SENSOR_DEVICE_TB600B_WQ_HCHO1OS_DEV + string "tb600b wq_hcho1os device uart path" + default "/dev/uart2_dev2" + depends on !SENSOR_TB600B_WQ_HCHO1OS_DRIVER_EXTUART + + if SENSOR_TB600B_WQ_HCHO1OS_DRIVER_EXTUART + config SENSOR_DEVICE_TB600B_WQ_HCHO1OS_DEV + string "tb600b wq_hcho1os device extra uart path" + default "/dev/extuart_dev5" + + config SENSOR_DEVICE_TB600B_WQ_HCHO1OS_DEV_EXT_PORT + int "if TB600B_WQ_HCHO1OS device using extuart, choose port" + default "5" + endif + endif + + if ADD_NUTTX_FETURES + config SENSOR_DEVICE_TB600B_WQ_HCHO1OS_DEV + string "tb600b wq_hcho1os device uart path" + default "/dev/ttyS1" + ---help--- + If USART1 is selected, then fill in /dev/ttyS1 here. + + endif + + if ADD_RTTHREAD_FETURES + config SENSOR_TB600B_WQ_HCHO1OS_DRIVER_EXTUART + bool "Using extra uart to support tb600b wq_hcho1os" + default y + + config SENSOR_DEVICE_TB600B_WQ_HCHO1OS_DEV + string "tb600b wq_hcho1os device uart path" + default "/dev/uart2" + depends on !SENSOR_TB600B_WQ_HCHO1OS_DRIVER_EXTUART + + if SENSOR_TB600B_WQ_HCHO1OS_DRIVER_EXTUART + config SENSOR_DEVICE_TB600B_WQ_HCHO1OS_DEV + string "tb600b wq_hcho1os device extra uart path" + default "/dev/extuart_dev1" + + config SENSOR_DEVICE_TB600B_WQ_HCHO1OS_DEV_EXT_PORT + int "if TB600B_WQ_HCHO1OS device using extuart, choose port" + default "1" + endif + endif + endif diff --git a/APP_Framework/Framework/sensor/hcho/Make.defs b/APP_Framework/Framework/sensor/hcho/Make.defs new file mode 100644 index 0000000..d3012ad --- /dev/null +++ b/APP_Framework/Framework/sensor/hcho/Make.defs @@ -0,0 +1,4 @@ +############################################################################ +# APP_Framework/Framework/sensor/hcho/Make.defs +############################################################################ +include $(wildcard $(APPDIR)/../../../APP_Framework/Framework/sensor/hcho/*/Make.defs) diff --git a/APP_Framework/Framework/sensor/hcho/Makefile b/APP_Framework/Framework/sensor/hcho/Makefile new file mode 100644 index 0000000..c30211f --- /dev/null +++ b/APP_Framework/Framework/sensor/hcho/Makefile @@ -0,0 +1,5 @@ +ifeq ($(CONFIG_SENSOR_TB600B_WQ_HCHO1OS),y) + SRC_DIR += tb600b_wq_hcho1os +endif + +include $(KERNEL_ROOT)/compiler.mk diff --git a/APP_Framework/Framework/sensor/hcho/SConscript b/APP_Framework/Framework/sensor/hcho/SConscript new file mode 100644 index 0000000..f307e3f --- /dev/null +++ b/APP_Framework/Framework/sensor/hcho/SConscript @@ -0,0 +1,14 @@ +import os +Import('RTT_ROOT') +from building import * + +cwd = GetCurrentDir() +objs = [] +list = os.listdir(cwd) + +for d in list: + path = os.path.join(cwd, d) + if os.path.isfile(os.path.join(path, 'SConscript')): + objs = objs + SConscript(os.path.join(path, 'SConscript')) + +Return('objs') diff --git a/APP_Framework/Framework/sensor/hcho/tb600b_wq_hcho1os/Make.defs b/APP_Framework/Framework/sensor/hcho/tb600b_wq_hcho1os/Make.defs new file mode 100644 index 0000000..3d040f6 --- /dev/null +++ b/APP_Framework/Framework/sensor/hcho/tb600b_wq_hcho1os/Make.defs @@ -0,0 +1,6 @@ +############################################################################ +# APP_Framework/Framework/sensor/hcho/tb600b_wq_hcho1os/Make.defs +############################################################################ +ifneq ($(CONFIG_SENSOR_TB600B_WQ_HCHO1OS),) +CONFIGURED_APPS += $(APPDIR)/../../../APP_Framework/Framework/sensor/hcho/tb600b_wq_hcho1os +endif diff --git a/APP_Framework/Framework/sensor/hcho/tb600b_wq_hcho1os/Makefile b/APP_Framework/Framework/sensor/hcho/tb600b_wq_hcho1os/Makefile new file mode 100644 index 0000000..9e7dd48 --- /dev/null +++ b/APP_Framework/Framework/sensor/hcho/tb600b_wq_hcho1os/Makefile @@ -0,0 +1,12 @@ +include $(KERNEL_ROOT)/.config + +ifeq ($(CONFIG_ADD_NUTTX_FETURES),y) + include $(APPDIR)/Make.defs + CSRCS += tb600b_wq_hcho1os.c + include $(APPDIR)/Application.mk +endif + +ifeq ($(CONFIG_ADD_XIZI_FETURES),y) + SRC_FILES := tb600b_wq_hcho1os.c + include $(KERNEL_ROOT)/compiler.mk +endif diff --git a/APP_Framework/Framework/sensor/hcho/tb600b_wq_hcho1os/SConscript b/APP_Framework/Framework/sensor/hcho/tb600b_wq_hcho1os/SConscript new file mode 100644 index 0000000..e8f068b --- /dev/null +++ b/APP_Framework/Framework/sensor/hcho/tb600b_wq_hcho1os/SConscript @@ -0,0 +1,10 @@ +from building import * +import os + +cwd = GetCurrentDir() +src = [] +if GetDepend(['SENSOR_TB600B_WQ_HCHO1OS']): + src += ['tb600b_wq_hcho1os.c'] +group = DefineGroup('sensor hcho', src, depend = [], CPPPATH = [cwd]) + +Return('group') \ No newline at end of file diff --git a/APP_Framework/Framework/sensor/hcho/tb600b_wq_hcho1os/tb600b_wq_hcho1os.c b/APP_Framework/Framework/sensor/hcho/tb600b_wq_hcho1os/tb600b_wq_hcho1os.c new file mode 100644 index 0000000..d1c103c --- /dev/null +++ b/APP_Framework/Framework/sensor/hcho/tb600b_wq_hcho1os/tb600b_wq_hcho1os.c @@ -0,0 +1,235 @@ +/* +* Copyright (c) 2020 AIIT XUOS Lab +* XiUOS is licensed under Mulan PSL v2. +* You can use this software according to the terms and conditions of the Mulan PSL v2. +* You may obtain a copy of Mulan PSL v2 at: +* http://license.coscl.org.cn/MulanPSL2 +* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, +* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, +* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. +* See the Mulan PSL v2 for more details. +*/ + +/** + * @file wq_hcho1os.c + * @brief wq_hcho1os driver base sensor + * @version 1.0 + * @author AIIT XUOS Lab + * @date 2021.12.15 + */ + +#include + +static struct SensorDevice wq_hcho1os; +static uint8_t ReadInstruction[9]; + +static struct SensorProductInfo info = +{ + SENSOR_ABILITY_HCHO, + "AQS", + "TB600B_WQ_HCHO1OS", +}; + +/** + * @description: Open TB600B WQ_HCHO1OS sensor device + * @param sdev - sensor device pointer + * @return success: 1 , failure: other + */ +#ifdef ADD_NUTTX_FETURES +static int SensorDeviceOpen(struct SensorDevice *sdev) +{ + sdev->fd = PrivOpen(SENSOR_DEVICE_TB600B_WQ_HCHO1OS_DEV, O_RDWR); + if (sdev->fd < 0) { + printf("open %s error\n", SENSOR_DEVICE_TB600B_WQ_HCHO1OS_DEV); + return -1; + } + + return sdev->fd; +} +#else +static int SensorDeviceOpen(struct SensorDevice *sdev) +{ + int result = 0; + + sdev->fd = PrivOpen(SENSOR_DEVICE_TB600B_WQ_HCHO1OS_DEV, O_RDWR); + if (sdev->fd < 0) { + printf("open %s error\n", SENSOR_DEVICE_TB600B_WQ_HCHO1OS_DEV); + return -1; + } + + struct SerialDataCfg cfg; + cfg.serial_baud_rate = BAUD_RATE_9600; + cfg.serial_data_bits = DATA_BITS_8; + cfg.serial_stop_bits = STOP_BITS_1; + cfg.serial_buffer_size = 128; + cfg.serial_parity_mode = PARITY_NONE; + cfg.serial_bit_order = 0; + cfg.serial_invert_mode = 0; +#ifdef SENSOR_TB600B_WQ_HCHO1OS_DRIVER_EXTUART + cfg.ext_uart_no = SENSOR_DEVICE_TB600B_WQ_HCHO1OS_DEV_EXT_PORT; + cfg.port_configure = PORT_CFG_INIT; +#endif + + struct PrivIoctlCfg ioctl_cfg; + ioctl_cfg.ioctl_driver_type = SERIAL_TYPE; + ioctl_cfg.args = &cfg; + result = PrivIoctl(sdev->fd, OPE_INT, &ioctl_cfg); + + return result; +} +#endif + +/** + * @description: Read sensor device + * @param sdev - sensor device pointer + * @param len - the length of the read data + * @return get data length + */ +static int SensorDeviceRead(struct SensorDevice *sdev, size_t len) +{ + uint8_t tmp = 0; + uint8_t idx = 0; + + /* this instruction will read gas with temperature and humidity,return 9 datas*/ + ReadInstruction[0] = 0xFF; + ReadInstruction[1] = 0x01; + ReadInstruction[2] = 0x86; + ReadInstruction[3] = 0x00; + ReadInstruction[4] = 0x00; + ReadInstruction[5] = 0x00; + ReadInstruction[6] = 0x00; + ReadInstruction[7] = 0x00; + ReadInstruction[8] = 0x79; + + PrivWrite(sdev->fd, ReadInstruction, 9); + + for(idx = 0; idx < 9; idx++) + { + if (PrivRead(sdev->fd, &tmp, 1) == 1) { + sdev->buffer[idx] = tmp; + } + } + + return idx; +} +/** + * @description: Read sensor device + * @param sdev - sensor device pointer + * @param len - the length of the read data + * @return get data length + */ +static int SensorDeviceWrite(struct SensorDevice *sdev, const void *buf, size_t len) +{ + return PrivWrite(sdev->fd, buf, len); + +} + +static struct SensorDone done = +{ + SensorDeviceOpen, + NULL, + SensorDeviceRead, + SensorDeviceWrite, + NULL, +}; + +/** + * @description: Init TB600B WQ_HCHO1OS sensor and register + * @return void + */ +static void SensorDeviceTb600bHcho1osInit(void) +{ + wq_hcho1os.name = SENSOR_DEVICE_TB600B_WQ_HCHO1OS; + wq_hcho1os.info = &info; + wq_hcho1os.done = &done; + + SensorDeviceRegister(&wq_hcho1os); +} + +static struct SensorQuantity wq_hcho1os_hcho; + +/* check data*/ +static uint8_t getCheckSum(uint8_t *packet) +{ + uint8_t i; + uint8_t checksum = 0; + for( i = 1; i < 12; i++) + { + checksum += packet[i]; + } + checksum = ~checksum + 1; + + return checksum; +} + +/** + * @description: Analysis TB600B WQ_HCHO1OS result + * @param quant - sensor quantity pointer + * @return quantity value + */ +static int32_t QuantityRead(struct SensorQuantity *quant) +{ + if (!quant) + return -1; + + uint32_t len = 0; + uint8_t checksum = 0; + uint16_t ppb, ugm3; + + if (quant->sdev->done->read != NULL) { + if(quant->sdev->status == SENSOR_DEVICE_PASSIVE) { + len = quant->sdev->done->read(quant->sdev, 9); + if (len == 0) + { + printf("error read data length = 0.\n"); + return -1; + } + checksum = getCheckSum(quant->sdev->buffer); + if(checksum == quant->sdev->buffer[8]) + { + ugm3 = (uint16_t)quant->sdev->buffer[2] * 256 + (uint16_t)quant->sdev->buffer[3]; + ppb = (uint16_t)quant->sdev->buffer[6] * 256 + (uint16_t)quant->sdev->buffer[7]; + + printf("Formaldehyde concentration is : %dug/m³(%dppb)\n", ugm3, ppb); + return ppb; + } + else + { + printf("This reading is wrong\n"); + return SENSOR_QUANTITY_VALUE_ERROR; + } + } + if (quant->sdev->status == SENSOR_DEVICE_ACTIVE) + { + printf("Please set passive mode.\n"); + } + }else{ + printf("%s don't have read done.\n", quant->name); + } + + return -1; +} + +/** + * @description: Init TB600B WQ_HCHO1OS quantity and register + * @return 0 + */ +int Tb600bWqHcho1osInit(void) +{ + SensorDeviceTb600bHcho1osInit(); + + wq_hcho1os_hcho.name = SENSOR_QUANTITY_TB600B_HCHO; + wq_hcho1os_hcho.type = SENSOR_QUANTITY_HCHO; + wq_hcho1os_hcho.value.decimal_places = 0; + wq_hcho1os_hcho.value.max_std = SENSOR_QUANTITY_VALUE_ERROR; + wq_hcho1os_hcho.value.min_std = SENSOR_QUANTITY_VALUE_ERROR; + wq_hcho1os_hcho.value.last_value = SENSOR_QUANTITY_VALUE_ERROR; + wq_hcho1os_hcho.value.max_value = SENSOR_QUANTITY_VALUE_ERROR; + wq_hcho1os_hcho.value.min_value = SENSOR_QUANTITY_VALUE_ERROR; + wq_hcho1os_hcho.sdev = &wq_hcho1os; + wq_hcho1os_hcho.ReadValue = QuantityRead; + + SensorQuantityRegister(&wq_hcho1os_hcho); + + return 0; +} \ No newline at end of file diff --git a/APP_Framework/Framework/sensor/humidity/Kconfig b/APP_Framework/Framework/sensor/humidity/Kconfig new file mode 100644 index 0000000..b473ef1 --- /dev/null +++ b/APP_Framework/Framework/sensor/humidity/Kconfig @@ -0,0 +1,40 @@ + +config SENSOR_HS300X_HUMIDITY + bool "Using HS300x for humidity" + default n + + if SENSOR_HS300X_HUMIDITY + config SENSOR_DEVICE_HS300X + string "HS300x sensor name" + default "hs300x_1" + + config SENSOR_QUANTITY_HS300X_HUMIDITY + string "HS300x quantity name" + default "humidity_1" + + if ADD_XIZI_FETURES + config SENSOR_DEVICE_HS300X_DEV + string "HS300x device name" + default "/dev/i2c1_dev0" + + config SENSOR_DEVICE_HS300X_I2C_ADDR + hex "HS300x device i2c address" + default 0x44 + endif + + + if ADD_NUTTX_FETURES + config SENSOR_DEVICE_HS300X_DEV + string "HS300x device name" + default "/dev/i2c1_dev0" + + config SENSOR_DEVICE_HS300X_I2C_ADDR + hex "HS300x device i2c address" + default 0x44 + + endif + + if ADD_RTTHREAD_FETURES + + endif + endif diff --git a/APP_Framework/Framework/sensor/humidity/Make.defs b/APP_Framework/Framework/sensor/humidity/Make.defs new file mode 100644 index 0000000..affd5db --- /dev/null +++ b/APP_Framework/Framework/sensor/humidity/Make.defs @@ -0,0 +1,4 @@ +############################################################################ +# APP_Framework/Framework/sensor/humidity/Make.defs +############################################################################ +include $(wildcard $(APPDIR)/../../../APP_Framework/Framework/sensor/humidity/*/Make.defs) diff --git a/APP_Framework/Framework/sensor/humidity/Makefile b/APP_Framework/Framework/sensor/humidity/Makefile new file mode 100644 index 0000000..979a424 --- /dev/null +++ b/APP_Framework/Framework/sensor/humidity/Makefile @@ -0,0 +1,5 @@ +ifeq ($(CONFIG_SENSOR_HS300X_HUMIDITY),y) + SRC_DIR += hs300x_humi +endif + +include $(KERNEL_ROOT)/compiler.mk diff --git a/APP_Framework/Framework/sensor/humidity/hs300x_humi/Make.defs b/APP_Framework/Framework/sensor/humidity/hs300x_humi/Make.defs new file mode 100644 index 0000000..76a42c6 --- /dev/null +++ b/APP_Framework/Framework/sensor/humidity/hs300x_humi/Make.defs @@ -0,0 +1,6 @@ +############################################################################ +# APP_Framework/Framework/sensor/humidity/hs300x_humi/Make.defs +############################################################################ +ifneq ($(CONFIG_SENSOR_HS300X_HUMIDITY),) +CONFIGURED_APPS += $(APPDIR)/../../../APP_Framework/Framework/sensor/humidity/hs300x_humi +endif diff --git a/APP_Framework/Framework/sensor/humidity/hs300x_humi/Makefile b/APP_Framework/Framework/sensor/humidity/hs300x_humi/Makefile new file mode 100644 index 0000000..58f85b1 --- /dev/null +++ b/APP_Framework/Framework/sensor/humidity/hs300x_humi/Makefile @@ -0,0 +1,13 @@ +include $(KERNEL_ROOT)/.config +ifeq ($(CONFIG_ADD_NUTTX_FETURES),y) + include $(APPDIR)/Make.defs + CSRCS += hs300x_humi.c + include $(APPDIR)/Application.mk + +endif + +ifeq ($(CONFIG_ADD_XIZI_FETURES),y) + SRC_FILES := hs300x_humi.c + include $(KERNEL_ROOT)/compiler.mk + +endif \ No newline at end of file diff --git a/APP_Framework/Framework/sensor/humidity/hs300x_humi/hs300x_humi.c b/APP_Framework/Framework/sensor/humidity/hs300x_humi/hs300x_humi.c new file mode 100644 index 0000000..e999b78 --- /dev/null +++ b/APP_Framework/Framework/sensor/humidity/hs300x_humi/hs300x_humi.c @@ -0,0 +1,157 @@ +/* +* Copyright (c) 2020 AIIT XUOS Lab +* XiUOS is licensed under Mulan PSL v2. +* You can use this software according to the terms and conditions of the Mulan PSL v2. +* You may obtain a copy of Mulan PSL v2 at: +* http://license.coscl.org.cn/MulanPSL2 +* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, +* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, +* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. +* See the Mulan PSL v2 for more details. +*/ + +/** + * @file hs300x_humi.c + * @brief HS300x humidity driver base sensor + * @version 1.0 + * @author AIIT XUOS Lab + * @date 2021.04.22 + */ + +#include + +static struct SensorDevice hs300x; + +static struct SensorProductInfo info = +{ + (SENSOR_ABILITY_HUMI | SENSOR_ABILITY_TEMP), + "Renesas", + "HS300x", +}; + +/** + * @description: Open HS300x sensor device + * @param sdev - sensor device pointer + * @return success : 0 error : -1 + */ +static int SensorDeviceOpen(struct SensorDevice *sdev) +{ +#ifdef ADD_NUTTX_FETURES + sdev->fd = PrivOpen(SENSOR_DEVICE_HS300X_DEV, O_RDWR); + + return sdev->fd; + +#else + int result; + uint16_t i2c_dev_addr = SENSOR_DEVICE_HS300X_I2C_ADDR; + + sdev->fd = PrivOpen(SENSOR_DEVICE_HS300X_DEV, O_RDWR); + + if (sdev->fd < 0) { + printf("open %s error\n", SENSOR_DEVICE_HS300X_DEV); + return -1; + } + + struct PrivIoctlCfg ioctl_cfg; + ioctl_cfg.ioctl_driver_type = I2C_TYPE; + ioctl_cfg.args = &i2c_dev_addr; + result = PrivIoctl(sdev->fd, OPE_INT, &ioctl_cfg); + + return result; +#endif +} + +/** + * @description: Read sensor device + * @param sdev - sensor device pointer + * @param len - the length of the read data + * @return success: 0 , failure: -1 + */ +static int SensorDeviceRead(struct SensorDevice *sdev, size_t len) +{ + //Read i2c device data from i2c device address + if (PrivRead(sdev->fd, sdev->buffer, len) < 0) + return -1; + + return 0; +} + +static struct SensorDone done = +{ + SensorDeviceOpen, + NULL, + SensorDeviceRead, + NULL, + NULL, +}; + +/** + * @description: Init HS300x sensor and register + * @return void + */ +static void SensorDeviceHs300xInit(void) +{ + hs300x.name = SENSOR_DEVICE_HS300X; + hs300x.info = &info; + hs300x.done = &done; + hs300x.status = SENSOR_DEVICE_PASSIVE; + + SensorDeviceRegister(&hs300x); +} + + + +static struct SensorQuantity hs300x_humidity; + +/** + * @description: Analysis HS300x humidity result + * @param quant - sensor quantity pointer + * @return quantity value + */ +static int32_t ReadHumidity(struct SensorQuantity *quant) +{ + if (!quant) + return -1; + + float result = 0.0; + if (quant->sdev->done->read != NULL) { + if (quant->sdev->status == SENSOR_DEVICE_PASSIVE) { + quant->sdev->done->read(quant->sdev, 4); + quant->sdev->done->read(quant->sdev, 4); /* It takes two reads to get the data right */ + result = ((quant->sdev->buffer[0] << 8 | quant->sdev->buffer[1] ) & 0x3fff) * 100.0 / ( (1 << 14) - 1); + + return (int32_t)(result * 10); + } + if (quant->sdev->status == SENSOR_DEVICE_ACTIVE) { + printf("Please set passive mode.\n"); + } + }else{ + printf("%s don't have read done.\n", quant->name); + } + + return -1; +} + +/** + * @description: Init HS300x humidity quantity and register + * @return 0 + */ +int Hs300xHumidityInit(void) +{ + SensorDeviceHs300xInit(); + + hs300x_humidity.name = SENSOR_QUANTITY_HS300X_HUMIDITY; + hs300x_humidity.type = SENSOR_QUANTITY_HUMI; + hs300x_humidity.value.decimal_places = 1; + hs300x_humidity.value.max_std = 1000; + hs300x_humidity.value.min_std = 0; + hs300x_humidity.value.last_value = SENSOR_QUANTITY_VALUE_ERROR; + hs300x_humidity.value.max_value = SENSOR_QUANTITY_VALUE_ERROR; + hs300x_humidity.value.min_value = SENSOR_QUANTITY_VALUE_ERROR; + hs300x_humidity.sdev = &hs300x; + hs300x_humidity.ReadValue = ReadHumidity; + + SensorQuantityRegister(&hs300x_humidity); + + return 0; +} \ No newline at end of file diff --git a/APP_Framework/Framework/sensor/iaq/Kconfig b/APP_Framework/Framework/sensor/iaq/Kconfig new file mode 100644 index 0000000..6b52c1d --- /dev/null +++ b/APP_Framework/Framework/sensor/iaq/Kconfig @@ -0,0 +1,48 @@ + +config SENSOR_TB600B_IAQ10 + bool "Using TB600B IAQ10" + default n + + if SENSOR_TB600B_IAQ10 + config SENSOR_DEVICE_TB600B_IAQ10 + string "tb600b iaq10 sensor name" + default "tb600b_iaq10_1" + + config SENSOR_QUANTITY_TB600B_IAQ + string "tb600b iaq10 quantity name" + default "iaq_1" + + if ADD_XIZI_FETURES + config SENSOR_TB600B_IAQ10_DRIVER_EXTUART + bool "Using extra uart to support tb600b iaq10" + default y + + config SENSOR_DEVICE_TB600B_IAQ10_DEV + string "tb600b iaq10 device uart path" + default "/dev/uart2_dev2" + depends on !SENSOR_TB600B_IAQ10_DRIVER_EXTUART + + if SENSOR_TB600B_IAQ10_DRIVER_EXTUART + config SENSOR_DEVICE_TB600B_IAQ10_DEV + string "tb600b iaq10 device extra uart path" + default "/dev/extuart_dev5" + + config SENSOR_DEVICE_TB600B_IAQ10_DEV_EXT_PORT + int "if TB600B_IAQ10 device using extuart, choose port" + default "5" + endif + endif + + if ADD_NUTTX_FETURES + config SENSOR_DEVICE_TB600B_IAQ10_DEV + string "tb600b iaq10 device uart path" + default "/dev/ttyS1" + ---help--- + If USART1 is selected, then fill in /dev/ttyS1 here. + + endif + + if ADD_RTTHREAD_FETURES + + endif + endif diff --git a/APP_Framework/Framework/sensor/iaq/Make.defs b/APP_Framework/Framework/sensor/iaq/Make.defs new file mode 100644 index 0000000..96a7b89 --- /dev/null +++ b/APP_Framework/Framework/sensor/iaq/Make.defs @@ -0,0 +1,4 @@ +############################################################################ +# APP_Framework/Framework/sensor/iaq/Make.defs +############################################################################ +include $(wildcard $(APPDIR)/../../../APP_Framework/Framework/sensor/iaq/*/Make.defs) diff --git a/APP_Framework/Framework/sensor/iaq/Makefile b/APP_Framework/Framework/sensor/iaq/Makefile new file mode 100644 index 0000000..775a2d2 --- /dev/null +++ b/APP_Framework/Framework/sensor/iaq/Makefile @@ -0,0 +1,5 @@ +ifeq ($(CONFIG_SENSOR_TB600B_IAQ10),y) + SRC_DIR += tb600b_iaq10 +endif + +include $(KERNEL_ROOT)/compiler.mk diff --git a/APP_Framework/Framework/sensor/iaq/tb600b_iaq10/Make.defs b/APP_Framework/Framework/sensor/iaq/tb600b_iaq10/Make.defs new file mode 100644 index 0000000..217e299 --- /dev/null +++ b/APP_Framework/Framework/sensor/iaq/tb600b_iaq10/Make.defs @@ -0,0 +1,6 @@ +############################################################################ +# APP_Framework/Framework/sensor/iaq/tb600b_iaq10/Make.defs +############################################################################ +ifneq ($(CONFIG_SENSOR_TB600B_IAQ10),) +CONFIGURED_APPS += $(APPDIR)/../../../APP_Framework/Framework/sensor/iaq/tb600b_iaq10 +endif diff --git a/APP_Framework/Framework/sensor/iaq/tb600b_iaq10/Makefile b/APP_Framework/Framework/sensor/iaq/tb600b_iaq10/Makefile new file mode 100644 index 0000000..39da6a6 --- /dev/null +++ b/APP_Framework/Framework/sensor/iaq/tb600b_iaq10/Makefile @@ -0,0 +1,12 @@ +include $(KERNEL_ROOT)/.config +ifeq ($(CONFIG_ADD_NUTTX_FETURES),y) + include $(APPDIR)/Make.defs + CSRCS += tb600b_iaq10.c + include $(APPDIR)/Application.mk +endif + + +ifeq ($(CONFIG_ADD_XIZI_FETURES),y) + SRC_FILES := tb600b_iaq10.c + include $(KERNEL_ROOT)/compiler.mk +endif diff --git a/APP_Framework/Framework/sensor/iaq/tb600b_iaq10/tb600b_iaq10.c b/APP_Framework/Framework/sensor/iaq/tb600b_iaq10/tb600b_iaq10.c new file mode 100644 index 0000000..14e2e13 --- /dev/null +++ b/APP_Framework/Framework/sensor/iaq/tb600b_iaq10/tb600b_iaq10.c @@ -0,0 +1,247 @@ +/* +* Copyright (c) 2020 AIIT XUOS Lab +* XiUOS is licensed under Mulan PSL v2. +* You can use this software according to the terms and conditions of the Mulan PSL v2. +* You may obtain a copy of Mulan PSL v2 at: +* http://license.coscl.org.cn/MulanPSL2 +* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, +* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, +* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. +* See the Mulan PSL v2 for more details. +*/ + +/** + * @file tb600b_iaq10.c + * @brief tb600b_iaq10 driver base sensor + * @version 1.0 + * @author AIIT XUOS Lab + * @date 2021.12.14 + */ + +#include + +static struct SensorDevice tb600b_iaq10; +static uint8_t ReadInstruction[9]; + +struct iaq_data { + uint16_t gas; + uint8_t TH; + uint8_t TL; + uint8_t RhH; + uint8_t RhL; +}; + +static struct SensorProductInfo info = +{ + SENSOR_ABILITY_IAQ, + "AQS", + "TB600B_IAQ10", +}; + +/** + * @description: Open tb600b_iaq10 sensor device + * @param sdev - sensor device pointer + * @return success: 1 , failure: other + */ +#ifdef ADD_NUTTX_FETURES +static int SensorDeviceOpen(struct SensorDevice *sdev) +{ + sdev->fd = PrivOpen(SENSOR_DEVICE_TB600B_IAQ10_DEV, O_RDWR); + if (sdev->fd < 0) { + printf("open %s error\n", SENSOR_DEVICE_TB600B_IAQ10_DEV); + } + + return sdev->fd; +} +#else +static int SensorDeviceOpen(struct SensorDevice *sdev) +{ + int result = 0; + + sdev->fd = PrivOpen(SENSOR_DEVICE_TB600B_IAQ10_DEV, O_RDWR); + if (sdev->fd < 0) { + printf("open %s error\n", SENSOR_DEVICE_TB600B_IAQ10_DEV); + return -1; + } + + struct SerialDataCfg cfg; + cfg.serial_baud_rate = BAUD_RATE_9600; + cfg.serial_data_bits = DATA_BITS_8; + cfg.serial_stop_bits = STOP_BITS_1; + cfg.serial_buffer_size = 128; + cfg.serial_parity_mode = PARITY_NONE; + cfg.serial_bit_order = 0; + cfg.serial_invert_mode = 0; +#ifdef SENSOR_TB600B_IAQ10_DRIVER_EXTUART + cfg.ext_uart_no = SENSOR_DEVICE_TB600B_IAQ10_DEV_EXT_PORT; + cfg.port_configure = PORT_CFG_INIT; +#endif + + struct PrivIoctlCfg ioctl_cfg; + ioctl_cfg.ioctl_driver_type = SERIAL_TYPE; + ioctl_cfg.args = &cfg; + result = PrivIoctl(sdev->fd, OPE_INT, &ioctl_cfg); + + return result; +} +#endif + +/** + * @description: Read sensor device + * @param sdev - sensor device pointer + * @param len - the length of the read data + * @return get data length + */ +static int SensorDeviceRead(struct SensorDevice *sdev, size_t len) +{ + uint8_t tmp = 0; + uint8_t idx = 0; + int32_t ret = 0; + + /* this instruction will read gas with temperature and humidity,return 13 datas*/ + ReadInstruction[0] = 0xFF; + ReadInstruction[1] = 0x01; + ReadInstruction[2] = 0x87; + ReadInstruction[3] = 0x00; + ReadInstruction[4] = 0x00; + ReadInstruction[5] = 0x00; + ReadInstruction[6] = 0x00; + ReadInstruction[7] = 0x00; + ReadInstruction[8] = 0x78; + + PrivWrite(sdev->fd, ReadInstruction, 9); + + for(idx = 0; idx < 13; idx++) + { + if (PrivRead(sdev->fd, &tmp, 1) == 1) { + sdev->buffer[idx] = tmp; + } + } + + return idx; +} +/** + * @description: Read sensor device + * @param sdev - sensor device pointer + * @param len - the length of the read data + * @return get data length + */ +static int SensorDeviceWrite(struct SensorDevice *sdev, const void *buf, size_t len) +{ + return PrivWrite(sdev->fd, buf, len); + +} + +static struct SensorDone done = +{ + SensorDeviceOpen, + NULL, + SensorDeviceRead, + SensorDeviceWrite, + NULL, +}; + +/** + * @description: Init tb600b_iaq10 sensor and register + * @return void + */ +static void SensorDeviceTb600bIaq10Init(void) +{ + tb600b_iaq10.name = SENSOR_DEVICE_TB600B_IAQ10; + tb600b_iaq10.info = &info; + tb600b_iaq10.done = &done; + + SensorDeviceRegister(&tb600b_iaq10); +} + +static struct SensorQuantity tb600b_iaq10_iaq; + +/* check data*/ +static uint8_t getCheckSum(uint8_t *packet) +{ + uint8_t i; + uint8_t checksum = 0; + for( i = 1; i < 12; i++) + { + checksum += packet[i]; + } + checksum = ~checksum + 1; + + return checksum; +} + +/** + * @description: Analysis tb600b_iaq10 result + * @param quant - sensor quantity pointer + * @return quantity value + */ +static int32_t QuantityRead(struct SensorQuantity *quant) +{ + if (!quant) + return -1; + + uint32_t len = 0; + uint8_t checksum = 0; + uint8_t TH, TL, RhH, RhL; + uint16_t gas; + struct iaq_data result; + + if (quant->sdev->done->read != NULL) { + if(quant->sdev->status == SENSOR_DEVICE_PASSIVE) { + len = quant->sdev->done->read(quant->sdev, 13); + if (len == 0) + { + printf("error read data length = 0.\n"); + return -1; + } + checksum = getCheckSum(quant->sdev->buffer); + if(checksum == quant->sdev->buffer[12]) + { + result.gas = (uint16_t)quant->sdev->buffer[6] * 256 + (uint16_t)quant->sdev->buffer[7]; + result.TH = ((int)((quant->sdev->buffer[8] << 8)|quant->sdev->buffer[9]))/100; + result.TL = ((int)((quant->sdev->buffer[8] << 8)|quant->sdev->buffer[9]))%100; + result.RhH = ((unsigned int)((quant->sdev->buffer[10] << 8)|quant->sdev->buffer[11]))/100; + result.RhL = ((unsigned int)((quant->sdev->buffer[10] << 8)|quant->sdev->buffer[11]))%100; + printf("Gas concentration is : %dppb\nThe temperature is : %d.%d℃\nThe humidity is : %d.%drh%%\n", result.gas, result.TH, result.TL, result.RhH, result.RhL); + return result.gas; + } + else + { + printf("This reading is wrong\n"); + return SENSOR_QUANTITY_VALUE_ERROR; + } + } + if (quant->sdev->status == SENSOR_DEVICE_ACTIVE) + { + printf("Please set passive mode.\n"); + } + }else{ + printf("%s don't have read done.\n", quant->name); + } + + return -1; +} + +/** + * @description: Init tb600b_iaq10 quantity and register + * @return 0 + */ +int Tb600bIaq10IaqInit(void) +{ + SensorDeviceTb600bIaq10Init(); + + tb600b_iaq10_iaq.name = SENSOR_QUANTITY_TB600B_IAQ; + tb600b_iaq10_iaq.type = SENSOR_QUANTITY_IAQ; + tb600b_iaq10_iaq.value.decimal_places = 0; + tb600b_iaq10_iaq.value.max_std = SENSOR_QUANTITY_VALUE_ERROR; + tb600b_iaq10_iaq.value.min_std = SENSOR_QUANTITY_VALUE_ERROR; + tb600b_iaq10_iaq.value.last_value = SENSOR_QUANTITY_VALUE_ERROR; + tb600b_iaq10_iaq.value.max_value = SENSOR_QUANTITY_VALUE_ERROR; + tb600b_iaq10_iaq.value.min_value = SENSOR_QUANTITY_VALUE_ERROR; + tb600b_iaq10_iaq.sdev = &tb600b_iaq10; + tb600b_iaq10_iaq.ReadValue = QuantityRead; + + SensorQuantityRegister(&tb600b_iaq10_iaq); + + return 0; +} \ No newline at end of file diff --git a/APP_Framework/Framework/sensor/pm/Kconfig b/APP_Framework/Framework/sensor/pm/Kconfig new file mode 100644 index 0000000..5c9d706 --- /dev/null +++ b/APP_Framework/Framework/sensor/pm/Kconfig @@ -0,0 +1,74 @@ + +config SENSOR_PS5308 + bool "Using PS5308" + default n + + if SENSOR_PS5308 + config SENSOR_DEVICE_PS5308 + string "PS5308 sensor name" + default "ps5308_1" + + config PS5308_PM1_0 + bool "Using pm1.0 function" + default n + + if PS5308_PM1_0 + config SENSOR_QUANTITY_PS5308_PM1_0 + string "PS5308 quantity PM1.0 name" + default "pm1_0_1" + endif + + config PS5308_PM2_5 + bool "Using pm2.5 function" + default n + + if PS5308_PM2_5 + config SENSOR_QUANTITY_PS5308_PM2_5 + string "PS5308 quantity PM2.5 name" + default "pm2_5_1" + endif + + config PS5308_PM10 + bool "Using pm10 function" + default n + + if PS5308_PM10 + config SENSOR_QUANTITY_PS5308_PM10 + string "PS5308 quantity PM10 name" + default "pm10_1" + endif + + if ADD_XIZI_FETURES + config SENSOR_PS5308_DRIVER_EXTUART + bool "Using extra uart to support PS5308" + default y + + config SENSOR_DEVICE_PS5308_DEV + string "PS5308 device name" + default "/dev/uart2_dev2" + depends on !SENSOR_PS5308_DRIVER_EXTUART + + if SENSOR_PS5308_DRIVER_EXTUART + config SENSOR_DEVICE_PS5308_DEV + string "PS5308 device extra uart path" + default "/dev/extuart_dev4" + + config SENSOR_DEVICE_PS5308_DEV_EXT_PORT + int "if PS5308 device using extuart, choose port" + default "4" + endif + endif + + if ADD_NUTTX_FETURES + config SENSOR_DEVICE_PS5308_DEV + string "PS5308 device name" + default "/dev/ttyS1" + ---help--- + If USART1 is selected, then fill in /dev/ttyS1 here. + + endif + + if ADD_RTTHREAD_FETURES + + endif + endif diff --git a/APP_Framework/Framework/sensor/pm/Make.defs b/APP_Framework/Framework/sensor/pm/Make.defs new file mode 100644 index 0000000..c263424 --- /dev/null +++ b/APP_Framework/Framework/sensor/pm/Make.defs @@ -0,0 +1,4 @@ +############################################################################ +# APP_Framework/Framework/sensor/pm/Make.defs +############################################################################ +include $(wildcard $(APPDIR)/../../../APP_Framework/Framework/sensor/pm/*/Make.defs) diff --git a/APP_Framework/Framework/sensor/pm/Makefile b/APP_Framework/Framework/sensor/pm/Makefile new file mode 100644 index 0000000..fb6558a --- /dev/null +++ b/APP_Framework/Framework/sensor/pm/Makefile @@ -0,0 +1,5 @@ +ifeq ($(CONFIG_SENSOR_PS5308),y) + SRC_DIR += ps5308 +endif + +include $(KERNEL_ROOT)/compiler.mk diff --git a/APP_Framework/Framework/sensor/pm/ps5308/Make.defs b/APP_Framework/Framework/sensor/pm/ps5308/Make.defs new file mode 100644 index 0000000..9299c93 --- /dev/null +++ b/APP_Framework/Framework/sensor/pm/ps5308/Make.defs @@ -0,0 +1,6 @@ +############################################################################ +# APP_Framework/Framework/sensor/pm/ps5308/Make.defs +############################################################################ +ifneq ($(CONFIG_SENSOR_PS5308),) +CONFIGURED_APPS += $(APPDIR)/../../../APP_Framework/Framework/sensor/pm/ps5308 +endif diff --git a/APP_Framework/Framework/sensor/pm/ps5308/Makefile b/APP_Framework/Framework/sensor/pm/ps5308/Makefile new file mode 100644 index 0000000..960968d --- /dev/null +++ b/APP_Framework/Framework/sensor/pm/ps5308/Makefile @@ -0,0 +1,11 @@ +include $(KERNEL_ROOT)/.config +ifeq ($(CONFIG_ADD_NUTTX_FETURES),y) + include $(APPDIR)/Make.defs + CSRCS += ps5308.c + include $(APPDIR)/Application.mk +endif + +ifeq ($(CONFIG_ADD_XIZI_FETURES),y) + SRC_FILES := ps5308.c + include $(KERNEL_ROOT)/compiler.mk +endif diff --git a/APP_Framework/Framework/sensor/pm/ps5308/ps5308.c b/APP_Framework/Framework/sensor/pm/ps5308/ps5308.c new file mode 100644 index 0000000..d46a5a5 --- /dev/null +++ b/APP_Framework/Framework/sensor/pm/ps5308/ps5308.c @@ -0,0 +1,384 @@ +/* +* Copyright (c) 2020 AIIT XUOS Lab +* XiUOS is licensed under Mulan PSL v2. +* You can use this software according to the terms and conditions of the Mulan PSL v2. +* You may obtain a copy of Mulan PSL v2 at: +* http://license.coscl.org.cn/MulanPSL2 +* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, +* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, +* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. +* See the Mulan PSL v2 for more details. +*/ + +/** + * @file ps5308.c + * @brief PS5308 PM1.0, PM2.5, PM10, driver base sensor + * @version 1.0 + * @author AIIT XUOS Lab + * @date 2021.04.22 + */ + +#include + +static struct SensorDevice ps5308; +static pthread_t active_task_id; +static pthread_mutex_t buff_lock; + +static struct SensorProductInfo info = +{ + SENSOR_ABILITY_PM, + "Pulsensor", + "PS5308", +}; + +/** + * @description: Read sensor task + * @param sdev - sensor device pointer + */ +static void *ReadTask(void *parameter) +{ + struct SensorDevice *sdev = (struct SensorDevice *)parameter; + while (1) { + PrivMutexObtain(&buff_lock); + sdev->done->read(sdev, 32); + PrivMutexAbandon(&buff_lock); + PrivTaskDelay(750); + } +} + +/** + * @description: Open PS5308 sensor device + * @param sdev - sensor device pointer + * @return success: 1 , failure: other + */ +#ifdef ADD_NUTTX_FETURES +static int SensorDeviceOpen(struct SensorDevice *sdev) +{ + int result = 0; + + result = PrivMutexCreate(&buff_lock, 0); + if (result != 0){ + printf("SensorDeviceOpen:mutex create failed, status=%d\n", result); + } + + sdev->fd = open(SENSOR_DEVICE_PS5308_DEV, O_RDWR); + if (sdev->fd < 0) { + printf("SensorDeviceOpen:open %s error\n", SENSOR_DEVICE_PS5308_DEV); + return -1; + } + + result = PrivTaskCreate(&active_task_id, NULL, &ReadTask, sdev); + if (result != 0){ + printf("SensorDeviceOpen:task create failed, status=%d\n", result); + } + + PrivTaskStartup(&active_task_id); + + return result; +} +#else +static int SensorDeviceOpen(struct SensorDevice *sdev) +{ + int result = 0; + + PrivMutexCreate(&buff_lock, 0); + + sdev->fd = open(SENSOR_DEVICE_PS5308_DEV, O_RDWR); + if (sdev->fd < 0) { + printf("open %s error\n", SENSOR_DEVICE_PS5308_DEV); + return -1; + } + + struct SerialDataCfg cfg; + cfg.serial_baud_rate = BAUD_RATE_9600; + cfg.serial_data_bits = DATA_BITS_8; + cfg.serial_stop_bits = STOP_BITS_1; + cfg.serial_buffer_size = 128; + cfg.serial_parity_mode = PARITY_NONE; + cfg.serial_bit_order = 0; + cfg.serial_invert_mode = 0; +#ifdef SENSOR_PS5308_DRIVER_EXTUART + cfg.ext_uart_no = SENSOR_DEVICE_PS5308_DEV_EXT_PORT; + cfg.port_configure = PORT_CFG_INIT; +#endif + + result = PrivIoctl(sdev->fd, OPE_INT, &cfg); + + PrivTaskCreate(&active_task_id, NULL, &ReadTask, sdev); + PrivTaskStartup(&active_task_id); + + return result; +} +#endif + +/** + * @description: Close PS5308 sensor device + * @param sdev - sensor device pointer + * @return 1 + */ +static int SensorDeviceClose(struct SensorDevice *sdev) +{ + PrivTaskDelete(active_task_id, 0); + PrivMutexDelete(&buff_lock); + return 0; +} + +/** + * @description: Read sensor device + * @param sdev - sensor device pointer + * @param len - the length of the read data + * @return get data length + */ +static int SensorDeviceRead(struct SensorDevice *sdev, size_t len) +{ + uint8_t tmp = 0; + int timeout = 0; + while (1) { + read(sdev->fd, &tmp, 1); + if ((tmp == 0x44) || (timeout >= 1000)) + break; + PrivTaskDelay(10); + ++timeout; + } + + if (tmp != 0x44) + return -1; + + uint8_t idx = 0; + sdev->buffer[idx++] = tmp; + + while ((idx < len) && (timeout < 1000)) { + if (read(sdev->fd, &tmp, 1) == 1) { + timeout = 0; + sdev->buffer[idx++] = tmp; + } + ++timeout; + } + + return idx; +} + +static struct SensorDone SensorDeviceDone = +{ + SensorDeviceOpen, + SensorDeviceClose, + SensorDeviceRead, + NULL, + NULL, +}; + +/** + * @description: Init PS5308 sensor and register + * @return void + */ +static void Ps5308Init(void) +{ + ps5308.name = SENSOR_DEVICE_PS5308; + ps5308.info = &info; + ps5308.done = &SensorDeviceDone; + ps5308.status = SENSOR_DEVICE_ACTIVE; + + SensorDeviceRegister(&ps5308); +} + + +#ifdef SENSOR_QUANTITY_PS5308_PM1_0 +static struct SensorQuantity ps5308_pm1_0; + +/** + * @description: Analysis PS5308 PM1.0 result + * @param quant - sensor quantity pointer + * @return quantity value + */ +static int32_t ReadPm1_0(struct SensorQuantity *quant) +{ + if (!quant) + return -1; + + uint32_t result; + if (quant->sdev->done->read != NULL) { + uint16_t checksum = 0; + PrivMutexObtain(&buff_lock); + + for (uint8_t i = 0; i < 30; i++) + checksum += quant->sdev->buffer[i]; + + if (checksum == (((uint16_t)quant->sdev->buffer[30] << 8) + ((uint16_t)quant->sdev->buffer[31]))) { + result = ((uint16_t)quant->sdev->buffer[4] << 8) + (uint16_t)quant->sdev->buffer[5]; + if (result > quant->value.max_value) + quant->value.max_value = result; + else if (result < quant->value.min_value) + quant->value.min_value = result; + quant->value.last_value = result; + + return result; + }else{ + printf("This reading is wrong\n"); + result = SENSOR_QUANTITY_VALUE_ERROR; + return result; + } + }else{ + printf("%s don't have read done.\n", quant->name); + } + + return -1; +} + +/** + * @description: Init PS5308 PM1.0 quantity and register + * @return 0 + */ +int Ps5308Pm1_0Init(void) +{ + Ps5308Init(); + + ps5308_pm1_0.name = SENSOR_QUANTITY_PS5308_PM1_0; + ps5308_pm1_0.type = SENSOR_QUANTITY_PM; + ps5308_pm1_0.value.decimal_places = 0; + ps5308_pm1_0.value.max_std = SENSOR_QUANTITY_VALUE_ERROR; + ps5308_pm1_0.value.min_std = 0; + ps5308_pm1_0.value.last_value = SENSOR_QUANTITY_VALUE_ERROR; + ps5308_pm1_0.value.max_value = SENSOR_QUANTITY_VALUE_ERROR; + ps5308_pm1_0.value.min_value = SENSOR_QUANTITY_VALUE_ERROR; + ps5308_pm1_0.sdev = &ps5308; + ps5308_pm1_0.ReadValue = ReadPm1_0; + + SensorQuantityRegister(&ps5308_pm1_0); + + return 0; +} +#endif + +#ifdef SENSOR_QUANTITY_PS5308_PM2_5 +static struct SensorQuantity ps5308_pm2_5; + +/** + * @description: Analysis PS5308 PM2.5 result + * @param quant - sensor quantity pointer + * @return quantity value + */ +static int32_t ReadPm2_5(struct SensorQuantity *quant) +{ + if (!quant) + return -1; + + uint32_t result; + if (quant->sdev->done->read != NULL) { + uint16_t checksum = 0; + PrivMutexObtain(&buff_lock); + + for (uint i = 0; i < 30; i++) + checksum += quant->sdev->buffer[i]; + + if (checksum == (((uint16_t)quant->sdev->buffer[30] << 8) + ((uint16_t)quant->sdev->buffer[31]))) { + result = ((uint16_t)quant->sdev->buffer[6] << 8) + (uint16_t)quant->sdev->buffer[7]; + if (result > quant->value.max_value) + quant->value.max_value = result; + else if (result < quant->value.min_value) + quant->value.min_value = result; + quant->value.last_value = result; + + return result; + }else{ + printf("This reading is wrong\n"); + result = SENSOR_QUANTITY_VALUE_ERROR; + return result; + } + }else{ + printf("%s don't have read done.\n", quant->name); + } + + return -1; +} + +/** + * @description: Init PS5308 PM2.5 quantity and register + * @return 0 + */ +int Ps5308Pm2_5Init(void) +{ + Ps5308Init(); + + ps5308_pm2_5.name = SENSOR_QUANTITY_PS5308_PM2_5; + ps5308_pm2_5.type = SENSOR_QUANTITY_PM; + ps5308_pm2_5.value.decimal_places = 0; + ps5308_pm2_5.value.max_std = 35; + ps5308_pm2_5.value.min_std = 0; + ps5308_pm2_5.value.last_value = SENSOR_QUANTITY_VALUE_ERROR; + ps5308_pm2_5.value.max_value = SENSOR_QUANTITY_VALUE_ERROR; + ps5308_pm2_5.value.min_value = SENSOR_QUANTITY_VALUE_ERROR; + ps5308_pm2_5.sdev = &ps5308; + ps5308_pm2_5.ReadValue = ReadPm2_5; + + SensorQuantityRegister(&ps5308_pm2_5); + + return 0; +} +#endif + +#ifdef SENSOR_QUANTITY_PS5308_PM10 +static struct SensorQuantity ps5308_pm10; + +/** + * @description: Analysis PS5308 PM10 result + * @param quant - sensor quantity pointer + * @return quantity value + */ +static int32_t ReadPm10(struct SensorQuantity *quant) +{ + if (!quant) + return -1; + + uint32_t result; + if (quant->sdev->done->read != NULL) { + uint16_t checksum = 0; + PrivMutexObtain(&buff_lock); + + for (uint i = 0; i < 30; i++) + checksum += quant->sdev->buffer[i]; + + if (checksum == (((uint16_t)quant->sdev->buffer[30] << 8) + ((uint16_t)quant->sdev->buffer[31]))) { + result = ((uint16_t)quant->sdev->buffer[8] << 8) + (uint16_t)quant->sdev->buffer[9]; + if (result > quant->value.max_value) + quant->value.max_value = result; + else if (result < quant->value.min_value) + quant->value.min_value = result; + quant->value.last_value = result; + + return result; + }else{ + printf("This reading is wrong\n"); + result = SENSOR_QUANTITY_VALUE_ERROR; + return result; + } + }else{ + printf("%s don't have read done.\n", quant->name); + } + + return -1; +} + +/** + * @description: Init PS5308 PM10 quantity and register + * @return 0 + */ +int Ps5308Pm10Init(void) +{ + Ps5308Init(); + + ps5308_pm10.name = SENSOR_QUANTITY_PS5308_PM10; + ps5308_pm10.type = SENSOR_QUANTITY_PM; + ps5308_pm10.value.decimal_places = 0; + ps5308_pm10.value.max_std = 75; + ps5308_pm10.value.min_std = 0; + ps5308_pm10.value.last_value = SENSOR_QUANTITY_VALUE_ERROR; + ps5308_pm10.value.max_value = SENSOR_QUANTITY_VALUE_ERROR; + ps5308_pm10.value.min_value = SENSOR_QUANTITY_VALUE_ERROR; + ps5308_pm10.sdev = &ps5308; + ps5308_pm10.ReadValue = ReadPm10; + + SensorQuantityRegister(&ps5308_pm10); + + return 0; +} +#endif diff --git a/APP_Framework/Framework/sensor/sensor.c b/APP_Framework/Framework/sensor/sensor.c new file mode 100644 index 0000000..372acb7 --- /dev/null +++ b/APP_Framework/Framework/sensor/sensor.c @@ -0,0 +1,397 @@ +/* +* Copyright (c) 2020 AIIT XUOS Lab +* XiUOS is licensed under Mulan PSL v2. +* You can use this software according to the terms and conditions of the Mulan PSL v2. +* You may obtain a copy of Mulan PSL v2 at: +* http://license.coscl.org.cn/MulanPSL2 +* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, +* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, +* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. +* See the Mulan PSL v2 for more details. +*/ + +/** + * @file sensor.c + * @brief Implement the sensor framework management, registration and done + * @version 1.0 + * @author AIIT XUOS Lab + * @date 2021.03.24 + */ + +#include + +/* Sensor quantity list table */ +static DoublelistType quant_table[SENSOR_QUANTITY_END]; + +/* Sensor device list */ +static DoublelistType sensor_device_list; + +/* Sensor quantity list lock */ +static pthread_mutex_t quant_table_lock; + +/* Sensor device list lock */ +static pthread_mutex_t sensor_device_list_lock; + +/** + * @description: Init sensor framework + * @return 0 + */ +int SensorFrameworkInit(void) +{ + int ret = 0; + for (int i = 0; i < SENSOR_QUANTITY_END; i++) + AppInitDoubleList(&quant_table[i]); + AppInitDoubleList(&sensor_device_list); + + ret = PrivMutexCreate(&quant_table_lock, 0); + if(ret < 0) { + printf("quant_table_lock mutex create failed.\n"); + } + ret = PrivMutexCreate(&sensor_device_list_lock, 0); + if(ret < 0) { + printf("sensor_device_list_lock mutex create failed.\n"); + } + + return 0; +} + +/* ============================= Sensor device interface operations ============================= */ + +/** + * @description: Find sensor device by name + * @param name - name string + * @return sensor device pointer + */ +static struct SensorDevice *SensorDeviceFindByName(const char *name) +{ + struct SensorDevice *ret = NULL; + struct DoublelistNode *node; + + if (name == NULL) + return NULL; + + PrivMutexObtain(&sensor_device_list_lock); + DOUBLE_LIST_FOR_EACH(node, &sensor_device_list) { + struct SensorDevice *sdev =CONTAINER_OF(node, + struct SensorDevice, link); + if (strncmp(sdev->name, name, NAME_NUM_MAX) == 0) { + ret = sdev; + break; + } + } + PrivMutexAbandon(&sensor_device_list_lock); + + return ret; +} + +/** + * @description: Check whether the sensor is capable + * @param sdev - sensor device pointer + * @param ability - the ability to detect certain data + * @return success: true , failure: false + */ +inline int SensorDeviceCheckAbility(struct SensorDevice *sdev, uint32_t ability) +{ + return (sdev->info->ability & ability) != 0; +} + +/** + * @description: Register the sensor to the linked list + * @param sdev - sensor device pointer + * @return success: 0 , failure: -1 + */ +int SensorDeviceRegister(struct SensorDevice *sdev) +{ + if (sdev == NULL) + return -1; + + if (SensorDeviceFindByName(sdev->name) != NULL) { + printf("%s: sensor with the same name already registered\n", __func__); + return -1; + } + + sdev->ref_cnt = 0; + AppInitDoubleList(&sdev->quant_list); + + PrivMutexObtain(&sensor_device_list_lock); + AppDoubleListInsertNodeAfter(&sensor_device_list, &sdev->link); + PrivMutexAbandon(&sensor_device_list_lock); + + return 0; +} + +/** + * @description: Unregister the sensor from the linked list + * @param sdev - sensor device pointer + * @return 0 + */ +int SensorDeviceUnregister(struct SensorDevice *sdev) +{ + if (!sdev) + return -1; + PrivMutexObtain(&sensor_device_list_lock); + AppDoubleListRmNode(&sdev->link); + PrivMutexAbandon(&sensor_device_list_lock); + + return 0; +} + +/** + * @description: Open sensor device + * @param sdev - sensor device pointer + * @return success: 0 , failure: other + */ +static int SensorDeviceOpen(struct SensorDevice *sdev) +{ + if (!sdev) + return -1; + + int result = 0; + + if (sdev->done->open != NULL) + result = sdev->done->open(sdev); + + if (result >= 0) { + printf("Device %s open success.\n", sdev->name); + }else{ + printf("Device %s open failed(%d).\n", sdev->name, result); + memset(sdev, 0, sizeof(struct SensorDevice)); + } + + return result; +} + +/** + * @description: Close sensor device + * @param sdev - sensor device pointer + * @return success: 0 , failure: other + */ +static int SensorDeviceClose(struct SensorDevice *sdev) +{ + int result = 0; + + if (sdev->fd >= 0) + PrivClose(sdev->fd); + + if (sdev->done->close != NULL) + result = sdev->done->close(sdev); + + if (result >= 0) + printf("%s successfully closed.\n", sdev->name); + else + printf("Closed %s failure.\n", sdev->name); + + return result; +} + +/* ============================= Sensor quantity interface operations ============================= */ + +/** + * @description: Find sensor quantity by name + * @param name - name string + * @param type - the quantity required + * @return sensor quantity pointer + */ +struct SensorQuantity *SensorQuantityFind(const char *name, + enum SensorQuantityType type) +{ + struct SensorQuantity *ret = NULL; + struct DoublelistNode *node; + + if (name == NULL || type < 0 || type >= SENSOR_QUANTITY_END) + return NULL; + + PrivMutexObtain(&quant_table_lock); + DOUBLE_LIST_FOR_EACH(node, &quant_table[type]) { + struct SensorQuantity *quant =CONTAINER_OF(node, + struct SensorQuantity, link); + if (strncmp(quant->name, name, NAME_NUM_MAX) == 0) { + ret = quant; + break; + } + } + PrivMutexAbandon(&quant_table_lock); + + return ret; +} + +/** + * @description: Register the quantity to the linked list + * @param quant - sensor quantity pointer + * @return success: 0 , failure: -1 + */ +int SensorQuantityRegister(struct SensorQuantity *quant) +{ + if (quant == NULL) + return -1; + + if (SensorDeviceFindByName(quant->sdev->name) == NULL) { + if(SensorDeviceRegister(quant->sdev) != 0) + return -1; + } + + PrivMutexObtain(&quant_table_lock); + AppDoubleListInsertNodeAfter(&quant->sdev->quant_list, &quant->quant_link); + AppDoubleListInsertNodeAfter(&quant_table[quant->type], &quant->link); + PrivMutexAbandon(&quant_table_lock); + + return 0; +} + +/** + * @description: Unregister the quantity from the linked list + * @param quant - sensor quantity pointer + * @return 0 + */ +int SensorQuantityUnregister(struct SensorQuantity *quant) +{ + if (!quant) + return -1; + PrivMutexObtain(&quant_table_lock); + AppDoubleListRmNode(&quant->quant_link); + AppDoubleListRmNode(&quant->link); + PrivMutexAbandon(&quant_table_lock); + + return 0; +} + +/** + * @description: Open the sensor quantity + * @param quant - sensor quantity pointer + * @return success: 0 , failure: other + */ +int SensorQuantityOpen(struct SensorQuantity *quant) +{ + if (!quant) + return -1; + + int ret = 0; + struct SensorDevice *sdev = quant->sdev; + + if (!sdev) + return -1; + + if (sdev->ref_cnt == 0) { + ret = SensorDeviceOpen(sdev); + if (ret < 0) { + printf("%s: open sensor device failed\n", __func__); + return ret; + } + } + sdev->ref_cnt++; + + return ret; +} + +/** + * @description: Close sensor quantity + * @param quant - sensor quantity pointer + * @return success: 0 , failure: other + */ +int SensorQuantityClose(struct SensorQuantity *quant) +{ + if (!quant) + return -1; + + int ret = 0; + struct SensorDevice *sdev = quant->sdev; + + if (!sdev) + return -1; + + if (sdev->ref_cnt == 0) + return ret; + + sdev->ref_cnt--; + if (sdev->ref_cnt == 0) + ret = SensorDeviceClose(sdev); + + return ret; +} + +/** + * @description: Read quantity current value + * @param quant - sensor quantity pointer + * @return quantity value + */ +int SensorQuantityRead(struct SensorQuantity *quant) +{ + if (!quant) + return -1; + + int result = 0; + struct SensorDevice *sdev = quant->sdev; + + if (!sdev) + return -1; + + if (quant->ReadValue != NULL) { + result = quant->ReadValue(quant); + } + + return result; +} + +/** + * @description: Configure quantity mode + * @param quant - sensor quantity pointer + * @param cmd - mode command + * @return success: 0 , failure: other + */ +int SensorQuantityControl(struct SensorQuantity *quant, int cmd) +{ + if (!quant) + return -1; + + if (quant->sdev->done->ioctl != NULL) { + return quant->sdev->done->ioctl(quant->sdev, cmd); + } + + return -1; +} + + +/* ============================= Check function ============================= */ + +/** + * @description: CRC16 check + * @param data sensor receive buffer + * @param length sensor receive buffer minus check code + * @return check code + */ +uint32_t Crc16(uint8_t * data, uint8_t length) +{ + int j; + unsigned int reg_crc=0xFFFF; + + while (length--) { + reg_crc ^= *data++; + for (j=0;j<8;j++) { + if(reg_crc & 0x01) + reg_crc=reg_crc >>1 ^ 0xA001; + else + reg_crc=reg_crc >>1; + } + } + + return reg_crc; +} + +/** + * @description: The checksum + * @param data sensor receive buffer + * @param head not check head length + * @param length sensor receive buffer minus check code + * @return check code + */ +uint8_t GetCheckSum(uint8_t *data, uint8_t head, uint8_t length) +{ + uint8_t i; + uint8_t checksum = 0; + for (i = head; i < length; i++) { + checksum += data[i]; + } + checksum = ~checksum + 1; + + return checksum; +} diff --git a/APP_Framework/Framework/sensor/sensor.h b/APP_Framework/Framework/sensor/sensor.h new file mode 100644 index 0000000..4ec9b64 --- /dev/null +++ b/APP_Framework/Framework/sensor/sensor.h @@ -0,0 +1,148 @@ +/* +* Copyright (c) 2020 AIIT XUOS Lab +* XiUOS is licensed under Mulan PSL v2. +* You can use this software according to the terms and conditions of the Mulan PSL v2. +* You may obtain a copy of Mulan PSL v2 at: +* http://license.coscl.org.cn/MulanPSL2 +* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, +* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, +* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. +* See the Mulan PSL v2 for more details. +*/ + +/** + * @file sensor.h + * @brief Structure and function declarations of the sensor framework + * @version 1.0 + * @author AIIT XUOS Lab + * @date 2021.03.24 + */ + +#ifndef SENSOR_H +#define SENSOR_H + +#include +#include +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +#define SENSOR_QUANTITY_VALUE_ERROR ((uint32_t)0xffffffff) + +/* Sensor quantity report mode */ +#define SENSOR_DEVICE_PASSIVE 0x00 +#define SENSOR_DEVICE_ACTIVE 0x01 + +#define SENSOR_RECEIVE_BUFFSIZE 32 + + +#if SENSOR_TYPE_END > 32 +#error "Too many sensor types" +#endif + +/* Sensor ability */ +#define SENSOR_ABILITY_CO2 ((uint32_t)(1 << SENSOR_QUANTITY_CO2)) +#define SENSOR_ABILITY_TEMP ((uint32_t)(1 << SENSOR_QUANTITY_TEMP)) +#define SENSOR_ABILITY_HUMI ((uint32_t)(1 << SENSOR_QUANTITY_HUMI)) +#define SENSOR_ABILITY_HCHO ((uint32_t)(1 << SENSOR_QUANTITY_HCHO)) +#define SENSOR_ABILITY_CO ((uint32_t)(1 << SENSOR_QUANTITY_CO)) +#define SENSOR_ABILITY_PM ((uint32_t)(1 << SENSOR_QUANTITY_PM)) +#define SENSOR_ABILITY_VOICE ((uint32_t)(1 << SENSOR_QUANTITY_VOICE)) +#define SENSOR_ABILITY_CH4 ((uint32_t)(1 << SENSOR_QUANTITY_CH4)) +#define SENSOR_ABILITY_IAQ ((uint32_t)(1 << SENSOR_QUANTITY_IAQ)) +#define SENSOR_ABILITY_TVOC ((uint32_t)(1 << SENSOR_QUANTITY_TVOC)) +#define SENSOR_ABILITY_HCHO ((uint32_t)(1 << SENSOR_QUANTITY_HCHO)) +#define SENSOR_ABILITY_WINDSPEED ((uint32_t)(1 << SENSOR_QUANTITY_WINDSPEED)) +#define SENSOR_ABILITY_WINDDIRECTION ((uint32_t)(1 << SENSOR_QUANTITY_WINDDIRECTION)) +#define SENSOR_ABILITY_ALTITUDE ((uint32_t)(1 << SENSOR_QUANTITY_ALTITUDE)) + +struct SensorProductInfo { + uint32_t ability; /* Bitwise OR of sensor ability */ + const char *vendor_name; + const char *model_name; +}; + +struct SensorDevice; + +struct SensorDone { + int (*open)(struct SensorDevice *sdev); + int (*close)(struct SensorDevice *sdev); + int (*read)(struct SensorDevice *sdev, size_t len); + int (*write)(struct SensorDevice *sdev, const void *buf, size_t len); + int (*ioctl)(struct SensorDevice *sdev, int cmd); +}; + +struct SensorDevice { + char *name; /* Name of sensor */ + struct SensorProductInfo *info; /* Sensor model info */ + struct SensorDone *done; + int fd; /* File descriptor */ + int status; /* Sensor work mode */ + uint8_t buffer[SENSOR_RECEIVE_BUFFSIZE]; /* Buffer for read data */ + + int ref_cnt; /* Reference count */ + DoublelistType quant_list; /* Sensor quantity link */ + struct DoublelistNode link; /* Sensors link node */ +}; + +enum SensorQuantityType { + SENSOR_QUANTITY_CO2 = 0, + SENSOR_QUANTITY_TEMP, + SENSOR_QUANTITY_HUMI, + SENSOR_QUANTITY_HCHO, + SENSOR_QUANTITY_CO, + SENSOR_QUANTITY_PM, + SENSOR_QUANTITY_VOICE, + SENSOR_QUANTITY_CH4, + SENSOR_QUANTITY_IAQ, + SENSOR_QUANTITY_TVOC, + SENSOR_QUANTITY_WINDSPEED, + SENSOR_QUANTITY_WINDDIRECTION, + SENSOR_QUANTITY_ALTITUDE, + /* ...... */ + SENSOR_QUANTITY_END, +}; + +struct SensorQuantityValue { + uint8_t decimal_places; /* The decimal place of the result */ + uint32_t last_value; /* The last read value, if it does not exist, is SENSOR_QUANTITY_VALUE_ERROR */ + uint32_t min_value; /* The minimum read value, if it does not exist, is SENSOR_QUANTITY_VALUE_ERROR */ + uint32_t max_value; /* The maximum read value, if it does not exist, is SENSOR_QUANTITY_VALUE_ERROR */ + uint32_t min_std; /* The minimum standard value, if it does not exist, is SENSOR_QUANTITY_VALUE_ERROR */ + uint32_t max_std; /* The maximum standard value, if it does not exist, is SENSOR_QUANTITY_VALUE_ERROR */ +}; + +struct SensorQuantity { + char *name; + enum SensorQuantityType type; + struct SensorQuantityValue value; + struct SensorDevice *sdev; + + int32_t (*ReadValue)(struct SensorQuantity *quant); + + struct DoublelistNode quant_link; + struct DoublelistNode link; +}; + +int SensorDeviceRegister(struct SensorDevice *sdev); +int SensorDeviceUnregister(struct SensorDevice *sdev); + +struct SensorQuantity *SensorQuantityFind(const char *name, enum SensorQuantityType type); +int SensorQuantityRegister(struct SensorQuantity *quant); +int SensorQuantityUnregister(struct SensorQuantity *quant); +int SensorQuantityOpen(struct SensorQuantity *quant); +int SensorQuantityClose(struct SensorQuantity *quant); +int SensorQuantityRead(struct SensorQuantity *quant); +int SensorQuantityControl(struct SensorQuantity *quant, int cmd); + +uint32_t Crc16(uint8_t * data, uint8_t length); +uint8_t GetCheckSum(uint8_t *data, uint8_t head, uint8_t length); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/APP_Framework/Framework/sensor/temperature/Kconfig b/APP_Framework/Framework/sensor/temperature/Kconfig new file mode 100644 index 0000000..c7eb158 --- /dev/null +++ b/APP_Framework/Framework/sensor/temperature/Kconfig @@ -0,0 +1,39 @@ + +config SENSOR_HS300X_TEMPERATURE + bool "Using HS300x for temperature" + default n + + if SENSOR_HS300X_TEMPERATURE + config SENSOR_DEVICE_HS300X + string "HS300x sensor name" + default "hs300x_1" + + config SENSOR_QUANTITY_HS300X_TEMPERATURE + string "HS300x quantity name" + default "temperature_1" + + if ADD_XIZI_FETURES + config SENSOR_DEVICE_HS300X_DEV + string "HS300x device name" + default "/dev/i2c1_dev0" + + config SENSOR_DEVICE_HS300X_I2C_ADDR + hex "HS300x device i2c address" + default 0x44 + endif + + if ADD_NUTTX_FETURES + config SENSOR_DEVICE_HS300X_DEV + string "HS300x device name" + default "/dev/i2c1_dev0" + + config SENSOR_DEVICE_HS300X_I2C_ADDR + hex "HS300x device i2c address" + default 0x44 + + endif + + if ADD_RTTHREAD_FETURES + + endif + endif diff --git a/APP_Framework/Framework/sensor/temperature/Make.defs b/APP_Framework/Framework/sensor/temperature/Make.defs new file mode 100644 index 0000000..1b54563 --- /dev/null +++ b/APP_Framework/Framework/sensor/temperature/Make.defs @@ -0,0 +1,4 @@ +############################################################################ +# APP_Framework/Framework/sensor/temperature//Make.defs +############################################################################ +include $(wildcard $(APPDIR)/../../../APP_Framework/Framework/sensor/temperature/*/Make.defs) diff --git a/APP_Framework/Framework/sensor/temperature/Makefile b/APP_Framework/Framework/sensor/temperature/Makefile new file mode 100644 index 0000000..361a871 --- /dev/null +++ b/APP_Framework/Framework/sensor/temperature/Makefile @@ -0,0 +1,5 @@ +ifeq ($(CONFIG_SENSOR_HS300X_TEMPERATURE),y) + SRC_DIR += hs300x_temp +endif + +include $(KERNEL_ROOT)/compiler.mk diff --git a/APP_Framework/Framework/sensor/temperature/hs300x_temp/Make.defs b/APP_Framework/Framework/sensor/temperature/hs300x_temp/Make.defs new file mode 100644 index 0000000..d438ca7 --- /dev/null +++ b/APP_Framework/Framework/sensor/temperature/hs300x_temp/Make.defs @@ -0,0 +1,6 @@ +############################################################################ +# APP_Framework/Framework/sensor/temperature/hs300x_temp/Make.defs +############################################################################ +ifneq ($(CONFIG_SENSOR_HS300X_TEMPERATURE),) +CONFIGURED_APPS += $(APPDIR)/../../../APP_Framework/Framework/sensor/temperature/hs300x_temp +endif diff --git a/APP_Framework/Framework/sensor/temperature/hs300x_temp/Makefile b/APP_Framework/Framework/sensor/temperature/hs300x_temp/Makefile new file mode 100644 index 0000000..047981e --- /dev/null +++ b/APP_Framework/Framework/sensor/temperature/hs300x_temp/Makefile @@ -0,0 +1,12 @@ +include $(KERNEL_ROOT)/.config +ifeq ($(CONFIG_ADD_NUTTX_FETURES),y) + include $(APPDIR)/Make.defs + CSRCS += hs300x_temp.c + include $(APPDIR)/Application.mk + +endif + +ifeq ($(CONFIG_ADD_XIZI_FETURES),y) + SRC_FILES := hs300x_temp.c + include $(KERNEL_ROOT)/compiler.mk +endif diff --git a/APP_Framework/Framework/sensor/temperature/hs300x_temp/hs300x_temp.c b/APP_Framework/Framework/sensor/temperature/hs300x_temp/hs300x_temp.c new file mode 100644 index 0000000..a758ab4 --- /dev/null +++ b/APP_Framework/Framework/sensor/temperature/hs300x_temp/hs300x_temp.c @@ -0,0 +1,157 @@ +/* +* Copyright (c) 2020 AIIT XUOS Lab +* XiUOS is licensed under Mulan PSL v2. +* You can use this software according to the terms and conditions of the Mulan PSL v2. +* You may obtain a copy of Mulan PSL v2 at: +* http://license.coscl.org.cn/MulanPSL2 +* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, +* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, +* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. +* See the Mulan PSL v2 for more details. +*/ + +/** + * @file hs300x_temp.c + * @brief HS300x temperature driver base sensor + * @version 1.0 + * @author AIIT XUOS Lab + * @date 2021.04.22 + */ + +#include + +static struct SensorDevice hs300x; + +static struct SensorProductInfo info = +{ + (SENSOR_ABILITY_HUMI | SENSOR_ABILITY_TEMP), + "Renesas", + "HS300x", +}; + +/** + * @description: Open HS300x sensor device + * @param sdev - sensor device pointer + * @return success : 0 error : -1 + */ +static int SensorDeviceOpen(struct SensorDevice *sdev) +{ +#ifdef ADD_NUTTX_FETURES + sdev->fd = PrivOpen(SENSOR_DEVICE_HS300X_DEV, O_RDWR); + + return sdev->fd; + +#else + int result; + uint16_t i2c_dev_addr = SENSOR_DEVICE_HS300X_I2C_ADDR; + + sdev->fd = PrivOpen(SENSOR_DEVICE_HS300X_DEV, O_RDWR); + if (sdev->fd < 0) { + printf("open %s error\n", SENSOR_DEVICE_HS300X_DEV); + return -1; + } + + struct PrivIoctlCfg ioctl_cfg; + ioctl_cfg.ioctl_driver_type = I2C_TYPE; + ioctl_cfg.args = &i2c_dev_addr; + result = PrivIoctl(sdev->fd, OPE_INT, &ioctl_cfg); + + return result; +#endif +} + +/** + * @description: Read sensor device + * @param sdev - sensor device pointer + * @param len - the length of the read data + * @return success: 0 , failure: -1 + */ +static int SensorDeviceRead(struct SensorDevice *sdev, size_t len) +{ + //Read i2c device data from i2c device address + if (PrivRead(sdev->fd, sdev->buffer, len) < 0) + return -1; + + return 0; +} + +static struct SensorDone done = +{ + SensorDeviceOpen, + NULL, + SensorDeviceRead, + NULL, + NULL, +}; + +/** + * @description: Init HS300x sensor and register + * @return void + */ +static void SensorDeviceHs300xInit(void) +{ + hs300x.name = SENSOR_DEVICE_HS300X; + hs300x.info = &info; + hs300x.done = &done; + hs300x.status = SENSOR_DEVICE_PASSIVE; + + SensorDeviceRegister(&hs300x); +} + + + +static struct SensorQuantity hs300x_temperature; + +/** + * @description: Analysis HS300x temperature result + * @param quant - sensor quantity pointer + * @return quantity value + */ +static int32_t ReadTemperature(struct SensorQuantity *quant) +{ + if (!quant) + return -1; + + float result; + if (quant->sdev->done->read != NULL) { + if (quant->sdev->status == SENSOR_DEVICE_PASSIVE) { + quant->sdev->done->read(quant->sdev, 4); + PrivTaskDelay(50); + quant->sdev->done->read(quant->sdev, 4); /* It takes two reads to get the data right */ + result = ((quant->sdev->buffer[2] << 8 | quant->sdev->buffer[3]) >> 2) * 165.0 /( (1 << 14) - 1) - 40.0; + + return (int32_t)(result * 10); + } + if (quant->sdev->status == SENSOR_DEVICE_ACTIVE) { + printf("Please set passive mode.\n"); + } + }else{ + printf("%s don't have read done.\n", quant->name); + } + + return -1; +} + +/** + * @description: Init HS300x temperature quantity and register + * @return 0 + */ +int Hs300xTemperatureInit(void) +{ + SensorDeviceHs300xInit(); + + hs300x_temperature.name = SENSOR_QUANTITY_HS300X_TEMPERATURE; + hs300x_temperature.type = SENSOR_QUANTITY_TEMP; + hs300x_temperature.value.decimal_places = 1; + hs300x_temperature.value.max_std = 1000; + hs300x_temperature.value.min_std = 0; + hs300x_temperature.value.last_value = SENSOR_QUANTITY_VALUE_ERROR; + hs300x_temperature.value.max_value = SENSOR_QUANTITY_VALUE_ERROR; + hs300x_temperature.value.min_value = SENSOR_QUANTITY_VALUE_ERROR; + hs300x_temperature.sdev = &hs300x; + hs300x_temperature.ReadValue = ReadTemperature; + + SensorQuantityRegister(&hs300x_temperature); + + return 0; +} \ No newline at end of file diff --git a/APP_Framework/Framework/sensor/tvoc/Kconfig b/APP_Framework/Framework/sensor/tvoc/Kconfig new file mode 100644 index 0000000..b667e48 --- /dev/null +++ b/APP_Framework/Framework/sensor/tvoc/Kconfig @@ -0,0 +1,48 @@ + +config SENSOR_TB600B_TVOC10 + bool "Using TB600B TVOC10" + default n + + if SENSOR_TB600B_TVOC10 + config SENSOR_DEVICE_TB600B_TVOC10 + string "tb600b tvoc10 sensor name" + default "tb600b_tvoc10_1" + + config SENSOR_QUANTITY_TB600B_TVOC + string "tb600b tvoc10 quantity name" + default "tvoc_1" + + if ADD_XIZI_FETURES + config SENSOR_TB600B_TVOC10_DRIVER_EXTUART + bool "Using extra uart to support tb600b tvoc10" + default y + + config SENSOR_DEVICE_TB600B_TVOC10_DEV + string "tb600b tvoc10 device uart path" + default "/dev/uart2_dev2" + depends on !SENSOR_TB600B_TVOC10_DRIVER_EXTUART + + if SENSOR_TB600B_TVOC10_DRIVER_EXTUART + config SENSOR_DEVICE_TB600B_TVOC10_DEV + string "tb600b tvoc10 device extra uart path" + default "/dev/extuart_dev6" + + config SENSOR_DEVICE_TB600B_TVOC10_DEV_EXT_PORT + int "if TB600B_TVOC10 device using extuart, choose port" + default "6" + endif + endif + + if ADD_NUTTX_FETURES + config SENSOR_DEVICE_TB600B_TVOC10_DEV + string "tb600b tvoc10 device uart path" + default "/dev/ttyS1" + ---help--- + If USART1 is selected, then fill in /dev/ttyS1 here. + + endif + + if ADD_RTTHREAD_FETURES + + endif + endif diff --git a/APP_Framework/Framework/sensor/tvoc/Make.defs b/APP_Framework/Framework/sensor/tvoc/Make.defs new file mode 100644 index 0000000..eb1c6ba --- /dev/null +++ b/APP_Framework/Framework/sensor/tvoc/Make.defs @@ -0,0 +1,4 @@ +############################################################################ +# APP_Framework/Framework/sensor/tvoc/Make.defs +############################################################################ +include $(wildcard $(APPDIR)/../../../APP_Framework/Framework/sensor/tvoc/*/Make.defs) diff --git a/APP_Framework/Framework/sensor/tvoc/Makefile b/APP_Framework/Framework/sensor/tvoc/Makefile new file mode 100644 index 0000000..8ef12bb --- /dev/null +++ b/APP_Framework/Framework/sensor/tvoc/Makefile @@ -0,0 +1,5 @@ +ifeq ($(CONFIG_SENSOR_TB600B_TVOC10),y) + SRC_DIR += tb600b_tvoc10 +endif + +include $(KERNEL_ROOT)/compiler.mk diff --git a/APP_Framework/Framework/sensor/tvoc/tb600b_tvoc10/Make.defs b/APP_Framework/Framework/sensor/tvoc/tb600b_tvoc10/Make.defs new file mode 100644 index 0000000..fbec91f --- /dev/null +++ b/APP_Framework/Framework/sensor/tvoc/tb600b_tvoc10/Make.defs @@ -0,0 +1,6 @@ +############################################################################ +# APP_Framework/Framework/sensor/tvoc/tb600b_tvoc10/Make.defs +############################################################################ +ifneq ($(CONFIG_SENSOR_TB600B_TVOC10),) +CONFIGURED_APPS += $(APPDIR)/../../../APP_Framework/Framework/sensor/tvoc/tb600b_tvoc10 +endif diff --git a/APP_Framework/Framework/sensor/tvoc/tb600b_tvoc10/Makefile b/APP_Framework/Framework/sensor/tvoc/tb600b_tvoc10/Makefile new file mode 100644 index 0000000..7fb2cad --- /dev/null +++ b/APP_Framework/Framework/sensor/tvoc/tb600b_tvoc10/Makefile @@ -0,0 +1,12 @@ +include $(KERNEL_ROOT)/.config + +ifeq ($(CONFIG_ADD_NUTTX_FETURES),y) + include $(APPDIR)/Make.defs + CSRCS += tb600b_tvoc10.c + include $(APPDIR)/Application.mk +endif + +ifeq ($(CONFIG_ADD_XIZI_FETURES),y) + SRC_FILES := tb600b_tvoc10.c + include $(KERNEL_ROOT)/compiler.mk +endif diff --git a/APP_Framework/Framework/sensor/tvoc/tb600b_tvoc10/tb600b_tvoc10.c b/APP_Framework/Framework/sensor/tvoc/tb600b_tvoc10/tb600b_tvoc10.c new file mode 100644 index 0000000..27847e0 --- /dev/null +++ b/APP_Framework/Framework/sensor/tvoc/tb600b_tvoc10/tb600b_tvoc10.c @@ -0,0 +1,240 @@ +/* +* Copyright (c) 2020 AIIT XUOS Lab +* XiUOS is licensed under Mulan PSL v2. +* You can use this software according to the terms and conditions of the Mulan PSL v2. +* You may obtain a copy of Mulan PSL v2 at: +* http://license.coscl.org.cn/MulanPSL2 +* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, +* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, +* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. +* See the Mulan PSL v2 for more details. +*/ + +/** + * @file tb600b_tvoc10.c + * @brief tb600b_tvoc10 driver base sensor + * @version 1.0 + * @author AIIT XUOS Lab + * @date 2021.12.15 + */ + +#include + +static struct SensorDevice tb600b_tvoc10; +static uint8_t ReadInstruction[9]; + +static struct SensorProductInfo info = +{ + SENSOR_ABILITY_TVOC, + "AQS", + "TB600B_TVOC10", +}; + +/** + * @description: Open TB600B TVOC10 sensor device + * @param sdev - sensor device pointer + * @return success: 1 , failure: other + */ +#ifdef ADD_NUTTX_FETURES +static int SensorDeviceOpen(struct SensorDevice *sdev) +{ + sdev->fd = PrivOpen(SENSOR_DEVICE_TB600B_TVOC10_DEV, O_RDWR); + if (sdev->fd < 0) { + printf("open %s error\n", SENSOR_DEVICE_TB600B_TVOC10_DEV); + return -1; + } + + return sdev->fd; +} +#else +static int SensorDeviceOpen(struct SensorDevice *sdev) +{ + int result = 0; + + sdev->fd = PrivOpen(SENSOR_DEVICE_TB600B_TVOC10_DEV, O_RDWR); + if (sdev->fd < 0) { + printf("open %s error\n", SENSOR_DEVICE_TB600B_TVOC10_DEV); + return -1; + } + + struct SerialDataCfg cfg; + cfg.serial_baud_rate = BAUD_RATE_9600; + cfg.serial_data_bits = DATA_BITS_8; + cfg.serial_stop_bits = STOP_BITS_1; + cfg.serial_buffer_size = 128; + cfg.serial_parity_mode = PARITY_NONE; + cfg.serial_bit_order = 0; + cfg.serial_invert_mode = 0; +#ifdef SENSOR_TB600B_TVOC10_DRIVER_EXTUART + cfg.ext_uart_no = SENSOR_DEVICE_TB600B_TVOC10_DEV_EXT_PORT; + cfg.port_configure = PORT_CFG_INIT; +#endif + + struct PrivIoctlCfg ioctl_cfg; + ioctl_cfg.ioctl_driver_type = SERIAL_TYPE; + ioctl_cfg.args = &cfg; + result = PrivIoctl(sdev->fd, OPE_INT, &ioctl_cfg); + + return result; +} +#endif + +/** + * @description: Read sensor device + * @param sdev - sensor device pointer + * @param len - the length of the read data + * @return get data length + */ +static int SensorDeviceRead(struct SensorDevice *sdev, size_t len) +{ + uint8_t tmp = 0; + uint8_t idx = 0; + + /* this instruction will read gas with temperature and humidity,return 13 datas*/ + ReadInstruction[0] = 0xFF; + ReadInstruction[1] = 0x01; + ReadInstruction[2] = 0x87; + ReadInstruction[3] = 0x00; + ReadInstruction[4] = 0x00; + ReadInstruction[5] = 0x00; + ReadInstruction[6] = 0x00; + ReadInstruction[7] = 0x00; + ReadInstruction[8] = 0x78; + + PrivWrite(sdev->fd, ReadInstruction, 9); + + for(idx = 0; idx < 13; idx++) + { + if (PrivRead(sdev->fd, &tmp, 1) == 1) { + sdev->buffer[idx] = tmp; + } + } + + return idx; +} +/** + * @description: Read sensor device + * @param sdev - sensor device pointer + * @param len - the length of the read data + * @return get data length + */ +static int SensorDeviceWrite(struct SensorDevice *sdev, const void *buf, size_t len) +{ + return PrivWrite(sdev->fd, buf, len); + +} + +static struct SensorDone done = +{ + SensorDeviceOpen, + NULL, + SensorDeviceRead, + SensorDeviceWrite, + NULL, +}; + +/** + * @description: Init TB600B TVOC10 sensor and register + * @return void + */ +static void SensorDeviceTb600bTvoc10Init(void) +{ + tb600b_tvoc10.name = SENSOR_DEVICE_TB600B_TVOC10; + tb600b_tvoc10.info = &info; + tb600b_tvoc10.done = &done; + + SensorDeviceRegister(&tb600b_tvoc10); +} + +static struct SensorQuantity tb600b_tvoc10_tvoc; + +/* check data*/ +static uint8_t getCheckSum(uint8_t *packet) +{ + uint8_t i; + uint8_t checksum = 0; + for( i = 1; i < 12; i++) + { + checksum += packet[i]; + } + checksum = ~checksum + 1; + + return checksum; +} + +/** + * @description: Analysis TB600B TVOC10 result + * @param quant - sensor quantity pointer + * @return quantity value + */ +static int32_t QuantityRead(struct SensorQuantity *quant) +{ + if (!quant) + return -1; + + uint32_t len = 0; + uint8_t checksum = 0; + uint8_t TH, TL, RhH, RhL; + uint16_t ppb, ugm3; + + if (quant->sdev->done->read != NULL) { + if(quant->sdev->status == SENSOR_DEVICE_PASSIVE) { + len = quant->sdev->done->read(quant->sdev, 13); + if (len == 0) + { + printf("error read data length = 0.\n"); + return -1; + } + checksum = getCheckSum(quant->sdev->buffer); + if(checksum == quant->sdev->buffer[12]) + { + ugm3 = (uint16_t)quant->sdev->buffer[2] * 256 + (uint16_t)quant->sdev->buffer[3]; + ppb = (uint16_t)quant->sdev->buffer[6] * 256 + (uint16_t)quant->sdev->buffer[7]; + TH = ((int)((quant->sdev->buffer[8] << 8)|quant->sdev->buffer[9]))/100; + TL = ((int)((quant->sdev->buffer[8] << 8)|quant->sdev->buffer[9]))%100; + RhH = ((unsigned int)((quant->sdev->buffer[10] << 8)|quant->sdev->buffer[11]))/100; + RhL = ((unsigned int)((quant->sdev->buffer[10] << 8)|quant->sdev->buffer[11]))%100; + + printf("tvoc concentration is : %dug/m³(%dppb)\nThe temperature is : %d.%d℃\nThe humidity is : %d.%drh%%\n", ugm3, ppb, TH, TL, RhH, RhL); + return ppb; + } + else + { + printf("This reading is wrong\n"); + return SENSOR_QUANTITY_VALUE_ERROR; + } + } + if (quant->sdev->status == SENSOR_DEVICE_ACTIVE) + { + printf("Please set passive mode.\n"); + } + }else{ + printf("%s don't have read done.\n", quant->name); + } + + return -1; +} + +/** + * @description: Init TB600B TVOC10 quantity and register + * @return 0 + */ +int Tb600bTvoc10TvocInit(void) +{ + SensorDeviceTb600bTvoc10Init(); + + tb600b_tvoc10_tvoc.name = SENSOR_QUANTITY_TB600B_TVOC; + tb600b_tvoc10_tvoc.type = SENSOR_QUANTITY_TVOC; + tb600b_tvoc10_tvoc.value.decimal_places = 0; + tb600b_tvoc10_tvoc.value.max_std = SENSOR_QUANTITY_VALUE_ERROR; + tb600b_tvoc10_tvoc.value.min_std = SENSOR_QUANTITY_VALUE_ERROR; + tb600b_tvoc10_tvoc.value.last_value = SENSOR_QUANTITY_VALUE_ERROR; + tb600b_tvoc10_tvoc.value.max_value = SENSOR_QUANTITY_VALUE_ERROR; + tb600b_tvoc10_tvoc.value.min_value = SENSOR_QUANTITY_VALUE_ERROR; + tb600b_tvoc10_tvoc.sdev = &tb600b_tvoc10; + tb600b_tvoc10_tvoc.ReadValue = QuantityRead; + + SensorQuantityRegister(&tb600b_tvoc10_tvoc); + + return 0; +} \ No newline at end of file diff --git a/APP_Framework/Framework/sensor/voice/Kconfig b/APP_Framework/Framework/sensor/voice/Kconfig new file mode 100644 index 0000000..87a8c21 --- /dev/null +++ b/APP_Framework/Framework/sensor/voice/Kconfig @@ -0,0 +1,65 @@ + +config SENSOR_D124 + bool "Using D124" + default n + + if SENSOR_D124 + config SENSOR_DEVICE_D124 + string "D124 sensor name" + default "d124_1" + + config SENSOR_QUANTITY_D124_VOICE + string "D124 quantity voice name" + default "voice_1" + + if ADD_XIZI_FETURES + config SENSOR_D124_DRIVER_EXTUART + bool "Using extra uart to support D124" + default y + + config SENSOR_DEVICE_D124_DEV + string "D124 device name" + default "/dev/uart2_dev2" + depends on !SENSOR_D124_DRIVER_EXTUART + + if SENSOR_D124_DRIVER_EXTUART + config SENSOR_DEVICE_D124_DEV + string "D124 device extra uart path" + default "/dev/extuart_dev4" + + config SENSOR_DEVICE_D124_DEV_EXT_PORT + int "if D124 device using extuart, choose port" + default "4" + endif + endif + + if ADD_NUTTX_FETURES + config SENSOR_DEVICE_D124_DEV + string "D124 device name" + default "/dev/ttyS1" + ---help--- + If USART1 is selected, then fill in /dev/ttyS1 here. + + endif + + if ADD_RTTHREAD_FETURES + config SENSOR_D124_DRIVER_EXTUART + bool "Using extra uart to support D124" + default y + + config SENSOR_DEVICE_D124_DEV + string "D124 device name" + default "/dev/uart2_dev2" + depends on !SENSOR_D124_DRIVER_EXTUART + + if SENSOR_D124_DRIVER_EXTUART + config SENSOR_DEVICE_D124_DEV + string "D124 device extra uart path" + default "/dev/extuart_dev4" + + config SENSOR_DEVICE_D124_DEV_EXT_PORT + int "if D124 device using extuart, choose port" + default "4" + endif + endif + endif diff --git a/APP_Framework/Framework/sensor/voice/Make.defs b/APP_Framework/Framework/sensor/voice/Make.defs new file mode 100644 index 0000000..754a962 --- /dev/null +++ b/APP_Framework/Framework/sensor/voice/Make.defs @@ -0,0 +1,4 @@ +############################################################################ +# APP_Framework/Framework/sensor/voice/Make.defs +############################################################################ +include $(wildcard $(APPDIR)/../../../APP_Framework/Framework/sensor/voice/*/Make.defs) diff --git a/APP_Framework/Framework/sensor/voice/Makefile b/APP_Framework/Framework/sensor/voice/Makefile new file mode 100644 index 0000000..a7c4056 --- /dev/null +++ b/APP_Framework/Framework/sensor/voice/Makefile @@ -0,0 +1,5 @@ +ifeq ($(CONFIG_SENSOR_D124),y) + SRC_DIR += d124 +endif + +include $(KERNEL_ROOT)/compiler.mk diff --git a/APP_Framework/Framework/sensor/voice/SConscript b/APP_Framework/Framework/sensor/voice/SConscript new file mode 100644 index 0000000..f307e3f --- /dev/null +++ b/APP_Framework/Framework/sensor/voice/SConscript @@ -0,0 +1,14 @@ +import os +Import('RTT_ROOT') +from building import * + +cwd = GetCurrentDir() +objs = [] +list = os.listdir(cwd) + +for d in list: + path = os.path.join(cwd, d) + if os.path.isfile(os.path.join(path, 'SConscript')): + objs = objs + SConscript(os.path.join(path, 'SConscript')) + +Return('objs') diff --git a/APP_Framework/Framework/sensor/voice/d124/Make.defs b/APP_Framework/Framework/sensor/voice/d124/Make.defs new file mode 100644 index 0000000..5c0308f --- /dev/null +++ b/APP_Framework/Framework/sensor/voice/d124/Make.defs @@ -0,0 +1,6 @@ +############################################################################ +# APP_Framework/Framework/sensor/voice/d124/Make.defs +############################################################################ +ifneq ($(CONFIG_SENSOR_D124),) +CONFIGURED_APPS += $(APPDIR)/../../../APP_Framework/Framework/sensor/voice/d124 +endif diff --git a/APP_Framework/Framework/sensor/voice/d124/Makefile b/APP_Framework/Framework/sensor/voice/d124/Makefile new file mode 100644 index 0000000..18f5d99 --- /dev/null +++ b/APP_Framework/Framework/sensor/voice/d124/Makefile @@ -0,0 +1,12 @@ +include $(KERNEL_ROOT)/.config + +ifeq ($(CONFIG_ADD_NUTTX_FETURES),y) + include $(APPDIR)/Make.defs + CSRCS += d124.c + include $(APPDIR)/Application.mk +endif + +ifeq ($(CONFIG_ADD_XIZI_FETURES),y) + SRC_FILES := d124.c + include $(KERNEL_ROOT)/compiler.mk +endif diff --git a/APP_Framework/Framework/sensor/voice/d124/SConscript b/APP_Framework/Framework/sensor/voice/d124/SConscript new file mode 100644 index 0000000..885542e --- /dev/null +++ b/APP_Framework/Framework/sensor/voice/d124/SConscript @@ -0,0 +1,10 @@ +from building import * +import os + +cwd = GetCurrentDir() +src = [] +if GetDepend(['SENSOR_D124']): + src += ['d124.c'] +group = DefineGroup('sensor voice d124', src, depend = [], CPPPATH = [cwd]) + +Return('group') \ No newline at end of file diff --git a/APP_Framework/Framework/sensor/voice/d124/d124.c b/APP_Framework/Framework/sensor/voice/d124/d124.c new file mode 100644 index 0000000..e066edf --- /dev/null +++ b/APP_Framework/Framework/sensor/voice/d124/d124.c @@ -0,0 +1,254 @@ +/* +* Copyright (c) 2020 AIIT XUOS Lab +* XiUOS is licensed under Mulan PSL v2. +* You can use this software according to the terms and conditions of the Mulan PSL v2. +* You may obtain a copy of Mulan PSL v2 at: +* http://license.coscl.org.cn/MulanPSL2 +* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, +* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, +* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. +* See the Mulan PSL v2 for more details. +*/ + +/** + * @file d124.c + * @brief D124 voice driver base sensor + * @version 1.0 + * @author AIIT XUOS Lab + * @date 2021.04.22 + */ + +#include + +static struct SensorDevice d124; +static pthread_t active_task_id; +static pthread_mutex_t buff_lock; + +static struct SensorProductInfo info = +{ + SENSOR_ABILITY_VOICE, + "龙戈电子", + "D124", +}; + +/** + * @description: Read sensor task + * @param sdev - sensor device pointer + */ +static void *ReadTask(void *parameter) +{ + struct SensorDevice *sdev = (struct SensorDevice *)parameter; + while (1) { + PrivMutexObtain(&buff_lock); + sdev->done->read(sdev, 5); + PrivMutexAbandon(&buff_lock); + PrivTaskDelay(750); + } +} + +/** + * @description: Open D124 voice device + * @param sdev - sensor device pointer + * @return success: 1 , failure: other + */ +#ifdef ADD_NUTTX_FETURES +static int SensorDeviceOpen(struct SensorDevice *sdev) +{ + int result = 0; + pthread_attr_t attr = PTHREAD_ATTR_INITIALIZER; + + result = PrivMutexCreate(&buff_lock, NULL); + if (result != 0){ + printf("SensorDeviceOpen:mutex create failed, status=%d\n", result); + } + + sdev->fd = PrivOpen(SENSOR_DEVICE_D124_DEV, O_RDWR); + if (sdev->fd < 0) { + printf("SensorDeviceOpen:open %s error\n", SENSOR_DEVICE_D124_DEV); + return -1; + } + + attr.priority = 20; + attr.stacksize = 2048; + + result = PrivTaskCreate(&active_task_id, &attr, &ReadTask, sdev); + if (result != 0){ + printf("SensorDeviceOpen:task create failed, status=%d\n", result); + } + PrivTaskStartup(&active_task_id); + + return result; +} +#else +static int SensorDeviceOpen(struct SensorDevice *sdev) +{ + int result = 0; + pthread_attr_t attr; + + PrivMutexCreate(&buff_lock, 0); + + sdev->fd = PrivOpen(SENSOR_DEVICE_D124_DEV, O_RDWR); + if (sdev->fd < 0) { + printf("open %s error\n", SENSOR_DEVICE_D124_DEV); + return -1; + } + + struct SerialDataCfg cfg; + cfg.serial_baud_rate = BAUD_RATE_9600; + cfg.serial_data_bits = DATA_BITS_8; + cfg.serial_stop_bits = STOP_BITS_1; + cfg.serial_buffer_size = 64; + cfg.serial_parity_mode = PARITY_NONE; + cfg.serial_bit_order = 0; + cfg.serial_invert_mode = 0; +#ifdef SENSOR_D124_DRIVER_EXTUART + cfg.ext_uart_no = SENSOR_DEVICE_D124_DEV_EXT_PORT; + cfg.port_configure = PORT_CFG_INIT; +#endif + + struct PrivIoctlCfg ioctl_cfg; + ioctl_cfg.ioctl_driver_type = SERIAL_TYPE; + ioctl_cfg.args = &cfg; + result = PrivIoctl(sdev->fd, OPE_INT, &ioctl_cfg); + + attr.schedparam.sched_priority = 20; + attr.stacksize = 2048; + + PrivTaskCreate(&active_task_id, &attr, &ReadTask, sdev); + PrivTaskStartup(&active_task_id); + + return result; +} +#endif + +/** + * @description: Close D124 sensor device + * @param sdev - sensor device pointer + * @return 1 + */ +static int SensorDeviceClose(struct SensorDevice *sdev) +{ + PrivTaskDelete(active_task_id, 0); + PrivMutexDelete(&buff_lock); + return 0; +} + +/** + * @description: Read sensor device + * @param sdev - sensor device pointer + * @param len - the length of the read data + * @return get data length + */ +static int SensorDeviceRead(struct SensorDevice *sdev, size_t len) +{ + uint8_t tmp = 0; + int timeout = 0; + while (1) { + PrivRead(sdev->fd, &tmp, 1); + if ((tmp == 0xAA) || (timeout >= 1000)) + break; + PrivTaskDelay(10); + ++timeout; + } + + if(tmp != 0xAA) + return -1; + + uint8_t idx = 0; + sdev->buffer[idx++] = tmp; + + while ((idx < len) && (timeout < 1000)) { + if (PrivRead(sdev->fd, &tmp, 1) == 1) { + timeout = 0; + sdev->buffer[idx++] = tmp; + } + ++timeout; + } + + return idx; +} + +static struct SensorDone done = +{ + SensorDeviceOpen, + SensorDeviceClose, + SensorDeviceRead, + NULL, + NULL, +}; + +/** + * @description: Init D124 sensor and register + * @return void + */ +static void D124Init(void) +{ + d124.name = SENSOR_DEVICE_D124; + d124.info = &info; + d124.done = &done; + d124.status = SENSOR_DEVICE_ACTIVE; + + SensorDeviceRegister(&d124); +} + + +static struct SensorQuantity d124_voice; + +/** + * @description: Analysis D124 voice result + * @param quant - sensor quantity pointer + * @return quantity value + */ +static int32_t ReadVoice(struct SensorQuantity *quant) +{ + if (!quant) + return -1; + + uint32_t result; + if (quant->sdev->done->read != NULL) { + PrivMutexObtain(&buff_lock); + + if (quant->sdev->buffer[3] == quant->sdev->buffer[1] + quant->sdev->buffer[2]) { + result = ((uint16_t)quant->sdev->buffer[1] << 8) + (uint16_t)quant->sdev->buffer[2]; + if (result > quant->value.max_value) + quant->value.max_value = result; + else if (result < quant->value.min_value) + quant->value.min_value = result; + quant->value.last_value = result; + + return result; + }else{ + printf("This reading is wrong\n"); + result = SENSOR_QUANTITY_VALUE_ERROR; + return result; + } + }else{ + printf("%s don't have read done.\n", quant->name); + } + + return -1; +} + +/** + * @description: Init D124 voice quantity and register + * @return 0 + */ +int D124VoiceInit(void) +{ + D124Init(); + + d124_voice.name = SENSOR_QUANTITY_D124_VOICE; + d124_voice.type = SENSOR_QUANTITY_VOICE; + d124_voice.value.decimal_places = 1; + d124_voice.value.max_std = 600; + d124_voice.value.min_std = 0; + d124_voice.value.last_value = SENSOR_QUANTITY_VALUE_ERROR; + d124_voice.value.max_value = SENSOR_QUANTITY_VALUE_ERROR; + d124_voice.value.min_value = SENSOR_QUANTITY_VALUE_ERROR; + d124_voice.sdev = &d124; + d124_voice.ReadValue = ReadVoice; + + SensorQuantityRegister(&d124_voice); + + return 0; +} diff --git a/APP_Framework/Framework/sensor/winddirection/Kconfig b/APP_Framework/Framework/sensor/winddirection/Kconfig new file mode 100644 index 0000000..726bfea --- /dev/null +++ b/APP_Framework/Framework/sensor/winddirection/Kconfig @@ -0,0 +1,48 @@ + +config SENSOR_QS_FX + bool "Using qs-fx wind direction sensor" + default n + + if SENSOR_QS_FX + config SENSOR_DEVICE_QS_FX + string "qs-fx sensor name" + default "qs_fx" + + config SENSOR_QUANTITY_QS_FX_WINDDIRECTION + string "qs-fx quantity name" + default "winddirection_1" + + if ADD_XIZI_FETURES + config SENSOR_QS_FX_DRIVER_EXTUART + bool "Using extra uart to support qs-fx" + default y + + config SENSOR_DEVICE_QS_FX_DEV + string "qs-fx device name" + default "/dev/uart2_dev2" + depends on !SENSOR_QS_FX_DRIVER_EXTUART + + if SENSOR_QS_FX_DRIVER_EXTUART + config SENSOR_DEVICE_QS_FX_DEV + string "qs-fx device extra uart path" + default "/dev/extuart_dev2" + + config SENSOR_DEVICE_QS_FX_DEV_EXT_PORT + int "if qs-fx device using extuart, choose port" + default "2" + endif + endif + + if ADD_NUTTX_FETURES + config SENSOR_DEVICE_QS_FX_DEV + string "qs-fx device name" + default "/dev/ttyS1" + ---help--- + If USART1 is selected, then fill in /dev/ttyS1 here. + + endif + + if ADD_RTTHREAD_FETURES + + endif + endif diff --git a/APP_Framework/Framework/sensor/winddirection/Make.defs b/APP_Framework/Framework/sensor/winddirection/Make.defs new file mode 100644 index 0000000..75fed1c --- /dev/null +++ b/APP_Framework/Framework/sensor/winddirection/Make.defs @@ -0,0 +1,4 @@ +############################################################################ +# APP_Framework/Framework/sensor/winddirection/Make.defs +############################################################################ +include $(wildcard $(APPDIR)/../../../APP_Framework/Framework/sensor/winddirection/*/Make.defs) diff --git a/APP_Framework/Framework/sensor/winddirection/Makefile b/APP_Framework/Framework/sensor/winddirection/Makefile new file mode 100644 index 0000000..5cd11c4 --- /dev/null +++ b/APP_Framework/Framework/sensor/winddirection/Makefile @@ -0,0 +1,5 @@ +ifeq ($(CONFIG_SENSOR_QS_FX),y) + SRC_DIR += qs-fx +endif + +include $(KERNEL_ROOT)/compiler.mk diff --git a/APP_Framework/Framework/sensor/winddirection/SConscript b/APP_Framework/Framework/sensor/winddirection/SConscript new file mode 100644 index 0000000..f307e3f --- /dev/null +++ b/APP_Framework/Framework/sensor/winddirection/SConscript @@ -0,0 +1,14 @@ +import os +Import('RTT_ROOT') +from building import * + +cwd = GetCurrentDir() +objs = [] +list = os.listdir(cwd) + +for d in list: + path = os.path.join(cwd, d) + if os.path.isfile(os.path.join(path, 'SConscript')): + objs = objs + SConscript(os.path.join(path, 'SConscript')) + +Return('objs') diff --git a/APP_Framework/Framework/sensor/winddirection/qs-fx/Make.defs b/APP_Framework/Framework/sensor/winddirection/qs-fx/Make.defs new file mode 100644 index 0000000..8d9518b --- /dev/null +++ b/APP_Framework/Framework/sensor/winddirection/qs-fx/Make.defs @@ -0,0 +1,6 @@ +############################################################################ +# APP_Framework/Framework/sensor/winddirection/qs-fx/Make.defs +############################################################################ +ifneq ($(CONFIG_SENSOR_QS_FX),) +CONFIGURED_APPS += $(APPDIR)/../../../APP_Framework/Framework/sensor/winddirection/qs-fx +endif diff --git a/APP_Framework/Framework/sensor/winddirection/qs-fx/Makefile b/APP_Framework/Framework/sensor/winddirection/qs-fx/Makefile new file mode 100644 index 0000000..e455225 --- /dev/null +++ b/APP_Framework/Framework/sensor/winddirection/qs-fx/Makefile @@ -0,0 +1,11 @@ +include $(KERNEL_ROOT)/.config +ifeq ($(CONFIG_ADD_NUTTX_FETURES),y) + include $(APPDIR)/Make.defs + CSRCS += qs-fx.c + include $(APPDIR)/Application.mk +endif + +ifeq ($(CONFIG_ADD_XIZI_FETURES),y) + SRC_FILES := qs-fx.c + include $(KERNEL_ROOT)/compiler.mk +endif diff --git a/APP_Framework/Framework/sensor/winddirection/qs-fx/SConscript b/APP_Framework/Framework/sensor/winddirection/qs-fx/SConscript new file mode 100644 index 0000000..cc607cb --- /dev/null +++ b/APP_Framework/Framework/sensor/winddirection/qs-fx/SConscript @@ -0,0 +1,10 @@ +from building import * +import os + +cwd = GetCurrentDir() +src = [] +if GetDepend(['SENSOR_QS_FX']): + src += ['qs-fx.c'] +group = DefineGroup('sensor wind direction qs-fx', src, depend = [], CPPPATH = [cwd]) + +Return('group') \ No newline at end of file diff --git a/APP_Framework/Framework/sensor/winddirection/qs-fx/qs-fx.c b/APP_Framework/Framework/sensor/winddirection/qs-fx/qs-fx.c new file mode 100644 index 0000000..24a6cb7 --- /dev/null +++ b/APP_Framework/Framework/sensor/winddirection/qs-fx/qs-fx.c @@ -0,0 +1,175 @@ +/* +* Copyright (c) 2020 AIIT XUOS Lab +* XiUOS is licensed under Mulan PSL v2. +* You can use this software according to the terms and conditions of the Mulan PSL v2. +* You may obtain a copy of Mulan PSL v2 at: +* http://license.coscl.org.cn/MulanPSL2 +* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, +* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, +* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. +* See the Mulan PSL v2 for more details. +*/ + +/** + * @file qs-fx.c + * @brief qs-fx wind direction driver base sensor + * @version 1.1 + * @author AIIT XUOS Lab + * @date 2021.12.10 + */ + +#include + +static struct SensorDevice qs_fx; +static char instructions[] = {0x02, 0x03, 0x00, 0x00, 0x00, 0x01, 0x84, 0x39}; + +static struct SensorProductInfo info = +{ + SENSOR_ABILITY_WINDDIRECTION, + "清易电子", + "QS-FX", +}; + +/** + * @description: Open QS-FX voice device + * @param sdev - sensor device pointer + * @return success: 1 , failure: other + */ +#ifdef ADD_NUTTX_FETURES +static int SensorDeviceOpen(struct SensorDevice *sdev) +{ + sdev->fd = PrivOpen(SENSOR_DEVICE_QS_FX_DEV, O_RDWR); + if (sdev->fd < 0) { + printf("open %s error\n", SENSOR_DEVICE_QS_FX_DEV); + return -1; + } + + return sdev->fd ; +} +#else +static int SensorDeviceOpen(struct SensorDevice *sdev) +{ + int result = 0; + + sdev->fd = PrivOpen(SENSOR_DEVICE_QS_FX_DEV, O_RDWR); + if (sdev->fd < 0) { + printf("open %s error\n", SENSOR_DEVICE_QS_FX_DEV); + return -1; + } + + struct SerialDataCfg cfg; + cfg.serial_baud_rate = BAUD_RATE_9600; + cfg.serial_data_bits = DATA_BITS_8; + cfg.serial_stop_bits = STOP_BITS_1; + cfg.serial_buffer_size = 64; + cfg.serial_parity_mode = PARITY_NONE; + cfg.serial_bit_order = 0; + cfg.serial_invert_mode = 0; +#ifdef SENSOR_QS_FX_DRIVER_EXTUART + cfg.ext_uart_no = SENSOR_DEVICE_QS_FX_DEV_EXT_PORT; + cfg.port_configure = PORT_CFG_INIT; +#endif + + struct PrivIoctlCfg ioctl_cfg; + ioctl_cfg.ioctl_driver_type = SERIAL_TYPE; + ioctl_cfg.args = &cfg; + result = PrivIoctl(sdev->fd, OPE_INT, &ioctl_cfg); + + return result; +} +#endif + +/** + * @description: Read sensor device + * @param sdev - sensor device pointer + * @param len - the length of the read data + * @return get data length + */ +static int SensorDeviceRead(struct SensorDevice *sdev, size_t len) +{ + if (PrivWrite(sdev->fd, instructions, sizeof(instructions)) < 0) + return -1; + + if (PrivRead(sdev->fd, sdev->buffer, len) < 0) + return -1; + + return 0; +} + +static struct SensorDone done = +{ + SensorDeviceOpen, + NULL, + SensorDeviceRead, + NULL, + NULL, +}; + +/** + * @description: Init QS-FX sensor and register + * @return void + */ +static void QsFxInit(void) +{ + qs_fx.name = SENSOR_DEVICE_QS_FX; + qs_fx.info = &info; + qs_fx.done = &done; + qs_fx.status = SENSOR_DEVICE_PASSIVE; + + SensorDeviceRegister(&qs_fx); +} + + +static struct SensorQuantity qs_fx_wind_direction; + +/** + * @description: Analysis QS-FX wind direction + * @param quant - sensor quantity pointer + * @return quantity value + */ +static int32_t ReadWindDirection(struct SensorQuantity *quant) +{ + if (!quant) + return -1; + + short result; + if (quant->sdev->done->read != NULL) { + if (quant->sdev->status == SENSOR_DEVICE_PASSIVE) { + quant->sdev->done->read(quant->sdev, 6); + result = (quant->sdev->buffer[3] << 8) | quant->sdev->buffer[4]; + + return (int32_t)result; + } + if (quant->sdev->status == SENSOR_DEVICE_ACTIVE) { + printf("Please set passive mode.\n"); + } + }else{ + printf("%s don't have read done.\n", quant->name); + } + + return -1; +} + +/** + * @description: Init QS-FX voice quantity and register + * @return 0 + */ +int QsFxWindDirectionInit(void) +{ + QsFxInit(); + + qs_fx_wind_direction.name = SENSOR_QUANTITY_QS_FX_WINDDIRECTION; + qs_fx_wind_direction.type = SENSOR_QUANTITY_WINDDIRECTION; + qs_fx_wind_direction.value.decimal_places = 1; + qs_fx_wind_direction.value.max_std = 600; + qs_fx_wind_direction.value.min_std = 0; + qs_fx_wind_direction.value.last_value = SENSOR_QUANTITY_VALUE_ERROR; + qs_fx_wind_direction.value.max_value = SENSOR_QUANTITY_VALUE_ERROR; + qs_fx_wind_direction.value.min_value = SENSOR_QUANTITY_VALUE_ERROR; + qs_fx_wind_direction.sdev = &qs_fx; + qs_fx_wind_direction.ReadValue = ReadWindDirection; + + SensorQuantityRegister(&qs_fx_wind_direction); + + return 0; +} diff --git a/APP_Framework/Framework/sensor/windspeed/Kconfig b/APP_Framework/Framework/sensor/windspeed/Kconfig new file mode 100644 index 0000000..91bc1fb --- /dev/null +++ b/APP_Framework/Framework/sensor/windspeed/Kconfig @@ -0,0 +1,48 @@ + +config SENSOR_QS_FS + bool "Using qs-fs wind speed sensor" + default n + + if SENSOR_QS_FS + config SENSOR_DEVICE_QS_FS + string "qs-fs sensor name" + default "qs-fs" + + config SENSOR_QUANTITY_QS_FS_WINDSPEED + string "qs-fs quantity name" + default "windspeed_1" + + if ADD_XIZI_FETURES + config SENSOR_QS_FS_DRIVER_EXTUART + bool "Using extra uart to support qs-fx" + default y + + config SENSOR_DEVICE_QS_FS_DEV + string "qs-fx device name" + default "/dev/uart2_dev2" + depends on !SENSOR_QS_FS_DRIVER_EXTUART + + if SENSOR_QS_FS_DRIVER_EXTUART + config SENSOR_DEVICE_QS_FS_DEV + string "qs-fx device extra uart path" + default "/dev/extuart_dev7" + + config SENSOR_DEVICE_QS_FS_DEV_EXT_PORT + int "if qs-fx device using extuart, choose port" + default "7" + endif + endif + + if ADD_NUTTX_FETURES + config SENSOR_DEVICE_QS_FS_DEV + string "qs-fx device name" + default "/dev/ttyS1" + ---help--- + If USART1 is selected, then fill in /dev/ttyS1 here. + + endif + + if ADD_RTTHREAD_FETURES + + endif + endif diff --git a/APP_Framework/Framework/sensor/windspeed/Make.defs b/APP_Framework/Framework/sensor/windspeed/Make.defs new file mode 100644 index 0000000..ae97154 --- /dev/null +++ b/APP_Framework/Framework/sensor/windspeed/Make.defs @@ -0,0 +1,4 @@ +############################################################################ +# APP_Framework/Framework/sensor/windspeed/Make.defs +############################################################################ +include $(wildcard $(APPDIR)/../../../APP_Framework/Framework/sensor/windspeed/*/Make.defs) diff --git a/APP_Framework/Framework/sensor/windspeed/Makefile b/APP_Framework/Framework/sensor/windspeed/Makefile new file mode 100644 index 0000000..39db45e --- /dev/null +++ b/APP_Framework/Framework/sensor/windspeed/Makefile @@ -0,0 +1,5 @@ +ifeq ($(CONFIG_SENSOR_QS_FS),y) + SRC_DIR += qs-fs +endif + +include $(KERNEL_ROOT)/compiler.mk diff --git a/APP_Framework/Framework/sensor/windspeed/SConscript b/APP_Framework/Framework/sensor/windspeed/SConscript new file mode 100644 index 0000000..f307e3f --- /dev/null +++ b/APP_Framework/Framework/sensor/windspeed/SConscript @@ -0,0 +1,14 @@ +import os +Import('RTT_ROOT') +from building import * + +cwd = GetCurrentDir() +objs = [] +list = os.listdir(cwd) + +for d in list: + path = os.path.join(cwd, d) + if os.path.isfile(os.path.join(path, 'SConscript')): + objs = objs + SConscript(os.path.join(path, 'SConscript')) + +Return('objs') diff --git a/APP_Framework/Framework/sensor/windspeed/qs-fs/Make.defs b/APP_Framework/Framework/sensor/windspeed/qs-fs/Make.defs new file mode 100644 index 0000000..8edbfb6 --- /dev/null +++ b/APP_Framework/Framework/sensor/windspeed/qs-fs/Make.defs @@ -0,0 +1,6 @@ +############################################################################ +# APP_Framework/Framework/sensor/windspeed/qs-fs/Make.defs +############################################################################ +ifneq ($(CONFIG_SENSOR_QS_FS),) +CONFIGURED_APPS += $(APPDIR)/../../../APP_Framework/Framework/sensor/windspeed/qs-fs +endif diff --git a/APP_Framework/Framework/sensor/windspeed/qs-fs/Makefile b/APP_Framework/Framework/sensor/windspeed/qs-fs/Makefile new file mode 100644 index 0000000..a687257 --- /dev/null +++ b/APP_Framework/Framework/sensor/windspeed/qs-fs/Makefile @@ -0,0 +1,11 @@ +include $(KERNEL_ROOT)/.config +ifeq ($(CONFIG_ADD_NUTTX_FETURES),y) + include $(APPDIR)/Make.defs + CSRCS += qs-fs.c + include $(APPDIR)/Application.mk +endif + +ifeq ($(CONFIG_ADD_XIZI_FETURES),y) + SRC_FILES := qs-fs.c + include $(KERNEL_ROOT)/compiler.mk +endif diff --git a/APP_Framework/Framework/sensor/windspeed/qs-fs/SConscript b/APP_Framework/Framework/sensor/windspeed/qs-fs/SConscript new file mode 100644 index 0000000..a38a757 --- /dev/null +++ b/APP_Framework/Framework/sensor/windspeed/qs-fs/SConscript @@ -0,0 +1,10 @@ +from building import * +import os + +cwd = GetCurrentDir() +src = [] +if GetDepend(['SENSOR_QS_FS']): + src += ['qs-fs.c'] +group = DefineGroup('sensor wind speed qs-fs', src, depend = [], CPPPATH = [cwd]) + +Return('group') \ No newline at end of file diff --git a/APP_Framework/Framework/sensor/windspeed/qs-fs/qs-fs.c b/APP_Framework/Framework/sensor/windspeed/qs-fs/qs-fs.c new file mode 100644 index 0000000..427fa82 --- /dev/null +++ b/APP_Framework/Framework/sensor/windspeed/qs-fs/qs-fs.c @@ -0,0 +1,174 @@ +/* +* Copyright (c) 2020 AIIT XUOS Lab +* XiUOS is licensed under Mulan PSL v2. +* You can use this software according to the terms and conditions of the Mulan PSL v2. +* You may obtain a copy of Mulan PSL v2 at: +* http://license.coscl.org.cn/MulanPSL2 +* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, +* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, +* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. +* See the Mulan PSL v2 for more details. +*/ + +/** + * @file qs-fs.c + * @brief qs-fs wind speed driver base sensor + * @version 1.1 + * @author AIIT XUOS Lab + * @date 2021.12.10 + */ + +#include + +static struct SensorDevice qs_fs; +static const unsigned char instructions[] = {0x01, 0x03, 0x00, 0x00, 0x00, 0x01, 0x84, 0x0A}; + +static struct SensorProductInfo info = +{ + SENSOR_ABILITY_WINDSPEED, + "清易电子", + "QS-FS", +}; + +/** + * @description: Open QS-FS voice device + * @param sdev - sensor device pointer + * @return success: 1 , failure: other + */ +#ifdef ADD_NUTTX_FETURES +static int SensorDeviceOpen(struct SensorDevice *sdev) +{ + sdev->fd = PrivOpen(SENSOR_DEVICE_QS_FS_DEV, O_RDWR); + if (sdev->fd < 0) { + printf("open %s error\n", SENSOR_DEVICE_QS_FS_DEV); + return -1; + } + return sdev->fd; +} +#else +static int SensorDeviceOpen(struct SensorDevice *sdev) +{ + int result = 0; + + sdev->fd = PrivOpen(SENSOR_DEVICE_QS_FS_DEV, O_RDWR); + if (sdev->fd < 0) { + printf("open %s error\n", SENSOR_DEVICE_QS_FS_DEV); + return -1; + } + + struct SerialDataCfg cfg; + cfg.serial_baud_rate = BAUD_RATE_9600; + cfg.serial_data_bits = DATA_BITS_8; + cfg.serial_stop_bits = STOP_BITS_1; + cfg.serial_buffer_size = 64; + cfg.serial_parity_mode = PARITY_NONE; + cfg.serial_bit_order = 0; + cfg.serial_invert_mode = 0; +#ifdef SENSOR_QS_FS_DRIVER_EXTUART + cfg.ext_uart_no = SENSOR_DEVICE_QS_FS_DEV_EXT_PORT; + cfg.port_configure = PORT_CFG_INIT; +#endif + + struct PrivIoctlCfg ioctl_cfg; + ioctl_cfg.ioctl_driver_type = SERIAL_TYPE; + ioctl_cfg.args = &cfg; + result = PrivIoctl(sdev->fd, OPE_INT, &ioctl_cfg); + + return result; +} +#endif + +/** + * @description: Read sensor device + * @param sdev - sensor device pointer + * @param len - the length of the read data + * @return get data length + */ +static int SensorDeviceRead(struct SensorDevice *sdev, size_t len) +{ + if (PrivWrite(sdev->fd, instructions, sizeof(instructions)) < 0) + return -1; + + if (PrivRead(sdev->fd, sdev->buffer, len) < 0) + return -1; + + return 0; +} + +static struct SensorDone done = +{ + SensorDeviceOpen, + NULL, + SensorDeviceRead, + NULL, + NULL, +}; + +/** + * @description: Init QS-FS sensor and register + * @return void + */ +static void QsFsInit(void) +{ + qs_fs.name = SENSOR_DEVICE_QS_FS; + qs_fs.info = &info; + qs_fs.done = &done; + qs_fs.status = SENSOR_DEVICE_PASSIVE; + + SensorDeviceRegister(&qs_fs); +} + + +static struct SensorQuantity qs_fs_wind_speed; + +/** + * @description: Analysis QS-FS wind speed + * @param quant - sensor quantity pointer + * @return quantity value + */ +static int32_t ReadWindSpeed(struct SensorQuantity *quant) +{ + if (!quant) + return -1; + + short result; + if (quant->sdev->done->read != NULL) { + if (quant->sdev->status == SENSOR_DEVICE_PASSIVE) { + quant->sdev->done->read(quant->sdev, 6); + result = (quant->sdev->buffer[3] << 8) | quant->sdev->buffer[4]; + + return (int32_t)result; + } + if (quant->sdev->status == SENSOR_DEVICE_ACTIVE) { + printf("Please set passive mode.\n"); + } + }else{ + printf("%s don't have read done.\n", quant->name); + } + + return -1; +} + +/** + * @description: Init QS-FS voice quantity and register + * @return 0 + */ +int QsFsWindSpeedInit(void) +{ + QsFsInit(); + + qs_fs_wind_speed.name = SENSOR_QUANTITY_QS_FS_WINDSPEED; + qs_fs_wind_speed.type = SENSOR_QUANTITY_WINDSPEED; + qs_fs_wind_speed.value.decimal_places = 1; + qs_fs_wind_speed.value.max_std = 600; + qs_fs_wind_speed.value.min_std = 0; + qs_fs_wind_speed.value.last_value = SENSOR_QUANTITY_VALUE_ERROR; + qs_fs_wind_speed.value.max_value = SENSOR_QUANTITY_VALUE_ERROR; + qs_fs_wind_speed.value.min_value = SENSOR_QUANTITY_VALUE_ERROR; + qs_fs_wind_speed.sdev = &qs_fs; + qs_fs_wind_speed.ReadValue = ReadWindSpeed; + + SensorQuantityRegister(&qs_fs_wind_speed); + + return 0; +} diff --git a/APP_Framework/Framework/transform_layer/Makefile b/APP_Framework/Framework/transform_layer/Makefile new file mode 100644 index 0000000..6a6d096 --- /dev/null +++ b/APP_Framework/Framework/transform_layer/Makefile @@ -0,0 +1,7 @@ +SRC_DIR := + +ifeq ($(CONFIG_ADD_XIZI_FETURES),y) + SRC_DIR += xizi +endif + +include $(KERNEL_ROOT)/compiler.mk \ No newline at end of file diff --git a/APP_Framework/Framework/transform_layer/SConscript b/APP_Framework/Framework/transform_layer/SConscript new file mode 100644 index 0000000..f307e3f --- /dev/null +++ b/APP_Framework/Framework/transform_layer/SConscript @@ -0,0 +1,14 @@ +import os +Import('RTT_ROOT') +from building import * + +cwd = GetCurrentDir() +objs = [] +list = os.listdir(cwd) + +for d in list: + path = os.path.join(cwd, d) + if os.path.isfile(os.path.join(path, 'SConscript')): + objs = objs + SConscript(os.path.join(path, 'SConscript')) + +Return('objs') diff --git a/APP_Framework/Framework/transform_layer/nuttx/Makefile b/APP_Framework/Framework/transform_layer/nuttx/Makefile new file mode 100644 index 0000000..1b72ae2 --- /dev/null +++ b/APP_Framework/Framework/transform_layer/nuttx/Makefile @@ -0,0 +1,5 @@ +include $(KERNEL_ROOT)/.config +include $(APPDIR)/Make.defs +CSRCS = transform.c + +include $(APPDIR)/Application.mk \ No newline at end of file diff --git a/APP_Framework/Framework/transform_layer/nuttx/transform.c b/APP_Framework/Framework/transform_layer/nuttx/transform.c new file mode 100644 index 0000000..45d8d30 --- /dev/null +++ b/APP_Framework/Framework/transform_layer/nuttx/transform.c @@ -0,0 +1,192 @@ +/* +* Copyright (c) 2020 AIIT XUOS Lab +* XiUOS is licensed under Mulan PSL v2. +* You can use this software according to the terms and conditions of the Mulan PSL v2. +* You may obtain a copy of Mulan PSL v2 at: +* http://license.coscl.org.cn/MulanPSL2 +* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, +* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, +* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. +* See the Mulan PSL v2 for more details. +*/ + +/** + * @file transform.c + * @brief Converts the framework interface to an operating system interface + * @version 1.0 + * @author AIIT XUOS Lab + * @date 2021.06.07 + */ + +#include "transform.h" + +/**************************mutex***************************/ +/* private mutex API */ +int PrivMutexCreate(pthread_mutex_t *p_mutex, const pthread_mutexattr_t *attr) +{ + return pthread_mutex_init(p_mutex, attr); +} + +int PrivMutexDelete(pthread_mutex_t *p_mutex) +{ + return pthread_mutex_destroy(p_mutex); +} + +int PrivMutexObtain(pthread_mutex_t *p_mutex) +{ + return pthread_mutex_lock(p_mutex); +} + +int PrivMutexAbandon(pthread_mutex_t *p_mutex) +{ + return pthread_mutex_unlock(p_mutex); +} + +/**********************semaphore****************************/ +int PrivSemaphoreCreate(sem_t *sem, int pshared, unsigned int value) +{ + return sem_init(sem, pshared, value); +} + +int PrivSemaphoreDelete(sem_t *sem) +{ + return sem_destroy(sem); +} + +int PrivSemaphoreObtainWait(sem_t *sem, const struct timespec *abstime) +{ + struct timespec timeout; + clock_gettime(CLOCK_REALTIME, &timeout); + timeout.tv_sec += abstime->tv_sec; + return sem_timedwait(sem, &timeout); +} + +int PrivSemaphoreObtainWaitForever(sem_t *sem) +{ + return sem_wait(sem); +} + +int PrivSemaphoreObtainNoWait(sem_t *sem) +{ + return sem_trywait(sem); +} + +int PrivSemaphoreAbandon(sem_t *sem) +{ + return sem_post(sem); +} + +/**************************task*************************/ +int PrivTaskCreate(pthread_t *thread, const pthread_attr_t *attr, + void *(*start_routine)(void *), void *arg) +{ + return pthread_create(thread, attr, start_routine, arg); +} + +int PrivTaskStartup(pthread_t *thread) +{ + return 0; +} + +int PrivTaskDelete(pthread_t thread, int sig) +{ + return pthread_kill(thread, sig); +} + +void PrivTaskQuit(void *value_ptr) +{ + pthread_exit(value_ptr); +} + +int PrivTaskDelay(int32_t ms) +{ + return usleep(1000 * ms); +} + +uint32_t PrivGetTickTime(void) +{ + struct timespec ts; + clock_gettime(CLOCK_MONOTONIC, &ts); + return ts.tv_sec * 1000 + ts.tv_nsec / 1000000; +} + +/*********************fs**************************/ + +/************************Driver Posix Transform***********************/ +int PrivOpen(const char *path, int flags) +{ + return open(path, flags); +} + +int PrivClose(int fd) +{ + return close(fd); +} + +int PrivRead(int fd, void *buf, size_t len) +{ + return read(fd, buf, len); +} + +int PrivWrite(int fd, const void *buf, size_t len) +{ + return write(fd, buf, len); +} + +static int PrivSerialIoctl(int fd, int cmd, void *args) +{ + struct SerialDataCfg *serial_cfg = (struct SerialDataCfg *)args; + return ioctl(fd, cmd, serial_cfg); +} + +static int PrivPinIoctl(int fd, int cmd, void *args) +{ + struct PinParam *pin_cfg = (struct PinParam *)args; + + return ioctl(fd, cmd, pin_cfg); +} + +int PrivIoctl(int fd, int cmd, void *args) +{ + int ret = 0; + struct PrivIoctlCfg *ioctl_cfg = (struct PrivIoctlCfg *)args; + + switch (ioctl_cfg->ioctl_driver_type) + { + case SERIAL_TYPE: + ret = PrivSerialIoctl(fd, cmd, ioctl_cfg->args); + break; + case PIN_TYPE: + ret = PrivPinIoctl(fd, cmd, ioctl_cfg->args); + break; + case I2C_TYPE: + ret = ioctl(fd, cmd, ioctl_cfg->args); + break; + default: + break; + } + + return ret; +} + +/********************memory api************/ +void *PrivMalloc(size_t size) +{ + return malloc(size); +} + +void *PrivRealloc(void *pointer, size_t size) +{ + return realloc(pointer, size); +} + +void *PrivCalloc(size_t count, size_t size) +{ + return calloc(count, size); +} + +void PrivFree(void *pointer) +{ + free(pointer); +} + diff --git a/APP_Framework/Framework/transform_layer/nuttx/transform.h b/APP_Framework/Framework/transform_layer/nuttx/transform.h new file mode 100644 index 0000000..1cf6b83 --- /dev/null +++ b/APP_Framework/Framework/transform_layer/nuttx/transform.h @@ -0,0 +1,218 @@ +/* +* Copyright (c) 2020 AIIT XUOS Lab +* XiUOS is licensed under Mulan PSL v2. +* You can use this software according to the terms and conditions of the Mulan PSL v2. +* You may obtain a copy of Mulan PSL v2 at: +* http://license.coscl.org.cn/MulanPSL2 +* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, +* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, +* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. +* See the Mulan PSL v2 for more details. +*/ + +/** + * @file transform.h + * @brief Interface function declarations required by the framework + * @version 1.0 + * @author AIIT XUOS Lab + * @date 2021.06.04 + */ + +#ifndef TRANSFORM_H +#define TRANSFORM_H + +#include +#include +#include +#include +#include +#include +#include + +typedef uint8_t uint8; +typedef uint16_t uint16; +typedef uint32_t uint32; +typedef uint64_t uint64; + +typedef int8_t int8; +typedef int16_t int16; +typedef int32_t int32; +typedef int64_t int64; + +#ifdef __cplusplus +extern "C" { +#endif + +#define OPE_INT 0x0000 +#define OPE_CFG 0x0001 + +#define NAME_NUM_MAX 32 + +/*********************GPIO define*********************/ +#define GPIO_LOW 0x00 +#define GPIO_HIGH 0x01 + +#define GPIO_CFG_OUTPUT 0x00 +#define GPIO_CFG_INPUT 0x01 +#define GPIO_CFG_INPUT_PULLUP 0x02 +#define GPIO_CFG_INPUT_PULLDOWN 0x03 +#define GPIO_CFG_OUTPUT_OD 0x04 + +#define GPIO_CONFIG_MODE 0xffffffff + +/********************SERIAL define*******************/ +#define BAUD_RATE_2400 2400 +#define BAUD_RATE_4800 4800 +#define BAUD_RATE_9600 9600 +#define BAUD_RATE_19200 19200 +#define BAUD_RATE_38400 38400 +#define BAUD_RATE_57600 57600 +#define BAUD_RATE_115200 115200 +#define BAUD_RATE_230400 230400 +#define BAUD_RATE_460800 460800 +#define BAUD_RATE_921600 921600 +#define BAUD_RATE_2000000 2000000 +#define BAUD_RATE_3000000 3000000 + +#define DATA_BITS_5 5 +#define DATA_BITS_6 6 +#define DATA_BITS_7 7 +#define DATA_BITS_8 8 +#define DATA_BITS_9 9 + +#define STOP_BITS_1 1 +#define STOP_BITS_2 2 +#define STOP_BITS_3 3 +#define STOP_BITS_4 4 + +#define PARITY_NONE 1 +#define PARITY_ODD 2 +#define PARITY_EVEN 3 + +#define BIT_ORDER_LSB 1 +#define BIT_ORDER_MSB 2 + +#define NRZ_NORMAL 1 +#define NRZ_INVERTED 2 + +#ifndef SERIAL_RB_BUFSZ +#define SERIAL_RB_BUFSZ 128 +#endif + +struct PinDevIrq +{ + int irq_mode;//< RISING/FALLING/HIGH/LOW + void (*hdr) (void *args);//< callback function + void *args;//< the params of callback function +}; + +struct PinParam +{ + int cmd;//< cmd:GPIO_CONFIG_MODE/GPIO_IRQ_REGISTER/GPIO_IRQ_FREE/GPIO_IRQ_DISABLE/GPIO_IRQ_ENABLE + long pin;//< pin number + int mode;//< pin mode: input/output + struct PinDevIrq irq_set;//< pin irq set + uint64 arg; +}; + +struct PinStat +{ + long pin;//< pin number + uint16_t val;//< pin level +}; + +enum ExtSerialPortConfigure +{ + PORT_CFG_INIT = 0, + PORT_CFG_PARITY_CHECK, + PORT_CFG_DISABLE, + PORT_CFG_DIV, +}; + +struct SerialDataCfg +{ + uint32_t serial_baud_rate; + uint8_t serial_data_bits; + uint8_t serial_stop_bits; + uint8_t serial_parity_mode; + uint8_t serial_bit_order; + uint8_t serial_invert_mode; + uint16_t serial_buffer_size; + + uint8 ext_uart_no; + enum ExtSerialPortConfigure port_configure; +}; + +enum IoctlDriverType +{ + SERIAL_TYPE = 0, + SPI_TYPE, + I2C_TYPE, + PIN_TYPE, + DEFAULT_TYPE, +}; + +struct PrivIoctlCfg +{ + enum IoctlDriverType ioctl_driver_type; + void *args; +}; + +int open(FAR const char *path, int oflags, ...); +int ioctl(int fd, int req, ...); +FAR void *malloc(size_t size); +FAR void *realloc(FAR void *oldmem, size_t size); +FAR void *calloc(size_t n, size_t elem_size); +void free(FAR void *mem); + +/**********************mutex**************************/ + +int PrivMutexCreate(pthread_mutex_t *p_mutex, const pthread_mutexattr_t *attr); +int PrivMutexDelete(pthread_mutex_t *p_mutex); +int PrivMutexObtain(pthread_mutex_t *p_mutex); +int PrivMutexAbandon(pthread_mutex_t *p_mutex); + + + + +/*********************semaphore**********************/ + +int PrivSemaphoreCreate(sem_t *sem, int pshared, unsigned int value); +int PrivSemaphoreDelete(sem_t *sem); +int PrivSemaphoreObtainWait(sem_t *sem, const struct timespec *abstime); +int PrivSemaphoreObtainWaitForever(sem_t *sem); +int PrivSemaphoreObtainNoWait(sem_t *sem); +int PrivSemaphoreAbandon(sem_t *sem); +int32_t PrivSemaphoreSetValue(int32_t sem, uint16_t val); + +/*********************task**************************/ + +int PrivTaskCreate(pthread_t *thread, const pthread_attr_t *attr, + void *(*start_routine)(void *), void *arg); +int PrivTaskStartup(pthread_t *thread); +int PrivTaskDelete(pthread_t thread, int sig); +void PrivTaskQuit(void *value_ptr); +int PrivTaskDelay(int32_t ms); +uint32_t PrivGetTickTime(void); + +/*********************driver*************************/ + +int PrivOpen(const char *path, int flags); +int PrivRead(int fd, void *buf, size_t len); +int PrivWrite(int fd, const void *buf, size_t len); +int PrivClose(int fd); +int PrivIoctl(int fd, int cmd, void *args); + +/*********************memory***********************/ + +void *PrivMalloc(size_t size); +void *PrivRealloc(void *pointer, size_t size); +void *PrivCalloc(size_t count, size_t size); +void PrivFree(void *pointer); + + +#ifdef __cplusplus +} +#endif + +#endif \ No newline at end of file diff --git a/APP_Framework/Framework/transform_layer/rtthread/SConscript b/APP_Framework/Framework/transform_layer/rtthread/SConscript new file mode 100644 index 0000000..c015125 --- /dev/null +++ b/APP_Framework/Framework/transform_layer/rtthread/SConscript @@ -0,0 +1,11 @@ +import os +from building import * +Import('RTT_ROOT') +Import('rtconfig') +cwd = GetCurrentDir() +DEPENDS = [""] + +SOURCES = ['transform.c'] +path = [cwd] +objs = DefineGroup('transform', src = SOURCES, depend = DEPENDS,CPPPATH = path) +Return("objs") \ No newline at end of file diff --git a/APP_Framework/Framework/transform_layer/rtthread/transform.c b/APP_Framework/Framework/transform_layer/rtthread/transform.c new file mode 100644 index 0000000..e792184 --- /dev/null +++ b/APP_Framework/Framework/transform_layer/rtthread/transform.c @@ -0,0 +1,197 @@ +/* +* Copyright (c) 2020 AIIT XUOS Lab +* XiUOS is licensed under Mulan PSL v2. +* You can use this software according to the terms and conditions of the Mulan PSL v2. +* You may obtain a copy of Mulan PSL v2 at: +* http://license.coscl.org.cn/MulanPSL2 +* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, +* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, +* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. +* See the Mulan PSL v2 for more details. +*/ + +/** + * @file xiuos.c + * @brief Converts the framework interface to an operating system interface + * @version 1.0 + * @author AIIT XUOS Lab + * @date 2021.06.07 + */ + +#include + +/**************************mutex***************************/ +/* private mutex API */ +int PrivMutexCreate(pthread_mutex_t *p_mutex, const pthread_mutexattr_t *attr) +{ + return pthread_mutex_init(p_mutex, attr); +} + +int PrivMutexDelete(pthread_mutex_t *p_mutex) +{ + return pthread_mutex_destroy(p_mutex); +} + +int PrivMutexObtain(pthread_mutex_t *p_mutex) +{ + return pthread_mutex_lock(p_mutex); +} + +int PrivMutexAbandon(pthread_mutex_t *p_mutex) +{ + return pthread_mutex_unlock(p_mutex); +} + +/**********************semaphore****************************/ +int PrivSemaphoreCreate(sem_t *sem, int pshared, unsigned int value) +{ + return sem_init(sem, pshared, value); +} + +int PrivSemaphoreDelete(sem_t *sem) +{ + return sem_destroy(sem); +} + +int PrivSemaphoreObtainWait(sem_t *sem, const struct timespec *abstime) +{ + return sem_timedwait(sem, abstime); +} + +int PrivSemaphoreObtainNoWait(sem_t *sem) +{ + return sem_trywait(sem); +} + +int PrivSemaphoreAbandon(sem_t *sem) +{ + return sem_post(sem); +} + +/**************************task*************************/ +int PrivTaskCreate(pthread_t *thread, const pthread_attr_t *attr, + void *(*start_routine)(void *), void *arg) +{ + pthread_attr_t attrtmp ; + pthread_attr_init(&attrtmp); + pthread_attr_setschedparam(&attrtmp, &(attr->schedparam)); /* 修改属性对应的优先级 */ + pthread_attr_setstacksize(&attrtmp, (size_t)((attr->stacksize))); + return pthread_create(thread, &attrtmp, start_routine, arg); +} + +int PrivTaskStartup(pthread_t *thread) +{ + return 0; +} + +int PrivTaskDelete(pthread_t thread, int sig) +{ + _pthread_data_t *ptd; + ptd = _pthread_get_data(thread); + return rt_thread_detach(ptd->tid); +} + +void PrivTaskQuit(void *value_ptr) +{ + pthread_exit(value_ptr); +} + +int PrivTaskDelay(int32_t ms) +{ + rt_thread_mdelay(ms); +} + +uint32_t PrivGetTickTime() +{ + return rt_tick_get_millisecond(); +} + +/*********************fs**************************/ + +/************************Driver Posix Transform***********************/ +int PrivOpen(const char *path, int flags) +{ + return open(path, flags); +} + +int PrivClose(int fd) +{ + return close(fd); +} + +int PrivRead(int fd, void *buf, size_t len) +{ + return read(fd, buf, len); +} + +int PrivWrite(int fd, const void *buf, size_t len) +{ + return write(fd, buf, len); +} + +static int PrivSerialIoctl(int fd, int cmd, void *args) +{ + struct dfs_fd *rt_fd; + int ret = 0; + struct serial_configure config = RT_SERIAL_CONFIG_DEFAULT; + struct SerialDataCfg *serial_cfg = (struct SerialDataCfg *)args; + config.baud_rate = serial_cfg->serial_baud_rate; + config.data_bits = serial_cfg->serial_data_bits; + config.stop_bits = serial_cfg->serial_stop_bits; + config.bufsz = RT_SERIAL_RB_BUFSZ; + config.parity = serial_cfg->serial_parity_mode; + config.invert = serial_cfg->serial_invert_mode; + config.reserved = serial_cfg->ext_uart_no; ///< using extuart port number + rt_fd = fd_get(fd); + ret = rt_fd->fops->ioctl(rt_fd, RT_DEVICE_CTRL_CONFIG, &config); + return ret; +} + +static int PrivPinIoctl(int fd, int cmd, void *args) +{ + struct PinParam *pin_cfg = (struct PinParam *)args; + + return ioctl(fd, cmd, pin_cfg); +} + +int PrivIoctl(int fd, int cmd, void *args) +{ + int ret; + struct PrivIoctlCfg *ioctl_cfg = (struct PrivIoctlCfg *)args; + + switch (ioctl_cfg->ioctl_driver_type) + { + case SERIAL_TYPE: + ret = PrivSerialIoctl(fd, cmd, ioctl_cfg->args); + break; + case PIN_TYPE: + ret = PrivPinIoctl(fd, cmd, ioctl_cfg->args); + break; + default: + break; + } + + return ret; +} + +/********************memory api************/ +void *PrivMalloc(size_t size) +{ + return malloc(size); +} + +void *PrivRealloc(void *pointer, size_t size) +{ + return realloc(pointer, size); +} + +void *PrivCalloc(size_t count, size_t size) +{ + return calloc(count, size); +} + +void PrivFree(void *pointer) +{ + free(pointer); +} + diff --git a/APP_Framework/Framework/transform_layer/rtthread/transform.h b/APP_Framework/Framework/transform_layer/rtthread/transform.h new file mode 100644 index 0000000..1210976 --- /dev/null +++ b/APP_Framework/Framework/transform_layer/rtthread/transform.h @@ -0,0 +1,204 @@ +/* +* Copyright (c) 2020 AIIT XUOS Lab +* XiUOS is licensed under Mulan PSL v2. +* You can use this software according to the terms and conditions of the Mulan PSL v2. +* You may obtain a copy of Mulan PSL v2 at: +* http://license.coscl.org.cn/MulanPSL2 +* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, +* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, +* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. +* See the Mulan PSL v2 for more details. +*/ + +/** + * @file transform.h + * @brief Interface function declarations required by the framework + * @version 1.0 + * @author AIIT XUOS Lab + * @date 2021.06.04 + */ + +#ifndef TRANSFORM_H +#define TRANSFORM_H +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#ifdef RT_USING_POSIX_TERMIOS +#include +#endif +#ifdef DRV_USING_OV2640 +#include +#endif +#if defined(RT_USING_SAL)&& defined (RT_USING_LWIP) +#include +#include +#elif defined RT_USING_LWIP +#include +#include +#endif /* RT_USING_SAL */ +#ifdef BOARD_K210_EVB +#include +#include +#endif + + +#ifdef __cplusplus +extern "C" { +#endif + +typedef signed char int8; +typedef signed short int16; +typedef signed int int32; +typedef unsigned char uint8; +typedef unsigned short uint16; +typedef unsigned int uint32; + +#ifdef ARCH_CPU_64BIT +typedef signed long int64; +typedef unsigned long uint64; +#else +typedef signed long long int64; +typedef unsigned long long uint64; +#endif + +#define OPE_INT 0x0000 +#define OPE_CFG 0x0001 + +#define NAME_NUM_MAX 32 + +/*********************GPIO define*********************/ +#define GPIO_LOW 0x00 +#define GPIO_HIGH 0x01 + +#define GPIO_CFG_OUTPUT 0x00 +#define GPIO_CFG_INPUT 0x01 +#define GPIO_CFG_INPUT_PULLUP 0x02 +#define GPIO_CFG_INPUT_PULLDOWN 0x03 +#define GPIO_CFG_OUTPUT_OD 0x04 + +#define GPIO_CONFIG_MODE 0xffffffff +#ifndef SERIAL_RB_BUFSZ +#define SERIAL_RB_BUFSZ 128 +#endif + +struct PinDevIrq +{ + int irq_mode;//< RISING/FALLING/HIGH/LOW + void (*hdr) (void *args);//< callback function + void *args;//< the params of callback function +}; + +struct PinParam +{ + int cmd;//< cmd:GPIO_CONFIG_MODE/GPIO_IRQ_REGISTER/GPIO_IRQ_FREE/GPIO_IRQ_DISABLE/GPIO_IRQ_ENABLE + long pin;//< pin number + int mode;//< pin mode: input/output + struct PinDevIrq irq_set;//< pin irq set + uint64_t arg; +}; + +struct PinStat +{ + long pin;//< pin number + uint16_t val;//< pin level +}; + +enum ExtSerialPortConfigure +{ + PORT_CFG_INIT = 0, + PORT_CFG_PARITY_CHECK, + PORT_CFG_DISABLE, + PORT_CFG_DIV, +}; + +struct SerialDataCfg +{ + uint32_t serial_baud_rate; + uint8_t serial_data_bits; + uint8_t serial_stop_bits; + uint8_t serial_parity_mode; + uint8_t serial_bit_order; + uint8_t serial_invert_mode; + uint16_t serial_buffer_size; + + uint8_t ext_uart_no; + enum ExtSerialPortConfigure port_configure; +}; + +enum IoctlDriverType +{ + SERIAL_TYPE = 0, + SPI_TYPE, + I2C_TYPE, + PIN_TYPE, + DEFAULT_TYPE, +}; + +struct PrivIoctlCfg +{ + enum IoctlDriverType ioctl_driver_type; + void *args; +}; + +/**********************mutex**************************/ + +int PrivMutexCreate(pthread_mutex_t *p_mutex, const pthread_mutexattr_t *attr); +int PrivMutexDelete(pthread_mutex_t *p_mutex); +int PrivMutexObtain(pthread_mutex_t *p_mutex); +int PrivMutexAbandon(pthread_mutex_t *p_mutex); + +/*********************semaphore**********************/ + +int PrivSemaphoreCreate(sem_t *sem, int pshared, unsigned int value); +int PrivSemaphoreDelete(sem_t *sem); +int PrivSemaphoreObtainWait(sem_t *sem, const struct timespec *abstime); +int PrivSemaphoreObtainNoWait(sem_t *sem); +int PrivSemaphoreAbandon(sem_t *sem); +int32_t PrivSemaphoreSetValue(int32_t sem, uint16_t val); + +/*********************task**************************/ + +int PrivTaskCreate(pthread_t *thread, const pthread_attr_t *attr, + void *(*start_routine)(void *), void *arg); +int PrivTaskStartup(pthread_t *thread); +int PrivTaskDelete(pthread_t thread, int sig); +void PrivTaskQuit(void *value_ptr); +int PrivTaskDelay(int32_t ms); +uint32_t PrivGetTickTime(); + +/*********************driver*************************/ + +int PrivOpen(const char *path, int flags); +int PrivRead(int fd, void *buf, size_t len); +int PrivWrite(int fd, const void *buf, size_t len); +int PrivClose(int fd); +int PrivIoctl(int fd, int cmd, void *args); + +/*********************memory***********************/ + +void *PrivMalloc(size_t size); +void *PrivRealloc(void *pointer, size_t size); +void *PrivCalloc(size_t count, size_t size); +void PrivFree(void *pointer); + + +#ifdef __cplusplus +} +#endif + +#endif \ No newline at end of file diff --git a/APP_Framework/Framework/transform_layer/xizi/Makefile b/APP_Framework/Framework/transform_layer/xizi/Makefile new file mode 100644 index 0000000..c62b9d5 --- /dev/null +++ b/APP_Framework/Framework/transform_layer/xizi/Makefile @@ -0,0 +1,5 @@ +SRC_DIR := user_api +SRC_FILES := userspace.c transform.c + +include $(KERNEL_ROOT)/compiler.mk + diff --git a/APP_Framework/Framework/transform_layer/xizi/transform.c b/APP_Framework/Framework/transform_layer/xizi/transform.c new file mode 100644 index 0000000..6d2e69d --- /dev/null +++ b/APP_Framework/Framework/transform_layer/xizi/transform.c @@ -0,0 +1,203 @@ +/* +* Copyright (c) 2020 AIIT XUOS Lab +* XiUOS is licensed under Mulan PSL v2. +* You can use this software according to the terms and conditions of the Mulan PSL v2. +* You may obtain a copy of Mulan PSL v2 at: +* http://license.coscl.org.cn/MulanPSL2 +* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, +* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, +* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. +* See the Mulan PSL v2 for more details. +*/ + +/** + * @file xiuos.c + * @brief Converts the framework interface to an operating system interface + * @version 1.0 + * @author AIIT XUOS Lab + * @date 2021.06.07 + */ + +#include + +/**************************mutex***************************/ +/* private mutex API */ +int PrivMutexCreate(pthread_mutex_t *p_mutex, const pthread_mutexattr_t *attr) +{ + return pthread_mutex_init(p_mutex, attr); +} + +int PrivMutexDelete(pthread_mutex_t *p_mutex) +{ + return pthread_mutex_destroy(p_mutex); +} + +int PrivMutexObtain(pthread_mutex_t *p_mutex) +{ + return pthread_mutex_lock(p_mutex); +} + +int PrivMutexAbandon(pthread_mutex_t *p_mutex) +{ + return pthread_mutex_unlock(p_mutex); +} + +/**********************semaphore****************************/ +int PrivSemaphoreCreate(sem_t *sem, int pshared, unsigned int value) +{ + return sem_init(sem, pshared, value); +} + +int PrivSemaphoreDelete(sem_t *sem) +{ + return sem_destroy(sem); +} + +int PrivSemaphoreObtainWait(sem_t *sem, const struct timespec *abstime) +{ + return sem_timedwait(sem, abstime); +} + +int PrivSemaphoreObtainNoWait(sem_t *sem) +{ + return sem_trywait(sem); +} + +int PrivSemaphoreAbandon(sem_t *sem) +{ + return sem_post(sem); +} + +/**************************task*************************/ +int PrivTaskCreate(pthread_t *thread, const pthread_attr_t *attr, + void *(*start_routine)(void *), void *arg) +{ + return pthread_create(thread, attr, start_routine, arg); +} + +int PrivTaskStartup(pthread_t *thread) +{ + return 0; +} +#ifdef SEPARATE_COMPILE +/* private API of xiuos to search the first user task in manage list */ +int PrivUserTaskSearch(void) +{ + return UserTaskSearch(); +} +#endif + +int PrivTaskDelete(pthread_t thread, int sig) +{ + return pthread_kill(thread, sig); +} + +void PrivTaskQuit(void *value_ptr) +{ + pthread_exit(value_ptr); +} + +int PrivTaskDelay(int32_t ms) +{ + UserTaskDelay(ms); +} + +uint32_t PrivGetTickTime() +{ + return CalculteTimeMsFromTick(CurrentTicksGain()); +} + +/*********************fs**************************/ +#ifdef FS_VFS +/************************Driver Posix Transform***********************/ +int PrivOpen(const char *path, int flags) +{ + return open(path, flags); +} + +int PrivClose(int fd) +{ + return close(fd); +} + +int PrivRead(int fd, void *buf, size_t len) +{ + return read(fd, buf, len); +} + +int PrivWrite(int fd, const void *buf, size_t len) +{ + return write(fd, buf, len); +} + +static int PrivSerialIoctl(int fd, int cmd, void *args) +{ + struct SerialDataCfg *serial_cfg = (struct SerialDataCfg *)args; + return ioctl(fd, cmd, serial_cfg); +} + +static int PrivPinIoctl(int fd, int cmd, void *args) +{ + struct PinParam *pin_cfg = (struct PinParam *)args; + + return ioctl(fd, cmd, pin_cfg); +} + +static int PrivLcdIoctl(int fd, int cmd, void *args) +{ + struct DeviceLcdInfo *lcd_cfg = (struct DeviceLcdInfo *)args; + + return ioctl(fd, cmd, lcd_cfg); +} + +int PrivIoctl(int fd, int cmd, void *args) +{ + int ret; + struct PrivIoctlCfg *ioctl_cfg = (struct PrivIoctlCfg *)args; + + switch (ioctl_cfg->ioctl_driver_type) + { + case SERIAL_TYPE: + ret = PrivSerialIoctl(fd, cmd, ioctl_cfg->args); + break; + case PIN_TYPE: + ret = PrivPinIoctl(fd, cmd, ioctl_cfg->args); + break; + case I2C_TYPE: + ret = ioctl(fd, cmd, ioctl_cfg->args); + break; + case LCD_TYPE: + ret = PrivLcdIoctl(fd, cmd, ioctl_cfg->args); + break; + case ADC_TYPE: + case DAC_TYPE: + ret = ioctl(fd, cmd, ioctl_cfg->args); + break; + default: + break; + } + + return ret; +} +#endif +/********************memory api************/ +void *PrivMalloc(size_t size) +{ + return UserMalloc(size); +} + +void *PrivRealloc(void *pointer, size_t size) +{ + return UserRealloc(pointer, size); +} + +void *PrivCalloc(size_t count, size_t size) +{ + return UserCalloc(count, size); +} + +void PrivFree(void *pointer) +{ + UserFree(pointer); +} + diff --git a/APP_Framework/Framework/transform_layer/xizi/transform.h b/APP_Framework/Framework/transform_layer/xizi/transform.h new file mode 100644 index 0000000..ae0d380 --- /dev/null +++ b/APP_Framework/Framework/transform_layer/xizi/transform.h @@ -0,0 +1,232 @@ +/* +* Copyright (c) 2020 AIIT XUOS Lab +* XiUOS is licensed under Mulan PSL v2. +* You can use this software according to the terms and conditions of the Mulan PSL v2. +* You may obtain a copy of Mulan PSL v2 at: +* http://license.coscl.org.cn/MulanPSL2 +* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, +* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, +* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. +* See the Mulan PSL v2 for more details. +*/ + +/** + * @file transform.h + * @brief Interface function declarations required by the framework + * @version 1.0 + * @author AIIT XUOS Lab + * @date 2021.06.04 + */ + +#ifndef TRANSFORM_H +#define TRANSFORM_H + +#include +#include +#include +#include +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +#define OPE_INT 0x0000 +#define OPE_CFG 0x0001 + +#define NAME_NUM_MAX 32 + +/*********************GPIO define*********************/ +#define GPIO_LOW 0x00 +#define GPIO_HIGH 0x01 + +#define GPIO_CFG_OUTPUT 0x00 +#define GPIO_CFG_INPUT 0x01 +#define GPIO_CFG_INPUT_PULLUP 0x02 +#define GPIO_CFG_INPUT_PULLDOWN 0x03 +#define GPIO_CFG_OUTPUT_OD 0x04 + +#define GPIO_CONFIG_MODE 0xffffffff + +/********************SERIAL define*******************/ +#define BAUD_RATE_2400 2400 +#define BAUD_RATE_4800 4800 +#define BAUD_RATE_9600 9600 +#define BAUD_RATE_19200 19200 +#define BAUD_RATE_38400 38400 +#define BAUD_RATE_57600 57600 +#define BAUD_RATE_115200 115200 +#define BAUD_RATE_230400 230400 +#define BAUD_RATE_460800 460800 +#define BAUD_RATE_921600 921600 +#define BAUD_RATE_2000000 2000000 +#define BAUD_RATE_3000000 3000000 + +#define DATA_BITS_5 5 +#define DATA_BITS_6 6 +#define DATA_BITS_7 7 +#define DATA_BITS_8 8 +#define DATA_BITS_9 9 + +#define STOP_BITS_1 1 +#define STOP_BITS_2 2 +#define STOP_BITS_3 3 +#define STOP_BITS_4 4 + +#define PARITY_NONE 1 +#define PARITY_ODD 2 +#define PARITY_EVEN 3 + +#define BIT_ORDER_LSB 1 +#define BIT_ORDER_MSB 2 + +#define NRZ_NORMAL 1 +#define NRZ_INVERTED 2 + +#ifndef SERIAL_RB_BUFSZ +#define SERIAL_RB_BUFSZ 128 +#endif + +struct PinDevIrq +{ + int irq_mode;//< RISING/FALLING/HIGH/LOW + void (*hdr) (void *args);//< callback function + void *args;//< the params of callback function +}; + +struct PinParam +{ + int cmd;//< cmd:GPIO_CONFIG_MODE/GPIO_IRQ_REGISTER/GPIO_IRQ_FREE/GPIO_IRQ_DISABLE/GPIO_IRQ_ENABLE + long pin;//< pin number + int mode;//< pin mode: input/output + struct PinDevIrq irq_set;//< pin irq set + uint64_t arg; +}; + +struct PinStat +{ + long pin;//< pin number + uint16_t val;//< pin level +}; + +enum ExtSerialPortConfigure +{ + PORT_CFG_INIT = 0, + PORT_CFG_PARITY_CHECK, + PORT_CFG_DISABLE, + PORT_CFG_DIV, +}; + +struct SerialDataCfg +{ + uint32_t serial_baud_rate; + uint8_t serial_data_bits; + uint8_t serial_stop_bits; + uint8_t serial_parity_mode; + uint8_t serial_bit_order; + uint8_t serial_invert_mode; + uint16_t serial_buffer_size; + + uint8_t ext_uart_no; + enum ExtSerialPortConfigure port_configure; +}; + +enum IoctlDriverType +{ + SERIAL_TYPE = 0, + SPI_TYPE, + I2C_TYPE, + PIN_TYPE, + LCD_TYPE, + ADC_TYPE, + DAC_TYPE, + DEFAULT_TYPE, +}; + +struct PrivIoctlCfg +{ + enum IoctlDriverType ioctl_driver_type; + void *args; +}; + +typedef struct +{ + uint16 x_pos; + uint16 y_pos; + uint16 width; + uint16 height; + uint8 font_size; + uint8 *addr; + uint16 font_color; + uint16 back_color; +}LcdStringParam; + +typedef struct +{ + uint16 x_startpos; + uint16 x_endpos; + uint16 y_startpos; + uint16 y_endpos; + void* pixel_color; +}LcdPixelParam; + +typedef struct +{ + char type; // 0:write string;1:write dot + LcdPixelParam pixel_info; + LcdStringParam string_info; +}LcdWriteParam; + +#define PRIV_SYSTICK_GET (CurrentTicksGain()) +#define PRIV_LCD_DEV "/dev/lcd_dev" +#define MY_DISP_HOR_RES BSP_LCD_Y_MAX +#define MY_DISP_VER_RES BSP_LCD_X_MAX +/**********************mutex**************************/ + +int PrivMutexCreate(pthread_mutex_t *p_mutex, const pthread_mutexattr_t *attr); +int PrivMutexDelete(pthread_mutex_t *p_mutex); +int PrivMutexObtain(pthread_mutex_t *p_mutex); +int PrivMutexAbandon(pthread_mutex_t *p_mutex); + +/*********************semaphore**********************/ + +int PrivSemaphoreCreate(sem_t *sem, int pshared, unsigned int value); +int PrivSemaphoreDelete(sem_t *sem); +int PrivSemaphoreObtainWait(sem_t *sem, const struct timespec *abstime); +int PrivSemaphoreObtainNoWait(sem_t *sem); +int PrivSemaphoreAbandon(sem_t *sem); +int32_t PrivSemaphoreSetValue(int32_t sem, uint16_t val); + +/*********************task**************************/ + +int PrivTaskCreate(pthread_t *thread, const pthread_attr_t *attr, + void *(*start_routine)(void *), void *arg); +int PrivTaskStartup(pthread_t *thread); +int PrivTaskDelete(pthread_t thread, int sig); +void PrivTaskQuit(void *value_ptr); +int PrivTaskDelay(int32_t ms); +int PrivUserTaskSearch(void); +uint32_t PrivGetTickTime(); + +/*********************driver*************************/ + +int PrivOpen(const char *path, int flags); +int PrivRead(int fd, void *buf, size_t len); +int PrivWrite(int fd, const void *buf, size_t len); +int PrivClose(int fd); +int PrivIoctl(int fd, int cmd, void *args); + +/*********************memory***********************/ + +void *PrivMalloc(size_t size); +void *PrivRealloc(void *pointer, size_t size); +void *PrivCalloc(size_t count, size_t size); +void PrivFree(void *pointer); + + +#ifdef __cplusplus +} +#endif + +#endif \ No newline at end of file diff --git a/APP_Framework/Framework/transform_layer/xizi/user_api/Makefile b/APP_Framework/Framework/transform_layer/xizi/user_api/Makefile new file mode 100644 index 0000000..f95a320 --- /dev/null +++ b/APP_Framework/Framework/transform_layer/xizi/user_api/Makefile @@ -0,0 +1,7 @@ +SRC_DIR := posix_support + +ifeq ($(CONFIG_SEPARATE_COMPILE),y) + SRC_DIR += switch_api +endif + +include $(KERNEL_ROOT)/compiler.mk \ No newline at end of file diff --git a/APP_Framework/Framework/transform_layer/xizi/user_api/include/bus.h b/APP_Framework/Framework/transform_layer/xizi/user_api/include/bus.h new file mode 100644 index 0000000..57769b5 --- /dev/null +++ b/APP_Framework/Framework/transform_layer/xizi/user_api/include/bus.h @@ -0,0 +1,35 @@ +/* +* Copyright (c) 2020 AIIT XUOS Lab +* XiUOS is licensed under Mulan PSL v2. +* You can use this software according to the terms and conditions of the Mulan PSL v2. +* You may obtain a copy of Mulan PSL v2 at: +* http://license.coscl.org.cn/MulanPSL2 +* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, +* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, +* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. +* See the Mulan PSL v2 for more details. +*/ + +/** +* @file bus.h +* @brief define bus driver framework function and common API +* @version 1.0 +* @author AIIT XUOS Lab +* @date 2021-04-24 +*/ + +#ifndef BUS_H +#define BUS_H + +#ifdef __cplusplus +extern "C" { +#endif + +#define OPE_INT 0x0000 +#define OPE_CFG 0x0001 + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/APP_Framework/Framework/transform_layer/xizi/user_api/include/bus_serial.h b/APP_Framework/Framework/transform_layer/xizi/user_api/include/bus_serial.h new file mode 100644 index 0000000..138fcf9 --- /dev/null +++ b/APP_Framework/Framework/transform_layer/xizi/user_api/include/bus_serial.h @@ -0,0 +1,67 @@ +/* +* Copyright (c) 2020 AIIT XUOS Lab +* XiUOS is licensed under Mulan PSL v2. +* You can use this software according to the terms and conditions of the Mulan PSL v2. +* You may obtain a copy of Mulan PSL v2 at: +* http://license.coscl.org.cn/MulanPSL2 +* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, +* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, +* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. +* See the Mulan PSL v2 for more details. +*/ + +/** +* @file bus_serial.h +* @brief define serial bus and drv function using bus driver framework +* @version 1.0 +* @author AIIT XUOS Lab +* @date +*/ + +#ifndef BUS_SERIAL_H +#define BUS_SERIAL_H + +#include +#ifdef __cplusplus +extern "C" { +#endif + +enum ExtSerialPortConfigure +{ + PORT_CFG_INIT = 0, + PORT_CFG_PARITY_CHECK, + PORT_CFG_DISABLE, + PORT_CFG_DIV, +}; + +struct SerialDataCfg +{ + uint32 serial_baud_rate; + uint8 serial_data_bits; + uint8 serial_stop_bits; + uint8 serial_parity_mode; + uint8 serial_bit_order; + uint8 serial_invert_mode; + uint16 serial_buffer_size; + + uint8 ext_uart_no; + enum ExtSerialPortConfigure port_configure; +}; + +struct SerialHwCfg +{ + uint32 serial_register_base; + uint32 serial_irq_interrupt; + void *private_data; +}; + +struct SerialCfgParam +{ + struct SerialDataCfg data_cfg; + struct SerialHwCfg hw_cfg; +}; +#ifdef __cplusplus +} +#endif + +#endif diff --git a/APP_Framework/Framework/transform_layer/xizi/user_api/include/dev_serial.h b/APP_Framework/Framework/transform_layer/xizi/user_api/include/dev_serial.h new file mode 100644 index 0000000..8fbd341 --- /dev/null +++ b/APP_Framework/Framework/transform_layer/xizi/user_api/include/dev_serial.h @@ -0,0 +1,70 @@ +/* +* Copyright (c) 2020 AIIT XUOS Lab +* XiUOS is licensed under Mulan PSL v2. +* You can use this software according to the terms and conditions of the Mulan PSL v2. +* You may obtain a copy of Mulan PSL v2 at: +* http://license.coscl.org.cn/MulanPSL2 +* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, +* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, +* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. +* See the Mulan PSL v2 for more details. +*/ + +/** +* @file dev_serial.h +* @brief define serial dev function using bus driver framework +* @version 1.0 +* @author AIIT XUOS Lab +* @date +*/ + +#ifndef DEV_SERIAL_H +#define DEV_SERIAL_H + +#ifdef __cplusplus +extern "C" { +#endif + +#define BAUD_RATE_2400 2400 +#define BAUD_RATE_4800 4800 +#define BAUD_RATE_9600 9600 +#define BAUD_RATE_19200 19200 +#define BAUD_RATE_38400 38400 +#define BAUD_RATE_57600 57600 +#define BAUD_RATE_115200 115200 +#define BAUD_RATE_230400 230400 +#define BAUD_RATE_460800 460800 +#define BAUD_RATE_921600 921600 +#define BAUD_RATE_2000000 2000000 +#define BAUD_RATE_3000000 3000000 + +#define DATA_BITS_5 5 +#define DATA_BITS_6 6 +#define DATA_BITS_7 7 +#define DATA_BITS_8 8 +#define DATA_BITS_9 9 + +#define STOP_BITS_1 1 +#define STOP_BITS_2 2 +#define STOP_BITS_3 3 +#define STOP_BITS_4 4 + +#define PARITY_NONE 1 +#define PARITY_ODD 2 +#define PARITY_EVEN 3 + +#define BIT_ORDER_LSB 1 +#define BIT_ORDER_MSB 2 + +#define NRZ_NORMAL 1 +#define NRZ_INVERTED 2 + +#ifndef SERIAL_RB_BUFSZ +#define SERIAL_RB_BUFSZ 128 +#endif + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/APP_Framework/Framework/transform_layer/xizi/user_api/posix_support/Makefile b/APP_Framework/Framework/transform_layer/xizi/user_api/posix_support/Makefile new file mode 100644 index 0000000..abdf776 --- /dev/null +++ b/APP_Framework/Framework/transform_layer/xizi/user_api/posix_support/Makefile @@ -0,0 +1,14 @@ +SRC_FILES := pthread.c +ifeq ($(CONFIG_KERNEL_SEMAPHORE),y) + SRC_FILES += semaphore.c +endif + +ifeq ($(CONFIG_KERNEL_MUTEX),y) + SRC_FILES += pthread_mutex.c +endif + +ifeq ($(CONFIG_KERNEL_MESSAGEQUEUE),y) + SRC_FILES += mqueue.c +endif + +include $(KERNEL_ROOT)/compiler.mk \ No newline at end of file diff --git a/APP_Framework/Framework/transform_layer/xizi/user_api/posix_support/include/fs.h b/APP_Framework/Framework/transform_layer/xizi/user_api/posix_support/include/fs.h new file mode 100644 index 0000000..f0fb8d2 --- /dev/null +++ b/APP_Framework/Framework/transform_layer/xizi/user_api/posix_support/include/fs.h @@ -0,0 +1,55 @@ +/* + * Copyright (c) 2020 AIIT XUOS Lab + * XiUOS is licensed under Mulan PSL v2. + * You can use this software according to the terms and conditions of the Mulan PSL v2. + * You may obtain a copy of Mulan PSL v2 at: + * http://license.coscl.org.cn/MulanPSL2 + * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, + * EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, + * MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. + * See the Mulan PSL v2 for more details. + */ + +/** +* @file: fs.h +* @brief: the macor definition of posix fs +* @version: 1.0 +* @author: AIIT XUOS Lab +* @date: 2020/4/20 +* +*/ + +#ifndef POSIX_FS_H +#define POSIX_FS_H + +// #include "../../switch_api/user_api.h" + +// #define open UserOpen +// #define read UserRead +// #define write UserWrite +// #define close UserClose +// #define lseek UserLseek +// #define rename UserRename +// #define unlink UserUnlink +// #define stat UserStat +// #define fstat UserFstat +// #define fsync UserFsync +// #define ftruncate UserFtruncate +// #define mkdir UserMkdir +// #define opendir UserOpendir +// #define closedir UserClosedir +// #define readdir UserReaddir +// #define rmdir UserRmdir +// #define chdir UserChdir +// #define getcwd UserGetcwd +// #define telldir UserTelldir +// #define seekdir UserSeekdir +// #define rewinddir UserRewinddir +// #define printf UserPrintf + +// #ifdef FS_DFS +// #define statfs UserStatfs +// #endif + +#endif + diff --git a/APP_Framework/Framework/transform_layer/xizi/user_api/posix_support/include/mqueue.h b/APP_Framework/Framework/transform_layer/xizi/user_api/posix_support/include/mqueue.h new file mode 100644 index 0000000..ae13f66 --- /dev/null +++ b/APP_Framework/Framework/transform_layer/xizi/user_api/posix_support/include/mqueue.h @@ -0,0 +1,57 @@ +/* + * Copyright (c) 2020 AIIT XUOS Lab + * XiUOS is licensed under Mulan PSL v2. + * You can use this software according to the terms and conditions of the Mulan PSL v2. + * You may obtain a copy of Mulan PSL v2 at: + * http://license.coscl.org.cn/MulanPSL2 + * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, + * EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, + * MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. + * See the Mulan PSL v2 for more details. + */ + +/** +* @file: msgqueue.h +* @brief: the function definition of posix msg queue +* @version: 1.0 +* @author: AIIT XUOS Lab +* @date: 2020/4/20 +* +*/ + +#ifndef MQUEUE_H +#define MQUEUE_H + +#ifdef __cplusplus +extern "C" { +#endif +#include "../../switch_api/user_api.h" +#include + +#define DEFAULT_MQUEUE_SIZE (10 * 1024) +#define DEFAULT_MAX_MSG_SIZE (1024) + +typedef int mqd_t; + +struct mq_attr { + long mq_flags; /* message queue flags */ + long mq_maxmsg; /* maximum number of messages */ + long mq_msgsize; /* maximum message size */ + long mq_curmsgs; /* number of messages currently queued */ +}; + +mqd_t mq_open(const char *name, int oflag, ...); +int mq_close(mqd_t mqdes); +ssize_t mq_receive(mqd_t mqdes, char *msg_ptr, size_t msg_len, unsigned *msg_prio); +int mq_send(mqd_t mqdes, const char *msg_ptr, size_t msg_len, unsigned msg_prio); +int mq_setattr(mqd_t mqdes, const struct mq_attr *mqstat, struct mq_attr *omqstat); +int mq_getattr(mqd_t mqdes, struct mq_attr *mqstat); +ssize_t mq_timedreceive(mqd_t mqdes, char *msg_ptr, size_t msg_len, unsigned *msg_prio, const struct timespec *abs_timeout); +int mq_timedsend(mqd_t mqdes, const char *msg_ptr, size_t msg_len, unsigned msg_prio, const struct timespec *abs_timeout); +int mq_unlink(const char *name); + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif diff --git a/APP_Framework/Framework/transform_layer/xizi/user_api/posix_support/include/pthread arm.h b/APP_Framework/Framework/transform_layer/xizi/user_api/posix_support/include/pthread arm.h new file mode 100644 index 0000000..c5b23a0 --- /dev/null +++ b/APP_Framework/Framework/transform_layer/xizi/user_api/posix_support/include/pthread arm.h @@ -0,0 +1,67 @@ +/* + * Copyright (c) 2020 AIIT XUOS Lab + * XiUOS is licensed under Mulan PSL v2. + * You can use this software according to the terms and conditions of the Mulan PSL v2. + * You may obtain a copy of Mulan PSL v2 at: + * http://license.coscl.org.cn/MulanPSL2 + * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, + * EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, + * MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. + * See the Mulan PSL v2 for more details. + */ + +/** +* @file: pthread_arm.h +* @brief: the attribute definition of posix pthread for arm +* @version: 1.0 +* @author: AIIT XUOS Lab +* @date: 2020/4/20 +* +*/ + +#ifndef PTHREAD_ARM_H +#define PTHREAD_ARM_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +typedef int pid_t; +typedef unsigned long int pthread_t; + +struct sched_param { + int sched_priority; /* process execution scheduling priority */ + size_t slice; /* time slice in SCHED_RR mode (ms) */ +}; +typedef struct pthread_attr { + unsigned char is_initialized; /* if the attr is initialized set to 1, otherwise set to 0 */ + void *stackaddr; /* the start addr of the stack of the pthead */ + size_t stacksize; /* the size of the stack of the pthead */ + unsigned char contentionscope; /* the scope of contention, only PTHREAD_SCOPE_SYSTEM is supported */ + unsigned char inheritsched; /* when set to PTHREAD_INHERIT_SCHED, specifies that the thread scheduling attributes + shall be inherited from the creating thread, and the scheduling attributes in this + attr argument shall be ignored */ + unsigned char schedpolicy; /* the sched policy of the thread */ + struct sched_param schedparam; /* the parameter of the thread scheduling */ + size_t guardsize; /* guardsize is set to protect the stack, not supported */ + unsigned char detachstate; /* when set to PTHREAD_CREATE_JOINABLE, thread will not end untill the creating thread end */ +} pthread_attr_t; + +typedef struct pthread_mutexattr { + int is_initialized; + int type; + int protocol; + int prioceiling; + int pshared; +} pthread_mutexattr_t; + +typedef int pthread_mutex_t ; + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* PTHREAD_H */ \ No newline at end of file diff --git a/APP_Framework/Framework/transform_layer/xizi/user_api/posix_support/include/pthread.h b/APP_Framework/Framework/transform_layer/xizi/user_api/posix_support/include/pthread.h new file mode 100644 index 0000000..9f65a97 --- /dev/null +++ b/APP_Framework/Framework/transform_layer/xizi/user_api/posix_support/include/pthread.h @@ -0,0 +1,108 @@ +/* + * Copyright (c) 2020 AIIT XUOS Lab + * XiUOS is licensed under Mulan PSL v2. + * You can use this software according to the terms and conditions of the Mulan PSL v2. + * You may obtain a copy of Mulan PSL v2 at: + * http://license.coscl.org.cn/MulanPSL2 + * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, + * EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, + * MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. + * See the Mulan PSL v2 for more details. + */ + +/** +* @file: pthread.h +* @brief: the attribute definition of posix pthread +* @version: 1.0 +* @author: AIIT XUOS Lab +* @date: 2020/4/20 +* +*/ + +#ifndef PTHREAD_H +#define PTHREAD_H + +#ifdef __cplusplus +extern "C" { +#endif +#include "../../switch_api/user_api.h" +#include +#include + +#if defined(ARCH_ARM) +#include "pthread arm.h" +#endif + +// enum { +// PTHREAD_BARRIER_SERIAL_THREAD, +// PTHREAD_CANCEL_ASYNCHRONOUS, +// PTHREAD_CANCEL_ENABLE, +// PTHREAD_CANCEL_DEFERRED, +// PTHREAD_CANCEL_DISABLE, +// PTHREAD_CANCELED, +// PTHREAD_CREATE_DETACHED, +// PTHREAD_CREATE_JOINABLE, +// PTHREAD_EXPLICIT_SCHED, +// PTHREAD_INHERIT_SCHED, +// PTHREAD_MUTEX_DEFAULT, +// PTHREAD_MUTEX_ERRORCHECK, +// PTHREAD_MUTEX_NORMAL, +// PTHREAD_MUTEX_RECURSIVE, +// PTHREAD_MUTEX_ROBUST, +// PTHREAD_MUTEX_STALLED, +// PTHREAD_ONCE_INIT, +// PTHREAD_PRIO_INHERIT, +// PTHREAD_PRIO_NONE, +// PTHREAD_PRIO_PROTECT, +// PTHREAD_PROCESS_SHARED, +// PTHREAD_PROCESS_PRIVATE, +// PTHREAD_SCOPE_PROCESS, +// PTHREAD_SCOPE_SYSTEM, +// }; + +typedef int pid_t; +// typedef int pthread_mutex_t ; + +/* function in pthread.c */ +int pthread_atfork(void (*prepare)(void), void (*parent)(void), void (*child)(void)); +int pthread_create(pthread_t *thread, const pthread_attr_t *attr, + void *(*start_routine)(void *), void *arg); +void pthread_exit(void *value_ptr); +int pthread_detach(pthread_t thread); +int pthread_join(pthread_t thread, void **retval); +int pthread_cancel(pthread_t thread); +void pthread_testcancel(void); +int pthread_setcancelstate(int state, int *oldstate); +int pthread_setcanceltype(int type, int *oldtype); +int pthread_kill(pthread_t thread, int sig); +int pthread_equal(pthread_t t1, pthread_t t2); +int pthread_setschedparam(pthread_t thread, int policy, const struct sched_param *pParam); +void pthread_cleanup_pop(int execute); +void pthread_cleanup_push(void (*routine)(void *), void *arg); +pthread_t pthread_self(void); +int pthread_getcpuclockid(pthread_t thread_id, clockid_t *clock_id); +int pthread_setconcurrency(int new_level); +int pthread_getconcurrency(void); +int pthread_setschedprio(pthread_t thread, int prio); +int pthread_setname_np(pthread_t thread, const char *name); +int pthread_timedjoin_np(pthread_t thread, void **retval, const struct timespec *abstime); + +/* function in pthread_mutex.c */ +int pthread_mutex_init(pthread_mutex_t *mutex, const pthread_mutexattr_t *attr); +int pthread_mutex_destroy(pthread_mutex_t *mutex); +int pthread_mutex_lock(pthread_mutex_t *mutex); +int pthread_mutex_unlock(pthread_mutex_t *mutex); +int pthread_mutex_trylock(pthread_mutex_t *mutex); + +int pthread_mutexattr_init(pthread_mutexattr_t *attr); +int pthread_mutexattr_destroy(pthread_mutexattr_t *attr); +int pthread_mutexattr_gettype(const pthread_mutexattr_t *attr, int *type); +int pthread_mutexattr_settype(pthread_mutexattr_t *attr, int type); +int pthread_mutexattr_setpshared(pthread_mutexattr_t *attr, int pshared); +int pthread_mutexattr_getpshared(pthread_mutexattr_t *attr, int *pshared); + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif \ No newline at end of file diff --git a/APP_Framework/Framework/transform_layer/xizi/user_api/posix_support/include/semaphore.h b/APP_Framework/Framework/transform_layer/xizi/user_api/posix_support/include/semaphore.h new file mode 100644 index 0000000..6bd096b --- /dev/null +++ b/APP_Framework/Framework/transform_layer/xizi/user_api/posix_support/include/semaphore.h @@ -0,0 +1,49 @@ +/* + * Copyright (c) 2020 AIIT XUOS Lab + * XiUOS is licensed under Mulan PSL v2. + * You can use this software according to the terms and conditions of the Mulan PSL v2. + * You may obtain a copy of Mulan PSL v2 at: + * http://license.coscl.org.cn/MulanPSL2 + * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, + * EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, + * MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. + * See the Mulan PSL v2 for more details. + */ + +/** +* @file: semaphore.h +* @brief: the functions definition of posix semaphore +* @version: 1.0 +* @author: AIIT XUOS Lab +* @date: 2020/4/20 +* +*/ + +#ifndef SEMAPHORE_H +#define SEMAPHORE_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include "../../switch_api/user_api.h" +#include + +typedef int sem_t; + +int sem_init(sem_t *sem, int pshared, unsigned int value); +sem_t *sem_open(const char *name, int oflag, ...); +int sem_post(sem_t *sem); +int sem_timedwait(sem_t *sem, const struct timespec *abs_timeout); +int sem_trywait(sem_t *sem); +int sem_unlink(const char *name); +int sem_wait(sem_t *sem); +int sem_getvalue(sem_t *sem, int *sval); +int sem_close(sem_t *sem); +int sem_destroy(sem_t *sem); + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* SEMAPHORE_H */ \ No newline at end of file diff --git a/APP_Framework/Framework/transform_layer/xizi/user_api/posix_support/mqueue.c b/APP_Framework/Framework/transform_layer/xizi/user_api/posix_support/mqueue.c new file mode 100644 index 0000000..e0f5e95 --- /dev/null +++ b/APP_Framework/Framework/transform_layer/xizi/user_api/posix_support/mqueue.c @@ -0,0 +1,94 @@ +/* + * Copyright (c) 2020 AIIT XUOS Lab + * XiUOS is licensed under Mulan PSL v2. + * You can use this software according to the terms and conditions of the Mulan PSL v2. + * You may obtain a copy of Mulan PSL v2 at: + * http://license.coscl.org.cn/MulanPSL2 + * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, + * EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, + * MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. + * See the Mulan PSL v2 for more details. + */ + +/** +* @file: mqueue.c +* @brief: posix api of mqueue +* @version: 1.0 +* @author: AIIT XUOS Lab +* @date: 2020/4/20 +* +*/ + +#include "include/mqueue.h" + +mqd_t mq_open(const char *name, int oflag, ...) +{ + + mqd_t mq; + + mq = UserMsgQueueCreate( DEFAULT_MQUEUE_SIZE, DEFAULT_MAX_MSG_SIZE); + if (mq < 0) { + return -1; + } + + return mq; +} + +int mq_close(mqd_t mqdes) +{ + return UserMsgQueueDelete(mqdes); +} + +ssize_t mq_receive(mqd_t mqdes, char *msg_ptr, size_t msg_len, unsigned *msg_prio) +{ + ssize_t ret; + + *msg_prio = 0; + ret = UserMsgQueueRecv(mqdes, msg_ptr, (unsigned long)&msg_len, 0); + + return ret; +} + +int mq_send(mqd_t mqdes, const char *msg_ptr, size_t msg_len, unsigned msg_prio) +{ + int ret; + ret = UserMsgQueueSend(mqdes, (void *)msg_ptr, msg_len); + return ret; +} + +int mq_setattr(mqd_t mqdes, const struct mq_attr *mqstat, struct mq_attr *omqstat) +{ + return 0; +} + +int mq_getattr(mqd_t mqdes, struct mq_attr *mqstat) +{ + return 0; +} + +ssize_t mq_timedreceive(mqd_t mqdes, char *msg_ptr, size_t msg_len, + unsigned *msg_prio, const struct timespec *abstime) +{ + ssize_t ret; + int ticks; + + *msg_prio = 0; + ticks = abstime->tv_sec * 1000 + + (abstime->tv_nsec / 1000000 ) ; + + ret = UserMsgQueueRecv(mqdes, msg_ptr, msg_len, ticks); + return ret; +} + +int mq_timedsend(mqd_t mqdes, const char *msg_ptr, size_t msg_len, + unsigned msg_prio, const struct timespec *abstime) +{ + int ret; + int ticks; + ticks = abstime->tv_sec * 1000 + + (abstime->tv_nsec / 1000000 ) ; + + ret = UserMsgQueueSendwait(mqdes, (void *)msg_ptr, msg_len, ticks); + + return ret; +} \ No newline at end of file diff --git a/APP_Framework/Framework/transform_layer/xizi/user_api/posix_support/pthread.c b/APP_Framework/Framework/transform_layer/xizi/user_api/posix_support/pthread.c new file mode 100644 index 0000000..7d1cef9 --- /dev/null +++ b/APP_Framework/Framework/transform_layer/xizi/user_api/posix_support/pthread.c @@ -0,0 +1,108 @@ +/* + * Copyright (c) 2020 AIIT XUOS Lab + * XiUOS is licensed under Mulan PSL v2. + * You can use this software according to the terms and conditions of the Mulan PSL v2. + * You may obtain a copy of Mulan PSL v2 at: + * http://license.coscl.org.cn/MulanPSL2 + * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, + * EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, + * MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. + * See the Mulan PSL v2 for more details. + */ + +/** +* @file: pthread.c +* @brief: posix api of pthread +* @version: 1.0 +* @author: AIIT XUOS Lab +* @date: 2020/4/20 +* +*/ +#include +#include +#include "include/pthread.h" + +int pthread_create(pthread_t *thread, const pthread_attr_t *attr, + void *(*start_routine)(void *), void *arg) +{ + int ret ; + int pid ; + char task_name[32] = {0}; + static int utask_id = 0; + UtaskType task ; + + if (NULL == attr) { + task.prio = KTASK_PRIORITY_MAX / 2; + task.stack_size = 1024 ; + } else { + task.prio = attr->schedparam.sched_priority ; + task.stack_size = attr->stacksize ; + } + + task.func_entry = start_routine ; + task.func_param = arg; + snprintf(task_name, sizeof(task_name) - 1, "utask%02d",utask_id++); + memcpy(task.name , task_name, sizeof(task_name) - 1); + + pid = UserTaskCreate(task); + if (pid < 0) + return -1 ; + + ret = UserTaskStartup(pid); + *thread = pid; + + return ret; + +} + +void pthread_exit(void *value_ptr){ + //todo add exit value + UserTaskQuit(); +} + +pthread_t pthread_self(void){ + + pthread_t pthread ; + pthread = UserGetTaskID(); + return pthread; +} + +int pthread_setschedprio(pthread_t thread, int prio) +{ + //add syscall + return 0; +} + +int pthread_equal(pthread_t t1, pthread_t t2) +{ + return (int)(t1 == t2); +} + +int pthread_cancel(pthread_t thread) +{ + return -1; +} + +void pthread_testcancel(void) +{ + return; +} + +int pthread_setcancelstate(int state, int *oldstate) +{ + return -1; +} + +int pthread_setcanceltype(int type, int *oldtype) +{ + return -1; +} + +int pthread_kill(pthread_t thread, int sig) +{ + /* This api should not be used, and will not be supported */ + UserTaskDelete(thread); + return -1; +} + + diff --git a/APP_Framework/Framework/transform_layer/xizi/user_api/posix_support/pthread_mutex.c b/APP_Framework/Framework/transform_layer/xizi/user_api/posix_support/pthread_mutex.c new file mode 100644 index 0000000..6237a55 --- /dev/null +++ b/APP_Framework/Framework/transform_layer/xizi/user_api/posix_support/pthread_mutex.c @@ -0,0 +1,125 @@ +/* + * Copyright (c) 2020 AIIT XUOS Lab + * XiUOS is licensed under Mulan PSL v2. + * You can use this software according to the terms and conditions of the Mulan PSL v2. + * You may obtain a copy of Mulan PSL v2 at: + * http://license.coscl.org.cn/MulanPSL2 + * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, + * EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, + * MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. + * See the Mulan PSL v2 for more details. + */ + +/** +* @file: pthread_mutex.c +* @brief: posix api of mutex +* @version: 1.0 +* @author: AIIT XUOS Lab +* @date: 2020/4/20 +* +*/ + +#include +#include "include/pthread.h" + +int pthread_mutex_init(pthread_mutex_t *p_mutex, const pthread_mutexattr_t *attr) +{ + *p_mutex = UserMutexCreate(); + if (*p_mutex < 0) { + return -1; + } + return 0; +} + +int pthread_mutex_destroy(pthread_mutex_t *p_mutex) +{ + UserMutexDelete(*p_mutex); + return 0; +} + +int pthread_mutex_lock(pthread_mutex_t *p_mutex) +{ + int ret = -1; + + + ret = UserMutexObtain(*p_mutex, WAITING_FOREVER); + + return ret; +} + +int pthread_mutex_unlock(pthread_mutex_t *p_mutex) +{ + int ret = -1; + + ret = UserMutexAbandon( *p_mutex ); + return ret; +} + +int pthread_mutex_trylock(pthread_mutex_t *p_mutex) +{ + int ret = -1; + ret = UserMutexObtain( *p_mutex , 0); + return ret; +} + +int pthread_mutexattr_init(pthread_mutexattr_t *attr) +{ + return 0; +} + +int pthread_mutexattr_destroy(pthread_mutexattr_t *attr) +{ + return 0; +} + +int pthread_mutexattr_gettype(const pthread_mutexattr_t *attr, int *type) +{ + return 0; +} + +int pthread_mutexattr_settype(pthread_mutexattr_t *attr, int type) +{ + return 0; +} + +int pthread_mutexattr_getprotocol(const pthread_mutexattr_t *restrict attr, int *restrict protocol) +{ + + return 0; +} + +int pthread_mutexattr_setprotocol(pthread_mutexattr_t *attr, int protocol) +{ + return 0; +} + +int pthread_mutex_getprioceiling(const pthread_mutex_t *restrict mutex, int *restrict prioceiling) +{ + return 0; +} + +int pthread_mutex_setprioceiling(pthread_mutex_t *restrict mutex, int prioceiling, int *restrict old_ceiling) +{ + return 0; +} + +int pthread_mutexattr_getprioceiling(const pthread_mutexattr_t *restrict attr, int *restrict prioceiling) +{ + return 0; +} + +int pthread_mutexattr_setprioceiling(pthread_mutexattr_t *attr, int prioceiling) +{ + return 0; +} + +int pthread_mutexattr_setpshared(pthread_mutexattr_t *attr, int pshared) +{ + return 0; +} + +int pthread_mutexattr_getpshared(pthread_mutexattr_t *attr, int *pshared) +{ + return 0; +} + diff --git a/APP_Framework/Framework/transform_layer/xizi/user_api/posix_support/semaphore.c b/APP_Framework/Framework/transform_layer/xizi/user_api/posix_support/semaphore.c new file mode 100644 index 0000000..2397704 --- /dev/null +++ b/APP_Framework/Framework/transform_layer/xizi/user_api/posix_support/semaphore.c @@ -0,0 +1,96 @@ +/* + * Copyright (c) 2020 AIIT XUOS Lab + * XiUOS is licensed under Mulan PSL v2. + * You can use this software according to the terms and conditions of the Mulan PSL v2. + * You may obtain a copy of Mulan PSL v2 at: + * http://license.coscl.org.cn/MulanPSL2 + * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, + * EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, + * MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. + * See the Mulan PSL v2 for more details. + */ + +/** +* @file: semaphore.c +* @brief: posix api of semphore +* @version: 1.0 +* @author: AIIT XUOS Lab +* @date: 2020/4/20 +* +*/ + +#include "include/semaphore.h" +#include + +int sem_init(sem_t *sem, int pshared, unsigned int value) +{ + *sem = UserSemaphoreCreate(value); + if (*sem < 0) { + return -1; + } + + return 0; +} + +sem_t *sem_open(const char *name, int oflag, ...) +{ + return 0; +} + +int sem_post(sem_t *sem) +{ + int ret; + + ret = UserSemaphoreAbandon(*sem); + return ret; +} + +int sem_timedwait(sem_t *sem, const struct timespec *abstime) +{ + int ret ; + int ticks = -1 ; + + if (abstime != NULL) { + ticks = abstime->tv_sec * 1000 + + (abstime->tv_nsec / 1000000 ) ; + } + + ret = UserSemaphoreObtain(*sem, ticks); + return ret; +} + +int sem_trywait(sem_t *sem) +{ + int ret ; + ret = UserSemaphoreObtain(*sem, 0); + return ret; +} + +int sem_unlink(const char *name) +{ + return 0; +} + +int sem_wait(sem_t *sem) +{ + int ret ; + ret = UserSemaphoreObtain(*sem, -1); + return ret; +} + +int sem_getvalue(sem_t *sem, int *sval) +{ + return 0; +} + +int sem_close(sem_t *sem) +{ + return 0; +} + +int sem_destroy(sem_t *sem) +{ + UserSemaphoreDelete(*sem); + return 0; +} + diff --git a/APP_Framework/Framework/transform_layer/xizi/user_api/switch_api/Makefile b/APP_Framework/Framework/transform_layer/xizi/user_api/switch_api/Makefile new file mode 100644 index 0000000..02b6b0c --- /dev/null +++ b/APP_Framework/Framework/transform_layer/xizi/user_api/switch_api/Makefile @@ -0,0 +1,27 @@ +ifeq ($(CONFIG_SEPARATE_COMPILE),y) + SRC_FILES :=user_print_info.c user_task.c user_mem.c + + ifeq ($(CONFIG_KERNEL_SEMAPHORE),y) + SRC_FILES += user_semaphore.c + endif + + ifeq ($(CONFIG_KERNEL_MUTEX),y) + SRC_FILES += user_mutex.c + endif + + ifeq ($(CONFIG_KERNEL_EVENT),y) + SRC_FILES += user_event.c + endif + + ifeq ($(CONFIG_KERNEL_MESSAGEQUEUE),y) + SRC_FILES += user_msg.c + endif + + ifeq ($(CONFIG_FS_VFS),y) + SRC_FILES += user_fs.c + endif +else + SRC_FILES := +endif + +include $(KERNEL_ROOT)/compiler.mk \ No newline at end of file diff --git a/APP_Framework/Framework/transform_layer/xizi/user_api/switch_api/user_api.h b/APP_Framework/Framework/transform_layer/xizi/user_api/switch_api/user_api.h new file mode 100644 index 0000000..660c709 --- /dev/null +++ b/APP_Framework/Framework/transform_layer/xizi/user_api/switch_api/user_api.h @@ -0,0 +1,247 @@ +/* + * Copyright (c) 2020 AIIT XUOS Lab + * XiUOS is licensed under Mulan PSL v2. + * You can use this software according to the terms and conditions of the Mulan PSL v2. + * You may obtain a copy of Mulan PSL v2 at: + * http://license.coscl.org.cn/MulanPSL2 + * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, + * EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, + * MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. + * See the Mulan PSL v2 for more details. + */ + +/** +* @file: user_api.h +* @brief: the priviate user api for application +* @version: 1.0 +* @author: AIIT XUOS Lab +* @date: 2020/4/20 +* +*/ + +#ifndef XS_USER_API_H +#define XS_USER_API_H + +#include +#include +#include +#include + + +#ifdef SEPARATE_COMPILE + +#include "../../../../../../Ubiquitous/XiZi/arch/kswitch.h" + +#define TASK_INFO 1 +#define MEM_INFO 2 +#define SEM_INFO 3 +#define EVENT_INFO 4 +#define MUTEX_INFO 5 +#define MEMPOOL_INFO 6 +#define MSGQUEUE_INFO 7 +#define DEVICE_INFO 8 +#define TIMER_INFO 9 + +int UserPrintInfo(unsigned long i); + +struct utask +{ + char name[NAME_NUM_MAX]; + void *func_entry; + void *func_param; + int32_t stack_size; + uint8_t prio; +}; +typedef struct utask UtaskType; + +typedef void DIR; + +int32_t UserTaskCreate(UtaskType utask); + +long UserTaskStartup(int32_t id); +long UserTaskDelete(int32_t id); +long UserTaskSearch(void); +void UserTaskQuit(void); +long UserTaskDelay(int32_t ms); +long UserGetTaskName(int32_t id ,char *name); +int32_t UserGetTaskID(void); +uint8_t UserGetTaskStat(int32_t id); + +#ifdef ARCH_SMP +long UserTaskCoreCombine(int32_t id,uint8_t core_id); +long UserTaskCoreUnCombine(int32_t id); +uint8_t UserGetTaskCombinedCore(int32_t id); +uint8_t UserGetTaskRunningCore(int32_t id); +#endif + +long UserGetTaskErrorstatus(int32_t id); +uint8_t UserGetTaskPriority(int32_t id); + + +void *UserMalloc(size_t size); +void *UserRealloc(void *pointer, size_t size); +void *UserCalloc(size_t count, size_t size); +void UserFree(void *pointer); + +#ifdef KERNEL_MUTEX +int32_t UserMutexCreate(); +void UserMutexDelete(int32_t mutex); +int32_t UserMutexObtain(int32_t mutex, int32_t wait_time); +int32_t UserMutexAbandon(int32_t mutex); +#endif + + +#ifdef KERNEL_SEMAPHORE +typedef int32 sem_t; +sem_t UserSemaphoreCreate(uint16_t val); +long UserSemaphoreDelete(sem_t sem); +long UserSemaphoreObtain(sem_t sem, int32_t wait_time); +long UserSemaphoreAbandon(sem_t sem); +long UserSemaphoreSetValue(sem_t sem, uint16_t val); +#endif + + +#ifdef KERNEL_EVENT +typedef int32 EventIdType; +EventIdType UserEventCreate(uint8_t flag); +void UserEventDelete(EventIdType event); +long UserEventTrigger(EventIdType event, uint32_t set); +long UserEventProcess(EventIdType event, uint32_t set, uint8_t option, + int32_t wait_time, uint32_t *Recved); +long UserEventReinit(EventIdType event); +#endif + + +#ifdef KERNEL_MESSAGEQUEUE +int32_t UserMsgQueueCreate(size_t msg_size, size_t max_msgs); +long UserMsgQueueDelete(int32_t mq ); +long UserMsgQueueSendwait(int32_t mq, const void *buffer, + size_t size, int32_t wait_time); +long UserMsgQueueSend(int32_t mq, const void *buffer, size_t size); +long UserMsgQueueUrgentSend(int32_t mq, const void *buffer, size_t size); +long UserMsgQueueRecv(int32_t mq, void *buffer, size_t size,int32_t wait_time); +long UserMsgQueueReinit(int32_t mq); +#endif + +int open(const char *path, int flags, ...); +int read(int fd, void *buf, size_t len); +int write(int fd, const void *buf, size_t len); +int close(int fd); +int ioctl(int fd, int cmd, void *args); +off_t lseek(int fd, off_t offset, int whence); +int rename(const char *from, const char *to); +int unlink(const char *path); +int stat(const char *path, struct stat *buf); +int fstat(int fd, struct stat *buf); +int fsync(int fd); +int ftruncate(int fd, off_t length); + +int mkdir(const char *path, mode_t mode); +DIR *opendir(const char *path); +int closedir(DIR *dirp); +struct dirent *readdir(DIR *dirp); +int rmdir(const char *path); +int chdir(const char *path); +char *getcwd(char *buf, size_t size); +long telldir(DIR *dirp); +void seekdir(DIR *dirp, off_t offset); +void rewinddir(DIR *dirp); + +#ifdef FS_VFS +struct statfs { + size_t f_bsize; + size_t f_blocks; + size_t f_bfree; +}; + +int statfs(const char *path, struct statfs *buf); + +/* NOTE!!!: when cutting out file system, the 'printf' function can not output angthing */ +int Userprintf(const char *fmt, ...); + +#endif + + +#else + +#include + +#ifdef FS_VFS +#include +#endif + +struct utask +{ + char name[NAME_NUM_MAX]; + void *func_entry; + void *func_param; + int32_t stack_size; + uint8_t prio; +}; +typedef struct utask UtaskType; +int32_t UserTaskCreate(UtaskType utask); + +#define UserTaskStartup StartupKTask +#define UserTaskDelete KTaskDelete +#define UserTaskQuit KTaskQuit +#define UserTaskDelay MdelayKTask +#define UserTaskSearch UTaskSearch + +long UserGetTaskName(int32_t id ,char *name); +int32_t UserGetTaskID(void); +uint8_t UserGetTaskStat(int32_t id); + +#ifdef ARCH_SMP +#define UserTaskCoreCombine KTaskCoreCombine +#define UserTaskCoreUnCombine KTaskCoreUnCombine + +uint8_t UserGetTaskCombinedCore(int32_t id); +uint8_t UserGetTaskRunningCore(int32_t id); +#endif + +long UserGetTaskErrorstatus(int32_t id); +uint8_t UserGetTaskPriority(int32_t id); + +#define UserMalloc x_malloc +#define UserRealloc x_realloc +#define UserCalloc x_calloc +#define UserFree x_free + +#ifdef KERNEL_MUTEX +#define UserMutexCreate KMutexCreate +#define UserMutexDelete KMutexDelete +#define UserMutexObtain KMutexObtain +#define UserMutexAbandon KMutexAbandon +#endif + + +#ifdef KERNEL_SEMAPHORE +#define UserSemaphoreCreate KSemaphoreCreate +#define UserSemaphoreDelete KSemaphoreDelete +#define UserSemaphoreObtain KSemaphoreObtain +#define UserSemaphoreAbandon KSemaphoreAbandon +#define UserSemaphoreSetValue KSemaphoreSetValue +#endif + +#ifdef KERNEL_EVENT +#define UserEventCreate KEventCreate +#define UserEventDelete KEventDelete +#define UserEventTrigger KEventTrigger +#define UserEventProcess KEventProcess +#endif + +#ifdef KERNEL_MESSAGEQUEUE +#define UserMsgQueueCreate KCreateMsgQueue +#define UserMsgQueueDelete KDeleteMsgQueue +#define UserMsgQueueSendwait KMsgQueueSendwait +#define UserMsgQueueSend KMsgQueueSend +#define UserMsgQueueUrgentSend KMsgQueueUrgentSend +#define UserMsgQueueRecv KMsgQueueRecv +#define UserMsgQueueReinit KMsgQueueReinit +#endif + +#define UserPrintf KPrintf + +#endif + +#endif \ No newline at end of file diff --git a/APP_Framework/Framework/transform_layer/xizi/user_api/switch_api/user_event.c b/APP_Framework/Framework/transform_layer/xizi/user_api/switch_api/user_event.c new file mode 100644 index 0000000..3c21534 --- /dev/null +++ b/APP_Framework/Framework/transform_layer/xizi/user_api/switch_api/user_event.c @@ -0,0 +1,73 @@ +/* + * Copyright (c) 2020 AIIT XUOS Lab + * XiUOS is licensed under Mulan PSL v2. + * You can use this software according to the terms and conditions of the Mulan PSL v2. + * You may obtain a copy of Mulan PSL v2 at: + * http://license.coscl.org.cn/MulanPSL2 + * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, + * EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, + * MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. + * See the Mulan PSL v2 for more details. + */ + +/** +* @file: user_event.c +* @brief: the priviate user api of event for application +* @version: 1.0 +* @author: AIIT XUOS Lab +* @date: 2020/4/20 +* +*/ + +#include "user_api.h" + +/** + * This function will create a event. + * + * @param flag the trigger way of event. + * + * @return id + */ +EventIdType UserEventCreate(uint8_t flag){ + return (EventIdType)KSwitch1(KS_USER_EVENT_CREATE,(uintptr_t)flag ); +} + +/** + * This function will delete a event. + * + * @param event the id number of event. + * + * @return + */ +void UserEventDelete(EventIdType event){ + KSwitch1(KS_USER_EVENT_DELETE,(uintptr_t)event); +} + +/** + * This function will trigger the event + * + * @param event the id number of event + * @param set trigger way & events flag + * + * @return EOK on success. + */ +x_err_t UserEventTrigger(EventIdType event, uint32_t set){ + return (x_err_t)KSwitch2(KS_USER_EVENT_TRIGGER,(uintptr_t)event, (uintptr_t)set ); +} + +/** + * This function will get the event and process this event + * + * @param event the id number of event + * @param set events flag + * @param option trigger way + * @param wait_time timeout + * @param Recved event processed flag + * + * @return EOK on success. + */ +x_err_t UserEventProcess(EventIdType event, uint32_t set, uint8_t option, + int32_t wait_time, uint32_t *Recved){ + return (x_err_t)KSwitch5(KS_USER_EVENT_PROCESS,(uintptr_t)event, (uintptr_t)set, (uintptr_t)option, (uintptr_t)wait_time, (uintptr_t)Recved); +} + diff --git a/APP_Framework/Framework/transform_layer/xizi/user_api/switch_api/user_fs.c b/APP_Framework/Framework/transform_layer/xizi/user_api/switch_api/user_fs.c new file mode 100644 index 0000000..d60afc7 --- /dev/null +++ b/APP_Framework/Framework/transform_layer/xizi/user_api/switch_api/user_fs.c @@ -0,0 +1,150 @@ +/* + * Copyright (c) 2020 AIIT XUOS Lab + * XiUOS is licensed under Mulan PSL v2. + * You can use this software according to the terms and conditions of the Mulan PSL v2. + * You may obtain a copy of Mulan PSL v2 at: + * http://license.coscl.org.cn/MulanPSL2 + * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, + * EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, + * MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. + * See the Mulan PSL v2 for more details. + */ + +/** +* @file: user_fs.c +* @brief: the priviate user api of fs for application +* @version: 1.0 +* @author: AIIT XUOS Lab +* @date: 2020/4/20 +* +*/ + +#include "user_api.h" +#include +#include + +#define stdio 1 +#define CONSOLEBUF_SIZE 128 + +int open(const char *path, int flags, ...){ + va_list ap; + mode_t mode; + + va_start(ap, flags); + mode = va_arg(ap, mode_t); + va_end(ap); + return (int)(KSwitch3(KS_USER_OPEN,(uintptr_t)path,(uintptr_t)flags,(uintptr_t)mode)); +} + +int read(int fd, void *buf, size_t len){ + return (int)(KSwitch3(KS_USER_READ,(uintptr_t)fd,(uintptr_t)buf,(uintptr_t)len)); +} + +int write(int fd, const void *buf, size_t len){ + return (int)(KSwitch3(KS_USER_WRITE,(uintptr_t)fd,(uintptr_t)buf,(uintptr_t)len)); +} + +int close(int fd){ + return (int)(KSwitch1(KS_USER_CLOSE,(uintptr_t)fd)); +} + +int ioctl(int fd, int cmd, void *args){ + return (int)(KSwitch3(KS_USER_IOCTL,(uintptr_t)fd,(uintptr_t)cmd,(uintptr_t)args)); +} + +off_t lseek(int fd, off_t offset, int whence){ + return (off_t)(KSwitch3(KS_USER_LSEEK,(uintptr_t)fd,(uintptr_t)offset,(uintptr_t)whence)); +} + +int rename(const char *from, const char *to){ + return (int)(KSwitch2(KS_USER_RENAME,(uintptr_t)from,(uintptr_t)to)); +} + +int unlink(const char *path){ + return (int)(KSwitch1(KS_USER_UNLINK,(uintptr_t)path)); +} + +int stat(const char *path, struct stat *buf){ + return (int)(KSwitch2(KS_USER_STAT,(uintptr_t)path,(uintptr_t)buf)); +} + +int fstat(int fd, struct stat *buf){ + return (int)(KSwitch2(KS_USER_FS_STAT,(uintptr_t)fd,(uintptr_t)buf)); +} + +int fsync(int fd){ + return (int)(KSwitch1(KS_USER_FS_SYNC,(uintptr_t)fd)); +} + +int ftruncate(int fd, off_t length){ + return (int)(KSwitch2(KS_USER_FTRUNCATE,(uintptr_t)fd,(uintptr_t)length)); +} + +int mkdir(const char *path, mode_t mode){ + return (int)(KSwitch2(KS_USER_MKDIR,(uintptr_t)path,(uintptr_t)mode)); +} + +DIR *opendir(const char *path){ + return (DIR *)(KSwitch1(KS_USER_OPENDIR,(uintptr_t)path)); +} + +int closedir(DIR *dirp){ + return (int)(KSwitch1(KS_USER_CLOSEDIR,(uintptr_t)dirp)); +} + +struct dirent *readdir(DIR *dirp){ + return (struct dirent *)(KSwitch1(KS_USER_READDIR,(uintptr_t)dirp)); +} + +int rmdir(const char *path){ + return (int)(KSwitch1(KS_USER_RMDIR,(uintptr_t)path)); +} + +int chdir(const char *path){ + return (int)(KSwitch1(KS_USER_CHDIR,(uintptr_t)path)); +} + +char *getcwd(char *buf, size_t size){ + return (char *)(KSwitch2(KS_USER_GETCWD,(uintptr_t)buf,(uintptr_t)size )); +} + +long telldir(DIR *dirp){ + return (long)(KSwitch1(KS_USER_TELLDIR,(uintptr_t)dirp)); +} + +void seekdir(DIR *dirp, off_t offset){ + return (void)(KSwitch2(KS_USER_SEEKDIR,(uintptr_t)dirp,(uintptr_t)offset)); +} + +void rewinddir(DIR *dirp){ + return (void)(KSwitch1(KS_USER_REWIND_DIR,(uintptr_t)dirp)); +} + +int statfs(const char *path, struct statfs *buf){ + return (int)(KSwitch2(KS_USER_STAT_FS,(uintptr_t)path,(uintptr_t)buf)); +} + +int Userprintf(const char *fmt, ...) +{ + if(stdio != NONE) + { + va_list args; + size_t length; + static char logbuf[CONSOLEBUF_SIZE]; + // int fd = 0; + // fd = open("/dev/uart0_dev0",O_RDWR); + + va_start(args, fmt); + + length = vsnprintf(logbuf, sizeof(logbuf) - 1, fmt, args); + if (length > CONSOLEBUF_SIZE - 1) + length = CONSOLEBUF_SIZE - 1; + + write(stdio, logbuf, length); + // write(fd, logbuf, length); + // close(fd); + va_end(args); + } + return 0; +} + diff --git a/APP_Framework/Framework/transform_layer/xizi/user_api/switch_api/user_mem.c b/APP_Framework/Framework/transform_layer/xizi/user_api/switch_api/user_mem.c new file mode 100644 index 0000000..1498e98 --- /dev/null +++ b/APP_Framework/Framework/transform_layer/xizi/user_api/switch_api/user_mem.c @@ -0,0 +1,103 @@ +/* + * Copyright (c) 2020 AIIT XUOS Lab + * XiUOS is licensed under Mulan PSL v2. + * You can use this software according to the terms and conditions of the Mulan PSL v2. + * You may obtain a copy of Mulan PSL v2 at: + * http://license.coscl.org.cn/MulanPSL2 + * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, + * EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, + * MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. + * See the Mulan PSL v2 for more details. + */ + +/** +* @file: user_mem.c +* @brief: the priviate user api of mem for application +* @version: 1.0 +* @author: AIIT XUOS Lab +* @date: 2020/4/20 +* +*/ + +#include "user_api.h" +#include + +/** + * This function is provided to allocate memory block. + * + * @param size the memory size to be allocated + * + * @return pointer on success; NULL on failure + */ +void *UserMalloc(size_t size){ + return (void *)(KSwitch1(KS_USER_MALLOC,(uintptr_t)size)); +} + +/** + * This function is provided to release memory block. + * + * @param pointer the memory to be released + */ +void UserFree(void *pointer){ + KSwitch1(KS_USER_FREE,(uintptr_t)pointer); + return; +} + +/** + * This function is provided to re-allocate memory block. + * + * @param pointer the old memory pointer + * @param size the memory size to be re-allocated + * + * @return pointer on success; NULL on failure + */ +void *UserRealloc(void *pointer, size_t size){ + x_size_t newsize = 0; + x_size_t oldsize = 0; + void *newmem = NONE; + + /* the given pointer is NULL */ + if (pointer == NONE) + return UserMalloc(size); + + /* parameter detection */ + if (size == 0) { + UserFree(pointer); + return NONE; + } + + /* allocate new memory */ + newmem = UserMalloc(size); + if(newmem == NONE) { + return NONE; + } + + /* copy the old memory and then release old memory pointer */ + memcpy((char*)newmem, (char*) pointer,size > oldsize ? oldsize : size); + UserFree(pointer); + + return newmem; +} + +/** + * This function will allocate memory blocks and then clear the memory. + * + * @param count the number of memory blocks + * @param size the size of a memory block + * + * @return pointer on success; NULL on failure + */ +void *UserCalloc(size_t count, size_t size){ + void *p = NONE; + + /* calls x_malloc to allocate count * size memory */ + p = UserMalloc(count * size); + + /* zero the memory */ + if (p) + memset((char*)p, 0, count * size); + + return p; +} + + diff --git a/APP_Framework/Framework/transform_layer/xizi/user_api/switch_api/user_msg.c b/APP_Framework/Framework/transform_layer/xizi/user_api/switch_api/user_msg.c new file mode 100644 index 0000000..f55ec56 --- /dev/null +++ b/APP_Framework/Framework/transform_layer/xizi/user_api/switch_api/user_msg.c @@ -0,0 +1,120 @@ +/* + * Copyright (c) 2020 AIIT XUOS Lab + * XiUOS is licensed under Mulan PSL v2. + * You can use this software according to the terms and conditions of the Mulan PSL v2. + * You may obtain a copy of Mulan PSL v2 at: + * http://license.coscl.org.cn/MulanPSL2 + * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, + * EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, + * MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. + * See the Mulan PSL v2 for more details. + */ + +/** +* @file: user_msg.c +* @brief: the priviate user api of msg queue for application +* @version: 1.0 +* @author: AIIT XUOS Lab +* @date: 2020/4/20 +* +*/ + +#include "user_api.h" + +/** + * This function will create a msg queue. + * + * @param msg_size the length of the msg queue. + * @param max_msgs the max length of the msg queue. + * + * @return id on success;ENOMEMORY/ERROR on failure + */ +int32_t UserMsgQueueCreate( size_t msg_size, + size_t max_msgs){ + return (int32_t)KSwitch2(KS_USER_MSGQUEUE_CREATE, (uintptr_t)msg_size, (uintptr_t)max_msgs); +} + +/** + * a dynamic messagequeue will be deleted from the manage list + * + * @param id the message id + * + * @return EOK on success;EINVALED on failure + * + */ +x_err_t UserMsgQueueDelete(int32_t mq ){ + return (x_err_t)KSwitch1(KS_USER_MSGQUEUE_DELETE, (uintptr_t)mq); +} + +/** + * send message with waiting time,current suspend task will be resumed + * + * @param id the message id + * @param buffer message info + * @param size the size of buffer + * @param timeout waiting time + * + * @return EOK on success;EINVALED on failure + * + */ +x_err_t UserMsgQueueSendwait(int32_t mq, const void *buffer, + size_t size, int32_t wait_time){ + return (x_err_t)KSwitch3(KS_USER_MSGQUEUE_SEND , (uintptr_t)mq, (uintptr_t)buffer, (uintptr_t)size ); +} + +/** + * send message without waiting time,current suspend task will be resumed + * + * @param id the message id + * @param buffer message info + * @param size the size of buffer + * + * @return EOK on success;EINVALED on failure + * + */ +x_err_t UserMsgQueueSend(int32_t mq, const void *buffer, size_t size){ + + return (x_err_t)KSwitch3(KS_USER_MSGQUEUE_SEND , (uintptr_t)mq, (uintptr_t)buffer, (uintptr_t)size ); + +} +/** + * send urgent message without waiting time, this message will be inserted to the head of the queue + * + * @param id the message id + * @param buffer message info + * @param size the size of buffer + * + * @return EOK on success;EINVALED on failure + * + */ +x_err_t UserMsgQueueUrgentSend(int32_t mq, const void *buffer, size_t size){ + + return (x_err_t)KSwitch3(KS_USER_MSGQUEUE_URGENTSEND , (uintptr_t)mq, (uintptr_t)buffer, (uintptr_t)size ); +} + +/** + * receive message with some waiting time + * + * @param id the message id + * @param buffer message info + * @param size the size of buffer + * @param timeout time needed waiting + * + * @return EOK on success;EINVALED on failure + * + */ +x_err_t UserMsgQueueRecv(int32_t mq, void *buffer, + size_t size,int32_t wait_time){ + return (x_err_t)KSwitch4(KS_USER_MSGQUEUE_RECV ,(uintptr_t)mq, (uintptr_t)buffer, (uintptr_t)size, (uintptr_t)wait_time ); +} + +/** + * This function will reset a event. + * + * @param id the id number of event. + * + * @return EOK on success;EINVALED on failure + */ +x_err_t UserMsgQueueReinit(int32_t mq){ + return (x_err_t)KSwitch1(KS_USER_MSGQUEUE_REINIT ,(uintptr_t)mq ); +} diff --git a/APP_Framework/Framework/transform_layer/xizi/user_api/switch_api/user_mutex.c b/APP_Framework/Framework/transform_layer/xizi/user_api/switch_api/user_mutex.c new file mode 100644 index 0000000..e7e35da --- /dev/null +++ b/APP_Framework/Framework/transform_layer/xizi/user_api/switch_api/user_mutex.c @@ -0,0 +1,71 @@ +/* + * Copyright (c) 2020 AIIT XUOS Lab + * XiUOS is licensed under Mulan PSL v2. + * You can use this software according to the terms and conditions of the Mulan PSL v2. + * You may obtain a copy of Mulan PSL v2 at: + * http://license.coscl.org.cn/MulanPSL2 + * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, + * EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, + * MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. + * See the Mulan PSL v2 for more details. + */ + +/** +* @file: user_mutex.c +* @brief: the priviate user api of mutex for application +* @version: 1.0 +* @author: AIIT XUOS Lab +* @date: 2020/4/20 +* +*/ + +#include "user_api.h" + +/** + * a mutex will be inited in static way,then this mutex will be inserted to the manage list + * + * @param mutex the mutex descriptor + * @param name mutex name + * @param flag mutex flag + * + * @return EOK on success + * + */ +int32_t UserMutexCreate(){ + return (int32_t)KSwitch0(KS_USER_MUTEX_CREATE); +} + +/** + * a dynamic mutex will be deleted from the manage list + * + * @param mutex mutex descriptor + * + */ +void UserMutexDelete(int32_t mutex){ + KSwitch1(KS_USER_MUTEX_DELETE,(uintptr_t)mutex); +} + +/** + * a mutex will be taken when mutex is available + * + * @param mutex mutex descriptor + * @param msec the time needed waiting + * + * @return EOK on success;ERROR on failure + * + */ +int32_t UserMutexObtain(int32_t mutex, int32_t wait_time){ + return (int32_t)KSwitch2(KS_USER_MUTEX_OBTAIN,(uintptr_t)mutex, (uintptr_t)wait_time); +} + +/** + * release the mutex and resume corresponding suspended task + * + * @param mutex mutex descriptor + * + * @return EOK on success;ERROR on failure + */ +int32_t UserMutexAbandon(int32_t mutex){ + return (int32_t)KSwitch1(KS_USER_MUTEX_ABANDON,(uintptr_t)mutex); +} + diff --git a/APP_Framework/Framework/transform_layer/xizi/user_api/switch_api/user_print_info.c b/APP_Framework/Framework/transform_layer/xizi/user_api/switch_api/user_print_info.c new file mode 100644 index 0000000..2589d18 --- /dev/null +++ b/APP_Framework/Framework/transform_layer/xizi/user_api/switch_api/user_print_info.c @@ -0,0 +1,28 @@ +/* + * Copyright (c) 2020 AIIT XUOS Lab + * XiUOS is licensed under Mulan PSL v2. + * You can use this software according to the terms and conditions of the Mulan PSL v2. + * You may obtain a copy of Mulan PSL v2 at: + * http://license.coscl.org.cn/MulanPSL2 + * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, + * EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, + * MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. + * See the Mulan PSL v2 for more details. + */ + +/** +* @file: user_print_info.c +* @brief: the priviate user api of user info print for application +* @version: 1.0 +* @author: AIIT XUOS Lab +* @date: 2020/4/20 +* +*/ + +#include "user_api.h" + +/* for debug */ +int UserPrintInfo(unsigned long i){ + return (int)KSwitch1(KS_USER_PRINT_INFO,i); +} + diff --git a/APP_Framework/Framework/transform_layer/xizi/user_api/switch_api/user_semaphore.c b/APP_Framework/Framework/transform_layer/xizi/user_api/switch_api/user_semaphore.c new file mode 100644 index 0000000..dad695b --- /dev/null +++ b/APP_Framework/Framework/transform_layer/xizi/user_api/switch_api/user_semaphore.c @@ -0,0 +1,73 @@ +/* + * Copyright (c) 2020 AIIT XUOS Lab + * XiUOS is licensed under Mulan PSL v2. + * You can use this software according to the terms and conditions of the Mulan PSL v2. + * You may obtain a copy of Mulan PSL v2 at: + * http://license.coscl.org.cn/MulanPSL2 + * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, + * EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, + * MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. + * See the Mulan PSL v2 for more details. + */ + +/** +* @file: user_semaphore.c +* @brief: the priviate user api of semphore for application +* @version: 1.0 +* @author: AIIT XUOS Lab +* @date: 2020/4/20 +* +*/ + +#include "user_api.h" + +/** + * Create a new semaphore with specified initial value. + * + * @param val initial value + * @return id of the semaphore + */ +sem_t UserSemaphoreCreate(uint16_t val){ + return (sem_t)KSwitch1(KS_USER_SEMAPHORE_CREATE,(uintptr_t)val); +} + +/** + * Delete a semaphore and wakeup all pending tasks on it. + * + * @param id id of the semaphore to be deleted + */ +x_err_t UserSemaphoreDelete(sem_t sem){ + return (x_err_t)KSwitch1(KS_USER_SEMAPHORE_DELETE,(uintptr_t)sem); +} + +/** + * Obtain a semaphore when its value is greater than 0; pend on it otherwise. + * + * @param id id of the semaphore to be obtained + * @param msec wait time in millisecond + * @return EOK on success, error code on failure + */ +x_err_t UserSemaphoreObtain(sem_t sem, int32_t wait_time){ + return (x_err_t)KSwitch2(KS_USER_SEMAPHORE_OBTAIN,(uintptr_t)sem,(uintptr_t)wait_time); +} + +/** + * Abandon a semaphore and wakeup a pending task if any. + * + * @param id id of the semaphore to be abandoned + * @return EOK on success, error code on failure + */ +x_err_t UserSemaphoreAbandon(sem_t sem){ + return (x_err_t)KSwitch1(KS_USER_SEMAPHORE_ABANDON,(uintptr_t)sem); +} + +/** + * Set the value of a semaphore, wakeup all pending tasks if new value is positive. + * + * @param id id of the semaphore for which to set value + * @param val new value + * @return EOK on success, error code on failure + */ +x_err_t UserSemaphoreSetValue(sem_t sem, uint16_t val){ + return (x_err_t)KSwitch2(KS_USER_SEMAPHORE_SETVALUE,(uintptr_t)sem,(uintptr_t)val); +} diff --git a/APP_Framework/Framework/transform_layer/xizi/user_api/switch_api/user_task.c b/APP_Framework/Framework/transform_layer/xizi/user_api/switch_api/user_task.c new file mode 100644 index 0000000..3663b1d --- /dev/null +++ b/APP_Framework/Framework/transform_layer/xizi/user_api/switch_api/user_task.c @@ -0,0 +1,139 @@ +/* + * Copyright (c) 2020 AIIT XUOS Lab + * XiUOS is licensed under Mulan PSL v2. + * You can use this software according to the terms and conditions of the Mulan PSL v2. + * You may obtain a copy of Mulan PSL v2 at: + * http://license.coscl.org.cn/MulanPSL2 + * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, + * EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, + * MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. + * See the Mulan PSL v2 for more details. + */ + +/** +* @file: user_task.c +* @brief: the priviate user api of task for application +* @version: 1.0 +* @author: AIIT XUOS Lab +* @date: 2020/4/20 +* +*/ + +#include "user_api.h" + +/** + * + * This function init a user task in dynamic way . + * + * @param name task name + * @param parameter task process function + * @param parameter task arg + * @param stack_size task stack size + * @param priority task priority + * @param tick task time slice + * + * @return EOK on success; ENOMEMORY/EEMPTY on failure + */ +int32_t UserTaskCreate(UtaskType utask){ + return (int32_t) KSwitch5(KS_USER_TASK_CREATE,(uintptr_t)utask.name,(uintptr_t)utask.func_entry,(uintptr_t)utask.func_param,(uintptr_t)utask.stack_size,(uintptr_t)utask.prio); +} + +/** + * This function will insert task to ready queue then schedule + * + * @param id task id + * + * @return EOK on success; EINVALED on failure + */ +x_err_t UserTaskStartup(int32_t id){ + return (x_err_t)KSwitch1(KS_USER_TASK_STARTUP,(uintptr_t)id); +} + +/** + * This function will remove a dynamic task out of the task manage list. + * + * @param id task id + * + * @return EOK on success; EINVALED on failure + */ +x_err_t UserTaskDelete(int32_t id){ + return (x_err_t)KSwitch1(KS_USER_TASK_DELETE,(uintptr_t)id); +} + +/** + * This function will find the first user task in task manage list. + * + * @param + * + * @return task id on success; EINVALED on failure + */ +x_err_t UserTaskSearch(void){ + return KSwitch0(KS_USER_TASK_SEARCH); +} + +void UserTaskQuit(void){ + KSwitch0(KS_USER_TASK_EXECEXIT); + return ; +} +/** + * This function will delay current task running with some ticks. + * + * @param tick delay ticks + * @return EOK on success; EINVALED/EEMPTY on failure + */ +x_err_t UserTaskDelay(int32_t ms){ + return (x_err_t)KSwitch1(KS_USER_TASK_DELAY,(uintptr_t)ms); +} + +x_err_t UserGetTaskName( int32_t id, char *name){ + return (x_err_t)KSwitch2(KS_USER_GET_TASK_NAME,(uintptr_t)id, (uintptr_t)name); +} + +int32_t UserGetTaskID(void){ + return (int32_t)KSwitch0(KS_USER_GET_TASK_ID); +} + +uint8_t UserGetTaskStat(int32_t id){ + return (uint8_t)KSwitch1(KS_USER_GET_TASK_STAT,(uintptr_t)id ); +} + +#ifdef ARCH_SMP +/** + * This function binds a task to cpu core. + * + * @param id task id + * @param coreid cpu core id + * + * @return EOK + */ +x_err_t UserTaskCoreCombine(int32_t id,uint8_t core_id){ + return (x_err_t)KSwitch2(KS_USER_TASK_CORE_COMBINE,(uintptr_t)id,core_id); +} +/** + * This function unbinds a task with cpu core. + * + * @param id task id + * + * @return EOK + */ +x_err_t UserTaskCoreUnCombine(int32_t id){ + return (x_err_t)KSwitch1(KS_USER_TASK_CORE_UNCOMBINE,(uintptr_t)id); +} + +uint8_t UserGetTaskCombinedCore(int32_t id){ + return (uint8_t)KSwitch1(KS_USER_GET_TASK_COMBINEED_CORE,(uintptr_t)id ); +} + +uint8 UserGetTaskRunningCore(int32_t id){ + return (uint8_t)KSwitch1(KS_USER_GET_TASK_RUNNING_CORE,(uintptr_t)id ); +} + +#endif + +x_err_t UserGetTaskErrorstatus(int32_t id){ + return (x_err_t)KSwitch1(KS_USER_GET_TASK_ERROR_STATUS,(uintptr_t)id ); +} + +uint8_t UserGetTaskPriority(int32_t id){ + return (uint8_t)KSwitch1(KS_USER_GET_TASK_PRIORITY,(uintptr_t)id ); +} diff --git a/APP_Framework/Framework/transform_layer/xizi/userspace.c b/APP_Framework/Framework/transform_layer/xizi/userspace.c new file mode 100644 index 0000000..fa56e57 --- /dev/null +++ b/APP_Framework/Framework/transform_layer/xizi/userspace.c @@ -0,0 +1,43 @@ +#include +#include + +extern int main(void); +extern void UserTaskQuit(void); +extern uintptr_t _ustext; +extern uintptr_t _uetext; +extern uintptr_t _ueronly; +extern uintptr_t _usdata; +extern uintptr_t _uedata; +extern uintptr_t _usbss; +extern uintptr_t _uebss; +typedef int (*main_t)(int argc, char *argv[]); +typedef void (*exit_t)(void); +struct userspace_s +{ + main_t us_entrypoint; + exit_t us_taskquit; + uintptr_t us_textstart; + uintptr_t us_textend; + uintptr_t us_datasource; + uintptr_t us_datastart; + uintptr_t us_dataend; + uintptr_t us_bssstart; + uintptr_t us_bssend; + uintptr_t us_heapend; +}; + +const struct userspace_s userspace __attribute__ ((section (".userspace"))) = +{ + /* General memory map */ + + .us_entrypoint = (main_t)main, + .us_taskquit = (exit_t)UserTaskQuit, + .us_textstart = (uintptr_t)&_ustext, + .us_textend = (uintptr_t)&_uetext, + .us_datasource = (uintptr_t)&_ueronly, + .us_datastart = (uintptr_t)&_usdata, + .us_dataend = (uintptr_t)&_uedata, + .us_bssstart = (uintptr_t)&_usbss, + .us_bssend = (uintptr_t)&_uebss, + +}; \ No newline at end of file diff --git a/APP_Framework/Kconfig b/APP_Framework/Kconfig new file mode 100644 index 0000000..8e96e6f --- /dev/null +++ b/APP_Framework/Kconfig @@ -0,0 +1,13 @@ +menu "APP_Framework" + + config APP_DIR + string + option env="SRC_APP_DIR" + default "." + +source "$APP_DIR/Framework/Kconfig" +source "$APP_DIR/Applications/Kconfig" +source "$APP_DIR/lib/Kconfig" + + +endmenu diff --git a/APP_Framework/Make.defs b/APP_Framework/Make.defs new file mode 100644 index 0000000..7f23f14 --- /dev/null +++ b/APP_Framework/Make.defs @@ -0,0 +1,5 @@ +############################################################################ +# APP_Framework/Make.defs +############################################################################ +CONFIGURED_APPS += $(APPDIR)/../../../APP_Framework +include $(wildcard $(APPDIR)/../../../APP_Framework/*/Make.defs) diff --git a/APP_Framework/Makefile b/APP_Framework/Makefile new file mode 100644 index 0000000..3a83291 --- /dev/null +++ b/APP_Framework/Makefile @@ -0,0 +1,11 @@ +include $(KERNEL_ROOT)/.config +ifeq ($(CONFIG_ADD_NUTTX_FETURES),y) + include $(APPDIR)/Make.defs + include $(APPDIR)/Application.mk +endif + +ifeq ($(CONFIG_ADD_XIZI_FETURES),y) + SRC_DIR := Applications Framework lib + include $(KERNEL_ROOT)/compiler.mk +endif + diff --git a/APP_Framework/lib/Kconfig b/APP_Framework/lib/Kconfig new file mode 100755 index 0000000..8fefd67 --- /dev/null +++ b/APP_Framework/lib/Kconfig @@ -0,0 +1,16 @@ +menu "lib" + choice + prompt "chose a kind of lib for app" + default APP_SELECT_NEWLIB + + config APP_SELECT_NEWLIB + bool "app select newlib" + + config APP_SELECT_OTHER_LIB + bool "app select other lib" + endchoice + source "$APP_DIR/lib/cJSON/Kconfig" + source "$APP_DIR/lib/queue/Kconfig" + source "$APP_DIR/lib/lvgl/Kconfig" + source "$APP_DIR/lib/embedded_database/Kconfig" +endmenu diff --git a/APP_Framework/lib/Makefile b/APP_Framework/lib/Makefile new file mode 100644 index 0000000..24a27d0 --- /dev/null +++ b/APP_Framework/lib/Makefile @@ -0,0 +1,17 @@ +# SRC_DIR := lvgl + +ifeq ($(CONFIG_APP_SELECT_NEWLIB),y) + ifeq ($(CONFIG_SEPARATE_COMPILE),y) + SRC_DIR += app_newlib + endif +endif + +ifeq ($(CONFIG_LIB_LV),y) + SRC_DIR += lvgl +endif + +ifeq ($(CONFIG_LIB_USING_CJSON),y) + SRC_DIR += cJSON +endif + +include $(KERNEL_ROOT)/compiler.mk diff --git a/APP_Framework/lib/SConscript b/APP_Framework/lib/SConscript new file mode 100644 index 0000000..f307e3f --- /dev/null +++ b/APP_Framework/lib/SConscript @@ -0,0 +1,14 @@ +import os +Import('RTT_ROOT') +from building import * + +cwd = GetCurrentDir() +objs = [] +list = os.listdir(cwd) + +for d in list: + path = os.path.join(cwd, d) + if os.path.isfile(os.path.join(path, 'SConscript')): + objs = objs + SConscript(os.path.join(path, 'SConscript')) + +Return('objs') diff --git a/Ubiquitous/Kselector_features b/Ubiquitous/Kselector_features new file mode 100644 index 0000000..60de293 --- /dev/null +++ b/Ubiquitous/Kselector_features @@ -0,0 +1,65 @@ +menu "Required Feature" # do not modify this, otherwise, (see `egrep '^# Required'` in kernel_selector.sh) + +menuconfig FS + bool "require file system" + default n + +if FS + config FS_VFS_FATFS + bool "Using FATFS file system" + default n + + config FS_CH376 + bool "Using CH376 file system" + default n + + config FS_LWEXT4 + bool "Using LWEXT4 file system" + default n +endif + + +menuconfig INDUSTRIAL + bool "Require industrial protocols support" + default n + +if INDUSTRIAL + config INDUSTRIAL_OPCUA + bool "Support OPCUA" + default n + + config INDUSTRIAL_SNAP7 + bool "Support Siemens Snap7" + default n + + config INDUSTRIAL_MODBUS + bool "Support Modbus" + default n + + config INDUSTRIAL_RS232 + bool "Support RS232" + default n + + config INDUSTRIAL_RS485 + bool "Support RS485" + default n +endif + + +menuconfig BUS + bool "require bus" + default y + +if BUS + menu "Required BUS" + config USB + bool "require USB bus" + default n + + config SERIAL + bool "require serial bus" + default n + endmenu +endif + +endmenu diff --git a/Ubiquitous/Kselector_features_meta b/Ubiquitous/Kselector_features_meta new file mode 100644 index 0000000..60de293 --- /dev/null +++ b/Ubiquitous/Kselector_features_meta @@ -0,0 +1,65 @@ +menu "Required Feature" # do not modify this, otherwise, (see `egrep '^# Required'` in kernel_selector.sh) + +menuconfig FS + bool "require file system" + default n + +if FS + config FS_VFS_FATFS + bool "Using FATFS file system" + default n + + config FS_CH376 + bool "Using CH376 file system" + default n + + config FS_LWEXT4 + bool "Using LWEXT4 file system" + default n +endif + + +menuconfig INDUSTRIAL + bool "Require industrial protocols support" + default n + +if INDUSTRIAL + config INDUSTRIAL_OPCUA + bool "Support OPCUA" + default n + + config INDUSTRIAL_SNAP7 + bool "Support Siemens Snap7" + default n + + config INDUSTRIAL_MODBUS + bool "Support Modbus" + default n + + config INDUSTRIAL_RS232 + bool "Support RS232" + default n + + config INDUSTRIAL_RS485 + bool "Support RS485" + default n +endif + + +menuconfig BUS + bool "require bus" + default y + +if BUS + menu "Required BUS" + config USB + bool "require USB bus" + default n + + config SERIAL + bool "require serial bus" + default n + endmenu +endif + +endmenu diff --git a/Ubiquitous/Kselector_params b/Ubiquitous/Kselector_params new file mode 100644 index 0000000..3f834ba --- /dev/null +++ b/Ubiquitous/Kselector_params @@ -0,0 +1,26 @@ +menu "Required Parameter" + config RAM_LESS_THAN + int "RAM footprint limit (MB) upper bound" + default 10000 + help + Kernel RAM footprint should be lower than this limit + + config RAM_GREATER_THAN + int "RAM footprint limit (MB) lower bound" + default 0 + help + Kernel RAM footprint should be higher than this limit + + config ROM_LESS_THAN + int "ROM limit (MB) upper bound" + default 10000 + help + Kernel ROM requirement should be lower than this limit + + config ROM_GREATER_THAN + int "ROM limit (MB) lower bound" + default 0 + help + Kernel ROM requirement should be higher than this limit + +endmenu diff --git a/Ubiquitous/Kselector_params_meta b/Ubiquitous/Kselector_params_meta new file mode 100644 index 0000000..3f834ba --- /dev/null +++ b/Ubiquitous/Kselector_params_meta @@ -0,0 +1,26 @@ +menu "Required Parameter" + config RAM_LESS_THAN + int "RAM footprint limit (MB) upper bound" + default 10000 + help + Kernel RAM footprint should be lower than this limit + + config RAM_GREATER_THAN + int "RAM footprint limit (MB) lower bound" + default 0 + help + Kernel RAM footprint should be higher than this limit + + config ROM_LESS_THAN + int "ROM limit (MB) upper bound" + default 10000 + help + Kernel ROM requirement should be lower than this limit + + config ROM_GREATER_THAN + int "ROM limit (MB) lower bound" + default 0 + help + Kernel ROM requirement should be higher than this limit + +endmenu diff --git a/Ubiquitous/RT-Thread_Fusion_XiUOS/README.md b/Ubiquitous/RT-Thread_Fusion_XiUOS/README.md new file mode 100644 index 0000000..25cc63e --- /dev/null +++ b/Ubiquitous/RT-Thread_Fusion_XiUOS/README.md @@ -0,0 +1,46 @@ +# 基于rt-thread的矽璓工业物联操作系统XiUOS + +矽璓工业物联操作系统XiUOS主要分为系统层 、框架层、和应用层。其中系统层支持XIUOS、Nuttx、rt-thread三个操作系统，该目录主要内容是基于**rt-thread的系统层。** + +## 目录内容 + +``` +xiuos/Ubiquitous/RT-Thread_Fusion_XiUOS + ├── README.md + ├── aiit_board 板级支持包 + |──stm32f407_core + |──k210 + ├── app_match_rt-thread WiFi、Camera 等适配rt-thread的用户驱动 + └── rt-thread rt-thread 代码 +``` + +## 支持平台 + +RT-Thread_Fusion_XiUOS/aiit_board 目前主要支持平台：stm32f407_core，k210,aiit-riscv64-board,stm32h743_openmv_h7plus,xidatong. + +RT-Thread_Fusion_XiUOS/app_match_rt-thread 目前主要支持 WiFi 和 Camera，其他驱动复用 RT-Thread 的内容。如果rt-thread官方仓库驱动不满足用户使用要求，如果用户增加相关驱动可在此目录。 + +RT-Thread_Fusion_XiUOS/rt-thread 使用 RT-Thread 作为系统基础设施，提供底层支持。 + +## 使用 + +运行以下指令下载代码、编译运行： + +``` +# 下载代码 +# 进入xiuos目录下载更新子模块(包括RT-thread 和 K210 SDK（如果用到K210 需更新kendryte-sdk）)执行以下三条命令或者直接执行当前目录下的download.sh脚本命令 +git submodule init +git submodule update Ubiquitous/RT-Thread_Fusion_XiUOS/rt-thread +git submodule update Ubiquitous/RT-Thread_Fusion_XiUOS/aiit_board/k210/kendryte-sdk/kendryte-sdk-source + +# 进入 xiuos/Ubiquitous/RT-Thread_Fusion_XiUOS/aiit_board/stm32f407_core 配置 Kconfig +scons --menuconfig +# 编译 +scons +# 烧录镜像 +st-flash write rtthread.bin 0x8000000 +``` + +同时也可以支持windows开发环境进行上述命令进行编译，需安装env插件，详细介绍可以参照[rt-thread官方资料](https://www.rt-thread.org/document/site/#/rt-thread-version/rt-thread-standard/application-note/setup/standard-project/an0017-standard-project?id=%e4%bd%bf%e7%94%a8-env-%e5%88%9b%e5%bb%ba-rt-thread-%e9%a1%b9%e7%9b%ae%e5%b7%a5%e7%a8%8b +)。 + diff --git a/Ubiquitous/RT-Thread_Fusion_XiUOS/download.sh b/Ubiquitous/RT-Thread_Fusion_XiUOS/download.sh new file mode 100755 index 0000000..07a0b16 --- /dev/null +++ b/Ubiquitous/RT-Thread_Fusion_XiUOS/download.sh @@ -0,0 +1,6 @@ +#切换到root目录 +cd ../../ +echo $(pwd) +git submodule init +git submodule update Ubiquitous/RT-Thread_Fusion_XiUOS/rt-thread +git submodule update Ubiquitous/RT-Thread_Fusion_XiUOS/aiit_board/k210/kendryte-sdk/kendryte-sdk-source \ No newline at end of file diff --git a/Ubiquitous/XiZi/.gitignore b/Ubiquitous/XiZi/.gitignore new file mode 100644 index 0000000..acc9294 --- /dev/null +++ b/Ubiquitous/XiZi/.gitignore @@ -0,0 +1,12 @@ +xsconfig.h +xsconfig.mk +.config +.config.old +build +XiUOS.* +*.swp +.vscode +# for kernel_selector +.selector +.selector.old +requirement.yaml \ No newline at end of file diff --git a/Ubiquitous/XiZi/Kconfig b/Ubiquitous/XiZi/Kconfig new file mode 100644 index 0000000..2272a4f --- /dev/null +++ b/Ubiquitous/XiZi/Kconfig @@ -0,0 +1,8 @@ + +source "$KERNEL_DIR/kernel/Kconfig" + +source "$KERNEL_DIR/lib/Kconfig" + +source "$KERNEL_DIR/fs/Kconfig" + +source "$KERNEL_DIR/../../APP_Framework/Kconfig" diff --git a/Ubiquitous/XiZi/LICENSE b/Ubiquitous/XiZi/LICENSE new file mode 100644 index 0000000..d63dfb7 --- /dev/null +++ b/Ubiquitous/XiZi/LICENSE @@ -0,0 +1,124 @@ +木兰宽松许可证， 第2版 + +2020年1月 http://license.coscl.org.cn/MulanPSL2 + +您对“软件”的复制、使用、修改及分发受木兰宽松许可证，第2版（“本许可证”）的如下条款的约束： + +0. 定义 + +“软件” 是指由“贡献”构成的许可在“本许可证”下的程序和相关文档的集合。 + +“贡献” 是指由任一“贡献者”许可在“本许可证”下的受版权法保护的作品。 + +“贡献者” 是指将受版权法保护的作品许可在“本许可证”下的自然人或“法人实体”。 + +“法人实体” 是指提交贡献的机构及其“关联实体”。 + +“关联实体” 是指，对“本许可证”下的行为方而言，控制、受控制或与其共同受控制的机构，此处的控制是指有受控方或共同受控方至少50%直接或间接的投票权、资金或其他有价证券。 + +1. 授予版权许可 + +每个“贡献者”根据“本许可证”授予您永久性的、全球性的、免费的、非独占的、不可撤销的版权许可，您可以复制、使用、修改、分发其“贡献”，不论修改与否。 + +2. 授予专利许可 + +每个“贡献者”根据“本许可证”授予您永久性的、全球性的、免费的、非独占的、不可撤销的（根据本条规定撤销除外）专利许可，供您制造、委托制造、使用、许诺销售、销售、进口其“贡献”或以其他方式转移其“贡献”。前述专利许可仅限于“贡献者”现在或将来拥有或控制的其“贡献”本身或其“贡献”与许可“贡献”时的“软件”结合而将必然会侵犯的专利权利要求，不包括对“贡献”的修改或包含“贡献”的其他结合。如果您或您的“关联实体”直接或间接地，就“软件”或其中的“贡献”对任何人发起专利侵权诉讼（包括反诉或交叉诉讼）或其他专利维权行动，指控其侵犯专利权，则“本许可证”授予您对“软件”的专利许可自您提起诉讼或发起维权行动之日终止。 + +3. 无商标许可 + +“本许可证”不提供对“贡献者”的商品名称、商标、服务标志或产品名称的商标许可，但您为满足第4条规定的声明义务而必须使用除外。 + +4. 分发限制 + +您可以在任何媒介中将“软件”以源程序形式或可执行形式重新分发，不论修改与否，但您必须向接收者提供“本许可证”的副本，并保留“软件”中的版权、商标、专利及免责声明。 + +5. 免责声明与责任限制 + +“软件”及其中的“贡献”在提供时不带任何明示或默示的担保。在任何情况下，“贡献者”或版权所有者不对任何人因使用“软件”或其中的“贡献”而引发的任何直接或间接损失承担责任，不论因何种原因导致或者基于何种法律理论，即使其曾被建议有此种损失的可能性。 + +6. 语言 + +“本许可证”以中英文双语表述，中英文版本具有同等法律效力。如果中英文版本存在任何冲突不一致，以中文版为准。 + +条款结束 + +如何将木兰宽松许可证，第2版，应用到您的软件 + +如果您希望将木兰宽松许可证，第2版，应用到您的新软件，为了方便接收者查阅，建议您完成如下三步： + +1， 请您补充如下声明中的空白，包括软件名、软件的首次发表年份以及您作为版权人的名字； + +2， 请您在软件包的一级目录下创建以“LICENSE”为名的文件，将整个许可证文本放入该文件中； + +3， 请将如下声明文本放入每个源文件的头部注释中。 + +Copyright (c) [Year] [name of copyright holder] +[Software Name] is licensed under Mulan PSL v2. +You can use this software according to the terms and conditions of the Mulan PSL v2. +You may obtain a copy of Mulan PSL v2 at: + http://license.coscl.org.cn/MulanPSL2 +THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, +EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, +MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. +See the Mulan PSL v2 for more details. +Mulan Permissive Software License，Version 2 +Mulan Permissive Software License，Version 2 (Mulan PSL v2) + +January 2020 http://license.coscl.org.cn/MulanPSL2 + +Your reproduction, use, modification and distribution of the Software shall be subject to Mulan PSL v2 (this License) with the following terms and conditions: + +0. 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IN THE CASE OF DIVERGENCE BETWEEN THE CHINESE AND ENGLISH VERSIONS, THE CHINESE VERSION SHALL PREVAIL. + +END OF THE TERMS AND CONDITIONS + +How to Apply the Mulan Permissive Software License，Version 2 (Mulan PSL v2) to Your Software + +To apply the Mulan PSL v2 to your work, for easy identification by recipients, you are suggested to complete following three steps: + +Fill in the blanks in following statement, including insert your software name, the year of the first publication of your software, and your name identified as the copyright owner; +Create a file named "LICENSE" which contains the whole context of this License in the first directory of your software package; +Attach the statement to the appropriate annotated syntax at the beginning of each source file. +Copyright (c) [Year] [name of copyright holder] +[Software Name] is licensed under Mulan PSL v2. +You can use this software according to the terms and conditions of the Mulan PSL v2. +You may obtain a copy of Mulan PSL v2 at: + http://license.coscl.org.cn/MulanPSL2 +THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, +EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, +MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. +See the Mulan PSL v2 for more details. diff --git a/Ubiquitous/XiZi/Makefile b/Ubiquitous/XiZi/Makefile new file mode 100755 index 0000000..7ef1113 --- /dev/null +++ b/Ubiquitous/XiZi/Makefile @@ -0,0 +1,140 @@ +MAKEFLAGS += --no-print-directory + + +.PHONY:all clean distclean show_info menuconfig +.PHONY:COMPILE_APP COMPILE_KERNEL + + +support :=kd233 stm32f407-st-discovery maix-go stm32f407zgt6 aiit-riscv64-board aiit-arm32-board hifive1-rev-B hifive1-emulator k210-emulator cortex-m3-emulator cortex-m4-emulator ok1052-c gapuino stm32f103-nano gd32vf103_rvstar cortex-m0-emulator rv32m1_vega nuvoton-m2354 +support += xidatong +SRC_DIR := + +export BOARD ?=kd233 +# This is the environment variable for kconfig-mconf +export KCONFIG_CONFIG ?= .config + +ifeq ($(filter $(BOARD),$(support)),) +$(warning "You should choose board like this:make BOARD=kd233") +$(warning "This is what we support:") +$(warning "$(support)") +$(error "break" ) +endif + +export TARGET +export COMPILE_TYPE +export KERNEL_ROOT ?=$(strip $(shell pwd)) + +MAKEFILES =$(KERNEL_ROOT)/.config +-include $(KERNEL_ROOT)/.config + +export BSP_ROOT ?= $(KERNEL_ROOT)/board/$(BOARD) +export UBIQUITOUS_ROOT ?= .. +include board/$(BOARD)/config.mk +export BSP_BUILD_DIR := board/$(BOARD) +export HOSTTOOLS_DIR ?= $(KERNEL_ROOT)/tool/hosttools +export CONFIG2H_EXE ?= $(HOSTTOOLS_DIR)/xsconfig.sh + +export GEN_KSELECTOR_EXE ?= $(HOSTTOOLS_DIR)/generate_kselector.py +export FEATURE2YAML_EXE ?= $(HOSTTOOLS_DIR)/kernel_selector.sh +export KSELECTOR_EXE ?= $(HOSTTOOLS_DIR)/kernel_selector.py +export CPPPATHS +export SRC_APP_DIR := ../../APP_Framework +export SRC_KERNEL_DIR := arch board lib fs kernel resources tool +export SRC_DIR:= $(SRC_APP_DIR) $(SRC_KERNEL_DIR) + +PART:= + +all: + +ifeq ($(CONFIG_COMPILER_APP)_$(CONFIG_COMPILER_KERNEL),y_) +include path_app.mk +PART += COMPILE_APP + +else ifeq ($(CONFIG_COMPILER_APP)_$(CONFIG_COMPILER_KERNEL),_y) +include path_kernel.mk +PART += COMPILE_KERNEL + +else ifeq ($(CONFIG_COMPILER_APP)_$(CONFIG_COMPILER_KERNEL),y_y) +include path_app.mk +include path_kernel.mk +PART := COMPILE_APP COMPILE_KERNEL + +else +include path_kernel.mk +CPPPATHS := $(KERNELPATHS) +PART := COMPILE_ALL +endif + + + +all: $(PART) + + +COMPILE_ALL: + @for dir in $(SRC_DIR);do \ + $(MAKE) -C $$dir; \ + done + @cp link.mk build/Makefile + @$(MAKE) -C build TARGET=XiZi_$(BOARD).elf LINK_FLAGS=LFLAGS + @rm build/Makefile build/make.obj + + + +show_info: + @echo "CONFIG_COMPILER_APP is :" $(CONFIG_COMPILER_APP) + @echo "CONFIG_COMPILER_KERNEL is :" $(CONFIG_COMPILER_KERNEL) + @echo "KERNELPATHS is :" $(KERNELPATHS) + @echo "TARGET is :" $(TARGET) + @echo "VPATH is :" $(VPATH) + @echo "BSP_ROOT is :" $(BSP_ROOT) + @echo "KERNEL_ROOT is :" $(KERNEL_ROOT) + @echo "CPPPATHS is :" $(CPPPATHS) + @echo "SRC_DIR is :" $(SRC_DIR) + @echo "BUILD_DIR is :" $(BUILD_DIR) + @echo "RTT_ROOT_DIR is :" $(RTT_ROOT_DIR) + @echo "BSP_BUILD_DIR is :" $(BSP_BUILD_DIR) + @echo "OBJS is :" $(OBJS) + @for f in $(CPPPATHS); do \ + echo $$f; \ + done + + + +menuconfig: + @if [ -f "$(BSP_ROOT)/.config" ]; then \ + cp $(BSP_ROOT)/.config $(KERNEL_ROOT)/.config; \ + else if [ -f "$(BSP_ROOT)/.defconfig" ]; then \ + cp $(BSP_ROOT)/.defconfig $(KERNEL_ROOT)/.config ;\ + fi ;fi + @kconfig-mconf $(BSP_ROOT)/Kconfig + @$(CONFIG2H_EXE) .config + @cp $(KERNEL_ROOT)/.config $(BSP_ROOT)/.config + +kernel_selector: + $(eval KCONFIG_CONFIG := .selector) + @if [ -f "$(BSP_ROOT)/.selector" ]; then \ + cp $(BSP_ROOT)/.selector $(KERNEL_ROOT)/.selector; \ + else if [ -f "$(BSP_ROOT)/.defselector" ]; then \ + cp $(BSP_ROOT)/.defselector $(KERNEL_ROOT)/.selector ;\ + fi ;fi + @$(GEN_KSELECTOR_EXE) + @cp "$(UBIQUITOUS_ROOT)/Kselector_features_meta" $(UBIQUITOUS_ROOT)/Kselector_features + @cp "$(UBIQUITOUS_ROOT)/Kselector_params_meta" $(UBIQUITOUS_ROOT)/Kselector_params + @kconfig-mconf $(BSP_ROOT)/Kselector + @$(FEATURE2YAML_EXE) .selector + @if [ -f "$(BSP_ROOT)/requirement.yaml" ]; then \ + cp $(BSP_ROOT)/requirement.yaml $(KERNEL_ROOT)/requirement.yaml; \ + fi + @$(KSELECTOR_EXE) + @cp $(KERNEL_ROOT)/.selector $(BSP_ROOT)/.selector + +clean: + @echo Clean target and build_dir + @rm -rf build + @rm -rf temp.txt + +distclean: + @echo Clean all configuration + @make clean + @rm -f .config* + @rm -f $(KERNEL_ROOT)/board/*/.config diff --git a/Ubiquitous/XiZi/README.md b/Ubiquitous/XiZi/README.md new file mode 100644 index 0000000..238db6a --- /dev/null +++ b/Ubiquitous/XiZi/README.md @@ -0,0 +1,68 @@ +# XiUOS README + +[矽璓XiUOS](http://xuos.io/)是一款面向智慧车间的工业物联网操作系统，主要由一个极简的微型实时操作系统内核XiZi和其上的工业物联框架构成，通过高效管理工业物联网设备、支撑工业物联应用，在生产车间内实现智能化的“感知环境、联网传输、知悉识别、控制调整”，促进以工业设备和工业控制系统为核心的人、机、物深度互联，帮助提升生产线的数字化和智能化水平。 + +## 目录结构 + +| 名称 | 说明 | +| -- | -- | +| arch | 架构代码 | +| board | 板级支持包 | +| fs | 文件系统 | +| kernel | 内核源码 | +| lib | 第三方库源码 | +| resources | 驱动文件 | +| tool | 系统工具 | +| | | + +## 硬件支持 + +目前XiUOS支持ARM和RISC-V两种架构的微处理器: + +### ARM + +ARM架构系列的开发板有 + + aiit-arm32-board nuvoton-m2354 ok1052-c stm32f103-nano stm32f407-st-discovery stm32f407zgt6 xidatong + +### RISC-V + +RISC-V架构系列的开发板有 + + aiit-riscv64-board gapuino gd32vf103_rvstar hifive1-rev-B kd233 maix-go rv32m1_vega + +## 开发环境 + +### 推荐使用： + +### 操作系统： [Ubuntu18.04](https://ubuntu.com/download/desktop) + +### 开发工具： [VSCode](http://101.36.126.201:8011/vscode_1.55.2-1618307277_amd64.deb) + +### 依赖包安装： + +``` +$ sudo apt-get install build-essential pkg-config +$ sudo apt-get install gcc make libncurses5-dev openssl libssl-dev bison flex libelf-dev autoconf libtool gperf libc6-dev +``` + +### 编译工具链： + +ARM： arm-none-eabi，默认安装到Ubuntu的/usr/bin/arm-none-eabi-，使用如下命令行下载 +```shell +$ sudo apt-get install gcc-arm-none-eabi +``` + +RISC-V: riscv-none-embed-，默认安装到Ubuntu的/opt/，下载源码并解压。[下载网址](https://github.com/ilg-archived/riscv-none-gcc/releases) + +```shell +$ tar -zxvf gnu-mcu-eclipse-riscv-none-gcc-8.2.0-2.1-20190425-1021-centos64.tgz -C /opt/ +``` + +### 烧写工具 + +ARM：ST-LINK NU-LINK + +RISC-V：K-FLash + +**每种开发板分别对应board目录下的一个文件夹，具体编译及烧录步骤请参见board目录下对应文件夹下的README文件。** diff --git a/Ubiquitous/XiZi/arch/Kconfig b/Ubiquitous/XiZi/arch/Kconfig new file mode 100644 index 0000000..42e27ec --- /dev/null +++ b/Ubiquitous/XiZi/arch/Kconfig @@ -0,0 +1,13 @@ +config ARCH_CPU_64BIT + bool + +config ARCH_RISCV + bool + +config ARCH_ARM + bool + +config ARCH_RISCV64 + select ARCH_RISCV + select ARCH_CPU_64BIT + bool \ No newline at end of file diff --git a/Ubiquitous/XiZi/arch/Makefile b/Ubiquitous/XiZi/arch/Makefile new file mode 100644 index 0000000..f629b85 --- /dev/null +++ b/Ubiquitous/XiZi/arch/Makefile @@ -0,0 +1,3 @@ +SRC_DIR := $(ARCH) + +include $(KERNEL_ROOT)/compiler.mk diff --git a/Ubiquitous/XiZi/arch/arm/Makefile b/Ubiquitous/XiZi/arch/arm/Makefile new file mode 100644 index 0000000..4deddfc --- /dev/null +++ b/Ubiquitous/XiZi/arch/arm/Makefile @@ -0,0 +1,38 @@ +# The following three platforms support compatiable instructions. + +ifeq ($(CONFIG_BOARD_CORTEX_M3_EVB),y) +SRC_DIR := shared +SRC_DIR += cortex-m3 +endif + +ifeq ($(CONFIG_BOARD_STM32F103_NANO),y) +SRC_DIR := shared +SRC_DIR += cortex-m3 +endif + +ifeq ($(CONFIG_BOARD_STM32F407_EVB),y) +SRC_DIR := shared +SRC_DIR += cortex-m4 +endif + +ifeq ($(CONFIG_BOARD_CORTEX_M4_EVB),y) +SRC_DIR := shared +SRC_DIR += cortex-m4 +endif + +ifeq ($(CONFIG_BOARD_CORTEX_M7_EVB),y) +SRC_DIR := shared +SRC_DIR += cortex-m7 +endif + +# cortex-m0 is ARMv6-m + +ifeq ($(CONFIG_BOARD_CORTEX_M0_EVB),y) +SRC_DIR += cortex-m0 +endif + +ifeq ($(CONFIG_BOARD_NUVOTON_M2354),y) +SRC_DIR += cortex-m23 +endif + +include $(KERNEL_ROOT)/compiler.mk diff --git a/Ubiquitous/XiZi/arch/arm/cortex-m0/Makefile b/Ubiquitous/XiZi/arch/arm/cortex-m0/Makefile new file mode 100644 index 0000000..fb37619 --- /dev/null +++ b/Ubiquitous/XiZi/arch/arm/cortex-m0/Makefile @@ -0,0 +1,3 @@ +SRC_FILES := boot.c interrupt.c interrupt_vector.S pendsv.S prepare_ahwstack.c arm32_switch.c + +include $(KERNEL_ROOT)/compiler.mk diff --git a/Ubiquitous/XiZi/arch/arm/cortex-m0/arch_interrupt.h b/Ubiquitous/XiZi/arch/arm/cortex-m0/arch_interrupt.h new file mode 100644 index 0000000..cfbb082 --- /dev/null +++ b/Ubiquitous/XiZi/arch/arm/cortex-m0/arch_interrupt.h @@ -0,0 +1,28 @@ +/* +* Copyright (c) 2020 AIIT XUOS Lab +* XiUOS is licensed under Mulan PSL v2. +* You can use this software according to the terms and conditions of the Mulan PSL v2. +* You may obtain a copy of Mulan PSL v2 at: +* http://license.coscl.org.cn/MulanPSL2 +* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, +* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, +* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. +* See the Mulan PSL v2 for more details. +*/ + +#ifndef ARCH_INTERRUPT_H__ +#define ARCH_INTERRUPT_H__ + +#include + +#define ARCH_MAX_IRQ_NUM (48) + +#define ARCH_IRQ_NUM_OFFSET 0 + +#define SYSTICK_IRQN 15 +#define UART1_IRQn 18 + +int32 ArchEnableHwIrq(uint32 irq_num); +int32 ArchDisableHwIrq(uint32 irq_num); + +#endif diff --git a/Ubiquitous/XiZi/arch/arm/cortex-m0/arm32_switch.c b/Ubiquitous/XiZi/arch/arm/cortex-m0/arm32_switch.c new file mode 100644 index 0000000..a35ad27 --- /dev/null +++ b/Ubiquitous/XiZi/arch/arm/cortex-m0/arm32_switch.c @@ -0,0 +1,241 @@ +/* +* Copyright (c) 2020 AIIT XUOS Lab +* XiUOS is licensed under Mulan PSL v2. +* You can use this software according to the terms and conditions of the Mulan PSL v2. +* You may obtain a copy of Mulan PSL v2 at: +* http://license.coscl.org.cn/MulanPSL2 +* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, +* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, +* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. +* See the Mulan PSL v2 for more details. +*/ + +#include +#include + +#define SCB_VTOR "0xE000ED08" +#define NVIC_INT_CTRL "0xE000ED04" +#define NVIC_SYSPRI2 "0xE000ED20" +#define NVIC_PENDSV_PRI "0x00FF0000" +#define NVIC_PENDSVSET "0x10000000" + +/* We replaced instructions that were not supported in thumb mode. */ + +void __attribute__((naked)) HwInterruptcontextSwitch(x_ubase from, x_ubase to, struct TaskDescriptor *to_task, void *context) +{ + asm volatile ("PUSH {R4}"); + asm volatile ("PUSH {R5}"); + + asm volatile ("LDR r4, =KtaskSwitchInterruptFlag"); + asm volatile ("LDR r5, [r4]"); + asm volatile ("CMP r5, #1"); + + asm volatile ("POP {R5}"); + asm volatile ("POP {R4}"); + + asm volatile ("BEQ Arm32SwitchReswitch"); + + asm volatile ("PUSH {R4}"); + asm volatile ("PUSH {R5}"); + asm volatile ("LDR r4, =KtaskSwitchInterruptFlag"); + + asm volatile ("MOV r5, #1"); + asm volatile ("STR r5, [r4]"); + asm volatile ("LDR r4, =InterruptFromKtask"); + asm volatile ("STR r0, [r4]"); + + asm volatile ("POP {R5}"); + asm volatile ("POP {R4}"); + + asm volatile ("B Arm32SwitchReswitch"); +} + +void __attribute__((naked)) Arm32SwitchReswitch() +{ + asm volatile ("PUSH {R4}"); + asm volatile ("LDR r4, =InterruptToKtask"); + asm volatile ("STR r1, [r4]"); + asm volatile ("LDR r4, =InterruptToKtaskDescriptor"); + asm volatile ("STR r2, [r4]"); + asm volatile ("LDR r0, =" NVIC_INT_CTRL); + asm volatile ("LDR r1, =" NVIC_PENDSVSET); + asm volatile ("STR r1, [r0]"); + asm volatile ("POP {R4}"); + asm volatile ("BX LR"); +} + +void __attribute__((naked)) SwitchKtaskContext(x_ubase from, x_ubase to, struct TaskDescriptor *to_task) +{ + asm volatile("B HwInterruptcontextSwitch"); +} + +void SwitchKtaskContextTo(x_ubase to, struct TaskDescriptor *to_task) +{ + asm volatile ("LDR r2, =InterruptToKtask"); + asm volatile ("STR r0, [r2]"); + asm volatile ("LDR r2, =InterruptToKtaskDescriptor"); + asm volatile ("STR r1, [r2]"); +#if defined (__VFP_FP__) && !defined(__SOFTFP__) + asm volatile ("MRS r2, CONTROL"); + asm volatile ("BIC r2, #0x04"); + asm volatile ("MSR CONTROL, r2"); +#endif + asm volatile ("LDR r1, =InterruptFromKtask"); + asm volatile ("MOV r0, #0x0"); + asm volatile ("STR r0, [r1]"); + asm volatile ("LDR r1, =KtaskSwitchInterruptFlag"); + asm volatile ("MOV r0, #1"); + asm volatile ("STR r0, [r1]"); + asm volatile ("LDR r0, =" NVIC_SYSPRI2); + asm volatile ("LDR r1, =" NVIC_PENDSV_PRI); + // asm volatile ("LDR.W r2, [r0,#0x00]"); + asm volatile ("LDR r2, [r0,#0x00]"); + asm volatile ("ORR r1,r1,r2"); + asm volatile ("STR r1, [r0]"); + asm volatile ("LDR r0, =" NVIC_INT_CTRL); + asm volatile ("LDR r1, =" NVIC_PENDSVSET); + asm volatile ("STR r1, [r0]"); + asm volatile ("LDR r0, =" SCB_VTOR); + asm volatile ("LDR r0, [r0]"); + asm volatile ("LDR r0, [r0]"); + asm volatile ("NOP"); + asm volatile ("MSR msp, r0"); + asm volatile ("CPSIE F"); + asm volatile ("CPSIE I"); + asm volatile ("BX lr"); +} + +void __attribute__((naked)) HardFaultHandler() +{ + asm volatile ("MRS r0, msp"); + + // asm volatile ("TST lr, #0x04"); + asm volatile ("MOV r1, lr"); + asm volatile ("MOV r2, #0x04"); + asm volatile ("TST r1, r2"); + + asm volatile ("BEQ Arm32SwitchGetSpDone"); + asm volatile ("MRS r0, psp"); + asm volatile ("B Arm32SwitchGetSpDone"); +} + +void __attribute__((naked)) Arm32SwitchGetSpDone() +{ + asm volatile ("MRS r3, primask"); + + // asm volatile ("STMFD r0!, {r3 - r11}"); + asm volatile ("SUB r0, r0, #0x24"); + asm volatile ("STMIA r0!, {r3 - r7}"); + asm volatile ("MOV r3, r8"); + asm volatile ("MOV r4, r9"); + asm volatile ("MOV r5, r10"); + asm volatile ("MOV r6, r11"); + asm volatile ("STMIA r0!, {r3 - r6}"); + asm volatile ("SUB r0, r0, #0x24"); + + // asm volatile ("STMFD r0!, {lr}"); + asm volatile ("SUB r0, r0, #0x4"); + asm volatile ("MOV r0, lr"); +#if defined (__VFP_FP__) && !defined(__SOFTFP__) + asm volatile ("MOV r4, #0x00"); + // asm volatile ("TST lr, #0x10"); + asm volatile ("MOV r1, lr"); + asm volatile ("MOV r2, #0x10"); + asm volatile ("TST r1, r2"); + + asm volatile ("MOVEQ r4, #0x01"); + asm volatile ("STMFD r0!, {r4}"); +#endif + // asm volatile ("TST lr, #0x04"); + asm volatile ("MOV r1, lr"); + asm volatile ("MOV r2, #0x04"); + asm volatile ("TST r1, r2"); + + asm volatile ("BEQ Arm32SwitchUpdateMsp"); + asm volatile ("MSR psp, r0"); + asm volatile ("B Arm32SwitchUpdateDone"); + asm volatile ("B Arm32SwitchUpdateMsp"); +} + +void __attribute__((naked)) Arm32SwitchUpdateMsp() +{ + asm volatile ("MSR msp, r0"); + asm volatile ("B Arm32SwitchUpdateDone"); +} + +void __attribute__((naked)) Arm32SwitchUpdateDone() +{ + asm volatile ("PUSH {LR}"); + asm volatile ("BL HwHardFaultException"); + + // asm volatile ("POP {LR}"); + asm volatile ("POP {R1}"); + asm volatile ("MOV lr, r1"); + + // asm volatile ("ORR lr, lr, #0x04"); + asm volatile ("MOV r1, lr"); + asm volatile ("MOV r2, #0x04"); + asm volatile ("ORR r1, r2"); + asm volatile ("MOV lr, r1"); + + asm volatile ("BX lr"); +} + +void __attribute__((naked)) MemFaultHandler() +{ + asm volatile ("MRS r0, msp"); + + // asm volatile ("TST lr, #0x04"); + asm volatile ("MOV r1, lr"); + asm volatile ("MOV r2, #0x04"); + asm volatile ("TST r1, r2"); + + asm volatile ("BEQ Arm32Switch1"); + asm volatile ("MRS r0, psp"); + asm volatile ("B Arm32Switch1"); +} + +void __attribute__((naked)) Arm32Switch1() +{ + asm volatile ("MRS r3, primask"); + + // asm volatile ("STMFD r0!, {r3 - r11}"); + asm volatile ("SUB r0, r0, #0x24"); + asm volatile ("STMIA r0!, {r3 - r7}"); + asm volatile ("MOV r3, r8"); + asm volatile ("MOV r4, r9"); + asm volatile ("MOV r5, r10"); + asm volatile ("MOV r6, r11"); + asm volatile ("STMIA r0!, {r3 - r6}"); + asm volatile ("SUB r0, r0, #0x24"); + +#if defined (__VFP_FP__) && !defined(__SOFTFP__) + asm volatile ("MOV r4, #0x00"); + // asm volatile ("TST lr, #0x10"); + asm volatile ("MOV r1, lr"); + asm volatile ("MOV r2, #0x10"); + asm volatile ("TST r1, r2"); + asm volatile ("MOV lr, r1"); + + asm volatile ("MOVEQ r4, #0x01"); + asm volatile ("STMFD r0!, {r4}"); +#endif + // asm volatile ("STMFD r0!, {lr}"); + asm volatile ("SUB r0, r0, #0x4"); + asm volatile ("MOV r0, lr"); + + asm volatile ("PUSH {LR}"); + asm volatile ("BL MemFaultHandle"); + + // asm volatile ("POP {LR}"); + asm volatile ("POP {R5}"); + asm volatile ("MOV lr, r5"); + + // asm volatile ("ORR lr, lr, #0x04"); + asm volatile ("MOV r5, lr"); + asm volatile ("MOV r6, #0x04"); + asm volatile ("ORR r5, r6"); + asm volatile ("MOV lr, r5"); + + asm volatile ("BX lr"); +} diff --git a/Ubiquitous/XiZi/arch/arm/cortex-m0/interrupt.c b/Ubiquitous/XiZi/arch/arm/cortex-m0/interrupt.c new file mode 100644 index 0000000..5a97255 --- /dev/null +++ b/Ubiquitous/XiZi/arch/arm/cortex-m0/interrupt.c @@ -0,0 +1,83 @@ +/* +* Copyright (c) 2020 AIIT XUOS Lab +* XiUOS is licensed under Mulan PSL v2. +* You can use this software according to the terms and conditions of the Mulan PSL v2. +* You may obtain a copy of Mulan PSL v2 at: +* http://license.coscl.org.cn/MulanPSL2 +* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, +* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, +* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. +* See the Mulan PSL v2 for more details. +*/ + +/** +* @file interrupt.c +* @brief support arm cortex-m0 interrupt function +* @version 1.0 +* @author AIIT XUOS Lab +* @date 2021-04-29 +*/ + +#include +#include + + +x_base __attribute__((naked)) DisableLocalInterrupt() +{ + asm volatile ("MRS r0, PRIMASK"); + asm volatile ("CPSID I"); + asm volatile ("BX LR "); +} + +void __attribute__((naked)) EnableLocalInterrupt(x_base level) +{ + asm volatile ("MSR PRIMASK, r0"); + asm volatile ("BX LR"); +} + +int32 ArchEnableHwIrq(uint32 irq_num) +{ + return EOK; +} + +int32 ArchDisableHwIrq(uint32 irq_num) +{ + return EOK; +} + +extern void KTaskOsAssignAfterIrq(void *context); + +void IsrEntry() +{ + uint32 ipsr; + + __asm__ volatile("MRS %0, IPSR" : "=r"(ipsr)); + + isrManager.done->incCounter(); + isrManager.done->handleIrq(ipsr); + KTaskOsAssignAfterIrq(NONE); + isrManager.done->decCounter(); +} + +void UsageFault_Handler(int irqn, void *arg) +{ + /* Go to infinite loop when Usage Fault exception occurs */ + while (1) + { + } +} + +void BusFault_Handler(int irqn, void *arg) +{ + /* Go to infinite loop when Bus Fault exception occurs */ + while (1) + { + } +} + +void NMI_Handler(int irqn, void *arg) +{ + while (1) + { + } +} diff --git a/Ubiquitous/XiZi/arch/arm/cortex-m0/prepare_ahwstack.c b/Ubiquitous/XiZi/arch/arm/cortex-m0/prepare_ahwstack.c new file mode 100644 index 0000000..6b59782 --- /dev/null +++ b/Ubiquitous/XiZi/arch/arm/cortex-m0/prepare_ahwstack.c @@ -0,0 +1,411 @@ +/* +* Copyright (c) 2020 AIIT XUOS Lab +* XiUOS is licensed under Mulan PSL v2. +* You can use this software according to the terms and conditions of the Mulan PSL v2. +* You may obtain a copy of Mulan PSL v2 at: +* http://license.coscl.org.cn/MulanPSL2 +* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, +* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, +* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. +* See the Mulan PSL v2 for more details. +*/ + +#include +#include +#include +#include "svc_handle.h" +#include +#include + +#if (defined ( __GNUC__ ) && defined ( __VFP_FP__ ) && !defined(__SOFTFP__)) +#define USE_FPU 1 +#else +#define USE_FPU 0 +#endif + +uint32 InterruptFromKtask; +uint32 InterruptToKtask; +uint32 KtaskSwitchInterruptFlag; +uint32 InterruptToKtaskDescriptor; +#define RunningKTask Assign.os_running_task + +static x_err_t (*ExceptionHook)(void *context) = NONE; + +struct ExceptionStackRegister +{ + uint32 r0; + uint32 r1; + uint32 r2; + uint32 r3; + uint32 r12; + uint32 lr; + uint32 pc; + uint32 psr; +}; + +struct StackRegisterContent +{ +#if defined ( __VFP_FP__ ) && !defined(__SOFTFP__) + uint32 flag; +#endif + uint32 primask; + uint32 r4; + uint32 r5; + uint32 r6; + uint32 r7; + uint32 r8; + uint32 r9; + uint32 r10; + uint32 r11; + // uint32 exc_ret; + + struct ExceptionStackRegister ExErrorStackContex; +}; + +struct ExceptionStackFrameFpu +{ + uint32 r0; + uint32 r1; + uint32 r2; + uint32 r3; + uint32 r12; + uint32 lr; + uint32 pc; + uint32 psr; + +#if USE_FPU + uint32 S0; + uint32 S1; + uint32 S2; + uint32 S3; + uint32 S4; + uint32 S5; + uint32 S6; + uint32 S7; + uint32 S8; + uint32 S9; + uint32 S10; + uint32 S11; + uint32 S12; + uint32 S13; + uint32 S14; + uint32 S15; + uint32 FPSCR; + uint32 NO_NAME; +#endif +}; + +struct StackFrameFpu +{ + uint32 flag; + + uint32 r4; + uint32 r5; + uint32 r6; + uint32 r7; + uint32 r8; + uint32 r9; + uint32 r10; + uint32 r11; + +#if USE_FPU + uint32 s16; + uint32 s17; + uint32 s18; + uint32 s19; + uint32 s20; + uint32 s21; + uint32 s22; + uint32 s23; + uint32 s24; + uint32 s25; + uint32 s26; + uint32 s27; + uint32 s28; + uint32 s29; + uint32 s30; + uint32 s31; +#endif + + struct ExceptionStackFrameFpu ExErrorStackContex; +}; + +uint8 KTaskStackSetup(struct TaskDescriptor *task) +{ + struct StackRegisterContent* StackContex; + int i = 0; + + task->stack_point = (uint8 *)ALIGN_MEN_DOWN((x_ubase)(task->task_base_info.stack_start + task->task_base_info.stack_depth), 8); + task->stack_point -= sizeof(struct StackRegisterContent); + + StackContex = (struct StackRegisterContent*)task->stack_point; + + for (i = 0; i < sizeof(struct StackRegisterContent) / sizeof(uint32); i++) + ((uint32 *)StackContex)[i] = 0xfadeface; + + StackContex->ExErrorStackContex.r0 = (unsigned long)task->task_base_info.func_param; + + StackContex->ExErrorStackContex.pc = (unsigned long)task->task_base_info.func_entry ; + StackContex->ExErrorStackContex.psr = 0x01000000L; + StackContex->primask = 0x00000000L; +#ifdef SEPARATE_COMPILE + if(task->task_dync_sched_member.isolation_flag == 1 ) { + StackContex->ExErrorStackContex.lr = (unsigned long)USERSPACE->us_taskquit; + } else { + StackContex->ExErrorStackContex.lr = (unsigned long)KTaskQuit; + } +#else + StackContex->ExErrorStackContex.lr = (unsigned long)KTaskQuit; +#endif + +#if USE_FPU + StackContex->flag = 0; +#endif + + return EOK; +} + + +void HwExceptionInstall(x_err_t (*exception_handle)(void *context)) +{ + ExceptionHook = exception_handle; +} + +#define SCB_CFSR (*(volatile const unsigned *)0xE000ED28) +#define SCB_HFSR (*(volatile const unsigned *)0xE000ED2C) +#define SCB_MMAR (*(volatile const unsigned *)0xE000ED34) +#define SCB_BFAR (*(volatile const unsigned *)0xE000ED38) +#define SCB_AIRCR (*(volatile unsigned long *)0xE000ED0C) +#define SCB_RESET_VALUE 0x05FA0004 + +#define SCB_CFSR_MFSR (*(volatile const unsigned char*)0xE000ED28) +#define SCB_CFSR_BFSR (*(volatile const unsigned char*)0xE000ED29) +#define SCB_CFSR_UFSR (*(volatile const unsigned short*)0xE000ED2A) + +#ifdef TOOL_SHELL +static void UsageFaultTrack(void) +{ + KPrintf("usage fault:\n"); + KPrintf("SCB_CFSR_UFSR:0x%02X ", SCB_CFSR_UFSR); + + if(SCB_CFSR_UFSR & (1<<0)) + KPrintf("UNDEFINSTR "); + + if(SCB_CFSR_UFSR & (1<<1)) + KPrintf("INVSTATE "); + + if(SCB_CFSR_UFSR & (1<<2)) + KPrintf("INVPC "); + + if(SCB_CFSR_UFSR & (1<<3)) + KPrintf("NOCP "); + + if(SCB_CFSR_UFSR & (1<<8)) + KPrintf("UNALIGNED "); + + if(SCB_CFSR_UFSR & (1<<9)) + KPrintf("DIVBYZERO "); + + KPrintf("\n"); +} + +static void BusFaultTrack(void) +{ + KPrintf("bus fault:\n"); + KPrintf("SCB_CFSR_BFSR:0x%02X ", SCB_CFSR_BFSR); + + if(SCB_CFSR_BFSR & (1<<0)) + KPrintf("IBUSERR "); + + if(SCB_CFSR_BFSR & (1<<1)) + KPrintf("PRECISERR "); + + if(SCB_CFSR_BFSR & (1<<2)) + KPrintf("IMPRECISERR "); + + if(SCB_CFSR_BFSR & (1<<3)) + KPrintf("UNSTKERR "); + + if(SCB_CFSR_BFSR & (1<<4)) + KPrintf("STKERR "); + + if(SCB_CFSR_BFSR & (1<<7)) + KPrintf("SCB->BFAR:%08X\n", SCB_BFAR); + else + KPrintf("\n"); +} + +static void MemManageFaultTrack(void) +{ + KPrintf("mem manage fault:\n"); + KPrintf("SCB_CFSR_MFSR:0x%02X ", SCB_CFSR_MFSR); + + if(SCB_CFSR_MFSR & (1<<0)) + KPrintf("IACCVIOL "); + if(SCB_CFSR_MFSR & (1<<1)) + KPrintf("DACCVIOL "); + + if(SCB_CFSR_MFSR & (1<<3)) + KPrintf("MUNSTKERR "); + + if(SCB_CFSR_MFSR & (1<<4)) + KPrintf("MSTKERR "); + + if(SCB_CFSR_MFSR & (1<<7)) + KPrintf("SCB->MMAR:%08X\n", SCB_MMAR); + else + KPrintf("\n"); +} + +static void HardFaultTrack(void) +{ + if(SCB_HFSR & (1UL<<1)) + KPrintf("failed vector fetch\n"); + + if(SCB_HFSR & (1UL<<30)) { + if(SCB_CFSR_BFSR) + BusFaultTrack(); + + if(SCB_CFSR_MFSR) + MemManageFaultTrack(); + + if(SCB_CFSR_UFSR) + UsageFaultTrack(); + } + + if(SCB_HFSR & (1UL<<31)) + KPrintf("debug event\n"); +} +#endif + +struct ExceptionInfo +{ + uint32 ExcReturn; + struct StackRegisterContent stackframe; +}; + +void HwHardFaultException(struct ExceptionInfo *ExceptionInfo) +{ + extern long ShowTask(void); + struct ExErrorStackContex* ExceptionStack = (struct ExErrorStackContex*)&ExceptionInfo->stackframe.ExErrorStackContex; + struct StackRegisterContent* context = (struct StackRegisterContent*)&ExceptionInfo->stackframe; + + if (ExceptionHook != NONE) { + x_err_t result = ExceptionHook(ExceptionStack); + if (result == EOK) return; + } + + KPrintf("psr: 0x%08x\n", context->ExErrorStackContex.psr); + KPrintf("r00: 0x%08x\n", context->ExErrorStackContex.r0); + KPrintf("r01: 0x%08x\n", context->ExErrorStackContex.r1); + KPrintf("r02: 0x%08x\n", context->ExErrorStackContex.r2); + KPrintf("r03: 0x%08x\n", context->ExErrorStackContex.r3); + KPrintf("r04: 0x%08x\n", context->r4); + KPrintf("r05: 0x%08x\n", context->r5); + KPrintf("r06: 0x%08x\n", context->r6); + KPrintf("r07: 0x%08x\n", context->r7); + KPrintf("r08: 0x%08x\n", context->r8); + KPrintf("r09: 0x%08x\n", context->r9); + KPrintf("r10: 0x%08x\n", context->r10); + KPrintf("r11: 0x%08x\n", context->r11); + //KPrintf("exc_ret: 0x%08x\n", context->exc_ret); + KPrintf("r12: 0x%08x\n", context->ExErrorStackContex.r12); + KPrintf(" lr: 0x%08x\n", context->ExErrorStackContex.lr); + KPrintf(" pc: 0x%08x\n", context->ExErrorStackContex.pc); + + if (ExceptionInfo->ExcReturn & (1 << 2)) { + KPrintf("hard fault on task: %s\r\n\r\n", GetKTaskDescriptor()->task_base_info.name); +#ifdef TOOL_SHELL + ShowTask(); +#endif + } else { + KPrintf("hard fault on handler\r\n\r\n"); + } + + if ( (ExceptionInfo->ExcReturn & 0x10) == 0) + KPrintf("FPU active!\r\n"); + +#ifdef TOOL_SHELL + HardFaultTrack(); +#endif + + while (1); +} + +void UpdateRunningTask(void) +{ + RunningKTask = (struct TaskDescriptor *)InterruptToKtaskDescriptor; +} + + +void MemFaultExceptionPrint(struct ExceptionInfo *ExceptionInfo) +{ + extern long ShowTask(void); + struct ExErrorStackContex* ExceptionStack = (struct ExErrorStackContex*)&ExceptionInfo->stackframe.ExErrorStackContex; + struct StackRegisterContent* context = (struct StackRegisterContent*)&ExceptionInfo->stackframe; + + if (ExceptionHook != NONE) { + x_err_t result = ExceptionHook(ExceptionStack); + if (result == EOK) return; + } + + KPrintf("psr: 0x%08x\n", context->ExErrorStackContex.psr); + KPrintf("r00: 0x%08x\n", context->ExErrorStackContex.r0); + KPrintf("r01: 0x%08x\n", context->ExErrorStackContex.r1); + KPrintf("r02: 0x%08x\n", context->ExErrorStackContex.r2); + KPrintf("r03: 0x%08x\n", context->ExErrorStackContex.r3); + KPrintf("r04: 0x%08x\n", context->r4); + KPrintf("r05: 0x%08x\n", context->r5); + KPrintf("r06: 0x%08x\n", context->r6); + KPrintf("r07: 0x%08x\n", context->r7); + KPrintf("r08: 0x%08x\n", context->r8); + KPrintf("r09: 0x%08x\n", context->r9); + KPrintf("r10: 0x%08x\n", context->r10); + KPrintf("r11: 0x%08x\n", context->r11); + KPrintf("exc_ret: 0x%08x\n", ExceptionInfo->ExcReturn); + KPrintf("r12: 0x%08x\n", context->ExErrorStackContex.r12); + KPrintf(" lr: 0x%08x\n", context->ExErrorStackContex.lr); + KPrintf(" pc: 0x%08x\n", context->ExErrorStackContex.pc); + + if (ExceptionInfo->ExcReturn & (1 << 2)) { + KPrintf("hard fault on task: %s\r\n\r\n", GetKTaskDescriptor()->task_base_info.name); +#ifdef TOOL_SHELL + ShowTask(); +#endif + } else { + KPrintf("hard fault on handler\r\n\r\n"); + } + + if ((ExceptionInfo->ExcReturn & 0x10) == 0) + KPrintf("FPU active!\r\n"); + + +#ifdef TOOL_SHELL + HardFaultTrack(); +#endif + + while (1); +} + +void MemFaultHandle(uintptr_t *sp) +{ +#ifdef TASK_ISOLATION + struct TaskDescriptor *task; + task = GetKTaskDescriptor(); + if( task->task_dync_sched_member.isolation_flag == 1){ + KPrintf("\nSegmentation fault, task: %s\n", task->task_base_info.name); + KTaskQuit(); + } + else +#endif + { + MemFaultExceptionPrint((struct ExceptionInfo *)sp); + } + +} + +__attribute__((weak)) void HwCpuReset(void) +{ + SCB_AIRCR = SCB_RESET_VALUE; +} +SHELL_EXPORT_CMD(SHELL_CMD_PERMISSION(0)|SHELL_CMD_TYPE(SHELL_TYPE_CMD_FUNC)|SHELL_CMD_PARAM_NUM(0), Reboot, HwCpuReset, reset machine ); \ No newline at end of file diff --git a/Ubiquitous/XiZi/arch/arm/cortex-m0/svc_handle.h b/Ubiquitous/XiZi/arch/arm/cortex-m0/svc_handle.h new file mode 100644 index 0000000..1822417 --- /dev/null +++ b/Ubiquitous/XiZi/arch/arm/cortex-m0/svc_handle.h @@ -0,0 +1,58 @@ +/* +* Copyright (c) 2020 AIIT XUOS Lab +* XiUOS is licensed under Mulan PSL v2. +* You can use this software according to the terms and conditions of the Mulan PSL v2. +* You may obtain a copy of Mulan PSL v2 at: +* http://license.coscl.org.cn/MulanPSL2 +* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, +* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, +* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. +* See the Mulan PSL v2 for more details. +*/ + +#ifndef __INC_SVC_HANDLE_H__ +#define __INC_SVC_HANDLE_H__ + +#if defined ( __VFP_FP__ ) && !defined(__SOFTFP__) +#define INT_FPU_REGS (1) +#else +#define INT_FPU_REGS (0) +#endif + +#define HW_INT_REGS (8) +#define SW_INT_REGS (9 + INT_FPU_REGS) + +#define REG_INT_R0 (SW_INT_REGS + 0) /* R0 */ +#define REG_INT_R1 (SW_INT_REGS + 1) /* R1 */ +#define REG_INT_R2 (SW_INT_REGS + 2) /* R2 */ +#define REG_INT_R3 (SW_INT_REGS + 3) /* R3 */ +#define REG_INT_R12 (SW_INT_REGS + 4) /* R12 */ +#define REG_INT_R14 (SW_INT_REGS + 5) /* R14 = LR */ +#define REG_INT_PC (SW_INT_REGS + 6) /* R15 = PC */ +#define REG_INT_XPSR (SW_INT_REGS + 7) /* xPSR */ + +#if defined ( __VFP_FP__ ) && !defined(__SOFTFP__) +#define REG_INT_FPU_FLAG (0) /* fpu flag */ +#define REG_INT_PRIMASK (1) /* PRIMASK */ +#define REG_INT_R4 (2) /* R4 */ +#define REG_INT_R5 (3) /* R5 */ +#define REG_INT_R6 (4) /* R6 */ +#define REG_INT_R7 (5) /* R7 */ +#define REG_INT_R8 (6) /* R8 */ +#define REG_INT_R9 (7) /* R9 */ +#define REG_INT_R10 (8) /* R10 */ +#define REG_INT_R11 (9) /* R11 */ +#else +#define REG_INT_PRIMASK (0) /* PRIMASK */ +#define REG_INT_R4 (1) /* R4 */ +#define REG_INT_R5 (2) /* R5 */ +#define REG_INT_R6 (3) /* R6 */ +#define REG_INT_R7 (4) /* R7 */ +#define REG_INT_R8 (5) /* R8 */ +#define REG_INT_R9 (6) /* R9 */ +#define REG_INT_R10 (7) /* R10 */ +#define REG_INT_R11 (8) /* R11 */ +#endif + + +#endif diff --git a/Ubiquitous/XiZi/arch/arm/cortex-m23/Makefile b/Ubiquitous/XiZi/arch/arm/cortex-m23/Makefile new file mode 100644 index 0000000..0ab93c0 --- /dev/null +++ b/Ubiquitous/XiZi/arch/arm/cortex-m23/Makefile @@ -0,0 +1,3 @@ +SRC_FILES := boot.S interrupt.c interrupt_vector.S pendsv.S prepare_ahwstack.c arm32_switch.c + +include $(KERNEL_ROOT)/compiler.mk diff --git a/Ubiquitous/XiZi/arch/arm/cortex-m23/arch_interrupt.h b/Ubiquitous/XiZi/arch/arm/cortex-m23/arch_interrupt.h new file mode 100644 index 0000000..97a212b --- /dev/null +++ b/Ubiquitous/XiZi/arch/arm/cortex-m23/arch_interrupt.h @@ -0,0 +1,28 @@ +/* +* Copyright (c) 2020 AIIT XUOS Lab +* XiUOS is licensed under Mulan PSL v2. +* You can use this software according to the terms and conditions of the Mulan PSL v2. +* You may obtain a copy of Mulan PSL v2 at: +* http://license.coscl.org.cn/MulanPSL2 +* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, +* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, +* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. +* See the Mulan PSL v2 for more details. +*/ + +#ifndef ARCH_INTERRUPT_H__ +#define ARCH_INTERRUPT_H__ + +#include + +#define ARCH_MAX_IRQ_NUM (256) + +#define ARCH_IRQ_NUM_OFFSET 14 + +#define SYSTICK_IRQ_NUM -1 +#define UART0_IRQ_NUM 36 + +int32 ArchEnableHwIrq(uint32 irq_num); +int32 ArchDisableHwIrq(uint32 irq_num); + +#endif diff --git a/Ubiquitous/XiZi/arch/arm/cortex-m23/arm32_switch.c b/Ubiquitous/XiZi/arch/arm/cortex-m23/arm32_switch.c new file mode 100644 index 0000000..e6c97d8 --- /dev/null +++ b/Ubiquitous/XiZi/arch/arm/cortex-m23/arm32_switch.c @@ -0,0 +1,179 @@ +/* +* Copyright (c) 2020 AIIT XUOS Lab +* XiUOS is licensed under Mulan PSL v2. +* You can use this software according to the terms and conditions of the Mulan PSL v2. +* You may obtain a copy of Mulan PSL v2 at: +* http://license.coscl.org.cn/MulanPSL2 +* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, +* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, +* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. +* See the Mulan PSL v2 for more details. +*/ + +#include +#include + +#define SCB_VTOR "0xE000ED08" +#define NVIC_INT_CTRL "0xE000ED04" +#define NVIC_SYSPRI2 "0xE000ED20" +#define NVIC_PENDSV_PRI "0xFFFF0000" +#define NVIC_PENDSVSET "0x10000000" + +void __attribute__((naked)) HwInterruptcontextSwitch(x_ubase from, x_ubase to, struct TaskDescriptor *to_task, void *context) +{ + asm volatile ("LDR r3, =InterruptFromKtask"); + asm volatile ("STR r0, [r3]"); + asm volatile ("LDR r3, =InterruptToKtask"); + asm volatile ("STR r1, [r3]"); + asm volatile ("LDR r3, =InterruptToKtaskDescriptor"); + asm volatile ("STR r2, [r3]"); + + asm volatile ("LDR r2, =KtaskSwitchInterruptFlag"); + asm volatile ("LDR r3, [r2]"); + asm volatile ("CMP r3, #1"); + + asm volatile ("BEQ Arm32SwitchReswitch"); + + asm volatile ("MOVS r3, #1"); + asm volatile ("STR r3, [r2]"); + + asm volatile ("B Arm32SwitchReswitch"); +} + +void __attribute__((naked)) Arm32SwitchReswitch() +{ + asm volatile ("LDR r2, =InterruptToKtask"); + asm volatile ("STR r1, [r2]"); + + asm volatile ("LDR r0, =" NVIC_INT_CTRL);/* trigger the PendSV exception (causes context switch) */ + asm volatile ("LDR r1, =" NVIC_PENDSVSET); + asm volatile ("STR r1, [r0]"); + asm volatile ("BX lr"); +} + +void __attribute__((naked)) SwitchKtaskContext(x_ubase from, x_ubase to, struct TaskDescriptor *to_task) +{ + asm volatile("B HwInterruptcontextSwitch"); +} + +void SwitchKtaskContextTo(x_ubase to, struct TaskDescriptor *to_task) +{ + asm volatile ("LDR r2, =InterruptToKtask"); + asm volatile ("STR r0, [r2]"); + asm volatile ("LDR r2, =InterruptToKtaskDescriptor"); + asm volatile ("STR r1, [r2]"); + + asm volatile ("LDR r1, =InterruptFromKtask"); + asm volatile ("MOV r0, #0x0"); + asm volatile ("STR r0, [r1]"); + asm volatile ("LDR r1, =KtaskSwitchInterruptFlag"); + asm volatile ("MOV r0, #1"); + asm volatile ("STR r0, [r1]"); + asm volatile ("LDR r0, =" NVIC_SYSPRI2); + asm volatile ("LDR r1, =" NVIC_PENDSV_PRI); + asm volatile ("LDR r2, [r0,#0x00]"); + asm volatile ("ORR r1,r1,r2"); + asm volatile ("STR r1, [r0]"); + asm volatile ("LDR r0, =" NVIC_INT_CTRL); + asm volatile ("LDR r1, =" NVIC_PENDSVSET); + asm volatile ("STR r1, [r0]"); + asm volatile ("LDR r0, =" SCB_VTOR); + asm volatile ("LDR r0, [r0]"); + asm volatile ("LDR r0, [r0]"); + asm volatile ("NOP"); + asm volatile ("MSR msp, r0"); + asm volatile ("CPSIE I"); + //asm volatile ("BX lr"); +} + +void __attribute__((naked)) Arm32SwitchGetSpDone() +{ + asm volatile ("MRS r3, primask"); + + asm volatile ("SUB r0, r0, #0x24"); + asm volatile ("STMIA r0!, {r3 - r7}"); + asm volatile ("MOV r3, r8"); + asm volatile ("MOV r4, r9"); + asm volatile ("MOV r5, r10"); + asm volatile ("MOV r6, r11"); + asm volatile ("STMIA r0!, {r3 - r6}"); + asm volatile ("SUB r0, r0, #0x24"); + + asm volatile ("SUB r0, r0, #0x4"); + asm volatile ("MOV r0, lr"); + + asm volatile ("MOV r1, lr"); + asm volatile ("MOV r2, #0x04"); + asm volatile ("TST r1, r2"); + + asm volatile ("BEQ Arm32SwitchUpdateMsp"); + asm volatile ("MSR psp, r0"); + asm volatile ("B Arm32SwitchUpdateDone"); + asm volatile ("B Arm32SwitchUpdateMsp"); +} + +void __attribute__((naked)) Arm32SwitchUpdateMsp() +{ + asm volatile ("MSR msp, r0"); + asm volatile ("B Arm32SwitchUpdateDone"); +} + +void __attribute__((naked)) Arm32SwitchUpdateDone() +{ + asm volatile ("PUSH {LR}"); + asm volatile ("BL HwHardFaultException"); + + asm volatile ("POP {R1}"); + asm volatile ("MOV lr, r1"); + + asm volatile ("MOV r1, lr"); + asm volatile ("MOV r2, #0x04"); + asm volatile ("ORR r1, r2"); + asm volatile ("MOV lr, r1"); + + asm volatile ("BX lr"); +} + +void __attribute__((naked)) MemFaultHandler() +{ + asm volatile ("MRS r0, msp"); + + // asm volatile ("TST lr, #0x04"); + asm volatile ("MOV r1, lr"); + asm volatile ("MOV r2, #0x04"); + asm volatile ("TST r1, r2"); + + asm volatile ("BEQ Arm32Switch1"); + asm volatile ("MRS r0, psp"); + asm volatile ("B Arm32Switch1"); +} + +void __attribute__((naked)) Arm32Switch1() +{ + asm volatile ("MRS r3, primask"); + + asm volatile ("SUB r0, r0, #0x24"); + asm volatile ("STMIA r0!, {r3 - r7}"); + asm volatile ("MOV r3, r8"); + asm volatile ("MOV r4, r9"); + asm volatile ("MOV r5, r10"); + asm volatile ("MOV r6, r11"); + asm volatile ("STMIA r0!, {r3 - r6}"); + asm volatile ("SUB r0, r0, #0x24"); + + asm volatile ("SUB r0, r0, #0x4"); + asm volatile ("MOV r0, lr"); + + asm volatile ("PUSH {LR}"); + asm volatile ("BL MemFaultHandle"); + + asm volatile ("POP {R5}"); + asm volatile ("MOV lr, r5"); + + asm volatile ("MOV r5, lr"); + asm volatile ("MOV r6, #0x04"); + asm volatile ("ORR r5, r6"); + asm volatile ("MOV lr, r5"); + + asm volatile ("BX lr"); +} diff --git a/Ubiquitous/XiZi/arch/arm/cortex-m23/interrupt.c b/Ubiquitous/XiZi/arch/arm/cortex-m23/interrupt.c new file mode 100644 index 0000000..c552bdb --- /dev/null +++ b/Ubiquitous/XiZi/arch/arm/cortex-m23/interrupt.c @@ -0,0 +1,83 @@ +/* +* Copyright (c) 2020 AIIT XUOS Lab +* XiUOS is licensed under Mulan PSL v2. +* You can use this software according to the terms and conditions of the Mulan PSL v2. +* You may obtain a copy of Mulan PSL v2 at: +* http://license.coscl.org.cn/MulanPSL2 +* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, +* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, +* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. +* See the Mulan PSL v2 for more details. +*/ + +/** +* @file interrupt.c +* @brief support arm cortex-m23 interrupt function +* @version 1.1 +* @author AIIT XUOS Lab +* @date 2022-02-24 +*/ + +#include +#include + + +x_base __attribute__((naked)) DisableLocalInterrupt() +{ + asm volatile ("MRS r0, PRIMASK"); + asm volatile ("CPSID I"); + asm volatile ("BX LR "); +} + +void __attribute__((naked)) EnableLocalInterrupt(x_base level) +{ + asm volatile ("MSR PRIMASK, r0"); + asm volatile ("BX LR"); +} + +int32 ArchEnableHwIrq(uint32 irq_num) +{ + return EOK; +} + +int32 ArchDisableHwIrq(uint32 irq_num) +{ + return EOK; +} + +extern void KTaskOsAssignAfterIrq(void *context); + +void IsrEntry() +{ + uint32 ipsr; + + __asm__ volatile("MRS %0, IPSR" : "=r"(ipsr)); + + isrManager.done->incCounter(); + isrManager.done->handleIrq(ipsr); + KTaskOsAssignAfterIrq(NONE); + isrManager.done->decCounter(); +} + +void UsageFault_Handler() +{ + /* Go to infinite loop when Usage Fault exception occurs */ + while (1) + { + } +} + +void BusFault_Handler() +{ + /* Go to infinite loop when Bus Fault exception occurs */ + while (1) + { + } +} + +void NMI_Handler() +{ + while (1) + { + } +} diff --git a/Ubiquitous/XiZi/arch/arm/cortex-m23/interrupt_vector.S b/Ubiquitous/XiZi/arch/arm/cortex-m23/interrupt_vector.S new file mode 100644 index 0000000..9ae49e8 --- /dev/null +++ b/Ubiquitous/XiZi/arch/arm/cortex-m23/interrupt_vector.S @@ -0,0 +1,197 @@ +/****************************************************************************//** + * @file startup_M2354.S + * @version V1.00 + * @brief CMSIS Device Startup File + * + * SPDX-License-Identifier: Apache-2.0 + * @copyright (C) 2018-2020 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ + +/** +* @file interrupt_vector.S +* @brief derived from M2354_SERIES_BSP_CMSIS_V3.00.002 +* @version 1.1 +* @author AIIT XUOS Lab +* @date 2022-02-23 +*/ + +/************************************************* +File name: interrupt_vector.S +Description: vector table for a M2354KJFAE +Others: +History: +1. Date: 2022-02-23 +Author: AIIT XUOS Lab +Modification: +1. take startup_M2354.S for XiUOS +*************************************************/ + + .align 2 + .thumb_func + .global __PC + .type __PC, % function + +__PC: + MOV r0, lr + BLX lr +.size __PC, . - __PC + + .global HardFaultHandler + .type HardFaultHandler, %function +HardFaultHandler: + /* get current context */ + MRS R0, PSP /* get fault thread stack pointer */ + PUSH {LR} + BL HwHardFaultException + POP {PC} + +/******************************************************************************* +* +* The minimal vector table for a Cortex M23. Note that the proper constructs +* must be placed on this to ensure that it ends up at physical address +* 0x0000.0000. +*******************************************************************************/ +.globl InterruptVectors + + .section .isr_vector,"a",%progbits + .type InterruptVectors, %object + .size InterruptVectors, . - InterruptVectors + +InterruptVectors: + .long _sp /* Top of Stack */ + .long Reset_Handler /* Reset Handler */ + .long NMI_Handler /* NMI Handler */ + .long HardFaultHandler /* Hard Fault Handler */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long IsrEntry /* SVCall Handler */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long PendSV_Handler /* PendSV Handler */ + .long SysTick_Handler /* SysTick Handler */ + + /* External interrupts */ + .long IsrEntry /*BOD_IRQHandler 0 */ + .long IsrEntry /*IRC_IRQHandler 1 */ + .long IsrEntry /*PWRWU_IRQHandler 2 */ + .long IsrEntry /*SRAM_IRQHandler 3 */ + .long IsrEntry /*CLKFAIL_IRQHandler 4 */ + .long IsrEntry /*Default_Handler 5 */ + .long IsrEntry /*RTC_IRQHandler 6 */ + .long IsrEntry /*RTC_TAMPER_IRQHandler 7 */ + .long IsrEntry /*WDT_IRQHandler 8 */ + .long IsrEntry /*WWDT_IRQHandler 9 */ + .long IsrEntry /*EINT0_IRQHandler 10 */ + .long IsrEntry /*EINT1_IRQHandler 11 */ + .long IsrEntry /*EINT2_IRQHandler 12 */ + .long IsrEntry /*EINT3_IRQHandler 13 */ + .long IsrEntry /*EINT4_IRQHandler 14 */ + .long IsrEntry /*EINT5_IRQHandler 15 */ + .long IsrEntry /*GPA_IRQHandler 16 */ + .long IsrEntry /*GPB_IRQHandler 17 */ + .long IsrEntry /*GPC_IRQHandler 18 */ + .long IsrEntry /*GPD_IRQHandler 19 */ + .long IsrEntry /*GPE_IRQHandler 20 */ + .long IsrEntry /*GPF_IRQHandler 21 */ + .long IsrEntry /*QSPI0_IRQHandler 22 */ + .long IsrEntry /*SPI0_IRQHandler 23 */ + .long IsrEntry /*BRAKE0_IRQHandler 24 */ + .long IsrEntry /*EPWM0_P0_IRQHandler 25 */ + .long IsrEntry /*EPWM0_P1_IRQHandler 26 */ + .long IsrEntry /*EPWM0_P2_IRQHandler 27 */ + .long IsrEntry /*BRAKE1_IRQHandler 28 */ + .long IsrEntry /*EPWM1_P0_IRQHandler 29 */ + .long IsrEntry /*EPWM1_P1_IRQHandler 30 */ + .long IsrEntry /*EPWM1_P2_IRQHandler 31 */ + .long IsrEntry /*TMR0_IRQHandler 32 */ + .long IsrEntry /*TMR1_IRQHandler 33 */ + .long IsrEntry /*TMR2_IRQHandler 34 */ + .long IsrEntry /*TMR3_IRQHandler 35 */ + .long UART0_IRQHandler /*UART0_IRQHandler 36 */ + .long IsrEntry /*UART1_IRQHandler 37 */ + .long IsrEntry /*I2C0_IRQHandler 38 */ + .long IsrEntry /*I2C1_IRQHandler 39 */ + .long IsrEntry /*PDMA0_IRQHandler 40 */ + .long IsrEntry /*DAC_IRQHandler 41 */ + .long IsrEntry /*EADC0_IRQHandler 42 */ + .long IsrEntry /*EADC1_IRQHandler 43 */ + .long IsrEntry /*ACMP01_IRQHandler 44 */ + .long IsrEntry /*Default_Handler 45 */ + .long IsrEntry /*EADC2_IRQHandler 46 */ + .long IsrEntry /*EADC3_IRQHandler 47 */ + .long IsrEntry /*UART2_IRQHandler 48 */ + .long IsrEntry /*UART3_IRQHandler 49 */ + .long IsrEntry /*Default_Handler 50 */ + .long IsrEntry /*SPI1_IRQHandler 51 */ + .long IsrEntry /*SPI2_IRQHandler 52 */ + .long IsrEntry /*USBD_IRQHandler 53 */ + .long IsrEntry /*USBH_IRQHandler 54 */ + .long IsrEntry /*USBOTG_IRQHandler 55 */ + .long IsrEntry /*CAN0_IRQHandler 56 */ + .long IsrEntry /*Default_Handler 57 */ + .long IsrEntry /*SC0_IRQHandler 58 */ + .long IsrEntry /*SC1_IRQHandler 59 */ + .long IsrEntry /*SC2_IRQHandler 60 */ + .long IsrEntry /*Default_Handler 61 */ + .long IsrEntry /*SPI3_IRQHandler 62 */ + .long IsrEntry /*Default_Handler 63 */ + .long IsrEntry /*SDH0_IRQHandler 64 */ + .long IsrEntry /*Default_Handler 65 */ + .long IsrEntry /*Default_Handler 66 */ + .long IsrEntry /*Default_Handler 67 */ + .long IsrEntry /*I2S0_IRQHandler 68 */ + .long IsrEntry /*Default_Handler 69 */ + .long IsrEntry /*OPA0_IRQHandler 70 */ + .long IsrEntry /*CRPT_IRQHandler 71 */ + .long IsrEntry /*GPG_IRQHandler 72 */ + .long IsrEntry /*EINT6_IRQHandler 73 */ + .long IsrEntry /*UART4_IRQHandler 74 */ + .long IsrEntry /*UART5_IRQHandler 75 */ + .long IsrEntry /*USCI0_IRQHandler 76 */ + .long IsrEntry /*USCI1_IRQHandler 77 */ + .long IsrEntry /*BPWM0_IRQHandler 78 */ + .long IsrEntry /*BPWM1_IRQHandler 79 */ + .long IsrEntry /*Default_Handler 80 */ + .long IsrEntry /*Default_Handler 81 */ + .long IsrEntry /*I2C2_IRQHandler 82 */ + .long IsrEntry /*Default_Handler 83 */ + .long IsrEntry /*QEI0_IRQHandler 84 */ + .long IsrEntry /*QEI1_IRQHandler 85 */ + .long IsrEntry /*ECAP0_IRQHandler 86 */ + .long IsrEntry /*ECAP1_IRQHandler 87 */ + .long IsrEntry /*GPH_IRQHandler 88 */ + .long IsrEntry /*EINT7_IRQHandler 89 */ + .long IsrEntry /*Default_Handler 90 */ + .long IsrEntry /*Default_Handler 91 */ + .long IsrEntry /*Default_Handler 92 */ + .long IsrEntry /*Default_Handler 93 */ + .long IsrEntry /*Default_Handler 94 */ + .long IsrEntry /*Default_Handler 95 */ + .long IsrEntry /*Default_Handler 96 */ + .long IsrEntry /*Default_Handler 97 */ + .long IsrEntry /*PDMA1_IRQHandler 98 */ + .long IsrEntry /*SCU_IRQHandler 99 */ + .long IsrEntry /*LCD_IRQHandler 100 */ + .long IsrEntry /*TRNG_IRQHandler 101 */ + .long IsrEntry /*Default_Handler 102 */ + .long IsrEntry /*Default_Handler 103 */ + .long IsrEntry /*Default_Handler 104 */ + .long IsrEntry /*Default_Handler 105 */ + .long IsrEntry /*Default_Handler 106 */ + .long IsrEntry /*Default_Handler 107 */ + .long IsrEntry /*Default_Handler 108 */ + .long IsrEntry /*KS_IRQHandler 109 */ + .long IsrEntry /*TAMPER_IRQHandler 110 */ + .long IsrEntry /*EWDT_IRQHandler 111 */ + .long IsrEntry /*EWWDT_IRQHandler 112 */ + .long IsrEntry /*NS_ISP_IRQHandler 113 */ + .long IsrEntry /*TMR4_IRQHandler 114 */ + .long IsrEntry /*TMR5_IRQHandler 115 */ + + .end + diff --git a/Ubiquitous/XiZi/arch/arm/cortex-m23/prepare_ahwstack.c b/Ubiquitous/XiZi/arch/arm/cortex-m23/prepare_ahwstack.c new file mode 100644 index 0000000..c4c02bc --- /dev/null +++ b/Ubiquitous/XiZi/arch/arm/cortex-m23/prepare_ahwstack.c @@ -0,0 +1,411 @@ +/* +* Copyright (c) 2020 AIIT XUOS Lab +* XiUOS is licensed under Mulan PSL v2. +* You can use this software according to the terms and conditions of the Mulan PSL v2. +* You may obtain a copy of Mulan PSL v2 at: +* http://license.coscl.org.cn/MulanPSL2 +* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, +* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, +* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. +* See the Mulan PSL v2 for more details. +*/ + +#include +#include +#include +#include "svc_handle.h" +#include +#include + +#if (defined ( __GNUC__ ) && defined ( __VFP_FP__ ) && !defined(__SOFTFP__)) +#define USE_FPU 1 +#else +#define USE_FPU 0 +#endif + +uint32 InterruptFromKtask; +uint32 InterruptToKtask; +uint32 KtaskSwitchInterruptFlag; +uint32 InterruptToKtaskDescriptor; +#define RunningKTask Assign.os_running_task + +static x_err_t (*ExceptionHook)(void *context) = NONE; + +struct ExceptionStackRegister +{ + uint32 r0; + uint32 r1; + uint32 r2; + uint32 r3; + uint32 r12; + uint32 lr; + uint32 pc; + uint32 psr; +}; + +struct StackRegisterContent +{ +#if defined ( __VFP_FP__ ) && !defined(__SOFTFP__) + uint32 flag; +#endif + //uint32 primask; + uint32 r4; + uint32 r5; + uint32 r6; + uint32 r7; + uint32 r8; + uint32 r9; + uint32 r10; + uint32 r11; + // uint32 exc_ret; + + struct ExceptionStackRegister ExErrorStackContex; +}; + +struct ExceptionStackFrameFpu +{ + uint32 r0; + uint32 r1; + uint32 r2; + uint32 r3; + uint32 r12; + uint32 lr; + uint32 pc; + uint32 psr; + +#if USE_FPU + uint32 S0; + uint32 S1; + uint32 S2; + uint32 S3; + uint32 S4; + uint32 S5; + uint32 S6; + uint32 S7; + uint32 S8; + uint32 S9; + uint32 S10; + uint32 S11; + uint32 S12; + uint32 S13; + uint32 S14; + uint32 S15; + uint32 FPSCR; + uint32 NO_NAME; +#endif +}; + +struct StackFrameFpu +{ + uint32 flag; + + uint32 r4; + uint32 r5; + uint32 r6; + uint32 r7; + uint32 r8; + uint32 r9; + uint32 r10; + uint32 r11; + +#if USE_FPU + uint32 s16; + uint32 s17; + uint32 s18; + uint32 s19; + uint32 s20; + uint32 s21; + uint32 s22; + uint32 s23; + uint32 s24; + uint32 s25; + uint32 s26; + uint32 s27; + uint32 s28; + uint32 s29; + uint32 s30; + uint32 s31; +#endif + + struct ExceptionStackFrameFpu ExErrorStackContex; +}; + +uint8 KTaskStackSetup(struct TaskDescriptor *task) +{ + struct StackRegisterContent* StackContex; + int i = 0; + + task->stack_point = (uint8 *)ALIGN_MEN_DOWN((x_ubase)(task->task_base_info.stack_start + task->task_base_info.stack_depth), 8); + task->stack_point -= sizeof(struct StackRegisterContent); + + StackContex = (struct StackRegisterContent*)task->stack_point; + + for (i = 0; i < sizeof(struct StackRegisterContent) / sizeof(uint32); i++) + ((uint32 *)StackContex)[i] = 0xfadeface; + + StackContex->ExErrorStackContex.r0 = (unsigned long)task->task_base_info.func_param; + + StackContex->ExErrorStackContex.pc = (unsigned long)task->task_base_info.func_entry ; + StackContex->ExErrorStackContex.psr = 0x01000000L; + //StackContex->primask = 0x00000000L; +#ifdef SEPARATE_COMPILE + if(task->task_dync_sched_member.isolation_flag == 1 ) { + StackContex->ExErrorStackContex.lr = (unsigned long)USERSPACE->us_taskquit; + } else { + StackContex->ExErrorStackContex.lr = (unsigned long)KTaskQuit; + } +#else + StackContex->ExErrorStackContex.lr = (unsigned long)KTaskQuit; +#endif + +#if USE_FPU + StackContex->flag = 0; +#endif + + return EOK; +} + + +void HwExceptionInstall(x_err_t (*exception_handle)(void *context)) +{ + ExceptionHook = exception_handle; +} + +#define SCB_CFSR (*(volatile const unsigned *)0xE000ED28) +#define SCB_HFSR (*(volatile const unsigned *)0xE000ED2C) +#define SCB_MMAR (*(volatile const unsigned *)0xE000ED34) +#define SCB_BFAR (*(volatile const unsigned *)0xE000ED38) +#define SCB_AIRCR (*(volatile unsigned long *)0xE000ED0C) +#define SCB_RESET_VALUE 0x05FA0004 + +#define SCB_CFSR_MFSR (*(volatile const unsigned char*)0xE000ED28) +#define SCB_CFSR_BFSR (*(volatile const unsigned char*)0xE000ED29) +#define SCB_CFSR_UFSR (*(volatile const unsigned short*)0xE000ED2A) + +#ifdef TOOL_SHELL +static void UsageFaultTrack(void) +{ + KPrintf("usage fault:\n"); + KPrintf("SCB_CFSR_UFSR:0x%02X ", SCB_CFSR_UFSR); + + if(SCB_CFSR_UFSR & (1<<0)) + KPrintf("UNDEFINSTR "); + + if(SCB_CFSR_UFSR & (1<<1)) + KPrintf("INVSTATE "); + + if(SCB_CFSR_UFSR & (1<<2)) + KPrintf("INVPC "); + + if(SCB_CFSR_UFSR & (1<<3)) + KPrintf("NOCP "); + + if(SCB_CFSR_UFSR & (1<<8)) + KPrintf("UNALIGNED "); + + if(SCB_CFSR_UFSR & (1<<9)) + KPrintf("DIVBYZERO "); + + KPrintf("\n"); +} + +static void BusFaultTrack(void) +{ + KPrintf("bus fault:\n"); + KPrintf("SCB_CFSR_BFSR:0x%02X ", SCB_CFSR_BFSR); + + if(SCB_CFSR_BFSR & (1<<0)) + KPrintf("IBUSERR "); + + if(SCB_CFSR_BFSR & (1<<1)) + KPrintf("PRECISERR "); + + if(SCB_CFSR_BFSR & (1<<2)) + KPrintf("IMPRECISERR "); + + if(SCB_CFSR_BFSR & (1<<3)) + KPrintf("UNSTKERR "); + + if(SCB_CFSR_BFSR & (1<<4)) + KPrintf("STKERR "); + + if(SCB_CFSR_BFSR & (1<<7)) + KPrintf("SCB->BFAR:%08X\n", SCB_BFAR); + else + KPrintf("\n"); +} + +static void MemManageFaultTrack(void) +{ + KPrintf("mem manage fault:\n"); + KPrintf("SCB_CFSR_MFSR:0x%02X ", SCB_CFSR_MFSR); + + if(SCB_CFSR_MFSR & (1<<0)) + KPrintf("IACCVIOL "); + if(SCB_CFSR_MFSR & (1<<1)) + KPrintf("DACCVIOL "); + + if(SCB_CFSR_MFSR & (1<<3)) + KPrintf("MUNSTKERR "); + + if(SCB_CFSR_MFSR & (1<<4)) + KPrintf("MSTKERR "); + + if(SCB_CFSR_MFSR & (1<<7)) + KPrintf("SCB->MMAR:%08X\n", SCB_MMAR); + else + KPrintf("\n"); +} + +static void HardFaultTrack(void) +{ + if(SCB_HFSR & (1UL<<1)) + KPrintf("failed vector fetch\n"); + + if(SCB_HFSR & (1UL<<30)) { + if(SCB_CFSR_BFSR) + BusFaultTrack(); + + if(SCB_CFSR_MFSR) + MemManageFaultTrack(); + + if(SCB_CFSR_UFSR) + UsageFaultTrack(); + } + + if(SCB_HFSR & (1UL<<31)) + KPrintf("debug event\n"); +} +#endif + +struct ExceptionInfo +{ + uint32 ExcReturn; + struct StackRegisterContent stackframe; +}; + +void HwHardFaultException(struct ExceptionInfo *ExceptionInfo) +{ + extern long ShowTask(void); + struct ExErrorStackContex* ExceptionStack = (struct ExErrorStackContex*)&ExceptionInfo->stackframe.ExErrorStackContex; + struct StackRegisterContent* context = (struct StackRegisterContent*)&ExceptionInfo->stackframe; + + if (ExceptionHook != NONE) { + x_err_t result = ExceptionHook(ExceptionStack); + if (result == EOK) return; + } + + KPrintf("psr: 0x%08x\n", context->ExErrorStackContex.psr); + KPrintf("r00: 0x%08x\n", context->ExErrorStackContex.r0); + KPrintf("r01: 0x%08x\n", context->ExErrorStackContex.r1); + KPrintf("r02: 0x%08x\n", context->ExErrorStackContex.r2); + KPrintf("r03: 0x%08x\n", context->ExErrorStackContex.r3); + KPrintf("r04: 0x%08x\n", context->r4); + KPrintf("r05: 0x%08x\n", context->r5); + KPrintf("r06: 0x%08x\n", context->r6); + KPrintf("r07: 0x%08x\n", context->r7); + KPrintf("r08: 0x%08x\n", context->r8); + KPrintf("r09: 0x%08x\n", context->r9); + KPrintf("r10: 0x%08x\n", context->r10); + KPrintf("r11: 0x%08x\n", context->r11); + //KPrintf("exc_ret: 0x%08x\n", context->exc_ret); + KPrintf("r12: 0x%08x\n", context->ExErrorStackContex.r12); + KPrintf(" lr: 0x%08x\n", context->ExErrorStackContex.lr); + KPrintf(" pc: 0x%08x\n", context->ExErrorStackContex.pc); + + if (ExceptionInfo->ExcReturn & (1 << 2)) { + KPrintf("hard fault on task: %s\r\n\r\n", GetKTaskDescriptor()->task_base_info.name); +#ifdef TOOL_SHELL + ShowTask(); +#endif + } else { + KPrintf("hard fault on handler\r\n\r\n"); + } + + if ( (ExceptionInfo->ExcReturn & 0x10) == 0) + KPrintf("FPU active!\r\n"); + +#ifdef TOOL_SHELL + HardFaultTrack(); +#endif + + while (1); +} + +void UpdateRunningTask(void) +{ + RunningKTask = (struct TaskDescriptor *)InterruptToKtaskDescriptor; +} + + +void MemFaultExceptionPrint(struct ExceptionInfo *ExceptionInfo) +{ + extern long ShowTask(void); + struct ExErrorStackContex* ExceptionStack = (struct ExErrorStackContex*)&ExceptionInfo->stackframe.ExErrorStackContex; + struct StackRegisterContent* context = (struct StackRegisterContent*)&ExceptionInfo->stackframe; + + if (ExceptionHook != NONE) { + x_err_t result = ExceptionHook(ExceptionStack); + if (result == EOK) return; + } + + KPrintf("psr: 0x%08x\n", context->ExErrorStackContex.psr); + KPrintf("r00: 0x%08x\n", context->ExErrorStackContex.r0); + KPrintf("r01: 0x%08x\n", context->ExErrorStackContex.r1); + KPrintf("r02: 0x%08x\n", context->ExErrorStackContex.r2); + KPrintf("r03: 0x%08x\n", context->ExErrorStackContex.r3); + KPrintf("r04: 0x%08x\n", context->r4); + KPrintf("r05: 0x%08x\n", context->r5); + KPrintf("r06: 0x%08x\n", context->r6); + KPrintf("r07: 0x%08x\n", context->r7); + KPrintf("r08: 0x%08x\n", context->r8); + KPrintf("r09: 0x%08x\n", context->r9); + KPrintf("r10: 0x%08x\n", context->r10); + KPrintf("r11: 0x%08x\n", context->r11); + KPrintf("exc_ret: 0x%08x\n", ExceptionInfo->ExcReturn); + KPrintf("r12: 0x%08x\n", context->ExErrorStackContex.r12); + KPrintf(" lr: 0x%08x\n", context->ExErrorStackContex.lr); + KPrintf(" pc: 0x%08x\n", context->ExErrorStackContex.pc); + + if (ExceptionInfo->ExcReturn & (1 << 2)) { + KPrintf("hard fault on task: %s\r\n\r\n", GetKTaskDescriptor()->task_base_info.name); +#ifdef TOOL_SHELL + ShowTask(); +#endif + } else { + KPrintf("hard fault on handler\r\n\r\n"); + } + + if ((ExceptionInfo->ExcReturn & 0x10) == 0) + KPrintf("FPU active!\r\n"); + + +#ifdef TOOL_SHELL + HardFaultTrack(); +#endif + + while (1); +} + +void MemFaultHandle(uintptr_t *sp) +{ +#ifdef TASK_ISOLATION + struct TaskDescriptor *task; + task = GetKTaskDescriptor(); + if( task->task_dync_sched_member.isolation_flag == 1){ + KPrintf("\nSegmentation fault, task: %s\n", task->task_base_info.name); + KTaskQuit(); + } + else +#endif + { + MemFaultExceptionPrint((struct ExceptionInfo *)sp); + } + +} + +__attribute__((weak)) void HwCpuReset(void) +{ + SCB_AIRCR = SCB_RESET_VALUE; +} +SHELL_EXPORT_CMD(SHELL_CMD_PERMISSION(0)|SHELL_CMD_TYPE(SHELL_TYPE_CMD_FUNC)|SHELL_CMD_PARAM_NUM(0), Reboot, HwCpuReset, reset machine ); \ No newline at end of file diff --git a/Ubiquitous/XiZi/arch/arm/cortex-m23/svc_handle.h b/Ubiquitous/XiZi/arch/arm/cortex-m23/svc_handle.h new file mode 100644 index 0000000..1822417 --- /dev/null +++ b/Ubiquitous/XiZi/arch/arm/cortex-m23/svc_handle.h @@ -0,0 +1,58 @@ +/* +* Copyright (c) 2020 AIIT XUOS Lab +* XiUOS is licensed under Mulan PSL v2. +* You can use this software according to the terms and conditions of the Mulan PSL v2. +* You may obtain a copy of Mulan PSL v2 at: +* http://license.coscl.org.cn/MulanPSL2 +* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, +* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, +* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. +* See the Mulan PSL v2 for more details. +*/ + +#ifndef __INC_SVC_HANDLE_H__ +#define __INC_SVC_HANDLE_H__ + +#if defined ( __VFP_FP__ ) && !defined(__SOFTFP__) +#define INT_FPU_REGS (1) +#else +#define INT_FPU_REGS (0) +#endif + +#define HW_INT_REGS (8) +#define SW_INT_REGS (9 + INT_FPU_REGS) + +#define REG_INT_R0 (SW_INT_REGS + 0) /* R0 */ +#define REG_INT_R1 (SW_INT_REGS + 1) /* R1 */ +#define REG_INT_R2 (SW_INT_REGS + 2) /* R2 */ +#define REG_INT_R3 (SW_INT_REGS + 3) /* R3 */ +#define REG_INT_R12 (SW_INT_REGS + 4) /* R12 */ +#define REG_INT_R14 (SW_INT_REGS + 5) /* R14 = LR */ +#define REG_INT_PC (SW_INT_REGS + 6) /* R15 = PC */ +#define REG_INT_XPSR (SW_INT_REGS + 7) /* xPSR */ + +#if defined ( __VFP_FP__ ) && !defined(__SOFTFP__) +#define REG_INT_FPU_FLAG (0) /* fpu flag */ +#define REG_INT_PRIMASK (1) /* PRIMASK */ +#define REG_INT_R4 (2) /* R4 */ +#define REG_INT_R5 (3) /* R5 */ +#define REG_INT_R6 (4) /* R6 */ +#define REG_INT_R7 (5) /* R7 */ +#define REG_INT_R8 (6) /* R8 */ +#define REG_INT_R9 (7) /* R9 */ +#define REG_INT_R10 (8) /* R10 */ +#define REG_INT_R11 (9) /* R11 */ +#else +#define REG_INT_PRIMASK (0) /* PRIMASK */ +#define REG_INT_R4 (1) /* R4 */ +#define REG_INT_R5 (2) /* R5 */ +#define REG_INT_R6 (3) /* R6 */ +#define REG_INT_R7 (4) /* R7 */ +#define REG_INT_R8 (5) /* R8 */ +#define REG_INT_R9 (6) /* R9 */ +#define REG_INT_R10 (7) /* R10 */ +#define REG_INT_R11 (8) /* R11 */ +#endif + + +#endif diff --git a/Ubiquitous/XiZi/arch/arm/cortex-m3/Makefile b/Ubiquitous/XiZi/arch/arm/cortex-m3/Makefile new file mode 100644 index 0000000..1bf3585 --- /dev/null +++ b/Ubiquitous/XiZi/arch/arm/cortex-m3/Makefile @@ -0,0 +1,11 @@ +ifeq ($(CONFIG_BOARD_CORTEX_M3_EVB),y) +SRC_FILES := boot.c interrupt_vector_evb.S +endif + +ifeq ($(CONFIG_BOARD_STM32F103_NANO),y) +SRC_FILES := boot.S interrupt_vector_nano.S +endif + +SRC_FILES += interrupt.c + +include $(KERNEL_ROOT)/compiler.mk diff --git a/Ubiquitous/XiZi/arch/arm/cortex-m3/arch_interrupt.h b/Ubiquitous/XiZi/arch/arm/cortex-m3/arch_interrupt.h new file mode 100644 index 0000000..068ec7f --- /dev/null +++ b/Ubiquitous/XiZi/arch/arm/cortex-m3/arch_interrupt.h @@ -0,0 +1,36 @@ +/* +* Copyright (c) 2020 AIIT XUOS Lab +* XiUOS is licensed under Mulan PSL v2. +* You can use this software according to the terms and conditions of the Mulan PSL v2. +* You may obtain a copy of Mulan PSL v2 at: +* http://license.coscl.org.cn/MulanPSL2 +* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, +* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, +* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. +* See the Mulan PSL v2 for more details. +*/ + +#ifndef ARCH_INTERRUPT_H__ +#define ARCH_INTERRUPT_H__ + +#include + +#ifdef BOARD_CORTEX_M3_EVB +#define ARCH_MAX_IRQ_NUM (256) +#endif + +#ifdef BOARD_STM32F103_NANO +#define ARCH_MAX_IRQ_NUM (64) +#endif + +#define ARCH_IRQ_NUM_OFFSET 0 + +#ifdef BOARD_CORTEX_M3_EVB +#define SYSTICK_IRQN 15 +#define UART1_IRQn 21 +#endif + +int32 ArchEnableHwIrq(uint32 irq_num); +int32 ArchDisableHwIrq(uint32 irq_num); + +#endif diff --git a/Ubiquitous/XiZi/arch/arm/cortex-m3/interrupt.c b/Ubiquitous/XiZi/arch/arm/cortex-m3/interrupt.c new file mode 100644 index 0000000..1164501 --- /dev/null +++ b/Ubiquitous/XiZi/arch/arm/cortex-m3/interrupt.c @@ -0,0 +1,84 @@ +/* +* Copyright (c) 2020 AIIT XUOS Lab +* XiUOS is licensed under Mulan PSL v2. +* You can use this software according to the terms and conditions of the Mulan PSL v2. +* You may obtain a copy of Mulan PSL v2 at: +* http://license.coscl.org.cn/MulanPSL2 +* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, +* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, +* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. +* See the Mulan PSL v2 for more details. +*/ + +/** +* @file interrupt.c +* @brief support arm cortex-m4 interrupt function +* @version 1.0 +* @author AIIT XUOS Lab +* @date 2021-04-29 +*/ + +#include +#include + + +x_base __attribute__((naked)) DisableLocalInterrupt() +{ + asm volatile ("MRS r0, PRIMASK"); + asm volatile ("CPSID I"); + asm volatile ("BX LR "); +} + +void __attribute__((naked)) EnableLocalInterrupt(x_base level) +{ + asm volatile ("MSR PRIMASK, r0"); + asm volatile ("BX LR"); +} + +int32 ArchEnableHwIrq(uint32 irq_num) +{ + return EOK; +} + +int32 ArchDisableHwIrq(uint32 irq_num) +{ + return EOK; +} + +extern void KTaskOsAssignAfterIrq(void *context); + +void IsrEntry() +{ + uint32 ipsr; + + __asm__ volatile("MRS %0, IPSR" : "=r"(ipsr)); + + isrManager.done->incCounter(); + isrManager.done->handleIrq(ipsr); + KTaskOsAssignAfterIrq(NONE); + isrManager.done->decCounter(); + +} + +void UsageFault_Handler(int irqn, void *arg) +{ + /* Go to infinite loop when Usage Fault exception occurs */ + while (1) + { + } +} + +void BusFault_Handler(int irqn, void *arg) +{ + /* Go to infinite loop when Bus Fault exception occurs */ + while (1) + { + } +} + +void NMI_Handler(int irqn, void *arg) +{ + while (1) + { + } +} diff --git a/Ubiquitous/XiZi/arch/arm/cortex-m4/Makefile b/Ubiquitous/XiZi/arch/arm/cortex-m4/Makefile new file mode 100644 index 0000000..74aa9e2 --- /dev/null +++ b/Ubiquitous/XiZi/arch/arm/cortex-m4/Makefile @@ -0,0 +1,7 @@ +SRC_FILES := system_init.c boot.S interrupt_vector.S coreclock.c interrupt.c svc_entry.S + +ifeq ($(CONFIG_TASK_ISOLATION),y) +SRC_FILES += svc_handle.c mpu.c +endif + +include $(KERNEL_ROOT)/compiler.mk diff --git a/Ubiquitous/XiZi/arch/arm/cortex-m4/arch_interrupt.h b/Ubiquitous/XiZi/arch/arm/cortex-m4/arch_interrupt.h new file mode 100644 index 0000000..bf2f211 --- /dev/null +++ b/Ubiquitous/XiZi/arch/arm/cortex-m4/arch_interrupt.h @@ -0,0 +1,25 @@ +/* +* Copyright (c) 2020 AIIT XUOS Lab +* XiUOS is licensed under Mulan PSL v2. +* You can use this software according to the terms and conditions of the Mulan PSL v2. +* You may obtain a copy of Mulan PSL v2 at: +* http://license.coscl.org.cn/MulanPSL2 +* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, +* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, +* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. +* See the Mulan PSL v2 for more details. +*/ + +#ifndef ARCH_INTERRUPT_H__ +#define ARCH_INTERRUPT_H__ + +#include + +#define ARCH_MAX_IRQ_NUM (256 + 16) + +#define ARCH_IRQ_NUM_OFFSET 16 + +int32 ArchEnableHwIrq(uint32 irq_num); +int32 ArchDisableHwIrq(uint32 irq_num); + +#endif diff --git a/Ubiquitous/XiZi/arch/arm/cortex-m4/kswitch.h b/Ubiquitous/XiZi/arch/arm/cortex-m4/kswitch.h new file mode 100644 index 0000000..586846f --- /dev/null +++ b/Ubiquitous/XiZi/arch/arm/cortex-m4/kswitch.h @@ -0,0 +1,292 @@ +/**************************************************************************** + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/** +* @file kswitch.h +* @brief risc-v ecall function +* @version 1.0 +* @author AIIT XUOS Lab +* @date 2021-04-25 +*/ + +/************************************************* +File name: kswitch.h +Description: arm svc function +Others: take incubator-nuttx arch/arm/include/armv7-m/syscall.h for references + https://github.com/apache/incubator-nuttx/tree/master/arch/arm/include/armv7-m/syscall.h +History: +1. Date: 2021-04-25 +Author: AIIT XUOS Lab +Modification: +1. Modify function name for a unified +2. Add some functions when there is no system call +*************************************************/ +#ifndef __XS_ARM_M4_KSWITCH_H__ +#define __XS_ARM_M4_KSWITCH_H__ + +#include +// #include +#include "../../../kernel/include/xs_service.h" + +#ifdef TASK_ISOLATION +#define KERNEL_SWITCH 0x00 + +/**************************************************************************** + * kernel switch functions + ****************************************************************************/ + +/* SVC call with call number and no parameters */ +static inline unsigned long KSwitch0(unsigned int nbr) +{ + register long reg0 __asm__("r0") = (long)(nbr); + + __asm__ __volatile__ + ( + "svc %1" + : "=r"(reg0) + : "i"(KERNEL_SWITCH), "r"(reg0) + : "memory" + ); + + return reg0; +} + +/* SVC call with call number and one parameter */ +static inline unsigned long KSwitch1(unsigned int nbr, unsigned long parm1) +{ + register long reg0 __asm__("r0") = (long)(nbr); + register long reg1 __asm__("r1") = (long)(parm1); + + __asm__ __volatile__ + ( + "svc %1" + : "=r"(reg0) + : "i"(KERNEL_SWITCH), "r"(reg0), "r"(reg1) + : "memory" + ); + + return reg0; +} + +/* SVC call with call number and two parameters */ +static inline unsigned long KSwitch2(unsigned int nbr, unsigned long parm1, + unsigned long parm2) +{ + register long reg0 __asm__("r0") = (long)(nbr); + register long reg2 __asm__("r2") = (long)(parm2); + register long reg1 __asm__("r1") = (long)(parm1); + + __asm__ __volatile__ + ( + "svc %1" + : "=r"(reg0) + : "i"(KERNEL_SWITCH), "r"(reg0), "r"(reg1), "r"(reg2) + : "memory" + ); + + return reg0; +} + + +/* SVC call with call number and four parameters. + * + */ +static inline unsigned long KSwitch3(unsigned int nbr, unsigned long parm1, + unsigned long parm2, unsigned long parm3) +{ + register long reg0 __asm__("r0") = (long)(nbr); + register long reg1 __asm__("r1") = (long)(parm1); + register long reg2 __asm__("r2") = (long)(parm2); + register long reg3 __asm__("r3") = (long)(parm3); + + + + __asm__ __volatile__ + ( + "svc %1" + : "=r"(reg0) + : "i"(KERNEL_SWITCH), "r"(reg0), "r"(reg1), "r"(reg2), + "r"(reg3) + : "memory" + ); + + return reg0; +} + +static inline unsigned long KSwitch4(unsigned int nbr, unsigned long parm1, + unsigned long parm2, unsigned long parm3, + unsigned long parm4) +{ + register long reg0 __asm__("r0") = (long)(nbr); + register long reg4 __asm__("r4") = (long)(parm4); + register long reg3 __asm__("r3") = (long)(parm3); + register long reg2 __asm__("r2") = (long)(parm2); + register long reg1 __asm__("r1") = (long)(parm1); + + __asm__ __volatile__ + ( + "svc %1" + : "=r"(reg0) + : "i"(KERNEL_SWITCH), "r"(reg0), "r"(reg1), "r"(reg2), + "r"(reg3), "r"(reg4) + : "memory" + ); + + return reg0; +} + +/* SVC call with call number and five parameters. + * + */ +static inline unsigned long KSwitch5(unsigned int nbr, unsigned long parm1, + unsigned long parm2, unsigned long parm3, + unsigned long parm4, unsigned long parm5) +{ + register long reg0 __asm__("r0") = (long)(nbr); + register long reg5 __asm__("r5") = (long)(parm5); + register long reg4 __asm__("r4") = (long)(parm4); + register long reg3 __asm__("r3") = (long)(parm3); + register long reg2 __asm__("r2") = (long)(parm2); + register long reg1 __asm__("r1") = (long)(parm1); + + __asm__ __volatile__ + ( + "svc %1" + : "=r"(reg0) + : "i"(KERNEL_SWITCH), "r"(reg0), "r"(reg1), "r"(reg2), + "r"(reg3), "r"(reg4), "r"(reg5) + : "memory" + ); + + return reg0; +} + +/* SVC call with call number and six parameters. + * + */ +static inline unsigned long KSwitch6(unsigned int nbr, unsigned long parm1, + unsigned long parm2, unsigned long parm3, + unsigned long parm4, unsigned long parm5, + unsigned long parm6) +{ + register long reg0 __asm__("r0") = (long)(nbr); + register long reg6 __asm__("r6") = (long)(parm6); + register long reg5 __asm__("r5") = (long)(parm5); + register long reg4 __asm__("r4") = (long)(parm4); + register long reg3 __asm__("r3") = (long)(parm3); + register long reg2 __asm__("r2") = (long)(parm2); + register long reg1 __asm__("r1") = (long)(parm1); + + __asm__ __volatile__ + ( + "svc %1" + : "=r"(reg0) + : "i"(KERNEL_SWITCH), "r"(reg0), "r"(reg1), "r"(reg2), + "r"(reg3), "r"(reg4), "r"(reg5), "r"(reg6) + : "memory" + ); + + return reg0; +} +#else + +static inline unsigned long KSwitch0(unsigned int knum) +{ + uintptr_t param[1] = {0}; + uint8_t num = 0; + (struct KernelService*)SERVICETABLE[knum].fun(knum, param, num); +} + +static inline unsigned long KSwitch1(unsigned int knum, unsigned long arg1) +{ + uintptr_t param[1] = {0}; + uint8_t num = 1; + param[0] = arg1; + (struct KernelService*)SERVICETABLE[knum].fun(knum, param, num); +} + + +static inline unsigned long KSwitch2(unsigned int knum, unsigned long arg1, + unsigned long arg2) +{ + uintptr_t param[2] = {0}; + uint8_t num = 2; + param[0] = arg1; + param[1] = arg2; + (struct KernelService*)SERVICETABLE[knum].fun(knum, param, num); +} + + +static inline unsigned long KSwitch3(unsigned int knum, unsigned long arg1, + unsigned long arg2, unsigned long arg3) +{ + uintptr_t param[3] = {0}; + uint8_t num = 3; + param[0] = arg1; + param[1] = arg2; + param[2] = arg3; + + (struct KernelService*)SERVICETABLE[knum].fun(knum, param, num); +} + +static inline unsigned long KSwitch4(unsigned int knum, unsigned long arg1, + unsigned long arg2, unsigned long arg3, + unsigned long arg4) +{ + uintptr_t param[4] = {0}; + uint8_t num = 4; + param[0] = arg1; + param[1] = arg2; + param[2] = arg3; + param[3] = arg4; + (struct KernelService*)SERVICETABLE[knum].fun(knum, param, num); +} + +static inline unsigned long KSwitch5(unsigned int knum, unsigned long arg1, + unsigned long arg2, unsigned long arg3, + unsigned long arg4, unsigned long arg5) +{ + uintptr_t param[5] = {0}; + uint8_t num = 5; + param[0] = arg1; + param[1] = arg2; + param[2] = arg3; + param[3] = arg4; + param[4] = arg5; + (struct KernelService*)SERVICETABLE[knum].fun(knum, param, num); +} + +static inline unsigned long KSwitch6(unsigned int knum, unsigned long arg1, + unsigned long arg2, unsigned long arg3, + unsigned long arg4, unsigned long arg5, + unsigned long arg6) +{ + uintptr_t param[6] = {0}; + uint8_t num = 6; + param[0] = arg1; + param[1] = arg2; + param[2] = arg3; + param[3] = arg4; + param[4] = arg5; + param[5] = arg6; + (struct KernelService*)SERVICETABLE[knum].fun(knum, param, num); +} + +#endif +#endif diff --git a/Ubiquitous/XiZi/arch/arm/cortex-m4/mpu.c b/Ubiquitous/XiZi/arch/arm/cortex-m4/mpu.c new file mode 100644 index 0000000..0eecba0 --- /dev/null +++ b/Ubiquitous/XiZi/arch/arm/cortex-m4/mpu.c @@ -0,0 +1,203 @@ +/* +* Copyright (c) 2020 AIIT XUOS Lab +* XiUOS is licensed under Mulan PSL v2. +* You can use this software according to the terms and conditions of the Mulan PSL v2. +* You may obtain a copy of Mulan PSL v2 at: +* http://license.coscl.org.cn/MulanPSL2 +* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, +* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, +* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. +* See the Mulan PSL v2 for more details. +*/ + +#include "stm32f4xx.h" +#include "mpu.h" +#include "board.h" +#include + + +void MpuEnable(uint32_t option) +{ + MPU->CTRL = MPU_ENABLE | option; + __DSB(); + __ISB(); + return ; +} + +void MpuDisable(void) +{ + __DMB(); + MPU->CTRL = 0; + return; +} + +void MpuClearRegion(uint8_t region) +{ + __DMB(); + MPU->RNR = region; + MPU->RBAR = 0; + MPU->RASR = 0; + return; +} + +void MpuClearAllRegion(void) +{ + __DMB(); + for (int i = 0 ; i < 8 ; i++) { + MPU->RNR = i; + MPU->RBAR = 0; + MPU->RASR = 0; + } + return; +} + +int8_t MpuAllocateRegion(void *task_mpu) +{ + if(task_mpu == NONE) + return -1; + struct Mpu *mpu = (struct Mpu *)task_mpu; + int8_t free_region; + + if ( mpu->count < MPU_MAX_REGION_NUM - 1) { + free_region = mpu->count; + mpu->count ++; + } + else + free_region = -1; + + return free_region ; +} + + +size_t MpuLog2Ceil(size_t size) +{ + size_t csize = 0; + + while (size > 0) { + size >>= 1; + csize ++; + } + + return csize; +} + +int8_t MpuAddRegion(void *task_mpu, x_base addr , size_t size , uint8_t type) +{ + + if(task_mpu == NONE) + return -1; + struct Mpu *mpu = (struct Mpu *)task_mpu; + uint32_t l2size; + int8_t region ; + + region = MpuAllocateRegion(mpu); + if (region < 0 ) { + // KPrintf("MPU region full \n"); + return region; + } + uint32_t flag = 0; + switch (type) + { + case REGION_TYPE_CODE: + flag = MPU_RASR_AP_RO_RO | MPU_RASR_TEX_0 | MPU_RASR_C | MPU_RASR_S; + break; + case REGION_TYPE_DATA: + flag = MPU_RASR_AP_RW_RW | MPU_RASR_TEX_0 | MPU_RASR_C | MPU_RASR_S ; + break; + case REGION_TYPE_BSS: + flag = MPU_RASR_AP_RW_RW | MPU_RASR_TEX_0 | MPU_RASR_C | MPU_RASR_S ; + break; + case REGION_TYPE_HEAP: + flag = MPU_RASR_AP_RW_RW | MPU_RASR_TEX_0 | MPU_RASR_C | MPU_RASR_S ; + break; + + default: + break; + } + + l2size = MpuLog2Ceil(size); + addr = MPU_ALIGN(addr , 1 << l2size ); + mpu->region[region].config.rasr = flag |MPU_RASR_REGION_SIZE(l2size) | MPU_ENABLE; + mpu->region[region].config.rbar = addr | MPU_RBAR_VALID | region ; //rbar must set region number + + return region; +} + +x_err_t MpuInit(void **task_mpu) +{ + + x_base addr_start; + uint32_t addr_size; + uint32_t flag; + + if (MPU->TYPE == 0) { + KPrintf("mpu not surport \n"); + return -1 ; + } + // KPrintf("mpu init ...\n"); + + struct Mpu *mpu; + mpu = (struct Mpu *)malloc(sizeof(struct Mpu)); + memset(mpu, 0, sizeof(struct Mpu)); + + if (mpu == NONE) + return -ENOMEMORY; + + MpuDisable(); + MpuClearAllRegion(); //clear + + SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk; + + //user flash + addr_start = USER_TEXT_START; + addr_size = USER_TEXT_END - USER_TEXT_START; + MpuAddRegion(mpu, addr_start , addr_size, REGION_TYPE_CODE); + + + //user sram + addr_start = USER_SRAM_START; + addr_size = USER_SRAM_END - USER_SRAM_START; + MpuAddRegion(mpu, addr_start , addr_size, REGION_TYPE_HEAP); + *task_mpu = mpu; + + return EOK; +} + +void MpuFree(void *task_mpu) +{ + if(task_mpu == NONE) + return; + MpuDisable(); + MpuClearAllRegion(); //clear + x_free(task_mpu); +} + +void MpuLoad(void *task_mpu) +{ + // KPrintf("MPU load .. \n"); + MpuDisable(); + MpuClearAllRegion(); //clear + if(task_mpu == NONE) + return; + struct Mpu *mpu = (struct Mpu *)task_mpu; + + uint8_t region = 0 ; + +#if 0 + for ( region = 0 ; region <= mpu->count -1 ; region ++ ){ + KPrintf("region: %d\n",region); + KPrintf("rasr 0x%08x \n",mpu->region[region].config.rasr); + KPrintf("rbar 0x%08x \n",mpu->region[region].config.rbar); + KPrintf("\n"); + } +#endif + + for ( region = 0 ; region <= mpu->count -1 ; region ++ ){ + MPU->RNR = region; + MPU->RBAR = mpu->region[region].config.rbar; + MPU->RASR = mpu->region[region].config.rasr; + } + __DSB(); + __ISB(); + MpuEnable(MPU_PRIVDEFENA); +} \ No newline at end of file diff --git a/Ubiquitous/XiZi/arch/arm/cortex-m4/mpu.h b/Ubiquitous/XiZi/arch/arm/cortex-m4/mpu.h new file mode 100644 index 0000000..3f3d50b --- /dev/null +++ b/Ubiquitous/XiZi/arch/arm/cortex-m4/mpu.h @@ -0,0 +1,97 @@ +/* +* Copyright (c) 2020 AIIT XUOS Lab +* XiUOS is licensed under Mulan PSL v2. +* You can use this software according to the terms and conditions of the Mulan PSL v2. +* You may obtain a copy of Mulan PSL v2 at: +* http://license.coscl.org.cn/MulanPSL2 +* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, +* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, +* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. +* See the Mulan PSL v2 for more details. +*/ +#ifndef MPU_H +#define MPU_H + +#include +#include + + +#define MPU_ALIGN(size, align) (((size)) & ~((align) - 1)) + +#define USER_TEXT_START (uintptr_t)( USERSPACE ) +#define USER_TEXT_END (uintptr_t)( USERSPACE->us_textend ) +#define USER_SRAM_START (uintptr_t)( USERSPACE->us_datastart ) +#define USER_SRAM_END (uintptr_t)( USER_MEMORY_END_ADDRESS ) + + + +#define MPU_MAX_REGION_NUM 8 + + +/* MPU Control Register Bit Definitions */ +#define MPU_ENABLE (1 << 0) /* Bit 0: Enable the MPU */ +#define MPU_HFNMIENA (1 << 1) /* Bit 1: Enable MPU during hard fault, NMI, and FAULTMAS */ +#define MPU_PRIVDEFENA (1 << 2) /* Bit 2: Enable privileged access to default memory map */ + +#define MPU_RBAR_VALID (1 << 4) + +#define MPU_RASR_ENABLE (1 << 0) /* Bit 0: Region enable */ +#define MPU_RASR_REGION_SIZE(n) ((n-1) << 1) + +#define MPU_RASR_AP_NO_NO (0 << 24) /* P:None U:None */ +#define MPU_RASR_AP_RW_NO (1 << 24) /* P:RW U:None */ +#define MPU_RASR_AP_RW_RO (2 << 24) /* P:RW U:RO */ +#define MPU_RASR_AP_RW_RW (3 << 24) /* P:RW U:RW */ +#define MPU_RASR_AP_RO_NO (5 << 24) /* P:RO U:None */ +#define MPU_RASR_AP_RO_RO (6 << 24) /* P:RO U:RO */ + +#define MPU_RASR_RASR_XN (1 << 28) /* Bit 28: Instruction access disable */ + +#define MPU_RASR_SRD_MASK (0xff << 8) +#define MPU_RASR_SRD_0 (0x01 << 8) +#define MPU_RASR_SRD_1 (0x02 << 8) +#define MPU_RASR_SRD_2 (0x04 << 8) +#define MPU_RASR_SRD_3 (0x08 << 8) +#define MPU_RASR_SRD_4 (0x10 << 8) +#define MPU_RASR_SRD_5 (0x20 << 8) +#define MPU_RASR_SRD_6 (0x40 << 8) +#define MPU_RASR_SRD_7 (0x80 << 8) + +#define MPU_RASR_TEX_SHIFT (19) /* Bits 19-21: TEX Address Permission */ +#define MPU_RASR_TEX_MASK (7 << 19) +#define MPU_RASR_TEX_0 (0 << 19) /* Strongly Ordered */ +#define MPU_RASR_TEX_1 (1 << 19) /* Normal */ +#define MPU_RASR_TEX_2 (2 << 19) /* Device */ +#define MPU_RASR_TEX_BB(bb) ((4|(bb)) << 19) + +#define MPU_RASR_B (1 << 16) /* Bit 16: Bufferable */ +#define MPU_RASR_C (1 << 17) /* Bit 17: Cacheable */ +#define MPU_RASR_S (1 << 18) /* Bit 18: Shareable */ + +struct MpuConfig +{ + uint32_t rasr; + uint32_t rbar; +}; + +struct MpuRegion +{ + x_base start; + x_base size; + struct MpuConfig config; +}; + +struct Mpu +{ + + uint8_t count; + struct MpuRegion region[MPU_MAX_REGION_NUM]; +}; + + +void MpuEnable( uint32_t option); +void MpuDisable(void); +x_err_t MpuInit(void **task_mpu); +void MpuLoad(void *task_mpu); + +#endif diff --git a/Ubiquitous/XiZi/arch/arm/cortex-m4/svc_entry.S b/Ubiquitous/XiZi/arch/arm/cortex-m4/svc_entry.S new file mode 100644 index 0000000..e8f06c4 --- /dev/null +++ b/Ubiquitous/XiZi/arch/arm/cortex-m4/svc_entry.S @@ -0,0 +1,81 @@ + /* +* Copyright (c) 2020 AIIT XUOS Lab +* XiUOS is licensed under Mulan PSL v2. +* You can use this software according to the terms and conditions of the Mulan PSL v2. +* You may obtain a copy of Mulan PSL v2 at: +* http://license.coscl.org.cn/MulanPSL2 +* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, +* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, +* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. +* See the Mulan PSL v2 for more details. +*/ + + #include + + .globl SVC_Entry + .syntax unified + .thumb + .file "svc_entry.S" + + .text + .type SVC_Entry, %function + .thumb_func +SVC_Entry: + MRS r3, PRIMASK + CPSID I + MRS r0, ipsr + MRS r1, psp /* R1=The process stack pointer (PSP) */ + + STMDB r1!, {r3-r11} /* Save the remaining registers plus the SP/PRIMASK values */ + +#if defined (__VFP_FP__) && !defined(__SOFTFP__) + MOV r2, #0x00 + TST lr, #0x10 + MOVEQ r2, #0x01 + STMFD r1!, {r2} +#endif + PUSH {lr} + BL Svcall /* R0=IRQ, R1=register save (msp) */ + POP {lr} + + MOV r1, r0 + +#ifdef TASK_ISOLATION + PUSH {lr} + BL GetTaskPrivilege + POP {lr} +#endif + +#if defined (__VFP_FP__) && !defined(__SOFTFP__) + LDMFD r1!, {r2} +#endif + + LDMIA r1!, {r3-r11} /* Recover R4-R11, FPU flag and PRIMASK*/ + +#if defined (__VFP_FP__) && !defined(__SOFTFP__) + ORR lr, lr, #0x10 + CMP r2, #0 + BICNE lr, lr, #0x10 +#endif + MSR psp, r1 + MRS r2, control + +#ifdef TASK_ISOLATION + CMP r0, #1 + BEQ unprivilege + +privilege: + BIC r2, r2, #0x01 + B exit + +unprivilege: + ORR r2, r2, #0x01 +#else + BIC r2, r2, #0x01 +#endif + +exit: + MSR control, r2 + ORR lr, lr, #0x04 + MSR PRIMASK, r3 + BX lr \ No newline at end of file diff --git a/Ubiquitous/XiZi/arch/arm/cortex-m4/svc_handle.c b/Ubiquitous/XiZi/arch/arm/cortex-m4/svc_handle.c new file mode 100644 index 0000000..b5b91d3 --- /dev/null +++ b/Ubiquitous/XiZi/arch/arm/cortex-m4/svc_handle.c @@ -0,0 +1,92 @@ +/* +* Copyright (c) 2020 AIIT XUOS Lab +* XiUOS is licensed under Mulan PSL v2. +* You can use this software according to the terms and conditions of the Mulan PSL v2. +* You may obtain a copy of Mulan PSL v2 at: +* http://license.coscl.org.cn/MulanPSL2 +* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, +* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, +* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. +* See the Mulan PSL v2 for more details. +*/ + +#include +#include +#include "svc_handle.h" +#include +#include + +static void SvcDispatch(void) __attribute__ ((naked, no_instrument_function)); +static void SvcDispatch(void) +{ + __asm__ __volatile__ + ( + " mov r12, sp\n" + " sub r12, r12, #36\n" + " and r12, r12, #7\n" + " add r12, r12, #36\n" + " sub sp, sp, r12\n" + " str r0, [sp, #0]\n" + " str r1, [sp, #4]\n" + " str r2, [sp, #8]\n" + " str r3, [sp, #12]\n" + " str r4, [sp, #16]\n" + " str r5, [sp, #20]\n" + " str r6, [sp, #24]\n" + " str lr, [sp, #28]\n" + " str r12, [sp, #32]\n" + " mov r0, sp\n" + " ldr r12, =SvcHandle\n" + " blx r12\n" + " ldr lr, [sp, #28]\n" + " ldr r2, [sp, #32]\n" + " add sp, sp, r2\n" + " svc 1" + ); +} + + +void _svcall(uintptr_t* contex) +{ + uint32_t svc_number; + KTaskDescriptorType tid; + + tid = GetKTaskDescriptor(); + svc_number = ((char *)contex[REG_INT_PC ])[-2]; + switch (svc_number) { + case 0: //svc handler + tid->task_dync_sched_member.svc_return = contex[REG_INT_PC]; + tid->task_dync_sched_member.isolation_status = 1; + contex[REG_INT_PC] = (uint32_t)SvcDispatch & ~1; + break; + case 1: // svc return + contex[REG_INT_PC] = tid->task_dync_sched_member.svc_return; + tid->task_dync_sched_member.isolation_status = 0; + break; + default: + KPrintf("unsurport svc call number :%d\n",svc_number); + break; + } +} + +uintptr_t SvcHandle(uintptr_t *sp) +{ + uint32_t service_num = 0; + service_num = ((uint32_t) sp[0]); //r0 + uint8_t param_num = g_service_table[service_num].param_num; + uintptr_t *param = sp + 1; + return g_service_table[service_num].fun(service_num,param,param_num) ; +} + + +uint32_t GetTaskPrivilege(void){ + uint32_t unprivileg = 0; + struct TaskDescriptor *task = GetKTaskDescriptor(); + if (task->task_dync_sched_member.isolation_flag == 1 && task->task_dync_sched_member.isolation_status == 0) { + unprivileg = 1; + } else { + unprivileg = 0; + } + + return unprivileg; +} diff --git a/Ubiquitous/XiZi/arch/arm/cortex-m7/Makefile b/Ubiquitous/XiZi/arch/arm/cortex-m7/Makefile new file mode 100644 index 0000000..cc89c7f --- /dev/null +++ b/Ubiquitous/XiZi/arch/arm/cortex-m7/Makefile @@ -0,0 +1,3 @@ +SRC_FILES := boot.S interrupt.c interrupt_vector.S + +include $(KERNEL_ROOT)/compiler.mk diff --git a/Ubiquitous/XiZi/arch/arm/cortex-m7/arch_interrupt.h b/Ubiquitous/XiZi/arch/arm/cortex-m7/arch_interrupt.h new file mode 100644 index 0000000..f759206 --- /dev/null +++ b/Ubiquitous/XiZi/arch/arm/cortex-m7/arch_interrupt.h @@ -0,0 +1,38 @@ +/* +* Copyright (c) 2020 AIIT XUOS Lab +* XiUOS is licensed under Mulan PSL v2. +* You can use this software according to the terms and conditions of the Mulan PSL v2. +* You may obtain a copy of Mulan PSL v2 at: +* http://license.coscl.org.cn/MulanPSL2 +* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, +* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, +* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. +* See the Mulan PSL v2 for more details. +*/ + +#ifndef ARCH_INTERRUPT_H__ +#define ARCH_INTERRUPT_H__ + +#include + +#define ARCH_MAX_IRQ_NUM (256) + +//#define ARCH_IRQ_NUM_OFFSET 0 + +//#define SYSTICK_IRQN 15 +//#define UART1_IRQn 36 +//#define UART2_IRQn 37 + +#define ARCH_IRQ_NUM_OFFSET 16 + +#define SYSTICK_IRQN -1 +#define UART1_IRQn 20 +#define UART2_IRQn 21 + +#define USB1_IRQn 113 +#define USB2_IRQn 112 + +int32 ArchEnableHwIrq(uint32 irq_num); +int32 ArchDisableHwIrq(uint32 irq_num); + +#endif diff --git a/Ubiquitous/XiZi/arch/arm/cortex-m7/interrupt.c b/Ubiquitous/XiZi/arch/arm/cortex-m7/interrupt.c new file mode 100644 index 0000000..db1f458 --- /dev/null +++ b/Ubiquitous/XiZi/arch/arm/cortex-m7/interrupt.c @@ -0,0 +1,83 @@ +/* +* Copyright (c) 2020 AIIT XUOS Lab +* XiUOS is licensed under Mulan PSL v2. +* You can use this software according to the terms and conditions of the Mulan PSL v2. +* You may obtain a copy of Mulan PSL v2 at: +* http://license.coscl.org.cn/MulanPSL2 +* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, +* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, +* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. +* See the Mulan PSL v2 for more details. +*/ + +/** +* @file interrupt.c +* @brief support arm cortex-m7 interrupt function +* @version 1.0 +* @author AIIT XUOS Lab +* @date 2021-05-28 +*/ + +#include +#include + + +x_base __attribute__((naked)) DisableLocalInterrupt() +{ + asm volatile ("MRS r0, PRIMASK"); + asm volatile ("CPSID I"); + asm volatile ("BX LR "); +} + +void __attribute__((naked)) EnableLocalInterrupt(x_base level) +{ + asm volatile ("MSR PRIMASK, r0"); + asm volatile ("BX LR"); +} + +int32 ArchEnableHwIrq(uint32 irq_num) +{ + return EOK; +} + +int32 ArchDisableHwIrq(uint32 irq_num) +{ + return EOK; +} + +extern void KTaskOsAssignAfterIrq(void *context); + +void IsrEntry() +{ + uint32 ipsr; + + __asm__ volatile("MRS %0, IPSR" : "=r"(ipsr)); + isrManager.done->incCounter(); + isrManager.done->handleIrq(ipsr); + KTaskOsAssignAfterIrq(NONE); + isrManager.done->decCounter(); + +} + +void UsageFault_Handler(int irqn, void *arg) +{ + /* Go to infinite loop when Usage Fault exception occurs */ + while (1) + { + } +} + +void BusFault_Handler(int irqn, void *arg) +{ + /* Go to infinite loop when Bus Fault exception occurs */ + while (1) + { + } +} + +void NMI_Handler(int irqn, void *arg) +{ + while (1) + { + } +} diff --git a/Ubiquitous/XiZi/arch/arm/shared/Makefile b/Ubiquitous/XiZi/arch/arm/shared/Makefile new file mode 100644 index 0000000..9edf7d3 --- /dev/null +++ b/Ubiquitous/XiZi/arch/arm/shared/Makefile @@ -0,0 +1,4 @@ +SRC_FILES := pendsv.S prepare_ahwstack.c arm32_switch.c + + +include $(KERNEL_ROOT)/compiler.mk diff --git a/Ubiquitous/XiZi/arch/arm/shared/arm32_switch.c b/Ubiquitous/XiZi/arch/arm/shared/arm32_switch.c new file mode 100644 index 0000000..09ee4bb --- /dev/null +++ b/Ubiquitous/XiZi/arch/arm/shared/arm32_switch.c @@ -0,0 +1,175 @@ +/* +* Copyright (c) 2020 AIIT XUOS Lab +* XiUOS is licensed under Mulan PSL v2. +* You can use this software according to the terms and conditions of the Mulan PSL v2. +* You may obtain a copy of Mulan PSL v2 at: +* http://license.coscl.org.cn/MulanPSL2 +* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, +* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, +* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. +* See the Mulan PSL v2 for more details. +*/ + +#include +#include + +#define SCB_VTOR "0xE000ED08" +#define NVIC_INT_CTRL "0xE000ED04" +#define NVIC_SYSPRI2 "0xE000ED20" +#define NVIC_PENDSV_PRI "0x00FF0000" +#define NVIC_PENDSVSET "0x10000000" + +void __attribute__((naked)) HwInterruptcontextSwitch(x_ubase from, x_ubase to, struct TaskDescriptor *to_task, void *context) +{ + asm volatile ("PUSH {R4}"); + asm volatile ("PUSH {R5}"); + + asm volatile ("LDR r4, =KtaskSwitchInterruptFlag"); + asm volatile ("LDR r5, [r4]"); + asm volatile ("CMP r5, #1"); + + asm volatile ("POP {R5}"); + asm volatile ("POP {R4}"); + + asm volatile ("BEQ Arm32SwitchReswitch"); + + asm volatile ("PUSH {R4}"); + asm volatile ("PUSH {R5}"); + asm volatile ("LDR r4, =KtaskSwitchInterruptFlag"); + + asm volatile ("MOV r5, #1"); + asm volatile ("STR r5, [r4]"); + asm volatile ("LDR r4, =InterruptFromKtask"); + asm volatile ("STR r0, [r4]"); + + asm volatile ("POP {R5}"); + asm volatile ("POP {R4}"); + + asm volatile ("B Arm32SwitchReswitch"); +} + +void __attribute__((naked)) Arm32SwitchReswitch() +{ + asm volatile ("PUSH {R4}"); + + asm volatile ("LDR r4, =InterruptToKtask"); + asm volatile ("STR r1, [r4]"); + asm volatile ("LDR r4, =InterruptToKtaskDescriptor"); + asm volatile ("STR r2, [r4]"); + asm volatile ("LDR r0, =" NVIC_INT_CTRL); + asm volatile ("LDR r1, =" NVIC_PENDSVSET); + asm volatile ("STR r1, [r0]"); + + asm volatile ("POP {R4}"); + + asm volatile ("BX LR"); +} + +void __attribute__((naked)) SwitchKtaskContext(x_ubase from, x_ubase to, struct TaskDescriptor *to_task) +{ + asm volatile("B HwInterruptcontextSwitch"); +} + +void __attribute__((naked)) SwitchKtaskContextTo(x_ubase to, struct TaskDescriptor *to_task) +{ + asm volatile ("LDR r2, =InterruptToKtask"); + asm volatile ("STR r0, [r2]"); + asm volatile ("LDR r2, =InterruptToKtaskDescriptor"); + asm volatile ("STR r1, [r2]"); +#if defined (__VFP_FP__) && !defined(__SOFTFP__) + asm volatile ("MRS r2, CONTROL"); + asm volatile ("BIC r2, #0x04"); + asm volatile ("MSR CONTROL, r2"); +#endif + asm volatile ("LDR r1, =InterruptFromKtask"); + asm volatile ("MOV r0, #0x0"); + asm volatile ("STR r0, [r1]"); + asm volatile ("LDR r1, =KtaskSwitchInterruptFlag"); + asm volatile ("MOV r0, #1"); + asm volatile ("STR r0, [r1]"); + asm volatile ("LDR r0, =" NVIC_SYSPRI2); + asm volatile ("LDR r1, =" NVIC_PENDSV_PRI); + asm volatile ("LDR.W r2, [r0,#0x00]"); + asm volatile ("ORR r1,r1,r2"); + asm volatile ("STR r1, [r0]"); + asm volatile ("LDR r0, =" NVIC_INT_CTRL); + asm volatile ("LDR r1, =" NVIC_PENDSVSET); + asm volatile ("STR r1, [r0]"); + asm volatile ("LDR r0, =" SCB_VTOR); + asm volatile ("LDR r0, [r0]"); + asm volatile ("LDR r0, [r0]"); + asm volatile ("NOP"); + asm volatile ("MSR msp, r0"); + asm volatile ("CPSIE F"); + asm volatile ("CPSIE I"); + asm volatile ("BX lr"); +} + +void __attribute__((naked)) HardFaultHandler() +{ + asm volatile ("MRS r0, msp"); + asm volatile ("TST lr, #0x04"); + asm volatile ("BEQ Arm32SwitchGetSpDone"); + asm volatile ("MRS r0, psp"); + asm volatile ("B Arm32SwitchGetSpDone"); +} + +void __attribute__((naked)) Arm32SwitchGetSpDone() +{ + asm volatile ("MRS r3, primask"); + asm volatile ("STMFD r0!, {r3 - r11}"); + asm volatile ("STMFD r0!, {lr}"); +#if defined (__VFP_FP__) && !defined(__SOFTFP__) + asm volatile ("MOV r4, #0x00"); + asm volatile ("TST lr, #0x10"); + asm volatile ("MOVEQ r4, #0x01"); + asm volatile ("STMFD r0!, {r4}"); +#endif + asm volatile ("TST lr, #0x04"); + asm volatile ("BEQ Arm32SwitchUpdateMsp"); + asm volatile ("MSR psp, r0"); + asm volatile ("B Arm32SwitchUpdateDone"); + asm volatile ("B Arm32SwitchUpdateMsp"); +} + +void __attribute__((naked)) Arm32SwitchUpdateMsp() +{ + asm volatile ("MSR msp, r0"); + asm volatile ("B Arm32SwitchUpdateDone"); +} + +void __attribute__((naked)) Arm32SwitchUpdateDone() +{ + asm volatile ("PUSH {LR}"); + asm volatile ("BL HwHardFaultException"); + asm volatile ("POP {LR}"); + asm volatile ("ORR lr, lr, #0x04"); + asm volatile ("BX lr"); +} + +void __attribute__((naked)) MemFaultHandler() +{ + asm volatile ("MRS r0, msp"); + asm volatile ("TST lr, #0x04"); + asm volatile ("BEQ Arm32Switch1"); + asm volatile ("MRS r0, psp"); + asm volatile ("B Arm32Switch1"); +} + +void __attribute__((naked)) Arm32Switch1() +{ + asm volatile ("MRS r3, primask"); + asm volatile ("STMFD r0!, {r3 - r11}"); +#if defined (__VFP_FP__) && !defined(__SOFTFP__) + asm volatile ("MOV r4, #0x00"); + asm volatile ("TST lr, #0x10"); + asm volatile ("MOVEQ r4, #0x01"); + asm volatile ("STMFD r0!, {r4}"); +#endif + asm volatile ("STMFD r0!, {lr}"); + asm volatile ("PUSH {LR}"); + asm volatile ("BL MemFaultHandle"); + asm volatile ("POP {LR}"); + asm volatile ("ORR lr, lr, #0x04"); + asm volatile ("BX lr"); +} diff --git a/Ubiquitous/XiZi/arch/arm/shared/prepare_ahwstack.c b/Ubiquitous/XiZi/arch/arm/shared/prepare_ahwstack.c new file mode 100644 index 0000000..57935a8 --- /dev/null +++ b/Ubiquitous/XiZi/arch/arm/shared/prepare_ahwstack.c @@ -0,0 +1,413 @@ +/* +* Copyright (c) 2020 AIIT XUOS Lab +* XiUOS is licensed under Mulan PSL v2. +* You can use this software according to the terms and conditions of the Mulan PSL v2. +* You may obtain a copy of Mulan PSL v2 at: +* http://license.coscl.org.cn/MulanPSL2 +* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, +* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, +* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. +* See the Mulan PSL v2 for more details. +*/ + +#include +#include +#include +#include "svc_handle.h" +#include +#ifdef TOOL_SHELL +#include +#endif + +#if (defined ( __GNUC__ ) && defined ( __VFP_FP__ ) && !defined(__SOFTFP__)) +#define USE_FPU 1 +#else +#define USE_FPU 0 +#endif + +uint32 InterruptFromKtask; +uint32 InterruptToKtask; +uint32 KtaskSwitchInterruptFlag; +uint32 InterruptToKtaskDescriptor; +#define RunningKTask Assign.os_running_task + +static x_err_t (*ExceptionHook)(void *context) = NONE; + +struct ExceptionStackRegister +{ + uint32 r0; + uint32 r1; + uint32 r2; + uint32 r3; + uint32 r12; + uint32 lr; + uint32 pc; + uint32 psr; +}; + +struct StackRegisterContent +{ +#if defined ( __VFP_FP__ ) && !defined(__SOFTFP__) + uint32 flag; +#endif + uint32 primask; + uint32 r4; + uint32 r5; + uint32 r6; + uint32 r7; + uint32 r8; + uint32 r9; + uint32 r10; + uint32 r11; + // uint32 exc_ret; + + struct ExceptionStackRegister ExErrorStackContex; +}; + +struct ExceptionStackFrameFpu +{ + uint32 r0; + uint32 r1; + uint32 r2; + uint32 r3; + uint32 r12; + uint32 lr; + uint32 pc; + uint32 psr; + +#if USE_FPU + uint32 S0; + uint32 S1; + uint32 S2; + uint32 S3; + uint32 S4; + uint32 S5; + uint32 S6; + uint32 S7; + uint32 S8; + uint32 S9; + uint32 S10; + uint32 S11; + uint32 S12; + uint32 S13; + uint32 S14; + uint32 S15; + uint32 FPSCR; + uint32 NO_NAME; +#endif +}; + +struct StackFrameFpu +{ + uint32 flag; + + uint32 r4; + uint32 r5; + uint32 r6; + uint32 r7; + uint32 r8; + uint32 r9; + uint32 r10; + uint32 r11; + +#if USE_FPU + uint32 s16; + uint32 s17; + uint32 s18; + uint32 s19; + uint32 s20; + uint32 s21; + uint32 s22; + uint32 s23; + uint32 s24; + uint32 s25; + uint32 s26; + uint32 s27; + uint32 s28; + uint32 s29; + uint32 s30; + uint32 s31; +#endif + + struct ExceptionStackFrameFpu ExErrorStackContex; +}; + +uint8 KTaskStackSetup(struct TaskDescriptor *task) +{ + struct StackRegisterContent* StackContex; + int i = 0; + + task->stack_point = (uint8 *)ALIGN_MEN_DOWN((x_ubase)(task->task_base_info.stack_start + task->task_base_info.stack_depth), 8); + task->stack_point -= sizeof(struct StackRegisterContent); + + StackContex = (struct StackRegisterContent*)task->stack_point; + + for (i = 0; i < sizeof(struct StackRegisterContent) / sizeof(uint32); i++) + ((uint32 *)StackContex)[i] = 0xfadeface; + + StackContex->ExErrorStackContex.r0 = (unsigned long)task->task_base_info.func_param; + + StackContex->ExErrorStackContex.pc = (unsigned long)task->task_base_info.func_entry ; + StackContex->ExErrorStackContex.psr = 0x01000000L; + StackContex->primask = 0x00000000L; +#ifdef SEPARATE_COMPILE + if(task->task_dync_sched_member.isolation_flag == 1 ) { + StackContex->ExErrorStackContex.lr = (unsigned long)USERSPACE->us_taskquit; + } else { + StackContex->ExErrorStackContex.lr = (unsigned long)KTaskQuit; + } +#else + StackContex->ExErrorStackContex.lr = (unsigned long)KTaskQuit; +#endif + +#if USE_FPU + StackContex->flag = 0; +#endif + + return EOK; +} + + +void HwExceptionInstall(x_err_t (*exception_handle)(void *context)) +{ + ExceptionHook = exception_handle; +} + +#define SCB_CFSR (*(volatile const unsigned *)0xE000ED28) +#define SCB_HFSR (*(volatile const unsigned *)0xE000ED2C) +#define SCB_MMAR (*(volatile const unsigned *)0xE000ED34) +#define SCB_BFAR (*(volatile const unsigned *)0xE000ED38) +#define SCB_AIRCR (*(volatile unsigned long *)0xE000ED0C) +#define SCB_RESET_VALUE 0x05FA0004 + +#define SCB_CFSR_MFSR (*(volatile const unsigned char*)0xE000ED28) +#define SCB_CFSR_BFSR (*(volatile const unsigned char*)0xE000ED29) +#define SCB_CFSR_UFSR (*(volatile const unsigned short*)0xE000ED2A) + +#ifdef TOOL_SHELL +static void UsageFaultTrack(void) +{ + KPrintf("usage fault:\n"); + KPrintf("SCB_CFSR_UFSR:0x%02X ", SCB_CFSR_UFSR); + + if(SCB_CFSR_UFSR & (1<<0)) + KPrintf("UNDEFINSTR "); + + if(SCB_CFSR_UFSR & (1<<1)) + KPrintf("INVSTATE "); + + if(SCB_CFSR_UFSR & (1<<2)) + KPrintf("INVPC "); + + if(SCB_CFSR_UFSR & (1<<3)) + KPrintf("NOCP "); + + if(SCB_CFSR_UFSR & (1<<8)) + KPrintf("UNALIGNED "); + + if(SCB_CFSR_UFSR & (1<<9)) + KPrintf("DIVBYZERO "); + + KPrintf("\n"); +} + +static void BusFaultTrack(void) +{ + KPrintf("bus fault:\n"); + KPrintf("SCB_CFSR_BFSR:0x%02X ", SCB_CFSR_BFSR); + + if(SCB_CFSR_BFSR & (1<<0)) + KPrintf("IBUSERR "); + + if(SCB_CFSR_BFSR & (1<<1)) + KPrintf("PRECISERR "); + + if(SCB_CFSR_BFSR & (1<<2)) + KPrintf("IMPRECISERR "); + + if(SCB_CFSR_BFSR & (1<<3)) + KPrintf("UNSTKERR "); + + if(SCB_CFSR_BFSR & (1<<4)) + KPrintf("STKERR "); + + if(SCB_CFSR_BFSR & (1<<7)) + KPrintf("SCB->BFAR:%08X\n", SCB_BFAR); + else + KPrintf("\n"); +} + +static void MemManageFaultTrack(void) +{ + KPrintf("mem manage fault:\n"); + KPrintf("SCB_CFSR_MFSR:0x%02X ", SCB_CFSR_MFSR); + + if(SCB_CFSR_MFSR & (1<<0)) + KPrintf("IACCVIOL "); + if(SCB_CFSR_MFSR & (1<<1)) + KPrintf("DACCVIOL "); + + if(SCB_CFSR_MFSR & (1<<3)) + KPrintf("MUNSTKERR "); + + if(SCB_CFSR_MFSR & (1<<4)) + KPrintf("MSTKERR "); + + if(SCB_CFSR_MFSR & (1<<7)) + KPrintf("SCB->MMAR:%08X\n", SCB_MMAR); + else + KPrintf("\n"); +} + +static void HardFaultTrack(void) +{ + if(SCB_HFSR & (1UL<<1)) + KPrintf("failed vector fetch\n"); + + if(SCB_HFSR & (1UL<<30)) { + if(SCB_CFSR_BFSR) + BusFaultTrack(); + + if(SCB_CFSR_MFSR) + MemManageFaultTrack(); + + if(SCB_CFSR_UFSR) + UsageFaultTrack(); + } + + if(SCB_HFSR & (1UL<<31)) + KPrintf("debug event\n"); +} +#endif + +struct ExceptionInfo +{ + uint32 ExcReturn; + struct StackRegisterContent stackframe; +}; + +void HwHardFaultException(struct ExceptionInfo *ExceptionInfo) +{ + extern long ShowTask(void); + struct ExErrorStackContex* ExceptionStack = (struct ExErrorStackContex*)&ExceptionInfo->stackframe.ExErrorStackContex; + struct StackRegisterContent* context = (struct StackRegisterContent*)&ExceptionInfo->stackframe; + + if (ExceptionHook != NONE) { + x_err_t result = ExceptionHook(ExceptionStack); + if (result == EOK) return; + } + + KPrintf("psr: 0x%08x\n", context->ExErrorStackContex.psr); + KPrintf("r00: 0x%08x\n", context->ExErrorStackContex.r0); + KPrintf("r01: 0x%08x\n", context->ExErrorStackContex.r1); + KPrintf("r02: 0x%08x\n", context->ExErrorStackContex.r2); + KPrintf("r03: 0x%08x\n", context->ExErrorStackContex.r3); + KPrintf("r04: 0x%08x\n", context->r4); + KPrintf("r05: 0x%08x\n", context->r5); + KPrintf("r06: 0x%08x\n", context->r6); + KPrintf("r07: 0x%08x\n", context->r7); + KPrintf("r08: 0x%08x\n", context->r8); + KPrintf("r09: 0x%08x\n", context->r9); + KPrintf("r10: 0x%08x\n", context->r10); + KPrintf("r11: 0x%08x\n", context->r11); + //KPrintf("exc_ret: 0x%08x\n", context->exc_ret); + KPrintf("r12: 0x%08x\n", context->ExErrorStackContex.r12); + KPrintf(" lr: 0x%08x\n", context->ExErrorStackContex.lr); + KPrintf(" pc: 0x%08x\n", context->ExErrorStackContex.pc); + + if (ExceptionInfo->ExcReturn & (1 << 2)) { + KPrintf("hard fault on task: %s\r\n\r\n", GetKTaskDescriptor()->task_base_info.name); +#ifdef TOOL_SHELL + ShowTask(); +#endif + } else { + KPrintf("hard fault on handler\r\n\r\n"); + } + + if ( (ExceptionInfo->ExcReturn & 0x10) == 0) + KPrintf("FPU active!\r\n"); + +#ifdef TOOL_SHELL + HardFaultTrack(); +#endif + + while (1); +} + +void UpdateRunningTask(void) +{ + RunningKTask = (struct TaskDescriptor *)InterruptToKtaskDescriptor; +} + + +void MemFaultExceptionPrint(struct ExceptionInfo *ExceptionInfo) +{ + extern long ShowTask(void); + struct ExErrorStackContex* ExceptionStack = (struct ExErrorStackContex*)&ExceptionInfo->stackframe.ExErrorStackContex; + struct StackRegisterContent* context = (struct StackRegisterContent*)&ExceptionInfo->stackframe; + + if (ExceptionHook != NONE) { + x_err_t result = ExceptionHook(ExceptionStack); + if (result == EOK) return; + } + + KPrintf("psr: 0x%08x\n", context->ExErrorStackContex.psr); + KPrintf("r00: 0x%08x\n", context->ExErrorStackContex.r0); + KPrintf("r01: 0x%08x\n", context->ExErrorStackContex.r1); + KPrintf("r02: 0x%08x\n", context->ExErrorStackContex.r2); + KPrintf("r03: 0x%08x\n", context->ExErrorStackContex.r3); + KPrintf("r04: 0x%08x\n", context->r4); + KPrintf("r05: 0x%08x\n", context->r5); + KPrintf("r06: 0x%08x\n", context->r6); + KPrintf("r07: 0x%08x\n", context->r7); + KPrintf("r08: 0x%08x\n", context->r8); + KPrintf("r09: 0x%08x\n", context->r9); + KPrintf("r10: 0x%08x\n", context->r10); + KPrintf("r11: 0x%08x\n", context->r11); + KPrintf("exc_ret: 0x%08x\n", ExceptionInfo->ExcReturn); + KPrintf("r12: 0x%08x\n", context->ExErrorStackContex.r12); + KPrintf(" lr: 0x%08x\n", context->ExErrorStackContex.lr); + KPrintf(" pc: 0x%08x\n", context->ExErrorStackContex.pc); + + if (ExceptionInfo->ExcReturn & (1 << 2)) { + KPrintf("hard fault on task: %s\r\n\r\n", GetKTaskDescriptor()->task_base_info.name); +#ifdef TOOL_SHELL + ShowTask(); +#endif + } else { + KPrintf("hard fault on handler\r\n\r\n"); + } + + if ((ExceptionInfo->ExcReturn & 0x10) == 0) + KPrintf("FPU active!\r\n"); + + +#ifdef TOOL_SHELL + HardFaultTrack(); +#endif + + while (1); +} + +void MemFaultHandle(uintptr_t *sp) +{ +#ifdef TASK_ISOLATION + struct TaskDescriptor *task; + task = GetKTaskDescriptor(); + if( task->task_dync_sched_member.isolation_flag == 1){ + KPrintf("\nSegmentation fault, task: %s\n", task->task_base_info.name); + KTaskQuit(); + } + else +#endif + { + MemFaultExceptionPrint((struct ExceptionInfo *)sp); + } + +} + +__attribute__((weak)) void HwCpuReset(void) +{ + SCB_AIRCR = SCB_RESET_VALUE; +} +SHELL_EXPORT_CMD(SHELL_CMD_PERMISSION(0)|SHELL_CMD_TYPE(SHELL_TYPE_CMD_FUNC)|SHELL_CMD_PARAM_NUM(0), Reboot, HwCpuReset, reset machine ); \ No newline at end of file diff --git a/Ubiquitous/XiZi/arch/arm/shared/svc_handle.h b/Ubiquitous/XiZi/arch/arm/shared/svc_handle.h new file mode 100644 index 0000000..1822417 --- /dev/null +++ b/Ubiquitous/XiZi/arch/arm/shared/svc_handle.h @@ -0,0 +1,58 @@ +/* +* Copyright (c) 2020 AIIT XUOS Lab +* XiUOS is licensed under Mulan PSL v2. +* You can use this software according to the terms and conditions of the Mulan PSL v2. +* You may obtain a copy of Mulan PSL v2 at: +* http://license.coscl.org.cn/MulanPSL2 +* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, +* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, +* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. +* See the Mulan PSL v2 for more details. +*/ + +#ifndef __INC_SVC_HANDLE_H__ +#define __INC_SVC_HANDLE_H__ + +#if defined ( __VFP_FP__ ) && !defined(__SOFTFP__) +#define INT_FPU_REGS (1) +#else +#define INT_FPU_REGS (0) +#endif + +#define HW_INT_REGS (8) +#define SW_INT_REGS (9 + INT_FPU_REGS) + +#define REG_INT_R0 (SW_INT_REGS + 0) /* R0 */ +#define REG_INT_R1 (SW_INT_REGS + 1) /* R1 */ +#define REG_INT_R2 (SW_INT_REGS + 2) /* R2 */ +#define REG_INT_R3 (SW_INT_REGS + 3) /* R3 */ +#define REG_INT_R12 (SW_INT_REGS + 4) /* R12 */ +#define REG_INT_R14 (SW_INT_REGS + 5) /* R14 = LR */ +#define REG_INT_PC (SW_INT_REGS + 6) /* R15 = PC */ +#define REG_INT_XPSR (SW_INT_REGS + 7) /* xPSR */ + +#if defined ( __VFP_FP__ ) && !defined(__SOFTFP__) +#define REG_INT_FPU_FLAG (0) /* fpu flag */ +#define REG_INT_PRIMASK (1) /* PRIMASK */ +#define REG_INT_R4 (2) /* R4 */ +#define REG_INT_R5 (3) /* R5 */ +#define REG_INT_R6 (4) /* R6 */ +#define REG_INT_R7 (5) /* R7 */ +#define REG_INT_R8 (6) /* R8 */ +#define REG_INT_R9 (7) /* R9 */ +#define REG_INT_R10 (8) /* R10 */ +#define REG_INT_R11 (9) /* R11 */ +#else +#define REG_INT_PRIMASK (0) /* PRIMASK */ +#define REG_INT_R4 (1) /* R4 */ +#define REG_INT_R5 (2) /* R5 */ +#define REG_INT_R6 (3) /* R6 */ +#define REG_INT_R7 (4) /* R7 */ +#define REG_INT_R8 (5) /* R8 */ +#define REG_INT_R9 (6) /* R9 */ +#define REG_INT_R10 (7) /* R10 */ +#define REG_INT_R11 (8) /* R11 */ +#endif + + +#endif diff --git a/Ubiquitous/XiZi/arch/kswitch.h b/Ubiquitous/XiZi/arch/kswitch.h new file mode 100644 index 0000000..f4d118b --- /dev/null +++ b/Ubiquitous/XiZi/arch/kswitch.h @@ -0,0 +1,28 @@ +/* +* Copyright (c) 2020 AIIT XUOS Lab +* XiUOS is licensed under Mulan PSL v2. +* You can use this software according to the terms and conditions of the Mulan PSL v2. +* You may obtain a copy of Mulan PSL v2 at: +* http://license.coscl.org.cn/MulanPSL2 +* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, +* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, +* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. +* See the Mulan PSL v2 for more details. +*/ + +#ifndef __KSWITCH_H__ +#define __KSWITCH_H__ + +#ifdef SEPARATE_COMPILE + +#if defined(ARCH_RISCV) +#include "risc-v/shared/kswitch.h" +#endif + +#if defined(ARCH_ARM) +#include "arm/cortex-m4/kswitch.h" +#endif + +#endif + +#endif \ No newline at end of file diff --git a/Ubiquitous/XiZi/arch/risc-v/Makefile b/Ubiquitous/XiZi/arch/risc-v/Makefile new file mode 100755 index 0000000..0d445c7 --- /dev/null +++ b/Ubiquitous/XiZi/arch/risc-v/Makefile @@ -0,0 +1,31 @@ +SRC_DIR := shared + +ifeq ($(CONFIG_BOARD_FE310_EVB),y) +SRC_DIR +=fe310 +endif + +ifeq ($(CONFIG_BOARD_K210_EVB),y) +SRC_DIR +=k210 +endif + +ifeq ($(CONFIG_BOARD_MAIX_GO_EVB),y) +SRC_DIR +=k210 +endif + +ifeq ($(CONFIG_BOARD_AIIT_RISCV_EVB),y) +SRC_DIR +=k210 +endif + +ifeq ($(CONFIG_BOARD_GAPUINO),y) +SRC_DIR +=gap8 +endif + +ifeq ($(CONFIG_BOARD_GD32VF103RVSTAR),y) +SRC_DIR +=gd32vf103_rvstar +endif + +ifeq ($(CONFIG_BOARD_RV32M1_VEGA),y) +SRC_DIR +=rv32m1_vega +endif + +include $(KERNEL_ROOT)/compiler.mk diff --git a/Ubiquitous/XiZi/arch/risc-v/fe310/LICENSE b/Ubiquitous/XiZi/arch/risc-v/fe310/LICENSE new file mode 100644 index 0000000..0b0b6c8 --- /dev/null +++ b/Ubiquitous/XiZi/arch/risc-v/fe310/LICENSE @@ -0,0 +1,206 @@ + +This software, except as otherwise noted in subrepositories, +is licensed under the Apache 2 license, quoted below. + + + Apache License + Version 2.0, January 2004 + http://www.apache.org/licenses/ + + TERMS AND CONDITIONS FOR USE, REPRODUCTION, AND DISTRIBUTION + + 1. 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We also recommend that a + file or class name and description of purpose be included on the + same "printed page" as the copyright notice for easier + identification within third-party archives. + + Copyright 2016 SiFive, Inc. + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. diff --git a/Ubiquitous/XiZi/arch/risc-v/fe310/Makefile b/Ubiquitous/XiZi/arch/risc-v/fe310/Makefile new file mode 100644 index 0000000..902b4be --- /dev/null +++ b/Ubiquitous/XiZi/arch/risc-v/fe310/Makefile @@ -0,0 +1,3 @@ +SRC_FILES := interrupt.c boot.S tick.c + +include $(KERNEL_ROOT)/compiler.mk diff --git a/Ubiquitous/XiZi/arch/risc-v/fe310/arch_interrupt.h b/Ubiquitous/XiZi/arch/risc-v/fe310/arch_interrupt.h new file mode 100644 index 0000000..f34849e --- /dev/null +++ b/Ubiquitous/XiZi/arch/risc-v/fe310/arch_interrupt.h @@ -0,0 +1,28 @@ +/* +* Copyright (c) 2020 AIIT XUOS Lab +* XiUOS is licensed under Mulan PSL v2. +* You can use this software according to the terms and conditions of the Mulan PSL v2. +* You may obtain a copy of Mulan PSL v2 at: +* http://license.coscl.org.cn/MulanPSL2 +* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, +* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, +* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. +* See the Mulan PSL v2 for more details. +*/ + +#ifndef ARCH_INTERRUPT_H__ +#define ARCH_INTERRUPT_H__ + +#include +#include + +#define ARCH_MAX_IRQ_NUM IRQN_MAX +#define ARCH_IRQ_NUM_OFFSET 0 + +uint32_t GetInterruptNumber(void); +void HwInterruptAck(uint32_t irq); + +int32_t ArchEnableHwIrq(int irq_num); +int32_t ArchDisableHwIrq(int irq_num); + +#endif diff --git a/Ubiquitous/XiZi/arch/risc-v/fe310/interrupt.c b/Ubiquitous/XiZi/arch/risc-v/fe310/interrupt.c new file mode 100644 index 0000000..0ec6bf2 --- /dev/null +++ b/Ubiquitous/XiZi/arch/risc-v/fe310/interrupt.c @@ -0,0 +1,281 @@ +/* +* Copyright (c) 2020 AIIT XUOS Lab +* XiUOS is licensed under Mulan PSL v2. +* You can use this software according to the terms and conditions of the Mulan PSL v2. +* You may obtain a copy of Mulan PSL v2 at: +* http://license.coscl.org.cn/MulanPSL2 +* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, +* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, +* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. +* See the Mulan PSL v2 for more details. +*/ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#ifdef TASK_ISOLATION +#include +#include +#endif + +#define MAX_HANDLERS PLIC_NUM_INTERRUPTS +extern plic_instance_t g_plic ; + +x_base DisableLocalInterrupt() +{ + x_base level; + + asm volatile ("csrrci %0, mstatus, 8" : "=r"(level)); + + return level; +} + +void EnableLocalInterrupt(x_base level) +{ + asm volatile ("csrw mstatus, %0" :: "r"(level)); +} + + +/** + * This function will mask a interrupt. + * @param vector the interrupt number + */ +int32_t ArchDisableHwIrq(int irq) +{ + PLIC_disable_interrupt(&g_plic, irq); + return 0; +} + +/** + * This function will un-mask a interrupt. + * @param vector the interrupt number + */ +int32_t ArchEnableHwIrq(int irq) +{ + PLIC_enable_interrupt(&g_plic, irq); + PLIC_set_priority(&g_plic, irq, 1); + return 0; +} + +uint32_t GetInterruptNumber(void) +{ + return (uint32_t)PLIC_claim_interrupt(&g_plic); +} + +void HwInterruptAck(uint32_t irq) +{ + PLIC_complete_interrupt(&g_plic, irq); +} + +/** + * This function will be call when external machine-level + * interrupt from PLIC occurred. + */ +uintptr_t HandleIrqMExt(uintptr_t cause, uintptr_t epc) +{ + uint32_t irq; + + /* get irq number */ + irq = GetInterruptNumber(); + /* get interrupt service routine */ + isrManager.done->handleIrq(irq); + HwInterruptAck(irq); +} + +extern int TickIsr(void); + +#ifdef TASK_ISOLATION +uintptr_t HandleTrap(uintptr_t mcause, uintptr_t epc, uintptr_t * sp) +{ + int cause = mcause & MCAUSE_CAUSE ; + + if (mcause & MCAUSE_INT) { + isrManager.done->incCounter(); + switch (cause) { + case IRQ_M_EXT: + HandleIrqMExt(mcause, epc); + break; + case IRQ_M_TIMER: + CLINT_MTIMECMP_ADDR = CLINT_MTIME_ADDR + TICK; + TickIsr(); + break; + } + isrManager.done->decCounter(); + }else { + x_base temp; + temp = DISABLE_INTERRUPT(); + KTaskDescriptorType tid; + extern long ShowTask(); + tid = GetKTaskDescriptor(); + + if(cause == CAUSE_USER_ECALL) { + tid->task_dync_sched_member.isolation_status = 1; + sp[0] += 4; + unsigned long service_num = (unsigned long)(sp[10]); + //KPrintf("Environment call from U-mode,service_num: %ld\n",service_num); + uint8_t param_num = g_service_table[service_num].param_num; + uintptr_t *param = sp + 11; + ENABLE_INTERRUPT(temp); + sp[10] = g_service_table[service_num].fun(service_num,param,param_num) ; + tid->task_dync_sched_member.isolation_status = 0; + + } else if( cause == CAUSE_MACHINE_ECALL) { + unsigned long service_num = (unsigned long)(sp[10]); + KPrintf("Environment call from M-mode, task:%s, flag: %d,service_num: %d\n \n",tid->task_base_info.name,tid->task_dync_sched_member.isolation_flag, service_num); + sp[0] += 4; + ENABLE_INTERRUPT(temp); + } + else if (cause == CAUSE_FAULT_LOAD || cause == CAUSE_FAULT_STORE || cause == CAUSE_FAULT_FETCH ){ + if ( tid->task_dync_sched_member.isolation_flag == 1) { + x_ubase fault_addr = READ_CSR(mtval); + // KPrintf("access fault ,addr : 0x%08x\n",fault_addr); + x_bool result ; + result = mem_access.FaultHandle(tid->task_dync_sched_member.isolation , fault_addr); + if(result) + mem_access.Load(tid->task_dync_sched_member.isolation); + else{ + KPrintf("\nSegmentation fault, task: %s\n",tid->task_base_info.name); + KTaskQuit(); + } + }else + goto __print; + } + else + { + KPrintf("\nException:\n"); + tid = GetKTaskDescriptor(); + switch (cause) + { + case CAUSE_MISALIGNED_FETCH: + KPrintf("Instruction address misaligned"); + break; + case CAUSE_FAULT_FETCH: + KPrintf("Instruction access fault"); + break; + case CAUSE_ILLEGAL_INSTRUCTION: + KPrintf("Illegal instruction"); + break; + case CAUSE_BREAKPOINT: + KPrintf("Breakpoint"); + break; + case CAUSE_MISALIGNED_LOAD: + KPrintf("Load address misaligned"); + break; + case CAUSE_FAULT_LOAD: + KPrintf("Load access fault"); + break; + case CAUSE_MISALIGNED_STORE: + KPrintf("Store address misaligned"); + break; + case CAUSE_FAULT_STORE: + KPrintf("Store access fault"); + break; + case CAUSE_SUPERVISOR_ECALL: + KPrintf("Environment call from S-mode"); + break; + case CAUSE_HYPERVISOR_ECALL: + KPrintf("Environment call from H-mode"); + break; + default: + KPrintf("Uknown exception : %08lX", cause); + break; + } +__print: + KPrintf("\n"); + //PrintStackFrame(sp); + KPrintf("exception pc => 0x%08x\n", epc); + KPrintf("current thread: %.*s\n", NAME_NUM_MAX, tid->task_base_info.name); +#ifdef TOOL_SHELL + ShowTask(); +#endif + while(RET_TRUE); + } + } + return epc; +} +#else +uintptr_t HandleTrap(uintptr_t mcause, uintptr_t epc, uintptr_t * sp) +{ + int cause = mcause & MCAUSE_CAUSE ; + + if (mcause & MCAUSE_INT) + { + isrManager.done->incCounter(); + switch (cause) + { + case IRQ_M_EXT: + HandleIrqMExt(mcause, epc); + break; + case IRQ_M_TIMER: + CLINT_MTIMECMP_ADDR = CLINT_MTIME_ADDR + TICK; + TickIsr(); + break; + } + isrManager.done->decCounter(); + } + else + { + + KTaskDescriptorType tid; + extern long ShowTask(); + + + DISABLE_INTERRUPT(); + + tid = GetKTaskDescriptor(); + KPrintf("\nException:\n"); + switch (cause) + { + case CAUSE_MISALIGNED_FETCH: + KPrintf("Instruction address misaligned"); + break; + case CAUSE_FAULT_FETCH: + KPrintf("Instruction access fault"); + break; + case CAUSE_ILLEGAL_INSTRUCTION: + KPrintf("Illegal instruction"); + break; + case CAUSE_BREAKPOINT: + KPrintf("Breakpoint"); + break; + case CAUSE_MISALIGNED_LOAD: + KPrintf("Load address misaligned"); + break; + case CAUSE_FAULT_LOAD: + KPrintf("Load access fault"); + break; + case CAUSE_MISALIGNED_STORE: + KPrintf("Store address misaligned"); + break; + case CAUSE_FAULT_STORE: + KPrintf("Store access fault"); + break; + case CAUSE_SUPERVISOR_ECALL: + KPrintf("Environment call from S-mode"); + break; + case CAUSE_HYPERVISOR_ECALL: + KPrintf("Environment call from H-mode"); + break; + default: + KPrintf("Uknown exception : %08lX", cause); + break; + } + KPrintf("\n"); + //PrintStackFrame(sp); + KPrintf("exception pc => 0x%08x\n", epc); + KPrintf("current thread: %.*s\n", NAME_NUM_MAX, tid->task_base_info.name); +#ifdef TOOL_SHELL + ShowTask(); +#endif + while (RET_TRUE); + } + return epc; + } +#endif + diff --git a/Ubiquitous/XiZi/arch/risc-v/fe310/tick.c b/Ubiquitous/XiZi/arch/risc-v/fe310/tick.c new file mode 100644 index 0000000..f3f70b7 --- /dev/null +++ b/Ubiquitous/XiZi/arch/risc-v/fe310/tick.c @@ -0,0 +1,23 @@ +/* +* Copyright (c) 2020 AIIT XUOS Lab +* XiUOS is licensed under Mulan PSL v2. +* You can use this software according to the terms and conditions of the Mulan PSL v2. +* You may obtain a copy of Mulan PSL v2 at: +* http://license.coscl.org.cn/MulanPSL2 +* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, +* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, +* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. +* See the Mulan PSL v2 for more details. +*/ + +#include +#include +#include + +static volatile unsigned long tick_cycles = 0; +int TickIsr(void) +{ + TickAndTaskTimesliceUpdate(); + + return 0; +} \ No newline at end of file diff --git a/Ubiquitous/XiZi/arch/risc-v/gap8/Makefile b/Ubiquitous/XiZi/arch/risc-v/gap8/Makefile new file mode 100755 index 0000000..6ab88ed --- /dev/null +++ b/Ubiquitous/XiZi/arch/risc-v/gap8/Makefile @@ -0,0 +1,3 @@ +SRC_FILES := boot.S interrupt.c tick.c + +include $(KERNEL_ROOT)/compiler.mk diff --git a/Ubiquitous/XiZi/arch/risc-v/gap8/arch_interrupt.h b/Ubiquitous/XiZi/arch/risc-v/gap8/arch_interrupt.h new file mode 100755 index 0000000..e470877 --- /dev/null +++ b/Ubiquitous/XiZi/arch/risc-v/gap8/arch_interrupt.h @@ -0,0 +1,305 @@ +/**************************************************************************** + * arch/risc-v/include/gap8/irq.h + * GAP8 event system + * + * Copyright (C) 2018 Gregory Nutt. All rights reserved. + * Author: hhuysqt <1020988872@qq.com> + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * GAP8 features a FC controller and a 8-core cluster. IRQ from peripherals + * have unique ID, which are dispatched to the FC or cluster by the SOC + * event unit, and then by the FC event unit or cluster event unit, and + * finally to FC or cluster. Peripherals share the same IRQ entry. + ****************************************************************************/ +/** +* @file arch_interrupt.h +* @brief support gap8 interrupt +* @version 1.0 +* @author AIIT XUOS Lab +* @date 2021-09-02 +*/ + +/************************************************* +File name: arch_interrupt.h +Description: support gap8 interrupt +Others: take nuttx/arch/risc-v/include/gap8/irq.h for references + https://github.com/apache/incubator-nuttx.git +History: +1. Date: 2021-09-02 +Author: AIIT XUOS Lab +Modification: add interrupt function definition +*************************************************/ + +#ifndef ARCH_INTERRUPT_H__ +#define ARCH_INTERRUPT_H__ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +/**************************************************************************** + * Pre-Processor Definitions + ****************************************************************************/ + +/* Unique ID in SOC domain */ + +/* uDMA data events. + * Each peripheral has a uDMA_ID. + * Each peripheral also has RX and TX event ID, which happen to be 2*uDMA_ID + * and 2*uDMA_ID+1. + */ + +#define GAP8_EVENT_UDMA_LVDS_RX 0 +#define GAP8_EVENT_UDMA_LVDS_TX 1 +#define GAP8_EVENT_UDMA_SPIM0_RX 2 +#define GAP8_EVENT_UDMA_SPIM0_TX 3 +#define GAP8_EVENT_UDMA_SPIM1_RX 4 +#define GAP8_EVENT_UDMA_SPIM1_TX 5 +#define GAP8_EVENT_UDMA_HYPERBUS_RX 6 +#define GAP8_EVENT_UDMA_HYPERBUS_TX 7 +#define GAP8_EVENT_UDMA_UART_RX 8 +#define GAP8_EVENT_UDMA_UART_TX 9 +#define GAP8_EVENT_UDMA_I2C0_RX 10 +#define GAP8_EVENT_UDMA_I2C0_TX 11 +#define GAP8_EVENT_UDMA_I2C1_RX 12 +#define GAP8_EVENT_UDMA_I2C1_TX 13 +#define GAP8_EVENT_UDMA_TCDM_RX 14 +#define GAP8_EVENT_UDMA_TCDM_TX 15 +#define GAP8_EVENT_UDMA_SAI_CH0 16 +#define GAP8_EVENT_UDMA_SAI_CH1 17 +#define GAP8_EVENT_UDMA_CPI_RX 18 + +#define GAP8_UDMA_MAX_EVENT 18 + +/* Other events of uDMA peripherals */ + +#define GAP8_EVENT_LVDS_GEN0 20 +#define GAP8_EVENT_LVDS_GEN1 21 +#define GAP8_EVENT_SPIM0_EOT 22 +#define GAP8_EVENT_SPIM1_EOT 23 +#define GAP8_EVENT_HYPERBUS_RESERVED 24 +#define GAP8_EVENT_UART_RESERVED 25 +#define GAP8_EVENT_I2C0_ERROR 26 +#define GAP8_EVENT_I2C1_ERROR 27 +#define GAP8_EVENT_I2S_RESERVED 28 +#define GAP8_EVENT_CAM_RESERVED 29 + +/* PMU events */ + +#define GAP8_EVENT_PMU_CLUSTER_POWER_ON 31 +#define GAP8_EVENT_PMU_CLUSTER_RESERVED0 32 +#define GAP8_EVENT_PMU_CLUSTER_RESERVED1 33 +#define GAP8_EVENT_PMU_CLUSTER_RESERVED2 34 +#define GAP8_EVENT_PMU_CLUSTER_CLOCK_GATING 35 +#define GAP8_EVENT_PMU_DLC_BRIDGE_PICL_OK 36 +#define GAP8_EVENT_PMU_DLC_BRIDGE_SCU_OK 37 + +/* Other SOC domain peripheral events */ + +#define GAP8_EVENT_PWM0 38 +#define GAP8_EVENT_PWM1 39 +#define GAP8_EVENT_PWM2 40 +#define GAP8_EVENT_PWM3 41 +#define GAP8_EVENT_GPIO 42 /* GPIO group interrupt */ +#define GAP8_EVENT_RTC_APB 43 +#define GAP8_EVENT_RTC 44 +#define GAP8_EVENT_RESERVED0 45 +#define GAP8_EVENT_RESERVED1 46 +#define GAP8_EVENT_RESERVED2 47 +#define GAP8_EVENT_SOC_SW_0 48 /* GAP8 SOC SW Event0 */ +#define GAP8_EVENT_SOC_SW_1 49 /* GAP8 SOC SW Event1 */ +#define GAP8_EVENT_SOC_SW_2 50 /* GAP8 SOC SW Event2 */ +#define GAP8_EVENT_SOC_SW_3 51 /* GAP8 SOC SW Event3 */ +#define GAP8_EVENT_SOC_SW_4 52 /* GAP8 SOC SW Event4 */ +#define GAP8_EVENT_SOC_SW_5 53 /* GAP8 SOC SW Event5 */ +#define GAP8_EVENT_SOC_SW_6 54 /* GAP8 SOC SW Event6 */ +#define GAP8_EVENT_SOC_SW_7 55 /* GAP8 SOC SW Event7 */ +#define GAP8_EVENT_REF32K_CLK_RISE 56 /* Reference 32K Clock event */ + +/* FC domain IRQ ID */ + +#define GAP8_IRQ_FC_SW_0 0 +#define GAP8_IRQ_FC_SW_1 1 +#define GAP8_IRQ_FC_SW_2 2 +#define GAP8_IRQ_FC_SW_3 3 +#define GAP8_IRQ_FC_SW_4 4 +#define GAP8_IRQ_FC_SW_5 5 +#define GAP8_IRQ_FC_SW_6 6 +#define GAP8_IRQ_FC_SW_7 7 +#define GAP8_IRQ_FC_TIMER_LO 10 +#define GAP8_IRQ_FC_TIMER_HI 11 +#define GAP8_IRQ_FC_UDMA 27 +#define GAP8_IRQ_FC_MPU 28 +#define GAP8_IRQ_FC_UDMA_ERR 29 +#define GAP8_IRQ_FC_HP_0 30 +#define GAP8_IRQ_FC_HP_1 31 + +#define GAP8_IRQ_RESERVED 60 + +/* Cluster domain IRQ ID */ + +/* TODO */ + +/* RISCY core exception vectors */ + +#define GAP8_IRQ_RST 32 +#define GAP8_IRQ_ILLEGAL 33 +#define GAP8_IRQ_SYSCALL 34 + +/* Total number of IRQs. + * 32 ISRs + reset-handler + illegal-instruction-handler + + * system-call-handler + */ + +#define NR_IRQS 35 + +/**************************************************************************** + * Public Types + ****************************************************************************/ + +/* SOC_EU - SOC domain event unit */ + +typedef struct +{ + volatile uint32_t EVENT; /* event register */ + volatile uint32_t FC_MASK_MSB; /* fc mask MSB register */ + volatile uint32_t FC_MASK_LSB; /* fc mask LSB register */ + volatile uint32_t CL_MASK_MSB; /* cluster mask MSB register */ + volatile uint32_t CL_MASK_LSB; /* cluster mask LSB register */ + volatile uint32_t PR_MASK_MSB; /* propagate mask MSB register */ + volatile uint32_t PR_MASK_LSB; /* propagate mask LSB register */ + volatile uint32_t ERR_MASK_MSB; /* error mask MSB register */ + volatile uint32_t ERR_MASK_LSB; /* error mask LSB register */ + volatile uint32_t TIMER_SEL_HI; /* timer high register */ + volatile uint32_t TIMER_SEL_LO; /* timer low register */ +} soc_eu_reg_t; + +#define SOC_EU ((soc_eu_reg_t *)0x1A106000U) + +/* FCEU - FC domain event unit */ + +typedef struct +{ + volatile uint32_t MASK; /* mask register */ + volatile uint32_t MASK_AND; /* mask-and(clr) register */ + volatile uint32_t MASK_OR; /* mask-or(set) register */ + volatile uint32_t MASK_IRQ; /* irq mask register */ + volatile uint32_t MASK_IRQ_AND; /* irq mask-and(clr) register */ + volatile uint32_t MASK_IRQ_OR; /* irq mask-or(set) register */ + volatile uint32_t STATUS; /* clock Status register */ + volatile uint32_t BUFFER; /* irq pending register */ + volatile uint32_t BUFFER_MASKED; /* buffer masked register */ + volatile uint32_t BUFFER_IRQ_MASKED; /* buffer irq masked register */ + volatile uint32_t BUFFER_CLEAR; /* clear irq pending */ + volatile uint32_t SW_EVENTS_MASK; /* software event mask register */ + volatile uint32_t SW_EVENTS_MASK_AND; /* software event mask and register */ + volatile uint32_t SW_EVENTS_MASK_OR; /* software event mask or register */ + volatile uint32_t EVENT_WAIT; /* event wait register */ + volatile uint32_t EVENT_WAIT_CLEAR; /* event wait clear register */ + volatile uint32_t MASK_SEC_IRQ; /* mask sec irq register */ +} fceu_reg_t; + +#define FCEU ((fceu_reg_t*)0x00204000U) + +/* Current interrupt event ID */ + +typedef struct +{ + volatile uint32_t CURRENT_EVENT; /* current event register */ +} soc_event_reg_t; + +#define SOC_EVENTS ((soc_event_reg_t*)0x00200F00UL) + +/* event trigger and mask */ + +typedef struct +{ + volatile uint32_t TRIGGER_SET[8]; /* trigger set register */ + volatile uint32_t _reserved0[8]; /* Offset: 0x20 (R/W) Empty Registers */ + volatile uint32_t TRIGGER_WAIT[8]; /* trigger wait register */ + volatile uint32_t _reserved1[8]; /* Offset: 0x60 (R/W) Empty Registers */ + volatile uint32_t TRIGGER_CLR[8]; /* trigger clear register */ +} eu_sw_events_trigger_reg_t; + +#define EU_SW_EVNT_TRIG ((eu_sw_events_trigger_reg_t*)0x00204100UL) + +#define ARCH_MAX_IRQ_NUM NR_IRQS + +int ArchEnableHwIrq(uint32_t irq_num); +int ArchDisableHwIrq(uint32_t irq_num); + + +/**************************************************************************** + * Name: up_disable_event + * + * Description: + * Disable the specific event. Note that setting 1 means to disable an + * event... + * + ****************************************************************************/ + +static inline void up_disable_event(int event) +{ + if (event >= 32) + { + SOC_EU->FC_MASK_MSB |= (1 << (event - 32)); + } + else + { + SOC_EU->FC_MASK_LSB |= (1 << event); + } +} + +/**************************************************************************** + * Name: up_enable_event + * + * Description: + * Enable the specific event. Note that setting 0 means to enable an + * event... + * + ****************************************************************************/ + +static inline void up_enable_event(int event) +{ + if (event >= 32) + { + SOC_EU->FC_MASK_MSB &= ~(1 << (event - 32)); + } + else + { + SOC_EU->FC_MASK_LSB &= ~(1 << event); + } +} + +#endif diff --git a/Ubiquitous/XiZi/arch/risc-v/gap8/gap8.h b/Ubiquitous/XiZi/arch/risc-v/gap8/gap8.h new file mode 100755 index 0000000..78bdaed --- /dev/null +++ b/Ubiquitous/XiZi/arch/risc-v/gap8/gap8.h @@ -0,0 +1,2064 @@ +/************************************************************************************ + * arch/risc-v/src/gap8/gap8.h + * Peripheral registers on GAP8 + * + * Copyright (C) 2018 Gregory Nutt. All rights reserved. + * Author: hhuysqt <1020988872@qq.com> + * Modified from gap_sdk + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +/** +* @file gap8.h +* @brief support gap8 chip fetures +* @version 1.0 +* @author AIIT XUOS Lab +* @date 2021-09-02 +*/ + +/************************************************* +File name: gap8.h +Description: support gap8 chip fetures +Others: take nuttx/arch/risc-v/src/gap8/gap8.h for references + https://github.com/apache/incubator-nuttx.git +History: +1. Date: 2021-09-02 +Author: AIIT XUOS Lab +Modification: +*************************************************/ + +#ifndef __ARCH_RISC_V_SRC_GAP8_GAP8_H +#define __ARCH_RISC_V_SRC_GAP8_GAP8_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include +#include + +/************************************************************************************ + * Public Types + ************************************************************************************/ + +#define SOC_PERI_BASE (0x1A100000UL) /* SOC Peripherals Base Address */ +#define CORE_PERI_BASE (0x00200000UL) /* RISC Core Peripheral Base Address */ +#define CONFIG_CORE_CLOCK_FREQ 200000000 +/* 2 basic timer */ + +typedef struct +{ + volatile uint32_t CFG_REG_LO; /* Configuration Register for lower 32-bits */ + volatile uint32_t CFG_REG_HI; /* Configuration Register for high 32-bits */ + volatile uint32_t VALUE_LO; /* Timer Value Register for low 32-bits */ + volatile uint32_t VALUE_HI; /* Timer Value Register for high 32-bits */ + volatile uint32_t CMP_LO; /* Timer comparator Register for low 32-bits */ + volatile uint32_t CMP_HI; /* Timer comparator Register for high 32-bits */ + volatile uint32_t START_LO; /* Timer start Register for low 32-bits */ + volatile uint32_t START_HI; /* Timer start Register for high 32-bits */ + volatile uint32_t RESET_LO; /* Timer reset Register for low 32-bits */ + volatile uint32_t RESET_HI; /* Timer reset Register for high 32-bits */ +} basic_tim_reg_t; + +#define BASIC_TIM ((basic_tim_reg_t*)(CORE_PERI_BASE + 0x0400UL)) + +#define BASIC_TIM_CASC_ENABLE (1L << 31) +#define BASIC_TIM_CASC_DISABLE (0L << 31) +#define BASIC_TIM_CLKSRC_FLL (0L << 7) +#define BASIC_TIM_CLKSRC_32K (1L << 7) +#define BASIC_TIM_PRESC_ENABLE (1L << 6) +#define BASIC_TIM_PRESC_DISABLE (0L << 6) +#define BASIC_TIM_ONE_SHOT (1L << 5) +#define BASIC_TIM_MODE_CONT (0L << 4) +#define BASIC_TIM_MODE_CYCL (1L << 4) +#define BASIC_TIM_IRQ_ENABLE (1L << 2) +#define BASIC_TIM_IRQ_DISABLE (0L << 2) +#define BASIC_TIM_RESET (1L << 1) +#define BASIC_TIM_ENABLE (1L << 0) + +typedef struct +{ + volatile uint32_t ICACHE_ENABLE; /* Cluster Icache Enable Register */ + volatile uint32_t ICACHE_FLUSH; /* Cluster Icache Flush Register */ + volatile uint32_t ICACHE_LX_SEL_FLUSH; /* Cluster Icache Level-X Flush Register or FC Flush Selected Address Register */ + volatile uint32_t ICACHE_SEL_FLUSH_STATUS; /* Cluster Icache Flush Selected Address Register or FC ICACHE status */ + volatile uint32_t ICACHE_IS_PRI; /* Cluster Icache is private Icache */ +} scbc_reg_t; + +#define CORE_SCBC_BASE (CORE_PERI_BASE + 0x1400UL) /* RISC Core System Control Block Cache Base Address */ +#define SCBC ((scbc_reg_t*)CORE_SCBC_BASE) /* Icache SCBC configuration struct */ + +/* FLL_CTRL */ + +typedef struct +{ + volatile uint32_t SOC_FLL_STATUS; /* Status register */ + volatile uint32_t SOC_CONF1; /* Configuration1 register */ + volatile uint32_t SOC_CONF2; /* Configuration2 register */ + volatile uint32_t SOC_INTEGRATOR; /* INTEGRATOR register */ + volatile uint32_t CLUSTER_FLL_STATUS; /* Status register */ + volatile uint32_t CLUSTER_CONF1; /* Configuration1 register */ + volatile uint32_t CLUSTER_CONF2; /* Configuration2 register */ + volatile uint32_t CLUSTER_INTEGRATOR; /* INTEGRATOR register */ + volatile uint32_t FLL_CONVERGE; /* Fll Converge register */ +} fll_ctrl_reg_t; + +#define FLL_CTRL ((fll_ctrl_reg_t *)SOC_PERI_BASE) + +/* FLL_STATUS - FLL_CTRL status register */ + +#define FLL_CTRL_STATUS_MULTI_FACTOR_MASK (0xFFFFU) +#define FLL_CTRL_STATUS_MULTI_FACTOR_SHIFT (0U) + +#define FLL_CTRL_STATUS_MULTI_FACTOR(x) (((uint32_t)(x) /* << FLL_CTRL_STATUS_MULTI_FACTOR_SHIFT */) & FLL_CTRL_STATUS_MULTI_FACTOR_MASK) + +#define READ_FLL_CTRL_STATUS_MULTI_FACTOR(x) (((uint32_t)(x) & FLL_CTRL_STATUS_MULTI_FACTOR_MASK) /* >> FLL_CTRL_STATUS_MULTI_FACTOR_SHIFT */) + +/* SOC_CONF1 - FLL_CTRL configuration 1 register */ + +#define FLL_CTRL_CONF1_MULTI_FACTOR_MASK (0xFFFFU) +#define FLL_CTRL_CONF1_MULTI_FACTOR_SHIFT (0U) + +#define FLL_CTRL_CONF1_MULTI_FACTOR(x) (((uint32_t)(x) /* << FLL_CTRL_CONF1_MULTI_FACTOR_SHIFT */) & FLL_CTRL_CONF1_MULTI_FACTOR_MASK) + +#define READ_FLL_CTRL_CONF1_MULTI_FACTOR(x) (((uint32_t)(x) & FLL_CTRL_CONF1_MULTI_FACTOR_MASK) /* >> FLL_CTRL_CONF1_MULTI_FACTOR_SHIFT */) + +#define FLL_CTRL_CONF1_DCO_INPUT_MASK (0x3FF0000U) +#define FLL_CTRL_CONF1_DCO_INPUT_SHIFT (16U) +#define FLL_CTRL_CONF1_DCO_INPUT(x) (((uint32_t)(x) << FLL_CTRL_CONF1_DCO_INPUT_SHIFT) & FLL_CTRL_CONF1_DCO_INPUT_MASK) +#define READ_FLL_CTRL_CONF1_DCO_INPUT(x) (((uint32_t)(x) & FLL_CTRL_CONF1_DCO_INPUT_MASK) >> FLL_CTRL_CONF1_DCO_INPUT_SHIFT) + +#define FLL_CTRL_CONF1_CLK_OUT_DIV_MASK (0x3C000000U) +#define FLL_CTRL_CONF1_CLK_OUT_DIV_SHIFT (26U) +#define FLL_CTRL_CONF1_CLK_OUT_DIV(x) (((uint32_t)(x) << FLL_CTRL_CONF1_CLK_OUT_DIV_SHIFT) & FLL_CTRL_CONF1_CLK_OUT_DIV_MASK) +#define READ_FLL_CTRL_CONF1_CLK_OUT_DIV(x) (((uint32_t)(x) & FLL_CTRL_CONF1_CLK_OUT_DIV_MASK) >> FLL_CTRL_CONF1_CLK_OUT_DIV_SHIFT) + +#define FLL_CTRL_CONF1_OUTPUT_LOCK_EN_MASK (0x40000000U) +#define FLL_CTRL_CONF1_OUTPUT_LOCK_EN_SHIFT (30U) +#define FLL_CTRL_CONF1_OUTPUT_LOCK_EN(x) (((uint32_t)(x) << FLL_CTRL_CONF1_OUTPUT_LOCK_EN_SHIFT) & FLL_CTRL_CONF1_OUTPUT_LOCK_EN_MASK) +#define READ_FLL_CTRL_CONF1_OUTPUT_LOCK_EN(x) (((uint32_t)(x) & FLL_CTRL_CONF1_OUTPUT_LOCK_EN_MASK) >> FLL_CTRL_CONF1_OUTPUT_LOCK_EN_SHIFT) + +#define FLL_CTRL_CONF1_MODE_MASK (0x80000000U) +#define FLL_CTRL_CONF1_MODE_SHIFT (31U) +#define FLL_CTRL_CONF1_MODE(x) (((uint32_t)(x) << FLL_CTRL_CONF1_MODE_SHIFT) & FLL_CTRL_CONF1_MODE_MASK) +#define READ_FLL_CTRL_CONF1_MODE(x) (((uint32_t)(x) & FLL_CTRL_CONF1_MODE_MASK) >> FLL_CTRL_CONF1_MODE_SHIFT) + +/* SOC_CONF2 - FLL_CTRL configuration 2 register */ + +#define FLL_CTRL_CONF2_LOOPGAIN_MASK (0xFU) +#define FLL_CTRL_CONF2_LOOPGAIN_SHIF T (0U) + +#define FLL_CTRL_CONF2_LOOPGAIN(x) (((uint32_t)(x) /* << FLL_CTRL_CONF2_LOOPGAIN_SHIFT */) & FLL_CTRL_CONF2_LOOPGAIN_MASK) + +#define READ_FLL_CTRL_CONF2_LOOPGAIN(x) (((uint32_t)(x) & FLL_CTRL_CONF2_LOOPGAIN_MASK)/* >> FLL_CTRL_CONF2_LOOPGAIN_SHIFT */) + +#define FLL_CTRL_CONF2_DEASSERT_CYCLES_MASK (0x3F0U) +#define FLL_CTRL_CONF2_DEASSERT_CYCLES_SHIFT (4U) +#define FLL_CTRL_CONF2_DEASSERT_CYCLES(x) (((uint32_t)(x) << FLL_CTRL_CONF2_DEASSERT_CYCLES_SHIFT) & FLL_CTRL_CONF2_DEASSERT_CYCLES_MASK) +#define READ_FLL_CTRL_CONF2_DEASSERT_CYCLES(x) (((uint32_t)(x) & FLL_CTRL_CONF2_DEASSERT_CYCLES_MASK) >> FLL_CTRL_CONF2_DEASSERT_CYCLES_SHIFT) + +#define FLL_CTRL_CONF2_ASSERT_CYCLES_MASK (0xFC00U) +#define FLL_CTRL_CONF2_ASSERT_CYCLES_SHIFT (10U) +#define FLL_CTRL_CONF2_ASSERT_CYCLES(x) (((uint32_t)(x) << FLL_CTRL_CONF2_ASSERT_CYCLES_SHIFT) & FLL_CTRL_CONF2_ASSERT_CYCLES_MASK) +#define READ_FLL_CTRL_CONF2_ASSERT_CYCLES(x) (((uint32_t)(x) & FLL_CTRL_CONF2_ASSERT_CYCLES_MASK) >> FLL_CTRL_CONF2_ASSERT_CYCLES_SHIFT) + +#define FLL_CTRL_CONF2_LOCK_TOLERANCE_MASK (0xFFF0000U) +#define FLL_CTRL_CONF2_LOCK_TOLERANCE_SHIFT (16U) +#define FLL_CTRL_CONF2_LOCK_TOLERANCE(x) (((uint32_t)(x) << FLL_CTRL_CONF2_LOCK_TOLERANCE_SHIFT) & FLL_CTRL_CONF2_LOCK_TOLERANCE_MASK) +#define READ_FLL_CTRL_CONF2_LOCK_TOLERANCE(x) (((uint32_t)(x) & FLL_CTRL_CONF2_LOCK_TOLERANCE_MASK) >> FLL_CTRL_CONF2_LOCK_TOLERANCE_SHIFT) + +#define FLL_CTRL_CONF2_CONF_CLK_SEL_MASK (0x20000000U) +#define FLL_CTRL_CONF2_CONF_CLK_SEL_SHIFT (29U) +#define FLL_CTRL_CONF2_CONF_CLK_SEL(x) (((uint32_t)(x) << FLL_CTRL_CONF2_CONF_CLK_SEL_SHIFT) & FLL_CTRL_CONF2_CONF_CLK_SEL_MASK) +#define READ_FLL_CTRL_CONF2_CONF_CLK_SEL(x) (((uint32_t)(x) & FLL_CTRL_CONF2_CONF_CLK_SEL_MASK) >> FLL_CTRL_CONF2_CONF_CLK_SEL_SHIFT) + +#define FLL_CTRL_CONF2_OPEN_LOOP_MASK (0x40000000U) +#define FLL_CTRL_CONF2_OPEN_LOOP_SHIFT (30U) +#define FLL_CTRL_CONF2_OPEN_LOOP(x) (((uint32_t)(x) << FLL_CTRL_CONF2_OPEN_LOOP_SHIFT) & FLL_CTRL_CONF2_OPEN_LOOP_MASK) +#define READ_FLL_CTRL_CONF2_OPEN_LOOP(x) (((uint32_t)(x) & FLL_CTRL_CONF2_OPEN_LOOP_MASK) >> FLL_CTRL_CONF2_OPEN_LOOP_SHIFT) + +#define FLL_CTRL_CONF2_DITHERING_MASK (0x80000000U) +#define FLL_CTRL_CONF2_DITHERING_SHIFT (31U) +#define FLL_CTRL_CONF2_DITHERING(x) (((uint32_t)(x) << FLL_CTRL_CONF2_DITHERING_SHIFT) & FLL_CTRL_CONF2_DITHERING_MASK) +#define READ_FLL_CTRL_CONF2_DITHERING(x) (((uint32_t)(x) & FLL_CTRL_CONF2_DITHERING_MASK) >> FLL_CTRL_CONF2_DITHERING_SHIFT) + +/* SOC_INTEGRATOR - FLL_CTRL configuration 2 register */ + +#define FLL_CTRL_INTEGRATOR_FRACT_PART_MASK (0xFFC0U) +#define FLL_CTRL_INTEGRATOR_FRACT_PART_SHIFT (6U) +#define FLL_CTRL_INTEGRATOR_FRACT_PART(x) (((uint32_t)(x) << FLL_CTRL_INTEGRATOR_FRACT_PART_SHIFT) & FLL_CTRL_INTEGRATOR_FRACT_PART_MASK) +#define READ_FLL_CTRL_INTEGRATOR_FRACT_PART(x) (((uint32_t)(x) & FLL_CTRL_INTEGRATOR_FRACT_PART_MASK) >> FLL_CTRL_INTEGRATOR_FRACT_PART_SHIFT) + +#define FLL_CTRL_INTEGRATOR_INT_PART_MASK (0x3FF0000U) +#define FLL_CTRL_INTEGRATOR_INT_PART_SHIFT (16U) +#define FLL_CTRL_INTEGRATOR_INT_PART(x) (((uint32_t)(x) << FLL_CTRL_INTEGRATOR_INT_PART_SHIFT) & FLL_CTRL_INTEGRATOR_INT_PART_MASK) +#define READ_FLL_CTRL_INTEGRATOR_INT_PART(x) (((uint32_t)(x) & FLL_CTRL_INTEGRATOR_INT_PART_MASK) >> FLL_CTRL_INTEGRATOR_INT_PART_SHIFT) + +/* FLL_CONVERGE - FLL_CTRL configuration 2 register */ + +#define FLL_CTRL_SOC_FLL_CONV_MASK (0x1U) +#define FLL_CTRL_SOC_FLL_CONV_SHIFT (0U) + +#define FLL_CTRL_SOC_FLL_CONV(x) (((uint32_t)(x) /* << FLL_CTRL_SOC_FLL_CONV_SHIFT */) & FLL_CTRL_SOC_FLL_CONV_MASK) + +#define READ_FLL_CTRL_SOC_FLL_CONV(x) (((uint32_t)(x) & FLL_CTRL_SOC_FLL_CONV_MASK) /* >> FLL_CTRL_SOC_FLL_CONV_SHIFT */) + +#define FLL_CTRL_CLUSTER_FLL_CONV_MASK (0x2U) +#define FLL_CTRL_CLUSTER_FLL_CONV_SHIFT (1U) +#define FLL_CTRL_CLUSTER_FLL_CONV(x) (((uint32_t)(x) << FLL_CTRL_CLUSTER_FLL_CONV_SHIFT) & FLL_CTRL_CLUSTER_FLL_CONV_MASK) +#define READ_FLL_CTRL_CLUSTER_FLL_CONV(x) (((uint32_t)(x) & FLL_CTRL_CLUSTER_FLL_CONV_MASK) >> FLL_CTRL_CLUSTER_FLL_CONV_SHIFT) + +/* The number of FLL */ + +#define FLL_NUM 2 + +/* The FLL reference frequency */ + +#define FLL_REF_CLK 32768 + +/* GPIO - Register Layout Typedef */ + +typedef struct +{ + volatile uint32_t DIR; /* gpio direction register */ + volatile uint32_t IN; /* gpio in register */ + volatile uint32_t OUT; /* gpio out register */ + volatile uint32_t INTEN; /* gpio inten register */ + volatile uint32_t INTCFG[2]; /* gpio int configuration registers */ + volatile uint32_t INTSTATUS; /* gpio int status register */ + volatile uint32_t EN; /* gpio enable register */ + volatile uint32_t PADCFG[8]; /* pad configuration registers */ +} gpio_reg_t; + +#define GPIO_INTCFG_TYPE_MASK (0x3U) +#define GPIO_INTCFG_TYPE_SHIFT (0U) +#define GPIO_INTCFG_TYPE(x) (((uint32_t)(x) << GPIO_INTCFG_TYPE_SHIFT) & GPIO_INTCFG_TYPE_MASK) + +#define GPIO_INTCFG_TYPE_BITS_WIDTH_MASK (0x3U) + +/* Peripheral GPIOA base pointer */ + +#define GPIOA ((gpio_reg_t *)(SOC_PERI_BASE + 0x1000u)) + +/* UDMA - General Register Layout Typedef */ + +typedef struct +{ + volatile uint32_t RX_SADDR; /* RX UDMA buffer transfer address register */ + volatile uint32_t RX_SIZE; /* RX UDMA buffer transfer size register */ + volatile uint32_t RX_CFG; /* RX UDMA transfer configuration register */ + volatile uint32_t RX_INITCFG; /* Reserved */ + volatile uint32_t TX_SADDR; /* TX UDMA buffer transfer address register */ + volatile uint32_t TX_SIZE; /* TX UDMA buffer transfer size register */ + volatile uint32_t TX_CFG; /* TX UDMA transfer configuration register */ + volatile uint32_t TX_INITCFG; /* Reserved */ +} udma_reg_t; + +/* RX_SADDR - RX TX UDMA buffer transfer address register */ + +#define UDMA_SADDR_ADDR_MASK (0xFFFFU) +#define UDMA_SADDR_ADDR_SHIFT (0U) +#define UDMA_SADDR_ADDR(x) (((uint32_t)(x) /* << UDMA_SADDR_ADDR_SHIFT */) & UDMA_SADDR_ADDR_MASK) + +/* RX_SIZE - RX TX UDMA buffer transfer size register */ + +#define UDMA_SIZE_SIZE_MASK (0x1FFFFU) +#define UDMA_SIZE_SIZE_SHIFT (0U) +#define UDMA_SIZE_SIZE(x) (((uint32_t)(x) << UDMA_SIZE_SIZE_SHIFT) & UDMA_SIZE_SIZE_MASK) + +/* RX_CFG - RX TX UDMA transfer configuration register */ + +#define UDMA_CFG_CONTINOUS_MASK (0x1U) +#define UDMA_CFG_CONTINOUS_SHIFT (0U) +#define UDMA_CFG_CONTINOUS(x) (((uint32_t)(x) /* << UDMA_CFG_CONTINOUS_SHIFT */) & UDMA_CFG_CONTINOUS_MASK) +#define UDMA_CFG_DATA_SIZE_MASK (0x6U) +#define UDMA_CFG_DATA_SIZE_SHIFT (1U) +#define UDMA_CFG_DATA_SIZE(x) (((uint32_t)(x) << UDMA_CFG_DATA_SIZE_SHIFT) & UDMA_CFG_DATA_SIZE_MASK) +#define UDMA_CFG_EN_MASK (0x10U) +#define UDMA_CFG_EN_SHIFT (4U) +#define UDMA_CFG_EN(x) (((uint32_t)(x) << UDMA_CFG_EN_SHIFT) & UDMA_CFG_EN_MASK) +#define UDMA_CFG_CLR_MASK (0x20U) +#define UDMA_CFG_CLR_SHIFT (5U) +#define UDMA_CFG_CLR(x) (((uint32_t)(x) << UDMA_CFG_CLR_SHIFT) & UDMA_CFG_CLR_MASK) + +/* Peripheral UDMA base address 0x1A102000 */ + +#define UDMA_BASE (0x1A102000) + +/* UDMA Global configuration - Register Layout Typedef */ + +typedef struct +{ + volatile uint32_t CG; /* clock gating register */ + volatile uint32_t EVTIN; /* input event register */ +} udma_gc_reg_t; + +#define UDMA_GC_BASE (UDMA_BASE + 0x780u) +#define UDMA_GC ((udma_gc_reg_t *)UDMA_GC_BASE) + +/* UDMA_GC - UDMA event in register, User chooses which events can come to + * UDMA as reference events, support up to 4 choices + */ + +#define UDMA_GC_EVTIN_CHOICE0_MASK (0xFFU) +#define UDMA_GC_EVTIN_CHOICE0_SHIFT (0U) +#define UDMA_GC_EVTIN_CHOICE0(x) (((uint32_t)(x) << UDMA_GC_EVTIN_CHOICE0_SHIFT) & UDMA_GC_EVTIN_CHOICE0_MASK) + +#define UDMA_GC_EVTIN_CHOICE1_MASK (0xFF00U) +#define UDMA_GC_EVTIN_CHOICE1_SHIFT (8U) +#define UDMA_GC_EVTIN_CHOICE1(x) (((uint32_t)(x) << UDMA_GC_EVTIN_CHOICE1_SHIFT) & UDMA_GC_EVTIN_CHOICE1_MASK) + +#define UDMA_GC_EVTIN_CHOICE2_MASK (0xFF0000U) +#define UDMA_GC_EVTIN_CHOICE2_SHIFT (16U) +#define UDMA_GC_EVTIN_CHOICE2(x) (((uint32_t)(x) << UDMA_GC_EVTIN_CHOICE2_SHIFT) & UDMA_GC_EVTIN_CHOICE2_MASK) + +#define UDMA_GC_EVTIN_CHOICE3_MASK (0xFF000000) +#define UDMA_GC_EVTIN_CHOICE3_SHIFT (24U) +#define UDMA_GC_EVTIN_CHOICE3(x) (((uint32_t)(x) << UDMA_GC_EVTIN_CHOICE3_SHIFT) & UDMA_GC_EVTIN_CHOICE3_MASK) + +/* LVDS - Register Layout Typedef */ + +typedef struct +{ + udma_reg_t UDMA_LVDS; /* UDMA general register */ + volatile uint32_t RF_CFG; /* configuration register */ + volatile uint32_t RF_GPIO; /* Reserved */ + volatile uint32_t RF_STATUS; /* Status register */ +} lvds_reg_t; + +#define LVDS_BASE (UDMA_BASE + 0 * 128U) +#define LVDS ((lvds_reg_t *)LVDS_BASE) + +/* RF_CFG - LVDS configuration register */ + +#define LVDS_RF_CFG_TX_ENB_MASK (0x1U) +#define LVDS_RF_CFG_TX_ENB_SHIFT (0U) +#define LVDS_RF_CFG_TX_ENB(x) (((uint32_t)(x) << /* LVDS_RF_CFG_TX_ENB_SHIFT */) & LVDS_RF_CFG_TX_ENB_MASK) + +#define LVDS_RF_CFG_TX_OEB_MASK (0x2U) +#define LVDS_RF_CFG_TX_OEB_SHIFT (1U) +#define LVDS_RF_CFG_TX_OEB(x) (((uint32_t)(x) << LVDS_RF_CFG_TX_OEB_SHIFT) & LVDS_RF_CFG_TX_OEB_MASK) + +#define LVDS_RF_CFG_TX_MODE_MASK (0x4U) +#define LVDS_RF_CFG_TX_MODE_SHIFT (2U) +#define LVDS_RF_CFG_TX_MODE(x) (((uint32_t)(x) << LVDS_RF_CFG_TX_MODE_SHIFT) & LVDS_RF_CFG_TX_MODE_MASK) + +#define LVDS_RF_CFG_TX_VSEL_MASK (0x8U) +#define LVDS_RF_CFG_TX_VSEL_SHIFT (3U) +#define LVDS_RF_CFG_TX_VSEL(x) (((uint32_t)(x) << LVDS_RF_CFG_TX_VSEL_SHIFT) & LVDS_RF_CFG_TX_VSEL_MASK) + +#define LVDS_RF_CFG_RX_ENB_MASK (0x10U) +#define LVDS_RF_CFG_RX_ENB_SHIFT (4U) +#define LVDS_RF_CFG_RX_ENB(x) (((uint32_t)(x) << LVDS_RF_CFG_RX_ENB_SHIFT) & LVDS_RF_CFG_RX_ENB_MASK) + +#define LVDS_RF_CFG_SD_RX_EN_MASK (0x20U) +#define LVDS_RF_CFG_SD_RX_EN_SHIFT (5U) +#define LVDS_RF_CFG_SD_RX_EN(x) (((uint32_t)(x) << LVDS_RF_CFG_SD_RX_EN_SHIFT) & LVDS_RF_CFG_SD_RX_EN_MASK) + +#define LVDS_RF_CFG_SD_TX_EN_MASK (0x40U) +#define LVDS_RF_CFG_SD_TX_EN_SHIFT (6U) +#define LVDS_RF_CFG_SD_TX_EN(x) (((uint32_t)(x) << LVDS_RF_CFG_SD_TX_EN_SHIFT) & LVDS_RF_CFG_SD_TX_EN_MASK) + +#define LVDS_RF_CFG_DDR_RX_EN_MASK (0x80U) +#define LVDS_RF_CFG_DDR_RX_EN_SHIFT (7U) +#define LVDS_RF_CFG_DDR_RX_EN(x) (((uint32_t)(x) << LVDS_RF_CFG_DDR_RX_EN_SHIFT) & LVDS_RF_CFG_DDR_RX_EN_MASK) + +#define LVDS_RF_CFG_DDR_TX_EN_MASK (0x100U) +#define LVDS_RF_CFG_DDR_TX_EN_SHIFT (8U) +#define LVDS_RF_CFG_DDR_TX_EN(x) (((uint32_t)(x) << LVDS_RF_CFG_DDR_TX_EN_SHIFT) & LVDS_RF_CFG_DDR_TX_EN_MASK) + +#define LVDS_RF_CFG_CLKSEL_MASK (0x200U) +#define LVDS_RF_CFG_CLKSEL_SHIFT (9U) +#define LVDS_RF_CFG_CLKSEL(x) (((uint32_t)(x) << LVDS_RF_CFG_CLKSEL_SHIFT) & LVDS_RF_CFG_CLKSEL_MASK) + +#define LVDS_RF_CFG_MODE_MASK (0x400U) +#define LVDS_RF_CFG_MODE_SHIFT (10U) +#define LVDS_RF_CFG_MODE(x) (((uint32_t)(x) << LVDS_RF_CFG_MODE_SHIFT) & LVDS_RF_CFG_MODE_MASK) + +#define LVDS_RF_CFG_MODE_VAL_MASK (0x800U) +#define LVDS_RF_CFG_MODE_VAL_SHIFT (11U) +#define LVDS_RF_CFG_MODE_VAL(x) (((uint32_t)(x) << LVDS_RF_CFG_MODE_VAL_SHIFT) & LVDS_RF_CFG_MODE_VAL_MASK) + +#define LVDS_RF_CFG_MODE_RX_MASK (0x1000U) +#define LVDS_RF_CFG_MODE_RX_SHIFT (12U) +#define LVDS_RF_CFG_MODE_RX(x) (((uint32_t)(x) << LVDS_RF_CFG_MODE_RX_SHIFT) & LVDS_RF_CFG_MODE_RX_MASK) + +/* RF_STATUS - LVDS Status register */ + +#define LVDS_RF_STATUS_SYNC_FLAG_MASK (0x1U) +#define LVDS_RF_STATUS_SYNC_FLAG_SHIFT (0U) +#define LVDS_RF_STATUS_SYNC_FLAG(x) (((uint32_t)(x) /* << LVDS_RF_STATUS_SYNC_FLAG_SHIFT */) & LVDS_RF_STATUS_SYNC_FLAG_MASK) + +/* ORCA - Register Layout Typedef */ + +typedef struct +{ + udma_reg_t UDMA_ORCA; /* ORCA UDMA general register */ + volatile uint32_t RF_CFG; /* ORCA configuration register */ + volatile uint32_t RF_GPIO; /* Reserved */ + volatile uint32_t RF_STATUS; /* ORCA Status register */ + volatile uint32_t PAD; /* ORCA reserved */ + volatile uint32_t CLKDIV_EN; /* ORCA uDMA clock divider enable register */ + volatile uint32_t CLKDIV_CFG; /* ORCA uDMA clock divider configuration register */ + volatile uint32_t CLKDIV_UPD; /* ORCA uDMA clock divider data register */ + volatile uint32_t ORCA_CFG; /* ORCA configuration register */ + volatile uint32_t CNT_EVENT; /* ORCA Status register */ +} orca_reg_t; + +#define ORCA_BASE (UDMA_BASE + 0 * 128U) +#define ORCA ((orca_reg_t *)ORCA_BASE) + +/* RF_CFG - ORCA configuration register */ + +#define ORCA_RF_CFG_TX_ENB_MASK (0x1U) +#define ORCA_RF_CFG_TX_ENB_SHIFT (0U) +#define ORCA_RF_CFG_TX_ENB(x) (((uint32_t)(x) /* << ORCA_RF_CFG_TX_ENB_SHIFT */) & ORCA_RF_CFG_TX_ENB_MASK) + +#define ORCA_RF_CFG_TX_OEB_MASK (0x2U) +#define ORCA_RF_CFG_TX_OEB_SHIFT (1U) +#define ORCA_RF_CFG_TX_OEB(x) (((uint32_t)(x) << ORCA_RF_CFG_TX_OEB_SHIFT) & ORCA_RF_CFG_TX_OEB_MASK) + +#define ORCA_RF_CFG_TX_MODE_MASK (0x4U) +#define ORCA_RF_CFG_TX_MODE_SHIFT (2U) +#define ORCA_RF_CFG_TX_MODE(x) (((uint32_t)(x) << ORCA_RF_CFG_TX_MODE_SHIFT) & ORCA_RF_CFG_TX_MODE_MASK) + +#define ORCA_RF_CFG_TX_VSEL_MASK (0x8U) +#define ORCA_RF_CFG_TX_VSEL_SHIFT (3U) +#define ORCA_RF_CFG_TX_VSEL(x) (((uint32_t)(x) << ORCA_RF_CFG_TX_VSEL_SHIFT) & ORCA_RF_CFG_TX_VSEL_MASK) + +#define ORCA_RF_CFG_RX_ENB_MASK (0x10U) +#define ORCA_RF_CFG_RX_ENB_SHIFT (4U) +#define ORCA_RF_CFG_RX_ENB(x) (((uint32_t)(x) << ORCA_RF_CFG_RX_ENB_SHIFT) & ORCA_RF_CFG_RX_ENB_MASK) + +#define ORCA_RF_CFG_SD_RX_EN_MASK (0x20U) +#define ORCA_RF_CFG_SD_RX_EN_SHIFT (5U) +#define ORCA_RF_CFG_SD_RX_EN(x) (((uint32_t)(x) << ORCA_RF_CFG_SD_RX_EN_SHIFT) & ORCA_RF_CFG_SD_RX_EN_MASK) + +#define ORCA_RF_CFG_SD_TX_EN_MASK (0x40U) +#define ORCA_RF_CFG_SD_TX_EN_SHIFT (6U) +#define ORCA_RF_CFG_SD_TX_EN(x) (((uint32_t)(x) << ORCA_RF_CFG_SD_TX_EN_SHIFT) & ORCA_RF_CFG_SD_TX_EN_MASK) + +#define ORCA_RF_CFG_DDR_RX_EN_MASK (0x80U) +#define ORCA_RF_CFG_DDR_RX_EN_SHIFT (7U) +#define ORCA_RF_CFG_DDR_RX_EN(x) (((uint32_t)(x) << ORCA_RF_CFG_DDR_RX_EN_SHIFT) & ORCA_RF_CFG_DDR_RX_EN_MASK) + +#define ORCA_RF_CFG_DDR_TX_EN_MASK (0x100U) +#define ORCA_RF_CFG_DDR_TX_EN_SHIFT (8U) +#define ORCA_RF_CFG_DDR_TX_EN(x) (((uint32_t)(x) << ORCA_RF_CFG_DDR_TX_EN_SHIFT) & ORCA_RF_CFG_DDR_TX_EN_MASK) + +#define ORCA_RF_CFG_CLKSEL_MASK (0x200U) +#define ORCA_RF_CFG_CLKSEL_SHIFT (9U) +#define ORCA_RF_CFG_CLKSEL(x) (((uint32_t)(x) << ORCA_RF_CFG_CLKSEL_SHIFT) & ORCA_RF_CFG_CLKSEL_MASK) + +#define ORCA_RF_CFG_MODE_MASK (0x400U) +#define ORCA_RF_CFG_MODE_SHIFT (10U) +#define ORCA_RF_CFG_MODE(x) (((uint32_t)(x) << ORCA_RF_CFG_MODE_SHIFT) & ORCA_RF_CFG_MODE_MASK) + +#define ORCA_RF_CFG_MODE_VAL_MASK (0x800U) +#define ORCA_RF_CFG_MODE_VAL_SHIFT (11U) +#define ORCA_RF_CFG_MODE_VAL(x) (((uint32_t)(x) << ORCA_RF_CFG_MODE_VAL_SHIFT) & ORCA_RF_CFG_MODE_VAL_MASK) + +#define ORCA_RF_CFG_MODE_RX_MASK (0x1000U) +#define ORCA_RF_CFG_MODE_RX_SHIFT (12U) +#define ORCA_RF_CFG_MODE_RX(x) (((uint32_t)(x) << ORCA_RF_CFG_MODE_RX_SHIFT) & ORCA_RF_CFG_MODE_RX_MASK) + +/* RF_STATUS - ORCA Status register */ + +#define ORCA_RF_STATUS_SYNC_FLAG_MASK (0x1U) +#define ORCA_RF_STATUS_SYNC_FLAG_SHIFT (0U) +#define ORCA_RF_STATUS_SYNC_FLAG(x) (((uint32_t)(x) /* << ORCA_RF_STATUS_SYNC_FLAG_SHIFT */) & ORCA_RF_STATUS_SYNC_FLAG_MASK) + +/* CLKDIV_EN - ORCA uDMA clock divider enable register */ + +#define ORCA_CLKDIV_EN_MASK (0x1U) +#define ORCA_CLKDIV_EN_SHIFT (0U) +#define ORCA_CLKDIV_EN(x) (((uint32_t)(x) /* << ORCA_CLKDIV_EN_SHIFT */) & ORCA_CLKDIV_EN_MASK) + +/* CLKDIV_CFG - ORCA uDMA clock divider configuration register */ + +#define ORCA_CLKDIV_CFG_MASK (0xFFU) +#define ORCA_CLKDIV_CFG_SHIFT (0U) +#define ORCA_CLKDIV_CFG(x) (((uint32_t)(x) /* << ORCA_CLKDIV_CFG_SHIFT */) & ORCA_CLKDIV_CFG_MASK) + +/* CLKDIV_UDP - ORCA uDMA clock divider enable register */ + +#define ORCA_CLKDIV_UDP_MASK (0x1U) +#define ORCA_CLKDIV_UDP_SHIFT (0U) +#define ORCA_CLKDIV_UDP(x) (((uint32_t)(x) /* << ORCA_CLKDIV_UDP_SHIFT */) & ORCA_CLKDIV_UDP_MASK) + +/* ORCA_CFG - ORCA configuration register */ + +#define ORCA_CFG_SIZE_MASK (0xFU) +#define ORCA_CFG_SIZE_SHIFT (0U) +#define ORCA_CFG_SIZE(x) (((uint32_t)(x) /* << ORCA_CFG_SIZE_SHIFT */) & ORCA_CFG_SIZE_MASK) + +#define ORCA_CFG_DELAY_MASK (0xF0U) +#define ORCA_CFG_DELAY_SHIFT (4U) +#define ORCA_CFG_DELAY(x) (((uint32_t)(x) << ORCA_CFG_DELAY_SHIFT) & ORCA_CFG_DELAY_MASK) + +#define ORCA_CFG_EN_MASK (0x100U) +#define ORCA_CFG_EN_SHIFT (8U) +#define ORCA_CFG_EN(x) (((uint32_t)(x) << ORCA_CFG_EN_SHIFT) & ORCA_CFG_EN_MASK) + +/* SPIM - Register Layout Typedef */ + +typedef struct +{ + udma_reg_t UDMA_SPIM; /* SPIM UDMA general register */ +} spim_reg_t; + +#define SPIM0_BASE (UDMA_BASE + 1 * 128U) +#define SPIM0 ((spim_reg_t *)SPIM0_BASE) +#define SPIM1_BASE (UDMA_BASE + 2 * 128U) +#define SPIM1 ((spim_reg_t *)SPIM1_BASE) + +/* uDMA - SPIM uDMA control CMD */ + +#define SPIM_CMD_CFG_ID 0 +#define SPIM_CMD_SOT_ID 1 +#define SPIM_CMD_SEND_CMD_ID 2 +#define SPIM_CMD_SEND_ADDR_ID 3 +#define SPIM_CMD_DUMMY_ID 4 +#define SPIM_CMD_WAIT_ID 5 +#define SPIM_CMD_TX_DATA_ID 6 +#define SPIM_CMD_RX_DATA_ID 7 +#define SPIM_CMD_RPT_ID 8 +#define SPIM_CMD_EOT_ID 9 +#define SPIM_CMD_RPT_END_ID 10 +#define SPIM_CMD_RX_CHECK_ID 11 +#define SPIM_CMD_FUL_ID 12 + +#define SPIM_CMD_MASK (0xF0000000U) +#define SPIM_CMD_SHIFT (28U) +#define SPIM_CMD(x) (((uint32_t)(x) << SPIM_CMD_SHIFT) & SPIM_CMD_MASK) + +/* SPIM_Register_Masks SPIM Register Masks */ + +/* CMD_CFG - SPIM configuration register */ + +#define SPIM_CMD_CFG_CLKDIV_MASK (0xFFU) +#define SPIM_CMD_CFG_CLKDIV_SHIFT (0U) +#define SPIM_CMD_CFG_CLKDIV(x) (((uint32_t)(x) /* << SPIM_CMD_CFG_CLKDIV_SHIFT */) & SPIM_CMD_CFG_CLKDIV_MASK) +#define SPIM_CMD_CFG_CPHA_MASK (0x100U) +#define SPIM_CMD_CFG_CPHA_SHIFT (8U) +#define SPIM_CMD_CFG_CPHA(x) (((uint32_t)(x) << SPIM_CMD_CFG_CPHA_SHIFT) & SPIM_CMD_CFG_CPHA_MASK) +#define SPIM_CMD_CFG_CPOL_MASK (0x200U) +#define SPIM_CMD_CFG_CPOL_SHIFT (9U) +#define SPIM_CMD_CFG_CPOL(x) (((uint32_t)(x) << SPIM_CMD_CFG_CPOL_SHIFT) & SPIM_CMD_CFG_CPOL_MASK) + +/* CMD_SOT - SPIM chip select (CS) */ + +#define SPIM_CMD_SOT_CS_MASK (0x3U) +#define SPIM_CMD_SOT_CS_SHIFT (0U) +#define SPIM_CMD_SOT_CS(x) (((uint32_t)(x) << SPIM_CMD_SOT_CS_SHIFT) & SPIM_CMD_SOT_CS_MASK) + +/* CMD_SEND_CMD - SPIM Transmit a command */ + +#define SPIM_CMD_SEND_VALUEL_MASK (0xFFU) +#define SPIM_CMD_SEND_VALUEL_SHIFT (0U) +#define SPIM_CMD_SEND_VALUEL(x) (((uint32_t)(x) /* << SPIM_CMD_SEND_VALUEL_SHIFT */) & SPIM_CMD_SEND_VALUEL_MASK) +#define SPIM_CMD_SEND_VALUEH_MASK (0xFF00U) +#define SPIM_CMD_SEND_VALUEH_SHIFT (8U) +#define SPIM_CMD_SEND_VALUEH(x) (((uint32_t)(x) << SPIM_CMD_SEND_VALUEH_SHIFT) & SPIM_CMD_SEND_VALUEH_MASK) +#define SPIM_CMD_SEND_CMD_SIZE_MASK (0x1F0000U) +#define SPIM_CMD_SEND_CMD_SIZE_SHIFT (16U) +#define SPIM_CMD_SEND_CMD_SIZE(x) (((uint32_t)(x) << SPIM_CMD_SEND_CMD_SIZE_SHIFT) & SPIM_CMD_SEND_CMD_SIZE_MASK) +#define SPIM_CMD_SEND_QPI_MASK (0x8000000U) +#define SPIM_CMD_SEND_QPI_SHIFT (27U) +#define SPIM_CMD_SEND_QPI(x) (((uint32_t)(x) << SPIM_CMD_SEND_QPI_SHIFT) & SPIM_CMD_SEND_QPI_MASK) + +/* CMD_SEND_ADDR - SPIM Transmit a address */ + +#define SPIM_CMD_SEND_ADDR_VALUE_MASK (0xFFFFU) +#define SPIM_CMD_SEND_ADDR_VALUE_SHIFT (0U) +#define SPIM_CMD_SEND_ADDR_VALUE(x) (((uint32_t)(x) /* << SPIM_CMD_SEND_ADDR_VALUE_SHIFT */) & SPIM_CMD_SEND_ADDR_VALUE_MASK) +#define SPIM_CMD_SEND_ADDR_CMD_SIZE_MASK (0x1F0000U) +#define SPIM_CMD_SEND_ADDR_CMD_SIZE_SHIFT (16U) +#define SPIM_CMD_SEND_ADDR_CMD_SIZE(x) (((uint32_t)(x) << SPIM_CMD_SEND_ADDR_CMD_SIZE_SHIFT) & SPIM_CMD_SEND_ADDR_CMD_SIZE_MASK) +#define SPIM_CMD_SEND_ADDR_QPI_MASK (0x8000000U) +#define SPIM_CMD_SEND_ADDR_QPI_SHIFT (27U) +#define SPIM_CMD_SEND_ADDR_QPI(x) (((uint32_t)(x) << SPIM_CMD_SEND_ADDR_QPI_SHIFT) & SPIM_CMD_SEND_ADDR_QPI_MASK) + +/* CMD_DUMMY - SPIM number of dummy cycle */ + +#define SPIM_CMD_DUMMY_CYCLE_MASK (0x1F0000U) +#define SPIM_CMD_DUMMY_CYCLE_SHIFT (16U) +#define SPIM_CMD_DUMMY_CYCLE(x) (((uint32_t)(x) << SPIM_CMD_DUMMY_CYCLE_SHIFT) & SPIM_CMD_DUMMY_CYCLE_MASK) + +/* CMD_WAIT - SPIM wait in which event - 2 bits */ + +#define SPIM_CMD_WAIT_EVENT_ID_MASK (0x3U) +#define SPIM_CMD_WAIT_EVENT_ID_SHIFT (0U) +#define SPIM_CMD_WAIT_EVENT_ID(x) (((uint32_t)(x) /* << SPIM_CMD_WAIT_EVENT_ID_SHIFT */) & SPIM_CMD_WAIT_EVENT_ID_MASK) + +/* CMD_TX_DATA - SPIM send data */ + +#define SPIM_CMD_TX_DATA_SIZE_MASK (0xFFFFU) +#define SPIM_CMD_TX_DATA_SIZE_SHIFT (0U) +#define SPIM_CMD_TX_DATA_SIZE(x) (((uint32_t)(x) /* << SPIM_CMD_TX_DATA_SIZE_SHIFT */) & SPIM_CMD_TX_DATA_SIZE_MASK) +#define SPIM_CMD_TX_DATA_BYTE_ALIGN_MASK (0x4000000U) +#define SPIM_CMD_TX_DATA_BYTE_ALIGN_SHIFT (26U) +#define SPIM_CMD_TX_DATA_BYTE_ALIGN(x) (((uint32_t)(x) << SPIM_CMD_TX_DATA_BYTE_ALIGN_SHIFT) & SPIM_CMD_TX_DATA_BYTE_ALIGN_MASK) +#define SPIM_CMD_TX_DATA_QPI_MASK (0x8000000U) +#define SPIM_CMD_TX_DATA_QPI_SHIFT (27U) +#define SPIM_CMD_TX_DATA_QPI(x) (((uint32_t)(x) << SPIM_CMD_TX_DATA_QPI_SHIFT) & SPIM_CMD_TX_DATA_QPI_MASK) + +/* CMD_RX_DATA - SPIM receive data */ + +#define SPIM_CMD_RX_DATA_SIZE_MASK (0xFFFFU) +#define SPIM_CMD_RX_DATA_SIZE_SHIFT (0U) +#define SPIM_CMD_RX_DATA_SIZE(x) (((uint32_t)(x) /* << SPIM_CMD_RX_DATA_SIZE_SHIFT */) & SPIM_CMD_RX_DATA_SIZE_MASK) +#define SPIM_CMD_RX_DATA_BYTE_ALIGN_MASK (0x4000000U) +#define SPIM_CMD_RX_DATA_BYTE_ALIGN_SHIFT (26U) +#define SPIM_CMD_RX_DATA_BYTE_ALIGN(x) (((uint32_t)(x) << SPIM_CMD_RX_DATA_BYTE_ALIGN_SHIFT) & SPIM_CMD_RX_DATA_BYTE_ALIGN_MASK) +#define SPIM_CMD_RX_DATA_QPI_MASK (0x8000000U) +#define SPIM_CMD_RX_DATA_QPI_SHIFT (27U) +#define SPIM_CMD_RX_DATA_QPI(x) (((uint32_t)(x) << SPIM_CMD_RX_DATA_QPI_SHIFT) & SPIM_CMD_RX_DATA_QPI_MASK) + +/* CMD_RPT - SPIM repeat the next transfer N times */ + +#define SPIM_CMD_RPT_CNT_MASK (0xFFFFU) +#define SPIM_CMD_RPT_CNT_SHIFT (0U) +#define SPIM_CMD_RPT_CNT(x) (((uint32_t)(x) /* << SPIM_CMD_RPT_CNT_SHIFT */) & SPIM_CMD_RPT_CNT_MASK) + +/* CMD_EOT - SPIM clears the chip select (CS), and send a end event or not */ + +#define SPIM_CMD_EOT_EVENT_GEN_MASK (0x1U) +#define SPIM_CMD_EOT_EVENT_GEN_SHIFT (0U) +#define SPIM_CMD_EOT_EVENT_GEN(x) (((uint32_t)(x) /* << SPIM_CMD_EOT_EVENT_GEN_SHIFT */) & SPIM_CMD_EOT_EVENT_GEN_MASK) + +/* CMD_RPT_END - SPIM End of the repeat loop */ + +#define SPIM_CMD_RPT_END_SPI_CMD_MASK (0xFU) +#define SPIM_CMD_RPT_END_SPI_CMD_SHIFT (0U) +#define SPIM_CMD_RPT_END_SPI_CMD(x) (((uint32_t)(x) /* << SPIM_CMD_RPT_END_SPI_CMD_SHIFT */) & SPIM_CMD_RPT_END_SPI_CMD_MASK) + +/* CMD_RX_CHECK - SPIM check up to 16 bits of data against an expected value */ + +#define SPIM_CMD_RX_CHECK_COMP_DATA_MASK (0xFFFFU) +#define SPIM_CMD_RX_CHECK_COMP_DATA_SHIFT (0U) +#define SPIM_CMD_RX_CHECK_COMP_DATA(x) (((uint32_t)(x) /* << SPIM_CMD_RX_CHECK_COMP_DATA_SHIFT */) & SPIM_CMD_RX_CHECK_COMP_DATA_MASK) + +/* The number of bits to check, maximum is 16bits */ + +#define SPIM_CMD_RX_CHECK_STATUS_SIZE_MASK (0xFF0000U) +#define SPIM_CMD_RX_CHECK_STATUS_SIZE_SHIFT (16U) +#define SPIM_CMD_RX_CHECK_STATUS_SIZE(x) (((uint32_t)(x) << SPIM_CMD_RX_CHECK_STATUS_SIZE_SHIFT) & SPIM_CMD_RX_CHECK_STATUS_SIZE_MASK) + +/* The type of checking, 0 - Equal; 1 - check the bits of one; + * 2 - check the bits of zero + */ + +#define SPIM_CMD_RX_CHECK_CHECK_TYPE_MASK (0x3000000U) +#define SPIM_CMD_RX_CHECK_CHECK_TYPE_SHIFT (24U) +#define SPIM_CMD_RX_CHECK_CHECK_TYPE(x) (((uint32_t)(x) << SPIM_CMD_RX_CHECK_CHECK_TYPE_SHIFT) & SPIM_CMD_RX_CHECK_CHECK_TYPE_MASK) +#define SPIM_CMD_RX_CHECK_BYTE_ALIGN_MASK (0x4000000U) +#define SPIM_CMD_RX_CHECK_BYTE_ALIGN_SHIFT (26U) +#define SPIM_CMD_RX_CHECK_BYTE_ALIGN(x) (((uint32_t)(x) << SPIM_CMD_RX_CHECK_BYTE_ALIGN_SHIFT) & SPIM_CMD_RX_CHECK_BYTE_ALIGN_MASK) + +/* The check bits transferred by QPI or not */ + +#define SPIM_CMD_RX_CHECK_QPI_MASK (0x8000000U) +#define SPIM_CMD_RX_CHECK_QPI_SHIFT (27U) +#define SPIM_CMD_RX_CHECK_QPI(x) (((uint32_t)(x) << SPIM_CMD_RX_CHECK_QPI_SHIFT) & SPIM_CMD_RX_CHECK_QPI_MASK) + +/* CMD_FULL_DULP - SPIM Activate full duplex mode */ + +#define SPIM_CMD_FULL_SIZE_CMD_MASK (0xFFFFU) +#define SPIM_CMD_FULL_SIZE_CMD_SHIFT (0U) +#define SPIM_CMD_FULL_SIZE_CMD(x) (((uint32_t)(x) /* << SPIM_CMD_FULL_SIZE_CMD_SHIFT */) & SPIM_CMD_FULL_SIZE_CMD_MASK) +#define SPIM_CMD_FULL_BYTE_ALIGN_CMD_MASK (0x4000000U) +#define SPIM_CMD_FULL_BYTE_ALIGN_CMD_SHIFT (26U) +#define SPIM_CMD_FULL_BYTE_ALIGN_CMD(x) (((uint32_t)(x) << SPIM_CMD_FULL_BYTE_ALIGN_CMD_SHIFT) & SPIM_CMD_FULL_BYTE_ALIGN_CMD_MASK) + +#define SPIM_CMD_CFG(clockDiv,cpol,cpha) (SPIM_CMD(SPIM_CMD_CFG_ID) \ + | SPIM_CMD_CFG_CLKDIV(clockDiv) \ + | SPIM_CMD_CFG_CPOL(cpol) \ + | SPIM_CMD_CFG_CPHA(cpha)) + +#define SPIM_CMD_SOT(cs) (SPIM_CMD(SPIM_CMD_SOT_ID) \ + | SPIM_CMD_SOT_CS(cs)) + +#define SPIM_CMD_SEND_CMD(cmd,bits,qpi) (SPIM_CMD(SPIM_CMD_SEND_CMD_ID) \ + | SPIM_CMD_SEND_VALUEL((cmd >> 8)) \ + | SPIM_CMD_SEND_VALUEH((cmd & 0xFF)) \ + | SPIM_CMD_SEND_CMD_SIZE(bits - 1) \ + | SPIM_CMD_SEND_QPI(qpi)) + +#define SPIM_CMD_SEND_ADDR(bits,qpi) (SPIM_CMD(SPIM_CMD_SEND_ADDR_ID) \ + | SPIM_CMD_SEND_ADDR_VALUE(0) \ + | SPIM_CMD_SEND_ADDR_CMD_SIZE((bits - 1)) \ + | SPIM_CMD_SEND_ADDR_QPI(qpi)) + +#ifndef __PLATFORM_GVSOC__ +#define SPIM_CMD_DUMMY(cycles) (cycles ? (SPIM_CMD(SPIM_CMD_DUMMY_ID) \ + | SPIM_CMD_DUMMY_CYCLE(cycles - 1)) : 0xFFFF0000u) +#else +#define SPIM_CMD_DUMMY(cycles) (cycles ? (SPIM_CMD(SPIM_CMD_DUMMY_ID) \ + | SPIM_CMD_DUMMY_CYCLE(cycles - 1)) : 0x0u) +#endif + +#define SPIM_CMD_TX_DATA(bits,qpi,byte_align) (SPIM_CMD(SPIM_CMD_TX_DATA_ID) \ + | SPIM_CMD_TX_DATA_SIZE((bits - 1)) \ + | SPIM_CMD_TX_DATA_BYTE_ALIGN(byte_align) \ + | SPIM_CMD_TX_DATA_QPI(qpi)) + +#define SPIM_CMD_RX_DATA(bits,qpi,byte_align) (SPIM_CMD(SPIM_CMD_RX_DATA_ID) \ + | SPIM_CMD_RX_DATA_SIZE((bits - 1)) \ + | SPIM_CMD_RX_DATA_BYTE_ALIGN(byte_align) \ + | SPIM_CMD_RX_DATA_QPI(qpi)) + +#define SPIM_CMD_RPT(iter) (SPIM_CMD(SPIM_CMD_RPT_ID) \ + | SPIM_CMD_RPT_CNT(iter)) + +#define SPIM_CMD_EOT(evt) (SPIM_CMD(SPIM_CMD_EOT_ID) \ + | SPIM_CMD_EOT_EVENT_GEN(evt)) + +#define SPIM_CMD_WAIT(event) (SPIM_CMD(SPIM_CMD_WAIT_ID) \ + | SPIM_CMD_WAIT_EVENT_ID(event)) + +#define SPIM_CMD_RPT_END() (SPIM_CMD(SPIM_CMD_RPT_END_ID)) + +#define SPIM_CMD_FUL(bits,byte_align) (SPIM_CMD(SPIM_CMD_RPT_END_ID) \ + | SPIM_CMD_FULL_SIZE_CMD((bits - 1)) \ + | SPIM_CMD_FULL_BYTE_ALIGN_CMD(byte_align)) + +#define SPIM_CMD_RX_CHECK(mode,bits,value,qpi,byte_align) \ + (SPIM_CMD(SPIM_CMD_RX_CHECK_ID) \ + | SPIM_CMD_RX_CHECK_COMP_DATA(value) \ + | SPIM_CMD_RX_CHECK_STATUS_SIZE((bits - 1)) \ + | SPIM_CMD_RX_CHECK_CHECK_TYPE(mode) \ + | SPIM_CMD_RX_CHECK_BYTE_ALIGN(byte_align) \ + | SPIM_CMD_RX_CHECK_QPI(qpi)) + +/* HYPERBUS - Register Layout Typedef */ + +typedef struct +{ + udma_reg_t UDMA_HYPERBUS; /* UDMA general register */ + volatile uint32_t EXT_ADDR; /* Memory access address register */ + volatile uint32_t EXT_CFG; /* Reserved */ + volatile uint32_t MEM_CFG0; /* Memory control Configuration register0 */ + volatile uint32_t MEM_CFG1; /* Memory control Configuration register1 */ + volatile uint32_t MEM_CFG2; /* Memory control Configuration register2 */ + volatile uint32_t MEM_CFG3; /* Memory control Configuration register3 */ + volatile uint32_t MEM_CFG4; /* Memory control Configuration register4 */ + volatile uint32_t MEM_CFG5; /* Memory control Configuration register5 */ + volatile uint32_t MEM_CFG6; /* Memory control Configuration register6 */ + volatile uint32_t MEM_CFG7; /* Memory control Configuration register7 */ +} hyperbus_reg_t; + +#define HYPERBUS_BASE0 (UDMA_BASE + 3 * 128U) +#define HYPERBUS0 ((hyperbus_reg_t *)HYPERBUS_BASE0) + +/* MEM_CFG0 - HYPERBUS Memory control Configuration register0 */ + +#define HYPERBUS_MEM_CFG0_MBR0_MASK (0xFFU) +#define HYPERBUS_MEM_CFG0_MBR0_SHIFT (0U) +#define HYPERBUS_MEM_CFG0_MBR0(x) (((uint32_t)(x) << HYPERBUS_MEM_CFG0_MBR0_SHIFT) & HYPERBUS_MEM_CFG0_MBR0_MASK) +#define HYPERBUS_MEM_CFG0_LATENCY0_MASK (0xF00U) +#define HYPERBUS_MEM_CFG0_LATENCY0_SHIFT (8U) +#define HYPERBUS_MEM_CFG0_LATENCY0(x) (((uint32_t)(x) << HYPERBUS_MEM_CFG0_LATENCY0_SHIFT) & HYPERBUS_MEM_CFG0_LATENCY0_MASK) +#define HYPERBUS_MEM_CFG0_WRAP_SIZE0_MASK (0x3000U) +#define HYPERBUS_MEM_CFG0_WRAP_SIZE0_SHIFT (12U) +#define HYPERBUS_MEM_CFG0_WRAP_SIZE0(x) (((uint32_t)(x) << HYPERBUS_MEM_CFG0_WRAP_SIZE0_SHIFT) & HYPERBUS_MEM_CFG0_WRAP_SIZE0_MASK) + +/* MEM_CFG1 - HYPERBUS Memory control Configuration register1 */ + +#define HYPERBUS_MEM_CFG1_RD_CSHI0_MASK (0xFU) +#define HYPERBUS_MEM_CFG1_RD_CSHI0_SHIFT (0U) +#define HYPERBUS_MEM_CFG1_RD_CSHI0(x) (((uint32_t)(x) << HYPERBUS_MEM_CFG1_RD_CSHI0_SHIFT) & HYPERBUS_MEM_CFG1_RD_CSHI0_MASK) +#define HYPERBUS_MEM_CFG1_RD_CSS0_MASK (0xF0U) +#define HYPERBUS_MEM_CFG1_RD_CSS0_SHIFT (4U) +#define HYPERBUS_MEM_CFG1_RD_CSS0(x) (((uint32_t)(x) << HYPERBUS_MEM_CFG1_RD_CSS0_SHIFT) & HYPERBUS_MEM_CFG1_RD_CSS0_MASK) +#define HYPERBUS_MEM_CFG1_RD_CSH0_MASK (0xF00U) +#define HYPERBUS_MEM_CFG1_RD_CSH0_SHIFT (8U) +#define HYPERBUS_MEM_CFG1_RD_CSH0(x) (((uint32_t)(x) << HYPERBUS_MEM_CFG1_RD_CSH0_SHIFT) & HYPERBUS_MEM_CFG1_RD_CSH0_MASK) +#define HYPERBUS_MEM_CFG1_WR_CSHI0_MASK (0xF000U) +#define HYPERBUS_MEM_CFG1_WR_CSHI0_SHIFT (12U) +#define HYPERBUS_MEM_CFG1_WR_CSHI0(x) (((uint32_t)(x) << HYPERBUS_MEM_CFG1_WR_CSHI0_SHIFT) & HYPERBUS_MEM_CFG1_WR_CSHI0_MASK) +#define HYPERBUS_MEM_CFG1_WR_CSS0_MASK (0xF0000U) +#define HYPERBUS_MEM_CFG1_WR_CSS0_SHIFT (16U) +#define HYPERBUS_MEM_CFG1_WR_CSS0(x) (((uint32_t)(x) << HYPERBUS_MEM_CFG1_WR_CSS0_SHIFT) & HYPERBUS_MEM_CFG1_WR_CSS0_MASK) +#define HYPERBUS_MEM_CFG1_WR_CSH0_MASK (0xF00000U) +#define HYPERBUS_MEM_CFG1_WR_CSH0_SHIFT (20U) +#define HYPERBUS_MEM_CFG1_WR_CSH0(x) (((uint32_t)(x) << HYPERBUS_MEM_CFG1_WR_CSH0_SHIFT) & HYPERBUS_MEM_CFG1_WR_CSH0_MASK) + +/* MEM_CFG2 - HYPERBUS Memory control Configuration register2 */ + +#define HYPERBUS_MEM_CFG2_RD_MAX_LENGTH0_MASK (0x1FFU) +#define HYPERBUS_MEM_CFG2_RD_MAX_LENGTH0_SHIFT (0U) +#define HYPERBUS_MEM_CFG2_RD_MAX_LENGTH0(x) (((uint32_t)(x) << HYPERBUS_MEM_CFG2_RD_MAX_LENGTH0_SHIFT) & HYPERBUS_MEM_CFG2_RD_MAX_LENGTH0_MASK) +#define HYPERBUS_MEM_CFG2_WR_MAX_LENGTH0_MASK (0x1FF0000U) +#define HYPERBUS_MEM_CFG2_WR_MAX_LENGTH0_SHIFT (16U) +#define HYPERBUS_MEM_CFG2_WR_MAX_LENGTH0(x) (((uint32_t)(x) << HYPERBUS_MEM_CFG2_WR_MAX_LENGTH0_SHIFT) & HYPERBUS_MEM_CFG2_WR_MAX_LENGTH0_MASK) + +/* MEM_CFG3 - HYPERBUS Memory control Configuration register3 */ + +#define HYPERBUS_MEM_CFG3_ACS0_MASK (0x1U) +#define HYPERBUS_MEM_CFG3_ACS0_SHIFT (0U) +#define HYPERBUS_MEM_CFG3_ACS0(x) (((uint32_t)(x) << HYPERBUS_MEM_CFG3_ACS0_SHIFT) & HYPERBUS_MEM_CFG3_ACS0_MASK) +#define HYPERBUS_MEM_CFG3_TCO0_MASK (0x2U) +#define HYPERBUS_MEM_CFG3_TCO0_SHIFT (1U) +#define HYPERBUS_MEM_CFG3_TCO0(x) (((uint32_t)(x) << HYPERBUS_MEM_CFG3_TCO0_SHIFT) & HYPERBUS_MEM_CFG3_TCO0_MASK) +#define HYPERBUS_MEM_CFG3_DT0_MASK (0x4U) +#define HYPERBUS_MEM_CFG3_DT0_SHIFT (2U) +#define HYPERBUS_MEM_CFG3_DT0(x) (((uint32_t)(x) << HYPERBUS_MEM_CFG3_DT0_SHIFT) & HYPERBUS_MEM_CFG3_DT0_MASK) +#define HYPERBUS_MEM_CFG3_CRT0_MASK (0x8U) +#define HYPERBUS_MEM_CFG3_CRT0_SHIFT (3U) +#define HYPERBUS_MEM_CFG3_CRT0(x) (((uint32_t)(x) << HYPERBUS_MEM_CFG3_CRT0_SHIFT) & HYPERBUS_MEM_CFG3_CRT0_MASK) +#define HYPERBUS_MEM_CFG3_RD_MAX_LEN_EN0_MASK (0x10U) +#define HYPERBUS_MEM_CFG3_RD_MAX_LEN_EN0_SHIFT (4U) +#define HYPERBUS_MEM_CFG3_RD_MAX_LEN_EN0(x) (((uint32_t)(x) << HYPERBUS_MEM_CFG3_RD_MAX_LEN_EN0_SHIFT) & HYPERBUS_MEM_CFG3_RD_MAX_LEN_EN0_MASK) +#define HYPERBUS_MEM_CFG3_WR_MAX_LEN_EN0_MASK (0x20U) +#define HYPERBUS_MEM_CFG3_WR_MAX_LEN_EN0_SHIFT (5U) +#define HYPERBUS_MEM_CFG3_WR_MAX_LEN_EN0(x) (((uint32_t)(x) << HYPERBUS_MEM_CFG3_WR_MAX_LEN_EN0_SHIFT) & HYPERBUS_MEM_CFG3_WR_MAX_LEN_EN0_MASK) +#define HYPERBUS_MEM_CFG3_RDS_DELAY_ADJ_MASK (0x300U) +#define HYPERBUS_MEM_CFG3_RDS_DELAY_ADJ_SHIFT (8U) +#define HYPERBUS_MEM_CFG3_RDS_DELAY_ADJ(x) (((uint32_t)(x) << HYPERBUS_MEM_CFG3_RDS_DELAY_ADJ_SHIFT) & HYPERBUS_MEM_CFG3_RDS_DELAY_ADJ_MASK) + +/* MEM_CFG4 - HYPERBUS Memory control Configuration register4 */ + +#define HYPERBUS_MEM_CFG4_MBR1_MASK (0xFFU) +#define HYPERBUS_MEM_CFG4_MBR1_SHIFT (0U) +#define HYPERBUS_MEM_CFG4_MBR1(x) (((uint32_t)(x) << HYPERBUS_MEM_CFG4_MBR1_SHIFT) & HYPERBUS_MEM_CFG4_MBR1_MASK) +#define HYPERBUS_MEM_CFG4_LATENCY1_MASK (0xF00U) +#define HYPERBUS_MEM_CFG4_LATENCY1_SHIFT (8U) +#define HYPERBUS_MEM_CFG4_LATENCY1(x) (((uint32_t)(x) << HYPERBUS_MEM_CFG4_LATENCY1_SHIFT) & HYPERBUS_MEM_CFG4_LATENCY1_MASK) +#define HYPERBUS_MEM_CFG4_WRAP_SIZE1_MASK (0x3000U) +#define HYPERBUS_MEM_CFG4_WRAP_SIZE1_SHIFT (12U) +#define HYPERBUS_MEM_CFG4_WRAP_SIZE1(x) (((uint32_t)(x) << HYPERBUS_MEM_CFG4_WRAP_SIZE1_SHIFT) & HYPERBUS_MEM_CFG4_WRAP_SIZE1_MASK) + +/* MEM_CFG5 - HYPERBUS Memory control Configuration register5 */ + +#define HYPERBUS_MEM_CFG5_RD_CSHI1_MASK (0xFU) +#define HYPERBUS_MEM_CFG5_RD_CSHI1_SHIFT (0U) +#define HYPERBUS_MEM_CFG5_RD_CSHI1(x) (((uint32_t)(x) << HYPERBUS_MEM_CFG5_RD_CSHI1_SHIFT) & HYPERBUS_MEM_CFG5_RD_CSHI1_MASK) +#define HYPERBUS_MEM_CFG5_RD_CSS1_MASK (0xF0U) +#define HYPERBUS_MEM_CFG5_RD_CSS1_SHIFT (4U) +#define HYPERBUS_MEM_CFG5_RD_CSS1(x) (((uint32_t)(x) << HYPERBUS_MEM_CFG5_RD_CSS1_SHIFT) & HYPERBUS_MEM_CFG5_RD_CSS1_MASK) +#define HYPERBUS_MEM_CFG5_RD_CSH1_MASK (0xF00U) +#define HYPERBUS_MEM_CFG5_RD_CSH1_SHIFT (8U) +#define HYPERBUS_MEM_CFG5_RD_CSH1(x) (((uint32_t)(x) << HYPERBUS_MEM_CFG5_RD_CSH1_SHIFT) & HYPERBUS_MEM_CFG5_RD_CSH1_MASK) +#define HYPERBUS_MEM_CFG5_WR_CSHI1_MASK (0xF000U) +#define HYPERBUS_MEM_CFG5_WR_CSHI1_SHIFT (12U) +#define HYPERBUS_MEM_CFG5_WR_CSHI1(x) (((uint32_t)(x) << HYPERBUS_MEM_CFG5_WR_CSHI1_SHIFT) & HYPERBUS_MEM_CFG5_WR_CSHI1_MASK) +#define HYPERBUS_MEM_CFG5_WR_CSS1_MASK (0xF0000U) +#define HYPERBUS_MEM_CFG5_WR_CSS1_SHIFT (16U) +#define HYPERBUS_MEM_CFG5_WR_CSS1(x) (((uint32_t)(x) << HYPERBUS_MEM_CFG5_WR_CSS1_SHIFT) & HYPERBUS_MEM_CFG5_WR_CSS1_MASK) +#define HYPERBUS_MEM_CFG5_WR_CSH1_MASK (0xF00000U) +#define HYPERBUS_MEM_CFG5_WR_CSH1_SHIFT (20U) +#define HYPERBUS_MEM_CFG5_WR_CSH1(x) (((uint32_t)(x) << HYPERBUS_MEM_CFG5_WR_CSH1_SHIFT) & HYPERBUS_MEM_CFG5_WR_CSH1_MASK) + +/* MEM_CFG6 - HYPERBUS Memory control Configuration register6 */ + +#define HYPERBUS_MEM_CFG6_RD_MAX_LENGTH1_MASK (0x1FFU) +#define HYPERBUS_MEM_CFG6_RD_MAX_LENGTH1_SHIFT (0U) +#define HYPERBUS_MEM_CFG6_RD_MAX_LENGTH1(x) (((uint32_t)(x) << HYPERBUS_MEM_CFG6_RD_MAX_LENGTH1_SHIFT) & HYPERBUS_MEM_CFG6_RD_MAX_LENGTH1_MASK) +#define HYPERBUS_MEM_CFG6_WR_MAX_LENGTH1_MASK (0x1FF0000U) +#define HYPERBUS_MEM_CFG6_WR_MAX_LENGTH1_SHIFT (16U) +#define HYPERBUS_MEM_CFG6_WR_MAX_LENGTH1(x) (((uint32_t)(x) << HYPERBUS_MEM_CFG6_WR_MAX_LENGTH1_SHIFT) & HYPERBUS_MEM_CFG6_WR_MAX_LENGTH1_MASK) + +/* MEM_CFG7 - HYPERBUS Memory control Configuration register7 */ + +#define HYPERBUS_MEM_CFG7_ACS1_MASK (0x1U) +#define HYPERBUS_MEM_CFG7_ACS1_SHIFT (0U) +#define HYPERBUS_MEM_CFG7_ACS1(x) (((uint32_t)(x) << HYPERBUS_MEM_CFG7_ACS1_SHIFT) & HYPERBUS_MEM_CFG7_ACS1_MASK) +#define HYPERBUS_MEM_CFG7_TCO1_MASK (0x2U) +#define HYPERBUS_MEM_CFG7_TCO1_SHIFT (1U) +#define HYPERBUS_MEM_CFG7_TCO1(x) (((uint32_t)(x) << HYPERBUS_MEM_CFG7_TCO1_SHIFT) & HYPERBUS_MEM_CFG7_TCO1_MASK) +#define HYPERBUS_MEM_CFG7_DT1_MASK (0x4U) +#define HYPERBUS_MEM_CFG7_DT1_SHIFT (2U) +#define HYPERBUS_MEM_CFG7_DT1(x) (((uint32_t)(x) << HYPERBUS_MEM_CFG7_DT1_SHIFT) & HYPERBUS_MEM_CFG7_DT1_MASK) +#define HYPERBUS_MEM_CFG7_CRT1_MASK (0x8U) +#define HYPERBUS_MEM_CFG7_CRT1_SHIFT (3U) +#define HYPERBUS_MEM_CFG7_CRT1(x) (((uint32_t)(x) << HYPERBUS_MEM_CFG7_CRT1_SHIFT) & HYPERBUS_MEM_CFG7_CRT1_MASK) +#define HYPERBUS_MEM_CFG7_RD_MAX_LEN_EN1_MASK (0x10U) +#define HYPERBUS_MEM_CFG7_RD_MAX_LEN_EN1_SHIFT (4U) +#define HYPERBUS_MEM_CFG7_RD_MAX_LEN_EN1(x) (((uint32_t)(x) << HYPERBUS_MEM_CFG7_RD_MAX_LEN_EN1_SHIFT) & HYPERBUS_MEM_CFG7_RD_MAX_LEN_EN1_MASK) +#define HYPERBUS_MEM_CFG7_WR_MAX_LEN_EN1_MASK (0x20U) +#define HYPERBUS_MEM_CFG7_WR_MAX_LEN_EN1_SHIFT (5U) +#define HYPERBUS_MEM_CFG7_WR_MAX_LEN_EN1(x) (((uint32_t)(x) << HYPERBUS_MEM_CFG7_WR_MAX_LEN_EN1_SHIFT) & HYPERBUS_MEM_CFG7_WR_MAX_LEN_EN1_MASK) + +/* UART - Register Layout Typedef */ + +typedef struct +{ + udma_reg_t UDMA_UART; /* UDMA general register */ + volatile uint32_t STATUS; /* Status register */ + volatile uint32_t SETUP; /* Configuration register */ +} uart_reg_t; + +#define UART_BASE (UDMA_BASE + 4 * 128U) +#define UART ((uart_reg_t *)UART_BASE) + +/* STATUS - UART Status register */ + +#define UART_STATUS_TX_BUSY_MASK (0x1U) +#define UART_STATUS_TX_BUSY_SHIFT (0U) +#define UART_STATUS_TX_BUSY(x) (((uint32_t)(x) << UART_STATUS_TX_BUSY_SHIFT) & UART_STATUS_TX_BUSY_MASK) +#define UART_STATUS_RX_BUSY_MASK (0x2U) +#define UART_STATUS_RX_BUSY_SHIFT (1U) +#define UART_STATUS_RX_BUSY(x) (((uint32_t)(x) << UART_STATUS_RX_BUSY_SHIFT) & UART_STATUS_RX_BUSY_MASK) +#define UART_STATUS_RX_PE_MASK (0x4U) +#define UART_STATUS_RX_PE_SHIFT (2U) +#define UART_STATUS_RX_PE(x) (((uint32_t)(x) << UART_STATUS_RX_PE_SHIFT) & UART_STATUS_RX_PE_MASK) + +/* SETUP - UART SETUP register */ + +#define UART_SETUP_PARITY_ENA_MASK (0x1U) +#define UART_SETUP_PARITY_ENA_SHIFT (0U) +#define UART_SETUP_PARITY_ENA(x) (((uint32_t)(x) << UART_SETUP_PARITY_ENA_SHIFT) & UART_SETUP_PARITY_ENA_MASK) + +#define UART_SETUP_BIT_LENGTH_MASK (0x6U) +#define UART_SETUP_BIT_LENGTH_SHIFT (1U) +#define UART_SETUP_BIT_LENGTH(x) (((uint32_t)(x) << UART_SETUP_BIT_LENGTH_SHIFT) & UART_SETUP_BIT_LENGTH_MASK) + +#define UART_SETUP_STOP_BITS_MASK (0x8U) +#define UART_SETUP_STOP_BITS_SHIFT (3U) +#define UART_SETUP_STOP_BITS(x) (((uint32_t)(x) << UART_SETUP_STOP_BITS_SHIFT) & UART_SETUP_STOP_BITS_MASK) + +#define UART_SETUP_TX_ENA_MASK (0x100U) +#define UART_SETUP_TX_ENA_SHIFT (8U) +#define UART_SETUP_TX_ENA(x) (((uint32_t)(x) << UART_SETUP_TX_ENA_SHIFT) & UART_SETUP_TX_ENA_MASK) + +#define UART_SETUP_RX_ENA_MASK (0x200U) +#define UART_SETUP_RX_ENA_SHIFT (9U) +#define UART_SETUP_RX_ENA(x) (((uint32_t)(x) << UART_SETUP_RX_ENA_SHIFT) & UART_SETUP_RX_ENA_MASK) + +#define UART_SETUP_CLKDIV_MASK (0xFFFF0000U) +#define UART_SETUP_CLKDIV_SHIFT (16U) +#define UART_SETUP_CLKDIV(x) (((uint32_t)(x) << UART_SETUP_CLKDIV_SHIFT) & UART_SETUP_CLKDIV_MASK) + +/* I2C - Register Layout Typedef */ + +typedef struct +{ + udma_reg_t UDMA_I2C; /* UDMA general register */ + volatile uint32_t STATUS; /* Status register */ + volatile uint32_t SETUP; /* Configuration register */ +} i2c_reg_t; + +#define I2C0_BASE (UDMA_BASE + 5 * 128U) +#define I2C0 ((i2c_reg_t *)I2C0_BASE) +#define I2C1_BASE (UDMA_BASE + 6 * 128U) +#define I2C1 ((i2c_reg_t *)I2C1_BASE) + +/* STATUS - I2C Status register */ + +#define I2C_STATUS_BUSY_MASK (0x1U) +#define I2C_STATUS_BUSY_SHIFT (0U) +#define I2C_STATUS_BUSY(x) (((uint32_t)(x) << I2C_STATUS_BUSY_SHIFT) & I2C_STATUS_BUSY_MASK) +#define I2C_STATUS_ARB_LOST_MASK (0x2U) +#define I2C_STATUS_ARB_LOST_SHIFT (1U) +#define I2C_STATUS_ARB_LOST(x) (((uint32_t)(x) << I2C_STATUS_ARB_LOST_SHIFT) & I2C_STATUS_ARB_LOST_MASK) + +/* SETUP - I2C SETUP register */ + +#define I2C_SETUP_DO_RST_MASK (0x1U) +#define I2C_SETUP_DO_RST_SHIFT (0U) +#define I2C_SETUP_DO_RST(x) (((uint32_t)(x) << I2C_SETUP_DO_RST_SHIFT) & I2C_SETUP_DO_RST_MASK) + +/* uDMA - I2C uDMA control CMD */ + +#define I2C_CMD_MASK (0xF0U) +#define I2C_CMD_SHIFT (4U) + +#define I2C_CMD_START ((((uint32_t)(0x0)) << I2C_CMD_SHIFT) & I2C_CMD_MASK) // 0x00 +#define I2C_CMD_WAIT_EV ((((uint32_t)(0x1)) << I2C_CMD_SHIFT) & I2C_CMD_MASK) // 0x10 +#define I2C_CMD_STOP ((((uint32_t)(0x2)) << I2C_CMD_SHIFT) & I2C_CMD_MASK) // 0x20 +#define I2C_CMD_RD_ACK ((((uint32_t)(0x4)) << I2C_CMD_SHIFT) & I2C_CMD_MASK) // 0x40 +#define I2C_CMD_RD_NACK ((((uint32_t)(0x6)) << I2C_CMD_SHIFT) & I2C_CMD_MASK) // 0x60 +#define I2C_CMD_WR ((((uint32_t)(0x8)) << I2C_CMD_SHIFT) & I2C_CMD_MASK) // 0x80 +#define I2C_CMD_WAIT ((((uint32_t)(0xA)) << I2C_CMD_SHIFT) & I2C_CMD_MASK) // 0xA0 +#define I2C_CMD_RPT ((((uint32_t)(0xC)) << I2C_CMD_SHIFT) & I2C_CMD_MASK) // 0xC0 +#define I2C_CMD_CFG ((((uint32_t)(0xE)) << I2C_CMD_SHIFT) & I2C_CMD_MASK) // 0xE0 + +/* TCDM - Register Layout Typedef */ + +typedef struct +{ + udma_reg_t UDMA_TCDM; /* UDMA general register */ + volatile uint32_t DST_ADDR; /* destination address register */ + volatile uint32_t SRC_ADDR; /* source address register */ +} tcdm_reg_t; + +#define TCDM_BASE (UDMA_BASE + 7 * 128U) +#define TCDM ((tcdm_reg_t *)TCDM_BASE) + +/* DST_ADDR - TCDM destination address register */ + +#define TCDM_DST_ADDR_MASK (0x1FFFFU) +#define TCDM_DST_ADDR_SHIFT (0U) +#define TCDM_DST_ADDR(x) (((uint32_t)(x) << TCDM_DST_ADDR_SHIFT) & TCDM_DST_ADDR_MASK) + +/* SRC_ADDR - TCDM source address register */ + +#define TCDM_SRC_ADDR_MASK (0x1FFFFU) +#define TCDM_SRC_ADDR_SHIFT (0U) +#define TCDM_SRC_ADDR(x) (((uint32_t)(x) << TCDM_SRC_ADDR_SHIFT) & TCDM_SRC_ADDR_MASK) + +/* I2S - Register Layout Typedef */ + +typedef struct +{ + udma_reg_t UDMA_I2S; /* UDMA general register */ + volatile uint32_t EXT; /* external clock configuration register */ + volatile uint32_t CFG_CLKGEN0; /* clock/WS generator 0 configuration register */ + volatile uint32_t CFG_CLKGEN1; /* clock/WS generator 1 configuration register */ + volatile uint32_t CHMODE; /* channels mode configuration register */ + volatile uint32_t FILT_CH0; /* channels 0 filtering configuration register */ + volatile uint32_t FILT_CH1; /* channels 0 filtering configuration register */ +} i2s_reg_t; + +#define I2S_BASE (UDMA_BASE + 8 * 128U) +#define I2S ((i2s_reg_t *)I2S_BASE) + +/* EXT - I2S external clock configuration Register */ + +#define I2S_EXT_BITS_WORD_MASK (0x1FU) +#define I2S_EXT_BITS_WORD_SHIFT (0U) +#define I2S_EXT_BITS_WORD(x) (((uint32_t)(x) << I2S_EXT_BITS_WORD_SHIFT) & I2S_EXT_BITS_WORD_MASK) + +/* CFG_CLKGEN0 - I2S clock/WS generator 0 configuration Register */ + +#define I2S_CFG_CLKGEN0_BITS_WORD_MASK (0x1FU) +#define I2S_CFG_CLKGEN0_BITS_WORD_SHIFT (0U) +#define I2S_CFG_CLKGEN0_BITS_WORD(x) (((uint32_t)(x) << I2S_CFG_CLKGEN0_BITS_WORD_SHIFT) & I2S_CFG_CLKGEN0_BITS_WORD_MASK) +#define I2S_CFG_CLKGEN0_CLK_EN_MASK (0x100U) +#define I2S_CFG_CLKGEN0_CLK_EN_SHIFT (8U) +#define I2S_CFG_CLKGEN0_CLK_EN(x) (((uint32_t)(x) << I2S_CFG_CLKGEN0_CLK_EN_SHIFT) & I2S_CFG_CLKGEN0_CLK_EN_MASK) +#define I2S_CFG_CLKGEN0_CLK_DIV_MASK (0xFFFF0000U) +#define I2S_CFG_CLKGEN0_CLK_DIV_SHIFT (16U) +#define I2S_CFG_CLKGEN0_CLK_DIV(x) (((uint32_t)(x) << I2S_CFG_CLKGEN0_CLK_DIV_SHIFT) & I2S_CFG_CLKGEN0_CLK_DIV_MASK) + +/* CFG_CLKGEN1 - I2S clock/WS generator 1 configuration Register */ + +#define I2S_CFG_CLKGEN1_BITS_WORD_MASK (0x1FU) +#define I2S_CFG_CLKGEN1_BITS_WORD_SHIFT (0U) +#define I2S_CFG_CLKGEN1_BITS_WORD(x) (((uint32_t)(x) << I2S_CFG_CLKGEN1_BITS_WORD_SHIFT) & I2S_CFG_CLKGEN1_BITS_WORD_MASK) +#define I2S_CFG_CLKGEN1_CLK_EN_MASK (0x100U) +#define I2S_CFG_CLKGEN1_CLK_EN_SHIFT (8U) +#define I2S_CFG_CLKGEN1_CLK_EN(x) (((uint32_t)(x) << I2S_CFG_CLKGEN1_CLK_EN_SHIFT) & I2S_CFG_CLKGEN1_CLK_EN_MASK) +#define I2S_CFG_CLKGEN1_CLK_DIV_MASK (0xFFFF0000U) +#define I2S_CFG_CLKGEN1_CLK_DIV_SHIFT (16U) +#define I2S_CFG_CLKGEN1_CLK_DIV(x) (((uint32_t)(x) << I2S_CFG_CLKGEN1_CLK_DIV_SHIFT) & I2S_CFG_CLKGEN1_CLK_DIV_MASK) + +/* CHMODE - I2S channels mode configuration Register */ + +#define I2S_CHMODE_CH0_SNAP_CAM_MASK (0x1U) +#define I2S_CHMODE_CH0_SNAP_CAM_SHIFT (0U) +#define I2S_CHMODE_CH0_SNAP_CAM(x) (((uint32_t)(x) << I2S_CHMODE_CH0_SNAP_CAM_SHIFT) & I2S_CHMODE_CH0_SNAP_CAM_MASK) +#define I2S_CHMODE_CH0_LSB_FIRST_MASK (0x10U) +#define I2S_CHMODE_CH0_LSB_FIRST_SHIFT (4U) +#define I2S_CHMODE_CH0_LSB_FIRST(x) (((uint32_t)(x) << I2S_CHMODE_CH0_LSB_FIRST_SHIFT) & I2S_CHMODE_CH0_LSB_FIRST_MASK) +#define I2S_CHMODE_CH0_PDM_USEFILTER_MASK (0x100U) +#define I2S_CHMODE_CH0_PDM_USEFILTER_SHIFT (8U) +#define I2S_CHMODE_CH0_PDM_USEFILTER(x) (((uint32_t)(x) << I2S_CHMODE_CH0_PDM_USEFILTER_SHIFT) & I2S_CHMODE_CH0_PDM_USEFILTER_MASK) +#define I2S_CHMODE_CH0_PDM_EN_MASK (0x1000U) +#define I2S_CHMODE_CH0_PDM_EN_SHIFT (12U) +#define I2S_CHMODE_CH0_PDM_EN(x) (((uint32_t)(x) << I2S_CHMODE_CH0_PDM_EN_SHIFT) & I2S_CHMODE_CH0_PDM_EN_MASK) +#define I2S_CHMODE_CH0_USEDDR_MASK (0x10000U) +#define I2S_CHMODE_CH0_USEDDR_SHIFT (16U) +#define I2S_CHMODE_CH0_USEDDR(x) (((uint32_t)(x) << I2S_CHMODE_CH0_USEDDR_SHIFT) & I2S_CHMODE_CH0_USEDDR_MASK) +#define I2S_CHMODE_CH0_MODE_MASK (0x3000000U) +#define I2S_CHMODE_CH0_MODE_SHIFT (24U) +#define I2S_CHMODE_CH0_MODE(x) (((uint32_t)(x) << I2S_CHMODE_CH0_MODE_SHIFT) & I2S_CHMODE_CH0_MODE_MASK) + +#define I2S_CHMODE_CH1_SNAP_CAM_MASK (0x2U) +#define I2S_CHMODE_CH1_SNAP_CAM_SHIFT (1U) +#define I2S_CHMODE_CH1_SNAP_CAM(x) (((uint32_t)(x) << I2S_CHMODE_CH1_SNAP_CAM_SHIFT) & I2S_CHMODE_CH1_SNAP_CAM_MASK) +#define I2S_CHMODE_CH1_LSB_FIRST_MASK (0x20U) +#define I2S_CHMODE_CH1_LSB_FIRST_SHIFT (5U) +#define I2S_CHMODE_CH1_LSB_FIRST(x) (((uint32_t)(x) << I2S_CHMODE_CH1_LSB_FIRST_SHIFT) & I2S_CHMODE_CH1_LSB_FIRST_MASK) +#define I2S_CHMODE_CH1_PDM_USEFILTER_MASK (0x200U) +#define I2S_CHMODE_CH1_PDM_USEFILTER_SHIFT (9U) +#define I2S_CHMODE_CH1_PDM_USEFILTER(x) (((uint32_t)(x) << I2S_CHMODE_CH1_PDM_USEFILTER_SHIFT) & I2S_CHMODE_CH1_PDM_USEFILTER_MASK) +#define I2S_CHMODE_CH1_PDM_EN_MASK (0x2000U) +#define I2S_CHMODE_CH1_PDM_EN_SHIFT (13U) +#define I2S_CHMODE_CH1_PDM_EN(x) (((uint32_t)(x) << I2S_CHMODE_CH1_PDM_EN_SHIFT) & I2S_CHMODE_CH1_PDM_EN_MASK) +#define I2S_CHMODE_CH1_USEDDR_MASK (0x20000U) +#define I2S_CHMODE_CH1_USEDDR_SHIFT (17U) +#define I2S_CHMODE_CH1_USEDDR(x) (((uint32_t)(x) << I2S_CHMODE_CH1_USEDDR_SHIFT) & I2S_CHMODE_CH1_USEDDR_MASK) +#define I2S_CHMODE_CH1_MODE_MASK (0xC000000U) +#define I2S_CHMODE_CH1_MODE_SHIFT (26U) +#define I2S_CHMODE_CH1_MODE(x) (((uint32_t)(x) << I2S_CHMODE_CH1_MODE_SHIFT) & I2S_CHMODE_CH1_MODE_MASK) + +/* FILT_CH0 - I2S channels 0 filtering configuration Register */ + +#define I2S_FILT_CH0_DECIMATION_MASK (0x3FFU) +#define I2S_FILT_CH0_DECIMATION_SHIFT (0U) +#define I2S_FILT_CH0_DECIMATION(x) (((uint32_t)(x) << I2S_FILT_CH0_DECIMATION_SHIFT) & I2S_FILT_CH0_DECIMATION_MASK) +#define I2S_FILT_CH0_SHIFT_MASK (0x70000U) +#define I2S_FILT_CH0_SHIFT_SHIFT (16U) +#define I2S_FILT_CH0_SHIFT(x) (((uint32_t)(x) << I2S_FILT_CH0_SHIFT_SHIFT) & I2S_FILT_CH0_SHIFT_MASK) + +/* FILT_CH1 - I2S channels 0 filtering configuration Register */ + +#define I2S_FILT_CH1_DECIMATION_MASK (0x3FFU) +#define I2S_FILT_CH1_DECIMATION_SHIFT (0U) +#define I2S_FILT_CH1_DECIMATION(x) (((uint32_t)(x) << I2S_FILT_CH1_DECIMATION_SHIFT) & I2S_FILT_CH1_DECIMATION_MASK) +#define I2S_FILT_CH1_SHIFT_MASK (0x70000U) +#define I2S_FILT_CH1_SHIFT_SHIFT (16U) +#define I2S_FILT_CH1_SHIFT(x) (((uint32_t)(x) << I2S_FILT_CH1_SHIFT_SHIFT) & I2S_FILT_CH1_SHIFT_MASK) + +/* CPI - Register Layout Typedef */ + +typedef struct +{ + udma_reg_t UDMA_CPI; /* UDMA general register */ + volatile uint32_t CFG_GLOB; /* global configuration register */ + volatile uint32_t CFG_LL; /* lower left comer configuration register */ + volatile uint32_t CFG_UR; /* upper right comer configuration register */ + volatile uint32_t CFG_SIZE; /* horizontal resolution configuration register */ + volatile uint32_t CFG_FILTER; /* RGB coefficients configuration register */ +} cpi_reg_t; + +#define CPI_BASE (UDMA_BASE + 9 * 128U) +#define CPI ((cpi_reg_t *)CPI_BASE) + +/* CFG_GLOB - CPI global configuration register */ + +#define CPI_CFG_GLOB_FRAMEDROP_EN_MASK (0x1U) +#define CPI_CFG_GLOB_FRAMEDROP_EN_SHIFT (0U) +#define CPI_CFG_GLOB_FRAMEDROP_EN(x) (((uint32_t)(x) << CPI_CFG_GLOB_FRAMEDROP_EN_SHIFT) & CPI_CFG_GLOB_FRAMEDROP_EN_MASK) +#define CPI_CFG_GLOB_FRAMEDROP_VAL_MASK (0x7EU) +#define CPI_CFG_GLOB_FRAMEDROP_VAL_SHIFT (1U) +#define CPI_CFG_GLOB_FRAMEDROP_VAL(x) (((uint32_t)(x) << CPI_CFG_GLOB_FRAMEDROP_VAL_SHIFT) & CPI_CFG_GLOB_FRAMEDROP_VAL_MASK) +#define CPI_CFG_GLOB_FRAMESLICE_EN_MASK (0x80U) +#define CPI_CFG_GLOB_FRAMESLICE_EN_SHIFT (7U) +#define CPI_CFG_GLOB_FRAMESLICE_EN(x) (((uint32_t)(x) << CPI_CFG_GLOB_FRAMESLICE_EN_SHIFT) & CPI_CFG_GLOB_FRAMESLICE_EN_MASK) +#define CPI_CFG_GLOB_FORMAT_MASK (0x700U) +#define CPI_CFG_GLOB_FORMAT_SHIFT (8U) +#define CPI_CFG_GLOB_FORMAT(x) (((uint32_t)(x) << CPI_CFG_GLOB_FORMAT_SHIFT) & CPI_CFG_GLOB_FORMAT_MASK) +#define CPI_CFG_GLOB_SHIFT_MASK (0x7800U) +#define CPI_CFG_GLOB_SHIFT_SHIFT (11U) +#define CPI_CFG_GLOB_SHIFT(x) (((uint32_t)(x) << CPI_CFG_GLOB_SHIFT_SHIFT) & CPI_CFG_GLOB_SHIFT_MASK) +#define CPI_CFG_GLOB_EN_MASK (0x80000000U) +#define CPI_CFG_GLOB_EN_SHIFT (31U) +#define CPI_CFG_GLOB_EN(x) (((uint32_t)(x) << CPI_CFG_GLOB_EN_SHIFT) & CPI_CFG_GLOB_EN_MASK) + +/* CFG_LL - CPI lower left comer configuration register */ + +#define CPI_CFG_LL_FRAMESLICE_LLX_MASK (0xFFFFU) +#define CPI_CFG_LL_FRAMESLICE_LLX_SHIFT (0U) +#define CPI_CFG_LL_FRAMESLICE_LLX(x) (((uint32_t)(x) << CPI_CFG_LL_FRAMESLICE_LLX_SHIFT) & CPI_CFG_LL_FRAMESLICE_LLX_MASK) +#define CPI_CFG_LL_FRAMESLICE_LLY_MASK (0xFFFF0000U) +#define CPI_CFG_LL_FRAMESLICE_LLY_SHIFT (16U) +#define CPI_CFG_LL_FRAMESLICE_LLY(x) (((uint32_t)(x) << CPI_CFG_LL_FRAMESLICE_LLY_SHIFT) & CPI_CFG_LL_FRAMESLICE_LLY_MASK) + +/* CFG_UR - CPI upper right comer configuration register */ + +#define CPI_CFG_UR_FRAMESLICE_URX_MASK (0xFFFFU) +#define CPI_CFG_UR_FRAMESLICE_URX_SHIFT (0U) +#define CPI_CFG_UR_FRAMESLICE_URX(x) (((uint32_t)(x) << CPI_CFG_UR_FRAMESLICE_URX_SHIFT) & CPI_CFG_UR_FRAMESLICE_URX_MASK) +#define CPI_CFG_UR_FRAMESLICE_URY_MASK (0xFFFF0000U) +#define CPI_CFG_UR_FRAMESLICE_URY_SHIFT (16U) +#define CPI_CFG_UR_FRAMESLICE_URY(x) (((uint32_t)(x) << CPI_CFG_UR_FRAMESLICE_URY_SHIFT) & CPI_CFG_UR_FRAMESLICE_URY_MASK) + +/* CFG_SIZE - CPI horizontal resolution configuration register */ + +#define CPI_CFG_SIZE_MASK (0xFFFF0000U) +#define CPI_CFG_SIZE_SHIFT (16U) +#define CPI_CFG_SIZE(x) (((uint32_t)(x) << CPI_CFG_SIZE_SHIFT) & CPI_CFG_SIZE_MASK) + +/* CFG_FILTER - CPI RGB coefficients configuration register */ + +#define CPI_CFG_FILTER_B_COEFF_MASK (0xFFU) +#define CPI_CFG_FILTER_B_COEFF_SHIFT (0U) +#define CPI_CFG_FILTER_B_COEFF(x) (((uint32_t)(x) << CPI_CFG_FILTER_B_COEFF_SHIFT) & CPI_CFG_FILTER_B_COEFF_MASK) +#define CPI_CFG_FILTER_G_COEFF_MASK (0xFF00U) +#define CPI_CFG_FILTER_G_COEFF_SHIFT (8U) +#define CPI_CFG_FILTER_G_COEFF(x) (((uint32_t)(x) << CPI_CFG_FILTER_G_COEFF_SHIFT) & CPI_CFG_FILTER_G_COEFF_MASK) +#define CPI_CFG_FILTER_R_COEFF_MASK (0xFF0000U) +#define CPI_CFG_FILTER_R_COEFF_SHIFT (16U) +#define CPI_CFG_FILTER_R_COEFF(x) (((uint32_t)(x) << CPI_CFG_FILTER_R_COEFF_SHIFT) & CPI_CFG_FILTER_R_COEFF_MASK) + +/* SOC_CTRL - Registers Layout Typedef */ + +typedef struct +{ + volatile uint32_t INFO; /* SOC_CTRL INFO register */ + volatile uint32_t _reserved0[2]; /* reserved */ + volatile uint32_t CLUSTER_ISO; /* SOC_CTRL Cluster Isolate register */ + volatile uint32_t _reserved1[23]; /* reserved */ + volatile uint32_t CLUSTER_BUSY; /* SOC_CTRL Busy register */ + volatile uint32_t CLUSTER_BYPASS; /* SOC_CTRL Cluster PMU bypass register */ + volatile uint32_t JTAG_REG; /* SOC_CTRL Jtag register */ + volatile uint32_t L2_SLEEP; /* SOC_CTRL L2 memory sleep register */ + volatile uint32_t SLEEP_CTRL; /* SOC_CTRL Slepp control register */ + volatile uint32_t CLKDIV0; /* SOC_CTRL Slepp control register */ + volatile uint32_t CLKDIV1; /* SOC_CTRL Slepp control register */ + volatile uint32_t CLKDIV2; /* SOC_CTRL Slepp control register */ + volatile uint32_t CLKDIV3; /* SOC_CTRL Slepp control register */ + volatile uint32_t CLKDIV4; /* SOC_CTRL Slepp control register */ + volatile uint32_t _reserved2[3]; /* reserved */ + volatile uint32_t CORE_STATUS; /* SOC_CTRL Slepp control register */ + volatile uint32_t CORE_STATUS_EOC; /* SOC_CTRL Slepp control register */ +} soc_strl_reg_t; + +#define SOC_CTRL_BASE (0x1A104000) +#define SOC_CTRL ((soc_strl_reg_t *)SOC_CTRL_BASE) + +/* CLUSTER_BYPASS - SOC_CTRL information register */ + +#define SOC_CTRL_CLUSTER_BYPASS_BYP_POW_MASK (0x1U) +#define SOC_CTRL_CLUSTER_BYPASS_BYP_POW_SHIFT (0U) +#define SOC_CTRL_CLUSTER_BYPASS_BYP_POW(x) (((uint32_t)(x) /* << SOC_CTRL_CLUSTER_BYPASS_BYP_POW_SHIFT*/) & SOC_CTRL_CLUSTER_BYPASS_BYP_POW_MASK) + +#define SOC_CTRL_CLUSTER_BYPASS_BYP_CFG_MASK (0x2U) +#define SOC_CTRL_CLUSTER_BYPASS_BYP_CFG_SHIFT (1U) +#define SOC_CTRL_CLUSTER_BYPASS_BYP_CFG(x) (((uint32_t)(x) << SOC_CTRL_CLUSTER_BYPASS_BYP_CFG_SHIFT) & SOC_CTRL_CLUSTER_BYPASS_BYP_CFG_MASK) + +#define SOC_CTRL_CLUSTER_BYPASS_POW_MASK (0x8U) +#define SOC_CTRL_CLUSTER_BYPASS_POW_SHIFT (3U) +#define SOC_CTRL_CLUSTER_BYPASS_POW(x) (((uint32_t)(x) << SOC_CTRL_CLUSTER_BYPASS_POW_SHIFT) & SOC_CTRL_CLUSTER_BYPASS_POW_MASK) + +#define SOC_CTRL_CLUSTER_BYPASS_CUURENT_SET_MASK (0x70U) +#define SOC_CTRL_CLUSTER_BYPASS_CUURENT_SET_SHIFT (4U) +#define SOC_CTRL_CLUSTER_BYPASS_CUURENT_SET(x) (((uint32_t)(x) << SOC_CTRL_CLUSTER_BYPASS_CUURENT_SET_SHIFT) & SOC_CTRL_CLUSTER_BYPASS_CUURENT_SET_MASK) + +#define SOC_CTRL_CLUSTER_BYPASS_DELAY_MASK (0x180U) +#define SOC_CTRL_CLUSTER_BYPASS_DELAY_SHIFT (7U) +#define SOC_CTRL_CLUSTER_BYPASS_DELAY(x) (((uint32_t)(x) << SOC_CTRL_CLUSTER_BYPASS_DELAY_SHIFT) & SOC_CTRL_CLUSTER_BYPASS_DELAY_MASK) + +#define SOC_CTRL_CLUSTER_BYPASS_BYP_CLK_MASK (0x200U) +#define SOC_CTRL_CLUSTER_BYPASS_BYP_CLK_SHIFT (9U) +#define SOC_CTRL_CLUSTER_BYPASS_BYP_CLK(x) (((uint32_t)(x) << SOC_CTRL_CLUSTER_BYPASS_BYP_CLK_SHIFT) & SOC_CTRL_CLUSTER_BYPASS_BYP_CLK_MASK) + +#define SOC_CTRL_CLUSTER_BYPASS_CLK_GATE_MASK (0x400U) +#define SOC_CTRL_CLUSTER_BYPASS_CLK_GATE_SHIFT (10U) +#define SOC_CTRL_CLUSTER_BYPASS_CLK_GATE(x) (((uint32_t)(x) << SOC_CTRL_CLUSTER_BYPASS_CLK_GATE_SHIFT) & SOC_CTRL_CLUSTER_BYPASS_CLK_GATE_MASK) +#define READ_SOC_CTRL_CLUSTER_BYPASS_CLK_GATE(x) (((uint32_t)(x) & SOC_CTRL_CLUSTER_BYPASS_CLK_GATE_MASK) >> SOC_CTRL_CLUSTER_BYPASS_CLK_GATE_SHIFT) + +#define SOC_CTRL_CLUSTER_BYPASS_FLL_PWD_MASK (0x800U) +#define SOC_CTRL_CLUSTER_BYPASS_FLL_PWD_SHIFT (11U) +#define SOC_CTRL_CLUSTER_BYPASS_FLL_PWD(x) (((uint32_t)(x) << SOC_CTRL_CLUSTER_BYPASS_FLL_PWD_SHIFT) & SOC_CTRL_CLUSTER_BYPASS_FLL_PWD_MASK) + +#define SOC_CTRL_CLUSTER_BYPASS_FLL_RET_MASK (0x1000U) +#define SOC_CTRL_CLUSTER_BYPASS_FLL_RET_SHIFT (12U) +#define SOC_CTRL_CLUSTER_BYPASS_FLL_RET(x) (((uint32_t)(x) << SOC_CTRL_CLUSTER_BYPASS_FLL_RET_SHIFT) & SOC_CTRL_CLUSTER_BYPASS_FLL_RET_MASK) + +#define SOC_CTRL_CLUSTER_BYPASS_RESET_MASK (0x2000U) +#define SOC_CTRL_CLUSTER_BYPASS_RESET_SHIFT (13U) +#define SOC_CTRL_CLUSTER_BYPASS_RESET(x) (((uint32_t)(x) << SOC_CTRL_CLUSTER_BYPASS_RESET_SHIFT) & SOC_CTRL_CLUSTER_BYPASS_RESET_MASK) + +#define SOC_CTRL_CLUSTER_BYPASS_BYP_ISO_MASK (0x4000U) +#define SOC_CTRL_CLUSTER_BYPASS_BYP_ISO_SHIFT (14U) +#define SOC_CTRL_CLUSTER_BYPASS_BYP_ISO(x) (((uint32_t)(x) << SOC_CTRL_CLUSTER_BYPASS_BYP_ISO_SHIFT) & SOC_CTRL_CLUSTER_BYPASS_BYP_ISO_MASK) + +#define SOC_CTRL_CLUSTER_BYPASS_PW_ISO_MASK (0x8000U) +#define SOC_CTRL_CLUSTER_BYPASS_PW_ISO_SHIFT (15U) +#define SOC_CTRL_CLUSTER_BYPASS_PW_ISO(x) (((uint32_t)(x) << SOC_CTRL_CLUSTER_BYPASS_PW_ISO_SHIFT) & SOC_CTRL_CLUSTER_BYPASS_PW_ISO_MASK) +#define READ_SOC_CTRL_CLUSTER_BYPASS_PW_ISO(x) (((uint32_t)(x) & SOC_CTRL_CLUSTER_BYPASS_PW_ISO_MASK) >> SOC_CTRL_CLUSTER_BYPASS_PW_ISO_SHIFT) + +/* STATUS - SOC_CTRL status register */ + +#define SOC_CTRL_CORE_STATUS_EOC_MASK (0x80000000U) +#define SOC_CTRL_CORE_STATUS_EOC_SHIFT (31U) +#define SOC_CTRL_CORE_STATUS_EOC(x) (((uint32_t)(x) << SOC_CTRL_CORE_STATUS_EOC_SHIFT) & SOC_CTRL_CORE_STATUS_EOC_MASK) + +/* PMU - General Register Layout Typedef */ + +typedef struct +{ + volatile uint32_t RAR_DCDC; /* CTRL control register */ + volatile uint32_t SLEEP_CTRL; /* CTRL sleep control register */ + volatile uint32_t FORCE; /* CTRL register */ +} soc_ctrl_pmu_reg_t; + +#define PMU_CTRL_BASE (SOC_CTRL_BASE + 0x0100u) +#define PMU_CTRL ((soc_ctrl_pmu_reg_t *)PMU_CTRL_BASE) + +/* RAR_DCDC - PMU control register */ + +#define PMU_CTRL_RAR_DCDC_NV_MASK (0x1FU) +#define PMU_CTRL_RAR_DCDC_NV_SHIFT (0U) + +#define PMU_CTRL_RAR_DCDC_NV(x) (((uint32_t)(x) /* << PMU_CTRL_RAR_DCDC_NV_SHIFT */) & PMU_CTRL_RAR_DCDC_NV_MASK) + +#define READ_PMU_CTRL_RAR_DCDC_NV(x) (((uint32_t)(x) & PMU_CTRL_RAR_DCDC_NV_MASK) /* >> PMU_CTRL_RAR_DCDC_NV_SHIFT */) + +#define PMU_CTRL_RAR_DCDC_MV_MASK (0x1F00U) +#define PMU_CTRL_RAR_DCDC_MV_SHIFT (8U) +#define PMU_CTRL_RAR_DCDC_MV(x) (((uint32_t)(x) << PMU_CTRL_RAR_DCDC_MV_SHIFT) & PMU_CTRL_RAR_DCDC_MV_MASK) +#define READ_PMU_CTRL_RAR_DCDC_MV(x) (((uint32_t)(x) & PMU_CTRL_RAR_DCDC_MV_MASK) >> PMU_CTRL_RAR_DCDC_MV_SHIFT) +#define PMU_CTRL_RAR_DCDC_LV_MASK (0x1F0000U) +#define PMU_CTRL_RAR_DCDC_LV_SHIFT (16U) +#define PMU_CTRL_RAR_DCDC_LV(x) (((uint32_t)(x) << PMU_CTRL_RAR_DCDC_LV_SHIFT) & PMU_CTRL_RAR_DCDC_LV_MASK) +#define READ_PMU_CTRL_RAR_DCDC_LV(x) (((uint32_t)(x) & PMU_CTRL_RAR_DCDC_LV_MASK) >> PMU_CTRL_RAR_DCDC_LV_SHIFT) +#define PMU_CTRL_RAR_DCDC_RV_MASK (0x1F000000U) +#define PMU_CTRL_RAR_DCDC_RV_SHIFT (24U) +#define PMU_CTRL_RAR_DCDC_RV(x) (((uint32_t)(x) << PMU_CTRL_RAR_DCDC_RV_SHIFT) & PMU_CTRL_RAR_DCDC_RV_MASK) +#define READ_PMU_CTRL_RAR_DCDC_RV(x) (((uint32_t)(x) & PMU_CTRL_RAR_DCDC_RV_MASK) >> PMU_CTRL_RAR_DCDC_RV_SHIFT) + +/* SLEEP_CTRL - PMU control register */ + +#define PMU_CTRL_SLEEP_CTRL_CFG_MEM_RET_MASK (0xFU) +#define PMU_CTRL_SLEEP_CTRL_CFG_MEM_RET_SHIFT (0U) + +#define PMU_CTRL_SLEEP_CTRL_CFG_MEM_RET(x) (((uint32_t)(x) /* << PMU_CTRL_SLEEP_CTRL_CFG_MEM_RET_SHIFT */) & PMU_CTRL_SLEEP_CTRL_CFG_MEM_RET_MASK) + +#define READ_PMU_CTRL_SLEEP_CTRL_CFG_MEM_RET(x) (((uint32_t)(x) & PMU_CTRL_SLEEP_CTRL_CFG_MEM_RET_MASK) /* >> PMU_CTRL_SLEEP_CTRL_CFG_MEM_RET_SHIFT */) + +#define PMU_CTRL_SLEEP_CTRL_CFG_FLL_SOC_RET_MASK (0x10U) +#define PMU_CTRL_SLEEP_CTRL_CFG_FLL_SOC_RET_SHIFT (4U) +#define PMU_CTRL_SLEEP_CTRL_CFG_FLL_SOC_RET(x) (((uint32_t)(x) << PMU_CTRL_SLEEP_CTRL_CFG_FLL_SOC_RET_SHIFT) & PMU_CTRL_SLEEP_CTRL_CFG_FLL_SOC_RET_MASK) +#define READ_PMU_CTRL_SLEEP_CTRL_CFG_FLL_SOC_RET(x) (((uint32_t)(x) & PMU_CTRL_SLEEP_CTRL_CFG_FLL_SOC_RET_MASK) >> PMU_CTRL_SLEEP_CTRL_CFG_FLL_SOC_RET_SHIFT) + +#define PMU_CTRL_SLEEP_CTRL_CFG_FLL_CLUSTER_RET_MASK (0x20U) +#define PMU_CTRL_SLEEP_CTRL_CFG_FLL_CLUSTER_RET_SHIFT (5U) +#define PMU_CTRL_SLEEP_CTRL_CFG_FLL_CLUSTER_RET(x) (((uint32_t)(x) << PMU_CTRL_SLEEP_CTRL_CFG_FLL_CLUSTER_RET_SHIFT) & PMU_CTRL_SLEEP_CTRL_CFG_FLL_CLUSTER_RET_MASK) +#define READ_PMU_CTRL_SLEEP_CTRL_CFG_FLL_CLUSTER_RET(x) (((uint32_t)(x) & PMU_CTRL_SLEEP_CTRL_CFG_FLL_CLUSTER_RET_MASK) >> PMU_CTRL_SLEEP_CTRL_CFG_FLL_CLUSTER_RET_SHIFT) + +#define PMU_CTRL_SLEEP_CTRL_EXT_WAKE_SEL_MASK (0x7C0U) +#define PMU_CTRL_SLEEP_CTRL_EXT_WAKE_SEL_SHIFT (6U) +#define PMU_CTRL_SLEEP_CTRL_EXT_WAKE_SEL(x) (((uint32_t)(x) << PMU_CTRL_SLEEP_CTRL_EXT_WAKE_SEL_SHIFT) & PMU_CTRL_SLEEP_CTRL_EXT_WAKE_SEL_MASK) +#define READ_PMU_CTRL_SLEEP_CTRL_EXT_WAKE_SEL(x) (((uint32_t)(x) & PMU_CTRL_SLEEP_CTRL_EXT_WAKE_SEL_MASK) >> PMU_CTRL_SLEEP_CTRL_EXT_WAKE_SEL_SHIFT) + +#define PMU_CTRL_SLEEP_CTRL_EXT_WAKE_TYPE_MASK (0x1800U) +#define PMU_CTRL_SLEEP_CTRL_EXT_WAKE_TYPE_SHIFT (11U) +#define PMU_CTRL_SLEEP_CTRL_EXT_WAKE_TYPE(x) (((uint32_t)(x) << PMU_CTRL_SLEEP_CTRL_EXT_WAKE_TYPE_SHIFT) & PMU_CTRL_SLEEP_CTRL_EXT_WAKE_TYPE_MASK) +#define READ_PMU_CTRL_SLEEP_CTRL_EXT_WAKE_TYPE(x) (((uint32_t)(x) & PMU_CTRL_SLEEP_CTRL_EXT_WAKE_TYPE_MASK) >> PMU_CTRL_SLEEP_CTRL_EXT_WAKE_TYPE_SHIFT) + +#define PMU_CTRL_SLEEP_CTRL_EXT_WAKE_EN_MASK (0x2000U) +#define PMU_CTRL_SLEEP_CTRL_EXT_WAKE_EN_SHIFT (13U) +#define PMU_CTRL_SLEEP_CTRL_EXT_WAKE_EN(x) (((uint32_t)(x) << PMU_CTRL_SLEEP_CTRL_EXT_WAKE_EN_SHIFT) & PMU_CTRL_SLEEP_CTRL_EXT_WAKE_EN_MASK) +#define READ_PMU_CTRL_SLEEP_CTRL_EXT_WAKE_EN(x) (((uint32_t)(x) & PMU_CTRL_SLEEP_CTRL_EXT_WAKE_EN_MASK) >> PMU_CTRL_SLEEP_CTRL_EXT_WAKE_EN_SHIFT) + +#define PMU_CTRL_SLEEP_CTRL_WAKEUP_MASK (0xC000U) +#define PMU_CTRL_SLEEP_CTRL_WAKEUP_SHIFT (14U) +#define PMU_CTRL_SLEEP_CTRL_WAKEUP(x) (((uint32_t)(x) << PMU_CTRL_SLEEP_CTRL_WAKEUP_SHIFT) & PMU_CTRL_SLEEP_CTRL_WAKEUP_MASK) +#define READ_PMU_CTRL_SLEEP_CTRL_WAKEUP(x) (((uint32_t)(x) & PMU_CTRL_SLEEP_CTRL_WAKEUP_MASK) >> PMU_CTRL_SLEEP_CTRL_WAKEUP_SHIFT) + +#define PMU_CTRL_SLEEP_CTRL_BOOT_L2_MASK (0x10000U) +#define PMU_CTRL_SLEEP_CTRL_BOOT_L2_SHIFT (16U) +#define PMU_CTRL_SLEEP_CTRL_BOOT_L2(x) (((uint32_t)(x) << PMU_CTRL_SLEEP_CTRL_BOOT_L2_SHIFT) & PMU_CTRL_SLEEP_CTRL_BOOT_L2_MASK) +#define READ_PMU_CTRL_SLEEP_CTRL_BOOT_L2(x) (((uint32_t)(x) & PMU_CTRL_SLEEP_CTRL_BOOT_L2_MASK) >> PMU_CTRL_SLEEP_CTRL_BOOT_L2_SHIFT) + +#define PMU_CTRL_SLEEP_CTRL_REBOOT_MASK (0xC0000U) +#define PMU_CTRL_SLEEP_CTRL_REBOOT_SHIFT (18U) +#define PMU_CTRL_SLEEP_CTRL_REBOOT(x) (((uint32_t)(x) << PMU_CTRL_SLEEP_CTRL_REBOOT_SHIFT) & PMU_CTRL_SLEEP_CTRL_REBOOT_MASK) +#define READ_PMU_CTRL_SLEEP_CTRL_REBOOT(x) (((uint32_t)(x) & PMU_CTRL_SLEEP_CTRL_REBOOT_MASK) >> PMU_CTRL_SLEEP_CTRL_REBOOT_SHIFT) + +#define PMU_CTRL_SLEEP_CTRL_CLUSTER_WAKEUP_MASK (0x100000U) +#define PMU_CTRL_SLEEP_CTRL_CLUSTER_WAKEUP_SHIFT (20U) +#define PMU_CTRL_SLEEP_CTRL_CLUSTER_WAKEUP(x) (((uint32_t)(x) << PMU_CTRL_SLEEP_CTRL_CLUSTER_WAKEUP_SHIFT) & PMU_CTRL_SLEEP_CTRL_CLUSTER_WAKEUP_MASK) +#define READ_PMU_CTRL_SLEEP_CTRL_CLUSTER_WAKEUP(x) (((uint32_t)(x) & PMU_CTRL_SLEEP_CTRL_CLUSTER_WAKEUP_MASK) >> PMU_CTRL_SLEEP_CTRL_CLUSTER_WAKEUP_SHIFT) + +/* FORCE - PMU control register */ + +#define PMU_CTRL_FORCE_MEM_RET_MASK (0xFU) +#define PMU_CTRL_FORCE_MEM_RET_SHIFT (0U) +#define PMU_CTRL_FORCE_MEM_RET(x) (((uint32_t)(x) /* << PMU_CTRL_FORCE_MEM_RET_SHIFT*/) & PMU_CTRL_FORCE_MEM_RET_MASK) + +#define PMU_CTRL_FORCE_MEM_PWD_MASK (0xF0U) +#define PMU_CTRL_FORCE_MEM_PWD_SHIFT (4U) +#define PMU_CTRL_FORCE_MEM_PWD(x) (((uint32_t)(x) << PMU_CTRL_FORCE_MEM_PWD_SHIFT) & PMU_CTRL_FORCE_MEM_PWD_MASK) + +#define PMU_CTRL_FORCE_FLL_CLUSTER_RET_MASK (0x100U) +#define PMU_CTRL_FORCE_FLL_CLUSTER_RET_SHIFT (8U) +#define PMU_CTRL_FORCE_FLL_CLUSTER_RET(x) (((uint32_t)(x) << PMU_CTRL_FORCE_FLL_CLUSTER_RET_SHIFT) & PMU_CTRL_FORCE_FLL_CLUSTER_RET_MASK) + +#define PMU_CTRL_FORCE_FLL_CLUSTER_PWD_MASK (0x200U) +#define PMU_CTRL_FORCE_FLL_CLUSTER_PWD_SHIFT (9U) +#define PMU_CTRL_FORCE_FLL_CLUSTER_PWD(x) (((uint32_t)(x) << PMU_CTRL_FORCE_FLL_CLUSTER_PWD_SHIFT) & PMU_CTRL_FORCE_FLL_CLUSTER_PWD_MASK) + +/* PORT - Register Layout Typedef */ + +typedef struct +{ + volatile uint32_t PADFUN[4]; /* PORT pad function register 0 */ + volatile uint32_t SLEEP_PADCFG[4]; /* PORT sleep pad configuration register 0 */ + volatile uint32_t PAD_SLEEP; /* PORT pad sleep register */ + volatile uint32_t _reserved0[7]; /* reserved */ + volatile uint32_t PADCFG[16]; /* PORT pad configuration register 0 */ +} port_reg_t; + +#define PORTA_BASE (SOC_CTRL_BASE + 0x0140u) +#define PORTA ((port_reg_t *)PORTA_BASE) + +#define GPIO_NUM 32 + +#define PORT_PADCFG_PULL_EN_MASK (0x1U) +#define PORT_PADCFG_PULL_EN_SHIFT (0U) +#define PORT_PADCFG_PULL_EN(x) (((uint32_t)(x) << PORT_PADCFG_PULL_EN_SHIFT) & PORT_PADCFG_PULL_EN_MASK) + +#define PORT_PADCFG_DRIVE_STRENGTH_MASK (0x2U) +#define PORT_PADCFG_DRIVE_STRENGTH_SHIFT (1U) +#define PORT_PADCFG_DRIVE_STRENGTH(x) (((uint32_t)(x) << PORT_PADCFG_DRIVE_STRENGTH_SHIFT) & PORT_PADCFG_DRIVE_STRENGTH_MASK) + +#define PORT_PADFUN_MUX_MASK (0x3U) +#define PORT_PADFUN_MUX_SHIFT (0U) +#define PORT_PADFUN_MUX(x) (((uint32_t)(x) << PORT_PADFUN_MUX_SHIFT) & PORT_PADFUN_MUX_MASK) + +/* IO_ISO - Register Layout Typedef */ + +typedef struct +{ + volatile uint32_t GPIO_ISO; /* GPIO power domains isolation */ + volatile uint32_t CAM_ISO; /* Cemera power domains isolation */ + volatile uint32_t LVDS_ISO; /* LVDS power domains isolation */ +} io_iso_reg_t; + +#define IO_ISO_BASE (SOC_CTRL_BASE + 0x01C0u) +#define IO_ISO ((io_iso_reg_t *)IO_ISO_BASE) + +#define IO_ISO_GPIO_ISO_MASK (0x1U) +#define IO_ISO_GPIO_ISO_SHIFT (0U) +#define IO_ISO_GPIO_ISO(x) (((uint32_t)(x) /* << IO_ISO_GPIO_ISO_SHIFT */) & IO_ISO_GPIO_ISO_MASK) + +#define IO_ISO_CAM_ISO_MASK (0x1U) +#define IO_ISO_CAM_ISO_SHIFT (0U) +#define IO_ISO_CAM_ISO(x) (((uint32_t)(x) /* << IO_ISO_CAM_ISO_SHIFT */) & IO_ISO_CAM_ISO_MASK) + +#define IO_ISO_LVDS_ISO_MASK (0x1U) +#define IO_ISO_LVDS_ISO_SHIFT (0U) +#define IO_ISO_LVDS_ISO(x) (((uint32_t)(x) /* << IO_ISO_LVDS_ISO_SHIFT */) & IO_ISO_LVDS_ISO_MASK) + +/* PWM - Register Layout Typedef */ + +typedef struct +{ + volatile uint32_t EVENT_CFG; /* event configuration register */ + volatile uint32_t CH_EN; /* channel enable register */ +} pwm_ctrl_reg_t; + +#define PWM_CTRL_BASE (SOC_PERI_BASE + 0x05100u) +#define PWM_CTRL ((pwm_ctrl_reg_t *)PWM_CTRL_BASE) + +/* Set Event. */ + +#define PWM_CTRL_EVENT_TIMER_CHAN_SET_MASK (0xFFFFU) +#define PWM_CTRL_EVENT_TIMER_CHAN_SET_SHIFT(x) ((uint32_t)(x)) +#define PWM_CTRL_EVENT_TIMER_CHAN_SET(tim, chan, evt) (((uint32_t)((uint32_t)tim << 2 | (uint32_t)chan) << PWM_CTRL_EVENT_TIMER_CHAN_SET_SHIFT(evt << 2)) & PWM_CTRL_EVENT_TIMER_CHAN_SET_MASK) + +/* Enable Event. */ + +#define PWM_CTRL_EVENT_TIMER_ENA_MASK (0xF0000U) +#define PWM_CTRL_EVENT_TIMER_ENA_SHIFT (16) +#define PWM_CTRL_EVENT_TIMER_ENA(x) (((uint32_t)(x) << PWM_CTRL_EVENT_TIMER_ENA_SHIFT) & PWM_CTRL_EVENT_TIMER_ENA_MASK) + +/* Timer enable. */ + +#define PWM_CTRL_CG_ENA_MASK (0xFU) +#define PWM_CTRL_CG_ENA_SHIFT (0) +#define PWM_CTRL_CG_ENA(x) (((uint32_t)(x) << PWM_CTRL_CG_ENA_SHIFT) & PWM_CTRL_CG_ENA_MASK) + +/* ADV_TIMER - Register Layout Typedef */ + +typedef struct +{ + volatile uint32_t CMD; /* control register */ + volatile uint32_t CFG; /* configuration register */ + volatile uint32_t TH; /* threshold register */ + volatile uint32_t CH_TH[4]; /* Channles' threshold register */ + volatile uint32_t CH_LUT[4]; /* Channles' LUT register */ + volatile uint32_t COUNTER; /* Counter register */ +} pwm_reg_t; + +#define PWM0_BASE (SOC_PERI_BASE + 0x05000u) +#define PWM0 ((pwm_reg_t *)PWM0_BASE) +#define PWM1_BASE (PWM0_BASE + 0x40u) +#define PWM1 ((pwm_reg_t *)PWM1_BASE) +#define PWM2_BASE (PWM1_BASE + 0x40u) +#define PWM2 ((pwm_reg_t *)PWM2_BASE) +#define PWM3_BASE (PWM2_BASE + 0x40u) +#define PWM3 ((pwm_reg_t *)PWM3_BASE) + +/* Send command. */ + +#define PWM_CMD_MASK (0x1FU) +#define PWM_CMD_SHIFT (0) +#define PWM_CMD(x) (((uint32_t)(x) << PWM_CMD_SHIFT) & PWM_CMD_MASK) + +/* Timer config. */ + +#define PWM_CONFIG_INPUT_SRC_MASK (0xFFU) +#define PWM_CONFIG_INPUT_SRC_SHIFT (0) +#define PWM_CONFIG_INPUT_SRC(x) (((uint32_t)(x) << PWM_CONFIG_INPUT_SRC_SHIFT) & PWM_CONFIG_INPUT_SRC_MASK) + +#define PWM_CONFIG_INPUT_MODE_MASK (0x700U) +#define PWM_CONFIG_INPUT_MODE_SHIFT (8) +#define PWM_CONFIG_INPUT_MODE(x) (((uint32_t)(x) << PWM_CONFIG_INPUT_MODE_SHIFT) & PWM_CONFIG_INPUT_MODE_MASK) + +#define PWM_CONFIG_CLKSEL_MASK (0x800U) +#define PWM_CONFIG_CLKSEL_SHIFT (11) +#define PWM_CONFIG_CLKSEL(x) (((uint32_t)(x) << PWM_CONFIG_CLKSEL_SHIFT) & PWM_CONFIG_CLKSEL_MASK) + +#define PWM_CONFIG_UPDOWNSEL_MASK (0x1000U) +#define PWM_CONFIG_UPDOWNSEL_SHIFT (12) +#define PWM_CONFIG_UPDOWNSEL(x) (((uint32_t)(x) << PWM_CONFIG_UPDOWNSEL_SHIFT) & PWM_CONFIG_UPDOWNSEL_MASK) + +#define PWM_CONFIG_PRESCALE_MASK (0xFF0000U) +#define PWM_CONFIG_PRESCALE_SHIFT (16) +#define PWM_CONFIG_PRESCALE(x) (((uint32_t)(x) << PWM_CONFIG_PRESCALE_SHIFT) & PWM_CONFIG_PRESCALE_MASK) + +/* Channel config. */ + +#define PWM_THRESHOLD_LOW_MASK (0xFFFFU) +#define PWM_THRESHOLD_LOW_SHIFT (0) +#define PWM_THRESHOLD_LOW(x) (((uint32_t)(x) << PWM_THRESHOLD_LOW_SHIFT) & PWM_THRESHOLD_LOW_MASK) + +#define PWM_THRESHOLD_HIGH_MASK (0xFFFF0000U) +#define PWM_THRESHOLD_HIGH_SHIFT (16) +#define PWM_THRESHOLD_HIGH(x) (((uint32_t)(x) << PWM_THRESHOLD_HIGH_SHIFT) & PWM_THRESHOLD_HIGH_MASK) + +/* Channel config. */ + +#define PWM_CHANNEL_CONFIG_THRESHOLD_MASK (0xFFFFU) +#define PWM_CHANNEL_CONFIG_THRESHOLD_SHIFT (0) +#define PWM_CHANNEL_CONFIG_THRESHOLD(x) (((uint32_t)(x) << PWM_CHANNEL_CONFIG_THRESHOLD_SHIFT) & PWM_CHANNEL_CONFIG_THRESHOLD_MASK) + +#define PWM_CHANNEL_CONFIG_MODE_MASK (0x70000U) +#define PWM_CHANNEL_CONFIG_MODE_SHIFT (16) +#define PWM_CHANNEL_CONFIG_MODE(x) (((uint32_t)(x) << PWM_CHANNEL_CONFIG_MODE_SHIFT) & PWM_CHANNEL_CONFIG_MODE_MASK) + +/* SOCEU - Register Layout Typedef */ + +typedef struct +{ + volatile uint32_t EVENT; /* event register */ + volatile uint32_t FC_MASK_MSB; /* fc mask MSB register */ + volatile uint32_t FC_MASK_LSB; /* fc mask LSB register */ + volatile uint32_t CL_MASK_MSB; /* cluster mask MSB register */ + volatile uint32_t CL_MASK_LSB; /* cluster mask LSB register */ + volatile uint32_t PR_MASK_MSB; /* propagate mask MSB register */ + volatile uint32_t PR_MASK_LSB; /* propagate mask LSB register */ + volatile uint32_t ERR_MASK_MSB; /* error mask MSB register */ + volatile uint32_t ERR_MASK_LSB; /* error mask LSB register */ + volatile uint32_t TIMER_SEL_HI; /* timer high register */ + volatile uint32_t TIMER_SEL_LO; /* timer low register */ +} soceu_reg_t; + +#define SOCEU_BASE (SOC_PERI_BASE + 0x06000u) +#define SOCEU ((soceu_reg_t *)SOCEU_BASE) + +/* The SOC events number */ + +#define SOC_EVENTS_NUM 0x08 +#define EU_EVT_GETCLUSTERBASE(coreId) (0x00200800u + (coreId << 6)) + +/* PMU - General Register Layout Typedef */ + +typedef struct +{ + volatile uint32_t PCTRL; /* PMU DLC control register */ + volatile uint32_t PRDATA; /* PMU DLC data register */ + volatile uint32_t DLC_SR; /* PMU DLC register */ + volatile uint32_t DLC_IMR; /* PMU DLC register */ + volatile uint32_t DLC_IFR; /* PMU DLC register */ + volatile uint32_t DLC_IOIFR; /* PMU DLC register */ + volatile uint32_t DLC_IDIFR; /* PMU DLC register */ + volatile uint32_t DLC_IMCIFR; /* PMU DLC register */ +} pmu_dlc_reg_t; + +#define PMU_DLC_BASE (SOC_PERI_BASE + 0x7000u) +#define PMU_DLC ((pmu_dlc_reg_t *)PMU_DLC_BASE) + +/* PCTRL - PMU DLC PICL control register */ + +#define PMU_DLC_PCTRL_START_MASK (0x1U) +#define PMU_DLC_PCTRL_START_SHIFT (0U) +#define PMU_DLC_PCTRL_START(x) (((uint32_t)(x) /* << PMU_DLC_PCTRL_START_SHIFT */) & PMU_DLC_PCTRL_START_MASK) +#define PMU_DLC_PCTRL_PADDR_MASK (0x7FFEU) +#define PMU_DLC_PCTRL_PADDR_SHIFT (1U) +#define PMU_DLC_PCTRL_PADDR(x) (((uint32_t)(x) << PMU_DLC_PCTRL_PADDR_SHIFT) & PMU_DLC_PCTRL_PADDR_MASK) +#define PMU_DLC_PCTRL_DIR_MASK (0x8000U) +#define PMU_DLC_PCTRL_DIR_SHIFT (15U) +#define PMU_DLC_PCTRL_DIR(x) (((uint32_t)(x) << PMU_DLC_PCTRL_DIR_SHIFT) & PMU_DLC_PCTRL_DIR_MASK) +#define PMU_DLC_PCTRL_PWDATA_MASK (0xFFFF0000U) +#define PMU_DLC_PCTRL_PWDATA_SHIFT (16U) +#define PMU_DLC_PCTRL_PWDATA(x) (((uint32_t)(x) << PMU_DLC_PCTRL_PWDATA_SHIFT) & PMU_DLC_PCTRL_PWDATA_MASK) + +/* PRDATA - PMU DLC PICL data read register */ + +#define PMU_DLC_PRDATA_PRDATA_MASK (0xFFU) +#define PMU_DLC_PRDATA_PRDATA_SHIFT (0U) +#define PMU_DLC_PRDATA_PRDATA(x) (((uint32_t)(x) /* << PMU_DLC_PRDATA_PRDATA_SHIFT */) & PMU_DLC_PRDATA_PRDATA_MASK) + +/* SR - PMU DLC DLC Status register */ + +#define PMU_DLC_SR_PICL_BUSY_MASK (0x1U) +#define PMU_DLC_SR_PICL_BUSY_SHIFT (0U) +#define PMU_DLC_SR_PICL_BUSY(x) (((uint32_t)(x) /* << PMU_DLC_SR_PICL_BUSY_SHIFT */) & PMU_DLC_SR_PICL_BUSY_MASK) +#define PMU_DLC_SR_SCU_BUSY_MASK (0x2U) +#define PMU_DLC_SR_SCU_BUSY_SHIFT (1U) +#define PMU_DLC_SR_SCU_BUSY(x) (((uint32_t)(x) << PMU_DLC_SR_SCU_BUSY_SHIFT) & PMU_DLC_SR_SCU_BUSY_MASK) + +/* IMR - PMU DLC Interrupt mask register */ + +#define PMU_DLC_IMR_ICU_OK_MASK_MASK (0x1U) +#define PMU_DLC_IMR_ICU_OK_MASK_SHIFT (0U) +#define PMU_DLC_IMR_ICU_OK_MASK(x) (((uint32_t)(x) /* << PMU_DLC_IMR_ICU_OK_MASK_SHIFT */) & PMU_DLC_IMR_ICU_OK_MASK_MASK) +#define PMU_DLC_IMR_ICU_DELAYED_MASK_MASK (0x2U) +#define PMU_DLC_IMR_ICU_DELAYED_MASK_SHIFT (1U) +#define PMU_DLC_IMR_ICU_DELAYED_MASK(x) (((uint32_t)(x) << PMU_DLC_IMR_ICU_DELAYED_MASK_SHIFT) & PMU_DLC_IMR_ICU_DELAYED_MASK_MASK) +#define PMU_DLC_IMR_ICU_MODE_CHANGED_MASK_MASK (0x4U) +#define PMU_DLC_IMR_ICU_MODE_CHANGED_MASK_SHIFT (2U) +#define PMU_DLC_IMR_ICU_MODE_CHANGED_MASK(x) (((uint32_t)(x) << PMU_DLC_IMR_ICU_MODE_CHANGED_MASK_SHIFT) & PMU_DLC_IMR_ICU_MODE_CHANGED_MASK_MASK) +#define PMU_DLC_IMR_PICL_OK_MASK_MASK (0x8U) +#define PMU_DLC_IMR_PICL_OK_MASK_SHIFT (3U) +#define PMU_DLC_IMR_PICL_OK_MASK(x) (((uint32_t)(x) << PMU_DLC_IMR_PICL_OK_MASK_SHIFT) & PMU_DLC_IMR_PICL_OK_MASK_MASK) +#define PMU_DLC_IMR_SCU_OK_MASK_MASK (0x10U) +#define PMU_DLC_IMR_SCU_OK_MASK_SHIFT (4U) +#define PMU_DLC_IMR_SCU_OK_MASK(x) (((uint32_t)(x) << PMU_DLC_IMR_SCU_OK_MASK_SHIFT) & PMU_DLC_IMR_SCU_OK_MASK_MASK) + +/* IFR - PMU DLC Interrupt flag register */ + +#define PMU_DLC_IFR_ICU_OK_FLAG_MASK (0x1U) +#define PMU_DLC_IFR_ICU_OK_FLAG_SHIFT (0U) +#define PMU_DLC_IFR_ICU_OK_FLAG(x) (((uint32_t)(x) /* << PMU_DLC_IFR_ICU_OK_FLAG_SHIFT */) & PMU_DLC_IFR_ICU_OK_FLAG_MASK) +#define PMU_DLC_IFR_ICU_DELAYED_FLAG_MASK (0x2U) +#define PMU_DLC_IFR_ICU_DELAYED_FLAG_SHIFT (1U) +#define PMU_DLC_IFR_ICU_DELAYED_FLAG(x) (((uint32_t)(x) << PMU_DLC_IFR_ICU_DELAYED_FLAG_SHIFT) & PMU_DLC_IFR_ICU_DELAYED_FLAG_MASK) +#define PMU_DLC_IFR_ICU_MODE_CHANGED_FLAG_MASK (0x4U) +#define PMU_DLC_IFR_ICU_MODE_CHANGED_FLAG_SHIFT (2U) +#define PMU_DLC_IFR_ICU_MODE_CHANGED_FLAG(x) (((uint32_t)(x) << PMU_DLC_IFR_ICU_MODE_CHANGED_FLAG_SHIFT) & PMU_DLC_IFR_ICU_MODE_CHANGED_FLAG_MASK) +#define PMU_DLC_IFR_PICL_OK_FLAG_MASK (0x8U) +#define PMU_DLC_IFR_PICL_OK_FLAG_SHIFT (3U) +#define PMU_DLC_IFR_PICL_OK_FLAG(x) (((uint32_t)(x) << PMU_DLC_IFR_PICL_OK_FLAG_SHIFT) & PMU_DLC_IFR_PICL_OK_FLAG_MASK) +#define PMU_DLC_IFR_SCU_OK_FLAG_MASK (0x10U) +#define PMU_DLC_IFR_SCU_OK_FLAG_SHIFT (4U) +#define PMU_DLC_IFR_SCU_OK_FLAG(x) (((uint32_t)(x) << PMU_DLC_IFR_SCU_OK_FLAG_SHIFT) & PMU_DLC_IFR_SCU_OK_FLAG_MASK) + +/* IOIFR - PMU DLC icu_ok interrupt flag register */ + +#define PMU_DLC_IOIFR_ICU_OK_FLAG_MASK (0xFFFFFFFEU) +#define PMU_DLC_IOIFR_ICU_OK_FLAG_SHIFT (1U) +#define PMU_DLC_IOIFR_ICU_OK_FLAG(x) (((uint32_t)(x) << PMU_DLC_IOIFR_ICU_OK_FLAG_SHIFT) & PMU_DLC_IOIFR_ICU_OK_FLAG_MASK) + +/* IDIFR - PMU DLC icu_delayed interrupt flag register */ + +#define PMU_DLC_IDIFR_ICU_DELAYED_FLAG_MASK (0xFFFFFFFEU) +#define PMU_DLC_IDIFR_ICU_DELAYED_FLAG_SHIFT (1U) +#define PMU_DLC_IDIFR_ICU_DELAYED_FLAG(x) (((uint32_t)(x) << PMU_DLC_IDIFR_ICU_DELAYED_FLAG_SHIFT) & PMU_DLC_IDIFR_ICU_DELAYED_FLAG_MASK) + +/* IMCIFR - PMU DLC icu_mode changed interrupt flag register */ + +#define PMU_DLC_IMCIFR_ICU_MODE_CHANGED_FLAG_MASK (0xFFFFFFFEU) +#define PMU_DLC_IMCIFR_ICU_MODE_CHANGED_FLAG_SHIFT (1U) +#define PMU_DLC_IMCIFR_ICU_MODE_CHANGED_FLAG(x) (((uint32_t)(x) << PMU_DLC_IMCIFR_ICU_MODE_CHANGED_FLAG_SHIFT) & PMU_DLC_IMCIFR_ICU_MODE_CHANGED_FLAG_MASK) + +/* PCTRL_PADDR The address to write in the DLC_PADDR register is + * CHIP_SEL_ADDR[4:0] concatenated with REG_ADDR[4:0]. + */ + +#define PMU_DLC_PICL_REG_ADDR_MASK (0x1FU) +#define PMU_DLC_PICL_REG_ADDR_SHIFT (0U) +#define PMU_DLC_PICL_REG_ADDR(x) (((uint32_t)(x) /* << PMU_DLC_PICL_REG_ADDR_SHIFT */) & PMU_DLC_PICL_REG_ADDR_MASK) +#define PMU_DLC_PICL_CHIP_SEL_ADDR_MASK (0x3E0U) +#define PMU_DLC_PICL_CHIP_SEL_ADDR_SHIFT (5U) +#define PMU_DLC_PICL_CHIP_SEL_ADDR(x) (((uint32_t)(x) << PMU_DLC_PICL_CHIP_SEL_ADDR_SHIFT) & PMU_DLC_PICL_CHIP_SEL_ADDR_MASK) + +/* CHIP_SEL_ADDR[4:0] */ + +#define PICL_WIU_ADDR 0x00 +#define PICL_ICU_ADDR 0x01 + +/* REG_ADDR[4:0] */ + +#define WIU_ISPMR_0 (PMU_DLC_PICL_CHIP_SEL_ADDR(PICL_WIU_ADDR) | PMU_DLC_PICL_REG_ADDR(0x00)) +#define WIU_ISPMR_1 (PMU_DLC_PICL_CHIP_SEL_ADDR(PICL_WIU_ADDR) | PMU_DLC_PICL_REG_ADDR(0x01)) +#define WIU_IFR_0 (PMU_DLC_PICL_CHIP_SEL_ADDR(PICL_WIU_ADDR) | PMU_DLC_PICL_REG_ADDR(0x02)) +#define WIU_IFR_1 (PMU_DLC_PICL_CHIP_SEL_ADDR(PICL_WIU_ADDR) | PMU_DLC_PICL_REG_ADDR(0x03)) +#define WIU_ICR_0 (PMU_DLC_PICL_CHIP_SEL_ADDR(PICL_WIU_ADDR) | PMU_DLC_PICL_REG_ADDR(0x04)) +#define WIU_ICR_1 (PMU_DLC_PICL_CHIP_SEL_ADDR(PICL_WIU_ADDR) | PMU_DLC_PICL_REG_ADDR(0x05)) +#define WIU_ICR_2 (PMU_DLC_PICL_CHIP_SEL_ADDR(PICL_WIU_ADDR) | PMU_DLC_PICL_REG_ADDR(0x06)) +#define WIU_ICR_3 (PMU_DLC_PICL_CHIP_SEL_ADDR(PICL_WIU_ADDR) | PMU_DLC_PICL_REG_ADDR(0x07)) +#define WIU_ICR_4 (PMU_DLC_PICL_CHIP_SEL_ADDR(PICL_WIU_ADDR) | PMU_DLC_PICL_REG_ADDR(0x08)) +#define WIU_ICR_5 (PMU_DLC_PICL_CHIP_SEL_ADDR(PICL_WIU_ADDR) | PMU_DLC_PICL_REG_ADDR(0x09)) +#define WIU_ICR_6 (PMU_DLC_PICL_CHIP_SEL_ADDR(PICL_WIU_ADDR) | PMU_DLC_PICL_REG_ADDR(0x0A)) +#define WIU_ICR_7 (PMU_DLC_PICL_CHIP_SEL_ADDR(PICL_WIU_ADDR) | PMU_DLC_PICL_REG_ADDR(0x0B)) +#define WIU_ICR_8 (PMU_DLC_PICL_CHIP_SEL_ADDR(PICL_WIU_ADDR) | PMU_DLC_PICL_REG_ADDR(0x0C)) +#define WIU_ICR_9 (PMU_DLC_PICL_CHIP_SEL_ADDR(PICL_WIU_ADDR) | PMU_DLC_PICL_REG_ADDR(0x0D)) +#define WIU_ICR_10 (PMU_DLC_PICL_CHIP_SEL_ADDR(PICL_WIU_ADDR) | PMU_DLC_PICL_REG_ADDR(0x0E)) +#define WIU_ICR_11 (PMU_DLC_PICL_CHIP_SEL_ADDR(PICL_WIU_ADDR) | PMU_DLC_PICL_REG_ADDR(0x0F)) +#define WIU_ICR_12 (PMU_DLC_PICL_CHIP_SEL_ADDR(PICL_WIU_ADDR) | PMU_DLC_PICL_REG_ADDR(0x10)) +#define WIU_ICR_13 (PMU_DLC_PICL_CHIP_SEL_ADDR(PICL_WIU_ADDR) | PMU_DLC_PICL_REG_ADDR(0x11)) +#define WIU_ICR_14 (PMU_DLC_PICL_CHIP_SEL_ADDR(PICL_WIU_ADDR) | PMU_DLC_PICL_REG_ADDR(0x12)) +#define WIU_ICR_15 (PMU_DLC_PICL_CHIP_SEL_ADDR(PICL_WIU_ADDR) | PMU_DLC_PICL_REG_ADDR(0x13)) + +/* REG_ADDR[4:0] */ + +#define ICU_CR (PMU_DLC_PICL_CHIP_SEL_ADDR(PICL_ICU_ADDR) | PMU_DLC_PICL_REG_ADDR(0x00)) +#define ICU_MR (PMU_DLC_PICL_CHIP_SEL_ADDR(PICL_ICU_ADDR) | PMU_DLC_PICL_REG_ADDR(0x01)) +#define ICU_ISMR (PMU_DLC_PICL_CHIP_SEL_ADDR(PICL_ICU_ADDR) | PMU_DLC_PICL_REG_ADDR(0x02)) +#define ICU_DMR_0 (PMU_DLC_PICL_CHIP_SEL_ADDR(PICL_ICU_ADDR) | PMU_DLC_PICL_REG_ADDR(0x03)) +#define ICU_DMA_1 (PMU_DLC_PICL_CHIP_SEL_ADDR(PICL_ICU_ADDR) | PMU_DLC_PICL_REG_ADDR(0x04)) + +/* RTC_APB - Register Layout Typedef */ + +typedef struct +{ + volatile uint32_t STATUS; /* RTC_APB_Status register */ + volatile uint32_t REQUEST; /* RTC_APB_Request register */ + volatile uint32_t DATA; /* RTC_APB_Data register */ + volatile uint32_t _reserved; /* reserved */ + volatile uint32_t IRQ_CTRL; /* RTC_APB_IRQ_Control register */ + volatile uint32_t IRQ_MASK; /* RTC_APB_IRQ_Mask register */ + volatile uint32_t IRQ_FLAG; /* RTC_APB_IRQ_Flag register */ +} rtc_apb_reg_t; + +#define RTC_APB_BASE (SOC_PERI_BASE + 0x08000u) +#define RTC_APB ((rtc_apb_reg_t *)RTC_APB_BASE) + +/* STATUS - RTC_APB STATUS register */ + +#define RTC_APB_STATUS_IRQ_EN_MASK (0x3FU) +#define RTC_APB_STATUS_IRQ_EN_SHIFT (0U) +#define RTC_APB_STATUS_IRQ_EN(x) (((uint32_t)(x)/* << RTC_APB_STATUS_IRQ_EN_SHIFT*/) & RTC_APB_STATUS_IRQ_EN_MASK) + +/* REQUEST - RTC_APB REQUEST Access register */ + +#define RTC_APB_REQUEST_ACCESS_ADDR_MASK (0x3FU) +#define RTC_APB_REQUEST_ACCESS_ADDR_SHIFT (0U) +#define RTC_APB_REQUEST_ACCESS_ADDR(x) (((uint32_t)(x)/* << RTC_APB_REQUEST_ACCESS_ADDR_SHIFT*/) & RTC_APB_REQUEST_ACCESS_ADDR_MASK) +#define RTC_APB_REQUEST_ACCESS_RW_MASK (0x10000U) +#define RTC_APB_REQUEST_ACCESS_RW_SHIFT (16U) +#define RTC_APB_REQUEST_ACCESS_RW(x) (((uint32_t)(x) << RTC_APB_REQUEST_ACCESS_RW_SHIFT) & RTC_APB_REQUEST_ACCESS_RW_MASK) + +/* IRQ_FLAG - RTC_APB IRQ_FLAG Access register */ + +#define RTC_APB_IRQ_FLAG_READ_MASK (0x1U) +#define RTC_APB_IRQ_FLAG_READ_SHIFT (0U) +#define RTC_APB_IRQ_FLAG_READ(x) (((uint32_t)(x)/* << RTC_APB_IRQ_FLAG_READ_SHIFT*/) & RTC_APB_IRQ_FLAG_READ_MASK) +#define RTC_APB_IRQ_FLAG_WRITE_MASK (0x2U) +#define RTC_APB_IRQ_FLAG_WRITE_SHIFT (1U) +#define RTC_APB_IRQ_FLAG_WRITE(x) (((uint32_t)(x) << RTC_APB_IRQ_FLAG_WRITE_SHIFT) & RTC_APB_IRQ_FLAG_WRITE_MASK) + +/* Bit field of RTC indirect Access Register */ + +#define RTC_STATUS_ADDR 0x00 +#define RTC_CTRL_ADDR 0x01 +#define RTC_CLK_CTRL_ADDR 0x02 +#define RTC_IRQ_CTRL_ADDR 0x08 +#define RTC_IRQ_MASK_ADDR 0x09 +#define RTC_IRQ_FLAG_ADDR 0x0A +#define RTC_CALENDAR_CTRL_ADDR 0x10 +#define RTC_CALENDAR_TIME_ADDR 0x12 +#define RTC_CALENDAR_DATE_ADDR 0x13 +#define RTC_ALARM_CTRL_ADDR 0x18 +#define RTC_ALARM_TIME_ADDR 0x1A +#define RTC_ALARM_DATE_ADDR 0x1B +#define RTC_TIMER_CTRL_ADDR 0x20 +#define RTC_TIMER_INIT_ADDR 0x21 +#define RTC_TIMER_VALUE_ADDR 0x22 +#define RTC_CLKIN_DIV_ADDR 0x28 +#define RTC_REF_CLK_CONF_ADDR 0x2A +#define RTC_TEST_ADDR 0x30 + +/* SR - RTC Status register */ + +#define RTC_SR_INT_RTC_MASK (0x1U) +#define RTC_SR_INT_RTC_SHIFT (0U) +#define RTC_SR_INT_RTC(x) (((uint32_t)(x)/* << RTC_SR_INT_RTC_SHIFT*/) & RTC_SR_INT_RTC_MASK) + +/* CR - RTC Control register */ + +#define RTC_CR_STANDBY_MASK (0x1U) +#define RTC_CR_STANDBY_SHIFT (0U) +#define RTC_CR_STANDBY(x) (((uint32_t)(x)/* << RTC_CR_STANDBY_SHIFT*/) & RTC_CR_STANDBY_MASK) +#define RTC_CR_CALIBRATION_EN_MASK (0x10U) +#define RTC_CR_CALIBRATION_EN_SHIFT (4U) +#define RTC_CR_CALIBRATION_EN(x) (((uint32_t)(x) << RTC_CR_CALIBRATION_EN_SHIFT) & RTC_CR_CALIBRATION_EN_MASK) +#define RTC_CR_SOFT_RST_MASK (0x100U) +#define RTC_CR_SOFT_RST_SHIFT (8U) +#define RTC_CR_SOFT_RST(x) (((uint32_t)(x) << RTC_CR_SOFT_RST_SHIFT) & RTC_CR_SOFT_RST_MASK) + +/* CCR - RTC Clock Control register */ + +#define RTC_CCR_CKOUT_STANDBY_MASK (0x1U) +#define RTC_CCR_CKOUT_STANDBY_SHIFT (0U) +#define RTC_CCR_CKOUT_STANDBY(x) (((uint32_t)(x)/* << RTC_CCR_CKOUT_STANDBY_SHIFT*/) & RTC_CCR_CKOUT_STANDBY_MASK) +#define RTC_CCR_DIV_AUTOCAL_MASK (0x1000U) +#define RTC_CCR_DIV_AUTOCAL_SHIFT (12U) +#define RTC_CCR_DIV_AUTOCAL(x) (((uint32_t)(x) << RTC_CCR_DIV_AUTOCAL_SHIFT) & RTC_CCR_DIV_AUTOCAL_MASK) +#define RTC_CCR_DIV_COMP_MASK (0x1F0000U) +#define RTC_CCR_DIV_COMP_SHIFT (16U) +#define RTC_CCR_DIV_COMP(x) (((uint32_t)(x) << RTC_CCR_DIV_COMP_SHIFT) & RTC_CCR_DIV_COMP_MASK) + +/* ICR - RTC IRQ Control register + * + * 00 INT_RTC high; + * 01 INT_RTC low; + * 10; INT_RTC high pulse with duration of 1 CKIN cycle + * 11; INT_RTC low pulse with duration of 1 CKIN cycle + */ + +#define RTC_ICR_FORM_MASK (0x3U) +#define RTC_ICR_FORM_SHIFT (0U) +#define RTC_ICR_FORM(x) (((uint32_t)(x)/* << RTC_ICR_FORM_SHIFT*/) & RTC_ICR_FORM_MASK) + +/* IMR - RTC IRQ MASK register */ + +#define RTC_IMR_ALARM_MASK (0x1U) +#define RTC_IMR_ALARM_SHIFT (0U) +#define RTC_IMR_ALARM(x) (((uint32_t)(x)/* << RTC_IMR_ALARM_SHIFT*/) & RTC_IMR_ALARM_MASK) +#define RTC_IMR_TIMER_MASK (0x10U) +#define RTC_IMR_TIMER_SHIFT (4U) +#define RTC_IMR_TIMER(x) (((uint32_t)(x) << RTC_IMR_TIMER_SHIFT) & RTC_IMR_TIMER_MASK) +#define RTC_IMR_CALIBRATION_MASK (0x1000U) +#define RTC_IMR_CALIBRATION_SHIFT (12U) +#define RTC_IMR_CALIBRATION(x) (((uint32_t)(x) << RTC_IMR_CALIBRATION_SHIFT) & RTC_IMR_CALIBRATION_MASK) + +/* IFR - RTC IRQ Flag register */ + +#define RTC_IFR_ALARM_MASK (0x1U) +#define RTC_IFR_ALARM_SHIFT (0U) +#define RTC_IFR_ALARM(x) (((uint32_t)(x)/* << RTC_IFR_ALARM_SHIFT*/) & RTC_IFR_ALARM_MASK) +#define RTC_IFR_TIMER_MASK (0x10U) +#define RTC_IFR_TIMER_SHIFT (4U) +#define RTC_IFR_TIMER(x) (((uint32_t)(x) << RTC_IFR_TIMER_SHIFT) & RTC_IFR_TIMER_MASK) +#define RTC_IFR_CALIBRATION_MASK (0x1000U) +#define RTC_IFR_CALIBRATION_SHIFT (12U) +#define RTC_IFR_CALIBRATION(x) (((uint32_t)(x) << RTC_IFR_CALIBRATION_SHIFT) & RTC_IFR_CALIBRATION_MASK) + +/* CALENDAR CTRL - RTC CALENDAR Control register */ + +#define RTC_CALENDAR_CTRL_STANDBY_MASK (0x1U) +#define RTC_CALENDAR_CTRL_STANDBY_SHIFT (0U) +#define RTC_CALENDAR_CTRL_STANDBY(x) (((uint32_t)(x)/* << RTC_CALENDAR_CTRL_STANDBY_SHIFT*/) & RTC_CALENDAR_CTRL_STANDBY_MASK) + +/* ALARM_CTRL - RTC Alarm control register */ + +#define RTC_ALARM_CTRL_STANDBY_MASK (0x1U) +#define RTC_ALARM_CTRL_STANDBY_SHIFT (0U) +#define RTC_ALARM_CTRL_STANDBY(x) (((uint32_t)(x)/* << RTC_ALARM_CTRL_STANDBY_SHIFT*/) & RTC_ALARM_CTRL_STANDBY_MASK) +#define RTC_ALARM_CTRL_MODE_MASK (0x10U) +#define RTC_ALARM_CTRL_MODE_SHIFT (4U) +#define RTC_ALARM_CTRL_MODE(x) (((uint32_t)(x) << RTC_ALARM_CTRL_MODE_SHIFT) & RTC_ALARM_CTRL_MODE_MASK) +#define RTC_ALARM_CTRL_CONFIG_MASK (0xF0000U) +#define RTC_ALARM_CTRL_CONFIG_SHIFT (16U) +#define RTC_ALARM_CTRL_CONFIG(x) (((uint32_t)(x) << RTC_ALARM_CTRL_CONFIG_SHIFT) & RTC_ALARM_CTRL_CONFIG_MASK) + +/* TIMER - RTC Count down register */ + +#define RTC_TIMER_STANDBY_MASK (0x1U) +#define RTC_TIMER_STANDBY_SHIFT (0U) +#define RTC_TIMER_STANDBY(x) (((uint32_t)(x)/* << RTC_TIMER_STANDBY_SHIFT*/) & RTC_TIMER_STANDBY_MASK) +#define RTC_TIMER_MODE_MASK (0x10U) +#define RTC_TIMER_MODE_SHIFT (4U) +#define RTC_TIMER_MODE(x) (((uint32_t)(x) << RTC_TIMER_MODE_SHIFT) & RTC_TIMER_MODE_MASK) + +/* CLKIN_DIV - RTC Clock in divider register */ + +#define RTC_CLKIN_DIV_VAL_MASK (0xFFFFU) +#define RTC_CLKIN_DIV_VAL_SHIFT (0U) +#define RTC_CLKIN_DIV_VAL(x) (((uint32_t)(x)/* << RTC_CLKIN_DIV_VAL_SHIFT*/) & RTC_CLKIN_DIV_VAL_MASK) + +/* CKREF_CONF - RTC Reference Clock configuration */ + +#define RTC_CKREF_CONF_VAL_MASK (0x3FFFFFU) +#define RTC_CKREF_CONF_VAL_SHIFT (0U) +#define RTC_CKREF_CONF_VAL(x) (((uint32_t)(x)/* << RTC_CKREF_CONF_VAL_SHIFT*/) & RTC_CKREF_CONF_VAL_MASK) + +/* EFUSE_CTRL - Register Layout Typedef */ + +typedef struct +{ + volatile uint32_t CMD; /* EFUSE_Control register */ + volatile uint32_t CFG; /* EFUSE_Control register */ +} efuse_ctrl_reg_t; + +#define EFUSE_CTRL_BASE (SOC_PERI_BASE + 0x09000u) +#define EFUSE_CTRL ((efuse_ctrl_reg_t *)EFUSE_CTRL_BASE) + +#define EFUSE_CTRL_CMD_READ 0x1 +#define EFUSE_CTRL_CMD_WRITE 0x2 +#define EFUSE_CTRL_CMD_SLEEP 0x4 + +/* EFUSE_REGS - Registers Layout Typedef */ + +typedef struct +{ + volatile uint32_t INFO; /**< EFUSE INFO register, offset: 0x000 */ + volatile uint32_t INFO2; /**< EFUSE_INFO2 register, offset: 0x004 */ + volatile uint32_t AES_KEY[16]; /**< EFUSE_AES_KEY registers, offset: 0x008 */ + volatile uint32_t AES_IV[8]; /**< EFUSE_AES_IV registers, offset: 0x048 */ + volatile uint32_t WAIT_XTAL_DELTA_LSB; /**< EFUSE_WAIT_XTAL_DELTA_LSB register, offset: 0x068 */ + volatile uint32_t WAIT_XTAL_DELTA_MSB; /**< EFUSE_WAIT_XTAL_DELTA_MSB register, offset: 0x06C */ + volatile uint32_t WAIT_XTAL_MIN; /**< EFUSE_WAIT_XTAL_MIN registers, offset: 0x070 */ + volatile uint32_t WAIT_XTAL_MAX; /**< EFUSE_WAIT_XTAL_MAX registers, offset: 0x074 */ +} efuse_regs_reg_t; + +#define EFUSE_REGS_BASE (SOC_PERI_BASE + 0x09200u) +#define EFUSE_REGS ((efuse_regs_reg_t *)EFUSE_REGS_BASE) + +/* INFO - EFUSE information register */ + +#define EFUSE_INFO_PLT_MASK (0x07U) +#define EFUSE_INFO_PLT_SHIFT (0U) +#define EFUSE_INFO_PLT(x) (((uint32_t)(x) << EFUSE_INFO_PLT_SHIFT) & EFUSE_INFO_PLT_MASK) + +#define EFUSE_INFO_BOOT_MASK (0x38U) +#define EFUSE_INFO_BOOT_SHIFT (3U) +#define EFUSE_INFO_BOOT(x) (((uint32_t)(x) << EFUSE_INFO_BOOT_SHIFT) & EFUSE_INFO_BOOT_MASK) + +#define EFUSE_INFO_ENCRYPTED_MASK (0x40U) +#define EFUSE_INFO_ENCRYPTED_SHIFT (6U) +#define EFUSE_INFO_ENCRYPTED(x) (((uint32_t)(x) << EFUSE_INFO_ENCRYPTED_SHIFT) & EFUSE_INFO_ENCRYPTED_MASK) + +#define EFUSE_INFO_WAIT_XTAL_MASK (0x80U) +#define EFUSE_INFO_WAIT_XTAL_SHIFT (7U) +#define EFUSE_INFO_WAIT_XTAL(x) (((uint32_t)(x) << EFUSE_INFO_WAIT_XTAL_SHIFT) & EFUSE_INFO_WAIT_XTAL_MASK) + +/* FC_STDOUT - Registers Layout Typedef */ + +typedef struct +{ + volatile uint32_t PUTC[16]; /* FC_STDOUT INFO register, offset: 0x000 */ +} fc_stdout_reg_t; + +#define FC_STDOUT_BASE (SOC_PERI_BASE + 0x10000u + (32 << 7)) +#define FC_STDOUT ((fc_stdout_reg_t *)FC_STDOUT_BASE) + +#ifdef FEATURE_CLUSTER +/* CLUSTER_STDOUT - Registers Layout Typedef */ + +typedef struct +{ + volatile uint32_t PUTC[16]; /* CLUSTER_STDOUT INFO register, offset: 0x000 */ +} cluster_stdout_reg_t; + +#define CLUSTER_STDOUT_BASE (SOC_PERI_BASE + 0x10000u) +#define CLUSTER_STDOUT ((cluster_stdout_reg_t *)CLUSTER_STDOUT_BASE) + +/* HWCE - Registers Layout Typedef */ + +typedef struct +{ + volatile uint32_t HWCE_TRIGGER_REG; /* Trigger register */ + volatile uint32_t HWCE_ACQUIRE_REG; /* Acquire register */ + volatile uint32_t HWCE_FINISHED_REG; /* Finished register */ + volatile uint32_t HWCE_STATUS_REG; /* Status register */ + volatile uint32_t HWCE_RUNNING_JOB_REG; /* Running Job register */ + volatile uint32_t HWCE_SOFT_CLEAR_REG; /* Soft_Clear register */ + volatile uint32_t _reserved0[2]; /* Non used registers */ + volatile uint32_t HWCE_GEN_CONFIG0_REG; /* Gen_Config0 register */ + volatile uint32_t HWCE_GEN_CONFIG1_REG; /* Gen_Config1 register */ + volatile uint32_t _reserved1[6]; /* unused registers */ + volatile uint32_t HWCE_Y_TRANS_SIZE_REG; /* Y_Trans_Size register */ + volatile uint32_t HWCE_Y_LINE_STRIDE_LENGTH_REG; /* Y_Line_Stride_Length register */ + volatile uint32_t HWCE_Y_FEAT_STRIDE_LENGTH_REG; /* Y_Feat_Stride_Length register */ + volatile uint32_t HWCE_Y_OUT_3_REG; /* Y_Out_3 register */ + volatile uint32_t HWCE_Y_OUT_2_REG; /* Y_Out_2 register */ + volatile uint32_t HWCE_Y_OUT_1_REG; /* Y_Out_1 register */ + volatile uint32_t HWCE_Y_OUT_0_REG; /* Y_Out_0 register */ + volatile uint32_t HWCE_Y_IN_3_REG; /* Y_In_3 register */ + volatile uint32_t HWCE_Y_IN_2_REG; /* Y_In_2 register */ + volatile uint32_t HWCE_Y_IN_1_REG; /* Y_In_1 register */ + volatile uint32_t HWCE_Y_IN_0_REG; /* Y_In_0 register */ + volatile uint32_t HWCE_X_TRANS_SIZE_REG; /* X_Trans_Size register */ + volatile uint32_t HWCE_X_LINE_STRIDE_LENGTH_REG; /* X_Line_Stride_Length register */ + volatile uint32_t HWCE_X_FEAT_STRIDE_LENGTH_REG; /* X_Feat_Stride_Length register */ + volatile uint32_t HWCE_X_IN_REG; /* X_In register */ + volatile uint32_t HWCE_W_REG; /* W register */ + volatile uint32_t HWCE_JOB_CONFIG0_REG; /* Job_Config0 register */ + volatile uint32_t HWCE_JOB_CONFIG1_REG; /* Job_Config1 register */ +} hwce_reg_t; + +#define HWCE_BASE (CORE_PERI_BASE + 0x00001000) +#define HWCE ((hwce_reg_t *) HWCE_BASE) + +/* Internal registers */ + +#define HWCE_TRIGGER (0x00) +#define HWCE_ACQUIRE (0x04) +#define HWCE_FINISHED (0x08) +#define HWCE_STATUS (0x0C) +#define HWCE_RUNNING_JOB (0x10) +#define HWCE_SOFT_CLEAR (0x14) +#define HWCE_GEN_CONFIG0 (0x20) +#define HWCE_GEN_CONFIG1 (0x24) + +/* Configuration registers */ + +#define HWCE_Y_TRANS_SIZE (0x40) +#define HWCE_Y_LINE_STRIDE_LENGTH (0x44) +#define HWCE_Y_FEAT_STRIDE_LENGTH (0x48) +#define HWCE_Y_OUT_3_BASE_ADDR (0x4C) +#define HWCE_Y_OUT_2_BASE_ADDR (0x50) +#define HWCE_Y_OUT_1_BASE_ADDR (0x54) +#define HWCE_Y_OUT_0_BASE_ADDR (0x58) +#define HWCE_Y_IN_3_BASE_ADDR (0x5C) +#define HWCE_Y_IN_2_BASE_ADDR (0x60) +#define HWCE_Y_IN_1_BASE_ADDR (0x64) +#define HWCE_Y_IN_0_BASE_ADDR (0x68) +#define HWCE_X_TRANS_SIZE (0x6C) +#define HWCE_X_LINE_STRIDE_LENGTH (0x70) +#define HWCE_X_FEAT_STRIDE_LENGTH (0x74) +#define HWCE_X_IN_BASE_ADDR (0x78) +#define HWCE_W_BASE_ADDR (0x7C) +#define HWCE_JOB_CONFIG0 (0x80) +#define HWCE_JOB_CONFIG1 (0x84) + +#define HWCE_NB_IO_REGS (18) + +#define HWCE_ACQUIRE_CONTEXT_COPY (-3) +#define HWCE_ACQUIRE_LOCKED (-2) +#define HWCE_ACQUIRE_QUEUE_FULL (-1) +#define HWCE_ACQUIRE_READY (0) + +#define HWCE_GEN_CONFIG0_WSTRIDE(x) ((x) >> 16) +#define HWCE_GEN_CONFIG0_NCP(x) (((x) >> 13) & 0x1) +#define HWCE_GEN_CONFIG0_CONV(x) (((x) >> 11) & 0x3) +#define HWCE_GEN_CONFIG0_VECT(x) (((x) >> 9) & 0x3) +#define HWCE_GEN_CONFIG0_UNS(x) (((x) >> 8) & 1) +#define HWCE_GEN_CONFIG0_NY(x) (((x) >> 7) & 1) +#define HWCE_GEN_CONFIG0_NF(x) (((x) >> 6) & 1) +#define HWCE_GEN_CONFIG0_QF(x) ((x) & 0x3f) + +#define HWCE_GEN_CONFIG0_CONV_5x5 (0) +#define HWCE_GEN_CONFIG0_CONV_3x3 (1) +#define HWCE_GEN_CONFIG0_CONV_4x7 (2) + +#define HWCE_GEN_CONFIG0_VECT_1 (0) +#define HWCE_GEN_CONFIG0_VECT_2 (1) +#define HWCE_GEN_CONFIG0_VECT_4 (2) + +#define HWCE_GEN_CONFIG1_PIXSHIFTR(x) (((x) >> 16) & 0x1F) +#define HWCE_GEN_CONFIG1_PIXMODE(x) (((x) >> 8) & 0x3) +#define HWCE_GEN_CONFIG1_PIXSHIFTL(x) (((x) >> 0) & 0x1F) + +#define HWCE_JOB_CONFIG0_NOYCONST(x) ((x) >> 16) +#define HWCE_JOB_CONFIG0_LBUFLEN(x) ((x) & 0x3ff) + +#define HWCE_JOB_CONFIG1_LO(x) (((x) >> 24) & 0x1) +#define HWCE_JOB_CONFIG1_WIF(x) (((x) >> 16) & 0x3F) +#define HWCE_JOB_CONFIG1_WOF(x) (((x) >> 8) & 0x1F) +#define HWCE_JOB_CONFIG1_VECT_DISABLE_MASK(x) (((x) >> 0) & 0xF) + +#define HWCE_JOB_STRIDE(x) ((x) >> 16) +#define HWCE_JOB_LENGTH(x) ((x) & 0xffff) + +#endif + +#endif /* __ARCH_RISC_V_SRC_GAP8_GAP8_H */ diff --git a/Ubiquitous/XiZi/arch/risc-v/gap8/tick.c b/Ubiquitous/XiZi/arch/risc-v/gap8/tick.c new file mode 100755 index 0000000..8aa23fd --- /dev/null +++ b/Ubiquitous/XiZi/arch/risc-v/gap8/tick.c @@ -0,0 +1,19 @@ +/* +* Copyright (c) 2020 AIIT XUOS Lab +* XiUOS is licensed under Mulan PSL v2. +* You can use this software according to the terms and conditions of the Mulan PSL v2. +* You may obtain a copy of Mulan PSL v2 at: +* http://license.coscl.org.cn/MulanPSL2 +* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, +* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, +* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. +* See the Mulan PSL v2 for more details. +*/ +#include +static volatile unsigned long tick_cycles = 0; +int TickIsr(void) +{ + TickAndTaskTimesliceUpdate(); + + return 0; +} \ No newline at end of file diff --git a/Ubiquitous/XiZi/arch/risc-v/gd32vf103_rvstar/Makefile b/Ubiquitous/XiZi/arch/risc-v/gd32vf103_rvstar/Makefile new file mode 100755 index 0000000..ea13210 --- /dev/null +++ b/Ubiquitous/XiZi/arch/risc-v/gd32vf103_rvstar/Makefile @@ -0,0 +1,3 @@ +SRC_FILES := boot.S intexc_gd32vf103.S interrupt.c tick.c + +include $(KERNEL_ROOT)/compiler.mk diff --git a/Ubiquitous/XiZi/arch/risc-v/gd32vf103_rvstar/arch_interrupt.h b/Ubiquitous/XiZi/arch/risc-v/gd32vf103_rvstar/arch_interrupt.h new file mode 100755 index 0000000..87e3734 --- /dev/null +++ b/Ubiquitous/XiZi/arch/risc-v/gd32vf103_rvstar/arch_interrupt.h @@ -0,0 +1,12 @@ +#ifndef ARCH_INTERRUPT_H__ +#define ARCH_INTERRUPT_H__ + +#include + +#define ARCH_MAX_IRQ_NUM 128 +#define ARCH_IRQ_NUM_OFFSET 0 + +int ArchEnableHwIrq(uint32_t irq_num); +int ArchDisableHwIrq(uint32_t irq_num); + +#endif \ No newline at end of file diff --git a/Ubiquitous/XiZi/arch/risc-v/gd32vf103_rvstar/tick.c b/Ubiquitous/XiZi/arch/risc-v/gd32vf103_rvstar/tick.c new file mode 100755 index 0000000..3a0e78d --- /dev/null +++ b/Ubiquitous/XiZi/arch/risc-v/gd32vf103_rvstar/tick.c @@ -0,0 +1,28 @@ +/* +* Copyright (c) 2020 AIIT XUOS Lab +* XiUOS is licensed under Mulan PSL v2. +* You can use this software according to the terms and conditions of the Mulan PSL v2. +* You may obtain a copy of Mulan PSL v2 at: +* http://license.coscl.org.cn/MulanPSL2 +* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, +* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, +* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. +* See the Mulan PSL v2 for more details. +*/ +#include +#include +#include + +#define SysTick_Handler eclic_mtip_handler + +/* This is the timer interrupt service routine. */ +void SysTick_Handler(void) +{ + SysTick_Reload(SYSTICK_TICK_CONST); + + // isrManager.done->incCounter(); + + TickAndTaskTimesliceUpdate(); + + // isrManager.done->decCounter(); +} diff --git a/Ubiquitous/XiZi/arch/risc-v/k210/Makefile b/Ubiquitous/XiZi/arch/risc-v/k210/Makefile new file mode 100644 index 0000000..7397d29 --- /dev/null +++ b/Ubiquitous/XiZi/arch/risc-v/k210/Makefile @@ -0,0 +1,7 @@ +SRC_FILES := interrupt.c boot.S tick.c + +ifeq ($(CONFIG_ARCH_SMP),y) + SRC_FILES += smp_support.c +endif + +include $(KERNEL_ROOT)/compiler.mk diff --git a/Ubiquitous/XiZi/arch/risc-v/k210/arch_interrupt.h b/Ubiquitous/XiZi/arch/risc-v/k210/arch_interrupt.h new file mode 100644 index 0000000..982ab71 --- /dev/null +++ b/Ubiquitous/XiZi/arch/risc-v/k210/arch_interrupt.h @@ -0,0 +1,25 @@ +/* +* Copyright (c) 2020 AIIT XUOS Lab +* XiUOS is licensed under Mulan PSL v2. +* You can use this software according to the terms and conditions of the Mulan PSL v2. +* You may obtain a copy of Mulan PSL v2 at: +* http://license.coscl.org.cn/MulanPSL2 +* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, +* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, +* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. +* See the Mulan PSL v2 for more details. +*/ + +#ifndef ARCH_INTERRUPT_H__ +#define ARCH_INTERRUPT_H__ + +#include + +#define ARCH_MAX_IRQ_NUM IRQN_MAX + +#define ARCH_IRQ_NUM_OFFSET 0 + +int32 ArchEnableHwIrq(uint32 irq_num); +int32 ArchDisableHwIrq(uint32 irq_num); + +#endif diff --git a/Ubiquitous/XiZi/arch/risc-v/k210/tick.h b/Ubiquitous/XiZi/arch/risc-v/k210/tick.h new file mode 100644 index 0000000..6aa0827 --- /dev/null +++ b/Ubiquitous/XiZi/arch/risc-v/k210/tick.h @@ -0,0 +1,19 @@ +/* +* Copyright (c) 2020 AIIT XUOS Lab +* XiUOS is licensed under Mulan PSL v2. +* You can use this software according to the terms and conditions of the Mulan PSL v2. +* You may obtain a copy of Mulan PSL v2 at: +* http://license.coscl.org.cn/MulanPSL2 +* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, +* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, +* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. +* See the Mulan PSL v2 for more details. +*/ + +#ifndef TICK_H__ +#define TICK_H__ + +int TickIsr(void); +int InitHwTick(void); + +#endif diff --git a/Ubiquitous/XiZi/arch/risc-v/rv32m1_vega/Makefile b/Ubiquitous/XiZi/arch/risc-v/rv32m1_vega/Makefile new file mode 100755 index 0000000..78887b4 --- /dev/null +++ b/Ubiquitous/XiZi/arch/risc-v/rv32m1_vega/Makefile @@ -0,0 +1,3 @@ +SRC_FILES := startup_RV32M1_ri5cy.S interrupt_gcc.S system_RV32M1_ri5cy.c interrupt.c + +include $(KERNEL_ROOT)/compiler.mk diff --git a/Ubiquitous/XiZi/arch/risc-v/rv32m1_vega/arch_interrupt.h b/Ubiquitous/XiZi/arch/risc-v/rv32m1_vega/arch_interrupt.h new file mode 100755 index 0000000..4ef8b63 --- /dev/null +++ b/Ubiquitous/XiZi/arch/risc-v/rv32m1_vega/arch_interrupt.h @@ -0,0 +1,20 @@ +/** +* @file arch_interrupt.h +* @brief support rv32m1_vega interrupt +* @version 1.0 +* @author AIIT XUOS Lab +* @date 2022-02-16 +*/ + +#ifndef ARCH_INTERRUPT_H__ +#define ARCH_INTERRUPT_H__ + +#include + +#define ARCH_MAX_IRQ_NUM NUMBER_OF_INT_VECTORS +#define ARCH_IRQ_NUM_OFFSET 0 + +int ArchEnableHwIrq(uint32_t irq_num); +int ArchDisableHwIrq(uint32_t irq_num); + +#endif \ No newline at end of file diff --git a/Ubiquitous/XiZi/arch/risc-v/rv32m1_vega/interrupt.c b/Ubiquitous/XiZi/arch/risc-v/rv32m1_vega/interrupt.c new file mode 100755 index 0000000..3c6d410 --- /dev/null +++ b/Ubiquitous/XiZi/arch/risc-v/rv32m1_vega/interrupt.c @@ -0,0 +1,69 @@ +/** +* @file interrupt.c +* @brief support interrupt +* @version 1.0 +* @author AIIT XUOS Lab +* @date 2021-09-02 +*/ + + +#include +#include +#include +#include "fsl_common.h" +#include + +int ArchDisableHwIrq(uint32_t irq_num) +{ + DisableIRQ(irq_num); + return 0; +} + +int ArchEnableHwIrq(uint32_t irq_num) +{ + EnableIRQ(irq_num); + return 0; +} + + +x_base DisableLocalInterrupt(void) +{ + __disable_irq(); + return 0; +} + +/**************************************************************************** + * Name: EnableLocalInterrupt + * + * Description: + * Return the current interrupt state and enable interrupts + * + ****************************************************************************/ + +void EnableLocalInterrupt(x_base oldstat) +{ + __enable_irq(); +} + +typedef void (*irq_handler_t)(void); +extern const irq_handler_t isrTable[]; + +void SystemIrqHandler(uint32_t mcause) +{ + uint32_t intNum; + + if (mcause & 0x80000000) /* For external interrupt. */ + { + intNum = mcause & 0x1FUL; + + /* Clear pending flag in EVENT unit .*/ + EVENT_UNIT->INTPTPENDCLEAR = (1U << intNum); + + /* Now call the real irq handler for intNum */ + isrManager.done->incCounter(); + isrTable[intNum](); + isrManager.done->decCounter(); + } +} + + diff --git a/Ubiquitous/XiZi/arch/risc-v/shared/Makefile b/Ubiquitous/XiZi/arch/risc-v/shared/Makefile new file mode 100644 index 0000000..8d1dd2c --- /dev/null +++ b/Ubiquitous/XiZi/arch/risc-v/shared/Makefile @@ -0,0 +1,9 @@ +SRC_FILES +=riscv64_switch.c +SRC_FILES +=prepare_rhwstack.c + +ifeq ($(CONFIG_TASK_ISOLATION),y) +SRC_FILES += pmp.c +endif + +include $(KERNEL_ROOT)/compiler.mk + diff --git a/Ubiquitous/XiZi/arch/risc-v/shared/boot.h b/Ubiquitous/XiZi/arch/risc-v/shared/boot.h new file mode 100644 index 0000000..e6c6505 --- /dev/null +++ b/Ubiquitous/XiZi/arch/risc-v/shared/boot.h @@ -0,0 +1,126 @@ +/* +* Copyright (c) 2020 AIIT XUOS Lab +* XiUOS is licensed under Mulan PSL v2. +* You can use this software according to the terms and conditions of the Mulan PSL v2. +* You may obtain a copy of Mulan PSL v2 at: +* http://license.coscl.org.cn/MulanPSL2 +* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, +* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, +* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. +* See the Mulan PSL v2 for more details. +*/ +#include "register_para.h" + +.macro ZERO_X_REGISTERS + xor zero, zero, zero + xor ra, ra, ra + xor sp, sp, sp + xor gp, gp, gp + xor tp, tp, tp + xor t0, t0, t0 + xor t1, t1, t1 + xor t2, t2, t2 + xor s0, s0, s0 + xor s1, s1, s1 + xor a0, a0, a0 + xor a1, a1, a1 + xor a2, a2, a2 + xor a3, a3, a3 + xor a4, a4, a4 + xor a5, a5, a5 + xor a6, a6, a6 + xor a7, a7, a7 + xor s2, s2, s2 + xor s3, s3, s3 + xor s4, s4, s4 + xor s5, s5, s5 + xor s6, s6, s6 + xor s7, s7, s7 + xor s8, s8, s8 + xor s9, s9, s9 + xor s10, s10, s10 + xor s11, s11, s11 + xor t3, t3, t3 + xor t4, t4, t4 + xor t5, t5, t5 + xor t6, t6, t6 +.endm + +.macro ZERO_F_REGISTERS + FSubDS f0, f0, f0 + FSubDS f1, f1, f1 + FSubDS f2, f2, f2 + FSubDS f3, f3, f3 + FSubDS f4, f4, f4 + FSubDS f5, f5, f5 + FSubDS f6, f6, f6 + FSubDS f7, f7, f7 + FSubDS f8, f8, f8 + FSubDS f9, f9, f9 + FSubDS f10,f10,f10 + FSubDS f11,f11,f11 + FSubDS f12,f12,f12 + FSubDS f13,f13,f13 + FSubDS f14,f14,f14 + FSubDS f15,f15,f15 + FSubDS f16,f16,f16 + FSubDS f17,f17,f17 + FSubDS f18,f18,f18 + FSubDS f19,f19,f19 + FSubDS f20,f20,f20 + FSubDS f21,f21,f21 + FSubDS f22,f22,f22 + FSubDS f23,f23,f23 + FSubDS f24,f24,f24 + FSubDS f25,f25,f25 + FSubDS f26,f26,f26 + FSubDS f27,f27,f27 + FSubDS f28,f28,f28 + FSubDS f29,f29,f29 + FSubDS f30,f30,f30 + FSubDS f31,f31,f31 +.endm + + .macro SAVE_X_REGISTERS + + addi sp, sp, -32 * RegLength + + StoreD ra, 1 * RegLength(sp) + + csrr ra, mstatus + StoreD ra, 2 * RegLength(sp) + + csrr ra, mepc + StoreD ra, 0 * RegLength(sp) + + StoreD tp, 4 * RegLength(sp) + StoreD t0, 5 * RegLength(sp) + StoreD t1, 6 * RegLength(sp) + StoreD t2, 7 * RegLength(sp) + StoreD s0, 8 * RegLength(sp) + StoreD s1, 9 * RegLength(sp) + StoreD a0, 10 * RegLength(sp) + StoreD a1, 11 * RegLength(sp) + StoreD a2, 12 * RegLength(sp) + StoreD a3, 13 * RegLength(sp) + StoreD a4, 14 * RegLength(sp) + StoreD a5, 15 * RegLength(sp) + StoreD a6, 16 * RegLength(sp) + StoreD a7, 17 * RegLength(sp) + StoreD s2, 18 * RegLength(sp) + StoreD s3, 19 * RegLength(sp) + StoreD s4, 20 * RegLength(sp) + StoreD s5, 21 * RegLength(sp) + StoreD s6, 22 * RegLength(sp) + StoreD s7, 23 * RegLength(sp) + StoreD s8, 24 * RegLength(sp) + StoreD s9, 25 * RegLength(sp) + StoreD s10, 26 * RegLength(sp) + StoreD s11, 27 * RegLength(sp) + StoreD t3, 28 * RegLength(sp) + StoreD t4, 29 * RegLength(sp) + StoreD t5, 30 * RegLength(sp) + StoreD t6, 31 * RegLength(sp) +.endm + + diff --git a/Ubiquitous/XiZi/arch/risc-v/shared/pmp.c b/Ubiquitous/XiZi/arch/risc-v/shared/pmp.c new file mode 100644 index 0000000..93117c6 --- /dev/null +++ b/Ubiquitous/XiZi/arch/risc-v/shared/pmp.c @@ -0,0 +1,517 @@ +/* +* Copyright (c) 2020 AIIT XUOS Lab +* XiUOS is licensed under Mulan PSL v2. +* You can use this software according to the terms and conditions of the Mulan PSL v2. +* You may obtain a copy of Mulan PSL v2 at: +* http://license.coscl.org.cn/MulanPSL2 +* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, +* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, +* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. +* See the Mulan PSL v2 for more details. +*/ + +#include "pmp.h" +#include +#include +#include + +#define USER_TEXT_START (uintptr_t)( USERSPACE ) +#define USER_TEXT_END (uintptr_t)( USERSPACE->us_textend ) +#define USER_SRAM_START (uintptr_t)( USERSPACE->us_datastart ) +#define USER_SRAM_END (uintptr_t)( USERSPACE->us_bssend ) + + +/** + * This function add a pmp tor region to task pmp config + * + * @param task_pmp the task pmp config structure + * @param start the memory start address + * @param size the memory address size + * @param type the memory type + * + * @return EOK + */ +x_err_t PmpAddTorRegion(void *task_pmp, x_ubase start , size_t size , uint8_t type ) +{ + if( task_pmp == NONE) + return -ERROR; + if (size == 0) + return EOK; + + struct Pmp *pmp; + pmp = (struct Pmp *)task_pmp ; + struct PmpRegionTor *region ; + region = (struct PmpRegionTor *)x_malloc(sizeof(struct PmpRegionTor )); + if (region == NONE) + return -ENOMEM; + + uint8_t flag = 0; + switch (type) + { + case REGION_TYPE_CODE: + flag = PMP_R | PMP_X ; + break; + case REGION_TYPE_DATA : + flag = PMP_R | PMP_W ; + break; + case REGION_TYPE_BSS : + flag = PMP_R | PMP_W ; + break; + case REGION_TYPE_HEAP : + flag = PMP_R | PMP_W ; + break; + + default: + break; + } + memset(region,0,sizeof(struct PmpRegionTor )); + InitDoubleLinkList(&(region->link)); + region->region_type = PMP_TOR_TYPE; + region->start = start; + region->end = start + size ; + region->entry[0].pmpcfg = PMP_NA4 | flag; + region->entry[0].pmpaddr = TO_PMP_ADDR(start); + + region->entry[1].pmpcfg = PMP_TOR | flag; + region->entry[1].pmpaddr = TO_PMP_ADDR(ALIGN_MEN_UP(region->end,4)); + + + if (pmp->count <= PMP_MAX_ENTRY_NUMBER - 2 ) + { + DoubleLinkListInsertNodeAfter(&pmp->tor_list, ®ion->link); + pmp->count = pmp->count + 2 ; + }else + { + struct PmpRegionTor *node ; + node = (struct PmpRegionTor *)pmp->tor_list.node_next ; + DoubleLinkListRmNode(&(node->link)); + DoubleLinkListInsertNodeAfter(&pmp->tor_list, ®ion->link); + DoubleLinkListInsertNodeAfter(&pmp->tor_swap_list, &node->link); + node->swap_count ++; + } + return EOK; +} + +/** + * This function free a pmp region + * + * @param task_pmp the task pmp config structure + * @param addr the memory address + * + * @return EOK + */ +x_err_t PmpClearRegion(void *task_pmp, x_ubase addr) +{ + // KPrintf("PmpClearRegion\n"); + if( task_pmp == NONE) + return -ERROR; + struct Pmp *pmp; + pmp = (struct Pmp *)task_pmp ; + + struct PmpRegionTor *tor_node = NONE; + DoubleLinklistType *link = NONE; + + if (!IsDoubleLinkListEmpty(&pmp->tor_list)) { + DOUBLE_LINKLIST_FOR_EACH(link, &pmp->tor_list) { + tor_node = CONTAINER_OF(link, struct PmpRegionTor, link); + if ( addr = tor_node->start ){ + pmp->count = pmp->count -2; + goto __free ; + } + } + } + if (!IsDoubleLinkListEmpty(&pmp->tor_swap_list)) { + DOUBLE_LINKLIST_FOR_EACH(link, &pmp->tor_swap_list) { + tor_node = CONTAINER_OF(link, struct PmpRegionTor, link); + if ( addr = tor_node->start ) { + goto __free; + } + } + } + +__free: + DoubleLinkListRmNode(&(tor_node->link)); + x_free(tor_node); + return EOK; +} + +/** + * This function init a task pmp config structure and add some pmp region + * + * @param task_pmp the task pmp config structure + * @param stack_start the task stack address + * @param stack_size the task stack size + * + * @return EOK + */ +x_err_t PmpInitIsolation(void **task_pmp, x_ubase stack_start , size_t stack_size) +{ + + struct Pmp *pmp ; + pmp = (struct Pmp *)x_malloc(sizeof(struct Pmp)); + if(pmp == NONE) + return -ENOMEMORY; + memset(pmp,0,sizeof(struct Pmp)); + InitDoubleLinkList(&(pmp->tor_list)); + InitDoubleLinkList(&(pmp->tor_swap_list)); + uint8_t index = 0; + + // text + if (USER_TEXT_END - USER_TEXT_START > 0 ) { + pmp->pmp_entry_reserve[index].pmpcfg = PMP_NA4 | PMP_R | PMP_X ; + pmp->pmp_entry_reserve[index].pmpaddr = TO_PMP_ADDR(USER_TEXT_START); + pmp->pmp_entry_reserve[index + 1].pmpcfg = PMP_TOR | PMP_R | PMP_X ; + pmp->pmp_entry_reserve[index + 1].pmpaddr = TO_PMP_ADDR(ALIGN_MEN_UP(USER_TEXT_END,4)); + index = index + 2 ; + pmp->count = pmp->count + 2; + pmp->reserve = pmp->reserve + 2; + } + + // data & bss + if (USER_SRAM_END - USER_SRAM_START > 0 ) { + pmp->pmp_entry_reserve[index].pmpcfg = PMP_NA4 | PMP_R | PMP_W ; + pmp->pmp_entry_reserve[index].pmpaddr = TO_PMP_ADDR(USER_SRAM_START); + pmp->pmp_entry_reserve[index + 1].pmpcfg = PMP_TOR | PMP_R | PMP_W ; + pmp->pmp_entry_reserve[index + 1].pmpaddr = TO_PMP_ADDR(ALIGN_MEN_UP(USER_SRAM_END,4)); + index = index + 2 ; + pmp->count = pmp->count + 2; + pmp->reserve = pmp->reserve + 2; + } + + if (stack_size > 0 ) { + pmp->pmp_entry_reserve[index].pmpcfg = PMP_NA4 | PMP_R | PMP_W | PMP_X ; + pmp->pmp_entry_reserve[index].pmpaddr = TO_PMP_ADDR(stack_start); + pmp->pmp_entry_reserve[index + 1].pmpcfg = PMP_TOR | PMP_R | PMP_W | PMP_X ; + pmp->pmp_entry_reserve[index + 1].pmpaddr = TO_PMP_ADDR(ALIGN_MEN_UP((stack_start + stack_size),4)); + pmp->count = pmp->count + 2; + pmp->reserve = pmp->reserve + 2; + } + + *task_pmp = (void *)pmp; + return EOK; +} + +/** + * This function free task pmp config structure + * + * @param task_pmp the task pmp config structure + * + */ +void PmpFree(void *task_pmp){ + // KPrintf("pmp free \n"); + + if( task_pmp == NONE) + return ; + struct Pmp *pmp; + pmp = (struct Pmp *)task_pmp ; + + struct PmpRegionTor *tor_node = NONE; + DoubleLinklistType *link = NONE; + + if (!IsDoubleLinkListEmpty(&(pmp->tor_list)) ){ + DOUBLE_LINKLIST_FOR_EACH(link, &pmp->tor_list) + { + tor_node = CONTAINER_OF(link, struct PmpRegionTor, link); + DoubleLinkListRmNode(&(tor_node->link)); + x_free(tor_node); + } + } + + if (!IsDoubleLinkListEmpty(&pmp->tor_swap_list)) { + DOUBLE_LINKLIST_FOR_EACH(link, &pmp->tor_swap_list) { + tor_node = CONTAINER_OF(link, struct PmpRegionTor, link); + DoubleLinkListRmNode(&(tor_node->link)); + x_free(tor_node); + } + } + + x_free(pmp); +} + +/** + * This function write value to pmp config register + * @param index pmpcfg register index + * @param value pmpcfg register value + * + */ +void WritePmpcfg(uint8_t index , x_ubase value) +{ + if ( index == 0 ) { + WRITE_CSR(pmpcfg0, value); + }else if ( index == 1 ) { + WRITE_CSR(pmpcfg1, value); + }else if ( index == 2 ) { + WRITE_CSR(pmpcfg2, value); + }else if ( index == 3 ) { + WRITE_CSR(pmpcfg3, value); + } +} + +/** + * This function write value to pmp addr register + * @param index pmpaddr register index + * @param value pmpaddr register value + * + */ +void WritePmpaddr(uint8_t index, x_ubase value) +{ + + if ( index == 0 ) { + WRITE_CSR(pmpaddr0, value); + }else if ( index == 1 ) { + WRITE_CSR(pmpaddr1, value); + }else if ( index == 2 ) { + WRITE_CSR(pmpaddr2, value); + }else if ( index == 3 ) { + WRITE_CSR(pmpaddr3, value); + }else if ( index == 4 ) { + WRITE_CSR(pmpaddr4, value); + }else if ( index == 5 ) { + WRITE_CSR(pmpaddr5, value); + }else if ( index == 6 ) { + WRITE_CSR(pmpaddr6, value); + }else if ( index == 7 ) { + WRITE_CSR(pmpaddr7, value); + }else if ( index == 8 ) { + WRITE_CSR(pmpaddr8, value); + }else if ( index == 9 ) { + WRITE_CSR(pmpaddr9, value); + }else if ( index == 10 ) { + WRITE_CSR(pmpaddr10, value); + }else if ( index == 11 ) { + WRITE_CSR(pmpaddr11, value); + }else if ( index == 12 ) { + WRITE_CSR(pmpaddr12, value); + }else if ( index == 13 ) { + WRITE_CSR(pmpaddr13, value); + }else if ( index == 14 ) { + WRITE_CSR(pmpaddr14, value); + }else if ( index == 15 ) { + WRITE_CSR(pmpaddr15, value); + } +} + +/** + * This function handle user task access memory fault, check addr in pmp swap list or not ,if addr is in + * pmp swap list, swap in to pmp list. + * + * @param task_pmp the task pmp config structure + * @param addr access addr when fault + * + * @return EOK + */ +x_bool PmpAccessFaultHandle(void *task_pmp, x_ubase addr) +{ + if( task_pmp == NONE) + return RET_FALSE; + struct Pmp *pmp; + pmp = (struct Pmp *)task_pmp ; + + x_bool ret = RET_FALSE; + uint8_t region_type; + DoubleLinklistType *link = NONE; + struct PmpRegionTor *tor_node = NONE; + + + if (!IsDoubleLinkListEmpty(&pmp->tor_swap_list) ) { + DOUBLE_LINKLIST_FOR_EACH(link, &pmp->tor_swap_list) { + tor_node = CONTAINER_OF(link, struct PmpRegionTor, link); + if ( addr >= tor_node->start && addr <= (tor_node->end) ) { + region_type = PMP_TOR; + goto __swap; + } + } + } + + goto __exit; + +__swap: + + if ( region_type = PMP_TOR ) { + if( pmp->count < PMP_MAX_ENTRY_NUMBER - 2) { + DoubleLinkListRmNode(&(tor_node->link)); + DoubleLinkListInsertNodeBefore(&pmp->tor_list, &tor_node->link); + pmp->count = pmp->count + 2; + } else { + struct PmpRegionTor *swap_node; + swap_node = (struct PmpRegionTor *)pmp->tor_list.node_next; + DoubleLinkListRmNode(&(swap_node->link)); + DoubleLinkListRmNode(&(tor_node->link)); + DoubleLinkListInsertNodeBefore(&pmp->tor_list, &tor_node->link); + DoubleLinkListInsertNodeBefore(&pmp->tor_swap_list, &swap_node->link); + swap_node->swap_count ++; + + } + + } + ret = RET_TRUE; + +__exit: + return ret; +} + +#if defined(ARCH_RISCV64) +/** + * This function clear pmp registers. + */ +void PmpClear(void) +{ + WRITE_CSR(pmpcfg0, 0); + WRITE_CSR(pmpcfg2, 0); + + WRITE_CSR(pmpaddr0, 0); + WRITE_CSR(pmpaddr1, 0); + WRITE_CSR(pmpaddr2, 0); + WRITE_CSR(pmpaddr3, 0); + WRITE_CSR(pmpaddr4, 0); + WRITE_CSR(pmpaddr5, 0); + WRITE_CSR(pmpaddr6, 0); + WRITE_CSR(pmpaddr7, 0); + WRITE_CSR(pmpaddr8, 0); + WRITE_CSR(pmpaddr9, 0); + WRITE_CSR(pmpaddr10, 0); + WRITE_CSR(pmpaddr11, 0); + WRITE_CSR(pmpaddr12, 0); + WRITE_CSR(pmpaddr13, 0); + WRITE_CSR(pmpaddr14, 0); + WRITE_CSR(pmpaddr15, 0); + +} + +/** + * This function load task pmp config to pmp register. + * @param task_pmp the task pmp config structure + * + */ +void PmpLoad(void *task_pmp) +{ + // KPrintf("pmpLoad \n"); + if( task_pmp == NONE) + return ; + struct Pmp *pmp; + pmp = (struct Pmp *)task_pmp ; + + PmpClear(); + uint8_t index = 0; + x_ubase pmpcfg0 = 0 ; + x_ubase pmpcfg2 = 0 ; + + + for( int i = 0 ; i < pmp->reserve; i++){ + pmpcfg0 |= pmp->pmp_entry_reserve[i].pmpcfg << ( index * 8) ; + WritePmpaddr(index , pmp->pmp_entry_reserve[i].pmpaddr ); + index ++ ; + } + + DoubleLinklistType *link = NONE; + struct PmpRegionTor *node2 = NONE; + + if (!IsDoubleLinkListEmpty(&pmp->tor_list) ){ + DOUBLE_LINKLIST_FOR_EACH(link, &pmp->tor_list) + { + node2 = CONTAINER_OF(link, struct PmpRegionTor, link); + WritePmpaddr(index ,node2->entry[0].pmpaddr ); + if (index < 8) + pmpcfg0 |= node2->entry[0].pmpcfg << ( index * 8); + else + pmpcfg2 |= node2->entry[0].pmpcfg << ( (index - 8) * 8); + index ++; + + WritePmpaddr(index ,node2->entry[1].pmpaddr ); + if (index < 8) + pmpcfg0 |= node2->entry[1].pmpcfg << ( index * 8); + else + pmpcfg2 |= node2->entry[1].pmpcfg << ( (index - 8) * 8); + index ++; + } + } + WritePmpcfg(0, pmpcfg0 ); + WritePmpcfg(2, pmpcfg2 ); +} + +#else + +/** + * This function clear pmp registers. + */ +void PmpClear(void) +{ + WRITE_CSR(pmpcfg0, 0); + WRITE_CSR(pmpcfg1, 0); + WRITE_CSR(pmpcfg2, 0); + WRITE_CSR(pmpcfg3, 0); + + WRITE_CSR(pmpaddr0, 0); + WRITE_CSR(pmpaddr1, 0); + WRITE_CSR(pmpaddr2, 0); + WRITE_CSR(pmpaddr3, 0); + WRITE_CSR(pmpaddr4, 0); + WRITE_CSR(pmpaddr5, 0); + WRITE_CSR(pmpaddr6, 0); + WRITE_CSR(pmpaddr7, 0); + WRITE_CSR(pmpaddr8, 0); + WRITE_CSR(pmpaddr9, 0); + WRITE_CSR(pmpaddr10, 0); + WRITE_CSR(pmpaddr11, 0); + WRITE_CSR(pmpaddr12, 0); + WRITE_CSR(pmpaddr13, 0); + WRITE_CSR(pmpaddr14, 0); + WRITE_CSR(pmpaddr15, 0); +} +#define PMP_CFG_CONVERSE(a,b,c,d) ( ((uint32_t)(d) << 24) | ((uint32_t)(c) << 16) | ((uint32_t)(b) << 8) | (uint32_t)(a) ) + +/** + * This function load task pmp config to pmp register. + * @param task_pmp the task pmp config structure + * + */ +void PmpLoad(void *task_pmp) +{ + // KPrintf("pmpLoad \n"); + if( task_pmp == NONE) + return ; + struct Pmp *pmp; + pmp = (struct Pmp *)task_pmp ; + + PmpClear(); + uint8_t index = 0; + + uint8_t pmpcfg[16] = { 0 } ; + uint32_t pmpcfg0 = 0 ; + uint32_t pmpcfg1 = 0 ; + uint32_t pmpcfg2 = 0 ; + uint32_t pmpcfg3 = 0 ; + + for( int i = 0 ; i < pmp->reserve; i++){ + pmpcfg[index] = pmp->pmp_entry_reserve[i].pmpcfg ; + WritePmpaddr(index , pmp->pmp_entry_reserve[i].pmpaddr ); + index ++ ; + } + + DoubleLinklistType *node = NONE; + struct PmpRegionTor *tor_node = NONE; + if (!IsDoubleLinkListEmpty(&(pmp->tor_list)) ){ + DOUBLE_LINKLIST_FOR_EACH(node, &(pmp->tor_list)) + { + tor_node = CONTAINER_OF(node, struct PmpRegionTor, link); + WritePmpaddr(index ,tor_node->entry[0].pmpaddr ); + pmpcfg[index] = tor_node->entry[0].pmpcfg; + index ++; + + WritePmpaddr(index ,tor_node->entry[1].pmpaddr ); + pmpcfg[index] = tor_node->entry[1].pmpcfg; + index ++; + } + } + + pmpcfg0 = PMP_CFG_CONVERSE(pmpcfg[0], pmpcfg[1], pmpcfg[2], pmpcfg[3]); + pmpcfg1 = PMP_CFG_CONVERSE(pmpcfg[4], pmpcfg[5], pmpcfg[6], pmpcfg[7]); + pmpcfg2 = PMP_CFG_CONVERSE(pmpcfg[8], pmpcfg[9], pmpcfg[10], pmpcfg[11]); + pmpcfg3 = PMP_CFG_CONVERSE(pmpcfg[12], pmpcfg[13], pmpcfg[14], pmpcfg[15]); + WritePmpcfg(0, pmpcfg0); + WritePmpcfg(1, pmpcfg1); + WritePmpcfg(2, pmpcfg2); + WritePmpcfg(3, pmpcfg3); +} + +#endif diff --git a/Ubiquitous/XiZi/arch/risc-v/shared/pmp.h b/Ubiquitous/XiZi/arch/risc-v/shared/pmp.h new file mode 100644 index 0000000..0e0b0cf --- /dev/null +++ b/Ubiquitous/XiZi/arch/risc-v/shared/pmp.h @@ -0,0 +1,93 @@ +/* +* Copyright (c) 2020 AIIT XUOS Lab +* XiUOS is licensed under Mulan PSL v2. +* You can use this software according to the terms and conditions of the Mulan PSL v2. +* You may obtain a copy of Mulan PSL v2 at: +* http://license.coscl.org.cn/MulanPSL2 +* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, +* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, +* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. +* See the Mulan PSL v2 for more details. +*/ + +#ifndef PMP_H +#define PMP_H + +#include + +#define PMP_MAX_ENTRY_NUMBER 16 +#define PMP_ENTRY_RESERVE 6 +#define PMP_ENTRY_MAX 255 + +#define PMP_R 0x01 /* Allow read */ +#define PMP_W 0x02 /* Allow write */ +#define PMP_X 0x04 /* Allow execute */ +#define PMP_L 0x80 /* PMP entry is locked */ +#define PMP_OFF 0x00 /* Null region */ +#define PMP_TOR 0x08 /* Top of range */ +#define PMP_NA4 0x10 /* Naturally aligned four-byte region */ +#define PMP_NAPOT 0x18 /* Naturally aligned power-of-two region */ + +#define PMP_TOR_TYPE 0 /* Top of range */ +#define PMP_NAPOT_TYPE 1 /* Naturally aligned power-of-two region */ + +#define PMP_SHIFT_ADDR 2 +#define PMP_TYPE_MASK 0x18 +#define TO_PMP_ADDR(addr) ((addr) >> PMP_SHIFT_ADDR) +#define FROM_PMP_ADDR(addr) ((addr) << PMP_SHIFT_ADDR) +#define TO_NAPOT_RANGE(size) (((size) - 1) >> 1) +#define TO_PMP_NAPOT(addr, size) TO_PMP_ADDR(addr | TO_NAPOT_RANGE(size)) + +struct PmpEntry +{ + uint8_t pmpcfg; +#if defined(ARCH_RISCV64) + uint64_t pmpaddr; +#else + uint32_t pmpaddr; +#endif + +}; + +struct PmpRegionNapot +{ + x_ubase start ; + x_ubase end; + uint16_t swap_count; + uint8_t region_type; + struct PmpEntry entry; + + DoubleLinklistType link; +}; + +struct PmpRegionTor +{ + x_ubase start ; + x_ubase end; + uint16_t swap_count; + uint8_t region_type; + struct PmpEntry entry[2]; + + DoubleLinklistType link; +}; + +struct Pmp +{ + uint8_t count; + uint8_t reserve; + struct PmpEntry pmp_entry_reserve[PMP_ENTRY_RESERVE]; + DoubleLinklistType tor_list; + + DoubleLinklistType tor_swap_list; +}; + + +x_err_t PmpAddTorRegion(void *task_pmp, x_ubase start , size_t size , uint8_t flag ); +x_err_t PmpInitIsolation(void **task_pmp, x_ubase stack_start , size_t stack_size); +void PmpFree(void *task_pmp); +void PmpClear(void); +x_err_t PmpClearRegion(void *task_pmp, x_ubase addr); +void PmpLoad(void *task_pmp); +x_bool PmpAccessFaultHandle(void *task_pmp, x_ubase addr); + +#endif diff --git a/Ubiquitous/XiZi/arch/risc-v/shared/prepare_rhwstack.c b/Ubiquitous/XiZi/arch/risc-v/shared/prepare_rhwstack.c new file mode 100644 index 0000000..2d1835a --- /dev/null +++ b/Ubiquitous/XiZi/arch/risc-v/shared/prepare_rhwstack.c @@ -0,0 +1,113 @@ +/* +* Copyright (c) 2020 AIIT XUOS Lab +* XiUOS is licensed under Mulan PSL v2. +* You can use this software according to the terms and conditions of the Mulan PSL v2. +* You may obtain a copy of Mulan PSL v2 at: +* http://license.coscl.org.cn/MulanPSL2 +* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, +* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, +* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. +* See the Mulan PSL v2 for more details. +*/ + +#include "register_para.h" +#include +#include +#include +#include +#ifdef TASK_ISOLATION +#include "encoding.h" +#include +#include +#endif + +struct StackRegisterContext +{ + x_ubase epc; + x_ubase ra; + x_ubase mstatus; + x_ubase gp; + x_ubase tp; + x_ubase t0; + x_ubase t1; + x_ubase t2; + x_ubase s0_fp; + x_ubase s1; + x_ubase a0; + x_ubase a1; + x_ubase a2; + x_ubase a3; + x_ubase a4; + x_ubase a5; + x_ubase a6; + x_ubase a7; + x_ubase s2; + x_ubase s3; + x_ubase s4; + x_ubase s5; + x_ubase s6; + x_ubase s7; + x_ubase s8; + x_ubase s9; + x_ubase s10; + x_ubase s11; + x_ubase t3; + x_ubase t4; + x_ubase t5; + x_ubase t6; +}; + +uint8 KTaskStackSetup(struct TaskDescriptor *task) +{ + struct StackRegisterContext *stack_contex; + int i; + + task->stack_point = (uint8 *)ALIGN_MEN_DOWN((x_ubase)(task->task_base_info.stack_start + task->task_base_info.stack_depth), RegLength); + + task->stack_point -= sizeof(struct StackRegisterContext); + + stack_contex = (struct StackRegisterContext *)task->stack_point; + + for (i = 0; i < sizeof(struct StackRegisterContext) / sizeof(x_ubase); i++) + ((x_ubase *)stack_contex)[i] = 0xfadeface; + +#ifdef SEPARATE_COMPILE + if (task->task_dync_sched_member.isolation_flag == 1) { + stack_contex->ra = (unsigned long)USERSPACE->us_taskquit; + } else { + stack_contex->ra = (x_ubase)KTaskQuit; + } + +#else + stack_contex->ra = (x_ubase)KTaskQuit; +#endif + + stack_contex->a0 = (x_ubase)task->task_base_info.func_param; + stack_contex->epc = (x_ubase)task->task_base_info.func_entry; + +#ifdef TASK_ISOLATION + stack_contex->tp = (x_ubase)task; + if(task->task_dync_sched_member.isolation_flag == 1) + stack_contex->mstatus = 0x00006080; + else +#endif + stack_contex->mstatus = 0x00007880; + + return EOK; +} + +#ifdef TASK_ISOLATION +void RestoreMstatus(uintptr_t *sp) +{ + struct TaskDescriptor *tid; + tid = (struct TaskDescriptor *)(sp[4]); + if(tid->task_dync_sched_member.isolation_flag == 1 && tid->task_dync_sched_member.isolation_status == 0){ + CLEAR_CSR(mstatus, (MSTATUS_MPP)); +#ifdef MOMERY_PROTECT_ENABLE + mem_access.Load(tid->task_dync_sched_member.isolation); +#endif + }else{ + SET_CSR(mstatus, MSTATUS_MPP); + } +} +#endif diff --git a/Ubiquitous/XiZi/arch/risc-v/shared/rcontroller.h b/Ubiquitous/XiZi/arch/risc-v/shared/rcontroller.h new file mode 100644 index 0000000..41f0aa5 --- /dev/null +++ b/Ubiquitous/XiZi/arch/risc-v/shared/rcontroller.h @@ -0,0 +1,109 @@ +/* +* Copyright (c) 2020 AIIT XUOS Lab +* XiUOS is licensed under Mulan PSL v2. +* You can use this software according to the terms and conditions of the Mulan PSL v2. +* You may obtain a copy of Mulan PSL v2 at: +* http://license.coscl.org.cn/MulanPSL2 +* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, +* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, +* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. +* See the Mulan PSL v2 for more details. +*/ + +#ifndef RISCV_PLIC_H__ +#define RISCV_PLIC_H__ + +#ifndef PLIC_BASE_ADDR +#define PLIC_BASE_ADDR 0x0 +#endif + +#define PLIC_PRIORITY_OFFSET (0x00000000UL) +#define PLIC_PRIORITY_SHIFT_PER_SOURCE 2 + +#define PLIC_PENDING_OFFSET (0x00001000UL) +#define PLIC_PENDING_SHIFT_PER_SOURCE 0 + +#define PLIC_ENABLE_OFFSET (0x00002000UL) +#define PLIC_ENABLE_SHIFT_PER_TARGET 7 + +#define PLIC_THRESHOLD_OFFSET (0x00200000UL) +#define PLIC_THRESHOLD_SHIFT_PER_TARGET 12 + +#define PLIC_CLAIM_OFFSET (0x00200004UL) +#define PLIC_CLAIM_SHIFT_PER_TARGET 12 + +#if defined(__GNUC__) && !defined(__ASSEMBLER__) +__attribute__((always_inline)) static inline void PlicSetFeature(unsigned int feature) +{ + volatile unsigned int *feature_ptr = (volatile unsigned int *)PLIC_BASE_ADDR; + *feature_ptr = feature; +} + +__attribute__((always_inline)) static inline void PlicSetThreshold(unsigned int threshold) +{ + unsigned int hart_id = READ_CSR(mhartid); + volatile unsigned int *threshold_ptr = (volatile unsigned int *)(PLIC_BASE_ADDR + + PLIC_THRESHOLD_OFFSET + + (hart_id << PLIC_THRESHOLD_SHIFT_PER_TARGET)); + *threshold_ptr = threshold; +} + +__attribute__((always_inline)) static inline void PlicSetPriority(unsigned int source, unsigned int priority) +{ + volatile unsigned int *priority_ptr = (volatile unsigned int *)(PLIC_BASE_ADDR + + PLIC_PRIORITY_OFFSET + + (source << PLIC_PRIORITY_SHIFT_PER_SOURCE)); + *priority_ptr = priority; +} + +__attribute__((always_inline)) static inline void PlicSetPending(unsigned int source) +{ + volatile unsigned int *current_ptr = (volatile unsigned int *)(PLIC_BASE_ADDR + + PLIC_PENDING_OFFSET + + ((source >> 5) << 2)); + *current_ptr = (1 << (source & 0x1F)); +} + +__attribute__((always_inline)) static inline void PlicIrqEnable(unsigned int source) +{ + unsigned int hart_id = READ_CSR(mhartid); + volatile unsigned int *current_ptr = (volatile unsigned int *)(PLIC_BASE_ADDR + + PLIC_ENABLE_OFFSET + + (hart_id << PLIC_ENABLE_SHIFT_PER_TARGET) + + ((source >> 5) << 2)); + unsigned int current = *current_ptr; + current = current | (1 << (source & 0x1F)); + *current_ptr = current; +} + +__attribute__((always_inline)) static inline void PlicIrqDisable(unsigned int source) +{ + unsigned int hart_id = READ_CSR(mhartid); + volatile unsigned int *current_ptr = (volatile unsigned int *)(PLIC_BASE_ADDR + + PLIC_ENABLE_OFFSET + + (hart_id << PLIC_ENABLE_SHIFT_PER_TARGET) + + ((source >> 5) << 2)); + unsigned int current = *current_ptr; + current = current & ~((1 << (source & 0x1F))); + *current_ptr = current; +} + +__attribute__((always_inline)) static inline unsigned int PlicIrqClaim(void) +{ + unsigned int hart_id = READ_CSR(mhartid); + volatile unsigned int *claim_addr = (volatile unsigned int *)(PLIC_BASE_ADDR + + PLIC_CLAIM_OFFSET + + (hart_id << PLIC_CLAIM_SHIFT_PER_TARGET)); + return *claim_addr; +} + +__attribute__((always_inline)) static inline void PlicIrqComplete(unsigned int source) +{ + unsigned int hart_id = READ_CSR(mhartid); + volatile unsigned int *claim_addr = (volatile unsigned int *)(PLIC_BASE_ADDR + + PLIC_CLAIM_OFFSET + + (hart_id << PLIC_CLAIM_SHIFT_PER_TARGET)); + *claim_addr = source; +} +#endif +#endif diff --git a/Ubiquitous/XiZi/arch/risc-v/shared/register_op.h b/Ubiquitous/XiZi/arch/risc-v/shared/register_op.h new file mode 100644 index 0000000..72ee6f6 --- /dev/null +++ b/Ubiquitous/XiZi/arch/risc-v/shared/register_op.h @@ -0,0 +1,43 @@ +/* +* Copyright (c) 2020 AIIT XUOS Lab +* XiUOS is licensed under Mulan PSL v2. +* You can use this software according to the terms and conditions of the Mulan PSL v2. +* You may obtain a copy of Mulan PSL v2 at: +* http://license.coscl.org.cn/MulanPSL2 +* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, +* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, +* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. +* See the Mulan PSL v2 for more details. +*/ + +#ifndef RISCV_OPS_H__ +#define RISCV_OPS_H__ + +#if defined(__GNUC__) && !defined(__ASSEMBLER__) + +#define READ_CSR(reg) ({ unsigned long __tmp; \ + asm volatile ("csrr %0, " #reg : "=r"(__tmp)); \ + __tmp; }) + +#define WRITE_CSR(reg, val) ({ \ + if (__builtin_constant_p(val) && (unsigned long)(val) < 32) \ + asm volatile ("csrw " #reg ", %0" :: "i"(val)); \ + else \ + asm volatile ("csrw " #reg ", %0" :: "r"(val)); }) + +#define SET_CSR(reg, bit) ({ unsigned long __tmp; \ + if (__builtin_constant_p(bit) && (unsigned long)(bit) < 32) \ + asm volatile ("csrrs %0, " #reg ", %1" : "=r"(__tmp) : "i"(bit)); \ + else \ + asm volatile ("csrrs %0, " #reg ", %1" : "=r"(__tmp) : "r"(bit)); \ + __tmp; }) + +#define CLEAR_CSR(reg, bit) ({ unsigned long __tmp; \ + if (__builtin_constant_p(bit) && (unsigned long)(bit) < 32) \ + asm volatile ("csrrc %0, " #reg ", %1" : "=r"(__tmp) : "i"(bit)); \ + else \ + asm volatile ("csrrc %0, " #reg ", %1" : "=r"(__tmp) : "r"(bit)); \ + __tmp; }) +#endif + +#endif diff --git a/Ubiquitous/XiZi/arch/risc-v/shared/register_para.h b/Ubiquitous/XiZi/arch/risc-v/shared/register_para.h new file mode 100644 index 0000000..05f53ce --- /dev/null +++ b/Ubiquitous/XiZi/arch/risc-v/shared/register_para.h @@ -0,0 +1,36 @@ +/* +* Copyright (c) 2020 AIIT XUOS Lab +* XiUOS is licensed under Mulan PSL v2. +* You can use this software according to the terms and conditions of the Mulan PSL v2. +* You may obtain a copy of Mulan PSL v2 at: +* http://license.coscl.org.cn/MulanPSL2 +* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, +* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, +* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. +* See the Mulan PSL v2 for more details. +*/ + +#ifndef CPUPORT_H__ +#define CPUPORT_H__ + +#include + +#ifdef ARCH_CPU_64BIT +#define StoreD sd +#define LoadD ld +#define FSubDS fsub.d +#define RegLength 8 +#define StoreDS "sd" +#define LoadDS "ld" +#define RegLengthS "8" +#else +#define StoreD sw +#define LoadD lw +#define FSubDS fsub.s +#define RegLength 4 +#define StoreDS "sw" +#define LoadDS "lw" +#define RegLengthS "4" +#endif + +#endif diff --git a/Ubiquitous/XiZi/arch/risc-v/shared/riscv64_switch.c b/Ubiquitous/XiZi/arch/risc-v/shared/riscv64_switch.c new file mode 100644 index 0000000..cabc661 --- /dev/null +++ b/Ubiquitous/XiZi/arch/risc-v/shared/riscv64_switch.c @@ -0,0 +1,134 @@ +/* +* Copyright (c) 2020 AIIT XUOS Lab +* XiUOS is licensed under Mulan PSL v2. +* You can use this software according to the terms and conditions of the Mulan PSL v2. +* You may obtain a copy of Mulan PSL v2 at: +* http://license.coscl.org.cn/MulanPSL2 +* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, +* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, +* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. +* See the Mulan PSL v2 for more details. +*/ + +#include "register_para.h" +#include +#include + +void __attribute__((naked)) SwitchKTaskContextExit() +{ + asm volatile (LoadDS " a0, 0 * " RegLengthS "(sp)"); + asm volatile ("csrw mepc, a0"); +#ifdef TASK_ISOLATION + asm volatile (LoadDS " a0, 2 * " RegLengthS "(sp)"); + asm volatile ("csrw mstatus, a0"); + asm volatile ("mv a0, sp"); + asm volatile ("jal RestoreMstatus"); +#else + asm volatile ("li t0, 0x00007800"); + asm volatile ("csrw mstatus, t0"); + asm volatile (LoadDS " a0, 2 * " RegLengthS "(sp)"); + asm volatile ("csrs mstatus, a0"); +#endif + asm volatile (LoadDS " ra, 1 * " RegLengthS "(sp)"); + asm volatile (LoadDS " tp, 4 * " RegLengthS "(sp)"); + asm volatile (LoadDS " t0, 5 * " RegLengthS "(sp)"); + asm volatile (LoadDS " t1, 6 * " RegLengthS "(sp)"); + asm volatile (LoadDS " t2, 7 * " RegLengthS "(sp)"); + asm volatile (LoadDS " s0, 8 * " RegLengthS "(sp)"); + asm volatile (LoadDS " s1, 9 * " RegLengthS "(sp)"); + asm volatile (LoadDS " a0, 10 * " RegLengthS "(sp)"); + asm volatile (LoadDS " a1, 11 * " RegLengthS "(sp)"); + asm volatile (LoadDS " a2, 12 * " RegLengthS "(sp)"); + asm volatile (LoadDS " a3, 13 * " RegLengthS "(sp)"); + asm volatile (LoadDS " a4, 14 * " RegLengthS "(sp)"); + asm volatile (LoadDS " a5, 15 * " RegLengthS "(sp)"); + asm volatile (LoadDS " a6, 16 * " RegLengthS "(sp)"); + asm volatile (LoadDS " a7, 17 * " RegLengthS "(sp)"); + asm volatile (LoadDS " s2, 18 * " RegLengthS "(sp)"); + asm volatile (LoadDS " s3, 19 * " RegLengthS "(sp)"); + asm volatile (LoadDS " s4, 20 * " RegLengthS "(sp)"); + asm volatile (LoadDS " s5, 21 * " RegLengthS "(sp)"); + asm volatile (LoadDS " s6, 22 * " RegLengthS "(sp)"); + asm volatile (LoadDS " s7, 23 * " RegLengthS "(sp)"); + asm volatile (LoadDS " s8, 24 * " RegLengthS "(sp)"); + asm volatile (LoadDS " s9, 25 * " RegLengthS "(sp)"); + asm volatile (LoadDS " s10, 26 * " RegLengthS "(sp)"); + asm volatile (LoadDS " s11, 27 * " RegLengthS "(sp)"); + asm volatile (LoadDS " t3, 28 * " RegLengthS "(sp)"); + asm volatile (LoadDS " t4, 29 * " RegLengthS "(sp)"); + asm volatile (LoadDS " t5, 30 * " RegLengthS "(sp)"); + asm volatile (LoadDS " t6, 31 * " RegLengthS "(sp)"); + asm volatile ("addi sp, sp, 32 * " RegLengthS ""); + asm volatile ("mret"); +} + +void __attribute__((naked)) SaveMpie() +{ + asm volatile (StoreDS " a0, 2 * " RegLengthS "(sp)"); + asm volatile (StoreDS " tp, 4 * " RegLengthS "(sp)"); + asm volatile (StoreDS " t0, 5 * " RegLengthS "(sp)"); + asm volatile (StoreDS " t1, 6 * " RegLengthS "(sp)"); + asm volatile (StoreDS " t2, 7 * " RegLengthS "(sp)"); + asm volatile (StoreDS " s0, 8 * " RegLengthS "(sp)"); + asm volatile (StoreDS " s1, 9 * " RegLengthS "(sp)"); + asm volatile (StoreDS " a0, 10 * " RegLengthS "(sp)"); + asm volatile (StoreDS " a1, 11 * " RegLengthS "(sp)"); + asm volatile (StoreDS " a2, 12 * " RegLengthS "(sp)"); + asm volatile (StoreDS " a3, 13 * " RegLengthS "(sp)"); + asm volatile (StoreDS " a4, 14 * " RegLengthS "(sp)"); + asm volatile (StoreDS " a5, 15 * " RegLengthS "(sp)"); + asm volatile (StoreDS " a6, 16 * " RegLengthS "(sp)"); + asm volatile (StoreDS " a7, 17 * " RegLengthS "(sp)"); + asm volatile (StoreDS " s2, 18 * " RegLengthS "(sp)"); + asm volatile (StoreDS " s3, 19 * " RegLengthS "(sp)"); + asm volatile (StoreDS " s4, 20 * " RegLengthS "(sp)"); + asm volatile (StoreDS " s5, 21 * " RegLengthS "(sp)"); + asm volatile (StoreDS " s6, 22 * " RegLengthS "(sp)"); + asm volatile (StoreDS " s7, 23 * " RegLengthS "(sp)"); + asm volatile (StoreDS " s8, 24 * " RegLengthS "(sp)"); + asm volatile (StoreDS " s9, 25 * " RegLengthS "(sp)"); + asm volatile (StoreDS " s10, 26 * " RegLengthS "(sp)"); + asm volatile (StoreDS " s11, 27 * " RegLengthS "(sp)"); + asm volatile (StoreDS " t3, 28 * " RegLengthS "(sp)"); + asm volatile (StoreDS " t4, 29 * " RegLengthS "(sp)"); + asm volatile (StoreDS " t5, 30 * " RegLengthS "(sp)"); + asm volatile (StoreDS " t6, 31 * " RegLengthS "(sp)"); + asm volatile (LoadDS " sp, (a1)"); + asm volatile ("mv a0, a2"); + asm volatile ("jal RestoreCpusLockStatus"); + asm volatile ("j SwitchKTaskContextExit"); +} + +void __attribute__((naked)) SwitchKtaskContextTo(x_ubase to, struct TaskDescriptor *to_task) +{ + asm volatile (LoadDS " sp, (a0)\n"); + asm volatile ("mv a0, a1"); + asm volatile ("jal RestoreCpusLockStatus"); + asm volatile (LoadDS " a7, 2 * " RegLengthS "(sp)"); + asm volatile ("csrw mstatus, a7"); + asm volatile ("j SwitchKTaskContextExit"); +} + +void __attribute__((naked)) SwitchKtaskContext(x_ubase from, x_ubase to, struct TaskDescriptor *to_task) +{ + asm volatile ("addi sp, sp, -32 * " RegLengthS); + asm volatile (StoreDS " sp, (a0)"); + asm volatile (StoreDS " x1, 0 * " RegLengthS "(sp)"); + asm volatile (StoreDS " x1, 1 * " RegLengthS "(sp)"); + asm volatile ("csrr a0, mstatus"); +#ifndef TASK_ISOLATION + asm volatile ("andi a0, a0, 8"); + asm volatile ("beqz a0, SaveMpie"); + asm volatile ("li a0, 0x80"); +#endif + asm volatile ("j SaveMpie"); +} + +void __attribute__((naked)) HwInterruptcontextSwitch(x_ubase from, x_ubase to, struct TaskDescriptor *to_task, void *context) +{ + asm volatile (StoreDS " a3, 0(a0)"); + asm volatile (LoadDS " sp, 0(a1)"); + asm volatile ("move a0, a2"); + asm volatile ("call RestoreCpusLockStatus"); + asm volatile ("j SwitchKTaskContextExit"); +} diff --git a/Ubiquitous/XiZi/board/Makefile b/Ubiquitous/XiZi/board/Makefile new file mode 100644 index 0000000..67e6867 --- /dev/null +++ b/Ubiquitous/XiZi/board/Makefile @@ -0,0 +1,6 @@ + +SRC_DIR := $(BOARD) + + + +include $(KERNEL_ROOT)/compiler.mk diff --git a/Ubiquitous/XiZi/board/aiit-arm32-board/.defconfig b/Ubiquitous/XiZi/board/aiit-arm32-board/.defconfig new file mode 100644 index 0000000..08045f2 --- /dev/null +++ b/Ubiquitous/XiZi/board/aiit-arm32-board/.defconfig @@ -0,0 +1,220 @@ +# +# Automatically generated file; DO NOT EDIT. +# XiUOS Project Configuration +# +CONFIG_BOARD_STM32F407_EVB=y +CONFIG_KERNEL_CONSOLE_DEVICE_NAME="uart1" +CONFIG_ARCH_ARM=y + +# +# aiit-arm32-board feature +# +CONFIG_BSP_USING_DMA=y +CONFIG_BSP_USING_GPIO=y +# CONFIG_BSP_USING_I2C is not set +# CONFIG_BSP_USING_LCD is not set +# CONFIG_BSP_USING_RTC is not set +# CONFIG_BSP_USING_SPI is not set +# CONFIG_BSP_USING_SPI1 is not set +# CONFIG_BSP_USING_SPI2 is not set +# CONFIG_BSP_USING_SPI3 is not set +# CONFIG_BSP_USING_HWTIMER is not set +# CONFIG_BSP_USING_TOUCH is not set +CONFIG_BSP_USING_WDT=y +CONFIG_BSP_USING_UART=y +# CONFIG_BSP_USING_UART1 is not set +# CONFIG_BSP_USING_UART2 is not set +# CONFIG_BSP_USING_UART3 is not set +# CONFIG_BSP_USING_UART4 is not set +# CONFIG_BSP_USING_UART5 is not set +# CONFIG_BSP_USING_USB is not set +# CONFIG_BSP_USING_STM32_USBH is not set + +# +# Hardware feature +# +CONFIG_RESOURCES_SERIAL=y +CONFIG_SERIAL_USING_DMA=y +# CONFIG_SERIAL_RB_BUFSZ is not set +# CONFIG_RESOURCES_HWTIMER is not set +# CONFIG_RESOURCES_CAN is not set +# CONFIG_RESOURCES_I2C is not set +# CONFIG_RESOURCES_LCD is not set +# CONFIG_RESOURCES_SDIO is not set +# CONFIG_RESOURCES_TOUCH is not set +CONFIG_RESOURCES_PIN=y +CONFIG_RESOURCES_RTC=y +# CONFIG_RESOURCES_SPI is not set +# CONFIG_RESOURCES_SPI_SD is not set +# CONFIG_RESOURCES_SPI_SFUD is not set +# SFUD_USING_SFDP is not set +# SFUD_USING_FLASH_INFO_TABLE is not set +# SFUD_DEBUG_LOG is not set +CONFIG_RESOURCES_WDT=y +# CONFIG_RESOURCES_USB is not set +# CONFIG_RESOURCES_USB_HOST is not set +# CONFIG_UDISK_MOUNTPOINT is not set +# CONFIG_USBH_MSTORAGE is not set +# CONFIG_RESOURCES_USB_DEVICE is not set +# CONFIG_USBD_THREAD_STACK_SZ is not set + +# +# Kernel feature +# +# CONFIG_SEPARATE_COMPILE is not set +# CONFIG_COMPILER_APP is not set +# CONFIG_COMPILER_KERNEL is not set +# +# Kernel Device Object +# +CONFIG_KERNEL_DEVICE=y +CONFIG_KERNEL_CONSOLE=y +CONFIG_KERNEL_CONSOLEBUF_SIZE=128 + +# +# Task feature +# +CONFIG_SCHED_POLICY_RR_REMAINSLICE=y +# CONFIG_SCHED_POLICY_RR is not set +# CONFIG_SCHED_POLICY_FIFO is not set + +# +# Inter-Task communication +# +CONFIG_KERNEL_SEMAPHORE=y +CONFIG_KERNEL_MUTEX=y +CONFIG_KERNEL_EVENT=y +CONFIG_KERNEL_MESSAGEQUEUE=y +# CONFIG_KTASK_PRIORITY_8 is not set +CONFIG_KTASK_PRIORITY_32=y +# CONFIG_KTASK_PRIORITY_256 is not set +CONFIG_KTASK_PRIORITY_MAX=32 +CONFIG_TICK_PER_SECOND=1000 +CONFIG_KERNEL_STACK_OVERFLOW_CHECK=y +CONFIG_KERNEL_BANNER=y +# CONFIG_KERNEL_HOOK is not set +CONFIG_KERNEL_SOFTTIMER=y +CONFIG_KERNEL_IDLE_HOOK=y +CONFIG_IDEL_HOOK_LIST_SIZE=4 +CONFIG_IDLE_KTASK_STACKSIZE=256 +CONFIG_USER_APPLICATION=y +# CONFIG_TASK_ISOLATION is not set + +# +# Memory Management +# +# CONFIG_KERNEL_MEMBLOCK is not set + +# +# Command shell +# +CONFIG_TOOL_SHELL=y +CONFIG_SHELL_ENTER_CR=y +CONFIG_SHELL_ENTER_LF=y +CONFIG_SHELL_ENTER_CR_AND_LF=y +# CONFIG_SHELL_ENTER_CRLF is not set + +# +# User Control +# +CONFIG_SHELL_DEFAULT_USER="letter" +CONFIG_SHELL_DEFAULT_USER_PASSWORD="" +CONFIG_SHELL_LOCK_TIMEOUT=10000 +CONFIG_SHELL_TASK_STACK_SIZE=4096 +CONFIG_SHELL_TASK_PRIORITY=20 +CONFIG_SHELL_MAX_NUMBER=5 +CONFIG_SHELL_PARAMETER_MAX_NUMBER=8 +CONFIG_SHELL_HISTORY_MAX_NUMBER=5 +CONFIG_SHELL_PRINT_BUFFER=128 +CONFIG_SHELL_USING_CMD_EXPORT=y +CONFIG_SHELL_HELP_SHOW_PERMISSION=y +# CONFIG_SHELL_HELP_LIST_USER is not set +# CONFIG_SHELL_HELP_LIST_VAR is not set +# CONFIG_SHELL_HELP_LIST_KEY is not set +CONFIG_KERNEL_QUEUEMANAGE=y +CONFIG_KERNEL_WORKQUEUE=y +CONFIG_WORKQUEUE_KTASK_STACKSIZE=512 +CONFIG_WORKQUEUE_KTASK_PRIORITY=23 +CONFIG_KERNEL_WAITQUEUE=y +CONFIG_KERNEL_DATAQUEUE=y +# CONFIG_KERNEL_CIRCULAR_AREA is not set +# CONFIG_KERNEL_AVL_TREE is not set +CONFIG_NAME_MAX=8 +CONFIG_ALIGN_SIZE=4 +CONFIG_KERNEL_COMPONENTS_INIT=y +CONFIG_KERNEL_USER_MAIN=y +CONFIG_MAIN_KTASK_STACK_SIZE=2048 +CONFIG_ENV_INIT_KTASK_STACK_SIZE=8192 +CONFIG_MAIN_KTASK_PRIORITY=10 +# CONFIG_USER_TEST is not set +# CONFIG_TOOL_TEST_SEM is not set +# CONFIG_TOOL_TEST_MUTEX is not set +# CONFIG_TOOL_TEST_EVENT is not set +# CONFIG_TOOL_TEST_MSG is not set +# CONFIG_TOOL_TEST_AVLTREE is not set +# CONFIG_TEST_CRICULAR_AREA is not set +# CONFIG_TOOL_TEST_MEM is not set +# CONFIG_TOOL_TEST_TIMER is not set +# CONFIG_TOOL_TEST_IWG is not set +# CONFIG_TOOL_TEST_REALTIME is not set +# CONFIG_TOOL_TEST_DBG is not set +# CONFIG_TOOL_TEST_SCHED is not set +# CONFIG_KERNEL_DEBUG is not set +CONFIG_DEBUG_INIT_CONFIG=y +CONFIG_DBG_INIT=1 +# CONFIG_ARCH_SMP is not set + +# +# File system +# +CONFIG_FS_VFS=y +CONFIG_VFS_USING_WORKDIR=y +CONFIG_FS_VFS_DEVFS=y + +# +# Fat filesystem +# + +# +# IOT-Device File system +# + +# +# Lwext4 filesystem +# + +# +# APP Framework +# + +# +# connection +# +# CONFIG_CONNECTION_AT is not set +# CONFIG_CONNECTION_MQTT is not set + +# +# medium communication +# + + +# +# Intelligence +# + +# +# Control +# + +# +# Lib +# +CONFIG_LIB=y +CONFIG_LIB_POSIX=y +CONFIG_LIB_NEWLIB=y + +CONFIG_LITTLEVGL2RTT_USING_DEMO=y + +# +# Security +# diff --git a/Ubiquitous/XiZi/board/aiit-arm32-board/Kconfig b/Ubiquitous/XiZi/board/aiit-arm32-board/Kconfig new file mode 100644 index 0000000..5016abc --- /dev/null +++ b/Ubiquitous/XiZi/board/aiit-arm32-board/Kconfig @@ -0,0 +1,69 @@ +mainmenu "XiZi Project Configuration" + +config BSP_DIR + string + option env="BSP_ROOT" + default "." + +config KERNEL_DIR + string + option env="KERNEL_ROOT" + default "../.." + +config BOARD_STM32F407_EVB + bool + select ARCH_ARM + default y + +source "$KERNEL_DIR/arch/Kconfig" + +menu "aiit-arm32-board feature" + source "$BSP_DIR/third_party_driver/Kconfig" + + menu "config default board resources" + menu "config board app name" + config BOARD_APP_NAME + string "config board app name" + default "/XiUOS_aiit-arm32-board_app.bin" + endmenu + + menu "config board service table" + config SERVICE_TABLE_ADDRESS + hex "board service table address" + default 0x20000000 + endmenu + + menu "config hardware resources for connection" + if CONNECTION_COMMUNICATION_ETHERNET + config ETHERNET_UART_NAME + string "ethernet uart name" + default "/dev/usart3_dev3" + endif + if CONNECTION_COMMUNICATION_WIFI + config WIFI_UART_NAME + string "wifi uart name" + default "/dev/usart3_dev3" + endif + if CONNECTION_COMMUNICATION_LORA + config LORA_SPI_NAME + string "lora spi name" + default "/dev/spi2_lora" + endif + endmenu + + menu "config board peripheral" + config MOUNT_SDCARD + bool "mount cd card" + default n + select BSP_USING_SDIO + endmenu + endmenu +endmenu + + + +menu "Hardware feature" +source "$KERNEL_DIR/resources/Kconfig" +endmenu + +source "$KERNEL_DIR/Kconfig" diff --git a/Ubiquitous/XiZi/board/aiit-arm32-board/Kselector b/Ubiquitous/XiZi/board/aiit-arm32-board/Kselector new file mode 100644 index 0000000..da73506 --- /dev/null +++ b/Ubiquitous/XiZi/board/aiit-arm32-board/Kselector @@ -0,0 +1,40 @@ + +mainmenu "Ubiquitous Kernel Selector" + +config BSP_DIR + string + option env="BSP_ROOT" + default "." + +config KERNEL_DIR + string + option env="KERNEL_ROOT" + default "../.." + +config UBIQUITOUS_DIR + string + option env="UBIQUITOUS_ROOT" + default "../../.." + +source "$UBIQUITOUS_DIR/Kselector_features" + +source "$UBIQUITOUS_DIR/Kselector_params" + +config MANUALLY_SELECT + bool "Manually select a kernel" + default n +if MANUALLY_SELECT +menu "Required Kernel" +choice + prompt "Select OS Kernel" + default SELECT_XIUOS + + config SELECT_RT_THREAD + bool "select RT_Thread" + config SELECT_NUTTX + bool "select Nuttx" + config SELECT_XIUOS + bool "select XiZi" +endchoice +endmenu +endif diff --git a/Ubiquitous/XiZi/board/aiit-arm32-board/Makefile b/Ubiquitous/XiZi/board/aiit-arm32-board/Makefile new file mode 100644 index 0000000..65bddea --- /dev/null +++ b/Ubiquitous/XiZi/board/aiit-arm32-board/Makefile @@ -0,0 +1,8 @@ +SRC_FILES := board.c + +SRC_DIR := third_party_driver + + + + +include $(KERNEL_ROOT)/compiler.mk diff --git a/Ubiquitous/XiZi/board/aiit-arm32-board/README.md b/Ubiquitous/XiZi/board/aiit-arm32-board/README.md new file mode 100644 index 0000000..005ee44 --- /dev/null +++ b/Ubiquitous/XiZi/board/aiit-arm32-board/README.md @@ -0,0 +1,82 @@ +# AIIT-ARM32-BOARD README + +## 1. 简介 + +| 硬件 | 描述 | +| -- | -- | +|芯片型号| Stm32F407zgt6| +|CPU|arm cortex-m4| +|主频| 168MHz | +|片内SRAM| 192KB | +|扩展SRAM| 1MB | +|片上FLASH| 512KB | +|扩展FLASH| 2MB | +| 外设 | 内嵌FPU处理器 | +| | DCMI、JTAG、OTG、ADC、DAC、USB、GPIO、UART、SPI、SDIO、RTC、I²S、CAN、DMA、MAC、I²C、WDT、Timer与PWM | + +XiUOS板级当前支持使用CH438、GPIO、I2C、LCD、USB、RTC、SDIO、SPI、Timer、UART和WDT等。 + +## 2. 编译说明 + +### 编译环境：Ubuntu18.04 + +### 编译工具链：arm-none-eabi-gcc + +编译步骤： +> 1.ARM下编译需要安装arm-none-eabi编译工具, 安装到Ubuntu的默认路径/usr/bin/arm-none-eabi-，使用如下命令行下载 +``` +sudo apt-get install gcc-arm-none-eabi +``` +>2.在代码根目录下执行以下命令，生成配置文件 + +``` +cd ./Ubiquitous/XiZi +make BOARD=aiit-arm32-board distclean +make BOARD=aiit-arm32-board menuconfig +``` +>3.在menuconfig界面配置需要关闭和开启的功能，按回车键进入下级菜单，按Y键选中需要开启的功能，按N键选中需要关闭的功能，配置结束后保存并退出 + +![img](./img/menu.png ) + +>4.继续执行以下命令，进行编译 +``` +make BOARD=aiit-arm32-board +``` +>5.如果编译正确无误，会产生XiZi_aiit-arm32-board.elf、XiZi_aiit-arm32-board.bin文件。其中XiZi_aiit-arm32-board.bin需要烧写到设备中进行运行。 +``` +sudo write build/XiZi_aiit-arm32-board.bin 0x8000000 +``` +>6.最后可以执行以下命令，清除配置文件和编译生成的文件 +``` +make BOARD=aiit-arm32-board distclean +``` + +## 3. 烧写及执行 + +将 BOARD=aiit-arm32-board开发板SWD经 st-link 转接到USB接口，然后使用st-flash工具进行烧写bin文件。 + +st-link 图片如下： + +
+ +
+ + +执行以下命令下载st-link工具驱动 +``` +git clone https://github.com/texane/stlink.git +``` +aiit-arm32-board下载连接示意图如下： +
+ +
+ +代码根目录下执行st-flash工具烧录 +``` +sudo st-flash write build/XiZi_aiit-arm32-board.bin 0x8000000 +``` +### 3.1 运行结果 + +如果编译 & 烧写无误，将会在串口终端上看到信息打印输出，(终端串口引脚为PA9、PA10)。 + +![img](./img/shell.png ) diff --git a/Ubiquitous/XiZi/board/aiit-arm32-board/board.c b/Ubiquitous/XiZi/board/aiit-arm32-board/board.c new file mode 100644 index 0000000..7a44604 --- /dev/null +++ b/Ubiquitous/XiZi/board/aiit-arm32-board/board.c @@ -0,0 +1,227 @@ +/* +* Copyright (c) 2020 AIIT XUOS Lab +* XiUOS is licensed under Mulan PSL v2. +* You can use this software according to the terms and conditions of the Mulan PSL v2. +* You may obtain a copy of Mulan PSL v2 at: +* http://license.coscl.org.cn/MulanPSL2 +* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, +* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, +* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. +* See the Mulan PSL v2 for more details. +*/ + +/** +* @file board.c +* @brief support aiit-arm32-board init configure and start-up +* @version 1.0 +* @author AIIT XUOS Lab +* @date 2021-04-25 +*/ + +/************************************************* +File name: board.c +Description: support aiit-arm32-board init configure and driver/task/... init +Others: +History: +1. Date: 2021-04-25 +Author: AIIT XUOS Lab +Modification: +1. support aiit-arm32-board InitBoardHardware +*************************************************/ + +#include +#include +#include +#include +#include + +extern void entry(void); +extern int Stm32HwPinInit(void); +extern int Stm32HwTimerInit(void); +extern int HwWdtInit(void); +extern int Stm32HwI2cInit(void); +extern int Stm32HwCh438Init(void); +extern int Stm32HwSpiInit(void); +extern int Stm32HwUsartInit(); +extern int Stm32HwRtcInit(); +extern int Stm32HwTouchBusInit(void); +extern int Stm32HwCanBusInit(void); +extern int HwSdioInit(); +extern int HwSramInit(void); +extern int Stm32HwAdcInit(void); +extern int Stm32HwDacInit(void); +extern int Stm32HwLcdInit(void); + +static void ClockConfiguration() +{ + int cr,cfgr,pllcfgr; + int cr1,cfgr1,pllcfgr1; + RCC->APB1ENR |= RCC_APB1ENR_PWREN; + PWR->CR |= PWR_CR_VOS; + RCC_HSEConfig(RCC_HSE_ON); + if (RCC_WaitForHSEStartUp() == SUCCESS) + { + RCC_HCLKConfig(RCC_SYSCLK_Div1); + RCC_PCLK2Config(RCC_HCLK_Div2); + RCC_PCLK1Config(RCC_HCLK_Div4); + RCC_PLLConfig(RCC_PLLSource_HSE, 8, 336, 2, 7); + + RCC_PLLCmd(ENABLE); + while (RCC_GetFlagStatus(RCC_FLAG_PLLRDY) == RESET); + + FLASH->ACR = FLASH_ACR_ICEN |FLASH_ACR_DCEN |FLASH_ACR_LATENCY_5WS; + RCC_SYSCLKConfig(RCC_SYSCLKSource_PLLCLK); + + while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS ) != RCC_CFGR_SWS_PLL); + } + SystemCoreClockUpdate(); + +} + +void NVIC_Configuration(void) +{ +#ifdef VECT_TAB_RAM + NVIC_SetVectorTable(NVIC_VectTab_RAM, 0x0); +#else + NVIC_SetVectorTable(NVIC_VectTab_FLASH, 0x0); +#endif + + NVIC_PriorityGroupConfig(NVIC_PriorityGroup_2); +} + +void SysTickConfiguration(void) +{ + RCC_ClocksTypeDef rcc_clocks; + uint32 cnts; + + RCC_GetClocksFreq(&rcc_clocks); + + cnts = (uint32)rcc_clocks.HCLK_Frequency / TICK_PER_SECOND; + cnts = cnts / 8; + + SysTick_Config(cnts); + SysTick_CLKSourceConfig(SysTick_CLKSource_HCLK_Div8); +} + +void SysTick_Handler(int irqn, void *arg) +{ + + TickAndTaskTimesliceUpdate(); + +} +DECLARE_HW_IRQ(SysTick_IRQn, SysTick_Handler, NONE); + +void stm32f407_start() +{ + entry(); +} +struct InitSequenceDesc _board_init[] = +{ +#ifdef BSP_USING_GPIO + { "hw pin", Stm32HwGpioInit }, +#endif +#ifdef BSP_USING_CH438 + { "hw_extuart", Stm32HwCh438Init }, +#endif +#ifdef BSP_USING_HWTIMER + { "hw timer", Stm32HwTimerInit }, +#endif +#ifdef BSP_USING_SPI + { "hw spi", Stm32HwSpiInit }, +#endif +#ifdef BSP_USING_WDT + { "hw wdg", HwWdtInit }, +#endif +#ifdef BSP_USING_I2C + { "hw i2c", Stm32HwI2cInit}, +#endif +#ifdef BSP_USING_RTC + { "hw rtc", Stm32HwRtcInit}, +#endif +#ifdef BSP_USING_TOUCH + { "hw touch", Stm32HwTouchBusInit}, +#endif +#ifdef BSP_USING_CAN + { "hw can", Stm32HwCanBusInit}, +#endif +#ifdef BSP_USING_SDIO + {"hw sdcard init",HwSdioInit}, +#endif +#ifdef BSP_USING_EXTMEM + { "hw extern sram", HwSramInit }, +#endif +#ifdef BSP_USING_ADC + {"hw adc init", Stm32HwAdcInit}, +#endif +#ifdef BSP_USING_DAC + {"hw dac init", Stm32HwDacInit}, +#endif +#ifdef BSP_USING_LCD + {"hw lcd init", Stm32HwLcdInit}, +#endif + { " NONE ",NONE }, +}; + +#if defined(FS_VFS) && defined(MOUNT_SDCARD) +#include + +/** + * @description: Mount SD card + * @return 0 + */ +int MountSDCard(void) +{ + if (MountFilesystem(SDIO_BUS_NAME, SDIO_DEVICE_NAME, SDIO_DRIVER_NAME, FSTYPE_FATFS, "/") == 0) + DBG("sd card mount to '/'"); + else + SYS_WARN("sd card mount to '/' failed!"); + + return 0; +} +#endif + +void InitBoardHardware() +{ + int i = 0; + int ret = 0; + ClockConfiguration(); + + NVIC_Configuration(); + + SysTickConfiguration(); + InitBoardMemory((void*)MEMORY_START_ADDRESS, (void*)MEMORY_END_ADDRESS); + +#ifdef BSP_USING_UART + Stm32HwUsartInit(); +#endif + +#ifdef KERNEL_CONSOLE + InstallConsole(KERNEL_CONSOLE_BUS_NAME, KERNEL_CONSOLE_DRV_NAME, KERNEL_CONSOLE_DEVICE_NAME); + KPrintf("\nconsole init completed.\n"); + + KPrintf("board initialization......\n"); +#endif + +#ifdef SEPARATE_COMPILE + + // init mpu + //extern int MPU_Init(void); + //extern struct task_mpu_config *mpuTaskInit(void); + //extern void MPULoad(struct task_mpu_config *mpu); + //extern void MPULoad1(struct task_mpu_config *mpu); + //extern void MPURead(void); + //MPU_Init(); + //MPULoad1(mpuTaskInit()); + //KPrintf("read mpu after load\n"); + //MPURead(); +#endif + + for(i = 0; _board_init[i].fn != NONE; i++) { + ret = _board_init[i].fn(); + KPrintf("initialize %s %s\n",_board_init[i].fn_name, ret == 0 ? "success" : "failed"); + } + + KPrintf("board init done.\n"); + KPrintf("start kernel...\n"); + KPrintf("%d",RCC_GetSYSCLKSource()); +} diff --git a/Ubiquitous/XiZi/board/aiit-arm32-board/board.h b/Ubiquitous/XiZi/board/aiit-arm32-board/board.h new file mode 100644 index 0000000..73ea0d6 --- /dev/null +++ b/Ubiquitous/XiZi/board/aiit-arm32-board/board.h @@ -0,0 +1,91 @@ +/* +* Copyright (c) 2020 AIIT XUOS Lab +* XiUOS is licensed under Mulan PSL v2. +* You can use this software according to the terms and conditions of the Mulan PSL v2. +* You may obtain a copy of Mulan PSL v2 at: +* http://license.coscl.org.cn/MulanPSL2 +* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, +* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, +* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. +* See the Mulan PSL v2 for more details. +*/ + +/** +* @file board.h +* @brief define aiit-arm32-board init configure and start-up function +* @version 1.0 +* @author AIIT XUOS Lab +* @date 2021-04-25 +*/ + +/************************************************* +File name: board.h +Description: define aiit-arm32-board board init function and struct +Others: +History: +1. Date: 2021-04-25 +Author: AIIT XUOS Lab +Modification: +1. define aiit-arm32-board InitBoardHardware +2. define aiit-arm32-board data and bss struct +*************************************************/ + +#ifndef BOARD_H +#define BOARD_H + +#include +#include + +extern int __stack_end__; +extern unsigned int g_service_table_start; +extern unsigned int g_service_table_end; + +#define STM32_USE_SDIO 0 + +#define STM32_EXT_SRAM 0 +#define STM32_EXT_SRAM_BEGIN 0x68000000 +#define STM32_EXT_SRAM_END 0x68080000 + +#define SURPORT_MPU + +#ifdef __ICCARM__ +extern char __ICFEDIT_region_RAM_end__; +#define STM32_SRAM_END &__ICFEDIT_region_RAM_end__ +#else + +#define MEMORY_START_ADDRESS (&__stack_end__) +#define STM32_SRAM_SIZE 128 +#define MEMORY_END_ADDRESS (0x20000000 + STM32_SRAM_SIZE * 1024) + +#ifdef SEPARATE_COMPILE +typedef int (*main_t)(int argc, char *argv[]); +typedef void (*exit_t)(void); +struct userspace_s +{ + main_t us_entrypoint; + exit_t us_taskquit; + uintptr_t us_textstart; + uintptr_t us_textend; + uintptr_t us_datasource; + uintptr_t us_datastart; + uintptr_t us_dataend; + uintptr_t us_bssstart; + uintptr_t us_bssend; + uintptr_t us_heapend; +}; +#define USERSPACE (( struct userspace_s *)(0x08040000)) + +#ifndef SERVICE_TABLE_ADDRESS +#define SERVICE_TABLE_ADDRESS (0x20000000) +#endif + +#define USER_SRAM_SIZE 64 +#define USER_MEMORY_START_ADDRESS (USERSPACE->us_bssend) +#define USER_MEMORY_END_ADDRESS (0x10000000 + USER_SRAM_SIZE * 1024) +#endif +#endif + +void InitBoardHardware(void); +void stm32f407_start(void); + +#endif \ No newline at end of file diff --git a/Ubiquitous/XiZi/board/aiit-arm32-board/config.mk b/Ubiquitous/XiZi/board/aiit-arm32-board/config.mk new file mode 100644 index 0000000..d69e4ea --- /dev/null +++ b/Ubiquitous/XiZi/board/aiit-arm32-board/config.mk @@ -0,0 +1,17 @@ +export CROSS_COMPILE ?=/usr/bin/arm-none-eabi- + +export CFLAGS := -mcpu=cortex-m4 -mthumb -mfpu=fpv4-sp-d16 -mfloat-abi=hard -ffunction-sections -fdata-sections -Dgcc -O0 -gdwarf-2 -g -fgnu89-inline -Wa,-mimplicit-it=thumb -Werror +export AFLAGS := -c -mcpu=cortex-m4 -mthumb -mfpu=fpv4-sp-d16 -mfloat-abi=hard -ffunction-sections -fdata-sections -x assembler-with-cpp -Wa,-mimplicit-it=thumb -gdwarf-2 +export LFLAGS := -mcpu=cortex-m4 -mthumb -mfpu=fpv4-sp-d16 -mfloat-abi=hard -ffunction-sections -fdata-sections -Wl,--gc-sections,-Map=XiZi.map,-cref,-u,Reset_Handler -T $(BSP_ROOT)/link.lds +export CXXFLAGS := -mcpu=cortex-m4 -mthumb -mfpu=fpv4-sp-d16 -mfloat-abi=hard -ffunction-sections -fdata-sections -Dgcc -O0 -gdwarf-2 -g + +export APPLFLAGS := -mcpu=cortex-m4 -mthumb -mfpu=fpv4-sp-d16 -mfloat-abi=hard -ffunction-sections -fdata-sections -Wl,--gc-sections,-Map=XiZi_app.map,-cref,-u, -T $(BSP_ROOT)/link_userspace.lds + +export DEFINES := -DHAVE_CCONFIG_H -DSTM32F407xx -DUSE_HAL_DRIVER -DHAVE_SIGINFO + +export USING_NEWLIB =1 +export USING_VFS = 1 +export USING_SPI = 1 +export ARCH = arm + +export USING_LORA = 1 diff --git a/Ubiquitous/XiZi/board/aiit-arm32-board/img/aiit.jpg b/Ubiquitous/XiZi/board/aiit-arm32-board/img/aiit.jpg new file mode 100644 index 0000000..ca47da8 Binary files /dev/null and b/Ubiquitous/XiZi/board/aiit-arm32-board/img/aiit.jpg differ diff --git a/Ubiquitous/XiZi/board/aiit-arm32-board/img/menu.png b/Ubiquitous/XiZi/board/aiit-arm32-board/img/menu.png new file mode 100644 index 0000000..889dfb8 Binary files /dev/null and b/Ubiquitous/XiZi/board/aiit-arm32-board/img/menu.png differ diff --git a/Ubiquitous/XiZi/board/aiit-arm32-board/img/shell.png b/Ubiquitous/XiZi/board/aiit-arm32-board/img/shell.png new file mode 100644 index 0000000..e9f0b62 Binary files /dev/null and b/Ubiquitous/XiZi/board/aiit-arm32-board/img/shell.png differ diff --git a/Ubiquitous/XiZi/board/aiit-arm32-board/img/st-link.png b/Ubiquitous/XiZi/board/aiit-arm32-board/img/st-link.png new file mode 100644 index 0000000..4284399 Binary files /dev/null and b/Ubiquitous/XiZi/board/aiit-arm32-board/img/st-link.png differ diff --git a/Ubiquitous/XiZi/board/aiit-arm32-board/link.lds b/Ubiquitous/XiZi/board/aiit-arm32-board/link.lds new file mode 100644 index 0000000..067ea19 --- /dev/null +++ b/Ubiquitous/XiZi/board/aiit-arm32-board/link.lds @@ -0,0 +1,110 @@ +/* +* Copyright (c) 2020 AIIT XUOS Lab +* XiUOS is licensed under Mulan PSL v2. +* You can use this software according to the terms and conditions of the Mulan PSL v2. +* You may obtain a copy of Mulan PSL v2 at: +* http://license.coscl.org.cn/MulanPSL2 +* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, +* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, +* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. +* See the Mulan PSL v2 for more details. +*/ + +__SYSTEM_STACKSIZE__ = 0x400; + +OUTPUT_ARCH(arm) + +MEMORY +{ + flash (rx) : ORIGIN = 0x08000000, LENGTH = 256k /* 256KB flash */ + sram (rw) : ORIGIN = 0x20001000, LENGTH = 124k /* 124k sram */ +} + +ENTRY(Reset_Handler) +SECTIONS +{ + .text : + { + . = ALIGN(4); + PROVIDE(_stext = ABSOLUTE(.)); + KEEP(*(.isr_vector)) /* Startup code */ + + + . = ALIGN(4); + *(.text .text.*) /* Normal code */ + *(.rodata .rodata*) /* read-only data (constants) */ + + *(.glue_7) + *(.glue_7t) + + /* section information for shell */ + . = ALIGN(4); + _shell_command_start = .; + KEEP (*(shellCommand)) + _shell_command_end = .; + . = ALIGN(4); + + /* the work i did */ + PROVIDE(__ctors_start__ = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array)) + PROVIDE(__ctors_end__ = .); + + . = ALIGN(4); + /* the work i did */ + + __isrtbl_idx_start = .; + KEEP(*(.isrtbl.idx)) + __isrtbl_start = .; + KEEP(*(.isrtbl)) + __isrtbl_end = .; + . = ALIGN(4); + + PROVIDE(g_service_table_start = ABSOLUTE(.)); + KEEP(*(.g_service_table)) + PROVIDE(g_service_table_end = ABSOLUTE(.)); + + PROVIDE(_etext = ABSOLUTE(.)); + } > flash + + __exidx_start = .; + .ARM.exidx : + { + PROVIDE(__exidx_start = ABSOLUTE(.)); + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + _sidata = .; + PROVIDE(__exidx_end = ABSOLUTE(.)); + } > flash + + .data : AT(__exidx_end) + { + . = ALIGN(4); + PROVIDE(_sdata = ABSOLUTE(.)); + *(.data .data.*) + PROVIDE(_edata = ABSOLUTE(.)); + } > sram + + .bss : + { + . = ALIGN(4); + __bss_start = ABSOLUTE(.); + + *(.bss .bss.*) + *(COMMON) + + . = ALIGN(4); + __bss_end = ABSOLUTE(.); + } > sram + + .stack : + { + . = ALIGN(4); + PROVIDE(__stack_start__ = ABSOLUTE(.)); + /* cpu stack */ + . = . + __SYSTEM_STACKSIZE__; + __stack_tp = .; + PROVIDE(__stack_end__ = ABSOLUTE(.)); + } > sram + + _end = ABSOLUTE(.); +} diff --git a/Ubiquitous/XiZi/board/aiit-arm32-board/link_userspace.lds b/Ubiquitous/XiZi/board/aiit-arm32-board/link_userspace.lds new file mode 100644 index 0000000..5de607e --- /dev/null +++ b/Ubiquitous/XiZi/board/aiit-arm32-board/link_userspace.lds @@ -0,0 +1,70 @@ +/* +* You can use this software according to the terms and conditions of the Mulan PSL v2. +* You may obtain a copy of Mulan PSL v2 at: +* http://license.coscl.org.cn/MulanPSL2 +* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, +* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, +* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. +* See the Mulan PSL v2 for more details. +*/ + +OUTPUT_ARCH(arm) + +MEMORY +{ + uflash (rx) : ORIGIN = 0x08040000, LENGTH = 256k /* 256KB uflash */ + usram (rw) : ORIGIN = 0x10000000, LENGTH = 64k /* 64K usram */ +} + +SECTIONS +{ + .userspace : + { + . = ALIGN(4); + KEEP(*(.userspace)) + } > uflash + + .text : + { + _ustext = ABSOLUTE(.); + *(.text .text.*) + *(.rodata .rodata*) + *(.glue_7) + *(.glue_7t) + PROVIDE(_uetext = ABSOLUTE(.)); + } > uflash + + .init_section : { + _sinit = ABSOLUTE(.); + KEEP(*(.init_array .init_array.*)) + _einit = ABSOLUTE(.); + } > uflash + + __uexidx_start = ABSOLUTE(.); + + .ARM.exidx : + { + PROVIDE(__uexidx_start = ABSOLUTE(.)); + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + PROVIDE(__uexidx_end = ABSOLUTE(.)); + } > uflash + + _ueronly = ABSOLUTE(.); + + .data : AT(_ueronly) + { + _usdata = ABSOLUTE(.); + *(.data .data.*) + . = ALIGN(4); + _uedata = ABSOLUTE(.); + } > usram + + .bss : { + . = ALIGN(4); + _usbss = ABSOLUTE(.); + *(.bss .bss.*) + *(.sbss .sbss.*) + . = ALIGN(4); + _uebss = ABSOLUTE(.); + } > usram +} \ No newline at end of file diff --git a/Ubiquitous/XiZi/board/aiit-arm32-board/third_party_driver/Kconfig b/Ubiquitous/XiZi/board/aiit-arm32-board/third_party_driver/Kconfig new file mode 100755 index 0000000..a7978bc --- /dev/null +++ b/Ubiquitous/XiZi/board/aiit-arm32-board/third_party_driver/Kconfig @@ -0,0 +1,138 @@ +menuconfig BSP_USING_CH438 +bool "Using CH438 device" +default y +if BSP_USING_CH438 +source "$BSP_DIR/third_party_driver/ch438/Kconfig" +endif + +menuconfig BSP_USING_DMA +bool "Using DMA device" +default y +if BSP_USING_DMA +source "$BSP_DIR/third_party_driver/common/Kconfig" +endif + +menuconfig BSP_USING_EXTMEM +bool "Using EXTMEM device" +default n +select MEM_EXTERN_SRAM +if BSP_USING_EXTMEM +source "$BSP_DIR/third_party_driver/extmem/Kconfig" +endif + +menuconfig BSP_USING_GPIO +bool "Using GPIO device " +default y +select RESOURCES_PIN +if BSP_USING_GPIO +source "$BSP_DIR/third_party_driver/gpio/Kconfig" +endif + +menuconfig BSP_USING_I2C +bool "Using I2C device" +default n +select RESOURCES_I2C +if BSP_USING_I2C +source "$BSP_DIR/third_party_driver/i2c/Kconfig" +endif + +menuconfig BSP_USING_LCD +bool "Using LCD device" +default n +select RESOURCES_LCD +if BSP_USING_LCD +source "$BSP_DIR/third_party_driver/lcd/Kconfig" +endif + +menuconfig BSP_USING_RTC +bool "Using RTC device" +default n +select RESOURCES_RTC +if BSP_USING_RTC +source "$BSP_DIR/third_party_driver/rtc/Kconfig" +endif + +menuconfig BSP_USING_SDIO +bool "Using SDIO device" +default n +select RESOURCES_SDIO +if BSP_USING_SDIO +source "$BSP_DIR/third_party_driver/sdio/Kconfig" +endif + +menuconfig BSP_USING_SPI +bool "Using SPI device" +default n +select RESOURCES_SPI +select BSP_USING_DMA +if BSP_USING_SPI +source "$BSP_DIR/third_party_driver/spi/Kconfig" +endif + +menuconfig BSP_USING_HWTIMER +bool "Using HWTIMER device" +default n +select RESOURCES_HWTIMER +if BSP_USING_HWTIMER +source "$BSP_DIR/third_party_driver/timer/Kconfig" +endif + +menuconfig BSP_USING_TOUCH +bool "Using TOUCH device" +default n +select RESOURCES_TOUCH +if BSP_USING_TOUCH +source "$BSP_DIR/third_party_driver/touch/Kconfig" +endif + +menuconfig BSP_USING_UART +bool "Using UART device" +default y +select RESOURCES_SERIAL +if BSP_USING_UART +source "$BSP_DIR/third_party_driver/uart/Kconfig" +endif + +menuconfig BSP_USING_ADC +bool "Using ADC device" +default n +select RESOURCES_ADC +if BSP_USING_ADC +source "$BSP_DIR/third_party_driver/adc/Kconfig" +endif + +menuconfig BSP_USING_DAC +bool "Using DAC device" +default n +select RESOURCES_DAC +if BSP_USING_DAC +source "$BSP_DIR/third_party_driver/dac/Kconfig" +endif + +menuconfig BSP_USING_CAN +bool "Using CAN device" +default n +select RESOURCES_CAN +if BSP_USING_CAN +source "$BSP_DIR/third_party_driver/can/Kconfig" +endif + +menuconfig BSP_USING_USB +bool "Using USB device" +default n +select BSP_USING_STM32_USBH +select RESOURCES_USB +select RESOURCES_USB_HOST +select USBH_MSTORAGE +select RESOURCES_USB_DEVICE +if BSP_USING_USB +source "$BSP_DIR/third_party_driver/usb/Kconfig" +endif + +menuconfig BSP_USING_WDT +bool "Using WATCHDOG device" +default y +select RESOURCES_WDT +if BSP_USING_WDT +source "$BSP_DIR/third_party_driver/watchdog/Kconfig" +endif diff --git a/Ubiquitous/XiZi/board/aiit-arm32-board/third_party_driver/Makefile b/Ubiquitous/XiZi/board/aiit-arm32-board/third_party_driver/Makefile new file mode 100644 index 0000000..dd2c656 --- /dev/null +++ b/Ubiquitous/XiZi/board/aiit-arm32-board/third_party_driver/Makefile @@ -0,0 +1,67 @@ +SRC_DIR := common + +ifeq ($(CONFIG_BSP_USING_CH438),y) + SRC_DIR += ch438 +endif + +ifeq ($(CONFIG_BSP_USING_EXTMEM),y) + SRC_DIR += extmem +endif + +ifeq ($(CONFIG_BSP_USING_GPIO),y) + SRC_DIR += gpio +endif + +ifeq ($(CONFIG_BSP_USING_I2C),y) + SRC_DIR += i2c +endif + +ifeq ($(CONFIG_BSP_USING_LCD),y) + SRC_DIR += lcd +endif + +ifeq ($(CONFIG_BSP_USING_RTC),y) + SRC_DIR += rtc +endif + +ifeq ($(CONFIG_BSP_USING_SDIO),y) + SRC_DIR += sdio +endif + +ifeq ($(CONFIG_BSP_USING_SPI),y) + SRC_DIR += spi +endif + +ifeq ($(CONFIG_BSP_USING_HWTIMER),y) + SRC_DIR += timer +endif + +ifeq ($(CONFIG_BSP_USING_TOUCH),y) + SRC_DIR += touch +endif + +ifeq ($(CONFIG_BSP_USING_UART),y) + SRC_DIR += uart +endif + +ifeq ($(CONFIG_BSP_USING_USB),y) + SRC_DIR += usb +endif + +ifeq ($(CONFIG_BSP_USING_WDT),y) + SRC_DIR += watchdog +endif + +ifeq ($(CONFIG_BSP_USING_CAN),y) + SRC_DIR += can +endif + +ifeq ($(CONFIG_BSP_USING_ADC),y) + SRC_DIR += adc +endif + +ifeq ($(CONFIG_BSP_USING_DAC),y) + SRC_DIR += dac +endif + +include $(KERNEL_ROOT)/compiler.mk diff --git a/Ubiquitous/XiZi/board/aiit-arm32-board/third_party_driver/adc/Kconfig b/Ubiquitous/XiZi/board/aiit-arm32-board/third_party_driver/adc/Kconfig new file mode 100644 index 0000000..ac7cd30 --- /dev/null +++ b/Ubiquitous/XiZi/board/aiit-arm32-board/third_party_driver/adc/Kconfig @@ -0,0 +1,76 @@ + + +menuconfig BSP_USING_ADC1 + bool "Enable ADC1" + default n + if BSP_USING_ADC1 + config ADC1_BUS_NAME + string "adc 1 bus name" + default "adc1" + + config ADC1_DRIVER_NAME + string "adc 1 driver name" + default "adc1_drv" + + config ADC1_DEVICE_NAME + string "adc 1 bus device name" + default "adc1_dev" + + config ADC1_GPIO_NUM + int "adc 1 gpio pin num" + default "0" + + config ADC1_GPIO_DEF + string "adc 1 gpio define type" + default "A" + endif + +menuconfig BSP_USING_ADC2 + bool "Enable ADC2" + default n + if BSP_USING_ADC2 + config ADC2_BUS_NAME + string "adc 2 bus name" + default "adc2" + + config ADC2_DRIVER_NAME + string "adc 2 driver name" + default "adc2_drv" + + config ADC2_DEVICE_NAME + string "adc 2 bus device name" + default "adc2_dev" + + config ADC2_GPIO_NUM + int "adc 2 gpio pin num" + default "6" + + config ADC2_GPIO_DEF + string "adc 2 gpio define type" + default "A" + endif + +menuconfig BSP_USING_ADC3 + bool "Enable ADC3" + default n + if BSP_USING_ADC3 + config ADC3_BUS_NAME + string "adc 3 bus name" + default "adc3" + + config ADC3_DRIVER_NAME + string "adc 3 driver name" + default "adc3_drv" + + config ADC3_DEVICE_NAME + string "adc 3 bus device name" + default "adc3_dev" + + config ADC3_GPIO_NUM + int "adc 3 gpio pin num" + default "0" + + config ADC3_GPIO_DEF + string "adc 3 gpio define type" + default "A" + endif diff --git a/Ubiquitous/XiZi/board/aiit-arm32-board/third_party_driver/adc/Makefile b/Ubiquitous/XiZi/board/aiit-arm32-board/third_party_driver/adc/Makefile new file mode 100644 index 0000000..c2dc54f --- /dev/null +++ b/Ubiquitous/XiZi/board/aiit-arm32-board/third_party_driver/adc/Makefile @@ -0,0 +1,3 @@ +SRC_FILES := connect_adc.c hardware_adc.c + +include $(KERNEL_ROOT)/compiler.mk \ No newline at end of file diff --git a/Ubiquitous/XiZi/board/aiit-arm32-board/third_party_driver/adc/connect_adc.c b/Ubiquitous/XiZi/board/aiit-arm32-board/third_party_driver/adc/connect_adc.c new file mode 100644 index 0000000..26f7e64 --- /dev/null +++ b/Ubiquitous/XiZi/board/aiit-arm32-board/third_party_driver/adc/connect_adc.c @@ -0,0 +1,433 @@ +/* +* Copyright (c) 2020 AIIT XUOS Lab +* XiUOS is licensed under Mulan PSL v2. +* You can use this software according to the terms and conditions of the Mulan PSL v2. +* You may obtain a copy of Mulan PSL v2 at: +* http://license.coscl.org.cn/MulanPSL2 +* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, +* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, +* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. +* See the Mulan PSL v2 for more details. +*/ + +/** +* @file connect_adc.c +* @brief support to register ADC pointer and function +* @version 1.1 +* @author AIIT XUOS Lab +* @date 2021-12-28 +*/ + +#include + +#define _ADC_CONS(string1, string2) string1##string2 +#define ADC_CONS(string1, string2) _ADC_CONS(string1, string2) + +#ifdef BSP_USING_ADC1 +#define ADC1_GPIO ADC_CONS(GPIO_Pin_, ADC1_GPIO_NUM) +#endif + +#ifdef BSP_USING_ADC2 +#define ADC2_GPIO ADC_CONS(GPIO_Pin_, ADC2_GPIO_NUM) +#endif + +#ifdef BSP_USING_ADC3 +#define ADC3_GPIO ADC_CONS(GPIO_Pin_, ADC3_GPIO_NUM) +#endif + +static int Stm32AdcUdelay(uint32 us) +{ + uint32 ticks; + uint32 told, tnow, tcnt = 0; + uint32 reload = SysTick->LOAD; + + ticks = us * reload / (1000000 / TICK_PER_SECOND); + told = SysTick->VAL; + while (1) { + tnow = SysTick->VAL; + if (tnow != told) { + if (tnow < told) { + tcnt += told - tnow; + } else { + tcnt += reload - tnow + told; + } + told = tnow; + if (tcnt >= ticks) { + return 0; + break; + } + } + } +} + +static GPIO_TypeDef* AdcGetGpioType(char *adc_gpio_def) +{ + if (0 == strncmp(adc_gpio_def, "A", 2)) { + return GPIOA; + } else if (0 == strncmp(adc_gpio_def, "B", 2)) { + return GPIOB; + } else if (0 == strncmp(adc_gpio_def, "C", 2)) { + return GPIOC; + } else if (0 == strncmp(adc_gpio_def, "F", 2)) { + return GPIOF; + } else { + printf("AdcGetGpioType do not support %s GPIO\n", adc_gpio_def); + return GPIOA; + } +} + +static uint32 AdcGetGpioRcc(char *adc_gpio_def) +{ + if (0 == strncmp(adc_gpio_def, "A", 2)) { + return RCC_AHB1Periph_GPIOA; + } else if (0 == strncmp(adc_gpio_def, "B", 2)) { + return RCC_AHB1Periph_GPIOB; + } else if (0 == strncmp(adc_gpio_def, "C", 2)) { + return RCC_AHB1Periph_GPIOC; + } else if (0 == strncmp(adc_gpio_def, "F", 2)) { + return RCC_AHB1Periph_GPIOF; + } else { + printf("AdcGetGpioRcc do not support %s GPIO\n", adc_gpio_def); + return RCC_AHB1Periph_GPIOA; + } +} + +static void AdcInit(struct AdcHardwareDevice *adc_dev) +{ + GPIO_InitTypeDef GPIO_InitStructure; + ADC_CommonInitTypeDef ADC_CommonInitStructure; + ADC_InitTypeDef ADC_InitStructure; + uint32_t RCC_AHB1Periph; + GPIO_TypeDef* GPIOx; + +#ifdef BSP_USING_ADC1 + if (0 == strncmp(adc_dev->haldev.dev_name, ADC1_DEVICE_NAME, NAME_NUM_MAX)) { + + GPIOx = AdcGetGpioType(ADC1_GPIO_DEF); + RCC_AHB1Periph = AdcGetGpioRcc(ADC1_GPIO_DEF); + + RCC_AHB1PeriphClockCmd(RCC_AHB1Periph, ENABLE);//enable GPIOA clock + RCC_APB2PeriphClockCmd(RCC_APB2Periph_ADC1, ENABLE);//enable ADC1 clock + + GPIO_InitStructure.GPIO_Pin = ADC1_GPIO; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AN;//analog input + GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL; + GPIO_Init(GPIOx, &GPIO_InitStructure); + + RCC_APB2PeriphResetCmd(RCC_APB2Periph_ADC1, ENABLE); + RCC_APB2PeriphResetCmd(RCC_APB2Periph_ADC1, DISABLE); + + ADC_CommonInitStructure.ADC_Mode = ADC_Mode_Independent; + ADC_CommonInitStructure.ADC_TwoSamplingDelay = ADC_TwoSamplingDelay_5Cycles; + ADC_CommonInitStructure.ADC_DMAAccessMode = ADC_DMAAccessMode_Disabled; + ADC_CommonInitStructure.ADC_Prescaler = ADC_Prescaler_Div4; + ADC_CommonInit(&ADC_CommonInitStructure); + + ADC_InitStructure.ADC_Resolution = ADC_Resolution_12b;//12 bit mode + ADC_InitStructure.ADC_ScanConvMode = DISABLE; + ADC_InitStructure.ADC_ContinuousConvMode = DISABLE; + ADC_InitStructure.ADC_ExternalTrigConvEdge = ADC_ExternalTrigConvEdge_None; + ADC_InitStructure.ADC_DataAlign = ADC_DataAlign_Right; + ADC_InitStructure.ADC_NbrOfConversion = 1; + ADC_Init(ADC1, &ADC_InitStructure); + + ADC_Cmd(ADC1, ENABLE); + } +#endif + +#ifdef BSP_USING_ADC2 + if (0 == strncmp(adc_dev->haldev.dev_name, ADC2_DEVICE_NAME, NAME_NUM_MAX)) { + + GPIOx = AdcGetGpioType(ADC2_GPIO_DEF); + RCC_AHB1Periph = AdcGetGpioRcc(ADC2_GPIO_DEF); + + RCC_AHB1PeriphClockCmd(RCC_AHB1Periph, ENABLE);//enable GPIOA clock + RCC_APB2PeriphClockCmd(RCC_APB2Periph_ADC2, ENABLE);//enable ADC2 clock + + GPIO_InitStructure.GPIO_Pin = ADC2_GPIO; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AN;//analog input + GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL; + GPIO_Init(GPIOx, &GPIO_InitStructure); + + RCC_APB2PeriphResetCmd(RCC_APB2Periph_ADC2, ENABLE); + RCC_APB2PeriphResetCmd(RCC_APB2Periph_ADC2, DISABLE); + + ADC_CommonInitStructure.ADC_Mode = ADC_Mode_Independent; + ADC_CommonInitStructure.ADC_TwoSamplingDelay = ADC_TwoSamplingDelay_5Cycles; + ADC_CommonInitStructure.ADC_DMAAccessMode = ADC_DMAAccessMode_Disabled; + ADC_CommonInitStructure.ADC_Prescaler = ADC_Prescaler_Div4; + ADC_CommonInit(&ADC_CommonInitStructure); + + ADC_InitStructure.ADC_Resolution = ADC_Resolution_12b;//12 bit mode + ADC_InitStructure.ADC_ScanConvMode = DISABLE; + ADC_InitStructure.ADC_ContinuousConvMode = DISABLE; + ADC_InitStructure.ADC_ExternalTrigConvEdge = ADC_ExternalTrigConvEdge_None; + ADC_InitStructure.ADC_DataAlign = ADC_DataAlign_Right; + ADC_InitStructure.ADC_NbrOfConversion = 1; + ADC_Init(ADC2, &ADC_InitStructure); + + ADC_Cmd(ADC2, ENABLE); + } +#endif + +#ifdef BSP_USING_ADC3 + if (0 == strncmp(adc_dev->haldev.dev_name, ADC3_DEVICE_NAME, NAME_NUM_MAX)) { + + GPIOx = AdcGetGpioType(ADC3_GPIO_DEF); + RCC_AHB1Periph = AdcGetGpioRcc(ADC3_GPIO_DEF); + + RCC_AHB1PeriphClockCmd(RCC_AHB1Periph, ENABLE);//enable GPIOA clock + RCC_APB2PeriphClockCmd(RCC_APB2Periph_ADC3, ENABLE);//enable ADC3 clock + + GPIO_InitStructure.GPIO_Pin = ADC3_GPIO; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AN;//analog input + GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL; + GPIO_Init(GPIOx, &GPIO_InitStructure); + + RCC_APB2PeriphResetCmd(RCC_APB2Periph_ADC3, ENABLE); + RCC_APB2PeriphResetCmd(RCC_APB2Periph_ADC3, DISABLE); + + ADC_CommonInitStructure.ADC_Mode = ADC_Mode_Independent; + ADC_CommonInitStructure.ADC_TwoSamplingDelay = ADC_TwoSamplingDelay_5Cycles; + ADC_CommonInitStructure.ADC_DMAAccessMode = ADC_DMAAccessMode_Disabled; + ADC_CommonInitStructure.ADC_Prescaler = ADC_Prescaler_Div4; + ADC_CommonInit(&ADC_CommonInitStructure); + + ADC_InitStructure.ADC_Resolution = ADC_Resolution_12b;//12 bit mode + ADC_InitStructure.ADC_ScanConvMode = DISABLE; + ADC_InitStructure.ADC_ContinuousConvMode = DISABLE; + ADC_InitStructure.ADC_ExternalTrigConvEdge = ADC_ExternalTrigConvEdge_None; + ADC_InitStructure.ADC_DataAlign = ADC_DataAlign_Right; + ADC_InitStructure.ADC_NbrOfConversion = 1; + ADC_Init(ADC3, &ADC_InitStructure); + + ADC_Cmd(ADC3, ENABLE); + } +#endif +} + +static uint16 GetAdcValue(ADC_TypeDef *ADCx, uint8 channel) +{ + //set ADCx channel, rank, sampletime + ADC_RegularChannelConfig(ADCx, channel, 1, ADC_SampleTime_480Cycles); + + ADC_SoftwareStartConv(ADCx); + + while(!ADC_GetFlagStatus(ADCx, ADC_FLAG_EOC)); + + return ADC_GetConversionValue(ADCx); +} + +static uint16 GetAdcAverageValue(ADC_TypeDef *ADCx, uint8 channel, uint8 times) +{ + uint32 temp_val = 0; + int i; + + for(i = 0;i < times;i ++) { + temp_val += GetAdcValue(ADCx, channel) & 0x0FFF; + KPrintf("GetAdcAverageValue val %u\n", GetAdcValue(ADCx, channel)); + Stm32AdcUdelay(5000); + } + return temp_val / times; +} + +static uint32 Stm32AdcOpen(void *dev) +{ + struct AdcHardwareDevice *adc_dev = (struct AdcHardwareDevice *)dev; + + AdcInit(adc_dev); + + return EOK; +} + +static uint32 Stm32AdcClose(void *dev) +{ + struct AdcHardwareDevice *adc_dev = (struct AdcHardwareDevice *)dev; + + ADC_DeInit(); + + return EOK; +} + +static uint32 Stm32AdcRead(void *dev, struct BusBlockReadParam *read_param) +{ + struct AdcHardwareDevice *adc_dev = (struct AdcHardwareDevice *)dev; + struct Stm32HwAdc *adc_cfg = (struct Stm32HwAdc *)adc_dev->haldev.private_data; + + uint16 adc_average_value = 0; + uint8 times = 20; + + adc_average_value = GetAdcAverageValue(adc_cfg->ADCx, adc_cfg->adc_channel, times); + + *(uint16 *)read_param->buffer = adc_average_value; + read_param->read_length = 2; + + return read_param->read_length; +} + +static uint32 Stm32AdcDrvConfigure(void *drv, struct BusConfigureInfo *configure_info) +{ + NULL_PARAM_CHECK(drv); + NULL_PARAM_CHECK(configure_info); + + x_err_t ret = EOK; + uint8 adc_channel; + + struct AdcDriver *adc_drv = (struct AdcDriver *)drv; + struct AdcHardwareDevice *adc_dev = (struct AdcHardwareDevice *)adc_drv->driver.owner_bus->owner_haldev; + struct Stm32HwAdc *adc_cfg = (struct Stm32HwAdc *)adc_dev->haldev.private_data; + + switch (configure_info->configure_cmd) + { + case OPE_CFG: + adc_cfg->adc_channel = *(uint8 *)configure_info->private_data; + if (adc_cfg->adc_channel > 18) { + KPrintf("Stm32AdcDrvConfigure set adc channel(0-18) %u error!", adc_cfg->adc_channel); + adc_cfg->adc_channel = 0; + ret = ERROR; + } + break; + default: + break; + } + + return ret; +} + +static const struct AdcDevDone dev_done = +{ + Stm32AdcOpen, + Stm32AdcClose, + NONE, + Stm32AdcRead, +}; + +int Stm32HwAdcInit(void) +{ + x_err_t ret = EOK; + +#ifdef BSP_USING_ADC1 + static struct AdcBus adc1_bus; + static struct AdcDriver adc1_drv; + static struct AdcHardwareDevice adc1_dev; + static struct Stm32HwAdc adc1_cfg; + + adc1_drv.configure = Stm32AdcDrvConfigure; + + ret = AdcBusInit(&adc1_bus, ADC1_BUS_NAME); + if (ret != EOK) { + KPrintf("ADC1 bus init error %d\n", ret); + return ERROR; + } + + ret = AdcDriverInit(&adc1_drv, ADC1_DRIVER_NAME); + if (ret != EOK) { + KPrintf("ADC1 driver init error %d\n", ret); + return ERROR; + } + ret = AdcDriverAttachToBus(ADC1_DRIVER_NAME, ADC1_BUS_NAME); + if (ret != EOK) { + KPrintf("ADC1 driver attach error %d\n", ret); + return ERROR; + } + + adc1_dev.adc_dev_done = &dev_done; + adc1_cfg.ADCx = ADC1; + adc1_cfg.adc_channel = 0; + + ret = AdcDeviceRegister(&adc1_dev, (void *)&adc1_cfg, ADC1_DEVICE_NAME); + if (ret != EOK) { + KPrintf("ADC1 device register error %d\n", ret); + return ERROR; + } + ret = AdcDeviceAttachToBus(ADC1_DEVICE_NAME, ADC1_BUS_NAME); + if (ret != EOK) { + KPrintf("ADC1 device register error %d\n", ret); + return ERROR; + } +#endif + +#ifdef BSP_USING_ADC2 + static struct AdcBus adc2_bus; + static struct AdcDriver adc2_drv; + static struct AdcHardwareDevice adc2_dev; + static struct Stm32HwAdc adc2_cfg; + + adc2_drv.configure = Stm32AdcDrvConfigure; + + ret = AdcBusInit(&adc2_bus, ADC2_BUS_NAME); + if (ret != EOK) { + KPrintf("ADC2 bus init error %d\n", ret); + return ERROR; + } + + ret = AdcDriverInit(&adc2_drv, ADC2_DRIVER_NAME); + if (ret != EOK) { + KPrintf("ADC2 driver init error %d\n", ret); + return ERROR; + } + ret = AdcDriverAttachToBus(ADC2_DRIVER_NAME, ADC2_BUS_NAME); + if (ret != EOK) { + KPrintf("ADC2 driver attach error %d\n", ret); + return ERROR; + } + + adc2_dev.adc_dev_done = &dev_done; + adc2_cfg.ADCx = ADC2; + adc2_cfg.adc_channel = 0; + + ret = AdcDeviceRegister(&adc2_dev, (void *)&adc2_cfg, ADC2_DEVICE_NAME); + if (ret != EOK) { + KPrintf("ADC2 device register error %d\n", ret); + return ERROR; + } + ret = AdcDeviceAttachToBus(ADC2_DEVICE_NAME, ADC2_BUS_NAME); + if (ret != EOK) { + KPrintf("ADC2 device register error %d\n", ret); + return ERROR; + } +#endif + +#ifdef BSP_USING_ADC3 + static struct AdcBus adc3_bus; + static struct AdcDriver adc3_drv; + static struct AdcHardwareDevice adc3_dev; + static struct Stm32HwAdc adc3_cfg; + + adc3_drv.configure = Stm32AdcDrvConfigure; + + ret = AdcBusInit(&adc3_bus, ADC3_BUS_NAME); + if (ret != EOK) { + KPrintf("ADC3 bus init error %d\n", ret); + return ERROR; + } + + ret = AdcDriverInit(&adc3_drv, ADC3_DRIVER_NAME); + if (ret != EOK) { + KPrintf("ADC3 driver init error %d\n", ret); + return ERROR; + } + ret = AdcDriverAttachToBus(ADC3_DRIVER_NAME, ADC3_BUS_NAME); + if (ret != EOK) { + KPrintf("ADC3 driver attach error %d\n", ret); + return ERROR; + } + + adc3_dev.adc_dev_done = &dev_done; + adc3_cfg.ADCx = ADC3; + adc3_cfg.adc_channel = 0; + + ret = AdcDeviceRegister(&adc3_dev, (void *)&adc3_cfg, ADC3_DEVICE_NAME); + if (ret != EOK) { + KPrintf("ADC3 device register error %d\n", ret); + return ERROR; + } + ret = AdcDeviceAttachToBus(ADC3_DEVICE_NAME, ADC3_BUS_NAME); + if (ret != EOK) { + KPrintf("ADC3 device register error %d\n", ret); + return ERROR; + } +#endif + + return ret; +} diff --git a/Ubiquitous/XiZi/board/aiit-arm32-board/third_party_driver/can/Kconfig b/Ubiquitous/XiZi/board/aiit-arm32-board/third_party_driver/can/Kconfig new file mode 100644 index 0000000..34fb7d2 --- /dev/null +++ b/Ubiquitous/XiZi/board/aiit-arm32-board/third_party_driver/can/Kconfig @@ -0,0 +1,11 @@ +config CAN_BUS_NAME_1 + string "can bus name" + default "can1" + +config CAN_DRIVER_NAME + string "can driver name" + default "can1_drv" + +config CAN_1_DEVICE_NAME_1 + string "can bus 1 device 1 name" + default "can1_dev1" \ No newline at end of file diff --git a/Ubiquitous/XiZi/board/aiit-arm32-board/third_party_driver/can/Makefile b/Ubiquitous/XiZi/board/aiit-arm32-board/third_party_driver/can/Makefile new file mode 100644 index 0000000..58de4cd --- /dev/null +++ b/Ubiquitous/XiZi/board/aiit-arm32-board/third_party_driver/can/Makefile @@ -0,0 +1,4 @@ +SRC_FILES := hardware_can.c connect_can.c + + +include $(KERNEL_ROOT)/compiler.mk \ No newline at end of file diff --git a/Ubiquitous/XiZi/board/aiit-arm32-board/third_party_driver/ch438/Kconfig b/Ubiquitous/XiZi/board/aiit-arm32-board/third_party_driver/ch438/Kconfig new file mode 100644 index 0000000..389b675 --- /dev/null +++ b/Ubiquitous/XiZi/board/aiit-arm32-board/third_party_driver/ch438/Kconfig @@ -0,0 +1,39 @@ +config CH438_BUS_NAME + string + default "extuart" + +config CH438_DRIVER_NAME + string + default "extuart_drv" + +config CH438_DEVICE_NAME_0 + string + default "extuart_dev0" + +config CH438_DEVICE_NAME_1 + string + default "extuart_dev1" + +config CH438_DEVICE_NAME_2 + string + default "extuart_dev2" + +config CH438_DEVICE_NAME_3 + string + default "extuart_dev3" + +config CH438_DEVICE_NAME_4 + string + default "extuart_dev4" + +config CH438_DEVICE_NAME_5 + string + default "extuart_dev5" + +config CH438_DEVICE_NAME_6 + string + default "extuart_dev6" + +config CH438_DEVICE_NAME_7 + string + default "extuart_dev7" diff --git a/Ubiquitous/XiZi/board/aiit-arm32-board/third_party_driver/ch438/Makefile b/Ubiquitous/XiZi/board/aiit-arm32-board/third_party_driver/ch438/Makefile new file mode 100644 index 0000000..4796857 --- /dev/null +++ b/Ubiquitous/XiZi/board/aiit-arm32-board/third_party_driver/ch438/Makefile @@ -0,0 +1,4 @@ +SRC_FILES := connect_ch438.c + + +include $(KERNEL_ROOT)/compiler.mk diff --git a/Ubiquitous/XiZi/board/aiit-arm32-board/third_party_driver/ch438/connect_ch438.c b/Ubiquitous/XiZi/board/aiit-arm32-board/third_party_driver/ch438/connect_ch438.c new file mode 100644 index 0000000..76288f4 --- /dev/null +++ b/Ubiquitous/XiZi/board/aiit-arm32-board/third_party_driver/ch438/connect_ch438.c @@ -0,0 +1,1403 @@ +/* +* Copyright (c) 2020 AIIT XUOS Lab +* XiUOS is licensed under Mulan PSL v2. +* You can use this software according to the terms and conditions of the Mulan PSL v2. +* You may obtain a copy of Mulan PSL v2 at: +* http://license.coscl.org.cn/MulanPSL2 +* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, +* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, +* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. +* See the Mulan PSL v2 for more details. +*/ + +/** +* @file connect_ch438.c +* @brief support to register ch438 pointer and function +* @version 1.0 +* @author AIIT XUOS Lab +* @date 2021-04-24 +*/ + +#include + +static const uint8 offset_addr[] = {0x00,0x10,0x20,0x30,0x08,0x18,0x28,0x38,}; /* uart offset address*/ +static const uint8 interrupt_num[8] = {0x01,0x02,0x04,0x08,0x10,0x20,0x40,0x80,}; /* SSR register data*/ +static BusType ch438_pin; +static int ch438_sem = NONE; + +static void Ch438Irq(void *parameter) +{ + KSemaphoreAbandon(ch438_sem); +} + +/** + * The time delay function. + * + * @param microseconds. + */ +static void Stm32Udelay(uint32 us) +{ + uint32 ticks; + uint32 told, tnow, tcnt = 0; + uint32 reload = SysTick->LOAD; + + ticks = us * reload / (1000000 / TICK_PER_SECOND); + told = SysTick->VAL; + while (1) { + tnow = SysTick->VAL; + if (tnow != told) { + if (tnow < told) { + tcnt += told - tnow; + } else { + tcnt += reload - tnow + told; + } + + told = tnow; + if (tcnt >= ticks) { + break; + } + } + } +} + +void CH438SetOutput(void) +{ + struct PinParam pin_cfg; + int ret = 0; + + struct BusConfigureInfo configure_info; + configure_info.configure_cmd = OPE_CFG; + configure_info.private_data = (void *)&pin_cfg; + + pin_cfg.cmd = GPIO_CONFIG_MODE; + pin_cfg.pin = CH438_D0_PIN; + pin_cfg.mode = GPIO_CFG_OUTPUT; + + ret = BusDrvConfigure(ch438_pin->owner_driver, &configure_info); + if (ret != EOK) { + KPrintf("config CH438_D0_PIN pin %d failed!\n", CH438_D0_PIN); + return ; + } + + pin_cfg.pin = CH438_D1_PIN; + ret = BusDrvConfigure(ch438_pin->owner_driver, &configure_info); + if (ret != EOK) { + KPrintf("config CH438_D1_PIN pin %d failed!\n", CH438_D1_PIN); + return ; + } + + pin_cfg.pin = CH438_D2_PIN; + ret = BusDrvConfigure(ch438_pin->owner_driver, &configure_info); + if (ret != EOK) { + KPrintf("config CH438_D2_PIN pin %d failed!\n", CH438_D2_PIN); + return ; + } + + pin_cfg.pin = CH438_D3_PIN; + ret = BusDrvConfigure(ch438_pin->owner_driver, &configure_info); + if (ret != EOK) { + KPrintf("config CH438_D3_PIN pin %d failed!\n", CH438_D3_PIN); + return ; + } + + pin_cfg.pin = CH438_D4_PIN; + ret = BusDrvConfigure(ch438_pin->owner_driver, &configure_info); + if (ret != EOK) { + KPrintf("config CH438_D4_PIN pin %d failed!\n", CH438_D4_PIN); + return ; + } + + pin_cfg.pin = CH438_D5_PIN; + ret = BusDrvConfigure(ch438_pin->owner_driver, &configure_info); + if (ret != EOK) { + KPrintf("config CH438_D5_PIN pin %d failed!\n", CH438_D5_PIN); + return ; + } + + pin_cfg.pin = CH438_D6_PIN; + ret = BusDrvConfigure(ch438_pin->owner_driver, &configure_info); + if (ret != EOK) { + KPrintf("config CH438_D6_PIN pin %d failed!\n", CH438_D6_PIN); + return ; + } + + pin_cfg.pin = CH438_D7_PIN; + ret = BusDrvConfigure(ch438_pin->owner_driver, &configure_info); + if (ret != EOK) { + KPrintf("config CH438_D7_PIN pin %d failed!\n", CH438_D7_PIN); + return ; + } +} + +void CH438SetInput(void) +{ + struct PinParam pin_cfg; + int ret = 0; + + struct BusConfigureInfo configure_info; + configure_info.configure_cmd = OPE_CFG; + configure_info.private_data = (void *)&pin_cfg; + + pin_cfg.cmd = GPIO_CONFIG_MODE; + pin_cfg.pin = CH438_D0_PIN; + pin_cfg.mode = GPIO_CFG_INPUT_PULLUP; + ret = BusDrvConfigure(ch438_pin->owner_driver, &configure_info); + if (ret != EOK) { + KPrintf("config CH438_D0_PIN pin %d INPUT_PULLUP failed!\n", CH438_D0_PIN); + return ; + } + + pin_cfg.pin = CH438_D1_PIN; + ret = BusDrvConfigure(ch438_pin->owner_driver, &configure_info); + if (ret != EOK) { + KPrintf("config CH438_D1_PIN pin %d INPUT_PULLUP failed!\n", CH438_D1_PIN); + return ; + } + + pin_cfg.pin = CH438_D2_PIN; + ret = BusDrvConfigure(ch438_pin->owner_driver, &configure_info); + if (ret != EOK) { + KPrintf("config CH438_D2_PIN pin %d INPUT_PULLUP failed!\n", CH438_D2_PIN); + return ; + } + + pin_cfg.pin = CH438_D3_PIN; + ret = BusDrvConfigure(ch438_pin->owner_driver, &configure_info); + if (ret != EOK) { + KPrintf("config CH438_D3_PIN pin %d INPUT_PULLUP failed!\n", CH438_D3_PIN); + return ; + } + + pin_cfg.pin = CH438_D4_PIN; + ret = BusDrvConfigure(ch438_pin->owner_driver, &configure_info); + if (ret != EOK) { + KPrintf("config CH438_D4_PIN pin %d INPUT_PULLUP failed!\n", CH438_D4_PIN); + return ; + } + + pin_cfg.pin = CH438_D5_PIN; + ret = BusDrvConfigure(ch438_pin->owner_driver, &configure_info); + if (ret != EOK) { + KPrintf("config CH438_D5_PIN pin %d INPUT_PULLUP failed!\n", CH438_D5_PIN); + return ; + } + + pin_cfg.pin = CH438_D6_PIN; + ret = BusDrvConfigure(ch438_pin->owner_driver, &configure_info); + if (ret != EOK) { + KPrintf("config CH438_D6_PIN pin %d INPUT_PULLUP failed!\n", CH438_D6_PIN); + return ; + } + + pin_cfg.pin = CH438_D7_PIN; + ret = BusDrvConfigure(ch438_pin->owner_driver, &configure_info); + if (ret != EOK) { + KPrintf("config CH438_D7_PIN pin %d INPUT_PULLUP failed!\n", CH438_D7_PIN); + return ; + } +} + +/********************************************************************************************************* +** Function name: ReadCH438Data +** Function: read data from CH438 +** input: address +** +** output: data +** +** date: 2011.8.26 +**------------------------------------------------------------------------------------------------------- +** modify: +** date: +**------------------------------------------------------------------------------------------------------- +********************************************************************************************************/ +uint8 ReadCH438Data( uint8 addr ) +{ +//read data api + +//ALE WR RD is high level when not busy, when reading data, put address on the serial port and put ALE low level for a few clock + +//switch input pin, put RD low level, delay a few clock, read the data from the serial port + +//put RD and ALE high level + uint8 dat; + struct PinStat pin_stat; + struct BusBlockWriteParam write_param; + struct BusBlockReadParam read_param; + write_param.buffer = (void *)&pin_stat; + read_param.buffer = (void *)&pin_stat; + + pin_stat.val = GPIO_HIGH; + + pin_stat.pin = CH438_NWR_PIN; + BusDevWriteData(ch438_pin->owner_haldev, &write_param); + + pin_stat.pin = CH438_NRD_PIN; + BusDevWriteData(ch438_pin->owner_haldev, &write_param); + + pin_stat.pin = CH438_ALE_PIN; + BusDevWriteData(ch438_pin->owner_haldev, &write_param); + + CH438SetOutput(); + Stm32Udelay(1); + + if (addr &0x80) { + pin_stat.val = GPIO_HIGH; + pin_stat.pin = CH438_D7_PIN; + BusDevWriteData(ch438_pin->owner_haldev, &write_param); + } else { + pin_stat.val = GPIO_LOW; + pin_stat.pin = CH438_D7_PIN; + BusDevWriteData(ch438_pin->owner_haldev, &write_param); + } + + if (addr &0x40) { + pin_stat.val = GPIO_HIGH; + pin_stat.pin = CH438_D6_PIN; + BusDevWriteData(ch438_pin->owner_haldev, &write_param); + } else { + pin_stat.val = GPIO_LOW; + pin_stat.pin = CH438_D6_PIN; + BusDevWriteData(ch438_pin->owner_haldev, &write_param); + } + + if (addr &0x20) { + pin_stat.val = GPIO_HIGH; + pin_stat.pin = CH438_D5_PIN; + BusDevWriteData(ch438_pin->owner_haldev, &write_param); + } else { + pin_stat.val = GPIO_LOW; + pin_stat.pin = CH438_D5_PIN; + BusDevWriteData(ch438_pin->owner_haldev, &write_param); + } + + if (addr &0x10) { + pin_stat.val = GPIO_HIGH; + pin_stat.pin = CH438_D4_PIN; + BusDevWriteData(ch438_pin->owner_haldev, &write_param); + } else { + pin_stat.val = GPIO_LOW; + pin_stat.pin = CH438_D4_PIN; + BusDevWriteData(ch438_pin->owner_haldev, &write_param); + } + + if (addr &0x08) { + pin_stat.val = GPIO_HIGH; + pin_stat.pin = CH438_D3_PIN; + BusDevWriteData(ch438_pin->owner_haldev, &write_param); + } else { + pin_stat.val = GPIO_LOW; + pin_stat.pin = CH438_D3_PIN; + BusDevWriteData(ch438_pin->owner_haldev, &write_param); + } + + if (addr &0x04) { + pin_stat.val = GPIO_HIGH; + pin_stat.pin = CH438_D2_PIN; + BusDevWriteData(ch438_pin->owner_haldev, &write_param); + } else { + pin_stat.val = GPIO_LOW; + pin_stat.pin = CH438_D2_PIN; + BusDevWriteData(ch438_pin->owner_haldev, &write_param); + } + + if (addr &0x02) { + pin_stat.val = GPIO_HIGH; + pin_stat.pin = CH438_D1_PIN; + BusDevWriteData(ch438_pin->owner_haldev, &write_param); + } else { + pin_stat.val = GPIO_LOW; + pin_stat.pin = CH438_D1_PIN; + BusDevWriteData(ch438_pin->owner_haldev, &write_param); + } + + if (addr &0x01) { + pin_stat.val = GPIO_HIGH; + pin_stat.pin = CH438_D0_PIN; + BusDevWriteData(ch438_pin->owner_haldev, &write_param); + } else { + pin_stat.val = GPIO_LOW; + pin_stat.pin = CH438_D0_PIN; + BusDevWriteData(ch438_pin->owner_haldev, &write_param); + } + + Stm32Udelay(1); + + pin_stat.val = GPIO_LOW; + pin_stat.pin = CH438_ALE_PIN; + BusDevWriteData(ch438_pin->owner_haldev, &write_param); + + Stm32Udelay(1); + + CH438SetInput(); + Stm32Udelay(1); + + pin_stat.val = GPIO_LOW; + pin_stat.pin = CH438_NRD_PIN; + BusDevWriteData(ch438_pin->owner_haldev, &write_param); + + Stm32Udelay(1); + + dat = 0; + + pin_stat.pin = CH438_D7_PIN; + if(BusDevReadData(ch438_pin->owner_haldev, &read_param)) + dat |= 0x80; + + pin_stat.pin = CH438_D6_PIN; + if (BusDevReadData(ch438_pin->owner_haldev, &read_param)) + dat |= 0x40; + + pin_stat.pin = CH438_D5_PIN; + if (BusDevReadData(ch438_pin->owner_haldev, &read_param)) + dat |= 0x20; + + pin_stat.pin = CH438_D4_PIN; + if (BusDevReadData(ch438_pin->owner_haldev, &read_param)) + dat |= 0x10; + + pin_stat.pin = CH438_D3_PIN; + if (BusDevReadData(ch438_pin->owner_haldev, &read_param)) + dat |= 0x08; + + pin_stat.pin = CH438_D2_PIN; + if (BusDevReadData(ch438_pin->owner_haldev, &read_param)) + dat |= 0x04; + + pin_stat.pin = CH438_D1_PIN; + if (BusDevReadData(ch438_pin->owner_haldev, &read_param)) + dat |= 0x02; + + pin_stat.pin = CH438_D0_PIN; + if (BusDevReadData(ch438_pin->owner_haldev, &read_param)) + dat |= 0x01; + + pin_stat.val = GPIO_HIGH; + pin_stat.pin = CH438_NRD_PIN; + BusDevWriteData(ch438_pin->owner_haldev, &write_param); + + pin_stat.val = GPIO_HIGH; + pin_stat.pin = CH438_ALE_PIN; + BusDevWriteData(ch438_pin->owner_haldev, &write_param); + + Stm32Udelay(1); + + return dat; +} + +void WriteCH438Data(uint8 addr, uint8 dat) +{ + struct PinStat pin_stat; + struct BusBlockWriteParam write_param; + write_param.buffer = (void *)&pin_stat; + + pin_stat.val = GPIO_HIGH; + pin_stat.pin = CH438_ALE_PIN; + BusDevWriteData(ch438_pin->owner_haldev, &write_param); + + pin_stat.val = GPIO_HIGH; + pin_stat.pin = CH438_NRD_PIN; + BusDevWriteData(ch438_pin->owner_haldev, &write_param); + + pin_stat.val = GPIO_HIGH; + pin_stat.pin = CH438_NWR_PIN; + BusDevWriteData(ch438_pin->owner_haldev, &write_param); + + CH438SetOutput(); + Stm32Udelay(1); + + if (addr &0x80) { + pin_stat.val = GPIO_HIGH; + pin_stat.pin = CH438_D7_PIN; + BusDevWriteData(ch438_pin->owner_haldev, &write_param); + } else { + pin_stat.val = GPIO_LOW; + pin_stat.pin = CH438_D7_PIN; + BusDevWriteData(ch438_pin->owner_haldev, &write_param); + } + + if (addr &0x40) { + pin_stat.val = GPIO_HIGH; + pin_stat.pin = CH438_D6_PIN; + BusDevWriteData(ch438_pin->owner_haldev, &write_param); + } else { + pin_stat.val = GPIO_LOW; + pin_stat.pin = CH438_D6_PIN; + BusDevWriteData(ch438_pin->owner_haldev, &write_param); + } + + if (addr &0x20) { + pin_stat.val = GPIO_HIGH; + pin_stat.pin = CH438_D5_PIN; + BusDevWriteData(ch438_pin->owner_haldev, &write_param); + } else { + pin_stat.val = GPIO_LOW; + pin_stat.pin = CH438_D5_PIN; + BusDevWriteData(ch438_pin->owner_haldev, &write_param); + } + + if (addr &0x10) { + pin_stat.val = GPIO_HIGH; + pin_stat.pin = CH438_D4_PIN; + BusDevWriteData(ch438_pin->owner_haldev, &write_param); + } else { + pin_stat.val = GPIO_LOW; + pin_stat.pin = CH438_D4_PIN; + BusDevWriteData(ch438_pin->owner_haldev, &write_param); + } + + if (addr &0x08) { + pin_stat.val = GPIO_HIGH; + pin_stat.pin = CH438_D3_PIN; + BusDevWriteData(ch438_pin->owner_haldev, &write_param); + } else { + pin_stat.val = GPIO_LOW; + pin_stat.pin = CH438_D3_PIN; + BusDevWriteData(ch438_pin->owner_haldev, &write_param); + } + + if (addr &0x04) { + pin_stat.val = GPIO_HIGH; + pin_stat.pin = CH438_D2_PIN; + BusDevWriteData(ch438_pin->owner_haldev, &write_param); + } else { + pin_stat.val = GPIO_LOW; + pin_stat.pin = CH438_D2_PIN; + BusDevWriteData(ch438_pin->owner_haldev, &write_param); + } + + if (addr &0x02) { + pin_stat.val = GPIO_HIGH; + pin_stat.pin = CH438_D1_PIN; + BusDevWriteData(ch438_pin->owner_haldev, &write_param); + } else { + pin_stat.val = GPIO_LOW; + pin_stat.pin = CH438_D1_PIN; + BusDevWriteData(ch438_pin->owner_haldev, &write_param); + } + + if (addr &0x01) { + pin_stat.val = GPIO_HIGH; + pin_stat.pin = CH438_D0_PIN; + BusDevWriteData(ch438_pin->owner_haldev, &write_param); + } else { + pin_stat.val = GPIO_LOW; + pin_stat.pin = CH438_D0_PIN; + BusDevWriteData(ch438_pin->owner_haldev, &write_param); + } + + Stm32Udelay(1); + + pin_stat.val = GPIO_LOW; + pin_stat.pin = CH438_ALE_PIN; + BusDevWriteData(ch438_pin->owner_haldev, &write_param); + + Stm32Udelay(1); + + if (dat &0x80) { + pin_stat.val = GPIO_HIGH; + pin_stat.pin = CH438_D7_PIN; + BusDevWriteData(ch438_pin->owner_haldev, &write_param); + } else { + pin_stat.val = GPIO_LOW; + pin_stat.pin = CH438_D7_PIN; + BusDevWriteData(ch438_pin->owner_haldev, &write_param); + } + + if (dat &0x40) { + pin_stat.val = GPIO_HIGH; + pin_stat.pin = CH438_D6_PIN; + BusDevWriteData(ch438_pin->owner_haldev, &write_param); + } else { + pin_stat.val = GPIO_LOW; + pin_stat.pin = CH438_D6_PIN; + BusDevWriteData(ch438_pin->owner_haldev, &write_param); + } + + if (dat &0x20) { + pin_stat.val = GPIO_HIGH; + pin_stat.pin = CH438_D5_PIN; + BusDevWriteData(ch438_pin->owner_haldev, &write_param); + } else { + pin_stat.val = GPIO_LOW; + pin_stat.pin = CH438_D5_PIN; + BusDevWriteData(ch438_pin->owner_haldev, &write_param); + } + + if (dat &0x10) { + pin_stat.val = GPIO_HIGH; + pin_stat.pin = CH438_D4_PIN; + BusDevWriteData(ch438_pin->owner_haldev, &write_param); + } else { + pin_stat.val = GPIO_LOW; + pin_stat.pin = CH438_D4_PIN; + BusDevWriteData(ch438_pin->owner_haldev, &write_param); + } + + if (dat &0x08) { + pin_stat.val = GPIO_HIGH; + pin_stat.pin = CH438_D3_PIN; + BusDevWriteData(ch438_pin->owner_haldev, &write_param); + } else { + pin_stat.val = GPIO_LOW; + pin_stat.pin = CH438_D3_PIN; + BusDevWriteData(ch438_pin->owner_haldev, &write_param); + } + + if (dat &0x04) { + pin_stat.val = GPIO_HIGH; + pin_stat.pin = CH438_D2_PIN; + BusDevWriteData(ch438_pin->owner_haldev, &write_param); + } else { + pin_stat.val = GPIO_LOW; + pin_stat.pin = CH438_D2_PIN; + BusDevWriteData(ch438_pin->owner_haldev, &write_param); + } + + if (dat &0x02) { + pin_stat.val = GPIO_HIGH; + pin_stat.pin = CH438_D1_PIN; + BusDevWriteData(ch438_pin->owner_haldev, &write_param); + } else { + pin_stat.val = GPIO_LOW; + pin_stat.pin = CH438_D1_PIN; + BusDevWriteData(ch438_pin->owner_haldev, &write_param); + } + + if (dat &0x01) { + pin_stat.val = GPIO_HIGH; + pin_stat.pin = CH438_D0_PIN; + BusDevWriteData(ch438_pin->owner_haldev, &write_param); + } else { + pin_stat.val = GPIO_LOW; + pin_stat.pin = CH438_D0_PIN; + BusDevWriteData(ch438_pin->owner_haldev, &write_param); + } + + Stm32Udelay(1); + + pin_stat.val = GPIO_LOW; + pin_stat.pin = CH438_NWR_PIN; + BusDevWriteData(ch438_pin->owner_haldev, &write_param); + + Stm32Udelay(1); + + pin_stat.val = GPIO_HIGH; + pin_stat.pin = CH438_NWR_PIN; + BusDevWriteData(ch438_pin->owner_haldev, &write_param); + + pin_stat.val = GPIO_HIGH; + pin_stat.pin = CH438_ALE_PIN; + BusDevWriteData(ch438_pin->owner_haldev, &write_param); + + Stm32Udelay(1); + + CH438SetInput(); + + return; +} + +/********************************************************************************************************* +** Function name: WriteCH438Block +** Function: write data to CH438 +** input: CH438 register address, data block length, data cache address +** +** output: +** +** date: 2011.8.26 +**------------------------------------------------------------------------------------------------------- +** modify: +** date: +**------------------------------------------------------------------------------------------------------- +********************************************************************************************************/ +void WriteCH438Block(uint8 maddr, uint8 mlen, uint8 *mbuf) +{ + while (mlen--) { + WriteCH438Data(maddr, *mbuf++); + } +} + +/********************************************************************************************************* +** Function name: Ch438UartSend +** Function: active FIFO mode, CH438 send multibyte data by uart 0, max length is 128 bytes a single time +** input: send data cache address, send data length +** +** output: +** +** date: 2011.8.26. +**------------------------------------------------------------------------------------------------------- +** modify: +** date: +**------------------------------------------------------------------------------------------------------- +********************************************************************************************************/ +void Ch438UartSend( uint8 ext_uart_no,uint8 *data, uint8 Num ) +{ + uint8 REG_LSR_ADDR,REG_THR_ADDR; + + REG_LSR_ADDR = offset_addr[ext_uart_no] | REG_LSR0_ADDR; + REG_THR_ADDR = offset_addr[ext_uart_no] | REG_THR0_ADDR; + + while (1) { + while((ReadCH438Data(REG_LSR_ADDR) & BIT_LSR_TEMT) == 0); /* wait for sending data done, THR and TSR is NULL */ + + if (Num <= 128) { + WriteCH438Block(REG_THR_ADDR, Num, data); + break; + } else { + WriteCH438Block(REG_THR_ADDR, 128, data); + Num -= 128; + data += 128; + } + } +} + +/********************************************************************************************************* +** Function name: Ch438UartRcv +** Function: forbidden FIFO mode, CH438 receive multibyte data from uart 0 +** input: recv data address +** +** output: recv data length +** +** date: 2011.8.26 +**------------------------------------------------------------------------------------------------------- +** modify: +** date: +**------------------------------------------------------------------------------------------------------- +********************************************************************************************************/ +uint8 Ch438UartRcv(uint8 ext_uart_no, uint8 *buf, x_size_t size) +{ + uint8 rcv_num = 0; + uint8 dat = 0; + uint8 REG_LSR_ADDR,REG_RBR_ADDR; + uint8 *read_buffer; + x_size_t buffer_index = 0; + + read_buffer = buf; + + REG_LSR_ADDR = offset_addr[ext_uart_no] | REG_LSR0_ADDR; + REG_RBR_ADDR = offset_addr[ext_uart_no] | REG_RBR0_ADDR; + + while ((ReadCH438Data(REG_LSR_ADDR) & BIT_LSR_DATARDY) == 0); /* wait for data is ready */ + + while (((ReadCH438Data(REG_LSR_ADDR) & BIT_LSR_DATARDY) == 0x01) && (size != 0)) { + dat = ReadCH438Data(REG_RBR_ADDR); + + *read_buffer = dat; + read_buffer++; + buffer_index++; + + if (CH438_BUFFSIZE == buffer_index) { + buffer_index = 0; + read_buffer = buf; + } + + rcv_num = rcv_num + 1; + --size; + } + + return rcv_num; +} + +static void Timeout438Proc(void *parameter) +{ + uint8_t rbr,lsr; + + while( ( ReadCH438Data( REG_LSR0_ADDR ) & BIT_LSR_DATARDY ) == 0x01 ) { + rbr = ReadCH438Data( REG_RBR0_ADDR ); + KPrintf("0.RBR=%02x\r\n",rbr); + } + + while( ( ReadCH438Data( REG_LSR1_ADDR ) & BIT_LSR_DATARDY ) == 0x01 ) { + rbr = ReadCH438Data( REG_RBR1_ADDR ); + KPrintf("1.RBR=%02x\r\n",rbr); + } + + while( ( ReadCH438Data( REG_LSR2_ADDR ) & BIT_LSR_DATARDY ) == 0x01 ) { + rbr = ReadCH438Data( REG_RBR2_ADDR ); + KPrintf("2.RBR=%02x\r\n",rbr); + } + + while( ( ReadCH438Data( REG_LSR3_ADDR ) & BIT_LSR_DATARDY ) == 0x01 ) { + rbr = ReadCH438Data( REG_RBR3_ADDR ); + KPrintf("3.RBR=%02x\r\n",rbr); + } + + while( ( ReadCH438Data( REG_LSR4_ADDR ) & BIT_LSR_DATARDY ) == 0x01 ) { + rbr = ReadCH438Data( REG_RBR4_ADDR ); + KPrintf("4.RBR=%02x\r\n",rbr); + } + + while( ( ReadCH438Data( REG_LSR5_ADDR ) & BIT_LSR_DATARDY ) == 0x01 ) { + rbr = ReadCH438Data( REG_RBR5_ADDR ); + KPrintf("5.RBR=%02x\r\n",rbr); + } + + while( ( ReadCH438Data( REG_LSR6_ADDR ) & BIT_LSR_DATARDY ) == 0x01 ) { + rbr = ReadCH438Data( REG_RBR6_ADDR ); + KPrintf("6.RBR=%02x\r\n",rbr); + } + + while( ( ReadCH438Data( REG_LSR7_ADDR ) & BIT_LSR_DATARDY ) == 0x01 ) { + rbr = ReadCH438Data( REG_RBR7_ADDR ); + KPrintf("7.RBR=%02x\r\n",rbr); + } +} + +void Set485Input(uint8 ch_no) +{ + struct PinStat pin_stat; + struct BusBlockWriteParam write_param; + write_param.buffer = (void *)&pin_stat; + + if (ch_no == 1) { + pin_stat.val = GPIO_LOW; + pin_stat.pin = DIR_485CH1_PIN; + BusDevWriteData(ch438_pin->owner_haldev, &write_param); + } + + if (ch_no == 2) { + pin_stat.val = GPIO_LOW; + pin_stat.pin = DIR_485CH2_PIN; + BusDevWriteData(ch438_pin->owner_haldev, &write_param); + } + + if (ch_no == 3) { + pin_stat.val = GPIO_LOW; + pin_stat.pin = DIR_485CH3_PIN; + BusDevWriteData(ch438_pin->owner_haldev, &write_param); + } +} + +void Set485Output(uint8 ch_no) +{ + struct PinStat pin_stat; + struct BusBlockWriteParam write_param; + write_param.buffer = (void *)&pin_stat; + + if (ch_no == 1) { + pin_stat.val = GPIO_HIGH; + pin_stat.pin = DIR_485CH1_PIN; + BusDevWriteData(ch438_pin->owner_haldev, &write_param); + } + + if (ch_no == 2) { + pin_stat.val = GPIO_HIGH; + pin_stat.pin = DIR_485CH2_PIN; + BusDevWriteData(ch438_pin->owner_haldev, &write_param); + } + + if (ch_no == 3) { + pin_stat.val = GPIO_HIGH; + pin_stat.pin = DIR_485CH3_PIN; + BusDevWriteData(ch438_pin->owner_haldev, &write_param); + } +} + +void Ch438PortInit( uint8 ext_uart_no,uint32 BaudRate ) +{ + uint32 div; + uint8 DLL,DLM,dlab; + uint8 REG_LCR_ADDR; + uint8 REG_DLL_ADDR; + uint8 REG_DLM_ADDR; + uint8 REG_IER_ADDR; + uint8 REG_MCR_ADDR; + uint8 REG_FCR_ADDR; + uint8 REG_RBR_ADDR; + uint8 REG_THR_ADDR; + uint8 REG_IIR_ADDR; + + REG_LCR_ADDR = offset_addr[ext_uart_no] | REG_LCR0_ADDR; + REG_DLL_ADDR = offset_addr[ext_uart_no] | REG_DLL0_ADDR; + REG_DLM_ADDR = offset_addr[ext_uart_no] | REG_DLM0_ADDR; + REG_IER_ADDR = offset_addr[ext_uart_no] | REG_IER0_ADDR; + REG_MCR_ADDR = offset_addr[ext_uart_no] | REG_MCR0_ADDR; + REG_FCR_ADDR = offset_addr[ext_uart_no] | REG_FCR0_ADDR; + REG_RBR_ADDR = offset_addr[ext_uart_no] | REG_RBR0_ADDR; + REG_THR_ADDR = offset_addr[ext_uart_no] | REG_THR0_ADDR; + REG_IIR_ADDR = offset_addr[ext_uart_no] | REG_IIR0_ADDR; + + WriteCH438Data(REG_IER_ADDR, BIT_IER_RESET); /* reset the uart */ + MdelayKTask(50); + + dlab = ReadCH438Data(REG_IER_ADDR); + dlab &= 0xDF; + WriteCH438Data(REG_IER_ADDR, dlab); + + dlab = ReadCH438Data(REG_LCR_ADDR); + dlab |= 0x80; //set LCR register DLAB bit 1 + WriteCH438Data(REG_LCR_ADDR, dlab); + + div = (Fpclk >> 4) / BaudRate; + DLM = div >> 8; + DLL = div & 0xff; + WriteCH438Data(REG_DLL_ADDR, DLL); /* set bps */ + WriteCH438Data(REG_DLM_ADDR, DLM); + WriteCH438Data(REG_FCR_ADDR, BIT_FCR_RECVTG1 | BIT_FCR_RECVTG0 | BIT_FCR_FIFOEN); /* set FIFO mode, 112 bytes */ + + WriteCH438Data(REG_LCR_ADDR, BIT_LCR_WORDSZ1 | BIT_LCR_WORDSZ0); /* 8 bit word size, 1 bit stop bit, no crc */ + + WriteCH438Data(REG_IER_ADDR, BIT_IER_IERECV); /* enable interrupt */ + + WriteCH438Data(REG_MCR_ADDR, BIT_MCR_OUT2);// | BIT_MCR_RTS | BIT_MCR_DTR ); /* allow interrupt output, DTR and RTS is 1 */ + + WriteCH438Data(REG_FCR_ADDR, ReadCH438Data(REG_FCR_ADDR)| BIT_FCR_TFIFORST); /* release the data in FIFO */ +} + +void CH438PortInitParityCheck(uint8 ext_uart_no, uint32 BaudRate) +{ + uint32 div; + uint8 DLL,DLM,dlab; + uint8 REG_LCR_ADDR; + uint8 REG_DLL_ADDR; + uint8 REG_DLM_ADDR; + uint8 REG_IER_ADDR; + uint8 REG_MCR_ADDR; + uint8 REG_FCR_ADDR; + uint8 REG_RBR_ADDR; + uint8 REG_THR_ADDR; + uint8 REG_IIR_ADDR; + + REG_LCR_ADDR = offset_addr[ext_uart_no] | REG_LCR0_ADDR; + REG_DLL_ADDR = offset_addr[ext_uart_no] | REG_DLL0_ADDR; + REG_DLM_ADDR = offset_addr[ext_uart_no] | REG_DLM0_ADDR; + REG_IER_ADDR = offset_addr[ext_uart_no] | REG_IER0_ADDR; + REG_MCR_ADDR = offset_addr[ext_uart_no] | REG_MCR0_ADDR; + REG_FCR_ADDR = offset_addr[ext_uart_no] | REG_FCR0_ADDR; + REG_RBR_ADDR = offset_addr[ext_uart_no] | REG_RBR0_ADDR; + REG_THR_ADDR = offset_addr[ext_uart_no] | REG_THR0_ADDR; + REG_IIR_ADDR = offset_addr[ext_uart_no] | REG_IIR0_ADDR; + + WriteCH438Data(REG_IER_ADDR, BIT_IER_RESET); /* reset the uart */ + MdelayKTask(50); + + dlab = ReadCH438Data(REG_IER_ADDR); + dlab &= 0xDF; + WriteCH438Data(REG_IER_ADDR, dlab); + + dlab = ReadCH438Data(REG_LCR_ADDR); + dlab |= 0x80; //set LCR register DLAB bit 1 + WriteCH438Data(REG_LCR_ADDR, dlab); + + div = (Fpclk >> 4) / BaudRate; + DLM = div >> 8; + DLL = div & 0xff; + WriteCH438Data(REG_DLL_ADDR, DLL); /* set bps */ + WriteCH438Data(REG_DLM_ADDR, DLM); + WriteCH438Data(REG_FCR_ADDR, BIT_FCR_RECVTG1 | BIT_FCR_FIFOEN); /* set FIFO mode, 64 bytes */ + + WriteCH438Data(REG_LCR_ADDR, BIT_LCR_WORDSZ1 | BIT_LCR_WORDSZ0 | BIT_LCR_PAREN | BIT_LCR_PARMODE0); /* 8 bit work size, 1 bit stop bit, even parity check */ + + WriteCH438Data(REG_IER_ADDR, BIT_IER_IERECV); /* enable interrupt */ + + WriteCH438Data(REG_MCR_ADDR, BIT_MCR_OUT2);// | BIT_MCR_RTS | BIT_MCR_DTR ); /* allow interrupt output, DTR and RTS is 1 */ + + WriteCH438Data(REG_FCR_ADDR, ReadCH438Data(REG_FCR_ADDR)| BIT_FCR_TFIFORST); /* release the data in FIFO */ +} + +static uint32 Stm32Ch438Configure(struct SerialCfgParam *ext_serial_cfg) +{ + NULL_PARAM_CHECK(ext_serial_cfg); + + switch (ext_serial_cfg->data_cfg.port_configure) + { + case PORT_CFG_INIT: + Ch438PortInit(ext_serial_cfg->data_cfg.ext_uart_no, ext_serial_cfg->data_cfg.serial_baud_rate); + break; + case PORT_CFG_PARITY_CHECK: + CH438PortInitParityCheck(ext_serial_cfg->data_cfg.ext_uart_no, ext_serial_cfg->data_cfg.serial_baud_rate); + break; + default: + KPrintf("Stm32Ch438Configure do not support configure %d\n", ext_serial_cfg->data_cfg.port_configure); + return ERROR; + break; + } + + return EOK; +} + +static uint32 Stm32Ch438Init(struct SerialDriver *serial_drv, struct SerialCfgParam *ext_serial_cfg) +{ + NULL_PARAM_CHECK(serial_drv); + + struct PinParam pin_cfg; + struct PinStat pin_stat; + int ret = 0; + + struct BusConfigureInfo configure_info; + configure_info.configure_cmd = OPE_CFG; + configure_info.private_data = (void *)&pin_cfg; + + struct BusBlockWriteParam write_param; + write_param.buffer = (void *)&pin_stat; + + ch438_pin = PinBusInitGet(); + + CH438SetOutput(); + + /* config NWR pin as output*/ + pin_cfg.cmd = GPIO_CONFIG_MODE; + pin_cfg.pin = CH438_NWR_PIN; + pin_cfg.mode = GPIO_CFG_OUTPUT; + + ret = BusDrvConfigure(ch438_pin->owner_driver, &configure_info); + if (ret != EOK) { + KPrintf("config NWR pin %d failed!\n", CH438_NWR_PIN); + return ERROR; + } + + /* config NRD pin as output*/ + pin_cfg.pin = CH438_NRD_PIN; + ret = BusDrvConfigure(ch438_pin->owner_driver, &configure_info); + if (ret != EOK) { + KPrintf("config NRD pin %d failed!\n", CH438_NRD_PIN); + return ERROR; + } + + /* config NCS pin as output*/ + pin_cfg.pin = CH438_NCS_PIN; + ret = BusDrvConfigure(ch438_pin->owner_driver, &configure_info); + if (ret != EOK) { + KPrintf("config NCS pin %d failed!\n", CH438_NCS_PIN); + return ERROR; + } + + /* config ALE pin as output*/ + pin_cfg.pin = CH438_ALE_PIN; + ret = BusDrvConfigure(ch438_pin->owner_driver, &configure_info); + if (ret != EOK) { + KPrintf("config ALE pin %d failed!\n", CH438_ALE_PIN); + return ERROR; + } + + /* config 485CH1 pin as output*/ + pin_cfg.pin = DIR_485CH1_PIN; + ret = BusDrvConfigure(ch438_pin->owner_driver, &configure_info); + if (ret != EOK) { + KPrintf("config 485CH1 pin %d failed!\n", DIR_485CH1_PIN); + return ERROR; + } + + /* config 485CH2 pin as output*/ + pin_cfg.pin = DIR_485CH2_PIN; + ret = BusDrvConfigure(ch438_pin->owner_driver, &configure_info); + if (ret != EOK) { + KPrintf("config 485CH2 pin %d failed!\n", DIR_485CH2_PIN); + return ERROR; + } + + /* config 485CH3 pin as output*/ + pin_cfg.pin = DIR_485CH3_PIN; + ret = BusDrvConfigure(ch438_pin->owner_driver, &configure_info); + if (ret != EOK) { + KPrintf("config 485CH3 pin %d failed!\n", DIR_485CH3_PIN); + return ERROR; + } + + /* set NWR pin as high*/ + pin_stat.pin = CH438_NWR_PIN; + pin_stat.val = GPIO_HIGH; + BusDevWriteData(ch438_pin->owner_haldev, &write_param); + + /* set NRD pin as high*/ + pin_stat.pin = CH438_NRD_PIN; + pin_stat.val = GPIO_HIGH; + BusDevWriteData(ch438_pin->owner_haldev, &write_param); + + /* set NCS pin as high*/ + pin_stat.pin = CH438_NCS_PIN; + pin_stat.val = GPIO_LOW; + BusDevWriteData(ch438_pin->owner_haldev, &write_param); + + /* set ALE pin as high*/ + pin_stat.pin = CH438_ALE_PIN; + pin_stat.val = GPIO_HIGH; + BusDevWriteData(ch438_pin->owner_haldev, &write_param); + + return Stm32Ch438Configure(ext_serial_cfg); +} + +static uint32 Stm32Ch438DrvConfigure(void *drv, struct BusConfigureInfo *configure_info) +{ + NULL_PARAM_CHECK(drv); + NULL_PARAM_CHECK(configure_info); + + x_err_t ret = EOK; + + struct SerialDriver *serial_drv = (struct SerialDriver *)drv; + struct SerialCfgParam *ext_serial_cfg = (struct SerialCfgParam *)configure_info->private_data; + + switch (configure_info->configure_cmd) + { + case OPE_INT: + ret = Stm32Ch438Init(serial_drv, ext_serial_cfg); + break; + default: + break; + } + + return ret; +} + +static uint32 Stm32Ch438WriteData(void *dev, struct BusBlockWriteParam *write_param) +{ + NULL_PARAM_CHECK(dev); + NULL_PARAM_CHECK(write_param); + + struct SerialHardwareDevice *serial_dev = (struct SerialHardwareDevice *)dev; + struct SerialDevParam *dev_param = (struct SerialDevParam *)serial_dev->haldev.private_data; + + if (2 == dev_param->ext_uart_no) { + Set485Output(2); + Stm32Udelay(20000); + } else if (3 == dev_param->ext_uart_no) { + Set485Output(1); + Stm32Udelay(20000); + } else if (7 == dev_param->ext_uart_no) { + Set485Output(3); + Stm32Udelay(20000); + } + + Ch438UartSend(dev_param->ext_uart_no, (uint8 *)write_param->buffer, write_param->size); + + if (2 == dev_param->ext_uart_no) { + Stm32Udelay(20000); + Set485Input(2); + } else if (3 == dev_param->ext_uart_no) { + Stm32Udelay(20000); + Set485Input(1); + } else if (7 == dev_param->ext_uart_no) { + Stm32Udelay(20000); + Set485Input(3); + } + + return EOK; +} + +static uint32 Stm32Ch438ReadData(void *dev, struct BusBlockReadParam *read_param) +{ + NULL_PARAM_CHECK(dev); + NULL_PARAM_CHECK(read_param); + + x_err_t result; + uint8 rcv_num = 0; + uint8 gInterruptStatus; + uint8 InterruptStatus; + static uint8 dat; + uint8 REG_LCR_ADDR; + uint8 REG_DLL_ADDR; + uint8 REG_DLM_ADDR; + uint8 REG_IER_ADDR; + uint8 REG_MCR_ADDR; + uint8 REG_FCR_ADDR; + uint8 REG_RBR_ADDR; + uint8 REG_THR_ADDR; + uint8 REG_IIR_ADDR; + uint8 REG_LSR_ADDR; + uint8 REG_MSR_ADDR; + + struct SerialHardwareDevice *serial_dev = (struct SerialHardwareDevice *)dev; + struct SerialDevParam *dev_param = (struct SerialDevParam *)serial_dev->haldev.private_data; + + result = KSemaphoreObtain(ch438_sem, WAITING_FOREVER); + if (EOK == result) { + gInterruptStatus = ReadCH438Data(REG_SSR_ADDR); + if (!gInterruptStatus) { + dat = ReadCH438Data(REG_LCR0_ADDR); + dat = ReadCH438Data(REG_IER0_ADDR); + dat = ReadCH438Data(REG_MCR0_ADDR); + dat = ReadCH438Data(REG_LSR0_ADDR); + dat = ReadCH438Data(REG_MSR0_ADDR); + dat = ReadCH438Data(REG_RBR0_ADDR); + dat = ReadCH438Data(REG_THR0_ADDR); + dat = ReadCH438Data(REG_IIR0_ADDR); + dat = dat ; + } else { + if (gInterruptStatus & interrupt_num[dev_param->ext_uart_no]) { /* check which uart port triggers interrupt*/ + REG_LCR_ADDR = offset_addr[dev_param->ext_uart_no] | REG_LCR0_ADDR; + REG_DLL_ADDR = offset_addr[dev_param->ext_uart_no] | REG_DLL0_ADDR; + REG_DLM_ADDR = offset_addr[dev_param->ext_uart_no] | REG_DLM0_ADDR; + REG_IER_ADDR = offset_addr[dev_param->ext_uart_no] | REG_IER0_ADDR; + REG_MCR_ADDR = offset_addr[dev_param->ext_uart_no] | REG_MCR0_ADDR; + REG_FCR_ADDR = offset_addr[dev_param->ext_uart_no] | REG_FCR0_ADDR; + REG_RBR_ADDR = offset_addr[dev_param->ext_uart_no] | REG_RBR0_ADDR; + REG_THR_ADDR = offset_addr[dev_param->ext_uart_no] | REG_THR0_ADDR; + REG_IIR_ADDR = offset_addr[dev_param->ext_uart_no] | REG_IIR0_ADDR; + REG_LSR_ADDR = offset_addr[dev_param->ext_uart_no] | REG_LSR0_ADDR; + REG_MSR_ADDR = offset_addr[dev_param->ext_uart_no] | REG_MSR0_ADDR; + + InterruptStatus = ReadCH438Data( REG_IIR_ADDR ) & 0x0f; /* read the status of the uart port*/ + + switch( InterruptStatus ) + { + case INT_NOINT: /* NO INTERRUPT */ + break; + case INT_THR_EMPTY: /* THR EMPTY INTERRUPT*/ + break; + case INT_RCV_OVERTIME: /* RECV OVERTIME INTERRUPT*/ + case INT_RCV_SUCCESS: /* RECV INTERRUPT SUCCESSFULLY*/ + rcv_num = Ch438UartRcv(dev_param->ext_uart_no, (uint8 *)read_param->buffer, read_param->size); + read_param->read_length = rcv_num; + break; + case INT_RCV_LINES: /* RECV LINES INTERRUPT */ + ReadCH438Data( REG_LSR_ADDR ); + break; + case INT_MODEM_CHANGE: /* MODEM CHANGE INTERRUPT */ + ReadCH438Data( REG_MSR_ADDR ); + break; + default: + break; + } + } + } + } + return rcv_num; +} + +static const struct SerialDevDone dev_done = +{ + NONE, + NONE, + Stm32Ch438WriteData, + Stm32Ch438ReadData, +}; + +static void Stm32Ch438InitDefault(struct SerialDriver *serial_drv) +{ + struct PinParam PinCfg; + BusType ch438_pin; + + struct BusConfigureInfo configure_info; + + int ret = 0; + configure_info.configure_cmd = OPE_CFG; + configure_info.private_data = (void *)&PinCfg; + + ch438_sem = KSemaphoreCreate(0); + if (ch438_sem < 0) { + KPrintf("Ch438InitDefault create sem failed .\n"); + return ; + } + + ch438_pin = PinBusInitGet(); + + PinCfg.cmd = GPIO_CONFIG_MODE; + PinCfg.pin = CH438_INT_PIN; + PinCfg.mode = GPIO_CFG_INPUT_PULLUP; + ret = BusDrvConfigure(ch438_pin->owner_driver, &configure_info); + if (ret != EOK) { + KPrintf("config BSP_CH438_INT_PIN pin %d failed!\n", CH438_INT_PIN); + return; + } + + PinCfg.cmd = GPIO_IRQ_REGISTER; + PinCfg.pin = CH438_INT_PIN; + PinCfg.irq_set.irq_mode = GPIO_IRQ_EDGE_FALLING; + PinCfg.irq_set.hdr = Ch438Irq; + PinCfg.irq_set.args = NONE; + ret = BusDrvConfigure(ch438_pin->owner_driver, &configure_info); + if (ret != EOK) { + KPrintf("config BSP_CH438_INT_PIN %d failed!\n", CH438_INT_PIN); + return; + } + + PinCfg.cmd = GPIO_IRQ_ENABLE; + PinCfg.pin = CH438_INT_PIN; + ret = BusDrvConfigure(ch438_pin->owner_driver, &configure_info); + if (ret != EOK) { + KPrintf("config BSP_CH438_INT_PIN %d failed!\n", CH438_INT_PIN); + return; + } + + struct SerialCfgParam serial_cfg; + memset(&serial_cfg, 0, sizeof(struct SerialCfgParam)); + configure_info.configure_cmd = OPE_INT; + configure_info.private_data = (void *)&serial_cfg; + + serial_cfg.data_cfg.port_configure = PORT_CFG_INIT; + + serial_cfg.data_cfg.ext_uart_no = 0; + serial_cfg.data_cfg.serial_baud_rate = BAUD_RATE_115200; + BusDrvConfigure(&serial_drv->driver, &configure_info); + + serial_cfg.data_cfg.ext_uart_no = 1; + serial_cfg.data_cfg.serial_baud_rate = BAUD_RATE_9600; + BusDrvConfigure(&serial_drv->driver, &configure_info); + + serial_cfg.data_cfg.ext_uart_no = 2; + serial_cfg.data_cfg.serial_baud_rate = BAUD_RATE_9600; + BusDrvConfigure(&serial_drv->driver, &configure_info); + + serial_cfg.data_cfg.ext_uart_no = 3; + serial_cfg.data_cfg.serial_baud_rate = BAUD_RATE_9600; + BusDrvConfigure(&serial_drv->driver, &configure_info); + + serial_cfg.data_cfg.ext_uart_no = 4; + serial_cfg.data_cfg.serial_baud_rate = BAUD_RATE_9600; + BusDrvConfigure(&serial_drv->driver, &configure_info); + + serial_cfg.data_cfg.ext_uart_no = 5; + serial_cfg.data_cfg.serial_baud_rate = BAUD_RATE_115200; + BusDrvConfigure(&serial_drv->driver, &configure_info); + + serial_cfg.data_cfg.ext_uart_no = 6; + serial_cfg.data_cfg.serial_baud_rate = BAUD_RATE_57600; + BusDrvConfigure(&serial_drv->driver, &configure_info); + + serial_cfg.data_cfg.ext_uart_no = 7; + serial_cfg.data_cfg.serial_baud_rate = BAUD_RATE_9600; + BusDrvConfigure(&serial_drv->driver, &configure_info); +} + +static uint32 Stm32Ch438DevRegister(struct SerialHardwareDevice *serial_dev, char *dev_name) +{ + x_err_t ret = EOK; + serial_dev->dev_done = &dev_done; + serial_dev->ext_serial_mode = RET_TRUE; + ret = SerialDeviceRegister(serial_dev, NONE, dev_name); + if (ret != EOK) { + KPrintf("Stm32HwCh438Init Serial device %s register error %d\n", dev_name, ret); + return ERROR; + } + + ret = SerialDeviceAttachToBus(dev_name, CH438_BUS_NAME); + if (ret != EOK) { + KPrintf("Stm32HwCh438Init Serial device %s register error %d\n", dev_name, ret); + return ERROR; + } + + return ret; +} + +int Stm32HwCh438Init(void) +{ + static struct SerialBus serial_bus; + static struct SerialDriver serial_drv; + + x_err_t ret = EOK; + + ret = SerialBusInit(&serial_bus, CH438_BUS_NAME); + if (ret != EOK) { + KPrintf("Stm32HwCh438Init Serial bus init error %d\n", ret); + return ERROR; + } + + serial_drv.configure = &Stm32Ch438DrvConfigure; + ret = SerialDriverInit(&serial_drv, CH438_DRIVER_NAME); + if (ret != EOK) { + KPrintf("Stm32HwCh438Init Serial driver init error %d\n", ret); + return ERROR; + } + + ret = SerialDriverAttachToBus(CH438_DRIVER_NAME, CH438_BUS_NAME); + if (ret != EOK) { + KPrintf("Stm32HwCh438Init Serial driver attach error %d\n", ret); + return ERROR; + } + + static struct SerialHardwareDevice serial_dev_0; + static struct SerialDevParam dev_param_0; + dev_param_0.ext_uart_no = 0; + serial_dev_0.haldev.private_data = (void *)&dev_param_0; + ret = Stm32Ch438DevRegister(&serial_dev_0, CH438_DEVICE_NAME_0); + if (ret != EOK) { + KPrintf("Stm32HwCh438Init Stm32Ch438DevRegister error %d\n", ret); + return ERROR; + } + + static struct SerialHardwareDevice serial_dev_1; + static struct SerialDevParam dev_param_1; + dev_param_1.ext_uart_no = 1; + serial_dev_1.haldev.private_data = (void *)&dev_param_1; + ret = Stm32Ch438DevRegister(&serial_dev_1, CH438_DEVICE_NAME_1); + if (ret != EOK) { + KPrintf("Stm32HwCh438Init Stm32Ch438DevRegister error %d\n", ret); + return ERROR; + } + + static struct SerialHardwareDevice serial_dev_2; + static struct SerialDevParam dev_param_2; + dev_param_2.ext_uart_no = 2; + serial_dev_2.haldev.private_data = (void *)&dev_param_2; + ret = Stm32Ch438DevRegister(&serial_dev_2, CH438_DEVICE_NAME_2); + if (ret != EOK) { + KPrintf("Stm32HwCh438Init Stm32Ch438DevRegister error %d\n", ret); + return ERROR; + } + + static struct SerialHardwareDevice serial_dev_3; + static struct SerialDevParam dev_param_3; + dev_param_3.ext_uart_no = 3; + serial_dev_3.haldev.private_data = (void *)&dev_param_3; + ret = Stm32Ch438DevRegister(&serial_dev_3, CH438_DEVICE_NAME_3); + if (ret != EOK) { + KPrintf("Stm32HwCh438Init Stm32Ch438DevRegister error %d\n", ret); + return ERROR; + } + + static struct SerialHardwareDevice serial_dev_4; + static struct SerialDevParam dev_param_4; + dev_param_4.ext_uart_no = 4; + serial_dev_4.haldev.private_data = (void *)&dev_param_4; + ret = Stm32Ch438DevRegister(&serial_dev_4, CH438_DEVICE_NAME_4); + if (ret != EOK) { + KPrintf("Stm32HwCh438Init Stm32Ch438DevRegister error %d\n", ret); + return ERROR; + } + + static struct SerialHardwareDevice serial_dev_5; + static struct SerialDevParam dev_param_5; + dev_param_5.ext_uart_no = 5; + serial_dev_5.haldev.private_data = (void *)&dev_param_5; + ret = Stm32Ch438DevRegister(&serial_dev_5, CH438_DEVICE_NAME_5); + if (ret != EOK) { + KPrintf("Stm32HwCh438Init Stm32Ch438DevRegister error %d\n", ret); + return ERROR; + } + + static struct SerialHardwareDevice serial_dev_6; + static struct SerialDevParam dev_param_6; + dev_param_6.ext_uart_no = 6; + serial_dev_6.haldev.private_data = (void *)&dev_param_6; + ret = Stm32Ch438DevRegister(&serial_dev_6, CH438_DEVICE_NAME_6); + if (ret != EOK) { + KPrintf("Stm32HwCh438Init Stm32Ch438DevRegister error %d\n", ret); + return ERROR; + } + + static struct SerialHardwareDevice serial_dev_7; + static struct SerialDevParam dev_param_7; + dev_param_7.ext_uart_no = 7; + serial_dev_7.haldev.private_data = (void *)&dev_param_7; + ret = Stm32Ch438DevRegister(&serial_dev_7, CH438_DEVICE_NAME_7); + if (ret != EOK) { + KPrintf("Stm32HwCh438Init Stm32Ch438DevRegister error %d\n", ret); + return ERROR; + } + + Stm32Ch438InitDefault(&serial_drv); + + return ret; +} + +void CH438RegTest(unsigned char num)//for test +{ + uint8 dat; + + KPrintf("current test serilnum: %02x \r\n",offset_addr[num]); + KPrintf("IER: %02x\r\n",ReadCH438Data(offset_addr[num] | REG_IER0_ADDR));//?IER + KPrintf("IIR: %02x\r\n",ReadCH438Data(offset_addr[num] | REG_IIR0_ADDR));//?IIR + KPrintf("LCR: %02x\r\n",ReadCH438Data(offset_addr[num] | REG_LCR0_ADDR));//?LCR + KPrintf("MCR: %02x\r\n",ReadCH438Data(offset_addr[num] | REG_MCR0_ADDR));//?MCR + KPrintf("LSR: %02x\r\n",ReadCH438Data(offset_addr[num] | REG_LSR0_ADDR));//?LSR + KPrintf("MSR: %02x\r\n",ReadCH438Data(offset_addr[num] | REG_MSR0_ADDR));//?MSR + KPrintf("FCR: %02x\r\n",ReadCH438Data(offset_addr[num] | REG_FCR0_ADDR));//?FCR + KPrintf("SSR: %02x\r\n",ReadCH438Data( offset_addr[num] | REG_SSR_ADDR ));//?SSR + + KPrintf("SCR0: %02x\r\n",(unsigned short)ReadCH438Data(offset_addr[num] | REG_SCR0_ADDR));//?SCR + dat = 0x55; + WriteCH438Data(offset_addr[num] | REG_SCR0_ADDR, dat); + KPrintf("SCR55: %02x\r\n",(unsigned short)ReadCH438Data(offset_addr[num] | REG_SCR0_ADDR));//?SCR + dat = 0xAA; + WriteCH438Data(offset_addr[num] | REG_SCR0_ADDR, dat); + KPrintf("SCRAA: %02x\r\n",(unsigned short)ReadCH438Data(offset_addr[num] | REG_SCR0_ADDR));//?SCR +} diff --git a/Ubiquitous/XiZi/board/aiit-arm32-board/third_party_driver/dac/Kconfig b/Ubiquitous/XiZi/board/aiit-arm32-board/third_party_driver/dac/Kconfig new file mode 100644 index 0000000..a289b6c --- /dev/null +++ b/Ubiquitous/XiZi/board/aiit-arm32-board/third_party_driver/dac/Kconfig @@ -0,0 +1,17 @@ +if BSP_USING_DAC + config DAC_BUS_NAME + string "dac bus name" + default "dac" + + config DAC_DRIVER_NAME + string "dac driver name" + default "dac_drv" + + config DAC_DEVICE_NAME + string "dac bus device name" + default "dac_dev" + + config DAC_GPIO_NUM + int "dac gpio pin num(only support 4 or 5)" + default "4" +endif diff --git a/Ubiquitous/XiZi/board/aiit-arm32-board/third_party_driver/dac/Makefile b/Ubiquitous/XiZi/board/aiit-arm32-board/third_party_driver/dac/Makefile new file mode 100644 index 0000000..4bd1c0c --- /dev/null +++ b/Ubiquitous/XiZi/board/aiit-arm32-board/third_party_driver/dac/Makefile @@ -0,0 +1,3 @@ +SRC_FILES := connect_dac.c hardware_dac.c + +include $(KERNEL_ROOT)/compiler.mk diff --git a/Ubiquitous/XiZi/board/aiit-arm32-board/third_party_driver/dac/connect_dac.c b/Ubiquitous/XiZi/board/aiit-arm32-board/third_party_driver/dac/connect_dac.c new file mode 100644 index 0000000..6186b0a --- /dev/null +++ b/Ubiquitous/XiZi/board/aiit-arm32-board/third_party_driver/dac/connect_dac.c @@ -0,0 +1,168 @@ +/* +* Copyright (c) 2020 AIIT XUOS Lab +* XiUOS is licensed under Mulan PSL v2. +* You can use this software according to the terms and conditions of the Mulan PSL v2. +* You may obtain a copy of Mulan PSL v2 at: +* http://license.coscl.org.cn/MulanPSL2 +* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, +* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, +* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. +* See the Mulan PSL v2 for more details. +*/ + +/** +* @file connect_dac.c +* @brief support to register DAC pointer and function +* @version 2.0 +* @author AIIT XUOS Lab +* @date 2022-1-10 +*/ + +#include + +#define _DAC_CONS(string1, string2) string1##string2 +#define DAC_CONS(string1, string2) _DAC_CONS(string1, string2) + +#ifdef BSP_USING_DAC +#define DAC_GPIO DAC_CONS(GPIO_Pin_, DAC_GPIO_NUM) +#endif + +static void DacInit(struct DacHardwareDevice *dac_dev) +{ + GPIO_InitTypeDef GPIO_InitStructure; + DAC_InitTypeDef DAC_InitType; + +#ifdef BSP_USING_DAC + if (0 == strncmp(dac_dev->haldev.dev_name, DAC_DEVICE_NAME, NAME_NUM_MAX)) { + RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOA, ENABLE);//enable GPIOA clock + RCC_APB1PeriphClockCmd(RCC_APB1Periph_DAC, ENABLE);//enable DAC clock + + GPIO_InitStructure.GPIO_Pin = DAC_GPIO; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AN; + GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_DOWN; + GPIO_Init(GPIOA, &GPIO_InitStructure); + + DAC_InitType.DAC_Trigger = DAC_Trigger_None;//disable trigger function TEN1=0 + DAC_InitType.DAC_WaveGeneration = DAC_WaveGeneration_None;//disable wave generation function + DAC_InitType.DAC_LFSRUnmask_TriangleAmplitude = DAC_LFSRUnmask_Bit0;//mask and amplitude configure + DAC_InitType.DAC_OutputBuffer = DAC_OutputBuffer_Disable;//disable DAC1 output buffer BOFF1=1 + DAC_Init(DAC_Channel_1, &DAC_InitType); + + DAC_Cmd(DAC_Channel_1, ENABLE);//enable DAC channel 1 + + DAC_SetChannel1Data(DAC_Align_12b_R, 0);//12 bits、R-Align data format, default 0 + } +#endif +} + +static uint32 Stm32DacOpen(void *dev) +{ + struct DacHardwareDevice *dac_dev = (struct DacHardwareDevice *)dev; + + DacInit(dac_dev); + + return EOK; +} + +static uint32 Stm32DacClose(void *dev) +{ + struct DacHardwareDevice *dac_dev = (struct DacHardwareDevice *)dev; + + DAC_DeInit(); + + return EOK; +} + +static uint32 Stm32DacRead(void *dev, struct BusBlockReadParam *read_param) +{ + struct DacHardwareDevice *dac_dev = (struct DacHardwareDevice *)dev; + + uint16 dac_set_value = 0; + + dac_set_value = DAC_GetDataOutputValue(DAC_Channel_1); + + *(uint16 *)read_param->buffer = dac_set_value; + read_param->read_length = 2; + + return read_param->read_length; +} + +static uint32 Stm32DacDrvConfigure(void *drv, struct BusConfigureInfo *configure_info) +{ + NULL_PARAM_CHECK(drv); + NULL_PARAM_CHECK(configure_info); + + x_err_t ret = EOK; + + struct DacDriver *dac_drv = (struct DacDriver *)drv; + struct DacHardwareDevice *dac_dev = (struct DacHardwareDevice *)dac_drv->driver.owner_bus->owner_haldev; + struct Stm32HwDac *dac_cfg = (struct Stm32HwDac *)dac_dev->haldev.private_data; + + switch (configure_info->configure_cmd) + { + case OPE_CFG: + dac_cfg->digital_data = *(uint16 *)configure_info->private_data; + DAC_SetChannel1Data(DAC_Align_12b_R, dac_cfg->digital_data);//12 bits、R-Align data format, digital data + break; + default: + break; + } + + return ret; +} + +static const struct DacDevDone dev_done = +{ + Stm32DacOpen, + Stm32DacClose, + NONE, + Stm32DacRead, +}; + +int Stm32HwDacInit(void) +{ + x_err_t ret = EOK; + +#ifdef BSP_USING_DAC + static struct DacBus dac_bus; + static struct DacDriver dac_drv; + static struct DacHardwareDevice dac_dev; + static struct Stm32HwDac dac_cfg; + + dac_drv.configure = Stm32DacDrvConfigure; + + ret = DacBusInit(&dac_bus, DAC_BUS_NAME); + if (ret != EOK) { + KPrintf("DAC bus init error %d\n", ret); + return ERROR; + } + + ret = DacDriverInit(&dac_drv, DAC_DRIVER_NAME); + if (ret != EOK) { + KPrintf("DAC driver init error %d\n", ret); + return ERROR; + } + ret = DacDriverAttachToBus(DAC_DRIVER_NAME, DAC_BUS_NAME); + if (ret != EOK) { + KPrintf("DAC driver attach error %d\n", ret); + return ERROR; + } + + dac_dev.dac_dev_done = &dev_done; + dac_cfg.DACx = DAC; + dac_cfg.digital_data = 0; + + ret = DacDeviceRegister(&dac_dev, (void *)&dac_cfg, DAC_DEVICE_NAME); + if (ret != EOK) { + KPrintf("DAC device register error %d\n", ret); + return ERROR; + } + ret = DacDeviceAttachToBus(DAC_DEVICE_NAME, DAC_BUS_NAME); + if (ret != EOK) { + KPrintf("DAC device register error %d\n", ret); + return ERROR; + } +#endif + + return ret; +} diff --git a/Ubiquitous/XiZi/board/aiit-arm32-board/third_party_driver/extmem/Kconfig b/Ubiquitous/XiZi/board/aiit-arm32-board/third_party_driver/extmem/Kconfig new file mode 100644 index 0000000..27186cb --- /dev/null +++ b/Ubiquitous/XiZi/board/aiit-arm32-board/third_party_driver/extmem/Kconfig @@ -0,0 +1,17 @@ +if BSP_USING_EXTMEM + config EXTSRAM_MAX_NUM + int + default 4 + + config BSP_USING_FSMC_BANK1_NORSRAM3 + bool "config fsmc bank1 sram3" + default n + if BSP_USING_FSMC_BANK1_NORSRAM3 + config BANK1_NORSRAM3_SIZE + hex "config sram3 chip size" + default 0x100000 + config BANK1_NORSRAM3_DATA_WIDTH + int "config sram3 chip data width" + default 16 + endif +endif diff --git a/Ubiquitous/XiZi/board/aiit-arm32-board/third_party_driver/extmem/Makefile b/Ubiquitous/XiZi/board/aiit-arm32-board/third_party_driver/extmem/Makefile new file mode 100644 index 0000000..cc3f729 --- /dev/null +++ b/Ubiquitous/XiZi/board/aiit-arm32-board/third_party_driver/extmem/Makefile @@ -0,0 +1,3 @@ +SRC_FILES := connect_extmem.c + +include $(KERNEL_ROOT)/compiler.mk diff --git a/Ubiquitous/XiZi/board/aiit-arm32-board/third_party_driver/extmem/connect_extmem.c b/Ubiquitous/XiZi/board/aiit-arm32-board/third_party_driver/extmem/connect_extmem.c new file mode 100644 index 0000000..3703fcd --- /dev/null +++ b/Ubiquitous/XiZi/board/aiit-arm32-board/third_party_driver/extmem/connect_extmem.c @@ -0,0 +1,162 @@ +/* +* Copyright (c) 2020 AIIT XUOS Lab +* XiUOS is licensed under Mulan PSL v2. +* You can use this software according to the terms and conditions of the Mulan PSL v2. +* You may obtain a copy of Mulan PSL v2 at: +* http://license.coscl.org.cn/MulanPSL2 +* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, +* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, +* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. +* See the Mulan PSL v2 for more details. +*/ + +/** +* @file connect_extmem.c +* @brief support extern memory by fsmc +* @version 1.0 +* @author AIIT XUOS Lab +* @date 2021-05-28 +*/ + +#include "connect_extmem.h" +#include "hardware_fsmc.h" +#include "hardware_gpio.h" +#include "hardware_rcc.h" +#include +#include + +#define FSMC_BANK1_NORSRAM3_START_ADDRESS 0x68000000 + +static FSMC_NORSRAMInitTypeDef hsram3; +static FSMC_NORSRAMTimingInitTypeDef hsram_read3; +static FSMC_NORSRAMTimingInitTypeDef hsram_write3; + +extern void ExtSramInitBoardMemory(void *start_phy_address, void *end_phy_address, uint8 extsram_idx); + +int HwSramInit(void) +{ + GPIO_InitTypeDef GPIO_InitStructure; + + RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOD|RCC_AHB1Periph_GPIOE|RCC_AHB1Periph_GPIOF|RCC_AHB1Periph_GPIOG, ENABLE); + RCC_AHB3PeriphClockCmd(RCC_AHB3Periph_FSMC,ENABLE); + + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0 | GPIO_Pin_1 | GPIO_Pin_4 | GPIO_Pin_5 | GPIO_Pin_8 | GPIO_Pin_9 | GPIO_Pin_10 | GPIO_Pin_11 | GPIO_Pin_12 | GPIO_Pin_13 | GPIO_Pin_14 | GPIO_Pin_15; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF; + GPIO_InitStructure.GPIO_OType = GPIO_OType_PP; + GPIO_InitStructure.GPIO_Speed = GPIO_Speed_100MHz; + GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL; + GPIO_Init(GPIOD, &GPIO_InitStructure); + + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_7 | GPIO_Pin_8 | GPIO_Pin_9 | GPIO_Pin_10 | GPIO_Pin_11 | GPIO_Pin_12 | GPIO_Pin_13 | GPIO_Pin_14 | GPIO_Pin_15; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF; + GPIO_InitStructure.GPIO_OType = GPIO_OType_PP; + GPIO_InitStructure.GPIO_Speed = GPIO_Speed_100MHz; + GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL; + GPIO_Init(GPIOE, &GPIO_InitStructure); + + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0 | GPIO_Pin_1 | GPIO_Pin_2 | GPIO_Pin_3 | GPIO_Pin_4 | GPIO_Pin_5 | GPIO_Pin_12 | GPIO_Pin_13 | GPIO_Pin_14 | GPIO_Pin_15; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF; + GPIO_InitStructure.GPIO_OType = GPIO_OType_PP; + GPIO_InitStructure.GPIO_Speed = GPIO_Speed_100MHz; + GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL; + GPIO_Init(GPIOF, &GPIO_InitStructure); + + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0 | GPIO_Pin_1 | GPIO_Pin_2 | GPIO_Pin_3 | GPIO_Pin_4 | GPIO_Pin_5 | GPIO_Pin_10 | GPIO_Pin_12; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF; + GPIO_InitStructure.GPIO_OType = GPIO_OType_PP; + GPIO_InitStructure.GPIO_Speed = GPIO_Speed_100MHz; + GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL; + GPIO_Init(GPIOG, &GPIO_InitStructure); + + GPIO_PinAFConfig(GPIOD,GPIO_PinSource0,GPIO_AF_FSMC); + GPIO_PinAFConfig(GPIOD,GPIO_PinSource1,GPIO_AF_FSMC); + GPIO_PinAFConfig(GPIOD,GPIO_PinSource4,GPIO_AF_FSMC); + GPIO_PinAFConfig(GPIOD,GPIO_PinSource5,GPIO_AF_FSMC); + GPIO_PinAFConfig(GPIOD,GPIO_PinSource8,GPIO_AF_FSMC); + GPIO_PinAFConfig(GPIOD,GPIO_PinSource9,GPIO_AF_FSMC); + GPIO_PinAFConfig(GPIOD,GPIO_PinSource10,GPIO_AF_FSMC); + GPIO_PinAFConfig(GPIOD,GPIO_PinSource11,GPIO_AF_FSMC); + GPIO_PinAFConfig(GPIOD,GPIO_PinSource12,GPIO_AF_FSMC); + GPIO_PinAFConfig(GPIOD,GPIO_PinSource13,GPIO_AF_FSMC); + GPIO_PinAFConfig(GPIOD,GPIO_PinSource14,GPIO_AF_FSMC); + GPIO_PinAFConfig(GPIOD,GPIO_PinSource15,GPIO_AF_FSMC); + + GPIO_PinAFConfig(GPIOE,GPIO_PinSource7,GPIO_AF_FSMC); + GPIO_PinAFConfig(GPIOE,GPIO_PinSource8,GPIO_AF_FSMC); + GPIO_PinAFConfig(GPIOE,GPIO_PinSource9,GPIO_AF_FSMC); + GPIO_PinAFConfig(GPIOE,GPIO_PinSource10,GPIO_AF_FSMC); + GPIO_PinAFConfig(GPIOE,GPIO_PinSource11,GPIO_AF_FSMC); + GPIO_PinAFConfig(GPIOE,GPIO_PinSource12,GPIO_AF_FSMC); + GPIO_PinAFConfig(GPIOE,GPIO_PinSource13,GPIO_AF_FSMC); + GPIO_PinAFConfig(GPIOE,GPIO_PinSource14,GPIO_AF_FSMC); + GPIO_PinAFConfig(GPIOE,GPIO_PinSource15,GPIO_AF_FSMC); + + GPIO_PinAFConfig(GPIOF,GPIO_PinSource0,GPIO_AF_FSMC); + GPIO_PinAFConfig(GPIOF,GPIO_PinSource1,GPIO_AF_FSMC); + GPIO_PinAFConfig(GPIOF,GPIO_PinSource2,GPIO_AF_FSMC); + GPIO_PinAFConfig(GPIOF,GPIO_PinSource3,GPIO_AF_FSMC); + GPIO_PinAFConfig(GPIOF,GPIO_PinSource4,GPIO_AF_FSMC); + GPIO_PinAFConfig(GPIOF,GPIO_PinSource5,GPIO_AF_FSMC); + GPIO_PinAFConfig(GPIOF,GPIO_PinSource12,GPIO_AF_FSMC); + GPIO_PinAFConfig(GPIOF,GPIO_PinSource13,GPIO_AF_FSMC); + GPIO_PinAFConfig(GPIOF,GPIO_PinSource14,GPIO_AF_FSMC); + GPIO_PinAFConfig(GPIOF,GPIO_PinSource15,GPIO_AF_FSMC); + + GPIO_PinAFConfig(GPIOG,GPIO_PinSource0,GPIO_AF_FSMC); + GPIO_PinAFConfig(GPIOG,GPIO_PinSource1,GPIO_AF_FSMC); + GPIO_PinAFConfig(GPIOG,GPIO_PinSource2,GPIO_AF_FSMC); + GPIO_PinAFConfig(GPIOG,GPIO_PinSource3,GPIO_AF_FSMC); + GPIO_PinAFConfig(GPIOG,GPIO_PinSource4,GPIO_AF_FSMC); + GPIO_PinAFConfig(GPIOG,GPIO_PinSource5,GPIO_AF_FSMC); + GPIO_PinAFConfig(GPIOG,GPIO_PinSource10,GPIO_AF_FSMC); + GPIO_PinAFConfig(GPIOG,GPIO_PinSource12,GPIO_AF_FSMC); + + hsram3.FSMC_ReadWriteTimingStruct = &hsram_read3; + hsram3.FSMC_WriteTimingStruct = &hsram_write3; + + /* hsram3.Init */ + hsram3.FSMC_DataAddressMux = FSMC_DataAddressMux_Disable; + hsram3.FSMC_MemoryType = FSMC_MemoryType_SRAM; + hsram3.FSMC_BurstAccessMode = FSMC_BurstAccessMode_Disable; + hsram3.FSMC_WaitSignalPolarity = FSMC_WaitSignalPolarity_Low; + hsram3.FSMC_WrapMode = FSMC_WrapMode_Disable; + hsram3.FSMC_WaitSignalActive = FSMC_WaitSignalActive_BeforeWaitState; + hsram3.FSMC_WriteOperation = FSMC_WriteOperation_Enable; + hsram3.FSMC_WaitSignal = FSMC_WaitSignal_Disable; + hsram3.FSMC_ExtendedMode = FSMC_ExtendedMode_Disable; + hsram3.FSMC_WriteBurst = FSMC_WriteBurst_Disable; + + hsram_read3.FSMC_AddressSetupTime = 0; + hsram_read3.FSMC_AddressHoldTime = 0; + hsram_read3.FSMC_DataSetupTime = 8; + hsram_read3.FSMC_BusTurnAroundDuration = 0; + hsram_read3.FSMC_CLKDivision = 0; + hsram_read3.FSMC_DataLatency = 0; + hsram_read3.FSMC_AccessMode = FSMC_AccessMode_A; + + hsram_write3.FSMC_AddressSetupTime = 0; + hsram_write3.FSMC_AddressHoldTime = 0; + hsram_write3.FSMC_DataSetupTime = 8; + hsram_write3.FSMC_BusTurnAroundDuration = 0; + hsram_write3.FSMC_CLKDivision = 0; + hsram_write3.FSMC_DataLatency = 0; + hsram_write3.FSMC_AccessMode = FSMC_AccessMode_A; + +#ifdef BSP_USING_FSMC_BANK1_NORSRAM3 + hsram3.FSMC_Bank = FSMC_Bank1_NORSRAM3; +#if BANK1_NORSRAM3_DATA_WIDTH == 8 + hsram3.FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_8b; +#elif BANK1_NORSRAM3_DATA_WIDTH == 16 + hsram3.FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_16b; +#else + hsram3.FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_32b; +#endif + FSMC_NORSRAMInit(&hsram3); + FSMC_NORSRAMCmd(FSMC_Bank1_NORSRAM3, ENABLE); + + ExtSramInitBoardMemory((void*)(FSMC_BANK1_NORSRAM3_START_ADDRESS), (void*)((FSMC_BANK1_NORSRAM3_START_ADDRESS + BANK1_NORSRAM3_SIZE)), 2); + +#endif + + return 0; +} \ No newline at end of file diff --git a/Ubiquitous/XiZi/board/aiit-arm32-board/third_party_driver/gpio/Kconfig b/Ubiquitous/XiZi/board/aiit-arm32-board/third_party_driver/gpio/Kconfig new file mode 100644 index 0000000..f284f60 --- /dev/null +++ b/Ubiquitous/XiZi/board/aiit-arm32-board/third_party_driver/gpio/Kconfig @@ -0,0 +1,12 @@ + +config PIN_BUS_NAME + string "pin bus name" + default "pin" + +config PIN_DRIVER_NAME + string "pin driver name" + default "pin_drv" + +config PIN_DEVICE_NAME + string "pin device name" + default "pin_dev" diff --git a/Ubiquitous/XiZi/board/aiit-arm32-board/third_party_driver/gpio/Makefile b/Ubiquitous/XiZi/board/aiit-arm32-board/third_party_driver/gpio/Makefile new file mode 100644 index 0000000..12e1dbe --- /dev/null +++ b/Ubiquitous/XiZi/board/aiit-arm32-board/third_party_driver/gpio/Makefile @@ -0,0 +1,3 @@ +SRC_FILES := connect_gpio.c hardware_gpio.c + +include $(KERNEL_ROOT)/compiler.mk diff --git a/Ubiquitous/XiZi/board/aiit-arm32-board/third_party_driver/i2c/Kconfig b/Ubiquitous/XiZi/board/aiit-arm32-board/third_party_driver/i2c/Kconfig new file mode 100644 index 0000000..e9e435d --- /dev/null +++ b/Ubiquitous/XiZi/board/aiit-arm32-board/third_party_driver/i2c/Kconfig @@ -0,0 +1,11 @@ +if BSP_USING_I2C + config I2C_BUS_NAME_1 + string "i2c bus 1 name" + default "i2c1" + config I2C_DRV_NAME_1 + string "i2c bus 1 driver name" + default "i2c1_drv" + config I2C_1_DEVICE_NAME_0 + string "i2c bus 1 device 0 name" + default "i2c1_dev0" +endif diff --git a/Ubiquitous/XiZi/board/aiit-arm32-board/third_party_driver/i2c/Makefile b/Ubiquitous/XiZi/board/aiit-arm32-board/third_party_driver/i2c/Makefile new file mode 100644 index 0000000..5f0faa5 --- /dev/null +++ b/Ubiquitous/XiZi/board/aiit-arm32-board/third_party_driver/i2c/Makefile @@ -0,0 +1,3 @@ +SRC_FILES := hardware_i2c.c connect_i2c.c + +include $(KERNEL_ROOT)/compiler.mk diff --git a/Ubiquitous/XiZi/board/aiit-arm32-board/third_party_driver/include/connect_adc.h b/Ubiquitous/XiZi/board/aiit-arm32-board/third_party_driver/include/connect_adc.h new file mode 100644 index 0000000..fa15f48 --- /dev/null +++ b/Ubiquitous/XiZi/board/aiit-arm32-board/third_party_driver/include/connect_adc.h @@ -0,0 +1,37 @@ +/* +* Copyright (c) 2020 AIIT XUOS Lab +* XiUOS is licensed under Mulan PSL v2. +* You can use this software according to the terms and conditions of the Mulan PSL v2. +* You may obtain a copy of Mulan PSL v2 at: +* http://license.coscl.org.cn/MulanPSL2 +* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, +* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, +* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. +* See the Mulan PSL v2 for more details. +*/ + +/** +* @file connect_adc.h +* @brief define aiit-arm32-board adc function and struct +* @version 1.1 +* @author AIIT XUOS Lab +* @date 2021-12-28 +*/ + +#ifndef CONNECT_ADC_H +#define CONNECT_ADC_H + +#include +#include +#include +#include + +struct Stm32HwAdc +{ + ADC_TypeDef *ADCx; + uint8 adc_channel; +}; + +int Stm32HwAdcInit(void); + +#endif diff --git a/Ubiquitous/XiZi/board/aiit-arm32-board/third_party_driver/include/connect_can.h b/Ubiquitous/XiZi/board/aiit-arm32-board/third_party_driver/include/connect_can.h new file mode 100644 index 0000000..85538a4 --- /dev/null +++ b/Ubiquitous/XiZi/board/aiit-arm32-board/third_party_driver/include/connect_can.h @@ -0,0 +1,41 @@ +/* +* Copyright (c) 2020 AIIT XUOS Lab +* XiUOS is licensed under Mulan PSL v2. +* You can use this software according to the terms and conditions of the Mulan PSL v2. +* You may obtain a copy of Mulan PSL v2 at: +* http://license.coscl.org.cn/MulanPSL2 +* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, +* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, +* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. +* See the Mulan PSL v2 for more details. +*/ + +/** +* @file connect_can.h +* @brief define aiit-arm32-board can function and struct +* @version 1.0 +* @author AIIT XUOS Lab +* @date 2021-04-25 +*/ + +#ifndef CONNECT_CAN_H +#define CONNECT_CAN_H + +#include +#include + +struct Stm32Can +{ + CAN_TypeDef *instance; + + char *bus_name; + + CAN_InitTypeDef init; + + uint8 can_flag; + struct CanBus can_bus; +}; + +int Stm32HwCanBusInit(void); + +#endif \ No newline at end of file diff --git a/Ubiquitous/XiZi/board/aiit-arm32-board/third_party_driver/include/connect_ch438.h b/Ubiquitous/XiZi/board/aiit-arm32-board/third_party_driver/include/connect_ch438.h new file mode 100755 index 0000000..05942f5 --- /dev/null +++ b/Ubiquitous/XiZi/board/aiit-arm32-board/third_party_driver/include/connect_ch438.h @@ -0,0 +1,293 @@ +/* +* Copyright (c) 2020 AIIT XUOS Lab +* XiUOS is licensed under Mulan PSL v2. +* You can use this software according to the terms and conditions of the Mulan PSL v2. +* You may obtain a copy of Mulan PSL v2 at: +* http://license.coscl.org.cn/MulanPSL2 +* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, +* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, +* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. +* See the Mulan PSL v2 for more details. +*/ + +/** +* @file connect_ch438.h +* @brief define aiit-arm32-board ch438 function and struct +* @version 1.0 +* @author AIIT XUOS Lab +* @date 2021-04-25 +*/ + +#ifndef CONNECT_CH438_H +#define CONNECT_CH438_H + +#include +#include + +#define CH438_BUFFSIZE 255 + +/******************************************************************************************/ + +/* chip definition */ +/* CH438serial port0 register address */ + +#define REG_RBR0_ADDR 0x00 /* serial port0receive buffer register address */ +#define REG_THR0_ADDR 0x00 /* serial port0send hold register address */ +#define REG_IER0_ADDR 0x01 /* serial port0interrupt enable register address */ +#define REG_IIR0_ADDR 0x02 /* serial port0interrupt identifies register address */ +#define REG_FCR0_ADDR 0x02 /* serial port0FIFO controls register address */ +#define REG_LCR0_ADDR 0x03 /* serial port0circuit control register address */ +#define REG_MCR0_ADDR 0x04 /* serial port0MODEM controls register address */ +#define REG_LSR0_ADDR 0x05 /* serial port0line status register address */ +#define REG_MSR0_ADDR 0x06 /* serial port0address of MODEM status register */ +#define REG_SCR0_ADDR 0x07 /* serial port0the user can define the register address */ +#define REG_DLL0_ADDR 0x00 /* Baud rate divisor latch low 8-bit byte address */ +#define REG_DLM0_ADDR 0x01 /* Baud rate divisor latch high 8-bit byte address */ + +/* CH438serial port1 register address */ + +#define REG_RBR1_ADDR 0x10 /* serial port1receive buffer register address */ +#define REG_THR1_ADDR 0x10 /* serial port1send hold register address */ +#define REG_IER1_ADDR 0x11 /* serial port1interrupt enable register address */ +#define REG_IIR1_ADDR 0x12 /* serial port1interrupt identifies register address */ +#define REG_FCR1_ADDR 0x12 /* serial port1FIFO controls register address */ +#define REG_LCR1_ADDR 0x13 /* serial port1circuit control register address */ +#define REG_MCR1_ADDR 0x14 /* serial port1MODEM controls register address */ +#define REG_LSR1_ADDR 0x15 /* serial port1line status register address */ +#define REG_MSR1_ADDR 0x16 /* serial port1address of MODEM status register */ +#define REG_SCR1_ADDR 0x17 /* serial port1the user can define the register address */ +#define REG_DLL1_ADDR 0x10 /* Baud rate divisor latch low 8-bit byte address */ +#define REG_DLM1_ADDR 0x11 /* Baud rate divisor latch high 8-bit byte address */ + + +/* CH438serial port2 register address */ + +#define REG_RBR2_ADDR 0x20 /* serial port2receive buffer register address */ +#define REG_THR2_ADDR 0x20 /* serial port2send hold register address */ +#define REG_IER2_ADDR 0x21 /* serial port2interrupt enable register address */ +#define REG_IIR2_ADDR 0x22 /* serial port2interrupt identifies register address */ +#define REG_FCR2_ADDR 0x22 /* serial port2FIFO controls register address */ +#define REG_LCR2_ADDR 0x23 /* serial port2circuit control register address */ +#define REG_MCR2_ADDR 0x24 /* serial port2MODEM controls register address */ +#define REG_LSR2_ADDR 0x25 /* serial port2line status register address */ +#define REG_MSR2_ADDR 0x26 /* serial port2address of MODEM status register */ +#define REG_SCR2_ADDR 0x27 /* serial port2the user can define the register address */ +#define REG_DLL2_ADDR 0x20 /* Baud rate divisor latch low 8-bit byte address */ +#define REG_DLM2_ADDR 0x21 /* Baud rate divisor latch high 8-bit byte address */ + + + +/* CH438serial port3 register address */ + +#define REG_RBR3_ADDR 0x30 /* serial port3receive buffer register address */ +#define REG_THR3_ADDR 0x30 /* serial port3send hold register address */ +#define REG_IER3_ADDR 0x31 /* serial port3interrupt enable register address */ +#define REG_IIR3_ADDR 0x32 /* serial port3interrupt identifies register address */ +#define REG_FCR3_ADDR 0x32 /* serial port3FIFO controls register address */ +#define REG_LCR3_ADDR 0x33 /* serial port3circuit control register address */ +#define REG_MCR3_ADDR 0x34 /* serial port3MODEM controls register address */ +#define REG_LSR3_ADDR 0x35 /* serial port3line status register address */ +#define REG_MSR3_ADDR 0x36 /* serial port3address of MODEM status register */ +#define REG_SCR3_ADDR 0x37 /* serial port3the user can define the register address */ +#define REG_DLL3_ADDR 0x30 /* Baud rate divisor latch low 8-bit byte address */ +#define REG_DLM3_ADDR 0x31 /* Baud rate divisor latch high 8-bit byte address */ + + +/* CH438serial port4 register address */ + +#define REG_RBR4_ADDR 0x08 /* serial port4receive buffer register address */ +#define REG_THR4_ADDR 0x08 /* serial port4send hold register address */ +#define REG_IER4_ADDR 0x09 /* serial port4interrupt enable register address */ +#define REG_IIR4_ADDR 0x0A /* serial port4interrupt identifies register address */ +#define REG_FCR4_ADDR 0x0A /* serial port4FIFO controls register address */ +#define REG_LCR4_ADDR 0x0B /* serial port4circuit control register address */ +#define REG_MCR4_ADDR 0x0C /* serial port4MODEM controls register address */ +#define REG_LSR4_ADDR 0x0D /* serial port4line status register address */ +#define REG_MSR4_ADDR 0x0E /* serial port4address of MODEM status register */ +#define REG_SCR4_ADDR 0x0F /* serial port4the user can define the register address */ +#define REG_DLL4_ADDR 0x08 /* Baud rate divisor latch low 8-bit byte address */ +#define REG_DLM4_ADDR 0x09 /* Baud rate divisor latch high 8-bit byte address */ + + + +/* CH438serial port5 register address */ + +#define REG_RBR5_ADDR 0x18 /* serial port5receive buffer register address */ +#define REG_THR5_ADDR 0x18 /* serial port5send hold register address */ +#define REG_IER5_ADDR 0x19 /* serial port5interrupt enable register address */ +#define REG_IIR5_ADDR 0x1A /* serial port5interrupt identifies register address */ +#define REG_FCR5_ADDR 0x1A /* serial port5FIFO controls register address */ +#define REG_LCR5_ADDR 0x1B /* serial port5circuit control register address */ +#define REG_MCR5_ADDR 0x1C /* serial port5MODEM controls register address */ +#define REG_LSR5_ADDR 0x1D /* serial port5line status register address */ +#define REG_MSR5_ADDR 0x1E /* serial port5address of MODEM status register */ +#define REG_SCR5_ADDR 0x1F /* serial port5the user can define the register address */ +#define REG_DLL5_ADDR 0x18 /* Baud rate divisor latch low 8-bit byte address */ +#define REG_DLM5_ADDR 0x19 /* Baud rate divisor latch high 8-bit byte address */ + + +/* CH438serial port6 register address */ + +#define REG_RBR6_ADDR 0x28 /* serial port6receive buffer register address */ +#define REG_THR6_ADDR 0x28 /* serial port6send hold register address */ +#define REG_IER6_ADDR 0x29 /* serial port6interrupt enable register address */ +#define REG_IIR6_ADDR 0x2A /* serial port6interrupt identifies register address */ +#define REG_FCR6_ADDR 0x2A /* serial port6FIFO controls register address */ +#define REG_LCR6_ADDR 0x2B /* serial port6circuit control register address */ +#define REG_MCR6_ADDR 0x2C /* serial port6MODEM controls register address */ +#define REG_LSR6_ADDR 0x2D /* serial port6line status register address */ +#define REG_MSR6_ADDR 0x2E /* serial port6address of MODEM status register */ +#define REG_SCR6_ADDR 0x2F /* serial port6the user can define the register address */ +#define REG_DLL6_ADDR 0x28 /* Baud rate divisor latch low 8-bit byte address */ +#define REG_DLM6_ADDR 0x29 /* Baud rate divisor latch high 8-bit byte address */ + + +/* CH438serial port7 register address */ + +#define REG_RBR7_ADDR 0x38 /* serial port7receive buffer register address */ +#define REG_THR7_ADDR 0x38 /* serial port7send hold register address */ +#define REG_IER7_ADDR 0x39 /* serial port7interrupt enable register address */ +#define REG_IIR7_ADDR 0x3A /* serial port7interrupt identifies register address */ +#define REG_FCR7_ADDR 0x3A /* serial port7FIFO controls register address */ +#define REG_LCR7_ADDR 0x3B /* serial port7circuit control register address */ +#define REG_MCR7_ADDR 0x3C /* serial port7MODEM controls register address */ +#define REG_LSR7_ADDR 0x3D /* serial port7line status register address */ +#define REG_MSR7_ADDR 0x3E /* serial port7address of MODEM status register */ +#define REG_SCR7_ADDR 0x3F /* serial port7the user can define the register address */ +#define REG_DLL7_ADDR 0x38 /* Baud rate divisor latch low 8-bit byte address */ +#define REG_DLM7_ADDR 0x39 /* Baud rate divisor latch high 8-bit byte address */ + + +#define REG_SSR_ADDR 0x4F /* pecial status register address */ + + +/* IER register bit */ + +#define BIT_IER_RESET 0x80 /* The bit is 1 soft reset serial port */ +#define BIT_IER_LOWPOWER 0x40 /* The bit is 1 close serial port internal reference clock */ +#define BIT_IER_SLP 0x20 /* serial port0 is SLP, 1 close clock vibrator */ +#define BIT_IER1_CK2X 0x20 /* serial port1 is CK2X, 1 force the external clock signal after 2 times as internal reference clock */ +#define BIT_IER_IEMODEM 0x08 /* The bit is 1 allows MODEM input status to interrupt */ +#define BIT_IER_IELINES 0x04 /* The bit is 1 allow receiving line status to be interrupted */ +#define BIT_IER_IETHRE 0x02 /* The bit is 1 allows the send hold register to break in mid-air */ +#define BIT_IER_IERECV 0x01 /* The bit is 1 allows receiving data interrupts */ + +/* IIR register bit */ + +#define BIT_IIR_FIFOENS1 0x80 +#define BIT_IIR_FIFOENS0 0x40 /* The two is 1 said use FIFO */ + +/* Interrupt type: 0001 has no interrupt, 0110 receiving line status is interrupted, 0100 receiving data can be interrupted, +1100 received data timeout interrupt, 0010THR register air interrupt, 0000MODEM input change interrupt */ +#define BIT_IIR_IID3 0x08 +#define BIT_IIR_IID2 0x04 +#define BIT_IIR_IID1 0x02 +#define BIT_IIR_NOINT 0x01 + +/* FCR register bit */ + +/* Trigger point: 00 corresponds to 1 byte, 01 corresponds to 16 bytes, 10 corresponds to 64 bytes, 11 corresponds to 112 bytes */ +#define BIT_FCR_RECVTG1 0x80 /* Set the trigger point for FIFO interruption and automatic hardware flow control */ +#define BIT_FCR_RECVTG0 0x40 /* Set the trigger point for FIFO interruption and automatic hardware flow control */ + +#define BIT_FCR_TFIFORST 0x04 /* The bit is 1 empty the data sent in FIFO */ +#define BIT_FCR_RFIFORST 0x02 /* The bit is 1 empty the data sent in FIFO */ +#define BIT_FCR_FIFOEN 0x01 /* The bit is 1 use FIFO, 0 disable FIFO */ + +/* LCR register bit */ + +#define BIT_LCR_DLAB 0x80 /* To access DLL, DLM, 0 to access RBR/THR/IER */ +#define BIT_LCR_BREAKEN 0x40 /* 1 forces a BREAK line interval*/ + +/* Set the check format: when PAREN is 1, 00 odd check, 01 even check, 10 MARK (set 1), 11 blank (SPACE, clear 0) */ +#define BIT_LCR_PARMODE1 0x20 /* Sets the parity bit format */ +#define BIT_LCR_PARMODE0 0x10 /* Sets the parity bit format */ + +#define BIT_LCR_PAREN 0x08 /* A value of 1 allows you to generate and receive parity bits when sending */ +#define BIT_LCR_STOPBIT 0x04 /* If is 1, then two stop bits, is 0, a stop bit */ + +/* Set word length: 00 for 5 data bits, 01 for 6 data bits, 10 for 7 data bits and 11 for 8 data bits */ +#define BIT_LCR_WORDSZ1 0x02 /* Set the word length length */ +#define BIT_LCR_WORDSZ0 0x01 + +/* MCR register bit */ + +#define BIT_MCR_AFE 0x20 /* For 1 allows automatic flow control of CTS and RTS hardware */ +#define BIT_MCR_LOOP 0x10 /* Is the test mode of 1 enabling internal loop */ +#define BIT_MCR_OUT2 0x08 /* 1 Allows an interrupt request for the serial port output */ +#define BIT_MCR_OUT1 0x04 /* The MODEM control bit defined for the user */ +#define BIT_MCR_RTS 0x02 /* The bit is 1 RTS pin output effective */ +#define BIT_MCR_DTR 0x01 /* The bit is 1 DTR pin output effective */ + +/* LSR register bit */ + +#define BIT_LSR_RFIFOERR 0x80 /* 1 said There is at least one error in receiving FIFO */ +#define BIT_LSR_TEMT 0x40 /* 1 said THR and TSR are empty */ +#define BIT_LSR_THRE 0x20 /* 1 said THR is empty*/ +#define BIT_LSR_BREAKINT 0x10 /* The bit is 1 said the BREAK line interval was detected*/ +#define BIT_LSR_FRAMEERR 0x08 /* The bit is 1 said error reading data frame */ +#define BIT_LSR_PARERR 0x04 /* The bit is 1 said parity error */ +#define BIT_LSR_OVERR 0x02 /* 1 said receive FIFO buffer overflow */ +#define BIT_LSR_DATARDY 0x01 /* The bit is 1 said receive data received in FIFO */ + +/* MSR register bit */ + +#define BIT_MSR_DCD 0x80 /* The bit is 1 said DCD pin effective */ +#define BIT_MSR_RI 0x40 /* The bit is 1 said RI pin effective */ +#define BIT_MSR_DSR 0x20 /* The bit is 1 said DSR pin effective */ +#define BIT_MSR_CTS 0x10 /* The bit is 1 said CTS pin effective */ +#define BIT_MSR_DDCD 0x08 /* The bit is 1 said DCD pin The input state has changed */ +#define BIT_MSR_TERI 0x04 /* The bit is 1 said RI pin The input state has changed */ +#define BIT_MSR_DDSR 0x02 /* The bit is 1 said DSR pin The input state has changed */ +#define BIT_MSR_DCTS 0x01 /* The bit is 1 said CTS pin The input state has changed */ + +/* Interrupt status code */ + +#define INT_NOINT 0x01 /* There is no interruption */ +#define INT_THR_EMPTY 0x02 /* THR empty interruption */ +#define INT_RCV_OVERTIME 0x0C /* Receive timeout interrupt */ +#define INT_RCV_SUCCESS 0x04 /* Interrupts are available to receive data */ +#define INT_RCV_LINES 0x06 /* Receiving line status interrupted */ +#define INT_MODEM_CHANGE 0x00 /* MODEM input changes interrupt */ + +#define CH438_IIR_FIFOS_ENABLED 0xC0 /* use FIFO */ + +#define Fpclk 1843200 /* Define the internal clock frequency */ + +#if 0 +#define CH438_D0_PIN GET_PIN(E,2) +#define CH438_D1_PIN GET_PIN(E,3) +#define CH438_D2_PIN GET_PIN(E,4) +#define CH438_D3_PIN GET_PIN(E,5) +#define CH438_D4_PIN GET_PIN(E,6) +#define CH438_D5_PIN GET_PIN(F,6) +#define CH438_D6_PIN GET_PIN(F,7) +#define CH438_D7_PIN GET_PIN(F,8) +#define CH438_NWR_PIN GET_PIN(C,4) +#define CH438_NRD_PIN GET_PIN(C,5) +#define CH438_NCS_PIN GET_PIN(B,1) +#define CH438_ALE_PIN GET_PIN(B,2) +#define CH438_INT_PIN GET_PIN(C,13) +#endif +#define CH438_D0_PIN 1 +#define CH438_D1_PIN 2 +#define CH438_D2_PIN 3 +#define CH438_D3_PIN 4 +#define CH438_D4_PIN 5 +#define CH438_D5_PIN 18 +#define CH438_D6_PIN 19 +#define CH438_D7_PIN 20 +#define CH438_NWR_PIN 44 +#define CH438_NRD_PIN 45 +#define CH438_NCS_PIN 47 +#define CH438_ALE_PIN 48 +#define CH438_INT_PIN 7 +#define DIR_485CH1_PIN 22 //485ch1 = ext_uart3 +#define DIR_485CH2_PIN 21 //485ch2 = ext_uart2 +#define DIR_485CH3_PIN 123 //485ch3 = ext_uart7 + +void CH438RegTest(unsigned char num); +void Set485Input(uint8 ch_no); +void Set485Output(uint8 ch_no); + +#endif diff --git a/Ubiquitous/XiZi/board/aiit-arm32-board/third_party_driver/include/connect_dac.h b/Ubiquitous/XiZi/board/aiit-arm32-board/third_party_driver/include/connect_dac.h new file mode 100644 index 0000000..dfc801a --- /dev/null +++ b/Ubiquitous/XiZi/board/aiit-arm32-board/third_party_driver/include/connect_dac.h @@ -0,0 +1,37 @@ +/* +* Copyright (c) 2020 AIIT XUOS Lab +* XiUOS is licensed under Mulan PSL v2. +* You can use this software according to the terms and conditions of the Mulan PSL v2. +* You may obtain a copy of Mulan PSL v2 at: +* http://license.coscl.org.cn/MulanPSL2 +* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, +* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, +* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. +* See the Mulan PSL v2 for more details. +*/ + +/** +* @file connect_dac.h +* @brief define aiit-arm32-board adc function and struct +* @version 2.0 +* @author AIIT XUOS Lab +* @date 2022-1-10 +*/ + +#ifndef CONNECT_DAC_H +#define CONNECT_DAC_H + +#include +#include +#include +#include + +struct Stm32HwDac +{ + DAC_TypeDef *DACx; + uint16 digital_data; +}; + +int Stm32HwDacInit(void); + +#endif diff --git a/Ubiquitous/XiZi/board/aiit-arm32-board/third_party_driver/include/connect_extmem.h b/Ubiquitous/XiZi/board/aiit-arm32-board/third_party_driver/include/connect_extmem.h new file mode 100644 index 0000000..57c8c43 --- /dev/null +++ b/Ubiquitous/XiZi/board/aiit-arm32-board/third_party_driver/include/connect_extmem.h @@ -0,0 +1,36 @@ +/* +* Copyright (c) 2020 AIIT XUOS Lab +* XiUOS is licensed under Mulan PSL v2. +* You can use this software according to the terms and conditions of the Mulan PSL v2. +* You may obtain a copy of Mulan PSL v2 at: +* http://license.coscl.org.cn/MulanPSL2 +* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, +* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, +* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. +* See the Mulan PSL v2 for more details. +*/ + +/** +* @file connect_extmem.h +* @brief declare aiit-arm32-board extmem fsmc function +* @version 1.0 +* @author AIIT XUOS Lab +* @date 2021-05-28 +*/ + +#ifndef CONNECT_EXTMEM_H +#define CONNECT_EXTMEM_H + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +int HwSramInit(void); + +#ifdef __cplusplus +} +#endif + +#endif \ No newline at end of file diff --git a/Ubiquitous/XiZi/board/aiit-arm32-board/third_party_driver/include/connect_gpio.h b/Ubiquitous/XiZi/board/aiit-arm32-board/third_party_driver/include/connect_gpio.h new file mode 100644 index 0000000..f6c4476 --- /dev/null +++ b/Ubiquitous/XiZi/board/aiit-arm32-board/third_party_driver/include/connect_gpio.h @@ -0,0 +1,88 @@ +/* +* Copyright (c) 2020 AIIT XUOS Lab +* XiUOS is licensed under Mulan PSL v2. +* You can use this software according to the terms and conditions of the Mulan PSL v2. +* You may obtain a copy of Mulan PSL v2 at: +* http://license.coscl.org.cn/MulanPSL2 +* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, +* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, +* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. +* See the Mulan PSL v2 for more details. +*/ + +/** +* @file connect_gpio.h +* @brief define aiit-arm32-board gpio function and struct +* @version 1.0 +* @author AIIT XUOS Lab +* @date 2021-04-25 +*/ + +#ifndef CONNECT_GPIO_H +#define CONNECT_GPIO_H + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +#define BITBAND(addr, bitnum) ((addr & 0xF0000000)+0x2000000+((addr &0xFFFFF)<<5)+(bitnum<<2)) +#define MEM_ADDR(addr) (*((volatile unsigned long *)(addr))) +#define BIT_ADDR(addr, bitnum) MEM_ADDR(BITBAND(addr, bitnum)) + +#define GPIOA_ODR_Addr (GPIOA_BASE+20) //0x40020014 +#define GPIOB_ODR_Addr (GPIOB_BASE+20) //0x40020414 +#define GPIOC_ODR_Addr (GPIOC_BASE+20) //0x40020814 +#define GPIOD_ODR_Addr (GPIOD_BASE+20) //0x40020C14 +#define GPIOE_ODR_Addr (GPIOE_BASE+20) //0x40021014 +#define GPIOF_ODR_Addr (GPIOF_BASE+20) //0x40021414 +#define GPIOG_ODR_Addr (GPIOG_BASE+20) //0x40021814 +#define GPIOH_ODR_Addr (GPIOH_BASE+20) //0x40021C14 +#define GPIOI_ODR_Addr (GPIOI_BASE+20) //0x40022014 + +#define GPIOA_IDR_Addr (GPIOA_BASE+16) //0x40020010 +#define GPIOB_IDR_Addr (GPIOB_BASE+16) //0x40020410 +#define GPIOC_IDR_Addr (GPIOC_BASE+16) //0x40020810 +#define GPIOD_IDR_Addr (GPIOD_BASE+16) //0x40020C10 +#define GPIOE_IDR_Addr (GPIOE_BASE+16) //0x40021010 +#define GPIOF_IDR_Addr (GPIOF_BASE+16) //0x40021410 +#define GPIOG_IDR_Addr (GPIOG_BASE+16) //0x40021810 +#define GPIOH_IDR_Addr (GPIOH_BASE+16) //0x40021C10 +#define GPIOI_IDR_Addr (GPIOI_BASE+16) //0x40022010 + + +#define PAout(n) BIT_ADDR(GPIOA_ODR_Addr,n) //output +#define PAin(n) BIT_ADDR(GPIOA_IDR_Addr,n) //input + +#define PBout(n) BIT_ADDR(GPIOB_ODR_Addr,n) //output +#define PBin(n) BIT_ADDR(GPIOB_IDR_Addr,n) //input + +#define PCout(n) BIT_ADDR(GPIOC_ODR_Addr,n) //output +#define PCin(n) BIT_ADDR(GPIOC_IDR_Addr,n) //input + +#define PDout(n) BIT_ADDR(GPIOD_ODR_Addr,n) //output +#define PDin(n) BIT_ADDR(GPIOD_IDR_Addr,n) //input + +#define PEout(n) BIT_ADDR(GPIOE_ODR_Addr,n) //output +#define PEin(n) BIT_ADDR(GPIOE_IDR_Addr,n) //input + +#define PFout(n) BIT_ADDR(GPIOF_ODR_Addr,n) //output +#define PFin(n) BIT_ADDR(GPIOF_IDR_Addr,n) //input + +#define PGout(n) BIT_ADDR(GPIOG_ODR_Addr,n) //output +#define PGin(n) BIT_ADDR(GPIOG_IDR_Addr,n) //input + +#define PHout(n) BIT_ADDR(GPIOH_ODR_Addr,n) //output +#define PHin(n) BIT_ADDR(GPIOH_IDR_Addr,n) //input + +#define PIout(n) BIT_ADDR(GPIOI_ODR_Addr,n) //output +#define PIin(n) BIT_ADDR(GPIOI_IDR_Addr,n) //input + +int Stm32HwGpioInit(void); + +#ifdef __cplusplus +} +#endif + +#endif \ No newline at end of file diff --git a/Ubiquitous/XiZi/board/aiit-arm32-board/third_party_driver/include/connect_hwtimer.h b/Ubiquitous/XiZi/board/aiit-arm32-board/third_party_driver/include/connect_hwtimer.h new file mode 100644 index 0000000..acecd9e --- /dev/null +++ b/Ubiquitous/XiZi/board/aiit-arm32-board/third_party_driver/include/connect_hwtimer.h @@ -0,0 +1,36 @@ +/* +* Copyright (c) 2020 AIIT XUOS Lab +* XiUOS is licensed under Mulan PSL v2. +* You can use this software according to the terms and conditions of the Mulan PSL v2. +* You may obtain a copy of Mulan PSL v2 at: +* http://license.coscl.org.cn/MulanPSL2 +* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, +* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, +* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. +* See the Mulan PSL v2 for more details. +*/ + +/** +* @file connect_hwtimer.h +* @brief define aiit-arm32-board hwtimer function and struct +* @version 1.0 +* @author AIIT XUOS Lab +* @date 2021-04-25 +*/ + +#ifndef CONNECT_HWTIMER_H +#define CONNECT_HWTIMER_H + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +int Stm32HwtimerInit(void); + +#ifdef __cplusplus +} +#endif + +#endif \ No newline at end of file diff --git a/Ubiquitous/XiZi/board/aiit-arm32-board/third_party_driver/include/connect_i2c.h b/Ubiquitous/XiZi/board/aiit-arm32-board/third_party_driver/include/connect_i2c.h new file mode 100644 index 0000000..8ab6897 --- /dev/null +++ b/Ubiquitous/XiZi/board/aiit-arm32-board/third_party_driver/include/connect_i2c.h @@ -0,0 +1,37 @@ +/* +* Copyright (c) 2020 AIIT XUOS Lab +* XiUOS is licensed under Mulan PSL v2. +* You can use this software according to the terms and conditions of the Mulan PSL v2. +* You may obtain a copy of Mulan PSL v2 at: +* http://license.coscl.org.cn/MulanPSL2 +* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, +* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, +* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. +* See the Mulan PSL v2 for more details. +*/ + +/** +* @file connect_i2c.h +* @brief define aiit-arm32-board i2c function and struct +* @version 1.0 +* @author AIIT XUOS Lab +* @date 2021-04-25 +*/ + +#ifndef CONNECT_I2C_H +#define CONNECT_I2C_H + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +int Stm32Udelay(uint32 us); +int Stm32HwI2cInit(void); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/Ubiquitous/XiZi/board/aiit-arm32-board/third_party_driver/include/connect_lcd.h b/Ubiquitous/XiZi/board/aiit-arm32-board/third_party_driver/include/connect_lcd.h new file mode 100644 index 0000000..2fe5376 --- /dev/null +++ b/Ubiquitous/XiZi/board/aiit-arm32-board/third_party_driver/include/connect_lcd.h @@ -0,0 +1,164 @@ +/* +* Copyright (c) 2020 AIIT XUOS Lab +* XiUOS is licensed under Mulan PSL v2. +* You can use this software according to the terms and conditions of the Mulan PSL v2. +* You may obtain a copy of Mulan PSL v2 at: +* http://license.coscl.org.cn/MulanPSL2 +* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, +* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, +* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. +* See the Mulan PSL v2 for more details. +*/ + +/** +* @file connect_lcd.h +* @brief declare aiit-arm32-board lcd fsmc function +* @version 2.0 +* @author AIIT XUOS Lab +* @date 2022-1-12 +*/ + +#ifndef CONNECT_LCD_H +#define CONNECT_LCD_H + +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +#define ILI9341 0x9341 + +#define NO_OPERATION 0x00 +#define SOFTWARE_RESET 0x01 +#define READ_ID 0x04 +#define READ_STATUS 0x09 +#define READ_POWER_MODE 0x0A +#define READ_MADCTL 0x0B +#define READ_PIXEL_FORMAT 0x0C +#define READ_IMAGE_FORMAT 0x0D +#define READ_SIGNAL_MODE 0x0E +#define READ_SELT_DIAG_RESULT 0x0F +#define SLEEP_ON 0x10 +#define SLEEP_OFF 0x11 +#define PARTIAL_DISPALY_ON 0x12 +#define NORMAL_DISPALY_ON 0x13 +#define INVERSION_DISPALY_OFF 0x20 +#define INVERSION_DISPALY_ON 0x21 +#define GAMMA_SET 0x26 +#define DISPALY_OFF 0x28 +#define DISPALY_ON 0x29 +#define HORIZONTAL_ADDRESS_SET 0x2A +#define VERTICAL_ADDRESS_SET 0x2B +#define MEMORY_WRITE 0x2C +#define COLOR_SET 0x2D +#define MEMORY_READ 0x2E +#define PARTIAL_AREA 0x30 +#define VERTICAL_SCROL_DEFINE 0x33 +#define TEAR_EFFECT_LINE_OFF 0x34 +#define TEAR_EFFECT_LINE_ON 0x35 +#define MEMORY_ACCESS_CTL 0x36 +#define VERTICAL_SCROL_S_ADD 0x37 +#define IDLE_MODE_OFF 0x38 +#define IDLE_MODE_ON 0x39 +#define PIXEL_FORMAT_SET 0x3A +#define WRITE_MEMORY_CONTINUE 0x3C +#define READ_MEMORY_CONTINUE 0x3E +#define SET_TEAR_SCANLINE 0x44 +#define GET_SCANLINE 0x45 +#define WRITE_BRIGHTNESS 0x51 +#define READ_BRIGHTNESS 0x52 +#define WRITE_CTRL_DISPALY 0x53 +#define READ_CTRL_DISPALY 0x54 +#define WRITE_BRIGHTNESS_CTL 0x55 +#define READ_BRIGHTNESS_CTL 0x56 +#define WRITE_MIN_BRIGHTNESS 0x5E +#define READ_MIN_BRIGHTNESS 0x5F +#define READ_ID1 0xDA +#define READ_ID2 0xDB +#define READ_ID3 0xDC +#define RGB_IF_SIGNAL_CTL 0xB0 +#define NORMAL_FRAME_CTL 0xB1 +#define IDLE_FRAME_CTL 0xB2 +#define PARTIAL_FRAME_CTL 0xB3 +#define INVERSION_CTL 0xB4 +#define BLANK_PORCH_CTL 0xB5 +#define DISPALY_FUNCTION_CTL 0xB6 +#define ENTRY_MODE_SET 0xB7 +#define BACKLIGHT_CTL1 0xB8 +#define BACKLIGHT_CTL2 0xB9 +#define BACKLIGHT_CTL3 0xBA +#define BACKLIGHT_CTL4 0xBB +#define BACKLIGHT_CTL5 0xBC +#define BACKLIGHT_CTL7 0xBE +#define BACKLIGHT_CTL8 0xBF +#define POWER_CTL1 0xC0 +#define POWER_CTL2 0xC1 +#define VCOM_CTL1 0xC5 +#define VCOM_CTL2 0xC7 +#define NV_MEMORY_WRITE 0xD0 +#define NV_MEMORY_PROTECT_KEY 0xD1 +#define NV_MEMORY_STATUS_READ 0xD2 +#define READ_ID4 0xD3 +#define POSITIVE_GAMMA_CORRECT 0xE0 +#define NEGATIVE_GAMMA_CORRECT 0xE1 +#define DIGITAL_GAMMA_CTL1 0xE2 +#define DIGITAL_GAMMA_CTL2 0xE3 +#define INTERFACE_CTL 0xF6 + +#define LCD_VERTICAL_SCEEN 0 +#define LCD_HORIZONTAL_SCEEN 1 + +//LCD Scan Direction +#define L2R_U2D 0 //from left to right , from up to down +#define L2R_D2U 1 +#define R2L_U2D 2 +#define R2L_D2U 3 + +#define U2D_L2R 4 +#define U2D_R2L 5 +#define D2U_L2R 6 +#define D2U_R2L 7 + +#define DFT_SCAN_DIR U2D_R2L //default scan direction + +#define FSMC_BANK1_NORSRAM4_START_ADDRESS 0x6C000000 +#define FSMC_BANK1_NORSRAM4_DATA_WIDTH 16 +#define STM32_FSMC_OFFSET 0x0000007E + +typedef struct +{ + volatile uint16_t LCD_REG_CMD;//0x6C00007E, ADDR_A6 = 0, RS =0, write CMD + volatile uint16_t LCD_RAM_DATA;//0x6C000080, ADDR_A6 =1, RS = 1, write DATA +} LCD_TypeDef; + +#ifndef AIIT_BOARD_LCD_BASE +#define AIIT_BOARD_LCD_BASE ((uint32_t)(FSMC_BANK1_NORSRAM4_START_ADDRESS | STM32_FSMC_OFFSET)) +#define AIIT_BOARD_LCD ((LCD_TypeDef *) AIIT_BOARD_LCD_BASE) +#endif + +typedef struct +{ + uint16_t width; + uint16_t height; + uint16_t lcd_id; + uint8_t lcd_direction; //0，Vertical screen；1，Horizontal screen + uint16_t write_ram_cmd; + uint16_t set_x_cmd; + uint16_t set_y_cmd; +} LCD_PARAM; + +struct Stm32HwLcd +{ + LCD_TypeDef *LCD; + LCD_PARAM lcd_param; +}; + +int Stm32HwLcdInit(void); + +#ifdef __cplusplus +} +#endif + +#endif \ No newline at end of file diff --git a/Ubiquitous/XiZi/board/aiit-arm32-board/third_party_driver/include/connect_rtc.h b/Ubiquitous/XiZi/board/aiit-arm32-board/third_party_driver/include/connect_rtc.h new file mode 100644 index 0000000..369b3cf --- /dev/null +++ b/Ubiquitous/XiZi/board/aiit-arm32-board/third_party_driver/include/connect_rtc.h @@ -0,0 +1,38 @@ +/* +* Copyright (c) 2020 AIIT XUOS Lab +* XiUOS is licensed under Mulan PSL v2. +* You can use this software according to the terms and conditions of the Mulan PSL v2. +* You may obtain a copy of Mulan PSL v2 at: +* http://license.coscl.org.cn/MulanPSL2 +* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, +* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, +* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. +* See the Mulan PSL v2 for more details. +*/ + +/** +* @file connect_i2c.h +* @brief define aiit-arm32-board i2c function and struct +* @version 1.0 +* @author AIIT XUOS Lab +* @date 2021-04-25 +*/ + +#ifndef CONNECT_RTC_H +#define CONNECT_RTC_H + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +#define RTC_CLOCK_SOURCE_LSI + +int Stm32HwRtcInit(void); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/Ubiquitous/XiZi/board/aiit-arm32-board/third_party_driver/include/connect_sdio.h b/Ubiquitous/XiZi/board/aiit-arm32-board/third_party_driver/include/connect_sdio.h new file mode 100644 index 0000000..13e923e --- /dev/null +++ b/Ubiquitous/XiZi/board/aiit-arm32-board/third_party_driver/include/connect_sdio.h @@ -0,0 +1,38 @@ +/* +* Copyright (c) 2020 AIIT XUOS Lab +* XiUOS is licensed under Mulan PSL v2. +* You can use this software according to the terms and conditions of the Mulan PSL v2. +* You may obtain a copy of Mulan PSL v2 at: +* http://license.coscl.org.cn/MulanPSL2 +* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, +* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, +* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. +* See the Mulan PSL v2 for more details. +*/ + +/** +* @file connect_sdio.h +* @brief define aiit-arm32-board sdio function and struct +* @version 1.0 +* @author AIIT XUOS Lab +* @date 2021-04-25 +*/ + +#ifndef CONNECT_SDIO_H +#define CONNECT_SDIO_H + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +#define SDIO_DMA_MODE 1 + +int HwSdioInit(void); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/Ubiquitous/XiZi/board/aiit-arm32-board/third_party_driver/include/connect_spi.h b/Ubiquitous/XiZi/board/aiit-arm32-board/third_party_driver/include/connect_spi.h new file mode 100644 index 0000000..3dc8b50 --- /dev/null +++ b/Ubiquitous/XiZi/board/aiit-arm32-board/third_party_driver/include/connect_spi.h @@ -0,0 +1,78 @@ +/* +* Copyright (c) 2020 AIIT XUOS Lab +* XiUOS is licensed under Mulan PSL v2. +* You can use this software according to the terms and conditions of the Mulan PSL v2. +* You may obtain a copy of Mulan PSL v2 at: +* http://license.coscl.org.cn/MulanPSL2 +* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, +* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, +* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. +* See the Mulan PSL v2 for more details. +*/ + +/** +* @file connect_spi.h +* @brief define aiit-arm32-board spi function and struct +* @version 1.0 +* @author AIIT XUOS Lab +* @date 2021-04-25 +*/ + +#ifndef CONNECT_SPI_H +#define CONNECT_SPI_H + +#include +#include +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +#define SPI_USING_RX_DMA_FLAG (1<<0) +#define SPI_USING_TX_DMA_FLAG (1<<1) + +struct Stm32HwSpiCs +{ + GPIO_TypeDef* GPIOx; + uint16_t GPIO_Pin; +}; + +struct Stm32SpiDma +{ + uint32_t dma_rcc; + DMA_Stream_TypeDef *instance; + uint32 channel; + IRQn_Type dma_irq; + DMA_InitTypeDef init; + x_size_t setting_len; + x_size_t last_index; +}; + +struct Stm32Spi +{ + SPI_TypeDef *instance; + + char *bus_name; + + SPI_InitTypeDef init; + + struct + { + struct Stm32SpiDma dma_rx; + struct Stm32SpiDma dma_tx; + }dma; + + uint8 spi_dma_flag; + struct SpiBus spi_bus; +}; + +int Stm32HwSpiInit(void); +x_err_t HwSpiDeviceAttach(const char *bus_name, const char *device_name, GPIO_TypeDef *cs_gpiox, uint16_t cs_gpio_pin); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/Ubiquitous/XiZi/board/aiit-arm32-board/third_party_driver/include/connect_spi_lora.h b/Ubiquitous/XiZi/board/aiit-arm32-board/third_party_driver/include/connect_spi_lora.h new file mode 100644 index 0000000..9ebf95b --- /dev/null +++ b/Ubiquitous/XiZi/board/aiit-arm32-board/third_party_driver/include/connect_spi_lora.h @@ -0,0 +1,63 @@ +/* +* Copyright (c) 2020 AIIT XUOS Lab +* XiUOS is licensed under Mulan PSL v2. +* You can use this software according to the terms and conditions of the Mulan PSL v2. +* You may obtain a copy of Mulan PSL v2 at: +* http://license.coscl.org.cn/MulanPSL2 +* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, +* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, +* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. +* See the Mulan PSL v2 for more details. +*/ + +/** +* @file connect_spi_lora.h +* @brief define spi lora dev function and struct using bus driver framework +* @version 1.0 +* @author AIIT XUOS Lab +* @date 2021-04-24 +*/ + +#ifndef CONNECT_SPI_LORA_H +#define CONNECT_SPI_LORA_H + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +#define SPI_LORA_FREQUENCY 10000000 +#define SPI_LORA_BUFFER_SIZE 256 + +typedef struct SpiLoraDevice *SpiLoraDeviceType; + +struct LoraDevDone +{ + uint32 (*open) (void *dev); + uint32 (*close) (void *dev); + uint32 (*write) (void *dev, struct BusBlockWriteParam *write_param); + uint32 (*read) (void *dev, struct BusBlockReadParam *read_param); +}; + +struct SpiLoraDevice +{ + struct SpiHardwareDevice *spi_dev; + struct SpiHardwareDevice lora_dev; +}; + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/Ubiquitous/XiZi/board/aiit-arm32-board/third_party_driver/include/connect_touch.h b/Ubiquitous/XiZi/board/aiit-arm32-board/third_party_driver/include/connect_touch.h new file mode 100644 index 0000000..d1e6a06 --- /dev/null +++ b/Ubiquitous/XiZi/board/aiit-arm32-board/third_party_driver/include/connect_touch.h @@ -0,0 +1,60 @@ +/* + * Copyright (c) Guangzhou Xingyi Electronic Technology Co., Ltd + * + * Change Logs: + * Date Author Notes + * 2014-5-7 alientek team first version + */ + +/** +* @file connect_touch.c +* @brief support aiit-arm32-board touch function and register to bus framework +* @version 1.0 +* @author AIIT XUOS Lab +* @date 2021-04-25 +*/ +#ifndef CONNECT_TOUCH_H +#define CONNECT_TOUCH_H + +#include +#include + +#define TP_PRES_DOWN 0x80 +#define TP_CATH_PRES 0x40 + +//touch screen control struct +typedef struct +{ + u16 x; + u16 y; + u8 sta; + float xfac; + float yfac; + short xoff; + short yoff; + u8 touchtype; +}touch_device_info; + +extern touch_device_info tp_dev; + +//save data struct +typedef struct +{ + s32 ty_xfac; + s32 ty_yfac; + short x_pos; + short y_pos; + u8 iic_touchtype; + u8 iic_flag; +}TP_modify_save; + +//io pin define +#define PEN PDin(6) +#define T_MISO PBin(4) +#define T_MOSI PBout(5) +#define T_CLK PBout(3) +#define TCS PGout(13) + +int Stm32HwTouchBusInit(void); + +#endif diff --git a/Ubiquitous/XiZi/board/aiit-arm32-board/third_party_driver/include/connect_usart.h b/Ubiquitous/XiZi/board/aiit-arm32-board/third_party_driver/include/connect_usart.h new file mode 100644 index 0000000..04a3491 --- /dev/null +++ b/Ubiquitous/XiZi/board/aiit-arm32-board/third_party_driver/include/connect_usart.h @@ -0,0 +1,63 @@ +/* +* Copyright (c) 2020 AIIT XUOS Lab +* XiUOS is licensed under Mulan PSL v2. +* You can use this software according to the terms and conditions of the Mulan PSL v2. +* You may obtain a copy of Mulan PSL v2 at: +* http://license.coscl.org.cn/MulanPSL2 +* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, +* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, +* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. +* See the Mulan PSL v2 for more details. +*/ + +/** +* @file connect_usart.h +* @brief define aiit-arm32-board usart function and struct +* @version 1.0 +* @author AIIT XUOS Lab +* @date 2021-04-25 +*/ + +#ifndef CONNECT_USART_H +#define CONNECT_USART_H + +#include +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +#define KERNEL_CONSOLE_BUS_NAME SERIAL_BUS_NAME_1 +#define KERNEL_CONSOLE_DRV_NAME SERIAL_DRV_NAME_1 +#define KERNEL_CONSOLE_DEVICE_NAME SERIAL_1_DEVICE_NAME_0 + +struct UsartHwCfg +{ + USART_TypeDef *uart_device; + IRQn_Type irq; +}; + +struct Stm32Usart +{ + struct Stm32UsartDma + { + DMA_Stream_TypeDef *RxStream; + uint32 RxCh; + uint32 RxFlag; + uint8 RxIrqCh; + x_size_t SettingRecvLen; + x_size_t LastRecvIndex; + } dma; + + struct SerialBus serial_bus; +}; + +int Stm32HwUsartInit(void); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/Ubiquitous/XiZi/board/aiit-arm32-board/third_party_driver/include/connect_usb.h b/Ubiquitous/XiZi/board/aiit-arm32-board/third_party_driver/include/connect_usb.h new file mode 100644 index 0000000..6ec36a4 --- /dev/null +++ b/Ubiquitous/XiZi/board/aiit-arm32-board/third_party_driver/include/connect_usb.h @@ -0,0 +1,36 @@ +/* +* Copyright (c) 2020 AIIT XUOS Lab +* XiUOS is licensed under Mulan PSL v2. +* You can use this software according to the terms and conditions of the Mulan PSL v2. +* You may obtain a copy of Mulan PSL v2 at: +* http://license.coscl.org.cn/MulanPSL2 +* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, +* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, +* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. +* See the Mulan PSL v2 for more details. +*/ + +/** +* @file connect_usb.h +* @brief define aiit-arm32-board usb function and struct +* @version 1.0 +* @author AIIT XUOS Lab +* @date 2021-04-25 +*/ + +#ifndef CONNECT_USB_H +#define CONNECT_USB_H + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +int Stm32HwUsbInit(void); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/Ubiquitous/XiZi/board/aiit-arm32-board/third_party_driver/include/connect_wdg.h b/Ubiquitous/XiZi/board/aiit-arm32-board/third_party_driver/include/connect_wdg.h new file mode 100644 index 0000000..3a711d5 --- /dev/null +++ b/Ubiquitous/XiZi/board/aiit-arm32-board/third_party_driver/include/connect_wdg.h @@ -0,0 +1,36 @@ +/* +* Copyright (c) 2020 AIIT XUOS Lab +* XiUOS is licensed under Mulan PSL v2. +* You can use this software according to the terms and conditions of the Mulan PSL v2. +* You may obtain a copy of Mulan PSL v2 at: +* http://license.coscl.org.cn/MulanPSL2 +* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, +* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, +* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. +* See the Mulan PSL v2 for more details. +*/ + +/** +* @file connect_wdg.h +* @brief define aiit-arm32-board watchdog function and struct +* @version 1.0 +* @author AIIT XUOS Lab +* @date 2021-04-25 +*/ + +#ifndef CONNECT_WDG_H +#define CONNECT_WDG_H + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +int HwWdtInit(void); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/Ubiquitous/XiZi/board/aiit-arm32-board/third_party_driver/lcd/Kconfig b/Ubiquitous/XiZi/board/aiit-arm32-board/third_party_driver/lcd/Kconfig new file mode 100644 index 0000000..fb419b4 --- /dev/null +++ b/Ubiquitous/XiZi/board/aiit-arm32-board/third_party_driver/lcd/Kconfig @@ -0,0 +1,17 @@ +if BSP_USING_LCD + config LCD_BUS_NAME + string "lcd bus name" + default "lcd" + config LCD_DRV_NAME + string "lcd bus driver name" + default "lcd_drv" + config LCD_DEVICE_NAME + string "lcd bus device name" + default "lcd_dev" + config BSP_LCD_X_MAX + int "LCD Height" + default 240 + config BSP_LCD_Y_MAX + int "LCD Width" + default 320 +endif diff --git a/Ubiquitous/XiZi/board/aiit-arm32-board/third_party_driver/lcd/Makefile b/Ubiquitous/XiZi/board/aiit-arm32-board/third_party_driver/lcd/Makefile new file mode 100644 index 0000000..05bd917 --- /dev/null +++ b/Ubiquitous/XiZi/board/aiit-arm32-board/third_party_driver/lcd/Makefile @@ -0,0 +1,4 @@ +SRC_FILES := connect_lcd.c + + +include $(KERNEL_ROOT)/compiler.mk diff --git a/Ubiquitous/XiZi/board/aiit-arm32-board/third_party_driver/lcd/connect_lcd.c b/Ubiquitous/XiZi/board/aiit-arm32-board/third_party_driver/lcd/connect_lcd.c new file mode 100644 index 0000000..0b2707a --- /dev/null +++ b/Ubiquitous/XiZi/board/aiit-arm32-board/third_party_driver/lcd/connect_lcd.c @@ -0,0 +1,657 @@ +/* + * Copyright (c) Guangzhou Xingyi Electronic Technology Co., Ltd + * + * Change Logs: + * Date Author Notes + * 2014-7-4 alientek first version + */ + +/** +* @file connect_lcd.c +* @brief support aiit-arm32-board lcd function and register to bus framework +* @version 2.0 +* @author AIIT XUOS Lab +* @date 2022-1-12 +*/ + +/************************************************* +File name: connect_lcd.c +Description: support aiit-arm32-board lcd configure and lcd bus register function +Others: take hardware/lcd/lcd.c for references +History: +1. Date: 2022-1-12 +Author: AIIT XUOS Lab +Modification: +1. support aiit-arm32-board lcd configure, write by FSMC function +2. support aiit-arm32-board lcd bus device and driver register +*************************************************/ + +#include +#include +#include +#include +#include + +static int Stm32LcdUdelay(uint32 us) +{ + uint32 ticks; + uint32 told, tnow, tcnt = 0; + uint32 reload = SysTick->LOAD; + + ticks = us * reload / (1000000 / TICK_PER_SECOND); + told = SysTick->VAL; + while (1) { + tnow = SysTick->VAL; + if (tnow != told) { + if (tnow < told) { + tcnt += told - tnow; + } else { + tcnt += reload - tnow + told; + } + told = tnow; + if (tcnt >= ticks) { + return 0; + break; + } + } + } +} + +static void HwFsmcInit() +{ + GPIO_InitTypeDef GPIO_InitStructure; + FSMC_NORSRAMInitTypeDef FSMC_NORSRAMInitStructure; + FSMC_NORSRAMTimingInitTypeDef readWriteTiming; + FSMC_NORSRAMTimingInitTypeDef writeTiming; + + RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOD|RCC_AHB1Periph_GPIOE|RCC_AHB1Periph_GPIOF|RCC_AHB1Periph_GPIOG, ENABLE); + RCC_AHB3PeriphClockCmd(RCC_AHB3Periph_FSMC, ENABLE); + + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_3;//PD3, LCD back light + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_OUT; + GPIO_InitStructure.GPIO_OType = GPIO_OType_PP; + GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz; + GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_UP; + GPIO_Init(GPIOD, &GPIO_InitStructure); + + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0 | GPIO_Pin_1 | GPIO_Pin_4 | GPIO_Pin_5 | GPIO_Pin_8 | GPIO_Pin_9 | GPIO_Pin_10 | GPIO_Pin_14 | GPIO_Pin_15; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF; + GPIO_InitStructure.GPIO_OType = GPIO_OType_PP; + GPIO_InitStructure.GPIO_Speed = GPIO_Speed_100MHz; + GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_UP; + GPIO_Init(GPIOD, &GPIO_InitStructure); + + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_7 | GPIO_Pin_8 | GPIO_Pin_9 | GPIO_Pin_10 | GPIO_Pin_11 | GPIO_Pin_12 | GPIO_Pin_13 | GPIO_Pin_14 | GPIO_Pin_15; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF; + GPIO_InitStructure.GPIO_OType = GPIO_OType_PP; + GPIO_InitStructure.GPIO_Speed = GPIO_Speed_100MHz; + GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_UP; + GPIO_Init(GPIOE, &GPIO_InitStructure); + + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_12;//PF12, FSMC_A6 + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF; + GPIO_InitStructure.GPIO_OType = GPIO_OType_PP; + GPIO_InitStructure.GPIO_Speed = GPIO_Speed_100MHz; + GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_UP; + GPIO_Init(GPIOF, &GPIO_InitStructure); + + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_12;//PG12, FSMC_NE4 + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF; + GPIO_InitStructure.GPIO_OType = GPIO_OType_PP; + GPIO_InitStructure.GPIO_Speed = GPIO_Speed_100MHz; + GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_UP; + GPIO_Init(GPIOG, &GPIO_InitStructure); + + GPIO_PinAFConfig(GPIOD, GPIO_PinSource0, GPIO_AF_FSMC);//PD0,AF12 + GPIO_PinAFConfig(GPIOD, GPIO_PinSource1, GPIO_AF_FSMC);//PD1,AF12 + GPIO_PinAFConfig(GPIOD, GPIO_PinSource4, GPIO_AF_FSMC);//PD4,AF12 + GPIO_PinAFConfig(GPIOD, GPIO_PinSource5, GPIO_AF_FSMC);//PD5,AF12 + GPIO_PinAFConfig(GPIOD, GPIO_PinSource8, GPIO_AF_FSMC);//PD8,AF12 + GPIO_PinAFConfig(GPIOD, GPIO_PinSource9, GPIO_AF_FSMC);//PD9,AF12 + GPIO_PinAFConfig(GPIOD, GPIO_PinSource10, GPIO_AF_FSMC);//PD10,AF12 + GPIO_PinAFConfig(GPIOD, GPIO_PinSource14, GPIO_AF_FSMC);//PD14,AF12 + GPIO_PinAFConfig(GPIOD, GPIO_PinSource15, GPIO_AF_FSMC);//PD15,AF12 + + GPIO_PinAFConfig(GPIOE, GPIO_PinSource7, GPIO_AF_FSMC);//PE7,AF12 + GPIO_PinAFConfig(GPIOE, GPIO_PinSource8, GPIO_AF_FSMC);//PE8,AF12 + GPIO_PinAFConfig(GPIOE, GPIO_PinSource9, GPIO_AF_FSMC);//PE9,AF12 + GPIO_PinAFConfig(GPIOE, GPIO_PinSource10, GPIO_AF_FSMC);//PE10,AF12 + GPIO_PinAFConfig(GPIOE, GPIO_PinSource11, GPIO_AF_FSMC);//PE11,AF12 + GPIO_PinAFConfig(GPIOE, GPIO_PinSource12, GPIO_AF_FSMC);//PE12,AF12 + GPIO_PinAFConfig(GPIOE, GPIO_PinSource13, GPIO_AF_FSMC);//PE13,AF12 + GPIO_PinAFConfig(GPIOE, GPIO_PinSource14, GPIO_AF_FSMC);//PE14,AF12 + GPIO_PinAFConfig(GPIOE, GPIO_PinSource15, GPIO_AF_FSMC);//PE15,AF12 + + GPIO_PinAFConfig(GPIOF, GPIO_PinSource12, GPIO_AF_FSMC);//PF12,AF12 + GPIO_PinAFConfig(GPIOG, GPIO_PinSource12, GPIO_AF_FSMC);//PG12,AF12 + + readWriteTiming.FSMC_AddressSetupTime = 0xF;//16 HCLK 1/168M=6ns*16=96ns + readWriteTiming.FSMC_AddressHoldTime = 0x00; + readWriteTiming.FSMC_DataSetupTime = 60;//60 HCLK 6*60=360ns + readWriteTiming.FSMC_BusTurnAroundDuration = 0x00; + readWriteTiming.FSMC_CLKDivision = 0x00; + readWriteTiming.FSMC_DataLatency = 0x00; + readWriteTiming.FSMC_AccessMode = FSMC_AccessMode_A;//mode A + + writeTiming.FSMC_AddressSetupTime = 9;//9 HCLK =54ns + writeTiming.FSMC_AddressHoldTime = 0x00; + writeTiming.FSMC_DataSetupTime = 8;//9 HCLK=54ns + writeTiming.FSMC_BusTurnAroundDuration = 0x00; + writeTiming.FSMC_CLKDivision = 0x00; + writeTiming.FSMC_DataLatency = 0x00; + writeTiming.FSMC_AccessMode = FSMC_AccessMode_A;//mode A + + FSMC_NORSRAMInitStructure.FSMC_Bank = FSMC_Bank1_NORSRAM4;//FSMC_NE4, register BTCR[6],[7]。 + FSMC_NORSRAMInitStructure.FSMC_DataAddressMux = FSMC_DataAddressMux_Disable; + FSMC_NORSRAMInitStructure.FSMC_MemoryType =FSMC_MemoryType_SRAM; + FSMC_NORSRAMInitStructure.FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_16b;//data bit width 16bit + FSMC_NORSRAMInitStructure.FSMC_BurstAccessMode =FSMC_BurstAccessMode_Disable; + FSMC_NORSRAMInitStructure.FSMC_WaitSignalPolarity = FSMC_WaitSignalPolarity_Low; + FSMC_NORSRAMInitStructure.FSMC_AsynchronousWait=FSMC_AsynchronousWait_Disable; + FSMC_NORSRAMInitStructure.FSMC_WrapMode = FSMC_WrapMode_Disable; + FSMC_NORSRAMInitStructure.FSMC_WaitSignalActive = FSMC_WaitSignalActive_BeforeWaitState; + FSMC_NORSRAMInitStructure.FSMC_WriteOperation = FSMC_WriteOperation_Enable; + FSMC_NORSRAMInitStructure.FSMC_WaitSignal = FSMC_WaitSignal_Disable; + FSMC_NORSRAMInitStructure.FSMC_ExtendedMode = FSMC_ExtendedMode_Enable; + FSMC_NORSRAMInitStructure.FSMC_WriteBurst = FSMC_WriteBurst_Disable; + FSMC_NORSRAMInitStructure.FSMC_ReadWriteTimingStruct = &readWriteTiming; + FSMC_NORSRAMInitStructure.FSMC_WriteTimingStruct = &writeTiming; + + FSMC_NORSRAMInit(&FSMC_NORSRAMInitStructure);//init FSMC init + + FSMC_NORSRAMCmd(FSMC_Bank1_NORSRAM4, ENABLE);//enable BANK1 +} + +static void LcdWriteCmd(LCD_TypeDef *LCD, uint16_t cmd) +{ + LCD->LCD_REG_CMD = cmd; +} + +static void LcdWriteData(LCD_TypeDef *LCD, uint16_t data) +{ + LCD->LCD_RAM_DATA = data; +} + +static void LcdWriteReg(LCD_TypeDef *LCD, uint16_t cmd, uint16_t data) +{ + LCD->LCD_REG_CMD = cmd; + LCD->LCD_RAM_DATA = data; +} + +static uint16_t LcdReadData(LCD_TypeDef *LCD) +{ + uint16_t data; + data = LCD->LCD_RAM_DATA; + return data; +} + +static uint16_t LcdReadReg(LCD_TypeDef *LCD, uint16_t cmd) +{ + LcdWriteCmd(LCD, cmd); + Stm32LcdUdelay(1000); + return LcdReadData(LCD); +} + +static void LcdDisplayOn(LCD_TypeDef *LCD) +{ + LcdWriteCmd(LCD, DISPALY_ON); +} + +static void LcdDisplayOff(LCD_TypeDef *LCD) +{ + LcdWriteCmd(LCD, DISPALY_OFF); +} + +static void LcdWriteRamCmd(struct Stm32HwLcd *hw_lcd) +{ + LcdWriteCmd(hw_lcd->LCD, hw_lcd->lcd_param.write_ram_cmd); +} + +static void LcdWriteRamColor(struct Stm32HwLcd *hw_lcd, uint16_t color) +{ + LcdWriteData(hw_lcd->LCD, color); +} + +static void LcdSetCursor(struct Stm32HwLcd *hw_lcd, uint16_t x_pos, uint16_t y_pos) +{ + LcdWriteCmd(hw_lcd->LCD, hw_lcd->lcd_param.set_x_cmd); + LcdWriteData(hw_lcd->LCD, x_pos >> 8); + LcdWriteData(hw_lcd->LCD, x_pos & 0xFF); + LcdWriteCmd(hw_lcd->LCD, hw_lcd->lcd_param.set_y_cmd); + LcdWriteData(hw_lcd->LCD, y_pos >> 8); + LcdWriteData(hw_lcd->LCD, y_pos & 0xFF); +} + +static void LcdDrawPoint(struct Stm32HwLcd *hw_lcd, uint16_t x, uint16_t y, uint16_t color) +{ + LcdSetCursor(hw_lcd, x, y); + LcdWriteRamCmd(hw_lcd); + LcdWriteRamColor(hw_lcd, color); +} + +//(start_x,start_y),(end_x,end_y), area: (end_x-start_x+1)*(end_y-start_y+1) +static void LcdDrawArea(struct Stm32HwLcd *hw_lcd, uint16_t start_x, uint16_t start_y, uint16_t end_x, uint16_t end_y, uint16_t *color) +{ + uint16_t height, width; + uint16_t i, j; + width = end_x - start_x + 1; + height = end_y - start_y + 1; + + for (i = 0; i < height; i++) { + LcdSetCursor(hw_lcd, start_x, start_y + i); + LcdWriteRamCmd(hw_lcd); + + for (j = 0; j < width; j++) { + LcdWriteRamColor(hw_lcd, color[i * width + j]); + } + } +} + +//mode 0 : draw char, default configure ; 1 : draw char over background +static void LcdDrawChar(struct Stm32HwLcd *hw_lcd, uint16_t x, uint16_t y, uint8_t char_data, uint8_t size, uint8_t mode, uint16_t color,uint16_t back_color) +{ + uint8_t temp, t1, t; + uint16_t y0 = y; + uint8_t csize = (size / 8 + ((size % 8) ? 1 : 0)) * (size / 2); + char_data = char_data - ' '; + for(t = 0;t < csize;t ++) { + if(12 == size) + temp = asc2_1206[char_data][t]; + else if(16 == size) + temp = asc2_1608[char_data][t]; + else if(24 == size) + temp = asc2_2412[char_data][t]; + else + return; + + for(t1 = 0;t1 < 8;t1 ++) { + if(temp & 0x80) + LcdDrawPoint(hw_lcd, x, y, color); + else if(mode == 0) + LcdDrawPoint(hw_lcd, x, y, back_color); + + temp <<= 1; + y++; + + if(y >= hw_lcd->lcd_param.height) + return;//over height + + if((y - y0) == size) { + y = y0; + x++; + if(x >= hw_lcd->lcd_param.width) + return;//over width + break; + } + } + } +} + +static void LcdDrawString(struct Stm32HwLcd *hw_lcd, uint16_t x, uint16_t y, uint16_t width, uint16_t height, uint8_t size, uint8_t *p, uint16_t color, uint16_t back_color) +{ + uint8_t x0 = x; + width += x; + height += y; + + while ((*p <= '~') && (*p >= ' ')) { + if (x >= width) { + x = x0; + y += size; + } + + if (y >= height) + break; + + LcdDrawChar(hw_lcd, x, y, *p, size, 0, color, back_color); + x += size / 2; + p++; + } +} + +static void LcdClear(struct Stm32HwLcd *hw_lcd, uint16_t color) +{ + uint32_t dot_index = 0; + uint32_t totalpoint = hw_lcd->lcd_param.width * hw_lcd->lcd_param.height; + + LcdSetCursor(hw_lcd, 0x00, 0x00); + LcdWriteRamCmd(hw_lcd); + + for (dot_index = 0; dot_index < totalpoint; dot_index ++) { + LcdWriteRamColor(hw_lcd, color); + } +} + +static void LcdScanDirection(struct Stm32HwLcd *hw_lcd, uint8_t scan_direction) +{ + uint16_t cmd = 0; + uint16_t temp; + + switch (scan_direction) { + case L2R_U2D: + cmd |= (0 << 7) | (0 << 6) | (0 << 5); + break; + case L2R_D2U: + cmd |= (1 << 7) | (0 << 6) | (0 << 5); + break; + case R2L_U2D: + cmd |= (0 << 7) | (1 << 6) | (0 << 5); + break; + case R2L_D2U: + cmd |= (1 << 7) | (1 << 6) | (0 << 5); + break; + case U2D_L2R: + cmd |= (0 << 7) | (0 << 6) | (1 << 5); + break; + case U2D_R2L: + cmd |= (0 << 7) | (1 << 6) | (1 << 5); + break; + case D2U_L2R: + cmd |= (1 << 7) | (0 << 6) | (1 << 5); + break; + case D2U_R2L: + cmd |= (1 << 7) | (1 << 6) | (1 << 5); + break; + } + + cmd |= 0X08;//set BGR bit + + LcdWriteReg(hw_lcd->LCD, MEMORY_ACCESS_CTL, cmd); + + if (cmd & INVERSION_DISPALY_OFF) {//reverse x、y + if (hw_lcd->lcd_param.width < hw_lcd->lcd_param.height) { + temp = hw_lcd->lcd_param.width; + hw_lcd->lcd_param.width = hw_lcd->lcd_param.height; + hw_lcd->lcd_param.height = temp; + } + } else { + if (hw_lcd->lcd_param.width > hw_lcd->lcd_param.height) { + temp = hw_lcd->lcd_param.width; + hw_lcd->lcd_param.width = hw_lcd->lcd_param.height; + hw_lcd->lcd_param.height = temp; + } + } + + LcdWriteCmd(hw_lcd->LCD, hw_lcd->lcd_param.set_x_cmd); + LcdWriteData(hw_lcd->LCD, 0); + LcdWriteData(hw_lcd->LCD, 0); + LcdWriteData(hw_lcd->LCD, (hw_lcd->lcd_param.width - 1) >> 8); + LcdWriteData(hw_lcd->LCD, (hw_lcd->lcd_param.width - 1) & 0xFF); + LcdWriteCmd(hw_lcd->LCD, hw_lcd->lcd_param.set_y_cmd); + LcdWriteData(hw_lcd->LCD, 0); + LcdWriteData(hw_lcd->LCD, 0); + LcdWriteData(hw_lcd->LCD, (hw_lcd->lcd_param.height - 1) >> 8); + LcdWriteData(hw_lcd->LCD, (hw_lcd->lcd_param.height - 1) & 0xFF); +} + +static void LcdDisplayDirection(struct Stm32HwLcd *hw_lcd) +{ + hw_lcd->lcd_param.write_ram_cmd = MEMORY_WRITE; + hw_lcd->lcd_param.set_x_cmd = HORIZONTAL_ADDRESS_SET; + hw_lcd->lcd_param.set_y_cmd = VERTICAL_ADDRESS_SET; + + LcdScanDirection(hw_lcd, DFT_SCAN_DIR); +} + +static void HwLcdInit(struct Stm32HwLcd *hw_lcd) +{ + LcdWriteCmd(hw_lcd->LCD, READ_ID4); + hw_lcd->lcd_param.lcd_id = LcdReadData(hw_lcd->LCD);//dummy read + hw_lcd->lcd_param.lcd_id = LcdReadData(hw_lcd->LCD);//0x00 + hw_lcd->lcd_param.lcd_id = LcdReadData(hw_lcd->LCD);//93 + hw_lcd->lcd_param.lcd_id <<= 8; + hw_lcd->lcd_param.lcd_id |= LcdReadData(hw_lcd->LCD);//41 + + KPrintf("HwLcdInit lcd id 0x%x\n", hw_lcd->lcd_param.lcd_id); + + if (ILI9341 == hw_lcd->lcd_param.lcd_id) { + FSMC_Bank1E->BWTR[6] &= ~(0xF << 0); + FSMC_Bank1E->BWTR[6] &= ~(0xF << 8); + FSMC_Bank1E->BWTR[6] |= 3 << 0; + FSMC_Bank1E->BWTR[6] |= 2 << 8; + + LcdWriteCmd(hw_lcd->LCD, 0xCF); + LcdWriteData(hw_lcd->LCD, 0x00); + LcdWriteData(hw_lcd->LCD, 0xC1); + LcdWriteData(hw_lcd->LCD, 0x30); + LcdWriteCmd(hw_lcd->LCD, 0xED); + LcdWriteData(hw_lcd->LCD, 0x64); + LcdWriteData(hw_lcd->LCD, 0x03); + LcdWriteData(hw_lcd->LCD, 0X12); + LcdWriteData(hw_lcd->LCD, 0X81); + LcdWriteCmd(hw_lcd->LCD, 0xE8); + LcdWriteData(hw_lcd->LCD, 0x85); + LcdWriteData(hw_lcd->LCD, 0x10); + LcdWriteData(hw_lcd->LCD, 0x7A); + LcdWriteCmd(hw_lcd->LCD, 0xCB); + LcdWriteData(hw_lcd->LCD, 0x39); + LcdWriteData(hw_lcd->LCD, 0x2C); + LcdWriteData(hw_lcd->LCD, 0x00); + LcdWriteData(hw_lcd->LCD, 0x34); + LcdWriteData(hw_lcd->LCD, 0x02); + LcdWriteCmd(hw_lcd->LCD, 0xF7); + LcdWriteData(hw_lcd->LCD, 0x20); + LcdWriteCmd(hw_lcd->LCD, 0xEA); + LcdWriteData(hw_lcd->LCD, 0x00); + LcdWriteData(hw_lcd->LCD, 0x00); + LcdWriteCmd(hw_lcd->LCD, POWER_CTL1);//Power control + LcdWriteData(hw_lcd->LCD, 0x1B);//VRH[5:0] + LcdWriteCmd(hw_lcd->LCD, POWER_CTL2);//Power control + LcdWriteData(hw_lcd->LCD, 0x01);//SAP[2:0];BT[3:0] + LcdWriteCmd(hw_lcd->LCD, VCOM_CTL1);//VCM control + LcdWriteData(hw_lcd->LCD, 0x30); + LcdWriteData(hw_lcd->LCD, 0x30); + LcdWriteCmd(hw_lcd->LCD, VCOM_CTL2);//VCM control2 + LcdWriteData(hw_lcd->LCD, 0xB7); + LcdWriteCmd(hw_lcd->LCD, MEMORY_ACCESS_CTL);// Memory Access Control + LcdWriteData(hw_lcd->LCD, 0x48); + LcdWriteCmd(hw_lcd->LCD, PIXEL_FORMAT_SET); + LcdWriteData(hw_lcd->LCD, 0x55); + LcdWriteCmd(hw_lcd->LCD, NORMAL_FRAME_CTL); + LcdWriteData(hw_lcd->LCD, 0x00); + LcdWriteData(hw_lcd->LCD, 0x1A); + LcdWriteCmd(hw_lcd->LCD, DISPALY_FUNCTION_CTL);// Display Function Control + LcdWriteData(hw_lcd->LCD, 0x0A); + LcdWriteData(hw_lcd->LCD, 0xA2); + LcdWriteCmd(hw_lcd->LCD, 0xF2);// 3Gamma Function Disable + LcdWriteData(hw_lcd->LCD, 0x00); + LcdWriteCmd(hw_lcd->LCD, GAMMA_SET);//Gamma curve selected + LcdWriteData(hw_lcd->LCD, 0x01); + LcdWriteCmd(hw_lcd->LCD, POSITIVE_GAMMA_CORRECT);//Set Gamma + LcdWriteData(hw_lcd->LCD, 0x0F); + LcdWriteData(hw_lcd->LCD, 0x2A); + LcdWriteData(hw_lcd->LCD, 0x28); + LcdWriteData(hw_lcd->LCD, 0x08); + LcdWriteData(hw_lcd->LCD, 0x0E); + LcdWriteData(hw_lcd->LCD, 0x08); + LcdWriteData(hw_lcd->LCD, 0x54); + LcdWriteData(hw_lcd->LCD, 0xA9); + LcdWriteData(hw_lcd->LCD, 0x43); + LcdWriteData(hw_lcd->LCD, 0x0A); + LcdWriteData(hw_lcd->LCD, 0x0F); + LcdWriteData(hw_lcd->LCD, 0x00); + LcdWriteData(hw_lcd->LCD, 0x00); + LcdWriteData(hw_lcd->LCD, 0x00); + LcdWriteData(hw_lcd->LCD, 0x00); + LcdWriteCmd(hw_lcd->LCD, NEGATIVE_GAMMA_CORRECT);//Set Gamma + LcdWriteData(hw_lcd->LCD, 0x00); + LcdWriteData(hw_lcd->LCD, 0x15); + LcdWriteData(hw_lcd->LCD, 0x17); + LcdWriteData(hw_lcd->LCD, 0x07); + LcdWriteData(hw_lcd->LCD, 0x11); + LcdWriteData(hw_lcd->LCD, 0x06); + LcdWriteData(hw_lcd->LCD, 0x2B); + LcdWriteData(hw_lcd->LCD, 0x56); + LcdWriteData(hw_lcd->LCD, 0x3C); + LcdWriteData(hw_lcd->LCD, 0x05); + LcdWriteData(hw_lcd->LCD, 0x10); + LcdWriteData(hw_lcd->LCD, 0x0F); + LcdWriteData(hw_lcd->LCD, 0x3F); + LcdWriteData(hw_lcd->LCD, 0x3F); + LcdWriteData(hw_lcd->LCD, 0x0F); + LcdWriteCmd(hw_lcd->LCD, VERTICAL_ADDRESS_SET); + LcdWriteData(hw_lcd->LCD, 0x00); + LcdWriteData(hw_lcd->LCD, 0x00); + LcdWriteData(hw_lcd->LCD, 0x01); + LcdWriteData(hw_lcd->LCD, 0x3f); + LcdWriteCmd(hw_lcd->LCD, HORIZONTAL_ADDRESS_SET); + LcdWriteData(hw_lcd->LCD, 0x00); + LcdWriteData(hw_lcd->LCD, 0x00); + LcdWriteData(hw_lcd->LCD, 0x00); + LcdWriteData(hw_lcd->LCD, 0xef); + LcdWriteCmd(hw_lcd->LCD, SLEEP_OFF);//Exit Sleep + Stm32LcdUdelay(120000); + LcdWriteCmd(hw_lcd->LCD, DISPALY_ON);//display on + + LcdDisplayDirection(hw_lcd); + PDout(3) = 1; + LcdClear(hw_lcd, WHITE); + } +} + +static uint32 LcdWrite(void *dev, struct BusBlockWriteParam *write_param) +{ + x_err_t ret = EOK; + + struct LcdHardwareDevice *lcd_dev = (struct LcdHardwareDevice *)dev; + struct Stm32HwLcd *hw_lcd = (struct Stm32HwLcd *)lcd_dev->haldev.private_data; + + if (write_param->buffer) { + LcdWriteParam *show = (LcdWriteParam *)write_param->buffer; + + //output string + if(0 == show->type) { + LcdDrawString(hw_lcd, show->string_info.x_pos, show->string_info.y_pos, show->string_info.width, show->string_info.height, + show->string_info.font_size, show->string_info.addr, show->string_info.font_color, show->string_info.back_color); + } + //output dot + else if (1 == show->type) { + LcdDrawArea(hw_lcd, show->pixel_info.x_startpos, show->pixel_info.y_startpos, show->pixel_info.x_endpos, show->pixel_info.y_endpos, + (uint16_t *)show->pixel_info.pixel_color); + } else { + KPrintf("LcdWrite donnot support show type(0 string; 1 dot) %u\n", show->type); + ret = ERROR; + } + } + + return ret; +} + +static uint32 LcdControl(void* drv, struct BusConfigureInfo *configure_info) +{ + x_err_t ret = EOK; + + return ret; +} + +static const struct LcdDevDone dev_done = +{ + NONE, + NONE, + LcdWrite, + NONE, +}; + +static int BoardLcdBusInit(struct LcdBus * lcd_bus, struct LcdDriver * lcd_driver,const char *bus_name, const char *drv_name) +{ + x_err_t ret = EOK; + + /*Init the lcd bus */ + ret = LcdBusInit( lcd_bus, bus_name); + if (EOK != ret) { + KPrintf("Board_lcd_init LcdBusInit error %d\n", ret); + return -ERROR; + } + + /*Init the lcd driver*/ + ret = LcdDriverInit( lcd_driver, drv_name); + if (EOK != ret) { + KPrintf("Board_LCD_init LcdDriverInit error %d\n", ret); + return -ERROR; + } + + /*Attach the lcd driver to the lcd bus*/ + ret = LcdDriverAttachToBus(drv_name, bus_name); + if (EOK != ret) { + KPrintf("Board_LCD_init LcdDriverAttachToBus error %d\n", ret); + return -ERROR; + } + + return ret; +} + +/*Attach the lcd device to the lcd bus*/ +static int BoardLcdDevBend(struct LcdHardwareDevice *lcd_device, void *param, const char *bus_name, const char *dev_name) +{ + x_err_t ret = EOK; + + ret = LcdDeviceRegister(lcd_device, param, dev_name); + if (EOK != ret) { + KPrintf("Board_LCD_init LcdDeviceInit device %s error %d\n", dev_name, ret); + return -ERROR; + } + + ret = LcdDeviceAttachToBus(dev_name, bus_name); + if (EOK != ret) { + KPrintf("Board_LCD_init LcdDeviceAttachToBus device %s error %d\n", dev_name, ret); + return -ERROR; + } + + return ret; +} + +int Stm32HwLcdInit(void) +{ + x_err_t ret = EOK; + +#ifdef BSP_USING_LCD + static struct LcdBus lcd_bus; + static struct LcdDriver lcd_drv; + static struct LcdHardwareDevice lcd_dev; + static struct Stm32HwLcd hw_lcd; + + memset(&lcd_bus, 0, sizeof(struct LcdBus)); + memset(&lcd_drv, 0, sizeof(struct LcdDriver)); + memset(&lcd_dev, 0, sizeof(struct LcdHardwareDevice)); + memset(&hw_lcd, 0, sizeof(struct Stm32HwLcd)); + + lcd_drv.configure = LcdControl; + + ret = BoardLcdBusInit(&lcd_bus, &lcd_drv, LCD_BUS_NAME, LCD_DRV_NAME); + if (EOK != ret) { + KPrintf("HwLcdInit BoardLcdBusInit error ret %u\n", ret); + return ERROR; + } + + lcd_dev.dev_done = &dev_done; + hw_lcd.LCD = AIIT_BOARD_LCD; + + /*depends on the LCD hardware*/ + hw_lcd.lcd_param.lcd_direction = LCD_HORIZONTAL_SCEEN;//Horizontal screen + if (LCD_HORIZONTAL_SCEEN == hw_lcd.lcd_param.lcd_direction) { + hw_lcd.lcd_param.width = 320; + hw_lcd.lcd_param.height = 240; + } else if (LCD_VERTICAL_SCEEN == hw_lcd.lcd_param.lcd_direction) { + hw_lcd.lcd_param.width = 240; + hw_lcd.lcd_param.height = 320; + } else { + hw_lcd.lcd_param.width = 320; + hw_lcd.lcd_param.height = 240; + } + + ret = BoardLcdDevBend(&lcd_dev, (void *)&hw_lcd, LCD_BUS_NAME, LCD_DEVICE_NAME); //init lcd device + if (EOK != ret) { + KPrintf("HwLcdInit BoardLcdDevBend error ret %u\n", ret); + return ERROR; + } + + Stm32LcdUdelay(5000000); + + HwFsmcInit(); + + Stm32LcdUdelay(20000); + + HwLcdInit(&hw_lcd); +#endif + + return ret; +} diff --git a/Ubiquitous/XiZi/board/aiit-arm32-board/third_party_driver/rtc/Kconfig b/Ubiquitous/XiZi/board/aiit-arm32-board/third_party_driver/rtc/Kconfig new file mode 100644 index 0000000..e853dd4 --- /dev/null +++ b/Ubiquitous/XiZi/board/aiit-arm32-board/third_party_driver/rtc/Kconfig @@ -0,0 +1,11 @@ +if BSP_USING_RTC + config RTC_BUS_NAME + string "rtc bus name" + default "rtc" + config RTC_DRV_NAME + string "rtc bus driver name" + default "rtc_drv" + config RTC_DEVICE_NAME + string "rtc bus device name" + default "rtc_dev" +endif diff --git a/Ubiquitous/XiZi/board/aiit-arm32-board/third_party_driver/rtc/Makefile b/Ubiquitous/XiZi/board/aiit-arm32-board/third_party_driver/rtc/Makefile new file mode 100644 index 0000000..15d4676 --- /dev/null +++ b/Ubiquitous/XiZi/board/aiit-arm32-board/third_party_driver/rtc/Makefile @@ -0,0 +1,3 @@ +SRC_FILES := hardware_rtc.c connect_rtc.c + +include $(KERNEL_ROOT)/compiler.mk diff --git a/Ubiquitous/XiZi/board/aiit-arm32-board/third_party_driver/rtc/connect_rtc.c b/Ubiquitous/XiZi/board/aiit-arm32-board/third_party_driver/rtc/connect_rtc.c new file mode 100644 index 0000000..30475e6 --- /dev/null +++ b/Ubiquitous/XiZi/board/aiit-arm32-board/third_party_driver/rtc/connect_rtc.c @@ -0,0 +1,269 @@ +/* +* Copyright (c) 2020 AIIT XUOS Lab +* XiUOS is licensed under Mulan PSL v2. +* You can use this software according to the terms and conditions of the Mulan PSL v2. +* You may obtain a copy of Mulan PSL v2 at: +* http://license.coscl.org.cn/MulanPSL2 +* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, +* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, +* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. +* See the Mulan PSL v2 for more details. +*/ + +/** +* @file connect_rtc.c +* @brief support aiit-arm32-board rtc function and register to bus framework +* @version 1.0 +* @author AIIT XUOS Lab +* @date 2021-04-25 +*/ + +#include +#include +#include +#include +#include +#include + +#define RTC_BACKUP_REGISTER 0x32F2 + +static int GetWeekDay(int year, int month, int day) +{ + if (month==1||month==2) { + year -=1; + month +=12; + } + return (day+1+2*month+3*(month+1)/5+year+(year/4)-year/100+year/400)%7+1; +} + +static uint32 RtcConfigure(void *drv, struct BusConfigureInfo *configure_info) +{ + NULL_PARAM_CHECK(drv); + + struct RtcDriver *rtc_drv = (struct RtcDriver *)drv; + struct RtcDrvConfigureParam *drv_param = (struct RtcDrvConfigureParam *)configure_info->private_data; + + int cmd = drv_param->rtc_operation_cmd; + time_t *time = drv_param->time; + + switch (cmd) + { + case OPER_RTC_GET_TIME: + { + struct tm ct; + RTC_TimeTypeDef t; + RTC_DateTypeDef d; + + memset(&ct,0,sizeof(struct tm)); + RTC_GetTime(RTC_Format_BIN,&t); + RTC_GetDate(RTC_Format_BIN,&d); + + ct.tm_year = d.RTC_Year + 100; + ct.tm_mon = d.RTC_Month - 1; + ct.tm_mday = d.RTC_Date; + ct.tm_wday = d.RTC_WeekDay; + + ct.tm_hour = t.RTC_Hours; + ct.tm_min = t.RTC_Minutes; + ct.tm_sec = t.RTC_Seconds; + + *time = mktime(&ct); + } + break; + + case OPER_RTC_SET_TIME: + { + struct tm *ct; + struct tm tm_new; + x_base lock; + RTC_TimeTypeDef rtc_time_structure; + RTC_InitTypeDef rtc_init_structure; + RTC_DateTypeDef rtc_date_structure; + + lock = CriticalAreaLock(); + ct = localtime(time); + memcpy(&tm_new, ct, sizeof(struct tm)); + CriticalAreaUnLock(lock); + RCC_APB1PeriphClockCmd(RCC_APB1Periph_PWR, ENABLE); + PWR_BackupAccessCmd(ENABLE); + rtc_init_structure.RTC_AsynchPrediv = 0x7F; + rtc_init_structure.RTC_SynchPrediv = 0xFF; + rtc_init_structure.RTC_HourFormat = RTC_HourFormat_24; + RTC_Init(&rtc_init_structure); + rtc_date_structure.RTC_Year = tm_new.tm_year - 100; + rtc_date_structure.RTC_Month = tm_new.tm_mon + 1; + rtc_date_structure.RTC_Date = tm_new.tm_mday; + rtc_date_structure.RTC_WeekDay = GetWeekDay(tm_new.tm_year+1900,tm_new.tm_mon+1,tm_new.tm_mday); + RTC_SetDate(RTC_Format_BIN, &rtc_date_structure); + if (tm_new.tm_hour > 11) { + rtc_time_structure.RTC_H12 = RTC_H12_PM; + } + else{ + rtc_time_structure.RTC_H12 = RTC_H12_AM; + } + rtc_time_structure.RTC_Hours = tm_new.tm_hour; + rtc_time_structure.RTC_Minutes = tm_new.tm_min; + rtc_time_structure.RTC_Seconds = tm_new.tm_sec; + + RTC_SetTime(RTC_Format_BIN, &rtc_time_structure); + + RTC_WriteBackupRegister(RTC_BKP_DR0, 0x32F2); + } + break; + } + + return EOK; +} + +int RtcConfiguration(void) +{ + RCC_APB1PeriphClockCmd(RCC_APB1Periph_PWR, ENABLE); + + PWR_BackupAccessCmd(ENABLE); + +#if defined (RTC_CLOCK_SOURCE_LSI) + RCC_LSICmd(ENABLE); + + while(RCC_GetFlagStatus(RCC_FLAG_LSIRDY) == RESET); + + RCC_RTCCLKConfig(RCC_RTCCLKSource_LSI); + + /* ck_spre(1Hz) = RTCCLK(LSI) /(uwAsynchPrediv + 1)*(uwSynchPrediv + 1)*/ + //uwSynchPrediv = 0xFF; + //uwAsynchPrediv = 0x7F; + +#elif defined (RTC_CLOCK_SOURCE_LSE) + RCC_LSEConfig(RCC_LSE_ON); + + while(RCC_GetFlagStatus(RCC_FLAG_LSERDY) == RESET); + + RCC_RTCCLKConfig(RCC_RTCCLKSource_LSE); + +#else +#error Please select the RTC Clock source inside the main.c file +#endif + + RCC_RTCCLKCmd(ENABLE); + + RTC_WaitForSynchro(); + + return 0; +} + +/*manage the rtc device operations*/ +static const struct RtcDevDone dev_done = +{ + .open = NONE, + .close = NONE, + .write = NONE, + .read = NONE, +}; + +static int BoardRtcBusInit(struct RtcBus *rtc_bus, struct RtcDriver *rtc_driver) +{ + x_err_t ret = EOK; + + /*Init the rtc bus */ + ret = RtcBusInit(rtc_bus, RTC_BUS_NAME); + if (EOK != ret) { + KPrintf("hw_rtc_init RtcBusInit error %d\n", ret); + return ERROR; + } + + /*Init the rtc driver*/ + ret = RtcDriverInit(rtc_driver, RTC_DRV_NAME); + if (EOK != ret) { + KPrintf("hw_rtc_init RtcDriverInit error %d\n", ret); + return ERROR; + } + + /*Attach the rtc driver to the rtc bus*/ + ret = RtcDriverAttachToBus(RTC_DRV_NAME, RTC_BUS_NAME); + if (EOK != ret) { + KPrintf("hw_rtc_init RtcDriverAttachToBus error %d\n", ret); + return ERROR; + } + + return ret; +} + +/*Attach the rtc device to the rtc bus*/ +static int BoardRtcDevBend(void) +{ + x_err_t ret = EOK; + + static struct RtcHardwareDevice rtc_device; + memset(&rtc_device, 0, sizeof(struct RtcHardwareDevice)); + + rtc_device.dev_done = &(dev_done); + + ret = RtcDeviceRegister(&rtc_device, NONE, RTC_DEVICE_NAME); + if (EOK != ret) { + KPrintf("hw_rtc_init RtcDeviceInit device %s error %d\n", RTC_DEVICE_NAME, ret); + return ERROR; + } + + ret = RtcDeviceAttachToBus(RTC_DEVICE_NAME, RTC_BUS_NAME); + if (EOK != ret) { + KPrintf("hw_rtc_init RtcDeviceAttachToBus device %s error %d\n", RTC_DEVICE_NAME, ret); + return ERROR; + } + + return ret; +} + +int Stm32HwRtcInit(void) +{ + x_err_t ret = EOK; + + static struct RtcBus rtc_bus; + memset(&rtc_bus, 0, sizeof(struct RtcBus)); + + static struct RtcDriver rtc_driver; + memset(&rtc_driver, 0, sizeof(struct RtcDriver)); + + rtc_driver.configure = &(RtcConfigure); + + ret = BoardRtcBusInit(&rtc_bus, &rtc_driver); + if (EOK != ret) { + KPrintf("hw_rtc_init error ret %u\n", ret); + return ERROR; + } + + ret = BoardRtcDevBend(); + if (EOK != ret) { + KPrintf("hw_rtc_init error ret %u\n", ret); + return ERROR; + } + + if (RTC_BACKUP_REGISTER != RTC_ReadBackupRegister(RTC_BKP_DR0)) { + if (0 != RtcConfiguration()) { + KPrintf("hw_rtc_init RtcConfiguration error...\n"); + return ERROR; + } + } else { + RTC_WaitForSynchro(); + } + + return ret; +} + +#ifdef TOOL_SHELL +void ShowTime(void) +{ + RTC_TimeTypeDef time; + RTC_DateTypeDef date; + RTC_GetDate(RTC_Format_BIN,&date); + RTC_GetTime(RTC_Format_BIN, &time); + KPrintf("Now Time = %d %02d %02d[%02d]-%0.2d:%0.2d:%0.2d \r\n", \ + date.RTC_Year, + date.RTC_Month, + date.RTC_Date, + date.RTC_WeekDay, + time.RTC_Hours, + time.RTC_Minutes, + time.RTC_Seconds); +} +SHELL_EXPORT_CMD(SHELL_CMD_PERMISSION(0)|SHELL_CMD_TYPE(SHELL_TYPE_CMD_FUNC)|SHELL_CMD_PARAM_NUM(0), + ShowTime, ShowTime, Arm test rtc function show time); +#endif diff --git a/Ubiquitous/XiZi/board/aiit-arm32-board/third_party_driver/sdio/Kconfig b/Ubiquitous/XiZi/board/aiit-arm32-board/third_party_driver/sdio/Kconfig new file mode 100644 index 0000000..a9d1dd3 --- /dev/null +++ b/Ubiquitous/XiZi/board/aiit-arm32-board/third_party_driver/sdio/Kconfig @@ -0,0 +1,13 @@ +if BSP_USING_SDIO +config SDIO_BUS_NAME + string "sdio bus name" + default "sdio" + +config SDIO_DRIVER_NAME + string "sdio driver name" + default "sdio_drv" + +config SDIO_DEVICE_NAME + string "sdio device name" + default "sdio_dev" +endif diff --git a/Ubiquitous/XiZi/board/aiit-arm32-board/third_party_driver/sdio/Makefile b/Ubiquitous/XiZi/board/aiit-arm32-board/third_party_driver/sdio/Makefile new file mode 100644 index 0000000..1f543e0 --- /dev/null +++ b/Ubiquitous/XiZi/board/aiit-arm32-board/third_party_driver/sdio/Makefile @@ -0,0 +1,4 @@ +SRC_FILES := connect_sdio.c sdio_sd.c hardware_sdio.c + + +include $(KERNEL_ROOT)/compiler.mk diff --git a/Ubiquitous/XiZi/board/aiit-arm32-board/third_party_driver/sdio/connect_sdio.c b/Ubiquitous/XiZi/board/aiit-arm32-board/third_party_driver/sdio/connect_sdio.c new file mode 100644 index 0000000..a29e227 --- /dev/null +++ b/Ubiquitous/XiZi/board/aiit-arm32-board/third_party_driver/sdio/connect_sdio.c @@ -0,0 +1,239 @@ +/* +* Copyright (c) 2020 AIIT XUOS Lab +* XiUOS is licensed under Mulan PSL v2. +* You can use this software according to the terms and conditions of the Mulan PSL v2. +* You may obtain a copy of Mulan PSL v2 at: +* http://license.coscl.org.cn/MulanPSL2 +* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, +* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, +* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. +* See the Mulan PSL v2 for more details. +*/ + +/** +* @file connect_sdio.c +* @brief support sdio function using bus driver framework +* @version 1.0 +* @author AIIT XUOS Lab +* @date 2021-04-22 +*/ + +/************************************************* +File name: connect_sdio.c +Description: support sdio function using bus driver framework +Others: hardware/sdio/sdio.c for references +History: +1. Date: 2021-04-22 +Author: AIIT XUOS Lab +Modification: Support aiit-arm32-board sdio configure, write and read functions +*************************************************/ + +#include +#include "sdio_sd.h" + +#ifndef SDCARD_SECTOR_SIZE +#define SDCARD_SECTOR_SIZE 512 +#endif + +static uint32 SdioConfigure(void *drv, struct BusConfigureInfo *ConfigureInfo) +{ + NULL_PARAM_CHECK(drv); + NULL_PARAM_CHECK(ConfigureInfo); + + if (ConfigureInfo->configure_cmd == OPER_BLK_GETGEOME) { + NULL_PARAM_CHECK(ConfigureInfo->private_data); + struct DeviceBlockArrange *args = (struct DeviceBlockArrange *)ConfigureInfo->private_data; + SD_GetCardInfo(&SDCardInfo); + + args->size_perbank = SDCardInfo.CardBlockSize; + args->block_size = SDCardInfo.CardBlockSize; + if (SDCardInfo.CardType == SDIO_HIGH_CAPACITY_SD_CARD) + args->bank_num = (SDCardInfo.SD_csd.DeviceSize + 1) * 1024; + else + args->bank_num = SDCardInfo.CardCapacity; + } + + return EOK; +} + +static int SDLock = -1; +static uint32 SDBuffer[512/sizeof(uint32_t)]; + +static uint32 SdioOpen(void *dev) +{ + NULL_PARAM_CHECK(dev); + + if (SDLock >= 0) { + KSemaphoreDelete(SDLock); + } + SDLock = KSemaphoreCreate(1); + if (SDLock < 0) { + return ERROR; + } + + return EOK; +} + +static uint32 SdioClose(void *dev) +{ + NULL_PARAM_CHECK(dev); + + KSemaphoreDelete(SDLock); + + return EOK; +} + +static uint32 SdioRead(void *dev, struct BusBlockReadParam *read_param) +{ + uint8 ret = SD_OK; + + KSemaphoreObtain(SDLock, WAITING_FOREVER); + + if (((uint32)read_param->buffer & 0x03) != 0) { + uint64_t sector; + uint8_t* temp; + + sector = (uint64_t)read_param->pos * SDCARD_SECTOR_SIZE; + temp = (uint8_t*)read_param->buffer; + + for (uint8 i = 0; i < read_param->size; i++) { + ret = SD_ReadBlock((uint8_t *)SDBuffer, sector, 1); + if (ret != SD_OK) { + KPrintf("read failed: %d, buffer 0x%08x\n", ret, temp); + return 0; + } +#if defined (SD_DMA_MODE) + ret = SD_WaitReadOperation(); + if (ret != SD_OK) { + KPrintf("read failed: %d, buffer 0x%08x\n", ret, temp); + return 0; + } +#endif + memcpy(temp, SDBuffer, SDCARD_SECTOR_SIZE); + + sector += SDCARD_SECTOR_SIZE; + temp += SDCARD_SECTOR_SIZE; + } + } else { + ret = SD_ReadBlock((uint8_t *)read_param->buffer, (uint64_t)read_param->pos * SDCARD_SECTOR_SIZE, read_param->size); + if (ret != SD_OK) { + KPrintf("read failed: %d, buffer 0x%08x\n", ret, (uint8_t *)read_param->buffer); + return 0; + } +#if defined (SD_DMA_MODE) + ret = SD_WaitReadOperation(); + if (ret != SD_OK) { + KPrintf("read failed: %d, buffer 0x%08x\n", ret, (uint8_t *)read_param->buffer); + return 0; + } +#endif + } + + KSemaphoreAbandon(SDLock); + + return read_param->size; +} + +static uint32 SdioWrite(void *dev, struct BusBlockWriteParam *write_param) +{ + uint8 ret = SD_OK; + + KSemaphoreObtain(SDLock, WAITING_FOREVER); + + if (((uint32)write_param->buffer & 0x03) != 0) { + uint64_t sector; + uint8_t* temp; + + sector = (uint64_t)write_param->pos * SDCARD_SECTOR_SIZE; + temp = (uint8_t*)write_param->buffer; + + for (uint8 i = 0; i < write_param->size; i++) { + memcpy(SDBuffer, temp, SDCARD_SECTOR_SIZE); + + ret = SD_WriteBlock((uint8_t *)SDBuffer, sector, 1); + if (ret != SD_OK) { + KPrintf("write failed: %d, buffer 0x%08x\n", ret, temp); + return 0; + } +#if defined (SD_DMA_MODE) + ret = SD_WaitWriteOperation(); + if (ret != SD_OK) { + KPrintf("write failed: %d, buffer 0x%08x\n", ret, temp); + return 0; + } +#endif + sector += SDCARD_SECTOR_SIZE; + temp += SDCARD_SECTOR_SIZE; + } + } else { + ret = SD_WriteBlock((uint8_t *)write_param->buffer, (uint64_t)write_param->pos * SDCARD_SECTOR_SIZE, write_param->size); + if (ret != SD_OK) { + KPrintf("write failed: %d, buffer 0x%08x\n", ret, (uint8_t *)write_param->buffer); + return 0; + } +#if defined (SD_DMA_MODE) + ret = SD_WaitWriteOperation(); + if (ret != SD_OK) { + KPrintf("write failed: %d, buffer 0x%08x\n", ret, (uint8_t *)write_param->buffer); + return 0; + } +#endif + } + + KSemaphoreAbandon(SDLock); + + return write_param->size; +} + +static struct SdioDevDone dev_done = +{ + SdioOpen, + SdioClose, + SdioWrite, + SdioRead, +}; + +int HwSdioInit(void) +{ + static struct SdioBus bus; + static struct SdioDriver drv; + static struct SdioHardwareDevice dev; + + x_err_t ret = EOK; + ret = SD_Init(); + if (ret != SD_OK) { + KPrintf("SD init failed!"); + return ERROR; + } + + ret = SdioBusInit(&bus, SDIO_BUS_NAME); + if (ret != EOK) { + KPrintf("Sdio bus init error %d\n", ret); + return ERROR; + } + + ret = SdioDriverInit(&drv, SDIO_DRIVER_NAME); + if (ret != EOK) { + KPrintf("Sdio driver init error %d\n", ret); + return ERROR; + } + ret = SdioDriverAttachToBus(SDIO_DRIVER_NAME, SDIO_BUS_NAME); + if (ret != EOK) { + KPrintf("Sdio driver attach error %d\n", ret); + return ERROR; + } + + dev.dev_done = &dev_done; + ret = SdioDeviceRegister(&dev, SDIO_DEVICE_NAME); + if (ret != EOK) { + KPrintf("Sdio device register error %d\n", ret); + return ERROR; + } + ret = SdioDeviceAttachToBus(SDIO_DEVICE_NAME, SDIO_BUS_NAME); + if (ret != EOK) { + KPrintf("Sdio device register error %d\n", ret); + return ERROR; + } + + return ret; +} diff --git a/Ubiquitous/XiZi/board/aiit-arm32-board/third_party_driver/spi/Kconfig b/Ubiquitous/XiZi/board/aiit-arm32-board/third_party_driver/spi/Kconfig new file mode 100644 index 0000000..4d35f14 --- /dev/null +++ b/Ubiquitous/XiZi/board/aiit-arm32-board/third_party_driver/spi/Kconfig @@ -0,0 +1,77 @@ +config BSP_USING_SPI1 +bool "Using spi1 " +default n + +if BSP_USING_SPI1 + config SPI_BUS_NAME_1 + string "spi bus 1 name" + default "spi1" + config SPI_1_DRV_NAME + string "spi bus 1 driver name" + default "spi1_drv" +endif + +config BSP_USING_SPI2 +bool "Using spi2 " +default n + +if BSP_USING_SPI2 + config SPI_BUS_NAME_2 + string "spi bus 2 name" + default "spi2" + config SPI_2_DRV_NAME + string "spi bus 2 driver name" + default "spi2_drv" + menuconfig RESOURCES_SPI_LORA + bool "Using spi lora function" + default n + if RESOURCES_SPI_LORA + config SX12XX_SPI_DEVICE_NAME + string "SX1278 lora device spi name" + default "spi2_dev0" + config SX12XX_DEVICE_NAME + string "SX1278 lora device name" + default "spi2_lora" + + config SX12XX_DEVICE_RST_PIN + int + default 10 + + config SX12XX_DEVICE_DO0_PIN + int + default 10 + + config SX12XX_DEVICE_DO1_PIN + int + default 10 + + config SX12XX_DEVICE_DO2_PIN + int + default 10 + + config SX12XX_DEVICE_DO3_PIN + int + default 10 + + config SX12XX_DEVICE_DO4_PIN + int + default 10 + + config SX12XX_DEVICE_DO5_PIN + int + default 10 + endif +endif + +config BSP_USING_SPI3 +bool "Using spi3 " +default n + +if BSP_USING_SPI3 + config SPI_BUS_NAME_3 + string "spi bus 3 name" + default "spi3" + config SPI_3_DRV_NAME + string "spi bus 3 driver name" + default "spi3_drv" +endif diff --git a/Ubiquitous/XiZi/board/aiit-arm32-board/third_party_driver/spi/Makefile b/Ubiquitous/XiZi/board/aiit-arm32-board/third_party_driver/spi/Makefile new file mode 100644 index 0000000..e87afde --- /dev/null +++ b/Ubiquitous/XiZi/board/aiit-arm32-board/third_party_driver/spi/Makefile @@ -0,0 +1,12 @@ +SRC_FILES := hardware_spi.c connect_spi.c + +ifeq ($(CONFIG_RESOURCES_SPI_SFUD),y) + SRC_FILES += connect_flash_spi.c +endif + +ifeq ($(CONFIG_RESOURCES_SPI_LORA),y) + SRC_DIR += third_party_spi_lora + SRC_FILES += connect_lora_spi.c +endif + +include $(KERNEL_ROOT)/compiler.mk diff --git a/Ubiquitous/XiZi/board/aiit-arm32-board/third_party_driver/spi/connect_flash_spi.c b/Ubiquitous/XiZi/board/aiit-arm32-board/third_party_driver/spi/connect_flash_spi.c new file mode 100644 index 0000000..ca67e28 --- /dev/null +++ b/Ubiquitous/XiZi/board/aiit-arm32-board/third_party_driver/spi/connect_flash_spi.c @@ -0,0 +1,56 @@ +/* + * Copyright (c) 2020 RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2018-11-27 SummerGift add spi flash port file + */ + +/** +* @file connect_flash_spi.c +* @brief support aiit-arm32-board spi flash function and register to bus framework +* @version 1.0 +* @author AIIT XUOS Lab +* @date 2021-04-25 +*/ + +/************************************************* +File name: connect_flash_spi.c +Description: support aiit-arm32-board spi flash bus register function +Others: take RT-Thread v4.0.2/bsp/stm32/stm32f407-atk-explorer/board/ports/spi-flash-init.c + https://github.com/RT-Thread/rt-thread/tree/v4.0.2 +History: +1. Date: 2021-04-25 +Author: AIIT XUOS Lab +Modification: +1. support aiit-arm32-board spi flash register to spi bus +2. support aiit-arm32-board spi flash init +*************************************************/ + +#include +#include +#include + +int FlashW25qxxSpiDeviceInit(void) +{ +#ifdef BSP_USING_SPI1 + + __IO uint32_t tmpreg = 0x00U; + RCC->AHB1ENR |= RCC_AHB1ENR_GPIOBEN; + tmpreg = RCC->AHB1ENR & RCC_AHB1ENR_GPIOBEN; + (void)tmpreg; + + if (EOK != HwSpiDeviceAttach(SPI_BUS_NAME_1, "spi1_dev0", GPIOB, GPIO_Pin_0)) { + return ERROR; + } + + if (NONE == SpiFlashInit(SPI_BUS_NAME_1, "spi1_dev0", SPI_1_DRV_NAME, "spi1_W25Q64")) { + return ERROR; + } + +#endif + + return EOK; +} \ No newline at end of file diff --git a/Ubiquitous/XiZi/board/aiit-arm32-board/third_party_driver/spi/connect_lora_spi.c b/Ubiquitous/XiZi/board/aiit-arm32-board/third_party_driver/spi/connect_lora_spi.c new file mode 100644 index 0000000..ec61b30 --- /dev/null +++ b/Ubiquitous/XiZi/board/aiit-arm32-board/third_party_driver/spi/connect_lora_spi.c @@ -0,0 +1,562 @@ +/* +* Copyright (c) 2020 AIIT XUOS Lab +* XiUOS is licensed under Mulan PSL v2. +* You can use this software according to the terms and conditions of the Mulan PSL v2. +* You may obtain a copy of Mulan PSL v2 at: +* http://license.coscl.org.cn/MulanPSL2 +* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, +* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, +* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. +* See the Mulan PSL v2 for more details. +*/ + +/** +* @file connect_lora_spi.c +* @brief support to register spi lora pointer and function +* @version 1.0 +* @author AIIT XUOS Lab +* @date 2021-05-17 +*/ + +#include + +static struct HardwareDev *g_spi_lora_dev; +static BusType buspin; +tRadioDriver *Radio = NONE; +void SX1276InitIo(void) +{ + struct PinParam PinCfg; + struct PinStat PinStat; + + struct BusConfigureInfo configure_info; + struct BusBlockWriteParam write_param; + + write_param.buffer = (void *)&PinStat; + configure_info.configure_cmd = OPE_CFG; + configure_info.private_data = (void *)&PinCfg; + + buspin = PinBusInitGet(); + + PinCfg.cmd = GPIO_CONFIG_MODE; + PinCfg.pin = SX12XX_DEVICE_DO0_PIN; + PinCfg.mode = GPIO_CFG_INPUT; + BusDrvConfigure(buspin->owner_driver, &configure_info); + + PinCfg.cmd = GPIO_CONFIG_MODE; + PinCfg.pin = SX12XX_DEVICE_DO1_PIN; + PinCfg.mode = GPIO_CFG_INPUT; + BusDrvConfigure(buspin->owner_driver, &configure_info); + + PinCfg.cmd = GPIO_CONFIG_MODE; + PinCfg.pin = SX12XX_DEVICE_DO2_PIN; + PinCfg.mode = GPIO_CFG_INPUT; + BusDrvConfigure(buspin->owner_driver, &configure_info); +} + +inline uint8_t SX1276ReadDio0(void) +{ + struct PinStat PinStat; + + struct BusBlockReadParam read_param; + read_param.buffer = (void *)&PinStat; + + PinStat.pin = SX12XX_DEVICE_DO0_PIN; + + return BusDevReadData(buspin->owner_haldev, &read_param); +} + +inline uint8_t SX1276ReadDio1(void) +{ + struct PinStat PinStat; + + struct BusBlockReadParam read_param; + read_param.buffer = (void *)&PinStat; + + PinStat.pin = SX12XX_DEVICE_DO1_PIN; + + return BusDevReadData(buspin->owner_haldev, &read_param); +} + +inline uint8_t SX1276ReadDio2(void) +{ + struct PinStat PinStat; + + struct BusBlockReadParam read_param; + read_param.buffer = (void *)&PinStat; + + PinStat.pin = SX12XX_DEVICE_DO2_PIN; + + return BusDevReadData(buspin->owner_haldev, &read_param); +} + +inline uint8_t SX1276ReadDio3(void) +{ + struct PinStat PinStat; + + struct BusBlockReadParam read_param; + read_param.buffer = (void *)&PinStat; + + PinStat.pin = SX12XX_DEVICE_DO3_PIN; + + return BusDevReadData(buspin->owner_haldev, &read_param); +} + +inline uint8_t SX1276ReadDio4(void) +{ + struct PinStat PinStat; + + struct BusBlockReadParam read_param; + read_param.buffer = (void *)&PinStat; + + PinStat.pin = SX12XX_DEVICE_DO4_PIN; + + return BusDevReadData(buspin->owner_haldev, &read_param); +} + +inline uint8_t SX1276ReadDio5(void) +{ + struct PinStat PinStat; + + struct BusBlockReadParam read_param; + read_param.buffer = (void *)&PinStat; + + PinStat.pin = SX12XX_DEVICE_DO5_PIN; + + return BusDevReadData(buspin->owner_haldev, &read_param); +} + +inline void SX1276WriteRxTx(uint8_t txEnable) +{ + if (txEnable != 0) + { + /*to do*/ + } + else + { + /*to do*/ + } +} + +void SX1276SetReset(uint8_t state) +{ + struct PinParam PinCfg; + struct PinStat PinStat; + + struct BusConfigureInfo configure_info; + struct BusBlockWriteParam write_param; + + configure_info.configure_cmd = OPE_CFG; + configure_info.private_data = (void *)&PinCfg; + write_param.buffer = (void *)&PinStat; + + if (state == RADIO_RESET_ON) + { + PinCfg.cmd = GPIO_CONFIG_MODE; + PinCfg.pin = SX12XX_DEVICE_RST_PIN; + PinCfg.mode = GPIO_CFG_OUTPUT; + BusDrvConfigure(buspin->owner_driver, &configure_info); + + PinStat.val = GPIO_LOW; + PinStat.pin = SX12XX_DEVICE_RST_PIN; + BusDevWriteData(buspin->owner_haldev, &write_param); + } + else + { + PinCfg.cmd = GPIO_CONFIG_MODE; + PinCfg.pin = SX12XX_DEVICE_RST_PIN; + PinCfg.mode = GPIO_CFG_INPUT; + BusDrvConfigure(buspin->owner_driver, &configure_info); + } +} + +void SX1276Write(uint8_t addr, uint8_t data) +{ + SX1276WriteBuffer(addr, &data, 1); +} + +void SX1276Read(uint8_t addr, uint8_t *data) +{ + SX1276ReadBuffer(addr, data, 1); +} + +void SX1276WriteBuffer(uint8_t addr, uint8_t *buffer, uint8_t size) +{ + struct BusBlockWriteParam write_param; + uint8 write_addr = addr | 0x80; + + BusDevOpen(g_spi_lora_dev); + + write_param.buffer = (void *)&write_addr; + write_param.size = 1; + BusDevWriteData(g_spi_lora_dev, &write_param); + + write_param.buffer = (void *)buffer; + write_param.size = size; + BusDevWriteData(g_spi_lora_dev, &write_param); + + BusDevClose(g_spi_lora_dev); +} + +void SX1276ReadBuffer(uint8_t addr, uint8_t *buffer, uint8_t size) +{ + struct BusBlockWriteParam write_param; + struct BusBlockReadParam read_param; + + uint8 write_addr = addr & 0x7F; + + BusDevOpen(g_spi_lora_dev); + + write_param.buffer = (void *)&write_addr; + write_param.size = 1; + BusDevWriteData(g_spi_lora_dev, &write_param); + + read_param.buffer = (void *)buffer; + read_param.size = size; + BusDevReadData(g_spi_lora_dev, &read_param); + + BusDevClose(g_spi_lora_dev); +} + +void SX1276WriteFifo(uint8_t *buffer, uint8_t size) +{ + SX1276WriteBuffer(0, buffer, size); +} + +void SX1276ReadFifo(uint8_t *buffer, uint8_t size) +{ + SX1276ReadBuffer(0, buffer, size); +} + +uint8_t SX1276_Spi_Check() +{ + uint8_t test = 0; + KPrintf("SX1276_Spi_Check start\n"); + tLoRaSettings settings; + SX1276Read(REG_LR_VERSION,&test); + KPrintf("version code of the chip is %x\n",test); + settings.RFFrequency = SX1276LoRaGetRFFrequency(); + KPrintf("SX1278 Lora parameters are :\nRFFrequency is %d\n",settings.RFFrequency); + settings.Power = SX1276LoRaGetRFPower(); + KPrintf("RFPower is %d\n",settings.Power); + settings.SignalBw = SX1276LoRaGetSignalBandwidth(); + KPrintf("SignalBw is %d\n",settings.SignalBw); + settings.SpreadingFactor = SX1276LoRaGetSpreadingFactor(); + KPrintf("SpreadingFactor is %d\n",settings.SpreadingFactor); + /*SPI confirm*/ + SX1276Write(REG_LR_HOPPERIOD, 0x91); + SX1276Read(REG_LR_HOPPERIOD, &test); + if (test != 0x91) { + return 0; + } + return test; +} + +/** + * This function supports to write data to the lora. + * + * @param dev lora dev descriptor + * @param write_param lora dev write datacfg param + */ +static uint32 SpiLoraWrite(void *dev, struct BusBlockWriteParam *write_param) +{ + NULL_PARAM_CHECK(dev); + NULL_PARAM_CHECK(write_param); + + if (write_param->size > 256) { + KPrintf("SpiLoraWrite ERROR:The message is too long!\n"); + return ERROR; + } else { + //Radio->SetTxPacket(write_param->buffer, write_param->size); + //while(Radio->Process() != RF_TX_DONE); + SX1276SetTxPacket(write_param->buffer, write_param->size); + while(SX1276Process() != RF_TX_DONE); + KPrintf("SpiLoraWrite success!\n"); + } + + return EOK; +} + +/** + * This function supports to read data from the lora. + * + * @param dev lora dev descriptor + * @param read_param lora dev read datacfg param + */ +static uint32 SpiLoraRead(void *dev, struct BusBlockReadParam *read_param) +{ + NULL_PARAM_CHECK(dev); + NULL_PARAM_CHECK(read_param); + + int read_times = 100; + + //Radio->StartRx(); + SX1276StartRx(); + KPrintf("SpiLoraRead Ready!\n"); + + while (read_times) { + if (SX1276Process() != RF_RX_DONE) { + read_times --; + MdelayKTask(500); + } else { + break; + } + } + + if (read_times > 0) { + SX1276GetRxPacket(read_param->buffer, (uint16 *)&read_param->read_length); + } else { + read_param->read_length = 0; + } + + //while(Radio->Process() != RF_RX_DONE); + //Radio->GetRxPacket(read_param->buffer, (uint16 *)&read_param->read_length); + // while(SX1276Process() != RF_RX_DONE); + // SX1276GetRxPacket(read_param->buffer, (uint16 *)&read_param->read_length); + + return read_param->read_length; +} + +static uint32 SpiLoraOpen(void *dev) +{ + NULL_PARAM_CHECK(dev); + + KPrintf("SpiLoraOpen start\n"); + + x_err_t ret = EOK; + static x_bool lora_init_status = RET_FALSE; + + if (RET_TRUE == lora_init_status) { + return EOK; + } + + struct HardwareDev *haldev = (struct HardwareDev *)dev; + + struct SpiHardwareDevice *lora_dev = CONTAINER_OF(haldev, struct SpiHardwareDevice, haldev); + NULL_PARAM_CHECK(lora_dev); + + SpiLoraDeviceType spi_lora_dev = CONTAINER_OF(lora_dev, struct SpiLoraDevice, lora_dev); + NULL_PARAM_CHECK(spi_lora_dev); + + struct Driver *spi_drv = spi_lora_dev->spi_dev->haldev.owner_bus->owner_driver; + + struct BusConfigureInfo configure_info; + struct SpiMasterParam spi_master_param; + spi_master_param.spi_data_bit_width = 8; + spi_master_param.spi_work_mode = SPI_MODE_0 | SPI_MSB; + spi_master_param.spi_maxfrequency = SPI_LORA_FREQUENCY; + spi_master_param.spi_data_endian = 0; + + configure_info.configure_cmd = OPE_CFG; + configure_info.private_data = (void *)&spi_master_param; + ret = BusDrvConfigure(spi_drv, &configure_info); + if (ret) { + KPrintf("spi drv OPE_CFG error drv %8p cfg %8p\n", spi_drv, &spi_master_param); + return ERROR; + } + + configure_info.configure_cmd = OPE_INT; + ret = BusDrvConfigure(spi_drv, &configure_info); + if (ret) { + KPrintf("spi drv OPE_INT error drv %8p\n", spi_drv); + return ERROR; + } + + SX1276Init(); + + if (0x91 != SX1276_Spi_Check()) { + KPrintf("LoRa check failed!\n!"); + } else { + Radio = RadioDriverInit(); + KPrintf("LoRa check ok!\nNote: The length of the message that can be sent in a single time is 256 characters\n"); + } + + lora_init_status = RET_TRUE; + + return ret; +} + +static uint32 SpiLoraClose(void *dev) +{ + NULL_PARAM_CHECK(dev); + + return EOK; +} + +static const struct LoraDevDone lora_done = +{ + .open = SpiLoraOpen, + .close = SpiLoraClose, + .write = SpiLoraWrite, + .read = SpiLoraRead, +}; + +/** + * This function supports to init spi_lora_dev + * + * @param bus_name spi bus name + * @param dev_name spi dev name + * @param drv_name spi drv name + * @param flash_name flash dev name + */ +SpiLoraDeviceType SpiLoraInit(char *bus_name, char *dev_name, char *drv_name, char *lora_name) +{ + NULL_PARAM_CHECK(dev_name); + NULL_PARAM_CHECK(drv_name); + NULL_PARAM_CHECK(lora_name); + NULL_PARAM_CHECK(bus_name); + + x_err_t ret; + static HardwareDevType haldev; + + haldev = SpiDeviceFind(dev_name, TYPE_SPI_DEV); + if (NONE == haldev) { + KPrintf("SpiLoraInit find spi haldev %s error! \n", dev_name); + return NONE; + } + + SpiLoraDeviceType spi_lora_dev = (SpiLoraDeviceType)malloc(sizeof(struct SpiLoraDevice)); + if (NONE == spi_lora_dev) { + KPrintf("SpiLoraInit malloc spi_lora_dev failed\n"); + free(spi_lora_dev); + return NONE; + } + + memset(spi_lora_dev, 0, sizeof(struct SpiLoraDevice)); + + spi_lora_dev->spi_dev = CONTAINER_OF(haldev, struct SpiHardwareDevice, haldev); + + spi_lora_dev->lora_dev.spi_dev_flag = RET_TRUE; + spi_lora_dev->lora_dev.haldev.dev_done = (struct HalDevDone *)&lora_done; + + spi_lora_dev->spi_dev->haldev.owner_bus->owner_driver = SpiDriverFind(drv_name, TYPE_SPI_DRV); + if (NONE == spi_lora_dev->spi_dev->haldev.owner_bus->owner_driver) { + KPrintf("SpiLoraInit find spi driver %s error! \n", drv_name); + free(spi_lora_dev); + return NONE; + } + + ret = SpiDeviceRegister(&spi_lora_dev->lora_dev, spi_lora_dev->spi_dev->haldev.private_data, lora_name); + if (EOK != ret) { + KPrintf("SpiLoraInit SpiDeviceRegister device %s error %d\n", lora_name, ret); + free(spi_lora_dev); + return NONE; + } + + ret = SpiDeviceAttachToBus(lora_name, bus_name); + if (EOK != ret) { + KPrintf("SpiLoraInit SpiDeviceAttachToBus device %s error %d\n", lora_name, ret); + free(spi_lora_dev); + return NONE; + } + + g_spi_lora_dev = &spi_lora_dev->spi_dev->haldev; + + return spi_lora_dev; +} + +/** + * This function supports to release spi_lora_dev + * + * @param spi_lora_dev spi lora descriptor + */ +uint32 SpiLoraRelease(SpiLoraDeviceType spi_lora_dev) +{ + NULL_PARAM_CHECK(spi_lora_dev); + + x_err_t ret; + + DeviceDeleteFromBus(spi_lora_dev->lora_dev.haldev.owner_bus, &spi_lora_dev->lora_dev.haldev); + + free(spi_lora_dev); + + return EOK; +} + +int LoraSx12xxSpiDeviceInit(void) +{ +#ifdef BSP_USING_SPI2 + __IO uint32_t tmpreg = 0x00U; + RCC->AHB1ENR |= RCC_AHB1ENR_GPIOAEN; + tmpreg = RCC->AHB1ENR & RCC_AHB1ENR_GPIOAEN; + (void)tmpreg; + + if (EOK != HwSpiDeviceAttach(SPI_BUS_NAME_2, SX12XX_SPI_DEVICE_NAME, GPIOC, GPIO_Pin_6)) { + return ERROR; + } + + if (NONE == SpiLoraInit(SPI_BUS_NAME_2, SX12XX_SPI_DEVICE_NAME, SPI_2_DRV_NAME, SX12XX_DEVICE_NAME)) { + return ERROR; + } + +#endif + + return EOK; +} + +//#define LORA_TEST +#ifdef LORA_TEST +/*Just for lora test*/ +static struct Bus *bus; +static struct HardwareDev *dev; +static struct Driver *drv; + +void LoraOpen(void) +{ + x_err_t ret = EOK; + + ret = LoraSx12xxSpiDeviceInit(); + if (EOK != ret) { + KPrintf("LoraSx12xxSpiDeviceInit failed\n"); + return; + } + + bus = BusFind(SPI_BUS_NAME_2); + dev = BusFindDevice(bus, SX12XX_DEVICE_NAME); + drv = BusFindDriver(bus, SPI_2_DRV_NAME); + + bus->match(drv, dev); + + ret = SpiLoraOpen(dev); + if (EOK != ret) { + KPrintf("LoRa init failed\n"); + return; + } + + KPrintf("LoRa init succeed\n"); + + return; +} +SHELL_EXPORT_CMD(SHELL_CMD_PERMISSION(0)|SHELL_CMD_TYPE(SHELL_TYPE_CMD_MAIN), + LoraOpen, LoraOpen, open lora device and read parameters ); + +static void LoraReceive(void) +{ + struct BusBlockReadParam read_param; + memset(&read_param, 0, sizeof(struct BusBlockReadParam)); + + read_param.buffer = malloc(SPI_LORA_BUFFER_SIZE); + + SpiLoraRead(dev, &read_param); + + free(read_param.buffer); +} +SHELL_EXPORT_CMD(SHELL_CMD_PERMISSION(0)|SHELL_CMD_TYPE(SHELL_TYPE_CMD_FUNC)|SHELL_CMD_PARAM_NUM(0), +LoraReceive, LoraReceive, lora wait message ); + +static void LoraSend(int argc, char *argv[]) +{ + char Msg[SPI_LORA_BUFFER_SIZE] = {0}; + struct BusBlockWriteParam write_param; + memset(&write_param, 0, sizeof(struct BusBlockWriteParam)); + + if (argc == 2) { + strncpy(Msg, argv[1], SPI_LORA_BUFFER_SIZE); + write_param.buffer = Msg; + write_param.size = strlen(Msg); + + SpiLoraWrite(dev, &write_param); + } +} +SHELL_EXPORT_CMD(SHELL_CMD_PERMISSION(0)|SHELL_CMD_TYPE(SHELL_TYPE_CMD_MAIN), +LoraSend, LoraSend, lora send message ); +#endif diff --git a/Ubiquitous/XiZi/board/aiit-arm32-board/third_party_driver/spi/connect_spi.c b/Ubiquitous/XiZi/board/aiit-arm32-board/third_party_driver/spi/connect_spi.c new file mode 100644 index 0000000..813a46a --- /dev/null +++ b/Ubiquitous/XiZi/board/aiit-arm32-board/third_party_driver/spi/connect_spi.c @@ -0,0 +1,1654 @@ +/* + * Copyright (c) 2020 RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2018-11-5 SummerGift first version + * 2018-12-11 greedyhao Porting for stm32f7xx + * 2019-01-03 zylx modify DMA initialization and spixfer function + * 2020-01-15 whj4674672 Porting for stm32h7xx + * 2020-06-18 thread-liu Porting for stm32mp1xx + * 2020-10-14 Dozingfiretruck Porting for stm32wbxx + */ + +/** +* @file connect_spi.c +* @brief support aiit-arm32-board spi function and register to bus framework +* @version 1.0 +* @author AIIT XUOS Lab +* @date 2021-04-25 +*/ + +/************************************************* +File name: connect_spi.c +Description: support aiit-arm32-board spi configure and spi bus register function +Others: take RT-Thread v4.0.2/bsp/stm32/libraries/HAL_Drivers/drv_spi.c for references + https://github.com/RT-Thread/rt-thread/tree/v4.0.2 +History: +1. Date: 2021-04-25 +Author: AIIT XUOS Lab +Modification: +1. support aiit-arm32-board spi configure, write and read +2. support aiit-arm32-board spi bus device and driver register +*************************************************/ + +#include +#include +#include +#include +#include +#include +#include +#include + +/* SPI GPIO define */ +#ifdef BSP_USING_SPI1 +#define SPI1_GPIO_NSS GPIO_Pin_4 +#define SPI1_NSS_PIN_SOURCE GPIO_PinSource4 +#define SPI1_GPIO_SCK GPIO_Pin_5 +#define SPI1_SCK_PIN_SOURCE GPIO_PinSource5 +#define SPI1_GPIO_MISO GPIO_Pin_6 +#define SPI1_MISO_PIN_SOURCE GPIO_PinSource6 +#define SPI1_GPIO_MOSI GPIO_Pin_7 +#define SPI1_MOSI_PIN_SOURCE GPIO_PinSource7 +#define SPI1_GPIO GPIOA +#define SPI1_GPIO_RCC RCC_AHB1Periph_GPIOA +#define RCC_APBPeriph_SPI1 RCC_APB2Periph_SPI1 +#endif + +#ifdef BSP_USING_SPI2 +#define SPI2_GPIO_NSS GPIO_Pin_6 +#define SPI2_NSS_PIN_SOURCE GPIO_PinSource6 +#define SPI2_GPIO_SCK GPIO_Pin_13 +#define SPI2_SCK_PIN_SOURCE GPIO_PinSource13 +#define SPI2_GPIO_MISO GPIO_Pin_2 +#define SPI2_MISO_PIN_SOURCE GPIO_PinSource2 +#define SPI2_GPIO_MOSI GPIO_Pin_3 +#define SPI2_MOSI_PIN_SOURCE GPIO_PinSource3 +#define SPI2_GPIO GPIOC +#define SPI2_SCK GPIOB +#define SPI2_GPIO_RCC RCC_AHB1Periph_GPIOC +#define SPI2_GPIO_RCC_SCK RCC_AHB1Periph_GPIOB +#define RCC_APBPeriph_SPI2 RCC_APB1Periph_SPI2 +#endif + +#ifdef BSP_USING_SPI3 +#define SPI3_GPIO_NSS GPIO_Pin_15 +#define SPI3_NSS_PIN_SOURCE GPIO_PinSource15 +#define SPI3_GPIO_SCK GPIO_Pin_10 +#define SPI3_SCK_PIN_SOURCE GPIO_PinSource10 +#define SPI3_GPIO_MISO GPIO_Pin_11 +#define SPI3_MISO_PIN_SOURCE GPIO_PinSource11 +#define SPI3_GPIO_MOSI GPIO_Pin_12 +#define SPI3_MOSI_PIN_SOURCE GPIO_PinSource12 +#define SPI3_GPIO GPIOC +#define SPI3_NSS GPIOA +#define SPI3_GPIO_RCC RCC_AHB1Periph_GPIOC +#define SPI3_GPIO_RCC_NSS RCC_AHB1Periph_GPIOA +#define RCC_APBPeriph_SPI3 RCC_APB2Periph_SPI3 +#endif + +/** + * This function SPI device initialization + * @param SpiDrv SPI device structure pointer + * @param cfg SPI device operating mode configuration structure pointer + * @return if successful return EOK + */ +static x_err_t Stm32SpiInit(struct Stm32Spi *SpiDrv, struct SpiMasterParam *cfg) +{ + NULL_PARAM_CHECK(SpiDrv); + NULL_PARAM_CHECK(cfg); + + SPI_InitTypeDef *SpiInit = &SpiDrv->init; + + if (cfg->spi_work_mode & DEV_SPI_SLAVE) + { + SpiInit->SPI_Mode = SPI_Mode_Slave; + } + else + { + SpiInit->SPI_Mode = SPI_Mode_Master; + } + + if (cfg->spi_work_mode & SPI_3WIRE) + { + SpiInit->SPI_Direction = SPI_Direction_1Line_Rx; + } + else + { + SpiInit->SPI_Direction = SPI_Direction_2Lines_FullDuplex; + } + + if (cfg->spi_data_bit_width == 8) + { + SpiInit->SPI_DataSize = SPI_DataSize_8b; + } + else if (cfg->spi_data_bit_width == 16) + { + SpiInit->SPI_DataSize = SPI_DataSize_16b; + } + else + { + return EPIO; + } + + if (cfg->spi_work_mode & SPI_LINE_CPHA) + { + SpiInit->SPI_CPHA = SPI_CPHA_2Edge; + } + else + { + SpiInit->SPI_CPHA = SPI_CPHA_1Edge; + } + + if (cfg->spi_work_mode & SPI_LINE_CPOL) + { + SpiInit->SPI_CPOL = SPI_CPOL_High; + } + else + { + SpiInit->SPI_CPOL = SPI_CPOL_Low; + } + + if (cfg->spi_work_mode & SPI_NO_CS) + { + SpiInit->SPI_NSS = SPI_NSS_Soft; + } + else + { + SpiInit->SPI_NSS = SPI_NSS_Soft; + } + + uint32_t SPI_APB_CLOCK; + + SPI_APB_CLOCK = system_core_clock>>apb_presc_table[(RCC->CFGR & RCC_CFGR_PPRE2)>> 13U]; + + if (cfg->spi_maxfrequency >= SPI_APB_CLOCK / 2) + { + SpiInit->SPI_BaudRatePrescaler = SPI_BaudRatePrescaler_2; + } + else if (cfg->spi_maxfrequency >= SPI_APB_CLOCK / 4) + { + SpiInit->SPI_BaudRatePrescaler = SPI_BaudRatePrescaler_4; + } + else if (cfg->spi_maxfrequency >= SPI_APB_CLOCK / 8) + { + SpiInit->SPI_BaudRatePrescaler = SPI_BaudRatePrescaler_8; + } + else if (cfg->spi_maxfrequency >= SPI_APB_CLOCK / 16) + { + SpiInit->SPI_BaudRatePrescaler = SPI_BaudRatePrescaler_16; + } + else if (cfg->spi_maxfrequency >= SPI_APB_CLOCK / 32) + { + SpiInit->SPI_BaudRatePrescaler = SPI_BaudRatePrescaler_32; + } + else if (cfg->spi_maxfrequency >= SPI_APB_CLOCK / 64) + { + SpiInit->SPI_BaudRatePrescaler = SPI_BaudRatePrescaler_64; + } + else if (cfg->spi_maxfrequency >= SPI_APB_CLOCK / 128) + { + SpiInit->SPI_BaudRatePrescaler = SPI_BaudRatePrescaler_128; + } + else + { + /* min prescaler 256 */ + SpiInit->SPI_BaudRatePrescaler = SPI_BaudRatePrescaler_256; + } + RCC_ClocksTypeDef RCC_ClocksStatus; + RCC_GetClocksFreq(&RCC_ClocksStatus); + + if (cfg->spi_work_mode & SPI_MSB) + { + SpiInit->SPI_FirstBit = SPI_FirstBit_MSB; /*Highest bit transmit first*/ + } + else + { + SpiInit->SPI_FirstBit = SPI_FirstBit_LSB; /*lowest bit transmit first*/ + } + + SpiInit->SPI_CRCPolynomial = 7; + + SPI_Init(SpiDrv->instance, SpiInit); + + SPI_Cmd(SpiDrv->instance, ENABLE); + + uint32_t prioritygroup = 0x00U; + /* DMA configuration */ + if (SpiDrv->spi_dma_flag & SPI_USING_RX_DMA_FLAG) + { + DMA_Init(SpiDrv->dma.dma_rx.instance, &SpiDrv->dma.dma_rx.init); + + prioritygroup = NVIC_GetPriorityGrouping(); + + NVIC_SetPriority(SpiDrv->dma.dma_rx.dma_irq, NVIC_EncodePriority(prioritygroup, 0, 0)); + + NVIC_EnableIRQ(SpiDrv->dma.dma_rx.dma_irq); + } + + if (SpiDrv->spi_dma_flag & SPI_USING_TX_DMA_FLAG) + { + DMA_Init(SpiDrv->dma.dma_tx.instance, &SpiDrv->dma.dma_tx.init); + + prioritygroup = NVIC_GetPriorityGrouping(); + + NVIC_SetPriority(SpiDrv->dma.dma_tx.dma_irq, NVIC_EncodePriority(prioritygroup, 0, 1)); + + NVIC_EnableIRQ(SpiDrv->dma.dma_tx.dma_irq); + } + + SpiDrv->instance->CR1 |= SPI_CR1_SPE; + + return EOK; +} + +/** + * This function Use DMA during spi transfer + * @param spi_bus SPI bus handle + * @param SettingLen Set data length + * @param RxBaseAddr Base address for receiving data + * @param TxBaseAddr Base address for sending data + * @return none + */ +static void DmaSpiConfig(struct SpiBus *spi_bus, uint32_t setting_len, void *rx_base_addr, void *tx_base_addr) +{ + struct Stm32Spi *spi = (struct Stm32Spi *)spi_bus->private_data; + uint32 tmpreg = 0x00U; + NVIC_InitTypeDef NVIC_InitStructure; + + if(spi->spi_dma_flag & SPI_USING_RX_DMA_FLAG) + { + spi->dma.dma_rx.setting_len = setting_len; + DMA_DeInit(spi->dma.dma_rx.instance); + while(DMA_GetCmdStatus(spi->dma.dma_rx.instance) != DISABLE); + spi->dma.dma_rx.init.DMA_Channel = spi->dma.dma_rx.channel; + spi->dma.dma_rx.init.DMA_PeripheralBaseAddr = (uint32_t)&(spi->instance->DR); + spi->dma.dma_rx.init.DMA_Memory0BaseAddr = (uint32_t)rx_base_addr; + spi->dma.dma_rx.init.DMA_DIR = DMA_DIR_PeripheralToMemory; + spi->dma.dma_rx.init.DMA_BufferSize = spi->dma.dma_rx.setting_len; + spi->dma.dma_rx.init.DMA_PeripheralInc = DMA_PeripheralInc_Disable; + spi->dma.dma_rx.init.DMA_MemoryInc = DMA_MemoryInc_Enable; + spi->dma.dma_rx.init.DMA_PeripheralDataSize = DMA_PeripheralDataSize_Byte; + spi->dma.dma_rx.init.DMA_MemoryDataSize = DMA_MemoryDataSize_Byte; + spi->dma.dma_rx.init.DMA_Mode = DMA_Mode_Normal; + spi->dma.dma_rx.init.DMA_Priority = DMA_Priority_High; + spi->dma.dma_rx.init.DMA_FIFOMode = DMA_FIFOMode_Disable; + spi->dma.dma_rx.init.DMA_FIFOThreshold = DMA_FIFOThreshold_Full; + spi->dma.dma_rx.init.DMA_MemoryBurst = DMA_MemoryBurst_INC4; + spi->dma.dma_rx.init.DMA_PeripheralBurst = DMA_PeripheralBurst_INC4; + DMA_Init(spi->dma.dma_rx.instance, &spi->dma.dma_rx.init); + DMA_ITConfig(spi->dma.dma_rx.instance, DMA_IT_TC, ENABLE); + + RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_DMA1, ENABLE); + RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_DMA2, ENABLE); + + DMA_Cmd(spi->dma.dma_rx.instance, ENABLE); + + NVIC_InitStructure.NVIC_IRQChannel = spi->dma.dma_rx.dma_irq; + NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 0; + NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0; + NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE; + NVIC_Init(&NVIC_InitStructure); + + tmpreg = 0x00U; + RCC->AHB1ENR |= spi->dma.dma_rx.dma_rcc; + tmpreg = RCC->AHB1ENR & spi->dma.dma_rx.dma_rcc; + (void)tmpreg; + } + + if(spi->spi_dma_flag & SPI_USING_TX_DMA_FLAG) + { + spi->dma.dma_tx.setting_len = setting_len; + DMA_DeInit(spi->dma.dma_tx.instance); + while(DMA_GetCmdStatus(spi->dma.dma_tx.instance) != DISABLE); + spi->dma.dma_tx.init.DMA_PeripheralBaseAddr = (uint32_t)&(spi->instance->DR); + spi->dma.dma_tx.init.DMA_Memory0BaseAddr = (uint32_t)tx_base_addr; + spi->dma.dma_tx.init.DMA_DIR = DMA_DIR_MemoryToPeripheral; + spi->dma.dma_tx.init.DMA_BufferSize = spi->dma.dma_tx.setting_len; + spi->dma.dma_tx.init.DMA_PeripheralInc = DMA_PeripheralInc_Disable; + spi->dma.dma_tx.init.DMA_MemoryInc = DMA_MemoryInc_Enable; + spi->dma.dma_tx.init.DMA_PeripheralDataSize = DMA_PeripheralDataSize_Byte; + spi->dma.dma_tx.init.DMA_MemoryDataSize = DMA_MemoryDataSize_Byte; + spi->dma.dma_tx.init.DMA_Mode = DMA_Mode_Normal; + spi->dma.dma_tx.init.DMA_Priority = DMA_Priority_Low; + spi->dma.dma_tx.init.DMA_FIFOMode = DMA_FIFOMode_Disable; + spi->dma.dma_tx.init.DMA_FIFOThreshold = DMA_FIFOThreshold_Full; + spi->dma.dma_tx.init.DMA_MemoryBurst = DMA_MemoryBurst_INC4; + spi->dma.dma_tx.init.DMA_PeripheralBurst = DMA_PeripheralBurst_INC4; + DMA_Init(spi->dma.dma_tx.instance, &spi->dma.dma_tx.init); + DMA_ITConfig(spi->dma.dma_tx.instance, DMA_IT_TC, ENABLE); + + RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_DMA1, ENABLE); + RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_DMA2, ENABLE); + + DMA_Cmd(spi->dma.dma_tx.instance, ENABLE); + + NVIC_InitStructure.NVIC_IRQChannel = spi->dma.dma_tx.dma_irq; + NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 0; + NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0; + NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE; + NVIC_Init(&NVIC_InitStructure); + + tmpreg = 0x00U; + RCC->AHB1ENR |= spi->dma.dma_rx.dma_rcc; + tmpreg = RCC->AHB1ENR & spi->dma.dma_rx.dma_rcc; + (void)tmpreg; + } +} + +/** + * This function DMA receiving completion interrupt + * @param spi_bus SPI bus pointer + * @return none + */ +static void DmaRxDoneIsr(struct SpiBus *spi_bus) +{ + struct Stm32Spi *spi = (struct Stm32Spi *) spi_bus->bus.private_data; + x_size_t recv_len; + x_base level; + + if (DMA_GetFlagStatus(spi->dma.dma_rx.instance, spi->spi_dma_flag) != RESET) + { + level = CriticalAreaLock(); + + recv_len = spi->dma.dma_rx.setting_len - spi->dma.dma_rx.last_index; + spi->dma.dma_rx.last_index = 0; + CriticalAreaUnLock(level); + DMA_ClearFlag(spi->dma.dma_rx.instance, spi->spi_dma_flag); + } +} + +/** + * This function DMA sending completion interrupt + * @param spi_bus SPI bus pointer + * @return none + */ +static void DmaTxDoneIsr(struct SpiBus *spi_bus) +{ + struct Stm32Spi *spi = (struct Stm32Spi *) spi_bus->bus.private_data; + x_size_t send_len; + x_base level; + + if (DMA_GetFlagStatus(spi->dma.dma_tx.instance, spi->spi_dma_flag) != RESET) + { + level = CriticalAreaLock(); + + send_len = spi->dma.dma_tx.setting_len - spi->dma.dma_tx.last_index; + spi->dma.dma_tx.last_index = 0; + CriticalAreaUnLock(level); + DMA_ClearFlag(spi->dma.dma_tx.instance, spi->spi_dma_flag); + } +} + +/** + * This function SPI wait timeout function + * @param SpiInit SPI Init structure definition + * @param SpiInstance SPI control handle + * @param Flag SPI Status flag + * @param State SPI status + * @param Timeout Overflow time + * @param Tickstart Starting time + * @return if successful return EOK + */ +static int SpiWaitUntilTimeout(SPI_InitTypeDef SpiInit, SPI_TypeDef *SpiInstance, uint32_t Flag, uint32_t State, uint32_t Timeout, uint32_t Tickstart) +{ + while((((SpiInstance->SR & Flag) == (Flag)) ? SET : RESET) != State) + { + if(Timeout != 0xFFFFFFFFU) + { + if((Timeout == 0U) || ((CurrentTicksGain() * 1000 / TICK_PER_SECOND-Tickstart) >= Timeout)) + { + SpiInstance->CR2 &= (~(SPI_IT_TXE | SPI_IT_RXNE | SPI_IT_ERR)); + + if((SpiInit.SPI_Mode == SPI_Mode_Master)&&((SpiInit.SPI_Direction == SPI_Direction_1Line_Rx)||(SpiInit.SPI_Direction == SPI_Direction_2Lines_RxOnly))) + { + /* Disable SPI peripheral */ + SpiInstance->CR1 &= (~SPI_CR1_SPE); + } + + return 3; + } + } + } + return 0; +} + +/** + * This function SPI sends data through DMA + * @param SpiInit SPI Init structure + * @param SpiInstance SPI control handle + * @param dma_init DMA Init structure + * @param dma_instance DMA Controller + * @param pData Send data buffer address + * @param Size Amount of data sent + * @return if successful return EOK + */ +int SpiTransmitDma(SPI_InitTypeDef SpiInit, SPI_TypeDef *SpiInstance, DMA_InitTypeDef dma_init, DMA_Stream_TypeDef *dma_instance, uint8_t *pData, uint16_t Size) +{ + int errorcode = 0; + __IO uint16_t TxXferCount; + uint8_t *pTxBuffPtr; + uint16_t TxXferSize; + + if((pData == NONE) || (Size == 0)) + { + errorcode = 1; + goto error; + } + + TxXferCount = Size; + pTxBuffPtr = (uint8_t *)pData; + TxXferSize = Size; + + /* Configure communication direction : 1Line */ + if(SpiInit.SPI_Direction == SPI_Direction_1Line_Rx) + { + SpiInstance->CR1 |= SPI_CR1_BIDIOE; + } + + /* Clear DBM bit */ + dma_instance->CR &= (uint32_t)(~DMA_SxCR_DBM); + + /* Configure DMA Stream data length */ + dma_instance->NDTR = TxXferCount; + + /* Memory to Peripheral */ + if((dma_init.DMA_DIR) == DMA_DIR_MemoryToPeripheral) + { + /* Configure DMA Stream destination address */ + dma_instance->PAR = SpiInstance->DR; + + /* Configure DMA Stream source address */ + dma_instance->M0AR = *pTxBuffPtr; + } + /* Peripheral to Memory */ + else + { + /* Configure DMA Stream source address */ + dma_instance->PAR = *pTxBuffPtr; + + /* Configure DMA Stream destination address */ + dma_instance->M0AR = SpiInstance->DR; + } + + /* Enable Common interrupts*/ + dma_instance->CR |= DMA_IT_TC | DMA_IT_TE | DMA_IT_DME | DMA_IT_HT; + dma_instance->FCR |= DMA_IT_FE; + dma_instance->CR |= DMA_SxCR_EN; + + /* Check if the SPI is already enabled */ + if((SpiInstance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE) + { + /* Enable SPI peripheral */ + SpiInstance->CR1 |= SPI_CR1_SPE; + } + + /* Enable the SPI Error Interrupt Bit */ + SpiInstance->CR2 |= SPI_CR2_ERRIE; + + /* Enable Tx DMA Request */ + SpiInstance->CR2 |=SPI_CR2_TXDMAEN; + +error : + return errorcode; +} + +/** + * This function SPI carries out duplex communication through DMA + * @param SpiInit SPI Init structure + * @param SpiInstance SPI control handle + * @param dmarx_init DMA Init structure---Rx + * @param dmarx_instance DMA Controller + * @param dmatx_init DMA Init structure---Tx + * @param dmatx_instance DMA Controller + * @param pTxData Send data buffer address + * @param pRxData Receive data buffer address + * @param Size Amount of data + * @return if successful return EOK + */ +int SpiTransmitreceiveDma(SPI_InitTypeDef SpiInit, SPI_TypeDef *SpiInstance, DMA_InitTypeDef dmarx_init, DMA_Stream_TypeDef *dmarx_instance, DMA_InitTypeDef dmatx_init, DMA_Stream_TypeDef *dmatx_instance, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size) +{ + uint32_t tmp = 0U; + int errorcode = 0; + __IO uint16_t TxXferCount; + __IO uint16_t RxXferCount; + uint8_t *pTxBuffPtr; + uint8_t *pRxBuffPtr; + uint16_t TxXferSize; + uint16_t RxXferSize; + + tmp = SpiInit.SPI_Mode; + if(!((tmp == SPI_Mode_Master) && (SpiInit.SPI_Direction == SPI_Direction_2Lines_FullDuplex))) + { + errorcode = 2; + goto error; + } + + if((pTxData == NONE ) || (pRxData == NONE ) || (Size == 0)) + { + errorcode = 1; + goto error; + } + + /* Set the transaction information */ + pTxBuffPtr = (uint8_t*)pTxData; + TxXferSize = Size; + TxXferCount = Size; + pRxBuffPtr = (uint8_t*)pRxData; + RxXferSize = Size; + RxXferCount = Size; + + /* Clear DBM bit */ + dmarx_instance->CR &= (uint32_t)(~DMA_SxCR_DBM); + + /* Configure DMA Stream data length */ + dmarx_instance->NDTR = RxXferCount; + + /* Memory to Peripheral */ + if((dmarx_init.DMA_DIR) == DMA_DIR_MemoryToPeripheral) + { + /* Configure DMA Stream destination address */ + dmarx_instance->PAR = SpiInstance->DR; + + /* Configure DMA Stream source address */ + dmarx_instance->M0AR = *pRxBuffPtr; + } + /* Peripheral to Memory */ + else + { + /* Configure DMA Stream source address */ + dmarx_instance->PAR = *pRxBuffPtr; + + /* Configure DMA Stream destination address */ + dmarx_instance->M0AR = SpiInstance->DR; + } + + /* Enable Common interrupts*/ + dmarx_instance->CR |= DMA_IT_TC | DMA_IT_TE | DMA_IT_DME | DMA_IT_HT; + dmarx_instance->FCR |= DMA_IT_FE; + dmarx_instance->CR |= DMA_SxCR_EN; + + /* Enable Rx DMA Request */ + SpiInstance->CR2 |= SPI_CR2_RXDMAEN; + + /* Clear DBM bit */ + dmatx_instance->CR &= (uint32_t)(~DMA_SxCR_DBM); + + /* Configure DMA Stream data length */ + dmatx_instance->NDTR = TxXferCount; + + /* Memory to Peripheral */ + if((dmatx_init.DMA_DIR) == DMA_DIR_MemoryToPeripheral) + { + /* Configure DMA Stream destination address */ + dmatx_instance->PAR = SpiInstance->DR; + + /* Configure DMA Stream source address */ + dmatx_instance->M0AR = *pTxBuffPtr; + } + /* Peripheral to Memory */ + else + { + /* Configure DMA Stream source address */ + dmatx_instance->PAR = *pTxBuffPtr; + + /* Configure DMA Stream destination address */ + dmatx_instance->M0AR = SpiInstance->DR; + } + + /* Enable Common interrupts*/ + dmatx_instance->CR |= DMA_IT_TC | DMA_IT_TE | DMA_IT_DME | DMA_IT_HT; + dmatx_instance->FCR |= DMA_IT_FE; + dmatx_instance->CR |= DMA_SxCR_EN; + + /* Check if the SPI is already enabled */ + if((SpiInstance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE) + { + /* Enable SPI peripheral */ + SpiInstance->CR1 |= SPI_CR1_SPE; + } + /* Enable the SPI Error Interrupt Bit */ + SpiInstance->CR2 |= SPI_CR2_ERRIE; + + /* Enable Tx DMA Request */ + SpiInstance->CR2 |= SPI_CR2_TXDMAEN; + +error : + return errorcode; +} + +/** + * This function SPI receives data through DMA + * @param SpiInit SPI Init structure + * @param SpiInstance SPI control handle + * @param dmarx_init DMA Init structure---Rx + * @param dmarx_instance DMA Controller + * @param dmatx_init DMA Init structure---Tx + * @param dmatx_instance DMA Controller + * @param pData Receive data buffer address + * @param Size Amount of data + * @return if successful return EOK + */ +int SpiReceiveDma(SPI_InitTypeDef SpiInit, SPI_TypeDef *SpiInstance, DMA_InitTypeDef dmarx_init, DMA_Stream_TypeDef *dmarx_instance, DMA_InitTypeDef dmatx_init, DMA_Stream_TypeDef *dmatx_instance, uint8_t *pData, uint16_t Size) +{ + int errorcode = 0; + __IO uint16_t RxXferCount; + uint8_t *pRxBuffPtr; + uint16_t RxXferSize; + + if((SpiInit.SPI_Direction == SPI_Direction_2Lines_FullDuplex)&&(SpiInit.SPI_Mode == SPI_Mode_Master)) + { + /* Call transmit-receive function to send Dummy data on Tx line and generate clock on CLK line */ + return SpiTransmitreceiveDma(SpiInit, SpiInstance, dmarx_init, dmarx_instance, dmatx_init, dmatx_instance, pData, pData, Size); + } + + if((pData == NONE) || (Size == 0)) + { + errorcode = 1; + goto error; + } + + RxXferCount = Size; + RxXferSize = Size; + pRxBuffPtr = (uint8_t *)pData; + + /* Configure communication direction : 1Line */ + if(SpiInit.SPI_Direction == SPI_Direction_1Line_Rx) + { + SpiInstance->CR1 &= (~SPI_CR1_BIDIOE); + } + /* Clear DBM bit */ + dmarx_instance->CR &= (uint32_t)(~DMA_SxCR_DBM); + + /* Configure DMA Stream data length */ + dmarx_instance->NDTR = RxXferCount; + + /* Memory to Peripheral */ + if((dmarx_init.DMA_DIR) == DMA_DIR_MemoryToPeripheral) + { + /* Configure DMA Stream destination address */ + dmarx_instance->PAR = SpiInstance->DR; + + /* Configure DMA Stream source address */ + dmarx_instance->M0AR = *pRxBuffPtr; + } + /* Peripheral to Memory */ + else + { + /* Configure DMA Stream source address */ + dmarx_instance->PAR = *pRxBuffPtr; + + /* Configure DMA Stream destination address */ + dmarx_instance->M0AR = SpiInstance->DR; + } + + /* Enable Common interrupts*/ + dmarx_instance->CR |= DMA_IT_TC | DMA_IT_TE | DMA_IT_DME | DMA_IT_HT; + dmarx_instance->FCR |= DMA_IT_FE; + dmarx_instance->CR |= DMA_SxCR_EN; + + /* Check if the SPI is already enabled */ + if((SpiInstance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE) + { + /* Enable SPI peripheral */ + SpiInstance->CR1 |= SPI_CR1_SPE; + } + + /* Enable the SPI Error Interrupt Bit */ + SpiInstance->CR2 |= SPI_CR2_ERRIE; + + /* Enable Rx DMA Request */ + SpiInstance->CR2 |= SPI_CR2_RXDMAEN; + +error: + return errorcode; +} + +/** + * This function SPI receives data + * @param SpiInit SPI Init structure + * @param SpiInstance SPI control handle + * @param pData Transmit data buffer address + * @param Size Amount of data + * @param Timeout waiting time + * @return if successful return EOK + */ +int SpiTransmit(SPI_InitTypeDef SpiInit, SPI_TypeDef *SpiInstance, uint8_t *pData, uint16_t Size, uint32_t Timeout) +{ + uint32_t tickstart = 0U; + int errorcode = 0; + __IO uint16_t TxXferCount; + __IO uint32_t SPITimeout; + + /* Init tickstart for timeout management*/ + tickstart = CurrentTicksGain() * 1000 / TICK_PER_SECOND; + + if((pData == NONE ) || (Size == 0)) + { + errorcode = 1; + goto error; + } + + TxXferCount = Size; + + /* Configure communication direction : 1Line */ + if(SpiInit.SPI_Direction == SPI_Direction_1Line_Rx) + { + SpiInstance->CR1 |= SPI_CR1_BIDIOE; + } + + /* Check if the SPI is already enabled */ + if((SpiInstance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE) + { + /* Enable SPI peripheral */ + SpiInstance->CR1 |= SPI_CR1_SPE; + } + + /* Transmit data in 16 Bit mode */ + if(SpiInit.SPI_DataSize == SPI_DataSize_16b) + { + if((SpiInit.SPI_Mode == SPI_Mode_Slave) || (TxXferCount == 0x01)) + { + SpiInstance->DR = *((uint16_t *)pData); + + pData += sizeof(uint16_t); + TxXferCount--; + } + /* Transmit data in 16 Bit mode */ + while (TxXferCount > 0U) + { + SPITimeout = 0x1000; + /* Wait until TXE flag is set to send data */ + while (SPI_I2S_GetFlagStatus(SpiInstance, SPI_I2S_FLAG_TXE) == RESET) + { + if((SPITimeout--) == 0) + { + KPrintf("spi time out\n"); + errorcode = 3; + goto error; + } + } + /* Write to the data register and write the data to be written into the transmit buffer */ + SpiInstance->DR = *((uint16_t *)pData); + + pData += sizeof(uint16_t); + TxXferCount--; + } + } + /* Transmit data in 8 Bit mode */ + else + { + if((SpiInit.SPI_Mode == SPI_Mode_Slave) || (TxXferCount == 0x01U)) + { + *((__IO uint8_t*)&SpiInstance->DR) = (*pData); + + pData += sizeof(uint8_t); + TxXferCount--; + } + + while(TxXferCount > 0) + { + SPITimeout = 0x1000; + + /* Wait for the send buffer to be empty, TXE event*/ + while (SPI_I2S_GetFlagStatus(SpiInstance, SPI_I2S_FLAG_TXE) == RESET) + { + if((SPITimeout--) == 0) + { + KPrintf("spi time out\n"); + errorcode = 3; + goto error; + } + } + + /* Write to the data register and write the data to be written into the transmit buffer*/ + *((__IO uint8_t*)&SpiInstance->DR) = (*pData); + + pData += sizeof(uint8_t); + TxXferCount--; + } +} + + /* Wait until TXE flag */ + if(SpiWaitUntilTimeout(SpiInit, SpiInstance, SPI_FLAG_TXE, SET, Timeout, tickstart) != 0) + { + errorcode = 3; + goto error; + } + + /* Check Busy flag */ + if(SpiWaitUntilTimeout(SpiInit, SpiInstance, SPI_FLAG_BSY, RESET, Timeout, tickstart) != 0) + { + errorcode = 1; + goto error; + } + +error: + return errorcode; +} + +/** + * This function SPI Transmit and receive + * @param SpiInit SPI Init structure + * @param SpiInstance SPI control handle + * @param pTxData Transmit data buffer address + * @param pRxData receive data buffer address + * @param Size Amount of data + * @param Timeout waiting time + * @return if successful return EOK + */ +int SpiTransmitreceive(SPI_InitTypeDef SpiInit, SPI_TypeDef *SpiInstance, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size, uint32_t Timeout) +{ + uint32_t tmp = 0U; + + uint32_t tickstart = 0U; + /* Variable used to alternate Rx and Tx during transfer */ + uint32_t txallowed = 1U; + int errorcode = 0; + __IO uint16_t TxXferCount; + __IO uint16_t RxXferCount; + + /* Init tickstart for timeout management*/ + tickstart = CurrentTicksGain() * 1000 / TICK_PER_SECOND; + + tmp = SpiInit.SPI_Mode; + + if(!((tmp == SPI_Mode_Master) && (SpiInit.SPI_Direction == SPI_Direction_2Lines_FullDuplex))) + { + errorcode = 2; + goto error; + } + + if((pTxData == NONE) || (pRxData == NONE) || (Size == 0)) + { + errorcode = 1; + goto error; + } + + TxXferCount = Size; + RxXferCount = Size; + + /* Check if the SPI is already enabled */ + if((SpiInstance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE) + { + /* Enable SPI peripheral */ + SpiInstance->CR1 |= SPI_CR1_SPE; + } + + /* Transmit and Receive data in 16 Bit mode */ + if(SpiInit.SPI_DataSize == SPI_DataSize_16b) + { + if((SpiInit.SPI_Mode == SPI_Mode_Slave) || (TxXferCount == 0x01U)) + { + SPI_I2S_ReceiveData(SpiInstance); + SpiInstance->DR = *((uint16_t *)pTxData); + + pTxData += sizeof(uint16_t); + TxXferCount--; + } + while ((TxXferCount > 0U) || (RxXferCount > 0U)) + { + /* Check TXE flag */ + if(txallowed && (TxXferCount > 0U) && (SPI_I2S_GetFlagStatus(SpiInstance, SPI_I2S_FLAG_TXE) == SET)) + { + SPI_I2S_ReceiveData(SpiInstance); + SpiInstance->DR = *((uint16_t *)pTxData); + pTxData += sizeof(uint16_t); + TxXferCount--; + /* Next Data is a reception (Rx). Tx not allowed */ + txallowed = 0U; + } + + /* Check RXNE flag */ + if((RxXferCount > 0U) && (SPI_I2S_GetFlagStatus(SpiInstance, SPI_I2S_FLAG_RXNE) == SET)) + { + *((uint16_t *)pRxData) = SpiInstance->DR; + pRxData += sizeof(uint16_t); + RxXferCount--; + /* Next Data is a Transmission (Tx). Tx is allowed */ + txallowed = 1U; + } + if((Timeout != 0xFFFFFFFFU) && ((CurrentTicksGain() * 1000 / TICK_PER_SECOND-tickstart) >= Timeout)) + { + errorcode = 3; + goto error; + } + } + } + /* Transmit and Receive data in 8 Bit mode */ + else + { + if((SpiInit.SPI_Mode == SPI_Mode_Slave) || (TxXferCount == 0x01U)) + { + SPI_I2S_ReceiveData(SpiInstance); + *((__IO uint8_t*)&SpiInstance->DR) = (*pTxData); + + pTxData += sizeof(uint8_t); + TxXferCount--; + } + while((TxXferCount > 0U) || (RxXferCount > 0U)) + { + /* Wait for the send buffer to be empty, TXE event */ + if (txallowed && (TxXferCount > 0U) && (SPI_I2S_GetFlagStatus(SpiInstance, SPI_I2S_FLAG_TXE) == SET)) + { + /* Write to the data register and write the data to be written into the transmit buffer */ + SPI_I2S_ReceiveData(SpiInstance); + *((__IO uint8_t*)&SpiInstance->DR) = (*pTxData); + + pTxData += sizeof(uint8_t); + TxXferCount--; + txallowed = 0U; + } + + if ((RxXferCount > 0U) && SPI_I2S_GetFlagStatus(SpiInstance, SPI_I2S_FLAG_RXNE) == SET) + { + *(uint8_t *)pRxData = SpiInstance->DR; + + pRxData += sizeof(uint8_t); + RxXferCount--; + txallowed = 1U; + } + if((Timeout != 0xFFFFFFFFU) && ((CurrentTicksGain() * 1000 / TICK_PER_SECOND-tickstart) >= Timeout)) + { + errorcode = 3; + goto error; + } + } + } + + /* Wait until TXE flag */ + if(SpiWaitUntilTimeout(SpiInit, SpiInstance, SPI_FLAG_TXE, SET, Timeout, tickstart) != 0) + { + errorcode = 3; + goto error; + } + + /* Check Busy flag */ + if(SpiWaitUntilTimeout(SpiInit, SpiInstance, SPI_FLAG_BSY, RESET, Timeout, tickstart) != 0) + { + errorcode = 1; + goto error; + } + +error : + return errorcode; +} + +/** + * This function SPI receive data + * @param SpiInit SPI Init structure + * @param SpiInstance SPI control handle + * @param pData data buffer address + * @param Size Amount of data + * @param Timeout waiting time + * @return if successful return EOK + */ +int SpiReceive(SPI_InitTypeDef SpiInit, SPI_TypeDef *SpiInstance, uint8_t *pData, uint16_t Size, uint32_t Timeout) +{ + uint32_t tickstart = 0U; + int errorcode = 0; + __IO uint16_t RxXferCount; + __IO uint32_t SPITimeout; + + if((SpiInit.SPI_Mode == SPI_Mode_Master) && (SpiInit.SPI_Direction == SPI_Direction_2Lines_FullDuplex)) + { + /* Call transmit-receive function to send Dummy data on Tx line and generate clock on CLK line */ + return SpiTransmitreceive(SpiInit, SpiInstance,pData,pData,Size,Timeout); + } + + /* Init tickstart for timeout management*/ + tickstart = CurrentTicksGain() * 1000 / TICK_PER_SECOND; + + if((pData == NONE ) || (Size == 0)) + { + errorcode = 1; + goto error; + } + + RxXferCount = Size; + + /* Configure communication direction: 1Line */ + if(SpiInit.SPI_Direction == SPI_Direction_1Line_Rx) + { + SpiInstance->CR1 &= (~SPI_CR1_BIDIOE); + } + + /* Check if the SPI is already enabled */ + if((SpiInstance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE) + { + /* Enable SPI peripheral */ + SpiInstance->CR1 |= SPI_CR1_SPE; + } + + /* Receive data in 8 Bit mode */ + if(SpiInit.SPI_DataSize == SPI_DataSize_8b) + { + /* Transfer loop */ + while(RxXferCount > 0U) + { + SPITimeout = 0x1000; + + /* Wait for the send buffer to be empty, TXE event*/ + while (SPI_I2S_GetFlagStatus(SpiInstance, SPI_I2S_FLAG_RXNE) == RESET) + { + if((SPITimeout--) == 0) + { + KPrintf("spi time out\n"); + errorcode = 3; + goto error; + } + } + + *(uint8_t *)pData = SpiInstance->DR; + + pData += sizeof(uint8_t); + RxXferCount--; + } + } + else + { + /* Transfer loop */ + while(RxXferCount > 0U) + { + SPITimeout = 0x1000; + /* Check the RXNE flag */ + while (SPI_I2S_GetFlagStatus(SpiInstance, SPI_I2S_FLAG_RXNE) == RESET) + { + if((SPITimeout--) == 0) + { + KPrintf("spi time out\n"); + errorcode = 3; + goto error; + } + } + *((uint16_t*)pData) = SpiInstance->DR; + pData += sizeof(uint16_t); + RxXferCount--; + } + } + + /* Check the end of the transaction */ + if((SpiInit.SPI_Mode == SPI_Mode_Master)&&((SpiInit.SPI_Direction == SPI_Direction_1Line_Rx)||(SpiInit.SPI_Direction == SPI_Direction_2Lines_RxOnly))) + { + /* Disable SPI peripheral */ + SpiInstance->CR1 &= (~SPI_CR1_SPE); + } + +error : + return errorcode; +} + +/** + * This function SPI write data + * @param spi_dev SPI device structure handle + * @param spi_datacfg SPI device information structure handle + * @return datacfg length + */ +static uint32 Stm32SpiWriteData(struct SpiHardwareDevice *spi_dev, struct SpiDataStandard *spi_datacfg) +{ + int state = 0; + x_size_t message_length, already_send_length; + uint16 send_length; + const uint8 *WriteBuf; + + NULL_PARAM_CHECK(spi_dev); + NULL_PARAM_CHECK(spi_datacfg); + + struct Stm32Spi *StmSpi = CONTAINER_OF(spi_dev->haldev.owner_bus, struct Stm32Spi, spi_bus); + SPI_TypeDef *SpiInstance = StmSpi->instance; + SPI_InitTypeDef *SpiInit = &StmSpi->init; + struct Stm32HwSpiCs *cs = (struct Stm32HwSpiCs *)spi_dev->private_data; + + while (NONE != spi_datacfg) { + if (spi_datacfg->spi_chip_select) { + GPIO_WriteBit(cs->GPIOx, cs->GPIO_Pin, Bit_RESET); + } + + message_length = spi_datacfg->length; + WriteBuf = spi_datacfg->tx_buff; + while (message_length) { + if (message_length > 65535) { + send_length = 65535; + message_length = message_length - 65535; + } else { + send_length = message_length; + message_length = 0; + } + + /* calculate the start address */ + already_send_length = spi_datacfg->length - send_length - message_length; + WriteBuf = (uint8 *)spi_datacfg->tx_buff + already_send_length; + + /* start once data exchange in DMA mode */ + if (spi_datacfg->tx_buff) { + if (StmSpi->spi_dma_flag & SPI_USING_TX_DMA_FLAG) { + state = SpiTransmitDma(*SpiInit, SpiInstance, StmSpi->dma.dma_tx.init, StmSpi->dma.dma_tx.instance, (uint8_t *)WriteBuf, send_length); + } else { + state = SpiTransmit(*SpiInit, SpiInstance, (uint8_t *)WriteBuf, send_length, 1000); + } + } + + if (state != 0) { + KPrintf("spi write error : %d\n", state); + spi_datacfg->length = 0; + } + } + + if (spi_datacfg->spi_cs_release) { + GPIO_WriteBit(cs->GPIOx, cs->GPIO_Pin, Bit_SET); + } + + spi_datacfg = spi_datacfg->next; + } + + return EOK; +} + +/** + * This function SPI read data + * @param spi_dev SPI device structure handle + * @param spi_datacfg SPI device information structure handle + * @return datacfg length + */ +static uint32 Stm32SpiReadData(struct SpiHardwareDevice *spi_dev, struct SpiDataStandard *spi_datacfg) +{ + NULL_PARAM_CHECK(spi_dev); + NULL_PARAM_CHECK(spi_datacfg); + + int state; + x_size_t message_length, already_send_length; + uint16 read_length, spi_read_length = 0; + uint8 *ReadBuf; + + struct Stm32Spi *StmSpi = CONTAINER_OF(spi_dev->haldev.owner_bus, struct Stm32Spi, spi_bus); + SPI_TypeDef *SpiInstance = StmSpi->instance; + SPI_InitTypeDef *SpiInit = &StmSpi->init; + struct Stm32HwSpiCs *cs = (struct Stm32HwSpiCs *)spi_dev->private_data; + + while(NONE != spi_datacfg) { + if (spi_datacfg->spi_chip_select) { + GPIO_WriteBit(cs->GPIOx, cs->GPIO_Pin, Bit_RESET); + } + + message_length = spi_datacfg->length; + ReadBuf = spi_datacfg->rx_buff; + while (message_length) { + if (message_length > 65535){ + read_length = 65535; + message_length = message_length - 65535; + } else { + read_length = message_length; + message_length = 0; + } + + /* calculate the start address */ + already_send_length = spi_datacfg->length - read_length - message_length; + ReadBuf = spi_datacfg->rx_buff + already_send_length; + /* start once data exchange in DMA mode */ + if ((spi_datacfg->rx_buff) && (ReadBuf)) { + //memset(ReadBuf, 0, read_length); + if (StmSpi->spi_dma_flag & SPI_USING_RX_DMA_FLAG) { + state = SpiReceiveDma(*SpiInit, SpiInstance, StmSpi->dma.dma_rx.init, StmSpi->dma.dma_rx.instance, StmSpi->dma.dma_tx.init, StmSpi->dma.dma_tx.instance, (uint8_t *)ReadBuf, read_length); + } else { + state = SpiReceive(*SpiInit, SpiInstance, ReadBuf, read_length, 1000); + } + } + + if (state != 0) { + KPrintf("spi read error : %d\n", state); + spi_datacfg->length = 0; + } + } + + if (spi_datacfg->spi_cs_release) { + GPIO_WriteBit(cs->GPIOx, cs->GPIO_Pin, Bit_SET); + } + + spi_read_length += spi_datacfg->length; + spi_datacfg = spi_datacfg->next; + } + + return spi_read_length; +} + +/** + * This function SPI driver initialization function + * @param spi_drv SPI driver structure handle + * @return if successful return EOK + */ +static uint32 SpiDrvInit(struct SpiDriver *spi_drv) +{ + NULL_PARAM_CHECK(spi_drv); + + SpiDeviceParam *dev_param = (SpiDeviceParam *)(spi_drv->driver.private_data); + + struct Stm32Spi *StmSpi = CONTAINER_OF(spi_drv->driver.owner_bus, struct Stm32Spi, spi_bus); + + return Stm32SpiInit(StmSpi, dev_param->spi_master_param); +} + +/** + * This function SPI driver configuration param + * @param spi_drv SPI driver structure handle + * @param spi_param SPI master param structure handle + * @return if successful return EOK + */ +static uint32 SpiDrvConfigure(struct SpiDriver *spi_drv, struct SpiMasterParam *spi_param) +{ + NULL_PARAM_CHECK(spi_drv); + NULL_PARAM_CHECK(spi_param); + + SpiDeviceParam *dev_param = (SpiDeviceParam *)(spi_drv->driver.private_data); + + dev_param->spi_master_param = spi_param; + dev_param->spi_master_param->spi_work_mode = dev_param->spi_master_param->spi_work_mode & SPI_MODE_MASK; + + return EOK; +} + +/*Configure the spi device param, make sure struct (configure_info->private_data) = (SpiMasterParam)*/ +static uint32 Stm32SpiDrvConfigure(void *drv, struct BusConfigureInfo *configure_info) +{ + NULL_PARAM_CHECK(drv); + NULL_PARAM_CHECK(configure_info); + + x_err_t ret = EOK; + struct SpiDriver *spi_drv = (struct SpiDriver *)drv; + struct SpiMasterParam *spi_param; + + switch (configure_info->configure_cmd) + { + case OPE_INT: + ret = SpiDrvInit(spi_drv); + break; + case OPE_CFG: + spi_param = (struct SpiMasterParam *)configure_info->private_data; + ret = SpiDrvConfigure(spi_drv, spi_param); + break; + default: + break; + } + + return ret; +} + +/*manage the spi device operations*/ +static const struct SpiDevDone spi_dev_done = +{ + .dev_open = NONE, + .dev_close = NONE, + .dev_write = Stm32SpiWriteData, + .dev_read = Stm32SpiReadData, +}; + +#if defined(BSP_USING_SPI1) +static struct Stm32Spi spi1; +#if defined(BSP_SPI1_TX_USING_DMA) +void DMA2_Stream3_IRQHandler(int irq_num, void *arg) +{ + DmaTxDoneIsr(&spi1.spi_bus); +} +DECLARE_HW_IRQ(DMA2_Stream3_IRQn, DMA2_Stream3_IRQHandler, NONE); +#endif + +#if defined(BSP_SPI1_RX_USING_DMA) +void DMA2_Stream0_IRQHandler(int irq_num, void *arg) +{ + DmaRxDoneIsr(&spi1.spi_bus); +} +DECLARE_HW_IRQ(DMA2_Stream0_IRQn, DMA2_Stream0_IRQHandler, NONE); +#endif +#endif + +#if defined(BSP_USING_SPI2) +static struct Stm32Spi spi2; +#if defined(BSP_SPI2_TX_USING_DMA) +void DMA1_Stream4_IRQHandler(int irq_num, void *arg) +{ + DmaTxDoneIsr(&spi2.spi_bus); +} +DECLARE_HW_IRQ(DMA1_Stream4_IRQn, DMA1_Stream4_IRQHandler, NONE); +#endif + +#if defined(BSP_SPI2_RX_USING_DMA) +void DMA1_Stream3_IRQHandler(int irq_num, void *arg) +{ + DmaTxDoneIsr(&spi2.spi_bus); +} +DECLARE_HW_IRQ(DMA1_Stream3_IRQn, DMA1_Stream3_IRQHandler, NONE); +#endif +#endif + +#if defined(BSP_USING_SPI3) +static struct Stm32Spi spi3; +#if defined(BSP_SPI3_TX_USING_DMA) +void DMA1_Stream7_IRQHandler(int irq_num, void *arg) +{ + DmaTxDoneIsr(&spi3.spi_bus); +} +DECLARE_HW_IRQ(DMA1_Stream7_IRQn, DMA1_Stream7_IRQHandler, NONE); +#endif + +#if defined(BSP_SPI3_RX_USING_DMA) +/** + * This function DMA2 Stream2 Interrupt service function + * + * @return none + */ +void DMA1_Stream2_IRQHandler(int irq_num, void *arg) +{ + DmaRxDoneIsr(&spi3.spi_bus); +} +DECLARE_HW_IRQ(DMA1_Stream2_IRQn, DMA1_Stream2_IRQHandler, NONE); +#endif +#endif + +/** + * This function RCC clock configuration function + * @return none + */ +static void RCCConfiguration(void) +{ +#ifdef BSP_USING_SPI1 + RCC_AHB1PeriphClockCmd(SPI1_GPIO_RCC, ENABLE); + + RCC_APB2PeriphClockCmd(RCC_APBPeriph_SPI1, ENABLE); +#endif + +#ifdef BSP_USING_SPI2 + RCC_AHB1PeriphClockCmd(SPI2_GPIO_RCC | SPI2_GPIO_RCC_SCK, ENABLE); + + RCC_APB1PeriphClockCmd(RCC_APBPeriph_SPI2, ENABLE); +#endif + +#ifdef BSP_USING_SPI3 + RCC_AHB1PeriphClockCmd(SPI3_GPIO_RCC | SPI3_GPIO_RCC_NSS, ENABLE); + + RCC_APB2PeriphClockCmd(RCC_APBPeriph_SPI3, ENABLE); +#endif +} +/** + * This function GPIO Configuration function + * @return none + */ +static void GPIOConfiguration(void) +{ + GPIO_InitTypeDef gpio_initstructure; + + gpio_initstructure.GPIO_Mode = GPIO_Mode_AF; /* Reuse function */ + gpio_initstructure.GPIO_OType = GPIO_OType_PP; /* Multiplex push-pull*/ + gpio_initstructure.GPIO_PuPd = GPIO_PuPd_UP; /* pull up */ + gpio_initstructure.GPIO_Speed = GPIO_Speed_2MHz; /* Level reversal speed */ + +#ifdef BSP_USING_SPI1 + gpio_initstructure.GPIO_Pin = SPI1_GPIO_NSS | SPI1_GPIO_SCK | SPI1_GPIO_MISO | SPI1_GPIO_MOSI; + /* Connect alternate function */ + GPIO_PinAFConfig(SPI1_GPIO, SPI1_NSS_PIN_SOURCE, GPIO_AF_SPI1); + GPIO_PinAFConfig(SPI1_GPIO, SPI1_SCK_PIN_SOURCE, GPIO_AF_SPI1); + GPIO_PinAFConfig(SPI1_GPIO, SPI1_MISO_PIN_SOURCE, GPIO_AF_SPI1); + GPIO_PinAFConfig(SPI1_GPIO, SPI1_MOSI_PIN_SOURCE, GPIO_AF_SPI1); + + GPIO_Init(SPI1_GPIO, &gpio_initstructure); /*SPI pin initialization*/ +#endif + +#ifdef BSP_USING_SPI2 + gpio_initstructure.GPIO_Pin = SPI2_GPIO_SCK; + /* Connect alternate function */ + GPIO_PinAFConfig(SPI2_SCK, SPI2_SCK_PIN_SOURCE, GPIO_AF_SPI2); + + GPIO_Init(SPI2_SCK, &gpio_initstructure); + + gpio_initstructure.GPIO_Pin = SPI2_GPIO_NSS | SPI2_GPIO_MISO | SPI2_GPIO_MOSI; + /* Connect alternate function */ + GPIO_PinAFConfig(SPI2_GPIO, SPI2_NSS_PIN_SOURCE, GPIO_AF_SPI2); + GPIO_PinAFConfig(SPI2_GPIO, SPI2_MISO_PIN_SOURCE, GPIO_AF_SPI2); + GPIO_PinAFConfig(SPI2_GPIO, SPI2_MOSI_PIN_SOURCE, GPIO_AF_SPI2); + + GPIO_Init(SPI2_GPIO, &gpio_initstructure); +#endif + +#ifdef BSP_USING_SPI3 + gpio_initstructure.GPIO_Pin = SPI3_GPIO_NSS; + /* Connect alternate function */ + GPIO_PinAFConfig(SPI3_NSS, SPI3_NSS_PIN_SOURCE, GPIO_AF_SPI3); + + GPIO_Init(SPI3_NSS, &gpio_initstructure); + + gpio_initstructure.GPIO_Pin = SPI3_GPIO_SCK | SPI3_GPIO_MISO | SPI3_GPIO_MOSI; + GPIO_PinAFConfig(SPI3_GPIO, SPI3_SCK_PIN_SOURCE, GPIO_AF_SPI3); + GPIO_PinAFConfig(SPI3_GPIO, SPI3_MISO_PIN_SOURCE, GPIO_AF_SPI3); + GPIO_PinAFConfig(SPI3_GPIO, SPI3_MOSI_PIN_SOURCE, GPIO_AF_SPI3); + + GPIO_Init(SPI3_GPIO, &gpio_initstructure); +#endif +} + +/** + * This function Init the spi bus 、spi driver and attach to the bus + * @param spi_bus Spi bus info pointer + * @param spi_driver Spi driver info pointer + * @return EOK + */ +static int BoardSpiBusInit(struct Stm32Spi *stm32spi_bus, struct SpiDriver *spi_driver, char* drv_name) +{ + x_err_t ret = EOK; + + /*Init the spi bus */ + ret = SpiBusInit(&stm32spi_bus->spi_bus, stm32spi_bus->bus_name); + if (EOK != ret) { + KPrintf("Board_Spi_init SpiBusInit error %d\n", ret); + return ERROR; + } + + /*Init the spi driver*/ + ret = SpiDriverInit(spi_driver, drv_name); + if (EOK != ret) { + KPrintf("Board_Spi_init SpiDriverInit error %d\n", ret); + return ERROR; + } + + /*Attach the spi driver to the spi bus*/ + ret = SpiDriverAttachToBus(drv_name, stm32spi_bus->bus_name); + if (EOK != ret) { + KPrintf("Board_Spi_init SpiDriverAttachToBus error %d\n", ret); + return ERROR; + } + + return ret; +} + +/** + * This function SPI bus initialization + * @return EOK + */ +static int Stm32HwSpiBusInit(void) +{ + x_err_t ret = EOK; + struct Stm32Spi *StmSpiBus; + + RCCConfiguration(); + GPIOConfiguration(); + +#ifdef BSP_USING_SPI1 + memset(&spi1, 0, sizeof(struct Stm32Spi)); + StmSpiBus = &spi1; + StmSpiBus->instance = SPI1; + StmSpiBus->bus_name = SPI_BUS_NAME_1; + StmSpiBus->spi_bus.private_data = &spi1; + DmaSpiConfig(&StmSpiBus->spi_bus, 0, NONE, NONE); + + static struct SpiDriver spi_driver_1; + memset(&spi_driver_1, 0, sizeof(struct SpiDriver)); + + spi_driver_1.configure = &(Stm32SpiDrvConfigure); + + ret = BoardSpiBusInit(StmSpiBus, &spi_driver_1, SPI_1_DRV_NAME); + if (EOK != ret) { + KPrintf("Board_Spi_Init spi_bus_init %s error ret %u\n", StmSpiBus->bus_name, ret); + return ERROR; + } +#endif + +#ifdef BSP_USING_SPI2 + memset(&spi2, 0, sizeof(struct Stm32Spi)); + StmSpiBus = &spi2; + StmSpiBus->instance = SPI2; + StmSpiBus->bus_name = SPI_BUS_NAME_2; + StmSpiBus->spi_bus.private_data = &spi2; + DmaSpiConfig(&StmSpiBus->spi_bus, 0, NONE, NONE); + + static struct SpiDriver spi_driver_2; + memset(&spi_driver_2, 0, sizeof(struct SpiDriver)); + + spi_driver_2.configure = &(Stm32SpiDrvConfigure); + + ret = BoardSpiBusInit(StmSpiBus, &spi_driver_2, SPI_2_DRV_NAME); + if (EOK != ret) { + return ERROR; + } +#endif + +#ifdef BSP_USING_SPI3 + memset(&spi3, 0, sizeof(struct Stm32Spi)); + StmSpiBus = &spi3; + StmSpiBus->instance = SPI3; + StmSpiBus->bus_name = SPI_BUS_NAME_3; + StmSpiBus->spi_bus.private_data = &spi3; + DmaSpiConfig(&StmSpiBus->spi_bus, 0, NONE, NONE); + + static struct SpiDriver spi_driver_3; + memset(&spi_driver_3, 0, sizeof(struct SpiDriver)); + + spi_driver_3.configure = &(Stm32SpiDrvConfigure); + + ret = BoardSpiBusInit(StmSpiBus, &spi_driver_3, SPI_3_DRV_NAME); + if (EOK != ret) { + KPrintf("Board_Spi_Init spi_bus_init %s error ret %u\n", StmSpiBus->bus_name, ret); + return ERROR; + } +#endif + return EOK; +} + +/** + * This function Mount the spi device to the bus + * @param bus_name Bus Name + * @param device_name spi device name + * @param cs_gpiox GPIO pin configuration handle + * @param cs_gpio_pin GPIO number + * @return EOK + */ +x_err_t HwSpiDeviceAttach(const char *bus_name, const char *device_name, GPIO_TypeDef *cs_gpiox, uint16_t cs_gpio_pin) +{ + NULL_PARAM_CHECK(bus_name); + NULL_PARAM_CHECK(device_name); + + x_err_t result; + struct SpiHardwareDevice *spi_device; + struct Stm32HwSpiCs *cs_pin_param; + static SpiDeviceParam spi_dev_param; + memset(&spi_dev_param, 0, sizeof(SpiDeviceParam)); + + /* initialize the cs pin && select the slave*/ + GPIO_InitTypeDef GPIO_Initure; + GPIO_Initure.GPIO_Pin = cs_gpio_pin; + GPIO_Initure.GPIO_Mode = GPIO_Mode_OUT; + GPIO_Initure.GPIO_PuPd = GPIO_PuPd_UP; + GPIO_Initure.GPIO_Speed = GPIO_Speed_50MHz; + GPIO_Init(cs_gpiox, &GPIO_Initure); + GPIO_WriteBit(cs_gpiox, cs_gpio_pin, Bit_SET); + + /* attach the device to spi bus*/ + spi_device = (struct SpiHardwareDevice *)x_malloc(sizeof(struct SpiHardwareDevice)); + CHECK(spi_device); + memset(spi_device, 0, sizeof(struct SpiHardwareDevice)); + cs_pin_param = (struct Stm32HwSpiCs *)x_malloc(sizeof(struct Stm32HwSpiCs)); + CHECK(cs_pin_param); + memset(cs_pin_param, 0, sizeof(struct Stm32HwSpiCs)); + cs_pin_param->GPIOx = cs_gpiox; + cs_pin_param->GPIO_Pin = cs_gpio_pin; + + spi_device->spi_dev_done = &spi_dev_done; + spi_device->private_data = (void *)cs_pin_param; + + result = SpiDeviceRegister(spi_device, (void *)&spi_dev_param, device_name); + if (result != EOK) { + SYS_ERR("%s device %p register faild, %d\n", device_name, spi_device, result); + } + + result = SpiDeviceAttachToBus(device_name, bus_name); + if (result != EOK) { + SYS_ERR("%s attach to %s faild, %d\n", device_name, bus_name, result); + } + + CHECK(result == EOK); + + KPrintf("%s attach to %s done\n", device_name, bus_name); + + return result; +} + +/** + * This function Get DMA information + * @return none + */ +static void Stm32GetDmaInfo(void) +{ +#ifdef BSP_SPI1_RX_USING_DMA /*SPI1 uses DMA receive enable*/ + spi1.spi_dma_flag |= SPI_USING_RX_DMA_FLAG; + spi1.dma.dma_rx.instance = DMA2_Stream0; + spi1.dma.dma_rx.dma_rcc = RCC_AHB1ENR_DMA2EN; + spi1.dma.dma_rx.channel = DMA_Channel_3; + spi1.dma.dma_rx.dma_irq = DMA2_Stream0_IRQn; +#endif +#ifdef BSP_SPI1_TX_USING_DMA /*SPI1 uses DMA send enable*/ + spi1.spi_dma_flag |= SPI_USING_TX_DMA_FLAG; + spi1.dma.dma_tx.instance = DMA2_Stream3; + spi1.dma.dma_tx.dma_rcc = RCC_AHB1ENR_DMA2EN; + spi1.dma.dma_tx.channel = DMA_Channel_3; + spi1.dma.dma_tx.dma_irq = DMA2_Stream3_IRQn; +#endif + +#ifdef BSP_SPI2_RX_USING_DMA /*SPI2 uses DMA receive enable*/ + spi2.spi_dma_flag |= SPI_USING_RX_DMA_FLAG; + spi2.dma.dma_rx.instance = DMA1_Stream3; /* DMA1 Data stream 3*/ + spi2.dma.dma_rx.dma_rcc = RCC_AHB1ENR_DMA1EN; + spi2.dma.dma_rx.channel = DMA_Channel_0; + spi2.dma.dma_rx.dma_irq = DMA1_Stream3_IRQn; +#endif +#ifdef BSP_SPI2_TX_USING_DMA /*SPI2 uses DMA send enable*/ + spi2.spi_dma_flag |= SPI_USING_TX_DMA_FLAG; + spi2.dma.dma_tx.instance = DMA1_Stream4; /* DMA1 Data stream 4*/ + spi2.dma.dma_tx.dma_rcc = RCC_AHB1ENR_DMA1EN; + spi2.dma.dma_tx.channel = DMA_Channel_0; + spi2.dma.dma_tx.dma_irq = DMA1_Stream4_IRQn; /*Enable DMA interrupt line*/ +#endif + +#ifdef BSP_SPI3_RX_USING_DMA /*SPI3 uses DMA receive enable*/ + spi3.spi_dma_flag |= SPI_USING_RX_DMA_FLAG; + spi3.dma.dma_rx.instance = DMA1_Stream2; /* DMA1 Data stream 2*/ + spi3.dma.dma_rx.dma_rcc = RCC_AHB1ENR_DMA1EN; + spi3.dma.dma_rx.channel = DMA_Channel_0; + spi3.dma.dma_rx.dma_irq = DMA1_Stream2_IRQn; /*Enable DMA interrupt line*/ +#endif +#ifdef BSP_SPI3_TX_USING_DMA /*SPI3 uses DMA send enable*/ + spi3.spi_dma_flag |= SPI_USING_TX_DMA_FLAG; + spi3.dma.dma_tx.instance = DMA1_Stream7; /* DMA1 Data stream 7*/ + spi3.dma.dma_tx.dma_rcc = RCC_AHB1ENR_DMA1EN; + spi3.dma.dma_tx.channel = DMA_Channel_0; + spi3.dma.dma_tx.dma_irq = DMA1_Stream7_IRQn; /*Enable DMA interrupt line*/ +#endif +} + +/** + * This function hardware spi initialization + * @return EOK + */ +int Stm32HwSpiInit(void) +{ + Stm32GetDmaInfo(); + return Stm32HwSpiBusInit(); +} diff --git a/Ubiquitous/XiZi/board/aiit-arm32-board/third_party_driver/timer/Kconfig b/Ubiquitous/XiZi/board/aiit-arm32-board/third_party_driver/timer/Kconfig new file mode 100644 index 0000000..33f325e --- /dev/null +++ b/Ubiquitous/XiZi/board/aiit-arm32-board/third_party_driver/timer/Kconfig @@ -0,0 +1,19 @@ +if BSP_USING_HWTIMER + config HWTIMER_BUS_NAME_2 + string "hwtimer bus name" + default "hwtim2" + + menuconfig ENABLE_TIM2 + bool "enable TIM2" + default y + + if ENABLE_TIM2 + config HWTIMER_2_DEVICE_NAME_2 + string "TIM2 dev name" + default "hwtim2_dev2" + + config HWTIMER_DRIVER_NAME_2 + string "TIM2 drv name" + default "hwtim2_drv" + endif +endif diff --git a/Ubiquitous/XiZi/board/aiit-arm32-board/third_party_driver/timer/Makefile b/Ubiquitous/XiZi/board/aiit-arm32-board/third_party_driver/timer/Makefile new file mode 100644 index 0000000..344a8d9 --- /dev/null +++ b/Ubiquitous/XiZi/board/aiit-arm32-board/third_party_driver/timer/Makefile @@ -0,0 +1,3 @@ +SRC_FILES := connect_hwtimer.c hardware_tim.c + +include $(KERNEL_ROOT)/compiler.mk diff --git a/Ubiquitous/XiZi/board/aiit-arm32-board/third_party_driver/timer/connect_hwtimer.c b/Ubiquitous/XiZi/board/aiit-arm32-board/third_party_driver/timer/connect_hwtimer.c new file mode 100644 index 0000000..621e4b2 --- /dev/null +++ b/Ubiquitous/XiZi/board/aiit-arm32-board/third_party_driver/timer/connect_hwtimer.c @@ -0,0 +1,185 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2018-12-10 zylx first version + * 2020-06-16 thread-liu Porting for stm32mp1 + * 2020-08-25 linyongkang Fix the timer clock frequency doubling problem + * 2020-10-14 Dozingfiretruck Porting for stm32wbxx + */ + +/** +* @file connect_hwtimer.c +* @brief support aiit-arm32-board hwtimer function and register to bus framework +* @version 1.0 +* @author AIIT XUOS Lab +* @date 2021-04-25 +*/ + +/************************************************* +File name: connect_hwtimer.c +Description: support aiit-arm32-board hwtimer configure and spi bus register function +Others: take RT-Thread v4.0.2/bsp/stm32/libraries/HAL_Drivers/drv_hwtimer.c for references + https://github.com/RT-Thread/rt-thread/tree/v4.0.2 +History: +1. Date: 2021-04-25 +Author: AIIT XUOS Lab +Modification: +1. support aiit-arm32-board hwtimer configure +2. support aiit-arm32-board hwtimer bus device and driver register +*************************************************/ + +#include +#include +#include +#include +#include + +static struct HwtimerCallBackInfo *ptim2_cb_info = NULL; + +#ifdef ENABLE_TIM2 +void TIM2_IRQHandler(int irq_num, void *arg) +{ + TIM_ClearITPendingBit(TIM2, TIM_IT_Update); + KPrintf("hwtimer 2 ... come ...\n"); + + if (ptim2_cb_info) { + if (ptim2_cb_info->timeout_callback){ + ptim2_cb_info->timeout_callback(ptim2_cb_info->param); + } + } +} +DECLARE_HW_IRQ(TIM2_IRQn, TIM2_IRQHandler, NONE); +#endif + +uint32 HwtimerOpen(void *dev) +{ + struct HwtimerHardwareDevice *hwtimer_dev = dev; + + RCC_APB1PeriphClockCmd(RCC_APB1Periph_TIM2, ENABLE); + + TIM_DeInit(TIM2); + + TIM_TimeBaseInitTypeDef timer_def; + timer_def.TIM_Period = (hwtimer_dev->hwtimer_param.period_millisecond) * 10 - 1; + timer_def.TIM_Prescaler = 8400 - 1; + timer_def.TIM_CounterMode = TIM_CounterMode_Up; + timer_def.TIM_ClockDivision = TIM_CKD_DIV1; + timer_def.TIM_RepetitionCounter = 0; + TIM_TimeBaseInit(TIM2, &timer_def); + + NVIC_InitTypeDef NVIC_InitStructure; + NVIC_InitStructure.NVIC_IRQChannel = TIM2_IRQn; + NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 0x01; + NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0x01; + NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE; + NVIC_Init(&NVIC_InitStructure); + + ptim2_cb_info = &hwtimer_dev->hwtimer_param.cb_info; + + TIM_ITConfig(TIM2, TIM_IT_Update, ENABLE); + + TIM_Cmd(TIM2, ENABLE); + return EOK; +} + +uint32 HwtimerClose(void *dev) +{ + TIM_Cmd(TIM2, DISABLE); + return EOK; +} + +/*manage the hwtimer device operations*/ +static const struct HwtimerDevDone dev_done = +{ + .open = HwtimerOpen, + .close = HwtimerClose, + .write = NONE, + .read = NONE, +}; + +/*Init hwtimer bus*/ +static int BoardHwtimerBusInit(struct HwtimerBus *hwtimer_bus, struct HwtimerDriver *hwtimer_driver) +{ + x_err_t ret = EOK; + + /*Init the hwtimer bus */ + ret = HwtimerBusInit(hwtimer_bus, HWTIMER_BUS_NAME_2); + if (EOK != ret) { + KPrintf("board_hwtimer_init HwtimerBusInit error %d\n", ret); + return ERROR; + } + + #ifdef ENABLE_TIM2 + /*Init the hwtimer driver*/ + hwtimer_driver->configure = NONE; + ret = HwtimerDriverInit(hwtimer_driver, HWTIMER_DRIVER_NAME_2); + if (EOK != ret) { + KPrintf("board_hwtimer_init HwtimerDriverInit error %d\n", ret); + return ERROR; + } + + /*Attach the hwtimer driver to the hwtimer bus*/ + ret = HwtimerDriverAttachToBus(HWTIMER_DRIVER_NAME_2, HWTIMER_BUS_NAME_2); + if (EOK != ret) { + KPrintf("board_hwtimer_init USEDriverAttachToBus error %d\n", ret); + return ERROR; + } + #endif + + return ret; +} + +/*Attach the hwtimer device to the hwtimer bus*/ +static int BoardHwtimerDevBend(void) +{ + #ifdef ENABLE_TIM2 + x_err_t ret = EOK; + static struct HwtimerHardwareDevice hwtimer_device_2; + memset(&hwtimer_device_2, 0, sizeof(struct HwtimerHardwareDevice)); + + hwtimer_device_2.dev_done = &dev_done; + + ret = HwtimerDeviceRegister(&hwtimer_device_2, NONE, HWTIMER_2_DEVICE_NAME_2); + if (EOK != ret) { + KPrintf("board_hwtimer_init HWTIMERDeviceInit device %s error %d\n", HWTIMER_2_DEVICE_NAME_2, ret); + return ERROR; + } + + ret = HwtimerDeviceAttachToBus(HWTIMER_2_DEVICE_NAME_2, HWTIMER_BUS_NAME_2); + if (EOK != ret) { + KPrintf("board_hwtimer_init HwtimerDeviceAttachToBus device %s error %d\n", HWTIMER_2_DEVICE_NAME_2, ret); + return ERROR; + } + + return ret; + #endif +} + +/*ARM-32 BOARD HWTIMER INIT*/ +int Stm32HwTimerInit(void) +{ + x_err_t ret = EOK; + static struct HwtimerBus hwtimer_bus; + memset(&hwtimer_bus, 0, sizeof(struct HwtimerBus)); + + static struct HwtimerDriver hwtimer_driver; + memset(&hwtimer_driver, 0, sizeof(struct HwtimerDriver)); + + ret = BoardHwtimerBusInit(&hwtimer_bus, &hwtimer_driver); + if (EOK != ret) { + KPrintf("board_hwtimer_Init error ret %u\n", ret); + return ERROR; + } + + ret = BoardHwtimerDevBend(); + if (EOK != ret) { + KPrintf("board_hwtimer_Init error ret %u\n", ret); + return ERROR; + } + + return ret; +} diff --git a/Ubiquitous/XiZi/board/aiit-arm32-board/third_party_driver/touch/Kconfig b/Ubiquitous/XiZi/board/aiit-arm32-board/third_party_driver/touch/Kconfig new file mode 100644 index 0000000..8e5193d --- /dev/null +++ b/Ubiquitous/XiZi/board/aiit-arm32-board/third_party_driver/touch/Kconfig @@ -0,0 +1,9 @@ +config TOUCH_BUS_NAME_1 + string "touch bus 1 name" + default "touch1" +config TOUCH_DRV_NAME_1 + string "touch bus 1 driver name" + default "touch1drv" +config TOUCH_1_DEVICE_NAME_0 + string "touch bus 1 device 0 name" + default "touch10" \ No newline at end of file diff --git a/Ubiquitous/XiZi/board/aiit-arm32-board/third_party_driver/touch/Makefile b/Ubiquitous/XiZi/board/aiit-arm32-board/third_party_driver/touch/Makefile new file mode 100644 index 0000000..63a85b4 --- /dev/null +++ b/Ubiquitous/XiZi/board/aiit-arm32-board/third_party_driver/touch/Makefile @@ -0,0 +1,3 @@ +SRC_FILES := connect_touch.c + +include $(KERNEL_ROOT)/compiler.mk \ No newline at end of file diff --git a/Ubiquitous/XiZi/board/aiit-arm32-board/third_party_driver/touch/connect_touch.c b/Ubiquitous/XiZi/board/aiit-arm32-board/third_party_driver/touch/connect_touch.c new file mode 100644 index 0000000..acd3f2f --- /dev/null +++ b/Ubiquitous/XiZi/board/aiit-arm32-board/third_party_driver/touch/connect_touch.c @@ -0,0 +1,300 @@ +/* + * Copyright (c) Guangzhou Xingyi Electronic Technology Co., Ltd + * + * Change Logs: + * Date Author Notes + * 2014-7-4 alientek first version + */ + +/** +* @file connect_touch.c +* @brief support aiit-arm32-board touch function and register to bus framework +* @version 1.0 +* @author AIIT XUOS Lab +* @date 2021-04-25 +*/ + +/************************************************* +File name: connect_touch.c +Description: support aiit-arm32-board touch configure and touch bus register function +Others: take hardware/touch/touch.c for references +History: +1. Date: 2021-04-25 +Author: AIIT XUOS Lab +Modification: +1. support aiit-arm32-board touch configure, write and read +2. support aiit-arm32-board touch bus device and driver register +*************************************************/ + +#include +#include +#include +#include +#include + +touch_device_info tp_dev = +{ + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, +}; + +unsigned char CMD_RDX=0XD0; +unsigned char CMD_RDY=0X90; + +TP_modify_save modify_save = +{ + 0,0,0,0,0,0 +}; + + static int Stm32Udelay(uint32 us) +{ + uint32 ticks; + uint32 told, tnow, tcnt = 0; + uint32 reload = SysTick->LOAD; + + ticks = us * reload / (1000000 / TICK_PER_SECOND); + told = SysTick->VAL; + while (1) { + tnow = SysTick->VAL; + if (tnow != told) { + if (tnow < told) { + tcnt += told - tnow; + } else { + tcnt += reload - tnow + told; + } + told = tnow; + if (tcnt >= ticks) { + return 0; + break; + } + } + } +} + +void TouchWriteByte(unsigned char num) +{ + u8 count=0; + for(count = 0;count < 8;count ++) { + if (num & 0x80) + T_MOSI=1; + else + T_MOSI=0; + num <<= 1; + T_CLK = 0; + Stm32Udelay(1); + T_CLK = 1; + } +} + +u16 TpReadAd(u8 cmd) +{ + u8 count = 0; + u16 Num = 0; + + T_CLK =0; + T_MOSI = 0; + TCS = 0; + + TouchWriteByte(cmd); + Stm32Udelay(6); + T_CLK = 0; + + Stm32Udelay(1); + T_CLK = 1; + + Stm32Udelay(1); + T_CLK = 0; + + for(count = 0;count < 16;count ++) { + Num <<= 1; + T_CLK = 0; + Stm32Udelay(1); + T_CLK =1; + if (T_MISO == 1) + Num++; + } + Num >>= 4; + TCS = 1; + + return(Num); +} + +#define READ_TIMES 5 +#define LOST_VAL 1 + +u16 TpReadXoy(u8 xy) +{ + u16 i, j; + u16 buf[READ_TIMES]; + u16 sum=0; + u16 temp; + for(i = 0;i < READ_TIMES;i ++) + buf[i]=TpReadAd(xy); + for(i = 0;i < READ_TIMES-1; i ++) { + for(j = i+1;j < READ_TIMES;j ++) { + if (buf[i] > buf[j]) { + temp=buf[i]; + buf[i]=buf[j]; + buf[j]=temp; + } + } + } + sum=0; + for(i = LOST_VAL;i < READ_TIMES - LOST_VAL;i ++) + sum+=buf[i]; + temp=sum/(READ_TIMES-2*LOST_VAL); + return temp; +} + +u8 TpReadXy(u16 *x, u16 *y) +{ + u16 xtemp,ytemp; + xtemp=TpReadXoy(CMD_RDX); + ytemp=TpReadXoy(CMD_RDY); + + *x=xtemp; + *y=ytemp; + return 1; +} + +static uint32 TouchRead(void *dev, struct BusBlockReadParam *read_param) +{ + uint32 ret = EOK; + NULL_PARAM_CHECK(read_param); + struct TouchDataStandard * data = ( struct TouchDataStandard*)read_param->buffer; + TpReadXy(&data->x,&data->y); + return ret; +} + +static uint32 TouchConfigure(void *drv, struct BusConfigureInfo *configure_info) +{ + GPIO_InitTypeDef gpio_initstructure; + + RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOB|RCC_AHB1Periph_GPIOG|RCC_AHB1Periph_GPIOD, ENABLE); + + gpio_initstructure.GPIO_Pin =GPIO_Pin_4; + gpio_initstructure.GPIO_Mode = GPIO_Mode_IN; + gpio_initstructure.GPIO_OType = GPIO_OType_PP; + gpio_initstructure.GPIO_Speed = GPIO_Speed_100MHz; + gpio_initstructure.GPIO_PuPd = GPIO_PuPd_UP; + GPIO_Init(GPIOB, &gpio_initstructure); + + gpio_initstructure.GPIO_Pin = GPIO_Pin_3; + gpio_initstructure.GPIO_Mode = GPIO_Mode_OUT; + GPIO_Init(GPIOB, &gpio_initstructure); + + gpio_initstructure.GPIO_Pin = GPIO_Pin_13; + gpio_initstructure.GPIO_Mode = GPIO_Mode_OUT; + GPIO_Init(GPIOG, &gpio_initstructure); + + gpio_initstructure.GPIO_Pin = GPIO_Pin_5; + gpio_initstructure.GPIO_Mode = GPIO_Mode_OUT; + GPIO_Init(GPIOB, &gpio_initstructure); + + gpio_initstructure.GPIO_Pin = GPIO_Pin_6; + gpio_initstructure.GPIO_Mode = GPIO_Mode_OUT; + GPIO_Init(GPIOD, &gpio_initstructure); + + return 0; +} + +struct TouchDevDone touch_dev_done = +{ + .open = NONE, + .close = NONE, + .write = NONE, + .read = TouchRead +}; + +struct Stm32Touch +{ + char *bus_name; + struct TouchBus touch_bus; +}; + +struct Stm32Touch touch; + +static int BoardTouchBusInit(struct Stm32Touch *stm32touch_bus, struct TouchDriver *touch_driver) +{ + x_err_t ret = EOK; + + /*Init the touch bus */ + ret = TouchBusInit(&stm32touch_bus->touch_bus, stm32touch_bus->bus_name); + if (EOK != ret) { + KPrintf("Board_touch_init touchBusInit error %d\n", ret); + return ERROR; + } + + /*Init the touch driver*/ + ret = TouchDriverInit(touch_driver, TOUCH_DRV_NAME_1); + if (EOK != ret){ + KPrintf("Board_touch_init touchDriverInit error %d\n", ret); + return ERROR; + } + + /*Attach the touch driver to the touch bus*/ + ret = TouchDriverAttachToBus(TOUCH_DRV_NAME_1, stm32touch_bus->bus_name); + if (EOK != ret){ + KPrintf("Board_touch_init TouchDriverAttachToBus error %d\n", ret); + return ERROR; + } + + return ret; +} + +/*Attach the touch device to the touch bus*/ +static int BoardTouchDevBend(void) +{ + x_err_t ret = EOK; + static struct TouchHardwareDevice touch_device; + memset(&touch_device, 0, sizeof(struct TouchHardwareDevice)); + + touch_device.dev_done = &touch_dev_done; + + ret = TouchDeviceRegister(&touch_device, NONE, TOUCH_1_DEVICE_NAME_0); + if (EOK != ret){ + KPrintf("TouchDeviceRegister device %s error %d\n", TOUCH_1_DEVICE_NAME_0, ret); + return ERROR; + } + + ret = TouchDeviceAttachToBus(TOUCH_1_DEVICE_NAME_0, TOUCH_BUS_NAME_1); + if (EOK != ret) { + KPrintf("TouchDeviceAttachToBus device %s error %d\n", TOUCH_1_DEVICE_NAME_0, ret); + return ERROR; + } + + return ret; +} + +int Stm32HwTouchBusInit(void) +{ + x_err_t ret = EOK; + struct Stm32Touch *Stmtouch; + + static struct TouchDriver touch_driver; + memset(&touch_driver, 0, sizeof(struct TouchDriver)); + + touch_driver.configure = TouchConfigure; + + Stmtouch = &touch; + Stmtouch->bus_name = TOUCH_BUS_NAME_1; + Stmtouch->touch_bus.private_data = &touch; + + ret = BoardTouchBusInit(Stmtouch, &touch_driver); + if (EOK != ret) { + return ERROR; + } + + ret = BoardTouchDevBend(); + if (EOK != ret) { + KPrintf("board_touch_Init error ret %u\n", ret); + return ERROR; + } + return EOK; +} diff --git a/Ubiquitous/XiZi/board/aiit-arm32-board/third_party_driver/uart/Kconfig b/Ubiquitous/XiZi/board/aiit-arm32-board/third_party_driver/uart/Kconfig new file mode 100644 index 0000000..c9a07f3 --- /dev/null +++ b/Ubiquitous/XiZi/board/aiit-arm32-board/third_party_driver/uart/Kconfig @@ -0,0 +1,89 @@ +menuconfig BSP_USING_USART1 + bool "Enable USART1" + default y + if BSP_USING_USART1 + config SERIAL_BUS_NAME_1 + string "serial bus 1 name" + default "usart1" + config SERIAL_DRV_NAME_1 + string "serial bus 1 driver name" + default "usart1_drv" + config SERIAL_1_DEVICE_NAME_0 + string "serial bus 1 device 0 name" + default "usart1_dev1" + config USART1_USING_DMA + bool "usart1 using DMA" + default n + endif + +menuconfig BSP_USING_USART2 + bool "Enable USART2" + default y + if BSP_USING_USART2 + config SERIAL_BUS_NAME_2 + string "serial bus 2 name" + default "usart2" + config SERIAL_DRV_NAME_2 + string "serial bus 2 driver name" + default "usart2_drv" + config SERIAL_2_DEVICE_NAME_0 + string "serial bus 2 device 0 name" + default "usart2_dev2" + config USART2_USING_DMA + bool "usart2 using DMA" + default n + endif + +menuconfig BSP_USING_USART3 + bool "Enable USART3" + default y + if BSP_USING_USART3 + config SERIAL_BUS_NAME_3 + string "serial bus 3 name" + default "usart3" + config SERIAL_DRV_NAME_3 + string "serial bus 3 driver name" + default "usart3_drv" + config SERIAL_3_DEVICE_NAME_0 + string "serial bus 3 device 0 name" + default "usart3_dev3" + config USART3_USING_DMA + bool "usart3 using DMA" + default n + endif + +menuconfig BSP_USING_UART4 + bool "Enable UART4" + default n + if BSP_USING_UART4 + config SERIAL_BUS_NAME_4 + string "serial bus 4 name" + default "uart4" + config SERIAL_DRV_NAME_4 + string "serial bus 4 driver name" + default "uart4_drv" + config SERIAL_4_DEVICE_NAME_0 + string "serial bus 4 device 0 name" + default "uart4_dev4" + config USART4_USING_DMA + bool "usart4 using DMA" + default n + endif + +menuconfig BSP_USING_UART5 + bool "Enable UART5" + default n + if BSP_USING_UART5 + config SERIAL_BUS_NAME_5 + string "serial bus 5 name" + default "uart5" + config SERIAL_DRV_NAME_5 + string "serial bus 5 driver name" + default "uart5_drv" + config SERIAL_5_DEVICE_NAME_0 + string "serial bus 5 device 0 name" + default "uart5_dev5" + config USART5_USING_DMA + bool "usart5 using DMA" + default n + endif diff --git a/Ubiquitous/XiZi/board/aiit-arm32-board/third_party_driver/uart/Makefile b/Ubiquitous/XiZi/board/aiit-arm32-board/third_party_driver/uart/Makefile new file mode 100644 index 0000000..b05646e --- /dev/null +++ b/Ubiquitous/XiZi/board/aiit-arm32-board/third_party_driver/uart/Makefile @@ -0,0 +1,3 @@ +SRC_FILES := connect_usart.c hardware_usart.c + +include $(KERNEL_ROOT)/compiler.mk diff --git a/Ubiquitous/XiZi/board/aiit-arm32-board/third_party_driver/uart/connect_usart.c b/Ubiquitous/XiZi/board/aiit-arm32-board/third_party_driver/uart/connect_usart.c new file mode 100644 index 0000000..32f8cda --- /dev/null +++ b/Ubiquitous/XiZi/board/aiit-arm32-board/third_party_driver/uart/connect_usart.c @@ -0,0 +1,879 @@ +/* + * Copyright (c) 2020 RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + */ + +/** +* @file connect_usart.c +* @brief support aiit-arm32-board usart function and register to bus framework +* @version 1.0 +* @author AIIT XUOS Lab +* @date 2021-04-25 +*/ + +/************************************************* +File name: connect_uart.c +Description: support aiit-arm32-board usart configure and uart bus register function +Others: take RT-Thread v4.0.2/bsp/stm32/libraries/HAL_Drivers/drv_usart.c for references + https://github.com/RT-Thread/rt-thread/tree/v4.0.2 +History: +1. Date: 2021-04-25 +Author: AIIT XUOS Lab +Modification: +1. support aiit-arm32-board usart configure, write and read +2. support aiit-arm32-board usart bus device and driver register +*************************************************/ + +#include +#include +#include +#include +#include + +/* UART GPIO define. */ +#define UART1_GPIO_TX GPIO_Pin_9 +#define UART1_TX_PIN_SOURCE GPIO_PinSource9 +#define UART1_GPIO_RX GPIO_Pin_10 +#define UART1_RX_PIN_SOURCE GPIO_PinSource10 +#define UART1_GPIO GPIOA +#define UART1_GPIO_RCC RCC_AHB1Periph_GPIOA +#define RCC_APBPeriph_UART1 RCC_APB2Periph_USART1 + +#define UART2_GPIO_TX GPIO_Pin_2 +#define UART2_TX_PIN_SOURCE GPIO_PinSource2 +#define UART2_GPIO_RX GPIO_Pin_3 +#define UART2_RX_PIN_SOURCE GPIO_PinSource3 +#define UART2_GPIO GPIOA +#define UART2_GPIO_RCC RCC_AHB1Periph_GPIOA +#define RCC_APBPeriph_UART2 RCC_APB1Periph_USART2 + +#define UART3_GPIO_TX GPIO_Pin_10 +#define UART3_TX_PIN_SOURCE GPIO_PinSource10 +#define UART3_GPIO_RX GPIO_Pin_11 +#define UART3_RX_PIN_SOURCE GPIO_PinSource11 +#define UART3_GPIO GPIOB +#define UART3_GPIO_RCC RCC_AHB1Periph_GPIOB +#define RCC_APBPeriph_UART3 RCC_APB1Periph_USART3 + +#define UART4_GPIO_TX GPIO_Pin_10 +#define UART4_TX_PIN_SOURCE GPIO_PinSource10 +#define UART4_GPIO_RX GPIO_Pin_11 +#define UART4_RX_PIN_SOURCE GPIO_PinSource11 +#define UART4_GPIO GPIOC +#define UART4_GPIO_RCC RCC_AHB1Periph_GPIOC +#define RCC_APBPeriph_UART4 RCC_APB1Periph_UART4 + +#define UART5_GPIO_TX GPIO_Pin_12 +#define UART5_TX_PIN_SOURCE GPIO_PinSource12 +#define UART5_GPIO_RX GPIO_Pin_2 +#define UART5_RX_PIN_SOURCE GPIO_PinSource2 +#define UART5_TX GPIOC +#define UART5_RX GPIOD +#define UART5_GPIO_RCC_TX RCC_AHB1Periph_GPIOC +#define UART5_GPIO_RCC_RX RCC_AHB1Periph_GPIOD +#define RCC_APBPeriph_UART5 RCC_APB1Periph_UART5 + +#define UART_ENABLE_IRQ(n) NVIC_EnableIRQ((n)) +#define UART_DISABLE_IRQ(n) NVIC_DisableIRQ((n)) + +static void RCCConfiguration(void) +{ +#ifdef BSP_USING_USART1 + RCC_AHB1PeriphClockCmd(UART1_GPIO_RCC, ENABLE); + RCC_APB2PeriphClockCmd(RCC_APBPeriph_UART1, ENABLE); +#endif + +#ifdef BSP_USING_USART2 + RCC_AHB1PeriphClockCmd(UART2_GPIO_RCC, ENABLE); + RCC_APB1PeriphClockCmd(RCC_APBPeriph_UART2, ENABLE); +#endif + +#ifdef BSP_USING_USART3 + RCC_AHB1PeriphClockCmd(UART3_GPIO_RCC, ENABLE); + RCC_APB1PeriphClockCmd(RCC_APBPeriph_UART3, ENABLE); +#endif + +#ifdef BSP_USING_UART4 + RCC_AHB1PeriphClockCmd(UART4_GPIO_RCC, ENABLE); + RCC_APB1PeriphClockCmd(RCC_APBPeriph_UART4, ENABLE); +#endif + +#ifdef BSP_USING_UART5 + RCC_AHB1PeriphClockCmd(UART5_GPIO_RCC_TX | UART5_GPIO_RCC_RX, ENABLE); + RCC_APB1PeriphClockCmd(RCC_APBPeriph_UART5, ENABLE); +#endif +} + +static void GPIOConfiguration(void) +{ + GPIO_InitTypeDef gpio_initstructure; + + gpio_initstructure.GPIO_Mode = GPIO_Mode_AF; + gpio_initstructure.GPIO_OType = GPIO_OType_PP; + gpio_initstructure.GPIO_PuPd = GPIO_PuPd_UP; + gpio_initstructure.GPIO_Speed = GPIO_Speed_2MHz; + +#ifdef BSP_USING_USART1 + gpio_initstructure.GPIO_Pin = UART1_GPIO_RX | UART1_GPIO_TX; + GPIO_PinAFConfig(UART1_GPIO, UART1_TX_PIN_SOURCE, GPIO_AF_USART1); + GPIO_PinAFConfig(UART1_GPIO, UART1_RX_PIN_SOURCE, GPIO_AF_USART1); + + GPIO_Init(UART1_GPIO, &gpio_initstructure); +#endif + +#ifdef BSP_USING_USART2 + gpio_initstructure.GPIO_Pin = UART2_GPIO_RX | UART2_GPIO_TX; + GPIO_PinAFConfig(UART2_GPIO, UART2_TX_PIN_SOURCE, GPIO_AF_USART2); + GPIO_PinAFConfig(UART2_GPIO, UART2_RX_PIN_SOURCE, GPIO_AF_USART2); + + GPIO_Init(UART2_GPIO, &gpio_initstructure); +#endif + +#ifdef BSP_USING_USART3 + gpio_initstructure.GPIO_Pin = UART3_GPIO_TX | UART3_GPIO_RX; + GPIO_PinAFConfig(UART3_GPIO, UART3_TX_PIN_SOURCE, GPIO_AF_USART3); + GPIO_PinAFConfig(UART3_GPIO, UART3_RX_PIN_SOURCE, GPIO_AF_USART3); + + GPIO_Init(UART3_GPIO, &gpio_initstructure); +#endif + +#ifdef BSP_USING_UART4 + gpio_initstructure.GPIO_Pin = UART4_GPIO_TX | UART4_GPIO_RX; + GPIO_PinAFConfig(UART4_GPIO, UART4_TX_PIN_SOURCE, GPIO_AF_UART4); + GPIO_PinAFConfig(UART4_GPIO, UART4_RX_PIN_SOURCE, GPIO_AF_UART4); + + GPIO_Init(UART4_GPIO, &gpio_initstructure); +#endif + +#ifdef BSP_USING_UART5 + gpio_initstructure.GPIO_Pin = UART5_GPIO_TX; + GPIO_PinAFConfig(UART5_TX, UART5_TX_PIN_SOURCE, GPIO_AF_UART5); + GPIO_Init(UART5_TX, &gpio_initstructure); + + gpio_initstructure.GPIO_Pin = UART5_GPIO_RX; + GPIO_PinAFConfig(UART5_RX, UART5_RX_PIN_SOURCE, GPIO_AF_UART5); + GPIO_Init(UART5_RX, &gpio_initstructure); +#endif +} + +static void NVIC_Configuration(IRQn_Type irq) +{ + NVIC_InitTypeDef nvic_initstructure; + + nvic_initstructure.NVIC_IRQChannel = irq; + nvic_initstructure.NVIC_IRQChannelPreemptionPriority = 0; + nvic_initstructure.NVIC_IRQChannelSubPriority = 1; + nvic_initstructure.NVIC_IRQChannelCmd = ENABLE; + NVIC_Init(&nvic_initstructure); +} + +static void DmaUartConfig(struct Stm32UsartDma *dma, USART_TypeDef *uart_device, uint32_t SettingRecvLen, void *mem_base_addr) +{ + DMA_InitTypeDef DMA_InitStructure; + + dma->SettingRecvLen = SettingRecvLen; + DMA_DeInit(dma->RxStream); + while (DMA_GetCmdStatus(dma->RxStream) != DISABLE); + DMA_InitStructure.DMA_Channel = dma->RxCh; + DMA_InitStructure.DMA_PeripheralBaseAddr = (uint32_t) &(uart_device->DR); + DMA_InitStructure.DMA_Memory0BaseAddr = (uint32_t)mem_base_addr; + DMA_InitStructure.DMA_DIR = DMA_DIR_PeripheralToMemory; + DMA_InitStructure.DMA_BufferSize = dma->SettingRecvLen; + DMA_InitStructure.DMA_PeripheralInc = DMA_PeripheralInc_Disable; + DMA_InitStructure.DMA_MemoryInc = DMA_MemoryInc_Enable; + DMA_InitStructure.DMA_PeripheralDataSize = DMA_PeripheralDataSize_Byte; + DMA_InitStructure.DMA_MemoryDataSize = DMA_PeripheralDataSize_Byte; + DMA_InitStructure.DMA_Mode = DMA_Mode_Circular; + DMA_InitStructure.DMA_Priority = DMA_Priority_High; + DMA_InitStructure.DMA_FIFOMode = DMA_FIFOMode_Disable; + DMA_InitStructure.DMA_FIFOThreshold = DMA_FIFOThreshold_Full; + DMA_InitStructure.DMA_MemoryBurst = DMA_MemoryBurst_Single; + DMA_InitStructure.DMA_PeripheralBurst = DMA_PeripheralBurst_Single; + DMA_Init(dma->RxStream, &DMA_InitStructure); +} + +static void DMAConfiguration(struct SerialHardwareDevice *serial_dev, USART_TypeDef *uart_device) +{ + struct Stm32Usart *serial = CONTAINER_OF(serial_dev->haldev.owner_bus, struct Stm32Usart, serial_bus); + struct Stm32UsartDma *dma = &serial->dma; + struct SerialCfgParam *serial_cfg = (struct SerialCfgParam *)serial_dev->private_data; + + NVIC_InitTypeDef nvic_initstructure; + + USART_ITConfig(uart_device, USART_IT_IDLE , ENABLE); + + RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_DMA1, ENABLE); + RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_DMA2, ENABLE); + + DmaUartConfig(dma, uart_device, serial_cfg->data_cfg.serial_buffer_size, serial_dev->serial_fifo.serial_rx->serial_rx_buffer); + + DMA_ClearFlag(dma->RxStream, dma->RxFlag); + DMA_ITConfig(dma->RxStream, DMA_IT_TC, ENABLE); + USART_DMACmd(uart_device, USART_DMAReq_Rx, ENABLE); + DMA_Cmd(dma->RxStream, ENABLE); + + nvic_initstructure.NVIC_IRQChannel = dma->RxIrqCh; + nvic_initstructure.NVIC_IRQChannelPreemptionPriority = 0; + nvic_initstructure.NVIC_IRQChannelSubPriority = 0; + nvic_initstructure.NVIC_IRQChannelCmd = ENABLE; + NVIC_Init(&nvic_initstructure); +} + +static void SerialCfgParamCheck(struct SerialCfgParam *serial_cfg_default, struct SerialCfgParam *serial_cfg_new) +{ + struct SerialDataCfg *data_cfg_default = &serial_cfg_default->data_cfg; + struct SerialDataCfg *data_cfg_new = &serial_cfg_new->data_cfg; + + if((data_cfg_default->serial_baud_rate != data_cfg_new->serial_baud_rate) && (data_cfg_new->serial_baud_rate)) { + data_cfg_default->serial_baud_rate = data_cfg_new->serial_baud_rate; + } + + if((data_cfg_default->serial_bit_order != data_cfg_new->serial_bit_order) && (data_cfg_new->serial_bit_order)) { + data_cfg_default->serial_bit_order = data_cfg_new->serial_bit_order; + } + + if((data_cfg_default->serial_buffer_size != data_cfg_new->serial_buffer_size) && (data_cfg_new->serial_buffer_size)) { + data_cfg_default->serial_buffer_size = data_cfg_new->serial_buffer_size; + } + + if((data_cfg_default->serial_data_bits != data_cfg_new->serial_data_bits) && (data_cfg_new->serial_data_bits)) { + data_cfg_default->serial_data_bits = data_cfg_new->serial_data_bits; + } + + if((data_cfg_default->serial_invert_mode != data_cfg_new->serial_invert_mode) && (data_cfg_new->serial_invert_mode)) { + data_cfg_default->serial_invert_mode = data_cfg_new->serial_invert_mode; + } + + if((data_cfg_default->serial_parity_mode != data_cfg_new->serial_parity_mode) && (data_cfg_new->serial_parity_mode)) { + data_cfg_default->serial_parity_mode = data_cfg_new->serial_parity_mode; + } + + if((data_cfg_default->serial_stop_bits != data_cfg_new->serial_stop_bits) && (data_cfg_new->serial_stop_bits)) { + data_cfg_default->serial_stop_bits = data_cfg_new->serial_stop_bits; + } +} + +static uint32 Stm32SerialInit(struct SerialDriver *serial_drv, struct BusConfigureInfo *configure_info) +{ + NULL_PARAM_CHECK(serial_drv); + + struct SerialCfgParam *serial_cfg = (struct SerialCfgParam *)serial_drv->private_data; + struct UsartHwCfg *serial_hw_cfg = (struct UsartHwCfg *)serial_cfg->hw_cfg.private_data; + + if (configure_info->private_data) { + struct SerialCfgParam *serial_cfg_new = (struct SerialCfgParam *)configure_info->private_data; + SerialCfgParamCheck(serial_cfg, serial_cfg_new); + } + + USART_InitTypeDef USART_InitStructure; + + USART_InitStructure.USART_BaudRate = serial_cfg->data_cfg.serial_baud_rate; + + if (serial_cfg->data_cfg.serial_data_bits == DATA_BITS_8) { + USART_InitStructure.USART_WordLength = USART_WordLength_8b; + } else if (serial_cfg->data_cfg.serial_data_bits == DATA_BITS_9) { + USART_InitStructure.USART_WordLength = USART_WordLength_9b; + } + + if (serial_cfg->data_cfg.serial_stop_bits == STOP_BITS_1) { + USART_InitStructure.USART_StopBits = USART_StopBits_1; + } else if (serial_cfg->data_cfg.serial_stop_bits == STOP_BITS_2) { + USART_InitStructure.USART_StopBits = USART_StopBits_2; + } + + if (serial_cfg->data_cfg.serial_parity_mode == PARITY_NONE) { + USART_InitStructure.USART_Parity = USART_Parity_No; + } else if (serial_cfg->data_cfg.serial_parity_mode == PARITY_ODD) { + USART_InitStructure.USART_Parity = USART_Parity_Odd; + } else if (serial_cfg->data_cfg.serial_parity_mode == PARITY_EVEN) { + USART_InitStructure.USART_Parity = USART_Parity_Even; + } + + USART_InitStructure.USART_HardwareFlowControl = USART_HardwareFlowControl_None; + USART_InitStructure.USART_Mode = USART_Mode_Rx | USART_Mode_Tx; + USART_Init(serial_hw_cfg->uart_device, &USART_InitStructure); + + USART_Cmd(serial_hw_cfg->uart_device, ENABLE); + + return EOK; +} + +static uint32 Stm32SerialConfigure(struct SerialDriver *serial_drv, int serial_operation_cmd) +{ + NULL_PARAM_CHECK(serial_drv); + + struct SerialHardwareDevice *serial_dev = (struct SerialHardwareDevice *)serial_drv->driver.owner_bus->owner_haldev; + struct SerialCfgParam *serial_cfg = (struct SerialCfgParam *)serial_drv->private_data; + struct UsartHwCfg *serial_hw_cfg = (struct UsartHwCfg *)serial_cfg->hw_cfg.private_data; + struct SerialDevParam *serial_dev_param = (struct SerialDevParam *)serial_dev->haldev.private_data; + + switch (serial_operation_cmd) + { + case OPER_CLR_INT: + UART_DISABLE_IRQ(serial_hw_cfg->irq); + USART_ITConfig(serial_hw_cfg->uart_device, USART_IT_RXNE, DISABLE); + break; + case OPER_SET_INT: + UART_ENABLE_IRQ(serial_hw_cfg->irq); + USART_ITConfig(serial_hw_cfg->uart_device, USART_IT_RXNE, ENABLE); + break; + case OPER_CONFIG : + if (SIGN_OPER_DMA_RX == serial_dev_param->serial_set_mode) { + DMAConfiguration(serial_dev, serial_hw_cfg->uart_device); + } + } + + return EOK; +} + +static int Stm32SerialPutchar(struct SerialHardwareDevice *serial_dev, char c) +{ + struct SerialCfgParam *serial_cfg = (struct SerialCfgParam *)serial_dev->private_data; + struct UsartHwCfg *serial_hw_cfg = (struct UsartHwCfg *)serial_cfg->hw_cfg.private_data; + + while (!(serial_hw_cfg->uart_device->SR & USART_FLAG_TXE)); + serial_hw_cfg->uart_device->DR = c; + + return EOK; +} + +static int Stm32SerialGetchar(struct SerialHardwareDevice *serial_dev) +{ + struct SerialCfgParam *serial_cfg = (struct SerialCfgParam *)serial_dev->private_data; + struct UsartHwCfg *serial_hw_cfg = (struct UsartHwCfg *)serial_cfg->hw_cfg.private_data; + + int ch = -1; + if (serial_hw_cfg->uart_device->SR & USART_FLAG_RXNE) { + ch = serial_hw_cfg->uart_device->DR & 0xff; + } + + return ch; +} + +static void DmaUartRxIdleIsr(struct SerialHardwareDevice *serial_dev, struct Stm32UsartDma *dma, USART_TypeDef *uart_device) +{ + x_base level = CriticalAreaLock(); + + x_size_t recv_total_index = dma->SettingRecvLen - DMA_GetCurrDataCounter(dma->RxStream); + x_size_t recv_len = recv_total_index - dma->LastRecvIndex; + dma->LastRecvIndex = recv_total_index; + CriticalAreaUnLock(level); + + if (recv_len) SerialSetIsr(serial_dev, SERIAL_EVENT_RX_DMADONE | (recv_len << 8)); + + USART_ReceiveData(uart_device); +} + +static void DmaRxDoneIsr(struct Stm32Usart *serial, struct SerialDriver *serial_drv, struct SerialHardwareDevice *serial_dev) +{ + struct Stm32UsartDma *dma = &serial->dma; + struct SerialCfgParam *serial_cfg = (struct SerialCfgParam *)serial_drv->private_data; + struct UsartHwCfg *serial_hw_cfg = (struct UsartHwCfg *)serial_cfg->hw_cfg.private_data; + + if (DMA_GetFlagStatus(dma->RxStream, dma->RxFlag) != RESET) { + x_base level = CriticalAreaLock(); + + x_size_t recv_len; + + x_size_t recv_total_index = dma->SettingRecvLen - DMA_GetCurrDataCounter(dma->RxStream); + if (0 != recv_total_index) { + recv_len = recv_total_index - dma->LastRecvIndex; + } else { + recv_len = dma->SettingRecvLen - dma->LastRecvIndex; + } + dma->LastRecvIndex = recv_total_index; + + CriticalAreaUnLock(level); + + if (recv_len) SerialSetIsr(serial_dev, SERIAL_EVENT_RX_DMADONE | (recv_len << 8)); + + DMA_ClearFlag(dma->RxStream, dma->RxFlag); + } +} + +static void UartIsr(struct Stm32Usart *serial, struct SerialDriver *serial_drv, struct SerialHardwareDevice *serial_dev) +{ + struct Stm32UsartDma *dma = &serial->dma; + struct SerialCfgParam *serial_cfg = (struct SerialCfgParam *)serial_drv->private_data; + struct UsartHwCfg *serial_hw_cfg = (struct UsartHwCfg *)serial_cfg->hw_cfg.private_data; + + if (USART_GetITStatus(serial_hw_cfg->uart_device, USART_IT_RXNE) != RESET) { + SerialSetIsr(serial_dev, SERIAL_EVENT_RX_IND); + USART_ClearITPendingBit(serial_hw_cfg->uart_device, USART_IT_RXNE); + } else if (USART_GetITStatus(serial_hw_cfg->uart_device, USART_IT_IDLE) != RESET) { + DmaUartRxIdleIsr(serial_dev, dma, serial_hw_cfg->uart_device); + } else if (USART_GetITStatus(serial_hw_cfg->uart_device, USART_IT_TC) != RESET) { + USART_ClearITPendingBit(serial_hw_cfg->uart_device, USART_IT_TC); + } else { + if (USART_GetFlagStatus(serial_hw_cfg->uart_device, USART_FLAG_ORE) == SET) { + USART_ReceiveData(serial_hw_cfg->uart_device); + } + } +} + +#ifdef BSP_USING_USART1 +struct Stm32Usart serial_1; +struct SerialDriver serial_driver_1; +struct SerialHardwareDevice serial_device_1; + +static const struct Stm32UsartDma usart_dma_1 = +{ + DMA2_Stream5, + DMA_Channel_4, + DMA_FLAG_TCIF5, + DMA2_Stream5_IRQn, + 0, + 0, +}; + +void USART1_IRQHandler(int irq_num, void *arg) +{ + UartIsr(&serial_1, &serial_driver_1, &serial_device_1); +} +DECLARE_HW_IRQ(USART1_IRQn, USART1_IRQHandler, NONE); + +void DMA2_Stream5_IRQHandler(int irq_num, void *arg) { + DmaRxDoneIsr(&serial_1, &serial_driver_1, &serial_device_1); +} +DECLARE_HW_IRQ(DMA2_Stream5_IRQn, DMA2_Stream5_IRQHandler, NONE); +#endif + +#ifdef BSP_USING_USART2 +struct Stm32Usart serial_2; +struct SerialDriver serial_driver_2; +struct SerialHardwareDevice serial_device_2; + +static const struct Stm32UsartDma usart_dma_2 = +{ + DMA1_Stream5, + DMA_Channel_4, + DMA_FLAG_TCIF5, + DMA1_Stream5_IRQn, + 0, + 0, +}; + +void USART2_IRQHandler(int irq_num, void *arg) +{ + UartIsr(&serial_2, &serial_driver_2, &serial_device_2); +} +DECLARE_HW_IRQ(USART2_IRQn, USART2_IRQHandler, NONE); + +void DMA1_Stream5_IRQHandler(int irq_num, void *arg) { + DmaRxDoneIsr(&serial_2, &serial_driver_2, &serial_device_2); +} +DECLARE_HW_IRQ(DMA1_Stream5_IRQn, DMA1_Stream5_IRQHandler, NONE); +#endif + +#ifdef BSP_USING_USART3 +struct Stm32Usart serial_3; +struct SerialDriver serial_driver_3; +struct SerialHardwareDevice serial_device_3; + +static const struct Stm32UsartDma usart_dma_3 = +{ + DMA1_Stream1, + DMA_Channel_4, + DMA_FLAG_TCIF1, + DMA1_Stream1_IRQn, + 0, + 0, +}; + +void USART3_IRQHandler(int irq_num, void *arg) +{ + UartIsr(&serial_3, &serial_driver_3, &serial_device_3); +} +DECLARE_HW_IRQ(USART3_IRQn, USART3_IRQHandler, NONE); + +void DMA1_Stream1_IRQHandler(int irq_num, void *arg) { + DmaRxDoneIsr(&serial_3, &serial_driver_3, &serial_device_3); +} +DECLARE_HW_IRQ(DMA1_Stream1_IRQn, DMA1_Stream1_IRQHandler, NONE); +#endif + +#ifdef BSP_USING_UART4 +struct Stm32Usart serial_4; +struct SerialDriver serial_driver_4; +struct SerialHardwareDevice serial_device_4; + +static const struct Stm32UsartDma uart_dma_4 = +{ + DMA1_Stream2, + DMA_Channel_4, + DMA_FLAG_TCIF2, + DMA1_Stream2_IRQn, + 0, + 0, +}; + +void UART4_IRQHandler(int irq_num, void *arg) +{ + UartIsr(&serial_4, &serial_driver_4, &serial_device_4); +} +DECLARE_HW_IRQ(UART4_IRQn, UART4_IRQHandler, NONE); + +void DMA1_Stream2_IRQHandler(int irq_num, void *arg) { + DmaRxDoneIsr(&serial_4, &serial_driver_4, &serial_device_4); +} +DECLARE_HW_IRQ(DMA1_Stream2_IRQn, DMA1_Stream2_IRQHandler, NONE); +#endif + +#ifdef BSP_USING_UART5 +struct Stm32Usart serial_5; +struct SerialDriver serial_driver_5; +struct SerialHardwareDevice serial_device_5; + +static const struct Stm32UsartDma uart_dma_5 = +{ + DMA1_Stream0, + DMA_Channel_4, + DMA_FLAG_TCIF0, + DMA1_Stream0_IRQn, + 0, + 0, +}; + +void UART5_IRQHandler(int irq_num, void *arg) +{ + UartIsr(&serial_5, &serial_driver_5, &serial_device_5); +} +DECLARE_HW_IRQ(UART5_IRQn, UART5_IRQHandler, NONE); + +void DMA1_Stream0_IRQHandler(int irq_num, void *arg) { + DmaRxDoneIsr(&serial_5, &serial_driver_5, &serial_device_5); +} +DECLARE_HW_IRQ(DMA1_Stream0_IRQn, DMA1_Stream0_IRQHandler, NONE); +#endif + +static uint32 Stm32SerialDrvConfigure(void *drv, struct BusConfigureInfo *configure_info) +{ + NULL_PARAM_CHECK(drv); + NULL_PARAM_CHECK(configure_info); + + x_err_t ret = EOK; + int serial_operation_cmd; + struct SerialDriver *serial_drv = (struct SerialDriver *)drv; + + switch (configure_info->configure_cmd) + { + case OPE_INT: + ret = Stm32SerialInit(serial_drv, configure_info); + break; + case OPE_CFG: + serial_operation_cmd = *(int *)configure_info->private_data; + ret = Stm32SerialConfigure(serial_drv, serial_operation_cmd); + break; + default: + break; + } + + return ret; +} + +static const struct SerialDataCfg data_cfg_init = +{ + .serial_baud_rate = BAUD_RATE_115200, + .serial_data_bits = DATA_BITS_8, + .serial_stop_bits = STOP_BITS_1, + .serial_parity_mode = PARITY_NONE, + .serial_bit_order = BIT_ORDER_LSB, + .serial_invert_mode = NRZ_NORMAL, + .serial_buffer_size = SERIAL_RB_BUFSZ, +}; + +/*manage the serial device operations*/ +static const struct SerialDrvDone drv_done = +{ + .init = Stm32SerialInit, + .configure = Stm32SerialConfigure, +}; + +/*manage the serial device hal operations*/ +static struct SerialHwDevDone hwdev_done = +{ + .put_char = Stm32SerialPutchar, + .get_char = Stm32SerialGetchar, +}; + +static int BoardSerialBusInit(struct SerialBus *serial_bus, struct SerialDriver *serial_driver, const char *bus_name, const char *drv_name) +{ + x_err_t ret = EOK; + + /*Init the serial bus */ + ret = SerialBusInit(serial_bus, bus_name); + if (EOK != ret) { + KPrintf("hw_serial_init SerialBusInit error %d\n", ret); + return ERROR; + } + + /*Init the serial driver*/ + ret = SerialDriverInit(serial_driver, drv_name); + if (EOK != ret) { + KPrintf("hw_serial_init SerialDriverInit error %d\n", ret); + return ERROR; + } + + /*Attach the serial driver to the serial bus*/ + ret = SerialDriverAttachToBus(drv_name, bus_name); + if (EOK != ret) { + KPrintf("hw_serial_init SerialDriverAttachToBus error %d\n", ret); + return ERROR; + } + + return ret; +} + +/*Attach the serial device to the serial bus*/ +static int BoardSerialDevBend(struct SerialHardwareDevice *serial_device, void *serial_param, const char *bus_name, const char *dev_name) +{ + x_err_t ret = EOK; + + ret = SerialDeviceRegister(serial_device, serial_param, dev_name); + if (EOK != ret) { + KPrintf("hw_serial_init SerialDeviceInit device %s error %d\n", dev_name, ret); + return ERROR; + } + + ret = SerialDeviceAttachToBus(dev_name, bus_name); + if (EOK != ret) { + KPrintf("hw_serial_init SerialDeviceAttachToBus device %s error %d\n", dev_name, ret); + return ERROR; + } + + return ret; +} + +int Stm32HwUsartInit(void) +{ + x_err_t ret = EOK; + + RCCConfiguration(); + GPIOConfiguration(); + +#ifdef BSP_USING_USART1 + static struct SerialCfgParam serial_cfg_1; + memset(&serial_cfg_1, 0, sizeof(struct SerialCfgParam)); + + static struct UsartHwCfg serial_hw_cfg_1; + memset(&serial_hw_cfg_1, 0, sizeof(struct UsartHwCfg)); + + static struct SerialDevParam serial_dev_param_1; + memset(&serial_dev_param_1, 0, sizeof(struct SerialDevParam)); + + serial_1.dma = usart_dma_1; + + serial_driver_1.drv_done = &drv_done; + serial_driver_1.configure = &Stm32SerialDrvConfigure; + serial_device_1.hwdev_done = &hwdev_done; + + serial_cfg_1.data_cfg = data_cfg_init; + + serial_hw_cfg_1.uart_device = USART1; + serial_hw_cfg_1.irq = USART1_IRQn; + serial_cfg_1.hw_cfg.private_data = (void *)&serial_hw_cfg_1; + serial_driver_1.private_data = (void *)&serial_cfg_1; + + serial_dev_param_1.serial_work_mode = SIGN_OPER_INT_RX; +#ifdef USART1_USING_DMA + serial_dev_param_1.serial_work_mode = SIGN_OPER_DMA_RX; +#endif + serial_device_1.haldev.private_data = (void *)&serial_dev_param_1; + + NVIC_Configuration(serial_hw_cfg_1.irq); + + ret = BoardSerialBusInit(&serial_1.serial_bus, &serial_driver_1, SERIAL_BUS_NAME_1, SERIAL_DRV_NAME_1); + if (EOK != ret) { + KPrintf("Stm32HwUsartInit usart1 error ret %u\n", ret); + return ERROR; + } + + ret = BoardSerialDevBend(&serial_device_1, (void *)&serial_cfg_1, SERIAL_BUS_NAME_1, SERIAL_1_DEVICE_NAME_0); + if (EOK != ret) { + KPrintf("Stm32HwUsartInit usart1 error ret %u\n", ret); + return ERROR; + } +#endif + +#ifdef BSP_USING_USART2 + static struct SerialCfgParam serial_cfg_2; + memset(&serial_cfg_2, 0, sizeof(struct SerialCfgParam)); + + static struct UsartHwCfg serial_hw_cfg_2; + memset(&serial_hw_cfg_2, 0, sizeof(struct UsartHwCfg)); + + static struct SerialDevParam serial_dev_param_2; + memset(&serial_dev_param_2, 0, sizeof(struct SerialDevParam)); + + serial_2.dma = usart_dma_2; + + serial_driver_2.drv_done = &drv_done; + serial_driver_2.configure = &Stm32SerialDrvConfigure; + serial_device_2.hwdev_done = &hwdev_done; + + serial_cfg_2.data_cfg = data_cfg_init; + + serial_hw_cfg_2.uart_device = USART2; + serial_hw_cfg_2.irq = USART2_IRQn; + serial_cfg_2.hw_cfg.private_data = (void *)&serial_hw_cfg_2; + serial_driver_2.private_data = (void *)&serial_cfg_2; + + serial_dev_param_2.serial_work_mode = SIGN_OPER_INT_RX; +#ifdef USART2_USING_DMA + serial_dev_param_2.serial_work_mode = SIGN_OPER_DMA_RX; +#endif + serial_device_2.haldev.private_data = (void *)&serial_dev_param_2; + + NVIC_Configuration(serial_hw_cfg_2.irq); + + ret = BoardSerialBusInit(&serial_2.serial_bus, &serial_driver_2, SERIAL_BUS_NAME_2, SERIAL_DRV_NAME_2); + if (EOK != ret) { + KPrintf("Stm32HwUsartInit usart2 error ret %u\n", ret); + return ERROR; + } + + ret = BoardSerialDevBend(&serial_device_2, (void *)&serial_cfg_2, SERIAL_BUS_NAME_2, SERIAL_2_DEVICE_NAME_0); + if (EOK != ret) { + KPrintf("Stm32HwUsartInit usart2 error ret %u\n", ret); + return ERROR; + } +#endif + +#ifdef BSP_USING_USART3 + static struct SerialCfgParam serial_cfg_3; + memset(&serial_cfg_3, 0, sizeof(struct SerialCfgParam)); + + static struct UsartHwCfg serial_hw_cfg_3; + memset(&serial_hw_cfg_3, 0, sizeof(struct UsartHwCfg)); + + static struct SerialDevParam serial_dev_param_3; + memset(&serial_dev_param_3, 0, sizeof(struct SerialDevParam)); + + serial_3.dma = usart_dma_3; + + serial_driver_3.drv_done = &drv_done; + serial_driver_3.configure = &Stm32SerialDrvConfigure; + serial_device_3.hwdev_done = &hwdev_done; + + serial_cfg_3.data_cfg = data_cfg_init; + + serial_hw_cfg_3.uart_device = USART3; + serial_hw_cfg_3.irq = USART3_IRQn; + serial_cfg_3.hw_cfg.private_data = (void *)&serial_hw_cfg_3; + serial_driver_3.private_data = (void *)&serial_cfg_3; + + serial_dev_param_3.serial_work_mode = SIGN_OPER_INT_RX; +#ifdef USART3_USING_DMA + serial_dev_param_3.serial_work_mode = SIGN_OPER_DMA_RX; +#endif + serial_device_3.haldev.private_data = (void *)&serial_dev_param_3; + + NVIC_Configuration(serial_hw_cfg_3.irq); + + ret = BoardSerialBusInit(&serial_3.serial_bus, &serial_driver_3, SERIAL_BUS_NAME_3, SERIAL_DRV_NAME_3); + if (EOK != ret) { + KPrintf("Stm32HwUsartInit usart3 error ret %u\n", ret); + return ERROR; + } + + ret = BoardSerialDevBend(&serial_device_3, (void *)&serial_cfg_3, SERIAL_BUS_NAME_3, SERIAL_3_DEVICE_NAME_0); + if (EOK != ret) { + KPrintf("Stm32HwUsartInit usart3 error ret %u\n", ret); + return ERROR; + } +#endif + +#ifdef BSP_USING_UART4 + static struct SerialCfgParam serial_cfg_4; + memset(&serial_cfg_4, 0, sizeof(struct SerialCfgParam)); + + static struct UsartHwCfg serial_hw_cfg_4; + memset(&serial_hw_cfg_4, 0, sizeof(struct UsartHwCfg)); + + static struct SerialDevParam serial_dev_param_4; + memset(&serial_dev_param_4, 0, sizeof(struct SerialDevParam)); + + serial_4.dma = uart_dma_4; + + serial_driver_4.drv_done = &drv_done; + serial_driver_4.configure = &Stm32SerialDrvConfigure; + serial_device_4.hwdev_done = &hwdev_done; + + serial_cfg_4.data_cfg = data_cfg_init; + + serial_hw_cfg_4.uart_device = UART4; + serial_hw_cfg_4.irq = UART4_IRQn; + serial_cfg_4.hw_cfg.private_data = (void *)&serial_hw_cfg_4; + serial_driver_4.private_data = (void *)&serial_cfg_4; + + serial_dev_param_4.serial_work_mode = SIGN_OPER_INT_RX; +#ifdef USART4_USING_DMA + serial_dev_param_4.serial_work_mode = SIGN_OPER_DMA_RX; +#endif + serial_device_4.haldev.private_data = (void *)&serial_dev_param_4; + + NVIC_Configuration(serial_hw_cfg_4.irq); + + ret = BoardSerialBusInit(&serial_4.serial_bus, &serial_driver_4, SERIAL_BUS_NAME_4, SERIAL_DRV_NAME_4); + if (EOK != ret) { + KPrintf("Stm32HwUsartInit usart4 error ret %u\n", ret); + return ERROR; + } + + ret = BoardSerialDevBend(&serial_device_4, (void *)&serial_cfg_4, SERIAL_BUS_NAME_4, SERIAL_4_DEVICE_NAME_0); + if (EOK != ret) { + KPrintf("Stm32HwUsartInit usart4 error ret %u\n", ret); + return ERROR; + } +#endif + +#ifdef BSP_USING_UART5 + static struct SerialCfgParam serial_cfg_5; + memset(&serial_cfg_5, 0, sizeof(struct SerialCfgParam)); + + static struct UsartHwCfg serial_hw_cfg_5; + memset(&serial_hw_cfg_5, 0, sizeof(struct UsartHwCfg)); + + static struct SerialDevParam serial_dev_param_5; + memset(&serial_dev_param_5, 0, sizeof(struct SerialDevParam)); + + serial_5.dma = uart_dma_5; + + serial_driver_5.drv_done = &drv_done; + serial_driver_5.configure = &Stm32SerialDrvConfigure; + serial_device_5.hwdev_done = &hwdev_done; + + serial_cfg_5.data_cfg = data_cfg_init; + + serial_hw_cfg_5.uart_device = UART5; + serial_hw_cfg_5.irq = UART5_IRQn; + serial_cfg_5.hw_cfg.private_data = (void *)&serial_hw_cfg_5; + serial_driver_5.private_data = (void *)&serial_cfg_5; + + serial_dev_param_5.serial_work_mode = SIGN_OPER_INT_RX; +#ifdef USART5_USING_DMA + serial_dev_param_5.serial_work_mode = SIGN_OPER_DMA_RX; +#endif + serial_device_5.haldev.private_data = (void *)&serial_dev_param_5; + + NVIC_Configuration(serial_hw_cfg_5.irq); + + ret = BoardSerialBusInit(&serial_5.serial_bus, &serial_driver_5, SERIAL_BUS_NAME_5, SERIAL_DRV_NAME_5); + if (EOK != ret) { + KPrintf("Stm32HwUsartInit usart5 error ret %u\n", ret); + return ERROR; + } + + ret = BoardSerialDevBend(&serial_device_5, (void *)&serial_cfg_5, SERIAL_BUS_NAME_5, SERIAL_5_DEVICE_NAME_0); + if (EOK != ret) { + KPrintf("Stm32HwUsartInit usart5 error ret %u\n", ret); + return ERROR; + } +#endif + + return ret; +} diff --git a/Ubiquitous/XiZi/board/aiit-arm32-board/third_party_driver/usb/Kconfig b/Ubiquitous/XiZi/board/aiit-arm32-board/third_party_driver/usb/Kconfig new file mode 100644 index 0000000..4fcd378 --- /dev/null +++ b/Ubiquitous/XiZi/board/aiit-arm32-board/third_party_driver/usb/Kconfig @@ -0,0 +1,15 @@ +config BSP_USING_STM32_USBH + bool "Using usb host" + default y + if BSP_USING_STM32_USBH + config USB_BUS_NAME + string "usb bus name" + default "usb" + config USB_DRIVER_NAME + string "usb bus driver name" + default "usb_drv" + config USB_DEVICE_NAME + string "usb bus device name" + default "usb_dev" + endif + diff --git a/Ubiquitous/XiZi/board/aiit-arm32-board/third_party_driver/usb/Makefile b/Ubiquitous/XiZi/board/aiit-arm32-board/third_party_driver/usb/Makefile new file mode 100644 index 0000000..6331e6e --- /dev/null +++ b/Ubiquitous/XiZi/board/aiit-arm32-board/third_party_driver/usb/Makefile @@ -0,0 +1,4 @@ +SRC_FILES := usb_bsp.c usbh.c connect_usb.c +SRC_FILES += STM32_USB_OTG_Driver/src/usb_core.c STM32_USB_OTG_Driver/src/usb_hcd.c STM32_USB_OTG_Driver/src/usb_hcd_int.c + +include $(KERNEL_ROOT)/compiler.mk diff --git a/Ubiquitous/XiZi/board/aiit-arm32-board/third_party_driver/usb/connect_usb.c b/Ubiquitous/XiZi/board/aiit-arm32-board/third_party_driver/usb/connect_usb.c new file mode 100644 index 0000000..64b5668 --- /dev/null +++ b/Ubiquitous/XiZi/board/aiit-arm32-board/third_party_driver/usb/connect_usb.c @@ -0,0 +1,123 @@ +/* +* Copyright (c) 2020 AIIT XUOS Lab +* XiUOS is licensed under Mulan PSL v2. +* You can use this software according to the terms and conditions of the Mulan PSL v2. +* You may obtain a copy of Mulan PSL v2 at: +* http://license.coscl.org.cn/MulanPSL2 +* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, +* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, +* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. +* See the Mulan PSL v2 for more details. +*/ + +/** +* @file connect_usb.c +* @brief support aiit-arm32-board usb function and register to bus framework +* @version 1.0 +* @author AIIT XUOS Lab +* @date 2021-04-25 +*/ + +#include +#include +#include + +uint32 UdiskRead_new_api(void *dev, struct BusBlockReadParam *read_param); +uint32 UdiskWirte_new_api(void *dev, struct BusBlockWriteParam *write_param); + +static uint32 UdiskOpenNewApi(void *dev) +{ + return EOK; +} + +static uint32 UdiskCloseNewApi(void *dev) +{ + return EOK; +} + +/*manage the usb device operations*/ +static const struct UsbDevDone dev_done = +{ + .open = UdiskOpenNewApi, + .close = UdiskCloseNewApi, + .write = UdiskWirte_new_api, + .read = UdiskRead_new_api, +}; + +/*Init usb bus*/ +static int BoardUsbBusInit(struct UsbBus *usb_bus, struct UsbDriver *usb_driver) +{ + x_err_t ret = EOK; + + /*Init the usb bus */ + ret = UsbBusInit(usb_bus, USB_BUS_NAME); + if (EOK != ret) { + KPrintf("board_usb_init UsbBusInit error %d\n", ret); + return ERROR; + } + + /*Init the usb driver*/ + ret = UsbDriverInit(usb_driver, USB_DRIVER_NAME); + if (EOK != ret){ + KPrintf("board_usb_init UsbDriverInit error %d\n", ret); + return ERROR; + } + + /*Attach the usb driver to the usb bus*/ + ret = UsbDriverAttachToBus(USB_DRIVER_NAME, USB_BUS_NAME); + if (EOK != ret) { + KPrintf("board_usb_init USEDriverAttachToBus error %d\n", ret); + return ERROR; + } + + return ret; +} + +/*Attach the usb device to the usb bus*/ +static int BoardUsbDevBend(void) +{ + x_err_t ret = EOK; + static struct UsbHardwareDevice usb_device1; + memset(&usb_device1, 0, sizeof(struct UsbHardwareDevice)); + + usb_device1.dev_done = &dev_done; + + ret = USBDeviceRegister(&usb_device1, NONE, USB_DEVICE_NAME); + if (EOK != ret) { + KPrintf("board_usb_init USBDeviceInit device %s error %d\n", USB_DEVICE_NAME, ret); + return ERROR; + } + + ret = USBDeviceAttachToBus(USB_DEVICE_NAME, USB_BUS_NAME); + if (EOK != ret) { + KPrintf("board_usb_init USBDeviceAttachToBus device %s error %d\n", USB_DEVICE_NAME, ret); + return ERROR; + } + + return ret; +} + +/*ARM-32 BOARD USB INIT*/ +int Stm32HwUsbInit(void) +{ + x_err_t ret = EOK; + static struct UsbBus usb_bus; + memset(&usb_bus, 0, sizeof(struct UsbBus)); + + static struct UsbDriver usb_driver; + memset(&usb_driver, 0, sizeof(struct UsbDriver)); + + ret = BoardUsbBusInit(&usb_bus, &usb_driver); + if (EOK != ret) { + KPrintf("board_usb_Init error ret %u\n", ret); + return ERROR; + } + + ret = BoardUsbDevBend(); + if (EOK != ret) { + KPrintf("board_usb_Init error ret %u\n", ret); + return ERROR; + } + + return ret; +} diff --git a/Ubiquitous/XiZi/board/aiit-arm32-board/third_party_driver/watchdog/Kconfig b/Ubiquitous/XiZi/board/aiit-arm32-board/third_party_driver/watchdog/Kconfig new file mode 100644 index 0000000..59a4443 --- /dev/null +++ b/Ubiquitous/XiZi/board/aiit-arm32-board/third_party_driver/watchdog/Kconfig @@ -0,0 +1,14 @@ + +if BSP_USING_WDT +config WDT_BUS_NAME + string "watchdog bus name" + default "wdt" + +config WDT_DRIVER_NAME + string "watchdog driver name" + default "wdt_drv" + +config WDT_DEVICE_NAME + string "watchdog device name" + default "wdt_dev" +endif diff --git a/Ubiquitous/XiZi/board/aiit-arm32-board/third_party_driver/watchdog/Makefile b/Ubiquitous/XiZi/board/aiit-arm32-board/third_party_driver/watchdog/Makefile new file mode 100644 index 0000000..e141d69 --- /dev/null +++ b/Ubiquitous/XiZi/board/aiit-arm32-board/third_party_driver/watchdog/Makefile @@ -0,0 +1,5 @@ +SRC_FILES := hardware_wdg.c connect_wdg.c + + + +include $(KERNEL_ROOT)/compiler.mk diff --git a/Ubiquitous/XiZi/board/aiit-arm32-board/third_party_driver/watchdog/connect_wdg.c b/Ubiquitous/XiZi/board/aiit-arm32-board/third_party_driver/watchdog/connect_wdg.c new file mode 100644 index 0000000..07fac14 --- /dev/null +++ b/Ubiquitous/XiZi/board/aiit-arm32-board/third_party_driver/watchdog/connect_wdg.c @@ -0,0 +1,133 @@ +/* +* Copyright (c) 2020 AIIT XUOS Lab +* XiUOS is licensed under Mulan PSL v2. +* You can use this software according to the terms and conditions of the Mulan PSL v2. +* You may obtain a copy of Mulan PSL v2 at: +* http://license.coscl.org.cn/MulanPSL2 +* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, +* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, +* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. +* See the Mulan PSL v2 for more details. +*/ + +/** +* @file connect_wdt.c +* @brief support aiit-arm32-board watchdog function and register to bus framework +* @version 1.0 +* @author AIIT XUOS Lab +* @date 2021-04-25 +*/ + +#include +#include + +/** + * This function Watchdog configuration function + * + * @param arg Watchdog device Parameters + * + * @return EOK + */ +static int WdgSet(uint16_t arg) +{ + IWDG_Enable(); + IWDG_WriteAccessCmd(IWDG_WriteAccess_Enable); + IWDG_SetPrescaler(IWDG_Prescaler_16); + IWDG_SetReload(arg); + while(IWDG_GetFlagStatus(IWDG_FLAG_RVU) != RESET); + IWDG_ReloadCounter(); + return 0; +} + +/** + * This function Watchdog initialization + * + * @param dev Watchdog driver structure handle + * + * @return EOK + */ +static uint32 WdtOpen(void *dev) +{ + WdgSet(4000); + return EOK; +} + +/** + * This function Watchdog control function + * + * @param drv Watchdog driver structure handle + * + * @param args Watchdog driver Parameters + * + * @return EOK + */ +static uint32 WdtConfigure(void *drv, struct BusConfigureInfo *args) +{ + switch (args->configure_cmd) + { + case OPER_WDT_SET_TIMEOUT: + if (WdgSet((uint16_t)*(int *)args->private_data) != 0) { + return ERROR; + } + break; + case OPER_WDT_KEEPALIVE: + IWDG_ReloadCounter(); + break; + default: + return ERROR; + } + return EOK; +} + +static const struct WdtDevDone dev_done = +{ + WdtOpen, + NONE, + NONE, + NONE, +}; + +/** + * This function Watchdog initialization + * + * @return EOK + */ +int HwWdtInit(void) +{ + x_err_t ret = EOK; + + static struct WdtBus wdt; + static struct WdtDriver drv; + static struct WdtHardwareDevice dev; + + ret = WdtBusInit(&wdt, WDT_BUS_NAME); + if (ret != EOK) { + KPrintf("Watchdog bus init error %d\n", ret); + return ERROR; + } + + drv.configure = WdtConfigure; + ret = WdtDriverInit(&drv, WDT_DRIVER_NAME); + if (ret != EOK) { + KPrintf("Watchdog driver init error %d\n", ret); + return ERROR; + } + ret = WdtDriverAttachToBus(WDT_DRIVER_NAME, WDT_BUS_NAME); + if (ret != EOK) { + KPrintf("Watchdog driver attach error %d\n", ret); + return ERROR; + } + + dev.dev_done = &dev_done; + + ret = WdtDeviceRegister(&dev, WDT_DEVICE_NAME); + if (ret != EOK) { + KPrintf("Watchdog device register error %d\n", ret); + return ERROR; + } + ret = WdtDeviceAttachToBus(WDT_DEVICE_NAME, WDT_BUS_NAME); + if (ret != EOK) { + KPrintf("Watchdog device register error %d\n", ret); + return ERROR; + } +} diff --git a/Ubiquitous/XiZi/board/aiit-riscv64-board/.defconfig b/Ubiquitous/XiZi/board/aiit-riscv64-board/.defconfig new file mode 100644 index 0000000..ed74228 --- /dev/null +++ b/Ubiquitous/XiZi/board/aiit-riscv64-board/.defconfig @@ -0,0 +1,268 @@ +# +# Automatically generated file; DO NOT EDIT. +# XiZi Project Configuration +# +CONFIG_BOARD_AIIT_RISCV_EVB=y +CONFIG_KERNEL_CONSOLE_DEVICE_NAME="uarths" +CONFIG_ARCH_CPU_64BIT=y +CONFIG_ARCH_RISCV=y +CONFIG_ARCH_RISCV64=y + +# +# aiit-riscv64-board feature +# +# CONFIG_BSP_USING_AUDIO is not set +# CONFIG_BSP_USING_CAMERA is not set +# CONFIG_BSP_USING_SDIO is not set +CONFIG_BSP_USING_CH438=y +CONFIG_BSP_CH438_ALE_PIN=23 +CONFIG_BSP_CH438_NWR_PIN=24 +CONFIG_BSP_CH438_NRD_PIN=25 +CONFIG_BSP_CH438_D0_PIN=27 +CONFIG_BSP_CH438_D1_PIN=28 +CONFIG_BSP_CH438_D2_PIN=29 +CONFIG_BSP_CH438_D3_PIN=30 +CONFIG_BSP_CH438_D4_PIN=31 +CONFIG_BSP_CH438_D5_PIN=32 +CONFIG_BSP_CH438_D6_PIN=33 +CONFIG_BSP_CH438_D7_PIN=34 +CONFIG_BSP_CH438_INT_PIN=35 +CONFIG_BSP_485_dir=18 +CONFIG_BSP_USING_DMA=y +CONFIG_BSP_USING_GPIO=y +# CONFIG_BSP_USING_I2C is not set +# CONFIG_BSP_I2C_SDA is not set +# CONFIG_BSP_I2C_SCL is not set +# CONFIG_BSP_USING_I2S is not set +# CONFIG_BSP_USING_LCD is not set +# CONFIG_BSP_USING_RTC is not set +# CONFIG_BSP_USING_SECURITY is not set +# CONFIG_BSP_USING_SPI is not set +CONFIG_BSP_USING_HWTIMER=n +CONFIG_BSP_USING_TIMER0=y +CONFIG_BSP_USING_TIMER1=y +CONFIG_BSP_USING_TIMER2=y +# CONFIG_BSP_USING_TOUCH is not set +CONFIG_BSP_USING_UART=y +CONFIG_BSP_USING_UART_HS=y +# CONFIG_BSP_USING_VIDEO is not set +CONFIG_BSP_USING_WDT=y +CONFIG_BSP_CONFIG_WDT0=y +# CONFIG_BSP_CONFIG_WDT1 is not set + +# +# General Purpose UARTs +# +CONFIG_BSP_USING_CH376=y +CONFIG_BSP_CH376_TXD=19 +CONFIG_BSP_CH376_RXD=20 + +# +# General Purpose UARTs +# +CONFIG_BSP_USING_UART2=y +CONFIG_BSP_UART2_TXD_PIN=20 +CONFIG_BSP_UART2_RXD_PIN=19 +CONFIG_BSP_USING_UART3=y +CONFIG_BSP_UART3_TXD_PIN=22 +CONFIG_BSP_UART3_RXD_PIN=23 + +CONFIG_BSP_USING_4G_OR_NB=y +CONFIG_BSP_USING_4G=y +# CONFIG_BSP_USING_NBIOT is not set +CONFIG_BSP_4G_STATUS=21 +CONFIG_BSP_4G_POWERKEY=37 +CONFIG_BSP_USING_WIFI_HFA21=y +CONFIG_BSP_WIFI_RST=22 + +CONFIG___STACKSIZE__=4096 + +# +# Hardware feature +# +CONFIG_RESOURCES_SERIAL=y +# CONFIG_SERIAL_USING_DMA is not set +# CONFIG_SERIAL_RB_BUFSZ is not set +# CONFIG_RESOURCES_HWTIMER is not set +# CONFIG_RESOURCES_CAN is not set +# CONFIG_RESOURCES_I2C is not set +# CONFIG_RESOURCES_LCD is not set +# CONFIG_RESOURCES_SDIO is not set +# CONFIG_RESOURCES_TOUCH is not set +CONFIG_RESOURCES_PIN=y +CONFIG_RESOURCES_RTC=y +# CONFIG_RESOURCES_SPI is not set +# CONFIG_RESOURCES_SPI_SD is not set +# CONFIG_RESOURCES_SPI_SFUD is not set +# SFUD_USING_SFDP is not set +# SFUD_USING_FLASH_INFO_TABLE is not set +# SFUD_DEBUG_LOG is not set +CONFIG_RESOURCES_WDT=y +# CONFIG_RESOURCES_USB is not set +# CONFIG_RESOURCES_USB_HOST is not set +# CONFIG_UDISK_MOUNTPOINT is not set +# CONFIG_USBH_MSTORAGE is not set +# CONFIG_RESOURCES_USB_DEVICE is not set +# CONFIG_USBD_THREAD_STACK_SZ is not set + +# +# Kernel feature +# +# CONFIG_SEPARATE_COMPILE is not set +# CONFIG_COMPILER_APP is not set +# CONFIG_COMPILER_KERNEL is not set +# +# Kernel Device Object +# +CONFIG_KERNEL_DEVICE=y +CONFIG_KERNEL_CONSOLE=y +CONFIG_KERNEL_CONSOLEBUF_SIZE=128 + +# +# Task feature +# +CONFIG_SCHED_POLICY_RR_REMAINSLICE=y +# CONFIG_SCHED_POLICY_RR is not set +# CONFIG_SCHED_POLICY_FIFO is not set + +# +# Inter-Task communication +# +CONFIG_KERNEL_SEMAPHORE=y +CONFIG_KERNEL_MUTEX=y +CONFIG_KERNEL_EVENT=y +CONFIG_KERNEL_MESSAGEQUEUE=y +# CONFIG_KTASK_PRIORITY_8 is not set +CONFIG_KTASK_PRIORITY_32=y +# CONFIG_KTASK_PRIORITY_256 is not set +CONFIG_KTASK_PRIORITY_MAX=32 +CONFIG_TICK_PER_SECOND=100 +CONFIG_KERNEL_STACK_OVERFLOW_CHECK=y +CONFIG_KERNEL_BANNER=y +# CONFIG_KERNEL_HOOK is not set +CONFIG_KERNEL_SOFTTIMER=y +CONFIG_KERNEL_IDLE_HOOK=y +CONFIG_IDEL_HOOK_LIST_SIZE=4 +CONFIG_IDLE_KTASK_STACKSIZE=1024 +CONFIG_USER_APPLICATION=y +# CONFIG_TASK_ISOLATION is not set + +# +# Memory Management +# +# CONFIG_KERNEL_MEMBLOCK is not set + +# +# Command shell +# +CONFIG_TOOL_SHELL=y +CONFIG_SHELL_ENTER_CR=y +CONFIG_SHELL_ENTER_LF=y +CONFIG_SHELL_ENTER_CR_AND_LF=y +# CONFIG_SHELL_ENTER_CRLF is not set + +# +# User Control +# +CONFIG_SHELL_DEFAULT_USER="letter" +CONFIG_SHELL_DEFAULT_USER_PASSWORD="" +CONFIG_SHELL_LOCK_TIMEOUT=10000 +CONFIG_SHELL_TASK_STACK_SIZE=4096 +CONFIG_SHELL_TASK_PRIORITY=20 +CONFIG_SHELL_MAX_NUMBER=5 +CONFIG_SHELL_PARAMETER_MAX_NUMBER=8 +CONFIG_SHELL_HISTORY_MAX_NUMBER=5 +CONFIG_SHELL_PRINT_BUFFER=128 +CONFIG_SHELL_USING_CMD_EXPORT=y +CONFIG_SHELL_HELP_SHOW_PERMISSION=y +# CONFIG_SHELL_HELP_LIST_USER is not set +# CONFIG_SHELL_HELP_LIST_VAR is not set +# CONFIG_SHELL_HELP_LIST_KEY is not set +CONFIG_KERNEL_QUEUEMANAGE=y +CONFIG_KERNEL_WORKQUEUE=y +CONFIG_WORKQUEUE_KTASK_STACKSIZE=512 +CONFIG_WORKQUEUE_KTASK_PRIORITY=23 +CONFIG_KERNEL_WAITQUEUE=y +CONFIG_KERNEL_DATAQUEUE=y +# CONFIG_KERNEL_CIRCULAR_AREA is not set +# CONFIG_KERNEL_AVL_TREE is not set +CONFIG_NAME_MAX=32 +CONFIG_ALIGN_SIZE=8 +CONFIG_KERNEL_COMPONENTS_INIT=y +CONFIG_KERNEL_USER_MAIN=y +CONFIG_MAIN_KTASK_STACK_SIZE=2048 +CONFIG_ENV_INIT_KTASK_STACK_SIZE=8192 +CONFIG_MAIN_KTASK_PRIORITY=10 +# CONFIG_USER_TEST is not set +# CONFIG_TOOL_TEST_SEM is not set +# CONFIG_TOOL_TEST_MUTEX is not set +# CONFIG_TOOL_TEST_EVENT is not set +# CONFIG_TOOL_TEST_MSG is not set +# CONFIG_TOOL_TEST_AVLTREE is not set +# CONFIG_TEST_CRICULAR_AREA is not set +# CONFIG_TOOL_TEST_MEM is not set +# CONFIG_TOOL_TEST_TIMER is not set +# CONFIG_TOOL_TEST_IWG is not set +# CONFIG_TOOL_TEST_REALTIME is not set +# CONFIG_TOOL_TEST_DBG is not set +# CONFIG_TOOL_TEST_SCHED is not set +# CONFIG_KERNEL_DEBUG is not set +CONFIG_DEBUG_INIT_CONFIG=y +CONFIG_DBG_INIT=1 +CONFIG_ARCH_SMP=y +CONFIG_CPUS_NR=2 + +# +# File system +# +CONFIG_FS_VFS=y +CONFIG_VFS_USING_WORKDIR=y +CONFIG_FS_VFS_DEVFS=y + +# +# Fat filesystem +# + +# +# IOT-Device File system +# + +# +# Lwext4 filesystem +# + +# +# APP Framework +# + +# +# connection +# +# CONFIG_CONNECTION_AT is not set +# CONFIG_CONNECTION_MQTT is not set + +# +# medium communication +# + + +# +# Intelligence +# + +# +# Control +# + +# +# Lib +# +CONFIG_LIB=y +CONFIG_LIB_POSIX=y +CONFIG_LIB_NEWLIB=y + +CONFIG_LITTLEVGL2RTT_USING_DEMO=y + +# +# Security +# diff --git a/Ubiquitous/XiZi/board/aiit-riscv64-board/Kconfig b/Ubiquitous/XiZi/board/aiit-riscv64-board/Kconfig new file mode 100644 index 0000000..babb6de --- /dev/null +++ b/Ubiquitous/XiZi/board/aiit-riscv64-board/Kconfig @@ -0,0 +1,85 @@ +mainmenu "XiZi Project Configuration" + +config BSP_DIR + string + option env="BSP_ROOT" + default "." + +config KERNEL_DIR + string + option env="KERNEL_ROOT" + default "../.." + +config BOARD_AIIT_RISCV_EVB + bool + select ARCH_RISCV + select ARCH_RISCV64 + select ARCH_CPU_64BIT + default y + +source "$KERNEL_DIR/arch/Kconfig" + +menu "aiit-riscv64-board feature" + source "$BSP_DIR/third_party_driver/Kconfig" + + menu "config default board resources" + menu "config board app name" + config BOARD_APP_NAME + string "config board app name" + default "/XiUOS_aiit-riscv64-board_app.bin" + endmenu + + menu "config board service table" + config SERVICE_TABLE_ADDRESS + hex "board service table address" + default 0x80100000 + endmenu + + menu "config hardware resources for connection" + if CONNECTION_COMMUNICATION_ETHERNET + config ETHERNET_UART_NAME + string "ethernet uart name" + default "/dev/uart3_dev3" + endif + if CONNECTION_COMMUNICATION_WIFI + config WIFI_UART_NAME + string "wifi uart name" + default "/dev/uart3_dev3" + endif + if CONNECTION_COMMUNICATION_LORA + config LORA_SPI_NAME + string "lora spi name" + default "/dev/spi1_lora" + endif + endmenu + + menu "config board peripheral" + config MOUNT_SDCARD + bool "mount cd card" + default n + select BSP_USING_SDIO + config MOUNT_USB + bool "mount usb" + default n + select BSP_USING_USB + endmenu + + endmenu + + config __STACKSIZE__ + int "stack size for interrupt" + default 4096 + +endmenu + + + + + +menu "Hardware feature" +source "$KERNEL_DIR/resources/Kconfig" +endmenu + +source "$KERNEL_DIR/Kconfig" + + diff --git a/Ubiquitous/XiZi/board/aiit-riscv64-board/Makefile b/Ubiquitous/XiZi/board/aiit-riscv64-board/Makefile new file mode 100644 index 0000000..12f4148 --- /dev/null +++ b/Ubiquitous/XiZi/board/aiit-riscv64-board/Makefile @@ -0,0 +1,6 @@ +SRC_FILES := board.c + +SRC_DIR := third_party_driver + + +include $(KERNEL_ROOT)/compiler.mk diff --git a/Ubiquitous/XiZi/board/aiit-riscv64-board/README.md b/Ubiquitous/XiZi/board/aiit-riscv64-board/README.md new file mode 100644 index 0000000..dc5aef2 --- /dev/null +++ b/Ubiquitous/XiZi/board/aiit-riscv64-board/README.md @@ -0,0 +1,73 @@ +# aiit-riscv64-board README + +## 1. 简介 + +| 硬件 | 描述 | +| -- | -- | +|芯片型号| K210 | +|CPU| 双核RV64GC | +|主频| 400MHz | +|片内SRAM| 8MB | +| 外设 | 内嵌AES与SHA256算法加速器 | +| | DVP、JTAG、OTP、FPIOA、GPIO、UART、SPI、RTC、I²S、I²C、WDT、Timer与PWM | + +XiUOS板级当前支持使用CH438、CH376、GPIO、I2C、LCD、RTC、SPI、Timer、UART和watchdog等。 + +## 2. 编译说明 + +编译环境：Ubuntu18.04 + +编译工具链：[riscv-none-embed-gcc](https://github.com/ilg-archived/riscv-none-gcc/releases) + +编译步骤： + +>1.将编译工具链的路径添加到board/aiit-riscv64-board/config.mk文件当中，例如将gnu-mcu-eclipse-riscv-none-gcc-8.2.0-2.1-20190425-1021-centos64.tgz解压到/opt/下时添加： +``` +export CROSS_COMPILE ?=/opt/gnu-mcu-eclipse/riscv-none-gcc/8.2.0-2.1-20190425-1021/bin/riscv-none-embed- +``` +>2.在代码根目录下执行以下命令，生成配置文件 +``` +cd ./Ubiquitous/XiZi +make BOARD=aiit-riscv64-board distclean +make BOARD=aiit-riscv64-board menuconfig +``` +>3.在menuconfig界面配置需要关闭和开启的功能，按回车键进入下级菜单，按Y键选中需要开启的功能，按N键选中需要关闭的功能，配置结束后选择Exit保存并退出 +>4.继续执行以下命令，进行编译 +``` +make BOARD=aiit-riscv64-board +``` +>5.如果编译正确无误，会产生XiZi_aiit-riscv64-board.elf、XiZi_aiit-riscv64-board.bin文件。其中XiZi_aiit-riscv64-board.bin需要烧写到设备中进行运行。 +>注：最后可以执行以下命令，清除配置文件和编译生成的文件 +``` +make BOARD=aiit-riscv64-board distclean +``` + +## 3. 烧写及执行 + +将开发板通过串口转USB模块连接到USB接口，开发板VCC悬空，TX连接模块RX，RX连接模块TX，GND连接模块GND，再将开发板BOOT引脚和GND引脚短接，最后将开发板电源上电，然后使用K-Flash工具进行烧写bin文件。 + +![aiit_riscv64_board](img/aiit_riscv64_board.png) + +执行以下命令安装K-Flash工具 +``` +sudo apt install python3 python3-pip +sudo pip3 install pyserial +sudo pip3 install pyelftools +sudo pip3 install kflash +``` +如果最后一步安装kflash出现错误，可以尝试以下命令 +``` +sudo python -m pip install kflash +sudo python3 -m pip install kflash +sudo pip install kflash +sudo pip2 install kflash +``` +代码根目录下执行K-Flash工具烧录，-p为USB端口号，视实际情况而定 +``` +kflash -t build/XiZi_aiit-riscv64-board.bin -p /dev/ttyUSB0 +``` +### 3.1 运行结果 + +如果编译 & 烧写无误，将开发板BOOT引脚与GND引脚断开后重新上电或将RESET引脚短接一下，将会在串口终端上看到信息打印输出。 + +![terminal](img/terminal.png) \ No newline at end of file diff --git a/Ubiquitous/XiZi/board/aiit-riscv64-board/config.mk b/Ubiquitous/XiZi/board/aiit-riscv64-board/config.mk new file mode 100644 index 0000000..f20436f --- /dev/null +++ b/Ubiquitous/XiZi/board/aiit-riscv64-board/config.mk @@ -0,0 +1,17 @@ +export CFLAGS := -mcmodel=medany -march=rv64imafdc -mabi=lp64d -fno-common -ffunction-sections -fdata-sections -fstrict-volatile-bitfields -O0 -ggdb -fgnu89-inline -Werror +export AFLAGS := -c -mcmodel=medany -march=rv64imafdc -mabi=lp64d -x assembler-with-cpp -ggdb +export LFLAGS := -mcmodel=medany -march=rv64imafdc -mabi=lp64d -nostartfiles -Wl,--gc-sections,-Map=XiZi.map,-cref,-u,_start -T $(BSP_ROOT)/link.lds + +export APPLFLAGS := -mcmodel=medany -march=rv64imafdc -mabi=lp64d -nostartfiles -Wl,--gc-sections,-Map=XiZi_app.map,-cref,-u, -T $(BSP_ROOT)/link_userspace.lds + +export CXXFLAGS := -mcmodel=medany -march=rv64imafdc -mabi=lp64d -fno-common -ffunction-sections -fdata-sections -fstrict-volatile-bitfields -O0 -ggdb -Werror + +export CROSS_COMPILE ?=/opt/gnu-mcu-eclipse/riscv-none-gcc/8.2.0-2.1-20190425-1021/bin/riscv-none-embed- +#export CROSS_COMPILE ?=/opt/xpack-riscv-none-embed-gcc-10.1.0-1.1/bin/riscv-none-embed- +export DEFINES := -DHAVE_CCONFIG_H -DHAVE_SIGINFO + + +export ARCH = risc-v +export MCU = k210 + +export USING_LORA = 1 diff --git a/Ubiquitous/XiZi/board/aiit-riscv64-board/img/aiit_riscv64_board.png b/Ubiquitous/XiZi/board/aiit-riscv64-board/img/aiit_riscv64_board.png new file mode 100644 index 0000000..15557a6 Binary files /dev/null and b/Ubiquitous/XiZi/board/aiit-riscv64-board/img/aiit_riscv64_board.png differ diff --git a/Ubiquitous/XiZi/board/aiit-riscv64-board/img/terminal.png b/Ubiquitous/XiZi/board/aiit-riscv64-board/img/terminal.png new file mode 100644 index 0000000..7921e29 Binary files /dev/null and b/Ubiquitous/XiZi/board/aiit-riscv64-board/img/terminal.png differ diff --git a/Ubiquitous/XiZi/board/aiit-riscv64-board/include/atomic.h b/Ubiquitous/XiZi/board/aiit-riscv64-board/include/atomic.h new file mode 100644 index 0000000..fc13ddf --- /dev/null +++ b/Ubiquitous/XiZi/board/aiit-riscv64-board/include/atomic.h @@ -0,0 +1,254 @@ + +/* Copyright 2018 Canaan Inc. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/** +* @file atomic.h +* @brief add from Canaan K210 SDK +* https://canaan-creative.com/developer +* @version 1.0 +* @author AIIT XUOS Lab +* @date 2021-04-25 +*/ + +#ifndef _BSP_ATOMIC_H +#define _BSP_ATOMIC_H + +#ifdef __cplusplus +extern "C" { +#endif + + +#define SPINLOCK_INIT \ + { \ + 0 \ + } + +#define CORELOCK_INIT \ + { \ + .lock = SPINLOCK_INIT, \ + .count = 0, \ + .core = -1 \ + } + + +/* Defination of memory barrier macro */ +#define mb() \ + { \ + asm volatile("fence" :: \ + : "memory"); \ + } + +#define atomic_set(ptr, val) (*(volatile typeof(*(ptr))*)(ptr) = val) +#define atomic_read(ptr) (*(volatile typeof(*(ptr))*)(ptr)) + +#ifndef __riscv_atomic +#error "atomic extension is required." +#endif +#define atomic_add(ptr, inc) __sync_fetch_and_add(ptr, inc) +#define atomic_or(ptr, inc) __sync_fetch_and_or(ptr, inc) +#define atomic_swap(ptr, swp) __sync_lock_test_and_set(ptr, swp) +#define atomic_cas(ptr, cmp, swp) __sync_val_compare_and_swap(ptr, cmp, swp) + +typedef struct _spinlock +{ + int lock; +} spinlock_t; + +typedef struct _semaphore +{ + spinlock_t lock; + int count; + int waiting; +} semaphore_t; + + +typedef struct _corelock +{ + spinlock_t lock; + int count; + int core; +} corelock_t; + +static inline int spinlock_trylock(spinlock_t *lock) +{ + int res = atomic_swap(&lock->lock, -1); + /* Use memory barrier to keep coherency */ + mb(); + return res; +} + +static inline void spinlock_lock(spinlock_t *lock) +{ + while (spinlock_trylock(lock)); +} + +static inline void spinlock_unlock(spinlock_t *lock) +{ + /* Use memory barrier to keep coherency */ + mb(); + atomic_set(&lock->lock, 0); + asm volatile ("nop"); +} + +static inline void semaphore_signal(semaphore_t *semaphore, int i) +{ + spinlock_lock(&(semaphore->lock)); + semaphore->count += i; + spinlock_unlock(&(semaphore->lock)); +} + +static inline void semaphore_wait(semaphore_t *semaphore, int i) +{ + atomic_add(&(semaphore->waiting), 1); + while (1) + { + spinlock_lock(&(semaphore->lock)); + if (semaphore->count >= i) + { + semaphore->count -= i; + atomic_add(&(semaphore->waiting), -1); + spinlock_unlock(&(semaphore->lock)); + break; + } + spinlock_unlock(&(semaphore->lock)); + } +} + +static inline int semaphore_count(semaphore_t *semaphore) +{ + int res = 0; + + spinlock_lock(&(semaphore->lock)); + res = semaphore->count; + spinlock_unlock(&(semaphore->lock)); + return res; +} + +static inline int semaphore_waiting(semaphore_t *semaphore) +{ + return atomic_read(&(semaphore->waiting)); +} + +static inline int corelock_trylock(corelock_t *lock) +{ + int res = 0; + unsigned long core; + + asm volatile("csrr %0, mhartid;" + : "=r"(core)); + if(spinlock_trylock(&lock->lock)) + { + return -1; + } + + if (lock->count == 0) + { + /* First time get lock */ + lock->count++; + lock->core = core; + res = 0; + } + else if (lock->core == core) + { + /* Same core get lock */ + lock->count++; + res = 0; + } + else + { + /* Different core get lock */ + res = -1; + } + spinlock_unlock(&lock->lock); + + return res; +} + +static inline void corelock_lock(corelock_t *lock) +{ + unsigned long core; + + asm volatile("csrr %0, mhartid;" + : "=r"(core)); + spinlock_lock(&lock->lock); + + if (lock->count == 0) + { + /* First time get lock */ + lock->count++; + lock->core = core; + } + else if (lock->core == core) + { + /* Same core get lock */ + lock->count++; + } + else + { + /* Different core get lock */ + spinlock_unlock(&lock->lock); + + do + { + while (atomic_read(&lock->count)) + ; + } while (corelock_trylock(lock)); + return; + } + spinlock_unlock(&lock->lock); +} + +static inline void corelock_unlock(corelock_t *lock) +{ + unsigned long core; + + asm volatile("csrr %0, mhartid;" + : "=r"(core)); + spinlock_lock(&lock->lock); + + if (lock->core == core) + { + /* Same core release lock */ + lock->count--; + if (lock->count <= 0) + { + lock->core = -1; + lock->count = 0; + } + } + else + { + /* Different core release lock */ + spinlock_unlock(&lock->lock); + + register unsigned long a7 asm("a7") = 93; + register unsigned long a0 asm("a0") = 0; + register unsigned long a1 asm("a1") = 0; + register unsigned long a2 asm("a2") = 0; + + asm volatile("scall" + : "+r"(a0) + : "r"(a1), "r"(a2), "r"(a7)); + } + spinlock_unlock(&lock->lock); +} + +#ifdef __cplusplus +} +#endif + +#endif /* _BSP_ATOMIC_H */ + diff --git a/Ubiquitous/XiZi/board/aiit-riscv64-board/include/bsp.h b/Ubiquitous/XiZi/board/aiit-riscv64-board/include/bsp.h new file mode 100644 index 0000000..ea1e7bc --- /dev/null +++ b/Ubiquitous/XiZi/board/aiit-riscv64-board/include/bsp.h @@ -0,0 +1,31 @@ +/* Copyright 2018 Canaan Inc. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/** +* @file bsp.h +* @brief add from Canaan K210 SDK +* https://canaan-creative.com/developer +* @version 1.0 +* @author AIIT XUOS Lab +* @date 2021-04-25 +*/ + +#ifndef _KENDRYTE_BSP_H +#define _KENDRYTE_BSP_H +#include "atomic.h" +#include "entry.h" +#include "sleep.h" +#include "encoding.h" +#endif \ No newline at end of file diff --git a/Ubiquitous/XiZi/board/aiit-riscv64-board/include/dump.h b/Ubiquitous/XiZi/board/aiit-riscv64-board/include/dump.h new file mode 100644 index 0000000..8da4c22 --- /dev/null +++ b/Ubiquitous/XiZi/board/aiit-riscv64-board/include/dump.h @@ -0,0 +1,150 @@ +/* Copyright 2018 Canaan Inc. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/** +* @file dump.h +* @brief add from Canaan K210 SDK +* https://canaan-creative.com/developer +* @version 1.0 +* @author AIIT XUOS Lab +* @date 2021-04-25 +*/ + +#ifndef _BSP_DUMP_H +#define _BSP_DUMP_H + +#include +#include +#include "syslog.h" +#include "hardware_uarths.h" + +#ifdef __cplusplus +extern "C" { +#endif + +#define DUMP_PRINTF printk + +static inline void +dump_core(const char *reason, uintptr_t cause, uintptr_t epc, uintptr_t regs[32], uintptr_t fregs[32]) +{ + static const char *const reg_usage[][2] = + { + {"zero ", "Hard-wired zero"}, + {"ra ", "Return address"}, + {"sp ", "Stack pointer"}, + {"gp ", "Global pointer"}, + {"tp ", "Task pointer"}, + {"t0 ", "Temporaries Caller"}, + {"t1 ", "Temporaries Caller"}, + {"t2 ", "Temporaries Caller"}, + {"s0/fp", "Saved register/frame pointer"}, + {"s1 ", "Saved register"}, + {"a0 ", "Function arguments/return values"}, + {"a1 ", "Function arguments/return values"}, + {"a2 ", "Function arguments values"}, + {"a3 ", "Function arguments values"}, + {"a4 ", "Function arguments values"}, + {"a5 ", "Function arguments values"}, + {"a6 ", "Function arguments values"}, + {"a7 ", "Function arguments values"}, + {"s2 ", "Saved registers"}, + {"s3 ", "Saved registers"}, + {"s4 ", "Saved registers"}, + {"s5 ", "Saved registers"}, + {"s6 ", "Saved registers"}, + {"s7 ", "Saved registers"}, + {"s8 ", "Saved registers"}, + {"s9 ", "Saved registers"}, + {"s10 ", "Saved registers"}, + {"s11 ", "Saved registers"}, + {"t3 ", "Temporaries Caller"}, + {"t4 ", "Temporaries Caller"}, + {"t5 ", "Temporaries Caller"}, + {"t6 ", "Temporaries Caller"}, + }; + + static const char *const regf_usage[][2] = + { + {"ft0 ", "FP temporaries"}, + {"ft1 ", "FP temporaries"}, + {"ft2 ", "FP temporaries"}, + {"ft3 ", "FP temporaries"}, + {"ft4 ", "FP temporaries"}, + {"ft5 ", "FP temporaries"}, + {"ft6 ", "FP temporaries"}, + {"ft7 ", "FP temporaries"}, + {"fs0 ", "FP saved registers"}, + {"fs1 ", "FP saved registers"}, + {"fa0 ", "FP arguments/return values"}, + {"fa1 ", "FP arguments/return values"}, + {"fa2 ", "FP arguments values"}, + {"fa3 ", "FP arguments values"}, + {"fa4 ", "FP arguments values"}, + {"fa5 ", "FP arguments values"}, + {"fa6 ", "FP arguments values"}, + {"fa7 ", "FP arguments values"}, + {"fs2 ", "FP Saved registers"}, + {"fs3 ", "FP Saved registers"}, + {"fs4 ", "FP Saved registers"}, + {"fs5 ", "FP Saved registers"}, + {"fs6 ", "FP Saved registers"}, + {"fs7 ", "FP Saved registers"}, + {"fs8 ", "FP Saved registers"}, + {"fs9 ", "FP Saved registers"}, + {"fs10", "FP Saved registers"}, + {"fs11", "FP Saved registers"}, + {"ft8 ", "FP Temporaries Caller"}, + {"ft9 ", "FP Temporaries Caller"}, + {"ft10", "FP Temporaries Caller"}, + {"ft11", "FP Temporaries Caller"}, + }; + + if (CONFIG_LOG_LEVEL >= LOG_ERROR) + { + const char unknown_reason[] = "unknown"; + + if (!reason) + reason = unknown_reason; + + DUMP_PRINTF("core dump: %s\r\n", reason); + DUMP_PRINTF("Cause 0x%016lx, EPC 0x%016lx\r\n", cause, epc); + + int i = 0; + for (i = 0; i < 32 / 2; i++) + { + DUMP_PRINTF( + "reg[%02d](%s) = 0x%016lx, reg[%02d](%s) = 0x%016lx\r\n", + i * 2, reg_usage[i * 2][0], regs[i * 2], + i * 2 + 1, reg_usage[i * 2 + 1][0], regs[i * 2 + 1]); + } + + for (i = 0; i < 32 / 2; i++) + { + DUMP_PRINTF( + "freg[%02d](%s) = 0x%016lx(%f), freg[%02d](%s) = 0x%016lx(%f)\r\n", + i * 2, regf_usage[i * 2][0], fregs[i * 2], (float)fregs[i * 2], + i * 2 + 1, regf_usage[i * 2 + 1][0], fregs[i * 2 + 1], (float)fregs[i * 2 + 1]); + } + } +} + +#undef DUMP_PRINTF + +#ifdef __cplusplus +} +#endif + +#endif /* _BSP_DUMP_H */ + diff --git a/Ubiquitous/XiZi/board/aiit-riscv64-board/include/encoding.h b/Ubiquitous/XiZi/board/aiit-riscv64-board/include/encoding.h new file mode 100644 index 0000000..6a5f1a6 --- /dev/null +++ b/Ubiquitous/XiZi/board/aiit-riscv64-board/include/encoding.h @@ -0,0 +1,1336 @@ +/* Copyright 2018 Canaan Inc. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/** +* @file encoding.h +* @brief add from Canaan K210 SDK +* https://canaan-creative.com/developer +* @version 1.0 +* @author AIIT XUOS Lab +* @date 2021-04-25 +*/ + +#ifndef RISCV_CSR_ENCODING_H +#define RISCV_CSR_ENCODING_H + +#define MSTATUS_UIE 0x00000001U +#define MSTATUS_SIE 0x00000002U +#define MSTATUS_HIE 0x00000004U +#define MSTATUS_MIE 0x00000008U +#define MSTATUS_UPIE 0x00000010U +#define MSTATUS_SPIE 0x00000020U +#define MSTATUS_HPIE 0x00000040U +#define MSTATUS_MPIE 0x00000080U +#define MSTATUS_SPP 0x00000100U +#define MSTATUS_HPP 0x00000600U +#define MSTATUS_MPP 0x00001800U +#define MSTATUS_FS 0x00006000U +#define MSTATUS_XS 0x00018000U +#define MSTATUS_MPRV 0x00020000U +#define MSTATUS_PUM 0x00040000U +#define MSTATUS_MXR 0x00080000U +#define MSTATUS_VM 0x1F000000U +#define MSTATUS32_SD 0x80000000U +#define MSTATUS64_SD 0x8000000000000000U + +#define SSTATUS_UIE 0x00000001U +#define SSTATUS_SIE 0x00000002U +#define SSTATUS_UPIE 0x00000010U +#define SSTATUS_SPIE 0x00000020U +#define SSTATUS_SPP 0x00000100U +#define SSTATUS_FS 0x00006000U +#define SSTATUS_XS 0x00018000U +#define SSTATUS_PUM 0x00040000U +#define SSTATUS32_SD 0x80000000U +#define SSTATUS64_SD 0x8000000000000000U + +#define DCSR_XDEBUGVER (3U<<30) +#define DCSR_NDRESET (1U<<29) +#define DCSR_FULLRESET (1U<<28) +#define DCSR_EBREAKM (1U<<15) +#define DCSR_EBREAKH (1U<<14) +#define DCSR_EBREAKS (1U<<13) +#define DCSR_EBREAKU (1U<<12) +#define DCSR_STOPCYCLE (1U<<10) +#define DCSR_STOPTIME (1U<<9) +#define DCSR_CAUSE (7U<<6) +#define DCSR_DEBUGINT (1U<<5) +#define DCSR_HALT (1U<<3) +#define DCSR_STEP (1U<<2) +#define DCSR_PRV (3U<<0) + +#define DCSR_CAUSE_NONE 0 +#define DCSR_CAUSE_SWBP 1 +#define DCSR_CAUSE_HWBP 2 +#define DCSR_CAUSE_DEBUGINT 3 +#define DCSR_CAUSE_STEP 4 +#define DCSR_CAUSE_HALT 5 + +#define MCONTROL_SELECT (1U<<19) +#define MCONTROL_TIMING (1U<<18) +#define MCONTROL_ACTION (0x3fU<<12) +#define MCONTROL_CHAIN (1U<<11) +#define MCONTROL_MATCH (0xfU<<7) +#define MCONTROL_M (1U<<6) +#define MCONTROL_H (1U<<5) +#define MCONTROL_S (1U<<4) +#define MCONTROL_U (1U<<3) +#define MCONTROL_EXECUTE (1U<<2) +#define MCONTROL_STORE (1U<<1) +#define MCONTROL_LOAD (1U<<0) + +#define MCONTROL_TYPE_NONE 0 +#define MCONTROL_TYPE_MATCH 2 + +#define MCONTROL_ACTION_DEBUG_EXCEPTION 0 +#define MCONTROL_ACTION_DEBUG_MODE 1 +#define MCONTROL_ACTION_TRACE_START 2 +#define MCONTROL_ACTION_TRACE_STOP 3 +#define MCONTROL_ACTION_TRACE_EMIT 4 + +#define MCONTROL_MATCH_EQUAL 0 +#define MCONTROL_MATCH_NAPOT 1 +#define MCONTROL_MATCH_GE 2 +#define MCONTROL_MATCH_LT 3 +#define MCONTROL_MATCH_MASK_LOW 4 +#define MCONTROL_MATCH_MASK_HIGH 5 + +#define MIP_SSIP (1U << IRQ_S_SOFT) +#define MIP_HSIP (1U << IRQ_H_SOFT) +#define MIP_MSIP (1U << IRQ_M_SOFT) +#define MIP_STIP (1U << IRQ_S_TIMER) +#define MIP_HTIP (1U << IRQ_H_TIMER) +#define MIP_MTIP (1U << IRQ_M_TIMER) +#define MIP_SEIP (1U << IRQ_S_EXT) +#define MIP_HEIP (1U << IRQ_H_EXT) +#define MIP_MEIP (1U << IRQ_M_EXT) + +#define SIP_SSIP MIP_SSIP +#define SIP_STIP MIP_STIP + +#define PRV_U 0 +#define PRV_S 1 +#define PRV_H 2 +#define PRV_M 3 + +#define VM_MBARE 0 +#define VM_MBB 1 +#define VM_MBBID 2 +#define VM_SV32 8 +#define VM_SV39 9 +#define VM_SV48 10 + +#define IRQ_S_SOFT 1 +#define IRQ_H_SOFT 2 +#define IRQ_M_SOFT 3 +#define IRQ_S_TIMER 5 +#define IRQ_H_TIMER 6 +#define IRQ_M_TIMER 7 +#define IRQ_S_EXT 9 +#define IRQ_H_EXT 10 +#define IRQ_M_EXT 11 +#define IRQ_COP 12 +#define IRQ_HOST 13 + +#define DEFAULT_RSTVEC 0x00001000U +#define DEFAULT_NMIVEC 0x00001004U +#define DEFAULT_MTVEC 0x00001010U +#define CONFIG_STRING_ADDR 0x0000100CU +#define EXT_IO_BASE 0x40000000U +#define DRAM_BASE 0x80000000U + +/* page table entry (PTE) fields */ +#define PTE_V 0x001U /* Valid */ +#define PTE_R 0x002U /* Read */ +#define PTE_W 0x004U /* Write */ +#define PTE_X 0x008U /* Execute */ +#define PTE_U 0x010U /* User */ +#define PTE_G 0x020U /* Global */ +#define PTE_A 0x040U /* Accessed */ +#define PTE_D 0x080U /* Dirty */ +#define PTE_SOFT 0x300U /* Reserved for Software */ + +#define PTE_PPN_SHIFT 10 + +#define MCONTROL_TYPE(xlen) (0xfULL<<((xlen)-4)) +#define MCONTROL_DMODE(xlen) (1ULL<<((xlen)-5)) +#define MCONTROL_MASKMAX(xlen) (0x3fULL<<((xlen)-11)) + +#define PTE_TABLE(PTE) (((PTE) & (PTE_V | PTE_R | PTE_W | PTE_X)) == PTE_V) + +#if defined(__riscv) + +#if defined(__riscv64) +# define MSTATUS_SD MSTATUS64_SD +# define SSTATUS_SD SSTATUS64_SD +# define RISCV_PGLEVEL_BITS 9 +#else +# define MSTATUS_SD MSTATUS32_SD +# define SSTATUS_SD SSTATUS32_SD +# define RISCV_PGLEVEL_BITS 10 +#endif +#define RISCV_PGSHIFT 12 +#define RISCV_PGSIZE (1 << RISCV_PGSHIFT) + +#ifndef __ASSEMBLER__ + +#if defined(__GNUC__) + +#define READ_CSR(reg) ({ unsigned long __tmp; \ + asm volatile ("csrr %0, " #reg : "=r"(__tmp)); \ + __tmp; }) + +#define WRITE_CSR(reg, val) ({ \ + if (__builtin_constant_p(val) && (unsigned long)(val) < 32) \ + asm volatile ("csrw " #reg ", %0" :: "i"(val)); \ + else \ + asm volatile ("csrw " #reg ", %0" :: "r"(val)); }) + +#define swap_csr(reg, val) ({ unsigned long __tmp; \ + if (__builtin_constant_p(val) && (unsigned long)(val) < 32) \ + asm volatile ("csrrw %0, " #reg ", %1" : "=r"(__tmp) : "i"(val)); \ + else \ + asm volatile ("csrrw %0, " #reg ", %1" : "=r"(__tmp) : "r"(val)); \ + __tmp; }) + +#define SET_CSR(reg, bit) ({ unsigned long __tmp; \ + if (__builtin_constant_p(bit) && (unsigned long)(bit) < 32) \ + asm volatile ("csrrs %0, " #reg ", %1" : "=r"(__tmp) : "i"(bit)); \ + else \ + asm volatile ("csrrs %0, " #reg ", %1" : "=r"(__tmp) : "r"(bit)); \ + __tmp; }) + +#define CLEAR_CSR(reg, bit) ({ unsigned long __tmp; \ + if (__builtin_constant_p(bit) && (unsigned long)(bit) < 32) \ + asm volatile ("csrrc %0, " #reg ", %1" : "=r"(__tmp) : "i"(bit)); \ + else \ + asm volatile ("csrrc %0, " #reg ", %1" : "=r"(__tmp) : "r"(bit)); \ + __tmp; }) + +#define read_time() READ_CSR(mtime) +#define read_cycle() READ_CSR(mcycle) +#define current_coreid() READ_CSR(mhartid) + +#endif + +#endif + +#endif + +#endif + +#ifndef RISCV_ENCODING_H +#define RISCV_ENCODING_H +#define MATCH_BEQ 0x63U +#define MASK_BEQ 0x707fU +#define MATCH_BNE 0x1063U +#define MASK_BNE 0x707fU +#define MATCH_BLT 0x4063U +#define MASK_BLT 0x707fU +#define MATCH_BGE 0x5063U +#define MASK_BGE 0x707fU +#define MATCH_BLTU 0x6063U +#define MASK_BLTU 0x707fU +#define MATCH_BGEU 0x7063U +#define MASK_BGEU 0x707fU +#define MATCH_JALR 0x67U +#define MASK_JALR 0x707fU +#define MATCH_JAL 0x6fU +#define MASK_JAL 0x7fU +#define MATCH_LUI 0x37U +#define MASK_LUI 0x7fU +#define MATCH_AUIPC 0x17U +#define MASK_AUIPC 0x7fU +#define MATCH_ADDI 0x13U +#define MASK_ADDI 0x707fU +#define MATCH_SLLI 0x1013U +#define MASK_SLLI 0xfc00707fU +#define MATCH_SLTI 0x2013U +#define MASK_SLTI 0x707fU +#define MATCH_SLTIU 0x3013U +#define MASK_SLTIU 0x707fU +#define MATCH_XORI 0x4013U +#define MASK_XORI 0x707fU +#define MATCH_SRLI 0x5013U +#define MASK_SRLI 0xfc00707fU +#define MATCH_SRAI 0x40005013U +#define MASK_SRAI 0xfc00707fU +#define MATCH_ORI 0x6013U +#define MASK_ORI 0x707fU +#define MATCH_ANDI 0x7013U +#define MASK_ANDI 0x707fU +#define MATCH_ADD 0x33U +#define MASK_ADD 0xfe00707fU +#define MATCH_SUB 0x40000033U +#define MASK_SUB 0xfe00707fU +#define MATCH_SLL 0x1033U +#define MASK_SLL 0xfe00707fU +#define MATCH_SLT 0x2033U +#define MASK_SLT 0xfe00707fU +#define MATCH_SLTU 0x3033U +#define MASK_SLTU 0xfe00707fU +#define MATCH_XOR 0x4033U +#define MASK_XOR 0xfe00707fU +#define MATCH_SRL 0x5033U +#define MASK_SRL 0xfe00707fU +#define MATCH_SRA 0x40005033U +#define MASK_SRA 0xfe00707fU +#define MATCH_OR 0x6033U +#define MASK_OR 0xfe00707fU +#define MATCH_AND 0x7033U +#define MASK_AND 0xfe00707fU +#define MATCH_ADDIW 0x1bU +#define MASK_ADDIW 0x707fU +#define MATCH_SLLIW 0x101bU +#define MASK_SLLIW 0xfe00707fU +#define MATCH_SRLIW 0x501bU +#define MASK_SRLIW 0xfe00707fU +#define MATCH_SRAIW 0x4000501bU +#define MASK_SRAIW 0xfe00707fU +#define MATCH_ADDW 0x3bU +#define MASK_ADDW 0xfe00707fU +#define MATCH_SUBW 0x4000003bU +#define MASK_SUBW 0xfe00707fU +#define MATCH_SLLW 0x103bU +#define MASK_SLLW 0xfe00707fU +#define MATCH_SRLW 0x503bU +#define MASK_SRLW 0xfe00707fU +#define MATCH_SRAW 0x4000503bU +#define MASK_SRAW 0xfe00707fU +#define MATCH_LB 0x3U +#define MASK_LB 0x707fU +#define MATCH_LH 0x1003U +#define MASK_LH 0x707fU +#define MATCH_LW 0x2003U +#define MASK_LW 0x707fU +#define MATCH_LD 0x3003U +#define MASK_LD 0x707fU +#define MATCH_LBU 0x4003U +#define MASK_LBU 0x707fU +#define MATCH_LHU 0x5003U +#define MASK_LHU 0x707fU +#define MATCH_LWU 0x6003U +#define MASK_LWU 0x707fU +#define MATCH_SB 0x23U +#define MASK_SB 0x707fU +#define MATCH_SH 0x1023U +#define MASK_SH 0x707fU +#define MATCH_SW 0x2023U +#define MASK_SW 0x707fU +#define MATCH_SD 0x3023U +#define MASK_SD 0x707fU +#define MATCH_FENCE 0xfU +#define MASK_FENCE 0x707fU +#define MATCH_FENCE_I 0x100fU +#define MASK_FENCE_I 0x707fU +#define MATCH_MUL 0x2000033U +#define MASK_MUL 0xfe00707fU +#define MATCH_MULH 0x2001033U +#define MASK_MULH 0xfe00707fU +#define MATCH_MULHSU 0x2002033U +#define MASK_MULHSU 0xfe00707fU +#define MATCH_MULHU 0x2003033U +#define MASK_MULHU 0xfe00707fU +#define MATCH_DIV 0x2004033U +#define MASK_DIV 0xfe00707fU +#define MATCH_DIVU 0x2005033U +#define MASK_DIVU 0xfe00707fU +#define MATCH_REM 0x2006033U +#define MASK_REM 0xfe00707fU +#define MATCH_REMU 0x2007033U +#define MASK_REMU 0xfe00707fU +#define MATCH_MULW 0x200003bU +#define MASK_MULW 0xfe00707fU +#define MATCH_DIVW 0x200403bU +#define MASK_DIVW 0xfe00707fU +#define MATCH_DIVUW 0x200503bU +#define MASK_DIVUW 0xfe00707fU +#define MATCH_REMW 0x200603bU +#define MASK_REMW 0xfe00707fU +#define MATCH_REMUW 0x200703bU +#define MASK_REMUW 0xfe00707fU +#define MATCH_AMOADD_W 0x202fU +#define MASK_AMOADD_W 0xf800707fU +#define MATCH_AMOXOR_W 0x2000202fU +#define MASK_AMOXOR_W 0xf800707fU +#define MATCH_AMOOR_W 0x4000202fU +#define MASK_AMOOR_W 0xf800707fU +#define MATCH_AMOAND_W 0x6000202fU +#define MASK_AMOAND_W 0xf800707fU +#define MATCH_AMOMIN_W 0x8000202fU +#define MASK_AMOMIN_W 0xf800707fU +#define MATCH_AMOMAX_W 0xa000202fU +#define MASK_AMOMAX_W 0xf800707fU +#define MATCH_AMOMINU_W 0xc000202fU +#define MASK_AMOMINU_W 0xf800707fU +#define MATCH_AMOMAXU_W 0xe000202fU +#define MASK_AMOMAXU_W 0xf800707fU +#define MATCH_AMOSWAP_W 0x800202fU +#define MASK_AMOSWAP_W 0xf800707fU +#define MATCH_LR_W 0x1000202fU +#define MASK_LR_W 0xf9f0707fU +#define MATCH_SC_W 0x1800202fU +#define MASK_SC_W 0xf800707fU +#define MATCH_AMOADD_D 0x302fU +#define MASK_AMOADD_D 0xf800707fU +#define MATCH_AMOXOR_D 0x2000302fU +#define MASK_AMOXOR_D 0xf800707fU +#define MATCH_AMOOR_D 0x4000302fU +#define MASK_AMOOR_D 0xf800707fU +#define MATCH_AMOAND_D 0x6000302fU +#define MASK_AMOAND_D 0xf800707fU +#define MATCH_AMOMIN_D 0x8000302fU +#define MASK_AMOMIN_D 0xf800707fU +#define MATCH_AMOMAX_D 0xa000302fU +#define MASK_AMOMAX_D 0xf800707fU +#define MATCH_AMOMINU_D 0xc000302fU +#define MASK_AMOMINU_D 0xf800707fU +#define MATCH_AMOMAXU_D 0xe000302fU +#define MASK_AMOMAXU_D 0xf800707fU +#define MATCH_AMOSWAP_D 0x800302fU +#define MASK_AMOSWAP_D 0xf800707fU +#define MATCH_LR_D 0x1000302fU +#define MASK_LR_D 0xf9f0707fU +#define MATCH_SC_D 0x1800302fU +#define MASK_SC_D 0xf800707fU +#define MATCH_ECALL 0x73U +#define MASK_ECALL 0xffffffffU +#define MATCH_EBREAK 0x100073U +#define MASK_EBREAK 0xffffffffU +#define MATCH_URET 0x200073U +#define MASK_URET 0xffffffffU +#define MATCH_SRET 0x10200073U +#define MASK_SRET 0xffffffffU +#define MATCH_HRET 0x20200073U +#define MASK_HRET 0xffffffffU +#define MATCH_MRET 0x30200073U +#define MASK_MRET 0xffffffffU +#define MATCH_DRET 0x7b200073U +#define MASK_DRET 0xffffffffU +#define MATCH_SFENCE_VM 0x10400073U +#define MASK_SFENCE_VM 0xfff07fffU +#define MATCH_WFI 0x10500073U +#define MASK_WFI 0xffffffffU +#define MATCH_CSRRW 0x1073U +#define MASK_CSRRW 0x707fU +#define MATCH_CSRRS 0x2073U +#define MASK_CSRRS 0x707fU +#define MATCH_CSRRC 0x3073U +#define MASK_CSRRC 0x707fU +#define MATCH_CSRRWI 0x5073U +#define MASK_CSRRWI 0x707fU +#define MATCH_CSRRSI 0x6073U +#define MASK_CSRRSI 0x707fU +#define MATCH_CSRRCI 0x7073U +#define MASK_CSRRCI 0x707fU +#define MATCH_FADD_S 0x53U +#define MASK_FADD_S 0xfe00007fU +#define MATCH_FSUB_S 0x8000053U +#define MASK_FSUB_S 0xfe00007fU +#define MATCH_FMUL_S 0x10000053U +#define MASK_FMUL_S 0xfe00007fU +#define MATCH_FDIV_S 0x18000053U +#define MASK_FDIV_S 0xfe00007fU +#define MATCH_FSGNJ_S 0x20000053U +#define MASK_FSGNJ_S 0xfe00707fU +#define MATCH_FSGNJN_S 0x20001053U +#define MASK_FSGNJN_S 0xfe00707fU +#define MATCH_FSGNJX_S 0x20002053U +#define MASK_FSGNJX_S 0xfe00707fU +#define MATCH_FMIN_S 0x28000053U +#define MASK_FMIN_S 0xfe00707fU +#define MATCH_FMAX_S 0x28001053U +#define MASK_FMAX_S 0xfe00707fU +#define MATCH_FSQRT_S 0x58000053U +#define MASK_FSQRT_S 0xfff0007fU +#define MATCH_FADD_D 0x2000053U +#define MASK_FADD_D 0xfe00007fU +#define MATCH_FSUB_D 0xa000053U +#define MASK_FSUB_D 0xfe00007fU +#define MATCH_FMUL_D 0x12000053U +#define MASK_FMUL_D 0xfe00007fU +#define MATCH_FDIV_D 0x1a000053U +#define MASK_FDIV_D 0xfe00007fU +#define MATCH_FSGNJ_D 0x22000053U +#define MASK_FSGNJ_D 0xfe00707fU +#define MATCH_FSGNJN_D 0x22001053U +#define MASK_FSGNJN_D 0xfe00707fU +#define MATCH_FSGNJX_D 0x22002053U +#define MASK_FSGNJX_D 0xfe00707fU +#define MATCH_FMIN_D 0x2a000053U +#define MASK_FMIN_D 0xfe00707fU +#define MATCH_FMAX_D 0x2a001053U +#define MASK_FMAX_D 0xfe00707fU +#define MATCH_FCVT_S_D 0x40100053U +#define MASK_FCVT_S_D 0xfff0007fU +#define MATCH_FCVT_D_S 0x42000053U +#define MASK_FCVT_D_S 0xfff0007fU +#define MATCH_FSQRT_D 0x5a000053U +#define MASK_FSQRT_D 0xfff0007fU +#define MATCH_FLE_S 0xa0000053U +#define MASK_FLE_S 0xfe00707fU +#define MATCH_FLT_S 0xa0001053U +#define MASK_FLT_S 0xfe00707fU +#define MATCH_FEQ_S 0xa0002053U +#define MASK_FEQ_S 0xfe00707fU +#define MATCH_FLE_D 0xa2000053U +#define MASK_FLE_D 0xfe00707fU +#define MATCH_FLT_D 0xa2001053U +#define MASK_FLT_D 0xfe00707fU +#define MATCH_FEQ_D 0xa2002053U +#define MASK_FEQ_D 0xfe00707fU +#define MATCH_FCVT_W_S 0xc0000053U +#define MASK_FCVT_W_S 0xfff0007fU +#define MATCH_FCVT_WU_S 0xc0100053U +#define MASK_FCVT_WU_S 0xfff0007fU +#define MATCH_FCVT_L_S 0xc0200053U +#define MASK_FCVT_L_S 0xfff0007fU +#define MATCH_FCVT_LU_S 0xc0300053U +#define MASK_FCVT_LU_S 0xfff0007fU +#define MATCH_FMV_X_S 0xe0000053U +#define MASK_FMV_X_S 0xfff0707fU +#define MATCH_FCLASS_S 0xe0001053U +#define MASK_FCLASS_S 0xfff0707fU +#define MATCH_FCVT_W_D 0xc2000053U +#define MASK_FCVT_W_D 0xfff0007fU +#define MATCH_FCVT_WU_D 0xc2100053U +#define MASK_FCVT_WU_D 0xfff0007fU +#define MATCH_FCVT_L_D 0xc2200053U +#define MASK_FCVT_L_D 0xfff0007fU +#define MATCH_FCVT_LU_D 0xc2300053U +#define MASK_FCVT_LU_D 0xfff0007fU +#define MATCH_FMV_X_D 0xe2000053U +#define MASK_FMV_X_D 0xfff0707fU +#define MATCH_FCLASS_D 0xe2001053U +#define MASK_FCLASS_D 0xfff0707fU +#define MATCH_FCVT_S_W 0xd0000053U +#define MASK_FCVT_S_W 0xfff0007fU +#define MATCH_FCVT_S_WU 0xd0100053U +#define MASK_FCVT_S_WU 0xfff0007fU +#define MATCH_FCVT_S_L 0xd0200053U +#define MASK_FCVT_S_L 0xfff0007fU +#define MATCH_FCVT_S_LU 0xd0300053U +#define MASK_FCVT_S_LU 0xfff0007fU +#define MATCH_FMV_S_X 0xf0000053U +#define MASK_FMV_S_X 0xfff0707fU +#define MATCH_FCVT_D_W 0xd2000053U +#define MASK_FCVT_D_W 0xfff0007fU +#define MATCH_FCVT_D_WU 0xd2100053U +#define MASK_FCVT_D_WU 0xfff0007fU +#define MATCH_FCVT_D_L 0xd2200053U +#define MASK_FCVT_D_L 0xfff0007fU +#define MATCH_FCVT_D_LU 0xd2300053U +#define MASK_FCVT_D_LU 0xfff0007fU +#define MATCH_FMV_D_X 0xf2000053U +#define MASK_FMV_D_X 0xfff0707fU +#define MATCH_FLW 0x2007U +#define MASK_FLW 0x707fU +#define MATCH_FLD 0x3007U +#define MASK_FLD 0x707fU +#define MATCH_FSW 0x2027U +#define MASK_FSW 0x707fU +#define MATCH_FSD 0x3027U +#define MASK_FSD 0x707fU +#define MATCH_FMADD_S 0x43U +#define MASK_FMADD_S 0x600007fU +#define MATCH_FMSUB_S 0x47U +#define MASK_FMSUB_S 0x600007fU +#define MATCH_FNMSUB_S 0x4bU +#define MASK_FNMSUB_S 0x600007fU +#define MATCH_FNMADD_S 0x4fU +#define MASK_FNMADD_S 0x600007fU +#define MATCH_FMADD_D 0x2000043U +#define MASK_FMADD_D 0x600007fU +#define MATCH_FMSUB_D 0x2000047U +#define MASK_FMSUB_D 0x600007fU +#define MATCH_FNMSUB_D 0x200004bU +#define MASK_FNMSUB_D 0x600007fU +#define MATCH_FNMADD_D 0x200004fU +#define MASK_FNMADD_D 0x600007fU +#define MATCH_C_NOP 0x1U +#define MASK_C_NOP 0xffffU +#define MATCH_C_ADDI16SP 0x6101U +#define MASK_C_ADDI16SP 0xef83U +#define MATCH_C_JR 0x8002U +#define MASK_C_JR 0xf07fU +#define MATCH_C_JALR 0x9002U +#define MASK_C_JALR 0xf07fU +#define MATCH_C_EBREAK 0x9002U +#define MASK_C_EBREAK 0xffffU +#define MATCH_C_LD 0x6000U +#define MASK_C_LD 0xe003U +#define MATCH_C_SD 0xe000U +#define MASK_C_SD 0xe003U +#define MATCH_C_ADDIW 0x2001U +#define MASK_C_ADDIW 0xe003U +#define MATCH_C_LDSP 0x6002U +#define MASK_C_LDSP 0xe003U +#define MATCH_C_SDSP 0xe002U +#define MASK_C_SDSP 0xe003U +#define MATCH_C_ADDI4SPN 0x0U +#define MASK_C_ADDI4SPN 0xe003U +#define MATCH_C_FLD 0x2000U +#define MASK_C_FLD 0xe003U +#define MATCH_C_LW 0x4000U +#define MASK_C_LW 0xe003U +#define MATCH_C_FLW 0x6000U +#define MASK_C_FLW 0xe003U +#define MATCH_C_FSD 0xa000U +#define MASK_C_FSD 0xe003U +#define MATCH_C_SW 0xc000U +#define MASK_C_SW 0xe003U +#define MATCH_C_FSW 0xe000U +#define MASK_C_FSW 0xe003U +#define MATCH_C_ADDI 0x1U +#define MASK_C_ADDI 0xe003U +#define MATCH_C_JAL 0x2001U +#define MASK_C_JAL 0xe003U +#define MATCH_C_LI 0x4001U +#define MASK_C_LI 0xe003U +#define MATCH_C_LUI 0x6001U +#define MASK_C_LUI 0xe003U +#define MATCH_C_SRLI 0x8001U +#define MASK_C_SRLI 0xec03U +#define MATCH_C_SRAI 0x8401U +#define MASK_C_SRAI 0xec03U +#define MATCH_C_ANDI 0x8801U +#define MASK_C_ANDI 0xec03U +#define MATCH_C_SUB 0x8c01U +#define MASK_C_SUB 0xfc63U +#define MATCH_C_XOR 0x8c21U +#define MASK_C_XOR 0xfc63U +#define MATCH_C_OR 0x8c41U +#define MASK_C_OR 0xfc63U +#define MATCH_C_AND 0x8c61U +#define MASK_C_AND 0xfc63U +#define MATCH_C_SUBW 0x9c01U +#define MASK_C_SUBW 0xfc63U +#define MATCH_C_ADDW 0x9c21U +#define MASK_C_ADDW 0xfc63U +#define MATCH_C_J 0xa001U +#define MASK_C_J 0xe003U +#define MATCH_C_BEQZ 0xc001U +#define MASK_C_BEQZ 0xe003U +#define MATCH_C_BNEZ 0xe001U +#define MASK_C_BNEZ 0xe003U +#define MATCH_C_SLLI 0x2U +#define MASK_C_SLLI 0xe003U +#define MATCH_C_FLDSP 0x2002U +#define MASK_C_FLDSP 0xe003U +#define MATCH_C_LWSP 0x4002U +#define MASK_C_LWSP 0xe003U +#define MATCH_C_FLWSP 0x6002U +#define MASK_C_FLWSP 0xe003U +#define MATCH_C_MV 0x8002U +#define MASK_C_MV 0xf003U +#define MATCH_C_ADD 0x9002U +#define MASK_C_ADD 0xf003U +#define MATCH_C_FSDSP 0xa002U +#define MASK_C_FSDSP 0xe003U +#define MATCH_C_SWSP 0xc002U +#define MASK_C_SWSP 0xe003U +#define MATCH_C_FSWSP 0xe002U +#define MASK_C_FSWSP 0xe003U +#define MATCH_CUSTOM0 0xbU +#define MASK_CUSTOM0 0x707fU +#define MATCH_CUSTOM0_RS1 0x200bU +#define MASK_CUSTOM0_RS1 0x707fU +#define MATCH_CUSTOM0_RS1_RS2 0x300bU +#define MASK_CUSTOM0_RS1_RS2 0x707fU +#define MATCH_CUSTOM0_RD 0x400bU +#define MASK_CUSTOM0_RD 0x707fU +#define MATCH_CUSTOM0_RD_RS1 0x600bU +#define MASK_CUSTOM0_RD_RS1 0x707fU +#define MATCH_CUSTOM0_RD_RS1_RS2 0x700bU +#define MASK_CUSTOM0_RD_RS1_RS2 0x707fU +#define MATCH_CUSTOM1 0x2bU +#define MASK_CUSTOM1 0x707fU +#define MATCH_CUSTOM1_RS1 0x202bU +#define MASK_CUSTOM1_RS1 0x707fU +#define MATCH_CUSTOM1_RS1_RS2 0x302bU +#define MASK_CUSTOM1_RS1_RS2 0x707fU +#define MATCH_CUSTOM1_RD 0x402bU +#define MASK_CUSTOM1_RD 0x707fU +#define MATCH_CUSTOM1_RD_RS1 0x602bU +#define MASK_CUSTOM1_RD_RS1 0x707fU +#define MATCH_CUSTOM1_RD_RS1_RS2 0x702bU +#define MASK_CUSTOM1_RD_RS1_RS2 0x707fU +#define MATCH_CUSTOM2 0x5bU +#define MASK_CUSTOM2 0x707fU +#define MATCH_CUSTOM2_RS1 0x205bU +#define MASK_CUSTOM2_RS1 0x707fU +#define MATCH_CUSTOM2_RS1_RS2 0x305bU +#define MASK_CUSTOM2_RS1_RS2 0x707fU +#define MATCH_CUSTOM2_RD 0x405bU +#define MASK_CUSTOM2_RD 0x707fU +#define MATCH_CUSTOM2_RD_RS1 0x605bU +#define MASK_CUSTOM2_RD_RS1 0x707fU +#define MATCH_CUSTOM2_RD_RS1_RS2 0x705bU +#define MASK_CUSTOM2_RD_RS1_RS2 0x707fU +#define MATCH_CUSTOM3 0x7bU +#define MASK_CUSTOM3 0x707fU +#define MATCH_CUSTOM3_RS1 0x207bU +#define MASK_CUSTOM3_RS1 0x707fU +#define MATCH_CUSTOM3_RS1_RS2 0x307bU +#define MASK_CUSTOM3_RS1_RS2 0x707fU +#define MATCH_CUSTOM3_RD 0x407bU +#define MASK_CUSTOM3_RD 0x707fU +#define MATCH_CUSTOM3_RD_RS1 0x607bU +#define MASK_CUSTOM3_RD_RS1 0x707fU +#define MATCH_CUSTOM3_RD_RS1_RS2 0x707bU +#define MASK_CUSTOM3_RD_RS1_RS2 0x707fU +#define CSR_FFLAGS 0x1U +#define CSR_FRM 0x2U +#define CSR_FCSR 0x3U +#define CSR_CYCLE 0xc00U +#define CSR_TIME 0xc01U +#define CSR_INSTRET 0xc02U +#define CSR_HPMCOUNTER3 0xc03U +#define CSR_HPMCOUNTER4 0xc04U +#define CSR_HPMCOUNTER5 0xc05U +#define CSR_HPMCOUNTER6 0xc06U +#define CSR_HPMCOUNTER7 0xc07U +#define CSR_HPMCOUNTER8 0xc08U +#define CSR_HPMCOUNTER9 0xc09U +#define CSR_HPMCOUNTER10 0xc0aU +#define CSR_HPMCOUNTER11 0xc0bU +#define CSR_HPMCOUNTER12 0xc0cU +#define CSR_HPMCOUNTER13 0xc0dU +#define CSR_HPMCOUNTER14 0xc0eU +#define CSR_HPMCOUNTER15 0xc0fU +#define CSR_HPMCOUNTER16 0xc10U +#define CSR_HPMCOUNTER17 0xc11U +#define CSR_HPMCOUNTER18 0xc12U +#define CSR_HPMCOUNTER19 0xc13U +#define CSR_HPMCOUNTER20 0xc14U +#define CSR_HPMCOUNTER21 0xc15U +#define CSR_HPMCOUNTER22 0xc16U +#define CSR_HPMCOUNTER23 0xc17U +#define CSR_HPMCOUNTER24 0xc18U +#define CSR_HPMCOUNTER25 0xc19U +#define CSR_HPMCOUNTER26 0xc1aU +#define CSR_HPMCOUNTER27 0xc1bU +#define CSR_HPMCOUNTER28 0xc1cU +#define CSR_HPMCOUNTER29 0xc1dU +#define CSR_HPMCOUNTER30 0xc1eU +#define CSR_HPMCOUNTER31 0xc1fU +#define CSR_SSTATUS 0x100U +#define CSR_SIE 0x104U +#define CSR_STVEC 0x105U +#define CSR_SSCRATCH 0x140U +#define CSR_SEPC 0x141U +#define CSR_SCAUSE 0x142U +#define CSR_SBADADDR 0x143U +#define CSR_SIP 0x144U +#define CSR_SPTBR 0x180U +#define CSR_MSTATUS 0x300U +#define CSR_MISA 0x301U +#define CSR_MEDELEG 0x302U +#define CSR_MIDELEG 0x303U +#define CSR_MIE 0x304U +#define CSR_MTVEC 0x305U +#define CSR_MSCRATCH 0x340U +#define CSR_MEPC 0x341U +#define CSR_MCAUSE 0x342U +#define CSR_MBADADDR 0x343U +#define CSR_MIP 0x344U +#define CSR_TSELECT 0x7a0U +#define CSR_TDATA1 0x7a1U +#define CSR_TDATA2 0x7a2U +#define CSR_TDATA3 0x7a3U +#define CSR_DCSR 0x7b0U +#define CSR_DPC 0x7b1U +#define CSR_DSCRATCH 0x7b2U +#define CSR_MCYCLE 0xb00U +#define CSR_MINSTRET 0xb02U +#define CSR_MHPMCOUNTER3 0xb03U +#define CSR_MHPMCOUNTER4 0xb04U +#define CSR_MHPMCOUNTER5 0xb05U +#define CSR_MHPMCOUNTER6 0xb06U +#define CSR_MHPMCOUNTER7 0xb07U +#define CSR_MHPMCOUNTER8 0xb08U +#define CSR_MHPMCOUNTER9 0xb09U +#define CSR_MHPMCOUNTER10 0xb0aU +#define CSR_MHPMCOUNTER11 0xb0bU +#define CSR_MHPMCOUNTER12 0xb0cU +#define CSR_MHPMCOUNTER13 0xb0dU +#define CSR_MHPMCOUNTER14 0xb0eU +#define CSR_MHPMCOUNTER15 0xb0fU +#define CSR_MHPMCOUNTER16 0xb10U +#define CSR_MHPMCOUNTER17 0xb11U +#define CSR_MHPMCOUNTER18 0xb12U +#define CSR_MHPMCOUNTER19 0xb13U +#define CSR_MHPMCOUNTER20 0xb14U +#define CSR_MHPMCOUNTER21 0xb15U +#define CSR_MHPMCOUNTER22 0xb16U +#define CSR_MHPMCOUNTER23 0xb17U +#define CSR_MHPMCOUNTER24 0xb18U +#define CSR_MHPMCOUNTER25 0xb19U +#define CSR_MHPMCOUNTER26 0xb1aU +#define CSR_MHPMCOUNTER27 0xb1bU +#define CSR_MHPMCOUNTER28 0xb1cU +#define CSR_MHPMCOUNTER29 0xb1dU +#define CSR_MHPMCOUNTER30 0xb1eU +#define CSR_MHPMCOUNTER31 0xb1fU +#define CSR_MUCOUNTEREN 0x320U +#define CSR_MSCOUNTEREN 0x321U +#define CSR_MHPMEVENT3 0x323U +#define CSR_MHPMEVENT4 0x324U +#define CSR_MHPMEVENT5 0x325U +#define CSR_MHPMEVENT6 0x326U +#define CSR_MHPMEVENT7 0x327U +#define CSR_MHPMEVENT8 0x328U +#define CSR_MHPMEVENT9 0x329U +#define CSR_MHPMEVENT10 0x32aU +#define CSR_MHPMEVENT11 0x32bU +#define CSR_MHPMEVENT12 0x32cU +#define CSR_MHPMEVENT13 0x32dU +#define CSR_MHPMEVENT14 0x32eU +#define CSR_MHPMEVENT15 0x32fU +#define CSR_MHPMEVENT16 0x330U +#define CSR_MHPMEVENT17 0x331U +#define CSR_MHPMEVENT18 0x332U +#define CSR_MHPMEVENT19 0x333U +#define CSR_MHPMEVENT20 0x334U +#define CSR_MHPMEVENT21 0x335U +#define CSR_MHPMEVENT22 0x336U +#define CSR_MHPMEVENT23 0x337U +#define CSR_MHPMEVENT24 0x338U +#define CSR_MHPMEVENT25 0x339U +#define CSR_MHPMEVENT26 0x33aU +#define CSR_MHPMEVENT27 0x33bU +#define CSR_MHPMEVENT28 0x33cU +#define CSR_MHPMEVENT29 0x33dU +#define CSR_MHPMEVENT30 0x33eU +#define CSR_MHPMEVENT31 0x33fU +#define CSR_MVENDORID 0xf11U +#define CSR_MARCHID 0xf12U +#define CSR_MIMPID 0xf13U +#define CSR_MHARTID 0xf14U +#define CSR_CYCLEH 0xc80U +#define CSR_TIMEH 0xc81U +#define CSR_INSTRETH 0xc82U +#define CSR_HPMCOUNTER3H 0xc83U +#define CSR_HPMCOUNTER4H 0xc84U +#define CSR_HPMCOUNTER5H 0xc85U +#define CSR_HPMCOUNTER6H 0xc86U +#define CSR_HPMCOUNTER7H 0xc87U +#define CSR_HPMCOUNTER8H 0xc88U +#define CSR_HPMCOUNTER9H 0xc89U +#define CSR_HPMCOUNTER10H 0xc8aU +#define CSR_HPMCOUNTER11H 0xc8bU +#define CSR_HPMCOUNTER12H 0xc8cU +#define CSR_HPMCOUNTER13H 0xc8dU +#define CSR_HPMCOUNTER14H 0xc8eU +#define CSR_HPMCOUNTER15H 0xc8fU +#define CSR_HPMCOUNTER16H 0xc90U +#define CSR_HPMCOUNTER17H 0xc91U +#define CSR_HPMCOUNTER18H 0xc92U +#define CSR_HPMCOUNTER19H 0xc93U +#define CSR_HPMCOUNTER20H 0xc94U +#define CSR_HPMCOUNTER21H 0xc95U +#define CSR_HPMCOUNTER22H 0xc96U +#define CSR_HPMCOUNTER23H 0xc97U +#define CSR_HPMCOUNTER24H 0xc98U +#define CSR_HPMCOUNTER25H 0xc99U +#define CSR_HPMCOUNTER26H 0xc9aU +#define CSR_HPMCOUNTER27H 0xc9bU +#define CSR_HPMCOUNTER28H 0xc9cU +#define CSR_HPMCOUNTER29H 0xc9dU +#define CSR_HPMCOUNTER30H 0xc9eU +#define CSR_HPMCOUNTER31H 0xc9fU +#define CSR_MCYCLEH 0xb80U +#define CSR_MINSTRETH 0xb82U +#define CSR_MHPMCOUNTER3H 0xb83U +#define CSR_MHPMCOUNTER4H 0xb84U +#define CSR_MHPMCOUNTER5H 0xb85U +#define CSR_MHPMCOUNTER6H 0xb86U +#define CSR_MHPMCOUNTER7H 0xb87U +#define CSR_MHPMCOUNTER8H 0xb88U +#define CSR_MHPMCOUNTER9H 0xb89U +#define CSR_MHPMCOUNTER10H 0xb8aU +#define CSR_MHPMCOUNTER11H 0xb8bU +#define CSR_MHPMCOUNTER12H 0xb8cU +#define CSR_MHPMCOUNTER13H 0xb8dU +#define CSR_MHPMCOUNTER14H 0xb8eU +#define CSR_MHPMCOUNTER15H 0xb8fU +#define CSR_MHPMCOUNTER16H 0xb90U +#define CSR_MHPMCOUNTER17H 0xb91U +#define CSR_MHPMCOUNTER18H 0xb92U +#define CSR_MHPMCOUNTER19H 0xb93U +#define CSR_MHPMCOUNTER20H 0xb94U +#define CSR_MHPMCOUNTER21H 0xb95U +#define CSR_MHPMCOUNTER22H 0xb96U +#define CSR_MHPMCOUNTER23H 0xb97U +#define CSR_MHPMCOUNTER24H 0xb98U +#define CSR_MHPMCOUNTER25H 0xb99U +#define CSR_MHPMCOUNTER26H 0xb9aU +#define CSR_MHPMCOUNTER27H 0xb9bU +#define CSR_MHPMCOUNTER28H 0xb9cU +#define CSR_MHPMCOUNTER29H 0xb9dU +#define CSR_MHPMCOUNTER30H 0xb9eU +#define CSR_MHPMCOUNTER31H 0xb9fU +#define CAUSE_MISALIGNED_FETCH 0x0 +#define CAUSE_FAULT_FETCH 0x1 +#define CAUSE_ILLEGAL_INSTRUCTION 0x2 +#define CAUSE_BREAKPOINT 0x3 +#define CAUSE_MISALIGNED_LOAD 0x4 +#define CAUSE_FAULT_LOAD 0x5 +#define CAUSE_MISALIGNED_STORE 0x6 +#define CAUSE_FAULT_STORE 0x7 +#define CAUSE_USER_ECALL 0x8 +#define CAUSE_SUPERVISOR_ECALL 0x9 +#define CAUSE_HYPERVISOR_ECALL 0xa +#define CAUSE_MACHINE_ECALL 0xb +#endif +#if defined(DECLARE_INSN) +DECLARE_INSN(beq, MATCH_BEQ, MASK_BEQ) +DECLARE_INSN(bne, MATCH_BNE, MASK_BNE) +DECLARE_INSN(blt, MATCH_BLT, MASK_BLT) +DECLARE_INSN(bge, MATCH_BGE, MASK_BGE) +DECLARE_INSN(bltu, MATCH_BLTU, MASK_BLTU) +DECLARE_INSN(bgeu, MATCH_BGEU, MASK_BGEU) +DECLARE_INSN(jalr, MATCH_JALR, MASK_JALR) +DECLARE_INSN(jal, MATCH_JAL, MASK_JAL) +DECLARE_INSN(lui, MATCH_LUI, MASK_LUI) +DECLARE_INSN(auipc, MATCH_AUIPC, MASK_AUIPC) +DECLARE_INSN(addi, MATCH_ADDI, MASK_ADDI) +DECLARE_INSN(slli, MATCH_SLLI, MASK_SLLI) +DECLARE_INSN(slti, MATCH_SLTI, MASK_SLTI) +DECLARE_INSN(sltiu, MATCH_SLTIU, MASK_SLTIU) +DECLARE_INSN(xori, MATCH_XORI, MASK_XORI) +DECLARE_INSN(srli, MATCH_SRLI, MASK_SRLI) +DECLARE_INSN(srai, MATCH_SRAI, MASK_SRAI) +DECLARE_INSN(ori, MATCH_ORI, MASK_ORI) +DECLARE_INSN(andi, MATCH_ANDI, MASK_ANDI) +DECLARE_INSN(add, MATCH_ADD, MASK_ADD) +DECLARE_INSN(sub, MATCH_SUB, MASK_SUB) +DECLARE_INSN(sll, MATCH_SLL, MASK_SLL) +DECLARE_INSN(slt, MATCH_SLT, MASK_SLT) +DECLARE_INSN(sltu, MATCH_SLTU, MASK_SLTU) +DECLARE_INSN(xor, MATCH_XOR, MASK_XOR) +DECLARE_INSN(srl, MATCH_SRL, MASK_SRL) +DECLARE_INSN(sra, MATCH_SRA, MASK_SRA) +DECLARE_INSN(or, MATCH_OR, MASK_OR) +DECLARE_INSN(and, MATCH_AND, MASK_AND) +DECLARE_INSN(addiw, MATCH_ADDIW, MASK_ADDIW) +DECLARE_INSN(slliw, MATCH_SLLIW, MASK_SLLIW) +DECLARE_INSN(srliw, MATCH_SRLIW, MASK_SRLIW) +DECLARE_INSN(sraiw, MATCH_SRAIW, MASK_SRAIW) +DECLARE_INSN(addw, MATCH_ADDW, MASK_ADDW) +DECLARE_INSN(subw, MATCH_SUBW, MASK_SUBW) +DECLARE_INSN(sllw, MATCH_SLLW, MASK_SLLW) +DECLARE_INSN(srlw, MATCH_SRLW, MASK_SRLW) +DECLARE_INSN(sraw, MATCH_SRAW, MASK_SRAW) +DECLARE_INSN(lb, MATCH_LB, MASK_LB) +DECLARE_INSN(lh, MATCH_LH, MASK_LH) +DECLARE_INSN(lw, MATCH_LW, MASK_LW) +DECLARE_INSN(ld, MATCH_LD, MASK_LD) +DECLARE_INSN(lbu, MATCH_LBU, MASK_LBU) +DECLARE_INSN(lhu, MATCH_LHU, MASK_LHU) +DECLARE_INSN(lwu, MATCH_LWU, MASK_LWU) +DECLARE_INSN(sb, MATCH_SB, MASK_SB) +DECLARE_INSN(sh, MATCH_SH, MASK_SH) +DECLARE_INSN(sw, MATCH_SW, MASK_SW) +DECLARE_INSN(sd, MATCH_SD, MASK_SD) +DECLARE_INSN(fence, MATCH_FENCE, MASK_FENCE) +DECLARE_INSN(fence_i, MATCH_FENCE_I, MASK_FENCE_I) +DECLARE_INSN(mul, MATCH_MUL, MASK_MUL) +DECLARE_INSN(mulh, MATCH_MULH, MASK_MULH) +DECLARE_INSN(mulhsu, MATCH_MULHSU, MASK_MULHSU) +DECLARE_INSN(mulhu, MATCH_MULHU, MASK_MULHU) +DECLARE_INSN(div, MATCH_DIV, MASK_DIV) +DECLARE_INSN(divu, MATCH_DIVU, MASK_DIVU) +DECLARE_INSN(rem, MATCH_REM, MASK_REM) +DECLARE_INSN(remu, MATCH_REMU, MASK_REMU) +DECLARE_INSN(mulw, MATCH_MULW, MASK_MULW) +DECLARE_INSN(divw, MATCH_DIVW, MASK_DIVW) +DECLARE_INSN(divuw, MATCH_DIVUW, MASK_DIVUW) +DECLARE_INSN(remw, MATCH_REMW, MASK_REMW) +DECLARE_INSN(remuw, MATCH_REMUW, MASK_REMUW) +DECLARE_INSN(amoadd_w, MATCH_AMOADD_W, MASK_AMOADD_W) +DECLARE_INSN(amoxor_w, MATCH_AMOXOR_W, MASK_AMOXOR_W) +DECLARE_INSN(amoor_w, MATCH_AMOOR_W, MASK_AMOOR_W) +DECLARE_INSN(amoand_w, MATCH_AMOAND_W, MASK_AMOAND_W) +DECLARE_INSN(amomin_w, MATCH_AMOMIN_W, MASK_AMOMIN_W) +DECLARE_INSN(amomax_w, MATCH_AMOMAX_W, MASK_AMOMAX_W) +DECLARE_INSN(amominu_w, MATCH_AMOMINU_W, MASK_AMOMINU_W) +DECLARE_INSN(amomaxu_w, MATCH_AMOMAXU_W, MASK_AMOMAXU_W) +DECLARE_INSN(amoswap_w, MATCH_AMOSWAP_W, MASK_AMOSWAP_W) +DECLARE_INSN(lr_w, MATCH_LR_W, MASK_LR_W) +DECLARE_INSN(sc_w, MATCH_SC_W, MASK_SC_W) +DECLARE_INSN(amoadd_d, MATCH_AMOADD_D, MASK_AMOADD_D) +DECLARE_INSN(amoxor_d, MATCH_AMOXOR_D, MASK_AMOXOR_D) +DECLARE_INSN(amoor_d, MATCH_AMOOR_D, MASK_AMOOR_D) +DECLARE_INSN(amoand_d, MATCH_AMOAND_D, MASK_AMOAND_D) +DECLARE_INSN(amomin_d, MATCH_AMOMIN_D, MASK_AMOMIN_D) +DECLARE_INSN(amomax_d, MATCH_AMOMAX_D, MASK_AMOMAX_D) +DECLARE_INSN(amominu_d, MATCH_AMOMINU_D, MASK_AMOMINU_D) +DECLARE_INSN(amomaxu_d, MATCH_AMOMAXU_D, MASK_AMOMAXU_D) +DECLARE_INSN(amoswap_d, MATCH_AMOSWAP_D, MASK_AMOSWAP_D) +DECLARE_INSN(lr_d, MATCH_LR_D, MASK_LR_D) +DECLARE_INSN(sc_d, MATCH_SC_D, MASK_SC_D) +DECLARE_INSN(ecall, MATCH_ECALL, MASK_ECALL) +DECLARE_INSN(ebreak, MATCH_EBREAK, MASK_EBREAK) +DECLARE_INSN(uret, MATCH_URET, MASK_URET) +DECLARE_INSN(sret, MATCH_SRET, MASK_SRET) +DECLARE_INSN(hret, MATCH_HRET, MASK_HRET) +DECLARE_INSN(mret, MATCH_MRET, MASK_MRET) +DECLARE_INSN(dret, MATCH_DRET, MASK_DRET) +DECLARE_INSN(sfence_vm, MATCH_SFENCE_VM, MASK_SFENCE_VM) +DECLARE_INSN(wfi, MATCH_WFI, MASK_WFI) +DECLARE_INSN(csrrw, MATCH_CSRRW, MASK_CSRRW) +DECLARE_INSN(csrrs, MATCH_CSRRS, MASK_CSRRS) +DECLARE_INSN(csrrc, MATCH_CSRRC, MASK_CSRRC) +DECLARE_INSN(csrrwi, MATCH_CSRRWI, MASK_CSRRWI) +DECLARE_INSN(csrrsi, MATCH_CSRRSI, MASK_CSRRSI) +DECLARE_INSN(csrrci, MATCH_CSRRCI, MASK_CSRRCI) +DECLARE_INSN(fadd_s, MATCH_FADD_S, MASK_FADD_S) +DECLARE_INSN(fsub_s, MATCH_FSUB_S, MASK_FSUB_S) +DECLARE_INSN(fmul_s, MATCH_FMUL_S, MASK_FMUL_S) +DECLARE_INSN(fdiv_s, MATCH_FDIV_S, MASK_FDIV_S) +DECLARE_INSN(fsgnj_s, MATCH_FSGNJ_S, MASK_FSGNJ_S) +DECLARE_INSN(fsgnjn_s, MATCH_FSGNJN_S, MASK_FSGNJN_S) +DECLARE_INSN(fsgnjx_s, MATCH_FSGNJX_S, MASK_FSGNJX_S) +DECLARE_INSN(fmin_s, MATCH_FMIN_S, MASK_FMIN_S) +DECLARE_INSN(fmax_s, MATCH_FMAX_S, MASK_FMAX_S) +DECLARE_INSN(fsqrt_s, MATCH_FSQRT_S, MASK_FSQRT_S) +DECLARE_INSN(fadd_d, MATCH_FADD_D, MASK_FADD_D) +DECLARE_INSN(fsub_d, MATCH_FSUB_D, MASK_FSUB_D) +DECLARE_INSN(fmul_d, MATCH_FMUL_D, MASK_FMUL_D) +DECLARE_INSN(fdiv_d, MATCH_FDIV_D, MASK_FDIV_D) +DECLARE_INSN(fsgnj_d, MATCH_FSGNJ_D, MASK_FSGNJ_D) +DECLARE_INSN(fsgnjn_d, MATCH_FSGNJN_D, MASK_FSGNJN_D) +DECLARE_INSN(fsgnjx_d, MATCH_FSGNJX_D, MASK_FSGNJX_D) +DECLARE_INSN(fmin_d, MATCH_FMIN_D, MASK_FMIN_D) +DECLARE_INSN(fmax_d, MATCH_FMAX_D, MASK_FMAX_D) +DECLARE_INSN(fcvt_s_d, MATCH_FCVT_S_D, MASK_FCVT_S_D) +DECLARE_INSN(fcvt_d_s, MATCH_FCVT_D_S, MASK_FCVT_D_S) +DECLARE_INSN(fsqrt_d, MATCH_FSQRT_D, MASK_FSQRT_D) +DECLARE_INSN(fle_s, MATCH_FLE_S, MASK_FLE_S) +DECLARE_INSN(flt_s, MATCH_FLT_S, MASK_FLT_S) +DECLARE_INSN(feq_s, MATCH_FEQ_S, MASK_FEQ_S) +DECLARE_INSN(fle_d, MATCH_FLE_D, MASK_FLE_D) +DECLARE_INSN(flt_d, MATCH_FLT_D, MASK_FLT_D) +DECLARE_INSN(feq_d, MATCH_FEQ_D, MASK_FEQ_D) +DECLARE_INSN(fcvt_w_s, MATCH_FCVT_W_S, MASK_FCVT_W_S) +DECLARE_INSN(fcvt_wu_s, MATCH_FCVT_WU_S, MASK_FCVT_WU_S) +DECLARE_INSN(fcvt_l_s, MATCH_FCVT_L_S, MASK_FCVT_L_S) +DECLARE_INSN(fcvt_lu_s, MATCH_FCVT_LU_S, MASK_FCVT_LU_S) +DECLARE_INSN(fmv_x_s, MATCH_FMV_X_S, MASK_FMV_X_S) +DECLARE_INSN(fclass_s, MATCH_FCLASS_S, MASK_FCLASS_S) +DECLARE_INSN(fcvt_w_d, MATCH_FCVT_W_D, MASK_FCVT_W_D) +DECLARE_INSN(fcvt_wu_d, MATCH_FCVT_WU_D, MASK_FCVT_WU_D) +DECLARE_INSN(fcvt_l_d, MATCH_FCVT_L_D, MASK_FCVT_L_D) +DECLARE_INSN(fcvt_lu_d, MATCH_FCVT_LU_D, MASK_FCVT_LU_D) +DECLARE_INSN(fmv_x_d, MATCH_FMV_X_D, MASK_FMV_X_D) +DECLARE_INSN(fclass_d, MATCH_FCLASS_D, MASK_FCLASS_D) +DECLARE_INSN(fcvt_s_w, MATCH_FCVT_S_W, MASK_FCVT_S_W) +DECLARE_INSN(fcvt_s_wu, MATCH_FCVT_S_WU, MASK_FCVT_S_WU) +DECLARE_INSN(fcvt_s_l, MATCH_FCVT_S_L, MASK_FCVT_S_L) +DECLARE_INSN(fcvt_s_lu, MATCH_FCVT_S_LU, MASK_FCVT_S_LU) +DECLARE_INSN(fmv_s_x, MATCH_FMV_S_X, MASK_FMV_S_X) +DECLARE_INSN(fcvt_d_w, MATCH_FCVT_D_W, MASK_FCVT_D_W) +DECLARE_INSN(fcvt_d_wu, MATCH_FCVT_D_WU, MASK_FCVT_D_WU) +DECLARE_INSN(fcvt_d_l, MATCH_FCVT_D_L, MASK_FCVT_D_L) +DECLARE_INSN(fcvt_d_lu, MATCH_FCVT_D_LU, MASK_FCVT_D_LU) +DECLARE_INSN(fmv_d_x, MATCH_FMV_D_X, MASK_FMV_D_X) +DECLARE_INSN(flw, MATCH_FLW, MASK_FLW) +DECLARE_INSN(fld, MATCH_FLD, MASK_FLD) +DECLARE_INSN(fsw, MATCH_FSW, MASK_FSW) +DECLARE_INSN(fsd, MATCH_FSD, MASK_FSD) +DECLARE_INSN(fmadd_s, MATCH_FMADD_S, MASK_FMADD_S) +DECLARE_INSN(fmsub_s, MATCH_FMSUB_S, MASK_FMSUB_S) +DECLARE_INSN(fnmsub_s, MATCH_FNMSUB_S, MASK_FNMSUB_S) +DECLARE_INSN(fnmadd_s, MATCH_FNMADD_S, MASK_FNMADD_S) +DECLARE_INSN(fmadd_d, MATCH_FMADD_D, MASK_FMADD_D) +DECLARE_INSN(fmsub_d, MATCH_FMSUB_D, MASK_FMSUB_D) +DECLARE_INSN(fnmsub_d, MATCH_FNMSUB_D, MASK_FNMSUB_D) +DECLARE_INSN(fnmadd_d, MATCH_FNMADD_D, MASK_FNMADD_D) +DECLARE_INSN(c_nop, MATCH_C_NOP, MASK_C_NOP) +DECLARE_INSN(c_addi16sp, MATCH_C_ADDI16SP, MASK_C_ADDI16SP) +DECLARE_INSN(c_jr, MATCH_C_JR, MASK_C_JR) +DECLARE_INSN(c_jalr, MATCH_C_JALR, MASK_C_JALR) +DECLARE_INSN(c_ebreak, MATCH_C_EBREAK, MASK_C_EBREAK) +DECLARE_INSN(c_ld, MATCH_C_LD, MASK_C_LD) +DECLARE_INSN(c_sd, MATCH_C_SD, MASK_C_SD) +DECLARE_INSN(c_addiw, MATCH_C_ADDIW, MASK_C_ADDIW) +DECLARE_INSN(c_ldsp, MATCH_C_LDSP, MASK_C_LDSP) +DECLARE_INSN(c_sdsp, MATCH_C_SDSP, MASK_C_SDSP) +DECLARE_INSN(c_addi4spn, MATCH_C_ADDI4SPN, MASK_C_ADDI4SPN) +DECLARE_INSN(c_fld, MATCH_C_FLD, MASK_C_FLD) +DECLARE_INSN(c_lw, MATCH_C_LW, MASK_C_LW) +DECLARE_INSN(c_flw, MATCH_C_FLW, MASK_C_FLW) +DECLARE_INSN(c_fsd, MATCH_C_FSD, MASK_C_FSD) +DECLARE_INSN(c_sw, MATCH_C_SW, MASK_C_SW) +DECLARE_INSN(c_fsw, MATCH_C_FSW, MASK_C_FSW) +DECLARE_INSN(c_addi, MATCH_C_ADDI, MASK_C_ADDI) +DECLARE_INSN(c_jal, MATCH_C_JAL, MASK_C_JAL) +DECLARE_INSN(c_li, MATCH_C_LI, MASK_C_LI) +DECLARE_INSN(c_lui, MATCH_C_LUI, MASK_C_LUI) +DECLARE_INSN(c_srli, MATCH_C_SRLI, MASK_C_SRLI) +DECLARE_INSN(c_srai, MATCH_C_SRAI, MASK_C_SRAI) +DECLARE_INSN(c_andi, MATCH_C_ANDI, MASK_C_ANDI) +DECLARE_INSN(c_sub, MATCH_C_SUB, MASK_C_SUB) +DECLARE_INSN(c_xor, MATCH_C_XOR, MASK_C_XOR) +DECLARE_INSN(c_or, MATCH_C_OR, MASK_C_OR) +DECLARE_INSN(c_and, MATCH_C_AND, MASK_C_AND) +DECLARE_INSN(c_subw, MATCH_C_SUBW, MASK_C_SUBW) +DECLARE_INSN(c_addw, MATCH_C_ADDW, MASK_C_ADDW) +DECLARE_INSN(c_j, MATCH_C_J, MASK_C_J) +DECLARE_INSN(c_beqz, MATCH_C_BEQZ, MASK_C_BEQZ) +DECLARE_INSN(c_bnez, MATCH_C_BNEZ, MASK_C_BNEZ) +DECLARE_INSN(c_slli, MATCH_C_SLLI, MASK_C_SLLI) +DECLARE_INSN(c_fldsp, MATCH_C_FLDSP, MASK_C_FLDSP) +DECLARE_INSN(c_lwsp, MATCH_C_LWSP, MASK_C_LWSP) +DECLARE_INSN(c_flwsp, MATCH_C_FLWSP, MASK_C_FLWSP) +DECLARE_INSN(c_mv, MATCH_C_MV, MASK_C_MV) +DECLARE_INSN(c_add, MATCH_C_ADD, MASK_C_ADD) +DECLARE_INSN(c_fsdsp, MATCH_C_FSDSP, MASK_C_FSDSP) +DECLARE_INSN(c_swsp, MATCH_C_SWSP, MASK_C_SWSP) +DECLARE_INSN(c_fswsp, MATCH_C_FSWSP, MASK_C_FSWSP) +DECLARE_INSN(custom0, MATCH_CUSTOM0, MASK_CUSTOM0) +DECLARE_INSN(custom0_rs1, MATCH_CUSTOM0_RS1, MASK_CUSTOM0_RS1) +DECLARE_INSN(custom0_rs1_rs2, MATCH_CUSTOM0_RS1_RS2, MASK_CUSTOM0_RS1_RS2) +DECLARE_INSN(custom0_rd, MATCH_CUSTOM0_RD, MASK_CUSTOM0_RD) +DECLARE_INSN(custom0_rd_rs1, MATCH_CUSTOM0_RD_RS1, MASK_CUSTOM0_RD_RS1) +DECLARE_INSN(custom0_rd_rs1_rs2, MATCH_CUSTOM0_RD_RS1_RS2, MASK_CUSTOM0_RD_RS1_RS2) +DECLARE_INSN(custom1, MATCH_CUSTOM1, MASK_CUSTOM1) +DECLARE_INSN(custom1_rs1, MATCH_CUSTOM1_RS1, MASK_CUSTOM1_RS1) +DECLARE_INSN(custom1_rs1_rs2, MATCH_CUSTOM1_RS1_RS2, MASK_CUSTOM1_RS1_RS2) +DECLARE_INSN(custom1_rd, MATCH_CUSTOM1_RD, MASK_CUSTOM1_RD) +DECLARE_INSN(custom1_rd_rs1, MATCH_CUSTOM1_RD_RS1, MASK_CUSTOM1_RD_RS1) +DECLARE_INSN(custom1_rd_rs1_rs2, MATCH_CUSTOM1_RD_RS1_RS2, MASK_CUSTOM1_RD_RS1_RS2) +DECLARE_INSN(custom2, MATCH_CUSTOM2, MASK_CUSTOM2) +DECLARE_INSN(custom2_rs1, MATCH_CUSTOM2_RS1, MASK_CUSTOM2_RS1) +DECLARE_INSN(custom2_rs1_rs2, MATCH_CUSTOM2_RS1_RS2, MASK_CUSTOM2_RS1_RS2) +DECLARE_INSN(custom2_rd, MATCH_CUSTOM2_RD, MASK_CUSTOM2_RD) +DECLARE_INSN(custom2_rd_rs1, MATCH_CUSTOM2_RD_RS1, MASK_CUSTOM2_RD_RS1) +DECLARE_INSN(custom2_rd_rs1_rs2, MATCH_CUSTOM2_RD_RS1_RS2, MASK_CUSTOM2_RD_RS1_RS2) +DECLARE_INSN(custom3, MATCH_CUSTOM3, MASK_CUSTOM3) +DECLARE_INSN(custom3_rs1, MATCH_CUSTOM3_RS1, MASK_CUSTOM3_RS1) +DECLARE_INSN(custom3_rs1_rs2, MATCH_CUSTOM3_RS1_RS2, MASK_CUSTOM3_RS1_RS2) +DECLARE_INSN(custom3_rd, MATCH_CUSTOM3_RD, MASK_CUSTOM3_RD) +DECLARE_INSN(custom3_rd_rs1, MATCH_CUSTOM3_RD_RS1, MASK_CUSTOM3_RD_RS1) +DECLARE_INSN(custom3_rd_rs1_rs2, MATCH_CUSTOM3_RD_RS1_RS2, MASK_CUSTOM3_RD_RS1_RS2) +#endif +#if defined(DECLARE_CSR) +DECLARE_CSR(fflags, CSR_FFLAGS) +DECLARE_CSR(frm, CSR_FRM) +DECLARE_CSR(fcsr, CSR_FCSR) +DECLARE_CSR(cycle, CSR_CYCLE) +DECLARE_CSR(time, CSR_TIME) +DECLARE_CSR(instret, CSR_INSTRET) +DECLARE_CSR(hpmcounter3, CSR_HPMCOUNTER3) +DECLARE_CSR(hpmcounter4, CSR_HPMCOUNTER4) +DECLARE_CSR(hpmcounter5, CSR_HPMCOUNTER5) +DECLARE_CSR(hpmcounter6, CSR_HPMCOUNTER6) +DECLARE_CSR(hpmcounter7, CSR_HPMCOUNTER7) +DECLARE_CSR(hpmcounter8, CSR_HPMCOUNTER8) +DECLARE_CSR(hpmcounter9, CSR_HPMCOUNTER9) +DECLARE_CSR(hpmcounter10, CSR_HPMCOUNTER10) +DECLARE_CSR(hpmcounter11, CSR_HPMCOUNTER11) +DECLARE_CSR(hpmcounter12, CSR_HPMCOUNTER12) +DECLARE_CSR(hpmcounter13, CSR_HPMCOUNTER13) +DECLARE_CSR(hpmcounter14, CSR_HPMCOUNTER14) +DECLARE_CSR(hpmcounter15, CSR_HPMCOUNTER15) +DECLARE_CSR(hpmcounter16, CSR_HPMCOUNTER16) +DECLARE_CSR(hpmcounter17, CSR_HPMCOUNTER17) +DECLARE_CSR(hpmcounter18, CSR_HPMCOUNTER18) +DECLARE_CSR(hpmcounter19, CSR_HPMCOUNTER19) +DECLARE_CSR(hpmcounter20, CSR_HPMCOUNTER20) +DECLARE_CSR(hpmcounter21, CSR_HPMCOUNTER21) +DECLARE_CSR(hpmcounter22, CSR_HPMCOUNTER22) +DECLARE_CSR(hpmcounter23, CSR_HPMCOUNTER23) +DECLARE_CSR(hpmcounter24, CSR_HPMCOUNTER24) +DECLARE_CSR(hpmcounter25, CSR_HPMCOUNTER25) +DECLARE_CSR(hpmcounter26, CSR_HPMCOUNTER26) +DECLARE_CSR(hpmcounter27, CSR_HPMCOUNTER27) +DECLARE_CSR(hpmcounter28, CSR_HPMCOUNTER28) +DECLARE_CSR(hpmcounter29, CSR_HPMCOUNTER29) +DECLARE_CSR(hpmcounter30, CSR_HPMCOUNTER30) +DECLARE_CSR(hpmcounter31, CSR_HPMCOUNTER31) +DECLARE_CSR(sstatus, CSR_SSTATUS) +DECLARE_CSR(sie, CSR_SIE) +DECLARE_CSR(stvec, CSR_STVEC) +DECLARE_CSR(sscratch, CSR_SSCRATCH) +DECLARE_CSR(sepc, CSR_SEPC) +DECLARE_CSR(scause, CSR_SCAUSE) +DECLARE_CSR(sbadaddr, CSR_SBADADDR) +DECLARE_CSR(sip, CSR_SIP) +DECLARE_CSR(sptbr, CSR_SPTBR) +DECLARE_CSR(mstatus, CSR_MSTATUS) +DECLARE_CSR(misa, CSR_MISA) +DECLARE_CSR(medeleg, CSR_MEDELEG) +DECLARE_CSR(mideleg, CSR_MIDELEG) +DECLARE_CSR(mie, CSR_MIE) +DECLARE_CSR(mtvec, CSR_MTVEC) +DECLARE_CSR(mscratch, CSR_MSCRATCH) +DECLARE_CSR(mepc, CSR_MEPC) +DECLARE_CSR(mcause, CSR_MCAUSE) +DECLARE_CSR(mbadaddr, CSR_MBADADDR) +DECLARE_CSR(mip, CSR_MIP) +DECLARE_CSR(tselect, CSR_TSELECT) +DECLARE_CSR(tdata1, CSR_TDATA1) +DECLARE_CSR(tdata2, CSR_TDATA2) +DECLARE_CSR(tdata3, CSR_TDATA3) +DECLARE_CSR(dcsr, CSR_DCSR) +DECLARE_CSR(dpc, CSR_DPC) +DECLARE_CSR(dscratch, CSR_DSCRATCH) +DECLARE_CSR(mcycle, CSR_MCYCLE) +DECLARE_CSR(minstret, CSR_MINSTRET) +DECLARE_CSR(mhpmcounter3, CSR_MHPMCOUNTER3) +DECLARE_CSR(mhpmcounter4, CSR_MHPMCOUNTER4) +DECLARE_CSR(mhpmcounter5, CSR_MHPMCOUNTER5) +DECLARE_CSR(mhpmcounter6, CSR_MHPMCOUNTER6) +DECLARE_CSR(mhpmcounter7, CSR_MHPMCOUNTER7) +DECLARE_CSR(mhpmcounter8, CSR_MHPMCOUNTER8) +DECLARE_CSR(mhpmcounter9, CSR_MHPMCOUNTER9) +DECLARE_CSR(mhpmcounter10, CSR_MHPMCOUNTER10) +DECLARE_CSR(mhpmcounter11, CSR_MHPMCOUNTER11) +DECLARE_CSR(mhpmcounter12, CSR_MHPMCOUNTER12) +DECLARE_CSR(mhpmcounter13, CSR_MHPMCOUNTER13) +DECLARE_CSR(mhpmcounter14, CSR_MHPMCOUNTER14) +DECLARE_CSR(mhpmcounter15, CSR_MHPMCOUNTER15) +DECLARE_CSR(mhpmcounter16, CSR_MHPMCOUNTER16) +DECLARE_CSR(mhpmcounter17, CSR_MHPMCOUNTER17) +DECLARE_CSR(mhpmcounter18, CSR_MHPMCOUNTER18) +DECLARE_CSR(mhpmcounter19, CSR_MHPMCOUNTER19) +DECLARE_CSR(mhpmcounter20, CSR_MHPMCOUNTER20) +DECLARE_CSR(mhpmcounter21, CSR_MHPMCOUNTER21) +DECLARE_CSR(mhpmcounter22, CSR_MHPMCOUNTER22) +DECLARE_CSR(mhpmcounter23, CSR_MHPMCOUNTER23) +DECLARE_CSR(mhpmcounter24, CSR_MHPMCOUNTER24) +DECLARE_CSR(mhpmcounter25, CSR_MHPMCOUNTER25) +DECLARE_CSR(mhpmcounter26, CSR_MHPMCOUNTER26) +DECLARE_CSR(mhpmcounter27, CSR_MHPMCOUNTER27) +DECLARE_CSR(mhpmcounter28, CSR_MHPMCOUNTER28) +DECLARE_CSR(mhpmcounter29, CSR_MHPMCOUNTER29) +DECLARE_CSR(mhpmcounter30, CSR_MHPMCOUNTER30) +DECLARE_CSR(mhpmcounter31, CSR_MHPMCOUNTER31) +DECLARE_CSR(mucounteren, CSR_MUCOUNTEREN) +DECLARE_CSR(mscounteren, CSR_MSCOUNTEREN) +DECLARE_CSR(mhpmevent3, CSR_MHPMEVENT3) +DECLARE_CSR(mhpmevent4, CSR_MHPMEVENT4) +DECLARE_CSR(mhpmevent5, CSR_MHPMEVENT5) +DECLARE_CSR(mhpmevent6, CSR_MHPMEVENT6) +DECLARE_CSR(mhpmevent7, CSR_MHPMEVENT7) +DECLARE_CSR(mhpmevent8, CSR_MHPMEVENT8) +DECLARE_CSR(mhpmevent9, CSR_MHPMEVENT9) +DECLARE_CSR(mhpmevent10, CSR_MHPMEVENT10) +DECLARE_CSR(mhpmevent11, CSR_MHPMEVENT11) +DECLARE_CSR(mhpmevent12, CSR_MHPMEVENT12) +DECLARE_CSR(mhpmevent13, CSR_MHPMEVENT13) +DECLARE_CSR(mhpmevent14, CSR_MHPMEVENT14) +DECLARE_CSR(mhpmevent15, CSR_MHPMEVENT15) +DECLARE_CSR(mhpmevent16, CSR_MHPMEVENT16) +DECLARE_CSR(mhpmevent17, CSR_MHPMEVENT17) +DECLARE_CSR(mhpmevent18, CSR_MHPMEVENT18) +DECLARE_CSR(mhpmevent19, CSR_MHPMEVENT19) +DECLARE_CSR(mhpmevent20, CSR_MHPMEVENT20) +DECLARE_CSR(mhpmevent21, CSR_MHPMEVENT21) +DECLARE_CSR(mhpmevent22, CSR_MHPMEVENT22) +DECLARE_CSR(mhpmevent23, CSR_MHPMEVENT23) +DECLARE_CSR(mhpmevent24, CSR_MHPMEVENT24) +DECLARE_CSR(mhpmevent25, CSR_MHPMEVENT25) +DECLARE_CSR(mhpmevent26, CSR_MHPMEVENT26) +DECLARE_CSR(mhpmevent27, CSR_MHPMEVENT27) +DECLARE_CSR(mhpmevent28, CSR_MHPMEVENT28) +DECLARE_CSR(mhpmevent29, CSR_MHPMEVENT29) +DECLARE_CSR(mhpmevent30, CSR_MHPMEVENT30) +DECLARE_CSR(mhpmevent31, CSR_MHPMEVENT31) +DECLARE_CSR(mvendorid, CSR_MVENDORID) +DECLARE_CSR(marchid, CSR_MARCHID) +DECLARE_CSR(mimpid, CSR_MIMPID) +DECLARE_CSR(mhartid, CSR_MHARTID) +DECLARE_CSR(cycleh, CSR_CYCLEH) +DECLARE_CSR(timeh, CSR_TIMEH) +DECLARE_CSR(instreth, CSR_INSTRETH) +DECLARE_CSR(hpmcounter3h, CSR_HPMCOUNTER3H) +DECLARE_CSR(hpmcounter4h, CSR_HPMCOUNTER4H) +DECLARE_CSR(hpmcounter5h, CSR_HPMCOUNTER5H) +DECLARE_CSR(hpmcounter6h, CSR_HPMCOUNTER6H) +DECLARE_CSR(hpmcounter7h, CSR_HPMCOUNTER7H) +DECLARE_CSR(hpmcounter8h, CSR_HPMCOUNTER8H) +DECLARE_CSR(hpmcounter9h, CSR_HPMCOUNTER9H) +DECLARE_CSR(hpmcounter10h, CSR_HPMCOUNTER10H) +DECLARE_CSR(hpmcounter11h, CSR_HPMCOUNTER11H) +DECLARE_CSR(hpmcounter12h, CSR_HPMCOUNTER12H) +DECLARE_CSR(hpmcounter13h, CSR_HPMCOUNTER13H) +DECLARE_CSR(hpmcounter14h, CSR_HPMCOUNTER14H) +DECLARE_CSR(hpmcounter15h, CSR_HPMCOUNTER15H) +DECLARE_CSR(hpmcounter16h, CSR_HPMCOUNTER16H) +DECLARE_CSR(hpmcounter17h, CSR_HPMCOUNTER17H) +DECLARE_CSR(hpmcounter18h, CSR_HPMCOUNTER18H) +DECLARE_CSR(hpmcounter19h, CSR_HPMCOUNTER19H) +DECLARE_CSR(hpmcounter20h, CSR_HPMCOUNTER20H) +DECLARE_CSR(hpmcounter21h, CSR_HPMCOUNTER21H) +DECLARE_CSR(hpmcounter22h, CSR_HPMCOUNTER22H) +DECLARE_CSR(hpmcounter23h, CSR_HPMCOUNTER23H) +DECLARE_CSR(hpmcounter24h, CSR_HPMCOUNTER24H) +DECLARE_CSR(hpmcounter25h, CSR_HPMCOUNTER25H) +DECLARE_CSR(hpmcounter26h, CSR_HPMCOUNTER26H) +DECLARE_CSR(hpmcounter27h, CSR_HPMCOUNTER27H) +DECLARE_CSR(hpmcounter28h, CSR_HPMCOUNTER28H) +DECLARE_CSR(hpmcounter29h, CSR_HPMCOUNTER29H) +DECLARE_CSR(hpmcounter30h, CSR_HPMCOUNTER30H) +DECLARE_CSR(hpmcounter31h, CSR_HPMCOUNTER31H) +DECLARE_CSR(mcycleh, CSR_MCYCLEH) +DECLARE_CSR(minstreth, CSR_MINSTRETH) +DECLARE_CSR(mhpmcounter3h, CSR_MHPMCOUNTER3H) +DECLARE_CSR(mhpmcounter4h, CSR_MHPMCOUNTER4H) +DECLARE_CSR(mhpmcounter5h, CSR_MHPMCOUNTER5H) +DECLARE_CSR(mhpmcounter6h, CSR_MHPMCOUNTER6H) +DECLARE_CSR(mhpmcounter7h, CSR_MHPMCOUNTER7H) +DECLARE_CSR(mhpmcounter8h, CSR_MHPMCOUNTER8H) +DECLARE_CSR(mhpmcounter9h, CSR_MHPMCOUNTER9H) +DECLARE_CSR(mhpmcounter10h, CSR_MHPMCOUNTER10H) +DECLARE_CSR(mhpmcounter11h, CSR_MHPMCOUNTER11H) +DECLARE_CSR(mhpmcounter12h, CSR_MHPMCOUNTER12H) +DECLARE_CSR(mhpmcounter13h, CSR_MHPMCOUNTER13H) +DECLARE_CSR(mhpmcounter14h, CSR_MHPMCOUNTER14H) +DECLARE_CSR(mhpmcounter15h, CSR_MHPMCOUNTER15H) +DECLARE_CSR(mhpmcounter16h, CSR_MHPMCOUNTER16H) +DECLARE_CSR(mhpmcounter17h, CSR_MHPMCOUNTER17H) +DECLARE_CSR(mhpmcounter18h, CSR_MHPMCOUNTER18H) +DECLARE_CSR(mhpmcounter19h, CSR_MHPMCOUNTER19H) +DECLARE_CSR(mhpmcounter20h, CSR_MHPMCOUNTER20H) +DECLARE_CSR(mhpmcounter21h, CSR_MHPMCOUNTER21H) +DECLARE_CSR(mhpmcounter22h, CSR_MHPMCOUNTER22H) +DECLARE_CSR(mhpmcounter23h, CSR_MHPMCOUNTER23H) +DECLARE_CSR(mhpmcounter24h, CSR_MHPMCOUNTER24H) +DECLARE_CSR(mhpmcounter25h, CSR_MHPMCOUNTER25H) +DECLARE_CSR(mhpmcounter26h, CSR_MHPMCOUNTER26H) +DECLARE_CSR(mhpmcounter27h, CSR_MHPMCOUNTER27H) +DECLARE_CSR(mhpmcounter28h, CSR_MHPMCOUNTER28H) +DECLARE_CSR(mhpmcounter29h, CSR_MHPMCOUNTER29H) +DECLARE_CSR(mhpmcounter30h, CSR_MHPMCOUNTER30H) +DECLARE_CSR(mhpmcounter31h, CSR_MHPMCOUNTER31H) +#endif +#if defined(DECLARE_CAUSE) +DECLARE_CAUSE("misaligned fetch", CAUSE_MISALIGNED_FETCH) +DECLARE_CAUSE("fault fetch", CAUSE_FAULT_FETCH) +DECLARE_CAUSE("illegal instruction", CAUSE_ILLEGAL_INSTRUCTION) +DECLARE_CAUSE("breakpoint", CAUSE_BREAKPOINT) +DECLARE_CAUSE("misaligned load", CAUSE_MISALIGNED_LOAD) +DECLARE_CAUSE("fault load", CAUSE_FAULT_LOAD) +DECLARE_CAUSE("misaligned store", CAUSE_MISALIGNED_STORE) +DECLARE_CAUSE("fault store", CAUSE_FAULT_STORE) +DECLARE_CAUSE("user_ecall", CAUSE_USER_ECALL) +DECLARE_CAUSE("supervisor_ecall", CAUSE_SUPERVISOR_ECALL) +DECLARE_CAUSE("hypervisor_ecall", CAUSE_HYPERVISOR_ECALL) +DECLARE_CAUSE("machine_ecall", CAUSE_MACHINE_ECALL) +#endif + diff --git a/Ubiquitous/XiZi/board/aiit-riscv64-board/include/entry.h b/Ubiquitous/XiZi/board/aiit-riscv64-board/include/entry.h new file mode 100644 index 0000000..41ff295 --- /dev/null +++ b/Ubiquitous/XiZi/board/aiit-riscv64-board/include/entry.h @@ -0,0 +1,90 @@ +/* Copyright 2018 Canaan Inc. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/** +* @file entry.h +* @brief add from Canaan K210 SDK +* https://canaan-creative.com/developer +* @version 1.0 +* @author AIIT XUOS Lab +* @date 2021-04-25 +*/ + +#ifndef _BSP_ENTRY_H +#define _BSP_ENTRY_H + +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +typedef int (*core_function)(void *ctx); + +typedef struct _core_instance_t +{ + core_function callback; + void *ctx; +} core_instance_t; + +int register_core1(core_function func, void *ctx); + +static inline void init_lma(void) +{ + extern unsigned int _data_lma; + extern unsigned int _data; + extern unsigned int _edata; + unsigned int *src, *dst; + + src = &_data_lma; + dst = &_data; + while (dst < &_edata) + *dst++ = *src++; +} + +static inline void init_bss(void) +{ + extern unsigned int _bss; + extern unsigned int _ebss; + unsigned int *dst; + + dst = &_bss; + while (dst < &_ebss) + *dst++ = 0; +} + +static inline void init_tls(void) +{ + register void *task_pointer asm("tp"); + extern char _tls_data; + + extern __thread char _tdata_begin, _tdata_end, _tbss_end; + + size_t tdata_size = &_tdata_end - &_tdata_begin; + + memcpy(task_pointer, &_tls_data, tdata_size); + + size_t tbss_size = &_tbss_end - &_tdata_end; + + memset(task_pointer + tdata_size, 0, tbss_size); +} + +#ifdef __cplusplus +} +#endif + +#endif /* _BSP_ENTRY_H */ + diff --git a/Ubiquitous/XiZi/board/aiit-riscv64-board/include/interrupt.h b/Ubiquitous/XiZi/board/aiit-riscv64-board/include/interrupt.h new file mode 100644 index 0000000..847b5fd --- /dev/null +++ b/Ubiquitous/XiZi/board/aiit-riscv64-board/include/interrupt.h @@ -0,0 +1,56 @@ +/* Copyright 2018 Canaan Inc. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/** +* @file interrupt.h +* @brief add from Canaan K210 SDK +* https://canaan-creative.com/developer +* @version 1.0 +* @author AIIT XUOS Lab +* @date 2021-04-25 +*/ + +#ifndef _BSP_INTERRUPT_H +#define _BSP_INTERRUPT_H + +#ifdef __cplusplus +extern "C" { +#endif +/* clang-format off */ +/* Machine interrupt mask for 64 bit system, 0x8000 0000 0000 0000 */ +#define CAUSE_MACHINE_IRQ_MASK (0x1ULL << 63) + +/* Machine interrupt reason mask for 64 bit system, 0x7FFF FFFF FFFF FFFF */ +#define CAUSE_MACHINE_IRQ_REASON_MASK (CAUSE_MACHINE_IRQ_MASK - 1) + +/* Hypervisor interrupt mask for 64 bit system, 0x8000 0000 0000 0000 */ +#define CAUSE_HYPERVISOR_IRQ_MASK (0x1ULL << 63) + +/* Hypervisor interrupt reason mask for 64 bit system, 0x7FFF FFFF FFFF FFFF */ +#define CAUSE_HYPERVISOR_IRQ_REASON_MASK (CAUSE_HYPERVISOR_IRQ_MASK - 1) + +/* Supervisor interrupt mask for 64 bit system, 0x8000 0000 0000 0000 */ +#define CAUSE_SUPERVISOR_IRQ_MASK (0x1ULL << 63) + +/* Supervisor interrupt reason mask for 64 bit system, 0x7FFF FFFF FFFF FFFF */ +#define CAUSE_SUPERVISOR_IRQ_REASON_MASK (CAUSE_SUPERVISOR_IRQ_MASK - 1) +/* clang-format on */ + +#ifdef __cplusplus +} +#endif + +#endif /* _BSP_INTERRUPT_H */ + diff --git a/Ubiquitous/XiZi/board/aiit-riscv64-board/include/platform.h b/Ubiquitous/XiZi/board/aiit-riscv64-board/include/platform.h new file mode 100644 index 0000000..c30e417 --- /dev/null +++ b/Ubiquitous/XiZi/board/aiit-riscv64-board/include/platform.h @@ -0,0 +1,108 @@ +/* Copyright 2018 Canaan Inc. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/** +* @file platform.h +* @brief add from Canaan K210 SDK +* https://canaan-creative.com/developer +* @version 1.0 +* @author AIIT XUOS Lab +* @date 2021-04-25 +*/ + +#ifndef _BSP_PLATFORM_H +#define _BSP_PLATFORM_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* clang-format off */ +/* Register base address */ + +/* Under Coreplex */ +#define CLINT_BASE_ADDR (0x02000000U) +#define PLIC_BASE_ADDR (0x0C000000U) + +/* Under TileLink */ +#define UARTHS_BASE_ADDR (0x38000000U) +#define GPIOHS_BASE_ADDR (0x38001000U) + +/* Under AXI 64 bit */ +#define RAM_BASE_ADDR (0x80000000U) +#define RAM_SIZE (6 * 1024 * 1024U) + +#define IO_BASE_ADDR (0x40000000U) +#define IO_SIZE (6 * 1024 * 1024U) + +#define AI_RAM_BASE_ADDR (0x80600000U) +#define AI_RAM_SIZE (2 * 1024 * 1024U) + +#define AI_IO_BASE_ADDR (0x40600000U) +#define AI_IO_SIZE (2 * 1024 * 1024U) + +#define AI_BASE_ADDR (0x40800000U) +#define AI_SIZE (12 * 1024 * 1024U) + +#define FFT_BASE_ADDR (0x42000000U) +#define FFT_SIZE (4 * 1024 * 1024U) + +#define ROM_BASE_ADDR (0x88000000U) +#define ROM_SIZE (128 * 1024U) + +/* Under AHB 32 bit */ +#define DMAC_BASE_ADDR (0x50000000U) + +/* Under APB1 32 bit */ +#define GPIO_BASE_ADDR (0x50200000U) +#define UART1_BASE_ADDR (0x50210000U) +#define UART2_BASE_ADDR (0x50220000U) +#define UART3_BASE_ADDR (0x50230000U) +#define SPI_SLAVE_BASE_ADDR (0x50240000U) +#define I2S0_BASE_ADDR (0x50250000U) +#define I2S1_BASE_ADDR (0x50260000U) +#define I2S2_BASE_ADDR (0x50270000U) +#define I2C0_BASE_ADDR (0x50280000U) +#define I2C1_BASE_ADDR (0x50290000U) +#define I2C2_BASE_ADDR (0x502A0000U) +#define FPIOA_BASE_ADDR (0x502B0000U) +#define SHA256_BASE_ADDR (0x502C0000U) +#define TIMER0_BASE_ADDR (0x502D0000U) +#define TIMER1_BASE_ADDR (0x502E0000U) +#define TIMER2_BASE_ADDR (0x502F0000U) + +/* Under APB2 32 bit */ +#define WDT0_BASE_ADDR (0x50400000U) +#define WDT1_BASE_ADDR (0x50410000U) +#define OTP_BASE_ADDR (0x50420000U) +#define DVP_BASE_ADDR (0x50430000U) +#define SYSCTL_BASE_ADDR (0x50440000U) +#define AES_BASE_ADDR (0x50450000U) +#define RTC_BASE_ADDR (0x50460000U) + + +/* Under APB3 32 bit */ +#define SPI0_BASE_ADDR (0x52000000U) +#define SPI1_BASE_ADDR (0x53000000U) +#define SPI3_BASE_ADDR (0x54000000U) + +/* clang-format on */ + +#ifdef __cplusplus +} +#endif + +#endif /* _BSP_PLATFORM_H */ + diff --git a/Ubiquitous/XiZi/board/aiit-riscv64-board/include/printf.h b/Ubiquitous/XiZi/board/aiit-riscv64-board/include/printf.h new file mode 100644 index 0000000..c41b3e4 --- /dev/null +++ b/Ubiquitous/XiZi/board/aiit-riscv64-board/include/printf.h @@ -0,0 +1,218 @@ +/** + * File: printf.h + * + * Copyright (c) 2004,2012 Kustaa Nyholm / SpareTimeLabs + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Kustaa Nyholm or SpareTimeLabs nor the + * names of its contributors may be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDER BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library; if not, write to the Free Software Foundation, + * Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * This library is really just two files: 'tinyprintf.h' and 'tinyprintf.c'. + * + * They provide a simple and small (+400 loc) printf functionality to be used + * in embedded systems. + * + * I've found them so useful in debugging that I do not bother with a debugger + * at all. + * + * They are distributed in source form, so to use them, just compile them into + * your project. + * + * Two printf variants are provided: printf and the 'sprintf' family of + * functions ('snprintf', 'sprintf', 'vsnprintf', 'vsprintf'). + * + * The formats supported by this implementation are: 'c' 'd' 'i' 'o' 'p' 'u' + * 's' 'x' 'X'. + * + * Zero padding, field width, and precision are also supported. + * + * If the library is compiled with 'PRINTF_SUPPORT_LONG' defined, then the + * long specifier is also supported. Note that this will pull in some long + * math routines (pun intended!) and thus make your executable noticeably + * longer. Likewise with 'PRINTF_LONG_LONG_SUPPORT' for the long long + * specifier, and with 'PRINTF_SIZE_T_SUPPORT' for the size_t specifier. + * + * The memory footprint of course depends on the target CPU, compiler and + * compiler options, but a rough guesstimate (based on a H8S target) is about + * 1.4 kB for code and some twenty 'int's and 'char's, say 60 bytes of stack + * space. Not too bad. Your mileage may vary. By hacking the source code you + * can get rid of some hundred bytes, I'm sure, but personally I feel the + * balance of functionality and flexibility versus code size is close to + * optimal for many embedded systems. + * + * To use the printf, you need to supply your own character output function, + * something like : + * + * void putc ( void* p, char c) { while (!SERIAL_PORT_EMPTY) ; + * SERIAL_PORT_TX_REGISTER = c; } + * + * Before you can call printf, you need to initialize it to use your character + * output function with something like: + * + * init_printf(NULL,putc); + * + * Notice the 'NULL' in 'init_printf' and the parameter 'void* p' in 'putc', + * the NULL (or any pointer) you pass into the 'init_printf' will eventually + * be passed to your 'putc' routine. This allows you to pass some storage + * space (or anything really) to the character output function, if necessary. + * This is not often needed but it was implemented like that because it made + * implementing the sprintf function so neat (look at the source code). + * + * The code is re-entrant, except for the 'init_printf' function, so it is + * safe to call it from interrupts too, although this may result in mixed + * output. If you rely on re-entrancy, take care that your 'putc' function is + * re-entrant! + * + * The printf and sprintf functions are actually macros that translate to + * 'tfp_printf' and 'tfp_sprintf' when 'TINYPRINTF_OVERRIDE_LIBC' is set + * (default). Setting it to 0 makes it possible to use them along with + * 'stdio.h' printf's in a single source file. When 'TINYPRINTF_OVERRIDE_LIBC' + * is set, please note that printf/sprintf are not function-like macros, so if + * you have variables or struct members with these names, things will explode + * in your face. Without variadic macros this is the best we can do to wrap + * these function. If it is a problem, just give up the macros and use the + * functions directly, or rename them. + * + * It is also possible to avoid defining tfp_printf and/or tfp_sprintf by + * clearing 'TINYPRINTF_DEFINE_TFP_PRINTF' and/or + * 'TINYPRINTF_DEFINE_TFP_SPRINTF' to 0. This allows for example to export + * only tfp_format, which is at the core of all the other functions. + * + * For further details see source code. + * + * regs Kusti, 23.10.2004 + */ + +/** +* @file printf.h +* @brief add from Canaan K210 SDK +* https://canaan-creative.com/developer +* @version 1.0 +* @author AIIT XUOS Lab +* @date 2021-04-25 +*/ + +#ifndef _BSP_PRINTF_H +#define _BSP_PRINTF_H + +#include +#include + +/* Global configuration */ + +/* Set this to 0 if you do not want to provide tfp_printf */ +#ifndef TINYPRINTF_DEFINE_TFP_PRINTF +#define TINYPRINTF_DEFINE_TFP_PRINTF 1 +#endif + +/** + * Set this to 0 if you do not want to provide + * tfp_sprintf/snprintf/vsprintf/vsnprintf + */ +#ifndef TINYPRINTF_DEFINE_TFP_SPRINTF +#define TINYPRINTF_DEFINE_TFP_SPRINTF 1 +#endif + +/** + * Set this to 0 if you do not want tfp_printf and + * tfp_{vsn,sn,vs,s}printf to be also available as + * printf/{vsn,sn,vs,s}printf + */ +#ifndef TINYPRINTF_OVERRIDE_LIBC +#define TINYPRINTF_OVERRIDE_LIBC 0 +#endif + +/* Optional external types dependencies */ + +/* Declarations */ + +#if defined(__GNUC__) +#define _TFP_SPECIFY_PRINTF_FMT(fmt_idx, arg1_idx) \ + __attribute__((format(printf, fmt_idx, arg1_idx))) +#else +#define _TFP_SPECIFY_PRINTF_FMT(fmt_idx, arg1_idx) +#endif + +#ifdef __cplusplus +extern "C" { +#endif + +typedef void (*putcf)(void*, char); + +/** + * 'tfp_format' really is the central function for all tinyprintf. For + * each output character after formatting, the 'putf' callback is + * called with 2 args: + * - an arbitrary void* 'putp' param defined by the user and + * passed unmodified from 'tfp_format', + * - the character. + * The 'tfp_printf' and 'tfp_sprintf' functions simply define their own + * callback and pass to it the right 'putp' it is expecting. + */ +void tfp_format(void *putp, putcf putf, const char *fmt, va_list va); + +#if TINYPRINTF_DEFINE_TFP_SPRINTF +int tfp_vsnprintf(char *str, size_t size, const char *fmt, va_list ap); +int tfp_snprintf(char *str, size_t size, const char *fmt, ...) + _TFP_SPECIFY_PRINTF_FMT(3, 4); +int tfp_vsprintf(char *str, const char *fmt, va_list ap); +int tfp_sprintf(char *str, const char *fmt, ...) _TFP_SPECIFY_PRINTF_FMT(2, 3); +#if TINYPRINTF_OVERRIDE_LIBC +#define vsnprintf tfp_vsnprintf +#define snprintf tfp_snprintf +#define vsprintf tfp_vsprintf +#define sprintf tfp_sprintf +#endif +#endif + +#if TINYPRINTF_DEFINE_TFP_PRINTF +void init_printf(void *putp, putcf putf); +void tfp_printf(char *fmt, ...) _TFP_SPECIFY_PRINTF_FMT(1, 2); +#if TINYPRINTF_OVERRIDE_LIBC +#define printf tfp_printf + +#ifdef __cplusplus +#include +namespace std +{ + template + auto tfp_printf(Args&&... args) -> decltype(::tfp_printf(std::forward(args)...)) + { + return ::tfp_printf(std::forward(args)...); + } +} +#endif +#endif +#endif + +int printk(const char *format, ...) _TFP_SPECIFY_PRINTF_FMT(1, 2); + +#ifdef __cplusplus +} +#endif + +#endif /* _BSP_PRINTF_H */ + diff --git a/Ubiquitous/XiZi/board/aiit-riscv64-board/include/sleep.h b/Ubiquitous/XiZi/board/aiit-riscv64-board/include/sleep.h new file mode 100644 index 0000000..a9da663 --- /dev/null +++ b/Ubiquitous/XiZi/board/aiit-riscv64-board/include/sleep.h @@ -0,0 +1,45 @@ +/* Copyright 2018 Canaan Inc. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/** +* @file sleep.h +* @brief add from Canaan K210 SDK +* https://canaan-creative.com/developer +* @version 1.0 +* @author AIIT XUOS Lab +* @date 2021-04-25 +*/ + +#ifndef _BSP_SLEEP_H +#define _BSP_SLEEP_H + +#include "encoding.h" +#include "clint.h" +#include "syscalls.h" + +#ifdef __cplusplus +extern "C" { +#endif + +int usleep(uint64_t usec); +int msleep(uint64_t msec); +unsigned int sleep(unsigned int seconds); + +#ifdef __cplusplus +} +#endif + +#endif /* _BSP_SLEEP_H */ + diff --git a/Ubiquitous/XiZi/board/aiit-riscv64-board/include/syscalls.h b/Ubiquitous/XiZi/board/aiit-riscv64-board/include/syscalls.h new file mode 100644 index 0000000..1134d51 --- /dev/null +++ b/Ubiquitous/XiZi/board/aiit-riscv64-board/include/syscalls.h @@ -0,0 +1,54 @@ +/* Copyright 2018 Canaan Inc. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/** +* @file syscalls.h +* @brief add from Canaan K210 SDK +* https://canaan-creative.com/developer +* @version 1.0 +* @author AIIT XUOS Lab +* @date 2021-04-25 +*/ + +#ifndef _BSP_SYSCALLS_H +#define _BSP_SYSCALLS_H + +#include +#include +#include +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +void __attribute__((noreturn)) sys_exit(int code); + +void setStats(int enable); + +#undef putchar +int putchar(int ch); +void printstr(const char *s); + +void printhex(uint64_t x); + + +#ifdef __cplusplus +} +#endif + +#endif /* _BSP_SYSCALLS_H */ + diff --git a/Ubiquitous/XiZi/board/aiit-riscv64-board/include/syslog.h b/Ubiquitous/XiZi/board/aiit-riscv64-board/include/syslog.h new file mode 100644 index 0000000..00d25dd --- /dev/null +++ b/Ubiquitous/XiZi/board/aiit-riscv64-board/include/syslog.h @@ -0,0 +1,151 @@ +/* Copyright 2018 Canaan Inc. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/** +* @file syslog.h +* @brief add from Canaan K210 SDK +* https://canaan-creative.com/developer +* @version 1.0 +* @author AIIT XUOS Lab +* @date 2021-04-25 +*/ + +#ifndef _SYSLOG_H +#define _SYSLOG_H + +#include +#include +#include "printf.h" +#include "encoding.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @brief Logging library + * + * Log library has two ways of managing log verbosity: compile time, set via + * menuconfig + * + * At compile time, filtering is done using CONFIG_LOG_DEFAULT_LEVEL macro, set via + * menuconfig. All logging statments for levels higher than CONFIG_LOG_DEFAULT_LEVEL + * will be removed by the preprocessor. + * + * + * How to use this library: + * + * In each C file which uses logging functionality, define TAG variable like this: + * + * static const char *TAG = "MODULE_NAME"; + * + * then use one of logging macros to produce output, e.g: + * + * LOGW(TAG, "Interrupt error %d", error); + * + * Several macros are available for different verbosity levels: + * + * LOGE - error + * LOGW - warning + * LOGI - info + * LOGD - debug + * LOGV - verbose + * + * To override default verbosity level at file or component scope, define LOG_LEVEL macro. + * At file scope, define it before including esp_log.h, e.g.: + * + * #define LOG_LEVEL LOG_VERBOSE + * #include "dxx_log.h" + * + * At component scope, define it in component makefile: + * + * CFLAGS += -D LOG_LEVEL=LOG_DEBUG + * + * + */ + +/* clang-format off */ +typedef enum _kendryte_log_level +{ + LOG_NONE, /*!< No log output */ + LOG_ERROR, /*!< Critical errors, software module can not recover on its own */ + LOG_WARN, /*!< Error conditions from which recovery measures have been taken */ + LOG_INFO, /*!< Information messages which describe normal flow of events */ + LOG_DEBUG, /*!< Extra information which is not necessary for normal use (values, pointers, sizes, etc). */ + LOG_VERBOSE /*!< Bigger chunks of debugging information, or frequent messages which can potentially flood the output. */ +} kendryte_log_level_t ; +/* clang-format on */ + +/* clang-format off */ +#if CONFIG_LOG_COLORS +#define LOG_COLOR_BLACK "30" +#define LOG_COLOR_RED "31" +#define LOG_COLOR_GREEN "32" +#define LOG_COLOR_BROWN "33" +#define LOG_COLOR_BLUE "34" +#define LOG_COLOR_PURPLE "35" +#define LOG_COLOR_CYAN "36" +#define LOG_COLOR(COLOR) "\033[0;" COLOR "m" +#define LOG_BOLD(COLOR) "\033[1;" COLOR "m" +#define LOG_RESET_COLOR "\033[0m" +#define LOG_COLOR_E LOG_COLOR(LOG_COLOR_RED) +#define LOG_COLOR_W LOG_COLOR(LOG_COLOR_BROWN) +#define LOG_COLOR_I LOG_COLOR(LOG_COLOR_GREEN) +#define LOG_COLOR_D +#define LOG_COLOR_V +#else /* CONFIG_LOG_COLORS */ +#define LOG_COLOR_E +#define LOG_COLOR_W +#define LOG_COLOR_I +#define LOG_COLOR_D +#define LOG_COLOR_V +#define LOG_RESET_COLOR +#endif /* CONFIG_LOG_COLORS */ +/* clang-format on */ + +#define LOG_FORMAT(letter, format) LOG_COLOR_ ## letter #letter " (%lu) %s: " format LOG_RESET_COLOR "\n" + +#ifdef LOG_LEVEL +#undef CONFIG_LOG_LEVEL +#define CONFIG_LOG_LEVEL LOG_LEVEL +#endif + +#ifdef LOG_KERNEL +#define LOG_PRINTF printk +#else +#define LOG_PRINTF printf +#endif + +#ifdef CONFIG_LOG_ENABLE +#define LOGE(tag, format, ...) do {if (CONFIG_LOG_LEVEL >= LOG_ERROR) LOG_PRINTF(LOG_FORMAT(E, format), read_cycle(), tag, ##__VA_ARGS__); } while (0) +#define LOGW(tag, format, ...) do {if (CONFIG_LOG_LEVEL >= LOG_WARN) LOG_PRINTF(LOG_FORMAT(W, format), read_cycle(), tag, ##__VA_ARGS__); } while (0) +#define LOGI(tag, format, ...) do {if (CONFIG_LOG_LEVEL >= LOG_INFO) LOG_PRINTF(LOG_FORMAT(I, format), read_cycle(), tag, ##__VA_ARGS__); } while (0) +#define LOGD(tag, format, ...) do {if (CONFIG_LOG_LEVEL >= LOG_DEBUG) LOG_PRINTF(LOG_FORMAT(D, format), read_cycle(), tag, ##__VA_ARGS__); } while (0) +#define LOGV(tag, format, ...) do {if (CONFIG_LOG_LEVEL >= LOG_VERBOSE) LOG_PRINTF(LOG_FORMAT(V, format), read_cycle(), tag, ##__VA_ARGS__); } while (0) +#else +#define LOGE(tag, format, ...) +#define LOGW(tag, format, ...) +#define LOGI(tag, format, ...) +#define LOGD(tag, format, ...) +#define LOGV(tag, format, ...) +#endif /* LOG_ENABLE */ + +#ifdef __cplusplus +} +#endif + + +#endif /* _SYSLOG_H */ + diff --git a/Ubiquitous/XiZi/board/aiit-riscv64-board/include/util.h b/Ubiquitous/XiZi/board/aiit-riscv64-board/include/util.h new file mode 100644 index 0000000..fb766b2 --- /dev/null +++ b/Ubiquitous/XiZi/board/aiit-riscv64-board/include/util.h @@ -0,0 +1,207 @@ +/* Copyright 2018 Canaan Inc. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/** +* @file util.h +* @brief add from Canaan K210 SDK +* https://canaan-creative.com/developer +* @version 1.0 +* @author AIIT XUOS Lab +* @date 2021-04-25 +*/ + +#ifndef _BSP_UTIL_H +#define _BSP_UTIL_H + + +#include +#if defined(__riscv) +#include "encoding.h" +#endif + +#ifdef __cplusplus +extern "C" { +#endif + +#if defined(__GNUC__) +#pragma GCC diagnostic ignored "-Wunused-parameter" +#pragma GCC diagnostic ignored "-Wunused-function" +#endif + +/** + * -------------------------------------------------------------------------- + * Macros + + * Set HOST_DEBUG to 1 if you are going to compile this for a host + * machine (ie Athena/Linux) for debug purposes and set HOST_DEBUG + * to 0 if you are compiling with the smips-gcc toolchain. + */ + +#ifndef HOST_DEBUG +#define HOST_DEBUG 0 +#endif + +/** + * Set PREALLOCATE to 1 if you want to preallocate the benchmark + * function before starting stats. If you have instruction/data + * caches and you don't want to count the overhead of misses, then + * you will need to use preallocation. +*/ + +#ifndef PREALLOCATE +#define PREALLOCATE 0 +#endif + + +#define static_assert(cond) \ + { \ + switch (0) \ + { \ + case 0: \ + case !!(long)(cond):; \ + } \ + } + +#define stringify_1(s) #s +#define stringify(s) stringify_1(s) +#define stats(code, iter) \ + do \ + { \ + unsigned long _c = -read_cycle(), _i = -READ_CSR(minstret); \ + code; \ + _c += read_cycle(), _i += READ_CSR(minstret); \ + if (cid == 0) \ + printf("\r\n%s: %ld cycles, %ld.%ld cycles/iter, %ld.%ld CPI\r\n", \ + stringify(code), _c, _c / iter, 10 * _c / iter % 10, _c / _i, 10 * _c / _i % 10); \ + } while (0) + + +/** + * Set SET_STATS to 1 if you want to carve out the piece that actually + * does the computation. + */ + +#if HOST_DEBUG +#include +static void setStats(int enable) {} +#else +extern void setStats(int enable); +#endif + + +static void printArray(const char name[], int n, const int arr[]) +{ +#if HOST_DEBUG + int i; + + printf(" %10s :", name); + for (i = 0; i < n; i++) + printf(" %3d ", arr[i]); + printf("\r\n"); +#endif +} + +static void printDoubleArray(const char name[], int n, const double arr[]) +{ +#if HOST_DEBUG + int i; + + printf(" %10s :", name); + for (i = 0; i < n; i++) + printf(" %g ", arr[i]); + printf("\r\n"); +#endif +} + +static int verify(int n, const volatile int *test, const int *verify) +{ + int i; + /* Unrolled for faster verification */ + for (i = 0; i < n / 2 * 2; i += 2) + { + int t0 = test[i], t1 = test[i + 1]; + int v0 = verify[i], v1 = verify[i + 1]; + + if (t0 != v0) + return i + 1; + if (t1 != v1) + return i + 2; + } + if (n % 2 != 0 && test[n - 1] != verify[n - 1]) + return n; + return 0; +} + +static int verifyDouble(int n, const volatile double *test, const double *verify) +{ + int i; + /* Unrolled for faster verification */ + for (i = 0; i < n / 2 * 2; i += 2) + { + double t0 = test[i], t1 = test[i + 1]; + double v0 = verify[i], v1 = verify[i + 1]; + int eq1 = t0 == v0, eq2 = t1 == v1; + + if (!(eq1 & eq2)) + return i + 1 + eq1; + } + if (n % 2 != 0 && test[n - 1] != verify[n - 1]) + return n; + return 0; +} + +static void __attribute__((noinline)) barrier(int ncores) +{ + static volatile int sense = 0; + static volatile int count = 0; + + static __thread int threadsense; + + __sync_synchronize(); + + threadsense = !threadsense; + if (__sync_fetch_and_add(&count, 1) == ncores - 1) + { + count = 0; + sense = threadsense; + } + else + { + while (sense != threadsense) + ; + } + + __sync_synchronize(); +} + +static uint64_t lfsr(uint64_t x) +{ + uint64_t bit = (x ^ (x >> 1)) & 1; + + return (x >> 1) | (bit << 62); +} + + +#if defined(__GNUC__) +#pragma GCC diagnostic warning "-Wunused-parameter" +#pragma GCC diagnostic warning "-Wunused-function" +#endif + +#ifdef __cplusplus +} +#endif + +#endif /* _BSP_UTIL_H */ + diff --git a/Ubiquitous/XiZi/board/aiit-riscv64-board/link.lds b/Ubiquitous/XiZi/board/aiit-riscv64-board/link.lds new file mode 100644 index 0000000..1d308d0 --- /dev/null +++ b/Ubiquitous/XiZi/board/aiit-riscv64-board/link.lds @@ -0,0 +1,117 @@ +/* +* Copyright (c) 2020 AIIT XUOS Lab +* XiUOS is licensed under Mulan PSL v2. +* You can use this software according to the terms and conditions of the Mulan PSL v2. +* You may obtain a copy of Mulan PSL v2 at: +* http://license.coscl.org.cn/MulanPSL2 +* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, +* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, +* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. +* See the Mulan PSL v2 for more details. +*/ + +__STACKSIZE__ = 4096; + +OUTPUT_ARCH( "riscv" ) + +MEMORY +{ + sram (wxa!ri): ORIGIN = 0x80000000, LENGTH = ( 6 * 1024 * 1024 ) +} + +ENTRY(_begin) +SECTIONS +{ + .start : + { + *(.start); + } > sram + + . = ALIGN(8); + + .text : + { + PROVIDE( _text = ABSOLUTE(.) ); + + *(.text .text.*) /* Normal code */ + *(.rodata .rodata*) /* read-only data (constants) */ + + /* section information for letter-shell */ + . = ALIGN(8); + _shell_command_start = .; + KEEP (*(shellCommand)) + _shell_command_end = .; + . = ALIGN(8); + + PROVIDE(__ctors_start__ = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array)) + PROVIDE(__ctors_end__ = .); + + . = ALIGN(4); + __isrtbl_idx_start = .; + KEEP(*(.isrtbl.idx)) + __isrtbl_start = .; + KEEP(*(.isrtbl)) + __isrtbl_end = .; + . = ALIGN(8); + + PROVIDE(g_service_table_start = ABSOLUTE(.)); + KEEP(*(.g_service_table)) + PROVIDE(g_service_table_end = ABSOLUTE(.)); + + PROVIDE( _etext = ABSOLUTE(.) ); + } > sram + + . = ALIGN(8); + + .data : + { + PROVIDE( _sdata = ABSOLUTE(.) ); + + /* Writable data segment */ + *(.data .data.*) + + . = ALIGN(8); + PROVIDE( __global_pointer$ = ABSOLUTE(.) + 0x800 ); + + /* Writable small data segment (.sdata segment) */ + *(.sdata .sdata.*) + + PROVIDE( _edata = ABSOLUTE(.) ); + } > sram + + .bss : + { + __bss_start = ABSOLUTE(.); + + /* Writable uninitialized small data segment (.sbss segment)*/ + *(.sbss .sbss.*) + *(.scommon) + + /* Uninitialized writeable data section (.bss segment)*/ + *(.bss .bss.*) + *(COMMON) + + . = ALIGN(8); + __bss_end = ABSOLUTE(.); + } > sram + + .stack : + { + . = ALIGN(64); + PROVIDE(__stack_start__ = ABSOLUTE(.)); + + /* cpu0 stack top site */ + . = . + __STACKSIZE__; + __stack_tp0 = . ; + + /* cpu1 stack top site */ + . = . + __STACKSIZE__; + __stack_tp1 = . ; + + PROVIDE( __stack_end__ = ABSOLUTE(.) ); + } > sram + + _end = ABSOLUTE(.); +} diff --git a/Ubiquitous/XiZi/board/aiit-riscv64-board/link_userspace.lds b/Ubiquitous/XiZi/board/aiit-riscv64-board/link_userspace.lds new file mode 100644 index 0000000..ab24dd3 --- /dev/null +++ b/Ubiquitous/XiZi/board/aiit-riscv64-board/link_userspace.lds @@ -0,0 +1,71 @@ +/* +* Copyright (c) 2020 AIIT XUOS Lab +* XiUOS is licensed under Mulan PSL v2. +* You can use this software according to the terms and conditions of the Mulan PSL v2. +* You may obtain a copy of Mulan PSL v2 at: +* http://license.coscl.org.cn/MulanPSL2 +* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, +* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, +* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. +* See the Mulan PSL v2 for more details. +*/ + +OUTPUT_ARCH("riscv") + +MEMORY +{ + usram (rw) : ORIGIN = 0x80101000, LENGTH = ( 5 * 1024 * 1024 - 4 * 1024 ) /* 5M -4k usram */ +} + +SECTIONS +{ + .userspace : + { + . = ALIGN(8); + KEEP(*(.userspace)) + } > usram + + .text : + { + _ustext = ABSOLUTE(.); + *(.text .text.*) + *(.rodata .rodata*) + *(.glue_7) + *(.glue_7t) + PROVIDE(_uetext = ABSOLUTE(.)); + } > usram + + .init_section : { + _sinit = ABSOLUTE(.); + KEEP(*(.init_array .init_array.*)) + _einit = ABSOLUTE(.); + } > usram + + __uexidx_start = ABSOLUTE(.); + + .ARM.exidx : + { + PROVIDE(__uexidx_start = ABSOLUTE(.)); + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + PROVIDE(__uexidx_end = ABSOLUTE(.)); + } > usram + + _ueronly = ABSOLUTE(.); + + .data : AT(_ueronly) + { + _usdata = ABSOLUTE(.); + *(.data .data.*) + . = ALIGN(8); + _uedata = ABSOLUTE(.); + } > usram + + .bss : { + . = ALIGN(8); + _usbss = ABSOLUTE(.); + *(.bss .bss.*) + *(.sbss .sbss.*) + . = ALIGN(8); + _uebss = ABSOLUTE(.); + } > usram +} \ No newline at end of file diff --git a/Ubiquitous/XiZi/board/aiit-riscv64-board/third_party_driver/Kconfig b/Ubiquitous/XiZi/board/aiit-riscv64-board/third_party_driver/Kconfig new file mode 100755 index 0000000..0bfef5c --- /dev/null +++ b/Ubiquitous/XiZi/board/aiit-riscv64-board/third_party_driver/Kconfig @@ -0,0 +1,110 @@ +menuconfig BSP_USING_CH376 +bool "Using CH376 device" +default n +select FS_VFS +select FS_CH376 +if BSP_USING_CH376 +source "$BSP_DIR/third_party_driver/ch376/Kconfig" +endif + +menuconfig BSP_USING_CH438 +bool "Using CH438 device" +default y +if BSP_USING_CH438 +source "$BSP_DIR/third_party_driver/ch438/Kconfig" +endif + +menuconfig BSP_USING_DMA +bool "Using DMA device" +default y +if BSP_USING_DMA +source "$BSP_DIR/third_party_driver/dma/Kconfig" +endif + +menuconfig BSP_USING_GPIO +bool "Using GPIO device" +default y +select RESOURCES_PIN +if BSP_USING_GPIO +source "$BSP_DIR/third_party_driver/gpio/Kconfig" +endif + +menuconfig BSP_USING_I2C +bool "Using I2C device" +default n +select RESOURCES_I2C +if BSP_USING_I2C +source "$BSP_DIR/third_party_driver/i2c/Kconfig" +endif + +menuconfig BSP_USING_LCD +bool "Using LCD device" +default n +select RESOURCES_LCD +select BSP_USING_SPI1 +if BSP_USING_LCD +source "$BSP_DIR/third_party_driver/lcd/Kconfig" +endif + +menuconfig BSP_USING_PLIC +bool "Using PLIC device" +default y +if BSP_USING_PLIC +source "$BSP_DIR/third_party_driver/plic/Kconfig" +endif + +menuconfig BSP_USING_RTC +bool "Using RTC device" +default n +select RESOURCES_RTC +if BSP_USING_RTC +source "$BSP_DIR/third_party_driver/rtc/Kconfig" +endif + +menuconfig BSP_USING_SPI +bool "Using SPI device" +default n +select RESOURCES_SPI +select BSP_USING_DMA +if BSP_USING_SPI +source "$BSP_DIR/third_party_driver/spi/Kconfig" +endif + +menuconfig BSP_USING_SYSCLOCK +bool "Using SYSCLOCK device" +default y +if BSP_USING_SYSCLOCK +source "$BSP_DIR/third_party_driver/sys_clock/Kconfig" +endif + +menuconfig BSP_USING_HWTIMER +bool "Using HWTIMER device" +default n +select RESOURCES_HWTIMER +if BSP_USING_HWTIMER +source "$BSP_DIR/third_party_driver/timer/Kconfig" +endif + +menuconfig BSP_USING_TOUCH +bool "Using TOUCH device" +default n +select RESOURCES_TOUCH +if BSP_USING_TOUCH +source "$BSP_DIR/third_party_driver/touch/Kconfig" +endif + +menuconfig BSP_USING_UART +bool "Using UART device" +default y +select RESOURCES_SERIAL +if BSP_USING_UART +source "$BSP_DIR/third_party_driver/uart/Kconfig" +endif + +menuconfig BSP_USING_WDT +bool "Using WATCHDOG device" +default y +select RESOURCES_WDT +if BSP_USING_WDT +source "$BSP_DIR/third_party_driver/watchdog/Kconfig" +endif diff --git a/Ubiquitous/XiZi/board/aiit-riscv64-board/third_party_driver/Makefile b/Ubiquitous/XiZi/board/aiit-riscv64-board/third_party_driver/Makefile new file mode 100644 index 0000000..6f18733 --- /dev/null +++ b/Ubiquitous/XiZi/board/aiit-riscv64-board/third_party_driver/Makefile @@ -0,0 +1,91 @@ +SRC_FILES := sleep.c + +ifeq ($(CONFIG_BSP_USING_AUDIO),y) + SRC_DIR += audio +endif + +ifeq ($(CONFIG_BSP_USING_CAMERA),y) + SRC_DIR += camera +endif + +ifeq ($(CONFIG_BSP_USING_CH376),y) + SRC_DIR += ch376 +endif + +ifeq ($(CONFIG_BSP_USING_CH438),y) + SRC_DIR += ch438 +endif + +ifeq ($(CONFIG_BSP_USING_DMA),y) + SRC_DIR += dma +endif + +ifeq ($(CONFIG_ BSP_USING_FFT),y) + SRC_DIR += fft +endif + +ifeq ($(CONFIG_BSP_USING_GPIO),y) + SRC_DIR += gpio +endif + +ifeq ($(CONFIG_BSP_USING_I2C),y) + SRC_DIR += i2c +endif + +ifeq ($(CONFIG_BSP_USING_I2S),y) + SRC_DIR += i2s +endif + +ifeq ($(CONFIG_BSP_USING_KPU),y) + SRC_DIR += kpu +endif + +ifeq ($(CONFIG_BSP_USING_LCD),y) + SRC_DIR += lcd +endif + +ifeq ($(CONFIG_BSP_USING_PLIC),y) + SRC_DIR += plic +endif + +ifeq ($(CONFIG_BSP_USING_PWM),y) + SRC_DIR += pwm +endif + +ifeq ($(CONFIG_BSP_USING_RTC),y) + SRC_DIR += rtc +endif + +ifeq ($(CONFIG_BSP_USING_SECURITY),y) + SRC_DIR += security +endif + +ifeq ($(CONFIG_BSP_USING_SPI),y) + SRC_DIR += spi +endif + +ifeq ($(CONFIG_BSP_USING_SYSCLOCK),y) + SRC_DIR += sys_clock +endif + +ifeq ($(CONFIG_BSP_USING_HWTIMER),y) + SRC_DIR += timer +endif + +ifeq ($(CONFIG_BSP_USING_TOUCH),y) + SRC_DIR += touch +endif + +ifeq ($(CONFIG_BSP_USING_UART),y) + SRC_DIR += uart +endif + +ifeq ($(CONFIG_BSP_USING_VIDEO),y) + SRC_DIR += video +endif + +ifeq ($(CONFIG_BSP_USING_WDT),y) + SRC_DIR += watchdog +endif + +include $(KERNEL_ROOT)/compiler.mk diff --git a/Ubiquitous/XiZi/board/aiit-riscv64-board/third_party_driver/ch376/Kconfig b/Ubiquitous/XiZi/board/aiit-riscv64-board/third_party_driver/ch376/Kconfig new file mode 100644 index 0000000..8bc0829 --- /dev/null +++ b/Ubiquitous/XiZi/board/aiit-riscv64-board/third_party_driver/ch376/Kconfig @@ -0,0 +1,35 @@ +menuconfig BSP_USING_SDIO +bool "Using CH376 SD card" +default n +select RESOURCES_SDIO +if BSP_USING_SDIO +config SDIO_BUS_NAME + string "sdio bus name" + default "sdio" + +config SDIO_DRIVER_NAME + string "sdio driver name" + default "sdio_drv" + +config SDIO_DEVICE_NAME + string "sdio device name" + default "sdio_dev" +endif + +menuconfig BSP_USING_USB +bool "Using CH376 USB" +default n +select RESOURCES_USB +if BSP_USING_USB +config USB_BUS_NAME + string "USB bus name" + default "usb" + +config USB_DRIVER_NAME + string "USB driver name" + default "usb_drv" + +config USB_DEVICE_NAME + string "USB device name" + default "usb_dev" +endif diff --git a/Ubiquitous/XiZi/board/aiit-riscv64-board/third_party_driver/ch376/Makefile b/Ubiquitous/XiZi/board/aiit-riscv64-board/third_party_driver/ch376/Makefile new file mode 100644 index 0000000..d5393d3 --- /dev/null +++ b/Ubiquitous/XiZi/board/aiit-riscv64-board/third_party_driver/ch376/Makefile @@ -0,0 +1,4 @@ +SRC_FILES := connect_ch376.c + + +include $(KERNEL_ROOT)/compiler.mk diff --git a/Ubiquitous/XiZi/board/aiit-riscv64-board/third_party_driver/ch376/connect_ch376.c b/Ubiquitous/XiZi/board/aiit-riscv64-board/third_party_driver/ch376/connect_ch376.c new file mode 100644 index 0000000..7957083 --- /dev/null +++ b/Ubiquitous/XiZi/board/aiit-riscv64-board/third_party_driver/ch376/connect_ch376.c @@ -0,0 +1,224 @@ +/* +* Copyright (c) 2020 AIIT XUOS Lab +* XiUOS is licensed under Mulan PSL v2. +* You can use this software according to the terms and conditions of the Mulan PSL v2. +* You may obtain a copy of Mulan PSL v2 at: +* http://license.coscl.org.cn/MulanPSL2 +* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, +* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, +* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. +* See the Mulan PSL v2 for more details. +*/ + +/** +* @file connect_ch436.c +* @brief support to register ch436 pointer and function +* @version 1.0 +* @author AIIT XUOS Lab +* @date 2021-04-24 +*/ + +#include +#include + +static struct HwCh376 sdio; + +static uint32 Ch376Configure(void *drv, struct BusConfigureInfo *configure_info) +{ + NULL_PARAM_CHECK(drv); + NULL_PARAM_CHECK(configure_info); + + uint8 temp[2]; + temp[0] = 0x57; + temp[1] = 0xab; + MdelayKTask(100); + + struct BusBlockWriteParam write_param; + write_param.pos = 0; + write_param.buffer = (void *)temp; + write_param.size = 2; + BusDevWriteData(sdio.dev, &write_param); + + write_param.pos = 0; + write_param.buffer = &configure_info->configure_cmd; + write_param.size = 1; + BusDevWriteData(sdio.dev, &write_param); + + return EOK; +} + +static int HwCh376RxInd(void *dev, x_size_t length) +{ + sdio.msg_len += length; + KSemaphoreAbandon(sdio.sem); + + return EOK; +} + +static uint32 Ch376Open(void *dev) +{ + NULL_PARAM_CHECK(dev); + + sdio.sem = KSemaphoreCreate(0); + if (sdio.sem < 0) { + KPrintf("CH376 open fail\n"); + return -ERROR; + } + + struct Bus *bus = BusFind(SERIAL_BUS_NAME_2); + struct Driver *bus_driver = BusFindDriver(bus, SERIAL_DRV_NAME_2); + sdio.dev = BusFindDevice(bus, SERIAL_2_DEVICE_NAME_0); + if (!sdio.dev) { + KPrintf("CH376 open fail\n"); + return -ERROR; + } + + struct SerialCfgParam serial_cfg; + memset(&serial_cfg, 0, sizeof(struct SerialCfgParam)); + serial_cfg.data_cfg.serial_buffer_size = 512; + struct BusConfigureInfo cfg; + cfg.configure_cmd = OPE_INT; + cfg.private_data = &serial_cfg; + + BusDrvConfigure(bus_driver, &cfg); + + bus->match(bus_driver, sdio.dev); + + struct SerialDevParam *serial_dev_param = (struct SerialDevParam *)sdio.dev->private_data; + serial_dev_param->serial_set_mode = SIGN_OPER_INT_RX; + BusDevOpen(sdio.dev); + + BusDevRecvCallback(sdio.dev, HwCh376RxInd); + + KPrintf("CH376 open done\n"); + + return EOK; +} + +static uint32 Ch376Close(void *dev) +{ + BusDevClose(sdio.dev); + KSemaphoreDelete(sdio.sem); + + return EOK; +} + +static uint32 Ch376Write(void *dev, struct BusBlockWriteParam *write_param) +{ + if (EOK == BusDevWriteData(sdio.dev, write_param)) + return EOK; + + return -ERROR; +} + +static uint32 Ch376Read(void *dev, struct BusBlockReadParam *read_param) +{ + if (KSemaphoreObtain(sdio.sem, WAITING_FOREVER) == EOK) { + while(KSemaphoreObtain(sdio.sem, TICK_PER_SECOND) != -ETIMEOUT); + read_param->size = sdio.msg_len; + BusDevReadData(sdio.dev, read_param); + sdio.msg_len = 0; + } + + return read_param->read_length; +} + +#ifdef BSP_USING_SDIO +static struct SdioDevDone sdio_done = +{ + Ch376Open, + Ch376Close, + Ch376Write, + Ch376Read, +}; +#endif + +#ifdef BSP_USING_USB +static struct UsbDevDone usb_done = +{ + Ch376Open, + Ch376Close, + Ch376Write, + Ch376Read, +}; +#endif + +int HwCh376Init(void) +{ + x_err_t ret = EOK; + +#ifdef BSP_USING_SDIO + static struct SdioBus sdio_bus; + static struct SdioDriver sdio_drv; + static struct SdioHardwareDevice sdio_dev; + + ret = SdioBusInit(&sdio_bus, SDIO_BUS_NAME); + if (ret != EOK) { + KPrintf("Sdio bus init error %d\n", ret); + return -ERROR; + } + + sdio_drv.configure = &Ch376Configure; + ret = SdioDriverInit(&sdio_drv, SDIO_DRIVER_NAME); + if (ret != EOK) { + KPrintf("Sdio driver init error %d\n", ret); + return -ERROR; + } + + ret = SdioDriverAttachToBus(SDIO_DRIVER_NAME, SDIO_BUS_NAME); + if (ret != EOK) { + KPrintf("Sdio driver attach error %d\n", ret); + return -ERROR; + } + + sdio_dev.dev_done = &sdio_done; + ret = SdioDeviceRegister(&sdio_dev, SDIO_DEVICE_NAME); + if (ret != EOK) { + KPrintf("Sdio device register error %d\n", ret); + return -ERROR; + } + + ret = SdioDeviceAttachToBus(SDIO_DEVICE_NAME, SDIO_BUS_NAME); + if (ret != EOK) { + KPrintf("Sdio device register error %d\n", ret); + return -ERROR; + } +#endif + +#ifdef BSP_USING_USB + static struct UsbBus usb_bus; + static struct UsbDriver usb_drv; + static struct UsbHardwareDevice usb_dev; + + ret = UsbBusInit(&usb_bus, USB_BUS_NAME); + if (ret != EOK) { + KPrintf("USB bus init error %d\n", ret); + return -ERROR; + } + + usb_drv.configure = &Ch376Configure; + ret = UsbDriverInit(&usb_drv, USB_DRIVER_NAME); + if (ret != EOK) { + KPrintf("USB driver init error %d\n", ret); + return -ERROR; + } + ret = UsbDriverAttachToBus(USB_DRIVER_NAME, USB_BUS_NAME); + if (ret != EOK) { + KPrintf("USB driver attach error %d\n", ret); + return -ERROR; + } + + usb_dev.dev_done = &usb_done; + ret = USBDeviceRegister(&usb_dev, NONE, USB_DEVICE_NAME); + if (ret != EOK) { + KPrintf("USB device register error %d\n", ret); + return -ERROR; + } + ret = USBDeviceAttachToBus(USB_DEVICE_NAME, USB_BUS_NAME); + if (ret != EOK) { + KPrintf("USB device register error %d\n", ret); + return -ERROR; + } +#endif + return ret; +} \ No newline at end of file diff --git a/Ubiquitous/XiZi/board/aiit-riscv64-board/third_party_driver/ch438/Kconfig b/Ubiquitous/XiZi/board/aiit-riscv64-board/third_party_driver/ch438/Kconfig new file mode 100644 index 0000000..2e3d5fa --- /dev/null +++ b/Ubiquitous/XiZi/board/aiit-riscv64-board/third_party_driver/ch438/Kconfig @@ -0,0 +1,136 @@ + +if BSP_USING_CH438 + config CH438_BUS_NAME + string + default "extuart" + + config CH438_DRIVER_NAME + string + default "extuart_drv" + + config CH438_DEVICE_NAME_0 + string + default "extuart_dev0" + + config CH438_DEVICE_NAME_1 + string + default "extuart_dev1" + + config CH438_DEVICE_NAME_2 + string + default "extuart_dev2" + + config CH438_DEVICE_NAME_3 + string + default "extuart_dev3" + + config CH438_DEVICE_NAME_4 + string + default "extuart_dev4" + + config CH438_DEVICE_NAME_5 + string + default "extuart_dev5" + + config CH438_DEVICE_NAME_6 + string + default "extuart_dev6" + + config CH438_DEVICE_NAME_7 + string + default "extuart_dev7" + + config BSP_CH438_ALE_PIN + int "ALE pin number for ch438" + default 23 + + config BSP_CH438_NWR_PIN + int "NWR pin number for ch438" + default 24 + + config BSP_CH438_NRD_PIN + int "NRD pin number for ch438" + default 25 + + config BSP_CH438_D0_PIN + int "D0 pin number for ch438" + default 27 + + config BSP_CH438_D1_PIN + int "D1 pin number for ch438" + default 28 + + config BSP_CH438_D2_PIN + int "D2 pin number for ch438" + default 29 + + config BSP_CH438_D3_PIN + int "D3 pin number for ch438" + default 30 + + config BSP_CH438_D4_PIN + int "D4 pin number for ch438" + default 31 + + config BSP_CH438_D5_PIN + int "D5 pin number for ch438" + default 32 + + config BSP_CH438_D6_PIN + int "D6 pin number for ch438" + default 33 + + config BSP_CH438_D7_PIN + int "D7 pin number for ch438" + default 34 + + config BSP_CH438_INT_PIN + int "INT pin number for ch438" + default 35 + + config BSP_485_dir + int "485 direction pin number for ch438" + default 18 + + + menuconfig BSP_USING_4G_OR_NB + bool "Select using the ec200t(4G) or bc28(NB-IOT)" + default y + if BSP_USING_4G_OR_NB + choice + prompt "Select using the ec200t(4G) or bc28(NB-IOT)" + default BSP_USING_4G + config BSP_USING_4G + bool "Using ec200t(4G)" + config BSP_USING_NBIOT + bool "Using bc26(NB-IOT)" + endchoice + + + if BSP_USING_4G + config BSP_4G_STATUS + int "STATUS pin number for ec200t" + default 21 + config BSP_4G_POWERKEY + int "POWERKEY pin number for ec200t" + default 37 + endif + + if BSP_USING_NBIOT + config BSP_NB_RESET + int "RESET pin number for bc28" + default 21 + endif + endif + + menuconfig BSP_USING_WIFI_HFA21 + bool "Using the hfa21(WIFI)" + default y + if BSP_USING_WIFI_HFA21 + config BSP_WIFI_RST + int "RESET pin number for hfa21" + default 22 + endif + +endif + diff --git a/Ubiquitous/XiZi/board/aiit-riscv64-board/third_party_driver/ch438/Makefile b/Ubiquitous/XiZi/board/aiit-riscv64-board/third_party_driver/ch438/Makefile new file mode 100644 index 0000000..4796857 --- /dev/null +++ b/Ubiquitous/XiZi/board/aiit-riscv64-board/third_party_driver/ch438/Makefile @@ -0,0 +1,4 @@ +SRC_FILES := connect_ch438.c + + +include $(KERNEL_ROOT)/compiler.mk diff --git a/Ubiquitous/XiZi/board/aiit-riscv64-board/third_party_driver/ch438/connect_ch438.c b/Ubiquitous/XiZi/board/aiit-riscv64-board/third_party_driver/ch438/connect_ch438.c new file mode 100755 index 0000000..81d2d15 --- /dev/null +++ b/Ubiquitous/XiZi/board/aiit-riscv64-board/third_party_driver/ch438/connect_ch438.c @@ -0,0 +1,1306 @@ +/* +* Copyright (c) 2020 AIIT XUOS Lab +* XiUOS is licensed under Mulan PSL v2. +* You can use this software according to the terms and conditions of the Mulan PSL v2. +* You may obtain a copy of Mulan PSL v2 at: +* http://license.coscl.org.cn/MulanPSL2 +* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, +* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, +* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. +* See the Mulan PSL v2 for more details. +*/ + +/** +* @file connect_ch438.c +* @brief support to register ch438 pointer and function +* @version 1.0 +* @author AIIT XUOS Lab +* @date 2021-04-24 +*/ + +#include +#include +#include +#include + +static uint8 offset_addr[] = {0x00,0x10,0x20,0x30,0x08,0x18,0x28,0x38,}; /* Offset address of serial port number */ +static uint8 interrupt_num[8] = {0x01,0x02,0x04,0x08,0x10,0x20,0x40,0x80,}; + +static BusType ch438_pin; +static int ch438_sem = NONE; + +static plic_irq_callback_t Ch438Irq(void *parameter) +{ + KSemaphoreAbandon(ch438_sem); +} + +static void CH438SetOutput(void) +{ + struct PinParam pin_cfg; + int ret = 0; + + struct BusConfigureInfo configure_info; + configure_info.configure_cmd = OPE_CFG; + configure_info.private_data = (void *)&pin_cfg; + + pin_cfg.cmd = GPIO_CONFIG_MODE; + pin_cfg.pin = BSP_CH438_D0_PIN; + pin_cfg.mode = GPIO_CFG_OUTPUT; + + ret = BusDrvConfigure(ch438_pin->owner_driver, &configure_info); + if (ret != EOK) { + KPrintf("config CH438_D0_PIN pin %d failed!\n", BSP_CH438_D0_PIN); + return ; + } + + pin_cfg.pin = BSP_CH438_D1_PIN; + ret = BusDrvConfigure(ch438_pin->owner_driver, &configure_info); + if (ret != EOK) { + KPrintf("config CH438_D1_PIN pin %d failed!\n", BSP_CH438_D1_PIN); + return ; + } + + pin_cfg.pin = BSP_CH438_D2_PIN; + ret = BusDrvConfigure(ch438_pin->owner_driver, &configure_info); + if (ret != EOK) { + KPrintf("config CH438_D2_PIN pin %d failed!\n", BSP_CH438_D2_PIN); + return ; + } + + pin_cfg.pin = BSP_CH438_D3_PIN; + ret = BusDrvConfigure(ch438_pin->owner_driver, &configure_info); + if (ret != EOK) { + KPrintf("config CH438_D3_PIN pin %d failed!\n", BSP_CH438_D3_PIN); + return ; + } + + pin_cfg.pin = BSP_CH438_D4_PIN; + ret = BusDrvConfigure(ch438_pin->owner_driver, &configure_info); + if (ret != EOK) { + KPrintf("config CH438_D4_PIN pin %d failed!\n", BSP_CH438_D4_PIN); + return ; + } + + pin_cfg.pin = BSP_CH438_D5_PIN; + ret = BusDrvConfigure(ch438_pin->owner_driver, &configure_info); + if (ret != EOK) { + KPrintf("config CH438_D5_PIN pin %d failed!\n", BSP_CH438_D5_PIN); + return ; + } + + pin_cfg.pin = BSP_CH438_D6_PIN; + ret = BusDrvConfigure(ch438_pin->owner_driver, &configure_info); + if (ret != EOK) { + KPrintf("config CH438_D6_PIN pin %d failed!\n", BSP_CH438_D6_PIN); + return ; + } + + pin_cfg.pin = BSP_CH438_D7_PIN; + ret = BusDrvConfigure(ch438_pin->owner_driver, &configure_info); + if (ret != EOK) { + KPrintf("config CH438_D7_PIN pin %d failed!\n", BSP_CH438_D7_PIN); + return ; + } +} + +static void CH438SetInput(void) +{ + struct PinParam pin_cfg; + int ret = 0; + + struct BusConfigureInfo configure_info; + configure_info.configure_cmd = OPE_CFG; + configure_info.private_data = (void *)&pin_cfg; + + pin_cfg.cmd = GPIO_CONFIG_MODE; + pin_cfg.pin = BSP_CH438_D0_PIN; + pin_cfg.mode = GPIO_CFG_INPUT_PULLUP; + ret = BusDrvConfigure(ch438_pin->owner_driver, &configure_info); + if (ret != EOK) { + KPrintf("config CH438_D0_PIN pin %d INPUT_PULLUP failed!\n", BSP_CH438_D0_PIN); + return ; + } + + pin_cfg.pin = BSP_CH438_D1_PIN; + ret = BusDrvConfigure(ch438_pin->owner_driver, &configure_info); + if (ret != EOK) { + KPrintf("config CH438_D1_PIN pin %d INPUT_PULLUP failed!\n", BSP_CH438_D1_PIN); + return ; + } + + pin_cfg.pin = BSP_CH438_D2_PIN; + ret = BusDrvConfigure(ch438_pin->owner_driver, &configure_info); + if (ret != EOK) { + KPrintf("config CH438_D2_PIN pin %d INPUT_PULLUP failed!\n", BSP_CH438_D2_PIN); + return ; + } + + pin_cfg.pin = BSP_CH438_D3_PIN; + ret = BusDrvConfigure(ch438_pin->owner_driver, &configure_info); + if (ret != EOK) { + KPrintf("config CH438_D3_PIN pin %d INPUT_PULLUP failed!\n", BSP_CH438_D3_PIN); + return ; + } + + pin_cfg.pin = BSP_CH438_D4_PIN; + ret = BusDrvConfigure(ch438_pin->owner_driver, &configure_info); + if (ret != EOK) { + KPrintf("config CH438_D4_PIN pin %d INPUT_PULLUP failed!\n", BSP_CH438_D4_PIN); + return ; + } + + pin_cfg.pin = BSP_CH438_D5_PIN; + ret = BusDrvConfigure(ch438_pin->owner_driver, &configure_info); + if (ret != EOK) { + KPrintf("config CH438_D5_PIN pin %d INPUT_PULLUP failed!\n", BSP_CH438_D5_PIN); + return ; + } + + pin_cfg.pin = BSP_CH438_D6_PIN; + ret = BusDrvConfigure(ch438_pin->owner_driver, &configure_info); + if (ret != EOK) { + KPrintf("config CH438_D6_PIN pin %d INPUT_PULLUP failed!\n", BSP_CH438_D6_PIN); + return ; + } + + pin_cfg.pin = BSP_CH438_D7_PIN; + ret = BusDrvConfigure(ch438_pin->owner_driver, &configure_info); + if (ret != EOK) { + KPrintf("config CH438_D7_PIN pin %d INPUT_PULLUP failed!\n", BSP_CH438_D7_PIN); + return ; + } +} + +void Set485Input(uint8 ch_no) +{ + struct PinStat pin_stat; + struct BusBlockWriteParam write_param; + write_param.buffer = (void *)&pin_stat; + + if (ch_no == 1) { + pin_stat.val = GPIO_LOW; + pin_stat.pin = BSP_485_dir; + BusDevWriteData(ch438_pin->owner_haldev, &write_param); + } +} + +void Set485Output(uint8 ch_no) +{ + struct PinStat pin_stat; + struct BusBlockWriteParam write_param; + write_param.buffer = (void *)&pin_stat; + if (ch_no == 1) { + pin_stat.val = GPIO_HIGH; + pin_stat.pin = BSP_485_dir; + BusDevWriteData(ch438_pin->owner_haldev, &write_param); + } +} + +uint8 ReadCH438Data(uint8 addr ) +{ + uint8 dat; + struct PinStat pin_stat; + struct BusBlockWriteParam write_param; + struct BusBlockReadParam read_param; + write_param.buffer = (void *)&pin_stat; + read_param.buffer = (void *)&pin_stat; + + pin_stat.val = GPIO_HIGH; + + pin_stat.pin = BSP_CH438_NWR_PIN; + BusDevWriteData(ch438_pin->owner_haldev, &write_param); + + pin_stat.pin = BSP_CH438_NRD_PIN; + BusDevWriteData(ch438_pin->owner_haldev, &write_param); + + pin_stat.pin = BSP_CH438_ALE_PIN; + BusDevWriteData(ch438_pin->owner_haldev, &write_param); + + CH438SetOutput(); + usleep(1); + + if (addr &0x80) { + pin_stat.val = GPIO_HIGH; + pin_stat.pin = BSP_CH438_D7_PIN; + BusDevWriteData(ch438_pin->owner_haldev, &write_param); + } else { + pin_stat.val = GPIO_LOW; + pin_stat.pin = BSP_CH438_D7_PIN; + BusDevWriteData(ch438_pin->owner_haldev, &write_param); + } + + if (addr &0x40) { + pin_stat.val = GPIO_HIGH; + pin_stat.pin = BSP_CH438_D6_PIN; + BusDevWriteData(ch438_pin->owner_haldev, &write_param); + } else { + pin_stat.val = GPIO_LOW; + pin_stat.pin = BSP_CH438_D6_PIN; + BusDevWriteData(ch438_pin->owner_haldev, &write_param); + } + + if (addr &0x20) { + pin_stat.val = GPIO_HIGH; + pin_stat.pin = BSP_CH438_D5_PIN; + BusDevWriteData(ch438_pin->owner_haldev, &write_param); + } else { + pin_stat.val = GPIO_LOW; + pin_stat.pin = BSP_CH438_D5_PIN; + BusDevWriteData(ch438_pin->owner_haldev, &write_param); + } + + if (addr &0x10) { + pin_stat.val = GPIO_HIGH; + pin_stat.pin = BSP_CH438_D4_PIN; + BusDevWriteData(ch438_pin->owner_haldev, &write_param); + } else { + pin_stat.val = GPIO_LOW; + pin_stat.pin = BSP_CH438_D4_PIN; + BusDevWriteData(ch438_pin->owner_haldev, &write_param); + } + + if (addr &0x08) { + pin_stat.val = GPIO_HIGH; + pin_stat.pin = BSP_CH438_D3_PIN; + BusDevWriteData(ch438_pin->owner_haldev, &write_param); + } else { + pin_stat.val = GPIO_LOW; + pin_stat.pin = BSP_CH438_D3_PIN; + BusDevWriteData(ch438_pin->owner_haldev, &write_param); + } + + if (addr &0x04) { + pin_stat.val = GPIO_HIGH; + pin_stat.pin = BSP_CH438_D2_PIN; + BusDevWriteData(ch438_pin->owner_haldev, &write_param); + } else { + pin_stat.val = GPIO_LOW; + pin_stat.pin = BSP_CH438_D2_PIN; + BusDevWriteData(ch438_pin->owner_haldev, &write_param); + } + + if (addr &0x02) { + pin_stat.val = GPIO_HIGH; + pin_stat.pin = BSP_CH438_D1_PIN; + BusDevWriteData(ch438_pin->owner_haldev, &write_param); + } else { + pin_stat.val = GPIO_LOW; + pin_stat.pin = BSP_CH438_D1_PIN; + BusDevWriteData(ch438_pin->owner_haldev, &write_param); + } + + if (addr &0x01) { + pin_stat.val = GPIO_HIGH; + pin_stat.pin = BSP_CH438_D0_PIN; + BusDevWriteData(ch438_pin->owner_haldev, &write_param); + } else { + pin_stat.val = GPIO_LOW; + pin_stat.pin = BSP_CH438_D0_PIN; + BusDevWriteData(ch438_pin->owner_haldev, &write_param); + } + + usleep(1); + + pin_stat.val = GPIO_LOW; + pin_stat.pin = BSP_CH438_ALE_PIN; + BusDevWriteData(ch438_pin->owner_haldev, &write_param); + + usleep(1); + + CH438SetInput(); + usleep(1); + + pin_stat.val = GPIO_LOW; + pin_stat.pin = BSP_CH438_NRD_PIN; + BusDevWriteData(ch438_pin->owner_haldev, &write_param); + + usleep(1); + + dat = 0; + pin_stat.pin = BSP_CH438_D7_PIN; + if (BusDevReadData(ch438_pin->owner_haldev, &read_param)) + dat |= 0x80; + + pin_stat.pin = BSP_CH438_D6_PIN; + if (BusDevReadData(ch438_pin->owner_haldev, &read_param)) + dat |= 0x40; + + pin_stat.pin = BSP_CH438_D5_PIN; + if (BusDevReadData(ch438_pin->owner_haldev, &read_param)) + dat |= 0x20; + + pin_stat.pin = BSP_CH438_D4_PIN; + if (BusDevReadData(ch438_pin->owner_haldev, &read_param)) + dat |= 0x10; + + pin_stat.pin = BSP_CH438_D3_PIN; + if (BusDevReadData(ch438_pin->owner_haldev, &read_param)) + dat |= 0x08; + + pin_stat.pin = BSP_CH438_D2_PIN; + if (BusDevReadData(ch438_pin->owner_haldev, &read_param)) + dat |= 0x04; + + pin_stat.pin = BSP_CH438_D1_PIN; + if (BusDevReadData(ch438_pin->owner_haldev, &read_param)) + dat |= 0x02; + + pin_stat.pin = BSP_CH438_D0_PIN; + if (BusDevReadData(ch438_pin->owner_haldev, &read_param)) + dat |= 0x01; + + pin_stat.val = GPIO_HIGH; + pin_stat.pin = BSP_CH438_NRD_PIN; + BusDevWriteData(ch438_pin->owner_haldev, &write_param); + + pin_stat.val = GPIO_HIGH; + pin_stat.pin = BSP_CH438_ALE_PIN; + BusDevWriteData(ch438_pin->owner_haldev, &write_param); + + usleep(1); + + return dat; +} + +static void WriteCH438Data(uint8 addr, uint8 dat) +{ + struct PinStat pin_stat; + struct BusBlockWriteParam write_param; + write_param.buffer = (void *)&pin_stat; + + pin_stat.val = GPIO_HIGH; + pin_stat.pin = BSP_CH438_ALE_PIN; + BusDevWriteData(ch438_pin->owner_haldev, &write_param); + + pin_stat.val = GPIO_HIGH; + pin_stat.pin = BSP_CH438_NRD_PIN; + BusDevWriteData(ch438_pin->owner_haldev, &write_param); + + pin_stat.val = GPIO_HIGH; + pin_stat.pin = BSP_CH438_NWR_PIN; + BusDevWriteData(ch438_pin->owner_haldev, &write_param); + + CH438SetOutput(); + usleep(1); + + if (addr &0x80) { + pin_stat.val = GPIO_HIGH; + pin_stat.pin = BSP_CH438_D7_PIN; + BusDevWriteData(ch438_pin->owner_haldev, &write_param); + } else { + pin_stat.val = GPIO_LOW; + pin_stat.pin = BSP_CH438_D7_PIN; + BusDevWriteData(ch438_pin->owner_haldev, &write_param); + } + + if (addr &0x40) { + pin_stat.val = GPIO_HIGH; + pin_stat.pin = BSP_CH438_D6_PIN; + BusDevWriteData(ch438_pin->owner_haldev, &write_param); + } else { + pin_stat.val = GPIO_LOW; + pin_stat.pin = BSP_CH438_D6_PIN; + BusDevWriteData(ch438_pin->owner_haldev, &write_param); + } + + if (addr &0x20) { + pin_stat.val = GPIO_HIGH; + pin_stat.pin = BSP_CH438_D5_PIN; + BusDevWriteData(ch438_pin->owner_haldev, &write_param); + } else { + pin_stat.val = GPIO_LOW; + pin_stat.pin = BSP_CH438_D5_PIN; + BusDevWriteData(ch438_pin->owner_haldev, &write_param); + } + + if (addr &0x10) { + pin_stat.val = GPIO_HIGH; + pin_stat.pin = BSP_CH438_D4_PIN; + BusDevWriteData(ch438_pin->owner_haldev, &write_param); + } else { + pin_stat.val = GPIO_LOW; + pin_stat.pin = BSP_CH438_D4_PIN; + BusDevWriteData(ch438_pin->owner_haldev, &write_param); + } + + if (addr &0x08) { + pin_stat.val = GPIO_HIGH; + pin_stat.pin = BSP_CH438_D3_PIN; + BusDevWriteData(ch438_pin->owner_haldev, &write_param); + } else { + pin_stat.val = GPIO_LOW; + pin_stat.pin = BSP_CH438_D3_PIN; + BusDevWriteData(ch438_pin->owner_haldev, &write_param); + } + + if (addr &0x04) { + pin_stat.val = GPIO_HIGH; + pin_stat.pin = BSP_CH438_D2_PIN; + BusDevWriteData(ch438_pin->owner_haldev, &write_param); + } else { + pin_stat.val = GPIO_LOW; + pin_stat.pin = BSP_CH438_D2_PIN; + BusDevWriteData(ch438_pin->owner_haldev, &write_param); + } + + if (addr &0x02) { + pin_stat.val = GPIO_HIGH; + pin_stat.pin = BSP_CH438_D1_PIN; + BusDevWriteData(ch438_pin->owner_haldev, &write_param); + } else { + pin_stat.val = GPIO_LOW; + pin_stat.pin = BSP_CH438_D1_PIN; + BusDevWriteData(ch438_pin->owner_haldev, &write_param); + } + + if (addr &0x01) { + pin_stat.val = GPIO_HIGH; + pin_stat.pin = BSP_CH438_D0_PIN; + BusDevWriteData(ch438_pin->owner_haldev, &write_param); + } else { + pin_stat.val = GPIO_LOW; + pin_stat.pin = BSP_CH438_D0_PIN; + BusDevWriteData(ch438_pin->owner_haldev, &write_param); + } + + usleep(1); + + pin_stat.val = GPIO_LOW; + pin_stat.pin = BSP_CH438_ALE_PIN; + BusDevWriteData(ch438_pin->owner_haldev, &write_param); + + usleep(1); + + if (dat &0x80) { + pin_stat.val = GPIO_HIGH; + pin_stat.pin = BSP_CH438_D7_PIN; + BusDevWriteData(ch438_pin->owner_haldev, &write_param); + } else { + pin_stat.val = GPIO_LOW; + pin_stat.pin = BSP_CH438_D7_PIN; + BusDevWriteData(ch438_pin->owner_haldev, &write_param); + } + + if (dat &0x40) { + pin_stat.val = GPIO_HIGH; + pin_stat.pin = BSP_CH438_D6_PIN; + BusDevWriteData(ch438_pin->owner_haldev, &write_param); + } else { + pin_stat.val = GPIO_LOW; + pin_stat.pin = BSP_CH438_D6_PIN; + BusDevWriteData(ch438_pin->owner_haldev, &write_param); + } + + if (dat &0x20) { + pin_stat.val = GPIO_HIGH; + pin_stat.pin = BSP_CH438_D5_PIN; + BusDevWriteData(ch438_pin->owner_haldev, &write_param); + } else { + pin_stat.val = GPIO_LOW; + pin_stat.pin = BSP_CH438_D5_PIN; + BusDevWriteData(ch438_pin->owner_haldev, &write_param); + } + + if (dat &0x10) { + pin_stat.val = GPIO_HIGH; + pin_stat.pin = BSP_CH438_D4_PIN; + BusDevWriteData(ch438_pin->owner_haldev, &write_param); + } else { + pin_stat.val = GPIO_LOW; + pin_stat.pin = BSP_CH438_D4_PIN; + BusDevWriteData(ch438_pin->owner_haldev, &write_param); + } + + if (dat &0x08) { + pin_stat.val = GPIO_HIGH; + pin_stat.pin = BSP_CH438_D3_PIN; + BusDevWriteData(ch438_pin->owner_haldev, &write_param); + } else { + pin_stat.val = GPIO_LOW; + pin_stat.pin = BSP_CH438_D3_PIN; + BusDevWriteData(ch438_pin->owner_haldev, &write_param); + } + + if (dat &0x04) { + pin_stat.val = GPIO_HIGH; + pin_stat.pin = BSP_CH438_D2_PIN; + BusDevWriteData(ch438_pin->owner_haldev, &write_param); + } else { + pin_stat.val = GPIO_LOW; + pin_stat.pin = BSP_CH438_D2_PIN; + BusDevWriteData(ch438_pin->owner_haldev, &write_param); + } + + if (dat &0x02) { + pin_stat.val = GPIO_HIGH; + pin_stat.pin = BSP_CH438_D1_PIN; + BusDevWriteData(ch438_pin->owner_haldev, &write_param); + } else { + pin_stat.val = GPIO_LOW; + pin_stat.pin = BSP_CH438_D1_PIN; + BusDevWriteData(ch438_pin->owner_haldev, &write_param); + } + + if (dat &0x01) { + pin_stat.val = GPIO_HIGH; + pin_stat.pin = BSP_CH438_D0_PIN; + BusDevWriteData(ch438_pin->owner_haldev, &write_param); + } else { + pin_stat.val = GPIO_LOW; + pin_stat.pin = BSP_CH438_D0_PIN; + BusDevWriteData(ch438_pin->owner_haldev, &write_param); + } + + usleep(1); + + pin_stat.val = GPIO_LOW; + pin_stat.pin = BSP_CH438_NWR_PIN; + BusDevWriteData(ch438_pin->owner_haldev, &write_param); + + usleep(1); + + pin_stat.val = GPIO_HIGH; + pin_stat.pin = BSP_CH438_NWR_PIN; + BusDevWriteData(ch438_pin->owner_haldev, &write_param); + + pin_stat.val = GPIO_HIGH; + pin_stat.pin = BSP_CH438_ALE_PIN; + BusDevWriteData(ch438_pin->owner_haldev, &write_param); + + usleep(1); + + CH438SetInput(); + + return; +} + +static void WriteCH438Block( uint8 mAddr, uint8 mLen, uint8 *mBuf ) +{ + while (mLen--) + { + WriteCH438Data(mAddr, *mBuf++); + } +} + +void CH438UartSend( uint8 ext_uart_no,uint8 *Data, uint8 Num ) +{ + uint8 REG_LSR_ADDR,REG_THR_ADDR; + + REG_LSR_ADDR = offset_addr[ext_uart_no] | REG_LSR0_ADDR; + REG_THR_ADDR = offset_addr[ext_uart_no] | REG_THR0_ADDR; + + while (1) + { + while((ReadCH438Data(REG_LSR_ADDR) & BIT_LSR_TEMT) == 0); + + if (Num <= 128) { + WriteCH438Block(REG_THR_ADDR, Num, Data); + break; + } else { + WriteCH438Block(REG_THR_ADDR, 128, Data); + Num -= 128; + Data += 128; + } + } +} + +uint8 CH438UARTRcv(uint8 ext_uart_no, uint8 *buf, x_size_t size ) +{ + x_size_t rcv_num = 0; + uint8 dat = 0; + uint8 REG_LSR_ADDR, REG_RBR_ADDR; + uint8 *read_buffer; + x_size_t buffer_index = 0; + + REG_LSR_ADDR = offset_addr[ext_uart_no] | REG_LSR0_ADDR; + REG_RBR_ADDR = offset_addr[ext_uart_no] | REG_RBR0_ADDR; + + read_buffer = buf; + + while ((ReadCH438Data(REG_LSR_ADDR) & BIT_LSR_DATARDY) == 0); + + while (((ReadCH438Data(REG_LSR_ADDR) & BIT_LSR_DATARDY) == 0x01) && (size != 0)) + { + dat = ReadCH438Data(REG_RBR_ADDR); + + *read_buffer = dat; + read_buffer++; + buffer_index++; + + if (BUFFSIZE == buffer_index) { + buffer_index = 0; + read_buffer = buf; + } + + rcv_num = rcv_num + 1; + --size; + } + + return rcv_num; +} + +void CH438_PORT_INIT( uint8 ext_uart_no,uint32 BaudRate ) +{ + uint32 div; + uint8 DLL,DLM,dlab; + uint8 REG_LCR_ADDR; + uint8 REG_DLL_ADDR; + uint8 REG_DLM_ADDR; + uint8 REG_IER_ADDR; + uint8 REG_MCR_ADDR; + uint8 REG_FCR_ADDR; + uint8 REG_RBR_ADDR; + uint8 REG_THR_ADDR; + uint8 REG_IIR_ADDR; + + REG_LCR_ADDR = offset_addr[ext_uart_no] | REG_LCR0_ADDR; + REG_DLL_ADDR = offset_addr[ext_uart_no] | REG_DLL0_ADDR; + REG_DLM_ADDR = offset_addr[ext_uart_no] | REG_DLM0_ADDR; + REG_IER_ADDR = offset_addr[ext_uart_no] | REG_IER0_ADDR; + REG_MCR_ADDR = offset_addr[ext_uart_no] | REG_MCR0_ADDR; + REG_FCR_ADDR = offset_addr[ext_uart_no] | REG_FCR0_ADDR; + REG_RBR_ADDR = offset_addr[ext_uart_no] | REG_RBR0_ADDR; + REG_THR_ADDR = offset_addr[ext_uart_no] | REG_THR0_ADDR; + REG_IIR_ADDR = offset_addr[ext_uart_no] | REG_IIR0_ADDR; + + WriteCH438Data(REG_IER_ADDR, BIT_IER_RESET); /* Reset the serial port */ + MdelayKTask(50); + + dlab = ReadCH438Data(REG_IER_ADDR); + dlab &= 0xDF; + WriteCH438Data(REG_IER_ADDR, dlab); + + dlab = ReadCH438Data(REG_LCR_ADDR); + dlab |= 0x80; + WriteCH438Data(REG_LCR_ADDR, dlab); + + div = (Fpclk >> 4) / BaudRate; + DLM = div >> 8; + DLL = div & 0xff; + WriteCH438Data(REG_DLL_ADDR, DLL);/* Set baud rate */ + WriteCH438Data(REG_DLM_ADDR, DLM); + WriteCH438Data(REG_FCR_ADDR, BIT_FCR_RECVTG1 | BIT_FCR_RECVTG0 | BIT_FCR_FIFOEN);/* Set FIFO mode */ + + WriteCH438Data(REG_LCR_ADDR, BIT_LCR_WORDSZ1 | BIT_LCR_WORDSZ0); + + WriteCH438Data(REG_IER_ADDR, BIT_IER_IERECV); + + WriteCH438Data(REG_MCR_ADDR, BIT_MCR_OUT2); + + WriteCH438Data(REG_FCR_ADDR, ReadCH438Data(REG_FCR_ADDR) | BIT_FCR_TFIFORST); +} + +void CH438PortInitParityCheck(uint8 ext_uart_no,uint32 BaudRate) +{ + uint32 div; + uint8 DLL,DLM,dlab; + uint8 REG_LCR_ADDR; + uint8 REG_DLL_ADDR; + uint8 REG_DLM_ADDR; + uint8 REG_IER_ADDR; + uint8 REG_MCR_ADDR; + uint8 REG_FCR_ADDR; + uint8 REG_RBR_ADDR; + uint8 REG_THR_ADDR; + uint8 REG_IIR_ADDR; + + REG_LCR_ADDR = offset_addr[ext_uart_no] | REG_LCR0_ADDR; + REG_DLL_ADDR = offset_addr[ext_uart_no] | REG_DLL0_ADDR; + REG_DLM_ADDR = offset_addr[ext_uart_no] | REG_DLM0_ADDR; + REG_IER_ADDR = offset_addr[ext_uart_no] | REG_IER0_ADDR; + REG_MCR_ADDR = offset_addr[ext_uart_no] | REG_MCR0_ADDR; + REG_FCR_ADDR = offset_addr[ext_uart_no] | REG_FCR0_ADDR; + REG_RBR_ADDR = offset_addr[ext_uart_no] | REG_RBR0_ADDR; + REG_THR_ADDR = offset_addr[ext_uart_no] | REG_THR0_ADDR; + REG_IIR_ADDR = offset_addr[ext_uart_no] | REG_IIR0_ADDR; + + WriteCH438Data(REG_IER_ADDR, BIT_IER_RESET);/* Reset the serial port */ + MdelayKTask(50); + + dlab = ReadCH438Data(REG_IER_ADDR); + dlab &= 0xDF; + WriteCH438Data(REG_IER_ADDR, dlab); + + dlab = ReadCH438Data(REG_LCR_ADDR); + dlab |= 0x80; + WriteCH438Data(REG_LCR_ADDR, dlab); + + div = (Fpclk >> 4) / BaudRate; + DLM = div >> 8; + DLL = div & 0xff; + WriteCH438Data(REG_DLL_ADDR, DLL);/* Set baud rate */ + WriteCH438Data(REG_DLM_ADDR, DLM); + WriteCH438Data(REG_FCR_ADDR, BIT_FCR_RECVTG1 | BIT_FCR_FIFOEN);/* Set FIFO mode */ + + WriteCH438Data(REG_LCR_ADDR, BIT_LCR_WORDSZ1 | BIT_LCR_WORDSZ0 | BIT_LCR_PAREN | BIT_LCR_PARMODE0); + + WriteCH438Data(REG_IER_ADDR, BIT_IER_IERECV); + + WriteCH438Data(REG_MCR_ADDR, BIT_MCR_OUT2); + + WriteCH438Data(REG_FCR_ADDR, ReadCH438Data(REG_FCR_ADDR) | BIT_FCR_TFIFORST); +} + +void CH438_PORT_DISABLE(uint8 ext_uart_no, uint32 BaudRate) +{ + uint32 div; + uint8 DLL,DLM,dlab; + uint8 REG_LCR_ADDR; + uint8 REG_DLL_ADDR; + uint8 REG_DLM_ADDR; + uint8 REG_IER_ADDR; + uint8 REG_MCR_ADDR; + uint8 REG_FCR_ADDR; + uint8 REG_RBR_ADDR; + uint8 REG_THR_ADDR; + uint8 REG_IIR_ADDR; + + REG_LCR_ADDR = offset_addr[ext_uart_no] | REG_LCR0_ADDR; + REG_DLL_ADDR = offset_addr[ext_uart_no] | REG_DLL0_ADDR; + REG_DLM_ADDR = offset_addr[ext_uart_no] | REG_DLM0_ADDR; + REG_IER_ADDR = offset_addr[ext_uart_no] | REG_IER0_ADDR; + REG_MCR_ADDR = offset_addr[ext_uart_no] | REG_MCR0_ADDR; + REG_FCR_ADDR = offset_addr[ext_uart_no] | REG_FCR0_ADDR; + REG_RBR_ADDR = offset_addr[ext_uart_no] | REG_RBR0_ADDR; + REG_THR_ADDR = offset_addr[ext_uart_no] | REG_THR0_ADDR; + REG_IIR_ADDR = offset_addr[ext_uart_no] | REG_IIR0_ADDR; + + WriteCH438Data(REG_IER_ADDR, BIT_IER_RESET); /* Reset the serial port */ + MdelayKTask(50); + + dlab = ReadCH438Data(REG_IER_ADDR); + dlab &= 0xDF; + WriteCH438Data(REG_IER_ADDR, dlab); + + dlab = ReadCH438Data(REG_LCR_ADDR); + dlab |= 0x80; + WriteCH438Data(REG_LCR_ADDR, dlab); + + div = (Fpclk >> 4) / BaudRate; + DLM = div >> 8; + DLL = div & 0xff; + WriteCH438Data(REG_DLL_ADDR, DLL);/* Set baud rate */ + WriteCH438Data(REG_DLM_ADDR, DLM); + WriteCH438Data(REG_FCR_ADDR, BIT_FCR_RECVTG1 | BIT_FCR_RECVTG0 | BIT_FCR_FIFOEN );/* Set FIFO mode */ + + WriteCH438Data(REG_LCR_ADDR, BIT_LCR_WORDSZ1 | BIT_LCR_WORDSZ0); + + WriteCH438Data(REG_IER_ADDR, 0); + + WriteCH438Data(REG_MCR_ADDR, BIT_MCR_OUT2); + + WriteCH438Data(REG_FCR_ADDR, ReadCH438Data(REG_FCR_ADDR) | BIT_FCR_TFIFORST); +} + +void CH438_PORT6_INIT(uint8 ext_uart_no, uint32 BaudRate) +{ + uint32 div; + uint8 DLL,DLM,dlab; + uint8 REG_LCR_ADDR; + uint8 REG_DLL_ADDR; + uint8 REG_DLM_ADDR; + uint8 REG_IER_ADDR; + uint8 REG_MCR_ADDR; + uint8 REG_FCR_ADDR; + uint8 REG_RBR_ADDR; + uint8 REG_THR_ADDR; + uint8 REG_IIR_ADDR; + + REG_LCR_ADDR = offset_addr[ext_uart_no] | REG_LCR0_ADDR; + REG_DLL_ADDR = offset_addr[ext_uart_no] | REG_DLL0_ADDR; + REG_DLM_ADDR = offset_addr[ext_uart_no] | REG_DLM0_ADDR; + REG_IER_ADDR = offset_addr[ext_uart_no] | REG_IER0_ADDR; + REG_MCR_ADDR = offset_addr[ext_uart_no] | REG_MCR0_ADDR; + REG_FCR_ADDR = offset_addr[ext_uart_no] | REG_FCR0_ADDR; + REG_RBR_ADDR = offset_addr[ext_uart_no] | REG_RBR0_ADDR; + REG_THR_ADDR = offset_addr[ext_uart_no] | REG_THR0_ADDR; + REG_IIR_ADDR = offset_addr[ext_uart_no] | REG_IIR0_ADDR; + + WriteCH438Data(REG_IER_ADDR, BIT_IER_RESET);/* Reset the serial port */ + MdelayKTask(50); + + dlab = ReadCH438Data(REG_IER_ADDR); + dlab &= 0xDF; + WriteCH438Data(REG_IER_ADDR, dlab); + + dlab = ReadCH438Data(REG_LCR_ADDR); + dlab |= 0x80; + WriteCH438Data(REG_LCR_ADDR, dlab); + + //div = ( 22118400 >> 4 ) / BaudRate; + div = ( 44236800 >> 4 ) / BaudRate; + DLM = div >> 8; + DLL = div & 0xff; + WriteCH438Data(REG_DLL_ADDR, DLL);/* Set baud rate */ + WriteCH438Data(REG_DLM_ADDR, DLM); + WriteCH438Data(REG_FCR_ADDR, BIT_FCR_RECVTG1 | BIT_FCR_RECVTG0 | BIT_FCR_FIFOEN);/* Set FIFO mode */ + + WriteCH438Data(REG_LCR_ADDR, BIT_LCR_WORDSZ1 | BIT_LCR_WORDSZ0); + + WriteCH438Data(REG_IER_ADDR, BIT_IER_IERECV | BIT_IER1_CK2X); + + WriteCH438Data(REG_MCR_ADDR, BIT_MCR_OUT2); + + WriteCH438Data(REG_FCR_ADDR, ReadCH438Data(REG_FCR_ADDR) | BIT_FCR_TFIFORST); +} + +static uint32 Ch438Configure(struct SerialCfgParam *ext_serial_cfg) +{ + NULL_PARAM_CHECK(ext_serial_cfg); + + switch (ext_serial_cfg->data_cfg.port_configure) + { + case PORT_CFG_INIT: + CH438_PORT_INIT(ext_serial_cfg->data_cfg.ext_uart_no, ext_serial_cfg->data_cfg.serial_baud_rate); + break; + case PORT_CFG_PARITY_CHECK: + CH438PortInitParityCheck(ext_serial_cfg->data_cfg.ext_uart_no, ext_serial_cfg->data_cfg.serial_baud_rate); + break; + case PORT_CFG_DISABLE: + CH438_PORT_DISABLE(ext_serial_cfg->data_cfg.ext_uart_no, ext_serial_cfg->data_cfg.serial_baud_rate); + break; + case PORT_CFG_DIV: + CH438_PORT6_INIT(ext_serial_cfg->data_cfg.ext_uart_no, ext_serial_cfg->data_cfg.serial_baud_rate); + break; + default: + KPrintf("Ch438Configure do not support configure %d\n", ext_serial_cfg->data_cfg.port_configure); + return ERROR; + break; + } + + return EOK; +} + +static uint32 Ch438Init(struct SerialDriver *serial_drv, struct SerialCfgParam *ext_serial_cfg) +{ + NULL_PARAM_CHECK(serial_drv); + + struct PinParam pin_cfg; + struct PinStat pin_stat; + int ret = 0; + + struct BusConfigureInfo configure_info; + configure_info.configure_cmd = OPE_CFG; + configure_info.private_data = (void *)&pin_cfg; + + struct BusBlockWriteParam write_param; + write_param.buffer = (void *)&pin_stat; + + ch438_pin = PinBusInitGet(); + + CH438SetOutput(); + + /* config NWR pin as output*/ + pin_cfg.cmd = GPIO_CONFIG_MODE; + pin_cfg.pin = BSP_CH438_NWR_PIN; + pin_cfg.mode = GPIO_CFG_OUTPUT; + + ret = BusDrvConfigure(ch438_pin->owner_driver, &configure_info); + if (ret != EOK) { + KPrintf("config BSP_CH438_NWR_PIN pin %d failed!\n", BSP_CH438_NWR_PIN); + return ERROR; + } + + /* config NRD pin as output*/ + pin_cfg.pin = BSP_CH438_NRD_PIN; + ret = BusDrvConfigure(ch438_pin->owner_driver, &configure_info); + if (ret != EOK) { + KPrintf("config NRD pin %d failed!\n", BSP_CH438_NRD_PIN); + return ERROR; + } + + /* config ALE pin as output*/ + pin_cfg.pin = BSP_CH438_ALE_PIN; + ret = BusDrvConfigure(ch438_pin->owner_driver, &configure_info); + if (ret != EOK) { + KPrintf("config ALE pin %d failed!\n", BSP_CH438_ALE_PIN); + return ERROR; + } + + /* config ALE pin as output*/ + pin_cfg.pin = BSP_485_dir; + ret = BusDrvConfigure(ch438_pin->owner_driver, &configure_info); + if (ret != EOK) { + KPrintf("config ALE pin %d failed!\n", BSP_485_dir); + return ERROR; + } + + /* config ALE pin as input pullup*/ + pin_cfg.pin = BSP_CH438_INT_PIN; + pin_cfg.mode = GPIO_CFG_INPUT_PULLUP; + ret = BusDrvConfigure(ch438_pin->owner_driver, &configure_info); + if (ret != EOK) { + KPrintf("config INIT pin %d failed!\n", BSP_CH438_INT_PIN); + return ERROR; + } + + /* set NWR pin as high*/ + pin_stat.pin = BSP_CH438_NWR_PIN; + pin_stat.val = GPIO_HIGH; + BusDevWriteData(ch438_pin->owner_haldev, &write_param); + + /* set NRD pin as high*/ + pin_stat.pin = BSP_CH438_NRD_PIN; + pin_stat.val = GPIO_HIGH; + BusDevWriteData(ch438_pin->owner_haldev, &write_param); + + /* set ALE pin as high*/ + pin_stat.pin = BSP_CH438_ALE_PIN; + pin_stat.val = GPIO_HIGH; + BusDevWriteData(ch438_pin->owner_haldev, &write_param); + + return Ch438Configure(ext_serial_cfg); +} + +static uint32 Ch438DrvConfigure(void *drv, struct BusConfigureInfo *configure_info) +{ + NULL_PARAM_CHECK(drv); + NULL_PARAM_CHECK(configure_info); + + x_err_t ret = EOK; + + struct SerialDriver *serial_drv = (struct SerialDriver *)drv; + struct SerialCfgParam *ext_serial_cfg = (struct SerialCfgParam *)configure_info->private_data; + + switch (configure_info->configure_cmd) + { + case OPE_INT: + ret = Ch438Init(serial_drv, ext_serial_cfg); + break; + default: + break; + } + + return ret; +} + +static uint32 Ch438WriteData(void *dev, struct BusBlockWriteParam *write_param) +{ + NULL_PARAM_CHECK(dev); + NULL_PARAM_CHECK(write_param); + + struct SerialHardwareDevice *serial_dev = (struct SerialHardwareDevice *)dev; + struct SerialDevParam *dev_param = (struct SerialDevParam *)serial_dev->haldev.private_data; + + if (4 == dev_param->ext_uart_no) { + Set485Output(1); + MdelayKTask(20); + } + + CH438UartSend(dev_param->ext_uart_no, (uint8 *)write_param->buffer, write_param->size); + + if (4 == dev_param->ext_uart_no) { + MdelayKTask(20); + Set485Input(1); + } + + return EOK; +} + +static uint32 Ch438ReadData(void *dev, struct BusBlockReadParam *read_param) +{ + NULL_PARAM_CHECK(dev); + NULL_PARAM_CHECK(read_param); + + x_err_t result; + uint8 rcv_num = 0; + uint8 gInterruptStatus; + uint8 InterruptStatus; + static uint8 dat; + uint8 REG_LCR_ADDR; + uint8 REG_DLL_ADDR; + uint8 REG_DLM_ADDR; + uint8 REG_IER_ADDR; + uint8 REG_MCR_ADDR; + uint8 REG_FCR_ADDR; + uint8 REG_RBR_ADDR; + uint8 REG_THR_ADDR; + uint8 REG_IIR_ADDR; + uint8 REG_LSR_ADDR; + uint8 REG_MSR_ADDR; + + struct SerialHardwareDevice *serial_dev = (struct SerialHardwareDevice *)dev; + struct SerialDevParam *dev_param = (struct SerialDevParam *)serial_dev->haldev.private_data; + + result = KSemaphoreObtain(ch438_sem, WAITING_FOREVER); + if (EOK == result) { + gInterruptStatus = ReadCH438Data(REG_SSR_ADDR); + + if(!gInterruptStatus) { + dat = ReadCH438Data(REG_LCR0_ADDR); + dat = ReadCH438Data(REG_IER0_ADDR); + dat = ReadCH438Data(REG_MCR0_ADDR); + dat = ReadCH438Data(REG_LSR0_ADDR); + dat = ReadCH438Data(REG_MSR0_ADDR); + dat = ReadCH438Data(REG_RBR0_ADDR); + dat = ReadCH438Data(REG_THR0_ADDR); + dat = ReadCH438Data(REG_IIR0_ADDR); + dat = dat; + } else { + if ( gInterruptStatus & interrupt_num[dev_param->ext_uart_no]) { /* Detect which serial port is interrupted */ + REG_LCR_ADDR = offset_addr[dev_param->ext_uart_no] | REG_LCR0_ADDR; + REG_DLL_ADDR = offset_addr[dev_param->ext_uart_no] | REG_DLL0_ADDR; + REG_DLM_ADDR = offset_addr[dev_param->ext_uart_no] | REG_DLM0_ADDR; + REG_IER_ADDR = offset_addr[dev_param->ext_uart_no] | REG_IER0_ADDR; + REG_MCR_ADDR = offset_addr[dev_param->ext_uart_no] | REG_MCR0_ADDR; + REG_FCR_ADDR = offset_addr[dev_param->ext_uart_no] | REG_FCR0_ADDR; + REG_RBR_ADDR = offset_addr[dev_param->ext_uart_no] | REG_RBR0_ADDR; + REG_THR_ADDR = offset_addr[dev_param->ext_uart_no] | REG_THR0_ADDR; + REG_IIR_ADDR = offset_addr[dev_param->ext_uart_no] | REG_IIR0_ADDR; + REG_LSR_ADDR = offset_addr[dev_param->ext_uart_no] | REG_LSR0_ADDR; + REG_MSR_ADDR = offset_addr[dev_param->ext_uart_no] | REG_MSR0_ADDR; + + /* The interrupted state of a read serial port */ + InterruptStatus = ReadCH438Data(REG_IIR_ADDR) & 0x0f; + + switch( InterruptStatus ) + { + case INT_NOINT: + break; + case INT_THR_EMPTY: + break; + case INT_RCV_OVERTIME: /* Receiving timeout interruption, triggered when no further data is available four data times after receiving a frame*/ + case INT_RCV_SUCCESS: /* Interrupts are available to receive data */ + rcv_num = CH438UARTRcv(dev_param->ext_uart_no, (uint8 *)read_param->buffer, read_param->size); + read_param->read_length = rcv_num; + break; + case INT_RCV_LINES: /* Receiving line status interrupted */ + ReadCH438Data(REG_LSR_ADDR); + break; + case INT_MODEM_CHANGE: /* MODEM input changes interrupt */ + ReadCH438Data(REG_MSR_ADDR); + break; + default: + break; + } + } + } + } + return rcv_num; +} + +static const struct SerialDevDone dev_done = +{ + NONE, + NONE, + Ch438WriteData, + Ch438ReadData, +}; + +static void Ch438InitDefault(struct SerialDriver *serial_drv) +{ + struct PinParam pin_cfg; + BusType ch438_pin; + + struct BusConfigureInfo configure_info; + + int ret = 0; + configure_info.configure_cmd = OPE_CFG; + configure_info.private_data = (void *)&pin_cfg; + + ch438_sem = KSemaphoreCreate(0); + if (ch438_sem < 0) { + KPrintf("Ch438InitDefault create sem failed .\n"); + return ; + } + + ch438_pin = PinBusInitGet(); + + pin_cfg.cmd = GPIO_CONFIG_MODE; + pin_cfg.pin = BSP_CH438_INT_PIN; + pin_cfg.mode = GPIO_CFG_INPUT_PULLUP; + ret = BusDrvConfigure(ch438_pin->owner_driver, &configure_info); + if (ret != EOK) { + KPrintf("config BSP_CH438_INT_PIN pin %d failed!\n", BSP_CH438_INT_PIN); + return; + } + + pin_cfg.cmd = GPIO_IRQ_REGISTER; + pin_cfg.pin = BSP_CH438_INT_PIN; + pin_cfg.irq_set.irq_mode = GPIO_IRQ_EDGE_FALLING; + pin_cfg.irq_set.hdr = (void *)Ch438Irq; + pin_cfg.irq_set.args = NONE; + ret = BusDrvConfigure(ch438_pin->owner_driver, &configure_info); + if (ret != EOK) { + KPrintf("config BSP_CH438_INT_PIN %d failed!\n", BSP_CH438_INT_PIN); + return; + } + + pin_cfg.cmd = GPIO_IRQ_ENABLE; + pin_cfg.pin = BSP_CH438_INT_PIN; + ret = BusDrvConfigure(ch438_pin->owner_driver, &configure_info); + if (ret != EOK) { + KPrintf("config BSP_CH438_INT_PIN %d failed!\n", BSP_CH438_INT_PIN); + return; + } + + struct SerialCfgParam serial_cfg; + memset(&serial_cfg, 0, sizeof(struct SerialCfgParam)); + configure_info.configure_cmd = OPE_INT; + configure_info.private_data = (void *)&serial_cfg; + + serial_cfg.data_cfg.port_configure = PORT_CFG_INIT; + + serial_cfg.data_cfg.ext_uart_no = 0; + serial_cfg.data_cfg.serial_baud_rate = BAUD_RATE_115200; + BusDrvConfigure(&serial_drv->driver, &configure_info); + + serial_cfg.data_cfg.ext_uart_no = 1; + serial_cfg.data_cfg.serial_baud_rate = BAUD_RATE_9600; + BusDrvConfigure(&serial_drv->driver, &configure_info); + + serial_cfg.data_cfg.ext_uart_no = 2; + serial_cfg.data_cfg.serial_baud_rate = BAUD_RATE_9600; + BusDrvConfigure(&serial_drv->driver, &configure_info); + + serial_cfg.data_cfg.ext_uart_no = 3; + serial_cfg.data_cfg.serial_baud_rate = BAUD_RATE_9600; + BusDrvConfigure(&serial_drv->driver, &configure_info); + + serial_cfg.data_cfg.ext_uart_no = 4; + serial_cfg.data_cfg.serial_baud_rate = BAUD_RATE_9600; + BusDrvConfigure(&serial_drv->driver, &configure_info); + + serial_cfg.data_cfg.ext_uart_no = 5; + serial_cfg.data_cfg.serial_baud_rate = BAUD_RATE_115200; + BusDrvConfigure(&serial_drv->driver, &configure_info); + + serial_cfg.data_cfg.ext_uart_no = 6; + serial_cfg.data_cfg.serial_baud_rate = BAUD_RATE_57600; + BusDrvConfigure(&serial_drv->driver, &configure_info); + + serial_cfg.data_cfg.ext_uart_no = 7; + serial_cfg.data_cfg.serial_baud_rate = BAUD_RATE_9600; + BusDrvConfigure(&serial_drv->driver, &configure_info); +} + +static uint32 Ch438DevRegister(struct SerialHardwareDevice *serial_dev, char *dev_name) +{ + x_err_t ret = EOK; + serial_dev->dev_done = &dev_done; + serial_dev->ext_serial_mode = RET_TRUE; + ret = SerialDeviceRegister(serial_dev, NONE, dev_name); + if (ret != EOK) { + KPrintf("HwCh438Init Serial device %s register error %d\n", dev_name, ret); + return ERROR; + } + + ret = SerialDeviceAttachToBus(dev_name, CH438_BUS_NAME); + if (ret != EOK) { + KPrintf("HwCh438Init Serial device %s register error %d\n", dev_name, ret); + return ERROR; + } + + return ret; +} + +int HwCh438Init(void) +{ + static struct SerialBus serial_bus; + static struct SerialDriver serial_drv; + + x_err_t ret = EOK; + + ret = SerialBusInit(&serial_bus, CH438_BUS_NAME); + if (ret != EOK) { + KPrintf("HwCh438Init Serial bus init error %d\n", ret); + return ERROR; + } + + serial_drv.configure = &Ch438DrvConfigure; + ret = SerialDriverInit(&serial_drv, CH438_DRIVER_NAME); + if (ret != EOK) { + KPrintf("HwCh438Init Serial driver init error %d\n", ret); + return ERROR; + } + + ret = SerialDriverAttachToBus(CH438_DRIVER_NAME, CH438_BUS_NAME); + if (ret != EOK) { + KPrintf("HwCh438Init Serial driver attach error %d\n", ret); + return ERROR; + } + + static struct SerialHardwareDevice serial_dev_0; + static struct SerialDevParam dev_param_0; + dev_param_0.ext_uart_no = 0; + serial_dev_0.haldev.private_data = (void *)&dev_param_0; + ret = Ch438DevRegister(&serial_dev_0, CH438_DEVICE_NAME_0); + if (ret != EOK) { + KPrintf("HwCh438Init Ch438DevRegister error %d\n", ret); + return ERROR; + } + + static struct SerialHardwareDevice serial_dev_1; + static struct SerialDevParam dev_param_1; + dev_param_1.ext_uart_no = 1; + serial_dev_1.haldev.private_data = (void *)&dev_param_1; + ret = Ch438DevRegister(&serial_dev_1, CH438_DEVICE_NAME_1); + if (ret != EOK) { + KPrintf("HwCh438Init Ch438DevRegister error %d\n", ret); + return ERROR; + } + + static struct SerialHardwareDevice serial_dev_2; + static struct SerialDevParam dev_param_2; + dev_param_2.ext_uart_no = 2; + serial_dev_2.haldev.private_data = (void *)&dev_param_2; + ret = Ch438DevRegister(&serial_dev_2, CH438_DEVICE_NAME_2); + if (ret != EOK) { + KPrintf("HwCh438Init Ch438DevRegister error %d\n", ret); + return ERROR; + } + + static struct SerialHardwareDevice serial_dev_3; + static struct SerialDevParam dev_param_3; + dev_param_3.ext_uart_no = 3; + serial_dev_3.haldev.private_data = (void *)&dev_param_3; + ret = Ch438DevRegister(&serial_dev_3, CH438_DEVICE_NAME_3); + if (ret != EOK) { + KPrintf("HwCh438Init Ch438DevRegister error %d\n", ret); + return ERROR; + } + + static struct SerialHardwareDevice serial_dev_4; + static struct SerialDevParam dev_param_4; + dev_param_4.ext_uart_no = 4; + serial_dev_4.haldev.private_data = (void *)&dev_param_4; + ret = Ch438DevRegister(&serial_dev_4, CH438_DEVICE_NAME_4); + if (ret != EOK) { + KPrintf("HwCh438Init Ch438DevRegister error %d\n", ret); + return ERROR; + } + + static struct SerialHardwareDevice serial_dev_5; + static struct SerialDevParam dev_param_5; + dev_param_5.ext_uart_no = 5; + serial_dev_5.haldev.private_data = (void *)&dev_param_5; + ret = Ch438DevRegister(&serial_dev_5, CH438_DEVICE_NAME_5); + if (ret != EOK) { + KPrintf("HwCh438Init Ch438DevRegister error %d\n", ret); + return ERROR; + } + + static struct SerialHardwareDevice serial_dev_6; + static struct SerialDevParam dev_param_6; + dev_param_6.ext_uart_no = 6; + serial_dev_6.private_data = (void *)&dev_param_6; + ret = Ch438DevRegister(&serial_dev_6, CH438_DEVICE_NAME_6); + if (ret != EOK) { + KPrintf("HwCh438Init Ch438DevRegister error %d\n", ret); + return ERROR; + } + + static struct SerialHardwareDevice serial_dev_7; + static struct SerialDevParam dev_param_7; + dev_param_7.ext_uart_no = 7; + serial_dev_7.private_data = (void *)&dev_param_7; + ret = Ch438DevRegister(&serial_dev_7, CH438_DEVICE_NAME_7); + if (ret != EOK) { + KPrintf("HwCh438Init Ch438DevRegister error %d\n", ret); + return ERROR; + } + + Ch438InitDefault(&serial_drv); + + return ret; +} diff --git a/Ubiquitous/XiZi/board/aiit-riscv64-board/third_party_driver/dma/Kconfig b/Ubiquitous/XiZi/board/aiit-riscv64-board/third_party_driver/dma/Kconfig new file mode 100644 index 0000000..8b13789 --- /dev/null +++ b/Ubiquitous/XiZi/board/aiit-riscv64-board/third_party_driver/dma/Kconfig @@ -0,0 +1 @@ + diff --git a/Ubiquitous/XiZi/board/aiit-riscv64-board/third_party_driver/dma/Makefile b/Ubiquitous/XiZi/board/aiit-riscv64-board/third_party_driver/dma/Makefile new file mode 100644 index 0000000..2929b90 --- /dev/null +++ b/Ubiquitous/XiZi/board/aiit-riscv64-board/third_party_driver/dma/Makefile @@ -0,0 +1,6 @@ +SRC_FILES := dmac.c + + + + +include $(KERNEL_ROOT)/compiler.mk diff --git a/Ubiquitous/XiZi/board/aiit-riscv64-board/third_party_driver/gpio/Kconfig b/Ubiquitous/XiZi/board/aiit-riscv64-board/third_party_driver/gpio/Kconfig new file mode 100644 index 0000000..35dce73 --- /dev/null +++ b/Ubiquitous/XiZi/board/aiit-riscv64-board/third_party_driver/gpio/Kconfig @@ -0,0 +1,11 @@ +config PIN_BUS_NAME + string "pin bus name" + default "pin" + +config PIN_DRIVER_NAME + string "pin driver name" + default "pin_drv" + +config PIN_DEVICE_NAME + string "pin device name" + default "pin_dev" diff --git a/Ubiquitous/XiZi/board/aiit-riscv64-board/third_party_driver/gpio/Makefile b/Ubiquitous/XiZi/board/aiit-riscv64-board/third_party_driver/gpio/Makefile new file mode 100644 index 0000000..e017f07 --- /dev/null +++ b/Ubiquitous/XiZi/board/aiit-riscv64-board/third_party_driver/gpio/Makefile @@ -0,0 +1,8 @@ +SRC_FILES := connect_gpio.c drv_io_config.c fpioa.c gpio.c gpiohs.c utils.c + + + + + + +include $(KERNEL_ROOT)/compiler.mk diff --git a/Ubiquitous/XiZi/board/aiit-riscv64-board/third_party_driver/i2c/Kconfig b/Ubiquitous/XiZi/board/aiit-riscv64-board/third_party_driver/i2c/Kconfig new file mode 100644 index 0000000..c935369 --- /dev/null +++ b/Ubiquitous/XiZi/board/aiit-riscv64-board/third_party_driver/i2c/Kconfig @@ -0,0 +1,17 @@ +if BSP_USING_I2C + config BSP_I2C_SDA + int "SDA pin number for I2C" + default 15 + config BSP_I2C_SCL + int "SCLK pin number for I2C" + default 17 + config I2C_BUS_NAME_1 + string "i2c bus 1 name" + default "i2c1" + config I2C_DRV_NAME_1 + string "i2c bus 1 driver name" + default "i2c1_drv" + config I2C_1_DEVICE_NAME_0 + string "i2c bus 1 device 0 name" + default "i2c1_dev0" +endif diff --git a/Ubiquitous/XiZi/board/aiit-riscv64-board/third_party_driver/i2c/Makefile b/Ubiquitous/XiZi/board/aiit-riscv64-board/third_party_driver/i2c/Makefile new file mode 100644 index 0000000..f4ca450 --- /dev/null +++ b/Ubiquitous/XiZi/board/aiit-riscv64-board/third_party_driver/i2c/Makefile @@ -0,0 +1,6 @@ +SRC_FILES := hardware_i2c.c connect_i2c.c + + + + +include $(KERNEL_ROOT)/compiler.mk diff --git a/Ubiquitous/XiZi/board/aiit-riscv64-board/third_party_driver/include/connect_ch376.h b/Ubiquitous/XiZi/board/aiit-riscv64-board/third_party_driver/include/connect_ch376.h new file mode 100644 index 0000000..0f13537 --- /dev/null +++ b/Ubiquitous/XiZi/board/aiit-riscv64-board/third_party_driver/include/connect_ch376.h @@ -0,0 +1,36 @@ +/* +* Copyright (c) 2020 AIIT XUOS Lab +* XiUOS is licensed under Mulan PSL v2. +* You can use this software according to the terms and conditions of the Mulan PSL v2. +* You may obtain a copy of Mulan PSL v2 at: +* http://license.coscl.org.cn/MulanPSL2 +* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, +* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, +* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. +* See the Mulan PSL v2 for more details. +*/ + +/** +* @file connect_ch376.h +* @brief define aiit-riscv64-board ch376 function and struct +* @version 1.0 +* @author AIIT XUOS Lab +* @date 2021-04-25 +*/ + +#ifndef CONNECT_CH376_H +#define CONNECT_CH376_H + +#include + +struct HwCh376 +{ + HardwareDevType dev; + x_size_t msg_len; + int sem; + KTaskDescriptorType task; +}; + +int HwCh376Init(void); + +#endif diff --git a/Ubiquitous/XiZi/board/aiit-riscv64-board/third_party_driver/include/connect_ch438.h b/Ubiquitous/XiZi/board/aiit-riscv64-board/third_party_driver/include/connect_ch438.h new file mode 100755 index 0000000..09e005d --- /dev/null +++ b/Ubiquitous/XiZi/board/aiit-riscv64-board/third_party_driver/include/connect_ch438.h @@ -0,0 +1,259 @@ +/* +* Copyright (c) 2020 AIIT XUOS Lab +* XiUOS is licensed under Mulan PSL v2. +* You can use this software according to the terms and conditions of the Mulan PSL v2. +* You may obtain a copy of Mulan PSL v2 at: +* http://license.coscl.org.cn/MulanPSL2 +* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, +* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, +* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. +* See the Mulan PSL v2 for more details. +*/ + +/** +* @file connect_ch438.h +* @brief define aiit-riscv64-board ch438 function and struct +* @version 1.0 +* @author AIIT XUOS Lab +* @date 2021-04-25 +*/ + +#ifndef CONNECT_CH438_H +#define CONNECT_CH438_H + +#include + +#define BUFFSIZE 255 + +/******************************************************************************************/ + +/* CH438serial port0 register address */ + +#define REG_RBR0_ADDR 0x00 /* serial port0receive buffer register address */ +#define REG_THR0_ADDR 0x00 /* serial port0send hold register address */ +#define REG_IER0_ADDR 0x01 /* serial port0interrupt enable register address */ +#define REG_IIR0_ADDR 0x02 /* serial port0interrupt identifies register address */ +#define REG_FCR0_ADDR 0x02 /* serial port0FIFO controls register address */ +#define REG_LCR0_ADDR 0x03 /* serial port0circuit control register address */ +#define REG_MCR0_ADDR 0x04 /* serial port0MODEM controls register address */ +#define REG_LSR0_ADDR 0x05 /* serial port0line status register address */ +#define REG_MSR0_ADDR 0x06 /* serial port0address of MODEM status register */ +#define REG_SCR0_ADDR 0x07 /* serial port0the user can define the register address */ +#define REG_DLL0_ADDR 0x00 /* Baud rate divisor latch low 8-bit byte address */ +#define REG_DLM0_ADDR 0x01 /* Baud rate divisor latch high 8-bit byte address */ + +/* CH438serial port1 register address */ + +#define REG_RBR1_ADDR 0x10 /* serial port1receive buffer register address */ +#define REG_THR1_ADDR 0x10 /* serial port1send hold register address */ +#define REG_IER1_ADDR 0x11 /* serial port1interrupt enable register address */ +#define REG_IIR1_ADDR 0x12 /* serial port1interrupt identifies register address */ +#define REG_FCR1_ADDR 0x12 /* serial port1FIFO controls register address */ +#define REG_LCR1_ADDR 0x13 /* serial port1circuit control register address */ +#define REG_MCR1_ADDR 0x14 /* serial port1MODEM controls register address */ +#define REG_LSR1_ADDR 0x15 /* serial port1line status register address */ +#define REG_MSR1_ADDR 0x16 /* serial port1address of MODEM status register */ +#define REG_SCR1_ADDR 0x17 /* serial port1the user can define the register address */ +#define REG_DLL1_ADDR 0x10 /* Baud rate divisor latch low 8-bit byte address */ +#define REG_DLM1_ADDR 0x11 /* Baud rate divisor latch high 8-bit byte address */ + + +/* CH438serial port2 register address */ + +#define REG_RBR2_ADDR 0x20 /* serial port2receive buffer register address */ +#define REG_THR2_ADDR 0x20 /* serial port2send hold register address */ +#define REG_IER2_ADDR 0x21 /* serial port2interrupt enable register address */ +#define REG_IIR2_ADDR 0x22 /* serial port2interrupt identifies register address */ +#define REG_FCR2_ADDR 0x22 /* serial port2FIFO controls register address */ +#define REG_LCR2_ADDR 0x23 /* serial port2circuit control register address */ +#define REG_MCR2_ADDR 0x24 /* serial port2MODEM controls register address */ +#define REG_LSR2_ADDR 0x25 /* serial port2line status register address */ +#define REG_MSR2_ADDR 0x26 /* serial port2address of MODEM status register */ +#define REG_SCR2_ADDR 0x27 /* serial port2the user can define the register address */ +#define REG_DLL2_ADDR 0x20 /* Baud rate divisor latch low 8-bit byte address */ +#define REG_DLM2_ADDR 0x21 /* Baud rate divisor latch high 8-bit byte address */ + + + +/* CH438serial port3 register address */ + +#define REG_RBR3_ADDR 0x30 /* serial port3receive buffer register address */ +#define REG_THR3_ADDR 0x30 /* serial port3send hold register address */ +#define REG_IER3_ADDR 0x31 /* serial port3interrupt enable register address */ +#define REG_IIR3_ADDR 0x32 /* serial port3interrupt identifies register address */ +#define REG_FCR3_ADDR 0x32 /* serial port3FIFO controls register address */ +#define REG_LCR3_ADDR 0x33 /* serial port3circuit control register address */ +#define REG_MCR3_ADDR 0x34 /* serial port3MODEM controls register address */ +#define REG_LSR3_ADDR 0x35 /* serial port3line status register address */ +#define REG_MSR3_ADDR 0x36 /* serial port3address of MODEM status register */ +#define REG_SCR3_ADDR 0x37 /* serial port3the user can define the register address */ +#define REG_DLL3_ADDR 0x30 /* Baud rate divisor latch low 8-bit byte address */ +#define REG_DLM3_ADDR 0x31 /* Baud rate divisor latch high 8-bit byte address */ + + +/* CH438serial port4 register address */ + +#define REG_RBR4_ADDR 0x08 /* serial port4receive buffer register address */ +#define REG_THR4_ADDR 0x08 /* serial port4send hold register address */ +#define REG_IER4_ADDR 0x09 /* serial port4interrupt enable register address */ +#define REG_IIR4_ADDR 0x0A /* serial port4interrupt identifies register address */ +#define REG_FCR4_ADDR 0x0A /* serial port4FIFO controls register address */ +#define REG_LCR4_ADDR 0x0B /* serial port4circuit control register address */ +#define REG_MCR4_ADDR 0x0C /* serial port4MODEM controls register address */ +#define REG_LSR4_ADDR 0x0D /* serial port4line status register address */ +#define REG_MSR4_ADDR 0x0E /* serial port4address of MODEM status register */ +#define REG_SCR4_ADDR 0x0F /* serial port4the user can define the register address */ +#define REG_DLL4_ADDR 0x08 /* Baud rate divisor latch low 8-bit byte address */ +#define REG_DLM4_ADDR 0x09 /* Baud rate divisor latch high 8-bit byte address */ + + + +/* CH438serial port5 register address */ + +#define REG_RBR5_ADDR 0x18 /* serial port5receive buffer register address */ +#define REG_THR5_ADDR 0x18 /* serial port5send hold register address */ +#define REG_IER5_ADDR 0x19 /* serial port5interrupt enable register address */ +#define REG_IIR5_ADDR 0x1A /* serial port5interrupt identifies register address */ +#define REG_FCR5_ADDR 0x1A /* serial port5FIFO controls register address */ +#define REG_LCR5_ADDR 0x1B /* serial port5circuit control register address */ +#define REG_MCR5_ADDR 0x1C /* serial port5MODEM controls register address */ +#define REG_LSR5_ADDR 0x1D /* serial port5line status register address */ +#define REG_MSR5_ADDR 0x1E /* serial port5address of MODEM status register */ +#define REG_SCR5_ADDR 0x1F /* serial port5the user can define the register address */ +#define REG_DLL5_ADDR 0x18 /* Baud rate divisor latch low 8-bit byte address */ +#define REG_DLM5_ADDR 0x19 /* Baud rate divisor latch high 8-bit byte address */ + + +/* CH438serial port6 register address */ + +#define REG_RBR6_ADDR 0x28 /* serial port6receive buffer register address */ +#define REG_THR6_ADDR 0x28 /* serial port6send hold register address */ +#define REG_IER6_ADDR 0x29 /* serial port6interrupt enable register address */ +#define REG_IIR6_ADDR 0x2A /* serial port6interrupt identifies register address */ +#define REG_FCR6_ADDR 0x2A /* serial port6FIFO controls register address */ +#define REG_LCR6_ADDR 0x2B /* serial port6circuit control register address */ +#define REG_MCR6_ADDR 0x2C /* serial port6MODEM controls register address */ +#define REG_LSR6_ADDR 0x2D /* serial port6line status register address */ +#define REG_MSR6_ADDR 0x2E /* serial port6address of MODEM status register */ +#define REG_SCR6_ADDR 0x2F /* serial port6the user can define the register address */ +#define REG_DLL6_ADDR 0x28 /* Baud rate divisor latch low 8-bit byte address */ +#define REG_DLM6_ADDR 0x29 /* Baud rate divisor latch high 8-bit byte address */ + + +/* CH438serial port7 register address */ + +#define REG_RBR7_ADDR 0x38 /* serial port7receive buffer register address */ +#define REG_THR7_ADDR 0x38 /* serial port7send hold register address */ +#define REG_IER7_ADDR 0x39 /* serial port7interrupt enable register address */ +#define REG_IIR7_ADDR 0x3A /* serial port7interrupt identifies register address */ +#define REG_FCR7_ADDR 0x3A /* serial port7FIFO controls register address */ +#define REG_LCR7_ADDR 0x3B /* serial port7circuit control register address */ +#define REG_MCR7_ADDR 0x3C /* serial port7MODEM controls register address */ +#define REG_LSR7_ADDR 0x3D /* serial port7line status register address */ +#define REG_MSR7_ADDR 0x3E /* serial port7address of MODEM status register */ +#define REG_SCR7_ADDR 0x3F /* serial port7the user can define the register address */ +#define REG_DLL7_ADDR 0x38 /* Baud rate divisor latch low 8-bit byte address */ +#define REG_DLM7_ADDR 0x39 /* Baud rate divisor latch high 8-bit byte address */ + + +#define REG_SSR_ADDR 0x4F /* pecial status register address */ + + +/* IER register bit */ + +#define BIT_IER_RESET 0x80 /* The bit is 1 soft reset serial port */ +#define BIT_IER_LOWPOWER 0x40 /* The bit is 1 close serial port internal reference clock */ +#define BIT_IER_SLP 0x20 /* serial port0 is SLP, 1 close clock vibrator */ +#define BIT_IER1_CK2X 0x20 /* serial port1 is CK2X, 1 force the external clock signal after 2 times as internal reference clock */ +#define BIT_IER_IEMODEM 0x08 /* The bit is 1 allows MODEM input status to interrupt */ +#define BIT_IER_IELINES 0x04 /* The bit is 1 allow receiving line status to be interrupted */ +#define BIT_IER_IETHRE 0x02 /* The bit is 1 allows the send hold register to break in mid-air */ +#define BIT_IER_IERECV 0x01 /* The bit is 1 allows receiving data interrupts */ + +/* IIR register bit */ + +#define BIT_IIR_FIFOENS1 0x80 +#define BIT_IIR_FIFOENS0 0x40 /* The two is 1 said use FIFO */ + +/* Interrupt type: 0001 has no interrupt, 0110 receiving line status is interrupted, 0100 receiving data can be interrupted, +1100 received data timeout interrupt, 0010THR register air interrupt, 0000MODEM input change interrupt */ +#define BIT_IIR_IID3 0x08 +#define BIT_IIR_IID2 0x04 +#define BIT_IIR_IID1 0x02 +#define BIT_IIR_NOINT 0x01 + +/* FCR register bit */ + +/* Trigger point: 00 corresponds to 1 byte, 01 corresponds to 16 bytes, 10 corresponds to 64 bytes, 11 corresponds to 112 bytes */ +#define BIT_FCR_RECVTG1 0x80 /* Set the trigger point for FIFO interruption and automatic hardware flow control */ +#define BIT_FCR_RECVTG0 0x40 /* Set the trigger point for FIFO interruption and automatic hardware flow control */ + +#define BIT_FCR_TFIFORST 0x04 /* The bit is 1 empty the data sent in FIFO */ +#define BIT_FCR_RFIFORST 0x02 /* The bit is 1 empty the data sent in FIFO */ +#define BIT_FCR_FIFOEN 0x01 /* The bit is 1 use FIFO, 0 disable FIFO */ + +/* LCR register bit */ + +#define BIT_LCR_DLAB 0x80 /* To access DLL, DLM, 0 to access RBR/THR/IER */ +#define BIT_LCR_BREAKEN 0x40 /* 1 forces a BREAK line interval*/ + +/* Set the check format: when PAREN is 1, 00 odd check, 01 even check, 10 MARK (set 1), 11 blank (SPACE, clear 0) */ +#define BIT_LCR_PARMODE1 0x20 /* Sets the parity bit format */ +#define BIT_LCR_PARMODE0 0x10 /* Sets the parity bit format */ + +#define BIT_LCR_PAREN 0x08 /* A value of 1 allows you to generate and receive parity bits when sending */ +#define BIT_LCR_STOPBIT 0x04 /* If is 1, then two stop bits, is 0, a stop bit */ + +/* Set word length: 00 for 5 data bits, 01 for 6 data bits, 10 for 7 data bits and 11 for 8 data bits */ +#define BIT_LCR_WORDSZ1 0x02 /* Set the word length length */ +#define BIT_LCR_WORDSZ0 0x01 + +/* MCR register bit */ + +#define BIT_MCR_AFE 0x20 /* For 1 allows automatic flow control of CTS and RTS hardware */ +#define BIT_MCR_LOOP 0x10 /* Is the test mode of 1 enabling internal loop */ +#define BIT_MCR_OUT2 0x08 /* 1 Allows an interrupt request for the serial port output */ +#define BIT_MCR_OUT1 0x04 /* The MODEM control bit defined for the user */ +#define BIT_MCR_RTS 0x02 /* The bit is 1 RTS pin output effective */ +#define BIT_MCR_DTR 0x01 /* The bit is 1 DTR pin output effective */ + +/* LSR register bit */ + +#define BIT_LSR_RFIFOERR 0x80 /* 1 said There is at least one error in receiving FIFO */ +#define BIT_LSR_TEMT 0x40 /* 1 said THR and TSR are empty */ +#define BIT_LSR_THRE 0x20 /* 1 said THR is empty*/ +#define BIT_LSR_BREAKINT 0x10 /* The bit is 1 said the BREAK line interval was detected*/ +#define BIT_LSR_FRAMEERR 0x08 /* The bit is 1 said error reading data frame */ +#define BIT_LSR_PARERR 0x04 /* The bit is 1 said parity error */ +#define BIT_LSR_OVERR 0x02 /* 1 said receive FIFO buffer overflow */ +#define BIT_LSR_DATARDY 0x01 /* The bit is 1 said receive data received in FIFO */ + +/* MSR register bit */ + +#define BIT_MSR_DCD 0x80 /* The bit is 1 said DCD pin effective */ +#define BIT_MSR_RI 0x40 /* The bit is 1 said RI pin effective */ +#define BIT_MSR_DSR 0x20 /* The bit is 1 said DSR pin effective */ +#define BIT_MSR_CTS 0x10 /* The bit is 1 said CTS pin effective */ +#define BIT_MSR_DDCD 0x08 /* The bit is 1 said DCD pin The input state has changed */ +#define BIT_MSR_TERI 0x04 /* The bit is 1 said RI pin The input state has changed */ +#define BIT_MSR_DDSR 0x02 /* The bit is 1 said DSR pin The input state has changed */ +#define BIT_MSR_DCTS 0x01 /* The bit is 1 said CTS pin The input state has changed */ + +/* Interrupt status code */ + +#define INT_NOINT 0x01 /* There is no interruption */ +#define INT_THR_EMPTY 0x02 /* THR empty interruption */ +#define INT_RCV_OVERTIME 0x0C /* Receive timeout interrupt */ +#define INT_RCV_SUCCESS 0x04 /* Interrupts are available to receive data */ +#define INT_RCV_LINES 0x06 /* Receiving line status interrupted */ +#define INT_MODEM_CHANGE 0x00 /* MODEM input changes interrupt */ + +#define CH438_IIR_FIFOS_ENABLED 0xC0 /* use FIFO */ + + +#define Fpclk 1843200 /* Define the internal clock frequency */ + +void Set485Input(uint8 ch_no); +void Set485Output(uint8 ch_no); + +#endif diff --git a/Ubiquitous/XiZi/board/aiit-riscv64-board/third_party_driver/include/connect_gpio.h b/Ubiquitous/XiZi/board/aiit-riscv64-board/third_party_driver/include/connect_gpio.h new file mode 100644 index 0000000..d3adbbe --- /dev/null +++ b/Ubiquitous/XiZi/board/aiit-riscv64-board/third_party_driver/include/connect_gpio.h @@ -0,0 +1,36 @@ +/* +* Copyright (c) 2020 AIIT XUOS Lab +* XiUOS is licensed under Mulan PSL v2. +* You can use this software according to the terms and conditions of the Mulan PSL v2. +* You may obtain a copy of Mulan PSL v2 at: +* http://license.coscl.org.cn/MulanPSL2 +* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, +* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, +* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. +* See the Mulan PSL v2 for more details. +*/ + +/** +* @file connect_gpio.h +* @brief define aiit-riscv64-board gpio function and struct +* @version 1.0 +* @author AIIT XUOS Lab +* @date 2021-04-25 +*/ + +#ifndef CONNECT_GPIO_H +#define CONNECT_GPIO_H + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +int HwGpioInit(void); + +#ifdef __cplusplus +} +#endif + +#endif \ No newline at end of file diff --git a/Ubiquitous/XiZi/board/aiit-riscv64-board/third_party_driver/include/connect_hwtimer.h b/Ubiquitous/XiZi/board/aiit-riscv64-board/third_party_driver/include/connect_hwtimer.h new file mode 100644 index 0000000..cb0a99e --- /dev/null +++ b/Ubiquitous/XiZi/board/aiit-riscv64-board/third_party_driver/include/connect_hwtimer.h @@ -0,0 +1,37 @@ +/* +* Copyright (c) 2020 AIIT XUOS Lab +* XiUOS is licensed under Mulan PSL v2. +* You can use this software according to the terms and conditions of the Mulan PSL v2. +* You may obtain a copy of Mulan PSL v2 at: +* http://license.coscl.org.cn/MulanPSL2 +* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, +* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, +* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. +* See the Mulan PSL v2 for more details. +*/ + +/** +* @file connect_hwtimer.h +* @brief define aiit-riscv64-board hwtimer function and struct +* @version 1.0 +* @author AIIT XUOS Lab +* @date 2021-04-25 +*/ + +#ifndef CONNECT_HWTIMER_H +#define CONNECT_HWTIMER_H + +#include +#include "hardware_hwtimer.h" + +#ifdef __cplusplus +extern "C" { +#endif + +int HwTimerInit(void); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/Ubiquitous/XiZi/board/aiit-riscv64-board/third_party_driver/include/connect_i2c.h b/Ubiquitous/XiZi/board/aiit-riscv64-board/third_party_driver/include/connect_i2c.h new file mode 100644 index 0000000..bdeabe5 --- /dev/null +++ b/Ubiquitous/XiZi/board/aiit-riscv64-board/third_party_driver/include/connect_i2c.h @@ -0,0 +1,36 @@ +/* +* Copyright (c) 2020 AIIT XUOS Lab +* XiUOS is licensed under Mulan PSL v2. +* You can use this software according to the terms and conditions of the Mulan PSL v2. +* You may obtain a copy of Mulan PSL v2 at: +* http://license.coscl.org.cn/MulanPSL2 +* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, +* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, +* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. +* See the Mulan PSL v2 for more details. +*/ + +/** +* @file connect_i2c.h +* @brief define aiit-riscv64-board i2c function and struct +* @version 1.0 +* @author AIIT XUOS Lab +* @date 2021-04-25 +*/ + +#ifndef CONNECT_I2C_H +#define CONNECT_I2C_H + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +int HwI2cInit(void); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/Ubiquitous/XiZi/board/aiit-riscv64-board/third_party_driver/include/connect_lcd.h b/Ubiquitous/XiZi/board/aiit-riscv64-board/third_party_driver/include/connect_lcd.h new file mode 100644 index 0000000..1fe935c --- /dev/null +++ b/Ubiquitous/XiZi/board/aiit-riscv64-board/third_party_driver/include/connect_lcd.h @@ -0,0 +1,52 @@ +/* Copyright 2018 Canaan Inc. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/** +* @file connect_lcd.h +* @brief define aiit-riscv64-board lcd function +* @version 1.0 +* @author AIIT XUOS Lab +* @date 2021-04-25 +*/ + +/************************************************* +File name: connect_lcd.h +Description: define aiit-riscv64-board lcd function +Others: https://canaan-creative.com/developer +History: +1. Date: 2021-04-25 +Author: AIIT XUOS Lab +Modification: +1. add aiit-riscv64-board lcd function +*************************************************/ + +#ifndef CONNECT_LCD_H +#define CONNECT_LCD_H + +#include +#include "hardware_spi.h" +#include + +#ifdef BSP_USING_TOUCH +#include "connect_touch.h" +#endif + +void DrvLcdClear(uint16_t color); +void LcdDrawLine(uint16 x1, uint16 y1, uint16 x2, uint16 y2,uint16 color); +void LcdDrawRectangle(uint16 x1, uint16 y1, uint16 x2, uint16 y2,uint16 color); +void LcdDrawCircle(uint16 x0,uint16 y0,uint8 r,uint16 color); + +int HwLcdInit(void); +#endif diff --git a/Ubiquitous/XiZi/board/aiit-riscv64-board/third_party_driver/include/connect_rtc.h b/Ubiquitous/XiZi/board/aiit-riscv64-board/third_party_driver/include/connect_rtc.h new file mode 100644 index 0000000..8d02d6e --- /dev/null +++ b/Ubiquitous/XiZi/board/aiit-riscv64-board/third_party_driver/include/connect_rtc.h @@ -0,0 +1,36 @@ +/* +* Copyright (c) 2020 AIIT XUOS Lab +* XiUOS is licensed under Mulan PSL v2. +* You can use this software according to the terms and conditions of the Mulan PSL v2. +* You may obtain a copy of Mulan PSL v2 at: +* http://license.coscl.org.cn/MulanPSL2 +* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, +* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, +* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. +* See the Mulan PSL v2 for more details. +*/ + +/** +* @file connect_rtc.h +* @brief define aiit-riscv64-board rtc function and struct +* @version 1.0 +* @author AIIT XUOS Lab +* @date 2021-04-25 +*/ + +#ifndef CONNECT_RTC_H +#define CONNECT_RTC_H + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +int HwRtcInit(void); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/Ubiquitous/XiZi/board/aiit-riscv64-board/third_party_driver/include/connect_spi.h b/Ubiquitous/XiZi/board/aiit-riscv64-board/third_party_driver/include/connect_spi.h new file mode 100644 index 0000000..cd746d0 --- /dev/null +++ b/Ubiquitous/XiZi/board/aiit-riscv64-board/third_party_driver/include/connect_spi.h @@ -0,0 +1,36 @@ +/* +* Copyright (c) 2020 AIIT XUOS Lab +* XiUOS is licensed under Mulan PSL v2. +* You can use this software according to the terms and conditions of the Mulan PSL v2. +* You may obtain a copy of Mulan PSL v2 at: +* http://license.coscl.org.cn/MulanPSL2 +* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, +* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, +* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. +* See the Mulan PSL v2 for more details. +*/ + +/** +* @file connect_spi.h +* @brief define aiit-riscv64-board spi function and struct +* @version 1.0 +* @author AIIT XUOS Lab +* @date 2021-04-25 +*/ + +#ifndef CONNECT_SPI_H +#define CONNECT_SPI_H + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +int HwSpiInit(void); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/Ubiquitous/XiZi/board/aiit-riscv64-board/third_party_driver/include/connect_spi_lora.h b/Ubiquitous/XiZi/board/aiit-riscv64-board/third_party_driver/include/connect_spi_lora.h new file mode 100644 index 0000000..1997577 --- /dev/null +++ b/Ubiquitous/XiZi/board/aiit-riscv64-board/third_party_driver/include/connect_spi_lora.h @@ -0,0 +1,63 @@ +/* +* Copyright (c) 2020 AIIT XUOS Lab +* XiUOS is licensed under Mulan PSL v2. +* You can use this software according to the terms and conditions of the Mulan PSL v2. +* You may obtain a copy of Mulan PSL v2 at: +* http://license.coscl.org.cn/MulanPSL2 +* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, +* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, +* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. +* See the Mulan PSL v2 for more details. +*/ + +/** +* @file connect_spi_lora.h +* @brief define spi lora dev function and struct using bus driver framework +* @version 1.0 +* @author AIIT XUOS Lab +* @date 2021-04-24 +*/ + +#ifndef CONNECT_SPI_LORA_H +#define CONNECT_SPI_LORA_H + +#include +#include +#include +#include +// #include +// #include +#include +#include +#include +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +#define SPI_LORA_FREQUENCY 10000000 +#define SPI_LORA_BUFFER_SIZE 256 + +typedef struct SpiLoraDevice *SpiLoraDeviceType; + +struct LoraDevDone +{ + uint32 (*open) (void *dev); + uint32 (*close) (void *dev); + uint32 (*write) (void *dev, struct BusBlockWriteParam *write_param); + uint32 (*read) (void *dev, struct BusBlockReadParam *read_param); +}; + +struct SpiLoraDevice +{ + struct SpiHardwareDevice *spi_dev; + struct SpiHardwareDevice lora_dev; +}; + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/Ubiquitous/XiZi/board/aiit-riscv64-board/third_party_driver/include/connect_touch.h b/Ubiquitous/XiZi/board/aiit-riscv64-board/third_party_driver/include/connect_touch.h new file mode 100644 index 0000000..fba1033 --- /dev/null +++ b/Ubiquitous/XiZi/board/aiit-riscv64-board/third_party_driver/include/connect_touch.h @@ -0,0 +1,66 @@ +/* +* Copyright (c) 2020 AIIT XUOS Lab +* XiUOS is licensed under Mulan PSL v2. +* You can use this software according to the terms and conditions of the Mulan PSL v2. +* You may obtain a copy of Mulan PSL v2 at: +* http://license.coscl.org.cn/MulanPSL2 +* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, +* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, +* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. +* See the Mulan PSL v2 for more details. +*/ + +/** +* @file connect_touch.h +* @brief define aiit-riscv64-board touch function and struct +* @version 1.0 +* @author AIIT XUOS Lab +* @date 2021-04-25 +*/ + +#ifndef CONNECT_TOUCH_H +#define CONNECT_TOUCH_H + +#include +#include "fpioa.h" +#include "gpio.h" +#include + +#define TP_CLK 0 +#define TP_CS 1 +#define TP_MISO 2 +#define TP_PEN 3 +#define TP_MOSI 4 + +#define TP_PRES_DOWN 0x80 +#define TP_CATH_PRES 0x40 + +//touch screen control struct +typedef struct +{ + unsigned short x; + unsigned short y; + unsigned char sta; + float xfac; + float yfac; + short xoff; + short yoff; + unsigned char touchtype; +}touch_device_info; + +extern touch_device_info tp_dev; + +//save data struct +typedef struct +{ + int ty_xfac; + int ty_yfac; + short x_pos; + short y_pos; + unsigned char iic_touchtype; + unsigned char iic_flag; +}TP_modify_save; + +int HwTouchBusInit(void); + +#endif diff --git a/Ubiquitous/XiZi/board/aiit-riscv64-board/third_party_driver/include/connect_uart.h b/Ubiquitous/XiZi/board/aiit-riscv64-board/third_party_driver/include/connect_uart.h new file mode 100644 index 0000000..7bbd251 --- /dev/null +++ b/Ubiquitous/XiZi/board/aiit-riscv64-board/third_party_driver/include/connect_uart.h @@ -0,0 +1,40 @@ +/* +* Copyright (c) 2020 AIIT XUOS Lab +* XiUOS is licensed under Mulan PSL v2. +* You can use this software according to the terms and conditions of the Mulan PSL v2. +* You may obtain a copy of Mulan PSL v2 at: +* http://license.coscl.org.cn/MulanPSL2 +* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, +* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, +* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. +* See the Mulan PSL v2 for more details. +*/ + +/** +* @file connect_uart.h +* @brief define aiit-riscv64-board uart function and struct +* @version 1.0 +* @author AIIT XUOS Lab +* @date 2021-04-25 +*/ + +#ifndef CONNECT_UART_H +#define CONNECT_UART_H + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +#define KERNEL_CONSOLE_BUS_NAME SERIAL_BUS_NAME_0 +#define KERNEL_CONSOLE_DRV_NAME SERIAL_DRV_NAME_0 +#define KERNEL_CONSOLE_DEVICE_NAME SERIAL_0_DEVICE_NAME_0 + +int HwUartInit(void); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/Ubiquitous/XiZi/board/aiit-riscv64-board/third_party_driver/include/connect_wdt.h b/Ubiquitous/XiZi/board/aiit-riscv64-board/third_party_driver/include/connect_wdt.h new file mode 100644 index 0000000..96cdb3e --- /dev/null +++ b/Ubiquitous/XiZi/board/aiit-riscv64-board/third_party_driver/include/connect_wdt.h @@ -0,0 +1,36 @@ +/* +* Copyright (c) 2020 AIIT XUOS Lab +* XiUOS is licensed under Mulan PSL v2. +* You can use this software according to the terms and conditions of the Mulan PSL v2. +* You may obtain a copy of Mulan PSL v2 at: +* http://license.coscl.org.cn/MulanPSL2 +* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, +* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, +* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. +* See the Mulan PSL v2 for more details. +*/ + +/** +* @file connect_wdt.h +* @brief define aiit-riscv64-board wdt function and struct +* @version 1.0 +* @author AIIT XUOS Lab +* @date 2021-04-25 +*/ + +#ifndef CONNECT_WDT_H +#define CONNECT_WDT_H + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +int HwWdtInit(void); + +#ifdef __cplusplus +} +#endif + +#endif \ No newline at end of file diff --git a/Ubiquitous/XiZi/board/aiit-riscv64-board/third_party_driver/lcd/Kconfig b/Ubiquitous/XiZi/board/aiit-riscv64-board/third_party_driver/lcd/Kconfig new file mode 100644 index 0000000..f058a8b --- /dev/null +++ b/Ubiquitous/XiZi/board/aiit-riscv64-board/third_party_driver/lcd/Kconfig @@ -0,0 +1,36 @@ + +if BSP_USING_LCD + config LCD_BUS_NAME + string "lcd bus name" + default "lcd" + config LCD_DRV_NAME + string "lcd bus driver name" + default "lcd_drv" + config LCD_DEVICE_NAME + string "lcd bus device name" + default "lcd_dev" + config BSP_LCD_CS_PIN + int "CS pin number of 8080 interface" + default 40 + config BSP_LCD_WR_PIN + int "WR pin number of 8080 interface" + default 38 + config BSP_LCD_DC_PIN + int "DC pin number of 8080 interface" + default 41 + config FPIOA_LCD_DC + int "DC FPIOA number of 8080 interface" + default 2 + config BSP_LCD_BL_PIN + int "BL pin number of 8080 interface" + default 47 + config FPIOA_LCD_BL + int "BL FPIOA number of 8080 interface" + default 10 + config BSP_LCD_X_MAX + int "LCD Height" + default 240 + config BSP_LCD_Y_MAX + int "LCD Width" + default 320 +endif diff --git a/Ubiquitous/XiZi/board/aiit-riscv64-board/third_party_driver/lcd/Makefile b/Ubiquitous/XiZi/board/aiit-riscv64-board/third_party_driver/lcd/Makefile new file mode 100644 index 0000000..05bd917 --- /dev/null +++ b/Ubiquitous/XiZi/board/aiit-riscv64-board/third_party_driver/lcd/Makefile @@ -0,0 +1,4 @@ +SRC_FILES := connect_lcd.c + + +include $(KERNEL_ROOT)/compiler.mk diff --git a/Ubiquitous/XiZi/board/aiit-riscv64-board/third_party_driver/plic/Kconfig b/Ubiquitous/XiZi/board/aiit-riscv64-board/third_party_driver/plic/Kconfig new file mode 100644 index 0000000..8b13789 --- /dev/null +++ b/Ubiquitous/XiZi/board/aiit-riscv64-board/third_party_driver/plic/Kconfig @@ -0,0 +1 @@ + diff --git a/Ubiquitous/XiZi/board/aiit-riscv64-board/third_party_driver/plic/Makefile b/Ubiquitous/XiZi/board/aiit-riscv64-board/third_party_driver/plic/Makefile new file mode 100644 index 0000000..b72b208 --- /dev/null +++ b/Ubiquitous/XiZi/board/aiit-riscv64-board/third_party_driver/plic/Makefile @@ -0,0 +1,5 @@ +SRC_FILES := drv_interrupt.c plic.c clint.c + + + +include $(KERNEL_ROOT)/compiler.mk diff --git a/Ubiquitous/XiZi/board/aiit-riscv64-board/third_party_driver/rtc/Kconfig b/Ubiquitous/XiZi/board/aiit-riscv64-board/third_party_driver/rtc/Kconfig new file mode 100644 index 0000000..e853dd4 --- /dev/null +++ b/Ubiquitous/XiZi/board/aiit-riscv64-board/third_party_driver/rtc/Kconfig @@ -0,0 +1,11 @@ +if BSP_USING_RTC + config RTC_BUS_NAME + string "rtc bus name" + default "rtc" + config RTC_DRV_NAME + string "rtc bus driver name" + default "rtc_drv" + config RTC_DEVICE_NAME + string "rtc bus device name" + default "rtc_dev" +endif diff --git a/Ubiquitous/XiZi/board/aiit-riscv64-board/third_party_driver/rtc/Makefile b/Ubiquitous/XiZi/board/aiit-riscv64-board/third_party_driver/rtc/Makefile new file mode 100644 index 0000000..23575e6 --- /dev/null +++ b/Ubiquitous/XiZi/board/aiit-riscv64-board/third_party_driver/rtc/Makefile @@ -0,0 +1,3 @@ +SRC_FILES := connect_rtc.c hardware_rtc.c + +include $(KERNEL_ROOT)/compiler.mk diff --git a/Ubiquitous/XiZi/board/aiit-riscv64-board/third_party_driver/rtc/connect_rtc.c b/Ubiquitous/XiZi/board/aiit-riscv64-board/third_party_driver/rtc/connect_rtc.c new file mode 100644 index 0000000..fc512b8 --- /dev/null +++ b/Ubiquitous/XiZi/board/aiit-riscv64-board/third_party_driver/rtc/connect_rtc.c @@ -0,0 +1,183 @@ +/* +* Copyright (c) 2020 AIIT XUOS Lab +* XiUOS is licensed under Mulan PSL v2. +* You can use this software according to the terms and conditions of the Mulan PSL v2. +* You may obtain a copy of Mulan PSL v2 at: +* http://license.coscl.org.cn/MulanPSL2 +* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, +* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, +* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. +* See the Mulan PSL v2 for more details. +*/ + +/** +* @file connect_rtc.c +* @brief support aiit-riscv64-board rtc function and register to bus framework +* @version 1.0 +* @author AIIT XUOS Lab +* @date 2021-04-25 +*/ + +#include +#include +#include +#include +#include +#include + +static int GetWeekDay(int year, int month, int day) +{ + /* Magic method to get weekday */ + int weekday = (day += month < 3 ? year-- : year - 2, + 23 * month / 9 + day + 4 + year / 4 - year / 100 + year / 400) % 7; + return weekday; +} + +static uint32 RtcConfigure(void *drv, struct BusConfigureInfo *configure_info) +{ + NULL_PARAM_CHECK(drv); + + struct RtcDriver *rtc_drv = (struct RtcDriver *)drv; + struct RtcDrvConfigureParam *drv_param = (struct RtcDrvConfigureParam *)configure_info->private_data; + + int cmd = drv_param->rtc_operation_cmd; + time_t *time = drv_param->time; + + switch (cmd) + { + case OPER_RTC_GET_TIME: + { + struct tm ct; + int year,month,day,hour,minute,second; + memset(&ct,0,sizeof(struct tm)); + + rtc_timer_get(&year, &month, &day, &hour, &minute, &second); + + ct.tm_year = year - 1900; + ct.tm_mon = month - 1; + ct.tm_mday = day; + ct.tm_wday = GetWeekDay(year, month, day); + + ct.tm_hour = hour; + ct.tm_min = minute; + ct.tm_sec = second; + + *time = mktime(&ct); + } + break; + case OPER_RTC_SET_TIME: + { + struct tm *ct; + struct tm tm_new; + x_base lock; + + lock = CriticalAreaLock(); + ct = localtime(time); + memcpy(&tm_new, ct, sizeof(struct tm)); + CriticalAreaUnLock(lock); + + sysctl_reset(SYSCTL_RESET_RTC); + sysctl_clock_enable(SYSCTL_CLOCK_RTC); + rtc_protect_set(0); + rtc_timer_set_clock_frequency(SysctlClockGetFreq(SYSCTL_CLOCK_IN0)); + rtc_timer_set_clock_count_value(1); + rtc_timer_set_mode(RTC_TIMER_RUNNING); + + if (rtc_timer_set(tm_new.tm_year+1900,tm_new.tm_mon+1,tm_new.tm_mday, + tm_new.tm_hour,tm_new.tm_min,tm_new.tm_sec)==-1) + return ERROR; + } + break; + } + return EOK; +} + +/*manage the rtc device operations*/ +static const struct RtcDevDone dev_done = +{ + .open = NONE, + .close = NONE, + .write = NONE, + .read = NONE, +}; + +static int BoardRtcBusInit(struct RtcBus *rtc_bus, struct RtcDriver *rtc_driver) +{ + x_err_t ret = EOK; + + /*Init the rtc bus */ + ret = RtcBusInit(rtc_bus, RTC_BUS_NAME); + if (EOK != ret) { + KPrintf("HwRtcInit RtcBusInit error %d\n", ret); + return ERROR; + } + + /*Init the rtc driver*/ + ret = RtcDriverInit(rtc_driver, RTC_DRV_NAME); + if (EOK != ret) { + KPrintf("HwRtcInit RtcDriverInit error %d\n", ret); + return ERROR; + } + + /*Attach the rtc driver to the rtc bus*/ + ret = RtcDriverAttachToBus(RTC_DRV_NAME, RTC_BUS_NAME); + if (EOK != ret) { + KPrintf("HwRtcInit RtcDriverAttachToBus error %d\n", ret); + return ERROR; + } + + return ret; +} + +/*Attach the rtc device to the rtc bus*/ +static int BoardRtcDevBend(void) +{ + x_err_t ret = EOK; + + static struct RtcHardwareDevice rtc_device; + memset(&rtc_device, 0, sizeof(struct RtcHardwareDevice)); + + rtc_device.dev_done = &(dev_done); + + ret = RtcDeviceRegister(&rtc_device, NONE, RTC_DEVICE_NAME); + if (EOK != ret) { + KPrintf("HwRtcInit RtcDeviceInit device %s error %d\n", RTC_DEVICE_NAME, ret); + return ERROR; + } + + ret = RtcDeviceAttachToBus(RTC_DEVICE_NAME, RTC_BUS_NAME); + if (EOK != ret) { + KPrintf("HwRtcInit RtcDeviceAttachToBus device %s error %d\n", RTC_DEVICE_NAME, ret); + return ERROR; + } + + return ret; +} + +int HwRtcInit(void) +{ + x_err_t ret = EOK; + + static struct RtcBus rtc_bus; + memset(&rtc_bus, 0, sizeof(struct RtcBus)); + + static struct RtcDriver rtc_driver; + memset(&rtc_driver, 0, sizeof(struct RtcDriver)); + + rtc_driver.configure = &(RtcConfigure); + + ret = BoardRtcBusInit(&rtc_bus, &rtc_driver); + if (EOK != ret) { + KPrintf("HwRtcInit error ret %u\n", ret); + return ERROR; + } + + ret = BoardRtcDevBend(); + if (EOK != ret) { + KPrintf("HwRtcInit error ret %u\n", ret); + } + + rtc_init(); + + return ret; +} diff --git a/Ubiquitous/XiZi/board/aiit-riscv64-board/third_party_driver/spi/Kconfig b/Ubiquitous/XiZi/board/aiit-riscv64-board/third_party_driver/spi/Kconfig new file mode 100644 index 0000000..de61c1e --- /dev/null +++ b/Ubiquitous/XiZi/board/aiit-riscv64-board/third_party_driver/spi/Kconfig @@ -0,0 +1,125 @@ +config BSP_USING_SPI1 +bool "Using spi1 " +default y + + +if BSP_USING_SPI1 + config SPI_BUS_NAME_1 + string "spi bus 1 name" + default "spi1" + config SPI_1_DRV_NAME + string "spi bus 1 driver name" + default "spi1_drv" + config BSP_SPI1_CLK_PIN + int "spi1 clk pin number" + default 6 + config BSP_SPI1_D0_PIN + int "spi1 d0 pin number" + default 8 + config BSP_SPI1_D1_PIN + int "spi1 d1 pin number" + default 7 + menuconfig BSP_SPI1_USING_SS0 + bool "SPI1 Enable SS0" + default y + if BSP_SPI1_USING_SS0 + config SPI_1_DEVICE_NAME_0 + string "spi bus 1 device 0 name" + default "spi1_dev0" + config BSP_SPI1_SS0_PIN + int "spi1 ss0 pin number" + default 9 + menuconfig RESOURCES_SPI_LORA + bool "Using spi lora function" + default n + if RESOURCES_SPI_LORA + config SX12XX_DEVICE_NAME + string "SX1278 lora device name" + default "spi1_lora" + config SX12XX_DEVICE_RST_PIN + int + default 10 + + config SX12XX_DEVICE_DO0_PIN + int + default 10 + + config SX12XX_DEVICE_DO1_PIN + int + default 10 + + config SX12XX_DEVICE_DO2_PIN + int + default 10 + + config SX12XX_DEVICE_DO3_PIN + int + default 10 + + config SX12XX_DEVICE_DO4_PIN + int + default 10 + + config SX12XX_DEVICE_DO5_PIN + int + default 10 + endif + endif + menuconfig BSP_SPI1_USING_SS1 + bool "SPI1 Enable SS1" + default y + if BSP_SPI1_USING_SS1 + config SPI_1_DEVICE_NAME_1 + string "spi bus 1 device 1 name" + default "spi1_dev1" + config BSP_SPI1_SS1_PIN + int "spi1 ss1 pin number" + default 33 + endif + menuconfig BSP_SPI1_USING_SS2 + bool "SPI1 Enable SS2" + default n + if BSP_SPI1_USING_SS2 + config SPI_1_DEVICE_NAME_2 + string "spi bus 1 device 2 name" + default "spi1_dev2" + config BSP_SPI1_SS2_PIN + int "spi1 ss2 pin number" + default 26 + endif + menuconfig BSP_SPI1_USING_SS3 + bool "SPI1 Enable SS3" + default n + if BSP_SPI1_USING_SS3 + config SPI_1_DEVICE_NAME_3 + string "spi bus 1 device 3 name" + default "spi1_dev3" + config BSP_SPI1_SS3_PIN + int "spi1 ss3 pin number" + default 27 + endif +endif + +config BSP_USING_TP +bool "Using LCD touch " +default n + +if BSP_USING_TP + config BSP_TP_SCK_PIN + int "TP SCK pin number" + default 42 + config BSP_TP_NCS_PIN + int "TP NCS pin number" + default 43 + config BSP_TP_MISO_PIN + int "TP MISO pin number" + default 44 + config BSP_TP_IRQ_PIN + int "TP IRQ pin number" + default 45 + config BSP_TP_MOSI_PIN + int "TP MOSI pin number" + default 46 + +endif + diff --git a/Ubiquitous/XiZi/board/aiit-riscv64-board/third_party_driver/spi/Makefile b/Ubiquitous/XiZi/board/aiit-riscv64-board/third_party_driver/spi/Makefile new file mode 100644 index 0000000..f64c853 --- /dev/null +++ b/Ubiquitous/XiZi/board/aiit-riscv64-board/third_party_driver/spi/Makefile @@ -0,0 +1,9 @@ +SRC_FILES := connect_spi.c hardware_spi.c + + +ifeq ($(CONFIG_RESOURCES_SPI_LORA),y) + SRC_DIR += third_party_spi_lora + SRC_FILES += connect_lora_spi.c +endif + +include $(KERNEL_ROOT)/compiler.mk diff --git a/Ubiquitous/XiZi/board/aiit-riscv64-board/third_party_driver/spi/connect_lora_spi.c b/Ubiquitous/XiZi/board/aiit-riscv64-board/third_party_driver/spi/connect_lora_spi.c new file mode 100644 index 0000000..12f7b35 --- /dev/null +++ b/Ubiquitous/XiZi/board/aiit-riscv64-board/third_party_driver/spi/connect_lora_spi.c @@ -0,0 +1,547 @@ +/* +* Copyright (c) 2020 AIIT XUOS Lab +* XiUOS is licensed under Mulan PSL v2. +* You can use this software according to the terms and conditions of the Mulan PSL v2. +* You may obtain a copy of Mulan PSL v2 at: +* http://license.coscl.org.cn/MulanPSL2 +* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, +* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, +* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. +* See the Mulan PSL v2 for more details. +*/ + +/** +* @file connect_lora_spi.c +* @brief support to register spi lora pointer and function +* @version 1.0 +* @author AIIT XUOS Lab +* @date 2021-05-17 +*/ + +#include + +static struct HardwareDev *g_spi_lora_dev; +static BusType buspin; +tRadioDriver *Radio = NONE; +void SX1276InitIo(void) +{ + struct PinParam PinCfg; + struct PinStat PinStat; + + struct BusConfigureInfo configure_info; + struct BusBlockWriteParam write_param; + + write_param.buffer = (void *)&PinStat; + configure_info.configure_cmd = OPE_CFG; + configure_info.private_data = (void *)&PinCfg; + + buspin = PinBusInitGet(); + + PinCfg.cmd = GPIO_CONFIG_MODE; + PinCfg.pin = SX12XX_DEVICE_DO0_PIN; + PinCfg.mode = GPIO_CFG_INPUT; + BusDrvConfigure(buspin->owner_driver, &configure_info); + + PinCfg.cmd = GPIO_CONFIG_MODE; + PinCfg.pin = SX12XX_DEVICE_DO1_PIN; + PinCfg.mode = GPIO_CFG_INPUT; + BusDrvConfigure(buspin->owner_driver, &configure_info); + + PinCfg.cmd = GPIO_CONFIG_MODE; + PinCfg.pin = SX12XX_DEVICE_DO2_PIN; + PinCfg.mode = GPIO_CFG_INPUT; + BusDrvConfigure(buspin->owner_driver, &configure_info); +} + +inline uint8_t SX1276ReadDio0(void) +{ + struct PinStat PinStat; + + struct BusBlockReadParam read_param; + read_param.buffer = (void *)&PinStat; + + PinStat.pin = SX12XX_DEVICE_DO0_PIN; + + return BusDevReadData(buspin->owner_haldev, &read_param); +} + +inline uint8_t SX1276ReadDio1(void) +{ + struct PinStat PinStat; + + struct BusBlockReadParam read_param; + read_param.buffer = (void *)&PinStat; + + PinStat.pin = SX12XX_DEVICE_DO1_PIN; + + return BusDevReadData(buspin->owner_haldev, &read_param); +} + +inline uint8_t SX1276ReadDio2(void) +{ + struct PinStat PinStat; + + struct BusBlockReadParam read_param; + read_param.buffer = (void *)&PinStat; + + PinStat.pin = SX12XX_DEVICE_DO2_PIN; + + return BusDevReadData(buspin->owner_haldev, &read_param); +} + +inline uint8_t SX1276ReadDio3(void) +{ + struct PinStat PinStat; + + struct BusBlockReadParam read_param; + read_param.buffer = (void *)&PinStat; + + PinStat.pin = SX12XX_DEVICE_DO3_PIN; + + return BusDevReadData(buspin->owner_haldev, &read_param); +} + +inline uint8_t SX1276ReadDio4(void) +{ + struct PinStat PinStat; + + struct BusBlockReadParam read_param; + read_param.buffer = (void *)&PinStat; + + PinStat.pin = SX12XX_DEVICE_DO4_PIN; + + return BusDevReadData(buspin->owner_haldev, &read_param); +} + +inline uint8_t SX1276ReadDio5(void) +{ + struct PinStat PinStat; + + struct BusBlockReadParam read_param; + read_param.buffer = (void *)&PinStat; + + PinStat.pin = SX12XX_DEVICE_DO5_PIN; + + return BusDevReadData(buspin->owner_haldev, &read_param); +} + +inline void SX1276WriteRxTx(uint8_t txEnable) +{ + return; +} + +void SX1276SetReset(uint8_t state) +{ + struct PinParam PinCfg; + struct PinStat PinStat; + + struct BusConfigureInfo configure_info; + struct BusBlockWriteParam write_param; + + configure_info.configure_cmd = OPE_CFG; + configure_info.private_data = (void *)&PinCfg; + write_param.buffer = (void *)&PinStat; + + if (state == RADIO_RESET_ON) + { + PinCfg.cmd = GPIO_CONFIG_MODE; + PinCfg.pin = SX12XX_DEVICE_RST_PIN; + PinCfg.mode = GPIO_CFG_OUTPUT; + BusDrvConfigure(buspin->owner_driver, &configure_info); + + PinStat.val = GPIO_LOW; + PinStat.pin = SX12XX_DEVICE_RST_PIN; + BusDevWriteData(buspin->owner_haldev, &write_param); + } + else + { + PinCfg.cmd = GPIO_CONFIG_MODE; + PinCfg.pin = SX12XX_DEVICE_RST_PIN; + PinCfg.mode = GPIO_CFG_INPUT; + BusDrvConfigure(buspin->owner_driver, &configure_info); + } +} + +void SX1276Write(uint8_t addr, uint8_t data) +{ + SX1276WriteBuffer(addr, &data, 1); +} + +void SX1276Read(uint8_t addr, uint8_t *data) +{ + SX1276ReadBuffer(addr, data, 1); +} + +void SX1276WriteBuffer(uint8_t addr, uint8_t *buffer, uint8_t size) +{ + struct BusBlockWriteParam write_param; + uint8 write_addr = addr | 0x80; + + BusDevOpen(g_spi_lora_dev); + + write_param.buffer = (void *)&write_addr; + write_param.size = 1; + BusDevWriteData(g_spi_lora_dev, &write_param); + + write_param.buffer = (void *)buffer; + write_param.size = size; + BusDevWriteData(g_spi_lora_dev, &write_param); + + BusDevClose(g_spi_lora_dev); +} + +void SX1276ReadBuffer(uint8_t addr, uint8_t *buffer, uint8_t size) +{ + struct BusBlockWriteParam write_param; + struct BusBlockReadParam read_param; + + uint8 write_addr = addr & 0x7F; + + BusDevOpen(g_spi_lora_dev); + + write_param.buffer = (void *)&write_addr; + write_param.size = 1; + BusDevWriteData(g_spi_lora_dev, &write_param); + + read_param.buffer = (void *)buffer; + read_param.size = size; + BusDevReadData(g_spi_lora_dev, &read_param); + + BusDevClose(g_spi_lora_dev); +} + +void SX1276WriteFifo(uint8_t *buffer, uint8_t size) +{ + SX1276WriteBuffer(0, buffer, size); +} + +void SX1276ReadFifo(uint8_t *buffer, uint8_t size) +{ + SX1276ReadBuffer(0, buffer, size); +} + +uint8_t SX1276_Spi_Check() +{ + uint8_t test = 0; + KPrintf("SX1276_Spi_Check start\n"); + tLoRaSettings settings; + SX1276Read(REG_LR_VERSION,&test); + KPrintf("version code of the chip is %x\n",test); + settings.RFFrequency = SX1276LoRaGetRFFrequency(); + KPrintf("SX1278 Lora parameters are :\nRFFrequency is %d\n",settings.RFFrequency); + settings.Power = SX1276LoRaGetRFPower(); + KPrintf("RFPower is %d\n",settings.Power); + settings.SignalBw = SX1276LoRaGetSignalBandwidth(); + KPrintf("SignalBw is %d\n",settings.SignalBw); + settings.SpreadingFactor = SX1276LoRaGetSpreadingFactor(); + KPrintf("SpreadingFactor is %d\n",settings.SpreadingFactor); + /*SPI confirm*/ + SX1276Write(REG_LR_HOPPERIOD, 0x91); + SX1276Read(REG_LR_HOPPERIOD, &test); + if (test != 0x91) { + return 0; + } + return test; +} + +/** + * This function supports to write data to the lora. + * + * @param dev lora dev descriptor + * @param write_param lora dev write datacfg param + */ +static uint32 SpiLoraWrite(void *dev, struct BusBlockWriteParam *write_param) +{ + NULL_PARAM_CHECK(dev); + NULL_PARAM_CHECK(write_param); + + if (write_param->size > 256) { + KPrintf("SpiLoraWrite ERROR:The message is too long!\n"); + return ERROR; + } else { + //Radio->SetTxPacket(write_param->buffer, write_param->size); + //while(Radio->Process() != RF_TX_DONE); + SX1276SetTxPacket(write_param->buffer, write_param->size); + while(SX1276Process() != RF_TX_DONE); + KPrintf("SpiLoraWrite success!\n"); + } + + return EOK; +} + +/** + * This function supports to read data from the lora. + * + * @param dev lora dev descriptor + * @param read_param lora dev read datacfg param + */ +static uint32 SpiLoraRead(void *dev, struct BusBlockReadParam *read_param) +{ + NULL_PARAM_CHECK(dev); + NULL_PARAM_CHECK(read_param); + + int read_times = 1000; + + //Radio->StartRx(); + SX1276StartRx(); + KPrintf("SpiLoraRead Ready!\n"); + + while (read_times) { + if (SX1276Process() != RF_RX_DONE) { + read_times --; + MdelayKTask(500); + } else { + break; + } + } + + if (read_times > 0) { + SX1276GetRxPacket(read_param->buffer, (uint16 *)&read_param->read_length); + } else { + read_param->read_length = 0; + } + + //while(Radio->Process() != RF_RX_DONE); + //Radio->GetRxPacket(read_param->buffer, (uint16 *)&read_param->read_length); + // while(SX1276Process() != RF_RX_DONE); + // SX1276GetRxPacket(read_param->buffer, (uint16 *)&read_param->read_length); + + return read_param->read_length; +} + +static uint32 SpiLoraOpen(void *dev) +{ + NULL_PARAM_CHECK(dev); + + KPrintf("SpiLoraOpen start\n"); + + x_err_t ret = EOK; + static x_bool lora_init_status = RET_FALSE; + + if (RET_TRUE == lora_init_status) { + return EOK; + } + + struct HardwareDev *haldev = (struct HardwareDev *)dev; + + struct SpiHardwareDevice *lora_dev = CONTAINER_OF(haldev, struct SpiHardwareDevice, haldev); + NULL_PARAM_CHECK(lora_dev); + + SpiLoraDeviceType spi_lora_dev = CONTAINER_OF(lora_dev, struct SpiLoraDevice, lora_dev); + NULL_PARAM_CHECK(spi_lora_dev); + + struct Driver *spi_drv = spi_lora_dev->spi_dev->haldev.owner_bus->owner_driver; + + struct BusConfigureInfo configure_info; + struct SpiMasterParam spi_master_param; + spi_master_param.spi_data_bit_width = 8; + spi_master_param.spi_work_mode = SPI_MODE_0 | SPI_MSB; + spi_master_param.spi_maxfrequency = SPI_LORA_FREQUENCY; + spi_master_param.spi_data_endian = 0; + + configure_info.configure_cmd = OPE_CFG; + configure_info.private_data = (void *)&spi_master_param; + ret = BusDrvConfigure(spi_drv, &configure_info); + if (ret) { + KPrintf("spi drv OPE_CFG error drv %8p cfg %8p\n", spi_drv, &spi_master_param); + return ERROR; + } + + configure_info.configure_cmd = OPE_INT; + ret = BusDrvConfigure(spi_drv, &configure_info); + if (ret) { + KPrintf("spi drv OPE_INT error drv %8p\n", spi_drv); + return ERROR; + } + + SX1276Init(); + + if (0x91 != SX1276_Spi_Check()) { + KPrintf("LoRa check failed!\n!"); + } else { + Radio = RadioDriverInit(); + KPrintf("LoRa check ok!\nNote: The length of the message that can be sent in a single time is 256 characters\n"); + } + + lora_init_status = RET_TRUE; + + return ret; +} + +static uint32 SpiLoraClose(void *dev) +{ + NULL_PARAM_CHECK(dev); + + return EOK; +} + +static const struct LoraDevDone lora_done = +{ + .open = SpiLoraOpen, + .close = SpiLoraClose, + .write = SpiLoraWrite, + .read = SpiLoraRead, +}; + +/** + * This function supports to init spi_lora_dev + * + * @param bus_name spi bus name + * @param dev_name spi dev name + * @param drv_name spi drv name + * @param flash_name flash dev name + */ +SpiLoraDeviceType SpiLoraInit(char *bus_name, char *dev_name, char *drv_name, char *lora_name) +{ + NULL_PARAM_CHECK(dev_name); + NULL_PARAM_CHECK(drv_name); + NULL_PARAM_CHECK(lora_name); + NULL_PARAM_CHECK(bus_name); + + x_err_t ret; + static HardwareDevType haldev; + + haldev = SpiDeviceFind(dev_name, TYPE_SPI_DEV); + if (NONE == haldev) { + KPrintf("SpiLoraInit find spi haldev %s error! \n", dev_name); + return NONE; + } + + SpiLoraDeviceType spi_lora_dev = (SpiLoraDeviceType)malloc(sizeof(struct SpiLoraDevice)); + if (NONE == spi_lora_dev) { + KPrintf("SpiLoraInit malloc spi_lora_dev failed\n"); + free(spi_lora_dev); + return NONE; + } + + memset(spi_lora_dev, 0, sizeof(struct SpiLoraDevice)); + + spi_lora_dev->spi_dev = CONTAINER_OF(haldev, struct SpiHardwareDevice, haldev); + + spi_lora_dev->lora_dev.spi_dev_flag = RET_TRUE; + spi_lora_dev->lora_dev.haldev.dev_done = (struct HalDevDone *)&lora_done; + + spi_lora_dev->spi_dev->haldev.owner_bus->owner_driver = SpiDriverFind(drv_name, TYPE_SPI_DRV); + if (NONE == spi_lora_dev->spi_dev->haldev.owner_bus->owner_driver) { + KPrintf("SpiLoraInit find spi driver %s error! \n", drv_name); + free(spi_lora_dev); + return NONE; + } + + ret = SpiDeviceRegister(&spi_lora_dev->lora_dev, spi_lora_dev->spi_dev->haldev.private_data, lora_name); + if (EOK != ret) { + KPrintf("SpiLoraInit SpiDeviceRegister device %s error %d\n", lora_name, ret); + free(spi_lora_dev); + return NONE; + } + + ret = SpiDeviceAttachToBus(lora_name, bus_name); + if (EOK != ret) { + KPrintf("SpiLoraInit SpiDeviceAttachToBus device %s error %d\n", lora_name, ret); + free(spi_lora_dev); + return NONE; + } + + g_spi_lora_dev = &spi_lora_dev->spi_dev->haldev; + + return spi_lora_dev; +} + +/** + * This function supports to release spi_lora_dev + * + * @param spi_lora_dev spi lora descriptor + */ +uint32 SpiLoraRelease(SpiLoraDeviceType spi_lora_dev) +{ + NULL_PARAM_CHECK(spi_lora_dev); + + x_err_t ret; + + DeviceDeleteFromBus(spi_lora_dev->lora_dev.haldev.owner_bus, &spi_lora_dev->lora_dev.haldev); + + free(spi_lora_dev); + + return EOK; +} + +int LoraSx12xxSpiDeviceInit(void) +{ +#ifdef BSP_USING_SPI1 + + if (NONE == SpiLoraInit(SPI_BUS_NAME_1, SPI_1_DEVICE_NAME_0, SPI_1_DRV_NAME, SX12XX_DEVICE_NAME)) { + return ERROR; + } + +#endif + + return EOK; +} + +//#define LORA_TEST +#ifdef LORA_TEST +/*Just for lora test*/ +static struct Bus *bus; +static struct HardwareDev *dev; +static struct Driver *drv; + +void LoraOpen(void) +{ + x_err_t ret = EOK; + + ret = LoraSx12xxSpiDeviceInit(); + if (EOK != ret) { + KPrintf("LoraSx12xxSpiDeviceInit failed\n"); + return; + } + + bus = BusFind(SPI_BUS_NAME_1); + dev = BusFindDevice(bus, SX12XX_DEVICE_NAME); + drv = BusFindDriver(bus, SPI_1_DRV_NAME); + + bus->match(drv, dev); + + ret = SpiLoraOpen(dev); + if (EOK != ret) { + KPrintf("LoRa init failed\n"); + return; + } + + KPrintf("LoRa init succeed\n"); + + return; +} +SHELL_EXPORT_CMD(SHELL_CMD_PERMISSION(0)|SHELL_CMD_TYPE(SHELL_TYPE_CMD_MAIN), + LoraOpen, LoraOpen, open lora device and read parameters ); + +static void LoraReceive(void) +{ + struct BusBlockReadParam read_param; + memset(&read_param, 0, sizeof(struct BusBlockReadParam)); + + read_param.buffer = malloc(SPI_LORA_BUFFER_SIZE); + + SpiLoraRead(dev, &read_param); + + free(read_param.buffer); +} +SHELL_EXPORT_CMD(SHELL_CMD_PERMISSION(0)|SHELL_CMD_TYPE(SHELL_TYPE_CMD_FUNC)|SHELL_CMD_PARAM_NUM(0), +LoraReceive, LoraReceive, lora wait message ); + +static void LoraSend(int argc, char *argv[]) +{ + char Msg[SPI_LORA_BUFFER_SIZE] = {0}; + struct BusBlockWriteParam write_param; + memset(&write_param, 0, sizeof(struct BusBlockWriteParam)); + + if (argc == 2) { + strncpy(Msg, argv[1], SPI_LORA_BUFFER_SIZE); + write_param.buffer = Msg; + write_param.size = strlen(Msg); + + SpiLoraWrite(dev, &write_param); + } +} +SHELL_EXPORT_CMD(SHELL_CMD_PERMISSION(0)|SHELL_CMD_TYPE(SHELL_TYPE_CMD_MAIN), +LoraSend, LoraSend, lora send message ); +#endif diff --git a/Ubiquitous/XiZi/board/aiit-riscv64-board/third_party_driver/sys_clock/Kconfig b/Ubiquitous/XiZi/board/aiit-riscv64-board/third_party_driver/sys_clock/Kconfig new file mode 100644 index 0000000..8b13789 --- /dev/null +++ b/Ubiquitous/XiZi/board/aiit-riscv64-board/third_party_driver/sys_clock/Kconfig @@ -0,0 +1 @@ + diff --git a/Ubiquitous/XiZi/board/aiit-riscv64-board/third_party_driver/sys_clock/Makefile b/Ubiquitous/XiZi/board/aiit-riscv64-board/third_party_driver/sys_clock/Makefile new file mode 100644 index 0000000..ef5fda1 --- /dev/null +++ b/Ubiquitous/XiZi/board/aiit-riscv64-board/third_party_driver/sys_clock/Makefile @@ -0,0 +1,6 @@ +SRC_FILES := sysctl.c + + + + +include $(KERNEL_ROOT)/compiler.mk diff --git a/Ubiquitous/XiZi/board/aiit-riscv64-board/third_party_driver/timer/Kconfig b/Ubiquitous/XiZi/board/aiit-riscv64-board/third_party_driver/timer/Kconfig new file mode 100644 index 0000000..fdc67b1 --- /dev/null +++ b/Ubiquitous/XiZi/board/aiit-riscv64-board/third_party_driver/timer/Kconfig @@ -0,0 +1,19 @@ +if BSP_USING_HWTIMER + config HWTIMER_BUS_NAME_1 + string "hwtimer bus name" + default "hwtim1" + + menuconfig ENABLE_TIM1 + bool "enable TIM1" + default y + + if ENABLE_TIM1 + config HWTIMER_1_DEVICE_NAME_1 + string "TIM1 dev name" + default "hwtim1_dev1" + + config HWTIMER_DRIVER_NAME_1 + string "TIM1 drv name" + default "hwtim1_drv" + endif +endif diff --git a/Ubiquitous/XiZi/board/aiit-riscv64-board/third_party_driver/timer/Makefile b/Ubiquitous/XiZi/board/aiit-riscv64-board/third_party_driver/timer/Makefile new file mode 100644 index 0000000..24d4ccf --- /dev/null +++ b/Ubiquitous/XiZi/board/aiit-riscv64-board/third_party_driver/timer/Makefile @@ -0,0 +1,5 @@ +SRC_FILES := hardware_hwtimer.c connect_hwtimer.c + + + +include $(KERNEL_ROOT)/compiler.mk diff --git a/Ubiquitous/XiZi/board/aiit-riscv64-board/third_party_driver/timer/connect_hwtimer.c b/Ubiquitous/XiZi/board/aiit-riscv64-board/third_party_driver/timer/connect_hwtimer.c new file mode 100644 index 0000000..7a7d23c --- /dev/null +++ b/Ubiquitous/XiZi/board/aiit-riscv64-board/third_party_driver/timer/connect_hwtimer.c @@ -0,0 +1,153 @@ +/* +* Copyright (c) 2020 AIIT XUOS Lab +* XiUOS is licensed under Mulan PSL v2. +* You can use this software according to the terms and conditions of the Mulan PSL v2. +* You may obtain a copy of Mulan PSL v2 at: +* http://license.coscl.org.cn/MulanPSL2 +* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, +* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, +* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. +* See the Mulan PSL v2 for more details. +*/ + +/** +* @file connect_hwtimer.c +* @brief support aiit-riscv64-board hwtimer function and register to bus framework +* @version 1.0 +* @author AIIT XUOS Lab +* @date 2021-04-25 +*/ + +#include +#include +#include +#include +#include +#include +#include + +static struct HwtimerCallBackInfo *ptim2_cb_info = NULL; + +int timer_callback(void *ctx) +{ + if (ptim2_cb_info) { + if (ptim2_cb_info->timeout_callback) { + ptim2_cb_info->timeout_callback(ptim2_cb_info->param); + } + } + return 0; +} + +uint32 HwtimerOpen(void *dev) +{ + struct HwtimerHardwareDevice *hwtimer_dev = dev; + + ptim2_cb_info = &hwtimer_dev->hwtimer_param.cb_info; + + plic_init(); + sysctl_enable_irq(); + timer_init(TIMER_DEVICE_1); + + size_t real_time = timer_set_interval(TIMER_DEVICE_1, TIMER_CHANNEL_1, hwtimer_dev->hwtimer_param.period_millisecond *1000); + KPrintf("timer_set_interval -- real_time : %ld\n", real_time); + timer_irq_register(TIMER_DEVICE_1, TIMER_CHANNEL_1, !hwtimer_dev->hwtimer_param.repeat, 1, timer_callback, NULL); + + timer_set_enable(TIMER_DEVICE_1, TIMER_CHANNEL_1, 1); + + return EOK; +} + +uint32 HwtimerClose(void *dev) +{ + timer_set_enable(TIMER_DEVICE_1, TIMER_CHANNEL_1, 0); + + return EOK; +} + +/*manage the hwtimer device operations*/ +static const struct HwtimerDevDone dev_done = +{ + .open = HwtimerOpen, + .close = HwtimerClose, + .write = NONE, + .read = NONE, +}; + +/*Init hwtimer bus*/ +static int BoardHwtimerBusInit(struct HwtimerBus *hwtimer_bus, struct HwtimerDriver *hwtimer_driver) +{ + x_err_t ret = EOK; + + /*Init the hwtimer bus */ + ret = HwtimerBusInit(hwtimer_bus, HWTIMER_BUS_NAME_1); + if (EOK != ret) { + KPrintf("board_hwtimer_init HwtimerBusInit error %d\n", ret); + return ERROR; + } + + /*Init the hwtimer driver*/ + hwtimer_driver->configure = NONE; + ret = HwtimerDriverInit(hwtimer_driver, HWTIMER_DRIVER_NAME_1); + if (EOK != ret) { + KPrintf("board_hwtimer_init HwtimerDriverInit error %d\n", ret); + return ERROR; + } + + /*Attach the hwtimer driver to the hwtimer bus*/ + ret = HwtimerDriverAttachToBus(HWTIMER_DRIVER_NAME_1, HWTIMER_BUS_NAME_1); + if (EOK != ret) { + KPrintf("board_hwtimer_init USEDriverAttachToBus error %d\n", ret); + return ERROR; + } + + return ret; +} + +/*Attach the hwtimer device to the hwtimer bus*/ +static int BoardHwtimerDevBend(void) +{ + x_err_t ret = EOK; + static struct HwtimerHardwareDevice hwtimer_device_0; + memset(&hwtimer_device_0, 0, sizeof(struct HwtimerHardwareDevice)); + + hwtimer_device_0.dev_done = &dev_done; + + ret = HwtimerDeviceRegister(&hwtimer_device_0, NONE, HWTIMER_1_DEVICE_NAME_1); + if (EOK != ret) { + KPrintf("BoardHwtimerDevBend HwtimerDeviceRegister device %s error %d\n", HWTIMER_1_DEVICE_NAME_1, ret); + return ERROR; + } + + ret = HwtimerDeviceAttachToBus(HWTIMER_1_DEVICE_NAME_1, HWTIMER_BUS_NAME_1); + if (EOK != ret) { + KPrintf("BoardHwtimerDevBend HwtimerDeviceAttachToBus device %s error %d\n", HWTIMER_1_DEVICE_NAME_1, ret); + return ERROR; + } + + return ret; +} + +/*K210 BOARD HWTIMER INIT*/ +int HwTimerInit(void) +{ + x_err_t ret = EOK; + static struct HwtimerBus hwtimer_bus; + memset(&hwtimer_bus, 0, sizeof(struct HwtimerBus)); + + static struct HwtimerDriver hwtimer_driver; + memset(&hwtimer_driver, 0, sizeof(struct HwtimerDriver)); + + ret = BoardHwtimerBusInit(&hwtimer_bus, &hwtimer_driver); + if (EOK != ret) { + KPrintf("board_hwtimer_Init error ret %u\n", ret); + return ERROR; + } + + ret = BoardHwtimerDevBend(); + if (EOK != ret) { + KPrintf("board_hwtimer_Init error ret %u\n", ret); + return ERROR; + } + + return ret; +} diff --git a/Ubiquitous/XiZi/board/aiit-riscv64-board/third_party_driver/touch/Kconfig b/Ubiquitous/XiZi/board/aiit-riscv64-board/third_party_driver/touch/Kconfig new file mode 100644 index 0000000..8e5193d --- /dev/null +++ b/Ubiquitous/XiZi/board/aiit-riscv64-board/third_party_driver/touch/Kconfig @@ -0,0 +1,9 @@ +config TOUCH_BUS_NAME_1 + string "touch bus 1 name" + default "touch1" +config TOUCH_DRV_NAME_1 + string "touch bus 1 driver name" + default "touch1drv" +config TOUCH_1_DEVICE_NAME_0 + string "touch bus 1 device 0 name" + default "touch10" \ No newline at end of file diff --git a/Ubiquitous/XiZi/board/aiit-riscv64-board/third_party_driver/touch/Makefile b/Ubiquitous/XiZi/board/aiit-riscv64-board/third_party_driver/touch/Makefile new file mode 100644 index 0000000..f32904a --- /dev/null +++ b/Ubiquitous/XiZi/board/aiit-riscv64-board/third_party_driver/touch/Makefile @@ -0,0 +1,6 @@ +SRC_FILES := connect_touch.c + + + + +include $(KERNEL_ROOT)/compiler.mk \ No newline at end of file diff --git a/Ubiquitous/XiZi/board/aiit-riscv64-board/third_party_driver/touch/connect_touch.c b/Ubiquitous/XiZi/board/aiit-riscv64-board/third_party_driver/touch/connect_touch.c new file mode 100644 index 0000000..516ee41 --- /dev/null +++ b/Ubiquitous/XiZi/board/aiit-riscv64-board/third_party_driver/touch/connect_touch.c @@ -0,0 +1,290 @@ +/* +* Copyright (c) 2020 AIIT XUOS Lab +* XiUOS is licensed under Mulan PSL v2. +* You can use this software according to the terms and conditions of the Mulan PSL v2. +* You may obtain a copy of Mulan PSL v2 at: +* http://license.coscl.org.cn/MulanPSL2 +* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, +* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, +* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. +* See the Mulan PSL v2 for more details. +*/ + +/** +* @file connect_touch.c +* @brief support aiit-riscv64-board touch function and register to bus framework +* @version 1.0 +* @author AIIT XUOS Lab +* @date 2021-04-25 +*/ + +#include + +touch_device_info tp_dev = +{ + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, +}; + +unsigned char CMD_RDX = 0XD0; +unsigned char CMD_RDY = 0X90; + +TP_modify_save modify_save = +{ + 0,0,0,0,0,0 +}; + +void TouchWriteByte(unsigned char num) +{ + unsigned char count=0; + for (count=0;count<8;count++) { + if (num&0x80) { + gpio_set_pin(TP_MOSI, GPIO_PV_HIGH); + } else { + gpio_set_pin(TP_MOSI, GPIO_PV_LOW); + } + num<<=1; + gpio_set_pin(TP_CLK, GPIO_PV_LOW); + usleep(1); + gpio_set_pin(TP_CLK, GPIO_PV_HIGH); + } +} + +unsigned short TpReadAd(unsigned char CMD) +{ + unsigned char count=0; + unsigned short Num=0; + + gpio_set_pin(TP_CLK, GPIO_PV_LOW); + gpio_set_pin(TP_MOSI, GPIO_PV_LOW); + gpio_set_pin(TP_CS, GPIO_PV_LOW); + + TouchWriteByte(CMD); + usleep(6); + gpio_set_pin(TP_CLK, GPIO_PV_LOW); + usleep(1); + gpio_set_pin(TP_CLK, GPIO_PV_HIGH); + usleep(1); + gpio_set_pin(TP_CLK, GPIO_PV_LOW); + for (count = 0;count < 16;count++) { + Num<<=1; + gpio_set_pin(TP_CLK, GPIO_PV_LOW); + usleep(1); + gpio_set_pin(TP_CLK, GPIO_PV_HIGH); + if(gpio_get_pin(TP_MISO)) + Num++; + } + Num>>=4; + gpio_set_pin(TP_CS, GPIO_PV_HIGH); + return(Num); +} + +#define READ_TIMES 5 +#define LOST_VAL 1 + +unsigned short TpReadXoy(unsigned char xy) +{ + unsigned short i, j; + unsigned short buf[READ_TIMES]; + unsigned short sum=0; + unsigned short temp; + for (i=0;ibuf[j]) { + temp=buf[i]; + buf[i]=buf[j]; + buf[j]=temp; + } + } + } + sum=0; + for(i=LOST_VAL;ibuffer; + TpReadXy(&data->x,&data->y); + return ret; +} + +/* +* read the twice +* return 0 is error 1 :ok +*/ +#define band_error 66 +unsigned char TP_Read_XY_TWICE(unsigned short *x, unsigned short *y) +{ + unsigned short fir_x, fir_y, sec_x, sec_y; + unsigned char flag; + flag = TpReadXy(&fir_x, &fir_y); + if (flag == 0) + return(0); + flag = TpReadXy(&sec_x, &sec_y); + if (flag == 0) + return(0); + if (((sec_x <= fir_x && fir_x < sec_x + band_error) || (fir_x <= sec_x && sec_x < fir_x + band_error)) + && ((sec_y <= fir_y && fir_y < sec_y + band_error) || (fir_y <= sec_y && sec_y < fir_y + band_error))) { + *x = (fir_x + sec_x) / 2; + *y = (fir_y + sec_y) / 2; + return 1; + } else + return 0; +} + +uint32 TouchConfigure(void *drv, struct BusConfigureInfo *configure_info) +{ + FpioaSetFunction(42, FUNC_GPIO0); + FpioaSetFunction(43, FUNC_GPIO1); + FpioaSetFunction(44, FUNC_GPIO2); + FpioaSetFunction(45, FUNC_GPIO3); + FpioaSetFunction(46, FUNC_GPIO4); + + gpio_init(); + gpio_set_drive_mode(TP_CLK, GPIO_DM_OUTPUT); + gpio_set_drive_mode(TP_CS , GPIO_DM_OUTPUT); + gpio_set_drive_mode(TP_MISO, GPIO_DM_INPUT); + gpio_set_drive_mode(TP_PEN, GPIO_DM_INPUT); + gpio_set_drive_mode(TP_MOSI, GPIO_DM_OUTPUT); + + return 0; +} + +struct TouchDevDone touch_dev_done = +{ + .open = NONE, + .close = NONE, + .write = NONE, + .read = TouchRead +}; + +void TP_Init(void) +{ + TouchConfigure(NONE,NONE); + while (1) { + TpReadXy(&tp_dev.x, &tp_dev.y); + KPrintf("tp_dev.x = %8d *** tp_dev.y= %8d \r\n", tp_dev.x, tp_dev.y); + MdelayKTask(100); + } +} + +unsigned short my_abs(unsigned short x1, unsigned short x2) +{ + if(x1>x2) + return x1-x2; + else + return x2-x1; +} + +struct RiscTouch +{ + char *BusName; + struct TouchBus touch_bus; +}; + +struct RiscTouch touch; + +static int BoardTouchBusInit(struct RiscTouch *risc_touch_bus, struct TouchDriver *touch_driver) +{ + x_err_t ret = EOK; + + /*Init the touch bus */ + ret = TouchBusInit(&risc_touch_bus->touch_bus, risc_touch_bus->BusName); + if (EOK != ret) { + KPrintf("Board_touch_init touchBusInit error %d\n", ret); + return ERROR; + } + + /*Init the touch driver*/ + ret = TouchDriverInit(touch_driver, TOUCH_DRV_NAME_1); + if (EOK != ret) { + KPrintf("Board_touch_init touchDriverInit error %d\n", ret); + return ERROR; + } + + /*Attach the touch driver to the touch bus*/ + ret = TouchDriverAttachToBus(TOUCH_DRV_NAME_1, risc_touch_bus->BusName); + if (EOK != ret) { + KPrintf("Board_touch_init TouchDriverAttachToBus error %d\n", ret); + return ERROR; + } + + return ret; +} + +/*Attach the touch device to the touch bus*/ +static int BoardTouchDevBend(void) +{ + x_err_t ret = EOK; + static struct TouchHardwareDevice touch_device; + memset(&touch_device, 0, sizeof(struct TouchHardwareDevice)); + + touch_device.dev_done = &touch_dev_done; + + ret = TouchDeviceRegister(&touch_device, NONE, TOUCH_1_DEVICE_NAME_0); + if (EOK != ret) { + KPrintf("device %s error %d\n", TOUCH_1_DEVICE_NAME_0, ret); + return ERROR; + } + + ret = TouchDeviceAttachToBus(TOUCH_1_DEVICE_NAME_0, TOUCH_BUS_NAME_1); + if (EOK != ret) { + KPrintf("device %s error %d\n", TOUCH_1_DEVICE_NAME_0, ret); + return ERROR; + } + + return ret; +} + +int HwTouchBusInit(void) +{ + x_err_t ret = EOK; + struct RiscTouch *risc_touch; + + static struct TouchDriver touch_driver; + memset(&touch_driver, 0, sizeof(struct TouchDriver)); + + touch_driver.configure = TouchConfigure; + + risc_touch = &touch; + risc_touch->BusName = TOUCH_BUS_NAME_1; + risc_touch->touch_bus.private_data = &touch; + + TouchConfigure(NONE,NONE); + + ret = BoardTouchBusInit(risc_touch, &touch_driver); + if (EOK != ret) { + return ERROR; + } + + ret = BoardTouchDevBend(); + if (EOK != ret) { + KPrintf("board_touch_Init error ret %u\n", ret); + return ERROR; + } + return EOK; +} diff --git a/Ubiquitous/XiZi/board/aiit-riscv64-board/third_party_driver/uart/Kconfig b/Ubiquitous/XiZi/board/aiit-riscv64-board/third_party_driver/uart/Kconfig new file mode 100644 index 0000000..16069de --- /dev/null +++ b/Ubiquitous/XiZi/board/aiit-riscv64-board/third_party_driver/uart/Kconfig @@ -0,0 +1,57 @@ +menuconfig BSP_USING_UART_HS + bool "Enable High Speed UART" + default y + if BSP_USING_UART_HS + config SERIAL_BUS_NAME_0 + string "serial high speed bus 0 name" + default "uart0" + config SERIAL_DRV_NAME_0 + string "serial high speed bus 0 driver name" + default "uart0_drv" + config SERIAL_0_DEVICE_NAME_0 + string "serial high speed bus 0 device 0 name" + default "uart0_dev0" + endif + + +menuconfig BSP_USING_UART2 + bool "Enable UART2" + default y + if BSP_USING_UART2 + config BSP_UART2_TXD_PIN + int "uart2 TXD pin number" + default 20 + config BSP_UART2_RXD_PIN + int "uart2 RXD pin number" + default 19 + config SERIAL_BUS_NAME_2 + string "serial bus 2 name" + default "uart2" + config SERIAL_DRV_NAME_2 + string "serial bus 2 driver name" + default "uart2_drv" + config SERIAL_2_DEVICE_NAME_0 + string "serial bus 2 device 0 name" + default "uart2_dev2" + endif + +menuconfig BSP_USING_UART3 + bool "Enable UART3" + default y + if BSP_USING_UART3 + config BSP_UART3_TXD_PIN + int "uart3 TXD pin number" + default 22 + config BSP_UART3_RXD_PIN + int "uart3 RXD pin number" + default 23 + config SERIAL_BUS_NAME_3 + string "serial bus 3 name" + default "uart3" + config SERIAL_DRV_NAME_3 + string "serial bus 3 driver name" + default "uart3_drv" + config SERIAL_3_DEVICE_NAME_0 + string "serial bus 3 device 0 name" + default "uart3_dev3" + endif diff --git a/Ubiquitous/XiZi/board/aiit-riscv64-board/third_party_driver/uart/Makefile b/Ubiquitous/XiZi/board/aiit-riscv64-board/third_party_driver/uart/Makefile new file mode 100644 index 0000000..7696ffa --- /dev/null +++ b/Ubiquitous/XiZi/board/aiit-riscv64-board/third_party_driver/uart/Makefile @@ -0,0 +1,3 @@ +SRC_FILES := connect_uart.c + +include $(KERNEL_ROOT)/compiler.mk diff --git a/Ubiquitous/XiZi/board/aiit-riscv64-board/third_party_driver/watchdog/Kconfig b/Ubiquitous/XiZi/board/aiit-riscv64-board/third_party_driver/watchdog/Kconfig new file mode 100644 index 0000000..e801fa0 --- /dev/null +++ b/Ubiquitous/XiZi/board/aiit-riscv64-board/third_party_driver/watchdog/Kconfig @@ -0,0 +1,34 @@ +menuconfig BSP_USING_WDT0 +bool "Using watchdog 0 " +default n +if BSP_USING_WDT0 +config WDT_BUS_NAME_0 + string "watchdog bus 0 name" + default "wdt0" + +config WDT_DRIVER_NAME_0 + string "watchdog driver 0 name" + default "wdt0_drv" + +config WDT_0_DEVICE_NAME_0 + string "watchdog device 0 name" + default "wdt0_dev0" +endif + +menuconfig BSP_USING_WDT1 +bool "Using watchdog 1 " +default n +if BSP_USING_WDT1 +config WDT_BUS_NAME_1 + string "watchdog bus 1 name" + default "wdt1" + +config WDT_DRIVER_NAME_1 + string "watchdog driver 1 name" + default "wdt1_drv" + +config WDT_1_DEVICE_NAME_1 + string "watchdog device 1 name" + default "wdt1_dev1" +endif + diff --git a/Ubiquitous/XiZi/board/aiit-riscv64-board/third_party_driver/watchdog/Makefile b/Ubiquitous/XiZi/board/aiit-riscv64-board/third_party_driver/watchdog/Makefile new file mode 100644 index 0000000..c4842fd --- /dev/null +++ b/Ubiquitous/XiZi/board/aiit-riscv64-board/third_party_driver/watchdog/Makefile @@ -0,0 +1,6 @@ +SRC_FILES := wdt.c connect_wdt.c + + + + +include $(KERNEL_ROOT)/compiler.mk diff --git a/Ubiquitous/XiZi/board/aiit-riscv64-board/third_party_driver/watchdog/connect_wdt.c b/Ubiquitous/XiZi/board/aiit-riscv64-board/third_party_driver/watchdog/connect_wdt.c new file mode 100644 index 0000000..ce4fd18 --- /dev/null +++ b/Ubiquitous/XiZi/board/aiit-riscv64-board/third_party_driver/watchdog/connect_wdt.c @@ -0,0 +1,165 @@ +/* +* Copyright (c) 2020 AIIT XUOS Lab +* XiUOS is licensed under Mulan PSL v2. +* You can use this software according to the terms and conditions of the Mulan PSL v2. +* You may obtain a copy of Mulan PSL v2 at: +* http://license.coscl.org.cn/MulanPSL2 +* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, +* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, +* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. +* See the Mulan PSL v2 for more details. +*/ + +/** +* @file connect_wdt.c +* @brief support aiit-riscv64-board watchdog function and register to bus framework +* @version 1.0 +* @author AIIT XUOS Lab +* @date 2021-04-25 +*/ + +#include +#include + +static uint32 WdtOpen(void *dev) +{ + NULL_PARAM_CHECK(dev); + + wdt_device_number_t id; + struct WdtHardwareDevice *wdt = (struct WdtHardwareDevice *)dev; + id = *(wdt_device_number_t *)wdt->private_data; + + wdt_init(id, 4095, NONE, NONE); + return EOK; +} + +static uint32 WdtConfigure(void *drv, struct BusConfigureInfo *args) +{ + NULL_PARAM_CHECK(drv); + NULL_PARAM_CHECK(args); + + struct WdtDriver *wdt = (struct WdtDriver *)drv; + wdt_device_number_t id = *(wdt_device_number_t *)wdt->private_data; + + switch (args->configure_cmd) + { + case OPER_WDT_SET_TIMEOUT: + if (wdt_init(id, (uint64_t)*(int *)args->private_data, NONE, NONE) == 0) { + return ERROR; + } + break; + case OPER_WDT_KEEPALIVE: + wdt_feed(id); + break; + default: + return ERROR; + } + return EOK; +} + +static const struct WdtDevDone dev_done = +{ + WdtOpen, + NONE, + NONE, + NONE, +}; + +int HwWdtInit(void) +{ + wdt_device_number_t id; + + x_err_t ret = EOK; + +#ifdef BSP_USING_WDT0 + { + static struct WdtBus wdt0; + + ret = WdtBusInit(&wdt0, WDT_BUS_NAME_0); + if (ret != EOK) { + KPrintf("Watchdog bus init error %d\n", ret); + return ERROR; + } + + static struct WdtDriver drv0; + drv0.configure = WdtConfigure; + id = WDT_DEVICE_0; + drv0.private_data = &id; + + ret = WdtDriverInit(&drv0, WDT_DRIVER_NAME_0); + if (ret != EOK) { + KPrintf("Watchdog driver init error %d\n", ret); + return ERROR; + } + + ret = WdtDriverAttachToBus(WDT_DRIVER_NAME_0, WDT_BUS_NAME_0); + if (ret != EOK) { + KPrintf("Watchdog driver attach error %d\n", ret); + return ERROR; + } + + static struct WdtHardwareDevice dev0; + dev0.dev_done = &dev_done; + dev0.private_data = &id; + + ret = WdtDeviceRegister(&dev0, WDT_0_DEVICE_NAME_0); + if (ret != EOK) { + KPrintf("Watchdog device register error %d\n", ret); + return ERROR; + } + + ret = WdtDeviceAttachToBus(WDT_0_DEVICE_NAME_0, WDT_BUS_NAME_0); + if (ret != EOK) { + KPrintf("Watchdog device register error %d\n", ret); + return ERROR; + } + } +#endif + +#ifdef BSP_USING_WDT1 + { + static struct WdtBus wdt1; + + ret = WdtBusInit(&wdt1, WDT_BUS_NAME_1); + if (ret != EOK) { + KPrintf("Watchdog bus init error %d\n", ret); + return ERROR; + } + + static struct WdtDriver drv1; + drv1.configure = WdtConfigure; + id = WDT_DEVICE_1; + drv1.private_data = &id; + + ret = WdtDriverInit(&drv1, WDT_DRIVER_NAME_1); + if (ret != EOK) { + KPrintf("Watchdog driver init error %d\n", ret); + return ERROR; + } + + ret = WdtDriverAttachToBus(WDT_DRIVER_NAME_1, WDT_BUS_NAME_1); + if (ret != EOK) { + KPrintf("Watchdog driver attach error %d\n", ret); + return ERROR; + } + + static struct WdtHardwareDevice dev1; + dev1.dev_done = &dev_done; + dev1.private_data = &id; + + ret = WdtDeviceRegister(&dev1, WDT_1_DEVICE_NAME_1); + if (ret != EOK) { + KPrintf("Watchdog device register error %d\n", ret); + return ERROR; + } + + ret = WdtDeviceAttachToBus(WDT_1_DEVICE_NAME_1, WDT_BUS_NAME_1); + if (ret != EOK) { + KPrintf("Watchdog device register error %d\n", ret); + return ERROR; + } + } +#endif + + return ret; +} diff --git a/Ubiquitous/XiZi/board/gapuino/Kconfig b/Ubiquitous/XiZi/board/gapuino/Kconfig new file mode 100755 index 0000000..7244944 --- /dev/null +++ b/Ubiquitous/XiZi/board/gapuino/Kconfig @@ -0,0 +1,69 @@ +mainmenu "XiZi Project Configuration" + +config BSP_DIR + string + option env="BSP_ROOT" + default "." + +config KERNEL_DIR + string + option env="KERNEL_ROOT" + default "../.." + +config BOARD_GAPUINO + bool + select ARCH_RISCV + default y + + +source "$KERNEL_DIR/arch/Kconfig" + +menu "gapuino feature" + source "$BSP_DIR/third_party_driver/Kconfig" + + menu "config default board resources" + menu "config board app name" + config BOARD_APP_NAME + string "config board app name" + default "/XiUOS_gapuino_app.bin" + endmenu + + menu "config board service table" + config SERVICE_TABLE_ADDRESS + hex "board service table address" + default 0x80100000 + endmenu + + menu "config hardware resources for connection" + if CONNECTION_COMMUNICATION_ETHERNET + config ETHERNET_UART_NAME + string "ethernet uart name" + default "/dev/uart3_dev3" + endif + if CONNECTION_COMMUNICATION_WIFI + config WIFI_UART_NAME + string "wifi uart name" + default "/dev/uart3_dev3" + endif + + endmenu + + endmenu + + config __STACKSIZE__ + int "stack size for interrupt" + default 4096 + +endmenu + + + + + +menu "Hardware feature" +source "$KERNEL_DIR/resources/Kconfig" +endmenu + +source "$KERNEL_DIR/Kconfig" + + diff --git a/Ubiquitous/XiZi/board/gapuino/Makefile b/Ubiquitous/XiZi/board/gapuino/Makefile new file mode 100755 index 0000000..12f4148 --- /dev/null +++ b/Ubiquitous/XiZi/board/gapuino/Makefile @@ -0,0 +1,6 @@ +SRC_FILES := board.c + +SRC_DIR := third_party_driver + + +include $(KERNEL_ROOT)/compiler.mk diff --git a/Ubiquitous/XiZi/board/gapuino/README.md b/Ubiquitous/XiZi/board/gapuino/README.md new file mode 100755 index 0000000..8e9d92a --- /dev/null +++ b/Ubiquitous/XiZi/board/gapuino/README.md @@ -0,0 +1,183 @@ +# 从零开始构建矽璓工业物联操作系统：使用risc-v架构的gapuino 开发板 + +[XiUOS](http://xuos.io/) (X Industrial Ubiquitous Operating System) 矽璓工业物联操作系统是一款面向工业物联场景的泛在操作系统，来自泛在操作系统研究计划。所谓泛在操作系统(UOS: Ubiquitous Operating Systems)，是支持互联网时代人机物融合泛在计算应用模式的新型操作系统，是传统操作系统概念的泛化与延伸。在泛在操作系统技术体系中，不同的泛在计算设备和泛在应用场景需要符合各自特性的不同UOS，XiUOS即是面向工业物联场景的一种UOS，主要由一个极简的微型实时操作系统(RTOS)内核和其上的智能工业物联框架构成，支持工业物联网(IIoT: Industrial Internet of Things)应用。 + + +## 开发环境搭建 + +### 推荐使用： + +**操作系统：** ubuntu18.04 [https://ubuntu.com/download/desktop](https://ubuntu.com/download/desktop) + +**开发工具推荐使用 VSCode ，VScode下载地址为：** VSCode [https://code.visualstudio.com/](https://code.visualstudio.com/)，推荐下载地址为 [http://vscode.cdn.azure.cn/stable/3c4e3df9e89829dce27b7b5c24508306b151f30d/code_1.55.2-1618307277_amd64.deb](http://vscode.cdn.azure.cn/stable/3c4e3df9e89829dce27b7b5c24508306b151f30d/code_1.55.2-1618307277_amd64.deb) + +### 依赖包安装： + +``` +$ sudo apt install build-essential pkg-config +$ sudo apt install gcc make libncurses5-dev openssl libssl-dev bison flex libelf-dev autoconf libtool gperf libc6-dev git +``` + +**源码下载：** XiUOS [https://www.gitlink.org.cn/xuos/xiuos](https://www.gitlink.org.cn/xuos/xiuos) + +新建一个空文件夹并进入文件夹中，并下载源码，具体命令如下： + +```c +mkdir test && cd test +git clone https://gitlink.org.cn/xuos/xiuos.git +``` + +1、打开XiUOS源码文件包可以看到以下目录： +| 名称 | 说明 | +| -- | -- | +| APP_Framework | 应用代码 | +| Ubiquitous | 板级支持包,支持NuttX、RT-Thread和XiZi内核 | + +2、打开XiZi内核源码文件包可以看到以下目录： +| 名称 | 说明 | +| -- | -- | +| arch | 架构代码 | +| board | 板级支持包 | +| fs | 文件系统 | +| kernel | 内核源码 | +| lib | 第三方库源码 | +| resources | 驱动文件 | +| tool | 系统工具 | + +使用VScode打开代码，具体操作步骤为：在源码文件夹下打开系统终端，输入`code .`即可打开VScode开发环境，如下图所示： + +![vscode](img/vscode.jpg) + +### 裁减配置工具的下载 + +裁减配置工具： + +**工具地址：** kconfig-frontends [https://www.gitlink.org.cn/xuos/kconfig-frontends](https://www.gitlink.org.cn/xuos/kconfig-frontends) + +```c +mkdir kfrontends && cd kfrontends +git clone https://gitlink.org.cn/xuos/kconfig-frontends.git +``` + +下载源码后按以下步骤执行软件安装： + +```c +cd kconfig-frontends +./xs_build.sh +``` + +### 编译工具链： + +RISC-V: riscv-none-embed-，默认安装到Ubuntu的/opt/，下载源码并解压。[下载网址 http://101.36.126.201:8011/gnu-mcu-eclipse.tar.bz2](http://101.36.126.201:8011/gnu-mcu-eclipse.tar.bz2) + +```shell +$ tar -xjf gnu-mcu-eclipse.tar.bz2 -C /opt/ +``` + +将上述解压的编译工具链的路径添加到board/hifive1-rev-B/config.mk文件当中，例如： + +``` +export CROSS_COMPILE ?=/opt/gnu-mcu-eclipse/riscv-none-gcc/8.2.0-2.1-20190425-1021/bin/riscv-none-embed- +``` + +若已存在`export CROSS_COMPILE ?=xxxx` 应该将原有的语句注释，再写入上面的语句。 + +# 在gapuino board 上创建第一个应用 + +## 1.gapuino board 简介 + +| 硬件 | 描述 | +| -- | -- | +|芯片型号| gap8 | +|架构| RV32IMAC | +|主频| 200+MHz | +|片内SRAM| 512KB | +| 外设 | UART、SPI、I2C | + +XiUOS板级当前支持使用UART。 + +## 2. 代码编写与编译说明 + +编辑环境：`VScode` + +编译工具链：`riscv-none-embed-gcc` + +使用`VScode`打开工程的方法有多种，本文介绍一种快捷键，在项目目录下将`code .`输入终端即可打开目标项目 + +修改`APP_Framework/Applications`文件夹下`main.c` + +在输出函数中写入 Hello, world! \n 完成代码编辑。 + + +编译步骤： + +1.在VScode终端下执行以下命令，生成配置文件 + +``` +cd ./Ubiquitous/XiZi +make BOARD=gapuino distclean +make BOARD=gapuino menuconfig +``` + +2.在menuconfig界面配置需要关闭和开启的功能，按回车键进入下级菜单，按Y键选中需要开启的功能，按N键选中需要关闭的功能，配置结束后选择Exit保存并退出 + +![menuconfig](img/menuconfig.png) + +3.继续执行以下命令，进行编译 + +``` +make BOARD=gapuino +``` + +4.如果编译正确无误，build文件夹下会产生XiZi_gapuino.elf、XiZi_gapuino.bin文件。 + +>注：最后可以执行以下命令，清除配置文件和编译生成的文件 + +``` +make BOARD=gapuino distclean +``` + +## 3. 烧写及执行 + +gapuino支持jtag，可以通过jtag进行烧录和调试。 +调试烧写需要下载gap sdk和openocd,下载配置方法参见以下文档： +https://greenwaves-technologies.com/setting-up-sdk/ + +在SDK 和openocd安装完成以后，按照如下步骤进行调试： + +1、进入sdk目录路径下 +``` +cd ~/gap_sdk +``` + +2、在当前终端输入 +``` +source sourceme.sh +``` +出现如下图所示的界面，输入7选择单板名称； +![choose](./img/choose_board.png) + +3、先按开发板的复位键，再在当前终端输入 +``` +gap8-openocd -f interface/ftdi/gapuino_ftdi.cfg -f target/gap8.tcl -f tcl/jtag_boot_entry.tcl +``` +在当前终端连接openocd，连接如下图所示： +![openocd](./img/openocd.png) + +4、打开一个新的终端，输入以下命令打开终端串口： +``` +sudo apt install screen +screen /dev/ttyUSB0 115200 +``` + +5、打开一个新的终端，进入编译生成的elf路径,输入例如： +``` +riscv32-unknown-elf-gdb build/XiZi_gapuino.elf -ex "target remote localhost:3333" +``` +结果如下图所示： +![gdb](./img/gdb_load.png) + +6、再输入load，最后输入continue命令即可在串口终端看到系统运行界面，如下图所示： +![terminal](./img/terminal.png) + + diff --git a/Ubiquitous/XiZi/board/gapuino/board.c b/Ubiquitous/XiZi/board/gapuino/board.c new file mode 100755 index 0000000..0f60217 --- /dev/null +++ b/Ubiquitous/XiZi/board/gapuino/board.c @@ -0,0 +1,77 @@ +/* +* Copyright (c) 2020 AIIT XUOS Lab +* XiUOS is licensed under Mulan PSL v2. +* You can use this software according to the terms and conditions of the Mulan PSL v2. +* You may obtain a copy of Mulan PSL v2 at: +* http://license.coscl.org.cn/MulanPSL2 +* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, +* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, +* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. +* See the Mulan PSL v2 for more details. +*/ + +/** +* @file board.c +* @brief support gap8 init configure and start-up +* @version 1.0 +* @author AIIT XUOS Lab +* @date 2021-09-02 +*/ + +#include +#include +#include +#include + +extern void entry(void); +extern int InitHwUart(void); +extern void irqinitialize(void); +extern void timer_initialize(void); +extern void gapuino_sysinit(void); + +extern unsigned int __bss_end__; +/* Return core id. */ +uint32_t _procid( void ) +{ + uint32_t ulProcid = 0; + __asm__ volatile( "csrr %0, mhartid" : "=r"( ulProcid ) ); + ulProcid = ulProcid & 0xf; + return ( ulProcid ); +} + +/* Return cluster id. */ +uint32_t _clusterid( void ) +{ + uint32_t ulCluster = 0; + __asm__ volatile( "csrr %0, mhartid" : "=r"( ulCluster ) ); + ulCluster = ulCluster >> 5; + return ( ulCluster ); +} + +void GapuinoStart(uint32_t mhartid) +{ + gapuino_sysinit(); + entry(); +} +void InitBoardHardware(void) +{ + irqinitialize(); + + InitBoardMemory(MEMORY_START_ADDRESS, MEMORY_END_ADDRESS); + + InitHwUart(); + InstallConsole("uart0", "uart0_drv", "uart0_dev0"); + + KPrintf("console init completed.\n"); + KPrintf("board initialization......\n"); + + timer_initialize(); + KPrintf("memory address range: [0x%08x - 0x%08x], size: %d\n", (x_ubase) MEMORY_START_ADDRESS, (x_ubase) MEMORY_END_ADDRESS, GAP8_SRAM_SIZE); + /* initialize memory system */ + KPrintf("gap8 cluster id: [0x%x], _procid: [0x%x]\n", _clusterid(),_procid()); + + KPrintf("board init done.\n"); + KPrintf("start kernel...\n"); + return; +} + diff --git a/Ubiquitous/XiZi/board/gapuino/board.h b/Ubiquitous/XiZi/board/gapuino/board.h new file mode 100755 index 0000000..469ff21 --- /dev/null +++ b/Ubiquitous/XiZi/board/gapuino/board.h @@ -0,0 +1,68 @@ +/* +* Copyright (c) 2020 AIIT XUOS Lab +* XiUOS is licensed under Mulan PSL v2. +* You can use this software according to the terms and conditions of the Mulan PSL v2. +* You may obtain a copy of Mulan PSL v2 at: +* http://license.coscl.org.cn/MulanPSL2 +* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, +* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, +* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. +* See the Mulan PSL v2 for more details. +*/ + +/** +* @file board.h +* @brief define gapuino-board init configure and start-up function +* @version 1.0 +* @author AIIT XUOS Lab +* @date 2021-09-02 +*/ + +/************************************************* +File name: board.h +Description: define gapuino-board init configure and start-up function +Others: +History: +1. Date: 2021-09-02 +Author: AIIT XUOS Lab +Modification: +1. define gapuino-board InitBoardHardware +2. define gapuino-board data and bss struct +*************************************************/ +#ifndef BOARD_H__ +#define BOARD_H__ + +#include +#include + +#ifndef __ASSEMBLY__ + +#undef EXTERN +#if defined(__cplusplus) +#define EXTERN extern "C" +extern "C" +{ +#else +#define EXTERN extern +#endif + +extern unsigned int __bss_start__; +extern unsigned int __bss_end__; +extern unsigned int _end; +extern unsigned int __stack_end__; +extern unsigned int g_service_table_start; +extern unsigned int g_service_table_end; + +// #define MEMORY_START_ADDRESS (void*)(&__bss_end__) +#define MEMORY_START_ADDRESS (void*)(&_end) +#define GAP8_SRAM_SIZE 512 +#define MEMORY_END_ADDRESS (void*)(0x1C000000 + GAP8_SRAM_SIZE * 1024) + + +#undef EXTERN +#if defined(__cplusplus) +} +#endif +#endif + +#endif diff --git a/Ubiquitous/XiZi/board/gapuino/config.mk b/Ubiquitous/XiZi/board/gapuino/config.mk new file mode 100755 index 0000000..2897695 --- /dev/null +++ b/Ubiquitous/XiZi/board/gapuino/config.mk @@ -0,0 +1,38 @@ +# ARCHCFLAGS = -fno-builtin +# ARCHCXXFLAGS = -fno-builtin -fno-exceptions -fcheck-new -fno-rtti +# ARCHPICFLAGS = -fpic -msingle-pic-base -mpic-register=r10 + +# ARCHOPTIMIZATION = -g +# ASARCHCPUFLAGS += -Wa,-g + +# ARCHCPUFLAGS = -march=rv32imcxgap8 -mPE=8 -mFC=1 -D__riscv__ -D__pulp__ -D__GAP8__ -fno-common -ffunction-sections -fdata-sections -fstrict-volatile-bitfields + +# export CFLAGS := $(ARCHCFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) -O0 -g3 -gdwarf-2 + +# export AFLAGS := $(CFLAGS) -D__ASSEMBLY__ $(ASARCHCPUFLAGS) + +# export LFLAGS := -march=rv32imcxgap8 -mPE=8 -mFC=1 -nostartfiles -Wl,--gc-sections,-Map=XiUOS_gap8.map,-cref,-u,reset_handler -T $(BSP_ROOT)/link.lds + +# export APPLFLAGS := -march=rv32imcxgap8 -mPE=8 -mFC=1 -nostartfiles -Wl,--gc-sections,-Map=XiUOS_app.map,-cref,-u, -T $(BSP_ROOT)/link_userspace.lds + +# export CXXFLAGS := $(ARCHCXXFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) + +# export CROSS_COMPILE ?=/opt/gap_riscv_toolchain/bin/riscv32-unknown-elf- + + +export CFLAGS := -mcmodel=medany -march=rv32imac -mabi=ilp32 -fno-common -ffunction-sections -fdata-sections -fstrict-volatile-bitfields -O0 -ggdb -fgnu89-inline -Werror +export AFLAGS := -c -mcmodel=medany -march=rv32imac -mabi=ilp32 -x assembler-with-cpp -ggdb +export LFLAGS := -mcmodel=medany -march=rv32imac -mabi=ilp32 -nostartfiles -Wl,--gc-sections,-Map=XiZi_gap8.map,-cref,-u,_start -T $(BSP_ROOT)/link.lds + +export APPLFLAGS := -mcmodel=medany -march=rv32imac -mabi=ilp32 -nostartfiles -Wl,--gc-sections,-Map=XiZi_app.map,-cref,-u, -T $(BSP_ROOT)/link_userspace.lds + +export CXXFLAGS := -mcmodel=medany -march=rv32imac -mabi=ilp32 -fno-common -ffunction-sections -fdata-sections -fstrict-volatile-bitfields -O0 -ggdb -Werror + +export CROSS_COMPILE ?=/opt/gnu-mcu-eclipse/riscv-none-gcc/8.2.0-2.1-20190425-1021/bin/riscv-none-embed- + +export DEFINES := -DHAVE_CCONFIG_H -DHAVE_SIGINFO + +export ARCH = risc-v +export MCU = GAP8 + + diff --git a/Ubiquitous/XiZi/board/gapuino/img/choose_board.png b/Ubiquitous/XiZi/board/gapuino/img/choose_board.png new file mode 100644 index 0000000..7d8f867 Binary files /dev/null and b/Ubiquitous/XiZi/board/gapuino/img/choose_board.png differ diff --git a/Ubiquitous/XiZi/board/gapuino/img/gdb_load.png b/Ubiquitous/XiZi/board/gapuino/img/gdb_load.png new file mode 100644 index 0000000..ede81e7 Binary files /dev/null and b/Ubiquitous/XiZi/board/gapuino/img/gdb_load.png differ diff --git a/Ubiquitous/XiZi/board/gapuino/img/menuconfig.png b/Ubiquitous/XiZi/board/gapuino/img/menuconfig.png new file mode 100644 index 0000000..e9516cf Binary files /dev/null and b/Ubiquitous/XiZi/board/gapuino/img/menuconfig.png differ diff --git a/Ubiquitous/XiZi/board/gapuino/img/openocd.png b/Ubiquitous/XiZi/board/gapuino/img/openocd.png new file mode 100644 index 0000000..2493c34 Binary files /dev/null and b/Ubiquitous/XiZi/board/gapuino/img/openocd.png differ diff --git a/Ubiquitous/XiZi/board/gapuino/img/terminal.png b/Ubiquitous/XiZi/board/gapuino/img/terminal.png new file mode 100644 index 0000000..8dad4f4 Binary files /dev/null and b/Ubiquitous/XiZi/board/gapuino/img/terminal.png differ diff --git a/Ubiquitous/XiZi/board/gapuino/img/vscode.jpg b/Ubiquitous/XiZi/board/gapuino/img/vscode.jpg new file mode 100644 index 0000000..b9bacff Binary files /dev/null and b/Ubiquitous/XiZi/board/gapuino/img/vscode.jpg differ diff --git a/Ubiquitous/XiZi/board/gapuino/link.lds b/Ubiquitous/XiZi/board/gapuino/link.lds new file mode 100755 index 0000000..4efa0b0 --- /dev/null +++ b/Ubiquitous/XiZi/board/gapuino/link.lds @@ -0,0 +1,138 @@ +/* +* Copyright (c) 2020 AIIT XUOS Lab +* XiUOS is licensed under Mulan PSL v2. +* You can use this software according to the terms and conditions of the Mulan PSL v2. +* You may obtain a copy of Mulan PSL v2 at: +* http://license.coscl.org.cn/MulanPSL2 +* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, +* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, +* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. +* See the Mulan PSL v2 for more details. +*/ + +OUTPUT_ARCH( riscv ) +SEARCH_DIR(.) +__DYNAMIC = 0; + +MEMORY +{ + L2 (wxa!ri) : ORIGIN = 0x1C000000, LENGTH = 0x80000 + FC_tcdm : ORIGIN = 0x1B000004, LENGTH = 0x3ffc + FC_tcdm_aliased : ORIGIN = 0x00000004, LENGTH = 0x3ffc +} + +__L1_STACK_SIZE = 0x400; +__FC_STACK_SIZE = 4096; + +/* We have to align each sector to word boundaries as our current s19->slm + * conversion scripts are not able to handle non-word aligned sections. + */ +ENTRY( reset_handler ) +SECTIONS +{ + .vectors_M : + { + . = ALIGN(4); + IRQ_U_Vector_Base = .; + KEEP(*(.vectors_M)) + } > L2 + + .dbg_struct : + { + . = ALIGN(4); + IRQ_M_Vector_Base = .; + KEEP(*(.dbg_struct)) + } > L2 + + . = ALIGN(4); + + .text : { + PROVIDE( _text = ABSOLUTE(.) ); + /* _stext = .; */ + *(.text .text.*) + /* *(.rodata .rodata*) */ + /* _etext = .; */ + + /* section information for shell */ + . = ALIGN(4); + _shell_command_start = .; + KEEP (*(shellCommand)) + _shell_command_end = .; + . = ALIGN(4); + + PROVIDE(__ctors_start__ = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array)) + PROVIDE(__ctors_end__ = .); + + . = ALIGN(4); + __isrtbl_idx_start = .; + KEEP(*(.isrtbl.idx)) + __isrtbl_start = .; + KEEP(*(.isrtbl)) + __isrtbl_end = .; + . = ALIGN(4); + + PROVIDE(g_service_table_start = ABSOLUTE(.)); + KEEP(*(.g_service_table)) + PROVIDE(g_service_table_end = ABSOLUTE(.)); + + /* _endtext = .; */ + PROVIDE( _etext = ABSOLUTE(.) ); + } > L2 + + .rodata : { + /* Due to limitations on FPGA loader, loadable sections must have + * base and size aligned on 4 bytes + */ + + . = ALIGN(4); + *(.rodata); + *(.rodata.*) + . = ALIGN(4); + } > L2 + . = ALIGN(4); + .data : { + + __data_start__ = .; /* create a global symbol at data start */ + *(.data .data.*) + + . = ALIGN(4); + PROVIDE( __global_pointer$ = ABSOLUTE(.) + 0x800 ); + *(.sdata .sdata.*) + + __data_end__ = .; /* define a global symbol at data end */ + } > L2 + + . = ALIGN(4); + + .bss : + { + __bss_start = ABSOLUTE(.); + _fbss = .; + + /* Writable uninitialized small data segment (.sbss segment)*/ + *(.sbss .sbss.*) + *(.scommon) + + /* Uninitialized writeable data section (.bss segment)*/ + *(.bss .bss.*) + *(COMMON) + + . = ALIGN(4); + __bss_end = ABSOLUTE(.); + + } > L2 + + .stack : + { + . = ALIGN(4); + PROVIDE(_idle_stack_start = ABSOLUTE(.)); + + . = . + __FC_STACK_SIZE; + + PROVIDE( _idle_stack_end = ABSOLUTE(.) ); + } > L2 + _end = ABSOLUTE(.); + +} diff --git a/Ubiquitous/XiZi/board/gapuino/third_party_driver/Kconfig b/Ubiquitous/XiZi/board/gapuino/third_party_driver/Kconfig new file mode 100755 index 0000000..cee6d37 --- /dev/null +++ b/Ubiquitous/XiZi/board/gapuino/third_party_driver/Kconfig @@ -0,0 +1,25 @@ +menuconfig BSP_USING_GPIO + bool "Using GPIO device" + default y + select RESOURCES_PIN + if BSP_USING_GPIO + source "$BSP_DIR/third_party_driver/gpio/Kconfig" + endif + +menuconfig BSP_USING_SYSCLOCK + bool "Using SYSCLOCK device" + default y + if BSP_USING_SYSCLOCK + source "$BSP_DIR/third_party_driver/sys_clock/Kconfig" + endif + +menuconfig BSP_USING_UART + bool "Using UART device" + default y + select RESOURCES_SERIAL + if BSP_USING_UART + source "$BSP_DIR/third_party_driver/uart/Kconfig" + endif + + + \ No newline at end of file diff --git a/Ubiquitous/XiZi/board/gapuino/third_party_driver/Makefile b/Ubiquitous/XiZi/board/gapuino/third_party_driver/Makefile new file mode 100755 index 0000000..f4f4cec --- /dev/null +++ b/Ubiquitous/XiZi/board/gapuino/third_party_driver/Makefile @@ -0,0 +1,21 @@ +SRC_FILES := +SRC_DIR := timer + +ifeq ($(CONFIG_BSP_USING_GPIO),y) + SRC_DIR += gpio +endif + +ifeq ($(CONFIG_BSP_USING_PLIC),y) + SRC_DIR += plic +endif + +ifeq ($(CONFIG_BSP_USING_SYSCLOCK),y) + SRC_DIR += sys_clock +endif + +ifeq ($(CONFIG_BSP_USING_UART),y) + SRC_DIR += uart +endif + + +include $(KERNEL_ROOT)/compiler.mk diff --git a/Ubiquitous/XiZi/board/gapuino/third_party_driver/gpio/Kconfig b/Ubiquitous/XiZi/board/gapuino/third_party_driver/gpio/Kconfig new file mode 100755 index 0000000..35dce73 --- /dev/null +++ b/Ubiquitous/XiZi/board/gapuino/third_party_driver/gpio/Kconfig @@ -0,0 +1,11 @@ +config PIN_BUS_NAME + string "pin bus name" + default "pin" + +config PIN_DRIVER_NAME + string "pin driver name" + default "pin_drv" + +config PIN_DEVICE_NAME + string "pin device name" + default "pin_dev" diff --git a/Ubiquitous/XiZi/board/gapuino/third_party_driver/gpio/Makefile b/Ubiquitous/XiZi/board/gapuino/third_party_driver/gpio/Makefile new file mode 100755 index 0000000..0eb7483 --- /dev/null +++ b/Ubiquitous/XiZi/board/gapuino/third_party_driver/gpio/Makefile @@ -0,0 +1,3 @@ +SRC_FILES := hardware_gpio.c + +include $(KERNEL_ROOT)/compiler.mk diff --git a/Ubiquitous/XiZi/board/gapuino/third_party_driver/include/connect_uart.h b/Ubiquitous/XiZi/board/gapuino/third_party_driver/include/connect_uart.h new file mode 100755 index 0000000..1bfa456 --- /dev/null +++ b/Ubiquitous/XiZi/board/gapuino/third_party_driver/include/connect_uart.h @@ -0,0 +1,38 @@ +/* +* Copyright (c) 2020 AIIT XUOS Lab +* XiUOS is licensed under Mulan PSL v2. +* You can use this software according to the terms and conditions of the Mulan PSL v2. +* You may obtain a copy of Mulan PSL v2 at: +* http://license.coscl.org.cn/MulanPSL2 +* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, +* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, +* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. +* See the Mulan PSL v2 for more details. +*/ + +/** +* @file connect_uart.h +* @brief define gap8-board uart function and struct +* @version 1.1 +* @author AIIT XUOS Lab +* @date 2021-07-27 +*/ + +#ifndef CONNECT_UART_H +#define CONNECT_UART_H + +#include + +#ifdef __cplusplus +extern "C" { +#endif + + + +int InitHwUart(void); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/Ubiquitous/XiZi/board/gapuino/third_party_driver/sys_clock/Kconfig b/Ubiquitous/XiZi/board/gapuino/third_party_driver/sys_clock/Kconfig new file mode 100755 index 0000000..8b13789 --- /dev/null +++ b/Ubiquitous/XiZi/board/gapuino/third_party_driver/sys_clock/Kconfig @@ -0,0 +1 @@ + diff --git a/Ubiquitous/XiZi/board/gapuino/third_party_driver/sys_clock/Makefile b/Ubiquitous/XiZi/board/gapuino/third_party_driver/sys_clock/Makefile new file mode 100755 index 0000000..ed938c8 --- /dev/null +++ b/Ubiquitous/XiZi/board/gapuino/third_party_driver/sys_clock/Makefile @@ -0,0 +1,3 @@ +SRC_FILES := gapuino_sysinit.c gap8_fll.c + +include $(KERNEL_ROOT)/compiler.mk diff --git a/Ubiquitous/XiZi/board/gapuino/third_party_driver/timer/Kconfig b/Ubiquitous/XiZi/board/gapuino/third_party_driver/timer/Kconfig new file mode 100755 index 0000000..fdc67b1 --- /dev/null +++ b/Ubiquitous/XiZi/board/gapuino/third_party_driver/timer/Kconfig @@ -0,0 +1,19 @@ +if BSP_USING_HWTIMER + config HWTIMER_BUS_NAME_1 + string "hwtimer bus name" + default "hwtim1" + + menuconfig ENABLE_TIM1 + bool "enable TIM1" + default y + + if ENABLE_TIM1 + config HWTIMER_1_DEVICE_NAME_1 + string "TIM1 dev name" + default "hwtim1_dev1" + + config HWTIMER_DRIVER_NAME_1 + string "TIM1 drv name" + default "hwtim1_drv" + endif +endif diff --git a/Ubiquitous/XiZi/board/gapuino/third_party_driver/timer/Makefile b/Ubiquitous/XiZi/board/gapuino/third_party_driver/timer/Makefile new file mode 100755 index 0000000..2d3d7a4 --- /dev/null +++ b/Ubiquitous/XiZi/board/gapuino/third_party_driver/timer/Makefile @@ -0,0 +1,3 @@ +SRC_FILES := hardware_hwtimer.c + +include $(KERNEL_ROOT)/compiler.mk diff --git a/Ubiquitous/XiZi/board/gapuino/third_party_driver/uart/Kconfig b/Ubiquitous/XiZi/board/gapuino/third_party_driver/uart/Kconfig new file mode 100755 index 0000000..3da44cd --- /dev/null +++ b/Ubiquitous/XiZi/board/gapuino/third_party_driver/uart/Kconfig @@ -0,0 +1,14 @@ +menuconfig BSP_USING_UART0 + bool "Enable UART0" + default y + if BSP_USING_UART0 + config SERIAL_BUS_NAME_0 + string "serial bus name" + default "uart0" + config SERIAL_DRV_NAME_0 + string "serial bus driver name" + default "uart0_drv" + config SERIAL_0_DEVICE_NAME_0 + string "serial bus device name" + default "uart0_dev0" + endif diff --git a/Ubiquitous/XiZi/board/gapuino/third_party_driver/uart/Makefile b/Ubiquitous/XiZi/board/gapuino/third_party_driver/uart/Makefile new file mode 100755 index 0000000..e2f8c71 --- /dev/null +++ b/Ubiquitous/XiZi/board/gapuino/third_party_driver/uart/Makefile @@ -0,0 +1,4 @@ +SRC_FILES := connect_uart.c hardware_udma.c + + +include $(KERNEL_ROOT)/compiler.mk diff --git a/Ubiquitous/XiZi/board/gapuino/third_party_driver/uart/connect_uart.c b/Ubiquitous/XiZi/board/gapuino/third_party_driver/uart/connect_uart.c new file mode 100755 index 0000000..c9360d9 --- /dev/null +++ b/Ubiquitous/XiZi/board/gapuino/third_party_driver/uart/connect_uart.c @@ -0,0 +1,329 @@ +/* +* Copyright (c) 2020 AIIT XUOS Lab +* XiUOS is licensed under Mulan PSL v2. +* You can use this software according to the terms and conditions of the Mulan PSL v2. +* You may obtain a copy of Mulan PSL v2 at: +* http://license.coscl.org.cn/MulanPSL2 +* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, +* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, +* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. +* See the Mulan PSL v2 for more details. +*/ + +/** +* @file connect_usart.c +* @brief support gap8-board uart function and register to bus framework +* @version 1.1 +* @author AIIT XUOS Lab +* @date 2021-09-02 +*/ + +#include +#include + +#include "connect_uart.h" +#include "hardware_udma.h" +#include "hardware_gpio.h" +#include + +static void SerialCfgParamCheck(struct SerialCfgParam *serial_cfg_default, struct SerialCfgParam *serial_cfg_new) +{ + struct SerialDataCfg *data_cfg_default = &serial_cfg_default->data_cfg; + struct SerialDataCfg *data_cfg_new = &serial_cfg_new->data_cfg; + + if ((data_cfg_default->serial_baud_rate != data_cfg_new->serial_baud_rate) && (data_cfg_new->serial_baud_rate)) { + data_cfg_default->serial_baud_rate = data_cfg_new->serial_baud_rate; + } + + if ((data_cfg_default->serial_bit_order != data_cfg_new->serial_bit_order) && (data_cfg_new->serial_bit_order)) { + data_cfg_default->serial_bit_order = data_cfg_new->serial_bit_order; + } + + if ((data_cfg_default->serial_buffer_size != data_cfg_new->serial_buffer_size) && (data_cfg_new->serial_buffer_size)) { + data_cfg_default->serial_buffer_size = data_cfg_new->serial_buffer_size; + } + + if ((data_cfg_default->serial_data_bits != data_cfg_new->serial_data_bits) && (data_cfg_new->serial_data_bits)) { + data_cfg_default->serial_data_bits = data_cfg_new->serial_data_bits; + } + + if ((data_cfg_default->serial_invert_mode != data_cfg_new->serial_invert_mode) && (data_cfg_new->serial_invert_mode)) { + data_cfg_default->serial_invert_mode = data_cfg_new->serial_invert_mode; + } + + if ((data_cfg_default->serial_parity_mode != data_cfg_new->serial_parity_mode) && (data_cfg_new->serial_parity_mode)) { + data_cfg_default->serial_parity_mode = data_cfg_new->serial_parity_mode; + } + + if ((data_cfg_default->serial_stop_bits != data_cfg_new->serial_stop_bits) && (data_cfg_new->serial_stop_bits)) { + data_cfg_default->serial_stop_bits = data_cfg_new->serial_stop_bits; + } +} + +static void UartRxIsr(void *arg) +{ + struct SerialBus *serial_bus = (struct SerialBus *)arg; + struct SerialHardwareDevice *serial_dev = (struct SerialHardwareDevice *)serial_bus->bus.owner_haldev; + + SerialSetIsr(serial_dev, SERIAL_EVENT_RX_IND); +} + +static uint32 SerialInit(struct SerialDriver *serial_drv, struct BusConfigureInfo *configure_info) +{ + asm volatile("nop"); + NULL_PARAM_CHECK(serial_drv); + struct SerialCfgParam *serial_cfg = (struct SerialCfgParam *)serial_drv->private_data; + + if (configure_info->private_data) { + struct SerialCfgParam *serial_cfg_new = (struct SerialCfgParam *)configure_info->private_data; + SerialCfgParamCheck(serial_cfg, serial_cfg_new); + } + + struct gap8_udma_peripheral *uart_udma = (struct gap8_udma_peripheral *)serial_cfg->hw_cfg.private_data; + uart_reg_t *uart_reg = (uart_reg_t *)uart_udma->regs; + uint32_t cfg_reg = 0; + + uint16_t div = CONFIG_CORE_CLOCK_FREQ / serial_cfg->data_cfg.serial_baud_rate; + + gap8_udma_init(uart_udma); + + /* Setup baudrate etc. */ + cfg_reg = UART_SETUP_BIT_LENGTH(serial_cfg->data_cfg.serial_data_bits - 5) | + UART_SETUP_PARITY_ENA(serial_cfg->data_cfg.serial_parity_mode - 1) | + UART_SETUP_STOP_BITS(serial_cfg->data_cfg.serial_stop_bits - 1) | + UART_SETUP_TX_ENA(1) | + UART_SETUP_RX_ENA(1) | + UART_SETUP_CLKDIV(div); + uart_reg->SETUP = cfg_reg; + + gap8_configpin(GAP8_PIN_A7_UART_TX | GAP8_PIN_PULL_UP | GAP8_PIN_SPEED_HIGH); + gap8_configpin(GAP8_PIN_B6_UART_RX | GAP8_PIN_PULL_UP | GAP8_PIN_SPEED_HIGH); + + return EOK; +} +static char g_uart1rxbuffer[128]; +static uint32 SerialConfigure(struct SerialDriver *serial_drv, int serial_operation_cmd) +{ + NULL_PARAM_CHECK(serial_drv); + + struct SerialHardwareDevice *serial_dev = (struct SerialHardwareDevice *)serial_drv->driver.owner_bus->owner_haldev; + + struct SerialCfgParam *serial_cfg = (struct SerialCfgParam *)serial_drv->private_data; + struct gap8_udma_peripheral *uart_udma = (struct gap8_udma_peripheral *)serial_cfg->hw_cfg.private_data; + + if (OPER_SET_INT == serial_operation_cmd) { + x_base lock = 0; + lock = DISABLE_INTERRUPT(); + + gap8_udma_rx_setirq(uart_udma, 1); + + gap8_udma_rx_start(uart_udma, g_uart1rxbuffer, 1, 1); + + ENABLE_INTERRUPT(lock); + } else if (OPER_CLR_INT == serial_operation_cmd) { + gap8_udma_rx_setirq(uart_udma, 0); + + gap8_udma_deinit(uart_udma); + } + + return EOK; +} + +static uint32 SerialDrvConfigure(void *drv, struct BusConfigureInfo *configure_info) +{ + NULL_PARAM_CHECK(drv); + NULL_PARAM_CHECK(configure_info); + + x_err_t ret = EOK; + int serial_operation_cmd; + struct SerialDriver *serial_drv = (struct SerialDriver *)drv; + + switch (configure_info->configure_cmd) + { + case OPE_INT: + ret = SerialInit(serial_drv, configure_info); + break; + case OPE_CFG: + serial_operation_cmd = *(int *)configure_info->private_data; + ret = SerialConfigure(serial_drv, serial_operation_cmd); + break; + default: + break; + } + + return ret; +} + +static int SerialPutChar(struct SerialHardwareDevice *serial_dev, char c) +{ + struct Driver *drv = serial_dev->haldev.owner_bus->owner_driver; + struct SerialDriver *serial_drv = (struct SerialDriver *)drv; + struct SerialDevParam *serial_dev_param = (struct SerialDevParam *)serial_dev->haldev.private_data; + struct SerialCfgParam *serial_cfg = (struct SerialCfgParam *)serial_dev->private_data; + struct gap8_udma_peripheral *uart_udma = (struct gap8_udma_peripheral *)serial_cfg->hw_cfg.private_data; + + gap8_udma_tx_setirq(uart_udma,1); + gap8_udma_tx_start(uart_udma, &c, 1, 1); + + for(int i = 999 ; i> 0 ; i--); + + return 0; +} + +static int SerialGetChar(struct SerialHardwareDevice *serial_dev) +{ + struct Driver *drv = serial_dev->haldev.owner_bus->owner_driver; + struct SerialDriver *serial_drv = (struct SerialDriver *)drv; + struct SerialDevParam *serial_dev_param = (struct SerialDevParam *)serial_dev->haldev.private_data; + struct SerialCfgParam *serial_cfg = (struct SerialCfgParam *)serial_dev->private_data; + struct gap8_udma_peripheral *uart_udma = (struct gap8_udma_peripheral *)serial_cfg->hw_cfg.private_data; + + uint8_t rx_buf[4] = {0}; + uint8_t ch = g_uart1rxbuffer[0]; + + /* Then trigger another reception */ + gap8_udma_rx_setirq(uart_udma, 1); + gap8_udma_rx_start(uart_udma, g_uart1rxbuffer, 1, 1); + + if (ch == 0) + return -ERROR; + + memset(g_uart1rxbuffer,0,128); + + return ch; +} + +static const struct SerialDataCfg data_cfg_init = +{ + .serial_baud_rate = BAUD_RATE_115200, + .serial_data_bits = DATA_BITS_8, + .serial_stop_bits = STOP_BITS_1, + .serial_parity_mode = PARITY_NONE, + .serial_bit_order = BIT_ORDER_LSB, + .serial_invert_mode = NRZ_NORMAL, + .serial_buffer_size = SERIAL_RB_BUFSZ, +}; + +static struct gap8_udma_peripheral gap8_udma = +{ + .regs = (volatile udma_reg_t *)UART, + .id = GAP8_UDMA_ID_UART, + .on_tx = NONE,//UartRxIsr?? + // .on_tx = UartTxIsr,//UartRxIsr?? + .tx_arg = NONE, + .on_rx = UartRxIsr, + .rx_arg = NONE, + .is_tx_continous = 0, + .is_rx_continous = 1, +}; + +/*manage the serial device operations*/ +static const struct SerialDrvDone drv_done = +{ + .init = SerialInit, + .configure = SerialConfigure, +}; + +/*manage the serial device hal operations*/ +static struct SerialHwDevDone hwdev_done = +{ + .put_char = SerialPutChar, + .get_char = SerialGetChar, +}; + +static int BoardSerialBusInit(struct SerialBus *serial_bus, struct SerialDriver *serial_driver, const char *bus_name, const char *drv_name) +{ + x_err_t ret = EOK; + + /*Init the serial bus */ + ret = SerialBusInit(serial_bus, bus_name); + if (EOK != ret) { + KPrintf("InitHwUart SerialBusInit error %d\n", ret); + return ERROR; + } + + /*Init the serial driver*/ + ret = SerialDriverInit(serial_driver, drv_name); + if (EOK != ret) { + KPrintf("InitHwUart SerialDriverInit error %d\n", ret); + return ERROR; + } + + /*Attach the serial driver to the serial bus*/ + ret = SerialDriverAttachToBus(drv_name, bus_name); + if (EOK != ret) { + KPrintf("InitHwUart SerialDriverAttachToBus error %d\n", ret); + return ERROR; + } + + return ret; +} + +/*Attach the serial device to the serial bus*/ +static int BoardSerialDevBend(struct SerialHardwareDevice *serial_device, void *serial_param, const char *bus_name, const char *dev_name) +{ + x_err_t ret = EOK; + + ret = SerialDeviceRegister(serial_device, serial_param, dev_name); + if (EOK != ret) { + KPrintf("InitHwUart SerialDeviceInit device %s error %d\n", dev_name, ret); + return ERROR; + } + + ret = SerialDeviceAttachToBus(dev_name, bus_name); + if (EOK != ret) { + KPrintf("InitHwUart SerialDeviceAttachToBus device %s error %d\n", dev_name, ret); + return ERROR; + } + + return ret; +} + +int InitHwUart(void) +{ + x_err_t ret = EOK; + + static struct SerialBus serial_bus; + memset(&serial_bus, 0, sizeof(struct SerialBus)); + + + static struct SerialDriver serial_driver; + memset(&serial_driver, 0, sizeof(struct SerialDriver)); + + static struct SerialHardwareDevice serial_device; + memset(&serial_device, 0, sizeof(struct SerialHardwareDevice)); + + static struct SerialCfgParam serial_cfg; + memset(&serial_cfg, 0, sizeof(struct SerialCfgParam)); + + static struct SerialDevParam serial_dev_param; + memset(&serial_dev_param, 0, sizeof(struct SerialDevParam)); + + serial_driver.drv_done = &drv_done; + serial_driver.configure = &SerialDrvConfigure; + serial_device.hwdev_done = &hwdev_done; + + serial_cfg.data_cfg = data_cfg_init; + + serial_cfg.hw_cfg.private_data = (void *)&gap8_udma; + serial_driver.private_data = (void *)&serial_cfg; + + serial_dev_param.serial_work_mode = SIGN_OPER_INT_RX; + serial_device.haldev.private_data = (void *)&serial_dev_param; + + ret = BoardSerialBusInit(&serial_bus, &serial_driver, SERIAL_BUS_NAME_0, SERIAL_DRV_NAME_0); + if (EOK != ret) { + KPrintf("InitHwUart uarths error ret %u\n", ret); + return ERROR; + } + + ret = BoardSerialDevBend(&serial_device, (void *)&serial_cfg, SERIAL_BUS_NAME_0, SERIAL_0_DEVICE_NAME_0); + if (EOK != ret) { + KPrintf("InitHwUart uarths error ret %u\n", ret); + return ERROR; + } + + gap8_udma.rx_arg = (void *)&serial_bus; + + return ret; +} diff --git a/Ubiquitous/XiZi/board/gd32vf103_rvstar/Kconfig b/Ubiquitous/XiZi/board/gd32vf103_rvstar/Kconfig new file mode 100755 index 0000000..ee5e727 --- /dev/null +++ b/Ubiquitous/XiZi/board/gd32vf103_rvstar/Kconfig @@ -0,0 +1,31 @@ +mainmenu "XiZi Project Configuration" + +config BSP_DIR + string + option env="BSP_ROOT" + default "." + +config KERNEL_DIR + string + option env="KERNEL_ROOT" + default "../.." + +config BOARD_GD32VF103RVSTAR + bool + select ARCH_RISCV + default y + +source "$KERNEL_DIR/arch/Kconfig" + +menu "gd32vf103_rvstar feature" + source "$BSP_DIR/third_party_driver/Kconfig" +endmenu + + +menu "Hardware feature" + source "$KERNEL_DIR/resources/Kconfig" +endmenu + +source "$KERNEL_DIR/Kconfig" + + diff --git a/Ubiquitous/XiZi/board/gd32vf103_rvstar/Makefile b/Ubiquitous/XiZi/board/gd32vf103_rvstar/Makefile new file mode 100755 index 0000000..00cf613 --- /dev/null +++ b/Ubiquitous/XiZi/board/gd32vf103_rvstar/Makefile @@ -0,0 +1,6 @@ +SRC_FILES := board.c gd32vf103v_rvstar.c + +SRC_DIR := third_party_driver + + +include $(KERNEL_ROOT)/compiler.mk diff --git a/Ubiquitous/XiZi/board/gd32vf103_rvstar/README.md b/Ubiquitous/XiZi/board/gd32vf103_rvstar/README.md new file mode 100755 index 0000000..355c154 --- /dev/null +++ b/Ubiquitous/XiZi/board/gd32vf103_rvstar/README.md @@ -0,0 +1,203 @@ +# 从零开始构建矽璓工业物联操作系统：使用risc-v架构的gd32vf103_rvstar 开发板 + +[XiUOS](http://xuos.io/) (X Industrial Ubiquitous Operating System) 矽璓工业物联操作系统是一款面向工业物联场景的泛在操作系统，来自泛在操作系统研究计划。所谓泛在操作系统(UOS: Ubiquitous Operating Systems)，是支持互联网时代人机物融合泛在计算应用模式的新型操作系统，是传统操作系统概念的泛化与延伸。在泛在操作系统技术体系中，不同的泛在计算设备和泛在应用场景需要符合各自特性的不同UOS，XiUOS即是面向工业物联场景的一种UOS，主要由一个极简的微型实时操作系统(RTOS)内核和其上的智能工业物联框架构成，支持工业物联网(IIoT: Industrial Internet of Things)应用。 + + +## 开发环境搭建 + +### 推荐使用： + +**操作系统：** ubuntu18.04 [https://ubuntu.com/download/desktop](https://ubuntu.com/download/desktop) + +**开发工具推荐使用 VSCode ，VScode下载地址为：** VSCode [https://code.visualstudio.com/](https://code.visualstudio.com/)，推荐下载地址为 [http://vscode.cdn.azure.cn/stable/3c4e3df9e89829dce27b7b5c24508306b151f30d/code_1.55.2-1618307277_amd64.deb](http://vscode.cdn.azure.cn/stable/3c4e3df9e89829dce27b7b5c24508306b151f30d/code_1.55.2-1618307277_amd64.deb) + +### 依赖包安装： + +``` +$ sudo apt install build-essential pkg-config +$ sudo apt install gcc make libncurses5-dev openssl libssl-dev bison flex libelf-dev autoconf libtool gperf libc6-dev git +``` + +**源码下载：** XiUOS [https://www.gitlink.org.cn/xuos/xiuos](https://www.gitlink.org.cn/xuos/xiuos) + +新建一个空文件夹并进入文件夹中，并下载源码，具体命令如下： + +```c +mkdir test && cd test +git clone https://gitlink.org.cn/xuos/xiuos.git +``` + +1、打开XiUOS源码文件包可以看到以下目录： +| 名称 | 说明 | +| -- | -- | +| APP_Framework | 应用代码 | +| Ubiquitous | 板级支持包,支持NuttX、RT-Thread和XiZi内核 | + +2、打开XiZi内核源码文件包可以看到以下目录： +| 名称 | 说明 | +| -- | -- | +| arch | 架构代码 | +| board | 板级支持包 | +| fs | 文件系统 | +| kernel | 内核源码 | +| lib | 第三方库源码 | +| resources | 驱动文件 | +| tool | 系统工具 | + +使用VScode打开代码，具体操作步骤为：在源码文件夹下打开系统终端，输入`code .`即可打开VScode开发环境，如下图所示： + +![vscode](img/vscode.jpg) + +### 裁减配置工具的下载 + +裁减配置工具： + +**工具地址：** kconfig-frontends [https://www.gitlink.org.cn/xuos/kconfig-frontends](https://www.gitlink.org.cn/xuos/kconfig-frontends) + +```c +mkdir kfrontends && cd kfrontends +git clone https://gitlink.org.cn/xuos/kconfig-frontends.git +``` + +下载源码后按以下步骤执行软件安装： + +```c +cd kconfig-frontends +./xs_build.sh +``` + +### 编译工具链： + +RISC-V: riscv-nuclei-elf-，默认安装到Ubuntu的/opt/，下载源码并解压。[下载网址 https://www.nucleisys.com/download.php] +![gnu](img/riscv_gnu.png) + +```shell +$ tar -xjf nuclei_riscv_newlibc_prebuilt_linux64_2020.08.tar.bz2 -C /opt/ +``` + +将上述解压的编译工具链的路径添加到board/hifive1-rev-B/config.mk文件当中，例如： + +``` +export CROSS_COMPILE ?=/opt/Nuclei/gcc/bin/riscv-nuclei-elf- +``` + +若已存在`export CROSS_COMPILE ?=xxxx` 应该将原有的语句注释，再写入上面的语句。 + +# 在gd32vf103_rvstar board 上创建第一个应用 + +## 1.gd32vf103_rvstar board 简介 + +| 硬件 | 描述 | +| -- | -- | +|芯片型号| gd32vf103 | +|架构| RV32IMAC | +|主频| 108MHz | +|片内SRAM| 32KB | +| 外设 | Timer（高级16位定时器，通用16位定时器）、U(S)ART、I2C、SPI/I2S、CAN、USBFS、ADC（16路外部通道）、DAC、EXMC、GPIO | + +XiUOS板级当前支持使用UART。 + +## 2. 代码编写与编译说明 + +编辑环境：`VScode` + +编译工具链：`riscv-none-embed-gcc` + +使用`VScode`打开工程的方法有多种，本文介绍一种快捷键，在项目目录下将`code .`输入终端即可打开目标项目 + +修改`APP_Framework/Applications`文件夹下`main.c` + +在输出函数中写入 Hello, world! \n 完成代码编辑。 + + +编译步骤： + +1.在VScode终端下执行以下命令，生成配置文件 + +``` +cd ./Ubiquitous/XiZi +make BOARD=gd32vf103_rvstar distclean +make BOARD=gd32vf103_rvstar menuconfig +``` + +2.在menuconfig界面配置需要关闭和开启的功能，按回车键进入下级菜单，按Y键选中需要开启的功能，按N键选中需要关闭的功能，配置结束后选择Exit保存并退出 + +![menuconfig](img/menuconfig.png) + +3.继续执行以下命令，进行编译 + +``` +make BOARD=gd32vf103_rvstar +``` + +4.如果编译正确无误，build文件夹下会产生XiZi_gd32vf103_rvstar.elf、XiZi_gd32vf103_rvstar.bin文件。 + +>注：最后可以执行以下命令，清除配置文件和编译生成的文件 + +``` +make BOARD=gd32vf103_rvstar distclean +``` + +## 3. 烧写及调试执行 +rvstar开发板启动模式说明： +![boot_mode](./img/boot_mode.png) + + +### 3.1 openocd gdb 调试方法 +选择boot模式，将引脚BOOT0 = H BOOT1 = H； + +rvstar支持openocd，可以通过openocd和gdb进行调试。 +调试需要下载openocd和nuclei sdk,下载配置方法参见以下文档： +https://doc.nucleisys.com/nuclei_sdk/quickstart.html#figure-quickstart-5 + +openocd安装完成以后，按照如下步骤进行调试： + +1、进入xiuos目录路径下 +``` +cd ~/xiuos/Ubiquitous/XiZi +``` + +2、编译生成elf文件 + + +3、使用USB先和串口连接好开发板，进入openocd目录下，再在当前终端输入 +``` +cd ~/Nuclei/openocd/0.10.0-15/bin + +./openocd -f ~/nuclei-sdk/SoC/gd32vf103/Board/gd32vf103v_rvstar/openocd_gd32vf103.cfg +``` +在当前终端连接openocd，连接如下图所示： +![openocd](./img/openocd.png) + +4、打开一个新的终端，输入以下命令打开终端串口： +``` +sudo apt install screen +screen /dev/ttyUSB0 115200 +``` + +5、打开一个新的终端，进入编译生成的elf路径,输入例如： +``` +riscv-nuclei-elf-gdb build/XiZi_gd32vf103_rvstar.elf -ex "target remote localhost:3333" +``` +结果如下图所示： +![gdb](./img/gdb_load.png) + +6、再输入load，最后输入continue命令即可在串口终端看到系统运行界面，如下图所示： +![terminal](./img/terminal.png) + +该调试方式会同步将ELF文件load到片上flash，此时将boot模式改成“主闪存”，断开gdb一样可以启动. + +### 3.2 bin文件烧写flash + +1、选择boot模式为“系统存储器”，将引脚BOOT0 = 1,BOOT1 = 0; +烧写可以通过如下两个支持ISP的串口： +![isp_usart](./img/ISP_support_usart.png) + +2、通过串口连接上开发板：串口RX接D5(tx)，串口TX接D6(rx)两个位置。 + +3、通过软件GigaDevice MCU ISP Programmer工具（下载地址：http://www.gd32mcu.com/en/download/7?kw=GD32VF1） 进行bin文件烧写。 +![GigaDevice](./img/GigaDevice.png) + +4、烧写完成后，改变BOOT模式为“主闪存”,将引脚BOOT0 = 0;，此时接上开发板调试串口UART4就可以进行串口输出了。 + +![binflash](./img/bin_flash.png) \ No newline at end of file diff --git a/Ubiquitous/XiZi/board/gd32vf103_rvstar/board.c b/Ubiquitous/XiZi/board/gd32vf103_rvstar/board.c new file mode 100755 index 0000000..da07772 --- /dev/null +++ b/Ubiquitous/XiZi/board/gd32vf103_rvstar/board.c @@ -0,0 +1,86 @@ +/* +* Copyright (c) 2020 AIIT XUOS Lab +* XiUOS is licensed under Mulan PSL v2. +* You can use this software according to the terms and conditions of the Mulan PSL v2. +* You may obtain a copy of Mulan PSL v2 at: +* http://license.coscl.org.cn/MulanPSL2 +* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, +* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, +* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. +* See the Mulan PSL v2 for more details. +*/ + +/** +* @file board.c +* @brief support rvstar init configure and start-up +* @version 1.0 +* @author AIIT XUOS Lab +* @date 2021-09-02 +*/ + +#include +#include +#include +#include +// #include +#include + +extern void entry(void); +extern int InitHwUart(); + +#ifndef configKERNEL_INTERRUPT_PRIORITY +#define configKERNEL_INTERRUPT_PRIORITY 0 +#endif + +void xPortTaskSwitch(void) +{ + /* Clear Software IRQ, A MUST */ + SysTimer_ClearSWIRQ(); + isrManager.done->setSwitchTrigerFlag(); +} + +void vPortSetupTimerInterrupt(void) +{ + uint64_t ticks = SYSTICK_TICK_CONST; + + /* Make SWI and SysTick the lowest priority interrupts. */ + /* Stop and clear the SysTimer. SysTimer as Non-Vector Interrupt */ + SysTick_Config(ticks); + ECLIC_DisableIRQ(SysTimer_IRQn); + ECLIC_SetLevelIRQ(SysTimer_IRQn, configKERNEL_INTERRUPT_PRIORITY); + ECLIC_SetShvIRQ(SysTimer_IRQn, ECLIC_NON_VECTOR_INTERRUPT); + ECLIC_EnableIRQ(SysTimer_IRQn); + + /* Set SWI interrupt level to lowest level/priority, SysTimerSW as Vector Interrupt */ + ECLIC_SetShvIRQ(SysTimerSW_IRQn, ECLIC_VECTOR_INTERRUPT); + ECLIC_SetLevelIRQ(SysTimerSW_IRQn, configKERNEL_INTERRUPT_PRIORITY); + ECLIC_EnableIRQ(SysTimerSW_IRQn); +} + +void Gd32vf103Start(void) +{ + entry(); +} +void InitBoardHardware(void) +{ + + vPortSetupTimerInterrupt(); + + + InitBoardMemory(MEMORY_START_ADDRESS, MEMORY_END_ADDRESS); + + InitHwUart(); + InstallConsole("uart4", "uart4_drv", "uart4_dev4"); + + KPrintf("console init completed.\n"); + KPrintf("board initialization......\n"); + + // InitHwTick(); + KPrintf("memory address range: [0x%08x - 0x%08x], size: %d\n", (x_ubase) MEMORY_START_ADDRESS, (x_ubase) MEMORY_END_ADDRESS, gd32vf103_SRAM_SIZE); + /* initialize memory system */ + + KPrintf("board init done.\n"); + KPrintf("start kernel...\n"); + return; +} + diff --git a/Ubiquitous/XiZi/board/gd32vf103_rvstar/board.h b/Ubiquitous/XiZi/board/gd32vf103_rvstar/board.h new file mode 100755 index 0000000..fee208c --- /dev/null +++ b/Ubiquitous/XiZi/board/gd32vf103_rvstar/board.h @@ -0,0 +1,67 @@ +/* +* Copyright (c) 2020 AIIT XUOS Lab +* XiUOS is licensed under Mulan PSL v2. +* You can use this software according to the terms and conditions of the Mulan PSL v2. +* You may obtain a copy of Mulan PSL v2 at: +* http://license.coscl.org.cn/MulanPSL2 +* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, +* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, +* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. +* See the Mulan PSL v2 for more details. +*/ + +/** +* @file board.h +* @brief define rvstar-board init configure and start-up function +* @version 1.0 +* @author AIIT XUOS Lab +* @date 2021-09-02 +*/ + +/************************************************* +File name: board.h +Description: define rvstar-board init configure and start-up function +Others: +History: +1. Date: 2021-09-02 +Author: AIIT XUOS Lab +Modification: +1. define rvstar-board InitBoardHardware +2. define rvstar-board data and bss struct +*************************************************/ +#ifndef BOARD_H__ +#define BOARD_H__ + +#include +#include + +#ifndef __ASSEMBLY__ + +#undef EXTERN +#if defined(__cplusplus) +#define EXTERN extern "C" +extern "C" +{ +#else +#define EXTERN extern +#endif + +extern unsigned int __bss_start__; +extern unsigned int __bss_end__; +extern unsigned int _end; +extern unsigned int __stack_end__; +extern unsigned int g_service_table_start; +extern unsigned int g_service_table_end; + +#define MEMORY_START_ADDRESS (void*)(&_end) +#define gd32vf103_SRAM_SIZE 0x00008000 +#define MEMORY_END_ADDRESS (void*)(0x20000000 + gd32vf103_SRAM_SIZE) + + +#undef EXTERN +#if defined(__cplusplus) +} +#endif +#endif + +#endif diff --git a/Ubiquitous/XiZi/board/gd32vf103_rvstar/config.mk b/Ubiquitous/XiZi/board/gd32vf103_rvstar/config.mk new file mode 100755 index 0000000..1c9b175 --- /dev/null +++ b/Ubiquitous/XiZi/board/gd32vf103_rvstar/config.mk @@ -0,0 +1,18 @@ + +export CFLAGS := -march=rv32imac -mabi=ilp32 -fno-common -ffunction-sections -fdata-sections -O0 -ggdb -fgnu89-inline -Werror +export AFLAGS := -march=rv32imac -mabi=ilp32 -x assembler-with-cpp -ggdb +export LFLAGS := -march=rv32imac -mabi=ilp32 -nostartfiles -Wl,--gc-sections,-Map=XiZi_gd32vf103.map,-cref,-u,_start -T $(BSP_ROOT)/link.lds + +export APPLFLAGS := -nostartfiles -Wl,--gc-sections,-Map=XiZi_app.map,-cref,-u, -T $(BSP_ROOT)/link_userspace.lds + +export CXXFLAGS := -fno-common -ffunction-sections -fdata-sections -fstrict-volatile-bitfields -O0 -ggdb -Werror + +export CROSS_COMPILE ?=/opt/Nuclei/gcc/bin/riscv-nuclei-elf- + +export DEFINES := -DHAVE_CCONFIG_H -DHAVE_SIGINFO + +export ARCH = risc-v +export MCU = GD32VF103 + + + diff --git a/Ubiquitous/XiZi/board/gd32vf103_rvstar/gd32vf103v_rvstar.c b/Ubiquitous/XiZi/board/gd32vf103_rvstar/gd32vf103v_rvstar.c new file mode 100755 index 0000000..f606453 --- /dev/null +++ b/Ubiquitous/XiZi/board/gd32vf103_rvstar/gd32vf103v_rvstar.c @@ -0,0 +1,200 @@ +/*! + * \file gd32vf103c_start.c + * \brief firmware functions to manage leds, keys, COM ports + * + * \version 2020-02-05, V1.0.0, rvstar board functions for GD32VF103 + */ + +/** +* @file gd32vf103_rvstar.c +* @brief add from nuclei SDK +* https://github.com/Nuclei-Software/nuclei-sdk +* @version 1.1 +* @author AIIT XUOS Lab +* @date 2021-12-03 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include "gd32vf103v_rvstar.h" + +// /* private variables */ +// static const uint32_t GPIO_PORT[LEDn] = {LEDG_GPIO_PORT, LEDB_GPIO_PORT, LEDR_GPIO_PORT}; + +// static const uint32_t GPIO_PIN[LEDn] = {LEDG_PIN, LEDB_PIN, LEDR_PIN}; + +// static const rcu_periph_enum GPIO_CLK[LEDn] = {LEDG_GPIO_CLK, LEDB_GPIO_CLK, LEDR_GPIO_CLK}; + +// static const uint32_t KEY_PORT[KEYn] = {WAKEUP_KEY_GPIO_PORT}; + +// static const uint32_t KEY_PIN[KEYn] = {WAKEUP_KEY_PIN}; + +// static const rcu_periph_enum KEY_CLK[KEYn] = {WAKEUP_KEY_GPIO_CLK}; + +// static const exti_line_enum KEY_EXTI_LINE[KEYn] = {WAKEUP_KEY_EXTI_LINE}; + +// static const uint8_t KEY_PORT_SOURCE[KEYn] = {WAKEUP_KEY_EXTI_PORT_SOURCE}; + +// static const uint8_t KEY_PIN_SOURCE[KEYn] = {WAKEUP_KEY_EXTI_PIN_SOURCE}; + +// static const uint8_t KEY_IRQn[KEYn] = {WAKEUP_KEY_EXTI_IRQn}; + +/* eval board low layer private functions */ +/*! + * \brief configure led GPIO + * \param[in] lednum: specify the led to be configured + * \arg LED1 + * \param[out] none + * \retval none + */ +// void gd_led_init(led_typedef_enum lednum) +// { +// /* enable the led clock */ +// rcu_periph_clock_enable(GPIO_CLK[lednum]); +// /* configure led GPIO port */ +// gpio_init(GPIO_PORT[lednum], GPIO_MODE_OUT_PP, GPIO_OSPEED_50MHZ, GPIO_PIN[lednum]); +// GPIO_BOP(GPIO_PORT[lednum]) = GPIO_PIN[lednum]; +// } + +/*! + * \brief turn on selected led + * \param[in] lednum: specify the led to be turned on + * \arg LED1 + * \param[out] none + * \retval none + */ +// void gd_led_on(led_typedef_enum lednum) +// { +// GPIO_BC(GPIO_PORT[lednum]) = GPIO_PIN[lednum]; +// } + +/*! + * \brief turn off selected led + * \param[in] lednum: specify the led to be turned off + * \arg LED1 + * \param[out] none + * \retval none + */ +// void gd_led_off(led_typedef_enum lednum) +// { +// GPIO_BOP(GPIO_PORT[lednum]) = GPIO_PIN[lednum]; +// } + +/*! + * \brief toggle selected led + * \param[in] lednum: specify the led to be toggled + * \arg LED1 + * \param[out] none + * \retval none + */ +// void gd_led_toggle(led_typedef_enum lednum) +// { +// gpio_bit_write(GPIO_PORT[lednum], GPIO_PIN[lednum], +// (bit_status)(1 - gpio_input_bit_get(GPIO_PORT[lednum], GPIO_PIN[lednum]))); +// } + +/*! + * \brief configure key + * \param[in] keynum: specify the key to be configured + * \arg KEY_WAKEUP: wakeup key + * \param[in] keymode: specify button mode + * \arg KEY_MODE_GPIO: key will be used as simple IO + * \arg KEY_MODE_EXTI: key will be connected to EXTI line with interrupt + * \param[out] none + * \retval none + */ +// void gd_key_init(key_typedef_enum keynum, keymode_typedef_enum keymode) +// { +// /* enable the key clock */ +// rcu_periph_clock_enable(KEY_CLK[keynum]); +// rcu_periph_clock_enable(RCU_AF); + +// /* configure button pin as input */ +// gpio_init(KEY_PORT[keynum], GPIO_MODE_IN_FLOATING, GPIO_OSPEED_50MHZ, KEY_PIN[keynum]); + +// if (keymode == KEY_MODE_EXTI) { +// /* enable and set key EXTI interrupt to the lowest priority */ +// ECLIC_EnableIRQ(KEY_IRQn[keynum]); +// ECLIC_SetLevelIRQ(KEY_IRQn[keynum], 1); +// ECLIC_SetPriorityIRQ(KEY_IRQn[keynum], 1); + +// /* connect key EXTI line to key GPIO pin */ +// gpio_exti_source_select(KEY_PORT_SOURCE[keynum], KEY_PIN_SOURCE[keynum]); + +// /* configure key EXTI line */ +// exti_init(KEY_EXTI_LINE[keynum], EXTI_INTERRUPT, EXTI_TRIG_FALLING); +// exti_interrupt_flag_clear(KEY_EXTI_LINE[keynum]); +// } +// } + +/*! + * \brief return the selected key state + * \param[in] keynum: specify the key to be checked + * \arg KEY_WAKEUP: wakeup key + * \param[out] none + * \retval the key's GPIO pin value + */ +// uint8_t gd_key_state_get(key_typedef_enum keynum) +// { +// return gpio_input_bit_get(KEY_PORT[keynum], KEY_PIN[keynum]); +// } + +/*! + * \brief configure COM port + * \param[in] com: COM on the board + * \arg GD32_COM0: COM0 on the board + * \param[out] none + * \retval none + */ +void gd_com_init(uint32_t usart_periph) +{ + /* enable GPIO TX and RX clock */ + rcu_periph_clock_enable(GD32_COM_TX_GPIO_CLK); + rcu_periph_clock_enable(GD32_COM_RX_GPIO_CLK); + + /* enable USART clock */ + rcu_periph_clock_enable(GD32_COM_CLK); + + /* connect port to USARTx_Tx */ + gpio_init(GD32_COM_TX_GPIO_PORT, GPIO_MODE_AF_PP, GPIO_OSPEED_50MHZ, GD32_COM_TX_PIN); + + /* connect port to USARTx_Rx */ + gpio_init(GD32_COM_RX_GPIO_PORT, GPIO_MODE_IN_FLOATING, GPIO_OSPEED_50MHZ, GD32_COM_RX_PIN); + + /* USART configure */ + usart_deinit(usart_periph); + usart_baudrate_set(usart_periph, 115200U); + usart_word_length_set(usart_periph, USART_WL_8BIT); + usart_stop_bit_set(usart_periph, USART_STB_1BIT); + usart_parity_config(usart_periph, USART_PM_NONE); + usart_hardware_flow_rts_config(usart_periph, USART_RTS_DISABLE); + usart_hardware_flow_cts_config(usart_periph, USART_CTS_DISABLE); + usart_receive_config(usart_periph, USART_RECEIVE_ENABLE); + usart_transmit_config(usart_periph, USART_TRANSMIT_ENABLE); + usart_enable(usart_periph); +} diff --git a/Ubiquitous/XiZi/board/gd32vf103_rvstar/gd32vf103v_rvstar.h b/Ubiquitous/XiZi/board/gd32vf103_rvstar/gd32vf103v_rvstar.h new file mode 100755 index 0000000..7ac21d8 --- /dev/null +++ b/Ubiquitous/XiZi/board/gd32vf103_rvstar/gd32vf103v_rvstar.h @@ -0,0 +1,131 @@ +/*! + \file gd32vf103c_start.h + \brief definitions for GD32VF103C_START's leds, keys and COM ports hardware resources + + \version 2019-06-05, V1.0.0, demo for GD32VF103 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef GD32VF103C_RVSTART_H +#define GD32VF103C_RVSTART_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include "nuclei_sdk_soc.h" + +/* exported types */ +typedef enum { + LED1 = 0, + LED2 = 1, + LED3 = 2, + LED_1 = 0, + LED_2 = 1, + LED_3 = 2 +} led_typedef_enum; + +typedef enum { + KEY_WAKEUP = 0, +} key_typedef_enum; + +typedef enum { + KEY_MODE_GPIO = 0, + KEY_MODE_EXTI = 1 +} keymode_typedef_enum; + + +// /* rvstar board low layer led */ +// #define LEDn 3U + +// #define LEDG_PIN GPIO_PIN_1 +// #define LEDG_GPIO_PORT GPIOA +// #define LEDG_GPIO_CLK RCU_GPIOA + +// #define LEDB_PIN GPIO_PIN_3 +// #define LEDB_GPIO_PORT GPIOA +// #define LEDB_GPIO_CLK RCU_GPIOA + +// #define LEDR_PIN GPIO_PIN_2 +// #define LEDR_GPIO_PORT GPIOA +// #define LEDR_GPIO_CLK RCU_GPIOA + +/* rvstar board UART com port */ +#define GD32_COM0 UART4 +#define GD32_COM_CLK RCU_UART4 +#define GD32_COM_TX_PIN GPIO_PIN_12 +#define GD32_COM_RX_PIN GPIO_PIN_2 +#define GD32_COM_TX_GPIO_PORT GPIOC +#define GD32_COM_RX_GPIO_PORT GPIOD +#define GD32_COM_TX_GPIO_CLK RCU_GPIOC +#define GD32_COM_RX_GPIO_CLK RCU_GPIOD + +/* rvstar board low layer button */ +#define KEYn (1U) + +/* wakeup push-button */ +#define WAKEUP_KEY_PIN GPIO_PIN_0 +#define WAKEUP_KEY_GPIO_PORT GPIOA +#define WAKEUP_KEY_GPIO_CLK RCU_GPIOA +#define WAKEUP_KEY_EXTI_LINE EXTI_0 +#define WAKEUP_KEY_EXTI_PORT_SOURCE GPIO_PORT_SOURCE_GPIOA +#define WAKEUP_KEY_EXTI_PIN_SOURCE GPIO_PIN_SOURCE_0 +#define WAKEUP_KEY_EXTI_IRQn EXTI0_IRQn + +/* function declarations */ +/* configure led GPIO */ +void gd_led_init(led_typedef_enum lednum); +/* turn on selected led */ +void gd_led_on(led_typedef_enum lednum); +/* turn off selected led */ +void gd_led_off(led_typedef_enum lednum); +/* toggle the selected led */ +void gd_led_toggle(led_typedef_enum lednum); +/* configure key */ +void gd_key_init(key_typedef_enum keynum, keymode_typedef_enum keymode); +/* return the selected key state */ +uint8_t gd_key_state_get(key_typedef_enum keynum); +/* configure COM port */ +void gd_com_init(uint32_t usart_periph); + +/* Defines for LED functions to new / general API */ +#define gd_rvstar_led_init gd_led_init +#define gd_rvstar_led_on gd_led_on +#define gd_rvstar_led_off gd_led_off +#define gd_rvstar_led_toggle gd_led_toggle + +#define gd_rvstar_key_init gd_key_init +#define gd_rvstar_key_state_get gd_key_state_get + +#ifdef __cplusplus +} +#endif + +#endif /* GD32VF103V_RVSTART_H */ + diff --git a/Ubiquitous/XiZi/board/gd32vf103_rvstar/img/GigaDevice.png b/Ubiquitous/XiZi/board/gd32vf103_rvstar/img/GigaDevice.png new file mode 100644 index 0000000..44d32e6 Binary files /dev/null and b/Ubiquitous/XiZi/board/gd32vf103_rvstar/img/GigaDevice.png differ diff --git a/Ubiquitous/XiZi/board/gd32vf103_rvstar/img/ISP_support_usart.png b/Ubiquitous/XiZi/board/gd32vf103_rvstar/img/ISP_support_usart.png new file mode 100644 index 0000000..80e4944 Binary files /dev/null and b/Ubiquitous/XiZi/board/gd32vf103_rvstar/img/ISP_support_usart.png differ diff --git a/Ubiquitous/XiZi/board/gd32vf103_rvstar/img/bin_flash.png b/Ubiquitous/XiZi/board/gd32vf103_rvstar/img/bin_flash.png new file mode 100644 index 0000000..8906efb Binary files /dev/null and b/Ubiquitous/XiZi/board/gd32vf103_rvstar/img/bin_flash.png differ diff --git a/Ubiquitous/XiZi/board/gd32vf103_rvstar/img/boot_mode.png b/Ubiquitous/XiZi/board/gd32vf103_rvstar/img/boot_mode.png new file mode 100644 index 0000000..358f0ca Binary files /dev/null and b/Ubiquitous/XiZi/board/gd32vf103_rvstar/img/boot_mode.png differ diff --git a/Ubiquitous/XiZi/board/gd32vf103_rvstar/img/gdb_load.png b/Ubiquitous/XiZi/board/gd32vf103_rvstar/img/gdb_load.png new file mode 100644 index 0000000..854815a Binary files /dev/null and b/Ubiquitous/XiZi/board/gd32vf103_rvstar/img/gdb_load.png differ diff --git a/Ubiquitous/XiZi/board/gd32vf103_rvstar/img/menuconfig.png b/Ubiquitous/XiZi/board/gd32vf103_rvstar/img/menuconfig.png new file mode 100644 index 0000000..1834232 Binary files /dev/null and b/Ubiquitous/XiZi/board/gd32vf103_rvstar/img/menuconfig.png differ diff --git a/Ubiquitous/XiZi/board/gd32vf103_rvstar/img/openocd.png b/Ubiquitous/XiZi/board/gd32vf103_rvstar/img/openocd.png new file mode 100644 index 0000000..356b725 Binary files /dev/null and b/Ubiquitous/XiZi/board/gd32vf103_rvstar/img/openocd.png differ diff --git a/Ubiquitous/XiZi/board/gd32vf103_rvstar/img/riscv_gnu.png b/Ubiquitous/XiZi/board/gd32vf103_rvstar/img/riscv_gnu.png new file mode 100644 index 0000000..f065e9f Binary files /dev/null and b/Ubiquitous/XiZi/board/gd32vf103_rvstar/img/riscv_gnu.png differ diff --git a/Ubiquitous/XiZi/board/gd32vf103_rvstar/img/terminal.png b/Ubiquitous/XiZi/board/gd32vf103_rvstar/img/terminal.png new file mode 100644 index 0000000..602810b Binary files /dev/null and b/Ubiquitous/XiZi/board/gd32vf103_rvstar/img/terminal.png differ diff --git a/Ubiquitous/XiZi/board/gd32vf103_rvstar/img/vscode.jpg b/Ubiquitous/XiZi/board/gd32vf103_rvstar/img/vscode.jpg new file mode 100644 index 0000000..b9bacff Binary files /dev/null and b/Ubiquitous/XiZi/board/gd32vf103_rvstar/img/vscode.jpg differ diff --git a/Ubiquitous/XiZi/board/gd32vf103_rvstar/link.lds b/Ubiquitous/XiZi/board/gd32vf103_rvstar/link.lds new file mode 100755 index 0000000..e277a00 --- /dev/null +++ b/Ubiquitous/XiZi/board/gd32vf103_rvstar/link.lds @@ -0,0 +1,299 @@ +/* + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +/****************************************************************************** + * @file gcc_Device.ld + * @brief GNU Linker Script for gd32vf103 based device + * @version V1.0.0 + * @date 17. Dec 2019 + ******************************************************************************/ + +/*********** Use Configuration Wizard in Context Menu *************************/ + +OUTPUT_ARCH( "riscv" ) +/********************* Flash Configuration ************************************ + * Flash Configuration + * Flash Base Address <0x0-0xFFFFFFFF:8> + * Flash Size (in Bytes) <0x0-0xFFFFFFFF:8> + * + */ +__ROM_BASE = 0x08000000; +__ROM_SIZE = 0x00020000; + +/*--------------------- ILM RAM Configuration --------------------------- + * ILM RAM Configuration + * ILM RAM Base Address <0x0-0xFFFFFFFF:8> + * ILM RAM Size (in Bytes) <0x0-0xFFFFFFFF:8> + * + */ +__ILM_RAM_BASE = 0x80000000; +__ILM_RAM_SIZE = 0x00010000; + +/*--------------------- Embedded RAM Configuration --------------------------- + * RAM Configuration + * RAM Base Address <0x0-0xFFFFFFFF:8> + * RAM Size (in Bytes) <0x0-0xFFFFFFFF:8> + * +*/ +__RAM_BASE = 0x20000000; +__RAM_SIZE = 0x00005000; + +/********************* Stack / Heap Configuration **************************** + * Stack / Heap Configuration + * Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> + * Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> + * + */ +__STACK_SIZE = 0x00000800; +__HEAP_SIZE = 0x00000800; + +/**************************** end of configuration section ********************/ + +/* Define base address and length of flash and ram */ +MEMORY +{ + flash (rxai!w) : ORIGIN = __ROM_BASE, LENGTH = __ROM_SIZE + ram (wxa!ri) : ORIGIN = __RAM_BASE, LENGTH = __RAM_SIZE +} +/* Linker script to place sections and symbol values. Should be used together + * with other linker script that defines memory regions FLASH,ILM and RAM. + * It references following symbols, which must be defined in code: + * _Start : Entry of reset handler + * + * It defines following symbols, which code can use without definition: + * _ilm_lma + * _ilm + * __etext + * _etext + * etext + * _eilm + * __preinit_array_start + * __preinit_array_end + * __init_array_start + * __init_array_end + * __fini_array_start + * __fini_array_end + * _data_lma + * _edata + * edata + * __data_end__ + * __bss_start + * __fbss + * _end + * end + * __heap_end + * __StackLimit + * __StackTop + * __STACK_SIZE + */ +/* Define entry label of program */ +ENTRY(_start) +SECTIONS +{ + __STACK_SIZE = DEFINED(__STACK_SIZE) ? __STACK_SIZE : 2K; + + .init : + { + /* vector table locate at flash */ + *(.vtable) + KEEP (*(SORT_NONE(.init))) + } >flash AT>flash + + .ilalign : + { + . = ALIGN(4); + /* Create a section label as _ilm_lma which located at flash */ + PROVIDE( _ilm_lma = . ); + } >flash AT>flash + + .ialign : + { + /* Create a section label as _ilm which located at flash */ + PROVIDE( _ilm = . ); + } >flash AT>flash + + /* Code section located at flash */ + .text : + { + *(.text.unlikely .text.unlikely.*) + *(.text.startup .text.startup.*) + *(.text .text.*) + /* section information for shell */ + . = ALIGN(4); + _shell_command_start = .; + KEEP (*(shellCommand)) + _shell_command_end = .; + . = ALIGN(4); + + PROVIDE(__ctors_start__ = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array)) + PROVIDE(__ctors_end__ = .); + + . = ALIGN(4); + __isrtbl_idx_start = .; + KEEP(*(.isrtbl.idx)) + __isrtbl_start = .; + KEEP(*(.isrtbl)) + __isrtbl_end = .; + . = ALIGN(4); + + PROVIDE(g_service_table_start = ABSOLUTE(.)); + KEEP(*(.g_service_table)) + PROVIDE(g_service_table_end = ABSOLUTE(.)); + + *(.gnu.linkonce.t.*) + } >flash AT>flash + + .rodata : ALIGN(4) + { + . = ALIGN(4); + *(.rdata) + *(.rodata .rodata.*) + /* section information for initial. */ + . = ALIGN(4); + + *(.gnu.linkonce.r.*) + . = ALIGN(8); + *(.srodata.cst16) + *(.srodata.cst8) + *(.srodata.cst4) + *(.srodata.cst2) + *(.srodata .srodata.*) + } >flash AT>flash + + .fini : + { + KEEP (*(SORT_NONE(.fini))) + } >flash AT>flash + + . = ALIGN(4); + + PROVIDE (__etext = .); + PROVIDE (_etext = .); + PROVIDE (etext = .); + PROVIDE( _eilm = . ); + + + .preinit_array : + { + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array)) + PROVIDE_HIDDEN (__preinit_array_end = .); + } >flash AT>flash + + .init_array : + { + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*))) + KEEP (*(.init_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .ctors)) + PROVIDE_HIDDEN (__init_array_end = .); + } >flash AT>flash + + .fini_array : + { + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT_BY_INIT_PRIORITY(.fini_array.*) SORT_BY_INIT_PRIORITY(.dtors.*))) + KEEP (*(.fini_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .dtors)) + PROVIDE_HIDDEN (__fini_array_end = .); + } >flash AT>flash + + .ctors : + { + /* gcc uses crtbegin.o to find the start of + * the constructors, so we make sure it is + * first. Because this is a wildcard, it + * doesn't matter if the user does not + * actually link against crtbegin.o; the + * linker won't look for a file to match a + * wildcard. The wildcard also means that it + * doesn't matter which directory crtbegin.o + * is in. + */ + KEEP (*crtbegin.o(.ctors)) + KEEP (*crtbegin?.o(.ctors)) + /* We don't want to include the .ctor section from + * the crtend.o file until after the sorted ctors. + * The .ctor section from the crtend file contains the + * end of ctors marker and it must be last + */ + KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*(.ctors)) + } >flash AT>flash + + .dtors : + { + KEEP (*crtbegin.o(.dtors)) + KEEP (*crtbegin?.o(.dtors)) + KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*(.dtors)) + } >flash AT>flash + + .lalign : + { + . = ALIGN(4); + PROVIDE( _data_lma = . ); + } >flash AT>flash + + .dalign : + { + . = ALIGN(4); + PROVIDE( _data = . ); + } >ram AT>flash + + /* Define data section virtual address is ram and physical address is flash */ + .data : + { + *(.data .data.*) + *(.gnu.linkonce.d.*) + . = ALIGN(8); + PROVIDE( __global_pointer$ = . + 0x800 ); + *(.sdata .sdata.* .sdata*) + *(.gnu.linkonce.s.*) + } >ram AT>flash + + . = ALIGN(4); + PROVIDE( _edata = . ); + PROVIDE( edata = . ); + + PROVIDE( _fbss = . ); + PROVIDE( __bss_start = . ); + .bss : + { + *(.sbss*) + *(.gnu.linkonce.sb.*) + *(.bss .bss.*) + *(.gnu.linkonce.b.*) + *(COMMON) + . = ALIGN(4); + } >ram AT>ram + + . = ALIGN(8); + + /* Define stack and head location at ram */ + .stack : + { + . = . + __STACK_SIZE; + PROVIDE( _sp = . ); + } >ram AT>ram + + PROVIDE( _end = . ); + PROVIDE( end = . ); + +} diff --git a/Ubiquitous/XiZi/board/gd32vf103_rvstar/nuclei_sdk_hal.h b/Ubiquitous/XiZi/board/gd32vf103_rvstar/nuclei_sdk_hal.h new file mode 100755 index 0000000..5f5a6c0 --- /dev/null +++ b/Ubiquitous/XiZi/board/gd32vf103_rvstar/nuclei_sdk_hal.h @@ -0,0 +1,20 @@ +// See LICENSE for license details. +#ifndef _NUCLEI_SDK_HAL_H +#define _NUCLEI_SDK_HAL_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include "gd32vf103v_rvstar.h" + +#define SOC_DEBUG_UART GD32_COM0 + +#ifndef NUCLEI_BANNER +#define NUCLEI_BANNER 1 +#endif + +#ifdef __cplusplus +} +#endif +#endif diff --git a/Ubiquitous/XiZi/board/gd32vf103_rvstar/nuclei_sdk_soc.h b/Ubiquitous/XiZi/board/gd32vf103_rvstar/nuclei_sdk_soc.h new file mode 100755 index 0000000..d247cac --- /dev/null +++ b/Ubiquitous/XiZi/board/gd32vf103_rvstar/nuclei_sdk_soc.h @@ -0,0 +1,20 @@ +// See LICENSE for license details. +#ifndef _NUCLEI_SDK_SOC_H +#define _NUCLEI_SDK_SOC_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include "gd32vf103.h" +// #include "gd32vf103_libopt.h" +#include "gd32vf103_rcu.h" +#include "gd32vf103_gpio.h" +#include "gd32vf103_usart.h" +#include "gd32vf103_timer.h" + + +#ifdef __cplusplus +} +#endif +#endif diff --git a/Ubiquitous/XiZi/board/gd32vf103_rvstar/third_party_driver/Kconfig b/Ubiquitous/XiZi/board/gd32vf103_rvstar/third_party_driver/Kconfig new file mode 100755 index 0000000..cee6d37 --- /dev/null +++ b/Ubiquitous/XiZi/board/gd32vf103_rvstar/third_party_driver/Kconfig @@ -0,0 +1,25 @@ +menuconfig BSP_USING_GPIO + bool "Using GPIO device" + default y + select RESOURCES_PIN + if BSP_USING_GPIO + source "$BSP_DIR/third_party_driver/gpio/Kconfig" + endif + +menuconfig BSP_USING_SYSCLOCK + bool "Using SYSCLOCK device" + default y + if BSP_USING_SYSCLOCK + source "$BSP_DIR/third_party_driver/sys_clock/Kconfig" + endif + +menuconfig BSP_USING_UART + bool "Using UART device" + default y + select RESOURCES_SERIAL + if BSP_USING_UART + source "$BSP_DIR/third_party_driver/uart/Kconfig" + endif + + + \ No newline at end of file diff --git a/Ubiquitous/XiZi/board/gd32vf103_rvstar/third_party_driver/Makefile b/Ubiquitous/XiZi/board/gd32vf103_rvstar/third_party_driver/Makefile new file mode 100755 index 0000000..48eef19 --- /dev/null +++ b/Ubiquitous/XiZi/board/gd32vf103_rvstar/third_party_driver/Makefile @@ -0,0 +1,17 @@ +SRC_FILES := system_gd32vf103.c +SRC_DIR := + +ifeq ($(CONFIG_BSP_USING_GPIO),y) + SRC_DIR += gpio +endif + +ifeq ($(CONFIG_BSP_USING_SYSCLOCK),y) + SRC_DIR += sys_clock +endif + +ifeq ($(CONFIG_BSP_USING_UART),y) + SRC_DIR += uart +endif + + +include $(KERNEL_ROOT)/compiler.mk diff --git a/Ubiquitous/XiZi/board/gd32vf103_rvstar/third_party_driver/gpio/Kconfig b/Ubiquitous/XiZi/board/gd32vf103_rvstar/third_party_driver/gpio/Kconfig new file mode 100755 index 0000000..35dce73 --- /dev/null +++ b/Ubiquitous/XiZi/board/gd32vf103_rvstar/third_party_driver/gpio/Kconfig @@ -0,0 +1,11 @@ +config PIN_BUS_NAME + string "pin bus name" + default "pin" + +config PIN_DRIVER_NAME + string "pin driver name" + default "pin_drv" + +config PIN_DEVICE_NAME + string "pin device name" + default "pin_dev" diff --git a/Ubiquitous/XiZi/board/gd32vf103_rvstar/third_party_driver/gpio/Makefile b/Ubiquitous/XiZi/board/gd32vf103_rvstar/third_party_driver/gpio/Makefile new file mode 100755 index 0000000..e364e40 --- /dev/null +++ b/Ubiquitous/XiZi/board/gd32vf103_rvstar/third_party_driver/gpio/Makefile @@ -0,0 +1,3 @@ +SRC_FILES := gd32vf103_gpio.c + +include $(KERNEL_ROOT)/compiler.mk diff --git a/Ubiquitous/XiZi/board/gd32vf103_rvstar/third_party_driver/include/connect_uart.h b/Ubiquitous/XiZi/board/gd32vf103_rvstar/third_party_driver/include/connect_uart.h new file mode 100755 index 0000000..fe141d1 --- /dev/null +++ b/Ubiquitous/XiZi/board/gd32vf103_rvstar/third_party_driver/include/connect_uart.h @@ -0,0 +1,38 @@ +/* +* Copyright (c) 2020 AIIT XUOS Lab +* XiUOS is licensed under Mulan PSL v2. +* You can use this software according to the terms and conditions of the Mulan PSL v2. +* You may obtain a copy of Mulan PSL v2 at: +* http://license.coscl.org.cn/MulanPSL2 +* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, +* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, +* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. +* See the Mulan PSL v2 for more details. +*/ + +/** +* @file connect_uart.h +* @brief define rvstar uart function +* @version 1.1 +* @author AIIT XUOS Lab +* @date 2021-12-03 +*/ + +#ifndef CONNECT_UART_H +#define CONNECT_UART_H + +#include + +#ifdef __cplusplus +extern "C" { +#endif + + + +int InitHwUart(void); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/Ubiquitous/XiZi/board/gd32vf103_rvstar/third_party_driver/uart/Kconfig b/Ubiquitous/XiZi/board/gd32vf103_rvstar/third_party_driver/uart/Kconfig new file mode 100755 index 0000000..6a9a7ae --- /dev/null +++ b/Ubiquitous/XiZi/board/gd32vf103_rvstar/third_party_driver/uart/Kconfig @@ -0,0 +1,14 @@ +menuconfig BSP_USING_UART4 + bool "Enable UART4" + default y + if BSP_USING_UART4 + config SERIAL_BUS_NAME_4 + string "serial bus name" + default "uart4" + config SERIAL_DRV_NAME_4 + string "serial bus driver name" + default "uart4_drv" + config SERIAL_4_DEVICE_NAME_4 + string "serial bus device name" + default "uart4_dev4" + endif diff --git a/Ubiquitous/XiZi/board/gd32vf103_rvstar/third_party_driver/uart/Makefile b/Ubiquitous/XiZi/board/gd32vf103_rvstar/third_party_driver/uart/Makefile new file mode 100755 index 0000000..9a3985b --- /dev/null +++ b/Ubiquitous/XiZi/board/gd32vf103_rvstar/third_party_driver/uart/Makefile @@ -0,0 +1,4 @@ +SRC_FILES := connect_uart.c gd32vf103_usart.c + + +include $(KERNEL_ROOT)/compiler.mk diff --git a/Ubiquitous/XiZi/board/gd32vf103_rvstar/third_party_driver/uart/connect_uart.c b/Ubiquitous/XiZi/board/gd32vf103_rvstar/third_party_driver/uart/connect_uart.c new file mode 100755 index 0000000..833b890 --- /dev/null +++ b/Ubiquitous/XiZi/board/gd32vf103_rvstar/third_party_driver/uart/connect_uart.c @@ -0,0 +1,377 @@ +/* +* Copyright (c) 2020 AIIT XUOS Lab +* XiUOS is licensed under Mulan PSL v2. +* You can use this software according to the terms and conditions of the Mulan PSL v2. +* You may obtain a copy of Mulan PSL v2 at: +* http://license.coscl.org.cn/MulanPSL2 +* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, +* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, +* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. +* See the Mulan PSL v2 for more details. +*/ + +/** +* @file connect_usart.c +* @brief supportrvstar-board uart function and register to bus framework +* @version 1.1 +* @author AIIT XUOS Lab +* @date 2021-12-03 +*/ + +#include +#include + +#include "connect_uart.h" +#include "gd32vf103_usart.h" +#include "gd32vf103.h" +#include + +static void SerialCfgParamCheck(struct SerialCfgParam *serial_cfg_default, struct SerialCfgParam *serial_cfg_new) +{ + struct SerialDataCfg *data_cfg_default = &serial_cfg_default->data_cfg; + struct SerialDataCfg *data_cfg_new = &serial_cfg_new->data_cfg; + + if ((data_cfg_default->serial_baud_rate != data_cfg_new->serial_baud_rate) && (data_cfg_new->serial_baud_rate)) { + data_cfg_default->serial_baud_rate = data_cfg_new->serial_baud_rate; + } + + if ((data_cfg_default->serial_bit_order != data_cfg_new->serial_bit_order) && (data_cfg_new->serial_bit_order)) { + data_cfg_default->serial_bit_order = data_cfg_new->serial_bit_order; + } + + if ((data_cfg_default->serial_buffer_size != data_cfg_new->serial_buffer_size) && (data_cfg_new->serial_buffer_size)) { + data_cfg_default->serial_buffer_size = data_cfg_new->serial_buffer_size; + } + + if ((data_cfg_default->serial_data_bits != data_cfg_new->serial_data_bits) && (data_cfg_new->serial_data_bits)) { + data_cfg_default->serial_data_bits = data_cfg_new->serial_data_bits; + } + + if ((data_cfg_default->serial_invert_mode != data_cfg_new->serial_invert_mode) && (data_cfg_new->serial_invert_mode)) { + data_cfg_default->serial_invert_mode = data_cfg_new->serial_invert_mode; + } + + if ((data_cfg_default->serial_parity_mode != data_cfg_new->serial_parity_mode) && (data_cfg_new->serial_parity_mode)) { + data_cfg_default->serial_parity_mode = data_cfg_new->serial_parity_mode; + } + + if ((data_cfg_default->serial_stop_bits != data_cfg_new->serial_stop_bits) && (data_cfg_new->serial_stop_bits)) { + data_cfg_default->serial_stop_bits = data_cfg_new->serial_stop_bits; + } +} + +static void UartIsr(struct SerialDriver *serial_drv, struct SerialHardwareDevice *serial_dev) +{ + struct SerialCfgParam *serial_cfg = (struct SerialCfgParam *)serial_drv->private_data; + + if ((usart_interrupt_flag_get(serial_cfg->hw_cfg.serial_register_base, USART_INT_FLAG_RBNE) + != RESET) + && (RESET != usart_flag_get(serial_cfg->hw_cfg.serial_register_base, USART_FLAG_RBNE))) + { + SerialSetIsr(serial_dev, SERIAL_EVENT_RX_IND); + usart_interrupt_flag_clear(serial_cfg->hw_cfg.serial_register_base, USART_INT_FLAG_RBNE); + usart_flag_clear(serial_cfg->hw_cfg.serial_register_base, USART_FLAG_RBNE); + } + else + { + if (usart_flag_get(serial_cfg->hw_cfg.serial_register_base, USART_FLAG_CTSF) != RESET) + { + usart_flag_clear(serial_cfg->hw_cfg.serial_register_base, USART_FLAG_CTSF); + } + + if (usart_flag_get(serial_cfg->hw_cfg.serial_register_base, USART_FLAG_LBDF) != RESET) + { + usart_flag_clear(serial_cfg->hw_cfg.serial_register_base, USART_FLAG_LBDF); + } + + if (usart_flag_get(serial_cfg->hw_cfg.serial_register_base, USART_FLAG_TC) != RESET) + { + usart_flag_clear(serial_cfg->hw_cfg.serial_register_base, USART_FLAG_TC); + } + } + +} + + +static uint32 SerialInit(struct SerialDriver *serial_drv, struct BusConfigureInfo *configure_info) +{ + NULL_PARAM_CHECK(serial_drv); + struct SerialCfgParam *serial_cfg = (struct SerialCfgParam *)serial_drv->private_data; + // struct UsartHwCfg *serial_hw_cfg = (struct UsartHwCfg *)serial_cfg->hw_cfg.private_data; + + + usart_deinit(serial_cfg->hw_cfg.serial_register_base); + usart_baudrate_set(serial_cfg->hw_cfg.serial_register_base, serial_cfg->data_cfg.serial_baud_rate); + + switch (serial_cfg->data_cfg.serial_data_bits) + { + case DATA_BITS_8: + usart_word_length_set(serial_cfg->hw_cfg.serial_register_base, USART_WL_8BIT); + break; + + case DATA_BITS_9: + usart_word_length_set(serial_cfg->hw_cfg.serial_register_base, USART_WL_9BIT); + break; + default: + usart_word_length_set(serial_cfg->hw_cfg.serial_register_base, USART_WL_8BIT); + break; + } + + switch (serial_cfg->data_cfg.serial_stop_bits) + { + case STOP_BITS_1: + usart_stop_bit_set(serial_cfg->hw_cfg.serial_register_base, USART_STB_1BIT); + break; + case STOP_BITS_2: + usart_stop_bit_set(serial_cfg->hw_cfg.serial_register_base, USART_STB_2BIT); + break; + default: + usart_stop_bit_set(serial_cfg->hw_cfg.serial_register_base, USART_STB_1BIT); + break; + } + + switch (serial_cfg->data_cfg.serial_parity_mode) + { + case PARITY_NONE: + usart_parity_config(serial_cfg->hw_cfg.serial_register_base, USART_PM_NONE); + break; + case PARITY_ODD: + usart_parity_config(serial_cfg->hw_cfg.serial_register_base, USART_PM_ODD); + break; + case PARITY_EVEN: + usart_parity_config(serial_cfg->hw_cfg.serial_register_base, USART_PM_EVEN); + break; + default: + usart_parity_config(serial_cfg->hw_cfg.serial_register_base, USART_PM_NONE); + break; + } + usart_hardware_flow_rts_config(serial_cfg->hw_cfg.serial_register_base, USART_RTS_DISABLE); + usart_hardware_flow_cts_config(serial_cfg->hw_cfg.serial_register_base, USART_CTS_DISABLE); + usart_receive_config(serial_cfg->hw_cfg.serial_register_base, USART_RECEIVE_ENABLE); + usart_transmit_config(serial_cfg->hw_cfg.serial_register_base, USART_TRANSMIT_ENABLE); + usart_enable(serial_cfg->hw_cfg.serial_register_base); + + + return EOK; +} + +static uint32 SerialConfigure(struct SerialDriver *serial_drv, int serial_operation_cmd) +{ + NULL_PARAM_CHECK(serial_drv); + + struct SerialCfgParam *serial_cfg = (struct SerialCfgParam *)serial_drv->private_data; + + switch (serial_operation_cmd) + { + case OPER_CLR_INT: + ECLIC_DisableIRQ(serial_cfg->hw_cfg.serial_irq_interrupt); + usart_interrupt_disable(serial_cfg->hw_cfg.serial_register_base, USART_INT_RBNE); + break; + case OPER_SET_INT: + ECLIC_EnableIRQ(serial_cfg->hw_cfg.serial_irq_interrupt); + /* enable USART0 receive interrupt */ + usart_interrupt_enable(serial_cfg->hw_cfg.serial_register_base, USART_INT_RBNE); + break; + } + + return EOK; +} + +static uint32 SerialDrvConfigure(void *drv, struct BusConfigureInfo *configure_info) +{ + NULL_PARAM_CHECK(drv); + NULL_PARAM_CHECK(configure_info); + + x_err_t ret = EOK; + int serial_operation_cmd; + struct SerialDriver *serial_drv = (struct SerialDriver *)drv; + + switch (configure_info->configure_cmd) + { + case OPE_INT: + ret = SerialInit(serial_drv, configure_info); + break; + case OPE_CFG: + serial_operation_cmd = *(int *)configure_info->private_data; + ret = SerialConfigure(serial_drv, serial_operation_cmd); + break; + default: + break; + } + + return ret; +} + +static int SerialPutChar(struct SerialHardwareDevice *serial_dev, char c) +{ + struct SerialCfgParam *serial_cfg = (struct SerialCfgParam *)serial_dev->private_data; + // struct UsartHwCfg *serial_hw_cfg = (struct UsartHwCfg *)serial_cfg->hw_cfg.private_data; + + usart_data_transmit(serial_cfg->hw_cfg.serial_register_base, (uint8_t) c); + while (usart_flag_get(serial_cfg->hw_cfg.serial_register_base, USART_FLAG_TBE) == RESET); + + return 0; +} + +static int SerialGetChar(struct SerialHardwareDevice *serial_dev) +{ + int ch = -1; + struct SerialCfgParam *serial_cfg = (struct SerialCfgParam *)serial_dev->private_data; + + if (RESET != usart_flag_get(serial_cfg->hw_cfg.serial_register_base, USART_FLAG_RBNE)) + { + ch = usart_data_receive(serial_cfg->hw_cfg.serial_register_base) & 0xff; + } + + return ch; +} + +static const struct SerialDataCfg data_cfg_init = +{ + .serial_baud_rate = BAUD_RATE_115200, + .serial_data_bits = DATA_BITS_8, + .serial_stop_bits = STOP_BITS_1, + .serial_parity_mode = PARITY_NONE, + .serial_bit_order = BIT_ORDER_LSB, + .serial_invert_mode = NRZ_NORMAL, + .serial_buffer_size = SERIAL_RB_BUFSZ, +}; + + + +/*manage the serial device operations*/ +static const struct SerialDrvDone drv_done = +{ + .init = SerialInit, + .configure = SerialConfigure, +}; + +/*manage the serial device hal operations*/ +static struct SerialHwDevDone hwdev_done = +{ + .put_char = SerialPutChar, + .get_char = SerialGetChar, +}; + +static int BoardSerialBusInit(struct SerialBus *serial_bus, struct SerialDriver *serial_driver, const char *bus_name, const char *drv_name) +{ + x_err_t ret = EOK; + + /*Init the serial bus */ + ret = SerialBusInit(serial_bus, bus_name); + if (EOK != ret) { + KPrintf("InitHwUart SerialBusInit error %d\n", ret); + return ERROR; + } + + /*Init the serial driver*/ + ret = SerialDriverInit(serial_driver, drv_name); + if (EOK != ret) { + KPrintf("InitHwUart SerialDriverInit error %d\n", ret); + return ERROR; + } + + /*Attach the serial driver to the serial bus*/ + ret = SerialDriverAttachToBus(drv_name, bus_name); + if (EOK != ret) { + KPrintf("InitHwUart SerialDriverAttachToBus error %d\n", ret); + return ERROR; + } + + return ret; +} + +/*Attach the serial device to the serial bus*/ +static int BoardSerialDevBend(struct SerialHardwareDevice *serial_device, void *serial_param, const char *bus_name, const char *dev_name) +{ + x_err_t ret = EOK; + + ret = SerialDeviceRegister(serial_device, serial_param, dev_name); + if (EOK != ret) { + KPrintf("InitHwUart SerialDeviceInit device %s error %d\n", dev_name, ret); + return ERROR; + } + + ret = SerialDeviceAttachToBus(dev_name, bus_name); + if (EOK != ret) { + KPrintf("InitHwUart SerialDeviceAttachToBus device %s error %d\n", dev_name, ret); + return ERROR; + } + + return ret; +} +#ifdef BSP_USING_UART4 +struct SerialDriver serial_driver_4; +struct SerialHardwareDevice serial_device_4; + +void UART4_IRQHandler(int irq_num, void *arg) +{ + UartIsr(&serial_driver_4, &serial_device_4); +} +// DECLARE_HW_IRQ(UART4_IRQn, UART4_IRQHandler, NONE); +#endif + +int InitHwUart(void) +{ + x_err_t ret = EOK; + +// #ifdef BSP_USING_UART0 +// rcu_periph_clock_enable(RCU_USART0); +// #endif + +// #ifdef BSP_USING_UART1 +// rcu_periph_clock_enable(RCU_USART1); +// #endif +// #ifdef BSP_USING_UART2 +// rcu_periph_clock_enable(RCU_USART2); +// #endif +// #ifdef BSP_USING_UART3 +// rcu_periph_clock_enable(RCU_UART3); +// #endif +#ifdef BSP_USING_UART4 + rcu_periph_clock_enable(RCU_UART4); +#endif + +#ifdef BSP_USING_UART4 + static struct SerialBus serial_bus; + memset(&serial_bus, 0, sizeof(struct SerialBus)); + + memset(&serial_driver_4, 0, sizeof(struct SerialDriver)); + + memset(&serial_device_4, 0, sizeof(struct SerialHardwareDevice)); + + static struct SerialCfgParam serial_cfg; + memset(&serial_cfg, 0, sizeof(struct SerialCfgParam)); + + static struct SerialDevParam serial_dev_param; + memset(&serial_dev_param, 0, sizeof(struct SerialDevParam)); + + serial_driver_4.drv_done = &drv_done; + serial_driver_4.configure = &SerialDrvConfigure; + serial_device_4.hwdev_done = &hwdev_done; + + serial_cfg.data_cfg = data_cfg_init; + + serial_cfg.hw_cfg.serial_register_base = UART4; + serial_cfg.hw_cfg.serial_irq_interrupt = UART4_IRQn; + + serial_driver_4.private_data = (void *)&serial_cfg; + + serial_dev_param.serial_work_mode = SIGN_OPER_INT_RX; + serial_device_4.haldev.private_data = (void *)&serial_dev_param; + + ret = BoardSerialBusInit(&serial_bus, &serial_driver_4, SERIAL_BUS_NAME_4, SERIAL_DRV_NAME_4); + if (EOK != ret) { + KPrintf("InitHwUart uarths error ret %u\n", ret); + return ERROR; + } + + ret = BoardSerialDevBend(&serial_device_4, (void *)&serial_cfg, SERIAL_BUS_NAME_4, SERIAL_4_DEVICE_NAME_4); + if (EOK != ret) { + KPrintf("InitHwUart uarths error ret %u\n", ret); + return ERROR; + } +#endif + + return ret; +} diff --git a/Ubiquitous/XiZi/board/hifive1-rev-B/.defconfig b/Ubiquitous/XiZi/board/hifive1-rev-B/.defconfig new file mode 100644 index 0000000..12ff322 --- /dev/null +++ b/Ubiquitous/XiZi/board/hifive1-rev-B/.defconfig @@ -0,0 +1,236 @@ +# +# Automatically generated file; DO NOT EDIT. +# XiZi Project Configuration +# +CONFIG_BOARD_FE310_EVB=y +CONFIG_KERNEL_CONSOLE_DEVICE_NAME="uart0" +#CONFIG_LED0=24 +#CONFIG_LED1=25 +CONFIG_ARCH_RISCV=y +CONFIG_ARCH_RISCV32=y +CONFIG_ARCH_CPU_32BIT=y + +# +# sifive feature +# +# CONFIG_BSP_USING_AUDIO is not set +# CONFIG_BSP_USING_CAMERA is not set +# CONFIG_BSP_USING_SDIO is not set +# CONFIG_BSP_USING_DMA is not set +CONFIG_BSP_USING_GPIO=y +# CONFIG_BSP_USING_I2C is not set +# CONFIG_BSP_USING_I2S is not set +# CONFIG_BSP_USING_LCD is not set +# CONFIG_BSP_USING_RTC is not set +# CONFIG_BSP_USING_SECURITY is not set +# CONFIG_BSP_USING_SPI is not set +CONFIG_BSP_USING_UART=y +# CONFIG_BSP_USING_UART_HS is not set +# CONFIG_BSP_USING_VIDEO is not set +# CONFIG_BSP_USING_WDT is not set + +# +# General Purpose UARTs +# + +CONFIG___STACKSIZE__=1024 + +# +# Hardware feature +# +CONFIG_RESOURCES_SERIAL=y +# CONFIG_SERIAL_USING_DMA=y +CONFIG_SERIAL_RB_BUFSZ=64 +CONFIG_FS_VFS=y +# CONFIG_RESOURCES_HWTIMER is not set +# CONFIG_RESOURCES_I2C is not set +# CONFIG_RESOURCES_LCD is not set +# CONFIG_RESOURCES_SDIO is not set +# CONFIG_RESOURCES_TOUCH is not set +# CONFIG_RESOURCES_PIN=y +# CONFIG_RESOURCES_RTC is not set +# CONFIG_RESOURCES_SPI is not set +#CONFIG_RESOURCES_SPI_SD is not set +#CONFIG_RESOURCES_SPI_SFUD is not set +# SFUD_USING_SFDP is not set +# SFUD_USING_FLASH_INFO_TABLE is not set +# SFUD_DEBUG_LOG is not set +# CONFIG_RESOURCES_WDT is not set +# CONFIG_RESOURCES_USB is not set +# CONFIG_RESOURCES_USB_HOST is not set +# CONFIG_UDISK_MOUNTPOINT is not set +# CONFIG_USBH_MSTORAGE is not set +# CONFIG_RESOURCES_USB_DEVICE is not set +# CONFIG_USBD_THREAD_STACK_SZ is not set + +# +# Kernel feature +# + +# +# Kernel Device Object +# +CONFIG_KERNEL_DEVICE=y +CONFIG_KERNEL_CONSOLE=y +CONFIG_KERNEL_CONSOLEBUF_SIZE=128 + +# +# Task feature +# +CONFIG_SCHED_POLICY_RR_REMAINSLICE=y +# CONFIG_SCHED_POLICY_RR is not set +# CONFIG_SCHED_POLICY_FIFO is not set + +# +# Memory Management +# +# CONFIG_KERNEL_MEMBLOCK is not set +CONFIG_MEM_ALIGN_SIZE=4 +CONFIG_MM_PAGE_SIZE=1024 + +# +# Using small memory allocator +# +# CONFIG_KERNEL_SMALL_MEM_ALLOC is not set + +# +# Inter-Task communication +# +# CONFIG_KERNEL_SEMAPHORE=y +# CONFIG_KERNEL_MUTEX=y +CONFIG_KERNEL_EVENT=y +CONFIG_KERNEL_MESSAGEQUEUE=y +CONFIG_KTASK_PRIORITY_8=y +CONFIG_KTASK_PRIORITY_MAX=8 +CONFIG_TICK_PER_SECOND=100 +# CONFIG_KERNEL_STACK_OVERFLOW_CHECK=y +CONFIG_KERNEL_BANNER=y +# CONFIG_KERNEL_HOOK is not set +# CONFIG_KERNEL_SOFTTIMER=y +# CONFIG_KERNEL_IDLE_HOOK=y +# CONFIG_IDEL_HOOK_LIST_SIZE=4 +CONFIG_IDLE_KTASK_STACKSIZE=512 +CONFIG_ZOMBIE_KTASK_STACKSIZE=512 +# CONFIG_KERNEL_TASK_ISOLATION is not set + +# +# Command shell +# +CONFIG_TOOL_SHELL=y +CONFIG_SHELL_TASK_PRIORITY=4 +CONFIG_SHELL_TASK_STACK_SIZE=2048 + +# +# User Control +# +CONFIG_SHELL_DEFAULT_USER="letter" +CONFIG_SHELL_DEFAULT_USER_PASSWORD="" +CONFIG_SHELL_LOCK_TIMEOUT=10000 +CONFIG_SHELL_ENTER_CR_AND_LF=y +# CONFIG_SHELL_ENTER_CRLF is not set +CONFIG_SHELL_ENTER_CR=y +CONFIG_SHELL_ENTER_LF=y +CONFIG_SHELL_MAX_NUMBER=5 +CONFIG_SHELL_PARAMETER_MAX_NUMBER=8 +CONFIG_SHELL_HISTORY_MAX_NUMBER=5 +CONFIG_SHELL_PRINT_BUFFER=128 +CONFIG_SHELL_USING_CMD_EXPORT=y +# CONFIG_SHELL_HELP_LIST_USER is not set +CONFIG_SHELL_HELP_SHOW_PERMISSION=y +# CONFIG_SHELL_HELP_LIST_VAR is not set +# CONFIG_SHELL_HELP_LIST_KEY is not set +#CONFIG_KERNEL_QUEUEMANAGE=y +# CONFIG_KERNEL_WORKQUEUE is not set +CONFIG_WORKQUEUE_KTASK_STACKSIZE=256 +CONFIG_WORKQUEUE_KTASK_PRIORITY=2 +CONFIG_QUEUE_MAX=2 +CONFIG_KERNEL_WAITQUEUE=y +CONFIG_KERNEL_DATAQUEUE=y +# CONFIG_KERNEL_CIRCULAR_AREA is not set +# CONFIG_KERNEL_AVL_TREE is not set +CONFIG_NAME_MAX=32 +CONFIG_ALIGN_SIZE=8 +CONFIG_KERNEL_COMPONENTS_INIT=n +CONFIG_KERNEL_USER_MAIN=y +CONFIG_MAIN_KTASK_STACK_SIZE=1500 +CONFIG_ENV_INIT_KTASK_STACK_SIZE=1024 +CONFIG_MAIN_KTASK_PRIORITY=3 +# CONFIG_USER_TEST is not set +# CONFIG_TOOL_TEST_SEM is not set +# CONFIG_TOOL_TEST_MUTEX is not set +# CONFIG_TOOL_TEST_EVENT is not set +# CONFIG_TOOL_TEST_MSG is not set +# CONFIG_TOOL_TEST_AVLTREE is not set +# CONFIG_TEST_CRICULAR_AREA is not set +# CONFIG_TOOL_TEST_MEM is not set +# CONFIG_TOOL_TEST_TIMER is not set +# CONFIG_TOOL_TEST_IWG is not set +# CONFIG_TOOL_TEST_REALTIME is not set +# CONFIG_TOOL_TEST_DBG is not set +# CONFIG_TOOL_TEST_SCHED is not set +# CONFIG_KERNEL_DEBUG is not set +#CONFIG_DEBUG_INIT_CONFIG=y +#CONFIG_DBG_INIT=1 +#CONFIG_ARCH_SMP=y +#CONFIG_CPUS_NR=2 + +# +# hash table config +# +CONFIG_ID_HTABLE_SIZE=4 +CONFIG_ID_NUM_MAX=16 + +# +# File system +# +CONFIG_FS_DFS=n +#CONFIG_DFS_USING_WORKDIR=y +#CONFIG_FS_DFS_DEVFS=y + +# +# Fat filesystem +# + +# +# IOT-Device File system +# + +# +# Lwext4 filesystem +# + +# +# APP Framework +# + +# +# connection +# +# CONFIG_CONNECTION_AT is not set +# CONFIG_CONNECTION_MQTT is not set + +# +# medium communication +# + + +# +# Intelligence +# + +# +# Control +# + +# +# Lib +# +CONFIG_LIB=y +CONFIG_LIB_POSIX=y +CONFIG_LIB_NEWLIB=y + +# CONFIG_LITTLEVGL2RTT_USING_DEMO=y + +# +# Security +# diff --git a/Ubiquitous/XiZi/board/hifive1-rev-B/Kconfig b/Ubiquitous/XiZi/board/hifive1-rev-B/Kconfig new file mode 100644 index 0000000..a735824 --- /dev/null +++ b/Ubiquitous/XiZi/board/hifive1-rev-B/Kconfig @@ -0,0 +1,58 @@ +mainmenu "XiZi Project Configuration" + +config BSP_DIR + string + option env="BSP_ROOT" + default "." + +config KERNEL_DIR + string + option env="KERNEL_ROOT" + default "../.." + +config BOARD_FE310_EVB + bool + select ARCH_RISCV + select ARCH_RISCV32 + select ARCH_CPU_32BIT + default y + +config KERNEL_CONSOLE_DEVICE_NAME + string + default "uart0" + + +source "$KERNEL_DIR/arch/Kconfig" + +menu "hifive1 feature" + source "$BSP_DIR/third_party_driver/Kconfig" + + menu "config default board resources" + menu "config board app name" + config BOARD_APP_NAME + string "config board app name" + default "/XiUOS_hifive1-rev-B_app.bin" + endmenu + + menu "config board service table" + config SERVICE_TABLE_ADDRESS + hex "board service table address" + default 0x2007F0000 + endmenu + + endmenu + + config __STACKSIZE__ + int "stack size for interrupt" + default 4096 + +endmenu + + +menu "Hardware feature" +source "$KERNEL_DIR/resources/Kconfig" +endmenu + +source "$KERNEL_DIR/Kconfig" + + diff --git a/Ubiquitous/XiZi/board/hifive1-rev-B/Makefile b/Ubiquitous/XiZi/board/hifive1-rev-B/Makefile new file mode 100644 index 0000000..ba3103b --- /dev/null +++ b/Ubiquitous/XiZi/board/hifive1-rev-B/Makefile @@ -0,0 +1,6 @@ +SRC_FILES := board.c + +SRC_DIR := third_party_driver + + +include $(KERNEL_ROOT)/compiler.mk \ No newline at end of file diff --git a/Ubiquitous/XiZi/board/hifive1-rev-B/README.md b/Ubiquitous/XiZi/board/hifive1-rev-B/README.md new file mode 100644 index 0000000..e766f75 --- /dev/null +++ b/Ubiquitous/XiZi/board/hifive1-rev-B/README.md @@ -0,0 +1,189 @@ +# 从零开始构建矽璓工业物联操作系统：使用risc-v架构的HiFive1 Rev B 开发板 + +[XiUOS](http://xuos.io/) (X Industrial Ubiquitous Operating System) 矽璓工业物联操作系统是一款面向工业物联场景的泛在操作系统，来自泛在操作系统研究计划。所谓泛在操作系统(UOS: Ubiquitous Operating Systems)，是支持互联网时代人机物融合泛在计算应用模式的新型操作系统，是传统操作系统概念的泛化与延伸。在泛在操作系统技术体系中，不同的泛在计算设备和泛在应用场景需要符合各自特性的不同UOS，XiUOS即是面向工业物联场景的一种UOS，主要由一个极简的微型实时操作系统(RTOS)内核和其上的智能工业物联框架构成，支持工业物联网(IIoT: Industrial Internet of Things)应用。 + +>注：最新版README请访问[从零开始构建矽璓工业物联操作系统：使用risc-v架构的HiFive1 Rev B 开发板](https://blog.csdn.net/AIIT_Ubiquitous/article/details/116259873)，如博客内容与本地文档有差异，以网站内容为准。 + +## 开发环境搭建 + +### 推荐使用： + +**操作系统：** ubuntu18.04 [https://ubuntu.com/download/desktop](https://ubuntu.com/download/desktop) + +**开发工具推荐使用 VSCode ，VScode下载地址为：** VSCode [https://code.visualstudio.com/](https://code.visualstudio.com/)，推荐下载地址为 [http://vscode.cdn.azure.cn/stable/3c4e3df9e89829dce27b7b5c24508306b151f30d/code_1.55.2-1618307277_amd64.deb](http://vscode.cdn.azure.cn/stable/3c4e3df9e89829dce27b7b5c24508306b151f30d/code_1.55.2-1618307277_amd64.deb) + +### 依赖包安装： + +``` +$ sudo apt install build-essential pkg-config +$ sudo apt install gcc make libncurses5-dev openssl libssl-dev bison flex libelf-dev autoconf libtool gperf libc6-dev git +``` + +**源码下载：** XiUOS [https://www.gitlink.org.cn/xuos/xiuos](https://www.gitlink.org.cn/xuos/xiuos) + +新建一个空文件夹并进入文件夹中，并下载源码，具体命令如下： + +```c +mkdir test && cd test +git clone https://gitlink.org.cn/xuos/xiuos.git +``` + +1、打开XiUOS源码文件包可以看到以下目录： +| 名称 | 说明 | +| -- | -- | +| APP_Framework | 应用代码 | +| Ubiquitous | 板级支持包,支持NuttX、RT-Thread和XiZi内核 | + +2、打开XiZi内核源码文件包可以看到以下目录： +| 名称 | 说明 | +| -- | -- | +| arch | 架构代码 | +| board | 板级支持包 | +| fs | 文件系统 | +| kernel | 内核源码 | +| lib | 第三方库源码 | +| resources | 驱动文件 | +| tool | 系统工具 | + +使用VScode打开代码，具体操作步骤为：在源码文件夹下打开系统终端，输入`code .`即可打开VScode开发环境，如下图所示： + +
+ +
+ +### 裁减配置工具的下载 + +裁减配置工具： + +**工具地址：** kconfig-frontends [https://www.gitlink.org.cn/xuos/kconfig-frontends](https://www.gitlink.org.cn/xuos/kconfig-frontends) + +```c +mkdir kfrontends && cd kfrontends +git clone https://gitlink.org.cn/xuos/kconfig-frontends.git +``` + +下载源码后按以下步骤执行软件安装： + +```c +cd kconfig-frontends + ./xs_build.sh +``` + +### 编译工具链： + +RISC-V: riscv-none-embed-，默认安装到Ubuntu的/opt/，下载源码并解压。[下载网址 http://101.36.126.201:8011/gnu-mcu-eclipse.tar.bz2](http://101.36.126.201:8011/gnu-mcu-eclipse.tar.bz2) + +```shell +$ tar -xjf gnu-mcu-eclipse.tar.bz2 -C /opt/ +``` + +将上述解压的编译工具链的路径添加到board/hifive1-rev-B/config.mk文件当中，例如： + +``` +export CROSS_COMPILE ?=/opt/gnu-mcu-eclipse/riscv-none-gcc/8.2.0-2.1-20190425-1021/bin/riscv-none-embed- +``` + +若已存在`export CROSS_COMPILE ?=xxxx` 应该将原有的语句注释，再写入上面的语句。 + +# 在HiFive1 Rev B board 上创建第一个应用 + +## 1.HiFive1 Rev B board 简介 + +| 硬件 | 描述 | +| -- | -- | +|芯片型号| FE310-G002 | +|架构| RV32IMAC | +|主频| 320+MHz | +|片内SRAM| 16KB | +| 外设 | UART、SPI、I2C | + +XiUOS板级当前支持使用UART。 + +## 2. 代码编写与编译说明 + +编辑环境：`VScode` + +编译工具链：`riscv-none-embed-gcc` + +使用`VScode`打开工程的方法有多种，本文介绍一种快捷键，在项目目录下将`code .`输入终端即可打开目标项目 + +修改`APP_Framework/Applications`文件夹下`main.c` + +在输出函数中写入 Hello, world! \n running on Hifive1 Rev B board完成代码编辑。 + +![main](img/main.jpg) + +编译步骤： + +1.在VScode终端下执行以下命令，生成配置文件 + +``` +cd ./Ubiquitous/XiZi +make BOARD=hifive1-rev-B distclean +make BOARD=hifive1-rev-B menuconfig +``` + +2.在menuconfig界面配置需要关闭和开启的功能，按回车键进入下级菜单，按Y键选中需要开启的功能，按N键选中需要关闭的功能，配置结束后选择Exit保存并退出 + +![menuconfig](img/menuconfig.png) + +3.继续执行以下命令，进行编译 + +``` +make BOARD=hifive1-rev-B +``` + +4.如果编译正确无误，build文件夹下会产生XiZi_hifive1-rev-B.elf、XiZi_hifive1-rev-B.bin文件。其中XiZi_hifive1-rev-B.bin需要烧写到设备中进行运行。 + +>注：最后可以执行以下命令，清除配置文件和编译生成的文件 + +``` +make BOARD=hifive1-rev-B distclean +``` + +## 3. 烧写及执行 + +hifive1-rev-B支持J-Link，可以通过J-Link进行烧录和调试。 + +![hifive1](img/hifive1-Rev-B.png) + +首先电脑需要安装J-Link Software and Documentation Pack，这里以Ubuntu18.04为例，下载[JLink_Linux_V700_x86_64.deb](https://www.segger.com/downloads/jlink/JLink_Linux_V700_x86_64.deb)，推荐使用[http://101.36.126.201:8011/JLink_Linux_V700_x86_64.deb](http://101.36.126.201:8011/JLink_Linux_V700_x86_64.deb)下载，然后执行以下命令安装到电脑上 + +```c +sudo apt install ./JLink_Linux_V700_x86_64.deb +``` + +使用 Micro USB 线将开发板与电脑连接，终端执行以下命令进入J-Link控制台，并通过J-Link连接设备 + +```c +JLinkExe -device FE310 -if jtag -jtagconf -1,-1 -speed 4000 +``` + +命令执行成功后终端如下图： + +![cmd1](img/jlink_cmd1.png) + +在J-Link控制台输入connect连接设备，如下图： + +![cmd2](img/jlink_cmd2.png) + +接着输入erase命令擦除FLASH，如图： + +![cmd3](img/jlink_cmd3.png) + +输入loadbin命令，并指定烧录的bin文件和烧录地址，将bin文件烧录到开发板中，如图： + +![cmd4](img/jlink_cmd4.png) + +### 3.1 运行结果 + +如果编译 & 烧写无误，可以通过screen工具打开串口终端，hifive1-rev-B连接电脑后，在/dev 目录下会多出/dev/ttyACM0、/dev/ttyACM1两个串口设备，一般串口输出为/dev/ttyACM0，通过screen命令打开串口： + +``` +sudo apt install screen +screen /dev/ttyACM0 115200 +``` + +按下开发板Reset按钮，将会在串口终端上看到信息打印输出 + +![terminal](img/terminal.png) diff --git a/Ubiquitous/XiZi/board/hifive1-rev-B/board.c b/Ubiquitous/XiZi/board/hifive1-rev-B/board.c new file mode 100644 index 0000000..174860d --- /dev/null +++ b/Ubiquitous/XiZi/board/hifive1-rev-B/board.c @@ -0,0 +1,71 @@ +/* +* Copyright (c) 2020 AIIT XUOS Lab +* XiUOS is licensed under Mulan PSL v2. +* You can use this software according to the terms and conditions of the Mulan PSL v2. +* You may obtain a copy of Mulan PSL v2 at: +* http://license.coscl.org.cn/MulanPSL2 +* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, +* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, +* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. +* See the Mulan PSL v2 for more details. +*/ + +/** +* @file board.c +* @brief support hifive1-rev-B-board init configure and start-up +* @version 1.0 +* @author AIIT XUOS Lab +* @date 2021-04-25 +*/ + +#include +#include +#include +#include +#include +#include +#include + +extern void use_default_clocks(void); +extern void use_pll(int refsel, int bypass, int r, int f, int q); +plic_instance_t g_plic = {0} ; + +void InitBoardHardware(void) +{ + + /* initialize the system clock */ + use_default_clocks(); + use_pll(0, 0, 1, 31, 1); + + /* initialize hardware interrupt */ + asm volatile( + "la t0, save_hw_context\n" + "csrw mtvec, t0" + ); + + PLIC_init(&g_plic, + PLIC_CTRL_ADDR, + PLIC_NUM_INTERRUPTS, + PLIC_NUM_PRIORITIES); + + SET_CSR(mie, MIP_MEIP); + + /* initialize timer*/ + CLINT_MTIMECMP_ADDR = CLINT_MTIME_ADDR + TICK; + SET_CSR(mie, MIP_MTIP); + + /* initialize memory system */ + InitBoardMemory(MEMORY_START_ADDRESS, MEMORY_END_ADDRESS); + + extern int InitHwUart(void); + InitHwUart(); + InstallConsole(SERIAL_BUS_NAME, SERIAL_DRV_NAME, SERIAL_DEVICE_NAME); + + KPrintf("\nconsole init completed.\n"); + KPrintf("board initialization......\n"); + + KPrintf("memory address range: [0x%08x - 0x%08x], size: %d\n", (x_ubase) MEMORY_START_ADDRESS, (x_ubase) MEMORY_END_ADDRESS, MEMORY_SIZE); + + return; +} + diff --git a/Ubiquitous/XiZi/board/hifive1-rev-B/board.h b/Ubiquitous/XiZi/board/hifive1-rev-B/board.h new file mode 100644 index 0000000..2ba5f8b --- /dev/null +++ b/Ubiquitous/XiZi/board/hifive1-rev-B/board.h @@ -0,0 +1,82 @@ +/* +* Copyright (c) 2020 AIIT XUOS Lab +* XiUOS is licensed under Mulan PSL v2. +* You can use this software according to the terms and conditions of the Mulan PSL v2. +* You may obtain a copy of Mulan PSL v2 at: +* http://license.coscl.org.cn/MulanPSL2 +* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, +* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, +* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. +* See the Mulan PSL v2 for more details. +*/ + +/** +* @file board.h +* @brief define hifive1-rev-B-board init configure and start-up function +* @version 1.0 +* @author AIIT XUOS Lab +* @date 2021-04-25 +*/ + +#ifndef __BOARD_H__ +#define __BOARD_H__ + +#include +#include + +#define TICK (2 * RTC_FREQ / TICK_PER_SECOND) + +#define CLINT_MTIME_ADDR (*((volatile uint64_t *)(CLINT_CTRL_ADDR + CLINT_MTIME))) +#define CLINT_MTIMECMP_ADDR (*((volatile uint64_t *)(CLINT_CTRL_ADDR + CLINT_MTIMECMP))) + +#define SERIAL_BUS_NAME "uart0" +#define SERIAL_DRV_NAME "uart0_drv" +#define SERIAL_DEVICE_NAME "uart0_dev0" + +#define SURPORT_PMP + +#ifdef SEPARATE_COMPILE +#define MEMORY_SIZE 12 +#else +#define MEMORY_SIZE 16 +#endif + +extern void *_end; +extern void *_heap_end; +extern void *__stack_end__; + +extern unsigned int g_service_table_start; +extern unsigned int g_service_table_end; + +#define MEMORY_START_ADDRESS (void *)&__stack_end__ +#define MEMORY_END_ADDRESS (void *)( 0x80000000 + MEMORY_SIZE * 1024 ) + + +#ifdef SEPARATE_COMPILE +typedef int (*main_t)(int argc, char *argv[]); +typedef void (*exit_t)(void); +struct UserSpaceS +{ + main_t us_entrypoint; + exit_t us_taskquit; + uintptr_t us_textstart; + uintptr_t us_textend; + uintptr_t us_datasource; + uintptr_t us_datastart; + uintptr_t us_dataend; + uintptr_t us_bssstart; + uintptr_t us_bssend; + uintptr_t us_heapend; +}; +#define USERSPACE (( struct UserSpaceS *)(0x20080000)) + +#ifndef SERVICE_TABLE_ADDRESS +#define SERVICE_TABLE_ADDRESS (0x2007F0000) //in flash +#endif + +#define USER_SRAM_SIZE 4 +#define USER_MEMORY_START_ADDRESS (USERSPACE->us_bssend) +#define USER_MEMORY_END_ADDRESS (0x80003000 + USER_SRAM_SIZE * 1024) +#endif + +#endif diff --git a/Ubiquitous/XiZi/board/hifive1-rev-B/config.mk b/Ubiquitous/XiZi/board/hifive1-rev-B/config.mk new file mode 100644 index 0000000..1f88e31 --- /dev/null +++ b/Ubiquitous/XiZi/board/hifive1-rev-B/config.mk @@ -0,0 +1,21 @@ +export CFLAGS := -mcmodel=medany -march=rv32imac -mabi=ilp32 -fno-common -ffunction-sections -fdata-sections -fstrict-volatile-bitfields -O0 -ggdb -fgnu89-inline -Werror +export AFLAGS := -c -mcmodel=medany -march=rv32imac -mabi=ilp32 -x assembler-with-cpp -ggdb +export LFLAGS := -mcmodel=medany -march=rv32imac -mabi=ilp32 -nostartfiles -Wl,--gc-sections,-Map=XiZi.map,-cref,-u,_start -T $(BSP_ROOT)/link.lds + +export APPLFLAGS := -mcmodel=medany -march=rv32imac -mabi=ilp32 -nostartfiles -Wl,--gc-sections,-Map=XiZi_app.map,-cref,-u, -T $(BSP_ROOT)/link_userspace.lds + +export CXXFLAGS := -mcmodel=medany -march=rv32imac -mabi=ilp32 -fno-common -ffunction-sections -fdata-sections -fstrict-volatile-bitfields -O0 -ggdb -Werror + +export CROSS_COMPILE ?=/opt/gnu-mcu-eclipse/riscv-none-gcc/8.2.0-2.1-20190425-1021/bin/riscv-none-embed- + +#export CROSS_COMPILE ?=/opt/xpack-riscv-none-embed-gcc-10.1.0-1.1/bin/riscv-none-embed- + +export DEFINES := -DHAVE_CCONFIG_H -DHAVE_SIGINFO + + +export ARCH = risc-v +export MCU = FE310 + +# export HAVE_SIGINFO=1 + +# export USING_LORA = 1 diff --git a/Ubiquitous/XiZi/board/hifive1-rev-B/img/hifive1-Rev-B.png b/Ubiquitous/XiZi/board/hifive1-rev-B/img/hifive1-Rev-B.png new file mode 100644 index 0000000..11cb6c5 Binary files /dev/null and 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100644 index 0000000..b9bacff Binary files /dev/null and b/Ubiquitous/XiZi/board/hifive1-rev-B/img/vscode.jpg differ diff --git a/Ubiquitous/XiZi/board/hifive1-rev-B/link.lds b/Ubiquitous/XiZi/board/hifive1-rev-B/link.lds new file mode 100644 index 0000000..ec0e43a --- /dev/null +++ b/Ubiquitous/XiZi/board/hifive1-rev-B/link.lds @@ -0,0 +1,105 @@ +/* +* Copyright (c) 2020 AIIT XUOS Lab +* XiUOS is licensed under Mulan PSL v2. +* You can use this software according to the terms and conditions of the Mulan PSL v2. +* You may obtain a copy of Mulan PSL v2 at: +* http://license.coscl.org.cn/MulanPSL2 +* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, +* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, +* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. +* See the Mulan PSL v2 for more details. +*/ + +OUTPUT_ARCH( "riscv" ) +__STACKSIZE__ = 1024; +ENTRY( _begin ) + +MEMORY +{ + flash (rxai!w) : ORIGIN = 0x20000000, LENGTH = 512M + sram (wxa!ri) : ORIGIN = 0x80000000, LENGTH = 12K +} + + +SECTIONS +{ + .start : + { + *(.init); + } > flash + .text : + { + *(.text .text.*) + *(.rodata .rodata*) + /* section information for shell */ + . = ALIGN(8); + _shell_command_start = .; + KEEP (*(shellCommand)) + _shell_command_end = .; + . = ALIGN(8); + + /* the work i did */ + PROVIDE(__ctors_start__ = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array)) + PROVIDE(__ctors_end__ = .); + + . = ALIGN(4); + __isrtbl_idx_start = .; + KEEP(*(.isrtbl.idx)) + __isrtbl_start = .; + KEEP(*(.isrtbl)) + __isrtbl_end = .; + . = ALIGN(8); + + PROVIDE(g_service_table_start = ABSOLUTE(.)); + KEEP(*(.g_service_table)) + PROVIDE(g_service_table_end = ABSOLUTE(.)); + + } > flash + + PROVIDE (_etext = .); + . = ALIGN(4); + + .lalign : + { + . = ALIGN(4); + PROVIDE( _data_lma = . ); + } >flash AT>flash + + .data : + { + . = ALIGN(4); + PROVIDE( _data = . ); + *(.data .data.*) + . = ALIGN(4); + PROVIDE( __global_pointer$ = . + 0x800 ); + *(.sdata .sdata.*) + } >sram AT>flash + + . = ALIGN(4); + PROVIDE( _edata = . ); + + PROVIDE( __bss_start = . ); + .bss : + { + *(.sbss*) + *(.bss .bss.*) + *(.scommon) + . = ALIGN(4); + } > sram + + . = ALIGN(8); + PROVIDE( _end = . ); + + .stack : + { + . = ALIGN(4); + /* cpu0 stack top site */ + . = . + __STACKSIZE__; + _sp = . ; + PROVIDE(_sp = ABSOLUTE(.)); + PROVIDE( __stack_end__ = ABSOLUTE(.) ); + } > sram + +} diff --git a/Ubiquitous/XiZi/board/hifive1-rev-B/link_userspace.lds b/Ubiquitous/XiZi/board/hifive1-rev-B/link_userspace.lds new file mode 100644 index 0000000..5cb8676 --- /dev/null +++ b/Ubiquitous/XiZi/board/hifive1-rev-B/link_userspace.lds @@ -0,0 +1,73 @@ +/* +* Copyright (c) 2020 AIIT XUOS Lab +* XiUOS is licensed under Mulan PSL v2. +* You can use this software according to the terms and conditions of the Mulan PSL v2. +* You may obtain a copy of Mulan PSL v2 at: +* http://license.coscl.org.cn/MulanPSL2 +* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, +* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, +* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. +* See the Mulan PSL v2 for more details. +*/ + +OUTPUT_ARCH("riscv") + +MEMORY +{ + uflash (rx) : ORIGIN = 0x20080000, LENGTH = 512k /* 512KB uflash */ + usram (rw) : ORIGIN = 0x80003000, LENGTH = 4k /* 4K usram */ +} + +SECTIONS +{ + .userspace : + { + . = ALIGN(4); + KEEP(*(.userspace)) + } > uflash + + .text : + { + _ustext = ABSOLUTE(.); + *(.text .text.*) + *(.rodata .rodata*) + *(.glue_7) + *(.glue_7t) + PROVIDE(_uetext = ABSOLUTE(.)); + } > uflash + + .init_section : { + _sinit = ABSOLUTE(.); + KEEP(*(.init_array .init_array.*)) + _einit = ABSOLUTE(.); + } > uflash + + __uexidx_start = ABSOLUTE(.); + + .ARM.exidx : + { + PROVIDE(__uexidx_start = ABSOLUTE(.)); + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + PROVIDE(__uexidx_end = ABSOLUTE(.)); + } > uflash + + _ueronly = ABSOLUTE(.); + + .data : AT(_ueronly) + { + _usdata = ABSOLUTE(.); + *(.data .data.*) + . = ALIGN(4); + _uedata = ABSOLUTE(.); + } > usram + + .bss : { + . = ALIGN(4); + _usbss = ABSOLUTE(.); + *(.bss .bss.*) + *(.sbss .sbss.*) + . = ALIGN(4); + _uebss = ABSOLUTE(.); + } > usram + +} \ No newline at end of file diff --git a/Ubiquitous/XiZi/board/hifive1-rev-B/third_party_driver/Kconfig b/Ubiquitous/XiZi/board/hifive1-rev-B/third_party_driver/Kconfig new file mode 100644 index 0000000..e69de29 diff --git a/Ubiquitous/XiZi/board/hifive1-rev-B/third_party_driver/LICENSE b/Ubiquitous/XiZi/board/hifive1-rev-B/third_party_driver/LICENSE new file mode 100644 index 0000000..0b0b6c8 --- /dev/null +++ b/Ubiquitous/XiZi/board/hifive1-rev-B/third_party_driver/LICENSE @@ -0,0 +1,206 @@ + +This software, except as otherwise noted in subrepositories, +is licensed under the Apache 2 license, quoted below. + + + Apache License + Version 2.0, January 2004 + http://www.apache.org/licenses/ + + TERMS AND CONDITIONS FOR USE, REPRODUCTION, AND DISTRIBUTION + + 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We also recommend that a + file or class name and description of purpose be included on the + same "printed page" as the copyright notice for easier + identification within third-party archives. + + Copyright 2016 SiFive, Inc. + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. diff --git a/Ubiquitous/XiZi/board/hifive1-rev-B/third_party_driver/Makefile b/Ubiquitous/XiZi/board/hifive1-rev-B/third_party_driver/Makefile new file mode 100644 index 0000000..00a7478 --- /dev/null +++ b/Ubiquitous/XiZi/board/hifive1-rev-B/third_party_driver/Makefile @@ -0,0 +1,3 @@ +SRC_FILES := connect_usart.c plic/plic_driver.c fe300prci/fe300prci_driver.c init.c + +include $(KERNEL_ROOT)/compiler.mk diff --git a/Ubiquitous/XiZi/board/hifive1-rev-B/third_party_driver/connect_usart.c b/Ubiquitous/XiZi/board/hifive1-rev-B/third_party_driver/connect_usart.c new file mode 100644 index 0000000..f9c4a33 --- /dev/null +++ b/Ubiquitous/XiZi/board/hifive1-rev-B/third_party_driver/connect_usart.c @@ -0,0 +1,263 @@ +/* +* Copyright (c) 2020 AIIT XUOS Lab +* XiUOS is licensed under Mulan PSL v2. +* You can use this software according to the terms and conditions of the Mulan PSL v2. +* You may obtain a copy of Mulan PSL v2 at: +* http://license.coscl.org.cn/MulanPSL2 +* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, +* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, +* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. +* See the Mulan PSL v2 for more details. +*/ + +/** +* @file connect_usart.c +* @brief support aiit-arm32-board usart function and register to bus framework +* @version 1.0 +* @author AIIT XUOS Lab +* @date 2021-04-25 +*/ + +#include +#include + +#include +#include +#include +#include +#include + +static void SerialCfgParamCheck(struct SerialCfgParam *serial_cfg_default, struct SerialCfgParam *serial_cfg_new) +{ + struct SerialDataCfg *data_cfg_default = &serial_cfg_default->data_cfg; + struct SerialDataCfg *data_cfg_new = &serial_cfg_new->data_cfg; + + if ((data_cfg_default->serial_baud_rate != data_cfg_new->serial_baud_rate) && (data_cfg_new->serial_baud_rate)) { + data_cfg_default->serial_baud_rate = data_cfg_new->serial_baud_rate; + } + + if ((data_cfg_default->serial_bit_order != data_cfg_new->serial_bit_order) && (data_cfg_new->serial_bit_order)) { + data_cfg_default->serial_bit_order = data_cfg_new->serial_bit_order; + } + + if ((data_cfg_default->serial_buffer_size != data_cfg_new->serial_buffer_size) && (data_cfg_new->serial_buffer_size)) { + data_cfg_default->serial_buffer_size = data_cfg_new->serial_buffer_size; + } + + if ((data_cfg_default->serial_data_bits != data_cfg_new->serial_data_bits) && (data_cfg_new->serial_data_bits)) { + data_cfg_default->serial_data_bits = data_cfg_new->serial_data_bits; + } + + if ((data_cfg_default->serial_invert_mode != data_cfg_new->serial_invert_mode) && (data_cfg_new->serial_invert_mode)) { + data_cfg_default->serial_invert_mode = data_cfg_new->serial_invert_mode; + } + + if ((data_cfg_default->serial_parity_mode != data_cfg_new->serial_parity_mode) && (data_cfg_new->serial_parity_mode)) { + data_cfg_default->serial_parity_mode = data_cfg_new->serial_parity_mode; + } + + if ((data_cfg_default->serial_stop_bits != data_cfg_new->serial_stop_bits) && (data_cfg_new->serial_stop_bits)) { + data_cfg_default->serial_stop_bits = data_cfg_new->serial_stop_bits; + } +} + +static void usart_handler(int vector, void *param) +{ + struct SerialBus *serial_bus = (struct SerialBus *)param; + struct SerialHardwareDevice *serial_dev = (struct SerialHardwareDevice *)serial_bus->bus.owner_haldev; + + SerialSetIsr(serial_dev, SERIAL_EVENT_RX_IND); +} + +static uint32 SerialInit(struct SerialDriver *serial_drv, struct BusConfigureInfo *configure_info) +{ + NULL_PARAM_CHECK(serial_drv); + struct SerialCfgParam *serial_cfg = (struct SerialCfgParam *)serial_drv->private_data; + + if (configure_info->private_data) { + struct SerialCfgParam *serial_cfg_new = (struct SerialCfgParam *)configure_info->private_data; + SerialCfgParamCheck(serial_cfg, serial_cfg_new); + } + + GPIO_REG(GPIO_IOF_SEL) &= ~IOF0_UART0_MASK; + GPIO_REG(GPIO_IOF_EN) |= IOF0_UART0_MASK; + + UART0_REG(UART_REG_DIV) = get_cpu_freq() / serial_cfg->data_cfg.serial_baud_rate - 1; + UART0_REG(UART_REG_TXCTRL) |= UART_TXEN; + UART0_REG(UART_REG_RXCTRL) |= UART_RXEN; + UART0_REG(UART_REG_IE) = UART_IP_RXWM; + + return EOK; +} + +static uint32 SerialConfigure(struct SerialDriver *serial_drv, int serial_operation_cmd) +{ + NULL_PARAM_CHECK(serial_drv); + + return EOK; +} + +static uint32 SerialDrvConfigure(void *drv, struct BusConfigureInfo *configure_info) +{ + NULL_PARAM_CHECK(drv); + NULL_PARAM_CHECK(configure_info); + + x_err_t ret = EOK; + int serial_operation_cmd; + struct SerialDriver *serial_drv = (struct SerialDriver *)drv; + + switch (configure_info->configure_cmd) + { + case OPE_INT: + ret = SerialInit(serial_drv, configure_info); + break; + case OPE_CFG: + serial_operation_cmd = *(int *)configure_info->private_data; + ret = SerialConfigure(serial_drv, serial_operation_cmd); + break; + default: + break; + } + + return ret; +} + +static int SerialPutChar(struct SerialHardwareDevice *serial_dev, char c) +{ + while (UART0_REG(UART_REG_TXFIFO) & 0x80000000) ; + UART0_REG(UART_REG_TXFIFO) = c; + + return 0; +} + +static int SerialGetChar(struct SerialHardwareDevice *serial_dev) +{ + int32_t val = UART0_REG(UART_REG_RXFIFO); + if (val > 0) + return (uint8_t)val; + else + return -1; +} + +static const struct SerialDataCfg data_cfg_init = +{ + .serial_baud_rate = BAUD_RATE_115200, + .serial_data_bits = DATA_BITS_8, + .serial_stop_bits = STOP_BITS_1, + .serial_parity_mode = PARITY_NONE, + .serial_bit_order = BIT_ORDER_LSB, + .serial_invert_mode = NRZ_NORMAL, + .serial_buffer_size = SERIAL_RB_BUFSZ, +}; + +/*manage the serial device operations*/ +static const struct SerialDrvDone drv_done = +{ + .init = SerialInit, + .configure = SerialConfigure, +}; + +/*manage the serial device hal operations*/ +static struct SerialHwDevDone hwdev_done = +{ + .put_char = SerialPutChar, + .get_char = SerialGetChar, +}; + +static int BoardSerialBusInit(struct SerialBus *serial_bus, struct SerialDriver *serial_driver, const char *bus_name, const char *drv_name) +{ + x_err_t ret = EOK; + + /*Init the serial bus */ + ret = SerialBusInit(serial_bus, bus_name); + if (EOK != ret) { + KPrintf("InitHwUart SerialBusInit error %d\n", ret); + return ERROR; + } + + /*Init the serial driver*/ + ret = SerialDriverInit(serial_driver, drv_name); + if (EOK != ret) { + KPrintf("InitHwUart SerialDriverInit error %d\n", ret); + return ERROR; + } + + /*Attach the serial driver to the serial bus*/ + ret = SerialDriverAttachToBus(drv_name, bus_name); + if (EOK != ret) { + KPrintf("InitHwUart SerialDriverAttachToBus error %d\n", ret); + return ERROR; + } + + return ret; +} + +/*Attach the serial device to the serial bus*/ +static int BoardSerialDevBend(struct SerialHardwareDevice *serial_device, void *serial_param, const char *bus_name, const char *dev_name) +{ + x_err_t ret = EOK; + + ret = SerialDeviceRegister(serial_device, serial_param, dev_name); + if (EOK != ret) { + KPrintf("InitHwUart SerialDeviceInit device %s error %d\n", dev_name, ret); + return ERROR; + } + + ret = SerialDeviceAttachToBus(dev_name, bus_name); + if (EOK != ret) { + KPrintf("InitHwUart SerialDeviceAttachToBus device %s error %d\n", dev_name, ret); + return ERROR; + } + + return ret; +} + +int InitHwUart(void) +{ + x_err_t ret = EOK; + + static struct SerialBus serial_bus; + memset(&serial_bus, 0, sizeof(struct SerialBus)); + + static struct SerialDriver serial_driver; + memset(&serial_driver, 0, sizeof(struct SerialDriver)); + + static struct SerialHardwareDevice serial_device; + memset(&serial_device, 0, sizeof(struct SerialHardwareDevice)); + + static struct SerialCfgParam serial_cfg; + memset(&serial_cfg, 0, sizeof(struct SerialCfgParam)); + + static struct SerialDevParam serial_dev_param; + memset(&serial_dev_param, 0, sizeof(struct SerialDevParam)); + + serial_driver.drv_done = &drv_done; + serial_driver.configure = &SerialDrvConfigure; + serial_device.hwdev_done = &hwdev_done; + + serial_cfg.data_cfg = data_cfg_init; + + serial_cfg.hw_cfg.serial_register_base = UART0_CTRL_ADDR; + serial_cfg.hw_cfg.serial_irq_interrupt = INT_UART0_BASE; + serial_driver.private_data = (void *)&serial_cfg; + + serial_dev_param.serial_work_mode = SIGN_OPER_INT_RX; + serial_device.haldev.private_data = (void *)&serial_dev_param; + + ret = BoardSerialBusInit(&serial_bus, &serial_driver, SERIAL_BUS_NAME, SERIAL_DRV_NAME); + if (EOK != ret) { + KPrintf("InitHwUart uarths error ret %u\n", ret); + return ERROR; + } + + ret = BoardSerialDevBend(&serial_device, (void *)&serial_cfg, SERIAL_BUS_NAME, SERIAL_DEVICE_NAME); + if (EOK != ret) { + KPrintf("InitHwUart uarths error ret %u\n", ret); + return ERROR; + } + + isrManager.done->registerIrq(serial_cfg.hw_cfg.serial_irq_interrupt, usart_handler, &serial_bus); + isrManager.done->enableIrq(serial_cfg.hw_cfg.serial_irq_interrupt); + + return ret; +} diff --git a/Ubiquitous/XiZi/board/hifive1-rev-B/third_party_driver/platform.h b/Ubiquitous/XiZi/board/hifive1-rev-B/third_party_driver/platform.h new file mode 100644 index 0000000..7634df4 --- /dev/null +++ b/Ubiquitous/XiZi/board/hifive1-rev-B/third_party_driver/platform.h @@ -0,0 +1,133 @@ +// See LICENSE for license details. + +#ifndef _SIFIVE_PLATFORM_H +#define _SIFIVE_PLATFORM_H + +// Some things missing from the official encoding.h +#define MCAUSE_INT 0x80000000 +#define MCAUSE_CAUSE 0x7FFFFFFF + +#include "sifive/const.h" +#include "sifive/devices/aon.h" +#include "sifive/devices/clint.h" +#include "sifive/devices/gpio.h" +#include "sifive/devices/otp.h" +#include "sifive/devices/plic.h" +#include "sifive/devices/prci.h" +#include "sifive/devices/pwm.h" +#include "sifive/devices/spi.h" +#include "sifive/devices/uart.h" + +/**************************************************************************** + * Platform definitions + *****************************************************************************/ + +// Memory map +#define MASKROM_MEM_ADDR _AC(0x00001000,UL) +#define TRAPVEC_TABLE_CTRL_ADDR _AC(0x00001010,UL) +#define OTP_MEM_ADDR _AC(0x00020000,UL) +#define CLINT_CTRL_ADDR _AC(0x02000000,UL) +#define PLIC_CTRL_ADDR _AC(0x0C000000,UL) +#define AON_CTRL_ADDR _AC(0x10000000,UL) +#define PRCI_CTRL_ADDR _AC(0x10008000,UL) +#define OTP_CTRL_ADDR _AC(0x10010000,UL) +#define GPIO_CTRL_ADDR _AC(0x10012000,UL) +#define UART0_CTRL_ADDR _AC(0x10013000,UL) +#define SPI0_CTRL_ADDR _AC(0x10014000,UL) +#define PWM0_CTRL_ADDR _AC(0x10015000,UL) +#define UART1_CTRL_ADDR _AC(0x10023000,UL) +#define SPI1_CTRL_ADDR _AC(0x10024000,UL) +#define PWM1_CTRL_ADDR _AC(0x10025000,UL) +#define SPI2_CTRL_ADDR _AC(0x10034000,UL) +#define PWM2_CTRL_ADDR _AC(0x10035000,UL) +#define SPI0_MEM_ADDR _AC(0x20000000,UL) +#define MEM_CTRL_ADDR _AC(0x80000000,UL) + +// IOF masks +#define IOF0_SPI1_MASK _AC(0x000007FC,UL) +#define SPI11_NUM_SS (4) +#define IOF_SPI1_SS0 (2u) +#define IOF_SPI1_SS1 (8u) +#define IOF_SPI1_SS2 (9u) +#define IOF_SPI1_SS3 (10u) +#define IOF_SPI1_MOSI (3u) +#define IOF_SPI1_MISO (4u) +#define IOF_SPI1_SCK (5u) +#define IOF_SPI1_DQ0 (3u) +#define IOF_SPI1_DQ1 (4u) +#define IOF_SPI1_DQ2 (6u) +#define IOF_SPI1_DQ3 (7u) + +#define IOF0_SPI2_MASK _AC(0xFC000000,UL) +#define SPI2_NUM_SS (1) +#define IOF_SPI2_SS0 (26u) +#define IOF_SPI2_MOSI (27u) +#define IOF_SPI2_MISO (28u) +#define IOF_SPI2_SCK (29u) +#define IOF_SPI2_DQ0 (27u) +#define IOF_SPI2_DQ1 (28u) +#define IOF_SPI2_DQ2 (30u) +#define IOF_SPI2_DQ3 (31u) + +//#define IOF0_I2C_MASK _AC(0x00003000,UL) + +#define IOF0_UART0_MASK _AC(0x00030000, UL) +#define IOF_UART0_RX (16u) +#define IOF_UART0_TX (17u) + +#define IOF0_UART1_MASK _AC(0x03000000, UL) +#define IOF_UART1_RX (24u) +#define IOF_UART1_TX (25u) + +#define IOF1_PWM0_MASK _AC(0x0000000F, UL) +#define IOF1_PWM1_MASK _AC(0x00780000, UL) +#define IOF1_PWM2_MASK _AC(0x00003C00, UL) + +// Interrupt numbers +#define INT_RESERVED 0 +#define INT_WDOGCMP 1 +#define INT_RTCCMP 2 +#define INT_UART0_BASE 3 +#define INT_UART1_BASE 4 +#define INT_SPI0_BASE 5 +#define INT_SPI1_BASE 6 +#define INT_SPI2_BASE 7 +#define INT_GPIO_BASE 8 +#define INT_PWM0_BASE 40 +#define INT_PWM1_BASE 44 +#define INT_PWM2_BASE 48 + +// Helper functions +#define _REG32(p, i) (*(volatile uint32_t *) ((p) + (i))) +#define _REG32P(p, i) ((volatile uint32_t *) ((p) + (i))) +#define AON_REG(offset) _REG32(AON_CTRL_ADDR, offset) +#define CLINT_REG(offset) _REG32(CLINT_CTRL_ADDR, offset) +#define GPIO_REG(offset) _REG32(GPIO_CTRL_ADDR, offset) +#define OTP_REG(offset) _REG32(OTP_CTRL_ADDR, offset) +#define PLIC_REG(offset) _REG32(PLIC_CTRL_ADDR, offset) +#define PRCI_REG(offset) _REG32(PRCI_CTRL_ADDR, offset) +#define PWM0_REG(offset) _REG32(PWM0_CTRL_ADDR, offset) +#define PWM1_REG(offset) _REG32(PWM1_CTRL_ADDR, offset) +#define PWM2_REG(offset) _REG32(PWM2_CTRL_ADDR, offset) +#define SPI0_REG(offset) _REG32(SPI0_CTRL_ADDR, offset) +#define SPI1_REG(offset) _REG32(SPI1_CTRL_ADDR, offset) +#define SPI2_REG(offset) _REG32(SPI2_CTRL_ADDR, offset) +#define UART0_REG(offset) _REG32(UART0_CTRL_ADDR, offset) +#define UART1_REG(offset) _REG32(UART1_CTRL_ADDR, offset) + +// Misc + +#include + +#define NUM_GPIO 32 + +#define PLIC_NUM_INTERRUPTS 52 +#define PLIC_NUM_PRIORITIES 7 +#define IRQN_MAX PLIC_NUM_INTERRUPTS +#include "hifive1.h" + +unsigned long get_cpu_freq(void); +unsigned long get_timer_freq(void); +uint64_t get_timer_value(void); + +#endif /* _SIFIVE_PLATFORM_H */ diff --git a/Ubiquitous/XiZi/board/kd233/.defconfig b/Ubiquitous/XiZi/board/kd233/.defconfig new file mode 100644 index 0000000..fca5c69 --- /dev/null +++ b/Ubiquitous/XiZi/board/kd233/.defconfig @@ -0,0 +1,233 @@ +# +# Automatically generated file; DO NOT EDIT. +# XiZi Project Configuration +# +CONFIG_BOARD_K210_EVB=y +CONFIG_KERNEL_CONSOLE_DEVICE_NAME="uarths" +CONFIG_LED0=24 +CONFIG_LED1=25 +CONFIG_ARCH_CPU_64BIT=y +CONFIG_ARCH_RISCV=y +CONFIG_ARCH_RISCV64=y + +# +# kd233 feature +# +# CONFIG_BSP_USING_AUDIO is not set +# CONFIG_BSP_USING_CAMERA is not set +# CONFIG_BSP_USING_SDIO is not set +CONFIG_BSP_USING_DMA=y +CONFIG_BSP_USING_GPIO=y +# CONFIG_BSP_USING_I2C is not set +# CONFIG_BSP_USING_I2S is not set +# CONFIG_BSP_USING_LCD is not set +# CONFIG_BSP_USING_RTC is not set +# CONFIG_BSP_USING_SECURITY is not set +# CONFIG_BSP_USING_SPI is not set +CONFIG_BSP_USING_UART=y +CONFIG_BSP_USING_UART_HS=y +# CONFIG_BSP_USING_VIDEO is not set +# CONFIG_BSP_USING_WDT is not set + +# +# General Purpose UARTs +# +CONFIG_BSP_USING_UART1=y +CONFIG_BSP_UART1_TXD_PIN=20 +CONFIG_BSP_UART1_RXD_PIN=21 +CONFIG_BSP_USING_UART2=y +CONFIG_BSP_UART2_TXD_PIN=28 +CONFIG_BSP_UART2_RXD_PIN=27 +CONFIG_BSP_USING_UART3=y +CONFIG_BSP_UART3_TXD_PIN=22 +CONFIG_BSP_UART3_RXD_PIN=23 +CONFIG___STACKSIZE__=4096 + +# +# Hardware feature +# +CONFIG_RESOURCES_SERIAL=y +# CONFIG_SERIAL_USING_DMA is not set +# CONFIG_SERIAL_RB_BUFSZ is not set +# CONFIG_RESOURCES_HWTIMER is not set +# CONFIG_RESOURCES_I2C is not set +# CONFIG_RESOURCES_LCD is not set +# CONFIG_RESOURCES_SDIO is not set +# CONFIG_RESOURCES_TOUCH is not set +CONFIG_RESOURCES_PIN=y +# CONFIG_RESOURCES_RTC is not set +# CONFIG_RESOURCES_SPI is not set +#CONFIG_RESOURCES_SPI_SD is not set +#CONFIG_RESOURCES_SPI_SFUD is not set +# SFUD_USING_SFDP is not set +# SFUD_USING_FLASH_INFO_TABLE is not set +# SFUD_DEBUG_LOG is not set +# CONFIG_RESOURCES_WDT is not set +# CONFIG_RESOURCES_USB is not set +# CONFIG_RESOURCES_USB_HOST is not set +# CONFIG_UDISK_MOUNTPOINT is not set +# CONFIG_USBH_MSTORAGE is not set +# CONFIG_RESOURCES_USB_DEVICE is not set +# CONFIG_USBD_THREAD_STACK_SZ is not set + +# +# Kernel feature +# +# CONFIG_SEPARATE_COMPILE is not set +# CONFIG_COMPILER_APP is not set +# CONFIG_COMPILER_KERNEL is not set +# +# Kernel Device Object +# +CONFIG_KERNEL_DEVICE=y +CONFIG_KERNEL_CONSOLE=y +CONFIG_KERNEL_CONSOLEBUF_SIZE=128 + +# +# Task feature +# +CONFIG_SCHED_POLICY_RR_REMAINSLICE=y +# CONFIG_SCHED_POLICY_RR is not set +# CONFIG_SCHED_POLICY_FIFO is not set + +# +# Inter-Task communication +# +CONFIG_KERNEL_SEMAPHORE=y +CONFIG_KERNEL_MUTEX=y +CONFIG_KERNEL_EVENT=y +CONFIG_KERNEL_MESSAGEQUEUE=y +# CONFIG_KTASK_PRIORITY_8 is not set +CONFIG_KTASK_PRIORITY_32=y +# CONFIG_KTASK_PRIORITY_256 is not set +CONFIG_KTASK_PRIORITY_MAX=32 +CONFIG_TICK_PER_SECOND=100 +CONFIG_KERNEL_STACK_OVERFLOW_CHECK=y +CONFIG_KERNEL_BANNER=y +# CONFIG_KERNEL_HOOK is not set +CONFIG_KERNEL_SOFTTIMER=y +CONFIG_KERNEL_IDLE_HOOK=y +CONFIG_IDEL_HOOK_LIST_SIZE=4 +CONFIG_IDLE_KTASK_STACKSIZE=1024 +CONFIG_USER_APPLICATION=y +# CONFIG_TASK_ISOLATION is not set + +# +# Memory Management +# +# CONFIG_KERNEL_MEMBLOCK is not set + +# +# Command shell +# +CONFIG_TOOL_SHELL=y +CONFIG_SHELL_TASK_PRIORITY=20 +CONFIG_SHELL_TASK_STACK_SIZE=4096 + +# +# User Control +# +CONFIG_SHELL_DEFAULT_USER="letter" +CONFIG_SHELL_DEFAULT_USER_PASSWORD="" +CONFIG_SHELL_LOCK_TIMEOUT=10000 +CONFIG_SHELL_ENTER_CR_AND_LF=y +# CONFIG_SHELL_ENTER_CRLF is not set +CONFIG_SHELL_ENTER_CR=y +CONFIG_SHELL_ENTER_LF=y +CONFIG_SHELL_MAX_NUMBER=5 +CONFIG_SHELL_PARAMETER_MAX_NUMBER=8 +CONFIG_SHELL_HISTORY_MAX_NUMBER=5 +CONFIG_SHELL_PRINT_BUFFER=128 +CONFIG_SHELL_USING_CMD_EXPORT=y +# CONFIG_SHELL_HELP_LIST_USER is not set +CONFIG_SHELL_HELP_SHOW_PERMISSION=y +# CONFIG_SHELL_HELP_LIST_VAR is not set +# CONFIG_SHELL_HELP_LIST_KEY is not set +CONFIG_KERNEL_QUEUEMANAGE=y +CONFIG_KERNEL_WORKQUEUE=y +CONFIG_WORKQUEUE_KTASK_STACKSIZE=512 +CONFIG_WORKQUEUE_KTASK_PRIORITY=23 +CONFIG_KERNEL_WAITQUEUE=y +CONFIG_KERNEL_DATAQUEUE=y +# CONFIG_KERNEL_CIRCULAR_AREA is not set +# CONFIG_KERNEL_AVL_TREE is not set +CONFIG_NAME_MAX=32 +CONFIG_ALIGN_SIZE=8 +CONFIG_KERNEL_COMPONENTS_INIT=y +CONFIG_KERNEL_USER_MAIN=y +CONFIG_MAIN_KTASK_STACK_SIZE=2048 +CONFIG_ENV_INIT_KTASK_STACK_SIZE=8192 +CONFIG_MAIN_KTASK_PRIORITY=10 +# CONFIG_USER_TEST is not set +# CONFIG_TOOL_TEST_SEM is not set +# CONFIG_TOOL_TEST_MUTEX is not set +# CONFIG_TOOL_TEST_EVENT is not set +# CONFIG_TOOL_TEST_MSG is not set +# CONFIG_TOOL_TEST_AVLTREE is not set +# CONFIG_TEST_CRICULAR_AREA is not set +# CONFIG_TOOL_TEST_MEM is not set +# CONFIG_TOOL_TEST_TIMER is not set +# CONFIG_TOOL_TEST_IWG is not set +# CONFIG_TOOL_TEST_REALTIME is not set +# CONFIG_TOOL_TEST_DBG is not set +# CONFIG_TOOL_TEST_SCHED is not set +# CONFIG_KERNEL_DEBUG is not set +CONFIG_DEBUG_INIT_CONFIG=y +CONFIG_DBG_INIT=1 +CONFIG_ARCH_SMP=y +CONFIG_CPUS_NR=2 + +# +# File system +# +CONFIG_FS_VFS=y +CONFIG_VFS_USING_WORKDIR=y +CONFIG_FS_VFS_DEVFS=y + +# +# Fat filesystem +# + +# +# IOT-Device File system +# + +# +# Lwext4 filesystem +# + +# +# APP Framework +# + +# +# connection +# +# CONFIG_CONNECTION_AT is not set +# CONFIG_CONNECTION_MQTT is not set + +# +# medium communication +# + + +# +# Intelligence +# + +# +# Control +# + +# +# Lib +# +CONFIG_LIB=y +CONFIG_LIB_POSIX=y +CONFIG_LIB_NEWLIB=y + +CONFIG_LITTLEVGL2RTT_USING_DEMO=y + +# +# Security +# diff --git a/Ubiquitous/XiZi/board/kd233/Kconfig b/Ubiquitous/XiZi/board/kd233/Kconfig new file mode 100644 index 0000000..67ebe8e --- /dev/null +++ b/Ubiquitous/XiZi/board/kd233/Kconfig @@ -0,0 +1,88 @@ +mainmenu "XiZi Project Configuration" + +config BSP_DIR + string + option env="BSP_ROOT" + default "." + +config KERNEL_DIR + string + option env="KERNEL_ROOT" + default "../.." + +config BOARD_K210_EVB + bool + select ARCH_RISCV + select ARCH_RISCV64 + select ARCH_CPU_64BIT + default y + +config LED0 + int + default 24 + + config LED1 + int + default 25 + + +source "$KERNEL_DIR/arch/Kconfig" + +menu "kd233 feature" + source "$BSP_DIR/third_party_driver/Kconfig" + + menu "config default board resources" + menu "config board app name" + config BOARD_APP_NAME + string "config board app name" + default "/XiUOS_kd233_app.bin" + endmenu + + menu "config board service table" + config SERVICE_TABLE_ADDRESS + hex "board service table address" + default 0x80100000 + endmenu + + menu "config hardware resources for connection" + if CONNECTION_COMMUNICATION_ETHERNET + config ETHERNET_UART_NAME + string "ethernet uart name" + default "/dev/uart3_dev3" + endif + if CONNECTION_COMMUNICATION_WIFI + config WIFI_UART_NAME + string "wifi uart name" + default "/dev/uart3_dev3" + endif + + endmenu + + menu "config board peripheral" + config MOUNT_SDCARD + bool "mount cd card" + default n + select BSP_USING_SPI + select BSP_USING_SPI1 + select RESOURCES_SPI_SD + endmenu + + endmenu + + config __STACKSIZE__ + int "stack size for interrupt" + default 4096 + +endmenu + + + + + +menu "Hardware feature" +source "$KERNEL_DIR/resources/Kconfig" +endmenu + +source "$KERNEL_DIR/Kconfig" + + diff --git a/Ubiquitous/XiZi/board/kd233/Makefile b/Ubiquitous/XiZi/board/kd233/Makefile new file mode 100644 index 0000000..12f4148 --- /dev/null +++ b/Ubiquitous/XiZi/board/kd233/Makefile @@ -0,0 +1,6 @@ +SRC_FILES := board.c + +SRC_DIR := third_party_driver + + +include $(KERNEL_ROOT)/compiler.mk diff --git a/Ubiquitous/XiZi/board/kd233/README.md b/Ubiquitous/XiZi/board/kd233/README.md new file mode 100644 index 0000000..c075aa8 --- /dev/null +++ b/Ubiquitous/XiZi/board/kd233/README.md @@ -0,0 +1,188 @@ +# 从零开始构建矽璓工业物联操作系统：使用risc-v架构的kd233开发板 + +[XiUOS](http://xuos.io/) (X Industrial Ubiquitous Operating System) 矽璓XiUOS是一款面向智慧车间的工业物联网操作系统，主要由一个极简的微型实时操作系统内核和其上的工业物联框架构成，通过高效管理工业物联网设备、支撑工业物联应用，在生产车间内实现智能化的“感知环境、联网传输、知悉识别、控制调整”，促进以工业设备和工业控制系统为核心的人、机、物深度互联，帮助提升生产线的数字化和智能化水平。 + +>注：最新版README请访问[从零开始构建矽璓工业物联操作系统：使用risc-v架构的kd233开发板](https://blog.csdn.net/AIIT_Ubiquitous/article/details/116175737)，如博客内容与本地文档有差异，以网站内容为准。 + +## 开发环境搭建 + +### 推荐使用： + +**操作系统：** ubuntu18.04 [https://ubuntu.com/download/desktop](https://ubuntu.com/download/desktop) +**开发工具推荐使用 VSCode ，VScode下载地址为：** VSCode [https://code.visualstudio.com/](https://code.visualstudio.com/)，推荐下载地址为 [http://vscode.cdn.azure.cn/stable/3c4e3df9e89829dce27b7b5c24508306b151f30d/code_1.55.2-1618307277_amd64.deb](http://vscode.cdn.azure.cn/stable/3c4e3df9e89829dce27b7b5c24508306b151f30d/code_1.55.2-1618307277_amd64.deb) + +### 依赖包安装： + +``` +$ sudo apt install build-essential pkg-config +$ sudo apt install gcc make libncurses5-dev openssl libssl-dev bison flex libelf-dev autoconf libtool gperf libc6-dev git +``` + +**源码下载：** XiUOS [https://www.gitlink.org.cn/xuos/xiuos](https://www.gitlink.org.cn/xuos/xiuos) +新建一个空文件夹并进入文件夹中，并下载源码，具体命令如下： + +```c +mkdir test && cd test +git clone https://gitlink.org.cn/xuos/xiuos.git +``` + +1、打开XiUOS源码文件包可以看到以下目录： +| 名称 | 说明 | +| -- | -- | +| APP_Framework | 应用代码 | +| Ubiquitous | 板级支持包,支持NuttX、RT-Thread和XiZi内核 | + +2、打开XiZi内核源码文件包可以看到以下目录： +| 名称 | 说明 | +| -- | -- | +| arch | 架构代码 | +| board | 板级支持包 | +| fs | 文件系统 | +| kernel | 内核源码 | +| lib | 第三方库源码 | +| resources | 驱动文件 | +| tool | 系统工具 | + +使用VScode打开代码，具体操作步骤为：在源码文件夹下打开系统终端，输入`code .`即可打开VScode开发环境，如下图所示： + +
+ +
+ +### 裁减配置工具的下载 +**裁减配置工具：** kconfig-frontends [https://www.gitlink.org.cn/xuos/kconfig-frontends](https://www.gitlink.org.cn/xuos/kconfig-frontends) +执行以下命令下载配置工具： + +```c +mkdir kfrontends && cd kfrontends +git clone https://gitlink.org.cn/xuos/kconfig-frontends.git +``` + +下载源码后按以下步骤执行软件安装： + +```c +cd kconfig-frontends +./xs_build.sh +``` + +### 编译工具链： + +RISC-V: riscv-none-embed-，默认安装到Ubuntu的/opt/，下载源码并解压。[下载网址 http://101.36.126.201:8011/gnu-mcu-eclipse.tar.bz2](http://101.36.126.201:8011/gnu-mcu-eclipse.tar.bz2) + +```shell +$ tar -xjf gnu-mcu-eclipse.tar.bz2 -C /opt/ +``` + +将上述解压的编译工具链的路径添加到board/kd233/config.mk文件当中，例如： + +``` +export CROSS_COMPILE ?=/opt/gnu-mcu-eclipse/riscv-none-gcc/8.2.0-2.1-20190425-1021/bin/riscv-none-embed- +``` + +若`CROSS_COMPILE ` 变量定义语句已经存在，将它替换成上面的语句 + +# 在KD233上创建第一个应用 --helloworld + +# KD233开发板简介 + +## 1. 微处理器简介 + +| 硬件 | 描述 | +| -- | -- | +|芯片型号| K210 | +|CPU| 双核RV64GC | +|主频| 400MHz | +|片内SRAM| 8MB | +| 外设 | DVP、JTAG、OTP、FPIOA、GPIO、UART、SPI、RTC、I²S、I²C、WDT、Timer与PWM | + +XiUOS板级当前支持使用GPIO、I2C、LCD、RTC、SPI、Timer、UART、watchdog。 + +## 2. 代码编写与编译说明 + +编辑环境：`VScode` + +编译工具链：`riscv-none-embed-gcc` +使用`VScode`打开工程的方法有多种，本文介绍一种快捷键，在项目目录下将`code .`输入终端即可打开目标项目 + +修改`APP_Framework/Applications`文件夹下`main.c` +在输出函数中写入 Hello, world!!! \n Running on KD233完成代码编辑。 + +![main](img/main.png) + +编译步骤： + +1.在`VScode`的“命令终端”下执行以下命令，生成配置文件 + +```c +cd ./Ubiquitous/XiZi +make BOARD=kd233 distclean +make BOARD=kd233 menuconfig +``` + +2.在`menuconfig`界面配置需要关闭和开启的功能，按回车键进入下级菜单，按Y键选中需要开启的功能，按N键选中需要关闭的功能，配置结束后选择Exit保存并退出（本实验无需选择任何选项，所以双击ESC结束选择，继续操作即可）。 + +![menuconfig1](img/menuconfig1.png) + +双击`ESC`键会出现如下图所示结果： + +![menuconfig2](img/menuconfig2.png) + +选择`yes`键退出。 + +若执行 `make BOARD=kd233 menuconfig`后出现以下界面： + +![menuconfig3](img/menuconfig3.png) + +解决的方法是将终端向上拉伸超过当前界面的三分之二以上，效果如下： + +![menuconfig4](img/menuconfig4.png) + +3.继续在`VScode`的“命令终端”中执行以下命令，进行编译 + +```c +make BOARD=kd233 +``` + +4.如果编译正确无误，会在build文件夹下生成XiZi_kd233.elf、XiZi_kd233.bin文件。其中XiZi_kd233.bin需要烧写到设备中进行运行。 + +>注：最后可以执行以下命令，清除配置文件和编译生成的文件 + +```c +make BOARD=kd233 distclean +``` + +## 3. 烧写及执行 + +连接开发板串口（即Type-C口）到USB接口，拨动电源开关打开开发板，然后使用K-Flash工具进行烧写bin文件。 + +![kd233](img/kd233.jpg) + +执行以下命令安装K-Flash工具 + +``` +sudo apt install python3 python3-pip +sudo pip3 install pyserial +sudo pip3 install pyelftools +sudo pip3 install kflash +``` + +如果最后一步安装kflash出现错误，可以尝试以下命令 + +``` +sudo python -m pip install kflash +sudo python3 -m pip install kflash +sudo pip install kflash +sudo pip2 install kflash +``` + +代码根目录下执行K-Flash工具烧录，-p为USB端口号，视实际情况而定 + +``` +sudo kflash -t build/XiZi_kd233.bin -p /dev/ttyUSB0 +``` + +### 3.1 运行结果 + +如果编译 & 烧写无误，将会在串口终端上看到信息打印输出。 + +![terminal](img/terminal.png) diff --git a/Ubiquitous/XiZi/board/kd233/config.mk b/Ubiquitous/XiZi/board/kd233/config.mk new file mode 100644 index 0000000..29b554c --- /dev/null +++ b/Ubiquitous/XiZi/board/kd233/config.mk @@ -0,0 +1,18 @@ +export CFLAGS := -mcmodel=medany -march=rv64imafdc -mabi=lp64d -fno-common -ffunction-sections -fdata-sections -fstrict-volatile-bitfields -O0 -ggdb -fgnu89-inline -Werror +export AFLAGS := -c -mcmodel=medany -march=rv64imafdc -mabi=lp64d -x assembler-with-cpp -ggdb +export LFLAGS := -mcmodel=medany -march=rv64imafdc -mabi=lp64d -nostartfiles -Wl,--gc-sections,-Map=XiZi_kd233.map,-cref,-u,_start -T $(BSP_ROOT)/link.lds + +export APPLFLAGS := -mcmodel=medany -march=rv64imafdc -mabi=lp64d -nostartfiles -Wl,--gc-sections,-Map=XiZi_app.map,-cref,-u, -T $(BSP_ROOT)/link_userspace.lds + + +export CXXFLAGS := -mcmodel=medany -march=rv64imafdc -mabi=lp64d -fno-common -ffunction-sections -fdata-sections -fstrict-volatile-bitfields -O0 -ggdb -Werror + +export CROSS_COMPILE ?=/opt/gnu-mcu-eclipse/riscv-none-gcc/8.2.0-2.1-20190425-1021/bin/riscv-none-embed- + + +export DEFINES := -DHAVE_CCONFIG_H -DHAVE_SIGINFO + +export ARCH = risc-v +export MCU = k210 + + diff --git a/Ubiquitous/XiZi/board/kd233/img/kd233.jpg b/Ubiquitous/XiZi/board/kd233/img/kd233.jpg new file mode 100644 index 0000000..8206fca Binary files /dev/null and b/Ubiquitous/XiZi/board/kd233/img/kd233.jpg differ diff --git a/Ubiquitous/XiZi/board/kd233/img/main.png b/Ubiquitous/XiZi/board/kd233/img/main.png new file mode 100644 index 0000000..26e304c Binary files /dev/null and b/Ubiquitous/XiZi/board/kd233/img/main.png differ diff --git a/Ubiquitous/XiZi/board/kd233/img/menuconfig1.png b/Ubiquitous/XiZi/board/kd233/img/menuconfig1.png new file mode 100644 index 0000000..da5b269 Binary files /dev/null and b/Ubiquitous/XiZi/board/kd233/img/menuconfig1.png differ diff --git a/Ubiquitous/XiZi/board/kd233/img/menuconfig2.png b/Ubiquitous/XiZi/board/kd233/img/menuconfig2.png new file mode 100644 index 0000000..090885a Binary files /dev/null and b/Ubiquitous/XiZi/board/kd233/img/menuconfig2.png differ diff --git a/Ubiquitous/XiZi/board/kd233/img/menuconfig3.png b/Ubiquitous/XiZi/board/kd233/img/menuconfig3.png new file mode 100644 index 0000000..b5d7f7b Binary files /dev/null and b/Ubiquitous/XiZi/board/kd233/img/menuconfig3.png differ diff --git a/Ubiquitous/XiZi/board/kd233/img/menuconfig4.png b/Ubiquitous/XiZi/board/kd233/img/menuconfig4.png new file mode 100644 index 0000000..fb6ba7d Binary files /dev/null and b/Ubiquitous/XiZi/board/kd233/img/menuconfig4.png differ diff --git a/Ubiquitous/XiZi/board/kd233/img/terminal.png b/Ubiquitous/XiZi/board/kd233/img/terminal.png new file mode 100644 index 0000000..f2cd49a Binary files /dev/null and b/Ubiquitous/XiZi/board/kd233/img/terminal.png differ diff --git a/Ubiquitous/XiZi/board/kd233/img/vscode.jpg b/Ubiquitous/XiZi/board/kd233/img/vscode.jpg new file mode 100644 index 0000000..b9bacff Binary files /dev/null and b/Ubiquitous/XiZi/board/kd233/img/vscode.jpg differ diff --git a/Ubiquitous/XiZi/board/kd233/link.lds b/Ubiquitous/XiZi/board/kd233/link.lds new file mode 100644 index 0000000..79bc98c --- /dev/null +++ b/Ubiquitous/XiZi/board/kd233/link.lds @@ -0,0 +1,115 @@ +/* +* Copyright (c) 2020 AIIT XUOS Lab +* XiUOS is licensed under Mulan PSL v2. +* You can use this software according to the terms and conditions of the Mulan PSL v2. +* You may obtain a copy of Mulan PSL v2 at: +* http://license.coscl.org.cn/MulanPSL2 +* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, +* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, +* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. +* See the Mulan PSL v2 for more details. +*/ + +__STACKSIZE__ = 4096; +OUTPUT_ARCH( "riscv" ) +MEMORY +{ + sram (wxa!ri): ORIGIN = 0x80000000, LENGTH = ( 6 * 1024 * 1024 ) +} + +ENTRY(_begin) +SECTIONS +{ + .start : + { + *(.start); + } > sram + + . = ALIGN(8); + + .text : + { + PROVIDE( _text = ABSOLUTE(.) ); + + *(.text .text.*) /* Normal code */ + *(.rodata .rodata*) /* read-only data (constants) */ + + /* section information for shell */ + . = ALIGN(8); + _shell_command_start = .; + KEEP (*(shellCommand)) + _shell_command_end = .; + . = ALIGN(8); + + PROVIDE(__ctors_start__ = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array)) + PROVIDE(__ctors_end__ = .); + + . = ALIGN(4); + + __isrtbl_idx_start = .; + KEEP(*(.isrtbl.idx)) + __isrtbl_start = .; + KEEP(*(.isrtbl)) + __isrtbl_end = .; + . = ALIGN(8); + + PROVIDE(g_service_table_start = ABSOLUTE(.)); + KEEP(*(.g_service_table)) + PROVIDE(g_service_table_end = ABSOLUTE(.)); + + PROVIDE( _etext = ABSOLUTE(.) ); + } > sram + + . = ALIGN(8); + + .data : + { + PROVIDE( _sdata = ABSOLUTE(.) ); + + /* Writable data segment */ + *(.data .data.*) + + . = ALIGN(8); + PROVIDE( __global_pointer$ = ABSOLUTE(.) + 0x800 ); + + /* Writable small data segment (.sdata segment) */ + *(.sdata .sdata.*) + + PROVIDE( _edata = ABSOLUTE(.) ); + } > sram + + .bss : + { + __bss_start = ABSOLUTE(.); + + /* Writable uninitialized small data segment (.sbss segment)*/ + *(.sbss .sbss.*) + *(.scommon) + + /* Uninitialized writeable data section (.bss segment)*/ + *(.bss .bss.*) + *(COMMON) + + . = ALIGN(8); + __bss_end = ABSOLUTE(.); + } > sram + + .stack : + { + . = ALIGN(64); + PROVIDE(__stack_start__ = ABSOLUTE(.)); + + /* cpu0 stack top site */ + . = . + __STACKSIZE__; + __stack_tp0 = . ; + + /* cpu1 stack top site */ + . = . + __STACKSIZE__; + __stack_tp1 = . ; + + PROVIDE( __stack_end__ = ABSOLUTE(.) ); + } > sram + _end = ABSOLUTE(.); +} diff --git a/Ubiquitous/XiZi/board/kd233/link_userspace.lds b/Ubiquitous/XiZi/board/kd233/link_userspace.lds new file mode 100644 index 0000000..2ff3513 --- /dev/null +++ b/Ubiquitous/XiZi/board/kd233/link_userspace.lds @@ -0,0 +1,76 @@ +/* +* Copyright (c) 2020 AIIT XUOS Lab +* XiUOS is licensed under Mulan PSL v2. +* You can use this software according to the terms and conditions of the Mulan PSL v2. +* You may obtain a copy of Mulan PSL v2 at: +* http://license.coscl.org.cn/MulanPSL2 +* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, +* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, +* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. +* See the Mulan PSL v2 for more details. +*/ + +OUTPUT_ARCH("riscv") +MEMORY +{ + usram (rw) : ORIGIN = 0x80101000, LENGTH = ( 5 * 1024 * 1024 - 4 * 1024 ) /* 5M -4k usram */ +} + +SECTIONS +{ + .userspace : + { + . = ALIGN(8); + KEEP(*(.userspace)) + } > usram + + .text : + { + _ustext = ABSOLUTE(.); + *(.text .text.*) + *(.rodata .rodata*) + *(.glue_7) + *(.glue_7t) + + PROVIDE(__ctors_start__ = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array)) + PROVIDE(__ctors_end__ = .); + + PROVIDE(_uetext = ABSOLUTE(.)); + } > usram + + .init_section : { + _sinit = ABSOLUTE(.); + KEEP(*(.init_array .init_array.*)) + _einit = ABSOLUTE(.); + } > usram + + __uexidx_start = ABSOLUTE(.); + + .ARM.exidx : + { + PROVIDE(__uexidx_start = ABSOLUTE(.)); + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + PROVIDE(__uexidx_end = ABSOLUTE(.)); + } > usram + + _ueronly = ABSOLUTE(.); + + .data : AT(_ueronly) + { + _usdata = ABSOLUTE(.); + *(.data .data.*) + . = ALIGN(8); + _uedata = ABSOLUTE(.); + } > usram + + .bss : { + . = ALIGN(8); + _usbss = ABSOLUTE(.); + *(.bss .bss.*) + *(.sbss .sbss.*) + . = ALIGN(8); + _uebss = ABSOLUTE(.); + } > usram +} \ No newline at end of file diff --git a/Ubiquitous/XiZi/board/kd233/third_party_driver/Kconfig b/Ubiquitous/XiZi/board/kd233/third_party_driver/Kconfig new file mode 100755 index 0000000..555ae4e --- /dev/null +++ b/Ubiquitous/XiZi/board/kd233/third_party_driver/Kconfig @@ -0,0 +1,77 @@ +menuconfig BSP_USING_DMA +bool "Using DMA device" +default y +if BSP_USING_DMA +source "$BSP_DIR/third_party_driver/dma/Kconfig" +endif + +menuconfig BSP_USING_GPIO +bool "Using GPIO device" +default y +select RESOURCES_PIN +if BSP_USING_GPIO +source "$BSP_DIR/third_party_driver/gpio/Kconfig" +endif + +menuconfig BSP_USING_I2C +bool "Using I2C device" +default n +select RESOURCES_I2C +if BSP_USING_I2C +source "$BSP_DIR/third_party_driver/i2c/Kconfig" +endif + +menuconfig BSP_USING_PLIC +bool "Using PLIC device" +default y +if BSP_USING_PLIC +source "$BSP_DIR/third_party_driver/plic/Kconfig" +endif + +menuconfig BSP_USING_RTC +bool "Using RTC device" +default n +select RESOURCES_RTC +if BSP_USING_RTC +source "$BSP_DIR/third_party_driver/rtc/Kconfig" +endif + +menuconfig BSP_USING_SPI +bool "Using SPI device" +default n +select RESOURCES_SPI +select BSP_USING_DMA +if BSP_USING_SPI +source "$BSP_DIR/third_party_driver/spi/Kconfig" +endif + +menuconfig BSP_USING_SYSCLOCK +bool "Using SYSCLOCK device" +default y +if BSP_USING_SYSCLOCK +source "$BSP_DIR/third_party_driver/sys_clock/Kconfig" +endif + +menuconfig BSP_USING_HWTIMER +bool "Using HWTIMER device" +default n +select RESOURCES_HWTIMER +if BSP_USING_HWTIMER +source "$BSP_DIR/third_party_driver/timer/Kconfig" +endif + +menuconfig BSP_USING_UART +bool "Using UART device" +default y +select RESOURCES_SERIAL +if BSP_USING_UART +source "$BSP_DIR/third_party_driver/uart/Kconfig" +endif + +menuconfig BSP_USING_WDT +bool "Using WATCHDOG device" +default y +select RESOURCES_WDT +if BSP_USING_WDT +source "$BSP_DIR/third_party_driver/watchdog/Kconfig" +endif diff --git a/Ubiquitous/XiZi/board/kd233/third_party_driver/Makefile b/Ubiquitous/XiZi/board/kd233/third_party_driver/Makefile new file mode 100644 index 0000000..21d8440 --- /dev/null +++ b/Ubiquitous/XiZi/board/kd233/third_party_driver/Makefile @@ -0,0 +1,63 @@ +SRC_FILES := sleep.c + +ifeq ($(CONFIG_BSP_USING_AUDIO),y) + SRC_DIR += audio +endif + +ifeq ($(CONFIG_BSP_USING_CAMERA),y) + SRC_DIR += camera +endif + +ifeq ($(CONFIG_BSP_USING_DMA),y) + SRC_DIR += dma +endif + +ifeq ($(CONFIG_BSP_USING_GPIO),y) + SRC_DIR += gpio +endif + +ifeq ($(CONFIG_BSP_USING_I2C),y) + SRC_DIR += i2c +endif + +ifeq ($(CONFIG_BSP_USING_I2S),y) + SRC_DIR += i2s +endif + +ifeq ($(CONFIG_BSP_USING_PLIC),y) + SRC_DIR += plic +endif + +ifeq ($(CONFIG_BSP_USING_RTC),y) + SRC_DIR += rtc +endif + +ifeq ($(CONFIG_BSP_USING_SECURITY),y) + SRC_DIR += security +endif + +ifeq ($(CONFIG_BSP_USING_SPI),y) + SRC_DIR += spi +endif + +ifeq ($(CONFIG_BSP_USING_SYSCLOCK),y) + SRC_DIR += sys_clock +endif + +ifeq ($(CONFIG_BSP_USING_HWTIMER),y) + SRC_DIR += timer +endif + +ifeq ($(CONFIG_BSP_USING_UART),y) + SRC_DIR += uart +endif + +ifeq ($(CONFIG_BSP_USING_VIDEO),y) + SRC_DIR += video +endif + +ifeq ($(CONFIG_BSP_USING_WDT),y) + SRC_DIR += watchdog +endif + +include $(KERNEL_ROOT)/compiler.mk diff --git a/Ubiquitous/XiZi/board/kd233/third_party_driver/dma/Kconfig b/Ubiquitous/XiZi/board/kd233/third_party_driver/dma/Kconfig new file mode 100644 index 0000000..8b13789 --- /dev/null +++ b/Ubiquitous/XiZi/board/kd233/third_party_driver/dma/Kconfig @@ -0,0 +1 @@ + diff --git a/Ubiquitous/XiZi/board/kd233/third_party_driver/dma/Makefile b/Ubiquitous/XiZi/board/kd233/third_party_driver/dma/Makefile new file mode 100644 index 0000000..2929b90 --- /dev/null +++ b/Ubiquitous/XiZi/board/kd233/third_party_driver/dma/Makefile @@ -0,0 +1,6 @@ +SRC_FILES := dmac.c + + + + +include $(KERNEL_ROOT)/compiler.mk diff --git a/Ubiquitous/XiZi/board/kd233/third_party_driver/gpio/Kconfig b/Ubiquitous/XiZi/board/kd233/third_party_driver/gpio/Kconfig new file mode 100644 index 0000000..35dce73 --- /dev/null +++ b/Ubiquitous/XiZi/board/kd233/third_party_driver/gpio/Kconfig @@ -0,0 +1,11 @@ +config PIN_BUS_NAME + string "pin bus name" + default "pin" + +config PIN_DRIVER_NAME + string "pin driver name" + default "pin_drv" + +config PIN_DEVICE_NAME + string "pin device name" + default "pin_dev" diff --git a/Ubiquitous/XiZi/board/kd233/third_party_driver/gpio/Makefile b/Ubiquitous/XiZi/board/kd233/third_party_driver/gpio/Makefile new file mode 100644 index 0000000..e017f07 --- /dev/null +++ b/Ubiquitous/XiZi/board/kd233/third_party_driver/gpio/Makefile @@ -0,0 +1,8 @@ +SRC_FILES := connect_gpio.c drv_io_config.c fpioa.c gpio.c gpiohs.c utils.c + + + + + + +include $(KERNEL_ROOT)/compiler.mk diff --git a/Ubiquitous/XiZi/board/kd233/third_party_driver/i2c/Kconfig b/Ubiquitous/XiZi/board/kd233/third_party_driver/i2c/Kconfig new file mode 100644 index 0000000..c935369 --- /dev/null +++ b/Ubiquitous/XiZi/board/kd233/third_party_driver/i2c/Kconfig @@ -0,0 +1,17 @@ +if BSP_USING_I2C + config BSP_I2C_SDA + int "SDA pin number for I2C" + default 15 + config BSP_I2C_SCL + int "SCLK pin number for I2C" + default 17 + config I2C_BUS_NAME_1 + string "i2c bus 1 name" + default "i2c1" + config I2C_DRV_NAME_1 + string "i2c bus 1 driver name" + default "i2c1_drv" + config I2C_1_DEVICE_NAME_0 + string "i2c bus 1 device 0 name" + default "i2c1_dev0" +endif diff --git a/Ubiquitous/XiZi/board/kd233/third_party_driver/i2c/Makefile b/Ubiquitous/XiZi/board/kd233/third_party_driver/i2c/Makefile new file mode 100644 index 0000000..b2bf436 --- /dev/null +++ b/Ubiquitous/XiZi/board/kd233/third_party_driver/i2c/Makefile @@ -0,0 +1,6 @@ +SRC_FILES := connect_i2c.c hardware_i2c.c + + + + +include $(KERNEL_ROOT)/compiler.mk diff --git a/Ubiquitous/XiZi/board/kd233/third_party_driver/include/clint.h b/Ubiquitous/XiZi/board/kd233/third_party_driver/include/clint.h new file mode 100644 index 0000000..58cccf4 --- /dev/null +++ b/Ubiquitous/XiZi/board/kd233/third_party_driver/include/clint.h @@ -0,0 +1,323 @@ +/* Copyright 2018 Canaan Inc. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/** +* @file clint.h +* @brief add from Canaan k210 SDK +* https://canaan-creative.com/developer +* @version 1.0 +* @author AIIT XUOS Lab +* @date 2021-04-25 +*/ + +#ifndef __CLINT_H__ +#define __CLINT_H__ + +#include +#include +#include "platform.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/* clang-format off */ +/* Register address offsets */ +#define CLINT_MSIP (0x0000) +#define CLINT_MSIP_SIZE (0x4) +#define CLINT_MTIMECMP (0x4000) +#define CLINT_MTIMECMP_SIZE (0x8) +#define CLINT_MTIME (0xBFF8) +#define CLINT_MTIME_SIZE (0x8) +/* Max number of cores */ +#define CLINT_MAX_CORES (4095) +/* Real number of cores */ +#define CLINT_NUM_CORES (2) +/* Clock frequency division factor */ +#define CLINT_CLOCK_DIV (50) +/* clang-format on */ + +/** + * @brief MSIP Registers + * + * Machine-mode software interrupts are generated by writing to a + * per-core memory-mapped control register. The msip registers are + * 32-bit wide WARL registers, where the LSB is reflected in the + * msip bit of the associated core’s mip register. Other bits in + * the msip registers are hardwired to zero. The mapping supports + * up to 4095 machine-mode cores. + */ +typedef struct _clint_msip +{ + uint32_t msip : 1; /*!< Bit 0 is msip */ + uint32_t zero : 31; /*!< Bits [32:1] is 0 */ +} __attribute__((packed, aligned(4))) clint_msip_t; + +/** + * @brief Timer compare Registers Machine-mode timer interrupts are + * generated by a real-time counter and a per-core comparator. The + * mtime register is a 64-bit read-only register that contains the + * current value of the real-time counter. Each mtimecmp register + * holds its core’s time comparator. A timer interrupt is pending + * whenever mtime is greater than or equal to the value in a + * core’s mtimecmp register. The timer interrupt is reflected in + * the mtip bit of the associated core’s mip register. + */ +typedef uint64_t clint_mtimecmp_t; + +/** + * @brief Timer Registers + * + * The mtime register has a 64-bit precision on all RV32, RV64, + * and RV128 systems. Platforms provide a 64-bit memory-mapped + * machine-mode timer compare register (mtimecmp), which causes a + * timer interrupt to be posted when the mtime register contains a + * value greater than or equal to the value in the mtimecmp + * register. The interrupt remains posted until it is cleared by + * writing the mtimecmp register. The interrupt will only be taken + * if interrupts are enabled and the MTIE bit is set in the mie + * register. + */ +typedef uint64_t clint_mtime_t; + +/** + * @brief CLINT object + * + * Coreplex-Local INTerrupts, which includes software interrupts, + * local timer interrupts, and other interrupts routed directly to + * a core. + */ +typedef struct _clint +{ + /* 0x0000 to 0x3FF8, MSIP Registers */ + clint_msip_t msip[CLINT_MAX_CORES]; + /* Resverd space, do not use */ + uint32_t resv0; + /* 0x4000 to 0xBFF0, Timer Compare Registers */ + clint_mtimecmp_t mtimecmp[CLINT_MAX_CORES]; + /* 0xBFF8, Time Register */ + clint_mtime_t mtime; +} __attribute__((packed, aligned(4))) clint_t; + +/** + * @brief Clint object instanse + */ +extern volatile clint_t* const clint; + +/** + * @brief Definitions for the timer callbacks + */ +typedef int (*clint_timer_callback_t)(void *ctx); + +/** + * @brief Definitions for local interprocessor interrupt callbacks + */ +typedef int (*clint_ipi_callback_t)(void *ctx); + +typedef struct _clint_timer_instance +{ + uint64_t interval; + uint64_t cycles; + uint64_t single_shot; + clint_timer_callback_t callback; + void *ctx; +} clint_timer_instance_t; + +typedef struct _clint_ipi_instance +{ + clint_ipi_callback_t callback; + void *ctx; +} clint_ipi_instance_t; + +/** + * @brief Get the time form CLINT timer register + * + * @note The CLINT must init to get right time + * + * @return 64bit Time + */ +uint64_t clint_get_time(void); + +/** + * @brief Init the CLINT timer + * + * @note MIP_MTIP will be clear after init. The MSTATUS_MIE must set by + * user. + * + * @return result + * - 0 Success + * - Other Fail + */ +int clint_timer_init(void); + +/** + * @brief Stop the CLINT timer + * + * @note MIP_MTIP will be clear after stop + * + * @return result + * - 0 Success + * - Other Fail + */ +int clint_timer_stop(void); + +/** + * @brief Start the CLINT timer + * + * @param[in] interval The interval with Millisecond(ms) + * @param[in] single_shot Single shot or repeat + * + * @return result + * - 0 Success + * - Other Fail + */ +int clint_timer_start(uint64_t interval, int single_shot); + +/** + * @brief Get the interval of timer + * + * @return The interval with Millisecond(ms) + */ +uint64_t clint_timer_get_interval(void); + +/** + * @brief Set the interval with Millisecond(ms) + * + * @param[in] interval The interval with Millisecond(ms) + * + * @return result + * - 0 Success + * - Other Fail + */ +int clint_timer_set_interval(uint64_t interval); + +/** + * @brief Get whether the timer is a single shot timer + * + * @return result + * - 0 It is a repeat timer + * - 1 It is a single shot timer + */ +int clint_timer_get_single_shot(void); + +/** + * @brief Set the timer working as a single shot timer or repeat timer + * + * @param[in] single_shot Single shot or repeat + * + * @return result + * - 0 Success + * - Other Fail + */ +int clint_timer_set_single_shot(int single_shot); + +/** + * @brief Set user callback function when timer is timeout + * + * @param[in] callback The callback function + * @param[in] ctx The context + * + * @return result + * - 0 Success + * - Other Fail + */ +int clint_timer_register(clint_timer_callback_t callback, void *ctx); + +/** + * @brief Deregister user callback function + * + * @return result + * - 0 Success + * - Other Fail + */ +int clint_timer_unregister(void); + +/** + * @brief Initialize local interprocessor interrupt + * + * @return result + * - 0 Success + * - Other Fail + */ +int clint_ipi_init(void); + +/** + * @brief Enable local interprocessor interrupt + * + * @return result + * - 0 Success + * - Other Fail + */ +int clint_ipi_enable(void); + +/** + * @brief Disable local interprocessor interrupt + * + * @return result + * - 0 Success + * - Other Fail + */ +int clint_ipi_disable(void); + +/** + * @brief Send local interprocessor interrupt to core by core id + * + * @param[in] core_id The core identifier + * + * @return result + * - 0 Success + * - Other Fail + */ +int clint_ipi_send(size_t core_id); + +/** + * @brief Clear local interprocessor interrupt + * + * @param[in] core_id The core identifier + * + * @return result + * - 1 An IPI was pending + * - 0 Non IPI was pending + * - -1 Fail + */ +int clint_ipi_clear(size_t core_id); + +/** + * @brief Set user callback function when interprocessor interrupt + * + * @param[in] callback The callback function + * @param[in] ctx The context + * + * @return result + * - 0 Success + * - Other Fail + */ +int clint_ipi_register(clint_ipi_callback_t callback, void *ctx); + +/** + * @brief Deregister user callback function + * + * @return result + * - 0 Success + * - Other Fail + */ +int clint_ipi_unregister(void); + +#ifdef __cplusplus +} +#endif + +#endif /* __CLINT_H__ */ + diff --git a/Ubiquitous/XiZi/board/kd233/third_party_driver/include/connect_gpio.h b/Ubiquitous/XiZi/board/kd233/third_party_driver/include/connect_gpio.h new file mode 100644 index 0000000..b6bae7b --- /dev/null +++ b/Ubiquitous/XiZi/board/kd233/third_party_driver/include/connect_gpio.h @@ -0,0 +1,36 @@ +/* +* Copyright (c) 2020 AIIT XUOS Lab +* XiUOS is licensed under Mulan PSL v2. +* You can use this software according to the terms and conditions of the Mulan PSL v2. +* You may obtain a copy of Mulan PSL v2 at: +* http://license.coscl.org.cn/MulanPSL2 +* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, +* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, +* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. +* See the Mulan PSL v2 for more details. +*/ + +/** +* @file connect_gpio.h +* @brief define kd233-board gpio function and struct +* @version 1.0 +* @author AIIT XUOS Lab +* @date 2021-04-25 +*/ + +#ifndef CONNECT_GPIO_H +#define CONNECT_GPIO_H + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +int HwGpioInit(void); + +#ifdef __cplusplus +} +#endif + +#endif \ No newline at end of file diff --git a/Ubiquitous/XiZi/board/kd233/third_party_driver/include/connect_hwtimer.h b/Ubiquitous/XiZi/board/kd233/third_party_driver/include/connect_hwtimer.h new file mode 100644 index 0000000..1303bff --- /dev/null +++ b/Ubiquitous/XiZi/board/kd233/third_party_driver/include/connect_hwtimer.h @@ -0,0 +1,37 @@ +/* +* Copyright (c) 2020 AIIT XUOS Lab +* XiUOS is licensed under Mulan PSL v2. +* You can use this software according to the terms and conditions of the Mulan PSL v2. +* You may obtain a copy of Mulan PSL v2 at: +* http://license.coscl.org.cn/MulanPSL2 +* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, +* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, +* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. +* See the Mulan PSL v2 for more details. +*/ + +/** +* @file connect_hwtimer.h +* @brief define kd233-board hwtimer function and struct +* @version 1.0 +* @author AIIT XUOS Lab +* @date 2021-04-25 +*/ + +#ifndef CONNECT_HWTIMER_H +#define CONNECT_HWTIMER_H + +#include +#include "hardware_hwtimer.h" + +#ifdef __cplusplus +extern "C" { +#endif + +int HwTimerInit(void); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/Ubiquitous/XiZi/board/kd233/third_party_driver/include/connect_i2c.h b/Ubiquitous/XiZi/board/kd233/third_party_driver/include/connect_i2c.h new file mode 100644 index 0000000..650dafa --- /dev/null +++ b/Ubiquitous/XiZi/board/kd233/third_party_driver/include/connect_i2c.h @@ -0,0 +1,36 @@ +/* +* Copyright (c) 2020 AIIT XUOS Lab +* XiUOS is licensed under Mulan PSL v2. +* You can use this software according to the terms and conditions of the Mulan PSL v2. +* You may obtain a copy of Mulan PSL v2 at: +* http://license.coscl.org.cn/MulanPSL2 +* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, +* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, +* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. +* See the Mulan PSL v2 for more details. +*/ + +/** +* @file connect_i2c.h +* @brief define kd233-board i2c function and struct +* @version 1.0 +* @author AIIT XUOS Lab +* @date 2021-04-25 +*/ + +#ifndef CONNECT_I2C_H +#define CONNECT_I2C_H + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +int HwI2cInit(void); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/Ubiquitous/XiZi/board/kd233/third_party_driver/include/connect_rtc.h b/Ubiquitous/XiZi/board/kd233/third_party_driver/include/connect_rtc.h new file mode 100644 index 0000000..fb1da41 --- /dev/null +++ b/Ubiquitous/XiZi/board/kd233/third_party_driver/include/connect_rtc.h @@ -0,0 +1,36 @@ +/* +* Copyright (c) 2020 AIIT XUOS Lab +* XiUOS is licensed under Mulan PSL v2. +* You can use this software according to the terms and conditions of the Mulan PSL v2. +* You may obtain a copy of Mulan PSL v2 at: +* http://license.coscl.org.cn/MulanPSL2 +* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, +* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, +* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. +* See the Mulan PSL v2 for more details. +*/ + +/** +* @file connect_rtc.h +* @brief define kd233-board rtc function and struct +* @version 1.0 +* @author AIIT XUOS Lab +* @date 2021-04-25 +*/ + +#ifndef CONNECT_RTC_H +#define CONNECT_RTC_H + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +int HwRtcInit(void); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/Ubiquitous/XiZi/board/kd233/third_party_driver/include/connect_spi.h b/Ubiquitous/XiZi/board/kd233/third_party_driver/include/connect_spi.h new file mode 100644 index 0000000..6df5442 --- /dev/null +++ b/Ubiquitous/XiZi/board/kd233/third_party_driver/include/connect_spi.h @@ -0,0 +1,36 @@ +/* +* Copyright (c) 2020 AIIT XUOS Lab +* XiUOS is licensed under Mulan PSL v2. +* You can use this software according to the terms and conditions of the Mulan PSL v2. +* You may obtain a copy of Mulan PSL v2 at: +* http://license.coscl.org.cn/MulanPSL2 +* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, +* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, +* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. +* See the Mulan PSL v2 for more details. +*/ + +/** +* @file connect_spi.h +* @brief define kd233-board spi function and struct +* @version 1.0 +* @author AIIT XUOS Lab +* @date 2021-04-25 +*/ + +#ifndef CONNECT_SPI_H +#define CONNECT_SPI_H + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +int HwSpiInit(void); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/Ubiquitous/XiZi/board/kd233/third_party_driver/include/connect_uart.h b/Ubiquitous/XiZi/board/kd233/third_party_driver/include/connect_uart.h new file mode 100644 index 0000000..8a336c3 --- /dev/null +++ b/Ubiquitous/XiZi/board/kd233/third_party_driver/include/connect_uart.h @@ -0,0 +1,40 @@ +/* +* Copyright (c) 2020 AIIT XUOS Lab +* XiUOS is licensed under Mulan PSL v2. +* You can use this software according to the terms and conditions of the Mulan PSL v2. +* You may obtain a copy of Mulan PSL v2 at: +* http://license.coscl.org.cn/MulanPSL2 +* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, +* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, +* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. +* See the Mulan PSL v2 for more details. +*/ + +/** +* @file connect_uart.h +* @brief define kd233-board uart function and struct +* @version 1.0 +* @author AIIT XUOS Lab +* @date 2021-04-25 +*/ + +#ifndef CONNECT_UART_H +#define CONNECT_UART_H + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +#define KERNEL_CONSOLE_BUS_NAME SERIAL_BUS_NAME_0 +#define KERNEL_CONSOLE_DRV_NAME SERIAL_DRV_NAME_0 +#define KERNEL_CONSOLE_DEVICE_NAME SERIAL_0_DEVICE_NAME_0 + +int HwUartInit(void); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/Ubiquitous/XiZi/board/kd233/third_party_driver/include/connect_wdt.h b/Ubiquitous/XiZi/board/kd233/third_party_driver/include/connect_wdt.h new file mode 100644 index 0000000..d0053bc --- /dev/null +++ b/Ubiquitous/XiZi/board/kd233/third_party_driver/include/connect_wdt.h @@ -0,0 +1,36 @@ +/* +* Copyright (c) 2020 AIIT XUOS Lab +* XiUOS is licensed under Mulan PSL v2. +* You can use this software according to the terms and conditions of the Mulan PSL v2. +* You may obtain a copy of Mulan PSL v2 at: +* http://license.coscl.org.cn/MulanPSL2 +* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, +* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, +* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. +* See the Mulan PSL v2 for more details. +*/ + +/** +* @file connect_wdt.h +* @brief define kd233-board wdt function and struct +* @version 1.0 +* @author AIIT XUOS Lab +* @date 2021-04-25 +*/ + +#ifndef CONNECT_WDT_H +#define CONNECT_WDT_H + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +int HwWdtInit(void); + +#ifdef __cplusplus +} +#endif + +#endif \ No newline at end of file diff --git a/Ubiquitous/XiZi/board/kd233/third_party_driver/rtc/Kconfig b/Ubiquitous/XiZi/board/kd233/third_party_driver/rtc/Kconfig new file mode 100644 index 0000000..e853dd4 --- /dev/null +++ b/Ubiquitous/XiZi/board/kd233/third_party_driver/rtc/Kconfig @@ -0,0 +1,11 @@ +if BSP_USING_RTC + config RTC_BUS_NAME + string "rtc bus name" + default "rtc" + config RTC_DRV_NAME + string "rtc bus driver name" + default "rtc_drv" + config RTC_DEVICE_NAME + string "rtc bus device name" + default "rtc_dev" +endif diff --git a/Ubiquitous/XiZi/board/kd233/third_party_driver/rtc/Makefile b/Ubiquitous/XiZi/board/kd233/third_party_driver/rtc/Makefile new file mode 100644 index 0000000..23575e6 --- /dev/null +++ b/Ubiquitous/XiZi/board/kd233/third_party_driver/rtc/Makefile @@ -0,0 +1,3 @@ +SRC_FILES := connect_rtc.c hardware_rtc.c + +include $(KERNEL_ROOT)/compiler.mk diff --git a/Ubiquitous/XiZi/board/kd233/third_party_driver/spi/Kconfig b/Ubiquitous/XiZi/board/kd233/third_party_driver/spi/Kconfig new file mode 100644 index 0000000..4ccf9f3 --- /dev/null +++ b/Ubiquitous/XiZi/board/kd233/third_party_driver/spi/Kconfig @@ -0,0 +1,67 @@ +config BSP_USING_SPI1 +bool "Using spi1 " +default y + + +if BSP_USING_SPI1 + config SPI_BUS_NAME_1 + string "spi bus 1 name" + default "spi1" + config SPI_1_DRV_NAME + string "spi bus 1 driver name" + default "spi1_drv" + config BSP_SPI1_CLK_PIN + int "spi1 clk pin number" + default 29 + config BSP_SPI1_D0_PIN + int "spi1 d0 pin number" + default 30 + config BSP_SPI1_D1_PIN + int "spi1 d1 pin number" + default 31 + menuconfig BSP_SPI1_USING_SS0 + bool "SPI1 Enable SS0" + default y + if BSP_SPI1_USING_SS0 + config SPI_1_DEVICE_NAME_0 + string "spi bus 1 device 0 name" + default "spi1_dev0" + config BSP_SPI1_SS0_PIN + int "spi1 ss0 pin number" + default 32 + endif + menuconfig BSP_SPI1_USING_SS1 + bool "SPI1 Enable SS1" + default y + if BSP_SPI1_USING_SS1 + config SPI_1_DEVICE_NAME_1 + string "spi bus 1 device 1 name" + default "spi1_dev1" + config BSP_SPI1_SS1_PIN + int "spi1 ss1 pin number" + default 33 + endif + menuconfig BSP_SPI1_USING_SS2 + bool "SPI1 Enable SS2" + default n + if BSP_SPI1_USING_SS2 + config SPI_1_DEVICE_NAME_2 + string "spi bus 1 device 2 name" + default "spi1_dev2" + config BSP_SPI1_SS2_PIN + int "spi1 ss2 pin number" + default 26 + endif + menuconfig BSP_SPI1_USING_SS3 + bool "SPI1 Enable SS3" + default n + if BSP_SPI1_USING_SS3 + config SPI_1_DEVICE_NAME_3 + string "spi bus 1 device 3 name" + default "spi1_dev3" + config BSP_SPI1_SS3_PIN + int "spi1 ss3 pin number" + default 27 + endif +endif + diff --git a/Ubiquitous/XiZi/board/kd233/third_party_driver/spi/Makefile b/Ubiquitous/XiZi/board/kd233/third_party_driver/spi/Makefile new file mode 100644 index 0000000..010350e --- /dev/null +++ b/Ubiquitous/XiZi/board/kd233/third_party_driver/spi/Makefile @@ -0,0 +1,6 @@ +SRC_FILES := connect_spi.c hardware_spi.c + + + + +include $(KERNEL_ROOT)/compiler.mk diff --git a/Ubiquitous/XiZi/board/kd233/third_party_driver/sys_clock/Kconfig b/Ubiquitous/XiZi/board/kd233/third_party_driver/sys_clock/Kconfig new file mode 100644 index 0000000..8b13789 --- /dev/null +++ b/Ubiquitous/XiZi/board/kd233/third_party_driver/sys_clock/Kconfig @@ -0,0 +1 @@ + diff --git a/Ubiquitous/XiZi/board/kd233/third_party_driver/sys_clock/Makefile b/Ubiquitous/XiZi/board/kd233/third_party_driver/sys_clock/Makefile new file mode 100644 index 0000000..ef5fda1 --- /dev/null +++ b/Ubiquitous/XiZi/board/kd233/third_party_driver/sys_clock/Makefile @@ -0,0 +1,6 @@ +SRC_FILES := sysctl.c + + + + +include $(KERNEL_ROOT)/compiler.mk diff --git a/Ubiquitous/XiZi/board/kd233/third_party_driver/timer/Kconfig b/Ubiquitous/XiZi/board/kd233/third_party_driver/timer/Kconfig new file mode 100644 index 0000000..fdc67b1 --- /dev/null +++ b/Ubiquitous/XiZi/board/kd233/third_party_driver/timer/Kconfig @@ -0,0 +1,19 @@ +if BSP_USING_HWTIMER + config HWTIMER_BUS_NAME_1 + string "hwtimer bus name" + default "hwtim1" + + menuconfig ENABLE_TIM1 + bool "enable TIM1" + default y + + if ENABLE_TIM1 + config HWTIMER_1_DEVICE_NAME_1 + string "TIM1 dev name" + default "hwtim1_dev1" + + config HWTIMER_DRIVER_NAME_1 + string "TIM1 drv name" + default "hwtim1_drv" + endif +endif diff --git a/Ubiquitous/XiZi/board/kd233/third_party_driver/timer/Makefile b/Ubiquitous/XiZi/board/kd233/third_party_driver/timer/Makefile new file mode 100644 index 0000000..06b6e3a --- /dev/null +++ b/Ubiquitous/XiZi/board/kd233/third_party_driver/timer/Makefile @@ -0,0 +1,3 @@ +SRC_FILES := hardware_hwtimer.c connect_hwtimer.c + +include $(KERNEL_ROOT)/compiler.mk diff --git a/Ubiquitous/XiZi/board/kd233/third_party_driver/timer/connect_hwtimer.c b/Ubiquitous/XiZi/board/kd233/third_party_driver/timer/connect_hwtimer.c new file mode 100644 index 0000000..7df6ac7 --- /dev/null +++ b/Ubiquitous/XiZi/board/kd233/third_party_driver/timer/connect_hwtimer.c @@ -0,0 +1,155 @@ +/* +* Copyright (c) 2020 AIIT XUOS Lab +* XiUOS is licensed under Mulan PSL v2. +* You can use this software according to the terms and conditions of the Mulan PSL v2. +* You may obtain a copy of Mulan PSL v2 at: +* http://license.coscl.org.cn/MulanPSL2 +* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, +* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, +* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. +* See the Mulan PSL v2 for more details. +*/ + +/** +* @file connect_hwtimer.c +* @brief support kd233-board hwtimer function and register to bus framework +* @version 1.0 +* @author AIIT XUOS Lab +* @date 2021-04-25 +*/ + +#include +#include +#include +#include +#include +#include +#include +#include "connect_hwtimer.h" + +static struct HwtimerCallBackInfo *ptim2_cb_info = NULL; + +int timer_callback(void *ctx) +{ + if (ptim2_cb_info) { + if (ptim2_cb_info->timeout_callback) { + ptim2_cb_info->timeout_callback(ptim2_cb_info->param); + } + } + return 0; +} + +uint32 HwtimerOpen(void *dev) +{ + struct HwtimerHardwareDevice *hwtimer_dev = dev; + + ptim2_cb_info = &hwtimer_dev->hwtimer_param.cb_info; + + plic_init(); + sysctl_enable_irq(); + timer_init(TIMER_DEVICE_1); + + size_t real_time = timer_set_interval(TIMER_DEVICE_1, TIMER_CHANNEL_1, hwtimer_dev->hwtimer_param.period_millisecond *1000); + KPrintf("timer_set_interval -- real_time : %ld\n", real_time); + timer_irq_register(TIMER_DEVICE_1, TIMER_CHANNEL_1, !hwtimer_dev->hwtimer_param.repeat, 1, timer_callback, NULL); + + timer_set_enable(TIMER_DEVICE_1, TIMER_CHANNEL_1, 1); + + return EOK; +} + +uint32 HwtimerClose(void *dev) +{ + timer_set_enable(TIMER_DEVICE_1, TIMER_CHANNEL_1, 0); + + return EOK; +} + +/*manage the hwtimer device operations*/ +static const struct HwtimerDevDone dev_done = +{ + .open = HwtimerOpen, + .close = HwtimerClose, + .write = NONE, + .read = NONE, +}; + +/*Init hwtimer bus*/ +static int BoardHwtimerBusInit(struct HwtimerBus *hwtimer_bus, struct HwtimerDriver *hwtimer_driver) +{ + x_err_t ret = EOK; + + /*Init the hwtimer bus */ + ret = HwtimerBusInit(hwtimer_bus, HWTIMER_BUS_NAME_1); + if (EOK != ret) { + KPrintf("board_hwtimer_init HwtimerBusInit error %d\n", ret); + return ERROR; + } + + /*Init the hwtimer driver*/ + hwtimer_driver->configure = NONE; + ret = HwtimerDriverInit(hwtimer_driver, HWTIMER_DRIVER_NAME_1); + if (EOK != ret) { + KPrintf("board_hwtimer_init HwtimerDriverInit error %d\n", ret); + return ERROR; + } + + /*Attach the hwtimer driver to the hwtimer bus*/ + ret = HwtimerDriverAttachToBus(HWTIMER_DRIVER_NAME_1, HWTIMER_BUS_NAME_1); + if (EOK != ret) { + KPrintf("board_hwtimer_init USEDriverAttachToBus error %d\n", ret); + return ERROR; + } + + return ret; +} + +/*Attach the hwtimer device to the hwtimer bus*/ +static int BoardHwtimerDevBend(void) +{ + x_err_t ret = EOK; + static struct HwtimerHardwareDevice hwtimer_device_0; + memset(&hwtimer_device_0, 0, sizeof(struct HwtimerHardwareDevice)); + + hwtimer_device_0.dev_done = &dev_done; + + ret = HwtimerDeviceRegister(&hwtimer_device_0, NONE, HWTIMER_1_DEVICE_NAME_1); + if (EOK != ret) { + KPrintf("board_hwtimer_init HWTIMERDeviceInit device %s error %d\n", HWTIMER_1_DEVICE_NAME_1, ret); + return ERROR; + } + + ret = HwtimerDeviceAttachToBus(HWTIMER_1_DEVICE_NAME_1, HWTIMER_BUS_NAME_1); + if (EOK != ret) { + KPrintf("board_hwtimer_init HwtimerDeviceAttachToBus device %s error %d\n", HWTIMER_1_DEVICE_NAME_1, ret); + return ERROR; + } + + return ret; +} + +/*K210 BOARD HWTIMER INIT*/ +int HwTimerInit(void) +{ + x_err_t ret = EOK; + static struct HwtimerBus hwtimer_bus; + memset(&hwtimer_bus, 0, sizeof(struct HwtimerBus)); + + static struct HwtimerDriver hwtimer_driver; + memset(&hwtimer_driver, 0, sizeof(struct HwtimerDriver)); + + + ret = BoardHwtimerBusInit(&hwtimer_bus, &hwtimer_driver); + if (EOK != ret) { + KPrintf("board_hwtimer_Init error ret %u\n", ret); + return ERROR; + } + + ret = BoardHwtimerDevBend(); + if (EOK != ret) { + KPrintf("board_hwtimer_Init error ret %u\n", ret); + return ERROR; + } + + return ret; +} diff --git a/Ubiquitous/XiZi/board/kd233/third_party_driver/uart/Kconfig b/Ubiquitous/XiZi/board/kd233/third_party_driver/uart/Kconfig new file mode 100644 index 0000000..08e75e0 --- /dev/null +++ b/Ubiquitous/XiZi/board/kd233/third_party_driver/uart/Kconfig @@ -0,0 +1,77 @@ +menuconfig BSP_USING_UART_HS + bool "Enable High Speed UART" + default y + if BSP_USING_UART_HS + config SERIAL_BUS_NAME_0 + string "serial high speed bus 0 name" + default "uart0" + config SERIAL_DRV_NAME_0 + string "serial high speed bus 0 driver name" + default "uart0_drv" + config SERIAL_0_DEVICE_NAME_0 + string "serial high speed bus 0 device 0 name" + default "uart0_dev0" + endif + +menuconfig BSP_USING_UART1 + bool "Enable UART1" + default y + if BSP_USING_UART1 + config BSP_UART1_TXD_PIN + int "uart1 TXD pin number" + default 20 + config BSP_UART1_RXD_PIN + int "uart1 RXD pin number" + default 21 + config SERIAL_BUS_NAME_1 + string "serial bus 1 name" + default "uart1" + config SERIAL_DRV_NAME_1 + string "serial bus 1 driver name" + default "uart1_drv" + config SERIAL_1_DEVICE_NAME_0 + string "serial bus 1 device 0 name" + default "uart1_dev1" + endif + +menuconfig BSP_USING_UART2 + bool "Enable UART2" + default y + if BSP_USING_UART2 + config BSP_UART2_TXD_PIN + int "uart2 TXD pin number" + default 28 + config BSP_UART2_RXD_PIN + int "uart2 RXD pin number" + default 27 + config SERIAL_BUS_NAME_2 + string "serial bus 2 name" + default "uart2" + config SERIAL_DRV_NAME_2 + string "serial bus 2 driver name" + default "uart2_drv" + config SERIAL_2_DEVICE_NAME_0 + string "serial bus 2 device 0 name" + default "uart2_dev2" + endif + +menuconfig BSP_USING_UART3 + bool "Enable UART3" + default y + if BSP_USING_UART3 + config BSP_UART3_TXD_PIN + int "uart3 TXD pin number" + default 22 + config BSP_UART3_RXD_PIN + int "uart3 RXD pin number" + default 23 + config SERIAL_BUS_NAME_3 + string "serial bus 3 name" + default "uart3" + config SERIAL_DRV_NAME_3 + string "serial bus 3 driver name" + default "uart3_drv" + config SERIAL_3_DEVICE_NAME_0 + string "serial bus 3 device 0 name" + default "uart3_dev3" + endif diff --git a/Ubiquitous/XiZi/board/kd233/third_party_driver/uart/Makefile b/Ubiquitous/XiZi/board/kd233/third_party_driver/uart/Makefile new file mode 100644 index 0000000..7696ffa --- /dev/null +++ b/Ubiquitous/XiZi/board/kd233/third_party_driver/uart/Makefile @@ -0,0 +1,3 @@ +SRC_FILES := connect_uart.c + +include $(KERNEL_ROOT)/compiler.mk diff --git a/Ubiquitous/XiZi/board/kd233/third_party_driver/watchdog/Kconfig b/Ubiquitous/XiZi/board/kd233/third_party_driver/watchdog/Kconfig new file mode 100644 index 0000000..e801fa0 --- /dev/null +++ b/Ubiquitous/XiZi/board/kd233/third_party_driver/watchdog/Kconfig @@ -0,0 +1,34 @@ +menuconfig BSP_USING_WDT0 +bool "Using watchdog 0 " +default n +if BSP_USING_WDT0 +config WDT_BUS_NAME_0 + string "watchdog bus 0 name" + default "wdt0" + +config WDT_DRIVER_NAME_0 + string "watchdog driver 0 name" + default "wdt0_drv" + +config WDT_0_DEVICE_NAME_0 + string "watchdog device 0 name" + default "wdt0_dev0" +endif + +menuconfig BSP_USING_WDT1 +bool "Using watchdog 1 " +default n +if BSP_USING_WDT1 +config WDT_BUS_NAME_1 + string "watchdog bus 1 name" + default "wdt1" + +config WDT_DRIVER_NAME_1 + string "watchdog driver 1 name" + default "wdt1_drv" + +config WDT_1_DEVICE_NAME_1 + string "watchdog device 1 name" + default "wdt1_dev1" +endif + diff --git a/Ubiquitous/XiZi/board/kd233/third_party_driver/watchdog/Makefile b/Ubiquitous/XiZi/board/kd233/third_party_driver/watchdog/Makefile new file mode 100644 index 0000000..c4842fd --- /dev/null +++ b/Ubiquitous/XiZi/board/kd233/third_party_driver/watchdog/Makefile @@ -0,0 +1,6 @@ +SRC_FILES := wdt.c connect_wdt.c + + + + +include $(KERNEL_ROOT)/compiler.mk diff --git a/Ubiquitous/XiZi/board/kd233/third_party_driver/watchdog/connect_wdt.c b/Ubiquitous/XiZi/board/kd233/third_party_driver/watchdog/connect_wdt.c new file mode 100644 index 0000000..1ebcd6b --- /dev/null +++ b/Ubiquitous/XiZi/board/kd233/third_party_driver/watchdog/connect_wdt.c @@ -0,0 +1,172 @@ +/* +* Copyright (c) 2020 AIIT XUOS Lab +* XiUOS is licensed under Mulan PSL v2. +* You can use this software according to the terms and conditions of the Mulan PSL v2. +* You may obtain a copy of Mulan PSL v2 at: +* http://license.coscl.org.cn/MulanPSL2 +* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, +* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, +* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. +* See the Mulan PSL v2 for more details. +*/ + +/** +* @file connect_wdt.c +* @brief support kd233-board watchdog function and register to bus framework +* @version 1.0 +* @author AIIT XUOS Lab +* @date 2021-04-25 +*/ + +#include "wdt.h" +#include "connect_wdt.h" + +static uint32 WdtOpen(void *dev) +{ + NULL_PARAM_CHECK(dev); + + wdt_device_number_t id; + struct WdtHardwareDevice *wdt = (struct WdtHardwareDevice *)dev; + id = *(wdt_device_number_t *)wdt->private_data; + + wdt_init(id, 4095, NONE, NONE); + return EOK; +} + +static uint32 WdtConfigure(void *drv, struct BusConfigureInfo *args) +{ + NULL_PARAM_CHECK(drv); + NULL_PARAM_CHECK(args); + + struct WdtDriver *wdt = (struct WdtDriver *)drv; + wdt_device_number_t id = *(wdt_device_number_t *)wdt->private_data; + + switch (args->configure_cmd) + { + case OPER_WDT_SET_TIMEOUT: + if (wdt_init(id, (uint64_t)*(int *)args->private_data, NONE, NONE) == 0) + { + return ERROR; + } + break; + case OPER_WDT_KEEPALIVE: + wdt_feed(id); + break; + default: + return ERROR; + } + return EOK; +} + +static const struct WdtDevDone dev_done = +{ + WdtOpen, + NONE, + NONE, + NONE, +}; + +int HwWdtInit(void) +{ + wdt_device_number_t id; + + x_err_t ret = EOK; + +#ifdef BSP_USING_WDT0 + { + static struct WdtBus wdt0; + + ret = WdtBusInit(&wdt0, WDT_BUS_NAME_0); + if(ret != EOK) + { + KPrintf("Watchdog bus init error %d\n", ret); + return ERROR; + } + + static struct WdtDriver drv0; + drv0.configure = WdtConfigure; + id = WDT_DEVICE_0; + drv0.private_data = &id; + + ret = WdtDriverInit(&drv0, WDT_DRIVER_NAME_0); + if(ret != EOK) + { + KPrintf("Watchdog driver init error %d\n", ret); + return ERROR; + } + ret = WdtDriverAttachToBus(WDT_DRIVER_NAME_0, WDT_BUS_NAME_0); + if(ret != EOK) + { + KPrintf("Watchdog driver attach error %d\n", ret); + return ERROR; + } + + static struct WdtHardwareDevice dev0; + dev0.dev_done = &dev_done; + dev0.private_data = &id; + + ret = WdtDeviceRegister(&dev0, WDT_0_DEVICE_NAME_0); + if(ret != EOK) + { + KPrintf("Watchdog device register error %d\n", ret); + return ERROR; + } + ret = WdtDeviceAttachToBus(WDT_0_DEVICE_NAME_0, WDT_BUS_NAME_0); + if(ret != EOK) + { + KPrintf("Watchdog device register error %d\n", ret); + return ERROR; + } + } +#endif + +#ifdef BSP_USING_WDT1 + { + static struct WdtBus wdt1; + + ret = WdtBusInit(&wdt1, WDT_BUS_NAME_1); + if(ret != EOK) + { + KPrintf("Watchdog bus init error %d\n", ret); + return ERROR; + } + + static struct WdtDriver drv1; + drv1.configure = WdtConfigure; + id = WDT_DEVICE_1; + drv1.private_data = &id; + + ret = WdtDriverInit(&drv1, WDT_DRIVER_NAME_1); + if(ret != EOK) + { + KPrintf("Watchdog driver init error %d\n", ret); + return ERROR; + } + ret = WdtDriverAttachToBus(WDT_DRIVER_NAME_1, WDT_BUS_NAME_1); + if(ret != EOK) + { + KPrintf("Watchdog driver attach error %d\n", ret); + return ERROR; + } + + static struct WdtHardwareDevice dev1; + dev1.dev_done = &dev_done; + dev1.private_data = &id; + + ret = WdtDeviceRegister(&dev1, WDT_1_DEVICE_NAME_1); + if(ret != EOK) + { + KPrintf("Watchdog device register error %d\n", ret); + return ERROR; + } + ret = WdtDeviceAttachToBus(WDT_1_DEVICE_NAME_1, WDT_BUS_NAME_1); + if(ret != EOK) + { + KPrintf("Watchdog device register error %d\n", ret); + return ERROR; + } + } +#endif + + return ret; +} diff --git a/Ubiquitous/XiZi/board/maix-go/.defconfig b/Ubiquitous/XiZi/board/maix-go/.defconfig new file mode 100644 index 0000000..a4c6198 --- /dev/null +++ b/Ubiquitous/XiZi/board/maix-go/.defconfig @@ -0,0 +1,234 @@ +# +# Automatically generated file; DO NOT EDIT. +# XiZi Project Configuration +# +CONFIG_BOARD_MAIX_GO_EVB=y +CONFIG_KERNEL_CONSOLE_DEVICE_NAME="uarths" +CONFIG_LED0=24 +CONFIG_LED1=25 +CONFIG_ARCH_CPU_64BIT=y +CONFIG_ARCH_RISCV=y +CONFIG_ARCH_RISCV64=y + +# +# spieed maix go feature +# +# CONFIG_BSP_USING_AUDIO is not set +# CONFIG_BSP_USING_CAMERA is not set +# CONFIG_BSP_USING_SDIO is not set +CONFIG_BSP_USING_DMA=y +CONFIG_BSP_USING_GPIO=y +# CONFIG_BSP_USING_I2C is not set +# CONFIG_BSP_USING_I2S is not set +# CONFIG_BSP_USING_LCD is not set +# CONFIG_BSP_USING_RTC is not set +# CONFIG_BSP_USING_SECURITY is not set +# CONFIG_BSP_USING_SPI is not set +CONFIG_BSP_USING_UART=y +CONFIG_BSP_USING_UART_HS=y +# CONFIG_BSP_USING_VIDEO is not set +# CONFIG_BSP_USING_WDT is not set + +# +# General Purpose UARTs +# +CONFIG_BSP_USING_UART1=y +CONFIG_BSP_UART1_TXD_PIN=20 +CONFIG_BSP_UART1_RXD_PIN=21 +CONFIG_BSP_USING_UART2=y +CONFIG_BSP_UART2_TXD_PIN=28 +CONFIG_BSP_UART2_RXD_PIN=27 +CONFIG_BSP_USING_UART3=y +CONFIG_BSP_UART3_TXD_PIN=22 +CONFIG_BSP_UART3_RXD_PIN=23 +CONFIG___STACKSIZE__=4096 + +# +# Hardware feature +# +CONFIG_RESOURCES_SERIAL=y +# CONFIG_SERIAL_USING_DMA is not set +# CONFIG_SERIAL_RB_BUFSZ is not set +# CONFIG_RESOURCES_HWTIMER is not set +# CONFIG_RESOURCES_I2C is not set +# CONFIG_RESOURCES_LCD is not set +# CONFIG_RESOURCES_SDIO is not set +# CONFIG_RESOURCES_TOUCH is not set +CONFIG_RESOURCES_PIN=y +# CONFIG_RESOURCES_RTC is not set +# CONFIG_RESOURCES_SPI is not set +# CONFIG_RESOURCES_SPI_SD is not set +# CONFIG_RESOURCES_SPI_SFUD is not set +# SFUD_USING_SFDP is not set +# SFUD_USING_FLASH_INFO_TABLE is not set +# SFUD_DEBUG_LOG is not set +# CONFIG_RESOURCES_WDT is not set +# CONFIG_RESOURCES_USB is not set +# CONFIG_RESOURCES_USB_HOST is not set +# CONFIG_UDISK_MOUNTPOINT is not set +# CONFIG_USBH_MSTORAGE is not set +# CONFIG_RESOURCES_USB_DEVICE is not set +# CONFIG_USBD_THREAD_STACK_SZ is not set + +# +# Kernel feature +# +# CONFIG_SEPARATE_COMPILE is not set +# CONFIG_COMPILER_APP is not set +# CONFIG_COMPILER_KERNEL is not set +# +# Kernel Device Object +# +CONFIG_KERNEL_DEVICE=y +CONFIG_KERNEL_CONSOLE=y +CONFIG_KERNEL_CONSOLEBUF_SIZE=128 + +# +# Task feature +# +CONFIG_SCHED_POLICY_RR_REMAINSLICE=y +# CONFIG_SCHED_POLICY_RR is not set +# CONFIG_SCHED_POLICY_FIFO is not set + +# +# Inter-Task communication +# +CONFIG_KERNEL_SEMAPHORE=y +CONFIG_KERNEL_MUTEX=y +CONFIG_KERNEL_EVENT=y +CONFIG_KERNEL_MESSAGEQUEUE=y +# CONFIG_KTASK_PRIORITY_8 is not set +CONFIG_KTASK_PRIORITY_32=y +# CONFIG_KTASK_PRIORITY_256 is not set +CONFIG_KTASK_PRIORITY_MAX=32 +CONFIG_TICK_PER_SECOND=100 +CONFIG_KERNEL_STACK_OVERFLOW_CHECK=y +CONFIG_KERNEL_BANNER=y +# CONFIG_KERNEL_HOOK is not set +CONFIG_KERNEL_SOFTTIMER=y +CONFIG_KERNEL_IDLE_HOOK=y +CONFIG_IDEL_HOOK_LIST_SIZE=4 +CONFIG_IDLE_KTASK_STACKSIZE=1024 +CONFIG_USER_APPLICATION=y +# CONFIG_TASK_ISOLATION is not set + +# +# Memory Management +# +# CONFIG_KERNEL_MEMBLOCK is not set + +# +# Command shell +# +CONFIG_TOOL_SHELL=y +CONFIG_SHELL_TASK_PRIORITY=20 +CONFIG_SHELL_TASK_STACK_SIZE=4096 + +# +# User Control +# +CONFIG_SHELL_DEFAULT_USER="letter" +CONFIG_SHELL_DEFAULT_USER_PASSWORD="" +CONFIG_SHELL_LOCK_TIMEOUT=10000 +CONFIG_SHELL_ENTER_CR_AND_LF=y +# CONFIG_SHELL_ENTER_CRLF is not set +CONFIG_SHELL_ENTER_CR=y +CONFIG_SHELL_ENTER_LF=y +CONFIG_SHELL_MAX_NUMBER=5 +CONFIG_SHELL_PARAMETER_MAX_NUMBER=8 +CONFIG_SHELL_HISTORY_MAX_NUMBER=5 +CONFIG_SHELL_PRINT_BUFFER=128 +CONFIG_SHELL_USING_CMD_EXPORT=y +# CONFIG_SHELL_HELP_LIST_USER is not set +CONFIG_SHELL_HELP_SHOW_PERMISSION=y +# CONFIG_SHELL_HELP_LIST_VAR is not set +# CONFIG_SHELL_HELP_LIST_KEY is not set +CONFIG_KERNEL_QUEUEMANAGE=y +CONFIG_KERNEL_WORKQUEUE=y +CONFIG_WORKQUEUE_KTASK_STACKSIZE=512 +CONFIG_WORKQUEUE_KTASK_PRIORITY=23 +CONFIG_KERNEL_WAITQUEUE=y +CONFIG_KERNEL_DATAQUEUE=y +# CONFIG_KERNEL_CIRCULAR_AREA is not set +# CONFIG_KERNEL_AVL_TREE is not set +CONFIG_NAME_MAX=32 +CONFIG_ALIGN_SIZE=8 +CONFIG_KERNEL_COMPONENTS_INIT=y +CONFIG_KERNEL_USER_MAIN=y +CONFIG_MAIN_KTASK_STACK_SIZE=2048 +CONFIG_ENV_INIT_KTASK_STACK_SIZE=8192 +CONFIG_MAIN_KTASK_PRIORITY=10 +# CONFIG_USER_TEST is not set +# CONFIG_TOOL_TEST_SEM is not set +# CONFIG_TOOL_TEST_MUTEX is not set +# CONFIG_TOOL_TEST_EVENT is not set +# CONFIG_TOOL_TEST_MSG is not set +# CONFIG_TOOL_TEST_AVLTREE is not set +# CONFIG_TEST_CRICULAR_AREA is not set +# CONFIG_TOOL_TEST_MEM is not set +# CONFIG_TOOL_TEST_TIMER is not set +# CONFIG_TOOL_TEST_IWG is not set +# CONFIG_TOOL_TEST_REALTIME is not set +# CONFIG_TOOL_TEST_DBG is not set +# CONFIG_TOOL_TEST_SCHED is not set +# CONFIG_KERNEL_DEBUG is not set +CONFIG_DEBUG_COLOR=y +CONFIG_DEBUG_INIT_CONFIG=y +CONFIG_DBG_INIT=1 +CONFIG_ARCH_SMP=y +CONFIG_CPUS_NR=2 + +# +# File system +# +CONFIG_FS_VFS=y +CONFIG_VFS_USING_WORKDIR=y +CONFIG_FS_VFS_DEVFS=y + +# +# Fat filesystem +# + +# +# IOT-Device File system +# + +# +# Lwext4 filesystem +# + +# +# APP Framework +# + +# +# connection +# +# CONFIG_CONNECTION_AT is not set +# CONFIG_CONNECTION_MQTT is not set + +# +# medium communication +# + + +# +# Intelligence +# + +# +# Control +# + +# +# Lib +# +CONFIG_LIB=y +CONFIG_LIB_POSIX=y +CONFIG_LIB_NEWLIB=y + +CONFIG_LITTLEVGL2RTT_USING_DEMO=y + +# +# Security +# diff --git a/Ubiquitous/XiZi/board/maix-go/Kconfig b/Ubiquitous/XiZi/board/maix-go/Kconfig new file mode 100644 index 0000000..cefd589 --- /dev/null +++ b/Ubiquitous/XiZi/board/maix-go/Kconfig @@ -0,0 +1,57 @@ +mainmenu "XiZi Project Configuration" + +config BSP_DIR + string + option env="BSP_ROOT" + default "." + +config KERNEL_DIR + string + option env="KERNEL_ROOT" + default "../.." + +config BOARD_MAIX_GO_EVB + bool + select ARCH_RISCV + select ARCH_RISCV64 + select ARCH_CPU_64BIT + default y + +source "$KERNEL_DIR/arch/Kconfig" + + +menu "spieed maix go feature" + source "$BSP_DIR/third_party_driver/Kconfig" + + menu "config default board resources" + menu "config board app name" + config BOARD_APP_NAME + string "config board app name" + default "/XiUOS_maix-go_app.bin" + endmenu + + menu "config board service table" + config SERVICE_TABLE_ADDRESS + hex "board service table address" + default 0x80100000 + endmenu + + endmenu + + config __STACKSIZE__ + int "stack size for interrupt" + default 4096 + +endmenu + + + + + +menu "Hardware feature" + source "$KERNEL_DIR/resources/Kconfig" +endmenu + +source "$KERNEL_DIR/Kconfig" + + diff --git a/Ubiquitous/XiZi/board/maix-go/Makefile b/Ubiquitous/XiZi/board/maix-go/Makefile new file mode 100644 index 0000000..12f4148 --- /dev/null +++ b/Ubiquitous/XiZi/board/maix-go/Makefile @@ -0,0 +1,6 @@ +SRC_FILES := board.c + +SRC_DIR := third_party_driver + + +include $(KERNEL_ROOT)/compiler.mk diff --git a/Ubiquitous/XiZi/board/maix-go/README.md b/Ubiquitous/XiZi/board/maix-go/README.md new file mode 100644 index 0000000..7279b48 --- /dev/null +++ b/Ubiquitous/XiZi/board/maix-go/README.md @@ -0,0 +1,73 @@ +# maix-go README + +## 1. 简介 + +| 硬件 | 描述 | +| -- | -- | +|芯片型号| K210 | +|CPU| 双核RV64GC | +|主频| 400MHz | +|片内SRAM| 8MB | +| 外设 | 内嵌AES与SHA256算法加速器 | +| | DVP、JTAG、OTP、FPIOA、GPIO、UART、SPI、RTC、I²S、I²C、WDT、Timer与PWM | + +XiUOS板级当前支持使用GPIO、UART等。 + +## 2. 编译说明 + +编译环境：Ubuntu18.04 + +编译工具链：[riscv-none-embed-gcc](https://github.com/ilg-archived/riscv-none-gcc/releases) + +编译步骤： + +>1.将编译工具链的路径添加到board/maix-go/config.mk文件当中，例如将gnu-mcu-eclipse-riscv-none-gcc-8.2.0-2.1-20190425-1021-centos64.tgz解压到/opt/下时添加： +``` +export CROSS_COMPILE ?=/opt/gnu-mcu-eclipse/riscv-none-gcc/8.2.0-2.1-20190425-1021/bin/riscv-none-embed- +``` +>2.在代码根目录下执行以下命令，生成配置文件 +``` +cd ./Ubiquitous/XiZi +make BOARD=maix-go distclean +make BOARD=maix-go menuconfig +``` +>3.在menuconfig界面配置需要关闭和开启的功能，按回车键进入下级菜单，按Y键选中需要开启的功能，按N键选中需要关闭的功能，配置结束后选择Exit保存并退出 +>4.继续执行以下命令，进行编译 +``` +make BOARD=maix-go +``` +>5.如果编译正确无误，会产生XiZi_maix-go.elf、XiZi_maix-go.bin文件。其中XiZi_maix-go.bin需要烧写到设备中进行运行。 +>注：最后可以执行以下命令，清除配置文件和编译生成的文件 +``` +make BOARD=maix-go distclean +``` + +## 3. 烧写及执行 + +连接开发板串口（即Type-C口）到USB接口，拨动开发板电源开关，然后使用K-Flash工具进行烧写bin文件。 + +![Maix-go](img/maix_go.jpg) + +执行以下命令安装K-Flash工具 +``` +sudo apt install python3 python3-pip +sudo pip3 install pyserial +sudo pip3 install pyelftools +sudo pip3 install kflash +``` +如果最后一步安装kflash出现错误，可以尝试以下命令 +``` +sudo python -m pip install kflash +sudo python3 -m pip install kflash +sudo pip install kflash +sudo pip2 install kflash +``` +代码根目录下执行K-Flash工具烧录，此时ls /dev/ttyUSB*会发现新增2个USB端口，烧录时选择后一个，例如此时新增的是/dev/ttyUSB0和/dev/ttyUSB1，选择/dev/ttyUSB1 +``` +kflash -t build/XiZi_kd233.bin -p /dev/ttyUSB1 +``` +### 3.1 运行结果 + +如果编译 & 烧写无误，将会在串口终端上看到信息打印输出。 + +![terminal](img/terminal.png) \ No newline at end of file diff --git a/Ubiquitous/XiZi/board/maix-go/config.mk b/Ubiquitous/XiZi/board/maix-go/config.mk new file mode 100644 index 0000000..04cea69 --- /dev/null +++ b/Ubiquitous/XiZi/board/maix-go/config.mk @@ -0,0 +1,19 @@ +export CFLAGS := -mcmodel=medany -march=rv64imafdc -mabi=lp64d -fno-common -ffunction-sections -fdata-sections -fstrict-volatile-bitfields -O0 -ggdb -fgnu89-inline -Werror +export AFLAGS := -c -mcmodel=medany -march=rv64imafdc -mabi=lp64d -x assembler-with-cpp -ggdb +export LFLAGS := -mcmodel=medany -march=rv64imafdc -mabi=lp64d -nostartfiles -Wl,--gc-sections,-Map=XiZi.map,-cref,-u,_start -T $(BSP_ROOT)/link.lds + +export APPLFLAGS := -mcmodel=medany -march=rv64imafdc -mabi=lp64d -nostartfiles -Wl,--gc-sections,-Map=XiZi_app.map,-cref,-u, -T $(BSP_ROOT)/link_userspace.lds + +export CXXFLAGS := -mcmodel=medany -march=rv64imafdc -mabi=lp64d -fno-common -ffunction-sections -fdata-sections -fstrict-volatile-bitfields -O0 -ggdb -Werror + +export CROSS_COMPILE ?=/opt/gnu-mcu-eclipse/riscv-none-gcc/8.2.0-2.1-20190425-1021/bin/riscv-none-embed- + +export DEFINES := -DHAVE_CCONFIG_H -DHAVE_SIGINFO + + +export ARCH = risc-v +export MCU = k210 + +# export HAVE_SIGINFO=1 + +# export USING_LORA = 1 diff --git a/Ubiquitous/XiZi/board/maix-go/doc/20200117183100in2v5v.pdf b/Ubiquitous/XiZi/board/maix-go/doc/20200117183100in2v5v.pdf new file mode 100644 index 0000000..8cfbac0 Binary files /dev/null and b/Ubiquitous/XiZi/board/maix-go/doc/20200117183100in2v5v.pdf differ diff --git a/Ubiquitous/XiZi/board/maix-go/doc/Maix_GO_2.20(Assembly drawing).pdf b/Ubiquitous/XiZi/board/maix-go/doc/Maix_GO_2.20(Assembly drawing).pdf new file mode 100644 index 0000000..6a9de16 Binary files /dev/null and b/Ubiquitous/XiZi/board/maix-go/doc/Maix_GO_2.20(Assembly drawing).pdf differ diff --git a/Ubiquitous/XiZi/board/maix-go/doc/Maix_GO_2.20(Schematic).pdf b/Ubiquitous/XiZi/board/maix-go/doc/Maix_GO_2.20(Schematic).pdf new file mode 100644 index 0000000..2121a5d Binary files /dev/null and b/Ubiquitous/XiZi/board/maix-go/doc/Maix_GO_2.20(Schematic).pdf differ diff --git a/Ubiquitous/XiZi/board/maix-go/img/maix_go.jpg b/Ubiquitous/XiZi/board/maix-go/img/maix_go.jpg new file mode 100644 index 0000000..d563559 Binary files /dev/null and b/Ubiquitous/XiZi/board/maix-go/img/maix_go.jpg differ diff --git a/Ubiquitous/XiZi/board/maix-go/img/terminal.png b/Ubiquitous/XiZi/board/maix-go/img/terminal.png new file mode 100644 index 0000000..d8af292 Binary files /dev/null and b/Ubiquitous/XiZi/board/maix-go/img/terminal.png differ diff --git a/Ubiquitous/XiZi/board/maix-go/link.lds b/Ubiquitous/XiZi/board/maix-go/link.lds new file mode 100644 index 0000000..60d1927 --- /dev/null +++ b/Ubiquitous/XiZi/board/maix-go/link.lds @@ -0,0 +1,118 @@ +/* +* Copyright (c) 2020 AIIT XUOS Lab +* XiUOS is licensed under Mulan PSL v2. +* You can use this software according to the terms and conditions of the Mulan PSL v2. +* You may obtain a copy of Mulan PSL v2 at: +* http://license.coscl.org.cn/MulanPSL2 +* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, +* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, +* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. +* See the Mulan PSL v2 for more details. +*/ + +__STACKSIZE__ = 4096; + +OUTPUT_ARCH( "riscv" ) + +MEMORY +{ + sram (wxa!ri): ORIGIN = 0x80000000, LENGTH = ( 6 * 1024 * 1024 ) +} + +ENTRY(_begin) +SECTIONS +{ + .start : + { + *(.start); + } > sram + + . = ALIGN(8); + + .text : + { + PROVIDE( _text = ABSOLUTE(.) ); + + *(.text .text.*) /* Normal code */ + *(.rodata .rodata*) /* read-only data (constants) */ + + /* section information for shell */ + . = ALIGN(8); + _shell_command_start = .; + KEEP (*(shellCommand)) + _shell_command_end = .; + . = ALIGN(8); + + PROVIDE(__ctors_start__ = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array)) + PROVIDE(__ctors_end__ = .); + + . = ALIGN(4); + + __isrtbl_idx_start = .; + KEEP(*(.isrtbl.idx)) + __isrtbl_start = .; + KEEP(*(.isrtbl)) + __isrtbl_end = .; + . = ALIGN(8); + + PROVIDE(g_service_table_start = ABSOLUTE(.)); + KEEP(*(.g_service_table)) + PROVIDE(g_service_table_end = ABSOLUTE(.)); + + PROVIDE( _etext = ABSOLUTE(.) ); + } > sram + + . = ALIGN(8); + + .data : + { + PROVIDE( _sdata = ABSOLUTE(.) ); + + /* Writable data segment */ + *(.data .data.*) + + . = ALIGN(8); + PROVIDE( __global_pointer$ = ABSOLUTE(.) + 0x800 ); + + /* Writable small data segment (.sdata segment) */ + *(.sdata .sdata.*) + + PROVIDE( _edata = ABSOLUTE(.) ); + } > sram + + .bss : + { + __bss_start = ABSOLUTE(.); + + /* Writable uninitialized small data segment (.sbss segment)*/ + *(.sbss .sbss.*) + *(.scommon) + + /* Uninitialized writeable data section (.bss segment)*/ + *(.bss .bss.*) + *(COMMON) + + . = ALIGN(8); + __bss_end = ABSOLUTE(.); + } > sram + + .stack : + { + . = ALIGN(64); + PROVIDE(__stack_start__ = ABSOLUTE(.)); + + /* cpu0 stack top site */ + . = . + __STACKSIZE__; + __stack_tp0 = . ; + + /* cpu1 stack top site */ + . = . + __STACKSIZE__; + __stack_tp1 = . ; + + PROVIDE( __stack_end__ = ABSOLUTE(.) ); + } > sram + _end = ABSOLUTE(.); + +} diff --git a/Ubiquitous/XiZi/board/maix-go/link_userspace.lds b/Ubiquitous/XiZi/board/maix-go/link_userspace.lds new file mode 100644 index 0000000..3aa0bac --- /dev/null +++ b/Ubiquitous/XiZi/board/maix-go/link_userspace.lds @@ -0,0 +1,72 @@ +/* +* Copyright (c) 2020 AIIT XUOS Lab +* XiUOS is licensed under Mulan PSL v2. +* You can use this software according to the terms and conditions of the Mulan PSL v2. +* You may obtain a copy of Mulan PSL v2 at: +* http://license.coscl.org.cn/MulanPSL2 +* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, +* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, +* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. +* See the Mulan PSL v2 for more details. +*/ + + +OUTPUT_ARCH("riscv") + +MEMORY +{ + usram (rw) : ORIGIN = 0x80101000, LENGTH = ( 5 * 1024 * 1024 - 4 * 1024 ) /* 5M -4k usram */ +} + +SECTIONS +{ + .userspace : + { + . = ALIGN(8); + KEEP(*(.userspace)) + } > usram + + .text : + { + _ustext = ABSOLUTE(.); + *(.text .text.*) + *(.rodata .rodata*) + *(.glue_7) + *(.glue_7t) + PROVIDE(_uetext = ABSOLUTE(.)); + } > usram + + .init_section : { + _sinit = ABSOLUTE(.); + KEEP(*(.init_array .init_array.*)) + _einit = ABSOLUTE(.); + } > usram + + __uexidx_start = ABSOLUTE(.); + + .ARM.exidx : + { + PROVIDE(__uexidx_start = ABSOLUTE(.)); + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + PROVIDE(__uexidx_end = ABSOLUTE(.)); + } > usram + + _ueronly = ABSOLUTE(.); + + .data : AT(_ueronly) + { + _usdata = ABSOLUTE(.); + *(.data .data.*) + . = ALIGN(8); + _uedata = ABSOLUTE(.); + } > usram + + .bss : { + . = ALIGN(8); + _usbss = ABSOLUTE(.); + *(.bss .bss.*) + *(.sbss .sbss.*) + . = ALIGN(8); + _uebss = ABSOLUTE(.); + } > usram +} \ No newline at end of file diff --git a/Ubiquitous/XiZi/board/maix-go/third_party_driver/Kconfig b/Ubiquitous/XiZi/board/maix-go/third_party_driver/Kconfig new file mode 100755 index 0000000..c8da392 --- /dev/null +++ b/Ubiquitous/XiZi/board/maix-go/third_party_driver/Kconfig @@ -0,0 +1,29 @@ + + +menuconfig BSP_USING_PLIC +bool "Using PLIC device" +default y +if BSP_USING_PLIC +source "$BSP_DIR/third_party_driver/plic/Kconfig" +endif + + + +menuconfig BSP_USING_SYSCLOCK +bool "Using SYSCLOCK device" +default y +if BSP_USING_SYSCLOCK +source "$BSP_DIR/third_party_driver/sys_clock/Kconfig" +endif + + + +menuconfig BSP_USING_UART +bool "Using UART device" +default y +select RESOURCES_SERIAL +if BSP_USING_UART +source "$BSP_DIR/third_party_driver/uart/Kconfig" +endif + + diff --git a/Ubiquitous/XiZi/board/maix-go/third_party_driver/Makefile b/Ubiquitous/XiZi/board/maix-go/third_party_driver/Makefile new file mode 100644 index 0000000..c75ecca --- /dev/null +++ b/Ubiquitous/XiZi/board/maix-go/third_party_driver/Makefile @@ -0,0 +1,65 @@ +SRC_FILES := sleep.c + +ifeq ($(CONFIG_BSP_USING_AUDIO),y) + SRC_DIR += audio +endif + +ifeq ($(CONFIG_BSP_USING_CAMERA),y) + SRC_DIR += camera +endif + +ifeq ($(CONFIG_BSP_USING_DMA),y) + SRC_DIR += dma +endif + +ifeq ($(CONFIG_BSP_USING_GPIO),y) + SRC_DIR += gpio +endif + +ifeq ($(CONFIG_BSP_USING_I2C),y) + SRC_DIR += i2c +endif + +ifeq ($(CONFIG_BSP_USING_I2S),y) + SRC_DIR += i2s +endif + +ifeq ($(CONFIG_BSP_USING_LCD),y) + SRC_DIR += lcd +endif + +ifeq ($(CONFIG_BSP_USING_PLIC),y) + SRC_DIR += plic +endif + +ifeq ($(CONFIG_BSP_USING_RTC),y) + SRC_DIR += rtc +endif + +ifeq ($(CONFIG_BSP_USING_SECURITY),y) + SRC_DIR += security +endif + +ifeq ($(CONFIG_BSP_USING_SPI),y) + SRC_DIR += spi +endif + +ifeq ($(CONFIG_BSP_USING_SYSCLOCK),y) + SRC_DIR += sys_clock +endif + + + +ifeq ($(CONFIG_BSP_USING_UART),y) + SRC_DIR += uart +endif + +ifeq ($(CONFIG_BSP_USING_VIDEO),y) + SRC_DIR += video +endif + +ifeq ($(CONFIG_BSP_USING_WDT),y) + SRC_DIR += watchdog +endif + +include $(KERNEL_ROOT)/compiler.mk diff --git a/Ubiquitous/XiZi/board/maix-go/third_party_driver/uart/Kconfig b/Ubiquitous/XiZi/board/maix-go/third_party_driver/uart/Kconfig new file mode 100644 index 0000000..08e75e0 --- /dev/null +++ b/Ubiquitous/XiZi/board/maix-go/third_party_driver/uart/Kconfig @@ -0,0 +1,77 @@ +menuconfig BSP_USING_UART_HS + bool "Enable High Speed UART" + default y + if BSP_USING_UART_HS + config SERIAL_BUS_NAME_0 + string "serial high speed bus 0 name" + default "uart0" + config SERIAL_DRV_NAME_0 + string "serial high speed bus 0 driver name" + default "uart0_drv" + config SERIAL_0_DEVICE_NAME_0 + string "serial high speed bus 0 device 0 name" + default "uart0_dev0" + endif + +menuconfig BSP_USING_UART1 + bool "Enable UART1" + default y + if BSP_USING_UART1 + config BSP_UART1_TXD_PIN + int "uart1 TXD pin number" + default 20 + config BSP_UART1_RXD_PIN + int "uart1 RXD pin number" + default 21 + config SERIAL_BUS_NAME_1 + string "serial bus 1 name" + default "uart1" + config SERIAL_DRV_NAME_1 + string "serial bus 1 driver name" + default "uart1_drv" + config SERIAL_1_DEVICE_NAME_0 + string "serial bus 1 device 0 name" + default "uart1_dev1" + endif + +menuconfig BSP_USING_UART2 + bool "Enable UART2" + default y + if BSP_USING_UART2 + config BSP_UART2_TXD_PIN + int "uart2 TXD pin number" + default 28 + config BSP_UART2_RXD_PIN + int "uart2 RXD pin number" + default 27 + config SERIAL_BUS_NAME_2 + string "serial bus 2 name" + default "uart2" + config SERIAL_DRV_NAME_2 + string "serial bus 2 driver name" + default "uart2_drv" + config SERIAL_2_DEVICE_NAME_0 + string "serial bus 2 device 0 name" + default "uart2_dev2" + endif + +menuconfig BSP_USING_UART3 + bool "Enable UART3" + default y + if BSP_USING_UART3 + config BSP_UART3_TXD_PIN + int "uart3 TXD pin number" + default 22 + config BSP_UART3_RXD_PIN + int "uart3 RXD pin number" + default 23 + config SERIAL_BUS_NAME_3 + string "serial bus 3 name" + default "uart3" + config SERIAL_DRV_NAME_3 + string "serial bus 3 driver name" + default "uart3_drv" + config SERIAL_3_DEVICE_NAME_0 + string "serial bus 3 device 0 name" + default "uart3_dev3" + endif diff --git a/Ubiquitous/XiZi/board/maix-go/third_party_driver/uart/Makefile b/Ubiquitous/XiZi/board/maix-go/third_party_driver/uart/Makefile new file mode 100644 index 0000000..b515f58 --- /dev/null +++ b/Ubiquitous/XiZi/board/maix-go/third_party_driver/uart/Makefile @@ -0,0 +1,3 @@ +SRC_FILES := connect_uart.c + +include $(KERNEL_ROOT)/compiler.mk diff --git a/Ubiquitous/XiZi/board/nuvoton-m2354/.defconfig b/Ubiquitous/XiZi/board/nuvoton-m2354/.defconfig new file mode 100644 index 0000000..060489d --- /dev/null +++ b/Ubiquitous/XiZi/board/nuvoton-m2354/.defconfig @@ -0,0 +1,218 @@ +# +# Automatically generated file; DO NOT EDIT. +# XiUOS Project Configuration +# +CONFIG_BOARD_NUVOTON_M2354=y +CONFIG_KERNEL_CONSOLE_DEVICE_NAME="uart1" +CONFIG_ARCH_ARM=y + +# +# nuvoton-m2354 feature +# +# CONFIG_BSP_USING_DMA is not set +# CONFIG_BSP_USING_GPIO is not set +# CONFIG_BSP_USING_I2C is not set +# CONFIG_BSP_USING_LCD is not set +# CONFIG_BSP_USING_EXTMEM is not set +# CONFIG_BSP_USING_SDIO is not set +# CONFIG_BSP_USING_RTC is not set +# CONFIG_BSP_USING_SPI is not set +# CONFIG_BSP_USING_HWTIMER is not set +# CONFIG_BSP_USING_WDT is not set +CONFIG_BSP_USING_UART=y +CONFIG_BSP_USING_UART1=y +# CONFIG_BSP_USING_UART2 is not set +# CONFIG_BSP_USING_UART3 is not set +# CONFIG_BSP_USING_UART4 is not set +# CONFIG_BSP_USING_UART5 is not set +# CONFIG_BSP_USING_USB is not set +# CONFIG_BSP_USING_STM32_USBH is not set + +# +# Hardware feature +# +CONFIG_RESOURCES_SERIAL=y +# CONFIG_SERIAL_USING_DMA is not set +# CONFIG_SERIAL_RB_BUFSZ is not set +# CONFIG_RESOURCES_CAN is not set +# CONFIG_RESOURCES_HWTIMER is not set +# CONFIG_RESOURCES_I2C is not set +# CONFIG_RESOURCES_LCD is not set +# CONFIG_RESOURCES_SDIO is not set +# CONFIG_RESOURCES_TOUCH is not set +CONFIG_RESOURCES_PIN=y +# CONFIG_RESOURCES_RTC is not set +# CONFIG_RESOURCES_SPI is not set +# CONFIG_RESOURCES_SPI_SD is not set +# CONFIG_RESOURCES_SPI_SFUD is not set +# SFUD_USING_SFDP is not set +# SFUD_USING_FLASH_INFO_TABLE is not set +# SFUD_DEBUG_LOG is not set +# CONFIG_RESOURCES_WDT is not set +# CONFIG_RESOURCES_USB is not set +# CONFIG_RESOURCES_USB_HOST is not set +# CONFIG_UDISK_MOUNTPOINT is not set +# CONFIG_USBH_MSTORAGE is not set +# CONFIG_RESOURCES_USB_DEVICE is not set +# CONFIG_USBD_THREAD_STACK_SZ is not set + +# +# Kernel feature +# +# CONFIG_SEPARATE_COMPILE is not set +# CONFIG_COMPILER_APP is not set +# CONFIG_COMPILER_KERNEL is not set +# +# Kernel Device Object +# +CONFIG_KERNEL_DEVICE=y +CONFIG_KERNEL_CONSOLE=y +CONFIG_KERNEL_CONSOLEBUF_SIZE=128 + +# +# Task feature +# +CONFIG_SCHED_POLICY_RR_REMAINSLICE=y +# CONFIG_SCHED_POLICY_RR is not set +# CONFIG_SCHED_POLICY_FIFO is not set + +# +# Inter-Task communication +# +CONFIG_KERNEL_SEMAPHORE=y +CONFIG_KERNEL_MUTEX=y +CONFIG_KERNEL_EVENT=y +CONFIG_KERNEL_MESSAGEQUEUE=y +# CONFIG_KTASK_PRIORITY_8 is not set +CONFIG_KTASK_PRIORITY_32=y +# CONFIG_KTASK_PRIORITY_256 is not set +CONFIG_KTASK_PRIORITY_MAX=32 +CONFIG_TICK_PER_SECOND=1000 +CONFIG_KERNEL_STACK_OVERFLOW_CHECK=y +CONFIG_KERNEL_BANNER=y +# CONFIG_KERNEL_HOOK is not set +CONFIG_KERNEL_SOFTTIMER=y +CONFIG_KERNEL_IDLE_HOOK=y +CONFIG_IDEL_HOOK_LIST_SIZE=4 +CONFIG_IDLE_KTASK_STACKSIZE=256 +CONFIG_USER_APPLICATION=y +# CONFIG_TASK_ISOLATION is not set + +# +# Memory Management +# +# CONFIG_KERNEL_MEMBLOCK is not set + +# +# Command shell +# +CONFIG_TOOL_SHELL=y +CONFIG_SHELL_ENTER_CR=y +CONFIG_SHELL_ENTER_LF=y +CONFIG_SHELL_ENTER_CR_AND_LF=y +# CONFIG_SHELL_ENTER_CRLF is not set + +# +# User Control +# +CONFIG_SHELL_DEFAULT_USER="letter" +CONFIG_SHELL_DEFAULT_USER_PASSWORD="" +CONFIG_SHELL_LOCK_TIMEOUT=10000 +CONFIG_SHELL_TASK_STACK_SIZE=4096 +CONFIG_SHELL_TASK_PRIORITY=20 +CONFIG_SHELL_MAX_NUMBER=5 +CONFIG_SHELL_PARAMETER_MAX_NUMBER=8 +CONFIG_SHELL_HISTORY_MAX_NUMBER=5 +CONFIG_SHELL_PRINT_BUFFER=128 +CONFIG_SHELL_USING_CMD_EXPORT=y +CONFIG_SHELL_HELP_SHOW_PERMISSION=y +# CONFIG_SHELL_HELP_LIST_USER is not set +# CONFIG_SHELL_HELP_LIST_VAR is not set +# CONFIG_SHELL_HELP_LIST_KEY is not set +CONFIG_KERNEL_QUEUEMANAGE=y +CONFIG_KERNEL_WORKQUEUE=y +# CONFIG_WORKQUEUE_KTASK_STACKSIZE is not set +# CONFIG_WORKQUEUE_KTASK_PRIORITY is not set +CONFIG_KERNEL_WAITQUEUE=y +CONFIG_KERNEL_DATAQUEUE=y +# CONFIG_KERNEL_CIRCULAR_AREA is not set +# CONFIG_KERNEL_AVL_TREE is not set +CONFIG_NAME_MAX=8 +CONFIG_ALIGN_SIZE=4 +CONFIG_KERNEL_COMPONENTS_INIT=y +CONFIG_KERNEL_USER_MAIN=y +CONFIG_MAIN_KTASK_STACK_SIZE=2048 +CONFIG_ENV_INIT_KTASK_STACK_SIZE=2048 +CONFIG_MAIN_KTASK_PRIORITY=10 +# CONFIG_USER_TEST is not set +# CONFIG_TOOL_TEST_SEM is not set +# CONFIG_TOOL_TEST_MUTEX is not set +# CONFIG_TOOL_TEST_EVENT is not set +# CONFIG_TOOL_TEST_MSG is not set +# CONFIG_TOOL_TEST_AVLTREE is not set +# CONFIG_TEST_CRICULAR_AREA is not set +# CONFIG_TOOL_TEST_MEM is not set +# CONFIG_TOOL_TEST_TIMER is not set +# CONFIG_TOOL_TEST_IWG is not set +# CONFIG_TOOL_TEST_REALTIME is not set +# CONFIG_TOOL_TEST_DBG is not set +# CONFIG_TOOL_TEST_SCHED is not set +# CONFIG_KERNEL_DEBUG is not set +CONFIG_DEBUG_INIT_CONFIG=y +CONFIG_DBG_INIT=1 +# CONFIG_ARCH_SMP is not set + +# +# File system +# +CONFIG_FS_VFS=y +CONFIG_VFS_USING_WORKDIR=y +CONFIG_FS_VFS_DEVFS=y + +# +# Fat filesystem +# + +# +# IOT-Device File system +# + +# +# Lwext4 filesystem +# + +# +# APP Framework +# + +# +# connection +# +# CONFIG_CONNECTION_AT is not set +# CONFIG_CONNECTION_MQTT is not set + +# +# medium communication +# + + +# +# Intelligence +# + +# +# Control +# + +# +# Lib +# +CONFIG_LIB=y +CONFIG_LIB_POSIX=y +CONFIG_LIB_NEWLIB=y + +# CONFIG_LITTLEVGL2RTT_USING_DEMO is not set + +# +# Security +# diff --git a/Ubiquitous/XiZi/board/nuvoton-m2354/Kconfig b/Ubiquitous/XiZi/board/nuvoton-m2354/Kconfig new file mode 100644 index 0000000..be4cb66 --- /dev/null +++ b/Ubiquitous/XiZi/board/nuvoton-m2354/Kconfig @@ -0,0 +1,44 @@ +mainmenu "XiUOS Project Configuration" + +config BSP_DIR + string + option env="BSP_ROOT" + default "." + +config KERNEL_DIR + string + option env="KERNEL_ROOT" + default "../.." + +config BOARD_NUVOTON_M2354 + bool + select ARCH_ARM + default y + +source "$KERNEL_DIR/arch/Kconfig" + +menu "nuvoton-m2354 feature" + source "$BSP_DIR/third_party_driver/Kconfig" + + menu "config default board resources" + menu "config board app name" + config BOARD_APP_NAME + string "config board app name" + default "/XiUOS_nuvoton_m2354_app.bin" + endmenu + + menu "config board service table" + config SERVICE_TABLE_ADDRESS + hex "board service table address" + default 0x20000000 + endmenu + + endmenu + +endmenu + +menu "Hardware feature" + source "$KERNEL_DIR/resources/Kconfig" +endmenu + +source "$KERNEL_DIR/Kconfig" diff --git a/Ubiquitous/XiZi/board/nuvoton-m2354/Makefile b/Ubiquitous/XiZi/board/nuvoton-m2354/Makefile new file mode 100644 index 0000000..618b0de --- /dev/null +++ b/Ubiquitous/XiZi/board/nuvoton-m2354/Makefile @@ -0,0 +1,5 @@ +SRC_FILES := board.c + +SRC_DIR := third_party_driver + +include $(KERNEL_ROOT)/compiler.mk diff --git a/Ubiquitous/XiZi/board/nuvoton-m2354/README.md b/Ubiquitous/XiZi/board/nuvoton-m2354/README.md new file mode 100644 index 0000000..f3bf38f --- /dev/null +++ b/Ubiquitous/XiZi/board/nuvoton-m2354/README.md @@ -0,0 +1,165 @@ +# 从零开始构建矽璓工业物联操作系统：使用ARM架构的nuvoton-m2354 + +# nuvoton-m2354 + +[XiUOS](http://xuos.io/) (X Industrial Ubiquitous Operating System) 矽璓XiUOS是一款面向智慧车间的工业物联网操作系统，主要由一个极简的微型实时操作系统内核和其上的工业物联框架构成，通过高效管理工业物联网设备、支撑工业物联应用，在生产车间内实现智能化的“感知环境、联网传输、知悉识别、控制调整”，促进以工业设备和工业控制系统为核心的人、机、物深度互联，帮助提升生产线的数字化和智能化水平。 + +## 1. 简介 + +| 硬件 | 描述 | +| -- | -- | +|芯片型号| M2354KJFA | +|架构| cortex-m23 | +|主频| 96MHz | +|片内SRAM| 256KB | +|Flash| 1MB Dual Bank Flash | +|外设支持| UART | + +XiUOS板级当前支持使用UART0。 + +## 2. 开发环境搭建 + +### 推荐使用： + +**操作系统：** ubuntu18.04 [https://ubuntu.com/download/desktop](https://ubuntu.com/download/desktop) + +更新`ubuntu 18.04`源的方法:（根据自身情况而定，可以不更改） + +第一步:打开sources.list文件 + +```c +sudo vim /etc/apt/sources.list +``` + +第二步:将以下内容复制到sources.list文件 + +```c +deb http://mirrors.aliyun.com/ubuntu/ bionic main restricted universe multiverse +deb http://mirrors.aliyun.com/ubuntu/ bionic-security main restricted universe multiverse +deb http://mirrors.aliyun.com/ubuntu/ bionic-updates main restricted universe multiverse +deb http://mirrors.aliyun.com/ubuntu/ bionic-proposed main restricted universe multiverse +deb http://mirrors.aliyun.com/ubuntu/ bionic-backports main restricted universe multiverse +deb-src http://mirrors.aliyun.com/ubuntu/ bionic main restricted universe multiverse +deb-src http://mirrors.aliyun.com/ubuntu/ bionic-security main restricted universe multiverse +deb-src http://mirrors.aliyun.com/ubuntu/ bionic-updates main restricted universe multiverse +deb-src http://mirrors.aliyun.com/ubuntu/ bionic-proposed main restricted universe multiverse +deb-src http://mirrors.aliyun.com/ubuntu/ bionic-backports main restricted universe multiverse +``` + +第三步:更新源和系统软件 + +```c +sudo apt-get update +sudo apt-get upgrade +``` + +**开发工具推荐使用 VSCode ，VScode下载地址为：** VSCode [https://code.visualstudio.com/](https://code.visualstudio.com/)，推荐下载地址为 [http://vscode.cdn.azure.cn/stable/3c4e3df9e89829dce27b7b5c24508306b151f30d/code_1.55.2-1618307277_amd64.deb](http://vscode.cdn.azure.cn/stable/3c4e3df9e89829dce27b7b5c24508306b151f30d/code_1.55.2-1618307277_amd64.deb) + +### 依赖包安装： + +``` +$ sudo apt install build-essential pkg-config git +$ sudo apt install gcc make libncurses5-dev openssl libssl-dev bison flex libelf-dev autoconf libtool gperf libc6-dev +``` + +**XiUOS操作系统源码下载：** XiUOS [https://www.gitlink.org.cn/xuos/xiuos](https://www.gitlink.org.cn/xuos/xiuos) + +新建一个空文件夹并进入文件夹中，并下载源码，具体命令如下： + +```c +mkdir test && cd test +git clone https://gitlink.org.cn/xuos/xiuos.git +``` + +1、打开XiUOS源码文件包可以看到以下目录： +| 名称 | 说明 | +| -- | -- | +| APP_Framework | 应用代码 | +| Ubiquitous | 板级支持包,支持NuttX、RT-Thread和XiZi内核 | + +2、打开XiZi内核源码文件包可以看到以下目录： +| 名称 | 说明 | +| -- | -- | +| arch | 架构代码 | +| board | 板级支持包 | +| fs | 文件系统 | +| kernel | 内核源码 | +| lib | 第三方库源码 | +| resources | 驱动文件 | +| tool | 系统工具 | + +使用VScode打开代码，具体操作步骤为：在源码文件夹下打开系统终端，输入`code .`即可打开VScode开发环境，如下图所示： + +
+ +
+ +### 裁减配置工具的下载 + +裁减配置工具： + +**工具地址：** kconfig-frontends [https://www.gitlink.org.cn/xuos/kconfig-frontends](https://www.gitlink.org.cn/xuos/kconfig-frontends)，下载与安装的具体命令如下： + +```c +mkdir kfrontends && cd kfrontends +git clone https://gitlink.org.cn/xuos/kconfig-frontends.git +``` + +下载源码后按以下步骤执行软件安装： + +```c +cd kconfig-frontends +./xs_build.sh +``` + +### 编译工具链： + +ARM： gcc-arm-none-eabi-6-2017-q1-update/bin/arm-none-eabi(`gcc 6.3.1 20170215 (release) [ARM/embedded-6-branch revision 245512]`)，安装到Ubuntu的/opt/arm-none-eabi-，需要在新唐官网下载和安装。 + +**官网地址：** M2354 [https://www.nuvoton.com.cn/products/microcontrollers/arm-cortex-m23-mcus/m2354-series/?group=Software&tab=2 +](https://www.nuvoton.com.cn/products/microcontrollers/arm-cortex-m23-mcus/m2354-series/?group=Software&tab=2 +) + +## 编译说明 + +### 编辑环境：`Ubuntu18.04` + +### 编译工具链：`arm-none-eabi-gcc` +使用`VScode`打开工程的方法有多种，本文介绍一种快捷键，在项目目录下将`code .`输入linux系统命令终端即可打开目标项目 + + +编译步骤： + +1.在VScode命令终端中执行以下命令，生成配置文件 + +```c +cd ./Ubiquitous/XiZi +make BOARD=nuvoton-m2354 distclean +make BOARD=nuvoton-m2354 menuconfig +``` + +2.在menuconfig界面配置需要关闭和开启的功能，按回车键进入下级菜单，按Y键选中需要开启的功能，按N键选中需要关闭的功能，配置结束后保存并退出（本例旨在演示简单的输出例程，所以没有需要配置的选项，双击快捷键ESC退出配置） + +![menuconfig](./img/menuconfig.png) + +退出时选择`yes`保存上面所配置的内容，如下图所示： + +![menuconfig1](./img/menuconfig1.png) + +3.继续执行以下命令，进行编译 + +``` +make BOARD=nuvoton-m2354 +``` + +4.如果编译正确无误，会产生XiZi_nuvoton-m2354.elf、XiZi_nuvoton-m2354.bin文件。 + +## 3. 烧写及运行 + +### 3.1 烧写 +1、nuvoton-m2354开发板使用片上Nu-Link2-Me v1.0烧写接口，拨码开关1 on 2 on 3 on 4 on，使用Micro USB与电脑连接(需提前安装Nu-Link_USB_Driver驱动)，便可支持虚拟串口功能，linux系统和windows系统均会提示接入新磁盘，将编译生成的bin文件拷贝至虚拟磁盘中，等待设备重启，提示再次接入新磁盘后即可完成烧写下载功能。 + +### 3.2 运行结果 + +1、按照3.1烧写步骤执行后，若程序正常，则串口终端上会显示启动信息打印输出。如下图所示： +![terminal](./img/terminal.png) diff --git a/Ubiquitous/XiZi/board/nuvoton-m2354/board.h b/Ubiquitous/XiZi/board/nuvoton-m2354/board.h new file mode 100644 index 0000000..52005a2 --- /dev/null +++ b/Ubiquitous/XiZi/board/nuvoton-m2354/board.h @@ -0,0 +1,33 @@ +/* +* Copyright (c) 2020 AIIT XUOS Lab +* XiUOS is licensed under Mulan PSL v2. +* You can use this software according to the terms and conditions of the Mulan PSL v2. +* You may obtain a copy of Mulan PSL v2 at: +* http://license.coscl.org.cn/MulanPSL2 +* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, +* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, +* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. +* See the Mulan PSL v2 for more details. +*/ + +/** +* @file board.h +* @brief define nuvoton-m2354 board init configure and start-up function +* @version 1.1 +* @author AIIT XUOS Lab +* @date 2022-02-24 +*/ + +#ifndef __BOARD_H__ +#define __BOARD_H__ + +#define SRAM_SIZE (256) +#define SRAM_END (0x20000000 + SRAM_SIZE * 1024) + +extern int __bss_end; +#define HEAP_BEGIN ((void *)&__bss_end) +#define HEAP_END (void *)SRAM_END + +void InitBoardHardware(void); + +#endif diff --git a/Ubiquitous/XiZi/board/nuvoton-m2354/config.mk b/Ubiquitous/XiZi/board/nuvoton-m2354/config.mk new file mode 100644 index 0000000..c64fd21 --- /dev/null +++ b/Ubiquitous/XiZi/board/nuvoton-m2354/config.mk @@ -0,0 +1,11 @@ +export CROSS_COMPILE ?= /opt/gcc-arm-none-eabi-6-2017-q1-update/bin/arm-none-eabi- + +export CFLAGS := -mcpu=cortex-m23 -mthumb -ffunction-sections -fdata-sections -Dgcc -O0 -gdwarf-2 -g -fgnu89-inline -Wa,-mimplicit-it=thumb +export AFLAGS := -c -mcpu=cortex-m23 -mthumb -ffunction-sections -fdata-sections -x assembler-with-cpp -Wa,-mimplicit-it=thumb -gdwarf-2 +export LFLAGS := -mcpu=cortex-m23 -mthumb -ffunction-sections -fdata-sections -Wl,--gc-sections,-Map=XiZi_nuvoton_m2354.map,-cref,-u,Reset_Handler -T $(BSP_ROOT)/link.lds +export CXXFLAGS := -mcpu=cortex-m23 -mthumb -ffunction-sections -fdata-sections -Dgcc -O0 -gdwarf-2 -g + +export DEFINES := -DHAVE_CCONFIG_H + +export ARCH = arm +export MCU = cortex-m23 diff --git a/Ubiquitous/XiZi/board/nuvoton-m2354/img/board.png b/Ubiquitous/XiZi/board/nuvoton-m2354/img/board.png new file mode 100644 index 0000000..1a8afc9 Binary files /dev/null and b/Ubiquitous/XiZi/board/nuvoton-m2354/img/board.png differ diff --git a/Ubiquitous/XiZi/board/nuvoton-m2354/img/menuconfig.png b/Ubiquitous/XiZi/board/nuvoton-m2354/img/menuconfig.png new file mode 100644 index 0000000..f46c9b7 Binary files /dev/null and b/Ubiquitous/XiZi/board/nuvoton-m2354/img/menuconfig.png differ diff --git a/Ubiquitous/XiZi/board/nuvoton-m2354/img/menuconfig1.png b/Ubiquitous/XiZi/board/nuvoton-m2354/img/menuconfig1.png new file mode 100644 index 0000000..691d38e Binary files /dev/null and b/Ubiquitous/XiZi/board/nuvoton-m2354/img/menuconfig1.png differ diff --git a/Ubiquitous/XiZi/board/nuvoton-m2354/img/terminal.png b/Ubiquitous/XiZi/board/nuvoton-m2354/img/terminal.png new file mode 100644 index 0000000..00bfaa5 Binary files /dev/null and b/Ubiquitous/XiZi/board/nuvoton-m2354/img/terminal.png differ diff --git a/Ubiquitous/XiZi/board/nuvoton-m2354/link.lds b/Ubiquitous/XiZi/board/nuvoton-m2354/link.lds new file mode 100644 index 0000000..ba72ba6 --- /dev/null +++ b/Ubiquitous/XiZi/board/nuvoton-m2354/link.lds @@ -0,0 +1,105 @@ +/* + * @copyright (C) 2020 Nuvoton Technology Corp. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + */ + +/* Linker script to configure memory regions. */ +MEMORY +{ + flash (rx) : ORIGIN = 0x00000000, LENGTH = 1024K /* 1024K flash */ + sram (rw) : ORIGIN = 0x20000000, LENGTH = 256K /* 256K sram */ +} +ENTRY(Reset_Handler) +_system_stack_size = 0x2000; + +SECTIONS +{ + .text : + { + . = ALIGN(4); + KEEP(*(.isr_vector)) /* Startup code */ + . = ALIGN(4); + *(.text) /* remaining code */ + *(.text.*) /* remaining code */ + *(.rodata) /* read-only data (constants) */ + *(.rodata*) + + /* section information for shell */ + . = ALIGN(4); + _shell_command_start = .; + KEEP (*(shellCommand)) + _shell_command_end = .; + . = ALIGN(4); + + __isrtbl_idx_start = .; + KEEP(*(.isrtbl.idx)) + __isrtbl_start = .; + KEEP(*(.isrtbl)) + __isrtbl_end = .; + . = ALIGN(4); + + PROVIDE(g_service_table_start = ABSOLUTE(.)); + KEEP(*(.g_service_table)) + PROVIDE(g_service_table_end = ABSOLUTE(.)); + + PROVIDE(_etext = ABSOLUTE(.)); + + . = ALIGN(4); + _etext = .; + } > flash = 0 + + /* .ARM.exidx is sorted, so has to go in its own output section. */ + __exidx_start = .; + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + + /* This is used by the startup in order to initialize the .data section */ + _sidata = .; + } > flash + __exidx_end = .; + + .stack : + { + . = . + _system_stack_size; + . = ALIGN(4); + _sp = .; + } > sram + + /* .data section which is used for initialized data */ + .data : AT (_sidata) + { + . = ALIGN(4); + /* This is used by the startup in order to initialize the .data section */ + _sdata = . ; + + *(.data) + *(.data.*) + + . = ALIGN(4); + /* This is used by the startup in order to initialize the .data section */ + _edata = . ; + } > sram + + __bss_start = .; + .bss : + { + . = ALIGN(4); + /* This is used by the startup in order to initialize the .bss section */ + _sbss = .; + + *(.bss) + *(.bss.*) + *(COMMON) + + . = ALIGN(4); + /* This is used by the startup in order to initialize the .bss section */ + _ebss = . ; + } > sram + __bss_end = .; + + _end = .; + +} diff --git a/Ubiquitous/XiZi/board/nuvoton-m2354/third_party_driver/Kconfig b/Ubiquitous/XiZi/board/nuvoton-m2354/third_party_driver/Kconfig new file mode 100644 index 0000000..6fdbc28 --- /dev/null +++ b/Ubiquitous/XiZi/board/nuvoton-m2354/third_party_driver/Kconfig @@ -0,0 +1,7 @@ +menuconfig BSP_USING_UART + bool "Using UART device" + default y + select RESOURCES_SERIAL + if BSP_USING_UART + source "$BSP_DIR/third_party_driver/uart/Kconfig" + endif diff --git a/Ubiquitous/XiZi/board/nuvoton-m2354/third_party_driver/Makefile b/Ubiquitous/XiZi/board/nuvoton-m2354/third_party_driver/Makefile new file mode 100644 index 0000000..a742f3e --- /dev/null +++ b/Ubiquitous/XiZi/board/nuvoton-m2354/third_party_driver/Makefile @@ -0,0 +1,7 @@ +SRC_DIR := common + +ifeq ($(CONFIG_BSP_USING_UART),y) + SRC_DIR += uart +endif + +include $(KERNEL_ROOT)/compiler.mk \ No newline at end of file diff --git a/Ubiquitous/XiZi/board/nuvoton-m2354/third_party_driver/include/Drivers/nu_acmp.h b/Ubiquitous/XiZi/board/nuvoton-m2354/third_party_driver/include/Drivers/nu_acmp.h new file mode 100644 index 0000000..234e981 --- /dev/null +++ b/Ubiquitous/XiZi/board/nuvoton-m2354/third_party_driver/include/Drivers/nu_acmp.h @@ -0,0 +1,382 @@ +/**************************************************************************//** + * @file nu_acmp.h + * @version V3.00 + * @brief ACMP Driver Header File + * + * @copyright SPDX-License-Identifier: Apache-2.0 + * @copyright Copyright (C) 2020 Nuvoton Technology Corp. All rights reserved. + ******************************************************************************/ +#ifndef __NU_ACMP_H__ +#define __NU_ACMP_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup ACMP_Driver ACMP Driver + @{ +*/ + + +/** @addtogroup ACMP_EXPORTED_CONSTANTS ACMP Exported Constants + @{ +*/ + + + +/*---------------------------------------------------------------------------------------------------------*/ +/* ACMP_CTL constant definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define ACMP_CTL_FILTSEL_OFF (0UL << 13) /*!< ACMP_CTL setting for filter function disabled. */ +#define ACMP_CTL_FILTSEL_1PCLK (1UL << 13) /*!< ACMP_CTL setting for 1 PCLK filter count. */ +#define ACMP_CTL_FILTSEL_2PCLK (2UL << 13) /*!< ACMP_CTL setting for 2 PCLK filter count. */ +#define ACMP_CTL_FILTSEL_4PCLK (3UL << 13) /*!< ACMP_CTL setting for 4 PCLK filter count. */ +#define ACMP_CTL_FILTSEL_8PCLK (4UL << 13) /*!< ACMP_CTL setting for 8 PCLK filter count. */ +#define ACMP_CTL_FILTSEL_16PCLK (5UL << 13) /*!< ACMP_CTL setting for 16 PCLK filter count. */ +#define ACMP_CTL_FILTSEL_32PCLK (6UL << 13) /*!< ACMP_CTL setting for 32 PCLK filter count. */ +#define ACMP_CTL_FILTSEL_64PCLK (7UL << 13) /*!< ACMP_CTL setting for 64 PCLK filter count. */ +#define ACMP_CTL_INTPOL_RF (0UL << 8) /*!< ACMP_CTL setting for selecting rising edge and falling edge as interrupt condition. */ +#define ACMP_CTL_INTPOL_R (1UL << 8) /*!< ACMP_CTL setting for selecting rising edge as interrupt condition. */ +#define ACMP_CTL_INTPOL_F (2UL << 8) /*!< ACMP_CTL setting for selecting falling edge as interrupt condition. */ +#define ACMP_CTL_POSSEL_P0 (0UL << 6) /*!< ACMP_CTL setting for selecting ACMPx_P0 pin as the source of ACMP V+. */ +#define ACMP_CTL_POSSEL_P1 (1UL << 6) /*!< ACMP_CTL setting for selecting ACMPx_P1 pin as the source of ACMP V+. */ +#define ACMP_CTL_POSSEL_P2 (2UL << 6) /*!< ACMP_CTL setting for selecting ACMPx_P2 pin as the source of ACMP V+. */ +#define ACMP_CTL_POSSEL_P3 (3UL << 6) /*!< ACMP_CTL setting for selecting ACMPx_P3 pin as the source of ACMP V+. */ +#define ACMP_CTL_NEGSEL_PIN (0UL << 4) /*!< ACMP_CTL setting for selecting the voltage of ACMP negative input pin as the source of ACMP V-. */ +#define ACMP_CTL_NEGSEL_CRV (1UL << 4) /*!< ACMP_CTL setting for selecting internal comparator reference voltage as the source of ACMP V-. */ +#define ACMP_CTL_NEGSEL_VBG (2UL << 4) /*!< ACMP_CTL setting for selecting internal Band-gap voltage as the source of ACMP V-. */ +#define ACMP_CTL_NEGSEL_DAC (3UL << 4) /*!< ACMP_CTL setting for selecting DAC output voltage as the source of ACMP V-. */ +#define ACMP_CTL_HYSTERESIS_30MV (3UL << 24) /*!< ACMP_CTL setting for enabling the hysteresis function at 30mV. */ +#define ACMP_CTL_HYSTERESIS_20MV (2UL << 24) /*!< ACMP_CTL setting for enabling the hysteresis function at 20mV. */ +#define ACMP_CTL_HYSTERESIS_10MV (1UL << 24) /*!< ACMP_CTL setting for enabling the hysteresis function at 10mV. */ +#define ACMP_CTL_HYSTERESIS_DISABLE (0UL << 2) /*!< ACMP_CTL setting for disabling the hysteresis function. */ + +/*---------------------------------------------------------------------------------------------------------*/ +/* ACMP_VREF constant definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define ACMP_VREF_CRVSSEL_VDDA (0UL << 6) /*!< ACMP_VREF setting for selecting analog supply voltage VDDA as the CRV source voltage */ +#define ACMP_VREF_CRVSSEL_INTVREF (1UL << 6) /*!< ACMP_VREF setting for selecting internal reference voltage as the CRV source voltage */ + + +/**@}*/ /* end of group ACMP_EXPORTED_CONSTANTS */ + + +/** @addtogroup ACMP_EXPORTED_FUNCTIONS ACMP Exported Functions + @{ +*/ + +/*---------------------------------------------------------------------------------------------------------*/ +/* Define Macros and functions */ +/*---------------------------------------------------------------------------------------------------------*/ + + +/** + * @brief This macro is used to enable output inverse function + * @param[in] acmp The pointer of the specified ACMP module + * @param[in] u32ChNum The ACMP number + * @return None + * @details This macro will set ACMPOINV bit of ACMP_CTL register to enable output inverse function. + */ +#define ACMP_ENABLE_OUTPUT_INVERSE(acmp, u32ChNum) ((acmp)->CTL[(u32ChNum)] |= ACMP_CTL_ACMPOINV_Msk) + +/** + * @brief This macro is used to disable output inverse function + * @param[in] acmp The pointer of the specified ACMP module + * @param[in] u32ChNum The ACMP number + * @return None + * @details This macro will clear ACMPOINV bit of ACMP_CTL register to disable output inverse function. + */ +#define ACMP_DISABLE_OUTPUT_INVERSE(acmp, u32ChNum) ((acmp)->CTL[(u32ChNum)] &= ~ACMP_CTL_ACMPOINV_Msk) + +/** + * @brief This macro is used to select ACMP negative input source + * @param[in] acmp The pointer of the specified ACMP module + * @param[in] u32ChNum The ACMP number + * @param[in] u32Src is comparator negative input selection. Including: + * - \ref ACMP_CTL_NEGSEL_PIN + * - \ref ACMP_CTL_NEGSEL_CRV + * - \ref ACMP_CTL_NEGSEL_VBG + * - \ref ACMP_CTL_NEGSEL_DAC + * @return None + * @details This macro will set NEGSEL (ACMP_CTL[5:4]) to determine the source of negative input. + */ +#define ACMP_SET_NEG_SRC(acmp, u32ChNum, u32Src) ((acmp)->CTL[(u32ChNum)] = ((acmp)->CTL[(u32ChNum)] & ~ACMP_CTL_NEGSEL_Msk) | (u32Src)) + +/** + * @brief This macro is used to enable hysteresis function + * @param[in] acmp The pointer of the specified ACMP module + * @param[in] u32ChNum The ACMP number + * @return None + */ +#define ACMP_ENABLE_HYSTERESIS(acmp, u32ChNum) ((acmp)->CTL[(u32ChNum)] |= ACMP_CTL_HYSTERESIS_30MV) + +/** + * @brief This macro is used to disable hysteresis function + * @param[in] acmp The pointer of the specified ACMP module + * @param[in] u32ChNum The ACMP number + * @return None + * @details This macro will set HYSSEL of ACMP_CTL register to disable hysteresis function. + */ +#define ACMP_DISABLE_HYSTERESIS(acmp, u32ChNum) ((acmp)->CTL[(u32ChNum)] &= ~ACMP_CTL_HYSSEL_Msk) + +/** + * @brief This macro is used to select hysteresis level + * @param[in] acmp The pointer of the specified ACMP module + * @param[in] u32ChNum The ACMP number + * @param[in] u32HysSel The hysteresis function option. Including: + * - \ref ACMP_CTL_HYSTERESIS_30MV + * - \ref ACMP_CTL_HYSTERESIS_20MV + * - \ref ACMP_CTL_HYSTERESIS_10MV + * - \ref ACMP_CTL_HYSTERESIS_DISABLE + * @return None + */ +#define ACMP_CONFIG_HYSTERESIS(acmp, u32ChNum, u32HysSel) ((acmp)->CTL[(u32ChNum)] = ((acmp)->CTL[(u32ChNum)] & ~ACMP_CTL_HYSSEL_Msk) | (u32HysSel)) + +/** + * @brief This macro is used to enable interrupt + * @param[in] acmp The pointer of the specified ACMP module + * @param[in] u32ChNum The ACMP number + * @return None + * @details This macro will set ACMPIE bit of ACMP_CTL register to enable interrupt function. + * If wake-up function is enabled, the wake-up interrupt will be enabled as well. + */ +#define ACMP_ENABLE_INT(acmp, u32ChNum) ((acmp)->CTL[(u32ChNum)] |= ACMP_CTL_ACMPIE_Msk) + +/** + * @brief This macro is used to disable interrupt + * @param[in] acmp The pointer of the specified ACMP module + * @param[in] u32ChNum The ACMP number + * @return None + * @details This macro will clear ACMPIE bit of ACMP_CTL register to disable interrupt function. + */ +#define ACMP_DISABLE_INT(acmp, u32ChNum) ((acmp)->CTL[(u32ChNum)] &= ~ACMP_CTL_ACMPIE_Msk) + +/** + * @brief This macro is used to enable ACMP + * @param[in] acmp The pointer of the specified ACMP module + * @param[in] u32ChNum The ACMP number + * @return None + * @details This macro will set ACMPEN bit of ACMP_CTL register to enable analog comparator. + */ +#define ACMP_ENABLE(acmp, u32ChNum) ((acmp)->CTL[(u32ChNum)] |= ACMP_CTL_ACMPEN_Msk) + +/** + * @brief This macro is used to disable ACMP + * @param[in] acmp The pointer of the specified ACMP module + * @param[in] u32ChNum The ACMP number + * @return None + * @details This macro will clear ACMPEN bit of ACMP_CTL register to disable analog comparator. + */ +#define ACMP_DISABLE(acmp, u32ChNum) ((acmp)->CTL[(u32ChNum)] &= ~ACMP_CTL_ACMPEN_Msk) + +/** + * @brief This macro is used to get ACMP output value + * @param[in] acmp The pointer of the specified ACMP module + * @param[in] u32ChNum The ACMP number + * @return ACMP output value + * @details This macro will return the ACMP output value. + */ +#define ACMP_GET_OUTPUT(acmp, u32ChNum) (((acmp)->STATUS & (ACMP_STATUS_ACMPO0_Msk<<((u32ChNum))))?1:0) + +/** + * @brief This macro is used to get ACMP interrupt flag + * @param[in] acmp The pointer of the specified ACMP module + * @param[in] u32ChNum The ACMP number + * @return ACMP interrupt occurred (1) or not (0) + * @details This macro will return the ACMP interrupt flag. + */ +#define ACMP_GET_INT_FLAG(acmp, u32ChNum) (((acmp)->STATUS & (ACMP_STATUS_ACMPIF0_Msk<<((u32ChNum))))?1:0) + +/** + * @brief This macro is used to clear ACMP interrupt flag + * @param[in] acmp The pointer of the specified ACMP module + * @param[in] u32ChNum The ACMP number + * @return None + * @details This macro will write 1 to ACMPIFn bit of ACMP_STATUS register to clear interrupt flag. + */ +#define ACMP_CLR_INT_FLAG(acmp, u32ChNum) ((acmp)->STATUS = (ACMP_STATUS_ACMPIF0_Msk<<((u32ChNum)))) + +/** + * @brief This macro is used to clear ACMP wake-up interrupt flag + * @param[in] acmp The pointer of the specified ACMP module + * @param[in] u32ChNum The ACMP number + * @return None + * @details This macro will write 1 to WKIFn bit of ACMP_STATUS register to clear interrupt flag. + */ +#define ACMP_CLR_WAKEUP_INT_FLAG(acmp, u32ChNum) ((acmp)->STATUS = (ACMP_STATUS_WKIF0_Msk<<((u32ChNum)))) + +/** + * @brief This macro is used to enable ACMP wake-up function + * @param[in] acmp The pointer of the specified ACMP module + * @param[in] u32ChNum The ACMP number + * @return None + * @details This macro will set WKEN (ACMP_CTL[16]) to enable ACMP wake-up function. + */ +#define ACMP_ENABLE_WAKEUP(acmp, u32ChNum) ((acmp)->CTL[(u32ChNum)] |= ACMP_CTL_WKEN_Msk) + +/** + * @brief This macro is used to disable ACMP wake-up function + * @param[in] acmp The pointer of the specified ACMP module + * @param[in] u32ChNum The ACMP number + * @return None + * @details This macro will clear WKEN (ACMP_CTL[16]) to disable ACMP wake-up function. + */ +#define ACMP_DISABLE_WAKEUP(acmp, u32ChNum) ((acmp)->CTL[(u32ChNum)] &= ~ACMP_CTL_WKEN_Msk) + +/** + * @brief This macro is used to select ACMP positive input pin + * @param[in] acmp The pointer of the specified ACMP module + * @param[in] u32ChNum The ACMP number + * @param[in] u32Pin Comparator positive pin selection. Including: + * - \ref ACMP_CTL_POSSEL_P0 + * - \ref ACMP_CTL_POSSEL_P1 + * - \ref ACMP_CTL_POSSEL_P2 + * - \ref ACMP_CTL_POSSEL_P3 + * @return None + * @details This macro will set POSSEL (ACMP_CTL[7:6]) to determine the comparator positive input pin. + */ +#define ACMP_SELECT_P(acmp, u32ChNum, u32Pin) ((acmp)->CTL[(u32ChNum)] = ((acmp)->CTL[(u32ChNum)] & ~ACMP_CTL_POSSEL_Msk) | (u32Pin)) + +/** + * @brief This macro is used to enable ACMP filter function + * @param[in] acmp The pointer of the specified ACMP module + * @param[in] u32ChNum The ACMP number + * @return None + * @details This macro will set OUTSEL (ACMP_CTL[12]) to enable output filter function. + */ +#define ACMP_ENABLE_FILTER(acmp, u32ChNum) ((acmp)->CTL[(u32ChNum)] |= ACMP_CTL_OUTSEL_Msk) + +/** + * @brief This macro is used to disable ACMP filter function + * @param[in] acmp The pointer of the specified ACMP module + * @param[in] u32ChNum The ACMP number + * @return None + * @details This macro will clear OUTSEL (ACMP_CTL[12]) to disable output filter function. + */ +#define ACMP_DISABLE_FILTER(acmp, u32ChNum) ((acmp)->CTL[(u32ChNum)] &= ~ACMP_CTL_OUTSEL_Msk) + +/** + * @brief This macro is used to set ACMP filter function + * @param[in] acmp The pointer of the specified ACMP module + * @param[in] u32ChNum The ACMP number + * @param[in] u32Cnt is comparator filter count setting. + * - \ref ACMP_CTL_FILTSEL_OFF + * - \ref ACMP_CTL_FILTSEL_1PCLK + * - \ref ACMP_CTL_FILTSEL_2PCLK + * - \ref ACMP_CTL_FILTSEL_4PCLK + * - \ref ACMP_CTL_FILTSEL_8PCLK + * - \ref ACMP_CTL_FILTSEL_16PCLK + * - \ref ACMP_CTL_FILTSEL_32PCLK + * - \ref ACMP_CTL_FILTSEL_64PCLK + * @return None + * @details When ACMP output filter function is enabled, the output sampling count is determined by FILTSEL (ACMP_CTL[15:13]). + */ +#define ACMP_SET_FILTER(acmp, u32ChNum, u32Cnt) ((acmp)->CTL[(u32ChNum)] = ((acmp)->CTL[(u32ChNum)] & ~ACMP_CTL_FILTSEL_Msk) | (u32Cnt)) + +/** + * @brief This macro is used to select comparator reference voltage + * @param[in] acmp The pointer of the specified ACMP module + * @param[in] u32Level The comparator reference voltage setting. + * The formula is: + * comparator reference voltage = CRV source voltage x (1/6 + u32Level/24) + * The range of u32Level is 0 ~ 15. + * @return None + * @details When CRV is selected as ACMP negative input source, the CRV level is determined by CRVCTL (ACMP_VREF[3:0]). + */ +#define ACMP_CRV_SEL(acmp, u32Level) ((acmp)->VREF = ((acmp)->VREF & ~ACMP_VREF_CRVCTL_Msk) | ((u32Level)<VREF = ((acmp)->VREF & ~ACMP_VREF_CRVSSEL_Msk) | (u32Src)) + +/** + * @brief This macro is used to select ACMP interrupt condition + * @param[in] acmp The pointer of the specified ACMP module + * @param[in] u32ChNum The ACMP number + * @param[in] u32Cond Comparator interrupt condition selection. Including: + * - \ref ACMP_CTL_INTPOL_RF + * - \ref ACMP_CTL_INTPOL_R + * - \ref ACMP_CTL_INTPOL_F + * @return None + * @details The ACMP output interrupt condition can be rising edge, falling edge or any edge. + */ +#define ACMP_SELECT_INT_COND(acmp, u32ChNum, u32Cond) ((acmp)->CTL[(u32ChNum)] = ((acmp)->CTL[(u32ChNum)] & ~ACMP_CTL_INTPOL_Msk) | (u32Cond)) + +/** + * @brief This macro is used to enable ACMP window latch mode + * @param[in] acmp The pointer of the specified ACMP module + * @param[in] u32ChNum The ACMP number + * @return None + * @details This macro will set WLATEN (ACMP_CTL[17]) to enable ACMP window latch mode. + * When ACMP0/1_WLAT pin is at high level, ACMPO0/1 passes through window latch + * block; when ACMP0/1_WLAT pin is at low level, the output of window latch block, + * WLATOUT, is frozen. + */ +#define ACMP_ENABLE_WINDOW_LATCH(acmp, u32ChNum) ((acmp)->CTL[(u32ChNum)] |= ACMP_CTL_WLATEN_Msk) + +/** + * @brief This macro is used to disable ACMP window latch mode + * @param[in] acmp The pointer of the specified ACMP module + * @param[in] u32ChNum The ACMP number + * @return None + * @details This macro will clear WLATEN (ACMP_CTL[17]) to disable ACMP window latch mode. + */ +#define ACMP_DISABLE_WINDOW_LATCH(acmp, u32ChNum) ((acmp)->CTL[(u32ChNum)] &= ~ACMP_CTL_WLATEN_Msk) + +/** + * @brief This macro is used to enable ACMP window compare mode + * @param[in] acmp The pointer of the specified ACMP module + * @param[in] u32ChNum The ACMP number + * @return None + * @details This macro will set WCMPSEL (ACMP_CTL[18]) to enable ACMP window compare mode. + * When window compare mode is enabled, user can connect the specific analog voltage + * source to either the positive inputs of both comparators or the negative inputs of + * both comparators. The upper bound and lower bound of the designated range are + * determined by the voltages applied to the other inputs of both comparators. If the + * output of a comparator is low and the other comparator outputs high, which means two + * comparators implies the upper and lower bound. User can directly monitor a specific + * analog voltage source via ACMPWO (ACMP_STATUS[16]). + */ +#define ACMP_ENABLE_WINDOW_COMPARE(acmp, u32ChNum) ((acmp)->CTL[(u32ChNum)] |= ACMP_CTL_WCMPSEL_Msk) + +/** + * @brief This macro is used to disable ACMP window compare mode + * @param[in] acmp The pointer of the specified ACMP module + * @param[in] u32ChNum The ACMP number + * @return None + * @details This macro will clear WCMPSEL (ACMP_CTL[18]) to disable ACMP window compare mode. + */ +#define ACMP_DISABLE_WINDOW_COMPARE(acmp, u32ChNum) ((acmp)->CTL[(u32ChNum)] &= ~ACMP_CTL_WCMPSEL_Msk) + + + + +/* Function prototype declaration */ +void ACMP_Open(ACMP_T *acmp, uint32_t u32ChNum, uint32_t u32NegSrc, uint32_t u32HysSel); +void ACMP_Close(ACMP_T *acmp, uint32_t u32ChNum); + + +/**@}*/ /* end of group ACMP_EXPORTED_FUNCTIONS */ +/**@}*/ /* end of group ACMP_Driver */ +/**@}*/ /* end of group Standard_Driver */ + +#ifdef __cplusplus +} +#endif + +#endif /* __NU_ACMP_H__ */ + + diff --git a/Ubiquitous/XiZi/board/nuvoton-m2354/third_party_driver/include/Drivers/nu_bpwm.h b/Ubiquitous/XiZi/board/nuvoton-m2354/third_party_driver/include/Drivers/nu_bpwm.h new file mode 100644 index 0000000..7708a43 --- /dev/null +++ b/Ubiquitous/XiZi/board/nuvoton-m2354/third_party_driver/include/Drivers/nu_bpwm.h @@ -0,0 +1,360 @@ +/**************************************************************************//** + * @file nu_bpwm.h + * @version V1.00 + * @brief M2354 series BPWM driver header file + * + * @copyright SPDX-License-Identifier: Apache-2.0 + * @copyright Copyright (C) 2020 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ +#ifndef __NU_BPWM_H__ +#define __NU_BPWM_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup BPWM_Driver BPWM Driver + @{ +*/ + +/** @addtogroup BPWM_EXPORTED_CONSTANTS BPWM Exported Constants + @{ +*/ +#define BPWM_CHANNEL_NUM (6UL) /*!< BPWM channel number */ +#define BPWM_CH_0_MASK (0x1UL) /*!< BPWM channel 0 mask \hideinitializer */ +#define BPWM_CH_1_MASK (0x2UL) /*!< BPWM channel 1 mask \hideinitializer */ +#define BPWM_CH_2_MASK (0x4UL) /*!< BPWM channel 2 mask \hideinitializer */ +#define BPWM_CH_3_MASK (0x8UL) /*!< BPWM channel 3 mask \hideinitializer */ +#define BPWM_CH_4_MASK (0x10UL) /*!< BPWM channel 4 mask \hideinitializer */ +#define BPWM_CH_5_MASK (0x20UL) /*!< BPWM channel 5 mask \hideinitializer */ + +/*---------------------------------------------------------------------------------------------------------*/ +/* Counter Type Constant Definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define BPWM_UP_COUNTER (0UL) /*!< Up counter type */ +#define BPWM_DOWN_COUNTER (1UL) /*!< Down counter type */ +#define BPWM_UP_DOWN_COUNTER (2UL) /*!< Up-Down counter type */ + +/*---------------------------------------------------------------------------------------------------------*/ +/* Aligned Type Constant Definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define BPWM_EDGE_ALIGNED (1UL) /*!< BPWM working in edge aligned type(down count) */ +#define BPWM_CENTER_ALIGNED (2UL) /*!< BPWM working in center aligned type */ + +/*---------------------------------------------------------------------------------------------------------*/ +/* Output Level Constant Definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define BPWM_OUTPUT_NOTHING (0UL) /*!< BPWM output nothing */ +#define BPWM_OUTPUT_LOW (1UL) /*!< BPWM output low */ +#define BPWM_OUTPUT_HIGH (2UL) /*!< BPWM output high */ +#define BPWM_OUTPUT_TOGGLE (3UL) /*!< BPWM output toggle */ + +/*---------------------------------------------------------------------------------------------------------*/ +/* Synchronous Start Function Control Constant Definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define BPWM_SSCTL_SSRC_PWM0 (0UL<SSCTL = ((bpwm)->SSCTL & ~BPWM_SSCTL_SSRC_Msk) | (u32SyncSrc) | BPWM_SSCTL_SSEN0_Msk) + +/** + * @brief Disable timer synchronous start counting function of specified channel(s) + * @param[in] bpwm The pointer of the specified BPWM module + * @param[in] u32ChannelMask Combination of enabled channels. This parameter is not used. + * @return None + * @details This macro is used to disable timer synchronous start counting function of specified channel(s). + * @note All channels share channel 0's setting. + * \hideinitializer + */ +#define BPWM_DISABLE_TIMER_SYNC(bpwm, u32ChannelMask) ((bpwm)->SSCTL &= ~BPWM_SSCTL_SSEN0_Msk) + +/** + * @brief This macro enable BPWM counter synchronous start counting function. + * @param[in] bpwm The pointer of the specified BPWM module + * @return None + * @details This macro is used to make selected BPWM0 and BPWM1 channel(s) start counting at the same time. + * To configure synchronous start counting channel(s) by BPWM_ENABLE_TIMER_SYNC() and BPWM_DISABLE_TIMER_SYNC(). + * \hideinitializer + */ +#define BPWM_TRIGGER_SYNC_START(bpwm) ((bpwm)->SSTRG = BPWM_SSTRG_CNTSEN_Msk) + +/** + * @brief This macro enable output inverter of specified channel(s) + * @param[in] bpwm The pointer of the specified BPWM module + * @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel + * Bit 0 represents channel 0, bit 1 represents channel 1... + * @return None + * \hideinitializer + */ +#define BPWM_ENABLE_OUTPUT_INVERTER(bpwm, u32ChannelMask) ((bpwm)->POLCTL = (u32ChannelMask)) + +/** + * @brief This macro get captured rising data + * @param[in] bpwm The pointer of the specified BPWM module + * @param[in] u32ChannelNum BPWM channel number. Valid values are between 0~5 + * @return None + * \hideinitializer + */ +#define BPWM_GET_CAPTURE_RISING_DATA(bpwm, u32ChannelNum) ((bpwm)->CAPDAT[(u32ChannelNum)].RCAPDAT) + +/** + * @brief This macro get captured falling data + * @param[in] bpwm The pointer of the specified BPWM module + * @param[in] u32ChannelNum BPWM channel number. Valid values are between 0~5 + * @return None + * \hideinitializer + */ +#define BPWM_GET_CAPTURE_FALLING_DATA(bpwm, u32ChannelNum) ((bpwm)->CAPDAT[(u32ChannelNum)].FCAPDAT) + +/** + * @brief This macro mask output logic to high or low + * @param[in] bpwm The pointer of the specified BPWM module + * @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel + * Bit 0 represents channel 0, bit 1 represents channel 1... + * @param[in] u32LevelMask Output logic to high or low + * @return None + * @details This macro is used to mask output logic to high or low of specified channel(s). + * @note If u32ChannelMask parameter is 0, then mask function will be disabled. + * \hideinitializer + */ +#define BPWM_MASK_OUTPUT(bpwm, u32ChannelMask, u32LevelMask) \ + { \ + (bpwm)->MSKEN = (u32ChannelMask); \ + (bpwm)->MSK = (u32LevelMask); \ + } + +/** + * @brief This macro set the prescaler of all channels + * @param[in] bpwm The pointer of the specified BPWM module + * @param[in] u32ChannelNum BPWM channel number. This parameter is not used. + * @param[in] u32Prescaler Clock prescaler of specified channel. Valid values are between 1 ~ 0xFFF + * @return None + * \hideinitializer + */ +#define BPWM_SET_PRESCALER(bpwm, u32ChannelNum, u32Prescaler) ((bpwm)->CLKPSC = (u32Prescaler)) + +/** + * @brief This macro set the duty of the selected channel + * @param[in] bpwm The pointer of the specified BPWM module + * @param[in] u32ChannelNum BPWM channel number. Valid values are between 0~5 + * @param[in] u32CMR Duty of specified channel. Valid values are between 0~0xFFFF + * @return None + * @note This new setting will take effect on next BPWM period + * \hideinitializer + */ +#define BPWM_SET_CMR(bpwm, u32ChannelNum, u32CMR) ((bpwm)->CMPDAT[(u32ChannelNum)] = (u32CMR)) + +/** + * @brief This macro get the duty of the selected channel + * @param[in] bpwm The pointer of the specified BPWM module + * @param[in] u32ChannelNum BPWM channel number. Valid values are between 0~5 + * @return Return the comparator of specified channel. Valid values are between 0~0xFFFF + * @details This macro is used to get the comparator of specified channel. + * \hideinitializer + */ +#define BPWM_GET_CMR(bpwm, u32ChannelNum) ((bpwm)->CMPDAT[(u32ChannelNum)]) + +/** + * @brief This macro set the period of all channels + * @param[in] bpwm The pointer of the specified BPWM module + * @param[in] u32ChannelNum BPWM channel number. This parameter is not used. + * @param[in] u32CNR Period of specified channel. Valid values are between 0~0xFFFF + * @return None + * @note This new setting will take effect on next BPWM period + * @note BPWM counter will stop if period length set to 0 + * \hideinitializer + */ +#define BPWM_SET_CNR(bpwm, u32ChannelNum, u32CNR) ((bpwm)->PERIOD = (u32CNR)) + +/** + * @brief This macro get the period of all channels + * @param[in] bpwm The pointer of the specified BPWM module + * @param[in] u32ChannelNum BPWM channel number. This parameter is not used. + * @return None + * \hideinitializer + */ +#define BPWM_GET_CNR(bpwm, u32ChannelNum) ((bpwm)->PERIOD) + +/** + * @brief This macro set the BPWM aligned type + * @param[in] bpwm The pointer of the specified BPWM module + * @param[in] u32ChannelMask Combination of enabled channels. This parameter is not used. + * @param[in] u32AlignedType BPWM aligned type, valid values are: + * - \ref BPWM_EDGE_ALIGNED + * - \ref BPWM_CENTER_ALIGNED + * @return None + * @note All channels share channel 0's setting. + * \hideinitializer + */ +#define BPWM_SET_ALIGNED_TYPE(bpwm, u32ChannelMask, u32AlignedType) ((bpwm)->CTL1 = (u32AlignedType)) + +/** + * @brief Clear counter of channel 0 + * @param[in] bpwm The pointer of the specified BPWM module + * @param[in] u32ChannelMask Combination of enabled channels. This parameter is not used. + * @return None + * @details This macro is used to clear counter of channel 0 + * \hideinitializer + */ +#define BPWM_CLR_COUNTER(bpwm, u32ChannelMask) ((bpwm)->CNTCLR = (BPWM_CNTCLR_CNTCLR0_Msk)) + +/** + * @brief Set output level at zero, compare up, period(center) and compare down of specified channel(s) + * @param[in] bpwm The pointer of the specified BPWM module + * @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel + * Bit 0 represents channel 0, bit 1 represents channel 1... + * @param[in] u32ZeroLevel output level at zero point, valid values are: + * - \ref BPWM_OUTPUT_NOTHING + * - \ref BPWM_OUTPUT_LOW + * - \ref BPWM_OUTPUT_HIGH + * - \ref BPWM_OUTPUT_TOGGLE + * @param[in] u32CmpUpLevel output level at compare up point, valid values are: + * - \ref BPWM_OUTPUT_NOTHING + * - \ref BPWM_OUTPUT_LOW + * - \ref BPWM_OUTPUT_HIGH + * - \ref BPWM_OUTPUT_TOGGLE + * @param[in] u32PeriodLevel output level at period(center) point, valid values are: + * - \ref BPWM_OUTPUT_NOTHING + * - \ref BPWM_OUTPUT_LOW + * - \ref BPWM_OUTPUT_HIGH + * - \ref BPWM_OUTPUT_TOGGLE + * @param[in] u32CmpDownLevel output level at compare down point, valid values are: + * - \ref BPWM_OUTPUT_NOTHING + * - \ref BPWM_OUTPUT_LOW + * - \ref BPWM_OUTPUT_HIGH + * - \ref BPWM_OUTPUT_TOGGLE + * @return None + * @details This macro is used to Set output level at zero, compare up, period(center) and compare down of specified channel(s) + * \hideinitializer + */ +#define BPWM_SET_OUTPUT_LEVEL(bpwm, u32ChannelMask, u32ZeroLevel, u32CmpUpLevel, u32PeriodLevel, u32CmpDownLevel) \ + do{ \ + uint32_t i; \ + for(i = 0UL; i < 6UL; i++) { \ + if((u32ChannelMask) & (1UL << i)) { \ + (bpwm)->WGCTL0 = (((bpwm)->WGCTL0 & ~(3UL << (i << 1))) | ((u32ZeroLevel) << (i << 1))); \ + (bpwm)->WGCTL0 = (((bpwm)->WGCTL0 & ~(3UL << (BPWM_WGCTL0_PRDPCTL0_Pos + (i << 1)))) | ((u32PeriodLevel) << (BPWM_WGCTL0_PRDPCTL0_Pos + (i << 1)))); \ + (bpwm)->WGCTL1 = (((bpwm)->WGCTL1 & ~(3UL << (i << 1))) | ((u32CmpUpLevel) << (i << 1))); \ + (bpwm)->WGCTL1 = (((bpwm)->WGCTL1 & ~(3UL << (BPWM_WGCTL1_CMPDCTL0_Pos + (i << 1)))) | ((u32CmpDownLevel) << (BPWM_WGCTL1_CMPDCTL0_Pos + (i << 1)))); \ + } \ + } \ + }while(0) + + +/*---------------------------------------------------------------------------------------------------------*/ +/* Define BPWM functions prototype */ +/*---------------------------------------------------------------------------------------------------------*/ +uint32_t BPWM_ConfigCaptureChannel(BPWM_T *bpwm, uint32_t u32ChannelNum, uint32_t u32UnitTimeNsec, uint32_t u32CaptureEdge); +uint32_t BPWM_ConfigOutputChannel(BPWM_T *bpwm, uint32_t u32ChannelNum, uint32_t u32Frequency, uint32_t u32DutyCycle); +void BPWM_Start(BPWM_T *bpwm, uint32_t u32ChannelMask); +void BPWM_Stop(BPWM_T *bpwm, uint32_t u32ChannelMask); +void BPWM_ForceStop(BPWM_T *bpwm, uint32_t u32ChannelMask); +void BPWM_EnableADCTrigger(BPWM_T *bpwm, uint32_t u32ChannelNum, uint32_t u32Condition); +void BPWM_DisableADCTrigger(BPWM_T *bpwm, uint32_t u32ChannelNum); +void BPWM_ClearADCTriggerFlag(BPWM_T *bpwm, uint32_t u32ChannelNum, uint32_t u32Condition); +uint32_t BPWM_GetADCTriggerFlag(BPWM_T *bpwm, uint32_t u32ChannelNum); +void BPWM_EnableCapture(BPWM_T *bpwm, uint32_t u32ChannelMask); +void BPWM_DisableCapture(BPWM_T *bpwm, uint32_t u32ChannelMask); +void BPWM_EnableOutput(BPWM_T *bpwm, uint32_t u32ChannelMask); +void BPWM_DisableOutput(BPWM_T *bpwm, uint32_t u32ChannelMask); +void BPWM_EnableCaptureInt(BPWM_T *bpwm, uint32_t u32ChannelNum, uint32_t u32Edge); +void BPWM_DisableCaptureInt(BPWM_T *bpwm, uint32_t u32ChannelNum, uint32_t u32Edge); +void BPWM_ClearCaptureIntFlag(BPWM_T *bpwm, uint32_t u32ChannelNum, uint32_t u32Edge); +uint32_t BPWM_GetCaptureIntFlag(BPWM_T *bpwm, uint32_t u32ChannelNum); +void BPWM_EnableDutyInt(BPWM_T *bpwm, uint32_t u32ChannelNum, uint32_t u32IntDutyType); +void BPWM_DisableDutyInt(BPWM_T *bpwm, uint32_t u32ChannelNum); +void BPWM_ClearDutyIntFlag(BPWM_T *bpwm, uint32_t u32ChannelNum); +uint32_t BPWM_GetDutyIntFlag(BPWM_T *bpwm, uint32_t u32ChannelNum); +void BPWM_EnablePeriodInt(BPWM_T *bpwm, uint32_t u32ChannelNum, uint32_t u32IntPeriodType); +void BPWM_DisablePeriodInt(BPWM_T *bpwm, uint32_t u32ChannelNum); +void BPWM_ClearPeriodIntFlag(BPWM_T *bpwm, uint32_t u32ChannelNum); +uint32_t BPWM_GetPeriodIntFlag(BPWM_T *bpwm, uint32_t u32ChannelNum); +void BPWM_EnableZeroInt(BPWM_T *bpwm, uint32_t u32ChannelNum); +void BPWM_DisableZeroInt(BPWM_T *bpwm, uint32_t u32ChannelNum); +void BPWM_ClearZeroIntFlag(BPWM_T *bpwm, uint32_t u32ChannelNum); +uint32_t BPWM_GetZeroIntFlag(BPWM_T *bpwm, uint32_t u32ChannelNum); +void BPWM_EnableLoadMode(BPWM_T *bpwm, uint32_t u32ChannelNum, uint32_t u32LoadMode); +void BPWM_DisableLoadMode(BPWM_T *bpwm, uint32_t u32ChannelNum, uint32_t u32LoadMode); +void BPWM_SetClockSource(BPWM_T *bpwm, uint32_t u32ChannelNum, uint32_t u32ClkSrcSel); +uint32_t BPWM_GetWrapAroundFlag(BPWM_T *bpwm, uint32_t u32ChannelNum); +void BPWM_ClearWrapAroundFlag(BPWM_T *bpwm, uint32_t u32ChannelNum); + +/**@}*/ /* end of group BPWM_EXPORTED_FUNCTIONS */ + +/**@}*/ /* end of group BPWM_Driver */ + +/**@}*/ /* end of group Standard_Driver */ + +#ifdef __cplusplus +} +#endif + +#endif /* __NU_BPWM_H__ */ + diff --git a/Ubiquitous/XiZi/board/nuvoton-m2354/third_party_driver/include/Drivers/nu_can.h b/Ubiquitous/XiZi/board/nuvoton-m2354/third_party_driver/include/Drivers/nu_can.h new file mode 100644 index 0000000..32ee780 --- /dev/null +++ b/Ubiquitous/XiZi/board/nuvoton-m2354/third_party_driver/include/Drivers/nu_can.h @@ -0,0 +1,188 @@ +/**************************************************************************//** + * @file nu_can.h + * @version V3.00 + * @brief CAN Driver Header File + * + * @copyright SPDX-License-Identifier: Apache-2.0 + * @copyright Copyright (C) 2020 Nuvoton Technology Corp. All rights reserved. + ******************************************************************************/ +#ifndef __NU_CAN_H__ +#define __NU_CAN_H__ + + +#ifdef __cplusplus +extern "C" +{ +#endif + + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup CAN_Driver CAN Driver + @{ +*/ + +/** @addtogroup CAN_EXPORTED_CONSTANTS CAN Exported Constants + @{ +*/ +/*---------------------------------------------------------------------------------------------------------*/ +/* CAN Test Mode Constant Definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define CAN_NORMAL_MODE 0U /*!< CAN select normal mode */ +#define CAN_BASIC_MODE 1U /*!< CAN select basic mode */ + +/*---------------------------------------------------------------------------------------------------------*/ +/* Message ID Type Constant Definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define CAN_STD_ID 0UL /*!< CAN select standard ID */ +#define CAN_EXT_ID 1UL /*!< CAN select extended ID */ + +/*---------------------------------------------------------------------------------------------------------*/ +/* Message Frame Type Constant Definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define CAN_REMOTE_FRAME 0 /*!< CAN frame select remote frame */ +#define CAN_DATA_FRAME 1 /*!< CAN frame select data frame */ + +/**@}*/ /* end of group CAN_EXPORTED_CONSTANTS */ + + +/** @addtogroup CAN_EXPORTED_STRUCTS CAN Exported Structs + @{ +*/ +/** + * @details CAN message structure + */ +typedef struct +{ + uint32_t IdType; /*!< ID type */ + uint32_t FrameType; /*!< Frame type */ + uint32_t Id; /*!< Message ID */ + uint8_t DLC; /*!< Data length */ + uint8_t Data[8]; /*!< Data */ + uint8_t padding[3]; /*!< Just for padding for memory alignment*/ +} STR_CANMSG_T; + +/** + * @details CAN mask message structure + */ +typedef struct +{ + uint8_t u8Xtd; /*!< Extended ID */ + uint8_t u8Dir; /*!< Direction */ + uint32_t u32Id; /*!< Message ID */ + uint8_t u8IdType; /*!< ID type*/ +} STR_CANMASK_T; + +/**@}*/ /* end of group CAN_EXPORTED_STRUCTS */ + +/** @cond HIDDEN_SYMBOLS */ +#define MSG(id) (id) +/** @endcond HIDDEN_SYMBOLS */ + +/** @addtogroup CAN_EXPORTED_FUNCTIONS CAN Exported Functions + @{ +*/ + +/** + * @brief Get interrupt status. + * + * @param[in] can The base address of can module. + * + * @return CAN module status register value. + * + * @details Status Interrupt is generated by bits BOff (CAN_STATUS[7]), EWarn (CAN_STATUS[6]), + * EPass (CAN_STATUS[5]), RxOk (CAN_STATUS[4]), TxOk (CAN_STATUS[3]), and LEC (CAN_STATUS[2:0]). + */ +#define CAN_GET_INT_STATUS(can) ((can)->STATUS) + +/** + * @brief Get specified interrupt pending status. + * + * @param[in] can The base address of can module. + * + * @return The source of the interrupt. + * + * @details If several interrupts are pending, the CAN Interrupt Register will point to the pending interrupt + * with the highest priority, disregarding their chronological order. + */ +#define CAN_GET_INT_PENDING_STATUS(can) ((can)->IIDR) + +/** + * @brief Disable wake-up function. + * + * @param[in] can The base address of can module. + * + * @return None + * + * @details The macro is used to disable wake-up function. + */ +#define CAN_DISABLE_WAKEUP(can) ((can)->WU_EN = 0) + +/** + * @brief Enable wake-up function. + * + * @param[in] can The base address of can module. + * + * @return None + * + * @details User can wake-up system when there is a falling edge in the CAN_Rx pin. + */ +#define CAN_ENABLE_WAKEUP(can) ((can)->WU_EN = CAN_WU_EN_WAKUP_EN_Msk) + +/** + * @brief Get specified Message Object new data into bit value. + * + * @param[in] can The base address of can module. + * @param[in] u32MsgNum Specified Message Object number, valid value are from 0 to 31. + * + * @return Specified Message Object new data into bit value. + * + * @details The NewDat bit (CAN_IFn_MCON[15]) of a specific Message Object can be set/reset by the software through the IFn Message Interface Registers + * or by the Message Handler after reception of a Data Frame or after a successful transmission. + */ +#define CAN_GET_NEW_DATA_IN_BIT(can, u32MsgNum) ((u32MsgNum) < 16 ? (can)->NDAT1 & (1 << (u32MsgNum)) : (can)->NDAT2 & (1 << ((u32MsgNum)-16))) + + +/*---------------------------------------------------------------------------------------------------------*/ +/* Define CAN functions prototype */ +/*---------------------------------------------------------------------------------------------------------*/ +uint32_t CAN_SetBaudRate(CAN_T *tCAN, uint32_t u32BaudRate); +void CAN_Close(CAN_T *tCAN); +uint32_t CAN_Open(CAN_T *tCAN, uint32_t u32BaudRate, uint32_t u32Mode); +void CAN_CLR_INT_PENDING_BIT(CAN_T *tCAN, uint8_t u32MsgNum); +void CAN_EnableInt(CAN_T *tCAN, uint32_t u32Mask); +void CAN_DisableInt(CAN_T *tCAN, uint32_t u32Mask); +int32_t CAN_Transmit(CAN_T *tCAN, uint32_t u32MsgNum, STR_CANMSG_T* pCanMsg); +int32_t CAN_Receive(CAN_T *tCAN, uint32_t u32MsgNum, STR_CANMSG_T* pCanMsg); +int32_t CAN_SetMultiRxMsg(CAN_T *tCAN, uint32_t u32MsgNum, uint32_t u32MsgCount, uint32_t u32IDType, uint32_t u32ID); +int32_t CAN_SetRxMsg(CAN_T *tCAN, uint32_t u32MsgNum, uint32_t u32IDType, uint32_t u32ID); +int32_t CAN_SetRxMsgAndMsk(CAN_T *tCAN, uint32_t u32MsgNum, uint32_t u32IDType, uint32_t u32ID, uint32_t u32IDMask); +int32_t CAN_SetTxMsg(CAN_T *tCAN, uint32_t u32MsgNum, STR_CANMSG_T* pCanMsg); +int32_t CAN_TriggerTxMsg(CAN_T *tCAN, uint32_t u32MsgNum); +void CAN_EnterInitMode(CAN_T *tCAN, uint8_t u8Mask); +void CAN_LeaveInitMode(CAN_T *tCAN); +void CAN_WaitMsg(CAN_T *tCAN); +uint32_t CAN_GetCANBitRate(CAN_T *tCAN); +void CAN_EnterTestMode(CAN_T *tCAN, uint8_t u8TestMask); +void CAN_LeaveTestMode(CAN_T *tCAN); +uint32_t CAN_IsNewDataReceived(CAN_T *tCAN, uint8_t u8MsgObj); +int32_t CAN_BasicSendMsg(CAN_T *tCAN, STR_CANMSG_T* pCanMsg); +int32_t CAN_BasicReceiveMsg(CAN_T *tCAN, STR_CANMSG_T* pCanMsg); +int32_t CAN_SetRxMsgObjAndMsk(CAN_T *tCAN, uint8_t u8MsgObj, uint8_t u8idType, uint32_t u32id, uint32_t u32idmask, uint8_t u8singleOrFifoLast); +int32_t CAN_SetRxMsgObj(CAN_T *tCAN, uint8_t u8MsgObj, uint8_t u8idType, uint32_t u32id, uint8_t u8singleOrFifoLast); +int32_t CAN_ReadMsgObj(CAN_T *tCAN, uint8_t u8MsgObj, uint8_t u8Release, STR_CANMSG_T* pCanMsg); + + +/**@}*/ /* end of group CAN_EXPORTED_FUNCTIONS */ + +/**@}*/ /* end of group CAN_Driver */ + +/**@}*/ /* end of group Standard_Driver */ + +#ifdef __cplusplus +} +#endif + +#endif /* __NU_CAN_H__ */ diff --git a/Ubiquitous/XiZi/board/nuvoton-m2354/third_party_driver/include/Drivers/nu_clk.h b/Ubiquitous/XiZi/board/nuvoton-m2354/third_party_driver/include/Drivers/nu_clk.h new file mode 100644 index 0000000..ff9fd8b --- /dev/null +++ b/Ubiquitous/XiZi/board/nuvoton-m2354/third_party_driver/include/Drivers/nu_clk.h @@ -0,0 +1,1070 @@ +/**************************************************************************//** + * @file nu_clk.h + * @version V3.0 + * @brief Clock Controller (CLK) driver header file + * + * @copyright SPDX-License-Identifier: Apache-2.0 + * @copyright Copyright (C) 2020 Nuvoton Technology Corp. All rights reserved. + ******************************************************************************/ +#ifndef __NU_CLK_H__ +#define __NU_CLK_H__ + + +#ifdef __cplusplus +extern "C" +{ +#endif + + + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup CLK_Driver CLK Driver + @{ +*/ + +/** @addtogroup CLK_EXPORTED_CONSTANTS CLK Exported Constants + @{ +*/ + + +#define FREQ_2MHZ 2000000UL +#define FREQ_4MHZ 4000000UL +#define FREQ_8MHZ 8000000UL +#define FREQ_12MHZ 12000000UL +#define FREQ_24MHZ 24000000UL +#define FREQ_25MHZ 25000000UL +#define FREQ_48MHZ 48000000UL +#define FREQ_50MHZ 50000000UL +#define FREQ_64MHZ 64000000UL +#define FREQ_75MHZ 75000000UL +#define FREQ_84MHZ 84000000UL +#define FREQ_96MHZ 96000000UL +#define FREQ_144MHZ 144000000UL +#define FREQ_200MHZ 200000000UL + + + +/*---------------------------------------------------------------------------------------------------------*/ +/* CLKSEL0 constant definitions. */ +/*---------------------------------------------------------------------------------------------------------*/ +#define CLK_CLKSEL0_HCLKSEL_HXT (0x00UL<>30) & 0x3UL) /*!< Calculate AHBCLK/APBCLK offset on MODULE index, 0x0:AHBCLK, 0x1:APBCLK0, 0x2:APBCLK1 */ +#define MODULE_CLKSEL(x) (((x) >>28) & 0x3UL) /*!< Calculate CLKSEL offset on MODULE index, 0x0:CLKSEL0, 0x1:CLKSEL1, 0x2:CLKSEL2, 0x3:CLKSEL3 */ +#define MODULE_CLKSEL_Msk(x) (((x) >>25) & 0x7UL) /*!< Calculate CLKSEL mask offset on MODULE index */ +#define MODULE_CLKSEL_Pos(x) (((x) >>20) & 0x1fUL) /*!< Calculate CLKSEL position offset on MODULE index */ +#define MODULE_CLKDIV(x) (((x) >>18) & 0x3UL) /*!< Calculate APBCLK CLKDIV on MODULE index, 0x0:CLKDIV0, 0x1:CLKDIV1, 0x4:CLKDIV4 */ +#define MODULE_CLKDIV_Msk(x) (((x) >>10) & 0xffUL) /*!< Calculate CLKDIV mask offset on MODULE index */ +#define MODULE_CLKDIV_Pos(x) (((x) >>5 ) & 0x1fUL) /*!< Calculate CLKDIV position offset on MODULE index */ +#define MODULE_IP_EN_Pos(x) (((x) >>0 ) & 0x1fUL) /*!< Calculate APBCLK offset on MODULE index */ +#define MODULE_NoMsk 0x0UL /*!< Not mask on MODULE index */ +#define NA MODULE_NoMsk /*!< Not Available */ + +#define MODULE_APBCLK_ENC(x) (((x) & 0x03UL) << 30) /*!< MODULE index, 0x0:AHBCLK, 0x1:APBCLK0, 0x2:APBCLK1 */ +#define MODULE_CLKSEL_ENC(x) (((x) & 0x03UL) << 28) /*!< CLKSEL offset on MODULE index, 0x0:CLKSEL0, 0x1:CLKSEL1, 0x2:CLKSEL2, 0x3:CLKSEL3 */ +#define MODULE_CLKSEL_Msk_ENC(x) (((x) & 0x07UL) << 25) /*!< CLKSEL mask offset on MODULE index */ +#define MODULE_CLKSEL_Pos_ENC(x) (((x) & 0x1fUL) << 20) /*!< CLKSEL position offset on MODULE index */ +#define MODULE_CLKDIV_ENC(x) (((x) & 0x03UL) << 18) /*!< APBCLK CLKDIV on MODULE index, 0x0:CLKDIV, 0x1:CLKDIV1, 0x4:CLKDIV4 */ +#define MODULE_CLKDIV_Msk_ENC(x) (((x) & 0xffUL) << 10) /*!< CLKDIV mask offset on MODULE index */ +#define MODULE_CLKDIV_Pos_ENC(x) (((x) & 0x1fUL) << 5) /*!< CLKDIV position offset on MODULE index */ +#define MODULE_IP_EN_Pos_ENC(x) (((x) & 0x1fUL) << 0) /*!< AHBCLK/APBCLK offset on MODULE index */ + + +/* AHBCLK */ +#define PDMA0_MODULE (MODULE_APBCLK_ENC( 0UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_AHBCLK_PDMA0CKEN_Pos)|\ + MODULE_CLKSEL_ENC( NA)|MODULE_CLKSEL_Msk_ENC(NA)|MODULE_CLKSEL_Pos_ENC(NA)|\ + MODULE_CLKDIV_ENC( NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA)) /*!< PDMA Module */ + +#define PDMA1_MODULE (MODULE_APBCLK_ENC( 0UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_AHBCLK_PDMA1CKEN_Pos)|\ + MODULE_CLKSEL_ENC( NA)|MODULE_CLKSEL_Msk_ENC(NA)|MODULE_CLKSEL_Pos_ENC(NA)|\ + MODULE_CLKDIV_ENC( NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA)) /*!< PDMA Module */ + +#define ISP_MODULE (MODULE_APBCLK_ENC( 0UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_AHBCLK_ISPCKEN_Pos)|\ + MODULE_CLKSEL_ENC( NA)|MODULE_CLKSEL_Msk_ENC(NA)|MODULE_CLKSEL_Pos_ENC(NA)|\ + MODULE_CLKDIV_ENC( NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA)) /*!< ISP Module */ + +#define EBI_MODULE (MODULE_APBCLK_ENC( 0UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_AHBCLK_EBICKEN_Pos)|\ + MODULE_CLKSEL_ENC( NA)|MODULE_CLKSEL_Msk_ENC(NA)|MODULE_CLKSEL_Pos_ENC(NA)|\ + MODULE_CLKDIV_ENC( NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA)) /*!< EBI Module */ + +#define EXST_MODULE (MODULE_APBCLK_ENC( 0UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_AHBCLK_EXSTCKEN_Pos)|\ + MODULE_CLKSEL_ENC( NA)|MODULE_CLKSEL_Msk_ENC(NA)|MODULE_CLKSEL_Pos_ENC(NA)|\ + MODULE_CLKDIV_ENC( NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA)) /*!< EXST Module */ + +#define SDH0_MODULE (MODULE_APBCLK_ENC( 0UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_AHBCLK_SDH0CKEN_Pos)|\ + MODULE_CLKSEL_ENC( 0UL)|MODULE_CLKSEL_Msk_ENC( 3UL)|MODULE_CLKSEL_Pos_ENC(20UL)|\ + MODULE_CLKDIV_ENC( 0UL)|MODULE_CLKDIV_Msk_ENC(0xFFUL)|MODULE_CLKDIV_Pos_ENC(24UL))/*!< SDH0 Module */ + +#define CRC_MODULE (MODULE_APBCLK_ENC( 0UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_AHBCLK_CRCCKEN_Pos)|\ + MODULE_CLKSEL_ENC( NA)|MODULE_CLKSEL_Msk_ENC(NA)|MODULE_CLKSEL_Pos_ENC(NA)|\ + MODULE_CLKDIV_ENC( NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA)) /*!< CRC Module */ + +#define CRPT_MODULE (MODULE_APBCLK_ENC( 0UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_AHBCLK_CRPTCKEN_Pos)|\ + MODULE_CLKSEL_ENC( NA)|MODULE_CLKSEL_Msk_ENC(NA)|MODULE_CLKSEL_Pos_ENC(NA)|\ + MODULE_CLKDIV_ENC( NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA)) /*!< CRPT Module */ + +#define KS_MODULE (MODULE_APBCLK_ENC( 0UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_AHBCLK_KSCKEN_Pos)|\ + MODULE_CLKSEL_ENC( NA)|MODULE_CLKSEL_Msk_ENC(NA)|MODULE_CLKSEL_Pos_ENC(NA)|\ + MODULE_CLKDIV_ENC( NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA)) /*!< KS Module */ + +#define TRACE_MODULE (MODULE_APBCLK_ENC( 0UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_AHBCLK_TRACECKEN_Pos)|\ + MODULE_CLKSEL_ENC( NA)|MODULE_CLKSEL_Msk_ENC(NA)|MODULE_CLKSEL_Pos_ENC(NA)|\ + MODULE_CLKDIV_ENC( NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA)) /*!< TRACE Module */ + +#define FMCIDLE_MODULE (MODULE_APBCLK_ENC( 0UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_AHBCLK_FMCIDLE_Pos)|\ + MODULE_CLKSEL_ENC( NA)|MODULE_CLKSEL_Msk_ENC(NA)|MODULE_CLKSEL_Pos_ENC(NA)|\ + MODULE_CLKDIV_ENC( NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA)) /*!< FMCIDLE Module */ + +#define USBH_MODULE (MODULE_APBCLK_ENC( 0UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_AHBCLK_USBHCKEN_Pos)|\ + MODULE_CLKSEL_ENC( 0UL)|MODULE_CLKSEL_Msk_ENC( 1UL)|MODULE_CLKSEL_Pos_ENC( 8UL)|\ + MODULE_CLKDIV_ENC( 0UL)|MODULE_CLKDIV_Msk_ENC(0xFUL)|MODULE_CLKDIV_Pos_ENC( 4UL)) /*!< USBH Module */ + +#define SRAM0_MODULE (MODULE_APBCLK_ENC( 0UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_AHBCLK_SRAM0CKEN_Pos)|\ + MODULE_CLKSEL_ENC( NA)|MODULE_CLKSEL_Msk_ENC(NA)|MODULE_CLKSEL_Pos_ENC(NA)|\ + MODULE_CLKDIV_ENC( NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA)) /*!< SRAM0 Module */ + +#define SRAM1_MODULE (MODULE_APBCLK_ENC( 0UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_AHBCLK_SRAM1CKEN_Pos)|\ + MODULE_CLKSEL_ENC( NA)|MODULE_CLKSEL_Msk_ENC(NA)|MODULE_CLKSEL_Pos_ENC(NA)|\ + MODULE_CLKDIV_ENC( NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA)) /*!< SRAM1 Module */ + +#define SRAM2_MODULE (MODULE_APBCLK_ENC( 0UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_AHBCLK_SRAM2CKEN_Pos)|\ + MODULE_CLKSEL_ENC( NA)|MODULE_CLKSEL_Msk_ENC(NA)|MODULE_CLKSEL_Pos_ENC(NA)|\ + MODULE_CLKDIV_ENC( NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA)) /*!< SRAM2 Module */ + +#define GPA_MODULE (MODULE_APBCLK_ENC( 0UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_AHBCLK_GPACKEN_Pos)|\ + MODULE_CLKSEL_ENC( NA)|MODULE_CLKSEL_Msk_ENC(NA)|MODULE_CLKSEL_Pos_ENC(NA)|\ + MODULE_CLKDIV_ENC( NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA)) /*!< GPA Module */ + +#define GPB_MODULE (MODULE_APBCLK_ENC( 0UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_AHBCLK_GPBCKEN_Pos)|\ + MODULE_CLKSEL_ENC( NA)|MODULE_CLKSEL_Msk_ENC(NA)|MODULE_CLKSEL_Pos_ENC(NA)|\ + MODULE_CLKDIV_ENC( NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA)) /*!< GPB Module */ + +#define GPC_MODULE (MODULE_APBCLK_ENC( 0UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_AHBCLK_GPCCKEN_Pos)|\ + MODULE_CLKSEL_ENC( NA)|MODULE_CLKSEL_Msk_ENC(NA)|MODULE_CLKSEL_Pos_ENC(NA)|\ + MODULE_CLKDIV_ENC( NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA)) /*!< GPC Module */ + +#define GPD_MODULE (MODULE_APBCLK_ENC( 0UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_AHBCLK_GPDCKEN_Pos)|\ + MODULE_CLKSEL_ENC( NA)|MODULE_CLKSEL_Msk_ENC(NA)|MODULE_CLKSEL_Pos_ENC(NA)|\ + MODULE_CLKDIV_ENC( NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA)) /*!< GPD Module */ + +#define GPE_MODULE (MODULE_APBCLK_ENC( 0UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_AHBCLK_GPECKEN_Pos)|\ + MODULE_CLKSEL_ENC( NA)|MODULE_CLKSEL_Msk_ENC(NA)|MODULE_CLKSEL_Pos_ENC(NA)|\ + MODULE_CLKDIV_ENC( NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA)) /*!< GPE Module */ + +#define GPF_MODULE (MODULE_APBCLK_ENC( 0UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_AHBCLK_GPFCKEN_Pos)|\ + MODULE_CLKSEL_ENC( NA)|MODULE_CLKSEL_Msk_ENC(NA)|MODULE_CLKSEL_Pos_ENC(NA)|\ + MODULE_CLKDIV_ENC( NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA)) /*!< GPF Module */ + +#define GPG_MODULE (MODULE_APBCLK_ENC( 0UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_AHBCLK_GPGCKEN_Pos)|\ + MODULE_CLKSEL_ENC( NA)|MODULE_CLKSEL_Msk_ENC(NA)|MODULE_CLKSEL_Pos_ENC(NA)|\ + MODULE_CLKDIV_ENC( NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA)) /*!< GPG Module */ + +#define GPH_MODULE (MODULE_APBCLK_ENC( 0UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_AHBCLK_GPHCKEN_Pos)|\ + MODULE_CLKSEL_ENC( NA)|MODULE_CLKSEL_Msk_ENC(NA)|MODULE_CLKSEL_Pos_ENC(NA)|\ + MODULE_CLKDIV_ENC( NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA)) /*!< GPH Module */ + +/* APBCLK0 */ +#define WDT_MODULE (MODULE_APBCLK_ENC( 1UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_APBCLK0_WDTCKEN_Pos)|\ + MODULE_CLKSEL_ENC( 1UL)|MODULE_CLKSEL_Msk_ENC( 3UL)|MODULE_CLKSEL_Pos_ENC( 0UL)|\ + MODULE_CLKDIV_ENC( NA)|MODULE_CLKDIV_Msk_ENC( NA)|MODULE_CLKDIV_Pos_ENC( NA)) /*!< WDT Module */ + +#define WWDT_MODULE (MODULE_APBCLK_ENC( 1UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_APBCLK0_WDTCKEN_Pos)|\ + MODULE_CLKSEL_ENC( 1UL)|MODULE_CLKSEL_Msk_ENC( 3UL)|MODULE_CLKSEL_Pos_ENC(30UL)|\ + MODULE_CLKDIV_ENC( NA)|MODULE_CLKDIV_Msk_ENC( NA)|MODULE_CLKDIV_Pos_ENC(NA)) /*!< WWDT Module */ + +#define RTC_MODULE (MODULE_APBCLK_ENC( 1UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_APBCLK0_RTCCKEN_Pos)|\ + MODULE_CLKSEL_ENC( NA)|MODULE_CLKSEL_Msk_ENC( NA)|MODULE_CLKSEL_Pos_ENC(NA)|\ + MODULE_CLKDIV_ENC( NA)|MODULE_CLKDIV_Msk_ENC( NA)|MODULE_CLKDIV_Pos_ENC(NA)) /*!< RTC Module */ + +#define TMR0_MODULE (MODULE_APBCLK_ENC( 1UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_APBCLK0_TMR0CKEN_Pos)|\ + MODULE_CLKSEL_ENC( 1UL)|MODULE_CLKSEL_Msk_ENC( 7UL)|MODULE_CLKSEL_Pos_ENC( 8UL)|\ + MODULE_CLKDIV_ENC( NA)|MODULE_CLKDIV_Msk_ENC( NA)|MODULE_CLKDIV_Pos_ENC( NA)) /*!< TMR0 Module */ + +#define TMR1_MODULE (MODULE_APBCLK_ENC( 1UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_APBCLK0_TMR1CKEN_Pos) |\ + MODULE_CLKSEL_ENC( 1UL)|MODULE_CLKSEL_Msk_ENC( 7UL)|MODULE_CLKSEL_Pos_ENC(12UL)|\ + MODULE_CLKDIV_ENC( NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC( NA)) /*!< TMR1 Module */ + +#define TMR2_MODULE (MODULE_APBCLK_ENC( 1UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_APBCLK0_TMR2CKEN_Pos) |\ + MODULE_CLKSEL_ENC( 1UL)|MODULE_CLKSEL_Msk_ENC( 7UL)|MODULE_CLKSEL_Pos_ENC(16UL)|\ + MODULE_CLKDIV_ENC( NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC( NA)) /*!< TMR2 Module */ + +#define TMR3_MODULE (MODULE_APBCLK_ENC( 1UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_APBCLK0_TMR3CKEN_Pos) |\ + MODULE_CLKSEL_ENC( 1UL)|MODULE_CLKSEL_Msk_ENC( 7UL)|MODULE_CLKSEL_Pos_ENC(20UL)|\ + MODULE_CLKDIV_ENC( NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC( NA)) /*!< TMR3 Module */ + +#define TMR4_MODULE (MODULE_APBCLK_ENC( 2UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_APBCLK1_TMR4CKEN_Pos) |\ + MODULE_CLKSEL_ENC( 3UL)|MODULE_CLKSEL_Msk_ENC( 7UL)|MODULE_CLKSEL_Pos_ENC(8UL)|\ + MODULE_CLKDIV_ENC( NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC( NA)) /*!< TMR4 Module */ + +#define TMR5_MODULE (MODULE_APBCLK_ENC( 2UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_APBCLK1_TMR5CKEN_Pos) |\ + MODULE_CLKSEL_ENC( 3UL)|MODULE_CLKSEL_Msk_ENC( 7UL)|MODULE_CLKSEL_Pos_ENC(12UL)|\ + MODULE_CLKDIV_ENC( NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC( NA)) /*!< TMR5 Module */ + +#define CLKO_MODULE (MODULE_APBCLK_ENC( 1UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_APBCLK0_CLKOCKEN_Pos) |\ + MODULE_CLKSEL_ENC( 1UL)|MODULE_CLKSEL_Msk_ENC(3UL)|MODULE_CLKSEL_Pos_ENC(28UL)|\ + MODULE_CLKDIV_ENC( NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC( NA)) /*!< CLKO Module */ + +#define ACMP01_MODULE (MODULE_APBCLK_ENC( 1UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_APBCLK0_ACMP01CKEN_Pos) |\ + MODULE_CLKSEL_ENC( NA)|MODULE_CLKSEL_Msk_ENC(NA)|MODULE_CLKSEL_Pos_ENC(NA)|\ + MODULE_CLKDIV_ENC( NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA)) /*!< ACMP01 Module */ + +#define I2C0_MODULE (MODULE_APBCLK_ENC( 1UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_APBCLK0_I2C0CKEN_Pos) |\ + MODULE_CLKSEL_ENC( NA)|MODULE_CLKSEL_Msk_ENC(NA)|MODULE_CLKSEL_Pos_ENC(NA)|\ + MODULE_CLKDIV_ENC( NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA)) /*!< I2C0 Module */ + +#define I2C1_MODULE (MODULE_APBCLK_ENC( 1UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_APBCLK0_I2C1CKEN_Pos) |\ + MODULE_CLKSEL_ENC( NA)|MODULE_CLKSEL_Msk_ENC(NA)|MODULE_CLKSEL_Pos_ENC(NA)|\ + MODULE_CLKDIV_ENC( NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA)) /*!< I2C1 Module */ + +#define I2C2_MODULE (MODULE_APBCLK_ENC( 1UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_APBCLK0_I2C2CKEN_Pos) |\ + MODULE_CLKSEL_ENC( NA)|MODULE_CLKSEL_Msk_ENC(NA)|MODULE_CLKSEL_Pos_ENC(NA)|\ + MODULE_CLKDIV_ENC( NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA)) /*!< I2C2 Module */ + +#define QSPI0_MODULE (MODULE_APBCLK_ENC( 1UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_APBCLK0_QSPI0CKEN_Pos) |\ + MODULE_CLKSEL_ENC( 2UL)|MODULE_CLKSEL_Msk_ENC( 3UL)|MODULE_CLKSEL_Pos_ENC( 2UL)|\ + MODULE_CLKDIV_ENC( NA)|MODULE_CLKDIV_Msk_ENC( NA)|MODULE_CLKDIV_Pos_ENC( NA)) /*!< QSPI0 Module */ + +#define SPI0_MODULE (MODULE_APBCLK_ENC(1UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_APBCLK0_SPI0CKEN_Pos) |\ + MODULE_CLKSEL_ENC(2UL)|MODULE_CLKSEL_Msk_ENC( 3UL)|MODULE_CLKSEL_Pos_ENC( 4UL)|\ + MODULE_CLKDIV_ENC(NA)|MODULE_CLKDIV_Msk_ENC( NA)|MODULE_CLKDIV_Pos_ENC( NA)) /*!< SPI0 Module */ + +#define SPI1_MODULE (MODULE_APBCLK_ENC( 1UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_APBCLK0_SPI1CKEN_Pos) |\ + MODULE_CLKSEL_ENC( 2UL)|MODULE_CLKSEL_Msk_ENC( 3UL)|MODULE_CLKSEL_Pos_ENC( 6UL)|\ + MODULE_CLKDIV_ENC( NA)|MODULE_CLKDIV_Msk_ENC( NA)|MODULE_CLKDIV_Pos_ENC( NA)) /*!< SPI1 Module */ + +#define SPI2_MODULE (MODULE_APBCLK_ENC( 1UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_APBCLK0_SPI2CKEN_Pos) |\ + MODULE_CLKSEL_ENC( 2UL)|MODULE_CLKSEL_Msk_ENC( 3UL)|MODULE_CLKSEL_Pos_ENC(10UL)|\ + MODULE_CLKDIV_ENC( NA)|MODULE_CLKDIV_Msk_ENC( NA)|MODULE_CLKDIV_Pos_ENC( NA)) /*!< SPI2 Module */ + +#define UART0_MODULE (MODULE_APBCLK_ENC( 1UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_APBCLK0_UART0CKEN_Pos)|\ + MODULE_CLKSEL_ENC( 2UL)|MODULE_CLKSEL_Msk_ENC( 7UL)|MODULE_CLKSEL_Pos_ENC(16UL)|\ + MODULE_CLKDIV_ENC( 0UL)|MODULE_CLKDIV_Msk_ENC(0x0FUL)|MODULE_CLKDIV_Pos_ENC( 8UL)) /*!< UART0 Module */ + +#define UART1_MODULE (MODULE_APBCLK_ENC( 1UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_APBCLK0_UART1CKEN_Pos)|\ + MODULE_CLKSEL_ENC( 2UL)|MODULE_CLKSEL_Msk_ENC( 7UL)|MODULE_CLKSEL_Pos_ENC(20UL)|\ + MODULE_CLKDIV_ENC( 0UL)|MODULE_CLKDIV_Msk_ENC(0x0FUL)|MODULE_CLKDIV_Pos_ENC(12UL)) /*!< UART1 Module */ + +#define UART2_MODULE (MODULE_APBCLK_ENC( 1UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_APBCLK0_UART2CKEN_Pos)|\ + MODULE_CLKSEL_ENC( 2UL)|MODULE_CLKSEL_Msk_ENC( 7UL)|MODULE_CLKSEL_Pos_ENC(24UL)|\ + MODULE_CLKDIV_ENC( 3UL)|MODULE_CLKDIV_Msk_ENC(0x0FUL)|MODULE_CLKDIV_Pos_ENC( 0UL)) /*!< UART2 Module */ + +#define UART3_MODULE (MODULE_APBCLK_ENC( 1UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_APBCLK0_UART3CKEN_Pos)|\ + MODULE_CLKSEL_ENC( 2UL)|MODULE_CLKSEL_Msk_ENC( 7UL)|MODULE_CLKSEL_Pos_ENC(28UL)|\ + MODULE_CLKDIV_ENC( 3UL)|MODULE_CLKDIV_Msk_ENC(0x0FUL)|MODULE_CLKDIV_Pos_ENC( 4UL)) /*!< UART3 Module */ + +#define UART4_MODULE (MODULE_APBCLK_ENC( 1UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_APBCLK0_UART4CKEN_Pos)|\ + MODULE_CLKSEL_ENC( 3UL)|MODULE_CLKSEL_Msk_ENC( 7UL)|MODULE_CLKSEL_Pos_ENC(24UL)|\ + MODULE_CLKDIV_ENC( 3UL)|MODULE_CLKDIV_Msk_ENC(0x0FUL)|MODULE_CLKDIV_Pos_ENC( 8UL)) /*!< UART4 Module */ + +#define UART5_MODULE (MODULE_APBCLK_ENC( 1UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_APBCLK0_UART5CKEN_Pos)|\ + MODULE_CLKSEL_ENC( 3UL)|MODULE_CLKSEL_Msk_ENC( 7UL)|MODULE_CLKSEL_Pos_ENC(28UL)|\ + MODULE_CLKDIV_ENC( 3UL)|MODULE_CLKDIV_Msk_ENC(0x0FUL)|MODULE_CLKDIV_Pos_ENC(12UL)) /*!< UART5 Module */ + +#define TAMPER_MODULE (MODULE_APBCLK_ENC( 1UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_APBCLK0_TAMPERCKEN_Pos)|\ + MODULE_CLKSEL_ENC( NA)|MODULE_CLKSEL_Msk_ENC( NA)|MODULE_CLKSEL_Pos_ENC( NA)|\ + MODULE_CLKDIV_ENC( NA)|MODULE_CLKDIV_Msk_ENC( NA)|MODULE_CLKDIV_Pos_ENC( NA)) /*!< TAMPER Module */ + +#define CAN0_MODULE (MODULE_APBCLK_ENC( 1UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_APBCLK0_CAN0CKEN_Pos)|\ + MODULE_CLKSEL_ENC( NA)|MODULE_CLKSEL_Msk_ENC(NA)|MODULE_CLKSEL_Pos_ENC(NA)|\ + MODULE_CLKDIV_ENC( NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA)) /*!< CAN0 Module */ + +#define OTG_MODULE (MODULE_APBCLK_ENC( 1UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_APBCLK0_OTGCKEN_Pos)|\ + MODULE_CLKSEL_ENC( 0UL)|MODULE_CLKSEL_Msk_ENC( 1UL)|MODULE_CLKSEL_Pos_ENC( 8UL)|\ + MODULE_CLKDIV_ENC( 0UL)|MODULE_CLKDIV_Msk_ENC(0x0FUL)|MODULE_CLKDIV_Pos_ENC( 4UL)) /*!< OTG Module */ + +#define USBD_MODULE (MODULE_APBCLK_ENC( 1UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_APBCLK0_USBDCKEN_Pos)|\ + MODULE_CLKSEL_ENC( 0UL)|MODULE_CLKSEL_Msk_ENC( 1UL)|MODULE_CLKSEL_Pos_ENC( 8UL)|\ + MODULE_CLKDIV_ENC( 0UL)|MODULE_CLKDIV_Msk_ENC(0x0FUL)|MODULE_CLKDIV_Pos_ENC(4UL)) /*!< USBD Module */ + +#define EADC_MODULE (MODULE_APBCLK_ENC( 1UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_APBCLK0_EADCCKEN_Pos)|\ + MODULE_CLKSEL_ENC( NA)|MODULE_CLKSEL_Msk_ENC( NA)|MODULE_CLKSEL_Pos_ENC( NA)|\ + MODULE_CLKDIV_ENC( 0UL)|MODULE_CLKDIV_Msk_ENC(0xFFUL)|MODULE_CLKDIV_Pos_ENC(16UL)) /*!< EADC Module */ + +#define I2S0_MODULE (MODULE_APBCLK_ENC( 1UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_APBCLK0_I2S0CKEN_Pos)|\ + MODULE_CLKSEL_ENC( 3UL)|MODULE_CLKSEL_Msk_ENC( 3UL)|MODULE_CLKSEL_Pos_ENC(16UL)|\ + MODULE_CLKDIV_ENC( NA)|MODULE_CLKDIV_Msk_ENC( NA)|MODULE_CLKDIV_Pos_ENC( NA)) /*!< I2S0 Module */ + +#define EWDT_MODULE (MODULE_APBCLK_ENC( 1UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_APBCLK0_EWDTCKEN_Pos)|\ + MODULE_CLKSEL_ENC( 1UL)|MODULE_CLKSEL_Msk_ENC( 3UL)|MODULE_CLKSEL_Pos_ENC( 4UL)|\ + MODULE_CLKDIV_ENC( NA)|MODULE_CLKDIV_Msk_ENC( NA)|MODULE_CLKDIV_Pos_ENC( NA)) /*!< EWDT Module */ + +#define EWWDT_MODULE (MODULE_APBCLK_ENC( 1UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_APBCLK0_EWDTCKEN_Pos)|\ + MODULE_CLKSEL_ENC( 1UL)|MODULE_CLKSEL_Msk_ENC( 3UL)|MODULE_CLKSEL_Pos_ENC( 6UL)|\ + MODULE_CLKDIV_ENC( NA)|MODULE_CLKDIV_Msk_ENC( NA)|MODULE_CLKDIV_Pos_ENC(NA)) /*!< EWWDT Module */ + + +/* APBCLK1 */ +#define SC0_MODULE (MODULE_APBCLK_ENC( 2UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_APBCLK1_SC0CKEN_Pos) |\ + MODULE_CLKSEL_ENC( 3UL)|MODULE_CLKSEL_Msk_ENC( 3UL)|MODULE_CLKSEL_Pos_ENC( 0UL)|\ + MODULE_CLKDIV_ENC( 1UL)|MODULE_CLKDIV_Msk_ENC(0xFFUL)|MODULE_CLKDIV_Pos_ENC( 0UL)) /*!< SC0 Module */ + +#define SC1_MODULE (MODULE_APBCLK_ENC( 2UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_APBCLK1_SC1CKEN_Pos) |\ + MODULE_CLKSEL_ENC( 3UL)|MODULE_CLKSEL_Msk_ENC( 3UL)|MODULE_CLKSEL_Pos_ENC( 2UL)|\ + MODULE_CLKDIV_ENC( 1UL)|MODULE_CLKDIV_Msk_ENC(0xFFUL)|MODULE_CLKDIV_Pos_ENC( 8UL)) /*!< SC1 Module */ + +#define SC2_MODULE (MODULE_APBCLK_ENC( 2UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_APBCLK1_SC2CKEN_Pos) |\ + MODULE_CLKSEL_ENC( 3UL)|MODULE_CLKSEL_Msk_ENC( 3UL)|MODULE_CLKSEL_Pos_ENC( 4UL)|\ + MODULE_CLKDIV_ENC( 1UL)|MODULE_CLKDIV_Msk_ENC(0xFFUL)|MODULE_CLKDIV_Pos_ENC(16UL)) /*!< SC2 Module */ + +#define SPI3_MODULE (MODULE_APBCLK_ENC( 2UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_APBCLK1_SPI3CKEN_Pos) |\ + MODULE_CLKSEL_ENC( 2UL)|MODULE_CLKSEL_Msk_ENC( 3UL)|MODULE_CLKSEL_Pos_ENC(12UL)|\ + MODULE_CLKDIV_ENC( NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA)) /*!< SPI3 Module */ + +#define USCI0_MODULE (MODULE_APBCLK_ENC( 2UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_APBCLK1_USCI0CKEN_Pos)|\ + MODULE_CLKSEL_ENC( NA)|MODULE_CLKSEL_Msk_ENC(NA)|MODULE_CLKSEL_Pos_ENC(NA)|\ + MODULE_CLKDIV_ENC( NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA)) /*!< USCI0 Module */ + +#define USCI1_MODULE (MODULE_APBCLK_ENC( 2UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_APBCLK1_USCI1CKEN_Pos)|\ + MODULE_CLKSEL_ENC( NA)|MODULE_CLKSEL_Msk_ENC(NA)|MODULE_CLKSEL_Pos_ENC(NA)|\ + MODULE_CLKDIV_ENC( NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA)) /*!< USCI1 Module */ + +#define DAC_MODULE (MODULE_APBCLK_ENC( 2UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_APBCLK1_DACCKEN_Pos)|\ + MODULE_CLKSEL_ENC( NA)|MODULE_CLKSEL_Msk_ENC(NA)|MODULE_CLKSEL_Pos_ENC(NA)|\ + MODULE_CLKDIV_ENC( NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA)) /*!< DAC Module */ + +#define EPWM0_MODULE (MODULE_APBCLK_ENC( 2UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_APBCLK1_EPWM0CKEN_Pos)|\ + MODULE_CLKSEL_ENC( NA)|MODULE_CLKSEL_Msk_ENC(NA)|MODULE_CLKSEL_Pos_ENC(NA)|\ + MODULE_CLKDIV_ENC( NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA)) /*!< EPWM0 Module */ + +#define EPWM1_MODULE (MODULE_APBCLK_ENC( 2UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_APBCLK1_EPWM1CKEN_Pos)|\ + MODULE_CLKSEL_ENC( NA)|MODULE_CLKSEL_Msk_ENC(NA)|MODULE_CLKSEL_Pos_ENC(NA)|\ + MODULE_CLKDIV_ENC( NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA)) /*!< EPWM1 Module */ + +#define BPWM0_MODULE (MODULE_APBCLK_ENC( 2UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_APBCLK1_BPWM0CKEN_Pos)|\ + MODULE_CLKSEL_ENC( NA)|MODULE_CLKSEL_Msk_ENC(NA)|MODULE_CLKSEL_Pos_ENC(NA)|\ + MODULE_CLKDIV_ENC( NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA)) /*!< BPWM0 Module */ + +#define BPWM1_MODULE (MODULE_APBCLK_ENC( 2UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_APBCLK1_BPWM1CKEN_Pos)|\ + MODULE_CLKSEL_ENC( NA)|MODULE_CLKSEL_Msk_ENC(NA)|MODULE_CLKSEL_Pos_ENC(NA)|\ + MODULE_CLKDIV_ENC( NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA)) /*!< BPWM1 Module */ + +#define QEI0_MODULE (MODULE_APBCLK_ENC( 2UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_APBCLK1_QEI0CKEN_Pos)|\ + MODULE_CLKSEL_ENC( NA)|MODULE_CLKSEL_Msk_ENC(NA)|MODULE_CLKSEL_Pos_ENC(NA)|\ + MODULE_CLKDIV_ENC( NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA)) /*!< QEI0 Module */ + +#define QEI1_MODULE (MODULE_APBCLK_ENC( 2UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_APBCLK1_QEI1CKEN_Pos)|\ + MODULE_CLKSEL_ENC( NA)|MODULE_CLKSEL_Msk_ENC(NA)|MODULE_CLKSEL_Pos_ENC(NA)|\ + MODULE_CLKDIV_ENC( NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA)) /*!< QEI1 Module */ + +#define LCD_MODULE (MODULE_APBCLK_ENC( 2UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_APBCLK1_LCDCKEN_Pos)|\ + MODULE_CLKSEL_ENC( 1UL)|MODULE_CLKSEL_Msk_ENC(1UL)|MODULE_CLKSEL_Pos_ENC(2UL)|\ + MODULE_CLKDIV_ENC( NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA)) /*!< LCD Module */ + +#define LCDCP_MODULE (MODULE_APBCLK_ENC( 2UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_APBCLK1_LCDCPCKEN_Pos)|\ + MODULE_CLKSEL_ENC( 1UL)|MODULE_CLKSEL_Msk_ENC(1UL)|MODULE_CLKSEL_Pos_ENC(3UL)|\ + MODULE_CLKDIV_ENC( NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA)) /*!< LCDCP Module */ + +#define TRNG_MODULE (MODULE_APBCLK_ENC( 2UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_APBCLK1_TRNGCKEN_Pos)|\ + MODULE_CLKSEL_ENC( NA)|MODULE_CLKSEL_Msk_ENC(NA)|MODULE_CLKSEL_Pos_ENC(NA)|\ + MODULE_CLKDIV_ENC( NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA)) /*!< TRNG Module */ + +#define ECAP0_MODULE (MODULE_APBCLK_ENC( 2UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_APBCLK1_ECAP0CKEN_Pos)|\ + MODULE_CLKSEL_ENC( NA)|MODULE_CLKSEL_Msk_ENC(NA)|MODULE_CLKSEL_Pos_ENC(NA)|\ + MODULE_CLKDIV_ENC( NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA)) /*!< ECAP0 Module */ + +#define ECAP1_MODULE (MODULE_APBCLK_ENC( 2UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_APBCLK1_ECAP1CKEN_Pos)|\ + MODULE_CLKSEL_ENC( NA)|MODULE_CLKSEL_Msk_ENC(NA)|MODULE_CLKSEL_Pos_ENC(NA)|\ + MODULE_CLKDIV_ENC( NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA)) /*!< ECAP1 Module */ + + +/*---------------------------------------------------------------------------------------------------------*/ +/* PDMSEL constant definitions. */ +/*---------------------------------------------------------------------------------------------------------*/ +#define CLK_PMUCTL_PDMSEL_PD (0x0UL << CLK_PMUCTL_PDMSEL_Pos) /*!< Select Power-down mode is Power-down mode */ +#define CLK_PMUCTL_PDMSEL_LLPD (0x1UL << CLK_PMUCTL_PDMSEL_Pos) /*!< Select Power-down mode is Low leakage Power-down mode */ +#define CLK_PMUCTL_PDMSEL_FWPD (0x2UL << CLK_PMUCTL_PDMSEL_Pos) /*!< Select Power-down mode is Fast Wake-up Power-down mode */ +#define CLK_PMUCTL_PDMSEL_ULLPD (0x3UL << CLK_PMUCTL_PDMSEL_Pos) /*!< Select Power-down mode is Ultra Low leakage Power-down mode */ +#define CLK_PMUCTL_PDMSEL_SPD (0x4UL << CLK_PMUCTL_PDMSEL_Pos) /*!< Select Power-down mode is Standby Power-down mode */ +#define CLK_PMUCTL_PDMSEL_DPD (0x6UL << CLK_PMUCTL_PDMSEL_Pos) /*!< Select Power-down mode is Deep Power-down mode */ + +/*---------------------------------------------------------------------------------------------------------*/ +/* WKTMRIS constant definitions. */ +/*---------------------------------------------------------------------------------------------------------*/ +#define CLK_PMUCTL_WKTMRIS_410 (0x0UL << CLK_PMUCTL_WKTMRIS_Pos) /*!< Select Wake-up Timer Time-out Interval is 410 LIRC clocks (12.8 ms) */ +#define CLK_PMUCTL_WKTMRIS_819 (0x1UL << CLK_PMUCTL_WKTMRIS_Pos) /*!< Select Wake-up Timer Time-out Interval is 819 LIRC clocks (25.6 ms) */ +#define CLK_PMUCTL_WKTMRIS_1638 (0x2UL << CLK_PMUCTL_WKTMRIS_Pos) /*!< Select Wake-up Timer Time-out Interval is 1638 LIRC clocks (51.2 ms) */ +#define CLK_PMUCTL_WKTMRIS_3277 (0x3UL << CLK_PMUCTL_WKTMRIS_Pos) /*!< Select Wake-up Timer Time-out Interval is 3277 LIRC clocks (102.4ms) */ +#define CLK_PMUCTL_WKTMRIS_13107 (0x4UL << CLK_PMUCTL_WKTMRIS_Pos) /*!< Select Wake-up Timer Time-out Interval is 13107 LIRC clocks (409.6ms) */ +#define CLK_PMUCTL_WKTMRIS_26214 (0x5UL << CLK_PMUCTL_WKTMRIS_Pos) /*!< Select Wake-up Timer Time-out Interval is 26214 LIRC clocks (819.2ms) */ +#define CLK_PMUCTL_WKTMRIS_52429 (0x6UL << CLK_PMUCTL_WKTMRIS_Pos) /*!< Select Wake-up Timer Time-out Interval is 52429 LIRC clocks (1638.4ms) */ +#define CLK_PMUCTL_WKTMRIS_209715 (0x7UL << CLK_PMUCTL_WKTMRIS_Pos) /*!< Select Wake-up Timer Time-out Interval is 209715 LIRC clocks (6553.6ms) */ + +/*---------------------------------------------------------------------------------------------------------*/ +/* SWKDBCLKSEL constant definitions. */ +/*---------------------------------------------------------------------------------------------------------*/ +#define CLK_SWKDBCTL_SWKDBCLKSEL_1 (0x0UL << CLK_SWKDBCTL_SWKDBCLKSEL_Pos) /*!< Select Standby Power-down Pin De-bounce Sampling Cycle is 1 clocks */ +#define CLK_SWKDBCTL_SWKDBCLKSEL_2 (0x1UL << CLK_SWKDBCTL_SWKDBCLKSEL_Pos) /*!< Select Standby Power-down Pin De-bounce Sampling Cycle is 2 clocks */ +#define CLK_SWKDBCTL_SWKDBCLKSEL_4 (0x2UL << CLK_SWKDBCTL_SWKDBCLKSEL_Pos) /*!< Select Standby Power-down Pin De-bounce Sampling Cycle is 4 clocks */ +#define CLK_SWKDBCTL_SWKDBCLKSEL_8 (0x3UL << CLK_SWKDBCTL_SWKDBCLKSEL_Pos) /*!< Select Standby Power-down Pin De-bounce Sampling Cycle is 8 clocks */ +#define CLK_SWKDBCTL_SWKDBCLKSEL_16 (0x4UL << CLK_SWKDBCTL_SWKDBCLKSEL_Pos) /*!< Select Standby Power-down Pin De-bounce Sampling Cycle is 16 clocks */ +#define CLK_SWKDBCTL_SWKDBCLKSEL_32 (0x5UL << CLK_SWKDBCTL_SWKDBCLKSEL_Pos) /*!< Select Standby Power-down Pin De-bounce Sampling Cycle is 32 clocks */ +#define CLK_SWKDBCTL_SWKDBCLKSEL_64 (0x6UL << CLK_SWKDBCTL_SWKDBCLKSEL_Pos) /*!< Select Standby Power-down Pin De-bounce Sampling Cycle is 64 clocks */ +#define CLK_SWKDBCTL_SWKDBCLKSEL_128 (0x7UL << CLK_SWKDBCTL_SWKDBCLKSEL_Pos) /*!< Select Standby Power-down Pin De-bounce Sampling Cycle is 128 clocks */ +#define CLK_SWKDBCTL_SWKDBCLKSEL_256 (0x8UL << CLK_SWKDBCTL_SWKDBCLKSEL_Pos) /*!< Select Standby Power-down Pin De-bounce Sampling Cycle is 256 clocks */ +#define CLK_SWKDBCTL_SWKDBCLKSEL_2x256 (0x9UL << CLK_SWKDBCTL_SWKDBCLKSEL_Pos) /*!< Select Standby Power-down Pin De-bounce Sampling Cycle is 2x256 clocks */ +#define CLK_SWKDBCTL_SWKDBCLKSEL_4x256 (0xaUL << CLK_SWKDBCTL_SWKDBCLKSEL_Pos) /*!< Select Standby Power-down Pin De-bounce Sampling Cycle is 4x256 clocks */ +#define CLK_SWKDBCTL_SWKDBCLKSEL_8x256 (0xbUL << CLK_SWKDBCTL_SWKDBCLKSEL_Pos) /*!< Select Standby Power-down Pin De-bounce Sampling Cycle is 8x256 clocks */ +#define CLK_SWKDBCTL_SWKDBCLKSEL_16x256 (0xcUL << CLK_SWKDBCTL_SWKDBCLKSEL_Pos) /*!< Select Standby Power-down Pin De-bounce Sampling Cycle is 16x256 clocks */ +#define CLK_SWKDBCTL_SWKDBCLKSEL_32x256 (0xdUL << CLK_SWKDBCTL_SWKDBCLKSEL_Pos) /*!< Select Standby Power-down Pin De-bounce Sampling Cycle is 32x256 clocks */ +#define CLK_SWKDBCTL_SWKDBCLKSEL_64x256 (0xeUL << CLK_SWKDBCTL_SWKDBCLKSEL_Pos) /*!< Select Standby Power-down Pin De-bounce Sampling Cycle is 64x256 clocks */ +#define CLK_SWKDBCTL_SWKDBCLKSEL_128x256 (0xfUL << CLK_SWKDBCTL_SWKDBCLKSEL_Pos) /*!< Select Standby Power-down Pin De-bounce Sampling Cycle is 128x256 clocks */ + +/*---------------------------------------------------------------------------------------------------------*/ +/* DPD Pin Rising/Falling Edge Wake-up Enable constant definitions. */ +/*---------------------------------------------------------------------------------------------------------*/ +#define CLK_DPDWKPIN_DISABLE (0x0UL << CLK_PMUCTL_WKPINEN_Pos) /*!< Disable Wake-up pin (GPC.0) at Deep Power-down mode \hideinitializer */ +#define CLK_DPDWKPIN_RISING (0x1UL << CLK_PMUCTL_WKPINEN_Pos) /*!< Enable Wake-up pin (GPC.0) rising edge at Deep Power-down mode \hideinitializer */ +#define CLK_DPDWKPIN_FALLING (0x2UL << CLK_PMUCTL_WKPINEN_Pos) /*!< Enable Wake-up pin (GPC.0) falling edge at Deep Power-down mode \hideinitializer */ +#define CLK_DPDWKPIN_BOTHEDGE (0x3UL << CLK_PMUCTL_WKPINEN_Pos) /*!< Enable Wake-up pin (GPC.0) both edge at Deep Power-down mode \hideinitializer */ + +#define CLK_DPDWKPIN0_DISABLE (0x0UL << CLK_PMUCTL_WKPINEN_Pos) /*!< Disable Wake-up pin0 (GPC.0) at Deep Power-down mode \hideinitializer */ +#define CLK_DPDWKPIN0_RISING (0x1UL << CLK_PMUCTL_WKPINEN_Pos) /*!< Enable Wake-up pin0 (GPC.0) rising edge at Deep Power-down mode \hideinitializer */ +#define CLK_DPDWKPIN0_FALLING (0x2UL << CLK_PMUCTL_WKPINEN_Pos) /*!< Enable Wake-up pin0 (GPC.0) falling edge at Deep Power-down mode \hideinitializer */ +#define CLK_DPDWKPIN0_BOTHEDGE (0x3UL << CLK_PMUCTL_WKPINEN_Pos) /*!< Enable Wake-up pin0 (GPC.0) both edge at Deep Power-down mode \hideinitializer */ + +#define CLK_DPDWKPIN1_DISABLE (0x0UL << CLK_PMUCTL_WKPINEN1_Pos) /*!< Disable Wake-up pin1 (GPB.0) at Deep Power-down mode \hideinitializer */ +#define CLK_DPDWKPIN1_RISING (0x1UL << CLK_PMUCTL_WKPINEN1_Pos) /*!< Enable Wake-up pin1 (GPB.0) rising edge at Deep Power-down mode \hideinitializer */ +#define CLK_DPDWKPIN1_FALLING (0x2UL << CLK_PMUCTL_WKPINEN1_Pos) /*!< Enable Wake-up pin1 (GPB.0) falling edge at Deep Power-down mode \hideinitializer */ +#define CLK_DPDWKPIN1_BOTHEDGE (0x3UL << CLK_PMUCTL_WKPINEN1_Pos) /*!< Enable Wake-up pin1 (GPB.0) both edge at Deep Power-down mode \hideinitializer */ + +#define CLK_DPDWKPIN2_DISABLE (0x0UL << CLK_PMUCTL_WKPINEN2_Pos) /*!< Disable Wake-up pin2 (GPB.2) at Deep Power-down mode \hideinitializer */ +#define CLK_DPDWKPIN2_RISING (0x1UL << CLK_PMUCTL_WKPINEN2_Pos) /*!< Enable Wake-up pin2 (GPB.2) rising edge at Deep Power-down mode \hideinitializer */ +#define CLK_DPDWKPIN2_FALLING (0x2UL << CLK_PMUCTL_WKPINEN2_Pos) /*!< Enable Wake-up pin2 (GPB.2) falling edge at Deep Power-down mode \hideinitializer */ +#define CLK_DPDWKPIN2_BOTHEDGE (0x3UL << CLK_PMUCTL_WKPINEN2_Pos) /*!< Enable Wake-up pin2 (GPB.2) both edge at Deep Power-down mode \hideinitializer */ + +#define CLK_DPDWKPIN3_DISABLE (0x0UL << CLK_PMUCTL_WKPINEN3_Pos) /*!< Disable Wake-up pin3 (GPB.12) at Deep Power-down mode \hideinitializer */ +#define CLK_DPDWKPIN3_RISING (0x1UL << CLK_PMUCTL_WKPINEN3_Pos) /*!< Enable Wake-up pin3 (GPB.12) rising edge at Deep Power-down mode \hideinitializer */ +#define CLK_DPDWKPIN3_FALLING (0x2UL << CLK_PMUCTL_WKPINEN3_Pos) /*!< Enable Wake-up pin3 (GPB.12) falling edge at Deep Power-down mode \hideinitializer */ +#define CLK_DPDWKPIN3_BOTHEDGE (0x3UL << CLK_PMUCTL_WKPINEN3_Pos) /*!< Enable Wake-up pin3 (GPB.12) both edge at Deep Power-down mode \hideinitializer */ + +#define CLK_DPDWKPIN4_DISABLE (0x0UL << CLK_PMUCTL_WKPINEN4_Pos) /*!< Disable Wake-up pin4 (GPF.6) at Deep Power-down mode \hideinitializer */ +#define CLK_DPDWKPIN4_RISING (0x1UL << CLK_PMUCTL_WKPINEN4_Pos) /*!< Enable Wake-up pin4 (GPF.6) rising edge at Deep Power-down mode \hideinitializer */ +#define CLK_DPDWKPIN4_FALLING (0x2UL << CLK_PMUCTL_WKPINEN4_Pos) /*!< Enable Wake-up pin4 (GPF.6) falling edge at Deep Power-down mode \hideinitializer */ +#define CLK_DPDWKPIN4_BOTHEDGE (0x3UL << CLK_PMUCTL_WKPINEN4_Pos) /*!< Enable Wake-up pin4 (GPF.6) both edge at Deep Power-down mode \hideinitializer */ + +/*---------------------------------------------------------------------------------------------------------*/ +/* SPD Pin Rising/Falling Edge Wake-up Enable constant definitions. */ +/*---------------------------------------------------------------------------------------------------------*/ +#define CLK_SPDWKPIN_ENABLE (0x1UL << 0) /*!< Enable Standby Power-down Pin Wake-up */ +#define CLK_SPDWKPIN_RISING (0x1UL << 1) /*!< Standby Power-down Wake-up on Standby Power-down Pin rising edge */ +#define CLK_SPDWKPIN_FALLING (0x1UL << 2) /*!< Standby Power-down Wake-up on Standby Power-down Pin falling edge */ +#define CLK_SPDWKPIN_DEBOUNCEEN (0x1UL << 8) /*!< Enable Standby power-down pin De-bounce function */ +#define CLK_SPDWKPIN_DEBOUNCEDIS (0x0UL << 8) /*!< Disable Standby power-down pin De-bounce function */ + + +/**@}*/ /* end of group CLK_EXPORTED_CONSTANTS */ + +/** @addtogroup CLK_EXPORTED_FUNCTIONS CLK Exported Functions + @{ +*/ + +/** + * @brief Disable Wake-up Timer + * @param None + * @return None + * @details This macro disables Wake-up timer at Standby or Deep Power-down mode. + */ +#define CLK_DISABLE_WKTMR() \ + do{ \ + while(CLK->PMUCTL & CLK_PMUCTL_WRBUSY_Msk); \ + CLK->PMUCTL &= ~CLK_PMUCTL_WKTMREN_Msk; \ + }while(0) + +/** + * @brief Enable Wake-up Timer + * @param None + * @return None + * @details This macro enables Wake-up timer at Standby or Deep Power-down mode. + */ +#define CLK_ENABLE_WKTMR() \ + do{ \ + while(CLK->PMUCTL & CLK_PMUCTL_WRBUSY_Msk); \ + CLK->PMUCTL |= CLK_PMUCTL_WKTMREN_Msk; \ + }while(0) + +/** + * @brief Disable DPD Mode Wake-up Pin + * @param None + * @return None + * @details This macro disables Wake-up pin at Deep Power-down mode. + */ +#define CLK_DISABLE_DPDWKPIN() \ + do{ \ + while(CLK->PMUCTL & CLK_PMUCTL_WRBUSY_Msk); \ + CLK->PMUCTL &= ~CLK_PMUCTL_WKPINEN_Msk; \ + }while(0) + +/** + * @brief Disable DPD Mode Wake-up Pin 0 + * @param None + * @return None + * @details This macro disables Wake-up pin 0 (GPC.0) at Deep Power-down mode. + */ +#define CLK_DISABLE_DPDWKPIN0() \ + do{ \ + while(CLK->PMUCTL & CLK_PMUCTL_WRBUSY_Msk); \ + CLK->PMUCTL &= ~CLK_PMUCTL_WKPIN0EN_Msk; \ + }while(0) + +/** + * @brief Disable DPD Mode Wake-up Pin 1 + * @param None + * @return None + * @details This macro disables Wake-up pin 1 (GPB.0) at Deep Power-down mode. + */ +#define CLK_DISABLE_DPDWKPIN1() \ + do{ \ + while(CLK->PMUCTL & CLK_PMUCTL_WRBUSY_Msk); \ + CLK->PMUCTL &= ~CLK_PMUCTL_WKPIN1EN_Msk; \ + }while(0) + +/** + * @brief Disable DPD Mode Wake-up Pin 2 + * @param None + * @return None + * @details This macro disables Wake-up pin 2 (GPB.2) at Deep Power-down mode. + */ +#define CLK_DISABLE_DPDWKPIN2() \ + do{ \ + while(CLK->PMUCTL & CLK_PMUCTL_WRBUSY_Msk); \ + CLK->PMUCTL &= ~CLK_PMUCTL_WKPIN2EN_Msk; \ + }while(0) + +/** + * @brief Disable DPD Mode Wake-up Pin 3 + * @param None + * @return None + * @details This macro disables Wake-up pin 3 (GPB.12) at Deep Power-down mode. + */ +#define CLK_DISABLE_DPDWKPIN3() \ + do{ \ + while(CLK->PMUCTL & CLK_PMUCTL_WRBUSY_Msk); \ + CLK->PMUCTL &= ~CLK_PMUCTL_WKPIN3EN_Msk; \ + }while(0) + +/** + * @brief Disable DPD Mode Wake-up Pin 4 + * @param None + * @return None + * @details This macro disables Wake-up pin 4 (GPF.6) at Deep Power-down mode. + */ +#define CLK_DISABLE_DPDWKPIN4() \ + do{ \ + while(CLK->PMUCTL & CLK_PMUCTL_WRBUSY_Msk); \ + CLK->PMUCTL &= ~CLK_PMUCTL_WKPIN4EN_Msk; \ + }while(0) + +/** + * @brief Disable SPD Mode ACMP Wake-up + * @param None + * @return None + * @details This macro disables ACMP wake-up at Standby Power-down mode. + */ +#define CLK_DISABLE_SPDACMP() \ + do{ \ + while(CLK->PMUCTL & CLK_PMUCTL_WRBUSY_Msk); \ + CLK->PMUCTL &= ~CLK_PMUCTL_ACMPSPWK_Msk; \ + }while(0) + +/** + * @brief Enable SPD Mode ACMP Wake-up + * @param None + * @return None + * @details This macro enables ACMP wake-up at Standby Power-down mode. + */ +#define CLK_ENABLE_SPDACMP() \ + do{ \ + while(CLK->PMUCTL & CLK_PMUCTL_WRBUSY_Msk); \ + CLK->PMUCTL |= CLK_PMUCTL_ACMPSPWK_Msk; \ + }while(0) + +/** + * @brief Disable SPD and DPD Mode RTC Wake-up + * @param None + * @return None + * @details This macro disables RTC Wake-up at Standby or Deep Power-down mode. + */ +#define CLK_DISABLE_RTCWK() \ + do{ \ + while(CLK->PMUCTL & CLK_PMUCTL_WRBUSY_Msk); \ + CLK->PMUCTL &= ~CLK_PMUCTL_RTCWKEN_Msk; \ + }while(0) + +/** + * @brief Enable SPD and DPD Mode RTC Wake-up + * @param None + * @return None + * @details This macro enables RTC Wake-up at Standby or Deep Power-down mode. + */ +#define CLK_ENABLE_RTCWK() \ + do{ \ + while(CLK->PMUCTL & CLK_PMUCTL_WRBUSY_Msk); \ + CLK->PMUCTL |= CLK_PMUCTL_RTCWKEN_Msk; \ + }while(0) + +/** + * @brief Set Wake-up Timer Time-out Interval + * + * @param[in] u32Interval The Wake-up Timer Time-out Interval selection. It could be + * - \ref CLK_PMUCTL_WKTMRIS_410 + * - \ref CLK_PMUCTL_WKTMRIS_819 + * - \ref CLK_PMUCTL_WKTMRIS_1638 + * - \ref CLK_PMUCTL_WKTMRIS_3277 + * - \ref CLK_PMUCTL_WKTMRIS_13107 + * - \ref CLK_PMUCTL_WKTMRIS_26214 + * - \ref CLK_PMUCTL_WKTMRIS_52429 + * - \ref CLK_PMUCTL_WKTMRIS_209715 + * + * @return None + * + * @details This function set Wake-up Timer Time-out Interval. + * + * + */ +#define CLK_SET_WKTMR_INTERVAL(u32Interval) \ + do{ \ + while(CLK->PMUCTL & CLK_PMUCTL_WRBUSY_Msk); \ + CLK->PMUCTL = (CLK->PMUCTL & (~CLK_PMUCTL_WKTMRIS_Msk)) | (u32Interval); \ + }while(0) + +/** + * @brief Set De-bounce Sampling Cycle Time + * + * @param[in] u32CycleSel The de-bounce sampling cycle selection. It could be + * - \ref CLK_SWKDBCTL_SWKDBCLKSEL_1 + * - \ref CLK_SWKDBCTL_SWKDBCLKSEL_2 + * - \ref CLK_SWKDBCTL_SWKDBCLKSEL_4 + * - \ref CLK_SWKDBCTL_SWKDBCLKSEL_8 + * - \ref CLK_SWKDBCTL_SWKDBCLKSEL_16 + * - \ref CLK_SWKDBCTL_SWKDBCLKSEL_32 + * - \ref CLK_SWKDBCTL_SWKDBCLKSEL_64 + * - \ref CLK_SWKDBCTL_SWKDBCLKSEL_128 + * - \ref CLK_SWKDBCTL_SWKDBCLKSEL_256 + * - \ref CLK_SWKDBCTL_SWKDBCLKSEL_2x256 + * - \ref CLK_SWKDBCTL_SWKDBCLKSEL_4x256 + * - \ref CLK_SWKDBCTL_SWKDBCLKSEL_8x256 + * - \ref CLK_SWKDBCTL_SWKDBCLKSEL_16x256 + * - \ref CLK_SWKDBCTL_SWKDBCLKSEL_32x256 + * - \ref CLK_SWKDBCTL_SWKDBCLKSEL_64x256 + * - \ref CLK_SWKDBCTL_SWKDBCLKSEL_128x256 + * + * @return None + * + * @details This function set Set De-bounce Sampling Cycle Time for Standby Power-down pin wake-up. + * + * + */ +#define CLK_SET_SPDDEBOUNCETIME(u32CycleSel) (CLK->SWKDBCTL = (u32CycleSel)) + +/** + * @brief Disable SPD Mode Tamper Wake-up + * @param None + * @return None + * @details This macro disables tamper Wake-up at Standby Power-down mode. + */ +#define CLK_DISABLE_SPDTAMPER() \ + do{ \ + while(CLK->PMUCTL & CLK_PMUCTL_WRBUSY_Msk); \ + CLK->PMUCTL &= ~CLK_PMUCTL_TAMPERWK_Msk; \ + }while(0) + +/** + * @brief Enable SPD and DPD Mode RTC Wake-up + * @param None + * @return None + * @details This macro enables tamper Wake-up at Standby Power-down mode. + */ +#define CLK_ENABLE_SPDTAMPER() \ + do{ \ + while(CLK->PMUCTL & CLK_PMUCTL_WRBUSY_Msk); \ + CLK->PMUCTL |= CLK_PMUCTL_TAMPERWK_Msk; \ + }while(0) + + +/*---------------------------------------------------------------------------------------------------------*/ +/* static inline functions */ +/*---------------------------------------------------------------------------------------------------------*/ +/* Declare these inline functions here to avoid MISRA C 2004 rule 8.1 error */ +__STATIC_INLINE void CLK_SysTickDelay(uint32_t us); +__STATIC_INLINE void CLK_SysTickLongDelay(uint32_t us); + + +/** + * @brief This function execute delay function. + * @param[in] us Delay time. The Max value is (2^24-1) / CPU Clock(MHz). Ex: + * 96MHz => 174762us, 84MHz => 199728us, + * 64MHz => 262143us, 48MHz => 349525us ... + * @return None + * @details Use the SysTick to generate the delay time and the UNIT is in us. + * The SysTick clock source is from HCLK, i.e the same as system core clock. + * User can use SystemCoreClockUpdate() to calculate CyclesPerUs automatically before using this function. + */ +__STATIC_INLINE void CLK_SysTickDelay(uint32_t us) +{ + SysTick->LOAD = us * CyclesPerUs; + SysTick->VAL = (0x0UL); + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | SysTick_CTRL_ENABLE_Msk; + + /* Waiting for down-count to zero */ + while((SysTick->CTRL & SysTick_CTRL_COUNTFLAG_Msk) == 0UL) + { + } + + /* Disable SysTick counter */ + SysTick->CTRL = 0UL; +} + +/** + * @brief This function execute long delay function. + * @param[in] us Delay time. + * @return None + * @details Use the SysTick to generate the long delay time and the UNIT is in us. + * The SysTick clock source is from HCLK, i.e the same as system core clock. + * User can use SystemCoreClockUpdate() to calculate CyclesPerUs automatically before using this function. + */ +__STATIC_INLINE void CLK_SysTickLongDelay(uint32_t us) +{ + uint32_t u32Delay; + + /* It should <= 65536us for each delay loop */ + u32Delay = 65536UL; + + do + { + if(us > u32Delay) + { + us -= u32Delay; + } + else + { + u32Delay = us; + us = 0UL; + } + + SysTick->LOAD = u32Delay * CyclesPerUs; + SysTick->VAL = (0x0UL); + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | SysTick_CTRL_ENABLE_Msk; + + /* Waiting for down-count to zero */ + while((SysTick->CTRL & SysTick_CTRL_COUNTFLAG_Msk) == 0UL); + + /* Disable SysTick counter */ + SysTick->CTRL = 0UL; + + } + while(us > 0UL); + +} + + +void CLK_DisableCKO(void); +void CLK_EnableCKO(uint32_t u32ClkSrc, uint32_t u32ClkDiv, uint32_t u32ClkDivBy1En); +void CLK_PowerDown(void); +void CLK_Idle(void); +uint32_t CLK_GetHXTFreq(void); +uint32_t CLK_GetLXTFreq(void); +uint32_t CLK_GetHCLKFreq(void); +uint32_t CLK_GetPCLK0Freq(void); +uint32_t CLK_GetPCLK1Freq(void); +uint32_t CLK_GetCPUFreq(void); +uint32_t CLK_SetCoreClock(uint32_t u32Hclk); +void CLK_SetHCLK(uint32_t u32ClkSrc, uint32_t u32ClkDiv); +void CLK_SetModuleClock(uint32_t u32ModuleIdx, uint32_t u32ClkSrc, uint32_t u32ClkDiv); +void CLK_SetSysTickClockSrc(uint32_t u32ClkSrc); +void CLK_EnableXtalRC(uint32_t u32ClkMask); +void CLK_DisableXtalRC(uint32_t u32ClkMask); +void CLK_EnableModuleClock(uint32_t u32ModuleIdx); +void CLK_DisableModuleClock(uint32_t u32ModuleIdx); +uint32_t CLK_EnablePLL(uint32_t u32PllClkSrc, uint32_t u32PllFreq); +void CLK_DisablePLL(void); +uint32_t CLK_WaitClockReady(uint32_t u32ClkMask); +void CLK_EnableSysTick(uint32_t u32ClkSrc, uint32_t u32Count); +void CLK_DisableSysTick(void); +void CLK_SetPowerDownMode(uint32_t u32PDMode); +void CLK_EnableDPDWKPin(uint32_t u32TriggerType); +uint32_t CLK_GetPMUWKSrc(void); +void CLK_EnableSPDWKPin(uint32_t u32Port, uint32_t u32Pin, uint32_t u32TriggerType, uint32_t u32DebounceEn); +uint32_t CLK_GetPLLClockFreq(void); +uint32_t CLK_GetModuleClockSource(uint32_t u32ModuleIdx); +uint32_t CLK_GetModuleClockDivider(uint32_t u32ModuleIdx); + + +/**@}*/ /* end of group CLK_EXPORTED_FUNCTIONS */ + +/**@}*/ /* end of group CLK_Driver */ + +/**@}*/ /* end of group Standard_Driver */ + + +#ifdef __cplusplus +} +#endif + + +#endif /* __NU_CLK_H__ */ + diff --git a/Ubiquitous/XiZi/board/nuvoton-m2354/third_party_driver/include/Drivers/nu_crc.h b/Ubiquitous/XiZi/board/nuvoton-m2354/third_party_driver/include/Drivers/nu_crc.h new file mode 100644 index 0000000..7a00089 --- /dev/null +++ b/Ubiquitous/XiZi/board/nuvoton-m2354/third_party_driver/include/Drivers/nu_crc.h @@ -0,0 +1,115 @@ +/**************************************************************************//** + * @file nu_crc.h + * @version V3.00 + * @brief Cyclic Redundancy Check(CRC) driver header file + * + * @copyright SPDX-License-Identifier: Apache-2.0 + * @copyright Copyright (C) 2020 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ +#ifndef __NU_CRC_H__ +#define __NU_CRC_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup CRC_Driver CRC Driver + @{ +*/ + +/** @addtogroup CRC_EXPORTED_CONSTANTS CRC Exported Constants + @{ +*/ +/*---------------------------------------------------------------------------------------------------------*/ +/* CRC Polynomial Mode Constant Definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define CRC_CCITT (0UL << CRC_CTL_CRCMODE_Pos) /*!SEED = (u32Seed); (crc)->CTL |= CRC_CTL_CHKSINIT_Msk; } while(0) + +/** + * @brief Get CRC Seed Value + * + * @param[in] crc The pointer of CRC module. + * + * @return CRC seed value + * + * @details This macro gets the current CRC seed value. + * \hideinitializer + */ +#define CRC_GET_SEED(crc) ((crc)->SEED) + +/** + * @brief CRC Write Data + * + * @param[in] crc The pointer of CRC module. + * @param[in] u32Data Write data + * + * @return None + * + * @details User can write data directly to CRC Write Data Register(CRC_DAT) by this macro to perform CRC operation. + * \hideinitializer + */ +#define CRC_WRITE_DATA(crc, u32Data) ((crc)->DAT = (u32Data)) + + +void CRC_Open(uint32_t u32Mode, uint32_t u32Attribute, uint32_t u32Seed, uint32_t u32DataLen); +uint32_t CRC_GetChecksum(void); + +/**@}*/ /* end of group CRC_EXPORTED_FUNCTIONS */ + +/**@}*/ /* end of group CRC_Driver */ + +/**@}*/ /* end of group Standard_Driver */ + +#ifdef __cplusplus +} +#endif + +#endif /* __NU_CRC_H__ */ + diff --git a/Ubiquitous/XiZi/board/nuvoton-m2354/third_party_driver/include/Drivers/nu_crypto.h b/Ubiquitous/XiZi/board/nuvoton-m2354/third_party_driver/include/Drivers/nu_crypto.h new file mode 100644 index 0000000..eebd671 --- /dev/null +++ b/Ubiquitous/XiZi/board/nuvoton-m2354/third_party_driver/include/Drivers/nu_crypto.h @@ -0,0 +1,559 @@ +/**************************************************************************//** + * @file nu_crypto.h + * @version V3.00 + * @brief Cryptographic Accelerator driver header file + * + * @copyright SPDX-License-Identifier: Apache-2.0 + * @copyright Copyright (C) 2020 Nuvoton Technology Corp. All rights reserved. + ******************************************************************************/ +#ifndef __NU_CRYPTO_H__ +#define __NU_CRYPTO_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup CRYPTO_Driver CRYPTO Driver + @{ +*/ + + +/** @addtogroup CRYPTO_EXPORTED_CONSTANTS CRYPTO Exported Constants + @{ +*/ + + +#define PRNG_KEY_SIZE_128 ( 0UL) /*!< Select to generate 128-bit random key \hideinitializer */ +#define PRNG_KEY_SIZE_163 ( 1UL) /*!< Select to generate 163-bit random key \hideinitializer */ +#define PRNG_KEY_SIZE_192 ( 2UL) /*!< Select to generate 192-bit random key \hideinitializer */ +#define PRNG_KEY_SIZE_224 ( 3UL) /*!< Select to generate 224-bit random key \hideinitializer */ +#define PRNG_KEY_SIZE_255 ( 4UL) /*!< Select to generate 255-bit random key \hideinitializer */ +#define PRNG_KEY_SIZE_256 ( 6UL) /*!< Select to generate 256-bit random key \hideinitializer */ +#define PRNG_KEY_SIZE_283 ( 7UL) /*!< Select to generate 283-bit random key (Key Store Only) \hideinitializer */ +#define PRNG_KEY_SIZE_384 ( 8UL) /*!< Select to generate 384-bit random key (Key Store Only) \hideinitializer */ +#define PRNG_KEY_SIZE_409 ( 9UL) /*!< Select to generate 409-bit random key (Key Store Only) \hideinitializer */ +#define PRNG_KEY_SIZE_512 (10UL) /*!< Select to generate 512-bit random key (Key Store Only) \hideinitializer */ +#define PRNG_KEY_SIZE_521 (11UL) /*!< Select to generate 521-bit random key (Key Store Only) \hideinitializer */ +#define PRNG_KEY_SIZE_571 (12UL) /*!< Select to generate 571-bit random key (Key Store Only) \hideinitializer */ + +#define PRNG_SEED_CONT (0UL) /*!< PRNG using current seed \hideinitializer */ +#define PRNG_SEED_RELOAD (1UL) /*!< PRNG reload new seed \hideinitializer */ + +#define AES_KEY_SIZE_128 (0UL) /*!< AES select 128-bit key length \hideinitializer */ +#define AES_KEY_SIZE_192 (1UL) /*!< AES select 192-bit key length \hideinitializer */ +#define AES_KEY_SIZE_256 (2UL) /*!< AES select 256-bit key length \hideinitializer */ + +#define AES_MODE_ECB (0UL) /*!< AES select ECB mode \hideinitializer */ +#define AES_MODE_CBC (1UL) /*!< AES select CBC mode \hideinitializer */ +#define AES_MODE_CFB (2UL) /*!< AES select CFB mode \hideinitializer */ +#define AES_MODE_OFB (3UL) /*!< AES select OFB mode \hideinitializer */ +#define AES_MODE_CTR (4UL) /*!< AES select CTR mode \hideinitializer */ +#define AES_MODE_CBC_CS1 (0x10UL) /*!< AES select CBC CS1 mode \hideinitializer */ +#define AES_MODE_CBC_CS2 (0x11UL) /*!< AES select CBC CS2 mode \hideinitializer */ +#define AES_MODE_CBC_CS3 (0x12UL) /*!< AES select CBC CS3 mode \hideinitializer */ +#define AES_MODE_GCM (0x20UL) +#define AES_MODE_GHASH (0x21UL) +#define AES_MODE_CCM (0x22UL) + +#define SM4_MODE_ECB (0x200UL) /*!< SM4 select ECB mode \hideinitializer */ +#define SM4_MODE_CBC (0x201UL) /*!< SM4 select CBC mode \hideinitializer */ +#define SM4_MODE_CFB (0x202UL) /*!< SM4 select CFB mode \hideinitializer */ +#define SM4_MODE_OFB (0x203UL) /*!< SM4 select OFB mode \hideinitializer */ +#define SM4_MODE_CTR (0x204UL) /*!< SM4 select CTR mode \hideinitializer */ +#define SM4_MODE_CBC_CS1 (0x210UL) /*!< SM4 select CBC CS1 mode \hideinitializer */ +#define SM4_MODE_CBC_CS2 (0x211UL) /*!< SM4 select CBC CS2 mode \hideinitializer */ +#define SM4_MODE_CBC_CS3 (0x212UL) /*!< SM4 select CBC CS3 mode \hideinitializer */ +#define SM4_MODE_GCM (0x220UL) +#define SM4_MODE_GHASH (0x221UL) +#define SM4_MODE_CCM (0x222UL) + + +#define AES_NO_SWAP (0UL) /*!< AES do not swap input and output data \hideinitializer */ +#define AES_OUT_SWAP (1UL) /*!< AES swap output data \hideinitializer */ +#define AES_IN_SWAP (2UL) /*!< AES swap input data \hideinitializer */ +#define AES_IN_OUT_SWAP (3UL) /*!< AES swap both input and output data \hideinitializer */ + +#define DES_MODE_ECB (0x000UL) /*!< DES select ECB mode \hideinitializer */ +#define DES_MODE_CBC (0x100UL) /*!< DES select CBC mode \hideinitializer */ +#define DES_MODE_CFB (0x200UL) /*!< DES select CFB mode \hideinitializer */ +#define DES_MODE_OFB (0x300UL) /*!< DES select OFB mode \hideinitializer */ +#define DES_MODE_CTR (0x400UL) /*!< DES select CTR mode \hideinitializer */ +#define TDES_MODE_ECB (0x004UL) /*!< TDES select ECB mode \hideinitializer */ +#define TDES_MODE_CBC (0x104UL) /*!< TDES select CBC mode \hideinitializer */ +#define TDES_MODE_CFB (0x204UL) /*!< TDES select CFB mode \hideinitializer */ +#define TDES_MODE_OFB (0x304UL) /*!< TDES select OFB mode \hideinitializer */ +#define TDES_MODE_CTR (0x404UL) /*!< TDES select CTR mode \hideinitializer */ + +#define TDES_NO_SWAP (0UL) /*!< TDES do not swap data \hideinitializer */ +#define TDES_WHL_SWAP (1UL) /*!< TDES swap high-low word \hideinitializer */ +#define TDES_OUT_SWAP (2UL) /*!< TDES swap output data \hideinitializer */ +#define TDES_OUT_WHL_SWAP (3UL) /*!< TDES swap output data and high-low word \hideinitializer */ +#define TDES_IN_SWAP (4UL) /*!< TDES swap input data \hideinitializer */ +#define TDES_IN_WHL_SWAP (5UL) /*!< TDES swap input data and high-low word \hideinitializer */ +#define TDES_IN_OUT_SWAP (6UL) /*!< TDES swap both input and output data \hideinitializer */ +#define TDES_IN_OUT_WHL_SWAP (7UL) /*!< TDES swap input, output and high-low word \hideinitializer */ + +#define SHA_MODE_SHA1 (0UL) /*!< SHA select SHA-1 160-bit \hideinitializer */ +#define SHA_MODE_SHA224 (5UL) /*!< SHA select SHA-224 224-bit \hideinitializer */ +#define SHA_MODE_SHA256 (4UL) /*!< SHA select SHA-256 256-bit \hideinitializer */ +#define SHA_MODE_SHA384 (7UL) /*!< SHA select SHA-384 384-bit \hideinitializer */ +#define SHA_MODE_SHA512 (6UL) /*!< SHA select SHA-512 512-bit \hideinitializer */ + +#define HMAC_MODE_SHA1 (8UL) /*!< HMAC select SHA-1 160-bit \hideinitializer */ +#define HMAC_MODE_SHA224 (13UL) /*!< HMAC select SHA-224 224-bit \hideinitializer */ +#define HMAC_MODE_SHA256 (12UL) /*!< HMAC select SHA-256 256-bit \hideinitializer */ +#define HMAC_MODE_SHA384 (15UL) /*!< HMAC select SHA-384 384-bit \hideinitializer */ +#define HMAC_MODE_SHA512 (14UL) /*!< HMAC select SHA-512 512-bit \hideinitializer */ + + +#define SHA_NO_SWAP (0UL) /*!< SHA do not swap input and output data \hideinitializer */ +#define SHA_OUT_SWAP (1UL) /*!< SHA swap output data \hideinitializer */ +#define SHA_IN_SWAP (2UL) /*!< SHA swap input data \hideinitializer */ +#define SHA_IN_OUT_SWAP (3UL) /*!< SHA swap both input and output data \hideinitializer */ + +#define CRYPTO_DMA_FIRST (0x4UL) /*!< Do first encrypt/decrypt in DMA cascade \hideinitializer */ +#define CRYPTO_DMA_ONE_SHOT (0x5UL) /*!< Do one shot encrypt/decrypt with DMA \hideinitializer */ +#define CRYPTO_DMA_CONTINUE (0x6UL) /*!< Do continuous encrypt/decrypt in DMA cascade \hideinitializer */ +#define CRYPTO_DMA_LAST (0x7UL) /*!< Do last encrypt/decrypt in DMA cascade \hideinitializer */ + +//--------------------------------------------------- + +#define RSA_MAX_KLEN (4096) +#define RSA_KBUF_HLEN (RSA_MAX_KLEN/4 + 8) +#define RSA_KBUF_BLEN (RSA_MAX_KLEN + 32) + +#define RSA_KEY_SIZE_1024 (0UL) /*!< RSA select 1024-bit key length \hideinitializer */ +#define RSA_KEY_SIZE_2048 (1UL) /*!< RSA select 2048-bit key length \hideinitializer */ +#define RSA_KEY_SIZE_3072 (2UL) /*!< RSA select 3072-bit key length \hideinitializer */ +#define RSA_KEY_SIZE_4096 (3UL) /*!< RSA select 4096-bit key length \hideinitializer */ + +#define RSA_MODE_NORMAL (0x000UL) /*!< RSA select normal mode \hideinitializer */ +#define RSA_MODE_CRT (0x004UL) /*!< RSA select CRT mode \hideinitializer */ +#define RSA_MODE_CRTBYPASS (0x00CUL) /*!< RSA select CRT bypass mode \hideinitializer */ +#define RSA_MODE_SCAP (0x100UL) /*!< RSA select SCAP mode \hideinitializer */ +#define RSA_MODE_CRT_SCAP (0x104UL) /*!< RSA select CRT SCAP mode \hideinitializer */ +#define RSA_MODE_CRTBYPASS_SCAP (0x10CUL) /*!< RSA select CRT bypass SCAP mode \hideinitializer */ + + +typedef enum +{ + /*!< ECC curve \hideinitializer */ + CURVE_P_192, /*!< ECC curve P-192 \hideinitializer */ + CURVE_P_224, /*!< ECC curve P-224 \hideinitializer */ + CURVE_P_256, /*!< ECC curve P-256 \hideinitializer */ + CURVE_P_384, /*!< ECC curve P-384 \hideinitializer */ + CURVE_P_521, /*!< ECC curve P-521 \hideinitializer */ + CURVE_K_163, /*!< ECC curve K-163 \hideinitializer */ + CURVE_K_233, /*!< ECC curve K-233 \hideinitializer */ + CURVE_K_283, /*!< ECC curve K-283 \hideinitializer */ + CURVE_K_409, /*!< ECC curve K-409 \hideinitializer */ + CURVE_K_571, /*!< ECC curve K-571 \hideinitializer */ + CURVE_B_163, /*!< ECC curve B-163 \hideinitializer */ + CURVE_B_233, /*!< ECC curve B-233 \hideinitializer */ + CURVE_B_283, /*!< ECC curve B-283 \hideinitializer */ + CURVE_B_409, /*!< ECC curve B-409 \hideinitializer */ + CURVE_B_571, /*!< ECC curve K-571 \hideinitializer */ + CURVE_KO_192, /*!< ECC 192-bits "Koblitz" curve \hideinitializer */ + CURVE_KO_224, /*!< ECC 224-bits "Koblitz" curve \hideinitializer */ + CURVE_KO_256, /*!< ECC 256-bits "Koblitz" curve \hideinitializer */ + CURVE_BP_256, /*!< ECC Brainpool 256-bits curve \hideinitializer */ + CURVE_BP_384, /*!< ECC Brainpool 256-bits curve \hideinitializer */ + CURVE_BP_512, /*!< ECC Brainpool 256-bits curve \hideinitializer */ + CURVE_25519, /*!< ECC curve-25519 \hideinitializer */ + CURVE_SM2_256, /*!< SM2 \hideinitializer */ + CURVE_UNDEF = -0x7fffffff, /*!< Invalid curve \hideinitializer */ +} +E_ECC_CURVE; + + + +typedef struct e_curve_t +{ + E_ECC_CURVE curve_id; + int32_t Echar; + char Ea[144]; + char Eb[144]; + char Px[144]; + char Py[144]; + int32_t Epl; + char Pp[176]; + int32_t Eol; + char Eorder[176]; + int32_t key_len; + int32_t irreducible_k1; + int32_t irreducible_k2; + int32_t irreducible_k3; + int32_t GF; +} ECC_CURVE; + + +/* RSA working buffer for normal mode */ +typedef struct +{ + uint32_t au32RsaOutput[128]; /* The RSA answer. */ + uint32_t au32RsaN[128]; /* The base of modulus operation word. */ + uint32_t au32RsaM[128]; /* The base of exponentiation words. */ + uint32_t au32RsaE[128]; /* The exponent of exponentiation words. */ +} RSA_BUF_NORMAL_T; + +/* RSA working buffer for CRT ( + CRT bypass) mode */ +typedef struct +{ + uint32_t au32RsaOutput[128]; /* The RSA answer. */ + uint32_t au32RsaN[128]; /* The base of modulus operation word. */ + uint32_t au32RsaM[128]; /* The base of exponentiation words. */ + uint32_t au32RsaE[128]; /* The exponent of exponentiation words. */ + uint32_t au32RsaP[128]; /* The Factor of Modulus Operation. */ + uint32_t au32RsaQ[128]; /* The Factor of Modulus Operation. */ + uint32_t au32RsaTmpCp[128]; /* The Temporary Value(Cp) of RSA CRT. */ + uint32_t au32RsaTmpCq[128]; /* The Temporary Value(Cq) of RSA CRT. */ + uint32_t au32RsaTmpDp[128]; /* The Temporary Value(Dp) of RSA CRT. */ + uint32_t au32RsaTmpDq[128]; /* The Temporary Value(Dq) of RSA CRT. */ + uint32_t au32RsaTmpRp[128]; /* The Temporary Value(Rp) of RSA CRT. */ + uint32_t au32RsaTmpRq[128]; /* The Temporary Value(Rq) of RSA CRT. */ +} RSA_BUF_CRT_T; + +/* RSA working buffer for SCAP mode */ +typedef struct +{ + uint32_t au32RsaOutput[128]; /* The RSA answer. */ + uint32_t au32RsaN[128]; /* The base of modulus operation word. */ + uint32_t au32RsaM[128]; /* The base of exponentiation words. */ + uint32_t au32RsaE[128]; /* The exponent of exponentiation words. */ + uint32_t au32RsaP[128]; /* The Factor of Modulus Operation. */ + uint32_t au32RsaQ[128]; /* The Factor of Modulus Operation. */ + uint32_t au32RsaTmpBlindKey[128]; /* The Temporary Value(blind key) of RSA SCAP. */ +} RSA_BUF_SCAP_T; + +/* RSA working buffer for CRT ( + CRT bypass ) + SCAP mode */ +typedef struct +{ + uint32_t au32RsaOutput[128]; /* The RSA answer. */ + uint32_t au32RsaN[128]; /* The base of modulus operation word. */ + uint32_t au32RsaM[128]; /* The base of exponentiation words. */ + uint32_t au32RsaE[128]; /* The exponent of exponentiation words. */ + uint32_t au32RsaP[128]; /* The Factor of Modulus Operation. */ + uint32_t au32RsaQ[128]; /* The Factor of Modulus Operation. */ + uint32_t au32RsaTmpCp[128]; /* The Temporary Value(Cp) of RSA CRT. */ + uint32_t au32RsaTmpCq[128]; /* The Temporary Value(Cq) of RSA CRT. */ + uint32_t au32RsaTmpDp[128]; /* The Temporary Value(Dp) of RSA CRT. */ + uint32_t au32RsaTmpDq[128]; /* The Temporary Value(Dq) of RSA CRT. */ + uint32_t au32RsaTmpRp[128]; /* The Temporary Value(Rp) of RSA CRT. */ + uint32_t au32RsaTmpRq[128]; /* The Temporary Value(Rq) of RSA CRT. */ + uint32_t au32RsaTmpBlindKey[128]; /* The Temporary Value(blind key) of RSA SCAP. */ +} RSA_BUF_CRT_SCAP_T; + +/* RSA working buffer for using key store */ +typedef struct +{ + uint32_t au32RsaOutput[128]; /* The RSA answer. */ + uint32_t au32RsaN[128]; /* The base of modulus operation word. */ + uint32_t au32RsaM[128]; /* The base of exponentiation words. */ +} RSA_BUF_KS_T; + +/**@}*/ /* end of group CRYPTO_EXPORTED_CONSTANTS */ + + +/** @addtogroup CRYPTO_EXPORTED_MACROS CRYPTO Exported Macros + @{ +*/ + +/*----------------------------------------------------------------------------------------------*/ +/* Macros */ +/*----------------------------------------------------------------------------------------------*/ + +/** + * @brief This macro enables PRNG interrupt. + * @param crpt Specified crypto module + * @return None + * \hideinitializer + */ +#define PRNG_ENABLE_INT(crpt) ((crpt)->INTEN |= CRPT_INTEN_PRNGIEN_Msk) + +/** + * @brief This macro disables PRNG interrupt. + * @param crpt Specified crypto module + * @return None + * \hideinitializer + */ +#define PRNG_DISABLE_INT(crpt) ((crpt)->INTEN &= ~CRPT_INTEN_PRNGIEN_Msk) + +/** + * @brief This macro gets PRNG interrupt flag. + * @param crpt Specified crypto module + * @return PRNG interrupt flag. + * \hideinitializer + */ +#define PRNG_GET_INT_FLAG(crpt) ((crpt)->INTSTS & CRPT_INTSTS_PRNGIF_Msk) + +/** + * @brief This macro clears PRNG interrupt flag. + * @param crpt Specified crypto module + * @return None + * \hideinitializer + */ +#define PRNG_CLR_INT_FLAG(crpt) ((crpt)->INTSTS = CRPT_INTSTS_PRNGIF_Msk) + +/** + * @brief This macro enables AES interrupt. + * @param crpt Specified crypto module + * @return None + * \hideinitializer + */ +#define AES_ENABLE_INT(crpt) ((crpt)->INTEN |= (CRPT_INTEN_AESIEN_Msk|CRPT_INTEN_AESEIEN_Msk)) + +/** + * @brief This macro disables AES interrupt. + * @param crpt Specified crypto module + * @return None + * \hideinitializer + */ +#define AES_DISABLE_INT(crpt) ((crpt)->INTEN &= ~(CRPT_INTEN_AESIEN_Msk|CRPT_INTEN_AESEIEN_Msk)) + +/** + * @brief This macro gets AES interrupt flag. + * @param crpt Specified crypto module + * @return AES interrupt flag. + * \hideinitializer + */ +#define AES_GET_INT_FLAG(crpt) ((crpt)->INTSTS & (CRPT_INTSTS_AESIF_Msk|CRPT_INTSTS_AESEIF_Msk)) + +/** + * @brief This macro clears AES interrupt flag. + * @param crpt Specified crypto module + * @return None + * \hideinitializer + */ +#define AES_CLR_INT_FLAG(crpt) ((crpt)->INTSTS = (CRPT_INTSTS_AESIF_Msk|CRPT_INTSTS_AESEIF_Msk)) + +/** + * @brief This macro enables AES key protection. + * @param crpt Specified crypto module + * @return None + * \hideinitializer + */ +#define AES_ENABLE_KEY_PROTECT(crpt) ((crpt)->AES_CTL |= CRPT_AES_CTL_KEYPRT_Msk) + +/** + * @brief This macro disables AES key protection. + * @param crpt Specified crypto module + * @return None + * \hideinitializer + */ +#define AES_DISABLE_KEY_PROTECT(crpt) ((crpt)->AES_CTL = ((crpt)->AES_CTL & ~CRPT_AES_CTL_KEYPRT_Msk) | (0x16UL<AES_CTL &= ~CRPT_AES_CTL_KEYPRT_Msk) + +/** + * @brief This macro enables TDES interrupt. + * @param crpt Specified crypto module + * @return None + * \hideinitializer + */ +#define TDES_ENABLE_INT(crpt) ((crpt)->INTEN |= (CRPT_INTEN_TDESIEN_Msk|CRPT_INTEN_TDESEIEN_Msk)) + +/** + * @brief This macro disables TDES interrupt. + * @param crpt Specified crypto module + * @return None + * \hideinitializer + */ +#define TDES_DISABLE_INT(crpt) ((crpt)->INTEN &= ~(CRPT_INTEN_TDESIEN_Msk|CRPT_INTEN_TDESEIEN_Msk)) + +/** + * @brief This macro gets TDES interrupt flag. + * @param crpt Specified crypto module + * @return TDES interrupt flag. + * \hideinitializer + */ +#define TDES_GET_INT_FLAG(crpt) ((crpt)->INTSTS & (CRPT_INTSTS_TDESIF_Msk|CRPT_INTSTS_TDESEIF_Msk)) + +/** + * @brief This macro clears TDES interrupt flag. + * @param crpt Specified crypto module + * @return None + * \hideinitializer + */ +#define TDES_CLR_INT_FLAG(crpt) ((crpt)->INTSTS = (CRPT_INTSTS_TDESIF_Msk|CRPT_INTSTS_TDESEIF_Msk)) + +/** + * @brief This macro enables TDES key protection. + * @param crpt Specified crypto module + * @return None + * \hideinitializer + */ +#define TDES_ENABLE_KEY_PROTECT(crpt) ((crpt)->TDES_CTL |= CRPT_TDES_CTL_KEYPRT_Msk) + +/** + * @brief This macro disables TDES key protection. + * @param crpt Specified crypto module + * @return None + * \hideinitializer + */ +#define TDES_DISABLE_KEY_PROTECT(crpt) ((crpt)->TDES_CTL = ((crpt)->TDES_CTL & ~CRPT_TDES_CTL_KEYPRT_Msk) | (0x16UL<TDES_CTL &= ~CRPT_TDES_CTL_KEYPRT_Msk) + +/** + * @brief This macro enables SHA interrupt. + * @param crpt Specified crypto module + * @return None + * \hideinitializer + */ +#define SHA_ENABLE_INT(crpt) ((crpt)->INTEN |= (CRPT_INTEN_HMACIEN_Msk|CRPT_INTEN_HMACEIEN_Msk)) + +/** + * @brief This macro disables SHA interrupt. + * @param crpt Specified crypto module + * @return None + * \hideinitializer + */ +#define SHA_DISABLE_INT(crpt) ((crpt)->INTEN &= ~(CRPT_INTEN_HMACIEN_Msk|CRPT_INTEN_HMACEIEN_Msk)) + +/** + * @brief This macro gets SHA interrupt flag. + * @param crpt Specified crypto module + * @return SHA interrupt flag. + * \hideinitializer + */ +#define SHA_GET_INT_FLAG(crpt) ((crpt)->INTSTS & (CRPT_INTSTS_HMACIF_Msk|CRPT_INTSTS_HMACEIF_Msk)) + +/** + * @brief This macro clears SHA interrupt flag. + * @param crpt Specified crypto module + * @return None + * \hideinitializer + */ +#define SHA_CLR_INT_FLAG(crpt) ((crpt)->INTSTS = (CRPT_INTSTS_HMACIF_Msk|CRPT_INTSTS_HMACEIF_Msk)) + +/** + * @brief This macro enables ECC interrupt. + * @param crpt Specified crypto module + * @return None + * \hideinitializer + */ +#define ECC_ENABLE_INT(crpt) ((crpt)->INTEN |= (CRPT_INTEN_ECCIEN_Msk|CRPT_INTEN_ECCEIEN_Msk)) + +/** + * @brief This macro disables ECC interrupt. + * @param crpt Specified crypto module + * @return None + * \hideinitializer + */ +#define ECC_DISABLE_INT(crpt) ((crpt)->INTEN &= ~(CRPT_INTEN_ECCIEN_Msk|CRPT_INTEN_ECCEIEN_Msk)) + +/** + * @brief This macro gets ECC interrupt flag. + * @param crpt Specified crypto module + * @return ECC interrupt flag. + * \hideinitializer + */ +#define ECC_GET_INT_FLAG(crpt) ((crpt)->INTSTS & (CRPT_INTSTS_ECCIF_Msk|CRPT_INTSTS_ECCEIF_Msk)) + +/** + * @brief This macro clears ECC interrupt flag. + * @param crpt Specified crypto module + * @return None + * \hideinitializer + */ +#define ECC_CLR_INT_FLAG(crpt) ((crpt)->INTSTS = (CRPT_INTSTS_ECCIF_Msk|CRPT_INTSTS_ECCEIF_Msk)) + +/** + * @brief This macro enables RSA interrupt. + * @param crpt Specified crypto module + * @return None + * \hideinitializer + */ +#define RSA_ENABLE_INT(crpt) ((crpt)->INTEN |= (CRPT_INTEN_RSAIEN_Msk|CRPT_INTEN_RSAEIEN_Msk)) + +/** + * @brief This macro disables RSA interrupt. + * @param crpt Specified crypto module + * @return None + * \hideinitializer + */ +#define RSA_DISABLE_INT(crpt) ((crpt)->INTEN &= ~(CRPT_INTEN_RSAIEN_Msk|CRPT_INTEN_RSAEIEN_Msk)) + +/** + * @brief This macro gets RSA interrupt flag. + * @param crpt Specified crypto module + * @return ECC interrupt flag. + * \hideinitializer + */ +#define RSA_GET_INT_FLAG(crpt) ((crpt)->INTSTS & (CRPT_INTSTS_RSAIF_Msk|CRPT_INTSTS_RSAEIF_Msk)) + +/** + * @brief This macro clears RSA interrupt flag. + * @param crpt Specified crypto module + * @return None + * \hideinitializer + */ +#define RSA_CLR_INT_FLAG(crpt) ((crpt)->INTSTS = (CRPT_INTSTS_RSAIF_Msk|CRPT_INTSTS_RSAEIF_Msk)) + + +/**@}*/ /* end of group CRYPTO_EXPORTED_MACROS */ + + + +/** @addtogroup CRYPTO_EXPORTED_FUNCTIONS CRYPTO Exported Functions + @{ +*/ + +/*---------------------------------------------------------------------------------------------------------*/ +/* Functions */ +/*---------------------------------------------------------------------------------------------------------*/ + +void PRNG_Open(CRPT_T *crpt, uint32_t u32KeySize, uint32_t u32SeedReload, uint32_t u32Seed); +void PRNG_Start(CRPT_T *crpt); +void PRNG_Read(CRPT_T *crpt, uint32_t u32RandKey[]); +void AES_Open(CRPT_T *crpt, uint32_t u32Channel, uint32_t u32EncDec, uint32_t u32OpMode, uint32_t u32KeySize, uint32_t u32SwapType); +void AES_Start(CRPT_T *crpt, int32_t u32Channel, uint32_t u32DMAMode); +void AES_SetKey(CRPT_T *crpt, uint32_t u32Channel, uint32_t au32Keys[], uint32_t u32KeySize); +void AES_SetKey_KS(CRPT_T *crpt, KS_MEM_Type mem, int32_t i32KeyIdx); +void AES_SetInitVect(CRPT_T *crpt, uint32_t u32Channel, uint32_t au32IV[]); +void AES_SetDMATransfer(CRPT_T *crpt, uint32_t u32Channel, uint32_t u32SrcAddr, uint32_t u32DstAddr, uint32_t u32TransCnt); +void SHA_Open(CRPT_T *crpt, uint32_t u32OpMode, uint32_t u32SwapType, uint32_t hmac_key_len); +void SHA_Start(CRPT_T *crpt, uint32_t u32DMAMode); +void SHA_SetDMATransfer(CRPT_T *crpt, uint32_t u32SrcAddr, uint32_t u32TransCnt); +void SHA_Read(CRPT_T *crpt, uint32_t u32Digest[]); +void ECC_DriverISR(CRPT_T *crpt); +int ECC_IsPrivateKeyValid(CRPT_T *crpt, E_ECC_CURVE ecc_curve, char private_k[]); +int32_t ECC_GenerateSecretZ(CRPT_T *crpt, E_ECC_CURVE ecc_curve, char *private_k, char public_k1[], char public_k2[], char secret_z[]); +int32_t ECC_GeneratePublicKey(CRPT_T *crpt, E_ECC_CURVE ecc_curve, char *private_k, char public_k1[], char public_k2[]); +int32_t ECC_GenerateSignature(CRPT_T *crpt, E_ECC_CURVE ecc_curve, char *message, char *d, char *k, char *R, char *S); +int32_t ECC_VerifySignature(CRPT_T *crpt, E_ECC_CURVE ecc_curve, char *message, char *public_k1, char *public_k2, char *R, char *S); + + +int32_t RSA_Open(CRPT_T *crpt, uint32_t u32OpMode, uint32_t u32KeySize, void *psRSA_Buf, uint32_t u32BufSize, uint32_t u32UseKS); +int32_t RSA_SetKey(CRPT_T *crpt, char *Key); +int32_t RSA_SetDMATransfer(CRPT_T *crpt, char *Src, char *n, char *P, char *Q); +void RSA_Start(CRPT_T *crpt); +int32_t RSA_Read(CRPT_T *crpt, char * Output); +int32_t RSA_SetKey_KS(CRPT_T *crpt, uint32_t u32KeyNum, uint32_t u32KSMemType, uint32_t u32BlindKeyNum); +int32_t RSA_SetDMATransfer_KS(CRPT_T *crpt, char *Src, char *n, uint32_t u32PNum, + uint32_t u32QNum, uint32_t u32CpNum, uint32_t u32CqNum, uint32_t u32DpNum, + uint32_t u32DqNum, uint32_t u32RpNum, uint32_t u32RqNum); +int32_t ECC_GeneratePublicKey_KS(CRPT_T *crpt, E_ECC_CURVE ecc_curve, KS_MEM_Type mem, int32_t i32KeyIdx, char public_k1[], char public_k2[], uint32_t u32ExtraOp); +int32_t ECC_GenerateSignature_KS(CRPT_T *crpt, E_ECC_CURVE ecc_curve, char *message, KS_MEM_Type mem_d, int32_t i32KeyIdx_d, KS_MEM_Type mem_k, int32_t i32KeyIdx_k, char *R, char *S); +int32_t ECC_VerifySignature_KS(CRPT_T *crpt, E_ECC_CURVE ecc_curve, char *message, KS_MEM_Type mem_pk1, int32_t i32KeyIdx_pk1, KS_MEM_Type mem_pk2, int32_t i32KeyIdx_pk2, char *R, char *S); +int32_t ECC_GenerateSecretZ_KS(CRPT_T *crpt, E_ECC_CURVE ecc_curve, KS_MEM_Type mem, int32_t i32KeyIdx, char public_k1[], char public_k2[]); + +void CRPT_Reg2Hex(int32_t count, uint32_t volatile reg[], char output[]); +void CRPT_Hex2Reg(char input[], uint32_t volatile reg[]); +int32_t ECC_GetCurve(CRPT_T *crpt, E_ECC_CURVE ecc_curve, ECC_CURVE *curve); + +/**@}*/ /* end of group CRYPTO_EXPORTED_FUNCTIONS */ + +/**@}*/ /* end of group CRYPTO_Driver */ + +/**@}*/ /* end of group Standard_Driver */ + +#ifdef __cplusplus +} +#endif + +#endif /* __NU_CRYPTO_H__ */ + diff --git a/Ubiquitous/XiZi/board/nuvoton-m2354/third_party_driver/include/Drivers/nu_dac.h b/Ubiquitous/XiZi/board/nuvoton-m2354/third_party_driver/include/Drivers/nu_dac.h new file mode 100644 index 0000000..f8de627 --- /dev/null +++ b/Ubiquitous/XiZi/board/nuvoton-m2354/third_party_driver/include/Drivers/nu_dac.h @@ -0,0 +1,255 @@ +/****************************************************************************** + * @file nu_dac.h + * @version V1.00 + * @brief M2354 series DAC driver header file + * + * @copyright SPDX-License-Identifier: Apache-2.0 + * @copyright Copyright (C) 2020 Nuvoton Technology Corp. All rights reserved. +*****************************************************************************/ +#ifndef __NU_DAC_H__ +#define __NU_DAC_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup DAC_Driver DAC Driver + @{ +*/ + + +/** @addtogroup DAC_EXPORTED_CONSTANTS DAC Exported Constants + @{ +*/ + +/*---------------------------------------------------------------------------------------------------------*/ +/* DAC_CTL Constant Definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define DAC_CTL_LALIGN_RIGHT_ALIGN (0UL<SWTRG = DAC_SWTRG_SWTRG_Msk) + +/** + * @brief Enable DAC data left-aligned. + * @param[in] dac The pointer of the specified DAC module. + * @return None + * @details User has to load data into DAC_DAT[15:4] bits. DAC_DAT[31:16] and DAC_DAT[3:0] are ignored in DAC conversion. + */ +#define DAC_ENABLE_LEFT_ALIGN(dac) ((dac)->CTL |= DAC_CTL_LALIGN_Msk) + +/** + * @brief Enable DAC data right-aligned. + * @param[in] dac The pointer of the specified DAC module. + * @return None + * @details User has to load data into DAC_DAT[11:0] bits, DAC_DAT[31:12] are ignored in DAC conversion. + */ +#define DAC_ENABLE_RIGHT_ALIGN(dac) ((dac)->CTL &= ~DAC_CTL_LALIGN_Msk) + +/** + * @brief Enable output voltage buffer. + * @param[in] dac The pointer of the specified DAC module. + * @return None + * @details The DAC integrates a voltage output buffer that can be used to reduce output impedance and + * drive external loads directly without having to add an external operational amplifier. + */ +#define DAC_ENABLE_BYPASS_BUFFER(dac) ((dac)->CTL |= DAC_CTL_BYPASS_Msk) + +/** + * @brief Disable output voltage buffer. + * @param[in] dac The pointer of the specified DAC module. + * @return None + * @details This macro is used to disable output voltage buffer. + */ +#define DAC_DISABLE_BYPASS_BUFFER(dac) ((dac)->CTL &= ~DAC_CTL_BYPASS_Msk) + +/** + * @brief Enable the interrupt. + * @param[in] dac The pointer of the specified DAC module. + * @param[in] u32Ch Not used in M2355 Series DAC. + * @return None + * @details This macro is used to enable DAC interrupt. + */ +#define DAC_ENABLE_INT(dac, u32Ch) ((dac)->CTL |= DAC_CTL_DACIEN_Msk) + +/** + * @brief Disable the interrupt. + * @param[in] dac The pointer of the specified DAC module. + * @param[in] u32Ch Not used in M2355 Series DAC. + * @return None + * @details This macro is used to disable DAC interrupt. + */ +#define DAC_DISABLE_INT(dac, u32Ch) ((dac)->CTL &= ~DAC_CTL_DACIEN_Msk) + +/** + * @brief Enable DMA under-run interrupt. + * @param[in] dac The pointer of the specified DAC module. + * @return None + * @details This macro is used to enable DMA under-run interrupt. + */ +#define DAC_ENABLE_DMAUDR_INT(dac) ((dac)->CTL |= DAC_CTL_DMAURIEN_Msk) + +/** + * @brief Disable DMA under-run interrupt. + * @param[in] dac The pointer of the specified DAC module. + * @return None + * @details This macro is used to disable DMA under-run interrupt. + */ +#define DAC_DISABLE_DMAUDR_INT(dac) ((dac)->CTL &= ~DAC_CTL_DMAURIEN_Msk) + +/** + * @brief Enable PDMA mode. + * @param[in] dac The pointer of the specified DAC module. + * @return None + * @details DAC DMA request is generated when a hardware trigger event occurs while DMAEN (DAC_CTL[2]) is set. + */ +#define DAC_ENABLE_PDMA(dac) ((dac)->CTL |= DAC_CTL_DMAEN_Msk) + +/** + * @brief Disable PDMA mode. + * @param[in] dac The pointer of the specified DAC module. + * @return None + * @details This macro is used to disable DMA mode. + */ +#define DAC_DISABLE_PDMA(dac) ((dac)->CTL &= ~DAC_CTL_DMAEN_Msk) + +/** + * @brief Write data for conversion. + * @param[in] dac The pointer of the specified DAC module. + * @param[in] u32Ch Not used in M2355 Series DAC. + * @param[in] u32Data Decides the data for conversion, valid range are between 0~0xFFF. + * @return None + * @details 12 bit left alignment: user has to load data into DAC_DAT[15:4] bits. + * 12 bit right alignment: user has to load data into DAC_DAT[11:0] bits. + */ +#define DAC_WRITE_DATA(dac, u32Ch, u32Data) ((dac)->DAT = (u32Data)) + +/** + * @brief Read DAC 12-bit holding data. + * @param[in] dac The pointer of the specified DAC module. + * @param[in] u32Ch Not used in M2355 Series DAC. + * @return Return DAC 12-bit holding data. + * @details This macro is used to read DAC_DAT register. + */ +#define DAC_READ_DATA(dac, u32Ch) ((dac)->DAT) + +/** + * @brief Get the busy state of DAC. + * @param[in] dac The pointer of the specified DAC module. + * @param[in] u32Ch Not used in M2355 Series DAC. + * @retval 0 Idle state. + * @retval 1 Busy state. + * @details This macro is used to read BUSY bit (DAC_STATUS[8]) to get busy state. + */ +#define DAC_IS_BUSY(dac, u32Ch) (((dac)->STATUS & DAC_STATUS_BUSY_Msk) >> DAC_STATUS_BUSY_Pos) + +/** + * @brief Get the interrupt flag. + * @param[in] dac The pointer of the specified DAC module. + * @param[in] u32Ch Not used in M2355 Series DAC. + * @retval 0 DAC is in conversion state. + * @retval 1 DAC conversion finish. + * @details This macro is used to read FINISH bit (DAC_STATUS[0]) to get DAC conversion complete finish flag. + */ +#define DAC_GET_INT_FLAG(dac, u32Ch) ((dac)->STATUS & DAC_STATUS_FINISH_Msk) + +/** + * @brief Get the DMA under-run flag. + * @param[in] dac The pointer of the specified DAC module. + * @retval 0 No DMA under-run error condition occurred. + * @retval 1 DMA under-run error condition occurred. + * @details This macro is used to read DMAUDR bit (DAC_STATUS[1]) to get DMA under-run state. + */ +#define DAC_GET_DMAUDR_FLAG(dac) (((dac)->STATUS & DAC_STATUS_DMAUDR_Msk) >> DAC_STATUS_DMAUDR_Pos) + +/** + * @brief This macro clear the interrupt status bit. + * @param[in] dac The pointer of the specified DAC module. + * @param[in] u32Ch Not used in M2355 Series DAC. + * @return None + * @details User writes FINISH bit (DAC_STATUS[0]) to clear DAC conversion complete finish flag. + */ +#define DAC_CLR_INT_FLAG(dac, u32Ch) ((dac)->STATUS = DAC_STATUS_FINISH_Msk) + +/** + * @brief This macro clear the DMA under-run flag. + * @param[in] dac The pointer of the specified DAC module. + * @return None + * @details User writes DMAUDR bit (DAC_STATUS[1]) to clear DMA under-run flag. + */ +#define DAC_CLR_DMAUDR_FLAG(dac) ((dac)->STATUS = DAC_STATUS_DMAUDR_Msk) + + +/** + * @brief Enable DAC group mode + * @param[in] dac The pointer of the specified DAC module. + * @return None + * @note Only DAC0 has this control bit. + * \hideinitializer + */ +#define DAC_ENABLE_GROUP_MODE(dac) ((dac)->CTL |= DAC_CTL_GRPEN_Msk) + +/** + * @brief Disable DAC group mode + * @param[in] dac The pointer of the specified DAC module. + * @return None + * @note Only DAC0 has this control bit. + * \hideinitializer + */ +#define DAC_DISABLE_GROUP_MODE(dac) ((dac)->CTL &= ~DAC_CTL_GRPEN_Msk) + +void DAC_Open(DAC_T *dac, uint32_t u32Ch, uint32_t u32TrgSrc); +void DAC_Close(DAC_T *dac, uint32_t u32Ch); +uint32_t DAC_SetDelayTime(DAC_T *dac, uint32_t u32Delay); + +/**@}*/ /* end of group DAC_EXPORTED_FUNCTIONS */ + +/**@}*/ /* end of group DAC_Driver */ + +/**@}*/ /* end of group Standard_Driver */ + +#ifdef __cplusplus +} +#endif + +#endif /* __NU_DAC_H__ */ + diff --git a/Ubiquitous/XiZi/board/nuvoton-m2354/third_party_driver/include/Drivers/nu_dpm.h b/Ubiquitous/XiZi/board/nuvoton-m2354/third_party_driver/include/Drivers/nu_dpm.h new file mode 100644 index 0000000..879b23a --- /dev/null +++ b/Ubiquitous/XiZi/board/nuvoton-m2354/third_party_driver/include/Drivers/nu_dpm.h @@ -0,0 +1,130 @@ +/**************************************************************************//** + * @file nu_dpm.h + * @version V3.00 + * @brief Debug Protection Mechanism (DPM) driver header file + * + * @copyright SPDX-License-Identifier: Apache-2.0 + * @copyright Copyright (C) 2020 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ +#ifndef __NU_DPM_H__ +#define __NU_DPM_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup DPM_Driver DPM Driver + @{ +*/ + +/** @addtogroup DPM_EXPORTED_CONSTANTS DPM Exported Constants + @{ +*/ + + +/*---------------------------------------------------------------------------------------------------------*/ +/* DPM Control Register Constant Definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define SECURE_DPM 0 /*!< Secure DPM module */ +#define NONSECURE_DPM 1 /*!< Non-secure DPM module */ + + +#define DPM_CTL_WVCODE (0x5AUL<STS & DPM_STS_BUSY_Msk); \ + DPM->CTL = (DPM->CTL & (~DPM_CTL_WVCODE_Msk)) | (DPM_CTL_WVCODE|DPM_CTL_INTEN_Msk); \ + }while(0) + +/** + * @brief Disable DPM Interrupt + * @param None + * @return None + * @details This macro disables DPM interrupt. + * This macro is for Secure DPM and Secure region only. + */ +#define DPM_DISABLE_INT() \ + do{ \ + while(DPM->STS & DPM_STS_BUSY_Msk); \ + DPM->CTL = (DPM->CTL & (~(DPM_CTL_WVCODE_Msk|DPM_CTL_INTEN_Msk))) | (DPM_CTL_WVCODE); \ + }while(0) + +/** + * @brief Enable Debugger to Access DPM Registers + * @param None + * @return None + * @details This macro enables debugger to access Secure and Non-secure DPM registers. + * This macro is for Secure DPM and Secure region only. + */ +#define DPM_ENABLE_DBG_ACCESS() \ + do{ \ + while(DPM->STS & DPM_STS_BUSY_Msk); \ + DPM->CTL = (DPM->CTL & (~(DPM_CTL_WVCODE_Msk|DPM_CTL_DACCDIS_Msk))) | (DPM_CTL_WVCODE); \ + }while(0) + +/** + * @brief Disable Debugger to Access DPM Registers + * @param None + * @return None + * @details This macro disables debugger to access Secure and Non-secure DPM registers. + * This macro is for Secure DPM and Secure region only. + */ +#define DPM_DISABLE_DBG_ACCESS() \ + do{ \ + while(DPM->STS & DPM_STS_BUSY_Msk); \ + DPM->CTL = (DPM->CTL & (~DPM_CTL_WVCODE_Msk)) | (DPM_CTL_WVCODE|DPM_CTL_DACCDIS_Msk); \ + }while(0) + + +void DPM_SetDebugDisable(uint32_t u32dpm); +void DPM_SetDebugLock(uint32_t u32dpm); +uint32_t DPM_GetDebugDisable(uint32_t u32dpm); +uint32_t DPM_GetDebugLock(uint32_t u32dpm); +uint32_t DPM_SetPasswordUpdate(uint32_t u32dpm, uint32_t au32Pwd[]); +uint32_t DPM_SetPasswordCompare(uint32_t u32dpm, uint32_t au32Pwd[]); +uint32_t DPM_GetPasswordErrorFlag(uint32_t u32dpm); +uint32_t DPM_GetIntFlag(void); +void DPM_ClearPasswordErrorFlag(uint32_t u32dpm); +void DPM_EnableDebuggerWriteAccess(uint32_t u32dpm); +void DPM_DisableDebuggerWriteAccess(uint32_t u32dpm); + + + +/**@}*/ /* end of group DPM_EXPORTED_FUNCTIONS */ + +/**@}*/ /* end of group DPM_Driver */ + +/**@}*/ /* end of group Standard_Driver */ + +#ifdef __cplusplus +} +#endif + +#endif /* __NU_DPM_H__ */ diff --git a/Ubiquitous/XiZi/board/nuvoton-m2354/third_party_driver/include/Drivers/nu_eadc.h b/Ubiquitous/XiZi/board/nuvoton-m2354/third_party_driver/include/Drivers/nu_eadc.h new file mode 100644 index 0000000..c94a282 --- /dev/null +++ b/Ubiquitous/XiZi/board/nuvoton-m2354/third_party_driver/include/Drivers/nu_eadc.h @@ -0,0 +1,560 @@ +/****************************************************************************** + * @file nu_eadc.h + * @version V0.10 + * @brief M2354 series EADC driver header file + * + * @copyright SPDX-License-Identifier: Apache-2.0 + * @copyright Copyright (C) 2020 Nuvoton Technology Corp. All rights reserved. +*****************************************************************************/ +#ifndef __NU_EADC_H__ +#define __NU_EADC_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup EADC_Driver EADC Driver + @{ +*/ + +/** @addtogroup EADC_EXPORTED_CONSTANTS EADC Exported Constants + @{ +*/ + +/*---------------------------------------------------------------------------------------------------------*/ +/* EADC_CTL Constant Definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define EADC_CTL_DIFFEN_SINGLE_END (0UL<CTL |= EADC_CTL_ADCRST_Msk) + +/** + * @brief Enable Sample Module PDMA transfer. + * @param[in] eadc The pointer of the specified EADC module. + * @param[in] u32ModuleMask the combination of sample module interrupt status bits. Each bit corresponds to a sample module interrupt status. + * This parameter decides which sample module interrupts will be disabled, valid range are between 1~0x7FFFF. + * @return None + * @details When A/D conversion is completed, the converted data is loaded into EADC_DATn (n: 0 ~ 18) register, + * user can enable this bit to generate a PDMA data transfer request. + * \hideinitializer + */ +#define EADC_ENABLE_SAMPLE_MODULE_PDMA(eadc, u32ModuleMask) ((eadc)->PDMACTL |= u32ModuleMask) + +/** + * @brief Disable Sample Module PDMA transfer. + * @param[in] eadc The pointer of the specified EADC module. + * @param[in] u32ModuleMask the combination of sample module interrupt status bits. Each bit corresponds to a sample module interrupt status. + * This parameter decides which sample module interrupts will be disabled, valid range are between 1~0x7FFFF. + * @return None + * @details This macro is used to disable sample module PDMA transfer. + * \hideinitializer + */ +#define EADC_DISABLE_SAMPLE_MODULE_PDMA(eadc, u32ModuleMask) ((eadc)->PDMACTL &= (~u32ModuleMask)) + +/** + * @brief Enable double buffer mode. + * @param[in] eadc The pointer of the specified EADC module. + * @param[in] u32ModuleNum Decides the sample module number, valid value are from 0 to 3. + * @return None + * @details The ADC controller supports a double buffer mode in sample module 0~3. + * If user enable DBMEN (EADC_SCTLn[23], n=0~3), the double buffer mode will enable. + */ +#define EADC_ENABLE_DOUBLE_BUFFER(eadc, u32ModuleNum) ((eadc)->SCTL[(u32ModuleNum)] |= EADC_SCTL_DBMEN_Msk) + +/** + * @brief Disable double buffer mode. + * @param[in] eadc The pointer of the specified EADC module. + * @param[in] u32ModuleNum Decides the sample module number, valid value are from 0 to 3. + * @return None + * @details Sample has one sample result register. + */ +#define EADC_DISABLE_DOUBLE_BUFFER(eadc, u32ModuleNum) ((eadc)->SCTL[(u32ModuleNum)] &= ~EADC_SCTL_DBMEN_Msk) + +/** + * @brief Set ADIFn at A/D end of conversion. + * @param[in] eadc The pointer of the specified EADC module. + * @param[in] u32ModuleNum Decides the sample module number, valid value are from 0 to 15. + * @return None + * @details The A/D converter generates ADIFn (EADC_STATUS2[3:0], n=0~3) at the start of conversion. + */ +#define EADC_ENABLE_INT_POSITION(eadc, u32ModuleNum) ((eadc)->SCTL[(u32ModuleNum)] |= EADC_SCTL_INTPOS_Msk) + +/** + * @brief Set ADIFn at A/D start of conversion. + * @param[in] eadc The pointer of the specified EADC module. + * @param[in] u32ModuleNum Decides the sample module number, valid value are from 0 to 15. + * @return None + * @details The A/D converter generates ADIFn (EADC_STATUS2[3:0], n=0~3) at the end of conversion. + */ +#define EADC_DISABLE_INT_POSITION(eadc, u32ModuleNum) ((eadc)->SCTL[(u32ModuleNum)] &= ~EADC_SCTL_INTPOS_Msk) + +/** + * @brief Enable the interrupt. + * @param[in] eadc The pointer of the specified EADC module. + * @param[in] u32Mask Decides the combination of interrupt status bits. Each bit corresponds to a interrupt status. + * This parameter decides which interrupts will be enabled. Bit 0 is ADCIEN0, bit 1 is ADCIEN1..., bit 3 is ADCIEN3. + * @return None + * @details The A/D converter generates a conversion end ADIFn (EADC_STATUS2[n]) upon the end of specific sample module A/D conversion. + * If ADCIENn bit (EADC_CTL[n+2]) is set then conversion end interrupt request ADINTn is generated (n=0~3). + */ +#define EADC_ENABLE_INT(eadc, u32Mask) ((eadc)->CTL |= ((u32Mask) << EADC_CTL_ADCIEN0_Pos)) + +/** + * @brief Disable the interrupt. + * @param[in] eadc The pointer of the specified EADC module. + * @param[in] u32Mask Decides the combination of interrupt status bits. Each bit corresponds to a interrupt status. + * This parameter decides which interrupts will be disabled. Bit 0 is ADCIEN0, bit 1 is ADCIEN1..., bit 3 is ADCIEN3. + * @return None + * @details Specific sample module A/D ADINT0 interrupt function Disabled. + */ +#define EADC_DISABLE_INT(eadc, u32Mask) ((eadc)->CTL &= ~((u32Mask) << EADC_CTL_ADCIEN0_Pos)) + +/** + * @brief Enable the sample module interrupt. + * @param[in] eadc The pointer of the specified EADC module. + * @param[in] u32IntSel Decides which interrupt source will be used, valid value are from 0 to 3. + * @param[in] u32ModuleMask the combination of sample module interrupt status bits. Each bit corresponds to a sample module interrupt status. + * This parameter decides which sample module interrupts will be enabled, valid range are between 1~0x7FFFF. + * @return None + * @details There are 4 ADC interrupts ADINT0~3, and each of these interrupts has its own interrupt vector address. + */ +#define EADC_ENABLE_SAMPLE_MODULE_INT(eadc, u32IntSel, u32ModuleMask) ((eadc)->INTSRC[(u32IntSel)] |= (u32ModuleMask)) + +/** + * @brief Disable the sample module interrupt. + * @param[in] eadc The pointer of the specified EADC module. + * @param[in] u32IntSel Decides which interrupt source will be used, valid value are from 0 to 3. + * @param[in] u32ModuleMask the combination of sample module interrupt status bits. Each bit corresponds to a sample module interrupt status. + * This parameter decides which sample module interrupts will be disabled, valid range are between 1~0x7FFFF. + * @return None + * @details There are 4 ADC interrupts ADINT0~3, and each of these interrupts has its own interrupt vector address. + */ +#define EADC_DISABLE_SAMPLE_MODULE_INT(eadc, u32IntSel, u32ModuleMask) ((eadc)->INTSRC[(u32IntSel)] &= (uint32_t)(~(u32ModuleMask))) + +/** + * @brief Set the input mode output format. + * @param[in] eadc The pointer of the specified EADC module. + * @param[in] u32Format Decides the output format. Valid values are: + * - \ref EADC_CTL_DMOF_STRAIGHT_BINARY :Select the straight binary format as the output format of the conversion result. + * - \ref EADC_CTL_DMOF_TWOS_COMPLEMENT :Select the 2's complement format as the output format of the conversion result. + * @return None + * @details The macro is used to set A/D input mode output format. + */ +#define EADC_SET_DMOF(eadc, u32Format) ((eadc)->CTL = ((eadc)->CTL & ~EADC_CTL_DMOF_Msk) | (u32Format)) + +/** + * @brief Start the A/D conversion. + * @param[in] eadc The pointer of the specified EADC module. + * @param[in] u32ModuleMask The combination of sample module. Each bit corresponds to a sample module. + * This parameter decides which sample module will be conversion, valid range are between 1~0x7FFFF. + * Bit 0 is sample module 0, bit 1 is sample module 1..., bit 18 is sample module 18. + * @return None + * @details After write EADC_SWTRG register to start ADC conversion, the EADC_PENDSTS register will show which SAMPLE will conversion. + */ +#define EADC_START_CONV(eadc, u32ModuleMask) ((eadc)->SWTRG = (u32ModuleMask)) + +/** + * @brief Cancel the conversion for sample module. + * @param[in] eadc The pointer of the specified EADC module. + * @param[in] u32ModuleMask The combination of sample module. Each bit corresponds to a sample module. + * This parameter decides which sample module will stop the conversion, valid range are between 1~0x7FFFF. + * Bit 0 is sample module 0, bit 1 is sample module 1..., bit 18 is sample module18. + * @return None + * @details If user want to disable the conversion of the sample module, user can write EADC_PENDSTS register to clear it. + */ +#define EADC_STOP_CONV(eadc, u32ModuleMask) ((eadc)->PENDSTS = (u32ModuleMask)) + +/** + * @brief Get the conversion pending flag. + * @param[in] eadc The pointer of the specified EADC module. + * @return Return the conversion pending sample module. + * @details This STPFn(EADC_PENDSTS[18:0]) bit remains 1 during pending state, when the respective ADC conversion is end, + * the STPFn (n=0~18) bit is automatically cleared to 0. + */ +#define EADC_GET_PENDING_CONV(eadc) ((eadc)->PENDSTS) + +/** + * @brief Get the conversion data of the user-specified sample module. + * @param[in] eadc The pointer of the specified EADC module. + * @param[in] u32ModuleNum Decides the sample module number, valid value are from 0 to 18. + * @return Return the conversion data of the user-specified sample module. + * @details This macro is used to read RESULT bit (EADC_DATn[15:0], n=0~18) field to get conversion data. + */ +#define EADC_GET_CONV_DATA(eadc, u32ModuleNum) ((eadc)->DAT[(u32ModuleNum)] & EADC_DAT_RESULT_Msk) + +/** + * @brief Get the data overrun flag of the user-specified sample module. + * @param[in] eadc The pointer of the specified EADC module. + * @param[in] u32ModuleMask The combination of data overrun status bits. Each bit corresponds to a data overrun status, valid range are between 1~0x7FFFF. + * @return Return the data overrun flag of the user-specified sample module. + * @details This macro is used to read OV bit (EADC_STATUS0[31:16], EADC_STATUS1[18:16]) field to get data overrun status. + */ +#define EADC_GET_DATA_OVERRUN_FLAG(eadc, u32ModuleMask) ((((eadc)->STATUS0 >> EADC_STATUS0_OV_Pos) | ((eadc)->STATUS1 & EADC_STATUS1_OV_Msk)) & (u32ModuleMask)) + +/** + * @brief Get the data valid flag of the user-specified sample module. + * @param[in] eadc The pointer of the specified EADC module. + * @param[in] u32ModuleMask The combination of data valid status bits. Each bit corresponds to a data valid status, valid range are between 1~0x7FFFF. + * @return Return the data valid flag of the user-specified sample module. + * @details This macro is used to read VALID bit (EADC_STATUS0[15:0], EADC_STATUS1[2:0]) field to get data valid status. + */ +#define EADC_GET_DATA_VALID_FLAG(eadc, u32ModuleMask) ((((eadc)->STATUS0 & EADC_STATUS0_VALID_Msk) | (((eadc)->STATUS1 & EADC_STATUS1_VALID_Msk) << 16)) & (u32ModuleMask)) + +/** + * @brief Get the double data of the user-specified sample module. + * @param[in] eadc The pointer of the specified EADC module. + * @param[in] u32ModuleNum Decides the sample module number, valid value are from 0 to 18. + * @return Return the double data of the user-specified sample module. + * @details This macro is used to read RESULT bit (EADC_DDATn[15:0], n=0~3) field to get conversion data. + */ +#define EADC_GET_DOUBLE_DATA(eadc, u32ModuleNum) ((eadc)->DDAT[(u32ModuleNum)] & EADC_DDAT0_RESULT_Msk) + +/** + * @brief Get the user-specified interrupt flags. + * @param[in] eadc The pointer of the specified EADC module. + * @param[in] u32Mask The combination of interrupt status bits. Each bit corresponds to a interrupt status. + * Bit 0 is ADIF0, bit 1 is ADIF1..., bit 3 is ADIF3. + * Bit 4 is ADCMPF0, bit 5 is ADCMPF1..., bit 7 is ADCMPF3. + * @return Return the user-specified interrupt flags. + * @details This macro is used to get the user-specified interrupt flags. + */ +#define EADC_GET_INT_FLAG(eadc, u32Mask) ((eadc)->STATUS2 & (u32Mask)) + +/** + * @brief Get the user-specified sample module overrun flags. + * @param[in] eadc The pointer of the specified EADC module. + * @param[in] u32ModuleMask The combination of sample module overrun status bits. Each bit corresponds to a sample module overrun status, valid range are between 1~0x7FFFF. + * @return Return the user-specified sample module overrun flags. + * @details This macro is used to get the user-specified sample module overrun flags. + */ +#define EADC_GET_SAMPLE_MODULE_OV_FLAG(eadc, u32ModuleMask) ((eadc)->OVSTS & (u32ModuleMask)) + +/** + * @brief Clear the selected interrupt status bits. + * @param[in] eadc The pointer of the specified EADC module. + * @param[in] u32Mask The combination of compare interrupt status bits. Each bit corresponds to a compare interrupt status. + * Bit 0 is ADIF0, bit 1 is ADIF1..., bit 3 is ADIF3. + * Bit 4 is ADCMPF0, bit 5 is ADCMPF1..., bit 7 is ADCMPF3. + * @return None + * @details This macro is used to clear clear the selected interrupt status bits. + */ +#define EADC_CLR_INT_FLAG(eadc, u32Mask) ((eadc)->STATUS2 = (u32Mask)) + +/** + * @brief Clear the selected sample module overrun status bits. + * @param[in] eadc The pointer of the specified EADC module. + * @param[in] u32ModuleMask The combination of sample module overrun status bits. Each bit corresponds to a sample module overrun status. + * Bit 0 is SPOVF0, bit 1 is SPOVF1..., bit 18 is SPOVF18. + * @return None + * @details This macro is used to clear the selected sample module overrun status bits. + */ +#define EADC_CLR_SAMPLE_MODULE_OV_FLAG(eadc, u32ModuleMask) ((eadc)->OVSTS = (u32ModuleMask)) + +/** + * @brief Check all sample module A/D result data register overrun flags. + * @param[in] eadc The pointer of the specified EADC module. + * @retval 0 None of sample module data register overrun flag is set to 1. + * @retval 1 Any one of sample module data register overrun flag is set to 1. + * @details The AOV bit (EADC_STATUS2[27]) will keep 1 when any one of sample module data register overrun flag OVn (EADC_DATn[16]) is set to 1. + */ +#define EADC_IS_DATA_OV(eadc) (((eadc)->STATUS2 & EADC_STATUS2_AOV_Msk) >> EADC_STATUS2_AOV_Pos) + +/** + * @brief Check all sample module A/D result data register valid flags. + * @param[in] eadc The pointer of the specified EADC module. + * @retval 0 None of sample module data register valid flag is set to 1. + * @retval 1 Any one of sample module data register valid flag is set to 1. + * @details The AVALID bit (EADC_STATUS2[26]) will keep 1 when any one of sample module data register valid flag VALIDn (EADC_DATn[17]) is set to 1. + */ +#define EADC_IS_DATA_VALID(eadc) (((eadc)->STATUS2 & EADC_STATUS2_AVALID_Msk) >> EADC_STATUS2_AVALID_Pos) + +/** + * @brief Check all A/D sample module start of conversion overrun flags. + * @param[in] eadc The pointer of the specified EADC module. + * @retval 0 None of sample module event overrun flag is set to 1. + * @retval 1 Any one of sample module event overrun flag is set to 1. + * @details The STOVF bit (EADC_STATUS2[25]) will keep 1 when any one of sample module event overrun flag SPOVFn (EADC_OVSTS[n]) is set to 1. + */ +#define EADC_IS_SAMPLE_MODULE_OV(eadc) (((eadc)->STATUS2 & EADC_STATUS2_STOVF_Msk) >> EADC_STATUS2_STOVF_Pos) + +/** + * @brief Check all A/D interrupt flag overrun bits. + * @param[in] eadc The pointer of the specified EADC module. + * @retval 0 None of ADINT interrupt flag is overwritten to 1. + * @retval 1 Any one of ADINT interrupt flag is overwritten to 1. + * @details The ADOVIF bit (EADC_STATUS2[24]) will keep 1 when any one of ADINT interrupt flag ADOVIFn (EADC_STATUS2[11:8]) is overwritten to 1. + */ +#define EADC_IS_INT_FLAG_OV(eadc) (((eadc)->STATUS2 & EADC_STATUS2_ADOVIF_Msk) >> EADC_STATUS2_ADOVIF_Pos) + +/** + * @brief Get the busy state of EADC. + * @param[in] eadc The pointer of the specified EADC module. + * @retval 0 Idle state. + * @retval 1 Busy state. + * @details This macro is used to read BUSY bit (EADC_STATUS2[23]) to get busy state. + */ +#define EADC_IS_BUSY(eadc) (((eadc)->STATUS2 & EADC_STATUS2_BUSY_Msk) >> EADC_STATUS2_BUSY_Pos) + +/** + * @brief Configure the comparator 0 and enable it. + * @param[in] eadc The pointer of the specified EADC module. + * @param[in] u32ModuleNum specifies the compare sample module, valid value are from 0 to 18. + * @param[in] u32Condition specifies the compare condition. Valid values are: + * - \ref EADC_CMP_CMPCOND_LESS_THAN :The compare condition is "less than the compare value" + * - \ref EADC_CMP_CMPCOND_GREATER_OR_EQUAL :The compare condition is "greater than or equal to the compare value + * @param[in] u16CMPData specifies the compare value, valid range are between 0~0xFFF. + * @param[in] u32MatchCount specifies the match count setting, valid range are between 0~0xF. + * @return None + * @details For example, ADC_ENABLE_CMP0(EADC, 5, ADC_ADCMPR_CMPCOND_GREATER_OR_EQUAL, 0x800, 10, EADC_CMP_CMPWEN_DISABLE, EADC_CMP_ADCMPIE_ENABLE); + * Means EADC will assert comparator 0 flag if sample module 5 conversion result is greater or + * equal to 0x800 for 10 times continuously, and a compare interrupt request is generated. + */ +#define EADC_ENABLE_CMP0(eadc,\ + u32ModuleNum,\ + u32Condition,\ + u16CMPData,\ + u32MatchCount) ((eadc)->CMP[0] |=(((u32ModuleNum) << EADC_CMP_CMPSPL_Pos)|\ + (u32Condition) |\ + ((u16CMPData) << EADC_CMP_CMPDAT_Pos)| \ + (((u32MatchCount) - 1UL) << EADC_CMP_CMPMCNT_Pos)|\ + EADC_CMP_ADCMPEN_Msk)) + +/** + * @brief Configure the comparator 1 and enable it. + * @param[in] eadc The pointer of the specified EADC module. + * @param[in] u32ModuleNum specifies the compare sample module, valid value are from 0 to 18. + * @param[in] u32Condition specifies the compare condition. Valid values are: + * - \ref EADC_CMP_CMPCOND_LESS_THAN :The compare condition is "less than the compare value" + * - \ref EADC_CMP_CMPCOND_GREATER_OR_EQUAL :The compare condition is "greater than or equal to the compare value + * @param[in] u16CMPData specifies the compare value, valid range are between 0~0xFFF. + * @param[in] u32MatchCount specifies the match count setting, valid range are between 0~0xF. + * @return None + * @details For example, ADC_ENABLE_CMP1(EADC, 5, ADC_ADCMPR_CMPCOND_GREATER_OR_EQUAL, 0x800, 10, EADC_CMP_ADCMPIE_ENABLE); + * Means EADC will assert comparator 1 flag if sample module 5 conversion result is greater or + * equal to 0x800 for 10 times continuously, and a compare interrupt request is generated. + */ +#define EADC_ENABLE_CMP1(eadc,\ + u32ModuleNum,\ + u32Condition,\ + u16CMPData,\ + u32MatchCount) ((eadc)->CMP[1] |=(((u32ModuleNum) << EADC_CMP_CMPSPL_Pos)|\ + (u32Condition) |\ + ((u16CMPData) << EADC_CMP_CMPDAT_Pos)| \ + (((u32MatchCount) - 1UL) << EADC_CMP_CMPMCNT_Pos)|\ + EADC_CMP_ADCMPEN_Msk)) + +/** + * @brief Configure the comparator 2 and enable it. + * @param[in] eadc The pointer of the specified EADC module. + * @param[in] u32ModuleNum specifies the compare sample module, valid value are from 0 to 18. + * @param[in] u32Condition specifies the compare condition. Valid values are: + * - \ref EADC_CMP_CMPCOND_LESS_THAN :The compare condition is "less than the compare value" + * - \ref EADC_CMP_CMPCOND_GREATER_OR_EQUAL :The compare condition is "greater than or equal to the compare value + * @param[in] u16CMPData specifies the compare value, valid range are between 0~0xFFF. + * @param[in] u32MatchCount specifies the match count setting, valid range are between 0~0xF. + * @return None + * @details For example, ADC_ENABLE_CMP2(EADC, 5, ADC_ADCMPR_CMPCOND_GREATER_OR_EQUAL, 0x800, 10, EADC_CMP_CMPWEN_DISABLE, EADC_CMP_ADCMPIE_ENABLE); + * Means EADC will assert comparator 2 flag if sample module 5 conversion result is greater or + * equal to 0x800 for 10 times continuously, and a compare interrupt request is generated. + */ +#define EADC_ENABLE_CMP2(eadc,\ + u32ModuleNum,\ + u32Condition,\ + u16CMPData,\ + u32MatchCount) ((eadc)->CMP[2] |=(((u32ModuleNum) << EADC_CMP_CMPSPL_Pos)|\ + (u32Condition) |\ + ((u16CMPData) << EADC_CMP_CMPDAT_Pos)| \ + (((u32MatchCount) - 1UL) << EADC_CMP_CMPMCNT_Pos)|\ + EADC_CMP_ADCMPEN_Msk)) + +/** + * @brief Configure the comparator 3 and enable it. + * @param[in] eadc The pointer of the specified EADC module. + * @param[in] u32ModuleNum specifies the compare sample module, valid value are from 0 to 18. + * @param[in] u32Condition specifies the compare condition. Valid values are: + * - \ref EADC_CMP_CMPCOND_LESS_THAN :The compare condition is "less than the compare value" + * - \ref EADC_CMP_CMPCOND_GREATER_OR_EQUAL :The compare condition is "greater than or equal to the compare value + * @param[in] u16CMPData specifies the compare value, valid range are between 0~0xFFF. + * @param[in] u32MatchCount specifies the match count setting, valid range are between 1~0xF. + * @return None + * @details For example, ADC_ENABLE_CMP3(EADC, 5, ADC_ADCMPR_CMPCOND_GREATER_OR_EQUAL, 0x800, 10, EADC_CMP_ADCMPIE_ENABLE); + * Means EADC will assert comparator 3 flag if sample module 5 conversion result is greater or + * equal to 0x800 for 10 times continuously, and a compare interrupt request is generated. + */ +#define EADC_ENABLE_CMP3(eadc,\ + u32ModuleNum,\ + u32Condition,\ + u16CMPData,\ + u32MatchCount) ((eadc)->CMP[3] |=(((u32ModuleNum) << EADC_CMP_CMPSPL_Pos)|\ + (u32Condition) |\ + ((u16CMPData) << EADC_CMP_CMPDAT_Pos)| \ + (((u32MatchCount) - 1UL) << EADC_CMP_CMPMCNT_Pos)|\ + EADC_CMP_ADCMPEN_Msk)) + +/** + * @brief Enable the compare window mode. + * @param[in] eadc The pointer of the specified EADC module. + * @param[in] u32CMP Specifies the compare register, valid value are 0 and 2. + * @return None + * @details ADCMPF0 (EADC_STATUS2[4]) will be set when both EADC_CMP0 and EADC_CMP1 compared condition matched. + */ +#define EADC_ENABLE_CMP_WINDOW_MODE(eadc, u32CMP) ((eadc)->CMP[(u32CMP)] |= EADC_CMP_CMPWEN_Msk) + +/** + * @brief Disable the compare window mode. + * @param[in] eadc The pointer of the specified EADC module. + * @param[in] u32CMP Specifies the compare register, valid value are 0 and 2. + * @return None + * @details ADCMPF2 (EADC_STATUS2[6]) will be set when both EADC_CMP2 and EADC_CMP3 compared condition matched. + */ +#define EADC_DISABLE_CMP_WINDOW_MODE(eadc, u32CMP) ((eadc)->CMP[(u32CMP)] &= ~EADC_CMP_CMPWEN_Msk) + +/** + * @brief Enable the compare interrupt. + * @param[in] eadc The pointer of the specified EADC module. + * @param[in] u32CMP Specifies the compare register, valid value are from 0 to 3. + * @return None + * @details If the compare function is enabled and the compare condition matches the setting of CMPCOND (EADC_CMPn[2], n=0~3) + * and CMPMCNT (EADC_CMPn[11:8], n=0~3), ADCMPFn (EADC_STATUS2[7:4], n=0~3) will be asserted, in the meanwhile, + * if ADCMPIE is set to 1, a compare interrupt request is generated. + */ +#define EADC_ENABLE_CMP_INT(eadc, u32CMP) ((eadc)->CMP[(u32CMP)] |= EADC_CMP_ADCMPIE_Msk) + +/** + * @brief Disable the compare interrupt. + * @param[in] eadc The pointer of the specified EADC module. + * @param[in] u32CMP Specifies the compare register, valid value are from 0 to 3. + * @return None + * @details This macro is used to disable the compare interrupt. + */ +#define EADC_DISABLE_CMP_INT(eadc, u32CMP) ((eadc)->CMP[(u32CMP)] &= ~EADC_CMP_ADCMPIE_Msk) + +/** + * @brief Disable comparator 0. + * @param[in] eadc The pointer of the specified EADC module. + * @return None + * @details This macro is used to disable comparator 0. + */ +#define EADC_DISABLE_CMP0(eadc) ((eadc)->CMP[0] = 0UL) + +/** + * @brief Disable comparator 1. + * @param[in] eadc The pointer of the specified EADC module. + * @return None + * @details This macro is used to disable comparator 1. + */ +#define EADC_DISABLE_CMP1(eadc) ((eadc)->CMP[1] = 0UL) + +/** + * @brief Disable comparator 2. + * @param[in] eadc The pointer of the specified EADC module. + * @return None + * @details This macro is used to disable comparator 2. + */ +#define EADC_DISABLE_CMP2(eadc) ((eadc)->CMP[2] = 0UL) + +/** + * @brief Disable comparator 3. + * @param[in] eadc The pointer of the specified EADC module. + * @return None + * @details This macro is used to disable comparator 3. + */ +#define EADC_DISABLE_CMP3(eadc) ((eadc)->CMP[3] = 0UL) + +/*---------------------------------------------------------------------------------------------------------*/ +/* Define EADC functions prototype */ +/*---------------------------------------------------------------------------------------------------------*/ +void EADC_Open(EADC_T *eadc, uint32_t u32InputMode); +void EADC_Close(EADC_T *eadc); +void EADC_ConfigSampleModule(EADC_T *eadc, uint32_t u32ModuleNum, uint32_t u32TriggerSrc, uint32_t u32Channel); +void EADC_SetTriggerDelayTime(EADC_T *eadc, uint32_t u32ModuleNum, uint32_t u32TriggerDelayTime, uint32_t u32DelayClockDivider); +void EADC_SetExtendSampleTime(EADC_T *eadc, uint32_t u32ModuleNum, uint32_t u32ExtendSampleTime); + +/**@}*/ /* end of group EADC_EXPORTED_FUNCTIONS */ + +/**@}*/ /* end of group EADC_Driver */ + +/**@}*/ /* end of group Standard_Driver */ + +#ifdef __cplusplus +} +#endif + +#endif /* __NU_EADC_H__ */ + diff --git a/Ubiquitous/XiZi/board/nuvoton-m2354/third_party_driver/include/Drivers/nu_ebi.h b/Ubiquitous/XiZi/board/nuvoton-m2354/third_party_driver/include/Drivers/nu_ebi.h new file mode 100644 index 0000000..77c928b --- /dev/null +++ b/Ubiquitous/XiZi/board/nuvoton-m2354/third_party_driver/include/Drivers/nu_ebi.h @@ -0,0 +1,369 @@ +/**************************************************************************//** + * @file nu_ebi.h + * @version V3.00 + * @brief External Bus Interface(EBI) driver header file + * + * @copyright SPDX-License-Identifier: Apache-2.0 + * @copyright Copyright (C) 2020 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ +#ifndef __NU_EBI_H__ +#define __NU_EBI_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup EBI_Driver EBI Driver + @{ +*/ + +/** @addtogroup EBI_EXPORTED_CONSTANTS EBI Exported Constants + @{ +*/ +/*---------------------------------------------------------------------------------------------------------*/ +/* Miscellaneous Constant Definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define EBI_BANK0_BASE_ADDR 0x60000000UL /*!< EBI bank0 base address \hideinitializer */ +#define EBI_BANK1_BASE_ADDR 0x60100000UL /*!< EBI bank1 base address \hideinitializer */ +#define EBI_BANK2_BASE_ADDR 0x60200000UL /*!< EBI bank2 base address \hideinitializer */ +#define EBI_BANK0_BASE_ADDR_NS 0x70000000UL /*!< EBI bank0 base address for Non-Secure \hideinitializer */ +#define EBI_BANK1_BASE_ADDR_NS 0x70100000UL /*!< EBI bank1 base address for Non-Secure \hideinitializer */ +#define EBI_BANK2_BASE_ADDR_NS 0x70200000UL /*!< EBI bank2 base address for Non-Secure \hideinitializer */ +#define EBI_MAX_SIZE 0x00100000UL /*!< Maximum EBI size for each bank is 1 MB \hideinitializer */ + +/*---------------------------------------------------------------------------------------------------------*/ +/* Constants for EBI bank number */ +/*---------------------------------------------------------------------------------------------------------*/ +#define EBI_BANK0 0UL /*!< EBI bank 0 \hideinitializer */ +#define EBI_BANK1 1UL /*!< EBI bank 1 \hideinitializer */ +#define EBI_BANK2 2UL /*!< EBI bank 2 \hideinitializer */ + +/*---------------------------------------------------------------------------------------------------------*/ +/* Constants for EBI data bus width */ +/*---------------------------------------------------------------------------------------------------------*/ +#define EBI_BUSWIDTH_8BIT 8UL /*!< EBI bus width is 8-bit \hideinitializer */ +#define EBI_BUSWIDTH_16BIT 16UL /*!< EBI bus width is 16-bit \hideinitializer */ + +/*---------------------------------------------------------------------------------------------------------*/ +/* Constants for EBI CS Active Level */ +/*---------------------------------------------------------------------------------------------------------*/ +#define EBI_CS_ACTIVE_LOW 0UL /*!< EBI CS active level is low \hideinitializer */ +#define EBI_CS_ACTIVE_HIGH 1UL /*!< EBI CS active level is high \hideinitializer */ + +/*---------------------------------------------------------------------------------------------------------*/ +/* Constants for EBI MCLK divider and Timing */ +/*---------------------------------------------------------------------------------------------------------*/ +#define EBI_MCLKDIV_1 0x0UL /*!< EBI output clock(MCLK) is HCLK/1 \hideinitializer */ +#define EBI_MCLKDIV_2 0x1UL /*!< EBI output clock(MCLK) is HCLK/2 \hideinitializer */ +#define EBI_MCLKDIV_4 0x2UL /*!< EBI output clock(MCLK) is HCLK/4 \hideinitializer */ +#define EBI_MCLKDIV_8 0x3UL /*!< EBI output clock(MCLK) is HCLK/8 \hideinitializer */ +#define EBI_MCLKDIV_16 0x4UL /*!< EBI output clock(MCLK) is HCLK/16 \hideinitializer */ +#define EBI_MCLKDIV_32 0x5UL /*!< EBI output clock(MCLK) is HCLK/32 \hideinitializer */ +#define EBI_MCLKDIV_64 0x6UL /*!< EBI output clock(MCLK) is HCLK/64 \hideinitializer */ +#define EBI_MCLKDIV_128 0x7UL /*!< EBI output clock(MCLK) is HCLK/128 \hideinitializer */ + +#define EBI_TIMING_FASTEST 0x0UL /*!< EBI timing is the fastest \hideinitializer */ +#define EBI_TIMING_VERYFAST 0x1UL /*!< EBI timing is very fast \hideinitializer */ +#define EBI_TIMING_FAST 0x2UL /*!< EBI timing is fast \hideinitializer */ +#define EBI_TIMING_NORMAL 0x3UL /*!< EBI timing is normal \hideinitializer */ +#define EBI_TIMING_SLOW 0x4UL /*!< EBI timing is slow \hideinitializer */ +#define EBI_TIMING_VERYSLOW 0x5UL /*!< EBI timing is very slow \hideinitializer */ +#define EBI_TIMING_SLOWEST 0x6UL /*!< EBI timing is the slowest \hideinitializer */ + +#define EBI_OPMODE_NORMAL 0x0UL /*!< EBI bus operate in normal mode \hideinitializer */ +#define EBI_OPMODE_CACCESS (EBI_CTL_CACCESS_Msk) /*!< EBI bus operate in Continuous Data Access mode \hideinitializer */ +#define EBI_OPMODE_ADSEPARATE (EBI_CTL_ADSEPEN_Msk) /*!< EBI bus operate in AD Separate mode \hideinitializer */ + +/**@}*/ /* end of group EBI_EXPORTED_CONSTANTS */ + + +/** @addtogroup EBI_EXPORTED_FUNCTIONS EBI Exported Functions + @{ +*/ + +/** + * @brief Read 8-bit data on EBI bank0 + * + * @param[in] ebi The pointer of EBI module. + * @param[in] u32Addr The data address on EBI bank0. + * + * @return 8-bit Data + * + * @details This macro is used to read 8-bit data from specify address on EBI bank0. + * \hideinitializer + */ +#define EBI0_READ_DATA8(ebi, u32Addr) (*((volatile unsigned char *)((((ebi)==EBI_S)? EBI_BANK0_BASE_ADDR:EBI_BANK0_BASE_ADDR_NS)+(u32Addr)))) + +/** + * @brief Write 8-bit data to EBI bank0 + * + * @param[in] ebi The pointer of EBI module. + * @param[in] u32Addr The data address on EBI bank0. + * @param[in] u32Data Specify data to be written. + * + * @return None + * + * @details This macro is used to write 8-bit data to specify address on EBI bank0. + * \hideinitializer + */ +#define EBI0_WRITE_DATA8(ebi, u32Addr, u32Data) (*((volatile unsigned char *)((((ebi)==EBI_S)? EBI_BANK0_BASE_ADDR:EBI_BANK0_BASE_ADDR_NS)+(u32Addr))) = (u32Data)) + +/** + * @brief Read 16-bit data on EBI bank0 + * + * @param[in] ebi The pointer of EBI module. + * @param[in] u32Addr The data address on EBI bank0. + * + * @return 16-bit Data + * + * @details This macro is used to read 16-bit data from specify address on EBI bank0. + * \hideinitializer + */ +#define EBI0_READ_DATA16(ebi, u32Addr) (*((volatile unsigned short *)((((ebi)==EBI_S)? EBI_BANK0_BASE_ADDR:EBI_BANK0_BASE_ADDR_NS)+(u32Addr)))) + +/** + * @brief Write 16-bit data to EBI bank0 + * + * @param[in] ebi The pointer of EBI module. + * @param[in] u32Addr The data address on EBI bank0. + * @param[in] u32Data Specify data to be written. + * + * @return None + * + * @details This macro is used to write 16-bit data to specify address on EBI bank0. + * \hideinitializer + */ +#define EBI0_WRITE_DATA16(ebi, u32Addr, u32Data) (*((volatile unsigned short *)((((ebi)==EBI_S)? EBI_BANK0_BASE_ADDR:EBI_BANK0_BASE_ADDR_NS)+(u32Addr))) = (u32Data)) + +/** + * @brief Read 32-bit data on EBI bank0 + * + * @param[in] ebi The pointer of EBI module. + * @param[in] u32Addr The data address on EBI bank0. + * + * @return 32-bit Data + * + * @details This macro is used to read 32-bit data from specify address on EBI bank0. + * \hideinitializer + */ +#define EBI0_READ_DATA32(ebi, u32Addr) (*((volatile unsigned int *)((((ebi)==EBI_S)? EBI_BANK0_BASE_ADDR:EBI_BANK0_BASE_ADDR_NS)+(u32Addr)))) + +/** + * @brief Write 32-bit data to EBI bank0 + * + * @param[in] ebi The pointer of EBI module. + * @param[in] u32Addr The data address on EBI bank0. + * @param[in] u32Data Specify data to be written. + * + * @return None + * + * @details This macro is used to write 32-bit data to specify address on EBI bank0. + * \hideinitializer + */ +#define EBI0_WRITE_DATA32(ebi, u32Addr, u32Data) (*((volatile unsigned int *)((((ebi)==EBI_S)? EBI_BANK0_BASE_ADDR:EBI_BANK0_BASE_ADDR_NS)+(u32Addr))) = (u32Data)) + +/** + * @brief Read 8-bit data on EBI bank1 + * + * @param[in] ebi The pointer of EBI module. + * @param[in] u32Addr The data address on EBI bank1. + * + * @return 8-bit Data + * + * @details This macro is used to read 8-bit data from specify address on EBI bank1. + * \hideinitializer + */ +#define EBI1_READ_DATA8(ebi, u32Addr) (*((volatile unsigned char *)((((ebi)==EBI_S)? EBI_BANK1_BASE_ADDR:EBI_BANK1_BASE_ADDR_NS)+(u32Addr)))) + +/** + * @brief Write 8-bit data to EBI bank1 + * + * @param[in] ebi The pointer of EBI module. + * @param[in] u32Addr The data address on EBI bank1. + * @param[in] u32Data Specify data to be written. + * + * @return None + * + * @details This macro is used to write 8-bit data to specify address on EBI bank1. + * \hideinitializer + */ +#define EBI1_WRITE_DATA8(ebi, u32Addr, u32Data) (*((volatile unsigned char *)((((ebi)==EBI_S)? EBI_BANK1_BASE_ADDR:EBI_BANK1_BASE_ADDR_NS)+(u32Addr))) = (u32Data)) + +/** + * @brief Read 16-bit data on EBI bank1 + * + * @param[in] ebi The pointer of EBI module. + * @param[in] u32Addr The data address on EBI bank1. + * + * @return 16-bit Data + * + * @details This macro is used to read 16-bit data from specify address on EBI bank1. + * \hideinitializer + */ +#define EBI1_READ_DATA16(ebi, u32Addr) (*((volatile unsigned short *)((((ebi)==EBI_S)? EBI_BANK1_BASE_ADDR:EBI_BANK1_BASE_ADDR_NS)+(u32Addr)))) + +/** + * @brief Write 16-bit data to EBI bank1 + * + * @param[in] ebi The pointer of EBI module. + * @param[in] u32Addr The data address on EBI bank1. + * @param[in] u32Data Specify data to be written. + * + * @return None + * + * @details This macro is used to write 16-bit data to specify address on EBI bank1. + * \hideinitializer + */ +#define EBI1_WRITE_DATA16(ebi, u32Addr, u32Data) (*((volatile unsigned short *)((((ebi)==EBI_S)? EBI_BANK1_BASE_ADDR:EBI_BANK1_BASE_ADDR_NS)+(u32Addr))) = (u32Data)) + +/** + * @brief Read 32-bit data on EBI bank1 + * + * @param[in] ebi The pointer of EBI module. + * @param[in] u32Addr The data address on EBI bank1. + * + * @return 32-bit Data + * + * @details This macro is used to read 32-bit data from specify address on EBI bank1. + * \hideinitializer + */ +#define EBI1_READ_DATA32(ebi, u32Addr) (*((volatile unsigned int *)((((ebi)==EBI_S)? EBI_BANK1_BASE_ADDR:EBI_BANK1_BASE_ADDR_NS)+(u32Addr)))) + +/** + * @brief Write 32-bit data to EBI bank1 + * + * @param[in] ebi The pointer of EBI module. + * @param[in] u32Addr The data address on EBI bank1. + * @param[in] u32Data Specify data to be written. + * + * @return None + * + * @details This macro is used to write 32-bit data to specify address on EBI bank1. + * \hideinitializer + */ +#define EBI1_WRITE_DATA32(ebi, u32Addr, u32Data) (*((volatile unsigned int *)((((ebi)==EBI_S)? EBI_BANK1_BASE_ADDR:EBI_BANK1_BASE_ADDR_NS)+(u32Addr))) = (u32Data)) + +/** + * @brief Read 8-bit data on EBI bank2 + * + * @param[in] ebi The pointer of EBI module. + * @param[in] u32Addr The data address on EBI bank2. + * + * @return 8-bit Data + * + * @details This macro is used to read 8-bit data from specify address on EBI bank2. + * \hideinitializer + */ +#define EBI2_READ_DATA8(ebi, u32Addr) (*((volatile unsigned char *)((((ebi)==EBI_S)? EBI_BANK2_BASE_ADDR:EBI_BANK2_BASE_ADDR_NS)+(u32Addr)))) + +/** + * @brief Write 8-bit data to EBI bank2 + * + * @param[in] ebi The pointer of EBI module. + * @param[in] u32Addr The data address on EBI bank2. + * @param[in] u32Data Specify data to be written. + * + * @return None + * + * @details This macro is used to write 8-bit data to specify address on EBI bank2. + * \hideinitializer + */ +#define EBI2_WRITE_DATA8(ebi, u32Addr, u32Data) (*((volatile unsigned char *)((((ebi)==EBI_S)? EBI_BANK2_BASE_ADDR:EBI_BANK2_BASE_ADDR_NS)+(u32Addr))) = (u32Data)) + +/** + * @brief Read 16-bit data on EBI bank2 + * + * @param[in] ebi The pointer of EBI module. + * @param[in] u32Addr The data address on EBI bank2. + * + * @return 16-bit Data + * + * @details This macro is used to read 16-bit data from specify address on EBI bank2. + */ +#define EBI2_READ_DATA16(ebi, u32Addr) (*((volatile unsigned short *)((((ebi)==EBI_S)? EBI_BANK2_BASE_ADDR:EBI_BANK2_BASE_ADDR_NS)+(u32Addr)))) + +/** + * @brief Write 16-bit data to EBI bank2 + * + * @param[in] ebi The pointer of EBI module. + * @param[in] u32Addr The data address on EBI bank2. + * @param[in] u32Data Specify data to be written. + * + * @return None + * + * @details This macro is used to write 16-bit data to specify address on EBI bank2. + * \hideinitializer + */ +#define EBI2_WRITE_DATA16(ebi, u32Addr, u32Data) (*((volatile unsigned short *)((((ebi)==EBI_S)? EBI_BANK2_BASE_ADDR:EBI_BANK2_BASE_ADDR_NS)+(u32Addr))) = (u32Data)) + +/** + * @brief Read 32-bit data on EBI bank2 + * + * @param[in] ebi The pointer of EBI module. + * @param[in] u32Addr The data address on EBI bank2. + * + * @return 32-bit Data + * + * @details This macro is used to read 32-bit data from specify address on EBI bank2. + * \hideinitializer + */ +#define EBI2_READ_DATA32(ebi, u32Addr) (*((volatile unsigned int *)((((ebi)==EBI_S)? EBI_BANK2_BASE_ADDR:EBI_BANK2_BASE_ADDR_NS)+(u32Addr)))) +/** + * @brief Write 32-bit data to EBI bank2 + * + * @param[in] ebi The pointer of EBI module. + * @param[in] u32Addr The data address on EBI bank2. + * @param[in] u32Data Specify data to be written. + * + * @return None + * + * @details This macro is used to write 32-bit data to specify address on EBI bank2. + * \hideinitializer + */ +#define EBI2_WRITE_DATA32(ebi, u32Addr, u32Data) (*((volatile unsigned int *)((((ebi)==EBI_S)? EBI_BANK2_BASE_ADDR:EBI_BANK2_BASE_ADDR_NS)+(u32Addr))) = (u32Data)) + +/** + * @brief Enable EBI Write Buffer + * + * @param[in] ebi The pointer of EBI module. + * + * @return None + * + * @details This macro is used to improve EBI write operation for all EBI banks. + * \hideinitializer + */ +#define EBI_ENABLE_WRITE_BUFFER(ebi) ((ebi)->CTL0 |= EBI_CTL_WBUFEN_Msk) + +/** + * @brief Disable EBI Write Buffer + * + * @param[in] ebi The pointer of EBI module. + * + * @return None + * + * @details This macro is used to disable EBI write buffer function. + * \hideinitializer + */ +#define EBI_DISABLE_WRITE_BUFFER(ebi) ((ebi)->CTL0 &= ~EBI_CTL_WBUFEN_Msk) + +void EBI_Open(uint32_t u32Bank, uint32_t u32DataWidth, uint32_t u32TimingClass, uint32_t u32BusMode, uint32_t u32CSActiveLevel); +void EBI_Close(uint32_t u32Bank); +void EBI_SetBusTiming(uint32_t u32Bank, uint32_t u32TimingConfig, uint32_t u32MclkDiv); + +/**@}*/ /* end of group EBI_EXPORTED_FUNCTIONS */ + +/**@}*/ /* end of group EBI_Driver */ + +/**@}*/ /* end of group Standard_Driver */ + +#ifdef __cplusplus +} +#endif + +#endif /* __NU_EBI_H__ */ diff --git a/Ubiquitous/XiZi/board/nuvoton-m2354/third_party_driver/include/Drivers/nu_ecap.h b/Ubiquitous/XiZi/board/nuvoton-m2354/third_party_driver/include/Drivers/nu_ecap.h new file mode 100644 index 0000000..16abdae --- /dev/null +++ b/Ubiquitous/XiZi/board/nuvoton-m2354/third_party_driver/include/Drivers/nu_ecap.h @@ -0,0 +1,458 @@ +/**************************************************************************//** + * @file nu_ecap.h + * @version V3.00 + + * @brief EnHanced Input Capture Timer(ECAP) driver header file + * + * @copyright SPDX-License-Identifier: Apache-2.0 + * @copyright Copyright (C) 2020 Nuvoton Technology Corp. All rights reserved. +*****************************************************************************/ +#ifndef __NU_ECAP_H__ +#define __NU_ECAP_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + + + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup ECAP_Driver ECAP Driver + @{ +*/ + +/** @addtogroup ECAP_EXPORTED_CONSTANTS ECAP Exported Constants + @{ +*/ + +#define ECAP_IC0 (0UL) /*!< ECAP IC0 Unit \hideinitializer */ +#define ECAP_IC1 (1UL) /*!< ECAP IC1 Unit \hideinitializer */ +#define ECAP_IC2 (2UL) /*!< ECAP IC2 Unit \hideinitializer */ + +/*---------------------------------------------------------------------------------------------------------*/ +/* ECAP CTL0 constant definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define ECAP_NOISE_FILTER_CLKDIV_1 (0UL<CTL0 = ((ecap)->CTL0 & ~ECAP_CTL0_NFCLKSEL_Msk)|(u32ClkSel)) + +/** + * @brief This macro is used to disable noise filter + * @param[in] ecap Specify ECAP port + * @return None + * @details This macro will disable the noise filter of input capture. + * \hideinitializer + */ +#define ECAP_NOISE_FILTER_DISABLE(ecap) ((ecap)->CTL0 |= ECAP_CTL0_CAPNFDIS_Msk) + +/** + * @brief This macro is used to enable noise filter + * @param[in] ecap Specify ECAP port + * @param[in] u32ClkSel Select noise filter clock divide number + * - \ref ECAP_NOISE_FILTER_CLKDIV_1 + * - \ref ECAP_NOISE_FILTER_CLKDIV_2 + * - \ref ECAP_NOISE_FILTER_CLKDIV_4 + * - \ref ECAP_NOISE_FILTER_CLKDIV_16 + * - \ref ECAP_NOISE_FILTER_CLKDIV_32 + * - \ref ECAP_NOISE_FILTER_CLKDIV_64 + * @return None + * @details This macro will enable the noise filter of input capture and set noise filter clock divide. + * \hideinitializer + */ +#define ECAP_NOISE_FILTER_ENABLE(ecap, u32ClkSel) ((ecap)->CTL0 = ((ecap)->CTL0 & ~(ECAP_CTL0_CAPNFDIS_Msk|ECAP_CTL0_NFCLKSEL_Msk))|(u32ClkSel)) + +/** + * @brief This macro is used to enable input channel unit + * @param[in] ecap Specify ECAP port + * @param[in] u32Mask The input channel mask + * - \ref ECAP_CTL0_IC0EN_Msk + * - \ref ECAP_CTL0_IC1EN_Msk + * - \ref ECAP_CTL0_IC2EN_Msk + * @return None + * @details This macro will enable the input channel_n to input capture. + * \hideinitializer + */ +#define ECAP_ENABLE_INPUT_CHANNEL(ecap, u32Mask) ((ecap)->CTL0 |= (u32Mask)) + +/** + * @brief This macro is used to disable input channel unit + * @param[in] ecap Specify ECAP port + * @param[in] u32Mask The input channel mask + * - \ref ECAP_CTL0_IC0EN_Msk + * - \ref ECAP_CTL0_IC1EN_Msk + * - \ref ECAP_CTL0_IC2EN_Msk + * @return None + * @details This macro will disable the input channel_n to input capture. + * \hideinitializer + */ +#define ECAP_DISABLE_INPUT_CHANNEL(ecap, u32Mask) ((ecap)->CTL0 &= ~(u32Mask)) + +/** + * @brief This macro is used to select input channel source + * @param[in] ecap Specify ECAP port + * @param[in] u32Index The input channel number + * - \ref ECAP_IC0 + * - \ref ECAP_IC1 + * - \ref ECAP_IC2 + * @param[in] u32Src The input source + * - \ref ECAP_CAP_INPUT_SRC_FROM_IC + * - \ref ECAP_CAP_INPUT_SRC_FROM_CH + * @return None + * @details This macro will select the input source from ICx, CHx. + * \hideinitializer + */ +#define ECAP_SEL_INPUT_SRC(ecap, u32Index, u32Src) ((ecap)->CTL0 = ((ecap)->CTL0 & ~(ECAP_CTL0_CAPSEL0_Msk<<((u32Index)<<1)))|(((u32Src)<CTL0 |= (u32Mask)) + +/** + * @brief This macro is used to disable input channel interrupt + * @param[in] ecap Specify ECAP port + * @param[in] u32Mask The input channel mask + * - \ref ECAP_IC0 + * - \ref ECAP_IC1 + * - \ref ECAP_IC2 + * @return None + * @details This macro will disable the input channel_n interrupt. + * \hideinitializer + */ +#define ECAP_DISABLE_INT(ecap, u32Mask) ((ecap)->CTL0 &= ~(u32Mask)) + +/** + * @brief This macro is used to enable input channel overflow interrupt + * @param[in] ecap Specify ECAP port + * @return None + * @details This macro will enable the input channel overflow interrupt. + * \hideinitializer + */ +#define ECAP_ENABLE_OVF_INT(ecap) ((ecap)->CTL0 |= ECAP_CTL0_OVIEN_Msk) + +/** + * @brief This macro is used to disable input channel overflow interrupt + * @param[in] ecap Specify ECAP port + * @return None + * @details This macro will disable the input channel overflow interrupt. + * \hideinitializer + */ +#define ECAP_DISABLE_OVF_INT(ecap) ((ecap)->CTL0 &= ~ECAP_CTL0_OVIEN_Msk) + +/** + * @brief This macro is used to enable input channel compare-match interrupt + * @param[in] ecap Specify ECAP port + * @return None + * @details This macro will enable the input channel compare-match interrupt. + * \hideinitializer + */ +#define ECAP_ENABLE_CMP_MATCH_INT(ecap) ((ecap)->CTL0 |= ECAP_CTL0_CMPIEN_Msk) + +/** + * @brief This macro is used to disable input channel compare-match interrupt + * @param[in] ecap Specify ECAP port + * @return None + * @details This macro will disable the input channel compare-match interrupt. + * \hideinitializer + */ +#define ECAP_DISABLE_CMP_MATCH_INT(ecap) ((ecap)->CTL0 &= ~ECAP_CTL0_CMPIEN_Msk) + +/** + * @brief This macro is used to start capture counter + * @param[in] ecap Specify ECAP port + * @return None + * @details This macro will start capture counter up-counting. + * \hideinitializer + */ +#define ECAP_CNT_START(ecap) ((ecap)->CTL0 |= ECAP_CTL0_CNTEN_Msk) + +/** + * @brief This macro is used to stop capture counter + * @param[in] ecap Specify ECAP port + * @return None + * @details This macro will stop capture counter up-counting. + * \hideinitializer + */ +#define ECAP_CNT_STOP(ecap) ((ecap)->CTL0 &= ~ECAP_CTL0_CNTEN_Msk) + +/** + * @brief This macro is used to set event to clear capture counter + * @param[in] ecap Specify ECAP port + * @param[in] u32Event The input channel number + * - \ref ECAP_CTL0_CMPCLREN_Msk + * - \ref ECAP_CTL1_CAP0RLDEN_Msk + * - \ref ECAP_CTL1_CAP1RLDEN_Msk + * - \ref ECAP_CTL1_CAP2RLDEN_Msk + * - \ref ECAP_CTL1_OVRLDEN_Msk + + * @return None + * @details This macro will enable and select compare or capture event that can clear capture counter. + * \hideinitializer + */ +#define ECAP_SET_CNT_CLEAR_EVENT(ecap, u32Event) do{ \ + if((u32Event) & ECAP_CTL0_CMPCLREN_Msk) \ + (ecap)->CTL0 |= ECAP_CTL0_CMPCLREN_Msk; \ + else \ + (ecap)->CTL0 &= ~ECAP_CTL0_CMPCLREN_Msk; \ + (ecap)->CTL1 = ((ecap)->CTL1 &(uint32_t)(~0xF00)) | ((u32Event) & 0xF00); \ + }while(0); + +/** + * @brief This macro is used to enable compare function + * @param[in] ecap Specify ECAP port + * @return None + * @details This macro will enable the compare function. + * \hideinitializer + */ +#define ECAP_ENABLE_CMP(ecap) ((ecap)->CTL0 |= ECAP_CTL0_CMPEN_Msk) + +/** + * @brief This macro is used to disable compare function + * @param[in] ecap Specify ECAP port + * @return None + * @details This macro will disable the compare function. + * \hideinitializer + */ +#define ECAP_DISABLE_CMP(ecap) ((ecap)->CTL0 &= ~ECAP_CTL0_CMPEN_Msk) + +/** + * @brief This macro is used to enable input capture function. + * @param[in] ecap Specify ECAP port + * @return None + * @details This macro will enable input capture timer/counter. + * \hideinitializer + */ +#define ECAP_ENABLE_CNT(ecap) ((ecap)->CTL0 |= ECAP_CTL0_CAPEN_Msk) + +/** + * @brief This macro is used to disable input capture function. + * @param[in] ecap Specify ECAP port + * @return None + * @details This macro will disable input capture timer/counter. + * \hideinitializer + */ +#define ECAP_DISABLE_CNT(ecap) ((ecap)->CTL0 &= ~ECAP_CTL0_CAPEN_Msk) + +/** + * @brief This macro is used to select input channel edge detection + * @param[in] ecap Specify ECAP port + * @param[in] u32Index The input channel number + * - \ref ECAP_IC0 + * - \ref ECAP_IC1 + * - \ref ECAP_IC2 + * @param[in] u32Edge The input source + * - \ref ECAP_RISING_EDGE + * - \ref ECAP_FALLING_EDGE + * - \ref ECAP_RISING_FALLING_EDGE + * @return None + * @details This macro will select input capture can detect falling edge, rising edge or either rising or falling edge change. + * \hideinitializer + */ +#define ECAP_SEL_CAPTURE_EDGE(ecap, u32Index, u32Edge) ((ecap)->CTL1 = ((ecap)->CTL1 & ~(ECAP_CTL1_EDGESEL0_Msk<<((u32Index)<<1)))|((u32Edge)<<((u32Index)<<1))) + +/** + * @brief This macro is used to select ECAP counter reload trigger source + * @param[in] ecap Specify ECAP port + * @param[in] u32TrigSrc The input source + * - \ref ECAP_CTL1_CAP0RLDEN_Msk + * - \ref ECAP_CTL1_CAP1RLDEN_Msk + * - \ref ECAP_CTL1_CAP2RLDEN_Msk + * - \ref ECAP_CTL1_OVRLDEN_Msk + * @return None + * @details This macro will select capture counter reload trigger source. + * \hideinitializer + */ +#define ECAP_SEL_RELOAD_TRIG_SRC(ecap, u32TrigSrc) ((ecap)->CTL1 = ((ecap)->CTL1 & ~0xF00)|(u32TrigSrc)) + +/** + * @brief This macro is used to select capture timer clock divide. + * @param[in] ecap Specify ECAP port + * @param[in] u32Clkdiv The input source + * - \ref ECAP_CAPTURE_TIMER_CLKDIV_1 + * - \ref ECAP_CAPTURE_TIMER_CLKDIV_4 + * - \ref ECAP_CAPTURE_TIMER_CLKDIV_16 + * - \ref ECAP_CAPTURE_TIMER_CLKDIV_32 + * - \ref ECAP_CAPTURE_TIMER_CLKDIV_64 + * - \ref ECAP_CAPTURE_TIMER_CLKDIV_96 + * - \ref ECAP_CAPTURE_TIMER_CLKDIV_112 + * - \ref ECAP_CAPTURE_TIMER_CLKDIV_128 + * @return None + * @details This macro will select capture timer clock has a pre-divider with eight divided option. + * \hideinitializer + */ +#define ECAP_SEL_TIMER_CLK_DIV(ecap, u32Clkdiv) ((ecap)->CTL1 = ((ecap)->CTL1 & ~ECAP_CTL1_CLKSEL_Msk)|(u32Clkdiv)) + +/** + * @brief This macro is used to select capture timer/counter clock source + * @param[in] ecap Specify ECAP port + * @param[in] u32ClkSrc The input source + * - \ref ECAP_CAPTURE_TIMER_CLK_SRC_CAP_CLK + * - \ref ECAP_CAPTURE_TIMER_CLK_SRC_CAP0 + * - \ref ECAP_CAPTURE_TIMER_CLK_SRC_CAP1 + * - \ref ECAP_CAPTURE_TIMER_CLK_SRC_CAP2 + * @return None + * @details This macro will select capture timer/clock clock source. + * \hideinitializer + */ +#define ECAP_SEL_TIMER_CLK_SRC(ecap, u32ClkSrc) ((ecap)->CTL1 = ((ecap)->CTL1 & ~ECAP_CTL1_CNTSRCSEL_Msk)|(u32ClkSrc)) + +/** + * @brief This macro is used to read input capture status + * @param[in] ecap Specify ECAP port + * @return Input capture status flags + * @details This macro will get the input capture interrupt status. + * \hideinitializer + */ +#define ECAP_GET_INT_STATUS(ecap) ((ecap)->STATUS) + +/** + * @brief This macro is used to get input channel interrupt flag + * @param[in] ecap Specify ECAP port + * @param[in] u32Mask The input channel mask + * - \ref ECAP_STATUS_CAPTF0_Msk + * - \ref ECAP_STATUS_CAPTF1_Msk + * - \ref ECAP_STATUS_CAPTF2_Msk + * - \ref ECAP_STATUS_CAPOVF_Msk + * - \ref ECAP_STATUS_CAPCMPF_Msk + * @return None + * @details This macro will write 1 to get the input channel_n interrupt flag. + * \hideinitializer + */ +#define ECAP_GET_CAPTURE_FLAG(ecap, u32Mask) (((ecap)->STATUS & (u32Mask))?1:0) + +/** + * @brief This macro is used to clear input channel interrupt flag + * @param[in] ecap Specify ECAP port + * @param[in] u32Mask The input channel mask + * - \ref ECAP_STATUS_CAPTF0_Msk + * - \ref ECAP_STATUS_CAPTF1_Msk + * - \ref ECAP_STATUS_CAPTF2_Msk + * - \ref ECAP_STATUS_CAPOVF_Msk + * - \ref ECAP_STATUS_CAPCMPF_Msk + * @return None + * @details This macro will write 1 to clear the input channel_n interrupt flag. + * \hideinitializer + */ +#define ECAP_CLR_CAPTURE_FLAG(ecap, u32Mask) ((ecap)->STATUS = (u32Mask)) + +/** + * @brief This macro is used to set input capture counter value + * @param[in] ecap Specify ECAP port + * @param[in] u32Val Counter value + * @return None + * @details This macro will set a counter value of input capture. + * \hideinitializer + */ +#define ECAP_SET_CNT_VALUE(ecap, u32Val) ((ecap)->CNT = (u32Val)) + +/** + * @brief This macro is used to get input capture counter value + * @param[in] ecap Specify ECAP port + * @return Capture counter value + * @details This macro will get a counter value of input capture. + * \hideinitializer + */ +#define ECAP_GET_CNT_VALUE(ecap) ((ecap)->CNT) + +/** + * @brief This macro is used to get input capture counter hold value + * @param[in] ecap Specify ECAP port + * @param[in] u32Index The input channel number + * - \ref ECAP_IC0 + * - \ref ECAP_IC1 + * - \ref ECAP_IC2 + * @return Capture counter hold value + * @details This macro will get a hold value of input capture channel_n. + * \hideinitializer + */ +#define ECAP_GET_CNT_HOLD_VALUE(ecap, u32Index) (*(__IO uint32_t *) (&((ecap)->HLD0) + (u32Index))) + +/** + * @brief This macro is used to set input capture counter compare value + * @param[in] ecap Specify ECAP port + * @param[in] u32Val Input capture compare value + * @return None + * @details This macro will set a compare value of input capture counter. + * \hideinitializer + */ +#define ECAP_SET_CNT_CMP(ecap, u32Val) ((ecap)->CNTCMP = (u32Val)) + +void ECAP_Open(ECAP_T* ecap, uint32_t u32FuncMask); +void ECAP_Close(ECAP_T* ecap); +void ECAP_EnableINT(ECAP_T* ecap, uint32_t u32Mask); +void ECAP_DisableINT(ECAP_T* ecap, uint32_t u32Mask); +/**@}*/ /* end of group ECAP_EXPORTED_FUNCTIONS */ + +/**@}*/ /* end of group ECAP_Driver */ + +/**@}*/ /* end of group Standard_Driver */ + +#ifdef __cplusplus +} +#endif + +#endif /*__NU_ECAP_H__*/ diff --git a/Ubiquitous/XiZi/board/nuvoton-m2354/third_party_driver/include/Drivers/nu_epwm.h b/Ubiquitous/XiZi/board/nuvoton-m2354/third_party_driver/include/Drivers/nu_epwm.h new file mode 100644 index 0000000..5d7d7a3 --- /dev/null +++ b/Ubiquitous/XiZi/board/nuvoton-m2354/third_party_driver/include/Drivers/nu_epwm.h @@ -0,0 +1,650 @@ +/**************************************************************************//** + * @file nu_epwm.h + * @version V3.00 + * @brief M2354 series EPWM driver header file + * + * @copyright SPDX-License-Identifier: Apache-2.0 + * @copyright Copyright (C) 2020 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ +#ifndef __NU_EPWM_H__ +#define __NU_EPWM_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup EPWM_Driver EPWM Driver + @{ +*/ + +/** @addtogroup EPWM_EXPORTED_CONSTANTS EPWM Exported Constants + @{ +*/ +#define EPWM_CHANNEL_NUM (6UL) /*!< EPWM channel number */ +#define EPWM_CH_0_MASK (0x1UL) /*!< EPWM channel 0 mask \hideinitializer */ +#define EPWM_CH_1_MASK (0x2UL) /*!< EPWM channel 1 mask \hideinitializer */ +#define EPWM_CH_2_MASK (0x4UL) /*!< EPWM channel 2 mask \hideinitializer */ +#define EPWM_CH_3_MASK (0x8UL) /*!< EPWM channel 3 mask \hideinitializer */ +#define EPWM_CH_4_MASK (0x10UL) /*!< EPWM channel 4 mask \hideinitializer */ +#define EPWM_CH_5_MASK (0x20UL) /*!< EPWM channel 5 mask \hideinitializer */ + +/*---------------------------------------------------------------------------------------------------------*/ +/* Counter Type Constant Definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define EPWM_UP_COUNTER (0UL) /*!< Up counter type */ +#define EPWM_DOWN_COUNTER (1UL) /*!< Down counter type */ +#define EPWM_UP_DOWN_COUNTER (2UL) /*!< Up-Down counter type */ + +/*---------------------------------------------------------------------------------------------------------*/ +/* Aligned Type Constant Definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define EPWM_EDGE_ALIGNED (1UL) /*!< EPWM working in edge aligned type(down count) */ +#define EPWM_CENTER_ALIGNED (2UL) /*!< EPWM working in center aligned type */ + +/*---------------------------------------------------------------------------------------------------------*/ +/* Output Level Constant Definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define EPWM_OUTPUT_NOTHING (0UL) /*!< EPWM output nothing */ +#define EPWM_OUTPUT_LOW (1UL) /*!< EPWM output low */ +#define EPWM_OUTPUT_HIGH (2UL) /*!< EPWM output high */ +#define EPWM_OUTPUT_TOGGLE (3UL) /*!< EPWM output toggle */ + +/*---------------------------------------------------------------------------------------------------------*/ +/* Synchronous Start Function Control Constant Definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define EPWM_SSCTL_SSRC_EPWM0 (0UL<CTL1 = (epwm)->CTL1 | (0x7ul<CTL1 = (epwm)->CTL1 & ~(0x7ul<CTL0 = (epwm)->CTL0 | EPWM_CTL0_GROUPEN_Msk) + +/** + * @brief This macro disable group mode + * @param[in] epwm The pointer of the specified EPWM module + * @return None + * @details This macro is used to disable group mode of EPWM module. + * \hideinitializer + */ +#define EPWM_DISABLE_GROUP_MODE(epwm) ((epwm)->CTL0 = (epwm)->CTL0 & ~EPWM_CTL0_GROUPEN_Msk) + +/** + * @brief Enable timer synchronous start counting function of specified channel(s) + * @param[in] epwm The pointer of the specified EPWM module + * @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel + * Bit 0 represents channel 0, bit 1 represents channel 1... + * @param[in] u32SyncSrc Synchronous start source selection, valid values are: + * - \ref EPWM_SSCTL_SSRC_EPWM0 + * - \ref EPWM_SSCTL_SSRC_EPWM1 + * - \ref EPWM_SSCTL_SSRC_BPWM0 + * - \ref EPWM_SSCTL_SSRC_BPWM1 + * @return None + * @details This macro is used to enable timer synchronous start counting function of specified channel(s). + * \hideinitializer + */ +#define EPWM_ENABLE_TIMER_SYNC(epwm, u32ChannelMask, u32SyncSrc) ((epwm)->SSCTL = ((epwm)->SSCTL & ~EPWM_SSCTL_SSRC_Msk) | (u32SyncSrc) | (u32ChannelMask)) + +/** + * @brief Disable timer synchronous start counting function of specified channel(s) + * @param[in] epwm The pointer of the specified EPWM module + * @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel + * Bit 0 represents channel 0, bit 1 represents channel 1... + * @return None + * @details This macro is used to disable timer synchronous start counting function of specified channel(s). + * \hideinitializer + */ +#define EPWM_DISABLE_TIMER_SYNC(epwm, u32ChannelMask) \ + do{ \ + int i;\ + for(i = 0; i < 6; i++) { \ + if((u32ChannelMask) & (1UL << i)) \ + { \ + (epwm)->SSCTL &= ~(1UL << i); \ + } \ + } \ + }while(0) + +/** + * @brief This macro enable EPWM counter synchronous start counting function. + * @param[in] epwm The pointer of the specified EPWM module + * @return None + * @details This macro is used to make selected EPWM0 and EPWM1 channel(s) start counting at the same time. + * To configure synchronous start counting channel(s) by EPWM_ENABLE_TIMER_SYNC() and EPWM_DISABLE_TIMER_SYNC(). + * \hideinitializer + */ +#define EPWM_TRIGGER_SYNC_START(epwm) ((epwm)->SSTRG = EPWM_SSTRG_CNTSEN_Msk) + +/** + * @brief This macro enable output inverter of specified channel(s) + * @param[in] epwm The pointer of the specified EPWM module + * @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel + * Bit 0 represents channel 0, bit 1 represents channel 1... + * @return None + * @details This macro is used to enable output inverter of specified channel(s). + * \hideinitializer + */ +#define EPWM_ENABLE_OUTPUT_INVERTER(epwm, u32ChannelMask) ((epwm)->POLCTL = (u32ChannelMask)) + +/** + * @brief This macro get captured rising data + * @param[in] epwm The pointer of the specified EPWM module + * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5 + * @return None + * @details This macro is used to get captured rising data of specified channel. + * \hideinitializer + */ +#define EPWM_GET_CAPTURE_RISING_DATA(epwm, u32ChannelNum) ((epwm)->CAPDAT[(u32ChannelNum)].RCAPDAT) + +/** + * @brief This macro get captured falling data + * @param[in] epwm The pointer of the specified EPWM module + * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5 + * @return None + * @details This macro is used to get captured falling data of specified channel. + * \hideinitializer + */ +#define EPWM_GET_CAPTURE_FALLING_DATA(epwm, u32ChannelNum) ((epwm)->CAPDAT[(u32ChannelNum)].FCAPDAT) + +/** + * @brief This macro mask output logic to high or low + * @param[in] epwm The pointer of the specified EPWM module + * @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel + * Bit 0 represents channel 0, bit 1 represents channel 1... + * @param[in] u32LevelMask Output logic to high or low + * @return None + * @details This macro is used to mask output logic to high or low of specified channel(s). + * @note If u32ChannelMask parameter is 0, then mask function will be disabled. + * \hideinitializer + */ +#define EPWM_MASK_OUTPUT(epwm, u32ChannelMask, u32LevelMask) \ + do{ \ + (epwm)->MSKEN = (u32ChannelMask); \ + (epwm)->MSK = (u32LevelMask); \ + }while(0) + +/** + * @brief This macro set the prescaler of the selected channel + * @param[in] epwm The pointer of the specified EPWM module + * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5 + * @param[in] u32Prescaler Clock prescaler of specified channel. Valid values are between 0 ~ 0xFFF + * @return None + * @details This macro is used to set the prescaler of specified channel. + * @note Every even channel N, and channel (N + 1) share a prescaler. So if channel 0 prescaler changed, channel 1 will also be affected. + * The clock of EPWM counter is divided by (u32Prescaler + 1). + * \hideinitializer + */ +#define EPWM_SET_PRESCALER(epwm, u32ChannelNum, u32Prescaler) ((epwm)->CLKPSC[(u32ChannelNum) >> 1] = (u32Prescaler)) + +/** + * @brief This macro get the prescaler of the selected channel + * @param[in] epwm The pointer of the specified EPWM module + * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5 + * @return Return Clock prescaler of specified channel. Valid values are between 0 ~ 0xFFF + * @details This macro is used to get the prescaler of specified channel. + * @note Every even channel N, and channel (N + 1) share a prescaler. So if channel 0 prescaler changed, channel 1 will also be affected. + * The clock of EPWM counter is divided by (u32Prescaler + 1). + * \hideinitializer + */ +#define EPWM_GET_PRESCALER(epwm, u32ChannelNum) ((epwm)->CLKPSC[(u32ChannelNum) >> 1U]) + +/** + * @brief This macro set the comparator of the selected channel + * @param[in] epwm The pointer of the specified EPWM module + * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5 + * @param[in] u32CMR Comparator of specified channel. Valid values are between 0~0xFFFF + * @return None + * @details This macro is used to set the comparator of specified channel. + * @note This new setting will take effect on next EPWM period. + * \hideinitializer + */ +#define EPWM_SET_CMR(epwm, u32ChannelNum, u32CMR) ((epwm)->CMPDAT[(u32ChannelNum)]= (u32CMR)) + +/** + * @brief This macro get the comparator of the selected channel + * @param[in] epwm The pointer of the specified EPWM module + * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5 + * @return Return the comparator of specified channel. Valid values are between 0~0xFFFF + * @details This macro is used to get the comparator of specified channel. + * \hideinitializer + */ +#define EPWM_GET_CMR(epwm, u32ChannelNum) ((epwm)->CMPDAT[(u32ChannelNum)]) + +/** + * @brief This macro set the free trigger comparator of the selected channel + * @param[in] epwm The pointer of the specified EPWM module + * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5 + * @param[in] u32FTCMR Free trigger comparator of specified channel. Valid values are between 0~0xFFFF + * @return None + * @details This macro is used to set the free trigger comparator of specified channel. + * @note This new setting will take effect on next EPWM period. + * \hideinitializer + */ +#define EPWM_SET_FTCMR(epwm, u32ChannelNum, u32FTCMR) (((epwm)->FTCMPDAT[((u32ChannelNum) >> 1U)]) = (u32FTCMR)) + +/** + * @brief This macro set the period of the selected channel + * @param[in] epwm The pointer of the specified EPWM module + * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5 + * @param[in] u32CNR Period of specified channel. Valid values are between 0~0xFFFF + * @return None + * @details This macro is used to set the period of specified channel. + * @note This new setting will take effect on next EPWM period. + * @note EPWM counter will stop if period length set to 0. + * \hideinitializer + */ +#define EPWM_SET_CNR(epwm, u32ChannelNum, u32CNR) ((epwm)->PERIOD[(u32ChannelNum)] = (u32CNR)) + +/** + * @brief This macro get the period of the selected channel + * @param[in] epwm The pointer of the specified EPWM module + * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5 + * @return Return the period of specified channel. Valid values are between 0~0xFFFF + * @details This macro is used to get the period of specified channel. + * \hideinitializer + */ +#define EPWM_GET_CNR(epwm, u32ChannelNum) ((epwm)->PERIOD[(u32ChannelNum)]) + +/** + * @brief This macro set the EPWM aligned type + * @param[in] epwm The pointer of the specified EPWM module + * @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel + * Bit 0 represents channel 0, bit 1 represents channel 1... + * @param[in] u32AlignedType EPWM aligned type, valid values are: + * - \ref EPWM_EDGE_ALIGNED + * - \ref EPWM_CENTER_ALIGNED + * @return None + * @details This macro is used to set the EPWM aligned type of specified channel(s). + * \hideinitializer + */ +#define EPWM_SET_ALIGNED_TYPE(epwm, u32ChannelMask, u32AlignedType) \ + do{ \ + uint32_t i; \ + for(i = 0UL; i < 6UL; i++) { \ + if((u32ChannelMask) & (1UL << i)) \ + { \ + (epwm)->CTL1 = (((epwm)->CTL1 & ~(3UL << (i << 1))) | ((u32AlignedType) << (i << 1))); \ + } \ + } \ + }while(0) + +/** + * @brief Set load window of window loading mode for specified channel(s) + * @param[in] epwm The pointer of the specified EPWM module + * @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel + * Bit 0 represents channel 0, bit 1 represents channel 1... + * @return None + * @details This macro is used to set load window of window loading mode for specified channel(s). + * \hideinitializer + */ +#define EPWM_SET_LOAD_WINDOW(epwm, u32ChannelMask) ((epwm)->LOAD |= (u32ChannelMask)) + +/** + * @brief Trigger synchronous event from specified channel(s) + * @param[in] epwm The pointer of the specified EPWM module + * @param[in] u32ChannelNum EPWM channel number. Valid values are 0, 2, 4 + * Bit 0 represents channel 0, bit 1 represents channel 2 and bit 2 represents channel 4 + * @return None + * @details This macro is used to trigger synchronous event from specified channel(s). + * \hideinitializer + */ +#define EPWM_TRIGGER_SYNC(epwm, u32ChannelNum) ((epwm)->SWSYNC |= (1U << ((u32ChannelNum) >> 1))) + +/** + * @brief Clear counter of specified channel(s) + * @param[in] epwm The pointer of the specified EPWM module + * @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel + * Bit 0 represents channel 0, bit 1 represents channel 1... + * @return None + * @details This macro is used to clear counter of specified channel(s). + * \hideinitializer + */ +#define EPWM_CLR_COUNTER(epwm, u32ChannelMask) ((epwm)->CNTCLR |= (u32ChannelMask)) + +/** + * @brief Set output level at zero, compare up, period(center) and compare down of specified channel(s) + * @param[in] epwm The pointer of the specified EPWM module + * @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel + * Bit 0 represents channel 0, bit 1 represents channel 1... + * @param[in] u32ZeroLevel output level at zero point, valid values are: + * - \ref EPWM_OUTPUT_NOTHING + * - \ref EPWM_OUTPUT_LOW + * - \ref EPWM_OUTPUT_HIGH + * - \ref EPWM_OUTPUT_TOGGLE + * @param[in] u32CmpUpLevel output level at compare up point, valid values are: + * - \ref EPWM_OUTPUT_NOTHING + * - \ref EPWM_OUTPUT_LOW + * - \ref EPWM_OUTPUT_HIGH + * - \ref EPWM_OUTPUT_TOGGLE + * @param[in] u32PeriodLevel output level at period(center) point, valid values are: + * - \ref EPWM_OUTPUT_NOTHING + * - \ref EPWM_OUTPUT_LOW + * - \ref EPWM_OUTPUT_HIGH + * - \ref EPWM_OUTPUT_TOGGLE + * @param[in] u32CmpDownLevel output level at compare down point, valid values are: + * - \ref EPWM_OUTPUT_NOTHING + * - \ref EPWM_OUTPUT_LOW + * - \ref EPWM_OUTPUT_HIGH + * - \ref EPWM_OUTPUT_TOGGLE + * @return None + * @details This macro is used to Set output level at zero, compare up, period(center) and compare down of specified channel(s). + * \hideinitializer + */ +#define EPWM_SET_OUTPUT_LEVEL(epwm, u32ChannelMask, u32ZeroLevel, u32CmpUpLevel, u32PeriodLevel, u32CmpDownLevel) \ + do{ \ + uint32_t i; \ + for(i = 0UL; i < 6UL; i++) { \ + if((u32ChannelMask) & (1UL << i)) { \ + (epwm)->WGCTL0 = (((epwm)->WGCTL0 & ~(3UL << (i << 1))) | ((u32ZeroLevel) << (i << 1))); \ + (epwm)->WGCTL0 = (((epwm)->WGCTL0 & ~(3UL << (EPWM_WGCTL0_PRDPCTL0_Pos + (i << 1)))) | ((u32PeriodLevel) << (EPWM_WGCTL0_PRDPCTL0_Pos + (i << 1)))); \ + (epwm)->WGCTL1 = (((epwm)->WGCTL1 & ~(3UL << (i << 1))) | ((u32CmpUpLevel) << (i << 1))); \ + (epwm)->WGCTL1 = (((epwm)->WGCTL1 & ~(3UL << (EPWM_WGCTL1_CMPDCTL0_Pos + (i << 1)))) | ((u32CmpDownLevel) << (EPWM_WGCTL1_CMPDCTL0_Pos + (i << 1)))); \ + } \ + } \ + }while(0) + +/** + * @brief Trigger brake event from specified channel(s) + * @param[in] epwm The pointer of the specified EPWM module + * @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel + * Bit 0 represents channel 0, bit 1 represents channel 2 and bit 2 represents channel 4 + * @param[in] u32BrakeType Type of brake trigger. + * - \ref EPWM_FB_EDGE + * - \ref EPWM_FB_LEVEL + * @return None + * @details This macro is used to trigger brake event from specified channel(s). + * \hideinitializer + */ +#define EPWM_TRIGGER_BRAKE(epwm, u32ChannelMask, u32BrakeType) ((epwm)->SWBRK |= ((u32ChannelMask) << (u32BrakeType))) + +/** + * @brief Set Dead zone clock source + * @param[in] epwm The pointer of the specified EPWM module + * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5 + * @param[in] u32AfterPrescaler Dead zone clock source is from prescaler output. Valid values are TRUE (after prescaler) or FALSE (before prescaler). + * @return None + * @details This macro is used to set Dead zone clock source. Every two channels share the same setting. + * @note The write-protection function should be disabled before using this function. + * \hideinitializer + */ +#define EPWM_SET_DEADZONE_CLK_SRC(epwm, u32ChannelNum, u32AfterPrescaler) \ + (((epwm)->DTCTL[(u32ChannelNum) >> 1]) = ((epwm)->DTCTL[(u32ChannelNum) >> 1] & ~EPWM_DTCTL0_1_DTCKSEL_Msk) | \ + ((u32AfterPrescaler) << EPWM_DTCTL0_1_DTCKSEL_Pos)) + +/*---------------------------------------------------------------------------------------------------------*/ +/* Define EPWM functions prototype */ +/*---------------------------------------------------------------------------------------------------------*/ +uint32_t EPWM_ConfigCaptureChannel(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32UnitTimeNsec, uint32_t u32CaptureEdge); +uint32_t EPWM_ConfigOutputChannel(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32Frequency, uint32_t u32DutyCycle); +void EPWM_Start(EPWM_T *epwm, uint32_t u32ChannelMask); +void EPWM_Stop(EPWM_T *epwm, uint32_t u32ChannelMask); +void EPWM_ForceStop(EPWM_T *epwm, uint32_t u32ChannelMask); +void EPWM_EnableADCTrigger(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32Condition); +void EPWM_DisableADCTrigger(EPWM_T *epwm, uint32_t u32ChannelNum); +int32_t EPWM_EnableADCTriggerPrescale(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32Prescale, uint32_t u32PrescaleCnt); +void EPWM_DisableADCTriggerPrescale(EPWM_T *epwm, uint32_t u32ChannelNum); +void EPWM_ClearADCTriggerFlag(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32Condition); +uint32_t EPWM_GetADCTriggerFlag(EPWM_T *epwm, uint32_t u32ChannelNum); +void EPWM_EnableDACTrigger(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32Condition); +void EPWM_DisableDACTrigger(EPWM_T *epwm, uint32_t u32ChannelNum); +void EPWM_ClearDACTriggerFlag(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32Condition); +uint32_t EPWM_GetDACTriggerFlag(EPWM_T *epwm, uint32_t u32ChannelNum); +void EPWM_EnableFaultBrake(EPWM_T *epwm, uint32_t u32ChannelMask, uint32_t u32LevelMask, uint32_t u32BrakeSource); +void EPWM_EnableCapture(EPWM_T *epwm, uint32_t u32ChannelMask); +void EPWM_DisableCapture(EPWM_T *epwm, uint32_t u32ChannelMask); +void EPWM_EnableOutput(EPWM_T *epwm, uint32_t u32ChannelMask); +void EPWM_DisableOutput(EPWM_T *epwm, uint32_t u32ChannelMask); +void EPWM_EnablePDMA(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32RisingFirst, uint32_t u32Mode); +void EPWM_DisablePDMA(EPWM_T *epwm, uint32_t u32ChannelNum); +void EPWM_EnableDeadZone(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32Duration); +void EPWM_DisableDeadZone(EPWM_T *epwm, uint32_t u32ChannelNum); +void EPWM_EnableCaptureInt(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32Edge); +void EPWM_DisableCaptureInt(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32Edge); +void EPWM_ClearCaptureIntFlag(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32Edge); +uint32_t EPWM_GetCaptureIntFlag(EPWM_T *epwm, uint32_t u32ChannelNum); +void EPWM_EnableDutyInt(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32IntDutyType); +void EPWM_DisableDutyInt(EPWM_T *epwm, uint32_t u32ChannelNum); +void EPWM_ClearDutyIntFlag(EPWM_T *epwm, uint32_t u32ChannelNum); +uint32_t EPWM_GetDutyIntFlag(EPWM_T *epwm, uint32_t u32ChannelNum); +void EPWM_EnableFaultBrakeInt(EPWM_T *epwm, uint32_t u32BrakeSource); +void EPWM_DisableFaultBrakeInt(EPWM_T *epwm, uint32_t u32BrakeSource); +void EPWM_ClearFaultBrakeIntFlag(EPWM_T *epwm, uint32_t u32BrakeSource); +uint32_t EPWM_GetFaultBrakeIntFlag(EPWM_T *epwm, uint32_t u32BrakeSource); +void EPWM_EnablePeriodInt(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32IntPeriodType); +void EPWM_DisablePeriodInt(EPWM_T *epwm, uint32_t u32ChannelNum); +void EPWM_ClearPeriodIntFlag(EPWM_T *epwm, uint32_t u32ChannelNum); +uint32_t EPWM_GetPeriodIntFlag(EPWM_T *epwm, uint32_t u32ChannelNum); +void EPWM_EnableZeroInt(EPWM_T *epwm, uint32_t u32ChannelNum); +void EPWM_DisableZeroInt(EPWM_T *epwm, uint32_t u32ChannelNum); +void EPWM_ClearZeroIntFlag(EPWM_T *epwm, uint32_t u32ChannelNum); +uint32_t EPWM_GetZeroIntFlag(EPWM_T *epwm, uint32_t u32ChannelNum); +void EPWM_EnableAcc(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32IntFlagCnt, uint32_t u32IntAccSrc); +void EPWM_DisableAcc(EPWM_T *epwm, uint32_t u32ChannelNum); +void EPWM_EnableAccInt(EPWM_T *epwm, uint32_t u32ChannelNum); +void EPWM_DisableAccInt(EPWM_T *epwm, uint32_t u32ChannelNum); +void EPWM_ClearAccInt(EPWM_T *epwm, uint32_t u32ChannelNum); +uint32_t EPWM_GetAccInt(EPWM_T *epwm, uint32_t u32ChannelNum); +void EPWM_EnableAccPDMA(EPWM_T *epwm, uint32_t u32ChannelNum); +void EPWM_DisableAccPDMA(EPWM_T *epwm, uint32_t u32ChannelNum); +void EPWM_EnableAccStopMode(EPWM_T *epwm, uint32_t u32ChannelNum); +void EPWM_DisableAccStopMode(EPWM_T *epwm, uint32_t u32ChannelNum); +void EPWM_ClearFTDutyIntFlag(EPWM_T *epwm, uint32_t u32ChannelNum); +uint32_t EPWM_GetFTDutyIntFlag(EPWM_T *epwm, uint32_t u32ChannelNum); +void EPWM_EnableLoadMode(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32LoadMode); +void EPWM_DisableLoadMode(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32LoadMode); +void EPWM_ConfigSyncPhase(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32SyncSrc, uint32_t u32Direction, uint32_t u32StartPhase); +void EPWM_EnableSyncPhase(EPWM_T *epwm, uint32_t u32ChannelMask); +void EPWM_DisableSyncPhase(EPWM_T *epwm, uint32_t u32ChannelMask); +void EPWM_EnableSyncNoiseFilter(EPWM_T *epwm, uint32_t u32ClkCnt, uint32_t u32ClkDivSel); +void EPWM_DisableSyncNoiseFilter(EPWM_T *epwm); +void EPWM_EnableSyncPinInverse(EPWM_T *epwm); +void EPWM_DisableSyncPinInverse(EPWM_T *epwm); +void EPWM_SetClockSource(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32ClkSrcSel); +void EPWM_EnableBrakeNoiseFilter(EPWM_T *epwm, uint32_t u32BrakePinNum, uint32_t u32ClkCnt, uint32_t u32ClkDivSel); +void EPWM_DisableBrakeNoiseFilter(EPWM_T *epwm, uint32_t u32BrakePinNum); +void EPWM_EnableBrakePinInverse(EPWM_T *epwm, uint32_t u32BrakePinNum); +void EPWM_DisableBrakePinInverse(EPWM_T *epwm, uint32_t u32BrakePinNum); +void EPWM_SetBrakePinSource(EPWM_T *epwm, uint32_t u32BrakePinNum, uint32_t u32SelAnotherModule); +void EPWM_SetLeadingEdgeBlanking(EPWM_T *epwm, uint32_t u32TrigSrcSel, uint32_t u32TrigType, uint32_t u32BlankingCnt, uint32_t u32BlankingEnable); +uint32_t EPWM_GetWrapAroundFlag(EPWM_T *epwm, uint32_t u32ChannelNum); +void EPWM_ClearWrapAroundFlag(EPWM_T *epwm, uint32_t u32ChannelNum); +void EPWM_EnableFaultDetect(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32AfterPrescaler, uint32_t u32ClkSel); +void EPWM_DisableFaultDetect(EPWM_T *epwm, uint32_t u32ChannelNum); +void EPWM_EnableFaultDetectOutput(EPWM_T *epwm, uint32_t u32ChannelNum); +void EPWM_DisableFaultDetectOutput(EPWM_T *epwm, uint32_t u32ChannelNum); +void EPWM_EnableFaultDetectDeglitch(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32DeglitchSmpCycle); +void EPWM_DisableFaultDetectDeglitch(EPWM_T *epwm, uint32_t u32ChannelNum); +void EPWM_EnableFaultDetectMask(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32MaskCnt); +void EPWM_DisableFaultDetectMask(EPWM_T *epwm, uint32_t u32ChannelNum); +void EPWM_EnableFaultDetectInt(EPWM_T *epwm, uint32_t u32ChannelNum); +void EPWM_DisableFaultDetectInt(EPWM_T *epwm, uint32_t u32ChannelNum); +void EPWM_ClearFaultDetectInt(EPWM_T *epwm, uint32_t u32ChannelNum); +uint32_t EPWM_GetFaultDetectInt(EPWM_T *epwm, uint32_t u32ChannelNum); + + +/**@}*/ /* end of group EPWM_EXPORTED_FUNCTIONS */ + +/**@}*/ /* end of group EPWM_Driver */ + +/**@}*/ /* end of group Standard_Driver */ + +#ifdef __cplusplus +} +#endif + +#endif /* __NU_EPWM_H__ */ + diff --git a/Ubiquitous/XiZi/board/nuvoton-m2354/third_party_driver/include/Drivers/nu_ewdt.h b/Ubiquitous/XiZi/board/nuvoton-m2354/third_party_driver/include/Drivers/nu_ewdt.h new file mode 100644 index 0000000..6e07dd6 --- /dev/null +++ b/Ubiquitous/XiZi/board/nuvoton-m2354/third_party_driver/include/Drivers/nu_ewdt.h @@ -0,0 +1,218 @@ +/**************************************************************************//** + * @file nu_ewdt.h + * @version V3.00 + * @brief Extra Watchdog Timer(EWDT) driver header file + * + * @copyright SPDX-License-Identifier: Apache-2.0 + * @copyright Copyright (C) 2020 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ +#ifndef __NU_EWDT_H__ +#define __NU_EWDT_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup EWDT_Driver EWDT Driver + @{ +*/ + +/** @addtogroup EWDT_EXPORTED_CONSTANTS EWDT Exported Constants + @{ +*/ +/*---------------------------------------------------------------------------------------------------------*/ +/* EWDT Time-out Interval Period Constant Definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define EWDT_TIMEOUT_2POW4 (0UL << EWDT_CTL_TOUTSEL_Pos) /*!< Setting EWDT time-out interval to 2^4 * EWDT clocks \hideinitializer */ +#define EWDT_TIMEOUT_2POW6 (1UL << EWDT_CTL_TOUTSEL_Pos) /*!< Setting EWDT time-out interval to 2^6 * EWDT clocks \hideinitializer */ +#define EWDT_TIMEOUT_2POW8 (2UL << EWDT_CTL_TOUTSEL_Pos) /*!< Setting EWDT time-out interval to 2^8 * EWDT clocks \hideinitializer */ +#define EWDT_TIMEOUT_2POW10 (3UL << EWDT_CTL_TOUTSEL_Pos) /*!< Setting EWDT time-out interval to 2^10 * EWDT clocks \hideinitializer */ +#define EWDT_TIMEOUT_2POW12 (4UL << EWDT_CTL_TOUTSEL_Pos) /*!< Setting EWDT time-out interval to 2^12 * EWDT clocks \hideinitializer */ +#define EWDT_TIMEOUT_2POW14 (5UL << EWDT_CTL_TOUTSEL_Pos) /*!< Setting EWDT time-out interval to 2^14 * EWDT clocks \hideinitializer */ +#define EWDT_TIMEOUT_2POW16 (6UL << EWDT_CTL_TOUTSEL_Pos) /*!< Setting EWDT time-out interval to 2^16 * EWDT clocks \hideinitializer */ +#define EWDT_TIMEOUT_2POW18 (7UL << EWDT_CTL_TOUTSEL_Pos) /*!< Setting EWDT time-out interval to 2^18 * EWDT clocks \hideinitializer */ +#define EWDT_TIMEOUT_2POW20 (8UL << EWDT_CTL_TOUTSEL_Pos) /*!< Setting EWDT time-out interval to 2^20 * EWDT clocks \hideinitializer */ + +/*---------------------------------------------------------------------------------------------------------*/ +/* EWDT Reset Delay Period Constant Definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define EWDT_RESET_DELAY_1026CLK (0UL << EWDT_ALTCTL_RSTDSEL_Pos) /*!< Setting EWDT reset delay period to 1026 * EWDT clocks \hideinitializer */ +#define EWDT_RESET_DELAY_130CLK (1UL << EWDT_ALTCTL_RSTDSEL_Pos) /*!< Setting EWDT reset delay period to 130 * EWDT clocks \hideinitializer */ +#define EWDT_RESET_DELAY_18CLK (2UL << EWDT_ALTCTL_RSTDSEL_Pos) /*!< Setting EWDT reset delay period to 18 * EWDT clocks \hideinitializer */ +#define EWDT_RESET_DELAY_3CLK (3UL << EWDT_ALTCTL_RSTDSEL_Pos) /*!< Setting EWDT reset delay period to 3 * EWDT clocks \hideinitializer */ + +/*---------------------------------------------------------------------------------------------------------*/ +/* EWDT Free Reset Counter Keyword Constant Definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define EWDT_RESET_COUNTER_KEYWORD (0x00005AA5UL) /*!< Fill this value to EWDT_RSTCNT register to free reset EWDT counter \hideinitializer */ + +/**@}*/ /* end of group EWDT_EXPORTED_CONSTANTS */ + + +/** @addtogroup EWDT_EXPORTED_FUNCTIONS EWDT Exported Functions + @{ +*/ + +/** + * @brief Clear EWDT Reset System Flag + * + * @param None + * + * @return None + * + * @details This macro clears EWDT time-out reset system flag. + * \hideinitializer + */ +#define EWDT_CLEAR_RESET_FLAG() (EWDT->CTL = (EWDT->CTL & ~(EWDT_CTL_IF_Msk | EWDT_CTL_WKF_Msk)) | EWDT_CTL_RSTF_Msk) + +/** + * @brief Clear EWDT Time-out Interrupt Flag + * + * @param None + * + * @return None + * + * @details This macro clears EWDT time-out interrupt flag. + * \hideinitializer + */ +#define EWDT_CLEAR_TIMEOUT_INT_FLAG() (EWDT->CTL = (EWDT->CTL & ~(EWDT_CTL_RSTF_Msk | EWDT_CTL_WKF_Msk)) | EWDT_CTL_IF_Msk) + +/** + * @brief Clear EWDT Wake-up Flag + * + * @param None + * + * @return None + * + * @details This macro clears EWDT time-out wake-up system flag. + * \hideinitializer + */ +#define EWDT_CLEAR_TIMEOUT_WAKEUP_FLAG() (EWDT->CTL = (EWDT->CTL & ~(EWDT_CTL_RSTF_Msk | EWDT_CTL_IF_Msk)) | EWDT_CTL_WKF_Msk) + +/** + * @brief Get EWDT Time-out Reset Flag + * + * @param None + * + * @retval 0 EWDT time-out reset system did not occur + * @retval 1 EWDT time-out reset system occurred + * + * @details This macro indicates system has been reset by EWDT time-out reset or not. + * \hideinitializer + */ +#define EWDT_GET_RESET_FLAG() ((EWDT->CTL & EWDT_CTL_RSTF_Msk)? 1UL : 0UL) + +/** + * @brief Get EWDT Time-out Interrupt Flag + * + * @param None + * + * @retval 0 EWDT time-out interrupt did not occur + * @retval 1 EWDT time-out interrupt occurred + * + * @details This macro indicates EWDT time-out interrupt occurred or not. + * \hideinitializer + */ +#define EWDT_GET_TIMEOUT_INT_FLAG() ((EWDT->CTL & EWDT_CTL_IF_Msk)? 1UL : 0UL) + +/** + * @brief Get EWDT Time-out Wake-up Flag + * + * @param None + * + * @retval 0 EWDT time-out interrupt does not cause CPU wake-up + * @retval 1 EWDT time-out interrupt event cause CPU wake-up + * + * @details This macro indicates EWDT time-out interrupt event has waked up system or not. + * \hideinitializer + */ +#define EWDT_GET_TIMEOUT_WAKEUP_FLAG() ((EWDT->CTL & EWDT_CTL_WKF_Msk)? 1UL : 0UL) + +/** + * @brief Reset EWDT Counter + * + * @param None + * + * @return None + * + * @details This macro is used to reset the internal 20-bit EWDT up counter value. + * @note If EWDT is activated and time-out reset system function is enabled also, user should \n + * reset the 20-bit EWDT up counter value to avoid generate EWDT time-out reset signal to \n + * reset system before the EWDT time-out reset delay period expires. + * \hideinitializer + */ +#define EWDT_RESET_COUNTER() (EWDT->RSTCNT = EWDT_RESET_COUNTER_KEYWORD) + + +/*---------------------------------------------------------------------------------------------------------*/ +/* static inline functions */ +/*---------------------------------------------------------------------------------------------------------*/ +/* Declare these inline functions here to avoid MISRA C 2004 rule 8.1 error */ +__STATIC_INLINE void EWDT_Close(void); +__STATIC_INLINE void EWDT_EnableInt(void); +__STATIC_INLINE void EWDT_DisableInt(void); + +/** + * @brief Stop EWDT Counting + * + * @param None + * + * @return None + * + * @details This function will stop EWDT counting and disable EWDT module. + */ +__STATIC_INLINE void EWDT_Close(void) +{ + EWDT->CTL = 0UL; + while((EWDT->CTL & EWDT_CTL_SYNC_Msk) == EWDT_CTL_SYNC_Msk) {} /* Wait disable WDTEN bit completed, it needs 2 * EWDT_CLK. */ +} + +/** + * @brief Enable EWDT Time-out Interrupt + * + * @param None + * + * @return None + * + * @details This function will enable the EWDT time-out interrupt function. + */ +__STATIC_INLINE void EWDT_EnableInt(void) +{ + EWDT->CTL |= EWDT_CTL_INTEN_Msk; +} + +/** + * @brief Disable EWDT Time-out Interrupt + * + * @param None + * + * @return None + * + * @details This function will disable the EWDT time-out interrupt function. + */ +__STATIC_INLINE void EWDT_DisableInt(void) +{ + /* Do not touch another write 1 clear bits */ + EWDT->CTL &= ~(EWDT_CTL_INTEN_Msk | EWDT_CTL_RSTF_Msk | EWDT_CTL_IF_Msk | EWDT_CTL_WKF_Msk); +} + +void EWDT_Open(uint32_t u32TimeoutInterval, uint32_t u32ResetDelay, uint32_t u32EnableReset, uint32_t u32EnableWakeup); + +/**@}*/ /* end of group WDT_EXPORTED_FUNCTIONS */ + +/**@}*/ /* end of group WDT_Driver */ + +/**@}*/ /* end of group Standard_Driver */ + +#ifdef __cplusplus +} +#endif + +#endif /* __NU_EWDT_H__ */ + diff --git a/Ubiquitous/XiZi/board/nuvoton-m2354/third_party_driver/include/Drivers/nu_ewwdt.h b/Ubiquitous/XiZi/board/nuvoton-m2354/third_party_driver/include/Drivers/nu_ewwdt.h new file mode 100644 index 0000000..a453e80 --- /dev/null +++ b/Ubiquitous/XiZi/board/nuvoton-m2354/third_party_driver/include/Drivers/nu_ewwdt.h @@ -0,0 +1,150 @@ +/**************************************************************************//** + * @file nu_ewwdt.h + * @version V3.00 + * @brief Extra Window Watchdog Timer(EWWDT) driver header file + * + * @copyright SPDX-License-Identifier: Apache-2.0 + * @copyright Copyright (C) 2020 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ +#ifndef __NU_EWWDT_H__ +#define __NU_EWWDT_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup EWWDT_Driver EWWDT Driver + @{ +*/ + +/** @addtogroup EWWDT_EXPORTED_CONSTANTS EWWDT Exported Constants + @{ +*/ +/*---------------------------------------------------------------------------------------------------------*/ +/* EWWDT Prescale Period Constant Definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define EWWDT_PRESCALER_1 (0 << EWWDT_CTL_PSCSEL_Pos) /*!< Select max time-out period to 1 * (64*EWWDT_CLK) \hideinitializer */ +#define EWWDT_PRESCALER_2 (1 << EWWDT_CTL_PSCSEL_Pos) /*!< Select max time-out period to 2 * (64*EWWDT_CLK) \hideinitializer */ +#define EWWDT_PRESCALER_4 (2 << EWWDT_CTL_PSCSEL_Pos) /*!< Select max time-out period to 4 * (64*EWWDT_CLK) \hideinitializer */ +#define EWWDT_PRESCALER_8 (3 << EWWDT_CTL_PSCSEL_Pos) /*!< Select max time-out period to 8 * (64*EWWDT_CLK) \hideinitializer */ +#define EWWDT_PRESCALER_16 (4 << EWWDT_CTL_PSCSEL_Pos) /*!< Select max time-out period to 16 * (64*EWWDT_CLK) \hideinitializer */ +#define EWWDT_PRESCALER_32 (5 << EWWDT_CTL_PSCSEL_Pos) /*!< Select max time-out period to 32 * (64*EWWDT_CLK) \hideinitializer */ +#define EWWDT_PRESCALER_64 (6 << EWWDT_CTL_PSCSEL_Pos) /*!< Select max time-out period to 64 * (64*EWWDT_CLK) \hideinitializer */ +#define EWWDT_PRESCALER_128 (7 << EWWDT_CTL_PSCSEL_Pos) /*!< Select max time-out period to 128 * (64*EWWDT_CLK) \hideinitializer */ +#define EWWDT_PRESCALER_192 (8 << EWWDT_CTL_PSCSEL_Pos) /*!< Select max time-out period to 192 * (64*EWWDT_CLK) \hideinitializer */ +#define EWWDT_PRESCALER_256 (9 << EWWDT_CTL_PSCSEL_Pos) /*!< Select max time-out period to 256 * (64*EWWDT_CLK) \hideinitializer */ +#define EWWDT_PRESCALER_384 (10 << EWWDT_CTL_PSCSEL_Pos) /*!< Select max time-out period to 384 * (64*EWWDT_CLK) \hideinitializer */ +#define EWWDT_PRESCALER_512 (11 << EWWDT_CTL_PSCSEL_Pos) /*!< Select max time-out period to 512 * (64*EWWDT_CLK) \hideinitializer */ +#define EWWDT_PRESCALER_768 (12 << EWWDT_CTL_PSCSEL_Pos) /*!< Select max time-out period to 768 * (64*EWWDT_CLK) \hideinitializer */ +#define EWWDT_PRESCALER_1024 (13 << EWWDT_CTL_PSCSEL_Pos) /*!< Select max time-out period to 1024 * (64*EWWDT_CLK) \hideinitializer */ +#define EWWDT_PRESCALER_1536 (14 << EWWDT_CTL_PSCSEL_Pos) /*!< Select max time-out period to 1536 * (64*EWWDT_CLK) \hideinitializer */ +#define EWWDT_PRESCALER_2048 (15 << EWWDT_CTL_PSCSEL_Pos) /*!< Select max time-out period to 2048 * (64*EWWDT_CLK) \hideinitializer */ + +/*---------------------------------------------------------------------------------------------------------*/ +/* EWWDT Reload Counter Keyword Constant Definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define EWWDT_RELOAD_WORD (0x00005AA5UL) /*!< Fill this value to EWWDT_RLDCNT register to reload EWWDT counter \hideinitializer */ + +/**@}*/ /* end of group EWWDT_EXPORTED_CONSTANTS */ + + +/** @addtogroup EWWDT_EXPORTED_FUNCTIONS EWWDT Exported Functions + @{ +*/ + +/** + * @brief Clear EWWDT Reset System Flag + * + * @param None + * + * @return None + * + * @details This macro is used to clear EWWDT time-out reset system flag. + * \hideinitializer + */ +#define EWWDT_CLEAR_RESET_FLAG() (EWWDT->STATUS = EWWDT_STATUS_WWDTRF_Msk) + +/** + * @brief Clear EWWDT Compared Match Interrupt Flag + * + * @param None + * + * @return None + * + * @details This macro is used to clear EWWDT compared match interrupt flag. + * \hideinitializer + */ +#define EWWDT_CLEAR_INT_FLAG() (EWWDT->STATUS = EWWDT_STATUS_WWDTIF_Msk) + +/** + * @brief Get EWWDT Reset System Flag + * + * @param None + * + * @retval 0 EWWDT time-out reset system did not occur + * @retval 1 EWWDT time-out reset system occurred + * + * @details This macro is used to indicate system has been reset by EWWDT time-out reset or not. + * \hideinitializer + */ +#define EWWDT_GET_RESET_FLAG() ((EWWDT->STATUS & EWWDT_STATUS_WWDTRF_Msk)? 1 : 0) + +/** + * @brief Get EWWDT Compared Match Interrupt Flag + * + * @param None + * + * @retval 0 EWWDT compare match interrupt did not occur + * @retval 1 EWWDT compare match interrupt occurred + * + * @details This macro is used to indicate EWWDT counter value matches CMPDAT value or not. + * \hideinitializer + */ +#define EWWDT_GET_INT_FLAG() ((EWWDT->STATUS & EWWDT_STATUS_WWDTIF_Msk)? 1 : 0) + +/** + * @brief Get EWWDT Counter + * + * @param None + * + * @return EWWDT Counter Value + * + * @details This macro reflects the current EWWDT counter value. + * \hideinitializer + */ +#define EWWDT_GET_COUNTER() (EWWDT->CNT) + +/** + * @brief Reload EWWDT Counter + * + * @param None + * + * @return None + * + * @details This macro is used to reload the EWWDT counter value to 0x3F. + * @note User can only write EWWDT_RLDCNT register to reload EWWDT counter value when current EWWDT counter value \n + * between 0 and CMPDAT value. If user writes EWWDT_RLDCNT when current EWWDT counter value is larger than CMPDAT, \n + * EWWDT reset signal will generate immediately to reset system. + * \hideinitializer + */ +#define EWWDT_RELOAD_COUNTER() (EWWDT->RLDCNT = EWWDT_RELOAD_WORD) + +void EWWDT_Open(uint32_t u32PreScale, uint32_t u32CmpValue, uint32_t u32EnableInt); + +/**@}*/ /* end of group EWWDT_EXPORTED_FUNCTIONS */ + +/**@}*/ /* end of group EWWDT_Driver */ + +/**@}*/ /* end of group Standard_Driver */ + +#ifdef __cplusplus +} +#endif + +#endif /* __NU_EWWDT_H__ */ diff --git a/Ubiquitous/XiZi/board/nuvoton-m2354/third_party_driver/include/Drivers/nu_fmc.h b/Ubiquitous/XiZi/board/nuvoton-m2354/third_party_driver/include/Drivers/nu_fmc.h new file mode 100644 index 0000000..98700d3 --- /dev/null +++ b/Ubiquitous/XiZi/board/nuvoton-m2354/third_party_driver/include/Drivers/nu_fmc.h @@ -0,0 +1,588 @@ +/**************************************************************************//** + * @file nu_fmc.h + * @version V3.0 + * $Revision: 2 $ + * $Date: 19/11/27 3:11p $ + * @brief M2355 Series Flash Memory Controller(FMC) driver header file + * + * @copyright SPDX-License-Identifier: Apache-2.0 + * @copyright Copyright (C) 2020 Nuvoton Technology Corp. All rights reserved. + ******************************************************************************/ +#ifndef __NU_FMC_H__ +#define __NU_FMC_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup FMC_Driver FMC Driver + @{ +*/ + +/** @addtogroup FMC_EXPORTED_CONSTANTS FMC Exported Constants + @{ +*/ + +/*---------------------------------------------------------------------------------------------------------*/ +/* Global constant definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define ISBEN 0UL +#define FMC_ISP ( (__PC() & 0x10000000) ? FMC_NS : FMC) + +/*---------------------------------------------------------------------------------------------------------*/ +/* Define Base Address */ +/*---------------------------------------------------------------------------------------------------------*/ +#define FMC_APROM_BASE 0x00000000UL /*!< APROM Base Address */ +#define FMC_APROM_END 0x00100000UL /*!< APROM end address */ +#define FMC_APROM_BANK0_END (FMC_APROM_END/2UL) /*!< APROM bank0 end address */ +#define FMC_LDROM_BASE 0x00100000UL /*!< LDROM Base Address */ +#define FMC_LDROM_END 0x00104000UL /*!< LDROM end address */ +#define FMC_DTFSH_BASE 0x00110000UL /*!< LDROM Base Address */ +#define FMC_DTFSH_END 0x00112000UL /*!< LDROM end address */ +#define FMC_XOM_BASE 0x00200000UL /*!< XOM Base Address */ +#define FMC_XOMR0_BASE 0x00200000UL /*!< XOMR 0 Base Address */ +#define FMC_XOMR1_BASE 0x00200010UL /*!< XOMR 1 Base Address */ +#define FMC_XOMR2_BASE 0x00200020UL /*!< XOMR 2 Base Address */ +#define FMC_XOMR3_BASE 0x00200030UL /*!< XOMR 3 Base Address */ +#define FMC_NSCBA_BASE 0x00210800UL /*!< Non-Secure base address */ +#define FMC_SCRLOCK_BASE 0x00610000UL /*!< Secure Region Lock base address */ +#define FMC_ARLOCK_BASE 0x00610008UL /*!< All Region Lock base address */ +#define FMC_CONFIG_BASE 0x00300000UL /*!< CONFIG Base Address */ +#define FMC_USER_CONFIG_0 0x00300000UL /*!< CONFIG 0 Address */ +#define FMC_USER_CONFIG_1 0x00300004UL /*!< CONFIG 1 Address */ +#define FMC_USER_CONFIG_2 0x00300008UL /*!< CONFIG 2 Address */ +#define FMC_USER_CONFIG_3 0x0030000CUL /*!< CONFIG 3 Address */ +#define FMC_OTP_BASE 0x00310000UL /*!< OTP flash base address */ + +#define FMC_FLASH_PAGE_SIZE 0x800UL /*!< Flash Page Size (2048 Bytes) */ +#define FMC_PAGE_ADDR_MASK 0xFFFFF800UL /*!< Flash page address mask */ +#define FMC_MULTI_WORD_PROG_LEN 512UL /*!< The maximum length of a multi-word program. */ + +#define FMC_APROM_SIZE FMC_APROM_END /*!< APROM Size */ +#define FMC_BANK_SIZE (FMC_APROM_SIZE/2UL) /*!< APROM Bank Size */ +#define FMC_LDROM_SIZE 0x4000UL /*!< LDROM Size (4 Kbytes) */ +#define FMC_OTP_ENTRY_CNT 256UL /*!< OTP entry number */ + +/*---------------------------------------------------------------------------------------------------------*/ +/* XOM region number constant definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define XOMR0 0UL /*!< XOM region 0 */ +#define XOMR1 1UL /*!< XOM region 1 */ +#define XOMR2 2UL /*!< XOM region 2 */ +#define XOMR3 3UL /*!< XOM region 3 */ + +/*---------------------------------------------------------------------------------------------------------*/ +/* ISPCTL constant definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define IS_BOOT_FROM_LDROM 0x1UL /*!< ISPCTL setting to select to boot from LDROM */ +#define IS_BOOT_FROM_APROM 0x0UL /*!< ISPCTL setting to select to boot from APROM */ + +/*---------------------------------------------------------------------------------------------------------*/ +/* ISPCMD constant definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define FMC_ISPCMD_READ 0x00UL /*!< ISP Command: Read Flash */ +#define FMC_ISPCMD_READ_UID 0x04UL /*!< ISP Command: Read Unique ID */ +#define FMC_ISPCMD_READ_ALL1 0x08UL /*!< ISP Command: Read all-one result */ +#define FMC_ISPCMD_READ_CID 0x0BUL /*!< ISP Command: Read Company ID */ +#define FMC_ISPCMD_READ_DID 0x0CUL /*!< ISP Command: Read Device ID */ +#define FMC_ISPCMD_READ_CKS 0x0DUL /*!< ISP Command: Read Checksum */ +#define FMC_ISPCMD_PROGRAM 0x21UL /*!< ISP Command: 32-bit Program Flash */ +#define FMC_ISPCMD_PAGE_ERASE 0x22UL /*!< ISP Command: Page Erase Flash */ +#define FMC_ISPCMD_BANK_ERASE 0x23UL /*!< ISP Command: Erase Flash bank 0 or 1 */ +#define FMC_ISPCMD_PROGRAM_MUL 0x27UL /*!< ISP Command: Flash Multi-Word Program */ +#define FMC_ISPCMD_RUN_ALL1 0x28UL /*!< ISP Command: Run all-one verification */ +#define FMC_ISPCMD_BANK_REMAP 0x2CUL /*!< ISP Command: Bank Remap */ +#define FMC_ISPCMD_RUN_CKS 0x2DUL /*!< ISP Command: Run Check Calculation */ +#define FMC_ISPCMD_VECMAP 0x2EUL /*!< ISP Command: Set vector mapping */ +#define FMC_ISPCMD_READ_64 0x40UL /*!< ISP Command: 64-bit read Flash */ +#define FMC_ISPCMD_PROGRAM_64 0x61UL /*!< ISP Command: 64-bit program Flash */ + +#define READ_ALLONE_YES 0xA11FFFFFUL /*!< Check-all-one result is all one. */ +#define READ_ALLONE_NOT 0xA1100000UL /*!< Check-all-one result is not all one. */ +#define READ_ALLONE_CMD_FAIL 0xFFFFFFFFUL /*!< Check-all-one command failed. */ + +/**@}*/ /* end of group FMC_EXPORTED_CONSTANTS */ + +/** @addtogroup FMC_EXPORTED_FUNCTIONS FMC Exported Functions + @{ +*/ + +/*---------------------------------------------------------------------------------------------------------*/ +/* FMC Macro Definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +/** + * @brief Enable ISP Function + * + * @param None + * + * @return None + * + * @details This function will set ISPEN bit of ISPCTL control register to enable ISP function. + * + */ +#define FMC_ENABLE_ISP() (FMC_ISP->ISPCTL |= FMC_ISPCTL_ISPEN_Msk) /*!< Enable ISP Function */ + +/** + * @brief Disable ISP Function + * + * @param None + * + * @return None + * + * @details This function will clear ISPEN bit of ISPCTL control register to disable ISP function. + * + */ +#define FMC_DISABLE_ISP() (FMC_ISP->ISPCTL &= ~FMC_ISPCTL_ISPEN_Msk) /*!< Disable ISP Function */ + +/** + * @brief Disable Non Secure ISP Function + * + * @param None + * + * @return None + * + * @details This function will clear ISPEN bit of ISPCTL control register to disable Non Secure ISP function. + * + */ + +#define FMC_ENABLE_LD_UPDATE() (FMC->ISPCTL |= FMC_ISPCTL_LDUEN_Msk) /*!< Enable LDROM Update Function */ + +/** + * @brief Disable LDROM Update Function + * + * @param None + * + * @return None + * + * @details This function will set ISPEN bit of ISPCTL control register to disable LDROM update function. + * + */ +#define FMC_DISABLE_LD_UPDATE() (FMC->ISPCTL &= ~FMC_ISPCTL_LDUEN_Msk) /*!< Disable LDROM Update Function */ + +/** + * @brief Enable User Configuration Update Function + * + * @param None + * + * @return None + * + * @details This function will set CFGUEN bit of ISPCTL control register to enable User Configuration update function. + * User needs to set CFGUEN bit before they can update User Configuration area. + * + */ +#define FMC_ENABLE_CFG_UPDATE() (FMC->ISPCTL |= FMC_ISPCTL_CFGUEN_Msk) /*!< Enable CONFIG Update Function */ + +/** + * @brief Disable User Configuration Update Function + * + * @param None + * + * @return None + * + * @details This function will clear CFGUEN bit of ISPCTL control register to disable User Configuration update function. + * + */ +#define FMC_DISABLE_CFG_UPDATE() (FMC->ISPCTL &= ~FMC_ISPCTL_CFGUEN_Msk) /*!< Disable CONFIG Update Function */ + + +/** + * @brief Enable APROM Update Function + * + * @param None + * + * @return None + * + * @details This function will set APUEN bit of ISPCTL control register to enable APROM update function. + * User needs to set APUEN bit before they can update APROM in APROM boot mode. + * + */ +#define FMC_ENABLE_AP_UPDATE() (FMC_ISP->ISPCTL |= FMC_ISPCTL_APUEN_Msk) /*!< Enable APROM Update Function */ + +/** + * @brief Disable APROM Update Function + * + * @param None + * + * @return None + * + * @details This function will clear APUEN bit of ISPCTL control register to disable APROM update function. + * + */ +#define FMC_DISABLE_AP_UPDATE() (FMC_ISP->ISPCTL &= ~FMC_ISPCTL_APUEN_Msk) /*!< Disable APROM Update Function */ + +/** + * @brief Get ISP Fail Flag + * + * @param None + * + * @return None + * + * @details This function is used to get ISP fail flag when do ISP actoin. + * + */ +#define FMC_GET_FAIL_FLAG() ((FMC_ISP->ISPCTL & FMC_ISPCTL_ISPFF_Msk) ? 1UL : 0UL) /*!< Get ISP fail flag */ + +/** + * @brief Clear ISP Fail Flag + * + * @param None + * + * @return None + * + * @details This function is used to clear ISP fail flag when ISP fail flag set. + * + */ +#define FMC_CLR_FAIL_FLAG() (FMC_ISP->ISPCTL |= FMC_ISPCTL_ISPFF_Msk) /*!< Clear ISP fail flag */ + +/** + * @brief Enable ISP Interrupt + * + * @param None + * + * @return None + * + * @details This function will enable ISP action interrupt. + * + */ +#define FMC_ENABLE_ISP_INT() (FMC_ISP->ISPCTL |= FMC_ISPCTL_INTEN_Msk) /*!< Enable ISP interrupt */ + +/** + * @brief Disable ISP Interrupt + * + * @param None + * + * @return None + * + * @details This function will disable ISP action interrupt. + * + */ +#define FMC_DISABLE_ISP_INT() (FMC_ISP->ISPCTL &= ~FMC_ISPCTL_INTEN_Msk) /*!< Disable ISP interrupt */ + +/** + * @brief Get ISP Interrupt Flag + * + * @param None + * + * @return None + * + * @details This function will get ISP action interrupt status + * + */ +#define FMC_GET_ISP_INT_FLAG() ((FMC_ISP->ISPSTS & FMC_ISPSTS_INTFLAG_Msk) ? 1UL : 0UL) /*!< Get ISP interrupt flag Status */ + +/** + * @brief Clear ISP Interrupt Flag + * + * @param None + * + * @return None + * + * @details This function will clear ISP interrupt flag + * + */ +#define FMC_CLEAR_ISP_INT_FLAG() (FMC_ISP->ISPSTS = FMC_ISPSTS_INTFLAG_Msk) /*!< Clear ISP interrupt flag*/ + +/** + * @brief Enable Data Flash Scrambling Function + * + * @param None + * + * @return None + * + * @details This function will set SCRAMEN bit of DFCTL control register to enable Data Flash Scrambling Function. + * + */ +#define FMC_ENABLE_SCRAMBLE() (FMC->DFCTL |= FMC_DFCTL_SCRAMEN_Msk) /*!< Enable Data Flash Scrambling Function */ + +/** + * @brief Disable Data Flash Scrambling Function + * + * @param None + * + * @return None + * + * @details This function will clear SCRAMEN bit of DFCTL control register to disable Data Flash Scrambling Function. + * + */ +#define FMC_DISABLE_SCRAMBLE() (FMC->DFCTL &= ~FMC_DFCTL_SCRAMEN_Msk) /*!< Disable Data Flash Scrambling Function */ + +/** + * @brief Enable Data Flash Silent Access Function + * + * @param None + * + * @return None + * + * @details This function will set SILENTEN bit of DFCTL control register to enable Data Flash Silent Access Function. + * + */ +#define FMC_ENABLE_SILENT() (FMC->DFCTL |= FMC_DFCTL_SILENTEN_Msk) /*!< Enable Data Flash Silent Access Function */ + +/** + * @brief Disable Data Flash Silent Access Function + * + * @param None + * + * @return None + * + * @details This function will clear SILENTEN bit of DFCTL control register to disable Data Flash Silent Access Function. + * + */ +#define FMC_DISABLE_SILENT() (FMC->DFCTL &= ~FMC_DFCTL_SILENTEN_Msk) /*!< Disable Data Flash Silent Access Function */ + +/** + * @brief Enable Data Flash Temper Attack Program Function + * + * @param None + * + * @return None + * + * @details This function will set TMPCLR bit of DFCTL control register to enable Data Flash Temper Attack Program Function. + * + */ +#define FMC_ENABLE_TMPCLR() (FMC->DFCTL |= FMC_DFCTL_TMPCLR_Msk) /*!< Enable Data Flash Temper Attack Program Function */ + +/** + * @brief Disable Data Flash Temper Attack Program Function + * + * @param None + * + * @return None + * + * @details This function will clear TMPCLR bit of DFCTL control register to disable Data Flash Temper Attack Program Function. + * + */ +#define FMC_DISABLE_TMPCLR() (FMC->DFCTL &= ~FMC_DFCTL_TMPCLR_Msk) /*!< Disable Data Flash Temper Attack Program Function */ + +/** + * @brief Get Data Flash Temper Attack Programming Done Flag + * + * @param None + * + * @return None + * + * @details This function will get Data Flash Temper Attack Programming Done flag + * + */ +#define FMC_GET_TMPCLRDONE_FLAG() ((FMC->DFSTS & FMC_DFSTS_TMPCLRDONE_Msk) ? 1UL : 0UL) /*!< Get Data Flash Temper Attack Programming Done Flag */ + +/** + * @brief Get Data Flash Temper Attack Programming Busy Flag + * + * @param None + * + * @return None + * + * @details This function will get Data Flash Temper Attack Programming Busy flag + * + */ +#define FMC_GET_TMPCLRBUSY_FLAG() ((FMC->DFSTS & FMC_DFSTS_TMPCLRBUSY_Msk) ? 1UL : 0UL) /*!< Get Data Flash Temper Attack Programming Busy Flag */ + +/** + * @brief Clear Data Flash Temper Attack Programming Done Flag + * + * @param None + * + * @return None + * + * @details This function will clear Data Flash Temper Attack Programming Done flag + * + */ +#define FMC_CLEAR_TMPCLRDONE_FLAG() (FMC->DFSTS |= FMC_DFSTS_TMPCLRDONE_Msk) /*!< Clear Data Flash Temper Attack Programming Done Flag */ + +/*---------------------------------------------------------------------------------------------------------*/ +/* inline functions */ +/*---------------------------------------------------------------------------------------------------------*/ +__STATIC_INLINE uint32_t FMC_ReadCID(void); +__STATIC_INLINE uint32_t FMC_ReadPID(void); +__STATIC_INLINE uint32_t FMC_ReadUID(uint8_t u8Index); +__STATIC_INLINE uint32_t FMC_ReadUCID(uint32_t u32Index); +__STATIC_INLINE void FMC_SetVectorPageAddr(uint32_t u32PageAddr); +__STATIC_INLINE uint32_t FMC_GetVECMAP(void); +__STATIC_INLINE void FMC_SetScrambleKey(uint32_t u32ScrambleKey); + +/** + * @brief Get current vector mapping address. + * + * @param None + * + * @return The current vector mapping address. + * + * @details To get VECMAP value which is the page address for remapping to vector page (0x0). + * + */ +__STATIC_INLINE uint32_t FMC_GetVECMAP(void) +{ + return (FMC->ISPSTS & FMC_ISPSTS_VECMAP_Msk); +} + +/** + * @brief Read company ID + * + * @param None + * + * @return The company ID (32-bit) + * + * @details The company ID of Nuvoton is fixed to be 0xDA + */ +__STATIC_INLINE uint32_t FMC_ReadCID(void) +{ + FMC_ISP->ISPCMD = FMC_ISPCMD_READ_CID; /* Set ISP Command Code */ + FMC_ISP->ISPADDR = 0x0u; /* Must keep 0x0 when read CID */ + FMC_ISP->ISPTRG = FMC_ISPTRG_ISPGO_Msk; /* Trigger to start ISP procedure */ +#if ISBEN + __ISB(); +#endif /* To make sure ISP/CPU be Synchronized */ + while(FMC_ISP->ISPTRG & FMC_ISPTRG_ISPGO_Msk) {} /* Waiting for ISP Done */ + + return FMC_ISP->ISPDAT; +} + +/** + * @brief Read product ID + * + * @param None + * + * @return The product ID (32-bit) + * + * @details This function is used to read product ID. + */ +__STATIC_INLINE uint32_t FMC_ReadPID(void) +{ + FMC_ISP->ISPCMD = FMC_ISPCMD_READ_DID; /* Set ISP Command Code */ + FMC_ISP->ISPADDR = 0x04u; /* Must keep 0x4 when read PID */ + FMC_ISP->ISPTRG = FMC_ISPTRG_ISPGO_Msk; /* Trigger to start ISP procedure */ +#if ISBEN + __ISB(); +#endif /* To make sure ISP/CPU be Synchronized */ + while(FMC_ISP->ISPTRG & FMC_ISPTRG_ISPGO_Msk) {} /* Waiting for ISP Done */ + + return FMC_ISP->ISPDAT; +} + + +/** + * @brief Read Unique ID + * + * @param[in] u8Index UID index. 0 = UID[31:0], 1 = UID[63:32], 2 = UID[95:64] + * + * @return The 32-bit unique ID data of specified UID index. + * + * @details To read out 96-bit Unique ID. + */ +__STATIC_INLINE uint32_t FMC_ReadUID(uint8_t u8Index) +{ + FMC_ISP->ISPCMD = FMC_ISPCMD_READ_UID; + FMC_ISP->ISPADDR = ((uint32_t)u8Index << 2u); + FMC_ISP->ISPDAT = 0u; + FMC_ISP->ISPTRG = 0x1u; +#if ISBEN + __ISB(); +#endif + while(FMC_ISP->ISPTRG) {} + + return FMC_ISP->ISPDAT; +} + +/** + * @brief To read UCID + * + * @param[in] u32Index Index of the UCID to read. u32Index must be 0, 1, 2, or 3. + * + * @return The UCID of specified index + * + * @details This function is used to read unique chip ID (UCID). + */ +__STATIC_INLINE uint32_t FMC_ReadUCID(uint32_t u32Index) +{ + FMC_ISP->ISPCMD = FMC_ISPCMD_READ_UID; /* Set ISP Command Code */ + FMC_ISP->ISPADDR = (0x04u * u32Index) + 0x10u; /* The UCID is at offset 0x10 with word alignment. */ + FMC_ISP->ISPTRG = FMC_ISPTRG_ISPGO_Msk; /* Trigger to start ISP procedure */ +#if ISBEN + __ISB(); +#endif /* To make sure ISP/CPU be Synchronized */ + while(FMC_ISP->ISPTRG & FMC_ISPTRG_ISPGO_Msk) {} /* Waiting for ISP Done */ + + return FMC_ISP->ISPDAT; +} + + +/** + * @brief Set vector mapping address + * + * @param[in] u32PageAddr The page address to remap to address 0x0. The address must be page alignment. + * + * @return To set VECMAP to remap specified page address to 0x0. + * + * @details This function is used to set VECMAP to map specified page to vector page (0x0). + */ +__STATIC_INLINE void FMC_SetVectorPageAddr(uint32_t u32PageAddr) +{ + FMC->ISPCMD = FMC_ISPCMD_VECMAP; /* Set ISP Command Code */ + FMC->ISPADDR = u32PageAddr; /* The address of specified page which will be map to address 0x0. It must be page alignment. */ + FMC->ISPTRG = 0x1u; /* Trigger to start ISP procedure */ +#if ISBEN + __ISB(); +#endif /* To make sure ISP/CPU be Synchronized */ + while(FMC->ISPTRG) {} /* Waiting for ISP Done */ +} + +/** + * @brief Set Data Flash scrambling key + * + * @param[in] u32ScramKey The value of scrambling key. + * + * @return NULL + * + * @details This function is used to set Data Flash scrambling key. + */ +__STATIC_INLINE void FMC_SetScrambleKey(uint32_t u32ScrambleKey) +{ + FMC->SCRKEY = u32ScrambleKey; +} + +/*---------------------------------------------------------------------------------------------------------*/ +/* Functions */ +/*---------------------------------------------------------------------------------------------------------*/ + +extern uint32_t FMC_CheckAllOne(uint32_t u32addr, uint32_t u32count); +extern void FMC_Close(void); +extern int32_t FMC_ConfigXOM(uint32_t xom_num, uint32_t xom_base, uint8_t xom_page); +extern int32_t FMC_Erase(uint32_t u32PageAddr); +extern int32_t FMC_EraseBank(uint32_t u32BankAddr); +extern int32_t FMC_EraseXOM(uint32_t xom_num); +extern uint32_t FMC_GetChkSum(uint32_t u32addr, uint32_t u32count); +extern int32_t FMC_IsOTPLocked(uint32_t otp_num); +extern int32_t FMC_GetXOMState(uint32_t xom_num); +extern int32_t FMC_LockOTP(uint32_t otp_num); +extern void FMC_Open(void); +extern uint32_t FMC_Read(uint32_t u32Addr); +extern int32_t FMC_Read64(uint32_t u32addr, uint32_t * u32data0, uint32_t * u32data1); +extern int32_t FMC_ReadOTP(uint32_t otp_num, uint32_t *low_word, uint32_t *high_word); +extern int32_t FMC_ReadConfig(uint32_t u32Config[], uint32_t u32Count); +extern void FMC_Write(uint32_t u32Addr, uint32_t u32Data); +extern int32_t FMC_Write8Bytes(uint32_t u32addr, uint32_t u32data0, uint32_t u32data1); +extern int32_t FMC_WriteConfig(uint32_t au32Config[], uint32_t u32Count); +extern int32_t FMC_WriteMultiple(uint32_t u32Addr, uint32_t pu32Buf[], uint32_t u32Len); +extern int32_t FMC_WriteOTP(uint32_t otp_num, uint32_t low_word, uint32_t high_word); +extern int32_t FMC_WriteMultipleA(uint32_t u32Addr, uint32_t pu32Buf[], uint32_t u32Len); +extern int32_t FMC_RemapBank(uint32_t u32Bank); + +/**@}*/ /* end of group FMC_EXPORTED_FUNCTIONS */ + +/**@}*/ /* end of group FMC_Driver */ + +/**@}*/ /* end of group Standard_Driver */ + +#ifdef __cplusplus +} +#endif + +#endif /* __NU_FMC_H__ */ + diff --git a/Ubiquitous/XiZi/board/nuvoton-m2354/third_party_driver/include/Drivers/nu_fvc.h b/Ubiquitous/XiZi/board/nuvoton-m2354/third_party_driver/include/Drivers/nu_fvc.h new file mode 100644 index 0000000..858ccd3 --- /dev/null +++ b/Ubiquitous/XiZi/board/nuvoton-m2354/third_party_driver/include/Drivers/nu_fvc.h @@ -0,0 +1,55 @@ +/**************************************************************************//** + * @file nu_fvc.h + * @version V3.00 + * @brief Firmware Version Counter Driver Header + * + * @copyright SPDX-License-Identifier: Apache-2.0 + * @copyright Copyright (C) 2020 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ +#ifndef __NU_FVC_H__ +#define __NU_FVC_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup FVC_Driver FVC Driver + @{ +*/ + +/** @addtogroup FVC_EXPORTED_CONSTANTS FVC Exported Constants + @{ +*/ + +#define FVC_VCODE (0x77100000ul) /*!< The key code for FVC_CTL write. */ + +/**@}*/ /* end of group FVC_EXPORTED_CONSTANTS */ + + +/** @addtogroup FVC_EXPORTED_FUNCTIONS FVC Exported Functions + @{ +*/ + +int32_t FVC_Open(void); +void FVC_EnableMonotone(void); +int32_t FVC_SetNVC(uint32_t u32NvcIdx, uint32_t u32Cnt); +int32_t FVC_GetNVC(uint32_t u32NvcIdx); + + +/**@}*/ /* end of group FVC_EXPORTED_FUNCTIONS */ + +/**@}*/ /* end of group FVC_Driver */ + +/**@}*/ /* end of group Standard_Driver */ + +#ifdef __cplusplus +} +#endif + +#endif /* __NU_FVC_H__ */ diff --git a/Ubiquitous/XiZi/board/nuvoton-m2354/third_party_driver/include/Drivers/nu_gpio.h b/Ubiquitous/XiZi/board/nuvoton-m2354/third_party_driver/include/Drivers/nu_gpio.h new file mode 100644 index 0000000..3a8f872 --- /dev/null +++ b/Ubiquitous/XiZi/board/nuvoton-m2354/third_party_driver/include/Drivers/nu_gpio.h @@ -0,0 +1,1155 @@ +/**************************************************************************//** + * @file nu_gpio.h + * @version V3.0 + * @brief M2354 series General Purpose I/O (GPIO) driver header file + * + * @copyright SPDX-License-Identifier: Apache-2.0 + * @copyright Copyright (C) 2020 Nuvoton Technology Corp. All rights reserved. + ******************************************************************************/ +#ifndef __NU_GPIO_H__ +#define __NU_GPIO_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup GPIO_Driver GPIO Driver + @{ +*/ + +/** @addtogroup GPIO_EXPORTED_CONSTANTS GPIO Exported Constants + @{ +*/ + +#define GPIO_PIN_MAX 16UL /*!< Specify Maximum Pins of Each GPIO Port */ + + +/*---------------------------------------------------------------------------------------------------------*/ +/* GPIO_MODE Constant Definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define GPIO_MODE_INPUT 0x0UL /*!< Input Mode */ +#define GPIO_MODE_OUTPUT 0x1UL /*!< Output Mode */ +#define GPIO_MODE_OPEN_DRAIN 0x2UL /*!< Open-Drain Mode */ +#define GPIO_MODE_QUASI 0x3UL /*!< Quasi-bidirectional Mode */ + + +/*---------------------------------------------------------------------------------------------------------*/ +/* GPIO Interrupt Type Constant Definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define GPIO_INT_RISING 0x00010000UL /*!< Interrupt enable by Input Rising Edge */ +#define GPIO_INT_FALLING 0x00000001UL /*!< Interrupt enable by Input Falling Edge */ +#define GPIO_INT_BOTH_EDGE 0x00010001UL /*!< Interrupt enable by both Rising Edge and Falling Edge */ +#define GPIO_INT_HIGH 0x01010000UL /*!< Interrupt enable by Level-High */ +#define GPIO_INT_LOW 0x01000001UL /*!< Interrupt enable by Level-Level */ + + +/*---------------------------------------------------------------------------------------------------------*/ +/* GPIO_INTTYPE Constant Definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define GPIO_INTTYPE_EDGE 0UL /*!< GPIO_INTTYPE Setting for Edge Trigger Mode */ +#define GPIO_INTTYPE_LEVEL 1UL /*!< GPIO_INTTYPE Setting for Edge Level Mode */ + + +/*---------------------------------------------------------------------------------------------------------*/ +/* GPIO Slew Rate Type Constant Definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define GPIO_SLEWCTL_NORMAL 0x0UL /*!< GPIO slew setting for normal Mode */ +#define GPIO_SLEWCTL_HIGH 0x1UL /*!< GPIO slew setting for high Mode */ +#define GPIO_SLEWCTL_FAST 0x2UL /*!< GPIO slew setting for fast Mode */ + + +/*---------------------------------------------------------------------------------------------------------*/ +/* GPIO Pull-up And Pull-down Type Constant Definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define GPIO_PUSEL_DISABLE 0x0UL /*!< GPIO PUSEL setting for Disable Mode */ +#define GPIO_PUSEL_PULL_UP 0x1UL /*!< GPIO PUSEL setting for Pull-up Mode */ +#define GPIO_PUSEL_PULL_DOWN 0x2UL /*!< GPIO PUSEL setting for Pull-down Mode */ + + +/*---------------------------------------------------------------------------------------------------------*/ +/* GPIO_DBCTL Constant Definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define GPIO_DBCTL_ICLK_ON 0x00000020UL /*!< GPIO_DBCTL setting for all IO pins edge detection circuit is always active after reset */ +#define GPIO_DBCTL_ICLK_OFF 0x00000000UL /*!< GPIO_DBCTL setting for edge detection circuit is active only if IO pin corresponding GPIOx_IEN bit is set to 1 */ + +#define GPIO_DBCTL_DBCLKSRC_LIRC 0x00000010UL /*!< GPIO_DBCTL setting for de-bounce counter clock source is the internal 10 kHz */ +#define GPIO_DBCTL_DBCLKSRC_HCLK 0x00000000UL /*!< GPIO_DBCTL setting for de-bounce counter clock source is the HCLK */ + +#define GPIO_DBCTL_DBCLKSEL_1 0x00000000UL /*!< GPIO_DBCTL setting for sampling cycle = 1 clocks */ +#define GPIO_DBCTL_DBCLKSEL_2 0x00000001UL /*!< GPIO_DBCTL setting for sampling cycle = 2 clocks */ +#define GPIO_DBCTL_DBCLKSEL_4 0x00000002UL /*!< GPIO_DBCTL setting for sampling cycle = 4 clocks */ +#define GPIO_DBCTL_DBCLKSEL_8 0x00000003UL /*!< GPIO_DBCTL setting for sampling cycle = 8 clocks */ +#define GPIO_DBCTL_DBCLKSEL_16 0x00000004UL /*!< GPIO_DBCTL setting for sampling cycle = 16 clocks */ +#define GPIO_DBCTL_DBCLKSEL_32 0x00000005UL /*!< GPIO_DBCTL setting for sampling cycle = 32 clocks */ +#define GPIO_DBCTL_DBCLKSEL_64 0x00000006UL /*!< GPIO_DBCTL setting for sampling cycle = 64 clocks */ +#define GPIO_DBCTL_DBCLKSEL_128 0x00000007UL /*!< GPIO_DBCTL setting for sampling cycle = 128 clocks */ +#define GPIO_DBCTL_DBCLKSEL_256 0x00000008UL /*!< GPIO_DBCTL setting for sampling cycle = 256 clocks */ +#define GPIO_DBCTL_DBCLKSEL_512 0x00000009UL /*!< GPIO_DBCTL setting for sampling cycle = 512 clocks */ +#define GPIO_DBCTL_DBCLKSEL_1024 0x0000000AUL /*!< GPIO_DBCTL setting for sampling cycle = 1024 clocks */ +#define GPIO_DBCTL_DBCLKSEL_2048 0x0000000BUL /*!< GPIO_DBCTL setting for sampling cycle = 2048 clocks */ +#define GPIO_DBCTL_DBCLKSEL_4096 0x0000000CUL /*!< GPIO_DBCTL setting for sampling cycle = 4096 clocks */ +#define GPIO_DBCTL_DBCLKSEL_8192 0x0000000DUL /*!< GPIO_DBCTL setting for sampling cycle = 8192 clocks */ +#define GPIO_DBCTL_DBCLKSEL_16384 0x0000000EUL /*!< GPIO_DBCTL setting for sampling cycle = 16384 clocks */ +#define GPIO_DBCTL_DBCLKSEL_32768 0x0000000FUL /*!< GPIO_DBCTL setting for sampling cycle = 32768 clocks */ + + +/** Define GPIO Pin Data Input/Output. It could be used to control each I/O pin by pin address mapping. + * Example 1: + * + * PA0 = 1; + * + * It is used to set PA.0 to high; + * + * Example 2: + * + * if (PA0) + * PA0 = 0; + * + * If PA.0 pin status is high, then set PA.0 data output to low. + */ + + +#if defined (SCU_INIT_IONSSET0_VAL) && (SCU_INIT_IONSSET0_VAL & BIT0 ) +#define PA0 PA0_NS /*!< Specify PA.0 Pin Data Input/Output */ +#else +#define PA0 PA0_S /*!< Specify PA.0 Pin Data Input/Output */ +#endif +#if defined (SCU_INIT_IONSSET0_VAL) && (SCU_INIT_IONSSET0_VAL & BIT1 ) +#define PA1 PA1_NS /*!< Specify PA.1 Pin Data Input/Output */ +#else +#define PA1 PA1_S /*!< Specify PA.1 Pin Data Input/Output */ +#endif +#if defined (SCU_INIT_IONSSET0_VAL) && (SCU_INIT_IONSSET0_VAL & BIT2 ) +#define PA2 PA2_NS /*!< Specify PA.2 Pin Data Input/Output */ +#else +#define PA2 PA2_S /*!< Specify PA.2 Pin Data Input/Output */ +#endif +#if defined (SCU_INIT_IONSSET0_VAL) && (SCU_INIT_IONSSET0_VAL & BIT3 ) +#define PA3 PA3_NS /*!< Specify PA.3 Pin Data Input/Output */ +#else +#define PA3 PA3_S /*!< Specify PA.3 Pin Data Input/Output */ +#endif +#if defined (SCU_INIT_IONSSET0_VAL) && (SCU_INIT_IONSSET0_VAL & BIT4 ) +#define PA4 PA4_NS /*!< Specify PA.4 Pin Data Input/Output */ +#else +#define PA4 PA4_S /*!< Specify PA.4 Pin Data Input/Output */ +#endif +#if defined (SCU_INIT_IONSSET0_VAL) && (SCU_INIT_IONSSET0_VAL & BIT5 ) +#define PA5 PA5_NS /*!< Specify PA.5 Pin Data Input/Output */ +#else +#define PA5 PA5_S /*!< Specify PA.5 Pin Data Input/Output */ +#endif +#if defined (SCU_INIT_IONSSET0_VAL) && (SCU_INIT_IONSSET0_VAL & BIT6 ) +#define PA6 PA6_NS /*!< Specify PA.6 Pin Data Input/Output */ +#else +#define PA6 PA6_S /*!< Specify PA.6 Pin Data Input/Output */ +#endif +#if defined (SCU_INIT_IONSSET0_VAL) && (SCU_INIT_IONSSET0_VAL & BIT7 ) +#define PA7 PA7_NS /*!< Specify PA.7 Pin Data Input/Output */ +#else +#define PA7 PA7_S /*!< Specify PA.7 Pin Data Input/Output */ +#endif +#if defined (SCU_INIT_IONSSET0_VAL) && (SCU_INIT_IONSSET0_VAL & BIT8 ) +#define PA8 PA8_NS /*!< Specify PA.8 Pin Data Input/Output */ +#else +#define PA8 PA8_S /*!< Specify PA.8 Pin Data Input/Output */ +#endif +#if defined (SCU_INIT_IONSSET0_VAL) && (SCU_INIT_IONSSET0_VAL & BIT9 ) +#define PA9 PA9_NS /*!< Specify PA.9 Pin Data Input/Output */ +#else +#define PA9 PA9_S /*!< Specify PA.9 Pin Data Input/Output */ +#endif +#if defined (SCU_INIT_IONSSET0_VAL) && (SCU_INIT_IONSSET0_VAL & BIT10 ) +#define PA10 PA10_NS /*!< Specify PA.10 Pin Data Input/Output */ +#else +#define PA10 PA10_S /*!< Specify PA.10 Pin Data Input/Output */ +#endif +#if defined (SCU_INIT_IONSSET0_VAL) && (SCU_INIT_IONSSET0_VAL & BIT11 ) +#define PA11 PA11_NS /*!< Specify PA.11 Pin Data Input/Output */ +#else +#define PA11 PA11_S /*!< Specify PA.11 Pin Data Input/Output */ +#endif +#if defined (SCU_INIT_IONSSET0_VAL) && (SCU_INIT_IONSSET0_VAL & BIT12 ) +#define PA12 PA12_NS /*!< Specify PA.12 Pin Data Input/Output */ +#else +#define PA12 PA12_S /*!< Specify PA.12 Pin Data Input/Output */ +#endif +#if defined (SCU_INIT_IONSSET0_VAL) && (SCU_INIT_IONSSET0_VAL & BIT13 ) +#define PA13 PA13_NS /*!< Specify PA.13 Pin Data Input/Output */ +#else +#define PA13 PA13_S /*!< Specify PA.13 Pin Data Input/Output */ +#endif +#if defined (SCU_INIT_IONSSET0_VAL) && (SCU_INIT_IONSSET0_VAL & BIT14 ) +#define PA14 PA14_NS /*!< Specify PA.14 Pin Data Input/Output */ +#else +#define PA14 PA14_S /*!< Specify PA.14 Pin Data Input/Output */ +#endif +#if defined (SCU_INIT_IONSSET0_VAL) && (SCU_INIT_IONSSET0_VAL & BIT15 ) +#define PA15 PA15_NS /*!< Specify PA.15 Pin Data Input/Output */ +#else +#define PA15 PA15_S /*!< Specify PA.15 Pin Data Input/Output */ +#endif + +#if defined (SCU_INIT_IONSSET1_VAL) && (SCU_INIT_IONSSET1_VAL & BIT0 ) +#define PB0 PB0_NS /*!< Specify PB.0 Pin Data Input/Output */ +#else +#define PB0 PB0_S /*!< Specify PB.0 Pin Data Input/Output */ +#endif +#if defined (SCU_INIT_IONSSET1_VAL) && (SCU_INIT_IONSSET1_VAL & BIT1 ) +#define PB1 PB1_NS /*!< Specify PB.1 Pin Data Input/Output */ +#else +#define PB1 PB1_S /*!< Specify PB.1 Pin Data Input/Output */ +#endif +#if defined (SCU_INIT_IONSSET1_VAL) && (SCU_INIT_IONSSET1_VAL & BIT2 ) +#define PB2 PB2_NS /*!< Specify PB.2 Pin Data Input/Output */ +#else +#define PB2 PB2_S /*!< Specify PB.2 Pin Data Input/Output */ +#endif +#if defined (SCU_INIT_IONSSET1_VAL) && (SCU_INIT_IONSSET1_VAL & BIT3 ) +#define PB3 PB3_NS /*!< Specify PB.3 Pin Data Input/Output */ +#else +#define PB3 PB3_S /*!< Specify PB.3 Pin Data Input/Output */ +#endif +#if defined (SCU_INIT_IONSSET1_VAL) && (SCU_INIT_IONSSET1_VAL & BIT4 ) +#define PB4 PB4_NS /*!< Specify PB.4 Pin Data Input/Output */ +#else +#define PB4 PB4_S /*!< Specify PB.4 Pin Data Input/Output */ +#endif +#if defined (SCU_INIT_IONSSET1_VAL) && (SCU_INIT_IONSSET1_VAL & BIT5 ) +#define PB5 PB5_NS /*!< Specify PB.5 Pin Data Input/Output */ +#else +#define PB5 PB5_S /*!< Specify PB.5 Pin Data Input/Output */ +#endif +#if defined (SCU_INIT_IONSSET1_VAL) && (SCU_INIT_IONSSET1_VAL & BIT6 ) +#define PB6 PB6_NS /*!< Specify PB.6 Pin Data Input/Output */ +#else +#define PB6 PB6_S /*!< Specify PB.6 Pin Data Input/Output */ +#endif +#if defined (SCU_INIT_IONSSET1_VAL) && (SCU_INIT_IONSSET1_VAL & BIT7 ) +#define PB7 PB7_NS /*!< Specify PB.7 Pin Data Input/Output */ +#else +#define PB7 PB7_S /*!< Specify PB.7 Pin Data Input/Output */ +#endif +#if defined (SCU_INIT_IONSSET1_VAL) && (SCU_INIT_IONSSET1_VAL & BIT8 ) +#define PB8 PB8_NS /*!< Specify PB.8 Pin Data Input/Output */ +#else +#define PB8 PB8_S /*!< Specify PB.8 Pin Data Input/Output */ +#endif +#if defined (SCU_INIT_IONSSET1_VAL) && (SCU_INIT_IONSSET1_VAL & BIT9 ) +#define PB9 PB9_NS /*!< Specify PB.9 Pin Data Input/Output */ +#else +#define PB9 PB9_S /*!< Specify PB.9 Pin Data Input/Output */ +#endif +#if defined (SCU_INIT_IONSSET1_VAL) && (SCU_INIT_IONSSET1_VAL & BIT10 ) +#define PB10 PB10_NS /*!< Specify PB.10 Pin Data Input/Output */ +#else +#define PB10 PB10_S /*!< Specify PB.10 Pin Data Input/Output */ +#endif +#if defined (SCU_INIT_IONSSET1_VAL) && (SCU_INIT_IONSSET1_VAL & BIT11 ) +#define PB11 PB11_NS /*!< Specify PB.11 Pin Data Input/Output */ +#else +#define PB11 PB11_S /*!< Specify PB.11 Pin Data Input/Output */ +#endif +#if defined (SCU_INIT_IONSSET1_VAL) && (SCU_INIT_IONSSET1_VAL & BIT12 ) +#define PB12 PB12_NS /*!< Specify PB.12 Pin Data Input/Output */ +#else +#define PB12 PB12_S /*!< Specify PB.12 Pin Data Input/Output */ +#endif +#if defined (SCU_INIT_IONSSET1_VAL) && (SCU_INIT_IONSSET1_VAL & BIT13 ) +#define PB13 PB13_NS /*!< Specify PB.13 Pin Data Input/Output */ +#else +#define PB13 PB13_S /*!< Specify PB.13 Pin Data Input/Output */ +#endif +#if defined (SCU_INIT_IONSSET1_VAL) && (SCU_INIT_IONSSET1_VAL & BIT14 ) +#define PB14 PB14_NS /*!< Specify PB.14 Pin Data Input/Output */ +#else +#define PB14 PB14_S /*!< Specify PB.14 Pin Data Input/Output */ +#endif +#if defined (SCU_INIT_IONSSET1_VAL) && (SCU_INIT_IONSSET1_VAL & BIT15 ) +#define PB15 PB15_NS /*!< Specify PB.15 Pin Data Input/Output */ +#else +#define PB15 PB15_S /*!< Specify PB.15 Pin Data Input/Output */ +#endif + +#if defined (SCU_INIT_IONSSET2_VAL) && (SCU_INIT_IONSSET2_VAL & BIT0 ) +#define PC0 PC0_NS /*!< Specify PC.0 Pin Data Input/Output */ +#else +#define PC0 PC0_S /*!< Specify PC.0 Pin Data Input/Output */ +#endif +#if defined (SCU_INIT_IONSSET2_VAL) && (SCU_INIT_IONSSET2_VAL & BIT1 ) +#define PC1 PC1_NS /*!< Specify PC.1 Pin Data Input/Output */ +#else +#define PC1 PC1_S /*!< Specify PC.1 Pin Data Input/Output */ +#endif +#if defined (SCU_INIT_IONSSET2_VAL) && (SCU_INIT_IONSSET2_VAL & BIT2 ) +#define PC2 PC2_NS /*!< Specify PC.2 Pin Data Input/Output */ +#else +#define PC2 PC2_S /*!< Specify PC.2 Pin Data Input/Output */ +#endif +#if defined (SCU_INIT_IONSSET2_VAL) && (SCU_INIT_IONSSET2_VAL & BIT3 ) +#define PC3 PC3_NS /*!< Specify PC.3 Pin Data Input/Output */ +#else +#define PC3 PC3_S /*!< Specify PC.3 Pin Data Input/Output */ +#endif +#if defined (SCU_INIT_IONSSET2_VAL) && (SCU_INIT_IONSSET2_VAL & BIT4 ) +#define PC4 PC4_NS /*!< Specify PC.4 Pin Data Input/Output */ +#else +#define PC4 PC4_S /*!< Specify PC.4 Pin Data Input/Output */ +#endif +#if defined (SCU_INIT_IONSSET2_VAL) && (SCU_INIT_IONSSET2_VAL & BIT5 ) +#define PC5 PC5_NS /*!< Specify PC.5 Pin Data Input/Output */ +#else +#define PC5 PC5_S /*!< Specify PC.5 Pin Data Input/Output */ +#endif +#if defined (SCU_INIT_IONSSET2_VAL) && (SCU_INIT_IONSSET2_VAL & BIT6 ) +#define PC6 PC6_NS /*!< Specify PC.6 Pin Data Input/Output */ +#else +#define PC6 PC6_S /*!< Specify PC.6 Pin Data Input/Output */ +#endif +#if defined (SCU_INIT_IONSSET2_VAL) && (SCU_INIT_IONSSET2_VAL & BIT7 ) +#define PC7 PC7_NS /*!< Specify PC.7 Pin Data Input/Output */ +#else +#define PC7 PC7_S /*!< Specify PC.7 Pin Data Input/Output */ +#endif +#if defined (SCU_INIT_IONSSET2_VAL) && (SCU_INIT_IONSSET2_VAL & BIT8 ) +#define PC8 PC8_NS /*!< Specify PC.8 Pin Data Input/Output */ +#else +#define PC8 PC8_S /*!< Specify PC.8 Pin Data Input/Output */ +#endif +#if defined (SCU_INIT_IONSSET2_VAL) && (SCU_INIT_IONSSET2_VAL & BIT9 ) +#define PC9 PC9_NS /*!< Specify PC.9 Pin Data Input/Output */ +#else +#define PC9 PC9_S /*!< Specify PC.9 Pin Data Input/Output */ +#endif +#if defined (SCU_INIT_IONSSET2_VAL) && (SCU_INIT_IONSSET2_VAL & BIT10 ) +#define PC10 PC10_NS /*!< Specify PC.10 Pin Data Input/Output */ +#else +#define PC10 PC10_S /*!< Specify PC.10 Pin Data Input/Output */ +#endif +#if defined (SCU_INIT_IONSSET2_VAL) && (SCU_INIT_IONSSET2_VAL & BIT11 ) +#define PC11 PC11_NS /*!< Specify PC.11 Pin Data Input/Output */ +#else +#define PC11 PC11_S /*!< Specify PC.11 Pin Data Input/Output */ +#endif +#if defined (SCU_INIT_IONSSET2_VAL) && (SCU_INIT_IONSSET2_VAL & BIT12 ) +#define PC12 PC12_NS /*!< Specify PC.12 Pin Data Input/Output */ +#else +#define PC12 PC12_S /*!< Specify PC.12 Pin Data Input/Output */ +#endif +#if defined (SCU_INIT_IONSSET2_VAL) && (SCU_INIT_IONSSET2_VAL & BIT13 ) +#define PC13 PC13_NS /*!< Specify PC.13 Pin Data Input/Output */ +#else +#define PC13 PC13_S /*!< Specify PC.13 Pin Data Input/Output */ +#endif + +#if defined (SCU_INIT_IONSSET3_VAL) && (SCU_INIT_IONSSET3_VAL & BIT0 ) +#define PD0 PD0_NS /*!< Specify PD.0 Pin Data Input/Output */ +#else +#define PD0 PD0_S /*!< Specify PD.0 Pin Data Input/Output */ +#endif +#if defined (SCU_INIT_IONSSET3_VAL) && (SCU_INIT_IONSSET3_VAL & BIT1 ) +#define PD1 PD1_NS /*!< Specify PD.1 Pin Data Input/Output */ +#else +#define PD1 PD1_S /*!< Specify PD.1 Pin Data Input/Output */ +#endif +#if defined (SCU_INIT_IONSSET3_VAL) && (SCU_INIT_IONSSET3_VAL & BIT2 ) +#define PD2 PD2_NS /*!< Specify PD.2 Pin Data Input/Output */ +#else +#define PD2 PD2_S /*!< Specify PD.2 Pin Data Input/Output */ +#endif +#if defined (SCU_INIT_IONSSET3_VAL) && (SCU_INIT_IONSSET3_VAL & BIT3 ) +#define PD3 PD3_NS /*!< Specify PD.3 Pin Data Input/Output */ +#else +#define PD3 PD3_S /*!< Specify PD.3 Pin Data Input/Output */ +#endif +#if defined (SCU_INIT_IONSSET3_VAL) && (SCU_INIT_IONSSET3_VAL & BIT4 ) +#define PD4 PD4_NS /*!< Specify PD.4 Pin Data Input/Output */ +#else +#define PD4 PD4_S /*!< Specify PD.4 Pin Data Input/Output */ +#endif +#if defined (SCU_INIT_IONSSET3_VAL) && (SCU_INIT_IONSSET3_VAL & BIT5 ) +#define PD5 PD5_NS /*!< Specify PD.5 Pin Data Input/Output */ +#else +#define PD5 PD5_S /*!< Specify PD.5 Pin Data Input/Output */ +#endif +#if defined (SCU_INIT_IONSSET3_VAL) && (SCU_INIT_IONSSET3_VAL & BIT6 ) +#define PD6 PD6_NS /*!< Specify PD.6 Pin Data Input/Output */ +#else +#define PD6 PD6_S /*!< Specify PD.6 Pin Data Input/Output */ +#endif +#if defined (SCU_INIT_IONSSET3_VAL) && (SCU_INIT_IONSSET3_VAL & BIT7 ) +#define PD7 PD7_NS /*!< Specify PD.7 Pin Data Input/Output */ +#else +#define PD7 PD7_S /*!< Specify PD.7 Pin Data Input/Output */ +#endif +#if defined (SCU_INIT_IONSSET3_VAL) && (SCU_INIT_IONSSET3_VAL & BIT8 ) +#define PD8 PD8_NS /*!< Specify PD.8 Pin Data Input/Output */ +#else +#define PD8 PD8_S /*!< Specify PD.8 Pin Data Input/Output */ +#endif +#if defined (SCU_INIT_IONSSET3_VAL) && (SCU_INIT_IONSSET3_VAL & BIT9 ) +#define PD9 PD9_NS /*!< Specify PD.9 Pin Data Input/Output */ +#else +#define PD9 PD9_S /*!< Specify PD.9 Pin Data Input/Output */ +#endif +#if defined (SCU_INIT_IONSSET3_VAL) && (SCU_INIT_IONSSET3_VAL & BIT10 ) +#define PD10 PD10_NS /*!< Specify PD.10 Pin Data Input/Output */ +#else +#define PD10 PD10_S /*!< Specify PD.10 Pin Data Input/Output */ +#endif +#if defined (SCU_INIT_IONSSET3_VAL) && (SCU_INIT_IONSSET3_VAL & BIT11 ) +#define PD11 PD11_NS /*!< Specify PD.11 Pin Data Input/Output */ +#else +#define PD11 PD11_S /*!< Specify PD.11 Pin Data Input/Output */ +#endif +#if defined (SCU_INIT_IONSSET3_VAL) && (SCU_INIT_IONSSET3_VAL & BIT12 ) +#define PD12 PD12_NS /*!< Specify PD.12 Pin Data Input/Output */ +#else +#define PD12 PD12_S /*!< Specify PD.12 Pin Data Input/Output */ +#endif +#if defined (SCU_INIT_IONSSET3_VAL) && (SCU_INIT_IONSSET3_VAL & BIT14 ) +#define PD14 PD14_NS /*!< Specify PD.14 Pin Data Input/Output */ +#else +#define PD14 PD14_S /*!< Specify PD.14 Pin Data Input/Output */ +#endif + +#if defined (SCU_INIT_IONSSET4_VAL) && (SCU_INIT_IONSSET4_VAL & BIT0 ) +#define PE0 PE0_NS /*!< Specify PE.0 Pin Data Input/Output */ +#else +#define PE0 PE0_S /*!< Specify PE.0 Pin Data Input/Output */ +#endif +#if defined (SCU_INIT_IONSSET4_VAL) && (SCU_INIT_IONSSET4_VAL & BIT1 ) +#define PE1 PE1_NS /*!< Specify PE.1 Pin Data Input/Output */ +#else +#define PE1 PE1_S /*!< Specify PE.1 Pin Data Input/Output */ +#endif +#if defined (SCU_INIT_IONSSET4_VAL) && (SCU_INIT_IONSSET4_VAL & BIT2 ) +#define PE2 PE2_NS /*!< Specify PE.2 Pin Data Input/Output */ +#else +#define PE2 PE2_S /*!< Specify PE.2 Pin Data Input/Output */ +#endif +#if defined (SCU_INIT_IONSSET4_VAL) && (SCU_INIT_IONSSET4_VAL & BIT3 ) +#define PE3 PE3_NS /*!< Specify PE.3 Pin Data Input/Output */ +#else +#define PE3 PE3_S /*!< Specify PE.3 Pin Data Input/Output */ +#endif +#if defined (SCU_INIT_IONSSET4_VAL) && (SCU_INIT_IONSSET4_VAL & BIT4 ) +#define PE4 PE4_NS /*!< Specify PE.4 Pin Data Input/Output */ +#else +#define PE4 PE4_S /*!< Specify PE.4 Pin Data Input/Output */ +#endif +#if defined (SCU_INIT_IONSSET4_VAL) && (SCU_INIT_IONSSET4_VAL & BIT5 ) +#define PE5 PE5_NS /*!< Specify PE.5 Pin Data Input/Output */ +#else +#define PE5 PE5_S /*!< Specify PE.5 Pin Data Input/Output */ +#endif +#if defined (SCU_INIT_IONSSET4_VAL) && (SCU_INIT_IONSSET4_VAL & BIT6 ) +#define PE6 PE6_NS /*!< Specify PE.6 Pin Data Input/Output */ +#else +#define PE6 PE6_S /*!< Specify PE.6 Pin Data Input/Output */ +#endif +#if defined (SCU_INIT_IONSSET4_VAL) && (SCU_INIT_IONSSET4_VAL & BIT7 ) +#define PE7 PE7_NS /*!< Specify PE.7 Pin Data Input/Output */ +#else +#define PE7 PE7_S /*!< Specify PE.7 Pin Data Input/Output */ +#endif +#if defined (SCU_INIT_IONSSET4_VAL) && (SCU_INIT_IONSSET4_VAL & BIT8 ) +#define PE8 PE8_NS /*!< Specify PE.8 Pin Data Input/Output */ +#else +#define PE8 PE8_S /*!< Specify PE.8 Pin Data Input/Output */ +#endif +#if defined (SCU_INIT_IONSSET4_VAL) && (SCU_INIT_IONSSET4_VAL & BIT9 ) +#define PE9 PE9_NS /*!< Specify PE.9 Pin Data Input/Output */ +#else +#define PE9 PE9_S /*!< Specify PE.9 Pin Data Input/Output */ +#endif +#if defined (SCU_INIT_IONSSET4_VAL) && (SCU_INIT_IONSSET4_VAL & BIT10 ) +#define PE10 PE10_NS /*!< Specify PE.10 Pin Data Input/Output */ +#else +#define PE10 PE10_S /*!< Specify PE.10 Pin Data Input/Output */ +#endif +#if defined (SCU_INIT_IONSSET4_VAL) && (SCU_INIT_IONSSET4_VAL & BIT11 ) +#define PE11 PE11_NS /*!< Specify PE.11 Pin Data Input/Output */ +#else +#define PE11 PE11_S /*!< Specify PE.11 Pin Data Input/Output */ +#endif +#if defined (SCU_INIT_IONSSET4_VAL) && (SCU_INIT_IONSSET4_VAL & BIT12 ) +#define PE12 PE12_NS /*!< Specify PE.12 Pin Data Input/Output */ +#else +#define PE12 PE12_S /*!< Specify PE.12 Pin Data Input/Output */ +#endif +#if defined (SCU_INIT_IONSSET4_VAL) && (SCU_INIT_IONSSET4_VAL & BIT13 ) +#define PE13 PE13_NS /*!< Specify PE.13 Pin Data Input/Output */ +#else +#define PE13 PE13_S /*!< Specify PE.13 Pin Data Input/Output */ +#endif +#if defined (SCU_INIT_IONSSET4_VAL) && (SCU_INIT_IONSSET4_VAL & BIT14 ) +#define PE14 PE14_NS /*!< Specify PE.14 Pin Data Input/Output */ +#else +#define PE14 PE14_S /*!< Specify PE.14 Pin Data Input/Output */ +#endif +#if defined (SCU_INIT_IONSSET4_VAL) && (SCU_INIT_IONSSET4_VAL & BIT15 ) +#define PE15 PE15_NS /*!< Specify PE.15 Pin Data Input/Output */ +#else +#define PE15 PE15_S /*!< Specify PE.15 Pin Data Input/Output */ +#endif + +#if defined (SCU_INIT_IONSSET5_VAL) && (SCU_INIT_IONSSET5_VAL & BIT0 ) +#define PF0 PF0_NS /*!< Specify PF.0 Pin Data Input/Output */ +#else +#define PF0 PF0_S /*!< Specify PF.0 Pin Data Input/Output */ +#endif +#if defined (SCU_INIT_IONSSET5_VAL) && (SCU_INIT_IONSSET5_VAL & BIT1 ) +#define PF1 PF1_NS /*!< Specify PF.1 Pin Data Input/Output */ +#else +#define PF1 PF1_S /*!< Specify PF.1 Pin Data Input/Output */ +#endif +#if defined (SCU_INIT_IONSSET5_VAL) && (SCU_INIT_IONSSET5_VAL & BIT2 ) +#define PF2 PF2_NS /*!< Specify PF.2 Pin Data Input/Output */ +#else +#define PF2 PF2_S /*!< Specify PF.2 Pin Data Input/Output */ +#endif +#if defined (SCU_INIT_IONSSET5_VAL) && (SCU_INIT_IONSSET5_VAL & BIT3 ) +#define PF3 PF3_NS /*!< Specify PF.3 Pin Data Input/Output */ +#else +#define PF3 PF3_S /*!< Specify PF.3 Pin Data Input/Output */ +#endif +#if defined (SCU_INIT_IONSSET5_VAL) && (SCU_INIT_IONSSET5_VAL & BIT4 ) +#define PF4 PF4_NS /*!< Specify PF.4 Pin Data Input/Output */ +#else +#define PF4 PF4_S /*!< Specify PF.4 Pin Data Input/Output */ +#endif +#if defined (SCU_INIT_IONSSET5_VAL) && (SCU_INIT_IONSSET5_VAL & BIT5 ) +#define PF5 PF5_NS /*!< Specify PF.5 Pin Data Input/Output */ +#else +#define PF5 PF5_S /*!< Specify PF.5 Pin Data Input/Output */ +#endif +#if defined (SCU_INIT_IONSSET5_VAL) && (SCU_INIT_IONSSET5_VAL & BIT6 ) +#define PF6 PF6_NS /*!< Specify PF.6 Pin Data Input/Output */ +#else +#define PF6 PF6_S /*!< Specify PF.6 Pin Data Input/Output */ +#endif +#if defined (SCU_INIT_IONSSET5_VAL) && (SCU_INIT_IONSSET5_VAL & BIT7 ) +#define PF7 PF7_NS /*!< Specify PF.7 Pin Data Input/Output */ +#else +#define PF7 PF7_S /*!< Specify PF.7 Pin Data Input/Output */ +#endif +#if defined (SCU_INIT_IONSSET5_VAL) && (SCU_INIT_IONSSET5_VAL & BIT8 ) +#define PF8 PF8_NS /*!< Specify PF.8 Pin Data Input/Output */ +#else +#define PF8 PF8_S /*!< Specify PF.8 Pin Data Input/Output */ +#endif +#if defined (SCU_INIT_IONSSET5_VAL) && (SCU_INIT_IONSSET5_VAL & BIT9 ) +#define PF9 PF9_NS /*!< Specify PF.9 Pin Data Input/Output */ +#else +#define PF9 PF9_S /*!< Specify PF.9 Pin Data Input/Output */ +#endif +#if defined (SCU_INIT_IONSSET5_VAL) && (SCU_INIT_IONSSET5_VAL & BIT10 ) +#define PF10 PF10_NS /*!< Specify PF.10 Pin Data Input/Output */ +#else +#define PF10 PF10_S /*!< Specify PF.10 Pin Data Input/Output */ +#endif +#if defined (SCU_INIT_IONSSET5_VAL) && (SCU_INIT_IONSSET5_VAL & BIT11 ) +#define PF11 PF11_NS /*!< Specify PF.11 Pin Data Input/Output */ +#else +#define PF11 PF11_S /*!< Specify PF.11 Pin Data Input/Output */ +#endif + +#if defined (SCU_INIT_IONSSET6_VAL) && (SCU_INIT_IONSSET6_VAL & BIT2 ) +#define PG2 PG2_NS /*!< Specify PG.2 Pin Data Input/Output */ +#else +#define PG2 PG2_S /*!< Specify PG.2 Pin Data Input/Output */ +#endif +#if defined (SCU_INIT_IONSSET6_VAL) && (SCU_INIT_IONSSET6_VAL & BIT3 ) +#define PG3 PG3_NS /*!< Specify PG.3 Pin Data Input/Output */ +#else +#define PG3 PG3_S /*!< Specify PG.3 Pin Data Input/Output */ +#endif +#if defined (SCU_INIT_IONSSET6_VAL) && (SCU_INIT_IONSSET6_VAL & BIT4 ) +#define PG4 PG4_NS /*!< Specify PG.4 Pin Data Input/Output */ +#else +#define PG4 PG4_S /*!< Specify PG.4 Pin Data Input/Output */ +#endif +#if defined (SCU_INIT_IONSSET6_VAL) && (SCU_INIT_IONSSET6_VAL & BIT9 ) +#define PG9 PG9_NS /*!< Specify PG.9 Pin Data Input/Output */ +#else +#define PG9 PG9_S /*!< Specify PG.9 Pin Data Input/Output */ +#endif +#if defined (SCU_INIT_IONSSET6_VAL) && (SCU_INIT_IONSSET6_VAL & BIT10 ) +#define PG10 PG10_NS /*!< Specify PG.10 Pin Data Input/Output */ +#else +#define PG10 PG10_S /*!< Specify PG.10 Pin Data Input/Output */ +#endif +#if defined (SCU_INIT_IONSSET6_VAL) && (SCU_INIT_IONSSET6_VAL & BIT11 ) +#define PG11 PG11_NS /*!< Specify PG.11 Pin Data Input/Output */ +#else +#define PG11 PG11_S /*!< Specify PG.11 Pin Data Input/Output */ +#endif +#if defined (SCU_INIT_IONSSET6_VAL) && (SCU_INIT_IONSSET6_VAL & BIT12 ) +#define PG12 PG12_NS /*!< Specify PG.12 Pin Data Input/Output */ +#else +#define PG12 PG12_S /*!< Specify PG.12 Pin Data Input/Output */ +#endif +#if defined (SCU_INIT_IONSSET6_VAL) && (SCU_INIT_IONSSET6_VAL & BIT13 ) +#define PG13 PG13_NS /*!< Specify PG.13 Pin Data Input/Output */ +#else +#define PG13 PG13_S /*!< Specify PG.13 Pin Data Input/Output */ +#endif +#if defined (SCU_INIT_IONSSET6_VAL) && (SCU_INIT_IONSSET6_VAL & BIT14 ) +#define PG14 PG14_NS /*!< Specify PG.14 Pin Data Input/Output */ +#else +#define PG14 PG14_S /*!< Specify PG.14 Pin Data Input/Output */ +#endif +#if defined (SCU_INIT_IONSSET6_VAL) && (SCU_INIT_IONSSET6_VAL & BIT15 ) +#define PG15 PG15_NS /*!< Specify PG.15 Pin Data Input/Output */ +#else +#define PG15 PG15_S /*!< Specify PG.15 Pin Data Input/Output */ +#endif + +#if defined (SCU_INIT_IONSSET7_VAL) && (SCU_INIT_IONSSET7_VAL & BIT4 ) +#define PH4 PH4_NS /*!< Specify PH.4 Pin Data Input/Output */ +#else +#define PH4 PH4_S /*!< Specify PH.4 Pin Data Input/Output */ +#endif +#if defined (SCU_INIT_IONSSET7_VAL) && (SCU_INIT_IONSSET7_VAL & BIT5 ) +#define PH5 PH5_NS /*!< Specify PH.5 Pin Data Input/Output */ +#else +#define PH5 PH5_S /*!< Specify PH.5 Pin Data Input/Output */ +#endif +#if defined (SCU_INIT_IONSSET7_VAL) && (SCU_INIT_IONSSET7_VAL & BIT6 ) +#define PH6 PH6_NS /*!< Specify PH.6 Pin Data Input/Output */ +#else +#define PH6 PH6_S /*!< Specify PH.6 Pin Data Input/Output */ +#endif +#if defined (SCU_INIT_IONSSET7_VAL) && (SCU_INIT_IONSSET7_VAL & BIT7 ) +#define PH7 PH7_NS /*!< Specify PH.7 Pin Data Input/Output */ +#else +#define PH7 PH7_S /*!< Specify PH.7 Pin Data Input/Output */ +#endif +#if defined (SCU_INIT_IONSSET7_VAL) && (SCU_INIT_IONSSET7_VAL & BIT8 ) +#define PH8 PH8_NS /*!< Specify PH.8 Pin Data Input/Output */ +#else +#define PH8 PH8_S /*!< Specify PH.8 Pin Data Input/Output */ +#endif +#if defined (SCU_INIT_IONSSET7_VAL) && (SCU_INIT_IONSSET7_VAL & BIT9 ) +#define PH9 PH9_NS /*!< Specify PH.9 Pin Data Input/Output */ +#else +#define PH9 PH9_S /*!< Specify PH.9 Pin Data Input/Output */ +#endif +#if defined (SCU_INIT_IONSSET7_VAL) && (SCU_INIT_IONSSET7_VAL & BIT10 ) +#define PH10 PH10_NS /*!< Specify PH.10 Pin Data Input/Output */ +#else +#define PH10 PH10_S /*!< Specify PH.10 Pin Data Input/Output */ +#endif +#if defined (SCU_INIT_IONSSET7_VAL) && (SCU_INIT_IONSSET7_VAL & BIT11 ) +#define PH11 PH11_NS /*!< Specify PH.11 Pin Data Input/Output */ +#else +#define PH11 PH11_S /*!< Specify PH.11 Pin Data Input/Output */ +#endif + + +/* GPIO bit definitions for secure */ +#define GPIO_PIN_DATA_S(port, pin) (*((volatile uint32_t *)((GPIO_PIN_DATA_BASE+(0x40*(port))) + ((pin)<<2)))) +#define PA0_S GPIO_PIN_DATA_S(0, 0 ) /*!< Specify PA.0 Pin Data Input/Output */ +#define PA1_S GPIO_PIN_DATA_S(0, 1 ) /*!< Specify PA.1 Pin Data Input/Output */ +#define PA2_S GPIO_PIN_DATA_S(0, 2 ) /*!< Specify PA.2 Pin Data Input/Output */ +#define PA3_S GPIO_PIN_DATA_S(0, 3 ) /*!< Specify PA.3 Pin Data Input/Output */ +#define PA4_S GPIO_PIN_DATA_S(0, 4 ) /*!< Specify PA.4 Pin Data Input/Output */ +#define PA5_S GPIO_PIN_DATA_S(0, 5 ) /*!< Specify PA.5 Pin Data Input/Output */ +#define PA6_S GPIO_PIN_DATA_S(0, 6 ) /*!< Specify PA.6 Pin Data Input/Output */ +#define PA7_S GPIO_PIN_DATA_S(0, 7 ) /*!< Specify PA.7 Pin Data Input/Output */ +#define PA8_S GPIO_PIN_DATA_S(0, 8 ) /*!< Specify PA.8 Pin Data Input/Output */ +#define PA9_S GPIO_PIN_DATA_S(0, 9 ) /*!< Specify PA.9 Pin Data Input/Output */ +#define PA10_S GPIO_PIN_DATA_S(0, 10) /*!< Specify PA.10 Pin Data Input/Output */ +#define PA11_S GPIO_PIN_DATA_S(0, 11) /*!< Specify PA.11 Pin Data Input/Output */ +#define PA12_S GPIO_PIN_DATA_S(0, 12) /*!< Specify PA.12 Pin Data Input/Output */ +#define PA13_S GPIO_PIN_DATA_S(0, 13) /*!< Specify PA.13 Pin Data Input/Output */ +#define PA14_S GPIO_PIN_DATA_S(0, 14) /*!< Specify PA.14 Pin Data Input/Output */ +#define PA15_S GPIO_PIN_DATA_S(0, 15) /*!< Specify PA.15 Pin Data Input/Output */ +#define PB0_S GPIO_PIN_DATA_S(1, 0 ) /*!< Specify PB.0 Pin Data Input/Output */ +#define PB1_S GPIO_PIN_DATA_S(1, 1 ) /*!< Specify PB.1 Pin Data Input/Output */ +#define PB2_S GPIO_PIN_DATA_S(1, 2 ) /*!< Specify PB.2 Pin Data Input/Output */ +#define PB3_S GPIO_PIN_DATA_S(1, 3 ) /*!< Specify PB.3 Pin Data Input/Output */ +#define PB4_S GPIO_PIN_DATA_S(1, 4 ) /*!< Specify PB.4 Pin Data Input/Output */ +#define PB5_S GPIO_PIN_DATA_S(1, 5 ) /*!< Specify PB.5 Pin Data Input/Output */ +#define PB6_S GPIO_PIN_DATA_S(1, 6 ) /*!< Specify PB.6 Pin Data Input/Output */ +#define PB7_S GPIO_PIN_DATA_S(1, 7 ) /*!< Specify PB.7 Pin Data Input/Output */ +#define PB8_S GPIO_PIN_DATA_S(1, 8 ) /*!< Specify PB.8 Pin Data Input/Output */ +#define PB9_S GPIO_PIN_DATA_S(1, 9 ) /*!< Specify PB.9 Pin Data Input/Output */ +#define PB10_S GPIO_PIN_DATA_S(1, 10) /*!< Specify PB.10 Pin Data Input/Output */ +#define PB11_S GPIO_PIN_DATA_S(1, 11) /*!< Specify PB.11 Pin Data Input/Output */ +#define PB12_S GPIO_PIN_DATA_S(1, 12) /*!< Specify PB.12 Pin Data Input/Output */ +#define PB13_S GPIO_PIN_DATA_S(1, 13) /*!< Specify PB.13 Pin Data Input/Output */ +#define PB14_S GPIO_PIN_DATA_S(1, 14) /*!< Specify PB.14 Pin Data Input/Output */ +#define PB15_S GPIO_PIN_DATA_S(1, 15) /*!< Specify PB.15 Pin Data Input/Output */ +#define PC0_S GPIO_PIN_DATA_S(2, 0 ) /*!< Specify PC.0 Pin Data Input/Output */ +#define PC1_S GPIO_PIN_DATA_S(2, 1 ) /*!< Specify PC.1 Pin Data Input/Output */ +#define PC2_S GPIO_PIN_DATA_S(2, 2 ) /*!< Specify PC.2 Pin Data Input/Output */ +#define PC3_S GPIO_PIN_DATA_S(2, 3 ) /*!< Specify PC.3 Pin Data Input/Output */ +#define PC4_S GPIO_PIN_DATA_S(2, 4 ) /*!< Specify PC.4 Pin Data Input/Output */ +#define PC5_S GPIO_PIN_DATA_S(2, 5 ) /*!< Specify PC.5 Pin Data Input/Output */ +#define PC6_S GPIO_PIN_DATA_S(2, 6 ) /*!< Specify PC.6 Pin Data Input/Output */ +#define PC7_S GPIO_PIN_DATA_S(2, 7 ) /*!< Specify PC.7 Pin Data Input/Output */ +#define PC8_S GPIO_PIN_DATA_S(2, 8 ) /*!< Specify PC.8 Pin Data Input/Output */ +#define PC9_S GPIO_PIN_DATA_S(2, 9 ) /*!< Specify PC.9 Pin Data Input/Output */ +#define PC10_S GPIO_PIN_DATA_S(2, 10) /*!< Specify PC.10 Pin Data Input/Output */ +#define PC11_S GPIO_PIN_DATA_S(2, 11) /*!< Specify PC.11 Pin Data Input/Output */ +#define PC12_S GPIO_PIN_DATA_S(2, 12) /*!< Specify PC.12 Pin Data Input/Output */ +#define PC13_S GPIO_PIN_DATA_S(2, 13) /*!< Specify PC.13 Pin Data Input/Output */ +#define PD0_S GPIO_PIN_DATA_S(3, 0 ) /*!< Specify PD.0 Pin Data Input/Output */ +#define PD1_S GPIO_PIN_DATA_S(3, 1 ) /*!< Specify PD.1 Pin Data Input/Output */ +#define PD2_S GPIO_PIN_DATA_S(3, 2 ) /*!< Specify PD.2 Pin Data Input/Output */ +#define PD3_S GPIO_PIN_DATA_S(3, 3 ) /*!< Specify PD.3 Pin Data Input/Output */ +#define PD4_S GPIO_PIN_DATA_S(3, 4 ) /*!< Specify PD.4 Pin Data Input/Output */ +#define PD5_S GPIO_PIN_DATA_S(3, 5 ) /*!< Specify PD.5 Pin Data Input/Output */ +#define PD6_S GPIO_PIN_DATA_S(3, 6 ) /*!< Specify PD.6 Pin Data Input/Output */ +#define PD7_S GPIO_PIN_DATA_S(3, 7 ) /*!< Specify PD.7 Pin Data Input/Output */ +#define PD8_S GPIO_PIN_DATA_S(3, 8 ) /*!< Specify PD.8 Pin Data Input/Output */ +#define PD9_S GPIO_PIN_DATA_S(3, 9 ) /*!< Specify PD.9 Pin Data Input/Output */ +#define PD10_S GPIO_PIN_DATA_S(3, 10) /*!< Specify PD.10 Pin Data Input/Output */ +#define PD11_S GPIO_PIN_DATA_S(3, 11) /*!< Specify PD.11 Pin Data Input/Output */ +#define PD12_S GPIO_PIN_DATA_S(3, 12) /*!< Specify PD.12 Pin Data Input/Output */ +#define PD14_S GPIO_PIN_DATA_S(3, 14) /*!< Specify PD.14 Pin Data Input/Output */ +#define PE0_S GPIO_PIN_DATA_S(4, 0 ) /*!< Specify PE.0 Pin Data Input/Output */ +#define PE1_S GPIO_PIN_DATA_S(4, 1 ) /*!< Specify PE.1 Pin Data Input/Output */ +#define PE2_S GPIO_PIN_DATA_S(4, 2 ) /*!< Specify PE.2 Pin Data Input/Output */ +#define PE3_S GPIO_PIN_DATA_S(4, 3 ) /*!< Specify PE.3 Pin Data Input/Output */ +#define PE4_S GPIO_PIN_DATA_S(4, 4 ) /*!< Specify PE.4 Pin Data Input/Output */ +#define PE5_S GPIO_PIN_DATA_S(4, 5 ) /*!< Specify PE.5 Pin Data Input/Output */ +#define PE6_S GPIO_PIN_DATA_S(4, 6 ) /*!< Specify PE.6 Pin Data Input/Output */ +#define PE7_S GPIO_PIN_DATA_S(4, 7 ) /*!< Specify PE.7 Pin Data Input/Output */ +#define PE8_S GPIO_PIN_DATA_S(4, 8 ) /*!< Specify PE.8 Pin Data Input/Output */ +#define PE9_S GPIO_PIN_DATA_S(4, 9 ) /*!< Specify PE.9 Pin Data Input/Output */ +#define PE10_S GPIO_PIN_DATA_S(4, 10) /*!< Specify PE.10 Pin Data Input/Output */ +#define PE11_S GPIO_PIN_DATA_S(4, 11) /*!< Specify PE.11 Pin Data Input/Output */ +#define PE12_S GPIO_PIN_DATA_S(4, 12) /*!< Specify PE.12 Pin Data Input/Output */ +#define PE13_S GPIO_PIN_DATA_S(4, 13) /*!< Specify PE.13 Pin Data Input/Output */ +#define PE14_S GPIO_PIN_DATA_S(4, 14) /*!< Specify PE.14 Pin Data Input/Output */ +#define PE15_S GPIO_PIN_DATA_S(4, 15) /*!< Specify PE.15 Pin Data Input/Output */ +#define PF0_S GPIO_PIN_DATA_S(5, 0 ) /*!< Specify PF.0 Pin Data Input/Output */ +#define PF1_S GPIO_PIN_DATA_S(5, 1 ) /*!< Specify PF.1 Pin Data Input/Output */ +#define PF2_S GPIO_PIN_DATA_S(5, 2 ) /*!< Specify PF.2 Pin Data Input/Output */ +#define PF3_S GPIO_PIN_DATA_S(5, 3 ) /*!< Specify PF.3 Pin Data Input/Output */ +#define PF4_S GPIO_PIN_DATA_S(5, 4 ) /*!< Specify PF.4 Pin Data Input/Output */ +#define PF5_S GPIO_PIN_DATA_S(5, 5 ) /*!< Specify PF.5 Pin Data Input/Output */ +#define PF6_S GPIO_PIN_DATA_S(5, 6 ) /*!< Specify PF.6 Pin Data Input/Output */ +#define PF7_S GPIO_PIN_DATA_S(5, 7 ) /*!< Specify PF.7 Pin Data Input/Output */ +#define PF8_S GPIO_PIN_DATA_S(5, 8 ) /*!< Specify PF.8 Pin Data Input/Output */ +#define PF9_S GPIO_PIN_DATA_S(5, 9 ) /*!< Specify PF.9 Pin Data Input/Output */ +#define PF10_S GPIO_PIN_DATA_S(5, 10) /*!< Specify PF.10 Pin Data Input/Output */ +#define PF11_S GPIO_PIN_DATA_S(5, 11) /*!< Specify PF.11 Pin Data Input/Output */ +#define PG2_S GPIO_PIN_DATA_S(6, 2 ) /*!< Specify PG.2 Pin Data Input/Output */ +#define PG3_S GPIO_PIN_DATA_S(6, 3 ) /*!< Specify PG.3 Pin Data Input/Output */ +#define PG4_S GPIO_PIN_DATA_S(6, 4 ) /*!< Specify PG.4 Pin Data Input/Output */ +#define PG9_S GPIO_PIN_DATA_S(6, 9 ) /*!< Specify PG.9 Pin Data Input/Output */ +#define PG10_S GPIO_PIN_DATA_S(6, 10) /*!< Specify PG.10 Pin Data Input/Output */ +#define PG11_S GPIO_PIN_DATA_S(6, 11) /*!< Specify PG.11 Pin Data Input/Output */ +#define PG12_S GPIO_PIN_DATA_S(6, 12) /*!< Specify PG.12 Pin Data Input/Output */ +#define PG13_S GPIO_PIN_DATA_S(6, 13) /*!< Specify PG.13 Pin Data Input/Output */ +#define PG14_S GPIO_PIN_DATA_S(6, 14) /*!< Specify PG.14 Pin Data Input/Output */ +#define PG15_S GPIO_PIN_DATA_S(6, 15) /*!< Specify PG.15 Pin Data Input/Output */ +#define PH4_S GPIO_PIN_DATA_S(7, 4 ) /*!< Specify PH.4 Pin Data Input/Output */ +#define PH5_S GPIO_PIN_DATA_S(7, 5 ) /*!< Specify PH.5 Pin Data Input/Output */ +#define PH6_S GPIO_PIN_DATA_S(7, 6 ) /*!< Specify PH.6 Pin Data Input/Output */ +#define PH7_S GPIO_PIN_DATA_S(7, 7 ) /*!< Specify PH.7 Pin Data Input/Output */ +#define PH8_S GPIO_PIN_DATA_S(7, 8 ) /*!< Specify PH.8 Pin Data Input/Output */ +#define PH9_S GPIO_PIN_DATA_S(7, 9 ) /*!< Specify PH.9 Pin Data Input/Output */ +#define PH10_S GPIO_PIN_DATA_S(7, 10) /*!< Specify PH.10 Pin Data Input/Output */ +#define PH11_S GPIO_PIN_DATA_S(7, 11) /*!< Specify PH.11 Pin Data Input/Output */ + +/* GPIO bit definitions for non-secure */ +#define GPIO_PIN_DATA_NS(port, pin) (*((volatile uint32_t *)((GPIO_PIN_DATA_BASE+NS_OFFSET+(0x40*(port))) + ((pin)<<2)))) +#define PA0_NS GPIO_PIN_DATA_NS(0, 0 ) /*!< Specify PA.0 Pin Data Input/Output */ +#define PA1_NS GPIO_PIN_DATA_NS(0, 1 ) /*!< Specify PA.1 Pin Data Input/Output */ +#define PA2_NS GPIO_PIN_DATA_NS(0, 2 ) /*!< Specify PA.2 Pin Data Input/Output */ +#define PA3_NS GPIO_PIN_DATA_NS(0, 3 ) /*!< Specify PA.3 Pin Data Input/Output */ +#define PA4_NS GPIO_PIN_DATA_NS(0, 4 ) /*!< Specify PA.4 Pin Data Input/Output */ +#define PA5_NS GPIO_PIN_DATA_NS(0, 5 ) /*!< Specify PA.5 Pin Data Input/Output */ +#define PA6_NS GPIO_PIN_DATA_NS(0, 6 ) /*!< Specify PA.6 Pin Data Input/Output */ +#define PA7_NS GPIO_PIN_DATA_NS(0, 7 ) /*!< Specify PA.7 Pin Data Input/Output */ +#define PA8_NS GPIO_PIN_DATA_NS(0, 8 ) /*!< Specify PA.8 Pin Data Input/Output */ +#define PA9_NS GPIO_PIN_DATA_NS(0, 9 ) /*!< Specify PA.9 Pin Data Input/Output */ +#define PA10_NS GPIO_PIN_DATA_NS(0, 10) /*!< Specify PA.10 Pin Data Input/Output */ +#define PA11_NS GPIO_PIN_DATA_NS(0, 11) /*!< Specify PA.11 Pin Data Input/Output */ +#define PA12_NS GPIO_PIN_DATA_NS(0, 12) /*!< Specify PA.12 Pin Data Input/Output */ +#define PA13_NS GPIO_PIN_DATA_NS(0, 13) /*!< Specify PA.13 Pin Data Input/Output */ +#define PA14_NS GPIO_PIN_DATA_NS(0, 14) /*!< Specify PA.14 Pin Data Input/Output */ +#define PA15_NS GPIO_PIN_DATA_NS(0, 15) /*!< Specify PA.15 Pin Data Input/Output */ +#define PB0_NS GPIO_PIN_DATA_NS(1, 0 ) /*!< Specify PB.0 Pin Data Input/Output */ +#define PB1_NS GPIO_PIN_DATA_NS(1, 1 ) /*!< Specify PB.1 Pin Data Input/Output */ +#define PB2_NS GPIO_PIN_DATA_NS(1, 2 ) /*!< Specify PB.2 Pin Data Input/Output */ +#define PB3_NS GPIO_PIN_DATA_NS(1, 3 ) /*!< Specify PB.3 Pin Data Input/Output */ +#define PB4_NS GPIO_PIN_DATA_NS(1, 4 ) /*!< Specify PB.4 Pin Data Input/Output */ +#define PB5_NS GPIO_PIN_DATA_NS(1, 5 ) /*!< Specify PB.5 Pin Data Input/Output */ +#define PB6_NS GPIO_PIN_DATA_NS(1, 6 ) /*!< Specify PB.6 Pin Data Input/Output */ +#define PB7_NS GPIO_PIN_DATA_NS(1, 7 ) /*!< Specify PB.7 Pin Data Input/Output */ +#define PB8_NS GPIO_PIN_DATA_NS(1, 8 ) /*!< Specify PB.8 Pin Data Input/Output */ +#define PB9_NS GPIO_PIN_DATA_NS(1, 9 ) /*!< Specify PB.9 Pin Data Input/Output */ +#define PB10_NS GPIO_PIN_DATA_NS(1, 10) /*!< Specify PB.10 Pin Data Input/Output */ +#define PB11_NS GPIO_PIN_DATA_NS(1, 11) /*!< Specify PB.11 Pin Data Input/Output */ +#define PB12_NS GPIO_PIN_DATA_NS(1, 12) /*!< Specify PB.12 Pin Data Input/Output */ +#define PB13_NS GPIO_PIN_DATA_NS(1, 13) /*!< Specify PB.13 Pin Data Input/Output */ +#define PB14_NS GPIO_PIN_DATA_NS(1, 14) /*!< Specify PB.14 Pin Data Input/Output */ +#define PB15_NS GPIO_PIN_DATA_NS(1, 15) /*!< Specify PB.15 Pin Data Input/Output */ +#define PC0_NS GPIO_PIN_DATA_NS(2, 0 ) /*!< Specify PC.0 Pin Data Input/Output */ +#define PC1_NS GPIO_PIN_DATA_NS(2, 1 ) /*!< Specify PC.1 Pin Data Input/Output */ +#define PC2_NS GPIO_PIN_DATA_NS(2, 2 ) /*!< Specify PC.2 Pin Data Input/Output */ +#define PC3_NS GPIO_PIN_DATA_NS(2, 3 ) /*!< Specify PC.3 Pin Data Input/Output */ +#define PC4_NS GPIO_PIN_DATA_NS(2, 4 ) /*!< Specify PC.4 Pin Data Input/Output */ +#define PC5_NS GPIO_PIN_DATA_NS(2, 5 ) /*!< Specify PC.5 Pin Data Input/Output */ +#define PC6_NS GPIO_PIN_DATA_NS(2, 6 ) /*!< Specify PC.6 Pin Data Input/Output */ +#define PC7_NS GPIO_PIN_DATA_NS(2, 7 ) /*!< Specify PC.7 Pin Data Input/Output */ +#define PC8_NS GPIO_PIN_DATA_NS(2, 8 ) /*!< Specify PC.8 Pin Data Input/Output */ +#define PC9_NS GPIO_PIN_DATA_NS(2, 9 ) /*!< Specify PC.9 Pin Data Input/Output */ +#define PC10_NS GPIO_PIN_DATA_NS(2, 10) /*!< Specify PC.10 Pin Data Input/Output */ +#define PC11_NS GPIO_PIN_DATA_NS(2, 11) /*!< Specify PC.11 Pin Data Input/Output */ +#define PC12_NS GPIO_PIN_DATA_NS(2, 12) /*!< Specify PC.12 Pin Data Input/Output */ +#define PC13_NS GPIO_PIN_DATA_NS(2, 13) /*!< Specify PC.13 Pin Data Input/Output */ +#define PD0_NS GPIO_PIN_DATA_NS(3, 0 ) /*!< Specify PD.0 Pin Data Input/Output */ +#define PD1_NS GPIO_PIN_DATA_NS(3, 1 ) /*!< Specify PD.1 Pin Data Input/Output */ +#define PD2_NS GPIO_PIN_DATA_NS(3, 2 ) /*!< Specify PD.2 Pin Data Input/Output */ +#define PD3_NS GPIO_PIN_DATA_NS(3, 3 ) /*!< Specify PD.3 Pin Data Input/Output */ +#define PD4_NS GPIO_PIN_DATA_NS(3, 4 ) /*!< Specify PD.4 Pin Data Input/Output */ +#define PD5_NS GPIO_PIN_DATA_NS(3, 5 ) /*!< Specify PD.5 Pin Data Input/Output */ +#define PD6_NS GPIO_PIN_DATA_NS(3, 6 ) /*!< Specify PD.6 Pin Data Input/Output */ +#define PD7_NS GPIO_PIN_DATA_NS(3, 7 ) /*!< Specify PD.7 Pin Data Input/Output */ +#define PD8_NS GPIO_PIN_DATA_NS(3, 8 ) /*!< Specify PD.8 Pin Data Input/Output */ +#define PD9_NS GPIO_PIN_DATA_NS(3, 9 ) /*!< Specify PD.9 Pin Data Input/Output */ +#define PD10_NS GPIO_PIN_DATA_NS(3, 10) /*!< Specify PD.10 Pin Data Input/Output */ +#define PD11_NS GPIO_PIN_DATA_NS(3, 11) /*!< Specify PD.11 Pin Data Input/Output */ +#define PD12_NS GPIO_PIN_DATA_NS(3, 12) /*!< Specify PD.12 Pin Data Input/Output */ +#define PD14_NS GPIO_PIN_DATA_NS(3, 14) /*!< Specify PD.14 Pin Data Input/Output */ +#define PE0_NS GPIO_PIN_DATA_NS(4, 0 ) /*!< Specify PE.0 Pin Data Input/Output */ +#define PE1_NS GPIO_PIN_DATA_NS(4, 1 ) /*!< Specify PE.1 Pin Data Input/Output */ +#define PE2_NS GPIO_PIN_DATA_NS(4, 2 ) /*!< Specify PE.2 Pin Data Input/Output */ +#define PE3_NS GPIO_PIN_DATA_NS(4, 3 ) /*!< Specify PE.3 Pin Data Input/Output */ +#define PE4_NS GPIO_PIN_DATA_NS(4, 4 ) /*!< Specify PE.4 Pin Data Input/Output */ +#define PE5_NS GPIO_PIN_DATA_NS(4, 5 ) /*!< Specify PE.5 Pin Data Input/Output */ +#define PE6_NS GPIO_PIN_DATA_NS(4, 6 ) /*!< Specify PE.6 Pin Data Input/Output */ +#define PE7_NS GPIO_PIN_DATA_NS(4, 7 ) /*!< Specify PE.7 Pin Data Input/Output */ +#define PE8_NS GPIO_PIN_DATA_NS(4, 8 ) /*!< Specify PE.8 Pin Data Input/Output */ +#define PE9_NS GPIO_PIN_DATA_NS(4, 9 ) /*!< Specify PE.9 Pin Data Input/Output */ +#define PE10_NS GPIO_PIN_DATA_NS(4, 10) /*!< Specify PE.10 Pin Data Input/Output */ +#define PE11_NS GPIO_PIN_DATA_NS(4, 11) /*!< Specify PE.11 Pin Data Input/Output */ +#define PE12_NS GPIO_PIN_DATA_NS(4, 12) /*!< Specify PE.12 Pin Data Input/Output */ +#define PE13_NS GPIO_PIN_DATA_NS(4, 13) /*!< Specify PE.13 Pin Data Input/Output */ +#define PE14_NS GPIO_PIN_DATA_NS(4, 14) /*!< Specify PE.14 Pin Data Input/Output */ +#define PE15_NS GPIO_PIN_DATA_NS(4, 15) /*!< Specify PE.15 Pin Data Input/Output */ +#define PF0_NS GPIO_PIN_DATA_NS(5, 0 ) /*!< Specify PF.0 Pin Data Input/Output */ +#define PF1_NS GPIO_PIN_DATA_NS(5, 1 ) /*!< Specify PF.1 Pin Data Input/Output */ +#define PF2_NS GPIO_PIN_DATA_NS(5, 2 ) /*!< Specify PF.2 Pin Data Input/Output */ +#define PF3_NS GPIO_PIN_DATA_NS(5, 3 ) /*!< Specify PF.3 Pin Data Input/Output */ +#define PF4_NS GPIO_PIN_DATA_NS(5, 4 ) /*!< Specify PF.4 Pin Data Input/Output */ +#define PF5_NS GPIO_PIN_DATA_NS(5, 5 ) /*!< Specify PF.5 Pin Data Input/Output */ +#define PF6_NS GPIO_PIN_DATA_NS(5, 6 ) /*!< Specify PF.6 Pin Data Input/Output */ +#define PF7_NS GPIO_PIN_DATA_NS(5, 7 ) /*!< Specify PF.7 Pin Data Input/Output */ +#define PF8_NS GPIO_PIN_DATA_NS(5, 8 ) /*!< Specify PF.8 Pin Data Input/Output */ +#define PF9_NS GPIO_PIN_DATA_NS(5, 9 ) /*!< Specify PF.9 Pin Data Input/Output */ +#define PF10_NS GPIO_PIN_DATA_NS(5, 10) /*!< Specify PF.10 Pin Data Input/Output */ +#define PF11_NS GPIO_PIN_DATA_NS(5, 11) /*!< Specify PF.11 Pin Data Input/Output */ +#define PG2_NS GPIO_PIN_DATA_NS(6, 2 ) /*!< Specify PG.2 Pin Data Input/Output */ +#define PG3_NS GPIO_PIN_DATA_NS(6, 3 ) /*!< Specify PG.3 Pin Data Input/Output */ +#define PG4_NS GPIO_PIN_DATA_NS(6, 4 ) /*!< Specify PG.4 Pin Data Input/Output */ +#define PG9_NS GPIO_PIN_DATA_NS(6, 9 ) /*!< Specify PG.9 Pin Data Input/Output */ +#define PG10_NS GPIO_PIN_DATA_NS(6, 10) /*!< Specify PG.10 Pin Data Input/Output */ +#define PG11_NS GPIO_PIN_DATA_NS(6, 11) /*!< Specify PG.11 Pin Data Input/Output */ +#define PG12_NS GPIO_PIN_DATA_NS(6, 12) /*!< Specify PG.12 Pin Data Input/Output */ +#define PG13_NS GPIO_PIN_DATA_NS(6, 13) /*!< Specify PG.13 Pin Data Input/Output */ +#define PG14_NS GPIO_PIN_DATA_NS(6, 14) /*!< Specify PG.14 Pin Data Input/Output */ +#define PG15_NS GPIO_PIN_DATA_NS(6, 15) /*!< Specify PG.15 Pin Data Input/Output */ +#define PH4_NS GPIO_PIN_DATA_NS(7, 4 ) /*!< Specify PH.4 Pin Data Input/Output */ +#define PH5_NS GPIO_PIN_DATA_NS(7, 5 ) /*!< Specify PH.5 Pin Data Input/Output */ +#define PH6_NS GPIO_PIN_DATA_NS(7, 6 ) /*!< Specify PH.6 Pin Data Input/Output */ +#define PH7_NS GPIO_PIN_DATA_NS(7, 7 ) /*!< Specify PH.7 Pin Data Input/Output */ +#define PH8_NS GPIO_PIN_DATA_NS(7, 8 ) /*!< Specify PH.8 Pin Data Input/Output */ +#define PH9_NS GPIO_PIN_DATA_NS(7, 9 ) /*!< Specify PH.9 Pin Data Input/Output */ +#define PH10_NS GPIO_PIN_DATA_NS(7, 10) /*!< Specify PH.10 Pin Data Input/Output */ +#define PH11_NS GPIO_PIN_DATA_NS(7, 11) /*!< Specify PH.11 Pin Data Input/Output */ + + +/**@}*/ /* end of group GPIO_EXPORTED_CONSTANTS */ + + +/** @addtogroup GPIO_EXPORTED_FUNCTIONS GPIO Exported Functions + @{ +*/ + +/** + * @brief Clear GPIO Pin Interrupt Flag + * + * @param[in] port GPIO port. It could be PA, PB, PC, PD, PE, PF, PG or PH. + * @param[in] u32PinMask The single or multiple pins of specified GPIO port. \n + * It could be BIT0 ~ BIT15 for PA, PB and PE. \n + * It could be BIT0 ~ BIT13 for PC. \n + * It could be BIT0 ~ BIT12, BIT14 for PD. \n + * It could be BIT0 ~ BIT11 for PF. \n + * It could be BIT2 ~ BIT3, BIT9 ~ BIT15 for PG. \n + * It could be BIT4 ~ BIT11 for PH. + * + * @return None + * + * @details Clear the interrupt status of specified GPIO pin. + */ +#define GPIO_CLR_INT_FLAG(port, u32PinMask) ((port)->INTSRC = (u32PinMask)) + +/** + * @brief Disable Pin De-bounce Function + * + * @param[in] port GPIO port. It could be PA, PB, PC, PD, PE, PF, PG or PH. + * @param[in] u32PinMask The single or multiple pins of specified GPIO port. \n + * It could be BIT0 ~ BIT15 for PA, PB and PE. \n + * It could be BIT0 ~ BIT13 for PC. \n + * It could be BIT0 ~ BIT12, BIT14 for PD. \n + * It could be BIT0 ~ BIT11 for PF. \n + * It could be BIT2 ~ BIT3, BIT9 ~ BIT15 for PG. \n + * It could be BIT4 ~ BIT11 for PH. + * + * @return None + * + * @details Disable the interrupt de-bounce function of specified GPIO pin. + */ +#define GPIO_DISABLE_DEBOUNCE(port, u32PinMask) ((port)->DBEN &= ~(u32PinMask)) + +/** + * @brief Enable Pin De-bounce Function + * + * @param[in] port GPIO port. It could be PA, PB, PC, PD, PE, PF, PG or PH. + * @param[in] u32PinMask The single or multiple pins of specified GPIO port. \n + * It could be BIT0 ~ BIT15 for PA, PB and PE. \n + * It could be BIT0 ~ BIT13 for PC. \n + * It could be BIT0 ~ BIT12, BIT14 for PD. \n + * It could be BIT0 ~ BIT11 for PF. \n + * It could be BIT2 ~ BIT3, BIT9 ~ BIT15 for PG. \n + * It could be BIT4 ~ BIT11 for PH. + * @return None + * + * @details Enable the interrupt de-bounce function of specified GPIO pin. + */ +#define GPIO_ENABLE_DEBOUNCE(port, u32PinMask) ((port)->DBEN |= (u32PinMask)) + +/** + * @brief Disable I/O Digital Input Path + * + * @param[in] port GPIO port. It could be PA, PB, PC, PD, PE, PF, PG or PH. + * @param[in] u32PinMask The single or multiple pins of specified GPIO port. \n + * It could be BIT0 ~ BIT15 for PA, PB and PE. \n + * It could be BIT0 ~ BIT13 for PC. \n + * It could be BIT0 ~ BIT12, BIT14 for PD. \n + * It could be BIT0 ~ BIT11 for PF. \n + * It could be BIT2 ~ BIT3, BIT9 ~ BIT15 for PG. \n + * It could be BIT4 ~ BIT11 for PH. + * + * @return None + * + * @details Disable I/O digital input path of specified GPIO pin. + */ +#define GPIO_DISABLE_DIGITAL_PATH(port, u32PinMask) ((port)->DINOFF |= ((u32PinMask)<<16)) + +/** + * @brief Enable I/O Digital Input Path + * + * @param[in] port GPIO port. It could be PA, PB, PC, PD, PE, PF, PG or PH. + * @param[in] u32PinMask The single or multiple pins of specified GPIO port. \n + * It could be BIT0 ~ BIT15 for PA, PB and PE. \n + * It could be BIT0 ~ BIT13 for PC. \n + * It could be BIT0 ~ BIT12, BIT14 for PD. \n + * It could be BIT0 ~ BIT11 for PF. \n + * It could be BIT2 ~ BIT3, BIT9 ~ BIT15 for PG. \n + * It could be BIT4 ~ BIT11 for PH. + * + * @return None + * + * @details Enable I/O digital input path of specified GPIO pin. + */ +#define GPIO_ENABLE_DIGITAL_PATH(port, u32PinMask) ((port)->DINOFF &= ~((u32PinMask)<<16)) + +/** + * @brief Disable I/O DOUT mask + * + * @param[in] port GPIO port. It could be PA, PB, PC, PD, PE, PF, PG or PH. + * @param[in] u32PinMask The single or multiple pins of specified GPIO port. \n + * It could be BIT0 ~ BIT15 for PA, PB and PE. \n + * It could be BIT0 ~ BIT13 for PC. \n + * It could be BIT0 ~ BIT12, BIT14 for PD. \n + * It could be BIT0 ~ BIT11 for PF. \n + * It could be BIT2 ~ BIT3, BIT9 ~ BIT15 for PG. \n + * It could be BIT4 ~ BIT11 for PH. + * + * @return None + * + * @details Disable I/O DOUT mask of specified GPIO pin. + */ +#define GPIO_DISABLE_DOUT_MASK(port, u32PinMask) ((port)->DATMSK &= ~(u32PinMask)) + +/** + * @brief Enable I/O DOUT mask + * + * @param[in] port GPIO port. It could be PA, PB, PC, PD, PE, PF, PG or PH. + * @param[in] u32PinMask The single or multiple pins of specified GPIO port. \n + * It could be BIT0 ~ BIT15 for PA, PB and PE. \n + * It could be BIT0 ~ BIT13 for PC. \n + * It could be BIT0 ~ BIT12, BIT14 for PD. \n + * It could be BIT0 ~ BIT11 for PF. \n + * It could be BIT2 ~ BIT3, BIT9 ~ BIT15 for PG. \n + * It could be BIT4 ~ BIT11 for PH. + * + * @return None + * + * @details Enable I/O DOUT mask of specified GPIO pin. + */ +#define GPIO_ENABLE_DOUT_MASK(port, u32PinMask) ((port)->DATMSK |= (u32PinMask)) + +/** + * @brief Get GPIO Pin Interrupt Flag + * + * @param[in] port GPIO port. It could be PA, PB, PC, PD, PE, PF, PG or PH. + * @param[in] u32PinMask The single or multiple pins of specified GPIO port. \n + * It could be BIT0 ~ BIT15 for PA, PB and PE. \n + * It could be BIT0 ~ BIT13 for PC. \n + * It could be BIT0 ~ BIT12, BIT14 for PD. \n + * It could be BIT0 ~ BIT11 for PF. \n + * It could be BIT2 ~ BIT3, BIT9 ~ BIT15 for PG. \n + * It could be BIT4 ~ BIT11 for PH. + * + * @retval 0 No interrupt at specified GPIO pin + * @retval 1 The specified GPIO pin generate an interrupt + * + * @details Get the interrupt status of specified GPIO pin. + */ +#define GPIO_GET_INT_FLAG(port, u32PinMask) ((port)->INTSRC & (u32PinMask)) + +/** + * @brief Set De-bounce Sampling Cycle Time + * + * @param[in] port GPIO port. It could be PA, PB, PC, PD, PE, PF, PG or PH. + * @param[in] u32ClkSrc The de-bounce counter clock source. It could be GPIO_DBCTL_DBCLKSRC_HCLK or GPIO_DBCTL_DBCLKSRC_LIRC. + * @param[in] u32ClkSel The de-bounce sampling cycle selection. It could be + * - \ref GPIO_DBCTL_DBCLKSEL_1 + * - \ref GPIO_DBCTL_DBCLKSEL_2 + * - \ref GPIO_DBCTL_DBCLKSEL_4 + * - \ref GPIO_DBCTL_DBCLKSEL_8 + * - \ref GPIO_DBCTL_DBCLKSEL_16 + * - \ref GPIO_DBCTL_DBCLKSEL_32 + * - \ref GPIO_DBCTL_DBCLKSEL_64 + * - \ref GPIO_DBCTL_DBCLKSEL_128 + * - \ref GPIO_DBCTL_DBCLKSEL_256 + * - \ref GPIO_DBCTL_DBCLKSEL_512 + * - \ref GPIO_DBCTL_DBCLKSEL_1024 + * - \ref GPIO_DBCTL_DBCLKSEL_2048 + * - \ref GPIO_DBCTL_DBCLKSEL_4096 + * - \ref GPIO_DBCTL_DBCLKSEL_8192 + * - \ref GPIO_DBCTL_DBCLKSEL_16384 + * - \ref GPIO_DBCTL_DBCLKSEL_32768 + * + * @return None + * + * @details Set the interrupt de-bounce sampling cycle time based on the debounce counter clock source. \n + * Example: _GPIO_SET_DEBOUNCE_TIME(PA, GPIO_DBCTL_DBCLKSRC_LIRC, GPIO_DBCTL_DBCLKSEL_4). \n + * It's meaning the De-debounce counter clock source is internal 10 KHz and sampling cycle selection is 4. \n + * Then the target de-bounce sampling cycle time is (4)*(1/(10*1000)) s = 4*0.0001 s = 400 us, + * and system will sampling interrupt input once per 400 us. + */ +#define GPIO_SET_DEBOUNCE_TIME(port, u32ClkSrc, u32ClkSel) ((port)->DBCTL = (GPIO_DBCTL_ICLKON_Msk | (u32ClkSrc) | (u32ClkSel))) + +/** + * @brief Get GPIO Port IN Data + * + * @param[in] port GPIO port. It could be PA, PB, PC, PD, PE, PF, PG or PH. + * + * @return The specified port data + * + * @details Get the PIN register of specified GPIO port. + */ +#define GPIO_GET_IN_DATA(port) ((port)->PIN) + +/** + * @brief Set GPIO Port OUT Data + * + * @param[in] port GPIO port. It could be PA, PB, PC, PD, PE, PF, PG or PH. + * @param[in] u32Data GPIO port data. + * + * @return None + * + * @details Set the Data into specified GPIO port. + */ +#define GPIO_SET_OUT_DATA(port, u32Data) ((port)->DOUT = (u32Data)) + +/** + * @brief Toggle Specified GPIO pin + * + * @param[in] u32Pin Pxy + * + * @return None + * + * @details Toggle the specified GPIO pint. + */ +#define GPIO_TOGGLE(u32Pin) ((u32Pin) ^= 1) + + +/** + * @brief Enable External GPIO interrupt + * + * @param[in] port GPIO port. It could be PA, PB, PC, PD, PE, PF, PG or PH. + * @param[in] u32Pin The pin of specified GPIO port. \n + * It could be 0 ~ 15 for PA, PB and PE. \n + * It could be 0 ~ 13 for PC GPIO port. \n + * It could be 0 ~ 12, 14 for PD GPIO port. \n + * It could be 0 ~ 11 for PF GPIO port. \n + * It could be 2 ~ 4, 9 ~ 15 for PG GPIO port. \n + * It could be 4 ~ 11 for PH GPIO port. + * @param[in] u32IntAttribs The interrupt attribute of specified GPIO pin. It could be + * - \ref GPIO_INT_RISING + * - \ref GPIO_INT_FALLING + * - \ref GPIO_INT_BOTH_EDGE + * - \ref GPIO_INT_HIGH + * - \ref GPIO_INT_LOW + * + * @return None + * + * @details This function is used to enable specified GPIO pin interrupt. + */ +#define GPIO_EnableEINT GPIO_EnableInt + +/** + * @brief Disable External GPIO interrupt + * + * @param[in] port GPIO port. It could be PA, PB, PC, PD, PE, PF, PG or PH. + * @param[in] u32Pin The pin of specified GPIO port. \n + * It could be 0 ~ 15 for PA, PB and PE. \n + * It could be 0 ~ 13 for PC GPIO port. \n + * It could be 0 ~ 12, 14 for PD GPIO port. \n + * It could be 0 ~ 11 for PF GPIO port. \n + * It could be 2 ~ 4, 9 ~ 15 for PG GPIO port. \n + * It could be 4 ~ 11 for PH GPIO port. + * + * @return None + * + * @details This function is used to enable specified GPIO pin interrupt. + */ +#define GPIO_DisableEINT GPIO_DisableInt + + +void GPIO_SetMode(GPIO_T *port, uint32_t u32PinMask, uint32_t u32Mode); +void GPIO_EnableInt(GPIO_T *port, uint32_t u32Pin, uint32_t u32IntAttribs); +void GPIO_DisableInt(GPIO_T *port, uint32_t u32Pin); +void GPIO_SetSlewCtl(GPIO_T *port, uint32_t u32PinMask, uint32_t u32Mode); +void GPIO_SetPullCtl(GPIO_T *port, uint32_t u32PinMask, uint32_t u32Mode); + + +/**@}*/ /* end of group GPIO_EXPORTED_FUNCTIONS */ + +/**@}*/ /* end of group GPIO_Driver */ + +/**@}*/ /* end of group Standard_Driver */ + +#ifdef __cplusplus +} +#endif + +#endif /* __NU_GPIO_H__ */ diff --git a/Ubiquitous/XiZi/board/nuvoton-m2354/third_party_driver/include/Drivers/nu_i2c.h b/Ubiquitous/XiZi/board/nuvoton-m2354/third_party_driver/include/Drivers/nu_i2c.h new file mode 100644 index 0000000..4ea5a45 --- /dev/null +++ b/Ubiquitous/XiZi/board/nuvoton-m2354/third_party_driver/include/Drivers/nu_i2c.h @@ -0,0 +1,523 @@ +/**************************************************************************//** + * @file nu_i2c.h + * @version V3.0 + * $Revision: 1 $ + * $Date: 16/07/07 7:50p $ + * @brief M2355 series I2C Serial Interface Controller(I2C) driver header file + * + * @copyright SPDX-License-Identifier: Apache-2.0 + * @copyright Copyright (C) 2020 Nuvoton Technology Corp. All rights reserved. + ******************************************************************************/ +#ifndef __NU_I2C_H__ +#define __NU_I2C_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup I2C_Driver I2C Driver + @{ +*/ + +/** @addtogroup I2C_EXPORTED_CONSTANTS I2C Exported Constants + @{ +*/ + +/*---------------------------------------------------------------------------------------------------------*/ +/* I2C_CTL constant definitions. */ +/*---------------------------------------------------------------------------------------------------------*/ +#define I2C_CTL_STA_SI (0x28U) /*!< I2C_CTL setting for I2C control bits. It would set STA and SI bits */ +#define I2C_CTL_STA_SI_AA (0x2CU) /*!< I2C_CTL setting for I2C control bits. It would set STA, SI and AA bits */ +#define I2C_CTL_STO_SI (0x18U) /*!< I2C_CTL setting for I2C control bits. It would set STO and SI bits */ +#define I2C_CTL_STO_SI_AA (0x1CU) /*!< I2C_CTL setting for I2C control bits. It would set STO, SI and AA bits */ +#define I2C_CTL_SI (0x08U) /*!< I2C_CTL setting for I2C control bits. It would set SI bit */ +#define I2C_CTL_SI_AA (0x0CU) /*!< I2C_CTL setting for I2C control bits. It would set SI and AA bits */ +#define I2C_CTL_STA (0x20U) /*!< I2C_CTL setting for I2C control bits. It would set STA bit */ +#define I2C_CTL_STO (0x10U) /*!< I2C_CTL setting for I2C control bits. It would set STO bit */ +#define I2C_CTL_AA (0x04U) /*!< I2C_CTL setting for I2C control bits. It would set AA bit */ + +/*---------------------------------------------------------------------------------------------------------*/ +/* I2C GCMode constant definitions. */ +/*---------------------------------------------------------------------------------------------------------*/ +#define I2C_GCMODE_ENABLE (1U) /*!< Enable I2C GC Mode */ +#define I2C_GCMODE_DISABLE (0U) /*!< Disable I2C GC Mode */ + +/*---------------------------------------------------------------------------------------------------------*/ +/* I2C SMBUS constant definitions. */ +/*---------------------------------------------------------------------------------------------------------*/ +#define I2C_SMBH_ENABLE (1U) /*!< Enable SMBus Host Mode enable */ +#define I2C_SMBD_ENABLE (0U) /*!< Enable SMBus Device Mode enable */ +#define I2C_PECTX_ENABLE (1U) /*!< Enable SMBus Packet Error Check Transmit function */ +#define I2C_PECTX_DISABLE (0U) /*!< Disable SMBus Packet Error Check Transmit function */ + +/**@}*/ /* end of group I2C_EXPORTED_CONSTANTS */ + +/** @addtogroup I2C_EXPORTED_FUNCTIONS I2C Exported Functions + @{ +*/ +/** + * @brief The macro is used to set I2C bus condition at One Time + * + * @param[in] i2c Specify I2C port + * @param[in] u8Ctrl A byte writes to I2C control register + * + * @return None + * + * @details Set I2C_CTL register to control I2C bus conditions of START, STOP, SI, ACK. + */ +#define I2C_SET_CONTROL_REG(i2c, u8Ctrl) ((i2c)->CTL0 = ((i2c)->CTL0 & ~0x3Cu) | (u8Ctrl)) + +/** + * @brief The macro is used to set START condition of I2C Bus + * + * @param[in] i2c Specify I2C port + * + * @return None + * + * @details Set the I2C bus START condition in I2C_CTL register. + */ +#define I2C_START(i2c) ((i2c)->CTL0 = ((i2c)->CTL0 | I2C_CTL0_SI_Msk) | I2C_CTL0_STA_Msk) + +/** + * @brief The macro is used to wait I2C bus status get ready + * + * @param[in] i2c Specify I2C port + * + * @return None + * + * @details When a new status is presented of I2C bus, the SI flag will be set in I2C_CTL register. + */ +#define I2C_WAIT_READY(i2c) while(!((i2c)->CTL0 & I2C_CTL0_SI_Msk)) + +/** + * @brief The macro is used to Read I2C Bus Data Register + * + * @param[in] i2c Specify I2C port + * + * @return A byte of I2C data register + * + * @details I2C controller read data from bus and save it in I2CDAT register. + */ +#define I2C_GET_DATA(i2c) ((i2c)->DAT) + +/** + * @brief Write a Data to I2C Data Register + * + * @param[in] i2c Specify I2C port + * @param[in] u8Data A byte that writes to data register + * + * @return None + * + * @details When write a data to I2C_DAT register, the I2C controller will shift it to I2C bus. + */ +#define I2C_SET_DATA(i2c, u8Data) ((i2c)->DAT = (u8Data)) + +/** + * @brief Get I2C Bus status code + * + * @param[in] i2c Specify I2C port + * + * @return I2C status code + * + * @details To get this status code to monitor I2C bus event. + */ +#define I2C_GET_STATUS(i2c) ((i2c)->STATUS0) + +/** + * @brief Get Time-out flag from I2C Bus + * + * @param[in] i2c Specify I2C port + * + * @retval 0 I2C Bus time-out is not happened + * @retval 1 I2C Bus time-out is happened + * + * @details When I2C bus occurs time-out event, the time-out flag will be set. + */ +#define I2C_GET_TIMEOUT_FLAG(i2c) ( ((i2c)->TOCTL & I2C_TOCTL_TOIF_Msk) == I2C_TOCTL_TOIF_Msk ? 1u : 0u) + +/** + * @brief To get wake-up flag from I2C Bus + * + * @param[in] i2c Specify I2C port + * + * @retval 0 Chip is not woken-up from power-down mode + * @retval 1 Chip is woken-up from power-down mode + * + * @details I2C bus occurs wake-up event, wake-up flag will be set. + */ +#define I2C_GET_WAKEUP_FLAG(i2c) ( ((i2c)->WKSTS & I2C_WKSTS_WKIF_Msk) == I2C_WKSTS_WKIF_Msk ? 1u : 0u) + +/** + * @brief To clear wake-up flag + * + * @param[in] i2c Specify I2C port + * + * @return None + * + * @details If wake-up flag is set, use this macro to clear it. + */ +#define I2C_CLEAR_WAKEUP_FLAG(i2c) ((i2c)->WKSTS = I2C_WKSTS_WKIF_Msk) + +/** + * @brief To get wake-up address frame ACK done flag from I2C Bus + * + * @param[in] i2c Specify I2C port + * + * @retval 0 The ACK bit cycle of address match frame is not done + * @retval 1 The ACK bit cycle of address match frame is done in power-down + * + * @details I2C bus occurs wake-up event and address frame ACK is done, this flag will be set. + * + * \hideinitializer + */ +#define I2C_GET_WAKEUP_DONE(i2c) ( ((i2c)->WKSTS & I2C_WKSTS_WKAKDONE_Msk) == I2C_WKSTS_WKAKDONE_Msk ? 1u : 0u) + +/** + * @brief To clear address frame ACK done flag + * + * @param[in] i2c Specify I2C port + * + * @return None + * + * @details If wake-up done is set, use this macro to clear it. + * + * \hideinitializer + */ +#define I2C_CLEAR_WAKEUP_DONE(i2c) ((i2c)->WKSTS = I2C_WKSTS_WKAKDONE_Msk) + +/** + * @brief To get read/write status bit in address wakeup frame + * + * @param[in] i2c Specify I2C port + * + * @retval 0 Write command be record on the address match wakeup frame + * @retval 1 Read command be record on the address match wakeup frame. + * + * @details I2C bus occurs wake-up event and address frame is received, this bit will record read/write status. + * + * \hideinitializer +*/ +#define I2C_GET_WAKEUP_WR_STATUS(i2c) ( ((i2c)->WKSTS & I2C_WKSTS_WRSTSWK_Msk) == I2C_WKSTS_WRSTSWK_Msk ? 1u : 0u) + +/** + * @brief To get SMBus Status + * + * @param[in] i2c Specify I2C port + * + * @return SMBus status + * + * @details To get the Bus Management status of I2C_BUSSTS register + * + */ +#define I2C_SMBUS_GET_STATUS(i2c) ((i2c)->BUSSTS) + +/** + * @brief Get SMBus CRC value + * + * @param[in] i2c Specify I2C port + * + * @return Packet error check byte value + * + * @details The CRC check value after a transmission or a reception by count by using CRC8 + * + */ +#define I2C_SMBUS_GET_PEC_VALUE(i2c) ((i2c)->PKTCRC) + +/** + * @brief Set SMBus Bytes number of Transmission or reception + * + * @param[in] i2c Specify I2C port + * @param[in] u32PktSize Transmit / Receive bytes + * + * @return None + * + * @details The transmission or receive byte number in one transaction when PECEN is set. The maximum is 255 bytes. + * + */ +#define I2C_SMBUS_SET_PACKET_BYTE_COUNT(i2c, u32PktSize) ((i2c)->PKTSIZE = (u32PktSize)) + +/** + * @brief Enable SMBus Alert function + * + * @param[in] i2c Specify I2C port + * + * @return None + * + * @details Device Mode(BMHEN=0): If ALERTEN(I2C_BUSCTL[4]) is set, the Alert pin will pull lo, and reply ACK when get ARP from host + * Host Mode(BMHEN=1): If ALERTEN(I2C_BUSCTL[4]) is set, the Alert pin is supported to receive alert state(Lo trigger) + * + */ +#define I2C_SMBUS_ENABLE_ALERT(i2c) ((i2c)->BUSCTL |= I2C_BUSCTL_ALERTEN_Msk) + +/** + * @brief Disable SMBus Alert pin function + * + * @param[in] i2c Specify I2C port + * + * @return None + * + * @details Device Mode(BMHEN=0): If ALERTEN(I2C_BUSCTL[4]) is clear, the Alert pin will pull hi, and reply NACK when get ARP from host + * Host Mode(BMHEN=1): If ALERTEN(I2C_BUSCTL[4]) is clear, the Alert pin is not supported to receive alert state(Lo trigger) + * + */ +#define I2C_SMBUS_DISABLE_ALERT(i2c) ((i2c)->BUSCTL &= ~I2C_BUSCTL_ALERTEN_Msk) + +/** + * @brief Set SMBus SUSCON pin is output mode + * + * @param[in] i2c Specify I2C port + * + * @return None + * + * @details This function to set SUSCON(I2C_BUSCTL[6]) pin is output mode. + * + * + */ +#define I2C_SMBUS_SET_SUSCON_OUT(i2c) ((i2c)->BUSCTL |= I2C_BUSCTL_SCTLOEN_Msk) + +/** + * @brief Set SMBus SUSCON pin is input mode + * + * @param[in] i2c Specify I2C port + * + * @return None + * + * @details This function to set SUSCON(I2C_BUSCTL[6]) pin is input mode. + * + * + */ +#define I2C_SMBUS_SET_SUSCON_IN(i2c) ((i2c)->BUSCTL &= ~I2C_BUSCTL_SCTLOEN_Msk) + +/** + * @brief Set SMBus SUSCON pin output high state + * + * @param[in] i2c Specify I2C port + * + * @return None + * + * @details This function to set SUSCON(I2C_BUSCTL[6]) pin is output hi state. + * + */ +#define I2C_SMBUS_SET_SUSCON_HIGH(i2c) ((i2c)->BUSCTL |= I2C_BUSCTL_SCTLOSTS_Msk) + + +/** + * @brief Set SMBus SUSCON pin output low state + * + * @param[in] i2c Specify I2C port + * + * @return None + * + * @details This function to set SUSCON(I2C_BUSCTL[6]) pin is output lo state. + * + */ +#define I2C_SMBUS_SET_SUSCON_LOW(i2c) ((i2c)->BUSCTL &= ~I2C_BUSCTL_SCTLOSTS_Msk) + +/** + * @brief Enable SMBus Acknowledge control by manual + * + * @param[in] i2c Specify I2C port + * + * @return None + * + * @details The 9th bit can response the ACK or NACK according the received data by user. When the byte is received, SCLK line stretching to low between the 8th and 9th SCLK pulse. + * + */ +#define I2C_SMBUS_ACK_MANUAL(i2c) ((i2c)->BUSCTL |= I2C_BUSCTL_ACKMEN_Msk) + +/** + * @brief Disable SMBus Acknowledge control by manual + * + * @param[in] i2c Specify I2C port + * + * @return None + * + * @details Disable acknowledge response control by user. + * + */ +#define I2C_SMBUS_ACK_AUTO(i2c) ((i2c)->BUSCTL &= ~I2C_BUSCTL_ACKMEN_Msk) + +/** + * @brief Enable SMBus Acknowledge manual interrupt + * + * @param[in] i2c Specify I2C port + * + * @return None + * + * @details This function is used to enable SMBUS acknowledge manual interrupt on the 9th clock cycle when SMBUS=1 and ACKMEN=1 + * + */ +#define I2C_SMBUS_9THBIT_INT_ENABLE(i2c) ((i2c)->BUSCTL |= I2C_BUSCTL_ACKM9SI_Msk) + +/** + * @brief Disable SMBus Acknowledge manual interrupt + * + * @param[in] i2c Specify I2C port + * + * @return None + * + * @details This function is used to disable SMBUS acknowledge manual interrupt on the 9th clock cycle when SMBUS=1 and ACKMEN=1 + * + */ +#define I2C_SMBUS_9THBIT_INT_DISABLE(i2c) ((i2c)->BUSCTL &= ~I2C_BUSCTL_ACKM9SI_Msk) + +/** + * @brief Enable SMBus PEC clear at REPEAT START + * + * @param[in] i2c Specify I2C port + * + * @return None + * + * @details This function is used to enable the condition of REAEAT START can clear the PEC calculation. + * + */ +#define I2C_SMBUS_RST_PEC_AT_START_ENABLE(i2c) ((i2c)->BUSCTL |= I2C_BUSCTL_PECCLR_Msk) + +/** + * @brief Disable SMBus PEC clear at Repeat START + * + * @param[in] i2c Specify I2C port + * + * @return None + * + * @details This function is used to disable the condition of Repeat START can clear the PEC calculation. + * + */ +#define I2C_SMBUS_RST_PEC_AT_START_DISABLE(i2c) ((i2c)->BUSCTL &= ~I2C_BUSCTL_PECCLR_Msk) + +/** + * @brief Enable RX PDMA function. + * @param[in] i2c The pointer of the specified I2C module. + * @return None. + * @details Set RXPDMAEN bit of I2C_CTL1 register to enable RX PDMA transfer function. + */ +#define I2C_ENABLE_RX_PDMA(i2c) ((i2c)->CTL1 |= I2C_CTL1_RXPDMAEN_Msk) + +/** + * @brief Enable TX PDMA function. + * @param[in] i2c The pointer of the specified I2C module. + * @return None. + * @details Set TXPDMAEN bit of I2C_CTL1 register to enable TX PDMA transfer function. + */ +#define I2C_ENABLE_TX_PDMA(i2c) ((i2c)->CTL1 |= I2C_CTL1_TXPDMAEN_Msk) + +/** + * @brief Disable RX PDMA transfer. + * @param[in] i2c The pointer of the specified I2C module. + * @return None. + * @details Clear RXPDMAEN bit of I2C_CTL1 register to disable RX PDMA transfer function. + */ +#define I2C_DISABLE_RX_PDMA(i2c) ((i2c)->CTL1 &= ~I2C_CTL1_RXPDMAEN_Msk) + +/** + * @brief Disable TX PDMA transfer. + * @param[in] i2c The pointer of the specified I2C module. + * @return None. + * @details Clear TXPDMAEN bit of I2C_CTL1 register to disable TX PDMA transfer function. + */ +#define I2C_DISABLE_TX_PDMA(i2c) ((i2c)->CTL1 &= ~I2C_CTL1_TXPDMAEN_Msk) + +/** + * @brief Enable PDMA stretch function. + * @param[in] i2c The pointer of the specified I2C module. + * @return None. + * @details Enable this function is to stretch bus by hardware after PDMA transfer is done if SI is not cleared. + */ +#define I2C_ENABLE_PDMA_STRETCH(i2c) ((i2c)->CTL1 |= I2C_CTL1_PDMASTR_Msk) + +/** + * @brief Disable PDMA stretch function. + * @param[in] i2c The pointer of the specified I2C module. + * @return None. + * @details I2C wil send STOP after PDMA transfers done automatically. + */ +#define I2C_DISABLE_PDMA_STRETCH(i2c) ((i2c)->CTL1 &= ~I2C_CTL1_PDMASTR_Msk) + +/** + * @brief Reset PDMA function. + * @param[in] i2c The pointer of the specified I2C module. + * @return None. + * @details I2C PDMA engine will be reset after this function is called. + */ +#define I2C_DISABLE_RST_PDMA(i2c) ((i2c)->CTL1 |= I2C_CTL1_PDMARST_Msk) + +/*---------------------------------------------------------------------------------------------------------*/ +/* inline functions */ +/*---------------------------------------------------------------------------------------------------------*/ +static __INLINE void I2C_STOP(I2C_T *i2c); + +/** + * @brief The macro is used to set STOP condition of I2C Bus + * + * @param[in] i2c Specify I2C port + * + * @return None + * + * @details Set the I2C bus STOP condition in I2C_CTL register. + */ +static __INLINE void I2C_STOP(I2C_T *i2c) +{ + + (i2c)->CTL0 |= (I2C_CTL0_SI_Msk | I2C_CTL0_STO_Msk); + while(i2c->CTL0 & I2C_CTL0_STO_Msk) {} +} + + +void I2C_ClearTimeoutFlag(I2C_T *i2c); +void I2C_Close(I2C_T *i2c); +void I2C_Trigger(I2C_T *i2c, uint8_t u8Start, uint8_t u8Stop, uint8_t u8Si, uint8_t u8Ack); +void I2C_DisableInt(I2C_T *i2c); +void I2C_EnableInt(I2C_T *i2c); +uint32_t I2C_GetBusClockFreq(I2C_T *i2c); +uint32_t I2C_GetIntFlag(I2C_T *i2c); +uint32_t I2C_GetStatus(I2C_T *i2c); +uint32_t I2C_Open(I2C_T *i2c, uint32_t u32BusClock); +uint8_t I2C_GetData(I2C_T *i2c); +void I2C_SetSlaveAddr(I2C_T *i2c, uint8_t u8SlaveNo, uint8_t u8SlaveAddr, uint8_t u8GCMode); +void I2C_SetSlaveAddrMask(I2C_T *i2c, uint8_t u8SlaveNo, uint8_t u8SlaveAddrMask); +uint32_t I2C_SetBusClockFreq(I2C_T *i2c, uint32_t u32BusClock); +void I2C_EnableTimeout(I2C_T *i2c, uint8_t u8LongTimeout); +void I2C_DisableTimeout(I2C_T *i2c); +void I2C_EnableWakeup(I2C_T *i2c); +void I2C_DisableWakeup(I2C_T *i2c); +void I2C_SetData(I2C_T *i2c, uint8_t u8Data); +uint8_t I2C_WriteByte(I2C_T *i2c, uint8_t u8SlaveAddr, uint8_t u8Data); +uint32_t I2C_WriteMultiBytes(I2C_T *i2c, uint8_t u8SlaveAddr, uint8_t au8Data[], uint32_t u32wLen); +uint8_t I2C_WriteByteOneReg(I2C_T *i2c, uint8_t u8SlaveAddr, uint8_t u8DataAddr, uint8_t u8Data); +uint32_t I2C_WriteMultiBytesOneReg(I2C_T *i2c, uint8_t u8SlaveAddr, uint8_t u8DataAddr, uint8_t au8Data[], uint32_t u32wLen); +uint8_t I2C_WriteByteTwoRegs(I2C_T *i2c, uint8_t u8SlaveAddr, uint16_t u16DataAddr, uint8_t u8Data); +uint32_t I2C_WriteMultiBytesTwoRegs(I2C_T *i2c, uint8_t u8SlaveAddr, uint16_t u16DataAddr, uint8_t au8Data[], uint32_t u32wLen); +uint8_t I2C_ReadByte(I2C_T *i2c, uint8_t u8SlaveAddr); +uint32_t I2C_ReadMultiBytes(I2C_T *i2c, uint8_t u8SlaveAddr, uint8_t au8Rdata[], uint32_t u32rLen); +uint8_t I2C_ReadByteOneReg(I2C_T *i2c, uint8_t u8SlaveAddr, uint8_t u8DataAddr); +uint32_t I2C_ReadMultiBytesOneReg(I2C_T *i2c, uint8_t u8SlaveAddr, uint8_t u8DataAddr, uint8_t au8Rdata[], uint32_t u32rLen); +uint8_t I2C_ReadByteTwoRegs(I2C_T *i2c, uint8_t u8SlaveAddr, uint16_t u16DataAddr); +uint32_t I2C_ReadMultiBytesTwoRegs(I2C_T *i2c, uint8_t u8SlaveAddr, uint16_t u16DataAddr, uint8_t au8Rdata[], uint32_t u32rLen); +uint32_t I2C_SMBusGetStatus(I2C_T *i2c); +void I2C_SMBusClearInterruptFlag(I2C_T *i2c, uint8_t u8ClrSMBusIntFlag); +void I2C_SMBusSetPacketByteCount(I2C_T *i2c, uint32_t u32PktSize); +void I2C_SMBusOpen(I2C_T *i2c, uint8_t u8HostDevice); +void I2C_SMBusClose(I2C_T *i2c); +void I2C_SMBusPECTxEnable(I2C_T *i2c, uint8_t u8PECTxEn); +uint8_t I2C_SMBusGetPECValue(I2C_T *i2c); +void I2C_SMBusIdleTimeout(I2C_T *i2c, uint32_t u32Us, uint32_t u32Hclk); +void I2C_SMBusTimeout(I2C_T *i2c, uint32_t ms, uint32_t u32Pclk); +void I2C_SMBusClockLoTimeout(I2C_T *i2c, uint32_t ms, uint32_t u32Pclk); + +/**@}*/ /* end of group I2C_EXPORTED_FUNCTIONS */ + +/**@}*/ /* end of group I2C_Driver */ + +/**@}*/ /* end of group Standard_Driver */ + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/Ubiquitous/XiZi/board/nuvoton-m2354/third_party_driver/include/Drivers/nu_i2s.h b/Ubiquitous/XiZi/board/nuvoton-m2354/third_party_driver/include/Drivers/nu_i2s.h new file mode 100644 index 0000000..b3ebe0c --- /dev/null +++ b/Ubiquitous/XiZi/board/nuvoton-m2354/third_party_driver/include/Drivers/nu_i2s.h @@ -0,0 +1,355 @@ +/****************************************************************************//** + * @file nu_i2s.h + * @version V3.00 + * @brief M2354 series I2S driver header file + * + * @copyright SPDX-License-Identifier: Apache-2.0 + * @copyright Copyright (C) 2020 Nuvoton Technology Corp. All rights reserved. +*****************************************************************************/ +#ifndef __NU_I2S_H__ +#define __NU_I2S_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup I2S_Driver I2S Driver + @{ +*/ + +/** @addtogroup I2S_EXPORTED_CONSTANTS I2S Exported Constants + @{ +*/ + +#define I2S_DATABIT_8 (0UL << I2S_CTL0_DATWIDTH_Pos) /*!< I2S data width is 8-bit \hideinitializer */ +#define I2S_DATABIT_16 (1UL << I2S_CTL0_DATWIDTH_Pos) /*!< I2S data width is 16-bit \hideinitializer */ +#define I2S_DATABIT_24 (2UL << I2S_CTL0_DATWIDTH_Pos) /*!< I2S data width is 24-bit \hideinitializer */ +#define I2S_DATABIT_32 (3UL << I2S_CTL0_DATWIDTH_Pos) /*!< I2S data width is 32-bit \hideinitializer */ + +/* Audio Format */ +#define I2S_MONO I2S_CTL0_MONO_Msk /*!< Mono channel \hideinitializer */ +#define I2S_STEREO (0UL) /*!< Stereo channel \hideinitializer */ +#define I2S_ENABLE_MONO I2S_MONO +#define I2S_DISABLE_MONO I2S_STEREO + +/* I2S Data Format */ +#define I2S_FORMAT_I2S (0UL << I2S_CTL0_FORMAT_Pos) /*!< I2S data format \hideinitializer */ +#define I2S_FORMAT_I2S_MSB (1UL << I2S_CTL0_FORMAT_Pos) /*!< I2S MSB data format \hideinitializer */ +#define I2S_FORMAT_I2S_LSB (2UL << I2S_CTL0_FORMAT_Pos) /*!< I2S LSB data format \hideinitializer */ +#define I2S_FORMAT_PCM (4UL << I2S_CTL0_FORMAT_Pos) /*!< PCM data format \hideinitializer */ +#define I2S_FORMAT_PCM_MSB (5UL << I2S_CTL0_FORMAT_Pos) /*!< PCM MSB data format \hideinitializer */ +#define I2S_FORMAT_PCM_LSB (6UL << I2S_CTL0_FORMAT_Pos) /*!< PCM LSB data format \hideinitializer */ + +/* I2S Data Format */ +#define I2S_ORDER_AT_MSB 0UL /*!< Channel data is at MSB \hideinitializer */ +#define I2S_ORDER_AT_LSB I2S_CTL0_ORDER_Msk /*!< Channel data is at LSB \hideinitializer */ + +/* I2S TDM Channel Number */ +#define I2S_TDM_2CH 0UL /*!< Use TDM 2 channel \hideinitializer */ +#define I2S_TDM_4CH 1UL /*!< Use TDM 4 channel \hideinitializer */ +#define I2S_TDM_6CH 2UL /*!< Use TDM 6 channel \hideinitializer */ +#define I2S_TDM_8CH 3UL /*!< Use TDM 8 channel \hideinitializer */ + +/* I2S TDM Channel Width */ +#define I2S_TDM_WIDTH_8BIT 0UL /*!< TDM channel witch is 8-bit \hideinitializer */ +#define I2S_TDM_WIDTH_16BIT 1UL /*!< TDM channel witch is 16-bit \hideinitializer */ +#define I2S_TDM_WIDTH_24BIT 2UL /*!< TDM channel witch is 24-bit \hideinitializer */ +#define I2S_TDM_WIDTH_32BIT 3UL /*!< TDM channel witch is 32-bit \hideinitializer */ + +/* I2S TDM Sync Width */ +#define I2S_TDM_SYNC_ONE_BCLK 0UL /*!< TDM sync widht is one BLCK period \hideinitializer */ +#define I2S_TDM_SYNC_ONE_CHANNEL 1UL /*!< TDM sync widht is one channel period \hideinitializer */ + +/* I2S Operation mode */ +#define I2S_MODE_SLAVE I2S_CTL0_SLAVE_Msk /*!< As slave mode \hideinitializer */ +#define I2S_MODE_MASTER 0UL /*!< As master mode \hideinitializer */ + +/* I2S FIFO Threshold */ +#define I2S_FIFO_TX_LEVEL_WORD_0 0UL /*!< TX threshold is 0 word \hideinitializer */ +#define I2S_FIFO_TX_LEVEL_WORD_1 (1UL << I2S_CTL1_TXTH_Pos) /*!< TX threshold is 1 word \hideinitializer */ +#define I2S_FIFO_TX_LEVEL_WORD_2 (2UL << I2S_CTL1_TXTH_Pos) /*!< TX threshold is 2 words \hideinitializer */ +#define I2S_FIFO_TX_LEVEL_WORD_3 (3UL << I2S_CTL1_TXTH_Pos) /*!< TX threshold is 3 words \hideinitializer */ +#define I2S_FIFO_TX_LEVEL_WORD_4 (4UL << I2S_CTL1_TXTH_Pos) /*!< TX threshold is 4 words \hideinitializer */ +#define I2S_FIFO_TX_LEVEL_WORD_5 (5UL << I2S_CTL1_TXTH_Pos) /*!< TX threshold is 5 words \hideinitializer */ +#define I2S_FIFO_TX_LEVEL_WORD_6 (6UL << I2S_CTL1_TXTH_Pos) /*!< TX threshold is 6 words \hideinitializer */ +#define I2S_FIFO_TX_LEVEL_WORD_7 (7UL << I2S_CTL1_TXTH_Pos) /*!< TX threshold is 7 words \hideinitializer */ +#define I2S_FIFO_TX_LEVEL_WORD_8 (8UL << I2S_CTL1_TXTH_Pos) /*!< TX threshold is 8 words \hideinitializer */ +#define I2S_FIFO_TX_LEVEL_WORD_9 (9UL << I2S_CTL1_TXTH_Pos) /*!< TX threshold is 9 words \hideinitializer */ +#define I2S_FIFO_TX_LEVEL_WORD_10 (10UL << I2S_CTL1_TXTH_Pos) /*!< TX threshold is 10 words \hideinitializer */ +#define I2S_FIFO_TX_LEVEL_WORD_11 (11UL << I2S_CTL1_TXTH_Pos) /*!< TX threshold is 11 words \hideinitializer */ +#define I2S_FIFO_TX_LEVEL_WORD_12 (12UL << I2S_CTL1_TXTH_Pos) /*!< TX threshold is 12 words \hideinitializer */ +#define I2S_FIFO_TX_LEVEL_WORD_13 (13UL << I2S_CTL1_TXTH_Pos) /*!< TX threshold is 13 words \hideinitializer */ +#define I2S_FIFO_TX_LEVEL_WORD_14 (14UL << I2S_CTL1_TXTH_Pos) /*!< TX threshold is 14 words \hideinitializer */ +#define I2S_FIFO_TX_LEVEL_WORD_15 (15UL << I2S_CTL1_TXTH_Pos) /*!< TX threshold is 15 words \hideinitializer */ + +#define I2S_FIFO_RX_LEVEL_WORD_1 0UL /*!< RX threshold is 1 word \hideinitializer */ +#define I2S_FIFO_RX_LEVEL_WORD_2 (1UL << I2S_CTL1_RXTH_Pos) /*!< RX threshold is 2 words \hideinitializer */ +#define I2S_FIFO_RX_LEVEL_WORD_3 (2UL << I2S_CTL1_RXTH_Pos) /*!< RX threshold is 3 words \hideinitializer */ +#define I2S_FIFO_RX_LEVEL_WORD_4 (3UL << I2S_CTL1_RXTH_Pos) /*!< RX threshold is 4 words \hideinitializer */ +#define I2S_FIFO_RX_LEVEL_WORD_5 (4UL << I2S_CTL1_RXTH_Pos) /*!< RX threshold is 5 words \hideinitializer */ +#define I2S_FIFO_RX_LEVEL_WORD_6 (5UL << I2S_CTL1_RXTH_Pos) /*!< RX threshold is 6 words \hideinitializer */ +#define I2S_FIFO_RX_LEVEL_WORD_7 (6UL << I2S_CTL1_RXTH_Pos) /*!< RX threshold is 7 words \hideinitializer */ +#define I2S_FIFO_RX_LEVEL_WORD_8 (7UL << I2S_CTL1_RXTH_Pos) /*!< RX threshold is 8 words \hideinitializer */ +#define I2S_FIFO_RX_LEVEL_WORD_9 (8UL << I2S_CTL1_RXTH_Pos) /*!< RX threshold is 9 words \hideinitializer */ +#define I2S_FIFO_RX_LEVEL_WORD_10 (9UL << I2S_CTL1_RXTH_Pos) /*!< RX threshold is 10 words \hideinitializer */ +#define I2S_FIFO_RX_LEVEL_WORD_11 (10UL << I2S_CTL1_RXTH_Pos) /*!< RX threshold is 11 words \hideinitializer */ +#define I2S_FIFO_RX_LEVEL_WORD_12 (11UL << I2S_CTL1_RXTH_Pos) /*!< RX threshold is 12 words \hideinitializer */ +#define I2S_FIFO_RX_LEVEL_WORD_13 (12UL << I2S_CTL1_RXTH_Pos) /*!< RX threshold is 13 words \hideinitializer */ +#define I2S_FIFO_RX_LEVEL_WORD_14 (13UL << I2S_CTL1_RXTH_Pos) /*!< RX threshold is 14 words \hideinitializer */ +#define I2S_FIFO_RX_LEVEL_WORD_15 (14UL << I2S_CTL1_RXTH_Pos) /*!< RX threshold is 15 words \hideinitializer */ +#define I2S_FIFO_RX_LEVEL_WORD_16 (15UL << I2S_CTL1_RXTH_Pos) /*!< RX threshold is 16 words \hideinitializer */ + +/* I2S Record Channel */ +#define I2S_MONO_RIGHT 0UL /*!< Record mono right channel \hideinitializer */ +#define I2S_MONO_LEFT I2S_CTL0_RXLCH_Msk /*!< Record mono left channel \hideinitializer */ + +/* I2S Channel */ +#define I2S_RIGHT 0UL /*!< Select right channel \hideinitializer */ +#define I2S_LEFT 1UL /*!< Select left channel \hideinitializer */ + +/**@}*/ /* end of group I2S_EXPORTED_CONSTANTS */ + + +/** @addtogroup I2S_EXPORTED_FUNCTIONS I2S Exported Functions + @{ +*/ + + +/** + * @brief Enable zero cross detect function. + * @param[in] i2s is the base address of I2S module. + * @param[in] u32ChMask is the mask for channel number (valid value is from (1~8). + * @return none + * \hideinitializer + */ +__STATIC_INLINE void I2S_ENABLE_TX_ZCD(I2S_T *i2s, uint32_t u32ChMask) +{ + if((u32ChMask > 0UL) && (u32ChMask < 9UL)) + { + i2s->CTL1 |= (1UL << (u32ChMask - 1UL)); + } +} + +/** + * @brief Disable zero cross detect function. + * @param[in] i2s is the base address of I2S module. + * @param[in] u32ChMask is the mask for channel number (valid value is from (1~8). + * @return none + * \hideinitializer + */ +__STATIC_INLINE void I2S_DISABLE_TX_ZCD(I2S_T *i2s, uint32_t u32ChMask) +{ + if((u32ChMask > 0UL) && (u32ChMask < 9UL)) + { + i2s->CTL1 &= ~(1UL << (u32ChMask - 1UL)); + } +} + +/** + * @brief Enable I2S Tx DMA function. I2S requests DMA to transfer data to Tx FIFO. + * @param[in] i2s is the base address of I2S module. + * @return none + * \hideinitializer + */ +#define I2S_ENABLE_TXDMA(i2s) ( (i2s)->CTL0 |= I2S_CTL0_TXPDMAEN_Msk ) + +/** + * @brief Disable I2S Tx DMA function. I2S requests DMA to transfer data to Tx FIFO. + * @param[in] i2s is the base address of I2S module. + * @return none + * \hideinitializer + */ +#define I2S_DISABLE_TXDMA(i2s) ( (i2s)->CTL0 &= ~I2S_CTL0_TXPDMAEN_Msk ) + +/** + * @brief Enable I2S Rx DMA function. I2S requests DMA to transfer data from Rx FIFO. + * @param[in] i2s is the base address of I2S module. + * @return none + * \hideinitializer + */ +#define I2S_ENABLE_RXDMA(i2s) ( (i2s)->CTL0 |= I2S_CTL0_RXPDMAEN_Msk ) + +/** + * @brief Disable I2S Rx DMA function. I2S requests DMA to transfer data from Rx FIFO. + * @param[in] i2s is the base address of I2S module. + * @return none + * \hideinitializer + */ +#define I2S_DISABLE_RXDMA(i2s) ( (i2s)->CTL0 &= ~I2S_CTL0_RXPDMAEN_Msk ) + +/** + * @brief Enable I2S Tx function . + * @param[in] i2s is the base address of I2S module. + * @return none + * \hideinitializer + */ +#define I2S_ENABLE_TX(i2s) ( (i2s)->CTL0 |= I2S_CTL0_TXEN_Msk ) + +/** + * @brief Disable I2S Tx function . + * @param[in] i2s is the base address of I2S module. + * @return none + * \hideinitializer + */ +#define I2S_DISABLE_TX(i2s) ( (i2s)->CTL0 &= ~I2S_CTL0_TXEN_Msk ) + +/** + * @brief Enable I2S Rx function . + * @param[in] i2s is the base address of I2S module. + * @return none + * \hideinitializer + */ +#define I2S_ENABLE_RX(i2s) ( (i2s)->CTL0 |= I2S_CTL0_RXEN_Msk ) + +/** + * @brief Disable I2S Rx function . + * @param[in] i2s is the base address of I2S module. + * @return none + * \hideinitializer + */ +#define I2S_DISABLE_RX(i2s) ( (i2s)->CTL0 &= ~I2S_CTL0_RXEN_Msk ) + +/** + * @brief Enable Tx Mute function . + * @param[in] i2s is the base address of I2S module. + * @return none + * \hideinitializer + */ +#define I2S_ENABLE_TX_MUTE(i2s) ( (i2s)->CTL0 |= I2S_CTL0_MUTE_Msk ) + +/** + * @brief Disable Tx Mute function . + * @param[in] i2s is the base address of I2S module. + * @return none + * \hideinitializer + */ +#define I2S_DISABLE_TX_MUTE(i2s) ( (i2s)->CTL0 &= ~I2S_CTL0_MUTE_Msk ) + +/** + * @brief Clear Tx FIFO. Internal pointer is reset to FIFO start point. + * @param[in] i2s is the base address of I2S module. + * @return none + * \hideinitializer + */ +#define I2S_CLR_TX_FIFO(i2s) ( (i2s)->CTL0 |= I2S_CTL0_TXFBCLR_Msk ) + +/** + * @brief Clear Rx FIFO. Internal pointer is reset to FIFO start point. + * @param[in] i2s is the base address of I2S module. + * @return none + * \hideinitializer + */ +#define I2S_CLR_RX_FIFO(i2s) ( (i2s)->CTL0 |= I2S_CTL0_RXFBCLR_Msk ) + +/** + * @brief This function sets the recording source channel when mono mode is used. + * @param[in] i2s is the base address of I2S module. + * @param[in] u32Ch left or right channel. Valid values are: + * - \ref I2S_MONO_LEFT + * - \ref I2S_MONO_RIGHT + * @return none + * \hideinitializer + */ +__STATIC_INLINE void I2S_SET_MONO_RX_CHANNEL(I2S_T *i2s, uint32_t u32Ch) +{ + u32Ch == I2S_MONO_LEFT ? + (i2s->CTL0 |= I2S_CTL0_RXLCH_Msk) : + (i2s->CTL0 &= ~I2S_CTL0_RXLCH_Msk); +} + +/** + * @brief Write data to I2S Tx FIFO. + * @param[in] i2s is the base address of I2S module. + * @param[in] u32Data: The data written to FIFO. + * @return none + * \hideinitializer + */ +#define I2S_WRITE_TX_FIFO(i2s, u32Data) ( (i2s)->TXFIFO = (u32Data) ) + +/** + * @brief Read Rx FIFO. + * @param[in] i2s is the base address of I2S module. + * @return Data in Rx FIFO. + * \hideinitializer + */ +#define I2S_READ_RX_FIFO(i2s) ( (i2s)->RXFIFO ) + +/** + * @brief This function gets the interrupt flag according to the mask parameter. + * @param[in] i2s is the base address of I2S module. + * @param[in] u32Mask is the mask for the all interrupt flags. + * @return The masked bit value of interrupt flag. + * \hideinitializer + */ +#define I2S_GET_INT_FLAG(i2s, u32Mask) ( (i2s)->STATUS0 & (u32Mask) ) + +/** + * @brief This function clears the interrupt flag according to the mask parameter. + * @param[in] i2s is the base address of I2S module. + * @param[in] u32Mask is the mask for the all interrupt flags. + * @return none + * \hideinitializer + */ +#define I2S_CLR_INT_FLAG(i2s, u32Mask) ( (i2s)->STATUS0 |= (u32Mask) ) + +/** + * @brief This function gets the zero crossing interrupt flag according to the mask parameter. + * @param[in] i2s is the base address of I2S module. + * @param[in] u32Mask is the mask for the all interrupt flags. + * @return The masked bit value of interrupt flag. + * \hideinitializer + */ +#define I2S_GET_ZC_INT_FLAG(i2s, u32Mask) ( (i2s)->STATUS1 & (u32Mask) ) + +/** + * @brief This function clears the zero crossing interrupt flag according to the mask parameter. + * @param[in] i2s is the base address of I2S module. + * @param[in] u32Mask is the mask for the all interrupt flags. + * @return none + * \hideinitializer + */ +#define I2S_CLR_ZC_INT_FLAG(i2s, u32Mask) ( (i2s)->STATUS1 |= (u32Mask) ) + +/** + * @brief Get transmit FIFO level + * @param[in] i2s is the base address of I2S module. + * @return FIFO level + * \hideinitializer + */ +#define I2S_GET_TX_FIFO_LEVEL(i2s) ( (((i2s)->STATUS1 & I2S_STATUS1_TXCNT_Msk) >> I2S_STATUS1_TXCNT_Pos) & 0xF ) + +/** + * @brief Get receive FIFO level + * @param[in] i2s is the base address of I2S module. + * @return FIFO level + * \hideinitializer + */ +#define I2S_GET_RX_FIFO_LEVEL(i2s) ( (((i2s)->STATUS1 & I2S_STATUS1_RXCNT_Msk) >> I2S_STATUS1_RXCNT_Pos) & 0xF ) + +uint32_t I2S_Open(I2S_T *i2s, uint32_t u32MasterSlave, uint32_t u32SampleRate, uint32_t u32WordWidth, uint32_t u32MonoData, uint32_t u32DataFormat); +void I2S_Close(I2S_T *i2s); +void I2S_EnableInt(I2S_T *i2s, uint32_t u32Mask); +void I2S_DisableInt(I2S_T *i2s, uint32_t u32Mask); +uint32_t I2S_EnableMCLK(I2S_T *i2s, uint32_t u32BusClock); +void I2S_DisableMCLK(I2S_T *i2s); +void I2S_SetFIFO(I2S_T *i2s, uint32_t u32TxThreshold, uint32_t u32RxThreshold); +void I2S_ConfigureTDM(I2S_T *i2s, uint32_t u32ChannelWidth, uint32_t u32ChannelNum, uint32_t u32SyncWidth); + + +/**@}*/ /* end of group I2S_EXPORTED_FUNCTIONS */ + +/**@}*/ /* end of group I2S_Driver */ + +/**@}*/ /* end of group Standard_Driver */ + +#ifdef __cplusplus +} +#endif + +#endif /* __NU_I2S_H__ */ diff --git a/Ubiquitous/XiZi/board/nuvoton-m2354/third_party_driver/include/Drivers/nu_keystore.h b/Ubiquitous/XiZi/board/nuvoton-m2354/third_party_driver/include/Drivers/nu_keystore.h new file mode 100644 index 0000000..eb055a3 --- /dev/null +++ b/Ubiquitous/XiZi/board/nuvoton-m2354/third_party_driver/include/Drivers/nu_keystore.h @@ -0,0 +1,132 @@ +/**************************************************************************//** + * @file nu_keystore.h + * @version V3.00 + * @brief Key Store Driver Header + * + * @copyright SPDX-License-Identifier: Apache-2.0 + * @copyright Copyright (C) 2020 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ +#ifndef __NU_KEYSTORE_H__ +#define __NU_KEYSTORE_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup KS_Driver Key Store Driver + @{ +*/ + +/** @addtogroup KS_EXPORTED_CONSTANTS Key Store Exported Constants + @{ +*/ + +#define KS_TOMETAKEY(x) (((uint32_t)(x) << KS_METADATA_NUMBER_Pos) & KS_METADATA_NUMBER_Msk) +#define KS_TOKEYIDX(x) (((uint32_t)(x) & KS_METADATA_NUMBER_Msk) >> KS_METADATA_NUMBER_Pos) + +typedef enum KSMEM +{ + KS_SRAM = 0, /*!< Volatile Memory */ + KS_FLASH = 1, /*!< Non-volatile Memory */ + KS_OTP = 2 /*!< One-Time Programming Memory */ +} KS_MEM_Type; + +#define KS_OP_READ (0 << KS_CTL_OPMODE_Pos) +#define KS_OP_WRITE (1 << KS_CTL_OPMODE_Pos) +#define KS_OP_ERASE (2 << KS_CTL_OPMODE_Pos) +#define KS_OP_ERASE_ALL (3 << KS_CTL_OPMODE_Pos) +#define KS_OP_REVOKE (4 << KS_CTL_OPMODE_Pos) +#define KS_OP_REMAN (5 << KS_CTL_OPMODE_Pos) + +#define KS_OWNER_AES (0ul) +#define KS_OWNER_HMAC (1ul) +#define KS_OWNER_RSA_EXP (2ul) +#define KS_OWNER_RSA_MID (3ul) +#define KS_OWNER_ECC (4ul) +#define KS_OWNER_CPU (5ul) + +#define KS_META_AES (0ul << KS_METADATA_OWNER_Pos) /*!< AES Access Only */ +#define KS_META_HMAC (1ul << KS_METADATA_OWNER_Pos) /*!< HMAC Access Only */ +#define KS_META_RSA_EXP (2ul << KS_METADATA_OWNER_Pos) /*!< RSA_EXP Access Only */ +#define KS_META_RSA_MID (3ul << KS_METADATA_OWNER_Pos) /*!< RSA_MID Access Only */ +#define KS_META_ECC (4ul << KS_METADATA_OWNER_Pos) /*!< ECC Access Only */ +#define KS_META_CPU (5ul << KS_METADATA_OWNER_Pos) /*!< CPU Access Only */ + +#define KS_META_128 ( 0ul << KS_METADATA_SIZE_Pos) /*!< Key size 128 bits */ +#define KS_META_163 ( 1ul << KS_METADATA_SIZE_Pos) /*!< Key size 163 bits */ +#define KS_META_192 ( 2ul << KS_METADATA_SIZE_Pos) /*!< Key size 192 bits */ +#define KS_META_224 ( 3ul << KS_METADATA_SIZE_Pos) /*!< Key size 224 bits */ +#define KS_META_233 ( 4ul << KS_METADATA_SIZE_Pos) /*!< Key size 233 bits */ +#define KS_META_255 ( 5ul << KS_METADATA_SIZE_Pos) /*!< Key size 255 bits */ +#define KS_META_256 ( 6ul << KS_METADATA_SIZE_Pos) /*!< Key size 256 bits */ +#define KS_META_283 ( 7ul << KS_METADATA_SIZE_Pos) /*!< Key size 283 bits */ +#define KS_META_384 ( 8ul << KS_METADATA_SIZE_Pos) /*!< Key size 384 bits */ +#define KS_META_409 ( 9ul << KS_METADATA_SIZE_Pos) /*!< Key size 409 bits */ +#define KS_META_512 (10ul << KS_METADATA_SIZE_Pos) /*!< Key size 512 bits */ +#define KS_META_521 (11ul << KS_METADATA_SIZE_Pos) /*!< Key size 521 bits */ +#define KS_META_571 (12ul << KS_METADATA_SIZE_Pos) /*!< Key size 571 bits */ +#define KS_META_1024 (16ul << KS_METADATA_SIZE_Pos) /*!< Key size 1024 bits */ +#define KS_META_1536 (17ul << KS_METADATA_SIZE_Pos) /*!< Key size 1024 bits */ +#define KS_META_2048 (18ul << KS_METADATA_SIZE_Pos) /*!< Key size 2048 bits */ +#define KS_META_3072 (19ul << KS_METADATA_SIZE_Pos) /*!< Key size 1024 bits */ +#define KS_META_4096 (20ul << KS_METADATA_SIZE_Pos) /*!< Key size 4096 bits */ + +#define KS_META_BOOT ( 1ul << KS_METADATA_BS_Pos) /*!< Key only used for boot ROM only */ + +#define KS_META_READABLE (1ul << KS_METADATA_READABLE_Pos) /*!< Allow the key to be read by software */ + +#define KS_META_PRIV (1ul << KS_METADATA_PRIV_Pos) /*!< Privilege key */ +#define KS_META_NONPRIV (0ul << KS_METADATA_PRIV_Pos) /*!< Non-privilege key */ + +#define KS_META_SECURE (1ul << KS_METADATA_SEC_Pos) /*!< Secure key */ +#define KS_META_NONSECURE (0ul << KS_METADATA_SEC_Pos) /*!< Non-secure key */ + + +/** + * @brief Enable scramble function + * @details This function is used to enable scramle function of Key Store. + */ + +#define KS_SCRAMBLING() KS->CTL |= KS_CTL_SCMB_Msk + + + + +/**@}*/ /* end of group KS_EXPORTED_CONSTANTS */ + + +/** @addtogroup KS_EXPORTED_FUNCTIONS Key Store Exported Functions + @{ +*/ + +void KS_Open(void); +int32_t KS_Read(KS_MEM_Type type, int32_t i32KeyIdx, uint32_t au32Key[], uint32_t u32WordCnt); +int32_t KS_Write(KS_MEM_Type eType, uint32_t u32Meta, uint32_t au32Key[]); +int32_t KS_WriteOTP(int32_t i32KeyIdx, uint32_t u32Meta, uint32_t au32Key[]); +int32_t KS_EraseKey(int32_t i32KeyIdx); +int32_t KS_EraseAll(KS_MEM_Type eType); +int32_t KS_RevokeKey(KS_MEM_Type eType, int32_t i32KeyIdx); +uint32_t KS_GetRemainSize(KS_MEM_Type eType); +int32_t KS_ToggleSRAM(void); +uint32_t KS_GetKeyWordCnt(uint32_t u32Meta); +uint32_t KS_GetRemainKeyCount(KS_MEM_Type mem); + +/**@}*/ /* end of group KS_EXPORTED_FUNCTIONS */ + +/**@}*/ /* end of group KS_Driver */ + +/**@}*/ /* end of group Standard_Driver */ + +#ifdef __cplusplus +} +#endif + +#endif /* __NU_KEYSTORE_H__ */ + + diff --git a/Ubiquitous/XiZi/board/nuvoton-m2354/third_party_driver/include/Drivers/nu_lcd.h b/Ubiquitous/XiZi/board/nuvoton-m2354/third_party_driver/include/Drivers/nu_lcd.h new file mode 100644 index 0000000..02613ec --- /dev/null +++ b/Ubiquitous/XiZi/board/nuvoton-m2354/third_party_driver/include/Drivers/nu_lcd.h @@ -0,0 +1,531 @@ +/**************************************************************************//** + * @file nu_lcd.h + * @version V3.00 + * @brief Liquid-Crystal Display(LCD) driver header file + * + * @copyright SPDX-License-Identifier: Apache-2.0 + * @copyright Copyright (C) 2020 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ +#ifndef __NU_LCD_H__ +#define __NU_LCD_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup LCD_Driver LCD Driver + @{ +*/ + +/** @addtogroup LCD_EXPORTED_CONSTANTS LCD Exported Constants + @{ +*/ +/*---------------------------------------------------------------------------------------------------------*/ +/* LCD Bias Voltage Level Selection Constant Definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define LCD_BIAS_LV_1_2 (1ul << LCD_PCTL_BIAS_Pos) /*!< LCD bias voltage level selection - 1/2 Bias \hideinitializer */ +#define LCD_BIAS_LV_1_3 (2ul << LCD_PCTL_BIAS_Pos) /*!< LCD bias voltage level selection - 1/3 Bias \hideinitializer */ +#define LCD_BIAS_LV_1_4 (3ul << LCD_PCTL_BIAS_Pos) /*!< LCD bias voltage level selection - 1/4 Bias \hideinitializer */ + +/*---------------------------------------------------------------------------------------------------------*/ +/* LCD COM Duty Ratio Selection Constant Definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define LCD_COM_DUTY_1_1 (0ul << LCD_PCTL_DUTY_Pos) /*!< LCD com duty ratio selection - 1/1 Duty \hideinitializer */ +#define LCD_COM_DUTY_1_2 (1ul << LCD_PCTL_DUTY_Pos) /*!< LCD com duty ratio selection - 1/2 Duty \hideinitializer */ +#define LCD_COM_DUTY_1_3 (2ul << LCD_PCTL_DUTY_Pos) /*!< LCD com duty ratio selection - 1/3 Duty \hideinitializer */ +#define LCD_COM_DUTY_1_4 (3ul << LCD_PCTL_DUTY_Pos) /*!< LCD com duty ratio selection - 1/4 Duty \hideinitializer */ +#define LCD_COM_DUTY_1_5 (4ul << LCD_PCTL_DUTY_Pos) /*!< LCD com duty ratio selection - 1/5 Duty \hideinitializer */ +#define LCD_COM_DUTY_1_6 (5ul << LCD_PCTL_DUTY_Pos) /*!< LCD com duty ratio selection - 1/6 Duty \hideinitializer */ +#define LCD_COM_DUTY_1_7 (6ul << LCD_PCTL_DUTY_Pos) /*!< LCD com duty ratio selection - 1/7 Duty \hideinitializer */ +#define LCD_COM_DUTY_1_8 (7ul << LCD_PCTL_DUTY_Pos) /*!< LCD com duty ratio selection - 1/8 Duty \hideinitializer */ + +/*---------------------------------------------------------------------------------------------------------*/ +/* LCD Waveform Attribute Selection Constant Definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define LCD_WAVEFORM_TYPE_A_NORMAL (0ul << LCD_PCTL_TYPE_Pos) /*!< LCD waveform Type-A, no inverse \hideinitializer */ +#define LCD_WAVEFORM_TYPE_B_NORMAL (1ul << LCD_PCTL_TYPE_Pos) /*!< LCD waveform Type-B, no inverse \hideinitializer */ +#define LCD_WAVEFORM_TYPE_A_INVERSE (2ul << LCD_PCTL_TYPE_Pos) /*!< LCD waveform Type-A and inverse \hideinitializer */ +#define LCD_WAVEFORM_TYPE_B_INVERSE (3ul << LCD_PCTL_TYPE_Pos) /*!< LCD waveform Type-B and inverse \hideinitializer */ + +/*---------------------------------------------------------------------------------------------------------*/ +/* LCD Charge Pump Voltage Selection Constant Definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define LCD_CP_VOLTAGE_LV_0 (0ul << LCD_PCTL_CPVSEL_Pos) /*!< Select LCD charge pump voltage 2.6 V \hideinitializer */ +#define LCD_CP_VOLTAGE_LV_1 (1ul << LCD_PCTL_CPVSEL_Pos) /*!< Select LCD charge pump voltage 2.8 V \hideinitializer */ +#define LCD_CP_VOLTAGE_LV_2 (2ul << LCD_PCTL_CPVSEL_Pos) /*!< Select LCD charge pump voltage 3.0 V \hideinitializer */ +#define LCD_CP_VOLTAGE_LV_3 (3ul << LCD_PCTL_CPVSEL_Pos) /*!< Select LCD charge pump voltage 3.2 V \hideinitializer */ +#define LCD_CP_VOLTAGE_LV_4 (4ul << LCD_PCTL_CPVSEL_Pos) /*!< Select LCD charge pump voltage 3.4 V \hideinitializer */ +#define LCD_CP_VOLTAGE_LV_5 (5ul << LCD_PCTL_CPVSEL_Pos) /*!< Select LCD charge pump voltage 3.6 V \hideinitializer */ + +/*---------------------------------------------------------------------------------------------------------*/ +/* LCD Interrupt Source Constant Definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define LCD_DISABLE_ALL_INT (0ul << LCD_INTEN_FCEIEN_Pos) /*!< Disable all LCD interrupt sources \hideinitializer */ +#define LCD_FRAME_COUNTING_END_INT (1ul << LCD_INTEN_FCEIEN_Pos) /*!< Indicate frame count end interrupt \hideinitializer */ +#define LCD_FRAME_END_INT (1ul << LCD_INTEN_FEIEN_Pos) /*!< Indicate frame end interrupt \hideinitializer */ +#define LCD_CPTOUT_INT (1ul << LCD_INTEN_CTOIEN_Pos) /*!< Indicate charge pump charging timeout interrupt \hideinitializer */ +#define LCD_ENABLE_ALL_INT (7ul << LCD_INTEN_FCEIEN_Pos) /*!< Enable all LCD interrupt sources \hideinitializer */ + +/*---------------------------------------------------------------------------------------------------------*/ +/* LCD Operation Voltage Source Constant Definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define LCD_VOLTAGE_SOURCE_VLCD (0ul << LCD_DCTL_VSRC_Pos) /*!< LCD voltage source from external VLCD power \hideinitializer */ +#define LCD_VOLTAGE_SOURCE_AVDD (1ul << LCD_DCTL_VSRC_Pos) /*!< LCD voltage source from internal VDD \hideinitializer */ +#define LCD_VOLTAGE_SOURCE_CP (2ul << LCD_DCTL_VSRC_Pos) /*!< LCD voltage source from built-in charge pump \hideinitializer */ + +/*---------------------------------------------------------------------------------------------------------*/ +/* LCD Driving Mode Selection Constant Definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define LCD_LOW_DRIVING_AND_BUF_OFF (0ul << LCD_DCTL_RESMODE_Pos) /*!< LCD operates with low-drive and voltage buffer disabled \hideinitializer */ +#define LCD_HIGH_DRIVING_AND_BUF_OFF (1ul << LCD_DCTL_RESMODE_Pos) /*!< LCD operates with high-drive and voltage buffer disabled \hideinitializer */ +#define LCD_LOW_DRIVING_AND_BUF_ON (2ul << LCD_DCTL_RESMODE_Pos) /*!< LCD operates with low-drive and voltage buffer enabled \hideinitializer */ +#define LCD_HIGH_DRIVING_AND_BUF_OFF_AND_PWR_SAVING (5ul << LCD_DCTL_RESMODE_Pos) /*!< LCD operates with high-drive, voltage buffer disabled and power saving \hideinitializer */ +#define LCD_LOW_DRIVING_AND_BUF_ON_AND_PWR_SAVING (6ul << LCD_DCTL_RESMODE_Pos) /*!< LCD operates with low-drive, voltage buffer enabled and power saving \hideinitializer */ + +/*---------------------------------------------------------------------------------------------------------*/ +/* LCD Power Saving Mode Constant Definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define LCD_PWR_SAVING_NORMAL_MODE (0ul << LCD_DCTL_PSVREV_Pos) /*!< The timing of LCD power saving is normal \hideinitializer */ +#define LCD_PWR_SAVING_REVERSE_MODE (1ul << LCD_DCTL_PSVREV_Pos) /*!< The timing of LCD power saving is reverse \hideinitializer */ + +/**@}*/ /* end of group LCD_EXPORTED_CONSTANTS */ + + +/** @addtogroup LCD_EXPORTED_STRUCTS LCD Exported Structs + @{ +*/ +/** + * @details LCD Configuration Data Struct + */ +typedef struct +{ + uint32_t u32SrcFreq; /*!< LCD clock source frequency */ + uint32_t u32ComDuty; /*!< COM duty */ + uint32_t u32BiasLevel; /*!< Bias level */ + uint32_t u32Framerate; /*!< Operation frame rate */ + uint32_t u32WaveformType; /*!< Waveform type */ + uint32_t u32IntSrc; /*!< Interrupt source */ + uint32_t u32DrivingMode; /*!< Driving mode */ + uint32_t u32VSrc; /*!< Voltage source */ +} S_LCD_CFG_T; + +/**@}*/ /* end of group LCD_EXPORTED_STRUCTS */ + + +/** @addtogroup LCD_EXPORTED_FUNCTIONS LCD Exported Functions + @{ +*/ + +/** + * @brief Enable LCD Display + * + * @param None + * + * @return None + * + * @details This macro is used to enable LCD display. + */ +#define LCD_ENABLE_DISPLAY() do{ LCD->CTL |= LCD_CTL_EN_Msk; while(LCD->CTL & LCD_CTL_SYNC_Msk) {} }while(0) + +/** + * @brief Disable LCD Display + * + * @param None + * + * @return None + * + * @details This macro is used to disable LCD display. + */ +#define LCD_DISABLE_DISPLAY() do{ LCD->CTL &= ~LCD_CTL_EN_Msk; while(LCD->CTL & LCD_CTL_SYNC_Msk) {} }while(0) + +/** + * @brief Set LCD Waveform Type + * + * @param[in] type The LCD waveform type. It could be one of the following type + * - \ref LCD_WAVEFORM_TYPE_A_NORMAL + * - \ref LCD_WAVEFORM_TYPE_B_NORMAL + * - \ref LCD_WAVEFORM_TYPE_A_INVERSE + * - \ref LCD_WAVEFORM_TYPE_B_INVERSE + * + * @return None + * + * @details This macro is used to set the attribute of LCD output waveform. + */ +#define LCD_WAVEFORM_TYPE(type) (LCD->PCTL = (LCD->PCTL & ~LCD_PCTL_TYPE_Msk) | (type)) + +/** + * @brief Set LCD Source Clock Divider + * + * @param[in] div The frequency divider, valid value is between 1 to 1024. + * + * @return None + * + * @details This macro is used to set the LCD operarion frequency is (LCD source frequency / div). + */ +#define LCD_SET_FREQDIV(div) (LCD->PCTL = (LCD->PCTL & ~LCD_PCTL_FREQDIV_Msk) | (((div)-1) << LCD_PCTL_FREQDIV_Pos)) + +/** + * @brief Set Charge Pump Voltage + * + * @param[in] voltage The target charge pump voltage. It could be one of the following voltage level + * - \ref LCD_CP_VOLTAGE_LV_0, 2.6 V + * - \ref LCD_CP_VOLTAGE_LV_1, 2.8 V + * - \ref LCD_CP_VOLTAGE_LV_2, 3.0 V + * - \ref LCD_CP_VOLTAGE_LV_3, 3.2 V + * - \ref LCD_CP_VOLTAGE_LV_4, 3.4 V + * - \ref LCD_CP_VOLTAGE_LV_5, 3.6 V + * + * @return None + * + * @details This macro is used to set charge pump voltage for VLCD. + */ +#define LCD_SET_CP_VOLTAGE(voltage) (LCD->PCTL = (LCD->PCTL & ~LCD_PCTL_CPVSEL_Msk) | (voltage)) + +/** + * @brief Decrease Charge Pump Voltage + * + * @param[in] unit The tuning units, valid value is between 0 to 7. + * One unit of voltage is about 0.03V, and the charge pump voltage is decreased (unit * 0.03)V. + * + * @return None + * + * @details This macro is used to decrease charge pump voltage by specific units. + */ +#define LCD_CP_VOLTAGE_DECREASE(unit) (LCD->PCTL = (LCD->PCTL & ~LCD_PCTL_CPVTUNE_Msk) | ((unit) << LCD_PCTL_CPVTUNE_Pos)) + +/** + * @brief Increase Charge Pump Voltage + * + * @param[in] unit The tuning units, valid value is between 1 to 8. + * One unit of voltage is about 0.03V, and the charge pump voltage is increased (unit * 0.03)V. + * + * @return None + * + * @details This macro is used to increase charge pump voltage by specific units. + */ +#define LCD_CP_VOLTAGE_INCREASE(unit) (LCD->PCTL = (LCD->PCTL & ~LCD_PCTL_CPVTUNE_Msk) | ((16-(unit)) << LCD_PCTL_CPVTUNE_Pos)) + +/** + * @brief Set LCD Blinking ON + * + * @param None + * + * @return None + * + * @details This macro is used to enable LCD blinking. + */ +#define LCD_BLINKING_ON() (LCD->FCTL |= LCD_FCTL_BLINK_Msk) + +/** + * @brief Set LCD Blinking OFF + * + * @param None + * + * @return None + * + * @details This macro is used to disable LCD blinking. + */ +#define LCD_BLINKING_OFF() (LCD->FCTL &= ~LCD_FCTL_BLINK_Msk) + +/** + * @brief Set LCD Frame Counting Value + * + * @param[in] value Frame counting value. Valid value is between 1 to 1024. + * + * @return None + * + * @details This macro is used to set the LCD frame counting value to configure the blink interval. + * @note For type-B waveform, the frame counter increases at the end of odd frames, not even frames. + */ +#define LCD_SET_FRAME_COUNTING_VALUE(value) (LCD->FCTL = (LCD->FCTL & ~LCD_FCTL_FCV_Msk) | (((value)-1) << LCD_FCTL_FCV_Pos)) + +/** + * @brief Set Null Frame Time + * + * @param[in] unit The unit parameter is used to determine the null frame time, valid value is between 0 to 15. + * And one unit time is one LCD operation clock period. + * + * @return None + * + * @details This macro is used to set the one null frame time. + * @note All COM and SEG output voltages will keep at 0V during a null frame. + */ +#define LCD_SET_NULL_FRAME_TIME(unit) (LCD->FCTL = (LCD->FCTL & ~LCD_FCTL_NFTIME_Msk) | ((unit) << LCD_FCTL_NFTIME_Pos)) + +/** + * @brief Set Continuous Frames + * + * @param[in] frame The continuous frames, valid setting is between 1 to 16 frames. + * + * @return None + * + * @details This macro is used to specify the number of continuous frames reached to insert one null frame. + */ +#define LCD_SET_CONTINUOUS_FRAME(frame) (LCD->FCTL = (LCD->FCTL & ~LCD_FCTL_NFNUM_Msk) | (((frame)-1) << LCD_FCTL_NFNUM_Pos)) + +/** + * @brief Select LCD Voltage Source + * + * @param[in] mode The LCD operation voltage source. It could be one of the following source + * - \ref LCD_VOLTAGE_SOURCE_VLCD + * - \ref LCD_VOLTAGE_SOURCE_AVDD + * - \ref LCD_VOLTAGE_SOURCE_CP + * + * @return None + * + * @details This macro is used to select LCD operation voltage source. + */ +#define LCD_VOLTAGE_SOURCE(source) (LCD->DCTL = (LCD->DCTL & ~LCD_DCTL_VSRC_Msk) | (source)) + +/** + * @brief Set LCD Driving Mode + * + * @param[in] mode The LCD operation driving mode. It could be one of the following mode + * - \ref LCD_LOW_DRIVING_AND_BUF_OFF + * - \ref LCD_HIGH_DRIVING_AND_BUF_OFF + * - \ref LCD_LOW_DRIVING_AND_BUF_ON + * - \ref LCD_HIGH_DRIVING_AND_BUF_OFF_AND_PWR_SAVING + * - \ref LCD_LOW_DRIVING_AND_BUF_ON_AND_PWR_SAVING + * + * @return None + * + * @details This macro is used to set LCD operation drivig mode. + */ +#define LCD_DRIVING_MODE(mode) (LCD->DCTL = (LCD->DCTL & ~(LCD_DCTL_RESMODE_Msk | LCD_DCTL_BUFEN_Msk | LCD_DCTL_PSVEN_Msk)) | (mode)) + +/** + * @brief Select Power Saving Mode + * + * @param[in] mode The LCD power saving mode selection. It could be one of the following constant definition + * - \ref LCD_PWR_SAVING_NORMAL_MODE + * - \ref LCD_PWR_SAVING_REVERSE_MODE + * + * @return None + * + * @details This macro is used to set the LCD power saving mode. + * When the timing of power saving mode is reversed, the original power saving period becomes no power saving, + * and the original no power saving period becomes power saving. + */ +#define LCD_PWR_SAVING_MODE(mode) (LCD->DCTL = (LCD->DCTL & ~LCD_DCTL_PSVREV_Msk) | (mode)) + +/** + * @brief Set Power Saving T1 Period + * + * @param[in] t1 The number of t1 to determine T1 period, valid value is between 1 to 16. + * And one unit of t1 period is half of LCD operation clock period. + * + * @return None + * + * @details This macro is used to configure the T1 (Enable Time) period of power saving. + */ +#define LCD_PWR_SAVING_T1_PERIOD(t1) (LCD->DCTL = (LCD->DCTL & ~LCD_DCTL_PSVT1_Msk) | (((t1)-1) << LCD_DCTL_PSVT1_Pos)) + +/** + * @brief Set Power Saving T2 Period + * + * @param[in] t2 The number of t2 to determine T2 period, valid value is between 1 to 16. + * And one unit of t1 period is half of LCD operation clock period. + * + * @return None + * + * @details This macro is used to configure the T2 (On Time) period of power saving. + */ +#define LCD_PWR_SAVING_T2_PERIOD(t2) (LCD->DCTL = (LCD->DCTL & ~LCD_DCTL_PSVT2_Msk) | (((t2)-1) << LCD_DCTL_PSVT2_Pos)) + +/** + * @brief Set Charging Timeout Time + * + * @param[in] value The maximum timeout value, valid value is between 1 to 8192. + * And one unit of timeout value is one LCD operation clock period. + * + * @return None + * + * @details This macro is used to set maximum timeout time of charge pump charging timer. + */ +#define LCD_SET_CHARGE_TIMEOUT_TIME(value) (LCD->DCTL = (LCD->DCTL & ~LCD_DCTL_CTOTIME_Msk) | (((value)-1) << LCD_DCTL_CTOTIME_Pos)) + +/** + * @brief Select Device Package Type + * + * @param[in] pak Select device package type. + * 0 for 128-pin package, and 1 for 64-pin package. + * + * @return None + * + * @details This macro is used to select device output pins for LCD controller with different package type. + */ +#define LCD_SELECT_PACKAGE_TYPE(pkg) (LCD->PKGSEL = (LCD->PKGSEL & ~LCD_PKGSEL_PKG_Msk) | ((pkg) << LCD_PKGSEL_PKG_Pos)) + +/** + * @brief Enable LCD Frame Counting End Interrupt + * + * @param None + * + * @return None + * + * @details This macro is used to enable frame count end interrupt function. + */ +#define LCD_ENABLE_FRAME_COUNTING_END_INT() (LCD->INTEN |= LCD_INTEN_FCEIEN_Msk) + +/** + * @brief Disable LCD Frame Counting End Interrupt + * + * @param None + * + * @return None + * + * @details This macro is used to disable frame count end interrupt function. + */ +#define LCD_DISABLE_FRAME_COUNTING_END_INT() (LCD->INTEN &= ~LCD_INTEN_FCEIEN_Msk) + +/** + * @brief Enable LCD Frame End Interrupt + * + * @param None + * + * @return None + * + * @details This macro is used to enable frame end interrupt function. + */ +#define LCD_ENABLE_FRAME_END_INT() (LCD->INTEN |= LCD_INTEN_FEIEN_Msk) + +/** + * @brief Disable LCD Frame End Interrupt + * + * @param None + * + * @return None + * + * @details This macro is used to disable frame end interrupt function. + */ +#define LCD_DISABLE_FRAME_END_INT() (LCD->INTEN &= ~LCD_INTEN_FEIEN_Msk) + +/** + * @brief Enable Charging Timeout Interrupt + * + * @param None + * + * @return None + * + * @details This macro is used to enable charge pump charging timeout interrupt function. + */ +#define LCD_ENABLE_CHARGE_TIMEOUT_INT() (LCD->INTEN |= LCD_INTEN_CTOIEN_Msk) + +/** + * @brief Disable Charging Timeout Interrupt + * + * @param None + * + * @return None + * + * @details This macro is used to disable charge pump charging timeout interrupt function. + */ +#define LCD_DISABLE_CHARGE_TIMEOUT_INT() (LCD->INTEN &= ~LCD_INTEN_CTOIEN_Msk) + +/** + * @brief Get LCD Frame Counting End Flag + * + * @param None + * + * @retval 0 Frame count end flag did not occur + * @retval 1 Frame count end flag occurred + * + * @details This macro gets frame count end flag. + */ +#define LCD_GET_FRAME_COUNTING_END_FLAG() ((LCD->STS & LCD_STS_FCEF_Msk)? 1UL : 0UL) + +/** + * @brief Clear LCD Frame Counting End Flag + * + * @param None + * + * @return None + * + * @details This macro clears frame count end flag. + */ +#define LCD_CLEAR_FRAME_COUNTING_END_FLAG() (LCD->STS = LCD_STS_FCEF_Msk) + +/** + * @brief Get LCD Frame End Flag + * + * @param None + * + * @retval 0 Frame end flag did not occur + * @retval 1 Frame end flag occurred + * + * @details This macro gets frame end flag. + */ +#define LCD_GET_FRAME_END_FLAG() ((LCD->STS & LCD_STS_FEF_Msk)? 1UL : 0UL) + +/** + * @brief Clear LCD Frame End Flag + * + * @param None + * + * @return None + * + * @details This macro clears frame end flag. + */ +#define LCD_CLEAR_FRAME_END_FLAG() (LCD->STS = LCD_STS_FEF_Msk) + +/** + * @brief Get Charging Timeout Flag + * + * @param None + * + * @retval 0 Charge pump timer timeout flag did not occur + * @retval 1 Charge pump timer timeout flag occurred + * + * @details This macro gets charge pump charging timeout flag. + */ +#define LCD_GET_CHARGE_TIMEOUT_FLAG() ((LCD->STS & LCD_STS_CTOF_Msk)? 1UL : 0UL) + +/** + * @brief Clear Charging Timeout Flag + * + * @param None + * + * @return None + * + * @details This macro clears charge pump charging timeout flag. + */ +#define LCD_CLEAR_CHARGE_TIMEOUT_FLAG() (LCD->STS = LCD_STS_CTOF_Msk) + +/** + * @brief Get Charging Time + * + * @param None + * + * @return Current 13-bit charging timer value + * + * @details This macro gets charging timer value while stops charge pump charging. + */ +#define LCD_GET_CHARGE_TIME() ((LCD->STS & LCD_STS_CTIME_Msk) >> 16) + + +uint32_t LCD_Open(S_LCD_CFG_T *pLCDCfg); +void LCD_Close(void); +void LCD_SetPixel(uint32_t u32Com, uint32_t u32Seg, uint32_t u32OnFlag); +void LCD_SetAllPixels(uint32_t u32OnOff); +uint32_t LCD_EnableBlink(uint32_t u32ms); +void LCD_DisableBlink(void); +void LCD_EnableInt(uint32_t u32IntSrc); +void LCD_DisableInt(uint32_t u32IntSrc); + +/**@}*/ /* end of group LCD_EXPORTED_FUNCTIONS */ + +/**@}*/ /* end of group LCD_Driver */ + +/**@}*/ /* end of group Standard_Driver */ + +#ifdef __cplusplus +} +#endif + +#endif /* __NU_LCD_H__ */ diff --git a/Ubiquitous/XiZi/board/nuvoton-m2354/third_party_driver/include/Drivers/nu_otg.h b/Ubiquitous/XiZi/board/nuvoton-m2354/third_party_driver/include/Drivers/nu_otg.h new file mode 100644 index 0000000..79a9af8 --- /dev/null +++ b/Ubiquitous/XiZi/board/nuvoton-m2354/third_party_driver/include/Drivers/nu_otg.h @@ -0,0 +1,256 @@ +/**************************************************************************//** + * @file nu_otg.h + * @version V3.00 + * @brief M2354 series OTG driver header file + * + * @copyright SPDX-License-Identifier: Apache-2.0 + * @copyright Copyright (C) 2020 Nuvoton Technology Corp. All rights reserved. + ******************************************************************************/ +#ifndef __NU_OTG_H__ +#define __NU_OTG_H__ + +/*---------------------------------------------------------------------------------------------------------*/ +/* Include related headers */ +/*---------------------------------------------------------------------------------------------------------*/ +#include "M2354.h" + +#ifdef __cplusplus +extern "C" +{ +#endif + + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup OTG_Driver OTG Driver + @{ +*/ + + +/** @addtogroup OTG_EXPORTED_CONSTANTS OTG Exported Constants + @{ +*/ + + + +/*---------------------------------------------------------------------------------------------------------*/ +/* OTG constant definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define OTG_VBUS_EN_ACTIVE_HIGH (0UL) /*!< USB VBUS power switch enable signal is active high. */ +#define OTG_VBUS_EN_ACTIVE_LOW (1UL) /*!< USB VBUS power switch enable signal is active low. */ +#define OTG_VBUS_ST_VALID_HIGH (0UL) /*!< USB VBUS power switch valid status is high. */ +#define OTG_VBUS_ST_VALID_LOW (1UL) /*!< USB VBUS power switch valid status is low. */ + + +/**@}*/ /* end of group OTG_EXPORTED_CONSTANTS */ + + +/** @addtogroup OTG_EXPORTED_FUNCTIONS OTG Exported Functions + @{ +*/ + +/*---------------------------------------------------------------------------------------------------------*/ +/* Define Macros and functions */ +/*---------------------------------------------------------------------------------------------------------*/ + + +/** + * @brief This macro is used to enable OTG function + * @param None + * @return None + * @details This macro will set OTGEN bit of OTG_CTL register to enable OTG function. + */ +#define OTG_ENABLE() (((__PC() & NS_OFFSET) == NS_OFFSET)? (OTG_NS->CTL |= OTG_CTL_OTGEN_Msk):(OTG->CTL |= OTG_CTL_OTGEN_Msk)) + +/** + * @brief This macro is used to disable OTG function + * @param None + * @return None + * @details This macro will clear OTGEN bit of OTG_CTL register to disable OTG function. + */ +#define OTG_DISABLE() (((__PC() & NS_OFFSET) == NS_OFFSET)? (OTG_NS->CTL &= ~OTG_CTL_OTGEN_Msk):(OTG->CTL &= ~OTG_CTL_OTGEN_Msk)) + +/** + * @brief This macro is used to enable USB PHY + * @param None + * @return None + * @details When the USB role is selected as OTG device, use this macro to enable USB PHY. + * This macro will set OTGPHYEN bit of OTG_PHYCTL register to enable USB PHY. + */ +#define OTG_ENABLE_PHY() (((__PC() & NS_OFFSET) == NS_OFFSET)? (OTG_NS->PHYCTL |= OTG_PHYCTL_OTGPHYEN_Msk):(OTG->PHYCTL |= OTG_PHYCTL_OTGPHYEN_Msk)) + +/** + * @brief This macro is used to disable USB PHY + * @param None + * @return None + * @details This macro will clear OTGPHYEN bit of OTG_PHYCTL register to disable USB PHY. + */ +#define OTG_DISABLE_PHY() (((__PC() & NS_OFFSET) == NS_OFFSET)? (OTG_NS->PHYCTL &= ~OTG_PHYCTL_OTGPHYEN_Msk):(OTG->PHYCTL &= ~OTG_PHYCTL_OTGPHYEN_Msk)) + +/** + * @brief This macro is used to enable ID detection function + * @param None + * @return None + * @details This macro will set IDDETEN bit of OTG_PHYCTL register to enable ID detection function. + */ +#define OTG_ENABLE_ID_DETECT() (((__PC() & NS_OFFSET) == NS_OFFSET)? (OTG_NS->PHYCTL |= OTG_PHYCTL_IDDETEN_Msk):(OTG->PHYCTL |= OTG_PHYCTL_IDDETEN_Msk)) + +/** + * @brief This macro is used to disable ID detection function + * @param None + * @return None + * @details This macro will clear IDDETEN bit of OTG_PHYCTL register to disable ID detection function. + */ +#define OTG_DISABLE_ID_DETECT() (((__PC() & NS_OFFSET) == NS_OFFSET)? (OTG_NS->PHYCTL &= ~OTG_PHYCTL_IDDETEN_Msk):(OTG->PHYCTL &= ~OTG_PHYCTL_IDDETEN_Msk)) + +/** + * @brief This macro is used to enable OTG wake-up function + * @param None + * @return None + * @details This macro will set WKEN bit of OTG_CTL register to enable OTG wake-up function. + */ +#define OTG_ENABLE_WAKEUP() (((__PC() & NS_OFFSET) == NS_OFFSET)? (OTG_NS->CTL |= OTG_CTL_WKEN_Msk):(OTG->CTL |= OTG_CTL_WKEN_Msk)) + +/** + * @brief This macro is used to disable OTG wake-up function + * @param None + * @return None + * @details This macro will clear WKEN bit of OTG_CTL register to disable OTG wake-up function. + */ +#define OTG_DISABLE_WAKEUP() (((__PC() & NS_OFFSET) == NS_OFFSET)? (OTG_NS->CTL &= ~OTG_CTL_WKEN_Msk):(OTG->CTL &= ~OTG_CTL_WKEN_Msk)) + +/** + * @brief This macro is used to set the polarity of USB_VBUS_EN pin + * @param[in] u32Pol The polarity selection. Valid values are listed below. + * - \ref OTG_VBUS_EN_ACTIVE_HIGH + * - \ref OTG_VBUS_EN_ACTIVE_LOW + * @return None + * @details This macro is used to set the polarity of external USB VBUS power switch enable signal. + */ +#define OTG_SET_VBUS_EN_POL(u32Pol) (((__PC() & NS_OFFSET) == NS_OFFSET)? (OTG_NS->PHYCTL = (OTG_NS->PHYCTL & (~OTG_PHYCTL_VBENPOL_Msk)) | ((u32Pol)<PHYCTL = (OTG->PHYCTL & (~OTG_PHYCTL_VBENPOL_Msk)) | ((u32Pol)<PHYCTL = (OTG_NS->PHYCTL & (~OTG_PHYCTL_VBSTSPOL_Msk)) | ((u32Pol)<PHYCTL = (OTG->PHYCTL & (~OTG_PHYCTL_VBSTSPOL_Msk)) | ((u32Pol)<INTEN |= (u32Mask)):(OTG->INTEN |= (u32Mask))) + +/** + * @brief This macro is used to disable OTG related interrupts + * @param[in] u32Mask The combination of interrupt source. Each bit corresponds to a interrupt source. Valid values are listed below. + * - \ref OTG_INTEN_ROLECHGIEN_Msk + * - \ref OTG_INTEN_VBEIEN_Msk + * - \ref OTG_INTEN_SRPFIEN_Msk + * - \ref OTG_INTEN_HNPFIEN_Msk + * - \ref OTG_INTEN_GOIDLEIEN_Msk + * - \ref OTG_INTEN_IDCHGIEN_Msk + * - \ref OTG_INTEN_PDEVIEN_Msk + * - \ref OTG_INTEN_HOSTIEN_Msk + * - \ref OTG_INTEN_BVLDCHGIEN_Msk + * - \ref OTG_INTEN_AVLDCHGIEN_Msk + * - \ref OTG_INTEN_VBCHGIEN_Msk + * - \ref OTG_INTEN_SECHGIEN_Msk + * - \ref OTG_INTEN_SRPDETIEN_Msk + * @return None + * @details This macro will disable OTG related interrupts specified by u32Mask parameter. + */ +#define OTG_DISABLE_INT(u32Mask) (((__PC() & NS_OFFSET) == NS_OFFSET)? (OTG_NS->INTEN &= ~(u32Mask)):(OTG->INTEN &= ~(u32Mask))) + +/** + * @brief This macro is used to get OTG related interrupt flags + * @param[in] u32Mask The combination of interrupt source. Each bit corresponds to a interrupt source. Valid values are listed below. + * - \ref OTG_INTSTS_ROLECHGIF_Msk + * - \ref OTG_INTSTS_VBEIF_Msk + * - \ref OTG_INTSTS_SRPFIF_Msk + * - \ref OTG_INTSTS_HNPFIF_Msk + * - \ref OTG_INTSTS_GOIDLEIF_Msk + * - \ref OTG_INTSTS_IDCHGIF_Msk + * - \ref OTG_INTSTS_PDEVIF_Msk + * - \ref OTG_INTSTS_HOSTIF_Msk + * - \ref OTG_INTSTS_BVLDCHGIF_Msk + * - \ref OTG_INTSTS_AVLDCHGIF_Msk + * - \ref OTG_INTSTS_VBCHGIF_Msk + * - \ref OTG_INTSTS_SECHGIF_Msk + * - \ref OTG_INTSTS_SRPDETIF_Msk + * @return Interrupt flags of selected sources. + * @details This macro will return OTG related interrupt flags specified by u32Mask parameter. + */ +#define OTG_GET_INT_FLAG(u32Mask) (((__PC() & NS_OFFSET) == NS_OFFSET)? (OTG_NS->INTSTS & (u32Mask)):(OTG->INTSTS & (u32Mask))) + +/** + * @brief This macro is used to clear OTG related interrupt flags + * @param[in] u32Mask The combination of interrupt source. Each bit corresponds to a interrupt source. Valid values are listed below. + * - \ref OTG_INTSTS_ROLECHGIF_Msk + * - \ref OTG_INTSTS_VBEIF_Msk + * - \ref OTG_INTSTS_SRPFIF_Msk + * - \ref OTG_INTSTS_HNPFIF_Msk + * - \ref OTG_INTSTS_GOIDLEIF_Msk + * - \ref OTG_INTSTS_IDCHGIF_Msk + * - \ref OTG_INTSTS_PDEVIF_Msk + * - \ref OTG_INTSTS_HOSTIF_Msk + * - \ref OTG_INTSTS_BVLDCHGIF_Msk + * - \ref OTG_INTSTS_AVLDCHGIF_Msk + * - \ref OTG_INTSTS_VBCHGIF_Msk + * - \ref OTG_INTSTS_SECHGIF_Msk + * - \ref OTG_INTSTS_SRPDETIF_Msk + * @return None + * @details This macro will clear OTG related interrupt flags specified by u32Mask parameter. + */ +#define OTG_CLR_INT_FLAG(u32Mask) (((__PC() & NS_OFFSET) == NS_OFFSET)? (OTG_NS->INTSTS = (u32Mask)):(OTG->INTSTS = (u32Mask))) + +/** + * @brief This macro is used to get OTG related status + * @param[in] u32Mask The combination of user specified source. Valid values are listed below. + * - \ref OTG_STATUS_OVERCUR_Msk + * - \ref OTG_STATUS_IDSTS_Msk + * - \ref OTG_STATUS_SESSEND_Msk + * - \ref OTG_STATUS_BVLD_Msk + * - \ref OTG_STATUS_AVLD_Msk + * - \ref OTG_STATUS_VBUSVLD_Msk + * @return The user specified status. + * @details This macro will return OTG related status specified by u32Mask parameter. + */ +#define OTG_GET_STATUS(u32Mask) (((__PC() & NS_OFFSET) == NS_OFFSET)? (OTG_NS->STATUS & (u32Mask)):(OTG->STATUS & (u32Mask))) + + + +/**@}*/ /* end of group OTG_EXPORTED_FUNCTIONS */ + +/**@}*/ /* end of group OTG_Driver */ + +/**@}*/ /* end of group Standard_Driver */ + +#ifdef __cplusplus +} +#endif + + +#endif /* __NU_OTG_H__ */ + diff --git a/Ubiquitous/XiZi/board/nuvoton-m2354/third_party_driver/include/Drivers/nu_partition_M2354.h b/Ubiquitous/XiZi/board/nuvoton-m2354/third_party_driver/include/Drivers/nu_partition_M2354.h new file mode 100644 index 0000000..4de1664 --- /dev/null +++ b/Ubiquitous/XiZi/board/nuvoton-m2354/third_party_driver/include/Drivers/nu_partition_M2354.h @@ -0,0 +1,697 @@ +/**************************************************************************//** + * @file nu_partition_M2354.h + * @version V3.00 + * @brief TrustZone partition file + * + * @copyright SPDX-License-Identifier: Apache-2.0 + * @copyright Copyright (C) 2020 Nuvoton Technology Corp. All rights reserved. + ******************************************************************************/ + +#ifndef PARTITION_M2354 +#define PARTITION_M2354 + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + +/* + Default M2354 pritition configuration file is for non-TrustZone sample code only. + If user wants to use TrurstZone, they should have their partition_m2354.h. + For TrustZone projects, path of local partition_m2354.h should be in the + front of the include path list to make sure local partition_m2354.h is used. + + It also apply to non-secure project of the TrustZone projects. + +*/ +# error "Link to default nu_partition_M2354.h in secure mode. Please check your include path." + +#endif + +/* +//-------- <<< Use Configuration Wizard in Context Menu >>> ----------------- +*/ + + +/* + SRAMNSSET +*/ +/* +// Bit 0..18 +// Secure SRAM Size <0=> 0 KB +// <0x4000=> 16KB +// <0x8000=> 32KB +// <0xc000=> 48KB +// <0x10000=> 64KB +// <0x14000=> 80KB +// <0x18000=> 96KB +// <0x1C000=> 112KB +// <0x20000=> 128KB +// <0x24000=> 144KB +// <0x28000=> 160KB +// <0x2C000=> 176KB +// <0x30000=> 192KB +// <0x34000=> 208KB +// <0x38000=> 224KB +// <0x3C000=> 240KB +// <0x40000=> 256KB +*/ +#define SCU_SECURE_SRAM_SIZE 0x18000 +#define NON_SECURE_SRAM_BASE (0x30000000 + SCU_SECURE_SRAM_SIZE) + + + +/*--------------------------------------------------------------------------------------------------------*/ + +/* + NSBA +*/ +#define FMC_INIT_NSBA 1 +/* +// Secure Flash ROM Size <0x800-0x80000:0x800> +*/ + +#define FMC_SECURE_ROM_SIZE 0x80000 + +#define FMC_NON_SECURE_BASE (0x10000000 + FMC_SECURE_ROM_SIZE) + +/*--------------------------------------------------------------------------------------------------------*/ + + +/* +// Peripheral Secure Attribution Configuration +*/ + +/* + PNSSET0 +*/ +/* +// Module 0..31 +// USBH <0=> Secure <1=> Non-Secure +// SD0 <0=> Secure <1=> Non-Secure +// EBI <0=> Secure <1=> Non-Secure +// PDMA1 <0=> Secure <1=> Non-Secure +*/ +#define SCU_INIT_PNSSET0_VAL 0x0 +/* + PNSSET1 +*/ +/* +// Module 0..31 +// CRC <0=> Secure <1=> Non-Secure +// CRPT <0=> Secure <1=> Non-Secure +*/ +#define SCU_INIT_PNSSET1_VAL 0x00000 +/* + PNSSET2 +*/ +/* +// Module 0..31 +// EWDT <0=> Secure <1=> Non-Secure +// EADC <0=> Secure <1=> Non-Secure +// ACMP01 <0=> Secure <1=> Non-Secure +// +// DAC <0=> Secure <1=> Non-Secure +// I2S0 <0=> Secure <1=> Non-Secure +// OTG <0=> Secure <1=> Non-Secure +// TIMER +// TMR23 <0=> Secure <1=> Non-Secure +// TMR45 <0=> Secure <1=> Non-Secure +// EPWM +// EPWM0 <0=> Secure <1=> Non-Secure +// EPWM1 <0=> Secure <1=> Non-Secure +// +// BPWM +// BPWM0 <0=> Secure <1=> Non-Secure +// BPWM1 <0=> Secure <1=> Non-Secure +// +*/ +#define SCU_INIT_PNSSET2_VAL 0x0 +/* + PNSSET3 +*/ +/* +// Module 0..31 +// SPI +// QSPI0 <0=> Secure <1=> Non-Secure +// SPI0 <0=> Secure <1=> Non-Secure +// SPI1 <0=> Secure <1=> Non-Secure +// SPI2 <0=> Secure <1=> Non-Secure +// SPI3 <0=> Secure <1=> Non-Secure +// +// UART +// UART0 <0=> Secure <1=> Non-Secure +// UART1 <0=> Secure <1=> Non-Secure +// UART2 <0=> Secure <1=> Non-Secure +// UART3 <0=> Secure <1=> Non-Secure +// UART4 <0=> Secure <1=> Non-Secure +// UART5 <0=> Secure <1=> Non-Secure +// +*/ +#define SCU_INIT_PNSSET3_VAL 0x00000 +/* + PNSSET4 +*/ +/* +// Module 0..31 +// I2C +// I2C0 <0=> Secure <1=> Non-Secure +// I2C1 <0=> Secure <1=> Non-Secure +// I2C2 <0=> Secure <1=> Non-Secure +// +// Smart Card +// SC0 <0=> Secure <1=> Non-Secure +// SC1 <0=> Secure <1=> Non-Secure +// SC2 <0=> Secure <1=> Non-Secure +// +*/ +#define SCU_INIT_PNSSET4_VAL 0x0 +/* + PNSSET5 +*/ +/* +// Module 0..31 +// CAN0 <0=> Secure <1=> Non-Secure +// QEI +// QEI0 <0=> Secure <1=> Non-Secure +// QEI1 <0=> Secure <1=> Non-Secure +// +// ECAP +// ECAP0 <0=> Secure <1=> Non-Secure +// ECAP1 <0=> Secure <1=> Non-Secure +// +// TRNG <0=> Secure <1=> Non-Secure +// LCD <0=> Secure <1=> Non-Secure +*/ +#define SCU_INIT_PNSSET5_VAL 0x0 +/* + PNSSET6 +*/ +/* +// Module 0..31 +// USBD <0=> Secure <1=> Non-Secure +// USCI +// USCI0 <0=> Secure <1=> Non-Secure +// USCI1 <0=> Secure <1=> Non-Secure +// +*/ +#define SCU_INIT_PNSSET6_VAL 0x0 +/* +// +*/ + + +/* +// GPIO Secure Attribution Configuration +*/ + +/* + IONSSET +*/ + +/* +// Bit 0..31 +// PA +// PA0 <0=> Secure <1=> Non-Secure +// PA1 <0=> Secure <1=> Non-Secure +// PA2 <0=> Secure <1=> Non-Secure +// PA3 <0=> Secure <1=> Non-Secure +// PA4 <0=> Secure <1=> Non-Secure +// PA5 <0=> Secure <1=> Non-Secure +// PA6 <0=> Secure <1=> Non-Secure +// PA7 <0=> Secure <1=> Non-Secure +// PA8 <0=> Secure <1=> Non-Secure +// PA9 <0=> Secure <1=> Non-Secure +// PA10 <0=> Secure <1=> Non-Secure +// PA11 <0=> Secure <1=> Non-Secure +// PA12 <0=> Secure <1=> Non-Secure +// PA13 <0=> Secure <1=> Non-Secure +// PA14 <0=> Secure <1=> Non-Secure +// PA15 <0=> Secure <1=> Non-Secure +// + +*/ +#define SCU_INIT_IONSSET0_VAL 0x00000000 + +/* +// Bit 0..31 +// PB +// PB0 <0=> Secure <1=> Non-Secure +// PB1 <0=> Secure <1=> Non-Secure +// PB2 <0=> Secure <1=> Non-Secure +// PB3 <0=> Secure <1=> Non-Secure +// PB4 <0=> Secure <1=> Non-Secure +// PB5 <0=> Secure <1=> Non-Secure +// PB6 <0=> Secure <1=> Non-Secure +// PB7 <0=> Secure <1=> Non-Secure +// PB8 <0=> Secure <1=> Non-Secure +// PB9 <0=> Secure <1=> Non-Secure +// PB10 <0=> Secure <1=> Non-Secure +// PB11 <0=> Secure <1=> Non-Secure +// PB12 <0=> Secure <1=> Non-Secure +// PB13 <0=> Secure <1=> Non-Secure +// PB14 <0=> Secure <1=> Non-Secure +// PB15 <0=> Secure <1=> Non-Secure +// +*/ +#define SCU_INIT_IONSSET1_VAL 0x00000000 + + +/* +// Bit 0..31 +// PC +// PC0 <0=> Secure <1=> Non-Secure +// PC1 <0=> Secure <1=> Non-Secure +// PC2 <0=> Secure <1=> Non-Secure +// PC3 <0=> Secure <1=> Non-Secure +// PC4 <0=> Secure <1=> Non-Secure +// PC5 <0=> Secure <1=> Non-Secure +// PC6 <0=> Secure <1=> Non-Secure +// PC7 <0=> Secure <1=> Non-Secure +// PC8 <0=> Secure <1=> Non-Secure +// PC9 <0=> Secure <1=> Non-Secure +// PC10 <0=> Secure <1=> Non-Secure +// PC11 <0=> Secure <1=> Non-Secure +// PC12 <0=> Secure <1=> Non-Secure +// PC13 <0=> Secure <1=> Non-Secure +// +*/ +#define SCU_INIT_IONSSET2_VAL 0x00000000 + +/* +// Bit 0..31 +// PD +// PD0 <0=> Secure <1=> Non-Secure +// PD1 <0=> Secure <1=> Non-Secure +// PD2 <0=> Secure <1=> Non-Secure +// PD3 <0=> Secure <1=> Non-Secure +// PD4 <0=> Secure <1=> Non-Secure +// PD5 <0=> Secure <1=> Non-Secure +// PD6 <0=> Secure <1=> Non-Secure +// PD7 <0=> Secure <1=> Non-Secure +// PD8 <0=> Secure <1=> Non-Secure +// PD9 <0=> Secure <1=> Non-Secure +// PD10 <0=> Secure <1=> Non-Secure +// PD11 <0=> Secure <1=> Non-Secure +// PD12 <0=> Secure <1=> Non-Secure +// PD14 <0=> Secure <1=> Non-Secure +// +*/ +#define SCU_INIT_IONSSET3_VAL 0x00000000 + + +/* +// Bit 0..31 +// PE +// PE0 <0=> Secure <1=> Non-Secure +// PE1 <0=> Secure <1=> Non-Secure +// PE2 <0=> Secure <1=> Non-Secure +// PE3 <0=> Secure <1=> Non-Secure +// PE4 <0=> Secure <1=> Non-Secure +// PE5 <0=> Secure <1=> Non-Secure +// PE6 <0=> Secure <1=> Non-Secure +// PE7 <0=> Secure <1=> Non-Secure +// PE8 <0=> Secure <1=> Non-Secure +// PE9 <0=> Secure <1=> Non-Secure +// PE10 <0=> Secure <1=> Non-Secure +// PE11 <0=> Secure <1=> Non-Secure +// PE12 <0=> Secure <1=> Non-Secure +// PE13 <0=> Secure <1=> Non-Secure +// PE14 <0=> Secure <1=> Non-Secure +// PE15 <0=> Secure <1=> Non-Secure +// +*/ +#define SCU_INIT_IONSSET4_VAL 0x00000000 + + +/* +// Bit 0..31 +// PF +// PF0 <0=> Secure <1=> Non-Secure +// PF1 <0=> Secure <1=> Non-Secure +// PF2 <0=> Secure <1=> Non-Secure +// PF3 <0=> Secure <1=> Non-Secure +// PF4 <0=> Secure <1=> Non-Secure +// PF5 <0=> Secure <1=> Non-Secure +// PF6 <0=> Secure <1=> Non-Secure +// PF7 <0=> Secure <1=> Non-Secure +// PF8 <0=> Secure <1=> Non-Secure +// PF9 <0=> Secure <1=> Non-Secure +// PF10 <0=> Secure <1=> Non-Secure +// PF11 <0=> Secure <1=> Non-Secure +// +*/ +#define SCU_INIT_IONSSET5_VAL 0x00000000 + + +/* +// Bit 0..31 +// PG +// PG2 <0=> Secure <1=> Non-Secure +// PG3 <0=> Secure <1=> Non-Secure +// PG4 <0=> Secure <1=> Non-Secure +// PG9 <0=> Secure <1=> Non-Secure +// PG10 <0=> Secure <1=> Non-Secure +// PG11 <0=> Secure <1=> Non-Secure +// PG12 <0=> Secure <1=> Non-Secure +// PG13 <0=> Secure <1=> Non-Secure +// PG14 <0=> Secure <1=> Non-Secure +// PG15 <0=> Secure <1=> Non-Secure +// +*/ +#define SCU_INIT_IONSSET6_VAL 0x00000000 + +/* +// Bit 0..31 +// PH +// PH4 <0=> Secure <1=> Non-Secure +// PH5 <0=> Secure <1=> Non-Secure +// PH6 <0=> Secure <1=> Non-Secure +// PH7 <0=> Secure <1=> Non-Secure +// PH8 <0=> Secure <1=> Non-Secure +// PH9 <0=> Secure <1=> Non-Secure +// PH10 <0=> Secure <1=> Non-Secure +// PH11 <0=> Secure <1=> Non-Secure +// +*/ +#define SCU_INIT_IONSSET7_VAL 0x00000000 + +/* +// +*/ + + + +/* +// Assign GPIO Interrupt to Secure or Non-secure Vector +*/ + + +/* + Initialize GPIO ITNS (Interrupts 0..31) +*/ + +/* +// Bit 0..31 +// GPA <0=> Secure <1=> Non-Secure +// GPB <0=> Secure <1=> Non-Secure +// GPC <0=> Secure <1=> Non-Secure +// GPD <0=> Secure <1=> Non-Secure +// GPE <0=> Secure <1=> Non-Secure +// GPF <0=> Secure <1=> Non-Secure +// GPG <0=> Secure <1=> Non-Secure +// GPH <0=> Secure <1=> Non-Secure +// EINT0 <0=> Secure <1=> Non-Secure +// EINT1 <0=> Secure <1=> Non-Secure +// EINT2 <0=> Secure <1=> Non-Secure +// EINT3 <0=> Secure <1=> Non-Secure +// EINT4 <0=> Secure <1=> Non-Secure +// EINT5 <0=> Secure <1=> Non-Secure +// EINT6 <0=> Secure <1=> Non-Secure +// EINT7 <0=> Secure <1=> Non-Secure +*/ +#define SCU_INIT_IONSSET_VAL 0x0000 +/* +// +*/ + + + +/* ---------------------------------------------------------------------------------------------------- */ + +/* +// Secure Attribute Unit (SAU) Control +*/ +#define SAU_INIT_CTRL 0 + +/* +// Enable SAU +// To enable Secure Attribute Unit (SAU). +*/ +#define SAU_INIT_CTRL_ENABLE 1 + +/* +// All Memory Attribute When SAU is disabled +// <0=> All Memory is Secure +// <1=> All Memory is Non-Secure +// To set the ALLNS bit in SAU CTRL. +// When all Memory is Non-Secure (ALLNS is 1), IDAU can override memory map configuration. +*/ +#define SAU_INIT_CTRL_ALLNS 0 + +/* +// +*/ + + +/* +// Enable and Set Secure/Non-Secure region +*/ +#define SAU_REGIONS_MAX 8 /* Max. number of SAU regions */ + +/* +// SAU Region 0 +// Setup SAU Region 0 +*/ +#define SAU_INIT_REGION0 0 +/* +// Start Address <0-0xFFFFFFE0> +*/ +#define SAU_INIT_START0 0x0003F000 /* start address of SAU region 0 */ +/* +// End Address <0x1F-0xFFFFFFFF> +*/ +#define SAU_INIT_END0 0x0003FFFF /* end address of SAU region 0 */ +/* +// Region is +// <0=>Non-Secure +// <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC0 1 +/* +// +*/ + +/* +// SAU Region 1 +// Setup SAU Region 1 +*/ +#define SAU_INIT_REGION1 0 +/* +// Start Address <0-0xFFFFFFE0> +*/ +#define SAU_INIT_START1 0x10040000 +/* +// End Address <0x1F-0xFFFFFFFF> +*/ +#define SAU_INIT_END1 0x1007FFFF +/* +// Region is +// <0=>Non-Secure +// <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC1 0 +/* +// +*/ + +/* +// SAU Region 2 +// Setup SAU Region 2 +*/ +#define SAU_INIT_REGION2 0 +/* +// Start Address <0-0xFFFFFFE0> +*/ +#define SAU_INIT_START2 0x2000F000 +/* +// End Address <0x1F-0xFFFFFFFF> +*/ +#define SAU_INIT_END2 0x2000FFFF +/* +// Region is +// <0=>Non-Secure +// <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC2 1 +/* +// +*/ + +/* +// SAU Region 3 +// Setup SAU Region 3 +*/ +#define SAU_INIT_REGION3 0 +/* +// Start Address <0-0xFFFFFFE0> +*/ +#define SAU_INIT_START3 0x3f000 +/* +// End Address <0x1F-0xFFFFFFFF> +*/ +#define SAU_INIT_END3 0x3f7ff +/* +// Region is +// <0=>Non-Secure +// <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC3 1 +/* +// +*/ + +/* + SAU Region 4 + Setup SAU Region 4 +*/ +#define SAU_INIT_REGION4 1 +/* + Start Address <0-0xFFFFFFE0> +*/ +#define SAU_INIT_START4 FMC_NON_SECURE_BASE /* start address of SAU region 4 */ + +/* + End Address <0x1F-0xFFFFFFFF> +*/ +#define SAU_INIT_END4 0x1007FFFF /* end address of SAU region 4 */ + +/* + Region is + <0=>Non-Secure + <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC4 0 +/* + +*/ + +/* + SAU Region 5 + Setup SAU Region 5 +*/ +#define SAU_INIT_REGION5 1 + +/* + Start Address <0-0xFFFFFFE0> +*/ +#define SAU_INIT_START5 0x00807E00 + +/* + End Address <0x1F-0xFFFFFFFF> +*/ +#define SAU_INIT_END5 0x00807FFF + +/* + Region is + <0=>Non-Secure + <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC5 1 +/* + +*/ + +/* + SAU Region 6 + Setup SAU Region 6 +*/ +#define SAU_INIT_REGION6 1 + +/* + Start Address <0-0xFFFFFFE0> +*/ +#define SAU_INIT_START6 NON_SECURE_SRAM_BASE + +/* + End Address <0x1F-0xFFFFFFFF> +*/ +#define SAU_INIT_END6 0x30017FFF + +/* + Region is + <0=>Non-Secure + <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC6 0 +/* + +*/ + +/* + SAU Region 7 + Setup SAU Region 7 +*/ +#define SAU_INIT_REGION7 1 + +/* + Start Address <0-0xFFFFFFE0> +*/ +#define SAU_INIT_START7 0x50000000 + +/* + End Address <0x1F-0xFFFFFFFF> +*/ +#define SAU_INIT_END7 0x5FFFFFFF + +/* + Region is + <0=>Non-Secure + <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC7 0 +/* + +*/ + +/* +// +*/ + +/* +// Setup behavior of Sleep and Exception Handling +*/ +#define SCB_CSR_AIRCR_INIT 1 + +/* +// Deep Sleep can be enabled by +// <0=>Secure and Non-Secure state +// <1=>Secure state only +// Value for SCB->CSR register bit DEEPSLEEPS +*/ +#define SCB_CSR_DEEPSLEEPS_VAL 0 + +/* +// System reset request accessible from +// <0=> Secure and Non-Secure state +// <1=> Secure state only +// Value for SCB->AIRCR register bit SYSRESETREQS +*/ +#define SCB_AIRCR_SYSRESETREQS_VAL 0 + +/* +// Priority of Non-Secure exceptions is +// <0=> Not altered +// <1=> Lowered to 0x80-0xFF +// Value for SCB->AIRCR register bit PRIS +*/ +#define SCB_AIRCR_PRIS_VAL 0 + +/* Assign HardFault to be always secure for safe */ +#define SCB_AIRCR_BFHFNMINS_VAL 0 + +/* +// +*/ + +/* + max 128 SAU regions. + SAU regions are defined in partition.h + */ + +#define SAU_INIT_REGION(n) \ + SAU->RNR = (n & SAU_RNR_REGION_Msk); \ + SAU->RBAR = (SAU_INIT_START##n & SAU_RBAR_BADDR_Msk); \ + SAU->RLAR = (SAU_INIT_END##n & SAU_RLAR_LADDR_Msk) | \ + ((SAU_INIT_NSC##n << SAU_RLAR_NSC_Pos) & SAU_RLAR_NSC_Msk) | 1U + + +#endif /* PARTITION_M2354 */ + diff --git a/Ubiquitous/XiZi/board/nuvoton-m2354/third_party_driver/include/Drivers/nu_pdma.h b/Ubiquitous/XiZi/board/nuvoton-m2354/third_party_driver/include/Drivers/nu_pdma.h new file mode 100644 index 0000000..0d4947e --- /dev/null +++ b/Ubiquitous/XiZi/board/nuvoton-m2354/third_party_driver/include/Drivers/nu_pdma.h @@ -0,0 +1,380 @@ +/**************************************************************************//** + * @file nu_pdma.h + * @version V3.00 + * @brief M2354 series PDMA driver header file + * + * @copyright SPDX-License-Identifier: Apache-2.0 + * @copyright Copyright (C) 2020 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ +#ifndef __NU_PDMA_H__ +#define __NU_PDMA_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup PDMA_Driver PDMA Driver + @{ +*/ + +/** @addtogroup PDMA_EXPORTED_CONSTANTS PDMA Exported Constants + @{ +*/ +#define PDMA_CH_MAX 8UL /*!< Specify Maximum Channels of PDMA \hideinitializer */ + +/*---------------------------------------------------------------------------------------------------------*/ +/* Operation Mode Constant Definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define PDMA_OP_STOP 0x00000000UL /*!INTSTS)) + +/** + * @brief Get Transfer Done Interrupt Status + * + * @param[in] pdma The pointer of the specified PDMA module + * + * @return None + * + * @details Get the transfer done Interrupt status. + */ +#define PDMA_GET_TD_STS(pdma) ((uint32_t)((pdma)->TDSTS)) + +/** + * @brief Clear Transfer Done Interrupt Status + * + * @param[in] pdma The pointer of the specified PDMA module + * @param[in] u32Mask The channel mask + * + * @return None + * + * @details Clear the transfer done Interrupt status. + */ +#define PDMA_CLR_TD_FLAG(pdma, u32Mask) ((uint32_t)((pdma)->TDSTS = (u32Mask))) + +/** + * @brief Get Target Abort Interrupt Status + * + * @param[in] pdma The pointer of the specified PDMA module + * + * @return None + * + * @details Get the target abort Interrupt status. + */ +#define PDMA_GET_ABORT_STS(pdma) ((uint32_t)((pdma)->ABTSTS)) + +/** + * @brief Clear Target Abort Interrupt Status + * + * @param[in] pdma The pointer of the specified PDMA module + * @param[in] u32Mask The channel mask + * + * @return None + * + * @details Clear the target abort Interrupt status. + */ +#define PDMA_CLR_ABORT_FLAG(pdma, u32Mask) ((uint32_t)((pdma)->ABTSTS = (u32Mask))) + +/** + * @brief Get PDMA Transfer Alignment Status + * + * @param[in] pdma The pointer of the specified PDMA module + * + * @return None + * + * @details Get the PDMA transfer alignment status. + */ +#define PDMA_GET_ALIGN_STS(pdma) ((uint32_t)((pdma)->ALIGN)) + +/** + * @brief Clear PDMA Transfer Alignment Interrupt Status + * + * @param[in] pdma The pointer of the specified PDMA module + * @param[in] u32Mask The channel mask + * + * @return None + * + * @details Clear the PDMA transfer alignment Interrupt status. + */ +#define PDMA_CLR_ALIGN_FLAG(pdma, u32Mask) ((uint32_t)((pdma)->ALIGN = (u32Mask))) + +/** + * @brief Clear Timeout Interrupt Status + * + * @param[in] pdma The pointer of the specified PDMA module + * @param[in] u32Ch The selected channel + * + * @return None + * + * @details Clear the selected channel timeout interrupt status. + * @note This function is only supported in channel 0 and channel 1. + */ +#define PDMA_CLR_TMOUT_FLAG(pdma, u32Ch) ((uint32_t)((pdma)->INTSTS = (1UL << ((u32Ch) + 8UL)))) + +/** + * @brief Check Channel Status + * + * @param[in] pdma The pointer of the specified PDMA module + * @param[in] u32Ch The selected channel + * + * @retval 0 Idle state + * @retval 1 Busy state + * + * @details Check the selected channel is busy or not. + */ +#define PDMA_IS_CH_BUSY(pdma, u32Ch) ((uint32_t)((pdma)->TRGSTS & (1UL << (u32Ch)))? 1 : 0) + +/** + * @brief Set Source Address + * + * @param[in] pdma The pointer of the specified PDMA module + * @param[in] u32Ch The selected channel + * @param[in] u32Addr The selected address + * + * @return None + * + * @details This macro set the selected channel source address. + */ +#define PDMA_SET_SRC_ADDR(pdma, u32Ch, u32Addr) ((uint32_t)((pdma)->DSCT[(u32Ch)].SA = (u32Addr))) + +/** + * @brief Set Destination Address + * + * @param[in] pdma The pointer of the specified PDMA module + * @param[in] u32Ch The selected channel + * @param[in] u32Addr The selected address + * + * @return None + * + * @details This macro set the selected channel destination address. + */ +#define PDMA_SET_DST_ADDR(pdma, u32Ch, u32Addr) ((uint32_t)((pdma)->DSCT[(u32Ch)].DA = (u32Addr))) + +/** + * @brief Set Transfer Count + * + * @param[in] pdma The pointer of the specified PDMA module + * @param[in] u32Ch The selected channel + * @param[in] u32TransCount Transfer Count + * + * @return None + * + * @details This macro set the selected channel transfer count. + */ +#define PDMA_SET_TRANS_CNT(pdma, u32Ch, u32TransCount) ((uint32_t)((pdma)->DSCT[(u32Ch)].CTL=((pdma)->DSCT[(u32Ch)].CTL&~PDMA_DSCT_CTL_TXCNT_Msk)|(((u32TransCount)-1UL) << PDMA_DSCT_CTL_TXCNT_Pos))) + +/** + * @brief Set Scatter-gather descriptor Address + * + * @param[in] pdma The pointer of the specified PDMA module + * @param[in] u32Ch The selected channel + * @param[in] u32Addr The descriptor address + * + * @return None + * + * @details This macro set the selected channel scatter-gather descriptor address. + */ +#define PDMA_SET_SCATTER_DESC(pdma, u32Ch, u32Addr) ((uint32_t)((pdma)->DSCT[(u32Ch)].NEXT = (u32Addr) - ((pdma)->SCATBA))) + +/** + * @brief Stop the channel + * + * @param[in] pdma The pointer of the specified PDMA module + * @param[in] u32Ch The selected channel + * + * @return None + * + * @details This macro stop the selected channel. + */ +#define PDMA_STOP(pdma, u32Ch) ((uint32_t)((pdma)->PAUSE = (1UL << (u32Ch)))) + +/** + * @brief Pause the channel + * + * @param[in] pdma The pointer of the specified PDMA module + * @param[in] u32Ch The selected channel + * + * @return None + * + * @details This macro pause the selected channel. + */ +#define PDMA_PAUSE(pdma, u32Ch) ((uint32_t)((pdma)->PAUSE = (1UL << (u32Ch)))) + +/** + * @brief Reset the channel + * + * @param[in] pdma The pointer of the specified PDMA module + * @param[in] u32Ch The selected channel + * + * @return None + * + * @details This macro reset the selected channel. + */ +#define PDMA_RESET(pdma, u32Ch) ((uint32_t)((pdma)->CHRST = (1UL << (u32Ch)))) + +/*---------------------------------------------------------------------------------------------------------*/ +/* Define PWM functions prototype */ +/*---------------------------------------------------------------------------------------------------------*/ +void PDMA_Open(PDMA_T *pdma, uint32_t u32Mask); +void PDMA_Close(PDMA_T *pdma); +void PDMA_SetTransferCnt(PDMA_T *pdma, uint32_t u32Ch, uint32_t u32Width, uint32_t u32TransCount); +void PDMA_SetStride(PDMA_T *pdma, uint32_t u32Ch, uint32_t u32DestLen, uint32_t u32SrcLen, uint32_t u32TransCount); +void PDMA_SetRepeat(PDMA_T * pdma, uint32_t u32Ch, uint32_t u32DestInterval, uint32_t u32SrcInterval, uint32_t u32RepeatCount); +void PDMA_SetTransferAddr(PDMA_T *pdma, uint32_t u32Ch, uint32_t u32SrcAddr, uint32_t u32SrcCtrl, uint32_t u32DstAddr, uint32_t u32DstCtrl); +void PDMA_SetTransferMode(PDMA_T *pdma, uint32_t u32Ch, uint32_t u32Peripheral, uint32_t u32ScatterEn, uint32_t u32DescAddr); +void PDMA_SetBurstType(PDMA_T *pdma, uint32_t u32Ch, uint32_t u32BurstType, uint32_t u32BurstSize); +void PDMA_EnableTimeout(PDMA_T *pdma, uint32_t u32Mask); +void PDMA_DisableTimeout(PDMA_T *pdma, uint32_t u32Mask); +void PDMA_SetTimeOut(PDMA_T *pdma, uint32_t u32Ch, uint32_t u32OnOff, uint32_t u32TimeOutCnt); +void PDMA_Trigger(PDMA_T *pdma, uint32_t u32Ch); +void PDMA_EnableInt(PDMA_T *pdma, uint32_t u32Ch, uint32_t u32Mask); +void PDMA_DisableInt(PDMA_T *pdma, uint32_t u32Ch, uint32_t u32Mask); + + +/**@}*/ /* end of group PDMA_EXPORTED_FUNCTIONS */ + +/**@}*/ /* end of group PDMA_Driver */ + +/**@}*/ /* end of group Standard_Driver */ + +#ifdef __cplusplus +} +#endif + +#endif /* __NU_PDMA_H__ */ diff --git a/Ubiquitous/XiZi/board/nuvoton-m2354/third_party_driver/include/Drivers/nu_plm.h b/Ubiquitous/XiZi/board/nuvoton-m2354/third_party_driver/include/Drivers/nu_plm.h new file mode 100644 index 0000000..e1320d3 --- /dev/null +++ b/Ubiquitous/XiZi/board/nuvoton-m2354/third_party_driver/include/Drivers/nu_plm.h @@ -0,0 +1,95 @@ +/**************************************************************************//** + * @file nu_plm.h + * @version V3.00 + * @brief Product life cycle management + * + * @copyright SPDX-License-Identifier: Apache-2.0 + * @copyright Copyright (C) 2020 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ +#ifndef __NU_PLM_H__ +#define __NU_PLM_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup PLM_Driver PLM Driver + @{ +*/ + +/** @addtogroup PLM_EXPORTED_CONSTANTS PLM Exported Constants + @{ +*/ + +typedef enum +{ + PLM_VENDOR = 0, + PLM_OEM = 1, + PLM_DEPLOYED = 3, + PLM_RMA = 7 +} PLM_STAGE_T; + +#define PLM_VCODE (0x475A0000ul) /*!< The key code for PLM_CTL write. */ + +/**@}*/ /* end of group FVC_EXPORTED_CONSTANTS */ + + +/** @addtogroup FVC_EXPORTED_FUNCTIONS FVC Exported Functions + @{ +*/ + + +/** + * @brief Get product life-cycle stage + * @return Current stage of PLM + * @details This function is used to Get PLM stage. + */ +#define PLM_GetStage() (PLM->STS & PLM_STS_STAGE_Msk) + + +/** + * @brief Set product life-cycle stage + * @param[in] stage Product life-cycle stage. It could be: + * \ref PLM_VENDOR + * \ref PLM_OEM + * \ref PLM_DEPLOYED + * \ref PLM_RMA + * @retval 0 Successful + * @retval -1 Failed + * @details This function is used to set PLM stage. It could be only be VENDOR, OEM, DEPLOYED and RMA. + * The setting of PLM cannot be rollback. + */ +__STATIC_INLINE int32_t PLM_SetStage(PLM_STAGE_T stage) +{ + + /* Do nothing when stage is not changed */ + if(PLM_GetStage() == stage) + return 0; + + PLM->CTL = PLM_VCODE | (stage); + + /* The dirty flag should be set when PLM stage set successfully. */ + if(PLM->STS & PLM_STS_DIRTY_Msk) + return -1; + + return 0; +} + +/**@}*/ /* end of group PLM_EXPORTED_FUNCTIONS */ + +/**@}*/ /* end of group PLM_Driver */ + +/**@}*/ /* end of group Standard_Driver */ + +#ifdef __cplusplus +} +#endif + +#endif /* __NU_PLM_H__ */ + diff --git a/Ubiquitous/XiZi/board/nuvoton-m2354/third_party_driver/include/Drivers/nu_qei.h b/Ubiquitous/XiZi/board/nuvoton-m2354/third_party_driver/include/Drivers/nu_qei.h new file mode 100644 index 0000000..c8a16d3 --- /dev/null +++ b/Ubiquitous/XiZi/board/nuvoton-m2354/third_party_driver/include/Drivers/nu_qei.h @@ -0,0 +1,388 @@ +/**************************************************************************//** + * @file nu_qei.h + * @version V3.00 + * @brief Quadrature Encoder Interface (QEI) driver header file + * + * @copyright SPDX-License-Identifier: Apache-2.0 + * @copyright Copyright (C) 2020 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ +#ifndef __NU_QEI_H__ +#define __NU_QEI_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup QEI_Driver QEI Driver + @{ +*/ + +/** @addtogroup QEI_EXPORTED_CONSTANTS QEI Exported Constants + @{ +*/ + +/*---------------------------------------------------------------------------------------------------------*/ +/* QEI counting mode selection constants definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define QEI_CTL_X4_FREE_COUNTING_MODE (0x0<CTL &= (~QEI_CTL_CMPEN_Msk)) + +/** + * @brief Enable QEI compare function + * @param[in] qei The pointer of the specified QEI module. + * @return None + * @details This macro enable QEI counter compare function. + * \hideinitializer + */ +#define QEI_ENABLE_CNT_CMP(qei) ((qei)->CTL |= QEI_CTL_CMPEN_Msk) + +/** + * @brief Disable QEI index latch function + * @param[in] qei The pointer of the specified QEI module. + * @return None + * @details This macro disable QEI index trigger counter latch function. + * \hideinitializer + */ +#define QEI_DISABLE_INDEX_LATCH(qei) ((qei)->CTL &= (~QEI_CTL_IDXLATEN_Msk)) + +/** + * @brief Enable QEI index latch function + * @param[in] qei The pointer of the specified QEI module. + * @return None + * @details This macro enable QEI index trigger counter latch function. + * \hideinitializer + */ +#define QEI_ENABLE_INDEX_LATCH(qei) ((qei)->CTL |= QEI_CTL_IDXLATEN_Msk) + +/** + * @brief Disable QEI index reload function + * @param[in] qei The pointer of the specified QEI module. + * @return None + * @details This macro disable QEI index trigger counter reload function. + * \hideinitializer + */ +#define QEI_DISABLE_INDEX_RELOAD(qei) ((qei)->CTL &= (~QEI_CTL_IDXRLDEN_Msk)) + +/** + * @brief Enable QEI index reload function + * @param[in] qei The pointer of the specified QEI module. + * @return None + * @details This macro enable QEI index trigger counter reload function. + * \hideinitializer + */ +#define QEI_ENABLE_INDEX_RELOAD(qei) ((qei)->CTL |= QEI_CTL_IDXRLDEN_Msk) + +/** + * @brief Disable QEI input + * @param[in] qei The pointer of the specified QEI module. + * @param[in] u32InputType Input signal type. + * - \ref QEI_CTL_CHAEN_Msk : QEA input + * - \ref QEI_CTL_CHAEN_Msk : QEB input + * - \ref QEI_CTL_IDXEN_Msk : IDX input + * @return None + * @details This macro disable specified QEI signal input. + * \hideinitializer + */ +#define QEI_DISABLE_INPUT(qei, u32InputType) ((qei)->CTL &= ~(u32InputType)) + +/** + * @brief Enable QEI input + * @param[in] qei The pointer of the specified QEI module. + * @param[in] u32InputType Input signal type . + * - \ref QEI_CTL_CHAEN_Msk : QEA input + * - \ref QEI_CTL_CHBEN_Msk : QEB input + * - \ref QEI_CTL_IDXEN_Msk : IDX input + * @return None + * @details This macro enable specified QEI signal input. + * \hideinitializer + */ +#define QEI_ENABLE_INPUT(qei, u32InputType) ((qei)->CTL |= (u32InputType)) + +/** + * @brief Disable inverted input polarity + * @param[in] qei The pointer of the specified QEI module. + * @param[in] u32InputType Input signal type . + * - \ref QEI_CTL_CHAINV_Msk : QEA Input + * - \ref QEI_CTL_CHBINV_Msk : QEB Input + * - \ref QEI_CTL_IDXINV_Msk : IDX Input + * @return None + * @details This macro disable specified QEI signal inverted input polarity. + * \hideinitializer + */ +#define QEI_DISABLE_INPUT_INV(qei, u32InputType) ((qei)->CTL &= ~(u32InputType)) + +/** + * @brief Enable inverted input polarity + * @param[in] qei The pointer of the specified QEI module. + * @param[in] u32InputType Input signal type. + * - \ref QEI_CTL_CHAINV_Msk : QEA Input + * - \ref QEI_CTL_CHBINV_Msk : QEB Input + * - \ref QEI_CTL_IDXINV_Msk : IDX Input + * @return None + * @details This macro inverse specified QEI signal input polarity. + * \hideinitializer + */ +#define QEI_ENABLE_INPUT_INV(qei, u32InputType) ((qei)->CTL |= (u32InputType)) + +/** + * @brief Disable QEI interrupt + * @param[in] qei The pointer of the specified QEI module. + * @param[in] u32IntSel Interrupt type selection. + * - \ref QEI_CTL_DIRIEN_Msk : Direction change interrupt + * - \ref QEI_CTL_OVUNIEN_Msk : Counter overflow or underflow interrupt + * - \ref QEI_CTL_CMPIEN_Msk : Compare-match interrupt + * - \ref QEI_CTL_IDXIEN_Msk : Index detected interrupt + * @return None + * @details This macro disable specified QEI interrupt. + * \hideinitializer + */ +#define QEI_DISABLE_INT(qei, u32IntSel) ((qei)->CTL &= ~(u32IntSel)) + +/** + * @brief Enable QEI interrupt + * @param[in] qei The pointer of the specified QEI module. + * @param[in] u32IntSel Interrupt type selection. + * - \ref QEI_CTL_DIRIEN_Msk : Direction change interrupt + * - \ref QEI_CTL_OVUNIEN_Msk : Counter overflow or underflow interrupt + * - \ref QEI_CTL_CMPIEN_Msk : Compare-match interrupt + * - \ref QEI_CTL_IDXIEN_Msk : Index detected interrupt + * @return None + * @details This macro enable specified QEI interrupt. + * \hideinitializer + */ +#define QEI_ENABLE_INT(qei, u32IntSel) ((qei)->CTL |= (u32IntSel)) + +/** + * @brief Disable QEI noise filter + * @param[in] qei The pointer of the specified QEI module. + * @return None + * @details This macro disable QEI noise filter function. + * \hideinitializer + */ +#define QEI_DISABLE_NOISE_FILTER(qei) ((qei)->CTL |= QEI_CTL_NFDIS_Msk) + +/** + * @brief Enable QEI noise filter + * @param[in] qei The pointer of the specified QEI module. + * @param[in] u32ClkSel The sampling frequency of the noise filter clock. + * - \ref QEI_CTL_NFCLKSEL_DIV1 + * - \ref QEI_CTL_NFCLKSEL_DIV2 + * - \ref QEI_CTL_NFCLKSEL_DIV4 + * - \ref QEI_CTL_NFCLKSEL_DIV16 + * - \ref QEI_CTL_NFCLKSEL_DIV32 + * - \ref QEI_CTL_NFCLKSEL_DIV64 + * @return None + * @details This macro enable QEI noise filter function and select noise filter clock. + * \hideinitializer + */ +#define QEI_ENABLE_NOISE_FILTER(qei, u32ClkSel) ((qei)->CTL = ((qei)->CTL & (~(QEI_CTL_NFDIS_Msk|QEI_CTL_NFCLKSEL_Msk))) | (u32ClkSel)) + +/** + * @brief Get QEI counter value + * @param[in] qei The pointer of the specified QEI module. + * @return QEI pulse counter register value. + * @details This macro get QEI pulse counter value. + * \hideinitializer + */ +#define QEI_GET_CNT_VALUE(qei) ((qei)->CNT) + +/** + * @brief Get QEI counting direction + * @param[in] qei The pointer of the specified QEI module. + * @retval 0 QEI counter is in down-counting. + * @retval 1 QEI counter is in up-counting. + * @details This macro get QEI counting direction. + * \hideinitializer + */ +#define QEI_GET_DIR(qei) (((qei)->STATUS & (QEI_STATUS_DIRF_Msk))?1:0) + +/** + * @brief Get QEI counter hold value + * @param[in] qei The pointer of the specified QEI module. + * @return QEI pulse counter hold register value. + * @details This macro get QEI pulse counter hold value, which is updated with counter value in hold counter value control. + * \hideinitializer + */ +#define QEI_GET_HOLD_VALUE(qei) ((qei)->CNTHOLD) + +/** + * @brief Get QEI counter index latch value + * @param[in] qei The pointer of the specified QEI module. + * @return QEI pulse counter index latch value + * @details This macro get QEI pulse counter index latch value, which is updated with counter value when the index is detected. + * \hideinitializer + */ +#define QEI_GET_INDEX_LATCH_VALUE(qei) ((qei)->CNTLATCH) + +/** + * @brief Set QEI counter index latch value + * @param[in] qei The pointer of the specified QEI module. + * @param[in] u32Val The latch value. + * @return QEI pulse counter index latch value + * @details This macro set QEI pulse counter index latch value, which is updated with counter value when the index is detected. + * \hideinitializer + */ +#define QEI_SET_INDEX_LATCH_VALUE(qei,u32Val) ((qei)->CNTLATCH = (u32Val)) + +/** + * @brief Get QEI interrupt flag status + * @param[in] qei The pointer of the specified QEI module. + * @param[in] u32IntSel Interrupt type selection. +* - \ref QEI_STATUS_DIRF_Msk : Counting direction flag + * - \ref QEI_STATUS_DIRCHGF_Msk : Direction change flag + * - \ref QEI_STATUS_OVUNF_Msk : Counter overflow or underflow flag + * - \ref QEI_STATUS_CMPF_Msk : Compare-match flag + * - \ref QEI_STATUS_IDXF_Msk : Index detected flag + * @retval 0 QEI specified interrupt flag is not set. + * @retval 1 QEI specified interrupt flag is set. + * @details This macro get QEI specified interrupt flag status. + * \hideinitializer + */ +#define QEI_GET_INT_FLAG(qei, u32IntSel) (((qei)->STATUS & (u32IntSel))?1:0) + + +/** + * @brief Clear QEI interrupt flag + * @param[in] qei The pointer of the specified QEI module. + * @param[in] u32IntSel Interrupt type selection. + * - \ref QEI_STATUS_DIRCHGF_Msk : Direction change flag + * - \ref QEI_STATUS_OVUNF_Msk : Counter overflow or underflow flag + * - \ref QEI_STATUS_CMPF_Msk : Compare-match flag + * - \ref QEI_STATUS_IDXF_Msk : Index detected flag + * @return None + * @details This macro clear QEI specified interrupt flag. + * \hideinitializer + */ +#define QEI_CLR_INT_FLAG(qei, u32IntSel) ((qei)->STATUS = (u32IntSel)) + +/** + * @brief Set QEI counter compare value + * @param[in] qei The pointer of the specified QEI module. + * @param[in] u32Value The counter compare value. + * @return None + * @details This macro set QEI pulse counter compare value. + * \hideinitializer + */ +#define QEI_SET_CNT_CMP(qei, u32Value) ((qei)->CNTCMP = (u32Value)) + +/** + * @brief Set QEI counter value + * @param[in] qei The pointer of the specified QEI module. + * @param[in] u32Value The counter compare value. + * @return None + * @details This macro set QEI pulse counter value. + * \hideinitializer + */ +#define QEI_SET_CNT_VALUE(qei, u32Value) ((qei)->CNT = (u32Value)) + +/** + * @brief Enable QEI counter hold mode + * @param[in] qei The pointer of the specified QEI module. + * @param[in] u32Type The triggered type. + * - \ref QEI_CTL_HOLDCNT_Msk : Hold QEI_CNT control + * - \ref QEI_CTL_HOLDTMR0_Msk : Hold QEI_CNT by Timer0 + * - \ref QEI_CTL_HOLDTMR1_Msk : Hold QEI_CNT by Timer1 + * - \ref QEI_CTL_HOLDTMR2_Msk : Hold QEI_CNT by Timer2 + * - \ref QEI_CTL_HOLDTMR3_Msk : Hold QEI_CNT by Timer3 + * @return None + * @details This macro enable QEI counter hold mode. + * \hideinitializer + */ +#define QEI_ENABLE_HOLD_TRG_SRC(qei, u32Type) ((qei)->CTL |= (u32Type)) + +/** + * @brief Disable QEI counter hold mode + * @param[in] qei The pointer of the specified QEI module. + * @param[in] u32Type The triggered type. + * - \ref QEI_CTL_HOLDCNT_Msk : Hold QEI_CNT control + * - \ref QEI_CTL_HOLDTMR0_Msk : Hold QEI_CNT by Timer0 + * - \ref QEI_CTL_HOLDTMR1_Msk : Hold QEI_CNT by Timer1 + * - \ref QEI_CTL_HOLDTMR2_Msk : Hold QEI_CNT by Timer2 + * - \ref QEI_CTL_HOLDTMR3_Msk : Hold QEI_CNT by Timer3 + * @return None + * @details This macro disable QEI counter hold mode. + * \hideinitializer + */ +#define QEI_DISABLE_HOLD_TRG_SRC(qei, u32Type) ((qei)->CTL &= ~(u32Type)) + +/** + * @brief Set QEI maximum count value + * @param[in] qei The pointer of the specified QEI module. + * @param[in] u32Value The counter maximum value. + * @return QEI maximum count value + * @details This macro set QEI maximum count value. + * \hideinitializer + */ +#define QEI_SET_CNT_MAX(qei, u32Value) ((qei)->CNTMAX = (u32Value)) + +/** + * @brief Set QEI counting mode + * @param[in] qei The pointer of the specified QEI module. + * @param[in] u32Mode QEI counting mode. + * - \ref QEI_CTL_X4_FREE_COUNTING_MODE + * - \ref QEI_CTL_X2_FREE_COUNTING_MODE + * - \ref QEI_CTL_X4_COMPARE_COUNTING_MODE + * - \ref QEI_CTL_X2_COMPARE_COUNTING_MODE + * @return None + * @details This macro set QEI counting mode. + * \hideinitializer + */ +#define QEI_SET_CNT_MODE(qei, u32Mode) ((qei)->CTL = ((qei)->CTL & (~QEI_CTL_MODE_Msk)) | (u32Mode)) + + +void QEI_Close(QEI_T* qei); +void QEI_DisableInt(QEI_T* qei, uint32_t u32IntSel); +void QEI_EnableInt(QEI_T* qei, uint32_t u32IntSel); +void QEI_Open(QEI_T* qei, uint32_t u32Mode, uint32_t u32Value); +void QEI_Start(QEI_T* qei); +void QEI_Stop(QEI_T* qei); + + +/**@}*/ /* end of group QEI_EXPORTED_FUNCTIONS */ + +/**@}*/ /* end of group QEI_Driver */ + +/**@}*/ /* end of group Standard_Driver */ + +#ifdef __cplusplus +} +#endif + +#endif /*__NU_QEI_H__*/ diff --git a/Ubiquitous/XiZi/board/nuvoton-m2354/third_party_driver/include/Drivers/nu_qspi.h b/Ubiquitous/XiZi/board/nuvoton-m2354/third_party_driver/include/Drivers/nu_qspi.h new file mode 100644 index 0000000..cff6014 --- /dev/null +++ b/Ubiquitous/XiZi/board/nuvoton-m2354/third_party_driver/include/Drivers/nu_qspi.h @@ -0,0 +1,399 @@ +/****************************************************************************** + * @file nu_qspi.h + * @version V3.00 + * @brief M2354 series QSPI driver header file + * + * @copyright SPDX-License-Identifier: Apache-2.0 + * @copyright Copyright (C) 2020 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ +#ifndef __NU_QSPI_H__ +#define __NU_QSPI_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup QSPI_Driver QSPI Driver + @{ +*/ + +/** @addtogroup QSPI_EXPORTED_CONSTANTS QSPI Exported Constants + @{ +*/ + +#define QSPI_MODE_0 (QSPI_CTL_TXNEG_Msk) /*!< CLKPOL=0; RXNEG=0; TXNEG=1 */ +#define QSPI_MODE_1 (QSPI_CTL_RXNEG_Msk) /*!< CLKPOL=0; RXNEG=1; TXNEG=0 */ +#define QSPI_MODE_2 (QSPI_CTL_CLKPOL_Msk | QSPI_CTL_RXNEG_Msk) /*!< CLKPOL=1; RXNEG=1; TXNEG=0 */ +#define QSPI_MODE_3 (QSPI_CTL_CLKPOL_Msk | QSPI_CTL_TXNEG_Msk) /*!< CLKPOL=1; RXNEG=0; TXNEG=1 */ + +#define QSPI_SLAVE (QSPI_CTL_SLAVE_Msk) /*!< Set as slave */ +#define QSPI_MASTER (0x0UL) /*!< Set as master */ + +#define QSPI_SS (QSPI_SSCTL_SS_Msk) /*!< Set SS */ +#define QSPI_SS_ACTIVE_HIGH (QSPI_SSCTL_SSACTPOL_Msk) /*!< SS active high */ +#define QSPI_SS_ACTIVE_LOW (0x0UL) /*!< SS active low */ + +/* QSPI Interrupt Mask */ +#define QSPI_UNIT_INT_MASK (0x001UL) /*!< Unit transfer interrupt mask */ +#define QSPI_SSACT_INT_MASK (0x002UL) /*!< Slave selection signal active interrupt mask */ +#define QSPI_SSINACT_INT_MASK (0x004UL) /*!< Slave selection signal inactive interrupt mask */ +#define QSPI_SLVUR_INT_MASK (0x008UL) /*!< Slave under run interrupt mask */ +#define QSPI_SLVBE_INT_MASK (0x010UL) /*!< Slave bit count error interrupt mask */ +#define QSPI_SLVTO_INT_MASK (0x020UL) /*!< Slave Mode Time-out interrupt mask */ +#define QSPI_TXUF_INT_MASK (0x040UL) /*!< Slave TX underflow interrupt mask */ +#define QSPI_FIFO_TXTH_INT_MASK (0x080UL) /*!< FIFO TX threshold interrupt mask */ +#define QSPI_FIFO_RXTH_INT_MASK (0x100UL) /*!< FIFO RX threshold interrupt mask */ +#define QSPI_FIFO_RXOV_INT_MASK (0x200UL) /*!< FIFO RX overrun interrupt mask */ +#define QSPI_FIFO_RXTO_INT_MASK (0x400UL) /*!< FIFO RX time-out interrupt mask */ + +/* QSPI Status Mask */ +#define QSPI_BUSY_MASK (0x01UL) /*!< Busy status mask */ +#define QSPI_RX_EMPTY_MASK (0x02UL) /*!< RX empty status mask */ +#define QSPI_RX_FULL_MASK (0x04UL) /*!< RX full status mask */ +#define QSPI_TX_EMPTY_MASK (0x08UL) /*!< TX empty status mask */ +#define QSPI_TX_FULL_MASK (0x10UL) /*!< TX full status mask */ +#define QSPI_TXRX_RESET_MASK (0x20UL) /*!< TX or RX reset status mask */ +#define QSPI_SPIEN_STS_MASK (0x40UL) /*!< SPIEN status mask */ +#define QSPI_SSLINE_STS_MASK (0x80UL) /*!< QSPIx_SS line status mask */ + +/* QSPI Status2 Mask */ +#define QSPI_SLVBENUM_MASK (0x01UL) /*!< Effective bit number of uncompleted RX data status mask */ + +/**@}*/ /* end of group QSPI_EXPORTED_CONSTANTS */ + + +/** @addtogroup QSPI_EXPORTED_FUNCTIONS QSPI Exported Functions + @{ +*/ + +/** + * @brief Clear the unit transfer interrupt flag. + * @param[in] qspi The pointer of the specified QSPI module. + * @return None. + * @details Write 1 to UNITIF bit of QSPI_STATUS register to clear the unit transfer interrupt flag. + */ +#define QSPI_CLR_UNIT_TRANS_INT_FLAG(qspi) ( (qspi)->STATUS = QSPI_STATUS_UNITIF_Msk ) + +/** + * @brief Disable 2-bit Transfer mode. + * @param[in] qspi The pointer of the specified QSPI module. + * @return None. + * @details Clear TWOBIT bit of QSPI_CTL register to disable 2-bit Transfer mode. + */ +#define QSPI_DISABLE_2BIT_MODE(qspi) ( (qspi)->CTL &= ~QSPI_CTL_TWOBIT_Msk ) + +/** + * @brief Disable Slave 3-wire mode. + * @param[in] qspi The pointer of the specified QSPI module. + * @return None. + * @details Clear SLV3WIRE bit of QSPI_SSCTL register to disable Slave 3-wire mode. + */ +#define QSPI_DISABLE_3WIRE_MODE(qspi) ( (qspi)->SSCTL &= ~QSPI_SSCTL_SLV3WIRE_Msk ) + +/** + * @brief Disable Dual I/O mode. + * @param[in] qspi The pointer of the specified QSPI module. + * @return None. + * @details Clear DUALIOEN bit of QSPI_CTL register to disable Dual I/O mode. + */ +#define QSPI_DISABLE_DUAL_MODE(qspi) ( (qspi)->CTL &= ~QSPI_CTL_DUALIOEN_Msk ) + +/** + * @brief Disable Quad I/O mode. + * @param[in] qspi The pointer of the specified QSPI module. + * @return None. + * @details Clear QUADIOEN bit of QSPI_CTL register to disable Quad I/O mode. + */ +#define QSPI_DISABLE_QUAD_MODE(qspi) ( (qspi)->CTL &= ~QSPI_CTL_QUADIOEN_Msk ) + +/** + * @brief Disable TX DTR mode. + * @param[in] qspi The pointer of the specified QSPI module. + * @return None. + * @details Clear TXDTREN bit of QSPI_CTL register to disable TX DTR mode. + */ +#define QSPI_DISABLE_TXDTR_MODE(qspi) ( (qspi)->CTL &= ~QSPI_CTL_TXDTREN_Msk ) + +/** + * @brief Enable 2-bit Transfer mode. + * @param[in] qspi The pointer of the specified QSPI module. + * @return None. + * @details Set TWOBIT bit of QSPI_CTL register to enable 2-bit Transfer mode. + */ +#define QSPI_ENABLE_2BIT_MODE(qspi) ( (qspi)->CTL |= QSPI_CTL_TWOBIT_Msk ) + +/** + * @brief Enable Slave 3-wire mode. + * @param[in] qspi The pointer of the specified QSPI module. + * @return None. + * @details Set SLV3WIRE bit of QSPI_SSCTL register to enable Slave 3-wire mode. + */ +#define QSPI_ENABLE_3WIRE_MODE(qspi) ( (qspi)->SSCTL |= QSPI_SSCTL_SLV3WIRE_Msk ) + +/** + * @brief Enable Dual input mode. + * @param[in] qspi The pointer of the specified QSPI module. + * @return None. + * @details Clear DATDIR bit and set DUALIOEN bit of QSPI_CTL register to enable Dual input mode. + */ +#define QSPI_ENABLE_DUAL_INPUT_MODE(qspi) ( (qspi)->CTL = ((qspi)->CTL & (~QSPI_CTL_DATDIR_Msk)) | QSPI_CTL_DUALIOEN_Msk ) + +/** + * @brief Enable Dual output mode. + * @param[in] qspi The pointer of the specified QSPI module. + * @return None. + * @details Set DATDIR bit and DUALIOEN bit of QSPI_CTL register to enable Dual output mode. + */ +#define QSPI_ENABLE_DUAL_OUTPUT_MODE(qspi) ( (qspi)->CTL |= (QSPI_CTL_DATDIR_Msk | QSPI_CTL_DUALIOEN_Msk) ) + +/** + * @brief Enable Quad input mode. + * @param[in] qspi The pointer of the specified QSPI module. + * @return None. + * @details Clear DATDIR bit and set QUADIOEN bit of QSPI_CTL register to enable Quad input mode. + */ +#define QSPI_ENABLE_QUAD_INPUT_MODE(qspi) ( (qspi)->CTL = ((qspi)->CTL & (~QSPI_CTL_DATDIR_Msk)) | QSPI_CTL_QUADIOEN_Msk ) + +/** + * @brief Enable Quad output mode. + * @param[in] qspi The pointer of the specified QSPI module. + * @return None. + * @details Set DATDIR bit and QUADIOEN bit of QSPI_CTL register to enable Quad output mode. + */ +#define QSPI_ENABLE_QUAD_OUTPUT_MODE(qspi) ( (qspi)->CTL |= (QSPI_CTL_DATDIR_Msk | QSPI_CTL_QUADIOEN_Msk) ) + +/** + * @brief Enable TX DTR mode. + * @param[in] qspi The pointer of the specified QSPI module. + * @return None. + * @details Set TXDTREN bit of QSPI_CTL register to enable TX DTR mode. + */ +#define QSPI_ENABLE_TXDTR_MODE(qspi) ( (qspi)->CTL |= QSPI_CTL_TXDTREN_Msk ) + +/** + * @brief Trigger RX PDMA function. + * @param[in] qspi The pointer of the specified QSPI module. + * @return None. + * @details Set RXPDMAEN bit of QSPI_PDMACTL register to enable RX PDMA transfer function. + */ +#define QSPI_TRIGGER_RX_PDMA(qspi) ( (qspi)->PDMACTL |= QSPI_PDMACTL_RXPDMAEN_Msk ) + +/** + * @brief Trigger TX PDMA function. + * @param[in] qspi The pointer of the specified QSPI module. + * @return None. + * @details Set TXPDMAEN bit of QSPI_PDMACTL register to enable TX PDMA transfer function. + */ +#define QSPI_TRIGGER_TX_PDMA(qspi) ( (qspi)->PDMACTL |= QSPI_PDMACTL_TXPDMAEN_Msk ) + +/** + * @brief Trigger TX and RX PDMA function. + * @param[in] qspi The pointer of the specified QSPI module. + * @return None. + * @details Set TXPDMAEN bit and RXPDMAEN bit of QSPI_PDMACTL register to enable TX and RX PDMA transfer function. + */ +#define QSPI_TRIGGER_TX_RX_PDMA(qspi) ( (qspi)->PDMACTL |= (QSPI_PDMACTL_TXPDMAEN_Msk | QSPI_PDMACTL_RXPDMAEN_Msk) ) + +/** + * @brief Disable RX PDMA transfer. + * @param[in] qspi The pointer of the specified QSPI module. + * @return None. + * @details Clear RXPDMAEN bit of QSPI_PDMACTL register to disable RX PDMA transfer function. + */ +#define QSPI_DISABLE_RX_PDMA(qspi) ( (qspi)->PDMACTL &= ~QSPI_PDMACTL_RXPDMAEN_Msk ) + +/** + * @brief Disable TX PDMA transfer. + * @param[in] qspi The pointer of the specified QSPI module. + * @return None. + * @details Clear TXPDMAEN bit of QSPI_PDMACTL register to disable TX PDMA transfer function. + */ +#define QSPI_DISABLE_TX_PDMA(qspi) ( (qspi)->PDMACTL &= ~QSPI_PDMACTL_TXPDMAEN_Msk ) + +/** + * @brief Disable TX and RX PDMA transfer. + * @param[in] qspi The pointer of the specified QSPI module. + * @return None. + * @details Clear TXPDMAEN bit and RXPDMAEN bit of QSPI_PDMACTL register to disable TX and RX PDMA transfer function. + */ +#define QSPI_DISABLE_TX_RX_PDMA(qspi) ( (qspi)->PDMACTL &= ~(QSPI_PDMACTL_TXPDMAEN_Msk | QSPI_PDMACTL_RXPDMAEN_Msk) ) + +/** + * @brief Get the count of available data in RX FIFO. + * @param[in] qspi The pointer of the specified QSPI module. + * @return The count of available data in RX FIFO. + * @details Read RXCNT (QSPI_STATUS[27:24]) to get the count of available data in RX FIFO. + */ +#define QSPI_GET_RX_FIFO_COUNT(qspi) ( ((qspi)->STATUS & QSPI_STATUS_RXCNT_Msk) >> QSPI_STATUS_RXCNT_Pos ) + +/** + * @brief Get the RX FIFO empty flag. + * @param[in] qspi The pointer of the specified QSPI module. + * @retval 0 RX FIFO is not empty. + * @retval 1 RX FIFO is empty. + * @details Read RXEMPTY bit of QSPI_STATUS register to get the RX FIFO empty flag. + */ +#define QSPI_GET_RX_FIFO_EMPTY_FLAG(qspi) ( ((qspi)->STATUS & QSPI_STATUS_RXEMPTY_Msk) >> QSPI_STATUS_RXEMPTY_Pos ) + +/** + * @brief Get the TX FIFO empty flag. + * @param[in] qspi The pointer of the specified QSPI module. + * @retval 0 TX FIFO is not empty. + * @retval 1 TX FIFO is empty. + * @details Read TXEMPTY bit of QSPI_STATUS register to get the TX FIFO empty flag. + */ +#define QSPI_GET_TX_FIFO_EMPTY_FLAG(qspi) ( ((qspi)->STATUS & QSPI_STATUS_TXEMPTY_Msk) >> QSPI_STATUS_TXEMPTY_Pos ) + +/** + * @brief Get the TX FIFO full flag. + * @param[in] qspi The pointer of the specified QSPI module. + * @retval 0 TX FIFO is not full. + * @retval 1 TX FIFO is full. + * @details Read TXFULL bit of QSPI_STATUS register to get the TX FIFO full flag. + */ +#define QSPI_GET_TX_FIFO_FULL_FLAG(qspi) ( ((qspi)->STATUS & QSPI_STATUS_TXFULL_Msk) >> QSPI_STATUS_TXFULL_Pos ) + +/** + * @brief Get the datum read from RX register. + * @param[in] qspi The pointer of the specified QSPI module. + * @return Data in RX register. + * @details Read QSPI_RX register to get the received datum. + */ +#define QSPI_READ_RX(qspi) ( (qspi)->RX ) + +/** + * @brief Write datum to TX register. + * @param[in] qspi The pointer of the specified QSPI module. + * @param[in] u32TxData The datum which user attempt to transfer through QSPI bus. + * @return None. + * @details Write u32TxData to QSPI_TX register. + */ +#define QSPI_WRITE_TX(qspi, u32TxData) ( (qspi)->TX = (u32TxData) ) + +/** + * @brief Set QSPIx_SS pin to high state. + * @param[in] qspi The pointer of the specified QSPI module. + * @return None. + * @details Disable automatic slave selection function and set QSPIx_SS pin to high state. + */ +#define QSPI_SET_SS_HIGH(qspi) ( (qspi)->SSCTL = ((qspi)->SSCTL & (~QSPI_SSCTL_AUTOSS_Msk)) | (QSPI_SSCTL_SSACTPOL_Msk | QSPI_SSCTL_SS_Msk) ) + +/** + * @brief Set QSPIx_SS pin to low state. + * @param[in] qspi The pointer of the specified QSPI module. + * @return None. + * @details Disable automatic slave selection function and set QSPIx_SS pin to low state. + */ +#define QSPI_SET_SS_LOW(qspi) ( (qspi)->SSCTL = ((qspi)->SSCTL & (~(QSPI_SSCTL_AUTOSS_Msk | QSPI_SSCTL_SSACTPOL_Msk))) | QSPI_SSCTL_SS_Msk ) + +/** + * @brief Enable Byte Reorder function. + * @param[in] qspi The pointer of the specified QSPI module. + * @return None. + * @details Enable Byte Reorder function. The suspend interval depends on the setting of SUSPITV (QSPI_CTL[7:4]). + */ +#define QSPI_ENABLE_BYTE_REORDER(qspi) ( (qspi)->CTL |= QSPI_CTL_REORDER_Msk ) + +/** + * @brief Disable Byte Reorder function. + * @param[in] qspi The pointer of the specified QSPI module. + * @return None. + * @details Clear REORDER bit field of QSPI_CTL register to disable Byte Reorder function. + */ +#define QSPI_DISABLE_BYTE_REORDER(qspi) ( (qspi)->CTL &= ~QSPI_CTL_REORDER_Msk ) + +/** + * @brief Set the length of suspend interval. + * @param[in] qspi The pointer of the specified QSPI module. + * @param[in] u32SuspCycle Decides the length of suspend interval. It could be 0 ~ 15. + * @return None. + * @details Set the length of suspend interval according to u32SuspCycle. + * The length of suspend interval is ((u32SuspCycle + 0.5) * the length of one QSPI bus clock cycle). + */ +#define QSPI_SET_SUSPEND_CYCLE(qspi, u32SuspCycle) ( (qspi)->CTL = ((qspi)->CTL & ~QSPI_CTL_SUSPITV_Msk) | ((u32SuspCycle) << QSPI_CTL_SUSPITV_Pos) ) + +/** + * @brief Set the QSPI transfer sequence with LSB first. + * @param[in] qspi The pointer of the specified QSPI module. + * @return None. + * @details Set LSB bit of QSPI_CTL register to set the QSPI transfer sequence with LSB first. + */ +#define QSPI_SET_LSB_FIRST(qspi) ( (qspi)->CTL |= QSPI_CTL_LSB_Msk ) + +/** + * @brief Set the QSPI transfer sequence with MSB first. + * @param[in] qspi The pointer of the specified QSPI module. + * @return None. + * @details Clear LSB bit of QSPI_CTL register to set the QSPI transfer sequence with MSB first. + */ +#define QSPI_SET_MSB_FIRST(qspi) ( (qspi)->CTL &= ~QSPI_CTL_LSB_Msk ) + +/** + * @brief Set the data width of a QSPI transaction. + * @param[in] qspi The pointer of the specified QSPI module. + * @param[in] u32Width The bit width of one transaction. + * @return None. + * @details The data width can be 8 ~ 32 bits. + */ +#define QSPI_SET_DATA_WIDTH(qspi, u32Width) ( (qspi)->CTL = ((qspi)->CTL & ~QSPI_CTL_DWIDTH_Msk) | (((u32Width) & 0x1F) << QSPI_CTL_DWIDTH_Pos) ) + +/** + * @brief Get the QSPI busy state. + * @param[in] qspi The pointer of the specified QSPI module. + * @retval 0 QSPI controller is not busy. + * @retval 1 QSPI controller is busy. + * @details This macro will return the busy state of QSPI controller. + */ +#define QSPI_IS_BUSY(qspi) ( ((qspi)->STATUS & QSPI_STATUS_BUSY_Msk) >> QSPI_STATUS_BUSY_Pos ) + +/** + * @brief Enable QSPI controller. + * @param[in] qspi The pointer of the specified QSPI module. + * @return None. + * @details Set SPIEN (QSPI_CTL[0]) to enable QSPI controller. + */ +#define QSPI_ENABLE(qspi) ( (qspi)->CTL |= QSPI_CTL_SPIEN_Msk ) + +/** + * @brief Disable QSPI controller. + * @param[in] qspi The pointer of the specified QSPI module. + * @return None. + * @details Clear SPIEN (QSPI_CTL[0]) to disable QSPI controller. + */ +#define QSPI_DISABLE(qspi) ( (qspi)->CTL &= ~QSPI_CTL_SPIEN_Msk ) + +/* Function prototype declaration */ +uint32_t QSPI_Open(QSPI_T *qspi, uint32_t u32MasterSlave, uint32_t u32QSPIMode, uint32_t u32DataWidth, uint32_t u32BusClock); +void QSPI_Close(QSPI_T *qspi); +void QSPI_ClearRxFIFO(QSPI_T *qspi); +void QSPI_ClearTxFIFO(QSPI_T *qspi); +void QSPI_DisableAutoSS(QSPI_T *qspi); +void QSPI_EnableAutoSS(QSPI_T *qspi, uint32_t u32SSPinMask, uint32_t u32ActiveLevel); +uint32_t QSPI_SetBusClock(QSPI_T *qspi, uint32_t u32BusClock); +void QSPI_SetFIFO(QSPI_T *qspi, uint32_t u32TxThreshold, uint32_t u32RxThreshold); +uint32_t QSPI_GetBusClock(QSPI_T *qspi); +void QSPI_EnableInt(QSPI_T *qspi, uint32_t u32Mask); +void QSPI_DisableInt(QSPI_T *qspi, uint32_t u32Mask); +uint32_t QSPI_GetIntFlag(QSPI_T *qspi, uint32_t u32Mask); +void QSPI_ClearIntFlag(QSPI_T *qspi, uint32_t u32Mask); +uint32_t QSPI_GetStatus(QSPI_T *qspi, uint32_t u32Mask); +uint32_t QSPI_GetStatus2(QSPI_T *qspi, uint32_t u32Mask); + + +/**@}*/ /* end of group QSPI_EXPORTED_FUNCTIONS */ + +/**@}*/ /* end of group QSPI_Driver */ + +/**@}*/ /* end of group Standard_Driver */ + +#ifdef __cplusplus +} +#endif + +#endif /* __NU_QSPI_H__ */ diff --git a/Ubiquitous/XiZi/board/nuvoton-m2354/third_party_driver/include/Drivers/nu_rng.h b/Ubiquitous/XiZi/board/nuvoton-m2354/third_party_driver/include/Drivers/nu_rng.h new file mode 100644 index 0000000..a30251e --- /dev/null +++ b/Ubiquitous/XiZi/board/nuvoton-m2354/third_party_driver/include/Drivers/nu_rng.h @@ -0,0 +1,57 @@ +/**************************************************************************//** + * @file nu_rng.h + * @version V3.00 + * @brief Random Number Generator Interface Controller (rng) driver header file + * + * @copyright SPDX-License-Identifier: Apache-2.0 + * @copyright Copyright (C) 2020 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ +#ifndef __NU_RNG_H__ +#define __NU_RNG_H__ + + +#ifdef __cplusplus +extern "C" +{ +#endif + + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup RNG_Driver RNG Driver + @{ +*/ + +/** @addtogroup RNG_EXPORTED_CONSTANTS RNG Exported Constants + @{ +*/ + +/**@}*/ /* end of group RNG_EXPORTED_CONSTANTS */ + + +/** @addtogroup RNG_EXPORTED_FUNCTIONS RNG Exported Functions + @{ +*/ + +int32_t RNG_Open(void); +int32_t RNG_Random(uint32_t *pu32Buf, int32_t nWords); + +int32_t RNG_ECDSA_Init(uint32_t u32KeySize, uint32_t au32ECC_N[18]); +int32_t RNG_ECDSA(uint32_t u32KeySize); +int32_t RNG_ECDH_Init(uint32_t u32KeySize, uint32_t au32ECC_N[18]); +int32_t RNG_ECDH(uint32_t u32KeySize); + +/**@}*/ /* end of group RNG_EXPORTED_FUNCTIONS */ + +/**@}*/ /* end of group RNG_Driver */ + +/**@}*/ /* end of group Standard_Driver */ + +#ifdef __cplusplus +} +#endif + +#endif /* __NU_RNG_H__ */ + diff --git a/Ubiquitous/XiZi/board/nuvoton-m2354/third_party_driver/include/Drivers/nu_rtc.h b/Ubiquitous/XiZi/board/nuvoton-m2354/third_party_driver/include/Drivers/nu_rtc.h new file mode 100644 index 0000000..6854643 --- /dev/null +++ b/Ubiquitous/XiZi/board/nuvoton-m2354/third_party_driver/include/Drivers/nu_rtc.h @@ -0,0 +1,396 @@ +/**************************************************************************//** + * @file nu_rtc.h + * @version V3.00 + * @brief Real Time Clock(RTC) driver header file + * + * @copyright SPDX-License-Identifier: Apache-2.0 + * @copyright Copyright (C) 2020 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ +#ifndef __NU_RTC_H__ +#define __NU_RTC_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup RTC_Driver RTC Driver + @{ +*/ + +/** @addtogroup RTC_EXPORTED_CONSTANTS RTC Exported Constants + @{ +*/ +/*---------------------------------------------------------------------------------------------------------*/ +/* RTC Initial Keyword Constant Definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define RTC_INIT_KEY 0xA5EB1357UL /*!< RTC Initiation Key to make RTC leaving reset state \hideinitializer */ + +/*---------------------------------------------------------------------------------------------------------*/ +/* RTC Time Attribute Constant Definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define RTC_CLOCK_12 0UL /*!< RTC as 12-hour time scale with AM and PM indication \hideinitializer */ +#define RTC_CLOCK_24 1UL /*!< RTC as 24-hour time scale \hideinitializer */ +#define RTC_AM 1UL /*!< RTC as AM indication \hideinitializer */ +#define RTC_PM 2UL /*!< RTC as PM indication \hideinitializer */ + +/*---------------------------------------------------------------------------------------------------------*/ +/* RTC Tick Period Constant Definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define RTC_TICK_1_SEC 0x0UL /*!< RTC time tick period is 1 second \hideinitializer */ +#define RTC_TICK_1_2_SEC 0x1UL /*!< RTC time tick period is 1/2 second \hideinitializer */ +#define RTC_TICK_1_4_SEC 0x2UL /*!< RTC time tick period is 1/4 second \hideinitializer */ +#define RTC_TICK_1_8_SEC 0x3UL /*!< RTC time tick period is 1/8 second \hideinitializer */ +#define RTC_TICK_1_16_SEC 0x4UL /*!< RTC time tick period is 1/16 second \hideinitializer */ +#define RTC_TICK_1_32_SEC 0x5UL /*!< RTC time tick period is 1/32 second \hideinitializer */ +#define RTC_TICK_1_64_SEC 0x6UL /*!< RTC time tick period is 1/64 second \hideinitializer */ +#define RTC_TICK_1_128_SEC 0x7UL /*!< RTC time tick period is 1/128 second \hideinitializer */ + +/*---------------------------------------------------------------------------------------------------------*/ +/* RTC Day of Week Constant Definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define RTC_SUNDAY 0x0UL /*!< Day of the Week is Sunday \hideinitializer */ +#define RTC_MONDAY 0x1UL /*!< Day of the Week is Monday \hideinitializer */ +#define RTC_TUESDAY 0x2UL /*!< Day of the Week is Tuesday \hideinitializer */ +#define RTC_WEDNESDAY 0x3UL /*!< Day of the Week is Wednesday \hideinitializer */ +#define RTC_THURSDAY 0x4UL /*!< Day of the Week is Thursday \hideinitializer */ +#define RTC_FRIDAY 0x5UL /*!< Day of the Week is Friday \hideinitializer */ +#define RTC_SATURDAY 0x6UL /*!< Day of the Week is Saturday \hideinitializer */ + +/*---------------------------------------------------------------------------------------------------------*/ +/* RTC Miscellaneous Constant Definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define RTC_YEAR2000 2000UL /*!< RTC Reference for compute year data \hideinitializer */ +#define RTC_FCR_REFERENCE 32752 /*!< RTC Reference for frequency compensation */ + +/*---------------------------------------------------------------------------------------------------------*/ +/* RTC Tamper Constant Definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define RTC_TAMPER0_SELECT (0x1UL << 0) /*!< Select Tamper 0 \hideinitializer */ +#define RTC_TAMPER1_SELECT (0x1UL << 1) /*!< Select Tamper 1 \hideinitializer */ +#define RTC_TAMPER2_SELECT (0x1UL << 2) /*!< Select Tamper 2 \hideinitializer */ +#define RTC_TAMPER3_SELECT (0x1UL << 3) /*!< Select Tamper 3 \hideinitializer */ +#define RTC_TAMPER4_SELECT (0x1UL << 4) /*!< Select Tamper 4 \hideinitializer */ +#define RTC_TAMPER5_SELECT (0x1UL << 5) /*!< Select Tamper 5 \hideinitializer */ +#define RTC_MAX_TAMPER_PIN_NUM 6UL /*!< Tamper Pin number \hideinitializer */ + +#define RTC_TAMPER_LOW_LEVEL_DETECT 0UL /*!< Tamper pin detect voltage level is low \hideinitializer */ +#define RTC_TAMPER_HIGH_LEVEL_DETECT 1UL /*!< Tamper pin detect voltage level is high \hideinitializer */ + +#define RTC_TAMPER_DEBOUNCE_DISABLE 0UL /*!< Disable RTC tamper pin de-bounce function \hideinitializer */ +#define RTC_TAMPER_DEBOUNCE_ENABLE 1UL /*!< Enable RTC tamper pin de-bounce function \hideinitializer */ + +#define RTC_PAIR0_SELECT (0x1UL << 0) /*!< Select Pair 0 \hideinitializer */ +#define RTC_PAIR1_SELECT (0x1UL << 1) /*!< Select Pair 1 \hideinitializer */ +#define RTC_PAIR2_SELECT (0x1UL << 2) /*!< Select Pair 2 \hideinitializer */ +#define RTC_MAX_PAIR_NUM 3UL /*!< Pair number \hideinitializer */ + +#define RTC_2POW10_CLK (0x0UL << RTC_TAMPCTL_DYNRATE_Pos) /*!< 1024 RTC clock cycles \hideinitializer */ +#define RTC_2POW11_CLK (0x1UL << RTC_TAMPCTL_DYNRATE_Pos) /*!< 1024 x 2 RTC clock cycles \hideinitializer */ +#define RTC_2POW12_CLK (0x2UL << RTC_TAMPCTL_DYNRATE_Pos) /*!< 1024 x 4 RTC clock cycles \hideinitializer */ +#define RTC_2POW13_CLK (0x3UL << RTC_TAMPCTL_DYNRATE_Pos) /*!< 1024 x 6 RTC clock cycles \hideinitializer */ +#define RTC_2POW14_CLK (0x4UL << RTC_TAMPCTL_DYNRATE_Pos) /*!< 1024 x 8 RTC clock cycles \hideinitializer */ +#define RTC_2POW15_CLK (0x5UL << RTC_TAMPCTL_DYNRATE_Pos) /*!< 1024 x 16 RTC clock cycles \hideinitializer */ +#define RTC_2POW16_CLK (0x6UL << RTC_TAMPCTL_DYNRATE_Pos) /*!< 1024 x 32 RTC clock cycles \hideinitializer */ +#define RTC_2POW17_CLK (0x7UL << RTC_TAMPCTL_DYNRATE_Pos) /*!< 1024 x 64 RTC clock cycles \hideinitializer */ + +#define RTC_REF_RANDOM_PATTERN 0x0UL /*!< The new reference pattern is generated by random number generator when the reference pattern run out \hideinitializer */ +#define RTC_REF_SEED_VALUE 0x1UL /*!< The new reference pattern is repeated from SEED (RTC_TAMPSEED[31:0]) when the reference pattern run out \hideinitializer */ + +/*---------------------------------------------------------------------------------------------------------*/ +/* RTC Clock Source Constant Definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define RTC_CLOCK_SOURCE_LXT 0UL /*!< Set RTC clock source as external LXT \hideinitializer */ +#define RTC_CLOCK_SOURCE_LIRC 1UL /*!< Set RTC clock source as LIRC \hideinitializer */ +#define RTC_CLOCK_SOURCE_LIRC32K 2UL /*!< Set RTC clock source as LIRC32K \hideinitializer */ + +/*---------------------------------------------------------------------------------------------------------*/ +/* RTC GPIO_MODE Constant Definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define RTC_IO_MODE_INPUT 0x0UL /*!< Input Mode */ +#define RTC_IO_MODE_OUTPUT 0x1UL /*!< Output Mode */ +#define RTC_IO_MODE_OPEN_DRAIN 0x2UL /*!< Open-Drain Mode */ +#define RTC_IO_MODE_QUASI 0x3UL /*!< Quasi-bidirectional Mode */ + +#define RTC_IO_DIGITAL_ENABLE 0UL /*!< I/O digital path is enabled */ +#define RTC_IO_DIGITAL_DISABLE 1UL /*!< I/O digital path is disabled */ + +#define RTC_IO_PULL_UP_DOWN_DISABLE 0x0UL /*!< I/O pull-up and pull-down is disabled */ +#define RTC_IO_PULL_UP_ENABLE 0x1UL /*!< I/O pull-up is enabled */ +#define RTC_IO_PULL_DOWN_ENABLE 0x2UL /*!< I/O pull-down is enabled */ + + +/**@}*/ /* end of group RTC_EXPORTED_CONSTANTS */ + + +/** @addtogroup RTC_EXPORTED_STRUCTS RTC Exported Structs + @{ +*/ +/** + * @details RTC define Time Data Struct + */ +typedef struct +{ + uint32_t u32Year; /*!< Year value */ + uint32_t u32Month; /*!< Month value */ + uint32_t u32Day; /*!< Day value */ + uint32_t u32DayOfWeek; /*!< Day of week value */ + uint32_t u32Hour; /*!< Hour value */ + uint32_t u32Minute; /*!< Minute value */ + uint32_t u32Second; /*!< Second value */ + uint32_t u32TimeScale; /*!< 12-Hour, 24-Hour */ + uint32_t u32AmPm; /*!< Only Time Scale select 12-hr used */ +} S_RTC_TIME_DATA_T; + +/**@}*/ /* end of group RTC_EXPORTED_STRUCTS */ + + +/** @addtogroup RTC_EXPORTED_FUNCTIONS RTC Exported Functions + @{ +*/ + +/** + * @brief Indicate is Leap Year or not + * + * @param[in] rtc The pointer of RTC module. + * + * @retval 0 This year is not a leap year + * @retval 1 This year is a leap year + * + * @details According to current date, return this year is leap year or not. + * \hideinitializer + */ +#define RTC_IS_LEAP_YEAR(rtc) (((rtc)->LEAPYEAR & RTC_LEAPYEAR_LEAPYEAR_Msk)? 1:0) + +/** + * @brief Clear RTC Alarm Interrupt Flag + * + * @param[in] rtc The pointer of RTC module. + * + * @return None + * + * @details This macro is used to clear RTC alarm interrupt flag. + * \hideinitializer + */ +#define RTC_CLEAR_ALARM_INT_FLAG(rtc) ((rtc)->INTSTS = RTC_INTSTS_ALMIF_Msk) + +/** + * @brief Clear RTC Tick Interrupt Flag + * + * @param[in] rtc The pointer of RTC module. + * + * @return None + * + * @details This macro is used to clear RTC tick interrupt flag. + * \hideinitializer + */ +#define RTC_CLEAR_TICK_INT_FLAG(rtc) ((rtc)->INTSTS = RTC_INTSTS_TICKIF_Msk) + +/** + * @brief Clear RTC Tamper Interrupt Flag + * + * @param[in] rtc The pointer of RTC module. + * @param[in] u32TamperFlag Tamper interrupt flag. It consists of: \n + * - \ref RTC_INTSTS_TAMP0IF_Msk \n + * - \ref RTC_INTSTS_TAMP1IF_Msk \n + * - \ref RTC_INTSTS_TAMP2IF_Msk \n + * - \ref RTC_INTSTS_TAMP3IF_Msk \n + * - \ref RTC_INTSTS_TAMP4IF_Msk \n + * - \ref RTC_INTSTS_TAMP5IF_Msk + * + * @return None + * + * @details This macro is used to clear RTC tamper pin interrupt flag. + * \hideinitializer + */ +#define RTC_CLEAR_TAMPER_INT_FLAG(rtc, u32TamperFlag) ((rtc)->INTSTS = (u32TamperFlag)) + +/** + * @brief Get RTC Alarm Interrupt Flag + * + * @param[in] rtc The pointer of RTC module. + * + * @retval 0 RTC alarm interrupt did not occur + * @retval 1 RTC alarm interrupt occurred + * + * @details This macro indicates RTC alarm interrupt occurred or not. + * \hideinitializer + */ +#define RTC_GET_ALARM_INT_FLAG(rtc) (((rtc)->INTSTS & RTC_INTSTS_ALMIF_Msk)? 1:0) + +/** + * @brief Get RTC Time Tick Interrupt Flag + * + * @param[in] rtc The pointer of RTC module. + * + * @retval 0 RTC time tick interrupt did not occur + * @retval 1 RTC time tick interrupt occurred + * + * @details This macro indicates RTC time tick interrupt occurred or not. + * \hideinitializer + */ +#define RTC_GET_TICK_INT_FLAG(rtc) (((rtc)->INTSTS & RTC_INTSTS_TICKIF_Msk)? 1:0) + +/** + * @brief Set I/O Control By GPIO + * + * @param[in] rtc The pointer of RTC module. + * + * @return None + * + * @details This macro sets the PF.4~11 pin I/O is controlled by GPIO module. + * \hideinitializer + */ +#define RTC_SET_IOCTL_BY_GPIO(rtc) ((rtc)->LXTCTL &= ~RTC_LXTCTL_IOCTLSEL_Msk) + +/** + * @brief Set I/O Control By RTC + * + * @param[in] rtc The pointer of RTC module. + * + * @return None + * + * @details This macro sets the PF.4~11 pin I/O is controlled by RTC module. + * \hideinitializer + */ +#define RTC_SET_IOCTL_BY_RTC(rtc) ((rtc)->LXTCTL |= RTC_LXTCTL_IOCTLSEL_Msk) + +/** + * @brief Get I/O Control Property + * + * @param[in] rtc The pointer of RTC module. + * + * @retval 0 PF.4~11 pin I/O is controlled by GPIO module + * @retval 1 PF.4~11 pin I/O is controlled by RTC module + * + * @details This macro indicates the PF.4~11 pin I/O control property. + * \hideinitializer + */ +#define RTC_GET_IOCTL_PROPERTY(rtc) (((rtc)->LXTCTL & RTC_LXTCTL_IOCTLSEL_Msk)? 1:0) + +/** + * @brief Get RTC Tamper Interrupt Flag + * + * @param[in] rtc The pointer of RTC module. + * + * @retval 0 RTC tamper event interrupt did not occur + * @retval 1 RTC tamper event interrupt occurred + * + * @details This macro indicates RTC tamper event occurred or not. + * \hideinitializer + */ +#define RTC_GET_TAMPER_INT_FLAG(rtc) (((rtc)->INTSTS & (0x3F00))? 1:0) + +/** + * @brief Get RTC Tamper Interrupt Status + * + * @param[in] rtc The pointer of RTC module. + * + * @retval RTC_INTSTS_TAMP0IF_Msk Tamper 0 interrupt flag is generated + * @retval RTC_INTSTS_TAMP1IF_Msk Tamper 1 interrupt flag is generated + * @retval RTC_INTSTS_TAMP2IF_Msk Tamper 2 interrupt flag is generated + * @retval RTC_INTSTS_TAMP3IF_Msk Tamper 3 interrupt flag is generated + * @retval RTC_INTSTS_TAMP4IF_Msk Tamper 4 interrupt flag is generated + * @retval RTC_INTSTS_TAMP5IF_Msk Tamper 5 interrupt flag is generated + * + * @details This macro indicates RTC tamper interrupt status. + * \hideinitializer + */ +#define RTC_GET_TAMPER_INT_STATUS(rtc) (((rtc)->INTSTS & (0x3F00))) + +/** + * @brief Enable RTC Tick Wake-up Function + * + * @param[in] rtc The pointer of RTC module. + * + * @return None + * + * @details This macro is used to enable RTC tick interrupt wake-up function. + * \hideinitializer + */ +#define RTC_ENABLE_TICK_WAKEUP(rtc) ((rtc)->INTEN |= RTC_INTEN_TICKIEN_Msk); + +/** + * @brief Disable RTC Tick Wake-up Function + * + * @param[in] rtc The pointer of RTC module. + * + * @return None + * + * @details This macro is used to disable RTC tick interrupt wake-up function. + * \hideinitializer + */ +#define RTC_DISABLE_TICK_WAKEUP(rtc) ((rtc)->INTEN &= ~RTC_INTEN_TICKIEN_Msk); + +/** + * @brief Read Spare Register + * + * @param[in] rtc The pointer of RTC module. + * @param[in] u32RegNum The spare register number, 0~19. + * + * @return Spare register content + * + * @details Read the specify spare register content. + * \hideinitializer + */ +#define RTC_READ_SPARE_REGISTER(rtc, u32RegNum) ((rtc)->SPR[(u32RegNum)]) + +/** + * @brief Write Spare Register + * + * @param[in] rtc The pointer of RTC module. + * @param[in] u32RegNum The spare register number, 0~19. + * @param[in] u32RegValue The spare register value. + * + * @return None + * + * @details Write specify data to spare register. + * \hideinitializer + */ +#define RTC_WRITE_SPARE_REGISTER(rtc, u32RegNum, u32RegValue) ((rtc)->SPR[(u32RegNum)] = (u32RegValue)) + + +void RTC_Open(S_RTC_TIME_DATA_T *sPt); +void RTC_Close(void); +void RTC_32KCalibration(int32_t i32FrequencyX10000); +void RTC_GetDateAndTime(S_RTC_TIME_DATA_T *sPt); +void RTC_GetAlarmDateAndTime(S_RTC_TIME_DATA_T *sPt); +void RTC_SetDateAndTime(S_RTC_TIME_DATA_T *sPt); +void RTC_SetAlarmDateAndTime(S_RTC_TIME_DATA_T *sPt); +void RTC_SetDate(uint32_t u32Year, uint32_t u32Month, uint32_t u32Day, uint32_t u32DayOfWeek); +void RTC_SetTime(uint32_t u32Hour, uint32_t u32Minute, uint32_t u32Second, uint32_t u32TimeMode, uint32_t u32AmPm); +void RTC_SetAlarmDate(uint32_t u32Year, uint32_t u32Month, uint32_t u32Day); +void RTC_SetAlarmTime(uint32_t u32Hour, uint32_t u32Minute, uint32_t u32Second, uint32_t u32TimeMode, uint32_t u32AmPm); +void RTC_SetAlarmDateMask(uint8_t u8IsTenYMsk, uint8_t u8IsYMsk, uint8_t u8IsTenMMsk, uint8_t u8IsMMsk, uint8_t u8IsTenDMsk, uint8_t u8IsDMsk); +void RTC_SetAlarmTimeMask(uint8_t u8IsTenHMsk, uint8_t u8IsHMsk, uint8_t u8IsTenMMsk, uint8_t u8IsMMsk, uint8_t u8IsTenSMsk, uint8_t u8IsSMsk); +uint32_t RTC_GetDayOfWeek(void); +void RTC_SetTickPeriod(uint32_t u32TickSelection); +void RTC_EnableInt(uint32_t u32IntFlagMask); +void RTC_DisableInt(uint32_t u32IntFlagMask); +void RTC_EnableSpareAccess(void); +void RTC_DisableSpareRegister(void); +void RTC_StaticTamperEnable(uint32_t u32TamperSelect, uint32_t u32DetecLevel, uint32_t u32DebounceEn); +void RTC_StaticTamperDisable(uint32_t u32TamperSelect); +void RTC_DynamicTamperEnable(uint32_t u32PairSel, uint32_t u32DebounceEn, uint32_t u32Pair1Source, uint32_t u32Pair2Source); +void RTC_DynamicTamperDisable(uint32_t u32PairSel); +void RTC_DynamicTamperConfig(uint32_t u32ChangeRate, uint32_t u32SeedReload, uint32_t u32RefPattern, uint32_t u32Seed); +uint32_t RTC_SetClockSource(uint32_t u32ClkSrc); +void RTC_SetGPIOMode(uint32_t u32PFPin, uint32_t u32Mode, uint32_t u32DigitalCtl, uint32_t u32PullCtl, uint32_t u32OutputLevel); +void RTC_SetGPIOLevel(uint32_t u32PFPin, uint32_t u32OutputLevel); + +/**@}*/ /* end of group RTC_EXPORTED_FUNCTIONS */ + +/**@}*/ /* end of group RTC_Driver */ + +/**@}*/ /* end of group Standard_Driver */ + +#ifdef __cplusplus +} +#endif + +#endif /* __NU_RTC_H__ */ diff --git a/Ubiquitous/XiZi/board/nuvoton-m2354/third_party_driver/include/Drivers/nu_sc.h b/Ubiquitous/XiZi/board/nuvoton-m2354/third_party_driver/include/Drivers/nu_sc.h new file mode 100644 index 0000000..5a853e7 --- /dev/null +++ b/Ubiquitous/XiZi/board/nuvoton-m2354/third_party_driver/include/Drivers/nu_sc.h @@ -0,0 +1,305 @@ +/**************************************************************************//** + * @file nu_sc.h + * @version V3.00 + * @brief Smartcard(SC) driver header file + * + * @copyright SPDX-License-Identifier: Apache-2.0 + * @copyright Copyright (C) 2020 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ +#ifndef __NU_SC_H__ +#define __NU_SC_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup SC_Driver SC Driver + @{ +*/ + +/** @addtogroup SC_EXPORTED_CONSTANTS SC Exported Constants + @{ +*/ +#define SC_INTERFACE_NUM (3UL) /*!< Smartcard interface numbers \hideinitializer */ +#define SC_PIN_STATE_HIGH (1UL) /*!< Smartcard pin status high \hideinitializer */ +#define SC_PIN_STATE_LOW (0UL) /*!< Smartcard pin status low \hideinitializer */ +#define SC_PIN_STATE_IGNORE (0xFFFFFFFFUL) /*!< Ignore pin status \hideinitializer */ +#define SC_CLK_ON (1UL) /*!< Smartcard clock on \hideinitializer */ +#define SC_CLK_OFF (0UL) /*!< Smartcard clock off \hideinitializer */ + +#define SC_TMR_MODE_0 (0UL << SC_TMRCTL0_OPMODE_Pos) /*!INTEN |= (u32Mask)) + +/** + * @brief This macro disable smartcard interrupt + * + * @param[in] sc The pointer of smartcard module. + * @param[in] u32Mask Interrupt mask to be disabled. A combination of + * - \ref SC_INTEN_ACERRIEN_Msk + * - \ref SC_INTEN_RXTOIEN_Msk + * - \ref SC_INTEN_INITIEN_Msk + * - \ref SC_INTEN_CDIEN_Msk + * - \ref SC_INTEN_BGTIEN_Msk + * - \ref SC_INTEN_TMR2IEN_Msk + * - \ref SC_INTEN_TMR1IEN_Msk + * - \ref SC_INTEN_TMR0IEN_Msk + * - \ref SC_INTEN_TERRIEN_Msk + * - \ref SC_INTEN_TBEIEN_Msk + * - \ref SC_INTEN_RDAIEN_Msk + * + * @return None + * + * @details The macro is used to disable Auto-convention error interrupt, Receiver buffer time-out interrupt, Initial end interrupt, + * Card detect interrupt, Block guard time interrupt, Timer2 interrupt, Timer1 interrupt, Timer0 interrupt, + * Transfer error interrupt, Transmit buffer empty interrupt or Receive data reach trigger level interrupt. + * \hideinitializer + */ +#define SC_DISABLE_INT(sc, u32Mask) ((sc)->INTEN &= ~(u32Mask)) + +/** + * @brief This macro set VCC pin state of smartcard interface + * + * @param[in] sc The pointer of smartcard module. + * @param[in] u32State Pin state of VCC pin, valid parameters are \ref SC_PIN_STATE_HIGH and \ref SC_PIN_STATE_LOW. + * + * @return None + * + * @details User can set PWREN (SC_PINCTL[0]) and PWRINV (SC_PINCTL[11]) to decide SC_PWR pin is in high or low level. + * \hideinitializer + */ +#define SC_SET_VCC_PIN(sc, u32State) \ + do {\ + while(((sc)->PINCTL & SC_PINCTL_SYNC_Msk) == SC_PINCTL_SYNC_Msk);\ + if(u32State)\ + (sc)->PINCTL |= SC_PINCTL_PWREN_Msk;\ + else\ + (sc)->PINCTL &= ~SC_PINCTL_PWREN_Msk;\ + }while(0) + + +/** + * @brief This macro turns CLK output on or off + * + * @param[in] sc The pointer of smartcard module. + * @param[in] u32OnOff Clock on or off for selected smartcard module, valid values are \ref SC_CLK_ON and \ref SC_CLK_OFF. + * + * @return None + * + * @details User can set CLKKEEP (SC_PINCTL[6]) to decide SC_CLK pin always keeps free running or not. + * \hideinitializer + */ +#define SC_SET_CLK_PIN(sc, u32OnOff)\ + do {\ + while(((sc)->PINCTL & SC_PINCTL_SYNC_Msk) == SC_PINCTL_SYNC_Msk);\ + if(u32OnOff)\ + (sc)->PINCTL |= SC_PINCTL_CLKKEEP_Msk;\ + else\ + (sc)->PINCTL &= ~(SC_PINCTL_CLKKEEP_Msk);\ + }while(0) + +/** + * @brief This macro set I/O pin state of smartcard interface + * + * @param[in] sc The pointer of smartcard module. + * @param[in] u32State Pin state of I/O pin, valid parameters are \ref SC_PIN_STATE_HIGH and \ref SC_PIN_STATE_LOW. + * + * @return None + * + * @details User can set SCDATA (SC_PINCTL[9]) to decide SC_DATA pin to high or low. + * \hideinitializer + */ +#define SC_SET_IO_PIN(sc, u32State)\ + do {\ + while(((sc)->PINCTL & SC_PINCTL_SYNC_Msk) == SC_PINCTL_SYNC_Msk);\ + if(u32State)\ + (sc)->PINCTL |= SC_PINCTL_SCDATA_Msk;\ + else\ + (sc)->PINCTL &= ~SC_PINCTL_SCDATA_Msk;\ + }while(0) + +/** + * @brief This macro set RST pin state of smartcard interface + * + * @param[in] sc The pointer of smartcard module. + * @param[in] u32State Pin state of RST pin, valid parameters are \ref SC_PIN_STATE_HIGH and \ref SC_PIN_STATE_LOW. + * + * @return None + * + * @details User can set SCRST (SC_PINCTL[1]) to decide SC_RST pin to high or low. + * \hideinitializer + */ +#define SC_SET_RST_PIN(sc, u32State)\ + do {\ + while(((sc)->PINCTL & SC_PINCTL_SYNC_Msk) == SC_PINCTL_SYNC_Msk);\ + if(u32State)\ + (sc)->PINCTL |= SC_PINCTL_RSTEN_Msk;\ + else\ + (sc)->PINCTL &= ~SC_PINCTL_RSTEN_Msk;\ + }while(0) + +/** + * @brief This macro read one byte from smartcard module receive FIFO + * + * @param[in] sc The pointer of smartcard module. + * + * @return One byte read from receive FIFO + * + * @details By reading DAT register, the SC will return an 8-bit received data. + * \hideinitializer + */ +#define SC_READ(sc) ((char)((sc)->DAT)) + +/** + * @brief This macro write one byte to smartcard module transmit FIFO + * + * @param[in] sc The pointer of smartcard module. + * @param[in] u8Data Data to write to transmit FIFO. + * + * @return None + * + * @details By writing data to DAT register, the SC will send out an 8-bit data. + * \hideinitializer + */ +#define SC_WRITE(sc, u8Data) ((sc)->DAT = (u8Data)) + +/** + * @brief This macro set smartcard stop bit length + * + * @param[in] sc The pointer of smartcard module. + * @param[in] u32Len Stop bit length, ether 1 or 2. + * + * @return None + * + * @details Stop bit length must be 1 for T = 1 protocol and 2 for T = 0 protocol. + * \hideinitializer + */ +#define SC_SET_STOP_BIT_LEN(sc, u32Len) ((sc)->CTL = ((sc)->CTL & ~SC_CTL_NSB_Msk) | (((u32Len) == 1)? SC_CTL_NSB_Msk : 0)) + + +/*---------------------------------------------------------------------------------------------------------*/ +/* static inline functions */ +/*---------------------------------------------------------------------------------------------------------*/ +/* Declare these inline functions here to avoid MISRA C 2004 rule 8.1 error */ +__STATIC_INLINE void SC_SetTxRetry(SC_T *sc, uint32_t u32Count); +__STATIC_INLINE void SC_SetRxRetry(SC_T *sc, uint32_t u32Count); + + +/** + * @brief Enable/Disable Tx error retry, and set Tx error retry count + * + * @param[in] sc The pointer of smartcard module. + * @param[in] u32Count The number of times of Tx error retry count, between 0~8. 0 means disable Tx error retry. + * + * @return None + * + * @details This function is used to enable/disable transmitter retry function when parity error has occurred, and set error retry count. + */ +__STATIC_INLINE void SC_SetTxRetry(SC_T *sc, uint32_t u32Count) +{ + while(((sc)->CTL & SC_CTL_SYNC_Msk) == SC_CTL_SYNC_Msk) {} + + /* Retry count must set while enable bit disabled, so disable it first */ + (sc)->CTL &= ~(SC_CTL_TXRTY_Msk | SC_CTL_TXRTYEN_Msk); + + if((u32Count) != 0UL) + { + while(((sc)->CTL & SC_CTL_SYNC_Msk) == SC_CTL_SYNC_Msk) {} + (sc)->CTL |= (((u32Count) - 1UL) << SC_CTL_TXRTY_Pos) | SC_CTL_TXRTYEN_Msk; + } +} + +/** + * @brief Enable/Disable Rx error retry, and set Rx error retry count + * + * @param[in] sc The pointer of smartcard module. + * @param[in] u32Count The number of times of Rx error retry count, between 0~8. 0 means disable Rx error retry. + * + * @return None + * + * @details This function is used to enable/disable receiver retry function when parity error has occurred, and set error retry count. + */ +__STATIC_INLINE void SC_SetRxRetry(SC_T *sc, uint32_t u32Count) +{ + while(((sc)->CTL & SC_CTL_SYNC_Msk) == SC_CTL_SYNC_Msk) {} + + /* Retry count must set while enable bit disabled, so disable it first */ + (sc)->CTL &= ~(SC_CTL_RXRTY_Msk | SC_CTL_RXRTYEN_Msk); + + if((u32Count) != 0UL) + { + while(((sc)->CTL & SC_CTL_SYNC_Msk) == SC_CTL_SYNC_Msk) {} + (sc)->CTL |= (((u32Count) - 1UL) << SC_CTL_RXRTY_Pos) | SC_CTL_RXRTYEN_Msk; + } +} + + +uint32_t SC_IsCardInserted(SC_T *sc); +void SC_ClearFIFO(SC_T *sc); +void SC_Close(SC_T *sc); +void SC_Open(SC_T *sc, uint32_t u32CardDet, uint32_t u32PWR); +void SC_ResetReader(SC_T *sc); +void SC_SetBlockGuardTime(SC_T *sc, uint32_t u32BGT); +void SC_SetCharGuardTime(SC_T *sc, uint32_t u32CGT); +void SC_StopAllTimer(SC_T *sc); +void SC_StartTimer(SC_T *sc, uint32_t u32TimerNum, uint32_t u32Mode, uint32_t u32ETUCount); +void SC_StopTimer(SC_T *sc, uint32_t u32TimerNum); +uint32_t SC_GetInterfaceClock(SC_T *sc); + +/**@}*/ /* end of group SC_EXPORTED_FUNCTIONS */ + +/**@}*/ /* end of group SC_Driver */ + +/**@}*/ /* end of group Standard_Driver */ + +#ifdef __cplusplus +} +#endif + +#endif /* __NU_SC_H__ */ diff --git a/Ubiquitous/XiZi/board/nuvoton-m2354/third_party_driver/include/Drivers/nu_scu.h b/Ubiquitous/XiZi/board/nuvoton-m2354/third_party_driver/include/Drivers/nu_scu.h new file mode 100644 index 0000000..5079c6d --- /dev/null +++ b/Ubiquitous/XiZi/board/nuvoton-m2354/third_party_driver/include/Drivers/nu_scu.h @@ -0,0 +1,358 @@ +/**************************************************************************//** + * @file nu_scu.h + * @version V3.00 + * @brief Secure Configuration Unit Driver Header + * + * @copyright SPDX-License-Identifier: Apache-2.0 + * @copyright Copyright (C) 2020 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ +#ifndef __NU_SCU_H__ +#define __NU_SCU_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup SCU_Driver SCU Driver + @{ +*/ + +/** @addtogroup SCU_EXPORTED_CONSTANTS SCU Exported Constants + @{ +*/ + + + + +/** + * @details Non-secure Attribution Definition. + */ +typedef enum NSATTR +{ + /****** PNNSET0 **********************************************************************************/ + USBH_Attr = 9, + SDH0_Attr = 13, + EBI_Attr = 16, + PDMA1_Attr = 24, + + /****** PNNSET1 **********************************************************************************/ + CRC_Attr = 32 + 17, + CRPT_Attr = 32 + 18, + + /****** PNNSET2 **********************************************************************************/ + EWDT_Attr = 64 + 2, + EADC_Attr = 64 + 3, + ACMP01_Attr = 64 + 5, + DAC_Attr = 64 + 7, + I2S0_Attr = 64 + 8, + OTG_Attr = 64 + 13, + TMR23_Attr = 64 + 17, + TMR45_Attr = 64 + 18, + EPWM0_Attr = 64 + 24, + EPWM1_Attr = 64 + 25, + BPWM0_Attr = 64 + 26, + BPWM1_Attr = 64 + 27, + /****** PNNSET3 **********************************************************************************/ + QSPI0_Attr = 96 + 0, + SPI0_Attr = 96 + 1, + SPI1_Attr = 96 + 2, + SPI2_Attr = 96 + 3, + SPI3_Attr = 96 + 4, + UART0_Attr = 96 + 16, + UART1_Attr = 96 + 17, + UART2_Attr = 96 + 18, + UART3_Attr = 96 + 19, + UART4_Attr = 96 + 20, + UART5_Attr = 96 + 21, + /****** PNNSET4 **********************************************************************************/ + I2C0_Attr = 128 + 0, + I2C1_Attr = 128 + 1, + I2C2_Attr = 128 + 2, + SC0_Attr = 128 + 16, + SC1_Attr = 128 + 17, + SC2_Attr = 128 + 18, + + + /****** PNNSET5 **********************************************************************************/ + CAN0_Attr = 160 + 0, + QEI0_Attr = 160 + 16, + QEI1_Attr = 160 + 17, + ECAP0_Attr = 160 + 20, + ECAP1_Attr = 160 + 21, + TRNG_Attr = 160 + 25, + LCD_Attr = 160 + 27, + + /****** PNNSET6 **********************************************************************************/ + USBD_Attr = 192 + 0, + USCI0_Attr = 192 + 16, + USCI1_Attr = 192 + 17 + + +} NSATTR_T; + + +/**@}*/ /* end of group SCU_EXPORTED_CONSTANTS */ + + +/** @addtogroup SCU_EXPORTED_FUNCTIONS SCU Exported Functions + @{ +*/ + +/** + * @brief Set peripheral non-secure attribution + * + * @param[in] nsattr The secure/non-secure attribution of specified module. + The possible value could be refer to \ref NSATTR. + * + * @return None + * + * @details This macro is used to set a peripheral to be non-secure peripheral. + * + */ +#define SCU_SET_PNSSET(nsattr) { SCU->PNSSET[(nsattr)/32] |= (1 << ((nsattr) & 0x1ful)); } + +/** + * @brief Get peripheral secure/non-secure attribution + * + * @param[in] nsattr The secure/non-secure attribution of specified module. + The possible value could be refer to \ref NSATTR. + * + * @return The secure/non-secure attribution of specified peripheral. + * @retval 0 The peripheral is secure + * @retval 1 The peripheral is non-secure + * + * @details This macro gets the peripheral secure/non-secure attribution. + */ +#define SCU_GET_PNSSET(nsattr) ((SCU->PNSSET[(nsattr)/32] >> ((nsattr) & 0x1ful)) & 1ul) + + +/** + * @brief Set secure/non-secure attribution of specified GPIO pin + * + * @param[in] port GPIO Port. It could be PA, PB, PC, PD, PE, PF, PG and PH. + * @param[in] bitmask Bit mask of each bit. 0 is secure. 1 is non-secure. + * + * @return None + * + * @details This macro sets GPIO pin secure/non-secure attribution. + */ +#define SCU_SET_IONSSET(port, mask) (SCU->IONSSET[((uint32_t)(port)-(GPIOA_BASE))/0x40] = (mask)) + + +/** + * @brief Get secure/non-secure attribution of specified GPIO port + * + * @param[in] port GPIO Port. It could be PA, PB, PC, PD, PE, PF, PG and PH. + * + * @return The secure/non-secure attribution of the port. + * @retval 0 The relative bit of specified IO port is secure + * @retval 1 The relative bit of specified IO port is non-secure + * + * @details This macro gets IO secure/non-secure attribution of specified IO port. + */ +#define SCU_GET_IONSSET(port) (SCU->IONSSET[((uint32_t)(port) - (GPIOA_BASE))/0x40]) + + +/** + * @brief Enable sercure violation interrupts + * + * @param[in] mask The mask of each secure violation interrupt source + * - \ref SCU_SVIOIEN_APB0IEN_Msk + * - \ref SCU_SVIOIEN_APB1IEN_Msk + * - \ref SCU_SVIOIEN_GPIOIEN_Msk + * - \ref SCU_SVIOIEN_EBIIEN_Msk + * - \ref SCU_SVIOIEN_USBHIEN_Msk + * - \ref SCU_SVIOIEN_CRCIEN_Msk + * - \ref SCU_SVIOIEN_SDH0IEN_Msk + * - \ref SCU_SVIOIEN_PDMA0IEN_Msk + * - \ref SCU_SVIOIEN_PDMA1IEN_Msk + * - \ref SCU_SVIOIEN_SRAM0IEN_Msk + * - \ref SCU_SVIOIEN_SRAM1IEN_Msk + * - \ref SCU_SVIOIEN_FMCIEN_Msk + * - \ref SCU_SVIOIEN_FLASHIEN_Msk + * - \ref SCU_SVIOIEN_SCUIEN_Msk + * - \ref SCU_SVIOIEN_SYSIEN_Msk + * - \ref SCU_SVIOIEN_CRPTIEN_Msk + * + * @return None + * + * @details This macro is used to enable secure violation interrupt of SCU. + * The secure violation interrupt could be used to detect attack of secure elements. + */ +#define SCU_ENABLE_INT(mask) (SCU->SVIOIEN |= (mask)) + + +/** + * @brief Disable sercure violation interrupts + * + * @param[in] mask The mask of each secure violation interrupt source + * - \ref SCU_SVIOIEN_APB0IEN_Msk + * - \ref SCU_SVIOIEN_APB1IEN_Msk + * - \ref SCU_SVIOIEN_GPIOIEN_Msk + * - \ref SCU_SVIOIEN_EBIIEN_Msk + * - \ref SCU_SVIOIEN_USBHIEN_Msk + * - \ref SCU_SVIOIEN_CRCIEN_Msk + * - \ref SCU_SVIOIEN_SDH0IEN_Msk + * - \ref SCU_SVIOIEN_PDMA0IEN_Msk + * - \ref SCU_SVIOIEN_PDMA1IEN_Msk + * - \ref SCU_SVIOIEN_SRAM0IEN_Msk + * - \ref SCU_SVIOIEN_SRAM1IEN_Msk + * - \ref SCU_SVIOIEN_FMCIEN_Msk + * - \ref SCU_SVIOIEN_FLASHIEN_Msk + * - \ref SCU_SVIOIEN_SCUIEN_Msk + * - \ref SCU_SVIOIEN_SYSIEN_Msk + * - \ref SCU_SVIOIEN_CRPTIEN_Msk + * + * @return None + * + * @details This macro is used to disable secure violation interrupt of SCU. + * + */ +#define SCU_DISABLE_INT(mask) (SCU->SVIOIEN &= (~(mask))) + + +/** + * @brief Get secure violation interrupt status + * + * @param mask The interrupt flag mask bit + * + * @return The value of SCU_SVINTSTS register + * + * @details Return interrupt flag of SCU_SVINTSTS register. + * + */ +#define SCU_GET_INT_FLAG(mask) (SCU->SVINTSTS&(mask)) + +/** + * @brief Clear secure violation interrupt flag + * + * @param[in] flag The combination of the specified interrupt flags. + * Each bit corresponds to a interrupt source. + * This parameter decides which interrupt flags will be cleared. + * - \ref SCU_SVINTSTS_APB0IF_Msk + * - \ref SCU_SVINTSTS_APB1IF_Msk + * - \ref SCU_SVINTSTS_GPIOIF_Msk + * - \ref SCU_SVINTSTS_EBIIF_Msk + * - \ref SCU_SVINTSTS_USBHIF_Msk + * - \ref SCU_SVINTSTS_CRCIF_Msk + * - \ref SCU_SVINTSTS_SDH0IF_Msk + * - \ref SCU_SVINTSTS_PDMA0IF_Msk + * - \ref SCU_SVINTSTS_PDMA1IF_Msk + * - \ref SCU_SVINTSTS_SRAM0IF_Msk + * - \ref SCU_SVINTSTS_SRAM1IF_Msk + * - \ref SCU_SVINTSTS_FMCIF_Msk + * - \ref SCU_SVINTSTS_FLASHIF_Msk + * - \ref SCU_SVINTSTS_SCUIF_Msk + * - \ref SCU_SVINTSTS_SYSIF_Msk + * - \ref SCU_SVINTSTS_CRPTIF_Msk + * + * @return None + * + * @details Clear SCU related interrupt flags specified by flag parameter. + * + */ +#define SCU_CLR_INT_FLAG(flag) (SCU->SVINTSTS = (flag)) + + + +/** + * @brief Control the behavior of non-secure monitor when CPU is in idle state. + * + * @param[in] opt Option for behavior control of non-secure monitor when CPU in idle. + * - true The counter keeps counting when CPU is in idle. + - false The counter will stop when CPU is in idle. + * + * @return None + * + * @details To control non-secure monitor counter when CPU is in idle. + * + */ +#define SCU_NSM_IDLE_ON(opt) ((opt)?(SCU->NSMCTL |= SCU_NSMCTL_IDLEON_Msk):(SCU->NSMCTL &= ~SCU_NSMCTL_IDLEON_Msk)) + +/** + * @brief Control the behavior of non-secure monitor when CPU is in debug state. + * + * @param[in] opt Option for behavior control of non-secure monitor when CPU in debug. + * - true The counter keeps counting when CPU is in debug. + - false The counter will stop when CPU is in debug. + * + * @return None + * + * @details To control non-secure monitor counter when CPU is in debug. + * + */ +#define SCU_NSM_DBG_ON(opt) ((opt)?(SCU->NSMCTL |= SCU_NSMCTL_DBGON_Msk):(SCU->NSMCTL &= ~SCU_NSMCTL_DBGON_Msk)) + + +/* Declare these inline functions here to avoid MISRA C 2004 rule 8.1 error */ +__STATIC_INLINE void SCU_NSMConfig(uint32_t u32Ticks, uint32_t u32Prescale); +__STATIC_INLINE void SCU_TimerConfig(uint32_t u32Ticks, uint32_t u32Prescale); + + +/** + * @brief Config non-secure monitor to detect timeout in non-secure state. + * + * @param[in] u32Ticks A specified period for timeout in non-secure state + * @param[in] u32Prescale A pre-scale divider to non-secure monitor clock + + * + * @return None + * + * @details This function is used to configure non-secure monitor. If the CPU state stay in non-secure state for + * a specified period. The non-secure monitor will timeout and assert an interrupt. Otherwise, the + * non-secure monitor will auto clear whenever returning to secure state. This could be used to avoid + * CPU state in non-secure state too long time for security purpose. User must enable SCU_IRQn if interrupt + * is necessary. + * + */ +__STATIC_INLINE void SCU_NSMConfig(uint32_t u32Ticks, uint32_t u32Prescale) +{ + + SCU->NSMLOAD = u32Ticks; + SCU->NSMVAL = 0ul; + SCU->NSMCTL = SCU_NSMCTL_AUTORLD_Msk | SCU_NSMCTL_NSMIEN_Msk | (u32Prescale & 0xfful); +} + + +/** + * @brief Config non-secure monitor to be a timer. + * + * @param[in] u32Ticks A specified period for timer interrupt. + * @param[in] u32Prescale A pre-scale divider to timer clock source. + + * + * @return None + * + * @details This function is used to configure non-secure monitor as a timer. In other words, the timer counter + * keeps counting even CPU is in secure state. + * + */ +__STATIC_INLINE void SCU_TimerConfig(uint32_t u32Ticks, uint32_t u32Prescale) +{ + + SCU->NSMLOAD = u32Ticks; + SCU->NSMVAL = 0ul; + SCU->NSMCTL = SCU_NSMCTL_AUTORLD_Msk | SCU_NSMCTL_NSMIEN_Msk | SCU_NSMCTL_TMRMOD_Msk | (u32Prescale & 0xfful); +} + + + + +/**@}*/ /* end of group SCU_EXPORTED_FUNCTIONS */ + +/**@}*/ /* end of group SCU_Driver */ + +/**@}*/ /* end of group Standard_Driver */ + +#ifdef __cplusplus +} +#endif + +#endif /* __NU_SCU_H__ */ + diff --git a/Ubiquitous/XiZi/board/nuvoton-m2354/third_party_driver/include/Drivers/nu_scuart.h b/Ubiquitous/XiZi/board/nuvoton-m2354/third_party_driver/include/Drivers/nu_scuart.h new file mode 100644 index 0000000..d9a3756 --- /dev/null +++ b/Ubiquitous/XiZi/board/nuvoton-m2354/third_party_driver/include/Drivers/nu_scuart.h @@ -0,0 +1,353 @@ +/**************************************************************************//** + * @file nu_scuart.h + * @version V3.00 + * @brief Smartcard UART mode (SCUART) driver header file + * + * @copyright SPDX-License-Identifier: Apache-2.0 + * @copyright Copyright (C) 2020 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ +#ifndef __NU_SCUART_H__ +#define __NU_SCUART_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup SCUART_Driver SCUART Driver + @{ +*/ + +/** @addtogroup SCUART_EXPORTED_CONSTANTS SCUART Exported Constants + @{ +*/ +#define SCUART_CHAR_LEN_5 (0x3UL << SC_UARTCTL_WLS_Pos) /*!< Set SCUART word length to 5 bits \hideinitializer */ +#define SCUART_CHAR_LEN_6 (0x2UL << SC_UARTCTL_WLS_Pos) /*!< Set SCUART word length to 6 bits \hideinitializer */ +#define SCUART_CHAR_LEN_7 (0x1UL << SC_UARTCTL_WLS_Pos) /*!< Set SCUART word length to 7 bits \hideinitializer */ +#define SCUART_CHAR_LEN_8 (0UL) /*!< Set SCUART word length to 8 bits \hideinitializer */ + +#define SCUART_PARITY_NONE (SC_UARTCTL_PBOFF_Msk) /*!< Set SCUART transfer with no parity \hideinitializer */ +#define SCUART_PARITY_ODD (SC_UARTCTL_OPE_Msk) /*!< Set SCUART transfer with odd parity \hideinitializer */ +#define SCUART_PARITY_EVEN (0UL) /*!< Set SCUART transfer with even parity \hideinitializer */ + +#define SCUART_STOP_BIT_1 (SC_CTL_NSB_Msk) /*!< Set SCUART transfer with one stop bit \hideinitializer */ +#define SCUART_STOP_BIT_2 (0UL) /*!< Set SCUART transfer with two stop bits \hideinitializer */ + +/**@}*/ /* end of group SCUART_EXPORTED_CONSTANTS */ + + +/** @addtogroup SCUART_EXPORTED_FUNCTIONS SCUART Exported Functions + @{ +*/ + +/* TX Macros */ +/** + * @brief Write Data to Tx data register + * + * @param[in] sc The pointer of smartcard module. + * @param[in] u8Data Data byte to transmit. + * + * @return None + * + * @details By writing data to DAT register, the SC will send out an 8-bit data. + * \hideinitializer + */ +#define SCUART_WRITE(sc, u8Data) ((sc)->DAT = (u8Data)) + +/** + * @brief Get Tx FIFO empty flag status from register + * + * @param[in] sc The pointer of smartcard module. + * + * @return Transmit FIFO empty status + * @retval 0 Transmit FIFO is not empty + * @retval SC_STATUS_TXEMPTY_Msk Transmit FIFO is empty + * + * @details When the last byte of Tx buffer has been transferred to Transmitter Shift Register, hardware sets TXEMPTY (SC_STATUS[9]) high. + * It will be cleared when writing data into DAT (SC_DAT[7:0]). + * \hideinitializer + */ +#define SCUART_GET_TX_EMPTY(sc) ((sc)->STATUS & SC_STATUS_TXEMPTY_Msk) + +/** + * @brief Get Tx FIFO full flag status from register + * + * @param[in] sc The pointer of smartcard module. + * + * @return Transmit FIFO full status + * @retval 0 Transmit FIFO is not full + * @retval SC_STATUS_TXFULL_Msk Transmit FIFO is full + * + * @details TXFULL (SC_STATUS[10]) is set when Tx buffer counts equals to 4, otherwise is cleared by hardware. + * \hideinitializer + */ +#define SCUART_GET_TX_FULL(sc) ((sc)->STATUS & SC_STATUS_TXFULL_Msk) + +/** + * @brief Wait specified smartcard port transmission complete + * + * @param[in] sc The pointer of smartcard module. + * + * @return None + * + * @details TXACT (SC_STATUS[31]) is cleared automatically when Tx transfer is finished or the last byte transmission has completed. + * + * @note This macro blocks until transmit complete. + * \hideinitializer + */ +#define SCUART_WAIT_TX_EMPTY(sc) while(((sc)->STATUS & SC_STATUS_TXACT_Msk) == SC_STATUS_TXACT_Msk) + +/** + * @brief Check specified smartcard port transmit FIFO is full or not + * + * @param[in] sc The pointer of smartcard module. + * + * @return Transmit FIFO full status + * @retval 0 Transmit FIFO is not full + * @retval 1 Transmit FIFO is full + * + * @details TXFULL (SC_STATUS[10]) indicates Tx buffer full or not. + * This bit is set when Tx buffer counts equals to 4, otherwise is cleared by hardware. + * \hideinitializer + */ +#define SCUART_IS_TX_FULL(sc) (((sc)->STATUS & SC_STATUS_TXFULL_Msk)? 1 : 0) + +/** + * @brief Check specified smartcard port transmission is over + * + * @param[in] sc The pointer of smartcard module. + * + * @return Transmit complete status + * @retval 0 Transmit is not complete + * @retval 1 Transmit complete + * + * @details TXACT (SC_STATUS[31]) indicates Tx Transmit is complete or not. + * \hideinitializer + */ +#define SCUART_IS_TX_EMPTY(sc) (((sc)->STATUS & SC_STATUS_TXACT_Msk)? 0 : 1) + +/** + * @brief Check specified smartcard port transmit FIFO empty status + * + * @param[in] sc The pointer of smartcard module. + * + * @return Transmit FIFO empty status + * @retval 0 Transmit FIFO is not empty + * @retval 1 Transmit FIFO is empty + * + * @details TXEMPTY (SC_STATUS[9]) is set by hardware when the last byte of Tx buffer has been transferred to Transmitter Shift Register. + * \hideinitializer + */ +#define SCUART_IS_TX_FIFO_EMPTY(sc) (((sc)->STATUS & SC_STATUS_TXEMPTY_Msk)? 1 : 0) + +/** + * @brief Check specified Smartcard port Transmission Status + * + * @param[in] sc The pointer of smartcard module. + * + * @retval 0 Transmit is completed + * @retval 1 Transmit is active + * + * @details TXACT (SC_STATUS[31]) is set by hardware when Tx transfer is in active and the STOP bit of the last byte has been transmitted. + * \hideinitializer + */ +#define SCUART_IS_TX_ACTIVE(sc) (((sc)->STATUS & SC_STATUS_TXACT_Msk)? 1 : 0) + + +/* RX Macros */ +/** + * @brief Read Rx data register + * + * @param[in] sc The pointer of smartcard module. + * + * @return The oldest data byte in RX FIFO + * + * @details By reading DAT register, the SC will return an 8-bit received data. + * \hideinitializer + */ +#define SCUART_READ(sc) ((sc)->DAT) + +/** + * @brief Get Rx FIFO empty flag status from register + * + * @param[in] sc The pointer of smartcard module. + * + * @return Receive FIFO empty status + * @retval 0 Receive FIFO is not empty + * @retval SC_STATUS_RXEMPTY_Msk Receive FIFO is empty + * + * @details When the last byte of Rx buffer has been read by CPU, hardware sets RXEMPTY (SC_STATUS[1]) high. + * It will be cleared when SC receives any new data. + * \hideinitializer + */ +#define SCUART_GET_RX_EMPTY(sc) ((sc)->STATUS & SC_STATUS_RXEMPTY_Msk) + +/** + * @brief Get Rx FIFO full flag status from register + * + * @param[in] sc The pointer of smartcard module. + * + * @return Receive FIFO full status + * @retval 0 Receive FIFO is not full + * @retval SC_STATUS_TXFULL_Msk Receive FIFO is full + * + * @details RXFULL (SC_STATUS[2]) is set when Rx buffer counts equals to 4, otherwise it is cleared by hardware. + * \hideinitializer + */ +#define SCUART_GET_RX_FULL(sc) ((sc)->STATUS & SC_STATUS_RXFULL_Msk) + +/** + * @brief Check if receive data number in FIFO reach FIFO trigger level or not + * + * @param[in] sc The pointer of smartcard module. + * + * @return Receive FIFO data status + * @retval 0 The number of bytes in receive FIFO is less than trigger level + * @retval 1 The number of bytes in receive FIFO equals or larger than trigger level + * + * @details RDAIF (SC_INTSTS[0]) is used for received data reaching trigger level RXTRGLV (SC_CTL[7:6]) interrupt status flag. + * + * @note If receive trigger level is \b not 1 byte, this macro return 0 does not necessary indicates there is no data in FIFO. + * \hideinitializer + */ +#define SCUART_IS_RX_READY(sc) (((sc)->INTSTS & SC_INTSTS_RDAIF_Msk)? 1 : 0) + +/** + * @brief Check specified smartcard port receive FIFO is full or not + * + * @param[in] sc The pointer of smartcard module. + * + * @return Receive FIFO full status + * @retval 0 Receive FIFO is not full + * @retval 1 Receive FIFO is full + * + * @details RXFULLF( SC_STATUS[2]) is set when Rx buffer counts equals to 4, otherwise it is cleared by hardware. + * \hideinitializer + */ +#define SCUART_IS_RX_FULL(sc) (((sc)->STATUS & SC_STATUS_RXFULL_Msk)? 1 : 0) + + +/* Interrupt Macros */ +/** + * @brief Enable specified interrupts + * + * @param[in] sc The pointer of smartcard module. + * @param[in] u32Mask Interrupt masks to enable, a combination of following bits, + * - \ref SC_INTEN_RXTOIEN_Msk + * - \ref SC_INTEN_TERRIEN_Msk + * - \ref SC_INTEN_TBEIEN_Msk + * - \ref SC_INTEN_RDAIEN_Msk + * + * @return None + * + * @details The macro is used to enable receiver buffer time-out interrupt, transfer error interrupt, + * transmit buffer empty interrupt or receive data reach trigger level interrupt. + * \hideinitializer + */ +#define SCUART_ENABLE_INT(sc, u32Mask) ((sc)->INTEN |= (u32Mask)) + +/** + * @brief Disable specified interrupts + * + * @param[in] sc The pointer of smartcard module. + * @param[in] u32Mask Interrupt masks to disable, a combination of following bits, + * - \ref SC_INTEN_RXTOIEN_Msk + * - \ref SC_INTEN_TERRIEN_Msk + * - \ref SC_INTEN_TBEIEN_Msk + * - \ref SC_INTEN_RDAIEN_Msk + * + * @return None + * + * @details The macro is used to disable receiver buffer time-out interrupt, transfer error interrupt, + * transmit buffer empty interrupt or receive data reach trigger level interrupt. + * \hideinitializer + */ +#define SCUART_DISABLE_INT(sc, u32Mask) ((sc)->INTEN &= ~(u32Mask)) + +/** + * @brief Get specified interrupt flag/status + * + * @param[in] sc The pointer of smartcard module. + * @param[in] u32Type Interrupt flag/status to check, could be one of following value + * - \ref SC_INTSTS_RXTOIF_Msk + * - \ref SC_INTSTS_TERRIF_Msk + * - \ref SC_INTSTS_TBEIF_Msk + * - \ref SC_INTSTS_RDAIF_Msk + * + * @return The status of specified interrupt + * @retval 0 Specified interrupt does not happened + * @retval 1 Specified interrupt happened + * + * @details The macro is used to get receiver buffer time-out interrupt status, transfer error interrupt status, + * transmit buffer empty interrupt status or receive data reach interrupt status. + * \hideinitializer + */ +#define SCUART_GET_INT_FLAG(sc, u32Type) (((sc)->INTSTS & (u32Type))? 1 : 0) + +/** + * @brief Clear specified interrupt flag/status + * + * @param[in] sc The pointer of smartcard module. + * @param[in] u32Type Interrupt flag/status to clear, only \ref SC_INTSTS_TERRIF_Msk valid for this macro. + * + * @return None + * + * @details The macro is used to clear transfer error interrupt flag. + * \hideinitializer + */ +#define SCUART_CLR_INT_FLAG(sc, u32Type) ((sc)->INTSTS = (u32Type)) + +/** + * @brief Get receive error flag/status + * + * @param[in] sc The pointer of smartcard module. + * + * @return Current receive error status, could one of following errors: + * @retval SC_STATUS_PEF_Msk Parity error + * @retval SC_STATUS_FEF_Msk Frame error + * @retval SC_STATUS_BEF_Msk Break error + * + * @details The macro is used to get receiver parity error status, frame error status or break error status. + * \hideinitializer + */ +#define SCUART_GET_ERR_FLAG(sc) ((sc)->STATUS & (SC_STATUS_PEF_Msk | SC_STATUS_FEF_Msk | SC_STATUS_BEF_Msk)) + +/** + * @brief Clear specified receive error flag/status + * + * @param[in] sc The pointer of smartcard module. + * @param[in] u32Mask Receive error flag/status to clear, combination following values + * - \ref SC_STATUS_PEF_Msk + * - \ref SC_STATUS_FEF_Msk + * - \ref SC_STATUS_BEF_Msk + * + * @return None + * + * @details The macro is used to clear receiver parity error flag, frame error flag or break error flag. + * \hideinitializer + */ +#define SCUART_CLR_ERR_FLAG(sc, u32Mask) ((sc)->STATUS = (u32Mask)) + +void SCUART_Close(SC_T* sc); +uint32_t SCUART_Open(SC_T* sc, uint32_t u32Baudrate); +uint32_t SCUART_Read(SC_T* sc, uint8_t pu8RxBuf[], uint32_t u32ReadBytes); +uint32_t SCUART_SetLineConfig(SC_T* sc, uint32_t u32Baudrate, uint32_t u32DataWidth, uint32_t u32Parity, uint32_t u32StopBits); +void SCUART_SetTimeoutCnt(SC_T* sc, uint32_t u32TOC); +void SCUART_Write(SC_T* sc, uint8_t pu8TxBuf[], uint32_t u32WriteBytes); + +/**@}*/ /* end of group SCUART_EXPORTED_FUNCTIONS */ + +/**@}*/ /* end of group SCUART_Driver */ + +/**@}*/ /* end of group Standard_Driver */ + +#ifdef __cplusplus +} +#endif + +#endif /* __NU_SCUART_H__ */ diff --git a/Ubiquitous/XiZi/board/nuvoton-m2354/third_party_driver/include/Drivers/nu_sdh.h b/Ubiquitous/XiZi/board/nuvoton-m2354/third_party_driver/include/Drivers/nu_sdh.h new file mode 100644 index 0000000..3304e1a --- /dev/null +++ b/Ubiquitous/XiZi/board/nuvoton-m2354/third_party_driver/include/Drivers/nu_sdh.h @@ -0,0 +1,203 @@ +/**************************************************************************//** + * @file nu_sdh.h + * @version V1.00 + * @brief M2354 SDH driver header file + * + * @copyright SPDX-License-Identifier: Apache-2.0 + * @copyright Copyright (C) 2020 Nuvoton Technology Corp. All rights reserved. +*****************************************************************************/ +#ifndef __NU_SDH_H__ +#define __NU_SDH_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + +#include + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup SDH_Driver SDH Driver + @{ +*/ + + +/** @addtogroup SDH_EXPORTED_CONSTANTS SDH Exported Constants + @{ +*/ + +#define SDH_ERR_ID 0xFFFF0100UL /*!< SDH error ID \hideinitializer */ + +#define SDH_TIMEOUT (SDH_ERR_ID|0x01UL) /*!< Timeout \hideinitializer */ +#define SDH_NO_MEMORY (SDH_ERR_ID|0x02UL) /*!< OOM \hideinitializer */ + +/* -- function return value */ +#define Successful 0U /*!< Success \hideinitializer */ +#define Fail 1U /*!< Failed \hideinitializer */ + +/* --- define type of SD card or MMC */ +#define SDH_TYPE_UNKNOWN 0UL /*!< Unknown card type \hideinitializer */ +#define SDH_TYPE_SD_HIGH 1UL /*!< SDHC card \hideinitializer */ +#define SDH_TYPE_SD_LOW 2UL /*!< SD card \hideinitializer */ +#define SDH_TYPE_MMC 3UL /*!< MMC card \hideinitializer */ +#define SDH_TYPE_EMMC 4UL /*!< eMMC card \hideinitializer */ + +/* SD error */ +#define SDH_NO_SD_CARD (SDH_ERR_ID|0x10UL) /*!< Card removed \hideinitializer */ +#define SDH_ERR_DEVICE (SDH_ERR_ID|0x11UL) /*!< Device error \hideinitializer */ +#define SDH_INIT_TIMEOUT (SDH_ERR_ID|0x12UL) /*!< Card init timeout \hideinitializer */ +#define SDH_SELECT_ERROR (SDH_ERR_ID|0x13UL) /*!< Card select error \hideinitializer */ +#define SDH_WRITE_PROTECT (SDH_ERR_ID|0x14UL) /*!< Card write protect \hideinitializer */ +#define SDH_INIT_ERROR (SDH_ERR_ID|0x15UL) /*!< Card init error \hideinitializer */ +#define SDH_CRC7_ERROR (SDH_ERR_ID|0x16UL) /*!< CRC 7 error \hideinitializer */ +#define SDH_CRC16_ERROR (SDH_ERR_ID|0x17UL) /*!< CRC 16 error \hideinitializer */ +#define SDH_CRC_ERROR (SDH_ERR_ID|0x18UL) /*!< CRC error \hideinitializer */ +#define SDH_CMD8_ERROR (SDH_ERR_ID|0x19UL) /*!< Command 8 error \hideinitializer */ + +#define MMC_FREQ 20000UL /*!< output 20MHz to MMC \hideinitializer */ +#define SD_FREQ 25000UL /*!< output 25MHz to SD \hideinitializer */ +#define SDHC_FREQ 50000UL /*!< output 50MHz to SDH \hideinitializer */ + +#define CardDetect_From_GPIO (1UL << 8) /*!< Card detection pin is GPIO \hideinitializer */ +#define CardDetect_From_DAT3 (1UL << 9) /*!< Card detection pin is DAT3 \hideinitializer */ + +/**@}*/ /* end of group SDH_EXPORTED_CONSTANTS */ + +/** @addtogroup SDH_EXPORTED_TYPEDEF SDH Exported Type Defines + @{ +*/ +#if defined ( __ARMCC_VERSION ) +#pragma pack(push) +#pragma pack(1) +#endif +typedef struct SDH_info_t +{ + unsigned int CardType; /*!< SDHC, SD, or MMC */ + unsigned int RCA; /*!< Relative card address */ + unsigned char IsCardInsert; /*!< Card insert state */ + unsigned int totalSectorN; /*!< Total sector number */ + unsigned int diskSize; /*!< Disk size in K bytes */ + int sectorSize; /*!< Sector size in bytes */ +} SDH_INFO_T; /*!< Structure holds SD card info */ +#if defined ( __ARMCC_VERSION ) +#pragma pack(pop) +#endif +/**@}*/ /* end of group SDH_EXPORTED_TYPEDEF */ + +/** @cond HIDDEN_SYMBOLS */ +extern SDH_INFO_T SD0; +extern uint8_t volatile g_u8SDDataReadyFlag; +extern uint8_t g_u8R3Flag; + +/** @endcond HIDDEN_SYMBOLS */ + +/** @addtogroup SDH_EXPORTED_FUNCTIONS SDH Exported Functions + @{ +*/ + +/** + * @brief Enable specified interrupt. + * + * @param[in] sdh The pointer of the specified SDH module. + * @param[in] u32IntMask Interrupt type mask: + * \ref SDH_INTEN_BLKDIEN_Msk / \ref SDH_INTEN_CRCIEN_Msk / \ref SDH_INTEN_CDIEN_Msk / + * \ref SDH_INTEN_CDSRC_Msk / \ref SDH_INTEN_RTOIEN_Msk / \ref SDH_INTEN_DITOIEN_Msk / + * \ref SDH_INTEN_WKIEN_Msk + * + * @return None. + * \hideinitializer + */ +#define SDH_ENABLE_INT(sdh, u32IntMask) ((sdh)->INTEN |= (u32IntMask)) + +/** + * @brief Disable specified interrupt. + * + * @param[in] sdh The pointer of the specified SDH module. + * @param[in] u32IntMask Interrupt type mask: + * \ref SDH_INTEN_BLKDIEN_Msk / \ref SDH_INTEN_CRCIEN_Msk / \ref SDH_INTEN_CDIEN_Msk / + * \ref SDH_INTEN_RTOIEN_Msk / \ref SDH_INTEN_DITOIEN_Msk / \ref SDH_INTEN_WKIEN_Msk / \ref SDH_INTEN_CDSRC_Msk / + * + * @return None. + * \hideinitializer + */ +#define SDH_DISABLE_INT(sdh, u32IntMask) ((sdh)->INTEN &= ~(u32IntMask)) + +/** + * @brief Get specified interrupt flag/status. + * + * @param[in] sdh The pointer of the specified SDH module. + * @param[in] u32IntMask Interrupt type mask: + * \ref SDH_INTSTS_BLKDIF_Msk / \ref SDH_INTSTS_CRCIF_Msk / \ref SDH_INTSTS_CRC7_Msk / + * \ref SDH_INTSTS_CRC16_Msk / \ref SDH_INTSTS_CRCSTS_Msk / \ref SDH_INTSTS_DAT0STS_Msk / + * \ref SDH_INTSTS_CDIF_Msk / \ref SDH_INTSTS_RTOIF_Msk / + * \ref SDH_INTSTS_DITOIF_Msk / \ref SDH_INTSTS_CDSTS_Msk / + * \ref SDH_INTSTS_DAT1STS_Msk + * + * + * @return 0 = The specified interrupt is not happened. + * 1 = The specified interrupt is happened. + * \hideinitializer + */ +#define SDH_GET_INT_FLAG(sdh, u32IntMask) (((sdh)->INTSTS & (u32IntMask))?1:0) + + +/** + * @brief Clear specified interrupt flag/status. + * + * @param[in] sdh The pointer of the specified SDH module. + * @param[in] u32IntMask Interrupt type mask: + * \ref SDH_INTSTS_BLKDIF_Msk / \ref SDH_INTSTS_CRCIF_Msk / \ref SDH_INTSTS_CDIF_Msk / + * \ref SDH_INTSTS_RTOIF_Msk / \ref SDH_INTSTS_DITOIF_Msk + * + * + * @return None. + * \hideinitializer + */ +#define SDH_CLR_INT_FLAG(sdh, u32IntMask) ((sdh)->INTSTS = (u32IntMask)) + + +/** + * @brief Check SD Card inserted or removed. + * + * @param[in] sdh The pointer of the specified SDH module. + * + * @return 1: Card inserted. + * 0: Card removed. + * \hideinitializer + */ +#define SDH_IS_CARD_PRESENT(sdh) ((((sdh) == SDH0)||((sdh) == SDH0_NS))? SD0.IsCardInsert : 0) + +/** + * @brief Get SD Card capacity. + * + * @param[in] sdh The pointer of the specified SDH module. + * + * @return SD Card capacity. (unit: KByte) + * \hideinitializer + */ +#define SDH_GET_CARD_CAPACITY(sdh) ((((sdh) == SDH0)||((sdh) == SDH0_NS))? SD0.diskSize : 0) + + +void SDH_Open(SDH_T *sdh, uint32_t u32CardDetSrc); +uint32_t SDH_Probe(SDH_T *sdh); +uint32_t SDH_Read(SDH_T *sdh, uint8_t *pu8BufAddr, uint32_t u32StartSec, uint32_t u32SecCount); +uint32_t SDH_Write(SDH_T *sdh, uint8_t *pu8BufAddr, uint32_t u32StartSec, uint32_t u32SecCount); + +uint32_t SDH_CardDetection(SDH_T *sdh); +void SDH_Open_Disk(SDH_T *sdh, uint32_t u32CardDetSrc); +void SDH_Close_Disk(SDH_T *sdh); + +/**@}*/ /* end of group SDH_EXPORTED_FUNCTIONS */ + +/**@}*/ /* end of group SDH_Driver */ + +/**@}*/ /* end of group Standard_Driver */ + +#ifdef __cplusplus +} +#endif + +#endif /* end of __NU_SDH_H__ */ diff --git a/Ubiquitous/XiZi/board/nuvoton-m2354/third_party_driver/include/Drivers/nu_spi.h b/Ubiquitous/XiZi/board/nuvoton-m2354/third_party_driver/include/Drivers/nu_spi.h new file mode 100644 index 0000000..067a56f --- /dev/null +++ b/Ubiquitous/XiZi/board/nuvoton-m2354/third_party_driver/include/Drivers/nu_spi.h @@ -0,0 +1,582 @@ +/****************************************************************************** + * @file nu_spi.h + * @version V3.00 + * @brief M2354 series SPI driver header file + * + * @copyright SPDX-License-Identifier: Apache-2.0 + * @copyright Copyright (C) 2020 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ +#ifndef __NU_SPI_H__ +#define __NU_SPI_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup SPI_Driver SPI Driver + @{ +*/ + +/** @addtogroup SPI_EXPORTED_CONSTANTS SPI Exported Constants + @{ +*/ + +#define SPI_MODE_0 (SPI_CTL_TXNEG_Msk) /*!< CLKPOL=0; RXNEG=0; TXNEG=1 */ +#define SPI_MODE_1 (SPI_CTL_RXNEG_Msk) /*!< CLKPOL=0; RXNEG=1; TXNEG=0 */ +#define SPI_MODE_2 (SPI_CTL_CLKPOL_Msk | SPI_CTL_RXNEG_Msk) /*!< CLKPOL=1; RXNEG=1; TXNEG=0 */ +#define SPI_MODE_3 (SPI_CTL_CLKPOL_Msk | SPI_CTL_TXNEG_Msk) /*!< CLKPOL=1; RXNEG=0; TXNEG=1 */ + +#define SPI_SLAVE (SPI_CTL_SLAVE_Msk) /*!< Set as slave */ +#define SPI_MASTER (0x0UL) /*!< Set as master */ + +#define SPI_SS (SPI_SSCTL_SS_Msk) /*!< Set SS */ +#define SPI_SS_ACTIVE_HIGH (SPI_SSCTL_SSACTPOL_Msk) /*!< SS active high */ +#define SPI_SS_ACTIVE_LOW (0x0UL) /*!< SS active low */ + +/* SPI Interrupt Mask */ +#define SPI_UNIT_INT_MASK (0x001UL) /*!< Unit transfer interrupt mask */ +#define SPI_SSACT_INT_MASK (0x002UL) /*!< Slave selection signal active interrupt mask */ +#define SPI_SSINACT_INT_MASK (0x004UL) /*!< Slave selection signal inactive interrupt mask */ +#define SPI_SLVUR_INT_MASK (0x008UL) /*!< Slave under run interrupt mask */ +#define SPI_SLVBE_INT_MASK (0x010UL) /*!< Slave bit count error interrupt mask */ +#define SPI_TXUF_INT_MASK (0x040UL) /*!< Slave TX underflow interrupt mask */ +#define SPI_FIFO_TXTH_INT_MASK (0x080UL) /*!< FIFO TX threshold interrupt mask */ +#define SPI_FIFO_RXTH_INT_MASK (0x100UL) /*!< FIFO RX threshold interrupt mask */ +#define SPI_FIFO_RXOV_INT_MASK (0x200UL) /*!< FIFO RX overrun interrupt mask */ +#define SPI_FIFO_RXTO_INT_MASK (0x400UL) /*!< FIFO RX time-out interrupt mask */ + +/* SPI Status Mask */ +#define SPI_BUSY_MASK (0x01UL) /*!< Busy status mask */ +#define SPI_RX_EMPTY_MASK (0x02UL) /*!< RX empty status mask */ +#define SPI_RX_FULL_MASK (0x04UL) /*!< RX full status mask */ +#define SPI_TX_EMPTY_MASK (0x08UL) /*!< TX empty status mask */ +#define SPI_TX_FULL_MASK (0x10UL) /*!< TX full status mask */ +#define SPI_TXRX_RESET_MASK (0x20UL) /*!< TX or RX reset status mask */ +#define SPI_SPIEN_STS_MASK (0x40UL) /*!< SPIEN status mask */ +#define SPI_SSLINE_STS_MASK (0x80UL) /*!< SPIx_SS line status mask */ + +/* SPI Status2 Mask */ +#define SPI_SLVBENUM_MASK (0x01UL) /*!< Effective bit number of uncompleted RX data status mask */ + + +/* I2S Data Width */ +#define SPII2S_DATABIT_8 (0UL << SPI_I2SCTL_WDWIDTH_Pos) /*!< I2S data width is 8-bit */ +#define SPII2S_DATABIT_16 (1UL << SPI_I2SCTL_WDWIDTH_Pos) /*!< I2S data width is 16-bit */ +#define SPII2S_DATABIT_24 (2UL << SPI_I2SCTL_WDWIDTH_Pos) /*!< I2S data width is 24-bit */ +#define SPII2S_DATABIT_32 (3UL << SPI_I2SCTL_WDWIDTH_Pos) /*!< I2S data width is 32-bit */ + +/* I2S Audio Format */ +#define SPII2S_MONO SPI_I2SCTL_MONO_Msk /*!< Monaural channel */ +#define SPII2S_STEREO (0UL) /*!< Stereo channel */ + +/* I2S Data Format */ +#define SPII2S_FORMAT_I2S (0UL << SPI_I2SCTL_FORMAT_Pos) /*!< I2S data format */ +#define SPII2S_FORMAT_MSB (1UL << SPI_I2SCTL_FORMAT_Pos) /*!< MSB justified data format */ +#define SPII2S_FORMAT_PCMA (2UL << SPI_I2SCTL_FORMAT_Pos) /*!< PCM mode A data format */ +#define SPII2S_FORMAT_PCMB (3UL << SPI_I2SCTL_FORMAT_Pos) /*!< PCM mode B data format */ + +/* I2S Operation mode */ +#define SPII2S_MODE_SLAVE SPI_I2SCTL_SLAVE_Msk /*!< As slave mode */ +#define SPII2S_MODE_MASTER (0UL) /*!< As master mode */ + +/* I2S TX FIFO Threshold */ +#define SPII2S_FIFO_TX_LEVEL_WORD_0 (0UL) /*!< TX threshold is 0 word */ +#define SPII2S_FIFO_TX_LEVEL_WORD_1 (1UL << SPI_FIFOCTL_TXTH_Pos) /*!< TX threshold is 1 word */ +#define SPII2S_FIFO_TX_LEVEL_WORD_2 (2UL << SPI_FIFOCTL_TXTH_Pos) /*!< TX threshold is 2 words */ +#define SPII2S_FIFO_TX_LEVEL_WORD_3 (3UL << SPI_FIFOCTL_TXTH_Pos) /*!< TX threshold is 3 words */ +/* I2S RX FIFO Threshold */ +#define SPII2S_FIFO_RX_LEVEL_WORD_1 (0UL) /*!< RX threshold is 1 word */ +#define SPII2S_FIFO_RX_LEVEL_WORD_2 (1UL << SPI_FIFOCTL_RXTH_Pos) /*!< RX threshold is 2 words */ +#define SPII2S_FIFO_RX_LEVEL_WORD_3 (2UL << SPI_FIFOCTL_RXTH_Pos) /*!< RX threshold is 3 words */ +#define SPII2S_FIFO_RX_LEVEL_WORD_4 (3UL << SPI_FIFOCTL_RXTH_Pos) /*!< RX threshold is 4 words */ + +/* I2S Record Channel */ +#define SPII2S_MONO_RIGHT (0UL) /*!< Record mono right channel */ +#define SPII2S_MONO_LEFT SPI_I2SCTL_RXLCH_Msk /*!< Record mono left channel */ + +/* I2S Channel */ +#define SPII2S_RIGHT (0UL) /*!< Select right channel */ +#define SPII2S_LEFT (1UL) /*!< Select left channel */ + +/* I2S Interrupt Mask */ +#define SPII2S_FIFO_TXTH_INT_MASK (0x01UL) /*!< TX FIFO threshold interrupt mask */ +#define SPII2S_FIFO_RXTH_INT_MASK (0x02UL) /*!< RX FIFO threshold interrupt mask */ +#define SPII2S_FIFO_RXOV_INT_MASK (0x04UL) /*!< RX FIFO overrun interrupt mask */ +#define SPII2S_FIFO_RXTO_INT_MASK (0x08UL) /*!< RX FIFO time-out interrupt mask */ +#define SPII2S_TXUF_INT_MASK (0x10UL) /*!< TX FIFO underflow interrupt mask */ +#define SPII2S_RIGHT_ZC_INT_MASK (0x20UL) /*!< Right channel zero cross interrupt mask */ +#define SPII2S_LEFT_ZC_INT_MASK (0x40UL) /*!< Left channel zero cross interrupt mask */ +#define SPII2S_SLAVE_ERR_INT_MASK (0x80UL) /*!< Bit clock loss interrupt mask */ + +/**@}*/ /* end of group SPI_EXPORTED_CONSTANTS */ + + +/** @addtogroup SPI_EXPORTED_FUNCTIONS SPI Exported Functions + @{ +*/ + +/** + * @brief Clear the unit transfer interrupt flag. + * @param[in] spi The pointer of the specified SPI module. + * @return None. + * @details Write 1 to UNITIF bit of SPI_STATUS register to clear the unit transfer interrupt flag. + */ +#define SPI_CLR_UNIT_TRANS_INT_FLAG(spi) ( (spi)->STATUS = SPI_STATUS_UNITIF_Msk ) + +/** + * @brief Disable Slave 3-wire mode. + * @param[in] spi The pointer of the specified SPI module. + * @return None. + * @details Clear SLV3WIRE bit of SPI_SSCTL register to disable Slave 3-wire mode. + */ +#define SPI_DISABLE_3WIRE_MODE(spi) ( (spi)->SSCTL &= ~SPI_SSCTL_SLV3WIRE_Msk ) + +/** + * @brief Enable Slave 3-wire mode. + * @param[in] spi The pointer of the specified SPI module. + * @return None. + * @details Set SLV3WIRE bit of SPI_SSCTL register to enable Slave 3-wire mode. + */ +#define SPI_ENABLE_3WIRE_MODE(spi) ( (spi)->SSCTL |= SPI_SSCTL_SLV3WIRE_Msk ) + +/** + * @brief Trigger RX PDMA function. + * @param[in] spi The pointer of the specified SPI module. + * @return None. + * @details Set RXPDMAEN bit of SPI_PDMACTL register to enable RX PDMA transfer function. + */ +#define SPI_TRIGGER_RX_PDMA(spi) ( (spi)->PDMACTL |= SPI_PDMACTL_RXPDMAEN_Msk ) + +/** + * @brief Trigger TX PDMA function. + * @param[in] spi The pointer of the specified SPI module. + * @return None. + * @details Set TXPDMAEN bit of SPI_PDMACTL register to enable TX PDMA transfer function. + */ +#define SPI_TRIGGER_TX_PDMA(spi) ( (spi)->PDMACTL |= SPI_PDMACTL_TXPDMAEN_Msk ) + +/** + * @brief Trigger TX and RX PDMA function. + * @param[in] spi The pointer of the specified SPI module. + * @return None. + * @details Set TXPDMAEN bit and RXPDMAEN bit of SPI_PDMACTL register to enable TX and RX PDMA transfer function. + */ +#define SPI_TRIGGER_TX_RX_PDMA(spi) ( (spi)->PDMACTL |= (SPI_PDMACTL_TXPDMAEN_Msk | SPI_PDMACTL_RXPDMAEN_Msk) ) + +/** + * @brief Disable RX PDMA transfer. + * @param[in] spi The pointer of the specified SPI module. + * @return None. + * @details Clear RXPDMAEN bit of SPI_PDMACTL register to disable RX PDMA transfer function. + */ +#define SPI_DISABLE_RX_PDMA(spi) ( (spi)->PDMACTL &= ~SPI_PDMACTL_RXPDMAEN_Msk ) + +/** + * @brief Disable TX PDMA transfer. + * @param[in] spi The pointer of the specified SPI module. + * @return None. + * @details Clear TXPDMAEN bit of SPI_PDMACTL register to disable TX PDMA transfer function. + */ +#define SPI_DISABLE_TX_PDMA(spi) ( (spi)->PDMACTL &= ~SPI_PDMACTL_TXPDMAEN_Msk ) + +/** + * @brief Disable TX and RX PDMA transfer. + * @param[in] spi The pointer of the specified SPI module. + * @return None. + * @details Clear TXPDMAEN bit and RXPDMAEN bit of SPI_PDMACTL register to disable TX and RX PDMA transfer function. + */ +#define SPI_DISABLE_TX_RX_PDMA(spi) ( (spi)->PDMACTL &= ~(SPI_PDMACTL_TXPDMAEN_Msk | SPI_PDMACTL_RXPDMAEN_Msk) ) + +/** + * @brief Get the count of available data in RX FIFO. + * @param[in] spi The pointer of the specified SPI module. + * @return The count of available data in RX FIFO. + * @details Read RXCNT (SPI_STATUS[27:24]) to get the count of available data in RX FIFO. + */ +#define SPI_GET_RX_FIFO_COUNT(spi) ( ((spi)->STATUS & SPI_STATUS_RXCNT_Msk) >> SPI_STATUS_RXCNT_Pos ) + +/** + * @brief Get the RX FIFO empty flag. + * @param[in] spi The pointer of the specified SPI module. + * @retval 0 RX FIFO is not empty. + * @retval 1 RX FIFO is empty. + * @details Read RXEMPTY bit of SPI_STATUS register to get the RX FIFO empty flag. + */ +#define SPI_GET_RX_FIFO_EMPTY_FLAG(spi) ( ((spi)->STATUS & SPI_STATUS_RXEMPTY_Msk) >> SPI_STATUS_RXEMPTY_Pos ) + +/** + * @brief Get the TX FIFO empty flag. + * @param[in] spi The pointer of the specified SPI module. + * @retval 0 TX FIFO is not empty. + * @retval 1 TX FIFO is empty. + * @details Read TXEMPTY bit of SPI_STATUS register to get the TX FIFO empty flag. + */ +#define SPI_GET_TX_FIFO_EMPTY_FLAG(spi) ( ((spi)->STATUS & SPI_STATUS_TXEMPTY_Msk) >> SPI_STATUS_TXEMPTY_Pos ) + +/** + * @brief Get the TX FIFO full flag. + * @param[in] spi The pointer of the specified SPI module. + * @retval 0 TX FIFO is not full. + * @retval 1 TX FIFO is full. + * @details Read TXFULL bit of SPI_STATUS register to get the TX FIFO full flag. + */ +#define SPI_GET_TX_FIFO_FULL_FLAG(spi) ( ((spi)->STATUS & SPI_STATUS_TXFULL_Msk) >> SPI_STATUS_TXFULL_Pos ) + +/** + * @brief Get the datum read from RX register. + * @param[in] spi The pointer of the specified SPI module. + * @return Data in RX register. + * @details Read SPI_RX register to get the received datum. + */ +#define SPI_READ_RX(spi) ( (spi)->RX ) + +/** + * @brief Write datum to TX register. + * @param[in] spi The pointer of the specified SPI module. + * @param[in] u32TxData The datum which user attempt to transfer through SPI bus. + * @return None. + * @details Write u32TxData to SPI_TX register. + */ +#define SPI_WRITE_TX(spi, u32TxData) ( (spi)->TX = (u32TxData) ) + +/** + * @brief Set SPIx_SS pin to high state. + * @param[in] spi The pointer of the specified SPI module. + * @return None. + * @details Disable automatic slave selection function and set SPIx_SS pin to high state. + */ +#define SPI_SET_SS_HIGH(spi) ( (spi)->SSCTL = ((spi)->SSCTL & (~SPI_SSCTL_AUTOSS_Msk)) | (SPI_SSCTL_SSACTPOL_Msk | SPI_SSCTL_SS_Msk) ) + +/** + * @brief Set SPIx_SS pin to low state. + * @param[in] spi The pointer of the specified SPI module. + * @return None. + * @details Disable automatic slave selection function and set SPIx_SS pin to low state. + */ +#define SPI_SET_SS_LOW(spi) ( (spi)->SSCTL = ((spi)->SSCTL & (~(SPI_SSCTL_AUTOSS_Msk | SPI_SSCTL_SSACTPOL_Msk))) | SPI_SSCTL_SS_Msk ) + +/** + * @brief Enable Byte Reorder function. + * @param[in] spi The pointer of the specified SPI module. + * @return None. + * @details Enable Byte Reorder function. The suspend interval depends on the setting of SUSPITV (SPI_CTL[7:4]). + */ +#define SPI_ENABLE_BYTE_REORDER(spi) ( (spi)->CTL |= SPI_CTL_REORDER_Msk ) + +/** + * @brief Disable Byte Reorder function. + * @param[in] spi The pointer of the specified SPI module. + * @return None. + * @details Clear REORDER bit field of SPI_CTL register to disable Byte Reorder function. + */ +#define SPI_DISABLE_BYTE_REORDER(spi) ( (spi)->CTL &= ~SPI_CTL_REORDER_Msk ) + +/** + * @brief Set the length of suspend interval. + * @param[in] spi The pointer of the specified SPI module. + * @param[in] u32SuspCycle Decides the length of suspend interval. It could be 0 ~ 15. + * @return None. + * @details Set the length of suspend interval according to u32SuspCycle. + * The length of suspend interval is ((u32SuspCycle + 0.5) * the length of one SPI bus clock cycle). + */ +#define SPI_SET_SUSPEND_CYCLE(spi, u32SuspCycle) ( (spi)->CTL = ((spi)->CTL & ~SPI_CTL_SUSPITV_Msk) | ((u32SuspCycle) << SPI_CTL_SUSPITV_Pos) ) + +/** + * @brief Set the SPI transfer sequence with LSB first. + * @param[in] spi The pointer of the specified SPI module. + * @return None. + * @details Set LSB bit of SPI_CTL register to set the SPI transfer sequence with LSB first. + */ +#define SPI_SET_LSB_FIRST(spi) ( (spi)->CTL |= SPI_CTL_LSB_Msk ) + +/** + * @brief Set the SPI transfer sequence with MSB first. + * @param[in] spi The pointer of the specified SPI module. + * @return None. + * @details Clear LSB bit of SPI_CTL register to set the SPI transfer sequence with MSB first. + */ +#define SPI_SET_MSB_FIRST(spi) ( (spi)->CTL &= ~SPI_CTL_LSB_Msk ) + +/** + * @brief Set the data width of a SPI transaction. + * @param[in] spi The pointer of the specified SPI module. + * @param[in] u32Width The bit width of one transaction. + * @return None. + * @details The data width can be 8 ~ 32 bits. + */ +#define SPI_SET_DATA_WIDTH(spi, u32Width) ( (spi)->CTL = ((spi)->CTL & ~SPI_CTL_DWIDTH_Msk) | (((u32Width) & 0x1F) << SPI_CTL_DWIDTH_Pos) ) + +/** + * @brief Get the SPI busy state. + * @param[in] spi The pointer of the specified SPI module. + * @retval 0 SPI controller is not busy. + * @retval 1 SPI controller is busy. + * @details This macro will return the busy state of SPI controller. + */ +#define SPI_IS_BUSY(spi) ( ((spi)->STATUS & SPI_STATUS_BUSY_Msk) >> SPI_STATUS_BUSY_Pos ) + +/** + * @brief Enable SPI controller. + * @param[in] spi The pointer of the specified SPI module. + * @return None. + * @details Set SPIEN (SPI_CTL[0]) to enable SPI controller. + */ +#define SPI_ENABLE(spi) ( (spi)->CTL |= SPI_CTL_SPIEN_Msk ) + +/** + * @brief Disable SPI controller. + * @param[in] spi The pointer of the specified SPI module. + * @return None. + * @details Clear SPIEN (SPI_CTL[0]) to disable SPI controller. + */ +#define SPI_DISABLE(spi) ( (spi)->CTL &= ~SPI_CTL_SPIEN_Msk ) + +/** + * @brief Enable zero cross detection function. + * @param[in] i2s The pointer of the specified I2S module. + * @param[in] u32ChMask The mask for left or right channel. Valid values are: + * - \ref SPII2S_RIGHT + * - \ref SPII2S_LEFT + * @return None + * @details This function will set RZCEN or LZCEN bit of SPI_I2SCTL register to enable zero cross detection function. + */ +__STATIC_INLINE void SPII2S_ENABLE_TX_ZCD(SPI_T *i2s, uint32_t u32ChMask) +{ + if(u32ChMask == SPII2S_RIGHT) + { + i2s->I2SCTL |= SPI_I2SCTL_RZCEN_Msk; + } + else + { + i2s->I2SCTL |= SPI_I2SCTL_LZCEN_Msk; + } +} + +/** + * @brief Disable zero cross detection function. + * @param[in] i2s The pointer of the specified I2S module. + * @param[in] u32ChMask The mask for left or right channel. Valid values are: + * - \ref SPII2S_RIGHT + * - \ref SPII2S_LEFT + * @return None + * @details This function will clear RZCEN or LZCEN bit of SPI_I2SCTL register to disable zero cross detection function. + */ +__STATIC_INLINE void SPII2S_DISABLE_TX_ZCD(SPI_T *i2s, uint32_t u32ChMask) +{ + if(u32ChMask == SPII2S_RIGHT) + { + i2s->I2SCTL &= ~SPI_I2SCTL_RZCEN_Msk; + } + else + { + i2s->I2SCTL &= ~SPI_I2SCTL_LZCEN_Msk; + } +} + +/** + * @brief Enable I2S TX DMA function. + * @param[in] i2s The pointer of the specified I2S module. + * @return None + * @details This macro will set TXPDMAEN bit of SPI_PDMACTL register to transmit data with PDMA. + */ +#define SPII2S_ENABLE_TXDMA(i2s) ( (i2s)->PDMACTL |= SPI_PDMACTL_TXPDMAEN_Msk ) + +/** + * @brief Disable I2S TX DMA function. + * @param[in] i2s The pointer of the specified I2S module. + * @return None + * @details This macro will clear TXPDMAEN bit of SPI_PDMACTL register to disable TX DMA function. + */ +#define SPII2S_DISABLE_TXDMA(i2s) ( (i2s)->PDMACTL &= ~SPI_PDMACTL_TXPDMAEN_Msk ) + +/** + * @brief Enable I2S RX DMA function. + * @param[in] i2s The pointer of the specified I2S module. + * @return None + * @details This macro will set RXPDMAEN bit of SPI_PDMACTL register to receive data with PDMA. + */ +#define SPII2S_ENABLE_RXDMA(i2s) ( (i2s)->PDMACTL |= SPI_PDMACTL_RXPDMAEN_Msk ) + +/** + * @brief Disable I2S RX DMA function. + * @param[in] i2s The pointer of the specified I2S module. + * @return None + * @details This macro will clear RXPDMAEN bit of SPI_PDMACTL register to disable RX DMA function. + */ +#define SPII2S_DISABLE_RXDMA(i2s) ( (i2s)->PDMACTL &= ~SPI_PDMACTL_RXPDMAEN_Msk ) + +/** + * @brief Enable I2S TX function. + * @param[in] i2s The pointer of the specified I2S module. + * @return None + * @details This macro will set TXEN bit of SPI_I2SCTL register to enable I2S TX function. + */ +#define SPII2S_ENABLE_TX(i2s) ( (i2s)->I2SCTL |= SPI_I2SCTL_TXEN_Msk ) + +/** + * @brief Disable I2S TX function. + * @param[in] i2s The pointer of the specified I2S module. + * @return None + * @details This macro will clear TXEN bit of SPI_I2SCTL register to disable I2S TX function. + */ +#define SPII2S_DISABLE_TX(i2s) ( (i2s)->I2SCTL &= ~SPI_I2SCTL_TXEN_Msk ) + +/** + * @brief Enable I2S RX function. + * @param[in] i2s The pointer of the specified I2S module. + * @return None + * @details This macro will set RXEN bit of SPI_I2SCTL register to enable I2S RX function. + */ +#define SPII2S_ENABLE_RX(i2s) ( (i2s)->I2SCTL |= SPI_I2SCTL_RXEN_Msk ) + +/** + * @brief Disable I2S RX function. + * @param[in] i2s The pointer of the specified I2S module. + * @return None + * @details This macro will clear RXEN bit of SPI_I2SCTL register to disable I2S RX function. + */ +#define SPII2S_DISABLE_RX(i2s) ( (i2s)->I2SCTL &= ~SPI_I2SCTL_RXEN_Msk ) + +/** + * @brief Enable TX Mute function. + * @param[in] i2s The pointer of the specified I2S module. + * @return None + * @details This macro will set MUTE bit of SPI_I2SCTL register to enable I2S TX mute function. + */ +#define SPII2S_ENABLE_TX_MUTE(i2s) ( (i2s)->I2SCTL |= SPI_I2SCTL_MUTE_Msk ) + +/** + * @brief Disable TX Mute function. + * @param[in] i2s The pointer of the specified I2S module. + * @return None + * @details This macro will clear MUTE bit of SPI_I2SCTL register to disable I2S TX mute function. + */ +#define SPII2S_DISABLE_TX_MUTE(i2s) ( (i2s)->I2SCTL &= ~SPI_I2SCTL_MUTE_Msk ) + +/** + * @brief Clear TX FIFO. + * @param[in] i2s The pointer of the specified I2S module. + * @return None + * @details This macro will clear TX FIFO. The internal TX FIFO pointer will be reset to FIFO start point. + */ +#define SPII2S_CLR_TX_FIFO(i2s) ( (i2s)->FIFOCTL |= SPI_FIFOCTL_TXFBCLR_Msk ) + +/** + * @brief Clear RX FIFO. + * @param[in] i2s The pointer of the specified I2S module. + * @return None + * @details This macro will clear RX FIFO. The internal RX FIFO pointer will be reset to FIFO start point. + */ +#define SPII2S_CLR_RX_FIFO(i2s) ( (i2s)->FIFOCTL |= SPI_FIFOCTL_RXFBCLR_Msk ) + +/** + * @brief This function sets the recording source channel when mono mode is used. + * @param[in] i2s The pointer of the specified I2S module. + * @param[in] u32Ch left or right channel. Valid values are: + * - \ref SPII2S_MONO_LEFT + * - \ref SPII2S_MONO_RIGHT + * @return None + * @details This function selects the recording source channel of monaural mode. + */ +__STATIC_INLINE void SPII2S_SET_MONO_RX_CHANNEL(SPI_T *i2s, uint32_t u32Ch) +{ + u32Ch == SPII2S_MONO_LEFT ? + (i2s->I2SCTL |= SPI_I2SCTL_RXLCH_Msk) : + (i2s->I2SCTL &= ~SPI_I2SCTL_RXLCH_Msk); +} + +/** + * @brief Write data to I2S TX FIFO. + * @param[in] i2s The pointer of the specified I2S module. + * @param[in] u32Data The value written to TX FIFO. + * @return None + * @details This macro will write a value to TX FIFO. + */ +#define SPII2S_WRITE_TX_FIFO(i2s, u32Data) ( (i2s)->TX = (u32Data) ) + +/** + * @brief Read RX FIFO. + * @param[in] i2s The pointer of the specified I2S module. + * @return The value read from RX FIFO. + * @details This function will return a value read from RX FIFO. + */ +#define SPII2S_READ_RX_FIFO(i2s) ( (i2s)->RX ) + +/** + * @brief Get the interrupt flag. + * @param[in] i2s The pointer of the specified I2S module. + * @param[in] u32Mask The mask value for all interrupt flags. + * @return The interrupt flags specified by the u32mask parameter. + * @details This macro will return the combination interrupt flags of SPI_I2SSTS register. The flags are specified by the u32mask parameter. + */ +#define SPII2S_GET_INT_FLAG(i2s, u32Mask) ( (i2s)->I2SSTS & (u32Mask) ) + +/** + * @brief Clear the interrupt flag. + * @param[in] i2s The pointer of the specified I2S module. + * @param[in] u32Mask The mask value for all interrupt flags. + * @return None + * @details This macro will clear the interrupt flags specified by the u32mask parameter. + * @note Except TX and RX FIFO threshold interrupt flags, the other interrupt flags can be cleared by writing 1 to itself. + */ +#define SPII2S_CLR_INT_FLAG(i2s, u32Mask) ( (i2s)->I2SSTS = (u32Mask) ) + +/** + * @brief Get transmit FIFO level + * @param[in] i2s The pointer of the specified I2S module. + * @return TX FIFO level + * @details This macro will return the number of available words in TX FIFO. + */ +#define SPII2S_GET_TX_FIFO_LEVEL(i2s) ( ((i2s)->I2SSTS & SPI_I2SSTS_TXCNT_Msk) >> SPI_I2SSTS_TXCNT_Pos ) + +/** + * @brief Get receive FIFO level + * @param[in] i2s The pointer of the specified I2S module. + * @return RX FIFO level + * @details This macro will return the number of available words in RX FIFO. + */ +#define SPII2S_GET_RX_FIFO_LEVEL(i2s) ( ((i2s)->I2SSTS & SPI_I2SSTS_RXCNT_Msk) >> SPI_I2SSTS_RXCNT_Pos ) + +/* Function prototype declaration */ +uint32_t SPI_Open(SPI_T *spi, uint32_t u32MasterSlave, uint32_t u32SPIMode, uint32_t u32DataWidth, uint32_t u32BusClock); +void SPI_Close(SPI_T *spi); +void SPI_ClearRxFIFO(SPI_T *spi); +void SPI_ClearTxFIFO(SPI_T *spi); +void SPI_DisableAutoSS(SPI_T *spi); +void SPI_EnableAutoSS(SPI_T *spi, uint32_t u32SSPinMask, uint32_t u32ActiveLevel); +uint32_t SPI_SetBusClock(SPI_T *spi, uint32_t u32BusClock); +void SPI_SetFIFO(SPI_T *spi, uint32_t u32TxThreshold, uint32_t u32RxThreshold); +uint32_t SPI_GetBusClock(SPI_T *spi); +void SPI_EnableInt(SPI_T *spi, uint32_t u32Mask); +void SPI_DisableInt(SPI_T *spi, uint32_t u32Mask); +uint32_t SPI_GetIntFlag(SPI_T *spi, uint32_t u32Mask); +void SPI_ClearIntFlag(SPI_T *spi, uint32_t u32Mask); +uint32_t SPI_GetStatus(SPI_T *spi, uint32_t u32Mask); +uint32_t SPI_GetStatus2(SPI_T *spi, uint32_t u32Mask); + +uint32_t SPII2S_Open(SPI_T *i2s, uint32_t u32MasterSlave, uint32_t u32SampleRate, uint32_t u32WordWidth, uint32_t u32Channels, uint32_t u32DataFormat); +void SPII2S_Close(SPI_T *i2s); +void SPII2S_EnableInt(SPI_T *i2s, uint32_t u32Mask); +void SPII2S_DisableInt(SPI_T *i2s, uint32_t u32Mask); +uint32_t SPII2S_EnableMCLK(SPI_T *i2s, uint32_t u32BusClock); +void SPII2S_DisableMCLK(SPI_T *i2s); +void SPII2S_SetFIFO(SPI_T *i2s, uint32_t u32TxThreshold, uint32_t u32RxThreshold); + + +/**@}*/ /* end of group SPI_EXPORTED_FUNCTIONS */ + +/**@}*/ /* end of group SPI_Driver */ + +/**@}*/ /* end of group Standard_Driver */ + +#ifdef __cplusplus +} +#endif + +#endif /* __NU_SPI_H__ */ diff --git a/Ubiquitous/XiZi/board/nuvoton-m2354/third_party_driver/include/Drivers/nu_sys.h b/Ubiquitous/XiZi/board/nuvoton-m2354/third_party_driver/include/Drivers/nu_sys.h new file mode 100644 index 0000000..08c6246 --- /dev/null +++ b/Ubiquitous/XiZi/board/nuvoton-m2354/third_party_driver/include/Drivers/nu_sys.h @@ -0,0 +1,4313 @@ +/**************************************************************************//** + * @file nu_sys.h + * @version V3 + * @brief M2354 series System Manager (SYS) driver header file + * + * @copyright SPDX-License-Identifier: Apache-2.0 + * @copyright Copyright (C) 2020 Nuvoton Technology Corp. All rights reserved. + ******************************************************************************/ +#ifndef __NU_SYS_H__ +#define __NU_SYS_H__ + + +#ifdef __cplusplus +extern "C" +{ +#endif + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup SYS_Driver SYS Driver + @{ +*/ + +/** @addtogroup SYS_EXPORTED_CONSTANTS SYS Exported Constants + @{ +*/ + +/*---------------------------------------------------------------------------------------------------------*/ +/* Module Reset Control Resister constant definitions. */ +/*---------------------------------------------------------------------------------------------------------*/ +#define PDMA0_RST ((0x0UL<<24)|(uint32_t)SYS_IPRST0_PDMA0RST_Pos) /*!< PDMA0 reset is one of the SYS_ResetModule parameter */ +#define EBI_RST ((0x0UL<<24)|(uint32_t)SYS_IPRST0_EBIRST_Pos) /*!< EBI reset is one of the SYS_ResetModule parameter */ +#define USBH_RST ((0x0UL<<24)|(uint32_t)SYS_IPRST0_USBHRST_Pos) /*!< USBH reset is one of the SYS_ResetModule parameter */ +#define SDH0_RST ((0x0UL<<24)|(uint32_t)SYS_IPRST0_SDH0RST_Pos) /*!< SDH0 reset is one of the SYS_ResetModule parameter */ +#define CRC_RST ((0x0UL<<24)|(uint32_t)SYS_IPRST0_CRCRST_Pos) /*!< CRC reset is one of the SYS_ResetModule parameter */ +#define CRPT_RST ((0x0UL<<24)|(uint32_t)SYS_IPRST0_CRPTRST_Pos) /*!< CRPT reset is one of the SYS_ResetModule parameter */ +#define KS_RST ((0x0UL<<24)|(uint32_t)SYS_IPRST0_KSRST_Pos) /*!< KS reset is one of the SYS_ResetModule parameter */ +#define PDMA1_RST ((0x0UL<<24)|(uint32_t)SYS_IPRST0_PDMA1RST_Pos) /*!< PDMA1 reset is one of the SYS_ResetModule parameter */ + +#define GPIO_RST ((0x4UL<<24)|(uint32_t)SYS_IPRST1_GPIORST_Pos) /*!< GPIO reset is one of the SYS_ResetModule parameter */ +#define TMR0_RST ((0x4UL<<24)|(uint32_t)SYS_IPRST1_TMR0RST_Pos) /*!< TMR0 reset is one of the SYS_ResetModule parameter */ +#define TMR1_RST ((0x4UL<<24)|(uint32_t)SYS_IPRST1_TMR1RST_Pos) /*!< TMR1 reset is one of the SYS_ResetModule parameter */ +#define TMR2_RST ((0x4UL<<24)|(uint32_t)SYS_IPRST1_TMR2RST_Pos) /*!< TMR2 reset is one of the SYS_ResetModule parameter */ +#define TMR3_RST ((0x4UL<<24)|(uint32_t)SYS_IPRST1_TMR3RST_Pos) /*!< TMR3 reset is one of the SYS_ResetModule parameter */ +#define TMR4_RST ((0x8UL<<24)|(uint32_t)SYS_IPRST2_TMR4RST_Pos) /*!< TMR4 reset is one of the SYS_ResetModule parameter */ +#define TMR5_RST ((0x8UL<<24)|(uint32_t)SYS_IPRST2_TMR5RST_Pos) /*!< TMR5 reset is one of the SYS_ResetModule parameter */ + +#define ACMP01_RST ((0x4UL<<24)|(uint32_t)SYS_IPRST1_ACMP01RST_Pos) /*!< ACMP01 reset is one of the SYS_ResetModule parameter */ +#define I2C0_RST ((0x4UL<<24)|(uint32_t)SYS_IPRST1_I2C0RST_Pos) /*!< I2C0 reset is one of the SYS_ResetModule parameter */ +#define I2C1_RST ((0x4UL<<24)|(uint32_t)SYS_IPRST1_I2C1RST_Pos) /*!< I2C1 reset is one of the SYS_ResetModule parameter */ +#define I2C2_RST ((0x4UL<<24)|(uint32_t)SYS_IPRST1_I2C2RST_Pos) /*!< I2C2 reset is one of the SYS_ResetModule parameter */ +#define QSPI0_RST ((0x4UL<<24)|(uint32_t)SYS_IPRST1_QSPI0RST_Pos) /*!< QSPI0 reset is one of the SYS_ResetModule parameter */ +#define SPI0_RST ((0x4UL<<24)|(uint32_t)SYS_IPRST1_SPI0RST_Pos) /*!< SPI0 reset is one of the SYS_ResetModule parameter */ +#define SPI1_RST ((0x4UL<<24)|(uint32_t)SYS_IPRST1_SPI1RST_Pos) /*!< SPI1 reset is one of the SYS_ResetModule parameter */ +#define SPI2_RST ((0x4UL<<24)|(uint32_t)SYS_IPRST1_SPI2RST_Pos) /*!< SPI2 reset is one of the SYS_ResetModule parameter */ +#define UART0_RST ((0x4UL<<24)|(uint32_t)SYS_IPRST1_UART0RST_Pos) /*!< UART0 reset is one of the SYS_ResetModule parameter */ +#define UART1_RST ((0x4UL<<24)|(uint32_t)SYS_IPRST1_UART1RST_Pos) /*!< UART1 reset is one of the SYS_ResetModule parameter */ +#define UART2_RST ((0x4UL<<24)|(uint32_t)SYS_IPRST1_UART2RST_Pos) /*!< UART2 reset is one of the SYS_ResetModule parameter */ +#define UART3_RST ((0x4UL<<24)|(uint32_t)SYS_IPRST1_UART3RST_Pos) /*!< UART3 reset is one of the SYS_ResetModule parameter */ +#define UART4_RST ((0x4UL<<24)|(uint32_t)SYS_IPRST1_UART4RST_Pos) /*!< UART4 reset is one of the SYS_ResetModule parameter */ +#define UART5_RST ((0x4UL<<24)|(uint32_t)SYS_IPRST1_UART5RST_Pos) /*!< UART5 reset is one of the SYS_ResetModule parameter */ +#define CAN0_RST ((0x4UL<<24)|(uint32_t)SYS_IPRST1_CAN0RST_Pos) /*!< CAN0 reset is one of the SYS_ResetModule parameter */ +#define OTG_RST ((0x4UL<<24)|(uint32_t)SYS_IPRST1_OTGRST_Pos) /*!< OTG reset is one of the SYS_ResetModule parameter */ +#define USBD_RST ((0x4UL<<24)|(uint32_t)SYS_IPRST1_USBDRST_Pos) /*!< USBD reset is one of the SYS_ResetModule parameter */ +#define EADC_RST ((0x4UL<<24)|(uint32_t)SYS_IPRST1_EADCRST_Pos) /*!< EADC reset is one of the SYS_ResetModule parameter */ +#define I2S0_RST ((0x4UL<<24)|(uint32_t)SYS_IPRST1_I2S0RST_Pos) /*!< I2S0 reset is one of the SYS_ResetModule parameter */ +#define LCD_RST ((0x4UL<<24)|(uint32_t)SYS_IPRST1_LCDRST_Pos) /*!< LCD reset is one of the SYS_ResetModule parameter */ +#define TRNG_RST ((0x4UL<<24)|(uint32_t)SYS_IPRST1_TRNGRST_Pos) /*!< TRNG reset is one of the SYS_ResetModule parameter */ + +#define SC0_RST ((0x8UL<<24)|(uint32_t)SYS_IPRST2_SC0RST_Pos) /*!< SC0 reset is one of the SYS_ResetModule parameter */ +#define SC1_RST ((0x8UL<<24)|(uint32_t)SYS_IPRST2_SC1RST_Pos) /*!< SC1 reset is one of the SYS_ResetModule parameter */ +#define SC2_RST ((0x8UL<<24)|(uint32_t)SYS_IPRST2_SC2RST_Pos) /*!< SC2 reset is one of the SYS_ResetModule parameter */ +#define SPI3_RST ((0x8UL<<24)|(uint32_t)SYS_IPRST2_SPI3RST_Pos) /*!< SPI3 reset is one of the SYS_ResetModule parameter */ +#define USCI0_RST ((0x8UL<<24)|(uint32_t)SYS_IPRST2_USCI0RST_Pos) /*!< USCI0 reset is one of the SYS_ResetModule parameter */ +#define USCI1_RST ((0x8UL<<24)|(uint32_t)SYS_IPRST2_USCI1RST_Pos) /*!< USCI1 reset is one of the SYS_ResetModule parameter */ +#define DAC_RST ((0x8UL<<24)|(uint32_t)SYS_IPRST2_DACRST_Pos) /*!< DAC reset is one of the SYS_ResetModule parameter */ +#define EPWM0_RST ((0x8UL<<24)|(uint32_t)SYS_IPRST2_EPWM0RST_Pos) /*!< EPWM0 reset is one of the SYS_ResetModule parameter */ +#define EPWM1_RST ((0x8UL<<24)|(uint32_t)SYS_IPRST2_EPWM1RST_Pos) /*!< EPWM1 reset is one of the SYS_ResetModule parameter */ +#define BPWM0_RST ((0x8UL<<24)|(uint32_t)SYS_IPRST2_BPWM0RST_Pos) /*!< BPWM0 reset is one of the SYS_ResetModule parameter */ +#define BPWM1_RST ((0x8UL<<24)|(uint32_t)SYS_IPRST2_BPWM1RST_Pos) /*!< BPWM1 reset is one of the SYS_ResetModule parameter */ +#define QEI0_RST ((0x8UL<<24)|(uint32_t)SYS_IPRST2_QEI0RST_Pos) /*!< QEI0 reset is one of the SYS_ResetModule parameter */ +#define QEI1_RST ((0x8UL<<24)|(uint32_t)SYS_IPRST2_QEI1RST_Pos) /*!< QEI1 reset is one of the SYS_ResetModule parameter */ +#define ECAP0_RST ((0x8UL<<24)|(uint32_t)SYS_IPRST2_ECAP0RST_Pos) /*!< ECAP0 reset is one of the SYS_ResetModule parameter */ +#define ECAP1_RST ((0x8UL<<24)|(uint32_t)SYS_IPRST2_ECAP1RST_Pos) /*!< ECAP1 reset is one of the SYS_ResetModule parameter */ + + +/*---------------------------------------------------------------------------------------------------------*/ +/* Brown Out Detector Threshold Voltage Selection constant definitions. */ +/*---------------------------------------------------------------------------------------------------------*/ +#define SYS_BODCTL_BOD_RST_EN (1UL<GPA_MFPL = (SYS->GPA_MFPL & (~SYS_GPA_MFPL_PA0MFP_Msk)) | SYS_GPA_MFPL_PA0MFP_UART0_RXD; + SYS->GPA_MFPL = (SYS->GPA_MFPL & (~SYS_GPA_MFPL_PA1MFP_Msk)) | SYS_GPA_MFPL_PA1MFP_UART0_TXD; +*/ + + +/* PA.0 MFP */ +#define SYS_GPA_MFPL_PA0MFP_GPIO (0x0UL<GPB_MFPL = (SYS->GPB_MFPL & (~ACMP0_N_PB3_Msk)) | ACMP0_N_PB3 /*!< Set PB3 function to ACMP0_N */ +#define SET_ACMP0_O_PB7() SYS->GPB_MFPL = (SYS->GPB_MFPL & (~ACMP0_O_PB7_Msk)) | ACMP0_O_PB7 /*!< Set PB7 function to ACMP0_O */ +#define SET_ACMP0_O_PC1() SYS->GPC_MFPL = (SYS->GPC_MFPL & (~ACMP0_O_PC1_Msk)) | ACMP0_O_PC1 /*!< Set PC1 function to ACMP0_O */ +#define SET_ACMP0_O_PC12() SYS->GPC_MFPH = (SYS->GPC_MFPH & (~ACMP0_O_PC12_Msk)) | ACMP0_O_PC12 /*!< Set PC12 function to ACMP0_O */ +#define SET_ACMP0_P0_PA11() SYS->GPA_MFPH = (SYS->GPA_MFPH & (~ACMP0_P0_PA11_Msk)) | ACMP0_P0_PA11 /*!< Set PA11 function to ACMP0_P0 */ +#define SET_ACMP0_P1_PB2() SYS->GPB_MFPL = (SYS->GPB_MFPL & (~ACMP0_P1_PB2_Msk)) | ACMP0_P1_PB2 /*!< Set PB2 function to ACMP0_P1 */ +#define SET_ACMP0_P2_PB12() SYS->GPB_MFPH = (SYS->GPB_MFPH & (~ACMP0_P2_PB12_Msk)) | ACMP0_P2_PB12 /*!< Set PB12 function to ACMP0_P2 */ +#define SET_ACMP0_P3_PB13() SYS->GPB_MFPH = (SYS->GPB_MFPH & (~ACMP0_P3_PB13_Msk)) | ACMP0_P3_PB13 /*!< Set PB13 function to ACMP0_P3 */ +#define SET_ACMP0_WLAT_PA7() SYS->GPA_MFPL = (SYS->GPA_MFPL & (~ACMP0_WLAT_PA7_Msk)) | ACMP0_WLAT_PA7 /*!< Set PA7 function to ACMP0_WLAT */ +#define SET_ACMP1_N_PB5() SYS->GPB_MFPL = (SYS->GPB_MFPL & (~ACMP1_N_PB5_Msk)) | ACMP1_N_PB5 /*!< Set PB5 function to ACMP1_N */ +#define SET_ACMP1_O_PB6() SYS->GPB_MFPL = (SYS->GPB_MFPL & (~ACMP1_O_PB6_Msk)) | ACMP1_O_PB6 /*!< Set PB6 function to ACMP1_O */ +#define SET_ACMP1_O_PC11() SYS->GPC_MFPH = (SYS->GPC_MFPH & (~ACMP1_O_PC11_Msk)) | ACMP1_O_PC11 /*!< Set PC11 function to ACMP1_O */ +#define SET_ACMP1_O_PC0() SYS->GPC_MFPL = (SYS->GPC_MFPL & (~ACMP1_O_PC0_Msk)) | ACMP1_O_PC0 /*!< Set PC0 function to ACMP1_O */ +#define SET_ACMP1_P0_PA10() SYS->GPA_MFPH = (SYS->GPA_MFPH & (~ACMP1_P0_PA10_Msk)) | ACMP1_P0_PA10 /*!< Set PA10 function to ACMP1_P0 */ +#define SET_ACMP1_P1_PB4() SYS->GPB_MFPL = (SYS->GPB_MFPL & (~ACMP1_P1_PB4_Msk)) | ACMP1_P1_PB4 /*!< Set PB4 function to ACMP1_P1 */ +#define SET_ACMP1_P2_PB12() SYS->GPB_MFPH = (SYS->GPB_MFPH & (~ACMP1_P2_PB12_Msk)) | ACMP1_P2_PB12 /*!< Set PB12 function to ACMP1_P2 */ +#define SET_ACMP1_P3_PB13() SYS->GPB_MFPH = (SYS->GPB_MFPH & (~ACMP1_P3_PB13_Msk)) | ACMP1_P3_PB13 /*!< Set PB13 function to ACMP1_P3 */ +#define SET_ACMP1_WLAT_PA6() SYS->GPA_MFPL = (SYS->GPA_MFPL & (~ACMP1_WLAT_PA6_Msk)) | ACMP1_WLAT_PA6 /*!< Set PA6 function to ACMP1_WLAT */ +#define SET_BPWM0_CH0_PA0() SYS->GPA_MFPL = (SYS->GPA_MFPL & (~BPWM0_CH0_PA0_Msk)) | BPWM0_CH0_PA0 /*!< Set PA0 function to BPWM0_CH0 */ +#define SET_BPWM0_CH0_PA11() SYS->GPA_MFPH = (SYS->GPA_MFPH & (~BPWM0_CH0_PA11_Msk)) | BPWM0_CH0_PA11 /*!< Set PA11 function to BPWM0_CH0 */ +#define SET_BPWM0_CH0_PE2() SYS->GPE_MFPL = (SYS->GPE_MFPL & (~BPWM0_CH0_PE2_Msk)) | BPWM0_CH0_PE2 /*!< Set PE2 function to BPWM0_CH0 */ +#define SET_BPWM0_CH0_PG14() SYS->GPG_MFPH = (SYS->GPG_MFPH & (~BPWM0_CH0_PG14_Msk)) | BPWM0_CH0_PG14 /*!< Set PG14 function to BPWM0_CH0 */ +#define SET_BPWM0_CH1_PA1() SYS->GPA_MFPL = (SYS->GPA_MFPL & (~BPWM0_CH1_PA1_Msk)) | BPWM0_CH1_PA1 /*!< Set PA1 function to BPWM0_CH1 */ +#define SET_BPWM0_CH1_PE3() SYS->GPE_MFPL = (SYS->GPE_MFPL & (~BPWM0_CH1_PE3_Msk)) | BPWM0_CH1_PE3 /*!< Set PE3 function to BPWM0_CH1 */ +#define SET_BPWM0_CH1_PG13() SYS->GPG_MFPH = (SYS->GPG_MFPH & (~BPWM0_CH1_PG13_Msk)) | BPWM0_CH1_PG13 /*!< Set PG13 function to BPWM0_CH1 */ +#define SET_BPWM0_CH1_PA10() SYS->GPA_MFPH = (SYS->GPA_MFPH & (~BPWM0_CH1_PA10_Msk)) | BPWM0_CH1_PA10 /*!< Set PA10 function to BPWM0_CH1 */ +#define SET_BPWM0_CH2_PE4() SYS->GPE_MFPL = (SYS->GPE_MFPL & (~BPWM0_CH2_PE4_Msk)) | BPWM0_CH2_PE4 /*!< Set PE4 function to BPWM0_CH2 */ +#define SET_BPWM0_CH2_PG12() SYS->GPG_MFPH = (SYS->GPG_MFPH & (~BPWM0_CH2_PG12_Msk)) | BPWM0_CH2_PG12 /*!< Set PG12 function to BPWM0_CH2 */ +#define SET_BPWM0_CH2_PA2() SYS->GPA_MFPL = (SYS->GPA_MFPL & (~BPWM0_CH2_PA2_Msk)) | BPWM0_CH2_PA2 /*!< Set PA2 function to BPWM0_CH2 */ +#define SET_BPWM0_CH2_PA9() SYS->GPA_MFPH = (SYS->GPA_MFPH & (~BPWM0_CH2_PA9_Msk)) | BPWM0_CH2_PA9 /*!< Set PA9 function to BPWM0_CH2 */ +#define SET_BPWM0_CH3_PG11() SYS->GPG_MFPH = (SYS->GPG_MFPH & (~BPWM0_CH3_PG11_Msk)) | BPWM0_CH3_PG11 /*!< Set PG11 function to BPWM0_CH3 */ +#define SET_BPWM0_CH3_PA3() SYS->GPA_MFPL = (SYS->GPA_MFPL & (~BPWM0_CH3_PA3_Msk)) | BPWM0_CH3_PA3 /*!< Set PA3 function to BPWM0_CH3 */ +#define SET_BPWM0_CH3_PA8() SYS->GPA_MFPH = (SYS->GPA_MFPH & (~BPWM0_CH3_PA8_Msk)) | BPWM0_CH3_PA8 /*!< Set PA8 function to BPWM0_CH3 */ +#define SET_BPWM0_CH3_PE5() SYS->GPE_MFPL = (SYS->GPE_MFPL & (~BPWM0_CH3_PE5_Msk)) | BPWM0_CH3_PE5 /*!< Set PE5 function to BPWM0_CH3 */ +#define SET_BPWM0_CH4_PG10() SYS->GPG_MFPH = (SYS->GPG_MFPH & (~BPWM0_CH4_PG10_Msk)) | BPWM0_CH4_PG10 /*!< Set PG10 function to BPWM0_CH4 */ +#define SET_BPWM0_CH4_PA4() SYS->GPA_MFPL = (SYS->GPA_MFPL & (~BPWM0_CH4_PA4_Msk)) | BPWM0_CH4_PA4 /*!< Set PA4 function to BPWM0_CH4 */ +#define SET_BPWM0_CH4_PC13() SYS->GPC_MFPH = (SYS->GPC_MFPH & (~BPWM0_CH4_PC13_Msk)) | BPWM0_CH4_PC13 /*!< Set PC13 function to BPWM0_CH4 */ +#define SET_BPWM0_CH4_PE6() SYS->GPE_MFPL = (SYS->GPE_MFPL & (~BPWM0_CH4_PE6_Msk)) | BPWM0_CH4_PE6 /*!< Set PE6 function to BPWM0_CH4 */ +#define SET_BPWM0_CH4_PF5() SYS->GPF_MFPL = (SYS->GPF_MFPL & (~BPWM0_CH4_PF5_Msk)) | BPWM0_CH4_PF5 /*!< Set PF5 function to BPWM0_CH4 */ +#define SET_BPWM0_CH5_PA5() SYS->GPA_MFPL = (SYS->GPA_MFPL & (~BPWM0_CH5_PA5_Msk)) | BPWM0_CH5_PA5 /*!< Set PA5 function to BPWM0_CH5 */ +#define SET_BPWM0_CH5_PE7() SYS->GPE_MFPL = (SYS->GPE_MFPL & (~BPWM0_CH5_PE7_Msk)) | BPWM0_CH5_PE7 /*!< Set PE7 function to BPWM0_CH5 */ +#define SET_BPWM0_CH5_PF4() SYS->GPF_MFPL = (SYS->GPF_MFPL & (~BPWM0_CH5_PF4_Msk)) | BPWM0_CH5_PF4 /*!< Set PF4 function to BPWM0_CH5 */ +#define SET_BPWM0_CH5_PD12() SYS->GPD_MFPH = (SYS->GPD_MFPH & (~BPWM0_CH5_PD12_Msk)) | BPWM0_CH5_PD12 /*!< Set PD12 function to BPWM0_CH5 */ +#define SET_BPWM0_CH5_PG9() SYS->GPG_MFPH = (SYS->GPG_MFPH & (~BPWM0_CH5_PG9_Msk)) | BPWM0_CH5_PG9 /*!< Set PG9 function to BPWM0_CH5 */ +#define SET_BPWM1_CH0_PB11() SYS->GPB_MFPH = (SYS->GPB_MFPH & (~BPWM1_CH0_PB11_Msk)) | BPWM1_CH0_PB11 /*!< Set PB11 function to BPWM1_CH0 */ +#define SET_BPWM1_CH0_PC7() SYS->GPC_MFPL = (SYS->GPC_MFPL & (~BPWM1_CH0_PC7_Msk)) | BPWM1_CH0_PC7 /*!< Set PC7 function to BPWM1_CH0 */ +#define SET_BPWM1_CH0_PF0() SYS->GPF_MFPL = (SYS->GPF_MFPL & (~BPWM1_CH0_PF0_Msk)) | BPWM1_CH0_PF0 /*!< Set PF0 function to BPWM1_CH0 */ +#define SET_BPWM1_CH0_PF3() SYS->GPF_MFPL = (SYS->GPF_MFPL & (~BPWM1_CH0_PF3_Msk)) | BPWM1_CH0_PF3 /*!< Set PF3 function to BPWM1_CH0 */ +#define SET_BPWM1_CH1_PC6() SYS->GPC_MFPL = (SYS->GPC_MFPL & (~BPWM1_CH1_PC6_Msk)) | BPWM1_CH1_PC6 /*!< Set PC6 function to BPWM1_CH1 */ +#define SET_BPWM1_CH1_PF1() SYS->GPF_MFPL = (SYS->GPF_MFPL & (~BPWM1_CH1_PF1_Msk)) | BPWM1_CH1_PF1 /*!< Set PF1 function to BPWM1_CH1 */ +#define SET_BPWM1_CH1_PF2() SYS->GPF_MFPL = (SYS->GPF_MFPL & (~BPWM1_CH1_PF2_Msk)) | BPWM1_CH1_PF2 /*!< Set PF2 function to BPWM1_CH1 */ +#define SET_BPWM1_CH1_PB10() SYS->GPB_MFPH = (SYS->GPB_MFPH & (~BPWM1_CH1_PB10_Msk)) | BPWM1_CH1_PB10 /*!< Set PB10 function to BPWM1_CH1 */ +#define SET_BPWM1_CH2_PB9() SYS->GPB_MFPH = (SYS->GPB_MFPH & (~BPWM1_CH2_PB9_Msk)) | BPWM1_CH2_PB9 /*!< Set PB9 function to BPWM1_CH2 */ +#define SET_BPWM1_CH2_PA7() SYS->GPA_MFPL = (SYS->GPA_MFPL & (~BPWM1_CH2_PA7_Msk)) | BPWM1_CH2_PA7 /*!< Set PA7 function to BPWM1_CH2 */ +#define SET_BPWM1_CH2_PA12() SYS->GPA_MFPH = (SYS->GPA_MFPH & (~BPWM1_CH2_PA12_Msk)) | BPWM1_CH2_PA12 /*!< Set PA12 function to BPWM1_CH2 */ +#define SET_BPWM1_CH3_PA6() SYS->GPA_MFPL = (SYS->GPA_MFPL & (~BPWM1_CH3_PA6_Msk)) | BPWM1_CH3_PA6 /*!< Set PA6 function to BPWM1_CH3 */ +#define SET_BPWM1_CH3_PA13() SYS->GPA_MFPH = (SYS->GPA_MFPH & (~BPWM1_CH3_PA13_Msk)) | BPWM1_CH3_PA13 /*!< Set PA13 function to BPWM1_CH3 */ +#define SET_BPWM1_CH3_PB8() SYS->GPB_MFPH = (SYS->GPB_MFPH & (~BPWM1_CH3_PB8_Msk)) | BPWM1_CH3_PB8 /*!< Set PB8 function to BPWM1_CH3 */ +#define SET_BPWM1_CH4_PA14() SYS->GPA_MFPH = (SYS->GPA_MFPH & (~BPWM1_CH4_PA14_Msk)) | BPWM1_CH4_PA14 /*!< Set PA14 function to BPWM1_CH4 */ +#define SET_BPWM1_CH4_PC8() SYS->GPC_MFPH = (SYS->GPC_MFPH & (~BPWM1_CH4_PC8_Msk)) | BPWM1_CH4_PC8 /*!< Set PC8 function to BPWM1_CH4 */ +#define SET_BPWM1_CH4_PB7() SYS->GPB_MFPL = (SYS->GPB_MFPL & (~BPWM1_CH4_PB7_Msk)) | BPWM1_CH4_PB7 /*!< Set PB7 function to BPWM1_CH4 */ +#define SET_BPWM1_CH5_PA15() SYS->GPA_MFPH = (SYS->GPA_MFPH & (~BPWM1_CH5_PA15_Msk)) | BPWM1_CH5_PA15 /*!< Set PA15 function to BPWM1_CH5 */ +#define SET_BPWM1_CH5_PB6() SYS->GPB_MFPL = (SYS->GPB_MFPL & (~BPWM1_CH5_PB6_Msk)) | BPWM1_CH5_PB6 /*!< Set PB6 function to BPWM1_CH5 */ +#define SET_BPWM1_CH5_PE13() SYS->GPE_MFPH = (SYS->GPE_MFPH & (~BPWM1_CH5_PE13_Msk)) | BPWM1_CH5_PE13 /*!< Set PE13 function to BPWM1_CH5 */ +#define SET_CAN0_RXD_PA13() SYS->GPA_MFPH = (SYS->GPA_MFPH & (~CAN0_RXD_PA13_Msk)) | CAN0_RXD_PA13 /*!< Set PA13 function to CAN0_RXD */ +#define SET_CAN0_RXD_PD10() SYS->GPD_MFPH = (SYS->GPD_MFPH & (~CAN0_RXD_PD10_Msk)) | CAN0_RXD_PD10 /*!< Set PD10 function to CAN0_RXD */ +#define SET_CAN0_RXD_PA4() SYS->GPA_MFPL = (SYS->GPA_MFPL & (~CAN0_RXD_PA4_Msk)) | CAN0_RXD_PA4 /*!< Set PA4 function to CAN0_RXD */ +#define SET_CAN0_RXD_PC4() SYS->GPC_MFPL = (SYS->GPC_MFPL & (~CAN0_RXD_PC4_Msk)) | CAN0_RXD_PC4 /*!< Set PC4 function to CAN0_RXD */ +#define SET_CAN0_RXD_PB10() SYS->GPB_MFPH = (SYS->GPB_MFPH & (~CAN0_RXD_PB10_Msk)) | CAN0_RXD_PB10 /*!< Set PB10 function to CAN0_RXD */ +#define SET_CAN0_RXD_PE15() SYS->GPE_MFPH = (SYS->GPE_MFPH & (~CAN0_RXD_PE15_Msk)) | CAN0_RXD_PE15 /*!< Set PE15 function to CAN0_RXD */ +#define SET_CAN0_TXD_PD11() SYS->GPD_MFPH = (SYS->GPD_MFPH & (~CAN0_TXD_PD11_Msk)) | CAN0_TXD_PD11 /*!< Set PD11 function to CAN0_TXD */ +#define SET_CAN0_TXD_PC5() SYS->GPC_MFPL = (SYS->GPC_MFPL & (~CAN0_TXD_PC5_Msk)) | CAN0_TXD_PC5 /*!< Set PC5 function to CAN0_TXD */ +#define SET_CAN0_TXD_PB11() SYS->GPB_MFPH = (SYS->GPB_MFPH & (~CAN0_TXD_PB11_Msk)) | CAN0_TXD_PB11 /*!< Set PB11 function to CAN0_TXD */ +#define SET_CAN0_TXD_PA12() SYS->GPA_MFPH = (SYS->GPA_MFPH & (~CAN0_TXD_PA12_Msk)) | CAN0_TXD_PA12 /*!< Set PA12 function to CAN0_TXD */ +#define SET_CAN0_TXD_PE14() SYS->GPE_MFPH = (SYS->GPE_MFPH & (~CAN0_TXD_PE14_Msk)) | CAN0_TXD_PE14 /*!< Set PE14 function to CAN0_TXD */ +#define SET_CAN0_TXD_PA5() SYS->GPA_MFPL = (SYS->GPA_MFPL & (~CAN0_TXD_PA5_Msk)) | CAN0_TXD_PA5 /*!< Set PA5 function to CAN0_TXD */ +#define SET_CLKO_PC13() SYS->GPC_MFPH = (SYS->GPC_MFPH & (~CLKO_PC13_Msk)) | CLKO_PC13 /*!< Set PC13 function to CLKO */ +#define SET_CLKO_PB14() SYS->GPB_MFPH = (SYS->GPB_MFPH & (~CLKO_PB14_Msk)) | CLKO_PB14 /*!< Set PB14 function to CLKO */ +#define SET_CLKO_PD12() SYS->GPD_MFPH = (SYS->GPD_MFPH & (~CLKO_PD12_Msk)) | CLKO_PD12 /*!< Set PD12 function to CLKO */ +#define SET_CLKO_PG15() SYS->GPG_MFPH = (SYS->GPG_MFPH & (~CLKO_PG15_Msk)) | CLKO_PG15 /*!< Set PG15 function to CLKO */ +#define SET_DAC0_OUT_PB12() SYS->GPB_MFPH = (SYS->GPB_MFPH & (~DAC0_OUT_PB12_Msk)) | DAC0_OUT_PB12 /*!< Set PB12 function to DAC0_OUT */ +#define SET_DAC0_OUT_PB12() SYS->GPB_MFPH = (SYS->GPB_MFPH & (~DAC0_OUT_PB12_Msk)) | DAC0_OUT_PB12 /*!< Set PB12 function to DAC0_OUT */ +#define SET_DAC0_ST_PA0() SYS->GPA_MFPL = (SYS->GPA_MFPL & (~DAC0_ST_PA0_Msk)) | DAC0_ST_PA0 /*!< Set PA0 function to DAC0_ST */ +#define SET_DAC0_ST_PA10() SYS->GPA_MFPH = (SYS->GPA_MFPH & (~DAC0_ST_PA10_Msk)) | DAC0_ST_PA10 /*!< Set PA10 function to DAC0_ST */ +#define SET_DAC1_OUT_PB13() SYS->GPB_MFPH = (SYS->GPB_MFPH & (~DAC1_OUT_PB13_Msk)) | DAC1_OUT_PB13 /*!< Set PB13 function to DAC1_OUT */ +#define SET_DAC1_OUT_PB13() SYS->GPB_MFPH = (SYS->GPB_MFPH & (~DAC1_OUT_PB13_Msk)) | DAC1_OUT_PB13 /*!< Set PB13 function to DAC1_OUT */ +#define SET_DAC1_ST_PA1() SYS->GPA_MFPL = (SYS->GPA_MFPL & (~DAC1_ST_PA1_Msk)) | DAC1_ST_PA1 /*!< Set PA1 function to DAC1_ST */ +#define SET_DAC1_ST_PA11() SYS->GPA_MFPH = (SYS->GPA_MFPH & (~DAC1_ST_PA11_Msk)) | DAC1_ST_PA11 /*!< Set PA11 function to DAC1_ST */ +#define SET_EADC0_CH0_PB0() SYS->GPB_MFPL = (SYS->GPB_MFPL & (~EADC0_CH0_PB0_Msk)) | EADC0_CH0_PB0 /*!< Set PB0 function to EADC0_CH0 */ +#define SET_EADC0_CH1_PB1() SYS->GPB_MFPL = (SYS->GPB_MFPL & (~EADC0_CH1_PB1_Msk)) | EADC0_CH1_PB1 /*!< Set PB1 function to EADC0_CH1 */ +#define SET_EADC0_CH10_PB10() SYS->GPB_MFPH = (SYS->GPB_MFPH & (~EADC0_CH10_PB10_Msk)) | EADC0_CH10_PB10 /*!< Set PB10 function to EADC0_CH10 */ +#define SET_EADC0_CH11_PB11() SYS->GPB_MFPH = (SYS->GPB_MFPH & (~EADC0_CH11_PB11_Msk)) | EADC0_CH11_PB11 /*!< Set PB11 function to EADC0_CH11 */ +#define SET_EADC0_CH12_PB12() SYS->GPB_MFPH = (SYS->GPB_MFPH & (~EADC0_CH12_PB12_Msk)) | EADC0_CH12_PB12 /*!< Set PB12 function to EADC0_CH12 */ +#define SET_EADC0_CH13_PB13() SYS->GPB_MFPH = (SYS->GPB_MFPH & (~EADC0_CH13_PB13_Msk)) | EADC0_CH13_PB13 /*!< Set PB13 function to EADC0_CH13 */ +#define SET_EADC0_CH14_PB14() SYS->GPB_MFPH = (SYS->GPB_MFPH & (~EADC0_CH14_PB14_Msk)) | EADC0_CH14_PB14 /*!< Set PB14 function to EADC0_CH14 */ +#define SET_EADC0_CH15_PB15() SYS->GPB_MFPH = (SYS->GPB_MFPH & (~EADC0_CH15_PB15_Msk)) | EADC0_CH15_PB15 /*!< Set PB15 function to EADC0_CH15 */ +#define SET_EADC0_CH15_PD10() SYS->GPD_MFPH = (SYS->GPD_MFPH & (~EADC0_CH15_PD10_Msk)) | EADC0_CH15_PD10 /*!< Set PD10 function to EADC0_CH15 */ +#define SET_EADC0_CH2_PB2() SYS->GPB_MFPL = (SYS->GPB_MFPL & (~EADC0_CH2_PB2_Msk)) | EADC0_CH2_PB2 /*!< Set PB2 function to EADC0_CH2 */ +#define SET_EADC0_CH3_PB3() SYS->GPB_MFPL = (SYS->GPB_MFPL & (~EADC0_CH3_PB3_Msk)) | EADC0_CH3_PB3 /*!< Set PB3 function to EADC0_CH3 */ +#define SET_EADC0_CH4_PB4() SYS->GPB_MFPL = (SYS->GPB_MFPL & (~EADC0_CH4_PB4_Msk)) | EADC0_CH4_PB4 /*!< Set PB4 function to EADC0_CH4 */ +#define SET_EADC0_CH5_PB5() SYS->GPB_MFPL = (SYS->GPB_MFPL & (~EADC0_CH5_PB5_Msk)) | EADC0_CH5_PB5 /*!< Set PB5 function to EADC0_CH5 */ +#define SET_EADC0_CH6_PB6() SYS->GPB_MFPL = (SYS->GPB_MFPL & (~EADC0_CH6_PB6_Msk)) | EADC0_CH6_PB6 /*!< Set PB6 function to EADC0_CH6 */ +#define SET_EADC0_CH7_PB7() SYS->GPB_MFPL = (SYS->GPB_MFPL & (~EADC0_CH7_PB7_Msk)) | EADC0_CH7_PB7 /*!< Set PB7 function to EADC0_CH7 */ +#define SET_EADC0_CH8_PB8() SYS->GPB_MFPH = (SYS->GPB_MFPH & (~EADC0_CH8_PB8_Msk)) | EADC0_CH8_PB8 /*!< Set PB8 function to EADC0_CH8 */ +#define SET_EADC0_CH9_PB9() SYS->GPB_MFPH = (SYS->GPB_MFPH & (~EADC0_CH9_PB9_Msk)) | EADC0_CH9_PB9 /*!< Set PB9 function to EADC0_CH9 */ +#define SET_EADC0_ST_PF5() SYS->GPF_MFPL = (SYS->GPF_MFPL & (~EADC0_ST_PF5_Msk)) | EADC0_ST_PF5 /*!< Set PF5 function to EADC0_ST */ +#define SET_EADC0_ST_PC13() SYS->GPC_MFPH = (SYS->GPC_MFPH & (~EADC0_ST_PC13_Msk)) | EADC0_ST_PC13 /*!< Set PC13 function to EADC0_ST */ +#define SET_EADC0_ST_PC1() SYS->GPC_MFPL = (SYS->GPC_MFPL & (~EADC0_ST_PC1_Msk)) | EADC0_ST_PC1 /*!< Set PC1 function to EADC0_ST */ +#define SET_EADC0_ST_PD12() SYS->GPD_MFPH = (SYS->GPD_MFPH & (~EADC0_ST_PD12_Msk)) | EADC0_ST_PD12 /*!< Set PD12 function to EADC0_ST */ +#define SET_EADC0_ST_PG15() SYS->GPG_MFPH = (SYS->GPG_MFPH & (~EADC0_ST_PG15_Msk)) | EADC0_ST_PG15 /*!< Set PG15 function to EADC0_ST */ +#define SET_EBI_AD0_PC0() SYS->GPC_MFPL = (SYS->GPC_MFPL & (~EBI_AD0_PC0_Msk)) | EBI_AD0_PC0 /*!< Set PC0 function to EBI_AD0 */ +#define SET_EBI_AD0_PG9() SYS->GPG_MFPH = (SYS->GPG_MFPH & (~EBI_AD0_PG9_Msk)) | EBI_AD0_PG9 /*!< Set PG9 function to EBI_AD0 */ +#define SET_EBI_AD1_PG10() SYS->GPG_MFPH = (SYS->GPG_MFPH & (~EBI_AD1_PG10_Msk)) | EBI_AD1_PG10 /*!< Set PG10 function to EBI_AD1 */ +#define SET_EBI_AD1_PC1() SYS->GPC_MFPL = (SYS->GPC_MFPL & (~EBI_AD1_PC1_Msk)) | EBI_AD1_PC1 /*!< Set PC1 function to EBI_AD1 */ +#define SET_EBI_AD10_PE1() SYS->GPE_MFPL = (SYS->GPE_MFPL & (~EBI_AD10_PE1_Msk)) | EBI_AD10_PE1 /*!< Set PE1 function to EBI_AD10 */ +#define SET_EBI_AD10_PD3() SYS->GPD_MFPL = (SYS->GPD_MFPL & (~EBI_AD10_PD3_Msk)) | EBI_AD10_PD3 /*!< Set PD3 function to EBI_AD10 */ +#define SET_EBI_AD10_PD13() SYS->GPD_MFPH = (SYS->GPD_MFPH & (~EBI_AD10_PD13_Msk)) | EBI_AD10_PD13 /*!< Set PD13 function to EBI_AD10 */ +#define SET_EBI_AD11_PE0() SYS->GPE_MFPL = (SYS->GPE_MFPL & (~EBI_AD11_PE0_Msk)) | EBI_AD11_PE0 /*!< Set PE0 function to EBI_AD11 */ +#define SET_EBI_AD11_PD2() SYS->GPD_MFPL = (SYS->GPD_MFPL & (~EBI_AD11_PD2_Msk)) | EBI_AD11_PD2 /*!< Set PD2 function to EBI_AD11 */ +#define SET_EBI_AD12_PD1() SYS->GPD_MFPL = (SYS->GPD_MFPL & (~EBI_AD12_PD1_Msk)) | EBI_AD12_PD1 /*!< Set PD1 function to EBI_AD12 */ +#define SET_EBI_AD12_PB15() SYS->GPB_MFPH = (SYS->GPB_MFPH & (~EBI_AD12_PB15_Msk)) | EBI_AD12_PB15 /*!< Set PB15 function to EBI_AD12 */ +#define SET_EBI_AD12_PH8() SYS->GPH_MFPH = (SYS->GPH_MFPH & (~EBI_AD12_PH8_Msk)) | EBI_AD12_PH8 /*!< Set PH8 function to EBI_AD12 */ +#define SET_EBI_AD13_PD0() SYS->GPD_MFPL = (SYS->GPD_MFPL & (~EBI_AD13_PD0_Msk)) | EBI_AD13_PD0 /*!< Set PD0 function to EBI_AD13 */ +#define SET_EBI_AD13_PB14() SYS->GPB_MFPH = (SYS->GPB_MFPH & (~EBI_AD13_PB14_Msk)) | EBI_AD13_PB14 /*!< Set PB14 function to EBI_AD13 */ +#define SET_EBI_AD13_PH9() SYS->GPH_MFPH = (SYS->GPH_MFPH & (~EBI_AD13_PH9_Msk)) | EBI_AD13_PH9 /*!< Set PH9 function to EBI_AD13 */ +#define SET_EBI_AD14_PB13() SYS->GPB_MFPH = (SYS->GPB_MFPH & (~EBI_AD14_PB13_Msk)) | EBI_AD14_PB13 /*!< Set PB13 function to EBI_AD14 */ +#define SET_EBI_AD14_PH10() SYS->GPH_MFPH = (SYS->GPH_MFPH & (~EBI_AD14_PH10_Msk)) | EBI_AD14_PH10 /*!< Set PH10 function to EBI_AD14 */ +#define SET_EBI_AD15_PB12() SYS->GPB_MFPH = (SYS->GPB_MFPH & (~EBI_AD15_PB12_Msk)) | EBI_AD15_PB12 /*!< Set PB12 function to EBI_AD15 */ +#define SET_EBI_AD15_PH11() SYS->GPH_MFPH = (SYS->GPH_MFPH & (~EBI_AD15_PH11_Msk)) | EBI_AD15_PH11 /*!< Set PH11 function to EBI_AD15 */ +#define SET_EBI_AD2_PC2() SYS->GPC_MFPL = (SYS->GPC_MFPL & (~EBI_AD2_PC2_Msk)) | EBI_AD2_PC2 /*!< Set PC2 function to EBI_AD2 */ +#define SET_EBI_AD2_PG11() SYS->GPG_MFPH = (SYS->GPG_MFPH & (~EBI_AD2_PG11_Msk)) | EBI_AD2_PG11 /*!< Set PG11 function to EBI_AD2 */ +#define SET_EBI_AD3_PG12() SYS->GPG_MFPH = (SYS->GPG_MFPH & (~EBI_AD3_PG12_Msk)) | EBI_AD3_PG12 /*!< Set PG12 function to EBI_AD3 */ +#define SET_EBI_AD3_PC3() SYS->GPC_MFPL = (SYS->GPC_MFPL & (~EBI_AD3_PC3_Msk)) | EBI_AD3_PC3 /*!< Set PC3 function to EBI_AD3 */ +#define SET_EBI_AD4_PC4() SYS->GPC_MFPL = (SYS->GPC_MFPL & (~EBI_AD4_PC4_Msk)) | EBI_AD4_PC4 /*!< Set PC4 function to EBI_AD4 */ +#define SET_EBI_AD4_PG13() SYS->GPG_MFPH = (SYS->GPG_MFPH & (~EBI_AD4_PG13_Msk)) | EBI_AD4_PG13 /*!< Set PG13 function to EBI_AD4 */ +#define SET_EBI_AD5_PG14() SYS->GPG_MFPH = (SYS->GPG_MFPH & (~EBI_AD5_PG14_Msk)) | EBI_AD5_PG14 /*!< Set PG14 function to EBI_AD5 */ +#define SET_EBI_AD5_PC5() SYS->GPC_MFPL = (SYS->GPC_MFPL & (~EBI_AD5_PC5_Msk)) | EBI_AD5_PC5 /*!< Set PC5 function to EBI_AD5 */ +#define SET_EBI_AD6_PD8() SYS->GPD_MFPH = (SYS->GPD_MFPH & (~EBI_AD6_PD8_Msk)) | EBI_AD6_PD8 /*!< Set PD8 function to EBI_AD6 */ +#define SET_EBI_AD6_PA6() SYS->GPA_MFPL = (SYS->GPA_MFPL & (~EBI_AD6_PA6_Msk)) | EBI_AD6_PA6 /*!< Set PA6 function to EBI_AD6 */ +#define SET_EBI_AD7_PD9() SYS->GPD_MFPH = (SYS->GPD_MFPH & (~EBI_AD7_PD9_Msk)) | EBI_AD7_PD9 /*!< Set PD9 function to EBI_AD7 */ +#define SET_EBI_AD7_PA7() SYS->GPA_MFPL = (SYS->GPA_MFPL & (~EBI_AD7_PA7_Msk)) | EBI_AD7_PA7 /*!< Set PA7 function to EBI_AD7 */ +#define SET_EBI_AD8_PE14() SYS->GPE_MFPH = (SYS->GPE_MFPH & (~EBI_AD8_PE14_Msk)) | EBI_AD8_PE14 /*!< Set PE14 function to EBI_AD8 */ +#define SET_EBI_AD8_PC6() SYS->GPC_MFPL = (SYS->GPC_MFPL & (~EBI_AD8_PC6_Msk)) | EBI_AD8_PC6 /*!< Set PC6 function to EBI_AD8 */ +#define SET_EBI_AD9_PC7() SYS->GPC_MFPL = (SYS->GPC_MFPL & (~EBI_AD9_PC7_Msk)) | EBI_AD9_PC7 /*!< Set PC7 function to EBI_AD9 */ +#define SET_EBI_AD9_PE15() SYS->GPE_MFPH = (SYS->GPE_MFPH & (~EBI_AD9_PE15_Msk)) | EBI_AD9_PE15 /*!< Set PE15 function to EBI_AD9 */ +#define SET_EBI_ADR0_PB5() SYS->GPB_MFPL = (SYS->GPB_MFPL & (~EBI_ADR0_PB5_Msk)) | EBI_ADR0_PB5 /*!< Set PB5 function to EBI_ADR0 */ +#define SET_EBI_ADR0_PH7() SYS->GPH_MFPL = (SYS->GPH_MFPL & (~EBI_ADR0_PH7_Msk)) | EBI_ADR0_PH7 /*!< Set PH7 function to EBI_ADR0 */ +#define SET_EBI_ADR1_PH6() SYS->GPH_MFPL = (SYS->GPH_MFPL & (~EBI_ADR1_PH6_Msk)) | EBI_ADR1_PH6 /*!< Set PH6 function to EBI_ADR1 */ +#define SET_EBI_ADR1_PB4() SYS->GPB_MFPL = (SYS->GPB_MFPL & (~EBI_ADR1_PB4_Msk)) | EBI_ADR1_PB4 /*!< Set PB4 function to EBI_ADR1 */ +#define SET_EBI_ADR10_PC13() SYS->GPC_MFPH = (SYS->GPC_MFPH & (~EBI_ADR10_PC13_Msk)) | EBI_ADR10_PC13 /*!< Set PC13 function to EBI_ADR10 */ +#define SET_EBI_ADR10_PE8() SYS->GPE_MFPH = (SYS->GPE_MFPH & (~EBI_ADR10_PE8_Msk)) | EBI_ADR10_PE8 /*!< Set PE8 function to EBI_ADR10 */ +#define SET_EBI_ADR11_PE9() SYS->GPE_MFPH = (SYS->GPE_MFPH & (~EBI_ADR11_PE9_Msk)) | EBI_ADR11_PE9 /*!< Set PE9 function to EBI_ADR11 */ +#define SET_EBI_ADR11_PG2() SYS->GPG_MFPL = (SYS->GPG_MFPL & (~EBI_ADR11_PG2_Msk)) | EBI_ADR11_PG2 /*!< Set PG2 function to EBI_ADR11 */ +#define SET_EBI_ADR12_PE10() SYS->GPE_MFPH = (SYS->GPE_MFPH & (~EBI_ADR12_PE10_Msk)) | EBI_ADR12_PE10 /*!< Set PE10 function to EBI_ADR12 */ +#define SET_EBI_ADR12_PG3() SYS->GPG_MFPL = (SYS->GPG_MFPL & (~EBI_ADR12_PG3_Msk)) | EBI_ADR12_PG3 /*!< Set PG3 function to EBI_ADR12 */ +#define SET_EBI_ADR13_PE11() SYS->GPE_MFPH = (SYS->GPE_MFPH & (~EBI_ADR13_PE11_Msk)) | EBI_ADR13_PE11 /*!< Set PE11 function to EBI_ADR13 */ +#define SET_EBI_ADR13_PG4() SYS->GPG_MFPL = (SYS->GPG_MFPL & (~EBI_ADR13_PG4_Msk)) | EBI_ADR13_PG4 /*!< Set PG4 function to EBI_ADR13 */ +#define SET_EBI_ADR14_PF11() SYS->GPF_MFPH = (SYS->GPF_MFPH & (~EBI_ADR14_PF11_Msk)) | EBI_ADR14_PF11 /*!< Set PF11 function to EBI_ADR14 */ +#define SET_EBI_ADR14_PE12() SYS->GPE_MFPH = (SYS->GPE_MFPH & (~EBI_ADR14_PE12_Msk)) | EBI_ADR14_PE12 /*!< Set PE12 function to EBI_ADR14 */ +#define SET_EBI_ADR15_PE13() SYS->GPE_MFPH = (SYS->GPE_MFPH & (~EBI_ADR15_PE13_Msk)) | EBI_ADR15_PE13 /*!< Set PE13 function to EBI_ADR15 */ +#define SET_EBI_ADR15_PF10() SYS->GPF_MFPH = (SYS->GPF_MFPH & (~EBI_ADR15_PF10_Msk)) | EBI_ADR15_PF10 /*!< Set PF10 function to EBI_ADR15 */ +#define SET_EBI_ADR16_PC8() SYS->GPC_MFPH = (SYS->GPC_MFPH & (~EBI_ADR16_PC8_Msk)) | EBI_ADR16_PC8 /*!< Set PC8 function to EBI_ADR16 */ +#define SET_EBI_ADR16_PF9() SYS->GPF_MFPH = (SYS->GPF_MFPH & (~EBI_ADR16_PF9_Msk)) | EBI_ADR16_PF9 /*!< Set PF9 function to EBI_ADR16 */ +#define SET_EBI_ADR16_PB11() SYS->GPB_MFPH = (SYS->GPB_MFPH & (~EBI_ADR16_PB11_Msk)) | EBI_ADR16_PB11 /*!< Set PB11 function to EBI_ADR16 */ +#define SET_EBI_ADR17_PB10() SYS->GPB_MFPH = (SYS->GPB_MFPH & (~EBI_ADR17_PB10_Msk)) | EBI_ADR17_PB10 /*!< Set PB10 function to EBI_ADR17 */ +#define SET_EBI_ADR17_PF8() SYS->GPF_MFPH = (SYS->GPF_MFPH & (~EBI_ADR17_PF8_Msk)) | EBI_ADR17_PF8 /*!< Set PF8 function to EBI_ADR17 */ +#define SET_EBI_ADR18_PF7() SYS->GPF_MFPL = (SYS->GPF_MFPL & (~EBI_ADR18_PF7_Msk)) | EBI_ADR18_PF7 /*!< Set PF7 function to EBI_ADR18 */ +#define SET_EBI_ADR18_PB9() SYS->GPB_MFPH = (SYS->GPB_MFPH & (~EBI_ADR18_PB9_Msk)) | EBI_ADR18_PB9 /*!< Set PB9 function to EBI_ADR18 */ +#define SET_EBI_ADR19_PB8() SYS->GPB_MFPH = (SYS->GPB_MFPH & (~EBI_ADR19_PB8_Msk)) | EBI_ADR19_PB8 /*!< Set PB8 function to EBI_ADR19 */ +#define SET_EBI_ADR19_PF6() SYS->GPF_MFPL = (SYS->GPF_MFPL & (~EBI_ADR19_PF6_Msk)) | EBI_ADR19_PF6 /*!< Set PF6 function to EBI_ADR19 */ +#define SET_EBI_ADR2_PB3() SYS->GPB_MFPL = (SYS->GPB_MFPL & (~EBI_ADR2_PB3_Msk)) | EBI_ADR2_PB3 /*!< Set PB3 function to EBI_ADR2 */ +#define SET_EBI_ADR2_PH5() SYS->GPH_MFPL = (SYS->GPH_MFPL & (~EBI_ADR2_PH5_Msk)) | EBI_ADR2_PH5 /*!< Set PH5 function to EBI_ADR2 */ +#define SET_EBI_ADR3_PH4() SYS->GPH_MFPL = (SYS->GPH_MFPL & (~EBI_ADR3_PH4_Msk)) | EBI_ADR3_PH4 /*!< Set PH4 function to EBI_ADR3 */ +#define SET_EBI_ADR3_PB2() SYS->GPB_MFPL = (SYS->GPB_MFPL & (~EBI_ADR3_PB2_Msk)) | EBI_ADR3_PB2 /*!< Set PB2 function to EBI_ADR3 */ +#define SET_EBI_ADR4_PC12() SYS->GPC_MFPH = (SYS->GPC_MFPH & (~EBI_ADR4_PC12_Msk)) | EBI_ADR4_PC12 /*!< Set PC12 function to EBI_ADR4 */ +#define SET_EBI_ADR5_PC11() SYS->GPC_MFPH = (SYS->GPC_MFPH & (~EBI_ADR5_PC11_Msk)) | EBI_ADR5_PC11 /*!< Set PC11 function to EBI_ADR5 */ +#define SET_EBI_ADR6_PC10() SYS->GPC_MFPH = (SYS->GPC_MFPH & (~EBI_ADR6_PC10_Msk)) | EBI_ADR6_PC10 /*!< Set PC10 function to EBI_ADR6 */ +#define SET_EBI_ADR7_PC9() SYS->GPC_MFPH = (SYS->GPC_MFPH & (~EBI_ADR7_PC9_Msk)) | EBI_ADR7_PC9 /*!< Set PC9 function to EBI_ADR7 */ +#define SET_EBI_ADR8_PB1() SYS->GPB_MFPL = (SYS->GPB_MFPL & (~EBI_ADR8_PB1_Msk)) | EBI_ADR8_PB1 /*!< Set PB1 function to EBI_ADR8 */ +#define SET_EBI_ADR9_PB0() SYS->GPB_MFPL = (SYS->GPB_MFPL & (~EBI_ADR9_PB0_Msk)) | EBI_ADR9_PB0 /*!< Set PB0 function to EBI_ADR9 */ +#define SET_EBI_ALE_PE2() SYS->GPE_MFPL = (SYS->GPE_MFPL & (~EBI_ALE_PE2_Msk)) | EBI_ALE_PE2 /*!< Set PE2 function to EBI_ALE */ +#define SET_EBI_ALE_PA8() SYS->GPA_MFPH = (SYS->GPA_MFPH & (~EBI_ALE_PA8_Msk)) | EBI_ALE_PA8 /*!< Set PA8 function to EBI_ALE */ +#define SET_EBI_MCLK_PA9() SYS->GPA_MFPH = (SYS->GPA_MFPH & (~EBI_MCLK_PA9_Msk)) | EBI_MCLK_PA9 /*!< Set PA9 function to EBI_MCLK */ +#define SET_EBI_MCLK_PE3() SYS->GPE_MFPL = (SYS->GPE_MFPL & (~EBI_MCLK_PE3_Msk)) | EBI_MCLK_PE3 /*!< Set PE3 function to EBI_MCLK */ +#define SET_EBI_nCS0_PD12() SYS->GPD_MFPH = (SYS->GPD_MFPH & (~EBI_nCS0_PD12_Msk)) | EBI_nCS0_PD12 /*!< Set PD12 function to EBI_nCS0 */ +#define SET_EBI_nCS0_PD14() SYS->GPD_MFPH = (SYS->GPD_MFPH & (~EBI_nCS0_PD14_Msk)) | EBI_nCS0_PD14 /*!< Set PD14 function to EBI_nCS0 */ +#define SET_EBI_nCS0_PF3() SYS->GPF_MFPL = (SYS->GPF_MFPL & (~EBI_nCS0_PF3_Msk)) | EBI_nCS0_PF3 /*!< Set PF3 function to EBI_nCS0 */ +#define SET_EBI_nCS0_PB7() SYS->GPB_MFPL = (SYS->GPB_MFPL & (~EBI_nCS0_PB7_Msk)) | EBI_nCS0_PB7 /*!< Set PB7 function to EBI_nCS0 */ +#define SET_EBI_nCS0_PF6() SYS->GPF_MFPL = (SYS->GPF_MFPL & (~EBI_nCS0_PF6_Msk)) | EBI_nCS0_PF6 /*!< Set PF6 function to EBI_nCS0 */ +#define SET_EBI_nCS1_PF2() SYS->GPF_MFPL = (SYS->GPF_MFPL & (~EBI_nCS1_PF2_Msk)) | EBI_nCS1_PF2 /*!< Set PF2 function to EBI_nCS1 */ +#define SET_EBI_nCS1_PB6() SYS->GPB_MFPL = (SYS->GPB_MFPL & (~EBI_nCS1_PB6_Msk)) | EBI_nCS1_PB6 /*!< Set PB6 function to EBI_nCS1 */ +#define SET_EBI_nCS1_PD11() SYS->GPD_MFPH = (SYS->GPD_MFPH & (~EBI_nCS1_PD11_Msk)) | EBI_nCS1_PD11 /*!< Set PD11 function to EBI_nCS1 */ +#define SET_EBI_nCS2_PD10() SYS->GPD_MFPH = (SYS->GPD_MFPH & (~EBI_nCS2_PD10_Msk)) | EBI_nCS2_PD10 /*!< Set PD10 function to EBI_nCS2 */ +#define SET_EBI_nRD_PE5() SYS->GPE_MFPL = (SYS->GPE_MFPL & (~EBI_nRD_PE5_Msk)) | EBI_nRD_PE5 /*!< Set PE5 function to EBI_nRD */ +#define SET_EBI_nRD_PA11() SYS->GPA_MFPH = (SYS->GPA_MFPH & (~EBI_nRD_PA11_Msk)) | EBI_nRD_PA11 /*!< Set PA11 function to EBI_nRD */ +#define SET_EBI_nWR_PE4() SYS->GPE_MFPL = (SYS->GPE_MFPL & (~EBI_nWR_PE4_Msk)) | EBI_nWR_PE4 /*!< Set PE4 function to EBI_nWR */ +#define SET_EBI_nWR_PA10() SYS->GPA_MFPH = (SYS->GPA_MFPH & (~EBI_nWR_PA10_Msk)) | EBI_nWR_PA10 /*!< Set PA10 function to EBI_nWR */ +#define SET_EBI_nWRH_PB6() SYS->GPB_MFPL = (SYS->GPB_MFPL & (~EBI_nWRH_PB6_Msk)) | EBI_nWRH_PB6 /*!< Set PB6 function to EBI_nWRH */ +#define SET_EBI_nWRL_PB7() SYS->GPB_MFPL = (SYS->GPB_MFPL & (~EBI_nWRL_PB7_Msk)) | EBI_nWRL_PB7 /*!< Set PB7 function to EBI_nWRL */ +#define SET_ECAP0_IC0_PE8() SYS->GPE_MFPH = (SYS->GPE_MFPH & (~ECAP0_IC0_PE8_Msk)) | ECAP0_IC0_PE8 /*!< Set PE8 function to ECAP0_IC0 */ +#define SET_ECAP0_IC0_PA10() SYS->GPA_MFPH = (SYS->GPA_MFPH & (~ECAP0_IC0_PA10_Msk)) | ECAP0_IC0_PA10 /*!< Set PA10 function to ECAP0_IC0 */ +#define SET_ECAP0_IC1_PA9() SYS->GPA_MFPH = (SYS->GPA_MFPH & (~ECAP0_IC1_PA9_Msk)) | ECAP0_IC1_PA9 /*!< Set PA9 function to ECAP0_IC1 */ +#define SET_ECAP0_IC1_PE9() SYS->GPE_MFPH = (SYS->GPE_MFPH & (~ECAP0_IC1_PE9_Msk)) | ECAP0_IC1_PE9 /*!< Set PE9 function to ECAP0_IC1 */ +#define SET_ECAP0_IC2_PE10() SYS->GPE_MFPH = (SYS->GPE_MFPH & (~ECAP0_IC2_PE10_Msk)) | ECAP0_IC2_PE10 /*!< Set PE10 function to ECAP0_IC2 */ +#define SET_ECAP0_IC2_PA8() SYS->GPA_MFPH = (SYS->GPA_MFPH & (~ECAP0_IC2_PA8_Msk)) | ECAP0_IC2_PA8 /*!< Set PA8 function to ECAP0_IC2 */ +#define SET_ECAP1_IC0_PE13() SYS->GPE_MFPH = (SYS->GPE_MFPH & (~ECAP1_IC0_PE13_Msk)) | ECAP1_IC0_PE13 /*!< Set PE13 function to ECAP1_IC0 */ +#define SET_ECAP1_IC0_PC10() SYS->GPC_MFPH = (SYS->GPC_MFPH & (~ECAP1_IC0_PC10_Msk)) | ECAP1_IC0_PC10 /*!< Set PC10 function to ECAP1_IC0 */ +#define SET_ECAP1_IC1_PC11() SYS->GPC_MFPH = (SYS->GPC_MFPH & (~ECAP1_IC1_PC11_Msk)) | ECAP1_IC1_PC11 /*!< Set PC11 function to ECAP1_IC1 */ +#define SET_ECAP1_IC1_PE12() SYS->GPE_MFPH = (SYS->GPE_MFPH & (~ECAP1_IC1_PE12_Msk)) | ECAP1_IC1_PE12 /*!< Set PE12 function to ECAP1_IC1 */ +#define SET_ECAP1_IC2_PC12() SYS->GPC_MFPH = (SYS->GPC_MFPH & (~ECAP1_IC2_PC12_Msk)) | ECAP1_IC2_PC12 /*!< Set PC12 function to ECAP1_IC2 */ +#define SET_ECAP1_IC2_PE11() SYS->GPE_MFPH = (SYS->GPE_MFPH & (~ECAP1_IC2_PE11_Msk)) | ECAP1_IC2_PE11 /*!< Set PE11 function to ECAP1_IC2 */ +#define SET_EPWM0_BRAKE0_PE8() SYS->GPE_MFPH = (SYS->GPE_MFPH & (~EPWM0_BRAKE0_PE8_Msk)) | EPWM0_BRAKE0_PE8 /*!< Set PE8 function to EPWM0_BRAKE0 */ +#define SET_EPWM0_BRAKE0_PB1() SYS->GPB_MFPL = (SYS->GPB_MFPL & (~EPWM0_BRAKE0_PB1_Msk)) | EPWM0_BRAKE0_PB1 /*!< Set PB1 function to EPWM0_BRAKE0 */ +#define SET_EPWM0_BRAKE1_PB14() SYS->GPB_MFPH = (SYS->GPB_MFPH & (~EPWM0_BRAKE1_PB14_Msk)) | EPWM0_BRAKE1_PB14 /*!< Set PB14 function to EPWM0_BRAKE1 */ +#define SET_EPWM0_BRAKE1_PE9() SYS->GPE_MFPH = (SYS->GPE_MFPH & (~EPWM0_BRAKE1_PE9_Msk)) | EPWM0_BRAKE1_PE9 /*!< Set PE9 function to EPWM0_BRAKE1 */ +#define SET_EPWM0_BRAKE1_PB0() SYS->GPB_MFPL = (SYS->GPB_MFPL & (~EPWM0_BRAKE1_PB0_Msk)) | EPWM0_BRAKE1_PB0 /*!< Set PB0 function to EPWM0_BRAKE1 */ +#define SET_EPWM0_CH0_PF5() SYS->GPF_MFPL = (SYS->GPF_MFPL & (~EPWM0_CH0_PF5_Msk)) | EPWM0_CH0_PF5 /*!< Set PF5 function to EPWM0_CH0 */ +#define SET_EPWM0_CH0_PA5() SYS->GPA_MFPL = (SYS->GPA_MFPL & (~EPWM0_CH0_PA5_Msk)) | EPWM0_CH0_PA5 /*!< Set PA5 function to EPWM0_CH0 */ +#define SET_EPWM0_CH0_PB5() SYS->GPB_MFPL = (SYS->GPB_MFPL & (~EPWM0_CH0_PB5_Msk)) | EPWM0_CH0_PB5 /*!< Set PB5 function to EPWM0_CH0 */ +#define SET_EPWM0_CH0_PE8() SYS->GPE_MFPH = (SYS->GPE_MFPH & (~EPWM0_CH0_PE8_Msk)) | EPWM0_CH0_PE8 /*!< Set PE8 function to EPWM0_CH0 */ +#define SET_EPWM0_CH0_PE7() SYS->GPE_MFPL = (SYS->GPE_MFPL & (~EPWM0_CH0_PE7_Msk)) | EPWM0_CH0_PE7 /*!< Set PE7 function to EPWM0_CH0 */ +#define SET_EPWM0_CH1_PA4() SYS->GPA_MFPL = (SYS->GPA_MFPL & (~EPWM0_CH1_PA4_Msk)) | EPWM0_CH1_PA4 /*!< Set PA4 function to EPWM0_CH1 */ +#define SET_EPWM0_CH1_PE9() SYS->GPE_MFPH = (SYS->GPE_MFPH & (~EPWM0_CH1_PE9_Msk)) | EPWM0_CH1_PE9 /*!< Set PE9 function to EPWM0_CH1 */ +#define SET_EPWM0_CH1_PE6() SYS->GPE_MFPL = (SYS->GPE_MFPL & (~EPWM0_CH1_PE6_Msk)) | EPWM0_CH1_PE6 /*!< Set PE6 function to EPWM0_CH1 */ +#define SET_EPWM0_CH1_PF4() SYS->GPF_MFPL = (SYS->GPF_MFPL & (~EPWM0_CH1_PF4_Msk)) | EPWM0_CH1_PF4 /*!< Set PF4 function to EPWM0_CH1 */ +#define SET_EPWM0_CH1_PB4() SYS->GPB_MFPL = (SYS->GPB_MFPL & (~EPWM0_CH1_PB4_Msk)) | EPWM0_CH1_PB4 /*!< Set PB4 function to EPWM0_CH1 */ +#define SET_EPWM0_CH2_PE10() SYS->GPE_MFPH = (SYS->GPE_MFPH & (~EPWM0_CH2_PE10_Msk)) | EPWM0_CH2_PE10 /*!< Set PE10 function to EPWM0_CH2 */ +#define SET_EPWM0_CH2_PE5() SYS->GPE_MFPL = (SYS->GPE_MFPL & (~EPWM0_CH2_PE5_Msk)) | EPWM0_CH2_PE5 /*!< Set PE5 function to EPWM0_CH2 */ +#define SET_EPWM0_CH2_PA3() SYS->GPA_MFPL = (SYS->GPA_MFPL & (~EPWM0_CH2_PA3_Msk)) | EPWM0_CH2_PA3 /*!< Set PA3 function to EPWM0_CH2 */ +#define SET_EPWM0_CH2_PB3() SYS->GPB_MFPL = (SYS->GPB_MFPL & (~EPWM0_CH2_PB3_Msk)) | EPWM0_CH2_PB3 /*!< Set PB3 function to EPWM0_CH2 */ +#define SET_EPWM0_CH3_PA2() SYS->GPA_MFPL = (SYS->GPA_MFPL & (~EPWM0_CH3_PA2_Msk)) | EPWM0_CH3_PA2 /*!< Set PA2 function to EPWM0_CH3 */ +#define SET_EPWM0_CH3_PB2() SYS->GPB_MFPL = (SYS->GPB_MFPL & (~EPWM0_CH3_PB2_Msk)) | EPWM0_CH3_PB2 /*!< Set PB2 function to EPWM0_CH3 */ +#define SET_EPWM0_CH3_PE11() SYS->GPE_MFPH = (SYS->GPE_MFPH & (~EPWM0_CH3_PE11_Msk)) | EPWM0_CH3_PE11 /*!< Set PE11 function to EPWM0_CH3 */ +#define SET_EPWM0_CH3_PE4() SYS->GPE_MFPL = (SYS->GPE_MFPL & (~EPWM0_CH3_PE4_Msk)) | EPWM0_CH3_PE4 /*!< Set PE4 function to EPWM0_CH3 */ +#define SET_EPWM0_CH4_PE3() SYS->GPE_MFPL = (SYS->GPE_MFPL & (~EPWM0_CH4_PE3_Msk)) | EPWM0_CH4_PE3 /*!< Set PE3 function to EPWM0_CH4 */ +#define SET_EPWM0_CH4_PD14() SYS->GPD_MFPH = (SYS->GPD_MFPH & (~EPWM0_CH4_PD14_Msk)) | EPWM0_CH4_PD14 /*!< Set PD14 function to EPWM0_CH4 */ +#define SET_EPWM0_CH4_PA1() SYS->GPA_MFPL = (SYS->GPA_MFPL & (~EPWM0_CH4_PA1_Msk)) | EPWM0_CH4_PA1 /*!< Set PA1 function to EPWM0_CH4 */ +#define SET_EPWM0_CH4_PE12() SYS->GPE_MFPH = (SYS->GPE_MFPH & (~EPWM0_CH4_PE12_Msk)) | EPWM0_CH4_PE12 /*!< Set PE12 function to EPWM0_CH4 */ +#define SET_EPWM0_CH4_PB1() SYS->GPB_MFPL = (SYS->GPB_MFPL & (~EPWM0_CH4_PB1_Msk)) | EPWM0_CH4_PB1 /*!< Set PB1 function to EPWM0_CH4 */ +#define SET_EPWM0_CH5_PA0() SYS->GPA_MFPL = (SYS->GPA_MFPL & (~EPWM0_CH5_PA0_Msk)) | EPWM0_CH5_PA0 /*!< Set PA0 function to EPWM0_CH5 */ +#define SET_EPWM0_CH5_PB0() SYS->GPB_MFPL = (SYS->GPB_MFPL & (~EPWM0_CH5_PB0_Msk)) | EPWM0_CH5_PB0 /*!< Set PB0 function to EPWM0_CH5 */ +#define SET_EPWM0_CH5_PE13() SYS->GPE_MFPH = (SYS->GPE_MFPH & (~EPWM0_CH5_PE13_Msk)) | EPWM0_CH5_PE13 /*!< Set PE13 function to EPWM0_CH5 */ +#define SET_EPWM0_CH5_PE2() SYS->GPE_MFPL = (SYS->GPE_MFPL & (~EPWM0_CH5_PE2_Msk)) | EPWM0_CH5_PE2 /*!< Set PE2 function to EPWM0_CH5 */ +#define SET_EPWM0_CH5_PH11() SYS->GPH_MFPH = (SYS->GPH_MFPH & (~EPWM0_CH5_PH11_Msk)) | EPWM0_CH5_PH11 /*!< Set PH11 function to EPWM0_CH5 */ +#define SET_EPWM0_SYNC_IN_PA15() SYS->GPA_MFPH = (SYS->GPA_MFPH & (~EPWM0_SYNC_IN_PA15_Msk)) | EPWM0_SYNC_IN_PA15/*!< Set PA15 function to EPWM0_SYNC_IN */ +#define SET_EPWM0_SYNC_OUT_PA11() SYS->GPA_MFPH = (SYS->GPA_MFPH & (~EPWM0_SYNC_OUT_PA11_Msk)) | EPWM0_SYNC_OUT_PA11/*!< Set PA11 function to EPWM0_SYNC_OUT */ +#define SET_EPWM0_SYNC_OUT_PF5() SYS->GPF_MFPL = (SYS->GPF_MFPL & (~EPWM0_SYNC_OUT_PF5_Msk)) | EPWM0_SYNC_OUT_PF5/*!< Set PF5 function to EPWM0_SYNC_OUT */ +#define SET_EPWM1_BRAKE0_PB7() SYS->GPB_MFPL = (SYS->GPB_MFPL & (~EPWM1_BRAKE0_PB7_Msk)) | EPWM1_BRAKE0_PB7 /*!< Set PB7 function to EPWM1_BRAKE0 */ +#define SET_EPWM1_BRAKE0_PE10() SYS->GPE_MFPH = (SYS->GPE_MFPH & (~EPWM1_BRAKE0_PE10_Msk)) | EPWM1_BRAKE0_PE10 /*!< Set PE10 function to EPWM1_BRAKE0 */ +#define SET_EPWM1_BRAKE1_PB6() SYS->GPB_MFPL = (SYS->GPB_MFPL & (~EPWM1_BRAKE1_PB6_Msk)) | EPWM1_BRAKE1_PB6 /*!< Set PB6 function to EPWM1_BRAKE1 */ +#define SET_EPWM1_BRAKE1_PA3() SYS->GPA_MFPL = (SYS->GPA_MFPL & (~EPWM1_BRAKE1_PA3_Msk)) | EPWM1_BRAKE1_PA3 /*!< Set PA3 function to EPWM1_BRAKE1 */ +#define SET_EPWM1_BRAKE1_PE11() SYS->GPE_MFPH = (SYS->GPE_MFPH & (~EPWM1_BRAKE1_PE11_Msk)) | EPWM1_BRAKE1_PE11 /*!< Set PE11 function to EPWM1_BRAKE1 */ +#define SET_EPWM1_CH0_PE13() SYS->GPE_MFPH = (SYS->GPE_MFPH & (~EPWM1_CH0_PE13_Msk)) | EPWM1_CH0_PE13 /*!< Set PE13 function to EPWM1_CH0 */ +#define SET_EPWM1_CH0_PC12() SYS->GPC_MFPH = (SYS->GPC_MFPH & (~EPWM1_CH0_PC12_Msk)) | EPWM1_CH0_PC12 /*!< Set PC12 function to EPWM1_CH0 */ +#define SET_EPWM1_CH0_PB15() SYS->GPB_MFPH = (SYS->GPB_MFPH & (~EPWM1_CH0_PB15_Msk)) | EPWM1_CH0_PB15 /*!< Set PB15 function to EPWM1_CH0 */ +#define SET_EPWM1_CH0_PC5() SYS->GPC_MFPL = (SYS->GPC_MFPL & (~EPWM1_CH0_PC5_Msk)) | EPWM1_CH0_PC5 /*!< Set PC5 function to EPWM1_CH0 */ +#define SET_EPWM1_CH1_PC8() SYS->GPC_MFPH = (SYS->GPC_MFPH & (~EPWM1_CH1_PC8_Msk)) | EPWM1_CH1_PC8 /*!< Set PC8 function to EPWM1_CH1 */ +#define SET_EPWM1_CH1_PC11() SYS->GPC_MFPH = (SYS->GPC_MFPH & (~EPWM1_CH1_PC11_Msk)) | EPWM1_CH1_PC11 /*!< Set PC11 function to EPWM1_CH1 */ +#define SET_EPWM1_CH1_PB14() SYS->GPB_MFPH = (SYS->GPB_MFPH & (~EPWM1_CH1_PB14_Msk)) | EPWM1_CH1_PB14 /*!< Set PB14 function to EPWM1_CH1 */ +#define SET_EPWM1_CH1_PC4() SYS->GPC_MFPL = (SYS->GPC_MFPL & (~EPWM1_CH1_PC4_Msk)) | EPWM1_CH1_PC4 /*!< Set PC4 function to EPWM1_CH1 */ +#define SET_EPWM1_CH2_PC7() SYS->GPC_MFPL = (SYS->GPC_MFPL & (~EPWM1_CH2_PC7_Msk)) | EPWM1_CH2_PC7 /*!< Set PC7 function to EPWM1_CH2 */ +#define SET_EPWM1_CH2_PC3() SYS->GPC_MFPL = (SYS->GPC_MFPL & (~EPWM1_CH2_PC3_Msk)) | EPWM1_CH2_PC3 /*!< Set PC3 function to EPWM1_CH2 */ +#define SET_EPWM1_CH2_PC10() SYS->GPC_MFPH = (SYS->GPC_MFPH & (~EPWM1_CH2_PC10_Msk)) | EPWM1_CH2_PC10 /*!< Set PC10 function to EPWM1_CH2 */ +#define SET_EPWM1_CH2_PB13() SYS->GPB_MFPH = (SYS->GPB_MFPH & (~EPWM1_CH2_PB13_Msk)) | EPWM1_CH2_PB13 /*!< Set PB13 function to EPWM1_CH2 */ +#define SET_EPWM1_CH3_PC6() SYS->GPC_MFPL = (SYS->GPC_MFPL & (~EPWM1_CH3_PC6_Msk)) | EPWM1_CH3_PC6 /*!< Set PC6 function to EPWM1_CH3 */ +#define SET_EPWM1_CH3_PC2() SYS->GPC_MFPL = (SYS->GPC_MFPL & (~EPWM1_CH3_PC2_Msk)) | EPWM1_CH3_PC2 /*!< Set PC2 function to EPWM1_CH3 */ +#define SET_EPWM1_CH3_PB12() SYS->GPB_MFPH = (SYS->GPB_MFPH & (~EPWM1_CH3_PB12_Msk)) | EPWM1_CH3_PB12 /*!< Set PB12 function to EPWM1_CH3 */ +#define SET_EPWM1_CH3_PC9() SYS->GPC_MFPH = (SYS->GPC_MFPH & (~EPWM1_CH3_PC9_Msk)) | EPWM1_CH3_PC9 /*!< Set PC9 function to EPWM1_CH3 */ +#define SET_EPWM1_CH4_PC1() SYS->GPC_MFPL = (SYS->GPC_MFPL & (~EPWM1_CH4_PC1_Msk)) | EPWM1_CH4_PC1 /*!< Set PC1 function to EPWM1_CH4 */ +#define SET_EPWM1_CH4_PB1() SYS->GPB_MFPL = (SYS->GPB_MFPL & (~EPWM1_CH4_PB1_Msk)) | EPWM1_CH4_PB1 /*!< Set PB1 function to EPWM1_CH4 */ +#define SET_EPWM1_CH4_PB7() SYS->GPB_MFPL = (SYS->GPB_MFPL & (~EPWM1_CH4_PB7_Msk)) | EPWM1_CH4_PB7 /*!< Set PB7 function to EPWM1_CH4 */ +#define SET_EPWM1_CH4_PA7() SYS->GPA_MFPL = (SYS->GPA_MFPL & (~EPWM1_CH4_PA7_Msk)) | EPWM1_CH4_PA7 /*!< Set PA7 function to EPWM1_CH4 */ +#define SET_EPWM1_CH5_PB6() SYS->GPB_MFPL = (SYS->GPB_MFPL & (~EPWM1_CH5_PB6_Msk)) | EPWM1_CH5_PB6 /*!< Set PB6 function to EPWM1_CH5 */ +#define SET_EPWM1_CH5_PC0() SYS->GPC_MFPL = (SYS->GPC_MFPL & (~EPWM1_CH5_PC0_Msk)) | EPWM1_CH5_PC0 /*!< Set PC0 function to EPWM1_CH5 */ +#define SET_EPWM1_CH5_PB0() SYS->GPB_MFPL = (SYS->GPB_MFPL & (~EPWM1_CH5_PB0_Msk)) | EPWM1_CH5_PB0 /*!< Set PB0 function to EPWM1_CH5 */ +#define SET_EPWM1_CH5_PA6() SYS->GPA_MFPL = (SYS->GPA_MFPL & (~EPWM1_CH5_PA6_Msk)) | EPWM1_CH5_PA6 /*!< Set PA6 function to EPWM1_CH5 */ +#define SET_I2C0_SCL_PE13() SYS->GPE_MFPH = (SYS->GPE_MFPH & (~I2C0_SCL_PE13_Msk)) | I2C0_SCL_PE13 /*!< Set PE13 function to I2C0_SCL */ +#define SET_I2C0_SCL_PB9() SYS->GPB_MFPH = (SYS->GPB_MFPH & (~I2C0_SCL_PB9_Msk)) | I2C0_SCL_PB9 /*!< Set PB9 function to I2C0_SCL */ +#define SET_I2C0_SCL_PD7() SYS->GPD_MFPL = (SYS->GPD_MFPL & (~I2C0_SCL_PD7_Msk)) | I2C0_SCL_PD7 /*!< Set PD7 function to I2C0_SCL */ +#define SET_I2C0_SCL_PA5() SYS->GPA_MFPL = (SYS->GPA_MFPL & (~I2C0_SCL_PA5_Msk)) | I2C0_SCL_PA5 /*!< Set PA5 function to I2C0_SCL */ +#define SET_I2C0_SCL_PB5() SYS->GPB_MFPL = (SYS->GPB_MFPL & (~I2C0_SCL_PB5_Msk)) | I2C0_SCL_PB5 /*!< Set PB5 function to I2C0_SCL */ +#define SET_I2C0_SCL_PC1() SYS->GPC_MFPL = (SYS->GPC_MFPL & (~I2C0_SCL_PC1_Msk)) | I2C0_SCL_PC1 /*!< Set PC1 function to I2C0_SCL */ +#define SET_I2C0_SCL_PC12() SYS->GPC_MFPH = (SYS->GPC_MFPH & (~I2C0_SCL_PC12_Msk)) | I2C0_SCL_PC12 /*!< Set PC12 function to I2C0_SCL */ +#define SET_I2C0_SCL_PF3() SYS->GPF_MFPL = (SYS->GPF_MFPL & (~I2C0_SCL_PF3_Msk)) | I2C0_SCL_PF3 /*!< Set PF3 function to I2C0_SCL */ +#define SET_I2C0_SDA_PB4() SYS->GPB_MFPL = (SYS->GPB_MFPL & (~I2C0_SDA_PB4_Msk)) | I2C0_SDA_PB4 /*!< Set PB4 function to I2C0_SDA */ +#define SET_I2C0_SDA_PD6() SYS->GPD_MFPL = (SYS->GPD_MFPL & (~I2C0_SDA_PD6_Msk)) | I2C0_SDA_PD6 /*!< Set PD6 function to I2C0_SDA */ +#define SET_I2C0_SDA_PB8() SYS->GPB_MFPH = (SYS->GPB_MFPH & (~I2C0_SDA_PB8_Msk)) | I2C0_SDA_PB8 /*!< Set PB8 function to I2C0_SDA */ +#define SET_I2C0_SDA_PC11() SYS->GPC_MFPH = (SYS->GPC_MFPH & (~I2C0_SDA_PC11_Msk)) | I2C0_SDA_PC11 /*!< Set PC11 function to I2C0_SDA */ +#define SET_I2C0_SDA_PF2() SYS->GPF_MFPL = (SYS->GPF_MFPL & (~I2C0_SDA_PF2_Msk)) | I2C0_SDA_PF2 /*!< Set PF2 function to I2C0_SDA */ +#define SET_I2C0_SDA_PC0() SYS->GPC_MFPL = (SYS->GPC_MFPL & (~I2C0_SDA_PC0_Msk)) | I2C0_SDA_PC0 /*!< Set PC0 function to I2C0_SDA */ +#define SET_I2C0_SDA_PC8() SYS->GPC_MFPH = (SYS->GPC_MFPH & (~I2C0_SDA_PC8_Msk)) | I2C0_SDA_PC8 /*!< Set PC8 function to I2C0_SDA */ +#define SET_I2C0_SDA_PA4() SYS->GPA_MFPL = (SYS->GPA_MFPL & (~I2C0_SDA_PA4_Msk)) | I2C0_SDA_PA4 /*!< Set PA4 function to I2C0_SDA */ +#define SET_I2C0_SMBAL_PA3() SYS->GPA_MFPL = (SYS->GPA_MFPL & (~I2C0_SMBAL_PA3_Msk)) | I2C0_SMBAL_PA3 /*!< Set PA3 function to I2C0_SMBAL */ +#define SET_I2C0_SMBAL_PG2() SYS->GPG_MFPL = (SYS->GPG_MFPL & (~I2C0_SMBAL_PG2_Msk)) | I2C0_SMBAL_PG2 /*!< Set PG2 function to I2C0_SMBAL */ +#define SET_I2C0_SMBAL_PC3() SYS->GPC_MFPL = (SYS->GPC_MFPL & (~I2C0_SMBAL_PC3_Msk)) | I2C0_SMBAL_PC3 /*!< Set PC3 function to I2C0_SMBAL */ +#define SET_I2C0_SMBSUS_PA2() SYS->GPA_MFPL = (SYS->GPA_MFPL & (~I2C0_SMBSUS_PA2_Msk)) | I2C0_SMBSUS_PA2 /*!< Set PA2 function to I2C0_SMBSUS */ +#define SET_I2C0_SMBSUS_PC2() SYS->GPC_MFPL = (SYS->GPC_MFPL & (~I2C0_SMBSUS_PC2_Msk)) | I2C0_SMBSUS_PC2 /*!< Set PC2 function to I2C0_SMBSUS */ +#define SET_I2C0_SMBSUS_PG3() SYS->GPG_MFPL = (SYS->GPG_MFPL & (~I2C0_SMBSUS_PG3_Msk)) | I2C0_SMBSUS_PG3 /*!< Set PG3 function to I2C0_SMBSUS */ +#define SET_I2C1_SCL_PB1() SYS->GPB_MFPL = (SYS->GPB_MFPL & (~I2C1_SCL_PB1_Msk)) | I2C1_SCL_PB1 /*!< Set PB1 function to I2C1_SCL */ +#define SET_I2C1_SCL_PE1() SYS->GPE_MFPL = (SYS->GPE_MFPL & (~I2C1_SCL_PE1_Msk)) | I2C1_SCL_PE1 /*!< Set PE1 function to I2C1_SCL */ +#define SET_I2C1_SCL_PF0() SYS->GPF_MFPL = (SYS->GPF_MFPL & (~I2C1_SCL_PF0_Msk)) | I2C1_SCL_PF0 /*!< Set PF0 function to I2C1_SCL */ +#define SET_I2C1_SCL_PA12() SYS->GPA_MFPH = (SYS->GPA_MFPH & (~I2C1_SCL_PA12_Msk)) | I2C1_SCL_PA12 /*!< Set PA12 function to I2C1_SCL */ +#define SET_I2C1_SCL_PA7() SYS->GPA_MFPL = (SYS->GPA_MFPL & (~I2C1_SCL_PA7_Msk)) | I2C1_SCL_PA7 /*!< Set PA7 function to I2C1_SCL */ +#define SET_I2C1_SCL_PB11() SYS->GPB_MFPH = (SYS->GPB_MFPH & (~I2C1_SCL_PB11_Msk)) | I2C1_SCL_PB11 /*!< Set PB11 function to I2C1_SCL */ +#define SET_I2C1_SCL_PG2() SYS->GPG_MFPL = (SYS->GPG_MFPL & (~I2C1_SCL_PG2_Msk)) | I2C1_SCL_PG2 /*!< Set PG2 function to I2C1_SCL */ +#define SET_I2C1_SCL_PA3() SYS->GPA_MFPL = (SYS->GPA_MFPL & (~I2C1_SCL_PA3_Msk)) | I2C1_SCL_PA3 /*!< Set PA3 function to I2C1_SCL */ +#define SET_I2C1_SCL_PC5() SYS->GPC_MFPL = (SYS->GPC_MFPL & (~I2C1_SCL_PC5_Msk)) | I2C1_SCL_PC5 /*!< Set PC5 function to I2C1_SCL */ +#define SET_I2C1_SCL_PD5() SYS->GPD_MFPL = (SYS->GPD_MFPL & (~I2C1_SCL_PD5_Msk)) | I2C1_SCL_PD5 /*!< Set PD5 function to I2C1_SCL */ +#define SET_I2C1_SCL_PB3() SYS->GPB_MFPL = (SYS->GPB_MFPL & (~I2C1_SCL_PB3_Msk)) | I2C1_SCL_PB3 /*!< Set PB3 function to I2C1_SCL */ +#define SET_I2C1_SDA_PA2() SYS->GPA_MFPL = (SYS->GPA_MFPL & (~I2C1_SDA_PA2_Msk)) | I2C1_SDA_PA2 /*!< Set PA2 function to I2C1_SDA */ +#define SET_I2C1_SDA_PB10() SYS->GPB_MFPH = (SYS->GPB_MFPH & (~I2C1_SDA_PB10_Msk)) | I2C1_SDA_PB10 /*!< Set PB10 function to I2C1_SDA */ +#define SET_I2C1_SDA_PF1() SYS->GPF_MFPL = (SYS->GPF_MFPL & (~I2C1_SDA_PF1_Msk)) | I2C1_SDA_PF1 /*!< Set PF1 function to I2C1_SDA */ +#define SET_I2C1_SDA_PB2() SYS->GPB_MFPL = (SYS->GPB_MFPL & (~I2C1_SDA_PB2_Msk)) | I2C1_SDA_PB2 /*!< Set PB2 function to I2C1_SDA */ +#define SET_I2C1_SDA_PD4() SYS->GPD_MFPL = (SYS->GPD_MFPL & (~I2C1_SDA_PD4_Msk)) | I2C1_SDA_PD4 /*!< Set PD4 function to I2C1_SDA */ +#define SET_I2C1_SDA_PA13() SYS->GPA_MFPH = (SYS->GPA_MFPH & (~I2C1_SDA_PA13_Msk)) | I2C1_SDA_PA13 /*!< Set PA13 function to I2C1_SDA */ +#define SET_I2C1_SDA_PA6() SYS->GPA_MFPL = (SYS->GPA_MFPL & (~I2C1_SDA_PA6_Msk)) | I2C1_SDA_PA6 /*!< Set PA6 function to I2C1_SDA */ +#define SET_I2C1_SDA_PE0() SYS->GPE_MFPL = (SYS->GPE_MFPL & (~I2C1_SDA_PE0_Msk)) | I2C1_SDA_PE0 /*!< Set PE0 function to I2C1_SDA */ +#define SET_I2C1_SDA_PG3() SYS->GPG_MFPL = (SYS->GPG_MFPL & (~I2C1_SDA_PG3_Msk)) | I2C1_SDA_PG3 /*!< Set PG3 function to I2C1_SDA */ +#define SET_I2C1_SDA_PC4() SYS->GPC_MFPL = (SYS->GPC_MFPL & (~I2C1_SDA_PC4_Msk)) | I2C1_SDA_PC4 /*!< Set PC4 function to I2C1_SDA */ +#define SET_I2C1_SDA_PB0() SYS->GPB_MFPL = (SYS->GPB_MFPL & (~I2C1_SDA_PB0_Msk)) | I2C1_SDA_PB0 /*!< Set PB0 function to I2C1_SDA */ +#define SET_I2C1_SMBAL_PB9() SYS->GPB_MFPH = (SYS->GPB_MFPH & (~I2C1_SMBAL_PB9_Msk)) | I2C1_SMBAL_PB9 /*!< Set PB9 function to I2C1_SMBAL */ +#define SET_I2C1_SMBAL_PH8() SYS->GPH_MFPH = (SYS->GPH_MFPH & (~I2C1_SMBAL_PH8_Msk)) | I2C1_SMBAL_PH8 /*!< Set PH8 function to I2C1_SMBAL */ +#define SET_I2C1_SMBAL_PC7() SYS->GPC_MFPL = (SYS->GPC_MFPL & (~I2C1_SMBAL_PC7_Msk)) | I2C1_SMBAL_PC7 /*!< Set PC7 function to I2C1_SMBAL */ +#define SET_I2C1_SMBSUS_PC6() SYS->GPC_MFPL = (SYS->GPC_MFPL & (~I2C1_SMBSUS_PC6_Msk)) | I2C1_SMBSUS_PC6 /*!< Set PC6 function to I2C1_SMBSUS */ +#define SET_I2C1_SMBSUS_PB8() SYS->GPB_MFPH = (SYS->GPB_MFPH & (~I2C1_SMBSUS_PB8_Msk)) | I2C1_SMBSUS_PB8 /*!< Set PB8 function to I2C1_SMBSUS */ +#define SET_I2C1_SMBSUS_PH9() SYS->GPH_MFPH = (SYS->GPH_MFPH & (~I2C1_SMBSUS_PH9_Msk)) | I2C1_SMBSUS_PH9 /*!< Set PH9 function to I2C1_SMBSUS */ +#define SET_I2C2_SCL_PA14() SYS->GPA_MFPH = (SYS->GPA_MFPH & (~I2C2_SCL_PA14_Msk)) | I2C2_SCL_PA14 /*!< Set PA14 function to I2C2_SCL */ +#define SET_I2C2_SCL_PH8() SYS->GPH_MFPH = (SYS->GPH_MFPH & (~I2C2_SCL_PH8_Msk)) | I2C2_SCL_PH8 /*!< Set PH8 function to I2C2_SCL */ +#define SET_I2C2_SCL_PA11() SYS->GPA_MFPH = (SYS->GPA_MFPH & (~I2C2_SCL_PA11_Msk)) | I2C2_SCL_PA11 /*!< Set PA11 function to I2C2_SCL */ +#define SET_I2C2_SCL_PB13() SYS->GPB_MFPH = (SYS->GPB_MFPH & (~I2C2_SCL_PB13_Msk)) | I2C2_SCL_PB13 /*!< Set PB13 function to I2C2_SCL */ +#define SET_I2C2_SCL_PD9() SYS->GPD_MFPH = (SYS->GPD_MFPH & (~I2C2_SCL_PD9_Msk)) | I2C2_SCL_PD9 /*!< Set PD9 function to I2C2_SCL */ +#define SET_I2C2_SCL_PA1() SYS->GPA_MFPL = (SYS->GPA_MFPL & (~I2C2_SCL_PA1_Msk)) | I2C2_SCL_PA1 /*!< Set PA1 function to I2C2_SCL */ +#define SET_I2C2_SCL_PD1() SYS->GPD_MFPL = (SYS->GPD_MFPL & (~I2C2_SCL_PD1_Msk)) | I2C2_SCL_PD1 /*!< Set PD1 function to I2C2_SCL */ +#define SET_I2C2_SDA_PD8() SYS->GPD_MFPH = (SYS->GPD_MFPH & (~I2C2_SDA_PD8_Msk)) | I2C2_SDA_PD8 /*!< Set PD8 function to I2C2_SDA */ +#define SET_I2C2_SDA_PD0() SYS->GPD_MFPL = (SYS->GPD_MFPL & (~I2C2_SDA_PD0_Msk)) | I2C2_SDA_PD0 /*!< Set PD0 function to I2C2_SDA */ +#define SET_I2C2_SDA_PA15() SYS->GPA_MFPH = (SYS->GPA_MFPH & (~I2C2_SDA_PA15_Msk)) | I2C2_SDA_PA15 /*!< Set PA15 function to I2C2_SDA */ +#define SET_I2C2_SDA_PH9() SYS->GPH_MFPH = (SYS->GPH_MFPH & (~I2C2_SDA_PH9_Msk)) | I2C2_SDA_PH9 /*!< Set PH9 function to I2C2_SDA */ +#define SET_I2C2_SDA_PA10() SYS->GPA_MFPH = (SYS->GPA_MFPH & (~I2C2_SDA_PA10_Msk)) | I2C2_SDA_PA10 /*!< Set PA10 function to I2C2_SDA */ +#define SET_I2C2_SDA_PA0() SYS->GPA_MFPL = (SYS->GPA_MFPL & (~I2C2_SDA_PA0_Msk)) | I2C2_SDA_PA0 /*!< Set PA0 function to I2C2_SDA */ +#define SET_I2C2_SDA_PB12() SYS->GPB_MFPH = (SYS->GPB_MFPH & (~I2C2_SDA_PB12_Msk)) | I2C2_SDA_PB12 /*!< Set PB12 function to I2C2_SDA */ +#define SET_I2C2_SMBAL_PB15() SYS->GPB_MFPH = (SYS->GPB_MFPH & (~I2C2_SMBAL_PB15_Msk)) | I2C2_SMBAL_PB15 /*!< Set PB15 function to I2C2_SMBAL */ +#define SET_I2C2_SMBSUS_PB14() SYS->GPB_MFPH = (SYS->GPB_MFPH & (~I2C2_SMBSUS_PB14_Msk)) | I2C2_SMBSUS_PB14 /*!< Set PB14 function to I2C2_SMBSUS */ +#define SET_I2S0_BCLK_PF10() SYS->GPF_MFPH = (SYS->GPF_MFPH & (~I2S0_BCLK_PF10_Msk)) | I2S0_BCLK_PF10 /*!< Set PF10 function to I2S0_BCLK */ +#define SET_I2S0_BCLK_PB5() SYS->GPB_MFPL = (SYS->GPB_MFPL & (~I2S0_BCLK_PB5_Msk)) | I2S0_BCLK_PB5 /*!< Set PB5 function to I2S0_BCLK */ +#define SET_I2S0_BCLK_PE1() SYS->GPE_MFPL = (SYS->GPE_MFPL & (~I2S0_BCLK_PE1_Msk)) | I2S0_BCLK_PE1 /*!< Set PE1 function to I2S0_BCLK */ +#define SET_I2S0_BCLK_PA12() SYS->GPA_MFPH = (SYS->GPA_MFPH & (~I2S0_BCLK_PA12_Msk)) | I2S0_BCLK_PA12 /*!< Set PA12 function to I2S0_BCLK */ +#define SET_I2S0_BCLK_PC4() SYS->GPC_MFPL = (SYS->GPC_MFPL & (~I2S0_BCLK_PC4_Msk)) | I2S0_BCLK_PC4 /*!< Set PC4 function to I2S0_BCLK */ +#define SET_I2S0_BCLK_PE8() SYS->GPE_MFPH = (SYS->GPE_MFPH & (~I2S0_BCLK_PE8_Msk)) | I2S0_BCLK_PE8 /*!< Set PE8 function to I2S0_BCLK */ +#define SET_I2S0_DI_PC2() SYS->GPC_MFPL = (SYS->GPC_MFPL & (~I2S0_DI_PC2_Msk)) | I2S0_DI_PC2 /*!< Set PC2 function to I2S0_DI */ +#define SET_I2S0_DI_PE10() SYS->GPE_MFPH = (SYS->GPE_MFPH & (~I2S0_DI_PE10_Msk)) | I2S0_DI_PE10 /*!< Set PE10 function to I2S0_DI */ +#define SET_I2S0_DI_PF8() SYS->GPF_MFPH = (SYS->GPF_MFPH & (~I2S0_DI_PF8_Msk)) | I2S0_DI_PF8 /*!< Set PF8 function to I2S0_DI */ +#define SET_I2S0_DI_PH8() SYS->GPH_MFPH = (SYS->GPH_MFPH & (~I2S0_DI_PH8_Msk)) | I2S0_DI_PH8 /*!< Set PH8 function to I2S0_DI */ +#define SET_I2S0_DI_PB3() SYS->GPB_MFPL = (SYS->GPB_MFPL & (~I2S0_DI_PB3_Msk)) | I2S0_DI_PB3 /*!< Set PB3 function to I2S0_DI */ +#define SET_I2S0_DI_PA14() SYS->GPA_MFPH = (SYS->GPA_MFPH & (~I2S0_DI_PA14_Msk)) | I2S0_DI_PA14 /*!< Set PA14 function to I2S0_DI */ +#define SET_I2S0_DO_PH9() SYS->GPH_MFPH = (SYS->GPH_MFPH & (~I2S0_DO_PH9_Msk)) | I2S0_DO_PH9 /*!< Set PH9 function to I2S0_DO */ +#define SET_I2S0_DO_PC1() SYS->GPC_MFPL = (SYS->GPC_MFPL & (~I2S0_DO_PC1_Msk)) | I2S0_DO_PC1 /*!< Set PC1 function to I2S0_DO */ +#define SET_I2S0_DO_PA15() SYS->GPA_MFPH = (SYS->GPA_MFPH & (~I2S0_DO_PA15_Msk)) | I2S0_DO_PA15 /*!< Set PA15 function to I2S0_DO */ +#define SET_I2S0_DO_PB2() SYS->GPB_MFPL = (SYS->GPB_MFPL & (~I2S0_DO_PB2_Msk)) | I2S0_DO_PB2 /*!< Set PB2 function to I2S0_DO */ +#define SET_I2S0_DO_PF7() SYS->GPF_MFPL = (SYS->GPF_MFPL & (~I2S0_DO_PF7_Msk)) | I2S0_DO_PF7 /*!< Set PF7 function to I2S0_DO */ +#define SET_I2S0_DO_PE11() SYS->GPE_MFPH = (SYS->GPE_MFPH & (~I2S0_DO_PE11_Msk)) | I2S0_DO_PE11 /*!< Set PE11 function to I2S0_DO */ +#define SET_I2S0_LRCK_PC0() SYS->GPC_MFPL = (SYS->GPC_MFPL & (~I2S0_LRCK_PC0_Msk)) | I2S0_LRCK_PC0 /*!< Set PC0 function to I2S0_LRCK */ +#define SET_I2S0_LRCK_PB1() SYS->GPB_MFPL = (SYS->GPB_MFPL & (~I2S0_LRCK_PB1_Msk)) | I2S0_LRCK_PB1 /*!< Set PB1 function to I2S0_LRCK */ +#define SET_I2S0_LRCK_PH10() SYS->GPH_MFPH = (SYS->GPH_MFPH & (~I2S0_LRCK_PH10_Msk)) | I2S0_LRCK_PH10 /*!< Set PH10 function to I2S0_LRCK */ +#define SET_I2S0_LRCK_PF6() SYS->GPF_MFPL = (SYS->GPF_MFPL & (~I2S0_LRCK_PF6_Msk)) | I2S0_LRCK_PF6 /*!< Set PF6 function to I2S0_LRCK */ +#define SET_I2S0_LRCK_PE12() SYS->GPE_MFPH = (SYS->GPE_MFPH & (~I2S0_LRCK_PE12_Msk)) | I2S0_LRCK_PE12 /*!< Set PE12 function to I2S0_LRCK */ +#define SET_I2S0_MCLK_PC3() SYS->GPC_MFPL = (SYS->GPC_MFPL & (~I2S0_MCLK_PC3_Msk)) | I2S0_MCLK_PC3 /*!< Set PC3 function to I2S0_MCLK */ +#define SET_I2S0_MCLK_PF9() SYS->GPF_MFPH = (SYS->GPF_MFPH & (~I2S0_MCLK_PF9_Msk)) | I2S0_MCLK_PF9 /*!< Set PF9 function to I2S0_MCLK */ +#define SET_I2S0_MCLK_PE0() SYS->GPE_MFPL = (SYS->GPE_MFPL & (~I2S0_MCLK_PE0_Msk)) | I2S0_MCLK_PE0 /*!< Set PE0 function to I2S0_MCLK */ +#define SET_I2S0_MCLK_PB4() SYS->GPB_MFPL = (SYS->GPB_MFPL & (~I2S0_MCLK_PB4_Msk)) | I2S0_MCLK_PB4 /*!< Set PB4 function to I2S0_MCLK */ +#define SET_I2S0_MCLK_PA13() SYS->GPA_MFPH = (SYS->GPA_MFPH & (~I2S0_MCLK_PA13_Msk)) | I2S0_MCLK_PA13 /*!< Set PA13 function to I2S0_MCLK */ +#define SET_I2S0_MCLK_PE9() SYS->GPE_MFPH = (SYS->GPE_MFPH & (~I2S0_MCLK_PE9_Msk)) | I2S0_MCLK_PE9 /*!< Set PE9 function to I2S0_MCLK */ +#define SET_ICE_CLK_PF1() SYS->GPF_MFPL = (SYS->GPF_MFPL & (~ICE_CLK_PF1_Msk)) | ICE_CLK_PF1 /*!< Set PF1 function to ICE_CLK */ +#define SET_ICE_DAT_PF0() SYS->GPF_MFPL = (SYS->GPF_MFPL & (~ICE_DAT_PF0_Msk)) | ICE_DAT_PF0 /*!< Set PF0 function to ICE_DAT */ +#define SET_INT0_PA6() SYS->GPA_MFPL = (SYS->GPA_MFPL & (~INT0_PA6_Msk)) | INT0_PA6 /*!< Set PA6 function to INT0 */ +#define SET_INT0_PB5() SYS->GPB_MFPL = (SYS->GPB_MFPL & (~INT0_PB5_Msk)) | INT0_PB5 /*!< Set PB5 function to INT0 */ +#define SET_INT1_PB4() SYS->GPB_MFPL = (SYS->GPB_MFPL & (~INT1_PB4_Msk)) | INT1_PB4 /*!< Set PB4 function to INT1 */ +#define SET_INT1_PA7() SYS->GPA_MFPL = (SYS->GPA_MFPL & (~INT1_PA7_Msk)) | INT1_PA7 /*!< Set PA7 function to INT1 */ +#define SET_INT2_PB3() SYS->GPB_MFPL = (SYS->GPB_MFPL & (~INT2_PB3_Msk)) | INT2_PB3 /*!< Set PB3 function to INT2 */ +#define SET_INT2_PC6() SYS->GPC_MFPL = (SYS->GPC_MFPL & (~INT2_PC6_Msk)) | INT2_PC6 /*!< Set PC6 function to INT2 */ +#define SET_INT3_PB2() SYS->GPB_MFPL = (SYS->GPB_MFPL & (~INT3_PB2_Msk)) | INT3_PB2 /*!< Set PB2 function to INT3 */ +#define SET_INT3_PC7() SYS->GPC_MFPL = (SYS->GPC_MFPL & (~INT3_PC7_Msk)) | INT3_PC7 /*!< Set PC7 function to INT3 */ +#define SET_INT4_PA8() SYS->GPA_MFPH = (SYS->GPA_MFPH & (~INT4_PA8_Msk)) | INT4_PA8 /*!< Set PA8 function to INT4 */ +#define SET_INT4_PB6() SYS->GPB_MFPL = (SYS->GPB_MFPL & (~INT4_PB6_Msk)) | INT4_PB6 /*!< Set PB6 function to INT4 */ +#define SET_INT5_PB7() SYS->GPB_MFPL = (SYS->GPB_MFPL & (~INT5_PB7_Msk)) | INT5_PB7 /*!< Set PB7 function to INT5 */ +#define SET_INT5_PD12() SYS->GPD_MFPH = (SYS->GPD_MFPH & (~INT5_PD12_Msk)) | INT5_PD12 /*!< Set PD12 function to INT5 */ +#define SET_INT6_PD11() SYS->GPD_MFPH = (SYS->GPD_MFPH & (~INT6_PD11_Msk)) | INT6_PD11 /*!< Set PD11 function to INT6 */ +#define SET_INT6_PB8() SYS->GPB_MFPH = (SYS->GPB_MFPH & (~INT6_PB8_Msk)) | INT6_PB8 /*!< Set PB8 function to INT6 */ +#define SET_INT7_PB9() SYS->GPB_MFPH = (SYS->GPB_MFPH & (~INT7_PB9_Msk)) | INT7_PB9 /*!< Set PB9 function to INT7 */ +#define SET_INT7_PD10() SYS->GPD_MFPH = (SYS->GPD_MFPH & (~INT7_PD10_Msk)) | INT7_PD10 /*!< Set PD10 function to INT7 */ +#define SET_LCD_COM0_PC0() SYS->GPC_MFPL = (SYS->GPC_MFPL & (~LCD_COM0_PC0_Msk)) | LCD_COM0_PC0 /*!< Set PC0 function to LCD_COM0 */ +#define SET_LCD_COM1_PC1() SYS->GPC_MFPL = (SYS->GPC_MFPL & (~LCD_COM1_PC1_Msk)) | LCD_COM1_PC1 /*!< Set PC1 function to LCD_COM1 */ +#define SET_LCD_COM2_PC2() SYS->GPC_MFPL = (SYS->GPC_MFPL & (~LCD_COM2_PC2_Msk)) | LCD_COM2_PC2 /*!< Set PC2 function to LCD_COM2 */ +#define SET_LCD_COM3_PC3() SYS->GPC_MFPL = (SYS->GPC_MFPL & (~LCD_COM3_PC3_Msk)) | LCD_COM3_PC3 /*!< Set PC3 function to LCD_COM3 */ +#define SET_LCD_COM4_PC4() SYS->GPC_MFPL = (SYS->GPC_MFPL & (~LCD_COM4_PC4_Msk)) | LCD_COM4_PC4 /*!< Set PC4 function to LCD_COM4 */ +#define SET_LCD_COM5_PC5() SYS->GPC_MFPL = (SYS->GPC_MFPL & (~LCD_COM5_PC5_Msk)) | LCD_COM5_PC5 /*!< Set PC5 function to LCD_COM5 */ +#define SET_LCD_COM6_PA0() SYS->GPA_MFPL = (SYS->GPA_MFPL & (~LCD_COM6_PA0_Msk)) | LCD_COM6_PA0 /*!< Set PA0 function to LCD_COM6 */ +#define SET_LCD_COM6_PD8() SYS->GPD_MFPH = (SYS->GPD_MFPH & (~LCD_COM6_PD8_Msk)) | LCD_COM6_PD8 /*!< Set PD8 function to LCD_SEG41 */ +#define SET_LCD_COM7_PA1() SYS->GPA_MFPL = (SYS->GPA_MFPL & (~LCD_COM7_PA1_Msk)) | LCD_COM7_PA1 /*!< Set PA1 function to LCD_COM7 */ +#define SET_LCD_COM7_PD9() SYS->GPD_MFPH = (SYS->GPD_MFPH & (~LCD_COM7_PD9_Msk)) | LCD_COM7_PD9 /*!< Set PD9 function to LCD_COM7 */ +#define SET_LCD_SEG0_PD14() SYS->GPD_MFPH = (SYS->GPD_MFPH & (~LCD_SEG0_PD14_Msk)) | LCD_SEG0_PD14 /*!< Set PD14 function to LCD_SEG0 */ +#define SET_LCD_SEG0_PD1() SYS->GPD_MFPL = (SYS->GPD_MFPL & (~LCD_SEG0_PD1_Msk)) | LCD_SEG0_PD1 /*!< Set PD1 function to LCD_SEG0 */ +#define SET_LCD_SEG1_PD2() SYS->GPD_MFPL = (SYS->GPD_MFPL & (~LCD_SEG1_PD2_Msk)) | LCD_SEG1_PD2 /*!< Set PD2 function to LCD_SEG1 */ +#define SET_LCD_SEG1_PH11() SYS->GPH_MFPH = (SYS->GPH_MFPH & (~LCD_SEG1_PH11_Msk)) | LCD_SEG1_PH11 /*!< Set PH11 function to LCD_SEG1 */ +#define SET_LCD_SEG10_PC7() SYS->GPC_MFPL = (SYS->GPC_MFPL & (~LCD_SEG10_PC7_Msk)) | LCD_SEG10_PC7 /*!< Set PC7 function to LCD_SEG10 */ +#define SET_LCD_SEG10_PE5() SYS->GPE_MFPL = (SYS->GPE_MFPL & (~LCD_SEG10_PE5_Msk)) | LCD_SEG10_PE5 /*!< Set PE5 function to LCD_SEG10 */ +#define SET_LCD_SEG11_PA8() SYS->GPA_MFPH = (SYS->GPA_MFPH & (~LCD_SEG11_PA8_Msk)) | LCD_SEG11_PA8 /*!< Set PA8 function to LCD_SEG11 */ +#define SET_LCD_SEG11_PE6() SYS->GPE_MFPL = (SYS->GPE_MFPL & (~LCD_SEG11_PE6_Msk)) | LCD_SEG11_PE6 /*!< Set PE6 function to LCD_SEG11 */ +#define SET_LCD_SEG12_PA9() SYS->GPA_MFPH = (SYS->GPA_MFPH & (~LCD_SEG12_PA9_Msk)) | LCD_SEG12_PA9 /*!< Set PA9 function to LCD_SEG12 */ +#define SET_LCD_SEG12_PE7() SYS->GPE_MFPL = (SYS->GPE_MFPL & (~LCD_SEG12_PE7_Msk)) | LCD_SEG12_PE7 /*!< Set PE7 function to LCD_SEG12 */ +#define SET_LCD_SEG13_PD6() SYS->GPD_MFPL = (SYS->GPD_MFPL & (~LCD_SEG13_PD6_Msk)) | LCD_SEG13_PD6 /*!< Set PD6 function to LCD_SEG13 */ +#define SET_LCD_SEG13_PA1() SYS->GPA_MFPL = (SYS->GPA_MFPL & (~LCD_SEG13_PA1_Msk)) | LCD_SEG13_PA1 /*!< Set PA1 function to LCD_SEG13 */ +#define SET_LCD_SEG14_PD7() SYS->GPD_MFPL = (SYS->GPD_MFPL & (~LCD_SEG14_PD7_Msk)) | LCD_SEG14_PD7 /*!< Set PD7 function to LCD_SEG14 */ +#define SET_LCD_SEG14_PA0() SYS->GPA_MFPL = (SYS->GPA_MFPL & (~LCD_SEG14_PA0_Msk)) | LCD_SEG14_PA0 /*!< Set PA0 function to LCD_SEG14 */ +#define SET_LCD_SEG15_PG15() SYS->GPG_MFPH = (SYS->GPG_MFPH & (~LCD_SEG15_PG15_Msk)) | LCD_SEG15_PG15 /*!< Set PG15 function to LCD_SEG15 */ +#define SET_LCD_SEG16_PG14() SYS->GPG_MFPH = (SYS->GPG_MFPH & (~LCD_SEG16_PG14_Msk)) | LCD_SEG16_PG14 /*!< Set PG14 function to LCD_SEG16 */ +#define SET_LCD_SEG17_PG13() SYS->GPG_MFPH = (SYS->GPG_MFPH & (~LCD_SEG17_PG13_Msk)) | LCD_SEG17_PG13 /*!< Set PG13 function to LCD_SEG17 */ +#define SET_LCD_SEG18_PG12() SYS->GPG_MFPH = (SYS->GPG_MFPH & (~LCD_SEG18_PG12_Msk)) | LCD_SEG18_PG12 /*!< Set PG12 function to LCD_SEG18 */ +#define SET_LCD_SEG19_PG11() SYS->GPG_MFPH = (SYS->GPG_MFPH & (~LCD_SEG19_PG11_Msk)) | LCD_SEG19_PG11 /*!< Set PG11 function to LCD_SEG19 */ +#define SET_LCD_SEG2_PH10() SYS->GPH_MFPH = (SYS->GPH_MFPH & (~LCD_SEG2_PH10_Msk)) | LCD_SEG2_PH10 /*!< Set PH10 function to LCD_SEG2 */ +#define SET_LCD_SEG2_PD3() SYS->GPD_MFPL = (SYS->GPD_MFPL & (~LCD_SEG2_PD3_Msk)) | LCD_SEG2_PD3 /*!< Set PD3 function to LCD_SEG2 */ +#define SET_LCD_SEG20_PG10() SYS->GPG_MFPH = (SYS->GPG_MFPH & (~LCD_SEG20_PG10_Msk)) | LCD_SEG20_PG10 /*!< Set PG10 function to LCD_SEG20 */ +#define SET_LCD_SEG21_PG9() SYS->GPG_MFPH = (SYS->GPG_MFPH & (~LCD_SEG21_PG9_Msk)) | LCD_SEG21_PG9 /*!< Set PG9 function to LCD_SEG21 */ +#define SET_LCD_SEG22_PE15() SYS->GPE_MFPH = (SYS->GPE_MFPH & (~LCD_SEG22_PE15_Msk)) | LCD_SEG22_PE15 /*!< Set PE15 function to LCD_SEG22 */ +#define SET_LCD_SEG23_PE14() SYS->GPE_MFPH = (SYS->GPE_MFPH & (~LCD_SEG23_PE14_Msk)) | LCD_SEG23_PE14 /*!< Set PE14 function to LCD_SEG23 */ +#define SET_LCD_SEG24_PA0() SYS->GPA_MFPL = (SYS->GPA_MFPL & (~LCD_SEG24_PA0_Msk)) | LCD_SEG24_PA0 /*!< Set PA0 function to LCD_SEG24 */ +#define SET_LCD_SEG25_PA1() SYS->GPA_MFPL = (SYS->GPA_MFPL & (~LCD_SEG25_PA1_Msk)) | LCD_SEG25_PA1 /*!< Set PA1 function to LCD_SEG25 */ +#define SET_LCD_SEG26_PA2() SYS->GPA_MFPL = (SYS->GPA_MFPL & (~LCD_SEG26_PA2_Msk)) | LCD_SEG26_PA2 /*!< Set PA2 function to LCD_SEG26 */ +#define SET_LCD_SEG27_PA3() SYS->GPA_MFPL = (SYS->GPA_MFPL & (~LCD_SEG27_PA3_Msk)) | LCD_SEG27_PA3 /*!< Set PA3 function to LCD_SEG27 */ +#define SET_LCD_SEG28_PA4() SYS->GPA_MFPL = (SYS->GPA_MFPL & (~LCD_SEG28_PA4_Msk)) | LCD_SEG28_PA4 /*!< Set PA4 function to LCD_SEG28 */ +#define SET_LCD_SEG29_PA5() SYS->GPA_MFPL = (SYS->GPA_MFPL & (~LCD_SEG29_PA5_Msk)) | LCD_SEG29_PA5 /*!< Set PA5 function to LCD_SEG29 */ +#define SET_LCD_SEG3_PA2() SYS->GPA_MFPL = (SYS->GPA_MFPL & (~LCD_SEG3_PA2_Msk)) | LCD_SEG3_PA2 /*!< Set PA2 function to LCD_SEG3 */ +#define SET_LCD_SEG3_PH9() SYS->GPH_MFPH = (SYS->GPH_MFPH & (~LCD_SEG3_PH9_Msk)) | LCD_SEG3_PH9 /*!< Set PH9 function to LCD_SEG3 */ +#define SET_LCD_SEG30_PE10() SYS->GPE_MFPH = (SYS->GPE_MFPH & (~LCD_SEG30_PE10_Msk)) | LCD_SEG30_PE10 /*!< Set PE10 function to LCD_SEG30 */ +#define SET_LCD_SEG31_PE9() SYS->GPE_MFPH = (SYS->GPE_MFPH & (~LCD_SEG31_PE9_Msk)) | LCD_SEG31_PE9 /*!< Set PE9 function to LCD_SEG31 */ +#define SET_LCD_SEG32_PE8() SYS->GPE_MFPH = (SYS->GPE_MFPH & (~LCD_SEG32_PE8_Msk)) | LCD_SEG32_PE8 /*!< Set PE8 function to LCD_SEG32 */ +#define SET_LCD_SEG33_PH7() SYS->GPH_MFPL = (SYS->GPH_MFPL & (~LCD_SEG33_PH7_Msk)) | LCD_SEG33_PH7 /*!< Set PH7 function to LCD_SEG33 */ +#define SET_LCD_SEG34_PH6() SYS->GPH_MFPL = (SYS->GPH_MFPL & (~LCD_SEG34_PH6_Msk)) | LCD_SEG34_PH6 /*!< Set PH6 function to LCD_SEG34 */ +#define SET_LCD_SEG35_PH5() SYS->GPH_MFPL = (SYS->GPH_MFPL & (~LCD_SEG35_PH5_Msk)) | LCD_SEG35_PH5 /*!< Set PH5 function to LCD_SEG35 */ +#define SET_LCD_SEG36_PH4() SYS->GPH_MFPL = (SYS->GPH_MFPL & (~LCD_SEG36_PH4_Msk)) | LCD_SEG36_PH4 /*!< Set PH4 function to LCD_SEG36 */ +#define SET_LCD_SEG37_PG4() SYS->GPG_MFPL = (SYS->GPG_MFPL & (~LCD_SEG37_PG4_Msk)) | LCD_SEG37_PG4 /*!< Set PG4 function to LCD_SEG37 */ +#define SET_LCD_SEG38_PG3() SYS->GPG_MFPL = (SYS->GPG_MFPL & (~LCD_SEG38_PG3_Msk)) | LCD_SEG38_PG3 /*!< Set PG3 function to LCD_SEG38 */ +#define SET_LCD_SEG39_PG2() SYS->GPG_MFPL = (SYS->GPG_MFPL & (~LCD_SEG39_PG2_Msk)) | LCD_SEG39_PG2 /*!< Set PG2 function to LCD_SEG39 */ +#define SET_LCD_SEG4_PH8() SYS->GPH_MFPH = (SYS->GPH_MFPH & (~LCD_SEG4_PH8_Msk)) | LCD_SEG4_PH8 /*!< Set PH8 function to LCD_SEG4 */ +#define SET_LCD_SEG4_PA3() SYS->GPA_MFPL = (SYS->GPA_MFPL & (~LCD_SEG4_PA3_Msk)) | LCD_SEG4_PA3 /*!< Set PA3 function to LCD_SEG4 */ +#define SET_LCD_SEG40_PD9() SYS->GPD_MFPH = (SYS->GPD_MFPH & (~LCD_SEG40_PD9_Msk)) | LCD_SEG40_PD9 /*!< Set PD9 function to LCD_SEG40 */ +#define SET_LCD_SEG41_PD8() SYS->GPD_MFPH = (SYS->GPD_MFPH & (~LCD_SEG41_PD8_Msk)) | LCD_SEG41_PD8 /*!< Set PD8 function to LCD_SEG41 */ +#define SET_LCD_SEG42_PC5() SYS->GPC_MFPL = (SYS->GPC_MFPL & (~LCD_SEG42_PC5_Msk)) | LCD_SEG42_PC5 /*!< Set PC5 function to LCD_SEG42 */ +#define SET_LCD_SEG43_PC4() SYS->GPC_MFPL = (SYS->GPC_MFPL & (~LCD_SEG43_PC4_Msk)) | LCD_SEG43_PC4 /*!< Set PC4 function to LCD_SEG43 */ +#define SET_LCD_SEG5_PA4() SYS->GPA_MFPL = (SYS->GPA_MFPL & (~LCD_SEG5_PA4_Msk)) | LCD_SEG5_PA4 /*!< Set PA4 function to LCD_SEG5 */ +#define SET_LCD_SEG5_PE0() SYS->GPE_MFPL = (SYS->GPE_MFPL & (~LCD_SEG5_PE0_Msk)) | LCD_SEG5_PE0 /*!< Set PE0 function to LCD_SEG5 */ +#define SET_LCD_SEG6_PE1() SYS->GPE_MFPL = (SYS->GPE_MFPL & (~LCD_SEG6_PE1_Msk)) | LCD_SEG6_PE1 /*!< Set PE1 function to LCD_SEG6 */ +#define SET_LCD_SEG6_PA5() SYS->GPA_MFPL = (SYS->GPA_MFPL & (~LCD_SEG6_PA5_Msk)) | LCD_SEG6_PA5 /*!< Set PA5 function to LCD_SEG6 */ +#define SET_LCD_SEG7_PA6() SYS->GPA_MFPL = (SYS->GPA_MFPL & (~LCD_SEG7_PA6_Msk)) | LCD_SEG7_PA6 /*!< Set PA6 function to LCD_SEG7 */ +#define SET_LCD_SEG7_PE2() SYS->GPE_MFPL = (SYS->GPE_MFPL & (~LCD_SEG7_PE2_Msk)) | LCD_SEG7_PE2 /*!< Set PE2 function to LCD_SEG7 */ +#define SET_LCD_SEG8_PE3() SYS->GPE_MFPL = (SYS->GPE_MFPL & (~LCD_SEG8_PE3_Msk)) | LCD_SEG8_PE3 /*!< Set PE3 function to LCD_SEG8 */ +#define SET_LCD_SEG8_PA7() SYS->GPA_MFPL = (SYS->GPA_MFPL & (~LCD_SEG8_PA7_Msk)) | LCD_SEG8_PA7 /*!< Set PA7 function to LCD_SEG8 */ +#define SET_LCD_SEG9_PC6() SYS->GPC_MFPL = (SYS->GPC_MFPL & (~LCD_SEG9_PC6_Msk)) | LCD_SEG9_PC6 /*!< Set PC6 function to LCD_SEG9 */ +#define SET_LCD_SEG9_PE4() SYS->GPE_MFPL = (SYS->GPE_MFPL & (~LCD_SEG9_PE4_Msk)) | LCD_SEG9_PE4 /*!< Set PE4 function to LCD_SEG9 */ +#define SET_QEI0_A_PD11() SYS->GPD_MFPH = (SYS->GPD_MFPH & (~QEI0_A_PD11_Msk)) | QEI0_A_PD11 /*!< Set PD11 function to QEI0_A */ +#define SET_QEI0_A_PA4() SYS->GPA_MFPL = (SYS->GPA_MFPL & (~QEI0_A_PA4_Msk)) | QEI0_A_PA4 /*!< Set PA4 function to QEI0_A */ +#define SET_QEI0_A_PE3() SYS->GPE_MFPL = (SYS->GPE_MFPL & (~QEI0_A_PE3_Msk)) | QEI0_A_PE3 /*!< Set PE3 function to QEI0_A */ +#define SET_QEI0_B_PE2() SYS->GPE_MFPL = (SYS->GPE_MFPL & (~QEI0_B_PE2_Msk)) | QEI0_B_PE2 /*!< Set PE2 function to QEI0_B */ +#define SET_QEI0_B_PD10() SYS->GPD_MFPH = (SYS->GPD_MFPH & (~QEI0_B_PD10_Msk)) | QEI0_B_PD10 /*!< Set PD10 function to QEI0_B */ +#define SET_QEI0_B_PA3() SYS->GPA_MFPL = (SYS->GPA_MFPL & (~QEI0_B_PA3_Msk)) | QEI0_B_PA3 /*!< Set PA3 function to QEI0_B */ +#define SET_QEI0_INDEX_PE4() SYS->GPE_MFPL = (SYS->GPE_MFPL & (~QEI0_INDEX_PE4_Msk)) | QEI0_INDEX_PE4 /*!< Set PE4 function to QEI0_INDEX */ +#define SET_QEI0_INDEX_PA5() SYS->GPA_MFPL = (SYS->GPA_MFPL & (~QEI0_INDEX_PA5_Msk)) | QEI0_INDEX_PA5 /*!< Set PA5 function to QEI0_INDEX */ +#define SET_QEI0_INDEX_PD12() SYS->GPD_MFPH = (SYS->GPD_MFPH & (~QEI0_INDEX_PD12_Msk)) | QEI0_INDEX_PD12 /*!< Set PD12 function to QEI0_INDEX */ +#define SET_QEI1_A_PA13() SYS->GPA_MFPH = (SYS->GPA_MFPH & (~QEI1_A_PA13_Msk)) | QEI1_A_PA13 /*!< Set PA13 function to QEI1_A */ +#define SET_QEI1_A_PE6() SYS->GPE_MFPL = (SYS->GPE_MFPL & (~QEI1_A_PE6_Msk)) | QEI1_A_PE6 /*!< Set PE6 function to QEI1_A */ +#define SET_QEI1_A_PA9() SYS->GPA_MFPH = (SYS->GPA_MFPH & (~QEI1_A_PA9_Msk)) | QEI1_A_PA9 /*!< Set PA9 function to QEI1_A */ +#define SET_QEI1_B_PE5() SYS->GPE_MFPL = (SYS->GPE_MFPL & (~QEI1_B_PE5_Msk)) | QEI1_B_PE5 /*!< Set PE5 function to QEI1_B */ +#define SET_QEI1_B_PA8() SYS->GPA_MFPH = (SYS->GPA_MFPH & (~QEI1_B_PA8_Msk)) | QEI1_B_PA8 /*!< Set PA8 function to QEI1_B */ +#define SET_QEI1_B_PA14() SYS->GPA_MFPH = (SYS->GPA_MFPH & (~QEI1_B_PA14_Msk)) | QEI1_B_PA14 /*!< Set PA14 function to QEI1_B */ +#define SET_QEI1_INDEX_PA10() SYS->GPA_MFPH = (SYS->GPA_MFPH & (~QEI1_INDEX_PA10_Msk)) | QEI1_INDEX_PA10 /*!< Set PA10 function to QEI1_INDEX */ +#define SET_QEI1_INDEX_PE7() SYS->GPE_MFPL = (SYS->GPE_MFPL & (~QEI1_INDEX_PE7_Msk)) | QEI1_INDEX_PE7 /*!< Set PE7 function to QEI1_INDEX */ +#define SET_QEI1_INDEX_PA12() SYS->GPA_MFPH = (SYS->GPA_MFPH & (~QEI1_INDEX_PA12_Msk)) | QEI1_INDEX_PA12 /*!< Set PA12 function to QEI1_INDEX */ +#define SET_QSPI0_CLK_PH8() SYS->GPH_MFPH = (SYS->GPH_MFPH & (~QSPI0_CLK_PH8_Msk)) | QSPI0_CLK_PH8 /*!< Set PH8 function to QSPI0_CLK */ +#define SET_QSPI0_CLK_PF2() SYS->GPF_MFPL = (SYS->GPF_MFPL & (~QSPI0_CLK_PF2_Msk)) | QSPI0_CLK_PF2 /*!< Set PF2 function to QSPI0_CLK */ +#define SET_QSPI0_CLK_PA2() SYS->GPA_MFPL = (SYS->GPA_MFPL & (~QSPI0_CLK_PA2_Msk)) | QSPI0_CLK_PA2 /*!< Set PA2 function to QSPI0_CLK */ +#define SET_QSPI0_CLK_PC2() SYS->GPC_MFPL = (SYS->GPC_MFPL & (~QSPI0_CLK_PC2_Msk)) | QSPI0_CLK_PC2 /*!< Set PC2 function to QSPI0_CLK */ +#define SET_QSPI0_MISO0_PC1() SYS->GPC_MFPL = (SYS->GPC_MFPL & (~QSPI0_MISO0_PC1_Msk)) | QSPI0_MISO0_PC1 /*!< Set PC1 function to QSPI0_MISO0 */ +#define SET_QSPI0_MISO0_PE1() SYS->GPE_MFPL = (SYS->GPE_MFPL & (~QSPI0_MISO0_PE1_Msk)) | QSPI0_MISO0_PE1 /*!< Set PE1 function to QSPI0_MISO0 */ +#define SET_QSPI0_MISO0_PA1() SYS->GPA_MFPL = (SYS->GPA_MFPL & (~QSPI0_MISO0_PA1_Msk)) | QSPI0_MISO0_PA1 /*!< Set PA1 function to QSPI0_MISO0 */ +#define SET_QSPI0_MISO1_PB1() SYS->GPB_MFPL = (SYS->GPB_MFPL & (~QSPI0_MISO1_PB1_Msk)) | QSPI0_MISO1_PB1 /*!< Set PB1 function to QSPI0_MISO1 */ +#define SET_QSPI0_MISO1_PC5() SYS->GPC_MFPL = (SYS->GPC_MFPL & (~QSPI0_MISO1_PC5_Msk)) | QSPI0_MISO1_PC5 /*!< Set PC5 function to QSPI0_MISO1 */ +#define SET_QSPI0_MISO1_PH10() SYS->GPH_MFPH = (SYS->GPH_MFPH & (~QSPI0_MISO1_PH10_Msk)) | QSPI0_MISO1_PH10 /*!< Set PH10 function to QSPI0_MISO1 */ +#define SET_QSPI0_MISO1_PA5() SYS->GPA_MFPL = (SYS->GPA_MFPL & (~QSPI0_MISO1_PA5_Msk)) | QSPI0_MISO1_PA5 /*!< Set PA5 function to QSPI0_MISO1 */ +#define SET_QSPI0_MOSI0_PC0() SYS->GPC_MFPL = (SYS->GPC_MFPL & (~QSPI0_MOSI0_PC0_Msk)) | QSPI0_MOSI0_PC0 /*!< Set PC0 function to QSPI0_MOSI0 */ +#define SET_QSPI0_MOSI0_PE0() SYS->GPE_MFPL = (SYS->GPE_MFPL & (~QSPI0_MOSI0_PE0_Msk)) | QSPI0_MOSI0_PE0 /*!< Set PE0 function to QSPI0_MOSI0 */ +#define SET_QSPI0_MOSI0_PA0() SYS->GPA_MFPL = (SYS->GPA_MFPL & (~QSPI0_MOSI0_PA0_Msk)) | QSPI0_MOSI0_PA0 /*!< Set PA0 function to QSPI0_MOSI0 */ +#define SET_QSPI0_MOSI1_PC4() SYS->GPC_MFPL = (SYS->GPC_MFPL & (~QSPI0_MOSI1_PC4_Msk)) | QSPI0_MOSI1_PC4 /*!< Set PC4 function to QSPI0_MOSI1 */ +#define SET_QSPI0_MOSI1_PH11() SYS->GPH_MFPH = (SYS->GPH_MFPH & (~QSPI0_MOSI1_PH11_Msk)) | QSPI0_MOSI1_PH11 /*!< Set PH11 function to QSPI0_MOSI1 */ +#define SET_QSPI0_MOSI1_PB0() SYS->GPB_MFPL = (SYS->GPB_MFPL & (~QSPI0_MOSI1_PB0_Msk)) | QSPI0_MOSI1_PB0 /*!< Set PB0 function to QSPI0_MOSI1 */ +#define SET_QSPI0_MOSI1_PA4() SYS->GPA_MFPL = (SYS->GPA_MFPL & (~QSPI0_MOSI1_PA4_Msk)) | QSPI0_MOSI1_PA4 /*!< Set PA4 function to QSPI0_MOSI1 */ +#define SET_QSPI0_SS_PA3() SYS->GPA_MFPL = (SYS->GPA_MFPL & (~QSPI0_SS_PA3_Msk)) | QSPI0_SS_PA3 /*!< Set PA3 function to QSPI0_SS */ +#define SET_QSPI0_SS_PC3() SYS->GPC_MFPL = (SYS->GPC_MFPL & (~QSPI0_SS_PC3_Msk)) | QSPI0_SS_PC3 /*!< Set PC3 function to QSPI0_SS */ +#define SET_QSPI0_SS_PH9() SYS->GPH_MFPH = (SYS->GPH_MFPH & (~QSPI0_SS_PH9_Msk)) | QSPI0_SS_PH9 /*!< Set PH9 function to QSPI0_SS */ +#define SET_SC0_CLK_PA0() SYS->GPA_MFPL = (SYS->GPA_MFPL & (~SC0_CLK_PA0_Msk)) | SC0_CLK_PA0 /*!< Set PA0 function to SC0_CLK */ +#define SET_SC0_CLK_PF6() SYS->GPF_MFPL = (SYS->GPF_MFPL & (~SC0_CLK_PF6_Msk)) | SC0_CLK_PF6 /*!< Set PF6 function to SC0_CLK */ +#define SET_SC0_CLK_PE2() SYS->GPE_MFPL = (SYS->GPE_MFPL & (~SC0_CLK_PE2_Msk)) | SC0_CLK_PE2 /*!< Set PE2 function to SC0_CLK */ +#define SET_SC0_CLK_PB5() SYS->GPB_MFPL = (SYS->GPB_MFPL & (~SC0_CLK_PB5_Msk)) | SC0_CLK_PB5 /*!< Set PB5 function to SC0_CLK */ +#define SET_SC0_DAT_PF7() SYS->GPF_MFPL = (SYS->GPF_MFPL & (~SC0_DAT_PF7_Msk)) | SC0_DAT_PF7 /*!< Set PF7 function to SC0_DAT */ +#define SET_SC0_DAT_PA1() SYS->GPA_MFPL = (SYS->GPA_MFPL & (~SC0_DAT_PA1_Msk)) | SC0_DAT_PA1 /*!< Set PA1 function to SC0_DAT */ +#define SET_SC0_DAT_PE3() SYS->GPE_MFPL = (SYS->GPE_MFPL & (~SC0_DAT_PE3_Msk)) | SC0_DAT_PE3 /*!< Set PE3 function to SC0_DAT */ +#define SET_SC0_DAT_PB4() SYS->GPB_MFPL = (SYS->GPB_MFPL & (~SC0_DAT_PB4_Msk)) | SC0_DAT_PB4 /*!< Set PB4 function to SC0_DAT */ +#define SET_SC0_PWR_PF9() SYS->GPF_MFPH = (SYS->GPF_MFPH & (~SC0_PWR_PF9_Msk)) | SC0_PWR_PF9 /*!< Set PF9 function to SC0_PWR */ +#define SET_SC0_PWR_PE5() SYS->GPE_MFPL = (SYS->GPE_MFPL & (~SC0_PWR_PE5_Msk)) | SC0_PWR_PE5 /*!< Set PE5 function to SC0_PWR */ +#define SET_SC0_PWR_PA3() SYS->GPA_MFPL = (SYS->GPA_MFPL & (~SC0_PWR_PA3_Msk)) | SC0_PWR_PA3 /*!< Set PA3 function to SC0_PWR */ +#define SET_SC0_PWR_PB2() SYS->GPB_MFPL = (SYS->GPB_MFPL & (~SC0_PWR_PB2_Msk)) | SC0_PWR_PB2 /*!< Set PB2 function to SC0_PWR */ +#define SET_SC0_RST_PE4() SYS->GPE_MFPL = (SYS->GPE_MFPL & (~SC0_RST_PE4_Msk)) | SC0_RST_PE4 /*!< Set PE4 function to SC0_RST */ +#define SET_SC0_RST_PF8() SYS->GPF_MFPH = (SYS->GPF_MFPH & (~SC0_RST_PF8_Msk)) | SC0_RST_PF8 /*!< Set PF8 function to SC0_RST */ +#define SET_SC0_RST_PA2() SYS->GPA_MFPL = (SYS->GPA_MFPL & (~SC0_RST_PA2_Msk)) | SC0_RST_PA2 /*!< Set PA2 function to SC0_RST */ +#define SET_SC0_RST_PB3() SYS->GPB_MFPL = (SYS->GPB_MFPL & (~SC0_RST_PB3_Msk)) | SC0_RST_PB3 /*!< Set PB3 function to SC0_RST */ +#define SET_SC0_nCD_PC12() SYS->GPC_MFPH = (SYS->GPC_MFPH & (~SC0_nCD_PC12_Msk)) | SC0_nCD_PC12 /*!< Set PC12 function to SC0_nCD */ +#define SET_SC0_nCD_PA4() SYS->GPA_MFPL = (SYS->GPA_MFPL & (~SC0_nCD_PA4_Msk)) | SC0_nCD_PA4 /*!< Set PA4 function to SC0_nCD */ +#define SET_SC0_nCD_PF10() SYS->GPF_MFPH = (SYS->GPF_MFPH & (~SC0_nCD_PF10_Msk)) | SC0_nCD_PF10 /*!< Set PF10 function to SC0_nCD */ +#define SET_SC0_nCD_PE6() SYS->GPE_MFPL = (SYS->GPE_MFPL & (~SC0_nCD_PE6_Msk)) | SC0_nCD_PE6 /*!< Set PE6 function to SC0_nCD */ +#define SET_SC1_CLK_PB12() SYS->GPB_MFPH = (SYS->GPB_MFPH & (~SC1_CLK_PB12_Msk)) | SC1_CLK_PB12 /*!< Set PB12 function to SC1_CLK */ +#define SET_SC1_CLK_PC0() SYS->GPC_MFPL = (SYS->GPC_MFPL & (~SC1_CLK_PC0_Msk)) | SC1_CLK_PC0 /*!< Set PC0 function to SC1_CLK */ +#define SET_SC1_CLK_PD4() SYS->GPD_MFPL = (SYS->GPD_MFPL & (~SC1_CLK_PD4_Msk)) | SC1_CLK_PD4 /*!< Set PD4 function to SC1_CLK */ +#define SET_SC1_DAT_PD5() SYS->GPD_MFPL = (SYS->GPD_MFPL & (~SC1_DAT_PD5_Msk)) | SC1_DAT_PD5 /*!< Set PD5 function to SC1_DAT */ +#define SET_SC1_DAT_PC1() SYS->GPC_MFPL = (SYS->GPC_MFPL & (~SC1_DAT_PC1_Msk)) | SC1_DAT_PC1 /*!< Set PC1 function to SC1_DAT */ +#define SET_SC1_DAT_PB13() SYS->GPB_MFPH = (SYS->GPB_MFPH & (~SC1_DAT_PB13_Msk)) | SC1_DAT_PB13 /*!< Set PB13 function to SC1_DAT */ +#define SET_SC1_PWR_PD7() SYS->GPD_MFPL = (SYS->GPD_MFPL & (~SC1_PWR_PD7_Msk)) | SC1_PWR_PD7 /*!< Set PD7 function to SC1_PWR */ +#define SET_SC1_PWR_PC3() SYS->GPC_MFPL = (SYS->GPC_MFPL & (~SC1_PWR_PC3_Msk)) | SC1_PWR_PC3 /*!< Set PC3 function to SC1_PWR */ +#define SET_SC1_PWR_PB15() SYS->GPB_MFPH = (SYS->GPB_MFPH & (~SC1_PWR_PB15_Msk)) | SC1_PWR_PB15 /*!< Set PB15 function to SC1_PWR */ +#define SET_SC1_RST_PD6() SYS->GPD_MFPL = (SYS->GPD_MFPL & (~SC1_RST_PD6_Msk)) | SC1_RST_PD6 /*!< Set PD6 function to SC1_RST */ +#define SET_SC1_RST_PB14() SYS->GPB_MFPH = (SYS->GPB_MFPH & (~SC1_RST_PB14_Msk)) | SC1_RST_PB14 /*!< Set PB14 function to SC1_RST */ +#define SET_SC1_RST_PC2() SYS->GPC_MFPL = (SYS->GPC_MFPL & (~SC1_RST_PC2_Msk)) | SC1_RST_PC2 /*!< Set PC2 function to SC1_RST */ +#define SET_SC1_nCD_PD14() SYS->GPD_MFPH = (SYS->GPD_MFPH & (~SC1_nCD_PD14_Msk)) | SC1_nCD_PD14 /*!< Set PD14 function to SC1_nCD */ +#define SET_SC1_nCD_PC4() SYS->GPC_MFPL = (SYS->GPC_MFPL & (~SC1_nCD_PC4_Msk)) | SC1_nCD_PC4 /*!< Set PC4 function to SC1_nCD */ +#define SET_SC1_nCD_PD3() SYS->GPD_MFPL = (SYS->GPD_MFPL & (~SC1_nCD_PD3_Msk)) | SC1_nCD_PD3 /*!< Set PD3 function to SC1_nCD */ +#define SET_SC2_CLK_PA6() SYS->GPA_MFPL = (SYS->GPA_MFPL & (~SC2_CLK_PA6_Msk)) | SC2_CLK_PA6 /*!< Set PA6 function to SC2_CLK */ +#define SET_SC2_CLK_PD0() SYS->GPD_MFPL = (SYS->GPD_MFPL & (~SC2_CLK_PD0_Msk)) | SC2_CLK_PD0 /*!< Set PD0 function to SC2_CLK */ +#define SET_SC2_CLK_PA15() SYS->GPA_MFPH = (SYS->GPA_MFPH & (~SC2_CLK_PA15_Msk)) | SC2_CLK_PA15 /*!< Set PA15 function to SC2_CLK */ +#define SET_SC2_CLK_PA8() SYS->GPA_MFPH = (SYS->GPA_MFPH & (~SC2_CLK_PA8_Msk)) | SC2_CLK_PA8 /*!< Set PA8 function to SC2_CLK */ +#define SET_SC2_CLK_PE0() SYS->GPE_MFPL = (SYS->GPE_MFPL & (~SC2_CLK_PE0_Msk)) | SC2_CLK_PE0 /*!< Set PE0 function to SC2_CLK */ +#define SET_SC2_DAT_PA9() SYS->GPA_MFPH = (SYS->GPA_MFPH & (~SC2_DAT_PA9_Msk)) | SC2_DAT_PA9 /*!< Set PA9 function to SC2_DAT */ +#define SET_SC2_DAT_PD1() SYS->GPD_MFPL = (SYS->GPD_MFPL & (~SC2_DAT_PD1_Msk)) | SC2_DAT_PD1 /*!< Set PD1 function to SC2_DAT */ +#define SET_SC2_DAT_PA7() SYS->GPA_MFPL = (SYS->GPA_MFPL & (~SC2_DAT_PA7_Msk)) | SC2_DAT_PA7 /*!< Set PA7 function to SC2_DAT */ +#define SET_SC2_DAT_PA14() SYS->GPA_MFPH = (SYS->GPA_MFPH & (~SC2_DAT_PA14_Msk)) | SC2_DAT_PA14 /*!< Set PA14 function to SC2_DAT */ +#define SET_SC2_DAT_PE1() SYS->GPE_MFPL = (SYS->GPE_MFPL & (~SC2_DAT_PE1_Msk)) | SC2_DAT_PE1 /*!< Set PE1 function to SC2_DAT */ +#define SET_SC2_PWR_PC7() SYS->GPC_MFPL = (SYS->GPC_MFPL & (~SC2_PWR_PC7_Msk)) | SC2_PWR_PC7 /*!< Set PC7 function to SC2_PWR */ +#define SET_SC2_PWR_PH8() SYS->GPH_MFPH = (SYS->GPH_MFPH & (~SC2_PWR_PH8_Msk)) | SC2_PWR_PH8 /*!< Set PH8 function to SC2_PWR */ +#define SET_SC2_PWR_PD3() SYS->GPD_MFPL = (SYS->GPD_MFPL & (~SC2_PWR_PD3_Msk)) | SC2_PWR_PD3 /*!< Set PD3 function to SC2_PWR */ +#define SET_SC2_PWR_PA11() SYS->GPA_MFPH = (SYS->GPA_MFPH & (~SC2_PWR_PA11_Msk)) | SC2_PWR_PA11 /*!< Set PA11 function to SC2_PWR */ +#define SET_SC2_PWR_PA12() SYS->GPA_MFPH = (SYS->GPA_MFPH & (~SC2_PWR_PA12_Msk)) | SC2_PWR_PA12 /*!< Set PA12 function to SC2_PWR */ +#define SET_SC2_RST_PD2() SYS->GPD_MFPL = (SYS->GPD_MFPL & (~SC2_RST_PD2_Msk)) | SC2_RST_PD2 /*!< Set PD2 function to SC2_RST */ +#define SET_SC2_RST_PC6() SYS->GPC_MFPL = (SYS->GPC_MFPL & (~SC2_RST_PC6_Msk)) | SC2_RST_PC6 /*!< Set PC6 function to SC2_RST */ +#define SET_SC2_RST_PH9() SYS->GPH_MFPH = (SYS->GPH_MFPH & (~SC2_RST_PH9_Msk)) | SC2_RST_PH9 /*!< Set PH9 function to SC2_RST */ +#define SET_SC2_RST_PA13() SYS->GPA_MFPH = (SYS->GPA_MFPH & (~SC2_RST_PA13_Msk)) | SC2_RST_PA13 /*!< Set PA13 function to SC2_RST */ +#define SET_SC2_RST_PA10() SYS->GPA_MFPH = (SYS->GPA_MFPH & (~SC2_RST_PA10_Msk)) | SC2_RST_PA10 /*!< Set PA10 function to SC2_RST */ +#define SET_SC2_nCD_PA5() SYS->GPA_MFPL = (SYS->GPA_MFPL & (~SC2_nCD_PA5_Msk)) | SC2_nCD_PA5 /*!< Set PA5 function to SC2_nCD */ +#define SET_SC2_nCD_PH10() SYS->GPH_MFPH = (SYS->GPH_MFPH & (~SC2_nCD_PH10_Msk)) | SC2_nCD_PH10 /*!< Set PH10 function to SC2_nCD */ +#define SET_SC2_nCD_PD13() SYS->GPD_MFPH = (SYS->GPD_MFPH & (~SC2_nCD_PD13_Msk)) | SC2_nCD_PD13 /*!< Set PD13 function to SC2_nCD */ +#define SET_SC2_nCD_PC13() SYS->GPC_MFPH = (SYS->GPC_MFPH & (~SC2_nCD_PC13_Msk)) | SC2_nCD_PC13 /*!< Set PC13 function to SC2_nCD */ +#define SET_SD0_CLK_PB1() SYS->GPB_MFPL = (SYS->GPB_MFPL & (~SD0_CLK_PB1_Msk)) | SD0_CLK_PB1 /*!< Set PB1 function to SD0_CLK */ +#define SET_SD0_CLK_PE6() SYS->GPE_MFPL = (SYS->GPE_MFPL & (~SD0_CLK_PE6_Msk)) | SD0_CLK_PE6 /*!< Set PE6 function to SD0_CLK */ +#define SET_SD0_CMD_PE7() SYS->GPE_MFPL = (SYS->GPE_MFPL & (~SD0_CMD_PE7_Msk)) | SD0_CMD_PE7 /*!< Set PE7 function to SD0_CMD */ +#define SET_SD0_CMD_PB0() SYS->GPB_MFPL = (SYS->GPB_MFPL & (~SD0_CMD_PB0_Msk)) | SD0_CMD_PB0 /*!< Set PB0 function to SD0_CMD */ +#define SET_SD0_DAT0_PE2() SYS->GPE_MFPL = (SYS->GPE_MFPL & (~SD0_DAT0_PE2_Msk)) | SD0_DAT0_PE2 /*!< Set PE2 function to SD0_DAT0 */ +#define SET_SD0_DAT0_PB2() SYS->GPB_MFPL = (SYS->GPB_MFPL & (~SD0_DAT0_PB2_Msk)) | SD0_DAT0_PB2 /*!< Set PB2 function to SD0_DAT0 */ +#define SET_SD0_DAT1_PE3() SYS->GPE_MFPL = (SYS->GPE_MFPL & (~SD0_DAT1_PE3_Msk)) | SD0_DAT1_PE3 /*!< Set PE3 function to SD0_DAT1 */ +#define SET_SD0_DAT1_PB3() SYS->GPB_MFPL = (SYS->GPB_MFPL & (~SD0_DAT1_PB3_Msk)) | SD0_DAT1_PB3 /*!< Set PB3 function to SD0_DAT1 */ +#define SET_SD0_DAT2_PE4() SYS->GPE_MFPL = (SYS->GPE_MFPL & (~SD0_DAT2_PE4_Msk)) | SD0_DAT2_PE4 /*!< Set PE4 function to SD0_DAT2 */ +#define SET_SD0_DAT2_PB4() SYS->GPB_MFPL = (SYS->GPB_MFPL & (~SD0_DAT2_PB4_Msk)) | SD0_DAT2_PB4 /*!< Set PB4 function to SD0_DAT2 */ +#define SET_SD0_DAT3_PE5() SYS->GPE_MFPL = (SYS->GPE_MFPL & (~SD0_DAT3_PE5_Msk)) | SD0_DAT3_PE5 /*!< Set PE5 function to SD0_DAT3 */ +#define SET_SD0_DAT3_PB5() SYS->GPB_MFPL = (SYS->GPB_MFPL & (~SD0_DAT3_PB5_Msk)) | SD0_DAT3_PB5 /*!< Set PB5 function to SD0_DAT3 */ +#define SET_SD0_nCD_PD13() SYS->GPD_MFPH = (SYS->GPD_MFPH & (~SD0_nCD_PD13_Msk)) | SD0_nCD_PD13 /*!< Set PD13 function to SD0_nCD */ +#define SET_SD0_nCD_PB12() SYS->GPB_MFPH = (SYS->GPB_MFPH & (~SD0_nCD_PB12_Msk)) | SD0_nCD_PB12 /*!< Set PB12 function to SD0_nCD */ +#define SET_SEG15_PC5() SYS->GPC_MFPL = (SYS->GPC_MFPL & (~SEG15_PC5_Msk)) | SEG15_PC5 /*!< Set PC5 function to SEG15 */ +#define SET_SEG16_PC4() SYS->GPC_MFPL = (SYS->GPC_MFPL & (~SEG16_PC4_Msk)) | SEG16_PC4 /*!< Set PC4 function to SEG16 */ +#define SET_SPI0_CLK_PD2() SYS->GPD_MFPL = (SYS->GPD_MFPL & (~SPI0_CLK_PD2_Msk)) | SPI0_CLK_PD2 /*!< Set PD2 function to SPI0_CLK */ +#define SET_SPI0_CLK_PB14() SYS->GPB_MFPH = (SYS->GPB_MFPH & (~SPI0_CLK_PB14_Msk)) | SPI0_CLK_PB14 /*!< Set PB14 function to SPI0_CLK */ +#define SET_SPI0_CLK_PF8() SYS->GPF_MFPH = (SYS->GPF_MFPH & (~SPI0_CLK_PF8_Msk)) | SPI0_CLK_PF8 /*!< Set PF8 function to SPI0_CLK */ +#define SET_SPI0_CLK_PA2() SYS->GPA_MFPL = (SYS->GPA_MFPL & (~SPI0_CLK_PA2_Msk)) | SPI0_CLK_PA2 /*!< Set PA2 function to SPI0_CLK */ +#define SET_SPI0_I2SMCLK_PB11() SYS->GPB_MFPH = (SYS->GPB_MFPH & (~SPI0_I2SMCLK_PB11_Msk)) | SPI0_I2SMCLK_PB11 /*!< Set PB11 function to SPI0_I2SMCLK */ +#define SET_SPI0_I2SMCLK_PB0() SYS->GPB_MFPL = (SYS->GPB_MFPL & (~SPI0_I2SMCLK_PB0_Msk)) | SPI0_I2SMCLK_PB0 /*!< Set PB0 function to SPI0_I2SMCLK */ +#define SET_SPI0_I2SMCLK_PF10() SYS->GPF_MFPH = (SYS->GPF_MFPH & (~SPI0_I2SMCLK_PF10_Msk)) | SPI0_I2SMCLK_PF10 /*!< Set PF10 function to SPI0_I2SMCLK */ +#define SET_SPI0_I2SMCLK_PA4() SYS->GPA_MFPL = (SYS->GPA_MFPL & (~SPI0_I2SMCLK_PA4_Msk)) | SPI0_I2SMCLK_PA4 /*!< Set PA4 function to SPI0_I2SMCLK */ +#define SET_SPI0_I2SMCLK_PD14() SYS->GPD_MFPH = (SYS->GPD_MFPH & (~SPI0_I2SMCLK_PD14_Msk)) | SPI0_I2SMCLK_PD14 /*!< Set PD14 function to SPI0_I2SMCLK */ +#define SET_SPI0_I2SMCLK_PD13() SYS->GPD_MFPH = (SYS->GPD_MFPH & (~SPI0_I2SMCLK_PD13_Msk)) | SPI0_I2SMCLK_PD13 /*!< Set PD13 function to SPI0_I2SMCLK */ +#define SET_SPI0_MISO_PA1() SYS->GPA_MFPL = (SYS->GPA_MFPL & (~SPI0_MISO_PA1_Msk)) | SPI0_MISO_PA1 /*!< Set PA1 function to SPI0_MISO */ +#define SET_SPI0_MISO_PF7() SYS->GPF_MFPL = (SYS->GPF_MFPL & (~SPI0_MISO_PF7_Msk)) | SPI0_MISO_PF7 /*!< Set PF7 function to SPI0_MISO */ +#define SET_SPI0_MISO_PD1() SYS->GPD_MFPL = (SYS->GPD_MFPL & (~SPI0_MISO_PD1_Msk)) | SPI0_MISO_PD1 /*!< Set PD1 function to SPI0_MISO */ +#define SET_SPI0_MISO_PB13() SYS->GPB_MFPH = (SYS->GPB_MFPH & (~SPI0_MISO_PB13_Msk)) | SPI0_MISO_PB13 /*!< Set PB13 function to SPI0_MISO */ +#define SET_SPI0_MOSI_PF6() SYS->GPF_MFPL = (SYS->GPF_MFPL & (~SPI0_MOSI_PF6_Msk)) | SPI0_MOSI_PF6 /*!< Set PF6 function to SPI0_MOSI */ +#define SET_SPI0_MOSI_PD0() SYS->GPD_MFPL = (SYS->GPD_MFPL & (~SPI0_MOSI_PD0_Msk)) | SPI0_MOSI_PD0 /*!< Set PD0 function to SPI0_MOSI */ +#define SET_SPI0_MOSI_PB12() SYS->GPB_MFPH = (SYS->GPB_MFPH & (~SPI0_MOSI_PB12_Msk)) | SPI0_MOSI_PB12 /*!< Set PB12 function to SPI0_MOSI */ +#define SET_SPI0_MOSI_PA0() SYS->GPA_MFPL = (SYS->GPA_MFPL & (~SPI0_MOSI_PA0_Msk)) | SPI0_MOSI_PA0 /*!< Set PA0 function to SPI0_MOSI */ +#define SET_SPI0_SS_PF9() SYS->GPF_MFPH = (SYS->GPF_MFPH & (~SPI0_SS_PF9_Msk)) | SPI0_SS_PF9 /*!< Set PF9 function to SPI0_SS */ +#define SET_SPI0_SS_PA3() SYS->GPA_MFPL = (SYS->GPA_MFPL & (~SPI0_SS_PA3_Msk)) | SPI0_SS_PA3 /*!< Set PA3 function to SPI0_SS */ +#define SET_SPI0_SS_PB15() SYS->GPB_MFPH = (SYS->GPB_MFPH & (~SPI0_SS_PB15_Msk)) | SPI0_SS_PB15 /*!< Set PB15 function to SPI0_SS */ +#define SET_SPI0_SS_PD3() SYS->GPD_MFPL = (SYS->GPD_MFPL & (~SPI0_SS_PD3_Msk)) | SPI0_SS_PD3 /*!< Set PD3 function to SPI0_SS */ +#define SET_SPI1_CLK_PD5() SYS->GPD_MFPL = (SYS->GPD_MFPL & (~SPI1_CLK_PD5_Msk)) | SPI1_CLK_PD5 /*!< Set PD5 function to SPI1_CLK */ +#define SET_SPI1_CLK_PH6() SYS->GPH_MFPL = (SYS->GPH_MFPL & (~SPI1_CLK_PH6_Msk)) | SPI1_CLK_PH6 /*!< Set PH6 function to SPI1_CLK */ +#define SET_SPI1_CLK_PC1() SYS->GPC_MFPL = (SYS->GPC_MFPL & (~SPI1_CLK_PC1_Msk)) | SPI1_CLK_PC1 /*!< Set PC1 function to SPI1_CLK */ +#define SET_SPI1_CLK_PB3() SYS->GPB_MFPL = (SYS->GPB_MFPL & (~SPI1_CLK_PB3_Msk)) | SPI1_CLK_PB3 /*!< Set PB3 function to SPI1_CLK */ +#define SET_SPI1_CLK_PH8() SYS->GPH_MFPH = (SYS->GPH_MFPH & (~SPI1_CLK_PH8_Msk)) | SPI1_CLK_PH8 /*!< Set PH8 function to SPI1_CLK */ +#define SET_SPI1_CLK_PA7() SYS->GPA_MFPL = (SYS->GPA_MFPL & (~SPI1_CLK_PA7_Msk)) | SPI1_CLK_PA7 /*!< Set PA7 function to SPI1_CLK */ +#define SET_SPI1_I2SMCLK_PC4() SYS->GPC_MFPL = (SYS->GPC_MFPL & (~SPI1_I2SMCLK_PC4_Msk)) | SPI1_I2SMCLK_PC4 /*!< Set PC4 function to SPI1_I2SMCLK */ +#define SET_SPI1_I2SMCLK_PB1() SYS->GPB_MFPL = (SYS->GPB_MFPL & (~SPI1_I2SMCLK_PB1_Msk)) | SPI1_I2SMCLK_PB1 /*!< Set PB1 function to SPI1_I2SMCLK */ +#define SET_SPI1_I2SMCLK_PA5() SYS->GPA_MFPL = (SYS->GPA_MFPL & (~SPI1_I2SMCLK_PA5_Msk)) | SPI1_I2SMCLK_PA5 /*!< Set PA5 function to SPI1_I2SMCLK */ +#define SET_SPI1_I2SMCLK_PD13() SYS->GPD_MFPH = (SYS->GPD_MFPH & (~SPI1_I2SMCLK_PD13_Msk)) | SPI1_I2SMCLK_PD13 /*!< Set PD13 function to SPI1_I2SMCLK */ +#define SET_SPI1_I2SMCLK_PH10() SYS->GPH_MFPH = (SYS->GPH_MFPH & (~SPI1_I2SMCLK_PH10_Msk)) | SPI1_I2SMCLK_PH10 /*!< Set PH10 function to SPI1_I2SMCLK */ +#define SET_SPI1_MISO_PC3() SYS->GPC_MFPL = (SYS->GPC_MFPL & (~SPI1_MISO_PC3_Msk)) | SPI1_MISO_PC3 /*!< Set PC3 function to SPI1_MISO */ +#define SET_SPI1_MISO_PC7() SYS->GPC_MFPL = (SYS->GPC_MFPL & (~SPI1_MISO_PC7_Msk)) | SPI1_MISO_PC7 /*!< Set PC7 function to SPI1_MISO */ +#define SET_SPI1_MISO_PH4() SYS->GPH_MFPL = (SYS->GPH_MFPL & (~SPI1_MISO_PH4_Msk)) | SPI1_MISO_PH4 /*!< Set PH4 function to SPI1_MISO */ +#define SET_SPI1_MISO_PB5() SYS->GPB_MFPL = (SYS->GPB_MFPL & (~SPI1_MISO_PB5_Msk)) | SPI1_MISO_PB5 /*!< Set PB5 function to SPI1_MISO */ +#define SET_SPI1_MISO_PE1() SYS->GPE_MFPL = (SYS->GPE_MFPL & (~SPI1_MISO_PE1_Msk)) | SPI1_MISO_PE1 /*!< Set PE1 function to SPI1_MISO */ +#define SET_SPI1_MISO_PD7() SYS->GPD_MFPL = (SYS->GPD_MFPL & (~SPI1_MISO_PD7_Msk)) | SPI1_MISO_PD7 /*!< Set PD7 function to SPI1_MISO */ +#define SET_SPI1_MOSI_PE0() SYS->GPE_MFPL = (SYS->GPE_MFPL & (~SPI1_MOSI_PE0_Msk)) | SPI1_MOSI_PE0 /*!< Set PE0 function to SPI1_MOSI */ +#define SET_SPI1_MOSI_PB4() SYS->GPB_MFPL = (SYS->GPB_MFPL & (~SPI1_MOSI_PB4_Msk)) | SPI1_MOSI_PB4 /*!< Set PB4 function to SPI1_MOSI */ +#define SET_SPI1_MOSI_PC6() SYS->GPC_MFPL = (SYS->GPC_MFPL & (~SPI1_MOSI_PC6_Msk)) | SPI1_MOSI_PC6 /*!< Set PC6 function to SPI1_MOSI */ +#define SET_SPI1_MOSI_PD6() SYS->GPD_MFPL = (SYS->GPD_MFPL & (~SPI1_MOSI_PD6_Msk)) | SPI1_MOSI_PD6 /*!< Set PD6 function to SPI1_MOSI */ +#define SET_SPI1_MOSI_PH5() SYS->GPH_MFPL = (SYS->GPH_MFPL & (~SPI1_MOSI_PH5_Msk)) | SPI1_MOSI_PH5 /*!< Set PH5 function to SPI1_MOSI */ +#define SET_SPI1_MOSI_PC2() SYS->GPC_MFPL = (SYS->GPC_MFPL & (~SPI1_MOSI_PC2_Msk)) | SPI1_MOSI_PC2 /*!< Set PC2 function to SPI1_MOSI */ +#define SET_SPI1_SS_PH7() SYS->GPH_MFPL = (SYS->GPH_MFPL & (~SPI1_SS_PH7_Msk)) | SPI1_SS_PH7 /*!< Set PH7 function to SPI1_SS */ +#define SET_SPI1_SS_PB2() SYS->GPB_MFPL = (SYS->GPB_MFPL & (~SPI1_SS_PB2_Msk)) | SPI1_SS_PB2 /*!< Set PB2 function to SPI1_SS */ +#define SET_SPI1_SS_PA6() SYS->GPA_MFPL = (SYS->GPA_MFPL & (~SPI1_SS_PA6_Msk)) | SPI1_SS_PA6 /*!< Set PA6 function to SPI1_SS */ +#define SET_SPI1_SS_PD4() SYS->GPD_MFPL = (SYS->GPD_MFPL & (~SPI1_SS_PD4_Msk)) | SPI1_SS_PD4 /*!< Set PD4 function to SPI1_SS */ +#define SET_SPI1_SS_PH9() SYS->GPH_MFPH = (SYS->GPH_MFPH & (~SPI1_SS_PH9_Msk)) | SPI1_SS_PH9 /*!< Set PH9 function to SPI1_SS */ +#define SET_SPI1_SS_PC0() SYS->GPC_MFPL = (SYS->GPC_MFPL & (~SPI1_SS_PC0_Msk)) | SPI1_SS_PC0 /*!< Set PC0 function to SPI1_SS */ +#define SET_SPI2_CLK_PE8() SYS->GPE_MFPH = (SYS->GPE_MFPH & (~SPI2_CLK_PE8_Msk)) | SPI2_CLK_PE8 /*!< Set PE8 function to SPI2_CLK */ +#define SET_SPI2_CLK_PA10() SYS->GPA_MFPH = (SYS->GPA_MFPH & (~SPI2_CLK_PA10_Msk)) | SPI2_CLK_PA10 /*!< Set PA10 function to SPI2_CLK */ +#define SET_SPI2_CLK_PA13() SYS->GPA_MFPH = (SYS->GPA_MFPH & (~SPI2_CLK_PA13_Msk)) | SPI2_CLK_PA13 /*!< Set PA13 function to SPI2_CLK */ +#define SET_SPI2_CLK_PG3() SYS->GPG_MFPL = (SYS->GPG_MFPL & (~SPI2_CLK_PG3_Msk)) | SPI2_CLK_PG3 /*!< Set PG3 function to SPI2_CLK */ +#define SET_SPI2_I2SMCLK_PE12() SYS->GPE_MFPH = (SYS->GPE_MFPH & (~SPI2_I2SMCLK_PE12_Msk)) | SPI2_I2SMCLK_PE12 /*!< Set PE12 function to SPI2_I2SMCLK */ +#define SET_SPI2_I2SMCLK_PC13() SYS->GPC_MFPH = (SYS->GPC_MFPH & (~SPI2_I2SMCLK_PC13_Msk)) | SPI2_I2SMCLK_PC13 /*!< Set PC13 function to SPI2_I2SMCLK */ +#define SET_SPI2_I2SMCLK_PB0() SYS->GPB_MFPL = (SYS->GPB_MFPL & (~SPI2_I2SMCLK_PB0_Msk)) | SPI2_I2SMCLK_PB0 /*!< Set PB0 function to SPI2_I2SMCLK */ +#define SET_SPI2_MISO_PE9() SYS->GPE_MFPH = (SYS->GPE_MFPH & (~SPI2_MISO_PE9_Msk)) | SPI2_MISO_PE9 /*!< Set PE9 function to SPI2_MISO */ +#define SET_SPI2_MISO_PA9() SYS->GPA_MFPH = (SYS->GPA_MFPH & (~SPI2_MISO_PA9_Msk)) | SPI2_MISO_PA9 /*!< Set PA9 function to SPI2_MISO */ +#define SET_SPI2_MISO_PA14() SYS->GPA_MFPH = (SYS->GPA_MFPH & (~SPI2_MISO_PA14_Msk)) | SPI2_MISO_PA14 /*!< Set PA14 function to SPI2_MISO */ +#define SET_SPI2_MISO_PG4() SYS->GPG_MFPL = (SYS->GPG_MFPL & (~SPI2_MISO_PG4_Msk)) | SPI2_MISO_PG4 /*!< Set PG4 function to SPI2_MISO */ +#define SET_SPI2_MOSI_PF11() SYS->GPF_MFPH = (SYS->GPF_MFPH & (~SPI2_MOSI_PF11_Msk)) | SPI2_MOSI_PF11 /*!< Set PF11 function to SPI2_MOSI */ +#define SET_SPI2_MOSI_PA15() SYS->GPA_MFPH = (SYS->GPA_MFPH & (~SPI2_MOSI_PA15_Msk)) | SPI2_MOSI_PA15 /*!< Set PA15 function to SPI2_MOSI */ +#define SET_SPI2_MOSI_PE10() SYS->GPE_MFPH = (SYS->GPE_MFPH & (~SPI2_MOSI_PE10_Msk)) | SPI2_MOSI_PE10 /*!< Set PE10 function to SPI2_MOSI */ +#define SET_SPI2_MOSI_PA8() SYS->GPA_MFPH = (SYS->GPA_MFPH & (~SPI2_MOSI_PA8_Msk)) | SPI2_MOSI_PA8 /*!< Set PA8 function to SPI2_MOSI */ +#define SET_SPI2_SS_PE11() SYS->GPE_MFPH = (SYS->GPE_MFPH & (~SPI2_SS_PE11_Msk)) | SPI2_SS_PE11 /*!< Set PE11 function to SPI2_SS */ +#define SET_SPI2_SS_PG2() SYS->GPG_MFPL = (SYS->GPG_MFPL & (~SPI2_SS_PG2_Msk)) | SPI2_SS_PG2 /*!< Set PG2 function to SPI2_SS */ +#define SET_SPI2_SS_PA11() SYS->GPA_MFPH = (SYS->GPA_MFPH & (~SPI2_SS_PA11_Msk)) | SPI2_SS_PA11 /*!< Set PA11 function to SPI2_SS */ +#define SET_SPI2_SS_PA12() SYS->GPA_MFPH = (SYS->GPA_MFPH & (~SPI2_SS_PA12_Msk)) | SPI2_SS_PA12 /*!< Set PA12 function to SPI2_SS */ +#define SET_SPI3_CLK_PC10() SYS->GPC_MFPH = (SYS->GPC_MFPH & (~SPI3_CLK_PC10_Msk)) | SPI3_CLK_PC10 /*!< Set PC10 function to SPI3_CLK */ +#define SET_SPI3_CLK_PE4() SYS->GPE_MFPL = (SYS->GPE_MFPL & (~SPI3_CLK_PE4_Msk)) | SPI3_CLK_PE4 /*!< Set PE4 function to SPI3_CLK */ +#define SET_SPI3_CLK_PB11() SYS->GPB_MFPH = (SYS->GPB_MFPH & (~SPI3_CLK_PB11_Msk)) | SPI3_CLK_PB11 /*!< Set PB11 function to SPI3_CLK */ +#define SET_SPI3_I2SMCLK_PE6() SYS->GPE_MFPL = (SYS->GPE_MFPL & (~SPI3_I2SMCLK_PE6_Msk)) | SPI3_I2SMCLK_PE6 /*!< Set PE6 function to SPI3_I2SMCLK */ +#define SET_SPI3_I2SMCLK_PF6() SYS->GPF_MFPL = (SYS->GPF_MFPL & (~SPI3_I2SMCLK_PF6_Msk)) | SPI3_I2SMCLK_PF6 /*!< Set PF6 function to SPI3_I2SMCLK */ +#define SET_SPI3_I2SMCLK_PB1() SYS->GPB_MFPL = (SYS->GPB_MFPL & (~SPI3_I2SMCLK_PB1_Msk)) | SPI3_I2SMCLK_PB1 /*!< Set PB1 function to SPI3_I2SMCLK */ +#define SET_SPI3_I2SMCLK_PD14() SYS->GPD_MFPH = (SYS->GPD_MFPH & (~SPI3_I2SMCLK_PD14_Msk)) | SPI3_I2SMCLK_PD14 /*!< Set PD14 function to SPI3_I2SMCLK */ +#define SET_SPI3_MISO_PE3() SYS->GPE_MFPL = (SYS->GPE_MFPL & (~SPI3_MISO_PE3_Msk)) | SPI3_MISO_PE3 /*!< Set PE3 function to SPI3_MISO */ +#define SET_SPI3_MISO_PC12() SYS->GPC_MFPH = (SYS->GPC_MFPH & (~SPI3_MISO_PC12_Msk)) | SPI3_MISO_PC12 /*!< Set PC12 function to SPI3_MISO */ +#define SET_SPI3_MISO_PB9() SYS->GPB_MFPH = (SYS->GPB_MFPH & (~SPI3_MISO_PB9_Msk)) | SPI3_MISO_PB9 /*!< Set PB9 function to SPI3_MISO */ +#define SET_SPI3_MOSI_PC11() SYS->GPC_MFPH = (SYS->GPC_MFPH & (~SPI3_MOSI_PC11_Msk)) | SPI3_MOSI_PC11 /*!< Set PC11 function to SPI3_MOSI */ +#define SET_SPI3_MOSI_PE2() SYS->GPE_MFPL = (SYS->GPE_MFPL & (~SPI3_MOSI_PE2_Msk)) | SPI3_MOSI_PE2 /*!< Set PE2 function to SPI3_MOSI */ +#define SET_SPI3_MOSI_PB8() SYS->GPB_MFPH = (SYS->GPB_MFPH & (~SPI3_MOSI_PB8_Msk)) | SPI3_MOSI_PB8 /*!< Set PB8 function to SPI3_MOSI */ +#define SET_SPI3_SS_PE5() SYS->GPE_MFPL = (SYS->GPE_MFPL & (~SPI3_SS_PE5_Msk)) | SPI3_SS_PE5 /*!< Set PE5 function to SPI3_SS */ +#define SET_SPI3_SS_PB10() SYS->GPB_MFPH = (SYS->GPB_MFPH & (~SPI3_SS_PB10_Msk)) | SPI3_SS_PB10 /*!< Set PB10 function to SPI3_SS */ +#define SET_SPI3_SS_PC9() SYS->GPC_MFPH = (SYS->GPC_MFPH & (~SPI3_SS_PC9_Msk)) | SPI3_SS_PC9 /*!< Set PC9 function to SPI3_SS */ +#define SET_TAMPER0_PF6() SYS->GPF_MFPL = (SYS->GPF_MFPL & (~TAMPER0_PF6_Msk)) | TAMPER0_PF6 /*!< Set PF6 function to TAMPER0 */ +#define SET_TAMPER1_PF7() SYS->GPF_MFPL = (SYS->GPF_MFPL & (~TAMPER1_PF7_Msk)) | TAMPER1_PF7 /*!< Set PF7 function to TAMPER1 */ +#define SET_TAMPER2_PF8() SYS->GPF_MFPH = (SYS->GPF_MFPH & (~TAMPER2_PF8_Msk)) | TAMPER2_PF8 /*!< Set PF8 function to TAMPER2 */ +#define SET_TAMPER3_PF9() SYS->GPF_MFPH = (SYS->GPF_MFPH & (~TAMPER3_PF9_Msk)) | TAMPER3_PF9 /*!< Set PF9 function to TAMPER3 */ +#define SET_TAMPER4_PF10() SYS->GPF_MFPH = (SYS->GPF_MFPH & (~TAMPER4_PF10_Msk)) | TAMPER4_PF10 /*!< Set PF10 function to TAMPER4 */ +#define SET_TAMPER5_PF11() SYS->GPF_MFPH = (SYS->GPF_MFPH & (~TAMPER5_PF11_Msk)) | TAMPER5_PF11 /*!< Set PF11 function to TAMPER5 */ +#define SET_TM0_PG2() SYS->GPG_MFPL = (SYS->GPG_MFPL & (~TM0_PG2_Msk)) | TM0_PG2 /*!< Set PG2 function to TM0 */ +#define SET_TM0_PB5() SYS->GPB_MFPL = (SYS->GPB_MFPL & (~TM0_PB5_Msk)) | TM0_PB5 /*!< Set PB5 function to TM0 */ +#define SET_TM0_PC7() SYS->GPC_MFPL = (SYS->GPC_MFPL & (~TM0_PC7_Msk)) | TM0_PC7 /*!< Set PC7 function to TM0 */ +#define SET_TM0_EXT_PB15() SYS->GPB_MFPH = (SYS->GPB_MFPH & (~TM0_EXT_PB15_Msk)) | TM0_EXT_PB15 /*!< Set PB15 function to TM0_EXT */ +#define SET_TM0_EXT_PA11() SYS->GPA_MFPH = (SYS->GPA_MFPH & (~TM0_EXT_PA11_Msk)) | TM0_EXT_PA11 /*!< Set PA11 function to TM0_EXT */ +#define SET_TM1_PC6() SYS->GPC_MFPL = (SYS->GPC_MFPL & (~TM1_PC6_Msk)) | TM1_PC6 /*!< Set PC6 function to TM1 */ +#define SET_TM1_PB4() SYS->GPB_MFPL = (SYS->GPB_MFPL & (~TM1_PB4_Msk)) | TM1_PB4 /*!< Set PB4 function to TM1 */ +#define SET_TM1_PG3() SYS->GPG_MFPL = (SYS->GPG_MFPL & (~TM1_PG3_Msk)) | TM1_PG3 /*!< Set PG3 function to TM1 */ +#define SET_TM1_EXT_PB14() SYS->GPB_MFPH = (SYS->GPB_MFPH & (~TM1_EXT_PB14_Msk)) | TM1_EXT_PB14 /*!< Set PB14 function to TM1_EXT */ +#define SET_TM1_EXT_PA10() SYS->GPA_MFPH = (SYS->GPA_MFPH & (~TM1_EXT_PA10_Msk)) | TM1_EXT_PA10 /*!< Set PA10 function to TM1_EXT */ +#define SET_TM2_PB3() SYS->GPB_MFPL = (SYS->GPB_MFPL & (~TM2_PB3_Msk)) | TM2_PB3 /*!< Set PB3 function to TM2 */ +#define SET_TM2_PA7() SYS->GPA_MFPL = (SYS->GPA_MFPL & (~TM2_PA7_Msk)) | TM2_PA7 /*!< Set PA7 function to TM2 */ +#define SET_TM2_PD0() SYS->GPD_MFPL = (SYS->GPD_MFPL & (~TM2_PD0_Msk)) | TM2_PD0 /*!< Set PD0 function to TM2 */ +#define SET_TM2_PG4() SYS->GPG_MFPL = (SYS->GPG_MFPL & (~TM2_PG4_Msk)) | TM2_PG4 /*!< Set PG4 function to TM2 */ +#define SET_TM2_EXT_PB13() SYS->GPB_MFPH = (SYS->GPB_MFPH & (~TM2_EXT_PB13_Msk)) | TM2_EXT_PB13 /*!< Set PB13 function to TM2_EXT */ +#define SET_TM2_EXT_PA9() SYS->GPA_MFPH = (SYS->GPA_MFPH & (~TM2_EXT_PA9_Msk)) | TM2_EXT_PA9 /*!< Set PA9 function to TM2_EXT */ +#define SET_TM3_PB2() SYS->GPB_MFPL = (SYS->GPB_MFPL & (~TM3_PB2_Msk)) | TM3_PB2 /*!< Set PB2 function to TM3 */ +#define SET_TM3_PA6() SYS->GPA_MFPL = (SYS->GPA_MFPL & (~TM3_PA6_Msk)) | TM3_PA6 /*!< Set PA6 function to TM3 */ +#define SET_TM3_PF11() SYS->GPF_MFPH = (SYS->GPF_MFPH & (~TM3_PF11_Msk)) | TM3_PF11 /*!< Set PF11 function to TM3 */ +#define SET_TM3_EXT_PB12() SYS->GPB_MFPH = (SYS->GPB_MFPH & (~TM3_EXT_PB12_Msk)) | TM3_EXT_PB12 /*!< Set PB12 function to TM3_EXT */ +#define SET_TM3_EXT_PA8() SYS->GPA_MFPH = (SYS->GPA_MFPH & (~TM3_EXT_PA8_Msk)) | TM3_EXT_PA8 /*!< Set PA8 function to TM3_EXT */ +#define SET_TM4_PA7() SYS->GPA_MFPL = (SYS->GPA_MFPL & (~TM4_PA7_Msk)) | TM4_PA7 /*!< Set PA7 function to TM4 */ +#define SET_TM4_PG4() SYS->GPG_MFPL = (SYS->GPG_MFPL & (~TM4_PG4_Msk)) | TM4_PG4 /*!< Set PG4 function to TM4 */ +#define SET_TM4_PB3() SYS->GPB_MFPL = (SYS->GPB_MFPL & (~TM4_PB3_Msk)) | TM4_PB3 /*!< Set PB3 function to TM4 */ +#define SET_TM4_EXT_PB13() SYS->GPB_MFPH = (SYS->GPB_MFPH & (~TM4_EXT_PB13_Msk)) | TM4_EXT_PB13 /*!< Set PB13 function to TM4_EXT */ +#define SET_TM4_EXT_PA9() SYS->GPA_MFPH = (SYS->GPA_MFPH & (~TM4_EXT_PA9_Msk)) | TM4_EXT_PA9 /*!< Set PA9 function to TM4_EXT */ +#define SET_TM5_PF11() SYS->GPF_MFPH = (SYS->GPF_MFPH & (~TM5_PF11_Msk)) | TM5_PF11 /*!< Set PF11 function to TM5 */ +#define SET_TM5_PB2() SYS->GPB_MFPL = (SYS->GPB_MFPL & (~TM5_PB2_Msk)) | TM5_PB2 /*!< Set PB2 function to TM5 */ +#define SET_TM5_PA6() SYS->GPA_MFPL = (SYS->GPA_MFPL & (~TM5_PA6_Msk)) | TM5_PA6 /*!< Set PA6 function to TM5 */ +#define SET_TM5_EXT_PA8() SYS->GPA_MFPH = (SYS->GPA_MFPH & (~TM5_EXT_PA8_Msk)) | TM5_EXT_PA8 /*!< Set PA8 function to TM5_EXT */ +#define SET_TM5_EXT_PB12() SYS->GPB_MFPH = (SYS->GPB_MFPH & (~TM5_EXT_PB12_Msk)) | TM5_EXT_PB12 /*!< Set PB12 function to TM5_EXT */ +#define SET_TRACE_CLK_PE12() SYS->GPE_MFPH = (SYS->GPE_MFPH & (~TRACE_CLK_PE12_Msk)) | TRACE_CLK_PE12 /*!< Set PE12 function to TRACE_CLK */ +#define SET_TRACE_DATA0_PE11() SYS->GPE_MFPH = (SYS->GPE_MFPH & (~TRACE_DATA0_PE11_Msk)) | TRACE_DATA0_PE11 /*!< Set PE11 function to TRACE_DATA0 */ +#define SET_TRACE_DATA1_PE10() SYS->GPE_MFPH = (SYS->GPE_MFPH & (~TRACE_DATA1_PE10_Msk)) | TRACE_DATA1_PE10 /*!< Set PE10 function to TRACE_DATA1 */ +#define SET_TRACE_DATA2_PE9() SYS->GPE_MFPH = (SYS->GPE_MFPH & (~TRACE_DATA2_PE9_Msk)) | TRACE_DATA2_PE9 /*!< Set PE9 function to TRACE_DATA2 */ +#define SET_TRACE_DATA3_PE8() SYS->GPE_MFPH = (SYS->GPE_MFPH & (~TRACE_DATA3_PE8_Msk)) | TRACE_DATA3_PE8 /*!< Set PE8 function to TRACE_DATA3 */ +#define SET_UART0_RXD_PA15() SYS->GPA_MFPH = (SYS->GPA_MFPH & (~UART0_RXD_PA15_Msk)) | UART0_RXD_PA15 /*!< Set PA15 function to UART0_RXD */ +#define SET_UART0_RXD_PD2() SYS->GPD_MFPL = (SYS->GPD_MFPL & (~UART0_RXD_PD2_Msk)) | UART0_RXD_PD2 /*!< Set PD2 function to UART0_RXD */ +#define SET_UART0_RXD_PA4() SYS->GPA_MFPL = (SYS->GPA_MFPL & (~UART0_RXD_PA4_Msk)) | UART0_RXD_PA4 /*!< Set PA4 function to UART0_RXD */ +#define SET_UART0_RXD_PB12() SYS->GPB_MFPH = (SYS->GPB_MFPH & (~UART0_RXD_PB12_Msk)) | UART0_RXD_PB12 /*!< Set PB12 function to UART0_RXD */ +#define SET_UART0_RXD_PA0() SYS->GPA_MFPL = (SYS->GPA_MFPL & (~UART0_RXD_PA0_Msk)) | UART0_RXD_PA0 /*!< Set PA0 function to UART0_RXD */ +#define SET_UART0_RXD_PF1() SYS->GPF_MFPL = (SYS->GPF_MFPL & (~UART0_RXD_PF1_Msk)) | UART0_RXD_PF1 /*!< Set PF1 function to UART0_RXD */ +#define SET_UART0_RXD_PC11() SYS->GPC_MFPH = (SYS->GPC_MFPH & (~UART0_RXD_PC11_Msk)) | UART0_RXD_PC11 /*!< Set PC11 function to UART0_RXD */ +#define SET_UART0_RXD_PB8() SYS->GPB_MFPH = (SYS->GPB_MFPH & (~UART0_RXD_PB8_Msk)) | UART0_RXD_PB8 /*!< Set PB8 function to UART0_RXD */ +#define SET_UART0_RXD_PH11() SYS->GPH_MFPH = (SYS->GPH_MFPH & (~UART0_RXD_PH11_Msk)) | UART0_RXD_PH11 /*!< Set PH11 function to UART0_RXD */ +#define SET_UART0_RXD_PA6() SYS->GPA_MFPL = (SYS->GPA_MFPL & (~UART0_RXD_PA6_Msk)) | UART0_RXD_PA6 /*!< Set PA6 function to UART0_RXD */ +#define SET_UART0_RXD_PF2() SYS->GPF_MFPL = (SYS->GPF_MFPL & (~UART0_RXD_PF2_Msk)) | UART0_RXD_PF2 /*!< Set PF2 function to UART0_RXD */ +#define SET_UART0_TXD_PA5() SYS->GPA_MFPL = (SYS->GPA_MFPL & (~UART0_TXD_PA5_Msk)) | UART0_TXD_PA5 /*!< Set PA5 function to UART0_TXD */ +#define SET_UART0_TXD_PA14() SYS->GPA_MFPH = (SYS->GPA_MFPH & (~UART0_TXD_PA14_Msk)) | UART0_TXD_PA14 /*!< Set PA14 function to UART0_TXD */ +#define SET_UART0_TXD_PF3() SYS->GPF_MFPL = (SYS->GPF_MFPL & (~UART0_TXD_PF3_Msk)) | UART0_TXD_PF3 /*!< Set PF3 function to UART0_TXD */ +#define SET_UART0_TXD_PA1() SYS->GPA_MFPL = (SYS->GPA_MFPL & (~UART0_TXD_PA1_Msk)) | UART0_TXD_PA1 /*!< Set PA1 function to UART0_TXD */ +#define SET_UART0_TXD_PH10() SYS->GPH_MFPH = (SYS->GPH_MFPH & (~UART0_TXD_PH10_Msk)) | UART0_TXD_PH10 /*!< Set PH10 function to UART0_TXD */ +#define SET_UART0_TXD_PD3() SYS->GPD_MFPL = (SYS->GPD_MFPL & (~UART0_TXD_PD3_Msk)) | UART0_TXD_PD3 /*!< Set PD3 function to UART0_TXD */ +#define SET_UART0_TXD_PB9() SYS->GPB_MFPH = (SYS->GPB_MFPH & (~UART0_TXD_PB9_Msk)) | UART0_TXD_PB9 /*!< Set PB9 function to UART0_TXD */ +#define SET_UART0_TXD_PB13() SYS->GPB_MFPH = (SYS->GPB_MFPH & (~UART0_TXD_PB13_Msk)) | UART0_TXD_PB13 /*!< Set PB13 function to UART0_TXD */ +#define SET_UART0_TXD_PA7() SYS->GPA_MFPL = (SYS->GPA_MFPL & (~UART0_TXD_PA7_Msk)) | UART0_TXD_PA7 /*!< Set PA7 function to UART0_TXD */ +#define SET_UART0_TXD_PF0() SYS->GPF_MFPL = (SYS->GPF_MFPL & (~UART0_TXD_PF0_Msk)) | UART0_TXD_PF0 /*!< Set PF0 function to UART0_TXD */ +#define SET_UART0_TXD_PC12() SYS->GPC_MFPH = (SYS->GPC_MFPH & (~UART0_TXD_PC12_Msk)) | UART0_TXD_PC12 /*!< Set PC12 function to UART0_TXD */ +#define SET_UART0_nCTS_PB15() SYS->GPB_MFPH = (SYS->GPB_MFPH & (~UART0_nCTS_PB15_Msk)) | UART0_nCTS_PB15 /*!< Set PB15 function to UART0_nCTS */ +#define SET_UART0_nCTS_PB11() SYS->GPB_MFPH = (SYS->GPB_MFPH & (~UART0_nCTS_PB11_Msk)) | UART0_nCTS_PB11 /*!< Set PB11 function to UART0_nCTS */ +#define SET_UART0_nCTS_PC7() SYS->GPC_MFPL = (SYS->GPC_MFPL & (~UART0_nCTS_PC7_Msk)) | UART0_nCTS_PC7 /*!< Set PC7 function to UART0_nCTS */ +#define SET_UART0_nCTS_PA5() SYS->GPA_MFPL = (SYS->GPA_MFPL & (~UART0_nCTS_PA5_Msk)) | UART0_nCTS_PA5 /*!< Set PA5 function to UART0_nCTS */ +#define SET_UART0_nRTS_PC6() SYS->GPC_MFPL = (SYS->GPC_MFPL & (~UART0_nRTS_PC6_Msk)) | UART0_nRTS_PC6 /*!< Set PC6 function to UART0_nRTS */ +#define SET_UART0_nRTS_PB14() SYS->GPB_MFPH = (SYS->GPB_MFPH & (~UART0_nRTS_PB14_Msk)) | UART0_nRTS_PB14 /*!< Set PB14 function to UART0_nRTS */ +#define SET_UART0_nRTS_PB10() SYS->GPB_MFPH = (SYS->GPB_MFPH & (~UART0_nRTS_PB10_Msk)) | UART0_nRTS_PB10 /*!< Set PB10 function to UART0_nRTS */ +#define SET_UART0_nRTS_PA4() SYS->GPA_MFPL = (SYS->GPA_MFPL & (~UART0_nRTS_PA4_Msk)) | UART0_nRTS_PA4 /*!< Set PA4 function to UART0_nRTS */ +#define SET_UART1_RXD_PA8() SYS->GPA_MFPH = (SYS->GPA_MFPH & (~UART1_RXD_PA8_Msk)) | UART1_RXD_PA8 /*!< Set PA8 function to UART1_RXD */ +#define SET_UART1_RXD_PB6() SYS->GPB_MFPL = (SYS->GPB_MFPL & (~UART1_RXD_PB6_Msk)) | UART1_RXD_PB6 /*!< Set PB6 function to UART1_RXD */ +#define SET_UART1_RXD_PC8() SYS->GPC_MFPH = (SYS->GPC_MFPH & (~UART1_RXD_PC8_Msk)) | UART1_RXD_PC8 /*!< Set PC8 function to UART1_RXD */ +#define SET_UART1_RXD_PA2() SYS->GPA_MFPL = (SYS->GPA_MFPL & (~UART1_RXD_PA2_Msk)) | UART1_RXD_PA2 /*!< Set PA2 function to UART1_RXD */ +#define SET_UART1_RXD_PH9() SYS->GPH_MFPH = (SYS->GPH_MFPH & (~UART1_RXD_PH9_Msk)) | UART1_RXD_PH9 /*!< Set PH9 function to UART1_RXD */ +#define SET_UART1_RXD_PD10() SYS->GPD_MFPH = (SYS->GPD_MFPH & (~UART1_RXD_PD10_Msk)) | UART1_RXD_PD10 /*!< Set PD10 function to UART1_RXD */ +#define SET_UART1_RXD_PB2() SYS->GPB_MFPL = (SYS->GPB_MFPL & (~UART1_RXD_PB2_Msk)) | UART1_RXD_PB2 /*!< Set PB2 function to UART1_RXD */ +#define SET_UART1_RXD_PD6() SYS->GPD_MFPL = (SYS->GPD_MFPL & (~UART1_RXD_PD6_Msk)) | UART1_RXD_PD6 /*!< Set PD6 function to UART1_RXD */ +#define SET_UART1_RXD_PF1() SYS->GPF_MFPL = (SYS->GPF_MFPL & (~UART1_RXD_PF1_Msk)) | UART1_RXD_PF1 /*!< Set PF1 function to UART1_RXD */ +#define SET_UART1_TXD_PA9() SYS->GPA_MFPH = (SYS->GPA_MFPH & (~UART1_TXD_PA9_Msk)) | UART1_TXD_PA9 /*!< Set PA9 function to UART1_TXD */ +#define SET_UART1_TXD_PD11() SYS->GPD_MFPH = (SYS->GPD_MFPH & (~UART1_TXD_PD11_Msk)) | UART1_TXD_PD11 /*!< Set PD11 function to UART1_TXD */ +#define SET_UART1_TXD_PF0() SYS->GPF_MFPL = (SYS->GPF_MFPL & (~UART1_TXD_PF0_Msk)) | UART1_TXD_PF0 /*!< Set PF0 function to UART1_TXD */ +#define SET_UART1_TXD_PB3() SYS->GPB_MFPL = (SYS->GPB_MFPL & (~UART1_TXD_PB3_Msk)) | UART1_TXD_PB3 /*!< Set PB3 function to UART1_TXD */ +#define SET_UART1_TXD_PH8() SYS->GPH_MFPH = (SYS->GPH_MFPH & (~UART1_TXD_PH8_Msk)) | UART1_TXD_PH8 /*!< Set PH8 function to UART1_TXD */ +#define SET_UART1_TXD_PA3() SYS->GPA_MFPL = (SYS->GPA_MFPL & (~UART1_TXD_PA3_Msk)) | UART1_TXD_PA3 /*!< Set PA3 function to UART1_TXD */ +#define SET_UART1_TXD_PD7() SYS->GPD_MFPL = (SYS->GPD_MFPL & (~UART1_TXD_PD7_Msk)) | UART1_TXD_PD7 /*!< Set PD7 function to UART1_TXD */ +#define SET_UART1_TXD_PE13() SYS->GPE_MFPH = (SYS->GPE_MFPH & (~UART1_TXD_PE13_Msk)) | UART1_TXD_PE13 /*!< Set PE13 function to UART1_TXD */ +#define SET_UART1_TXD_PB7() SYS->GPB_MFPL = (SYS->GPB_MFPL & (~UART1_TXD_PB7_Msk)) | UART1_TXD_PB7 /*!< Set PB7 function to UART1_TXD */ +#define SET_UART1_nCTS_PB9() SYS->GPB_MFPH = (SYS->GPB_MFPH & (~UART1_nCTS_PB9_Msk)) | UART1_nCTS_PB9 /*!< Set PB9 function to UART1_nCTS */ +#define SET_UART1_nCTS_PE11() SYS->GPE_MFPH = (SYS->GPE_MFPH & (~UART1_nCTS_PE11_Msk)) | UART1_nCTS_PE11 /*!< Set PE11 function to UART1_nCTS */ +#define SET_UART1_nCTS_PA1() SYS->GPA_MFPL = (SYS->GPA_MFPL & (~UART1_nCTS_PA1_Msk)) | UART1_nCTS_PA1 /*!< Set PA1 function to UART1_nCTS */ +#define SET_UART1_nRTS_PB8() SYS->GPB_MFPH = (SYS->GPB_MFPH & (~UART1_nRTS_PB8_Msk)) | UART1_nRTS_PB8 /*!< Set PB8 function to UART1_nRTS */ +#define SET_UART1_nRTS_PA0() SYS->GPA_MFPL = (SYS->GPA_MFPL & (~UART1_nRTS_PA0_Msk)) | UART1_nRTS_PA0 /*!< Set PA0 function to UART1_nRTS */ +#define SET_UART1_nRTS_PE12() SYS->GPE_MFPH = (SYS->GPE_MFPH & (~UART1_nRTS_PE12_Msk)) | UART1_nRTS_PE12 /*!< Set PE12 function to UART1_nRTS */ +#define SET_UART2_RXD_PE15() SYS->GPE_MFPH = (SYS->GPE_MFPH & (~UART2_RXD_PE15_Msk)) | UART2_RXD_PE15 /*!< Set PE15 function to UART2_RXD */ +#define SET_UART2_RXD_PC4() SYS->GPC_MFPL = (SYS->GPC_MFPL & (~UART2_RXD_PC4_Msk)) | UART2_RXD_PC4 /*!< Set PC4 function to UART2_RXD */ +#define SET_UART2_RXD_PD12() SYS->GPD_MFPH = (SYS->GPD_MFPH & (~UART2_RXD_PD12_Msk)) | UART2_RXD_PD12 /*!< Set PD12 function to UART2_RXD */ +#define SET_UART2_RXD_PF5() SYS->GPF_MFPL = (SYS->GPF_MFPL & (~UART2_RXD_PF5_Msk)) | UART2_RXD_PF5 /*!< Set PF5 function to UART2_RXD */ +#define SET_UART2_RXD_PE9() SYS->GPE_MFPH = (SYS->GPE_MFPH & (~UART2_RXD_PE9_Msk)) | UART2_RXD_PE9 /*!< Set PE9 function to UART2_RXD */ +#define SET_UART2_RXD_PC0() SYS->GPC_MFPL = (SYS->GPC_MFPL & (~UART2_RXD_PC0_Msk)) | UART2_RXD_PC0 /*!< Set PC0 function to UART2_RXD */ +#define SET_UART2_RXD_PB0() SYS->GPB_MFPL = (SYS->GPB_MFPL & (~UART2_RXD_PB0_Msk)) | UART2_RXD_PB0 /*!< Set PB0 function to UART2_RXD */ +#define SET_UART2_RXD_PB4() SYS->GPB_MFPL = (SYS->GPB_MFPL & (~UART2_RXD_PB4_Msk)) | UART2_RXD_PB4 /*!< Set PB4 function to UART2_RXD */ +#define SET_UART2_TXD_PF4() SYS->GPF_MFPL = (SYS->GPF_MFPL & (~UART2_TXD_PF4_Msk)) | UART2_TXD_PF4 /*!< Set PF4 function to UART2_TXD */ +#define SET_UART2_TXD_PC1() SYS->GPC_MFPL = (SYS->GPC_MFPL & (~UART2_TXD_PC1_Msk)) | UART2_TXD_PC1 /*!< Set PC1 function to UART2_TXD */ +#define SET_UART2_TXD_PB5() SYS->GPB_MFPL = (SYS->GPB_MFPL & (~UART2_TXD_PB5_Msk)) | UART2_TXD_PB5 /*!< Set PB5 function to UART2_TXD */ +#define SET_UART2_TXD_PE14() SYS->GPE_MFPH = (SYS->GPE_MFPH & (~UART2_TXD_PE14_Msk)) | UART2_TXD_PE14 /*!< Set PE14 function to UART2_TXD */ +#define SET_UART2_TXD_PC13() SYS->GPC_MFPH = (SYS->GPC_MFPH & (~UART2_TXD_PC13_Msk)) | UART2_TXD_PC13 /*!< Set PC13 function to UART2_TXD */ +#define SET_UART2_TXD_PC5() SYS->GPC_MFPL = (SYS->GPC_MFPL & (~UART2_TXD_PC5_Msk)) | UART2_TXD_PC5 /*!< Set PC5 function to UART2_TXD */ +#define SET_UART2_TXD_PE8() SYS->GPE_MFPH = (SYS->GPE_MFPH & (~UART2_TXD_PE8_Msk)) | UART2_TXD_PE8 /*!< Set PE8 function to UART2_TXD */ +#define SET_UART2_TXD_PB1() SYS->GPB_MFPL = (SYS->GPB_MFPL & (~UART2_TXD_PB1_Msk)) | UART2_TXD_PB1 /*!< Set PB1 function to UART2_TXD */ +#define SET_UART2_nCTS_PF5() SYS->GPF_MFPL = (SYS->GPF_MFPL & (~UART2_nCTS_PF5_Msk)) | UART2_nCTS_PF5 /*!< Set PF5 function to UART2_nCTS */ +#define SET_UART2_nCTS_PD9() SYS->GPD_MFPH = (SYS->GPD_MFPH & (~UART2_nCTS_PD9_Msk)) | UART2_nCTS_PD9 /*!< Set PD9 function to UART2_nCTS */ +#define SET_UART2_nCTS_PC2() SYS->GPC_MFPL = (SYS->GPC_MFPL & (~UART2_nCTS_PC2_Msk)) | UART2_nCTS_PC2 /*!< Set PC2 function to UART2_nCTS */ +#define SET_UART2_nRTS_PC3() SYS->GPC_MFPL = (SYS->GPC_MFPL & (~UART2_nRTS_PC3_Msk)) | UART2_nRTS_PC3 /*!< Set PC3 function to UART2_nRTS */ +#define SET_UART2_nRTS_PD8() SYS->GPD_MFPH = (SYS->GPD_MFPH & (~UART2_nRTS_PD8_Msk)) | UART2_nRTS_PD8 /*!< Set PD8 function to UART2_nRTS */ +#define SET_UART2_nRTS_PF4() SYS->GPF_MFPL = (SYS->GPF_MFPL & (~UART2_nRTS_PF4_Msk)) | UART2_nRTS_PF4 /*!< Set PF4 function to UART2_nRTS */ +#define SET_UART3_RXD_PD0() SYS->GPD_MFPL = (SYS->GPD_MFPL & (~UART3_RXD_PD0_Msk)) | UART3_RXD_PD0 /*!< Set PD0 function to UART3_RXD */ +#define SET_UART3_RXD_PC9() SYS->GPC_MFPH = (SYS->GPC_MFPH & (~UART3_RXD_PC9_Msk)) | UART3_RXD_PC9 /*!< Set PC9 function to UART3_RXD */ +#define SET_UART3_RXD_PE0() SYS->GPE_MFPL = (SYS->GPE_MFPL & (~UART3_RXD_PE0_Msk)) | UART3_RXD_PE0 /*!< Set PE0 function to UART3_RXD */ +#define SET_UART3_RXD_PC2() SYS->GPC_MFPL = (SYS->GPC_MFPL & (~UART3_RXD_PC2_Msk)) | UART3_RXD_PC2 /*!< Set PC2 function to UART3_RXD */ +#define SET_UART3_RXD_PB14() SYS->GPB_MFPH = (SYS->GPB_MFPH & (~UART3_RXD_PB14_Msk)) | UART3_RXD_PB14 /*!< Set PB14 function to UART3_RXD */ +#define SET_UART3_RXD_PE11() SYS->GPE_MFPH = (SYS->GPE_MFPH & (~UART3_RXD_PE11_Msk)) | UART3_RXD_PE11 /*!< Set PE11 function to UART3_RXD */ +#define SET_UART3_TXD_PC10() SYS->GPC_MFPH = (SYS->GPC_MFPH & (~UART3_TXD_PC10_Msk)) | UART3_TXD_PC10 /*!< Set PC10 function to UART3_TXD */ +#define SET_UART3_TXD_PB15() SYS->GPB_MFPH = (SYS->GPB_MFPH & (~UART3_TXD_PB15_Msk)) | UART3_TXD_PB15 /*!< Set PB15 function to UART3_TXD */ +#define SET_UART3_TXD_PE10() SYS->GPE_MFPH = (SYS->GPE_MFPH & (~UART3_TXD_PE10_Msk)) | UART3_TXD_PE10 /*!< Set PE10 function to UART3_TXD */ +#define SET_UART3_TXD_PC3() SYS->GPC_MFPL = (SYS->GPC_MFPL & (~UART3_TXD_PC3_Msk)) | UART3_TXD_PC3 /*!< Set PC3 function to UART3_TXD */ +#define SET_UART3_TXD_PD1() SYS->GPD_MFPL = (SYS->GPD_MFPL & (~UART3_TXD_PD1_Msk)) | UART3_TXD_PD1 /*!< Set PD1 function to UART3_TXD */ +#define SET_UART3_TXD_PE1() SYS->GPE_MFPL = (SYS->GPE_MFPL & (~UART3_TXD_PE1_Msk)) | UART3_TXD_PE1 /*!< Set PE1 function to UART3_TXD */ +#define SET_UART3_nCTS_PB12() SYS->GPB_MFPH = (SYS->GPB_MFPH & (~UART3_nCTS_PB12_Msk)) | UART3_nCTS_PB12 /*!< Set PB12 function to UART3_nCTS */ +#define SET_UART3_nCTS_PH9() SYS->GPH_MFPH = (SYS->GPH_MFPH & (~UART3_nCTS_PH9_Msk)) | UART3_nCTS_PH9 /*!< Set PH9 function to UART3_nCTS */ +#define SET_UART3_nCTS_PD2() SYS->GPD_MFPL = (SYS->GPD_MFPL & (~UART3_nCTS_PD2_Msk)) | UART3_nCTS_PD2 /*!< Set PD2 function to UART3_nCTS */ +#define SET_UART3_nRTS_PH8() SYS->GPH_MFPH = (SYS->GPH_MFPH & (~UART3_nRTS_PH8_Msk)) | UART3_nRTS_PH8 /*!< Set PH8 function to UART3_nRTS */ +#define SET_UART3_nRTS_PD3() SYS->GPD_MFPL = (SYS->GPD_MFPL & (~UART3_nRTS_PD3_Msk)) | UART3_nRTS_PD3 /*!< Set PD3 function to UART3_nRTS */ +#define SET_UART3_nRTS_PB13() SYS->GPB_MFPH = (SYS->GPB_MFPH & (~UART3_nRTS_PB13_Msk)) | UART3_nRTS_PB13 /*!< Set PB13 function to UART3_nRTS */ +#define SET_UART4_RXD_PA2() SYS->GPA_MFPL = (SYS->GPA_MFPL & (~UART4_RXD_PA2_Msk)) | UART4_RXD_PA2 /*!< Set PA2 function to UART4_RXD */ +#define SET_UART4_RXD_PA13() SYS->GPA_MFPH = (SYS->GPA_MFPH & (~UART4_RXD_PA13_Msk)) | UART4_RXD_PA13 /*!< Set PA13 function to UART4_RXD */ +#define SET_UART4_RXD_PC4() SYS->GPC_MFPL = (SYS->GPC_MFPL & (~UART4_RXD_PC4_Msk)) | UART4_RXD_PC4 /*!< Set PC4 function to UART4_RXD */ +#define SET_UART4_RXD_PH11() SYS->GPH_MFPH = (SYS->GPH_MFPH & (~UART4_RXD_PH11_Msk)) | UART4_RXD_PH11 /*!< Set PH11 function to UART4_RXD */ +#define SET_UART4_RXD_PF6() SYS->GPF_MFPL = (SYS->GPF_MFPL & (~UART4_RXD_PF6_Msk)) | UART4_RXD_PF6 /*!< Set PF6 function to UART4_RXD */ +#define SET_UART4_RXD_PB10() SYS->GPB_MFPH = (SYS->GPB_MFPH & (~UART4_RXD_PB10_Msk)) | UART4_RXD_PB10 /*!< Set PB10 function to UART4_RXD */ +#define SET_UART4_RXD_PC6() SYS->GPC_MFPL = (SYS->GPC_MFPL & (~UART4_RXD_PC6_Msk)) | UART4_RXD_PC6 /*!< Set PC6 function to UART4_RXD */ +#define SET_UART4_TXD_PA3() SYS->GPA_MFPL = (SYS->GPA_MFPL & (~UART4_TXD_PA3_Msk)) | UART4_TXD_PA3 /*!< Set PA3 function to UART4_TXD */ +#define SET_UART4_TXD_PC5() SYS->GPC_MFPL = (SYS->GPC_MFPL & (~UART4_TXD_PC5_Msk)) | UART4_TXD_PC5 /*!< Set PC5 function to UART4_TXD */ +#define SET_UART4_TXD_PC7() SYS->GPC_MFPL = (SYS->GPC_MFPL & (~UART4_TXD_PC7_Msk)) | UART4_TXD_PC7 /*!< Set PC7 function to UART4_TXD */ +#define SET_UART4_TXD_PA12() SYS->GPA_MFPH = (SYS->GPA_MFPH & (~UART4_TXD_PA12_Msk)) | UART4_TXD_PA12 /*!< Set PA12 function to UART4_TXD */ +#define SET_UART4_TXD_PF7() SYS->GPF_MFPL = (SYS->GPF_MFPL & (~UART4_TXD_PF7_Msk)) | UART4_TXD_PF7 /*!< Set PF7 function to UART4_TXD */ +#define SET_UART4_TXD_PH10() SYS->GPH_MFPH = (SYS->GPH_MFPH & (~UART4_TXD_PH10_Msk)) | UART4_TXD_PH10 /*!< Set PH10 function to UART4_TXD */ +#define SET_UART4_TXD_PB11() SYS->GPB_MFPH = (SYS->GPB_MFPH & (~UART4_TXD_PB11_Msk)) | UART4_TXD_PB11 /*!< Set PB11 function to UART4_TXD */ +#define SET_UART4_nCTS_PC8() SYS->GPC_MFPH = (SYS->GPC_MFPH & (~UART4_nCTS_PC8_Msk)) | UART4_nCTS_PC8 /*!< Set PC8 function to UART4_nCTS */ +#define SET_UART4_nCTS_PE1() SYS->GPE_MFPL = (SYS->GPE_MFPL & (~UART4_nCTS_PE1_Msk)) | UART4_nCTS_PE1 /*!< Set PE1 function to UART4_nCTS */ +#define SET_UART4_nRTS_PE0() SYS->GPE_MFPL = (SYS->GPE_MFPL & (~UART4_nRTS_PE0_Msk)) | UART4_nRTS_PE0 /*!< Set PE0 function to UART4_nRTS */ +#define SET_UART4_nRTS_PE13() SYS->GPE_MFPH = (SYS->GPE_MFPH & (~UART4_nRTS_PE13_Msk)) | UART4_nRTS_PE13 /*!< Set PE13 function to UART4_nRTS */ +#define SET_UART5_RXD_PB4() SYS->GPB_MFPL = (SYS->GPB_MFPL & (~UART5_RXD_PB4_Msk)) | UART5_RXD_PB4 /*!< Set PB4 function to UART5_RXD */ +#define SET_UART5_RXD_PF10() SYS->GPF_MFPH = (SYS->GPF_MFPH & (~UART5_RXD_PF10_Msk)) | UART5_RXD_PF10 /*!< Set PF10 function to UART5_RXD */ +#define SET_UART5_RXD_PE6() SYS->GPE_MFPL = (SYS->GPE_MFPL & (~UART5_RXD_PE6_Msk)) | UART5_RXD_PE6 /*!< Set PE6 function to UART5_RXD */ +#define SET_UART5_RXD_PA4() SYS->GPA_MFPL = (SYS->GPA_MFPL & (~UART5_RXD_PA4_Msk)) | UART5_RXD_PA4 /*!< Set PA4 function to UART5_RXD */ +#define SET_UART5_TXD_PF11() SYS->GPF_MFPH = (SYS->GPF_MFPH & (~UART5_TXD_PF11_Msk)) | UART5_TXD_PF11 /*!< Set PF11 function to UART5_TXD */ +#define SET_UART5_TXD_PB5() SYS->GPB_MFPL = (SYS->GPB_MFPL & (~UART5_TXD_PB5_Msk)) | UART5_TXD_PB5 /*!< Set PB5 function to UART5_TXD */ +#define SET_UART5_TXD_PE7() SYS->GPE_MFPL = (SYS->GPE_MFPL & (~UART5_TXD_PE7_Msk)) | UART5_TXD_PE7 /*!< Set PE7 function to UART5_TXD */ +#define SET_UART5_TXD_PA5() SYS->GPA_MFPL = (SYS->GPA_MFPL & (~UART5_TXD_PA5_Msk)) | UART5_TXD_PA5 /*!< Set PA5 function to UART5_TXD */ +#define SET_UART5_nCTS_PB2() SYS->GPB_MFPL = (SYS->GPB_MFPL & (~UART5_nCTS_PB2_Msk)) | UART5_nCTS_PB2 /*!< Set PB2 function to UART5_nCTS */ +#define SET_UART5_nCTS_PF8() SYS->GPF_MFPH = (SYS->GPF_MFPH & (~UART5_nCTS_PF8_Msk)) | UART5_nCTS_PF8 /*!< Set PF8 function to UART5_nCTS */ +#define SET_UART5_nRTS_PF9() SYS->GPF_MFPH = (SYS->GPF_MFPH & (~UART5_nRTS_PF9_Msk)) | UART5_nRTS_PF9 /*!< Set PF9 function to UART5_nRTS */ +#define SET_UART5_nRTS_PB3() SYS->GPB_MFPL = (SYS->GPB_MFPL & (~UART5_nRTS_PB3_Msk)) | UART5_nRTS_PB3 /*!< Set PB3 function to UART5_nRTS */ +#define SET_USB_D_P_PA14() SYS->GPA_MFPH = (SYS->GPA_MFPH & (~USB_D_P_PA14_Msk)) | USB_D_P_PA14 /*!< Set PA14 function to USB_D_P */ +#define SET_USB_D_N_PA13() SYS->GPA_MFPH = (SYS->GPA_MFPH & (~USB_D_N_PA13_Msk)) | USB_D_N_PA13 /*!< Set PA13 function to USB_D_N */ +#define SET_USB_OTG_ID_PA15() SYS->GPA_MFPH = (SYS->GPA_MFPH & (~USB_OTG_ID_PA15_Msk)) | USB_OTG_ID_PA15 /*!< Set PA15 function to USB_OTG_ID */ +#define SET_USB_VBUS_PA12() SYS->GPA_MFPH = (SYS->GPA_MFPH & (~USB_VBUS_PA12_Msk)) | USB_VBUS_PA12 /*!< Set PA12 function to USB_VBUS */ +#define SET_USB_VBUS_EN_PB15() SYS->GPB_MFPH = (SYS->GPB_MFPH & (~USB_VBUS_EN_PB15_Msk)) | USB_VBUS_EN_PB15 /*!< Set PB15 function to USB_VBUS_EN */ +#define SET_USB_VBUS_EN_PB6() SYS->GPB_MFPL = (SYS->GPB_MFPL & (~USB_VBUS_EN_PB6_Msk)) | USB_VBUS_EN_PB6 /*!< Set PB6 function to USB_VBUS_EN */ +#define SET_USB_VBUS_ST_PB14() SYS->GPB_MFPH = (SYS->GPB_MFPH & (~USB_VBUS_ST_PB14_Msk)) | USB_VBUS_ST_PB14 /*!< Set PB14 function to USB_VBUS_ST */ +#define SET_USB_VBUS_ST_PB7() SYS->GPB_MFPL = (SYS->GPB_MFPL & (~USB_VBUS_ST_PB7_Msk)) | USB_VBUS_ST_PB7 /*!< Set PB7 function to USB_VBUS_ST */ +#define SET_USB_VBUS_ST_PD4() SYS->GPD_MFPL = (SYS->GPD_MFPL & (~USB_VBUS_ST_PD4_Msk)) | USB_VBUS_ST_PD4 /*!< Set PD4 function to USB_VBUS_ST */ +#define SET_USCI0_CLK_PA11() SYS->GPA_MFPH = (SYS->GPA_MFPH & (~USCI0_CLK_PA11_Msk)) | USCI0_CLK_PA11 /*!< Set PA11 function to USCI0_CLK */ +#define SET_USCI0_CLK_PD0() SYS->GPD_MFPL = (SYS->GPD_MFPL & (~USCI0_CLK_PD0_Msk)) | USCI0_CLK_PD0 /*!< Set PD0 function to USCI0_CLK */ +#define SET_USCI0_CLK_PB12() SYS->GPB_MFPH = (SYS->GPB_MFPH & (~USCI0_CLK_PB12_Msk)) | USCI0_CLK_PB12 /*!< Set PB12 function to USCI0_CLK */ +#define SET_USCI0_CLK_PE2() SYS->GPE_MFPL = (SYS->GPE_MFPL & (~USCI0_CLK_PE2_Msk)) | USCI0_CLK_PE2 /*!< Set PE2 function to USCI0_CLK */ +#define SET_USCI0_CTL0_PC13() SYS->GPC_MFPH = (SYS->GPC_MFPH & (~USCI0_CTL0_PC13_Msk)) | USCI0_CTL0_PC13 /*!< Set PC13 function to USCI0_CTL0 */ +#define SET_USCI0_CTL0_PD14() SYS->GPD_MFPH = (SYS->GPD_MFPH & (~USCI0_CTL0_PD14_Msk)) | USCI0_CTL0_PD14 /*!< Set PD14 function to USCI0_CTL0 */ +#define SET_USCI0_CTL0_PE6() SYS->GPE_MFPL = (SYS->GPE_MFPL & (~USCI0_CTL0_PE6_Msk)) | USCI0_CTL0_PE6 /*!< Set PE6 function to USCI0_CTL0 */ +#define SET_USCI0_CTL0_PD4() SYS->GPD_MFPL = (SYS->GPD_MFPL & (~USCI0_CTL0_PD4_Msk)) | USCI0_CTL0_PD4 /*!< Set PD4 function to USCI0_CTL0 */ +#define SET_USCI0_CTL1_PD3() SYS->GPD_MFPL = (SYS->GPD_MFPL & (~USCI0_CTL1_PD3_Msk)) | USCI0_CTL1_PD3 /*!< Set PD3 function to USCI0_CTL1 */ +#define SET_USCI0_CTL1_PA8() SYS->GPA_MFPH = (SYS->GPA_MFPH & (~USCI0_CTL1_PA8_Msk)) | USCI0_CTL1_PA8 /*!< Set PA8 function to USCI0_CTL1 */ +#define SET_USCI0_CTL1_PE5() SYS->GPE_MFPL = (SYS->GPE_MFPL & (~USCI0_CTL1_PE5_Msk)) | USCI0_CTL1_PE5 /*!< Set PE5 function to USCI0_CTL1 */ +#define SET_USCI0_CTL1_PB15() SYS->GPB_MFPH = (SYS->GPB_MFPH & (~USCI0_CTL1_PB15_Msk)) | USCI0_CTL1_PB15 /*!< Set PB15 function to USCI0_CTL1 */ +#define SET_USCI0_DAT0_PB13() SYS->GPB_MFPH = (SYS->GPB_MFPH & (~USCI0_DAT0_PB13_Msk)) | USCI0_DAT0_PB13 /*!< Set PB13 function to USCI0_DAT0 */ +#define SET_USCI0_DAT0_PE3() SYS->GPE_MFPL = (SYS->GPE_MFPL & (~USCI0_DAT0_PE3_Msk)) | USCI0_DAT0_PE3 /*!< Set PE3 function to USCI0_DAT0 */ +#define SET_USCI0_DAT0_PA10() SYS->GPA_MFPH = (SYS->GPA_MFPH & (~USCI0_DAT0_PA10_Msk)) | USCI0_DAT0_PA10 /*!< Set PA10 function to USCI0_DAT0 */ +#define SET_USCI0_DAT0_PD1() SYS->GPD_MFPL = (SYS->GPD_MFPL & (~USCI0_DAT0_PD1_Msk)) | USCI0_DAT0_PD1 /*!< Set PD1 function to USCI0_DAT0 */ +#define SET_USCI0_DAT1_PA9() SYS->GPA_MFPH = (SYS->GPA_MFPH & (~USCI0_DAT1_PA9_Msk)) | USCI0_DAT1_PA9 /*!< Set PA9 function to USCI0_DAT1 */ +#define SET_USCI0_DAT1_PE4() SYS->GPE_MFPL = (SYS->GPE_MFPL & (~USCI0_DAT1_PE4_Msk)) | USCI0_DAT1_PE4 /*!< Set PE4 function to USCI0_DAT1 */ +#define SET_USCI0_DAT1_PB14() SYS->GPB_MFPH = (SYS->GPB_MFPH & (~USCI0_DAT1_PB14_Msk)) | USCI0_DAT1_PB14 /*!< Set PB14 function to USCI0_DAT1 */ +#define SET_USCI0_DAT1_PD2() SYS->GPD_MFPL = (SYS->GPD_MFPL & (~USCI0_DAT1_PD2_Msk)) | USCI0_DAT1_PD2 /*!< Set PD2 function to USCI0_DAT1 */ +#define SET_USCI1_CLK_PE12() SYS->GPE_MFPH = (SYS->GPE_MFPH & (~USCI1_CLK_PE12_Msk)) | USCI1_CLK_PE12 /*!< Set PE12 function to USCI1_CLK */ +#define SET_USCI1_CLK_PB1() SYS->GPB_MFPL = (SYS->GPB_MFPL & (~USCI1_CLK_PB1_Msk)) | USCI1_CLK_PB1 /*!< Set PB1 function to USCI1_CLK */ +#define SET_USCI1_CLK_PD7() SYS->GPD_MFPL = (SYS->GPD_MFPL & (~USCI1_CLK_PD7_Msk)) | USCI1_CLK_PD7 /*!< Set PD7 function to USCI1_CLK */ +#define SET_USCI1_CLK_PB8() SYS->GPB_MFPH = (SYS->GPB_MFPH & (~USCI1_CLK_PB8_Msk)) | USCI1_CLK_PB8 /*!< Set PB8 function to USCI1_CLK */ +#define SET_USCI1_CTL0_PE9() SYS->GPE_MFPH = (SYS->GPE_MFPH & (~USCI1_CTL0_PE9_Msk)) | USCI1_CTL0_PE9 /*!< Set PE9 function to USCI1_CTL0 */ +#define SET_USCI1_CTL0_PB5() SYS->GPB_MFPL = (SYS->GPB_MFPL & (~USCI1_CTL0_PB5_Msk)) | USCI1_CTL0_PB5 /*!< Set PB5 function to USCI1_CTL0 */ +#define SET_USCI1_CTL0_PD3() SYS->GPD_MFPL = (SYS->GPD_MFPL & (~USCI1_CTL0_PD3_Msk)) | USCI1_CTL0_PD3 /*!< Set PD3 function to USCI1_CTL0 */ +#define SET_USCI1_CTL0_PB10() SYS->GPB_MFPH = (SYS->GPB_MFPH & (~USCI1_CTL0_PB10_Msk)) | USCI1_CTL0_PB10 /*!< Set PB10 function to USCI1_CTL0 */ +#define SET_USCI1_CTL1_PB4() SYS->GPB_MFPL = (SYS->GPB_MFPL & (~USCI1_CTL1_PB4_Msk)) | USCI1_CTL1_PB4 /*!< Set PB4 function to USCI1_CTL1 */ +#define SET_USCI1_CTL1_PD4() SYS->GPD_MFPL = (SYS->GPD_MFPL & (~USCI1_CTL1_PD4_Msk)) | USCI1_CTL1_PD4 /*!< Set PD4 function to USCI1_CTL1 */ +#define SET_USCI1_CTL1_PE8() SYS->GPE_MFPH = (SYS->GPE_MFPH & (~USCI1_CTL1_PE8_Msk)) | USCI1_CTL1_PE8 /*!< Set PE8 function to USCI1_CTL1 */ +#define SET_USCI1_CTL1_PB9() SYS->GPB_MFPH = (SYS->GPB_MFPH & (~USCI1_CTL1_PB9_Msk)) | USCI1_CTL1_PB9 /*!< Set PB9 function to USCI1_CTL1 */ +#define SET_USCI1_DAT0_PB7() SYS->GPB_MFPL = (SYS->GPB_MFPL & (~USCI1_DAT0_PB7_Msk)) | USCI1_DAT0_PB7 /*!< Set PB7 function to USCI1_DAT0 */ +#define SET_USCI1_DAT0_PE10() SYS->GPE_MFPH = (SYS->GPE_MFPH & (~USCI1_DAT0_PE10_Msk)) | USCI1_DAT0_PE10 /*!< Set PE10 function to USCI1_DAT0 */ +#define SET_USCI1_DAT0_PB2() SYS->GPB_MFPL = (SYS->GPB_MFPL & (~USCI1_DAT0_PB2_Msk)) | USCI1_DAT0_PB2 /*!< Set PB2 function to USCI1_DAT0 */ +#define SET_USCI1_DAT0_PD5() SYS->GPD_MFPL = (SYS->GPD_MFPL & (~USCI1_DAT0_PD5_Msk)) | USCI1_DAT0_PD5 /*!< Set PD5 function to USCI1_DAT0 */ +#define SET_USCI1_DAT1_PD6() SYS->GPD_MFPL = (SYS->GPD_MFPL & (~USCI1_DAT1_PD6_Msk)) | USCI1_DAT1_PD6 /*!< Set PD6 function to USCI1_DAT1 */ +#define SET_USCI1_DAT1_PB6() SYS->GPB_MFPL = (SYS->GPB_MFPL & (~USCI1_DAT1_PB6_Msk)) | USCI1_DAT1_PB6 /*!< Set PB6 function to USCI1_DAT1 */ +#define SET_USCI1_DAT1_PE11() SYS->GPE_MFPH = (SYS->GPE_MFPH & (~USCI1_DAT1_PE11_Msk)) | USCI1_DAT1_PE11 /*!< Set PE11 function to USCI1_DAT1 */ +#define SET_USCI1_DAT1_PB3() SYS->GPB_MFPL = (SYS->GPB_MFPL & (~USCI1_DAT1_PB3_Msk)) | USCI1_DAT1_PB3 /*!< Set PB3 function to USCI1_DAT1 */ +#define SET_X32_IN_PF5() SYS->GPF_MFPL = (SYS->GPF_MFPL & (~X32_IN_PF5_Msk)) | X32_IN_PF5 /*!< Set PF5 function to X32_IN */ +#define SET_X32_OUT_PF4() SYS->GPF_MFPL = (SYS->GPF_MFPL & (~X32_OUT_PF4_Msk)) | X32_OUT_PF4 /*!< Set PF4 function to X32_OUT */ +#define SET_XT1_IN_PF3() SYS->GPF_MFPL = (SYS->GPF_MFPL & (~XT1_IN_PF3_Msk)) | XT1_IN_PF3 /*!< Set PF3 function to XT1_IN */ +#define SET_XT1_OUT_PF2() SYS->GPF_MFPL = (SYS->GPF_MFPL & (~XT1_OUT_PF2_Msk)) | XT1_OUT_PF2 /*!< Set PF2 function to XT1_OUT */ + + +/** + * @brief Clear Brown-out detector interrupt flag + * @param None + * @return None + * @details This macro clear Brown-out detector interrupt flag. + */ +#define SYS_CLEAR_BOD_INT_FLAG() \ + do{ \ + while(SYS->BODCTL & SYS_BODCTL_WRBUSY_Msk); \ + SYS->BODCTL |= SYS_BODCTL_BODIF_Msk; \ + }while(0) + +/** + * @brief Disable Brown-out detector function + * @param None + * @return None + * @details This macro disable Brown-out detector function. + * The register write-protection function should be disabled before using this macro. + */ +#define SYS_DISABLE_BOD() \ + do{ \ + while(SYS->BODCTL & SYS_BODCTL_WRBUSY_Msk); \ + SYS->BODCTL &= ~SYS_BODCTL_BODEN_Msk; \ + }while(0) + +/** + * @brief Enable Brown-out detector function + * @param None + * @return None + * @details This macro enable Brown-out detector function. + * The register write-protection function should be disabled before using this macro. + */ +#define SYS_ENABLE_BOD() \ + do{ \ + while(SYS->BODCTL & SYS_BODCTL_WRBUSY_Msk); \ + SYS->BODCTL |= SYS_BODCTL_BODEN_Msk; \ + }while(0) + +/** + * @brief Get Brown-out detector interrupt flag + * @param None + * @retval 0 Brown-out detect interrupt flag is not set. + * @retval >=1 Brown-out detect interrupt flag is set. + * @details This macro get Brown-out detector interrupt flag. + */ +#define SYS_GET_BOD_INT_FLAG() (SYS->BODCTL & SYS_BODCTL_BODIF_Msk) + +/** + * @brief Get Brown-out detector status + * @param None + * @retval 0 System voltage is higher than BOD threshold voltage setting or BOD function is disabled. + * @retval >=1 System voltage is lower than BOD threshold voltage setting. + * @details This macro get Brown-out detector output status. + * If the BOD function is disabled, this function always return 0. + */ +#define SYS_GET_BOD_OUTPUT() (SYS->BODCTL & SYS_BODCTL_BODOUT_Msk) + +/** + * @brief Enable Brown-out detector interrupt function + * @param None + * @return None + * @details This macro enable Brown-out detector interrupt function. + * The register write-protection function should be disabled before using this macro. + */ +#define SYS_DISABLE_BOD_RST() \ + do{ \ + while(SYS->BODCTL & SYS_BODCTL_WRBUSY_Msk); \ + SYS->BODCTL &= ~SYS_BODCTL_BODRSTEN_Msk; \ + }while(0) + +/** + * @brief Enable Brown-out detector reset function + * @param None + * @return None + * @details This macro enable Brown-out detect reset function. + * The register write-protection function should be disabled before using this macro. + */ +#define SYS_ENABLE_BOD_RST() \ + do{ \ + while(SYS->BODCTL & SYS_BODCTL_WRBUSY_Msk); \ + SYS->BODCTL |= SYS_BODCTL_BODRSTEN_Msk; \ + }while(0) + +/** + * @brief Set Brown-out detector voltage level + * @param[in] u32Level is Brown-out voltage level. Including : + * - \ref SYS_BODCTL_BODVL_1_6V + * - \ref SYS_BODCTL_BODVL_1_8V + * - \ref SYS_BODCTL_BODVL_2_0V + * - \ref SYS_BODCTL_BODVL_2_2V + * - \ref SYS_BODCTL_BODVL_2_4V + * - \ref SYS_BODCTL_BODVL_2_6V + * - \ref SYS_BODCTL_BODVL_2_8V + * - \ref SYS_BODCTL_BODVL_3_0V + * @return None + * @details This macro set Brown-out detector voltage level. + * The write-protection function should be disabled before using this macro. + */ +#define SYS_SET_BOD_LEVEL(u32Level) \ + do{ \ + while(SYS->BODCTL & SYS_BODCTL_WRBUSY_Msk); \ + SYS->BODCTL = (SYS->BODCTL & ~SYS_BODCTL_BODVL_Msk) | (u32Level); \ + }while(0) + +/** + * @brief Get reset source is from Brown-out detector reset + * @param None + * @retval 0 Previous reset source is not from Brown-out detector reset + * @retval >=1 Previous reset source is from Brown-out detector reset + * @details This macro get previous reset source is from Brown-out detect reset or not. + */ +#define SYS_IS_BOD_RST() (SYS->RSTSTS & SYS_RSTSTS_BODRF_Msk) + +/** + * @brief Get reset source is from CPU reset + * @param None + * @retval 0 Previous reset source is not from CPU reset + * @retval >=1 Previous reset source is from CPU reset + * @details This macro get previous reset source is from CPU reset. + */ +#define SYS_IS_CPU_RST() (SYS->RSTSTS & SYS_RSTSTS_CPURF_Msk) + +/** + * @brief Get reset source is from LVR Reset + * @param None + * @retval 0 Previous reset source is not from Low-Voltage-Reset + * @retval >=1 Previous reset source is from Low-Voltage-Reset + * @details This macro get previous reset source is from Low-Voltage-Reset. + */ +#define SYS_IS_LVR_RST() (SYS->RSTSTS & SYS_RSTSTS_LVRF_Msk) + +/** + * @brief Get reset source is from Power-on Reset + * @param None + * @retval 0 Previous reset source is not from Power-on Reset + * @retval >=1 Previous reset source is from Power-on Reset + * @details This macro get previous reset source is from Power-on Reset. + */ +#define SYS_IS_POR_RST() (SYS->RSTSTS & SYS_RSTSTS_PORF_Msk) + +/** + * @brief Get reset source is from reset pin reset + * @param None + * @retval 0 Previous reset source is not from reset pin reset + * @retval >=1 Previous reset source is from reset pin reset + * @details This macro get previous reset source is from reset pin reset. + */ +#define SYS_IS_RSTPIN_RST() (SYS->RSTSTS & SYS_RSTSTS_PINRF_Msk) + +/** + * @brief Get reset source is from system reset + * @param None + * @retval 0 Previous reset source is not from system reset + * @retval >=1 Previous reset source is from system reset + * @details This macro get previous reset source is from system reset. + */ +#define SYS_IS_SYSTEM_RST() (SYS->RSTSTS & SYS_RSTSTS_SYSRF_Msk) + +/** + * @brief Get reset source is from window watch dog reset + * @param None + * @retval 0 Previous reset source is not from window watch dog reset + * @retval >=1 Previous reset source is from window watch dog reset + * @details This macro get previous reset source is from window watch dog reset. + */ +#define SYS_IS_WDT_RST() (SYS->RSTSTS & SYS_RSTSTS_WDTRF_Msk) + +/** + * @brief Disable Low-Voltage-Reset function + * @param None + * @return None + * @details This macro disable Low-Voltage-Reset function. + * The register write-protection function should be disabled before using this macro. + */ +#define SYS_DISABLE_LVR() \ + do{ \ + while(SYS->BODCTL & SYS_BODCTL_WRBUSY_Msk); \ + SYS->BODCTL &= ~SYS_BODCTL_LVREN_Msk; \ + }while(0) + +/** + * @brief Enable Low-Voltage-Reset function + * @param None + * @return None + * @details This macro enable Low-Voltage-Reset function. + * The register write-protection function should be disabled before using this macro. + */ +#define SYS_ENABLE_LVR() \ + do{ \ + while(SYS->BODCTL & SYS_BODCTL_WRBUSY_Msk); \ + SYS->BODCTL |= SYS_BODCTL_LVREN_Msk; \ + }while(0) + +/** + * @brief Disable Power-on Reset function + * @param None + * @return None + * @details This macro disable Power-on Reset function. + * The register write-protection function should be disabled before using this macro. + */ +#define SYS_DISABLE_POR() (SYS->PORCTL0 = 0x5AA5) + +/** + * @brief Enable Power-on Reset function + * @param None + * @return None + * @details This macro enable Power-on Reset function. + * The register write-protection function should be disabled before using this macro. + */ +#define SYS_ENABLE_POR() (SYS->PORCTL0 = 0) + +/** + * @brief Clear reset source flag + * @param[in] u32RstSrc is reset source. Including : + * - \ref SYS_RSTSTS_PORF_Msk + * - \ref SYS_RSTSTS_PINRF_Msk + * - \ref SYS_RSTSTS_WDTRF_Msk + * - \ref SYS_RSTSTS_LVRF_Msk + * - \ref SYS_RSTSTS_BODRF_Msk + * - \ref SYS_RSTSTS_SYSRF_Msk + * - \ref SYS_RSTSTS_CPURF_Msk + * - \ref SYS_RSTSTS_CPULKRF_Msk + * @return None + * @details This macro clear reset source flag. + */ +#define SYS_CLEAR_RST_SOURCE(u32RstSrc) ((SYS->RSTSTS) = (u32RstSrc) ) + + +/*---------------------------------------------------------------------------------------------------------*/ +/* static inline functions */ +/*---------------------------------------------------------------------------------------------------------*/ +/* Declare these inline functions here to avoid MISRA C 2004 rule 8.1 error */ +__STATIC_INLINE void SYS_UnlockReg(void); +__STATIC_INLINE void SYS_LockReg(void); + + +/** + * @brief Disable register write-protection function + * @param None + * @return None + * @details This function disable register write-protection function. + * To unlock the protected register to allow write access. + */ +__STATIC_INLINE void SYS_UnlockReg(void) +{ + do + { + SYS->REGLCTL = 0x59UL; + SYS->REGLCTL = 0x16UL; + SYS->REGLCTL = 0x88UL; + } + while(SYS->REGLCTL == 0UL); +} + +/** + * @brief Enable register write-protection function + * @param None + * @return None + * @details This function is used to enable register write-protection function. + * To lock the protected register to forbid write access. + */ +__STATIC_INLINE void SYS_LockReg(void) +{ + SYS->REGLCTL = 0UL; +} + + +void SYS_ClearResetSrc(uint32_t u32Src); +uint32_t SYS_GetBODStatus(void); +uint32_t SYS_GetResetSrc(void); +uint32_t SYS_IsRegLocked(void); +uint32_t SYS_ReadPDID(void); +void SYS_ResetChip(void); +void SYS_ResetCPU(void); +void SYS_ResetModule(uint32_t u32ModuleIndex); +void SYS_EnableBOD(int32_t i32Mode, uint32_t u32BODLevel); +void SYS_DisableBOD(void); +void SYS_SetPowerLevel(uint32_t u32PowerLevel); +uint32_t SYS_SetPowerRegulator(uint32_t u32PowerRegulator); +void SYS_SetSSRAMPowerMode(uint32_t u32SRAMSel, uint32_t u32PowerMode); +void SYS_SetPSRAMPowerMode(uint32_t u32SRAMSel, uint32_t u32PowerMode); +void SYS_SetVRef(uint32_t u32VRefCTL); + + +/**@}*/ /* end of group SYS_EXPORTED_FUNCTIONS */ + +/**@}*/ /* end of group SYS_Driver */ + +/**@}*/ /* end of group Standard_Driver */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __NU_SYS_H__ */ + diff --git a/Ubiquitous/XiZi/board/nuvoton-m2354/third_party_driver/include/Drivers/nu_tamper.h b/Ubiquitous/XiZi/board/nuvoton-m2354/third_party_driver/include/Drivers/nu_tamper.h new file mode 100644 index 0000000..4edf945 --- /dev/null +++ b/Ubiquitous/XiZi/board/nuvoton-m2354/third_party_driver/include/Drivers/nu_tamper.h @@ -0,0 +1,464 @@ +/**************************************************************************//** + * @file nu_tamper.h + * @version V3.00 + * @brief M2354 series TAMPER driver header file + * + * @copyright SPDX-License-Identifier: Apache-2.0 + * @copyright Copyright (C) 2020 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ +#ifndef __NU_TAMPER_H__ +#define __NU_TAMPER_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup TAMPER_Driver Tamper Driver + @{ +*/ + +/** @addtogroup TAMPER_EXPORTED_CONSTANTS Tamper Exported Constants + @{ +*/ + +#define TAMPER_TAMPER0_SELECT (0x1UL << 0) /*!< Select Tamper 0 */ +#define TAMPER_TAMPER1_SELECT (0x1UL << 1) /*!< Select Tamper 1 */ +#define TAMPER_TAMPER2_SELECT (0x1UL << 2) /*!< Select Tamper 2 */ +#define TAMPER_TAMPER3_SELECT (0x1UL << 3) /*!< Select Tamper 3 */ +#define TAMPER_TAMPER4_SELECT (0x1UL << 4) /*!< Select Tamper 4 */ +#define TAMPER_TAMPER5_SELECT (0x1UL << 5) /*!< Select Tamper 5 */ +#define TAMPER_MAX_TAMPER_PIN_NUM 6UL /*!< Tamper Pin number */ + +#define TAMPER_TAMPER_HIGH_LEVEL_DETECT 1UL /*!< Tamper pin detect voltage level is high */ +#define TAMPER_TAMPER_LOW_LEVEL_DETECT 0UL /*!< Tamper pin detect voltage level is low */ + +#define TAMPER_TAMPER_DEBOUNCE_ENABLE 1UL /*!< Enable tamper pin de-bounce function */ +#define TAMPER_TAMPER_DEBOUNCE_DISABLE 0UL /*!< Disable tamper pin de-bounce function */ + +#define TAMPER_PAIR0_SELECT (0x1UL << 0) /*!< Select Pair 0 */ +#define TAMPER_PAIR1_SELECT (0x1UL << 1) /*!< Select Pair 1 */ +#define TAMPER_PAIR2_SELECT (0x1UL << 2) /*!< Select Pair 2 */ +#define TAMPER_MAX_PAIR_NUM 3UL /*!< Pair number */ + +#define TAMPER_2POW6_CLK (0x0UL << TAMPER_TIOCTL_DYNRATE_Pos) /*!< 64 RTC clock cycles */ +#define TAMPER_2POW7_CLK (0x1UL << TAMPER_TIOCTL_DYNRATE_Pos) /*!< 64 x 2 RTC clock cycles */ +#define TAMPER_2POW8_CLK (0x2UL << TAMPER_TIOCTL_DYNRATE_Pos) /*!< 64 x 4 RTC clock cycles */ +#define TAMPER_2POW9_CLK (0x3UL << TAMPER_TIOCTL_DYNRATE_Pos) /*!< 64 x 6 RTC clock cycles */ +#define TAMPER_2POW10_CLK (0x4UL << TAMPER_TIOCTL_DYNRATE_Pos) /*!< 64 x 8 RTC clock cycles */ +#define TAMPER_2POW11_CLK (0x5UL << TAMPER_TIOCTL_DYNRATE_Pos) /*!< 64 x 10 RTC clock cycles */ +#define TAMPER_2POW12_CLK (0x6UL << TAMPER_TIOCTL_DYNRATE_Pos) /*!< 64 x 12 RTC clock cycles */ +#define TAMPER_2POW13_CLK (0x7UL << TAMPER_TIOCTL_DYNRATE_Pos) /*!< 64 x 14 RTC clock cycles */ + +#define TAMPER_ACTS_2POW10_CLK (0x0UL << 5) /*!< 1024 LIRC32K clock cycles */ +#define TAMPER_ACTS_2POW11_CLK (0x1UL << 5) /*!< 1024 x 2 LIRC32K clock cycles */ +#define TAMPER_ACTS_2POW12_CLK (0x2UL << 5) /*!< 1024 x 4 LIRC32K clock cycles */ +#define TAMPER_ACTS_2POW13_CLK (0x3UL << 5) /*!< 1024 x 6 LIRC32K clock cycles */ +#define TAMPER_ACTS_2POW14_CLK (0x4UL << 5) /*!< 1024 x 8 LIRC32K clock cycles */ +#define TAMPER_ACTS_2POW15_CLK (0x5UL << 5) /*!< 1024 x 16 LIRC32K clock cycles */ +#define TAMPER_ACTS_2POW16_CLK (0x6UL << 5) /*!< 1024 x 32 LIRC32K clock cycles */ +#define TAMPER_ACTS_2POW17_CLK (0x7UL << 5) /*!< 1024 x 64 LIRC32K clock cycles */ + +#define TAMPER_REF_RANDOM_PATTERN 0x0UL /*!< The new reference pattern is generated by random number generator when the reference pattern run out */ +#define TAMPER_REF_SEED 0x1UL /*!< The new reference pattern is repeated from SEED (TAMPER_SEED[31:0]) when the reference pattern run out */ + +#define TAMPER_VG_192M_SAMPLE 0x0UL /*!< Select voltage glitch 192M sampleing rate */ + +/**@}*/ /* end of group TAMPER_EXPORTED_CONSTANTS */ + + +/** @addtogroup TAMPER_EXPORTED_FUNCTIONS Tamper Exported Functions + @{ +*/ + +/** + * @brief Reset Tamper Coreblock + * + * @param None + * + * @return None + * + * @details To set TAMPER INIT control register to reset the tamper coreblock. + * + */ +#define TAMPER_CORE_RESET() ((uint32_t)(TAMPER->INIT = 0x55AA)) + +/** + * @brief Release Tamper Coreblock + * + * @param None + * + * @return None + * + * @details To set TAMPER INIT control register to release the tamper coreblock. + * + */ +#define TAMPER_CORE_RELEASE() ((uint32_t)(TAMPER->INIT = 0x5500)) + +/** + * @brief Get the Voltage Regulator Power Ready Status + * + * @param None + * + * @retval 0 The power status of voltage regulator is not ready. + * @retval 1 The power status of voltage regulator is ready. + * + * @details This macro will return the power status of voltage regulator. + * + */ +#define TAMPER_TLDO_IS_READY() (TAMPER->INIT & TAMPER_INIT_TLDORDY_Msk ? 1:0) + +/** + * @brief Enable LXT Clock Detection + * + * @param None + * + * @return None + * + * @details To set TAMPER FUNEN control register to enable LXT clock detection. + * + */ +#define TAMPER_ENABLE_LXTDET() ((uint32_t)(TAMPER->FUNEN = (TAMPER->FUNEN & ~0xFFUL) | 0x44)) + +/** + * @brief Disable LXT Clock Detection + * + * @param None + * + * @return None + * + * @details To set TAMPER FUNEN control register to disable LXT clock detection. + * + */ +#define TAMPER_DISABLE_LXTDET() ((uint32_t)(TAMPER->FUNEN = (TAMPER->FUNEN & ~0xFFUL) | 0x40)) + +/** + * @brief Tamper I/O TAMPER Block Detection Selection + * + * @param[in] u32TamperSelect Tamper pin select. Possible options are + * - \ref TAMPER_TAMPER0_SELECT + * - \ref TAMPER_TAMPER1_SELECT + * - \ref TAMPER_TAMPER2_SELECT + * - \ref TAMPER_TAMPER3_SELECT + * - \ref TAMPER_TAMPER4_SELECT + * - \ref TAMPER_TAMPER5_SELECT + * + * @return None + * + * @details To set TAMPER FUNEN control register to select tamper I/O 0~5 and its function is detected through TAMPER block. + * + */ +__STATIC_INLINE void TAMPER_IOSEL_TAMPER(uint32_t u32TamperSelect) +{ + uint32_t i; + + for(i = 0UL; i < (uint32_t)TAMPER_MAX_TAMPER_PIN_NUM; i++) + { + if(u32TamperSelect & (0x1UL << i)) + { + TAMPER->FUNEN = (TAMPER->FUNEN & ~0xFFUL) | (0x94 + i * 0x10UL); + } + } +} + +/** + * @brief Tamper I/O RTC Block Detection Selection + * + * @param[in] u32TamperSelect Tamper pin select. Possible options are + * - \ref TAMPER_TAMPER0_SELECT + * - \ref TAMPER_TAMPER1_SELECT + * - \ref TAMPER_TAMPER2_SELECT + * - \ref TAMPER_TAMPER3_SELECT + * - \ref TAMPER_TAMPER4_SELECT + * - \ref TAMPER_TAMPER5_SELECT + * + * @return None + * + * @details To set TAMPER FUNEN control register to select tamper I/O 0~5 and its function is detected through RTC block. + * + */ +__STATIC_INLINE void TAMPER_IOSEL_RTC(uint32_t u32TamperSelect) +{ + uint32_t i; + + for(i = 0UL; i < (uint32_t)TAMPER_MAX_TAMPER_PIN_NUM; i++) + { + if(u32TamperSelect & (0x1UL << i)) + { + TAMPER->FUNEN = (TAMPER->FUNEN & ~0xFFUL) | (0x90 + i * 0x10UL); + } + } +} + +/** + * @brief Enable HIRC48M + * + * @param None + * + * @return None + * + * @details To set TAMPER FUNEN control register to enable HIRC48M. + * + */ +#define TAMPER_ENABLE_HIRC48M() ((uint32_t)(TAMPER->FUNEN &= (~TAMPER_FUNEN_HIRC48MEN_Msk))) + +/** + * @brief Disable HIRC48M + * + * @param None + * + * @return None + * + * @details To set TAMPER FUNEN control register to disable HIRC48M. + * + */ +#define TAMPER_DISABLE_HIRC48M() ((uint32_t)(TAMPER->FUNEN = (TAMPER->FUNEN & (~TAMPER_FUNEN_HIRC48MEN_Msk)) | (0x5A << TAMPER_FUNEN_HIRC48MEN_Pos))) + +/** + * @brief Voltage Glitch Sampling Rate Selection + * + * @param[in] u32VGSampleRate Voltage Glitch sampling rate select. Possible option is + * - \ref TAMPER_VG_192M_SAMPLE + * + * @return None + * + * @details To set TAMPER FUNEN control register to enable voltage glitch channel 0~3 to select voltage glitch sampling rate. + * + */ +__STATIC_INLINE void TAMPER_VG_SAMPLE_SEL(uint32_t u32VGSampleRate) +{ + TAMPER->FUNEN &= ~0xF000000UL; + + if(u32VGSampleRate == TAMPER_VG_192M_SAMPLE) + { + TAMPER->FUNEN |= TAMPER_FUNEN_VGCHEN0_Msk | TAMPER_FUNEN_VGCHEN1_Msk | TAMPER_FUNEN_VGCHEN2_Msk | TAMPER_FUNEN_VGCHEN3_Msk; + } +} + +/** + * @brief Enable to Trigger Key Store + * + * @param None + * + * @return None + * + * @details Set KSTRIGEN bit of TAMPER TRIEN control register to trigger Key Store when Tamper event is detected. + * + */ +#define TAMPER_ENABLE_KS_TRIG() ((uint32_t)(TAMPER->TRIEN |= TAMPER_TRIEN_KSTRIGEN_Msk)) + +/** + * @brief Disable to Trigger Key Store + * + * @param None + * + * @return None + * + * @details Clear KSTRIGEN bit of TAMPER TRIEN control register to not trigger Key Store when Tamper event is detected. + * + */ +#define TAMPER_DISABLE_KS_TRIG() ((uint32_t)(TAMPER->TRIEN &= (~TAMPER_TRIEN_KSTRIGEN_Msk))) + +/** + * @brief Enable Wake-up Function + * + * @param None + * + * @return None + * + * @details Set WAKEUPEN bit of TAMPER TRIEN control register to wake-up the system when Tamper event is detected. + * + */ +#define TAMPER_ENABLE_WAKEUP() ((uint32_t)(TAMPER->TRIEN |= TAMPER_TRIEN_WAKEUPEN_Msk)) + +/** + * @brief Disable Wake-up Function + * + * @param None + * + * @return None + * + * @details Clear WAKEUPEN bit of TAMPER TRIEN control register to not wake-up the system when Tamper event is detected. + * + */ +#define TAMPER_DISABLE_WAKEUP() ((uint32_t)(TAMPER->TRIEN &= (~TAMPER_TRIEN_WAKEUPEN_Msk))) + +/** + * @brief Enable to Clear Crypto Function + * + * @param None + * + * @return None + * + * @details Set CRYPTOEN bit of TAMPER TRIEN control register to reset Crypto when Tamper event is detected. + * + */ +#define TAMPER_ENABLE_CRYPTO() ((uint32_t)(TAMPER->TRIEN |= TAMPER_TRIEN_CRYPTOEN_Msk)) + +/** + * @brief Disable to Clear Crypto Function + * + * @param None + * + * @return None + * + * @details Clear CRYPTOEN bit of TAMPER TRIEN control register to not reset Crypto when Tamper event is detected. + * + */ +#define TAMPER_DISABLE_CRYPTO() ((uint32_t)(TAMPER->TRIEN &= (~TAMPER_TRIEN_CRYPTOEN_Msk))) + +/** + * @brief Enable to Trigger Chip Reset + * + * @param None + * + * @return None + * + * @details Set CHIPRSTEN bit of TAMPER TRIEN control register to reset the system when Tamper event is detected. + * + */ +#define TAMPER_ENABLE_CHIPRST() ((uint32_t)(TAMPER->TRIEN |= TAMPER_TRIEN_CHIPRSTEN_Msk)) + +/** + * @brief Disable to Trigger Chip Reset + * + * @param None + * + * @return None + * + * @details Clear CHIPRSTEN bit of TAMPER TRIEN control register to not reset the system when Tamper event is detected. + * + */ +#define TAMPER_DISABLE_CHIPRST() ((uint32_t)(TAMPER->TRIEN &= (~TAMPER_TRIEN_CHIPRSTEN_Msk))) + +/** + * @brief Enable to Clear RTC Spare Register + * + * @param None + * + * @return None + * + * @details Set RTCSPCLREN bit of TAMPER TRIEN control register to reset RTC spare register when Tamper event is detected. + * + */ +#define TAMPER_ENABLE_RTCSPCLR() ((uint32_t)(TAMPER->TRIEN |= TAMPER_TRIEN_RTCSPCLREN_Msk)) + +/** + * @brief Disable to Clear RTC Spare Register + * + * @param None + * + * @return None + * + * @details Clear RTCSPCLREN bit of TAMPER TRIEN control register to not reset RTC spare register when Tamper event is detected. + * + */ +#define TAMPER_DISABLE_RTCSPCLR() ((uint32_t)(TAMPER->TRIEN &= (~TAMPER_TRIEN_RTCSPCLREN_Msk))) + +/** + * @brief Get Tamper Interrupt Flag + * + * @param None + * + * @retval 0 Tamper event Interrupt did not occur + * @retval 1 Tamper event Interrupt occurred + * + * @details This macro indicates Tamper event intertupt occurred or not. + * + */ +#define TAMPER_GET_INT_FLAG() ((TAMPER->INTSTS & (0xAA7FAFFF))? 1:0) + +/** + * @brief Clear Tamper Interrupt Status + * + * @param[in] u32TamperFlag Tamper event interrupt flag. It consists of: + * - \ref TAMPER_INTSTS_TAMP0IF_Msk + * - \ref TAMPER_INTSTS_TAMP1IF_Msk + * - \ref TAMPER_INTSTS_TAMP2IF_Msk + * - \ref TAMPER_INTSTS_TAMP3IF_Msk + * - \ref TAMPER_INTSTS_TAMP4IF_Msk + * - \ref TAMPER_INTSTS_TAMP5IF_Msk + * - \ref TAMPER_INTSTS_CLKFAILIF_Msk + * - \ref TAMPER_INTSTS_CLKSTOPIF_Msk + * - \ref TAMPER_INTSTS_OVPOUTIF_Msk + * - \ref TAMPER_INTSTS_VGPEVIF_Msk + * - \ref TAMPER_INTSTS_VGNEVIF_Msk + * - \ref TAMPER_INTSTS_ACTSEIF_Msk + * - \ref TAMPER_INTSTS_ACTST5IF_Msk + * - \ref TAMPER_INTSTS_ACTST25IF_Msk + * - \ref TAMPER_INTSTS_BODIF_Msk + * - \ref TAMPER_INTSTS_ACTST1IF_Msk + * - \ref TAMPER_INTSTS_ACTST3IF_Msk + * - \ref TAMPER_INTSTS_ACTST21IF_Msk + * - \ref TAMPER_INTSTS_ACTST23IF_Msk + * + * @return None + * + * @details This macro is used to clear Tamper event flag. + * + */ +#define TAMPER_CLR_INT_STATUS(u32TamperFlag) (TAMPER->INTSTS = (u32TamperFlag)) + +/** + * @brief Get Tamper Interrupt Status + * + * @param None + * + * @retval TAMPER_INTSTS_TAMP0IF_Msk + * @retval TAMPER_INTSTS_TAMP1IF_Msk + * @retval TAMPER_INTSTS_TAMP2IF_Msk + * @retval TAMPER_INTSTS_TAMP3IF_Msk + * @retval TAMPER_INTSTS_TAMP4IF_Msk + * @retval TAMPER_INTSTS_TAMP5IF_Msk + * @retval TAMPER_INTSTS_CLKFAILIF_Msk + * @retval TAMPER_INTSTS_CLKSTOPIF_Msk + * @retval TAMPER_INTSTS_OVPOUTIF_Msk + * @retval TAMPER_INTSTS_VGPEVIF_Msk + * @retval TAMPER_INTSTS_VGNEVIF_Msk + * @retval TAMPER_INTSTS_ACTSEFIF_Msk + * @retval TAMPER_INTSTS_ACTST5IF_Msk + * @retval TAMPER_INTSTS_ACTST25IF_Msk + * @retval TAMPER_INTSTS_RTCLVRIF_Msk + * @retval TAMPER_INTSTS_RIOTRIGIF_Msk + * @retval TAMPER_INTSTS_RCLKTRIGIF_Msk + * @retval TAMPER_INTSTS_BODIF_Msk + * @retval TAMPER_INTSTS_ACTST1IF_Msk + * @retval TAMPER_INTSTS_ACTST3IF_Msk + * @retval TAMPER_INTSTS_ACTST21IF_Msk + * @retval TAMPER_INTSTS_ACTST23IF_Msk + * + * @details This macro indicates Tamper event status. + * + */ +#define TAMPER_GET_INT_STATUS() ((TAMPER->INTSTS & (0xAA7FAFFF))) + +void TAMPER_EnableInt(uint32_t u32IntFlagMask); +void TAMPER_DisableInt(uint32_t u32IntFlagMask); +void TAMPER_StaticTamperEnable(uint32_t u32TamperSelect, uint32_t u32DetecLevel, uint32_t u32DebounceEn); +void TAMPER_StaticTamperDisable(uint32_t u32TamperSelect); +void TAMPER_DynamicTamperEnable(uint32_t u32PairSel, uint32_t u32DebounceEn, uint32_t u32Pair1Source, uint32_t u32Pair2Source); +void TAMPER_DynamicTamperDisable(uint32_t u32PairSel); +void TAMPER_DynamicTamperConfig(uint32_t u32ChangeRate, uint32_t u32SeedReload, uint32_t u32RefPattern, uint32_t u32Seed); +void TAMPER_ActiveShieldDynamicTamperEnable(uint32_t u32PairSel1, uint32_t u32Pair1Source1, uint32_t u32PairSel2, uint32_t u32Pair1Source2); +void TAMPER_ActiveShieldDynamicTamperDisable(uint32_t u32PairSel1, uint32_t u32PairSe2); +void TAMPER_ActiveShieldDynamicTamperConfig(uint32_t u32ChangeRate1, uint32_t u32SeedReload1, uint32_t u32RefPattern1, uint32_t u32Seed, + uint32_t u32ChangeRate2, uint32_t u32SeedReload2, uint32_t u32RefPattern2, uint32_t u32Seed2); + + +/**@}*/ /* end of group TAMPER_EXPORTED_FUNCTIONS */ + +/**@}*/ /* end of group TAMPER_Driver */ + +/**@}*/ /* end of group Standard_Driver */ + +#ifdef __cplusplus +} +#endif + +#endif /* __NU_TAMPER_H__ */ + diff --git a/Ubiquitous/XiZi/board/nuvoton-m2354/third_party_driver/include/Drivers/nu_timer.h b/Ubiquitous/XiZi/board/nuvoton-m2354/third_party_driver/include/Drivers/nu_timer.h new file mode 100644 index 0000000..21bd179 --- /dev/null +++ b/Ubiquitous/XiZi/board/nuvoton-m2354/third_party_driver/include/Drivers/nu_timer.h @@ -0,0 +1,541 @@ +/**************************************************************************//** + * @file nu_timer.h + * @version V3.00 + * @brief Timer Controller(Timer) driver header file + * + * @copyright SPDX-License-Identifier: Apache-2.0 + * @copyright Copyright (C) 2020 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ +#ifndef __NU_TIMER_H__ +#define __NU_TIMER_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup TIMER_Driver TIMER Driver + @{ +*/ + +/** @addtogroup TIMER_EXPORTED_CONSTANTS TIMER Exported Constants + @{ +*/ +/*---------------------------------------------------------------------------------------------------------*/ +/* TIMER Operation Mode, External Counter and Capture Mode Constant Definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define TIMER_ONESHOT_MODE (0UL << TIMER_CTL_OPMODE_Pos) /*!< Timer working in one-shot mode \hideinitializer */ +#define TIMER_PERIODIC_MODE (1UL << TIMER_CTL_OPMODE_Pos) /*!< Timer working in periodic mode \hideinitializer */ +#define TIMER_TOGGLE_MODE (2UL << TIMER_CTL_OPMODE_Pos) /*!< Timer working in toggle-output mode \hideinitializer */ +#define TIMER_CONTINUOUS_MODE (3UL << TIMER_CTL_OPMODE_Pos) /*!< Timer working in continuous counting mode \hideinitializer */ +#define TIMER_TOUT_PIN_FROM_TMX (0UL << TIMER_CTL_TGLPINSEL_Pos) /*!< Timer toggle-output pin is from TMx pin \hideinitializer */ +#define TIMER_TOUT_PIN_FROM_TMX_EXT (1UL << TIMER_CTL_TGLPINSEL_Pos) /*!< Timer toggle-output pin is from TMx_EXT pin \hideinitializer */ + +#define TIMER_COUNTER_EVENT_FALLING (0UL << TIMER_EXTCTL_CNTPHASE_Pos) /*!< Counter increase on falling edge detection \hideinitializer */ +#define TIMER_COUNTER_EVENT_RISING (1UL << TIMER_EXTCTL_CNTPHASE_Pos) /*!< Counter increase on rising edge detection \hideinitializer */ +#define TIMER_CAPTURE_FREE_COUNTING_MODE (0UL << TIMER_EXTCTL_CAPFUNCS_Pos) /*!< Timer capture event to get timer counter value \hideinitializer */ +#define TIMER_CAPTURE_COUNTER_RESET_MODE (1UL << TIMER_EXTCTL_CAPFUNCS_Pos) /*!< Timer capture event to reset timer counter \hideinitializer */ + +#define TIMER_CAPTURE_EVENT_FALLING (0UL << TIMER_EXTCTL_CAPEDGE_Pos) /*!< Falling edge detection to trigger capture event \hideinitializer */ +#define TIMER_CAPTURE_EVENT_RISING (1UL << TIMER_EXTCTL_CAPEDGE_Pos) /*!< Rising edge detection to trigger capture event \hideinitializer */ +#define TIMER_CAPTURE_EVENT_FALLING_RISING (2UL << TIMER_EXTCTL_CAPEDGE_Pos) /*!< Both falling and rising edge detection to trigger capture event, and first event at falling edge \hideinitializer */ +#define TIMER_CAPTURE_EVENT_RISING_FALLING (3UL << TIMER_EXTCTL_CAPEDGE_Pos) /*!< Both rising and falling edge detection to trigger capture event, and first event at rising edge \hideinitializer */ +#define TIMER_CAPTURE_EVENT_GET_LOW_PERIOD (6UL << TIMER_EXTCTL_CAPEDGE_Pos) /*!< First capture event is at falling edge, follows are at at rising edge \hideinitializer */ +#define TIMER_CAPTURE_EVENT_GET_HIGH_PERIOD (7UL << TIMER_EXTCTL_CAPEDGE_Pos) /*!< First capture event is at rising edge, follows are at at falling edge \hideinitializer */ + +#define TIMER_CAPTURE_SOURCE_FROM_PIN (0UL << TIMER_CTL_CAPSRC_Pos) /*!< The capture source is from TMx_EXT pin \hideinitializer */ +#define TIMER_CAPTURE_SOURCE_FROM_INTERNAL (1UL << TIMER_CTL_CAPSRC_Pos) /*!< The capture source is from internal ACMPx signal or clock source \hideinitializer */ + +#define TIMER_CAPTURE_SOURCE_DIV_1 (0UL << TIMER_EXTCTL_CAPDIVSCL_Pos) /*!< Input capture source divide 1 \hideinitializer */ +#define TIMER_CAPTURE_SOURCE_DIV_2 (1UL << TIMER_EXTCTL_CAPDIVSCL_Pos) /*!< Input capture source divide 2 \hideinitializer */ +#define TIMER_CAPTURE_SOURCE_DIV_4 (2UL << TIMER_EXTCTL_CAPDIVSCL_Pos) /*!< Input capture source divide 4 \hideinitializer */ +#define TIMER_CAPTURE_SOURCE_DIV_8 (3UL << TIMER_EXTCTL_CAPDIVSCL_Pos) /*!< Input capture source divide 8 \hideinitializer */ +#define TIMER_CAPTURE_SOURCE_DIV_16 (4UL << TIMER_EXTCTL_CAPDIVSCL_Pos) /*!< Input capture source divide 16 \hideinitializer */ +#define TIMER_CAPTURE_SOURCE_DIV_32 (5UL << TIMER_EXTCTL_CAPDIVSCL_Pos) /*!< Input capture source divide 32 \hideinitializer */ +#define TIMER_CAPTURE_SOURCE_DIV_64 (6UL << TIMER_EXTCTL_CAPDIVSCL_Pos) /*!< Input capture source divide 64 \hideinitializer */ +#define TIMER_CAPTURE_SOURCE_DIV_128 (7UL << TIMER_EXTCTL_CAPDIVSCL_Pos) /*!< Input capture source divide 128 \hideinitializer */ +#define TIMER_CAPTURE_SOURCE_DIV_256 (8UL << TIMER_EXTCTL_CAPDIVSCL_Pos) /*!< Input capture source divide 256 \hideinitializer */ + +#define TIMER_INTER_CAPTURE_SOURCE_ACMP0 (0UL << TIMER_EXTCTL_INTERCAPSEL_Pos) /*!< Capture source from internal ACMP0 output signal \hideinitializer */ +#define TIMER_INTER_CAPTURE_SOURCE_ACMP1 (1UL << TIMER_EXTCTL_INTERCAPSEL_Pos) /*!< Capture source from internal ACMP1 output signal \hideinitializer */ +#define TIMER_INTER_CAPTURE_SOURCE_HXT (2UL << TIMER_EXTCTL_INTERCAPSEL_Pos) /*!< Capture source from HXT \hideinitializer */ +#define TIMER_INTER_CAPTURE_SOURCE_LXT (3UL << TIMER_EXTCTL_INTERCAPSEL_Pos) /*!< Capture source from LXT \hideinitializer */ +#define TIMER_INTER_CAPTURE_SOURCE_HIRC (4UL << TIMER_EXTCTL_INTERCAPSEL_Pos) /*!< Capture source from HIRC \hideinitializer */ +#define TIMER_INTER_CAPTURE_SOURCE_LIRC (5UL << TIMER_EXTCTL_INTERCAPSEL_Pos) /*!< Capture source from LIRC \hideinitializer */ +#define TIMER_INTER_CAPTURE_SOURCE_MIRC (6UL << TIMER_EXTCTL_INTERCAPSEL_Pos) /*!< Capture source from MIRC. Only available on TIMER4 and TIMER5 \hideinitializer */ + +#define TIMER_TRGSRC_TIMEOUT_EVENT (0UL << TIMER_TRGCTL_TRGSSEL_Pos) /*!< Select internal trigger source from timer time-out event \hideinitializer */ +#define TIMER_TRGSRC_CAPTURE_EVENT (1UL << TIMER_TRGCTL_TRGSSEL_Pos) /*!< Select internal trigger source from timer capture event \hideinitializer */ +#define TIMER_TRG_TO_PWM (TIMER_TRGCTL_TRGPWM_Msk) /*!< Each timer event as EPWM and BPWM counter clock source. NOT supported on TIMER4 and TIMER5 \hideinitializer */ +#define TIMER_TRG_TO_EADC (TIMER_TRGCTL_TRGEADC_Msk) /*!< Each timer event to start ADC conversion \hideinitializer */ +#define TIMER_TRG_TO_DAC (TIMER_TRGCTL_TRGDAC_Msk) /*!< Each timer event to start DAC conversion. NOT supported on TIMER4 and TIMER5 \hideinitializer */ +#define TIMER_TRG_TO_PDMA (TIMER_TRGCTL_TRGPDMA_Msk) /*!< Each timer event to trigger PDMA transfer \hideinitializer */ + +/**@}*/ /* end of group TIMER_EXPORTED_CONSTANTS */ + + +/** @addtogroup TIMER_EXPORTED_FUNCTIONS TIMER Exported Functions + @{ +*/ + +/** + * @brief Set Timer Compared Value + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0 ~ TIMER5. + * @param[in] u32Value Timer compare value. Valid values are between 2 to 0xFFFFFF. + * + * @return None + * + * @details This macro is used to set timer compared value to adjust timer time-out interval. + * @note 1. Never write 0x0 or 0x1 in this field, or the core will run into unknown state. \n + * 2. If update timer compared value in continuous counting mode, timer counter value will keep counting continuously. \n + * But if timer is operating at other modes, the timer up counter will restart counting and start from 0. + * \hideinitializer + */ +#define TIMER_SET_CMP_VALUE(timer, u32Value) ((timer)->CMP = (u32Value)) + +/** + * @brief Set Timer Prescale Value + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0 ~ TIMER5. + * @param[in] u32Value Timer prescale value. Valid values are between 0 to 0xFF. + * + * @return None + * + * @details This macro is used to set timer prescale value and timer source clock will be divided by (prescale + 1) \n + * before it is fed into timer. + * \hideinitializer + */ +#define TIMER_SET_PRESCALE_VALUE(timer, u32Value) ((timer)->CTL = ((timer)->CTL & ~TIMER_CTL_PSC_Msk) | (u32Value)) + +/** + * @brief Check specify Timer Status + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0 ~ TIMER5. + * + * @retval 0 Timer 24-bit up counter is inactive + * @retval 1 Timer 24-bit up counter is active + * + * @details This macro is used to check if specify Timer counter is inactive or active. + * \hideinitializer + */ +#define TIMER_IS_ACTIVE(timer) ((((timer)->CTL & TIMER_CTL_ACTSTS_Msk) == TIMER_CTL_ACTSTS_Msk)? 1 : 0) + +/** + * @brief Select Toggle-output Pin + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0 ~ TIMER5. + * @param[in] u32ToutSel Toggle-output pin selection, valid values are: + * - \ref TIMER_TOUT_PIN_FROM_TMX + * - \ref TIMER_TOUT_PIN_FROM_TMX_EXT + * + * @return None + * + * @details This macro is used to select timer toggle-output pin is output on TMx or TMx_EXT pin. + * \hideinitializer + */ +#define TIMER_SELECT_TOUT_PIN(timer, u32ToutSel) ((timer)->CTL = ((timer)->CTL & ~TIMER_CTL_TGLPINSEL_Msk) | (u32ToutSel)) + +/** + * @brief Set Timer Operating Mode + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0 ~ TIMER5. + * @param[in] u32OpMode Operation mode. Possible options are + * - \ref TIMER_ONESHOT_MODE + * - \ref TIMER_PERIODIC_MODE + * - \ref TIMER_TOGGLE_MODE + * - \ref TIMER_CONTINUOUS_MODE + * + * @return None + * \hideinitializer + */ +#define TIMER_SET_OPMODE(timer, u32OpMode) ((timer)->CTL = ((timer)->CTL & ~TIMER_CTL_OPMODE_Msk) | (u32OpMode)) + + +/*---------------------------------------------------------------------------------------------------------*/ +/* static inline functions */ +/*---------------------------------------------------------------------------------------------------------*/ +/* Declare these inline functions here to avoid MISRA C 2004 rule 8.1 error */ +__STATIC_INLINE void TIMER_Start(TIMER_T *timer); +__STATIC_INLINE void TIMER_Stop(TIMER_T *timer); +__STATIC_INLINE void TIMER_EnableWakeup(TIMER_T *timer); +__STATIC_INLINE void TIMER_DisableWakeup(TIMER_T *timer); +__STATIC_INLINE void TIMER_StartCapture(TIMER_T *timer); +__STATIC_INLINE void TIMER_StopCapture(TIMER_T *timer); +__STATIC_INLINE void TIMER_EnableCaptureDebounce(TIMER_T *timer); +__STATIC_INLINE void TIMER_DisableCaptureDebounce(TIMER_T *timer); +__STATIC_INLINE void TIMER_EnableEventCounterDebounce(TIMER_T *timer); +__STATIC_INLINE void TIMER_DisableEventCounterDebounce(TIMER_T *timer); +__STATIC_INLINE void TIMER_EnableInt(TIMER_T *timer); +__STATIC_INLINE void TIMER_DisableInt(TIMER_T *timer); +__STATIC_INLINE void TIMER_EnableCaptureInt(TIMER_T *timer); +__STATIC_INLINE void TIMER_DisableCaptureInt(TIMER_T *timer); +__STATIC_INLINE uint32_t TIMER_GetIntFlag(TIMER_T *timer); +__STATIC_INLINE void TIMER_ClearIntFlag(TIMER_T *timer); +__STATIC_INLINE uint32_t TIMER_GetCaptureIntFlag(TIMER_T *timer); +__STATIC_INLINE void TIMER_ClearCaptureIntFlag(TIMER_T *timer); +__STATIC_INLINE uint32_t TIMER_GetWakeupFlag(TIMER_T *timer); +__STATIC_INLINE void TIMER_ClearWakeupFlag(TIMER_T *timer); +__STATIC_INLINE uint32_t TIMER_GetCaptureData(TIMER_T *timer); +__STATIC_INLINE uint32_t TIMER_GetCounter(TIMER_T *timer); +__STATIC_INLINE void TIMER_ResetCounter(TIMER_T *timer); + + +/** + * @brief Start Timer Counting + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0 ~ TIMER5. + * + * @return None + * + * @details This function is used to start Timer counting. + */ +__STATIC_INLINE void TIMER_Start(TIMER_T *timer) +{ + timer->CTL |= TIMER_CTL_CNTEN_Msk; +} + +/** + * @brief Stop Timer Counting + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0 ~ TIMER5. + * + * @return None + * + * @details This function is used to stop/suspend Timer counting. + */ +__STATIC_INLINE void TIMER_Stop(TIMER_T *timer) +{ + timer->CTL &= ~TIMER_CTL_CNTEN_Msk; +} + +/** + * @brief Enable Timer Interrupt Wake-up Function + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0 ~ TIMER5. + * + * @return None + * + * @details This function is used to enable the timer interrupt wake-up function and interrupt source could be time-out interrupt, \n + * counter event interrupt or capture trigger interrupt. + * @note To wake the system from Power-down mode, timer clock source must be ether LXT or LIRC. + */ +__STATIC_INLINE void TIMER_EnableWakeup(TIMER_T *timer) +{ + timer->CTL |= TIMER_CTL_WKEN_Msk; +} + +/** + * @brief Disable Timer Wake-up Function + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0 ~ TIMER5. + * + * @return None + * + * @details This function is used to disable the timer interrupt wake-up function. + */ +__STATIC_INLINE void TIMER_DisableWakeup(TIMER_T *timer) +{ + timer->CTL &= ~TIMER_CTL_WKEN_Msk; +} + +/** + * @brief Start Timer Capture Function + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0 ~ TIMER5. + * + * @return None + * + * @details This function is used to start Timer capture function. + */ +__STATIC_INLINE void TIMER_StartCapture(TIMER_T *timer) +{ + timer->EXTCTL |= TIMER_EXTCTL_CAPEN_Msk; +} + +/** + * @brief Stop Timer Capture Function + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0 ~ TIMER5. + * + * @return None + * + * @details This function is used to stop Timer capture function. + */ +__STATIC_INLINE void TIMER_StopCapture(TIMER_T *timer) +{ + timer->EXTCTL &= ~TIMER_EXTCTL_CAPEN_Msk; +} + +/** + * @brief Enable Capture Pin De-bounce + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0 ~ TIMER5. + * + * @return None + * + * @details This function is used to enable the detect de-bounce function of capture pin. + */ +__STATIC_INLINE void TIMER_EnableCaptureDebounce(TIMER_T *timer) +{ + timer->EXTCTL |= TIMER_EXTCTL_CAPDBEN_Msk; +} + +/** + * @brief Disable Capture Pin De-bounce + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0 ~ TIMER5. + * + * @return None + * + * @details This function is used to disable the detect de-bounce function of capture pin. + */ +__STATIC_INLINE void TIMER_DisableCaptureDebounce(TIMER_T *timer) +{ + timer->EXTCTL &= ~TIMER_EXTCTL_CAPDBEN_Msk; +} + +/** + * @brief Enable Counter Pin De-bounce + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0 ~ TIMER5. + * + * @return None + * + * @details This function is used to enable the detect de-bounce function of counter pin. + */ +__STATIC_INLINE void TIMER_EnableEventCounterDebounce(TIMER_T *timer) +{ + timer->EXTCTL |= TIMER_EXTCTL_CNTDBEN_Msk; +} + +/** + * @brief Disable Counter Pin De-bounce + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0 ~ TIMER5. + * + * @return None + * + * @details This function is used to disable the detect de-bounce function of counter pin. + */ +__STATIC_INLINE void TIMER_DisableEventCounterDebounce(TIMER_T *timer) +{ + timer->EXTCTL &= ~TIMER_EXTCTL_CNTDBEN_Msk; +} + +/** + * @brief Enable Timer Time-out Interrupt + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0 ~ TIMER5. + * + * @return None + * + * @details This function is used to enable the timer time-out interrupt function. + */ +__STATIC_INLINE void TIMER_EnableInt(TIMER_T *timer) +{ + timer->CTL |= TIMER_CTL_INTEN_Msk; +} + +/** + * @brief Disable Timer Time-out Interrupt + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0 ~ TIMER5. + * + * @return None + * + * @details This function is used to disable the timer time-out interrupt function. + */ +__STATIC_INLINE void TIMER_DisableInt(TIMER_T *timer) +{ + timer->CTL &= ~TIMER_CTL_INTEN_Msk; +} + +/** + * @brief Enable Capture Trigger Interrupt + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0 ~ TIMER5. + * + * @return None + * + * @details This function is used to enable the timer capture trigger interrupt function. + */ +__STATIC_INLINE void TIMER_EnableCaptureInt(TIMER_T *timer) +{ + timer->EXTCTL |= TIMER_EXTCTL_CAPIEN_Msk; +} + +/** + * @brief Disable Capture Trigger Interrupt + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0 ~ TIMER5. + * + * @return None + * + * @details This function is used to disable the timer capture trigger interrupt function. + */ +__STATIC_INLINE void TIMER_DisableCaptureInt(TIMER_T *timer) +{ + timer->EXTCTL &= ~TIMER_EXTCTL_CAPIEN_Msk; +} + +/** + * @brief Get Timer Time-out Interrupt Flag + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0 ~ TIMER5. + * + * @retval 0 Timer time-out interrupt did not occur + * @retval 1 Timer time-out interrupt occurred + * + * @details This function indicates timer time-out interrupt occurred or not. + */ +__STATIC_INLINE uint32_t TIMER_GetIntFlag(TIMER_T *timer) +{ + return (((timer->INTSTS & TIMER_INTSTS_TIF_Msk) == TIMER_INTSTS_TIF_Msk) ? 1UL : 0UL); +} + +/** + * @brief Clear Timer Time-out Interrupt Flag + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0 ~ TIMER5. + * + * @return None + * + * @details This function clears timer time-out interrupt flag to 0. + */ +__STATIC_INLINE void TIMER_ClearIntFlag(TIMER_T *timer) +{ + timer->INTSTS = TIMER_INTSTS_TIF_Msk; +} + +/** + * @brief Get Timer Capture Interrupt Flag + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0 ~ TIMER5. + * + * @retval 0 Timer capture interrupt did not occur + * @retval 1 Timer capture interrupt occurred + * + * @details This function indicates timer capture trigger interrupt occurred or not. + */ +__STATIC_INLINE uint32_t TIMER_GetCaptureIntFlag(TIMER_T *timer) +{ + return timer->EINTSTS; +} + +/** + * @brief Clear Timer Capture Interrupt Flag + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0 ~ TIMER5. + * + * @return None + * + * @details This function clears timer capture trigger interrupt flag to 0. + */ +__STATIC_INLINE void TIMER_ClearCaptureIntFlag(TIMER_T *timer) +{ + timer->EINTSTS = TIMER_EINTSTS_CAPIF_Msk; +} + +/** + * @brief Get Timer Wake-up Flag + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0 ~ TIMER5. + * + * @retval 0 Timer does not cause CPU wake-up + * @retval 1 Timer interrupt event cause CPU wake-up + * + * @details This function indicates timer interrupt event has waked up system or not. + */ +__STATIC_INLINE uint32_t TIMER_GetWakeupFlag(TIMER_T *timer) +{ + return (((timer->INTSTS & TIMER_INTSTS_TWKF_Msk) == TIMER_INTSTS_TWKF_Msk) ? 1UL : 0UL); +} + +/** + * @brief Clear Timer Wake-up Flag + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0 ~ TIMER5. + * + * @return None + * + * @details This function clears the timer wake-up system flag to 0. + */ +__STATIC_INLINE void TIMER_ClearWakeupFlag(TIMER_T *timer) +{ + timer->INTSTS = TIMER_INTSTS_TWKF_Msk; +} + +/** + * @brief Get Capture value + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0 ~ TIMER5. + * + * @return 24-bit Capture Value + * + * @details This function reports the current 24-bit timer capture value. + */ +__STATIC_INLINE uint32_t TIMER_GetCaptureData(TIMER_T *timer) +{ + return timer->CAP; +} + +/** + * @brief Get Counter value + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0 ~ TIMER5. + * + * @return 24-bit Counter Value + * + * @details This function reports the current 24-bit timer counter value. + */ +__STATIC_INLINE uint32_t TIMER_GetCounter(TIMER_T *timer) +{ + return timer->CNT; +} + +/** + * @brief Reset Counter + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0 ~ TIMER5. + * + * @return None + * + * @details This function is used to reset current counter value and internal prescale counter value. + */ +__STATIC_INLINE void TIMER_ResetCounter(TIMER_T *timer) +{ + timer->CNT = 0UL; + while((timer->CNT & TIMER_CNT_RSTACT_Msk) == TIMER_CNT_RSTACT_Msk) {} +} + + +uint32_t TIMER_Open(TIMER_T *timer, uint32_t u32Mode, uint32_t u32Freq); +void TIMER_Close(TIMER_T *timer); +void TIMER_Delay(TIMER_T *timer, uint32_t u32Usec); +void TIMER_EnableCapture(TIMER_T *timer, uint32_t u32CapMode, uint32_t u32Edge); +void TIMER_DisableCapture(TIMER_T *timer); +void TIMER_EnableEventCounter(TIMER_T *timer, uint32_t u32Edge); +void TIMER_DisableEventCounter(TIMER_T *timer); +uint32_t TIMER_GetModuleClock(TIMER_T *timer); +void TIMER_EnableFreqCounter(TIMER_T *timer, uint32_t u32DropCount, uint32_t u32Timeout, uint32_t u32EnableInt); +void TIMER_DisableFreqCounter(TIMER_T *timer); +void TIMER_SetTriggerSource(TIMER_T *timer, uint32_t u32Src); +void TIMER_SetTriggerTarget(TIMER_T *timer, uint32_t u32Mask); + +/**@}*/ /* end of group TIMER_EXPORTED_FUNCTIONS */ + +/**@}*/ /* end of group TIMER_Driver */ + +/**@}*/ /* end of group Standard_Driver */ + +#ifdef __cplusplus +} +#endif + +#endif /* __NU_TIMER_H__ */ diff --git a/Ubiquitous/XiZi/board/nuvoton-m2354/third_party_driver/include/Drivers/nu_timer_pwm.h b/Ubiquitous/XiZi/board/nuvoton-m2354/third_party_driver/include/Drivers/nu_timer_pwm.h new file mode 100644 index 0000000..5627fb9 --- /dev/null +++ b/Ubiquitous/XiZi/board/nuvoton-m2354/third_party_driver/include/Drivers/nu_timer_pwm.h @@ -0,0 +1,877 @@ +/**************************************************************************//** + * @file timer.h + * @version V3.00 + * @brief Timer PWM Controller(Timer PWM) driver header file + * + * @copyright SPDX-License-Identifier: Apache-2.0 + * @copyright Copyright (C) 2020 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ +#ifndef __NU_TIMER_PWM_H__ +#define __NU_TIMER_PWM_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup TIMER_PWM_Driver TIMER PWM Driver + @{ +*/ + +/** @addtogroup TIMER_PWM_EXPORTED_CONSTANTS TIMER PWM Exported Constants + @{ +*/ +/*---------------------------------------------------------------------------------------------------------*/ +/* Output Channel Constant Definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define TPWM_CH0 (BIT0) /*!< Indicate PWMx_CH0 \hideinitializer */ +#define TPWM_CH1 (BIT1) /*!< Indicate PWMx_CH1 \hideinitializer */ + +/*---------------------------------------------------------------------------------------------------------*/ +/* Counter Type Constant Definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define TPWM_UP_COUNT (0UL << TIMER_PWMCTL_CNTTYPE_Pos) /*!< Up count type \hideinitializer */ +#define TPWM_DOWN_COUNT (1UL << TIMER_PWMCTL_CNTTYPE_Pos) /*!< Down count type \hideinitializer */ +#define TPWM_UP_DOWN_COUNT (2UL << TIMER_PWMCTL_CNTTYPE_Pos) /*!< Up-Down count type \hideinitializer */ + +/*---------------------------------------------------------------------------------------------------------*/ +/* Counter Mode Constant Definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define TPWM_AUTO_RELOAD_MODE (0UL) /*!< Auto-reload mode \hideinitializer */ +#define TPWM_ONE_SHOT_MODE (TIMER_PWMCTL_CNTMODE_Msk) /*!< One-shot mode \hideinitializer */ + +/*---------------------------------------------------------------------------------------------------------*/ +/* Output Level Constant Definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define TPWM_OUTPUT_TOGGLE (0UL) /*!< Timer PWM output toggle \hideinitializer */ +#define TPWM_OUTPUT_NOTHING (1UL) /*!< Timer PWM output nothing \hideinitializer */ +#define TPWM_OUTPUT_LOW (2UL) /*!< Timer PWM output low \hideinitializer */ +#define TPWM_OUTPUT_HIGH (3UL) /*!< Timer PWM output high \hideinitializer */ + +/*---------------------------------------------------------------------------------------------------------*/ +/* Trigger Event Source Select Constant Definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define TPWM_TRIGGER_EVENT_AT_ZERO_POINT (0UL << TIMER_PWMTRGCTL_TRGSEL_Pos) /*!< Timer PWM trigger event while counter zero point event occurred \hideinitializer */ +#define TPWM_TRIGGER_EVENT_AT_PERIOD_POINT (1UL << TIMER_PWMTRGCTL_TRGSEL_Pos) /*!< Timer PWM trigger event while counter period point event occurred \hideinitializer */ +#define TPWM_TRIGGER_EVENT_AT_ZERO_OR_PERIOD_POINT (2UL << TIMER_PWMTRGCTL_TRGSEL_Pos) /*!< Timer PWM trigger event while counter zero or period point event occurred \hideinitializer */ +#define TPWM_TRIGGER_EVENT_AT_COMPARE_UP_POINT (3UL << TIMER_PWMTRGCTL_TRGSEL_Pos) /*!< Timer PWM trigger event while counter up count compare point event occurred \hideinitializer */ +#define TPWM_TRIGGER_EVENT_AT_COMPARE_DOWN_POINT (4UL << TIMER_PWMTRGCTL_TRGSEL_Pos) /*!< Timer PWM trigger event while counter down count compare point event occurred \hideinitializer */ +#define TPWM_TRIGGER_EVENT_AT_PERIOD_OR_COMPARE_UP_POINT (5UL << TIMER_PWMTRGCTL_TRGSEL_Pos) /*!< Timer PWM trigger event while counter period or up count compare point event occurred \hideinitializer */ + +/*---------------------------------------------------------------------------------------------------------*/ +/* Brake Control Constant Definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define TPWM_BRAKE_SOURCE_EDGE_ACMP0 (TIMER_PWMBRKCTL_CPO0EBEN_Msk) /*!< Comparator 0 as edge-detect fault brake source \hideinitializer */ +#define TPWM_BRAKE_SOURCE_EDGE_ACMP1 (TIMER_PWMBRKCTL_CPO1EBEN_Msk) /*!< Comparator 1 as edge-detect fault brake source \hideinitializer */ +#define TPWM_BRAKE_SOURCE_EDGE_BKPIN (TIMER_PWMBRKCTL_BRKPEEN_Msk) /*!< Brake pin as edge-detect fault brake source \hideinitializer */ +#define TPWM_BRAKE_SOURCE_EDGE_SYS_CSS (TIMER_PWMBRKCTL_SYSEBEN_Msk | (TIMER_PWMFAILBRK_CSSBRKEN_Msk << 16)) /*!< System fail condition: clock security system detection as edge-detect fault brake source \hideinitializer */ +#define TPWM_BRAKE_SOURCE_EDGE_SYS_BOD (TIMER_PWMBRKCTL_SYSEBEN_Msk | (TIMER_PWMFAILBRK_BODBRKEN_Msk << 16)) /*!< System fail condition: brown-out detection as edge-detect fault brake source \hideinitializer */ +#define TPWM_BRAKE_SOURCE_EDGE_SYS_COR (TIMER_PWMBRKCTL_SYSEBEN_Msk | (TIMER_PWMFAILBRK_CORBRKEN_Msk << 16)) /*!< System fail condition: core lockup detection as edge-detect fault brake source \hideinitializer */ +#define TPWM_BRAKE_SOURCE_EDGE_SYS_RAM (TIMER_PWMBRKCTL_SYSEBEN_Msk | (TIMER_PWMFAILBRK_RAMBRKEN_Msk << 16)) /*!< System fail condition: SRAM parity error detection as edge-detect fault brake source \hideinitializer */ + +#define TPWM_BRAKE_SOURCE_LEVEL_ACMP0 (TIMER_PWMBRKCTL_CPO0LBEN_Msk) /*!< Comparator 0 as level-detect fault brake source \hideinitializer */ +#define TPWM_BRAKE_SOURCE_LEVEL_ACMP1 (TIMER_PWMBRKCTL_CPO1LBEN_Msk) /*!< Comparator 1 as level-detect fault brake source \hideinitializer */ +#define TPWM_BRAKE_SOURCE_LEVEL_BKPIN (TIMER_PWMBRKCTL_BRKPLEN_Msk) /*!< Brake pin as level-detect fault brake source \hideinitializer */ +#define TPWM_BRAKE_SOURCE_LEVEL_SYS_CSS (TIMER_PWMBRKCTL_SYSLBEN_Msk | (TIMER_PWMFAILBRK_CSSBRKEN_Msk << 16)) /*!< System fail condition: clock security system detection as level-detect fault brake source \hideinitializer */ +#define TPWM_BRAKE_SOURCE_LEVEL_SYS_BOD (TIMER_PWMBRKCTL_SYSLBEN_Msk | (TIMER_PWMFAILBRK_BODBRKEN_Msk << 16)) /*!< System fail condition: brown-out detection as level-detect fault brake source \hideinitializer */ +#define TPWM_BRAKE_SOURCE_LEVEL_SYS_COR (TIMER_PWMBRKCTL_SYSLBEN_Msk | (TIMER_PWMFAILBRK_CORBRKEN_Msk << 16)) /*!< System fail condition: core lockup detection as level-detect fault brake source \hideinitializer */ +#define TPWM_BRAKE_SOURCE_LEVEL_SYS_RAM (TIMER_PWMBRKCTL_SYSLBEN_Msk | (TIMER_PWMFAILBRK_RAMBRKEN_Msk << 16)) /*!< System fail condition: SRAM parity error detection as level-detect fault brake source \hideinitializer */ + +#define TPWM_BRAKE_EDGE (TIMER_PWMSWBRK_BRKETRG_Msk) /*!< Edge-detect fault brake \hideinitializer */ +#define TPWM_BRAKE_LEVEL (TIMER_PWMSWBRK_BRKLTRG_Msk) /*!< Level-detect fault brake \hideinitializer */ + +/*---------------------------------------------------------------------------------------------------------*/ +/* Load Mode Constant Definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define TPWM_LOAD_MODE_PERIOD (0UL) /*!< Timer PWM period load mode \hideinitializer */ +#define TPWM_LOAD_MODE_IMMEDIATE (TIMER_PWMCTL_IMMLDEN_Msk) /*!< Timer PWM immediately load mode \hideinitializer */ +#define TPWM_LOAD_MODE_CENTER (TIMER_PWMCTL_CTRLD_Msk) /*!< Timer PWM center load mode \hideinitializer */ + +/*---------------------------------------------------------------------------------------------------------*/ +/* Brake Pin De-bounce Clock Source Select Constant Definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define TPWM_BKP_DBCLK_PCLK_DIV_1 (0UL) /*!< De-bounce clock is PCLK divide by 1 \hideinitializer */ +#define TPWM_BKP_DBCLK_PCLK_DIV_2 (1UL) /*!< De-bounce clock is PCLK divide by 2 \hideinitializer */ +#define TPWM_BKP_DBCLK_PCLK_DIV_4 (2UL) /*!< De-bounce clock is PCLK divide by 4 \hideinitializer */ +#define TPWM_BKP_DBCLK_PCLK_DIV_8 (3UL) /*!< De-bounce clock is PCLK divide by 8 \hideinitializer */ +#define TPWM_BKP_DBCLK_PCLK_DIV_16 (4UL) /*!< De-bounce clock is PCLK divide by 16 \hideinitializer */ +#define TPWM_BKP_DBCLK_PCLK_DIV_32 (5UL) /*!< De-bounce clock is PCLK divide by 32 \hideinitializer */ +#define TPWM_BKP_DBCLK_PCLK_DIV_64 (6UL) /*!< De-bounce clock is PCLK divide by 64 \hideinitializer */ +#define TPWM_BKP_DBCLK_PCLK_DIV_128 (7UL) /*!< De-bounce clock is PCLK divide by 128 \hideinitializer */ + +/*---------------------------------------------------------------------------------------------------------*/ +/* Brake Pin Source Select Constant Definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define TPWM_TM_BRAKE0 (0UL) /*!< Brake pin source comes from TM_BRAKE0 \hideinitializer */ +#define TPWM_TM_BRAKE1 (1UL) /*!< Brake pin source comes from TM_BRAKE1 \hideinitializer */ +#define TPWM_TM_BRAKE2 (2UL) /*!< Brake pin source comes from TM_BRAKE2 \hideinitializer */ +#define TPWM_TM_BRAKE3 (3UL) /*!< Brake pin source comes from TM_BRAKE3 \hideinitializer */ + +/*---------------------------------------------------------------------------------------------------------*/ +/* Counter Clock Source Select Constant Definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define TPWM_CNTR_CLKSRC_TMR_CLK (0UL) /*!< Timer PWM Clock source selects to TMR_CLK \hideinitializer */ +#define TPWM_CNTR_CLKSRC_TIMER0_INT (1UL) /*!< Timer PWM Clock source selects to TIMER0 interrupt event \hideinitializer */ +#define TPWM_CNTR_CLKSRC_TIMER1_INT (2UL) /*!< Timer PWM Clock source selects to TIMER1 interrupt event \hideinitializer */ +#define TPWM_CNTR_CLKSRC_TIMER2_INT (3UL) /*!< Timer PWM Clock source selects to TIMER2 interrupt event \hideinitializer */ +#define TPWM_CNTR_CLKSRC_TIMER3_INT (4UL) /*!< Timer PWM Clock source selects to TIMER3 interrupt event \hideinitializer */ + +/*---------------------------------------------------------------------------------------------------------*/ +/* Counter Synchronous Mode Constant Definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define TPWM_CNTR_SYNC_DISABLE (0UL) /*!< Disable TIMER PWM synchronous function \hideinitializer */ +#define TPWM_CNTR_SYNC_START_BY_TIMER0 ((0<PWMCTL) & TMR45_BASE) == TMR45_BASE) { \ + (timer)->CTL |= TIMER_CTL_FUNCSEL_Msk; \ + while(((timer)->CTL & TIMER_CTL_FUNCSEL_Msk) == 0) {} \ + } else { \ + (timer)->ALTCTL = TIMER_ALTCTL_FUNCSEL_Msk; \ + while(((timer)->ALTCTL & TIMER_ALTCTL_FUNCSEL_Msk) == 0) {} \ + } \ + }while(0) + +/** + * @brief Disable PWM Counter Mode + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0 ~ TIMER5. + * + * @return None + * + * @details This macro is used to disable specified Timer channel as PWM counter mode, then timer counter mode is available. + * @note All registers about PWM counter function will be cleared to 0 after executing this macro. + * \hideinitializer + */ +#define TPWM_DISABLE_PWM_MODE(timer) \ + do{ \ + if(((uint32_t)&((timer)->PWMCTL) & TMR45_BASE) == TMR45_BASE) { \ + (timer)->CTL &= ~TIMER_CTL_FUNCSEL_Msk; \ + while(((timer)->CTL & TIMER_CTL_FUNCSEL_Msk) == TIMER_CTL_FUNCSEL_Msk) {} \ + } else { \ + (timer)->ALTCTL &= ~TIMER_ALTCTL_FUNCSEL_Msk; \ + while(((timer)->ALTCTL & TIMER_ALTCTL_FUNCSEL_Msk) == TIMER_ALTCTL_FUNCSEL_Msk) {} \ + } \ + }while(0) + + +/** + * @brief Enable Independent Mode + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @return None + * + * @details This macro is used to enable independent mode of TIMER PWM module and complementary mode will be disabled. + * @note NOT available on TIMER4 and TIMER5. + * \hideinitializer + */ +#define TPWM_ENABLE_INDEPENDENT_MODE(timer) ((timer)->PWMCTL &= ~(1ul << TIMER_PWMCTL_OUTMODE_Pos)) + +/** + * @brief Enable Complementary Mode + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @return None + * + * @details This macro is used to enable complementary mode of Timer PWM module and independent mode will be disabled. + * @note NOT available on TIMER4 and TIMER5. + * \hideinitializer + */ +#define TPWM_ENABLE_COMPLEMENTARY_MODE(timer) ((timer)->PWMCTL |= (1 << TIMER_PWMCTL_OUTMODE_Pos)) + +/** + * @brief Set Counter Type + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * @param[in] type Timer PWM count type, could be one of the following type + * - \ref TPWM_UP_COUNT + * - \ref TPWM_DOWN_COUNT + * - \ref TPWM_UP_DOWN_COUNT + * + * @return None + * + * @details This macro is used to set Timer PWM counter type. + * @note NOT available on TIMER4 and TIMER5. Both TIMER4 and TIMER5 are only support count up. + * \hideinitializer + */ +#define TPWM_SET_COUNTER_TYPE(timer, type) ((timer)->PWMCTL = ((timer)->PWMCTL & ~TIMER_PWMCTL_CNTTYPE_Msk) | (type)) + +/** + * @brief Start PWM Counter + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0 ~ TIMER5. + * + * @return None + * + * @details This macro is used to enable PWM generator and start counter counting. + * \hideinitializer + */ +#define TPWM_START_COUNTER(timer) ((timer)->PWMCTL |= TIMER_PWMCTL_CNTEN_Msk) + +/** + * @brief Stop PWM Counter + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0 ~ TIMER5. + * + * @return None + * + * @details This macro is used to stop PWM counter after current period is completed. + * \hideinitializer + */ +#define TPWM_STOP_COUNTER(timer) ((timer)->PWMPERIOD = 0x0) + +/** + * @brief Set Counter Clock Prescaler + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0 ~ TIMER5. + * + * @param[in] prescaler Clock prescaler of specified channel. + * Valid values are between 0x0~0xFFF for TIMER0, TIMER1, TIMER2, TIMER3, and + * valid values are between 0x0~0xFF for TIMER4 and TIMER5. + * + * @return None + * + * @details This macro is used to set the prescaler of specified TIMER PWM. + * @note If prescaler is 0, then there is no scaling in counter clock source. + * \hideinitializer + */ +#define TPWM_SET_PRESCALER(timer, prescaler) ((timer)->PWMCLKPSC = (prescaler)) + +/** + * @brief Get Counter Clock Prescaler + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0 ~ TIMER5. + * + * @return Target prescaler setting, CLKPSC (TIMERx_PWMCLKPSC[11:0]) + * + * @details Get the prescaler setting, the target counter clock divider is (CLKPSC + 1). + * \hideinitializer + */ +#define TPWM_GET_PRESCALER(timer) ((timer)->PWMCLKPSC) + +/** + * @brief Set Couner Period + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0 ~ TIMER5. + * + * @param[in] period Period of specified channel. Valid values are between 0x0~0xFFFF. + * + * @return None + * + * @details This macro is used to set the period of specified TIMER PWM. + * \hideinitializer + */ +#define TPWM_SET_PERIOD(timer, period) ((timer)->PWMPERIOD = (period)) + +/** + * @brief Get Couner Period + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0 ~ TIMER5. + * + * @return Target period setting, PERIOD (TIMERx_PWMPERIOD[15:0]) + * + * @details This macro is used to get the period of specified TIMER PWM. + * \hideinitializer + */ +#define TPWM_GET_PERIOD(timer) ((timer)->PWMPERIOD) + +/** + * @brief Set Comparator Value + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0 ~ TIMER5. + * + * @param[in] cmp Comparator of specified channel. Valid values are between 0x0~0xFFFF. + * + * @return None + * + * @details This macro is used to set the comparator value of specified TIMER PWM. + * \hideinitializer + */ +#define TPWM_SET_CMPDAT(timer, cmp) ((timer)->PWMCMPDAT = (cmp)) + +/** + * @brief Get Comparator Value + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0 ~ TIMER5. + * + * @return Target comparator setting, CMPDAT (TIMERx_PWMCMPDAT[15:0]) + * + * @details This macro is used to get the comparator value of specified TIMER PWM. + * \hideinitializer + */ +#define TPWM_GET_CMPDAT(timer) ((timer)->PWMCMPDAT) + +/** + * @brief Clear Counter + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0 ~ TIMER5. + * + * @return None + * + * @details This macro is used to clear counter of specified TIMER PWM. + * \hideinitializer + */ +#define TPWM_CLEAR_COUNTER(timer) ((timer)->PWMCNTCLR = TIMER_PWMCNTCLR_CNTCLR_Msk) + +/** + * @brief Software Trigger Brake Event + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @param[in] type Type of brake trigger. Valid values are: + * - \ref TPWM_BRAKE_EDGE + * - \ref TPWM_BRAKE_LEVEL + * + * @return None + * + * @details This macro is used to trigger brake event by writing PWMSWBRK register. + * @note NOT available on TIMER4 and TIMER5. + * \hideinitializer + */ +#define TPWM_SW_TRIGGER_BRAKE(timer, type) ((timer)->PWMSWBRK = (type)) + +/** + * @brief Enable Output Function + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0 ~ TIMER5. + * + * @param[in] ch Enable specified channel output function. Valid values are: + * For TIMER0 ~ TIMER3, the valid value could be a combination of \ref TPWM_CH0 and \ref TPWM_CH1. + * For TIMER4, TIMER5, the valid value could be \ref TPWM_CH0 or \ref TPWM_CH1. + * + * @return None + * + * @details This macro is used to enable output function of specified output pins. + * \hideinitializer + */ +#define TPWM_ENABLE_OUTPUT(timer, ch) \ + do{ \ + if(((uint32_t)&((timer)->PWMCTL) & TMR45_BASE) == TMR45_BASE) { \ + if((ch) == BIT0) \ + (timer)->PWMPOEN = BIT0; \ + else \ + (timer)->PWMPOEN = (BIT0 | BIT8); \ + } else { \ + (timer)->PWMPOEN = (ch); \ + } \ + }while(0) + +/** + * @brief Set Output Inverse + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0 ~ TIMER5. + * + * @param[in] ch Set specified channel output is inversed or not. + * For TIMER0 ~ TIMER3, the valid value could be a combination of \ref TPWM_CH0 and \ref TPWM_CH1. + * But this parameter is no effect on TIMER4 and TIMER5. + * + * @return None + * + * @details This macro is used to enable output inverse of specified output pins. + * \hideinitializer + */ +#define TPWM_SET_OUTPUT_INVERSE(timer, ch) \ + do{ \ + if(((uint32_t)&((timer)->PWMCTL) & TMR45_BASE) == TMR45_BASE) { \ + (timer)->PWMPOLCTL = BIT0; \ + } else { \ + (timer)->PWMPOLCTL = (ch); \ + } \ + }while(0) + +/** + * @brief Enable Output Mask Function + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @param[in] ch Enable specified channel output mask function. Valid value could be a combination of \ref TPWM_CH0 and \ref TPWM_CH1. + * + * @param[in] level Output to high or low on specified mask channel. + * + * @return None + * + * @details This macro is used to enable output mask function of specified output pins. + * @note NOT available on TIMER4 and TIMER5. + * \hideinitializer + */ +#define TPWM_SET_MASK_OUTPUT(timer, ch, level) do {(timer)->PWMMSKEN = (ch); (timer)->PWMMSK = (level); }while(0) + +/** + * @brief Set Counter Synchronous Mode + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @param[in] mode Synchronous mode. Possible options are: + * - \ref TPWM_CNTR_SYNC_DISABLE + * - \ref TPWM_CNTR_SYNC_START_BY_TIMER0 + * - \ref TPWM_CNTR_SYNC_CLEAR_BY_TIMER0 + * - \ref TPWM_CNTR_SYNC_START_BY_TIMER2 + * - \ref TPWM_CNTR_SYNC_CLEAR_BY_TIMER2 + * + * @return None + * + * @details This macro is used to set counter synchronous mode of specified Timer PWM module. + * @note Only support all PWM counters are synchronous by TIMER0 PWM or TIMER0~1 PWM counter synchronous by TIMER0 PWM and + * TIMER2~3 PWM counter synchronous by TIMER2 PWM. + * @note NOT available on TIMER4 and TIMER5. + * \hideinitializer + */ +#define TPWM_SET_COUNTER_SYNC_MODE(timer, mode) ((timer)->PWMSCTL = (mode)) + +/** + * @brief Trigger Counter Synchronous + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @return None + * + * @details This macro is used to trigger synchronous event by specified TIMER PWM. + * @note 1. This macro is only available for TIMER0 PWM and TIMER2 PWM. \n + * 2. STRGEN (PWMSTRG[0]) is write only and always read as 0. + * @note NOT available on TIMER4 and TIMER5. + * \hideinitializer + */ +#define TPWM_TRIGGER_COUNTER_SYNC(timer) ((timer)->PWMSTRG = TIMER_PWMSTRG_STRGEN_Msk) + +/** + * @brief Enable Timer PWM Interrupt Wake-up Function + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER4 or TIMER5. + * + * @return None + * + * @details This macro is used to enable the timer pwm interrupt wake-up function. + * @note Only available on TIMER4 and TIMER5. + * \hideinitializer + */ +#define TPWM_ENABLE_PWMINT_WAKEUP(timer) ((timer)->PWMCTL |= TIMER_PWMCTL_WKEN_Msk) + +/** + * @brief Disable Timer PWM Interrupt Wake-up Function + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER4 or TIMER5. + * + * @return None + * + * @details This macro is used to disable the timer pwm interrupt wake-up function. + * @note Only available on TIMER4 and TIMER5. + * \hideinitializer + */ +#define TPWM_DISABLE_PWMINT_WAKEUP(timer) ((timer)->PWMCTL &= ~TIMER_PWMCTL_WKEN_Msk) + +/** + * @brief Enable Zero Event Interrupt + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @return None + * + * @details This macro is used to enable the zero event interrupt function. + * @note NOT available on TIMER4 and TIMER5. + * \hideinitializer + */ +#define TPWM_ENABLE_ZERO_INT(timer) ((timer)->PWMINTEN0 |= TIMER_PWMINTEN0_ZIEN_Msk) + +/** + * @brief Disable Zero Event Interrupt + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @return None + * + * @details This macro is used to disable the zero event interrupt function. + * @note NOT available on TIMER4 and TIMER5. + * \hideinitializer + */ +#define TPWM_DISABLE_ZERO_INT(timer) ((timer)->PWMINTEN0 &= ~TIMER_PWMINTEN0_ZIEN_Msk) + +/** + * @brief Get Zero Event Interrupt Flag + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @retval 0 Zero event interrupt did not occur + * @retval 1 Zero event interrupt occurred + * + * @details This macro indicates zero event occurred or not. + * @note NOT available on TIMER4 and TIMER5. + * \hideinitializer + */ +#define TPWM_GET_ZERO_INT_FLAG(timer) (((timer)->PWMINTSTS0 & TIMER_PWMINTSTS0_ZIF_Msk)? 1 : 0) + +/** + * @brief Clear Zero Event Interrupt Flag + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @return None + * + * @details This macro clears zero event interrupt flag. + * @note NOT available on TIMER4 and TIMER5. + * \hideinitializer + */ +#define TPWM_CLEAR_ZERO_INT_FLAG(timer) ((timer)->PWMINTSTS0 = TIMER_PWMINTSTS0_ZIF_Msk) + +/** + * @brief Enable Period Event Interrupt + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0 ~ TIMER5. + * + * @return None + * + * @details This macro is used to enable the period event interrupt function. + * \hideinitializer + */ +#define TPWM_ENABLE_PERIOD_INT(timer) ((timer)->PWMINTEN0 |= TIMER_PWMINTEN0_PIEN_Msk) + +/** + * @brief Disable Period Event Interrupt + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0 ~ TIMER5. + * + * @return None + * + * @details This macro is used to disable the period event interrupt function. + * \hideinitializer + */ +#define TPWM_DISABLE_PERIOD_INT(timer) ((timer)->PWMINTEN0 &= ~TIMER_PWMINTEN0_PIEN_Msk) + +/** + * @brief Get Period Event Interrupt Flag + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0 ~ TIMER5. + * + * @retval 0 Period event interrupt did not occur + * @retval 1 Period event interrupt occurred + * + * @details This macro indicates period event occurred or not. + * \hideinitializer + */ +#define TPWM_GET_PERIOD_INT_FLAG(timer) (((timer)->PWMINTSTS0 & TIMER_PWMINTSTS0_PIF_Msk)? 1 : 0) + +/** + * @brief Clear Period Event Interrupt Flag + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0 ~ TIMER5. + * + * @return None + * + * @details This macro clears period event interrupt flag. + * \hideinitializer + */ +#define TPWM_CLEAR_PERIOD_INT_FLAG(timer) ((timer)->PWMINTSTS0 = TIMER_PWMINTSTS0_PIF_Msk) + +/** + * @brief Enable Compare Up Event Interrupt + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0 ~ TIMER5. + * + * @return None + * + * @details This macro is used to enable the compare up event interrupt function. + * \hideinitializer + */ +#define TPWM_ENABLE_CMP_UP_INT(timer) ((timer)->PWMINTEN0 |= TIMER_PWMINTEN0_CMPUIEN_Msk) + +/** + * @brief Disable Compare Up Event Interrupt + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0 ~ TIMER5. + * + * @return None + * + * @details This macro is used to disable the compare up event interrupt function. + * \hideinitializer + */ +#define TPWM_DISABLE_CMP_UP_INT(timer) ((timer)->PWMINTEN0 &= ~TIMER_PWMINTEN0_CMPUIEN_Msk) + +/** + * @brief Get Compare Up Event Interrupt Flag + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0 ~ TIMER5. + * + * @retval 0 Compare up event interrupt did not occur + * @retval 1 Compare up event interrupt occurred + * + * @details This macro indicates compare up event occurred or not. + * \hideinitializer + */ +#define TPWM_GET_CMP_UP_INT_FLAG(timer) (((timer)->PWMINTSTS0 & TIMER_PWMINTSTS0_CMPUIF_Msk)? 1 : 0) + +/** + * @brief Clear Compare Up Event Interrupt Flag + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0 ~ TIMER5. + * + * @return None + * + * @details This macro clears compare up event interrupt flag. + * \hideinitializer + */ +#define TPWM_CLEAR_CMP_UP_INT_FLAG(timer) ((timer)->PWMINTSTS0 = TIMER_PWMINTSTS0_CMPUIF_Msk) + +/** + * @brief Enable Compare Down Event Interrupt + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @return None + * + * @details This macro is used to enable the compare down event interrupt function. + * @note NOT available on TIMER4 and TIMER5. + * \hideinitializer + */ +#define TPWM_ENABLE_CMP_DOWN_INT(timer) ((timer)->PWMINTEN0 |= TIMER_PWMINTEN0_CMPDIEN_Msk) + +/** + * @brief Disable Compare Down Event Interrupt + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @return None + * + * @details This macro is used to disable the compare down event interrupt function. + * @note NOT available on TIMER4 and TIMER5. + * \hideinitializer + */ +#define TPWM_DISABLE_CMP_DOWN_INT(timer) ((timer)->PWMINTEN0 &= ~TIMER_PWMINTEN0_CMPDIEN_Msk) + +/** + * @brief Get Compare Down Event Interrupt Flag + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @retval 0 Compare down event interrupt did not occur + * @retval 1 Compare down event interrupt occurred + * + * @details This macro indicates compare down event occurred or not. + * @note NOT available on TIMER4 and TIMER5. + * \hideinitializer + */ +#define TPWM_GET_CMP_DOWN_INT_FLAG(timer) (((timer)->PWMINTSTS0 & TIMER_PWMINTSTS0_CMPDIF_Msk)? 1 : 0) + +/** + * @brief Clear Compare Down Event Interrupt Flag + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @return None + * + * @details This macro clears compare down event interrupt flag. + * @note NOT available on TIMER4 and TIMER5. + * \hideinitializer + */ +#define TPWM_CLEAR_CMP_DOWN_INT_FLAG(timer) ((timer)->PWMINTSTS0 = TIMER_PWMINTSTS0_CMPDIF_Msk) + +/** + * @brief Get Counter Reach Maximum Count Status + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0 ~ TIMER5. + * + * @retval 0 Timer PWM counter never counts to maximum value + * @retval 1 Timer PWM counter counts to maximum value, 0xFFFF + * + * @details This macro indicates Timer PWM counter has count to 0xFFFF or not. + * \hideinitializer + */ +#define TPWM_GET_REACH_MAX_CNT_STATUS(timer) (((timer)->PWMSTATUS & TIMER_PWMSTATUS_CNTMAXF_Msk)? 1 : 0) + +/** + * @brief Clear Counter Reach Maximum Count Status + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0 ~ TIMER5. + * + * @return None + * + * @details This macro clears reach maximum count status. + * \hideinitializer + */ +#define TPWM_CLEAR_REACH_MAX_CNT_STATUS(timer) ((timer)->PWMSTATUS = TIMER_PWMSTATUS_CNTMAXF_Msk) + +/** + * @brief Get Trigger ADC Status + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0 ~ TIMER5. + * + * @retval 0 Trigger ADC start conversion is not occur + * @retval 1 Specified counter compare event has trigger ADC start conversion + * + * @details This macro is used to indicate PWM counter compare event has triggered ADC start conversion. + * \hideinitializer + */ +#define TPWM_GET_TRG_ADC_STATUS(timer) (((timer)->PWMSTATUS & TIMER_PWMSTATUS_EADCTRGF_Msk)? 1 : 0) + +/** + * @brief Clear Trigger ADC Status + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0 ~ TIMER5. + * + * @return None + * + * @details This macro is used to clear PWM counter compare event trigger ADC status. + * \hideinitializer + */ +#define TPWM_CLEAR_TRG_ADC_STATUS(timer) ((timer)->PWMSTATUS = TIMER_PWMSTATUS_EADCTRGF_Msk) + +/** + * @brief Get Trigger PDMA Status + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER4 ~ TIMER5. + * + * @retval 0 Trigger PDMA transfer data is not occur + * @retval 1 Specified counter compare event has trigger PDMA transfer data + * + * @details This macro is used to indicate PWM counter compare event has triggered PDMA start transfer data. + * @note Only available on TIMER4 and TIMER5. + * \hideinitializer + */ +#define TPWM_GET_TRG_PDMA_STATUS(timer) (((timer)->PWMSTATUS & TIMER_PWMSTATUS_PDMATRGF_Msk)? 1 : 0) + +/** + * @brief Clear Trigger PDMA Status + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER4 ~ TIMER5. + * + * @return None + * + * @details This macro is used to clear PWM counter compare event trigger PDMA status. + * @note Only available on TIMER4 and TIMER5. + * \hideinitializer + */ +#define TPWM_CLEAR_TRG_PDMA_STATUS(timer) ((timer)->PWMSTATUS = TIMER_PWMSTATUS_PDMATRGF_Msk) + +/** + * @brief Get PWM Interrupt Wake-up Flag + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER4 ~ TIMER5. + * + * @retval 0 PWM does not cause CPU wake-up + * @retval 1 PWM interrupt event cause CPU wake-up + * + * @details This function indicates PWM interrupt event has waked up system or not. + * @note Only available on TIMER4 and TIMER5. + */ +#define TPWM_GET_PWMINT_WAKEUP_STATUS(timer) (((timer)->PWMSTATUS & TIMER_PWMSTATUS_WKF_Msk)? 1 : 0) + +/** + * @brief Clear PWM Interrupt Wake-up Flag + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER4 ~ TIMER5. + * + * @return None + * + * @details This macro is used to clear PWM interrupt wakeup status. + * @note Only available on TIMER4 and TIMER5. + * \hideinitializer + */ +#define TPWM_CLEAR_PWMINT_WAKEUP_STATUS(timer) ((timer)->PWMSTATUS = TIMER_PWMSTATUS_WKF_Msk) + +/** + * @brief Set Brake Event at Brake Pin High or Low-to-High + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @return None + * + * @details This macro is used to set detect brake event when external brake pin at high level or transfer from low to high. + * @note The default brake pin detection is high level or from low to high. + * @note NOT available on TIMER4 and TIMER5. + * \hideinitializer + */ +#define TPWM_SET_BRAKE_PIN_HIGH_DETECT(timer) ((timer)->PWMBNF &= ~TIMER_PWMBNF_BRKPINV_Msk) + +/** + * @brief Set Brake Event at Brake Pin Low or High-to-Low + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @return None + * + * @details This macro is used to set detect brake event when external brake pin at low level or transfer from high to low. + * @note NOT available on TIMER4 and TIMER5. + * \hideinitializer + */ +#define TPWM_SET_BRAKE_PIN_LOW_DETECT(timer) ((timer)->PWMBNF |= TIMER_PWMBNF_BRKPINV_Msk) + +/** + * @brief Set External Brake Pin Source + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * @param[in] pin The external brake pin source, could be one of following source + * - \ref TPWM_TM_BRAKE0 + * - \ref TPWM_TM_BRAKE1 + * - \ref TPWM_TM_BRAKE2 + * - \ref TPWM_TM_BRAKE3 + * + * @return None + * + * @details This macro is used to set detect brake event when external brake pin at high level or transfer from low to high. + * @note NOT available on TIMER4 and TIMER5. + * \hideinitializer + */ +#define TPWM_SET_BRAKE_PIN_SOURCE(timer, pin) ((timer)->PWMBNF = ((timer)->PWMBNF & ~TIMER_PWMBNF_BKPINSRC_Msk) | ((pin)< + +#ifdef __cplusplus +extern "C" +{ +#endif + + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup UART_Driver UART Driver + @{ +*/ + +/** @addtogroup UART_EXPORTED_CONSTANTS UART Exported Constants + @{ +*/ + +/*---------------------------------------------------------------------------------------------------------*/ +/* UART FIFO size constants definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define UART0_FIFO_SIZE 16UL /*!< UART0 supports separated receive/transmit 16/16 bytes entry FIFO */ +#define UART1_FIFO_SIZE 16UL /*!< UART1 supports separated receive/transmit 16/16 bytes entry FIFO */ +#define UART2_FIFO_SIZE 16UL /*!< UART2 supports separated receive/transmit 16/16 bytes entry FIFO */ +#define UART3_FIFO_SIZE 16UL /*!< UART3 supports separated receive/transmit 16/16 bytes entry FIFO */ +#define UART4_FIFO_SIZE 16UL /*!< UART4 supports separated receive/transmit 16/16 bytes entry FIFO */ +#define UART5_FIFO_SIZE 16UL /*!< UART5 supports separated receive/transmit 16/16 bytes entry FIFO */ + + +/*---------------------------------------------------------------------------------------------------------*/ +/* UART_FIFO constants definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define UART_FIFO_RFITL_1BYTE (0x0UL << UART_FIFO_RFITL_Pos) /*!< UART_FIFO setting to set RX FIFO Trigger Level to 1 byte */ +#define UART_FIFO_RFITL_4BYTES (0x1UL << UART_FIFO_RFITL_Pos) /*!< UART_FIFO setting to set RX FIFO Trigger Level to 4 bytes */ +#define UART_FIFO_RFITL_8BYTES (0x2UL << UART_FIFO_RFITL_Pos) /*!< UART_FIFO setting to set RX FIFO Trigger Level to 8 bytes */ +#define UART_FIFO_RFITL_14BYTES (0x3UL << UART_FIFO_RFITL_Pos) /*!< UART_FIFO setting to set RX FIFO Trigger Level to 14 bytes */ + +#define UART_FIFO_RTSTRGLV_1BYTE (0x0UL << UART_FIFO_RTSTRGLV_Pos) /*!< UART_FIFO setting to set RTS Trigger Level to 1 byte */ +#define UART_FIFO_RTSTRGLV_4BYTES (0x1UL << UART_FIFO_RTSTRGLV_Pos) /*!< UART_FIFO setting to set RTS Trigger Level to 4 bytes */ +#define UART_FIFO_RTSTRGLV_8BYTES (0x2UL << UART_FIFO_RTSTRGLV_Pos) /*!< UART_FIFO setting to set RTS Trigger Level to 8 bytes */ +#define UART_FIFO_RTSTRGLV_14BYTES (0x3UL << UART_FIFO_RTSTRGLV_Pos) /*!< UART_FIFO setting to set RTS Trigger Level to 14 bytes */ + +/*---------------------------------------------------------------------------------------------------------*/ +/* UART_LINE constants definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define UART_WORD_LEN_5 (0UL) /*!< UART_LINE setting to set UART word length to 5 bits */ +#define UART_WORD_LEN_6 (1UL) /*!< UART_LINE setting to set UART word length to 6 bits */ +#define UART_WORD_LEN_7 (2UL) /*!< UART_LINE setting to set UART word length to 7 bits */ +#define UART_WORD_LEN_8 (3UL) /*!< UART_LINE setting to set UART word length to 8 bits */ + +#define UART_PARITY_NONE (0x0UL << UART_LINE_PBE_Pos) /*!< UART_LINE setting to set UART as no parity */ +#define UART_PARITY_ODD (0x1UL << UART_LINE_PBE_Pos) /*!< UART_LINE setting to set UART as odd parity */ +#define UART_PARITY_EVEN (0x3UL << UART_LINE_PBE_Pos) /*!< UART_LINE setting to set UART as even parity */ +#define UART_PARITY_MARK (0x5UL << UART_LINE_PBE_Pos) /*!< UART_LINE setting to keep parity bit as '1' */ +#define UART_PARITY_SPACE (0x7UL << UART_LINE_PBE_Pos) /*!< UART_LINE setting to keep parity bit as '0' */ + +#define UART_STOP_BIT_1 (0x0UL << UART_LINE_NSB_Pos) /*!< UART_LINE setting for one stop bit */ +#define UART_STOP_BIT_1_5 (0x1UL << UART_LINE_NSB_Pos) /*!< UART_LINE setting for 1.5 stop bit when 5-bit word length */ +#define UART_STOP_BIT_2 (0x1UL << UART_LINE_NSB_Pos) /*!< UART_LINE setting for two stop bit when 6, 7, 8-bit word length */ + + +/*---------------------------------------------------------------------------------------------------------*/ +/* UART RTS ACTIVE LEVEL constants definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define UART_RTS_IS_LOW_LEV_ACTIVE (0x1UL << UART_MODEM_RTSACTLV_Pos) /*!< Set RTS is Low Level Active */ +#define UART_RTS_IS_HIGH_LEV_ACTIVE (0x0UL << UART_MODEM_RTSACTLV_Pos) /*!< Set RTS is High Level Active */ + + +/*---------------------------------------------------------------------------------------------------------*/ +/* UART_IRDA constants definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define UART_IRDA_TXEN (0x1UL << UART_IRDA_TXEN_Pos) /*!< Set IrDA function Tx mode */ +#define UART_IRDA_RXEN (0x0UL << UART_IRDA_TXEN_Pos) /*!< Set IrDA function Rx mode */ + + +/*---------------------------------------------------------------------------------------------------------*/ +/* UART_FUNCSEL constants definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define UART_FUNCSEL_UART (0x0UL << UART_FUNCSEL_FUNCSEL_Pos) /*!< UART_FUNCSEL setting to set UART Function (Default) */ +#define UART_FUNCSEL_LIN (0x1UL << UART_FUNCSEL_FUNCSEL_Pos) /*!< UART_FUNCSEL setting to set LIN Function */ +#define UART_FUNCSEL_IrDA (0x2UL << UART_FUNCSEL_FUNCSEL_Pos) /*!< UART_FUNCSEL setting to set IrDA Function */ +#define UART_FUNCSEL_RS485 (0x3UL << UART_FUNCSEL_FUNCSEL_Pos) /*!< UART_FUNCSEL setting to set RS485 Function */ +#define UART_FUNCSEL_SINGLE_WIRE (0x4ul << UART_FUNCSEL_FUNCSEL_Pos) /*!< UART_FUNCSEL setting to set Single Wire Function */ + + +/*---------------------------------------------------------------------------------------------------------*/ +/* UART_LINCTL constants definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define UART_LINCTL_BRKFL(x) (((x)-1UL) << UART_LINCTL_BRKFL_Pos) /*!< UART_LINCTL setting to set LIN Break Field Length, x = 10 ~ 15, default value is 12 */ +#define UART_LINCTL_BSL(x) (((x)-1UL) << UART_LINCTL_BSL_Pos) /*!< UART_LINCTL setting to set LIN Break/Sync Delimiter Length, x = 1 ~ 4 */ +#define UART_LINCTL_HSEL_BREAK (0x0UL << UART_LINCTL_HSEL_Pos) /*!< UART_LINCTL setting to set LIN Header Select to break field */ +#define UART_LINCTL_HSEL_BREAK_SYNC (0x1UL << UART_LINCTL_HSEL_Pos) /*!< UART_LINCTL setting to set LIN Header Select to break field and sync field */ +#define UART_LINCTL_HSEL_BREAK_SYNC_ID (0x2UL << UART_LINCTL_HSEL_Pos) /*!< UART_LINCTL setting to set LIN Header Select to break field, sync field and ID field*/ +#define UART_LINCTL_PID(x) ((x) << UART_LINCTL_PID_Pos) /*!< UART_LINCTL setting to set LIN PID value */ + + +/*---------------------------------------------------------------------------------------------------------*/ +/* UART BAUDRATE MODE constants definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define UART_BAUD_MODE0 (0UL) /*!< Set UART Baudrate Mode is Mode0 */ +#define UART_BAUD_MODE2 (UART_BAUD_BAUDM1_Msk | UART_BAUD_BAUDM0_Msk) /*!< Set UART Baudrate Mode is Mode2 */ + + + +/**@}*/ /* end of group UART_EXPORTED_CONSTANTS */ + + +/** @addtogroup UART_EXPORTED_FUNCTIONS UART Exported Functions + @{ +*/ + + +/** + * @brief Calculate UART baudrate mode0 divider + * + * @param[in] u32SrcFreq UART clock frequency + * @param[in] u32BaudRate Baudrate of UART module + * + * @return UART baudrate mode0 divider + * + * @details This macro calculate UART baudrate mode0 divider. + */ +#define UART_BAUD_MODE0_DIVIDER(u32SrcFreq, u32BaudRate) ((((u32SrcFreq) + ((u32BaudRate)*8ul)) / (u32BaudRate) >> 4ul)-2ul) + + +/** + * @brief Calculate UART baudrate mode2 divider + * + * @param[in] u32SrcFreq UART clock frequency + * @param[in] u32BaudRate Baudrate of UART module + * + * @return UART baudrate mode2 divider + * + * @details This macro calculate UART baudrate mode2 divider. + */ +#define UART_BAUD_MODE2_DIVIDER(u32SrcFreq, u32BaudRate) ((((u32SrcFreq) + ((u32BaudRate)/2ul)) / (u32BaudRate))-2ul) + + +/** + * @brief Write UART data + * + * @param[in] uart The pointer of the specified UART module + * @param[in] u8Data Data byte to transmit. + * + * @return None + * + * @details This macro write Data to Tx data register. + */ +#define UART_WRITE(uart, u8Data) ((uart)->DAT = (u8Data)) + + +/** + * @brief Read UART data + * + * @param[in] uart The pointer of the specified UART module + * + * @return The oldest data byte in RX FIFO. + * + * @details This macro read Rx data register. + */ +#define UART_READ(uart) ((uart)->DAT) + + +/** + * @brief Get Tx empty + * + * @param[in] uart The pointer of the specified UART module + * + * @retval 0 Tx FIFO is not empty + * @retval >=1 Tx FIFO is empty + * + * @details This macro get Transmitter FIFO empty register value. + */ +#define UART_GET_TX_EMPTY(uart) ((uart)->FIFOSTS & UART_FIFOSTS_TXEMPTY_Msk) + + +/** + * @brief Get Rx empty + * + * @param[in] uart The pointer of the specified UART module + * + * @retval 0 Rx FIFO is not empty + * @retval >=1 Rx FIFO is empty + * + * @details This macro get Receiver FIFO empty register value. + */ +#define UART_GET_RX_EMPTY(uart) ((uart)->FIFOSTS & UART_FIFOSTS_RXEMPTY_Msk) + + +/** + * @brief Check specified uart port transmission is over. + * + * @param[in] uart The pointer of the specified UART module + * + * @retval 0 Tx transmission is not over + * @retval 1 Tx transmission is over + * + * @details This macro return Transmitter Empty Flag register bit value. + * It indicates if specified uart port transmission is over nor not. + */ +#define UART_IS_TX_EMPTY(uart) (((uart)->FIFOSTS & UART_FIFOSTS_TXEMPTYF_Msk) >> UART_FIFOSTS_TXEMPTYF_Pos) + + +/** + * @brief Wait specified uart port transmission is over + * + * @param[in] uart The pointer of the specified UART module + * + * @return None + * + * @details This macro wait specified uart port transmission is over. + */ +#define UART_WAIT_TX_EMPTY(uart) while(!((((uart)->FIFOSTS) & UART_FIFOSTS_TXEMPTYF_Msk) >> UART_FIFOSTS_TXEMPTYF_Pos)) + + +/** + * @brief Check RX is ready or not + * + * @param[in] uart The pointer of the specified UART module + * + * @retval 0 The number of bytes in the RX FIFO is less than the RFITL + * @retval 1 The number of bytes in the RX FIFO equals or larger than RFITL + * + * @details This macro check receive data available interrupt flag is set or not. + */ +#define UART_IS_RX_READY(uart) (((uart)->INTSTS & UART_INTSTS_RDAIF_Msk)>>UART_INTSTS_RDAIF_Pos) + + +/** + * @brief Check TX FIFO is full or not + * + * @param[in] uart The pointer of the specified UART module + * + * @retval 1 TX FIFO is full + * @retval 0 TX FIFO is not full + * + * @details This macro check TX FIFO is full or not. + */ +#define UART_IS_TX_FULL(uart) (((uart)->FIFOSTS & UART_FIFOSTS_TXFULL_Msk)>>UART_FIFOSTS_TXFULL_Pos) + + +/** + * @brief Check RX FIFO is full or not + * + * @param[in] uart The pointer of the specified UART module + * + * @retval 1 RX FIFO is full + * @retval 0 RX FIFO is not full + * + * @details This macro check RX FIFO is full or not. + */ +#define UART_IS_RX_FULL(uart) (((uart)->FIFOSTS & UART_FIFOSTS_RXFULL_Msk)>>UART_FIFOSTS_RXFULL_Pos) + + +/** + * @brief Get Tx full register value + * + * @param[in] uart The pointer of the specified UART module + * + * @retval 0 Tx FIFO is not full. + * @retval >=1 Tx FIFO is full. + * + * @details This macro get Tx full register value. + */ +#define UART_GET_TX_FULL(uart) ((uart)->FIFOSTS & UART_FIFOSTS_TXFULL_Msk) + + +/** + * @brief Get Rx full register value + * + * @param[in] uart The pointer of the specified UART module + * + * @retval 0 Rx FIFO is not full. + * @retval >=1 Rx FIFO is full. + * + * @details This macro get Rx full register value. + */ +#define UART_GET_RX_FULL(uart) ((uart)->FIFOSTS & UART_FIFOSTS_RXFULL_Msk) + +/** + * @brief Rx Idle Status register value + * + * @param[in] uart The pointer of the specified UART module + * + * @retval 0 Rx is busy. + * @retval 1 Rx is Idle(Default) + * + * @details This macro get Rx Idle Status register value. + * \hideinitializer + */ +#define UART_RX_IDLE(uart) (((uart)->FIFOSTS & UART_FIFOSTS_RXIDLE_Msk )>> UART_FIFOSTS_RXIDLE_Pos) + + +/** + * @brief Enable specified UART interrupt + * + * @param[in] uart The pointer of the specified UART module + * @param[in] u32eIntSel Interrupt type select + * - \ref UART_INTEN_TXENDIEN_Msk : Transmitter empty interrupt + * - \ref UART_INTEN_ABRIEN_Msk : Auto baud rate interrupt + * - \ref UART_INTEN_LINIEN_Msk : Lin bus interrupt + * - \ref UART_INTEN_WKIEN_Msk : Wake-up interrupt + * - \ref UART_INTEN_BUFERRIEN_Msk : Buffer Error interrupt + * - \ref UART_INTEN_RXTOIEN_Msk : Rx time-out interrupt + * - \ref UART_INTEN_MODEMIEN_Msk : Modem interrupt + * - \ref UART_INTEN_RLSIEN_Msk : Rx Line status interrupt + * - \ref UART_INTEN_THREIEN_Msk : Tx empty interrupt + * - \ref UART_INTEN_RDAIEN_Msk : Rx ready interrupt + * + * @return None + * + * @details This macro enable specified UART interrupt. + */ +#define UART_ENABLE_INT(uart, u32eIntSel) ((uart)->INTEN |= (u32eIntSel)) + + +/** + * @brief Disable specified UART interrupt + * + * @param[in] uart The pointer of the specified UART module + * @param[in] u32eIntSel Interrupt type select + * - \ref UART_INTEN_TXENDIEN_Msk : Transmitter Empty Interrupt + * - \ref UART_INTEN_ABRIEN_Msk : Auto-baud Rate Interrupt + * - \ref UART_INTEN_LINIEN_Msk : Lin Bus interrupt + * - \ref UART_INTEN_WKIEN_Msk : Wake-up interrupt + * - \ref UART_INTEN_BUFERRIEN_Msk : Buffer Error interrupt + * - \ref UART_INTEN_RXTOIEN_Msk : Rx Time-out Interrupt + * - \ref UART_INTEN_MODEMIEN_Msk : MODEM Status Interrupt + * - \ref UART_INTEN_RLSIEN_Msk : Receive Line Status Interrupt + * - \ref UART_INTEN_THREIEN_Msk : Transmit Holding Register Empty Interrupt + * - \ref UART_INTEN_RDAIEN_Msk : Receive Data Available Interrupt + * + * @return None + * + * @details This macro enable specified UART interrupt. + */ +#define UART_DISABLE_INT(uart, u32eIntSel) ((uart)->INTEN &= ~ (u32eIntSel)) + + +/** + * @brief Get specified interrupt flag/status + * + * @param[in] uart The pointer of the specified UART module + * @param[in] u32eIntTypeFlag Interrupt Type Flag, should be + * - \ref UART_INTSTS_ABRINT_Msk : Auto-baud Rate Interrupt Indicator + * - \ref UART_INTSTS_HWBUFEINT_Msk : PDMA Mode Buffer Error Interrupt Indicator + * - \ref UART_INTSTS_HWTOINT_Msk : PDMA Mode Rx Time-out Interrupt Indicator + * - \ref UART_INTSTS_HWMODINT_Msk : PDMA Mode MODEM Status Interrupt Indicator + * - \ref UART_INTSTS_HWRLSINT_Msk : PDMA Mode Receive Line Status Interrupt Indicator + * - \ref UART_INTSTS_SWBEINT_Msk : Single-wire Bit Error Detect Interrupt Indicator + * - \ref UART_INTSTS_HWBUFEIF_Msk : PDMA Mode Buffer Error Interrupt Flag + * - \ref UART_INTSTS_HWTOIF_Msk : PDMA Mode Time-out Interrupt Flag + * - \ref UART_INTSTS_HWMODIF_Msk : PDMA Mode MODEM Status Interrupt Flag + * - \ref UART_INTSTS_HWRLSIF_Msk : PDMA Mode Receive Line Status Flag + * - \ref UART_INTSTS_SWBEIF_Msk : Single-wire Bit Error Detect Interrupt Flag + * - \ref UART_INTSTS_TXENDINT_Msk : Transmitter Empty Interrupt Indicator + * - \ref UART_INTSTS_LININT_Msk : LIN Bus Interrupt Indicator + * - \ref UART_INTSTS_WKINT_Msk : Wake-up Interrupt Indicator + * - \ref UART_INTSTS_BUFERRINT_Msk : Buffer Error Interrupt Indicator + * - \ref UART_INTSTS_RXTOINT_Msk : Rx Time-out Interrupt Indicator + * - \ref UART_INTSTS_MODEMINT_Msk : Modem Status Interrupt Indicator + * - \ref UART_INTSTS_RLSINT_Msk : Receive Line Status Interrupt Indicator + * - \ref UART_INTSTS_THREINT_Msk : Transmit Holding Register Empty Interrupt Indicator + * - \ref UART_INTSTS_RDAINT_Msk : Receive Data Available Interrupt Indicator + * - \ref UART_INTSTS_TXENDIF_Msk : Transmitter Empty Interrupt Flag + * - \ref UART_INTSTS_LINIF_Msk : LIN Bus Interrupt Flag + * - \ref UART_INTSTS_WKIF_Msk : Wake-up Interrupt Flag + * - \ref UART_INTSTS_BUFERRIF_Msk : Buffer Error Interrupt Flag + * - \ref UART_INTSTS_RXTOIF_Msk : Rx Time-out Interrupt Flag + * - \ref UART_INTSTS_MODEMIF_Msk : MODEM Status Interrupt Flag + * - \ref UART_INTSTS_RLSIF_Msk : Receive Line Status Interrupt Flag + * - \ref UART_INTSTS_THREIF_Msk : Transmit Holding Register Empty Interrupt Flag + * - \ref UART_INTSTS_RDAIF_Msk : Receive Data Available Interrupt Flag + * + * @retval 0 The specified interrupt is not happened. + * 1 The specified interrupt is happened. + * + * @details This macro get specified interrupt flag or interrupt indicator status. + */ +#define UART_GET_INT_FLAG(uart,u32eIntTypeFlag) (((uart)->INTSTS & (u32eIntTypeFlag))?1:0) + +/*---------------------------------------------------------------------------------------------------------*/ +/* static inline functions */ +/*---------------------------------------------------------------------------------------------------------*/ +/* Declare these inline functions here to avoid MISRA C 2004 rule 8.1 error */ +static __INLINE void UART_CLEAR_RTS(UART_T* uart); +static __INLINE void UART_SET_RTS(UART_T* uart); + + +/** + * @brief Set RTS pin to low + * + * @param[in] uart The pointer of the specified UART module + * + * @return None + * + * @details This macro set RTS pin to low. + */ +__STATIC_INLINE void UART_CLEAR_RTS(UART_T* uart) +{ + uart->MODEM |= UART_MODEM_RTSACTLV_Msk; + uart->MODEM &= ~UART_MODEM_RTS_Msk; +} + + +/** + * @brief Set RTS pin to high + * + * @param[in] uart The pointer of the specified UART module + * + * @return None + * + * @details This macro set RTS pin to high. + */ +__STATIC_INLINE void UART_SET_RTS(UART_T* uart) +{ + uart->MODEM |= UART_MODEM_RTSACTLV_Msk | UART_MODEM_RTS_Msk; +} + + +/** + * @brief Clear RS-485 Address Byte Detection Flag + * + * @param[in] uart The pointer of the specified UART module + * + * @return None + * + * @details This macro clear RS-485 address byte detection flag. + */ +#define UART_RS485_CLEAR_ADDR_FLAG(uart) ((uart)->FIFOSTS = UART_FIFOSTS_ADDRDETF_Msk) + + +/** + * @brief Get RS-485 Address Byte Detection Flag + * + * @param[in] uart The pointer of the specified UART module + * + * @retval 0 Receiver detects a data that is not an address bit. + * @retval 1 Receiver detects a data that is an address bit. + * + * @details This macro get RS-485 address byte detection flag. + */ +#define UART_RS485_GET_ADDR_FLAG(uart) (((uart)->FIFOSTS & UART_FIFOSTS_ADDRDETF_Msk) >> UART_FIFOSTS_ADDRDETF_Pos) + + +/** + * @brief Enable specified UART PDMA function + * + * @param[in] uart The pointer of the specified UART module + * @param[in] u32FuncSel Combination of following functions + * - \ref UART_INTEN_TXPDMAEN_Msk + * - \ref UART_INTEN_RXPDMAEN_Msk + * + * @return None + * + * @details This macro enable specified UART PDMA function. + */ +#define UART_PDMA_ENABLE(uart, u32FuncSel) ((uart)->INTEN |= (u32FuncSel)) + + +/** + * @brief Disable specified UART PDMA function + * + * @param[in] uart The pointer of the specified UART module + * @param[in] u32FuncSel Combination of following functions + * - \ref UART_INTEN_TXPDMAEN_Msk + * - \ref UART_INTEN_RXPDMAEN_Msk + * + * @return None + * + * @details This macro disable specified UART PDMA function. + */ +#define UART_PDMA_DISABLE(uart, u32FuncSel) ((uart)->INTEN &= ~(u32FuncSel)) + + +void UART_ClearIntFlag(UART_T* uart, uint32_t u32InterruptFlag); +void UART_Close(UART_T* uart); +void UART_DisableFlowCtrl(UART_T* uart); +void UART_DisableInt(UART_T* uart, uint32_t u32InterruptFlag); +void UART_EnableFlowCtrl(UART_T* uart); +void UART_EnableInt(UART_T* uart, uint32_t u32InterruptFlag); +void UART_Open(UART_T* uart, uint32_t u32baudrate); +uint32_t UART_Read(UART_T* uart, uint8_t pu8RxBuf[], uint32_t u32ReadBytes); +void UART_SetLineConfig(UART_T* uart, uint32_t u32baudrate, uint32_t u32data_width, uint32_t u32parity, uint32_t u32stop_bits); +void UART_SetTimeoutCnt(UART_T* uart, uint32_t u32TOC); +void UART_SelectIrDAMode(UART_T* uart, uint32_t u32Buadrate, uint32_t u32Direction); +void UART_SelectRS485Mode(UART_T* uart, uint32_t u32Mode, uint32_t u32Addr); +void UART_SelectLINMode(UART_T* uart, uint32_t u32Mode, uint32_t u32BreakLength); +uint32_t UART_Write(UART_T* uart, uint8_t pu8TxBuf[], uint32_t u32WriteBytes); +void UART_SelectSingleWireMode(UART_T *uart); + + +/**@}*/ /* end of group UART_EXPORTED_FUNCTIONS */ + +/**@}*/ /* end of group UART_Driver */ + +/**@}*/ /* end of group Standard_Driver */ + +#ifdef __cplusplus +} +#endif + +#endif /* __NU_UART_H__ */ diff --git a/Ubiquitous/XiZi/board/nuvoton-m2354/third_party_driver/include/Drivers/nu_usbd.h b/Ubiquitous/XiZi/board/nuvoton-m2354/third_party_driver/include/Drivers/nu_usbd.h new file mode 100644 index 0000000..d0a7c0f --- /dev/null +++ b/Ubiquitous/XiZi/board/nuvoton-m2354/third_party_driver/include/Drivers/nu_usbd.h @@ -0,0 +1,796 @@ +/****************************************************************************** + * @file nu_usbd.h + * @version V3.00 + * @brief M2354 series USBD driver header file + * + * @copyright SPDX-License-Identifier: Apache-2.0 + * @copyright Copyright (C) 2020 Nuvoton Technology Corp. All rights reserved. + ******************************************************************************/ +#ifndef __NU_USBD_H__ +#define __NU_USBD_H__ + +#define SUPPORT_LPM // define to support LPM + +#ifdef __cplusplus +extern "C" +{ +#endif + + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup USBD_Driver USBD Driver + @{ +*/ + +/** @addtogroup USBD_EXPORTED_STRUCTS USBD Exported Structs + @{ +*/ + +typedef struct s_usbd_info +{ + uint8_t *gu8DevDesc; /*!< Pointer for USB Device Descriptor */ + uint8_t *gu8ConfigDesc; /*!< Pointer for USB Configuration Descriptor */ + uint8_t **gu8StringDesc; /*!< Pointer for USB String Descriptor pointers */ + uint8_t **gu8HidReportDesc; /*!< Pointer for USB HID Report Descriptor */ + uint8_t *gu8BosDesc; /*!< Pointer for USB BOS Descriptor */ + uint32_t *gu32HidReportSize; /*!< Pointer for HID Report descriptor Size */ + uint32_t *gu32ConfigHidDescIdx; /*!< Pointer for HID Descriptor start index */ + +} S_USBD_INFO_T; /*!< Device description structure */ + +extern const S_USBD_INFO_T gsInfo; + +/**@}*/ /* end of group USBD_EXPORTED_STRUCTS */ + + +/** @addtogroup USBD_EXPORTED_CONSTANTS USBD Exported Constants + @{ +*/ + +#define USBD_BUF_BASE (uint32_t)(((__PC() & NS_OFFSET) == NS_OFFSET)? (USBD_BASE+NS_OFFSET+0x100UL):(USBD_BASE+0x100UL)) /*!< USBD buffer base address */ +#define USBD_MAX_EP 12UL /*!< Total EP number */ + +#define EP0 0UL /*!< Endpoint 0 */ +#define EP1 1UL /*!< Endpoint 1 */ +#define EP2 2UL /*!< Endpoint 2 */ +#define EP3 3UL /*!< Endpoint 3 */ +#define EP4 4UL /*!< Endpoint 4 */ +#define EP5 5UL /*!< Endpoint 5 */ +#define EP6 6UL /*!< Endpoint 6 */ +#define EP7 7UL /*!< Endpoint 7 */ +#define EP8 8UL /*!< Endpoint 8 */ +#define EP9 9UL /*!< Endpoint 9 */ +#define EP10 10UL /*!< Endpoint 10 */ +#define EP11 11UL /*!< Endpoint 11 */ + +/** @cond HIDDEN_SYMBOLS */ +/* USB Request Type */ +#define REQ_STANDARD 0x00UL +#define REQ_CLASS 0x20UL +#define REQ_VENDOR 0x40UL + +/* USB Standard Request */ +#define GET_STATUS 0x00UL +#define CLEAR_FEATURE 0x01UL +#define SET_FEATURE 0x03UL +#define SET_ADDRESS 0x05UL +#define GET_DESCRIPTOR 0x06UL +#define SET_DESCRIPTOR 0x07UL +#define GET_CONFIGURATION 0x08UL +#define SET_CONFIGURATION 0x09UL +#define GET_INTERFACE 0x0AUL +#define SET_INTERFACE 0x0BUL +#define SYNC_FRAME 0x0CUL + +/* USB Descriptor Type */ +#define DESC_DEVICE 0x01UL +#define DESC_CONFIG 0x02UL +#define DESC_STRING 0x03UL +#define DESC_INTERFACE 0x04UL +#define DESC_ENDPOINT 0x05UL +#define DESC_QUALIFIER 0x06UL +#define DESC_OTHERSPEED 0x07UL +#define DESC_IFPOWER 0x08UL +#define DESC_OTG 0x09UL +#define DESC_BOS 0x0FUL +#define DESC_CAPABILITY 0x10UL + +/* USB Device Capability Type */ +#define CAP_WIRELESS 0x01UL +#define CAP_USB20_EXT 0x02UL + +/*! b, then return a. Otherwise, return b. + */ +#define USBD_Maximum(a,b) ((a)>(b) ? (a) : (b)) + +/** + * @brief Compare two input numbers and return minimum one + * + * @param[in] a First number to be compared + * @param[in] b Second number to be compared + * + * @return Minimum value between a and b + * + * @details If a < b, then return a. Otherwise, return b. + */ +#define USBD_Minimum(a,b) ((a)<(b) ? (a) : (b)) + +/** + * @brief Enable USB + * + * @param None + * + * @return None + * + * @details To set USB ATTR control register to enable USB and PHY. + * + */ +#define USBD_ENABLE_USB() (((__PC() & NS_OFFSET) == NS_OFFSET)? ((uint32_t)(USBD_NS->ATTR |= 0x7D0)):((uint32_t)(USBD->ATTR |= 0x7D0))) + +/** + * @brief Disable USB + * + * @param None + * + * @return None + * + * @details To set USB ATTR control register to disable USB. + * + */ +#define USBD_DISABLE_USB() (((__PC() & NS_OFFSET) == NS_OFFSET)? ((uint32_t)(USBD_NS->ATTR &= ~USBD_USB_EN)):((uint32_t)(USBD->ATTR &= ~USBD_USB_EN))) + +/** + * @brief Enable USB PHY + * + * @param None + * + * @return None + * + * @details To set USB ATTR control register to enable USB PHY. + * + */ +#define USBD_ENABLE_PHY() (((__PC() & NS_OFFSET) == NS_OFFSET)? ((uint32_t)(USBD_NS->ATTR |= USBD_PHY_EN)):((uint32_t)(USBD->ATTR |= USBD_PHY_EN))) + +/** + * @brief Disable USB PHY + * + * @param None + * + * @return None + * + * @details To set USB ATTR control register to disable USB PHY. + * + */ +#define USBD_DISABLE_PHY() (((__PC() & NS_OFFSET) == NS_OFFSET)? ((uint32_t)(USBD_NS->ATTR &= ~USBD_PHY_EN)):((uint32_t)(USBD->ATTR &= ~USBD_PHY_EN))) + +/** + * @brief Enable SE0. Force USB PHY transceiver to drive SE0. + * + * @param None + * + * @return None + * + * @details Set DRVSE0 bit of USB_DRVSE0 register to enable software-disconnect function. Force USB PHY transceiver to drive SE0 to bus. + * + */ +#define USBD_SET_SE0() (((__PC() & NS_OFFSET) == NS_OFFSET)? ((uint32_t)(USBD_NS->SE0 |= USBD_DRVSE0)):((uint32_t)(USBD->SE0 |= USBD_DRVSE0))) + +/** + * @brief Disable SE0 + * + * @param None + * + * @return None + * + * @details Clear DRVSE0 bit of USB_DRVSE0 register to disable software-disconnect function. + * + */ +#define USBD_CLR_SE0() (((__PC() & NS_OFFSET) == NS_OFFSET)? ((uint32_t)(USBD_NS->SE0 &= ~USBD_DRVSE0)):((uint32_t)(USBD->SE0 &= ~USBD_DRVSE0))) + +/** + * @brief Set USB device address + * + * @param[in] addr The USB device address. + * + * @return None + * + * @details Write USB device address to USB_FADDR register. + * + */ +#define USBD_SET_ADDR(addr) (((__PC() & NS_OFFSET) == NS_OFFSET)? (USBD_NS->FADDR = (addr)):(USBD->FADDR = (addr))) + +/** + * @brief Get USB device address + * + * @param None + * + * @return USB device address + * + * @details Read USB_FADDR register to get USB device address. + * + */ +#define USBD_GET_ADDR() (((__PC() & NS_OFFSET) == NS_OFFSET)? ((uint32_t)(USBD_NS->FADDR)):((uint32_t)(USBD->FADDR))) + +/** + * @brief Enable USB interrupt function + * + * @param[in] intr The combination of the specified interrupt enable bits. + * Each bit corresponds to a interrupt enable bit. + * This parameter decides which interrupts will be enabled. + * (USBD_INT_WAKEUP, USBD_INT_FLDET, USBD_INT_USB, USBD_INT_BUS) + * + * @return None + * + * @details Enable USB related interrupt functions specified by intr parameter. + * + */ +#define USBD_ENABLE_INT(intr) (((__PC() & NS_OFFSET) == NS_OFFSET)? (USBD_NS->INTEN |= (intr)):(USBD->INTEN |= (intr))) + +/** + * @brief Get interrupt status + * + * @param None + * + * @return The value of USB_INTSTS register + * + * @details Return all interrupt flags of USB_INTSTS register. + * + */ +#define USBD_GET_INT_FLAG() (((__PC() & NS_OFFSET) == NS_OFFSET)? ((uint32_t)(USBD_NS->INTSTS)):((uint32_t)(USBD->INTSTS))) + +/** + * @brief Clear USB interrupt flag + * + * @param[in] flag The combination of the specified interrupt flags. + * Each bit corresponds to a interrupt source. + * This parameter decides which interrupt flags will be cleared. + * (USBD_INTSTS_WAKEUP, USBD_INTSTS_FLDET, USBD_INTSTS_BUS, USBD_INTSTS_USB) + * + * @return None + * + * @details Clear USB related interrupt flags specified by flag parameter. + * + */ +#define USBD_CLR_INT_FLAG(flag) (((__PC() & NS_OFFSET) == NS_OFFSET)? (USBD_NS->INTSTS = (flag)):(USBD->INTSTS = (flag))) + +/** + * @brief Get endpoint status + * + * @param None + * + * @return The value of USB_EPSTS register. + * + * @details Return all endpoint status. + * + */ +#define USBD_GET_EP_FLAG() (((__PC() & NS_OFFSET) == NS_OFFSET)? ((uint32_t)(USBD_NS->EPSTS)):((uint32_t)(USBD->EPSTS))) + +/** + * @brief Get USB bus state + * + * @param None + * + * @return The value of USB_ATTR[13:12] and USB_ATTR[3:0]. + * Bit 0 indicates USB bus reset status. + * Bit 1 indicates USB bus suspend status. + * Bit 2 indicates USB bus resume status. + * Bit 3 indicates USB bus time-out status. + * Bit 12 indicates USB bus LPM L1 suspend status. + * Bit 13 indicates USB bus LPM L1 resume status. + * + * @details Return USB_ATTR[13:12] and USB_ATTR[3:0] for USB bus events. + * + */ +#define USBD_GET_BUS_STATE() (((__PC() & NS_OFFSET) == NS_OFFSET)? ((uint32_t)(USBD_NS->ATTR & 0x300F)):((uint32_t)(USBD->ATTR & 0x300F))) + +/** + * @brief Check cable connection state + * + * @param None + * + * @retval 0 USB cable is not attached. + * @retval 1 USB cable is attached. + * + * @details Check the connection state by FLDET bit of USB_FLDET register. + * + */ +#define USBD_IS_ATTACHED() (((__PC() & NS_OFFSET) == NS_OFFSET)? ((uint32_t)(USBD_NS->VBUSDET & USBD_VBUSDET_VBUSDET_Msk)):((uint32_t)(USBD->VBUSDET & USBD_VBUSDET_VBUSDET_Msk))) + +/** + * @brief Stop USB transaction of the specified endpoint ID + * + * @param[in] ep The USB endpoint ID. M2354 Series supports 12 hardware endpoint ID. This parameter could be 0 ~ 11. + * + * @return None + * + * @details Write 1 to CLRRDY bit of USB_CFGPx register to stop USB transaction of the specified endpoint ID. + * + */ +#define USBD_STOP_TRANSACTION(ep) (((__PC() & NS_OFFSET) == NS_OFFSET)? (*((__IO uint32_t *) ((uint32_t)&USBD_NS->EP[0].CFGP + (uint32_t)((ep) << 4))) |= USBD_CFGP_CLRRDY_Msk):(*((__IO uint32_t *) ((uint32_t)&USBD->EP[0].CFGP + (uint32_t)((ep) << 4))) |= USBD_CFGP_CLRRDY_Msk)) + +/** + * @brief Set USB DATA1 PID for the specified endpoint ID + * + * @param[in] ep The USB endpoint ID. M2354 Series supports 12 hardware endpoint ID. This parameter could be 0 ~ 11. + * + * @return None + * + * @details Set DSQ_SYNC bit of USB_CFGx register to specify the DATA1 PID for the following IN token transaction. + * Base on this setting, hardware will toggle PID between DATA0 and DATA1 automatically for IN token transactions in single buffer mode. + * + */ +#define USBD_SET_DATA1(ep) (((__PC() & NS_OFFSET) == NS_OFFSET)? (*((__IO uint32_t *) ((uint32_t)&USBD_NS->EP[0].CFG + (uint32_t)((ep) << 4))) |= USBD_CFG_DSQSYNC_Msk):(*((__IO uint32_t *) ((uint32_t)&USBD->EP[0].CFG + (uint32_t)((ep) << 4))) |= USBD_CFG_DSQSYNC_Msk)) + +/** + * @brief Set USB DATA0 PID for the specified endpoint ID + * + * @param[in] ep The USB endpoint ID. M2354 Series supports 12 hardware endpoint ID. This parameter could be 0 ~ 11. + * + * @return None + * + * @details Clear DSQ_SYNC bit of USB_CFGx register to specify the DATA0 PID for the following IN token transaction. + * Base on this setting, hardware will toggle PID between DATA0 and DATA1 automatically for IN token transactions in single buffer mode. + * + */ +#define USBD_SET_DATA0(ep) (((__PC() & NS_OFFSET) == NS_OFFSET)? (*((__IO uint32_t *) ((uint32_t)&USBD_NS->EP[0].CFG + (uint32_t)((ep) << 4))) &= (~USBD_CFG_DSQSYNC_Msk)):(*((__IO uint32_t *) ((uint32_t)&USBD->EP[0].CFG + (uint32_t)((ep) << 4))) &= (~USBD_CFG_DSQSYNC_Msk))) + +/** + * @brief Set USB payload size (IN data) + * + * @param[in] ep The USB endpoint ID. M2354 Series supports 12 hardware endpoint ID. This parameter could be 0 ~ 11. + * + * @param[in] size The transfer length. + * + * @return None + * + * @details This macro will write the transfer length to USB_MXPLDx register for IN data transaction. + * + */ +#define USBD_SET_PAYLOAD_LEN(ep, size) (((__PC() & NS_OFFSET) == NS_OFFSET)? (*((__IO uint32_t *) ((uint32_t)&USBD_NS->EP[0].MXPLD + (uint32_t)((ep) << 4))) = (size)):(*((__IO uint32_t *) ((uint32_t)&USBD->EP[0].MXPLD + (uint32_t)((ep) << 4))) = (size))) + +/** + * @brief Get USB payload size (OUT data) + * + * @param[in] ep The USB endpoint ID. M2354 Series supports 12 hardware endpoint ID. This parameter could be 0 ~ 11. + * + * @return The value of USB_MXPLDx register. + * + * @details Get the data length of OUT data transaction by reading USB_MXPLDx register. + * + */ +#define USBD_GET_PAYLOAD_LEN(ep) (((__PC() & NS_OFFSET) == NS_OFFSET)? ((uint32_t)*((__IO uint32_t *) ((uint32_t)&USBD_NS->EP[0].MXPLD + (uint32_t)((ep) << 4)))):((uint32_t)*((__IO uint32_t *) ((uint32_t)&USBD->EP[0].MXPLD + (uint32_t)((ep) << 4))))) + +/** + * @brief Configure endpoint + * + * @param[in] ep The USB endpoint ID. M2354 Series supports 12 hardware endpoint ID. This parameter could be 0 ~ 11. + * + * @param[in] config The USB configuration. + * + * @return None + * + * @details This macro will write config parameter to USB_CFGx register of specified endpoint ID. + * + */ +#define USBD_CONFIG_EP(ep, config) (((__PC() & NS_OFFSET) == NS_OFFSET)? (*((__IO uint32_t *) ((uint32_t)&USBD_NS->EP[0].CFG + (uint32_t)((ep) << 4))) = (config)):(*((__IO uint32_t *) ((uint32_t)&USBD->EP[0].CFG + (uint32_t)((ep) << 4))) = (config))) + +/** + * @brief Set USB endpoint buffer + * + * @param[in] ep The USB endpoint ID. M2354 Series supports 12 hardware endpoint ID. This parameter could be 0 ~ 11. + * + * @param[in] offset The SRAM offset. + * + * @return None + * + * @details This macro will set the SRAM offset for the specified endpoint ID. + * + */ +#define USBD_SET_EP_BUF_ADDR(ep, offset) (((__PC() & NS_OFFSET) == NS_OFFSET)? (*((__IO uint32_t *) ((uint32_t)&USBD_NS->EP[0].BUFSEG + (uint32_t)((ep) << 4))) = (offset)):(*((__IO uint32_t *) ((uint32_t)&USBD->EP[0].BUFSEG + (uint32_t)((ep) << 4))) = (offset))) + +/** + * @brief Get the offset of the specified USB endpoint buffer + * + * @param[in] ep The USB endpoint ID. M2354 Series supports 12 hardware endpoint ID. This parameter could be 0 ~ 11. + * + * @return The offset of the specified endpoint buffer. + * + * @details This macro will return the SRAM offset of the specified endpoint ID. + * + */ +#define USBD_GET_EP_BUF_ADDR(ep) (((__PC() & NS_OFFSET) == NS_OFFSET)? ((uint32_t)*((__IO uint32_t *) ((uint32_t)&USBD_NS->EP[0].BUFSEG + (uint32_t)((ep) << 4)))):((uint32_t)*((__IO uint32_t *) ((uint32_t)&USBD->EP[0].BUFSEG + (uint32_t)((ep) << 4))))) + +/** + * @brief Set USB endpoint stall state + * + * @param[in] ep The USB endpoint ID. M2354 Series supports 12 hardware endpoint ID. This parameter could be 0 ~ 11. + * + * @return None + * + * @details Set USB endpoint stall state for the specified endpoint ID. Endpoint will respond STALL token automatically. + * + */ +#define USBD_SET_EP_STALL(ep) (((__PC() & NS_OFFSET) == NS_OFFSET)? (*((__IO uint32_t *) ((uint32_t)&USBD_NS->EP[0].CFGP + (uint32_t)((ep) << 4))) |= USBD_CFGP_SSTALL_Msk):(*((__IO uint32_t *) ((uint32_t)&USBD->EP[0].CFGP + (uint32_t)((ep) << 4))) |= USBD_CFGP_SSTALL_Msk)) + +/** + * @brief Clear USB endpoint stall state + * + * @param[in] ep The USB endpoint ID. M2354 Series supports 12 hardware endpoint ID. This parameter could be 0 ~ 11. + * + * @return None + * + * @details Clear USB endpoint stall state for the specified endpoint ID. Endpoint will respond ACK/NAK token. + * + */ +#define USBD_CLR_EP_STALL(ep) (((__PC() & NS_OFFSET) == NS_OFFSET)? (*((__IO uint32_t *) ((uint32_t)&USBD_NS->EP[0].CFGP + (uint32_t)((ep) << 4))) &= ~USBD_CFGP_SSTALL_Msk):(*((__IO uint32_t *) ((uint32_t)&USBD->EP[0].CFGP + (uint32_t)((ep) << 4))) &= ~USBD_CFGP_SSTALL_Msk)) + +/** + * @brief Get USB endpoint stall state + * + * @param[in] ep The USB endpoint ID. M2354 Series supports 12 hardware endpoint ID. This parameter could be 0 ~ 11. + * + * @retval 0 USB endpoint is not stalled. + * @retval Others USB endpoint is stalled. + * + * @details Get USB endpoint stall state of the specified endpoint ID. + * + */ +#define USBD_GET_EP_STALL(ep) (((__PC() & NS_OFFSET) == NS_OFFSET)? (*((__IO uint32_t *) ((uint32_t)&USBD_NS->EP[0].CFGP + (uint32_t)((ep) << 4))) & USBD_CFGP_SSTALL_Msk):(*((__IO uint32_t *) ((uint32_t)&USBD->EP[0].CFGP + (uint32_t)((ep) << 4))) & USBD_CFGP_SSTALL_Msk)) + +/** + * @brief Set USB double buffer mode for the specified endpoint ID + * + * @param[in] ep The USB endpoint ID. M2354 Series supports 12 hardware endpoint ID. This parameter could be 0 ~ 11. + * + * @return None + * + * @details Set DBEN bit of USB_CFGx register to enable the double buffer mode of the specified endpoint ID. + * + */ +#define USBD_SET_DB_MODE(ep) (((__PC() & NS_OFFSET) == NS_OFFSET)? (*((__IO uint32_t *) ((uint32_t)&USBD_NS->EP[0].CFG + (uint32_t)((ep) << 4))) |= USBD_CFG_DBEN_Msk):(*((__IO uint32_t *) ((uint32_t)&USBD->EP[0].CFG + (uint32_t)((ep) << 4))) |= USBD_CFG_DBEN_Msk)) + +/** + * @brief Set USB single buffer mode for the specified endpoint ID + * + * @param[in] ep The USB endpoint ID. M2354 Series supports 12 hardware endpoint ID. This parameter could be 0 ~ 11. + * + * @return None + * + * @details Clear DBEN bit of USB_CFGx register to enable the single buffer mode of the specified endpoint ID. + * + */ +#define USBD_SET_SB_MODE(ep) (((__PC() & NS_OFFSET) == NS_OFFSET)? (*((__IO uint32_t *) ((uint32_t)&USBD_NS->EP[0].CFG + (uint32_t)((ep) << 4))) &= (~USBD_CFG_DBEN_Msk)):(*((__IO uint32_t *) ((uint32_t)&USBD->EP[0].CFG + (uint32_t)((ep) << 4))) &= (~USBD_CFG_DBEN_Msk))) + +/** + * @brief Get the buffer mode of the specified USB endpoint buffer + * + * @param[in] ep The USB endpoint ID. M2354 Series supports 12 hardware endpoint ID. This parameter could be 0 ~ 11. + * + * @retval 0 USB is single buffer mode. + * @retval 1 USB is double buffer mode. + * + * @details This macro will return the buffer mode of the specified endpoint ID. + * + */ +#define USBD_IS_DB_MODE(ep) (((__PC() & NS_OFFSET) == NS_OFFSET)? (*((__IO uint32_t *) ((uint32_t)&USBD_NS->EP[0].CFG + (uint32_t)((ep) << 4))) & USBD_CFG_DBEN_Msk):(*((__IO uint32_t *) ((uint32_t)&USBD->EP[0].CFG + (uint32_t)((ep) << 4))) & USBD_CFG_DBEN_Msk)) + +/** + * @brief Set to active in USB double buffer mode for the specified endpoint ID + * + * @param[in] ep The USB endpoint ID. M2354 Series supports 12 hardware endpoint ID. This parameter could be 0 ~ 11. + * + * @return None + * + * @details Set DBTGACTIVE bit of USB_CFGx register for toggle active in the double buffer mode of the specified endpoint ID. + * + */ +#define USBD_SET_DB_ACTIVE(ep) (((__PC() & NS_OFFSET) == NS_OFFSET)? (*((__IO uint32_t *) ((uint32_t)&USBD_NS->EP[0].CFG + (uint32_t)((ep) << 4))) |= USBD_CFG_DBTGACTIVE_Msk):(*((__IO uint32_t *) ((uint32_t)&USBD->EP[0].CFG + (uint32_t)((ep) << 4))) |= USBD_CFG_DBTGACTIVE_Msk)) + +/** + * @brief Set to inactive in USB double buffer mode for the specified endpoint ID + * + * @param[in] ep The USB endpoint ID. M2354 Series supports 12 hardware endpoint ID. This parameter could be 0 ~ 11. + * + * @return None + * + * @details Clear DBTGACTIVE bit of USB_CFGx register for toggle inactive in the double buffer mode of the specified endpoint ID. + * + */ +#define USBD_SET_DB_INACTIVE(ep) (((__PC() & NS_OFFSET) == NS_OFFSET)? (*((__IO uint32_t *) ((uint32_t)&USBD_NS->EP[0].CFG + (uint32_t)((ep) << 4))) &= (~USBD_CFG_DBTGACTIVE_Msk)):(*((__IO uint32_t *) ((uint32_t)&USBD->EP[0].CFG + (uint32_t)((ep) << 4))) &= (~USBD_CFG_DBTGACTIVE_Msk))) + +/** + * @brief To support byte access between USB SRAM and system SRAM + * + * @param[in] dest Destination pointer. + * + * @param[in] src Source pointer. + * + * @param[in] size Byte count. + * + * @return None + * + * @details This function will copy the number of data specified by size and src parameters to the address specified by dest parameter. + * + */ +__STATIC_INLINE void USBD_MemCopy(uint8_t dest[], uint8_t src[], uint32_t size) +{ + uint32_t volatile i = 0UL; + + while(size--) + { + dest[i] = src[i]; + i++; + } +} + +/** + * @brief Set USB endpoint stall state + * + * @param[in] epnum USB endpoint number + * + * @return None + * + * @details Set USB endpoint stall state. Endpoint will respond STALL token automatically. + * + */ +__STATIC_INLINE void USBD_SetStall(uint8_t epnum) +{ + uint32_t u32CfgAddr; + uint32_t u32Cfg; + uint32_t i; + USBD_T *pUSBD; + + if((__PC() & NS_OFFSET) == NS_OFFSET) + { + pUSBD = USBD_NS; + } + else + { + pUSBD = USBD; + } + + for(i = 0UL; i < USBD_MAX_EP; i++) + { + u32CfgAddr = (uint32_t)(i << 4) + (uint32_t)&pUSBD->EP[0].CFG; /* USBD_CFG0 */ + u32Cfg = *((__IO uint32_t *)(u32CfgAddr)); + + if((u32Cfg & 0xFUL) == epnum) + { + u32CfgAddr = (uint32_t)(i << 4) + (uint32_t)&pUSBD->EP[0].CFGP; /* USBD_CFGP0 */ + u32Cfg = *((__IO uint32_t *)(u32CfgAddr)); + + *((__IO uint32_t *)(u32CfgAddr)) = (u32Cfg | USBD_CFGP_SSTALL); + break; + } + } +} + +/** + * @brief Clear USB endpoint stall state + * + * @param[in] epnum USB endpoint number + * + * @return None + * + * @details Clear USB endpoint stall state. Endpoint will respond ACK/NAK token. + */ +__STATIC_INLINE void USBD_ClearStall(uint8_t epnum) +{ + uint32_t u32CfgAddr; + uint32_t u32Cfg; + uint32_t i; + USBD_T *pUSBD; + + if((__PC() & NS_OFFSET) == NS_OFFSET) + { + pUSBD = USBD_NS; + } + else + { + pUSBD = USBD; + } + + for(i = 0UL; i < USBD_MAX_EP; i++) + { + u32CfgAddr = (uint32_t)(i << 4) + (uint32_t)&pUSBD->EP[0].CFG; /* USBD_CFG0 */ + u32Cfg = *((__IO uint32_t *)(u32CfgAddr)); + + if((u32Cfg & 0xFUL) == epnum) + { + u32CfgAddr = (uint32_t)(i << 4) + (uint32_t)&pUSBD->EP[0].CFGP; /* USBD_CFGP0 */ + u32Cfg = *((__IO uint32_t *)(u32CfgAddr)); + + *((__IO uint32_t *)(u32CfgAddr)) = (u32Cfg & ~USBD_CFGP_SSTALL); + break; + } + } +} + +/** + * @brief Get USB endpoint stall state + * + * @param[in] epnum USB endpoint number + * + * @retval 0 USB endpoint is not stalled. + * @retval Others USB endpoint is stalled. + * + * @details Get USB endpoint stall state. + * + */ +__STATIC_INLINE uint32_t USBD_GetStall(uint8_t epnum) +{ + uint32_t u32CfgAddr = 0UL; + uint32_t u32Cfg; + uint32_t i; + USBD_T *pUSBD; + + if((__PC() & NS_OFFSET) == NS_OFFSET) + { + pUSBD = USBD_NS; + } + else + { + pUSBD = USBD; + } + + for(i = 0UL; i < USBD_MAX_EP; i++) + { + u32CfgAddr = (uint32_t)(i << 4) + (uint32_t)&pUSBD->EP[0].CFG; /* USBD_CFG0 */ + u32Cfg = *((__IO uint32_t *)(u32CfgAddr)); + + if((u32Cfg & 0xFUL) == epnum) + { + u32CfgAddr = (uint32_t)(i << 4) + (uint32_t)&pUSBD->EP[0].CFGP; /* USBD_CFGP0 */ + break; + } + } + + return ((*((__IO uint32_t *)(u32CfgAddr))) & USBD_CFGP_SSTALL); +} + +extern uint8_t g_USBD_au8SetupPacket[8]; +extern volatile uint8_t g_USBD_u8RemoteWakeupEn; + +typedef void (*VENDOR_REQ)(void); /*!< Functional pointer type definition for Vendor class */ +typedef void (*CLASS_REQ)(void); /*!< Functional pointer type declaration for USB class request callback handler */ +typedef void (*SET_INTERFACE_REQ)(uint32_t u32AltInterface); /*!< Functional pointer type declaration for USB set interface request callback handler */ +typedef void (*SET_CONFIG_CB)(void); /*!< Functional pointer type declaration for USB set configuration request callback handler */ + +extern const S_USBD_INFO_T *g_USBD_sInfo; + +extern VENDOR_REQ g_USBD_pfnVendorRequest; +extern CLASS_REQ g_USBD_pfnClassRequest; +extern SET_INTERFACE_REQ g_USBD_pfnSetInterface; +extern SET_CONFIG_CB g_USBD_pfnSetConfigCallback; +extern uint32_t g_USBD_u32EpStallLock; + +/*--------------------------------------------------------------------*/ +void USBD_Open(const S_USBD_INFO_T *param, CLASS_REQ pfnClassReq, SET_INTERFACE_REQ pfnSetInterface); +void USBD_Start(void); +void USBD_GetSetupPacket(uint8_t *buf); +void USBD_ProcessSetupPacket(void); +void USBD_GetDescriptor(void); +void USBD_StandardRequest(void); +void USBD_PrepareCtrlIn(uint8_t pu8Buf[], uint32_t u32Size); +void USBD_CtrlIn(void); +void USBD_PrepareCtrlOut(uint8_t *pu8Buf, uint32_t u32Size); +void USBD_CtrlOut(void); +void USBD_SwReset(void); +void USBD_SetVendorRequest(VENDOR_REQ pfnVendorReq); +void USBD_SetConfigCallback(SET_CONFIG_CB pfnSetConfigCallback); +void USBD_LockEpStall(uint32_t u32EpBitmap); + + +/**@}*/ /* end of group USBD_EXPORTED_FUNCTIONS */ + +/**@}*/ /* end of group USBD_Driver */ + +/**@}*/ /* end of group Standard_Driver */ + +#ifdef __cplusplus +} +#endif + +#endif /* __NU_USBD_H__ */ diff --git a/Ubiquitous/XiZi/board/nuvoton-m2354/third_party_driver/include/Drivers/nu_usci_i2c.h b/Ubiquitous/XiZi/board/nuvoton-m2354/third_party_driver/include/Drivers/nu_usci_i2c.h new file mode 100644 index 0000000..e629759 --- /dev/null +++ b/Ubiquitous/XiZi/board/nuvoton-m2354/third_party_driver/include/Drivers/nu_usci_i2c.h @@ -0,0 +1,318 @@ +/**************************************************************************//** + * @file nu_usci_i2c.h + * @version V3.0 + * $Revision: 1 $ + * $Date: 16/07/07 7:50p $ + * @brief M2355 series USCI I2C(UI2C) driver header file + * + * @copyright SPDX-License-Identifier: Apache-2.0 + * @copyright Copyright (C) 2020 Nuvoton Technology Corp. All rights reserved. + ******************************************************************************/ +#ifndef __NU_USCI_I2C_H__ +#define __NU_USCI_I2C_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup USCI_I2C_Driver USCI_I2C Driver + @{ +*/ + +/** @addtogroup USCI_I2C_EXPORTED_CONSTANTS USCI_I2C Exported Constants + @{ +*/ + +/*---------------------------------------------------------------------------------------------------------*/ +/* USCI_I2C master event definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +enum UI2C_MASTER_EVENT +{ + MASTER_SEND_ADDRESS = 10u, /*!< Master send address to Slave */ + MASTER_SEND_H_WR_ADDRESS, /*!< Master send High address to Slave */ + MASTER_SEND_H_RD_ADDRESS, /*!< Master send address to Slave (Read ADDR) */ + MASTER_SEND_L_ADDRESS, /*!< Master send Low address to Slave */ + MASTER_SEND_DATA, /*!< Master Send Data to Slave */ + MASTER_SEND_REPEAT_START, /*!< Master send repeat start to Slave */ + MASTER_READ_DATA, /*!< Master Get Data from Slave */ + MASTER_STOP, /*!< Master send stop to Slave */ + MASTER_SEND_START /*!< Master send start to Slave */ +}; + +/*---------------------------------------------------------------------------------------------------------*/ +/* USCI_I2C slave event definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +enum UI2C_SLAVE_EVENT +{ + SLAVE_ADDRESS_ACK = 100u, /*!< Slave send address ACK */ + SLAVE_H_WR_ADDRESS_ACK, /*!< Slave send High address ACK */ + SLAVE_L_WR_ADDRESS_ACK, /*!< Slave send Low address ACK */ + SLAVE_GET_DATA, /*!< Slave Get Data from Master (Write CMD) */ + SLAVE_SEND_DATA, /*!< Slave Send Data to Master (Read CMD) */ + SLAVE_H_RD_ADDRESS_ACK, /*!< Slave send High address ACK */ + SLAVE_L_RD_ADDRESS_ACK /*!< Slave send Low address ACK */ +}; + +/*---------------------------------------------------------------------------------------------------------*/ +/* USCI_CTL constant definitions. */ +/*---------------------------------------------------------------------------------------------------------*/ +#define UI2C_CTL_PTRG (0x20U) /*!< USCI_CTL setting for I2C control bits. It would set PTRG bit */ +#define UI2C_CTL_STA (0x08U) /*!< USCI_CTL setting for I2C control bits. It would set STA bit */ +#define UI2C_CTL_STO (0x04U) /*!< USCI_CTL setting for I2C control bits. It would set STO bit */ +#define UI2C_CTL_AA (0x02U) /*!< USCI_CTL setting for I2C control bits. It would set AA bit */ + +/*---------------------------------------------------------------------------------------------------------*/ +/* USCI_I2C GCMode constant definitions. */ +/*---------------------------------------------------------------------------------------------------------*/ +#define UI2C_GCMODE_ENABLE (1U) /*!< Enable USCI_I2C GC Mode */ +#define UI2C_GCMODE_DISABLE (0U) /*!< Disable USCI_I2C GC Mode */ + +/*---------------------------------------------------------------------------------------------------------*/ +/* USCI_I2C Wakeup Mode constant definitions. */ +/*---------------------------------------------------------------------------------------------------------*/ +#define UI2C_DATA_TOGGLE_WK (0x0U << UI2C_WKCTL_WKADDREN_Pos) /*!< Wakeup according data toggle */ +#define UI2C_ADDR_MATCH_WK (0x1U << UI2C_WKCTL_WKADDREN_Pos) /*!< Wakeup according address match */ + +/*---------------------------------------------------------------------------------------------------------*/ +/* USCI_I2C interrupt mask definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define UI2C_TO_INT_MASK (0x001U) /*!< Time-out interrupt mask */ +#define UI2C_STAR_INT_MASK (0x002U) /*!< Start condition received interrupt mask */ +#define UI2C_STOR_INT_MASK (0x004U) /*!< Stop condition received interrupt mask */ +#define UI2C_NACK_INT_MASK (0x008U) /*!< Non-acknowledge interrupt mask */ +#define UI2C_ARBLO_INT_MASK (0x010U) /*!< Arbitration lost interrupt mask */ +#define UI2C_ERR_INT_MASK (0x020U) /*!< Error interrupt mask */ +#define UI2C_ACK_INT_MASK (0x040U) /*!< Acknowledge interrupt mask */ + +/**@}*/ /* end of group USCI_I2C_EXPORTED_CONSTANTS */ + + +/** @addtogroup USCI_I2C_EXPORTED_FUNCTIONS USCI_I2C Exported Functions + @{ +*/ + +/** + * @brief This macro sets the USCI_I2C protocol control register at one time + * + * @param[in] ui2c The pointer of the specified USCI_I2C module. + * @param[in] u8Ctrl Set the register value of USCI_I2C control register. + * + * @return None + * + * @details Set UI2C_PROTCTL register to control USCI_I2C bus conditions of START, STOP, PTRG, ACK. + */ +#define UI2C_SET_CONTROL_REG(ui2c, u8Ctrl) ((ui2c)->PROTCTL = ((ui2c)->PROTCTL & ~0x2EU) | (u8Ctrl)) + +/** + * @brief This macro only set START bit to protocol control register of USCI_I2C module. + * + * @param[in] ui2c The pointer of the specified USCI_I2C module. + * + * @return None + * + * @details Set the USCI_I2C bus START condition in UI2C_PROTCTL register. + */ +#define UI2C_START(ui2c) ((ui2c)->PROTCTL = ((ui2c)->PROTCTL & ~UI2C_PROTCTL_PTRG_Msk) | UI2C_PROTCTL_STA_Msk) + +/** + * @brief This macro only set STOP bit to the control register of USCI_I2C module + * + * @param[in] ui2c The pointer of the specified USCI_I2C module. + * + * @return None + * + * @details Set the USCI_I2C bus STOP condition in UI2C_PROTCTL register. + */ +#define UI2C_STOP(ui2c) ((ui2c)->PROTCTL = ((ui2c)->PROTCTL & ~0x2E) | (UI2C_PROTCTL_PTRG_Msk | UI2C_PROTCTL_STO_Msk)) + +/** + * @brief This macro returns the data stored in data register of USCI_I2C module + * + * @param[in] ui2c The pointer of the specified USCI_I2C module. + * + * @return Data + * + * @details Read a byte data value of UI2C_RXDAT register from USCI_I2C bus + */ +#define UI2C_GET_DATA(ui2c) ((ui2c)->RXDAT) + +/** + * @brief This macro writes the data to data register of USCI_I2C module + * + * @param[in] ui2c The pointer of the specified USCI_I2C module. + * @param[in] u8Data The data which will be written to data register of USCI_I2C module. + * + * @return None + * + * @details Write a byte data value of UI2C_TXDAT register, then sends address or data to USCI I2C bus + */ +#define UI2C_SET_DATA(ui2c, u8Data) ((ui2c)->TXDAT = (u8Data)) + +/** + * @brief This macro returns time-out flag + * + * @param[in] ui2c The pointer of the specified USCI_I2C module. + * + * @retval 0 USCI_I2C bus time-out is not happened + * @retval 1 USCI_I2C bus time-out is happened + * + * @details USCI_I2C bus occurs time-out event, the time-out flag will be set. If not occurs time-out event, this bit is cleared. + */ +#define UI2C_GET_TIMEOUT_FLAG(ui2c) (((ui2c)->PROTSTS & UI2C_PROTSTS_TOIF_Msk) == UI2C_PROTSTS_TOIF_Msk ? 1:0) + +/** + * @brief This macro returns wake-up flag + * + * @param[in] ui2c The pointer of the specified USCI_I2C module. + * + * @retval 0 Chip is not woken-up from power-down mode + * @retval 1 Chip is woken-up from power-down mode + * + * @details USCI_I2C controller wake-up flag will be set when USCI_I2C bus occurs wake-up from deep-sleep. + */ +#define UI2C_GET_WAKEUP_FLAG(ui2c) (((ui2c)->WKSTS & UI2C_WKSTS_WKF_Msk) == UI2C_WKSTS_WKF_Msk ? 1:0) + +/** + * @brief This macro is used to clear USCI_I2C wake-up flag + * + * @param[in] ui2c The pointer of the specified USCI_I2C module. + * + * @return None + * + * @details If USCI_I2C wake-up flag is set, use this macro to clear it. + */ +#define UI2C_CLR_WAKEUP_FLAG(ui2c) ((ui2c)->WKSTS = UI2C_WKSTS_WKF_Msk) + +/** + * @brief This macro disables the USCI_I2C 10-bit address mode + * + * @param[in] ui2c The pointer of the specified USCI_I2C module. + * + * @return None + * + * @details The UI2C_I2C is 7-bit address mode, when disable USCI_I2C 10-bit address match function. + */ +#define UI2C_DISABLE_10BIT_ADDR_MODE(ui2c) ((ui2c)->PROTCTL &= ~(UI2C_PROTCTL_ADDR10EN_Msk)) + +/** + * @brief This macro enables the 10-bit address mode + * + * @param[in] ui2c The pointer of the specified USCI_I2C module. + * + * @return None + * + * @details To enable USCI_I2C 10-bit address match function. + */ +#define UI2C_ENABLE_10BIT_ADDR_MODE(ui2c) ((ui2c)->PROTCTL |= UI2C_PROTCTL_ADDR10EN_Msk) + +/** + * @brief This macro gets USCI_I2C protocol interrupt flag or bus status + * + * @param[in] ui2c The pointer of the specified USCI_I2C module. + * + * @return A word data of USCI_I2C_PROTSTS register + * + * @details Read a word data of USCI_I2C PROTSTS register to get USCI_I2C bus Interrupt flags or status. + */ +#define UI2C_GET_PROT_STATUS(ui2c) ((ui2c)->PROTSTS) + +/** + * @brief This macro clears specified protocol interrupt flag + * @param[in] ui2c The pointer of the specified USCI_I2C module. + * @param[in] u32IntTypeFlag Interrupt Type Flag, should be + * - \ref UI2C_PROTSTS_ACKIF_Msk + * - \ref UI2C_PROTSTS_ERRIF_Msk + * - \ref UI2C_PROTSTS_ARBLOIF_Msk + * - \ref UI2C_PROTSTS_NACKIF_Msk + * - \ref UI2C_PROTSTS_STORIF_Msk + * - \ref UI2C_PROTSTS_STARIF_Msk + * - \ref UI2C_PROTSTS_TOIF_Msk + * @return None + * + * @details To clear interrupt flag when USCI_I2C occurs interrupt and set interrupt flag. + */ +#define UI2C_CLR_PROT_INT_FLAG(ui2c,u32IntTypeFlag) ((ui2c)->PROTSTS = (u32IntTypeFlag)) + +/** + * @brief This macro enables specified protocol interrupt + * @param[in] ui2c The pointer of the specified USCI_I2C module. + * @param[in] u32IntSel Interrupt Type, should be + * - \ref UI2C_PROTIEN_ACKIEN_Msk + * - \ref UI2C_PROTIEN_ERRIEN_Msk + * - \ref UI2C_PROTIEN_ARBLOIEN_Msk + * - \ref UI2C_PROTIEN_NACKIEN_Msk + * - \ref UI2C_PROTIEN_STORIEN_Msk + * - \ref UI2C_PROTIEN_STARIEN_Msk + * - \ref UI2C_PROTIEN_TOIEN_Msk + * @return None + * + * @details Set specified USCI_I2C protocol interrupt bits to enable interrupt function. + */ +#define UI2C_ENABLE_PROT_INT(ui2c, u32IntSel) ((ui2c)->PROTIEN |= (u32IntSel)) + +/** + * @brief This macro disables specified protocol interrupt + * @param[in] ui2c The pointer of the specified USCI_I2C module. + * @param[in] u32IntSel Interrupt Type, should be + * - \ref UI2C_PROTIEN_ACKIEN_Msk + * - \ref UI2C_PROTIEN_ERRIEN_Msk + * - \ref UI2C_PROTIEN_ARBLOIEN_Msk + * - \ref UI2C_PROTIEN_NACKIEN_Msk + * - \ref UI2C_PROTIEN_STORIEN_Msk + * - \ref UI2C_PROTIEN_STARIEN_Msk + * - \ref UI2C_PROTIEN_TOIEN_Msk + * @return None + * + * @details Clear specified USCI_I2C protocol interrupt bits to disable interrupt funtion. + */ +#define UI2C_DISABLE_PROT_INT(ui2c, u32IntSel) ((ui2c)->PROTIEN &= ~ (u32IntSel)) + + +uint32_t UI2C_Open(UI2C_T *ui2c, uint32_t u32BusClock); +void UI2C_Close(UI2C_T *ui2c); +void UI2C_ClearTimeoutFlag(UI2C_T *ui2c); +void UI2C_Trigger(UI2C_T *ui2c, uint8_t u8Start, uint8_t u8Stop, uint8_t u8Ptrg, uint8_t u8Ack); +void UI2C_DisableInt(UI2C_T *ui2c, uint32_t u32Mask); +void UI2C_EnableInt(UI2C_T *ui2c, uint32_t u32Mask); +uint32_t UI2C_GetBusClockFreq(UI2C_T *ui2c); +uint32_t UI2C_SetBusClockFreq(UI2C_T *ui2c, uint32_t u32BusClock); +uint32_t UI2C_GetIntFlag(UI2C_T *ui2c, uint32_t u32Mask); +void UI2C_ClearIntFlag(UI2C_T* ui2c, uint32_t u32Mask); +uint32_t UI2C_GetData(UI2C_T *ui2c); +void UI2C_SetData(UI2C_T *ui2c, uint8_t u8Data); +void UI2C_SetSlaveAddr(UI2C_T *ui2c, uint8_t u8SlaveNo, uint16_t u16SlaveAddr, uint8_t u8GCMode); +void UI2C_SetSlaveAddrMask(UI2C_T *ui2c, uint8_t u8SlaveNo, uint16_t u16SlaveAddrMask); +void UI2C_EnableTimeout(UI2C_T *ui2c, uint32_t u32TimeoutCnt); +void UI2C_DisableTimeout(UI2C_T *ui2c); +void UI2C_EnableWakeup(UI2C_T *ui2c, uint8_t u8WakeupMode); +void UI2C_DisableWakeup(UI2C_T *ui2c); +uint8_t UI2C_WriteByte(UI2C_T *ui2c, uint8_t u8SlaveAddr, uint8_t data); +uint32_t UI2C_WriteMultiBytes(UI2C_T *ui2c, uint8_t u8SlaveAddr, uint8_t data[], uint32_t u32wLen); +uint8_t UI2C_WriteByteOneReg(UI2C_T *ui2c, uint8_t u8SlaveAddr, uint8_t u8DataAddr, uint8_t data); +uint32_t UI2C_WriteMultiBytesOneReg(UI2C_T *ui2c, uint8_t u8SlaveAddr, uint8_t u8DataAddr, uint8_t data[], uint32_t u32wLen); +uint8_t UI2C_WriteByteTwoRegs(UI2C_T *ui2c, uint8_t u8SlaveAddr, uint16_t u16DataAddr, uint8_t data); +uint32_t UI2C_WriteMultiBytesTwoRegs(UI2C_T *ui2c, uint8_t u8SlaveAddr, uint16_t u16DataAddr, uint8_t data[], uint32_t u32wLen); +uint8_t UI2C_ReadByte(UI2C_T *ui2c, uint8_t u8SlaveAddr); +uint32_t UI2C_ReadMultiBytes(UI2C_T *ui2c, uint8_t u8SlaveAddr, uint8_t rdata[], uint32_t u32rLen); +uint8_t UI2C_ReadByteOneReg(UI2C_T *ui2c, uint8_t u8SlaveAddr, uint8_t u8DataAddr); +uint32_t UI2C_ReadMultiBytesOneReg(UI2C_T *ui2c, uint8_t u8SlaveAddr, uint8_t u8DataAddr, uint8_t rdata[], uint32_t u32rLen); +uint8_t UI2C_ReadByteTwoRegs(UI2C_T *ui2c, uint8_t u8SlaveAddr, uint16_t u16DataAddr); +uint32_t UI2C_ReadMultiBytesTwoRegs(UI2C_T *ui2c, uint8_t u8SlaveAddr, uint16_t u16DataAddr, uint8_t rdata[], uint32_t u32rLen); +/**@}*/ /* end of group USCI_I2C_EXPORTED_FUNCTIONS */ + +/**@}*/ /* end of group USCI_I2C_Driver */ + +/**@}*/ /* end of group Standard_Driver */ + +#ifdef __cplusplus +} +#endif + +#endif + diff --git a/Ubiquitous/XiZi/board/nuvoton-m2354/third_party_driver/include/Drivers/nu_usci_spi.h b/Ubiquitous/XiZi/board/nuvoton-m2354/third_party_driver/include/Drivers/nu_usci_spi.h new file mode 100644 index 0000000..6689bd3 --- /dev/null +++ b/Ubiquitous/XiZi/board/nuvoton-m2354/third_party_driver/include/Drivers/nu_usci_spi.h @@ -0,0 +1,420 @@ +/****************************************************************************//** + * @file nu_usci_spi.h + * @version V3.00 + * @brief M2354 series USCI_SPI driver header file + * + * @copyright SPDX-License-Identifier: Apache-2.0 + * @copyright Copyright (C) 2020 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ +#ifndef __NU_USCI_SPI_H__ +#define __NU_USCI_SPI_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup USCI_SPI_Driver USCI_SPI Driver + @{ +*/ + +/** @addtogroup USCI_SPI_EXPORTED_CONSTANTS USCI_SPI Exported Constants + @{ +*/ + +#define USPI_MODE_0 (0x0UL << USPI_PROTCTL_SCLKMODE_Pos) /*!< SCLK idle low; data transmit with falling edge and receive with rising edge */ +#define USPI_MODE_1 (0x1UL << USPI_PROTCTL_SCLKMODE_Pos) /*!< SCLK idle low; data transmit with rising edge and receive with falling edge */ +#define USPI_MODE_2 (0x2UL << USPI_PROTCTL_SCLKMODE_Pos) /*!< SCLK idle high; data transmit with rising edge and receive with falling edge */ +#define USPI_MODE_3 (0x3UL << USPI_PROTCTL_SCLKMODE_Pos) /*!< SCLK idle high; data transmit with falling edge and receive with rising edge */ + +#define USPI_SLAVE (USPI_PROTCTL_SLAVE_Msk) /*!< Set as slave */ +#define USPI_MASTER (0x0UL) /*!< Set as master */ + +#define USPI_SS (USPI_PROTCTL_SS_Msk) /*!< Set SS */ +#define USPI_SS_ACTIVE_HIGH (0x0UL) /*!< SS active high */ +#define USPI_SS_ACTIVE_LOW (USPI_LINECTL_CTLOINV_Msk) /*!< SS active low */ + +/* USCI_SPI Interrupt Mask */ +#define USPI_SSINACT_INT_MASK (0x001UL) /*!< Slave Slave Inactive interrupt mask */ +#define USPI_SSACT_INT_MASK (0x002UL) /*!< Slave Slave Active interrupt mask */ +#define USPI_SLVTO_INT_MASK (0x004UL) /*!< Slave Mode Time-out interrupt mask */ +#define USPI_SLVBE_INT_MASK (0x008UL) /*!< Slave Mode Bit Count Error interrupt mask */ +#define USPI_TXUDR_INT_MASK (0x010UL) /*!< Slave Transmit Under Run interrupt mask */ +#define USPI_RXOV_INT_MASK (0x020UL) /*!< Receive Buffer Overrun interrupt mask */ +#define USPI_TXST_INT_MASK (0x040UL) /*!< Transmit Start interrupt mask */ +#define USPI_TXEND_INT_MASK (0x080UL) /*!< Transmit End interrupt mask */ +#define USPI_RXST_INT_MASK (0x100UL) /*!< Receive Start interrupt mask */ +#define USPI_RXEND_INT_MASK (0x200UL) /*!< Receive End interrupt mask */ + +/* USCI_SPI Status Mask */ +#define USPI_BUSY_MASK (0x01UL) /*!< Busy status mask */ +#define USPI_RX_EMPTY_MASK (0x02UL) /*!< RX empty status mask */ +#define USPI_RX_FULL_MASK (0x04UL) /*!< RX full status mask */ +#define USPI_TX_EMPTY_MASK (0x08UL) /*!< TX empty status mask */ +#define USPI_TX_FULL_MASK (0x10UL) /*!< TX full status mask */ +#define USPI_SSLINE_STS_MASK (0x20UL) /*!< USCI_SPI_SS line status mask */ + +/**@}*/ /* end of group USCI_SPI_EXPORTED_CONSTANTS */ + + +/** @addtogroup USCI_SPI_EXPORTED_FUNCTIONS USCI_SPI Exported Functions + @{ +*/ + +/** + * @brief Disable slave 3-wire mode. + * @param[in] uspi The pointer of the specified USCI_SPI module. + * @return None + * \hideinitializer + */ +#define USPI_DISABLE_3WIRE_MODE(uspi) ( (uspi)->PROTCTL &= ~USPI_PROTCTL_SLV3WIRE_Msk ) + +/** + * @brief Enable slave 3-wire mode. + * @param[in] uspi The pointer of the specified USCI_SPI module. + * @return None + * \hideinitializer + */ +#define USPI_ENABLE_3WIRE_MODE(uspi) ( (uspi)->PROTCTL |= USPI_PROTCTL_SLV3WIRE_Msk ) + +/** + * @brief Get the Rx buffer empty flag. + * @param[in] uspi The pointer of the specified USCI_SPI module. + * @return Rx buffer flag + * @retval 0: Rx buffer is not empty + * @retval 1: Rx buffer is empty + * \hideinitializer + */ +#define USPI_GET_RX_EMPTY_FLAG(uspi) ( ((uspi)->BUFSTS & USPI_BUFSTS_RXEMPTY_Msk) == USPI_BUFSTS_RXEMPTY_Msk ? 1:0 ) + +/** + * @brief Get the Tx buffer empty flag. + * @param[in] uspi The pointer of the specified USCI_SPI module. + * @return Tx buffer flag + * @retval 0: Tx buffer is not empty + * @retval 1: Tx buffer is empty + * \hideinitializer + */ +#define USPI_GET_TX_EMPTY_FLAG(uspi) ( ((uspi)->BUFSTS & USPI_BUFSTS_TXEMPTY_Msk) == USPI_BUFSTS_TXEMPTY_Msk ? 1:0 ) + +/** + * @brief Get the Tx buffer full flag. + * @param[in] uspi The pointer of the specified USCI_SPI module. + * @return Tx buffer flag + * @retval 0: Tx buffer is not full + * @retval 1: Tx buffer is full + * \hideinitializer + */ +#define USPI_GET_TX_FULL_FLAG(uspi) ( ((uspi)->BUFSTS & USPI_BUFSTS_TXFULL_Msk) == USPI_BUFSTS_TXFULL_Msk ? 1:0 ) + +/** + * @brief Get the datum read from RX register. + * @param[in] uspi The pointer of the specified USCI_SPI module. + * @return data in Rx register + * \hideinitializer + */ +#define USPI_READ_RX(uspi) ( (uspi)->RXDAT ) + +/** + * @brief Write datum to TX register. + * @param[in] uspi The pointer of the specified USCI_SPI module. + * @param[in] u32TxData The datum which user attempt to transfer through USCI_SPI bus. + * @return None + * \hideinitializer + */ +#define USPI_WRITE_TX(uspi, u32TxData) ( (uspi)->TXDAT = (u32TxData) ) + +/** + * @brief Set USCI_SPI_SS pin to high state. + * @param[in] uspi The pointer of the specified USCI_SPI module. + * @return None. + * @details Disable automatic slave selection function and set USCI_SPI_SS pin to high state. Only available in Master mode. + * \hideinitializer + */ +#define USPI_SET_SS_HIGH(uspi) \ + do{ \ + (uspi)->LINECTL &= ~USPI_LINECTL_CTLOINV_Msk; \ + (uspi)->PROTCTL = (((uspi)->PROTCTL & ~USPI_PROTCTL_AUTOSS_Msk) | USPI_PROTCTL_SS_Msk); \ + }while(0) + +/** + * @brief Set USCI_SPI_SS pin to low state. + * @param[in] uspi The pointer of the specified USCI_SPI module. + * @return None. + * @details Disable automatic slave selection function and set USCI_SPI_SS pin to low state. Only available in Master mode. + * \hideinitializer + */ +#define USPI_SET_SS_LOW(uspi) \ + do{ \ + (uspi)->LINECTL |= USPI_LINECTL_CTLOINV_Msk; \ + (uspi)->PROTCTL = (((uspi)->PROTCTL & ~USPI_PROTCTL_AUTOSS_Msk) | USPI_PROTCTL_SS_Msk); \ + }while(0) + +/** + * @brief Set the length of suspend interval. + * @param[in] uspi The pointer of the specified USCI_SPI module. + * @param[in] u32SuspCycle Decide the length of suspend interval. + * @return None + * \hideinitializer + */ +#define USPI_SET_SUSPEND_CYCLE(uspi, u32SuspCycle) ( (uspi)->PROTCTL = ((uspi)->PROTCTL & ~USPI_PROTCTL_SUSPITV_Msk) | ((u32SuspCycle) << USPI_PROTCTL_SUSPITV_Pos) ) + +/** + * @brief Set the USCI_SPI transfer sequence with LSB first. + * @param[in] uspi The pointer of the specified USCI_SPI module. + * @return None + * \hideinitializer + */ +#define USPI_SET_LSB_FIRST(uspi) ( (uspi)->LINECTL |= USPI_LINECTL_LSB_Msk ) + +/** + * @brief Set the USCI_SPI transfer sequence with MSB first. + * @param[in] uspi The pointer of the specified USCI_SPI module. + * @return None + * \hideinitializer + */ +#define USPI_SET_MSB_FIRST(uspi) ( (uspi)->LINECTL &= ~USPI_LINECTL_LSB_Msk ) + +/** + * @brief Set the data width of a USCI_SPI transaction. + * @param[in] uspi The pointer of the specified USCI_SPI module. + * @param[in] u32Width The data width + * @return None + * \hideinitializer + */ +#define USPI_SET_DATA_WIDTH(uspi, u32Width) \ + do{ \ + if((u32Width) == 16ul){ \ + (uspi)->LINECTL = ((uspi)->LINECTL & ~USPI_LINECTL_DWIDTH_Msk) | (0 << USPI_LINECTL_DWIDTH_Pos); \ + }else { \ + (uspi)->LINECTL = ((uspi)->LINECTL & ~USPI_LINECTL_DWIDTH_Msk) | ((u32Width) << USPI_LINECTL_DWIDTH_Pos); \ + } \ + }while(0) + +/** + * @brief Get the USCI_SPI busy state. + * @param[in] uspi The pointer of the specified USCI_SPI module. + * @return USCI_SPI busy status + * @retval 0: USCI_SPI module is not busy + * @retval 1: USCI_SPI module is busy + * \hideinitializer + */ +#define USPI_IS_BUSY(uspi) ( ((uspi)->PROTSTS & USPI_PROTSTS_BUSY_Msk) == USPI_PROTSTS_BUSY_Msk ? 1:0 ) + +/** + * @brief Get the USCI_SPI wakeup flag. + * @param[in] uspi The pointer of the specified USCI_SPI module. + * @return Wakeup status. + * @retval 0 Flag is not set. + * @retval 1 Flag is set. + * \hideinitializer + */ +#define USPI_GET_WAKEUP_FLAG(uspi) ( ((uspi)->WKSTS & USPI_WKSTS_WKF_Msk) == USPI_WKSTS_WKF_Msk ? 1:0 ) + +/** + * @brief Clear the USCI_SPI wakeup flag. + * @param[in] uspi The pointer of the specified USCI_SPI module. + * @return None + * \hideinitializer + */ +#define USPI_CLR_WAKEUP_FLAG(uspi) ( (uspi)->WKSTS |= USPI_WKSTS_WKF_Msk ) + +/** + * @brief Get protocol interrupt flag/status. + * @param[in] uspi The pointer of the specified USCI_SPI module. + * @return The interrupt flag/status of protocol status register. + * \hideinitializer + */ +#define USPI_GET_PROT_STATUS(uspi) ( (uspi)->PROTSTS ) + +/** + * @brief Clear specified protocol interrupt flag. + * @param[in] uspi The pointer of the specified USCI_SPI module. + * @param[in] u32IntTypeFlag Interrupt Type Flag, should be + * - \ref USPI_PROTSTS_SSACTIF_Msk + * - \ref USPI_PROTSTS_SSINAIF_Msk + * - \ref USPI_PROTSTS_SLVBEIF_Msk + * - \ref USPI_PROTSTS_SLVTOIF_Msk + * - \ref USPI_PROTSTS_RXENDIF_Msk + * - \ref USPI_PROTSTS_RXSTIF_Msk + * - \ref USPI_PROTSTS_TXENDIF_Msk + * - \ref USPI_PROTSTS_TXSTIF_Msk + * @return None + * \hideinitializer + */ +#define USPI_CLR_PROT_INT_FLAG(uspi, u32IntTypeFlag) ( (uspi)->PROTSTS = (u32IntTypeFlag) ) + +/** + * @brief Get buffer interrupt flag/status. + * @param[in] uspi The pointer of the specified USCI_SPI module. + * @return The interrupt flag/status of buffer status register. + * \hideinitializer + */ +#define USPI_GET_BUF_STATUS(uspi) ( (uspi)->BUFSTS ) + +/** + * @brief Clear specified buffer interrupt flag. + * @param[in] uspi The pointer of the specified USCI_SPI module. + * @param[in] u32IntTypeFlag Interrupt Type Flag, should be + * - \ref USPI_BUFSTS_TXUDRIF_Msk + * - \ref USPI_BUFSTS_RXOVIF_Msk + * @return None + * \hideinitializer + */ +#define USPI_CLR_BUF_INT_FLAG(uspi, u32IntTypeFlag) ( (uspi)->BUFSTS = (u32IntTypeFlag) ) + +/** + * @brief Enable specified protocol interrupt. + * @param[in] uspi The pointer of the specified USCI_SPI module. + * @param[in] u32IntSel Interrupt Type, should be + * - \ref USPI_PROTIEN_SLVBEIEN_Msk + * - \ref USPI_PROTIEN_SLVTOIEN_Msk + * - \ref USPI_PROTIEN_SSACTIEN_Msk + * - \ref USPI_PROTIEN_SSINAIEN_Msk + * @return None + * \hideinitializer + */ +#define USPI_ENABLE_PROT_INT(uspi, u32IntSel) ( (uspi)->PROTIEN |= (u32IntSel) ) + +/** + * @brief Disable specified protocol interrupt. + * @param[in] uspi The pointer of the specified USCI_SPI module. + * @param[in] u32IntSel Interrupt Type, should be + * - \ref USPI_PROTIEN_SLVBEIEN_Msk + * - \ref USPI_PROTIEN_SLVTOIEN_Msk + * - \ref USPI_PROTIEN_SSACTIEN_Msk + * - \ref USPI_PROTIEN_SSINAIEN_Msk + * @return None + * \hideinitializer + */ +#define USPI_DISABLE_PROT_INT(uspi, u32IntSel) ( (uspi)->PROTIEN &= ~ (u32IntSel) ) + +/** + * @brief Enable specified buffer interrupt. + * @param[in] uspi The pointer of the specified USCI_SPI module. + * @param[in] u32IntSel Interrupt Type, should be + * - \ref USPI_BUFCTL_RXOVIEN_Msk + * - \ref USPI_BUFCTL_TXUDRIEN_Msk + * @return None + * \hideinitializer + */ +#define USPI_ENABLE_BUF_INT(uspi, u32IntSel) ( (uspi)->BUFCTL |= (u32IntSel) ) + +/** + * @brief Disable specified buffer interrupt. + * @param[in] uspi The pointer of the specified USCI_SPI module. + * @param[in] u32IntSel Interrupt Type, should be + * - \ref USPI_BUFCTL_RXOVIEN_Msk + * - \ref USPI_BUFCTL_TXUDRIEN_Msk + * @return None + * \hideinitializer + */ +#define USPI_DISABLE_BUF_INT(uspi, u32IntSel) ( (uspi)->BUFCTL &= ~ (u32IntSel) ) + +/** + * @brief Enable specified transfer interrupt. + * @param[in] uspi The pointer of the specified USCI_SPI module. + * @param[in] u32IntSel Interrupt Type, should be + * - \ref USPI_INTEN_RXENDIEN_Msk + * - \ref USPI_INTEN_RXSTIEN_Msk + * - \ref USPI_INTEN_TXENDIEN_Msk + * - \ref USPI_INTEN_TXSTIEN_Msk + * @return None + * \hideinitializer + */ +#define USPI_ENABLE_TRANS_INT(uspi, u32IntSel) ( (uspi)->INTEN |= (u32IntSel) ) + +/** + * @brief Disable specified transfer interrupt. + * @param[in] uspi The pointer of the specified USCI_SPI module. + * @param[in] u32IntSel Interrupt Type, should be + * - \ref USPI_INTEN_RXENDIEN_Msk + * - \ref USPI_INTEN_RXSTIEN_Msk + * - \ref USPI_INTEN_TXENDIEN_Msk + * - \ref USPI_INTEN_TXSTIEN_Msk + * @return None + * \hideinitializer + */ +#define USPI_DISABLE_TRANS_INT(uspi, u32IntSel) ( (uspi)->INTEN &= ~ (u32IntSel) ) + +/** + * @brief Trigger RX PDMA function. + * @param[in] uspi The pointer of the specified USCI_SPI module. + * @return None. + * @details Set RXPDMAEN bit of USPI_PDMACTL register to enable RX PDMA transfer function. + */ +#define USPI_TRIGGER_RX_PDMA(uspi) ( (uspi)->PDMACTL |= USPI_PDMACTL_RXPDMAEN_Msk | USPI_PDMACTL_PDMAEN_Msk ) + +/** + * @brief Trigger TX PDMA function. + * @param[in] uspi The pointer of the specified USCI_SPI module. + * @return None. + * @details Set TXPDMAEN bit of USPI_PDMACTL register to enable TX PDMA transfer function. + */ +#define USPI_TRIGGER_TX_PDMA(uspi) ( (uspi)->PDMACTL |= USPI_PDMACTL_TXPDMAEN_Msk | USPI_PDMACTL_PDMAEN_Msk ) + +/** + * @brief Trigger TX and RX PDMA function. + * @param[in] uspi The pointer of the specified USCI_SPI module. + * @return None. + * @details Set TXPDMAEN bit and RXPDMAEN bit of USPI_PDMACTL register to enable TX and RX PDMA transfer function. + */ +#define USPI_TRIGGER_TX_RX_PDMA(uspi) ( (uspi)->PDMACTL |= USPI_PDMACTL_TXPDMAEN_Msk | USPI_PDMACTL_RXPDMAEN_Msk | USPI_PDMACTL_PDMAEN_Msk ) + +/** + * @brief Disable RX PDMA transfer. + * @param[in] uspi The pointer of the specified USCI_SPI module. + * @return None. + * @details Clear RXPDMAEN bit of USPI_PDMACTL register to disable RX PDMA transfer function. + */ +#define USPI_DISABLE_RX_PDMA(uspi) ( (uspi)->PDMACTL &= ~USPI_PDMACTL_RXPDMAEN_Msk ) + +/** + * @brief Disable TX PDMA transfer. + * @param[in] uspi The pointer of the specified USCI_SPI module. + * @return None. + * @details Clear TXPDMAEN bit of USPI_PDMACTL register to disable TX PDMA transfer function. + */ +#define USPI_DISABLE_TX_PDMA(uspi) ( (uspi)->PDMACTL &= ~USPI_PDMACTL_TXPDMAEN_Msk ) + +/** + * @brief Disable TX and RX PDMA transfer. + * @param[in] uspi The pointer of the specified USCI_SPI module. + * @return None. + * @details Clear TXPDMAEN bit and RXPDMAEN bit of USPI_PDMACTL register to disable TX and RX PDMA transfer function. + */ +#define USPI_DISABLE_TX_RX_PDMA(uspi) ( (uspi)->PDMACTL &= ~(USPI_PDMACTL_TXPDMAEN_Msk | USPI_PDMACTL_RXPDMAEN_Msk) ) + +uint32_t USPI_Open(USPI_T *uspi, uint32_t u32MasterSlave, uint32_t u32SPIMode, uint32_t u32DataWidth, uint32_t u32BusClock); +void USPI_Close(USPI_T *uspi); +void USPI_ClearRxBuf(USPI_T *uspi); +void USPI_ClearTxBuf(USPI_T *uspi); +void USPI_DisableAutoSS(USPI_T *uspi); +void USPI_EnableAutoSS(USPI_T *uspi, uint32_t u32SSPinMask, uint32_t u32ActiveLevel); +uint32_t USPI_SetBusClock(USPI_T *uspi, uint32_t u32BusClock); +uint32_t USPI_GetBusClock(USPI_T *uspi); +void USPI_EnableInt(USPI_T *uspi, uint32_t u32Mask); +void USPI_DisableInt(USPI_T *uspi, uint32_t u32Mask); +uint32_t USPI_GetIntFlag(USPI_T *uspi, uint32_t u32Mask); +void USPI_ClearIntFlag(USPI_T *uspi, uint32_t u32Mask); +uint32_t USPI_GetStatus(USPI_T *uspi, uint32_t u32Mask); +void USPI_EnableWakeup(USPI_T *uspi); +void USPI_DisableWakeup(USPI_T *uspi); + + +/**@}*/ /* end of group USCI_SPI_EXPORTED_FUNCTIONS */ + +/**@}*/ /* end of group USCI_SPI_Driver */ + +/**@}*/ /* end of group Standard_Driver */ + +#ifdef __cplusplus +} +#endif + +#endif /* __NU_USCI_SPI_H__ */ diff --git a/Ubiquitous/XiZi/board/nuvoton-m2354/third_party_driver/include/Drivers/nu_usci_uart.h b/Ubiquitous/XiZi/board/nuvoton-m2354/third_party_driver/include/Drivers/nu_usci_uart.h new file mode 100644 index 0000000..550955c --- /dev/null +++ b/Ubiquitous/XiZi/board/nuvoton-m2354/third_party_driver/include/Drivers/nu_usci_uart.h @@ -0,0 +1,445 @@ +/****************************************************************************** + * @file nu_usci_uart.h + * @version V3.00 + * @brief M2354 series USCI UART (UUART) driver header file + * + * @copyright SPDX-License-Identifier: Apache-2.0 + * @copyright Copyright (C) 2020 Nuvoton Technology Corp. All rights reserved. +*****************************************************************************/ +#ifndef __NU_USCI_UART_H__ +#define __NU_USCI_UART_H__ + + +#ifdef __cplusplus +extern "C" +{ +#endif + + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup USCI_UART_Driver USCI_UART Driver + @{ +*/ + +/** @addtogroup USCI_UART_EXPORTED_CONSTANTS USCI_UART Exported Constants + @{ +*/ + +/*---------------------------------------------------------------------------------------------------------*/ +/* UUART_LINECTL constants definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define UUART_WORD_LEN_6 (6UL << UUART_LINECTL_DWIDTH_Pos) /*!< UUART_LINECTL setting to set UART word length to 6 bits */ +#define UUART_WORD_LEN_7 (7UL << UUART_LINECTL_DWIDTH_Pos) /*!< UUART_LINECTL setting to set UART word length to 7 bits */ +#define UUART_WORD_LEN_8 (8UL << UUART_LINECTL_DWIDTH_Pos) /*!< UUART_LINECTL setting to set UART word length to 8 bits */ +#define UUART_WORD_LEN_9 (9UL << UUART_LINECTL_DWIDTH_Pos) /*!< UUART_LINECTL setting to set UART word length to 9 bits */ + +/*---------------------------------------------------------------------------------------------------------*/ +/* UUART_PROTCTL constants definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define UUART_PARITY_NONE (0x0UL << UUART_PROTCTL_PARITYEN_Pos) /*!< UUART_PROTCTL setting to set UART as no parity */ +#define UUART_PARITY_ODD (0x1UL << UUART_PROTCTL_PARITYEN_Pos) /*!< UUART_PROTCTL setting to set UART as odd parity */ +#define UUART_PARITY_EVEN (0x3UL << UUART_PROTCTL_PARITYEN_Pos) /*!< UUART_PROTCTL setting to set UART as even parity */ + +#define UUART_STOP_BIT_1 (0x0UL) /*!< UUART_PROTCTL setting for one stop bit */ +#define UUART_STOP_BIT_2 (0x1UL) /*!< UUART_PROTCTL setting for two stop bit */ + +/*---------------------------------------------------------------------------------------------------------*/ +/* USCI UART interrupt mask definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define UUART_ABR_INT_MASK (0x002UL) /*!< Auto-baud rate interrupt mask */ +#define UUART_RLS_INT_MASK (0x004UL) /*!< Receive line status interrupt mask */ +#define UUART_BUF_RXOV_INT_MASK (0x008UL) /*!< Buffer RX overrun interrupt mask */ +#define UUART_TXST_INT_MASK (0x010UL) /*!< TX start interrupt mask */ +#define UUART_TXEND_INT_MASK (0x020UL) /*!< Tx end interrupt mask */ +#define UUART_RXST_INT_MASK (0x040UL) /*!< RX start interrupt mask */ +#define UUART_RXEND_INT_MASK (0x080UL) /*!< RX end interrupt mask */ + + +/**@}*/ /* end of group USCI_UART_EXPORTED_CONSTANTS */ + + +/** @addtogroup USCI_UART_EXPORTED_FUNCTIONS USCI_UART Exported Functions + @{ +*/ + + +/** + * @brief Write USCI_UART data + * + * @param[in] uuart The pointer of the specified USCI_UART module + * @param[in] u8Data Data byte to transmit. + * + * @return None + * + * @details This macro write Data to Tx data register. + */ +#define UUART_WRITE(uuart, u8Data) ((uuart)->TXDAT = (u8Data)) + + +/** + * @brief Read USCI_UART data + * + * @param[in] uuart The pointer of the specified USCI_UART module + * + * @return The oldest data byte in RX buffer. + * + * @details This macro read Rx data register. + */ +#define UUART_READ(uuart) ((uuart)->RXDAT) + + +/** + * @brief Get Tx empty + * + * @param[in] uuart The pointer of the specified USCI_UART module + * + * @retval 0 Tx buffer is not empty + * @retval >=1 Tx buffer is empty + * + * @details This macro get Transmitter buffer empty register value. + */ +#define UUART_GET_TX_EMPTY(uuart) ((uuart)->BUFSTS & UUART_BUFSTS_TXEMPTY_Msk) + + +/** + * @brief Get Rx empty + * + * @param[in] uuart The pointer of the specified USCI_UART module + * + * @retval 0 Rx buffer is not empty + * @retval >=1 Rx buffer is empty + * + * @details This macro get Receiver buffer empty register value. + */ +#define UUART_GET_RX_EMPTY(uuart) ((uuart)->BUFSTS & UUART_BUFSTS_RXEMPTY_Msk) + + +/** + * @brief Check specified usci_uart port transmission is over. + * + * @param[in] uuart The pointer of the specified USCI_UART module + * + * @retval 0 Tx transmission is not over + * @retval 1 Tx transmission is over + * + * @details This macro return Transmitter Empty Flag register bit value. \n + * It indicates if specified usci_uart port transmission is over nor not. + */ +#define UUART_IS_TX_EMPTY(uuart) (((uuart)->BUFSTS & UUART_BUFSTS_TXEMPTY_Msk) >> UUART_BUFSTS_TXEMPTY_Pos) + + +/** + * @brief Check specified usci_uart port receiver is empty. + * + * @param[in] uuart The pointer of the specified USCI_UART module + * + * @retval 0 Rx receiver is not empty + * @retval 1 Rx receiver is empty + * + * @details This macro return Receive Empty Flag register bit value. \n + * It indicates if specified usci_uart port receiver is empty nor not. + */ +#define UUART_IS_RX_EMPTY(uuart) (((uuart)->BUFSTS & UUART_BUFSTS_RXEMPTY_Msk) >> UUART_BUFSTS_RXEMPTY_Pos) + + +/** + * @brief Wait specified usci_uart port transmission is over + * + * @param[in] uuart The pointer of the specified USCI_UART module + * + * @return None + * + * @details This macro wait specified usci_uart port transmission is over. + */ +#define UUART_WAIT_TX_EMPTY(uuart) while(!((((uuart)->BUFSTS) & UUART_BUFSTS_TXEMPTY_Msk) >> UUART_BUFSTS_TXEMPTY_Pos)) + + +/** + * @brief Check TX buffer is full or not + * + * @param[in] uuart The pointer of the specified USCI_UART module + * + * @retval 1 TX buffer is full + * @retval 0 TX buffer is not full + * + * @details This macro check TX buffer is full or not. + */ +#define UUART_IS_TX_FULL(uuart) (((uuart)->BUFSTS & UUART_BUFSTS_TXFULL_Msk)>>UUART_BUFSTS_TXFULL_Pos) + + +/** + * @brief Check RX buffer is full or not + * + * @param[in] uuart The pointer of the specified USCI_UART module + * + * @retval 1 RX buffer is full + * @retval 0 RX buffer is not full + * + * @details This macro check RX buffer is full or not. + */ +#define UUART_IS_RX_FULL(uuart) (((uuart)->BUFSTS & UUART_BUFSTS_RXFULL_Msk)>>UUART_BUFSTS_RXFULL_Pos) + + +/** + * @brief Get Tx full register value + * + * @param[in] uuart The pointer of the specified USCI_UART module + * + * @retval 0 Tx buffer is not full. + * @retval >=1 Tx buffer is full. + * + * @details This macro get Tx full register value. + */ +#define UUART_GET_TX_FULL(uuart) ((uuart)->BUFSTS & UUART_BUFSTS_TXFULL_Msk) + + +/** + * @brief Get Rx full register value + * + * @param[in] uuart The pointer of the specified USCI_UART module + * + * @retval 0 Rx buffer is not full. + * @retval >=1 Rx buffer is full. + * + * @details This macro get Rx full register value. + */ +#define UUART_GET_RX_FULL(uuart) ((uuart)->BUFSTS & UUART_BUFSTS_RXFULL_Msk) + + +/** + * @brief Enable specified USCI_UART protocol interrupt + * + * @param[in] uuart The pointer of the specified USCI_UART module + * @param[in] u32IntSel Interrupt type select + * - \ref UUART_PROTIEN_RLSIEN_Msk : Rx Line status interrupt + * - \ref UUART_PROTIEN_ABRIEN_Msk : Auto-baud rate interrupt + * + * @return None + * + * @details This macro enable specified USCI_UART protocol interrupt. + */ +#define UUART_ENABLE_PROT_INT(uuart, u32IntSel) ((uuart)->PROTIEN |= (u32IntSel)) + + +/** + * @brief Disable specified USCI_UART protocol interrupt + * + * @param[in] uuart The pointer of the specified USCI_UART module + * @param[in] u32IntSel Interrupt type select + * - \ref UUART_PROTIEN_RLSIEN_Msk : Rx Line status interrupt + * - \ref UUART_PROTIEN_ABRIEN_Msk : Auto-baud rate interrupt + * + * @return None + * + * @details This macro disable specified USCI_UART protocol interrupt. + */ +#define UUART_DISABLE_PROT_INT(uuart, u32IntSel) ((uuart)->PROTIEN &= ~(u32IntSel)) + + +/** + * @brief Enable specified USCI_UART buffer interrupt + * + * @param[in] uuart The pointer of the specified USCI_UART module + * @param[in] u32IntSel Interrupt type select + * - \ref UUART_BUFCTL_RXOVIEN_Msk : Receive buffer overrun error interrupt + * + * @return None + * + * @details This macro enable specified USCI_UART buffer interrupt. + */ +#define UUART_ENABLE_BUF_INT(uuart, u32IntSel) ((uuart)->BUFCTL |= (u32IntSel)) + + +/** + * @brief Disable specified USCI_UART buffer interrupt + * + * @param[in] uuart The pointer of the specified USCI_UART module + * @param[in] u32IntSel Interrupt type select + * - \ref UUART_BUFCTL_RXOVIEN_Msk : Receive buffer overrun error interrupt + * + * @return None + * + * @details This macro disable specified USCI_UART buffer interrupt. + */ +#define UUART_DISABLE_BUF_INT(uuart, u32IntSel) ((uuart)->BUFCTL &= ~ (u32IntSel)) + + +/** + * @brief Enable specified USCI_UART transfer interrupt + * + * @param[in] uuart The pointer of the specified USCI_UART module + * @param[in] u32IntSel Interrupt type select + * - \ref UUART_INTEN_RXENDIEN_Msk : Receive end interrupt + * - \ref UUART_INTEN_RXSTIEN_Msk : Receive start interrupt + * - \ref UUART_INTEN_TXENDIEN_Msk : Transmit end interrupt + * - \ref UUART_INTEN_TXSTIEN_Msk : Transmit start interrupt + * + * @return None + * + * @details This macro enable specified USCI_UART transfer interrupt. + */ +#define UUART_ENABLE_TRANS_INT(uuart, u32IntSel) ((uuart)->INTEN |= (u32IntSel)) + + +/** + * @brief Disable specified USCI_UART transfer interrupt + * + * @param[in] uuart The pointer of the specified USCI_UART module + * @param[in] u32IntSel Interrupt type select + * - \ref UUART_INTEN_RXENDIEN_Msk : Receive end interrupt + * - \ref UUART_INTEN_RXSTIEN_Msk : Receive start interrupt + * - \ref UUART_INTEN_TXENDIEN_Msk : Transmit end interrupt + * - \ref UUART_INTEN_TXSTIEN_Msk : Transmit start interrupt + * + * @return None + * + * @details This macro disable specified USCI_UART transfer interrupt. + */ +#define UUART_DISABLE_TRANS_INT(uuart, u32IntSel) ((uuart)->INTEN &= ~(u32IntSel)) + + +/** + * @brief Get protocol interrupt flag/status + * + * @param[in] uuart The pointer of the specified USCI_UART module + * + * @return The interrupt flag/status of protocol status register. + * + * @details This macro get protocol status register value. + */ +#define UUART_GET_PROT_STATUS(uuart) ((uuart)->PROTSTS) + + +/** + * @brief Clear specified protocol interrupt flag + * + * @param[in] uuart The pointer of the specified USCI_UART module + * @param[in] u32IntTypeFlag Interrupt Type Flag, should be + * - \ref UUART_PROTSTS_ABERRSTS_Msk : Auto-baud Rate Error Interrupt Indicator + * - \ref UUART_PROTSTS_ABRDETIF_Msk : Auto-baud Rate Detected Interrupt Flag + * - \ref UUART_PROTSTS_BREAK_Msk : Break Flag + * - \ref UUART_PROTSTS_FRMERR_Msk : Framing Error Flag + * - \ref UUART_PROTSTS_PARITYERR_Msk : Parity Error Flag + * - \ref UUART_PROTSTS_RXENDIF_Msk : Receive End Interrupt Flag + * - \ref UUART_PROTSTS_RXSTIF_Msk : Receive Start Interrupt Flag + * - \ref UUART_PROTSTS_TXENDIF_Msk : Transmit End Interrupt Flag + * - \ref UUART_PROTSTS_TXSTIF_Msk : Transmit Start Interrupt Flag + * + * @return None + * + * @details This macro clear specified protocol interrupt flag. + */ +#define UUART_CLR_PROT_INT_FLAG(uuart,u32IntTypeFlag) ((uuart)->PROTSTS = (u32IntTypeFlag)) + + +/** + * @brief Get transmit/receive buffer interrupt flag/status + * + * @param[in] uuart The pointer of the specified USCI_UART module + * + * @return The interrupt flag/status of buffer status register. + * + * @details This macro get buffer status register value. + */ +#define UUART_GET_BUF_STATUS(uuart) ((uuart)->BUFSTS) + + +/** + * @brief Clear specified buffer interrupt flag + * + * @param[in] uuart The pointer of the specified USCI_UART module + * @param[in] u32IntTypeFlag Interrupt Type Flag, should be + * - \ref UUART_BUFSTS_RXOVIF_Msk : Receive Buffer Over-run Error Interrupt Indicator + * + * @return None + * + * @details This macro clear specified buffer interrupt flag. + */ +#define UUART_CLR_BUF_INT_FLAG(uuart,u32IntTypeFlag) ((uuart)->BUFSTS = (u32IntTypeFlag)) + + +/** + * @brief Get wakeup flag + * + * @param[in] uuart The pointer of the specified USCI_UART module + * + * @retval 0 Chip did not wake up from power-down mode. + * @retval 1 Chip waked up from power-down mode. + * + * @details This macro get wakeup flag. + */ +#define UUART_GET_WAKEUP_FLAG(uuart) ((uuart)->WKSTS & UUART_WKSTS_WKF_Msk ? 1: 0 ) + + +/** + * @brief Clear wakeup flag + * + * @param[in] uuart The pointer of the specified USCI_UART module + * + * @return None + * + * @details This macro clear wakeup flag. + */ +#define UUART_CLR_WAKEUP_FLAG(uuart) ((uuart)->WKSTS = UUART_WKSTS_WKF_Msk) + + +/** + * @brief Enable specified USCI_UART PDMA function + * + * @param[in] uuart The pointer of the specified USCI_UART module + * @param[in] u32FuncSel Combination of following functions + * - \ref UUART_PDMACTL_TXPDMAEN_Msk + * - \ref UUART_PDMACTL_RXPDMAEN_Msk + * - \ref UUART_PDMACTL_PDMAEN_Msk + * + * @return None + * + * @details This macro enable specified USCI_UART PDMA function. + */ +#define UUART_PDMA_ENABLE(uuart, u32FuncSel) ((uuart)->PDMACTL |= (u32FuncSel)) + +/** + * @brief Disable specified USCI_UART PDMA function + * + * @param[in] uuart The pointer of the specified USCI_UART module + * @param[in] u32FuncSel Combination of following functions + * - \ref UUART_PDMACTL_TXPDMAEN_Msk + * - \ref UUART_PDMACTL_RXPDMAEN_Msk + * - \ref UUART_PDMACTL_PDMAEN_Msk + * + * @return None + * + * @details This macro disable specified USCI_UART PDMA function. + */ +#define UUART_PDMA_DISABLE(uuart, u32FuncSel) ((uuart)->PDMACTL &= ~(u32FuncSel)) + + +void UUART_ClearIntFlag(UUART_T* uuart, uint32_t u32Mask); +uint32_t UUART_GetIntFlag(UUART_T* uuart, uint32_t u32Mask); +void UUART_Close(UUART_T* uuart); +void UUART_DisableInt(UUART_T* uuart, uint32_t u32Mask); +void UUART_EnableInt(UUART_T* uuart, uint32_t u32Mask); +uint32_t UUART_Open(UUART_T* uuart, uint32_t u32baudrate); +uint32_t UUART_Read(UUART_T* uuart, uint8_t pu8RxBuf[], uint32_t u32ReadBytes); +uint32_t UUART_SetLine_Config(UUART_T* uuart, uint32_t u32baudrate, uint32_t u32data_width, uint32_t u32parity, uint32_t u32stop_bits); +uint32_t UUART_Write(UUART_T* uuart, uint8_t pu8TxBuf[], uint32_t u32WriteBytes); +void UUART_EnableWakeup(UUART_T* uuart, uint32_t u32WakeupMode); +void UUART_DisableWakeup(UUART_T* uuart); +void UUART_EnableFlowCtrl(UUART_T* uuart); +void UUART_DisableFlowCtrl(UUART_T* uuart); + + +/**@}*/ /* end of group USCI_UART_EXPORTED_FUNCTIONS */ + +/**@}*/ /* end of group USCI_UART_Driver */ + +/**@}*/ /* end of group Standard_Driver */ + +#ifdef __cplusplus +} +#endif + +#endif /* __NU_USCI_UART_H__ */ diff --git a/Ubiquitous/XiZi/board/nuvoton-m2354/third_party_driver/include/Drivers/nu_wdt.h b/Ubiquitous/XiZi/board/nuvoton-m2354/third_party_driver/include/Drivers/nu_wdt.h new file mode 100644 index 0000000..d85fa24 --- /dev/null +++ b/Ubiquitous/XiZi/board/nuvoton-m2354/third_party_driver/include/Drivers/nu_wdt.h @@ -0,0 +1,217 @@ +/**************************************************************************//** + * @file nu_wdt.h + * @version V3.00 + * @brief Watchdog Timer(WDT) driver header file + * + * @copyright SPDX-License-Identifier: Apache-2.0 + * @copyright Copyright (C) 2020 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ +#ifndef __NU_WDT_H__ +#define __NU_WDT_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup WDT_Driver WDT Driver + @{ +*/ + +/** @addtogroup WDT_EXPORTED_CONSTANTS WDT Exported Constants + @{ +*/ +/*---------------------------------------------------------------------------------------------------------*/ +/* WDT Time-out Interval Period Constant Definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define WDT_TIMEOUT_2POW4 (0UL << WDT_CTL_TOUTSEL_Pos) /*!< Setting WDT time-out interval to 2^4 * WDT clocks \hideinitializer */ +#define WDT_TIMEOUT_2POW6 (1UL << WDT_CTL_TOUTSEL_Pos) /*!< Setting WDT time-out interval to 2^6 * WDT clocks \hideinitializer */ +#define WDT_TIMEOUT_2POW8 (2UL << WDT_CTL_TOUTSEL_Pos) /*!< Setting WDT time-out interval to 2^8 * WDT clocks \hideinitializer */ +#define WDT_TIMEOUT_2POW10 (3UL << WDT_CTL_TOUTSEL_Pos) /*!< Setting WDT time-out interval to 2^10 * WDT clocks \hideinitializer */ +#define WDT_TIMEOUT_2POW12 (4UL << WDT_CTL_TOUTSEL_Pos) /*!< Setting WDT time-out interval to 2^12 * WDT clocks \hideinitializer */ +#define WDT_TIMEOUT_2POW14 (5UL << WDT_CTL_TOUTSEL_Pos) /*!< Setting WDT time-out interval to 2^14 * WDT clocks \hideinitializer */ +#define WDT_TIMEOUT_2POW16 (6UL << WDT_CTL_TOUTSEL_Pos) /*!< Setting WDT time-out interval to 2^16 * WDT clocks \hideinitializer */ +#define WDT_TIMEOUT_2POW18 (7UL << WDT_CTL_TOUTSEL_Pos) /*!< Setting WDT time-out interval to 2^18 * WDT clocks \hideinitializer */ +#define WDT_TIMEOUT_2POW20 (8UL << WDT_CTL_TOUTSEL_Pos) /*!< Setting WDT time-out interval to 2^20 * WDT clocks \hideinitializer */ + +/*---------------------------------------------------------------------------------------------------------*/ +/* WDT Reset Delay Period Constant Definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define WDT_RESET_DELAY_1026CLK (0UL << WDT_ALTCTL_RSTDSEL_Pos) /*!< Setting WDT reset delay period to 1026 * WDT clocks \hideinitializer */ +#define WDT_RESET_DELAY_130CLK (1UL << WDT_ALTCTL_RSTDSEL_Pos) /*!< Setting WDT reset delay period to 130 * WDT clocks \hideinitializer */ +#define WDT_RESET_DELAY_18CLK (2UL << WDT_ALTCTL_RSTDSEL_Pos) /*!< Setting WDT reset delay period to 18 * WDT clocks \hideinitializer */ +#define WDT_RESET_DELAY_3CLK (3UL << WDT_ALTCTL_RSTDSEL_Pos) /*!< Setting WDT reset delay period to 3 * WDT clocks \hideinitializer */ + +/*---------------------------------------------------------------------------------------------------------*/ +/* WDT Free Reset Counter Keyword Constant Definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define WDT_RESET_COUNTER_KEYWORD (0x00005AA5UL) /*!< Fill this value to WDT_RSTCNT register to free reset WDT counter \hideinitializer */ + +/**@}*/ /* end of group WDT_EXPORTED_CONSTANTS */ + + +/** @addtogroup WDT_EXPORTED_FUNCTIONS WDT Exported Functions + @{ +*/ + +/** + * @brief Clear WDT Reset System Flag + * + * @param None + * + * @return None + * + * @details This macro clears WDT time-out reset system flag. + * \hideinitializer + */ +#define WDT_CLEAR_RESET_FLAG() (WDT->CTL = (WDT->CTL & ~(WDT_CTL_IF_Msk | WDT_CTL_WKF_Msk)) | WDT_CTL_RSTF_Msk) + +/** + * @brief Clear WDT Time-out Interrupt Flag + * + * @param None + * + * @return None + * + * @details This macro clears WDT time-out interrupt flag. + * \hideinitializer + */ +#define WDT_CLEAR_TIMEOUT_INT_FLAG() (WDT->CTL = (WDT->CTL & ~(WDT_CTL_RSTF_Msk | WDT_CTL_WKF_Msk)) | WDT_CTL_IF_Msk) + +/** + * @brief Clear WDT Wake-up Flag + * + * @param None + * + * @return None + * + * @details This macro clears WDT time-out wake-up system flag. + * \hideinitializer + */ +#define WDT_CLEAR_TIMEOUT_WAKEUP_FLAG() (WDT->CTL = (WDT->CTL & ~(WDT_CTL_RSTF_Msk | WDT_CTL_IF_Msk)) | WDT_CTL_WKF_Msk) + +/** + * @brief Get WDT Time-out Reset Flag + * + * @param None + * + * @retval 0 WDT time-out reset system did not occur + * @retval 1 WDT time-out reset system occurred + * + * @details This macro indicates system has been reset by WDT time-out reset or not. + * \hideinitializer + */ +#define WDT_GET_RESET_FLAG() ((WDT->CTL & WDT_CTL_RSTF_Msk)? 1UL : 0UL) + +/** + * @brief Get WDT Time-out Interrupt Flag + * + * @param None + * + * @retval 0 WDT time-out interrupt did not occur + * @retval 1 WDT time-out interrupt occurred + * + * @details This macro indicates WDT time-out interrupt occurred or not. + * \hideinitializer + */ +#define WDT_GET_TIMEOUT_INT_FLAG() ((WDT->CTL & WDT_CTL_IF_Msk)? 1UL : 0UL) + +/** + * @brief Get WDT Time-out Wake-up Flag + * + * @param None + * + * @retval 0 WDT time-out interrupt does not cause CPU wake-up + * @retval 1 WDT time-out interrupt event cause CPU wake-up + * + * @details This macro indicates WDT time-out interrupt event has waked up system or not. + * \hideinitializer + */ +#define WDT_GET_TIMEOUT_WAKEUP_FLAG() ((WDT->CTL & WDT_CTL_WKF_Msk)? 1UL : 0UL) + +/** + * @brief Reset WDT Counter + * + * @param None + * + * @return None + * + * @details This macro is used to reset the internal 20-bit WDT up counter value. + * @note If WDT is activated and time-out reset system function is enabled also, user should \n + * reset the 20-bit WDT up counter value to avoid generate WDT time-out reset signal to \n + * reset system before the WDT time-out reset delay period expires. + * \hideinitializer + */ +#define WDT_RESET_COUNTER() (WDT->RSTCNT = WDT_RESET_COUNTER_KEYWORD) + + +/*---------------------------------------------------------------------------------------------------------*/ +/* static inline functions */ +/*---------------------------------------------------------------------------------------------------------*/ +/* Declare these inline functions here to avoid MISRA C 2004 rule 8.1 error */ +__STATIC_INLINE void WDT_Close(void); +__STATIC_INLINE void WDT_EnableInt(void); +__STATIC_INLINE void WDT_DisableInt(void); + +/** + * @brief Stop WDT Counting + * + * @param None + * + * @return None + * + * @details This function will stop WDT counting and disable WDT module. + */ +__STATIC_INLINE void WDT_Close(void) +{ + WDT->CTL = 0UL; + while(WDT->CTL & WDT_CTL_SYNC_Msk) {} /* Wait disable WDTEN bit completed, it needs 2 * WDT_CLK. */ +} + +/** + * @brief Enable WDT Time-out Interrupt + * + * @param None + * + * @return None + * + * @details This function will enable the WDT time-out interrupt function. + */ +__STATIC_INLINE void WDT_EnableInt(void) +{ + WDT->CTL |= WDT_CTL_INTEN_Msk; +} + +/** + * @brief Disable WDT Time-out Interrupt + * + * @param None + * + * @return None + * + * @details This function will disable the WDT time-out interrupt function. + */ +__STATIC_INLINE void WDT_DisableInt(void) +{ + /* Do not touch another write 1 clear bits */ + WDT->CTL &= ~(WDT_CTL_INTEN_Msk | WDT_CTL_RSTF_Msk | WDT_CTL_IF_Msk | WDT_CTL_WKF_Msk); +} + +void WDT_Open(uint32_t u32TimeoutInterval, uint32_t u32ResetDelay, uint32_t u32EnableReset, uint32_t u32EnableWakeup); + +/**@}*/ /* end of group WDT_EXPORTED_FUNCTIONS */ + +/**@}*/ /* end of group WDT_Driver */ + +/**@}*/ /* end of group Standard_Driver */ + +#ifdef __cplusplus +} +#endif + +#endif /* __NU_WDT_H__ */ diff --git a/Ubiquitous/XiZi/board/nuvoton-m2354/third_party_driver/include/Drivers/nu_wwdt.h b/Ubiquitous/XiZi/board/nuvoton-m2354/third_party_driver/include/Drivers/nu_wwdt.h new file mode 100644 index 0000000..da86138 --- /dev/null +++ b/Ubiquitous/XiZi/board/nuvoton-m2354/third_party_driver/include/Drivers/nu_wwdt.h @@ -0,0 +1,151 @@ +/**************************************************************************//** + * @file nu_wwdt.h + * @version V3.00 + * @brief Window Watchdog Timer(WWDT) driver header file + * + * @copyright SPDX-License-Identifier: Apache-2.0 + * @copyright Copyright (C) 2020 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ +#ifndef __NU_WWDT_H__ +#define __NU_WWDT_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup WWDT_Driver WWDT Driver + @{ +*/ + +/** @addtogroup WWDT_EXPORTED_CONSTANTS WWDT Exported Constants + @{ +*/ +/*---------------------------------------------------------------------------------------------------------*/ +/* WWDT Prescale Period Constant Definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define WWDT_PRESCALER_1 (0 << WWDT_CTL_PSCSEL_Pos) /*!< Select max time-out period to 1 * (64*WWDT_CLK) \hideinitializer */ +#define WWDT_PRESCALER_2 (1 << WWDT_CTL_PSCSEL_Pos) /*!< Select max time-out period to 2 * (64*WWDT_CLK) \hideinitializer */ +#define WWDT_PRESCALER_4 (2 << WWDT_CTL_PSCSEL_Pos) /*!< Select max time-out period to 4 * (64*WWDT_CLK) \hideinitializer */ +#define WWDT_PRESCALER_8 (3 << WWDT_CTL_PSCSEL_Pos) /*!< Select max time-out period to 8 * (64*WWDT_CLK) \hideinitializer */ +#define WWDT_PRESCALER_16 (4 << WWDT_CTL_PSCSEL_Pos) /*!< Select max time-out period to 16 * (64*WWDT_CLK) \hideinitializer */ +#define WWDT_PRESCALER_32 (5 << WWDT_CTL_PSCSEL_Pos) /*!< Select max time-out period to 32 * (64*WWDT_CLK) \hideinitializer */ +#define WWDT_PRESCALER_64 (6 << WWDT_CTL_PSCSEL_Pos) /*!< Select max time-out period to 64 * (64*WWDT_CLK) \hideinitializer */ +#define WWDT_PRESCALER_128 (7 << WWDT_CTL_PSCSEL_Pos) /*!< Select max time-out period to 128 * (64*WWDT_CLK) \hideinitializer */ +#define WWDT_PRESCALER_192 (8 << WWDT_CTL_PSCSEL_Pos) /*!< Select max time-out period to 192 * (64*WWDT_CLK) \hideinitializer */ +#define WWDT_PRESCALER_256 (9 << WWDT_CTL_PSCSEL_Pos) /*!< Select max time-out period to 256 * (64*WWDT_CLK) \hideinitializer */ +#define WWDT_PRESCALER_384 (10 << WWDT_CTL_PSCSEL_Pos) /*!< Select max time-out period to 384 * (64*WWDT_CLK) \hideinitializer */ +#define WWDT_PRESCALER_512 (11 << WWDT_CTL_PSCSEL_Pos) /*!< Select max time-out period to 512 * (64*WWDT_CLK) \hideinitializer */ +#define WWDT_PRESCALER_768 (12 << WWDT_CTL_PSCSEL_Pos) /*!< Select max time-out period to 768 * (64*WWDT_CLK) \hideinitializer */ +#define WWDT_PRESCALER_1024 (13 << WWDT_CTL_PSCSEL_Pos) /*!< Select max time-out period to 1024 * (64*WWDT_CLK) \hideinitializer */ +#define WWDT_PRESCALER_1536 (14 << WWDT_CTL_PSCSEL_Pos) /*!< Select max time-out period to 1536 * (64*WWDT_CLK) \hideinitializer */ +#define WWDT_PRESCALER_2048 (15 << WWDT_CTL_PSCSEL_Pos) /*!< Select max time-out period to 2048 * (64*WWDT_CLK) \hideinitializer */ + +/*---------------------------------------------------------------------------------------------------------*/ +/* WWDT Reload Counter Keyword Constant Definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define WWDT_RELOAD_WORD (0x00005AA5) /*!< Fill this value to WWDT_RLDCNT register to reload WWDT counter \hideinitializer */ + +/**@}*/ /* end of group WWDT_EXPORTED_CONSTANTS */ + + +/** @addtogroup WWDT_EXPORTED_FUNCTIONS WWDT Exported Functions + @{ +*/ + +/** + * @brief Clear WWDT Reset System Flag + * + * @param None + * + * @return None + * + * @details This macro is used to clear WWDT time-out reset system flag. + * \hideinitializer + */ +#define WWDT_CLEAR_RESET_FLAG() (WWDT->STATUS = WWDT_STATUS_WWDTRF_Msk) + +/** + * @brief Clear WWDT Compared Match Interrupt Flag + * + * @param None + * + * @return None + * + * @details This macro is used to clear WWDT compared match interrupt flag. + * \hideinitializer + */ +#define WWDT_CLEAR_INT_FLAG() (WWDT->STATUS = WWDT_STATUS_WWDTIF_Msk) + +/** + * @brief Get WWDT Reset System Flag + * + * @param None + * + * @retval 0 WWDT time-out reset system did not occur + * @retval 1 WWDT time-out reset system occurred + * + * @details This macro is used to indicate system has been reset by WWDT time-out reset or not. + * \hideinitializer + */ +#define WWDT_GET_RESET_FLAG() ((WWDT->STATUS & WWDT_STATUS_WWDTRF_Msk)? 1 : 0) + +/** + * @brief Get WWDT Compared Match Interrupt Flag + * + * @param None + * + * @retval 0 WWDT compare match interrupt did not occur + * @retval 1 WWDT compare match interrupt occurred + * + * @details This macro is used to indicate WWDT counter value matches CMPDAT value or not. + * \hideinitializer + */ +#define WWDT_GET_INT_FLAG() ((WWDT->STATUS & WWDT_STATUS_WWDTIF_Msk)? 1 : 0) + +/** + * @brief Get WWDT Counter + * + * @param None + * + * @return WWDT Counter Value + * + * @details This macro reflects the current WWDT counter value. + * \hideinitializer + */ +#define WWDT_GET_COUNTER() (WWDT->CNT) + +/** + * @brief Reload WWDT Counter + * + * @param None + * + * @return None + * + * @details This macro is used to reload the WWDT counter value to 0x3F. + * @note User can only write WWDT_RLDCNT register to reload WWDT counter value when current WWDT counter value \n + * between 0 and CMPDAT value. If user writes WWDT_RLDCNT when current WWDT counter value is larger than CMPDAT, \n + * WWDT reset signal will generate immediately to reset system. + * \hideinitializer + */ +#define WWDT_RELOAD_COUNTER() (WWDT->RLDCNT = WWDT_RELOAD_WORD) + +void WWDT_Open(uint32_t u32PreScale, uint32_t u32CmpValue, uint32_t u32EnableInt); + +/**@}*/ /* end of group WWDT_EXPORTED_FUNCTIONS */ + +/**@}*/ /* end of group WWDT_Driver */ + +/**@}*/ /* end of group Standard_Driver */ + +#ifdef __cplusplus +} +#endif + +#endif /* __NU_WWDT_H__ */ + diff --git a/Ubiquitous/XiZi/board/nuvoton-m2354/third_party_driver/include/NuUtils/inc/nu_bitutil.h b/Ubiquitous/XiZi/board/nuvoton-m2354/third_party_driver/include/NuUtils/inc/nu_bitutil.h new file mode 100644 index 0000000..e74ad35 --- /dev/null +++ b/Ubiquitous/XiZi/board/nuvoton-m2354/third_party_driver/include/NuUtils/inc/nu_bitutil.h @@ -0,0 +1,215 @@ +/**************************************************************************//** +* +* @copyright (C) 2020 Nuvoton Technology Corp. All rights reserved. +* +* SPDX-License-Identifier: Apache-2.0 +* +* Change Logs: +* Date Author Notes +* 2020-2-7 Wayne First version +* +******************************************************************************/ +#ifndef __NU_BITUTIL_H__ +#define __NU_BITUTIL_H__ + +#if defined(__ICCARM__) + #include +#endif + +#ifdef __cplusplus +extern "C" { +#endif + +/* ---------------------------------------------- + * Count Leading Zeros Count Trailing Zeros + * (MSB)00000000000000001000000000001000(LSB) + * ################| |!!! + * Find Highest Set Find First Set + * ---------------------------------------------- + * + * ---------------------------------------------- + * Count Leading Ones Count Trailing Ones + * (MSB)11111111111111110111111111110111(LSB) + * ^^^^^^^^^^^^^^^^| |@@@ + * Find Highest Zero Find First Zero + * ---------------------------------------------- +*/ + +/* Count Leading Zeros in word - Find Highest Set + EX: x=(MSB)00000000000000001000000000001000(LSB) + ################| + Find Highest Set + nu_clz will start zero-counting from MSB and return the number. +*/ +__STATIC_INLINE int nu_clz(uint32_t x) +{ + return x ? __CLZ(x):32; +} + +/* Count Leading Ones in word - Find Highest Zero + EX: x=(MSB)11111111111111110111111111110111(LSB) + ^^^^^^^^^^^^^^^^| + Find Highest Zero + nu_clo will start one-counting from MSB and return the number. +*/ +__STATIC_INLINE int nu_clo(uint32_t x) +{ + return nu_clz(~x); +} + +/* Count Trailing Zero in word - Find First Set + EX: x=(MSB)00000000000000001000000000001000(LSB) + |!!! + Find First Set + nu_ctz will start zero-counting from LSB and return the number. +*/ +__STATIC_INLINE int nu_ctz(uint32_t x) +{ + int c = 32; + if (x) + c = __CLZ(x & -x); + return x ? 31 - c : c; +} + +/* Count Trailing Ones in word - Find First Zero + EX: x=(MSB)11111111111111110111111111110111(LSB) + |@@@ + Find First Zero + nu_cto will start one-counting from LSB and return the number. +*/ +__STATIC_INLINE int nu_cto(uint32_t x) +{ + return nu_ctz(~x); +} + +/* Get 16-bit from a byte-array in little-endian */ +__STATIC_INLINE uint16_t nu_get16_le(const uint8_t *pos) +{ + uint16_t val; + + val = *pos ++; + val += (*pos << 8); + + return val; +} + +/* Set 16-bit to a byte-array in little-endian */ +__STATIC_INLINE void nu_set16_le(uint8_t *pos, uint16_t val) +{ + *pos ++ = val & 0xFF; + *pos = val >> 8; +} + +/* Get 32-bit from a byte-array in little-endian */ +__STATIC_INLINE uint32_t nu_get32_le(const uint8_t *pos) +{ + uint32_t val; + + val = *pos ++; + val += (*pos ++ << 8); + val += (*pos ++ << 16); + val += (*pos ++ << 24); + + return val; +} + +/* Get 24-bit from a byte-array in little-endian */ +__STATIC_INLINE uint32_t nu_get24_le(const uint8_t *pos) +{ + uint32_t val; + + val = *pos ++; + val += (*pos ++ << 8); + val += (*pos ++ << 16); + + return val; +} + +/* Set 24-bit to a byte-array in little-endian */ +__STATIC_INLINE void nu_set24_le(uint8_t *pos, uint32_t val) +{ + *pos ++ = val & 0xFF; + *pos ++ = (val >> 8) & 0xFF; + *pos ++ = (val >> 16) & 0xFF; +} + +/* Set 32-bit to a byte-array in little-endian */ +__STATIC_INLINE void nu_set32_le(uint8_t *pos, uint32_t val) +{ + *pos ++ = val & 0xFF; + *pos ++ = (val >> 8) & 0xFF; + *pos ++ = (val >> 16) & 0xFF; + *pos = (val >> 24) & 0xFF; +} + +/* Get 16-bit from a byte-array in big-endian */ +__STATIC_INLINE uint16_t nu_get16_be(const uint8_t *pos) +{ + uint16_t val; + + val = *pos ++; + val <<= 8; + val += *pos; + + return val; +} + +/* Set 16-bit to a byte-array in big-endian */ +__STATIC_INLINE void nu_set16_be(uint8_t *pos, uint16_t val) +{ + *pos ++ = val >> 8; + *pos = (val & 0xFF); +} + +/* Get 24-bit from a byte-array in big-endian */ +__STATIC_INLINE uint32_t nu_get24_be(const uint8_t *pos) +{ + uint32_t val; + + val = *pos ++; + val <<= 8; + val += *pos ++; + val <<= 8; + val += *pos ++; + + return val; +} + +/* Set 24-bit to a byte-array in big-endian */ +__STATIC_INLINE void nu_set24_be(uint8_t *pos, uint32_t val) +{ + *pos ++ = val >> 16; + *pos ++ = val >> 8; + *pos ++ = (val & 0xFF); +} + +/* Get 32-bit from a byte-array in big-endian */ +__STATIC_INLINE uint32_t nu_get32_be(const uint8_t *pos) +{ + uint32_t val; + + val = *pos ++; + val <<= 8; + val += *pos ++; + val <<= 8; + val += *pos ++; + val <<= 8; + val += *pos; + + return val; +} + +/* Set 32-bit to a byte-array in big-endian */ +__STATIC_INLINE void nu_set32_be(uint8_t *pos, uint32_t val) +{ + *pos ++ = val >> 24; + *pos ++ = val >> 16; + *pos ++ = val >> 8; + *pos ++ = (val & 0xFF); +} + +#ifdef __cplusplus +} +#endif + +#endif //__NU_BITUTIL_H__ diff --git a/Ubiquitous/XiZi/board/nuvoton-m2354/third_party_driver/include/NuUtils/inc/nu_miscutil.h b/Ubiquitous/XiZi/board/nuvoton-m2354/third_party_driver/include/NuUtils/inc/nu_miscutil.h new file mode 100644 index 0000000..6f7c72a --- /dev/null +++ b/Ubiquitous/XiZi/board/nuvoton-m2354/third_party_driver/include/NuUtils/inc/nu_miscutil.h @@ -0,0 +1,39 @@ +/**************************************************************************//** +* +* @copyright (C) 2020 Nuvoton Technology Corp. All rights reserved. +* +* SPDX-License-Identifier: Apache-2.0 +* +* Change Logs: +* Date Author Notes +* 2020-2-7 Wayne First version +* +******************************************************************************/ + +#ifndef NU_MISC_UTIL_H +#define NU_MISC_UTIL_H + +#ifdef __cplusplus +extern "C" { +#endif + +#define NU_MAX(a,b) ((a)>(b)?(a):(b)) +#define NU_MIN(a,b) ((a)<(b)?(a):(b)) +#define NU_CLAMP(x, min, max) NU_MIN(NU_MAX((x), (min)), (max)) +#define NU_ALIGN_DOWN(X, ALIGN) ((X) & ~((ALIGN) - 1)) +#define NU_ALIGN_UP(X, ALIGN) (((X) + (ALIGN) - 1) & ~((ALIGN) - 1)) +#define NU_ISALIGNED(a, b) (((a) & (b - 1)) == 0) + +#define SET_BIT(REG, BIT) ((REG) |= (BIT)) +#define CLEAR_BIT(REG, BIT) ((REG) &= ~(BIT)) +#define READ_BIT(REG, BIT) ((REG) & (BIT)) +#define CLEAR_REG(REG) ((REG) = (0x0)) +#define WRITE_REG(REG, VAL) ((REG) = (VAL)) +#define READ_REG(REG) ((REG)) +#define MODIFY_REG(REG, CLEARMASK, SETMASK) WRITE_REG((REG), (((READ_REG(REG)) & (~(CLEARMASK))) | (SETMASK))) + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/Ubiquitous/XiZi/board/nuvoton-m2354/third_party_driver/include/Regs/M2354.h b/Ubiquitous/XiZi/board/nuvoton-m2354/third_party_driver/include/Regs/M2354.h new file mode 100644 index 0000000..5b546a0 --- /dev/null +++ b/Ubiquitous/XiZi/board/nuvoton-m2354/third_party_driver/include/Regs/M2354.h @@ -0,0 +1,1100 @@ +/**************************************************************************//** + * @file M2354.h + * @version V3.0 + * @brief Peripheral Access Layer Header File + * + * @copyright SPDX-License-Identifier: Apache-2.0 + * @copyright Copyright (C) 2020 Nuvoton Technology Corp. All rights reserved. + ******************************************************************************/ + +/** + \mainpage Introduction + * + * + * This user manual describes the usage of M2354 device driver + * + * Disclaimer + * + * The Software is furnished "AS IS", without warranty as to performance or results, and + * the entire risk as to performance or results is assumed by YOU. Nuvoton disclaims all + * warranties, express, implied or otherwise, with regard to the Software, its use, or + * operation, including without limitation any and all warranties of merchantability, fitness + * for a particular purpose, and non-infringement of intellectual property rights. + * + */ + + +#ifndef __M2354_H__ +#define __M2354_H__ + +/*=============================================================================*/ +typedef volatile unsigned char vu8; +typedef volatile unsigned int vu32; +typedef volatile unsigned short vu16; +#define M8(adr) (*((vu8 *) (adr))) +#define M16(adr) (*((vu16 *) (adr))) +#define M32(adr) (*((vu32 *) (adr))) + +#define outpw(port,value) (*((volatile unsigned int *)(port))=(value)) +#define inpw(port) ((*((volatile unsigned int *)(port)))) +#define outpb(port,value) (*((volatile unsigned char *)(port))=(value)) +#define inpb(port) ((*((volatile unsigned char *)(port)))) +#define outps(port,value) (*((volatile unsigned short *)(port))=(value)) +#define inps(port) ((*((volatile unsigned short *)(port)))) + +#define outp32(port,value) (*((volatile unsigned int *)(port))=(value)) +#define inp32(port) ((*((volatile unsigned int *)(port)))) +#define outp8(port,value) (*((volatile unsigned char *)(port))=(value)) +#define inp8(port) ((*((volatile unsigned char *)(port)))) +#define outp16(port,value) (*((volatile unsigned short *)(port))=(value)) +#define inp16(port) ((*((volatile unsigned short *)(port)))) + + +#define E_SUCCESS 0 + +#define TRUE (1L) +#define FALSE (0L) + +#define ENABLE 1 +#define DISABLE 0 + +/* Bit Mask Definitions */ +#define BIT0 0x00000001UL +#define BIT1 0x00000002UL +#define BIT2 0x00000004UL +#define BIT3 0x00000008UL +#define BIT4 0x00000010UL +#define BIT5 0x00000020UL +#define BIT6 0x00000040UL +#define BIT7 0x00000080UL +#define BIT8 0x00000100UL +#define BIT9 0x00000200UL +#define BIT10 0x00000400UL +#define BIT11 0x00000800UL +#define BIT12 0x00001000UL +#define BIT13 0x00002000UL +#define BIT14 0x00004000UL +#define BIT15 0x00008000UL +#define BIT16 0x00010000UL +#define BIT17 0x00020000UL +#define BIT18 0x00040000UL +#define BIT19 0x00080000UL +#define BIT20 0x00100000UL +#define BIT21 0x00200000UL +#define BIT22 0x00400000UL +#define BIT23 0x00800000UL +#define BIT24 0x01000000UL +#define BIT25 0x02000000UL +#define BIT26 0x04000000UL +#define BIT27 0x08000000UL +#define BIT28 0x10000000UL +#define BIT29 0x20000000UL +#define BIT30 0x40000000UL +#define BIT31 0x80000000UL + + +/* Byte Mask Definitions */ +#define BYTE0_Msk (0x000000FFUL) +#define BYTE1_Msk (0x0000FF00UL) +#define BYTE2_Msk (0x00FF0000UL) +#define BYTE3_Msk (0xFF000000UL) + +#define _GET_BYTE0(u32Param) (((u32Param) & BYTE0_Msk) ) /*!< Extract Byte 0 (Bit 0~ 7) from parameter u32Param */ +#define _GET_BYTE1(u32Param) (((u32Param) & BYTE1_Msk) >> 8UL) /*!< Extract Byte 1 (Bit 8~15) from parameter u32Param */ +#define _GET_BYTE2(u32Param) (((u32Param) & BYTE2_Msk) >> 16UL) /*!< Extract Byte 2 (Bit 16~23) from parameter u32Param */ +#define _GET_BYTE3(u32Param) (((u32Param) & BYTE3_Msk) >> 24UL) /*!< Extract Byte 3 (Bit 24~31) from parameter u32Param */ + + + +#ifdef __cplusplus +extern "C" { +#endif + +/******************************************************************************/ +/* Processor and Core Peripherals */ +/******************************************************************************/ +/** @addtogroup CMSIS_Device CMSIS Definitions + Configuration of the Cortex-M23 Processor and Core Peripherals + @{ +*/ + + +/* + * ========================================================================== + * ---------- Interrupt Number Definition ----------------------------------- + * ========================================================================== + */ + +/** + * @details Interrupt Number Definition. The maximum of 32 Specific Interrupts are possible. + */ +typedef enum IRQn +{ + /****** Cortex-M0 Processor Exceptions Numbers ***************************************************/ + NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ + HardFault_IRQn = -13, /*!< 3 Cortex-M23 Hard Fault Interrupt */ + SVCall_IRQn = -5, /*!< 11 Cortex-M23 SV Call Interrupt */ + PendSV_IRQn = -2, /*!< 14 Cortex-M23 Pend SV Interrupt */ + SysTick_IRQn = -1, /*!< 15 Cortex-M23 System Tick Interrupt */ + + /****** ARMIKMCU Swift specific Interrupt Numbers ************************************************/ + + BOD_IRQn = 0, /*!< Brown Out detection Interrupt */ + IRC_IRQn = 1, /*!< Internal RC Interrupt */ + PWRWU_IRQn = 2, /*!< Power Down Wake Up Interrupt */ + RAMPE_IRQn = 3, /*!< SRAM parity check failed Interrupt */ + CKFAIL_IRQn = 4, /*!< Clock failed Interrupt */ + ISP_IRQn = 5, /*!< FMC ISP Interrupt */ + RTC_IRQn = 6, /*!< Real Time Clock Interrupt */ + RTC_TAMPER_IRQn = 7, /*!< RTC Tamper detection Interrupt */ + WDT_IRQn = 8, /*!< Watchdog Timer Interrupt */ + WWDT_IRQn = 9, /*!< Window Watchdog Timer Interrupt */ + EINT0_IRQn = 10, /*!< External Input 0 Interrupt */ + EINT1_IRQn = 11, /*!< External Input 1 Interrupt */ + EINT2_IRQn = 12, /*!< External Input 2 Interrupt */ + EINT3_IRQn = 13, /*!< External Input 3 Interrupt */ + EINT4_IRQn = 14, /*!< External Input 4 Interrupt */ + EINT5_IRQn = 15, /*!< External Input 5 Interrupt */ + GPA_IRQn = 16, /*!< GPIO Port A Interrupt */ + GPB_IRQn = 17, /*!< GPIO Port B Interrupt */ + GPC_IRQn = 18, /*!< GPIO Port C Interrupt */ + GPD_IRQn = 19, /*!< GPIO Port D Interrupt */ + GPE_IRQn = 20, /*!< GPIO Port E Interrupt */ + GPF_IRQn = 21, /*!< GPIO Port F Interrupt */ + QSPI0_IRQn = 22, /*!< QSPI0 Interrupt */ + SPI0_IRQn = 23, /*!< SPI0 Interrupt */ + BRAKE0_IRQn = 24, /*!< BRAKE0 Interrupt */ + EPWM0_P0_IRQn = 25, /*!< EPWM0P0 Interrupt */ + EPWM0_P1_IRQn = 26, /*!< EPWM0P1 Interrupt */ + EPWM0_P2_IRQn = 27, /*!< EPWM0P2 Interrupt */ + BRAKE1_IRQn = 28, /*!< BRAKE1 Interrupt */ + EPWM1_P0_IRQn = 29, /*!< EPWM1P0 Interrupt */ + EPWM1_P1_IRQn = 30, /*!< EPWM1P1 Interrupt */ + EPWM1_P2_IRQn = 31, /*!< EPWM1P2 Interrupt */ + TMR0_IRQn = 32, /*!< Timer 0 Interrupt */ + TMR1_IRQn = 33, /*!< Timer 1 Interrupt */ + TMR2_IRQn = 34, /*!< Timer 2 Interrupt */ + TMR3_IRQn = 35, /*!< Timer 3 Interrupt */ + UART0_IRQn = 36, /*!< UART 0 Interrupt */ + UART1_IRQn = 37, /*!< UART 1 Interrupt */ + I2C0_IRQn = 38, /*!< I2C 0 Interrupt */ + I2C1_IRQn = 39, /*!< I2C 1 Interrupt */ + PDMA0_IRQn = 40, /*!< Peripheral DMA 0 Interrupt */ + DAC_IRQn = 41, /*!< DAC Interrupt */ + EADC0_IRQn = 42, /*!< EADC Source 0 Interrupt */ + EADC1_IRQn = 43, /*!< EADC Source 1 Interrupt */ + ACMP01_IRQn = 44, /*!< Analog Comparator 0 and 1 Interrupt */ + EADC2_IRQn = 46, /*!< EADC Source 2 Interrupt */ + EADC3_IRQn = 47, /*!< EADC Source 3 Interrupt */ + UART2_IRQn = 48, /*!< UART2 Interrupt */ + UART3_IRQn = 49, /*!< UART3 Interrupt */ + SPI1_IRQn = 51, /*!< SPI1 Interrupt */ + SPI2_IRQn = 52, /*!< SPI2 Interrupt */ + USBD_IRQn = 53, /*!< USB device Interrupt */ + USBH_IRQn = 54, /*!< USB host Interrupt */ + USBOTG_IRQn = 55, /*!< USB OTG Interrupt */ + CAN0_IRQn = 56, /*!< CAN0 Interrupt */ + SC0_IRQn = 58, /*!< Smart Card 0 Interrupt */ + SC1_IRQn = 59, /*!< Smart Card 1 Interrupt */ + SC2_IRQn = 60, /*!< Smart Card 2 Interrupt */ + SPI3_IRQn = 62, /*!< SPI3 Interrupt */ + SDH0_IRQn = 64, /*!< SDH0 Interrupt */ + I2S0_IRQn = 68, /*!< I2S0 Interrupt */ + CRPT_IRQn = 71, /*!< CRPT Interrupt */ + GPG_IRQn = 72, /*!< GPIO Port G Interrupt */ + EINT6_IRQn = 73, /*!< External Input 6 Interrupt */ + UART4_IRQn = 74, /*!< UART4 Interrupt */ + UART5_IRQn = 75, /*!< UART5 Interrupt */ + USCI0_IRQn = 76, /*!< USCI0 Interrupt */ + USCI1_IRQn = 77, /*!< USCI1 Interrupt */ + BPWM0_IRQn = 78, /*!< BPWM0 Interrupt */ + BPWM1_IRQn = 79, /*!< BPWM1 Interrupt */ + I2C2_IRQn = 82, /*!< I2C2 Interrupt */ + QEI0_IRQn = 84, /*!< QEI0 Interrupt */ + QEI1_IRQn = 85, /*!< QEI1 Interrupt */ + ECAP0_IRQn = 86, /*!< ECAP0 Interrupt */ + ECAP1_IRQn = 87, /*!< ECAP1 Interrupt */ + GPH_IRQn = 88, /*!< GPIO Port H Interrupt */ + EINT7_IRQn = 89, /*!< External Input 7 Interrupt */ + PDMA1_IRQn = 98, /*!< Peripheral DMA 1 Interrupt */ + SCU_IRQn = 99, /*!< SCU Interrupt */ + LCD_IRQn = 100, /*!< LCD interrupt */ + TRNG_IRQn = 101, /*!< TRNG interrupt */ + KS_IRQn = 109, /*!< Key Store interrupt */ + TAMPER_IRQn = 110, /*!< TAMPER interrupt */ + EWDT_IRQn = 111, /*!< Extra Watchdog Timer interrupt */ + EWWDT_IRQn = 112, /*!< Extra Window Watchdog Timer interrupt */ + NS_ISP_IRQn = 113, /*!< Non-secure FMC ISP interrupt */ + TMR4_IRQn = 114, /*!< Timer 4 Interrupt */ + TMR5_IRQn = 115, /*!< Timer 5 Interrupt */ + + +} IRQn_Type; + + +/* ================================================================================ */ +/* ================ Processor and Core Peripheral Section ================ */ +/* ================================================================================ */ + +/* ------- Start of section using anonymous unions and disabling warnings ------- */ +#if defined (__CC_ARM) +#pragma push +#pragma anon_unions +#elif defined (__ICCARM__) +#pragma language=extended +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) +#pragma clang diagnostic push +#pragma clang diagnostic ignored "-Wc11-extensions" +#pragma clang diagnostic ignored "-Wreserved-id-macro" +#elif defined (__GNUC__) +/* anonymous unions are enabled by default */ +#elif defined (__TMS470__) +/* anonymous unions are enabled by default */ +#elif defined (__TASKING__) +#pragma warning 586 +#elif defined (__CSMC__) +/* anonymous unions are enabled by default */ +#else +#warning Not supported compiler type +#endif + + +/* -------- Configuration of the Cortex-ARMv8MBL Processor and Core Peripherals ------- */ +#define __ARMv8MBL_REV 0x0000U /* Core revision r0p0 */ +#define __SAU_PRESENT 1U /* SAU present */ +#define __SAUREGION_PRESENT 1U /* SAU present */ +#define __MPU_PRESENT 1U /* MPU present */ +#define __VTOR_PRESENT 1U /* VTOR present */ +#define __NVIC_PRIO_BITS 2U /* Number of Bits used for Priority Levels */ +#define __Vendor_SysTickConfig 0U /* Set to 1 if different SysTick Config is used */ +#define USE_ASSERT 0U /* Define to use Assert function or not */ + +/**@}*/ /* end of group CMSIS */ + +#include "core_armv8mbl.h" /* Processor and core peripherals */ +#include "system_M2354.h" /* System Header */ +#include "nu_partition_M2354.h" + +/** + * Initialize the system clock + * + * @brief Setup the micro controller system + * Initialize the PLL and update the SystemFrequency variable + */ +extern void SystemInit(void); + + +/******************************************************************************/ +/* Device Specific Peripheral registers structures */ +/******************************************************************************/ + + +#include "acmp_reg.h" +#include "bpwm_reg.h" +#include "can_reg.h" +#include "clk_reg.h" +#include "crc_reg.h" +#include "dac_reg.h" +#include "eadc_reg.h" +#include "ebi_reg.h" +#include "ecap_reg.h" +#include "fmc_reg.h" +#include "gpio_reg.h" +#include "hdiv_reg.h" +#include "i2c_reg.h" +#include "i2s_reg.h" +#include "pdma_reg.h" +#include "epwm_reg.h" +#include "qei_reg.h" +#include "rtc_reg.h" +#include "sc_reg.h" +#include "scu_reg.h" +#include "sdh_reg.h" +#include "qspi_reg.h" +#include "spi_reg.h" +#include "sys_reg.h" +#include "timer_reg.h" +#include "trng_reg.h" +#include "uart_reg.h" +#include "ui2c_reg.h" +#include "usbh_reg.h" +#include "usbd_reg.h" +#include "otg_reg.h" +#include "crpt_reg.h" +#include "uspi_reg.h" +#include "uuart_reg.h" +#include "wdt_reg.h" +#include "wwdt_reg.h" +#include "keystore_reg.h" +#include "tamper_reg.h" +#include "lcd_reg.h" +#include "ewdt_reg.h" +#include "ewwdt_reg.h" + + + +/******************************************************************************/ +/* Peripheral memory map */ +/******************************************************************************/ +/** @addtogroup PERIPHERAL_BASE Peripheral Memory Base + Memory Mapped Structure for Series Peripheral + @{ + */ + + +/* Peripheral and SRAM base address */ +#define SRAM_BASE (0x20000000UL) /*!< (SRAM ) Base Address */ +#define PERIPH_BASE (0x40000000UL) /*!< (Peripheral) Base Address */ +#define NS_OFFSET (0x10000000UL) + +/* Peripheral memory map */ +#define AHBPERIPH_BASE PERIPH_BASE +#define APBPERIPH_BASE (PERIPH_BASE + 0x00040000UL) + +/*!< AHB peripherals */ +#define SYS_BASE (AHBPERIPH_BASE + 0x00000UL) +#define CLK_BASE (AHBPERIPH_BASE + 0x00200UL) +#define INT_BASE (AHBPERIPH_BASE + 0x00300UL) +#define GPIO_BASE (AHBPERIPH_BASE + 0x04000UL) +#define GPIOA_BASE (AHBPERIPH_BASE + 0x04000UL) +#define GPIOB_BASE (AHBPERIPH_BASE + 0x04040UL) +#define GPIOC_BASE (AHBPERIPH_BASE + 0x04080UL) +#define GPIOD_BASE (AHBPERIPH_BASE + 0x040C0UL) +#define GPIOE_BASE (AHBPERIPH_BASE + 0x04100UL) +#define GPIOF_BASE (AHBPERIPH_BASE + 0x04140UL) +#define GPIOG_BASE (AHBPERIPH_BASE + 0x04180UL) +#define GPIOH_BASE (AHBPERIPH_BASE + 0x041C0UL) +#define GPIO_DBCTL_BASE (AHBPERIPH_BASE + 0x04440UL) +#define GPIO_PIN_DATA_BASE (AHBPERIPH_BASE + 0x04800UL) +#define PDMA0_BASE (AHBPERIPH_BASE + 0x08000UL) +#define PDMA1_BASE (AHBPERIPH_BASE + 0x18000UL) +#define USBH_BASE (AHBPERIPH_BASE + 0x09000UL) +#define FMC_BASE (AHBPERIPH_BASE + 0x0C000UL) +#define SDH0_BASE (AHBPERIPH_BASE + 0x0D000UL) +#define SDH1_BASE (AHBPERIPH_BASE + 0x0E000UL) +#define EBI_BASE (AHBPERIPH_BASE + 0x10000UL) +#define CRC_BASE (AHBPERIPH_BASE + 0x31000UL) +#define CRPT_BASE (AHBPERIPH_BASE + 0x32000UL) +#define SCU_BASE (AHBPERIPH_BASE + 0x2F000UL) +#define FVC_BASE (AHBPERIPH_BASE + 0x2F500UL) +#define DPM_BASE (AHBPERIPH_BASE + 0x2F600UL) +#define PLM_BASE (AHBPERIPH_BASE + 0x2F700UL) + +#define BTF_BASE (AHBPERIPH_BASE + 0x2F800UL) + +/*!< APB peripherals */ +#define WDT_BASE (APBPERIPH_BASE + 0x00000UL) +#define WWDT_BASE (APBPERIPH_BASE + 0x00100UL) +#define RTC_BASE (APBPERIPH_BASE + 0x01000UL) +#define EADC_BASE (APBPERIPH_BASE + 0x03000UL) +#define ACMP01_BASE (APBPERIPH_BASE + 0x05000UL) +#define DAC0_BASE (APBPERIPH_BASE + 0x07000UL) +#define DAC1_BASE (APBPERIPH_BASE + 0x07040UL) +#define I2S0_BASE (APBPERIPH_BASE + 0x08000UL) +#define OTG_BASE (APBPERIPH_BASE + 0x0D000UL) +#define TMR01_BASE (APBPERIPH_BASE + 0x10000UL) +#define TMR23_BASE (APBPERIPH_BASE + 0x11000UL) +#define TMR45_BASE (APBPERIPH_BASE + 0x12000UL) +#define EPWM0_BASE (APBPERIPH_BASE + 0x18000UL) +#define EPWM1_BASE (APBPERIPH_BASE + 0x19000UL) +#define BPWM0_BASE (APBPERIPH_BASE + 0x1A000UL) +#define BPWM1_BASE (APBPERIPH_BASE + 0x1B000UL) +#define QSPI0_BASE (APBPERIPH_BASE + 0x20000UL) +#define SPI0_BASE (APBPERIPH_BASE + 0x21000UL) +#define SPI1_BASE (APBPERIPH_BASE + 0x22000UL) +#define SPI2_BASE (APBPERIPH_BASE + 0x23000UL) +#define SPI3_BASE (APBPERIPH_BASE + 0x24000UL) +#define UART0_BASE (APBPERIPH_BASE + 0x30000UL) +#define UART0_BASE (APBPERIPH_BASE + 0x30000UL) +#define UART1_BASE (APBPERIPH_BASE + 0x31000UL) +#define UART2_BASE (APBPERIPH_BASE + 0x32000UL) +#define UART3_BASE (APBPERIPH_BASE + 0x33000UL) +#define UART4_BASE (APBPERIPH_BASE + 0x34000UL) +#define UART5_BASE (APBPERIPH_BASE + 0x35000UL) +#define I2C0_BASE (APBPERIPH_BASE + 0x40000UL) +#define I2C1_BASE (APBPERIPH_BASE + 0x41000UL) +#define I2C2_BASE (APBPERIPH_BASE + 0x42000UL) +#define SC0_BASE (APBPERIPH_BASE + 0x50000UL) +#define SC1_BASE (APBPERIPH_BASE + 0x51000UL) +#define SC2_BASE (APBPERIPH_BASE + 0x52000UL) +#define CAN0_BASE (APBPERIPH_BASE + 0x60000UL) +#define QEI0_BASE (APBPERIPH_BASE + 0x70000UL) +#define QEI1_BASE (APBPERIPH_BASE + 0x71000UL) +#define ECAP0_BASE (APBPERIPH_BASE + 0x74000UL) +#define ECAP1_BASE (APBPERIPH_BASE + 0x75000UL) +#define TRNG_BASE (APBPERIPH_BASE + 0x79000UL) +#define USBD_BASE (APBPERIPH_BASE + 0x80000UL) +#define USCI0_BASE (APBPERIPH_BASE + 0x90000UL) +#define USCI1_BASE (APBPERIPH_BASE + 0x91000UL) + +#define EWDT_BASE (APBPERIPH_BASE + 0x02000UL) +#define EWWDT_BASE (APBPERIPH_BASE + 0x02100UL) + + +#define KS_BASE (AHBPERIPH_BASE + 0x35000UL) +#define TAMPER_BASE (AHBPERIPH_BASE + 0xBD000UL) +#define LCD_BASE (AHBPERIPH_BASE + 0xBB000UL) + + + +/**@}*/ /* PERIPHERAL */ + +/******************************************************************************/ +/* Peripheral declaration */ +/******************************************************************************/ + +/** @addtogroup PMODULE Peripheral Pointer + The Declaration of Peripheral Pointer + @{ + */ + +/** @addtogroup PMODULE_S Secure Peripheral Pointer + The Declaration of Secure Peripheral Pointer + @{ +*/ + +#define PA_S ((GPIO_T *) GPIOA_BASE) /*!< GPIO PORTA Pointer */ +#define PB_S ((GPIO_T *) GPIOB_BASE) /*!< GPIO PORTB Pointer */ +#define PC_S ((GPIO_T *) GPIOC_BASE) /*!< GPIO PORTC Pointer */ +#define PD_S ((GPIO_T *) GPIOD_BASE) /*!< GPIO PORTD Pointer */ +#define PE_S ((GPIO_T *) GPIOE_BASE) /*!< GPIO PORTE Pointer */ +#define PF_S ((GPIO_T *) GPIOF_BASE) /*!< GPIO PORTF Pointer */ +#define PG_S ((GPIO_T *) GPIOG_BASE) /*!< GPIO PORTG Pointer */ +#define PH_S ((GPIO_T *) GPIOH_BASE) /*!< GPIO PORTH Pointer */ + +#define UART0_S ((UART_T *) UART0_BASE) /*!< UART0 Pointer */ +#define UART1_S ((UART_T *) UART1_BASE) /*!< UART1 Pointer */ +#define UART2_S ((UART_T *) UART2_BASE) /*!< UART2 Pointer */ +#define UART3_S ((UART_T *) UART3_BASE) /*!< UART3 Pointer */ +#define UART4_S ((UART_T *) UART4_BASE) /*!< UART4 Pointer */ +#define UART5_S ((UART_T *) UART5_BASE) /*!< UART5 Pointer */ + + +#define TIMER0_S ((TIMER_T *) TMR01_BASE) /*!< TIMER0 Pointer */ +#define TIMER1_S ((TIMER_T *) (TMR01_BASE + 0x100UL)) /*!< TIMER1 Pointer */ +#define TIMER2_S ((TIMER_T *) TMR23_BASE) /*!< TIMER2 Pointer */ +#define TIMER3_S ((TIMER_T *) (TMR23_BASE + 0x100UL)) /*!< TIMER3 Pointer */ +#define TIMER4_S ((TIMER_T *) TMR45_BASE) /*!< TIMER4 Pointer */ +#define TIMER5_S ((TIMER_T *) (TMR45_BASE + 0x100UL)) /*!< TIMER5 Pointer */ + +#define WDT_S ((WDT_T *) WDT_BASE) /*!< Watch Dog Timer Pointer */ + +#define WWDT_S ((WWDT_T *) WWDT_BASE) /*!< Window Watch Dog Timer Pointer */ + +#define QSPI0_S ((QSPI_T *) QSPI0_BASE) /*!< QSPI0 Pointer */ +#define SPI0_S ((SPI_T *) SPI0_BASE) /*!< SPI0 Pointer */ +#define SPI1_S ((SPI_T *) SPI1_BASE) /*!< SPI1 Pointer */ +#define SPI2_S ((SPI_T *) SPI2_BASE) /*!< SPI2 Pointer */ +#define SPI3_S ((SPI_T *) SPI3_BASE) /*!< SPI3 Pointer */ + +#define I2S0_S ((I2S_T *) I2S0_BASE) /*!< I2S0 Pointer */ + +#define I2C0_S ((I2C_T *) I2C0_BASE) /*!< I2C0 Pointer */ +#define I2C1_S ((I2C_T *) I2C1_BASE) /*!< I2C1 Pointer */ +#define I2C2_S ((I2C_T *) I2C2_BASE) /*!< I2C1 Pointer */ + +#define QEI0_S ((QEI_T *) QEI0_BASE) /*!< QEI0 Pointer */ +#define QEI1_S ((QEI_T *) QEI1_BASE) /*!< QEI1 Pointer */ + +#define RTC_S ((RTC_T *) RTC_BASE) /*!< RTC Pointer */ + +#define ACMP01_S ((ACMP_T *) ACMP01_BASE) /*!< ACMP01 Pointer */ + +#define CLK_S ((CLK_T *) CLK_BASE) /*!< System Clock Controller Pointer */ + +#define DAC0_S ((DAC_T *) DAC0_BASE) /*!< DAC0 Pointer */ +#define DAC1_S ((DAC_T *) DAC1_BASE) /*!< DAC1 Pointer */ + +#define EADC_S ((EADC_T *) EADC_BASE) /*!< EADC Pointer */ + +#define SYS_S ((SYS_T *) SYS_BASE) /*!< System Global Controller Pointer */ + +#define SYSINT_S ((SYS_INT_T *) INT_BASE) /*!< Interrupt Source Controller Pointer */ + +#define FMC_S ((FMC_T *) FMC_BASE) /*!< Flash Memory Controller */ + +#define SDH0_S ((SDH_T *) SDH0_BASE) + +#define CRPT_S ((CRPT_T *) CRPT_BASE) /*!< Crypto Accelerator Pointer */ +#define TRNG_S ((TRNG_T *)TRNG_BASE) /*!< True Random Number Pointer */ + +#define BPWM0_S ((BPWM_T *) BPWM0_BASE) /*!< BPWM0 Pointer */ +#define BPWM1_S ((BPWM_T *) BPWM1_BASE) /*!< BPWM1 Pointer */ + +#define EPWM0_S ((EPWM_T *) EPWM0_BASE) /*!< EPWM0 Pointer */ +#define EPWM1_S ((EPWM_T *) EPWM1_BASE) /*!< EPWM1 Pointer */ + +#define SC0_S ((SC_T *) SC0_BASE) /*!< SC0 Pointer */ +#define SC1_S ((SC_T *) SC1_BASE) /*!< SC1 Pointer */ +#define SC2_S ((SC_T *) SC2_BASE) /*!< SC2 Pointer */ + +#define EBI_S ((EBI_T *) EBI_BASE) /*!< EBI Pointer */ + +#define CRC_S ((CRC_T *) CRC_BASE) /*!< CRC Pointer */ + +#define USBD_S ((USBD_T *) USBD_BASE) /*!< USB Device Pointer */ +#define USBH_S ((USBH_T *) USBH_BASE) /*!< USBH Pointer */ +#define OTG_S ((OTG_T *) OTG_BASE) /*!< OTG Pointer */ + +#define PDMA0_S ((PDMA_T *) PDMA0_BASE) /*!< PDMA0 Pointer */ +#define PDMA1_S ((PDMA_T *) PDMA1_BASE) /*!< PDMA1 Pointer */ + +#define UI2C0_S ((UI2C_T *) USCI0_BASE) /*!< UI2C0 Pointer */ +#define UI2C1_S ((UI2C_T *) USCI1_BASE) /*!< UI2C1 Pointer */ + +#define USPI0_S ((USPI_T *) USCI0_BASE) /*!< USPI0 Pointer */ +#define USPI1_S ((USPI_T *) USCI1_BASE) /*!< USPI1 Pointer */ + +#define UUART0_S ((UUART_T *) USCI0_BASE) /*!< UUART0 Pointer */ +#define UUART1_S ((UUART_T *) USCI1_BASE) /*!< UUART1 Pointer */ + +#define SCU_S ((SCU_T *) SCU_BASE) /*!< SCU Pointer */ +#define ECAP0_S ((ECAP_T *) ECAP0_BASE) /*!< ECAP0 Pointer */ +#define ECAP1_S ((ECAP_T *) ECAP1_BASE) /*!< ECAP1 Pointer */ + +#define CAN0_S ((CAN_T *)CAN0_BASE) /*!< CAN0 Pointer */ + +#define KS_S ((KS_T *)KS_BASE) /*!< Key Store Pointer */ +#define TAMPER_S ((TAMPER_T *)TAMPER_BASE) /*!< TAMPER Pointer */ +#define LCD_S ((LCD_T *)LCD_BASE) /*!< LCD Pointer */ + +#define EWDT_S ((EWDT_T *) EWDT_BASE) /*!< Extra Watch Dog Timer Pointer */ + +#define EWWDT_S ((EWWDT_T *) EWWDT_BASE) /*!< Extra Window Watch Dog Timer Pointer*/ + +#define FVC_S ((FVC_T *) FVC_BASE) +#define DPM_S ((DPM_T *) DPM_BASE) +#define PLM_S ((PLM_T *) PLM_BASE) + + + +/**@}*/ /* end of group PMODULE_S */ + +/** @addtogroup PMODULE_NS Non-secure Peripheral Pointer + The Declaration of Non-secure Peripheral Pointer + @{ +*/ + + +#define PA_NS ((GPIO_T *) (GPIOA_BASE+NS_OFFSET)) /*!< GPIO PORTA Pointer */ +#define PB_NS ((GPIO_T *) (GPIOB_BASE+NS_OFFSET)) /*!< GPIO PORTB Pointer */ +#define PC_NS ((GPIO_T *) (GPIOC_BASE+NS_OFFSET)) /*!< GPIO PORTC Pointer */ +#define PD_NS ((GPIO_T *) (GPIOD_BASE+NS_OFFSET)) /*!< GPIO PORTD Pointer */ +#define PE_NS ((GPIO_T *) (GPIOE_BASE+NS_OFFSET)) /*!< GPIO PORTE Pointer */ +#define PF_NS ((GPIO_T *) (GPIOF_BASE+NS_OFFSET)) /*!< GPIO PORTF Pointer */ +#define PG_NS ((GPIO_T *) (GPIOG_BASE+NS_OFFSET)) /*!< GPIO PORTG Pointer */ +#define PH_NS ((GPIO_T *) (GPIOH_BASE+NS_OFFSET)) /*!< GPIO PORTH Pointer */ +#define UART0_NS ((UART_T *) (UART0_BASE+NS_OFFSET)) /*!< UART0 Pointer */ +#define UART1_NS ((UART_T *) (UART1_BASE+NS_OFFSET)) /*!< UART1 Pointer */ +#define UART2_NS ((UART_T *) (UART2_BASE+NS_OFFSET)) /*!< UART2 Pointer */ +#define UART3_NS ((UART_T *) (UART3_BASE+NS_OFFSET)) /*!< UART3 Pointer */ +#define UART4_NS ((UART_T *) (UART4_BASE+NS_OFFSET)) /*!< UART4 Pointer */ +#define UART5_NS ((UART_T *) (UART5_BASE+NS_OFFSET)) /*!< UART5 Pointer */ +#define TIMER2_NS ((TIMER_T *) (TMR23_BASE+NS_OFFSET)) /*!< TIMER2 Pointer */ +#define TIMER3_NS ((TIMER_T *) (TMR23_BASE+NS_OFFSET+0x100UL)) /*!< TIMER3 Pointer */ +#define TIMER4_NS ((TIMER_T *) (TMR45_BASE+NS_OFFSET)) /*!< TIMER4 Pointer */ +#define TIMER5_NS ((TIMER_T *) (TMR45_BASE+NS_OFFSET+0x100UL)) /*!< TIMER5 Pointer */ +#define QSPI0_NS ((QSPI_T *) (QSPI0_BASE+NS_OFFSET)) /*!< QSPI0 Pointer */ +#define SPI0_NS ((SPI_T *) (SPI0_BASE+NS_OFFSET)) /*!< SPI0 Pointer */ +#define SPI1_NS ((SPI_T *) (SPI1_BASE+NS_OFFSET)) /*!< SPI1 Pointer */ +#define SPI2_NS ((SPI_T *) (SPI2_BASE+NS_OFFSET)) /*!< SPI2 Pointer */ +#define SPI3_NS ((SPI_T *) (SPI3_BASE+NS_OFFSET)) /*!< SPI3 Pointer */ +#define I2S0_NS ((I2S_T *) (I2S0_BASE+NS_OFFSET)) /*!< I2S0 Pointer */ +#define I2C0_NS ((I2C_T *) (I2C0_BASE+NS_OFFSET)) /*!< I2C0 Pointer */ +#define I2C1_NS ((I2C_T *) (I2C1_BASE+NS_OFFSET)) /*!< I2C1 Pointer */ +#define I2C2_NS ((I2C_T *) (I2C2_BASE+NS_OFFSET)) /*!< I2C1 Pointer */ +#define QEI0_NS ((QEI_T *) (QEI0_BASE+NS_OFFSET)) /*!< QEI0 Pointer */ +#define QEI1_NS ((QEI_T *) (QEI1_BASE+NS_OFFSET)) /*!< QEI1 Pointer */ +#define ACMP01_NS ((ACMP_T *) (ACMP01_BASE+NS_OFFSET)) /*!< ACMP01 Pointer */ +#define DAC0_NS ((DAC_T *) (DAC0_BASE+NS_OFFSET)) /*!< DAC0 Pointer */ +#define DAC1_NS ((DAC_T *) (DAC1_BASE+NS_OFFSET)) /*!< DAC1 Pointer */ +#define EADC_NS ((EADC_T *) (EADC_BASE+NS_OFFSET)) /*!< EADC Pointer */ +#define SDH0_NS ((SDH_T *) (SDH0_BASE +NS_OFFSET)) +#define CRPT_NS ((CRPT_T *) (CRPT_BASE +NS_OFFSET)) +#define TRNG_NS ((TRNG_T *) (TRNG_BASE +NS_OFFSET)) /*!< Random Number Generator Pointer */ +#define BPWM0_NS ((BPWM_T *) (BPWM0_BASE+NS_OFFSET)) /*!< BPWM0 Pointer */ +#define BPWM1_NS ((BPWM_T *) (BPWM1_BASE+NS_OFFSET)) /*!< BPWM1 Pointer */ +#define EPWM0_NS ((EPWM_T *) (EPWM0_BASE+NS_OFFSET)) /*!< EPWM0 Pointer */ +#define EPWM1_NS ((EPWM_T *) (EPWM1_BASE+NS_OFFSET)) /*!< EPWM1 Pointer */ +#define SC0_NS ((SC_T *) (SC0_BASE +NS_OFFSET)) /*!< SC0 Pointer */ +#define SC1_NS ((SC_T *) (SC1_BASE +NS_OFFSET)) /*!< SC1 Pointer */ +#define SC2_NS ((SC_T *) (SC2_BASE +NS_OFFSET)) /*!< SC2 Pointer */ +#define EBI_NS ((EBI_T *) (EBI_BASE +NS_OFFSET)) /*!< EBI Pointer */ +#define CRC_NS ((CRC_T *) (CRC_BASE +NS_OFFSET)) /*!< CRC Pointer */ +#define USBD_NS ((USBD_T *) (USBD_BASE +NS_OFFSET)) /*!< USB Device Pointer */ +#define USBH_NS ((USBH_T *) (USBH_BASE +NS_OFFSET)) /*!< USBH Pointer */ +#define OTG_NS ((OTG_T *) (OTG_BASE +NS_OFFSET)) /*!< OTG Pointer */ +#define PDMA1_NS ((PDMA_T *) (PDMA1_BASE +NS_OFFSET)) /*!< PDMA1 Pointer */ +#define UI2C0_NS ((UI2C_T *) (USCI0_BASE +NS_OFFSET)) /*!< UI2C0 Pointer */ +#define UI2C1_NS ((UI2C_T *) (USCI1_BASE +NS_OFFSET)) /*!< UI2C1 Pointer */ +#define USPI0_NS ((USPI_T *) (USCI0_BASE +NS_OFFSET)) /*!< USPI0 Pointer */ +#define USPI1_NS ((USPI_T *) (USCI1_BASE +NS_OFFSET)) /*!< USPI1 Pointer */ +#define UUART0_NS ((UUART_T *) (USCI0_BASE+NS_OFFSET)) /*!< UUART0 Pointer */ +#define UUART1_NS ((UUART_T *) (USCI1_BASE+NS_OFFSET)) /*!< UUART1 Pointer */ +#define SCU_NS ((SCU_T *) (SCU_BASE +NS_OFFSET)) /*!< SCU Pointer */ +#define ECAP0_NS ((ECAP_T *) (ECAP0_BASE+NS_OFFSET)) /*!< ECAP0 Pointer */ +#define ECAP1_NS ((ECAP_T *) (ECAP1_BASE+NS_OFFSET)) /*!< ECAP1 Pointer */ +#define CAN0_NS ((CAN_T *) (CAN0_BASE +NS_OFFSET)) /*!< CAN0 Pointer */ + +#define EWDT_NS ((EWDT_T *) (EWDT_BASE+NS_OFFSET)) /*!< Extra Watch Dog Timer Pointer */ + +#define EWWDT_NS ((EWWDT_T *) (EWWDT_BASE+NS_OFFSET)) /*!< Extra Window Watch Dog Timer Pointer*/ + + +#define LCD_NS ((LCD_T *)(LCD_BASE+NS_OFFSET)) /*!< LCD Pointer */ +#define DPM_NS ((DPM_T *)(DPM_BASE+NS_OFFSET)) +#define FMC_NS ((FMC_T *)(FMC_BASE+NS_OFFSET)) /*!< Flash Memory Controller */ +#define SYS_NS ((SYS_T *)(SYS_BASE+NS_OFFSET)) +#define CLK_NS ((CLK_T *)(CLK_BASE+NS_OFFSET)) + + +/**@}*/ /* end of group PMODULE_NS */ + +/** @addtogroup PMODULE_SNS Peripheral Pointer + The Declaration of Peripheral Pointer + @{ +*/ + +/* Always Secure Modules */ +#define SYS SYS_S +#define SYSINT SYSINT_S +#define CLK CLK_S +#define FMC FMC_S +#define SCU SCU_S +#define FVC FVC_S +#define PLM PLM_S +#define DPM DPM_S +#define PDMA0 PDMA0_S +#define WDT WDT_S +#define WWDT WWDT_S +#define TIMER0 TIMER0_S +#define TIMER1 TIMER1_S +#define RTC RTC_S +#define KS KS_S +#define TAMPER TAMPER_S + +#if defined (SCU_INIT_PNSSET0_VAL) && (SCU_INIT_PNSSET0_VAL & BIT9 ) +# define USBH USBH_NS +#else +# define USBH USBH_S +#endif + +#if defined (SCU_INIT_PNSSET0_VAL) && (SCU_INIT_PNSSET0_VAL & BIT13) +# define SDH0 SDH0_NS +#else +# define SDH0 SDH0_S +#endif + +#if defined (SCU_INIT_PNSSET0_VAL) && (SCU_INIT_PNSSET0_VAL & BIT16) +# define EBI EBI_NS +#else +# define EBI EBI_S +#endif + + +#if defined (SCU_INIT_PNSSET0_VAL) && (SCU_INIT_PNSSET0_VAL & BIT24) +# define PDMA1 PDMA1_NS +#else +# define PDMA1 PDMA1_S +#endif + +#if defined (SCU_INIT_PNSSET1_VAL) && (SCU_INIT_PNSSET1_VAL & BIT17) +# define CRC CRC_NS +#else +# define CRC CRC_S +#endif + +#if defined (SCU_INIT_PNSSET1_VAL) && (SCU_INIT_PNSSET1_VAL & BIT18) +# define CRPT CRPT_NS +#else +# define CRPT CRPT_S +#endif + +#if defined (SCU_INIT_PNSSET2_VAL) && (SCU_INIT_PNSSET2_VAL & BIT2 ) +# define EWDT EWDT_NS +# define EWWDT EWWDT_NS +#else +# define EWDT EWDT_S +# define EWWDT EWWDT_S +#endif + +#if defined (SCU_INIT_PNSSET2_VAL) && (SCU_INIT_PNSSET2_VAL & BIT3 ) +# define EADC EADC_NS +#else +# define EADC EADC_S +#endif + +#if defined (SCU_INIT_PNSSET2_VAL) && (SCU_INIT_PNSSET2_VAL & BIT3 ) +# define EADC EADC_NS +#else +# define EADC EADC_S +#endif + +#if defined (SCU_INIT_PNSSET2_VAL) && (SCU_INIT_PNSSET2_VAL & BIT3 ) +# define EADC EADC_NS +#else +# define EADC EADC_S +#endif + +#if defined (SCU_INIT_PNSSET2_VAL) && (SCU_INIT_PNSSET2_VAL & BIT3 ) +# define EADC EADC_NS +#else +# define EADC EADC_S +#endif + +#if defined (SCU_INIT_PNSSET2_VAL) && (SCU_INIT_PNSSET2_VAL & BIT5 ) +# define ACMP01 ACMP01_NS +#else +# define ACMP01 ACMP01_S +#endif + +#if defined (SCU_INIT_PNSSET2_VAL) && (SCU_INIT_PNSSET2_VAL & BIT7 ) +# define DAC0 DAC0_NS +# define DAC1 DAC1_NS +#else +# define DAC0 DAC0_S +# define DAC1 DAC1_S +#endif + +#if defined (SCU_INIT_PNSSET2_VAL) && (SCU_INIT_PNSSET2_VAL & BIT8 ) +# define I2S0 I2S0_NS +#else +# define I2S0 I2S0_S +#endif + +#if defined (SCU_INIT_PNSSET2_VAL) && (SCU_INIT_PNSSET2_VAL & BIT13) +# define OTG OTG_NS +#else +# define OTG OTG_S +#endif + +#if defined (SCU_INIT_PNSSET2_VAL) && (SCU_INIT_PNSSET2_VAL & BIT17) +# define TIMER2 TIMER2_NS +# define TIMER3 TIMER3_NS +#else +# define TIMER2 TIMER2_S +# define TIMER3 TIMER3_S +#endif + +#if defined (SCU_INIT_PNSSET2_VAL) && (SCU_INIT_PNSSET2_VAL & BIT18) +# define TIMER4 TIMER4_NS +# define TIMER5 TIMER5_NS +#else +# define TIMER4 TIMER4_S +# define TIMER5 TIMER5_S +#endif + +#if defined (SCU_INIT_PNSSET2_VAL) && (SCU_INIT_PNSSET2_VAL & BIT24) +# define EPWM0 EPWM0_NS +#else +# define EPWM0 EPWM0_S +#endif + +#if defined (SCU_INIT_PNSSET2_VAL) && (SCU_INIT_PNSSET2_VAL & BIT24) +# define EPWM0 EPWM0_NS +#else +# define EPWM0 EPWM0_S +#endif + +#if defined (SCU_INIT_PNSSET2_VAL) && (SCU_INIT_PNSSET2_VAL & BIT24) +# define EPWM0 EPWM0_NS +#else +# define EPWM0 EPWM0_S +#endif + +#if defined (SCU_INIT_PNSSET2_VAL) && (SCU_INIT_PNSSET2_VAL & BIT25) +# define EPWM1 EPWM1_NS +#else +# define EPWM1 EPWM1_S +#endif + +#if defined (SCU_INIT_PNSSET2_VAL) && (SCU_INIT_PNSSET2_VAL & BIT25) +# define EPWM1 EPWM1_NS +#else +# define EPWM1 EPWM1_S +#endif + +#if defined (SCU_INIT_PNSSET2_VAL) && (SCU_INIT_PNSSET2_VAL & BIT25) +# define EPWM1 EPWM1_NS +#else +# define EPWM1 EPWM1_S +#endif + +#if defined (SCU_INIT_PNSSET2_VAL) && (SCU_INIT_PNSSET2_VAL & BIT26) +# define BPWM0 BPWM0_NS +#else +# define BPWM0 BPWM0_S +#endif + +#if defined (SCU_INIT_PNSSET2_VAL) && (SCU_INIT_PNSSET2_VAL & BIT27) +# define BPWM1 BPWM1_NS +#else +# define BPWM1 BPWM1_S +#endif + +#if defined (SCU_INIT_PNSSET3_VAL) && (SCU_INIT_PNSSET3_VAL & BIT0 ) +# define QSPI0 QSPI0_NS +#else +# define QSPI0 QSPI0_S +#endif + +#if defined (SCU_INIT_PNSSET3_VAL) && (SCU_INIT_PNSSET3_VAL & BIT1 ) +# define SPI0 SPI0_NS +#else +# define SPI0 SPI0_S +#endif + +#if defined (SCU_INIT_PNSSET3_VAL) && (SCU_INIT_PNSSET3_VAL & BIT2 ) +# define SPI1 SPI1_NS +#else +# define SPI1 SPI1_S +#endif + +#if defined (SCU_INIT_PNSSET3_VAL) && (SCU_INIT_PNSSET3_VAL & BIT3 ) +# define SPI2 SPI2_NS +#else +# define SPI2 SPI2_S +#endif + +#if defined (SCU_INIT_PNSSET3_VAL) && (SCU_INIT_PNSSET3_VAL & BIT4 ) +# define SPI3 SPI3_NS +#else +# define SPI3 SPI3_S +#endif + +#if defined (SCU_INIT_PNSSET3_VAL) && (SCU_INIT_PNSSET3_VAL & BIT16) +# define UART0 UART0_NS +#else +# define UART0 UART0_S +#endif + +#if defined (SCU_INIT_PNSSET3_VAL) && (SCU_INIT_PNSSET3_VAL & BIT17) +# define UART1 UART1_NS +#else +# define UART1 UART1_S +#endif + +#if defined (SCU_INIT_PNSSET3_VAL) && (SCU_INIT_PNSSET3_VAL & BIT18) +# define UART2 UART2_NS +#else +# define UART2 UART2_S +#endif + +#if defined (SCU_INIT_PNSSET3_VAL) && (SCU_INIT_PNSSET3_VAL & BIT19) +# define UART3 UART3_NS +#else +# define UART3 UART3_S +#endif + +#if defined (SCU_INIT_PNSSET3_VAL) && (SCU_INIT_PNSSET3_VAL & BIT20) +# define UART4 UART4_NS +#else +# define UART4 UART4_S +#endif + +#if defined (SCU_INIT_PNSSET3_VAL) && (SCU_INIT_PNSSET3_VAL & BIT21) +# define UART5 UART5_NS +#else +# define UART5 UART5_S +#endif + +#if defined (SCU_INIT_PNSSET4_VAL) && (SCU_INIT_PNSSET4_VAL & BIT0 ) +# define I2C0 I2C0_NS +#else +# define I2C0 I2C0_S +#endif + +#if defined (SCU_INIT_PNSSET4_VAL) && (SCU_INIT_PNSSET4_VAL & BIT1 ) +# define I2C1 I2C1_NS +#else +# define I2C1 I2C1_S +#endif + +#if defined (SCU_INIT_PNSSET4_VAL) && (SCU_INIT_PNSSET4_VAL & BIT2 ) +# define I2C2 I2C2_NS +#else +# define I2C2 I2C2_S +#endif + +#if defined (SCU_INIT_PNSSET4_VAL) && (SCU_INIT_PNSSET4_VAL & BIT16) +# define SC0 SC0_NS +#else +# define SC0 SC0_S +#endif + +#if defined (SCU_INIT_PNSSET4_VAL) && (SCU_INIT_PNSSET4_VAL & BIT17) +# define SC1 SC1_NS +#else +# define SC1 SC1_S +#endif + +#if defined (SCU_INIT_PNSSET4_VAL) && (SCU_INIT_PNSSET4_VAL & BIT18) +# define SC2 SC2_NS +#else +# define SC2 SC2_S +#endif + +#if defined (SCU_INIT_PNSSET5_VAL) && (SCU_INIT_PNSSET5_VAL & BIT0 ) +# define CAN0 CAN0_NS +#else +# define CAN0 CAN0_S +#endif + +#if defined (SCU_INIT_PNSSET5_VAL) && (SCU_INIT_PNSSET5_VAL & BIT16) +# define QEI0 QEI0_NS +#else +# define QEI0 QEI0_S +#endif + +#if defined (SCU_INIT_PNSSET5_VAL) && (SCU_INIT_PNSSET5_VAL & BIT17) +# define QEI1 QEI1_NS +#else +# define QEI1 QEI1_S +#endif + +#if defined (SCU_INIT_PNSSET5_VAL) && (SCU_INIT_PNSSET5_VAL & BIT20) +# define ECAP0 ECAP0_NS +#else +# define ECAP0 ECAP0_S +#endif + +#if defined (SCU_INIT_PNSSET5_VAL) && (SCU_INIT_PNSSET5_VAL & BIT21) +# define ECAP1 ECAP1_NS +#else +# define ECAP1 ECAP1_S +#endif + +#if defined (SCU_INIT_PNSSET5_VAL) && (SCU_INIT_PNSSET5_VAL & BIT25) +# define TRNG TRNG_NS +#else +# define TRNG TRNG_S +#endif + +#if defined (SCU_INIT_PNSSET5_VAL) && (SCU_INIT_PNSSET5_VAL & BIT27) +# define LCD LCD_NS +#else +# define LCD LCD_S +#endif + +#if defined (SCU_INIT_PNSSET6_VAL) && (SCU_INIT_PNSSET6_VAL & BIT0 ) +# define USBD USBD_NS +#else +# define USBD USBD_S +#endif + +#if defined (SCU_INIT_PNSSET6_VAL) && (SCU_INIT_PNSSET6_VAL & BIT16) +# define USCI0 USCI0_NS +# define UI2C0 UI2C0_NS +# define USPI0 USPI0_NS +# define UUART0 UUART0_NS + +#else +# define USCI0 USCI0_S +# define UI2C0 UI2C0_S +# define USPI0 USPI0_S +# define UUART0 UUART0_S + +#endif + +#if defined (SCU_INIT_PNSSET6_VAL) && (SCU_INIT_PNSSET6_VAL & BIT17) +# define USCI1 USCI1_NS +# define USPI1 USPI1_NS +# define UI2C1 UI2C1_NS +# define UUART1 UUART1_NS + +#else +# define USCI1 USCI1_S +# define USPI1 USPI1_S +# define UI2C1 UI2C1_S +# define UUART1 UUART1_S +#endif + +#define PA ( (__PC() & NS_OFFSET) ? PA_NS : PA_S) +#define PB ( (__PC() & NS_OFFSET) ? PB_NS : PB_S) +#define PC ( (__PC() & NS_OFFSET) ? PC_NS : PC_S) +#define PD ( (__PC() & NS_OFFSET) ? PD_NS : PD_S) +#define PE ( (__PC() & NS_OFFSET) ? PE_NS : PE_S) +#define PF ( (__PC() & NS_OFFSET) ? PF_NS : PF_S) +#define PG ( (__PC() & NS_OFFSET) ? PG_NS : PG_S) +#define PH ( (__PC() & NS_OFFSET) ? PH_NS : PH_S) + +/**@}*/ /* end of group PMODULE_SNS */ + +/**@}*/ /* end of group PMODULE */ + +/* -------------------- End of section using anonymous unions ------------------- */ +#if defined (__CC_ARM) +#pragma pop +#elif defined (__ICCARM__) +/* leave anonymous unions enabled */ +#elif (__ARMCC_VERSION >= 6010050) +#pragma clang diagnostic pop +#elif defined (__GNUC__) +/* anonymous unions are enabled by default */ +#elif defined (__TMS470__) +/* anonymous unions are enabled by default */ +#elif defined (__TASKING__) +#pragma warning restore +#elif defined (__CSMC__) +/* anonymous unions are enabled by default */ +#else +#warning Not supported compiler type +#endif + +#ifdef __cplusplus +} +#endif + + + +/******************************************************************************/ +/* Peripheral header files */ +/******************************************************************************/ +#include "nu_sys.h" +#include "nu_clk.h" +#include "nu_dac.h" +#include "nu_eadc.h" +#include "nu_ebi.h" +#include "nu_ecap.h" +#include "nu_fmc.h" +#include "nu_gpio.h" +#include "nu_i2c.h" +#include "nu_i2s.h" +#include "nu_bpwm.h" +#include "nu_epwm.h" +#include "nu_qspi.h" +#include "nu_spi.h" +#include "nu_timer.h" +#include "nu_timer_pwm.h" +#include "nu_wdt.h" +#include "nu_wwdt.h" +#include "nu_rtc.h" +#include "nu_uart.h" +#include "nu_acmp.h" +#include "nu_crc.h" +#include "nu_usbd.h" +#include "nu_otg.h" +#include "nu_pdma.h" +#include "nu_ebi.h" +#include "nu_keystore.h" +#include "nu_crypto.h" +#include "nu_sc.h" +#include "nu_scuart.h" +#include "nu_usci_spi.h" +#include "nu_usci_uart.h" +#include "nu_usci_i2c.h" +#include "nu_sdh.h" +#include "nu_qei.h" +#include "nu_can.h" +#include "nu_scu.h" +#include "nu_tamper.h" +#include "nu_rng.h" +#include "nu_dpm.h" +#include "nu_fvc.h" +#include "nu_ewwdt.h" +#include "nu_ewdt.h" +#include "nu_plm.h" +#include "nu_lcd.h" + +#endif /* __M2354_H__ */ + diff --git a/Ubiquitous/XiZi/board/nuvoton-m2354/third_party_driver/include/Regs/NuMicro.h b/Ubiquitous/XiZi/board/nuvoton-m2354/third_party_driver/include/Regs/NuMicro.h new file mode 100644 index 0000000..cccccd4 --- /dev/null +++ b/Ubiquitous/XiZi/board/nuvoton-m2354/third_party_driver/include/Regs/NuMicro.h @@ -0,0 +1,17 @@ +/**************************************************************************//** + * @file NuMicro.h + * @version V1.00 + * @brief NuMicro peripheral access layer header file. + * + * @copyright SPDX-License-Identifier: Apache-2.0 + * @copyright Copyright (C) 2020 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ +#ifndef __NUMICRO_H__ +#define __NUMICRO_H__ + +#include "nutool_clkcfg.h" +#include "M2354.h" + +#endif /* __NUMICRO_H__ */ + + diff --git a/Ubiquitous/XiZi/board/nuvoton-m2354/third_party_driver/include/Regs/acmp_reg.h b/Ubiquitous/XiZi/board/nuvoton-m2354/third_party_driver/include/Regs/acmp_reg.h new file mode 100644 index 0000000..5d110ac --- /dev/null +++ b/Ubiquitous/XiZi/board/nuvoton-m2354/third_party_driver/include/Regs/acmp_reg.h @@ -0,0 +1,244 @@ +/**************************************************************************//** + * @file acmp_reg.h + * @version V1.00 + * @brief ACMP register definition header file + * + * @copyright SPDX-License-Identifier: Apache-2.0 + * @copyright Copyright (C) 2020 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ +#ifndef __ACMP_REG_H__ +#define __ACMP_REG_H__ + +/** @addtogroup REGISTER Control Register + + @{ + +*/ + + +/*---------------------- Analog Comparator Controller -------------------------*/ +/** + @addtogroup ACMP Analog Comparator Controller(ACMP) + Memory Mapped Structure for ACMP Controller + @{ +*/ + +typedef struct +{ + + + /** + * @var ACMP_T::CTL + * Offset: 0x00 Analog Comparator 0 Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |ACMPEN |Comparator Enable Bit + * | | |0 = Comparator 0 Disabled. + * | | |1 = Comparator 0 Enabled. + * |[1] |ACMPIE |Comparator Interrupt Enable Bit + * | | |0 = Comparator 0 interrupt Disabled. + * | | |1 = Comparator 0 interrupt Enabled. + * | | |If WKEN (ACMP_CTL0[16]) is set to 1, the wake-up interrupt function will be enabled as well. + * |[2] |HYSEN |Comparator Hysteresis Enable Bit + * | | |0 = Comparator 0 hysteresis Disabled. + * | | |1 = Comparator 0 hysteresis Enabled. + * | | |Note: If HYSEN = 0, user can adjust HYS by HYSSEL. + * | | |Note: If HYSEN = 1, HYSSEL is invalid. The Hysteresis is fixed to 30mV. + * |[3] |ACMPOINV |Comparator Output Inverse + * | | |0 = Comparator 0 output inverse Disabled. + * | | |1 = Comparator 0 output inverse Enabled. + * |[5:4] |NEGSEL |Comparator Negative Input Selection + * | | |00 = ACMP0_N pin. + * | | |01 = Internal comparator reference voltage (CRV). + * | | |10 = Band-gap voltage. + * | | |11 = DAC output. + * |[7:6] |POSSEL |Comparator Positive Input Selection + * | | |00 = Input from ACMP0_P0. + * | | |01 = Input from ACMP0_P1. + * | | |10 = Input from ACMP0_P2. + * | | |11 = Input from ACMP0_P3. + * |[9:8] |INTPOL |Interrupt Condition Polarity Selection + * | | |ACMPIF0 will be set to 1 when comparator output edge condition is detected. + * | | |00 = Rising edge or falling edge. + * | | |01 = Rising edge. + * | | |10 = Falling edge. + * | | |11 = Reserved. + * |[12] |OUTSEL |Comparator Output Select + * | | |0 = Comparator 0 output to ACMP0_O pin is unfiltered comparator output. + * | | |1 = Comparator 0 output to ACMP0_O pin is from filter output. + * |[15:13] |FILTSEL |Comparator Output Filter Count Selection + * | | |000 = Filter function is Disabled. + * | | |001 = ACMP0 output is sampled 1 consecutive PCLK. + * | | |010 = ACMP0 output is sampled 2 consecutive PCLKs. + * | | |011 = ACMP0 output is sampled 4 consecutive PCLKs. + * | | |100 = ACMP0 output is sampled 8 consecutive PCLKs. + * | | |101 = ACMP0 output is sampled 16 consecutive PCLKs. + * | | |110 = ACMP0 output is sampled 32 consecutive PCLKs. + * | | |111 = ACMP0 output is sampled 64 consecutive PCLKs. + * |[16] |WKEN |Power-down Wake-up Enable Bit + * | | |0 = Wake-up function Disabled. + * | | |1 = Wake-up function Enabled. + * |[17] |WLATEN |Window Latch Mode Enable Bit + * | | |0 = Window Latch Mode Disabled. + * | | |1 = Window Latch Mode Enabled. + * |[18] |WCMPSEL |Window Compare Mode Selection + * | | |0 = Window Compare Mode Disabled. + * | | |1 = Window Compare Mode is Selected. + * |[25:24] |HYSSEL |Hysteresis Mode Selection + * | | |00 = Hysteresis is 0mV. + * | | |01 = Hysteresis is 10mV. + * | | |10 = Hysteresis is 20mV. + * | | |11 = Hysteresis is 30mV. + * |[29:28] |MODESEL |Propagation Delay Mode Selection + * | | |00 = Max propagation delay is 4.5uS, operation current is 1.2uA. + * | | |01 = Max propagation delay is 2uS, operation current is 3uA. + * | | |10 = Max propagation delay is 600nS, operation current is 10uA. + * | | |11 = Max propagation delay is 200nS, operation current is 75uA. + * @var ACMP_T::STATUS + * Offset: 0x08 Analog Comparator Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |ACMPIF0 |Comparator 0 Interrupt Flag + * | | |This bit is set by hardware when the edge condition defined by INTPOL (ACMP_CTL0[9:8]) is detected on comparator 0 output + * | | |This will generate an interrupt if ACMPIE (ACMP_CTL0[1]) is set to 1. + * | | |Note: Write 1 to clear this bit to 0. + * |[1] |ACMPIF1 |Comparator 1 Interrupt Flag + * | | |This bit is set by hardware when the edge condition defined by INTPOL (ACMP_CTL1[9:8]) is detected on comparator 1 output + * | | |This will cause an interrupt if ACMPIE (ACMP_CTL1[1]) is set to 1. + * | | |Note: Write 1 to clear this bit to 0. + * |[4] |ACMPO0 |Comparator 0 Output + * | | |Synchronized to the PCLK to allow reading by software + * | | |Cleared when the comparator 0 is disabled, i.e + * | | |ACMPEN (ACMP_CTL0[0]) is cleared to 0. + * |[5] |ACMPO1 |Comparator 1 Output + * | | |Synchronized to the PCLK to allow reading by software + * | | |Cleared when the comparator 1 is disabled, i.e + * | | |ACMPEN (ACMP_CTL1[0]) is cleared to 0. + * |[8] |WKIF0 |Comparator 0 Power-down Wake-up Interrupt Flag + * | | |This bit will be set to 1 when ACMP0 wake-up interrupt event occurs. + * | | |0 = No power-down wake-up occurred. + * | | |1 = Power-down wake-up occurred. + * | | |Note: Write 1 to clear this bit to 0. + * |[9] |WKIF1 |Comparator 1 Power-down Wake-up Interrupt Flag + * | | |This bit will be set to 1 when ACMP1 wake-up interrupt event occurs. + * | | |0 = No power-down wake-up occurred. + * | | |1 = Power-down wake-up occurred. + * | | |Note: Write 1 to clear this bit to 0. + * |[12] |ACMPS0 |Comparator 0 Status + * | | |Synchronized to the PCLK to allow reading by software + * | | |Cleared when the comparator 0 is disabled, i.e + * | | |ACMPEN (ACMP_CTL0[0]) is cleared to 0. + * |[13] |ACMPS1 |Comparator 1 Status + * | | |Synchronized to the PCLK to allow reading by software + * | | |Cleared when the comparator 1 is disabled, i.e + * | | |ACMPEN (ACMP_CTL1[0]) is cleared to 0. + * |[16] |ACMPWO |Comparator Window Output + * | | |This bit shows the output status of window compare mode + * | | |0 = The positive input voltage is outside the window. + * | | |1 = The positive input voltage is in the window. + * @var ACMP_T::VREF + * Offset: 0x0C Analog Comparator Reference Voltage Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[3:0] |CRVCTL |Comparator Reference Voltage Setting + * | | |CRV = CRV source voltage * (1/6+CRVCTL/24). + * |[6] |CRVSSEL |CRV Source Voltage Selection + * | | |0 = VDDA is selected as CRV source voltage. + * | | |1 = The reference voltage defined by SYS_VREFCTL register is selected as CRV source voltage. + */ + + __IO uint32_t CTL[2]; /*!< [0x0000~0x0004] Analog Comparator 0~1 Control Register */ + __IO uint32_t STATUS; /*!< [0x0008] Analog Comparator Status Register */ + __IO uint32_t VREF; /*!< [0x000c] Analog Comparator Reference Voltage Control Register */ + +} ACMP_T; + +/** + @addtogroup ACMP_CONST ACMP Bit Field Definition + Constant Definitions for ACMP Controller + @{ +*/ + +#define ACMP_CTL_ACMPEN_Pos (0) /*!< ACMP_T::CTL: ACMPEN Position */ +#define ACMP_CTL_ACMPEN_Msk (0x1ul << ACMP_CTL_ACMPEN_Pos) /*!< ACMP_T::CTL: ACMPEN Mask */ + +#define ACMP_CTL_ACMPIE_Pos (1) /*!< ACMP_T::CTL: ACMPIE Position */ +#define ACMP_CTL_ACMPIE_Msk (0x1ul << ACMP_CTL_ACMPIE_Pos) /*!< ACMP_T::CTL: ACMPIE Mask */ + +#define ACMP_CTL_HYSEN_Pos (2) /*!< ACMP_T::CTL: HYSEN Position */ +#define ACMP_CTL_HYSEN_Msk (0x1ul << ACMP_CTL_HYSEN_Pos) /*!< ACMP_T::CTL: HYSEN Mask */ + +#define ACMP_CTL_ACMPOINV_Pos (3) /*!< ACMP_T::CTL: ACMPOINV Position */ +#define ACMP_CTL_ACMPOINV_Msk (0x1ul << ACMP_CTL_ACMPOINV_Pos) /*!< ACMP_T::CTL: ACMPOINV Mask */ + +#define ACMP_CTL_NEGSEL_Pos (4) /*!< ACMP_T::CTL: NEGSEL Position */ +#define ACMP_CTL_NEGSEL_Msk (0x3ul << ACMP_CTL_NEGSEL_Pos) /*!< ACMP_T::CTL: NEGSEL Mask */ + +#define ACMP_CTL_POSSEL_Pos (6) /*!< ACMP_T::CTL: POSSEL Position */ +#define ACMP_CTL_POSSEL_Msk (0x3ul << ACMP_CTL_POSSEL_Pos) /*!< ACMP_T::CTL: POSSEL Mask */ + +#define ACMP_CTL_INTPOL_Pos (8) /*!< ACMP_T::CTL: INTPOL Position */ +#define ACMP_CTL_INTPOL_Msk (0x3ul << ACMP_CTL_INTPOL_Pos) /*!< ACMP_T::CTL: INTPOL Mask */ + +#define ACMP_CTL_OUTSEL_Pos (12) /*!< ACMP_T::CTL: OUTSEL Position */ +#define ACMP_CTL_OUTSEL_Msk (0x1ul << ACMP_CTL_OUTSEL_Pos) /*!< ACMP_T::CTL: OUTSEL Mask */ + +#define ACMP_CTL_FILTSEL_Pos (13) /*!< ACMP_T::CTL: FILTSEL Position */ +#define ACMP_CTL_FILTSEL_Msk (0x7ul << ACMP_CTL_FILTSEL_Pos) /*!< ACMP_T::CTL: FILTSEL Mask */ + +#define ACMP_CTL_WKEN_Pos (16) /*!< ACMP_T::CTL: WKEN Position */ +#define ACMP_CTL_WKEN_Msk (0x1ul << ACMP_CTL_WKEN_Pos) /*!< ACMP_T::CTL: WKEN Mask */ + +#define ACMP_CTL_WLATEN_Pos (17) /*!< ACMP_T::CTL: WLATEN Position */ +#define ACMP_CTL_WLATEN_Msk (0x1ul << ACMP_CTL_WLATEN_Pos) /*!< ACMP_T::CTL: WLATEN Mask */ + +#define ACMP_CTL_WCMPSEL_Pos (18) /*!< ACMP_T::CTL: WCMPSEL Position */ +#define ACMP_CTL_WCMPSEL_Msk (0x1ul << ACMP_CTL_WCMPSEL_Pos) /*!< ACMP_T::CTL: WCMPSEL Mask */ + +#define ACMP_CTL_HYSSEL_Pos (24) /*!< ACMP_T::CTL: HYSSEL Position */ +#define ACMP_CTL_HYSSEL_Msk (0x3ul << ACMP_CTL_HYSSEL_Pos) /*!< ACMP_T::CTL: HYSSEL Mask */ + +#define ACMP_CTL_MODESEL_Pos (28) /*!< ACMP_T::CTL: MODESEL Position */ +#define ACMP_CTL_MODESEL_Msk (0x3ul << ACMP_CTL_MODESEL_Pos) /*!< ACMP_T::CTL: MODESEL Mask */ + +#define ACMP_STATUS_ACMPIF0_Pos (0) /*!< ACMP_T::STATUS: ACMPIF0 Position */ +#define ACMP_STATUS_ACMPIF0_Msk (0x1ul << ACMP_STATUS_ACMPIF0_Pos) /*!< ACMP_T::STATUS: ACMPIF0 Mask */ + +#define ACMP_STATUS_ACMPIF1_Pos (1) /*!< ACMP_T::STATUS: ACMPIF1 Position */ +#define ACMP_STATUS_ACMPIF1_Msk (0x1ul << ACMP_STATUS_ACMPIF1_Pos) /*!< ACMP_T::STATUS: ACMPIF1 Mask */ + +#define ACMP_STATUS_ACMPO0_Pos (4) /*!< ACMP_T::STATUS: ACMPO0 Position */ +#define ACMP_STATUS_ACMPO0_Msk (0x1ul << ACMP_STATUS_ACMPO0_Pos) /*!< ACMP_T::STATUS: ACMPO0 Mask */ + +#define ACMP_STATUS_ACMPO1_Pos (5) /*!< ACMP_T::STATUS: ACMPO1 Position */ +#define ACMP_STATUS_ACMPO1_Msk (0x1ul << ACMP_STATUS_ACMPO1_Pos) /*!< ACMP_T::STATUS: ACMPO1 Mask */ + +#define ACMP_STATUS_WKIF0_Pos (8) /*!< ACMP_T::STATUS: WKIF0 Position */ +#define ACMP_STATUS_WKIF0_Msk (0x1ul << ACMP_STATUS_WKIF0_Pos) /*!< ACMP_T::STATUS: WKIF0 Mask */ + +#define ACMP_STATUS_WKIF1_Pos (9) /*!< ACMP_T::STATUS: WKIF1 Position */ +#define ACMP_STATUS_WKIF1_Msk (0x1ul << ACMP_STATUS_WKIF1_Pos) /*!< ACMP_T::STATUS: WKIF1 Mask */ + +#define ACMP_STATUS_ACMPS0_Pos (12) /*!< ACMP_T::STATUS: ACMPS0 Position */ +#define ACMP_STATUS_ACMPS0_Msk (0x1ul << ACMP_STATUS_ACMPS0_Pos) /*!< ACMP_T::STATUS: ACMPS0 Mask */ + +#define ACMP_STATUS_ACMPS1_Pos (13) /*!< ACMP_T::STATUS: ACMPS1 Position */ +#define ACMP_STATUS_ACMPS1_Msk (0x1ul << ACMP_STATUS_ACMPS1_Pos) /*!< ACMP_T::STATUS: ACMPS1 Mask */ + +#define ACMP_STATUS_ACMPWO_Pos (16) /*!< ACMP_T::STATUS: ACMPWO Position */ +#define ACMP_STATUS_ACMPWO_Msk (0x1ul << ACMP_STATUS_ACMPWO_Pos) /*!< ACMP_T::STATUS: ACMPWO Mask */ + +#define ACMP_VREF_CRVCTL_Pos (0) /*!< ACMP_T::VREF: CRVCTL Position */ +#define ACMP_VREF_CRVCTL_Msk (0xful << ACMP_VREF_CRVCTL_Pos) /*!< ACMP_T::VREF: CRVCTL Mask */ + +#define ACMP_VREF_CRVSSEL_Pos (6) /*!< ACMP_T::VREF: CRVSSEL Position */ +#define ACMP_VREF_CRVSSEL_Msk (0x1ul << ACMP_VREF_CRVSSEL_Pos) /*!< ACMP_T::VREF: CRVSSEL Mask */ + +/**@}*/ /* ACMP_CONST */ +/**@}*/ /* end of ACMP register group */ +/**@}*/ /* end of REGISTER group */ + +#endif /* __ACMP_REG_H__ */ diff --git a/Ubiquitous/XiZi/board/nuvoton-m2354/third_party_driver/include/Regs/bpwm_reg.h b/Ubiquitous/XiZi/board/nuvoton-m2354/third_party_driver/include/Regs/bpwm_reg.h new file mode 100644 index 0000000..14455bf --- /dev/null +++ b/Ubiquitous/XiZi/board/nuvoton-m2354/third_party_driver/include/Regs/bpwm_reg.h @@ -0,0 +1,1800 @@ +/**************************************************************************//** + * @file bpwm_reg.h + * @version V1.00 + * @brief BPWM register definition header file + * + * @copyright SPDX-License-Identifier: Apache-2.0 + * @copyright Copyright (C) 2020 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ +#ifndef __BPWM_REG_H__ +#define __BPWM_REG_H__ + +/** @addtogroup REGISTER Control Register + + @{ + +*/ + + +/*---------------------- Basic Pulse Width Modulation Controller -------------------------*/ +/** + @addtogroup BPWM Basic Pulse Width Modulation Controller(BPWM) + Memory Mapped Structure for BPWM Controller + @{ +*/ + +typedef struct +{ + /** + * @var BCAPDAT_T::RCAPDAT + * Offset: 0x20C BPWM Rising Capture Data Register 0~5 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |RCAPDAT |BPWM Rising Capture Data (Read Only) + * | | |When rising capture condition happened, the BPWM counter value will be saved in this register. + * @var BCAPDAT_T::FCAPDAT + * Offset: 0x210 BPWM Falling Capture Data Register 0~5 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |FCAPDAT |BPWM Falling Capture Data (Read Only) + * | | |When falling capture condition happened, the BPWM counter value will be saved in this register. + */ + __IO uint32_t RCAPDAT; /*!< [0x20C/0x214/0x21C/0x224/0x22C/0x234] BPWM Rising Capture Data Register 0~5 */ + __IO uint32_t FCAPDAT; /*!< [0x210/0x218/0x220/0x228/0x230/0x238] BPWM Falling Capture Data Register 0~5 */ +} BCAPDAT_T; + + +typedef struct +{ + /** + * @var BPWM_T::CTL0 + * Offset: 0x00 BPWM Control Register 0 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |CTRLD0 |Center Re-load + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |In up-down counter type, PERIOD will load to PBUF at the end point of each period + * | | |CMPDAT will load to CMPBUF at the center point of a period + * |[1] |CTRLD1 |Center Re-load + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |In up-down counter type, PERIOD will load to PBUF at the end point of each period + * | | |CMPDAT will load to CMPBUF at the center point of a period + * |[2] |CTRLD2 |Center Re-load + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |In up-down counter type, PERIOD will load to PBUF at the end point of each period + * | | |CMPDAT will load to CMPBUF at the center point of a period + * |[3] |CTRLD3 |Center Re-load + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |In up-down counter type, PERIOD will load to PBUF at the end point of each period + * | | |CMPDAT will load to CMPBUF at the center point of a period + * |[4] |CTRLD4 |Center Re-load + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |In up-down counter type, PERIOD will load to PBUF at the end point of each period + * | | |CMPDAT will load to CMPBUF at the center point of a period + * |[5] |CTRLD5 |Center Re-load + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |In up-down counter type, PERIOD will load to PBUF at the end point of each period + * | | |CMPDAT will load to CMPBUF at the center point of a period + * |[16] |IMMLDEN0 |Immediately Load Enable Bit(S) + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |0 = PERIOD will load to PBUF at the end point of each period + * | | |CMPDAT will load to CMPBUF at the end point or center point of each period by setting CTRLD bit. + * | | |1 = PERIOD/CMPDAT will load to PBUF and CMPBUF immediately when software update PERIOD/CMPDAT. + * | | |Note: If IMMLDENn is Enabled, WINLDENn and CTRLDn will be invalid. + * |[17] |IMMLDEN1 |Immediately Load Enable Bit(S) + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |0 = PERIOD will load to PBUF at the end point of each period + * | | |CMPDAT will load to CMPBUF at the end point or center point of each period by setting CTRLD bit. + * | | |1 = PERIOD/CMPDAT will load to PBUF and CMPBUF immediately when software update PERIOD/CMPDAT. + * | | |Note: If IMMLDENn is Enabled, WINLDENn and CTRLDn will be invalid. + * |[18] |IMMLDEN2 |Immediately Load Enable Bit(S) + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |0 = PERIOD will load to PBUF at the end point of each period + * | | |CMPDAT will load to CMPBUF at the end point or center point of each period by setting CTRLD bit. + * | | |1 = PERIOD/CMPDAT will load to PBUF and CMPBUF immediately when software update PERIOD/CMPDAT. + * | | |Note: If IMMLDENn is Enabled, WINLDENn and CTRLDn will be invalid. + * |[19] |IMMLDEN3 |Immediately Load Enable Bit(S) + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |0 = PERIOD will load to PBUF at the end point of each period + * | | |CMPDAT will load to CMPBUF at the end point or center point of each period by setting CTRLD bit. + * | | |1 = PERIOD/CMPDAT will load to PBUF and CMPBUF immediately when software update PERIOD/CMPDAT. + * | | |Note: If IMMLDENn is Enabled, WINLDENn and CTRLDn will be invalid. + * |[20] |IMMLDEN4 |Immediately Load Enable Bit(S) + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |0 = PERIOD will load to PBUF at the end point of each period + * | | |CMPDAT will load to CMPBUF at the end point or center point of each period by setting CTRLD bit. + * | | |1 = PERIOD/CMPDAT will load to PBUF and CMPBUF immediately when software update PERIOD/CMPDAT. + * | | |Note: If IMMLDENn is Enabled, WINLDENn and CTRLDn will be invalid. + * |[21] |IMMLDEN5 |Immediately Load Enable Bit(S) + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |0 = PERIOD will load to PBUF at the end point of each period + * | | |CMPDAT will load to CMPBUF at the end point or center point of each period by setting CTRLD bit. + * | | |1 = PERIOD/CMPDAT will load to PBUF and CMPBUF immediately when software update PERIOD/CMPDAT. + * | | |Note: If IMMLDENn is Enabled, WINLDENn and CTRLDn will be invalid. + * |[30] |DBGHALT |ICE Debug Mode Counter Halt (Write Protect) + * | | |If counter halt is enabled, BPWM all counters will keep current value until exit ICE debug mode. + * | | |0 = ICE debug mode counter halt Disable. + * | | |1 = ICE debug mode counter halt Enable. + * | | |Note: This register is write protected. Refer to SYS_REGLCTL register. + * |[31] |DBGTRIOFF |ICE Debug Mode Acknowledge Disable (Write Protect) + * | | |0 = ICE debug mode acknowledgement effects BPWM output. + * | | |BPWM pin will be forced as tri-state while ICE debug mode acknowledged. + * | | |1 = ICE debug mode acknowledgement Disabled. + * | | |BPWM pin will keep output no matter ICE debug mode acknowledged or not. + * | | |Note: This register is write protected. Refer to SYS_REGLCTL register. + * @var BPWM_T::CTL1 + * Offset: 0x04 BPWM Control Register 1 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[1:0] |CNTTYPE0 |BPWM Counter Behavior Type 0 + * | | |Each bit n controls corresponding BPWM channel n. + * | | |00 = Up counter type (supports in capture mode). + * | | |01 = Down count type (supports in capture mode). + * | | |10 = Up-down counter type. + * | | |11 = Reserved. + * @var BPWM_T::CLKSRC + * Offset: 0x10 BPWM Clock Source Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[2:0] |ECLKSRC0 |BPWM_CH01 External Clock Source Select + * | | |000 = BPWMx_CLK, x denotes 0 or 1. + * | | |001 = TIMER0 overflow. + * | | |010 = TIMER1 overflow. + * | | |011 = TIMER2 overflow. + * | | |100 = TIMER3 overflow. + * | | |Others = Reserved. + * @var BPWM_T::CLKPSC + * Offset: 0x14 BPWM Clock Prescale Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[11:0] |CLKPSC |BPWM Counter Clock Prescale + * | | |The clock of BPWM counter is decided by clock prescaler + * | | |Each BPWM pair share one BPWM counter clock prescaler + * | | |The clock of BPWM counter is divided by (CLKPSC+ 1) + * @var BPWM_T::CNTEN + * Offset: 0x20 BPWM Counter Enable Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |CNTEN0 |BPWM Counter 0 Enable Bit + * | | |0 = BPWM Counter and clock prescaler stop running. + * | | |1 = BPWM Counter and clock prescaler start running. + * @var BPWM_T::CNTCLR + * Offset: 0x24 BPWM Clear Counter Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |CNTCLR0 |Clear BPWM Counter Control Bit 0 + * | | |It is automatically cleared by hardware. + * | | |0 = No effect. + * | | |1 = Clear 16-bit BPWM counter to 0000H. + * @var BPWM_T::PERIOD + * Offset: 0x30 BPWM Period Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |PERIOD |BPWM Period Register + * | | |Up-Count mode: In this mode, BPWM counter counts from 0 to PERIOD, and restarts from 0. + * | | |Down-Count mode: In this mode, BPWM counter counts from PERIOD to 0, and restarts from PERIOD. + * | | |BPWM period time = (PERIOD+1) * BPWM_CLK period. + * | | |Up-Down-Count mode: In this mode, BPWM counter counts from 0 to PERIOD, then decrements to 0 and repeats again. + * | | |BPWM period time = 2 * PERIOD * BPWM_CLK period. + * @var BPWM_T::CMPDAT[6] + * Offset: 0x50 BPWM Comparator Register 0~5 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |CMPDAT |BPWM Comparator Register + * | | |CMPDAT use to compare with CNTR to generate BPWM waveform, interrupt and trigger EADC. + * | | |In independent mode, CMPDAT0~5 denote as 6 independent BPWM_CH0~5 compared point. + * @var BPWM_T::CNT + * Offset: 0x90 BPWM Counter Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |CNT |BPWM Data Register (Read Only) + * | | |User can monitor CNTR to know the current value in 16-bit period counter. + * |[16] |DIRF |BPWM Direction Indicator Flag (Read Only) + * | | |0 = Counter is Down count. + * | | |1 = Counter is UP count. + * @var BPWM_T::WGCTL0 + * Offset: 0xB0 BPWM Generation Register 0 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[1:0] |ZPCTL0 |BPWM Zero Point Control + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |00 = Do nothing. + * | | |01 = BPWM zero point output Low. + * | | |10 = BPWM zero point output High. + * | | |11 = BPWM zero point output Toggle. + * | | |BPWM can control output level when BPWM counter count to zero. + * |[3:2] |ZPCTL1 |BPWM Zero Point Control + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |00 = Do nothing. + * | | |01 = BPWM zero point output Low. + * | | |10 = BPWM zero point output High. + * | | |11 = BPWM zero point output Toggle. + * | | |BPWM can control output level when BPWM counter count to zero. + * |[5:4] |ZPCTL2 |BPWM Zero Point Control + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |00 = Do nothing. + * | | |01 = BPWM zero point output Low. + * | | |10 = BPWM zero point output High. + * | | |11 = BPWM zero point output Toggle. + * | | |BPWM can control output level when BPWM counter count to zero. + * |[7:6] |ZPCTL3 |BPWM Zero Point Control + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |00 = Do nothing. + * | | |01 = BPWM zero point output Low. + * | | |10 = BPWM zero point output High. + * | | |11 = BPWM zero point output Toggle. + * | | |BPWM can control output level when BPWM counter count to zero. + * |[9:8] |ZPCTL4 |BPWM Zero Point Control + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |00 = Do nothing. + * | | |01 = BPWM zero point output Low. + * | | |10 = BPWM zero point output High. + * | | |11 = BPWM zero point output Toggle. + * | | |BPWM can control output level when BPWM counter count to zero. + * |[11:10] |ZPCTL5 |BPWM Zero Point Control + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |00 = Do nothing. + * | | |01 = BPWM zero point output Low. + * | | |10 = BPWM zero point output High. + * | | |11 = BPWM zero point output Toggle. + * | | |BPWM can control output level when BPWM counter count to zero. + * |[17:16] |PRDPCTL0 |BPWM Period (Center) Point Control + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |00 = Do nothing. + * | | |01 = BPWM period (center) point output Low. + * | | |10 = BPWM period (center) point output High. + * | | |11 = BPWM period (center) point output Toggle. + * | | |BPWM can control output level when BPWM counter count to (PERIOD+1). + * | | |Note: This bit is center point control when BPWM counter operating in up-down counter type. + * |[19:18] |PRDPCTL1 |BPWM Period (Center) Point Control + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |00 = Do nothing. + * | | |01 = BPWM period (center) point output Low. + * | | |10 = BPWM period (center) point output High. + * | | |11 = BPWM period (center) point output Toggle. + * | | |BPWM can control output level when BPWM counter count to (PERIOD+1). + * | | |Note: This bit is center point control when BPWM counter operating in up-down counter type. + * |[21:20] |PRDPCTL2 |BPWM Period (Center) Point Control + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |00 = Do nothing. + * | | |01 = BPWM period (center) point output Low. + * | | |10 = BPWM period (center) point output High. + * | | |11 = BPWM period (center) point output Toggle. + * | | |BPWM can control output level when BPWM counter count to (PERIOD+1). + * | | |Note: This bit is center point control when BPWM counter operating in up-down counter type. + * |[23:22] |PRDPCTL3 |BPWM Period (Center) Point Control + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |00 = Do nothing. + * | | |01 = BPWM period (center) point output Low. + * | | |10 = BPWM period (center) point output High. + * | | |11 = BPWM period (center) point output Toggle. + * | | |BPWM can control output level when BPWM counter count to (PERIOD+1). + * | | |Note: This bit is center point control when BPWM counter operating in up-down counter type. + * |[25:24] |PRDPCTL4 |BPWM Period (Center) Point Control + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |00 = Do nothing. + * | | |01 = BPWM period (center) point output Low. + * | | |10 = BPWM period (center) point output High. + * | | |11 = BPWM period (center) point output Toggle. + * | | |BPWM can control output level when BPWM counter count to (PERIOD+1). + * | | |Note: This bit is center point control when BPWM counter operating in up-down counter type. + * |[27:26] |PRDPCTL5 |BPWM Period (Center) Point Control + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |00 = Do nothing. + * | | |01 = BPWM period (center) point output Low. + * | | |10 = BPWM period (center) point output High. + * | | |11 = BPWM period (center) point output Toggle. + * | | |BPWM can control output level when BPWM counter count to (PERIOD+1). + * | | |Note: This bit is center point control when BPWM counter operating in up-down counter type. + * @var BPWM_T::WGCTL1 + * Offset: 0xB4 BPWM Generation Register 1 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[1:0] |CMPUCTL0 |BPWM Compare Up Point Control + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |00 = Do nothing. + * | | |01 = BPWM compare up point output Low. + * | | |10 = BPWM compare up point output High. + * | | |11 = BPWM compare up point output Toggle. + * | | |BPWM can control output level when BPWM counter up count to CMPDAT. + * |[3:2] |CMPUCTL1 |BPWM Compare Up Point Control + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |00 = Do nothing. + * | | |01 = BPWM compare up point output Low. + * | | |10 = BPWM compare up point output High. + * | | |11 = BPWM compare up point output Toggle. + * | | |BPWM can control output level when BPWM counter up count to CMPDAT. + * |[5:4] |CMPUCTL2 |BPWM Compare Up Point Control + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |00 = Do nothing. + * | | |01 = BPWM compare up point output Low. + * | | |10 = BPWM compare up point output High. + * | | |11 = BPWM compare up point output Toggle. + * | | |BPWM can control output level when BPWM counter up count to CMPDAT. + * |[7:6] |CMPUCTL3 |BPWM Compare Up Point Control + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |00 = Do nothing. + * | | |01 = BPWM compare up point output Low. + * | | |10 = BPWM compare up point output High. + * | | |11 = BPWM compare up point output Toggle. + * | | |BPWM can control output level when BPWM counter up count to CMPDAT. + * |[9:8] |CMPUCTL4 |BPWM Compare Up Point Control + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |00 = Do nothing. + * | | |01 = BPWM compare up point output Low. + * | | |10 = BPWM compare up point output High. + * | | |11 = BPWM compare up point output Toggle. + * | | |BPWM can control output level when BPWM counter up count to CMPDAT. + * |[11:10] |CMPUCTL5 |BPWM Compare Up Point Control + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |00 = Do nothing. + * | | |01 = BPWM compare up point output Low. + * | | |10 = BPWM compare up point output High. + * | | |11 = BPWM compare up point output Toggle. + * | | |BPWM can control output level when BPWM counter up count to CMPDAT. + * |[17:16] |CMPDCTL0 |BPWM Compare Down Point Control + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |00 = Do nothing. + * | | |01 = BPWM compare down point output Low. + * | | |10 = BPWM compare down point output High. + * | | |11 = BPWM compare down point output Toggle. + * | | |BPWM can control output level when BPWM counter down count to CMPDAT. + * |[19:18] |CMPDCTL1 |BPWM Compare Down Point Control + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |00 = Do nothing. + * | | |01 = BPWM compare down point output Low. + * | | |10 = BPWM compare down point output High. + * | | |11 = BPWM compare down point output Toggle. + * | | |BPWM can control output level when BPWM counter down count to CMPDAT. + * |[21:20] |CMPDCTL2 |BPWM Compare Down Point Control + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |00 = Do nothing. + * | | |01 = BPWM compare down point output Low. + * | | |10 = BPWM compare down point output High. + * | | |11 = BPWM compare down point output Toggle. + * | | |BPWM can control output level when BPWM counter down count to CMPDAT. + * |[23:22] |CMPDCTL3 |BPWM Compare Down Point Control + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |00 = Do nothing. + * | | |01 = BPWM compare down point output Low. + * | | |10 = BPWM compare down point output High. + * | | |11 = BPWM compare down point output Toggle. + * | | |BPWM can control output level when BPWM counter down count to CMPDAT. + * |[25:24] |CMPDCTL4 |BPWM Compare Down Point Control + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |00 = Do nothing. + * | | |01 = BPWM compare down point output Low. + * | | |10 = BPWM compare down point output High. + * | | |11 = BPWM compare down point output Toggle. + * | | |BPWM can control output level when BPWM counter down count to CMPDAT. + * |[27:26] |CMPDCTL5 |BPWM Compare Down Point Control + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |00 = Do nothing. + * | | |01 = BPWM compare down point output Low. + * | | |10 = BPWM compare down point output High. + * | | |11 = BPWM compare down point output Toggle. + * | | |BPWM can control output level when BPWM counter down count to CMPDAT. + * @var BPWM_T::MSKEN + * Offset: 0xB8 BPWM Mask Enable Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |MSKEN0 |BPWM Mask Enable Bits + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |The BPWM output signal will be masked when this bit is enabled + * | | |The corresponding BPWM channel n will output MSKDATn (BPWM_MSK[5:0]) data. + * | | |0 = BPWM output signal is non-masked. + * | | |1 = BPWM output signal is masked and output MSKDATn data. + * |[1] |MSKEN1 |BPWM Mask Enable Bits + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |The BPWM output signal will be masked when this bit is enabled + * | | |The corresponding BPWM channel n will output MSKDATn (BPWM_MSK[5:0]) data. + * | | |0 = BPWM output signal is non-masked. + * | | |1 = BPWM output signal is masked and output MSKDATn data. + * |[2] |MSKEN2 |BPWM Mask Enable Bits + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |The BPWM output signal will be masked when this bit is enabled + * | | |The corresponding BPWM channel n will output MSKDATn (BPWM_MSK[5:0]) data. + * | | |0 = BPWM output signal is non-masked. + * | | |1 = BPWM output signal is masked and output MSKDATn data. + * |[3] |MSKEN3 |BPWM Mask Enable Bits + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |The BPWM output signal will be masked when this bit is enabled + * | | |The corresponding BPWM channel n will output MSKDATn (BPWM_MSK[5:0]) data. + * | | |0 = BPWM output signal is non-masked. + * | | |1 = BPWM output signal is masked and output MSKDATn data. + * |[4] |MSKEN4 |BPWM Mask Enable Bits + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |The BPWM output signal will be masked when this bit is enabled + * | | |The corresponding BPWM channel n will output MSKDATn (BPWM_MSK[5:0]) data. + * | | |0 = BPWM output signal is non-masked. + * | | |1 = BPWM output signal is masked and output MSKDATn data. + * |[5] |MSKEN5 |BPWM Mask Enable Bits + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |The BPWM output signal will be masked when this bit is enabled + * | | |The corresponding BPWM channel n will output MSKDATn (BPWM_MSK[5:0]) data. + * | | |0 = BPWM output signal is non-masked. + * | | |1 = BPWM output signal is masked and output MSKDATn data. + * @var BPWM_T::MSK + * Offset: 0xBC BPWM Mask Data Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |MSKDAT0 |BPWM Mask Data Bit + * | | |This data bit control the state of BPWMn output pin, if corresponding mask function is enabled + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |0 = Output logic low to BPWMn. + * | | |1 = Output logic high to BPWMn. + * |[1] |MSKDAT1 |BPWM Mask Data Bit + * | | |This data bit control the state of BPWMn output pin, if corresponding mask function is enabled + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |0 = Output logic low to BPWMn. + * | | |1 = Output logic high to BPWMn. + * |[2] |MSKDAT2 |BPWM Mask Data Bit + * | | |This data bit control the state of BPWMn output pin, if corresponding mask function is enabled + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |0 = Output logic low to BPWMn. + * | | |1 = Output logic high to BPWMn. + * |[3] |MSKDAT3 |BPWM Mask Data Bit + * | | |This data bit control the state of BPWMn output pin, if corresponding mask function is enabled + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |0 = Output logic low to BPWMn. + * | | |1 = Output logic high to BPWMn. + * |[4] |MSKDAT4 |BPWM Mask Data Bit + * | | |This data bit control the state of BPWMn output pin, if corresponding mask function is enabled + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |0 = Output logic low to BPWMn. + * | | |1 = Output logic high to BPWMn. + * |[5] |MSKDAT5 |BPWM Mask Data Bit + * | | |This data bit control the state of BPWMn output pin, if corresponding mask function is enabled + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |0 = Output logic low to BPWMn. + * | | |1 = Output logic high to BPWMn. + * @var BPWM_T::POLCTL + * Offset: 0xD4 BPWM Pin Polar Inverse Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |PINV0 |BPWM PIN Polar Inverse Control + * | | |The register controls polarity state of BPWM output + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |0 = BPWM output polar inverse Disabled. + * | | |1 = BPWM output polar inverse Enabled. + * |[1] |PINV1 |BPWM PIN Polar Inverse Control + * | | |The register controls polarity state of BPWM output + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |0 = BPWM output polar inverse Disabled. + * | | |1 = BPWM output polar inverse Enabled. + * |[2] |PINV2 |BPWM PIN Polar Inverse Control + * | | |The register controls polarity state of BPWM output + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |0 = BPWM output polar inverse Disabled. + * | | |1 = BPWM output polar inverse Enabled. + * |[3] |PINV3 |BPWM PIN Polar Inverse Control + * | | |The register controls polarity state of BPWM output + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |0 = BPWM output polar inverse Disabled. + * | | |1 = BPWM output polar inverse Enabled. + * |[4] |PINV4 |BPWM PIN Polar Inverse Control + * | | |The register controls polarity state of BPWM output + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |0 = BPWM output polar inverse Disabled. + * | | |1 = BPWM output polar inverse Enabled. + * |[5] |PINV5 |BPWM PIN Polar Inverse Control + * | | |The register controls polarity state of BPWM output + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |0 = BPWM output polar inverse Disabled. + * | | |1 = BPWM output polar inverse Enabled. + * @var BPWM_T::POEN + * Offset: 0xD8 BPWM Output Enable Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |POEN0 |BPWM Pin Output Enable Bits + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |0 = BPWM pin at tri-state. + * | | |1 = BPWM pin in output mode. + * |[1] |POEN1 |BPWM Pin Output Enable Bits + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |0 = BPWM pin at tri-state. + * | | |1 = BPWM pin in output mode. + * |[2] |POEN2 |BPWM Pin Output Enable Bits + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |0 = BPWM pin at tri-state. + * | | |1 = BPWM pin in output mode. + * |[3] |POEN3 |BPWM Pin Output Enable Bits + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |0 = BPWM pin at tri-state. + * | | |1 = BPWM pin in output mode. + * |[4] |POEN4 |BPWM Pin Output Enable Bits + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |0 = BPWM pin at tri-state. + * | | |1 = BPWM pin in output mode. + * |[5] |POEN5 |BPWM Pin Output Enable Bits + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |0 = BPWM pin at tri-state. + * | | |1 = BPWM pin in output mode. + * @var BPWM_T::INTEN + * Offset: 0xE0 BPWM Interrupt Enable Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |ZIEN0 |BPWM Zero Point Interrupt 0 Enable Bit + * | | |0 = Zero point interrupt Disabled. + * | | |1 = Zero point interrupt Enabled. + * |[8] |PIEN0 |BPWM Period Point Interrupt 0 Enable Bit + * | | |0 = Period point interrupt Disabled. + * | | |1 = Period point interrupt Enabled. + * | | |Note: When up-down counter type period point means center point. + * |[16] |CMPUIEN0 |BPWM Compare Up Count Interrupt Enable Bits + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |0 = Compare up count interrupt Disabled. + * | | |1 = Compare up count interrupt Enabled. + * |[17] |CMPUIEN1 |BPWM Compare Up Count Interrupt Enable Bits + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |0 = Compare up count interrupt Disabled. + * | | |1 = Compare up count interrupt Enabled. + * |[18] |CMPUIEN2 |BPWM Compare Up Count Interrupt Enable Bits + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |0 = Compare up count interrupt Disabled. + * | | |1 = Compare up count interrupt Enabled. + * |[19] |CMPUIEN3 |BPWM Compare Up Count Interrupt Enable Bits + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |0 = Compare up count interrupt Disabled. + * | | |1 = Compare up count interrupt Enabled. + * |[20] |CMPUIEN4 |BPWM Compare Up Count Interrupt Enable Bits + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |0 = Compare up count interrupt Disabled. + * | | |1 = Compare up count interrupt Enabled. + * |[21] |CMPUIEN5 |BPWM Compare Up Count Interrupt Enable Bits + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |0 = Compare up count interrupt Disabled. + * | | |1 = Compare up count interrupt Enabled. + * |[24] |CMPDIEN0 |BPWM Compare Down Count Interrupt Enable Bits + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |0 = Compare down count interrupt Disabled. + * | | |1 = Compare down count interrupt Enabled. + * |[25] |CMPDIEN1 |BPWM Compare Down Count Interrupt Enable Bits + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |0 = Compare down count interrupt Disabled. + * | | |1 = Compare down count interrupt Enabled. + * |[26] |CMPDIEN2 |BPWM Compare Down Count Interrupt Enable Bits + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |0 = Compare down count interrupt Disabled. + * | | |1 = Compare down count interrupt Enabled. + * |[27] |CMPDIEN3 |BPWM Compare Down Count Interrupt Enable Bits + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |0 = Compare down count interrupt Disabled. + * | | |1 = Compare down count interrupt Enabled. + * |[28] |CMPDIEN4 |BPWM Compare Down Count Interrupt Enable Bits + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |0 = Compare down count interrupt Disabled. + * | | |1 = Compare down count interrupt Enabled. + * |[29] |CMPDIEN5 |BPWM Compare Down Count Interrupt Enable Bits + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |0 = Compare down count interrupt Disabled. + * | | |1 = Compare down count interrupt Enabled. + * @var BPWM_T::INTSTS + * Offset: 0xE8 BPWM Interrupt Flag Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |ZIF0 |BPWM Zero Point Interrupt Flag 0 + * | | |This bit is set by hardware when BPWM_CH0 counter reaches zero, software can write 1 to clear this bit to zero. + * |[8] |PIF0 |BPWM Period Point Interrupt Flag 0 + * | | |This bit is set by hardware when BPWM_CH0 counter reaches BPWM_PERIOD0, software can write 1 to clear this bit to zero. + * |[16] |CMPUIF0 |BPWM Compare Up Count Interrupt Flag + * | | |Flag is set by hardware when BPWM counter up count and reaches BPWM_CMPDATn, software can clear this bit by writing 1 to it + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |Note: If CMPDAT equal to PERIOD, this flag is not working in up counter type selection. + * |[17] |CMPUIF1 |BPWM Compare Up Count Interrupt Flag + * | | |Flag is set by hardware when BPWM counter up count and reaches BPWM_CMPDATn, software can clear this bit by writing 1 to it + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |Note: If CMPDAT equal to PERIOD, this flag is not working in up counter type selection. + * |[18] |CMPUIF2 |BPWM Compare Up Count Interrupt Flag + * | | |Flag is set by hardware when BPWM counter up count and reaches BPWM_CMPDATn, software can clear this bit by writing 1 to it + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |Note: If CMPDAT equal to PERIOD, this flag is not working in up counter type selection. + * |[19] |CMPUIF3 |BPWM Compare Up Count Interrupt Flag + * | | |Flag is set by hardware when BPWM counter up count and reaches BPWM_CMPDATn, software can clear this bit by writing 1 to it + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |Note: If CMPDAT equal to PERIOD, this flag is not working in up counter type selection. + * |[20] |CMPUIF4 |BPWM Compare Up Count Interrupt Flag + * | | |Flag is set by hardware when BPWM counter up count and reaches BPWM_CMPDATn, software can clear this bit by writing 1 to it + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |Note: If CMPDAT equal to PERIOD, this flag is not working in up counter type selection. + * |[21] |CMPUIF5 |BPWM Compare Up Count Interrupt Flag + * | | |Flag is set by hardware when BPWM counter up count and reaches BPWM_CMPDATn, software can clear this bit by writing 1 to it + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |Note: If CMPDAT equal to PERIOD, this flag is not working in up counter type selection. + * |[24] |CMPDIF0 |BPWM Compare Down Count Interrupt Flag + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |Flag is set by hardware when BPWM counter down count and reaches BPWM_CMPDATn, software can clear this bit by writing 1 to it. + * | | |Note: If CMPDAT equal to PERIOD, this flag is not working in down counter type selection. + * |[25] |CMPDIF1 |BPWM Compare Down Count Interrupt Flag + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |Flag is set by hardware when BPWM counter down count and reaches BPWM_CMPDATn, software can clear this bit by writing 1 to it. + * | | |Note: If CMPDAT equal to PERIOD, this flag is not working in down counter type selection. + * |[26] |CMPDIF2 |BPWM Compare Down Count Interrupt Flag + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |Flag is set by hardware when BPWM counter down count and reaches BPWM_CMPDATn, software can clear this bit by writing 1 to it. + * | | |Note: If CMPDAT equal to PERIOD, this flag is not working in down counter type selection. + * |[27] |CMPDIF3 |BPWM Compare Down Count Interrupt Flag + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |Flag is set by hardware when BPWM counter down count and reaches BPWM_CMPDATn, software can clear this bit by writing 1 to it. + * | | |Note: If CMPDAT equal to PERIOD, this flag is not working in down counter type selection. + * |[28] |CMPDIF4 |BPWM Compare Down Count Interrupt Flag + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |Flag is set by hardware when BPWM counter down count and reaches BPWM_CMPDATn, software can clear this bit by writing 1 to it. + * | | |Note: If CMPDAT equal to PERIOD, this flag is not working in down counter type selection. + * |[29] |CMPDIF5 |BPWM Compare Down Count Interrupt Flag + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |Flag is set by hardware when BPWM counter down count and reaches BPWM_CMPDATn, software can clear this bit by writing 1 to it. + * | | |Note: If CMPDAT equal to PERIOD, this flag is not working in down counter type selection. + * @var BPWM_T::EADCTS0 + * Offset: 0xF8 BPWM Trigger EADC Source Select Register 0 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[3:0] |TRGSEL0 |BPWM_CH0 Trigger EADC Source Select + * | | |0000 = BPWM_CH0 zero point. + * | | |0001 = BPWM_CH0 period point. + * | | |0010 = BPWM_CH0 zero or period point. + * | | |0011 = BPWM_CH0 up-count CMPDAT point. + * | | |0100 = BPWM_CH0 down-count CMPDAT point. + * | | |0101 = Reserved. + * | | |0110 = Reserved. + * | | |0111 = Reserved. + * | | |1000 = BPWM_CH1 up-count CMPDAT point. + * | | |1001 = BPWM_CH1 down-count CMPDAT point. + * | | |Others reserved + * |[7] |TRGEN0 |BPWM_CH0 Trigger EADC Enable Bit + * |[11:8] |TRGSEL1 |BPWM_CH1 Trigger EADC Source Select + * | | |0000 = BPWM_CH0 zero point. + * | | |0001 = BPWM_CH0 period point. + * | | |0010 = BPWM_CH0 zero or period point. + * | | |0011 = BPWM_CH0 up-count CMPDAT point. + * | | |0100 = BPWM_CH0 down-count CMPDAT point. + * | | |0101 = Reserved. + * | | |0110 = Reserved. + * | | |0111 = Reserved. + * | | |1000 = BPWM_CH1 up-count CMPDAT point. + * | | |1001 = BPWM_CH1 down-count CMPDAT point. + * | | |Others reserved + * |[15] |TRGEN1 |BPWM_CH1 Trigger EADC Enable Bit + * |[19:16] |TRGSEL2 |BPWM_CH2 Trigger EADC Source Select + * | | |0000 = BPWM_CH2 zero point. + * | | |0001 = BPWM_CH2 period point. + * | | |0010 = BPWM_CH2 zero or period point. + * | | |0011 = BPWM_CH2 up-count CMPDAT point. + * | | |0100 = BPWM_CH2 down-count CMPDAT point. + * | | |0101 = Reserved. + * | | |0110 = Reserved. + * | | |0111 = Reserved. + * | | |1000 = BPWM_CH3 up-count CMPDAT point. + * | | |1001 = BPWM_CH3 down-count CMPDAT point. + * | | |Others reserved + * |[23] |TRGEN2 |BPWM_CH2 Trigger EADC Enable Bit + * |[27:24] |TRGSEL3 |BPWM_CH3 Trigger EADC Source Select + * | | |0000 = BPWM_CH2 zero point. + * | | |0001 = BPWM_CH2 period point. + * | | |0010 = BPWM_CH2 zero or period point. + * | | |0011 = BPWM_CH2 up-count CMPDAT point. + * | | |0100 = BPWM_CH2 down-count CMPDAT point. + * | | |0101 = Reserved. + * | | |0110 = Reserved. + * | | |0111 = Reserved. + * | | |1000 = BPWM_CH3 up-count CMPDAT point. + * | | |1001 = BPWM_CH3 down-count CMPDAT point. + * | | |Others reserved. + * |[31] |TRGEN3 |BPWM_CH3 Trigger EADC Enable Bit + * @var BPWM_T::EADCTS1 + * Offset: 0xFC BPWM Trigger EADC Source Select Register 1 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[3:0] |TRGSEL4 |BPWM_CH4 Trigger EADC Source Select + * | | |0000 = BPWM_CH4 zero point. + * | | |0001 = BPWM_CH4 period point. + * | | |0010 = BPWM_CH4 zero or period point. + * | | |0011 = BPWM_CH4 up-count CMPDAT point. + * | | |0100 = BPWM_CH4 down-count CMPDAT point. + * | | |0101 = Reserved. + * | | |0110 = Reserved. + * | | |0111 = Reserved. + * | | |1000 = BPWM_CH5 up-count CMPDAT point. + * | | |1001 = BPWM_CH5 down-count CMPDAT point. + * | | |Others reserved + * |[7] |TRGEN4 |BPWM_CH4 Trigger EADC Enable Bit + * |[11:8] |TRGSEL5 |BPWM_CH5 Trigger EADC Source Select + * | | |0000 = BPWM_CH4 zero point. + * | | |0001 = BPWM_CH4 period point. + * | | |0010 = BPWM_CH4 zero or period point. + * | | |0011 = BPWM_CH4 up-count CMPDAT point. + * | | |0100 = BPWM_CH4 down-count CMPDAT point. + * | | |0101 = Reserved. + * | | |0110 = Reserved. + * | | |0111 = Reserved. + * | | |1000 = BPWM_CH5 up-count CMPDAT point. + * | | |1001 = BPWM_CH5 down-count CMPDAT point. + * | | |Others reserved + * |[15] |TRGEN5 |BPWM_CH5 Trigger EADC Enable Bit + * @var BPWM_T::SSCTL + * Offset: 0x110 BPWM Synchronous Start Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |SSEN0 |BPWM Synchronous Start Function 0 Enable Bit + * | | |When synchronous start function is enabled, the BPWM_CH0 counter enable bit (CNTEN0) can be enabled by writing BPWM synchronous start trigger bit (CNTSEN). + * | | |0 = BPWM synchronous start function Disabled. + * | | |1 = BPWM synchronous start function Enabled. + * |[9:8] |SSRC |BPWM Synchronous Start Source Select + * | | |00 = Synchronous start source come from PWM0. + * | | |01 = Synchronous start source come from PWM1. + * | | |10 = Synchronous start source come from BPWM0. + * | | |11 = Synchronous start source come from BPWM1. + * @var BPWM_T::SSTRG + * Offset: 0x114 BPWM Synchronous Start Trigger Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |CNTSEN |BPWM Counter Synchronous Start Enable Bit(Write Only) + * | | |BPMW counter synchronous enable function is used to make PWM or BPWM channels start counting at the same time. + * | | |Writing this bit to 1 will also set the counter enable bit if correlated BPWM channel counter synchronous start function is enabled. + * @var BPWM_T::STATUS + * Offset: 0x120 BPWM Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |CNTMAX0 |Time-base Counter 0 Equal to 0xFFFF Latched Status + * | | |0 = indicates the time-base counter never reached its maximum value 0xFFFF. + * | | |1 = indicates the time-base counter reached its maximum value, software can write 1 to clear this bit. + * |[16] |EADCTRG0 |EADC Start of Conversion Status + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |0 = Indicates no EADC start of conversion trigger event has occurred. + * | | |1 = Indicates an EADC start of conversion trigger event has occurred, software can write 1 to clear this bit. + * |[17] |EADCTRG1 |EADC Start of Conversion Status + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |0 = Indicates no EADC start of conversion trigger event has occurred. + * | | |1 = Indicates an EADC start of conversion trigger event has occurred, software can write 1 to clear this bit. + * |[18] |EADCTRG2 |EADC Start of Conversion Status + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |0 = Indicates no EADC start of conversion trigger event has occurred. + * | | |1 = Indicates an EADC start of conversion trigger event has occurred, software can write 1 to clear this bit. + * |[19] |EADCTRG3 |EADC Start of Conversion Status + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |0 = Indicates no EADC start of conversion trigger event has occurred. + * | | |1 = Indicates an EADC start of conversion trigger event has occurred, software can write 1 to clear this bit. + * |[20] |EADCTRG4 |EADC Start of Conversion Status + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |0 = Indicates no EADC start of conversion trigger event has occurred. + * | | |1 = Indicates an EADC start of conversion trigger event has occurred, software can write 1 to clear this bit. + * |[21] |EADCTRG5 |EADC Start of Conversion Status + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |0 = Indicates no EADC start of conversion trigger event has occurred. + * | | |1 = Indicates an EADC start of conversion trigger event has occurred, software can write 1 to clear this bit. + * @var BPWM_T::CAPINEN + * Offset: 0x200 BPWM Capture Input Enable Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |CAPINEN0 |Capture Input Enable Bits + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |0 = BPWM Channel capture input path Disabled + * | | |The input of BPWM channel capture function is always regarded as 0. + * | | |1 = BPWM Channel capture input path Enabled + * | | |The input of BPWM channel capture function comes from correlative multifunction pin. + * |[1] |CAPINEN1 |Capture Input Enable Bits + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |0 = BPWM Channel capture input path Disabled + * | | |The input of BPWM channel capture function is always regarded as 0. + * | | |1 = BPWM Channel capture input path Enabled + * | | |The input of BPWM channel capture function comes from correlative multifunction pin. + * |[2] |CAPINEN2 |Capture Input Enable Bits + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |0 = BPWM Channel capture input path Disabled + * | | |The input of BPWM channel capture function is always regarded as 0. + * | | |1 = BPWM Channel capture input path Enabled + * | | |The input of BPWM channel capture function comes from correlative multifunction pin. + * |[3] |CAPINEN3 |Capture Input Enable Bits + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |0 = BPWM Channel capture input path Disabled + * | | |The input of BPWM channel capture function is always regarded as 0. + * | | |1 = BPWM Channel capture input path Enabled + * | | |The input of BPWM channel capture function comes from correlative multifunction pin. + * |[4] |CAPINEN4 |Capture Input Enable Bits + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |0 = BPWM Channel capture input path Disabled + * | | |The input of BPWM channel capture function is always regarded as 0. + * | | |1 = BPWM Channel capture input path Enabled + * | | |The input of BPWM channel capture function comes from correlative multifunction pin. + * |[5] |CAPINEN5 |Capture Input Enable Bits + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |0 = BPWM Channel capture input path Disabled + * | | |The input of BPWM channel capture function is always regarded as 0. + * | | |1 = BPWM Channel capture input path Enabled + * | | |The input of BPWM channel capture function comes from correlative multifunction pin. + * @var BPWM_T::CAPCTL + * Offset: 0x204 BPWM Capture Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |CAPEN0 |Capture Function Enable Bits + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |0 = Capture function Disabled. RCAPDAT/FCAPDAT register will not be updated. + * | | |1 = Capture function Enabled + * | | |Capture latched the BPWM counter value when detected rising or falling edge of input signal and saved to RCAPDAT (Rising latch) and FCAPDAT (Falling latch). + * |[1] |CAPEN1 |Capture Function Enable Bits + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |0 = Capture function Disabled. RCAPDAT/FCAPDAT register will not be updated. + * | | |1 = Capture function Enabled + * | | |Capture latched the BPWM counter value when detected rising or falling edge of input signal and saved to RCAPDAT (Rising latch) and FCAPDAT (Falling latch). + * |[2] |CAPEN2 |Capture Function Enable Bits + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |0 = Capture function Disabled. RCAPDAT/FCAPDAT register will not be updated. + * | | |1 = Capture function Enabled + * | | |Capture latched the BPWM counter value when detected rising or falling edge of input signal and saved to RCAPDAT (Rising latch) and FCAPDAT (Falling latch). + * |[3] |CAPEN3 |Capture Function Enable Bits + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |0 = Capture function Disabled. RCAPDAT/FCAPDAT register will not be updated. + * | | |1 = Capture function Enabled + * | | |Capture latched the BPWM counter value when detected rising or falling edge of input signal and saved to RCAPDAT (Rising latch) and FCAPDAT (Falling latch). + * |[4] |CAPEN4 |Capture Function Enable Bits + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |0 = Capture function Disabled. RCAPDAT/FCAPDAT register will not be updated. + * | | |1 = Capture function Enabled + * | | |Capture latched the BPWM counter value when detected rising or falling edge of input signal and saved to RCAPDAT (Rising latch) and FCAPDAT (Falling latch). + * |[5] |CAPEN5 |Capture Function Enable Bits + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |0 = Capture function Disabled. RCAPDAT/FCAPDAT register will not be updated. + * | | |1 = Capture function Enabled + * | | |Capture latched the BPWM counter value when detected rising or falling edge of input signal and saved to RCAPDAT (Rising latch) and FCAPDAT (Falling latch). + * |[8] |CAPINV0 |Capture Inverter Enable Bits + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |0 = Capture source inverter Disabled. + * | | |1 = Capture source inverter Enabled. Reverse the input signal from GPIO. + * |[9] |CAPINV1 |Capture Inverter Enable Bits + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |0 = Capture source inverter Disabled. + * | | |1 = Capture source inverter Enabled. Reverse the input signal from GPIO. + * |[10] |CAPINV2 |Capture Inverter Enable Bits + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |0 = Capture source inverter Disabled. + * | | |1 = Capture source inverter Enabled. Reverse the input signal from GPIO. + * |[11] |CAPINV3 |Capture Inverter Enable Bits + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |0 = Capture source inverter Disabled. + * | | |1 = Capture source inverter Enabled. Reverse the input signal from GPIO. + * |[12] |CAPINV4 |Capture Inverter Enable Bits + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |0 = Capture source inverter Disabled. + * | | |1 = Capture source inverter Enabled. Reverse the input signal from GPIO. + * |[13] |CAPINV5 |Capture Inverter Enable Bits + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |0 = Capture source inverter Disabled. + * | | |1 = Capture source inverter Enabled. Reverse the input signal from GPIO. + * |[16] |RCRLDEN0 |Rising Capture Reload Enable Bits + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |0 = Rising capture reload counter Disabled. + * | | |1 = Rising capture reload counter Enabled. + * |[17] |RCRLDEN1 |Rising Capture Reload Enable Bits + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |0 = Rising capture reload counter Disabled. + * | | |1 = Rising capture reload counter Enabled. + * |[18] |RCRLDEN2 |Rising Capture Reload Enable Bits + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |0 = Rising capture reload counter Disabled. + * | | |1 = Rising capture reload counter Enabled. + * |[19] |RCRLDEN3 |Rising Capture Reload Enable Bits + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |0 = Rising capture reload counter Disabled. + * | | |1 = Rising capture reload counter Enabled. + * |[20] |RCRLDEN4 |Rising Capture Reload Enable Bits + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |0 = Rising capture reload counter Disabled. + * | | |1 = Rising capture reload counter Enabled. + * |[21] |RCRLDEN5 |Rising Capture Reload Enable Bits + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |0 = Rising capture reload counter Disabled. + * | | |1 = Rising capture reload counter Enabled. + * |[24] |FCRLDEN0 |Falling Capture Reload Enable Bits + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |0 = Falling capture reload counter Disabled. + * | | |1 = Falling capture reload counter Enabled. + * |[25] |FCRLDEN1 |Falling Capture Reload Enable Bits + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |0 = Falling capture reload counter Disabled. + * | | |1 = Falling capture reload counter Enabled. + * |[26] |FCRLDEN2 |Falling Capture Reload Enable Bits + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |0 = Falling capture reload counter Disabled. + * | | |1 = Falling capture reload counter Enabled. + * |[27] |FCRLDEN3 |Falling Capture Reload Enable Bits + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |0 = Falling capture reload counter Disabled. + * | | |1 = Falling capture reload counter Enabled. + * |[28] |FCRLDEN4 |Falling Capture Reload Enable Bits + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |0 = Falling capture reload counter Disabled. + * | | |1 = Falling capture reload counter Enabled. + * |[29] |FCRLDEN5 |Falling Capture Reload Enable Bits + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |0 = Falling capture reload counter Disabled. + * | | |1 = Falling capture reload counter Enabled. + * @var BPWM_T::CAPSTS + * Offset: 0x208 BPWM Capture Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |CRIFOV0 |Capture Rising Interrupt Flag Overrun Status (Read Only) + * | | |This flag indicates if rising latch happened when the corresponding CAPRIF is 1 + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |Note: This bit will be cleared automatically when user clear corresponding CAPRIF. + * |[1] |CRIFOV1 |Capture Rising Interrupt Flag Overrun Status (Read Only) + * | | |This flag indicates if rising latch happened when the corresponding CAPRIF is 1 + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |Note: This bit will be cleared automatically when user clear corresponding CAPRIF. + * |[2] |CRIFOV2 |Capture Rising Interrupt Flag Overrun Status (Read Only) + * | | |This flag indicates if rising latch happened when the corresponding CAPRIF is 1 + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |Note: This bit will be cleared automatically when user clear corresponding CAPRIF. + * |[3] |CRIFOV3 |Capture Rising Interrupt Flag Overrun Status (Read Only) + * | | |This flag indicates if rising latch happened when the corresponding CAPRIF is 1 + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |Note: This bit will be cleared automatically when user clear corresponding CAPRIF. + * |[4] |CRIFOV4 |Capture Rising Interrupt Flag Overrun Status (Read Only) + * | | |This flag indicates if rising latch happened when the corresponding CAPRIF is 1 + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |Note: This bit will be cleared automatically when user clear corresponding CAPRIF. + * |[5] |CRIFOV5 |Capture Rising Interrupt Flag Overrun Status (Read Only) + * | | |This flag indicates if rising latch happened when the corresponding CAPRIF is 1 + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |Note: This bit will be cleared automatically when user clear corresponding CAPRIF. + * |[8] |CFIFOV0 |Capture Falling Interrupt Flag Overrun Status (Read Only) + * | | |This flag indicates if falling latch happened when the corresponding CAPFIF is 1 + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |Note: This bit will be cleared automatically when user clear corresponding CAPFIF. + * |[9] |CFIFOV1 |Capture Falling Interrupt Flag Overrun Status (Read Only) + * | | |This flag indicates if falling latch happened when the corresponding CAPFIF is 1 + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |Note: This bit will be cleared automatically when user clear corresponding CAPFIF. + * |[10] |CFIFOV2 |Capture Falling Interrupt Flag Overrun Status (Read Only) + * | | |This flag indicates if falling latch happened when the corresponding CAPFIF is 1 + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |Note: This bit will be cleared automatically when user clear corresponding CAPFIF. + * |[11] |CFIFOV3 |Capture Falling Interrupt Flag Overrun Status (Read Only) + * | | |This flag indicates if falling latch happened when the corresponding CAPFIF is 1 + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |Note: This bit will be cleared automatically when user clear corresponding CAPFIF. + * |[12] |CFIFOV4 |Capture Falling Interrupt Flag Overrun Status (Read Only) + * | | |This flag indicates if falling latch happened when the corresponding CAPFIF is 1 + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |Note: This bit will be cleared automatically when user clear corresponding CAPFIF. + * |[13] |CFIFOV5 |Capture Falling Interrupt Flag Overrun Status (Read Only) + * | | |This flag indicates if falling latch happened when the corresponding CAPFIF is 1 + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |Note: This bit will be cleared automatically when user clear corresponding CAPFIF. + * @var BPWM_T::CAPIEN + * Offset: 0x250 BPWM Capture Interrupt Enable Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[5:0] |CAPRIENn |BPWM Capture Rising Latch Interrupt Enable Bits + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |0 = Capture rising edge latch interrupt Disabled. + * | | |1 = Capture rising edge latch interrupt Enabled. + * |[13:8] |CAPFIENn |BPWM Capture Falling Latch Interrupt Enable Bits + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |0 = Capture falling edge latch interrupt Disabled. + * | | |1 = Capture falling edge latch interrupt Enabled. + * @var BPWM_T::CAPIF + * Offset: 0x254 BPWM Capture Interrupt Flag Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |CAPRIF0 |BPWM Capture Rising Latch Interrupt Flag + * | | |This bit is writing 1 to clear. Each bit n controls the corresponding BPWM channel n. + * | | |0 = No capture rising latch condition happened. + * | | |1 = Capture rising latch condition happened, this flag will be set to high. + * |[1] |CAPRIF1 |BPWM Capture Rising Latch Interrupt Flag + * | | |This bit is writing 1 to clear. Each bit n controls the corresponding BPWM channel n. + * | | |0 = No capture rising latch condition happened. + * | | |1 = Capture rising latch condition happened, this flag will be set to high. + * |[2] |CAPRIF2 |BPWM Capture Rising Latch Interrupt Flag + * | | |This bit is writing 1 to clear. Each bit n controls the corresponding BPWM channel n. + * | | |0 = No capture rising latch condition happened. + * | | |1 = Capture rising latch condition happened, this flag will be set to high. + * |[3] |CAPRIF3 |BPWM Capture Rising Latch Interrupt Flag + * | | |This bit is writing 1 to clear. Each bit n controls the corresponding BPWM channel n. + * | | |0 = No capture rising latch condition happened. + * | | |1 = Capture rising latch condition happened, this flag will be set to high. + * |[4] |CAPRIF4 |BPWM Capture Rising Latch Interrupt Flag + * | | |This bit is writing 1 to clear. Each bit n controls the corresponding BPWM channel n. + * | | |0 = No capture rising latch condition happened. + * | | |1 = Capture rising latch condition happened, this flag will be set to high. + * |[5] |CAPRIF5 |BPWM Capture Rising Latch Interrupt Flag + * | | |This bit is writing 1 to clear. Each bit n controls the corresponding BPWM channel n. + * | | |0 = No capture rising latch condition happened. + * | | |1 = Capture rising latch condition happened, this flag will be set to high. + * |[8] |CAPFIF0 |BPWM Capture Falling Latch Interrupt Flag + * | | |This bit is writing 1 to clear. Each bit n controls the corresponding BPWM channel n. + * | | |0 = No capture falling latch condition happened. + * | | |1 = Capture falling latch condition happened, this flag will be set to high. + * |[9] |CAPFIF1 |BPWM Capture Falling Latch Interrupt Flag + * | | |This bit is writing 1 to clear. Each bit n controls the corresponding BPWM channel n. + * | | |0 = No capture falling latch condition happened. + * | | |1 = Capture falling latch condition happened, this flag will be set to high. + * |[10] |CAPFIF2 |BPWM Capture Falling Latch Interrupt Flag + * | | |This bit is writing 1 to clear. Each bit n controls the corresponding BPWM channel n. + * | | |0 = No capture falling latch condition happened. + * | | |1 = Capture falling latch condition happened, this flag will be set to high. + * |[11] |CAPFIF3 |BPWM Capture Falling Latch Interrupt Flag + * | | |This bit is writing 1 to clear. Each bit n controls the corresponding BPWM channel n. + * | | |0 = No capture falling latch condition happened. + * | | |1 = Capture falling latch condition happened, this flag will be set to high. + * |[12] |CAPFIF4 |BPWM Capture Falling Latch Interrupt Flag + * | | |This bit is writing 1 to clear. Each bit n controls the corresponding BPWM channel n. + * | | |0 = No capture falling latch condition happened. + * | | |1 = Capture falling latch condition happened, this flag will be set to high. + * |[13] |CAPFIF5 |BPWM Capture Falling Latch Interrupt Flag + * | | |This bit is writing 1 to clear. Each bit n controls the corresponding BPWM channel n. + * | | |0 = No capture falling latch condition happened. + * | | |1 = Capture falling latch condition happened, this flag will be set to high. + * @var BPWM_T::PBUF + * Offset: 0x304 BPWM PERIOD Buffer + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |PBUF |BPWM Period Buffer (Read Only) + * | | |Used as PERIOD active register. + * @var BPWM_T::CMPBUF[6] + * Offset: 0x31C BPWM CMPDAT 0~5 Buffer + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |CMPBUF |BPWM Comparator Buffer (Read Only) + * | | |Used as CMP active register. + */ + __IO uint32_t CTL0; /*!< [0x0000] BPWM Control Register 0 */ + __IO uint32_t CTL1; /*!< [0x0004] BPWM Control Register 1 */ + __I uint32_t RESERVED0[2]; + __IO uint32_t CLKSRC; /*!< [0x0010] BPWM Clock Source Register */ + __IO uint32_t CLKPSC; /*!< [0x0014] BPWM Clock Prescale Register */ + __I uint32_t RESERVED1[2]; + __IO uint32_t CNTEN; /*!< [0x0020] BPWM Counter Enable Register */ + __IO uint32_t CNTCLR; /*!< [0x0024] BPWM Clear Counter Register */ + __I uint32_t RESERVED2[2]; + __IO uint32_t PERIOD; /*!< [0x0030] BPWM Period Register */ + __I uint32_t RESERVED3[7]; + __IO uint32_t CMPDAT[6]; /*!< [0x0050~0x0064] BPWM Comparator Register 0~5 */ + __I uint32_t RESERVED4[10]; + __I uint32_t CNT; /*!< [0x0090] BPWM Counter Register */ + __I uint32_t RESERVED5[7]; + __IO uint32_t WGCTL0; /*!< [0x00b0] BPWM Generation Register 0 */ + __IO uint32_t WGCTL1; /*!< [0x00b4] BPWM Generation Register 1 */ + __IO uint32_t MSKEN; /*!< [0x00b8] BPWM Mask Enable Register */ + __IO uint32_t MSK; /*!< [0x00bc] BPWM Mask Data Register */ + __I uint32_t RESERVED6[5]; + __IO uint32_t POLCTL; /*!< [0x00d4] BPWM Pin Polar Inverse Register */ + __IO uint32_t POEN; /*!< [0x00d8] BPWM Output Enable Register */ + __I uint32_t RESERVED7[1]; + __IO uint32_t INTEN; /*!< [0x00e0] BPWM Interrupt Enable Register */ + __I uint32_t RESERVED8[1]; + __IO uint32_t INTSTS; /*!< [0x00e8] BPWM Interrupt Flag Register */ + __I uint32_t RESERVED9[3]; + __IO uint32_t EADCTS0; /*!< [0x00f8] BPWM Trigger EADC Source Select Register 0 */ + __IO uint32_t EADCTS1; /*!< [0x00fc] BPWM Trigger EADC Source Select Register 1 */ + __I uint32_t RESERVED10[4]; + __IO uint32_t SSCTL; /*!< [0x0110] BPWM Synchronous Start Control Register */ + __O uint32_t SSTRG; /*!< [0x0114] BPWM Synchronous Start Trigger Register */ + __I uint32_t RESERVED11[2]; + __IO uint32_t STATUS; /*!< [0x0120] BPWM Status Register */ + __I uint32_t RESERVED12[55]; + __IO uint32_t CAPINEN; /*!< [0x0200] BPWM Capture Input Enable Register */ + __IO uint32_t CAPCTL; /*!< [0x0204] BPWM Capture Control Register */ + __I uint32_t CAPSTS; /*!< [0x0208] BPWM Capture Status Register */ + BCAPDAT_T CAPDAT[6]; /*!< [0x020c~0x0238] BPWM Rising and Falling Capture Data Register 0~5 */ + __I uint32_t RESERVED13[5]; + __IO uint32_t CAPIEN; /*!< [0x0250] BPWM Capture Interrupt Enable Register */ + __IO uint32_t CAPIF; /*!< [0x0254] BPWM Capture Interrupt Flag Register */ + __I uint32_t RESERVED14[43]; + __I uint32_t PBUF; /*!< [0x0304] BPWM PERIOD Buffer */ + __I uint32_t RESERVED15[5]; + __I uint32_t CMPBUF[6]; /*!< [0x031c~0x0330] BPWM CMPDAT 0~5 Buffer */ + +} BPWM_T; + +/** + @addtogroup BPWM_CONST BPWM Bit Field Definition + Constant Definitions for BPWM Controller + @{ +*/ + +#define BPWM_CTL0_CTRLD0_Pos (0) /*!< BPWM_T::CTL0: CTRLD0 Position */ +#define BPWM_CTL0_CTRLD0_Msk (0x1ul << BPWM_CTL0_CTRLD0_Pos) /*!< BPWM_T::CTL0: CTRLD0 Mask */ + +#define BPWM_CTL0_CTRLD1_Pos (1) /*!< BPWM_T::CTL0: CTRLD1 Position */ +#define BPWM_CTL0_CTRLD1_Msk (0x1ul << BPWM_CTL0_CTRLD1_Pos) /*!< BPWM_T::CTL0: CTRLD1 Mask */ + +#define BPWM_CTL0_CTRLD2_Pos (2) /*!< BPWM_T::CTL0: CTRLD2 Position */ +#define BPWM_CTL0_CTRLD2_Msk (0x1ul << BPWM_CTL0_CTRLD2_Pos) /*!< BPWM_T::CTL0: CTRLD2 Mask */ + +#define BPWM_CTL0_CTRLD3_Pos (3) /*!< BPWM_T::CTL0: CTRLD3 Position */ +#define BPWM_CTL0_CTRLD3_Msk (0x1ul << BPWM_CTL0_CTRLD3_Pos) /*!< BPWM_T::CTL0: CTRLD3 Mask */ + +#define BPWM_CTL0_CTRLD4_Pos (4) /*!< BPWM_T::CTL0: CTRLD4 Position */ +#define BPWM_CTL0_CTRLD4_Msk (0x1ul << BPWM_CTL0_CTRLD4_Pos) /*!< BPWM_T::CTL0: CTRLD4 Mask */ + +#define BPWM_CTL0_CTRLD5_Pos (5) /*!< BPWM_T::CTL0: CTRLD5 Position */ +#define BPWM_CTL0_CTRLD5_Msk (0x1ul << BPWM_CTL0_CTRLD5_Pos) /*!< BPWM_T::CTL0: CTRLD5 Mask */ + +#define BPWM_CTL0_IMMLDEN0_Pos (16) /*!< BPWM_T::CTL0: IMMLDEN0 Position */ +#define BPWM_CTL0_IMMLDEN0_Msk (0x1ul << BPWM_CTL0_IMMLDEN0_Pos) /*!< BPWM_T::CTL0: IMMLDEN0 Mask */ + +#define BPWM_CTL0_IMMLDEN1_Pos (17) /*!< BPWM_T::CTL0: IMMLDEN1 Position */ +#define BPWM_CTL0_IMMLDEN1_Msk (0x1ul << BPWM_CTL0_IMMLDEN1_Pos) /*!< BPWM_T::CTL0: IMMLDEN1 Mask */ + +#define BPWM_CTL0_IMMLDEN2_Pos (18) /*!< BPWM_T::CTL0: IMMLDEN2 Position */ +#define BPWM_CTL0_IMMLDEN2_Msk (0x1ul << BPWM_CTL0_IMMLDEN2_Pos) /*!< BPWM_T::CTL0: IMMLDEN2 Mask */ + +#define BPWM_CTL0_IMMLDEN3_Pos (19) /*!< BPWM_T::CTL0: IMMLDEN3 Position */ +#define BPWM_CTL0_IMMLDEN3_Msk (0x1ul << BPWM_CTL0_IMMLDEN3_Pos) /*!< BPWM_T::CTL0: IMMLDEN3 Mask */ + +#define BPWM_CTL0_IMMLDEN4_Pos (20) /*!< BPWM_T::CTL0: IMMLDEN4 Position */ +#define BPWM_CTL0_IMMLDEN4_Msk (0x1ul << BPWM_CTL0_IMMLDEN4_Pos) /*!< BPWM_T::CTL0: IMMLDEN4 Mask */ + +#define BPWM_CTL0_IMMLDEN5_Pos (21) /*!< BPWM_T::CTL0: IMMLDEN5 Position */ +#define BPWM_CTL0_IMMLDEN5_Msk (0x1ul << BPWM_CTL0_IMMLDEN5_Pos) /*!< BPWM_T::CTL0: IMMLDEN5 Mask */ + +#define BPWM_CTL0_DBGHALT_Pos (30) /*!< BPWM_T::CTL0: DBGHALT Position */ +#define BPWM_CTL0_DBGHALT_Msk (0x1ul << BPWM_CTL0_DBGHALT_Pos) /*!< BPWM_T::CTL0: DBGHALT Mask */ + +#define BPWM_CTL0_DBGTRIOFF_Pos (31) /*!< BPWM_T::CTL0: DBGTRIOFF Position */ +#define BPWM_CTL0_DBGTRIOFF_Msk (0x1ul << BPWM_CTL0_DBGTRIOFF_Pos) /*!< BPWM_T::CTL0: DBGTRIOFF Mask */ + +#define BPWM_CTL1_CNTTYPE0_Pos (0) /*!< BPWM_T::CTL1: CNTTYPE0 Position */ +#define BPWM_CTL1_CNTTYPE0_Msk (0x3ul << BPWM_CTL1_CNTTYPE0_Pos) /*!< BPWM_T::CTL1: CNTTYPE0 Mask */ + +#define BPWM_CLKSRC_ECLKSRC0_Pos (0) /*!< BPWM_T::CLKSRC: ECLKSRC0 Position */ +#define BPWM_CLKSRC_ECLKSRC0_Msk (0x7ul << BPWM_CLKSRC_ECLKSRC0_Pos) /*!< BPWM_T::CLKSRC: ECLKSRC0 Mask */ + +#define BPWM_CLKPSC_CLKPSC_Pos (0) /*!< BPWM_T::CLKPSC: CLKPSC Position */ +#define BPWM_CLKPSC_CLKPSC_Msk (0xffful << BPWM_CLKPSC_CLKPSC_Pos) /*!< BPWM_T::CLKPSC: CLKPSC Mask */ + +#define BPWM_CNTEN_CNTEN0_Pos (0) /*!< BPWM_T::CNTEN: CNTEN0 Position */ +#define BPWM_CNTEN_CNTEN0_Msk (0x1ul << BPWM_CNTEN_CNTEN0_Pos) /*!< BPWM_T::CNTEN: CNTEN0 Mask */ + +#define BPWM_CNTCLR_CNTCLR0_Pos (0) /*!< BPWM_T::CNTCLR: CNTCLR0 Position */ +#define BPWM_CNTCLR_CNTCLR0_Msk (0x1ul << BPWM_CNTCLR_CNTCLR0_Pos) /*!< BPWM_T::CNTCLR: CNTCLR0 Mask */ + +#define BPWM_PERIOD_PERIOD_Pos (0) /*!< BPWM_T::PERIOD: PERIOD Position */ +#define BPWM_PERIOD_PERIOD_Msk (0xfffful << BPWM_PERIOD_PERIOD_Pos) /*!< BPWM_T::PERIOD: PERIOD Mask */ + +#define BPWM_CMPDAT0_CMPDAT_Pos (0) /*!< BPWM_T::CMPDAT0: CMPDAT Position */ +#define BPWM_CMPDAT0_CMPDAT_Msk (0xfffful << BPWM_CMPDAT0_CMPDAT_Pos) /*!< BPWM_T::CMPDAT0: CMPDAT Mask */ + +#define BPWM_CMPDAT1_CMPDAT_Pos (0) /*!< BPWM_T::CMPDAT1: CMPDAT Position */ +#define BPWM_CMPDAT1_CMPDAT_Msk (0xfffful << BPWM_CMPDAT1_CMPDAT_Pos) /*!< BPWM_T::CMPDAT1: CMPDAT Mask */ + +#define BPWM_CMPDAT2_CMPDAT_Pos (0) /*!< BPWM_T::CMPDAT2: CMPDAT Position */ +#define BPWM_CMPDAT2_CMPDAT_Msk (0xfffful << BPWM_CMPDAT2_CMPDAT_Pos) /*!< BPWM_T::CMPDAT2: CMPDAT Mask */ + +#define BPWM_CMPDAT3_CMPDAT_Pos (0) /*!< BPWM_T::CMPDAT3: CMPDAT Position */ +#define BPWM_CMPDAT3_CMPDAT_Msk (0xfffful << BPWM_CMPDAT3_CMPDAT_Pos) /*!< BPWM_T::CMPDAT3: CMPDAT Mask */ + +#define BPWM_CMPDAT4_CMPDAT_Pos (0) /*!< BPWM_T::CMPDAT4: CMPDAT Position */ +#define BPWM_CMPDAT4_CMPDAT_Msk (0xfffful << BPWM_CMPDAT4_CMPDAT_Pos) /*!< BPWM_T::CMPDAT4: CMPDAT Mask */ + +#define BPWM_CMPDAT5_CMPDAT_Pos (0) /*!< BPWM_T::CMPDAT5: CMPDAT Position */ +#define BPWM_CMPDAT5_CMPDAT_Msk (0xfffful << BPWM_CMPDAT5_CMPDAT_Pos) /*!< BPWM_T::CMPDAT5: CMPDAT Mask */ + +#define BPWM_CNT_CNT_Pos (0) /*!< BPWM_T::CNT: CNT Position */ +#define BPWM_CNT_CNT_Msk (0xfffful << BPWM_CNT_CNT_Pos) /*!< BPWM_T::CNT: CNT Mask */ + +#define BPWM_CNT_DIRF_Pos (16) /*!< BPWM_T::CNT: DIRF Position */ +#define BPWM_CNT_DIRF_Msk (0x1ul << BPWM_CNT_DIRF_Pos) /*!< BPWM_T::CNT: DIRF Mask */ + +#define BPWM_WGCTL0_ZPCTL0_Pos (0) /*!< BPWM_T::WGCTL0: ZPCTL0 Position */ +#define BPWM_WGCTL0_ZPCTL0_Msk (0x3ul << BPWM_WGCTL0_ZPCTL0_Pos) /*!< BPWM_T::WGCTL0: ZPCTL0 Mask */ + +#define BPWM_WGCTL0_ZPCTL1_Pos (2) /*!< BPWM_T::WGCTL0: ZPCTL1 Position */ +#define BPWM_WGCTL0_ZPCTL1_Msk (0x3ul << BPWM_WGCTL0_ZPCTL1_Pos) /*!< BPWM_T::WGCTL0: ZPCTL1 Mask */ + +#define BPWM_WGCTL0_ZPCTL2_Pos (4) /*!< BPWM_T::WGCTL0: ZPCTL2 Position */ +#define BPWM_WGCTL0_ZPCTL2_Msk (0x3ul << BPWM_WGCTL0_ZPCTL2_Pos) /*!< BPWM_T::WGCTL0: ZPCTL2 Mask */ + +#define BPWM_WGCTL0_ZPCTL3_Pos (6) /*!< BPWM_T::WGCTL0: ZPCTL3 Position */ +#define BPWM_WGCTL0_ZPCTL3_Msk (0x3ul << BPWM_WGCTL0_ZPCTL3_Pos) /*!< BPWM_T::WGCTL0: ZPCTL3 Mask */ + +#define BPWM_WGCTL0_ZPCTL4_Pos (8) /*!< BPWM_T::WGCTL0: ZPCTL4 Position */ +#define BPWM_WGCTL0_ZPCTL4_Msk (0x3ul << BPWM_WGCTL0_ZPCTL4_Pos) /*!< BPWM_T::WGCTL0: ZPCTL4 Mask */ + +#define BPWM_WGCTL0_ZPCTL5_Pos (10) /*!< BPWM_T::WGCTL0: ZPCTL5 Position */ +#define BPWM_WGCTL0_ZPCTL5_Msk (0x3ul << BPWM_WGCTL0_ZPCTL5_Pos) /*!< BPWM_T::WGCTL0: ZPCTL5 Mask */ + +#define BPWM_WGCTL0_ZPCTLn_Pos (0) /*!< BPWM_T::WGCTL0: ZPCTLn Position */ +#define BPWM_WGCTL0_ZPCTLn_Msk (0xffful << BPWM_WGCTL0_ZPCTLn_Pos) /*!< BPWM_T::WGCTL0: ZPCTLn Mask */ + +#define BPWM_WGCTL0_PRDPCTL0_Pos (16) /*!< BPWM_T::WGCTL0: PRDPCTL0 Position */ +#define BPWM_WGCTL0_PRDPCTL0_Msk (0x3ul << BPWM_WGCTL0_PRDPCTL0_Pos) /*!< BPWM_T::WGCTL0: PRDPCTL0 Mask */ + +#define BPWM_WGCTL0_PRDPCTL1_Pos (18) /*!< BPWM_T::WGCTL0: PRDPCTL1 Position */ +#define BPWM_WGCTL0_PRDPCTL1_Msk (0x3ul << BPWM_WGCTL0_PRDPCTL1_Pos) /*!< BPWM_T::WGCTL0: PRDPCTL1 Mask */ + +#define BPWM_WGCTL0_PRDPCTL2_Pos (20) /*!< BPWM_T::WGCTL0: PRDPCTL2 Position */ +#define BPWM_WGCTL0_PRDPCTL2_Msk (0x3ul << BPWM_WGCTL0_PRDPCTL2_Pos) /*!< BPWM_T::WGCTL0: PRDPCTL2 Mask */ + +#define BPWM_WGCTL0_PRDPCTL3_Pos (22) /*!< BPWM_T::WGCTL0: PRDPCTL3 Position */ +#define BPWM_WGCTL0_PRDPCTL3_Msk (0x3ul << BPWM_WGCTL0_PRDPCTL3_Pos) /*!< BPWM_T::WGCTL0: PRDPCTL3 Mask */ + +#define BPWM_WGCTL0_PRDPCTL4_Pos (24) /*!< BPWM_T::WGCTL0: PRDPCTL4 Position */ +#define BPWM_WGCTL0_PRDPCTL4_Msk (0x3ul << BPWM_WGCTL0_PRDPCTL4_Pos) /*!< BPWM_T::WGCTL0: PRDPCTL4 Mask */ + +#define BPWM_WGCTL0_PRDPCTL5_Pos (26) /*!< BPWM_T::WGCTL0: PRDPCTL5 Position */ +#define BPWM_WGCTL0_PRDPCTL5_Msk (0x3ul << BPWM_WGCTL0_PRDPCTL5_Pos) /*!< BPWM_T::WGCTL0: PRDPCTL5 Mask */ + +#define BPWM_WGCTL0_PRDPCTLn_Pos (16) /*!< BPWM_T::WGCTL0: PRDPCTLn Position */ +#define BPWM_WGCTL0_PRDPCTLn_Msk (0xffful << BPWM_WGCTL0_PRDPCTLn_Pos) /*!< BPWM_T::WGCTL0: PRDPCTLn Mask */ + +#define BPWM_WGCTL1_CMPUCTL0_Pos (0) /*!< BPWM_T::WGCTL1: CMPUCTL0 Position */ +#define BPWM_WGCTL1_CMPUCTL0_Msk (0x3ul << BPWM_WGCTL1_CMPUCTL0_Pos) /*!< BPWM_T::WGCTL1: CMPUCTL0 Mask */ + +#define BPWM_WGCTL1_CMPUCTL1_Pos (2) /*!< BPWM_T::WGCTL1: CMPUCTL1 Position */ +#define BPWM_WGCTL1_CMPUCTL1_Msk (0x3ul << BPWM_WGCTL1_CMPUCTL1_Pos) /*!< BPWM_T::WGCTL1: CMPUCTL1 Mask */ + +#define BPWM_WGCTL1_CMPUCTL2_Pos (4) /*!< BPWM_T::WGCTL1: CMPUCTL2 Position */ +#define BPWM_WGCTL1_CMPUCTL2_Msk (0x3ul << BPWM_WGCTL1_CMPUCTL2_Pos) /*!< BPWM_T::WGCTL1: CMPUCTL2 Mask */ + +#define BPWM_WGCTL1_CMPUCTL3_Pos (6) /*!< BPWM_T::WGCTL1: CMPUCTL3 Position */ +#define BPWM_WGCTL1_CMPUCTL3_Msk (0x3ul << BPWM_WGCTL1_CMPUCTL3_Pos) /*!< BPWM_T::WGCTL1: CMPUCTL3 Mask */ + +#define BPWM_WGCTL1_CMPUCTL4_Pos (8) /*!< BPWM_T::WGCTL1: CMPUCTL4 Position */ +#define BPWM_WGCTL1_CMPUCTL4_Msk (0x3ul << BPWM_WGCTL1_CMPUCTL4_Pos) /*!< BPWM_T::WGCTL1: CMPUCTL4 Mask */ + +#define BPWM_WGCTL1_CMPUCTL5_Pos (10) /*!< BPWM_T::WGCTL1: CMPUCTL5 Position */ +#define BPWM_WGCTL1_CMPUCTL5_Msk (0x3ul << BPWM_WGCTL1_CMPUCTL5_Pos) /*!< BPWM_T::WGCTL1: CMPUCTL5 Mask */ + +#define BPWM_WGCTL1_CMPUCTLn_Pos (0) /*!< BPWM_T::WGCTL1: CMPUCTLn Position */ +#define BPWM_WGCTL1_CMPUCTLn_Msk (0xffful << BPWM_WGCTL1_CMPUCTLn_Pos) /*!< BPWM_T::WGCTL1: CMPUCTLn Mask */ + +#define BPWM_WGCTL1_CMPDCTL0_Pos (16) /*!< BPWM_T::WGCTL1: CMPDCTL0 Position */ +#define BPWM_WGCTL1_CMPDCTL0_Msk (0x3ul << BPWM_WGCTL1_CMPDCTL0_Pos) /*!< BPWM_T::WGCTL1: CMPDCTL0 Mask */ + +#define BPWM_WGCTL1_CMPDCTL1_Pos (18) /*!< BPWM_T::WGCTL1: CMPDCTL1 Position */ +#define BPWM_WGCTL1_CMPDCTL1_Msk (0x3ul << BPWM_WGCTL1_CMPDCTL1_Pos) /*!< BPWM_T::WGCTL1: CMPDCTL1 Mask */ + +#define BPWM_WGCTL1_CMPDCTL2_Pos (20) /*!< BPWM_T::WGCTL1: CMPDCTL2 Position */ +#define BPWM_WGCTL1_CMPDCTL2_Msk (0x3ul << BPWM_WGCTL1_CMPDCTL2_Pos) /*!< BPWM_T::WGCTL1: CMPDCTL2 Mask */ + +#define BPWM_WGCTL1_CMPDCTL3_Pos (22) /*!< BPWM_T::WGCTL1: CMPDCTL3 Position */ +#define BPWM_WGCTL1_CMPDCTL3_Msk (0x3ul << BPWM_WGCTL1_CMPDCTL3_Pos) /*!< BPWM_T::WGCTL1: CMPDCTL3 Mask */ + +#define BPWM_WGCTL1_CMPDCTL4_Pos (24) /*!< BPWM_T::WGCTL1: CMPDCTL4 Position */ +#define BPWM_WGCTL1_CMPDCTL4_Msk (0x3ul << BPWM_WGCTL1_CMPDCTL4_Pos) /*!< BPWM_T::WGCTL1: CMPDCTL4 Mask */ + +#define BPWM_WGCTL1_CMPDCTL5_Pos (26) /*!< BPWM_T::WGCTL1: CMPDCTL5 Position */ +#define BPWM_WGCTL1_CMPDCTL5_Msk (0x3ul << BPWM_WGCTL1_CMPDCTL5_Pos) /*!< BPWM_T::WGCTL1: CMPDCTL5 Mask */ + +#define BPWM_WGCTL1_CMPDCTLn_Pos (16) /*!< BPWM_T::WGCTL1: CMPDCTLn Position */ +#define BPWM_WGCTL1_CMPDCTLn_Msk (0xffful << BPWM_WGCTL1_CMPDCTLn_Pos) /*!< BPWM_T::WGCTL1: CMPDCTLn Mask */ + +#define BPWM_MSKEN_MSKEN0_Pos (0) /*!< BPWM_T::MSKEN: MSKEN0 Position */ +#define BPWM_MSKEN_MSKEN0_Msk (0x1ul << BPWM_MSKEN_MSKEN0_Pos) /*!< BPWM_T::MSKEN: MSKEN0 Mask */ + +#define BPWM_MSKEN_MSKEN1_Pos (1) /*!< BPWM_T::MSKEN: MSKEN1 Position */ +#define BPWM_MSKEN_MSKEN1_Msk (0x1ul << BPWM_MSKEN_MSKEN1_Pos) /*!< BPWM_T::MSKEN: MSKEN1 Mask */ + +#define BPWM_MSKEN_MSKEN2_Pos (2) /*!< BPWM_T::MSKEN: MSKEN2 Position */ +#define BPWM_MSKEN_MSKEN2_Msk (0x1ul << BPWM_MSKEN_MSKEN2_Pos) /*!< BPWM_T::MSKEN: MSKEN2 Mask */ + +#define BPWM_MSKEN_MSKEN3_Pos (3) /*!< BPWM_T::MSKEN: MSKEN3 Position */ +#define BPWM_MSKEN_MSKEN3_Msk (0x1ul << BPWM_MSKEN_MSKEN3_Pos) /*!< BPWM_T::MSKEN: MSKEN3 Mask */ + +#define BPWM_MSKEN_MSKEN4_Pos (4) /*!< BPWM_T::MSKEN: MSKEN4 Position */ +#define BPWM_MSKEN_MSKEN4_Msk (0x1ul << BPWM_MSKEN_MSKEN4_Pos) /*!< BPWM_T::MSKEN: MSKEN4 Mask */ + +#define BPWM_MSKEN_MSKEN5_Pos (5) /*!< BPWM_T::MSKEN: MSKEN5 Position */ +#define BPWM_MSKEN_MSKEN5_Msk (0x1ul << BPWM_MSKEN_MSKEN5_Pos) /*!< BPWM_T::MSKEN: MSKEN5 Mask */ + +#define BPWM_MSKEN_MSKENn_Pos (0) /*!< BPWM_T::MSKEN: MSKENn Position */ +#define BPWM_MSKEN_MSKENn_Msk (0x3ful << BPWM_MSKEN_MSKENn_Pos) /*!< BPWM_T::MSKEN: MSKENn Mask */ + +#define BPWM_MSK_MSKDAT0_Pos (0) /*!< BPWM_T::MSK: MSKDAT0 Position */ +#define BPWM_MSK_MSKDAT0_Msk (0x1ul << BPWM_MSK_MSKDAT0_Pos) /*!< BPWM_T::MSK: MSKDAT0 Mask */ + +#define BPWM_MSK_MSKDAT1_Pos (1) /*!< BPWM_T::MSK: MSKDAT1 Position */ +#define BPWM_MSK_MSKDAT1_Msk (0x1ul << BPWM_MSK_MSKDAT1_Pos) /*!< BPWM_T::MSK: MSKDAT1 Mask */ + +#define BPWM_MSK_MSKDAT2_Pos (2) /*!< BPWM_T::MSK: MSKDAT2 Position */ +#define BPWM_MSK_MSKDAT2_Msk (0x1ul << BPWM_MSK_MSKDAT2_Pos) /*!< BPWM_T::MSK: MSKDAT2 Mask */ + +#define BPWM_MSK_MSKDAT3_Pos (3) /*!< BPWM_T::MSK: MSKDAT3 Position */ +#define BPWM_MSK_MSKDAT3_Msk (0x1ul << BPWM_MSK_MSKDAT3_Pos) /*!< BPWM_T::MSK: MSKDAT3 Mask */ + +#define BPWM_MSK_MSKDAT4_Pos (4) /*!< BPWM_T::MSK: MSKDAT4 Position */ +#define BPWM_MSK_MSKDAT4_Msk (0x1ul << BPWM_MSK_MSKDAT4_Pos) /*!< BPWM_T::MSK: MSKDAT4 Mask */ + +#define BPWM_MSK_MSKDAT5_Pos (5) /*!< BPWM_T::MSK: MSKDAT5 Position */ +#define BPWM_MSK_MSKDAT5_Msk (0x1ul << BPWM_MSK_MSKDAT5_Pos) /*!< BPWM_T::MSK: MSKDAT5 Mask */ + +#define BPWM_MSK_MSKDATn_Pos (0) /*!< BPWM_T::MSK: MSKDATn Position */ +#define BPWM_MSK_MSKDATn_Msk (0x3ful << BPWM_MSK_MSKDATn_Pos) /*!< BPWM_T::MSK: MSKDATn Mask */ + +#define BPWM_POLCTL_PINV0_Pos (0) /*!< BPWM_T::POLCTL: PINV0 Position */ +#define BPWM_POLCTL_PINV0_Msk (0x1ul << BPWM_POLCTL_PINV0_Pos) /*!< BPWM_T::POLCTL: PINV0 Mask */ + +#define BPWM_POLCTL_PINV1_Pos (1) /*!< BPWM_T::POLCTL: PINV1 Position */ +#define BPWM_POLCTL_PINV1_Msk (0x1ul << BPWM_POLCTL_PINV1_Pos) /*!< BPWM_T::POLCTL: PINV1 Mask */ + +#define BPWM_POLCTL_PINV2_Pos (2) /*!< BPWM_T::POLCTL: PINV2 Position */ +#define BPWM_POLCTL_PINV2_Msk (0x1ul << BPWM_POLCTL_PINV2_Pos) /*!< BPWM_T::POLCTL: PINV2 Mask */ + +#define BPWM_POLCTL_PINV3_Pos (3) /*!< BPWM_T::POLCTL: PINV3 Position */ +#define BPWM_POLCTL_PINV3_Msk (0x1ul << BPWM_POLCTL_PINV3_Pos) /*!< BPWM_T::POLCTL: PINV3 Mask */ + +#define BPWM_POLCTL_PINV4_Pos (4) /*!< BPWM_T::POLCTL: PINV4 Position */ +#define BPWM_POLCTL_PINV4_Msk (0x1ul << BPWM_POLCTL_PINV4_Pos) /*!< BPWM_T::POLCTL: PINV4 Mask */ + +#define BPWM_POLCTL_PINV5_Pos (5) /*!< BPWM_T::POLCTL: PINV5 Position */ +#define BPWM_POLCTL_PINV5_Msk (0x1ul << BPWM_POLCTL_PINV5_Pos) /*!< BPWM_T::POLCTL: PINV5 Mask */ + +#define BPWM_POLCTL_PINVn_Pos (0) /*!< BPWM_T::POLCTL: PINVn Position */ +#define BPWM_POLCTL_PINVn_Msk (0x3ful << BPWM_POLCTL_PINVn_Pos) /*!< BPWM_T::POLCTL: PINVn Mask */ + +#define BPWM_POEN_POEN0_Pos (0) /*!< BPWM_T::POEN: POEN0 Position */ +#define BPWM_POEN_POEN0_Msk (0x1ul << BPWM_POEN_POEN0_Pos) /*!< BPWM_T::POEN: POEN0 Mask */ + +#define BPWM_POEN_POEN1_Pos (1) /*!< BPWM_T::POEN: POEN1 Position */ +#define BPWM_POEN_POEN1_Msk (0x1ul << BPWM_POEN_POEN1_Pos) /*!< BPWM_T::POEN: POEN1 Mask */ + +#define BPWM_POEN_POEN2_Pos (2) /*!< BPWM_T::POEN: POEN2 Position */ +#define BPWM_POEN_POEN2_Msk (0x1ul << BPWM_POEN_POEN2_Pos) /*!< BPWM_T::POEN: POEN2 Mask */ + +#define BPWM_POEN_POEN3_Pos (3) /*!< BPWM_T::POEN: POEN3 Position */ +#define BPWM_POEN_POEN3_Msk (0x1ul << BPWM_POEN_POEN3_Pos) /*!< BPWM_T::POEN: POEN3 Mask */ + +#define BPWM_POEN_POEN4_Pos (4) /*!< BPWM_T::POEN: POEN4 Position */ +#define BPWM_POEN_POEN4_Msk (0x1ul << BPWM_POEN_POEN4_Pos) /*!< BPWM_T::POEN: POEN4 Mask */ + +#define BPWM_POEN_POEN5_Pos (5) /*!< BPWM_T::POEN: POEN5 Position */ +#define BPWM_POEN_POEN5_Msk (0x1ul << BPWM_POEN_POEN5_Pos) /*!< BPWM_T::POEN: POEN5 Mask */ + +#define BPWM_POEN_POENn_Pos (0) /*!< BPWM_T::POEN: POENn Position */ +#define BPWM_POEN_POENn_Msk (0x3ful << BPWM_POEN_POENn_Pos) /*!< BPWM_T::POEN: POENn Mask */ + +#define BPWM_INTEN_ZIEN0_Pos (0) /*!< BPWM_T::INTEN: ZIEN0 Position */ +#define BPWM_INTEN_ZIEN0_Msk (0x1ul << BPWM_INTEN_ZIEN0_Pos) /*!< BPWM_T::INTEN: ZIEN0 Mask */ + +#define BPWM_INTEN_PIEN0_Pos (8) /*!< BPWM_T::INTEN: PIEN0 Position */ +#define BPWM_INTEN_PIEN0_Msk (0x1ul << BPWM_INTEN_PIEN0_Pos) /*!< BPWM_T::INTEN: PIEN0 Mask */ + +#define BPWM_INTEN_CMPUIEN0_Pos (16) /*!< BPWM_T::INTEN: CMPUIEN0 Position */ +#define BPWM_INTEN_CMPUIEN0_Msk (0x1ul << BPWM_INTEN_CMPUIEN0_Pos) /*!< BPWM_T::INTEN: CMPUIEN0 Mask */ + +#define BPWM_INTEN_CMPUIEN1_Pos (17) /*!< BPWM_T::INTEN: CMPUIEN1 Position */ +#define BPWM_INTEN_CMPUIEN1_Msk (0x1ul << BPWM_INTEN_CMPUIEN1_Pos) /*!< BPWM_T::INTEN: CMPUIEN1 Mask */ + +#define BPWM_INTEN_CMPUIEN2_Pos (18) /*!< BPWM_T::INTEN: CMPUIEN2 Position */ +#define BPWM_INTEN_CMPUIEN2_Msk (0x1ul << BPWM_INTEN_CMPUIEN2_Pos) /*!< BPWM_T::INTEN: CMPUIEN2 Mask */ + +#define BPWM_INTEN_CMPUIEN3_Pos (19) /*!< BPWM_T::INTEN: CMPUIEN3 Position */ +#define BPWM_INTEN_CMPUIEN3_Msk (0x1ul << BPWM_INTEN_CMPUIEN3_Pos) /*!< BPWM_T::INTEN: CMPUIEN3 Mask */ + +#define BPWM_INTEN_CMPUIEN4_Pos (20) /*!< BPWM_T::INTEN: CMPUIEN4 Position */ +#define BPWM_INTEN_CMPUIEN4_Msk (0x1ul << BPWM_INTEN_CMPUIEN4_Pos) /*!< BPWM_T::INTEN: CMPUIEN4 Mask */ + +#define BPWM_INTEN_CMPUIEN5_Pos (21) /*!< BPWM_T::INTEN: CMPUIEN5 Position */ +#define BPWM_INTEN_CMPUIEN5_Msk (0x1ul << BPWM_INTEN_CMPUIEN5_Pos) /*!< BPWM_T::INTEN: CMPUIEN5 Mask */ + +#define BPWM_INTEN_CMPUIENn_Pos (16) /*!< BPWM_T::INTEN: CMPUIENn Position */ +#define BPWM_INTEN_CMPUIENn_Msk (0x3ful << BPWM_INTEN_CMPUIENn_Pos) /*!< BPWM_T::INTEN: CMPUIENn Mask */ + +#define BPWM_INTEN_CMPDIEN0_Pos (24) /*!< BPWM_T::INTEN: CMPDIEN0 Position */ +#define BPWM_INTEN_CMPDIEN0_Msk (0x1ul << BPWM_INTEN_CMPDIEN0_Pos) /*!< BPWM_T::INTEN: CMPDIEN0 Mask */ + +#define BPWM_INTEN_CMPDIEN1_Pos (25) /*!< BPWM_T::INTEN: CMPDIEN1 Position */ +#define BPWM_INTEN_CMPDIEN1_Msk (0x1ul << BPWM_INTEN_CMPDIEN1_Pos) /*!< BPWM_T::INTEN: CMPDIEN1 Mask */ + +#define BPWM_INTEN_CMPDIEN2_Pos (26) /*!< BPWM_T::INTEN: CMPDIEN2 Position */ +#define BPWM_INTEN_CMPDIEN2_Msk (0x1ul << BPWM_INTEN_CMPDIEN2_Pos) /*!< BPWM_T::INTEN: CMPDIEN2 Mask */ + +#define BPWM_INTEN_CMPDIEN3_Pos (27) /*!< BPWM_T::INTEN: CMPDIEN3 Position */ +#define BPWM_INTEN_CMPDIEN3_Msk (0x1ul << BPWM_INTEN_CMPDIEN3_Pos) /*!< BPWM_T::INTEN: CMPDIEN3 Mask */ + +#define BPWM_INTEN_CMPDIEN4_Pos (28) /*!< BPWM_T::INTEN: CMPDIEN4 Position */ +#define BPWM_INTEN_CMPDIEN4_Msk (0x1ul << BPWM_INTEN_CMPDIEN4_Pos) /*!< BPWM_T::INTEN: CMPDIEN4 Mask */ + +#define BPWM_INTEN_CMPDIEN5_Pos (29) /*!< BPWM_T::INTEN: CMPDIEN5 Position */ +#define BPWM_INTEN_CMPDIEN5_Msk (0x1ul << BPWM_INTEN_CMPDIEN5_Pos) /*!< BPWM_T::INTEN: CMPDIEN5 Mask */ + +#define BPWM_INTEN_CMPDIENn_Pos (24) /*!< BPWM_T::INTEN: CMPDIENn Position */ +#define BPWM_INTEN_CMPDIENn_Msk (0x3ful << BPWM_INTEN_CMPDIENn_Pos) /*!< BPWM_T::INTEN: CMPDIENn Mask */ + +#define BPWM_INTSTS_ZIF0_Pos (0) /*!< BPWM_T::INTSTS: ZIF0 Position */ +#define BPWM_INTSTS_ZIF0_Msk (0x1ul << BPWM_INTSTS_ZIF0_Pos) /*!< BPWM_T::INTSTS: ZIF0 Mask */ + +#define BPWM_INTSTS_PIF0_Pos (8) /*!< BPWM_T::INTSTS: PIF0 Position */ +#define BPWM_INTSTS_PIF0_Msk (0x1ul << BPWM_INTSTS_PIF0_Pos) /*!< BPWM_T::INTSTS: PIF0 Mask */ + +#define BPWM_INTSTS_CMPUIF0_Pos (16) /*!< BPWM_T::INTSTS: CMPUIF0 Position */ +#define BPWM_INTSTS_CMPUIF0_Msk (0x1ul << BPWM_INTSTS_CMPUIF0_Pos) /*!< BPWM_T::INTSTS: CMPUIF0 Mask */ + +#define BPWM_INTSTS_CMPUIF1_Pos (17) /*!< BPWM_T::INTSTS: CMPUIF1 Position */ +#define BPWM_INTSTS_CMPUIF1_Msk (0x1ul << BPWM_INTSTS_CMPUIF1_Pos) /*!< BPWM_T::INTSTS: CMPUIF1 Mask */ + +#define BPWM_INTSTS_CMPUIF2_Pos (18) /*!< BPWM_T::INTSTS: CMPUIF2 Position */ +#define BPWM_INTSTS_CMPUIF2_Msk (0x1ul << BPWM_INTSTS_CMPUIF2_Pos) /*!< BPWM_T::INTSTS: CMPUIF2 Mask */ + +#define BPWM_INTSTS_CMPUIF3_Pos (19) /*!< BPWM_T::INTSTS: CMPUIF3 Position */ +#define BPWM_INTSTS_CMPUIF3_Msk (0x1ul << BPWM_INTSTS_CMPUIF3_Pos) /*!< BPWM_T::INTSTS: CMPUIF3 Mask */ + +#define BPWM_INTSTS_CMPUIF4_Pos (20) /*!< BPWM_T::INTSTS: CMPUIF4 Position */ +#define BPWM_INTSTS_CMPUIF4_Msk (0x1ul << BPWM_INTSTS_CMPUIF4_Pos) /*!< BPWM_T::INTSTS: CMPUIF4 Mask */ + +#define BPWM_INTSTS_CMPUIF5_Pos (21) /*!< BPWM_T::INTSTS: CMPUIF5 Position */ +#define BPWM_INTSTS_CMPUIF5_Msk (0x1ul << BPWM_INTSTS_CMPUIF5_Pos) /*!< BPWM_T::INTSTS: CMPUIF5 Mask */ + +#define BPWM_INTSTS_CMPUIFn_Pos (16) /*!< BPWM_T::INTSTS: CMPUIFn Position */ +#define BPWM_INTSTS_CMPUIFn_Msk (0x3ful << BPWM_INTSTS_CMPUIFn_Pos) /*!< BPWM_T::INTSTS: CMPUIFn Mask */ + +#define BPWM_INTSTS_CMPDIF0_Pos (24) /*!< BPWM_T::INTSTS: CMPDIF0 Position */ +#define BPWM_INTSTS_CMPDIF0_Msk (0x1ul << BPWM_INTSTS_CMPDIF0_Pos) /*!< BPWM_T::INTSTS: CMPDIF0 Mask */ + +#define BPWM_INTSTS_CMPDIF1_Pos (25) /*!< BPWM_T::INTSTS: CMPDIF1 Position */ +#define BPWM_INTSTS_CMPDIF1_Msk (0x1ul << BPWM_INTSTS_CMPDIF1_Pos) /*!< BPWM_T::INTSTS: CMPDIF1 Mask */ + +#define BPWM_INTSTS_CMPDIF2_Pos (26) /*!< BPWM_T::INTSTS: CMPDIF2 Position */ +#define BPWM_INTSTS_CMPDIF2_Msk (0x1ul << BPWM_INTSTS_CMPDIF2_Pos) /*!< BPWM_T::INTSTS: CMPDIF2 Mask */ + +#define BPWM_INTSTS_CMPDIF3_Pos (27) /*!< BPWM_T::INTSTS: CMPDIF3 Position */ +#define BPWM_INTSTS_CMPDIF3_Msk (0x1ul << BPWM_INTSTS_CMPDIF3_Pos) /*!< BPWM_T::INTSTS: CMPDIF3 Mask */ + +#define BPWM_INTSTS_CMPDIF4_Pos (28) /*!< BPWM_T::INTSTS: CMPDIF4 Position */ +#define BPWM_INTSTS_CMPDIF4_Msk (0x1ul << BPWM_INTSTS_CMPDIF4_Pos) /*!< BPWM_T::INTSTS: CMPDIF4 Mask */ + +#define BPWM_INTSTS_CMPDIF5_Pos (29) /*!< BPWM_T::INTSTS: CMPDIF5 Position */ +#define BPWM_INTSTS_CMPDIF5_Msk (0x1ul << BPWM_INTSTS_CMPDIF5_Pos) /*!< BPWM_T::INTSTS: CMPDIF5 Mask */ + +#define BPWM_INTSTS_CMPDIFn_Pos (24) /*!< BPWM_T::INTSTS: CMPDIFn Position */ +#define BPWM_INTSTS_CMPDIFn_Msk (0x3ful << BPWM_INTSTS_CMPDIFn_Pos) /*!< BPWM_T::INTSTS: CMPDIFn Mask */ + +#define BPWM_EADCTS0_TRGSEL0_Pos (0) /*!< BPWM_T::EADCTS0: TRGSEL0 Position */ +#define BPWM_EADCTS0_TRGSEL0_Msk (0xful << BPWM_EADCTS0_TRGSEL0_Pos) /*!< BPWM_T::EADCTS0: TRGSEL0 Mask */ + +#define BPWM_EADCTS0_TRGEN0_Pos (7) /*!< BPWM_T::EADCTS0: TRGEN0 Position */ +#define BPWM_EADCTS0_TRGEN0_Msk (0x1ul << BPWM_EADCTS0_TRGEN0_Pos) /*!< BPWM_T::EADCTS0: TRGEN0 Mask */ + +#define BPWM_EADCTS0_TRGSEL1_Pos (8) /*!< BPWM_T::EADCTS0: TRGSEL1 Position */ +#define BPWM_EADCTS0_TRGSEL1_Msk (0xful << BPWM_EADCTS0_TRGSEL1_Pos) /*!< BPWM_T::EADCTS0: TRGSEL1 Mask */ + +#define BPWM_EADCTS0_TRGEN1_Pos (15) /*!< BPWM_T::EADCTS0: TRGEN1 Position */ +#define BPWM_EADCTS0_TRGEN1_Msk (0x1ul << BPWM_EADCTS0_TRGEN1_Pos) /*!< BPWM_T::EADCTS0: TRGEN1 Mask */ + +#define BPWM_EADCTS0_TRGSEL2_Pos (16) /*!< BPWM_T::EADCTS0: TRGSEL2 Position */ +#define BPWM_EADCTS0_TRGSEL2_Msk (0xful << BPWM_EADCTS0_TRGSEL2_Pos) /*!< BPWM_T::EADCTS0: TRGSEL2 Mask */ + +#define BPWM_EADCTS0_TRGEN2_Pos (23) /*!< BPWM_T::EADCTS0: TRGEN2 Position */ +#define BPWM_EADCTS0_TRGEN2_Msk (0x1ul << BPWM_EADCTS0_TRGEN2_Pos) /*!< BPWM_T::EADCTS0: TRGEN2 Mask */ + +#define BPWM_EADCTS0_TRGSEL3_Pos (24) /*!< BPWM_T::EADCTS0: TRGSEL3 Position */ +#define BPWM_EADCTS0_TRGSEL3_Msk (0xful << BPWM_EADCTS0_TRGSEL3_Pos) /*!< BPWM_T::EADCTS0: TRGSEL3 Mask */ + +#define BPWM_EADCTS0_TRGEN3_Pos (31) /*!< BPWM_T::EADCTS0: TRGEN3 Position */ +#define BPWM_EADCTS0_TRGEN3_Msk (0x1ul << BPWM_EADCTS0_TRGEN3_Pos) /*!< BPWM_T::EADCTS0: TRGEN3 Mask */ + +#define BPWM_EADCTS1_TRGSEL4_Pos (0) /*!< BPWM_T::EADCTS1: TRGSEL4 Position */ +#define BPWM_EADCTS1_TRGSEL4_Msk (0xful << BPWM_EADCTS1_TRGSEL4_Pos) /*!< BPWM_T::EADCTS1: TRGSEL4 Mask */ + +#define BPWM_EADCTS1_TRGEN4_Pos (7) /*!< BPWM_T::EADCTS1: TRGEN4 Position */ +#define BPWM_EADCTS1_TRGEN4_Msk (0x1ul << BPWM_EADCTS1_TRGEN4_Pos) /*!< BPWM_T::EADCTS1: TRGEN4 Mask */ + +#define BPWM_EADCTS1_TRGSEL5_Pos (8) /*!< BPWM_T::EADCTS1: TRGSEL5 Position */ +#define BPWM_EADCTS1_TRGSEL5_Msk (0xful << BPWM_EADCTS1_TRGSEL5_Pos) /*!< BPWM_T::EADCTS1: TRGSEL5 Mask */ + +#define BPWM_EADCTS1_TRGEN5_Pos (15) /*!< BPWM_T::EADCTS1: TRGEN5 Position */ +#define BPWM_EADCTS1_TRGEN5_Msk (0x1ul << BPWM_EADCTS1_TRGEN5_Pos) /*!< BPWM_T::EADCTS1: TRGEN5 Mask */ + +#define BPWM_SSCTL_SSEN0_Pos (0) /*!< BPWM_T::SSCTL: SSEN0 Position */ +#define BPWM_SSCTL_SSEN0_Msk (0x1ul << BPWM_SSCTL_SSEN0_Pos) /*!< BPWM_T::SSCTL: SSEN0 Mask */ + +#define BPWM_SSCTL_SSRC_Pos (8) /*!< BPWM_T::SSCTL: SSRC Position */ +#define BPWM_SSCTL_SSRC_Msk (0x3ul << BPWM_SSCTL_SSRC_Pos) /*!< BPWM_T::SSCTL: SSRC Mask */ + +#define BPWM_SSTRG_CNTSEN_Pos (0) /*!< BPWM_T::SSTRG: CNTSEN Position */ +#define BPWM_SSTRG_CNTSEN_Msk (0x1ul << BPWM_SSTRG_CNTSEN_Pos) /*!< BPWM_T::SSTRG: CNTSEN Mask */ + +#define BPWM_STATUS_CNTMAX0_Pos (0) /*!< BPWM_T::STATUS: CNTMAX0 Position */ +#define BPWM_STATUS_CNTMAX0_Msk (0x1ul << BPWM_STATUS_CNTMAX0_Pos) /*!< BPWM_T::STATUS: CNTMAX0 Mask */ + +#define BPWM_STATUS_EADCTRG0_Pos (16) /*!< BPWM_T::STATUS: EADCTRG0 Position */ +#define BPWM_STATUS_EADCTRG0_Msk (0x1ul << BPWM_STATUS_EADCTRG0_Pos) /*!< BPWM_T::STATUS: EADCTRG0 Mask */ + +#define BPWM_STATUS_EADCTRG1_Pos (17) /*!< BPWM_T::STATUS: EADCTRG1 Position */ +#define BPWM_STATUS_EADCTRG1_Msk (0x1ul << BPWM_STATUS_EADCTRG1_Pos) /*!< BPWM_T::STATUS: EADCTRG1 Mask */ + +#define BPWM_STATUS_EADCTRG2_Pos (18) /*!< BPWM_T::STATUS: EADCTRG2 Position */ +#define BPWM_STATUS_EADCTRG2_Msk (0x1ul << BPWM_STATUS_EADCTRG2_Pos) /*!< BPWM_T::STATUS: EADCTRG2 Mask */ + +#define BPWM_STATUS_EADCTRG3_Pos (19) /*!< BPWM_T::STATUS: EADCTRG3 Position */ +#define BPWM_STATUS_EADCTRG3_Msk (0x1ul << BPWM_STATUS_EADCTRG3_Pos) /*!< BPWM_T::STATUS: EADCTRG3 Mask */ + +#define BPWM_STATUS_EADCTRG4_Pos (20) /*!< BPWM_T::STATUS: EADCTRG4 Position */ +#define BPWM_STATUS_EADCTRG4_Msk (0x1ul << BPWM_STATUS_EADCTRG4_Pos) /*!< BPWM_T::STATUS: EADCTRG4 Mask */ + +#define BPWM_STATUS_EADCTRG5_Pos (21) /*!< BPWM_T::STATUS: EADCTRG5 Position */ +#define BPWM_STATUS_EADCTRG5_Msk (0x1ul << BPWM_STATUS_EADCTRG5_Pos) /*!< BPWM_T::STATUS: EADCTRG5 Mask */ + +#define BPWM_STATUS_EADCTRGn_Pos (16) /*!< BPWM_T::STATUS: EADCTRGn Position */ +#define BPWM_STATUS_EADCTRGn_Msk (0x3ful << BPWM_STATUS_EADCTRGn_Pos) /*!< BPWM_T::STATUS: EADCTRGn Mask */ + +#define BPWM_CAPINEN_CAPINEN0_Pos (0) /*!< BPWM_T::CAPINEN: CAPINEN0 Position */ +#define BPWM_CAPINEN_CAPINEN0_Msk (0x1ul << BPWM_CAPINEN_CAPINEN0_Pos) /*!< BPWM_T::CAPINEN: CAPINEN0 Mask */ + +#define BPWM_CAPINEN_CAPINEN1_Pos (1) /*!< BPWM_T::CAPINEN: CAPINEN1 Position */ +#define BPWM_CAPINEN_CAPINEN1_Msk (0x1ul << BPWM_CAPINEN_CAPINEN1_Pos) /*!< BPWM_T::CAPINEN: CAPINEN1 Mask */ + +#define BPWM_CAPINEN_CAPINEN2_Pos (2) /*!< BPWM_T::CAPINEN: CAPINEN2 Position */ +#define BPWM_CAPINEN_CAPINEN2_Msk (0x1ul << BPWM_CAPINEN_CAPINEN2_Pos) /*!< BPWM_T::CAPINEN: CAPINEN2 Mask */ + +#define BPWM_CAPINEN_CAPINEN3_Pos (3) /*!< BPWM_T::CAPINEN: CAPINEN3 Position */ +#define BPWM_CAPINEN_CAPINEN3_Msk (0x1ul << BPWM_CAPINEN_CAPINEN3_Pos) /*!< BPWM_T::CAPINEN: CAPINEN3 Mask */ + +#define BPWM_CAPINEN_CAPINEN4_Pos (4) /*!< BPWM_T::CAPINEN: CAPINEN4 Position */ +#define BPWM_CAPINEN_CAPINEN4_Msk (0x1ul << BPWM_CAPINEN_CAPINEN4_Pos) /*!< BPWM_T::CAPINEN: CAPINEN4 Mask */ + +#define BPWM_CAPINEN_CAPINEN5_Pos (5) /*!< BPWM_T::CAPINEN: CAPINEN5 Position */ +#define BPWM_CAPINEN_CAPINEN5_Msk (0x1ul << BPWM_CAPINEN_CAPINEN5_Pos) /*!< BPWM_T::CAPINEN: CAPINEN5 Mask */ + +#define BPWM_CAPINEN_CAPINENn_Pos (0) /*!< BPWM_T::CAPINEN: CAPINENn Position */ +#define BPWM_CAPINEN_CAPINENn_Msk (0x3ful << BPWM_CAPINEN_CAPINENn_Pos) /*!< BPWM_T::CAPINEN: CAPINENn Mask */ + +#define BPWM_CAPCTL_CAPEN0_Pos (0) /*!< BPWM_T::CAPCTL: CAPEN0 Position */ +#define BPWM_CAPCTL_CAPEN0_Msk (0x1ul << BPWM_CAPCTL_CAPEN0_Pos) /*!< BPWM_T::CAPCTL: CAPEN0 Mask */ + +#define BPWM_CAPCTL_CAPEN1_Pos (1) /*!< BPWM_T::CAPCTL: CAPEN1 Position */ +#define BPWM_CAPCTL_CAPEN1_Msk (0x1ul << BPWM_CAPCTL_CAPEN1_Pos) /*!< BPWM_T::CAPCTL: CAPEN1 Mask */ + +#define BPWM_CAPCTL_CAPEN2_Pos (2) /*!< BPWM_T::CAPCTL: CAPEN2 Position */ +#define BPWM_CAPCTL_CAPEN2_Msk (0x1ul << BPWM_CAPCTL_CAPEN2_Pos) /*!< BPWM_T::CAPCTL: CAPEN2 Mask */ + +#define BPWM_CAPCTL_CAPEN3_Pos (3) /*!< BPWM_T::CAPCTL: CAPEN3 Position */ +#define BPWM_CAPCTL_CAPEN3_Msk (0x1ul << BPWM_CAPCTL_CAPEN3_Pos) /*!< BPWM_T::CAPCTL: CAPEN3 Mask */ + +#define BPWM_CAPCTL_CAPEN4_Pos (4) /*!< BPWM_T::CAPCTL: CAPEN4 Position */ +#define BPWM_CAPCTL_CAPEN4_Msk (0x1ul << BPWM_CAPCTL_CAPEN4_Pos) /*!< BPWM_T::CAPCTL: CAPEN4 Mask */ + +#define BPWM_CAPCTL_CAPEN5_Pos (5) /*!< BPWM_T::CAPCTL: CAPEN5 Position */ +#define BPWM_CAPCTL_CAPEN5_Msk (0x1ul << BPWM_CAPCTL_CAPEN5_Pos) /*!< BPWM_T::CAPCTL: CAPEN5 Mask */ + +#define BPWM_CAPCTL_CAPENn_Pos (0) /*!< BPWM_T::CAPCTL: CAPENn Position */ +#define BPWM_CAPCTL_CAPENn_Msk (0x3ful << BPWM_CAPCTL_CAPENn_Pos) /*!< BPWM_T::CAPCTL: CAPENn Mask */ + +#define BPWM_CAPCTL_CAPINV0_Pos (8) /*!< BPWM_T::CAPCTL: CAPINV0 Position */ +#define BPWM_CAPCTL_CAPINV0_Msk (0x1ul << BPWM_CAPCTL_CAPINV0_Pos) /*!< BPWM_T::CAPCTL: CAPINV0 Mask */ + +#define BPWM_CAPCTL_CAPINV1_Pos (9) /*!< BPWM_T::CAPCTL: CAPINV1 Position */ +#define BPWM_CAPCTL_CAPINV1_Msk (0x1ul << BPWM_CAPCTL_CAPINV1_Pos) /*!< BPWM_T::CAPCTL: CAPINV1 Mask */ + +#define BPWM_CAPCTL_CAPINV2_Pos (10) /*!< BPWM_T::CAPCTL: CAPINV2 Position */ +#define BPWM_CAPCTL_CAPINV2_Msk (0x1ul << BPWM_CAPCTL_CAPINV2_Pos) /*!< BPWM_T::CAPCTL: CAPINV2 Mask */ + +#define BPWM_CAPCTL_CAPINV3_Pos (11) /*!< BPWM_T::CAPCTL: CAPINV3 Position */ +#define BPWM_CAPCTL_CAPINV3_Msk (0x1ul << BPWM_CAPCTL_CAPINV3_Pos) /*!< BPWM_T::CAPCTL: CAPINV3 Mask */ + +#define BPWM_CAPCTL_CAPINV4_Pos (12) /*!< BPWM_T::CAPCTL: CAPINV4 Position */ +#define BPWM_CAPCTL_CAPINV4_Msk (0x1ul << BPWM_CAPCTL_CAPINV4_Pos) /*!< BPWM_T::CAPCTL: CAPINV4 Mask */ + +#define BPWM_CAPCTL_CAPINV5_Pos (13) /*!< BPWM_T::CAPCTL: CAPINV5 Position */ +#define BPWM_CAPCTL_CAPINV5_Msk (0x1ul << BPWM_CAPCTL_CAPINV5_Pos) /*!< BPWM_T::CAPCTL: CAPINV5 Mask */ + +#define BPWM_CAPCTL_CAPINVn_Pos (8) /*!< BPWM_T::CAPCTL: CAPINVn Position */ +#define BPWM_CAPCTL_CAPINVn_Msk (0x3ful << BPWM_CAPCTL_CAPINVn_Pos) /*!< BPWM_T::CAPCTL: CAPINVn Mask */ + +#define BPWM_CAPCTL_RCRLDEN0_Pos (16) /*!< BPWM_T::CAPCTL: RCRLDEN0 Position */ +#define BPWM_CAPCTL_RCRLDEN0_Msk (0x1ul << BPWM_CAPCTL_RCRLDEN0_Pos) /*!< BPWM_T::CAPCTL: RCRLDEN0 Mask */ + +#define BPWM_CAPCTL_RCRLDEN1_Pos (17) /*!< BPWM_T::CAPCTL: RCRLDEN1 Position */ +#define BPWM_CAPCTL_RCRLDEN1_Msk (0x1ul << BPWM_CAPCTL_RCRLDEN1_Pos) /*!< BPWM_T::CAPCTL: RCRLDEN1 Mask */ + +#define BPWM_CAPCTL_RCRLDEN2_Pos (18) /*!< BPWM_T::CAPCTL: RCRLDEN2 Position */ +#define BPWM_CAPCTL_RCRLDEN2_Msk (0x1ul << BPWM_CAPCTL_RCRLDEN2_Pos) /*!< BPWM_T::CAPCTL: RCRLDEN2 Mask */ + +#define BPWM_CAPCTL_RCRLDEN3_Pos (19) /*!< BPWM_T::CAPCTL: RCRLDEN3 Position */ +#define BPWM_CAPCTL_RCRLDEN3_Msk (0x1ul << BPWM_CAPCTL_RCRLDEN3_Pos) /*!< BPWM_T::CAPCTL: RCRLDEN3 Mask */ + +#define BPWM_CAPCTL_RCRLDEN4_Pos (20) /*!< BPWM_T::CAPCTL: RCRLDEN4 Position */ +#define BPWM_CAPCTL_RCRLDEN4_Msk (0x1ul << BPWM_CAPCTL_RCRLDEN4_Pos) /*!< BPWM_T::CAPCTL: RCRLDEN4 Mask */ + +#define BPWM_CAPCTL_RCRLDEN5_Pos (21) /*!< BPWM_T::CAPCTL: RCRLDEN5 Position */ +#define BPWM_CAPCTL_RCRLDEN5_Msk (0x1ul << BPWM_CAPCTL_RCRLDEN5_Pos) /*!< BPWM_T::CAPCTL: RCRLDEN5 Mask */ + +#define BPWM_CAPCTL_RCRLDENn_Pos (16) /*!< BPWM_T::CAPCTL: RCRLDENn Position */ +#define BPWM_CAPCTL_RCRLDENn_Msk (0x3ful << BPWM_CAPCTL_RCRLDENn_Pos) /*!< BPWM_T::CAPCTL: RCRLDENn Mask */ + +#define BPWM_CAPCTL_FCRLDEN0_Pos (24) /*!< BPWM_T::CAPCTL: FCRLDEN0 Position */ +#define BPWM_CAPCTL_FCRLDEN0_Msk (0x1ul << BPWM_CAPCTL_FCRLDEN0_Pos) /*!< BPWM_T::CAPCTL: FCRLDEN0 Mask */ + +#define BPWM_CAPCTL_FCRLDEN1_Pos (25) /*!< BPWM_T::CAPCTL: FCRLDEN1 Position */ +#define BPWM_CAPCTL_FCRLDEN1_Msk (0x1ul << BPWM_CAPCTL_FCRLDEN1_Pos) /*!< BPWM_T::CAPCTL: FCRLDEN1 Mask */ + +#define BPWM_CAPCTL_FCRLDEN2_Pos (26) /*!< BPWM_T::CAPCTL: FCRLDEN2 Position */ +#define BPWM_CAPCTL_FCRLDEN2_Msk (0x1ul << BPWM_CAPCTL_FCRLDEN2_Pos) /*!< BPWM_T::CAPCTL: FCRLDEN2 Mask */ + +#define BPWM_CAPCTL_FCRLDEN3_Pos (27) /*!< BPWM_T::CAPCTL: FCRLDEN3 Position */ +#define BPWM_CAPCTL_FCRLDEN3_Msk (0x1ul << BPWM_CAPCTL_FCRLDEN3_Pos) /*!< BPWM_T::CAPCTL: FCRLDEN3 Mask */ + +#define BPWM_CAPCTL_FCRLDEN4_Pos (28) /*!< BPWM_T::CAPCTL: FCRLDEN4 Position */ +#define BPWM_CAPCTL_FCRLDEN4_Msk (0x1ul << BPWM_CAPCTL_FCRLDEN4_Pos) /*!< BPWM_T::CAPCTL: FCRLDEN4 Mask */ + +#define BPWM_CAPCTL_FCRLDEN5_Pos (29) /*!< BPWM_T::CAPCTL: FCRLDEN5 Position */ +#define BPWM_CAPCTL_FCRLDEN5_Msk (0x1ul << BPWM_CAPCTL_FCRLDEN5_Pos) /*!< BPWM_T::CAPCTL: FCRLDEN5 Mask */ + +#define BPWM_CAPCTL_FCRLDENn_Pos (24) /*!< BPWM_T::CAPCTL: FCRLDENn Position */ +#define BPWM_CAPCTL_FCRLDENn_Msk (0x3ful << BPWM_CAPCTL_FCRLDENn_Pos) /*!< BPWM_T::CAPCTL: FCRLDENn Mask */ + +#define BPWM_CAPSTS_CRIFOV0_Pos (0) /*!< BPWM_T::CAPSTS: CRIFOV0 Position */ +#define BPWM_CAPSTS_CRIFOV0_Msk (0x1ul << BPWM_CAPSTS_CRIFOV0_Pos) /*!< BPWM_T::CAPSTS: CRIFOV0 Mask */ + +#define BPWM_CAPSTS_CRIFOV1_Pos (1) /*!< BPWM_T::CAPSTS: CRIFOV1 Position */ +#define BPWM_CAPSTS_CRIFOV1_Msk (0x1ul << BPWM_CAPSTS_CRIFOV1_Pos) /*!< BPWM_T::CAPSTS: CRIFOV1 Mask */ + +#define BPWM_CAPSTS_CRIFOV2_Pos (2) /*!< BPWM_T::CAPSTS: CRIFOV2 Position */ +#define BPWM_CAPSTS_CRIFOV2_Msk (0x1ul << BPWM_CAPSTS_CRIFOV2_Pos) /*!< BPWM_T::CAPSTS: CRIFOV2 Mask */ + +#define BPWM_CAPSTS_CRIFOV3_Pos (3) /*!< BPWM_T::CAPSTS: CRIFOV3 Position */ +#define BPWM_CAPSTS_CRIFOV3_Msk (0x1ul << BPWM_CAPSTS_CRIFOV3_Pos) /*!< BPWM_T::CAPSTS: CRIFOV3 Mask */ + +#define BPWM_CAPSTS_CRIFOV4_Pos (4) /*!< BPWM_T::CAPSTS: CRIFOV4 Position */ +#define BPWM_CAPSTS_CRIFOV4_Msk (0x1ul << BPWM_CAPSTS_CRIFOV4_Pos) /*!< BPWM_T::CAPSTS: CRIFOV4 Mask */ + +#define BPWM_CAPSTS_CRIFOV5_Pos (5) /*!< BPWM_T::CAPSTS: CRIFOV5 Position */ +#define BPWM_CAPSTS_CRIFOV5_Msk (0x1ul << BPWM_CAPSTS_CRIFOV5_Pos) /*!< BPWM_T::CAPSTS: CRIFOV5 Mask */ + +#define BPWM_CAPSTS_CRIFOVn_Pos (0) /*!< BPWM_T::CAPSTS: CRIFOVn Position */ +#define BPWM_CAPSTS_CRIFOVn_Msk (0x3ful << BPWM_CAPSTS_CRIFOVn_Pos) /*!< BPWM_T::CAPSTS: CRIFOVn Mask */ + +#define BPWM_CAPSTS_CFIFOV0_Pos (8) /*!< BPWM_T::CAPSTS: CFIFOV0 Position */ +#define BPWM_CAPSTS_CFIFOV0_Msk (0x1ul << BPWM_CAPSTS_CFIFOV0_Pos) /*!< BPWM_T::CAPSTS: CFIFOV0 Mask */ + +#define BPWM_CAPSTS_CFIFOV1_Pos (9) /*!< BPWM_T::CAPSTS: CFIFOV1 Position */ +#define BPWM_CAPSTS_CFIFOV1_Msk (0x1ul << BPWM_CAPSTS_CFIFOV1_Pos) /*!< BPWM_T::CAPSTS: CFIFOV1 Mask */ + +#define BPWM_CAPSTS_CFIFOV2_Pos (10) /*!< BPWM_T::CAPSTS: CFIFOV2 Position */ +#define BPWM_CAPSTS_CFIFOV2_Msk (0x1ul << BPWM_CAPSTS_CFIFOV2_Pos) /*!< BPWM_T::CAPSTS: CFIFOV2 Mask */ + +#define BPWM_CAPSTS_CFIFOV3_Pos (11) /*!< BPWM_T::CAPSTS: CFIFOV3 Position */ +#define BPWM_CAPSTS_CFIFOV3_Msk (0x1ul << BPWM_CAPSTS_CFIFOV3_Pos) /*!< BPWM_T::CAPSTS: CFIFOV3 Mask */ + +#define BPWM_CAPSTS_CFIFOV4_Pos (12) /*!< BPWM_T::CAPSTS: CFIFOV4 Position */ +#define BPWM_CAPSTS_CFIFOV4_Msk (0x1ul << BPWM_CAPSTS_CFIFOV4_Pos) /*!< BPWM_T::CAPSTS: CFIFOV4 Mask */ + +#define BPWM_CAPSTS_CFIFOV5_Pos (13) /*!< BPWM_T::CAPSTS: CFIFOV5 Position */ +#define BPWM_CAPSTS_CFIFOV5_Msk (0x1ul << BPWM_CAPSTS_CFIFOV5_Pos) /*!< BPWM_T::CAPSTS: CFIFOV5 Mask */ + +#define BPWM_CAPSTS_CFIFOVn_Pos (8) /*!< BPWM_T::CAPSTS: CFIFOVn Position */ +#define BPWM_CAPSTS_CFIFOVn_Msk (0x3ful << BPWM_CAPSTS_CFIFOVn_Pos) /*!< BPWM_T::CAPSTS: CFIFOVn Mask */ + +#define BPWM_RCAPDAT0_RCAPDAT_Pos (0) /*!< BPWM_T::RCAPDAT0: RCAPDAT Position */ +#define BPWM_RCAPDAT0_RCAPDAT_Msk (0xfffful << BPWM_RCAPDAT0_RCAPDAT_Pos) /*!< BPWM_T::RCAPDAT0: RCAPDAT Mask */ + +#define BPWM_FCAPDAT0_FCAPDAT_Pos (0) /*!< BPWM_T::FCAPDAT0: FCAPDAT Position */ +#define BPWM_FCAPDAT0_FCAPDAT_Msk (0xfffful << BPWM_FCAPDAT0_FCAPDAT_Pos) /*!< BPWM_T::FCAPDAT0: FCAPDAT Mask */ + +#define BPWM_RCAPDAT1_RCAPDAT_Pos (0) /*!< BPWM_T::RCAPDAT1: RCAPDAT Position */ +#define BPWM_RCAPDAT1_RCAPDAT_Msk (0xfffful << BPWM_RCAPDAT1_RCAPDAT_Pos) /*!< BPWM_T::RCAPDAT1: RCAPDAT Mask */ + +#define BPWM_FCAPDAT1_FCAPDAT_Pos (0) /*!< BPWM_T::FCAPDAT1: FCAPDAT Position */ +#define BPWM_FCAPDAT1_FCAPDAT_Msk (0xfffful << BPWM_FCAPDAT1_FCAPDAT_Pos) /*!< BPWM_T::FCAPDAT1: FCAPDAT Mask */ + +#define BPWM_RCAPDAT2_RCAPDAT_Pos (0) /*!< BPWM_T::RCAPDAT2: RCAPDAT Position */ +#define BPWM_RCAPDAT2_RCAPDAT_Msk (0xfffful << BPWM_RCAPDAT2_RCAPDAT_Pos) /*!< BPWM_T::RCAPDAT2: RCAPDAT Mask */ + +#define BPWM_FCAPDAT2_FCAPDAT_Pos (0) /*!< BPWM_T::FCAPDAT2: FCAPDAT Position */ +#define BPWM_FCAPDAT2_FCAPDAT_Msk (0xfffful << BPWM_FCAPDAT2_FCAPDAT_Pos) /*!< BPWM_T::FCAPDAT2: FCAPDAT Mask */ + +#define BPWM_RCAPDAT3_RCAPDAT_Pos (0) /*!< BPWM_T::RCAPDAT3: RCAPDAT Position */ +#define BPWM_RCAPDAT3_RCAPDAT_Msk (0xfffful << BPWM_RCAPDAT3_RCAPDAT_Pos) /*!< BPWM_T::RCAPDAT3: RCAPDAT Mask */ + +#define BPWM_FCAPDAT3_FCAPDAT_Pos (0) /*!< BPWM_T::FCAPDAT3: FCAPDAT Position */ +#define BPWM_FCAPDAT3_FCAPDAT_Msk (0xfffful << BPWM_FCAPDAT3_FCAPDAT_Pos) /*!< BPWM_T::FCAPDAT3: FCAPDAT Mask */ + +#define BPWM_RCAPDAT4_RCAPDAT_Pos (0) /*!< BPWM_T::RCAPDAT4: RCAPDAT Position */ +#define BPWM_RCAPDAT4_RCAPDAT_Msk (0xfffful << BPWM_RCAPDAT4_RCAPDAT_Pos) /*!< BPWM_T::RCAPDAT4: RCAPDAT Mask */ + +#define BPWM_FCAPDAT4_FCAPDAT_Pos (0) /*!< BPWM_T::FCAPDAT4: FCAPDAT Position */ +#define BPWM_FCAPDAT4_FCAPDAT_Msk (0xfffful << BPWM_FCAPDAT4_FCAPDAT_Pos) /*!< BPWM_T::FCAPDAT4: FCAPDAT Mask */ + +#define BPWM_RCAPDAT5_RCAPDAT_Pos (0) /*!< BPWM_T::RCAPDAT5: RCAPDAT Position */ +#define BPWM_RCAPDAT5_RCAPDAT_Msk (0xfffful << BPWM_RCAPDAT5_RCAPDAT_Pos) /*!< BPWM_T::RCAPDAT5: RCAPDAT Mask */ + +#define BPWM_FCAPDAT5_FCAPDAT_Pos (0) /*!< BPWM_T::FCAPDAT5: FCAPDAT Position */ +#define BPWM_FCAPDAT5_FCAPDAT_Msk (0xfffful << BPWM_FCAPDAT5_FCAPDAT_Pos) /*!< BPWM_T::FCAPDAT5: FCAPDAT Mask */ + +#define BPWM_CAPIEN_CAPRIENn_Pos (0) /*!< BPWM_T::CAPIEN: CAPRIENn Position */ +#define BPWM_CAPIEN_CAPRIENn_Msk (0x3ful << BPWM_CAPIEN_CAPRIENn_Pos) /*!< BPWM_T::CAPIEN: CAPRIENn Mask */ + +#define BPWM_CAPIEN_CAPFIENn_Pos (8) /*!< BPWM_T::CAPIEN: CAPFIENn Position */ +#define BPWM_CAPIEN_CAPFIENn_Msk (0x3ful << BPWM_CAPIEN_CAPFIENn_Pos) /*!< BPWM_T::CAPIEN: CAPFIENn Mask */ + +#define BPWM_CAPIF_CAPRIF0_Pos (0) /*!< BPWM_T::CAPIF: CAPRIF0 Position */ +#define BPWM_CAPIF_CAPRIF0_Msk (0x1ul << BPWM_CAPIF_CAPRIF0_Pos) /*!< BPWM_T::CAPIF: CAPRIF0 Mask */ + +#define BPWM_CAPIF_CAPRIF1_Pos (1) /*!< BPWM_T::CAPIF: CAPRIF1 Position */ +#define BPWM_CAPIF_CAPRIF1_Msk (0x1ul << BPWM_CAPIF_CAPRIF1_Pos) /*!< BPWM_T::CAPIF: CAPRIF1 Mask */ + +#define BPWM_CAPIF_CAPRIF2_Pos (2) /*!< BPWM_T::CAPIF: CAPRIF2 Position */ +#define BPWM_CAPIF_CAPRIF2_Msk (0x1ul << BPWM_CAPIF_CAPRIF2_Pos) /*!< BPWM_T::CAPIF: CAPRIF2 Mask */ + +#define BPWM_CAPIF_CAPRIF3_Pos (3) /*!< BPWM_T::CAPIF: CAPRIF3 Position */ +#define BPWM_CAPIF_CAPRIF3_Msk (0x1ul << BPWM_CAPIF_CAPRIF3_Pos) /*!< BPWM_T::CAPIF: CAPRIF3 Mask */ + +#define BPWM_CAPIF_CAPRIF4_Pos (4) /*!< BPWM_T::CAPIF: CAPRIF4 Position */ +#define BPWM_CAPIF_CAPRIF4_Msk (0x1ul << BPWM_CAPIF_CAPRIF4_Pos) /*!< BPWM_T::CAPIF: CAPRIF4 Mask */ + +#define BPWM_CAPIF_CAPRIF5_Pos (5) /*!< BPWM_T::CAPIF: CAPRIF5 Position */ +#define BPWM_CAPIF_CAPRIF5_Msk (0x1ul << BPWM_CAPIF_CAPRIF5_Pos) /*!< BPWM_T::CAPIF: CAPRIF5 Mask */ + +#define BPWM_CAPIF_CAPRIFn_Pos (0) /*!< BPWM_T::CAPIF: CAPRIFn Position */ +#define BPWM_CAPIF_CAPRIFn_Msk (0x3ful << BPWM_CAPIF_CAPRIFn_Pos) /*!< BPWM_T::CAPIF: CAPRIFn Mask */ + +#define BPWM_CAPIF_CAPFIF0_Pos (8) /*!< BPWM_T::CAPIF: CAPFIF0 Position */ +#define BPWM_CAPIF_CAPFIF0_Msk (0x1ul << BPWM_CAPIF_CAPFIF0_Pos) /*!< BPWM_T::CAPIF: CAPFIF0 Mask */ + +#define BPWM_CAPIF_CAPFIF1_Pos (9) /*!< BPWM_T::CAPIF: CAPFIF1 Position */ +#define BPWM_CAPIF_CAPFIF1_Msk (0x1ul << BPWM_CAPIF_CAPFIF1_Pos) /*!< BPWM_T::CAPIF: CAPFIF1 Mask */ + +#define BPWM_CAPIF_CAPFIF2_Pos (10) /*!< BPWM_T::CAPIF: CAPFIF2 Position */ +#define BPWM_CAPIF_CAPFIF2_Msk (0x1ul << BPWM_CAPIF_CAPFIF2_Pos) /*!< BPWM_T::CAPIF: CAPFIF2 Mask */ + +#define BPWM_CAPIF_CAPFIF3_Pos (11) /*!< BPWM_T::CAPIF: CAPFIF3 Position */ +#define BPWM_CAPIF_CAPFIF3_Msk (0x1ul << BPWM_CAPIF_CAPFIF3_Pos) /*!< BPWM_T::CAPIF: CAPFIF3 Mask */ + +#define BPWM_CAPIF_CAPFIF4_Pos (12) /*!< BPWM_T::CAPIF: CAPFIF4 Position */ +#define BPWM_CAPIF_CAPFIF4_Msk (0x1ul << BPWM_CAPIF_CAPFIF4_Pos) /*!< BPWM_T::CAPIF: CAPFIF4 Mask */ + +#define BPWM_CAPIF_CAPFIF5_Pos (13) /*!< BPWM_T::CAPIF: CAPFIF5 Position */ +#define BPWM_CAPIF_CAPFIF5_Msk (0x1ul << BPWM_CAPIF_CAPFIF5_Pos) /*!< BPWM_T::CAPIF: CAPFIF5 Mask */ + +#define BPWM_CAPIF_CAPFIFn_Pos (8) /*!< BPWM_T::CAPIF: CAPFIFn Position */ +#define BPWM_CAPIF_CAPFIFn_Msk (0x3ful << BPWM_CAPIF_CAPFIFn_Pos) /*!< BPWM_T::CAPIF: CAPFIFn Mask */ + +#define BPWM_PBUF_PBUF_Pos (0) /*!< BPWM_T::PBUF: PBUF Position */ +#define BPWM_PBUF_PBUF_Msk (0xfffful << BPWM_PBUF_PBUF_Pos) /*!< BPWM_T::PBUF: PBUF Mask */ + +#define BPWM_CMPBUF0_CMPBUF_Pos (0) /*!< BPWM_T::CMPBUF0: CMPBUF Position */ +#define BPWM_CMPBUF0_CMPBUF_Msk (0xfffful << BPWM_CMPBUF0_CMPBUF_Pos) /*!< BPWM_T::CMPBUF0: CMPBUF Mask */ + +#define BPWM_CMPBUF1_CMPBUF_Pos (0) /*!< BPWM_T::CMPBUF1: CMPBUF Position */ +#define BPWM_CMPBUF1_CMPBUF_Msk (0xfffful << BPWM_CMPBUF1_CMPBUF_Pos) /*!< BPWM_T::CMPBUF1: CMPBUF Mask */ + +#define BPWM_CMPBUF2_CMPBUF_Pos (0) /*!< BPWM_T::CMPBUF2: CMPBUF Position */ +#define BPWM_CMPBUF2_CMPBUF_Msk (0xfffful << BPWM_CMPBUF2_CMPBUF_Pos) /*!< BPWM_T::CMPBUF2: CMPBUF Mask */ + +#define BPWM_CMPBUF3_CMPBUF_Pos (0) /*!< BPWM_T::CMPBUF3: CMPBUF Position */ +#define BPWM_CMPBUF3_CMPBUF_Msk (0xfffful << BPWM_CMPBUF3_CMPBUF_Pos) /*!< BPWM_T::CMPBUF3: CMPBUF Mask */ + +#define BPWM_CMPBUF4_CMPBUF_Pos (0) /*!< BPWM_T::CMPBUF4: CMPBUF Position */ +#define BPWM_CMPBUF4_CMPBUF_Msk (0xfffful << BPWM_CMPBUF4_CMPBUF_Pos) /*!< BPWM_T::CMPBUF4: CMPBUF Mask */ + +#define BPWM_CMPBUF5_CMPBUF_Pos (0) /*!< BPWM_T::CMPBUF5: CMPBUF Position */ +#define BPWM_CMPBUF5_CMPBUF_Msk (0xfffful << BPWM_CMPBUF5_CMPBUF_Pos) /*!< BPWM_T::CMPBUF5: CMPBUF Mask */ + +/**@}*/ /* BPWM_CONST */ +/**@}*/ /* end of BPWM register group */ +/**@}*/ /* end of REGISTER group */ + + +#endif /* __BPWM_REG_H__ */ diff --git a/Ubiquitous/XiZi/board/nuvoton-m2354/third_party_driver/include/Regs/can_reg.h b/Ubiquitous/XiZi/board/nuvoton-m2354/third_party_driver/include/Regs/can_reg.h new file mode 100644 index 0000000..76f5d28 --- /dev/null +++ b/Ubiquitous/XiZi/board/nuvoton-m2354/third_party_driver/include/Regs/can_reg.h @@ -0,0 +1,790 @@ +/**************************************************************************//** + * @file can_reg.h + * @version V1.00 + * @brief CAN register definition header file + * + * @copyright SPDX-License-Identifier: Apache-2.0 + * @copyright Copyright (C) 2020 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ +#ifndef __CAN_REG_H__ +#define __CAN_REG_H__ + +/** @addtogroup REGISTER Control Register + + @{ + +*/ + + +/*---------------------- Controller Area Network Controller -------------------------*/ +/** + @addtogroup CAN Controller Area Network Controller(CAN) + Memory Mapped Structure for CAN Controller + @{ +*/ + + +typedef struct +{ + + + + /** + * @var CAN_IF_T::CREQ + * Offset: 0x20, 0x80 IFn (Register Map Note 2) Command Request Registers + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[5:0] |MessageNumber|Message Number + * | | |0x01-0x20: Valid Message Number, the Message Object in the Message + * | | |RAM is selected for data transfer. + * | | |0x00: Not a valid Message Number, interpreted as 0x20. + * | | |0x21-0x3F: Not a valid Message Number, interpreted as 0x01-0x1F. + * |[15] |Busy |Busy Flag + * | | |0 = Read/write action has finished. + * | | |1 = Writing to the IFn Command Request Register is in progress. + * | | |This bit can only be read by the software. + * @var CAN_IF_T::CMASK + * Offset: 0x24, 0x84 IFn Command Mask Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |DAT_B |Access Data Bytes [7:4] + * | | |Write Operation: + * | | |0 = Data Bytes [7:4] unchanged. + * | | |1 = Transfer Data Bytes [7:4] to Message Object. + * | | |Read Operation: + * | | |0 = Data Bytes [7:4] unchanged. + * | | |1 = Transfer Data Bytes [7:4] to IFn Message Buffer Register. + * |[1] |DAT_A |Access Data Bytes [3:0] + * | | |Write Operation: + * | | |0 = Data Bytes [3:0] unchanged. + * | | |1 = Transfer Data Bytes [3:0] to Message Object. + * | | |Read Operation: + * | | |0 = Data Bytes [3:0] unchanged. + * | | |1 = Transfer Data Bytes [3:0] to IFn Message Buffer Register. + * |[2] |TxRqst_NewDat|Access Transmission Request Bit When Write Operation + * | | |0 = TxRqst bit unchanged. + * | | |1 = Set TxRqst bit. + * | | |Note: If a transmission is requested by programming bit TxRqst/NewDat in the IFn Command Mask Register, bit TxRqst in the IFn Message Control Register will be ignored. + * | | |Access New Data Bit when Read Operation. + * | | |0 = NewDat bit remains unchanged. + * | | |1 = Clear NewDat bit in the Message Object. + * | | |Note: A read access to a Message Object can be combined with the reset of the control bits IntPnd and NewDat. + * | | |The values of these bits transferred to the IFn Message Control Register always reflect the status before resetting these bits. + * |[3] |ClrIntPnd |Clear Interrupt Pending Bit + * | | |Write Operation: + * | | |When writing to a Message Object, this bit is ignored. + * | | |Read Operation: + * | | |0 = IntPnd bit (CAN_IFn_MCON[13]) remains unchanged. + * | | |1 = Clear IntPnd bit in the Message Object. + * |[4] |Control |Control Access Control Bits + * | | |Write Operation: + * | | |0 = Control Bits unchanged. + * | | |1 = Transfer Control Bits to Message Object. + * | | |Read Operation: + * | | |0 = Control Bits unchanged. + * | | |1 = Transfer Control Bits to IFn Message Buffer Register. + * |[5] |Arb |Access Arbitration Bits + * | | |Write Operation: + * | | |0 = Arbitration bits unchanged. + * | | |1 = Transfer Identifier + Dir (CAN_IFn_ARB2[13]) + Xtd (CAN_IFn_ARB2[14]) + MsgVal (CAN_IFn_APB2[15]) to Message Object. + * | | |Read Operation: + * | | |0 = Arbitration bits unchanged. + * | | |1 = Transfer Identifier + Dir + Xtd + MsgVal to IFn Message Buffer Register. + * |[6] |Mask |Access Mask Bits + * | | |Write Operation: + * | | |0 = Mask bits unchanged. + * | | |1 = Transfer Identifier Mask + MDir + MXtd to Message Object. + * | | |Read Operation: + * | | |0 = Mask bits unchanged. + * | | |1 = Transfer Identifier Mask + MDir + MXtd to IFn Message Buffer Register. + * |[7] |WR_RD |Write / Read Mode + * | | |0 = Read: Transfer data from the Message Object addressed by the Command Request Register into the selected Message Buffer Registers. + * | | |1 = Write: Transfer data from the selected Message Buffer Registers to the Message Object addressed by the Command Request Register. + * @var CAN_IF_T::MASK1 + * Offset: 0x28, 0x88 IFn Mask 1 Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |Msk[15:0] |Identifier Mask 15-0 + * | | |0 = The corresponding bit in the identifier of the message object cannot inhibit the match in the acceptance filtering. + * | | |1 = The corresponding identifier bit is used for acceptance filtering. + * @var CAN_IF_T::MASK2 + * Offset: 0x2C, 0x8C IFn Mask 2 Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[12:0] |Msk[28:16]|Identifier Mask 28-16 + * | | |0 = The corresponding bit in the identifier of the message object cannot inhibit the match in the acceptance filtering. + * | | |1 = The corresponding identifier bit is used for acceptance filtering. + * |[14] |MDir |Mask Message Direction + * | | |0 = The message direction bit (Dir (CAN_IFn_ARB2[13])) has no effect on the acceptance filtering. + * | | |1 = The message direction bit (Dir) is used for acceptance filtering. + * |[15] |MXtd |Mask Extended Identifier + * | | |0 = The extended identifier bit (IDE) has no effect on the acceptance filtering. + * | | |1 = The extended identifier bit (IDE) is used for acceptance filtering. + * | | |Note: When 11-bit ("standard") Identifiers are used for a Message Object, the identifiers of received Data Frames are written into bits ID28 to ID18 (CAN_IFn_ARB2[12:2]). + * | | |For acceptance filtering, only these bits together with mask bits Msk28 to Msk18 (CAN_IFn_MASK2[12:2]) are considered. + * @var CAN_IF_T::ARB1 + * Offset: 0x30, 0x90 IFn Arbitration 1 Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |ID[15:0] |Message Identifier 15-0 + * | | |ID28 - ID0, 29-bit Identifier ("Extended Frame"). + * | | |ID28 - ID18, 11-bit Identifier ("Standard Frame") + * @var CAN_IF_T::ARB2 + * Offset: 0x34, 0x94 IFn Arbitration 2 Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[12:0] |ID[28:16] |Message Identifier 28-16 + * | | |ID28 - ID0, 29-bit Identifier ("Extended Frame"). + * | | |ID28 - ID18, 11-bit Identifier ("Standard Frame") + * |[13] |Dir |Message Direction + * | | |0 = Direction is receive. + * | | |On TxRqst, a Remote Frame with the identifier of this Message Object is transmitted. + * | | |On reception of a Data Frame with matching identifier, that message is stored in this Message Object. + * | | |1 = Direction is transmit. + * | | |On TxRqst, the respective Message Object is transmitted as a Data Frame. + * | | |On reception of a Remote Frame with matching identifier, the TxRqst bit (CAN_IFn_CMASK[2]) of this Message Object is set (if RmtEn (CAN_IFn_MCON[9]) = one). + * |[14] |Xtd |Extended Identifier + * | | |0 = The 11-bit ("standard") Identifier will be used for this Message Object. + * | | |1 = The 29-bit ("extended") Identifier will be used for this Message Object. + * |[15] |MsgVal |Message Valid + * | | |0 = The Message Object is ignored by the Message Handler. + * | | |1 = The Message Object is configured and should be considered by the Message Handler. + * | | |Note: The application software must reset the MsgVal bit of all unused Messages Objects during the initialization before it resets bit Init (CAN_CON[0]). + * | | |This bit must also be reset before the identifier Id28-0 (CAN_IFn_ARB1/2), the control bits Xtd (CAN_IFn_ARB2[14]), Dir (CAN_IFn_APB2[13]), or the Data Length Code DLC3-0 (CAN_IFn_MCON[3:0]) are modified, or if the Messages Object is no longer required. + * @var CAN_IF_T::MCON + * Offset: 0x38, 0x98 IFn Message Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[3:0] |DLC |Data Length Code + * | | |0-8: Data Frame has 0-8 data bytes. + * | | |9-15: Data Frame has 8 data bytes + * | | |Note: The Data Length Code of a Message Object must be defined the same as in all the corresponding objects with the same identifier at other nodes. + * | | |When the Message Handler stores a data frame, it will write the DLC to the value given by the received message. + * | | |Data 0: 1st data byte of a CAN Data Frame + * | | |Data 1: 2nd data byte of a CAN Data Frame + * | | |Data 2: 3rd data byte of a CAN Data Frame + * | | |Data 3: 4th data byte of a CAN Data Frame + * | | |Data 4: 5th data byte of a CAN Data Frame + * | | |Data 5: 6th data byte of a CAN Data Frame + * | | |Data 6: 7th data byte of a CAN Data Frame + * | | |Data 7 : 8th data byte of a CAN Data Frame + * | | |Note: The Data 0 Byte is the first data byte shifted into the shift register of the CAN Core during a reception while the Data 7 byte is the last. + * | | |When the Message Handler stores a Data Frame, it will write all the eight data bytes into a Message Object. + * | | |If the Data Length Code is less than 8, the remaining bytes of the Message Object will be overwritten by unspecified values. + * |[7] |EoB |End Of Buffer + * | | |0 = Message Object belongs to a FIFO Buffer and is not the last Message Object of that FIFO Buffer. + * | | |1 = Single Message Object or last Message Object of a FIFO Buffer. + * | | |Note: This bit is used to concatenate two or more Message Objects (up to 32) to build a FIFO Buffer. + * | | |For single Message Objects (not belonging to a FIFO Buffer), this bit must always be set to one. + * |[8] |TxRqst |Transmit Request + * | | |0 = This Message Object is not waiting for transmission. + * | | |1 = The transmission of this Message Object is requested and is not yet done. + * |[9] |RmtEn |Remote Enable Control + * | | |0 = At the reception of a Remote Frame, TxRqst (CAN_IFn_MCON[8]) is left unchanged. + * | | |1 = At the reception of a Remote Frame, TxRqst is set. + * |[10] |RxIE |Receive Interrupt Enable Control + * | | |0 = IntPnd (CAN_IFn_MCON[13]) will be left unchanged after a successful reception of a frame. + * | | |1 = IntPnd will be set after a successful reception of a frame. + * |[11] |TxIE |Transmit Interrupt Enable Control + * | | |0 = IntPnd (CAN_IFn_MCON[13]) will be left unchanged after the successful transmission of a frame. + * | | |1 = IntPnd will be set after a successful transmission of a frame. + * |[12] |UMask |Use Acceptance Mask + * | | |0 = Mask ignored. + * | | |1 = Use Mask (Msk28-0, MXtd, and MDir) for acceptance filtering. + * | | |Note: If the UMask bit is set to one, the Message Object's mask bits have to be programmed during initialization of the Message Object before MsgVal bit (CAN_IFn_APB2[15]) is set to one. + * |[13] |IntPnd |Interrupt Pending + * | | |0 = This message object is not the source of an interrupt. + * | | |1 = This message object is the source of an interrupt. + * | | |The Interrupt Identifier in the Interrupt Register will point to this message object if there is no other interrupt source with higher priority. + * |[14] |MsgLst |Message Lost (only valid for Message Objects with direction = receive). + * | | |0 = No message lost since last time this bit was reset by the CPU. + * | | |1 = The Message Handler stored a new message into this object when NewDat was still set, the CPU has lost a message. + * |[15] |NewDat |New Data + * | | |0 = No new data has been written into the data portion of this Message Object by the Message Handler since last time this flag was cleared by the application software. + * | | |1 = The Message Handler or the application software has written new data into the data portion of this Message Object. + * @var CAN_IF_T::DAT_A1 + * Offset: 0x3C, 0x9C IFn Data A1 Register (Register Map Note 3) + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[7:0] |Data0 |Data Byte 0 + * | | |1st data byte of a CAN Data Frame + * |[15:8] |Data1 |Data Byte 1 + * | | |2nd data byte of a CAN Data Frame + * @var CAN_IF_T::DAT_A2 + * Offset: 0x40, 0xA0 IFn Data A2 Register (Register Map Note 3) + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[7:0] |Data2 |Data Byte 2 + * | | |3rd data byte of CAN Data Frame + * |[15:8] |Data3 |Data Byte 3 + * | | |4th data byte of CAN Data Frame + * @var CAN_IF_T::DAT_B1 + * Offset: 0x44, 0xA4 IFn Data B1 Register (Register Map Note 3) + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[7:0] |Data4 |Data Byte 4 + * | | |5th data byte of CAN Data Frame + * |[15:8] |Data5 |Data Byte 5 + * | | |6th data byte of CAN Data Frame + * @var CAN_IF_T::DAT_B2 + * Offset: 0x48, 0xA8 IFn Data B2 Register (Register Map Note 3) + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[7:0] |Data6 |Data Byte 6 + * | | |7th data byte of CAN Data Frame. + * |[15:8] |Data7 |Data Byte 7 + * | | |8th data byte of CAN Data Frame. + */ + + __IO uint32_t CREQ; /* Offset: 0x20, 0x80 IFn (Register Map Note 2) Command Request Registers */ + __IO uint32_t CMASK; /* Offset: 0x24, 0x84 IFn Command Mask Register */ + __IO uint32_t MASK1; /* Offset: 0x28, 0x88 IFn Mask 1 Register */ + __IO uint32_t MASK2; /* Offset: 0x2C, 0x8C IFn Mask 2 Register */ + __IO uint32_t ARB1; /* Offset: 0x30, 0x90 IFn Arbitration 1 Register */ + __IO uint32_t ARB2; /* Offset: 0x34, 0x94 IFn Arbitration 2 Register */ + __IO uint32_t MCON; /* Offset: 0x38, 0x98 IFn Message Control Register */ + __IO uint32_t DAT_A1; /* Offset: 0x3C, 0x9C IFn Data A1 Register (Register Map Note 3) */ + __IO uint32_t DAT_A2; /* Offset: 0x40, 0xA0 IFn Data A2 Register (Register Map Note 3) */ + __IO uint32_t DAT_B1; /* Offset: 0x44, 0xA4 IFn Data B1 Register (Register Map Note 3) */ + __IO uint32_t DAT_B2; /* Offset: 0x48, 0xA8 IFn Data B2 Register (Register Map Note 3) */ + __I uint32_t RESERVE0[13]; + +} CAN_IF_T; + + + + +typedef struct +{ + + + + /** + * @var CAN_T::CON + * Offset: 0x00 Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |Init |Init Initialization + * | | |0 = Normal Operation. + * | | |1 = Initialization is started. + * |[1] |IE |Module Interrupt Enable Control + * | | |0 = Disabled. + * | | |1 = Enabled. + * |[2] |SIE |Status Change Interrupt Enable Control + * | | |0 = Disabled - No Status Change Interrupt will be generated. + * | | |1 = Enabled - An interrupt will be generated when a message transfer is successfully completed or a CAN bus error is detected. + * |[3] |EIE |Error Interrupt Enable Control + * | | |0 = Disabled - No Error Status Interrupt will be generated. + * | | |1 = Enabled - A change in the bits BOff (CAN_STATUS[7]) or EWarn (CAN_STATUS[6]) in the Status Register will generate an interrupt. + * |[5] |DAR |Automatic Re-Transmission Disable Control + * | | |0 = Automatic Retransmission of disturbed messages enabled. + * | | |1 = Automatic Retransmission disabled. + * |[6] |CCE |Configuration Change Enable Control + * | | |0 = No write access to the Bit Timing Register. + * | | |1 = Write access to the Bit Timing Register (CAN_BTIME) allowed. (while Init bit (CAN_CON[0]) = 1). + * |[7] |Test |Test Mode Enable Control + * | | |0 = Normal Operation. + * | | |1 = Test Mode. + * @var CAN_T::STATUS + * Offset: 0x04 Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[2:0] |LEC |Last Error Code (Type Of The Last Error To Occur On The CAN Bus) + * | | |The LEC field holds a code, which indicates the type of the last error to occur on the CAN bus. + * | | |This field will be cleared to '0' when a message has been transferred (reception or transmission) without error. + * | | |The unused code '7' may be written by the CPU to check for updates. + * | | |The following table describes the error code. + * |[3] |TxOK |Transmitted A Message Successfully + * | | |0 = Since this bit was reset by the CPU, no message has been successfully transmitted. + * | | |This bit is never reset by the CAN Core. + * | | |1 = Since this bit was last reset by the CPU, a message has been successfully (error free and acknowledged by at least one other node) transmitted. + * |[4] |RxOK |Received A Message Successfully + * | | |0 = No message has been successfully received since this bit was last reset by the CPU. + * | | |This bit is never reset by the CAN Core. + * | | |1 = A message has been successfully received since this bit was last reset by the CPU (independent of the result of acceptance filtering). + * |[5] |EPass |Error Passive (Read Only) + * | | |0 = The CAN Core is error active. + * | | |1 = The CAN Core is in the error passive state as defined in the CAN Specification. + * |[6] |EWarn |Error Warning Status (Read Only) + * | | |0 = Both error counters are below the error warning limit of 96. + * | | |1 = At least one of the error counters in the EML has reached the error warning limit of 96. + * |[7] |BOff |Bus-Off Status (Read Only) + * | | |0 = The CAN module is not in bus-off state. + * | | |1 = The CAN module is in bus-off state. + * @var CAN_T::ERR + * Offset: 0x08 Error Counter Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[7:0] |TEC |Transmit Error Counter + * | | |Actual state of the Transmit Error Counter. Values between 0 and 255. + * |[14:8] |REC |Receive Error Counter + * | | |Actual state of the Receive Error Counter. Values between 0 and 127. + * |[15] |RP |Receive Error Passive + * | | |0 = The Receive Error Counter is below the error passive level. + * | | |1 = The Receive Error Counter has reached the error passive level as defined in the CAN Specification. + * @var CAN_T::BTIME + * Offset: 0x0C Bit Timing Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[5:0] |BRP |Baud Rate Prescaler + * | | |0x01-0x3F: The value by which the oscillator frequency is divided for generating the bit time quanta. + * | | |The bit time is built up from a multiple of this quanta. + * | | |Valid values for the Baud Rate Prescaler are [ 0 ... 63 ]. + * | | |The actual interpretation by the hardware of this value is such that one more than the value programmed here is used. + * |[7:6] |SJW |(Re)Synchronization Jump Width + * | | |0x0-0x3: Valid programmed values are [0 ... 3]. + * | | |The actual interpretation by the hardware of this value is such that one more than the value programmed here is used. + * |[11:8] |TSeg1 |Time Segment Before The Sample Point Minus Sync_Seg + * | | |0x01-0x0F: valid values for TSeg1 are [1 ... 15]. + * | | |The actual interpretation by the hardware of this value is such that one more than the value programmed is used. + * |[14:12] |TSeg2 |Time Segment After Sample Point + * | | |0x0-0x7: Valid values for TSeg2 are [0 ... 7]. + * | | |The actual interpretation by the hardware of this value is such that one more than the value programmed here is used. + * @var CAN_T::IIDR + * Offset: 0x10 Interrupt Identifier Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |IntId |Interrupt Identifier (Indicates The Source Of The Interrupt) + * | | |If several interrupts are pending, the CAN Interrupt Register will point to the pending interrupt with the highest priority, disregarding their chronological order. + * | | |An interrupt remains pending until the application software has cleared it. + * | | |If IntId is different from 0x0000 and IE (CAN_IFn_MCON[1]) is set, the IRQ interrupt signal to the EIC is active. + * | | |The interrupt remains active until IntId is back to value 0x0000 (the cause of the interrupt is reset) or until IE is reset. + * | | |The Status Interrupt has the highest priority. + * | | |Among the message interrupts, the Message Object' s interrupt priority decreases with increasing message number. + * | | |A message interrupt is cleared by clearing the Message Object's IntPnd bit (CAN_IFn_MCON[13]). + * | | |The Status Interrupt is cleared by reading the Status Register. + * @var CAN_T::TEST + * Offset: 0x14 Test Register (Register Map Note 1) + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[1:0] |Res |Reserved + * | | |There are reserved bits. + * | | |These bits are always read as '0' and must always be written with '0'. + * |[2] |Basic |Basic Mode + * | | |0 = Basic Mode disabled. + * | | |1= IF1 Registers used as Tx Buffer, IF2 Registers used as Rx Buffer. + * |[3] |Silent |Silent Mode + * | | |0 = Normal operation. + * | | |1 = The module is in Silent Mode. + * |[4] |LBack |Loop Back Mode Enable Control + * | | |0 = Loop Back Mode is disabled. + * | | |1 = Loop Back Mode is enabled. + * |[6:5] |Tx10 |Tx[1:0]: Control Of CAN_TX Pin + * | | |00 = Reset value, CAN_TX pin is controlled by the CAN Core. + * | | |01 = Sample Point can be monitored at CAN_TX pin. + * | | |10 = CAN_TX pin drives a dominant ('0') value. + * | | |11 = CAN_TX pin drives a recessive ('1') value. + * |[7] |Rx |Monitors The Actual Value Of CAN_RX Pin (Read Only) + * | | |0 = The CAN bus is dominant (CAN_RX = '0'). + * | | |1 = The CAN bus is recessive (CAN_RX = '1'). + * @var CAN_T::BRPE + * Offset: 0x18 Baud Rate Prescaler Extension Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[3:0] |BRPE |BRPE: Baud Rate Prescaler Extension + * | | |0x00-0x0F: By programming BRPE, the Baud Rate Prescaler can be extended to values up to 1023. + * | | |The actual interpretation by the hardware is that one more than the value programmed by BRPE (MSBs) and BTIME (LSBs) is used. + * @var CAN_T::IF + * Offset: 0x20~0xFC CAN Interface Registers + * --------------------------------------------------------------------------------------------------- + * CAN interface structure. Refer to \ref CAN_IF_T for detail information. + * + * @var CAN_T::TXREQ1 + * Offset: 0x100 Transmission Request Register 1 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |TxRqst[16:1]|Transmission Request Bits 16-1 (Of All Message Objects) + * | | |0 = This Message Object is not waiting for transmission. + * | | |1 = The transmission of this Message Object is requested and is not yet done. + * | | |These bits are read only. + * @var CAN_T::TXREQ2 + * Offset: 0x104 Transmission Request Register 2 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |TxRqst[32:17]|Transmission Request Bits 32-17 (Of All Message Objects) + * | | |0 = This Message Object is not waiting for transmission. + * | | |1 = The transmission of this Message Object is requested and is not yet done. + * | | |These bits are read only. + * @var CAN_T::NDAT1 + * Offset: 0x120 New Data Register 1 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |NewData[16:1]|New Data Bits 16-1 (Of All Message Objects) + * | | |0 = No new data has been written into the data portion of this Message Object by the Message Handler since the last time this flag was cleared by the application software. + * | | |1 = The Message Handler or the application software has written new data into the data portion of this Message Object. + * @var CAN_T::NDAT2 + * Offset: 0x124 New Data Register 2 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |NewData[32:17]|New Data Bits 32-17 (Of All Message Objects) + * | | |0 = No new data has been written into the data portion of this Message Object by the Message Handler since the last time this flag was cleared by the application software. + * | | |1 = The Message Handler or the application software has written new data into the data portion of this Message Object. + * @var CAN_T::IPND1 + * Offset: 0x140 Interrupt Pending Register 1 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |IntPnd[16:1]|Interrupt Pending Bits 16-1 (Of All Message Objects) + * | | |0 = This message object is not the source of an interrupt. + * | | |1 = This message object is the source of an interrupt. + * @var CAN_T::IPND2 + * Offset: 0x144 Interrupt Pending Register 2 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |IntPnd[32:17]|Interrupt Pending Bits 32-17(Of All Message Objects) + * | | |0 = This message object is not the source of an interrupt. + * | | |1 = This message object is the source of an interrupt. + * @var CAN_T::MVLD1 + * Offset: 0x160 Message Valid Register 1 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |MsgVal[16:1]|Message Valid Bits 16-1 (Of All Message Objects) (Read Only) + * | | |0 = This Message Object is ignored by the Message Handler. + * | | |1 = This Message Object is configured and should be considered by the Message Handler. + * | | |Ex. + * | | |CAN_MVLD1[0] means Message object No.1 is valid or not. + * | | |If CAN_MVLD1[0] is set, message object No.1 is configured. + * @var CAN_T::MVLD2 + * Offset: 0x164 Message Valid Register 2 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |MsgVal[32:17]|Message Valid Bits 32-17 (Of All Message Objects) (Read Only) + * | | |0 = This Message Object is ignored by the Message Handler. + * | | |1 = This Message Object is configured and should be considered by the Message Handler. + * | | |Ex.CAN_MVLD2[15] means Message object No.32 is valid or not. + * | | |If CAN_MVLD2[15] is set, message object No.32 is configured. + * @var CAN_T::WU_EN + * Offset: 0x168 Wake-up Enable Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |WAKUP_EN |Wake-Up Enable Control + * | | |0 = The wake-up function Disabled. + * | | |1 = The wake-up function Enabled. + * | | |Note: User can wake-up system when there is a falling edge in the CAN_Rx pin. + * @var CAN_T::WU_STATUS + * Offset: 0x16C Wake-up Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |WAKUP_STS |Wake-Up Status + * | | |0 = No wake-up event occurred. + * | | |1 = Wake-up event occurred. + * | | |Note: This bit can be cleared by writing '0'. + */ + + __IO uint32_t CON; /* Offset: 0x00 Control Register */ + __IO uint32_t STATUS; /* Offset: 0x04 Status Register */ + __I uint32_t ERR; /* Offset: 0x08 Error Counter Register */ + __IO uint32_t BTIME; /* Offset: 0x0C Bit Timing Register */ + __I uint32_t IIDR; /* Offset: 0x10 Interrupt Identifier Register */ + __IO uint32_t TEST; /* Offset: 0x14 Test Register (Register Map Note 1) */ + __IO uint32_t BRPE; /* Offset: 0x18 Baud Rate Prescaler Extension Register */ + __I uint32_t RESERVE0[1]; + __IO CAN_IF_T IF[2]; /* Offset: 0x20~0xFC CAN Interface Registers */ + __I uint32_t RESERVE1[8]; + __I uint32_t TXREQ1; /* Offset: 0x100 Transmission Request Register 1 */ + __I uint32_t TXREQ2; /* Offset: 0x104 Transmission Request Register 2 */ + __I uint32_t RESERVE3[6]; + __I uint32_t NDAT1; /* Offset: 0x120 New Data Register 1 */ + __I uint32_t NDAT2; /* Offset: 0x124 New Data Register 2 */ + __I uint32_t RESERVE4[6]; + __I uint32_t IPND1; /* Offset: 0x140 Interrupt Pending Register 1 */ + __I uint32_t IPND2; /* Offset: 0x144 Interrupt Pending Register 2 */ + __I uint32_t RESERVE5[6]; + __I uint32_t MVLD1; /* Offset: 0x160 Message Valid Register 1 */ + __I uint32_t MVLD2; /* Offset: 0x164 Message Valid Register 2 */ + __IO uint32_t WU_EN; /* Offset: 0x168 Wake-up Enable Register */ + __IO uint32_t WU_STATUS; /* Offset: 0x16C Wake-up Status Register */ + +} CAN_T; + + + +/** + @addtogroup CAN_CONST CAN Bit Field Definition + Constant Definitions for CAN Controller + @{ +*/ +/* CAN CON Bit Field Definitions */ +#define CAN_CON_TEST_Pos 7 /*!< CAN_T::CON: TEST Position */ +#define CAN_CON_TEST_Msk (0x1ul << CAN_CON_TEST_Pos) /*!< CAN_T::CON: TEST Mask */ + +#define CAN_CON_CCE_Pos 6 /*!< CAN_T::CON: CCE Position */ +#define CAN_CON_CCE_Msk (0x1ul << CAN_CON_CCE_Pos) /*!< CAN_T::CON: CCE Mask */ + +#define CAN_CON_DAR_Pos 5 /*!< CAN_T::CON: DAR Position */ +#define CAN_CON_DAR_Msk (0x1ul << CAN_CON_DAR_Pos) /*!< CAN_T::CON: DAR Mask */ + +#define CAN_CON_EIE_Pos 3 /*!< CAN_T::CON: EIE Position */ +#define CAN_CON_EIE_Msk (0x1ul << CAN_CON_EIE_Pos) /*!< CAN_T::CON: EIE Mask */ + +#define CAN_CON_SIE_Pos 2 /*!< CAN_T::CON: SIE Position */ +#define CAN_CON_SIE_Msk (0x1ul << CAN_CON_SIE_Pos) /*!< CAN_T::CON: SIE Mask */ + +#define CAN_CON_IE_Pos 1 /*!< CAN_T::CON: IE Position */ +#define CAN_CON_IE_Msk (0x1ul << CAN_CON_IE_Pos) /*!< CAN_T::CON: IE Mask */ + +#define CAN_CON_INIT_Pos 0 /*!< CAN_T::CON: INIT Position */ +#define CAN_CON_INIT_Msk (0x1ul << CAN_CON_INIT_Pos) /*!< CAN_T::CON: INIT Mask */ + +/* CAN STATUS Bit Field Definitions */ +#define CAN_STATUS_BOFF_Pos 7 /*!< CAN_T::STATUS: BOFF Position */ +#define CAN_STATUS_BOFF_Msk (0x1ul << CAN_STATUS_BOFF_Pos) /*!< CAN_T::STATUS: BOFF Mask */ + +#define CAN_STATUS_EWARN_Pos 6 /*!< CAN_T::STATUS: EWARN Position */ +#define CAN_STATUS_EWARN_Msk (0x1ul << CAN_STATUS_EWARN_Pos) /*!< CAN_T::STATUS: EWARN Mask */ + +#define CAN_STATUS_EPASS_Pos 5 /*!< CAN_T::STATUS: EPASS Position */ +#define CAN_STATUS_EPASS_Msk (0x1ul << CAN_STATUS_EPASS_Pos) /*!< CAN_T::STATUS: EPASS Mask */ + +#define CAN_STATUS_RXOK_Pos 4 /*!< CAN_T::STATUS: RXOK Position */ +#define CAN_STATUS_RXOK_Msk (0x1ul << CAN_STATUS_RXOK_Pos) /*!< CAN_T::STATUS: RXOK Mask */ + +#define CAN_STATUS_TXOK_Pos 3 /*!< CAN_T::STATUS: TXOK Position */ +#define CAN_STATUS_TXOK_Msk (0x1ul << CAN_STATUS_TXOK_Pos) /*!< CAN_T::STATUS: TXOK Mask */ + +#define CAN_STATUS_LEC_Pos 0 /*!< CAN_T::STATUS: LEC Position */ +#define CAN_STATUS_LEC_Msk (0x7ul << CAN_STATUS_LEC_Pos) /*!< CAN_T::STATUS: LEC Mask */ + +/* CAN ERR Bit Field Definitions */ +#define CAN_ERR_RP_Pos 15 /*!< CAN_T::ERR: RP Position */ +#define CAN_ERR_RP_Msk (0x1ul << CAN_ERR_RP_Pos) /*!< CAN_T::ERR: RP Mask */ + +#define CAN_ERR_REC_Pos 8 /*!< CAN_T::ERR: REC Position */ +#define CAN_ERR_REC_Msk (0x7Ful << CAN_ERR_REC_Pos) /*!< CAN_T::ERR: REC Mask */ + +#define CAN_ERR_TEC_Pos 0 /*!< CAN_T::ERR: TEC Position */ +#define CAN_ERR_TEC_Msk (0xFFul << CAN_ERR_TEC_Pos) /*!< CAN_T::ERR: TEC Mask */ + +/* CAN BTIME Bit Field Definitions */ +#define CAN_BTIME_TSEG2_Pos 12 /*!< CAN_T::BTIME: TSEG2 Position */ +#define CAN_BTIME_TSEG2_Msk (0x7ul << CAN_BTIME_TSEG2_Pos) /*!< CAN_T::BTIME: TSEG2 Mask */ + +#define CAN_BTIME_TSEG1_Pos 8 /*!< CAN_T::BTIME: TSEG1 Position */ +#define CAN_BTIME_TSEG1_Msk (0xFul << CAN_BTIME_TSEG1_Pos) /*!< CAN_T::BTIME: TSEG1 Mask */ + +#define CAN_BTIME_SJW_Pos 6 /*!< CAN_T::BTIME: SJW Position */ +#define CAN_BTIME_SJW_Msk (0x3ul << CAN_BTIME_SJW_Pos) /*!< CAN_T::BTIME: SJW Mask */ + +#define CAN_BTIME_BRP_Pos 0 /*!< CAN_T::BTIME: BRP Position */ +#define CAN_BTIME_BRP_Msk (0x3Ful << CAN_BTIME_BRP_Pos) /*!< CAN_T::BTIME: BRP Mask */ + +/* CAN IIDR Bit Field Definitions */ +#define CAN_IIDR_INTID_Pos 0 /*!< CAN_T::IIDR: INTID Position */ +#define CAN_IIDR_INTID_Msk (0xFFFFul << CAN_IIDR_INTID_Pos) /*!< CAN_T::IIDR: INTID Mask */ + +/* CAN TEST Bit Field Definitions */ +#define CAN_TEST_RX_Pos 7 /*!< CAN_T::TEST: RX Position */ +#define CAN_TEST_RX_Msk (0x1ul << CAN_TEST_RX_Pos) /*!< CAN_T::TEST: RX Mask */ + +#define CAN_TEST_TX_Pos 5 /*!< CAN_T::TEST: TX Position */ +#define CAN_TEST_TX_Msk (0x3ul << CAN_TEST_TX_Pos) /*!< CAN_T::TEST: TX Mask */ + +#define CAN_TEST_LBACK_Pos 4 /*!< CAN_T::TEST: LBACK Position */ +#define CAN_TEST_LBACK_Msk (0x1ul << CAN_TEST_LBACK_Pos) /*!< CAN_T::TEST: LBACK Mask */ + +#define CAN_TEST_SILENT_Pos 3 /*!< CAN_T::TEST: Silent Position */ +#define CAN_TEST_SILENT_Msk (0x1ul << CAN_TEST_SILENT_Pos) /*!< CAN_T::TEST: Silent Mask */ + +#define CAN_TEST_BASIC_Pos 2 /*!< CAN_T::TEST: Basic Position */ +#define CAN_TEST_BASIC_Msk (0x1ul << CAN_TEST_BASIC_Pos) /*!< CAN_T::TEST: Basic Mask */ + +/* CAN BPRE Bit Field Definitions */ +#define CAN_BRPE_BRPE_Pos 0 /*!< CAN_T::BRPE: BRPE Position */ +#define CAN_BRPE_BRPE_Msk (0xFul << CAN_BRPE_BRPE_Pos) /*!< CAN_T::BRPE: BRPE Mask */ + +/* CAN IFn_CREQ Bit Field Definitions */ +#define CAN_IF_CREQ_BUSY_Pos 15 /*!< CAN_IF_T::CREQ: BUSY Position */ +#define CAN_IF_CREQ_BUSY_Msk (0x1ul << CAN_IF_CREQ_BUSY_Pos) /*!< CAN_IF_T::CREQ: BUSY Mask */ + +#define CAN_IF_CREQ_MSGNUM_Pos 0 /*!< CAN_IF_T::CREQ: MSGNUM Position */ +#define CAN_IF_CREQ_MSGNUM_Msk (0x3Ful << CAN_IF_CREQ_MSGNUM_Pos) /*!< CAN_IF_T::CREQ: MSGNUM Mask */ + +/* CAN IFn_CMASK Bit Field Definitions */ +#define CAN_IF_CMASK_WRRD_Pos 7 /*!< CAN_IF_T::CMASK: WRRD Position */ +#define CAN_IF_CMASK_WRRD_Msk (0x1ul << CAN_IF_CMASK_WRRD_Pos) /*!< CAN_IF_T::CMASK: WRRD Mask */ + +#define CAN_IF_CMASK_MASK_Pos 6 /*!< CAN_IF_T::CMASK: MASK Position */ +#define CAN_IF_CMASK_MASK_Msk (0x1ul << CAN_IF_CMASK_MASK_Pos) /*!< CAN_IF_T::CMASK: MASK Mask */ + +#define CAN_IF_CMASK_ARB_Pos 5 /*!< CAN_IF_T::CMASK: ARB Position */ +#define CAN_IF_CMASK_ARB_Msk (0x1ul << CAN_IF_CMASK_ARB_Pos) /*!< CAN_IF_T::CMASK: ARB Mask */ + +#define CAN_IF_CMASK_CONTROL_Pos 4 /*!< CAN_IF_T::CMASK: CONTROL Position */ +#define CAN_IF_CMASK_CONTROL_Msk (0x1ul << CAN_IF_CMASK_CONTROL_Pos) /*!< CAN_IF_T::CMASK: CONTROL Mask */ + +#define CAN_IF_CMASK_CLRINTPND_Pos 3 /*!< CAN_IF_T::CMASK: CLRINTPND Position */ +#define CAN_IF_CMASK_CLRINTPND_Msk (0x1ul << CAN_IF_CMASK_CLRINTPND_Pos) /*!< CAN_IF_T::CMASK: CLRINTPND Mask */ + +#define CAN_IF_CMASK_TXRQSTNEWDAT_Pos 2 /*!< CAN_IF_T::CMASK: TXRQSTNEWDAT Position */ +#define CAN_IF_CMASK_TXRQSTNEWDAT_Msk (0x1ul << CAN_IF_CMASK_TXRQSTNEWDAT_Pos) /*!< CAN_IF_T::CMASK: TXRQSTNEWDAT Mask */ + +#define CAN_IF_CMASK_DATAA_Pos 1 /*!< CAN_IF_T::CMASK: DATAA Position */ +#define CAN_IF_CMASK_DATAA_Msk (0x1ul << CAN_IF_CMASK_DATAA_Pos) /*!< CAN_IF_T::CMASK: DATAA Mask */ + +#define CAN_IF_CMASK_DATAB_Pos 0 /*!< CAN_IF_T::CMASK: DATAB Position */ +#define CAN_IF_CMASK_DATAB_Msk (0x1ul << CAN_IF_CMASK_DATAB_Pos) /*!< CAN_IF_T::CMASK: DATAB Mask */ + +/* CAN IFn_MASK1 Bit Field Definitions */ +#define CAN_IF_MASK1_MSK_Pos 0 /*!< CAN_IF_T::MASK1: MSK Position */ +#define CAN_IF_MASK1_MSK_Msk (0xFFul << CAN_IF_MASK1_MSK_Pos) /*!< CAN_IF_T::MASK1: MSK Mask */ + +/* CAN IFn_MASK2 Bit Field Definitions */ +#define CAN_IF_MASK2_MXTD_Pos 15 /*!< CAN_IF_T::MASK2: MXTD Position */ +#define CAN_IF_MASK2_MXTD_Msk (0x1ul << CAN_IF_MASK2_MXTD_Pos) /*!< CAN_IF_T::MASK2: MXTD Mask */ + +#define CAN_IF_MASK2_MDIR_Pos 14 /*!< CAN_IF_T::MASK2: MDIR Position */ +#define CAN_IF_MASK2_MDIR_Msk (0x1ul << CAN_IF_MASK2_MDIR_Pos) /*!< CAN_IF_T::MASK2: MDIR Mask */ + +#define CAN_IF_MASK2_MSK_Pos 0 /*!< CAN_IF_T::MASK2: MSK Position */ +#define CAN_IF_MASK2_MSK_Msk (0x1FFul << CAN_IF_MASK2_MSK_Pos) /*!< CAN_IF_T::MASK2: MSK Mask */ + +/* CAN IFn_ARB1 Bit Field Definitions */ +#define CAN_IF_ARB1_ID_Pos 0 /*!< CAN_IF_T::ARB1: ID Position */ +#define CAN_IF_ARB1_ID_Msk (0xFFFFul << CAN_IF_ARB1_ID_Pos) /*!< CAN_IF_T::ARB1: ID Mask */ + +/* CAN IFn_ARB2 Bit Field Definitions */ +#define CAN_IF_ARB2_MSGVAL_Pos 15 /*!< CAN_IF_T::ARB2: MSGVAL Position */ +#define CAN_IF_ARB2_MSGVAL_Msk (0x1ul << CAN_IF_ARB2_MSGVAL_Pos) /*!< CAN_IF_T::ARB2: MSGVAL Mask */ + +#define CAN_IF_ARB2_XTD_Pos 14 /*!< CAN_IF_T::ARB2: XTD Position */ +#define CAN_IF_ARB2_XTD_Msk (0x1ul << CAN_IF_ARB2_XTD_Pos) /*!< CAN_IF_T::ARB2: XTD Mask */ + +#define CAN_IF_ARB2_DIR_Pos 13 /*!< CAN_IF_T::ARB2: DIR Position */ +#define CAN_IF_ARB2_DIR_Msk (0x1ul << CAN_IF_ARB2_DIR_Pos) /*!< CAN_IF_T::ARB2: DIR Mask */ + +#define CAN_IF_ARB2_ID_Pos 0 /*!< CAN_IF_T::ARB2: ID Position */ +#define CAN_IF_ARB2_ID_Msk (0x1FFFul << CAN_IF_ARB2_ID_Pos) /*!< CAN_IF_T::ARB2: ID Mask */ + +/* CAN IFn_MCON Bit Field Definitions */ +#define CAN_IF_MCON_NEWDAT_Pos 15 /*!< CAN_IF_T::MCON: NEWDAT Position */ +#define CAN_IF_MCON_NEWDAT_Msk (0x1ul << CAN_IF_MCON_NEWDAT_Pos) /*!< CAN_IF_T::MCON: NEWDAT Mask */ + +#define CAN_IF_MCON_MSGLST_Pos 14 /*!< CAN_IF_T::MCON: MSGLST Position */ +#define CAN_IF_MCON_MSGLST_Msk (0x1ul << CAN_IF_MCON_MSGLST_Pos) /*!< CAN_IF_T::MCON: MSGLST Mask */ + +#define CAN_IF_MCON_INTPND_Pos 13 /*!< CAN_IF_T::MCON: INTPND Position */ +#define CAN_IF_MCON_INTPND_Msk (0x1ul << CAN_IF_MCON_INTPND_Pos) /*!< CAN_IF_T::MCON: INTPND Mask */ + +#define CAN_IF_MCON_UMASK_Pos 12 /*!< CAN_IF_T::MCON: UMASK Position */ +#define CAN_IF_MCON_UMASK_Msk (0x1ul << CAN_IF_MCON_UMASK_Pos) /*!< CAN_IF_T::MCON: UMASK Mask */ + +#define CAN_IF_MCON_TXIE_Pos 11 /*!< CAN_IF_T::MCON: TXIE Position */ +#define CAN_IF_MCON_TXIE_Msk (0x1ul << CAN_IF_MCON_TXIE_Pos) /*!< CAN_IF_T::MCON: TXIE Mask */ + +#define CAN_IF_MCON_RXIE_Pos 10 /*!< CAN_IF_T::MCON: RXIE Position */ +#define CAN_IF_MCON_RXIE_Msk (0x1ul << CAN_IF_MCON_RXIE_Pos) /*!< CAN_IF_T::MCON: RXIE Mask */ + +#define CAN_IF_MCON_RMTEN_Pos 9 /*!< CAN_IF_T::MCON: RMTEN Position */ +#define CAN_IF_MCON_RMTEN_Msk (0x1ul << CAN_IF_MCON_RMTEN_Pos) /*!< CAN_IF_T::MCON: RMTEN Mask */ + +#define CAN_IF_MCON_TXRQST_Pos 8 /*!< CAN_IF_T::MCON: TXRQST Position */ +#define CAN_IF_MCON_TXRQST_Msk (0x1ul << CAN_IF_MCON_TXRQST_Pos) /*!< CAN_IF_T::MCON: TXRQST Mask */ + +#define CAN_IF_MCON_EOB_Pos 7 /*!< CAN_IF_T::MCON: EOB Position */ +#define CAN_IF_MCON_EOB_Msk (0x1ul << CAN_IF_MCON_EOB_Pos) /*!< CAN_IF_T::MCON: EOB Mask */ + +#define CAN_IF_MCON_DLC_Pos 0 /*!< CAN_IF_T::MCON: DLC Position */ +#define CAN_IF_MCON_DLC_Msk (0xFul << CAN_IF_MCON_DLC_Pos) /*!< CAN_IF_T::MCON: DLC Mask */ + +/* CAN IFn_DATA_A1 Bit Field Definitions */ +#define CAN_IF_DAT_A1_DATA1_Pos 8 /*!< CAN_IF_T::DATAA1: DATA1 Position */ +#define CAN_IF_DAT_A1_DATA1_Msk (0xFFul << CAN_IF_DAT_A1_DATA1_Pos) /*!< CAN_IF_T::DATAA1: DATA1 Mask */ + +#define CAN_IF_DAT_A1_DATA0_Pos 0 /*!< CAN_IF_T::DATAA1: DATA0 Position */ +#define CAN_IF_DAT_A1_DATA0_Msk (0xFFul << CAN_IF_DAT_A1_DATA0_Pos) /*!< CAN_IF_T::DATAA1: DATA0 Mask */ + +/* CAN IFn_DATA_A2 Bit Field Definitions */ +#define CAN_IF_DAT_A2_DATA3_Pos 8 /*!< CAN_IF_T::DATAA1: DATA3 Position */ +#define CAN_IF_DAT_A2_DATA3_Msk (0xFFul << CAN_IF_DAT_A2_DATA3_Pos) /*!< CAN_IF_T::DATAA1: DATA3 Mask */ + +#define CAN_IF_DAT_A2_DATA2_Pos 0 /*!< CAN_IF_T::DATAA1: DATA2 Position */ +#define CAN_IF_DAT_A2_DATA2_Msk (0xFFul << CAN_IF_DAT_A2_DATA2_Pos) /*!< CAN_IF_T::DATAA1: DATA2 Mask */ + +/* CAN IFn_DATA_B1 Bit Field Definitions */ +#define CAN_IF_DAT_B1_DATA5_Pos 8 /*!< CAN_IF_T::DATAB1: DATA5 Position */ +#define CAN_IF_DAT_B1_DATA5_Msk (0xFFul << CAN_IF_DAT_B1_DATA5_Pos) /*!< CAN_IF_T::DATAB1: DATA5 Mask */ + +#define CAN_IF_DAT_B1_DATA4_Pos 0 /*!< CAN_IF_T::DATAB1: DATA4 Position */ +#define CAN_IF_DAT_B1_DATA4_Msk (0xFFul << CAN_IF_DAT_B1_DATA4_Pos) /*!< CAN_IF_T::DATAB1: DATA4 Mask */ + +/* CAN IFn_DATA_B2 Bit Field Definitions */ +#define CAN_IF_DAT_B2_DATA7_Pos 8 /*!< CAN_IF_T::DATAB2: DATA7 Position */ +#define CAN_IF_DAT_B2_DATA7_Msk (0xFFul << CAN_IF_DAT_B2_DATA7_Pos) /*!< CAN_IF_T::DATAB2: DATA7 Mask */ + +#define CAN_IF_DAT_B2_DATA6_Pos 0 /*!< CAN_IF_T::DATAB2: DATA6 Position */ +#define CAN_IF_DAT_B2_DATA6_Msk (0xFFul << CAN_IF_DAT_B2_DATA6_Pos) /*!< CAN_IF_T::DATAB2: DATA6 Mask */ + +/* CAN IFn_TXRQST1 Bit Field Definitions */ +#define CAN_TXRQST1_TXRQST_Pos 0 /*!< CAN_T::TXRQST1: TXRQST Position */ +#define CAN_TXRQST1_TXRQST_Msk (0xFFFFul << CAN_TXRQST1_TXRQST_Pos) /*!< CAN_T::TXRQST1: TXRQST Mask */ + +/* CAN IFn_TXRQST2 Bit Field Definitions */ +#define CAN_TXRQST2_TXRQST_Pos 0 /*!< CAN_T::TXRQST2: TXRQST Position */ +#define CAN_TXRQST2_TXRQST_Msk (0xFFFFul << CAN_TXRQST2_TXRQST_Pos) /*!< CAN_T::TXRQST2: TXRQST Mask */ + +/* CAN IFn_NDAT1 Bit Field Definitions */ +#define CAN_NDAT1_NEWDATA_Pos 0 /*!< CAN_T::NDAT1: NEWDATA Position */ +#define CAN_NDAT1_NEWDATA_Msk (0xFFFFul << CAN_NDAT1_NEWDATA_Pos) /*!< CAN_T::NDAT1: NEWDATA Mask */ + +/* CAN IFn_NDAT2 Bit Field Definitions */ +#define CAN_NDAT2_NEWDATA_Pos 0 /*!< CAN_T::NDAT2: NEWDATA Position */ +#define CAN_NDAT2_NEWDATA_Msk (0xFFFFul << CAN_NDAT2_NEWDATA_Pos) /*!< CAN_T::NDAT2: NEWDATA Mask */ + +/* CAN IFn_IPND1 Bit Field Definitions */ +#define CAN_IPND1_INTPND_Pos 0 /*!< CAN_T::IPND1: INTPND Position */ +#define CAN_IPND1_INTPND_Msk (0xFFFFul << CAN_IPND1_INTPND_Pos) /*!< CAN_T::IPND1: INTPND Mask */ + +/* CAN IFn_IPND2 Bit Field Definitions */ +#define CAN_IPND2_INTPND_Pos 0 /*!< CAN_T::IPND2: INTPND Position */ +#define CAN_IPND2_INTPND_Msk (0xFFFFul << CAN_IPND2_INTPND_Pos) /*!< CAN_T::IPND2: INTPND Mask */ + +/* CAN IFn_MVLD1 Bit Field Definitions */ +#define CAN_MVLD1_MSGVAL_Pos 0 /*!< CAN_T::MVLD1: MSGVAL Position */ +#define CAN_MVLD1_MSGVAL_Msk (0xFFFFul << CAN_MVLD1_MSGVAL_Pos) /*!< CAN_T::MVLD1: MSGVAL Mask */ + +/* CAN IFn_MVLD2 Bit Field Definitions */ +#define CAN_MVLD2_MSGVAL_Pos 0 /*!< CAN_T::MVLD2: MSGVAL Position */ +#define CAN_MVLD2_MSGVAL_Msk (0xFFFFul << CAN_MVLD2_MSGVAL_Pos) /*!< CAN_T::MVLD2: MSGVAL Mask */ + +/* CAN WUEN Bit Field Definitions */ +#define CAN_WU_EN_WAKUP_EN_Pos 0 /*!< CAN_T::WU_EN: WAKUP_EN Position */ +#define CAN_WU_EN_WAKUP_EN_Msk (0x1ul << CAN_WU_EN_WAKUP_EN_Pos) /*!< CAN_T::WU_EN: WAKUP_EN Mask */ + +/* CAN WUSTATUS Bit Field Definitions */ +#define CAN_WU_STATUS_WAKUP_STS_Pos 0 /*!< CAN_T::WU_STATUS: WAKUP_STS Position */ +#define CAN_WU_STATUS_WAKUP_STS_Msk (0x1ul << CAN_WU_STATUS_WAKUP_STS_Pos) /*!< CAN_T::WU_STATUS: WAKUP_STS Mask */ + + +/**@}*/ /* CAN_CONST */ +/**@}*/ /* end of CAN register group */ +/**@}*/ /* end of REGISTER group */ + + +#endif /* __CAN_REG_H__ */ diff --git a/Ubiquitous/XiZi/board/nuvoton-m2354/third_party_driver/include/Regs/clk_reg.h b/Ubiquitous/XiZi/board/nuvoton-m2354/third_party_driver/include/Regs/clk_reg.h new file mode 100644 index 0000000..34a3eb8 --- /dev/null +++ b/Ubiquitous/XiZi/board/nuvoton-m2354/third_party_driver/include/Regs/clk_reg.h @@ -0,0 +1,1815 @@ +/**************************************************************************//** + * @file clk_reg.h + * @version V1.00 + * @brief CLK register definition header file + * + * @copyright SPDX-License-Identifier: Apache-2.0 + * @copyright Copyright (C) 2020 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ +#ifndef __CLK_REG_H__ +#define __CLK_REG_H__ + +/** @addtogroup REGISTER Control Register + + @{ + +*/ + + +/*---------------------- System Clock Controller -------------------------*/ +/** + @addtogroup CLK System Clock Controller(CLK) + Memory Mapped Structure for CLK Controller + @{ +*/ + +typedef struct +{ + + /** + * @var CLK_T::PWRCTL + * Offset: 0x00 System Power-down Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |HXTEN |HXT Enable Bit (Write Protect) + * | | |0 = 4~24 MHz external high speed crystal (HXT) Disabled. + * | | |1 = 4~24 MHz external high speed crystal (HXT) Enabled. + * | | |Note1: This bit is write protected. Refer to the SYS_REGLCTL register. + * | | |Note2: HXT cannot be disabled and HXTEN will always read as 1 if HCLK clock source is selected from HXT or PLL (clock source from HXT). + * |[1] |LXTEN |LXT Enable Bit (Write Protect) + * | | |0 = 32.768 kHz external low speed crystal (extLXT) Disabled. + * | | |1 = 32.768 kHz external low speed crystal (extLXT) Enabled. + * | | |Note1: This bit is write protected. Refer to the SYS_REGLCTL register. + * | | |Note2: LXT cannot be disabled and LXTEN will always read as 1 if HCLK clock source is selected from LXT when the LXT clock source is selected as extLXT by setting C32KS(RTC_LXTCTL[7]) to 1. + * |[2] |HIRCEN |HIRC Enable Bit (Write Protect) + * | | |The HCLK default clock source is from HIRC and this bit default value is 1. + * | | |0 = 12 MHz internal high speed RC oscillator (HIRC) Disabled. + * | | |1 = 12 MHz internal high speed RC oscillator (HIRC) Enabled. + * | | |Note1: This bit is write protected. Refer to the SYS_REGLCTL register. + * | | |Note2: HIRC cannot be disabled and HIRCEN will always read as 1 if HCLK clock source is selected from HIRC or PLL (clock source from HIRC). + * |[3] |LIRCEN |LIRC Enable Bit (Write Protect) + * | | |0 = 32 kHz internal low speed RC oscillator (LIRC) Disabled. + * | | |1 = 32 kHz internal low speed RC oscillator (LIRC) Enabled. + * | | |Note1: This bit is write protected. Refer to the SYS_REGLCTL register. + * | | |Note2: LIRC cannot be disabled and LIRCEN will always read as 1 if HCLK clock source is selected from LIRC. + * | | |Note3: If CWDTEN(CONFIG[31,4:3]) is set to 111, LIRC clock can be enabled or disabled by setting LIRCEN(CLK_PWRCTL[3]). + * | | |If CWDTEN(CONFIG0[31,4:3]) is not set to 111, LIRC cannot be disabled in normal mode and LIRCEN will always read as 1 + * | | |In Power-down mode, LIRC clock is controlled by LIRCEN(CLK_PWRCTL[3]) and CWDTPDEN (CONFIG0[30]) setting. + * |[5] |PDWKIEN |Power-down Mode Wake-up Interrupt Enable Bit (Write Protect) + * | | |0 = Power-down mode wake-up interrupt Disabled. + * | | |1 = Power-down mode wake-up interrupt Enabled. + * | | |Note1: The interrupt will occur when both PDWKIF and PDWKIEN are high, after resume from Power-down mode. + * | | |Note2: This bit is write protected. Refer to the SYS_REGLCTL register. + * |[6] |PDWKIF |Power-down Mode Wake-up Interrupt Status + * | | |Set by Power-down wake-up event, it indicates that resume from Power-down mode. + * | | |The flag is set if the EINT7~0, GPIO, UART0~5, USBH, USBD, OTG, CAN0, BOD, ACMP, WDT, EWDT, SDH0, TIMER, I2C0~2, USCI0~1, RTC, TAMPER and CLKD wake-up occurred. + * | | |Note1: Write 1 to clear the bit to 0. + * | | |Note2: This bit works only if PDWKIEN (CLK_PWRCTL[5]) set to 1. + * |[7] |PDEN |System Power-down Enable (Write Protect) + * | | |When this bit is set to 1, Power-down mode is enabled and the chip keeps active till the CPU sleep mode is also active and then the chip enters Power-down mode. + * | | |When chip wakes up from Power-down mode, this bit is auto cleared. Users need to set this bit again for next Power-down. + * | | |In Power-down mode, HXT, HIRC, HIRC48, PLL and system clock will be disabled and ignored the clock source selection. + * | | |The clocks of peripheral are not controlled by Power-down mode, if the peripheral clock source is from LXT, LIRC or MIRC. + * | | |0 = Chip operating normally or chip in idle mode because of WFI command. + * | | |1 = Chip waits CPU sleep command WFI and then enters Power-down mode. + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * |[11:10] |HXTGAIN |HXT Gain Control Bit (Write Protect) + * | | |Gain control is used to enlarge the gain of crystal to make sure crystal work normally. + * | | |If gain control is enabled, crystal will consume more power than gain control off. + * | | |00 = HXT frequency is lower than from 8 MHz. + * | | |01 = HXT frequency is from 8 MHz to 12 MHz. + * | | |10 = HXT frequency is from 12 MHz to 16 MHz. + * | | |11 = HXT frequency is higher than 16 MHz. + * | | |Note: These bits are write protected. Refer to the SYS_REGLCTL register. + * |[12] |HXTSELTYP |HXT Crystal Type Select Bit (Write Protect) + * | | |0 = Select INV type. + * | | |1 = Select GM type. + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * |[13] |HXTTBEN |HXT Crystal TURBO Mode (Write Protect) + * | | |0 = HXT Crystal TURBO mode disabled. + * | | |1 = HXT Crystal TURBO mode enabled. + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * |[18] |HIRC48EN |HIRC48 Enable Bit (Write Protect) + * | | |0 = 48 MHz internal high speed RC oscillator (HIRC48) Disabled. + * | | |1 = 48 MHz internal high speed RC oscillator (HIRC48) Enabled. + * | | |Note 1: This bit is write protected. Refer to the SYS_REGLCTL register. + * | | |Note 2: HIRC48 cannot be disabled and HIRC48EN will always read as 1 if HCLK clock source is selected from HIRC48. + * |[20] |MIRC1P2MEN|MIRC1P2M Enable Bit (Write Protect) + * | | |0 = 1.2 MHz internal medium speed RC oscillator (MIRC1P2M) Disabled. + * | | |1 = 1.2 MHz internal medium speed RC oscillator (MIRC1P2M) Enabled. + * | | |Note 1: This bit is write protected. Refer to the SYS_REGLCTL register. + * | | |Note 2: This clock source only for LCD use. + * |[21] |MIRCEN |MIRC Enable Bit (Write Protect) + * | | |0 = 4 MHz internal medium speed RC oscillator (MIRC) Disabled. + * | | |1 = 4 MHz internal medium speed RC oscillator (MIRC) Enabled. + * | | |Note 1: This bit is write protected. Refer to the SYS_REGLCTL register. + * | | |Note 2: MIRC cannot be disabled and MIRC will always read as 1 if HCLK clock source is selected from MIRC. + * @var CLK_T::AHBCLK + * Offset: 0x04 AHB Devices Clock Enable Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |PDMA0CKEN |PDMA0 Controller Clock Enable Bit (Secure) + * | | |0 = PDMA0 peripheral clock Disabled. + * | | |1 = PDMA0 peripheral clock Enabled. + * |[1] |PDMA1CKEN |PDMA1 Controller Clock Enable Bit + * | | |0 = PDMA1 peripheral clock Disabled. + * | | |1 = PDMA1 peripheral clock Enabled. + * |[2] |ISPCKEN |Flash ISP Controller Clock Enable Bit + * | | |0 = Flash ISP peripheral clock Disabled. + * | | |1 = Flash ISP peripheral clock Enabled. + * |[3] |EBICKEN |EBI Controller Clock Enable Bit + * | | |0 = EBI peripheral clock Disabled. + * | | |1 = EBI peripheral clock Enabled. + * |[4] |EXSTCKEN |External System Tick Clock Enable Bit + * | | |0 = External System tick clock Disabled. + * | | |1 = External System tick clock Enabled. + * |[6] |SDH0CKEN |SDHOST0 Controller Clock Enable Bit + * | | |0 = SDHOST0 peripheral clock Disabled. + * | | |1 = SDHOST0 peripheral clock Enabled. + * |[7] |CRCCKEN |CRC Generator Controller Clock Enable Bit + * | | |0 = CRC peripheral clock Disabled. + * | | |1 = CRC peripheral clock Enabled. + * |[12] |CRPTCKEN |Cryptographic Accelerator Clock Enable Bit + * | | |0 = Cryptographic Accelerator clock Disabled. + * | | |1 = Cryptographic Accelerator clock Enabled. + * |[13] |KSCKEN |Key Store Clock Enable Bit + * | | |0 = Key store clock Disabled. + * | | |1 = Key store clock Enabled. + * |[14] |TRACECKEN |Trace Clock Enable Bit + * | | |0 = Trace clock Disabled. + * | | |1 = Trace clock Enabled. + * |[15] |FMCIDLE |Flash Memory Controller Clock Enable Bit in IDLE Mode + * | | |0 = FMC clock Disabled when chip is under IDLE mode. + * | | |1 = FMC clock Enabled when chip is under IDLE mode. + * |[16] |USBHCKEN |USB HOST 1.1 Controller Clock Enable Bit + * | | |0 = USB HOST 1.1 peripheral clock Disabled. + * | | |1 = USB HOST 1.1 peripheral clock Enabled. + * |[20] |SRAM0CKEN |SRAM Bank0 Controller Clock Enable Bit + * | | |0 = SRAM bank0 clock Disabled. + * | | |1 = SRAM bank0 clock Enabled. + * |[21] |SRAM1CKEN |SRAM Bank1 Controller Clock Enable Bit + * | | |0 = SRAM bank1 clock Disabled. + * | | |1 = SRAM bank1 clock Enabled. + * |[22] |SRAM2CKEN |SRAM Bank2 Controller Clock Enable Bit + * | | |0 = SRAM bank2 clock Disabled. + * | | |1 = SRAM bank2 clock Enabled. + * |[24] |GPACKEN |GPIOA Clock Enable Bit + * | | |0 = GPIOA port clock Disabled. + * | | |1 = GPIOA port clock Enabled. + * |[25] |GPBCKEN |GPIOB Clock Enable Bit + * | | |0 = GPIOB port clock Disabled. + * | | |1 = GPIOB port clock Enabled. + * |[26] |GPCCKEN |GPIOC Clock Enable Bit + * | | |0 = GPIOC port clock Disabled. + * | | |1 = GPIOC port clock Enabled. + * |[27] |GPDCKEN |GPIOD Clock Enable Bit + * | | |0 = GPIOD port clock Disabled. + * | | |1 = GPIOD port clock Enabled. + * |[28] |GPECKEN |GPIOE Clock Enable Bit + * | | |0 = GPIOE port clock Disabled. + * | | |1 = GPIOE port clock Enabled. + * |[29] |GPFCKEN |GPIOF Clock Enable Bit + * | | |0 = GPIOF port clock Disabled. + * | | |1 = GPIOF port clock Enabled. + * |[30] |GPGCKEN |GPIOG Clock Enable Bit + * | | |0 = GPIOG port clock Disabled. + * | | |1 = GPIOG port clock Enabled. + * |[31] |GPHCKEN |GPIOH Clock Enable Bit + * | | |0 = GPIOH port clock Disabled. + * | | |1 = GPIOH port clock Enabled. + * @var CLK_T::APBCLK0 + * Offset: 0x08 APB Devices Clock Enable Control Register 0 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |WDTCKEN |Watchdog Timer Clock Enable Bit (Write Protect) + * | | |0 = Watchdog timer and Windows watchdog timer clock Disabled. + * | | |1 = Watchdog timer and Windows watchdog timer clock Enabled. + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * |[1] |RTCCKEN |Real-time-clock APB Interface Clock Enable Bit + * | | |This bit is used to control the RTC APB clock only. + * | | |The RTC peripheral clock source is selected from RTCCKSEL(RTC_LXTCTL[7]). + * | | |It can be selected to 32.768 kHz external low speed crystal (LXT) or 32 kHz internal low speed RC oscillator (LIRC). + * | | |0 = RTC clock Disabled. + * | | |1 = RTC clock Enabled. + * |[2] |TMR0CKEN |Timer0 Clock Enable Bit + * | | |0 = Timer0 clock Disabled. + * | | |1 = Timer0 clock Enabled. + * |[3] |TMR1CKEN |Timer1 Clock Enable Bit + * | | |0 = Timer1 clock Disabled. + * | | |1 = Timer1 clock Enabled. + * |[4] |TMR2CKEN |Timer2 Clock Enable Bit + * | | |0 = Timer2 clock Disabled. + * | | |1 = Timer2 clock Enabled. + * |[5] |TMR3CKEN |Timer3 Clock Enable Bit + * | | |0 = Timer3 clock Disabled. + * | | |1 = Timer3 clock Enabled. + * |[6] |CLKOCKEN |CLKO Clock Enable Bit + * | | |0 = CLKO clock Disabled. + * | | |1 = CLKO clock Enabled. + * |[7] |ACMP01CKEN|Analog Comparator 0/1 Clock Enable Bit + * | | |0 = Analog comparator 0/1 clock Disabled. + * | | |1 = Analog comparator 0/1 clock Enabled. + * |[8] |I2C0CKEN |I2C0 Clock Enable Bit + * | | |0 = I2C0 clock Disabled. + * | | |1 = I2C0 clock Enabled. + * |[9] |I2C1CKEN |I2C1 Clock Enable Bit + * | | |0 = I2C1 clock Disabled. + * | | |1 = I2C1 clock Enabled. + * |[10] |I2C2CKEN |I2C2 Clock Enable Bit + * | | |0 = I2C2 clock Disabled. + * | | |1 = I2C2 clock Enabled. + * |[12] |QSPI0CKEN |QSPI0 Clock Enable Bit + * | | |0 = QSPI0 clock Disabled. + * | | |1 = QSPI0 clock Enabled. + * |[13] |SPI0CKEN |SPI0 Clock Enable Bit + * | | |0 = SPI0 clock Disabled. + * | | |1 = SPI0 clock Enabled. + * |[14] |SPI1CKEN |SPI1 Clock Enable Bit + * | | |0 = SPI1 clock Disabled. + * | | |1 = SPI1 clock Enabled. + * |[15] |SPI2CKEN |SPI2 Clock Enable Bit + * | | |0 = SPI2 clock Disabled. + * | | |1 = SPI2 clock Enabled. + * |[16] |UART0CKEN |UART0 Clock Enable Bit + * | | |0 = UART0 clock Disabled. + * | | |1 = UART0 clock Enabled. + * |[17] |UART1CKEN |UART1 Clock Enable Bit + * | | |0 = UART1 clock Disabled. + * | | |1 = UART1 clock Enabled. + * |[18] |UART2CKEN |UART2 Clock Enable Bit + * | | |0 = UART2 clock Disabled. + * | | |1 = UART2 clock Enabled. + * |[19] |UART3CKEN |UART3 Clock Enable Bit + * | | |0 = UART3 clock Disabled. + * | | |1 = UART3 clock Enabled. + * |[20] |UART4CKEN |UART4 Clock Enable Bit + * | | |0 = UART4 clock Disabled. + * | | |1 = UART4 clock Enabled. + * |[21] |UART5CKEN |UART5 Clock Enable Bit + * | | |0 = UART5 clock Disabled. + * | | |1 = UART5 clock Enabled. + * |[24] |CAN0CKEN |CAN0 Clock Enable Bit + * | | |0 = CAN0 clock Disabled. + * | | |1 = CAN0 clock Enabled. + * |[26] |OTGCKEN |USB OTG Clock Enable Bit + * | | |0 = USB OTG clock Disabled. + * | | |1 = USB OTG clock Enabled. + * |[27] |USBDCKEN |USB Device Clock Enable Bit + * | | |0 = USB Device clock Disabled. + * | | |1 = USB Device clock Enabled. + * |[28] |EADCCKEN |Enhanced Analog-digital-converter (EADC) Clock Enable Bit + * | | |0 = EADC clock Disabled. + * | | |1 = EADC clock Enabled. + * |[29] |I2S0CKEN |I2S0 Clock Enable Bit + * | | |0 = I2S0 Clock Disabled. + * | | |1 = I2S0 Clock Enabled. + * |[31] |EWDTCKEN |Extra Watchdog Timer Clock Enable Bit (Write Protect) + * | | |0 = Extra Watchdog timer and Extra Windows watchdog timer clock Disabled. + * | | |1 = Extra Watchdog timer and Extra Windows watchdog timer clock Enabled. + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * @var CLK_T::APBCLK1 + * Offset: 0x0C APB Devices Clock Enable Control Register 1 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |SC0CKEN |Smart Card 0 (SC0) Clock Enable Bit + * | | |0 = SC0 clock Disabled. + * | | |1 = SC0 clock Enabled. + * |[1] |SC1CKEN |Smart Card 1 (SC1) Clock Enable Bit + * | | |0 = SC1 clock Disabled. + * | | |1 = SC1 clock Enabled. + * |[2] |SC2CKEN |Smart Card 2 (SC2) Clock Enable Bit + * | | |0 = SC2 clock Disabled. + * | | |1 = SC2 clock Enabled. + * |[4] |TMR4CKEN |Timer4 Clock Enable Bit + * | | |0 = Timer4 clock Disabled. + * | | |1 = Timer4 clock Enabled. + * |[5] |TMR5CKEN |Timer5 Clock Enable Bit + * | | |0 = Timer5 clock Disabled. + * | | |1 = Timer5 clock Enabled. + * |[6] |SPI3CKEN |SPI3 Clock Enable Bit + * | | |0 = SPI3 clock Disabled. + * | | |1 = SPI3 clock Enabled. + * |[8] |USCI0CKEN |USCI0 Clock Enable Bit + * | | |0 = USCI0 clock Disabled. + * | | |1 = USCI0 clock Enabled. + * |[9] |USCI1CKEN |USCI1 Clock Enable Bit + * | | |0 = USCI1 clock Disabled. + * | | |1 = USCI1 clock Enabled. + * |[12] |DACCKEN |DAC Clock Enable Bit + * | | |0 = DAC clock Disabled. + * | | |1 = DAC clock Enabled. + * |[16] |EPWM0CKEN |EPWM0 Clock Enable Bit + * | | |0 = EPWM0 clock Disabled. + * | | |1 = EPWM0 clock Enabled. + * |[17] |EPWM1CKEN |EPWM1 Clock Enable Bit + * | | |0 = EPWM1 clock Disabled. + * | | |1 = EPWM1 clock Enabled. + * |[18] |BPWM0CKEN |BPWM0 Clock Enable Bit + * | | |0 = BPWM0 clock Disabled. + * | | |1 = BPWM0 clock Enabled. + * |[19] |BPWM1CKEN |BPWM1 Clock Enable Bit + * | | |0 = BPWM1 clock Disabled. + * | | |1 = BPWM1 clock Enabled. + * |[22] |QEI0CKEN |QEI0 Clock Enable Bit + * | | |0 = QEI0 clock Disabled. + * | | |1 = QEI0 clock Enabled. + * |[23] |QEI1CKEN |QEI1 Clock Enable Bit + * | | |0 = QEI1 clock Disabled. + * | | |1 = QEI1 clock Enabled. + * |[25] |TRNGCKEN |TRNG Clock Enable Bit + * | | |0 = TRNG clock Disabled. + * | | |1 = TRNG clock Enabled. + * |[26] |ECAP0CKEN |ECAP0 Clock Enable Bit + * | | |0 = ECAP0 clock Disabled. + * | | |1 = ECAP0 clock Enabled. + * |[27] |ECAP1CKEN |ECAP1 Clock Enable Bit + * | | |0 = ECAP1 clock Disabled. + * | | |1 = ECAP1 clock Enabled. + * |[28] |LCDCPCKEN |LCD Charge Pump Clock Enable Bit + * | | |0 = LCD charge pump clock Disabled. + * | | |1 = LCD charge pump clock Enabled. + * @var CLK_T::CLKSEL0 + * Offset: 0x10 Clock Source Select Control Register 0 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[2:0] |HCLKSEL |HCLK Clock Source Selection (Write Protect) + * | | |Before clock switching, the related clock sources (both pre-select and new-select) must be turned on. + * | | |000 = Clock source from HXT. + * | | |001 = Clock source from LXT. + * | | |010 = Clock source from PLL. + * | | |011 = Clock source from LIRC. + * | | |100 = Reserved. + * | | |101 = Clock source from HIRC48. + * | | |110 = Clock source from MIRC. + * | | |111 = Clock source from HIRC. + * | | |Note: These bits are write protected. Refer to the SYS_REGLCTL register. + * |[5:3] |STCLKSEL |SysTick Clock Source Selection (Write Protect) + * | | |If SYST_CTRL[2]=0, SysTick uses listed clock source below. + * | | |000 = Clock source from HXT. + * | | |001 = Clock source from LXT. + * | | |010 = Clock source from HXT/2. + * | | |011 = Clock source from HCLK/2. + * | | |111 = Clock source from HIRC/2. + * | | |Others = Reserved. + * | | |Note1: if SysTick clock source is not from HCLK (i.e SYST_CTRL[2] = 0), + * | | |SysTick need to enable EXSTCKEN(CLK_AHBCLK[4]) and clock frequency must less than or equal to HCLK/2. + * | | |Note2: These bits are write protected. Refer to the SYS_REGLCTL register. + * |[8] |USBSEL |USB Clock Source Selection (Write Protect) + * | | |0 = Clock source from HIRC48. + * | | |1 = Clock source from PLL. + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * |[21:20] |SDH0SEL |SDHOST0 Peripheral Clock Source Selection (Write Protect) + * | | |00 = Clock source from HXT clock. + * | | |01 = Clock source from PLL clock. + * | | |10 = Clock source from HCLK. + * | | |11 = Clock source from HIRC clock. + * | | |Note: These bits are write protected. Refer to the SYS_REGLCTL register. + * @var CLK_T::CLKSEL1 + * Offset: 0x14 Clock Source Select Control Register 1 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[1:0] |WDTSEL |Watchdog Timer Clock Source Selection (Write Protect) + * | | |00 = Reserved. + * | | |01 = Clock source from 32.768 kHz external low speed crystal oscillator (LXT). + * | | |10 = Clock source from HCLK/2048. + * | | |11 = Clock source from 32 kHz internal low speed RC oscillator (LIRC). + * | | |Note: These bits are write protected. Refer to the SYS_REGLCTL register. + * |[2] |LCDSEL |LCD Clock Source Selection + * | | |0 = Clock source from 32 kHz internal low speed RC oscillator (LIRC). + * | | |1 = Clock source from 32.768 kHz external low speed crystal oscillator (LXT). + * |[3] |LCDCPSEL |LCD Charge Pump Clock Source Selection + * | | |0 = Clock source from 1.2 MHz internal medium speed RC oscillator (MIRC1P2M). + * | | |1 = Clock source from 4 MHz internal medium speed RC oscillator (MIRC). + * |[5:4] |EWDTSEL |Extra Watchdog Timer Clock Source Selection (Write Protect) + * | | |00 = Reserved. + * | | |01 = Clock source from 32.768 kHz external low speed crystal oscillator (LXT). + * | | |10 = Clock source from HCLK/2048. + * | | |11 = Clock source from 32 kHz internal low speed RC oscillator (LIRC). + * | | |Note: These bits are write protected. Refer to the SYS_REGLCTL register. + * |[7:6] |EWWDTSEL |Extra Window Watchdog Timer Clock Source Selection (Write Protect) + * | | |10 = Clock source from HCLK/2048. + * | | |11 = Clock source from 32 kHz internal low speed RC oscillator (LIRC). + * | | |Others = Reserved. + * | | |Note: These bits are write protected. Refer to the SYS_REGLCTL register. + * |[10:8] |TMR0SEL |TIMER0 Clock Source Selection + * | | |000 = Clock source from 4~24 MHz external high speed crystal oscillator (HXT). + * | | |001 = Clock source from 32.768 kHz external low speed crystal oscillator (LXT). + * | | |010 = Clock source from PCLK0. + * | | |011 = Clock source from external clock TM0 pin. + * | | |101 = Clock source from 32 kHz internal low speed RC oscillator (LIRC). + * | | |111 = Clock source from 12 MHz internal high speed RC oscillator (HIRC). + * | | |Others = Reserved. + * |[14:12] |TMR1SEL |TIMER1 Clock Source Selection + * | | |000 = Clock source from 4~24 MHz external high speed crystal oscillator (HXT). + * | | |001 = Clock source from 32.768 kHz external low speed crystal oscillator (LXT). + * | | |010 = Clock source from PCLK0. + * | | |011 = Clock source from external clock TM1 pin. + * | | |101 = Clock source from 32 kHz internal low speed RC oscillator (LIRC). + * | | |111 = Clock source from 12 MHz internal high speed RC oscillator (HIRC). + * | | |Others = Reserved. + * |[18:16] |TMR2SEL |TIMER2 Clock Source Selection + * | | |000 = Clock source from 4~24 MHz external high speed crystal oscillator (HXT). + * | | |001 = Clock source from 32.768 kHz external low speed crystal oscillator (LXT). + * | | |010 = Clock source from PCLK1. + * | | |011 = Clock source from external clock TM2 pin. + * | | |101 = Clock source from 32 kHz internal low speed RC oscillator (LIRC). + * | | |111 = Clock source from 12 MHz internal high speed RC oscillator (HIRC). + * | | |Others = Reserved. + * |[22:20] |TMR3SEL |TIMER3 Clock Source Selection + * | | |000 = Clock source from 4~24 MHz external high speed crystal oscillator (HXT). + * | | |001 = Clock source from 32.768 kHz external low speed crystal oscillator (LXT). + * | | |010 = Clock source from PCLK1. + * | | |011 = Clock source from external clock TM3 pin. + * | | |101 = Clock source from 32 kHz internal low speed RC oscillator (LIRC). + * | | |111 = Clock source from 12 MHz internal high speed RC oscillator (HIRC). + * | | |Others = Reserved. + * |[29:28] |CLKOSEL |Clock Output Clock Source Selection + * | | |00 = Clock source from 4~24 MHz external high speed crystal oscillator (HXT). + * | | |01 = Clock source from 32.768 kHz external low speed crystal oscillator (LXT). + * | | |10 = Clock source from HCLK. + * | | |11 = Clock source from 12 MHz internal high speed RC oscillator (HIRC). + * |[31:30] |WWDTSEL |Window Watchdog Timer Clock Source Selection (Write Protect) + * | | |10 = Clock source from HCLK/2048. + * | | |11 = Clock source from 10 kHz internal low speed RC oscillator (LIRC). + * | | |Others = Reserved. + * | | |Note: These bits are write protected. Refer to the SYS_REGLCTL register. + * @var CLK_T::CLKSEL2 + * Offset: 0x18 Clock Source Select Control Register 2 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |EPWM0SEL |EPWM0 Clock Source Selection (Read Only) + * | | |The peripheral clock source of EPWM0 is defined by EPWM0SEL. + * | | |1 = Clock source from PCLK0. + * |[1] |EPWM1SEL |EPWM1 Clock Source Selection (Read Only) + * | | |The peripheral clock source of EPWM1 is defined by EPWM1SEL. + * | | |1 = Clock source from PCLK1. + * |[3:2] |QSPI0SEL |QSPI0 Clock Source Selection + * | | |00 = Clock source from 4~24 MHz external high speed crystal oscillator (HXT). + * | | |01 = Clock source from PLL. + * | | |10 = Clock source from PCLK0. + * | | |11 = Clock source from 12 MHz internal high speed RC oscillator (HIRC). + * |[5:4] |SPI0SEL |SPI0 Clock Source Selection + * | | |00 = Clock source from 4~24 MHz external high speed crystal oscillator (HXT). + * | | |01 = Clock source from PLL. + * | | |10 = Clock source from PCLK1. + * | | |11 = Clock source from 12 MHz internal high speed RC oscillator (HIRC). + * |[7:6] |SPI1SEL |SPI1 Clock Source Selection + * | | |00 = Clock source from 4~24 MHz external high speed crystal oscillator (HXT). + * | | |01 = Clock source from PLL. + * | | |10 = Clock source from PCLK0. + * | | |11 = Clock source from 12 MHz internal high speed RC oscillator (HIRC). + * |[8] |BPWM0SEL |BPWM0 Clock Source Selection (Read Only) + * | | |The peripheral clock source of BPWM0 is defined by BPWM0SEL. + * | | |1 = Clock source from PCLK0. + * |[9] |BPWM1SEL |BPWM1 Clock Source Selection (Read Only) + * | | |The peripheral clock source of BPWM1 is defined by BPWM1SEL. + * | | |1 = Clock source from PCLK1. + * |[11:10] |SPI2SEL |SPI2 Clock Source Selection + * | | |00 = Clock source from 4~24 MHz external high speed crystal oscillator (HXT). + * | | |01 = Clock source from PLL. + * | | |10 = Clock source from PCLK1. + * | | |11 = Clock source from 12 MHz internal high speed RC oscillator (HIRC). + * |[13:12] |SPI3SEL |SPI3 Clock Source Selection + * | | |00 = Clock source from 4~24 MHz external high speed crystal oscillator (HXT). + * | | |01 = Clock source from PLL. + * | | |10 = Clock source from PCLK0. + * | | |11 = Clock source from 12 MHz internal high speed RC oscillator (HIRC). + * |[18:16] |UART0SEL |UART0 Clock Source Selection + * | | |000 = Clock source from 4~24 MHz external high speed crystal oscillator (HXT). + * | | |001 = Clock source from PLL. + * | | |010 = Clock source from 32.768 kHz external low speed crystal oscillator (LXT). + * | | |011 = Clock source from 12 MHz internal high speed RC oscillator (HIRC). + * | | |100 = Clock source from PCLK0. + * | | |Others = Reserved. + * |[22:20] |UART1SEL |UART1 Clock Source Selection + * | | |000 = Clock source from 4~24 MHz external high speed crystal oscillator (HXT). + * | | |001 = Clock source from PLL. + * | | |010 = Clock source from 32.768 kHz external low speed crystal oscillator (LXT). + * | | |011 = Clock source from 12 MHz internal high speed RC oscillator (HIRC). + * | | |100 = Clock source from PCLK1. + * | | |Others = Reserved. + * |[26:24] |UART2SEL |UART2 Clock Source Selection + * | | |000 = Clock source from 4~24 MHz external high speed crystal oscillator (HXT). + * | | |001 = Clock source from PLL. + * | | |010 = Clock source from 32.768 kHz external low speed crystal oscillator (LXT). + * | | |011 = Clock source from 12 MHz internal high speed RC oscillator (HIRC). + * | | |100 = Clock source from PCLK0. + * | | |Others = Reserved. + * |[32:28] |UART3SEL |UART3 Clock Source Selection + * | | |000 = Clock source from 4~24 MHz external high speed crystal oscillator (HXT). + * | | |001 = Clock source from PLL. + * | | |010 = Clock source from 32.768 kHz external low speed crystal oscillator (LXT). + * | | |011 = Clock source from 12 MHz internal high speed RC oscillator (HIRC). + * | | |100 = Clock source from PCLK1. + * | | |Others = Reserved. + * @var CLK_T::CLKSEL3 + * Offset: 0x1C Clock Source Select Control Register 3 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[1:0] |SC0SEL |Smart Card 0 (SC0) Clock Source Selection + * | | |00 = Clock source from 4~24 MHz external high speed crystal oscillator (HXT). + * | | |01 = Clock source from PLL. + * | | |10 = Clock source from PCLK0. + * | | |11 = Clock source from 12 MHz internal high speed RC oscillator (HIRC). + * |[3:2] |SC1SEL |Smart Card 1 (SC1) Clock Source Selection + * | | |00 = Clock source from 4~24 MHz external high speed crystal oscillator (HXT). + * | | |01 = Clock source from PLL. + * | | |10 = Clock source from PCLK1. + * | | |11 = Clock source from 12 MHz internal high speed RC oscillator (HIRC). + * |[5:4] |SC2SEL |Smart Card 2 (SC2) Clock Source Selection + * | | |00 = Clock source from 4~24 MHz external high speed crystal oscillator (HXT). + * | | |01 = Clock source from PLL. + * | | |10 = Clock source from PCLK0. + * | | |11 = Clock source from 12 MHz internal high speed RC oscillator (HIRC). + * |[10:8] |TMR4SEL |TIMER4 Clock Source Selection + * | | |000 = Clock source from 4~24 MHz external high speed crystal oscillator (HXT). + * | | |001 = Clock source from 32.768 kHz external low speed crystal oscillator (LXT). + * | | |010 = Clock source from PCLK0. + * | | |011 = Clock source from external clock TM4 pin. + * | | |100 = Clock source from 4 MHz internal medium speed RC oscillator (MIRC). + * | | |101 = Clock source from 32 kHz internal low speed RC oscillator (LIRC). + * | | |110 = Reserved. + * | | |111 = Clock source from 12 MHz internal high speed RC oscillator (HIRC). + * |[14:12] |TMR5SEL |TIMER5 Clock Source Selection + * | | |000 = Clock source from 4~24 MHz external high speed crystal oscillator (HXT). + * | | |001 = Clock source from 32.768 kHz external low speed crystal oscillator (LXT). + * | | |010 = Clock source from PCLK0. + * | | |011 = Clock source from external clock TM5 pin. + * | | |100 = Clock source from 4 MHz internal medium speed RC oscillator (MIRC). + * | | |101 = Clock source from 32 kHz internal low speed RC oscillator (LIRC). + * | | |110 = Reserved. + * | | |111 = Clock source from 12 MHz internal high speed RC oscillator (HIRC). + * |[17:16] |I2S0SEL |I2S0 Clock Source Selection + * | | |00 = Clock source from HXT clock. + * | | |01 = Clock source from PLL clock. + * | | |10 = Clock source from PCLK0. + * | | |11 = Clock source from HIRC clock. + * |[27:24] |UART4SEL |UART4 Clock Source Selection + * | | |000 = Clock source from 4~24 MHz external high speed crystal oscillator (HXT). + * | | |001 = Clock source from PLL. + * | | |010 = Clock source from 32.768 kHz external low speed crystal oscillator (LXT). + * | | |011 = Clock source from 12 MHz internal high speed RC oscillator (HIRC). + * | | |100 = Clock source from PCLK0. + * | | |Others = Reserved. + * |[28:30] |UART5SEL |UART5 Clock Source Selection + * | | |000 = Clock source from 4~24 MHz external high speed crystal oscillator (HXT). + * | | |001 = Clock source from PLL. + * | | |010 = Clock source from 32.768 kHz external low speed crystal oscillator (LXT). + * | | |011 = Clock source from 12 MHz internal high speed RC oscillator (HIRC). + * | | |100 = Clock source from PCLK1. + * | | |Others = Reserved. + * @var CLK_T::CLKDIV0 + * Offset: 0x20 Clock Divider Number Register 0 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[3:0] |HCLKDIV |HCLK Clock Divide Number from HCLK Clock Source + * | | |HCLK clock frequency = (HCLK clock source frequency) / (HCLKDIV + 1). + * |[7:4] |USBDIV |USB Clock Divide Number from USB Clock Source + * | | |USB clock frequency = (USB clock source frequency) / (USBDIV + 1). + * |[11:8] |UART0DIV |UART0 Clock Divide Number from UART0 Clock Source + * | | |UART0 clock frequency = (UART0 clock source frequency) / (UART0DIV + 1). + * |[15:12] |UART1DIV |UART1 Clock Divide Number from UART1 Clock Source + * | | |UART1 clock frequency = (UART1 clock source frequency) / (UART1DIV + 1). + * |[23:16] |EADCDIV |EADC Clock Divide Number from EADC Clock Source + * | | |EADC clock frequency = (EADC clock source frequency) / (EADCDIV + 1). + * |[31:24] |SDH0DIV |SDHOST0 Clock Divide Number from SDHOST0 Clock Source + * | | |SDHOST0 clock frequency = (SDHOST0 clock source frequency) / (SDH0DIV + 1). + * @var CLK_T::CLKDIV1 + * Offset: 0x24 Clock Divider Number Register 1 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[7:0] |SC0DIV |Smart Card 0 (SC0) Clock Divide Number from SC0 Clock Source + * | | |SC0 clock frequency = (SC0 clock source frequency) / (SC0DIV + 1). + * |[15:8] |SC1DIV |Smart Card 1 (SC1) Clock Divide Number from SC1 Clock Source + * | | |SC1 clock frequency = (SC1 clock source frequency) / (SC1DIV + 1). + * |[23:16] |SC2DIV |Smart Card 2 (SC2) Clock Divide Number from SC2 Clock Source + * | | |SC2 clock frequency = (SC2 clock source frequency) / (SC2DIV + 1). + * @var CLK_T::CLKDIV4 + * Offset: 0x30 Clock Divider Number Register 4 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[3:0] |UART2DIV |UART2 Clock Divide Number from UART2 Clock Source + * | | |UART2 clock frequency = (UART2 clock source frequency) / (UART2DIV + 1). + * |[7:4] |UART3DIV |UART3 Clock Divide Number from UART3 Clock Source + * | | |UART3 clock frequency = (UART3 clock source frequency) / (UART3DIV + 1). + * |[11:8] |UART4DIV |UART4 Clock Divide Number from UART4 Clock Source + * | | |UART4 clock frequency = (UART4 clock source frequency) / (UART4DIV + 1). + * |[15:12] |UART5DIV |UART5 Clock Divide Number from UART5 Clock Source + * | | |UART5 clock frequency = (UART5 clock source frequency) / (UART5DIV + 1). + * @var CLK_T::PLLCTL + * Offset: 0x40 PLL Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[8:0] |FBDIV |PLL Feedback Divider Control (Write Protect) + * | | |Refer to the PLL formulas. + * | | |Note: These bits are write protected. Refer to the SYS_REGLCTL register. + * |[13:9] |INDIV |PLL Input Divider Control (Write Protect) + * | | |Refer to the PLL formulas. + * | | |Note: These bits are write protected. Refer to the SYS_REGLCTL register. + * |[15:14] |OUTDIV |PLL Output Divider Control (Write Protect) + * | | |Refer to the PLL formulas. + * | | |Note: These bits are write protected. Refer to the SYS_REGLCTL register. + * |[16] |PD |Power-down Mode (Write Protect) + * | | |0 = PLL is enable (in normal mode). + * | | |1 = PLL is disable (in Power-down mode) (default). + * | | |Note1: If set the PDEN bit to 1 in CLK_PWRCTL register, the PLL will enter Power-down mode, too. + * | | |Note2: This bit is write protected. Refer to the SYS_REGLCTL register. + * |[17] |BP |PLL Bypass Control (Write Protect) + * | | |0 = PLL is in normal mode (default). + * | | |1 = PLL clock output is same as PLL input clock FIN. + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * |[19] |PLLSRC |PLL Source Clock Selection (Write Protect) + * | | |0 = PLL source clock from 4~24 MHz external high-speed crystal oscillator (HXT). + * | | |1 = PLL source clock from 12 MHz internal high-speed oscillator (HIRC). + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * |[23] |STBSEL |PLL Stable Counter Selection (Write Protect) + * | | |0 = PLL stable time is 6144 PLL source clock (suitable for source clock is equal to or less than 12 MHz). + * | | |1 = PLL stable time is 12288 PLL source clock (suitable for source clock is larger than 12 MHz). + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * @var CLK_T::STATUS + * Offset: 0x50 Clock Status Monitor Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |HXTSTB |HXT Clock Source Stable Flag (Read Only) + * | | |0 = 4~24 MHz external high speed crystal oscillator (HXT) clock is not stable or disabled. + * | | |1 = 4~24 MHz external high speed crystal oscillator (HXT) clock is stable and enabled. + * |[1] |LXTSTB |LXT Clock Source Stable Flag (Read Only) + * | | |LXT clock source can be selected as extLXT or LIRC32 by setting C32KS(RTC_LXTCTL[7]). + * | | |If C32KS is set to 0 the LXT stable flag is set when extLXT clock source is stable. + * | | |If C32KS is set to 1 the LXT stable flag is set when LIRC32 clock source is stable. + * | | |0 = 32.768 kHz external low speed crystal oscillator (LXT) clock is not stable or disabled. + * | | |1 = 32.768 kHz external low speed crystal oscillator (LXT) clock is stabled and enabled. + * |[2] |PLLSTB |Internal PLL Clock Source Stable Flag (Read Only) + * | | |0 = Internal PLL clock is not stable or disabled. + * | | |1 = Internal PLL clock is stable and enabled. + * |[3] |LIRCSTB |LIRC Clock Source Stable Flag (Read Only) + * | | |0 = 32 kHz internal low speed RC oscillator (LIRC) clock is not stable or disabled. + * | | |1 = 32 kHz internal low speed RC oscillator (LIRC) clock is stable and enabled. + * |[4] |HIRCSTB |HIRC Clock Source Stable Flag (Read Only) + * | | |0 = 12 MHz internal high speed RC oscillator (HIRC) clock is not stable or disabled. + * | | |1 = 12 MHz internal high speed RC oscillator (HIRC) clock is stable and enabled. + * |[5] |MIRCSTB |MIRC Clock Source Stable Flag (Read Only) + * | | |0 = 4 MHz internal medium speed RC oscillator (MIRC) clock is not stable or disabled. + * | | |1 = 4 MHz internal medium speed RC oscillator (MIRC) clock is stable and enabled. + * |[6] |HIRC48STB |HIRC48 Clock Source Stable Flag (Read Only) + * | | |0 = 48 MHz internal high speed RC oscillator (HIRC48) clock is not stable or disabled. + * | | |1 = 48 MHz internal high speed RC oscillator (HIRC48) clock is stable and enabled. + * |[7] |CLKSFAIL |Clock Switching Fail Flag (Read Only) + * | | |This bit is updated when software switches system clock source. + * | | |If switch target clock is stable, this bit will be set to 0. + * | | |If switch target clock is not stable, this bit will be set to 1. + * | | |0 = Clock switching success. + * | | |1 = Clock switching failure. + * | | |Note: This bit is read only. + * | | |After selected clock source is stable, hardware will switch system clock to selected clock automatically, and CLKSFAIL will be cleared automatically by hardware. + * |[8] |EXTLXTSTB |EXTLXT Clock Source Stable Flag (Read Only) + * | | |0 = 32.768 kHz external low speed crystal oscillator (extLXT) clock is not stable or disabled. + * | | |1 = 32.768 kHz external low speed crystal oscillator (extLXT) clock is stable and enabled. + * |[9] |LIRC32STB |LIRC32 Clock Source Stable Flag (Read Only) + * | | |0 = 32 kHz internal low speed RC oscillator (LIRC32) clock is not stable or disabled. + * | | |1 = 32 kHz internal low speed RC oscillator (LIRC32) clock is stable and enabled. + * @var CLK_T::CLKOCTL + * Offset: 0x60 Clock Output Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[3:0] |FREQSEL |Clock Output Frequency Selection + * | | |The formula of output frequency is Fout = Fin/2^(N+1). + * | | |Fin is the input clock frequency. + * | | |Fout is the frequency of divider output clock. + * | | |N is the 4-bit value of FREQSEL[3:0]. + * |[4] |CLKOEN |Clock Output Enable Bit + * | | |0 = Clock Output function Disabled. + * | | |1 = Clock Output function Enabled. + * |[5] |DIV1EN |Clock Output Divide One Enable Bit + * | | |0 = Clock Output will output clock with source frequency divided by FREQSEL. + * | | |1 = Clock Output will output clock with source frequency. + * |[6] |CLK1HZEN |Clock Output 1Hz Enable Bit + * | | |0 = 1 Hz clock output for 32.768 kHz frequency compensation Disabled. + * | | |1 = 1 Hz clock output for 32.768 kHz frequency compensation Enabled. + * @var CLK_T::CLKDCTL + * Offset: 0x70 Clock Fail Detector Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[4] |HXTFDEN |HXT Clock Fail Detector Enable Bit + * | | |0 = 4~24 MHz external high speed crystal oscillator (HXT) clock fail detector Disabled. + * | | |1 = 4~24 MHz external high speed crystal oscillator (HXT) clock fail detector Enabled. + * |[5] |HXTFIEN |HXT Clock Fail Interrupt Enable Bit + * | | |0 = 4~24 MHz external high speed crystal oscillator (HXT) clock fail interrupt Disabled. + * | | |1 = 4~24 MHz external high speed crystal oscillator (HXT) clock fail interrupt Enabled. + * |[6] |HXTFDSEL |HXT Clock Fail Detector Selection + * | | |0 = 4~24 MHz external high speed crystal oscillator (HXT) clock fail detector after HXT stable. + * | | |1 = 4~24 MHz external high speed crystal oscillator (HXT) clock fail detector bypass HXT stable. + * | | |Note: When HXT Clock Fail Detector Selection is set, detector will keep detect whether HXT is stable or not, prevent HXT fail before stable. + * |[12] |LXTFDEN |LXT Clock Fail Detector Enable Bit + * | | |0 = 32.768 kHz external low speed crystal oscillator (LXT) clock fail detector Disabled. + * | | |1 = 32.768 kHz external low speed crystal oscillator (LXT) clock fail detector Enabled. + * |[13] |LXTFIEN |LXT Clock Fail Interrupt Enable Bit + * | | |0 = 32.768 kHz external low speed crystal oscillator (LXT) clock fail interrupt Disabled. + * | | |1 = 32.768 kHz external low speed crystal oscillator (LXT) clock fail interrupt Enabled. + * |[16] |HXTFQDEN |HXT Clock Frequency Monitor Enable Bit + * | | |0 = 4~24 MHz external high speed crystal oscillator (HXT) clock frequency monitor Disabled. + * | | |1 = 4~24 MHz external high speed crystal oscillator (HXT) clock frequency monitor Enabled. + * |[17] |HXTFQIEN |HXT Clock Frequency Monitor Interrupt Enable Bit + * | | |0 = 4~24 MHz external high speed crystal oscillator (HXT) clock frequency monitor fail interrupt Disabled. + * | | |1 = 4~24 MHz external high speed crystal oscillator (HXT) clock frequency monitor fail interrupt Enabled. + * @var CLK_T::CLKDSTS + * Offset: 0x74 Clock Fail Detector Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |HXTFIF |HXT Clock Fail Interrupt Flag (Write Protect) + * | | |0 = 4~24 MHz external high speed crystal oscillator (HXT) clock is normal. + * | | |1 = 4~24 MHz external high speed crystal oscillator (HXT) clock stops. + * | | |Note1: Write 1 to clear the bit to 0. + * | | |Note2: This bit is write protected. Refer to the SYS_REGLCTL register. + * |[1] |LXTFIF |LXT Clock Fail Interrupt Flag (Write Protect) + * | | |0 = 32.768 kHz external low speed crystal oscillator (LXT) clock is normal. + * | | |1 = 32.768 kHz external low speed crystal oscillator (LXT) stops. + * | | |Note1: Write 1 to clear the bit to 0. + * | | |Note2: This bit is write protected. Refer to the SYS_REGLCTL register. + * |[8] |HXTFQIF |HXT Clock Frequency Monitor Interrupt Flag (Write Protect) + * | | |0 = 4~24 MHz external high speed crystal oscillator (HXT) clock is normal. + * | | |1 = 4~24 MHz external high speed crystal oscillator (HXT) clock frequency is abnormal. + * | | |Note1: Write 1 to clear the bit to 0. + * | | |Note2: This bit is write protected. Refer to the SYS_REGLCTL register. + * @var CLK_T::CDUPB + * Offset: 0x78 Clock Frequency Detector Upper Boundary Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[9:0] |UPERBD |HXT Clock Frequency Detector Upper Boundary + * | | |The bits define the high value of frequency monitor window. + * | | |When HXT frequency monitor value higher than this register, the HXT frequency detect fail interrupt flag will set to 1. + * @var CLK_T::CDLOWB + * Offset: 0x7C Clock Frequency Detector Lower Boundary Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[9:0] |LOWERBD |HXT Clock Frequency Detector Lower Boundary + * | | |The bits define the low value of frequency monitor window. + * | | |When HXT frequency monitor value lower than this register, the HXT frequency detect fail interrupt flag will set to 1. + * @var CLK_T::PMUCTL + * Offset: 0x90 Power Manager Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[2:0] |PDMSEL |Power-down Mode Selection (Write Protect) + * | | |These bits control chip Power-down mode grade selection when CPU execute WFI/WFE instruction. + * | | |000 = Power-down mode is selected (PD). + * | | |001 = Low leakage Power-down mode is selected (LLPD). + * | | |010 = Fast wake-up Power-down (FWPD). + * | | |011 = Ultra low leakage Power-down mode is selected (ULLPD). + * | | |100 = Standby Power-down mode is selected (SPD). + * | | |101 = Reserved. + * | | |110 = Deep Power-down mode is selected (DPD). + * | | |111 = Reserved. + * | | |Note: These bits are write protected. Refer to the SYS_REGLCTL register. + * |[4] |VDROPEN |Standby Power Down Mode Regulator Output Voltage Drop Enable Bit (Write Protect) + * | | |If this bit be asserted, regulator output voltage drop to 0.9V when SPD mode. + * | | |0 = Regulator voltage auto drop function Disabled. + * | | |1 = Regulator voltage auto drop function Enabled. (default) + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * |[7] |WRBUSY |Write Busy Flag (Read Only) + * | | |If CLK_PMUCTL be written, this bit be asserted automatic by hardware, and be de-asserted when write procedure finish. + * | | |0 = CLK_PMUCTL write ready. + * | | |1 = CLK_PMUCTL write ignore. + * |[8] |WKTMREN |Wake-up Timer Enable Bit (Write Protect) + * | | |0 = Wake-up timer Disable in Deep Power-down mode or Standby Power-down mode. + * | | |1 = Wake-up timer Enabled in Deep Power-down mode or Standby Power-down mode. + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * |[11:9] |WKTMRIS |Wake-up Timer Time-out Interval Select (Write Protect) + * | | |These bits control wake-up timer time-out interval when chip under Deep Power-down mode or Standby Power-down mode. + * | | |000 = Time-out interval is 410 LIRC clocks (12.8ms). + * | | |001 = Time-out interval is 819 LIRC clocks (25.6ms). + * | | |010 = Time-out interval is 1638 LIRC clocks (51.2ms). + * | | |011 = Time-out interval is 3277 LIRC clocks (102.4ms). + * | | |100 = Time-out interval is 13107 LIRC clocks (409.6ms). + * | | |101 = Time-out interval is 26214 LIRC clocks (819.2ms). + * | | |110 = Time-out interval is 52429 LIRC clocks (1638.4ms). + * | | |111 = Time-out interval is 209715 LIRC clocks (6553.6ms). + * |[17:16] |WKPINEN0 |Wake-up Pin 0 Enable (Write Protect) + * | | |This is control register for GPC.0 to wake-up pin. + * | | |00 = Wake-up pin Disable in Deep Power-down mode. + * | | |01 = Wake-up pin rising edge Enabled in Deep Power-down mode. + * | | |10 = Wake-up pin falling edge Enabled in Deep Power-down mode. + * | | |11 = Wake-up pin both edge Enabled in Deep Power-down mode. + * | | |Note: These bits are write protected. Refer to the SYS_REGLCTL register. + * |[18] |ACMPSPWK |ACMP Standby Power-down Mode Wake-up Enable (Write Protect) + * | | |0 = ACMP wake-up disable in Standby Power-down mode. + * | | |1 = ACMP wake-up enabled in Standby Power-down mode. + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * |[19] |TAMPERWK |Tamper Standby Power-down Mode Wake-up Enable Bit (Write Protect) + * | | |0 = Tamper wake-up disable at Standby Power-down mode. + * | | |1 = Tamper wake-up enabled at Standby Power-down mode. + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * |[23] |RTCWKEN |RTC Wake-up Enable (Write Protect) + * | | |This is a protected register. Please refer to open lock sequence to program it. + * | | |0 = RTC wake-up Disable in Deep Power-down mode or Standby Power-down mode. + * | | |1 = RTC wake-up Enabled in Deep Power-down mode or Standby Power-down mode. + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * |[25:24] |WKPINEN1 |Wake-up Pin 1 Enable (Write Protect) + * | | |This is control register for GPB.0 to wake-up pin. + * | | |00 = Wake-up pin Disable in Deep Power-down mode. + * | | |01 = Wake-up pin rising edge Enabled in Deep Power-down mode. + * | | |10 = Wake-up pin falling edge Enabled in Deep Power-down mode. + * | | |11 = Wake-up pin both edge Enabled in Deep Power-down mode. + * | | |Note: These bits are write protected. Refer to the SYS_REGLCTL register. + * |[27:26] |WKPINEN2 |Wake-up Pin 2 Enable (Write Protect) + * | | |This is control register for GPB.2 to wake-up pin. + * | | |00 = Wake-up pin Disable in Deep Power-down mode. + * | | |01 = Wake-up pin rising edge Enabled in Deep Power-down mode. + * | | |10 = Wake-up pin falling edge Enabled in Deep Power-down mode. + * | | |11 = Wake-up pin both edge Enabled in Deep Power-down mode. + * | | |Note: These bits are write protected. Refer to the SYS_REGLCTL register. + * |[29:28] |WKPINEN3 |Wake-up Pin 3 Enable (Write Protect) + * | | |This is control register for GPB.12 to wake-up pin. + * | | |00 = Wake-up pin Disable in Deep Power-down mode. + * | | |01 = Wake-up pin rising edge Enabled in Deep Power-down mode. + * | | |10 = Wake-up pin falling edge Enabled in Deep Power-down mode. + * | | |11 = Wake-up pin both edge Enabled in Deep Power-down mode. + * | | |Note: These bits are write protected. Refer to the SYS_REGLCTL register. + * |[31:30] |WKPINEN4 |Wake-up Pin 4 Enable (Write Protect) + * | | |This is control register for GPF.6 to wake-up pin. + * | | |00 = Wake-up pin Disable in Deep Power-down mode. + * | | |01 = Wake-up pin rising edge Enabled in Deep Power-down mode. + * | | |10 = Wake-up pin falling edge Enabled in Deep Power-down mode. + * | | |11 = Wake-up pin both edge Enabled in Deep Power-down mode. + * | | |Note: These bits are write protected. Refer to the SYS_REGLCTL register. + * @var CLK_T::PMUSTS + * Offset: 0x94 Power Manager Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |PINWK0 |Pin 0 Wake-up Flag (Read Only) + * | | |This flag indicates that wake-up of chip from Deep Power-down mode (DPD) was requested by a transition of the Wake-up pin (GPC.0). + * | | |This flag is cleared when DPD mode is entered. + * |[1] |TMRWK |Timer Wake-up Flag (Read Only) + * | | |This flag indicates that wake-up of chip from Deep Power-down mode (DPD) or Standby Power-down (SPD) mode was requested by wakeup timer time-out. + * | | |This flag is cleared when DPD or SPD mode is entered. + * |[2] |RTCWK |RTC Wake-up Flag (Read Only) + * | | |This flag indicates that wakeup of device from Deep Power-down mode (DPD) or Standby Power-down (SPD) mode was requested with a RTC alarm, tick time or tamper happened. + * | | |This flag is cleared when DPD or SPD mode is entered. + * |[3] |PINWK1 |Pin 1 Wake-up Flag (Read Only) + * | | |This flag indicates that wake-up of chip from Deep Power-down mode (DPD) was requested by a transition of the Wake-up pin (GPB.0). + * | | |This flag is cleared when DPD mode is entered. + * |[4] |PINWK2 |Pin 2 Wake-up Flag (Read Only) + * | | |This flag indicates that wake-up of chip from Deep Power-down mode (DPD) was requested by a transition of the Wake-up pin (GPB.2). + * | | |This flag is cleared when DPD mode is entered. + * |[5] |PINWK3 |Pin 3 Wake-up Flag (Read Only) + * | | |This flag indicates that wake-up of chip from Deep Power-down mode (DPD) was requested by a transition of the Wake-up pin (GPB.12). + * | | |This flag is cleared when DPD mode is entered. + * |[6] |PINWK4 |Pin 4 Wake-up Flag (Read Only) + * | | |This flag indicates that wake-up of chip from Deep Power-down mode (DPD) was requested by a transition of the Wake-up pin (GPF.6). + * | | |This flag is cleared when DPD mode is entered. + * |[8] |GPAWK |GPA Wake-up Flag (Read Only) + * | | |This flag indicates that wake-up of chip from Standby Power-down mode (SPD) was requested by a transition of selected one GPA group pins. + * | | |This flag is cleared when SPD mode is entered. + * |[9] |GPBWK |GPB Wake-up Flag (Read Only) + * | | |This flag indicates that wake-up of chip from Standby Power-down mode (SPD) was requested by a transition of selected one GPB group pins. + * | | |This flag is cleared when SPD mode is entered. + * |[10] |GPCWK |GPC Wake-up Flag (Read Only) + * | | |This flag indicates that wake-up of chip from Standby Power-down mode (SPD) was requested by a transition of selected one GPC group pins. + * | | |This flag is cleared when SPD mode is entered. + * |[11] |GPDWK |GPD Wake-up Flag (Read Only) + * | | |This flag indicates that wake-up of chip from Standby Power-down mode (SPD) was requested by a transition of selected one GPD group pins. + * | | |This flag is cleared when SPD mode is entered. + * |[12] |LVRWK |LVR Wake-up Flag (Read Only) + * | | |This flag indicates that wake-up of device from Standby Power-down mode (SPD) was requested with a LVR happened. + * | | |This flag is cleared when SPD mode is entered. + * |[13] |BODWK |BOD Wake-up Flag (Read Only) + * | | |This flag indicates that wake-up of device from Standby Power-down mode (SPD) was requested with a BOD happened. + * | | |This flag is cleared when SPD mode is entered. + * |[14] |ACMPWK |ACMP Wake-up Flag (Read Only) + * | | |This flag indicates that wake-up of device from Standby Power-down mode (SPD) was requested with a ACMP transition. + * | | |This flag is cleared when SPD mode is entered. + * |[15] |TAMPERWK |Tamper Wake-up Flag (Read Only) + * | | |This flag indicates that wakeup of device from Standby Power-down mode (SPD) was requested with a Tamper event occurred. + * | | |This flag is cleared when SPD mode is entered. + * |[31] |CLRWK |Clear Wake-up Flag + * | | |0 = No clear. + * | | |1 = Clear all wake-up flag. + * | | |Note: This bit is auto cleared by hardware. + * @var CLK_T::SWKDBCTL + * Offset: 0x9C Standby Power-down Wake-up De-bounce Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[3:0] |SWKDBCLKSEL|Standby Power-down Wake-up De-bounce Sampling Cycle Selection + * | | |0000 = Sample wake-up input once per 1 clocks. + * | | |0001 = Sample wake-up input once per 2 clocks. + * | | |0010 = Sample wake-up input once per 4 clocks. + * | | |0011 = Sample wake-up input once per 8 clocks. + * | | |0100 = Sample wake-up input once per 16 clocks. + * | | |0101 = Sample wake-up input once per 32 clocks. + * | | |0110 = Sample wake-up input once per 64 clocks. + * | | |0111 = Sample wake-up input once per 128 clocks. + * | | |1000 = Sample wake-up input once per 256 clocks. + * | | |1001 = Sample wake-up input once per 2*256 clocks. + * | | |1010 = Sample wake-up input once per 4*256 clocks. + * | | |1011 = Sample wake-up input once per 8*256 clocks. + * | | |1100 = Sample wake-up input once per 16*256 clocks. + * | | |1101 = Sample wake-up input once per 32*256 clocks. + * | | |1110 = Sample wake-up input once per 64*256 clocks. + * | | |1111 = Sample wake-up input once per 128*256 clocks. + * | | |Note: De-bounce counter clock source is the 32 kHz internal low speed RC oscillator (LIRC). + * @var CLK_T::PASWKCTL + * Offset: 0xA0 GPA Standby Power-down Wake-up Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |WKEN |Standby Power-down Pin Wake-up Enable Bit + * | | |0 = GPA group pin wake-up function disabled. + * | | |1 = GPA group pin wake-up function Enabled. + * |[1] |PRWKEN |Pin Rising Edge Wake-up Enable Bit + * | | |0 = GPA group pin rising edge wake-up function Disabled. + * | | |1 = GPA group pin rising edge wake-up function Enabled. + * |[2] |PFWKEN |Pin Falling Edge Wake-up Enable Bit + * | | |0 = GPA group pin falling edge wake-up function Disabled. + * | | |1 = GPA group pin falling edge wake-up function Enabled. + * |[7:4] |WKPSEL |GPA Standby Power-down Wake-up Pin Select + * | | |0000 = GPA.0 wake-up function enabled. + * | | |0001 = GPA.1 wake-up function enabled. + * | | |0010 = GPA.2 wake-up function enabled. + * | | |0011 = GPA.3 wake-up function enabled. + * | | |0100 = GPA.4 wake-up function enabled. + * | | |0101 = GPA.5 wake-up function enabled. + * | | |0110 = GPA.6 wake-up function enabled. + * | | |0111 = GPA.7 wake-up function enabled. + * | | |1000 = GPA.8 wake-up function enabled. + * | | |1001 = GPA.9 wake-up function enabled. + * | | |1010 = GPA.10 wake-up function enabled. + * | | |1011 = GPA.11 wake-up function enabled. + * | | |1100 = GPA.12 wake-up function enabled. + * | | |1101 = GPA.13 wake-up function enabled. + * | | |1110 = GPA.14 wake-up function enabled. + * | | |1111 = GPA.15 wake-up function enabled. + * |[8] |DBEN |GPA Input Signal De-bounce Enable Bit + * | | |The DBEN bit is used to enable the de-bounce function for each corresponding IO. + * | | |If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the wakeup. + * | | |The de-bounce clock source is the 32 kHz internal low speed RC oscillator (LIRC). + * | | |0 = Standby power-down wake-up pin De-bounce function Disable. + * | | |1 = Standby power-down wake-up pin De-bounce function Enable. + * | | |The de-bounce function is valid only for edge triggered. + * @var CLK_T::PBSWKCTL + * Offset: 0xA4 GPB Standby Power-down Wake-up Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |WKEN |Standby Power-down Pin Wake-up Enable Bit + * | | |0 = GPB group pin wake-up function Disabled. + * | | |1 = GPB group pin wake-up function Enabled. + * |[1] |PRWKEN |Pin Rising Edge Wake-up Enable Bit + * | | |0 = GPB group pin rising edge wake-up function Disabled. + * | | |1 = GPB group pin rising edge wake-up function Enabled. + * |[2] |PFWKEN |Pin Falling Edge Wake-up Enable Bit + * | | |0 = GPB group pin falling edge wake-up function Disabled. + * | | |1 = GPB group pin falling edge wake-up function Enabled. + * |[7:4] |WKPSEL |GPB Standby Power-down Wake-up Pin Select + * | | |0000 = GPB.0 wake-up function enabled. + * | | |0001 = GPB.1 wake-up function enabled. + * | | |0010 = GPB.2 wake-up function enabled. + * | | |0011 = GPB.3 wake-up function enabled. + * | | |0100 = GPB.4 wake-up function enabled. + * | | |0101 = GPB.5 wake-up function enabled. + * | | |0110 = GPB.6 wake-up function enabled. + * | | |0111 = GPB.7 wake-up function enabled. + * | | |1000 = GPB.8 wake-up function enabled. + * | | |1001 = GPB.9 wake-up function enabled. + * | | |1010 = GPB.10 wake-up function enabled. + * | | |1011 = GPB.11 wake-up function enabled. + * | | |1100 = GPB.12 wake-up function enabled. + * | | |1101 = GPB.13 wake-up function enabled. + * | | |1110 = GPB.14 wake-up function enabled. + * | | |1111 = GPB.15 wake-up function enabled. + * |[8] |DBEN |GPB Input Signal De-bounce Enable Bit + * | | |The DBEN bit is used to enable the de-bounce function for each corresponding IO. + * | | |If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the wakeup. + * | | |The de-bounce clock source is the 32 kHz internal low speed RC oscillator (LIRC). + * | | |0 = Standby power-down wake-up pin De-bounce function Disable. + * | | |1 = Standby power-down wake-up pin De-bounce function Enable. + * | | |The de-bounce function is valid only for edge triggered. + * @var CLK_T::PCSWKCTL + * Offset: 0xA8 GPC Standby Power-down Wake-up Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |WKEN |Standby Power-down Pin Wake-up Enable Bit + * | | |0 = GPC group pin wake-up function Disabled. + * | | |1 = GPC group pin wake-up function Enabled. + * |[1] |PRWKEN |Pin Rising Edge Wake-up Enable Bit + * | | |0 = GPC group pin rising edge wake-up function Disabled. + * | | |1 = GPC group pin rising edge wake-up function Enabled. + * |[2] |PFWKEN |Pin Falling Edge Wake-up Enable Bit + * | | |0 = GPC group pin falling edge wake-up function Disabled. + * | | |1 = GPC group pin falling edge wake-up function Enabled. + * |[7:4] |WKPSEL |GPC Standby Power-down Wake-up Pin Select + * | | |0000 = GPC.0 wake-up function enabled. + * | | |0001 = GPC.1 wake-up function enabled. + * | | |0010 = GPC.2 wake-up function enabled. + * | | |0011 = GPC.3 wake-up function enabled. + * | | |0100 = GPC.4 wake-up function enabled. + * | | |0101 = GPC.5 wake-up function enabled. + * | | |0110 = GPC.6 wake-up function enabled. + * | | |0111 = GPC.7 wake-up function enabled. + * | | |1000 = GPC.8 wake-up function enabled. + * | | |1001 = GPC.9 wake-up function enabled. + * | | |1010 = GPC.10 wake-up function enabled. + * | | |1011 = GPC.11 wake-up function enabled. + * | | |1100 = GPC.12 wake-up function enabled. + * | | |1101 = GPC.13 wake-up function enabled. + * | | |1110 = Reserved. + * | | |1111 = Reserved. + * |[8] |DBEN |GPC Input Signal De-bounce Enable Bit + * | | |The DBEN bit is used to enable the de-bounce function for each corresponding IO. + * | | |If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the wakeup. + * | | |The de-bounce clock source is the 10 kHz internal low speed RC oscillator (LIRC). + * | | |0 = Standby power-down wake-up pin De-bounce function Disable. + * | | |1 = Standby power-down wake-up pin De-bounce function Enable. + * | | |The de-bounce function is valid only for edge triggered. + * @var CLK_T::PDSWKCTL + * Offset: 0xAC GPD Standby Power-down Wake-up Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |WKEN |Standby Power-down Pin Wake-up Enable Bit + * | | |0 = GPD group pin wake-up function Disabled. + * | | |1 = GPD group pin wake-up function Enabled. + * |[1] |PRWKEN |Pin Rising Edge Wake-up Enable Bit + * | | |0 = GPD group pin rising edge wake-up function Disabled. + * | | |1 = GPD group pin rising edge wake-up function Enabled. + * |[2] |PFWKEN |Pin Falling Edge Wake-up Enable Bit + * | | |0 = GPD group pin falling edge wake-up function Disabled. + * | | |1 = GPD group pin falling edge wake-up function Enabled. + * |[7:4] |WKPSEL |GPD Standby Power-down Wake-up Pin Select + * | | |0000 = GPD.0 wake-up function enabled. + * | | |0001 = GPD.1 wake-up function enabled. + * | | |0010 = GPD.2 wake-up function enabled. + * | | |0011 = GPD.3 wake-up function enabled. + * | | |0100 = GPD.4 wake-up function enabled. + * | | |0101 = GPD.5 wake-up function enabled. + * | | |0110 = GPD.6 wake-up function enabled. + * | | |0111 = GPD.7 wake-up function enabled. + * | | |1000 = GPD.8 wake-up function enabled. + * | | |1001 = GPD.9 wake-up function enabled. + * | | |1010 = GPD.10 wake-up function enabled. + * | | |1011 = GPD.11 wake-up function enabled. + * | | |1100 = GPD.12 wake-up function enabled. + * | | |1101 = Reserved. + * | | |1110 = GPD.14 wake-up function enabled. + * | | |1111 = Reserved. + * |[8] |DBEN |GPD Input Signal De-bounce Enable Bit + * | | |The DBEN bit is used to enable the de-bounce function for each corresponding IO. + * | | |If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the wakeup. + * | | |The de-bounce clock source is the 32 kHz internal low speed RC oscillator (LIRC). + * | | |0 = Standby power-down wake-up pin De-bounce function Disable. + * | | |1 = Standby power-down wake-up pin De-bounce function Enable. + * | | |The de-bounce function is valid only for edge triggered. + * @var CLK_T::IOPDCTL + * Offset: 0xB0 GPIO Standby Power-down Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |IOHR |GPIO Hold Release + * | | |When GPIO enter standby power-down mode, all I/O status are hold to keep normal operating status. + * | | |After chip was waked up from standby Power-down mode, the I/O still keeps hold status until user sets this bit to release I/O hold status. + * | | |Note: This bit is auto cleared by hardware. + * @var CLK_T::HXTFSEL + * Offset: 0xB4 HXT Filter Select Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |HXTFSEL |HXT Filter Select + * | | |0 = HXT frequency is > 12MHz. + * | | |1 = HXT frequency is <= 12MHz. + * | | |Note: This bit is auto cleared by hardware. + */ + + + __IO uint32_t PWRCTL; /*!< [0x0000] System Power-down Control Register */ + __IO uint32_t AHBCLK; /*!< [0x0004] AHB Devices Clock Enable Control Register */ + __IO uint32_t APBCLK0; /*!< [0x0008] APB Devices Clock Enable Control Register 0 */ + __IO uint32_t APBCLK1; /*!< [0x000C] APB Devices Clock Enable Control Register 1 */ + __IO uint32_t CLKSEL0; /*!< [0x0010] Clock Source Select Control Register 0 */ + __IO uint32_t CLKSEL1; /*!< [0x0014] Clock Source Select Control Register 1 */ + __IO uint32_t CLKSEL2; /*!< [0x0018] Clock Source Select Control Register 2 */ + __IO uint32_t CLKSEL3; /*!< [0x001C] Clock Source Select Control Register 3 */ + __IO uint32_t CLKDIV0; /*!< [0x0020] Clock Divider Number Register 0 */ + __IO uint32_t CLKDIV1; /*!< [0x0024] Clock Divider Number Register 1 */ + __I uint32_t RESERVE0[2]; + __IO uint32_t CLKDIV4; /*!< [0x0030] Clock Divider Number Register 4 */ + __I uint32_t RESERVE7[1]; + __I uint32_t RESERVE1[2]; + __IO uint32_t PLLCTL; /*!< [0x0040] PLL Control Register */ + __I uint32_t RESERVE2[3]; + __I uint32_t STATUS; /*!< [0x0050] Clock Status Monitor Register */ + __I uint32_t RESERVE3[3]; + __IO uint32_t CLKOCTL; /*!< [0x0060] Clock Output Control Register */ + __I uint32_t RESERVE4[3]; + __IO uint32_t CLKDCTL; /*!< [0x0070] Clock Fail Detector Control Register */ + __IO uint32_t CLKDSTS; /*!< [0x0074] Clock Fail Detector Status Register */ + __IO uint32_t CDUPB; /*!< [0x0078] Clock Frequency Detector Upper Boundary Register */ + __IO uint32_t CDLOWB; /*!< [0x007C] Clock Frequency Detector Low Boundary Register */ + __I uint32_t RESERVE5[4]; + __IO uint32_t PMUCTL; /*!< [0x0090] Power Manager Control Register */ + __IO uint32_t PMUSTS; /*!< [0x0094] Power Manager Status Register */ + __I uint32_t RESERVE6[1]; + __IO uint32_t SWKDBCTL; /*!< [0x009C] Standby Power-down Wake-up De-bounce Control Register */ + __IO uint32_t PASWKCTL; /*!< [0x00A0] GPA Standby Power-down Wake-up Control Register */ + __IO uint32_t PBSWKCTL; /*!< [0x00A4] GPB Standby Power-down Wake-up Control Register */ + __IO uint32_t PCSWKCTL; /*!< [0x00A8] GPC Standby Power-down Wake-up Control Register */ + __IO uint32_t PDSWKCTL; /*!< [0x00AC] GPD Standby Power-down Wake-up Control Register */ + __IO uint32_t IOPDCTL; /*!< [0x00B0] GPIO Standby Power-down Control Register */ + __IO uint32_t HXTFSEL; /*!< [0x00B4] HXT Filter Select Control Register */ + +} CLK_T; + +/** + @addtogroup CLK_CONST CLK Bit Field Definition + Constant Definitions for CLK Controller + @{ +*/ + +#define CLK_PWRCTL_HXTEN_Pos (0) /*!< CLK_T::PWRCTL: HXTEN Position */ +#define CLK_PWRCTL_HXTEN_Msk (0x1ul << CLK_PWRCTL_HXTEN_Pos) /*!< CLK_T::PWRCTL: HXTEN Mask */ + +#define CLK_PWRCTL_LXTEN_Pos (1) /*!< CLK_T::PWRCTL: LXTEN Position */ +#define CLK_PWRCTL_LXTEN_Msk (0x1ul << CLK_PWRCTL_LXTEN_Pos) /*!< CLK_T::PWRCTL: LXTEN Mask */ + +#define CLK_PWRCTL_HIRCEN_Pos (2) /*!< CLK_T::PWRCTL: HIRCEN Position */ +#define CLK_PWRCTL_HIRCEN_Msk (0x1ul << CLK_PWRCTL_HIRCEN_Pos) /*!< CLK_T::PWRCTL: HIRCEN Mask */ + +#define CLK_PWRCTL_LIRCEN_Pos (3) /*!< CLK_T::PWRCTL: LIRCEN Position */ +#define CLK_PWRCTL_LIRCEN_Msk (0x1ul << CLK_PWRCTL_LIRCEN_Pos) /*!< CLK_T::PWRCTL: LIRCEN Mask */ + +#define CLK_PWRCTL_PDWKIEN_Pos (5) /*!< CLK_T::PWRCTL: PDWKIEN Position */ +#define CLK_PWRCTL_PDWKIEN_Msk (0x1ul << CLK_PWRCTL_PDWKIEN_Pos) /*!< CLK_T::PWRCTL: PDWKIEN Mask */ + +#define CLK_PWRCTL_PDWKIF_Pos (6) /*!< CLK_T::PWRCTL: PDWKIF Position */ +#define CLK_PWRCTL_PDWKIF_Msk (0x1ul << CLK_PWRCTL_PDWKIF_Pos) /*!< CLK_T::PWRCTL: PDWKIF Mask */ + +#define CLK_PWRCTL_PDEN_Pos (7) /*!< CLK_T::PWRCTL: PDEN Position */ +#define CLK_PWRCTL_PDEN_Msk (0x1ul << CLK_PWRCTL_PDEN_Pos) /*!< CLK_T::PWRCTL: PDEN Mask */ + +#define CLK_PWRCTL_HXTGAIN_Pos (10) /*!< CLK_T::PWRCTL: HXTGAIN Position */ +#define CLK_PWRCTL_HXTGAIN_Msk (0x3ul << CLK_PWRCTL_HXTGAIN_Pos) /*!< CLK_T::PWRCTL: HXTGAIN Mask */ + +#define CLK_PWRCTL_HXTSELTYP_Pos (12) /*!< CLK_T::PWRCTL: HXTSELTYP Position */ +#define CLK_PWRCTL_HXTSELTYP_Msk (0x1ul << CLK_PWRCTL_HXTSELTYP_Pos) /*!< CLK_T::PWRCTL: HXTSELTYP Mask */ + +#define CLK_PWRCTL_HXTTBEN_Pos (13) /*!< CLK_T::PWRCTL: HXTTBEN Position */ +#define CLK_PWRCTL_HXTTBEN_Msk (0x1ul << CLK_PWRCTL_HXTTBEN_Pos) /*!< CLK_T::PWRCTL: HXTTBEN Mask */ + +#define CLK_PWRCTL_HIRC48EN_Pos (18) /*!< CLK_T::PWRCTL: HIRC48EN Position */ +#define CLK_PWRCTL_HIRC48EN_Msk (0x1ul << CLK_PWRCTL_HIRC48EN_Pos) /*!< CLK_T::PWRCTL: HIRC48EN Mask */ + +#define CLK_PWRCTL_MIRC1P2MEN_Pos (20) /*!< CLK_T::PWRCTL: MIRC1P2MEN Position */ +#define CLK_PWRCTL_MIRC1P2MEN_Msk (0x1ul << CLK_PWRCTL_MIRC1P2MEN_Pos) /*!< CLK_T::PWRCTL: MIRC1P2MEN Mask */ + +#define CLK_PWRCTL_MIRCEN_Pos (21) /*!< CLK_T::PWRCTL: MIRCEN Position */ +#define CLK_PWRCTL_MIRCEN_Msk (0x1ul << CLK_PWRCTL_MIRCEN_Pos) /*!< CLK_T::PWRCTL: MIRCEN Mask */ + +#define CLK_AHBCLK_PDMA0CKEN_Pos (0) /*!< CLK_T::AHBCLK: PDMA0CKEN Position */ +#define CLK_AHBCLK_PDMA0CKEN_Msk (0x1ul << CLK_AHBCLK_PDMA0CKEN_Pos) /*!< CLK_T::AHBCLK: PDMA0CKEN Mask */ + +#define CLK_AHBCLK_PDMA1CKEN_Pos (1) /*!< CLK_T::AHBCLK: PDMA1CKEN Position */ +#define CLK_AHBCLK_PDMA1CKEN_Msk (0x1ul << CLK_AHBCLK_PDMA1CKEN_Pos) /*!< CLK_T::AHBCLK: PDMA1CKEN Mask */ + +#define CLK_AHBCLK_ISPCKEN_Pos (2) /*!< CLK_T::AHBCLK: ISPCKEN Position */ +#define CLK_AHBCLK_ISPCKEN_Msk (0x1ul << CLK_AHBCLK_ISPCKEN_Pos) /*!< CLK_T::AHBCLK: ISPCKEN Mask */ + +#define CLK_AHBCLK_EBICKEN_Pos (3) /*!< CLK_T::AHBCLK: EBICKEN Position */ +#define CLK_AHBCLK_EBICKEN_Msk (0x1ul << CLK_AHBCLK_EBICKEN_Pos) /*!< CLK_T::AHBCLK: EBICKEN Mask */ + +#define CLK_AHBCLK_EXSTCKEN_Pos (4) /*!< CLK_T::AHBCLK: EXSTCKEN Position */ +#define CLK_AHBCLK_EXSTCKEN_Msk (0x1ul << CLK_AHBCLK_EXSTCKEN_Pos) /*!< CLK_T::AHBCLK: EXSTCKEN Mask */ + +#define CLK_AHBCLK_SDH0CKEN_Pos (6) /*!< CLK_T::AHBCLK: SDH0CKEN Position */ +#define CLK_AHBCLK_SDH0CKEN_Msk (0x1ul << CLK_AHBCLK_SDH0CKEN_Pos) /*!< CLK_T::AHBCLK: SDH0CKEN Mask */ + +#define CLK_AHBCLK_CRCCKEN_Pos (7) /*!< CLK_T::AHBCLK: CRCCKEN Position */ +#define CLK_AHBCLK_CRCCKEN_Msk (0x1ul << CLK_AHBCLK_CRCCKEN_Pos) /*!< CLK_T::AHBCLK: CRCCKEN Mask */ + +#define CLK_AHBCLK_CRPTCKEN_Pos (12) /*!< CLK_T::AHBCLK: CRPTCKEN Position */ +#define CLK_AHBCLK_CRPTCKEN_Msk (0x1ul << CLK_AHBCLK_CRPTCKEN_Pos) /*!< CLK_T::AHBCLK: CRPTCKEN Mask */ + +#define CLK_AHBCLK_KSCKEN_Pos (13) /*!< CLK_T::AHBCLK: KSCKEN Position */ +#define CLK_AHBCLK_KSCKEN_Msk (0x1ul << CLK_AHBCLK_KSCKEN_Pos) /*!< CLK_T::AHBCLK: KSCKEN Mask */ + +#define CLK_AHBCLK_TRACECKEN_Pos (14) /*!< CLK_T::AHBCLK: TRACECKEN Position */ +#define CLK_AHBCLK_TRACECKEN_Msk (0x1ul << CLK_AHBCLK_TRACECKEN_Pos) /*!< CLK_T::AHBCLK: TRACECKEN Mask */ + +#define CLK_AHBCLK_FMCIDLE_Pos (15) /*!< CLK_T::AHBCLK: FMCIDLE Position */ +#define CLK_AHBCLK_FMCIDLE_Msk (0x1ul << CLK_AHBCLK_FMCIDLE_Pos) /*!< CLK_T::AHBCLK: FMCIDLE Mask */ + +#define CLK_AHBCLK_USBHCKEN_Pos (16) /*!< CLK_T::AHBCLK: USBHCKEN Position */ +#define CLK_AHBCLK_USBHCKEN_Msk (0x1ul << CLK_AHBCLK_USBHCKEN_Pos) /*!< CLK_T::AHBCLK: USBHCKEN Mask */ + +#define CLK_AHBCLK_SRAM0CKEN_Pos (20) /*!< CLK_T::AHBCLK: SRAM0CKEN Position */ +#define CLK_AHBCLK_SRAM0CKEN_Msk (0x1ul << CLK_AHBCLK_SRAM0CKEN_Pos) /*!< CLK_T::AHBCLK: SRAM0CKEN Mask */ + +#define CLK_AHBCLK_SRAM1CKEN_Pos (21) /*!< CLK_T::AHBCLK: SRAM1CKEN Position */ +#define CLK_AHBCLK_SRAM1CKEN_Msk (0x1ul << CLK_AHBCLK_SRAM1CKEN_Pos) /*!< CLK_T::AHBCLK: SRAM1CKEN Mask */ + +#define CLK_AHBCLK_SRAM2CKEN_Pos (22) /*!< CLK_T::AHBCLK: SRAM2CKEN Position */ +#define CLK_AHBCLK_SRAM2CKEN_Msk (0x1ul << CLK_AHBCLK_SRAM2CKEN_Pos) /*!< CLK_T::AHBCLK: SRAM2CKEN Mask */ + +#define CLK_AHBCLK_GPACKEN_Pos (24) /*!< CLK_T::AHBCLK: GPACKEN Position */ +#define CLK_AHBCLK_GPACKEN_Msk (0x1ul << CLK_AHBCLK_GPACKEN_Pos) /*!< CLK_T::AHBCLK: GPACKEN Mask */ + +#define CLK_AHBCLK_GPBCKEN_Pos (25) /*!< CLK_T::AHBCLK: GPBCKEN Position */ +#define CLK_AHBCLK_GPBCKEN_Msk (0x1ul << CLK_AHBCLK_GPBCKEN_Pos) /*!< CLK_T::AHBCLK: GPBCKEN Mask */ + +#define CLK_AHBCLK_GPCCKEN_Pos (26) /*!< CLK_T::AHBCLK: GPCCKEN Position */ +#define CLK_AHBCLK_GPCCKEN_Msk (0x1ul << CLK_AHBCLK_GPCCKEN_Pos) /*!< CLK_T::AHBCLK: GPCCKEN Mask */ + +#define CLK_AHBCLK_GPDCKEN_Pos (27) /*!< CLK_T::AHBCLK: GPDCKEN Position */ +#define CLK_AHBCLK_GPDCKEN_Msk (0x1ul << CLK_AHBCLK_GPDCKEN_Pos) /*!< CLK_T::AHBCLK: GPDCKEN Mask */ + +#define CLK_AHBCLK_GPECKEN_Pos (28) /*!< CLK_T::AHBCLK: GPECKEN Position */ +#define CLK_AHBCLK_GPECKEN_Msk (0x1ul << CLK_AHBCLK_GPECKEN_Pos) /*!< CLK_T::AHBCLK: GPECKEN Mask */ + +#define CLK_AHBCLK_GPFCKEN_Pos (29) /*!< CLK_T::AHBCLK: GPFCKEN Position */ +#define CLK_AHBCLK_GPFCKEN_Msk (0x1ul << CLK_AHBCLK_GPFCKEN_Pos) /*!< CLK_T::AHBCLK: GPFCKEN Mask */ + +#define CLK_AHBCLK_GPGCKEN_Pos (30) /*!< CLK_T::AHBCLK: GPGCKEN Position */ +#define CLK_AHBCLK_GPGCKEN_Msk (0x1ul << CLK_AHBCLK_GPGCKEN_Pos) /*!< CLK_T::AHBCLK: GPGCKEN Mask */ + +#define CLK_AHBCLK_GPHCKEN_Pos (31) /*!< CLK_T::AHBCLK: GPHCKEN Position */ +#define CLK_AHBCLK_GPHCKEN_Msk (0x1ul << CLK_AHBCLK_GPHCKEN_Pos) /*!< CLK_T::AHBCLK: GPHCKEN Mask */ + +#define CLK_APBCLK0_WDTCKEN_Pos (0) /*!< CLK_T::APBCLK0: WDTCKEN Position */ +#define CLK_APBCLK0_WDTCKEN_Msk (0x1ul << CLK_APBCLK0_WDTCKEN_Pos) /*!< CLK_T::APBCLK0: WDTCKEN Mask */ + +#define CLK_APBCLK0_RTCCKEN_Pos (1) /*!< CLK_T::APBCLK0: RTCCKEN Position */ +#define CLK_APBCLK0_RTCCKEN_Msk (0x1ul << CLK_APBCLK0_RTCCKEN_Pos) /*!< CLK_T::APBCLK0: RTCCKEN Mask */ + +#define CLK_APBCLK0_TMR0CKEN_Pos (2) /*!< CLK_T::APBCLK0: TMR0CKEN Position */ +#define CLK_APBCLK0_TMR0CKEN_Msk (0x1ul << CLK_APBCLK0_TMR0CKEN_Pos) /*!< CLK_T::APBCLK0: TMR0CKEN Mask */ + +#define CLK_APBCLK0_TMR1CKEN_Pos (3) /*!< CLK_T::APBCLK0: TMR1CKEN Position */ +#define CLK_APBCLK0_TMR1CKEN_Msk (0x1ul << CLK_APBCLK0_TMR1CKEN_Pos) /*!< CLK_T::APBCLK0: TMR1CKEN Mask */ + +#define CLK_APBCLK0_TMR2CKEN_Pos (4) /*!< CLK_T::APBCLK0: TMR2CKEN Position */ +#define CLK_APBCLK0_TMR2CKEN_Msk (0x1ul << CLK_APBCLK0_TMR2CKEN_Pos) /*!< CLK_T::APBCLK0: TMR2CKEN Mask */ + +#define CLK_APBCLK0_TMR3CKEN_Pos (5) /*!< CLK_T::APBCLK0: TMR3CKEN Position */ +#define CLK_APBCLK0_TMR3CKEN_Msk (0x1ul << CLK_APBCLK0_TMR3CKEN_Pos) /*!< CLK_T::APBCLK0: TMR3CKEN Mask */ + +#define CLK_APBCLK0_CLKOCKEN_Pos (6) /*!< CLK_T::APBCLK0: CLKOCKEN Position */ +#define CLK_APBCLK0_CLKOCKEN_Msk (0x1ul << CLK_APBCLK0_CLKOCKEN_Pos) /*!< CLK_T::APBCLK0: CLKOCKEN Mask */ + +#define CLK_APBCLK0_ACMP01CKEN_Pos (7) /*!< CLK_T::APBCLK0: ACMP01CKEN Position */ +#define CLK_APBCLK0_ACMP01CKEN_Msk (0x1ul << CLK_APBCLK0_ACMP01CKEN_Pos) /*!< CLK_T::APBCLK0: ACMP01CKEN Mask */ + +#define CLK_APBCLK0_I2C0CKEN_Pos (8) /*!< CLK_T::APBCLK0: I2C0CKEN Position */ +#define CLK_APBCLK0_I2C0CKEN_Msk (0x1ul << CLK_APBCLK0_I2C0CKEN_Pos) /*!< CLK_T::APBCLK0: I2C0CKEN Mask */ + +#define CLK_APBCLK0_I2C1CKEN_Pos (9) /*!< CLK_T::APBCLK0: I2C1CKEN Position */ +#define CLK_APBCLK0_I2C1CKEN_Msk (0x1ul << CLK_APBCLK0_I2C1CKEN_Pos) /*!< CLK_T::APBCLK0: I2C1CKEN Mask */ + +#define CLK_APBCLK0_I2C2CKEN_Pos (10) /*!< CLK_T::APBCLK0: I2C2CKEN Position */ +#define CLK_APBCLK0_I2C2CKEN_Msk (0x1ul << CLK_APBCLK0_I2C2CKEN_Pos) /*!< CLK_T::APBCLK0: I2C2CKEN Mask */ + +#define CLK_APBCLK0_QSPI0CKEN_Pos (12) /*!< CLK_T::APBCLK0: QSPI0CKEN Position */ +#define CLK_APBCLK0_QSPI0CKEN_Msk (0x1ul << CLK_APBCLK0_QSPI0CKEN_Pos) /*!< CLK_T::APBCLK0: QSPI0CKEN Mask */ + +#define CLK_APBCLK0_SPI0CKEN_Pos (13) /*!< CLK_T::APBCLK0: SPI0CKEN Position */ +#define CLK_APBCLK0_SPI0CKEN_Msk (0x1ul << CLK_APBCLK0_SPI0CKEN_Pos) /*!< CLK_T::APBCLK0: SPI0CKEN Mask */ + +#define CLK_APBCLK0_SPI1CKEN_Pos (14) /*!< CLK_T::APBCLK0: SPI1CKEN Position */ +#define CLK_APBCLK0_SPI1CKEN_Msk (0x1ul << CLK_APBCLK0_SPI1CKEN_Pos) /*!< CLK_T::APBCLK0: SPI1CKEN Mask */ + +#define CLK_APBCLK0_SPI2CKEN_Pos (15) /*!< CLK_T::APBCLK0: SPI2CKEN Position */ +#define CLK_APBCLK0_SPI2CKEN_Msk (0x1ul << CLK_APBCLK0_SPI2CKEN_Pos) /*!< CLK_T::APBCLK0: SPI2CKEN Mask */ + +#define CLK_APBCLK0_UART0CKEN_Pos (16) /*!< CLK_T::APBCLK0: UART0CKEN Position */ +#define CLK_APBCLK0_UART0CKEN_Msk (0x1ul << CLK_APBCLK0_UART0CKEN_Pos) /*!< CLK_T::APBCLK0: UART0CKEN Mask */ + +#define CLK_APBCLK0_UART1CKEN_Pos (17) /*!< CLK_T::APBCLK0: UART1CKEN Position */ +#define CLK_APBCLK0_UART1CKEN_Msk (0x1ul << CLK_APBCLK0_UART1CKEN_Pos) /*!< CLK_T::APBCLK0: UART1CKEN Mask */ + +#define CLK_APBCLK0_UART2CKEN_Pos (18) /*!< CLK_T::APBCLK0: UART2CKEN Position */ +#define CLK_APBCLK0_UART2CKEN_Msk (0x1ul << CLK_APBCLK0_UART2CKEN_Pos) /*!< CLK_T::APBCLK0: UART2CKEN Mask */ + +#define CLK_APBCLK0_UART3CKEN_Pos (19) /*!< CLK_T::APBCLK0: UART3CKEN Position */ +#define CLK_APBCLK0_UART3CKEN_Msk (0x1ul << CLK_APBCLK0_UART3CKEN_Pos) /*!< CLK_T::APBCLK0: UART3CKEN Mask */ + +#define CLK_APBCLK0_UART4CKEN_Pos (20) /*!< CLK_T::APBCLK0: UART4CKEN Position */ +#define CLK_APBCLK0_UART4CKEN_Msk (0x1ul << CLK_APBCLK0_UART4CKEN_Pos) /*!< CLK_T::APBCLK0: UART4CKEN Mask */ + +#define CLK_APBCLK0_UART5CKEN_Pos (21) /*!< CLK_T::APBCLK0: UART5CKEN Position */ +#define CLK_APBCLK0_UART5CKEN_Msk (0x1ul << CLK_APBCLK0_UART5CKEN_Pos) /*!< CLK_T::APBCLK0: UART5CKEN Mask */ + +#define CLK_APBCLK0_TAMPERCKEN_Pos (22) /*!< CLK_T::APBCLK0: TAMPERCKEN Position */ +#define CLK_APBCLK0_TAMPERCKEN_Msk (0x1ul << CLK_APBCLK0_TAMPERCKEN_Pos) /*!< CLK_T::APBCLK0: TAMPERCKEN Mask */ + +#define CLK_APBCLK0_CAN0CKEN_Pos (24) /*!< CLK_T::APBCLK0: CAN0CKEN Position */ +#define CLK_APBCLK0_CAN0CKEN_Msk (0x1ul << CLK_APBCLK0_CAN0CKEN_Pos) /*!< CLK_T::APBCLK0: CAN0CKEN Mask */ + +#define CLK_APBCLK0_OTGCKEN_Pos (26) /*!< CLK_T::APBCLK0: OTGCKEN Position */ +#define CLK_APBCLK0_OTGCKEN_Msk (0x1ul << CLK_APBCLK0_OTGCKEN_Pos) /*!< CLK_T::APBCLK0: OTGCKEN Mask */ + +#define CLK_APBCLK0_USBDCKEN_Pos (27) /*!< CLK_T::APBCLK0: USBDCKEN Position */ +#define CLK_APBCLK0_USBDCKEN_Msk (0x1ul << CLK_APBCLK0_USBDCKEN_Pos) /*!< CLK_T::APBCLK0: USBDCKEN Mask */ + +#define CLK_APBCLK0_USBDCKEN_Pos (27) /*!< CLK_T::APBCLK0: USBDCKEN Position */ +#define CLK_APBCLK0_USBDCKEN_Msk (0x1ul << CLK_APBCLK0_USBDCKEN_Pos) /*!< CLK_T::APBCLK0: USBDCKEN Mask */ + +#define CLK_APBCLK0_EADCCKEN_Pos (28) /*!< CLK_T::APBCLK0: EADCCKEN Position */ +#define CLK_APBCLK0_EADCCKEN_Msk (0x1ul << CLK_APBCLK0_EADCCKEN_Pos) /*!< CLK_T::APBCLK0: EADCCKEN Mask */ + +#define CLK_APBCLK0_I2S0CKEN_Pos (29) /*!< CLK_T::APBCLK0: I2S0CKEN Position */ +#define CLK_APBCLK0_I2S0CKEN_Msk (0x1ul << CLK_APBCLK0_I2S0CKEN_Pos) /*!< CLK_T::APBCLK0: I2S0CKEN Mask */ + +#define CLK_APBCLK0_EWDTCKEN_Pos (31) /*!< CLK_T::APBCLK0: EWDTCKEN Position */ +#define CLK_APBCLK0_EWDTCKEN_Msk (0x1ul << CLK_APBCLK0_EWDTCKEN_Pos) /*!< CLK_T::APBCLK0: EWDTCKEN Mask */ + +#define CLK_APBCLK1_SC0CKEN_Pos (0) /*!< CLK_T::APBCLK1: SC0CKEN Position */ +#define CLK_APBCLK1_SC0CKEN_Msk (0x1ul << CLK_APBCLK1_SC0CKEN_Pos) /*!< CLK_T::APBCLK1: SC0CKEN Mask */ + +#define CLK_APBCLK1_SC1CKEN_Pos (1) /*!< CLK_T::APBCLK1: SC1CKEN Position */ +#define CLK_APBCLK1_SC1CKEN_Msk (0x1ul << CLK_APBCLK1_SC1CKEN_Pos) /*!< CLK_T::APBCLK1: SC1CKEN Mask */ + +#define CLK_APBCLK1_SC2CKEN_Pos (2) /*!< CLK_T::APBCLK1: SC2CKEN Position */ +#define CLK_APBCLK1_SC2CKEN_Msk (0x1ul << CLK_APBCLK1_SC2CKEN_Pos) /*!< CLK_T::APBCLK1: SC2CKEN Mask */ + +#define CLK_APBCLK1_TMR4CKEN_Pos (4) /*!< CLK_T::APBCLK1: TMR4CKEN Position */ +#define CLK_APBCLK1_TMR4CKEN_Msk (0x1ul << CLK_APBCLK1_TMR4CKEN_Pos) /*!< CLK_T::APBCLK1: TMR4CKEN Mask */ + +#define CLK_APBCLK1_TMR5CKEN_Pos (5) /*!< CLK_T::APBCLK1: TMR5CKEN Position */ +#define CLK_APBCLK1_TMR5CKEN_Msk (0x1ul << CLK_APBCLK1_TMR5CKEN_Pos) /*!< CLK_T::APBCLK1: TMR5CKEN Mask */ + +#define CLK_APBCLK1_SPI3CKEN_Pos (6) /*!< CLK_T::APBCLK1: SPI3CKEN Position */ +#define CLK_APBCLK1_SPI3CKEN_Msk (0x1ul << CLK_APBCLK1_SPI3CKEN_Pos) /*!< CLK_T::APBCLK1: SPI3CKEN Mask */ + +#define CLK_APBCLK1_USCI0CKEN_Pos (8) /*!< CLK_T::APBCLK1: USCI0CKEN Position */ +#define CLK_APBCLK1_USCI0CKEN_Msk (0x1ul << CLK_APBCLK1_USCI0CKEN_Pos) /*!< CLK_T::APBCLK1: USCI0CKEN Mask */ + +#define CLK_APBCLK1_USCI1CKEN_Pos (9) /*!< CLK_T::APBCLK1: USCI1CKEN Position */ +#define CLK_APBCLK1_USCI1CKEN_Msk (0x1ul << CLK_APBCLK1_USCI1CKEN_Pos) /*!< CLK_T::APBCLK1: USCI1CKEN Mask */ + +#define CLK_APBCLK1_DACCKEN_Pos (12) /*!< CLK_T::APBCLK1: DACCKEN Position */ +#define CLK_APBCLK1_DACCKEN_Msk (0x1ul << CLK_APBCLK1_DACCKEN_Pos) /*!< CLK_T::APBCLK1: DACCKEN Mask */ + +#define CLK_APBCLK1_EPWM0CKEN_Pos (16) /*!< CLK_T::APBCLK1: EPWM0CKEN Position */ +#define CLK_APBCLK1_EPWM0CKEN_Msk (0x1ul << CLK_APBCLK1_EPWM0CKEN_Pos) /*!< CLK_T::APBCLK1: EPWM0CKEN Mask */ + +#define CLK_APBCLK1_EPWM1CKEN_Pos (17) /*!< CLK_T::APBCLK1: EPWM1CKEN Position */ +#define CLK_APBCLK1_EPWM1CKEN_Msk (0x1ul << CLK_APBCLK1_EPWM1CKEN_Pos) /*!< CLK_T::APBCLK1: EPWM1CKEN Mask */ + +#define CLK_APBCLK1_BPWM0CKEN_Pos (18) /*!< CLK_T::APBCLK1: BPWM0CKEN Position */ +#define CLK_APBCLK1_BPWM0CKEN_Msk (0x1ul << CLK_APBCLK1_BPWM0CKEN_Pos) /*!< CLK_T::APBCLK1: BPWM0CKEN Mask */ + +#define CLK_APBCLK1_BPWM1CKEN_Pos (19) /*!< CLK_T::APBCLK1: BPWM1CKEN Position */ +#define CLK_APBCLK1_BPWM1CKEN_Msk (0x1ul << CLK_APBCLK1_BPWM1CKEN_Pos) /*!< CLK_T::APBCLK1: BPWM1CKEN Mask */ + +#define CLK_APBCLK1_QEI0CKEN_Pos (22) /*!< CLK_T::APBCLK1: QEI0CKEN Position */ +#define CLK_APBCLK1_QEI0CKEN_Msk (0x1ul << CLK_APBCLK1_QEI0CKEN_Pos) /*!< CLK_T::APBCLK1: QEI0CKEN Mask */ + +#define CLK_APBCLK1_QEI1CKEN_Pos (23) /*!< CLK_T::APBCLK1: QEI1CKEN Position */ +#define CLK_APBCLK1_QEI1CKEN_Msk (0x1ul << CLK_APBCLK1_QEI1CKEN_Pos) /*!< CLK_T::APBCLK1: QEI1CKEN Mask */ + +#define CLK_APBCLK1_LCDCKEN_Pos (24) /*!< CLK_T::APBCLK1: LCDCKEN Position */ +#define CLK_APBCLK1_LCDCKEN_Msk (0x1ul << CLK_APBCLK1_LCDCKEN_Pos) /*!< CLK_T::APBCLK1: LCKCKEN Mask */ + +#define CLK_APBCLK1_TRNGCKEN_Pos (25) /*!< CLK_T::APBCLK1: TRNGCKEN Position */ +#define CLK_APBCLK1_TRNGCKEN_Msk (0x1ul << CLK_APBCLK1_TRNGCKEN_Pos) /*!< CLK_T::APBCLK1: TRNGCKEN Mask */ + +#define CLK_APBCLK1_ECAP0CKEN_Pos (26) /*!< CLK_T::APBCLK1: ECAP0CKEN Position */ +#define CLK_APBCLK1_ECAP0CKEN_Msk (0x1ul << CLK_APBCLK1_ECAP0CKEN_Pos) /*!< CLK_T::APBCLK1: ECAP0CKEN Mask */ + +#define CLK_APBCLK1_ECAP1CKEN_Pos (27) /*!< CLK_T::APBCLK1: ECAP1CKEN Position */ +#define CLK_APBCLK1_ECAP1CKEN_Msk (0x1ul << CLK_APBCLK1_ECAP1CKEN_Pos) /*!< CLK_T::APBCLK1: ECAP1CKEN Mask */ + +#define CLK_APBCLK1_LCDCPCKEN_Pos (28) /*!< CLK_T::APBCLK1: LCDCPCKEN Position */ +#define CLK_APBCLK1_LCDCPCKEN_Msk (0x1ul << CLK_APBCLK1_LCDCPCKEN_Pos) /*!< CLK_T::APBCLK1: LCDCPCKEN Mask */ + +#define CLK_CLKSEL0_HCLKSEL_Pos (0) /*!< CLK_T::CLKSEL0: HCLKSEL Position */ +#define CLK_CLKSEL0_HCLKSEL_Msk (0x7ul << CLK_CLKSEL0_HCLKSEL_Pos) /*!< CLK_T::CLKSEL0: HCLKSEL Mask */ + +#define CLK_CLKSEL0_STCLKSEL_Pos (3) /*!< CLK_T::CLKSEL0: STCLKSEL Position */ +#define CLK_CLKSEL0_STCLKSEL_Msk (0x7ul << CLK_CLKSEL0_STCLKSEL_Pos) /*!< CLK_T::CLKSEL0: STCLKSEL Mask */ + +#define CLK_CLKSEL0_USBSEL_Pos (8) /*!< CLK_T::CLKSEL0: USBSEL Position */ +#define CLK_CLKSEL0_USBSEL_Msk (0x1ul << CLK_CLKSEL0_USBSEL_Pos) /*!< CLK_T::CLKSEL0: USBSEL Mask */ + +#define CLK_CLKSEL0_SDH0SEL_Pos (20) /*!< CLK_T::CLKSEL0: SDH0SEL Position */ +#define CLK_CLKSEL0_SDH0SEL_Msk (0x3ul << CLK_CLKSEL0_SDH0SEL_Pos) /*!< CLK_T::CLKSEL0: SDH0SEL Mask */ + +#define CLK_CLKSEL1_WDTSEL_Pos (0) /*!< CLK_T::CLKSEL1: WDTSEL Position */ +#define CLK_CLKSEL1_WDTSEL_Msk (0x3ul << CLK_CLKSEL1_WDTSEL_Pos) /*!< CLK_T::CLKSEL1: WDTSEL Mask */ + +#define CLK_CLKSEL1_LCDSEL_Pos (2) /*!< CLK_T::CLKSEL1: LCDSEL Position */ +#define CLK_CLKSEL1_LCDSEL_Msk (0x1ul << CLK_CLKSEL1_LCDSEL_Pos) /*!< CLK_T::CLKSEL1: LCDSEL Mask */ + +#define CLK_CLKSEL1_LCDCPSEL_Pos (3) /*!< CLK_T::CLKSEL1: LCDCPSEL Position */ +#define CLK_CLKSEL1_LCDCPSEL_Msk (0x1ul << CLK_CLKSEL1_LCDCPSEL_Pos) /*!< CLK_T::CLKSEL1: LCDCPSEL Mask */ + +#define CLK_CLKSEL1_EWDTSEL_Pos (4) /*!< CLK_T::CLKSEL1: EWDTSEL Position */ +#define CLK_CLKSEL1_EWDTSEL_Msk (0x3ul << CLK_CLKSEL1_EWDTSEL_Pos) /*!< CLK_T::CLKSEL1: EWDTSEL Mask */ + +#define CLK_CLKSEL1_EWWDTSEL_Pos (6) /*!< CLK_T::CLKSEL1: EWWDTSEL Position */ +#define CLK_CLKSEL1_EWWDTSEL_Msk (0x3ul << CLK_CLKSEL1_EWWDTSEL_Pos) /*!< CLK_T::CLKSEL1: EWWDTSEL Mask */ + +#define CLK_CLKSEL1_TMR0SEL_Pos (8) /*!< CLK_T::CLKSEL1: TMR0SEL Position */ +#define CLK_CLKSEL1_TMR0SEL_Msk (0x7ul << CLK_CLKSEL1_TMR0SEL_Pos) /*!< CLK_T::CLKSEL1: TMR0SEL Mask */ + +#define CLK_CLKSEL1_TMR1SEL_Pos (12) /*!< CLK_T::CLKSEL1: TMR1SEL Position */ +#define CLK_CLKSEL1_TMR1SEL_Msk (0x7ul << CLK_CLKSEL1_TMR1SEL_Pos) /*!< CLK_T::CLKSEL1: TMR1SEL Mask */ + +#define CLK_CLKSEL1_TMR2SEL_Pos (16) /*!< CLK_T::CLKSEL1: TMR2SEL Position */ +#define CLK_CLKSEL1_TMR2SEL_Msk (0x7ul << CLK_CLKSEL1_TMR2SEL_Pos) /*!< CLK_T::CLKSEL1: TMR2SEL Mask */ + +#define CLK_CLKSEL1_TMR3SEL_Pos (20) /*!< CLK_T::CLKSEL1: TMR3SEL Position */ +#define CLK_CLKSEL1_TMR3SEL_Msk (0x7ul << CLK_CLKSEL1_TMR3SEL_Pos) /*!< CLK_T::CLKSEL1: TMR3SEL Mask */ + +#define CLK_CLKSEL1_CLKOSEL_Pos (28) /*!< CLK_T::CLKSEL1: CLKOSEL Position */ +#define CLK_CLKSEL1_CLKOSEL_Msk (0x3ul << CLK_CLKSEL1_CLKOSEL_Pos) /*!< CLK_T::CLKSEL1: CLKOSEL Mask */ + +#define CLK_CLKSEL1_WWDTSEL_Pos (30) /*!< CLK_T::CLKSEL1: WWDTSEL Position */ +#define CLK_CLKSEL1_WWDTSEL_Msk (0x3ul << CLK_CLKSEL1_WWDTSEL_Pos) /*!< CLK_T::CLKSEL1: WWDTSEL Mask */ + +#define CLK_CLKSEL2_EPWM0SEL_Pos (0) /*!< CLK_T::CLKSEL2: EPWM0SEL Position */ +#define CLK_CLKSEL2_EPWM0SEL_Msk (0x1ul << CLK_CLKSEL2_EPWM0SEL_Pos) /*!< CLK_T::CLKSEL2: EPWM0SEL Mask */ + +#define CLK_CLKSEL2_EPWM1SEL_Pos (1) /*!< CLK_T::CLKSEL2: EPWM1SEL Position */ +#define CLK_CLKSEL2_EPWM1SEL_Msk (0x1ul << CLK_CLKSEL2_EPWM1SEL_Pos) /*!< CLK_T::CLKSEL2: EPWM1SEL Mask */ + +#define CLK_CLKSEL2_QSPI0SEL_Pos (2) /*!< CLK_T::CLKSEL2: QSPI0SEL Position */ +#define CLK_CLKSEL2_QSPI0SEL_Msk (0x3ul << CLK_CLKSEL2_QSPI0SEL_Pos) /*!< CLK_T::CLKSEL2: QSPI0SEL Mask */ + +#define CLK_CLKSEL2_SPI0SEL_Pos (4) /*!< CLK_T::CLKSEL2: SPI0SEL Position */ +#define CLK_CLKSEL2_SPI0SEL_Msk (0x3ul << CLK_CLKSEL2_SPI0SEL_Pos) /*!< CLK_T::CLKSEL2: SPI0SEL Mask */ + +#define CLK_CLKSEL2_SPI1SEL_Pos (6) /*!< CLK_T::CLKSEL2: SPI1SEL Position */ +#define CLK_CLKSEL2_SPI1SEL_Msk (0x3ul << CLK_CLKSEL2_SPI1SEL_Pos) /*!< CLK_T::CLKSEL2: SPI1SEL Mask */ + +#define CLK_CLKSEL2_SPI2SEL_Pos (10) /*!< CLK_T::CLKSEL2: SPI2SEL Position */ +#define CLK_CLKSEL2_SPI2SEL_Msk (0x3ul << CLK_CLKSEL2_SPI2SEL_Pos) /*!< CLK_T::CLKSEL2: SPI2SEL Mask */ + +#define CLK_CLKSEL2_BPWM0SEL_Pos (8) /*!< CLK_T::CLKSEL2: BPWM0SEL Position */ +#define CLK_CLKSEL2_BPWM0SEL_Msk (0x1ul << CLK_CLKSEL2_BPWM0SEL_Pos) /*!< CLK_T::CLKSEL2: BPWM0SEL Mask */ + +#define CLK_CLKSEL2_BPWM1SEL_Pos (9) /*!< CLK_T::CLKSEL2: BPWM1SEL Position */ +#define CLK_CLKSEL2_BPWM1SEL_Msk (0x1ul << CLK_CLKSEL2_BPWM1SEL_Pos) /*!< CLK_T::CLKSEL2: BPWM1SEL Mask */ + +#define CLK_CLKSEL2_SPI3SEL_Pos (12) /*!< CLK_T::CLKSEL2: SPI3SEL Position */ +#define CLK_CLKSEL2_SPI3SEL_Msk (0x3ul << CLK_CLKSEL2_SPI3SEL_Pos) /*!< CLK_T::CLKSEL2: SPI3SEL Mask */ + +#define CLK_CLKSEL2_UART0SEL_Pos (16) /*!< CLK_T::CLKSEL2: UART0SEL Position */ +#define CLK_CLKSEL2_UART0SEL_Msk (0x7ul << CLK_CLKSEL2_UART0SEL_Pos) /*!< CLK_T::CLKSEL2: UART0SEL Mask */ + +#define CLK_CLKSEL2_UART1SEL_Pos (20) /*!< CLK_T::CLKSEL2: UART1SEL Position */ +#define CLK_CLKSEL2_UART1SEL_Msk (0x7ul << CLK_CLKSEL2_UART1SEL_Pos) /*!< CLK_T::CLKSEL2: UART1SEL Mask */ + +#define CLK_CLKSEL2_UART2SEL_Pos (24) /*!< CLK_T::CLKSEL2: UART2SEL Position */ +#define CLK_CLKSEL2_UART2SEL_Msk (0x7ul << CLK_CLKSEL2_UART2SEL_Pos) /*!< CLK_T::CLKSEL2: UART2SEL Mask */ + +#define CLK_CLKSEL2_UART3SEL_Pos (28) /*!< CLK_T::CLKSEL2: UART3SEL Position */ +#define CLK_CLKSEL2_UART3SEL_Msk (0x7ul << CLK_CLKSEL2_UART3SEL_Pos) /*!< CLK_T::CLKSEL2: UART3SEL Mask */ + +#define CLK_CLKSEL3_SC0SEL_Pos (0) /*!< CLK_T::CLKSEL3: SC0SEL Position */ +#define CLK_CLKSEL3_SC0SEL_Msk (0x3ul << CLK_CLKSEL3_SC0SEL_Pos) /*!< CLK_T::CLKSEL3: SC0SEL Mask */ + +#define CLK_CLKSEL3_SC1SEL_Pos (2) /*!< CLK_T::CLKSEL3: SC1SEL Position */ +#define CLK_CLKSEL3_SC1SEL_Msk (0x3ul << CLK_CLKSEL3_SC1SEL_Pos) /*!< CLK_T::CLKSEL3: SC1SEL Mask */ + +#define CLK_CLKSEL3_SC2SEL_Pos (4) /*!< CLK_T::CLKSEL3: SC2SEL Position */ +#define CLK_CLKSEL3_SC2SEL_Msk (0x3ul << CLK_CLKSEL3_SC2SEL_Pos) /*!< CLK_T::CLKSEL3: SC2SEL Mask */ + +#define CLK_CLKSEL3_TMR4SEL_Pos (8) /*!< CLK_T::CLKSEL3: TMR4SEL Position */ +#define CLK_CLKSEL3_TMR4SEL_Msk (0x7ul << CLK_CLKSEL3_TMR4SEL_Pos) /*!< CLK_T::CLKSEL3: TMR4SEL Mask */ + +#define CLK_CLKSEL3_TMR5SEL_Pos (12) /*!< CLK_T::CLKSEL3: TMR5SEL Position */ +#define CLK_CLKSEL3_TMR5SEL_Msk (0x7ul << CLK_CLKSEL3_TMR5SEL_Pos) /*!< CLK_T::CLKSEL3: TMR5SEL Mask */ + +#define CLK_CLKSEL3_I2S0SEL_Pos (16) /*!< CLK_T::CLKSEL3: I2S0SEL Position */ +#define CLK_CLKSEL3_I2S0SEL_Msk (0x3ul << CLK_CLKSEL3_I2S0SEL_Pos) /*!< CLK_T::CLKSEL3: I2S0SEL Mask */ + +#define CLK_CLKSEL3_UART4SEL_Pos (24) /*!< CLK_T::CLKSEL3: UART4SEL Position */ +#define CLK_CLKSEL3_UART4SEL_Msk (0x7ul << CLK_CLKSEL3_UART4SEL_Pos) /*!< CLK_T::CLKSEL3: UART4SEL Mask */ + +#define CLK_CLKSEL3_UART5SEL_Pos (28) /*!< CLK_T::CLKSEL3: UART5SEL Position */ +#define CLK_CLKSEL3_UART5SEL_Msk (0x7ul << CLK_CLKSEL3_UART5SEL_Pos) /*!< CLK_T::CLKSEL3: UART5SEL Mask */ + +#define CLK_CLKDIV0_HCLKDIV_Pos (0) /*!< CLK_T::CLKDIV0: HCLKDIV Position */ +#define CLK_CLKDIV0_HCLKDIV_Msk (0xful << CLK_CLKDIV0_HCLKDIV_Pos) /*!< CLK_T::CLKDIV0: HCLKDIV Mask */ + +#define CLK_CLKDIV0_USBDIV_Pos (4) /*!< CLK_T::CLKDIV0: USBDIV Position */ +#define CLK_CLKDIV0_USBDIV_Msk (0xful << CLK_CLKDIV0_USBDIV_Pos) /*!< CLK_T::CLKDIV0: USBDIV Mask */ + +#define CLK_CLKDIV0_UART0DIV_Pos (8) /*!< CLK_T::CLKDIV0: UART0DIV Position */ +#define CLK_CLKDIV0_UART0DIV_Msk (0xful << CLK_CLKDIV0_UART0DIV_Pos) /*!< CLK_T::CLKDIV0: UART0DIV Mask */ + +#define CLK_CLKDIV0_UART1DIV_Pos (12) /*!< CLK_T::CLKDIV0: UART1DIV Position */ +#define CLK_CLKDIV0_UART1DIV_Msk (0xful << CLK_CLKDIV0_UART1DIV_Pos) /*!< CLK_T::CLKDIV0: UART1DIV Mask */ + +#define CLK_CLKDIV0_EADCDIV_Pos (16) /*!< CLK_T::CLKDIV0: EADCDIV Position */ +#define CLK_CLKDIV0_EADCDIV_Msk (0xfful << CLK_CLKDIV0_EADCDIV_Pos) /*!< CLK_T::CLKDIV0: EADCDIV Mask */ + +#define CLK_CLKDIV0_SDH0DIV_Pos (24) /*!< CLK_T::CLKDIV0: SDH0DIV Position */ +#define CLK_CLKDIV0_SDH0DIV_Msk (0xfful << CLK_CLKDIV0_SDH0DIV_Pos) /*!< CLK_T::CLKDIV0: SDH0DIV Mask */ + +#define CLK_CLKDIV1_SC0DIV_Pos (0) /*!< CLK_T::CLKDIV1: SC0DIV Position */ +#define CLK_CLKDIV1_SC0DIV_Msk (0xfful << CLK_CLKDIV1_SC0DIV_Pos) /*!< CLK_T::CLKDIV1: SC0DIV Mask */ + +#define CLK_CLKDIV1_SC1DIV_Pos (8) /*!< CLK_T::CLKDIV1: SC1DIV Position */ +#define CLK_CLKDIV1_SC1DIV_Msk (0xfful << CLK_CLKDIV1_SC1DIV_Pos) /*!< CLK_T::CLKDIV1: SC1DIV Mask */ + +#define CLK_CLKDIV1_SC2DIV_Pos (16) /*!< CLK_T::CLKDIV1: SC2DIV Position */ +#define CLK_CLKDIV1_SC2DIV_Msk (0xfful << CLK_CLKDIV1_SC2DIV_Pos) /*!< CLK_T::CLKDIV1: SC2DIV Mask */ + +#define CLK_CLKDIV4_UART2DIV_Pos (0) /*!< CLK_T::CLKDIV4: UART2DIV Position */ +#define CLK_CLKDIV4_UART2DIV_Msk (0xful << CLK_CLKDIV4_UART2DIV_Pos) /*!< CLK_T::CLKDIV4: UART2DIV Mask */ + +#define CLK_CLKDIV4_UART3DIV_Pos (4) /*!< CLK_T::CLKDIV4: UART3DIV Position */ +#define CLK_CLKDIV4_UART3DIV_Msk (0xful << CLK_CLKDIV4_UART3DIV_Pos) /*!< CLK_T::CLKDIV4: UART3DIV Mask */ + +#define CLK_CLKDIV4_UART4DIV_Pos (8) /*!< CLK_T::CLKDIV4: UART4DIV Position */ +#define CLK_CLKDIV4_UART4DIV_Msk (0xful << CLK_CLKDIV4_UART4DIV_Pos) /*!< CLK_T::CLKDIV4: UART4DIV Mask */ + +#define CLK_CLKDIV4_UART5DIV_Pos (12) /*!< CLK_T::CLKDIV4: UART5DIV Position */ +#define CLK_CLKDIV4_UART5DIV_Msk (0xful << CLK_CLKDIV4_UART5DIV_Pos) /*!< CLK_T::CLKDIV4: UART5DIV Mask */ + +#define CLK_PLLCTL_FBDIV_Pos (0) /*!< CLK_T::PLLCTL: FBDIV Position */ +#define CLK_PLLCTL_FBDIV_Msk (0x1fful << CLK_PLLCTL_FBDIV_Pos) /*!< CLK_T::PLLCTL: FBDIV Mask */ + +#define CLK_PLLCTL_INDIV_Pos (9) /*!< CLK_T::PLLCTL: INDIV Position */ +#define CLK_PLLCTL_INDIV_Msk (0x1ful << CLK_PLLCTL_INDIV_Pos) /*!< CLK_T::PLLCTL: INDIV Mask */ + +#define CLK_PLLCTL_OUTDIV_Pos (14) /*!< CLK_T::PLLCTL: OUTDIV Position */ +#define CLK_PLLCTL_OUTDIV_Msk (0x3ul << CLK_PLLCTL_OUTDIV_Pos) /*!< CLK_T::PLLCTL: OUTDIV Mask */ + +#define CLK_PLLCTL_PD_Pos (16) /*!< CLK_T::PLLCTL: PD Position */ +#define CLK_PLLCTL_PD_Msk (0x1ul << CLK_PLLCTL_PD_Pos) /*!< CLK_T::PLLCTL: PD Mask */ + +#define CLK_PLLCTL_BP_Pos (17) /*!< CLK_T::PLLCTL: BP Position */ +#define CLK_PLLCTL_BP_Msk (0x1ul << CLK_PLLCTL_BP_Pos) /*!< CLK_T::PLLCTL: BP Mask */ + +#define CLK_PLLCTL_PLLSRC_Pos (19) /*!< CLK_T::PLLCTL: PLLSRC Position */ +#define CLK_PLLCTL_PLLSRC_Msk (0x1ul << CLK_PLLCTL_PLLSRC_Pos) /*!< CLK_T::PLLCTL: PLLSRC Mask */ + +#define CLK_PLLCTL_STBSEL_Pos (23) /*!< CLK_T::PLLCTL: STBSEL Position */ +#define CLK_PLLCTL_STBSEL_Msk (0x1ul << CLK_PLLCTL_STBSEL_Pos) /*!< CLK_T::PLLCTL: STBSEL Mask */ + +#define CLK_STATUS_HXTSTB_Pos (0) /*!< CLK_T::STATUS: HXTSTB Position */ +#define CLK_STATUS_HXTSTB_Msk (0x1ul << CLK_STATUS_HXTSTB_Pos) /*!< CLK_T::STATUS: HXTSTB Mask */ + +#define CLK_STATUS_LXTSTB_Pos (1) /*!< CLK_T::STATUS: LXTSTB Position */ +#define CLK_STATUS_LXTSTB_Msk (0x1ul << CLK_STATUS_LXTSTB_Pos) /*!< CLK_T::STATUS: LXTSTB Mask */ + +#define CLK_STATUS_PLLSTB_Pos (2) /*!< CLK_T::STATUS: PLLSTB Position */ +#define CLK_STATUS_PLLSTB_Msk (0x1ul << CLK_STATUS_PLLSTB_Pos) /*!< CLK_T::STATUS: PLLSTB Mask */ + +#define CLK_STATUS_LIRCSTB_Pos (3) /*!< CLK_T::STATUS: LIRCSTB Position */ +#define CLK_STATUS_LIRCSTB_Msk (0x1ul << CLK_STATUS_LIRCSTB_Pos) /*!< CLK_T::STATUS: LIRCSTB Mask */ + +#define CLK_STATUS_HIRCSTB_Pos (4) /*!< CLK_T::STATUS: HIRCSTB Position */ +#define CLK_STATUS_HIRCSTB_Msk (0x1ul << CLK_STATUS_HIRCSTB_Pos) /*!< CLK_T::STATUS: HIRCSTB Mask */ + +#define CLK_STATUS_MIRCSTB_Pos (5) /*!< CLK_T::STATUS: MIRCSTB Position */ +#define CLK_STATUS_MIRCSTB_Msk (0x1ul << CLK_STATUS_MIRCSTB_Pos) /*!< CLK_T::STATUS: MIRCSTB Mask */ + +#define CLK_STATUS_HIRC48STB_Pos (6) /*!< CLK_T::STATUS: HIRC48STB Position */ +#define CLK_STATUS_HIRC48STB_Msk (0x1ul << CLK_STATUS_HIRC48STB_Pos) /*!< CLK_T::STATUS: HIRC48STB Mask */ + +#define CLK_STATUS_CLKSFAIL_Pos (7) /*!< CLK_T::STATUS: CLKSFAIL Position */ +#define CLK_STATUS_CLKSFAIL_Msk (0x1ul << CLK_STATUS_CLKSFAIL_Pos) /*!< CLK_T::STATUS: CLKSFAIL Mask */ + +#define CLK_STATUS_EXTLXTSTB_Pos (8) /*!< CLK_T::STATUS: EXTLXTSTB Position */ +#define CLK_STATUS_EXTLXTSTB_Msk (0x1ul << CLK_STATUS_EXTLXTSTB_Pos) /*!< CLK_T::STATUS: EXTLXTSTB Mask */ + +#define CLK_STATUS_LIRC32STB_Pos (9) /*!< CLK_T::STATUS: LIRC32STB Position */ +#define CLK_STATUS_LIRC32STB_Msk (0x1ul << CLK_STATUS_LIRC32STB_Pos) /*!< CLK_T::STATUS: LIRC32STB Mask */ + +#define CLK_CLKOCTL_FREQSEL_Pos (0) /*!< CLK_T::CLKOCTL: FREQSEL Position */ +#define CLK_CLKOCTL_FREQSEL_Msk (0xful << CLK_CLKOCTL_FREQSEL_Pos) /*!< CLK_T::CLKOCTL: FREQSEL Mask */ + +#define CLK_CLKOCTL_CLKOEN_Pos (4) /*!< CLK_T::CLKOCTL: CLKOEN Position */ +#define CLK_CLKOCTL_CLKOEN_Msk (0x1ul << CLK_CLKOCTL_CLKOEN_Pos) /*!< CLK_T::CLKOCTL: CLKOEN Mask */ + +#define CLK_CLKOCTL_DIV1EN_Pos (5) /*!< CLK_T::CLKOCTL: DIV1EN Position */ +#define CLK_CLKOCTL_DIV1EN_Msk (0x1ul << CLK_CLKOCTL_DIV1EN_Pos) /*!< CLK_T::CLKOCTL: DIV1EN Mask */ + +#define CLK_CLKOCTL_CLK1HZEN_Pos (6) /*!< CLK_T::CLKOCTL: CLK1HZEN Position */ +#define CLK_CLKOCTL_CLK1HZEN_Msk (0x1ul << CLK_CLKOCTL_CLK1HZEN_Pos) /*!< CLK_T::CLKOCTL: CLK1HZEN Mask */ + +#define CLK_CLKDCTL_HXTFDEN_Pos (4) /*!< CLK_T::CLKDCTL: HXTFDEN Position */ +#define CLK_CLKDCTL_HXTFDEN_Msk (0x1ul << CLK_CLKDCTL_HXTFDEN_Pos) /*!< CLK_T::CLKDCTL: HXTFDEN Mask */ + +#define CLK_CLKDCTL_HXTFIEN_Pos (5) /*!< CLK_T::CLKDCTL: HXTFIEN Position */ +#define CLK_CLKDCTL_HXTFIEN_Msk (0x1ul << CLK_CLKDCTL_HXTFIEN_Pos) /*!< CLK_T::CLKDCTL: HXTFIEN Mask */ + +#define CLK_CLKDCTL_HXTFDSEL_Pos (6) /*!< CLK_T::CLKDCTL: HXTFDSEL Position */ +#define CLK_CLKDCTL_HXTFDSEL_Msk (0x1ul << CLK_CLKDCTL_HXTFDSEL_Pos) /*!< CLK_T::CLKDCTL: HXTFDSEL Mask */ + +#define CLK_CLKDCTL_LXTFDEN_Pos (12) /*!< CLK_T::CLKDCTL: LXTFDEN Position */ +#define CLK_CLKDCTL_LXTFDEN_Msk (0x1ul << CLK_CLKDCTL_LXTFDEN_Pos) /*!< CLK_T::CLKDCTL: LXTFDEN Mask */ + +#define CLK_CLKDCTL_LXTFIEN_Pos (13) /*!< CLK_T::CLKDCTL: LXTFIEN Position */ +#define CLK_CLKDCTL_LXTFIEN_Msk (0x1ul << CLK_CLKDCTL_LXTFIEN_Pos) /*!< CLK_T::CLKDCTL: LXTFIEN Mask */ + +#define CLK_CLKDCTL_HXTFQDEN_Pos (16) /*!< CLK_T::CLKDCTL: HXTFQDEN Position */ +#define CLK_CLKDCTL_HXTFQDEN_Msk (0x1ul << CLK_CLKDCTL_HXTFQDEN_Pos) /*!< CLK_T::CLKDCTL: HXTFQDEN Mask */ + +#define CLK_CLKDCTL_HXTFQIEN_Pos (17) /*!< CLK_T::CLKDCTL: HXTFQIEN Position */ +#define CLK_CLKDCTL_HXTFQIEN_Msk (0x1ul << CLK_CLKDCTL_HXTFQIEN_Pos) /*!< CLK_T::CLKDCTL: HXTFQIEN Mask */ + +#define CLK_CLKDSTS_HXTFIF_Pos (0) /*!< CLK_T::CLKDSTS: HXTFIF Position */ +#define CLK_CLKDSTS_HXTFIF_Msk (0x1ul << CLK_CLKDSTS_HXTFIF_Pos) /*!< CLK_T::CLKDSTS: HXTFIF Mask */ + +#define CLK_CLKDSTS_LXTFIF_Pos (1) /*!< CLK_T::CLKDSTS: LXTFIF Position */ +#define CLK_CLKDSTS_LXTFIF_Msk (0x1ul << CLK_CLKDSTS_LXTFIF_Pos) /*!< CLK_T::CLKDSTS: LXTFIF Mask */ + +#define CLK_CLKDSTS_HXTFQIF_Pos (8) /*!< CLK_T::CLKDSTS: HXTFQIF Position */ +#define CLK_CLKDSTS_HXTFQIF_Msk (0x1ul << CLK_CLKDSTS_HXTFQIF_Pos) /*!< CLK_T::CLKDSTS: HXTFQIF Mask */ + +#define CLK_CDUPB_UPERBD_Pos (0) /*!< CLK_T::CDUPB: UPERBD Position */ +#define CLK_CDUPB_UPERBD_Msk (0x3fful << CLK_CDUPB_UPERBD_Pos) /*!< CLK_T::CDUPB: UPERBD Mask */ + +#define CLK_CDLOWB_LOWERBD_Pos (0) /*!< CLK_T::CDLOWB: LOWERBD Position */ +#define CLK_CDLOWB_LOWERBD_Msk (0x3fful << CLK_CDLOWB_LOWERBD_Pos) /*!< CLK_T::CDLOWB: LOWERBD Mask */ + +#define CLK_PMUCTL_PDMSEL_Pos (0) /*!< CLK_T::PMUCTL: PDMSEL Position */ +#define CLK_PMUCTL_PDMSEL_Msk (0x7ul<< CLK_PMUCTL_PDMSEL_Pos) /*!< CLK_T::PMUCTL: PDMSEL Mask */ + +#define CLK_PMUCTL_VDROPEN_Pos (4) /*!< CLK_T::PMUCTL: VDROPEN Position */ +#define CLK_PMUCTL_VDROPEN_Msk (0x1ul<< CLK_PMUCTL_VDROPEN_Pos) /*!< CLK_T::PMUCTL: VDROPEN Mask */ + +#define CLK_PMUCTL_WRBUSY_Pos (7) /*!< CLK_T::PMUCTL: WRBUSY Position */ +#define CLK_PMUCTL_WRBUSY_Msk (0x1ul<< CLK_PMUCTL_WRBUSY_Pos) /*!< CLK_T::PMUCTL: WRBUSY Mask */ + +#define CLK_PMUCTL_WKTMREN_Pos (8) /*!< CLK_T::PMUCTL: WKTMREN Position */ +#define CLK_PMUCTL_WKTMREN_Msk (0x1ul<< CLK_PMUCTL_WKTMREN_Pos) /*!< CLK_T::PMUCTL: WKTMREN Mask */ + +#define CLK_PMUCTL_WKTMRIS_Pos (9) /*!< CLK_T::PMUCTL: WKTMRIS Position */ +#define CLK_PMUCTL_WKTMRIS_Msk (0x7ul<< CLK_PMUCTL_WKTMRIS_Pos) /*!< CLK_T::PMUCTL: WKTMRIS Mask */ + +#define CLK_PMUCTL_WKPINEN_Pos (16) /*!< CLK_T::PMUCTL: WKPINEN Position */ +#define CLK_PMUCTL_WKPINEN_Msk (0x3ul<< CLK_PMUCTL_WKPINEN_Pos) /*!< CLK_T::PMUCTL: WKPINEN Mask */ + +#define CLK_PMUCTL_WKPINEN0_Pos (16) /*!< CLK_T::PMUCTL: WKPINEN0 Position */ +#define CLK_PMUCTL_WKPINEN0_Msk (0x3ul<< CLK_PMUCTL_WKPINEN0_Pos) /*!< CLK_T::PMUCTL: WKPINEN0 Mask */ + +#define CLK_PMUCTL_ACMPSPWK_Pos (18) /*!< CLK_T::PMUCTL: ACMPSPWK Position */ +#define CLK_PMUCTL_ACMPSPWK_Msk (0x1ul<< CLK_PMUCTL_ACMPSPWK_Pos) /*!< CLK_T::PMUCTL: ACMPSPWK Mask */ + +#define CLK_PMUCTL_TAMPERWK_Pos (19) /*!< CLK_T::PMUCTL: TAMPERWK Position */ +#define CLK_PMUCTL_TAMPERWK_Msk (0x1ul<< CLK_PMUCTL_TAMPERWK_Pos) /*!< CLK_T::PMUCTL: TAMPERWK Mask */ + +#define CLK_PMUCTL_RTCWKEN_Pos (23) /*!< CLK_T::PMUCTL: RTCWKEN Position */ +#define CLK_PMUCTL_RTCWKEN_Msk (0x1ul<< CLK_PMUCTL_RTCWKEN_Pos) /*!< CLK_T::PMUCTL: RTCWKEN Mask */ + +#define CLK_PMUCTL_WKPINEN1_Pos (24) /*!< CLK_T::PMUCTL: WKPINEN1 Position */ +#define CLK_PMUCTL_WKPINEN1_Msk (0x3ul << CLK_PMUCTL_WKPINEN1_Pos) /*!< CLK_T::PMUCTL: WKPINEN1 Mask */ + +#define CLK_PMUCTL_WKPINEN2_Pos (26) /*!< CLK_T::PMUCTL: WKPINEN2 Position */ +#define CLK_PMUCTL_WKPINEN2_Msk (0x3ul << CLK_PMUCTL_WKPINEN2_Pos) /*!< CLK_T::PMUCTL: WKPINEN2 Mask */ + +#define CLK_PMUCTL_WKPINEN3_Pos (28) /*!< CLK_T::PMUCTL: WKPINEN3 Position */ +#define CLK_PMUCTL_WKPINEN3_Msk (0x3ul << CLK_PMUCTL_WKPINEN3_Pos) /*!< CLK_T::PMUCTL: WKPINEN3 Mask */ + +#define CLK_PMUCTL_WKPINEN4_Pos (30) /*!< CLK_T::PMUCTL: WKPINEN4 Position */ +#define CLK_PMUCTL_WKPINEN4_Msk (0x3ul << CLK_PMUCTL_WKPINEN4_Pos) /*!< CLK_T::PMUCTL: WKPINEN4 Mask */ + +#define CLK_PMUSTS_PINWK0_Pos (0) /*!< CLK_T::PMUSTS: PINWK0 Position */ +#define CLK_PMUSTS_PINWK0_Msk (0x1ul << CLK_PMUSTS_PINWK0_Pos) /*!< CLK_T::PMUSTS: PINWK0 Mask */ + +#define CLK_PMUSTS_PINWK_Pos (0) /*!< CLK_T::PMUSTS: PINWK Position */ +#define CLK_PMUSTS_PINWK_Msk (0x1ul << CLK_PMUSTS_PINWK_Pos) /*!< CLK_T::PMUSTS: PINWK Mask */ + +#define CLK_PMUSTS_TMRWK_Pos (1) /*!< CLK_T::PMUSTS: TMRWK Position */ +#define CLK_PMUSTS_TMRWK_Msk (0x1ul << CLK_PMUSTS_TMRWK_Pos) /*!< CLK_T::PMUSTS: TMRWK Mask */ + +#define CLK_PMUSTS_RTCWK_Pos (2) /*!< CLK_T::PMUSTS: RTCWK Position */ +#define CLK_PMUSTS_RTCWK_Msk (0x1ul << CLK_PMUSTS_RTCWK_Pos) /*!< CLK_T::PMUSTS: RTCWK Mask */ + +#define CLK_PMUSTS_PINWK1_Pos (3) /*!< CLK_T::PMUSTS: PINWK1 Position */ +#define CLK_PMUSTS_PINWK1_Msk (0x1ul << CLK_PMUSTS_PINWK1_Pos) /*!< CLK_T::PMUSTS: PINWK1 Mask */ + +#define CLK_PMUSTS_PINWK2_Pos (4) /*!< CLK_T::PMUSTS: PINWK2 Position */ +#define CLK_PMUSTS_PINWK2_Msk (0x1ul << CLK_PMUSTS_PINWK2_Pos) /*!< CLK_T::PMUSTS: PINWK2 Mask */ + +#define CLK_PMUSTS_PINWK3_Pos (5) /*!< CLK_T::PMUSTS: PINWK3 Position */ +#define CLK_PMUSTS_PINWK3_Msk (0x1ul << CLK_PMUSTS_PINWK3_Pos) /*!< CLK_T::PMUSTS: PINWK3 Mask */ + +#define CLK_PMUSTS_PINWK4_Pos (6) /*!< CLK_T::PMUSTS: PINWK4 Position */ +#define CLK_PMUSTS_PINWK4_Msk (0x1ul << CLK_PMUSTS_PINWK4_Pos) /*!< CLK_T::PMUSTS: PINWK4 Mask */ + +#define CLK_PMUSTS_GPAWK_Pos (8) /*!< CLK_T::PMUSTS: GPAWK Position */ +#define CLK_PMUSTS_GPAWK_Msk (0x1ul << CLK_PMUSTS_GPAWK_Pos) /*!< CLK_T::PMUSTS: GPAWK Mask */ + +#define CLK_PMUSTS_GPBWK_Pos (9) /*!< CLK_T::PMUSTS: GPBWK Position */ +#define CLK_PMUSTS_GPBWK_Msk (0x1ul << CLK_PMUSTS_GPBWK_Pos) /*!< CLK_T::PMUSTS: GPBWK Mask */ + +#define CLK_PMUSTS_GPCWK_Pos (10) /*!< CLK_T::PMUSTS: GPCWK Position */ +#define CLK_PMUSTS_GPCWK_Msk (0x1ul << CLK_PMUSTS_GPCWK_Pos) /*!< CLK_T::PMUSTS: GPCWK Mask */ + +#define CLK_PMUSTS_GPDWK_Pos (11) /*!< CLK_T::PMUSTS: GPDWK Position */ +#define CLK_PMUSTS_GPDWK_Msk (0x1ul << CLK_PMUSTS_GPDWK_Pos) /*!< CLK_T::PMUSTS: GPDWK Mask */ + +#define CLK_PMUSTS_LVRWK_Pos (12) /*!< CLK_T::PMUSTS: LVRWK Position */ +#define CLK_PMUSTS_LVRWK_Msk (0x1ul << CLK_PMUSTS_LVRWK_Pos) /*!< CLK_T::PMUSTS: LVRWK Mask */ + +#define CLK_PMUSTS_BODWK_Pos (13) /*!< CLK_T::PMUSTS: BODWK Position */ +#define CLK_PMUSTS_BODWK_Msk (0x1ul << CLK_PMUSTS_BODWK_Pos) /*!< CLK_T::PMUSTS: BODWK Mask */ + +#define CLK_PMUSTS_ACMPWK_Pos (14) /*!< CLK_T::PMUSTS: ACMPWK Position */ +#define CLK_PMUSTS_ACMPWK_Msk (0x1ul << CLK_PMUSTS_ACMPWK_Pos) /*!< CLK_T::PMUSTS: ACMPWK Mask */ + +#define CLK_PMUSTS_TAMPERWK_Pos (15) /*!< CLK_T::PMUSTS: TAMPERWK Position */ +#define CLK_PMUSTS_TAMPERWK_Msk (0x1ul << CLK_PMUSTS_TAMPERWK_Pos) /*!< CLK_T::PMUSTS: TAMPERWK Mask */ + +#define CLK_PMUSTS_CLRWK_Pos (31) /*!< CLK_T::PMUSTS: CLRWK Position */ +#define CLK_PMUSTS_CLRWK_Msk (0x1ul << CLK_PMUSTS_CLRWK_Pos) /*!< CLK_T::PMUSTS: CLRWK Mask */ + +#define CLK_SWKDBCTL_SWKDBCLKSEL_Pos (0) /*!< CLK_T::SWKDBCTL: SWKDBCLKSEL Position */ +#define CLK_SWKDBCTL_SWKDBCLKSEL_Msk (0xFul<< CLK_SWKDBCTL_SWKDBCLKSEL_Pos) /*!< CLK_T::SWKDBCTL: SWKDBCLKSEL Mask */ + +#define CLK_PASWKCTL_WKEN_Pos (0) /*!< CLK_T::PASWKCTL: WKEN Position */ +#define CLK_PASWKCTL_WKEN_Msk (0x1ul << CLK_PASWKCTL_WKEN_Pos) /*!< CLK_T::PASWKCTL: WKEN Mask */ + +#define CLK_PASWKCTL_PRWKEN_Pos (1) /*!< CLK_T::PASWKCTL: PRWKEN Position */ +#define CLK_PASWKCTL_PRWKEN_Msk (0x1ul << CLK_PASWKCTL_PRWKEN_Pos) /*!< CLK_T::PASWKCTL: PRWKEN Mask */ + +#define CLK_PASWKCTL_PFWKEN_Pos (2) /*!< CLK_T::PASWKCTL: PFWKEN Position */ +#define CLK_PASWKCTL_PFWKEN_Msk (0x1ul << CLK_PASWKCTL_PFWKEN_Pos) /*!< CLK_T::PASWKCTL: PFWKEN Mask */ + +#define CLK_PASWKCTL_WKPSEL_Pos (4) /*!< CLK_T::PASWKCTL: WKPSEL Position */ +#define CLK_PASWKCTL_WKPSEL_Msk (0xful << CLK_PASWKCTL_WKPSEL_Pos) /*!< CLK_T::PASWKCTL: WKPSEL Mask */ + +#define CLK_PASWKCTL_DBEN_Pos (8) /*!< CLK_T::PASWKCTL: DBEN Position */ +#define CLK_PASWKCTL_DBEN_Msk (0x1ul << CLK_PASWKCTL_DBEN_Pos) /*!< CLK_T::PASWKCTL: DBEN Mask */ + +#define CLK_PBSWKCTL_WKEN_Pos (0) /*!< CLK_T::PBSWKCTL: WKEN Position */ +#define CLK_PBSWKCTL_WKEN_Msk (0x1ul << CLK_PBSWKCTL_WKEN_Pos) /*!< CLK_T::PBSWKCTL: WKEN Mask */ + +#define CLK_PBSWKCTL_PRWKEN_Pos (1) /*!< CLK_T::PBSWKCTL: PRWKEN Position */ +#define CLK_PBSWKCTL_PRWKEN_Msk (0x1ul << CLK_PBSWKCTL_PRWKEN_Pos) /*!< CLK_T::PBSWKCTL: PRWKEN Mask */ + +#define CLK_PBSWKCTL_PFWKEN_Pos (2) /*!< CLK_T::PBSWKCTL: PFWKEN Position */ +#define CLK_PBSWKCTL_PFWKEN_Msk (0x1ul << CLK_PBSWKCTL_PFWKEN_Pos) /*!< CLK_T::PBSWKCTL: PFWKEN Mask */ + +#define CLK_PBSWKCTL_WKPSEL_Pos (4) /*!< CLK_T::PBSWKCTL: WKPSEL Position */ +#define CLK_PBSWKCTL_WKPSEL_Msk (0xful << CLK_PBSWKCTL_WKPSEL_Pos) /*!< CLK_T::PBSWKCTL: WKPSEL Mask */ + +#define CLK_PBSWKCTL_DBEN_Pos (8) /*!< CLK_T::PBSWKCTL: DBEN Position */ +#define CLK_PBSWKCTL_DBEN_Msk (0x1ul << CLK_PBSWKCTL_DBEN_Pos) /*!< CLK_T::PBSWKCTL: DBEN Mask */ + +#define CLK_PCSWKCTL_WKEN_Pos (0) /*!< CLK_T::PCSWKCTL: WKEN Position */ +#define CLK_PCSWKCTL_WKEN_Msk (0x1ul << CLK_PCSWKCTL_WKEN_Pos) /*!< CLK_T::PCSWKCTL: WKEN Mask */ + +#define CLK_PCSWKCTL_PRWKEN_Pos (1) /*!< CLK_T::PCSWKCTL: PRWKEN Position */ +#define CLK_PCSWKCTL_PRWKEN_Msk (0x1ul << CLK_PCSWKCTL_PRWKEN_Pos) /*!< CLK_T::PCSWKCTL: PRWKEN Mask */ + +#define CLK_PCSWKCTL_PFWKEN_Pos (2) /*!< CLK_T::PCSWKCTL: PFWKEN Position */ +#define CLK_PCSWKCTL_PFWKEN_Msk (0x1ul << CLK_PCSWKCTL_PFWKEN_Pos) /*!< CLK_T::PCSWKCTL: PFWKEN Mask */ + +#define CLK_PCSWKCTL_WKPSEL_Pos (4) /*!< CLK_T::PCSWKCTL: WKPSEL Position */ +#define CLK_PCSWKCTL_WKPSEL_Msk (0xful << CLK_PCSWKCTL_WKPSEL_Pos) /*!< CLK_T::PCSWKCTL: WKPSEL Mask */ + +#define CLK_PCSWKCTL_DBEN_Pos (8) /*!< CLK_T::PCSWKCTL: DBEN Position */ +#define CLK_PCSWKCTL_DBEN_Msk (0x1ul << CLK_PCSWKCTL_DBEN_Pos) /*!< CLK_T::PCSWKCTL: DBEN Mask */ + +#define CLK_PDSWKCTL_WKEN_Pos (0) /*!< CLK_T::PDSWKCTL: WKEN Position */ +#define CLK_PDSWKCTL_WKEN_Msk (0x1ul << CLK_PDSWKCTL_WKEN_Pos) /*!< CLK_T::PDSWKCTL: WKEN Mask */ + +#define CLK_PDSWKCTL_PRWKEN_Pos (1) /*!< CLK_T::PDSWKCTL: PRWKEN Position */ +#define CLK_PDSWKCTL_PRWKEN_Msk (0x1ul << CLK_PDSWKCTL_PRWKEN_Pos) /*!< CLK_T::PDSWKCTL: PRWKEN Mask */ + +#define CLK_PDSWKCTL_PFWKEN_Pos (2) /*!< CLK_T::PDSWKCTL: PFWKEN Position */ +#define CLK_PDSWKCTL_PFWKEN_Msk (0x1ul << CLK_PDSWKCTL_PFWKEN_Pos) /*!< CLK_T::PDSWKCTL: PFWKEN Mask */ + +#define CLK_PDSWKCTL_WKPSEL_Pos (4) /*!< CLK_T::PDSWKCTL: WKPSEL Position */ +#define CLK_PDSWKCTL_WKPSEL_Msk (0xful << CLK_PDSWKCTL_WKPSEL_Pos) /*!< CLK_T::PDSWKCTL: WKPSEL Mask */ + +#define CLK_PDSWKCTL_DBEN_Pos (8) /*!< CLK_T::PDSWKCTL: DBEN Position */ +#define CLK_PDSWKCTL_DBEN_Msk (0x1ul << CLK_PDSWKCTL_DBEN_Pos) /*!< CLK_T::PDSWKCTL: DBEN Mask */ + +#define CLK_IOPDCTL_IOHR_Pos (0) /*!< CLK_T::IOPDCTL: IOHR Position */ +#define CLK_IOPDCTL_IOHR_Msk (0x1ul << CLK_IOPDCTL_IOHR_Pos) /*!< CLK_T::IOPDCTL: IOHR Mask */ + +#define CLK_HXTFSEL_HXTFSEL_Pos (0) /*!< CLK_T::HXTFSEL: HXTFSEL Position */ +#define CLK_HXTFSEL_HXTFSEL_Msk (0x1ul << CLK_HXTFSEL_HXTFSEL_Pos) /*!< CLK_T::HXTFSEL: HXTFSEL Mask */ + + +/**@}*/ /* CLK_CONST */ +/**@}*/ /* end of CLK register group */ +/**@}*/ /* end of REGISTER group */ + +#endif /* __CLK_REG_H__ */ diff --git a/Ubiquitous/XiZi/board/nuvoton-m2354/third_party_driver/include/Regs/crc_reg.h b/Ubiquitous/XiZi/board/nuvoton-m2354/third_party_driver/include/Regs/crc_reg.h new file mode 100644 index 0000000..4fe1913 --- /dev/null +++ b/Ubiquitous/XiZi/board/nuvoton-m2354/third_party_driver/include/Regs/crc_reg.h @@ -0,0 +1,153 @@ +/**************************************************************************//** + * @file crc_reg.h + * @version V1.00 + * @brief CRC register definition header file + * + * @copyright SPDX-License-Identifier: Apache-2.0 + * @copyright Copyright (C) 2020 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ +#ifndef __CRC_REG_H__ +#define __CRC_REG_H__ + +/** @addtogroup REGISTER Control Register + + @{ + +*/ + + +/*---------------------- Cyclic Redundancy Check Controller -------------------------*/ +/** + @addtogroup CRC Cyclic Redundancy Check Controller(CRC) + Memory Mapped Structure for CRC Controller + @{ +*/ + +typedef struct +{ + + + /** + * @var CRC_T::CTL + * Offset: 0x00 CRC Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |CRCEN |CRC Channel Generator Enable Bit + * | | |Set this bit 1 to enable CRC generator for CRC operation. + * | | |0 = No effect. + * | | |1 = CRC operation generator is active. + * |[1] |CHKSINIT |Checksum Initialization + * | | |Set this bit will auto reload SEED (CRC_SEED [31:0]) to CHECKSUM (CRC_CHECKSUM[31:0]) as CRC operation initial value. + * | | |0 = No effect. + * | | |1 = Reload SEED value to CHECKSUM register as CRC operation initial checksum value. + * | | |The others contents of CRC_CTL register will not be cleared. + * | | |Note1: This bit will be cleared automatically + * | | |Note2: Setting this bit will reload the seed value from CRC_SEED register as checksum initial value. + * |[24] |DATREV |Write Data Bit Order Reverse Enable Bit + * | | |This bit is used to enable the bit order reverse function per byte for write data value DATA (CRC_DATA[31:0]) in CRC_DAT register. + * | | |0 = Bit order reversed for CRC_DATA write data in Disabled. + * | | |1 = Bit order reversed for CRC_DATA write data in Enabled (per byte). + * | | |Note: If the write data is 0xAABBCCDD, the bit order reverse for CRC write data in is 0x55DD33BB. + * |[25] |CHKSREV |Checksum Bit Order Reverse Enable Bit + * | | |This bit is used to enable the bit order reverse function for checksum result CHECKSUM (CRC_CHECKSUM[31:0]). + * | | |0 = Bit order reverse for CRC CHECKSUMCRC checksum Disabled. + * | | |1 = Bit order reverse for CRC CHECKSUMCRC checksum Enabled. + * | | |Note: If the checksum result is 0xDD7B0F2E, the bit order reverse result for CRC checksum is 0x74F0DEBB. + * |[26] |DATFMT |Write Data 1's Complement Enable Bit + * | | |This bit is used to enable the 1's complement function for write data value DATA (CRC_DATA[31:0]). + * | | |0 = 1's complement for CRC_DATA writes data in Disabled. + * | | |1 = 1's complement for CRC_DATA writes data in Enabled. + * |[27] |CHKSFMT |Checksum 1's Complement Enable Bit + * | | |This bit is used to enable the 1's complement function for checksum result in CHECKSUM (CRC_CHECKSUM[31:0]) register. + * | | |0 = 1's complement for CRC CHECKSUM Disabled. + * | | |1 = 1's complement for CRC CHECKSUMCRC Enabled. + * |[29:28] |DATLEN |CPU Write Data Length + * | | |This field indicates the valid write data length of DATA (CRC_DAT[31:0]). + * | | |00 = Data length is 8-bit mode. + * | | |01 = Data length is 16-bit mode. + * | | |1x = Data length is 32-bit mode. + * | | |Note: When the write data length is 8-bit mode, the valid data in CRC_DAT register is only DATA[7:0] bits; if the write data length is 16-bit mode, the valid data in CRC_DAT register is only DATA[15:0] + * |[31:30] |CRCMODE |CRC Polynomial Mode + * | | |This field indicates the CRC operation polynomial mode. + * | | |00 = CRC-CCITT Polynomial mode. + * | | |01 = CRC-8 Polynomial mode. + * | | |10 = CRC-16 Polynomial mode. + * | | |11 = CRC-32 Polynomial mode. + * @var CRC_T::DAT + * Offset: 0x04 CRC Write Data Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |DATA |CRC Write Data Bits + * | | |User can write data directly by CPU mode or use PDMA function to write data to this field to perform CRC operation. + * | | |Note: When the write data length is 8-bit mode, the valid data in CRC_DAT register is only DATA[7:0] bits; if the write data length is 16-bit mode, the valid data in CRC_DAT register is only DATA[15:0]. + * @var CRC_T::SEED + * Offset: 0x08 CRC Seed Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |SEED |CRC Seed Value + * | | |This field indicates the CRC seed value. + * | | |Note1: This field SEED value will be reloaded to as checksum initial value CHECKSUM (CRC_CHECKSUM[31:0]) register) after perform CRC engine reset, CHKSINIT (CRC_CTL[1]) to 1. + * | | |Note2: The valid bits of CRC_SEED[31:0] is correlated to CRCMODE (CRC_CTL[31:30]). + * @var CRC_T::CHECKSUM + * Offset: 0x0C CRC Checksum Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |CHECKSUM |CRC Checksum Results + * | | |This field indicates the CRC checksum result. + * | | |Note: The valid bits of CRC_CHECKSUM[31:0] is correlated to CRCMODE (CRC_CTL[31:30]). + */ + __IO uint32_t CTL; /*!< [0x0000] CRC Control Register */ + __IO uint32_t DAT; /*!< [0x0004] CRC Write Data Register */ + __IO uint32_t SEED; /*!< [0x0008] CRC Seed Register */ + __I uint32_t CHECKSUM; /*!< [0x000c] CRC Checksum Register */ + +} CRC_T; + +/** + @addtogroup CRC_CONST CRC Bit Field Definition + Constant Definitions for CRC Controller + @{ +*/ + +#define CRC_CTL_CRCEN_Pos (0) /*!< CRC_T::CTL: CRCEN Position */ +#define CRC_CTL_CRCEN_Msk (0x1ul << CRC_CTL_CRCEN_Pos) /*!< CRC_T::CTL: CRCEN Mask */ + +#define CRC_CTL_CHKSINIT_Pos (1) /*!< CRC_T::CTL: CHKSINIT Position */ +#define CRC_CTL_CHKSINIT_Msk (0x1ul << CRC_CTL_CHKSINIT_Pos) /*!< CRC_T::CTL: CHKSINIT Mask */ + +#define CRC_CTL_DATREV_Pos (24) /*!< CRC_T::CTL: DATREV Position */ +#define CRC_CTL_DATREV_Msk (0x1ul << CRC_CTL_DATREV_Pos) /*!< CRC_T::CTL: DATREV Mask */ + +#define CRC_CTL_CHKSREV_Pos (25) /*!< CRC_T::CTL: CHKSREV Position */ +#define CRC_CTL_CHKSREV_Msk (0x1ul << CRC_CTL_CHKSREV_Pos) /*!< CRC_T::CTL: CHKSREV Mask */ + +#define CRC_CTL_DATFMT_Pos (26) /*!< CRC_T::CTL: DATFMT Position */ +#define CRC_CTL_DATFMT_Msk (0x1ul << CRC_CTL_DATFMT_Pos) /*!< CRC_T::CTL: DATFMT Mask */ + +#define CRC_CTL_CHKSFMT_Pos (27) /*!< CRC_T::CTL: CHKSFMT Position */ +#define CRC_CTL_CHKSFMT_Msk (0x1ul << CRC_CTL_CHKSFMT_Pos) /*!< CRC_T::CTL: CHKSFMT Mask */ + +#define CRC_CTL_DATLEN_Pos (28) /*!< CRC_T::CTL: DATLEN Position */ +#define CRC_CTL_DATLEN_Msk (0x3ul << CRC_CTL_DATLEN_Pos) /*!< CRC_T::CTL: DATLEN Mask */ + +#define CRC_CTL_CRCMODE_Pos (30) /*!< CRC_T::CTL: CRCMODE Position */ +#define CRC_CTL_CRCMODE_Msk (0x3ul << CRC_CTL_CRCMODE_Pos) /*!< CRC_T::CTL: CRCMODE Mask */ + +#define CRC_DAT_DATA_Pos (0) /*!< CRC_T::DAT: DATA Position */ +#define CRC_DAT_DATA_Msk (0xfffffffful << CRC_DAT_DATA_Pos) /*!< CRC_T::DAT: DATA Mask */ + +#define CRC_SEED_SEED_Pos (0) /*!< CRC_T::SEED: SEED Position */ +#define CRC_SEED_SEED_Msk (0xfffffffful << CRC_SEED_SEED_Pos) /*!< CRC_T::SEED: SEED Mask */ + +#define CRC_CHECKSUM_CHECKSUM_Pos (0) /*!< CRC_T::CHECKSUM: CHECKSUM Position */ +#define CRC_CHECKSUM_CHECKSUM_Msk (0xfffffffful << CRC_CHECKSUM_CHECKSUM_Pos) /*!< CRC_T::CHECKSUM: CHECKSUM Mask */ + +/**@}*/ /* CRC_CONST */ +/**@}*/ /* end of CRC register group */ +/**@}*/ /* end of REGISTER group */ + +#endif /* __CLK_REG_H__ */ diff --git a/Ubiquitous/XiZi/board/nuvoton-m2354/third_party_driver/include/Regs/crpt_reg.h b/Ubiquitous/XiZi/board/nuvoton-m2354/third_party_driver/include/Regs/crpt_reg.h new file mode 100644 index 0000000..ddffb2b --- /dev/null +++ b/Ubiquitous/XiZi/board/nuvoton-m2354/third_party_driver/include/Regs/crpt_reg.h @@ -0,0 +1,2083 @@ +/**************************************************************************//** +* @file crpt_reg.h +* @version V1.00 +* @brief CRPT register definition header file +* +* @copyright SPDX-License-Identifier: Apache-2.0 +* @copyright Copyright (C) 2020 Nuvoton Technology Corp. All rights reserved. +*****************************************************************************/ +#ifndef __CRPT_REG_H__ +#define __CRPT_REG_H__ + + +/** @addtogroup REGISTER Control Register + + @{ + +*/ + + +/*---------------------- Cryptographic Accelerator -------------------------*/ +/** + @addtogroup CRPT Cryptographic Accelerator(CRPT) + Memory Mapped Structure for CRPT Controller + @{ +*/ + +typedef struct +{ + + + /** + * @var CRPT_T::INTEN + * Offset: 0x00 Crypto Interrupt Enable Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |AESIEN |AES Interrupt Enable Bit + * | | |0 = AES interrupt Disabled. + * | | |1 = AES interrupt Enabled. + * | | |Note: In DMA mode, an interrupt will be triggered when amount of data set in AES_DMA_CNT is fed into the AES engine. + * | | |In Non-DMA mode, an interrupt will be triggered when the AES engine finishes the operation. + * |[1] |AESEIEN |AES Error Flag Enable Bit + * | | |0 = AES error interrupt flag Disabled. + * | | |1 = AES error interrupt flag Enabled. + * |[16] |PRNGIEN |PRNG Interrupt Enable Bit + * | | |0 = PRNG interrupt Disabled. + * | | |1 = PRNG interrupt Enabled. + * |[17] |PRNGEIEN |PRNG Error Flag Enable Bit + * | | |0 = PRNG error interrupt flag Disabled. + * | | |1 = PRNG error interrupt flag Enabled. + * |[22] |ECCIEN |ECC Interrupt Enable Bit + * | | |0 = ECC interrupt Disabled. + * | | |1 = ECC interrupt Enabled. + * | | |Note: In DMA mode, an interrupt will be triggered when amount of data set in ECC_DMA_CNT is fed into the ECC engine + * | | |In Non-DMA mode, an interrupt will be triggered when the ECC engine finishes the operation. + * |[23] |ECCEIEN |ECC Error Interrupt Enable Bit + * | | |0 = ECC error interrupt flag Disabled. + * | | |1 = ECC error interrupt flag Enabled. + * |[24] |HMACIEN |SHA/HMAC Interrupt Enable Bit + * | | |0 = SHA/HMAC interrupt Disabled. + * | | |1 = SHA/HMAC interrupt Enabled. + * | | |Note: In DMA mode, an interrupt will be triggered when amount of data set in HMAC_DMA_CNT is fed into the SHA/HMAC engine + * | | |In Non-DMA mode, an interrupt will be triggered when the SHA/HMAC engine finishes the operation. + * |[25] |HMACEIEN |SHA/HMAC Error Interrupt Enable Bit + * | | |0 = SHA/HMAC error interrupt flag Disabled. + * | | |1 = HMAC error interrupt flag Enabled. + * |[30] |RSAIEN |RSA Interrupt Enable Bit + * | | |0 = RSA interrupt Disabled. + * | | |1 = RSA interrupt Enabled. + * | | |Note: In DMA mode, an interrupt will be triggered when amount of data set in RSA_DMA_CNT is fed into the RSA engine. + * |[31] |RSAEIEN |RSA Error Interrupt Enable Bit + * | | |0 = RSA error interrupt flag Disabled. + * | | |1 = RSA error interrupt flag Enabled. + * @var CRPT_T::INTSTS + * Offset: 0x04 Crypto Interrupt Flag + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |AESIF |AES Finish Interrupt Flag + * | | |0 = No AES interrupt. + * | | |1 = AES encryption/decryption done interrupt. + * | | |Note:This bit is cleared by writing 1, and it has no effect by writing 0. + * |[1] |AESEIF |AES Error Flag + * | | |0 = No AES error. + * | | |1 = AES encryption/decryption error interrupt. + * | | |Note:This bit is cleared by writing 1, and it has no effect by writing 0. + * |[16] |PRNGIF |PRNG Finish Interrupt Flag + * | | |0 = No PRNG interrupt. + * | | |1 = PRNG key generation done interrupt. + * | | |Note:This bit is cleared by writing 1, and it has no effect by writing 0. + * |[17] |PRNGEIF |PRNGError Flag + * | | |0 = No PRNG error. + * | | |1 = PRNG key generation error interrupt. + * | | |Note:This bit is cleared by writing 1, and it has no effect by writing 0. + * |[22] |ECCIF |ECC Finish Interrupt Flag + * | | |0 = No ECC interrupt. + * | | |1 = ECC operation done interrupt. + * | | |Note:This bit is cleared by writing 1, and it has no effect by writing 0. + * |[23] |ECCEIF |ECC Error Flag + * | | |This register includes operating and setting error + * | | |The detail flag is shown in CRPT_ECC_STS register. + * | | |0 = No ECC error. + * | | |1 = ECC error interrupt. + * | | |Note:This bit is cleared by writing 1, and it has no effect by writing 0. + * |[24] |HMACIF |SHA/HMAC Finish Interrupt Flag + * | | |0 = No SHA/HMAC interrupt. + * | | |1 = SHA/HMAC operation done interrupt. + * | | |Note:This bit is cleared by writing 1, and it has no effect by writing 0. + * |[25] |HMACEIF |SHA/HMAC Error Flag + * | | |This register includes operating and setting error + * | | |The detail flag is shown in CRPT_HMAC_STS register. + * | | |0 = No SHA/HMAC error. + * | | |1 = SHA/HMAC error interrupt. + * | | |Note:This bit is cleared by writing 1, and it has no effect by writing 0. + * |[30] |RSAIF |RSA Finish Interrupt Flag + * | | |This bit is cleared by writing 1, and it has no effect by writing 0. + * | | |0 = No RSA interrupt. + * | | |1 = RSA operation done interrupt. + * |[31] |RSAEIF |RSA Error Interrupt Flag + * | | |This register includes operating and setting error + * | | |The detail flag is shown in CRPT_RSA_STS register. + * | | |This bit is cleared by writing 1, and it has no effect by writing 0. + * | | |0 = No RSA error. + * | | |1 = RSA error interrupt. + * @var CRPT_T::PRNG_CTL + * Offset: 0x08 PRNG Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |START |Start PRNG Engine + * | | |0 = Stop PRNG engine. + * | | |1 = Generate new key and store the new key to register CRPT_PRNG_KEYx, which will be cleared when the new key is generated. + * |[1] |SEEDRLD |Reload New Seed for PRNG Engine + * | | |0 = Generating key based on the current seed. + * | | |1 = Reload new seed. + * |[5:2] |KEYSZ |PRNG Generate Key Size + * | | |0000 = 128 bits. + * | | |0001 = 163 bits. + * | | |0010 = 192 bits. + * | | |0011 = 224 bits. + * | | |0100 = 233 bits. + * | | |0101 = 255 bits. + * | | |0110 = 256 bits. + * | | |0111 = 283 bits (only for KS). + * | | |1000 = 384 bits (only for KS). + * | | |1001 = 409 bits (only for KS). + * | | |1010 = 512 bits (only for KS). + * | | |1011 = 521 bits (only for KS). + * | | |1100 = 571 bits (only for KS). + * | | |1101 = Reserved. + * | | |1110 = Reserved. + * | | |1111 = Reserved. + * | | |Note: 283~571 bits only generate for Key Store. + * |[6] |SEEDSEL |Seed Select + * | | |This bit can be set to 1 only after SEEDRDY (TRNG_CTL[9]) bit become to 1. + * | | |0 = Select the seed which is from PRNG. + * | | |1 = Select the seed which is from TRNG. (not from CRPT_PRNG_SEED) + * |[7] |SEEDSRC |Seed Source (Read Only) + * | | |0 = Seed is from PRNG. + * | | |1 = Seed is from TRNG. (not from CRPT_PRNG_SEED) + * | | |Note: This bit is cleared to u20180u2019 when SEEDSEL is 0. + * |[8] |BUSY |PRNG Busy (Read Only) + * | | |0 = PRNG engine is idle. + * | | |1 = Indicate that the PRNG engine is generating CRPT_PRNG_KEYx. + * @var CRPT_T::PRNG_SEED + * Offset: 0x0C Seed for PRNG + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |SEED |Seed for PRNG (Write Only) + * | | |The bits store the seed for PRNG engine. + * | | |Note: In TRNG+PRNG mode, the seed is from TRNGengine, and it will not store in this register. + * @var CRPT_T::PRNG_KEY + * Offset: 0x10-0x2C PRNG Generated Key + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |KEY |Store PRNG Generated Key (Read Only) + * | | |The bits store the key that is generated by PRNG. + * @var CRPT_T::PRNG_STS + * Offset: 0x30 PRNG Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |BUSY |PRNG Busy Flag + * | | |0 = PRNG engine is idle. + * | | |1 = Indicate that the PRNG engine is generating CRPT_PRNG_KEYx. + * |[16] |KCTLERR |PRNG Key Control Register Error Flag + * | | |0 = No error. + * | | |1 = PRNG key control error + * | | |When PRNG execute ECDSA or ECDH, but PRNG seed not from TRNG or key is not written to the SRAM of key store (WSDST,CRPT_PRNG_KSCTL[23:22] is not equal to u201900u2019). + * |[17] |KSERR |PRNG Access Key Store Error Flag + * | | |0 = No error. + * | | |1 = Access key store fail. + * @var CRPT_T::AES_FDBCK + * Offset: 0x50-0x5C AES Engine Output Feedback Data After Cryptographic Operation + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |FDBCK |AES Feedback Information + * | | |The feedback value is 128 bits in size. + * | | |The AES engine uses the data from CRPT_AES_FDBCKx as the data inputted to CRPT_AES_IVx for the next block in DMA cascade mode. + * | | |The AES engine outputs feedback information for IV in the next block operation + * | | |Software can use this feedback information to implement more than four DMA channels + * | | |Software can store that feedback value temporarily + * | | |After switching back, fill the stored feedback value to CRPT_AES_IVx in the same channel operation, and then continue the operation with the original setting. + * @var CRPT_T::AES_GCM_IVCNT + * Offset: 0x80-0x84 AES GCM IV Byte Count Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |CNT |AES GCM IV Byte Count + * | | |The bit length of IV is 64 bits for AES GCM mode + * | | |The CRPT_AES_GCM_IVCNT keeps the low weightbyte count of initial vector (i.e., len(IV)[34:3])of AES GCM mode and can be read and written. + * @var CRPT_T::AES_GCM_ACNT + * Offset: 0x88-0x8C AES GCM A Byte Count Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |CNT |AES GCM aByte Count + * | | |The bit length of A is 64 bits for AES GCM mode + * | | |The CRPT_AES_GCM_ACNT keeps the low weightbyte count of theadditional authenticated data (i.e., len(A)[34:3])of AES GCM mode and can be read and written. + * @var CRPT_T::AES_GCM_PCNT + * Offset: 0x90-0x94 AES GCM P Byte Count Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |CNT |AES GCM PByte Count + * | | |The bit length of Por Cis 39 bits for AES GCM mode + * | | |The CRPT_AES_GCM_PCNT0 keeps the low weightbyte count of theplaintextor ciphertext (i.e., len(P)[34:3] or len(C)[34:3])of AES GCM mode and can be read and written. + * |[60:32] |CNT |AES GCM P Byte Count + * | | |The bit length of Por C is 39 bits for AES GCM mode + * | | |The CRPT_AES_GCM_PCNT1 keeps the high weightbyte count of theplaintext or ciphertext (i.e., len(P)[38:35] or len(C)[38:35])of AES GCM mode and can be read and written. + * | | |The bit length of Por C is 64 bits for AES CCM mode + * | | |The CRPT_AES_GCM_PCNT1 keeps the high weightbyte count of theplaintext or ciphertext (i.e., len(P)[63:35] or len(C)[63:35])of AES CCM mode and can be read and written. + * @var CRPT_T::AES_FBADDR + * Offset: 0xA0 AES DMA Feedback Address Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |FBADDR |AES DMA Feedback Address + * | | |In DMA cascade mode, software can update DMA feedbackaddress register for automatically reading and writing feedback vaules via DMA.The FBADDR keeps the feedback address of the feedback data for the next cascade operation + * | | |Based on the feedback address, the AES accelerator can read thefeedback dataof the last cascade opeation from SRAM memory space and write thefeedback dataof the current cascade opeation to SRAM memory space + * | | |The start of feedback address should be located at word boundary + * | | |In other words, bit 1 and 0 of FBADDR are ignored. + * | | |FBADDR can be read and written. + * | | |In DMA mode, software can update the next CRPT_AES_FBADDR before triggering START. + * @var CRPT_T::AES_CTL + * Offset: 0x100 AES Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |START |AES Engine Start + * | | |0 = No effect. + * | | |1 = Start AES engine. BUSY flag will be set. + * | | |Note: This bit is always 0 when it read back. + * |[1] |STOP |AES Engine Stop + * | | |0 = No effect. + * | | |1 = Stop AES engine. + * | | |Note: This bit is always 0 when it read back. + * |[3:2] |KEYSZ |AES Key Size + * | | |This bit defines three different key size for AES operation. + * | | |2u2019b00 = 128 bits key. + * | | |2u2019b01 = 192 bits key. + * | | |2u2019b10 = 256 bits key. + * | | |2u2019b11 = Reserved. + * | | |If the AES accelerator is operating and the corresponding flag BUSY is 1, updating this register has no effect. + * | | |Note:When SM4EN=1, the key size of AESmust be 128. + * |[5] |DMALAST |AES Last Block + * | | |In DMA mode, this bit must be set as beginning the last DMA cascade round. + * | | |In Non-DMA mode, this bit must be set when feeding in the last block of data in ECB, CBC, CTR, OFB, and CFB mode, and feeding in the (last-1) block of data at CBC-CS1, CBC-CS2, and CBC-CS3 mode. + * | | |This bit is always 0 when it read back. Must be written again once START is triggered. + * |[6] |DMACSCAD |AES Engine DMA with Cascade Mode + * | | |0 = DMA cascade function Disabled. + * | | |1 = In DMA cascade mode, software can update DMA source address register, destination address register, and byte count register during a cascade operation, without finishing the accelerator operation. + * |[7] |DMAEN |AES Engine DMA Enable Bit + * | | |0 = AES DMA engine Disabled. + * | | |The AES engine operates in Non-DMA mode. The data need to be written in CRPT_AES_DATIN. + * | | |1 = AES_DMA engine Enabled. + * | | |The AES engine operates in DMA mode, and data movement from/to the engine is done by DMA logic. + * |[15:8] |OPMODE |AES Engine Operation Modes + * | | |0x00 = ECB (Electronic Codebook Mode) 0x01 = CBC (Cipher Block Chaining Mode). + * | | |0x02 = CFB (Cipher Feedback Mode). + * | | |0x03 = OFB (Output Feedback Mode). + * | | |0x04 = CTR (Counter Mode). + * | | |0x10 = CBC-CS1 (CBC Ciphertext-Stealing 1 Mode). + * | | |0x11 = CBC-CS2 (CBC Ciphertext-Stealing 2 Mode). + * | | |0x12 = CBC-CS3 (CBC Ciphertext-Stealing 3 Mode). + * | | |0x20 = GCM (Galois/Counter Mode). + * | | |0x21 = GHASH (Galois Hash Function). + * | | |0x22 = CCM (Counter with CBC-MAC Mode). + * |[16] |ENCRYPTO |AES Encryption/Decryption + * | | |0 = AES engine executes decryption operation. + * | | |1 = AES engine executes encryption operation. + * |[17] |SM4EN |SM4 Engine Enable + * | | |0 = Enable AES engine. + * | | |1 =Enable SM4 engine. + * |[20] |FBIN |Feedback Input to AES Via DMA Automatically + * | | |0 = Disable DMA automatical feedback input fucntion. + * | | |1 =Enable DMA automatical feedback input fucntion.when DMAEN = 1. + * |[21] |FBOUT |Feedback Output From AES Via DMA Automatically + * | | |0 = Disable DMA automatical feedback output fucntion. + * | | |1 =Enable DMA automatical feedback output fucntion when DMAEN = 1. + * |[22] |OUTSWAP |AES Engine Output Data Swap + * | | |0 = Keep the original order. + * | | |1 =The order that CPU reads data from the accelerator will be changed from {byte3, byte2, byte1, byte0} to {byte0, byte1, byte2, byte3}. + * |[23] |INSWAP |AES Engine Input Data Swap + * | | |0 = Keep the original order. + * | | |1 =The order that CPU feeds data to the accelerator will be changed from {byte3, byte2, byte1, byte0} to {byte0, byte1, byte2, byte3}. + * |[24] |KOUTSWAP |AES Engine Output Key, Initial Vector and Feedback Swap + * | | |0 = Keep the original order. + * | | |1 =The order that CPU readskey, initial vector and feeback from the accelerator will be changed from {byte3, byte2, byte1, byte0} to {byte0, byte1, byte2, byte3}. + * |[25] |KINSWAP |AES Engine Input Key and Initial Vector Swap + * | | |0 = Keep the original order. + * | | |1 =The order that CPU feeds key and initial vector to the accelerator will be changed from {byte3, byte2, byte1, byte0} to {byte0, byte1, byte2, byte3}. + * |[30:26] |KEYUNPRT |Unprotect Key + * | | |Writing 0 to CRPT_AES_CTL[31] and u201C10110u201D to CRPT_AES_CTL[30:26] is to unprotect theAES key. + * | | |The KEYUNPRT can be read and written + * | | |When it is written as the AES engine is operating, BUSY flag is 1, there would be no effect on KEYUNPRT. + * |[31] |KEYPRT |Protect Key + * | | |Read as a flag to reflect KEYPRT. + * | | |0 = No effect. + * | | |1 = Protect the content of the AES key from reading + * | | |The return value for reading CRPT_AES_KEYx is not the content of the registers CRPT_AES_KEYx + * | | |Once it is set, it can be cleared by asserting KEYUNPRT + * | | |And the key content would be cleared as well. + * @var CRPT_T::AES_STS + * Offset: 0x104 AES Engine Flag + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |BUSY |AES Engine Busy + * | | |0 = The AES engine is idle or finished. + * | | |1 = The AES engine is under processing. + * |[8] |INBUFEMPTY|AES Input Buffer Empty + * | | |0 = There are some data in input buffer waiting for the AES engine to process. + * | | |1 = AES input buffer is empty + * | | |Software needs to feed data to the AES engine + * | | |Otherwise, the AES engine will be pending to wait for input data. + * |[9] |INBUFFULL |AES Input Buffer Full Flag + * | | |0 = AES input buffer is not full. Software can feed the data into the AES engine. + * | | |1 = AES input buffer is full + * | | |Software cannot feed data to the AES engine + * | | |Otherwise, the flag INBUFERR will be set to 1. + * |[10] |INBUFERR |AES Input Buffer Error Flag + * | | |0 = No error. + * | | |1 = Error happens during feeding data to the AES engine. + * |[12] |CNTERR |CRPT_AES_CNT Setting Error + * | | |0 = No error in CRPT_AES_CNT setting. + * | | |1 = CRPT_AES_CNT is 0 or not a multiply of 16 in ECB, CBC, CFB, OFB, and CTR mode if DMAEN (CRPT_AES_CTL[7]) is enabled. + * |[16] |OUTBUFEMPTY|AES Out Buffer Empty + * | | |0 = AES output buffer is not empty. There are some valid data kept in output buffer. + * | | |1 = AES output buffer is empty + * | | |Software cannot get data from CRPT_AES_DATOUT + * | | |Otherwise, the flag OUTBUFERR will be set to 1 since the output buffer is empty. + * |[17] |OUTBUFFULL|AES Out Buffer Full Flag + * | | |0 = AES output buffer is not full. + * | | |1 = AES output buffer is full, and software needs to get data from CRPT_AES_DATOUT + * | | |Otherwise, the AES engine will be pending since the output buffer is full. + * |[18] |OUTBUFERR |AES Out Buffer Error Flag + * | | |0 = No error. + * | | |1 = Error happens during getting the result from AES engine. + * |[20] |BUSERR |AES DMA Access Bus Error Flag + * | | |0 = No error. + * | | |1 = Bus error will stop DMA operation and AES engine. + * |[21] |KSERR |AES Engine Access Key Store Error Flag + * | | |0 = No error. + * | | |1 = Access error will stop AES engine. + * @var CRPT_T::AES_DATIN + * Offset: 0x108 AES Engine Data Input Port Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |DATIN |AES Engine Input Port + * | | |CPU feeds data to AES engine through this port by checking CRPT_AES_STS. Feed data as INBUFFULL is 0. + * @var CRPT_T::AES_DATOUT + * Offset: 0x10C AES Engine Data Output Port Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |DATOUT |AES Engine Output Port + * | | |CPU gets results from the AES engine through this port by checking CRPT_AES_STS + * | | |Get data as OUTBUFEMPTY is 0. + * @var CRPT_T::AES_KEY + * Offset: 0x110-0x12C AES Key Word Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |KEY |CRPT_AES_KEYx + * | | |The KEY keeps the security key for AES operation. + * | | |x = 0, 1..7. + * | | |The security key for AES accelerator can be 128, 192, or 256 bits and four, six, or eight 32-bit registers are to store each security key. + * | | |{CRPT_AES_KEY3, CRPT_AES_KEY2, CRPT_AES_KEY1, CRPT_AES_KEY0} stores the 128-bit security key for AES operation. + * | | |{CRPT_AES_KEY5, CRPT_AES_KEY4, CRPT_AES_KEY3, CRPT_AES_KEY2, CRPT_AES_KEY1, CRPT_AES_KEY0} stores the 192-bit security key for AES operation. + * | | |{CRPT_AES_KEY7, CRPT_AES_KEY6, CRPT_AES_KEY5, CRPT_AES_KEY4, CRPT_AES_KEY3, CRPT_AES_KEY2, CRPT_AES_KEY1, CRPT_AES_KEY0} stores the 256-bit security key for AES operation. + * @var CRPT_T::AES_IV + * Offset: 0x130-0x13C AES Initial Vector Word Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |IV |AES Initial Vectors + * | | |x = 0, 1..3. + * | | |Four initial vectors (CRPT_AES_IV0, CRPT_AES_IV1, CRPT_AES_IV2, and CRPT_AES_IV3) are for AES operating in CBC, CFB, and OFB mode + * | | |Four registers (CRPT_AES_IV0, CRPT_AES_IV1, CRPT_AES_IV2, and CRPT_AES_IV3) act as Nonce counter when the AES engine is operating in CTR mode. + * @var CRPT_T::AES_SADDR + * Offset: 0x140 AES DMA Source Address Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |SADDR |AES DMA Source Address + * | | |The AES accelerator supports DMA function to transfer the plain text between SRAM memory space and embedded FIFO + * | | |The SADDR keeps the source address of the data buffer where the source text is stored + * | | |Based on the source address, the AES accelerator can read the plain text (encryption) / cipher text (descryption) from SRAM memory space and do AES operation + * | | |The start of source address should be located at word boundary + * | | |In other words, bit 1 and 0 of SADDR are ignored. + * | | |SADDR can be read and written + * | | |Writing to SADDR while the AES accelerator is operating doesnu2019t affect the current AES operation + * | | |But the value of SADDR will be updated later on + * | | |Consequently, software can prepare the DMA source address for the next AES operation. + * | | |In DMA mode, software can update the next CRPT_AES_SADDR before triggering START. + * | | |The value of CRPT_AES_SADDR and CRPT_AES_DADDR can be the same. + * @var CRPT_T::AES_DADDR + * Offset: 0x144 AES DMA Destination Address Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |DADDR |AES DMA Destination Address + * | | |The AES accelerator supports DMA function to transfer the cipher text between SRAM memory space and embedded FIFO + * | | |The DADDR keeps the destination address of the data buffer where the engine output text will be stored + * | | |Based on the destination address, the AES accelerator can write the cipher text (encryption) / plain text (decryption) back to SRAM memory space after the AES operation is finished + * | | |The start of destination address should be located at word boundary + * | | |In other words, bit 1 and 0 of DADDR are ignored. + * | | |DADDR can be read and written + * | | |Writing to DADDR while the AES accelerator is operating doesnu2019t affect the current AES operation + * | | |But the value of DADDR will be updated later on + * | | |Consequently, software can prepare the destination address for the next AES operation. + * | | |In DMA mode, software can update the next CRPT_AES_DADDR before triggering START. + * | | |The value of CRPT_AES_SADDR and CRPT_AES_DADDR can be the same. + * @var CRPT_T::AES_CNT + * Offset: 0x148 AES Byte Count Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |CNT |AES Byte Count + * | | |The CRPT_AES_CNT keeps the byte count of source text that is for the AES engine operating in DMA mode + * | | |The CRPT_AES_CNT is 32-bit and the maximum of byte count is 4G bytes. + * | | |CRPT_AES_CNT can be read and written + * | | |Writing to CRPT_AES_CNT while the AES accelerator is operating doesnu2019t affect the current AES operation + * | | |But the value of CRPT_AES_CNT will be updated later on + * | | |Consequently, software can prepare the byte count of data for the next AES operation. + * | | |According to CBC-CS1, CBC-CS2, and CBC-CS3 standard, the count of operation data must be more than 16 bytes + * | | |Operations that are qual or less than one block will output unexpected result. + * | | |In Non-DMA ECB, CBC, CFB, OFB, CTR, CCM and GCM mode, CRPT_AES_CNT must be set as byte count for the last block of data before feeding in the last block of data + * | | |In Non-DMA CBC-CS1, CBC-CS2, and CBC-CS3 mode, CRPT_AES_CNT must be set as byte count for the last two blocks of data before feeding in the last two blocks of data. + * | | |In AES GCM mode without DMA cascade fucntion, the value of CRPT_AES_CNT is equal to the total value of{CRPT_AES_GCM_IVCNT1, CRPT_AES_GCM_IVCNT0}, {CRPT_AES_GCM_ACNT1, CRPT_AES_GCM_ACNT0} and {CRPT_AES_GCM_PCNT1, CRPT_AES_GCM_PCNT0}. + * | | |In AES GCM mode with DMA cascade fucntion,the value of CRPT_AES_CNT represents the byte count of source text in this cascade function + * | | |Thus, the value of CRPT_AES_CNT is less than or equal to the total value of {CRPT_AES_GCM_IVCNT1, CRPT_AES_GCM_IVCNT0}, {CRPT_AES_GCM_ACNT1, CRPT_AES_GCM_ACNT0} and {CRPT_AES_GCM_PCNT1, CRPT_AES_GCM_PCNT0} and must be block alignment. + * | | |In AES CCM mode without DMA cascade fucntion, the value of CRPT_AES_CNT is equal to the total value of {CRPT_AES_GCM_ACNT1, CRPT_AES_GCM_ACNT0} and {CRPT_AES_GCM_PCNT1, CRPT_AES_GCM_PCNT0}. + * | | |In AES CCM mode with DMA cascade fucntion,the value of CRPT_AES_CNT represents the byte count of source text in this cascade function + * | | |Thus, the value of CRPT_AES_CNT is less than or equal to the total value of {CRPT_AES_GCM_ACNT1, CRPT_AES_GCM_ACNT0} and {CRPT_AES_GCM_PCNT1, CRPT_AES_GCM_PCNT0} and must be block alignment, except for the last block of plaintext or ciphertext. + * @var CRPT_T::HMAC_CTL + * Offset: 0x300 SHA/HMAC Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |START |SHA/HMAC Engine Start + * | | |0 = No effect. + * | | |1 = Start SHA/HMAC engine. BUSY flag will be set. + * | | |Note: This bit is always 0 when it read back. + * |[1] |STOP |SHA/HMAC Engine Stop + * | | |0 = No effect. + * | | |1 = Stop SHA/HMAC engine. + * | | |Note: This bit is always 0 when it read back. + * |[4] |DMAFIRST |SHA/HMAC First Blockin Cascadefunction + * | | |This bit must be set as feeding in first byte of data. + * |[5] |DMALAST |SHA/HMAC Last Block + * | | |This bit must be set as feeding in last byte of data. + * |[6] |DMACSCAD |SHA/HMAC Engine DMA with Cascade Mode + * | | |0 = DMA cascade function Disabled. + * | | |1 = In DMA cascade mode, software can update DMA source address register, destination address register, and byte count register during a cascade operation, without finishing the accelerator operation. + * |[7] |DMAEN |SHA/HMAC Engine DMA Enable Bit + * | | |0 = SHA/HMAC DMA engine Disabled. + * | | |SHA/HMAC engine operates in Non-DMA mode. The data need to be written in CRPT_HMAC_DATIN. + * | | |1 = SHA/HMAC DMA engine Enabled. + * | | |SHA/HMAC engine operates in DMA mode, and data movement from/to the engine is done by DMA logic. + * |[10:8] |OPMODE |SHA/HMAC Engine Operation Modes + * | | |0x0xx: SHA1-160 + * | | |0x100: SHA2-256 + * | | |0x101: SHA2-224 + * | | |0x110: SHA2-512 + * | | |0x111: SHA2-384 + * | | |Note: These bits can be read and written. But writing tothem wouldnu2019t take effect as BUSY is 1.. + * | | |Note:When SM3EN=1, SHA/HMAC only execute SM3-256. + * |[11] |HMACEN |HMAC_SHA Engine Operating Mode + * | | |0 = Execute SHA function. + * | | |1 = Execute HMAC function. + * |[13] |SM3EN |SM3 Engine Enable Bit + * | | |0 = Execute other function. + * | | |1 = Execute SM3 function. + * |[20] |FBIN |Feedback Input to SHA/HMAC Via DMA Automatically + * | | |0 = Disable DMA automatical feedback input fucntion.. + * | | |1 = Enable DMA automatical feedback input fucntion when DMAEN = 1. + * |[21] |FBOUT |Feedback Output From SHA/HMAC Via DMA Automatically + * | | |0 = Disable DMA automatical feedback output fucntion.. + * | | |1 = Enable DMA automatical feedback output fucntion when DMAEN = 1. + * |[22] |OUTSWAP |SHA/HMAC Engine Output Data Swap + * | | |0 = Keep the original order. + * | | |1 = The order that CPU feeds data to the accelerator will be changed from {byte3, byte2, byte1, byte0} to {byte0, byte1, byte2, byte3}. + * |[23] |INSWAP |SHA/HMAC Engine Input Data Swap + * | | |0 = Keep the original order. + * | | |1 = The order that CPU feeds data to the accelerator will be changed from {byte3, byte2, byte1, byte0} to {byte0, byte1, byte2, byte3}. + * @var CRPT_T::HMAC_STS + * Offset: 0x304 SHA/HMAC Status Flag + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |BUSY |SHA/HMAC Engine Busy + * | | |0 = SHA/HMAC engine is idle or finished. + * | | |1 = SHA/HMAC engine is busy. + * |[1] |DMABUSY |SHA/HMAC Engine DMA Busy Flag + * | | |0 = SHA/HMAC DMA engine is idle or finished. + * | | |1 = SHA/HMAC DMA engine is busy. + * |[8] |DMAERR |SHA/HMAC Engine DMA Error Flag + * | | |0 = Show the SHA/HMAC engine access normal. + * | | |1 = Show the SHA/HMAC engine access error. + * |[9] |KSERR |HMAC Engine Access Key Store Error Flag + * | | |0 = No error. + * | | |1 = Access error will stop HMAC engine. + * |[16] |DATINREQ |SHA/HMAC Non-dMA Mode Data Input Request + * | | |0 = No effect. + * | | |1 = Request SHA/HMAC Non-DMA mode data input. + * @var CRPT_T::HMAC_DGST + * Offset: 0x308-0x344 SHA/HMAC Output Feedback Data + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |DGST |SHA/HMACOutput Feedback Data Output Register + * | | |For SHA-160, the digest is stored in CRPT_HMAC_DGST0 ~ CRPT_HMAC_DGST4. + * | | |For SHA-224, the digest is stored in CRPT_HMAC_DGST0 ~ CRPT_HMAC_DGST6. + * | | |For SHA-256, the digest is stored in CRPT_HMAC_DGST0 ~ CRPT_HMAC_DGST7. + * | | |For SHA-384, the digest is stored in CRPT_HMAC_DGST0 ~ CRPT_HMAC_DGST11. + * | | |For SHA-512, the digest is stored in CRPT_HMAC_DGST0 ~ CRPT_HMAC_DGST15. + * @var CRPT_T::HMAC_KEYCNT + * Offset: 0x348 SHA/HMAC Key Byte Count Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |KEYCNT |SHA/HMAC Key Byte Count + * | | |The CRPT_HMAC_KEYCNT keeps the byte count of key that SHA/HMAC engine operates + * | | |The register is 32-bit and the maximum byte count is 4G bytes + * | | |It can be read and written. + * | | |Writing to the register CRPT_HMAC_KEYCNT as the SHA/HMAC accelerator operating doesnu2019t affect the current SHA/HMAC operation + * | | |But the value of CRPT_HMAC_KEYCNT will be updated later on + * | | |Consequently, software can prepare the key count for the next SHA/HMAC operation. + * @var CRPT_T::HMAC_SADDR + * Offset: 0x34C SHA/HMAC DMA Source Address Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |SADDR |SHA/HMAC DMA Source Address + * | | |The SHA/HMAC accelerator supports DMA function to transfer the plain text between SRAM memory space and embedded FIFO + * | | |The CRPT_HMAC_SADDR keeps the source address of the data buffer where the source text is stored + * | | |Based on the source address, the SHA/HMAC accelerator can read the plain text from SRAM memory space and do SHA/HMAC operation + * | | |The start of source address should be located at word boundary + * | | |In other words, bit 1 and 0 of CRPT_HMAC_SADDR are ignored. + * | | |CRPT_HMAC_SADDR can be read and written + * | | |Writing to CRPT_HMAC_SADDR while the SHA/HMAC accelerator is operating doesnu2019t affect the current SHA/HMAC operation + * | | |But the value of CRPT_HMAC_SADDR will be updated later on + * | | |Consequently, software can prepare the DMA source address for the next SHA/HMAC operation. + * | | |In DMA mode, software can update the next CRPT_HMAC_SADDR before triggering START. + * | | |CRPT_HMAC_SADDR and CRPT_HMAC_DADDR can be the same in the value. + * @var CRPT_T::HMAC_DMACNT + * Offset: 0x350 SHA/HMAC Byte Count Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |DMACNT |SHA/HMAC Operation Byte Count + * | | |The CRPT_HMAC_DMACNT keeps the byte count of source text that is for the SHA/HMAC engine operating in DMA mode + * | | |The CRPT_HMAC_DMACNT is 32-bit and the maximum of byte count is 4G bytes. + * | | |CRPT_HMAC_DMACNT can be read and written + * | | |Writing to CRPT_HMAC_DMACNT while the SHA/HMAC accelerator is operating doesnu2019t affect the current SHA/HMAC operation + * | | |But the value of CRPT_HMAC_DMACNT will be updated later on + * | | |Consequently, software can prepare the byte count of data for the next SHA/HMAC operation. + * | | |In Non-DMA mode, CRPT_HMAC_DMACNT must be set as the byte count of the last block before feeding in the last block of data. + * @var CRPT_T::HMAC_DATIN + * Offset: 0x354 SHA/HMAC Engine Non-dMA Mode Data Input Port Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |DATIN |SHA/HMAC Engine Input Port + * | | |CPU feeds data to SHA/HMAC engine through this port by checking CRPT_HMAC_STS + * | | |Feed data as DATINREQ is 1. + * @var CRPT_T::HMAC_FDBCK + * Offset: 0x358-0x42C SHA/HMAC Output Feedback Data After SHA/HMAC Operation + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |FDBCK |SHA/HMAC Feedback Information + * | | |The feedback value is 1728 bits in size for SHA1/2. + * | | |The SHA/HMAC engine uses the data from CRPT_HMAC_FDBCKx as the data inputted to CRPT_HMAC_FDBCKx for the next block in DMA cascade mode. + * | | |The SHA/HMAC engine outputs feedback information for initial setting in the next block operation + * | | |Software can store that feedback value temporarily + * | | |After switching back, fill the stored feedback value to CRPT_HMAC_FDBCKx in the same operation, and then continue the operation with the original setting. + * @var CRPT_T::HMAC_FBADDR + * Offset: 0x4FC SHA/HMAC DMA Feedback Address Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |FBADDR |SHA/HMAC DMA Feedback Address + * | | |In DMA cascade mode, software can update DMA feedbackaddress register for automatically reading and writing feedback vaules via DMA.The FBADDR keeps the feedback address of the feedback data for the next cascade operation + * | | |Based on the feedback address, the SHA/HMAC accelerator can read thefeedback dataof the last cascade opeation from SRAM memory space and write thefeedback dataof the current cascade opeation to SRAM memory space + * | | |The start of feedback address should be located at word boundary + * | | |In other words, bit 1 and 0 of FBADDR are ignored. + * | | |FBADDR can be read and written. + * | | |In DMA mode, software can update the next CRPT_HMAC_FBADDR before triggering START. + * @var CRPT_T::ECC_CTL + * Offset: 0x800 ECC Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |START |ECC Accelerator Start + * | | |0 = No effect. + * | | |1 = Start ECC accelerator. BUSY flag will be set. + * | | |This bit is always 0 when it read back. + * | | |ECC accelerator will ignore this START signal when BUSY flag is 1. + * |[1] |STOP |ECC Accelerator Stop + * | | |0 = No effect. + * | | |1 = Abort ECC accelerator and make it into idle state. + * | | |This bit is always 0 when it read back. + * | | |Remember to clear ECC interrupt flag after stopping ECC accelerator. + * |[3] |PFA2C |Primg Field Adder with 2Cycles + * | | |0 = cost1 cycle . + * | | |1 = cost 2 cycles. + * |[4] |ECDSAS |Generate S in ECDSA Signature Generation + * | | |0 = No effect. + * | | |1 = Formula for generating S. + * | | |POINTX1 = ((POINTX2 * POINTY1 + POINTY2 ) / POINTX1) % CURVEN. + * |[5] |ECDSAR |Generate R in ECDSA Signature Generation + * | | |0 = No effect. + * | | |1 = Formula for generating R. + * | | |(POINTX1, POINTY1) = SCALARK * (POINTX1, POINTY1). + * |[7] |DMAEN |ECC Accelerator DMA Enable Bit + * | | |0 = ECC DMA engine Disabled. + * | | |1 = ECC DMA engine Enabled. + * | | |Only when START and DMAEN are 1, ECC DMA engine will be active + * |[8] |FSEL |Field Selection + * | | |0 = Binary Field (GF(2m )). + * | | |1 = Prime Field (GF(p)). + * |[10:9] |ECCOP |Point Operation for BF and PF + * | | |00 = Point multiplication :. + * | | |(POINTX1, POINTY1) = SCALARK * (POINTX1, POINTY1). + * | | |01 = Modulus operation : choose by MODOP (CRPT_ECC_CTL[12:11]). + * | | |10 = Point addition :. + * | | |(POINTX1, POINTY1) = (POINTX1, POINTY1) +. + * | | |(POINTX2, POINTY2) + * | | |11 = Point doubling :. + * | | |(POINTX1, POINTY1) = 2 * (POINTX1, POINTY1). + * | | |Besides above three input data, point operations still need the parameters of elliptic curve (CURVEA, CURVEB, CURVEN and CURVEM) as shown in Figure 6.27-11 + * |[12:11] |MODOP |Modulus Operation for PF + * | | |00 = Division :. + * | | |POINTX1 = (POINTY1 / POINTX1) % CURVEN. + * | | |01 = Multiplication :. + * | | |POINTX1 = (POINTX1 * POINTY1) % CURVEN. + * | | |10 = Addition :. + * | | |POINTX1 = (POINTX1 + POINTY1) % CURVEN. + * | | |11 = Subtraction :. + * | | |POINTX1 = (POINTX1 - POINTY1) % CURVEN. + * | | |MODOP is active only when ECCOP = 01. + * |[13] |CSEL |Curve Selection + * | | |0 = NISTsuggested curve. + * | | |1 = Montgomery curve. + * |[14] |SCAP |Side-channel Attack Protection + * | | |0 = Full speed without side-channel protection. + * | | |1 = Less speed with side-channel protection. + * |[15] |SBM |Secure-boot Mode + * | | |0 = (POINTX1,POINTY1)from user data. + * | | |1 = (POINTX1,POINTY1)from secure boot key. + * |[16] |LDP1 |The Control Signal of RegisterPOINTX1and POINTY1for the xand Y Coordinate of the First Point + * | | |0 = The register for POINTX1 and POINTY1 is not modified by DMA or user. + * | | |1 = The register for POINTX1 and POINTY1 is modified by DMA or user. + * |[17] |LDP2 |The Control Signal of Register POINTX2and POINTY2for the xand Y Coordinate of the Second Point + * | | |0 = The register for POINTX2 and POINTY2 is not modified by DMA or user. + * | | |1 = The register for POINTX2 and POINTY2 is modified by DMA or user. + * |[18] |LDA |The Control Signal of Register for the Parameter CURVEA of Elliptic Curve + * | | |0 = The register for CURVEA is not modified by DMA or user. + * | | |1 = The register for CURVEA is modified by DMA or user. + * |[19] |LDB |The Control Signal of Register for the Parameter CURVEB of Elliptic Curve + * | | |0 = The register for CURVEB is not modified by DMA or user. + * | | |1 = The register for CURVEB is modified by DMA or user. + * |[20] |LDN |The Control Signal of Register for the Parameter CURVEN of Elliptic Curve + * | | |0 = The register for CURVEN is not modified by DMA or user. + * | | |1 = The register for CURVEN is modified by DMA or user. + * |[21] |LDK |The Control Signal of Register for SCALARK + * | | |0 = The register for SCALARK is not modified by DMA or user. + * | | |1 = The register for SCALARK is modified by DMA or user. + * |[31:22] |CURVEM |The key length of elliptic curve. + * @var CRPT_T::ECC_STS + * Offset: 0x804 ECC Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |BUSY |ECC Accelerator Busy Flag + * | | |0 = The ECC accelerator is idle or finished. + * | | |1 = The ECC accelerator is under processing and protects all registers. + * | | |Remember to clear ECC interrupt flag after ECC accelerator finished + * |[1] |DMABUSY |ECC DMA Busy Flag + * | | |0 = ECC DMA is idle or finished. + * | | |1 = ECC DMA is busy. + * |[16] |BUSERR |ECC DMA Access Bus Error Flag + * | | |0 = No error. + * | | |1 = Bus error will stop DMA operation and ECC accelerator.. + * |[17] |KSERR |ECC Engine Access Key Store Error Flag + * | | |0 = No error. + * | | |1 = Access error will stop ECC engine. + * @var CRPT_T::ECC_X1 + * Offset: 0x808-0x84C ECC the X-coordinate Word of the First Point + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |POINTX1 |ECC the X-coordinate Value of the First Point + * | | |For B-163 or K-163, POINTX1 is stored in CRPT_ECC_X1_00~CRPT_ECC_X1_05 + * | | |For B-233 or K-233, POINTX1 is stored in CRPT_ECC_X1_00~CRPT_ECC_X1_07 + * | | |For B-283 or K-283, POINTX1 is stored in CRPT_ECC_X1_00~CRPT_ECC_X1_08 + * | | |For B-409 or K-409, POINTX1 is stored in CRPT_ECC_X1_00~CRPT_ECC_X1_12 + * | | |For B-571 or K-571, POINTX1 is stored in CRPT_ECC_X1_00~CRPT_ECC_X1_17 + * | | |For P-192, POINTX1 is stored in CRPT_ECC_X1_00~CRPT_ECC_X1_05 + * | | |For P-224, POINTX1 is stored in CRPT_ECC_X1_00~CRPT_ECC_X1_06 + * | | |For P-256, POINTX1 is stored in CRPT_ECC_X1_00~CRPT_ECC_X1_07 + * | | |For P-384, POINTX1 is stored in CRPT_ECC_X1_00~CRPT_ECC_X1_11 + * | | |For P-521, POINTX1 is stored in CRPT_ECC_X1_00~CRPT_ECC_X1_16 + * @var CRPT_T::ECC_Y1 + * Offset: 0x850-0x894 ECC the Y-coordinate Word of the First Point + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |POINTY1 |ECC the Y-coordinate Value of the First Point + * | | |For B-163 or K-163, POINTY1 is stored in CRPT_ECC_Y1_00~CRPT_ECC_Y1_05 + * | | |For B-233 or K-233, POINTY1 is stored in CRPT_ECC_Y1_00~CRPT_ECC_Y1_07 + * | | |For B-283 or K-283, POINTY1 is stored in CRPT_ECC_Y1_00~CRPT_ECC_Y1_08 + * | | |For B-409 or K-409, POINTY1 is stored in CRPT_ECC_Y1_00~CRPT_ECC_Y1_12 + * | | |For B-571 or K-571, POINTY1 is stored in CRPT_ECC_Y1_00~CRPT_ECC_Y1_17 + * | | |For P-192, POINTY1 is stored in CRPT_ECC_Y1_00~CRPT_ECC_Y1_05 + * | | |For P-224, POINTY1 is stored in CRPT_ECC_Y1_00~CRPT_ECC_Y1_06 + * | | |For P-256, POINTY1 is stored in CRPT_ECC_Y1_00~CRPT_ECC_Y1_07 + * | | |For P-384, POINTY1 is stored in CRPT_ECC_Y1_00~CRPT_ECC_Y1_11 + * | | |For P-521, POINTY1 is stored in CRPT_ECC_Y1_00~CRPT_ECC_Y1_16 + * @var CRPT_T::ECC_X2 + * Offset: 0x898-0x8DC ECC the X-coordinate Word of the Second Point + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |POINTX2 |ECC the X-coordinate Value of the Second Point + * | | |For B-163 or K-163, POINTX2 is stored in CRPT_ECC_X2_00~CRPT_ECC_X2_05 + * | | |For B-233 or K-233, POINTX2 is stored in CRPT_ECC_X2_00~CRPT_ECC_X2_07 + * | | |For B-283 or K-283, POINTX2 is stored in CRPT_ECC_X2_00~CRPT_ECC_X2_08 + * | | |For B-409 or K-409, POINTX2 is stored in CRPT_ECC_X2_00~CRPT_ECC_X2_12 + * | | |For B-571 or K-571, POINTX2 is stored in CRPT_ECC_X2_00~CRPT_ECC_X2_17 + * | | |For P-192, POINTX2 is stored in CRPT_ECC_X2_00~CRPT_ECC_X2_05 + * | | |For P-224, POINTX2 is stored in CRPT_ECC_X2_00~CRPT_ECC_X2_06 + * | | |For P-256, POINTX2 is stored in CRPT_ECC_X2_00~CRPT_ECC_X2_07 + * | | |For P-384, POINTX2 is stored in CRPT_ECC_X2_00~CRPT_ECC_X2_11 + * | | |For P-521, POINTX2 is stored in CRPT_ECC_X2_00~CRPT_ECC_X2_16 + * @var CRPT_T::ECC_Y2 + * Offset: 0x8E0-0x924 ECC the Y-coordinate Word of the Second Point + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |POINTY2 |ECC the Y-coordinate Value of the Second Point + * | | |For B-163 or K-163, POINTY2 is stored in CRPT_ECC_Y2_00~CRPT_ECC_Y2_05 + * | | |For B-233 or K-233, POINTY2 is stored in CRPT_ECC_Y2_00~CRPT_ECC_Y2_07 + * | | |For B-283 or K-283, POINTY2 is stored in CRPT_ECC_Y2_00~CRPT_ECC_Y2_08 + * | | |For B-409 or K-409, POINTY2 is stored in CRPT_ECC_Y2_00~CRPT_ECC_Y2_12 + * | | |For B-571 or K-571, POINTY2 is stored in CRPT_ECC_Y2_00~CRPT_ECC_Y2_17 + * | | |For P-192, POINTY2 is stored in CRPT_ECC_Y2_00~CRPT_ECC_Y2_05 + * | | |For P-224, POINTY2 is stored in CRPT_ECC_Y2_00~CRPT_ECC_Y2_06 + * | | |For P-256, POINTY2 is stored in CRPT_ECC_Y2_00~CRPT_ECC_Y2_07 + * | | |For P-384, POINTY2 is stored in CRPT_ECC_Y2_00~CRPT_ECC_Y2_11 + * | | |For P-521, POINTY2 is stored in CRPT_ECC_Y2_00~CRPT_ECC_Y2_16 + * @var CRPT_T::ECC_A + * Offset: 0x928-0x96C ECC the Parameter CURVEA Word of Elliptic Curve + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |CURVEA |ECC the Parameter CURVEA Value of Elliptic Curve + * | | |The formula of elliptic curve is y2=x3+CURVEA*x+CURVEB in GF(p) and y2+x*y=x3+CURVEA*x2+CURVEB in GF(2m). + * | | |For B-163 or K-163, CURVEA is stored in CRPT_ECC_A_00~CRPT_ECC_A_05 + * | | |For B-233 or K-233, CURVEA is stored in CRPT_ECC_A_00~CRPT_ECC_A_07 + * | | |For B-283 or K-283, CURVEA is stored in CRPT_ECC_A_00~CRPT_ECC_A_08 + * | | |For B-409 or K-409, CURVEA is stored in CRPT_ECC_A_00~CRPT_ECC_A_12 + * | | |For B-571 or K-571, CURVEA is stored in CRPT_ECC_A_00~CRPT_ECC_A_17 + * | | |For P-192, CURVEA is stored in CRPT_ECC_A_00~CRPT_ECC_A_05 + * | | |For P-224, CURVEA is stored in CRPT_ECC_A_00~CRPT_ECC_A_06 + * | | |For P-256, CURVEA is stored in CRPT_ECC_A_00~CRPT_ECC_A_07 + * | | |For P-384, CURVEA is stored in CRPT_ECC_A_00~CRPT_ECC_A_11 + * | | |For P-521, CURVEA is stored in CRPT_ECC_A_00~CRPT_ECC_A_16 + * @var CRPT_T::ECC_B + * Offset: 0x970-0x9B4 ECC the Parameter CURVEB Word of Elliptic Curve + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |CURVEB |ECC the Parameter CURVEB Value of Elliptic Curve + * | | |The formula of elliptic curve is y2=x3+CURVEA*x+CURVEB in GF(p) and y2+x*y=x3+CURVEA*x2+CURVEB in GF(2m). + * | | |For B-163 or K-163, CURVEB is stored in CRPT_ECC_B_00~CRPT_ECC_B_05 + * | | |For B-233 or K-233, CURVEB is stored in CRPT_ECC_B_00~CRPT_ECC_B_07 + * | | |For B-283 or K-283, CURVEB is stored in CRPT_ECC_B_00~CRPT_ECC_B_08 + * | | |For B-409 or K-409, CURVEB is stored in CRPT_ECC_B_00~CRPT_ECC_B_12 + * | | |For B-521 or K-521, CURVEB is stored in CRPT_ECC_B_00~CRPT_ECC_B_17 + * | | |For P-192, CURVEB is stored in CRPT_ECC_B_00~CRPT_ECC_B_05 + * | | |For P-224, CURVEB is stored in CRPT_ECC_B_00~CRPT_ECC_B_06 + * | | |For P-256, CURVEB is stored in CRPT_ECC_B_00~CRPT_ECC_B_07 + * | | |For P-384, CURVEB is stored in CRPT_ECC_B_00~CRPT_ECC_B_11 + * | | |For P-521, CURVEB is stored in CRPT_ECC_B_00~CRPT_ECC_B_16 + * @var CRPT_T::ECC_N + * Offset: 0x9B8-0x9FC ECC the Parameter CURVEN Word of Elliptic Curve + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |CURVEN |ECC the Parameter CURVEN Value of Elliptic Curve + * | | |In GF(p), CURVEN is the prime p. + * | | |In GF(2m), CURVEN is the irreducible polynomial. + * | | |For B-163 or K-163, CURVEN is stored in CRYPTO_ECC_N_00~CRYPTO_ECC_N_05 + * | | |For B-233 or K-233, CURVEN is stored in CRYPTO_ECC_N_00~CRYPTO_ECC_N_07 + * | | |For B-283 or K-283, CURVEN is stored in CRYPTO_ECC_N_00~CRYPTO_ECC_N_08 + * | | |For B-409 or K-409, CURVEN is stored in CRYPTO_ECC_N_00~CRYPTO_ECC_N_12 + * | | |For B-571 or K-571, CURVEN is stored in CRYPTO_ECC_N_00~CRYPTO_ECC_N_17 + * | | |For P-192, CURVEN is stored in CRYPTO_ECC_N_00~CRYPTO_ECC_N_05 + * | | |For P-224, CURVEN is stored in CRYPTO_ECC_N_00~CRYPTO_ECC_N_06 + * | | |For P-256, CURVEN is stored in CRYPTO_ECC_N_00~CRYPTO_ECC_N_07 + * | | |For P-384, CURVEN is stored in CRYPTO_ECC_N_00~CRYPTO_ECC_N_11 + * | | |For P-521, CURVEN is stored in CRYPTO_ECC_N_00~CRYPTO_ECC_N_16 + * @var CRPT_T::ECC_K + * Offset: 0xA00-0xA44 ECC the Scalar SCALARK Word of Point Multiplication + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |SCALARK |ECC the Scalar SCALARK Value of Point Multiplication + * | | |Because the SCALARK usually stores the private key, ECC accelerator do not allow to read the register SCALARK. + * | | |For B-163 or K-163, SCALARK is stored in CRYPTO_ECC_K_00~CRYPTO_ECC_K_05 + * | | |For B-233 or K-233, SCALARK is stored in CRYPTO_ECC_K_00~CRYPTO_ECC_K_07 + * | | |For B-283 or K-283, SCALARK is stored in CRYPTO_ECC_K_00~CRYPTO_ECC_K_08 + * | | |For B-409 or K-409, SCALARK is stored in CRYPTO_ECC_K_00~CRYPTO_ECC_K_12 + * | | |For B-571 or K-571, SCALARK is stored in CRYPTO_ECC_K_00~CRYPTO_ECC_K_17 + * | | |For P-192, SCALARK is stored in CRYPTO_ECC_K_00~CRYPTO_ECC_K_05 + * | | |For P-224, SCALARK is stored in CRYPTO_ECC_K_00~CRYPTO_ECC_K_06 + * | | |For P-256, SCALARK is stored in CRYPTO_ECC_K_00~CRYPTO_ECC_K_07 + * | | |For P-384, SCALARK is stored in CRYPTO_ECC_K_00~CRYPTO_ECC_K_11 + * | | |For P-521, SCALARK is stored in CRYPTO_ECC_K_00~CRYPTO_ECC_K_16 + * @var CRPT_T::ECC_SADDR + * Offset: 0xA48 ECC DMA Source Address Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |SADDR |ECC DMA Source Address + * | | |The ECC accelerator supports DMA function to transfer the DATA and PARAMETER between SRAM memory space and ECC accelerator. + * | | |The SADDR keeps the source address of the data buffer where the source text is stored. Based on the source address, + * | | |the ECC accelerator can read the DATA and PARAMETER from SRAM memory space and do ECC operation. + * | | |The start of source address should be located at word boundary. That is, bit 1 and 0 of SADDR are ignored. + * | | |SADDR can be read and written. In DMA mode, software must update the CRYPTO_ECC_SADDR before triggering START. + * @var CRPT_T::ECC_DADDR + * Offset: 0xA4C ECC DMA Destination Address Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |DADDR |ECC DMA Destination Address + * | | |The ECC accelerator supports DMA function to transfer the DATA and PARAMETER between SRAM memory and ECC accelerator + * | | |The DADDR keeps the destination address of the data buffer where output data of ECC engine will be stored + * | | |Based on the destination address, the ECC accelerator can write the result data back to SRAM memory space after the ECC operation is finished + * | | |The start of destination address should be located at word boundary + * | | |That is, bit 1 and 0 of DADDR are ignored + * | | |DADDR can be read and written + * | | |In DMA mode, software must update the CRPT_ECC_DADDR before triggering START + * @var CRPT_T::ECC_STARTREG + * Offset: 0xA50 ECC Starting Address of Updated Registers + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |STARTREG |ECC Starting Address of Updated Registers + * | | |The address of the updated registers that DMA feeds the first data or parameter to ECC engine + * | | |When ECC engine is active, ECC accelerator does not allow users to modify STARTREG, for example, to update input data from register CRPT_ECC POINTX1 + * | | |Thus, the value of STARTREG is 0x808. + * @var CRPT_T::ECC_WORDCNT + * Offset: 0xA54 ECC DMA Word Count + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |WORDCNT |ECC DMA Word Count + * | | |The CRPT_ECC_WORDCNT keeps the word count of source data that is for the required input data of ECC accelerator with various operations in DMA mode + * | | |Although CRPT_ECC_WORDCNT is 32-bit, the maximum of word count in ECC accelerator is 144words + * | | |CRPT_ECC_WORDCNT can be read and written + * @var CRPT_T::RSA_CTL + * Offset: 0xB00 RSA Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |START |RSA Accelerator Start + * | | |0 = No effect. + * | | |1 = Start RSAaccelerator. BUSY flag will be set. + * | | |This bit is always 0 when it read back. + * | | |RSAaccelerator will ignore this START signal when BUSY flag is 1. + * |[1] |STOP |RSA Accelerator Stop + * | | |0 = No effect. + * | | |1 = Abort RSA accelerator and make it into initialstate. + * | | |This bit is always 0 when it read back. + * | | |Remember to clear RSA interrupt flag after stopping RSA accelerator. + * |[2] |CRT |CRT Enable Control + * | | |0 = CRT Disabled. + * | | |1 = CRT Enabled. + * | | |CRT is only used in decryption with key length 2048, 3072,4096 bits. + * |[3] |CRTBYP |CRT BypassEnable Control + * | | |0 = CRT Bypass Disabled. + * | | |1 = CRT Bypass Enabled. + * | | |CRT bypass is only used in CRT decryption with the same key. + * | | |Note: If users want to decrypt repeatedly with the same key, they can execute CRT bypass mode after the first time CRT decryption(means the second time to the latest time), but they canu2019t set CRTBYP to 1 in non-CRT mode. + * |[5:4] |KEYLENG |The Key Length of RSA Operation + * | | |00 = 1024bits. + * | | |01 = 2048bits. + * | | |10 = 3072bits. + * | | |11 = 4096bits. + * |[8] |SCAP |Side Channel Attack Protection Enable Control + * | | |0 = Side Channel Attack Protection Disabled. + * | | |1 = Side Channel Attack Protection Enabled. + * @var CRPT_T::RSA_STS + * Offset: 0xB04 RSA Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |BUSY |RSA Accelerator Busy Flag + * | | |0 = The RSA accelerator is idle or finished. + * | | |1 = The RSA accelerator is under processing and protects all registers. + * | | |Remember to clear RSA interrupt flag after RSA accelerator finished + * |[1] |DMABUSY |RSA DMA Busy Flag + * | | |0 = RSA DMA is idle or finished. + * | | |1 = RSA DMA is busy. + * |[16] |BUSERR |RSA DMA Access Bus Error Flag + * | | |0 = No error. + * | | |1 = Bus error will stop DMA operation and RSA accelerator. + * |[17] |CTLERR |RSA Control Register Error Flag + * | | |0 = No error. + * | | |1 = RSA control error. RSA will not start in the unsupported situation. + * | | |Note: If user use the control error condition, but donu2019t set START(CRPT_RSA_CTL[0]) to 1, CTLERR still be set to 1. + * |[18] |KSERR |RSA Engine Access Key Store Error Flag + * | | |0 = No error. + * | | |1 = Access error will stop RSA engine. + * @var CRPT_T::RSA_SADDR + * Offset: 0xB08-0xB18 RSA DMA Source Address Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |SADDR0 |RSA DMA Source Address Register0 + * | | |The RSA accelerator supports DMA function to transfer the DATA and PARAMETER between SRAM memory space and RSA accelarator. + * | | |This register is stored the address of RSA the Base of Exponentiation (M,N,E,p,q). + * @var CRPT_T::RSA_DADDR + * Offset: 0xB1C RSA DMA Destination Address Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |DADDR |RSA DMA Destination Address Register + * | | |The RSA accelerator supports DMA function to transfer the DATA and PARAMETER between SRAM memory space and RSA accelarator. + * | | |This register is stored the address of RSA DMA Destination Address Register (Ans). + * @var CRPT_T::RSA_MADDR + * Offset: 0xB20-0xB38 RSA DMA Middle Address Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |MADDR |RSA DMA Middle Address Register + * | | |The RSA accelerator supports DMA function to transfer the DATA and PARAMETER between SRAM memory space and RSA accelarator. + * | | |This register is stored the address of RSA CRT the Temporary Value (Cp -> Mp -> Sp, Cq -> Mq -> Sq, Dp, Dq, Rp, Rq, E'). + * @var CRPT_T::PRNG_KSCTL + * Offset: 0xF00 PRNG Key Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[4:0] |NUM |Write Key Number + * | | |The key number is sent to key store + * | | |Note: Only for destination Is OTP of Key Store. + * |[16] |TRUST |Write Key Trust Selection Bit + * | | |0 = Set written key as the non-secure key. + * | | |1 = Set written key as the secure key. + * |[18] |PRIV |Privilege Key Selection Bit + * | | |0 = Set key as the non-privilege key. + * | | |1 = Set key as the privilege key. + * |[19] |ECDH |ECDH Control Bit + * | | |0 =reserved. + * | | |1 = key is written to key store and used in ECDH. + * | | |Note:When ECDH was set to u20181u2019, 1 + * | | |PRNG seed must from TRNG and key is must written to the SRAM of key store (WSDST, CRPT_PRNG_KSCTL[23:22] must set to u201800u2019) + * | | |Otherwise, KCTLERRwill become u20181u2019(CRPT_PRNG_KSSTS[16]) + * | | |2 + * | | |Key must in the interval [1, n-1] (the parameter n is from ECC) + * | | |The value of n canu2019t be 0 or 1, otherwise, PRNG will always keep busy. + * |[20] |ECDSA |ECDSA Control Bit + * | | |0 =reserved. + * | | |1 = key is written to key store and used in ECDSA. + * | | |Note:When ECDSA was set to u20181u2019, 1 + * | | |PRNG seed must from TRNGand key is must written to the SRAM of key store (WSDST, CRPT_PRNG_KSCTL[23:22] must set to u201800u2019) + * | | |Otherwise, KCTLERRwill become u20181u2019(CRPT_PRNG_KSSTS[16]) + * | | |2.Key must in the interval [1, n-1] (the parameter n is from ECC) + * | | |The value of n canu2019t be 0 or 1, otherwise, PRNG will always keep busy. + * |[21] |WDST |Write Key Destination + * | | |0 = key is written to registers CRPT_PRNG_KEYx. + * | | |1 = key is written to key store. + * |[23:22] |WSDST |Write Key Store Destination + * | | |00 = key is written to the SRAM of key store. + * | | |10 = key is written to the OTP of key store. + * | | |Others = reserved. + * |[26:24] |OWNER |Write Key Owner Selection Bits + * | | |000 = Only for AES used. + * | | |001 = Only for HMAC engine used. + * | | |100 = Only for ECC engine used. + * | | |101 = Only for CPU engine use. + * | | |Others = reserved. + * @var CRPT_T::PRNG_KSSTS + * Offset: 0xF04 PRNG Key Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[4:0] |NUM |Key Number + * | | |The key number is generated by key store + * |[16] |KCTLERR |PRNG Key Control Register Error Flag + * | | |0 = No error. + * | | |1 = PRNG key control error + * | | |When PRNG execute ECDSA or ECDH, but PRNG seed not from TRNG or key is not written to the SRAM of key store (WSDST,CRPT_PRNG_KSCTL[23:22] is not equal to u201900u2019). + * @var CRPT_T::AES_KSCTL + * Offset: 0xF10 AES Key Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[4:0] |NUM |Read Key Number + * | | |The key number is sent to key store + * |[5] |RSRC |Read Key Destination + * | | |0 = key is read from registers CRPT_AESx_KEYx. + * | | |1 = key is read from key store. + * |[7:6] |RSSRC |Read Key Store Destination + * | | |00 = key is read from the SRAM of key store. + * | | |10 = key is read from the OTP of key store. + * | | |Others = reserved. + * @var CRPT_T::HMAC_KSCTL + * Offset: 0xF30 HMAC Key Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[4:0] |NUM |Read Key Number + * | | |The key number is sent to key store + * |[5] |RSRC |Read Key Destination + * | | |0 = key is read from HMAC registers. + * | | |1 = key is read from key store. + * |[7:6] |RSSRC |Read Key Store Destination + * | | |00 = key is read from the SRAM of key store. + * | | |10 = key is read from the OTP of key store. + * | | |Others = reserved. + * @var CRPT_T::ECC_KSCTL + * Offset: 0xF40 ECC Key Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[4:0] |NUMK |Read Key Number K + * | | |The key number of CRPT_ECC_K is sent to key store when RSRCK =1. + * |[5] |RSRCK |Read Key Destinationfor Key Number K + * | | |0 = key is read from ECC registers. + * | | |1 = key is read from key store. + * |[7:6] |RSSRCK |Read Key Store Destinationfor Key Number K + * | | |00 = key is read from the SRAM of key store. + * | | |10 = key is read from the OTP of key store. + * | | |Others = reserved. + * |[14] |ECDH |ECDH Control Bit + * | | |0 =reserved. + * | | |1 = Set ECC opereration is in ECDH + * | | |When this bit and RSRCK are equal to 0x1, ECC will read ECDH private key to CRPT_ECC_K from key store. + * |[16] |TRUST |Write Key Trust Selection Bit + * | | |0 = Set ECDH written key as the non-secure key. + * | | |1 = Set ECDH written key as the secure key. + * |[18] |PRIV |Write Key Privilege Selection Bit + * | | |0 = Set ECDH written key as the non-privilege key. + * | | |1 = Set ECDHwritten key as the privilege key. + * |[20] |XY |ECDH Output Select Bit + * | | |0 =The ECDH written key is from X-coordinate Value. + * | | |1 = The ECDH written key is from Y-coordinate Value. + * |[21] |WDST |Write Key Destination + * | | |0 = The ECDH writtenkey is in registers CRPT_ECC_X1 and CRPT_ECC_Y. + * | | |1 = The ECDH writtenkey is written to key store. + * |[23:22] |WSDST |Write Key Store Destination + * | | |00 = The ECDH writtenkey is written to the SRAM of key store. + * | | |10 = The ECDH writtenkey is written to the OTP of key store. + * | | |Others = reserved. + * |[26:24] |OWNER |Write Key Owner Selection Bits + * | | |000 = The ECDH written key is only for AES used. + * | | |001 = The ECDH written key is only for HMAC engine used. + * | | |100 = The ECDH written key is only for ECC engine used. + * | | |101 = The ECDH written key is only for CPU engine use. + * | | |Others = reserved. + * @var CRPT_T::ECC_KSSTS + * Offset: 0xF44 ECC Key Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[4:0] |NUM |Key Number + * | | |The key number is generated by key store after ECDH. + * @var CRPT_T::ECC_KSXY + * Offset: 0xF48 ECC XY Number Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[4:0] |NUMX |Read Key Number X + * | | |The key number of CRPT_ECC_X1 is sent to key store when RSRCXY =1. + * |[5] |RSRCXY |Read Key Source for Key Number xand Y + * | | |0 = key is read from ECC registers. + * | | |1 = key is read from key store. + * |[7:6] |RSSRCX |Read Key Store Source for Key Number X + * | | |00 = key is read from the SRAM of key store. + * | | |10 = key is read from the OTP of key store. + * | | |Others = reserved. + * |[12:8] |NUMY |Read Key Number Y + * | | |The key number of CRPT_ECC_Y1 is sent to key store when RSRCXY =1. + * |[15:14] |RSSRCY |Read Key Store Source for Key Number Y + * | | |00 = key is read from the SRAM of key store. + * | | |10 = key is read from the OTP of key store. + * | | |Others = reserved. + * @var CRPT_T::RSA_KSCTL + * Offset: 0xF50 RSA Key Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[4:0] |NUM |Read Key Number + * | | |The key number is sent to key store + * |[5] |RSRC |Read Key Destination + * | | |0 = key is read from RSA engine. + * | | |1 = key is read from key store. + * |[7:6] |RSSRC |Read Key Store Destination + * | | |00 = key is read from the SRAM of key store. + * | | |10 = key is read from the OTP of key store. + * | | |Others = reserved. + * |[12:8] |BKNUM |Read Exponent Blind Key Number + * | | |The key number is sent to key store, and its destination always be the SRAM of key store + * | | |CPU canu2019t read the exponent blind key. + * | | |Note:Use this key number, only when executing SCA protection but no-CRT mode. + * @var CRPT_T::RSA_KSSTS + * Offset: 0xF54-0xF58 RSA Key Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[4:0] |NUM0 |Key Number0 + * | | |The key number is generated by key store, RSA can get complete p by key number in Key Store while operating. + * |[12:8] |NUM1 |Key Number1 + * | | |The key number is generated by key store, RSA can get complete q by key number in Key Store while operating. + * |[20:16] |NUM2 |Key Number2 + * | | |The key number is generated by key store, RSA can get or store Cp by key number in Key Store while operating. + * |[28:24] |NUM3 |Key Number3 + * | | |The key number is generated by key store, RSA can get or store Cq by key number in Key Store while operating. + * |[36:32] |NUM4 |Key Number4 + * | | |The key number is generated by key store, RSA can get or store Dp by key number in Key Store while operating. + * |[44:40] |NUM5 |Key Number5 + * | | |The key number is generated by key store, RSA can get or store Dq by key number in Key Store while operating. + * |[52:48] |NUM6 |Key Number6 + * | | |The key number is generated by key store, RSA can get or store Rp by key number in Key Store while operating. + * |[60:56] |NUM7 |Key Number7 + * | | |The key number is generated by key store, RSA can get or store Rq by key number in Key Store while operating. + */ + __IO uint32_t INTEN; /*!< [0x0000] Crypto Interrupt Enable Control Register */ + __IO uint32_t INTSTS; /*!< [0x0004] Crypto Interrupt Flag */ + __IO uint32_t PRNG_CTL; /*!< [0x0008] PRNG Control Register */ + __O uint32_t PRNG_SEED; /*!< [0x000c] Seed for PRNG */ + __I uint32_t PRNG_KEY[8]; /*!< [0x0010] ~ [0x002c] PRNG Generated Key0 ~ Key7 */ + __I uint32_t PRNG_STS; /*!< [0x0030] PRNG Status Register */ + __I uint32_t RESERVE0[7]; + __I uint32_t AES_FDBCK[4]; /*!< [0x0050] ~ [0x005c] AES Engine Output Feedback Data after Cryptographic Operation */ + __I uint32_t RESERVE1[8]; + __IO uint32_t AES_GCM_IVCNT[2]; /*!< [0x0080] ~ [0x0084] AES GCM IV Byte Count Register 0 */ + __IO uint32_t AES_GCM_ACNT[2]; /*!< [0x0088] ~ [0x008c] AES GCM A Byte Count Register 0 */ + __IO uint32_t AES_GCM_PCNT[2]; /*!< [0x0090] ~ [0x0094] AES GCM P Byte Count Register 0 */ + __I uint32_t RESERVE2[2]; + __IO uint32_t AES_FBADDR; /*!< [0x00a0] AES DMA Feedback Address Register */ + __I uint32_t RESERVE3[23]; + __IO uint32_t AES_CTL; /*!< [0x0100] AES Control Register */ + __I uint32_t AES_STS; /*!< [0x0104] AES Engine Flag */ + __IO uint32_t AES_DATIN; /*!< [0x0108] AES Engine Data Input Port Register */ + __I uint32_t AES_DATOUT; /*!< [0x010c] AES Engine Data Output Port Register */ + __IO uint32_t AES_KEY[8]; /*!< [0x0110] ~ [0x012c] AES Key Word 0~7 Register for Channel 0 */ + __IO uint32_t AES_IV[4]; /*!< [0x0130] ~ [0x013c] AES Initial Vector Word 0 ~ 3 Register for Channel 0 */ + __IO uint32_t AES_SADDR; /*!< [0x0140] AES DMA Source Address Register */ + __IO uint32_t AES_DADDR; /*!< [0x0144] AES DMA Destination Address Register */ + __IO uint32_t AES_CNT; /*!< [0x0148] AES Byte Count Register */ + __I uint32_t RESERVE4[109]; + __IO uint32_t HMAC_CTL; /*!< [0x0300] SHA/HMAC Control Register */ + __I uint32_t HMAC_STS; /*!< [0x0304] SHA/HMAC Status Flag */ + __I uint32_t HMAC_DGST[16]; /*!< [0x0308] ~ [0x0344] SHA/HMAC Digest Message 0~15 */ + __IO uint32_t HMAC_KEYCNT; /*!< [0x0348] SHA/HMAC Key Byte Count Register */ + __IO uint32_t HMAC_SADDR; /*!< [0x034c] SHA/HMAC DMA Source Address Register */ + __IO uint32_t HMAC_DMACNT; /*!< [0x0350] SHA/HMAC Byte Count Register */ + __IO uint32_t HMAC_DATIN; /*!< [0x0354] SHA/HMAC Engine Non-dMA Mode Data Input Port Register */ + __IO uint32_t HMAC_FDBCK[54]; /*!< [0x0358] ~ [0x042c] SHA/HMAC Output Feedback Data 0After SHA/HMAC Operation */ + __I uint32_t RESERVE5[51]; + __IO uint32_t HMAC_FBADDR; /*!< [0x04fc] SHA/HMAC DMA Feedback Address Register */ + __I uint32_t RESERVE6[192]; + __IO uint32_t ECC_CTL; /*!< [0x0800] ECC Control Register */ + __I uint32_t ECC_STS; /*!< [0x0804] ECC Status Register */ + __IO uint32_t ECC_X1[18]; /*!< [0x0808] ~ [0x084c] ECC the X-coordinate Word0 of the First Point */ + __IO uint32_t ECC_Y1[18]; /*!< [0x0850] ~ [0x0894] ECC The Y-coordinate word 0~17 of the first point */ + __IO uint32_t ECC_X2[18]; /*!< [0x0898] ~ [0x08dc] ECC The X-coordinate word 0~17 of the second point */ + __IO uint32_t ECC_Y2[18]; /*!< [0x08e0] ~ [0x0924] ECC The Y-coordinate word 0~17 of the second point */ + __IO uint32_t ECC_A[18]; /*!< [0x0928] ~ [0x096c] ECC The parameter CURVEA word 0~17 of elliptic curve */ + __IO uint32_t ECC_B[18]; /*!< [0x0970] ~ [0x09b4] ECC The parameter CURVEB word 0~17 of elliptic curve */ + __IO uint32_t ECC_N[18]; /*!< [0x09b8] ~ [0x09fc] ECC The parameter CURVEN word 0~17 of elliptic curve */ + __O uint32_t ECC_K[18]; /*!< [0x0a00] ~ [0x0a44] ECC The scalar SCALARK word 0~17 of point multiplication */ + __IO uint32_t ECC_SADDR; /*!< [0x0a48] ECC DMA Source Address Register */ + __IO uint32_t ECC_DADDR; /*!< [0x0a4c] ECC DMA Destination Address Register */ + __IO uint32_t ECC_STARTREG; /*!< [0x0a50] ECC Starting Address of Updated Registers */ + __IO uint32_t ECC_WORDCNT; /*!< [0x0a54] ECC DMA Word Count */ + __I uint32_t RESERVE7[42]; + __IO uint32_t RSA_CTL; /*!< [0x0b00] RSA Control Register */ + __I uint32_t RSA_STS; /*!< [0x0b04] RSA Status Register */ + __IO uint32_t RSA_SADDR[5]; /*!< [0x0b08] ~ [0x0b18] RSA DMA Source Address Register0 */ + __IO uint32_t RSA_DADDR; /*!< [0x0b1c] RSA DMA Destination Address Register */ + __IO uint32_t RSA_MADDR[7]; /*!< [0x0b20] ~ [0x0b38] RSA DMA Middle Address Register0 */ + __I uint32_t RESERVE8[241]; + __O uint32_t PRNG_KSCTL; /*!< [0x0f00] PRNG Key Control Register */ + __I uint32_t PRNG_KSSTS; /*!< [0x0f04] PRNG Key Status Register */ + __I uint32_t RESERVE9[2]; + __O uint32_t AES_KSCTL; /*!< [0x0f10] AES Key Control Register */ + __I uint32_t RESERVE10[7]; + __O uint32_t HMAC_KSCTL; /*!< [0x0f30] HMAC Key Control Register */ + __I uint32_t RESERVE11[3]; + __O uint32_t ECC_KSCTL; /*!< [0x0f40] ECC Key Control Register */ + __I uint32_t ECC_KSSTS; /*!< [0x0f44] ECC Key Status Register */ + __O uint32_t ECC_KSXY; /*!< [0x0f48] ECC XY Number Register */ + __I uint32_t RESERVE12[1]; + __O uint32_t RSA_KSCTL; /*!< [0x0f50] RSA Key Control Register */ + __IO uint32_t RSA_KSSTS[2]; /*!< [0x0f54] ~ [0x0f58] RSA Key Status Register 0 */ + __I uint32_t RESERVE13[40]; + +} CRPT_T; + +/** + @addtogroup CRPT_CONST CRYPTO Bit Field Definition + Constant Definitions for CRYPTO Controller + @{ +*/ + +#define CRPT_INTEN_AESIEN_Pos (0) /*!< CRPT_T::INTEN: AESIEN Position */ +#define CRPT_INTEN_AESIEN_Msk (0x1ul << CRPT_INTEN_AESIEN_Pos) /*!< CRPT_T::INTEN: AESIEN Mask */ + +#define CRPT_INTEN_AESEIEN_Pos (1) /*!< CRPT_T::INTEN: AESEIEN Position */ +#define CRPT_INTEN_AESEIEN_Msk (0x1ul << CRPT_INTEN_AESEIEN_Pos) /*!< CRPT_T::INTEN: AESEIEN Mask */ + +#define CRPT_INTEN_PRNGIEN_Pos (16) /*!< CRPT_T::INTEN: PRNGIEN Position */ +#define CRPT_INTEN_PRNGIEN_Msk (0x1ul << CRPT_INTEN_PRNGIEN_Pos) /*!< CRPT_T::INTEN: PRNGIEN Mask */ + +#define CRPT_INTEN_PRNGEIEN_Pos (17) /*!< CRPT_T::INTEN: PRNGEIEN Position */ +#define CRPT_INTEN_PRNGEIEN_Msk (0x1ul << CRPT_INTEN_PRNGEIEN_Pos) /*!< CRPT_T::INTEN: PRNGEIEN Mask */ + +#define CRPT_INTEN_ECCIEN_Pos (22) /*!< CRPT_T::INTEN: ECCIEN Position */ +#define CRPT_INTEN_ECCIEN_Msk (0x1ul << CRPT_INTEN_ECCIEN_Pos) /*!< CRPT_T::INTEN: ECCIEN Mask */ + +#define CRPT_INTEN_ECCEIEN_Pos (23) /*!< CRPT_T::INTEN: ECCEIEN Position */ +#define CRPT_INTEN_ECCEIEN_Msk (0x1ul << CRPT_INTEN_ECCEIEN_Pos) /*!< CRPT_T::INTEN: ECCEIEN Mask */ + +#define CRPT_INTEN_HMACIEN_Pos (24) /*!< CRPT_T::INTEN: HMACIEN Position */ +#define CRPT_INTEN_HMACIEN_Msk (0x1ul << CRPT_INTEN_HMACIEN_Pos) /*!< CRPT_T::INTEN: HMACIEN Mask */ + +#define CRPT_INTEN_HMACEIEN_Pos (25) /*!< CRPT_T::INTEN: HMACEIEN Position */ +#define CRPT_INTEN_HMACEIEN_Msk (0x1ul << CRPT_INTEN_HMACEIEN_Pos) /*!< CRPT_T::INTEN: HMACEIEN Mask */ + +#define CRPT_INTEN_RSAIEN_Pos (30) /*!< CRPT_T::INTEN: RSAIEN Position */ +#define CRPT_INTEN_RSAIEN_Msk (0x1ul << CRPT_INTEN_RSAIEN_Pos) /*!< CRPT_T::INTEN: RSAIEN Mask */ + +#define CRPT_INTEN_RSAEIEN_Pos (31) /*!< CRPT_T::INTEN: RSAEIEN Position */ +#define CRPT_INTEN_RSAEIEN_Msk (0x1ul << CRPT_INTEN_RSAEIEN_Pos) /*!< CRPT_T::INTEN: RSAEIEN Mask */ + +#define CRPT_INTSTS_AESIF_Pos (0) /*!< CRPT_T::INTSTS: AESIF Position */ +#define CRPT_INTSTS_AESIF_Msk (0x1ul << CRPT_INTSTS_AESIF_Pos) /*!< CRPT_T::INTSTS: AESIF Mask */ + +#define CRPT_INTSTS_AESEIF_Pos (1) /*!< CRPT_T::INTSTS: AESEIF Position */ +#define CRPT_INTSTS_AESEIF_Msk (0x1ul << CRPT_INTSTS_AESEIF_Pos) /*!< CRPT_T::INTSTS: AESEIF Mask */ + +#define CRPT_INTSTS_PRNGIF_Pos (16) /*!< CRPT_T::INTSTS: PRNGIF Position */ +#define CRPT_INTSTS_PRNGIF_Msk (0x1ul << CRPT_INTSTS_PRNGIF_Pos) /*!< CRPT_T::INTSTS: PRNGIF Mask */ + +#define CRPT_INTSTS_PRNGEIF_Pos (17) /*!< CRPT_T::INTSTS: PRNGEIF Position */ +#define CRPT_INTSTS_PRNGEIF_Msk (0x1ul << CRPT_INTSTS_PRNGEIF_Pos) /*!< CRPT_T::INTSTS: PRNGEIF Mask */ + +#define CRPT_INTSTS_ECCIF_Pos (22) /*!< CRPT_T::INTSTS: ECCIF Position */ +#define CRPT_INTSTS_ECCIF_Msk (0x1ul << CRPT_INTSTS_ECCIF_Pos) /*!< CRPT_T::INTSTS: ECCIF Mask */ + +#define CRPT_INTSTS_ECCEIF_Pos (23) /*!< CRPT_T::INTSTS: ECCEIF Position */ +#define CRPT_INTSTS_ECCEIF_Msk (0x1ul << CRPT_INTSTS_ECCEIF_Pos) /*!< CRPT_T::INTSTS: ECCEIF Mask */ + +#define CRPT_INTSTS_HMACIF_Pos (24) /*!< CRPT_T::INTSTS: HMACIF Position */ +#define CRPT_INTSTS_HMACIF_Msk (0x1ul << CRPT_INTSTS_HMACIF_Pos) /*!< CRPT_T::INTSTS: HMACIF Mask */ + +#define CRPT_INTSTS_HMACEIF_Pos (25) /*!< CRPT_T::INTSTS: HMACEIF Position */ +#define CRPT_INTSTS_HMACEIF_Msk (0x1ul << CRPT_INTSTS_HMACEIF_Pos) /*!< CRPT_T::INTSTS: HMACEIF Mask */ + +#define CRPT_INTSTS_RSAIF_Pos (30) /*!< CRPT_T::INTSTS: RSAIF Position */ +#define CRPT_INTSTS_RSAIF_Msk (0x1ul << CRPT_INTSTS_RSAIF_Pos) /*!< CRPT_T::INTSTS: RSAIF Mask */ + +#define CRPT_INTSTS_RSAEIF_Pos (31) /*!< CRPT_T::INTSTS: RSAEIF Position */ +#define CRPT_INTSTS_RSAEIF_Msk (0x1ul << CRPT_INTSTS_RSAEIF_Pos) /*!< CRPT_T::INTSTS: RSAEIF Mask */ + +#define CRPT_PRNG_CTL_START_Pos (0) /*!< CRPT_T::PRNG_CTL: START Position */ +#define CRPT_PRNG_CTL_START_Msk (0x1ul << CRPT_PRNG_CTL_START_Pos) /*!< CRPT_T::PRNG_CTL: START Mask */ + +#define CRPT_PRNG_CTL_SEEDRLD_Pos (1) /*!< CRPT_T::PRNG_CTL: SEEDRLD Position */ +#define CRPT_PRNG_CTL_SEEDRLD_Msk (0x1ul << CRPT_PRNG_CTL_SEEDRLD_Pos) /*!< CRPT_T::PRNG_CTL: SEEDRLD Mask */ + +#define CRPT_PRNG_CTL_KEYSZ_Pos (2) /*!< CRPT_T::PRNG_CTL: KEYSZ Position */ +#define CRPT_PRNG_CTL_KEYSZ_Msk (0xful << CRPT_PRNG_CTL_KEYSZ_Pos) /*!< CRPT_T::PRNG_CTL: KEYSZ Mask */ + +#define CRPT_PRNG_CTL_SEEDSEL_Pos (6) /*!< CRPT_T::PRNG_CTL: SEEDSEL Position */ +#define CRPT_PRNG_CTL_SEEDSEL_Msk (0x1ul << CRPT_PRNG_CTL_SEEDSEL_Pos) /*!< CRPT_T::PRNG_CTL: SEEDSEL Mask */ + +#define CRPT_PRNG_CTL_SEEDSRC_Pos (7) /*!< CRPT_T::PRNG_CTL: SEEDSRC Position */ +#define CRPT_PRNG_CTL_SEEDSRC_Msk (0x1ul << CRPT_PRNG_CTL_SEEDSRC_Pos) /*!< CRPT_T::PRNG_CTL: SEEDSRC Mask */ + +#define CRPT_PRNG_CTL_BUSY_Pos (8) /*!< CRPT_T::PRNG_CTL: BUSY Position */ +#define CRPT_PRNG_CTL_BUSY_Msk (0x1ul << CRPT_PRNG_CTL_BUSY_Pos) /*!< CRPT_T::PRNG_CTL: BUSY Mask */ + +#define CRPT_PRNG_SEED_SEED_Pos (0) /*!< CRPT_T::PRNG_SEED: SEED Position */ +#define CRPT_PRNG_SEED_SEED_Msk (0xfffffffful << CRPT_PRNG_SEED_SEED_Pos) /*!< CRPT_T::PRNG_SEED: SEED Mask */ + +#define CRPT_PRNG_KEY0_KEY_Pos (0) /*!< CRPT_T::PRNG_KEY0: KEY Position */ +#define CRPT_PRNG_KEY0_KEY_Msk (0xfffffffful << CRPT_PRNG_KEY0_KEY_Pos) /*!< CRPT_T::PRNG_KEY0: KEY Mask */ + +#define CRPT_PRNG_KEY1_KEY_Pos (0) /*!< CRPT_T::PRNG_KEY1: KEY Position */ +#define CRPT_PRNG_KEY1_KEY_Msk (0xfffffffful << CRPT_PRNG_KEY1_KEY_Pos) /*!< CRPT_T::PRNG_KEY1: KEY Mask */ + +#define CRPT_PRNG_KEY2_KEY_Pos (0) /*!< CRPT_T::PRNG_KEY2: KEY Position */ +#define CRPT_PRNG_KEY2_KEY_Msk (0xfffffffful << CRPT_PRNG_KEY2_KEY_Pos) /*!< CRPT_T::PRNG_KEY2: KEY Mask */ + +#define CRPT_PRNG_KEY3_KEY_Pos (0) /*!< CRPT_T::PRNG_KEY3: KEY Position */ +#define CRPT_PRNG_KEY3_KEY_Msk (0xfffffffful << CRPT_PRNG_KEY3_KEY_Pos) /*!< CRPT_T::PRNG_KEY3: KEY Mask */ + +#define CRPT_PRNG_KEY4_KEY_Pos (0) /*!< CRPT_T::PRNG_KEY4: KEY Position */ +#define CRPT_PRNG_KEY4_KEY_Msk (0xfffffffful << CRPT_PRNG_KEY4_KEY_Pos) /*!< CRPT_T::PRNG_KEY4: KEY Mask */ + +#define CRPT_PRNG_KEY5_KEY_Pos (0) /*!< CRPT_T::PRNG_KEY5: KEY Position */ +#define CRPT_PRNG_KEY5_KEY_Msk (0xfffffffful << CRPT_PRNG_KEY5_KEY_Pos) /*!< CRPT_T::PRNG_KEY5: KEY Mask */ + +#define CRPT_PRNG_KEY6_KEY_Pos (0) /*!< CRPT_T::PRNG_KEY6: KEY Position */ +#define CRPT_PRNG_KEY6_KEY_Msk (0xfffffffful << CRPT_PRNG_KEY6_KEY_Pos) /*!< CRPT_T::PRNG_KEY6: KEY Mask */ + +#define CRPT_PRNG_KEY7_KEY_Pos (0) /*!< CRPT_T::PRNG_KEY7: KEY Position */ +#define CRPT_PRNG_KEY7_KEY_Msk (0xfffffffful << CRPT_PRNG_KEY7_KEY_Pos) /*!< CRPT_T::PRNG_KEY7: KEY Mask */ + +#define CRPT_PRNG_STS_BUSY_Pos (0) /*!< CRPT_T::PRNG_STS: BUSY Position */ +#define CRPT_PRNG_STS_BUSY_Msk (0x1ul << CRPT_PRNG_STS_BUSY_Pos) /*!< CRPT_T::PRNG_STS: BUSY Mask */ + +#define CRPT_PRNG_STS_KCTLERR_Pos (16) /*!< CRPT_T::PRNG_STS: KCTLERR Position */ +#define CRPT_PRNG_STS_KCTLERR_Msk (0x1ul << CRPT_PRNG_STS_KCTLERR_Pos) /*!< CRPT_T::PRNG_STS: KCTLERR Mask */ + +#define CRPT_PRNG_STS_KSERR_Pos (17) /*!< CRPT_T::PRNG_STS: KSERR Position */ +#define CRPT_PRNG_STS_KSERR_Msk (0x1ul << CRPT_PRNG_STS_KSERR_Pos) /*!< CRPT_T::PRNG_STS: KSERR Mask */ + +#define CRPT_AES_FDBCK0_FDBCK_Pos (0) /*!< CRPT_T::AES_FDBCK0: FDBCK Position */ +#define CRPT_AES_FDBCK0_FDBCK_Msk (0xfffffffful << CRPT_AES_FDBCK0_FDBCK_Pos) /*!< CRPT_T::AES_FDBCK0: FDBCK Mask */ + +#define CRPT_AES_FDBCK1_FDBCK_Pos (0) /*!< CRPT_T::AES_FDBCK1: FDBCK Position */ +#define CRPT_AES_FDBCK1_FDBCK_Msk (0xfffffffful << CRPT_AES_FDBCK1_FDBCK_Pos) /*!< CRPT_T::AES_FDBCK1: FDBCK Mask */ + +#define CRPT_AES_FDBCK2_FDBCK_Pos (0) /*!< CRPT_T::AES_FDBCK2: FDBCK Position */ +#define CRPT_AES_FDBCK2_FDBCK_Msk (0xfffffffful << CRPT_AES_FDBCK2_FDBCK_Pos) /*!< CRPT_T::AES_FDBCK2: FDBCK Mask */ + +#define CRPT_AES_FDBCK3_FDBCK_Pos (0) /*!< CRPT_T::AES_FDBCK3: FDBCK Position */ +#define CRPT_AES_FDBCK3_FDBCK_Msk (0xfffffffful << CRPT_AES_FDBCK3_FDBCK_Pos) /*!< CRPT_T::AES_FDBCK3: FDBCK Mask */ + +#define CRPT_AES_GCM_IVCNT0_CNT_Pos (0) /*!< CRPT_T::AES_GCM_IVCNT0: CNT Position */ +#define CRPT_AES_GCM_IVCNT0_CNT_Msk (0xfffffffful << CRPT_AES_GCM_IVCNT0_CNT_Pos) /*!< CRPT_T::AES_GCM_IVCNT0: CNT Mask */ + +#define CRPT_AES_GCM_IVCNT1_CNT_Pos (0) /*!< CRPT_T::AES_GCM_IVCNT1: CNT Position */ +#define CRPT_AES_GCM_IVCNT1_CNT_Msk (0x1ffffffful << CRPT_AES_GCM_IVCNT1_CNT_Pos) /*!< CRPT_T::AES_GCM_IVCNT1: CNT Mask */ + +#define CRPT_AES_GCM_ACNT0_CNT_Pos (0) /*!< CRPT_T::AES_GCM_ACNT0: CNT Position */ +#define CRPT_AES_GCM_ACNT0_CNT_Msk (0xfffffffful << CRPT_AES_GCM_ACNT0_CNT_Pos) /*!< CRPT_T::AES_GCM_ACNT0: CNT Mask */ + +#define CRPT_AES_GCM_ACNT1_CNT_Pos (0) /*!< CRPT_T::AES_GCM_ACNT1: CNT Position */ +#define CRPT_AES_GCM_ACNT1_CNT_Msk (0x1ffffffful << CRPT_AES_GCM_ACNT1_CNT_Pos) /*!< CRPT_T::AES_GCM_ACNT1: CNT Mask */ + +#define CRPT_AES_GCM_PCNT0_CNT_Pos (0) /*!< CRPT_T::AES_GCM_PCNT0: CNT Position */ +#define CRPT_AES_GCM_PCNT0_CNT_Msk (0xfffffffful << CRPT_AES_GCM_PCNT0_CNT_Pos) /*!< CRPT_T::AES_GCM_PCNT0: CNT Mask */ + +#define CRPT_AES_GCM_PCNT1_CNT_Pos (0) /*!< CRPT_T::AES_GCM_PCNT1: CNT Position */ +#define CRPT_AES_GCM_PCNT1_CNT_Msk (0x1ffffffful << CRPT_AES_GCM_PCNT1_CNT_Pos) /*!< CRPT_T::AES_GCM_PCNT1: CNT Mask */ + +#define CRPT_AES_FBADDR_FBADDR_Pos (0) /*!< CRPT_T::AES_FBADDR: FBADDR Position */ +#define CRPT_AES_FBADDR_FBADDR_Msk (0xfffffffful << CRPT_AES_FBADDR_FBADDR_Pos) /*!< CRPT_T::AES_FBADDR: FBADDR Mask */ + +#define CRPT_AES_CTL_START_Pos (0) /*!< CRPT_T::AES_CTL: START Position */ +#define CRPT_AES_CTL_START_Msk (0x1ul << CRPT_AES_CTL_START_Pos) /*!< CRPT_T::AES_CTL: START Mask */ + +#define CRPT_AES_CTL_STOP_Pos (1) /*!< CRPT_T::AES_CTL: STOP Position */ +#define CRPT_AES_CTL_STOP_Msk (0x1ul << CRPT_AES_CTL_STOP_Pos) /*!< CRPT_T::AES_CTL: STOP Mask */ + +#define CRPT_AES_CTL_KEYSZ_Pos (2) /*!< CRPT_T::AES_CTL: KEYSZ Position */ +#define CRPT_AES_CTL_KEYSZ_Msk (0x3ul << CRPT_AES_CTL_KEYSZ_Pos) /*!< CRPT_T::AES_CTL: KEYSZ Mask */ + +#define CRPT_AES_CTL_DMALAST_Pos (5) /*!< CRPT_T::AES_CTL: DMALAST Position */ +#define CRPT_AES_CTL_DMALAST_Msk (0x1ul << CRPT_AES_CTL_DMALAST_Pos) /*!< CRPT_T::AES_CTL: DMALAST Mask */ + +#define CRPT_AES_CTL_DMACSCAD_Pos (6) /*!< CRPT_T::AES_CTL: DMACSCAD Position */ +#define CRPT_AES_CTL_DMACSCAD_Msk (0x1ul << CRPT_AES_CTL_DMACSCAD_Pos) /*!< CRPT_T::AES_CTL: DMACSCAD Mask */ + +#define CRPT_AES_CTL_DMAEN_Pos (7) /*!< CRPT_T::AES_CTL: DMAEN Position */ +#define CRPT_AES_CTL_DMAEN_Msk (0x1ul << CRPT_AES_CTL_DMAEN_Pos) /*!< CRPT_T::AES_CTL: DMAEN Mask */ + +#define CRPT_AES_CTL_OPMODE_Pos (8) /*!< CRPT_T::AES_CTL: OPMODE Position */ +#define CRPT_AES_CTL_OPMODE_Msk (0xfful << CRPT_AES_CTL_OPMODE_Pos) /*!< CRPT_T::AES_CTL: OPMODE Mask */ + +#define CRPT_AES_CTL_ENCRPT_Pos (16) /*!< CRPT_T::AES_CTL: ENCRYPTO Position */ +#define CRPT_AES_CTL_ENCRPT_Msk (0x1ul << CRPT_AES_CTL_ENCRPT_Pos) /*!< CRPT_T::AES_CTL: ENCRYPTO Mask */ + +#define CRPT_AES_CTL_SM4EN_Pos (17) /*!< CRPT_T::AES_CTL: SM4EN Position */ +#define CRPT_AES_CTL_SM4EN_Msk (0x1ul << CRPT_AES_CTL_SM4EN_Pos) /*!< CRPT_T::AES_CTL: SM4EN Mask */ + +#define CRPT_AES_CTL_FBIN_Pos (20) /*!< CRPT_T::AES_CTL: FBIN Position */ +#define CRPT_AES_CTL_FBIN_Msk (0x1ul << CRPT_AES_CTL_FBIN_Pos) /*!< CRPT_T::AES_CTL: FBIN Mask */ + +#define CRPT_AES_CTL_FBOUT_Pos (21) /*!< CRPT_T::AES_CTL: FBOUT Position */ +#define CRPT_AES_CTL_FBOUT_Msk (0x1ul << CRPT_AES_CTL_FBOUT_Pos) /*!< CRPT_T::AES_CTL: FBOUT Mask */ + +#define CRPT_AES_CTL_OUTSWAP_Pos (22) /*!< CRPT_T::AES_CTL: OUTSWAP Position */ +#define CRPT_AES_CTL_OUTSWAP_Msk (0x1ul << CRPT_AES_CTL_OUTSWAP_Pos) /*!< CRPT_T::AES_CTL: OUTSWAP Mask */ + +#define CRPT_AES_CTL_INSWAP_Pos (23) /*!< CRPT_T::AES_CTL: INSWAP Position */ +#define CRPT_AES_CTL_INSWAP_Msk (0x1ul << CRPT_AES_CTL_INSWAP_Pos) /*!< CRPT_T::AES_CTL: INSWAP Mask */ + +#define CRPT_AES_CTL_KOUTSWAP_Pos (24) /*!< CRPT_T::AES_CTL: KOUTSWAP Position */ +#define CRPT_AES_CTL_KOUTSWAP_Msk (0x1ul << CRPT_AES_CTL_KOUTSWAP_Pos) /*!< CRPT_T::AES_CTL: KOUTSWAP Mask */ + +#define CRPT_AES_CTL_KINSWAP_Pos (25) /*!< CRPT_T::AES_CTL: KINSWAP Position */ +#define CRPT_AES_CTL_KINSWAP_Msk (0x1ul << CRPT_AES_CTL_KINSWAP_Pos) /*!< CRPT_T::AES_CTL: KINSWAP Mask */ + +#define CRPT_AES_CTL_KEYUNPRT_Pos (26) /*!< CRPT_T::AES_CTL: KEYUNPRT Position */ +#define CRPT_AES_CTL_KEYUNPRT_Msk (0x1ful << CRPT_AES_CTL_KEYUNPRT_Pos) /*!< CRPT_T::AES_CTL: KEYUNPRT Mask */ + +#define CRPT_AES_CTL_KEYPRT_Pos (31) /*!< CRPT_T::AES_CTL: KEYPRT Position */ +#define CRPT_AES_CTL_KEYPRT_Msk (0x1ul << CRPT_AES_CTL_KEYPRT_Pos) /*!< CRPT_T::AES_CTL: KEYPRT Mask */ + +#define CRPT_AES_STS_BUSY_Pos (0) /*!< CRPT_T::AES_STS: BUSY Position */ +#define CRPT_AES_STS_BUSY_Msk (0x1ul << CRPT_AES_STS_BUSY_Pos) /*!< CRPT_T::AES_STS: BUSY Mask */ + +#define CRPT_AES_STS_INBUFEMPTY_Pos (8) /*!< CRPT_T::AES_STS: INBUFEMPTY Position */ +#define CRPT_AES_STS_INBUFEMPTY_Msk (0x1ul << CRPT_AES_STS_INBUFEMPTY_Pos) /*!< CRPT_T::AES_STS: INBUFEMPTY Mask */ + +#define CRPT_AES_STS_INBUFFULL_Pos (9) /*!< CRPT_T::AES_STS: INBUFFULL Position */ +#define CRPT_AES_STS_INBUFFULL_Msk (0x1ul << CRPT_AES_STS_INBUFFULL_Pos) /*!< CRPT_T::AES_STS: INBUFFULL Mask */ + +#define CRPT_AES_STS_INBUFERR_Pos (10) /*!< CRPT_T::AES_STS: INBUFERR Position */ +#define CRPT_AES_STS_INBUFERR_Msk (0x1ul << CRPT_AES_STS_INBUFERR_Pos) /*!< CRPT_T::AES_STS: INBUFERR Mask */ + +#define CRPT_AES_STS_CNTERR_Pos (12) /*!< CRPT_T::AES_STS: CNTERR Position */ +#define CRPT_AES_STS_CNTERR_Msk (0x1ul << CRPT_AES_STS_CNTERR_Pos) /*!< CRPT_T::AES_STS: CNTERR Mask */ + +#define CRPT_AES_STS_OUTBUFEMPTY_Pos (16) /*!< CRPT_T::AES_STS: OUTBUFEMPTY Position*/ +#define CRPT_AES_STS_OUTBUFEMPTY_Msk (0x1ul << CRPT_AES_STS_OUTBUFEMPTY_Pos) /*!< CRPT_T::AES_STS: OUTBUFEMPTY Mask */ + +#define CRPT_AES_STS_OUTBUFFULL_Pos (17) /*!< CRPT_T::AES_STS: OUTBUFFULL Position */ +#define CRPT_AES_STS_OUTBUFFULL_Msk (0x1ul << CRPT_AES_STS_OUTBUFFULL_Pos) /*!< CRPT_T::AES_STS: OUTBUFFULL Mask */ + +#define CRPT_AES_STS_OUTBUFERR_Pos (18) /*!< CRPT_T::AES_STS: OUTBUFERR Position */ +#define CRPT_AES_STS_OUTBUFERR_Msk (0x1ul << CRPT_AES_STS_OUTBUFERR_Pos) /*!< CRPT_T::AES_STS: OUTBUFERR Mask */ + +#define CRPT_AES_STS_BUSERR_Pos (20) /*!< CRPT_T::AES_STS: BUSERR Position */ +#define CRPT_AES_STS_BUSERR_Msk (0x1ul << CRPT_AES_STS_BUSERR_Pos) /*!< CRPT_T::AES_STS: BUSERR Mask */ + +#define CRPT_AES_STS_KSERR_Pos (21) /*!< CRPT_T::AES_STS: KSERR Position */ +#define CRPT_AES_STS_KSERR_Msk (0x1ul << CRPT_AES_STS_KSERR_Pos) /*!< CRPT_T::AES_STS: KSERR Mask */ + +#define CRPT_AES_DATIN_DATIN_Pos (0) /*!< CRPT_T::AES_DATIN: DATIN Position */ +#define CRPT_AES_DATIN_DATIN_Msk (0xfffffffful << CRPT_AES_DATIN_DATIN_Pos) /*!< CRPT_T::AES_DATIN: DATIN Mask */ + +#define CRPT_AES_DATOUT_DATOUT_Pos (0) /*!< CRPT_T::AES_DATOUT: DATOUT Position */ +#define CRPT_AES_DATOUT_DATOUT_Msk (0xfffffffful << CRPT_AES_DATOUT_DATOUT_Pos) /*!< CRPT_T::AES_DATOUT: DATOUT Mask */ + +#define CRPT_AES_KEY0_KEY_Pos (0) /*!< CRPT_T::AES_KEY0: KEY Position */ +#define CRPT_AES_KEY0_KEY_Msk (0xfffffffful << CRPT_AES_KEY0_KEY_Pos) /*!< CRPT_T::AES_KEY0: KEY Mask */ + +#define CRPT_AES_KEY1_KEY_Pos (0) /*!< CRPT_T::AES_KEY1: KEY Position */ +#define CRPT_AES_KEY1_KEY_Msk (0xfffffffful << CRPT_AES_KEY1_KEY_Pos) /*!< CRPT_T::AES_KEY1: KEY Mask */ + +#define CRPT_AES_KEY2_KEY_Pos (0) /*!< CRPT_T::AES_KEY2: KEY Position */ +#define CRPT_AES_KEY2_KEY_Msk (0xfffffffful << CRPT_AES_KEY2_KEY_Pos) /*!< CRPT_T::AES_KEY2: KEY Mask */ + +#define CRPT_AES_KEY3_KEY_Pos (0) /*!< CRPT_T::AES_KEY3: KEY Position */ +#define CRPT_AES_KEY3_KEY_Msk (0xfffffffful << CRPT_AES_KEY3_KEY_Pos) /*!< CRPT_T::AES_KEY3: KEY Mask */ + +#define CRPT_AES_KEY4_KEY_Pos (0) /*!< CRPT_T::AES_KEY4: KEY Position */ +#define CRPT_AES_KEY4_KEY_Msk (0xfffffffful << CRPT_AES_KEY4_KEY_Pos) /*!< CRPT_T::AES_KEY4: KEY Mask */ + +#define CRPT_AES_KEY5_KEY_Pos (0) /*!< CRPT_T::AES_KEY5: KEY Position */ +#define CRPT_AES_KEY5_KEY_Msk (0xfffffffful << CRPT_AES_KEY5_KEY_Pos) /*!< CRPT_T::AES_KEY5: KEY Mask */ + +#define CRPT_AES_KEY6_KEY_Pos (0) /*!< CRPT_T::AES_KEY6: KEY Position */ +#define CRPT_AES_KEY6_KEY_Msk (0xfffffffful << CRPT_AES_KEY6_KEY_Pos) /*!< CRPT_T::AES_KEY6: KEY Mask */ + +#define CRPT_AES_KEY7_KEY_Pos (0) /*!< CRPT_T::AES_KEY7: KEY Position */ +#define CRPT_AES_KEY7_KEY_Msk (0xfffffffful << CRPT_AES_KEY7_KEY_Pos) /*!< CRPT_T::AES_KEY7: KEY Mask */ + +#define CRPT_AES_IV0_IV_Pos (0) /*!< CRPT_T::AES_IV0: IV Position */ +#define CRPT_AES_IV0_IV_Msk (0xfffffffful << CRPT_AES_IV0_IV_Pos) /*!< CRPT_T::AES_IV0: IV Mask */ + +#define CRPT_AES_IV1_IV_Pos (0) /*!< CRPT_T::AES_IV1: IV Position */ +#define CRPT_AES_IV1_IV_Msk (0xfffffffful << CRPT_AES_IV1_IV_Pos) /*!< CRPT_T::AES_IV1: IV Mask */ + +#define CRPT_AES_IV2_IV_Pos (0) /*!< CRPT_T::AES_IV2: IV Position */ +#define CRPT_AES_IV2_IV_Msk (0xfffffffful << CRPT_AES_IV2_IV_Pos) /*!< CRPT_T::AES_IV2: IV Mask */ + +#define CRPT_AES_IV3_IV_Pos (0) /*!< CRPT_T::AES_IV3: IV Position */ +#define CRPT_AES_IV3_IV_Msk (0xfffffffful << CRPT_AES_IV3_IV_Pos) /*!< CRPT_T::AES_IV3: IV Mask */ + +#define CRPT_AES_SADDR_SADDR_Pos (0) /*!< CRPT_T::AES_SADDR: SADDR Position */ +#define CRPT_AES_SADDR_SADDR_Msk (0xfffffffful << CRPT_AES_SADDR_SADDR_Pos) /*!< CRPT_T::AES_SADDR: SADDR Mask */ + +#define CRPT_AES_DADDR_DADDR_Pos (0) /*!< CRPT_T::AES_DADDR: DADDR Position */ +#define CRPT_AES_DADDR_DADDR_Msk (0xfffffffful << CRPT_AES_DADDR_DADDR_Pos) /*!< CRPT_T::AES_DADDR: DADDR Mask */ + +#define CRPT_AES_CNT_CNT_Pos (0) /*!< CRPT_T::AES_CNT: CNT Position */ +#define CRPT_AES_CNT_CNT_Msk (0xfffffffful << CRPT_AES_CNT_CNT_Pos) /*!< CRPT_T::AES_CNT: CNT Mask */ + +#define CRPT_HMAC_CTL_START_Pos (0) /*!< CRPT_T::HMAC_CTL: START Position */ +#define CRPT_HMAC_CTL_START_Msk (0x1ul << CRPT_HMAC_CTL_START_Pos) /*!< CRPT_T::HMAC_CTL: START Mask */ + +#define CRPT_HMAC_CTL_STOP_Pos (1) /*!< CRPT_T::HMAC_CTL: STOP Position */ +#define CRPT_HMAC_CTL_STOP_Msk (0x1ul << CRPT_HMAC_CTL_STOP_Pos) /*!< CRPT_T::HMAC_CTL: STOP Mask */ + +#define CRPT_HMAC_CTL_DMAFIRST_Pos (4) /*!< CRPT_T::HMAC_CTL: DMAFIRST Position */ +#define CRPT_HMAC_CTL_DMAFIRST_Msk (0x1ul << CRPT_HMAC_CTL_DMAFIRST_Pos) /*!< CRPT_T::HMAC_CTL: DMAFIRST Mask */ + +#define CRPT_HMAC_CTL_DMALAST_Pos (5) /*!< CRPT_T::HMAC_CTL: DMALAST Position */ +#define CRPT_HMAC_CTL_DMALAST_Msk (0x1ul << CRPT_HMAC_CTL_DMALAST_Pos) /*!< CRPT_T::HMAC_CTL: DMALAST Mask */ + +#define CRPT_HMAC_CTL_DMACSCAD_Pos (6) /*!< CRPT_T::HMAC_CTL: DMACSCAD Position */ +#define CRPT_HMAC_CTL_DMACSCAD_Msk (0x1ul << CRPT_HMAC_CTL_DMACSCAD_Pos) /*!< CRPT_T::HMAC_CTL: DMACSCAD Mask */ + +#define CRPT_HMAC_CTL_DMAEN_Pos (7) /*!< CRPT_T::HMAC_CTL: DMAEN Position */ +#define CRPT_HMAC_CTL_DMAEN_Msk (0x1ul << CRPT_HMAC_CTL_DMAEN_Pos) /*!< CRPT_T::HMAC_CTL: DMAEN Mask */ + +#define CRPT_HMAC_CTL_OPMODE_Pos (8) /*!< CRPT_T::HMAC_CTL: OPMODE Position */ +#define CRPT_HMAC_CTL_OPMODE_Msk (0x7ul << CRPT_HMAC_CTL_OPMODE_Pos) /*!< CRPT_T::HMAC_CTL: OPMODE Mask */ + +#define CRPT_HMAC_CTL_HMACEN_Pos (11) /*!< CRPT_T::HMAC_CTL: HMACEN Position */ +#define CRPT_HMAC_CTL_HMACEN_Msk (0x1ul << CRPT_HMAC_CTL_HMACEN_Pos) /*!< CRPT_T::HMAC_CTL: HMACEN Mask */ + +#define CRPT_HMAC_CTL_SM3EN_Pos (13) /*!< CRPT_T::HMAC_CTL: SM3EN Position */ +#define CRPT_HMAC_CTL_SM3EN_Msk (0x1ul << CRPT_HMAC_CTL_SM3EN_Pos) /*!< CRPT_T::HMAC_CTL: SM3EN Mask */ + +#define CRPT_HMAC_CTL_FBIN_Pos (20) /*!< CRPT_T::HMAC_CTL: FBIN Position */ +#define CRPT_HMAC_CTL_FBIN_Msk (0x1ul << CRPT_HMAC_CTL_FBIN_Pos) /*!< CRPT_T::HMAC_CTL: FBIN Mask */ + +#define CRPT_HMAC_CTL_FBOUT_Pos (21) /*!< CRPT_T::HMAC_CTL: FBOUT Position */ +#define CRPT_HMAC_CTL_FBOUT_Msk (0x1ul << CRPT_HMAC_CTL_FBOUT_Pos) /*!< CRPT_T::HMAC_CTL: FBOUT Mask */ + +#define CRPT_HMAC_CTL_OUTSWAP_Pos (22) /*!< CRPT_T::HMAC_CTL: OUTSWAP Position */ +#define CRPT_HMAC_CTL_OUTSWAP_Msk (0x1ul << CRPT_HMAC_CTL_OUTSWAP_Pos) /*!< CRPT_T::HMAC_CTL: OUTSWAP Mask */ + +#define CRPT_HMAC_CTL_INSWAP_Pos (23) /*!< CRPT_T::HMAC_CTL: INSWAP Position */ +#define CRPT_HMAC_CTL_INSWAP_Msk (0x1ul << CRPT_HMAC_CTL_INSWAP_Pos) /*!< CRPT_T::HMAC_CTL: INSWAP Mask */ + +#define CRPT_HMAC_STS_BUSY_Pos (0) /*!< CRPT_T::HMAC_STS: BUSY Position */ +#define CRPT_HMAC_STS_BUSY_Msk (0x1ul << CRPT_HMAC_STS_BUSY_Pos) /*!< CRPT_T::HMAC_STS: BUSY Mask */ + +#define CRPT_HMAC_STS_DMABUSY_Pos (1) /*!< CRPT_T::HMAC_STS: DMABUSY Position */ +#define CRPT_HMAC_STS_DMABUSY_Msk (0x1ul << CRPT_HMAC_STS_DMABUSY_Pos) /*!< CRPT_T::HMAC_STS: DMABUSY Mask */ + +#define CRPT_HMAC_STS_DMAERR_Pos (8) /*!< CRPT_T::HMAC_STS: DMAERR Position */ +#define CRPT_HMAC_STS_DMAERR_Msk (0x1ul << CRPT_HMAC_STS_DMAERR_Pos) /*!< CRPT_T::HMAC_STS: DMAERR Mask */ + +#define CRPT_HMAC_STS_KSERR_Pos (9) /*!< CRPT_T::HMAC_STS: KSERR Position */ +#define CRPT_HMAC_STS_KSERR_Msk (0x1ul << CRPT_HMAC_STS_KSERR_Pos) /*!< CRPT_T::HMAC_STS: KSERR Mask */ + +#define CRPT_HMAC_STS_DATINREQ_Pos (16) /*!< CRPT_T::HMAC_STS: DATINREQ Position */ +#define CRPT_HMAC_STS_DATINREQ_Msk (0x1ul << CRPT_HMAC_STS_DATINREQ_Pos) /*!< CRPT_T::HMAC_STS: DATINREQ Mask */ + +#define CRPT_HMAC_DGST0_DGST_Pos (0) /*!< CRPT_T::HMAC_DGST0: DGST Position */ +#define CRPT_HMAC_DGST0_DGST_Msk (0xfffffffful << CRPT_HMAC_DGST0_DGST_Pos) /*!< CRPT_T::HMAC_DGST0: DGST Mask */ + +#define CRPT_HMAC_DGST1_DGST_Pos (0) /*!< CRPT_T::HMAC_DGST1: DGST Position */ +#define CRPT_HMAC_DGST1_DGST_Msk (0xfffffffful << CRPT_HMAC_DGST1_DGST_Pos) /*!< CRPT_T::HMAC_DGST1: DGST Mask */ + +#define CRPT_HMAC_DGST2_DGST_Pos (0) /*!< CRPT_T::HMAC_DGST2: DGST Position */ +#define CRPT_HMAC_DGST2_DGST_Msk (0xfffffffful << CRPT_HMAC_DGST2_DGST_Pos) /*!< CRPT_T::HMAC_DGST2: DGST Mask */ + +#define CRPT_HMAC_DGST3_DGST_Pos (0) /*!< CRPT_T::HMAC_DGST3: DGST Position */ +#define CRPT_HMAC_DGST3_DGST_Msk (0xfffffffful << CRPT_HMAC_DGST3_DGST_Pos) /*!< CRPT_T::HMAC_DGST3: DGST Mask */ + +#define CRPT_HMAC_DGST4_DGST_Pos (0) /*!< CRPT_T::HMAC_DGST4: DGST Position */ +#define CRPT_HMAC_DGST4_DGST_Msk (0xfffffffful << CRPT_HMAC_DGST4_DGST_Pos) /*!< CRPT_T::HMAC_DGST4: DGST Mask */ + +#define CRPT_HMAC_DGST5_DGST_Pos (0) /*!< CRPT_T::HMAC_DGST5: DGST Position */ +#define CRPT_HMAC_DGST5_DGST_Msk (0xfffffffful << CRPT_HMAC_DGST5_DGST_Pos) /*!< CRPT_T::HMAC_DGST5: DGST Mask */ + +#define CRPT_HMAC_DGST6_DGST_Pos (0) /*!< CRPT_T::HMAC_DGST6: DGST Position */ +#define CRPT_HMAC_DGST6_DGST_Msk (0xfffffffful << CRPT_HMAC_DGST6_DGST_Pos) /*!< CRPT_T::HMAC_DGST6: DGST Mask */ + +#define CRPT_HMAC_DGST7_DGST_Pos (0) /*!< CRPT_T::HMAC_DGST7: DGST Position */ +#define CRPT_HMAC_DGST7_DGST_Msk (0xfffffffful << CRPT_HMAC_DGST7_DGST_Pos) /*!< CRPT_T::HMAC_DGST7: DGST Mask */ + +#define CRPT_HMAC_DGST8_DGST_Pos (0) /*!< CRPT_T::HMAC_DGST8: DGST Position */ +#define CRPT_HMAC_DGST8_DGST_Msk (0xfffffffful << CRPT_HMAC_DGST8_DGST_Pos) /*!< CRPT_T::HMAC_DGST8: DGST Mask */ + +#define CRPT_HMAC_DGST9_DGST_Pos (0) /*!< CRPT_T::HMAC_DGST9: DGST Position */ +#define CRPT_HMAC_DGST9_DGST_Msk (0xfffffffful << CRPT_HMAC_DGST9_DGST_Pos) /*!< CRPT_T::HMAC_DGST9: DGST Mask */ + +#define CRPT_HMAC_DGST10_DGST_Pos (0) /*!< CRPT_T::HMAC_DGST10: DGST Position */ +#define CRPT_HMAC_DGST10_DGST_Msk (0xfffffffful << CRPT_HMAC_DGST10_DGST_Pos) /*!< CRPT_T::HMAC_DGST10: DGST Mask */ + +#define CRPT_HMAC_DGST11_DGST_Pos (0) /*!< CRPT_T::HMAC_DGST11: DGST Position */ +#define CRPT_HMAC_DGST11_DGST_Msk (0xfffffffful << CRPT_HMAC_DGST11_DGST_Pos) /*!< CRPT_T::HMAC_DGST11: DGST Mask */ + +#define CRPT_HMAC_DGST12_DGST_Pos (0) /*!< CRPT_T::HMAC_DGST12: DGST Position */ +#define CRPT_HMAC_DGST12_DGST_Msk (0xfffffffful << CRPT_HMAC_DGST12_DGST_Pos) /*!< CRPT_T::HMAC_DGST12: DGST Mask */ + +#define CRPT_HMAC_DGST13_DGST_Pos (0) /*!< CRPT_T::HMAC_DGST13: DGST Position */ +#define CRPT_HMAC_DGST13_DGST_Msk (0xfffffffful << CRPT_HMAC_DGST13_DGST_Pos) /*!< CRPT_T::HMAC_DGST13: DGST Mask */ + +#define CRPT_HMAC_DGST14_DGST_Pos (0) /*!< CRPT_T::HMAC_DGST14: DGST Position */ +#define CRPT_HMAC_DGST14_DGST_Msk (0xfffffffful << CRPT_HMAC_DGST14_DGST_Pos) /*!< CRPT_T::HMAC_DGST14: DGST Mask */ + +#define CRPT_HMAC_DGST15_DGST_Pos (0) /*!< CRPT_T::HMAC_DGST15: DGST Position */ +#define CRPT_HMAC_DGST15_DGST_Msk (0xfffffffful << CRPT_HMAC_DGST15_DGST_Pos) /*!< CRPT_T::HMAC_DGST15: DGST Mask */ + +#define CRPT_HMAC_KEYCNT_KEYCNT_Pos (0) /*!< CRPT_T::HMAC_KEYCNT: KEYCNT Position */ +#define CRPT_HMAC_KEYCNT_KEYCNT_Msk (0xfffffffful << CRPT_HMAC_KEYCNT_KEYCNT_Pos) /*!< CRPT_T::HMAC_KEYCNT: KEYCNT Mask */ + +#define CRPT_HMAC_SADDR_SADDR_Pos (0) /*!< CRPT_T::HMAC_SADDR: SADDR Position */ +#define CRPT_HMAC_SADDR_SADDR_Msk (0xfffffffful << CRPT_HMAC_SADDR_SADDR_Pos) /*!< CRPT_T::HMAC_SADDR: SADDR Mask */ + +#define CRPT_HMAC_DMACNT_DMACNT_Pos (0) /*!< CRPT_T::HMAC_DMACNT: DMACNT Position */ +#define CRPT_HMAC_DMACNT_DMACNT_Msk (0xfffffffful << CRPT_HMAC_DMACNT_DMACNT_Pos) /*!< CRPT_T::HMAC_DMACNT: DMACNT Mask */ + +#define CRPT_HMAC_DATIN_DATIN_Pos (0) /*!< CRPT_T::HMAC_DATIN: DATIN Position */ +#define CRPT_HMAC_DATIN_DATIN_Msk (0xfffffffful << CRPT_HMAC_DATIN_DATIN_Pos) /*!< CRPT_T::HMAC_DATIN: DATIN Mask */ + +#define CRPT_HMAC_FDBCK0_FDBCK_Pos (0) /*!< CRPT_T::HMAC_FDBCK0: FDBCK Position */ +#define CRPT_HMAC_FDBCK0_FDBCK_Msk (0xfffffffful << CRPT_HMAC_FDBCK0_FDBCK_Pos) /*!< CRPT_T::HMAC_FDBCK0: FDBCK Mask */ + +#define CRPT_HMAC_FDBCK1_FDBCK_Pos (0) /*!< CRPT_T::HMAC_FDBCK1: FDBCK Position */ +#define CRPT_HMAC_FDBCK1_FDBCK_Msk (0xfffffffful << CRPT_HMAC_FDBCK1_FDBCK_Pos) /*!< CRPT_T::HMAC_FDBCK1: FDBCK Mask */ + +#define CRPT_HMAC_FDBCK2_FDBCK_Pos (0) /*!< CRPT_T::HMAC_FDBCK2: FDBCK Position */ +#define CRPT_HMAC_FDBCK2_FDBCK_Msk (0xfffffffful << CRPT_HMAC_FDBCK2_FDBCK_Pos) /*!< CRPT_T::HMAC_FDBCK2: FDBCK Mask */ + +#define CRPT_HMAC_FDBCK3_FDBCK_Pos (0) /*!< CRPT_T::HMAC_FDBCK3: FDBCK Position */ +#define CRPT_HMAC_FDBCK3_FDBCK_Msk (0xfffffffful << CRPT_HMAC_FDBCK3_FDBCK_Pos) /*!< CRPT_T::HMAC_FDBCK3: FDBCK Mask */ + +#define CRPT_HMAC_FDBCK4_FDBCK_Pos (0) /*!< CRPT_T::HMAC_FDBCK4: FDBCK Position */ +#define CRPT_HMAC_FDBCK4_FDBCK_Msk (0xfffffffful << CRPT_HMAC_FDBCK4_FDBCK_Pos) /*!< CRPT_T::HMAC_FDBCK4: FDBCK Mask */ + +#define CRPT_HMAC_FDBCK5_FDBCK_Pos (0) /*!< CRPT_T::HMAC_FDBCK5: FDBCK Position */ +#define CRPT_HMAC_FDBCK5_FDBCK_Msk (0xfffffffful << CRPT_HMAC_FDBCK5_FDBCK_Pos) /*!< CRPT_T::HMAC_FDBCK5: FDBCK Mask */ + +#define CRPT_HMAC_FDBCK6_FDBCK_Pos (0) /*!< CRPT_T::HMAC_FDBCK6: FDBCK Position */ +#define CRPT_HMAC_FDBCK6_FDBCK_Msk (0xfffffffful << CRPT_HMAC_FDBCK6_FDBCK_Pos) /*!< CRPT_T::HMAC_FDBCK6: FDBCK Mask */ + +#define CRPT_HMAC_FDBCK7_FDBCK_Pos (0) /*!< CRPT_T::HMAC_FDBCK7: FDBCK Position */ +#define CRPT_HMAC_FDBCK7_FDBCK_Msk (0xfffffffful << CRPT_HMAC_FDBCK7_FDBCK_Pos) /*!< CRPT_T::HMAC_FDBCK7: FDBCK Mask */ + +#define CRPT_HMAC_FDBCK8_FDBCK_Pos (0) /*!< CRPT_T::HMAC_FDBCK8: FDBCK Position */ +#define CRPT_HMAC_FDBCK8_FDBCK_Msk (0xfffffffful << CRPT_HMAC_FDBCK8_FDBCK_Pos) /*!< CRPT_T::HMAC_FDBCK8: FDBCK Mask */ + +#define CRPT_HMAC_FDBCK9_FDBCK_Pos (0) /*!< CRPT_T::HMAC_FDBCK9: FDBCK Position */ +#define CRPT_HMAC_FDBCK9_FDBCK_Msk (0xfffffffful << CRPT_HMAC_FDBCK9_FDBCK_Pos) /*!< CRPT_T::HMAC_FDBCK9: FDBCK Mask */ + +#define CRPT_HMAC_FDBCK10_FDBCK_Pos (0) /*!< CRPT_T::HMAC_FDBCK10: FDBCK Position */ +#define CRPT_HMAC_FDBCK10_FDBCK_Msk (0xfffffffful << CRPT_HMAC_FDBCK10_FDBCK_Pos) /*!< CRPT_T::HMAC_FDBCK10: FDBCK Mask */ + +#define CRPT_HMAC_FDBCK11_FDBCK_Pos (0) /*!< CRPT_T::HMAC_FDBCK11: FDBCK Position */ +#define CRPT_HMAC_FDBCK11_FDBCK_Msk (0xfffffffful << CRPT_HMAC_FDBCK11_FDBCK_Pos) /*!< CRPT_T::HMAC_FDBCK11: FDBCK Mask */ + +#define CRPT_HMAC_FDBCK12_FDBCK_Pos (0) /*!< CRPT_T::HMAC_FDBCK12: FDBCK Position */ +#define CRPT_HMAC_FDBCK12_FDBCK_Msk (0xfffffffful << CRPT_HMAC_FDBCK12_FDBCK_Pos) /*!< CRPT_T::HMAC_FDBCK12: FDBCK Mask */ + +#define CRPT_HMAC_FDBCK13_FDBCK_Pos (0) /*!< CRPT_T::HMAC_FDBCK13: FDBCK Position */ +#define CRPT_HMAC_FDBCK13_FDBCK_Msk (0xfffffffful << CRPT_HMAC_FDBCK13_FDBCK_Pos) /*!< CRPT_T::HMAC_FDBCK13: FDBCK Mask */ + +#define CRPT_HMAC_FDBCK14_FDBCK_Pos (0) /*!< CRPT_T::HMAC_FDBCK14: FDBCK Position */ +#define CRPT_HMAC_FDBCK14_FDBCK_Msk (0xfffffffful << CRPT_HMAC_FDBCK14_FDBCK_Pos) /*!< CRPT_T::HMAC_FDBCK14: FDBCK Mask */ + +#define CRPT_HMAC_FDBCK15_FDBCK_Pos (0) /*!< CRPT_T::HMAC_FDBCK15: FDBCK Position */ +#define CRPT_HMAC_FDBCK15_FDBCK_Msk (0xfffffffful << CRPT_HMAC_FDBCK15_FDBCK_Pos) /*!< CRPT_T::HMAC_FDBCK15: FDBCK Mask */ + +#define CRPT_HMAC_FDBCK16_FDBCK_Pos (0) /*!< CRPT_T::HMAC_FDBCK16: FDBCK Position */ +#define CRPT_HMAC_FDBCK16_FDBCK_Msk (0xfffffffful << CRPT_HMAC_FDBCK16_FDBCK_Pos) /*!< CRPT_T::HMAC_FDBCK16: FDBCK Mask */ + +#define CRPT_HMAC_FDBCK17_FDBCK_Pos (0) /*!< CRPT_T::HMAC_FDBCK17: FDBCK Position */ +#define CRPT_HMAC_FDBCK17_FDBCK_Msk (0xfffffffful << CRPT_HMAC_FDBCK17_FDBCK_Pos) /*!< CRPT_T::HMAC_FDBCK17: FDBCK Mask */ + +#define CRPT_HMAC_FDBCK18_FDBCK_Pos (0) /*!< CRPT_T::HMAC_FDBCK18: FDBCK Position */ +#define CRPT_HMAC_FDBCK18_FDBCK_Msk (0xfffffffful << CRPT_HMAC_FDBCK18_FDBCK_Pos) /*!< CRPT_T::HMAC_FDBCK18: FDBCK Mask */ + +#define CRPT_HMAC_FDBCK19_FDBCK_Pos (0) /*!< CRPT_T::HMAC_FDBCK19: FDBCK Position */ +#define CRPT_HMAC_FDBCK19_FDBCK_Msk (0xfffffffful << CRPT_HMAC_FDBCK19_FDBCK_Pos) /*!< CRPT_T::HMAC_FDBCK19: FDBCK Mask */ + +#define CRPT_HMAC_FDBCK20_FDBCK_Pos (0) /*!< CRPT_T::HMAC_FDBCK20: FDBCK Position */ +#define CRPT_HMAC_FDBCK20_FDBCK_Msk (0xfffffffful << CRPT_HMAC_FDBCK20_FDBCK_Pos) /*!< CRPT_T::HMAC_FDBCK20: FDBCK Mask */ + +#define CRPT_HMAC_FDBCK21_FDBCK_Pos (0) /*!< CRPT_T::HMAC_FDBCK21: FDBCK Position */ +#define CRPT_HMAC_FDBCK21_FDBCK_Msk (0xfffffffful << CRPT_HMAC_FDBCK21_FDBCK_Pos) /*!< CRPT_T::HMAC_FDBCK21: FDBCK Mask */ + +#define CRPT_HMAC_FDBCK22_FDBCK_Pos (0) /*!< CRPT_T::HMAC_FDBCK22: FDBCK Position */ +#define CRPT_HMAC_FDBCK22_FDBCK_Msk (0xfffffffful << CRPT_HMAC_FDBCK22_FDBCK_Pos) /*!< CRPT_T::HMAC_FDBCK22: FDBCK Mask */ + +#define CRPT_HMAC_FDBCK23_FDBCK_Pos (0) /*!< CRPT_T::HMAC_FDBCK23: FDBCK Position */ +#define CRPT_HMAC_FDBCK23_FDBCK_Msk (0xfffffffful << CRPT_HMAC_FDBCK23_FDBCK_Pos) /*!< CRPT_T::HMAC_FDBCK23: FDBCK Mask */ + +#define CRPT_HMAC_FDBCK24_FDBCK_Pos (0) /*!< CRPT_T::HMAC_FDBCK24: FDBCK Position */ +#define CRPT_HMAC_FDBCK24_FDBCK_Msk (0xfffffffful << CRPT_HMAC_FDBCK24_FDBCK_Pos) /*!< CRPT_T::HMAC_FDBCK24: FDBCK Mask */ + +#define CRPT_HMAC_FDBCK25_FDBCK_Pos (0) /*!< CRPT_T::HMAC_FDBCK25: FDBCK Position */ +#define CRPT_HMAC_FDBCK25_FDBCK_Msk (0xfffffffful << CRPT_HMAC_FDBCK25_FDBCK_Pos) /*!< CRPT_T::HMAC_FDBCK25: FDBCK Mask */ + +#define CRPT_HMAC_FDBCK26_FDBCK_Pos (0) /*!< CRPT_T::HMAC_FDBCK26: FDBCK Position */ +#define CRPT_HMAC_FDBCK26_FDBCK_Msk (0xfffffffful << CRPT_HMAC_FDBCK26_FDBCK_Pos) /*!< CRPT_T::HMAC_FDBCK26: FDBCK Mask */ + +#define CRPT_HMAC_FDBCK27_FDBCK_Pos (0) /*!< CRPT_T::HMAC_FDBCK27: FDBCK Position */ +#define CRPT_HMAC_FDBCK27_FDBCK_Msk (0xfffffffful << CRPT_HMAC_FDBCK27_FDBCK_Pos) /*!< CRPT_T::HMAC_FDBCK27: FDBCK Mask */ + +#define CRPT_HMAC_FDBCK28_FDBCK_Pos (0) /*!< CRPT_T::HMAC_FDBCK28: FDBCK Position */ +#define CRPT_HMAC_FDBCK28_FDBCK_Msk (0xfffffffful << CRPT_HMAC_FDBCK28_FDBCK_Pos) /*!< CRPT_T::HMAC_FDBCK28: FDBCK Mask */ + +#define CRPT_HMAC_FDBCK29_FDBCK_Pos (0) /*!< CRPT_T::HMAC_FDBCK29: FDBCK Position */ +#define CRPT_HMAC_FDBCK29_FDBCK_Msk (0xfffffffful << CRPT_HMAC_FDBCK29_FDBCK_Pos) /*!< CRPT_T::HMAC_FDBCK29: FDBCK Mask */ + +#define CRPT_HMAC_FDBCK30_FDBCK_Pos (0) /*!< CRPT_T::HMAC_FDBCK30: FDBCK Position */ +#define CRPT_HMAC_FDBCK30_FDBCK_Msk (0xfffffffful << CRPT_HMAC_FDBCK30_FDBCK_Pos) /*!< CRPT_T::HMAC_FDBCK30: FDBCK Mask */ + +#define CRPT_HMAC_FDBCK31_FDBCK_Pos (0) /*!< CRPT_T::HMAC_FDBCK31: FDBCK Position */ +#define CRPT_HMAC_FDBCK31_FDBCK_Msk (0xfffffffful << CRPT_HMAC_FDBCK31_FDBCK_Pos) /*!< CRPT_T::HMAC_FDBCK31: FDBCK Mask */ + +#define CRPT_HMAC_FDBCK32_FDBCK_Pos (0) /*!< CRPT_T::HMAC_FDBCK32: FDBCK Position */ +#define CRPT_HMAC_FDBCK32_FDBCK_Msk (0xfffffffful << CRPT_HMAC_FDBCK32_FDBCK_Pos) /*!< CRPT_T::HMAC_FDBCK32: FDBCK Mask */ + +#define CRPT_HMAC_FDBCK33_FDBCK_Pos (0) /*!< CRPT_T::HMAC_FDBCK33: FDBCK Position */ +#define CRPT_HMAC_FDBCK33_FDBCK_Msk (0xfffffffful << CRPT_HMAC_FDBCK33_FDBCK_Pos) /*!< CRPT_T::HMAC_FDBCK33: FDBCK Mask */ + +#define CRPT_HMAC_FDBCK34_FDBCK_Pos (0) /*!< CRPT_T::HMAC_FDBCK34: FDBCK Position */ +#define CRPT_HMAC_FDBCK34_FDBCK_Msk (0xfffffffful << CRPT_HMAC_FDBCK34_FDBCK_Pos) /*!< CRPT_T::HMAC_FDBCK34: FDBCK Mask */ + +#define CRPT_HMAC_FDBCK35_FDBCK_Pos (0) /*!< CRPT_T::HMAC_FDBCK35: FDBCK Position */ +#define CRPT_HMAC_FDBCK35_FDBCK_Msk (0xfffffffful << CRPT_HMAC_FDBCK35_FDBCK_Pos) /*!< CRPT_T::HMAC_FDBCK35: FDBCK Mask */ + +#define CRPT_HMAC_FDBCK36_FDBCK_Pos (0) /*!< CRPT_T::HMAC_FDBCK36: FDBCK Position */ +#define CRPT_HMAC_FDBCK36_FDBCK_Msk (0xfffffffful << CRPT_HMAC_FDBCK36_FDBCK_Pos) /*!< CRPT_T::HMAC_FDBCK36: FDBCK Mask */ + +#define CRPT_HMAC_FDBCK37_FDBCK_Pos (0) /*!< CRPT_T::HMAC_FDBCK37: FDBCK Position */ +#define CRPT_HMAC_FDBCK37_FDBCK_Msk (0xfffffffful << CRPT_HMAC_FDBCK37_FDBCK_Pos) /*!< CRPT_T::HMAC_FDBCK37: FDBCK Mask */ + +#define CRPT_HMAC_FDBCK38_FDBCK_Pos (0) /*!< CRPT_T::HMAC_FDBCK38: FDBCK Position */ +#define CRPT_HMAC_FDBCK38_FDBCK_Msk (0xfffffffful << CRPT_HMAC_FDBCK38_FDBCK_Pos) /*!< CRPT_T::HMAC_FDBCK38: FDBCK Mask */ + +#define CRPT_HMAC_FDBCK39_FDBCK_Pos (0) /*!< CRPT_T::HMAC_FDBCK39: FDBCK Position */ +#define CRPT_HMAC_FDBCK39_FDBCK_Msk (0xfffffffful << CRPT_HMAC_FDBCK39_FDBCK_Pos) /*!< CRPT_T::HMAC_FDBCK39: FDBCK Mask */ + +#define CRPT_HMAC_FDBCK40_FDBCK_Pos (0) /*!< CRPT_T::HMAC_FDBCK40: FDBCK Position */ +#define CRPT_HMAC_FDBCK40_FDBCK_Msk (0xfffffffful << CRPT_HMAC_FDBCK40_FDBCK_Pos) /*!< CRPT_T::HMAC_FDBCK40: FDBCK Mask */ + +#define CRPT_HMAC_FDBCK41_FDBCK_Pos (0) /*!< CRPT_T::HMAC_FDBCK41: FDBCK Position */ +#define CRPT_HMAC_FDBCK41_FDBCK_Msk (0xfffffffful << CRPT_HMAC_FDBCK41_FDBCK_Pos) /*!< CRPT_T::HMAC_FDBCK41: FDBCK Mask */ + +#define CRPT_HMAC_FDBCK42_FDBCK_Pos (0) /*!< CRPT_T::HMAC_FDBCK42: FDBCK Position */ +#define CRPT_HMAC_FDBCK42_FDBCK_Msk (0xfffffffful << CRPT_HMAC_FDBCK42_FDBCK_Pos) /*!< CRPT_T::HMAC_FDBCK42: FDBCK Mask */ + +#define CRPT_HMAC_FDBCK43_FDBCK_Pos (0) /*!< CRPT_T::HMAC_FDBCK43: FDBCK Position */ +#define CRPT_HMAC_FDBCK43_FDBCK_Msk (0xfffffffful << CRPT_HMAC_FDBCK43_FDBCK_Pos) /*!< CRPT_T::HMAC_FDBCK43: FDBCK Mask */ + +#define CRPT_HMAC_FDBCK44_FDBCK_Pos (0) /*!< CRPT_T::HMAC_FDBCK44: FDBCK Position */ +#define CRPT_HMAC_FDBCK44_FDBCK_Msk (0xfffffffful << CRPT_HMAC_FDBCK44_FDBCK_Pos) /*!< CRPT_T::HMAC_FDBCK44: FDBCK Mask */ + +#define CRPT_HMAC_FDBCK45_FDBCK_Pos (0) /*!< CRPT_T::HMAC_FDBCK45: FDBCK Position */ +#define CRPT_HMAC_FDBCK45_FDBCK_Msk (0xfffffffful << CRPT_HMAC_FDBCK45_FDBCK_Pos) /*!< CRPT_T::HMAC_FDBCK45: FDBCK Mask */ + +#define CRPT_HMAC_FDBCK46_FDBCK_Pos (0) /*!< CRPT_T::HMAC_FDBCK46: FDBCK Position */ +#define CRPT_HMAC_FDBCK46_FDBCK_Msk (0xfffffffful << CRPT_HMAC_FDBCK46_FDBCK_Pos) /*!< CRPT_T::HMAC_FDBCK46: FDBCK Mask */ + +#define CRPT_HMAC_FDBCK47_FDBCK_Pos (0) /*!< CRPT_T::HMAC_FDBCK47: FDBCK Position */ +#define CRPT_HMAC_FDBCK47_FDBCK_Msk (0xfffffffful << CRPT_HMAC_FDBCK47_FDBCK_Pos) /*!< CRPT_T::HMAC_FDBCK47: FDBCK Mask */ + +#define CRPT_HMAC_FDBCK48_FDBCK_Pos (0) /*!< CRPT_T::HMAC_FDBCK48: FDBCK Position */ +#define CRPT_HMAC_FDBCK48_FDBCK_Msk (0xfffffffful << CRPT_HMAC_FDBCK48_FDBCK_Pos) /*!< CRPT_T::HMAC_FDBCK48: FDBCK Mask */ + +#define CRPT_HMAC_FDBCK49_FDBCK_Pos (0) /*!< CRPT_T::HMAC_FDBCK49: FDBCK Position */ +#define CRPT_HMAC_FDBCK49_FDBCK_Msk (0xfffffffful << CRPT_HMAC_FDBCK49_FDBCK_Pos) /*!< CRPT_T::HMAC_FDBCK49: FDBCK Mask */ + +#define CRPT_HMAC_FDBCK50_FDBCK_Pos (0) /*!< CRPT_T::HMAC_FDBCK50: FDBCK Position */ +#define CRPT_HMAC_FDBCK50_FDBCK_Msk (0xfffffffful << CRPT_HMAC_FDBCK50_FDBCK_Pos) /*!< CRPT_T::HMAC_FDBCK50: FDBCK Mask */ + +#define CRPT_HMAC_FDBCK51_FDBCK_Pos (0) /*!< CRPT_T::HMAC_FDBCK51: FDBCK Position */ +#define CRPT_HMAC_FDBCK51_FDBCK_Msk (0xfffffffful << CRPT_HMAC_FDBCK51_FDBCK_Pos) /*!< CRPT_T::HMAC_FDBCK51: FDBCK Mask */ + +#define CRPT_HMAC_FDBCK52_FDBCK_Pos (0) /*!< CRPT_T::HMAC_FDBCK52: FDBCK Position */ +#define CRPT_HMAC_FDBCK52_FDBCK_Msk (0xfffffffful << CRPT_HMAC_FDBCK52_FDBCK_Pos) /*!< CRPT_T::HMAC_FDBCK52: FDBCK Mask */ + +#define CRPT_HMAC_FDBCK53_FDBCK_Pos (0) /*!< CRPT_T::HMAC_FDBCK53: FDBCK Position */ +#define CRPT_HMAC_FDBCK53_FDBCK_Msk (0xfffffffful << CRPT_HMAC_FDBCK53_FDBCK_Pos) /*!< CRPT_T::HMAC_FDBCK53: FDBCK Mask */ + +#define CRPT_HMAC_FBADDR_FBADDR_Pos (0) /*!< CRPT_T::HMAC_FBADDR: FBADDR Position */ +#define CRPT_HMAC_FBADDR_FBADDR_Msk (0xfffffffful << CRPT_HMAC_FBADDR_FBADDR_Pos) /*!< CRPT_T::HMAC_FBADDR: FBADDR Mask */ + +#define CRPT_ECC_CTL_START_Pos (0) /*!< CRPT_T::ECC_CTL: START Position */ +#define CRPT_ECC_CTL_START_Msk (0x1ul << CRPT_ECC_CTL_START_Pos) /*!< CRPT_T::ECC_CTL: START Mask */ + +#define CRPT_ECC_CTL_STOP_Pos (1) /*!< CRPT_T::ECC_CTL: STOP Position */ +#define CRPT_ECC_CTL_STOP_Msk (0x1ul << CRPT_ECC_CTL_STOP_Pos) /*!< CRPT_T::ECC_CTL: STOP Mask */ + +#define CRPT_ECC_CTL_PFA2C_Pos (3) /*!< CRPT_T::ECC_CTL: PFA2C Position */ +#define CRPT_ECC_CTL_PFA2C_Msk (0x1ul << CRPT_ECC_CTL_PFA2C_Pos) /*!< CRPT_T::ECC_CTL: PFA2C Mask */ + +#define CRPT_ECC_CTL_ECDSAS_Pos (4) /*!< CRPT_T::ECC_CTL: ECDSAS Position */ +#define CRPT_ECC_CTL_ECDSAS_Msk (0x1ul << CRPT_ECC_CTL_ECDSAS_Pos) /*!< CRPT_T::ECC_CTL: ECDSAS Mask */ + +#define CRPT_ECC_CTL_ECDSAR_Pos (5) /*!< CRPT_T::ECC_CTL: ECDSAR Position */ +#define CRPT_ECC_CTL_ECDSAR_Msk (0x1ul << CRPT_ECC_CTL_ECDSAR_Pos) /*!< CRPT_T::ECC_CTL: ECDSAR Mask */ + +#define CRPT_ECC_CTL_DMAEN_Pos (7) /*!< CRPT_T::ECC_CTL: DMAEN Position */ +#define CRPT_ECC_CTL_DMAEN_Msk (0x1ul << CRPT_ECC_CTL_DMAEN_Pos) /*!< CRPT_T::ECC_CTL: DMAEN Mask */ + +#define CRPT_ECC_CTL_FSEL_Pos (8) /*!< CRPT_T::ECC_CTL: FSEL Position */ +#define CRPT_ECC_CTL_FSEL_Msk (0x1ul << CRPT_ECC_CTL_FSEL_Pos) /*!< CRPT_T::ECC_CTL: FSEL Mask */ + +#define CRPT_ECC_CTL_ECCOP_Pos (9) /*!< CRPT_T::ECC_CTL: ECCOP Position */ +#define CRPT_ECC_CTL_ECCOP_Msk (0x3ul << CRPT_ECC_CTL_ECCOP_Pos) /*!< CRPT_T::ECC_CTL: ECCOP Mask */ + +#define CRPT_ECC_CTL_MODOP_Pos (11) /*!< CRPT_T::ECC_CTL: MODOP Position */ +#define CRPT_ECC_CTL_MODOP_Msk (0x3ul << CRPT_ECC_CTL_MODOP_Pos) /*!< CRPT_T::ECC_CTL: MODOP Mask */ + +#define CRPT_ECC_CTL_CSEL_Pos (13) /*!< CRPT_T::ECC_CTL: CSEL Position */ +#define CRPT_ECC_CTL_CSEL_Msk (0x1ul << CRPT_ECC_CTL_CSEL_Pos) /*!< CRPT_T::ECC_CTL: CSEL Mask */ + +#define CRPT_ECC_CTL_SCAP_Pos (14) /*!< CRPT_T::ECC_CTL: SCAP Position */ +#define CRPT_ECC_CTL_SCAP_Msk (0x1ul << CRPT_ECC_CTL_SCAP_Pos) /*!< CRPT_T::ECC_CTL: SCAP Mask */ + +#define CRPT_ECC_CTL_SBM_Pos (15) /*!< CRPT_T::ECC_CTL: SBM Position */ +#define CRPT_ECC_CTL_SBM_Msk (0x1ul << CRPT_ECC_CTL_SBM_Pos) /*!< CRPT_T::ECC_CTL: SBM Mask */ + +#define CRPT_ECC_CTL_LDP1_Pos (16) /*!< CRPT_T::ECC_CTL: LDP1 Position */ +#define CRPT_ECC_CTL_LDP1_Msk (0x1ul << CRPT_ECC_CTL_LDP1_Pos) /*!< CRPT_T::ECC_CTL: LDP1 Mask */ + +#define CRPT_ECC_CTL_LDP2_Pos (17) /*!< CRPT_T::ECC_CTL: LDP2 Position */ +#define CRPT_ECC_CTL_LDP2_Msk (0x1ul << CRPT_ECC_CTL_LDP2_Pos) /*!< CRPT_T::ECC_CTL: LDP2 Mask */ + +#define CRPT_ECC_CTL_LDA_Pos (18) /*!< CRPT_T::ECC_CTL: LDA Position */ +#define CRPT_ECC_CTL_LDA_Msk (0x1ul << CRPT_ECC_CTL_LDA_Pos) /*!< CRPT_T::ECC_CTL: LDA Mask */ + +#define CRPT_ECC_CTL_LDB_Pos (19) /*!< CRPT_T::ECC_CTL: LDB Position */ +#define CRPT_ECC_CTL_LDB_Msk (0x1ul << CRPT_ECC_CTL_LDB_Pos) /*!< CRPT_T::ECC_CTL: LDB Mask */ + +#define CRPT_ECC_CTL_LDN_Pos (20) /*!< CRPT_T::ECC_CTL: LDN Position */ +#define CRPT_ECC_CTL_LDN_Msk (0x1ul << CRPT_ECC_CTL_LDN_Pos) /*!< CRPT_T::ECC_CTL: LDN Mask */ + +#define CRPT_ECC_CTL_LDK_Pos (21) /*!< CRPT_T::ECC_CTL: LDK Position */ +#define CRPT_ECC_CTL_LDK_Msk (0x1ul << CRPT_ECC_CTL_LDK_Pos) /*!< CRPT_T::ECC_CTL: LDK Mask */ + +#define CRPT_ECC_CTL_CURVEM_Pos (22) /*!< CRPT_T::ECC_CTL: CURVEM Position */ +#define CRPT_ECC_CTL_CURVEM_Msk (0x3fful << CRPT_ECC_CTL_CURVEM_Pos) /*!< CRPT_T::ECC_CTL: CURVEM Mask */ + +#define CRPT_ECC_STS_BUSY_Pos (0) /*!< CRPT_T::ECC_STS: BUSY Position */ +#define CRPT_ECC_STS_BUSY_Msk (0x1ul << CRPT_ECC_STS_BUSY_Pos) /*!< CRPT_T::ECC_STS: BUSY Mask */ + +#define CRPT_ECC_STS_DMABUSY_Pos (1) /*!< CRPT_T::ECC_STS: DMABUSY Position */ +#define CRPT_ECC_STS_DMABUSY_Msk (0x1ul << CRPT_ECC_STS_DMABUSY_Pos) /*!< CRPT_T::ECC_STS: DMABUSY Mask */ + +#define CRPT_ECC_STS_BUSERR_Pos (16) /*!< CRPT_T::ECC_STS: BUSERR Position */ +#define CRPT_ECC_STS_BUSERR_Msk (0x1ul << CRPT_ECC_STS_BUSERR_Pos) /*!< CRPT_T::ECC_STS: BUSERR Mask */ + +#define CRPT_ECC_STS_KSERR_Pos (17) /*!< CRPT_T::ECC_STS: KSERR Position */ +#define CRPT_ECC_STS_KSERR_Msk (0x1ul << CRPT_ECC_STS_KSERR_Pos) /*!< CRPT_T::ECC_STS: KSERR Mask */ + +#define CRPT_ECC_X1_Pos (0) /*!< CRPT_T::ECC_X1: POINTX Position */ +#define CRPT_ECC_X1_Msk (0xfffffffful << CRPT_ECC_X1_Pos) /*!< CRPT_T::ECC_X1: POINTX Mask */ + + +#define CRPT_ECC_X2_Pos (0) /*!< CRPT_T::ECC_X2: POINTX2 Position */ +#define CRPT_ECC_X2TX_Msk (0xfffffffful << CRPT_ECC_X2_Pos) /*!< CRPT_T::ECC_X2: POINTX2 Mask */ + + +#define CRPT_ECC_Y2_Pos (0) /*!< CRPT_T::ECC_Y2: POINTY2 Position */ +#define CRPT_ECC_Y2_Msk (0xfffffffful << CRPT_ECC_Y2_Pos) /*!< CRPT_T::ECC_Y2: POINTY2 Mask */ + +#define CRPT_ECC_A_Pos (0) /*!< CRPT_T::ECC_A: CURVEA Position */ +#define CRPT_ECC_A_Msk (0xfffffffful << CRPT_ECC_A_Pos) /*!< CRPT_T::ECC_A: CURVEA Mask */ + +#define CRPT_ECC_B_Pos (0) /*!< CRPT_T::ECC_B: CURVEB Position */ +#define CRPT_ECC_B_Msk (0xfffffffful << CRPT_ECC_B_Pos) /*!< CRPT_T::ECC_B: CURVEB Mask */ + +#define CRPT_ECC_N_Pos (0) /*!< CRPT_T::ECC_N: SCALARK Position */ +#define CRPT_ECC_N_Msk (0xfffffffful << CRPT_ECC_N_Pos) /*!< CRPT_T::ECC_N: SCALARK Mask */ + +#define CRPT_ECC_DADDR_DADDR_Pos (0) /*!< CRPT_T::ECC_DADDR: DADDR Position */ +#define CRPT_ECC_DADDR_DADDR_Msk (0xfffffffful << CRPT_ECC_DADDR_DADDR_Pos) /*!< CRPT_T::ECC_DADDR: DADDR Mask */ + +#define CRPT_ECC_STARTREG_STARTREG_Pos (0) /*!< CRPT_T::ECC_STARTREG: STARTREG Position*/ +#define CRPT_ECC_STARTREG_STARTREG_Msk (0xfffffffful << CRPT_ECC_STARTREG_STARTREG_Pos) /*!< CRPT_T::ECC_STARTREG: STARTREG Mask */ + +#define CRPT_ECC_WORDCNT_WORDCNT_Pos (0) /*!< CRPT_T::ECC_WORDCNT: WORDCNT Position*/ +#define CRPT_ECC_WORDCNT_WORDCNT_Msk (0xfffffffful << CRPT_ECC_WORDCNT_WORDCNT_Pos) /*!< CRPT_T::ECC_WORDCNT: WORDCNT Mask */ + +#define CRPT_RSA_CTL_START_Pos (0) /*!< CRPT_T::RSA_CTL: START Position */ +#define CRPT_RSA_CTL_START_Msk (0x1ul << CRPT_RSA_CTL_START_Pos) /*!< CRPT_T::RSA_CTL: START Mask */ + +#define CRPT_RSA_CTL_STOP_Pos (1) /*!< CRPT_T::RSA_CTL: STOP Position */ +#define CRPT_RSA_CTL_STOP_Msk (0x1ul << CRPT_RSA_CTL_STOP_Pos) /*!< CRPT_T::RSA_CTL: STOP Mask */ + +#define CRPT_RSA_CTL_CRT_Pos (2) /*!< CRPT_T::RSA_CTL: CRT Position */ +#define CRPT_RSA_CTL_CRT_Msk (0x1ul << CRPT_RSA_CTL_CRT_Pos) /*!< CRPT_T::RSA_CTL: CRT Mask */ + +#define CRPT_RSA_CTL_CRTBYP_Pos (3) /*!< CRPT_T::RSA_CTL: CRTBYP Position */ +#define CRPT_RSA_CTL_CRTBYP_Msk (0x1ul << CRPT_RSA_CTL_CRTBYP_Pos) /*!< CRPT_T::RSA_CTL: CRTBYP Mask */ + +#define CRPT_RSA_CTL_KEYLENG_Pos (4) /*!< CRPT_T::RSA_CTL: KEYLENG Position */ +#define CRPT_RSA_CTL_KEYLENG_Msk (0x3ul << CRPT_RSA_CTL_KEYLENG_Pos) /*!< CRPT_T::RSA_CTL: KEYLENG Mask */ + +#define CRPT_RSA_CTL_SCAP_Pos (8) /*!< CRPT_T::RSA_CTL: SCAP Position */ +#define CRPT_RSA_CTL_SCAP_Msk (0x1ul << CRPT_RSA_CTL_SCAP_Pos) /*!< CRPT_T::RSA_CTL: SCAP Mask */ + +#define CRPT_RSA_STS_BUSY_Pos (0) /*!< CRPT_T::RSA_STS: BUSY Position */ +#define CRPT_RSA_STS_BUSY_Msk (0x1ul << CRPT_RSA_STS_BUSY_Pos) /*!< CRPT_T::RSA_STS: BUSY Mask */ + +#define CRPT_RSA_STS_DMABUSY_Pos (1) /*!< CRPT_T::RSA_STS: DMABUSY Position */ +#define CRPT_RSA_STS_DMABUSY_Msk (0x1ul << CRPT_RSA_STS_DMABUSY_Pos) /*!< CRPT_T::RSA_STS: DMABUSY Mask */ + +#define CRPT_RSA_STS_BUSERR_Pos (16) /*!< CRPT_T::RSA_STS: BUSERR Position */ +#define CRPT_RSA_STS_BUSERR_Msk (0x1ul << CRPT_RSA_STS_BUSERR_Pos) /*!< CRPT_T::RSA_STS: BUSERR Mask */ + +#define CRPT_RSA_STS_CTLERR_Pos (17) /*!< CRPT_T::RSA_STS: CTLERR Position */ +#define CRPT_RSA_STS_CTLERR_Msk (0x1ul << CRPT_RSA_STS_CTLERR_Pos) /*!< CRPT_T::RSA_STS: CTLERR Mask */ + +#define CRPT_RSA_STS_KSERR_Pos (18) /*!< CRPT_T::RSA_STS: KSERR Position */ +#define CRPT_RSA_STS_KSERR_Msk (0x1ul << CRPT_RSA_STS_KSERR_Pos) /*!< CRPT_T::RSA_STS: KSERR Mask */ + +#define CRPT_RSA_SADDR_Pos (0) /*!< CRPT_T::RSA_SADDR: SADDR Position */ +#define CRPT_RSA_SADDR_Msk (0xfffffffful << CRPT_RSA_SADDR_Pos) /*!< CRPT_T::RSA_SADDR: SADDR Mask */ + +#define CRPT_RSA_DADDR_Pos (0) /*!< CRPT_T::RSA_DADDR: DADDR Position */ +#define CRPT_RSA_DADDR_Msk (0xfffffffful << CRPT_RSA_DADDR_Pos) /*!< CRPT_T::RSA_DADDR: DADDR Mask */ + +#define CRPT_RSA_MADDR_Pos (0) /*!< CRPT_T::RSA_MADDR: MADDR Position */ +#define CRPT_RSA_MADDR_Msk (0xfffffffful << CRPT_RSA_MADDR_Pos) /*!< CRPT_T::RSA_MADDR: MADDR Mask */ + +#define CRPT_PRNG_KSCTL_NUM_Pos (0) /*!< CRPT_T::PRNG_KSCTL: NUM Position */ +#define CRPT_PRNG_KSCTL_NUM_Msk (0x1ful << CRPT_PRNG_KSCTL_NUM_Pos) /*!< CRPT_T::PRNG_KSCTL: NUM Mask */ + +#define CRPT_PRNG_KSCTL_TRUST_Pos (16) /*!< CRPT_T::PRNG_KSCTL: TRUST Position */ +#define CRPT_PRNG_KSCTL_TRUST_Msk (0x1ul << CRPT_PRNG_KSCTL_TRUST_Pos) /*!< CRPT_T::PRNG_KSCTL: TRUST Mask */ + +#define CRPT_PRNG_KSCTL_PRIV_Pos (18) /*!< CRPT_T::PRNG_KSCTL: PRIV Position */ +#define CRPT_PRNG_KSCTL_PRIV_Msk (0x1ul << CRPT_PRNG_KSCTL_PRIV_Pos) /*!< CRPT_T::PRNG_KSCTL: PRIV Mask */ + +#define CRPT_PRNG_KSCTL_ECDH_Pos (19) /*!< CRPT_T::PRNG_KSCTL: ECDH Position */ +#define CRPT_PRNG_KSCTL_ECDH_Msk (0x1ul << CRPT_PRNG_KSCTL_ECDH_Pos) /*!< CRPT_T::PRNG_KSCTL: ECDH Mask */ + +#define CRPT_PRNG_KSCTL_ECDSA_Pos (20) /*!< CRPT_T::PRNG_KSCTL: ECDSA Position */ +#define CRPT_PRNG_KSCTL_ECDSA_Msk (0x1ul << CRPT_PRNG_KSCTL_ECDSA_Pos) /*!< CRPT_T::PRNG_KSCTL: ECDSA Mask */ + +#define CRPT_PRNG_KSCTL_WDST_Pos (21) /*!< CRPT_T::PRNG_KSCTL: WDST Position */ +#define CRPT_PRNG_KSCTL_WDST_Msk (0x1ul << CRPT_PRNG_KSCTL_WDST_Pos) /*!< CRPT_T::PRNG_KSCTL: WDST Mask */ + +#define CRPT_PRNG_KSCTL_WSDST_Pos (22) /*!< CRPT_T::PRNG_KSCTL: WSDST Position */ +#define CRPT_PRNG_KSCTL_WSDST_Msk (0x3ul << CRPT_PRNG_KSCTL_WSDST_Pos) /*!< CRPT_T::PRNG_KSCTL: WSDST Mask */ + +#define CRPT_PRNG_KSCTL_OWNER_Pos (24) /*!< CRPT_T::PRNG_KSCTL: OWNER Position */ +#define CRPT_PRNG_KSCTL_OWNER_Msk (0x7ul << CRPT_PRNG_KSCTL_OWNER_Pos) /*!< CRPT_T::PRNG_KSCTL: OWNER Mask */ + +#define CRPT_PRNG_KSSTS_NUM_Pos (0) /*!< CRPT_T::PRNG_KSSTS: NUM Position */ +#define CRPT_PRNG_KSSTS_NUM_Msk (0x1ful << CRPT_PRNG_KSSTS_NUM_Pos) /*!< CRPT_T::PRNG_KSSTS: NUM Mask */ + +#define CRPT_PRNG_KSSTS_KCTLERR_Pos (16) /*!< CRPT_T::PRNG_KSSTS: KCTLERR Position */ +#define CRPT_PRNG_KSSTS_KCTLERR_Msk (0x1ul << CRPT_PRNG_KSSTS_KCTLERR_Pos) /*!< CRPT_T::PRNG_KSSTS: KCTLERR Mask */ + +#define CRPT_AES_KSCTL_NUM_Pos (0) /*!< CRPT_T::AES_KSCTL: NUM Position */ +#define CRPT_AES_KSCTL_NUM_Msk (0x1ful << CRPT_AES_KSCTL_NUM_Pos) /*!< CRPT_T::AES_KSCTL: NUM Mask */ + +#define CRPT_AES_KSCTL_RSRC_Pos (5) /*!< CRPT_T::AES_KSCTL: RSRC Position */ +#define CRPT_AES_KSCTL_RSRC_Msk (0x1ul << CRPT_AES_KSCTL_RSRC_Pos) /*!< CRPT_T::AES_KSCTL: RSRC Mask */ + +#define CRPT_AES_KSCTL_RSSRC_Pos (6) /*!< CRPT_T::AES_KSCTL: RSSRC Position */ +#define CRPT_AES_KSCTL_RSSRC_Msk (0x3ul << CRPT_AES_KSCTL_RSSRC_Pos) /*!< CRPT_T::AES_KSCTL: RSSRC Mask */ + +#define CRPT_HMAC_KSCTL_NUM_Pos (0) /*!< CRPT_T::HMAC_KSCTL: NUM Position */ +#define CRPT_HMAC_KSCTL_NUM_Msk (0x1ful << CRPT_HMAC_KSCTL_NUM_Pos) /*!< CRPT_T::HMAC_KSCTL: NUM Mask */ + +#define CRPT_HMAC_KSCTL_RSRC_Pos (5) /*!< CRPT_T::HMAC_KSCTL: RSRC Position */ +#define CRPT_HMAC_KSCTL_RSRC_Msk (0x1ul << CRPT_HMAC_KSCTL_RSRC_Pos) /*!< CRPT_T::HMAC_KSCTL: RSRC Mask */ + +#define CRPT_HMAC_KSCTL_RSSRC_Pos (6) /*!< CRPT_T::HMAC_KSCTL: RSSRC Position */ +#define CRPT_HMAC_KSCTL_RSSRC_Msk (0x3ul << CRPT_HMAC_KSCTL_RSSRC_Pos) /*!< CRPT_T::HMAC_KSCTL: RSSRC Mask */ + +#define CRPT_ECC_KSCTL_NUMK_Pos (0) /*!< CRPT_T::ECC_KSCTL: NUMK Position */ +#define CRPT_ECC_KSCTL_NUMK_Msk (0x1ful << CRPT_ECC_KSCTL_NUMK_Pos) /*!< CRPT_T::ECC_KSCTL: NUMK Mask */ + +#define CRPT_ECC_KSCTL_RSRCK_Pos (5) /*!< CRPT_T::ECC_KSCTL: RSRCK Position */ +#define CRPT_ECC_KSCTL_RSRCK_Msk (0x1ul << CRPT_ECC_KSCTL_RSRCK_Pos) /*!< CRPT_T::ECC_KSCTL: RSRCK Mask */ + +#define CRPT_ECC_KSCTL_RSSRCK_Pos (6) /*!< CRPT_T::ECC_KSCTL: RSSRCK Position */ +#define CRPT_ECC_KSCTL_RSSRCK_Msk (0x3ul << CRPT_ECC_KSCTL_RSSRCK_Pos) /*!< CRPT_T::ECC_KSCTL: RSSRCK Mask */ + +#define CRPT_ECC_KSCTL_ECDH_Pos (14) /*!< CRPT_T::ECC_KSCTL: ECDH Position */ +#define CRPT_ECC_KSCTL_ECDH_Msk (0x1ul << CRPT_ECC_KSCTL_ECDH_Pos) /*!< CRPT_T::ECC_KSCTL: ECDH Mask */ + +#define CRPT_ECC_KSCTL_TRUST_Pos (16) /*!< CRPT_T::ECC_KSCTL: TRUST Position */ +#define CRPT_ECC_KSCTL_TRUST_Msk (0x1ul << CRPT_ECC_KSCTL_TRUST_Pos) /*!< CRPT_T::ECC_KSCTL: TRUST Mask */ + +#define CRPT_ECC_KSCTL_PRIV_Pos (18) /*!< CRPT_T::ECC_KSCTL: PRIV Position */ +#define CRPT_ECC_KSCTL_PRIV_Msk (0x1ul << CRPT_ECC_KSCTL_PRIV_Pos) /*!< CRPT_T::ECC_KSCTL: PRIV Mask */ + +#define CRPT_ECC_KSCTL_XY_Pos (20) /*!< CRPT_T::ECC_KSCTL: XY Position */ +#define CRPT_ECC_KSCTL_XY_Msk (0x1ul << CRPT_ECC_KSCTL_XY_Pos) /*!< CRPT_T::ECC_KSCTL: XY Mask */ + +#define CRPT_ECC_KSCTL_WDST_Pos (21) /*!< CRPT_T::ECC_KSCTL: WDST Position */ +#define CRPT_ECC_KSCTL_WDST_Msk (0x1ul << CRPT_ECC_KSCTL_WDST_Pos) /*!< CRPT_T::ECC_KSCTL: WDST Mask */ + +#define CRPT_ECC_KSCTL_WSDST_Pos (22) /*!< CRPT_T::ECC_KSCTL: WSDST Position */ +#define CRPT_ECC_KSCTL_WSDST_Msk (0x3ul << CRPT_ECC_KSCTL_WSDST_Pos) /*!< CRPT_T::ECC_KSCTL: WSDST Mask */ + +#define CRPT_ECC_KSCTL_OWNER_Pos (24) /*!< CRPT_T::ECC_KSCTL: OWNER Position */ +#define CRPT_ECC_KSCTL_OWNER_Msk (0x7ul << CRPT_ECC_KSCTL_OWNER_Pos) /*!< CRPT_T::ECC_KSCTL: OWNER Mask */ + +#define CRPT_ECC_KSSTS_NUM_Pos (0) /*!< CRPT_T::ECC_KSSTS: NUM Position */ +#define CRPT_ECC_KSSTS_NUM_Msk (0x1ful << CRPT_ECC_KSSTS_NUM_Pos) /*!< CRPT_T::ECC_KSSTS: NUM Mask */ + +#define CRPT_ECC_KSXY_NUMX_Pos (0) /*!< CRPT_T::ECC_KSXY: NUMX Position */ +#define CRPT_ECC_KSXY_NUMX_Msk (0x1ful << CRPT_ECC_KSXY_NUMX_Pos) /*!< CRPT_T::ECC_KSXY: NUMX Mask */ + +#define CRPT_ECC_KSXY_RSRCXY_Pos (5) /*!< CRPT_T::ECC_KSXY: RSRCXY Position */ +#define CRPT_ECC_KSXY_RSRCXY_Msk (0x1ul << CRPT_ECC_KSXY_RSRCXY_Pos) /*!< CRPT_T::ECC_KSXY: RSRCXY Mask */ + +#define CRPT_ECC_KSXY_RSSRCX_Pos (6) /*!< CRPT_T::ECC_KSXY: RSSRCX Position */ +#define CRPT_ECC_KSXY_RSSRCX_Msk (0x3ul << CRPT_ECC_KSXY_RSSRCX_Pos) /*!< CRPT_T::ECC_KSXY: RSSRCX Mask */ + +#define CRPT_ECC_KSXY_NUMY_Pos (8) /*!< CRPT_T::ECC_KSXY: NUMY Position */ +#define CRPT_ECC_KSXY_NUMY_Msk (0x1ful << CRPT_ECC_KSXY_NUMY_Pos) /*!< CRPT_T::ECC_KSXY: NUMY Mask */ + +#define CRPT_ECC_KSXY_RSSRCY_Pos (14) /*!< CRPT_T::ECC_KSXY: RSSRCY Position */ +#define CRPT_ECC_KSXY_RSSRCY_Msk (0x3ul << CRPT_ECC_KSXY_RSSRCY_Pos) /*!< CRPT_T::ECC_KSXY: RSSRCY Mask */ + +#define CRPT_RSA_KSCTL_NUM_Pos (0) /*!< CRPT_T::RSA_KSCTL: NUM Position */ +#define CRPT_RSA_KSCTL_NUM_Msk (0x1ful << CRPT_RSA_KSCTL_NUM_Pos) /*!< CRPT_T::RSA_KSCTL: NUM Mask */ + +#define CRPT_RSA_KSCTL_RSRC_Pos (5) /*!< CRPT_T::RSA_KSCTL: RSRC Position */ +#define CRPT_RSA_KSCTL_RSRC_Msk (0x1ul << CRPT_RSA_KSCTL_RSRC_Pos) /*!< CRPT_T::RSA_KSCTL: RSRC Mask */ + +#define CRPT_RSA_KSCTL_RSSRC_Pos (6) /*!< CRPT_T::RSA_KSCTL: RSSRC Position */ +#define CRPT_RSA_KSCTL_RSSRC_Msk (0x3ul << CRPT_RSA_KSCTL_RSSRC_Pos) /*!< CRPT_T::RSA_KSCTL: RSSRC Mask */ + +#define CRPT_RSA_KSCTL_BKNUM_Pos (8) /*!< CRPT_T::RSA_KSCTL: BKNUM Position */ +#define CRPT_RSA_KSCTL_BKNUM_Msk (0x1ful << CRPT_RSA_KSCTL_BKNUM_Pos) /*!< CRPT_T::RSA_KSCTL: BKNUM Mask */ + +#define CRPT_RSA_KSSTS0_NUM0_Pos (0) /*!< CRPT_T::RSA_KSSTS0: NUM0 Position */ +#define CRPT_RSA_KSSTS0_NUM0_Msk (0x1ful << CRPT_RSA_KSSTS0_NUM0_Pos) /*!< CRPT_T::RSA_KSSTS0: NUM0 Mask */ + +#define CRPT_RSA_KSSTS0_NUM1_Pos (8) /*!< CRPT_T::RSA_KSSTS0: NUM1 Position */ +#define CRPT_RSA_KSSTS0_NUM1_Msk (0x1ful << CRPT_RSA_KSSTS0_NUM1_Pos) /*!< CRPT_T::RSA_KSSTS0: NUM1 Mask */ + +#define CRPT_RSA_KSSTS0_NUM2_Pos (16) /*!< CRPT_T::RSA_KSSTS0: NUM2 Position */ +#define CRPT_RSA_KSSTS0_NUM2_Msk (0x1ful << CRPT_RSA_KSSTS0_NUM2_Pos) /*!< CRPT_T::RSA_KSSTS0: NUM2 Mask */ + +#define CRPT_RSA_KSSTS0_NUM3_Pos (24) /*!< CRPT_T::RSA_KSSTS0: NUM3 Position */ +#define CRPT_RSA_KSSTS0_NUM3_Msk (0x1ful << CRPT_RSA_KSSTS0_NUM3_Pos) /*!< CRPT_T::RSA_KSSTS0: NUM3 Mask */ + +#define CRPT_RSA_KSSTS1_NUM4_Pos (0) /*!< CRPT_T::RSA_KSSTS1: NUM4 Position */ +#define CRPT_RSA_KSSTS1_NUM4_Msk (0x1ful << CRPT_RSA_KSSTS1_NUM4_Pos) /*!< CRPT_T::RSA_KSSTS1: NUM4 Mask */ + +#define CRPT_RSA_KSSTS1_NUM5_Pos (8) /*!< CRPT_T::RSA_KSSTS1: NUM5 Position */ +#define CRPT_RSA_KSSTS1_NUM5_Msk (0x1ful << CRPT_RSA_KSSTS1_NUM5_Pos) /*!< CRPT_T::RSA_KSSTS1: NUM5 Mask */ + +#define CRPT_RSA_KSSTS1_NUM6_Pos (16) /*!< CRPT_T::RSA_KSSTS1: NUM6 Position */ +#define CRPT_RSA_KSSTS1_NUM6_Msk (0x1ful << CRPT_RSA_KSSTS1_NUM6_Pos) /*!< CRPT_T::RSA_KSSTS1: NUM6 Mask */ + +#define CRPT_RSA_KSSTS1_NUM7_Pos (24) /*!< CRPT_T::RSA_KSSTS1: NUM7 Position */ +#define CRPT_RSA_KSSTS1_NUM7_Msk (0x1ful << CRPT_RSA_KSSTS1_NUM7_Pos) /*!< CRPT_T::RSA_KSSTS1: NUM7 Mask */ + +#define CRPT_VERSION_MINOR_Pos (0) /*!< CRPT_T::VERSION: MINOR Position */ +#define CRPT_VERSION_MINOR_Msk (0xfffful << CRPT_VERSION_MINOR_Pos) /*!< CRPT_T::VERSION: MINOR Mask */ + +#define CRPT_VERSION_SUB_Pos (16) /*!< CRPT_T::VERSION: SUB Position */ +#define CRPT_VERSION_SUB_Msk (0xfful << CRPT_VERSION_SUB_Pos) /*!< CRPT_T::VERSION: SUB Mask */ + +#define CRPT_VERSION_MAJOR_Pos (24) /*!< CRPT_T::VERSION: MAJOR Position */ +#define CRPT_VERSION_MAJOR_Msk (0xfful << CRPT_VERSION_MAJOR_Pos) /*!< CRPT_T::VERSION: MAJOR Mask */ + +/**@}*/ /* CRPT_CONST */ +/**@}*/ /* end of CRYPTO register group */ + + +/**@}*/ /* end of REGISTER group */ + +#endif /* __CRPT_REG_H__ */ diff --git a/Ubiquitous/XiZi/board/nuvoton-m2354/third_party_driver/include/Regs/dac_reg.h b/Ubiquitous/XiZi/board/nuvoton-m2354/third_party_driver/include/Regs/dac_reg.h new file mode 100644 index 0000000..564203d --- /dev/null +++ b/Ubiquitous/XiZi/board/nuvoton-m2354/third_party_driver/include/Regs/dac_reg.h @@ -0,0 +1,208 @@ +/**************************************************************************//** + * @file dac_reg.h + * @version V1.00 + * @brief DAC register definition header file + * + * @copyright SPDX-License-Identifier: Apache-2.0 + * @copyright Copyright (C) 2020 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ +#ifndef __DAC_REG_H__ +#define __DAC_REG_H__ + + +/** @addtogroup REGISTER Control Register + + @{ + +*/ + +/*---------------------- Digital to Analog Converter -------------------------*/ +/** + @addtogroup DAC Digital to Analog Converter(DAC) + Memory Mapped Structure for DAC Controller + @{ +*/ + + +typedef struct +{ + + + + /** + * @var DAC_T::CTL + * Offset: 0x00 DAC Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |DACEN |DAC Enable Bit + * | | |0 = DAC is Disabled. + * | | |1 = DAC is Enabled. + * |[1] |DACIEN |DAC Interrupt Enable Bit + * | | |0 = Interrupt is Disabled. + * | | |1 = Interrupt is Enabled. + * |[2] |DMAEN |DMA Mode Enable Bit + * | | |0 = DMA mode Disabled. + * | | |1 = DMA mode Enabled. + * |[3] |DMAURIEN |DMA Under-run Interrupt Enable Bit + * | | |0 = DMA under-run interrupt Disabled. + * | | |1 = DMA under-run interrupt Enabled. + * |[4] |TRGEN |Trigger Mode Enable Bit + * | | |0 = DAC event trigger mode Disabled. + * | | |1 = DAC event trigger mode Enabled. + * |[7:5] |TRGSEL |Trigger Source Selection + * | | |000 = Software trigger. + * | | |001 = External pin DAC0_ST trigger. + * | | |010 = Timer 0 trigger. + * | | |011 = Timer 1 trigger. + * | | |100 = Timer 2 trigger. + * | | |101 = Timer 3 trigger. + * | | |110 = EPWM0 trigger. + * | | |111 = EPWM1 trigger. + * |[8] |BYPASS |Bypass Buffer Mode + * | | |0 = Output voltage buffer Enabled. + * | | |1 = Output voltage buffer Disabled. + * |[10] |LALIGN |DAC Data Left-aligned Enabled Control + * | | |0 = Right alignment. + * | | |1 = Left alignment. + * |[13:12] |ETRGSEL |External Pin Trigger Selection + * | | |00 = Low level trigger. + * | | |01 = High level trigger. + * | | |10 = Falling edge trigger. + * | | |11 = Rising edge trigger. + * |[15:14] |BWSEL |DAC Data Bit-width Selection + * | | |00 = data is 12 bits. + * | | |01 = data is 8 bits. + * | | |Others = reserved. + * |[16] |GRPEN |DAC Group Mode Enable Bit + * | | |0 = DAC0 and DAC1 are not grouped. + * | | |1 = DAC0 and DAC1 are grouped. + * @var DAC_T::SWTRG + * Offset: 0x04 DAC Software Trigger Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |SWTRG |Software Trigger + * | | |0 = Software trigger Disabled. + * | | |1 = Software trigger Enabled. + * | | |User writes this bit to generate one shot pulse and it is cleared to 0 by hardware automatically; Reading this bit will always get 0. + * @var DAC_T::DAT + * Offset: 0x08 DAC Data Holding Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |DACDAT |DAC 12-bit Holding Data + * | | |These bits are written by user software which specifies 12-bit conversion data for DAC output. + * | | |The unused bits (DACDAT[3:0] in left-alignment mode and DACDAT[15:12] in right alignment mode) are ignored by DAC controller hardware. + * | | |12 bit left alignment: user has to load data into DACDAT[15:4] bits. + * | | |12 bit right alignment: user has to load data into DACDAT[11:0] bits. + * @var DAC_T::DATOUT + * Offset: 0x0C DAC Data Output Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[11:0] |DATOUT |DAC 12-bit Output Data + * | | |These bits are current digital data for DAC output conversion. + * | | |It is loaded from DAC_DAT register and user cannot write it directly. + * @var DAC_T::STATUS + * Offset: 0x10 DAC Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |FINISH |DAC Conversion Complete Finish Flag + * | | |0 = DAC is in conversion state. + * | | |1 = DAC conversion finish. + * | | |This bit set to 1 when conversion time counter counts to SETTLET. + * | | |It is cleared to 0 when DAC starts a new conversion. + * | | |User writes 1 to clear this bit to 0. + * |[1] |DMAUDR |DMA Under-run Interrupt Flag + * | | |0 = No DMA under-run error condition occurred. + * | | |1 = DMA under-run error condition occurred. + * | | |User writes 1 to clear this bit. + * |[8] |BUSY |DAC Busy Flag (Read Only) + * | | |0 = DAC is ready for next conversion. + * | | |1 = DAC is busy in conversion. + * | | |This is read only bit. + * @var DAC_T::TCTL + * Offset: 0x14 DAC Timing Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[9:0] |SETTLET |DAC Output Settling Time + * | | |User software needs to write appropriate value to these bits to meet DAC conversion settling time base on PCLK (APB clock) speed. + * | | |For example, DAC controller clock speed is 64MHz and DAC conversion setting time is 1 us, SETTLET value must be greater than 0x40. + */ + __IO uint32_t CTL; /*!< [0x0000] DAC Control Register */ + __IO uint32_t SWTRG; /*!< [0x0004] DAC Software Trigger Control Register */ + __IO uint32_t DAT; /*!< [0x0008] DAC Data Holding Register */ + __I uint32_t DATOUT; /*!< [0x000c] DAC Data Output Register */ + __IO uint32_t STATUS; /*!< [0x0010] DAC Status Register */ + __IO uint32_t TCTL; /*!< [0x0014] DAC Timing Control Register */ + +} DAC_T; + +/** + @addtogroup DAC_CONST DAC Bit Field Definition + Constant Definitions for DAC Controller + @{ +*/ + +#define DAC_CTL_DACEN_Pos (0) /*!< DAC_T::CTL: DACEN Position */ +#define DAC_CTL_DACEN_Msk (0x1ul << DAC_CTL_DACEN_Pos) /*!< DAC_T::CTL: DACEN Mask */ + +#define DAC_CTL_DACIEN_Pos (1) /*!< DAC_T::CTL: DACIEN Position */ +#define DAC_CTL_DACIEN_Msk (0x1ul << DAC_CTL_DACIEN_Pos) /*!< DAC_T::CTL: DACIEN Mask */ + +#define DAC_CTL_DMAEN_Pos (2) /*!< DAC_T::CTL: DMAEN Position */ +#define DAC_CTL_DMAEN_Msk (0x1ul << DAC_CTL_DMAEN_Pos) /*!< DAC_T::CTL: DMAEN Mask */ + +#define DAC_CTL_DMAURIEN_Pos (3) /*!< DAC_T::CTL: DMAURIEN Position */ +#define DAC_CTL_DMAURIEN_Msk (0x1ul << DAC_CTL_DMAURIEN_Pos) /*!< DAC_T::CTL: DMAURIEN Mask */ + +#define DAC_CTL_TRGEN_Pos (4) /*!< DAC_T::CTL: TRGEN Position */ +#define DAC_CTL_TRGEN_Msk (0x1ul << DAC_CTL_TRGEN_Pos) /*!< DAC_T::CTL: TRGEN Mask */ + +#define DAC_CTL_TRGSEL_Pos (5) /*!< DAC_T::CTL: TRGSEL Position */ +#define DAC_CTL_TRGSEL_Msk (0x7ul << DAC_CTL_TRGSEL_Pos) /*!< DAC_T::CTL: TRGSEL Mask */ + +#define DAC_CTL_BYPASS_Pos (8) /*!< DAC_T::CTL: BYPASS Position */ +#define DAC_CTL_BYPASS_Msk (0x1ul << DAC_CTL_BYPASS_Pos) /*!< DAC_T::CTL: BYPASS Mask */ + +#define DAC_CTL_LALIGN_Pos (10) /*!< DAC_T::CTL: LALIGN Position */ +#define DAC_CTL_LALIGN_Msk (0x1ul << DAC_CTL_LALIGN_Pos) /*!< DAC_T::CTL: LALIGN Mask */ + +#define DAC_CTL_ETRGSEL_Pos (12) /*!< DAC_T::CTL: ETRGSEL Position */ +#define DAC_CTL_ETRGSEL_Msk (0x3ul << DAC_CTL_ETRGSEL_Pos) /*!< DAC_T::CTL: ETRGSEL Mask */ + +#define DAC_CTL_BWSEL_Pos (14) /*!< DAC_T::CTL: BWSEL Position */ +#define DAC_CTL_BWSEL_Msk (0x3ul << DAC_CTL_BWSEL_Pos) /*!< DAC_T::CTL: BWSEL Mask */ + +#define DAC_CTL_GRPEN_Pos (16) /*!< DAC_T::CTL: GRPEN Position */ +#define DAC_CTL_GRPEN_Msk (0x1ul << DAC_CTL_GRPEN_Pos) /*!< DAC_T::CTL: GRPEN Mask */ + +#define DAC_SWTRG_SWTRG_Pos (0) /*!< DAC_T::SWTRG: SWTRG Position */ +#define DAC_SWTRG_SWTRG_Msk (0x1ul << DAC_SWTRG_SWTRG_Pos) /*!< DAC_T::SWTRG: SWTRG Mask */ + +#define DAC_DAT_DACDAT_Pos (0) /*!< DAC_T::DAT: DACDAT Position */ +#define DAC_DAT_DACDAT_Msk (0xfffful << DAC_DAT_DACDAT_Pos) /*!< DAC_T::DAT: DACDAT Mask */ + +#define DAC_DATOUT_DATOUT_Pos (0) /*!< DAC_T::DATOUT: DATOUT Position */ +#define DAC_DATOUT_DATOUT_Msk (0xffful << DAC_DATOUT_DATOUT_Pos) /*!< DAC_T::DATOUT: DATOUT Mask */ + +#define DAC_STATUS_FINISH_Pos (0) /*!< DAC_T::STATUS: FINISH Position */ +#define DAC_STATUS_FINISH_Msk (0x1ul << DAC_STATUS_FINISH_Pos) /*!< DAC_T::STATUS: FINISH Mask */ + +#define DAC_STATUS_DMAUDR_Pos (1) /*!< DAC_T::STATUS: DMAUDR Position */ +#define DAC_STATUS_DMAUDR_Msk (0x1ul << DAC_STATUS_DMAUDR_Pos) /*!< DAC_T::STATUS: DMAUDR Mask */ + +#define DAC_STATUS_BUSY_Pos (8) /*!< DAC_T::STATUS: BUSY Position */ +#define DAC_STATUS_BUSY_Msk (0x1ul << DAC_STATUS_BUSY_Pos) /*!< DAC_T::STATUS: BUSY Mask */ + +#define DAC_TCTL_SETTLET_Pos (0) /*!< DAC_T::TCTL: SETTLET Position */ +#define DAC_TCTL_SETTLET_Msk (0x3fful << DAC_TCTL_SETTLET_Pos) /*!< DAC_T::TCTL: SETTLET Mask */ + +/**@}*/ /* DAC_CONST */ +/**@}*/ /* end of DAC register group */ +/**@}*/ /* end of REGISTER group */ + +#endif /* __DAC_REG_H__ */ diff --git a/Ubiquitous/XiZi/board/nuvoton-m2354/third_party_driver/include/Regs/eadc_reg.h b/Ubiquitous/XiZi/board/nuvoton-m2354/third_party_driver/include/Regs/eadc_reg.h new file mode 100644 index 0000000..bedb6a6 --- /dev/null +++ b/Ubiquitous/XiZi/board/nuvoton-m2354/third_party_driver/include/Regs/eadc_reg.h @@ -0,0 +1,1707 @@ +/**************************************************************************//** + * @file eadc_reg.h + * @version V1.00 + * @brief EADC register definition header file + * + * @copyright SPDX-License-Identifier: Apache-2.0 + * @copyright Copyright (C) 2020 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ +#ifndef __EADC_REG_H__ +#define __EADC_REG_H__ + +/** @addtogroup REGISTER Control Register + + @{ + +*/ + +/*---------------------- Enhanced Analog to Digital Converter -------------------------*/ +/** + @addtogroup EADC Enhanced Analog to Digital Converter(EADC) + Memory Mapped Structure for EADC Controller + @{ +*/ + + +typedef struct +{ + + + /** + * @var EADC_T::DAT[19] + * Offset: 0x00 ADC Data Register 0~18 for Sample Module 0~18 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |RESULT |ADC Conversion Result + * | | |This field contains 12 bits conversion result. + * | | |When DMOF (EADC_CTL[9]) is set to 0, 12-bit ADC conversion result with unsigned format will be filled in RESULT[11:0] and zero will be filled in RESULT[15:12]. + * | | |When DMOF (EADC_CTL[9]) set to 1, 12-bit ADC conversion result with 2'complement format will be filled in RESULT[11:0] and signed bits to will be filled in RESULT[15:12]. + * |[16] |OV |Overrun Flag + * | | |If converted data in RESULT[11:0] has not been read before new conversion result is loaded to this register, OV is set to 1. + * | | |0 = Data in RESULT[11:0] is recent conversion result. + * | | |1 = Data in RESULT[11:0] is overwrite. + * | | |Note: It is cleared by hardware after EADC_DAT register is read. + * |[17] |VALID |Valid Flag + * | | |This bit is set to 1 when corresponding sample module channel analog input conversion is completed and cleared by hardware after EADC_DAT register is read. + * | | |0 = Data in RESULT[11:0] bits is not valid. + * | | |1 = Data in RESULT[11:0] bits is valid. + * @var EADC_T::CURDAT + * Offset: 0x4C ADC PDMA Current Transfer Data Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[17:0] |CURDAT |ADC PDMA Current Transfer Data Register + * | | |This register is a shadow register of EADC_DATn (n=0~18) for PDMA support. + * | | |This is a read only register. + * @var EADC_T::CTL + * Offset: 0x50 ADC Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |ADCEN |ADC Converter Enable Bit + * | | |0 = Disabled EADC. + * | | |1 = Enabled EADC. + * | | |Note: Before starting ADC conversion function, this bit should be set to 1 + * | | |Clear it to 0 to disable ADC converter analog circuit power consumption. + * |[1] |ADCRST |ADC Converter Control Circuits Reset + * | | |0 = No effect. + * | | |1 = Cause ADC control circuits reset to initial state, but not change the ADC registers value. + * | | |Note: ADCRST bit remains 1 during ADC reset, when ADC reset end, the ADCRST bit is automatically cleared to 0. + * |[2] |ADCIEN0 |Specific Sample Module ADC ADINT0 Interrupt Enable Bit + * | | |The ADC converter generates a conversion end ADIF0 (EADC_STATUS2[0]) upon the end of specific sample module ADC conversion + * | | |If ADCIEN0 bit is set then conversion end interrupt request ADINT0 is generated. + * | | |0 = Specific sample module ADC ADINT0 interrupt function Disabled. + * | | |1 = Specific sample module ADC ADINT0 interrupt function Enabled. + * |[3] |ADCIEN1 |Specific Sample Module ADC ADINT1 Interrupt Enable Bit + * | | |The ADC converter generates a conversion end ADIF1 (EADC_STATUS2[1]) upon the end of specific sample module ADC conversion + * | | |If ADCIEN1 bit is set then conversion end interrupt request ADINT1 is generated. + * | | |0 = Specific sample module ADC ADINT1 interrupt function Disabled. + * | | |1 = Specific sample module ADC ADINT1 interrupt function Enabled. + * |[4] |ADCIEN2 |Specific Sample Module ADC ADINT2 Interrupt Enable Bit + * | | |The ADC converter generates a conversion end ADIF2 (EADC_STATUS2[2]) upon the end of specific sample module ADC conversion + * | | |If ADCIEN2 bit is set then conversion end interrupt request ADINT2 is generated. + * | | |0 = Specific sample module ADC ADINT2 interrupt function Disabled. + * | | |1 = Specific sample module ADC ADINT2 interrupt function Enabled. + * |[5] |ADCIEN3 |Specific Sample Module ADC ADINT3 Interrupt Enable Bit + * | | |The ADC converter generates a conversion end ADIF3 (EADC_STATUS2[3]) upon the end of specific sample module ADC conversion + * | | |If ADCIEN3 bit is set then conversion end interrupt request ADINT3 is generated. + * | | |0 = Specific sample module ADC ADINT3 interrupt function Disabled. + * | | |1 = Specific sample module ADC ADINT3 interrupt function Enabled. + * |[7:6] |RESSEL |Resolution Selection + * | | |00 = 6-bit ADC result will be put at RESULT (EADC_DATn[5:0]). + * | | |01 = 8-bit ADC result will be put at RESULT (EADC_DATn[7:0]). + * | | |10 = 10-bit ADC result will be put at RESULT (EADC_DATn[9:0]). + * | | |11 = 12-bit ADC result will be put at RESULT (EADC_DATn[11:0]). + * |[8] |DIFFEN |Differential Analog Input Mode Enable Bit + * | | |0 = Single-end analog input mode. + * | | |1 = Differential analog input mode. + * |[9] |DMOF |ADC Differential Input Mode Output Format + * | | |0 = ADC conversion result will be filled in RESULT (EADC_DATn[15:0] , n= 0 ~18) with unsigned format. + * | | |1 = ADC conversion result will be filled in RESULT (EADC_DATn[15:0] , n= 0 ~18) with 2'complement format. + * @var EADC_T::SWTRG + * Offset: 0x54 ADC Sample Module Software Start Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[18:0] |SWTRG |ADC Sample Module 0~18 Software Force to Start ADC Conversion + * | | |0 = No effect. + * | | |1 = Cause an ADC conversion when the priority is given to sample module. + * | | |Note: After write this register to start ADC conversion, the EADC_PENDSTS register will show which sample module will conversion + * | | |If user want to disable the conversion of the sample module, user can write EADC_PENDSTS register to clear it. + * @var EADC_T::PENDSTS + * Offset: 0x58 ADC Start of Conversion Pending Flag Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[18:0] |STPF |ADC Sample Module 0~18 Start of Conversion Pending Flag + * | | |Read: + * | | |0 = There is no pending conversion for sample module. + * | | |1 = Sample module ADC start of conversion is pending. + * | | |Write: + * | | |1 = clear pending flag and cancel the conversion for sample module. + * | | |Note: This bit remains 1 during pending state, when the respective ADC conversion is end, the STPFn (n=0~18) bit is automatically cleared to 0 + * @var EADC_T::OVSTS + * Offset: 0x5C ADC Sample Module Start of Conversion Overrun Flag Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[18:0] |SPOVF |ADC SAMPLE0~18 Overrun Flag + * | | |0 = No sample module event overrun. + * | | |1 = Indicates a new sample module event is generated while an old one event is pending. + * | | |Note: This bit is cleared by writing 1 to it. + * @var EADC_T::SCTL[19] + * Offset: 0x80 ADC Sample Module 0~18 Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[3:0] |CHSEL |ADC Sample Module Channel Selection + * | | |00H = EADC_CH0 (slow channel). + * | | |01H = EADC_CH1 (slow channel). + * | | |02H = EADC_CH2 (slow channel). + * | | |03H = EADC_CH3 (slow channel). + * | | |04H = EADC_CH4 (slow channel). + * | | |05H = EADC_CH5 (slow channel). + * | | |06H = EADC_CH6 (slow channel). + * | | |07H = EADC_CH7 (slow channel). + * | | |08H = EADC_CH8 (slow channel). + * | | |09H = EADC_CH9 (slow channel). + * | | |0AH = EADC_CH10 (fast channel). + * | | |0BH = EADC_CH11 (fast channel). + * | | |0CH = EADC_CH12 (fast channel). + * | | |0DH = EADC_CH13 (fast channel). + * | | |0EH = EADC_CH14 (fast channel). + * | | |0FH = EADC_CH15 (fast channel). + * |[4] |EXTREN |ADC External Trigger Rising Edge Enable Bit + * | | |0 = Rising edge Disabled when ADC selects EADC0_ST as trigger source. + * | | |1 = Rising edge Enabled when ADC selects EADC0_ST as trigger source. + * |[5] |EXTFEN |ADC External Trigger Falling Edge Enable Bit + * | | |0 = Falling edge Disabled when ADC selects EADC0_ST as trigger source. + * | | |1 = Falling edge Enabled when ADC selects EADC0_ST as trigger source. + * |[7:6] |TRGDLYDIV |ADC Sample Module Start of Conversion Trigger Delay Clock Divider Selection + * | | |Trigger delay clock frequency: + * | | |00 = ADC_CLK/1. + * | | |01 = ADC_CLK/2. + * | | |10 = ADC_CLK/4. + * | | |11 = ADC_CLK/16. + * |[15:8] |TRGDLYCNT |ADC Sample Module Start of Conversion Trigger Delay Time + * | | |Trigger delay time = TRGDLYCNT x ADC_CLK x n (n=1,2,4,16 from TRGDLYDIV setting). + * |[20:16] |TRGSEL |ADC Sample Module Start of Conversion Trigger Source Selection + * | | |0H = Disable trigger. + * | | |1H = External trigger from EADC0_ST pin input. + * | | |2H = ADC ADINT0 interrupt EOC (End of conversion) pulse trigger. + * | | |3H = ADC ADINT1 interrupt EOC (End of conversion) pulse trigger. + * | | |4H = Timer0 overflow pulse trigger. + * | | |5H = Timer1 overflow pulse trigger. + * | | |6H = Timer2 overflow pulse trigger. + * | | |7H = Timer3 overflow pulse trigger. + * | | |8H = Timer4 overflow pulse trigger. + * | | |9H = Timer5 overflow pulse trigger. + * | | |AH = EPWM0TG0. + * | | |BH = EPWM0TG1. + * | | |CH = EPWM0TG2. + * | | |DH = EPWM0TG3. + * | | |EH = EPWM0TG4. + * | | |FH = EPWM0TG5. + * | | |10H = EPWM1TG0. + * | | |11H = EPWM1TG1. + * | | |12H = EPWM1TG2. + * | | |13H = EPWM1TG3. + * | | |14H = EPWM1TG4. + * | | |15H = EPWM1TG5. + * | | |16H = BPWM0TG. + * | | |17H = BPWM1TG. + * | | |other = Reserved. + * |[22] |INTPOS |Interrupt Flag Position Select + * | | |0 = Set ADIFn (EADC_STATUS2[n], n=0~3) at ADC end of conversion. + * | | |1 = Set ADIFn (EADC_STATUS2[n], n=0~3) at ADC start of conversion. + * |[23] |DBMEN |Double Buffer Mode Enable Bit + * | | |0 = Sample has one sample result register. (default). + * | | |1 = Sample has two sample result registers. + * |[31:24] |EXTSMPT |ADC Sampling Time Extend + * | | |When ADC converting at high conversion rate, the sampling time of analog input voltage may not enough if input channel loading is heavy, user can extend ADC sampling time after trigger source is coming to get enough sampling time. + * | | |The range of start delay time is from 0~255 ADC clock. + * @var EADC_T::INTSRC[4] + * Offset: 0xD0 ADC interrupt 0~3 Source Enable Control Register. + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |SPLIE0 |Sample Module 0 Interrupt Enable Bit + * | | |0 = Sample Module 0 interrupt Disabled. + * | | |1 = Sample Module 0 interrupt Enabled. + * |[1] |SPLIE1 |Sample Module 1 Interrupt Enable Bit + * | | |0 = Sample Module 1 interrupt Disabled. + * | | |1 = Sample Module 1 interrupt Enabled. + * |[2] |SPLIE2 |Sample Module 2 Interrupt Enable Bit + * | | |0 = Sample Module 2 interrupt Disabled. + * | | |1 = Sample Module 2 interrupt Enabled. + * |[3] |SPLIE3 |Sample Module 3 Interrupt Enable Bit + * | | |0 = Sample Module 3 interrupt Disabled. + * | | |1 = Sample Module 3 interrupt Enabled. + * |[4] |SPLIE4 |Sample Module 4 Interrupt Enable Bit + * | | |0 = Sample Module 4 interrupt Disabled. + * | | |1 = Sample Module 4 interrupt Enabled. + * |[5] |SPLIE5 |Sample Module 5 Interrupt Enable Bit + * | | |0 = Sample Module 5 interrupt Disabled. + * | | |1 = Sample Module 5 interrupt Enabled. + * |[6] |SPLIE6 |Sample Module 6 Interrupt Enable Bit + * | | |0 = Sample Module 6 interrupt Disabled. + * | | |1 = Sample Module 6 interrupt Enabled. + * |[7] |SPLIE7 |Sample Module 7 Interrupt Enable Bit + * | | |0 = Sample Module 7 interrupt Disabled. + * | | |1 = Sample Module 7 interrupt Enabled. + * |[8] |SPLIE8 |Sample Module 8 Interrupt Enable Bit + * | | |0 = Sample Module 8 interrupt Disabled. + * | | |1 = Sample Module 8 interrupt Enabled. + * |[9] |SPLIE9 |Sample Module 9 Interrupt Enable Bit + * | | |0 = Sample Module 9 interrupt Disabled. + * | | |1 = Sample Module 9 interrupt Enabled. + * |[10] |SPLIE10 |Sample Module 10 Interrupt Enable Bit + * | | |0 = Sample Module 10 interrupt Disabled. + * | | |1 = Sample Module 10 interrupt Enabled. + * |[11] |SPLIE11 |Sample Module 11 Interrupt Enable Bit + * | | |0 = Sample Module 11 interrupt Disabled. + * | | |1 = Sample Module 11 interrupt Enabled. + * |[12] |SPLIE12 |Sample Module 12 Interrupt Enable Bit + * | | |0 = Sample Module 12 interrupt Disabled. + * | | |1 = Sample Module 12 interrupt Enabled. + * |[13] |SPLIE13 |Sample Module 13 Interrupt Enable Bit + * | | |0 = Sample Module 13 interrupt Disabled. + * | | |1 = Sample Module 13 interrupt Enabled. + * |[14] |SPLIE14 |Sample Module 14 Interrupt Enable Bit + * | | |0 = Sample Module 14 interrupt Disabled. + * | | |1 = Sample Module 14 interrupt Enabled. + * |[15] |SPLIE15 |Sample Module 15 Interrupt Enable Bit + * | | |0 = Sample Module 15 interrupt Disabled. + * | | |1 = Sample Module 15 interrupt Enabled. + * |[16] |SPLIE16 |Sample Module 16 Interrupt Enable Bit + * | | |0 = Sample Module 16 interrupt Disabled. + * | | |1 = Sample Module 16 interrupt Enabled. + * |[17] |SPLIE17 |Sample Module 17 Interrupt Enable Bit + * | | |0 = Sample Module 17 interrupt Disabled. + * | | |1 = Sample Module 17 interrupt Enabled. + * |[18] |SPLIE18 |Sample Module 18 Interrupt Enable Bit + * | | |0 = Sample Module 18 interrupt Disabled. + * | | |1 = Sample Module 18 interrupt Enabled. + * @var EADC_T::CMP[4] + * Offset: 0xE0 ADC Result Compare Register 0~3 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |ADCMPEN |ADC Result Compare Enable Bit + * | | |0 = Compare Disabled. + * | | |1 = Compare Enabled. + * | | |Set this bit to 1 to enable compare CMPDAT (EADC_CMPn[27:16], n=0~3) with specified sample module conversion result when converted data is loaded into EADC_DAT register. + * |[1] |ADCMPIE |ADC Result Compare Interrupt Enable Bit + * | | |0 = Compare function interrupt Disabled. + * | | |1 = Compare function interrupt Enabled. + * | | |If the compare function is enabled and the compare condition matches the setting of CMPCOND (EADC_CMPn[2], n=0~3) and CMPMCNT (EADC_CMPn[11:8], n=0~3), ADCMPFn (EADC_STATUS2[7:4], n=0~3) will be asserted, in the meanwhile, if ADCMPIE is set to 1, a compare interrupt request is generated. + * |[2] |CMPCOND |Compare Condition + * | | |0= Set the compare condition as that when a 12-bit ADC conversion result is less than the 12-bit CMPDAT (EADC_CMPn [27:16]), the internal match counter will increase one. + * | | |1= Set the compare condition as that when a 12-bit ADC conversion result is greater or equal to the 12-bit CMPDAT (EADC_CMPn [27:16]), the internal match counter will increase one. + * | | |Note: When the internal counter reaches the value to (CMPMCNT (EADC_CMPn[11:8], n=0~3) +1), the CMPF bit will be set. + * |[7:3] |CMPSPL |Compare Sample Module Selection + * | | |00000 = Sample Module 0 conversion result EADC_DAT0 is selected to be compared. + * | | |00001 = Sample Module 1 conversion result EADC_DAT1 is selected to be compared. + * | | |00010 = Sample Module 2 conversion result EADC_DAT2 is selected to be compared. + * | | |00011 = Sample Module 3 conversion result EADC_DAT3 is selected to be compared. + * | | |00100 = Sample Module 4 conversion result EADC_DAT4 is selected to be compared. + * | | |00101 = Sample Module 5 conversion result EADC_DAT5 is selected to be compared. + * | | |00110 = Sample Module 6 conversion result EADC_DAT6 is selected to be compared. + * | | |00111 = Sample Module 7 conversion result EADC_DAT7 is selected to be compared. + * | | |01000 = Sample Module 8 conversion result EADC_DAT8 is selected to be compared. + * | | |01001 = Sample Module 9 conversion result EADC_DAT9 is selected to be compared. + * | | |01010 = Sample Module 10 conversion result EADC_DAT10 is selected to be compared. + * | | |01011 = Sample Module 11 conversion result EADC_DAT11 is selected to be compared. + * | | |01100 = Sample Module 12 conversion result EADC_DAT12 is selected to be compared. + * | | |01101 = Sample Module 13 conversion result EADC_DAT13 is selected to be compared. + * | | |01110 = Sample Module 14 conversion result EADC_DAT14 is selected to be compared. + * | | |01111 = Sample Module 15 conversion result EADC_DAT15 is selected to be compared. + * | | |10000 = Sample Module 16 conversion result EADC_DAT16 is selected to be compared. + * | | |10001 = Sample Module 17 conversion result EADC_DAT17 is selected to be compared. + * | | |10010 = Sample Module 18 conversion result EADC_DAT18 is selected to be compared. + * |[11:8] |CMPMCNT |Compare Match Count + * | | |When the specified ADC sample module analog conversion result matches the compare condition defined by CMPCOND (EADC_CMPn[2], n=0~3), the internal match counter will increase 1 + * | | |If the compare result does not meet the compare condition, the internal compare match counter will reset to 0 + * | | |When the internal counter reaches the value to (CMPMCNT +1), the ADCMPFn (EADC_STATUS2[7:4], n=0~3) will be set. + * |[15] |CMPWEN |Compare Window Mode Enable Bit + * | | |0 = ADCMPF0 (EADC_STATUS2[4]) will be set when EADC_CMP0 compared condition matched + * | | |ADCMPF2 (EADC_STATUS2[6]) will be set when EADC_CMP2 compared condition matched + * | | |1 = ADCMPF0 (EADC_STATUS2[4]) will be set when both EADC_CMP0 and EADC_CMP1 compared condition matched + * | | |ADCMPF2 (EADC_STATUS2[6]) will be set when both EADC_CMP2 and EADC_CMP3 compared condition matched. + * | | |Note: This bit is only present in EADC_CMP0 and EADC_CMP2 register. + * |[27:16] |CMPDAT |Comparison Data + * | | |The 12 bits data is used to compare with conversion result of specified sample module + * | | |User can use it to monitor the external analog input pin voltage transition without imposing a load on software. + * @var EADC_T::STATUS0 + * Offset: 0xF0 ADC Status Register 0 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |VALID |EADC_DAT0~15 Data Valid Flag + * | | |It is a mirror of VALID bit in sample module ADC result data register EADC_DATn. (n=0~18). + * |[31:16] |OV |EADC_DAT0~15 Overrun Flag + * | | |It is a mirror to OV bit in sample module ADC result data register EADC_DATn. (n=0~18). + * @var EADC_T::STATUS1 + * Offset: 0xF4 ADC Status Register 1 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[2:0] |VALID |EADC_DAT16~18 Data Valid Flag + * | | |It is a mirror of VALID bit in sample module ADC result data register EADC_DATn. (n=0~18). + * |[18:16] |OV |EADC_DAT16~18 Overrun Flag + * | | |It is a mirror to OV bit in sample module ADC result data register EADC_DATn. (n=0~18). + * @var EADC_T::STATUS2 + * Offset: 0xF8 ADC Status Register 2 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |ADIF0 |ADC ADINT0 Interrupt Flag + * | | |0 = No ADINT0 interrupt pulse received. + * | | |1 = ADINT0 interrupt pulse has been received. + * | | |Note1: This bit is cleared by writing 1 to it. + * | | |Note2:This bit indicates whether an ADC conversion of specific sample module has been completed + * |[1] |ADIF1 |ADC ADINT1 Interrupt Flag + * | | |0 = No ADINT1 interrupt pulse received. + * | | |1 = ADINT1 interrupt pulse has been received. + * | | |Note1: This bit is cleared by writing 1 to it. + * | | |Note2:This bit indicates whether an ADC conversion of specific sample module has been completed + * |[2] |ADIF2 |ADC ADINT2 Interrupt Flag + * | | |0 = No ADINT2 interrupt pulse received. + * | | |1 = ADINT2 interrupt pulse has been received. + * | | |Note1: This bit is cleared by writing 1 to it. + * | | |Note2:This bit indicates whether an ADC conversion of specific sample module has been completed + * |[3] |ADIF3 |ADC ADINT3 Interrupt Flag + * | | |0 = No ADINT3 interrupt pulse received. + * | | |1 = ADINT3 interrupt pulse has been received. + * | | |Note1: This bit is cleared by writing 1 to it. + * | | |Note2:This bit indicates whether an ADC conversion of specific sample module has been completed + * |[4] |ADCMPF0 |ADC Compare 0 Flag + * | | |When the specific sample module ADC conversion result meets setting condition in EADC_CMP0 then this bit is set to 1. + * | | |0 = Conversion result in EADC_DAT does not meet EADC_CMP0 register setting. + * | | |1 = Conversion result in EADC_DAT meets EADC_CMP0 register setting. + * | | |Note: This bit is cleared by writing 1 to it. + * |[5] |ADCMPF1 |ADC Compare 1 Flag + * | | |When the specific sample module ADC conversion result meets setting condition in EADC_CMP1 then this bit is set to 1. + * | | |0 = Conversion result in EADC_DAT does not meet EADC_CMP1 register setting. + * | | |1 = Conversion result in EADC_DAT meets EADC_CMP1 register setting. + * | | |Note: This bit is cleared by writing 1 to it. + * |[6] |ADCMPF2 |ADC Compare 2 Flag + * | | |When the specific sample module ADC conversion result meets setting condition in EADC_CMP2 then this bit is set to 1. + * | | |0 = Conversion result in EADC_DAT does not meet EADC_CMP2 register setting. + * | | |1 = Conversion result in EADC_DAT meets EADC_CMP2 register setting. + * | | |Note: This bit is cleared by writing 1 to it. + * |[7] |ADCMPF3 |ADC Compare 3 Flag + * | | |When the specific sample module ADC conversion result meets setting condition in EADC_CMP3 then this bit is set to 1. + * | | |0 = Conversion result in EADC_DAT does not meet EADC_CMP3 register setting. + * | | |1 = Conversion result in EADC_DAT meets EADC_CMP3 register setting. + * | | |Note: This bit is cleared by writing 1 to it. + * |[8] |ADOVIF0 |ADC ADINT0 Interrupt Flag Overrun + * | | |0 = ADINT0 interrupt flag is not overwritten to 1. + * | | |1 = ADINT0 interrupt flag is overwritten to 1. + * | | |Note: This bit is cleared by writing 1 to it. + * |[9] |ADOVIF1 |ADC ADINT1 Interrupt Flag Overrun + * | | |0 = ADINT1 interrupt flag is not overwritten to 1. + * | | |1 = ADINT1 interrupt flag is overwritten to 1. + * | | |Note: This bit is cleared by writing 1 to it. + * |[10] |ADOVIF2 |ADC ADINT2 Interrupt Flag Overrun + * | | |0 = ADINT2 interrupt flag is not overwritten to 1. + * | | |1 = ADINT2 interrupt flag is s overwritten to 1. + * | | |Note: This bit is cleared by writing 1 to it. + * |[11] |ADOVIF3 |ADC ADINT3 Interrupt Flag Overrun + * | | |0 = ADINT3 interrupt flag is not overwritten to 1. + * | | |1 = ADINT3 interrupt flag is overwritten to 1. + * | | |Note: This bit is cleared by writing 1 to it. + * |[12] |ADCMPO0 |ADC Compare 0 Output Status (Read Only) + * | | |The 12 bits compare0 data CMPDAT0 (EADC_CMP0[27:16]) is used to compare with conversion result of specified sample module. + * | | |User can use it to monitor the external analog input pin voltage status. + * | | |0 = Conversion result in EADC_DAT less than CMPDAT0 setting. + * | | |1 = Conversion result in EADC_DAT great than or equal CMPDAT0 setting. + * |[13] |ADCMPO1 |ADC Compare 1 Output Status (Read Only) + * | | |The 12 bits compare1 data CMPDAT1 (EADC_CMP1[27:16]) is used to compare with conversion result of specified sample module. + * | | |User can use it to monitor the external analog input pin voltage status. + * | | |0 = Conversion result in EADC_DAT less than CMPDAT1 setting. + * | | |1 = Conversion result in EADC_DAT great than or equal CMPDAT1 setting. + * |[14] |ADCMPO2 |ADC Compare 2 Output Status (Read Only) + * | | |The 12 bits compare2 data CMPDAT2 (EADC_CMP2[27:16]) is used to compare with conversion result of specified sample module. + * | | |User can use it to monitor the external analog input pin voltage status. + * | | |0 = Conversion result in EADC_DAT less than CMPDAT2 setting. + * | | |1 = Conversion result in EADC_DAT great than or equal CMPDAT2 setting. + * |[15] |ADCMPO3 |ADC Compare 3 Output Status (Read Only) + * | | |The 12 bits compare3 data CMPDAT3 (EADC_CMP3[27:16]) is used to compare with conversion result of specified sample module. + * | | |User can use it to monitor the external analog input pin voltage status. + * | | |0 = Conversion result in EADC_DAT less than CMPDAT3 setting. + * | | |1 = Conversion result in EADC_DAT great than or equal CMPDAT3 setting. + * |[20:16] |CHANNEL |Current Conversion Channel (Read Only) + * | | |This filed reflects ADC current conversion channel when BUSY=1. + * | | |It is read only. + * | | |00H = EADC_CH0. + * | | |01H = EADC_CH1. + * | | |02H = EADC_CH2. + * | | |03H = EADC_CH3. + * | | |04H = EADC_CH4. + * | | |05H = EADC_CH5. + * | | |06H = EADC_CH6. + * | | |07H = EADC_CH7. + * | | |08H = EADC_CH8. + * | | |09H = EADC_CH9. + * | | |0AH = EADC_CH10. + * | | |0BH = EADC_CH11. + * | | |0CH = EADC_CH12. + * | | |0DH = EADC_CH13. + * | | |0EH = EADC_CH14. + * | | |0FH = EADC_CH15. + * | | |10H = VBG. + * | | |11H = VTEMP. + * | | |12H = VBAT/4. + * |[23] |BUSY |Busy/Idle (Read Only) + * | | |0 = EADC is in idle state. + * | | |1 = EADC is busy at conversion. + * |[24] |ADOVIF |All ADC Interrupt Flag Overrun Bits Check (Read Only) + * | | |n=0~3. + * | | |0 = None of ADINT interrupt flag ADOVIFn (EADC_STATUS2[11:8]) is overwritten to 1. + * | | |1 = Any one of ADINT interrupt flag ADOVIFn (EADC_STATUS2[11:8]) is overwritten to 1. + * | | |Note: This bit will keep 1 when any ADOVIFn Flag is equal to 1. + * |[25] |STOVF |for All ADC Sample Module Start of Conversion Overrun Flags Check (Read Only) + * | | |n=0~18. + * | | |0 = None of sample module event overrun flag SPOVFn (EADC_OVSTS[n]) is set to 1. + * | | |1 = Any one of sample module event overrun flag SPOVFn (EADC_OVSTS[n]) is set to 1. + * | | |Note: This bit will keep 1 when any SPOVFn Flag is equal to 1. + * |[26] |AVALID |for All Sample Module ADC Result Data Register EADC_DAT Data Valid Flag Check (Read Only) + * | | |n=0~18. + * | | |0 = None of sample module data register valid flag VALIDn (EADC_DATn[17]) is set to 1. + * | | |1 = Any one of sample module data register valid flag VALIDn (EADC_DATn[17]) is set to 1. + * | | |Note: This bit will keep 1 when any VALIDn Flag is equal to 1. + * |[27] |AOV |for All Sample Module ADC Result Data Register Overrun Flags Check (Read Only) + * | | |n=0~18. + * | | |0 = None of sample module data register overrun flag OVn (EADC_DATn[16]) is set to 1. + * | | |1 = Any one of sample module data register overrun flag OVn (EADC_DATn[16]) is set to 1. + * | | |Note: This bit will keep 1 when any OVn Flag is equal to 1. + * @var EADC_T::STATUS3 + * Offset: 0xFC ADC Status Register 3 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[4:0] |CURSPL |ADC Current Sample Module + * | | |This register show the current ADC is controlled by which sample module control logic modules. + * | | |If the ADC is Idle, this bit filed will set to 0x1F. + * | | |This is a read only register. + * @var EADC_T::DDAT + * Offset: 0x100-0x10C ADC Double Data Register n for Sample Module n, n=0~3 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |RESULT |ADC Conversion Results + * | | |This field contains 12 bits conversion results. + * | | |When the DMOF (EADC_CTL[9]) is set to 0, 12-bit ADC conversion result with unsigned format will be filled in RESULT [11:0] and zero will be filled in RESULT [15:12]. + * | | |When DMOF (EADC_CTL[9]) set to 1, 12-bit ADC conversion result with 2'complement format will be filled in RESULT [11:0] and signed bits to will be filled in RESULT [15:12]. + * |[16] |OV |Overrun Flag + * | | |0 = Data in RESULT (EADC_DATn[15:0], n=0~3) is recent conversion result. + * | | |1 = Data in RESULT (EADC_DATn[15:0], n=0~3) is overwrite. + * | | |If converted data in RESULT[15:0] has not been read before new conversion result is loaded to this register, OV is set to 1. + * | | |It is cleared by hardware after EADC_DDAT register is read. + * |[17] |VALID |Valid Flag + * | | |0 = Double data in RESULT (EADC_DDATn[15:0]) is not valid. + * | | |1 = Double data in RESULT (EADC_DDATn[15:0]) is valid. + * | | |This bit is set to 1 when corresponding sample module channel analog input conversion is completed and cleared by hardware after EADC_DDATn register is read. + * | | |(n=0~3). + * @var EADC_T::PWRM + * Offset: 0x110 ADC Power Management Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |PWUPRDY |ADC Power-up Sequence Completed and Ready for Conversion (Read Only) + * | | |0 = ADC is not ready for conversion may be in power down state or in the progress of power up. + * | | |1 = ADC is ready for conversion. + * |[1] |PWUCALEN |Power Up Calibration Function Enable Control + * | | |0 = Disable the function of calibration at power up. + * | | |1 = Enable the function of calibration at power up. + * | | |Note: This bit work together with CALSEL (EADC_CALCTL [3]), see the following + * | | |{PWUCALEN, CALSEL } Description: + * | | |PWUCALEN is 0 and CALSEL is 0: No need to calibrate. + * | | |PWUCALEN is 0 and CALSEL is 1: No need to calibrate. + * | | |PWUCALEN is 1 and CALSEL is 0: Load calibration word when power up. + * | | |PWUCALEN is 1 and CALSEL is 1: Calibrate when power up. + * |[3:2] |PWDMOD |ADC Power-down Mode + * | | |Set this bit fields to select ADC power down mode when system power-down. + * | | |00 = ADC Deep power down mode. + * | | |01 = ADC Power down. + * | | |10 = ADC Standby mode. + * | | |11 = ADC Deep power down mode. + * | | |Note: Different PWDMOD has different power down/up sequence, in order to avoid ADC powering up with wrong sequence; user must keep PWMOD consistent each time in power down and start up + * |[19:8] |LDOSUT |ADC Internal LDO Start-up Time + * | | |Set this bit fields to control LDO start-up time + * | | |The minimum required LDO start-up time is 20us + * | | |LDO start-up time = (1/ADC_CLK) x LDOSUT. + * @var EADC_T::CALCTL + * Offset: 0x114 ADC Calibration Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[1] |CALSTART |Calibration Functional Block Start + * | | |0 = Stops calibration functional block. + * | | |1 = Starts calibration functional block. + * | | |Note: This bit is set by SW and clear by HW after re-calibration finish + * |[2] |CALDONE |Calibration Functional Block Complete (Read Only) + * | | |0 = During a calibration. + * | | |1 = Calibration is completed. + * |[3] |CALSEL |Select Calibration Functional Block + * | | |0 = Load calibration word when calibration functional block is active. + * | | |1 = Execute calibration when calibration functional block is active. + * @var EADC_T::CALDWRD + * Offset: 0x118 ADC Calibration Load Word Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[6:0] |CALWORD |Calibration Word Bits + * | | |Write to this register with the previous calibration word before load calibration action. + * | | |Read this register after calibration done. + * | | |Note: The calibration block contains two parts CALIBRATION and LOAD CALIBRATION; if the calibration block configure as CALIBRATION; then this register represent the result of calibration when calibration is completed; if configure as LOAD CALIBRATION ; configure this register before loading calibration action, after loading calibration complete, the laoded calibration word will apply to the ADC; while in loading calibration function the loaded value will not be equal to the original CALWORD until calibration is done. + */ + + __I uint32_t DAT[19]; /*!< [0x0000~0x0048] ADC Data Register n for Sample Module n, n=0~18 */ + __I uint32_t CURDAT; /*!< [0x004c] ADC PDMA Current Transfer Data Register */ + __IO uint32_t CTL; /*!< [0x0050] ADC Control Register */ + __O uint32_t SWTRG; /*!< [0x0054] ADC Sample Module Software Start Register */ + __IO uint32_t PENDSTS; /*!< [0x0058] ADC Start of Conversion Pending Flag Register */ + __IO uint32_t OVSTS; /*!< [0x005c] ADC Sample Module Start of Conversion Overrun Flag Register */ + __I uint32_t RESERVE0[8]; + __IO uint32_t SCTL[19]; /*!< [0x0080~0x00c8] ADC Sample Module n Control Register, n=0~18 */ + __I uint32_t RESERVE1[1]; + __IO uint32_t INTSRC[4]; /*!< [0x00d0~0x00dc] ADC interrupt n Source Enable Control Register, n=0~3 */ + __IO uint32_t CMP[4]; /*!< [0x00e0~0x00ec] ADC Result Compare Register n, n=0~3 */ + __I uint32_t STATUS0; /*!< [0x00f0] ADC Status Register 0 */ + __I uint32_t STATUS1; /*!< [0x00f4] ADC Status Register 1 */ + __IO uint32_t STATUS2; /*!< [0x00f8] ADC Status Register 2 */ + __I uint32_t STATUS3; /*!< [0x00fc] ADC Status Register 3 */ + __I uint32_t DDAT[4]; /*!< [0x0100~0x010c] ADC Double Data Register n for Sample Module n, n=0~3 */ + __IO uint32_t PWRM; /*!< [0x0110] ADC Power Management Register */ + __IO uint32_t CALCTL; /*!< [0x0114] ADC Calibration Control Register */ + __IO uint32_t CALDWRD; /*!< [0x0118] ADC Calibration Load Word Register */ + __I uint32_t RESERVE2[5]; + __IO uint32_t PDMACTL; /*!< [0x0130] ADC PDMA Control Register */ + +} EADC_T; + +/** + @addtogroup EADC_CONST EADC Bit Field Definition + Constant Definitions for EADC Controller + @{ +*/ + +#define EADC_DAT_RESULT_Pos (0) /*!< EADC_T::DAT: RESULT Position */ +#define EADC_DAT_RESULT_Msk (0xfffful << EADC_DAT_RESULT_Pos) /*!< EADC_T::DAT: RESULT Mask */ + +#define EADC_DAT_OV_Pos (16) /*!< EADC_T::DAT: OV Position */ +#define EADC_DAT_OV_Msk (0x1ul << EADC_DAT_OV_Pos) /*!< EADC_T::DAT: OV Mask */ + +#define EADC_DAT_VALID_Pos (17) /*!< EADC_T::DAT: VALID Position */ +#define EADC_DAT_VALID_Msk (0x1ul << EADC_DAT_VALID_Pos) /*!< EADC_T::DAT: VALID Mask */ + +#define EADC_DAT0_RESULT_Pos (0) /*!< EADC_T::DAT0: RESULT Position */ +#define EADC_DAT0_RESULT_Msk (0xfffful << EADC_DAT0_RESULT_Pos) /*!< EADC_T::DAT0: RESULT Mask */ + +#define EADC_DAT0_OV_Pos (16) /*!< EADC_T::DAT0: OV Position */ +#define EADC_DAT0_OV_Msk (0x1ul << EADC_DAT0_OV_Pos) /*!< EADC_T::DAT0: OV Mask */ + +#define EADC_DAT0_VALID_Pos (17) /*!< EADC_T::DAT0: VALID Position */ +#define EADC_DAT0_VALID_Msk (0x1ul << EADC_DAT0_VALID_Pos) /*!< EADC_T::DAT0: VALID Mask */ + +#define EADC_DAT1_RESULT_Pos (0) /*!< EADC_T::DAT1: RESULT Position */ +#define EADC_DAT1_RESULT_Msk (0xfffful << EADC_DAT1_RESULT_Pos) /*!< EADC_T::DAT1: RESULT Mask */ + +#define EADC_DAT1_OV_Pos (16) /*!< EADC_T::DAT1: OV Position */ +#define EADC_DAT1_OV_Msk (0x1ul << EADC_DAT1_OV_Pos) /*!< EADC_T::DAT1: OV Mask */ + +#define EADC_DAT1_VALID_Pos (17) /*!< EADC_T::DAT1: VALID Position */ +#define EADC_DAT1_VALID_Msk (0x1ul << EADC_DAT1_VALID_Pos) /*!< EADC_T::DAT1: VALID Mask */ + +#define EADC_DAT2_RESULT_Pos (0) /*!< EADC_T::DAT2: RESULT Position */ +#define EADC_DAT2_RESULT_Msk (0xfffful << EADC_DAT2_RESULT_Pos) /*!< EADC_T::DAT2: RESULT Mask */ + +#define EADC_DAT2_OV_Pos (16) /*!< EADC_T::DAT2: OV Position */ +#define EADC_DAT2_OV_Msk (0x1ul << EADC_DAT2_OV_Pos) /*!< EADC_T::DAT2: OV Mask */ + +#define EADC_DAT2_VALID_Pos (17) /*!< EADC_T::DAT2: VALID Position */ +#define EADC_DAT2_VALID_Msk (0x1ul << EADC_DAT2_VALID_Pos) /*!< EADC_T::DAT2: VALID Mask */ + +#define EADC_DAT3_RESULT_Pos (0) /*!< EADC_T::DAT3: RESULT Position */ +#define EADC_DAT3_RESULT_Msk (0xfffful << EADC_DAT3_RESULT_Pos) /*!< EADC_T::DAT3: RESULT Mask */ + +#define EADC_DAT3_OV_Pos (16) /*!< EADC_T::DAT3: OV Position */ +#define EADC_DAT3_OV_Msk (0x1ul << EADC_DAT3_OV_Pos) /*!< EADC_T::DAT3: OV Mask */ + +#define EADC_DAT3_VALID_Pos (17) /*!< EADC_T::DAT3: VALID Position */ +#define EADC_DAT3_VALID_Msk (0x1ul << EADC_DAT3_VALID_Pos) /*!< EADC_T::DAT3: VALID Mask */ + +#define EADC_DAT4_RESULT_Pos (0) /*!< EADC_T::DAT4: RESULT Position */ +#define EADC_DAT4_RESULT_Msk (0xfffful << EADC_DAT4_RESULT_Pos) /*!< EADC_T::DAT4: RESULT Mask */ + +#define EADC_DAT4_OV_Pos (16) /*!< EADC_T::DAT4: OV Position */ +#define EADC_DAT4_OV_Msk (0x1ul << EADC_DAT4_OV_Pos) /*!< EADC_T::DAT4: OV Mask */ + +#define EADC_DAT4_VALID_Pos (17) /*!< EADC_T::DAT4: VALID Position */ +#define EADC_DAT4_VALID_Msk (0x1ul << EADC_DAT4_VALID_Pos) /*!< EADC_T::DAT4: VALID Mask */ + +#define EADC_DAT5_RESULT_Pos (0) /*!< EADC_T::DAT5: RESULT Position */ +#define EADC_DAT5_RESULT_Msk (0xfffful << EADC_DAT5_RESULT_Pos) /*!< EADC_T::DAT5: RESULT Mask */ + +#define EADC_DAT5_OV_Pos (16) /*!< EADC_T::DAT5: OV Position */ +#define EADC_DAT5_OV_Msk (0x1ul << EADC_DAT5_OV_Pos) /*!< EADC_T::DAT5: OV Mask */ + +#define EADC_DAT5_VALID_Pos (17) /*!< EADC_T::DAT5: VALID Position */ +#define EADC_DAT5_VALID_Msk (0x1ul << EADC_DAT5_VALID_Pos) /*!< EADC_T::DAT5: VALID Mask */ + +#define EADC_DAT6_RESULT_Pos (0) /*!< EADC_T::DAT6: RESULT Position */ +#define EADC_DAT6_RESULT_Msk (0xfffful << EADC_DAT6_RESULT_Pos) /*!< EADC_T::DAT6: RESULT Mask */ + +#define EADC_DAT6_OV_Pos (16) /*!< EADC_T::DAT6: OV Position */ +#define EADC_DAT6_OV_Msk (0x1ul << EADC_DAT6_OV_Pos) /*!< EADC_T::DAT6: OV Mask */ + +#define EADC_DAT6_VALID_Pos (17) /*!< EADC_T::DAT6: VALID Position */ +#define EADC_DAT6_VALID_Msk (0x1ul << EADC_DAT6_VALID_Pos) /*!< EADC_T::DAT6: VALID Mask */ + +#define EADC_DAT7_RESULT_Pos (0) /*!< EADC_T::DAT7: RESULT Position */ +#define EADC_DAT7_RESULT_Msk (0xfffful << EADC_DAT7_RESULT_Pos) /*!< EADC_T::DAT7: RESULT Mask */ + +#define EADC_DAT7_OV_Pos (16) /*!< EADC_T::DAT7: OV Position */ +#define EADC_DAT7_OV_Msk (0x1ul << EADC_DAT7_OV_Pos) /*!< EADC_T::DAT7: OV Mask */ + +#define EADC_DAT7_VALID_Pos (17) /*!< EADC_T::DAT7: VALID Position */ +#define EADC_DAT7_VALID_Msk (0x1ul << EADC_DAT7_VALID_Pos) /*!< EADC_T::DAT7: VALID Mask */ + +#define EADC_DAT8_RESULT_Pos (0) /*!< EADC_T::DAT8: RESULT Position */ +#define EADC_DAT8_RESULT_Msk (0xfffful << EADC_DAT8_RESULT_Pos) /*!< EADC_T::DAT8: RESULT Mask */ + +#define EADC_DAT8_OV_Pos (16) /*!< EADC_T::DAT8: OV Position */ +#define EADC_DAT8_OV_Msk (0x1ul << EADC_DAT8_OV_Pos) /*!< EADC_T::DAT8: OV Mask */ + +#define EADC_DAT8_VALID_Pos (17) /*!< EADC_T::DAT8: VALID Position */ +#define EADC_DAT8_VALID_Msk (0x1ul << EADC_DAT8_VALID_Pos) /*!< EADC_T::DAT8: VALID Mask */ + +#define EADC_DAT9_RESULT_Pos (0) /*!< EADC_T::DAT9: RESULT Position */ +#define EADC_DAT9_RESULT_Msk (0xfffful << EADC_DAT9_RESULT_Pos) /*!< EADC_T::DAT9: RESULT Mask */ + +#define EADC_DAT9_OV_Pos (16) /*!< EADC_T::DAT9: OV Position */ +#define EADC_DAT9_OV_Msk (0x1ul << EADC_DAT9_OV_Pos) /*!< EADC_T::DAT9: OV Mask */ + +#define EADC_DAT9_VALID_Pos (17) /*!< EADC_T::DAT9: VALID Position */ +#define EADC_DAT9_VALID_Msk (0x1ul << EADC_DAT9_VALID_Pos) /*!< EADC_T::DAT9: VALID Mask */ + +#define EADC_DAT10_RESULT_Pos (0) /*!< EADC_T::DAT10: RESULT Position */ +#define EADC_DAT10_RESULT_Msk (0xfffful << EADC_DAT10_RESULT_Pos) /*!< EADC_T::DAT10: RESULT Mask */ + +#define EADC_DAT10_OV_Pos (16) /*!< EADC_T::DAT10: OV Position */ +#define EADC_DAT10_OV_Msk (0x1ul << EADC_DAT10_OV_Pos) /*!< EADC_T::DAT10: OV Mask */ + +#define EADC_DAT10_VALID_Pos (17) /*!< EADC_T::DAT10: VALID Position */ +#define EADC_DAT10_VALID_Msk (0x1ul << EADC_DAT10_VALID_Pos) /*!< EADC_T::DAT10: VALID Mask */ + +#define EADC_DAT11_RESULT_Pos (0) /*!< EADC_T::DAT11: RESULT Position */ +#define EADC_DAT11_RESULT_Msk (0xfffful << EADC_DAT11_RESULT_Pos) /*!< EADC_T::DAT11: RESULT Mask */ + +#define EADC_DAT11_OV_Pos (16) /*!< EADC_T::DAT11: OV Position */ +#define EADC_DAT11_OV_Msk (0x1ul << EADC_DAT11_OV_Pos) /*!< EADC_T::DAT11: OV Mask */ + +#define EADC_DAT11_VALID_Pos (17) /*!< EADC_T::DAT11: VALID Position */ +#define EADC_DAT11_VALID_Msk (0x1ul << EADC_DAT11_VALID_Pos) /*!< EADC_T::DAT11: VALID Mask */ + +#define EADC_DAT12_RESULT_Pos (0) /*!< EADC_T::DAT12: RESULT Position */ +#define EADC_DAT12_RESULT_Msk (0xfffful << EADC_DAT12_RESULT_Pos) /*!< EADC_T::DAT12: RESULT Mask */ + +#define EADC_DAT12_OV_Pos (16) /*!< EADC_T::DAT12: OV Position */ +#define EADC_DAT12_OV_Msk (0x1ul << EADC_DAT12_OV_Pos) /*!< EADC_T::DAT12: OV Mask */ + +#define EADC_DAT12_VALID_Pos (17) /*!< EADC_T::DAT12: VALID Position */ +#define EADC_DAT12_VALID_Msk (0x1ul << EADC_DAT12_VALID_Pos) /*!< EADC_T::DAT12: VALID Mask */ + +#define EADC_DAT13_RESULT_Pos (0) /*!< EADC_T::DAT13: RESULT Position */ +#define EADC_DAT13_RESULT_Msk (0xfffful << EADC_DAT13_RESULT_Pos) /*!< EADC_T::DAT13: RESULT Mask */ + +#define EADC_DAT13_OV_Pos (16) /*!< EADC_T::DAT13: OV Position */ +#define EADC_DAT13_OV_Msk (0x1ul << EADC_DAT13_OV_Pos) /*!< EADC_T::DAT13: OV Mask */ + +#define EADC_DAT13_VALID_Pos (17) /*!< EADC_T::DAT13: VALID Position */ +#define EADC_DAT13_VALID_Msk (0x1ul << EADC_DAT13_VALID_Pos) /*!< EADC_T::DAT13: VALID Mask */ + +#define EADC_DAT14_RESULT_Pos (0) /*!< EADC_T::DAT14: RESULT Position */ +#define EADC_DAT14_RESULT_Msk (0xfffful << EADC_DAT14_RESULT_Pos) /*!< EADC_T::DAT14: RESULT Mask */ + +#define EADC_DAT14_OV_Pos (16) /*!< EADC_T::DAT14: OV Position */ +#define EADC_DAT14_OV_Msk (0x1ul << EADC_DAT14_OV_Pos) /*!< EADC_T::DAT14: OV Mask */ + +#define EADC_DAT14_VALID_Pos (17) /*!< EADC_T::DAT14: VALID Position */ +#define EADC_DAT14_VALID_Msk (0x1ul << EADC_DAT14_VALID_Pos) /*!< EADC_T::DAT14: VALID Mask */ + +#define EADC_DAT15_RESULT_Pos (0) /*!< EADC_T::DAT15: RESULT Position */ +#define EADC_DAT15_RESULT_Msk (0xfffful << EADC_DAT15_RESULT_Pos) /*!< EADC_T::DAT15: RESULT Mask */ + +#define EADC_DAT15_OV_Pos (16) /*!< EADC_T::DAT15: OV Position */ +#define EADC_DAT15_OV_Msk (0x1ul << EADC_DAT15_OV_Pos) /*!< EADC_T::DAT15: OV Mask */ + +#define EADC_DAT15_VALID_Pos (17) /*!< EADC_T::DAT15: VALID Position */ +#define EADC_DAT15_VALID_Msk (0x1ul << EADC_DAT15_VALID_Pos) /*!< EADC_T::DAT15: VALID Mask */ + +#define EADC_DAT16_RESULT_Pos (0) /*!< EADC_T::DAT16: RESULT Position */ +#define EADC_DAT16_RESULT_Msk (0xfffful << EADC_DAT16_RESULT_Pos) /*!< EADC_T::DAT16: RESULT Mask */ + +#define EADC_DAT16_OV_Pos (16) /*!< EADC_T::DAT16: OV Position */ +#define EADC_DAT16_OV_Msk (0x1ul << EADC_DAT16_OV_Pos) /*!< EADC_T::DAT16: OV Mask */ + +#define EADC_DAT16_VALID_Pos (17) /*!< EADC_T::DAT16: VALID Position */ +#define EADC_DAT16_VALID_Msk (0x1ul << EADC_DAT16_VALID_Pos) /*!< EADC_T::DAT16: VALID Mask */ + +#define EADC_DAT17_RESULT_Pos (0) /*!< EADC_T::DAT17: RESULT Position */ +#define EADC_DAT17_RESULT_Msk (0xfffful << EADC_DAT17_RESULT_Pos) /*!< EADC_T::DAT17: RESULT Mask */ + +#define EADC_DAT17_OV_Pos (16) /*!< EADC_T::DAT17: OV Position */ +#define EADC_DAT17_OV_Msk (0x1ul << EADC_DAT17_OV_Pos) /*!< EADC_T::DAT17: OV Mask */ + +#define EADC_DAT17_VALID_Pos (17) /*!< EADC_T::DAT17: VALID Position */ +#define EADC_DAT17_VALID_Msk (0x1ul << EADC_DAT17_VALID_Pos) /*!< EADC_T::DAT17: VALID Mask */ + +#define EADC_DAT18_RESULT_Pos (0) /*!< EADC_T::DAT18: RESULT Position */ +#define EADC_DAT18_RESULT_Msk (0xfffful << EADC_DAT18_RESULT_Pos) /*!< EADC_T::DAT18: RESULT Mask */ + +#define EADC_DAT18_OV_Pos (16) /*!< EADC_T::DAT18: OV Position */ +#define EADC_DAT18_OV_Msk (0x1ul << EADC_DAT18_OV_Pos) /*!< EADC_T::DAT18: OV Mask */ + +#define EADC_DAT18_VALID_Pos (17) /*!< EADC_T::DAT18: VALID Position */ +#define EADC_DAT18_VALID_Msk (0x1ul << EADC_DAT18_VALID_Pos) /*!< EADC_T::DAT18: VALID Mask */ + +#define EADC_CURDAT_CURDAT_Pos (0) /*!< EADC_T::CURDAT: CURDAT Position */ +#define EADC_CURDAT_CURDAT_Msk (0x3fffful << EADC_CURDAT_CURDAT_Pos) /*!< EADC_T::CURDAT: CURDAT Mask */ + +#define EADC_CTL_ADCEN_Pos (0) /*!< EADC_T::CTL: ADCEN Position */ +#define EADC_CTL_ADCEN_Msk (0x1ul << EADC_CTL_ADCEN_Pos) /*!< EADC_T::CTL: ADCEN Mask */ + +#define EADC_CTL_ADCRST_Pos (1) /*!< EADC_T::CTL: ADCRST Position */ +#define EADC_CTL_ADCRST_Msk (0x1ul << EADC_CTL_ADCRST_Pos) /*!< EADC_T::CTL: ADCRST Mask */ + +#define EADC_CTL_ADCIEN0_Pos (2) /*!< EADC_T::CTL: ADCIEN0 Position */ +#define EADC_CTL_ADCIEN0_Msk (0x1ul << EADC_CTL_ADCIEN0_Pos) /*!< EADC_T::CTL: ADCIEN0 Mask */ + +#define EADC_CTL_ADCIEN1_Pos (3) /*!< EADC_T::CTL: ADCIEN1 Position */ +#define EADC_CTL_ADCIEN1_Msk (0x1ul << EADC_CTL_ADCIEN1_Pos) /*!< EADC_T::CTL: ADCIEN1 Mask */ + +#define EADC_CTL_ADCIEN2_Pos (4) /*!< EADC_T::CTL: ADCIEN2 Position */ +#define EADC_CTL_ADCIEN2_Msk (0x1ul << EADC_CTL_ADCIEN2_Pos) /*!< EADC_T::CTL: ADCIEN2 Mask */ + +#define EADC_CTL_ADCIEN3_Pos (5) /*!< EADC_T::CTL: ADCIEN3 Position */ +#define EADC_CTL_ADCIEN3_Msk (0x1ul << EADC_CTL_ADCIEN3_Pos) /*!< EADC_T::CTL: ADCIEN3 Mask */ + +#define EADC_CTL_RESSEL_Pos (6) /*!< EADC_T::CTL: RESSEL Position */ +#define EADC_CTL_RESSEL_Msk (0x3ul << EADC_CTL_RESSEL_Pos) /*!< EADC_T::CTL: RESSEL Mask */ + +#define EADC_CTL_DIFFEN_Pos (8) /*!< EADC_T::CTL: DIFFEN Position */ +#define EADC_CTL_DIFFEN_Msk (0x1ul << EADC_CTL_DIFFEN_Pos) /*!< EADC_T::CTL: DIFFEN Mask */ + +#define EADC_CTL_DMOF_Pos (9) /*!< EADC_T::CTL: DMOF Position */ +#define EADC_CTL_DMOF_Msk (0x1ul << EADC_CTL_DMOF_Pos) /*!< EADC_T::CTL: DMOF Mask */ + +#define EADC_SWTRG_SWTRG_Pos (0) /*!< EADC_T::SWTRG: SWTRG Position */ +#define EADC_SWTRG_SWTRG_Msk (0x7fffful << EADC_SWTRG_SWTRG_Pos) /*!< EADC_T::SWTRG: SWTRG Mask */ + +#define EADC_PENDSTS_STPF_Pos (0) /*!< EADC_T::PENDSTS: STPF Position */ +#define EADC_PENDSTS_STPF_Msk (0x7fffful << EADC_PENDSTS_STPF_Pos) /*!< EADC_T::PENDSTS: STPF Mask */ + +#define EADC_OVSTS_SPOVF_Pos (0) /*!< EADC_T::OVSTS: SPOVF Position */ +#define EADC_OVSTS_SPOVF_Msk (0x7fffful << EADC_OVSTS_SPOVF_Pos) /*!< EADC_T::OVSTS: SPOVF Mask */ + +#define EADC_SCTL_CHSEL_Pos (0) /*!< EADC_T::SCTL: CHSEL Position */ +#define EADC_SCTL_CHSEL_Msk (0xful << EADC_SCTL_CHSEL_Pos) /*!< EADC_T::SCTL: CHSEL Mask */ + +#define EADC_SCTL_EXTREN_Pos (4) /*!< EADC_T::SCTL: EXTREN Position */ +#define EADC_SCTL_EXTREN_Msk (0x1ul << EADC_SCTL_EXTREN_Pos) /*!< EADC_T::SCTL: EXTREN Mask */ + +#define EADC_SCTL_EXTFEN_Pos (5) /*!< EADC_T::SCTL: EXTFEN Position */ +#define EADC_SCTL_EXTFEN_Msk (0x1ul << EADC_SCTL_EXTFEN_Pos) /*!< EADC_T::SCTL: EXTFEN Mask */ + +#define EADC_SCTL_TRGDLYDIV_Pos (6) /*!< EADC_T::SCTL: TRGDLYDIV Position */ +#define EADC_SCTL_TRGDLYDIV_Msk (0x3ul << EADC_SCTL_TRGDLYDIV_Pos) /*!< EADC_T::SCTL: TRGDLYDIV Mask */ + +#define EADC_SCTL_TRGDLYCNT_Pos (8) /*!< EADC_T::SCTL: TRGDLYCNT Position */ +#define EADC_SCTL_TRGDLYCNT_Msk (0xfful << EADC_SCTL_TRGDLYCNT_Pos) /*!< EADC_T::SCTL: TRGDLYCNT Mask */ + +#define EADC_SCTL_TRGSEL_Pos (16) /*!< EADC_T::SCTL: TRGSEL Position */ +#define EADC_SCTL_TRGSEL_Msk (0x1ful << EADC_SCTL_TRGSEL_Pos) /*!< EADC_T::SCTL: TRGSEL Mask */ + +#define EADC_SCTL_INTPOS_Pos (22) /*!< EADC_T::SCTL: INTPOS Position */ +#define EADC_SCTL_INTPOS_Msk (0x1ul << EADC_SCTL_INTPOS_Pos) /*!< EADC_T::SCTL: INTPOS Mask */ + +#define EADC_SCTL_DBMEN_Pos (23) /*!< EADC_T::SCTL: DBMEN Position */ +#define EADC_SCTL_DBMEN_Msk (0x1ul << EADC_SCTL_DBMEN_Pos) /*!< EADC_T::SCTL: DBMEN Mask */ + +#define EADC_SCTL_EXTSMPT_Pos (24) /*!< EADC_T::SCTL: EXTSMPT Position */ +#define EADC_SCTL_EXTSMPT_Msk (0xfful << EADC_SCTL_EXTSMPT_Pos) /*!< EADC_T::SCTL: EXTSMPT Mask */ + +#define EADC_SCTL0_CHSEL_Pos (0) /*!< EADC_T::SCTL0: CHSEL Position */ +#define EADC_SCTL0_CHSEL_Msk (0xful << EADC_SCTL0_CHSEL_Pos) /*!< EADC_T::SCTL0: CHSEL Mask */ + +#define EADC_SCTL0_EXTREN_Pos (4) /*!< EADC_T::SCTL0: EXTREN Position */ +#define EADC_SCTL0_EXTREN_Msk (0x1ul << EADC_SCTL0_EXTREN_Pos) /*!< EADC_T::SCTL0: EXTREN Mask */ + +#define EADC_SCTL0_EXTFEN_Pos (5) /*!< EADC_T::SCTL0: EXTFEN Position */ +#define EADC_SCTL0_EXTFEN_Msk (0x1ul << EADC_SCTL0_EXTFEN_Pos) /*!< EADC_T::SCTL0: EXTFEN Mask */ + +#define EADC_SCTL0_TRGDLYDIV_Pos (6) /*!< EADC_T::SCTL0: TRGDLYDIV Position */ +#define EADC_SCTL0_TRGDLYDIV_Msk (0x3ul << EADC_SCTL0_TRGDLYDIV_Pos) /*!< EADC_T::SCTL0: TRGDLYDIV Mask */ + +#define EADC_SCTL0_TRGDLYCNT_Pos (8) /*!< EADC_T::SCTL0: TRGDLYCNT Position */ +#define EADC_SCTL0_TRGDLYCNT_Msk (0xfful << EADC_SCTL0_TRGDLYCNT_Pos) /*!< EADC_T::SCTL0: TRGDLYCNT Mask */ + +#define EADC_SCTL0_TRGSEL_Pos (16) /*!< EADC_T::SCTL0: TRGSEL Position */ +#define EADC_SCTL0_TRGSEL_Msk (0x1ful << EADC_SCTL0_TRGSEL_Pos) /*!< EADC_T::SCTL0: TRGSEL Mask */ + +#define EADC_SCTL0_INTPOS_Pos (22) /*!< EADC_T::SCTL0: INTPOS Position */ +#define EADC_SCTL0_INTPOS_Msk (0x1ul << EADC_SCTL0_INTPOS_Pos) /*!< EADC_T::SCTL0: INTPOS Mask */ + +#define EADC_SCTL0_DBMEN_Pos (23) /*!< EADC_T::SCTL0: DBMEN Position */ +#define EADC_SCTL0_DBMEN_Msk (0x1ul << EADC_SCTL0_DBMEN_Pos) /*!< EADC_T::SCTL0: DBMEN Mask */ + +#define EADC_SCTL0_EXTSMPT_Pos (24) /*!< EADC_T::SCTL0: EXTSMPT Position */ +#define EADC_SCTL0_EXTSMPT_Msk (0xfful << EADC_SCTL0_EXTSMPT_Pos) /*!< EADC_T::SCTL0: EXTSMPT Mask */ + +#define EADC_SCTL1_CHSEL_Pos (0) /*!< EADC_T::SCTL1: CHSEL Position */ +#define EADC_SCTL1_CHSEL_Msk (0xful << EADC_SCTL1_CHSEL_Pos) /*!< EADC_T::SCTL1: CHSEL Mask */ + +#define EADC_SCTL1_EXTREN_Pos (4) /*!< EADC_T::SCTL1: EXTREN Position */ +#define EADC_SCTL1_EXTREN_Msk (0x1ul << EADC_SCTL1_EXTREN_Pos) /*!< EADC_T::SCTL1: EXTREN Mask */ + +#define EADC_SCTL1_EXTFEN_Pos (5) /*!< EADC_T::SCTL1: EXTFEN Position */ +#define EADC_SCTL1_EXTFEN_Msk (0x1ul << EADC_SCTL1_EXTFEN_Pos) /*!< EADC_T::SCTL1: EXTFEN Mask */ + +#define EADC_SCTL1_TRGDLYDIV_Pos (6) /*!< EADC_T::SCTL1: TRGDLYDIV Position */ +#define EADC_SCTL1_TRGDLYDIV_Msk (0x3ul << EADC_SCTL1_TRGDLYDIV_Pos) /*!< EADC_T::SCTL1: TRGDLYDIV Mask */ + +#define EADC_SCTL1_TRGDLYCNT_Pos (8) /*!< EADC_T::SCTL1: TRGDLYCNT Position */ +#define EADC_SCTL1_TRGDLYCNT_Msk (0xfful << EADC_SCTL1_TRGDLYCNT_Pos) /*!< EADC_T::SCTL1: TRGDLYCNT Mask */ + +#define EADC_SCTL1_TRGSEL_Pos (16) /*!< EADC_T::SCTL1: TRGSEL Position */ +#define EADC_SCTL1_TRGSEL_Msk (0x1ful << EADC_SCTL1_TRGSEL_Pos) /*!< EADC_T::SCTL1: TRGSEL Mask */ + +#define EADC_SCTL1_INTPOS_Pos (22) /*!< EADC_T::SCTL1: INTPOS Position */ +#define EADC_SCTL1_INTPOS_Msk (0x1ul << EADC_SCTL1_INTPOS_Pos) /*!< EADC_T::SCTL1: INTPOS Mask */ + +#define EADC_SCTL1_DBMEN_Pos (23) /*!< EADC_T::SCTL1: DBMEN Position */ +#define EADC_SCTL1_DBMEN_Msk (0x1ul << EADC_SCTL1_DBMEN_Pos) /*!< EADC_T::SCTL1: DBMEN Mask */ + +#define EADC_SCTL1_EXTSMPT_Pos (24) /*!< EADC_T::SCTL1: EXTSMPT Position */ +#define EADC_SCTL1_EXTSMPT_Msk (0xfful << EADC_SCTL1_EXTSMPT_Pos) /*!< EADC_T::SCTL1: EXTSMPT Mask */ + +#define EADC_SCTL2_CHSEL_Pos (0) /*!< EADC_T::SCTL2: CHSEL Position */ +#define EADC_SCTL2_CHSEL_Msk (0xful << EADC_SCTL2_CHSEL_Pos) /*!< EADC_T::SCTL2: CHSEL Mask */ + +#define EADC_SCTL2_EXTREN_Pos (4) /*!< EADC_T::SCTL2: EXTREN Position */ +#define EADC_SCTL2_EXTREN_Msk (0x1ul << EADC_SCTL2_EXTREN_Pos) /*!< EADC_T::SCTL2: EXTREN Mask */ + +#define EADC_SCTL2_EXTFEN_Pos (5) /*!< EADC_T::SCTL2: EXTFEN Position */ +#define EADC_SCTL2_EXTFEN_Msk (0x1ul << EADC_SCTL2_EXTFEN_Pos) /*!< EADC_T::SCTL2: EXTFEN Mask */ + +#define EADC_SCTL2_TRGDLYDIV_Pos (6) /*!< EADC_T::SCTL2: TRGDLYDIV Position */ +#define EADC_SCTL2_TRGDLYDIV_Msk (0x3ul << EADC_SCTL2_TRGDLYDIV_Pos) /*!< EADC_T::SCTL2: TRGDLYDIV Mask */ + +#define EADC_SCTL2_TRGDLYCNT_Pos (8) /*!< EADC_T::SCTL2: TRGDLYCNT Position */ +#define EADC_SCTL2_TRGDLYCNT_Msk (0xfful << EADC_SCTL2_TRGDLYCNT_Pos) /*!< EADC_T::SCTL2: TRGDLYCNT Mask */ + +#define EADC_SCTL2_TRGSEL_Pos (16) /*!< EADC_T::SCTL2: TRGSEL Position */ +#define EADC_SCTL2_TRGSEL_Msk (0x1ful << EADC_SCTL2_TRGSEL_Pos) /*!< EADC_T::SCTL2: TRGSEL Mask */ + +#define EADC_SCTL2_INTPOS_Pos (22) /*!< EADC_T::SCTL2: INTPOS Position */ +#define EADC_SCTL2_INTPOS_Msk (0x1ul << EADC_SCTL2_INTPOS_Pos) /*!< EADC_T::SCTL2: INTPOS Mask */ + +#define EADC_SCTL2_DBMEN_Pos (23) /*!< EADC_T::SCTL2: DBMEN Position */ +#define EADC_SCTL2_DBMEN_Msk (0x1ul << EADC_SCTL2_DBMEN_Pos) /*!< EADC_T::SCTL2: DBMEN Mask */ + +#define EADC_SCTL2_EXTSMPT_Pos (24) /*!< EADC_T::SCTL2: EXTSMPT Position */ +#define EADC_SCTL2_EXTSMPT_Msk (0xfful << EADC_SCTL2_EXTSMPT_Pos) /*!< EADC_T::SCTL2: EXTSMPT Mask */ + +#define EADC_SCTL3_CHSEL_Pos (0) /*!< EADC_T::SCTL3: CHSEL Position */ +#define EADC_SCTL3_CHSEL_Msk (0xful << EADC_SCTL3_CHSEL_Pos) /*!< EADC_T::SCTL3: CHSEL Mask */ + +#define EADC_SCTL3_EXTREN_Pos (4) /*!< EADC_T::SCTL3: EXTREN Position */ +#define EADC_SCTL3_EXTREN_Msk (0x1ul << EADC_SCTL3_EXTREN_Pos) /*!< EADC_T::SCTL3: EXTREN Mask */ + +#define EADC_SCTL3_EXTFEN_Pos (5) /*!< EADC_T::SCTL3: EXTFEN Position */ +#define EADC_SCTL3_EXTFEN_Msk (0x1ul << EADC_SCTL3_EXTFEN_Pos) /*!< EADC_T::SCTL3: EXTFEN Mask */ + +#define EADC_SCTL3_TRGDLYDIV_Pos (6) /*!< EADC_T::SCTL3: TRGDLYDIV Position */ +#define EADC_SCTL3_TRGDLYDIV_Msk (0x3ul << EADC_SCTL3_TRGDLYDIV_Pos) /*!< EADC_T::SCTL3: TRGDLYDIV Mask */ + +#define EADC_SCTL3_TRGDLYCNT_Pos (8) /*!< EADC_T::SCTL3: TRGDLYCNT Position */ +#define EADC_SCTL3_TRGDLYCNT_Msk (0xfful << EADC_SCTL3_TRGDLYCNT_Pos) /*!< EADC_T::SCTL3: TRGDLYCNT Mask */ + +#define EADC_SCTL3_TRGSEL_Pos (16) /*!< EADC_T::SCTL3: TRGSEL Position */ +#define EADC_SCTL3_TRGSEL_Msk (0x1ful << EADC_SCTL3_TRGSEL_Pos) /*!< EADC_T::SCTL3: TRGSEL Mask */ + +#define EADC_SCTL3_INTPOS_Pos (22) /*!< EADC_T::SCTL3: INTPOS Position */ +#define EADC_SCTL3_INTPOS_Msk (0x1ul << EADC_SCTL3_INTPOS_Pos) /*!< EADC_T::SCTL3: INTPOS Mask */ + +#define EADC_SCTL3_DBMEN_Pos (23) /*!< EADC_T::SCTL3: DBMEN Position */ +#define EADC_SCTL3_DBMEN_Msk (0x1ul << EADC_SCTL3_DBMEN_Pos) /*!< EADC_T::SCTL3: DBMEN Mask */ + +#define EADC_SCTL3_EXTSMPT_Pos (24) /*!< EADC_T::SCTL3: EXTSMPT Position */ +#define EADC_SCTL3_EXTSMPT_Msk (0xfful << EADC_SCTL3_EXTSMPT_Pos) /*!< EADC_T::SCTL3: EXTSMPT Mask */ + +#define EADC_SCTL4_CHSEL_Pos (0) /*!< EADC_T::SCTL4: CHSEL Position */ +#define EADC_SCTL4_CHSEL_Msk (0xful << EADC_SCTL4_CHSEL_Pos) /*!< EADC_T::SCTL4: CHSEL Mask */ + +#define EADC_SCTL4_EXTREN_Pos (4) /*!< EADC_T::SCTL4: EXTREN Position */ +#define EADC_SCTL4_EXTREN_Msk (0x1ul << EADC_SCTL4_EXTREN_Pos) /*!< EADC_T::SCTL4: EXTREN Mask */ + +#define EADC_SCTL4_EXTFEN_Pos (5) /*!< EADC_T::SCTL4: EXTFEN Position */ +#define EADC_SCTL4_EXTFEN_Msk (0x1ul << EADC_SCTL4_EXTFEN_Pos) /*!< EADC_T::SCTL4: EXTFEN Mask */ + +#define EADC_SCTL4_TRGDLYDIV_Pos (6) /*!< EADC_T::SCTL4: TRGDLYDIV Position */ +#define EADC_SCTL4_TRGDLYDIV_Msk (0x3ul << EADC_SCTL4_TRGDLYDIV_Pos) /*!< EADC_T::SCTL4: TRGDLYDIV Mask */ + +#define EADC_SCTL4_TRGDLYCNT_Pos (8) /*!< EADC_T::SCTL4: TRGDLYCNT Position */ +#define EADC_SCTL4_TRGDLYCNT_Msk (0xfful << EADC_SCTL4_TRGDLYCNT_Pos) /*!< EADC_T::SCTL4: TRGDLYCNT Mask */ + +#define EADC_SCTL4_TRGSEL_Pos (16) /*!< EADC_T::SCTL4: TRGSEL Position */ +#define EADC_SCTL4_TRGSEL_Msk (0x1ful << EADC_SCTL4_TRGSEL_Pos) /*!< EADC_T::SCTL4: TRGSEL Mask */ + +#define EADC_SCTL4_INTPOS_Pos (22) /*!< EADC_T::SCTL4: INTPOS Position */ +#define EADC_SCTL4_INTPOS_Msk (0x1ul << EADC_SCTL4_INTPOS_Pos) /*!< EADC_T::SCTL4: INTPOS Mask */ + +#define EADC_SCTL4_EXTSMPT_Pos (24) /*!< EADC_T::SCTL4: EXTSMPT Position */ +#define EADC_SCTL4_EXTSMPT_Msk (0xfful << EADC_SCTL4_EXTSMPT_Pos) /*!< EADC_T::SCTL4: EXTSMPT Mask */ + +#define EADC_SCTL5_CHSEL_Pos (0) /*!< EADC_T::SCTL5: CHSEL Position */ +#define EADC_SCTL5_CHSEL_Msk (0xful << EADC_SCTL5_CHSEL_Pos) /*!< EADC_T::SCTL5: CHSEL Mask */ + +#define EADC_SCTL5_EXTREN_Pos (4) /*!< EADC_T::SCTL5: EXTREN Position */ +#define EADC_SCTL5_EXTREN_Msk (0x1ul << EADC_SCTL5_EXTREN_Pos) /*!< EADC_T::SCTL5: EXTREN Mask */ + +#define EADC_SCTL5_EXTFEN_Pos (5) /*!< EADC_T::SCTL5: EXTFEN Position */ +#define EADC_SCTL5_EXTFEN_Msk (0x1ul << EADC_SCTL5_EXTFEN_Pos) /*!< EADC_T::SCTL5: EXTFEN Mask */ + +#define EADC_SCTL5_TRGDLYDIV_Pos (6) /*!< EADC_T::SCTL5: TRGDLYDIV Position */ +#define EADC_SCTL5_TRGDLYDIV_Msk (0x3ul << EADC_SCTL5_TRGDLYDIV_Pos) /*!< EADC_T::SCTL5: TRGDLYDIV Mask */ + +#define EADC_SCTL5_TRGDLYCNT_Pos (8) /*!< EADC_T::SCTL5: TRGDLYCNT Position */ +#define EADC_SCTL5_TRGDLYCNT_Msk (0xfful << EADC_SCTL5_TRGDLYCNT_Pos) /*!< EADC_T::SCTL5: TRGDLYCNT Mask */ + +#define EADC_SCTL5_TRGSEL_Pos (16) /*!< EADC_T::SCTL5: TRGSEL Position */ +#define EADC_SCTL5_TRGSEL_Msk (0x1ful << EADC_SCTL5_TRGSEL_Pos) /*!< EADC_T::SCTL5: TRGSEL Mask */ + +#define EADC_SCTL5_INTPOS_Pos (22) /*!< EADC_T::SCTL5: INTPOS Position */ +#define EADC_SCTL5_INTPOS_Msk (0x1ul << EADC_SCTL5_INTPOS_Pos) /*!< EADC_T::SCTL5: INTPOS Mask */ + +#define EADC_SCTL5_EXTSMPT_Pos (24) /*!< EADC_T::SCTL5: EXTSMPT Position */ +#define EADC_SCTL5_EXTSMPT_Msk (0xfful << EADC_SCTL5_EXTSMPT_Pos) /*!< EADC_T::SCTL5: EXTSMPT Mask */ + +#define EADC_SCTL6_CHSEL_Pos (0) /*!< EADC_T::SCTL6: CHSEL Position */ +#define EADC_SCTL6_CHSEL_Msk (0xful << EADC_SCTL6_CHSEL_Pos) /*!< EADC_T::SCTL6: CHSEL Mask */ + +#define EADC_SCTL6_EXTREN_Pos (4) /*!< EADC_T::SCTL6: EXTREN Position */ +#define EADC_SCTL6_EXTREN_Msk (0x1ul << EADC_SCTL6_EXTREN_Pos) /*!< EADC_T::SCTL6: EXTREN Mask */ + +#define EADC_SCTL6_EXTFEN_Pos (5) /*!< EADC_T::SCTL6: EXTFEN Position */ +#define EADC_SCTL6_EXTFEN_Msk (0x1ul << EADC_SCTL6_EXTFEN_Pos) /*!< EADC_T::SCTL6: EXTFEN Mask */ + +#define EADC_SCTL6_TRGDLYDIV_Pos (6) /*!< EADC_T::SCTL6: TRGDLYDIV Position */ +#define EADC_SCTL6_TRGDLYDIV_Msk (0x3ul << EADC_SCTL6_TRGDLYDIV_Pos) /*!< EADC_T::SCTL6: TRGDLYDIV Mask */ + +#define EADC_SCTL6_TRGDLYCNT_Pos (8) /*!< EADC_T::SCTL6: TRGDLYCNT Position */ +#define EADC_SCTL6_TRGDLYCNT_Msk (0xfful << EADC_SCTL6_TRGDLYCNT_Pos) /*!< EADC_T::SCTL6: TRGDLYCNT Mask */ + +#define EADC_SCTL6_TRGSEL_Pos (16) /*!< EADC_T::SCTL6: TRGSEL Position */ +#define EADC_SCTL6_TRGSEL_Msk (0x1ful << EADC_SCTL6_TRGSEL_Pos) /*!< EADC_T::SCTL6: TRGSEL Mask */ + +#define EADC_SCTL6_INTPOS_Pos (22) /*!< EADC_T::SCTL6: INTPOS Position */ +#define EADC_SCTL6_INTPOS_Msk (0x1ul << EADC_SCTL6_INTPOS_Pos) /*!< EADC_T::SCTL6: INTPOS Mask */ + +#define EADC_SCTL6_EXTSMPT_Pos (24) /*!< EADC_T::SCTL6: EXTSMPT Position */ +#define EADC_SCTL6_EXTSMPT_Msk (0xfful << EADC_SCTL6_EXTSMPT_Pos) /*!< EADC_T::SCTL6: EXTSMPT Mask */ + +#define EADC_SCTL7_CHSEL_Pos (0) /*!< EADC_T::SCTL7: CHSEL Position */ +#define EADC_SCTL7_CHSEL_Msk (0xful << EADC_SCTL7_CHSEL_Pos) /*!< EADC_T::SCTL7: CHSEL Mask */ + +#define EADC_SCTL7_EXTREN_Pos (4) /*!< EADC_T::SCTL7: EXTREN Position */ +#define EADC_SCTL7_EXTREN_Msk (0x1ul << EADC_SCTL7_EXTREN_Pos) /*!< EADC_T::SCTL7: EXTREN Mask */ + +#define EADC_SCTL7_EXTFEN_Pos (5) /*!< EADC_T::SCTL7: EXTFEN Position */ +#define EADC_SCTL7_EXTFEN_Msk (0x1ul << EADC_SCTL7_EXTFEN_Pos) /*!< EADC_T::SCTL7: EXTFEN Mask */ + +#define EADC_SCTL7_TRGDLYDIV_Pos (6) /*!< EADC_T::SCTL7: TRGDLYDIV Position */ +#define EADC_SCTL7_TRGDLYDIV_Msk (0x3ul << EADC_SCTL7_TRGDLYDIV_Pos) /*!< EADC_T::SCTL7: TRGDLYDIV Mask */ + +#define EADC_SCTL7_TRGDLYCNT_Pos (8) /*!< EADC_T::SCTL7: TRGDLYCNT Position */ +#define EADC_SCTL7_TRGDLYCNT_Msk (0xfful << EADC_SCTL7_TRGDLYCNT_Pos) /*!< EADC_T::SCTL7: TRGDLYCNT Mask */ + +#define EADC_SCTL7_TRGSEL_Pos (16) /*!< EADC_T::SCTL7: TRGSEL Position */ +#define EADC_SCTL7_TRGSEL_Msk (0x1ful << EADC_SCTL7_TRGSEL_Pos) /*!< EADC_T::SCTL7: TRGSEL Mask */ + +#define EADC_SCTL7_INTPOS_Pos (22) /*!< EADC_T::SCTL7: INTPOS Position */ +#define EADC_SCTL7_INTPOS_Msk (0x1ul << EADC_SCTL7_INTPOS_Pos) /*!< EADC_T::SCTL7: INTPOS Mask */ + +#define EADC_SCTL7_EXTSMPT_Pos (24) /*!< EADC_T::SCTL7: EXTSMPT Position */ +#define EADC_SCTL7_EXTSMPT_Msk (0xfful << EADC_SCTL7_EXTSMPT_Pos) /*!< EADC_T::SCTL7: EXTSMPT Mask */ + +#define EADC_SCTL8_CHSEL_Pos (0) /*!< EADC_T::SCTL8: CHSEL Position */ +#define EADC_SCTL8_CHSEL_Msk (0xful << EADC_SCTL8_CHSEL_Pos) /*!< EADC_T::SCTL8: CHSEL Mask */ + +#define EADC_SCTL8_EXTREN_Pos (4) /*!< EADC_T::SCTL8: EXTREN Position */ +#define EADC_SCTL8_EXTREN_Msk (0x1ul << EADC_SCTL8_EXTREN_Pos) /*!< EADC_T::SCTL8: EXTREN Mask */ + +#define EADC_SCTL8_EXTFEN_Pos (5) /*!< EADC_T::SCTL8: EXTFEN Position */ +#define EADC_SCTL8_EXTFEN_Msk (0x1ul << EADC_SCTL8_EXTFEN_Pos) /*!< EADC_T::SCTL8: EXTFEN Mask */ + +#define EADC_SCTL8_TRGDLYDIV_Pos (6) /*!< EADC_T::SCTL8: TRGDLYDIV Position */ +#define EADC_SCTL8_TRGDLYDIV_Msk (0x3ul << EADC_SCTL8_TRGDLYDIV_Pos) /*!< EADC_T::SCTL8: TRGDLYDIV Mask */ + +#define EADC_SCTL8_TRGDLYCNT_Pos (8) /*!< EADC_T::SCTL8: TRGDLYCNT Position */ +#define EADC_SCTL8_TRGDLYCNT_Msk (0xfful << EADC_SCTL8_TRGDLYCNT_Pos) /*!< EADC_T::SCTL8: TRGDLYCNT Mask */ + +#define EADC_SCTL8_TRGSEL_Pos (16) /*!< EADC_T::SCTL8: TRGSEL Position */ +#define EADC_SCTL8_TRGSEL_Msk (0x1ful << EADC_SCTL8_TRGSEL_Pos) /*!< EADC_T::SCTL8: TRGSEL Mask */ + +#define EADC_SCTL8_INTPOS_Pos (22) /*!< EADC_T::SCTL8: INTPOS Position */ +#define EADC_SCTL8_INTPOS_Msk (0x1ul << EADC_SCTL8_INTPOS_Pos) /*!< EADC_T::SCTL8: INTPOS Mask */ + +#define EADC_SCTL8_EXTSMPT_Pos (24) /*!< EADC_T::SCTL8: EXTSMPT Position */ +#define EADC_SCTL8_EXTSMPT_Msk (0xfful << EADC_SCTL8_EXTSMPT_Pos) /*!< EADC_T::SCTL8: EXTSMPT Mask */ + +#define EADC_SCTL9_CHSEL_Pos (0) /*!< EADC_T::SCTL9: CHSEL Position */ +#define EADC_SCTL9_CHSEL_Msk (0xful << EADC_SCTL9_CHSEL_Pos) /*!< EADC_T::SCTL9: CHSEL Mask */ + +#define EADC_SCTL9_EXTREN_Pos (4) /*!< EADC_T::SCTL9: EXTREN Position */ +#define EADC_SCTL9_EXTREN_Msk (0x1ul << EADC_SCTL9_EXTREN_Pos) /*!< EADC_T::SCTL9: EXTREN Mask */ + +#define EADC_SCTL9_EXTFEN_Pos (5) /*!< EADC_T::SCTL9: EXTFEN Position */ +#define EADC_SCTL9_EXTFEN_Msk (0x1ul << EADC_SCTL9_EXTFEN_Pos) /*!< EADC_T::SCTL9: EXTFEN Mask */ + +#define EADC_SCTL9_TRGDLYDIV_Pos (6) /*!< EADC_T::SCTL9: TRGDLYDIV Position */ +#define EADC_SCTL9_TRGDLYDIV_Msk (0x3ul << EADC_SCTL9_TRGDLYDIV_Pos) /*!< EADC_T::SCTL9: TRGDLYDIV Mask */ + +#define EADC_SCTL9_TRGDLYCNT_Pos (8) /*!< EADC_T::SCTL9: TRGDLYCNT Position */ +#define EADC_SCTL9_TRGDLYCNT_Msk (0xfful << EADC_SCTL9_TRGDLYCNT_Pos) /*!< EADC_T::SCTL9: TRGDLYCNT Mask */ + +#define EADC_SCTL9_TRGSEL_Pos (16) /*!< EADC_T::SCTL9: TRGSEL Position */ +#define EADC_SCTL9_TRGSEL_Msk (0x1ful << EADC_SCTL9_TRGSEL_Pos) /*!< EADC_T::SCTL9: TRGSEL Mask */ + +#define EADC_SCTL9_INTPOS_Pos (22) /*!< EADC_T::SCTL9: INTPOS Position */ +#define EADC_SCTL9_INTPOS_Msk (0x1ul << EADC_SCTL9_INTPOS_Pos) /*!< EADC_T::SCTL9: INTPOS Mask */ + +#define EADC_SCTL9_EXTSMPT_Pos (24) /*!< EADC_T::SCTL9: EXTSMPT Position */ +#define EADC_SCTL9_EXTSMPT_Msk (0xfful << EADC_SCTL9_EXTSMPT_Pos) /*!< EADC_T::SCTL9: EXTSMPT Mask */ + +#define EADC_SCTL10_CHSEL_Pos (0) /*!< EADC_T::SCTL10: CHSEL Position */ +#define EADC_SCTL10_CHSEL_Msk (0xful << EADC_SCTL10_CHSEL_Pos) /*!< EADC_T::SCTL10: CHSEL Mask */ + +#define EADC_SCTL10_EXTREN_Pos (4) /*!< EADC_T::SCTL10: EXTREN Position */ +#define EADC_SCTL10_EXTREN_Msk (0x1ul << EADC_SCTL10_EXTREN_Pos) /*!< EADC_T::SCTL10: EXTREN Mask */ + +#define EADC_SCTL10_EXTFEN_Pos (5) /*!< EADC_T::SCTL10: EXTFEN Position */ +#define EADC_SCTL10_EXTFEN_Msk (0x1ul << EADC_SCTL10_EXTFEN_Pos) /*!< EADC_T::SCTL10: EXTFEN Mask */ + +#define EADC_SCTL10_TRGDLYDIV_Pos (6) /*!< EADC_T::SCTL10: TRGDLYDIV Position */ +#define EADC_SCTL10_TRGDLYDIV_Msk (0x3ul << EADC_SCTL10_TRGDLYDIV_Pos) /*!< EADC_T::SCTL10: TRGDLYDIV Mask */ + +#define EADC_SCTL10_TRGDLYCNT_Pos (8) /*!< EADC_T::SCTL10: TRGDLYCNT Position */ +#define EADC_SCTL10_TRGDLYCNT_Msk (0xfful << EADC_SCTL10_TRGDLYCNT_Pos) /*!< EADC_T::SCTL10: TRGDLYCNT Mask */ + +#define EADC_SCTL10_TRGSEL_Pos (16) /*!< EADC_T::SCTL10: TRGSEL Position */ +#define EADC_SCTL10_TRGSEL_Msk (0x1ful << EADC_SCTL10_TRGSEL_Pos) /*!< EADC_T::SCTL10: TRGSEL Mask */ + +#define EADC_SCTL10_INTPOS_Pos (22) /*!< EADC_T::SCTL10: INTPOS Position */ +#define EADC_SCTL10_INTPOS_Msk (0x1ul << EADC_SCTL10_INTPOS_Pos) /*!< EADC_T::SCTL10: INTPOS Mask */ + +#define EADC_SCTL10_EXTSMPT_Pos (24) /*!< EADC_T::SCTL10: EXTSMPT Position */ +#define EADC_SCTL10_EXTSMPT_Msk (0xfful << EADC_SCTL10_EXTSMPT_Pos) /*!< EADC_T::SCTL10: EXTSMPT Mask */ + +#define EADC_SCTL11_CHSEL_Pos (0) /*!< EADC_T::SCTL11: CHSEL Position */ +#define EADC_SCTL11_CHSEL_Msk (0xful << EADC_SCTL11_CHSEL_Pos) /*!< EADC_T::SCTL11: CHSEL Mask */ + +#define EADC_SCTL11_EXTREN_Pos (4) /*!< EADC_T::SCTL11: EXTREN Position */ +#define EADC_SCTL11_EXTREN_Msk (0x1ul << EADC_SCTL11_EXTREN_Pos) /*!< EADC_T::SCTL11: EXTREN Mask */ + +#define EADC_SCTL11_EXTFEN_Pos (5) /*!< EADC_T::SCTL11: EXTFEN Position */ +#define EADC_SCTL11_EXTFEN_Msk (0x1ul << EADC_SCTL11_EXTFEN_Pos) /*!< EADC_T::SCTL11: EXTFEN Mask */ + +#define EADC_SCTL11_TRGDLYDIV_Pos (6) /*!< EADC_T::SCTL11: TRGDLYDIV Position */ +#define EADC_SCTL11_TRGDLYDIV_Msk (0x3ul << EADC_SCTL11_TRGDLYDIV_Pos) /*!< EADC_T::SCTL11: TRGDLYDIV Mask */ + +#define EADC_SCTL11_TRGDLYCNT_Pos (8) /*!< EADC_T::SCTL11: TRGDLYCNT Position */ +#define EADC_SCTL11_TRGDLYCNT_Msk (0xfful << EADC_SCTL11_TRGDLYCNT_Pos) /*!< EADC_T::SCTL11: TRGDLYCNT Mask */ + +#define EADC_SCTL11_TRGSEL_Pos (16) /*!< EADC_T::SCTL11: TRGSEL Position */ +#define EADC_SCTL11_TRGSEL_Msk (0x1ful << EADC_SCTL11_TRGSEL_Pos) /*!< EADC_T::SCTL11: TRGSEL Mask */ + +#define EADC_SCTL11_INTPOS_Pos (22) /*!< EADC_T::SCTL11: INTPOS Position */ +#define EADC_SCTL11_INTPOS_Msk (0x1ul << EADC_SCTL11_INTPOS_Pos) /*!< EADC_T::SCTL11: INTPOS Mask */ + +#define EADC_SCTL11_EXTSMPT_Pos (24) /*!< EADC_T::SCTL11: EXTSMPT Position */ +#define EADC_SCTL11_EXTSMPT_Msk (0xfful << EADC_SCTL11_EXTSMPT_Pos) /*!< EADC_T::SCTL11: EXTSMPT Mask */ + +#define EADC_SCTL12_CHSEL_Pos (0) /*!< EADC_T::SCTL12: CHSEL Position */ +#define EADC_SCTL12_CHSEL_Msk (0xful << EADC_SCTL12_CHSEL_Pos) /*!< EADC_T::SCTL12: CHSEL Mask */ + +#define EADC_SCTL12_EXTREN_Pos (4) /*!< EADC_T::SCTL12: EXTREN Position */ +#define EADC_SCTL12_EXTREN_Msk (0x1ul << EADC_SCTL12_EXTREN_Pos) /*!< EADC_T::SCTL12: EXTREN Mask */ + +#define EADC_SCTL12_EXTFEN_Pos (5) /*!< EADC_T::SCTL12: EXTFEN Position */ +#define EADC_SCTL12_EXTFEN_Msk (0x1ul << EADC_SCTL12_EXTFEN_Pos) /*!< EADC_T::SCTL12: EXTFEN Mask */ + +#define EADC_SCTL12_TRGDLYDIV_Pos (6) /*!< EADC_T::SCTL12: TRGDLYDIV Position */ +#define EADC_SCTL12_TRGDLYDIV_Msk (0x3ul << EADC_SCTL12_TRGDLYDIV_Pos) /*!< EADC_T::SCTL12: TRGDLYDIV Mask */ + +#define EADC_SCTL12_TRGDLYCNT_Pos (8) /*!< EADC_T::SCTL12: TRGDLYCNT Position */ +#define EADC_SCTL12_TRGDLYCNT_Msk (0xfful << EADC_SCTL12_TRGDLYCNT_Pos) /*!< EADC_T::SCTL12: TRGDLYCNT Mask */ + +#define EADC_SCTL12_TRGSEL_Pos (16) /*!< EADC_T::SCTL12: TRGSEL Position */ +#define EADC_SCTL12_TRGSEL_Msk (0x1ful << EADC_SCTL12_TRGSEL_Pos) /*!< EADC_T::SCTL12: TRGSEL Mask */ + +#define EADC_SCTL12_INTPOS_Pos (22) /*!< EADC_T::SCTL12: INTPOS Position */ +#define EADC_SCTL12_INTPOS_Msk (0x1ul << EADC_SCTL12_INTPOS_Pos) /*!< EADC_T::SCTL12: INTPOS Mask */ + +#define EADC_SCTL12_EXTSMPT_Pos (24) /*!< EADC_T::SCTL12: EXTSMPT Position */ +#define EADC_SCTL12_EXTSMPT_Msk (0xfful << EADC_SCTL12_EXTSMPT_Pos) /*!< EADC_T::SCTL12: EXTSMPT Mask */ + +#define EADC_SCTL13_CHSEL_Pos (0) /*!< EADC_T::SCTL13: CHSEL Position */ +#define EADC_SCTL13_CHSEL_Msk (0xful << EADC_SCTL13_CHSEL_Pos) /*!< EADC_T::SCTL13: CHSEL Mask */ + +#define EADC_SCTL13_EXTREN_Pos (4) /*!< EADC_T::SCTL13: EXTREN Position */ +#define EADC_SCTL13_EXTREN_Msk (0x1ul << EADC_SCTL13_EXTREN_Pos) /*!< EADC_T::SCTL13: EXTREN Mask */ + +#define EADC_SCTL13_EXTFEN_Pos (5) /*!< EADC_T::SCTL13: EXTFEN Position */ +#define EADC_SCTL13_EXTFEN_Msk (0x1ul << EADC_SCTL13_EXTFEN_Pos) /*!< EADC_T::SCTL13: EXTFEN Mask */ + +#define EADC_SCTL13_TRGDLYDIV_Pos (6) /*!< EADC_T::SCTL13: TRGDLYDIV Position */ +#define EADC_SCTL13_TRGDLYDIV_Msk (0x3ul << EADC_SCTL13_TRGDLYDIV_Pos) /*!< EADC_T::SCTL13: TRGDLYDIV Mask */ + +#define EADC_SCTL13_TRGDLYCNT_Pos (8) /*!< EADC_T::SCTL13: TRGDLYCNT Position */ +#define EADC_SCTL13_TRGDLYCNT_Msk (0xfful << EADC_SCTL13_TRGDLYCNT_Pos) /*!< EADC_T::SCTL13: TRGDLYCNT Mask */ + +#define EADC_SCTL13_TRGSEL_Pos (16) /*!< EADC_T::SCTL13: TRGSEL Position */ +#define EADC_SCTL13_TRGSEL_Msk (0x1ful << EADC_SCTL13_TRGSEL_Pos) /*!< EADC_T::SCTL13: TRGSEL Mask */ + +#define EADC_SCTL13_INTPOS_Pos (22) /*!< EADC_T::SCTL13: INTPOS Position */ +#define EADC_SCTL13_INTPOS_Msk (0x1ul << EADC_SCTL13_INTPOS_Pos) /*!< EADC_T::SCTL13: INTPOS Mask */ + +#define EADC_SCTL13_EXTSMPT_Pos (24) /*!< EADC_T::SCTL13: EXTSMPT Position */ +#define EADC_SCTL13_EXTSMPT_Msk (0xfful << EADC_SCTL13_EXTSMPT_Pos) /*!< EADC_T::SCTL13: EXTSMPT Mask */ + +#define EADC_SCTL14_CHSEL_Pos (0) /*!< EADC_T::SCTL14: CHSEL Position */ +#define EADC_SCTL14_CHSEL_Msk (0xful << EADC_SCTL14_CHSEL_Pos) /*!< EADC_T::SCTL14: CHSEL Mask */ + +#define EADC_SCTL14_EXTREN_Pos (4) /*!< EADC_T::SCTL14: EXTREN Position */ +#define EADC_SCTL14_EXTREN_Msk (0x1ul << EADC_SCTL14_EXTREN_Pos) /*!< EADC_T::SCTL14: EXTREN Mask */ + +#define EADC_SCTL14_EXTFEN_Pos (5) /*!< EADC_T::SCTL14: EXTFEN Position */ +#define EADC_SCTL14_EXTFEN_Msk (0x1ul << EADC_SCTL14_EXTFEN_Pos) /*!< EADC_T::SCTL14: EXTFEN Mask */ + +#define EADC_SCTL14_TRGDLYDIV_Pos (6) /*!< EADC_T::SCTL14: TRGDLYDIV Position */ +#define EADC_SCTL14_TRGDLYDIV_Msk (0x3ul << EADC_SCTL14_TRGDLYDIV_Pos) /*!< EADC_T::SCTL14: TRGDLYDIV Mask */ + +#define EADC_SCTL14_TRGDLYCNT_Pos (8) /*!< EADC_T::SCTL14: TRGDLYCNT Position */ +#define EADC_SCTL14_TRGDLYCNT_Msk (0xfful << EADC_SCTL14_TRGDLYCNT_Pos) /*!< EADC_T::SCTL14: TRGDLYCNT Mask */ + +#define EADC_SCTL14_TRGSEL_Pos (16) /*!< EADC_T::SCTL14: TRGSEL Position */ +#define EADC_SCTL14_TRGSEL_Msk (0x1ful << EADC_SCTL14_TRGSEL_Pos) /*!< EADC_T::SCTL14: TRGSEL Mask */ + +#define EADC_SCTL14_INTPOS_Pos (22) /*!< EADC_T::SCTL14: INTPOS Position */ +#define EADC_SCTL14_INTPOS_Msk (0x1ul << EADC_SCTL14_INTPOS_Pos) /*!< EADC_T::SCTL14: INTPOS Mask */ + +#define EADC_SCTL14_EXTSMPT_Pos (24) /*!< EADC_T::SCTL14: EXTSMPT Position */ +#define EADC_SCTL14_EXTSMPT_Msk (0xfful << EADC_SCTL14_EXTSMPT_Pos) /*!< EADC_T::SCTL14: EXTSMPT Mask */ + +#define EADC_SCTL15_CHSEL_Pos (0) /*!< EADC_T::SCTL15: CHSEL Position */ +#define EADC_SCTL15_CHSEL_Msk (0xful << EADC_SCTL15_CHSEL_Pos) /*!< EADC_T::SCTL15: CHSEL Mask */ + +#define EADC_SCTL15_EXTREN_Pos (4) /*!< EADC_T::SCTL15: EXTREN Position */ +#define EADC_SCTL15_EXTREN_Msk (0x1ul << EADC_SCTL15_EXTREN_Pos) /*!< EADC_T::SCTL15: EXTREN Mask */ + +#define EADC_SCTL15_EXTFEN_Pos (5) /*!< EADC_T::SCTL15: EXTFEN Position */ +#define EADC_SCTL15_EXTFEN_Msk (0x1ul << EADC_SCTL15_EXTFEN_Pos) /*!< EADC_T::SCTL15: EXTFEN Mask */ + +#define EADC_SCTL15_TRGDLYDIV_Pos (6) /*!< EADC_T::SCTL15: TRGDLYDIV Position */ +#define EADC_SCTL15_TRGDLYDIV_Msk (0x3ul << EADC_SCTL15_TRGDLYDIV_Pos) /*!< EADC_T::SCTL15: TRGDLYDIV Mask */ + +#define EADC_SCTL15_TRGDLYCNT_Pos (8) /*!< EADC_T::SCTL15: TRGDLYCNT Position */ +#define EADC_SCTL15_TRGDLYCNT_Msk (0xfful << EADC_SCTL15_TRGDLYCNT_Pos) /*!< EADC_T::SCTL15: TRGDLYCNT Mask */ + +#define EADC_SCTL15_TRGSEL_Pos (16) /*!< EADC_T::SCTL15: TRGSEL Position */ +#define EADC_SCTL15_TRGSEL_Msk (0x1ful << EADC_SCTL15_TRGSEL_Pos) /*!< EADC_T::SCTL15: TRGSEL Mask */ + +#define EADC_SCTL15_INTPOS_Pos (22) /*!< EADC_T::SCTL15: INTPOS Position */ +#define EADC_SCTL15_INTPOS_Msk (0x1ul << EADC_SCTL15_INTPOS_Pos) /*!< EADC_T::SCTL15: INTPOS Mask */ + +#define EADC_SCTL15_EXTSMPT_Pos (24) /*!< EADC_T::SCTL15: EXTSMPT Position */ +#define EADC_SCTL15_EXTSMPT_Msk (0xfful << EADC_SCTL15_EXTSMPT_Pos) /*!< EADC_T::SCTL15: EXTSMPT Mask */ + +#define EADC_SCTL16_EXTSMPT_Pos (24) /*!< EADC_T::SCTL16: EXTSMPT Position */ +#define EADC_SCTL16_EXTSMPT_Msk (0xfful << EADC_SCTL16_EXTSMPT_Pos) /*!< EADC_T::SCTL16: EXTSMPT Mask */ + +#define EADC_SCTL17_EXTSMPT_Pos (24) /*!< EADC_T::SCTL17: EXTSMPT Position */ +#define EADC_SCTL17_EXTSMPT_Msk (0xfful << EADC_SCTL17_EXTSMPT_Pos) /*!< EADC_T::SCTL17: EXTSMPT Mask */ + +#define EADC_SCTL18_EXTSMPT_Pos (24) /*!< EADC_T::SCTL18: EXTSMPT Position */ +#define EADC_SCTL18_EXTSMPT_Msk (0xfful << EADC_SCTL18_EXTSMPT_Pos) /*!< EADC_T::SCTL18: EXTSMPT Mask */ + +#define EADC_INTSRC0_SPLIE0_Pos (0) /*!< EADC_T::INTSRC0: SPLIE0 Position */ +#define EADC_INTSRC0_SPLIE0_Msk (0x1ul << EADC_INTSRC0_SPLIE0_Pos) /*!< EADC_T::INTSRC0: SPLIE0 Mask */ + +#define EADC_INTSRC0_SPLIE1_Pos (1) /*!< EADC_T::INTSRC0: SPLIE1 Position */ +#define EADC_INTSRC0_SPLIE1_Msk (0x1ul << EADC_INTSRC0_SPLIE1_Pos) /*!< EADC_T::INTSRC0: SPLIE1 Mask */ + +#define EADC_INTSRC0_SPLIE2_Pos (2) /*!< EADC_T::INTSRC0: SPLIE2 Position */ +#define EADC_INTSRC0_SPLIE2_Msk (0x1ul << EADC_INTSRC0_SPLIE2_Pos) /*!< EADC_T::INTSRC0: SPLIE2 Mask */ + +#define EADC_INTSRC0_SPLIE3_Pos (3) /*!< EADC_T::INTSRC0: SPLIE3 Position */ +#define EADC_INTSRC0_SPLIE3_Msk (0x1ul << EADC_INTSRC0_SPLIE3_Pos) /*!< EADC_T::INTSRC0: SPLIE3 Mask */ + +#define EADC_INTSRC0_SPLIE4_Pos (4) /*!< EADC_T::INTSRC0: SPLIE4 Position */ +#define EADC_INTSRC0_SPLIE4_Msk (0x1ul << EADC_INTSRC0_SPLIE4_Pos) /*!< EADC_T::INTSRC0: SPLIE4 Mask */ + +#define EADC_INTSRC0_SPLIE5_Pos (5) /*!< EADC_T::INTSRC0: SPLIE5 Position */ +#define EADC_INTSRC0_SPLIE5_Msk (0x1ul << EADC_INTSRC0_SPLIE5_Pos) /*!< EADC_T::INTSRC0: SPLIE5 Mask */ + +#define EADC_INTSRC0_SPLIE6_Pos (6) /*!< EADC_T::INTSRC0: SPLIE6 Position */ +#define EADC_INTSRC0_SPLIE6_Msk (0x1ul << EADC_INTSRC0_SPLIE6_Pos) /*!< EADC_T::INTSRC0: SPLIE6 Mask */ + +#define EADC_INTSRC0_SPLIE7_Pos (7) /*!< EADC_T::INTSRC0: SPLIE7 Position */ +#define EADC_INTSRC0_SPLIE7_Msk (0x1ul << EADC_INTSRC0_SPLIE7_Pos) /*!< EADC_T::INTSRC0: SPLIE7 Mask */ + +#define EADC_INTSRC0_SPLIE8_Pos (8) /*!< EADC_T::INTSRC0: SPLIE8 Position */ +#define EADC_INTSRC0_SPLIE8_Msk (0x1ul << EADC_INTSRC0_SPLIE8_Pos) /*!< EADC_T::INTSRC0: SPLIE8 Mask */ + +#define EADC_INTSRC0_SPLIE9_Pos (9) /*!< EADC_T::INTSRC0: SPLIE9 Position */ +#define EADC_INTSRC0_SPLIE9_Msk (0x1ul << EADC_INTSRC0_SPLIE9_Pos) /*!< EADC_T::INTSRC0: SPLIE9 Mask */ + +#define EADC_INTSRC0_SPLIE10_Pos (10) /*!< EADC_T::INTSRC0: SPLIE10 Position */ +#define EADC_INTSRC0_SPLIE10_Msk (0x1ul << EADC_INTSRC0_SPLIE10_Pos) /*!< EADC_T::INTSRC0: SPLIE10 Mask */ + +#define EADC_INTSRC0_SPLIE11_Pos (11) /*!< EADC_T::INTSRC0: SPLIE11 Position */ +#define EADC_INTSRC0_SPLIE11_Msk (0x1ul << EADC_INTSRC0_SPLIE11_Pos) /*!< EADC_T::INTSRC0: SPLIE11 Mask */ + +#define EADC_INTSRC0_SPLIE12_Pos (12) /*!< EADC_T::INTSRC0: SPLIE12 Position */ +#define EADC_INTSRC0_SPLIE12_Msk (0x1ul << EADC_INTSRC0_SPLIE12_Pos) /*!< EADC_T::INTSRC0: SPLIE12 Mask */ + +#define EADC_INTSRC0_SPLIE13_Pos (13) /*!< EADC_T::INTSRC0: SPLIE13 Position */ +#define EADC_INTSRC0_SPLIE13_Msk (0x1ul << EADC_INTSRC0_SPLIE13_Pos) /*!< EADC_T::INTSRC0: SPLIE13 Mask */ + +#define EADC_INTSRC0_SPLIE14_Pos (14) /*!< EADC_T::INTSRC0: SPLIE14 Position */ +#define EADC_INTSRC0_SPLIE14_Msk (0x1ul << EADC_INTSRC0_SPLIE14_Pos) /*!< EADC_T::INTSRC0: SPLIE14 Mask */ + +#define EADC_INTSRC0_SPLIE15_Pos (15) /*!< EADC_T::INTSRC0: SPLIE15 Position */ +#define EADC_INTSRC0_SPLIE15_Msk (0x1ul << EADC_INTSRC0_SPLIE15_Pos) /*!< EADC_T::INTSRC0: SPLIE15 Mask */ + +#define EADC_INTSRC0_SPLIE16_Pos (16) /*!< EADC_T::INTSRC0: SPLIE16 Position */ +#define EADC_INTSRC0_SPLIE16_Msk (0x1ul << EADC_INTSRC0_SPLIE16_Pos) /*!< EADC_T::INTSRC0: SPLIE16 Mask */ + +#define EADC_INTSRC0_SPLIE17_Pos (17) /*!< EADC_T::INTSRC0: SPLIE17 Position */ +#define EADC_INTSRC0_SPLIE17_Msk (0x1ul << EADC_INTSRC0_SPLIE17_Pos) /*!< EADC_T::INTSRC0: SPLIE17 Mask */ + +#define EADC_INTSRC0_SPLIE18_Pos (18) /*!< EADC_T::INTSRC0: SPLIE18 Position */ +#define EADC_INTSRC0_SPLIE18_Msk (0x1ul << EADC_INTSRC0_SPLIE18_Pos) /*!< EADC_T::INTSRC0: SPLIE18 Mask */ + +#define EADC_INTSRC1_SPLIE0_Pos (0) /*!< EADC_T::INTSRC1: SPLIE0 Position */ +#define EADC_INTSRC1_SPLIE0_Msk (0x1ul << EADC_INTSRC1_SPLIE0_Pos) /*!< EADC_T::INTSRC1: SPLIE0 Mask */ + +#define EADC_INTSRC1_SPLIE1_Pos (1) /*!< EADC_T::INTSRC1: SPLIE1 Position */ +#define EADC_INTSRC1_SPLIE1_Msk (0x1ul << EADC_INTSRC1_SPLIE1_Pos) /*!< EADC_T::INTSRC1: SPLIE1 Mask */ + +#define EADC_INTSRC1_SPLIE2_Pos (2) /*!< EADC_T::INTSRC1: SPLIE2 Position */ +#define EADC_INTSRC1_SPLIE2_Msk (0x1ul << EADC_INTSRC1_SPLIE2_Pos) /*!< EADC_T::INTSRC1: SPLIE2 Mask */ + +#define EADC_INTSRC1_SPLIE3_Pos (3) /*!< EADC_T::INTSRC1: SPLIE3 Position */ +#define EADC_INTSRC1_SPLIE3_Msk (0x1ul << EADC_INTSRC1_SPLIE3_Pos) /*!< EADC_T::INTSRC1: SPLIE3 Mask */ + +#define EADC_INTSRC1_SPLIE4_Pos (4) /*!< EADC_T::INTSRC1: SPLIE4 Position */ +#define EADC_INTSRC1_SPLIE4_Msk (0x1ul << EADC_INTSRC1_SPLIE4_Pos) /*!< EADC_T::INTSRC1: SPLIE4 Mask */ + +#define EADC_INTSRC1_SPLIE5_Pos (5) /*!< EADC_T::INTSRC1: SPLIE5 Position */ +#define EADC_INTSRC1_SPLIE5_Msk (0x1ul << EADC_INTSRC1_SPLIE5_Pos) /*!< EADC_T::INTSRC1: SPLIE5 Mask */ + +#define EADC_INTSRC1_SPLIE6_Pos (6) /*!< EADC_T::INTSRC1: SPLIE6 Position */ +#define EADC_INTSRC1_SPLIE6_Msk (0x1ul << EADC_INTSRC1_SPLIE6_Pos) /*!< EADC_T::INTSRC1: SPLIE6 Mask */ + +#define EADC_INTSRC1_SPLIE7_Pos (7) /*!< EADC_T::INTSRC1: SPLIE7 Position */ +#define EADC_INTSRC1_SPLIE7_Msk (0x1ul << EADC_INTSRC1_SPLIE7_Pos) /*!< EADC_T::INTSRC1: SPLIE7 Mask */ + +#define EADC_INTSRC1_SPLIE8_Pos (8) /*!< EADC_T::INTSRC1: SPLIE8 Position */ +#define EADC_INTSRC1_SPLIE8_Msk (0x1ul << EADC_INTSRC1_SPLIE8_Pos) /*!< EADC_T::INTSRC1: SPLIE8 Mask */ + +#define EADC_INTSRC1_SPLIE9_Pos (9) /*!< EADC_T::INTSRC1: SPLIE9 Position */ +#define EADC_INTSRC1_SPLIE9_Msk (0x1ul << EADC_INTSRC1_SPLIE9_Pos) /*!< EADC_T::INTSRC1: SPLIE9 Mask */ + +#define EADC_INTSRC1_SPLIE10_Pos (10) /*!< EADC_T::INTSRC1: SPLIE10 Position */ +#define EADC_INTSRC1_SPLIE10_Msk (0x1ul << EADC_INTSRC1_SPLIE10_Pos) /*!< EADC_T::INTSRC1: SPLIE10 Mask */ + +#define EADC_INTSRC1_SPLIE11_Pos (11) /*!< EADC_T::INTSRC1: SPLIE11 Position */ +#define EADC_INTSRC1_SPLIE11_Msk (0x1ul << EADC_INTSRC1_SPLIE11_Pos) /*!< EADC_T::INTSRC1: SPLIE11 Mask */ + +#define EADC_INTSRC1_SPLIE12_Pos (12) /*!< EADC_T::INTSRC1: SPLIE12 Position */ +#define EADC_INTSRC1_SPLIE12_Msk (0x1ul << EADC_INTSRC1_SPLIE12_Pos) /*!< EADC_T::INTSRC1: SPLIE12 Mask */ + +#define EADC_INTSRC1_SPLIE13_Pos (13) /*!< EADC_T::INTSRC1: SPLIE13 Position */ +#define EADC_INTSRC1_SPLIE13_Msk (0x1ul << EADC_INTSRC1_SPLIE13_Pos) /*!< EADC_T::INTSRC1: SPLIE13 Mask */ + +#define EADC_INTSRC1_SPLIE14_Pos (14) /*!< EADC_T::INTSRC1: SPLIE14 Position */ +#define EADC_INTSRC1_SPLIE14_Msk (0x1ul << EADC_INTSRC1_SPLIE14_Pos) /*!< EADC_T::INTSRC1: SPLIE14 Mask */ + +#define EADC_INTSRC1_SPLIE15_Pos (15) /*!< EADC_T::INTSRC1: SPLIE15 Position */ +#define EADC_INTSRC1_SPLIE15_Msk (0x1ul << EADC_INTSRC1_SPLIE15_Pos) /*!< EADC_T::INTSRC1: SPLIE15 Mask */ + +#define EADC_INTSRC1_SPLIE16_Pos (16) /*!< EADC_T::INTSRC1: SPLIE16 Position */ +#define EADC_INTSRC1_SPLIE16_Msk (0x1ul << EADC_INTSRC1_SPLIE16_Pos) /*!< EADC_T::INTSRC1: SPLIE16 Mask */ + +#define EADC_INTSRC1_SPLIE17_Pos (17) /*!< EADC_T::INTSRC1: SPLIE17 Position */ +#define EADC_INTSRC1_SPLIE17_Msk (0x1ul << EADC_INTSRC1_SPLIE17_Pos) /*!< EADC_T::INTSRC1: SPLIE17 Mask */ + +#define EADC_INTSRC1_SPLIE18_Pos (18) /*!< EADC_T::INTSRC1: SPLIE18 Position */ +#define EADC_INTSRC1_SPLIE18_Msk (0x1ul << EADC_INTSRC1_SPLIE18_Pos) /*!< EADC_T::INTSRC1: SPLIE18 Mask */ + +#define EADC_INTSRC2_SPLIE0_Pos (0) /*!< EADC_T::INTSRC2: SPLIE0 Position */ +#define EADC_INTSRC2_SPLIE0_Msk (0x1ul << EADC_INTSRC2_SPLIE0_Pos) /*!< EADC_T::INTSRC2: SPLIE0 Mask */ + +#define EADC_INTSRC2_SPLIE1_Pos (1) /*!< EADC_T::INTSRC2: SPLIE1 Position */ +#define EADC_INTSRC2_SPLIE1_Msk (0x1ul << EADC_INTSRC2_SPLIE1_Pos) /*!< EADC_T::INTSRC2: SPLIE1 Mask */ + +#define EADC_INTSRC2_SPLIE2_Pos (2) /*!< EADC_T::INTSRC2: SPLIE2 Position */ +#define EADC_INTSRC2_SPLIE2_Msk (0x1ul << EADC_INTSRC2_SPLIE2_Pos) /*!< EADC_T::INTSRC2: SPLIE2 Mask */ + +#define EADC_INTSRC2_SPLIE3_Pos (3) /*!< EADC_T::INTSRC2: SPLIE3 Position */ +#define EADC_INTSRC2_SPLIE3_Msk (0x1ul << EADC_INTSRC2_SPLIE3_Pos) /*!< EADC_T::INTSRC2: SPLIE3 Mask */ + +#define EADC_INTSRC2_SPLIE4_Pos (4) /*!< EADC_T::INTSRC2: SPLIE4 Position */ +#define EADC_INTSRC2_SPLIE4_Msk (0x1ul << EADC_INTSRC2_SPLIE4_Pos) /*!< EADC_T::INTSRC2: SPLIE4 Mask */ + +#define EADC_INTSRC2_SPLIE5_Pos (5) /*!< EADC_T::INTSRC2: SPLIE5 Position */ +#define EADC_INTSRC2_SPLIE5_Msk (0x1ul << EADC_INTSRC2_SPLIE5_Pos) /*!< EADC_T::INTSRC2: SPLIE5 Mask */ + +#define EADC_INTSRC2_SPLIE6_Pos (6) /*!< EADC_T::INTSRC2: SPLIE6 Position */ +#define EADC_INTSRC2_SPLIE6_Msk (0x1ul << EADC_INTSRC2_SPLIE6_Pos) /*!< EADC_T::INTSRC2: SPLIE6 Mask */ + +#define EADC_INTSRC2_SPLIE7_Pos (7) /*!< EADC_T::INTSRC2: SPLIE7 Position */ +#define EADC_INTSRC2_SPLIE7_Msk (0x1ul << EADC_INTSRC2_SPLIE7_Pos) /*!< EADC_T::INTSRC2: SPLIE7 Mask */ + +#define EADC_INTSRC2_SPLIE8_Pos (8) /*!< EADC_T::INTSRC2: SPLIE8 Position */ +#define EADC_INTSRC2_SPLIE8_Msk (0x1ul << EADC_INTSRC2_SPLIE8_Pos) /*!< EADC_T::INTSRC2: SPLIE8 Mask */ + +#define EADC_INTSRC2_SPLIE9_Pos (9) /*!< EADC_T::INTSRC2: SPLIE9 Position */ +#define EADC_INTSRC2_SPLIE9_Msk (0x1ul << EADC_INTSRC2_SPLIE9_Pos) /*!< EADC_T::INTSRC2: SPLIE9 Mask */ + +#define EADC_INTSRC2_SPLIE10_Pos (10) /*!< EADC_T::INTSRC2: SPLIE10 Position */ +#define EADC_INTSRC2_SPLIE10_Msk (0x1ul << EADC_INTSRC2_SPLIE10_Pos) /*!< EADC_T::INTSRC2: SPLIE10 Mask */ + +#define EADC_INTSRC2_SPLIE11_Pos (11) /*!< EADC_T::INTSRC2: SPLIE11 Position */ +#define EADC_INTSRC2_SPLIE11_Msk (0x1ul << EADC_INTSRC2_SPLIE11_Pos) /*!< EADC_T::INTSRC2: SPLIE11 Mask */ + +#define EADC_INTSRC2_SPLIE12_Pos (12) /*!< EADC_T::INTSRC2: SPLIE12 Position */ +#define EADC_INTSRC2_SPLIE12_Msk (0x1ul << EADC_INTSRC2_SPLIE12_Pos) /*!< EADC_T::INTSRC2: SPLIE12 Mask */ + +#define EADC_INTSRC2_SPLIE13_Pos (13) /*!< EADC_T::INTSRC2: SPLIE13 Position */ +#define EADC_INTSRC2_SPLIE13_Msk (0x1ul << EADC_INTSRC2_SPLIE13_Pos) /*!< EADC_T::INTSRC2: SPLIE13 Mask */ + +#define EADC_INTSRC2_SPLIE14_Pos (14) /*!< EADC_T::INTSRC2: SPLIE14 Position */ +#define EADC_INTSRC2_SPLIE14_Msk (0x1ul << EADC_INTSRC2_SPLIE14_Pos) /*!< EADC_T::INTSRC2: SPLIE14 Mask */ + +#define EADC_INTSRC2_SPLIE15_Pos (15) /*!< EADC_T::INTSRC2: SPLIE15 Position */ +#define EADC_INTSRC2_SPLIE15_Msk (0x1ul << EADC_INTSRC2_SPLIE15_Pos) /*!< EADC_T::INTSRC2: SPLIE15 Mask */ + +#define EADC_INTSRC2_SPLIE16_Pos (16) /*!< EADC_T::INTSRC2: SPLIE16 Position */ +#define EADC_INTSRC2_SPLIE16_Msk (0x1ul << EADC_INTSRC2_SPLIE16_Pos) /*!< EADC_T::INTSRC2: SPLIE16 Mask */ + +#define EADC_INTSRC2_SPLIE17_Pos (17) /*!< EADC_T::INTSRC2: SPLIE17 Position */ +#define EADC_INTSRC2_SPLIE17_Msk (0x1ul << EADC_INTSRC2_SPLIE17_Pos) /*!< EADC_T::INTSRC2: SPLIE17 Mask */ + +#define EADC_INTSRC2_SPLIE18_Pos (18) /*!< EADC_T::INTSRC2: SPLIE18 Position */ +#define EADC_INTSRC2_SPLIE18_Msk (0x1ul << EADC_INTSRC2_SPLIE18_Pos) /*!< EADC_T::INTSRC2: SPLIE18 Mask */ + +#define EADC_INTSRC3_SPLIE0_Pos (0) /*!< EADC_T::INTSRC3: SPLIE0 Position */ +#define EADC_INTSRC3_SPLIE0_Msk (0x1ul << EADC_INTSRC3_SPLIE0_Pos) /*!< EADC_T::INTSRC3: SPLIE0 Mask */ + +#define EADC_INTSRC3_SPLIE1_Pos (1) /*!< EADC_T::INTSRC3: SPLIE1 Position */ +#define EADC_INTSRC3_SPLIE1_Msk (0x1ul << EADC_INTSRC3_SPLIE1_Pos) /*!< EADC_T::INTSRC3: SPLIE1 Mask */ + +#define EADC_INTSRC3_SPLIE2_Pos (2) /*!< EADC_T::INTSRC3: SPLIE2 Position */ +#define EADC_INTSRC3_SPLIE2_Msk (0x1ul << EADC_INTSRC3_SPLIE2_Pos) /*!< EADC_T::INTSRC3: SPLIE2 Mask */ + +#define EADC_INTSRC3_SPLIE3_Pos (3) /*!< EADC_T::INTSRC3: SPLIE3 Position */ +#define EADC_INTSRC3_SPLIE3_Msk (0x1ul << EADC_INTSRC3_SPLIE3_Pos) /*!< EADC_T::INTSRC3: SPLIE3 Mask */ + +#define EADC_INTSRC3_SPLIE4_Pos (4) /*!< EADC_T::INTSRC3: SPLIE4 Position */ +#define EADC_INTSRC3_SPLIE4_Msk (0x1ul << EADC_INTSRC3_SPLIE4_Pos) /*!< EADC_T::INTSRC3: SPLIE4 Mask */ + +#define EADC_INTSRC3_SPLIE5_Pos (5) /*!< EADC_T::INTSRC3: SPLIE5 Position */ +#define EADC_INTSRC3_SPLIE5_Msk (0x1ul << EADC_INTSRC3_SPLIE5_Pos) /*!< EADC_T::INTSRC3: SPLIE5 Mask */ + +#define EADC_INTSRC3_SPLIE6_Pos (6) /*!< EADC_T::INTSRC3: SPLIE6 Position */ +#define EADC_INTSRC3_SPLIE6_Msk (0x1ul << EADC_INTSRC3_SPLIE6_Pos) /*!< EADC_T::INTSRC3: SPLIE6 Mask */ + +#define EADC_INTSRC3_SPLIE7_Pos (7) /*!< EADC_T::INTSRC3: SPLIE7 Position */ +#define EADC_INTSRC3_SPLIE7_Msk (0x1ul << EADC_INTSRC3_SPLIE7_Pos) /*!< EADC_T::INTSRC3: SPLIE7 Mask */ + +#define EADC_INTSRC3_SPLIE8_Pos (8) /*!< EADC_T::INTSRC3: SPLIE8 Position */ +#define EADC_INTSRC3_SPLIE8_Msk (0x1ul << EADC_INTSRC3_SPLIE8_Pos) /*!< EADC_T::INTSRC3: SPLIE8 Mask */ + +#define EADC_INTSRC3_SPLIE9_Pos (9) /*!< EADC_T::INTSRC3: SPLIE9 Position */ +#define EADC_INTSRC3_SPLIE9_Msk (0x1ul << EADC_INTSRC3_SPLIE9_Pos) /*!< EADC_T::INTSRC3: SPLIE9 Mask */ + +#define EADC_INTSRC3_SPLIE10_Pos (10) /*!< EADC_T::INTSRC3: SPLIE10 Position */ +#define EADC_INTSRC3_SPLIE10_Msk (0x1ul << EADC_INTSRC3_SPLIE10_Pos) /*!< EADC_T::INTSRC3: SPLIE10 Mask */ + +#define EADC_INTSRC3_SPLIE11_Pos (11) /*!< EADC_T::INTSRC3: SPLIE11 Position */ +#define EADC_INTSRC3_SPLIE11_Msk (0x1ul << EADC_INTSRC3_SPLIE11_Pos) /*!< EADC_T::INTSRC3: SPLIE11 Mask */ + +#define EADC_INTSRC3_SPLIE12_Pos (12) /*!< EADC_T::INTSRC3: SPLIE12 Position */ +#define EADC_INTSRC3_SPLIE12_Msk (0x1ul << EADC_INTSRC3_SPLIE12_Pos) /*!< EADC_T::INTSRC3: SPLIE12 Mask */ + +#define EADC_INTSRC3_SPLIE13_Pos (13) /*!< EADC_T::INTSRC3: SPLIE13 Position */ +#define EADC_INTSRC3_SPLIE13_Msk (0x1ul << EADC_INTSRC3_SPLIE13_Pos) /*!< EADC_T::INTSRC3: SPLIE13 Mask */ + +#define EADC_INTSRC3_SPLIE14_Pos (14) /*!< EADC_T::INTSRC3: SPLIE14 Position */ +#define EADC_INTSRC3_SPLIE14_Msk (0x1ul << EADC_INTSRC3_SPLIE14_Pos) /*!< EADC_T::INTSRC3: SPLIE14 Mask */ + +#define EADC_INTSRC3_SPLIE15_Pos (15) /*!< EADC_T::INTSRC3: SPLIE15 Position */ +#define EADC_INTSRC3_SPLIE15_Msk (0x1ul << EADC_INTSRC3_SPLIE15_Pos) /*!< EADC_T::INTSRC3: SPLIE15 Mask */ + +#define EADC_INTSRC3_SPLIE16_Pos (16) /*!< EADC_T::INTSRC3: SPLIE16 Position */ +#define EADC_INTSRC3_SPLIE16_Msk (0x1ul << EADC_INTSRC3_SPLIE16_Pos) /*!< EADC_T::INTSRC3: SPLIE16 Mask */ + +#define EADC_INTSRC3_SPLIE17_Pos (17) /*!< EADC_T::INTSRC3: SPLIE17 Position */ +#define EADC_INTSRC3_SPLIE17_Msk (0x1ul << EADC_INTSRC3_SPLIE17_Pos) /*!< EADC_T::INTSRC3: SPLIE17 Mask */ + +#define EADC_INTSRC3_SPLIE18_Pos (18) /*!< EADC_T::INTSRC3: SPLIE18 Position */ +#define EADC_INTSRC3_SPLIE18_Msk (0x1ul << EADC_INTSRC3_SPLIE18_Pos) /*!< EADC_T::INTSRC3: SPLIE18 Mask */ + +#define EADC_CMP_ADCMPEN_Pos (0) /*!< EADC_T::CMP: ADCMPEN Position */ +#define EADC_CMP_ADCMPEN_Msk (0x1ul << EADC_CMP_ADCMPEN_Pos) /*!< EADC_T::CMP: ADCMPEN Mask */ + +#define EADC_CMP_ADCMPIE_Pos (1) /*!< EADC_T::CMP: ADCMPIE Position */ +#define EADC_CMP_ADCMPIE_Msk (0x1ul << EADC_CMP_ADCMPIE_Pos) /*!< EADC_T::CMP: ADCMPIE Mask */ + +#define EADC_CMP_CMPCOND_Pos (2) /*!< EADC_T::CMP: CMPCOND Position */ +#define EADC_CMP_CMPCOND_Msk (0x1ul << EADC_CMP_CMPCOND_Pos) /*!< EADC_T::CMP: CMPCOND Mask */ + +#define EADC_CMP_CMPSPL_Pos (3) /*!< EADC_T::CMP: CMPSPL Position */ +#define EADC_CMP_CMPSPL_Msk (0x1ful << EADC_CMP_CMPSPL_Pos) /*!< EADC_T::CMP: CMPSPL Mask */ + +#define EADC_CMP_CMPMCNT_Pos (8) /*!< EADC_T::CMP: CMPMCNT Position */ +#define EADC_CMP_CMPMCNT_Msk (0xful << EADC_CMP_CMPMCNT_Pos) /*!< EADC_T::CMP: CMPMCNT Mask */ + +#define EADC_CMP_CMPWEN_Pos (15) /*!< EADC_T::CMP: CMPWEN Position */ +#define EADC_CMP_CMPWEN_Msk (0x1ul << EADC_CMP_CMPWEN_Pos) /*!< EADC_T::CMP: CMPWEN Mask */ + +#define EADC_CMP_CMPDAT_Pos (16) /*!< EADC_T::CMP: CMPDAT Position */ +#define EADC_CMP_CMPDAT_Msk (0xffful << EADC_CMP_CMPDAT_Pos) /*!< EADC_T::CMP: CMPDAT Mask */ + +#define EADC_CMP0_ADCMPEN_Pos (0) /*!< EADC_T::CMP0: ADCMPEN Position */ +#define EADC_CMP0_ADCMPEN_Msk (0x1ul << EADC_CMP0_ADCMPEN_Pos) /*!< EADC_T::CMP0: ADCMPEN Mask */ + +#define EADC_CMP0_ADCMPIE_Pos (1) /*!< EADC_T::CMP0: ADCMPIE Position */ +#define EADC_CMP0_ADCMPIE_Msk (0x1ul << EADC_CMP0_ADCMPIE_Pos) /*!< EADC_T::CMP0: ADCMPIE Mask */ + +#define EADC_CMP0_CMPCOND_Pos (2) /*!< EADC_T::CMP0: CMPCOND Position */ +#define EADC_CMP0_CMPCOND_Msk (0x1ul << EADC_CMP0_CMPCOND_Pos) /*!< EADC_T::CMP0: CMPCOND Mask */ + +#define EADC_CMP0_CMPSPL_Pos (3) /*!< EADC_T::CMP0: CMPSPL Position */ +#define EADC_CMP0_CMPSPL_Msk (0x1ful << EADC_CMP0_CMPSPL_Pos) /*!< EADC_T::CMP0: CMPSPL Mask */ + +#define EADC_CMP0_CMPMCNT_Pos (8) /*!< EADC_T::CMP0: CMPMCNT Position */ +#define EADC_CMP0_CMPMCNT_Msk (0xful << EADC_CMP0_CMPMCNT_Pos) /*!< EADC_T::CMP0: CMPMCNT Mask */ + +#define EADC_CMP0_CMPWEN_Pos (15) /*!< EADC_T::CMP0: CMPWEN Position */ +#define EADC_CMP0_CMPWEN_Msk (0x1ul << EADC_CMP0_CMPWEN_Pos) /*!< EADC_T::CMP0: CMPWEN Mask */ + +#define EADC_CMP0_CMPDAT_Pos (16) /*!< EADC_T::CMP0: CMPDAT Position */ +#define EADC_CMP0_CMPDAT_Msk (0xffful << EADC_CMP0_CMPDAT_Pos) /*!< EADC_T::CMP0: CMPDAT Mask */ + +#define EADC_CMP1_ADCMPEN_Pos (0) /*!< EADC_T::CMP1: ADCMPEN Position */ +#define EADC_CMP1_ADCMPEN_Msk (0x1ul << EADC_CMP1_ADCMPEN_Pos) /*!< EADC_T::CMP1: ADCMPEN Mask */ + +#define EADC_CMP1_ADCMPIE_Pos (1) /*!< EADC_T::CMP1: ADCMPIE Position */ +#define EADC_CMP1_ADCMPIE_Msk (0x1ul << EADC_CMP1_ADCMPIE_Pos) /*!< EADC_T::CMP1: ADCMPIE Mask */ + +#define EADC_CMP1_CMPCOND_Pos (2) /*!< EADC_T::CMP1: CMPCOND Position */ +#define EADC_CMP1_CMPCOND_Msk (0x1ul << EADC_CMP1_CMPCOND_Pos) /*!< EADC_T::CMP1: CMPCOND Mask */ + +#define EADC_CMP1_CMPSPL_Pos (3) /*!< EADC_T::CMP1: CMPSPL Position */ +#define EADC_CMP1_CMPSPL_Msk (0x1ful << EADC_CMP1_CMPSPL_Pos) /*!< EADC_T::CMP1: CMPSPL Mask */ + +#define EADC_CMP1_CMPMCNT_Pos (8) /*!< EADC_T::CMP1: CMPMCNT Position */ +#define EADC_CMP1_CMPMCNT_Msk (0xful << EADC_CMP1_CMPMCNT_Pos) /*!< EADC_T::CMP1: CMPMCNT Mask */ + +#define EADC_CMP1_CMPWEN_Pos (15) /*!< EADC_T::CMP1: CMPWEN Position */ +#define EADC_CMP1_CMPWEN_Msk (0x1ul << EADC_CMP1_CMPWEN_Pos) /*!< EADC_T::CMP1: CMPWEN Mask */ + +#define EADC_CMP1_CMPDAT_Pos (16) /*!< EADC_T::CMP1: CMPDAT Position */ +#define EADC_CMP1_CMPDAT_Msk (0xffful << EADC_CMP1_CMPDAT_Pos) /*!< EADC_T::CMP1: CMPDAT Mask */ + +#define EADC_CMP2_ADCMPEN_Pos (0) /*!< EADC_T::CMP2: ADCMPEN Position */ +#define EADC_CMP2_ADCMPEN_Msk (0x1ul << EADC_CMP2_ADCMPEN_Pos) /*!< EADC_T::CMP2: ADCMPEN Mask */ + +#define EADC_CMP2_ADCMPIE_Pos (1) /*!< EADC_T::CMP2: ADCMPIE Position */ +#define EADC_CMP2_ADCMPIE_Msk (0x1ul << EADC_CMP2_ADCMPIE_Pos) /*!< EADC_T::CMP2: ADCMPIE Mask */ + +#define EADC_CMP2_CMPCOND_Pos (2) /*!< EADC_T::CMP2: CMPCOND Position */ +#define EADC_CMP2_CMPCOND_Msk (0x1ul << EADC_CMP2_CMPCOND_Pos) /*!< EADC_T::CMP2: CMPCOND Mask */ + +#define EADC_CMP2_CMPSPL_Pos (3) /*!< EADC_T::CMP2: CMPSPL Position */ +#define EADC_CMP2_CMPSPL_Msk (0x1ful << EADC_CMP2_CMPSPL_Pos) /*!< EADC_T::CMP2: CMPSPL Mask */ + +#define EADC_CMP2_CMPMCNT_Pos (8) /*!< EADC_T::CMP2: CMPMCNT Position */ +#define EADC_CMP2_CMPMCNT_Msk (0xful << EADC_CMP2_CMPMCNT_Pos) /*!< EADC_T::CMP2: CMPMCNT Mask */ + +#define EADC_CMP2_CMPWEN_Pos (15) /*!< EADC_T::CMP2: CMPWEN Position */ +#define EADC_CMP2_CMPWEN_Msk (0x1ul << EADC_CMP2_CMPWEN_Pos) /*!< EADC_T::CMP2: CMPWEN Mask */ + +#define EADC_CMP2_CMPDAT_Pos (16) /*!< EADC_T::CMP2: CMPDAT Position */ +#define EADC_CMP2_CMPDAT_Msk (0xffful << EADC_CMP2_CMPDAT_Pos) /*!< EADC_T::CMP2: CMPDAT Mask */ + +#define EADC_CMP3_ADCMPEN_Pos (0) /*!< EADC_T::CMP3: ADCMPEN Position */ +#define EADC_CMP3_ADCMPEN_Msk (0x1ul << EADC_CMP3_ADCMPEN_Pos) /*!< EADC_T::CMP3: ADCMPEN Mask */ + +#define EADC_CMP3_ADCMPIE_Pos (1) /*!< EADC_T::CMP3: ADCMPIE Position */ +#define EADC_CMP3_ADCMPIE_Msk (0x1ul << EADC_CMP3_ADCMPIE_Pos) /*!< EADC_T::CMP3: ADCMPIE Mask */ + +#define EADC_CMP3_CMPCOND_Pos (2) /*!< EADC_T::CMP3: CMPCOND Position */ +#define EADC_CMP3_CMPCOND_Msk (0x1ul << EADC_CMP3_CMPCOND_Pos) /*!< EADC_T::CMP3: CMPCOND Mask */ + +#define EADC_CMP3_CMPSPL_Pos (3) /*!< EADC_T::CMP3: CMPSPL Position */ +#define EADC_CMP3_CMPSPL_Msk (0x1ful << EADC_CMP3_CMPSPL_Pos) /*!< EADC_T::CMP3: CMPSPL Mask */ + +#define EADC_CMP3_CMPMCNT_Pos (8) /*!< EADC_T::CMP3: CMPMCNT Position */ +#define EADC_CMP3_CMPMCNT_Msk (0xful << EADC_CMP3_CMPMCNT_Pos) /*!< EADC_T::CMP3: CMPMCNT Mask */ + +#define EADC_CMP3_CMPWEN_Pos (15) /*!< EADC_T::CMP3: CMPWEN Position */ +#define EADC_CMP3_CMPWEN_Msk (0x1ul << EADC_CMP3_CMPWEN_Pos) /*!< EADC_T::CMP3: CMPWEN Mask */ + +#define EADC_CMP3_CMPDAT_Pos (16) /*!< EADC_T::CMP3: CMPDAT Position */ +#define EADC_CMP3_CMPDAT_Msk (0xffful << EADC_CMP3_CMPDAT_Pos) /*!< EADC_T::CMP3: CMPDAT Mask */ + +#define EADC_STATUS0_VALID_Pos (0) /*!< EADC_T::STATUS0: VALID Position */ +#define EADC_STATUS0_VALID_Msk (0xfffful << EADC_STATUS0_VALID_Pos) /*!< EADC_T::STATUS0: VALID Mask */ + +#define EADC_STATUS0_OV_Pos (16) /*!< EADC_T::STATUS0: OV Position */ +#define EADC_STATUS0_OV_Msk (0xfffful << EADC_STATUS0_OV_Pos) /*!< EADC_T::STATUS0: OV Mask */ + +#define EADC_STATUS1_VALID_Pos (0) /*!< EADC_T::STATUS1: VALID Position */ +#define EADC_STATUS1_VALID_Msk (0x7ul << EADC_STATUS1_VALID_Pos) /*!< EADC_T::STATUS1: VALID Mask */ + +#define EADC_STATUS1_OV_Pos (16) /*!< EADC_T::STATUS1: OV Position */ +#define EADC_STATUS1_OV_Msk (0x7ul << EADC_STATUS1_OV_Pos) /*!< EADC_T::STATUS1: OV Mask */ + +#define EADC_STATUS2_ADIF0_Pos (0) /*!< EADC_T::STATUS2: ADIF0 Position */ +#define EADC_STATUS2_ADIF0_Msk (0x1ul << EADC_STATUS2_ADIF0_Pos) /*!< EADC_T::STATUS2: ADIF0 Mask */ + +#define EADC_STATUS2_ADIF1_Pos (1) /*!< EADC_T::STATUS2: ADIF1 Position */ +#define EADC_STATUS2_ADIF1_Msk (0x1ul << EADC_STATUS2_ADIF1_Pos) /*!< EADC_T::STATUS2: ADIF1 Mask */ + +#define EADC_STATUS2_ADIF2_Pos (2) /*!< EADC_T::STATUS2: ADIF2 Position */ +#define EADC_STATUS2_ADIF2_Msk (0x1ul << EADC_STATUS2_ADIF2_Pos) /*!< EADC_T::STATUS2: ADIF2 Mask */ + +#define EADC_STATUS2_ADIF3_Pos (3) /*!< EADC_T::STATUS2: ADIF3 Position */ +#define EADC_STATUS2_ADIF3_Msk (0x1ul << EADC_STATUS2_ADIF3_Pos) /*!< EADC_T::STATUS2: ADIF3 Mask */ + +#define EADC_STATUS2_ADCMPF0_Pos (4) /*!< EADC_T::STATUS2: ADCMPF0 Position */ +#define EADC_STATUS2_ADCMPF0_Msk (0x1ul << EADC_STATUS2_ADCMPF0_Pos) /*!< EADC_T::STATUS2: ADCMPF0 Mask */ + +#define EADC_STATUS2_ADCMPF1_Pos (5) /*!< EADC_T::STATUS2: ADCMPF1 Position */ +#define EADC_STATUS2_ADCMPF1_Msk (0x1ul << EADC_STATUS2_ADCMPF1_Pos) /*!< EADC_T::STATUS2: ADCMPF1 Mask */ + +#define EADC_STATUS2_ADCMPF2_Pos (6) /*!< EADC_T::STATUS2: ADCMPF2 Position */ +#define EADC_STATUS2_ADCMPF2_Msk (0x1ul << EADC_STATUS2_ADCMPF2_Pos) /*!< EADC_T::STATUS2: ADCMPF2 Mask */ + +#define EADC_STATUS2_ADCMPF3_Pos (7) /*!< EADC_T::STATUS2: ADCMPF3 Position */ +#define EADC_STATUS2_ADCMPF3_Msk (0x1ul << EADC_STATUS2_ADCMPF3_Pos) /*!< EADC_T::STATUS2: ADCMPF3 Mask */ + +#define EADC_STATUS2_ADOVIF0_Pos (8) /*!< EADC_T::STATUS2: ADOVIF0 Position */ +#define EADC_STATUS2_ADOVIF0_Msk (0x1ul << EADC_STATUS2_ADOVIF0_Pos) /*!< EADC_T::STATUS2: ADOVIF0 Mask */ + +#define EADC_STATUS2_ADOVIF1_Pos (9) /*!< EADC_T::STATUS2: ADOVIF1 Position */ +#define EADC_STATUS2_ADOVIF1_Msk (0x1ul << EADC_STATUS2_ADOVIF1_Pos) /*!< EADC_T::STATUS2: ADOVIF1 Mask */ + +#define EADC_STATUS2_ADOVIF2_Pos (10) /*!< EADC_T::STATUS2: ADOVIF2 Position */ +#define EADC_STATUS2_ADOVIF2_Msk (0x1ul << EADC_STATUS2_ADOVIF2_Pos) /*!< EADC_T::STATUS2: ADOVIF2 Mask */ + +#define EADC_STATUS2_ADOVIF3_Pos (11) /*!< EADC_T::STATUS2: ADOVIF3 Position */ +#define EADC_STATUS2_ADOVIF3_Msk (0x1ul << EADC_STATUS2_ADOVIF3_Pos) /*!< EADC_T::STATUS2: ADOVIF3 Mask */ + +#define EADC_STATUS2_ADCMPO0_Pos (12) /*!< EADC_T::STATUS2: ADCMPO0 Position */ +#define EADC_STATUS2_ADCMPO0_Msk (0x1ul << EADC_STATUS2_ADCMPO0_Pos) /*!< EADC_T::STATUS2: ADCMPO0 Mask */ + +#define EADC_STATUS2_ADCMPO1_Pos (13) /*!< EADC_T::STATUS2: ADCMPO1 Position */ +#define EADC_STATUS2_ADCMPO1_Msk (0x1ul << EADC_STATUS2_ADCMPO1_Pos) /*!< EADC_T::STATUS2: ADCMPO1 Mask */ + +#define EADC_STATUS2_ADCMPO2_Pos (14) /*!< EADC_T::STATUS2: ADCMPO2 Position */ +#define EADC_STATUS2_ADCMPO2_Msk (0x1ul << EADC_STATUS2_ADCMPO2_Pos) /*!< EADC_T::STATUS2: ADCMPO2 Mask */ + +#define EADC_STATUS2_ADCMPO3_Pos (15) /*!< EADC_T::STATUS2: ADCMPO3 Position */ +#define EADC_STATUS2_ADCMPO3_Msk (0x1ul << EADC_STATUS2_ADCMPO3_Pos) /*!< EADC_T::STATUS2: ADCMPO3 Mask */ + +#define EADC_STATUS2_CHANNEL_Pos (16) /*!< EADC_T::STATUS2: CHANNEL Position */ +#define EADC_STATUS2_CHANNEL_Msk (0x1ful << EADC_STATUS2_CHANNEL_Pos) /*!< EADC_T::STATUS2: CHANNEL Mask */ + +#define EADC_STATUS2_BUSY_Pos (23) /*!< EADC_T::STATUS2: BUSY Position */ +#define EADC_STATUS2_BUSY_Msk (0x1ul << EADC_STATUS2_BUSY_Pos) /*!< EADC_T::STATUS2: BUSY Mask */ + +#define EADC_STATUS2_ADOVIF_Pos (24) /*!< EADC_T::STATUS2: ADOVIF Position */ +#define EADC_STATUS2_ADOVIF_Msk (0x1ul << EADC_STATUS2_ADOVIF_Pos) /*!< EADC_T::STATUS2: ADOVIF Mask */ + +#define EADC_STATUS2_STOVF_Pos (25) /*!< EADC_T::STATUS2: STOVF Position */ +#define EADC_STATUS2_STOVF_Msk (0x1ul << EADC_STATUS2_STOVF_Pos) /*!< EADC_T::STATUS2: STOVF Mask */ + +#define EADC_STATUS2_AVALID_Pos (26) /*!< EADC_T::STATUS2: AVALID Position */ +#define EADC_STATUS2_AVALID_Msk (0x1ul << EADC_STATUS2_AVALID_Pos) /*!< EADC_T::STATUS2: AVALID Mask */ + +#define EADC_STATUS2_AOV_Pos (27) /*!< EADC_T::STATUS2: AOV Position */ +#define EADC_STATUS2_AOV_Msk (0x1ul << EADC_STATUS2_AOV_Pos) /*!< EADC_T::STATUS2: AOV Mask */ + +#define EADC_STATUS3_CURSPL_Pos (0) /*!< EADC_T::STATUS3: CURSPL Position */ +#define EADC_STATUS3_CURSPL_Msk (0x1ful << EADC_STATUS3_CURSPL_Pos) /*!< EADC_T::STATUS3: CURSPL Mask */ + +#define EADC_DDAT0_RESULT_Pos (0) /*!< EADC_T::DDAT0: RESULT Position */ +#define EADC_DDAT0_RESULT_Msk (0xfffful << EADC_DDAT0_RESULT_Pos) /*!< EADC_T::DDAT0: RESULT Mask */ + +#define EADC_DDAT0_OV_Pos (16) /*!< EADC_T::DDAT0: OV Position */ +#define EADC_DDAT0_OV_Msk (0x1ul << EADC_DDAT0_OV_Pos) /*!< EADC_T::DDAT0: OV Mask */ + +#define EADC_DDAT0_VALID_Pos (17) /*!< EADC_T::DDAT0: VALID Position */ +#define EADC_DDAT0_VALID_Msk (0x1ul << EADC_DDAT0_VALID_Pos) /*!< EADC_T::DDAT0: VALID Mask */ + +#define EADC_DDAT1_RESULT_Pos (0) /*!< EADC_T::DDAT1: RESULT Position */ +#define EADC_DDAT1_RESULT_Msk (0xfffful << EADC_DDAT1_RESULT_Pos) /*!< EADC_T::DDAT1: RESULT Mask */ + +#define EADC_DDAT1_OV_Pos (16) /*!< EADC_T::DDAT1: OV Position */ +#define EADC_DDAT1_OV_Msk (0x1ul << EADC_DDAT1_OV_Pos) /*!< EADC_T::DDAT1: OV Mask */ + +#define EADC_DDAT1_VALID_Pos (17) /*!< EADC_T::DDAT1: VALID Position */ +#define EADC_DDAT1_VALID_Msk (0x1ul << EADC_DDAT1_VALID_Pos) /*!< EADC_T::DDAT1: VALID Mask */ + +#define EADC_DDAT2_RESULT_Pos (0) /*!< EADC_T::DDAT2: RESULT Position */ +#define EADC_DDAT2_RESULT_Msk (0xfffful << EADC_DDAT2_RESULT_Pos) /*!< EADC_T::DDAT2: RESULT Mask */ + +#define EADC_DDAT2_OV_Pos (16) /*!< EADC_T::DDAT2: OV Position */ +#define EADC_DDAT2_OV_Msk (0x1ul << EADC_DDAT2_OV_Pos) /*!< EADC_T::DDAT2: OV Mask */ + +#define EADC_DDAT2_VALID_Pos (17) /*!< EADC_T::DDAT2: VALID Position */ +#define EADC_DDAT2_VALID_Msk (0x1ul << EADC_DDAT2_VALID_Pos) /*!< EADC_T::DDAT2: VALID Mask */ + +#define EADC_DDAT3_RESULT_Pos (0) /*!< EADC_T::DDAT3: RESULT Position */ +#define EADC_DDAT3_RESULT_Msk (0xfffful << EADC_DDAT3_RESULT_Pos) /*!< EADC_T::DDAT3: RESULT Mask */ + +#define EADC_DDAT3_OV_Pos (16) /*!< EADC_T::DDAT3: OV Position */ +#define EADC_DDAT3_OV_Msk (0x1ul << EADC_DDAT3_OV_Pos) /*!< EADC_T::DDAT3: OV Mask */ + +#define EADC_DDAT3_VALID_Pos (17) /*!< EADC_T::DDAT3: VALID Position */ +#define EADC_DDAT3_VALID_Msk (0x1ul << EADC_DDAT3_VALID_Pos) /*!< EADC_T::DDAT3: VALID Mask */ + +#define EADC_PWRM_PWUPRDY_Pos (0) /*!< EADC_T::PWRM: PWUPRDY Position */ +#define EADC_PWRM_PWUPRDY_Msk (0x1ul << EADC_PWRM_PWUPRDY_Pos) /*!< EADC_T::PWRM: PWUPRDY Mask */ + +#define EADC_PWRM_PWUCALEN_Pos (1) /*!< EADC_T::PWRM: PWUCALEN Position */ +#define EADC_PWRM_PWUCALEN_Msk (0x1ul << EADC_PWRM_PWUCALEN_Pos) /*!< EADC_T::PWRM: PWUCALEN Mask */ + +#define EADC_PWRM_PWDMOD_Pos (2) /*!< EADC_T::PWRM: PWDMOD Position */ +#define EADC_PWRM_PWDMOD_Msk (0x3ul << EADC_PWRM_PWDMOD_Pos) /*!< EADC_T::PWRM: PWDMOD Mask */ + +#define EADC_PWRM_LDOSUT_Pos (8) /*!< EADC_T::PWRM: LDOSUT Position */ +#define EADC_PWRM_LDOSUT_Msk (0xffful << EADC_PWRM_LDOSUT_Pos) /*!< EADC_T::PWRM: LDOSUT Mask */ + +#define EADC_CALCTL_CALSTART_Pos (1) /*!< EADC_T::CALCTL: CALSTART Position */ +#define EADC_CALCTL_CALSTART_Msk (0x1ul << EADC_CALCTL_CALSTART_Pos) /*!< EADC_T::CALCTL: CALSTART Mask */ + +#define EADC_CALCTL_CALDONE_Pos (2) /*!< EADC_T::CALCTL: CALDONE Position */ +#define EADC_CALCTL_CALDONE_Msk (0x1ul << EADC_CALCTL_CALDONE_Pos) /*!< EADC_T::CALCTL: CALDONE Mask */ + +#define EADC_CALCTL_CALSEL_Pos (3) /*!< EADC_T::CALCTL: CALSEL Position */ +#define EADC_CALCTL_CALSEL_Msk (0x1ul << EADC_CALCTL_CALSEL_Pos) /*!< EADC_T::CALCTL: CALSEL Mask */ + +#define EADC_CALDWRD_CALWORD_Pos (0) /*!< EADC_T::CALDWRD: CALWORD Position */ +#define EADC_CALDWRD_CALWORD_Msk (0x7ful << EADC_CALDWRD_CALWORD_Pos) /*!< EADC_T::CALDWRD: CALWORD Mask */ + +#define EADC_PDMACTL_PDMATEN_Pos (0) /*!< EADC_T::PDMACTL: PDMATEN Position */ +#define EADC_PDMACTL_PDMATEN_Msk (0x7fffful << EADC_PDMACTL_PDMATEN_Pos) /*!< EADC_T::PDMACTL: PDMATEN Mask */ + + +/**@}*/ /* EADC_CONST */ +/**@}*/ /* end of EADC register group */ +/**@}*/ /* end of REGISTER group */ + + + +#endif /* __EADC_REG_H__ */ diff --git a/Ubiquitous/XiZi/board/nuvoton-m2354/third_party_driver/include/Regs/ebi_reg.h b/Ubiquitous/XiZi/board/nuvoton-m2354/third_party_driver/include/Regs/ebi_reg.h new file mode 100644 index 0000000..f884d34 --- /dev/null +++ b/Ubiquitous/XiZi/board/nuvoton-m2354/third_party_driver/include/Regs/ebi_reg.h @@ -0,0 +1,163 @@ +/**************************************************************************//** + * @file ebi_reg.h + * @version V1.00 + * @brief EBI register definition header file + * + * @copyright SPDX-License-Identifier: Apache-2.0 + * @copyright Copyright (C) 2020 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ +#ifndef __EBI_REG_H__ +#define __EBI_REG_H__ + +/** @addtogroup REGISTER Control Register + + @{ + +*/ + + +/*---------------------- External Bus Interface Controller -------------------------*/ +/** + @addtogroup EBI External Bus Interface Controller(EBI) + Memory Mapped Structure for EBI Controller + @{ +*/ + +typedef struct +{ + + + /** + * @var EBI_T::CTL0 + * Offset: 0x00 External Bus Interface Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |EN |EBI Enable Bit + * | | |This bit is the functional enable bit for EBI. + * | | |0 = EBI function Disabled. + * | | |1 = EBI function Enabled. + * |[1] |DW16 |EBI Data Width 16-bit Select + * | | |This bit defines if the EBI data width is 8-bit or 16-bit. + * | | |0 = EBI data width is 8-bit. + * | | |1 = EBI data width is 16-bit. + * |[2] |CSPOLINV |Chip Select Pin Polar Inverse + * | | |This bit defines the active level of EBI chip select pin (EBI_nCS). + * | | |0 = Chip select pin (EBI_nCS) is active low. + * | | |1 = Chip select pin (EBI_nCS) is active high. + * |[3] |ADSEPEN |EBI Address/Data Bus Separating Mode Enable Bit + * | | |0 = Address/Data Bus Separating Mode Disabled. + * | | |1 = Address/Data Bus Separating Mode Enabled. + * |[4] |CACCESS |Continuous Data Access Mode + * | | |When continuous access mode enabled, the tASU, tALE and tLHD cycles are bypass for continuous data transfer request. + * | | |0 = Continuous data access mode Disabled. + * | | |1 = Continuous data access mode Enabled. + * |[10:8] |MCLKDIV |External Output Clock Divider + * | | |The frequency of EBI output clock (MCLK) is controlled by MCLKDIV as follow: + * | | |000 = HCLK/1. + * | | |001 = HCLK/2. + * | | |010 = HCLK/4. + * | | |011 = HCLK/8. + * | | |100 = HCLK/16. + * | | |101 = HCLK/32. + * | | |110 = HCLK/64. + * | | |111 = HCLK/128. + * |[18:16] |TALE |Extend Time of ALE + * | | |The EBI_ALE high pulse period (tALE) to latch the address can be controlled by TALE. + * | | |tALE = (TALE+1)*EBI_MCLK. + * | | |Note: This field only available in EBI_CTL0 register + * |[24] |WBUFEN |EBI Write Buffer Enable Bit + * | | |0 = EBI write buffer Disabled. + * | | |1 = EBI write buffer Enabled. + * | | |Note: This bit only available in EBI_CTL0 register + * @var EBI_T::TCTL0 + * Offset: 0x04 External Bus Interface Timing Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[7:3] |TACC |EBI Data Access Time + * | | |TACC define data access time (tACC). + * | | |tACC = (TACC+1) * EBI_MCLK. + * |[10:8] |TAHD |EBI Data Access Hold Time + * | | |TAHD define data access hold time (tAHD). + * | | |tAHD = (TAHD+1) * EBI_MCLK. + * |[15:12] |W2X |Idle Cycle After Write + * | | |This field defines the number of W2X idle cycle. + * | | |W2X idle cycle = (W2X * EBI_MCLK). + * | | |When write action is finish, W2X idle cycle is inserted and EBI_nCS return to idle state. + * |[22] |RAHDOFF |Access Hold Time Disable Control When Read + * | | |0 = The Data Access Hold Time (tAHD) during EBI reading is Enabled. + * | | |1 = The Data Access Hold Time (tAHD) during EBI reading is Disabled. + * |[23] |WAHDOFF |Access Hold Time Disable Control When Write + * | | |0 = The Data Access Hold Time (tAHD) during EBI writing is Enabled. + * | | |1 = The Data Access Hold Time (tAHD) during EBI writing is Disabled. + * |[27:24] |R2R |Idle Cycle Between Read-to-read + * | | |This field defines the number of R2R idle cycle. + * | | |R2R idle cycle = (R2R * EBI_MCLK). + * | | |When read action is finish and next action is going to read, R2R idle cycle is inserted and EBI_nCS return to idle state. + */ + __IO uint32_t CTL0; /*!< [0x0000] External Bus Interface Bank0 Control Register */ + __IO uint32_t TCTL0; /*!< [0x0004] External Bus Interface Bank0 Timing Control Register */ + __I uint32_t RESERVE0[2]; + __IO uint32_t CTL1; /*!< [0x0010] External Bus Interface Bank1 Control Register */ + __IO uint32_t TCTL1; /*!< [0x0014] External Bus Interface Bank1 Timing Control Register */ + __I uint32_t RESERVE1[2]; + __IO uint32_t CTL2; /*!< [0x0020] External Bus Interface Bank2 Control Register */ + __IO uint32_t TCTL2; /*!< [0x0024] External Bus Interface Bank2 Timing Control Register */ + +} EBI_T; + +/** + @addtogroup EBI_CONST EBI Bit Field Definition + Constant Definitions for EBI Controller + @{ +*/ + +#define EBI_CTL_EN_Pos (0) /*!< EBI_T::CTL0: EN Position */ +#define EBI_CTL_EN_Msk (0x1ul << EBI_CTL_EN_Pos) /*!< EBI_T::CTL0: EN Mask */ + +#define EBI_CTL_DW16_Pos (1) /*!< EBI_T::CTL0: DW16 Position */ +#define EBI_CTL_DW16_Msk (0x1ul << EBI_CTL_DW16_Pos) /*!< EBI_T::CTL0: DW16 Mask */ + +#define EBI_CTL_CSPOLINV_Pos (2) /*!< EBI_T::CTL0: CSPOLINV Position */ +#define EBI_CTL_CSPOLINV_Msk (0x1ul << EBI_CTL_CSPOLINV_Pos) /*!< EBI_T::CTL0: CSPOLINV Mask */ + +#define EBI_CTL_ADSEPEN_Pos (3) /*!< EBI_T::CTL0: ADSEPEN Position */ +#define EBI_CTL_ADSEPEN_Msk (0x1ul << EBI_CTL_ADSEPEN_Pos) /*!< EBI_T::CTL0: ADSEPEN Mask */ + +#define EBI_CTL_CACCESS_Pos (4) /*!< EBI_T::CTL0: CACCESS Position */ +#define EBI_CTL_CACCESS_Msk (0x1ul << EBI_CTL_CACCESS_Pos) /*!< EBI_T::CTL0: CACCESS Mask */ + +#define EBI_CTL_MCLKDIV_Pos (8) /*!< EBI_T::CTL0: MCLKDIV Position */ +#define EBI_CTL_MCLKDIV_Msk (0x7ul << EBI_CTL_MCLKDIV_Pos) /*!< EBI_T::CTL0: MCLKDIV Mask */ + +#define EBI_CTL_TALE_Pos (16) /*!< EBI_T::CTL0: TALE Position */ +#define EBI_CTL_TALE_Msk (0x7ul << EBI_CTL_TALE_Pos) /*!< EBI_T::CTL0: TALE Mask */ + +#define EBI_CTL_WBUFEN_Pos (24) /*!< EBI_T::CTL0: WBUFEN Position */ +#define EBI_CTL_WBUFEN_Msk (0x1ul << EBI_CTL_WBUFEN_Pos) /*!< EBI_T::CTL0: WBUFEN Mask */ + +#define EBI_TCTL_TACC_Pos (3) /*!< EBI_T::TCTL0: TACC Position */ +#define EBI_TCTL_TACC_Msk (0x1ful << EBI_TCTL_TACC_Pos) /*!< EBI_T::TCTL0: TACC Mask */ + +#define EBI_TCTL_TAHD_Pos (8) /*!< EBI_T::TCTL0: TAHD Position */ +#define EBI_TCTL_TAHD_Msk (0x7ul << EBI_TCTL_TAHD_Pos) /*!< EBI_T::TCTL0: TAHD Mask */ + +#define EBI_TCTL_W2X_Pos (12) /*!< EBI_T::TCTL0: W2X Position */ +#define EBI_TCTL_W2X_Msk (0xful << EBI_TCTL_W2X_Pos) /*!< EBI_T::TCTL0: W2X Mask */ + +#define EBI_TCTL_RAHDOFF_Pos (22) /*!< EBI_T::TCTL0: RAHDOFF Position */ +#define EBI_TCTL_RAHDOFF_Msk (0x1ul << EBI_TCTL_RAHDOFF_Pos) /*!< EBI_T::TCTL0: RAHDOFF Mask */ + +#define EBI_TCTL_WAHDOFF_Pos (23) /*!< EBI_T::TCTL0: WAHDOFF Position */ +#define EBI_TCTL_WAHDOFF_Msk (0x1ul << EBI_TCTL_WAHDOFF_Pos) /*!< EBI_T::TCTL0: WAHDOFF Mask */ + +#define EBI_TCTL_R2R_Pos (24) /*!< EBI_T::TCTL0: R2R Position */ +#define EBI_TCTL_R2R_Msk (0xful << EBI_TCTL_R2R_Pos) /*!< EBI_T::TCTL0: R2R Mask */ + +/**@}*/ /* EBI_CONST */ +/**@}*/ /* end of EBI register group */ +/**@}*/ /* end of REGISTER group */ + + +#endif /* __EBI_REG_H__ */ diff --git a/Ubiquitous/XiZi/board/nuvoton-m2354/third_party_driver/include/Regs/ecap_reg.h b/Ubiquitous/XiZi/board/nuvoton-m2354/third_party_driver/include/Regs/ecap_reg.h new file mode 100644 index 0000000..8710ce5 --- /dev/null +++ b/Ubiquitous/XiZi/board/nuvoton-m2354/third_party_driver/include/Regs/ecap_reg.h @@ -0,0 +1,388 @@ +/**************************************************************************//** + * @file ecap_reg.h + * @version V1.00 + * @brief ECAP register definition header file + * + * @copyright SPDX-License-Identifier: Apache-2.0 + * @copyright Copyright (C) 2020 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ +#ifndef __ECAP_REG_H__ +#define __ECAP_REG_H__ + +/** + @addtogroup REGISTER Control Register + + @{ + +*/ + +/*---------------------- Enhanced Input Capture Timer -------------------------*/ +/** + @addtogroup ECAP Enhanced Input Capture Timer(ECAP) + Memory Mapped Structure for ECAP Controller + @{ +*/ + +typedef struct +{ + + /** + * @var ECAP_T::CNT + * Offset: 0x00 Input Capture Counter (24-bit up counter) + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[23:0] |CNT |Input Capture Timer/Counter + * | | |The input Capture Timer/Counter is a 24-bit up-counting counter + * | | |The clock source for the counter is from the clock divider + * @var ECAP_T::HLD0 + * Offset: 0x04 Input Capture Hold Register 0 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[23:0] |HOLD |Input Capture Counter Hold Register + * | | |When an active input capture channel detects a valid edge signal change, the ECAPCNT value is latched into the corresponding holding register + * | | |Each input channel has its own holding register named by ECAP_HLDx where x is from 0 to 2 to indicate inputs from IC0 to IC2, respectively. + * @var ECAP_T::HLD1 + * Offset: 0x08 Input Capture Hold Register 1 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[23:0] |HOLD |Input Capture Counter Hold Register + * | | |When an active input capture channel detects a valid edge signal change, the ECAPCNT value is latched into the corresponding holding register + * | | |Each input channel has its own holding register named by ECAP_HLDx where x is from 0 to 2 to indicate inputs from IC0 to IC2, respectively. + * @var ECAP_T::HLD2 + * Offset: 0x0C Input Capture Hold Register 2 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[23:0] |HOLD |Input Capture Counter Hold Register + * | | |When an active input capture channel detects a valid edge signal change, the ECAPCNT value is latched into the corresponding holding register + * | | |Each input channel has its own holding register named by ECAP_HLDx where x is from 0 to 2 to indicate inputs from IC0 to IC2, respectively. + * @var ECAP_T::CNTCMP + * Offset: 0x10 Input Capture Compare Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[23:0] |CNTCMP |Input Capture Counter Compare Register + * | | |If the compare function is enabled (CMPEN = 1), this register (ECAP_CNTCMP) is used to compare with the capture counter (ECAP_CNT). + * | | |If the reload control is enabled (RLDEN[n] = 1, n=0~3), an overflow event or capture events will trigger the hardware to load the value of this register (ECAP_CNTCMP) into ECAP_CNT. + * @var ECAP_T::CTL0 + * Offset: 0x14 Input Capture Control Register 0 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[2:0] |NFCLKSEL |Noise Filter Clock Pre-divide Selection + * | | |To determine the sampling frequency of the Noise Filter clock + * | | |000 = CAP_CLK. + * | | |001 = CAP_CLK/2. + * | | |010 = CAP_CLK/4. + * | | |011 = CAP_CLK/16. + * | | |100 = CAP_CLK/32. + * | | |101 = CAP_CLK/64. + * |[3] |CAPNFDIS |Input Capture Noise Filter Disable Control + * | | |0 = Noise filter of Input Capture Enabled. + * | | |1 = Noise filter of Input Capture Disabled (Bypass). + * |[4] |IC0EN |Port Pin IC0 Input to Input Capture Unit Enable Control + * | | |0 = IC0 input to Input Capture Unit Disabled. + * | | |1 = IC0 input to Input Capture Unit Enabled. + * |[5] |IC1EN |Port Pin IC1 Input to Input Capture Unit Enable Control + * | | |0 = IC1 input to Input Capture Unit Disabled. + * | | |1 = IC1 input to Input Capture Unit Enabled. + * |[6] |IC2EN |Port Pin IC2 Input to Input Capture Unit Enable Control + * | | |0 = IC2 input to Input Capture Unit Disabled. + * | | |1 = IC2 input to Input Capture Unit Enabled. + * |[9:8] |CAPSEL0 |CAP0 Input Source Selection + * | | |00 = CAP0 input is from port pin ICAP0. + * | | |01 = Reserved. + * | | |10 = CAP0 input is from signal CHA of QEI controller unit n. + * | | |11 = Reserved. + * | | |Note: Input capture unit n matches QEIn, where n = 0~1. + * |[11:10] |CAPSEL1 |CAP1 Input Source Selection + * | | |00 = CAP1 input is from port pin ICAP1. + * | | |01 = Reserved. + * | | |10 = CAP1 input is from signal CHB of QEI controller unit n. + * | | |11 = Reserved. + * | | |Note: Input capture unit n matches QEIn, where n = 0~1. + * |[13:12] |CAPSEL2 |CAP2 Input Source Selection + * | | |00 = CAP2 input is from port pin ICAP2. + * | | |01 = Reserved. + * | | |10 = CAP2 input is from signal CHX of QEI controller unit n. + * | | |11 = Reserved. + * | | |Note: Input capture unit n matches QEIn, where n = 0~1. + * |[16] |CAPIEN0 |Input Capture Channel 0 Interrupt Enable Control + * | | |0 = The flag CAPTF0 can trigger Input Capture interrupt Disabled. + * | | |1 = The flag CAPTF0 can trigger Input Capture interrupt Enabled. + * |[17] |CAPIEN1 |Input Capture Channel 1 Interrupt Enable Control + * | | |0 = The flag CAPTF1 can trigger Input Capture interrupt Disabled. + * | | |1 = The flag CAPTF1 can trigger Input Capture interrupt Enabled. + * |[18] |CAPIEN2 |Input Capture Channel 2 Interrupt Enable Control + * | | |0 = The flag CAPTF2 can trigger Input Capture interrupt Disabled. + * | | |1 = The flag CAPTF2 can trigger Input Capture interrupt Enabled. + * |[20] |OVIEN |CAPOVF Trigger Input Capture Interrupt Enable Control + * | | |0 = The flag CAPOVF can trigger Input Capture interrupt Disabled. + * | | |1 = The flag CAPOVF can trigger Input Capture interrupt Enabled. + * |[21] |CMPIEN |CAPCMPF Trigger Input Capture Interrupt Enable Control + * | | |0 = The flag CAPCMPF can trigger Input Capture interrupt Disabled. + * | | |1 = The flag CAPCMPF can trigger Input Capture interrupt Enabled. + * |[24] |CNTEN |Input Capture Counter Start Counting Control + * | | |Setting this bit to 1, the capture counter (ECAP_CNT) starts up-counting synchronously with the clock from the . + * | | |0 = ECAP_CNT stop counting. + * | | |1 = ECAP_CNT starts up-counting. + * |[25] |CMPCLREN |Input Capture Counter Cleared by Compare-match Control + * | | |If this bit is set to 1, the capture counter (ECAP_CNT) will be cleared to 0 when the compare-match event (CAPCMPF = 1) occurs. + * | | |0 = Compare-match event (CAPCMPF) can clear capture counter (ECAP_CNT) Disabled. + * | | |1 = Compare-match event (CAPCMPF) can clear capture counter (ECAP_CNT) Enabled. + * |[28] |CMPEN |Compare Function Enable Control + * | | |The compare function in input capture timer/counter is to compare the dynamic counting ECAP_CNT with the compare register ECAP_CNTCMP, if ECAP_CNT value reaches ECAP_CNTCMP, the flag CAPCMPF will be set. + * | | |0 = The compare function Disabled. + * | | |1 = The compare function Enabled. + * |[29] |CAPEN |Input Capture Timer/Counter Enable Control + * | | |0 = Input Capture function Disabled. + * | | |1 = Input Capture function Enabled. + * @var ECAP_T::CTL1 + * Offset: 0x18 Input Capture Control Register 1 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[1:0] |EDGESEL0 |Channel 0 Captured Edge Selection + * | | |Input capture0 can detect falling edge change only, rising edge change only or both edge change + * | | |00 = Detect rising edge only. + * | | |01 = Detect falling edge only. + * | | |1x = Detect both rising and falling edge. + * |[3:2] |EDGESEL1 |Channel 1 Captured Edge Selection + * | | |Input capture1 can detect falling edge change only, rising edge change only or both edge change + * | | |00 = Detect rising edge only. + * | | |01 = Detect falling edge only. + * | | |1x = Detect both rising and falling edge. + * |[5:4] |EDGESEL2 |Channel 2 Captured Edge Selection + * | | |Input capture2 can detect falling edge change only, rising edge change only or both edge changes + * | | |00 = Detect rising edge only. + * | | |01 = Detect falling edge only. + * | | |1x = Detect both rising and falling edge. + * |[8] |CAP0RLDEN |Capture Counteru2019s Reload Function Triggered by Event CAPTE0 Enable Bit + * | | |0 = The reload triggered by Event CAPTE0 Disabled. + * | | |1 = The reload triggered by Event CAPTE0 Enabled. + * |[9] |CAP1RLDEN |Capture Counteru2019s Reload Function Triggered by Event CAPTE1 Enable Bit + * | | |0 = The reload triggered by Event CAPTE1 Disabled. + * | | |1 = The reload triggered by Event CAPTE1 Enabled. + * |[10] |CAP2RLDEN |Capture Counteru2019s Reload Function Triggered by Event CAPTE2 Enable Bit + * | | |0 = The reload triggered by Event CAPTE2 Disabled. + * | | |1 = The reload triggered by Event CAPTE2 Enabled. + * |[11] |OVRLDEN |Capture Counteru2019s Reload Function Triggered by Overflow Enable Bit + * | | |0 = The reload triggered by CAPOV Disabled. + * | | |1 = The reload triggered by CAPOV Enabled. + * |[14:12] |CLKSEL |Capture Timer Clock Divide Selection + * | | |The capture timer clock has a pre-divider with eight divided options controlled by CLKSEL[2:0]. + * | | |000 = CAP_CLK/1. + * | | |001 = CAP_CLK/4. + * | | |010 = CAP_CLK/16. + * | | |011 = CAP_CLK/32. + * | | |100 = CAP_CLK/64. + * | | |101 = CAP_CLK/96. + * | | |110 = CAP_CLK/112. + * | | |111 = CAP_CLK/128. + * |[17:16] |CNTSRCSEL |Capture Timer/Counter Clock Source Selection + * | | |Select the capture timer/counter clock source. + * | | |00 = CAP_CLK (default). + * | | |01 = CAP0. + * | | |10 = CAP1. + * | | |11 = CAP2. + * |[20] |CAP0CLREN |Capture Counter Cleared by Capture Event0 Control + * | | |0 = Event CAPTE0 can clear capture counter (ECAP_CNT) Disabled. + * | | |1 = Event CAPTE0 can clear capture counter (ECAP_CNT) Enabled. + * |[21] |CAP1CLREN |Capture Counter Cleared by Capture Event1 Control + * | | |0 = Event CAPTE1 can clear capture counter (ECAP_CNT) Disabled. + * | | |1 = Event CAPTE1 can clear capture counter (ECAP_CNT) Enabled. + * |[22] |CAP2CLREN |Capture Counter Cleared by Capture Event2 Control + * | | |0 = Event CAPTE2 can clear capture counter (ECAP_CNT) Disabled. + * | | |1 = Event CAPTE2 can clear capture counter (ECAP_CNT) Enabled. + * @var ECAP_T::STATUS + * Offset: 0x1C Input Capture Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |CAPTF0 |Input Capture Channel 0 Triggered Flag + * | | |When the input capture channel 0 detects a valid edge change at CAP0 input, it will set flag CAPTF0 to high. + * | | |0 = No valid edge change has been detected at CAP0 input since last clear. + * | | |1 = At least a valid edge change has been detected at CAP0 input since last clear. + * | | |Note: This bit is only cleared by writing 1 to it. + * |[1] |CAPTF1 |Input Capture Channel 1 Triggered Flag + * | | |When the input capture channel 1 detects a valid edge change at CAP1 input, it will set flag CAPTF1 to high. + * | | |0 = No valid edge change has been detected at CAP1 input since last clear. + * | | |1 = At least a valid edge change has been detected at CAP1 input since last clear. + * | | |Note: This bit is only cleared by writing 1 to it. + * |[2] |CAPTF2 |Input Capture Channel 2 Triggered Flag + * | | |When the input capture channel 2 detects a valid edge change at CAP2 input, it will set flag CAPTF2 to high. + * | | |0 = No valid edge change has been detected at CAP2 input since last clear. + * | | |1 = At least a valid edge change has been detected at CAP2 input since last clear. + * | | |Note: This bit is only cleared by writing 1 to it. + * |[4] |CAPCMPF |Input Capture Compare-match Flag + * | | |If the input capture compare function is enabled, the flag is set by hardware when capture counter (ECAP_CNT) up counts and reaches the ECAP_CNTCMP value. + * | | |0 = ECAP_CNT has not matched ECAP_CNTCMP value since last clear. + * | | |1 = ECAP_CNT has matched ECAP_CNTCMP value at least once since last clear. + * | | |Note: This bit is only cleared by writing 1 to it. + * |[5] |CAPOVF |Input Capture Counter Overflow Flag + * | | |Flag is set by hardware when counter (ECAP_CNT) overflows from 0x00FF_FFFF to zero. + * | | |0 = No overflow event has occurred since last clear. + * | | |1 = Overflow event(s) has/have occurred since last clear. + * | | |Note: This bit is only cleared by writing 1 to it. + * |[6] |CAP0 |Value of Input Channel 0, CAP0 (Read Only) + * | | |Reflecting the value of input channel 0, CAP0 + * | | |(The bit is read only and write is ignored) + * |[7] |CAP1 |Value of Input Channel 1, CAP1 (Read Only) + * | | |Reflecting the value of input channel 1, CAP1 + * | | |(The bit is read only and write is ignored) + * |[8] |CAP2 |Value of Input Channel 2, CAP2 (Read Only) + * | | |Reflecting the value of input channel 2, CAP2. + * | | |(The bit is read only and write is ignored) + */ + __IO uint32_t CNT; /*!< [0x0000] Input Capture Counter */ + __IO uint32_t HLD0; /*!< [0x0004] Input Capture Hold Register 0 */ + __IO uint32_t HLD1; /*!< [0x0008] Input Capture Hold Register 1 */ + __IO uint32_t HLD2; /*!< [0x000c] Input Capture Hold Register 2 */ + __IO uint32_t CNTCMP; /*!< [0x0010] Input Capture Compare Register */ + __IO uint32_t CTL0; /*!< [0x0014] Input Capture Control Register 0 */ + __IO uint32_t CTL1; /*!< [0x0018] Input Capture Control Register 1 */ + __IO uint32_t STATUS; /*!< [0x001c] Input Capture Status Register */ + +} ECAP_T; + +/** + @addtogroup ECAP_CONST ECAP Bit Field Definition + Constant Definitions for ECAP Controller + @{ +*/ + +#define ECAP_CNT_CNT_Pos (0) /*!< ECAP_T::CNT: CNT Position */ +#define ECAP_CNT_CNT_Msk (0xfffffful << ECAP_CNT_CNT_Pos) /*!< ECAP_T::CNT: CNT Mask */ + +#define ECAP_HLD0_HOLD_Pos (0) /*!< ECAP_T::HLD0: HOLD Position */ +#define ECAP_HLD0_HOLD_Msk (0xfffffful << ECAP_HLD0_HOLD_Pos) /*!< ECAP_T::HLD0: HOLD Mask */ + +#define ECAP_HLD1_HOLD_Pos (0) /*!< ECAP_T::HLD1: HOLD Position */ +#define ECAP_HLD1_HOLD_Msk (0xfffffful << ECAP_HLD1_HOLD_Pos) /*!< ECAP_T::HLD1: HOLD Mask */ + +#define ECAP_HLD2_HOLD_Pos (0) /*!< ECAP_T::HLD2: HOLD Position */ +#define ECAP_HLD2_HOLD_Msk (0xfffffful << ECAP_HLD2_HOLD_Pos) /*!< ECAP_T::HLD2: HOLD Mask */ + +#define ECAP_CNTCMP_CNTCMP_Pos (0) /*!< ECAP_T::CNTCMP: CNTCMP Position */ +#define ECAP_CNTCMP_CNTCMP_Msk (0xfffffful << ECAP_CNTCMP_CNTCMP_Pos) /*!< ECAP_T::CNTCMP: CNTCMP Mask */ + +#define ECAP_CTL0_NFCLKSEL_Pos (0) /*!< ECAP_T::CTL0: NFCLKSEL Position */ +#define ECAP_CTL0_NFCLKSEL_Msk (0x7ul << ECAP_CTL0_NFCLKSEL_Pos) /*!< ECAP_T::CTL0: NFCLKSEL Mask */ + +#define ECAP_CTL0_CAPNFDIS_Pos (3) /*!< ECAP_T::CTL0: CAPNFDIS Position */ +#define ECAP_CTL0_CAPNFDIS_Msk (0x1ul << ECAP_CTL0_CAPNFDIS_Pos) /*!< ECAP_T::CTL0: CAPNFDIS Mask */ + +#define ECAP_CTL0_IC0EN_Pos (4) /*!< ECAP_T::CTL0: IC0EN Position */ +#define ECAP_CTL0_IC0EN_Msk (0x1ul << ECAP_CTL0_IC0EN_Pos) /*!< ECAP_T::CTL0: IC0EN Mask */ + +#define ECAP_CTL0_IC1EN_Pos (5) /*!< ECAP_T::CTL0: IC1EN Position */ +#define ECAP_CTL0_IC1EN_Msk (0x1ul << ECAP_CTL0_IC1EN_Pos) /*!< ECAP_T::CTL0: IC1EN Mask */ + +#define ECAP_CTL0_IC2EN_Pos (6) /*!< ECAP_T::CTL0: IC2EN Position */ +#define ECAP_CTL0_IC2EN_Msk (0x1ul << ECAP_CTL0_IC2EN_Pos) /*!< ECAP_T::CTL0: IC2EN Mask */ + +#define ECAP_CTL0_CAPSEL0_Pos (8) /*!< ECAP_T::CTL0: CAPSEL0 Position */ +#define ECAP_CTL0_CAPSEL0_Msk (0x3ul << ECAP_CTL0_CAPSEL0_Pos) /*!< ECAP_T::CTL0: CAPSEL0 Mask */ + +#define ECAP_CTL0_CAPSEL1_Pos (10) /*!< ECAP_T::CTL0: CAPSEL1 Position */ +#define ECAP_CTL0_CAPSEL1_Msk (0x3ul << ECAP_CTL0_CAPSEL1_Pos) /*!< ECAP_T::CTL0: CAPSEL1 Mask */ + +#define ECAP_CTL0_CAPSEL2_Pos (12) /*!< ECAP_T::CTL0: CAPSEL2 Position */ +#define ECAP_CTL0_CAPSEL2_Msk (0x3ul << ECAP_CTL0_CAPSEL2_Pos) /*!< ECAP_T::CTL0: CAPSEL2 Mask */ + +#define ECAP_CTL0_CAPIEN0_Pos (16) /*!< ECAP_T::CTL0: CAPIEN0 Position */ +#define ECAP_CTL0_CAPIEN0_Msk (0x1ul << ECAP_CTL0_CAPIEN0_Pos) /*!< ECAP_T::CTL0: CAPIEN0 Mask */ + +#define ECAP_CTL0_CAPIEN1_Pos (17) /*!< ECAP_T::CTL0: CAPIEN1 Position */ +#define ECAP_CTL0_CAPIEN1_Msk (0x1ul << ECAP_CTL0_CAPIEN1_Pos) /*!< ECAP_T::CTL0: CAPIEN1 Mask */ + +#define ECAP_CTL0_CAPIEN2_Pos (18) /*!< ECAP_T::CTL0: CAPIEN2 Position */ +#define ECAP_CTL0_CAPIEN2_Msk (0x1ul << ECAP_CTL0_CAPIEN2_Pos) /*!< ECAP_T::CTL0: CAPIEN2 Mask */ + +#define ECAP_CTL0_OVIEN_Pos (20) /*!< ECAP_T::CTL0: OVIEN Position */ +#define ECAP_CTL0_OVIEN_Msk (0x1ul << ECAP_CTL0_OVIEN_Pos) /*!< ECAP_T::CTL0: OVIEN Mask */ + +#define ECAP_CTL0_CMPIEN_Pos (21) /*!< ECAP_T::CTL0: CMPIEN Position */ +#define ECAP_CTL0_CMPIEN_Msk (0x1ul << ECAP_CTL0_CMPIEN_Pos) /*!< ECAP_T::CTL0: CMPIEN Mask */ + +#define ECAP_CTL0_CNTEN_Pos (24) /*!< ECAP_T::CTL0: CNTEN Position */ +#define ECAP_CTL0_CNTEN_Msk (0x1ul << ECAP_CTL0_CNTEN_Pos) /*!< ECAP_T::CTL0: CNTEN Mask */ + +#define ECAP_CTL0_CMPCLREN_Pos (25) /*!< ECAP_T::CTL0: CMPCLREN Position */ +#define ECAP_CTL0_CMPCLREN_Msk (0x1ul << ECAP_CTL0_CMPCLREN_Pos) /*!< ECAP_T::CTL0: CMPCLREN Mask */ + +#define ECAP_CTL0_CMPEN_Pos (28) /*!< ECAP_T::CTL0: CMPEN Position */ +#define ECAP_CTL0_CMPEN_Msk (0x1ul << ECAP_CTL0_CMPEN_Pos) /*!< ECAP_T::CTL0: CMPEN Mask */ + +#define ECAP_CTL0_CAPEN_Pos (29) /*!< ECAP_T::CTL0: CAPEN Position */ +#define ECAP_CTL0_CAPEN_Msk (0x1ul << ECAP_CTL0_CAPEN_Pos) /*!< ECAP_T::CTL0: CAPEN Mask */ + +#define ECAP_CTL1_EDGESEL0_Pos (0) /*!< ECAP_T::CTL1: EDGESEL0 Position */ +#define ECAP_CTL1_EDGESEL0_Msk (0x3ul << ECAP_CTL1_EDGESEL0_Pos) /*!< ECAP_T::CTL1: EDGESEL0 Mask */ + +#define ECAP_CTL1_EDGESEL1_Pos (2) /*!< ECAP_T::CTL1: EDGESEL1 Position */ +#define ECAP_CTL1_EDGESEL1_Msk (0x3ul << ECAP_CTL1_EDGESEL1_Pos) /*!< ECAP_T::CTL1: EDGESEL1 Mask */ + +#define ECAP_CTL1_EDGESEL2_Pos (4) /*!< ECAP_T::CTL1: EDGESEL2 Position */ +#define ECAP_CTL1_EDGESEL2_Msk (0x3ul << ECAP_CTL1_EDGESEL2_Pos) /*!< ECAP_T::CTL1: EDGESEL2 Mask */ + +#define ECAP_CTL1_CAP0RLDEN_Pos (8) /*!< ECAP_T::CTL1: CAP0RLDEN Position */ +#define ECAP_CTL1_CAP0RLDEN_Msk (0x1ul << ECAP_CTL1_CAP0RLDEN_Pos) /*!< ECAP_T::CTL1: CAP0RLDEN Mask */ + +#define ECAP_CTL1_CAP1RLDEN_Pos (9) /*!< ECAP_T::CTL1: CAP1RLDEN Position */ +#define ECAP_CTL1_CAP1RLDEN_Msk (0x1ul << ECAP_CTL1_CAP1RLDEN_Pos) /*!< ECAP_T::CTL1: CAP1RLDEN Mask */ + +#define ECAP_CTL1_CAP2RLDEN_Pos (10) /*!< ECAP_T::CTL1: CAP2RLDEN Position */ +#define ECAP_CTL1_CAP2RLDEN_Msk (0x1ul << ECAP_CTL1_CAP2RLDEN_Pos) /*!< ECAP_T::CTL1: CAP2RLDEN Mask */ + +#define ECAP_CTL1_OVRLDEN_Pos (11) /*!< ECAP_T::CTL1: OVRLDEN Position */ +#define ECAP_CTL1_OVRLDEN_Msk (0x1ul << ECAP_CTL1_OVRLDEN_Pos) /*!< ECAP_T::CTL1: OVRLDEN Mask */ + +#define ECAP_CTL1_CLKSEL_Pos (12) /*!< ECAP_T::CTL1: CLKSEL Position */ +#define ECAP_CTL1_CLKSEL_Msk (0x7ul << ECAP_CTL1_CLKSEL_Pos) /*!< ECAP_T::CTL1: CLKSEL Mask */ + +#define ECAP_CTL1_CNTSRCSEL_Pos (16) /*!< ECAP_T::CTL1: CNTSRCSEL Position */ +#define ECAP_CTL1_CNTSRCSEL_Msk (0x3ul << ECAP_CTL1_CNTSRCSEL_Pos) /*!< ECAP_T::CTL1: CNTSRCSEL Mask */ + +#define ECAP_CTL1_CAP0CLREN_Pos (20) /*!< ECAP_T::CTL1: CAP0CLREN Position */ +#define ECAP_CTL1_CAP0CLREN_Msk (0x1ul << ECAP_CTL1_CAP0CLREN_Pos) /*!< ECAP_T::CTL1: CAP0CLREN Mask */ + +#define ECAP_CTL1_CAP1CLREN_Pos (21) /*!< ECAP_T::CTL1: CAP1CLREN Position */ +#define ECAP_CTL1_CAP1CLREN_Msk (0x1ul << ECAP_CTL1_CAP1CLREN_Pos) /*!< ECAP_T::CTL1: CAP1CLREN Mask */ + +#define ECAP_CTL1_CAP2CLREN_Pos (22) /*!< ECAP_T::CTL1: CAP2CLREN Position */ +#define ECAP_CTL1_CAP2CLREN_Msk (0x1ul << ECAP_CTL1_CAP2CLREN_Pos) /*!< ECAP_T::CTL1: CAP2CLREN Mask */ + +#define ECAP_STATUS_CAPTF0_Pos (0) /*!< ECAP_T::STATUS: CAPTF0 Position */ +#define ECAP_STATUS_CAPTF0_Msk (0x1ul << ECAP_STATUS_CAPTF0_Pos) /*!< ECAP_T::STATUS: CAPTF0 Mask */ + +#define ECAP_STATUS_CAPTF1_Pos (1) /*!< ECAP_T::STATUS: CAPTF1 Position */ +#define ECAP_STATUS_CAPTF1_Msk (0x1ul << ECAP_STATUS_CAPTF1_Pos) /*!< ECAP_T::STATUS: CAPTF1 Mask */ + +#define ECAP_STATUS_CAPTF2_Pos (2) /*!< ECAP_T::STATUS: CAPTF2 Position */ +#define ECAP_STATUS_CAPTF2_Msk (0x1ul << ECAP_STATUS_CAPTF2_Pos) /*!< ECAP_T::STATUS: CAPTF2 Mask */ + +#define ECAP_STATUS_CAPCMPF_Pos (4) /*!< ECAP_T::STATUS: CAPCMPF Position */ +#define ECAP_STATUS_CAPCMPF_Msk (0x1ul << ECAP_STATUS_CAPCMPF_Pos) /*!< ECAP_T::STATUS: CAPCMPF Mask */ + +#define ECAP_STATUS_CAPOVF_Pos (5) /*!< ECAP_T::STATUS: CAPOVF Position */ +#define ECAP_STATUS_CAPOVF_Msk (0x1ul << ECAP_STATUS_CAPOVF_Pos) /*!< ECAP_T::STATUS: CAPOVF Mask */ + +#define ECAP_STATUS_CAP0_Pos (8) /*!< ECAP_T::STATUS: CAP0 Position */ +#define ECAP_STATUS_CAP0_Msk (0x1ul << ECAP_STATUS_CAP0_Pos) /*!< ECAP_T::STATUS: CAP0 Mask */ + +#define ECAP_STATUS_CAP1_Pos (9) /*!< ECAP_T::STATUS: CAP1 Position */ +#define ECAP_STATUS_CAP1_Msk (0x1ul << ECAP_STATUS_CAP1_Pos) /*!< ECAP_T::STATUS: CAP1 Mask */ + +#define ECAP_STATUS_CAP2_Pos (10) /*!< ECAP_T::STATUS: CAP2 Position */ +#define ECAP_STATUS_CAP2_Msk (0x1ul << ECAP_STATUS_CAP2_Pos) /*!< ECAP_T::STATUS: CAP2 Mask */ + +/**@}*/ /* ECAP_CONST */ +/**@}*/ /* end of ECAP register group */ +/**@}*/ /* end of REGISTER group */ + + +#endif /* __ECAP_REG_H__ */ diff --git a/Ubiquitous/XiZi/board/nuvoton-m2354/third_party_driver/include/Regs/epwm_reg.h b/Ubiquitous/XiZi/board/nuvoton-m2354/third_party_driver/include/Regs/epwm_reg.h new file mode 100644 index 0000000..813f8b1 --- /dev/null +++ b/Ubiquitous/XiZi/board/nuvoton-m2354/third_party_driver/include/Regs/epwm_reg.h @@ -0,0 +1,4001 @@ +/**************************************************************************//** + * @file epwm_reg.h + * @version V1.00 + * @brief EPWM register definition header file + * + * @copyright SPDX-License-Identifier: Apache-2.0 + * @copyright Copyright (C) 2020 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ +#ifndef __EPWM_REG_H__ +#define __EPWM_REG_H__ + +/** + @addtogroup REGISTER Control Register + + @{ + +*/ + + +/*---------------------- Enhanced Pulse Width Modulation Controller -------------------------*/ +/** + @addtogroup EPWM Enhanced Pulse Width Modulation Controller(EPWM) + Memory Mapped Structure for EPWM Controller + @{ +*/ + +typedef struct +{ + /** + * @var ECAPDAT_T::RCAPDAT + * Offset: 0x20C EPWM Rising Capture Data Register 0~5 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |RCAPDAT |EPWM Rising Capture Data (Read Only) + * | | |When rising capture condition happened, the EPWM counter value will be saved in this register. + * @var ECAPDAT_T::FCAPDAT + * Offset: 0x210 EPWM Falling Capture Data Register 0~5 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |FCAPDAT |EPWM Falling Capture Data (Read Only) + * | | |When falling capture condition happened, the EPWM counter value will be saved in this register. + */ + __IO uint32_t RCAPDAT; /*!< [0x20C/0x214/0x21C/0x224/0x22C/0x234] EPWM Rising Capture Data Register 0~5 */ + __IO uint32_t FCAPDAT; /*!< [0x210/0x218/0x220/0x228/0x230/0x238] EPWM Falling Capture Data Register 0~5 */ +} ECAPDAT_T; + +typedef struct +{ + + + /** + * @var EPWM_T::CTL0 + * Offset: 0x00 EPWM Control Register 0 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |CTRLD0 |Center Re-load + * | | |In up-down counter type, PERIOD0 register will load to PBUF0 register at the end point of each period. + * | | |CMPDAT0 register will load to CMPBUF0 register at the center point of a period. + * |[1] |CTRLD1 |Center Re-load + * | | |In up-down counter type, PERIOD1 register will load to PBUF1 register at the end point of each period. + * | | |CMPDAT1 register will load to CMPBUF1 register at the center point of a period. + * |[2] |CTRLD2 |Center Re-load + * | | |In up-down counter type, PERIOD2 register will load to PBUF2 register at the end point of each period. + * | | |CMPDAT2 register will load to CMPBUF2 register at the center point of a period. + * |[3] |CTRLD3 |Center Re-load + * | | |In up-down counter type, PERIOD3 register will load to PBUF3 register at the end point of each period. + * | | |CMPDAT3 register will load to CMPBUF3 register at the center point of a period. + * |[4] |CTRLD4 |Center Re-load + * | | |In up-down counter type, PERIOD4 register will load to PBUF4 register at the end point of each period. + * | | |CMPDAT4 register will load to CMPBUF4 register at the center point of a period. + * |[5] |CTRLD5 |Center Re-load + * | | |In up-down counter type, PERIOD5 register will load to PBUF5 register at the end point of each period. + * | | |CMPDAT5 register will load to CMPBUF5 register at the center point of a period. + * |[8] |WINLDEN0 |Window Load Enable Bits + * | | |0 = PERIOD0 register will load to PBUF0 register at the end point of each period. + * | | |CMPDAT0 register will load to CMPBUF0 register at the end point or center point of each period by setting CTRLD0 bit. + * | | |1 = PERIOD0 register will load to PBUF0 and CMPDAT0 registers will load to CMPBUF0 register at the end point of each period when valid reload window is set. + * | | |The valid reload window is set by software write 1 to EPWM_LOAD register, and cleared by hardware after load success. + * |[9] |WINLDEN1 |Window Load Enable Bits + * | | |0 = PERIOD1 register will load to PBUF1 register at the end point of each period. + * | | |CMPDAT1 register will load to CMPBUF1 register at the end point or center point of each period by setting CTRLD1 bit. + * | | |1 = PERIOD1 register will load to PBUF1 and CMPDAT1 registers will load to CMPBUF1 register at the end point of each period when valid reload window is set. + * | | |The valid reload window is set by software write 1 to EPWM_LOAD register, and cleared by hardware after load success. + * |[10] |WINLDEN2 |Window Load Enable Bits + * | | |0 = PERIOD2 register will load to PBUF2 register at the end point of each period. + * | | |CMPDAT2 register will load to CMPBUF2 register at the end point or center point of each period by setting CTRLD2 bit. + * | | |1 = PERIOD2 register will load to PBUF2 and CMPDAT2 registers will load to CMPBUF2 register at the end point of each period when valid reload window is set. + * | | |The valid reload window is set by software write 1 to EPWM_LOAD register, and cleared by hardware after load success. + * |[11] |WINLDEN3 |Window Load Enable Bits + * | | |0 = PERIOD3 register will load to PBUF3 register at the end point of each period. + * | | |CMPDAT3 register will load to CMPBUF3 register at the end point or center point of each period by setting CTRLD3 bit. + * | | |1 = PERIOD3 register will load to PBUF3 and CMPDAT3 registers will load to CMPBUF3 register at the end point of each period when valid reload window is set. + * | | |The valid reload window is set by software write 1 to EPWM_LOAD register, and cleared by hardware after load success. + * |[12] |WINLDEN4 |Window Load Enable Bits + * | | |0 = PERIOD4 register will load to PBUF4 register at the end point of each period. + * | | |CMPDAT4 register will load to CMPBUF4 register at the end point or center point of each period by setting CTRLD4 bit. + * | | |1 = PERIOD4 register will load to PBUF4 and CMPDAT4 registers will load to CMPBUF4 register at the end point of each period when valid reload window is set. + * | | |The valid reload window is set by software write 1 to EPWM_LOAD register, and cleared by hardware after load success. + * |[13] |WINLDEN5 |Window Load Enable Bits + * | | |0 = PERIOD5 register will load to PBUF5 register at the end point of each period. + * | | |CMPDAT5 register will load to CMPBUF5 register at the end point or center point of each period by setting CTRLD5 bit. + * | | |1 = PERIOD5 register will load to PBUF5 and CMPDAT5 registers will load to CMPBUF5 register at the end point of each period when valid reload window is set. + * | | |The valid reload window is set by software write 1 to EPWM_LOAD register, and cleared by hardware after load success. + * |[16] |IMMLDEN0 |Immediately Load Enable Bits + * | | |0 = PERIOD0 register will load to PBUF0 register at the end point of each period. + * | | |CMPDAT0 register will load to CMPBUF0 register at the end point or center point of each period by setting CTRLD0 bit. + * | | |1 = PERIOD0/CMPDAT0 registers will load to PBUF0 and CMPBUF0 register immediately when software update PERIOD0/CMPDAT0 register. + * | | |Note: If IMMLDEN0 bit is enabled, WINLDEN0 bit and CTRLD0 bits will be invalid. + * |[17] |IMMLDEN1 |Immediately Load Enable Bits + * | | |0 = PERIOD1 register will load to PBUF1 register at the end point of each period. + * | | |CMPDAT1 register will load to CMPBUF1 register at the end point or center point of each period by setting CTRLD1 bit. + * | | |1 = PERIOD1/CMPDAT1 registers will load to PBUF1 and CMPBUF1 register immediately when software update PERIOD1/CMPDAT1 register. + * | | |Note: If IMMLDEN1 bit is enabled, WINLDEN1 bit and CTRLD1 bits will be invalid. + * |[18] |IMMLDEN2 |Immediately Load Enable Bits + * | | |0 = PERIOD2 register will load to PBUF2 register at the end point of each period. + * | | |CMPDAT2 register will load to CMPBUF2 register at the end point or center point of each period by setting CTRLD2 bit. + * | | |1 = PERIOD2/CMPDAT2 registers will load to PBUF2 and CMPBUF2 register immediately when software update PERIOD2/CMPDAT2 register. + * | | |Note: If IMMLDEN2 bit is enabled, WINLDEN2 bit and CTRLD2 bits will be invalid. + * |[19] |IMMLDEN3 |Immediately Load Enable Bits + * | | |0 = PERIOD3 register will load to PBUF3 register at the end point of each period. + * | | |CMPDAT3 register will load to CMPBUF3 register at the end point or center point of each period by setting CTRLD3 bit. + * | | |1 = PERIOD3/CMPDAT3 registers will load to PBUF3 and CMPBUF3 register immediately when software update PERIOD3/CMPDAT3 register. + * | | |Note: If IMMLDEN3 bit is enabled, WINLDEN3 bit and CTRLD3 bits will be invalid. + * |[20] |IMMLDEN4 |Immediately Load Enable Bits + * | | |0 = PERIOD4 register will load to PBUF4 register at the end point of each period. + * | | |CMPDAT4 register will load to CMPBUF4 register at the end point or center point of each period by setting CTRLD4 bit. + * | | |1 = PERIOD4/CMPDAT4 registers will load to PBUF4 and CMPBUF4 register immediately when software update PERIOD4/CMPDAT4 register. + * | | |Note: If IMMLDEN4 bit is enabled, WINLDEN4 bit and CTRLD4 bits will be invalid. + * |[21] |IMMLDEN5 |Immediately Load Enable Bits + * | | |0 = PERIOD5 register will load to PBUF5 register at the end point of each period. + * | | |CMPDAT5 register will load to CMPBUF5 register at the end point or center point of each period by setting CTRLD5 bit. + * | | |1 = PERIOD5/CMPDAT5 registers will load to PBUF5 and CMPBUF5 register immediately when software update PERIOD5/CMPDAT5 register. + * | | |Note: If IMMLDEN5 bit is enabled, WINLDEN5 bit and CTRLD5 bits will be invalid. + * |[24] |GROUPEN |Group Function Enable Bit + * | | |0 = The output waveform of each EPWM channel are independent. + * | | |1 = Unify the EPWMx_CH2 and EPWMx_CH4 to output the same waveform as EPWMx_CH0 and unify the EPWMx_CH3 and EPWMx_CH5 to output the same waveform as EPWMx_CH1. + * |[30] |DBGHALT |ICE Debug Mode Counter Halt (Write Protect) + * | | |If counter halt is enabled, EPWM all counters will keep current value until exit ICE debug mode. + * | | |0 = ICE debug mode counter halt disable. + * | | |1 = ICE debug mode counter halt enable. + * | | |Note: This register is write protected. Refer toSYS_REGLCTL register. + * |[31] |DBGTRIOFF |ICE Debug Mode Acknowledge Disable (Write Protect) + * | | |0 = ICE debug mode acknowledgement effects EPWM output. + * | | |EPWM pin will be forced as tri-state while ICE debug mode acknowledged. + * | | |1 = ICE debug mode acknowledgement disabled. + * | | |EPWM pin will keep output no matter ICE debug mode acknowledged or not. + * | | |Note: This register is write protected. Refer to SYS_REGLCTL register. + * @var EPWM_T::CTL1 + * Offset: 0x04 EPWM Control Register 1 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[1:0] |CNTTYPE0 |EPWM Counter Behavior Type + * | | |00 = Up counter type (supports in capture mode). + * | | |01 = Down count type (supports in capture mode). + * | | |10 = Up-down counter type. + * | | |11 = Reserved. + * |[3:2] |CNTTYPE1 |EPWM Counter Behavior Type + * | | |00 = Up counter type (supports in capture mode). + * | | |01 = Down count type (supports in capture mode). + * | | |10 = Up-down counter type. + * | | |11 = Reserved. + * |[5:4] |CNTTYPE2 |EPWM Counter Behavior Type + * | | |00 = Up counter type (supports in capture mode). + * | | |01 = Down count type (supports in capture mode). + * | | |10 = Up-down counter type. + * | | |11 = Reserved. + * |[7:6] |CNTTYPE3 |EPWM Counter Behavior Type + * | | |00 = Up counter type (supports in capture mode). + * | | |01 = Down count type (supports in capture mode). + * | | |10 = Up-down counter type. + * | | |11 = Reserved. + * |[9:8] |CNTTYPE4 |EPWM Counter Behavior Type + * | | |00 = Up counter type (supports in capture mode). + * | | |01 = Down count type (supports in capture mode). + * | | |10 = Up-down counter type. + * | | |11 = Reserved. + * |[11:10] |CNTTYPE5 |EPWM Counter Behavior Type + * | | |00 = Up counter type (supports in capture mode). + * | | |01 = Down count type (supports in capture mode). + * | | |10 = Up-down counter type. + * | | |11 = Reserved. + * |[16] |CNTMODE0 |EPWM Counter Mode + * | | |0 = Auto-reload mode. + * | | |1 = One-shot mode. + * |[17] |CNTMODE1 |EPWM Counter Mode + * | | |0 = Auto-reload mode. + * | | |1 = One-shot mode. + * |[18] |CNTMODE2 |EPWM Counter Mode + * | | |0 = Auto-reload mode. + * | | |1 = One-shot mode. + * |[19] |CNTMODE3 |EPWM Counter Mode + * | | |0 = Auto-reload mode. + * | | |1 = One-shot mode. + * |[20] |CNTMODE4 |EPWM Counter Mode + * | | |0 = Auto-reload mode. + * | | |1 = One-shot mode. + * |[21] |CNTMODE5 |EPWM Counter Mode + * | | |0 = Auto-reload mode. + * | | |1 = One-shot mode. + * |[24] |OUTMODE0 |EPWM Output Mode + * | | |Each bit n controls the output mode of corresponding EPWM channel n. + * | | |0 = EPWM independent mode. + * | | |1 = EPWM complementary mode. + * | | |Note: When operating in group function, these bits must all set to the same mode. + * |[25] |OUTMODE2 |EPWM Output Mode + * | | |Each bit n controls the output mode of corresponding EPWM channel n. + * | | |0 = EPWM independent mode. + * | | |1 = EPWM complementary mode. + * | | |Note: When operating in group function, these bits must all set to the same mode. + * |[26] |OUTMODE4 |EPWM Output Mode + * | | |Each bit n controls the output mode of corresponding EPWM channel n. + * | | |0 = EPWM independent mode. + * | | |1 = EPWM complementary mode. + * | | |Note: When operating in group function, these bits must all set to the same mode. + * @var EPWM_T::SYNC + * Offset: 0x08 EPWM Synchronization Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |PHSEN0 |SYNC Phase Enable Bits + * | | |0 = EPWM counter disable to load PHS value. + * | | |1 = EPWM counter enable to load PHS value. + * |[1] |PHSEN2 |SYNC Phase Enable Bits + * | | |0 = EPWM counter disable to load PHS value. + * | | |1 = EPWM counter enable to load PHS value. + * |[2] |PHSEN4 |SYNC Phase Enable Bits + * | | |0 = EPWM counter disable to load PHS value. + * | | |1 = EPWM counter enable to load PHS value. + * |[9:8] |SINSRC0 |EPWM0_SYNC_IN Source Selection + * | | |00 = Synchronize source from SYNC_IN or SWSYNC. + * | | |01 = Counter equal to 0. + * | | |10 = Counter equal to EPWM_CMPDATm, m denotes 1, 3, 5. + * | | |11 = SYNC_OUT will not be generated. + * |[11:10] |SINSRC2 |EPWM0_SYNC_IN Source Selection + * | | |00 = Synchronize source from SYNC_IN or SWSYNC. + * | | |01 = Counter equal to 0. + * | | |10 = Counter equal to EPWM_CMPDATm, m denotes 1, 3, 5. + * | | |11 = SYNC_OUT will not be generated. + * |[13:12] |SINSRC4 |EPWM0_SYNC_IN Source Selection + * | | |00 = Synchronize source from SYNC_IN or SWSYNC. + * | | |01 = Counter equal to 0. + * | | |10 = Counter equal to EPWM_CMPDATm, m denotes 1, 3, 5. + * | | |11 = SYNC_OUT will not be generated. + * |[16] |SNFLTEN |EPWM0_SYNC_IN Noise Filter Enable Bits + * | | |0 = Noise filter of input pin EPWM0_SYNC_IN is Disabled. + * | | |1 = Noise filter of input pin EPWM0_SYNC_IN is Enabled. + * |[19:17] |SFLTCSEL |SYNC Edge Detector Filter Clock Selection + * | | |000 = Filter clock = HCLK. + * | | |001 = Filter clock = HCLK/2. + * | | |010 = Filter clock = HCLK/4. + * | | |011 = Filter clock = HCLK/8. + * | | |100 = Filter clock = HCLK/16. + * | | |101 = Filter clock = HCLK/32. + * | | |110 = Filter clock = HCLK/64. + * | | |111 = Filter clock = HCLK/128. + * |[22:20] |SFLTCNT |SYNC Edge Detector Filter Count + * | | |The register bits control the counter number of edge detector. + * |[23] |SINPINV |SYNC Input Pin Inverse + * | | |0 = The state of pin EPWM0_SYNC_IN is passed to the negative edge detector. + * | | |1 = The inverse state of pin EPWM0_SYNC_IN is passed to the negative edge detector. + * |[24] |PHSDIR0 |EPWM Phase Direction Control + * | | |0 = Control EPWM counter count decrement after synchronizing. + * | | |1 = Control EPWM counter count increment after synchronizing. + * |[25] |PHSDIR2 |EPWM Phase Direction Control + * | | |0 = Control EPWM counter count decrement after synchronizing. + * | | |1 = Control EPWM counter count increment after synchronizing. + * |[26] |PHSDIR4 |EPWM Phase Direction Control + * | | |0 = Control EPWM counter count decrement after synchronizing. + * | | |1 = Control EPWM counter count increment after synchronizing. + * @var EPWM_T::SWSYNC + * Offset: 0x0C EPWM Software Control Synchronization Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |SWSYNC0 |Software SYNC Function + * | | |When SINSRCn (EPWM_SYNC[13:8]) is selected to 0, SYNC_OUT source is come from SYNC_IN or this bit. + * |[1] |SWSYNC2 |Software SYNC Function + * | | |When SINSRCn (EPWM_SYNC[13:8]) is selected to 0, SYNC_OUT source is come from SYNC_IN or this bit. + * |[2] |SWSYNC4 |Software SYNC Function + * | | |When SINSRCn (EPWM_SYNC[13:8]) is selected to 0, SYNC_OUT source is come from SYNC_IN or this bit. + * @var EPWM_T::CLKSRC + * Offset: 0x10 EPWM Clock Source Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[2:0] |ECLKSRC0 |EPWM_CH01 External Clock Source Select + * | | |000 = EPWMx_CLK, x denotes 0 or 1. + * | | |001 = TIMER0 overflow. + * | | |010 = TIMER1 overflow. + * | | |011 = TIMER2 overflow. + * | | |100 = TIMER3 overflow. + * | | |Others = Reserved. + * |[10:8] |ECLKSRC2 |EPWM_CH23 External Clock Source Select + * | | |000 = EPWMx_CLK, x denotes 0 or 1. + * | | |001 = TIMER0 overflow. + * | | |010 = TIMER1 overflow. + * | | |011 = TIMER2 overflow. + * | | |100 = TIMER3 overflow. + * | | |Others = Reserved. + * |[18:16] |ECLKSRC4 |EPWM_CH45 External Clock Source Select + * | | |000 = EPWMx_CLK, x denotes 0 or 1. + * | | |001 = TIMER0 overflow. + * | | |010 = TIMER1 overflow. + * | | |011 = TIMER2 overflow. + * | | |100 = TIMER3 overflow. + * | | |Others = Reserved. + * @var EPWM_T::CLKPSC[3] + * Offset: 0x14 EPWM Clock Prescale Register 0/1, 2/3, 4/5 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[11:0] |CLKPSC |EPWM Counter Clock Prescale + * | | |The clock of EPWM counter is decided by clock prescaler + * | | |Each EPWM pair share one EPWM counter clock prescaler + * | | |The clock of EPWM counter is divided by (CLKPSC+ 1) + * @var EPWM_T::CNTEN + * Offset: 0x20 EPWM Counter Enable Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |CNTEN0 |EPWM Counter Enable Bits + * | | |0 = EPWM Counter and clock prescaler Stop Running. + * | | |1 = EPWM Counter and clock prescaler Start Running. + * |[1] |CNTEN1 |EPWM Counter Enable Bits + * | | |0 = EPWM Counter and clock prescaler Stop Running. + * | | |1 = EPWM Counter and clock prescaler Start Running. + * |[2] |CNTEN2 |EPWM Counter Enable Bits + * | | |0 = EPWM Counter and clock prescaler Stop Running. + * | | |1 = EPWM Counter and clock prescaler Start Running. + * |[3] |CNTEN3 |EPWM Counter Enable Bits + * | | |0 = EPWM Counter and clock prescaler Stop Running. + * | | |1 = EPWM Counter and clock prescaler Start Running. + * |[4] |CNTEN4 |EPWM Counter Enable Bits + * | | |0 = EPWM Counter and clock prescaler Stop Running. + * | | |1 = EPWM Counter and clock prescaler Start Running. + * |[5] |CNTEN5 |EPWM Counter Enable Bits + * | | |0 = EPWM Counter and clock prescaler Stop Running. + * | | |1 = EPWM Counter and clock prescaler Start Running. + * @var EPWM_T::CNTCLR + * Offset: 0x24 EPWM Clear Counter Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |CNTCLR0 |Clear EPWM Counter Control Bit + * | | |It is automatically cleared by hardware. + * | | |0 = No effect. + * | | |1 = Clear 16-bit EPWM counter to 0000H. + * |[1] |CNTCLR1 |Clear EPWM Counter Control Bit + * | | |It is automatically cleared by hardware. + * | | |0 = No effect. + * | | |1 = Clear 16-bit EPWM counter to 0000H. + * |[2] |CNTCLR2 |Clear EPWM Counter Control Bit + * | | |It is automatically cleared by hardware. + * | | |0 = No effect. + * | | |1 = Clear 16-bit EPWM counter to 0000H. + * |[3] |CNTCLR3 |Clear EPWM Counter Control Bit + * | | |It is automatically cleared by hardware. + * | | |0 = No effect. + * | | |1 = Clear 16-bit EPWM counter to 0000H. + * |[4] |CNTCLR4 |Clear EPWM Counter Control Bit + * | | |It is automatically cleared by hardware. + * | | |0 = No effect. + * | | |1 = Clear 16-bit EPWM counter to 0000H. + * |[5] |CNTCLR5 |Clear EPWM Counter Control Bit + * | | |It is automatically cleared by hardware. + * | | |0 = No effect. + * | | |1 = Clear 16-bit EPWM counter to 0000H. + * @var EPWM_T::LOAD + * Offset: 0x28 EPWM Load Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |LOAD0 |Re-load EPWM Comparator Register (CMPDAT) Control Bit + * | | |This bit is software write, hardware clear when current EPWM period end. + * | | |Write Operation: + * | | |0 = No effect. + * | | |1 = Set load window of window loading mode. + * | | |Read Operation: + * | | |0 = No load window is set. + * | | |1 = Load window is set. + * | | |Note: This bit only use in window loading mode, WINLDEN0(EPWM_CTL0[13:8]) = 1. + * |[1] |LOAD1 |Re-load EPWM Comparator Register (CMPDAT) Control Bit + * | | |This bit is software write, hardware clear when current EPWM period end. + * | | |Write Operation: + * | | |0 = No effect. + * | | |1 = Set load window of window loading mode. + * | | |Read Operation: + * | | |0 = No load window is set. + * | | |1 = Load window is set. + * | | |Note: This bit only use in window loading mode, WINLDEN1(EPWM_CTL0[13:8]) = 1. + * |[2] |LOAD2 |Re-load EPWM Comparator Register (CMPDAT) Control Bit + * | | |This bit is software write, hardware clear when current EPWM period end. + * | | |Write Operation: + * | | |0 = No effect. + * | | |1 = Set load window of window loading mode. + * | | |Read Operation: + * | | |0 = No load window is set. + * | | |1 = Load window is set. + * | | |Note: This bit only use in window loading mode, WINLDEN2(EPWM_CTL0[13:8]) = 1. + * |[3] |LOAD3 |Re-load EPWM Comparator Register (CMPDAT) Control Bit + * | | |This bit is software write, hardware clear when current EPWM period end. + * | | |Write Operation: + * | | |0 = No effect. + * | | |1 = Set load window of window loading mode. + * | | |Read Operation: + * | | |0 = No load window is set. + * | | |1 = Load window is set. + * | | |Note: This bit only use in window loading mode, WINLDEN3(EPWM_CTL0[13:8]) = 1. + * |[4] |LOAD4 |Re-load EPWM Comparator Register (CMPDAT) Control Bit + * | | |This bit is software write, hardware clear when current EPWM period end. + * | | |Write Operation: + * | | |0 = No effect. + * | | |1 = Set load window of window loading mode. + * | | |Read Operation: + * | | |0 = No load window is set. + * | | |1 = Load window is set. + * | | |Note: This bit only use in window loading mode, WINLDEN4(EPWM_CTL0[13:8]) = 1. + * |[5] |LOAD5 |Re-load EPWM Comparator Register (CMPDAT) Control Bit + * | | |This bit is software write, hardware clear when current EPWM period end. + * | | |Write Operation: + * | | |0 = No effect. + * | | |1 = Set load window of window loading mode. + * | | |Read Operation: + * | | |0 = No load window is set. + * | | |1 = Load window is set. + * | | |Note: This bit only use in window loading mode, WINLDENn(EPWM_CTL0[13:8]) = 1. + * @var EPWM_T::PERIOD[6] + * Offset: 0x30 EPWM Period Register 0~5 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |PERIOD |EPWM Period Register + * | | |Up-Count mode: In this mode, EPWM counter counts from 0 to PERIOD, and restarts from 0. + * | | |Down-Count mode: In this mode, EPWM counter counts from PERIOD to 0, and restarts from PERIOD. + * | | |EPWM period time = (PERIOD+1) * EPWM_CLK period. + * | | |Up-Down-Count mode: In this mode, EPWM counter counts from 0 to PERIOD, then decrements to 0 and repeats again. + * | | |EPWM period time = 2 * PERIOD * EPWM_CLK period. + * @var EPWM_T::CMPDAT[6] + * Offset: 0x50 EPWM Comparator Register 0 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |CMP |EPWM Comparator Register + * | | |CMP use to compare with CNTR to generate EPWM waveform, interrupt and trigger EADC/DAC. + * | | |In independent mode, CMPDAT0~5 denote as 6 independent EPWM_CH0~5 compared point. + * | | |In complementary mode, CMPDAT0, 2, 4 denote as first compared point, and CMPDAT1, 3, 5 denote as second compared point for the corresponding 3 complementary pairs EPWM_CH0 and EPWM_CH1, EPWM_CH2 and EPWM_CH3, EPWM_CH4 and EPWM_CH5. + * @var EPWM_T::DTCTL[3] + * Offset: 0x70 EPWM Dead-Time Control Register 0/1,2/3,4/5 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[11:0] |DTCNT |Dead-time Counter (Write Protect) + * | | |The dead-time can be calculated from the following formula: + * | | |Dead-time = (DTCNT[11:0]+1) * EPWM_CLK period. + * | | |Note: This register is write protected. Refer to SYS_REGLCTL register. + * |[16] |DTEN |Enable Dead-time Insertion for EPWM Pair (EPWM_CH0, EPWM_CH1) (EPWM_CH2, EPWM_CH3) (EPWM_CH4, EPWM_CH5) (Write Protect) + * | | |Dead-time insertion is only active when this pair of complementary EPWM is enabled + * | | |If dead- time insertion is inactive, the outputs of pin pair are complementary without any delay. + * | | |0 = Dead-time insertion Disabled on the pin pair. + * | | |1 = Dead-time insertion Enabled on the pin pair. + * | | |Note: This register is write protected. Refer toSYS_REGLCTL register. + * |[24] |DTCKSEL |Dead-time Clock Select (Write Protect) + * | | |0 = Dead-time clock source from EPWM_CLK. + * | | |1 = Dead-time clock source from prescaler output. + * | | |Note: This register is write protected. Refer toREGWRPROT register. + * @var EPWM_T::PHS[3] + * Offset: 0x80 EPWM Counter Phase Register 0/1,2/3,4/5 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |PHS |EPWM Synchronous Start Phase Bits + * | | |PHS determines the EPWM synchronous start phase value. These bits only use in synchronous function. + * @var EPWM_T::CNT[6] + * Offset: 0x90 EPWM Counter Register 0~5 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |CNT |EPWM Data Register (Read Only) + * | | |User can monitor CNTR to know the current value in 16-bit period counter. + * |[16] |DIRF |EPWM Direction Indicator Flag (Read Only) + * | | |0 = Counter is Down count. + * | | |1 = Counter is UP count. + * @var EPWM_T::WGCTL0 + * Offset: 0xB0 EPWM Generation Register 0 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[1:0] |ZPCTL0 |EPWM Zero Point Control + * | | |00 = Do nothing. + * | | |01 = EPWM zero point output Low. + * | | |10 = EPWM zero point output High. + * | | |11 = EPWM zero point output Toggle. + * | | |EPWM can control output level when EPWM counter count to zero. + * |[3:2] |ZPCTL1 |EPWM Zero Point Control + * | | |00 = Do nothing. + * | | |01 = EPWM zero point output Low. + * | | |10 = EPWM zero point output High. + * | | |11 = EPWM zero point output Toggle. + * | | |EPWM can control output level when EPWM counter count to zero. + * |[5:4] |ZPCTL2 |EPWM Zero Point Control + * | | |00 = Do nothing. + * | | |01 = EPWM zero point output Low. + * | | |10 = EPWM zero point output High. + * | | |11 = EPWM zero point output Toggle. + * | | |EPWM can control output level when EPWM counter count to zero. + * |[7:6] |ZPCTL3 |EPWM Zero Point Control + * | | |00 = Do nothing. + * | | |01 = EPWM zero point output Low. + * | | |10 = EPWM zero point output High. + * | | |11 = EPWM zero point output Toggle. + * | | |EPWM can control output level when EPWM counter count to zero. + * |[9:8] |ZPCTL4 |EPWM Zero Point Control + * | | |00 = Do nothing. + * | | |01 = EPWM zero point output Low. + * | | |10 = EPWM zero point output High. + * | | |11 = EPWM zero point output Toggle. + * | | |EPWM can control output level when EPWM counter count to zero. + * |[11:10] |ZPCTL5 |EPWM Zero Point Control + * | | |00 = Do nothing. + * | | |01 = EPWM zero point output Low. + * | | |10 = EPWM zero point output High. + * | | |11 = EPWM zero point output Toggle. + * | | |EPWM can control output level when EPWM counter count to zero. + * |[17:16] |PRDPCTL0 |EPWM Period (Center) Point Control + * | | |00 = Do nothing. + * | | |01 = EPWM period (center) point output Low. + * | | |10 = EPWM period (center) point output High. + * | | |11 = EPWM period (center) point output Toggle. + * | | |EPWM can control output level when EPWM counter count to (PERIOD0+1). + * | | |Note: This bit is center point control when EPWM counter operating in up-down counter type. + * |[19:18] |PRDPCTL1 |EPWM Period (Center) Point Control + * | | |00 = Do nothing. + * | | |01 = EPWM period (center) point output Low. + * | | |10 = EPWM period (center) point output High. + * | | |11 = EPWM period (center) point output Toggle. + * | | |EPWM can control output level when EPWM counter count to (PERIOD1+1). + * | | |Note: This bit is center point control when EPWM counter operating in up-down counter type. + * |[21:20] |PRDPCTL2 |EPWM Period (Center) Point Control + * | | |00 = Do nothing. + * | | |01 = EPWM period (center) point output Low. + * | | |10 = EPWM period (center) point output High. + * | | |11 = EPWM period (center) point output Toggle. + * | | |EPWM can control output level when EPWM counter count to (PERIOD2+1). + * | | |Note: This bit is center point control when EPWM counter operating in up-down counter type. + * |[23:22] |PRDPCTL3 |EPWM Period (Center) Point Control + * | | |00 = Do nothing. + * | | |01 = EPWM period (center) point output Low. + * | | |10 = EPWM period (center) point output High. + * | | |11 = EPWM period (center) point output Toggle. + * | | |EPWM can control output level when EPWM counter count to (PERIOD3+1). + * | | |Note: This bit is center point control when EPWM counter operating in up-down counter type. + * |[25:24] |PRDPCTL4 |EPWM Period (Center) Point Control + * | | |00 = Do nothing. + * | | |01 = EPWM period (center) point output Low. + * | | |10 = EPWM period (center) point output High. + * | | |11 = EPWM period (center) point output Toggle. + * | | |EPWM can control output level when EPWM counter count to (PERIOD4+1). + * | | |Note: This bit is center point control when EPWM counter operating in up-down counter type. + * |[27:26] |PRDPCTL5 |EPWM Period (Center) Point Control + * | | |00 = Do nothing. + * | | |01 = EPWM period (center) point output Low. + * | | |10 = EPWM period (center) point output High. + * | | |11 = EPWM period (center) point output Toggle. + * | | |EPWM can control output level when EPWM counter count to (PERIOD5+1). + * | | |Note: This bit is center point control when EPWM counter operating in up-down counter type. + * @var EPWM_T::WGCTL1 + * Offset: 0xB4 EPWM Generation Register 1 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[1:0] |CMPUCTL0 |EPWM Compare Up Point Control + * | | |00 = Do nothing. + * | | |01 = EPWM compare up point output Low. + * | | |10 = EPWM compare up point output High. + * | | |11 = EPWM compare up point output Toggle. + * | | |EPWM can control output level when EPWM counter up count to CMPDAT. + * | | |Note: In complementary mode, CMPUCTL1, 3, 5 use as another CMPUCTL for channel 0, 2, 4. + * |[3:2] |CMPUCTL1 |EPWM Compare Up Point Control + * | | |00 = Do nothing. + * | | |01 = EPWM compare up point output Low. + * | | |10 = EPWM compare up point output High. + * | | |11 = EPWM compare up point output Toggle. + * | | |EPWM can control output level when EPWM counter up count to CMPDAT. + * | | |Note: In complementary mode, CMPUCTL1, 3, 5 use as another CMPUCTL for channel 0, 2, 4. + * |[5:4] |CMPUCTL2 |EPWM Compare Up Point Control + * | | |00 = Do nothing. + * | | |01 = EPWM compare up point output Low. + * | | |10 = EPWM compare up point output High. + * | | |11 = EPWM compare up point output Toggle. + * | | |EPWM can control output level when EPWM counter up count to CMPDAT. + * | | |Note: In complementary mode, CMPUCTL1, 3, 5 use as another CMPUCTL for channel 0, 2, 4. + * |[7:6] |CMPUCTL3 |EPWM Compare Up Point Control + * | | |00 = Do nothing. + * | | |01 = EPWM compare up point output Low. + * | | |10 = EPWM compare up point output High. + * | | |11 = EPWM compare up point output Toggle. + * | | |EPWM can control output level when EPWM counter up count to CMPDAT. + * | | |Note: In complementary mode, CMPUCTL1, 3, 5 use as another CMPUCTL for channel 0, 2, 4. + * |[9:8] |CMPUCTL4 |EPWM Compare Up Point Control + * | | |00 = Do nothing. + * | | |01 = EPWM compare up point output Low. + * | | |10 = EPWM compare up point output High. + * | | |11 = EPWM compare up point output Toggle. + * | | |EPWM can control output level when EPWM counter up count to CMPDAT. + * | | |Note: In complementary mode, CMPUCTL1, 3, 5 use as another CMPUCTL for channel 0, 2, 4. + * |[11:10] |CMPUCTL5 |EPWM Compare Up Point Control + * | | |00 = Do nothing. + * | | |01 = EPWM compare up point output Low. + * | | |10 = EPWM compare up point output High. + * | | |11 = EPWM compare up point output Toggle. + * | | |EPWM can control output level when EPWM counter up count to CMPDAT. + * | | |Note: In complementary mode, CMPUCTL1, 3, 5 use as another CMPUCTL for channel 0, 2, 4. + * |[17:16] |CMPDCTL0 |EPWM Compare Down Point Control + * | | |00 = Do nothing. + * | | |01 = EPWM compare down point output Low. + * | | |10 = EPWM compare down point output High. + * | | |11 = EPWM compare down point output Toggle. + * | | |EPWM can control output level when EPWM counter down count to CMPDAT. + * | | |Note: In complementary mode, CMPDCTL1, 3, 5 use as another CMPDCTL for channel 0, 2, 4. + * |[19:18] |CMPDCTL1 |EPWM Compare Down Point Control + * | | |00 = Do nothing. + * | | |01 = EPWM compare down point output Low. + * | | |10 = EPWM compare down point output High. + * | | |11 = EPWM compare down point output Toggle. + * | | |EPWM can control output level when EPWM counter down count to CMPDAT. + * | | |Note: In complementary mode, CMPDCTL1, 3, 5 use as another CMPDCTL for channel 0, 2, 4. + * |[21:20] |CMPDCTL2 |EPWM Compare Down Point Control + * | | |00 = Do nothing. + * | | |01 = EPWM compare down point output Low. + * | | |10 = EPWM compare down point output High. + * | | |11 = EPWM compare down point output Toggle. + * | | |EPWM can control output level when EPWM counter down count to CMPDAT. + * | | |Note: In complementary mode, CMPDCTL1, 3, 5 use as another CMPDCTL for channel 0, 2, 4. + * |[23:22] |CMPDCTL3 |EPWM Compare Down Point Control + * | | |00 = Do nothing. + * | | |01 = EPWM compare down point output Low. + * | | |10 = EPWM compare down point output High. + * | | |11 = EPWM compare down point output Toggle. + * | | |EPWM can control output level when EPWM counter down count to CMPDAT. + * | | |Note: In complementary mode, CMPDCTL1, 3, 5 use as another CMPDCTL for channel 0, 2, 4. + * |[25:24] |CMPDCTL4 |EPWM Compare Down Point Control + * | | |00 = Do nothing. + * | | |01 = EPWM compare down point output Low. + * | | |10 = EPWM compare down point output High. + * | | |11 = EPWM compare down point output Toggle. + * | | |EPWM can control output level when EPWM counter down count to CMPDAT. + * | | |Note: In complementary mode, CMPDCTL1, 3, 5 use as another CMPDCTL for channel 0, 2, 4. + * |[27:26] |CMPDCTL5 |EPWM Compare Down Point Control + * | | |00 = Do nothing. + * | | |01 = EPWM compare down point output Low. + * | | |10 = EPWM compare down point output High. + * | | |11 = EPWM compare down point output Toggle. + * | | |EPWM can control output level when EPWM counter down count to CMPDAT. + * | | |Note: In complementary mode, CMPDCTL1, 3, 5 use as another CMPDCTL for channel 0, 2, 4. + * @var EPWM_T::MSKEN + * Offset: 0xB8 EPWM Mask Enable Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |MSKEN0 |EPWM Mask Enable Bits + * | | |The EPWM output signal will be masked when this bit is enabled. + * | | |The corresponding EPWM channel 0 will output MSKDAT0 (EPWM_MSK[5:0]) data. + * | | |0 = EPWM output signal is non-masked. + * | | |1 = EPWM output signal is masked and output MSKDAT0 data. + * |[1] |MSKEN1 |EPWM Mask Enable Bits + * | | |The EPWM output signal will be masked when this bit is enabled. + * | | |The corresponding EPWM channel 1 will output MSKDAT1 (EPWM_MSK[5:0]) data. + * | | |0 = EPWM output signal is non-masked. + * | | |1 = EPWM output signal is masked and output MSKDAT1 data. + * |[2] |MSKEN2 |EPWM Mask Enable Bits + * | | |The EPWM output signal will be masked when this bit is enabled. + * | | |The corresponding EPWM channel 2 will output MSKDAT2 (EPWM_MSK[5:0]) data. + * | | |0 = EPWM output signal is non-masked. + * | | |1 = EPWM output signal is masked and output MSKDAT2 data. + * |[3] |MSKEN3 |EPWM Mask Enable Bits + * | | |The EPWM output signal will be masked when this bit is enabled. + * | | |The corresponding EPWM channel 3 will output MSKDAT3 (EPWM_MSK[5:0]) data. + * | | |0 = EPWM output signal is non-masked. + * | | |1 = EPWM output signal is masked and output MSKDAT3 data. + * |[4] |MSKEN4 |EPWM Mask Enable Bits + * | | |The EPWM output signal will be masked when this bit is enabled. + * | | |The corresponding EPWM channel 4 will output MSKDAT4 (EPWM_MSK[5:0]) data. + * | | |0 = EPWM output signal is non-masked. + * | | |1 = EPWM output signal is masked and output MSKDAT4 data. + * |[5] |MSKEN5 |EPWM Mask Enable Bits + * | | |The EPWM output signal will be masked when this bit is enabled. + * | | |The corresponding EPWM channel 5 will output MSKDAT5 (EPWM_MSK[5:0]) data. + * | | |0 = EPWM output signal is non-masked. + * | | |1 = EPWM output signal is masked and output MSKDAT5 data. + * @var EPWM_T::MSK + * Offset: 0xBC EPWM Mask Data Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |MSKDAT0 |EPWM Mask Data Bit + * | | |This data bit control the state of EPWM_CH0 output pin, if corresponding mask function is enabled. + * | | |0 = Output logic low to EPWM_CH0. + * | | |1 = Output logic high to EPWM_CH0. + * |[1] |MSKDAT1 |EPWM Mask Data Bit + * | | |This data bit control the state of EPWM_CH1 output pin, if corresponding mask function is enabled. + * | | |0 = Output logic low to EPWM_CH1. + * | | |1 = Output logic high to EPWM_CH1. + * |[2] |MSKDAT2 |EPWM Mask Data Bit + * | | |This data bit control the state of EPWM_CH2 output pin, if corresponding mask function is enabled. + * | | |0 = Output logic low to EPWM_CH2. + * | | |1 = Output logic high to EPWM_CH2. + * |[3] |MSKDAT3 |EPWM Mask Data Bit + * | | |This data bit control the state of EPWM_CH3 output pin, if corresponding mask function is enabled. + * | | |0 = Output logic low to EPWM_CH3. + * | | |1 = Output logic high to EPWM_CH3. + * |[4] |MSKDAT4 |EPWM Mask Data Bit + * | | |This data bit control the state of EPWM_CH4 output pin, if corresponding mask function is enabled. + * | | |0 = Output logic low to EPWM_CH4. + * | | |1 = Output logic high to EPWM_CH4. + * |[5] |MSKDAT5 |EPWM Mask Data Bit + * | | |This data bit control the state of EPWM_CH5 output pin, if corresponding mask function is enabled. + * | | |0 = Output logic low to EPWM_CH5. + * | | |1 = Output logic high to EPWM_CH5. + * @var EPWM_T::BNF + * Offset: 0xC0 EPWM Brake Noise Filter Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |BRK0NFEN |EPWM Brake 0 Noise Filter Enable Bit + * | | |0 = Noise filter of EPWM Brake 0 Disabled. + * | | |1 = Noise filter of EPWM Brake 0 Enabled. + * |[3:1] |BRK0NFSEL |Brake 0 Edge Detector Filter Clock Selection + * | | |000 = Filter clock = HCLK. + * | | |001 = Filter clock = HCLK/2. + * | | |010 = Filter clock = HCLK/4. + * | | |011 = Filter clock = HCLK/8. + * | | |100 = Filter clock = HCLK/16. + * | | |101 = Filter clock = HCLK/32. + * | | |110 = Filter clock = HCLK/64. + * | | |111 = Filter clock = HCLK/128. + * |[6:4] |BRK0FCNT |Brake 0 Edge Detector Filter Count + * | | |The register bits control the Brake0 filter counter to count from 0 to BRK0FCNT. + * |[7] |BRK0PINV |Brake 0 Pin Inverse + * | | |0 = The state of pin EPWMx_BRAKE0 is passed to the negative edge detector. + * | | |1 = The inversed state of pin EPWMx_BRAKE0 is passed to the negative edge detector. + * |[8] |BRK1NFEN |EPWM Brake 1 Noise Filter Enable Bit + * | | |0 = Noise filter of EPWM Brake 1 Disabled. + * | | |1 = Noise filter of EPWM Brake 1 Enabled. + * |[11:9] |BRK1NFSEL |Brake 1 Edge Detector Filter Clock Selection + * | | |000 = Filter clock = HCLK. + * | | |001 = Filter clock = HCLK/2. + * | | |010 = Filter clock = HCLK/4. + * | | |011 = Filter clock = HCLK/8. + * | | |100 = Filter clock = HCLK/16. + * | | |101 = Filter clock = HCLK/32. + * | | |110 = Filter clock = HCLK/64. + * | | |111 = Filter clock = HCLK/128. + * |[14:12] |BRK1FCNT |Brake 1 Edge Detector Filter Count + * | | |The register bits control the Brake1 filter counter to count from 0 to BRK1FCNT. + * |[15] |BRK1PINV |Brake 1 Pin Inverse + * | | |0 = The state of pin EPWMx_BRAKE1 is passed to the negative edge detector. + * | | |1 = The inversed state of pin EPWMx_BRAKE1 is passed to the negative edge detector. + * |[16] |BK0SRC |Brake 0 Pin Source Select + * | | |For EPWM0 setting: + * | | |0 = Brake 0 pin source come from EPWM0_BRAKE0. + * | | |1 = Brake 0 pin source come from EPWM1_BRAKE0. + * | | |For EPWM1 setting: + * | | |0 = Brake 0 pin source come from EPWM1_BRAKE0. + * | | |1 = Brake 0 pin source come from EPWM0_BRAKE0. + * |[24] |BK1SRC |Brake 1 Pin Source Select + * | | |For EPWM0 setting: + * | | |0 = Brake 1 pin source come from EPWM0_BRAKE1. + * | | |1 = Brake 1 pin source come from EPWM1_BRAKE1. + * | | |For EPWM1 setting: + * | | |0 = Brake 1 pin source come from EPWM1_BRAKE1. + * | | |1 = Brake 1 pin source come from EPWM0_BRAKE1. + * @var EPWM_T::FAILBRK + * Offset: 0xC4 EPWM System Fail Brake Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |CSSBRKEN |Clock Security System Detection Trigger EPWM Brake Function 0 Enable Bit + * | | |0 = Brake Function triggered by CSS detection Disabled. + * | | |1 = Brake Function triggered by CSS detection Enabled. + * |[1] |BODBRKEN |Brown-out Detection Trigger EPWM Brake Function 0 Enable Bit + * | | |0 = Brake Function triggered by BOD Disabled. + * | | |1 = Brake Function triggered by BOD Enabled. + * |[2] |RAMBRKEN |SRAM Parity Error Detection Trigger EPWM Brake Function 0 Enable Bit + * | | |0 = Brake Function triggered by SRAM parity error detection Disabled. + * | | |1 = Brake Function triggered by SRAM parity error detection Enabled. + * |[3] |CORBRKEN |Core Lockup Detection Trigger EPWM Brake Function 0 Enable Bit + * | | |0 = Brake Function triggered by Core lockup detection Disabled. + * | | |1 = Brake Function triggered by Core lockup detection Enabled. + * @var EPWM_T::BRKCTL[3] + * Offset: 0xC8 EPWM Brake Edge Detect Control Register 0/1,2/3,4/5 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |CPO0EBEN |Enable ACMP0_O Digital Output As Edge-detect Brake Source (Write Protect) + * | | |0 = ACMP0_O as edge-detect brake source Disabled. + * | | |1 = ACMP0_O as edge-detect brake source Enabled. + * | | |Note: This register is write protected. Refer to SYS_REGLCTL register. + * |[1] |CPO1EBEN |Enable ACMP1_O Digital Output As Edge-detect Brake Source (Write Protect) + * | | |0 = ACMP1_O as edge-detect brake source Disabled. + * | | |1 = ACMP1_O as edge-detect brake source Enabled. + * | | |Note: This register is write protected. Refer to SYS_REGLCTL register. + * |[4] |BRKP0EEN |Enable EPWMx_BRAKE0 Pin As Edge-detect Brake Source (Write Protect) + * | | |0 = EPWMx_BRAKE0 pin as edge-detect brake source Disabled. + * | | |1 = EPWMx_BRAKE0 pin as edge-detect brake source Enabled. + * | | |Note: This register is write protected. Refer to SYS_REGLCTL register. + * |[5] |BRKP1EEN |Enable EPWMx_BRAKE1 Pin As Edge-detect Brake Source (Write Protect) + * | | |0 = EPWMx_BRAKE1 pin as edge-detect brake source Disabled. + * | | |1 = EPWMx_BRAKE1 pin as edge-detect brake source Enabled. + * | | |Note: This register is write protected. Refer to SYS_REGLCTL register. + * |[7] |SYSEBEN |Enable System Fail As Edge-detect Brake Source (Write Protect) + * | | |0 = System Fail condition as edge-detect brake source Disabled. + * | | |1 = System Fail condition as edge-detect brake source Enabled. + * | | |Note: This register is write protected. Refer to SYS_REGLCTL register. + * |[8] |CPO0LBEN |Enable ACMP0_O Digital Output As Level-detect Brake Source (Write Protect) + * | | |0 = ACMP0_O as level-detect brake source Disabled. + * | | |1 = ACMP0_O as level-detect brake source Enabled. + * | | |Note: This register is write protected. Refer to SYS_REGLCTL register. + * |[9] |CPO1LBEN |Enable ACMP1_O Digital Output As Level-detect Brake Source (Write Protect) + * | | |0 = ACMP1_O as level-detect brake source Disabled. + * | | |1 = ACMP1_O as level-detect brake source Enabled. + * | | |Note: This register is write protected. Refer to SYS_REGLCTL register. + * |[12] |BRKP0LEN |Enable BKP0 Pin As Level-detect Brake Source (Write Protect) + * | | |0 = EPWMx_BRAKE0 pin as level-detect brake source Disabled. + * | | |1 = EPWMx_BRAKE0 pin as level-detect brake source Enabled. + * | | |Note: This register is write protected. Refer to SYS_REGLCTL register. + * |[13] |BRKP1LEN |Enable BKP1 Pin As Level-detect Brake Source (Write Protect) + * | | |0 = EPWMx_BRAKE1 pin as level-detect brake source Disabled. + * | | |1 = EPWMx_BRAKE1 pin as level-detect brake source Enabled. + * | | |Note: This register is write protected. Refer to SYS_REGLCTL register. + * |[15] |SYSLBEN |Enable System Fail As Level-detect Brake Source (Write Protect) + * | | |0 = System Fail condition as level-detect brake source Disabled. + * | | |1 = System Fail condition as level-detect brake source Enabled. + * | | |Note: This register is write protected. Refer to SYS_REGLCTL register. + * |[17:16] |BRKAEVEN |EPWM Brake Action Select for Even Channel (Write Protect) + * | | |00 = EPWMx brake event will not affect even channels output. + * | | |01 = EPWM even channel output tri-state when EPWMx brake event happened. + * | | |10 = EPWM even channel output low level when EPWMx brake event happened. + * | | |11 = EPWM even channel output high level when EPWMx brake event happened. + * | | |Note: This register is write protected. Refer to SYS_REGLCTL register. + * |[19:18] |BRKAODD |EPWM Brake Action Select for Odd Channel (Write Protect) + * | | |00 = EPWMx brake event will not affect odd channels output. + * | | |01 = EPWM odd channel output tri-state when EPWMx brake event happened. + * | | |10 = EPWM odd channel output low level when EPWMx brake event happened. + * | | |11 = EPWM odd channel output high level when EPWMx brake event happened. + * | | |Note: This register is write protected. Refer to SYS_REGLCTL register. + * |[20] |EADCEBEN |Enable EADC Result Monitor (EADCRM) As Edge-detect Brake Source (Write Protect) + * | | |0 = EADCRM as edge-detect brake source Disabled. + * | | |1 = EADCRM as edge-detect brake source Enabled. + * | | |Note: This register is write protected. Refer to SYS_REGLCTL register. + * |[28] |EADCLBEN |Enable EADC Result Monitor (EADCRM) As Level-detect Brake Source (Write Protect) + * | | |0 = EADCRM as level-detect brake source Disabled. + * | | |1 = EADCRM as level-detect brake source Enabled. + * | | |Note: This register is write protected. Refer to SYS_REGLCTL register. + * @var EPWM_T::POLCTL + * Offset: 0xD4 EPWM Pin Polar Inverse Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |PINV0 |EPWM_CH0 PIN Polar Inverse Control + * | | |The register controls polarity state of EPWM_CH0 output. + * | | |0 = EPWM_CH0 output polar inverse Disabled. + * | | |1 = EPWM_CH0 output polar inverse Enabled. + * |[1] |PINV1 |EPWM_CH1 PIN Polar Inverse Control + * | | |The register controls polarity state of EPWM_CH1 output. + * | | |0 = EPWM_CH1 output polar inverse Disabled. + * | | |1 = EPWM_CH1 output polar inverse Enabled. + * |[2] |PINV2 |EPWM_CH2 PIN Polar Inverse Control + * | | |The register controls polarity state of EPWM_CH2 output. + * | | |0 = EPWM_CH2 output polar inverse Disabled. + * | | |1 = EPWM_CH2 output polar inverse Enabled. + * |[3] |PINV3 |EPWM_CH3 PIN Polar Inverse Control + * | | |The register controls polarity state of EPWM_CH3 output. + * | | |0 = EPWM_CH3 output polar inverse Disabled. + * | | |1 = EPWM_CH3 output polar inverse Enabled. + * |[4] |PINV4 |EPWM_CH4 PIN Polar Inverse Control + * | | |The register controls polarity state of EPWM_CH4 output. + * | | |0 = EPWM_CH4 output polar inverse Disabled. + * | | |1 = EPWM_CH4 output polar inverse Enabled. + * |[5] |PINV5 |EPWM_CH5 PIN Polar Inverse Control + * | | |The register controls polarity state of EPWM_CH5 output. + * | | |0 = EPWM_CH5 output polar inverse Disabled. + * | | |1 = EPWM_CH5 output polar inverse Enabled. + * @var EPWM_T::POEN + * Offset: 0xD8 EPWM Output Enable Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |POEN0 |EPWM_CH0 Pin Output Enable Bits + * | | |0 = EPWM_CH0 pin at tri-state. + * | | |1 = EPWM_CH0 pin in output mode. + * |[1] |POEN1 |EPWM_CH1 Pin Output Enable Bits + * | | |0 = EPWM_CH1 pin at tri-state. + * | | |1 = EPWM_CH1 pin in output mode. + * |[2] |POEN2 |EPWM_CH2 Pin Output Enable Bits + * | | |0 = EPWM_CH2 pin at tri-state. + * | | |1 = EPWM_CH2 pin in output mode. + * |[3] |POEN3 |EPWM_CH3 Pin Output Enable Bits + * | | |0 = EPWM_CH3 pin at tri-state. + * | | |1 = EPWM_CH3 pin in output mode. + * |[4] |POEN4 |EPWM_CH4 Pin Output Enable Bits + * | | |0 = EPWM_CH4 pin at tri-state. + * | | |1 = EPWM_CH4 pin in output mode. + * |[5] |POEN5 |EPWM_CH5 Pin Output Enable Bits + * | | |0 = EPWM_CH5 pin at tri-state. + * | | |1 = EPWM_CH5 pin in output mode. + * @var EPWM_T::SWBRK + * Offset: 0xDC EPWM Software Brake Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |BRKETRG0 |EPWM Edge Brake Software Trigger (Write Only) (Write Protect) + * | | |Write 1 to this bit will trigger edge brake, and set BRKEIF0 to 1 in EPWM_INTSTS1 register. + * | | |Note: This register is write protected. Refer to SYS_REGLCTL register. + * |[1] |BRKETRG2 |EPWM Edge Brake Software Trigger (Write Only) (Write Protect) + * | | |Write 1 to this bit will trigger edge brake, and set BRKEIF2 to 1 in EPWM_INTSTS1 register. + * | | |Note: This register is write protected. Refer to SYS_REGLCTL register. + * |[2] |BRKETRG4 |EPWM Edge Brake Software Trigger (Write Only) (Write Protect) + * | | |Write 1 to this bit will trigger edge brake, and set BRKEIF4 to 1 in EPWM_INTSTS1 register. + * | | |Note: This register is write protected. Refer to SYS_REGLCTL register. + * |[8] |BRKLTRG0 |EPWM Level Brake Software Trigger (Write Only) (Write Protect) + * | | |Write 1 to this bit will trigger level brake, and set BRKLIF0 to 1 in EPWM_INTSTS1 register. + * | | |Note: This register is write protected. Refer to SYS_REGLCTL register. + * |[9] |BRKLTRG2 |EPWM Level Brake Software Trigger (Write Only) (Write Protect) + * | | |Write 1 to this bit will trigger level brake, and set BRKLIF2 to 1 in EPWM_INTSTS1 register. + * | | |Note: This register is write protected. Refer to SYS_REGLCTL register. + * |[10] |BRKLTRG4 |EPWM Level Brake Software Trigger (Write Only) (Write Protect) + * | | |Write 1 to this bit will trigger level brake, and set BRKLIF4 to 1 in EPWM_INTSTS1 register. + * | | |Note: This register is write protected. Refer to SYS_REGLCTL register. + * @var EPWM_T::INTEN0 + * Offset: 0xE0 EPWM Interrupt Enable Register 0 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |ZIEN0 |EPWM Zero Point Interrupt Enable Bits + * | | |0 = Zero point interrupt Disabled. + * | | |1 = Zero point interrupt Enabled. + * | | |Note: Odd channels will read always 0 at complementary mode. + * |[1] |ZIEN1 |EPWM Zero Point Interrupt Enable Bits + * | | |0 = Zero point interrupt Disabled. + * | | |1 = Zero point interrupt Enabled. + * | | |Note: Odd channels will read always 0 at complementary mode. + * |[2] |ZIEN2 |EPWM Zero Point Interrupt Enable Bits + * | | |0 = Zero point interrupt Disabled. + * | | |1 = Zero point interrupt Enabled. + * | | |Note: Odd channels will read always 0 at complementary mode. + * |[3] |ZIEN3 |EPWM Zero Point Interrupt Enable Bits + * | | |0 = Zero point interrupt Disabled. + * | | |1 = Zero point interrupt Enabled. + * | | |Note: Odd channels will read always 0 at complementary mode. + * |[4] |ZIEN4 |EPWM Zero Point Interrupt Enable Bits + * | | |0 = Zero point interrupt Disabled. + * | | |1 = Zero point interrupt Enabled. + * | | |Note: Odd channels will read always 0 at complementary mode. + * |[5] |ZIEN5 |EPWM Zero Point Interrupt Enable Bits + * | | |0 = Zero point interrupt Disabled. + * | | |1 = Zero point interrupt Enabled. + * | | |Note: Odd channels will read always 0 at complementary mode. + * |[8] |PIEN0 |EPWM Period Point Interrupt Enable Bits + * | | |0 = Period point interrupt Disabled. + * | | |1 = Period point interrupt Enabled. + * | | |Note1: When up-down counter type period point means center point. + * | | |Note2: Odd channels will read always 0 at complementary mode. + * |[9] |PIEN1 |EPWM Period Point Interrupt Enable Bits + * | | |0 = Period point interrupt Disabled. + * | | |1 = Period point interrupt Enabled. + * | | |Note1: When up-down counter type period point means center point. + * | | |Note2: Odd channels will read always 0 at complementary mode. + * |[10] |PIEN2 |EPWM Period Point Interrupt Enable Bits + * | | |0 = Period point interrupt Disabled. + * | | |1 = Period point interrupt Enabled. + * | | |Note1: When up-down counter type period point means center point. + * | | |Note2: Odd channels will read always 0 at complementary mode. + * |[11] |PIEN3 |EPWM Period Point Interrupt Enable Bits + * | | |0 = Period point interrupt Disabled. + * | | |1 = Period point interrupt Enabled. + * | | |Note1: When up-down counter type period point means center point. + * | | |Note2: Odd channels will read always 0 at complementary mode. + * |[12] |PIEN4 |EPWM Period Point Interrupt Enable Bits + * | | |0 = Period point interrupt Disabled. + * | | |1 = Period point interrupt Enabled. + * | | |Note1: When up-down counter type period point means center point. + * | | |Note2: Odd channels will read always 0 at complementary mode. + * |[13] |PIEN5 |EPWM Period Point Interrupt Enable Bits + * | | |0 = Period point interrupt Disabled. + * | | |1 = Period point interrupt Enabled. + * | | |Note1: When up-down counter type period point means center point. + * | | |Note2: Odd channels will read always 0 at complementary mode. + * |[16] |CMPUIEN0 |EPWM Compare Up Count Interrupt Enable Bits + * | | |0 = Compare up count interrupt Disabled. + * | | |1 = Compare up count interrupt Enabled. + * | | |Note: In complementary mode, CMPUIEN1, 3, 5 use as another CMPUIEN for channel 0, 2, 4. + * |[17] |CMPUIEN1 |EPWM Compare Up Count Interrupt Enable Bits + * | | |0 = Compare up count interrupt Disabled. + * | | |1 = Compare up count interrupt Enabled. + * | | |Note: In complementary mode, CMPUIEN1, 3, 5 use as another CMPUIEN for channel 0, 2, 4. + * |[18] |CMPUIEN2 |EPWM Compare Up Count Interrupt Enable Bits + * | | |0 = Compare up count interrupt Disabled. + * | | |1 = Compare up count interrupt Enabled. + * | | |Note: In complementary mode, CMPUIEN1, 3, 5 use as another CMPUIEN for channel 0, 2, 4. + * |[19] |CMPUIEN3 |EPWM Compare Up Count Interrupt Enable Bits + * | | |0 = Compare up count interrupt Disabled. + * | | |1 = Compare up count interrupt Enabled. + * | | |Note: In complementary mode, CMPUIEN1, 3, 5 use as another CMPUIEN for channel 0, 2, 4. + * |[20] |CMPUIEN4 |EPWM Compare Up Count Interrupt Enable Bits + * | | |0 = Compare up count interrupt Disabled. + * | | |1 = Compare up count interrupt Enabled. + * | | |Note: In complementary mode, CMPUIEN1, 3, 5 use as another CMPUIEN for channel 0, 2, 4. + * |[21] |CMPUIEN5 |EPWM Compare Up Count Interrupt Enable Bits + * | | |0 = Compare up count interrupt Disabled. + * | | |1 = Compare up count interrupt Enabled. + * | | |Note: In complementary mode, CMPUIEN1, 3, 5 use as another CMPUIEN for channel 0, 2, 4. + * |[24] |CMPDIEN0 |EPWM Compare Down Count Interrupt Enable Bits + * | | |0 = Compare down count interrupt Disabled. + * | | |1 = Compare down count interrupt Enabled. + * | | |Note: In complementary mode, CMPDIEN1, 3, 5 use as another CMPDIEN for channel 0, 2, 4. + * |[25] |CMPDIEN1 |EPWM Compare Down Count Interrupt Enable Bits + * | | |0 = Compare down count interrupt Disabled. + * | | |1 = Compare down count interrupt Enabled. + * | | |Note: In complementary mode, CMPDIEN1, 3, 5 use as another CMPDIEN for channel 0, 2, 4. + * |[26] |CMPDIEN2 |EPWM Compare Down Count Interrupt Enable Bits + * | | |0 = Compare down count interrupt Disabled. + * | | |1 = Compare down count interrupt Enabled. + * | | |Note: In complementary mode, CMPDIEN1, 3, 5 use as another CMPDIEN for channel 0, 2, 4. + * |[27] |CMPDIEN3 |EPWM Compare Down Count Interrupt Enable Bits + * | | |0 = Compare down count interrupt Disabled. + * | | |1 = Compare down count interrupt Enabled. + * | | |Note: In complementary mode, CMPDIEN1, 3, 5 use as another CMPDIEN for channel 0, 2, 4. + * |[28] |CMPDIEN4 |EPWM Compare Down Count Interrupt Enable Bits + * | | |0 = Compare down count interrupt Disabled. + * | | |1 = Compare down count interrupt Enabled. + * | | |Note: In complementary mode, CMPDIEN1, 3, 5 use as another CMPDIEN for channel 0, 2, 4. + * |[29] |CMPDIEN5 |EPWM Compare Down Count Interrupt Enable Bits + * | | |0 = Compare down count interrupt Disabled. + * | | |1 = Compare down count interrupt Enabled. + * | | |Note: In complementary mode, CMPDIEN1, 3, 5 use as another CMPDIEN for channel 0, 2, 4. + * @var EPWM_T::INTEN1 + * Offset: 0xE4 EPWM Interrupt Enable Register 1 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |BRKEIEN0_1|EPWM Edge-detect Brake Interrupt Enable for Channel0/1 (Write Protect) + * | | |0 = Edge-detect Brake interrupt for channel0/1 Disabled. + * | | |1 = Edge-detect Brake interrupt for channel0/1 Enabled. + * | | |Note: This register is write protected. Refer to SYS_REGLCTL register. + * |[1] |BRKEIEN2_3|EPWM Edge-detect Brake Interrupt Enable for Channel2/3 (Write Protect) + * | | |0 = Edge-detect Brake interrupt for channel2/3 Disabled. + * | | |1 = Edge-detect Brake interrupt for channel2/3 Enabled. + * | | |Note: This register is write protected. Refer to SYS_REGLCTL register. + * |[2] |BRKEIEN4_5|EPWM Edge-detect Brake Interrupt Enable for Channel4/5 (Write Protect) + * | | |0 = Edge-detect Brake interrupt for channel4/5 Disabled. + * | | |1 = Edge-detect Brake interrupt for channel4/5 Enabled. + * | | |Note: This register is write protected. Refer to SYS_REGLCTL register. + * |[8] |BRKLIEN0_1|EPWM Level-detect Brake Interrupt Enable for Channel0/1 (Write Protect) + * | | |0 = Level-detect Brake interrupt for channel0/1 Disabled. + * | | |1 = Level-detect Brake interrupt for channel0/1 Enabled. + * | | |Note: This register is write protected. Refer to SYS_REGLCTL register. + * |[9] |BRKLIEN2_3|EPWM Level-detect Brake Interrupt Enable for Channel2/3 (Write Protect) + * | | |0 = Level-detect Brake interrupt for channel2/3 Disabled. + * | | |1 = Level-detect Brake interrupt for channel2/3 Enabled. + * | | |Note: This register is write protected. Refer to SYS_REGLCTL register. + * |[10] |BRKLIEN4_5|EPWM Level-detect Brake Interrupt Enable for Channel4/5 (Write Protect) + * | | |0 = Level-detect Brake interrupt for channel4/5 Disabled. + * | | |1 = Level-detect Brake interrupt for channel4/5 Enabled. + * | | |Note: This register is write protected. Refer to SYS_REGLCTL register. + * @var EPWM_T::INTSTS0 + * Offset: 0xE8 EPWM Interrupt Flag Register 0 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |ZIF0 |EPWM Zero Point Interrupt Flag + * | | |This bit is set by hardware when EPWM counter reaches zero, software can write 1 to clear this bit to zero. + * |[1] |ZIF1 |EPWM Zero Point Interrupt Flag + * | | |This bit is set by hardware when EPWM counter reaches zero, software can write 1 to clear this bit to zero. + * |[2] |ZIF2 |EPWM Zero Point Interrupt Flag + * | | |This bit is set by hardware when EPWM counter reaches zero, software can write 1 to clear this bit to zero. + * |[3] |ZIF3 |EPWM Zero Point Interrupt Flag + * | | |This bit is set by hardware when EPWM counter reaches zero, software can write 1 to clear this bit to zero. + * |[4] |ZIF4 |EPWM Zero Point Interrupt Flag + * | | |This bit is set by hardware when EPWM counter reaches zero, software can write 1 to clear this bit to zero. + * |[5] |ZIF5 |EPWM Zero Point Interrupt Flag + * | | |This bit is set by hardware when EPWM counter reaches zero, software can write 1 to clear this bit to zero. + * |[8] |PIF0 |EPWM Period Point Interrupt Flag + * | | |This bit is set by hardware when EPWM counter reaches EPWM_PERIOD0, software can write 1 to clear this bit to zero + * |[9] |PIF1 |EPWM Period Point Interrupt Flag + * | | |This bit is set by hardware when EPWM counter reaches EPWM_PERIOD1, software can write 1 to clear this bit to zero + * |[10] |PIF2 |EPWM Period Point Interrupt Flag + * | | |This bit is set by hardware when EPWM counter reaches EPWM_PERIOD2, software can write 1 to clear this bit to zero + * |[11] |PIF3 |EPWM Period Point Interrupt Flag + * | | |This bit is set by hardware when EPWM counter reaches EPWM_PERIOD4, software can write 1 to clear this bit to zero + * |[12] |PIF4 |EPWM Period Point Interrupt Flag + * | | |This bit is set by hardware when EPWM counter reaches EPWM_PERIOD5, software can write 1 to clear this bit to zero + * |[13] |PIF5 |EPWM Period Point Interrupt Flag + * | | |This bit is set by hardware when EPWM counter reaches EPWM_PERIODn, software can write 1 to clear this bit to zero. + * |[16] |CMPUIF0 |EPWM Compare Up Count Interrupt Flag + * | | |Flag is set by hardware when EPWM counter up count and reaches EPWM_CMPDAT0, software can clear this bit by writing 1 to it. + * | | |Note1: If CMPDAT equal to PERIOD, this flag is not working in up counter type selection. + * | | |Note2: In complementary mode, CMPUIF1, 3, 5 use as another CMPUIF for channel 0, 2, 4. + * |[17] |CMPUIF1 |EPWM Compare Up Count Interrupt Flag + * | | |Flag is set by hardware when EPWM counter up count and reaches EPWM_CMPDAT1, software can clear this bit by writing 1 to it. + * | | |Note1: If CMPDAT equal to PERIOD, this flag is not working in up counter type selection. + * | | |Note2: In complementary mode, CMPUIF1, 3, 5 use as another CMPUIF for channel 0, 2, 4. + * |[18] |CMPUIF2 |EPWM Compare Up Count Interrupt Flag + * | | |Flag is set by hardware when EPWM counter up count and reaches EPWM_CMPDAT2, software can clear this bit by writing 1 to it. + * | | |Note1: If CMPDAT equal to PERIOD, this flag is not working in up counter type selection. + * | | |Note2: In complementary mode, CMPUIF1, 3, 5 use as another CMPUIF for channel 0, 2, 4. + * |[19] |CMPUIF3 |EPWM Compare Up Count Interrupt Flag + * | | |Flag is set by hardware when EPWM counter up count and reaches EPWM_CMPDAT3, software can clear this bit by writing 1 to it. + * | | |Note1: If CMPDAT equal to PERIOD, this flag is not working in up counter type selection. + * | | |Note2: In complementary mode, CMPUIF1, 3, 5 use as another CMPUIF for channel 0, 2, 4. + * |[20] |CMPUIF4 |EPWM Compare Up Count Interrupt Flag + * | | |Flag is set by hardware when EPWM counter up count and reaches EPWM_CMPDAT4, software can clear this bit by writing 1 to it. + * | | |Note1: If CMPDAT equal to PERIOD, this flag is not working in up counter type selection. + * | | |Note2: In complementary mode, CMPUIF1, 3, 5 use as another CMPUIF for channel 0, 2, 4. + * |[21] |CMPUIF5 |EPWM Compare Up Count Interrupt Flag + * | | |Flag is set by hardware when EPWM counter up count and reaches EPWM_CMPDAT5, software can clear this bit by writing 1 to it. + * | | |Note1: If CMPDAT equal to PERIOD, this flag is not working in up counter type selection. + * | | |Note2: In complementary mode, CMPUIF1, 3, 5 use as another CMPUIF for channel 0, 2, 4. + * |[24] |CMPDIF0 |EPWM Compare Down Count Interrupt Flag + * | | |Flag is set by hardware when EPWM counter down count and reaches EPWM_CMPDAT0, software can clear this bit by writing 1 to it. + * | | |Note1: If CMPDAT equal to PERIOD, this flag is not working in down counter type selection. + * | | |Note2: In complementary mode, CMPDIF1, 3, 5 use as another CMPDIF for channel 0, 2, 4. + * |[25] |CMPDIF1 |EPWM Compare Down Count Interrupt Flag + * | | |Flag is set by hardware when EPWM counter down count and reaches EPWM_CMPDAT1, software can clear this bit by writing 1 to it. + * | | |Note1: If CMPDAT equal to PERIOD, this flag is not working in down counter type selection. + * | | |Note2: In complementary mode, CMPDIF1, 3, 5 use as another CMPDIF for channel 0, 2, 4. + * |[26] |CMPDIF2 |EPWM Compare Down Count Interrupt Flag + * | | |Flag is set by hardware when EPWM counter down count and reaches EPWM_CMPDAT2, software can clear this bit by writing 1 to it. + * | | |Note1: If CMPDAT equal to PERIOD, this flag is not working in down counter type selection. + * | | |Note2: In complementary mode, CMPDIF1, 3, 5 use as another CMPDIF for channel 0, 2, 4. + * |[27] |CMPDIF3 |EPWM Compare Down Count Interrupt Flag + * | | |Flag is set by hardware when EPWM counter down count and reaches EPWM_CMPDAT3, software can clear this bit by writing 1 to it. + * | | |Note1: If CMPDAT equal to PERIOD, this flag is not working in down counter type selection. + * | | |Note2: In complementary mode, CMPDIF1, 3, 5 use as another CMPDIF for channel 0, 2, 4. + * |[28] |CMPDIF4 |EPWM Compare Down Count Interrupt Flag + * | | |Flag is set by hardware when EPWM counter down count and reaches EPWM_CMPDAT4, software can clear this bit by writing 1 to it. + * | | |Note1: If CMPDAT equal to PERIOD, this flag is not working in down counter type selection. + * | | |Note2: In complementary mode, CMPDIF1, 3, 5 use as another CMPDIF for channel 0, 2, 4. + * |[29] |CMPDIF5 |EPWM Compare Down Count Interrupt Flag + * | | |Flag is set by hardware when EPWM counter down count and reaches EPWM_CMPDAT5, software can clear this bit by writing 1 to it. + * | | |Note1: If CMPDAT equal to PERIOD, this flag is not working in down counter type selection. + * | | |Note2: In complementary mode, CMPDIF1, 3, 5 use as another CMPDIF for channel 0, 2, 4. + * @var EPWM_T::INTSTS1 + * Offset: 0xEC EPWM Interrupt Flag Register 1 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |BRKEIF0 |EPWM Channel0 Edge-detect Brake Interrupt Flag (Write Protect) + * | | |0 = EPWM channel0 edge-detect brake event do not happened. + * | | |1 = When EPWM channel0 edge-detect brake event happened, this bit is set to 1, writing 1 to clear. + * | | |Note: This register is write protected. Refer to SYS_REGLCTL register. + * |[1] |BRKEIF1 |EPWM Channel1 Edge-detect Brake Interrupt Flag (Write Protect) + * | | |0 = EPWM channel1 edge-detect brake event do not happened. + * | | |1 = When EPWM channel1 edge-detect brake event happened, this bit is set to 1, writing 1 to clear. + * | | |Note: This register is write protected. Refer to SYS_REGLCTL register. + * |[2] |BRKEIF2 |EPWM Channel2 Edge-detect Brake Interrupt Flag (Write Protect) + * | | |0 = EPWM channel2 edge-detect brake event do not happened. + * | | |1 = When EPWM channel2 edge-detect brake event happened, this bit is set to 1, writing 1 to clear. + * | | |Note: This register is write protected. Refer to SYS_REGLCTL register. + * |[3] |BRKEIF3 |EPWM Channel3 Edge-detect Brake Interrupt Flag (Write Protect) + * | | |0 = EPWM channel3 edge-detect brake event do not happened. + * | | |1 = When EPWM channel3 edge-detect brake event happened, this bit is set to 1, writing 1 to clear. + * | | |Note: This register is write protected. Refer to SYS_REGLCTL register. + * |[4] |BRKEIF4 |EPWM Channel4 Edge-detect Brake Interrupt Flag (Write Protect) + * | | |0 = EPWM channel4 edge-detect brake event do not happened. + * | | |1 = When EPWM channel4 edge-detect brake event happened, this bit is set to 1, writing 1 to clear. + * | | |Note: This register is write protected. Refer to SYS_REGLCTL register. + * |[5] |BRKEIF5 |EPWM Channel5 Edge-detect Brake Interrupt Flag (Write Protect) + * | | |0 = EPWM channel5 edge-detect brake event do not happened. + * | | |1 = When EPWM channel5 edge-detect brake event happened, this bit is set to 1, writing 1 to clear. + * | | |Note: This register is write protected. Refer to SYS_REGLCTL register. + * |[8] |BRKLIF0 |EPWM Channel0 Level-detect Brake Interrupt Flag (Write Protect) + * | | |0 = EPWM channel0 level-detect brake event do not happened. + * | | |1 = When EPWM channel0 level-detect brake event happened, this bit is set to 1, writing 1 to clear. + * | | |Note: This register is write protected. Refer to SYS_REGLCTL register. + * |[9] |BRKLIF1 |EPWM Channel1 Level-detect Brake Interrupt Flag (Write Protect) + * | | |0 = EPWM channel1 level-detect brake event do not happened. + * | | |1 = When EPWM channel1 level-detect brake event happened, this bit is set to 1, writing 1 to clear. + * | | |Note: This register is write protected. Refer to SYS_REGLCTL register. + * |[10] |BRKLIF2 |EPWM Channel2 Level-detect Brake Interrupt Flag (Write Protect) + * | | |0 = EPWM channel2 level-detect brake event do not happened. + * | | |1 = When EPWM channel2 level-detect brake event happened, this bit is set to 1, writing 1 to clear. + * | | |Note: This register is write protected. Refer to SYS_REGLCTL register. + * |[11] |BRKLIF3 |EPWM Channel3 Level-detect Brake Interrupt Flag (Write Protect) + * | | |0 = EPWM channel3 level-detect brake event do not happened. + * | | |1 = When EPWM channel3 level-detect brake event happened, this bit is set to 1, writing 1 to clear. + * | | |Note: This register is write protected. Refer to SYS_REGLCTL register. + * |[12] |BRKLIF4 |EPWM Channel4 Level-detect Brake Interrupt Flag (Write Protect) + * | | |0 = EPWM channel4 level-detect brake event do not happened. + * | | |1 = When EPWM channel4 level-detect brake event happened, this bit is set to 1, writing 1 to clear. + * | | |Note: This register is write protected. Refer to SYS_REGLCTL register. + * |[13] |BRKLIF5 |EPWM Channel5 Level-detect Brake Interrupt Flag (Write Protect) + * | | |0 = EPWM channel5 level-detect brake event do not happened. + * | | |1 = When EPWM channel5 level-detect brake event happened, this bit is set to 1, writing 1 to clear. + * | | |Note: This register is write protected. Refer to SYS_REGLCTL register. + * |[16] |BRKESTS0 |EPWM Channel0 Edge-detect Brake Status (Read Only) + * | | |0 = EPWM channel0 edge-detect brake state is released. + * | | |1 = When EPWM channel0 edge-detect brake detects a falling edge of any enabled brake source; this flag will be set to indicate the EPWM channel0 at brake state, writing 1 to clear. + * |[17] |BRKESTS1 |EPWM Channel1 Edge-detect Brake Status (Read Only) + * | | |0 = EPWM channel1 edge-detect brake state is released. + * | | |1 = When EPWM channel1 edge-detect brake detects a falling edge of any enabled brake source; this flag will be set to indicate the EPWM channel1 at brake state, writing 1 to clear. + * |[18] |BRKESTS2 |EPWM Channel2 Edge-detect Brake Status (Read Only) + * | | |0 = EPWM channel2 edge-detect brake state is released. + * | | |1 = When EPWM channel2 edge-detect brake detects a falling edge of any enabled brake source; this flag will be set to indicate the EPWM channel2 at brake state, writing 1 to clear. + * |[19] |BRKESTS3 |EPWM Channel3 Edge-detect Brake Status (Read Only) + * | | |0 = EPWM channel3 edge-detect brake state is released. + * | | |1 = When EPWM channel3 edge-detect brake detects a falling edge of any enabled brake source; this flag will be set to indicate the EPWM channel3 at brake state, writing 1 to clear. + * |[20] |BRKESTS4 |EPWM Channel4 Edge-detect Brake Status (Read Only) + * | | |0 = EPWM channel4 edge-detect brake state is released. + * | | |1 = When EPWM channel4 edge-detect brake detects a falling edge of any enabled brake source; this flag will be set to indicate the EPWM channel4 at brake state, writing 1 to clear. + * |[21] |BRKESTS5 |EPWM Channel5 Edge-detect Brake Status (Read Only) + * | | |0 = EPWM channel5 edge-detect brake state is released. + * | | |1 = When EPWM channel5 edge-detect brake detects a falling edge of any enabled brake source; this flag will be set to indicate the EPWM channel5 at brake state, writing 1 to clear. + * |[24] |BRKLSTS0 |EPWM Channel0 Level-detect Brake Status (Read Only) + * | | |0 = EPWM channel0 level-detect brake state is released. + * | | |1 = When EPWM channel0 level-detect brake detects a falling edge of any enabled brake source; this flag will be set to indicate the EPWM channel0 at brake state. + * | | |Note: This bit is read only and auto cleared by hardware + * | | |When enabled brake source return to high level, EPWM will release brake state until current EPWM period finished + * | | |The EPWM waveform will start output from next full EPWM period. + * |[25] |BRKLSTS1 |EPWM Channel1 Level-detect Brake Status (Read Only) + * | | |0 = EPWM channel1 level-detect brake state is released. + * | | |1 = When EPWM channel1 level-detect brake detects a falling edge of any enabled brake source; this flag will be set to indicate the EPWM channel1 at brake state. + * | | |Note: This bit is read only and auto cleared by hardware + * | | |When enabled brake source return to high level, EPWM will release brake state until current EPWM period finished + * | | |The EPWM waveform will start output from next full EPWM period. + * |[26] |BRKLSTS2 |EPWM Channel2 Level-detect Brake Status (Read Only) + * | | |0 = EPWM channel2 level-detect brake state is released. + * | | |1 = When EPWM channel2 level-detect brake detects a falling edge of any enabled brake source; this flag will be set to indicate the EPWM channel2 at brake state. + * | | |Note: This bit is read only and auto cleared by hardware + * | | |When enabled brake source return to high level, EPWM will release brake state until current EPWM period finished + * | | |The EPWM waveform will start output from next full EPWM period. + * |[27] |BRKLSTS3 |EPWM Channel3 Level-detect Brake Status (Read Only) + * | | |0 = EPWM channel3 level-detect brake state is released. + * | | |1 = When EPWM channel3 level-detect brake detects a falling edge of any enabled brake source; this flag will be set to indicate the EPWM channel3 at brake state. + * | | |Note: This bit is read only and auto cleared by hardware + * | | |When enabled brake source return to high level, EPWM will release brake state until current EPWM period finished + * | | |The EPWM waveform will start output from next full EPWM period. + * |[28] |BRKLSTS4 |EPWM Channel4 Level-detect Brake Status (Read Only) + * | | |0 = EPWM channel4 level-detect brake state is released. + * | | |1 = When EPWM channel4 level-detect brake detects a falling edge of any enabled brake source; this flag will be set to indicate the EPWM channel4 at brake state. + * | | |Note: This bit is read only and auto cleared by hardware + * | | |When enabled brake source return to high level, EPWM will release brake state until current EPWM period finished + * | | |The EPWM waveform will start output from next full EPWM period. + * |[29] |BRKLSTS5 |EPWM Channel5 Level-detect Brake Status (Read Only) + * | | |0 = EPWM channel5 level-detect brake state is released. + * | | |1 = When EPWM channel5 level-detect brake detects a falling edge of any enabled brake source; this flag will be set to indicate the EPWM channel5 at brake state. + * | | |Note: This bit is read only and auto cleared by hardware + * | | |When enabled brake source return to high level, EPWM will release brake state until current EPWM period finished + * | | |The EPWM waveform will start output from next full EPWM period. + * @var EPWM_T::DACTRGEN + * Offset: 0xF4 EPWM Trigger DAC Enable Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |ZTE0 |EPWM Zero Point Trigger DAC Enable Bits + * | | |EPWM can trigger EADC/DAC/DMA to start action when EPWM counter down count to zero if this bit is set to1. + * | | |0 = EPWM period point trigger DAC function Disabled. + * | | |1 = EPWM period point trigger DAC function Enabled. + * |[1] |ZTE1 |EPWM Zero Point Trigger DAC Enable Bits + * | | |EPWM can trigger EADC/DAC/DMA to start action when EPWM counter down count to zero if this bit is set to1. + * | | |0 = EPWM period point trigger DAC function Disabled. + * | | |1 = EPWM period point trigger DAC function Enabled. + * |[2] |ZTE2 |EPWM Zero Point Trigger DAC Enable Bits + * | | |EPWM can trigger EADC/DAC/DMA to start action when EPWM counter down count to zero if this bit is set to1. + * | | |0 = EPWM period point trigger DAC function Disabled. + * | | |1 = EPWM period point trigger DAC function Enabled. + * |[3] |ZTE3 |EPWM Zero Point Trigger DAC Enable Bits + * | | |EPWM can trigger EADC/DAC/DMA to start action when EPWM counter down count to zero if this bit is set to1. + * | | |0 = EPWM period point trigger DAC function Disabled. + * | | |1 = EPWM period point trigger DAC function Enabled. + * |[4] |ZTE4 |EPWM Zero Point Trigger DAC Enable Bits + * | | |EPWM can trigger EADC/DAC/DMA to start action when EPWM counter down count to zero if this bit is set to1. + * | | |0 = EPWM period point trigger DAC function Disabled. + * | | |1 = EPWM period point trigger DAC function Enabled. + * |[5] |ZTE5 |EPWM Zero Point Trigger DAC Enable Bits + * | | |EPWM can trigger EADC/DAC/DMA to start action when EPWM counter down count to zero if this bit is set to1. + * | | |0 = EPWM period point trigger DAC function Disabled. + * | | |1 = EPWM period point trigger DAC function Enabled. + * |[8] |PTE0 |EPWM Period Point Trigger DAC Enable Bits + * | | |EPWM can trigger DAC to start action when EPWM counter up count to (PERIODn+1) if this bit is set to1. + * | | |0 = EPWM period point trigger DAC function Disabled. + * | | |1 = EPWM period point trigger DAC function Enabled. + * |[9] |PTE1 |EPWM Period Point Trigger DAC Enable Bits + * | | |EPWM can trigger DAC to start action when EPWM counter up count to (PERIODn+1) if this bit is set to1. + * | | |0 = EPWM period point trigger DAC function Disabled. + * | | |1 = EPWM period point trigger DAC function Enabled. + * |[10] |PTE2 |EPWM Period Point Trigger DAC Enable Bits + * | | |EPWM can trigger DAC to start action when EPWM counter up count to (PERIODn+1) if this bit is set to1. + * | | |0 = EPWM period point trigger DAC function Disabled. + * | | |1 = EPWM period point trigger DAC function Enabled. + * |[11] |PTE3 |EPWM Period Point Trigger DAC Enable Bits + * | | |EPWM can trigger DAC to start action when EPWM counter up count to (PERIODn+1) if this bit is set to1. + * | | |0 = EPWM period point trigger DAC function Disabled. + * | | |1 = EPWM period point trigger DAC function Enabled. + * |[12] |PTE4 |EPWM Period Point Trigger DAC Enable Bits + * | | |EPWM can trigger DAC to start action when EPWM counter up count to (PERIODn+1) if this bit is set to1. + * | | |0 = EPWM period point trigger DAC function Disabled. + * | | |1 = EPWM period point trigger DAC function Enabled. + * |[13] |PTE5 |EPWM Period Point Trigger DAC Enable Bits + * | | |EPWM can trigger DAC to start action when EPWM counter up count to (PERIODn+1) if this bit is set to1. + * | | |0 = EPWM period point trigger DAC function Disabled. + * | | |1 = EPWM period point trigger DAC function Enabled. + * |[16] |CUTRGE0 |EPWM Compare Up Count Point Trigger DAC Enable Bits + * | | |EPWM can trigger DAC to start action when EPWM counter up count to CMPDAT if this bit is set to1. + * | | |0 = EPWM Compare Up point trigger DAC function Disabled. + * | | |1 = EPWM Compare Up point trigger DAC function Enabled. + * | | |Note1: This bit should keep at 0 when EPWM counter operating in down counter type. + * | | |Note2: In complementary mode, CUTRGE1, 3, 5 use as another CUTRGE for channel 0, 2, 4. + * |[17] |CUTRGE1 |EPWM Compare Up Count Point Trigger DAC Enable Bits + * | | |EPWM can trigger DAC to start action when EPWM counter up count to CMPDAT if this bit is set to1. + * | | |0 = EPWM Compare Up point trigger DAC function Disabled. + * | | |1 = EPWM Compare Up point trigger DAC function Enabled. + * | | |Note1: This bit should keep at 0 when EPWM counter operating in down counter type. + * | | |Note2: In complementary mode, CUTRGE1, 3, 5 use as another CUTRGE for channel 0, 2, 4. + * |[18] |CUTRGE2 |EPWM Compare Up Count Point Trigger DAC Enable Bits + * | | |EPWM can trigger DAC to start action when EPWM counter up count to CMPDAT if this bit is set to1. + * | | |0 = EPWM Compare Up point trigger DAC function Disabled. + * | | |1 = EPWM Compare Up point trigger DAC function Enabled. + * | | |Note1: This bit should keep at 0 when EPWM counter operating in down counter type. + * | | |Note2: In complementary mode, CUTRGE1, 3, 5 use as another CUTRGE for channel 0, 2, 4. + * |[19] |CUTRGE3 |EPWM Compare Up Count Point Trigger DAC Enable Bits + * | | |EPWM can trigger DAC to start action when EPWM counter up count to CMPDAT if this bit is set to1. + * | | |0 = EPWM Compare Up point trigger DAC function Disabled. + * | | |1 = EPWM Compare Up point trigger DAC function Enabled. + * | | |Note1: This bit should keep at 0 when EPWM counter operating in down counter type. + * | | |Note2: In complementary mode, CUTRGE1, 3, 5 use as another CUTRGE for channel 0, 2, 4. + * |[20] |CUTRGE4 |EPWM Compare Up Count Point Trigger DAC Enable Bits + * | | |EPWM can trigger DAC to start action when EPWM counter up count to CMPDAT if this bit is set to1. + * | | |0 = EPWM Compare Up point trigger DAC function Disabled. + * | | |1 = EPWM Compare Up point trigger DAC function Enabled. + * | | |Note1: This bit should keep at 0 when EPWM counter operating in down counter type. + * | | |Note2: In complementary mode, CUTRGE1, 3, 5 use as another CUTRGE for channel 0, 2, 4. + * |[21] |CUTRGE5 |EPWM Compare Up Count Point Trigger DAC Enable Bits + * | | |EPWM can trigger DAC to start action when EPWM counter up count to CMPDAT if this bit is set to1. + * | | |0 = EPWM Compare Up point trigger DAC function Disabled. + * | | |1 = EPWM Compare Up point trigger DAC function Enabled. + * | | |Note1: This bit should keep at 0 when EPWM counter operating in down counter type. + * | | |Note2: In complementary mode, CUTRGE1, 3, 5 use as another CUTRGE for channel 0, 2, 4. + * |[24] |CDTRGE0 |EPWM Compare Down Count Point Trigger DAC Enable Bits + * | | |EPWM can trigger DAC to start action when EPWM counter down count to CMPDAT if this bit is set to1. + * | | |0 = EPWM Compare Down count point trigger DAC function Disabled. + * | | |1 = EPWM Compare Down count point trigger DAC function Enabled. + * | | |Note1: This bit should keep at 0 when EPWM counter operating in up counter type. + * | | |Note2: In complementary mode, CDTRGE1, 3, 5 use as another CDTRGE for channel 0, 2, 4. + * |[25] |CDTRGE1 |EPWM Compare Down Count Point Trigger DAC Enable Bits + * | | |EPWM can trigger DAC to start action when EPWM counter down count to CMPDAT if this bit is set to1. + * | | |0 = EPWM Compare Down count point trigger DAC function Disabled. + * | | |1 = EPWM Compare Down count point trigger DAC function Enabled. + * | | |Note1: This bit should keep at 0 when EPWM counter operating in up counter type. + * | | |Note2: In complementary mode, CDTRGE1, 3, 5 use as another CDTRGE for channel 0, 2, 4. + * |[26] |CDTRGE2 |EPWM Compare Down Count Point Trigger DAC Enable Bits + * | | |EPWM can trigger DAC to start action when EPWM counter down count to CMPDAT if this bit is set to1. + * | | |0 = EPWM Compare Down count point trigger DAC function Disabled. + * | | |1 = EPWM Compare Down count point trigger DAC function Enabled. + * | | |Note1: This bit should keep at 0 when EPWM counter operating in up counter type. + * | | |Note2: In complementary mode, CDTRGE1, 3, 5 use as another CDTRGE for channel 0, 2, 4. + * |[27] |CDTRGE3 |EPWM Compare Down Count Point Trigger DAC Enable Bits + * | | |EPWM can trigger DAC to start action when EPWM counter down count to CMPDAT if this bit is set to1. + * | | |0 = EPWM Compare Down count point trigger DAC function Disabled. + * | | |1 = EPWM Compare Down count point trigger DAC function Enabled. + * | | |Note1: This bit should keep at 0 when EPWM counter operating in up counter type. + * | | |Note2: In complementary mode, CDTRGE1, 3, 5 use as another CDTRGE for channel 0, 2, 4. + * |[28] |CDTRGE4 |EPWM Compare Down Count Point Trigger DAC Enable Bits + * | | |EPWM can trigger DAC to start action when EPWM counter down count to CMPDAT if this bit is set to1. + * | | |0 = EPWM Compare Down count point trigger DAC function Disabled. + * | | |1 = EPWM Compare Down count point trigger DAC function Enabled. + * | | |Note1: This bit should keep at 0 when EPWM counter operating in up counter type. + * | | |Note2: In complementary mode, CDTRGE1, 3, 5 use as another CDTRGE for channel 0, 2, 4. + * |[29] |CDTRGE5 |EPWM Compare Down Count Point Trigger DAC Enable Bits + * | | |EPWM can trigger DAC to start action when EPWM counter down count to CMPDAT if this bit is set to1. + * | | |0 = EPWM Compare Down count point trigger DAC function Disabled. + * | | |1 = EPWM Compare Down count point trigger DAC function Enabled. + * | | |Note1: This bit should keep at 0 when EPWM counter operating in up counter type. + * | | |Note2: In complementary mode, CDTRGE1, 3, 5 use as another CDTRGE for channel 0, 2, 4. + * @var EPWM_T::EADCTS0 + * Offset: 0xF8 EPWM Trigger EADC Source Select Register 0 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[3:0] |TRGSEL0 |EPWM_CH0 Trigger EADC Source Select + * | | |0000 = EPWM_CH0 zero point. + * | | |0001 = EPWM_CH0 period point. + * | | |0010 = EPWM_CH0 zero or period point. + * | | |0011 = EPWM_CH0 up-count CMPDAT point. + * | | |0100 = EPWM_CH0 down-count CMPDAT point. + * | | |0101 = EPWM_CH1 zero point. + * | | |0110 = EPWM_CH1 period point. + * | | |0111 = EPWM_CH1 zero or period point. + * | | |1000 = EPWM_CH1 up-count CMPDAT point. + * | | |1001 = EPWM_CH1 down-count CMPDAT point. + * | | |1010 = EPWM_CH0 up-count free CMPDAT point. + * | | |1011 = EPWM_CH0 down-count free CMPDAT point. + * | | |1100 = EPWM_CH2 up-count free CMPDAT point. + * | | |1101 = EPWM_CH2 down-count free CMPDAT point. + * | | |1110 = EPWM_CH4 up-count free CMPDAT point. + * | | |1111 = EPWM_CH4 down-count free CMPDAT point. + * |[7] |TRGEN0 |EPWM_CH0 Trigger EADC enable bit + * |[11:8] |TRGSEL1 |EPWM_CH1 Trigger EADC Source Select + * | | |0000 = EPWM_CH0 zero point. + * | | |0001 = EPWM_CH0 period point. + * | | |0010 = EPWM_CH0 zero or period point. + * | | |0011 = EPWM_CH0 up-count CMPDAT point. + * | | |0100 = EPWM_CH0 down-count CMPDAT point. + * | | |0101 = EPWM_CH1 zero point. + * | | |0110 = EPWM_CH1 period point. + * | | |0111 = EPWM_CH1 zero or period point. + * | | |1000 = EPWM_CH1 up-count CMPDAT point. + * | | |1001 = EPWM_CH1 down-count CMPDAT point. + * | | |1010 = EPWM_CH0 up-count free CMPDAT point. + * | | |1011 = EPWM_CH0 down-count free CMPDAT point. + * | | |1100 = EPWM_CH2 up-count free CMPDAT point. + * | | |1101 = EPWM_CH2 down-count free CMPDAT point. + * | | |1110 = EPWM_CH4 up-count free CMPDAT point. + * | | |1111 = EPWM_CH4 down-count free CMPDAT point. + * |[15] |TRGEN1 |EPWM_CH1 Trigger EADC enable bit + * |[19:16] |TRGSEL2 |EPWM_CH2 Trigger EADC Source Select + * | | |0000 = EPWM_CH2 zero point. + * | | |0001 = EPWM_CH2 period point. + * | | |0010 = EPWM_CH2 zero or period point. + * | | |0011 = EPWM_CH2 up-count CMPDAT point. + * | | |0100 = EPWM_CH2 down-count CMPDAT point. + * | | |0101 = EPWM_CH3 zero point. + * | | |0110 = EPWM_CH3 period point. + * | | |0111 = EPWM_CH3 zero or period point. + * | | |1000 = EPWM_CH3 up-count CMPDAT point. + * | | |1001 = EPWM_CH3 down-count CMPDAT point. + * | | |1010 = EPWM_CH0 up-count free CMPDAT point. + * | | |1011 = EPWM_CH0 down-count free CMPDAT point. + * | | |1100 = EPWM_CH2 up-count free CMPDAT point. + * | | |1101 = EPWM_CH2 down-count free CMPDAT point. + * | | |1110 = EPWM_CH4 up-count free CMPDAT point. + * | | |1111 = EPWM_CH4 down-count free CMPDAT point. + * |[23] |TRGEN2 |EPWM_CH2 Trigger EADC enable bit + * |[27:24] |TRGSEL3 |EPWM_CH3 Trigger EADC Source Select + * | | |0000 = EPWM_CH2 zero point. + * | | |0001 = EPWM_CH2 period point. + * | | |0010 = EPWM_CH2 zero or period point. + * | | |0011 = EPWM_CH2 up-count CMPDAT point. + * | | |0100 = EPWM_CH2 down-count CMPDAT point. + * | | |0101 = EPWM_CH3 zero point. + * | | |0110 = EPWM_CH3 period point. + * | | |0111 = EPWM_CH3 zero or period point. + * | | |1000 = EPWM_CH3 up-count CMPDAT point. + * | | |1001 = EPWM_CH3 down-count CMPDAT point. + * | | |1010 = EPWM_CH0 up-count free CMPDAT point. + * | | |1011 = EPWM_CH0 down-count free CMPDAT point. + * | | |1100 = EPWM_CH2 up-count free CMPDAT point. + * | | |1101 = EPWM_CH2 down-count free CMPDAT point. + * | | |1110 = EPWM_CH4 up-count free CMPDAT point. + * | | |1111 = EPWM_CH4 down-count free CMPDAT point. + * |[31] |TRGEN3 |EPWM_CH3 Trigger EADC enable bit + * @var EPWM_T::EADCTS1 + * Offset: 0xFC EPWM Trigger EADC Source Select Register 1 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[3:0] |TRGSEL4 |EPWM_CH4 Trigger EADC Source Select + * | | |0000 = EPWM_CH4 zero point. + * | | |0001 = EPWM_CH4 period point. + * | | |0010 = EPWM_CH4 zero or period point. + * | | |0011 = EPWM_CH4 up-count CMPDAT point. + * | | |0100 = EPWM_CH4 down-count CMPDAT point. + * | | |0101 = EPWM_CH5 zero point. + * | | |0110 = EPWM_CH5 period point. + * | | |0111 = EPWM_CH5 zero or period point. + * | | |1000 = EPWM_CH5 up-count CMPDAT point. + * | | |1001 = EPWM_CH5 down-count CMPDAT point. + * | | |1010 = EPWM_CH0 up-count free CMPDAT point. + * | | |1011 = EPWM_CH0 down-count free CMPDAT point. + * | | |1100 = EPWM_CH2 up-count free CMPDAT point. + * | | |1101 = EPWM_CH2 down-count free CMPDAT point. + * | | |1110 = EPWM_CH4 up-count free CMPDAT point. + * | | |1111 = EPWM_CH4 down-count free CMPDAT point. + * |[7] |TRGEN4 |EPWM_CH4 Trigger EADC enable bit + * |[11:8] |TRGSEL5 |EPWM_CH5 Trigger EADC Source Select + * | | |0000 = EPWM_CH4 zero point. + * | | |0001 = EPWM_CH4 period point. + * | | |0010 = EPWM_CH4 zero or period point. + * | | |0011 = EPWM_CH4 up-count CMPDAT point. + * | | |0100 = EPWM_CH4 down-count CMPDAT point. + * | | |0101 = EPWM_CH5 zero point. + * | | |0110 = EPWM_CH5 period point. + * | | |0111 = EPWM_CH5 zero or period point. + * | | |1000 = EPWM_CH5 up-count CMPDAT point. + * | | |1001 = EPWM_CH5 down-count CMPDAT point. + * | | |1010 = EPWM_CH0 up-count free CMPDAT point. + * | | |1011 = EPWM_CH0 down-count free CMPDAT point. + * | | |1100 = EPWM_CH2 up-count free CMPDAT point. + * | | |1101 = EPWM_CH2 down-count free CMPDAT point. + * | | |1110 = EPWM_CH4 up-count free CMPDAT point. + * | | |1111 = EPWM_CH4 down-count free CMPDAT point. + * |[15] |TRGEN5 |EPWM_CH5 Trigger EADC enable bit + * @var EPWM_T::FTCMPDAT[3] + * Offset: 0x100 EPWM Free Trigger Compare Register 0/1,2/3,4/5 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |FTCMP |EPWM Free Trigger Compare Register + * | | |FTCMP use to compare with even CNTR to trigger EADC + * | | |FTCMPDAT0, 2, 4 corresponding complementary pairs EPWM_CH0 and EPWM_CH1, EPWM_CH2 and EPWM_CH3, EPWM_CH4 and EPWM_CH5. + * @var EPWM_T::SSCTL + * Offset: 0x110 EPWM Synchronous Start Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |SSEN0 |EPWM Synchronous Start Function Enable Bits + * | | |When synchronous start function is enabled, the EPWM counter enable register (EPWM_CNTEN) can be enabled by writing EPWM synchronous start trigger bit (CNTSEN). + * | | |0 = EPWM synchronous start function Disabled. + * | | |1 = EPWM synchronous start function Enabled. + * |[1] |SSEN1 |EPWM Synchronous Start Function Enable Bits + * | | |When synchronous start function is enabled, the EPWM counter enable register (EPWM_CNTEN) can be enabled by writing EPWM synchronous start trigger bit (CNTSEN). + * | | |0 = EPWM synchronous start function Disabled. + * | | |1 = EPWM synchronous start function Enabled. + * |[2] |SSEN2 |EPWM Synchronous Start Function Enable Bits + * | | |When synchronous start function is enabled, the EPWM counter enable register (EPWM_CNTEN) can be enabled by writing EPWM synchronous start trigger bit (CNTSEN). + * | | |0 = EPWM synchronous start function Disabled. + * | | |1 = EPWM synchronous start function Enabled. + * |[3] |SSEN3 |EPWM Synchronous Start Function Enable Bits + * | | |When synchronous start function is enabled, the EPWM counter enable register (EPWM_CNTEN) can be enabled by writing EPWM synchronous start trigger bit (CNTSEN). + * | | |0 = EPWM synchronous start function Disabled. + * | | |1 = EPWM synchronous start function Enabled. + * |[4] |SSEN4 |EPWM Synchronous Start Function Enable Bits + * | | |When synchronous start function is enabled, the EPWM counter enable register (EPWM_CNTEN) can be enabled by writing EPWM synchronous start trigger bit (CNTSEN). + * | | |0 = EPWM synchronous start function Disabled. + * | | |1 = EPWM synchronous start function Enabled. + * |[5] |SSEN5 |EPWM Synchronous Start Function Enable Bits + * | | |When synchronous start function is enabled, the EPWM counter enable register (EPWM_CNTEN) can be enabled by writing EPWM synchronous start trigger bit (CNTSEN). + * | | |0 = EPWM synchronous start function Disabled. + * | | |1 = EPWM synchronous start function Enabled. + * |[9:8] |SSRC |EPWM Synchronous Start Source Select Bits + * | | |00 = Synchronous start source come from EPWM0. + * | | |01 = Synchronous start source come from EPWM1. + * | | |10 = Synchronous start source come from BPWM0. + * | | |11 = Synchronous start source come from BPWM1. + * @var EPWM_T::SSTRG + * Offset: 0x114 EPWM Synchronous Start Trigger Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |CNTSEN |EPWM Counter Synchronous Start Enable (Write Only) + * | | |PMW counter synchronous enable function is used to make selected EPWM channels (include EPWM0_CHx and EPWM1_CHx) start counting at the same time. + * | | |Writing this bit to 1 will also set the counter enable bit (CNTENn, n denotes channel 0 to 5) if correlated EPWM channel counter synchronous start function is enabled. + * @var EPWM_T::LEBCTL + * Offset: 0x118 EPWM Leading Edge Blanking Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |LEBEN |EPWM Leading Edge Blanking Enable Bit + * | | |0 = EPWM Leading Edge Blanking Disabled. + * | | |1 = EPWM Leading Edge Blanking Enabled. + * |[8] |SRCEN0 |EPWM Leading Edge Blanking Source From EPWM_CH0 Enable Bit + * | | |0 = EPWM Leading Edge Blanking Source from EPWM_CH0 Disabled. + * | | |1 = EPWM Leading Edge Blanking Source from EPWM_CH0 Enabled. + * |[9] |SRCEN2 |EPWM Leading Edge Blanking Source From EPWM_CH2 Enable Bit + * | | |0 = EPWM Leading Edge Blanking Source from EPWM_CH2 Disabled. + * | | |1 = EPWM Leading Edge Blanking Source from EPWM_CH2 Enabled. + * |[10] |SRCEN4 |EPWM Leading Edge Blanking Source From EPWM_CH4 Enable Bit + * | | |0 = EPWM Leading Edge Blanking Source from EPWM_CH4 Disabled. + * | | |1 = EPWM Leading Edge Blanking Source from EPWM_CH4 Enabled. + * |[17:16] |TRGTYPE |EPWM Leading Edge Blanking Trigger Type + * | | |0 = When detect leading edge blanking source rising edge, blanking counter start counting. + * | | |1 = When detect leading edge blanking source falling edge, blanking counter start counting. + * | | |2 = When detect leading edge blanking source rising or falling edge, blanking counter start counting. + * | | |3 = Reserved. + * @var EPWM_T::LEBCNT + * Offset: 0x11C EPWM Leading Edge Blanking Counter Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[8:0] |LEBCNT |EPWM Leading Edge Blanking Counter + * | | |This counter value decides leading edge blanking window size. + * | | |Blanking window size = LEBCNT+1, and LEB counter clock base is ECLK. + * @var EPWM_T::STATUS + * Offset: 0x120 EPWM Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |CNTMAXF0 |Time-base Counter Equal to 0xFFFF Latched Flag + * | | |0 = indicates the time-base counter never reached its maximum value 0xFFFF. + * | | |1 = indicates the time-base counter reached its maximum value, software can write 1 to clear this bit. + * |[1] |CNTMAXF1 |Time-base Counter Equal to 0xFFFF Latched Flag + * | | |0 = indicates the time-base counter never reached its maximum value 0xFFFF. + * | | |1 = indicates the time-base counter reached its maximum value, software can write 1 to clear this bit. + * |[2] |CNTMAXF2 |Time-base Counter Equal to 0xFFFF Latched Flag + * | | |0 = indicates the time-base counter never reached its maximum value 0xFFFF. + * | | |1 = indicates the time-base counter reached its maximum value, software can write 1 to clear this bit. + * |[3] |CNTMAXF3 |Time-base Counter Equal to 0xFFFF Latched Flag + * | | |0 = indicates the time-base counter never reached its maximum value 0xFFFF. + * | | |1 = indicates the time-base counter reached its maximum value, software can write 1 to clear this bit. + * |[4] |CNTMAXF4 |Time-base Counter Equal to 0xFFFF Latched Flag + * | | |0 = indicates the time-base counter never reached its maximum value 0xFFFF. + * | | |1 = indicates the time-base counter reached its maximum value, software can write 1 to clear this bit. + * |[5] |CNTMAXF5 |Time-base Counter Equal to 0xFFFF Latched Flag + * | | |0 = indicates the time-base counter never reached its maximum value 0xFFFF. + * | | |1 = indicates the time-base counter reached its maximum value, software can write 1 to clear this bit. + * |[8] |SYNCINF0 |Input Synchronization Latched Flag + * | | |0 = Indicates no SYNC_IN event has occurred. + * | | |1 = Indicates an SYNC_IN event has occurred, software can write 1 to clear this bit. + * |[9] |SYNCINF2 |Input Synchronization Latched Flag + * | | |0 = Indicates no SYNC_IN event has occurred. + * | | |1 = Indicates an SYNC_IN event has occurred, software can write 1 to clear this bit. + * |[10] |SYNCINF4 |Input Synchronization Latched Flag + * | | |0 = Indicates no SYNC_IN event has occurred. + * | | |1 = Indicates an SYNC_IN event has occurred, software can write 1 to clear this bit. + * |[16] |EADCTRGF0 |EADC Start of Conversion Flag + * | | |0 = Indicates no EADC start of conversion trigger event has occurred. + * | | |1 = Indicates an EADC start of conversion trigger event has occurred, software can write 1 to clear this bit. + * |[17] |EADCTRGF1 |EADC Start of Conversion Flag + * | | |0 = Indicates no EADC start of conversion trigger event has occurred. + * | | |1 = Indicates an EADC start of conversion trigger event has occurred, software can write 1 to clear this bit. + * |[18] |EADCTRGF2 |EADC Start of Conversion Flag + * | | |0 = Indicates no EADC start of conversion trigger event has occurred. + * | | |1 = Indicates an EADC start of conversion trigger event has occurred, software can write 1 to clear this bit. + * |[19] |EADCTRGF3 |EADC Start of Conversion Flag + * | | |0 = Indicates no EADC start of conversion trigger event has occurred. + * | | |1 = Indicates an EADC start of conversion trigger event has occurred, software can write 1 to clear this bit. + * |[20] |EADCTRGF4 |EADC Start of Conversion Flag + * | | |0 = Indicates no EADC start of conversion trigger event has occurred. + * | | |1 = Indicates an EADC start of conversion trigger event has occurred, software can write 1 to clear this bit. + * |[21] |EADCTRGF5 |EADC Start of Conversion Flag + * | | |0 = Indicates no EADC start of conversion trigger event has occurred. + * | | |1 = Indicates an EADC start of conversion trigger event has occurred, software can write 1 to clear this bit. + * |[24] |DACTRGF |DAC Start of Conversion Flag + * | | |0 = Indicates no DAC start of conversion trigger event has occurred. + * | | |1 = Indicates an DAC start of conversion trigger event has occurred, software can write 1 to clear this bit + * @var EPWM_T::IFA[6] + * Offset: 0x130 EPWM Interrupt Flag Accumulator Register 0~5 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |IFACNT |EPWM_CHn Interrupt Flag Counter + * | | |The register sets the count number which defines how many times of EPWM_CHn period occurs to set bit IFAIFn to request the EPWM period interrupt. + * | | |EPWM flag will be set in every IFACNT[15:0] times of EPWM period. + * |[24] |STPMOD |EPWM_CHn Interrupt Flag Accumulator Stop Mode Enable Bits + * | | |0 = EPWM_CHn interrupt flag accumulator stop mode disable. + * | | |1 = EPWM_CHn interrupt flag accumulator stop mode enable. + * |[29:28] |IFASEL |EPWM_CHn Interrupt Flag Accumulator Source Select + * | | |00 = CNT equal to Zero in channel n. + * | | |01 = CNT equal to PERIOD in channel n. + * | | |10 = CNT equal to CMPU in channel n. + * | | |11 = CNT equal to CMPD in channel n. + * |[31] |IFAEN |EPWM_CHn Interrupt Flag Accumulator Enable Bits + * | | |0 = EPWM_CHn interrupt flag accumulator disable. + * | | |1 = EPWM_CHn interrupt flag accumulator enable. + * @var EPWM_T::AINTSTS + * Offset: 0x150 EPWM Accumulator Interrupt Flag Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |IFAIF0 |EPWM_CHn Interrupt Flag Accumulator Interrupt Flag + * | | |Flag is set by hardware when condition match IFASEL in EPWM_IFAn register, software can clear this bit by writing 1 to it. + * |[1] |IFAIF1 |EPWM_CHn Interrupt Flag Accumulator Interrupt Flag + * | | |Flag is set by hardware when condition match IFASEL in EPWM_IFAn register, software can clear this bit by writing 1 to it. + * |[2] |IFAIF2 |EPWM_CHn Interrupt Flag Accumulator Interrupt Flag + * | | |Flag is set by hardware when condition match IFASEL in EPWM_IFAn register, software can clear this bit by writing 1 to it. + * |[3] |IFAIF3 |EPWM_CHn Interrupt Flag Accumulator Interrupt Flag + * | | |Flag is set by hardware when condition match IFASEL in EPWM_IFAn register, software can clear this bit by writing 1 to it. + * |[4] |IFAIF4 |EPWM_CHn Interrupt Flag Accumulator Interrupt Flag + * | | |Flag is set by hardware when condition match IFASEL in EPWM_IFAn register, software can clear this bit by writing 1 to it. + * |[5] |IFAIF5 |EPWM_CHn Interrupt Flag Accumulator Interrupt Flag + * | | |Flag is set by hardware when condition match IFASEL in EPWM_IFAn register, software can clear this bit by writing 1 to it. + * @var EPWM_T::AINTEN + * Offset: 0x154 EPWM Accumulator Interrupt Enable Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |IFAIEN0 |EPWM_CHn Interrupt Flag Accumulator Interrupt Enable Bits + * | | |0 = Interrupt Flag accumulator interrupt Disabled. + * | | |1 = Interrupt Flag accumulator interrupt Enabled. + * |[1] |IFAIEN1 |EPWM_CHn Interrupt Flag Accumulator Interrupt Enable Bits + * | | |0 = Interrupt Flag accumulator interrupt Disabled. + * | | |1 = Interrupt Flag accumulator interrupt Enabled. + * |[2] |IFAIEN2 |EPWM_CHn Interrupt Flag Accumulator Interrupt Enable Bits + * | | |0 = Interrupt Flag accumulator interrupt Disabled. + * | | |1 = Interrupt Flag accumulator interrupt Enabled. + * |[3] |IFAIEN3 |EPWM_CHn Interrupt Flag Accumulator Interrupt Enable Bits + * | | |0 = Interrupt Flag accumulator interrupt Disabled. + * | | |1 = Interrupt Flag accumulator interrupt Enabled. + * |[4] |IFAIEN4 |EPWM_CHn Interrupt Flag Accumulator Interrupt Enable Bits + * | | |0 = Interrupt Flag accumulator interrupt Disabled. + * | | |1 = Interrupt Flag accumulator interrupt Enabled. + * |[5] |IFAIEN5 |EPWM_CHn Interrupt Flag Accumulator Interrupt Enable Bits + * | | |0 = Interrupt Flag accumulator interrupt Disabled. + * | | |1 = Interrupt Flag accumulator interrupt Enabled. + * @var EPWM_T::APDMACTL + * Offset: 0x158 EPWM Accumulator PDMA Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |APDMAEN0 |Channel N Accumulator PDMA Enable Bits + * | | |0 = Channel n PDMA function Disabled. + * | | |1 = Channel n PDMA function Enabled for the channel n to trigger PDMA to transfer memory data to register. + * |[1] |APDMAEN1 |Channel N Accumulator PDMA Enable Bits + * | | |0 = Channel n PDMA function Disabled. + * | | |1 = Channel n PDMA function Enabled for the channel n to trigger PDMA to transfer memory data to register. + * |[2] |APDMAEN2 |Channel N Accumulator PDMA Enable Bits + * | | |0 = Channel n PDMA function Disabled. + * | | |1 = Channel n PDMA function Enabled for the channel n to trigger PDMA to transfer memory data to register. + * |[3] |APDMAEN3 |Channel N Accumulator PDMA Enable Bits + * | | |0 = Channel n PDMA function Disabled. + * | | |1 = Channel n PDMA function Enabled for the channel n to trigger PDMA to transfer memory data to register. + * |[4] |APDMAEN4 |Channel N Accumulator PDMA Enable Bits + * | | |0 = Channel n PDMA function Disabled. + * | | |1 = Channel n PDMA function Enabled for the channel n to trigger PDMA to transfer memory data to register. + * |[5] |APDMAEN5 |Channel N Accumulator PDMA Enable Bits + * | | |0 = Channel n PDMA function Disabled. + * | | |1 = Channel n PDMA function Enabled for the channel n to trigger PDMA to transfer memory data to register. + * @var EPWM_T::CAPINEN + * Offset: 0x200 EPWM Capture Input Enable Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |CAPINEN0 |Capture Input Enable Bits + * | | |0 = EPWM Channel capture input path Disabled + * | | |The input of EPWM channel capture function is always regarded as 0. + * | | |1 = EPWM Channel capture input path Enabled + * | | |The input of EPWM channel capture function comes from correlative multifunction pin. + * |[1] |CAPINEN1 |Capture Input Enable Bits + * | | |0 = EPWM Channel capture input path Disabled + * | | |The input of EPWM channel capture function is always regarded as 0. + * | | |1 = EPWM Channel capture input path Enabled + * | | |The input of EPWM channel capture function comes from correlative multifunction pin. + * |[2] |CAPINEN2 |Capture Input Enable Bits + * | | |0 = EPWM Channel capture input path Disabled + * | | |The input of EPWM channel capture function is always regarded as 0. + * | | |1 = EPWM Channel capture input path Enabled + * | | |The input of EPWM channel capture function comes from correlative multifunction pin. + * |[3] |CAPINEN3 |Capture Input Enable Bits + * | | |0 = EPWM Channel capture input path Disabled + * | | |The input of EPWM channel capture function is always regarded as 0. + * | | |1 = EPWM Channel capture input path Enabled + * | | |The input of EPWM channel capture function comes from correlative multifunction pin. + * |[4] |CAPINEN4 |Capture Input Enable Bits + * | | |0 = EPWM Channel capture input path Disabled + * | | |The input of EPWM channel capture function is always regarded as 0. + * | | |1 = EPWM Channel capture input path Enabled + * | | |The input of EPWM channel capture function comes from correlative multifunction pin. + * |[5] |CAPINEN5 |Capture Input Enable Bits + * | | |0 = EPWM Channel capture input path Disabled + * | | |The input of EPWM channel capture function is always regarded as 0. + * | | |1 = EPWM Channel capture input path Enabled + * | | |The input of EPWM channel capture function comes from correlative multifunction pin. + * @var EPWM_T::CAPCTL + * Offset: 0x204 EPWM Capture Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |CAPEN0 |Capture Function Enable Bits + * | | |0 = Capture function Disabled. RCAPDAT/FCAPDAT register will not be updated. + * | | |1 = Capture function Enabled + * | | |Capture latched the EPWM counter value when detected rising or falling edge of input signal and saved to RCAPDAT (Rising latch) and FCAPDAT (Falling latch). + * |[1] |CAPEN1 |Capture Function Enable Bits + * | | |0 = Capture function Disabled. RCAPDAT/FCAPDAT register will not be updated. + * | | |1 = Capture function Enabled + * | | |Capture latched the EPWM counter value when detected rising or falling edge of input signal and saved to RCAPDAT (Rising latch) and FCAPDAT (Falling latch). + * |[2] |CAPEN2 |Capture Function Enable Bits + * | | |0 = Capture function Disabled. RCAPDAT/FCAPDAT register will not be updated. + * | | |1 = Capture function Enabled + * | | |Capture latched the EPWM counter value when detected rising or falling edge of input signal and saved to RCAPDAT (Rising latch) and FCAPDAT (Falling latch). + * |[3] |CAPEN3 |Capture Function Enable Bits + * | | |0 = Capture function Disabled. RCAPDAT/FCAPDAT register will not be updated. + * | | |1 = Capture function Enabled + * | | |Capture latched the EPWM counter value when detected rising or falling edge of input signal and saved to RCAPDAT (Rising latch) and FCAPDAT (Falling latch). + * |[4] |CAPEN4 |Capture Function Enable Bits + * | | |0 = Capture function Disabled. RCAPDAT/FCAPDAT register will not be updated. + * | | |1 = Capture function Enabled + * | | |Capture latched the EPWM counter value when detected rising or falling edge of input signal and saved to RCAPDAT (Rising latch) and FCAPDAT (Falling latch). + * |[5] |CAPEN5 |Capture Function Enable Bits + * | | |0 = Capture function Disabled. RCAPDAT/FCAPDAT register will not be updated. + * | | |1 = Capture function Enabled + * | | |Capture latched the EPWM counter value when detected rising or falling edge of input signal and saved to RCAPDAT (Rising latch) and FCAPDAT (Falling latch). + * |[8] |CAPINV0 |Capture Inverter Enable Bits + * | | |0 = Capture source inverter Disabled. + * | | |1 = Capture source inverter Enabled. Reverse the input signal from GPIO. + * |[9] |CAPINV1 |Capture Inverter Enable Bits + * | | |0 = Capture source inverter Disabled. + * | | |1 = Capture source inverter Enabled. Reverse the input signal from GPIO. + * |[10] |CAPINV2 |Capture Inverter Enable Bits + * | | |0 = Capture source inverter Disabled. + * | | |1 = Capture source inverter Enabled. Reverse the input signal from GPIO. + * |[11] |CAPINV3 |Capture Inverter Enable Bits + * | | |0 = Capture source inverter Disabled. + * | | |1 = Capture source inverter Enabled. Reverse the input signal from GPIO. + * |[12] |CAPINV4 |Capture Inverter Enable Bits + * | | |0 = Capture source inverter Disabled. + * | | |1 = Capture source inverter Enabled. Reverse the input signal from GPIO. + * |[13] |CAPINV5 |Capture Inverter Enable Bits + * | | |0 = Capture source inverter Disabled. + * | | |1 = Capture source inverter Enabled. Reverse the input signal from GPIO. + * |[16] |RCRLDEN0 |Rising Capture Reload Enable Bits + * | | |0 = Rising capture reload counter Disabled. + * | | |1 = Rising capture reload counter Enabled. + * |[17] |RCRLDEN1 |Rising Capture Reload Enable Bits + * | | |0 = Rising capture reload counter Disabled. + * | | |1 = Rising capture reload counter Enabled. + * |[18] |RCRLDEN2 |Rising Capture Reload Enable Bits + * | | |0 = Rising capture reload counter Disabled. + * | | |1 = Rising capture reload counter Enabled. + * |[19] |RCRLDEN3 |Rising Capture Reload Enable Bits + * | | |0 = Rising capture reload counter Disabled. + * | | |1 = Rising capture reload counter Enabled. + * |[20] |RCRLDEN4 |Rising Capture Reload Enable Bits + * | | |0 = Rising capture reload counter Disabled. + * | | |1 = Rising capture reload counter Enabled. + * |[21] |RCRLDEN5 |Rising Capture Reload Enable Bits + * | | |0 = Rising capture reload counter Disabled. + * | | |1 = Rising capture reload counter Enabled. + * |[24] |FCRLDEN0 |Falling Capture Reload Enable Bits + * | | |0 = Falling capture reload counter Disabled. + * | | |1 = Falling capture reload counter Enabled. + * |[25] |FCRLDEN1 |Falling Capture Reload Enable Bits + * | | |0 = Falling capture reload counter Disabled. + * | | |1 = Falling capture reload counter Enabled. + * |[26] |FCRLDEN2 |Falling Capture Reload Enable Bits + * | | |0 = Falling capture reload counter Disabled. + * | | |1 = Falling capture reload counter Enabled. + * |[27] |FCRLDEN3 |Falling Capture Reload Enable Bits + * | | |0 = Falling capture reload counter Disabled. + * | | |1 = Falling capture reload counter Enabled. + * |[28] |FCRLDEN4 |Falling Capture Reload Enable Bits + * | | |0 = Falling capture reload counter Disabled. + * | | |1 = Falling capture reload counter Enabled. + * |[29] |FCRLDEN5 |Falling Capture Reload Enable Bits + * | | |0 = Falling capture reload counter Disabled. + * | | |1 = Falling capture reload counter Enabled. + * @var EPWM_T::CAPSTS + * Offset: 0x208 EPWM Capture Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |CRLIFOV0 |Capture Rising Latch Interrupt Flag Overrun Status (Read Only) + * | | |This flag indicates if rising latch happened when the corresponding CRLIF is 1. + * | | |Note: This bit will be cleared automatically when user clear corresponding CRLIF. + * |[1] |CRLIFOV1 |Capture Rising Latch Interrupt Flag Overrun Status (Read Only) + * | | |This flag indicates if rising latch happened when the corresponding CRLIF is 1. + * | | |Note: This bit will be cleared automatically when user clear corresponding CRLIF. + * |[2] |CRLIFOV2 |Capture Rising Latch Interrupt Flag Overrun Status (Read Only) + * | | |This flag indicates if rising latch happened when the corresponding CRLIF is 1. + * | | |Note: This bit will be cleared automatically when user clear corresponding CRLIF. + * |[3] |CRLIFOV3 |Capture Rising Latch Interrupt Flag Overrun Status (Read Only) + * | | |This flag indicates if rising latch happened when the corresponding CRLIF is 1. + * | | |Note: This bit will be cleared automatically when user clear corresponding CRLIF. + * |[4] |CRLIFOV4 |Capture Rising Latch Interrupt Flag Overrun Status (Read Only) + * | | |This flag indicates if rising latch happened when the corresponding CRLIF is 1. + * | | |Note: This bit will be cleared automatically when user clear corresponding CRLIF. + * |[5] |CRLIFOV5 |Capture Rising Latch Interrupt Flag Overrun Status (Read Only) + * | | |This flag indicates if rising latch happened when the corresponding CRLIF is 1. + * | | |Note: This bit will be cleared automatically when user clear corresponding CRLIF. + * |[8] |CFLIFOV0 |Capture Falling Latch Interrupt Flag Overrun Status (Read Only) + * | | |This flag indicates if falling latch happened when the corresponding CFLIF is 1. + * | | |Note: This bit will be cleared automatically when user clear corresponding CFLIF. + * |[9] |CFLIFOV1 |Capture Falling Latch Interrupt Flag Overrun Status (Read Only) + * | | |This flag indicates if falling latch happened when the corresponding CFLIF is 1. + * | | |Note: This bit will be cleared automatically when user clear corresponding CFLIF. + * |[10] |CFLIFOV2 |Capture Falling Latch Interrupt Flag Overrun Status (Read Only) + * | | |This flag indicates if falling latch happened when the corresponding CFLIF is 1. + * | | |Note: This bit will be cleared automatically when user clear corresponding CFLIF. + * |[11] |CFLIFOV3 |Capture Falling Latch Interrupt Flag Overrun Status (Read Only) + * | | |This flag indicates if falling latch happened when the corresponding CFLIF is 1. + * | | |Note: This bit will be cleared automatically when user clear corresponding CFLIF. + * |[12] |CFLIFOV4 |Capture Falling Latch Interrupt Flag Overrun Status (Read Only) + * | | |This flag indicates if falling latch happened when the corresponding CFLIF is 1. + * | | |Note: This bit will be cleared automatically when user clear corresponding CFLIF. + * |[13] |CFLIFOV5 |Capture Falling Latch Interrupt Flag Overrun Status (Read Only) + * | | |This flag indicates if falling latch happened when the corresponding CFLIF is 1. + * | | |Note: This bit will be cleared automatically when user clear corresponding CFLIF. + * @var EPWM_T::PDMACTL + * Offset: 0x23C EPWM PDMA Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |CHEN0_1 |Channel 0/1 PDMA Enable + * | | |0 = Channel 0/1 PDMA function Disabled. + * | | |1 = Channel 0/1 PDMA function Enabled for the channel 0/1 captured data and transfer to memory. + * |[2:1] |CAPMOD0_1 |Select EPWM_RCAPDAT0/1 or EPWM_FCAPDAT0/1 to Do PDMA Transfer + * | | |00 = Reserved. + * | | |01 = EPWM_RCAPDAT0/1 register. + * | | |10 = EPWM_FCAPDAT0/1 register. + * | | |11 = Both EPWM_RCAPDAT0/1 and EPWM_FCAPDAT0/1 registers. + * |[3] |CAPORD0_1 |Capture Channel 0/1 Rising/Falling Order + * | | |Set this bit to determine whether the EPWM_RCAPDAT0/1 or EPWM_FCAPDAT0/1 register is the first captured data transferred to memory through PDMA when CAPMOD0_1 bits are set to = 0x3. + * | | |0 = EPWM_FCAPDAT0/1 register is the first captured data to memory. + * | | |1 = EPWM_RCAPDAT0/1 register is the first captured data to memory. + * |[4] |CHSEL0_1 |Select Channel 0/1 to Do PDMA Transfer + * | | |0 = Channel0. + * | | |1 = Channel1. + * |[8] |CHEN2_3 |Channel 2/3 PDMA Enable + * | | |0 = Channel 2/3 PDMA function Disabled. + * | | |1 = Channel 2/3 PDMA function Enabled for the channel 2/3 captured data and transfer to memory. + * |[10:9] |CAPMOD2_3 |Select EPWM_RCAPDAT2/3 or EPWM_FCAODAT2/3 to Do PDMA Transfer + * | | |00 = Reserved. + * | | |01 = EPWM_RCAPDAT2/3 register. + * | | |10 = EPWM_FCAPDAT2/3 register. + * | | |11 = Both EPWM_RCAPDAT2/3 and EPWM_FCAPDAT2/3 registers. + * |[11] |CAPORD2_3 |Capture Channel 2/3 Rising/Falling Order + * | | |Set this bit to determine whether the EPWM_RCAPDAT2/3 or EPWM_FCAPDAT2/3 register is the first captured data transferred to memory through PDMA when CAPMOD2_3 bits are set to =0x3. + * | | |0 = EPWM_FCAPDAT2/3 register is the first captured data to memory. + * | | |1 = EPWM_RCAPDAT2/3 register is the first captured data to memory. + * |[12] |CHSEL2_3 |Select Channel 2/3 to Do PDMA Transfer + * | | |0 = Channel2. + * | | |1 = Channel3. + * |[16] |CHEN4_5 |Channel 4/5 PDMA Enable + * | | |0 = Channel 4/5 PDMA function Disabled. + * | | |1 = Channel 4/5 PDMA function Enabled for the channel 4/5 captured data and transfer to memory. + * |[18:17] |CAPMOD4_5 |Select EPWM_RCAPDAT4/5 or EPWM_FCAPDAT4/5 to Do PDMA Transfer + * | | |00 = Reserved. + * | | |01 = EPWM_RCAPDAT4/5 register. + * | | |10 = EPWM_FCAPDAT4/5 register. + * | | |11 = Both EPWM_RCAPDAT4/5 and EPWM_FCAPDAT4/5 registers. + * |[19] |CAPORD4_5 |Capture Channel 4/5 Rising/Falling Order + * | | |Set this bit to determine whether the EPWM_RCAPDAT4/5 or EPWM_FCAPDAT4/5 register is the first captured data transferred to memory through PDMA when CAPMOD4_5 bits =are set to 0x3. + * | | |0 = EPWM_FCAPDAT4/5 register is the first captured data to memory. + * | | |1 = EPWM_RCAPDAT4/5 register is the first captured data to memory. + * |[20] |CHSEL4_5 |Select Channel 4/5 to Do PDMA Transfer + * | | |0 = Channel4. + * | | |1 = Channel5. + * @var EPWM_T::PDMACAP[3] + * Offset: 0x240 EPWM Capture Channel 01 PDMA Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |CAPBUF |EPWM Capture PDMA Register (Read Only) + * | | |This register is use as a buffer to transfer EPWM capture rising or falling data to memory by PDMA. + * @var EPWM_T::CAPIEN + * Offset: 0x250 EPWM Capture Interrupt Enable Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |CAPRIEN0 |EPWM Capture Rising Latch Interrupt Enable Bits + * | | |0 = Capture rising edge latch interrupt Disabled. + * | | |1 = Capture rising edge latch interrupt Enabled. + * | | |Note: When Capture with PDMA operating, corresponding channel CAPRIEN0 bit must be disabled. + * |[1] |CAPRIEN1 |EPWM Capture Rising Latch Interrupt Enable Bits + * | | |0 = Capture rising edge latch interrupt Disabled. + * | | |1 = Capture rising edge latch interrupt Enabled. + * | | |Note: When Capture with PDMA operating, corresponding channel CAPRIEN1 bit must be disabled. + * |[2] |CAPRIEN2 |EPWM Capture Rising Latch Interrupt Enable Bits + * | | |0 = Capture rising edge latch interrupt Disabled. + * | | |1 = Capture rising edge latch interrupt Enabled. + * | | |Note: When Capture with PDMA operating, corresponding channel CAPRIEN2 bit must be disabled. + * |[3] |CAPRIEN3 |EPWM Capture Rising Latch Interrupt Enable Bits + * | | |0 = Capture rising edge latch interrupt Disabled. + * | | |1 = Capture rising edge latch interrupt Enabled. + * | | |Note: When Capture with PDMA operating, corresponding channel CAPRIEN3 bit must be disabled. + * |[4] |CAPRIEN4 |EPWM Capture Rising Latch Interrupt Enable Bits + * | | |0 = Capture rising edge latch interrupt Disabled. + * | | |1 = Capture rising edge latch interrupt Enabled. + * | | |Note: When Capture with PDMA operating, corresponding channel CAPRIEN4 bit must be disabled. + * |[5] |CAPRIEN5 |EPWM Capture Rising Latch Interrupt Enable Bits + * | | |0 = Capture rising edge latch interrupt Disabled. + * | | |1 = Capture rising edge latch interrupt Enabled. + * | | |Note: When Capture with PDMA operating, corresponding channel CAPRIEN5 bit must be disabled. + * |[8] |CAPFIEN0 |EPWM Capture Falling Latch Interrupt Enable Bits + * | | |0 = Capture falling edge latch interrupt Disabled. + * | | |1 = Capture falling edge latch interrupt Enabled. + * | | |Note: When Capture with PDMA operating, corresponding channel CAPFIEN0 bit must be disabled. + * |[9] |CAPFIEN1 |EPWM Capture Falling Latch Interrupt Enable Bits + * | | |0 = Capture falling edge latch interrupt Disabled. + * | | |1 = Capture falling edge latch interrupt Enabled. + * | | |Note: When Capture with PDMA operating, corresponding channel CAPFIEN1 bit must be disabled. + * |[10] |CAPFIEN2 |EPWM Capture Falling Latch Interrupt Enable Bits + * | | |0 = Capture falling edge latch interrupt Disabled. + * | | |1 = Capture falling edge latch interrupt Enabled. + * | | |Note: When Capture with PDMA operating, corresponding channel CAPFIEN2 bit must be disabled. + * |[11] |CAPFIEN3 |EPWM Capture Falling Latch Interrupt Enable Bits + * | | |0 = Capture falling edge latch interrupt Disabled. + * | | |1 = Capture falling edge latch interrupt Enabled. + * | | |Note: When Capture with PDMA operating, corresponding channel CAPFIEN3 bit must be disabled. + * |[12] |CAPFIEN4 |EPWM Capture Falling Latch Interrupt Enable Bits + * | | |0 = Capture falling edge latch interrupt Disabled. + * | | |1 = Capture falling edge latch interrupt Enabled. + * | | |Note: When Capture with PDMA operating, corresponding channel CAPFIEN4 bit must be disabled. + * |[13] |CAPFIEN5 |EPWM Capture Falling Latch Interrupt Enable Bits + * | | |0 = Capture falling edge latch interrupt Disabled. + * | | |1 = Capture falling edge latch interrupt Enabled. + * | | |Note: When Capture with PDMA operating, corresponding channel CAPFIEN5 bit must be disabled. + * @var EPWM_T::CAPIF + * Offset: 0x254 EPWM Capture Interrupt Flag Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |CRLIF0 |EPWM Capture Rising Latch Interrupt Flag + * | | |This bit is writing 1 to clear. + * | | |0 = No capture rising latch condition happened. + * | | |1 = Capture rising latch condition happened, this flag will be set to high. + * | | |Note: When Capture with PDMA operating, corresponding channel CRLIF0 bit will cleared by hardware after PDMA transfer data. + * |[1] |CRLIF1 |EPWM Capture Rising Latch Interrupt Flag + * | | |This bit is writing 1 to clear. + * | | |0 = No capture rising latch condition happened. + * | | |1 = Capture rising latch condition happened, this flag will be set to high. + * | | |Note: When Capture with PDMA operating, corresponding channel CRLIF1 bit will cleared by hardware after PDMA transfer data. + * |[2] |CRLIF2 |EPWM Capture Rising Latch Interrupt Flag + * | | |This bit is writing 1 to clear. + * | | |0 = No capture rising latch condition happened. + * | | |1 = Capture rising latch condition happened, this flag will be set to high. + * | | |Note: When Capture with PDMA operating, corresponding channel CRLIF2 bit will cleared by hardware after PDMA transfer data. + * |[3] |CRLIF3 |EPWM Capture Rising Latch Interrupt Flag + * | | |This bit is writing 1 to clear. + * | | |0 = No capture rising latch condition happened. + * | | |1 = Capture rising latch condition happened, this flag will be set to high. + * | | |Note: When Capture with PDMA operating, corresponding channel CRLIF3 bit will cleared by hardware after PDMA transfer data. + * |[4] |CRLIF4 |EPWM Capture Rising Latch Interrupt Flag + * | | |This bit is writing 1 to clear. + * | | |0 = No capture rising latch condition happened. + * | | |1 = Capture rising latch condition happened, this flag will be set to high. + * | | |Note: When Capture with PDMA operating, corresponding channel CRLIF4 bit will cleared by hardware after PDMA transfer data. + * |[5] |CRLIF5 |EPWM Capture Rising Latch Interrupt Flag + * | | |This bit is writing 1 to clear. + * | | |0 = No capture rising latch condition happened. + * | | |1 = Capture rising latch condition happened, this flag will be set to high. + * | | |Note: When Capture with PDMA operating, corresponding channel CRLIF5 bit will cleared by hardware after PDMA transfer data. + * |[8] |CFLIF0 |EPWM Capture Falling Latch Interrupt Flag + * | | |This bit is writing 1 to clear. + * | | |0 = No capture falling latch condition happened. + * | | |1 = Capture falling latch condition happened, this flag will be set to high. + * | | |Note: When Capture with PDMA operating, corresponding channel CFLIF0 bit will cleared by hardware after PDMA transfer data. + * |[9] |CFLIF1 |EPWM Capture Falling Latch Interrupt Flag + * | | |This bit is writing 1 to clear. + * | | |0 = No capture falling latch condition happened. + * | | |1 = Capture falling latch condition happened, this flag will be set to high. + * | | |Note: When Capture with PDMA operating, corresponding channel CFLIF1 bit will cleared by hardware after PDMA transfer data. + * |[10] |CFLIF2 |EPWM Capture Falling Latch Interrupt Flag + * | | |This bit is writing 1 to clear. + * | | |0 = No capture falling latch condition happened. + * | | |1 = Capture falling latch condition happened, this flag will be set to high. + * | | |Note: When Capture with PDMA operating, corresponding channel CFLIF2 bit will cleared by hardware after PDMA transfer data. + * |[11] |CFLIF3 |EPWM Capture Falling Latch Interrupt Flag + * | | |This bit is writing 1 to clear. + * | | |0 = No capture falling latch condition happened. + * | | |1 = Capture falling latch condition happened, this flag will be set to high. + * | | |Note: When Capture with PDMA operating, corresponding channel CFLIF3 bit will cleared by hardware after PDMA transfer data. + * |[12] |CFLIF4 |EPWM Capture Falling Latch Interrupt Flag + * | | |This bit is writing 1 to clear. + * | | |0 = No capture falling latch condition happened. + * | | |1 = Capture falling latch condition happened, this flag will be set to high. + * | | |Note: When Capture with PDMA operating, corresponding channel CFLIF4 bit will cleared by hardware after PDMA transfer data. + * |[13] |CFLIF5 |EPWM Capture Falling Latch Interrupt Flag + * | | |This bit is writing 1 to clear. + * | | |0 = No capture falling latch condition happened. + * | | |1 = Capture falling latch condition happened, this flag will be set to high. + * | | |Note: When Capture with PDMA operating, CAPIF corresponding channel CFLIF will cleared by hardware after PDMA transfer data. + * @var EPWM_T::PBUF[6] + * Offset: 0x304 EPWM PERIOD0~5 Buffer + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |PBUF |EPWM Period Register Buffer (Read Only) + * | | |Used as PERIOD active register. + * @var EPWM_T::CMPBUF[6] + * Offset: 0x31C EPWM CMPDAT0~5 Buffer + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |CMPBUF |EPWM Comparator Register Buffer (Read Only) + * | | |Used as CMP active register. + * @var EPWM_T::CPSCBUF[3] + * Offset: 0x334 EPWM CLKPSC0_1/2_3/4_5 Buffer + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[11:0] |CPSCBUF |EPWM Counter Clock Prescale Buffer + * | | |Use as EPWM counter clock prescale active register. + * @var EPWM_T::FTCBUF[3] + * Offset: 0x340 EPWM FTCMPDAT0_1/2_3/4_5 Buffer + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |FTCMPBUF |EPWM FTCMPDAT Buffer (Read Only) + * | | |Used as FTCMPDAT active register. + * @var EPWM_T::FTCI + * Offset: 0x34C EPWM FTCMPDAT Indicator Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |FTCMU0 |EPWM FTCMPDAT Up Indicator + * | | |Indicator will be set to high when FTCMPDATn equal to CNTn and DIRF=1, software can write 1 to clear this bit. + * |[1] |FTCMU2 |EPWM FTCMPDAT Up Indicator + * | | |Indicator will be set to high when FTCMPDATn equal to CNTn and DIRF=1, software can write 1 to clear this bit. + * |[2] |FTCMU4 |EPWM FTCMPDAT Up Indicator + * | | |Indicator will be set to high when FTCMPDATn equal to CNTn and DIRF=1, software can write 1 to clear this bit. + * |[8] |FTCMD0 |EPWM FTCMPDAT Down Indicator + * | | |Indicator will be set to high when FTCMPDATn equal to CNTn and DIRF=0, software can write 1 to clear this bit. + * |[9] |FTCMD2 |EPWM FTCMPDAT Down Indicator + * | | |Indicator will be set to high when FTCMPDATn equal to CNTn and DIRF=0, software can write 1 to clear this bit. + * |[10] |FTCMD4 |EPWM FTCMPDAT Down Indicator + * | | |Indicator will be set to high when FTCMPDATn equal to CNTn and DIRF=0, software can write 1 to clear this bit. + */ + __IO uint32_t CTL0; /*!< [0x0000] EPWM Control Register 0 */ + __IO uint32_t CTL1; /*!< [0x0004] EPWM Control Register 1 */ + __IO uint32_t SYNC; /*!< [0x0008] EPWM Synchronization Register */ + __IO uint32_t SWSYNC; /*!< [0x000c] EPWM Software Control Synchronization Register */ + __IO uint32_t CLKSRC; /*!< [0x0010] EPWM Clock Source Register */ + __IO uint32_t CLKPSC[3]; /*!< [0x0014~0x001c] EPWM Clock Prescale Register 0_1,2_3,4_5 */ + __IO uint32_t CNTEN; /*!< [0x0020] EPWM Counter Enable Register */ + __IO uint32_t CNTCLR; /*!< [0x0024] EPWM Clear Counter Register */ + __IO uint32_t LOAD; /*!< [0x0028] EPWM Load Register */ + __I uint32_t RESERVE0[1]; + __IO uint32_t PERIOD[6]; /*!< [0x0030~0x0044] EPWM Period Register 0~5 */ + __I uint32_t RESERVE1[2]; + __IO uint32_t CMPDAT[6]; /*!< [0x0050~0x0064] EPWM Comparator Register 0~5 */ + __I uint32_t RESERVE2[2]; + __IO uint32_t DTCTL[3]; /*!< [0x0070~0x0078] EPWM Dead-Time Control Register 0_1,2_3,4_5 */ + __I uint32_t RESERVE3[1]; + __IO uint32_t PHS[3]; /*!< [0x0080~0x0088] EPWM Counter Phase Register 0_1,2_3,4_5 */ + __I uint32_t RESERVE4[1]; + __I uint32_t CNT[6]; /*!< [0x0090~0x00A4 EPWM Counter Register 0~5 */ + __I uint32_t RESERVE5[2]; + __IO uint32_t WGCTL0; /*!< [0x00b0] EPWM Generation Register 0 */ + __IO uint32_t WGCTL1; /*!< [0x00b4] EPWM Generation Register 1 */ + __IO uint32_t MSKEN; /*!< [0x00b8] EPWM Mask Enable Register */ + __IO uint32_t MSK; /*!< [0x00bc] EPWM Mask Data Register */ + __IO uint32_t BNF; /*!< [0x00c0] EPWM Brake Noise Filter Register */ + __IO uint32_t FAILBRK; /*!< [0x00c4] EPWM System Fail Brake Control Register */ + __IO uint32_t BRKCTL[3]; /*!< [0x00c8~0x00d0] EPWM Brake Edge Detect Control Register 0_1,2_3,4_5 */ + __IO uint32_t POLCTL; /*!< [0x00d4] EPWM Pin Polar Inverse Register */ + __IO uint32_t POEN; /*!< [0x00d8] EPWM Output Enable Register */ + __O uint32_t SWBRK; /*!< [0x00dc] EPWM Software Brake Control Register */ + __IO uint32_t INTEN0; /*!< [0x00e0] EPWM Interrupt Enable Register 0 */ + __IO uint32_t INTEN1; /*!< [0x00e4] EPWM Interrupt Enable Register 1 */ + __IO uint32_t INTSTS0; /*!< [0x00e8] EPWM Interrupt Flag Register 0 */ + __IO uint32_t INTSTS1; /*!< [0x00ec] EPWM Interrupt Flag Register 1 */ + __I uint32_t RESERVE6[1]; + __IO uint32_t DACTRGEN; /*!< [0x00f4] EPWM Trigger DAC Enable Register */ + __IO uint32_t EADCTS0; /*!< [0x00f8] EPWM Trigger EADC Source Select Register 0 */ + __IO uint32_t EADCTS1; /*!< [0x00fc] EPWM Trigger EADC Source Select Register 1 */ + __IO uint32_t FTCMPDAT[3]; /*!< [0x0100~0x108] EPWM Free Trigger Compare Register 0_1,2_3,4_5 */ + __I uint32_t RESERVE7[1]; + __IO uint32_t SSCTL; /*!< [0x0110] EPWM Synchronous Start Control Register */ + __O uint32_t SSTRG; /*!< [0x0114] EPWM Synchronous Start Trigger Register */ + __IO uint32_t LEBCTL; /*!< [0x0118] EPWM Leading Edge Blanking Control Register */ + __IO uint32_t LEBCNT; /*!< [0x011c] EPWM Leading Edge Blanking Counter Register */ + __IO uint32_t STATUS; /*!< [0x0120] EPWM Status Register */ + __I uint32_t RESERVE8[3]; + __IO uint32_t IFA[6]; /*!< [0x0130~0x144] EPWM Interrupt Flag Accumulator Register 0~5 */ + __I uint32_t RESERVE9[2]; + __IO uint32_t AINTSTS; /*!< [0x0150] EPWM Accumulator Interrupt Flag Register */ + __IO uint32_t AINTEN; /*!< [0x0154] EPWM Accumulator Interrupt Enable Register */ + __IO uint32_t APDMACTL; /*!< [0x0158] EPWM Accumulator PDMA Control Register */ + __I uint32_t RESERVE10[1]; + __IO uint32_t FDEN; /*!< [0x0160] EPWM Fault Detect Enable Register */ + __IO uint32_t FDCTL[6]; /*!< [0x0164~0x178] EPWM Fault Detect Control Register 0~5 */ + __IO uint32_t FDIEN; /*!< [0x017C] EPWM Fault Detect Interrupt Enable Register */ + __IO uint32_t FDSTS; /*!< [0x0180] EPWM Fault Detect Interrupt Flag Register */ + __IO uint32_t EADCPSCCTL; /*!< [0x0184] EPWM Trigger EADC Prescale Control Register */ + __IO uint32_t EADCPSC0; /*!< [0x0188] EPWM Trigger EADC Prescale Register 0 */ + __IO uint32_t EADCPSC1; /*!< [0x018C] EPWM Trigger EADC Prescale Register 1 */ + __IO uint32_t EADCPSCNT0; /*!< [0x0190] EPWM Trigger EADC Prescale Counter Register 0 */ + __IO uint32_t EADCPSCNT1; /*!< [0x0194] EPWM Trigger EADC Prescale Counter Register 1 */ + __I uint32_t RESERVE11[26]; + __IO uint32_t CAPINEN; /*!< [0x0200] EPWM Capture Input Enable Register */ + __IO uint32_t CAPCTL; /*!< [0x0204] EPWM Capture Control Register */ + __I uint32_t CAPSTS; /*!< [0x0208] EPWM Capture Status Register */ + ECAPDAT_T CAPDAT[6]; /*!< [0x020c~0x0238] EPWM Rising and Falling Capture Data Register 0~5 */ + __IO uint32_t PDMACTL; /*!< [0x023c] EPWM PDMA Control Register */ + __I uint32_t PDMACAP[3]; /*!< [0x0240~0x248] EPWM Capture Channel 0_1,2_3,4_5 PDMA Register */ + __I uint32_t RESERVE12[1]; + __IO uint32_t CAPIEN; /*!< [0x0250] EPWM Capture Interrupt Enable Register */ + __IO uint32_t CAPIF; /*!< [0x0254] EPWM Capture Interrupt Flag Register */ + __I uint32_t RESERVE13[43]; + __I uint32_t PBUF[6]; /*!< [0x0304~0x0318 EPWM PERIOD0~5 Buffer */ + __I uint32_t CMPBUF[6]; /*!< [0x031C~0x0330 EPWM CMPDAT0~5 Buffer */ + __I uint32_t CPSCBUF[3]; /*!< [0x0334~0x33c] EPWM CLKPSC0_1,2_3,4_5 Buffer */ + __I uint32_t FTCBUF[3]; /*!< [0x0340~0x348] EPWM FTCMPDAT0_1,2_3,4_5 Buffer */ + __IO uint32_t FTCI; /*!< [0x034c] EPWM FTCMPDAT Indicator Register */ + +} EPWM_T; + +/** + @addtogroup EPWM_CONST EPWM Bit Field Definition + Constant Definitions for EPWM Controller + @{ +*/ + +#define EPWM_CTL0_CTRLD0_Pos (0) /*!< EPWM_T::CTL0: CTRLD0 Position */ +#define EPWM_CTL0_CTRLD0_Msk (0x1ul << EPWM_CTL0_CTRLD0_Pos) /*!< EPWM_T::CTL0: CTRLD0 Mask */ + +#define EPWM_CTL0_CTRLD1_Pos (1) /*!< EPWM_T::CTL0: CTRLD1 Position */ +#define EPWM_CTL0_CTRLD1_Msk (0x1ul << EPWM_CTL0_CTRLD1_Pos) /*!< EPWM_T::CTL0: CTRLD1 Mask */ + +#define EPWM_CTL0_CTRLD2_Pos (2) /*!< EPWM_T::CTL0: CTRLD2 Position */ +#define EPWM_CTL0_CTRLD2_Msk (0x1ul << EPWM_CTL0_CTRLD2_Pos) /*!< EPWM_T::CTL0: CTRLD2 Mask */ + +#define EPWM_CTL0_CTRLD3_Pos (3) /*!< EPWM_T::CTL0: CTRLD3 Position */ +#define EPWM_CTL0_CTRLD3_Msk (0x1ul << EPWM_CTL0_CTRLD3_Pos) /*!< EPWM_T::CTL0: CTRLD3 Mask */ + +#define EPWM_CTL0_CTRLD4_Pos (4) /*!< EPWM_T::CTL0: CTRLD4 Position */ +#define EPWM_CTL0_CTRLD4_Msk (0x1ul << EPWM_CTL0_CTRLD4_Pos) /*!< EPWM_T::CTL0: CTRLD4 Mask */ + +#define EPWM_CTL0_CTRLD5_Pos (5) /*!< EPWM_T::CTL0: CTRLD5 Position */ +#define EPWM_CTL0_CTRLD5_Msk (0x1ul << EPWM_CTL0_CTRLD5_Pos) /*!< EPWM_T::CTL0: CTRLD5 Mask */ + +#define EPWM_CTL0_WINLDEN0_Pos (8) /*!< EPWM_T::CTL0: WINLDEN0 Position */ +#define EPWM_CTL0_WINLDEN0_Msk (0x1ul << EPWM_CTL0_WINLDEN0_Pos) /*!< EPWM_T::CTL0: WINLDEN0 Mask */ + +#define EPWM_CTL0_WINLDEN1_Pos (9) /*!< EPWM_T::CTL0: WINLDEN1 Position */ +#define EPWM_CTL0_WINLDEN1_Msk (0x1ul << EPWM_CTL0_WINLDEN1_Pos) /*!< EPWM_T::CTL0: WINLDEN1 Mask */ + +#define EPWM_CTL0_WINLDEN2_Pos (10) /*!< EPWM_T::CTL0: WINLDEN2 Position */ +#define EPWM_CTL0_WINLDEN2_Msk (0x1ul << EPWM_CTL0_WINLDEN2_Pos) /*!< EPWM_T::CTL0: WINLDEN2 Mask */ + +#define EPWM_CTL0_WINLDEN3_Pos (11) /*!< EPWM_T::CTL0: WINLDEN3 Position */ +#define EPWM_CTL0_WINLDEN3_Msk (0x1ul << EPWM_CTL0_WINLDEN3_Pos) /*!< EPWM_T::CTL0: WINLDEN3 Mask */ + +#define EPWM_CTL0_WINLDEN4_Pos (12) /*!< EPWM_T::CTL0: WINLDEN4 Position */ +#define EPWM_CTL0_WINLDEN4_Msk (0x1ul << EPWM_CTL0_WINLDEN4_Pos) /*!< EPWM_T::CTL0: WINLDEN4 Mask */ + +#define EPWM_CTL0_WINLDEN5_Pos (13) /*!< EPWM_T::CTL0: WINLDEN5 Position */ +#define EPWM_CTL0_WINLDEN5_Msk (0x1ul << EPWM_CTL0_WINLDEN5_Pos) /*!< EPWM_T::CTL0: WINLDEN5 Mask */ + +#define EPWM_CTL0_IMMLDEN0_Pos (16) /*!< EPWM_T::CTL0: IMMLDEN0 Position */ +#define EPWM_CTL0_IMMLDEN0_Msk (0x1ul << EPWM_CTL0_IMMLDEN0_Pos) /*!< EPWM_T::CTL0: IMMLDEN0 Mask */ + +#define EPWM_CTL0_IMMLDEN1_Pos (17) /*!< EPWM_T::CTL0: IMMLDEN1 Position */ +#define EPWM_CTL0_IMMLDEN1_Msk (0x1ul << EPWM_CTL0_IMMLDEN1_Pos) /*!< EPWM_T::CTL0: IMMLDEN1 Mask */ + +#define EPWM_CTL0_IMMLDEN2_Pos (18) /*!< EPWM_T::CTL0: IMMLDEN2 Position */ +#define EPWM_CTL0_IMMLDEN2_Msk (0x1ul << EPWM_CTL0_IMMLDEN2_Pos) /*!< EPWM_T::CTL0: IMMLDEN2 Mask */ + +#define EPWM_CTL0_IMMLDEN3_Pos (19) /*!< EPWM_T::CTL0: IMMLDEN3 Position */ +#define EPWM_CTL0_IMMLDEN3_Msk (0x1ul << EPWM_CTL0_IMMLDEN3_Pos) /*!< EPWM_T::CTL0: IMMLDEN3 Mask */ + +#define EPWM_CTL0_IMMLDEN4_Pos (20) /*!< EPWM_T::CTL0: IMMLDEN4 Position */ +#define EPWM_CTL0_IMMLDEN4_Msk (0x1ul << EPWM_CTL0_IMMLDEN4_Pos) /*!< EPWM_T::CTL0: IMMLDEN4 Mask */ + +#define EPWM_CTL0_IMMLDEN5_Pos (21) /*!< EPWM_T::CTL0: IMMLDEN5 Position */ +#define EPWM_CTL0_IMMLDEN5_Msk (0x1ul << EPWM_CTL0_IMMLDEN5_Pos) /*!< EPWM_T::CTL0: IMMLDEN5 Mask */ + +#define EPWM_CTL0_GROUPEN_Pos (24) /*!< EPWM_T::CTL0: GROUPEN Position */ +#define EPWM_CTL0_GROUPEN_Msk (0x1ul << EPWM_CTL0_GROUPEN_Pos) /*!< EPWM_T::CTL0: GROUPEN Mask */ + +#define EPWM_CTL0_DBGHALT_Pos (30) /*!< EPWM_T::CTL0: DBGHALT Position */ +#define EPWM_CTL0_DBGHALT_Msk (0x1ul << EPWM_CTL0_DBGHALT_Pos) /*!< EPWM_T::CTL0: DBGHALT Mask */ + +#define EPWM_CTL0_DBGTRIOFF_Pos (31) /*!< EPWM_T::CTL0: DBGTRIOFF Position */ +#define EPWM_CTL0_DBGTRIOFF_Msk (0x1ul << EPWM_CTL0_DBGTRIOFF_Pos) /*!< EPWM_T::CTL0: DBGTRIOFF Mask */ + +#define EPWM_CTL1_CNTTYPE0_Pos (0) /*!< EPWM_T::CTL1: CNTTYPE0 Position */ +#define EPWM_CTL1_CNTTYPE0_Msk (0x3ul << EPWM_CTL1_CNTTYPE0_Pos) /*!< EPWM_T::CTL1: CNTTYPE0 Mask */ + +#define EPWM_CTL1_CNTTYPE1_Pos (2) /*!< EPWM_T::CTL1: CNTTYPE1 Position */ +#define EPWM_CTL1_CNTTYPE1_Msk (0x3ul << EPWM_CTL1_CNTTYPE1_Pos) /*!< EPWM_T::CTL1: CNTTYPE1 Mask */ + +#define EPWM_CTL1_CNTTYPE2_Pos (4) /*!< EPWM_T::CTL1: CNTTYPE2 Position */ +#define EPWM_CTL1_CNTTYPE2_Msk (0x3ul << EPWM_CTL1_CNTTYPE2_Pos) /*!< EPWM_T::CTL1: CNTTYPE2 Mask */ + +#define EPWM_CTL1_CNTTYPE3_Pos (6) /*!< EPWM_T::CTL1: CNTTYPE3 Position */ +#define EPWM_CTL1_CNTTYPE3_Msk (0x3ul << EPWM_CTL1_CNTTYPE3_Pos) /*!< EPWM_T::CTL1: CNTTYPE3 Mask */ + +#define EPWM_CTL1_CNTTYPE4_Pos (8) /*!< EPWM_T::CTL1: CNTTYPE4 Position */ +#define EPWM_CTL1_CNTTYPE4_Msk (0x3ul << EPWM_CTL1_CNTTYPE4_Pos) /*!< EPWM_T::CTL1: CNTTYPE4 Mask */ + +#define EPWM_CTL1_CNTTYPE5_Pos (10) /*!< EPWM_T::CTL1: CNTTYPE5 Position */ +#define EPWM_CTL1_CNTTYPE5_Msk (0x3ul << EPWM_CTL1_CNTTYPE5_Pos) /*!< EPWM_T::CTL1: CNTTYPE5 Mask */ + +#define EPWM_CTL1_CNTMODE0_Pos (16) /*!< EPWM_T::CTL1: CNTMODE0 Position */ +#define EPWM_CTL1_CNTMODE0_Msk (0x1ul << EPWM_CTL1_CNTMODE0_Pos) /*!< EPWM_T::CTL1: CNTMODE0 Mask */ + +#define EPWM_CTL1_CNTMODE1_Pos (17) /*!< EPWM_T::CTL1: CNTMODE1 Position */ +#define EPWM_CTL1_CNTMODE1_Msk (0x1ul << EPWM_CTL1_CNTMODE1_Pos) /*!< EPWM_T::CTL1: CNTMODE1 Mask */ + +#define EPWM_CTL1_CNTMODE2_Pos (18) /*!< EPWM_T::CTL1: CNTMODE2 Position */ +#define EPWM_CTL1_CNTMODE2_Msk (0x1ul << EPWM_CTL1_CNTMODE2_Pos) /*!< EPWM_T::CTL1: CNTMODE2 Mask */ + +#define EPWM_CTL1_CNTMODE3_Pos (19) /*!< EPWM_T::CTL1: CNTMODE3 Position */ +#define EPWM_CTL1_CNTMODE3_Msk (0x1ul << EPWM_CTL1_CNTMODE3_Pos) /*!< EPWM_T::CTL1: CNTMODE3 Mask */ + +#define EPWM_CTL1_CNTMODE4_Pos (20) /*!< EPWM_T::CTL1: CNTMODE4 Position */ +#define EPWM_CTL1_CNTMODE4_Msk (0x1ul << EPWM_CTL1_CNTMODE4_Pos) /*!< EPWM_T::CTL1: CNTMODE4 Mask */ + +#define EPWM_CTL1_CNTMODE5_Pos (21) /*!< EPWM_T::CTL1: CNTMODE5 Position */ +#define EPWM_CTL1_CNTMODE5_Msk (0x1ul << EPWM_CTL1_CNTMODE5_Pos) /*!< EPWM_T::CTL1: CNTMODE5 Mask */ + +#define EPWM_CTL1_OUTMODE0_Pos (24) /*!< EPWM_T::CTL1: OUTMODE0 Position */ +#define EPWM_CTL1_OUTMODE0_Msk (0x1ul << EPWM_CTL1_OUTMODE0_Pos) /*!< EPWM_T::CTL1: OUTMODE0 Mask */ + +#define EPWM_CTL1_OUTMODE2_Pos (25) /*!< EPWM_T::CTL1: OUTMODE2 Position */ +#define EPWM_CTL1_OUTMODE2_Msk (0x1ul << EPWM_CTL1_OUTMODE2_Pos) /*!< EPWM_T::CTL1: OUTMODE2 Mask */ + +#define EPWM_CTL1_OUTMODE4_Pos (26) /*!< EPWM_T::CTL1: OUTMODE4 Position */ +#define EPWM_CTL1_OUTMODE4_Msk (0x1ul << EPWM_CTL1_OUTMODE4_Pos) /*!< EPWM_T::CTL1: OUTMODE4 Mask */ + +#define EPWM_SYNC_PHSEN0_Pos (0) /*!< EPWM_T::SYNC: PHSEN0 Position */ +#define EPWM_SYNC_PHSEN0_Msk (0x1ul << EPWM_SYNC_PHSEN0_Pos) /*!< EPWM_T::SYNC: PHSEN0 Mask */ + +#define EPWM_SYNC_PHSEN2_Pos (1) /*!< EPWM_T::SYNC: PHSEN2 Position */ +#define EPWM_SYNC_PHSEN2_Msk (0x1ul << EPWM_SYNC_PHSEN2_Pos) /*!< EPWM_T::SYNC: PHSEN2 Mask */ + +#define EPWM_SYNC_PHSEN4_Pos (2) /*!< EPWM_T::SYNC: PHSEN4 Position */ +#define EPWM_SYNC_PHSEN4_Msk (0x1ul << EPWM_SYNC_PHSEN4_Pos) /*!< EPWM_T::SYNC: PHSEN4 Mask */ + +#define EPWM_SYNC_SINSRC0_Pos (8) /*!< EPWM_T::SYNC: SINSRC0 Position */ +#define EPWM_SYNC_SINSRC0_Msk (0x3ul << EPWM_SYNC_SINSRC0_Pos) /*!< EPWM_T::SYNC: SINSRC0 Mask */ + +#define EPWM_SYNC_SINSRC2_Pos (10) /*!< EPWM_T::SYNC: SINSRC2 Position */ +#define EPWM_SYNC_SINSRC2_Msk (0x3ul << EPWM_SYNC_SINSRC2_Pos) /*!< EPWM_T::SYNC: SINSRC2 Mask */ + +#define EPWM_SYNC_SINSRC4_Pos (12) /*!< EPWM_T::SYNC: SINSRC4 Position */ +#define EPWM_SYNC_SINSRC4_Msk (0x3ul << EPWM_SYNC_SINSRC4_Pos) /*!< EPWM_T::SYNC: SINSRC4 Mask */ + +#define EPWM_SYNC_SNFLTEN_Pos (16) /*!< EPWM_T::SYNC: SNFLTEN Position */ +#define EPWM_SYNC_SNFLTEN_Msk (0x1ul << EPWM_SYNC_SNFLTEN_Pos) /*!< EPWM_T::SYNC: SNFLTEN Mask */ + +#define EPWM_SYNC_SFLTCSEL_Pos (17) /*!< EPWM_T::SYNC: SFLTCSEL Position */ +#define EPWM_SYNC_SFLTCSEL_Msk (0x7ul << EPWM_SYNC_SFLTCSEL_Pos) /*!< EPWM_T::SYNC: SFLTCSEL Mask */ + +#define EPWM_SYNC_SFLTCNT_Pos (20) /*!< EPWM_T::SYNC: SFLTCNT Position */ +#define EPWM_SYNC_SFLTCNT_Msk (0x7ul << EPWM_SYNC_SFLTCNT_Pos) /*!< EPWM_T::SYNC: SFLTCNT Mask */ + +#define EPWM_SYNC_SINPINV_Pos (23) /*!< EPWM_T::SYNC: SINPINV Position */ +#define EPWM_SYNC_SINPINV_Msk (0x1ul << EPWM_SYNC_SINPINV_Pos) /*!< EPWM_T::SYNC: SINPINV Mask */ + +#define EPWM_SYNC_PHSDIR0_Pos (24) /*!< EPWM_T::SYNC: PHSDIR0 Position */ +#define EPWM_SYNC_PHSDIR0_Msk (0x1ul << EPWM_SYNC_PHSDIR0_Pos) /*!< EPWM_T::SYNC: PHSDIR0 Mask */ + +#define EPWM_SYNC_PHSDIR2_Pos (25) /*!< EPWM_T::SYNC: PHSDIR2 Position */ +#define EPWM_SYNC_PHSDIR2_Msk (0x1ul << EPWM_SYNC_PHSDIR2_Pos) /*!< EPWM_T::SYNC: PHSDIR2 Mask */ + +#define EPWM_SYNC_PHSDIR4_Pos (26) /*!< EPWM_T::SYNC: PHSDIR4 Position */ +#define EPWM_SYNC_PHSDIR4_Msk (0x1ul << EPWM_SYNC_PHSDIR4_Pos) /*!< EPWM_T::SYNC: PHSDIR4 Mask */ + +#define EPWM_SWSYNC_SWSYNC0_Pos (0) /*!< EPWM_T::SWSYNC: SWSYNC0 Position */ +#define EPWM_SWSYNC_SWSYNC0_Msk (0x1ul << EPWM_SWSYNC_SWSYNC0_Pos) /*!< EPWM_T::SWSYNC: SWSYNC0 Mask */ + +#define EPWM_SWSYNC_SWSYNC2_Pos (1) /*!< EPWM_T::SWSYNC: SWSYNC2 Position */ +#define EPWM_SWSYNC_SWSYNC2_Msk (0x1ul << EPWM_SWSYNC_SWSYNC2_Pos) /*!< EPWM_T::SWSYNC: SWSYNC2 Mask */ + +#define EPWM_SWSYNC_SWSYNC4_Pos (2) /*!< EPWM_T::SWSYNC: SWSYNC4 Position */ +#define EPWM_SWSYNC_SWSYNC4_Msk (0x1ul << EPWM_SWSYNC_SWSYNC4_Pos) /*!< EPWM_T::SWSYNC: SWSYNC4 Mask */ + +#define EPWM_CLKSRC_ECLKSRC0_Pos (0) /*!< EPWM_T::CLKSRC: ECLKSRC0 Position */ +#define EPWM_CLKSRC_ECLKSRC0_Msk (0x7ul << EPWM_CLKSRC_ECLKSRC0_Pos) /*!< EPWM_T::CLKSRC: ECLKSRC0 Mask */ + +#define EPWM_CLKSRC_ECLKSRC2_Pos (8) /*!< EPWM_T::CLKSRC: ECLKSRC2 Position */ +#define EPWM_CLKSRC_ECLKSRC2_Msk (0x7ul << EPWM_CLKSRC_ECLKSRC2_Pos) /*!< EPWM_T::CLKSRC: ECLKSRC2 Mask */ + +#define EPWM_CLKSRC_ECLKSRC4_Pos (16) /*!< EPWM_T::CLKSRC: ECLKSRC4 Position */ +#define EPWM_CLKSRC_ECLKSRC4_Msk (0x7ul << EPWM_CLKSRC_ECLKSRC4_Pos) /*!< EPWM_T::CLKSRC: ECLKSRC4 Mask */ + +#define EPWM_CLKPSC0_1_CLKPSC_Pos (0) /*!< EPWM_T::CLKPSC0_1: CLKPSC Position */ +#define EPWM_CLKPSC0_1_CLKPSC_Msk (0xffful << EPWM_CLKPSC0_1_CLKPSC_Pos) /*!< EPWM_T::CLKPSC0_1: CLKPSC Mask */ + +#define EPWM_CLKPSC2_3_CLKPSC_Pos (0) /*!< EPWM_T::CLKPSC2_3: CLKPSC Position */ +#define EPWM_CLKPSC2_3_CLKPSC_Msk (0xffful << EPWM_CLKPSC2_3_CLKPSC_Pos) /*!< EPWM_T::CLKPSC2_3: CLKPSC Mask */ + +#define EPWM_CLKPSC4_5_CLKPSC_Pos (0) /*!< EPWM_T::CLKPSC4_5: CLKPSC Position */ +#define EPWM_CLKPSC4_5_CLKPSC_Msk (0xffful << EPWM_CLKPSC4_5_CLKPSC_Pos) /*!< EPWM_T::CLKPSC4_5: CLKPSC Mask */ + +#define EPWM_CNTEN_CNTEN0_Pos (0) /*!< EPWM_T::CNTEN: CNTEN0 Position */ +#define EPWM_CNTEN_CNTEN0_Msk (0x1ul << EPWM_CNTEN_CNTEN0_Pos) /*!< EPWM_T::CNTEN: CNTEN0 Mask */ + +#define EPWM_CNTEN_CNTEN1_Pos (1) /*!< EPWM_T::CNTEN: CNTEN1 Position */ +#define EPWM_CNTEN_CNTEN1_Msk (0x1ul << EPWM_CNTEN_CNTEN1_Pos) /*!< EPWM_T::CNTEN: CNTEN1 Mask */ + +#define EPWM_CNTEN_CNTEN2_Pos (2) /*!< EPWM_T::CNTEN: CNTEN2 Position */ +#define EPWM_CNTEN_CNTEN2_Msk (0x1ul << EPWM_CNTEN_CNTEN2_Pos) /*!< EPWM_T::CNTEN: CNTEN2 Mask */ + +#define EPWM_CNTEN_CNTEN3_Pos (3) /*!< EPWM_T::CNTEN: CNTEN3 Position */ +#define EPWM_CNTEN_CNTEN3_Msk (0x1ul << EPWM_CNTEN_CNTEN3_Pos) /*!< EPWM_T::CNTEN: CNTEN3 Mask */ + +#define EPWM_CNTEN_CNTEN4_Pos (4) /*!< EPWM_T::CNTEN: CNTEN4 Position */ +#define EPWM_CNTEN_CNTEN4_Msk (0x1ul << EPWM_CNTEN_CNTEN4_Pos) /*!< EPWM_T::CNTEN: CNTEN4 Mask */ + +#define EPWM_CNTEN_CNTEN5_Pos (5) /*!< EPWM_T::CNTEN: CNTEN5 Position */ +#define EPWM_CNTEN_CNTEN5_Msk (0x1ul << EPWM_CNTEN_CNTEN5_Pos) /*!< EPWM_T::CNTEN: CNTEN5 Mask */ + +#define EPWM_CNTCLR_CNTCLR0_Pos (0) /*!< EPWM_T::CNTCLR: CNTCLR0 Position */ +#define EPWM_CNTCLR_CNTCLR0_Msk (0x1ul << EPWM_CNTCLR_CNTCLR0_Pos) /*!< EPWM_T::CNTCLR: CNTCLR0 Mask */ + +#define EPWM_CNTCLR_CNTCLR1_Pos (1) /*!< EPWM_T::CNTCLR: CNTCLR1 Position */ +#define EPWM_CNTCLR_CNTCLR1_Msk (0x1ul << EPWM_CNTCLR_CNTCLR1_Pos) /*!< EPWM_T::CNTCLR: CNTCLR1 Mask */ + +#define EPWM_CNTCLR_CNTCLR2_Pos (2) /*!< EPWM_T::CNTCLR: CNTCLR2 Position */ +#define EPWM_CNTCLR_CNTCLR2_Msk (0x1ul << EPWM_CNTCLR_CNTCLR2_Pos) /*!< EPWM_T::CNTCLR: CNTCLR2 Mask */ + +#define EPWM_CNTCLR_CNTCLR3_Pos (3) /*!< EPWM_T::CNTCLR: CNTCLR3 Position */ +#define EPWM_CNTCLR_CNTCLR3_Msk (0x1ul << EPWM_CNTCLR_CNTCLR3_Pos) /*!< EPWM_T::CNTCLR: CNTCLR3 Mask */ + +#define EPWM_CNTCLR_CNTCLR4_Pos (4) /*!< EPWM_T::CNTCLR: CNTCLR4 Position */ +#define EPWM_CNTCLR_CNTCLR4_Msk (0x1ul << EPWM_CNTCLR_CNTCLR4_Pos) /*!< EPWM_T::CNTCLR: CNTCLR4 Mask */ + +#define EPWM_CNTCLR_CNTCLR5_Pos (5) /*!< EPWM_T::CNTCLR: CNTCLR5 Position */ +#define EPWM_CNTCLR_CNTCLR5_Msk (0x1ul << EPWM_CNTCLR_CNTCLR5_Pos) /*!< EPWM_T::CNTCLR: CNTCLR5 Mask */ + +#define EPWM_LOAD_LOAD0_Pos (0) /*!< EPWM_T::LOAD: LOAD0 Position */ +#define EPWM_LOAD_LOAD0_Msk (0x1ul << EPWM_LOAD_LOAD0_Pos) /*!< EPWM_T::LOAD: LOAD0 Mask */ + +#define EPWM_LOAD_LOAD1_Pos (1) /*!< EPWM_T::LOAD: LOAD1 Position */ +#define EPWM_LOAD_LOAD1_Msk (0x1ul << EPWM_LOAD_LOAD1_Pos) /*!< EPWM_T::LOAD: LOAD1 Mask */ + +#define EPWM_LOAD_LOAD2_Pos (2) /*!< EPWM_T::LOAD: LOAD2 Position */ +#define EPWM_LOAD_LOAD2_Msk (0x1ul << EPWM_LOAD_LOAD2_Pos) /*!< EPWM_T::LOAD: LOAD2 Mask */ + +#define EPWM_LOAD_LOAD3_Pos (3) /*!< EPWM_T::LOAD: LOAD3 Position */ +#define EPWM_LOAD_LOAD3_Msk (0x1ul << EPWM_LOAD_LOAD3_Pos) /*!< EPWM_T::LOAD: LOAD3 Mask */ + +#define EPWM_LOAD_LOAD4_Pos (4) /*!< EPWM_T::LOAD: LOAD4 Position */ +#define EPWM_LOAD_LOAD4_Msk (0x1ul << EPWM_LOAD_LOAD4_Pos) /*!< EPWM_T::LOAD: LOAD4 Mask */ + +#define EPWM_LOAD_LOAD5_Pos (5) /*!< EPWM_T::LOAD: LOAD5 Position */ +#define EPWM_LOAD_LOAD5_Msk (0x1ul << EPWM_LOAD_LOAD5_Pos) /*!< EPWM_T::LOAD: LOAD5 Mask */ + +#define EPWM_PERIOD0_PERIOD_Pos (0) /*!< EPWM_T::PERIOD0: PERIOD Position */ +#define EPWM_PERIOD0_PERIOD_Msk (0xfffful << EPWM_PERIOD0_PERIOD_Pos) /*!< EPWM_T::PERIOD0: PERIOD Mask */ + +#define EPWM_PERIOD1_PERIOD_Pos (0) /*!< EPWM_T::PERIOD1: PERIOD Position */ +#define EPWM_PERIOD1_PERIOD_Msk (0xfffful << EPWM_PERIOD1_PERIOD_Pos) /*!< EPWM_T::PERIOD1: PERIOD Mask */ + +#define EPWM_PERIOD2_PERIOD_Pos (0) /*!< EPWM_T::PERIOD2: PERIOD Position */ +#define EPWM_PERIOD2_PERIOD_Msk (0xfffful << EPWM_PERIOD2_PERIOD_Pos) /*!< EPWM_T::PERIOD2: PERIOD Mask */ + +#define EPWM_PERIOD3_PERIOD_Pos (0) /*!< EPWM_T::PERIOD3: PERIOD Position */ +#define EPWM_PERIOD3_PERIOD_Msk (0xfffful << EPWM_PERIOD3_PERIOD_Pos) /*!< EPWM_T::PERIOD3: PERIOD Mask */ + +#define EPWM_PERIOD4_PERIOD_Pos (0) /*!< EPWM_T::PERIOD4: PERIOD Position */ +#define EPWM_PERIOD4_PERIOD_Msk (0xfffful << EPWM_PERIOD4_PERIOD_Pos) /*!< EPWM_T::PERIOD4: PERIOD Mask */ + +#define EPWM_PERIOD5_PERIOD_Pos (0) /*!< EPWM_T::PERIOD5: PERIOD Position */ +#define EPWM_PERIOD5_PERIOD_Msk (0xfffful << EPWM_PERIOD5_PERIOD_Pos) /*!< EPWM_T::PERIOD5: PERIOD Mask */ + +#define EPWM_CMPDAT0_CMP_Pos (0) /*!< EPWM_T::CMPDAT0: CMP Position */ +#define EPWM_CMPDAT0_CMP_Msk (0xfffful << EPWM_CMPDAT0_CMP_Pos) /*!< EPWM_T::CMPDAT0: CMP Mask */ + +#define EPWM_CMPDAT1_CMP_Pos (0) /*!< EPWM_T::CMPDAT1: CMP Position */ +#define EPWM_CMPDAT1_CMP_Msk (0xfffful << EPWM_CMPDAT1_CMP_Pos) /*!< EPWM_T::CMPDAT1: CMP Mask */ + +#define EPWM_CMPDAT2_CMP_Pos (0) /*!< EPWM_T::CMPDAT2: CMP Position */ +#define EPWM_CMPDAT2_CMP_Msk (0xfffful << EPWM_CMPDAT2_CMP_Pos) /*!< EPWM_T::CMPDAT2: CMP Mask */ + +#define EPWM_CMPDAT3_CMP_Pos (0) /*!< EPWM_T::CMPDAT3: CMP Position */ +#define EPWM_CMPDAT3_CMP_Msk (0xfffful << EPWM_CMPDAT3_CMP_Pos) /*!< EPWM_T::CMPDAT3: CMP Mask */ + +#define EPWM_CMPDAT4_CMP_Pos (0) /*!< EPWM_T::CMPDAT4: CMP Position */ +#define EPWM_CMPDAT4_CMP_Msk (0xfffful << EPWM_CMPDAT4_CMP_Pos) /*!< EPWM_T::CMPDAT4: CMP Mask */ + +#define EPWM_CMPDAT5_CMP_Pos (0) /*!< EPWM_T::CMPDAT5: CMP Position */ +#define EPWM_CMPDAT5_CMP_Msk (0xfffful << EPWM_CMPDAT5_CMP_Pos) /*!< EPWM_T::CMPDAT5: CMP Mask */ + +#define EPWM_DTCTL0_1_DTCNT_Pos (0) /*!< EPWM_T::DTCTL0_1: DTCNT Position */ +#define EPWM_DTCTL0_1_DTCNT_Msk (0xffful << EPWM_DTCTL0_1_DTCNT_Pos) /*!< EPWM_T::DTCTL0_1: DTCNT Mask */ + +#define EPWM_DTCTL0_1_DTEN_Pos (16) /*!< EPWM_T::DTCTL0_1: DTEN Position */ +#define EPWM_DTCTL0_1_DTEN_Msk (0x1ul << EPWM_DTCTL0_1_DTEN_Pos) /*!< EPWM_T::DTCTL0_1: DTEN Mask */ + +#define EPWM_DTCTL0_1_DTCKSEL_Pos (24) /*!< EPWM_T::DTCTL0_1: DTCKSEL Position */ +#define EPWM_DTCTL0_1_DTCKSEL_Msk (0x1ul << EPWM_DTCTL0_1_DTCKSEL_Pos) /*!< EPWM_T::DTCTL0_1: DTCKSEL Mask */ + +#define EPWM_DTCTL2_3_DTCNT_Pos (0) /*!< EPWM_T::DTCTL2_3: DTCNT Position */ +#define EPWM_DTCTL2_3_DTCNT_Msk (0xffful << EPWM_DTCTL2_3_DTCNT_Pos) /*!< EPWM_T::DTCTL2_3: DTCNT Mask */ + +#define EPWM_DTCTL2_3_DTEN_Pos (16) /*!< EPWM_T::DTCTL2_3: DTEN Position */ +#define EPWM_DTCTL2_3_DTEN_Msk (0x1ul << EPWM_DTCTL2_3_DTEN_Pos) /*!< EPWM_T::DTCTL2_3: DTEN Mask */ + +#define EPWM_DTCTL2_3_DTCKSEL_Pos (24) /*!< EPWM_T::DTCTL2_3: DTCKSEL Position */ +#define EPWM_DTCTL2_3_DTCKSEL_Msk (0x1ul << EPWM_DTCTL2_3_DTCKSEL_Pos) /*!< EPWM_T::DTCTL2_3: DTCKSEL Mask */ + +#define EPWM_DTCTL4_5_DTCNT_Pos (0) /*!< EPWM_T::DTCTL4_5: DTCNT Position */ +#define EPWM_DTCTL4_5_DTCNT_Msk (0xffful << EPWM_DTCTL4_5_DTCNT_Pos) /*!< EPWM_T::DTCTL4_5: DTCNT Mask */ + +#define EPWM_DTCTL4_5_DTEN_Pos (16) /*!< EPWM_T::DTCTL4_5: DTEN Position */ +#define EPWM_DTCTL4_5_DTEN_Msk (0x1ul << EPWM_DTCTL4_5_DTEN_Pos) /*!< EPWM_T::DTCTL4_5: DTEN Mask */ + +#define EPWM_DTCTL4_5_DTCKSEL_Pos (24) /*!< EPWM_T::DTCTL4_5: DTCKSEL Position */ +#define EPWM_DTCTL4_5_DTCKSEL_Msk (0x1ul << EPWM_DTCTL4_5_DTCKSEL_Pos) /*!< EPWM_T::DTCTL4_5: DTCKSEL Mask */ + +#define EPWM_PHS0_1_PHS_Pos (0) /*!< EPWM_T::PHS0_1: PHS Position */ +#define EPWM_PHS0_1_PHS_Msk (0xfffful << EPWM_PHS0_1_PHS_Pos) /*!< EPWM_T::PHS0_1: PHS Mask */ + +#define EPWM_PHS2_3_PHS_Pos (0) /*!< EPWM_T::PHS2_3: PHS Position */ +#define EPWM_PHS2_3_PHS_Msk (0xfffful << EPWM_PHS2_3_PHS_Pos) /*!< EPWM_T::PHS2_3: PHS Mask */ + +#define EPWM_PHS4_5_PHS_Pos (0) /*!< EPWM_T::PHS4_5: PHS Position */ +#define EPWM_PHS4_5_PHS_Msk (0xfffful << EPWM_PHS4_5_PHS_Pos) /*!< EPWM_T::PHS4_5: PHS Mask */ + +#define EPWM_CNT0_CNT_Pos (0) /*!< EPWM_T::CNT0: CNT Position */ +#define EPWM_CNT0_CNT_Msk (0xfffful << EPWM_CNT0_CNT_Pos) /*!< EPWM_T::CNT0: CNT Mask */ + +#define EPWM_CNT0_DIRF_Pos (16) /*!< EPWM_T::CNT0: DIRF Position */ +#define EPWM_CNT0_DIRF_Msk (0x1ul << EPWM_CNT0_DIRF_Pos) /*!< EPWM_T::CNT0: DIRF Mask */ + +#define EPWM_CNT1_CNT_Pos (0) /*!< EPWM_T::CNT1: CNT Position */ +#define EPWM_CNT1_CNT_Msk (0xfffful << EPWM_CNT1_CNT_Pos) /*!< EPWM_T::CNT1: CNT Mask */ + +#define EPWM_CNT1_DIRF_Pos (16) /*!< EPWM_T::CNT1: DIRF Position */ +#define EPWM_CNT1_DIRF_Msk (0x1ul << EPWM_CNT1_DIRF_Pos) /*!< EPWM_T::CNT1: DIRF Mask */ + +#define EPWM_CNT2_CNT_Pos (0) /*!< EPWM_T::CNT2: CNT Position */ +#define EPWM_CNT2_CNT_Msk (0xfffful << EPWM_CNT2_CNT_Pos) /*!< EPWM_T::CNT2: CNT Mask */ + +#define EPWM_CNT2_DIRF_Pos (16) /*!< EPWM_T::CNT2: DIRF Position */ +#define EPWM_CNT2_DIRF_Msk (0x1ul << EPWM_CNT2_DIRF_Pos) /*!< EPWM_T::CNT2: DIRF Mask */ + +#define EPWM_CNT3_CNT_Pos (0) /*!< EPWM_T::CNT3: CNT Position */ +#define EPWM_CNT3_CNT_Msk (0xfffful << EPWM_CNT3_CNT_Pos) /*!< EPWM_T::CNT3: CNT Mask */ + +#define EPWM_CNT3_DIRF_Pos (16) /*!< EPWM_T::CNT3: DIRF Position */ +#define EPWM_CNT3_DIRF_Msk (0x1ul << EPWM_CNT3_DIRF_Pos) /*!< EPWM_T::CNT3: DIRF Mask */ + +#define EPWM_CNT4_CNT_Pos (0) /*!< EPWM_T::CNT4: CNT Position */ +#define EPWM_CNT4_CNT_Msk (0xfffful << EPWM_CNT4_CNT_Pos) /*!< EPWM_T::CNT4: CNT Mask */ + +#define EPWM_CNT4_DIRF_Pos (16) /*!< EPWM_T::CNT4: DIRF Position */ +#define EPWM_CNT4_DIRF_Msk (0x1ul << EPWM_CNT4_DIRF_Pos) /*!< EPWM_T::CNT4: DIRF Mask */ + +#define EPWM_CNT5_CNT_Pos (0) /*!< EPWM_T::CNT5: CNT Position */ +#define EPWM_CNT5_CNT_Msk (0xfffful << EPWM_CNT5_CNT_Pos) /*!< EPWM_T::CNT5: CNT Mask */ + +#define EPWM_CNT5_DIRF_Pos (16) /*!< EPWM_T::CNT5: DIRF Position */ +#define EPWM_CNT5_DIRF_Msk (0x1ul << EPWM_CNT5_DIRF_Pos) /*!< EPWM_T::CNT5: DIRF Mask */ + +#define EPWM_WGCTL0_ZPCTL0_Pos (0) /*!< EPWM_T::WGCTL0: ZPCTL0 Position */ +#define EPWM_WGCTL0_ZPCTL0_Msk (0x3ul << EPWM_WGCTL0_ZPCTL0_Pos) /*!< EPWM_T::WGCTL0: ZPCTL0 Mask */ + +#define EPWM_WGCTL0_ZPCTL1_Pos (2) /*!< EPWM_T::WGCTL0: ZPCTL1 Position */ +#define EPWM_WGCTL0_ZPCTL1_Msk (0x3ul << EPWM_WGCTL0_ZPCTL1_Pos) /*!< EPWM_T::WGCTL0: ZPCTL1 Mask */ + +#define EPWM_WGCTL0_ZPCTL2_Pos (4) /*!< EPWM_T::WGCTL0: ZPCTL2 Position */ +#define EPWM_WGCTL0_ZPCTL2_Msk (0x3ul << EPWM_WGCTL0_ZPCTL2_Pos) /*!< EPWM_T::WGCTL0: ZPCTL2 Mask */ + +#define EPWM_WGCTL0_ZPCTL3_Pos (6) /*!< EPWM_T::WGCTL0: ZPCTL3 Position */ +#define EPWM_WGCTL0_ZPCTL3_Msk (0x3ul << EPWM_WGCTL0_ZPCTL3_Pos) /*!< EPWM_T::WGCTL0: ZPCTL3 Mask */ + +#define EPWM_WGCTL0_ZPCTL4_Pos (8) /*!< EPWM_T::WGCTL0: ZPCTL4 Position */ +#define EPWM_WGCTL0_ZPCTL4_Msk (0x3ul << EPWM_WGCTL0_ZPCTL4_Pos) /*!< EPWM_T::WGCTL0: ZPCTL4 Mask */ + +#define EPWM_WGCTL0_ZPCTL5_Pos (10) /*!< EPWM_T::WGCTL0: ZPCTL5 Position */ +#define EPWM_WGCTL0_ZPCTL5_Msk (0x3ul << EPWM_WGCTL0_ZPCTL5_Pos) /*!< EPWM_T::WGCTL0: ZPCTL5 Mask */ + +#define EPWM_WGCTL0_PRDPCTL0_Pos (16) /*!< EPWM_T::WGCTL0: PRDPCTL0 Position */ +#define EPWM_WGCTL0_PRDPCTL0_Msk (0x3ul << EPWM_WGCTL0_PRDPCTL0_Pos) /*!< EPWM_T::WGCTL0: PRDPCTL0 Mask */ + +#define EPWM_WGCTL0_PRDPCTL1_Pos (18) /*!< EPWM_T::WGCTL0: PRDPCTL1 Position */ +#define EPWM_WGCTL0_PRDPCTL1_Msk (0x3ul << EPWM_WGCTL0_PRDPCTL1_Pos) /*!< EPWM_T::WGCTL0: PRDPCTL1 Mask */ + +#define EPWM_WGCTL0_PRDPCTL2_Pos (20) /*!< EPWM_T::WGCTL0: PRDPCTL2 Position */ +#define EPWM_WGCTL0_PRDPCTL2_Msk (0x3ul << EPWM_WGCTL0_PRDPCTL2_Pos) /*!< EPWM_T::WGCTL0: PRDPCTL2 Mask */ + +#define EPWM_WGCTL0_PRDPCTL3_Pos (22) /*!< EPWM_T::WGCTL0: PRDPCTL3 Position */ +#define EPWM_WGCTL0_PRDPCTL3_Msk (0x3ul << EPWM_WGCTL0_PRDPCTL3_Pos) /*!< EPWM_T::WGCTL0: PRDPCTL3 Mask */ + +#define EPWM_WGCTL0_PRDPCTL4_Pos (24) /*!< EPWM_T::WGCTL0: PRDPCTL4 Position */ +#define EPWM_WGCTL0_PRDPCTL4_Msk (0x3ul << EPWM_WGCTL0_PRDPCTL4_Pos) /*!< EPWM_T::WGCTL0: PRDPCTL4 Mask */ + +#define EPWM_WGCTL0_PRDPCTL5_Pos (26) /*!< EPWM_T::WGCTL0: PRDPCTL5 Position */ +#define EPWM_WGCTL0_PRDPCTL5_Msk (0x3ul << EPWM_WGCTL0_PRDPCTL5_Pos) /*!< EPWM_T::WGCTL0: PRDPCTL5 Mask */ + +#define EPWM_WGCTL1_CMPUCTL0_Pos (0) /*!< EPWM_T::WGCTL1: CMPUCTL0 Position */ +#define EPWM_WGCTL1_CMPUCTL0_Msk (0x3ul << EPWM_WGCTL1_CMPUCTL0_Pos) /*!< EPWM_T::WGCTL1: CMPUCTL0 Mask */ + +#define EPWM_WGCTL1_CMPUCTL1_Pos (2) /*!< EPWM_T::WGCTL1: CMPUCTL1 Position */ +#define EPWM_WGCTL1_CMPUCTL1_Msk (0x3ul << EPWM_WGCTL1_CMPUCTL1_Pos) /*!< EPWM_T::WGCTL1: CMPUCTL1 Mask */ + +#define EPWM_WGCTL1_CMPUCTL2_Pos (4) /*!< EPWM_T::WGCTL1: CMPUCTL2 Position */ +#define EPWM_WGCTL1_CMPUCTL2_Msk (0x3ul << EPWM_WGCTL1_CMPUCTL2_Pos) /*!< EPWM_T::WGCTL1: CMPUCTL2 Mask */ + +#define EPWM_WGCTL1_CMPUCTL3_Pos (6) /*!< EPWM_T::WGCTL1: CMPUCTL3 Position */ +#define EPWM_WGCTL1_CMPUCTL3_Msk (0x3ul << EPWM_WGCTL1_CMPUCTL3_Pos) /*!< EPWM_T::WGCTL1: CMPUCTL3 Mask */ + +#define EPWM_WGCTL1_CMPUCTL4_Pos (8) /*!< EPWM_T::WGCTL1: CMPUCTL4 Position */ +#define EPWM_WGCTL1_CMPUCTL4_Msk (0x3ul << EPWM_WGCTL1_CMPUCTL4_Pos) /*!< EPWM_T::WGCTL1: CMPUCTL4 Mask */ + +#define EPWM_WGCTL1_CMPUCTL5_Pos (10) /*!< EPWM_T::WGCTL1: CMPUCTL5 Position */ +#define EPWM_WGCTL1_CMPUCTL5_Msk (0x3ul << EPWM_WGCTL1_CMPUCTL5_Pos) /*!< EPWM_T::WGCTL1: CMPUCTL5 Mask */ + +#define EPWM_WGCTL1_CMPDCTL0_Pos (16) /*!< EPWM_T::WGCTL1: CMPDCTL0 Position */ +#define EPWM_WGCTL1_CMPDCTL0_Msk (0x3ul << EPWM_WGCTL1_CMPDCTL0_Pos) /*!< EPWM_T::WGCTL1: CMPDCTL0 Mask */ + +#define EPWM_WGCTL1_CMPDCTL1_Pos (18) /*!< EPWM_T::WGCTL1: CMPDCTL1 Position */ +#define EPWM_WGCTL1_CMPDCTL1_Msk (0x3ul << EPWM_WGCTL1_CMPDCTL1_Pos) /*!< EPWM_T::WGCTL1: CMPDCTL1 Mask */ + +#define EPWM_WGCTL1_CMPDCTL2_Pos (20) /*!< EPWM_T::WGCTL1: CMPDCTL2 Position */ +#define EPWM_WGCTL1_CMPDCTL2_Msk (0x3ul << EPWM_WGCTL1_CMPDCTL2_Pos) /*!< EPWM_T::WGCTL1: CMPDCTL2 Mask */ + +#define EPWM_WGCTL1_CMPDCTL3_Pos (22) /*!< EPWM_T::WGCTL1: CMPDCTL3 Position */ +#define EPWM_WGCTL1_CMPDCTL3_Msk (0x3ul << EPWM_WGCTL1_CMPDCTL3_Pos) /*!< EPWM_T::WGCTL1: CMPDCTL3 Mask */ + +#define EPWM_WGCTL1_CMPDCTL4_Pos (24) /*!< EPWM_T::WGCTL1: CMPDCTL4 Position */ +#define EPWM_WGCTL1_CMPDCTL4_Msk (0x3ul << EPWM_WGCTL1_CMPDCTL4_Pos) /*!< EPWM_T::WGCTL1: CMPDCTL4 Mask */ + +#define EPWM_WGCTL1_CMPDCTL5_Pos (26) /*!< EPWM_T::WGCTL1: CMPDCTL5 Position */ +#define EPWM_WGCTL1_CMPDCTL5_Msk (0x3ul << EPWM_WGCTL1_CMPDCTL5_Pos) /*!< EPWM_T::WGCTL1: CMPDCTL5 Mask */ + +#define EPWM_MSKEN_MSKEN0_Pos (0) /*!< EPWM_T::MSKEN: MSKEN0 Position */ +#define EPWM_MSKEN_MSKEN0_Msk (0x1ul << EPWM_MSKEN_MSKEN0_Pos) /*!< EPWM_T::MSKEN: MSKEN0 Mask */ + +#define EPWM_MSKEN_MSKEN1_Pos (1) /*!< EPWM_T::MSKEN: MSKEN1 Position */ +#define EPWM_MSKEN_MSKEN1_Msk (0x1ul << EPWM_MSKEN_MSKEN1_Pos) /*!< EPWM_T::MSKEN: MSKEN1 Mask */ + +#define EPWM_MSKEN_MSKEN2_Pos (2) /*!< EPWM_T::MSKEN: MSKEN2 Position */ +#define EPWM_MSKEN_MSKEN2_Msk (0x1ul << EPWM_MSKEN_MSKEN2_Pos) /*!< EPWM_T::MSKEN: MSKEN2 Mask */ + +#define EPWM_MSKEN_MSKEN3_Pos (3) /*!< EPWM_T::MSKEN: MSKEN3 Position */ +#define EPWM_MSKEN_MSKEN3_Msk (0x1ul << EPWM_MSKEN_MSKEN3_Pos) /*!< EPWM_T::MSKEN: MSKEN3 Mask */ + +#define EPWM_MSKEN_MSKEN4_Pos (4) /*!< EPWM_T::MSKEN: MSKEN4 Position */ +#define EPWM_MSKEN_MSKEN4_Msk (0x1ul << EPWM_MSKEN_MSKEN4_Pos) /*!< EPWM_T::MSKEN: MSKEN4 Mask */ + +#define EPWM_MSKEN_MSKEN5_Pos (5) /*!< EPWM_T::MSKEN: MSKEN5 Position */ +#define EPWM_MSKEN_MSKEN5_Msk (0x1ul << EPWM_MSKEN_MSKEN5_Pos) /*!< EPWM_T::MSKEN: MSKEN5 Mask */ + +#define EPWM_MSK_MSKDAT0_Pos (0) /*!< EPWM_T::MSK: MSKDAT0 Position */ +#define EPWM_MSK_MSKDAT0_Msk (0x1ul << EPWM_MSK_MSKDAT0_Pos) /*!< EPWM_T::MSK: MSKDAT0 Mask */ + +#define EPWM_MSK_MSKDAT1_Pos (1) /*!< EPWM_T::MSK: MSKDAT1 Position */ +#define EPWM_MSK_MSKDAT1_Msk (0x1ul << EPWM_MSK_MSKDAT1_Pos) /*!< EPWM_T::MSK: MSKDAT1 Mask */ + +#define EPWM_MSK_MSKDAT2_Pos (2) /*!< EPWM_T::MSK: MSKDAT2 Position */ +#define EPWM_MSK_MSKDAT2_Msk (0x1ul << EPWM_MSK_MSKDAT2_Pos) /*!< EPWM_T::MSK: MSKDAT2 Mask */ + +#define EPWM_MSK_MSKDAT3_Pos (3) /*!< EPWM_T::MSK: MSKDAT3 Position */ +#define EPWM_MSK_MSKDAT3_Msk (0x1ul << EPWM_MSK_MSKDAT3_Pos) /*!< EPWM_T::MSK: MSKDAT3 Mask */ + +#define EPWM_MSK_MSKDAT4_Pos (4) /*!< EPWM_T::MSK: MSKDAT4 Position */ +#define EPWM_MSK_MSKDAT4_Msk (0x1ul << EPWM_MSK_MSKDAT4_Pos) /*!< EPWM_T::MSK: MSKDAT4 Mask */ + +#define EPWM_MSK_MSKDAT5_Pos (5) /*!< EPWM_T::MSK: MSKDAT5 Position */ +#define EPWM_MSK_MSKDAT5_Msk (0x1ul << EPWM_MSK_MSKDAT5_Pos) /*!< EPWM_T::MSK: MSKDAT5 Mask */ + +#define EPWM_BNF_BRK0NFEN_Pos (0) /*!< EPWM_T::BNF: BRK0NFEN Position */ +#define EPWM_BNF_BRK0NFEN_Msk (0x1ul << EPWM_BNF_BRK0NFEN_Pos) /*!< EPWM_T::BNF: BRK0NFEN Mask */ + +#define EPWM_BNF_BRK0NFSEL_Pos (1) /*!< EPWM_T::BNF: BRK0NFSEL Position */ +#define EPWM_BNF_BRK0NFSEL_Msk (0x7ul << EPWM_BNF_BRK0NFSEL_Pos) /*!< EPWM_T::BNF: BRK0NFSEL Mask */ + +#define EPWM_BNF_BRK0FCNT_Pos (4) /*!< EPWM_T::BNF: BRK0FCNT Position */ +#define EPWM_BNF_BRK0FCNT_Msk (0x7ul << EPWM_BNF_BRK0FCNT_Pos) /*!< EPWM_T::BNF: BRK0FCNT Mask */ + +#define EPWM_BNF_BRK0PINV_Pos (7) /*!< EPWM_T::BNF: BRK0PINV Position */ +#define EPWM_BNF_BRK0PINV_Msk (0x1ul << EPWM_BNF_BRK0PINV_Pos) /*!< EPWM_T::BNF: BRK0PINV Mask */ + +#define EPWM_BNF_BRK1NFEN_Pos (8) /*!< EPWM_T::BNF: BRK1NFEN Position */ +#define EPWM_BNF_BRK1NFEN_Msk (0x1ul << EPWM_BNF_BRK1NFEN_Pos) /*!< EPWM_T::BNF: BRK1NFEN Mask */ + +#define EPWM_BNF_BRK1NFSEL_Pos (9) /*!< EPWM_T::BNF: BRK1NFSEL Position */ +#define EPWM_BNF_BRK1NFSEL_Msk (0x7ul << EPWM_BNF_BRK1NFSEL_Pos) /*!< EPWM_T::BNF: BRK1NFSEL Mask */ + +#define EPWM_BNF_BRK1FCNT_Pos (12) /*!< EPWM_T::BNF: BRK1FCNT Position */ +#define EPWM_BNF_BRK1FCNT_Msk (0x7ul << EPWM_BNF_BRK1FCNT_Pos) /*!< EPWM_T::BNF: BRK1FCNT Mask */ + +#define EPWM_BNF_BRK1PINV_Pos (15) /*!< EPWM_T::BNF: BRK1PINV Position */ +#define EPWM_BNF_BRK1PINV_Msk (0x1ul << EPWM_BNF_BRK1PINV_Pos) /*!< EPWM_T::BNF: BRK1PINV Mask */ + +#define EPWM_BNF_BK0SRC_Pos (16) /*!< EPWM_T::BNF: BK0SRC Position */ +#define EPWM_BNF_BK0SRC_Msk (0x1ul << EPWM_BNF_BK0SRC_Pos) /*!< EPWM_T::BNF: BK0SRC Mask */ + +#define EPWM_BNF_BK1SRC_Pos (24) /*!< EPWM_T::BNF: BK1SRC Position */ +#define EPWM_BNF_BK1SRC_Msk (0x1ul << EPWM_BNF_BK1SRC_Pos) /*!< EPWM_T::BNF: BK1SRC Mask */ + +#define EPWM_FAILBRK_CSSBRKEN_Pos (0) /*!< EPWM_T::FAILBRK: CSSBRKEN Position */ +#define EPWM_FAILBRK_CSSBRKEN_Msk (0x1ul << EPWM_FAILBRK_CSSBRKEN_Pos) /*!< EPWM_T::FAILBRK: CSSBRKEN Mask */ + +#define EPWM_FAILBRK_BODBRKEN_Pos (1) /*!< EPWM_T::FAILBRK: BODBRKEN Position */ +#define EPWM_FAILBRK_BODBRKEN_Msk (0x1ul << EPWM_FAILBRK_BODBRKEN_Pos) /*!< EPWM_T::FAILBRK: BODBRKEN Mask */ + +#define EPWM_FAILBRK_RAMBRKEN_Pos (2) /*!< EPWM_T::FAILBRK: RAMBRKEN Position */ +#define EPWM_FAILBRK_RAMBRKEN_Msk (0x1ul << EPWM_FAILBRK_RAMBRKEN_Pos) /*!< EPWM_T::FAILBRK: RAMBRKEN Mask */ + +#define EPWM_FAILBRK_CORBRKEN_Pos (3) /*!< EPWM_T::FAILBRK: CORBRKEN Position */ +#define EPWM_FAILBRK_CORBRKEN_Msk (0x1ul << EPWM_FAILBRK_CORBRKEN_Pos) /*!< EPWM_T::FAILBRK: CORBRKEN Mask */ + +#define EPWM_BRKCTL0_1_CPO0EBEN_Pos (0) /*!< EPWM_T::BRKCTL0_1: CPO0EBEN Position */ +#define EPWM_BRKCTL0_1_CPO0EBEN_Msk (0x1ul << EPWM_BRKCTL0_1_CPO0EBEN_Pos) /*!< EPWM_T::BRKCTL0_1: CPO0EBEN Mask */ + +#define EPWM_BRKCTL0_1_CPO1EBEN_Pos (1) /*!< EPWM_T::BRKCTL0_1: CPO1EBEN Position */ +#define EPWM_BRKCTL0_1_CPO1EBEN_Msk (0x1ul << EPWM_BRKCTL0_1_CPO1EBEN_Pos) /*!< EPWM_T::BRKCTL0_1: CPO1EBEN Mask */ + +#define EPWM_BRKCTL0_1_BRKP0EEN_Pos (4) /*!< EPWM_T::BRKCTL0_1: BRKP0EEN Position */ +#define EPWM_BRKCTL0_1_BRKP0EEN_Msk (0x1ul << EPWM_BRKCTL0_1_BRKP0EEN_Pos) /*!< EPWM_T::BRKCTL0_1: BRKP0EEN Mask */ + +#define EPWM_BRKCTL0_1_BRKP1EEN_Pos (5) /*!< EPWM_T::BRKCTL0_1: BRKP1EEN Position */ +#define EPWM_BRKCTL0_1_BRKP1EEN_Msk (0x1ul << EPWM_BRKCTL0_1_BRKP1EEN_Pos) /*!< EPWM_T::BRKCTL0_1: BRKP1EEN Mask */ + +#define EPWM_BRKCTL0_1_SYSEBEN_Pos (7) /*!< EPWM_T::BRKCTL0_1: SYSEBEN Position */ +#define EPWM_BRKCTL0_1_SYSEBEN_Msk (0x1ul << EPWM_BRKCTL0_1_SYSEBEN_Pos) /*!< EPWM_T::BRKCTL0_1: SYSEBEN Mask */ + +#define EPWM_BRKCTL0_1_CPO0LBEN_Pos (8) /*!< EPWM_T::BRKCTL0_1: CPO0LBEN Position */ +#define EPWM_BRKCTL0_1_CPO0LBEN_Msk (0x1ul << EPWM_BRKCTL0_1_CPO0LBEN_Pos) /*!< EPWM_T::BRKCTL0_1: CPO0LBEN Mask */ + +#define EPWM_BRKCTL0_1_CPO1LBEN_Pos (9) /*!< EPWM_T::BRKCTL0_1: CPO1LBEN Position */ +#define EPWM_BRKCTL0_1_CPO1LBEN_Msk (0x1ul << EPWM_BRKCTL0_1_CPO1LBEN_Pos) /*!< EPWM_T::BRKCTL0_1: CPO1LBEN Mask */ + +#define EPWM_BRKCTL0_1_BRKP0LEN_Pos (12) /*!< EPWM_T::BRKCTL0_1: BRKP0LEN Position */ +#define EPWM_BRKCTL0_1_BRKP0LEN_Msk (0x1ul << EPWM_BRKCTL0_1_BRKP0LEN_Pos) /*!< EPWM_T::BRKCTL0_1: BRKP0LEN Mask */ + +#define EPWM_BRKCTL0_1_BRKP1LEN_Pos (13) /*!< EPWM_T::BRKCTL0_1: BRKP1LEN Position */ +#define EPWM_BRKCTL0_1_BRKP1LEN_Msk (0x1ul << EPWM_BRKCTL0_1_BRKP1LEN_Pos) /*!< EPWM_T::BRKCTL0_1: BRKP1LEN Mask */ + +#define EPWM_BRKCTL0_1_SYSLBEN_Pos (15) /*!< EPWM_T::BRKCTL0_1: SYSLBEN Position */ +#define EPWM_BRKCTL0_1_SYSLBEN_Msk (0x1ul << EPWM_BRKCTL0_1_SYSLBEN_Pos) /*!< EPWM_T::BRKCTL0_1: SYSLBEN Mask */ + +#define EPWM_BRKCTL0_1_BRKAEVEN_Pos (16) /*!< EPWM_T::BRKCTL0_1: BRKAEVEN Position */ +#define EPWM_BRKCTL0_1_BRKAEVEN_Msk (0x3ul << EPWM_BRKCTL0_1_BRKAEVEN_Pos) /*!< EPWM_T::BRKCTL0_1: BRKAEVEN Mask */ + +#define EPWM_BRKCTL0_1_BRKAODD_Pos (18) /*!< EPWM_T::BRKCTL0_1: BRKAODD Position */ +#define EPWM_BRKCTL0_1_BRKAODD_Msk (0x3ul << EPWM_BRKCTL0_1_BRKAODD_Pos) /*!< EPWM_T::BRKCTL0_1: BRKAODD Mask */ + +#define EPWM_BRKCTL0_1_EADCEBEN_Pos (20) /*!< EPWM_T::BRKCTL0_1: EADCEBEN Position */ +#define EPWM_BRKCTL0_1_EADCEBEN_Msk (0x1ul << EPWM_BRKCTL0_1_EADCEBEN_Pos) /*!< EPWM_T::BRKCTL0_1: EADCEBEN Mask */ + +#define EPWM_BRKCTL0_1_EADCLBEN_Pos (28) /*!< EPWM_T::BRKCTL0_1: EADCLBEN Position */ +#define EPWM_BRKCTL0_1_EADCLBEN_Msk (0x1ul << EPWM_BRKCTL0_1_EADCLBEN_Pos) /*!< EPWM_T::BRKCTL0_1: EADCLBEN Mask */ + +#define EPWM_BRKCTL2_3_CPO0EBEN_Pos (0) /*!< EPWM_T::BRKCTL2_3: CPO0EBEN Position */ +#define EPWM_BRKCTL2_3_CPO0EBEN_Msk (0x1ul << EPWM_BRKCTL2_3_CPO0EBEN_Pos) /*!< EPWM_T::BRKCTL2_3: CPO0EBEN Mask */ + +#define EPWM_BRKCTL2_3_CPO1EBEN_Pos (1) /*!< EPWM_T::BRKCTL2_3: CPO1EBEN Position */ +#define EPWM_BRKCTL2_3_CPO1EBEN_Msk (0x1ul << EPWM_BRKCTL2_3_CPO1EBEN_Pos) /*!< EPWM_T::BRKCTL2_3: CPO1EBEN Mask */ + +#define EPWM_BRKCTL2_3_BRKP0EEN_Pos (4) /*!< EPWM_T::BRKCTL2_3: BRKP0EEN Position */ +#define EPWM_BRKCTL2_3_BRKP0EEN_Msk (0x1ul << EPWM_BRKCTL2_3_BRKP0EEN_Pos) /*!< EPWM_T::BRKCTL2_3: BRKP0EEN Mask */ + +#define EPWM_BRKCTL2_3_BRKP1EEN_Pos (5) /*!< EPWM_T::BRKCTL2_3: BRKP1EEN Position */ +#define EPWM_BRKCTL2_3_BRKP1EEN_Msk (0x1ul << EPWM_BRKCTL2_3_BRKP1EEN_Pos) /*!< EPWM_T::BRKCTL2_3: BRKP1EEN Mask */ + +#define EPWM_BRKCTL2_3_SYSEBEN_Pos (7) /*!< EPWM_T::BRKCTL2_3: SYSEBEN Position */ +#define EPWM_BRKCTL2_3_SYSEBEN_Msk (0x1ul << EPWM_BRKCTL2_3_SYSEBEN_Pos) /*!< EPWM_T::BRKCTL2_3: SYSEBEN Mask */ + +#define EPWM_BRKCTL2_3_CPO0LBEN_Pos (8) /*!< EPWM_T::BRKCTL2_3: CPO0LBEN Position */ +#define EPWM_BRKCTL2_3_CPO0LBEN_Msk (0x1ul << EPWM_BRKCTL2_3_CPO0LBEN_Pos) /*!< EPWM_T::BRKCTL2_3: CPO0LBEN Mask */ + +#define EPWM_BRKCTL2_3_CPO1LBEN_Pos (9) /*!< EPWM_T::BRKCTL2_3: CPO1LBEN Position */ +#define EPWM_BRKCTL2_3_CPO1LBEN_Msk (0x1ul << EPWM_BRKCTL2_3_CPO1LBEN_Pos) /*!< EPWM_T::BRKCTL2_3: CPO1LBEN Mask */ + +#define EPWM_BRKCTL2_3_BRKP0LEN_Pos (12) /*!< EPWM_T::BRKCTL2_3: BRKP0LEN Position */ +#define EPWM_BRKCTL2_3_BRKP0LEN_Msk (0x1ul << EPWM_BRKCTL2_3_BRKP0LEN_Pos) /*!< EPWM_T::BRKCTL2_3: BRKP0LEN Mask */ + +#define EPWM_BRKCTL2_3_BRKP1LEN_Pos (13) /*!< EPWM_T::BRKCTL2_3: BRKP1LEN Position */ +#define EPWM_BRKCTL2_3_BRKP1LEN_Msk (0x1ul << EPWM_BRKCTL2_3_BRKP1LEN_Pos) /*!< EPWM_T::BRKCTL2_3: BRKP1LEN Mask */ + +#define EPWM_BRKCTL2_3_SYSLBEN_Pos (15) /*!< EPWM_T::BRKCTL2_3: SYSLBEN Position */ +#define EPWM_BRKCTL2_3_SYSLBEN_Msk (0x1ul << EPWM_BRKCTL2_3_SYSLBEN_Pos) /*!< EPWM_T::BRKCTL2_3: SYSLBEN Mask */ + +#define EPWM_BRKCTL2_3_BRKAEVEN_Pos (16) /*!< EPWM_T::BRKCTL2_3: BRKAEVEN Position */ +#define EPWM_BRKCTL2_3_BRKAEVEN_Msk (0x3ul << EPWM_BRKCTL2_3_BRKAEVEN_Pos) /*!< EPWM_T::BRKCTL2_3: BRKAEVEN Mask */ + +#define EPWM_BRKCTL2_3_BRKAODD_Pos (18) /*!< EPWM_T::BRKCTL2_3: BRKAODD Position */ +#define EPWM_BRKCTL2_3_BRKAODD_Msk (0x3ul << EPWM_BRKCTL2_3_BRKAODD_Pos) /*!< EPWM_T::BRKCTL2_3: BRKAODD Mask */ + +#define EPWM_BRKCTL2_3_EADCEBEN_Pos (20) /*!< EPWM_T::BRKCTL2_3: EADCEBEN Position */ +#define EPWM_BRKCTL2_3_EADCEBEN_Msk (0x1ul << EPWM_BRKCTL2_3_EADCEBEN_Pos) /*!< EPWM_T::BRKCTL2_3: EADCEBEN Mask */ + +#define EPWM_BRKCTL2_3_EADCLBEN_Pos (28) /*!< EPWM_T::BRKCTL2_3: EADCLBEN Position */ +#define EPWM_BRKCTL2_3_EADCLBEN_Msk (0x1ul << EPWM_BRKCTL2_3_EADCLBEN_Pos) /*!< EPWM_T::BRKCTL2_3: EADCLBEN Mask */ + +#define EPWM_BRKCTL4_5_CPO0EBEN_Pos (0) /*!< EPWM_T::BRKCTL4_5: CPO0EBEN Position */ +#define EPWM_BRKCTL4_5_CPO0EBEN_Msk (0x1ul << EPWM_BRKCTL4_5_CPO0EBEN_Pos) /*!< EPWM_T::BRKCTL4_5: CPO0EBEN Mask */ + +#define EPWM_BRKCTL4_5_CPO1EBEN_Pos (1) /*!< EPWM_T::BRKCTL4_5: CPO1EBEN Position */ +#define EPWM_BRKCTL4_5_CPO1EBEN_Msk (0x1ul << EPWM_BRKCTL4_5_CPO1EBEN_Pos) /*!< EPWM_T::BRKCTL4_5: CPO1EBEN Mask */ + +#define EPWM_BRKCTL4_5_BRKP0EEN_Pos (4) /*!< EPWM_T::BRKCTL4_5: BRKP0EEN Position */ +#define EPWM_BRKCTL4_5_BRKP0EEN_Msk (0x1ul << EPWM_BRKCTL4_5_BRKP0EEN_Pos) /*!< EPWM_T::BRKCTL4_5: BRKP0EEN Mask */ + +#define EPWM_BRKCTL4_5_BRKP1EEN_Pos (5) /*!< EPWM_T::BRKCTL4_5: BRKP1EEN Position */ +#define EPWM_BRKCTL4_5_BRKP1EEN_Msk (0x1ul << EPWM_BRKCTL4_5_BRKP1EEN_Pos) /*!< EPWM_T::BRKCTL4_5: BRKP1EEN Mask */ + +#define EPWM_BRKCTL4_5_SYSEBEN_Pos (7) /*!< EPWM_T::BRKCTL4_5: SYSEBEN Position */ +#define EPWM_BRKCTL4_5_SYSEBEN_Msk (0x1ul << EPWM_BRKCTL4_5_SYSEBEN_Pos) /*!< EPWM_T::BRKCTL4_5: SYSEBEN Mask */ + +#define EPWM_BRKCTL4_5_CPO0LBEN_Pos (8) /*!< EPWM_T::BRKCTL4_5: CPO0LBEN Position */ +#define EPWM_BRKCTL4_5_CPO0LBEN_Msk (0x1ul << EPWM_BRKCTL4_5_CPO0LBEN_Pos) /*!< EPWM_T::BRKCTL4_5: CPO0LBEN Mask */ + +#define EPWM_BRKCTL4_5_CPO1LBEN_Pos (9) /*!< EPWM_T::BRKCTL4_5: CPO1LBEN Position */ +#define EPWM_BRKCTL4_5_CPO1LBEN_Msk (0x1ul << EPWM_BRKCTL4_5_CPO1LBEN_Pos) /*!< EPWM_T::BRKCTL4_5: CPO1LBEN Mask */ + +#define EPWM_BRKCTL4_5_BRKP0LEN_Pos (12) /*!< EPWM_T::BRKCTL4_5: BRKP0LEN Position */ +#define EPWM_BRKCTL4_5_BRKP0LEN_Msk (0x1ul << EPWM_BRKCTL4_5_BRKP0LEN_Pos) /*!< EPWM_T::BRKCTL4_5: BRKP0LEN Mask */ + +#define EPWM_BRKCTL4_5_BRKP1LEN_Pos (13) /*!< EPWM_T::BRKCTL4_5: BRKP1LEN Position */ +#define EPWM_BRKCTL4_5_BRKP1LEN_Msk (0x1ul << EPWM_BRKCTL4_5_BRKP1LEN_Pos) /*!< EPWM_T::BRKCTL4_5: BRKP1LEN Mask */ + +#define EPWM_BRKCTL4_5_SYSLBEN_Pos (15) /*!< EPWM_T::BRKCTL4_5: SYSLBEN Position */ +#define EPWM_BRKCTL4_5_SYSLBEN_Msk (0x1ul << EPWM_BRKCTL4_5_SYSLBEN_Pos) /*!< EPWM_T::BRKCTL4_5: SYSLBEN Mask */ + +#define EPWM_BRKCTL4_5_BRKAEVEN_Pos (16) /*!< EPWM_T::BRKCTL4_5: BRKAEVEN Position */ +#define EPWM_BRKCTL4_5_BRKAEVEN_Msk (0x3ul << EPWM_BRKCTL4_5_BRKAEVEN_Pos) /*!< EPWM_T::BRKCTL4_5: BRKAEVEN Mask */ + +#define EPWM_BRKCTL4_5_BRKAODD_Pos (18) /*!< EPWM_T::BRKCTL4_5: BRKAODD Position */ +#define EPWM_BRKCTL4_5_BRKAODD_Msk (0x3ul << EPWM_BRKCTL4_5_BRKAODD_Pos) /*!< EPWM_T::BRKCTL4_5: BRKAODD Mask */ + +#define EPWM_BRKCTL4_5_EADCEBEN_Pos (20) /*!< EPWM_T::BRKCTL4_5: EADCEBEN Position */ +#define EPWM_BRKCTL4_5_EADCEBEN_Msk (0x1ul << EPWM_BRKCTL4_5_EADCEBEN_Pos) /*!< EPWM_T::BRKCTL4_5: EADCEBEN Mask */ + +#define EPWM_BRKCTL4_5_EADCLBEN_Pos (28) /*!< EPWM_T::BRKCTL4_5: EADCLBEN Position */ +#define EPWM_BRKCTL4_5_EADCLBEN_Msk (0x1ul << EPWM_BRKCTL4_5_EADCLBEN_Pos) /*!< EPWM_T::BRKCTL4_5: EADCLBEN Mask */ + +#define EPWM_POLCTL_PINV0_Pos (0) /*!< EPWM_T::POLCTL: PINV0 Position */ +#define EPWM_POLCTL_PINV0_Msk (0x1ul << EPWM_POLCTL_PINV0_Pos) /*!< EPWM_T::POLCTL: PINV0 Mask */ + +#define EPWM_POLCTL_PINV1_Pos (1) /*!< EPWM_T::POLCTL: PINV1 Position */ +#define EPWM_POLCTL_PINV1_Msk (0x1ul << EPWM_POLCTL_PINV1_Pos) /*!< EPWM_T::POLCTL: PINV1 Mask */ + +#define EPWM_POLCTL_PINV2_Pos (2) /*!< EPWM_T::POLCTL: PINV2 Position */ +#define EPWM_POLCTL_PINV2_Msk (0x1ul << EPWM_POLCTL_PINV2_Pos) /*!< EPWM_T::POLCTL: PINV2 Mask */ + +#define EPWM_POLCTL_PINV3_Pos (3) /*!< EPWM_T::POLCTL: PINV3 Position */ +#define EPWM_POLCTL_PINV3_Msk (0x1ul << EPWM_POLCTL_PINV3_Pos) /*!< EPWM_T::POLCTL: PINV3 Mask */ + +#define EPWM_POLCTL_PINV4_Pos (4) /*!< EPWM_T::POLCTL: PINV4 Position */ +#define EPWM_POLCTL_PINV4_Msk (0x1ul << EPWM_POLCTL_PINV4_Pos) /*!< EPWM_T::POLCTL: PINV4 Mask */ + +#define EPWM_POLCTL_PINV5_Pos (5) /*!< EPWM_T::POLCTL: PINV5 Position */ +#define EPWM_POLCTL_PINV5_Msk (0x1ul << EPWM_POLCTL_PINV5_Pos) /*!< EPWM_T::POLCTL: PINV5 Mask */ + +#define EPWM_POEN_POEN0_Pos (0) /*!< EPWM_T::POEN: POEN0 Position */ +#define EPWM_POEN_POEN0_Msk (0x1ul << EPWM_POEN_POEN0_Pos) /*!< EPWM_T::POEN: POEN0 Mask */ + +#define EPWM_POEN_POEN1_Pos (1) /*!< EPWM_T::POEN: POEN1 Position */ +#define EPWM_POEN_POEN1_Msk (0x1ul << EPWM_POEN_POEN1_Pos) /*!< EPWM_T::POEN: POEN1 Mask */ + +#define EPWM_POEN_POEN2_Pos (2) /*!< EPWM_T::POEN: POEN2 Position */ +#define EPWM_POEN_POEN2_Msk (0x1ul << EPWM_POEN_POEN2_Pos) /*!< EPWM_T::POEN: POEN2 Mask */ + +#define EPWM_POEN_POEN3_Pos (3) /*!< EPWM_T::POEN: POEN3 Position */ +#define EPWM_POEN_POEN3_Msk (0x1ul << EPWM_POEN_POEN3_Pos) /*!< EPWM_T::POEN: POEN3 Mask */ + +#define EPWM_POEN_POEN4_Pos (4) /*!< EPWM_T::POEN: POEN4 Position */ +#define EPWM_POEN_POEN4_Msk (0x1ul << EPWM_POEN_POEN4_Pos) /*!< EPWM_T::POEN: POEN4 Mask */ + +#define EPWM_POEN_POEN5_Pos (5) /*!< EPWM_T::POEN: POEN5 Position */ +#define EPWM_POEN_POEN5_Msk (0x1ul << EPWM_POEN_POEN5_Pos) /*!< EPWM_T::POEN: POEN5 Mask */ + +#define EPWM_SWBRK_BRKETRG0_Pos (0) /*!< EPWM_T::SWBRK: BRKETRG0 Position */ +#define EPWM_SWBRK_BRKETRG0_Msk (0x1ul << EPWM_SWBRK_BRKETRG0_Pos) /*!< EPWM_T::SWBRK: BRKETRG0 Mask */ + +#define EPWM_SWBRK_BRKETRG2_Pos (1) /*!< EPWM_T::SWBRK: BRKETRG2 Position */ +#define EPWM_SWBRK_BRKETRG2_Msk (0x1ul << EPWM_SWBRK_BRKETRG2_Pos) /*!< EPWM_T::SWBRK: BRKETRG2 Mask */ + +#define EPWM_SWBRK_BRKETRG4_Pos (2) /*!< EPWM_T::SWBRK: BRKETRG4 Position */ +#define EPWM_SWBRK_BRKETRG4_Msk (0x1ul << EPWM_SWBRK_BRKETRG4_Pos) /*!< EPWM_T::SWBRK: BRKETRG4 Mask */ + +#define EPWM_SWBRK_BRKLTRG0_Pos (8) /*!< EPWM_T::SWBRK: BRKLTRG0 Position */ +#define EPWM_SWBRK_BRKLTRG0_Msk (0x1ul << EPWM_SWBRK_BRKLTRG0_Pos) /*!< EPWM_T::SWBRK: BRKLTRG0 Mask */ + +#define EPWM_SWBRK_BRKLTRG2_Pos (9) /*!< EPWM_T::SWBRK: BRKLTRG2 Position */ +#define EPWM_SWBRK_BRKLTRG2_Msk (0x1ul << EPWM_SWBRK_BRKLTRG2_Pos) /*!< EPWM_T::SWBRK: BRKLTRG2 Mask */ + +#define EPWM_SWBRK_BRKLTRG4_Pos (10) /*!< EPWM_T::SWBRK: BRKLTRG4 Position */ +#define EPWM_SWBRK_BRKLTRG4_Msk (0x1ul << EPWM_SWBRK_BRKLTRG4_Pos) /*!< EPWM_T::SWBRK: BRKLTRG4 Mask */ + +#define EPWM_INTEN0_ZIEN0_Pos (0) /*!< EPWM_T::INTEN0: ZIEN0 Position */ +#define EPWM_INTEN0_ZIEN0_Msk (0x1ul << EPWM_INTEN0_ZIEN0_Pos) /*!< EPWM_T::INTEN0: ZIEN0 Mask */ + +#define EPWM_INTEN0_ZIEN1_Pos (1) /*!< EPWM_T::INTEN0: ZIEN1 Position */ +#define EPWM_INTEN0_ZIEN1_Msk (0x1ul << EPWM_INTEN0_ZIEN1_Pos) /*!< EPWM_T::INTEN0: ZIEN1 Mask */ + +#define EPWM_INTEN0_ZIEN2_Pos (2) /*!< EPWM_T::INTEN0: ZIEN2 Position */ +#define EPWM_INTEN0_ZIEN2_Msk (0x1ul << EPWM_INTEN0_ZIEN2_Pos) /*!< EPWM_T::INTEN0: ZIEN2 Mask */ + +#define EPWM_INTEN0_ZIEN3_Pos (3) /*!< EPWM_T::INTEN0: ZIEN3 Position */ +#define EPWM_INTEN0_ZIEN3_Msk (0x1ul << EPWM_INTEN0_ZIEN3_Pos) /*!< EPWM_T::INTEN0: ZIEN3 Mask */ + +#define EPWM_INTEN0_ZIEN4_Pos (4) /*!< EPWM_T::INTEN0: ZIEN4 Position */ +#define EPWM_INTEN0_ZIEN4_Msk (0x1ul << EPWM_INTEN0_ZIEN4_Pos) /*!< EPWM_T::INTEN0: ZIEN4 Mask */ + +#define EPWM_INTEN0_ZIEN5_Pos (5) /*!< EPWM_T::INTEN0: ZIEN5 Position */ +#define EPWM_INTEN0_ZIEN5_Msk (0x1ul << EPWM_INTEN0_ZIEN5_Pos) /*!< EPWM_T::INTEN0: ZIEN5 Mask */ + +#define EPWM_INTEN0_PIEN0_Pos (8) /*!< EPWM_T::INTEN0: PIEN0 Position */ +#define EPWM_INTEN0_PIEN0_Msk (0x1ul << EPWM_INTEN0_PIEN0_Pos) /*!< EPWM_T::INTEN0: PIEN0 Mask */ + +#define EPWM_INTEN0_PIEN1_Pos (9) /*!< EPWM_T::INTEN0: PIEN1 Position */ +#define EPWM_INTEN0_PIEN1_Msk (0x1ul << EPWM_INTEN0_PIEN1_Pos) /*!< EPWM_T::INTEN0: PIEN1 Mask */ + +#define EPWM_INTEN0_PIEN2_Pos (10) /*!< EPWM_T::INTEN0: PIEN2 Position */ +#define EPWM_INTEN0_PIEN2_Msk (0x1ul << EPWM_INTEN0_PIEN2_Pos) /*!< EPWM_T::INTEN0: PIEN2 Mask */ + +#define EPWM_INTEN0_PIEN3_Pos (11) /*!< EPWM_T::INTEN0: PIEN3 Position */ +#define EPWM_INTEN0_PIEN3_Msk (0x1ul << EPWM_INTEN0_PIEN3_Pos) /*!< EPWM_T::INTEN0: PIEN3 Mask */ + +#define EPWM_INTEN0_PIEN4_Pos (12) /*!< EPWM_T::INTEN0: PIEN4 Position */ +#define EPWM_INTEN0_PIEN4_Msk (0x1ul << EPWM_INTEN0_PIEN4_Pos) /*!< EPWM_T::INTEN0: PIEN4 Mask */ + +#define EPWM_INTEN0_PIEN5_Pos (13) /*!< EPWM_T::INTEN0: PIEN5 Position */ +#define EPWM_INTEN0_PIEN5_Msk (0x1ul << EPWM_INTEN0_PIEN5_Pos) /*!< EPWM_T::INTEN0: PIEN5 Mask */ + +#define EPWM_INTEN0_CMPUIEN0_Pos (16) /*!< EPWM_T::INTEN0: CMPUIEN0 Position */ +#define EPWM_INTEN0_CMPUIEN0_Msk (0x1ul << EPWM_INTEN0_CMPUIEN0_Pos) /*!< EPWM_T::INTEN0: CMPUIEN0 Mask */ + +#define EPWM_INTEN0_CMPUIEN1_Pos (17) /*!< EPWM_T::INTEN0: CMPUIEN1 Position */ +#define EPWM_INTEN0_CMPUIEN1_Msk (0x1ul << EPWM_INTEN0_CMPUIEN1_Pos) /*!< EPWM_T::INTEN0: CMPUIEN1 Mask */ + +#define EPWM_INTEN0_CMPUIEN2_Pos (18) /*!< EPWM_T::INTEN0: CMPUIEN2 Position */ +#define EPWM_INTEN0_CMPUIEN2_Msk (0x1ul << EPWM_INTEN0_CMPUIEN2_Pos) /*!< EPWM_T::INTEN0: CMPUIEN2 Mask */ + +#define EPWM_INTEN0_CMPUIEN3_Pos (19) /*!< EPWM_T::INTEN0: CMPUIEN3 Position */ +#define EPWM_INTEN0_CMPUIEN3_Msk (0x1ul << EPWM_INTEN0_CMPUIEN3_Pos) /*!< EPWM_T::INTEN0: CMPUIEN3 Mask */ + +#define EPWM_INTEN0_CMPUIEN4_Pos (20) /*!< EPWM_T::INTEN0: CMPUIEN4 Position */ +#define EPWM_INTEN0_CMPUIEN4_Msk (0x1ul << EPWM_INTEN0_CMPUIEN4_Pos) /*!< EPWM_T::INTEN0: CMPUIEN4 Mask */ + +#define EPWM_INTEN0_CMPUIEN5_Pos (21) /*!< EPWM_T::INTEN0: CMPUIEN5 Position */ +#define EPWM_INTEN0_CMPUIEN5_Msk (0x1ul << EPWM_INTEN0_CMPUIEN5_Pos) /*!< EPWM_T::INTEN0: CMPUIEN5 Mask */ + +#define EPWM_INTEN0_CMPDIEN0_Pos (24) /*!< EPWM_T::INTEN0: CMPDIEN0 Position */ +#define EPWM_INTEN0_CMPDIEN0_Msk (0x1ul << EPWM_INTEN0_CMPDIEN0_Pos) /*!< EPWM_T::INTEN0: CMPDIEN0 Mask */ + +#define EPWM_INTEN0_CMPDIEN1_Pos (25) /*!< EPWM_T::INTEN0: CMPDIEN1 Position */ +#define EPWM_INTEN0_CMPDIEN1_Msk (0x1ul << EPWM_INTEN0_CMPDIEN1_Pos) /*!< EPWM_T::INTEN0: CMPDIEN1 Mask */ + +#define EPWM_INTEN0_CMPDIEN2_Pos (26) /*!< EPWM_T::INTEN0: CMPDIEN2 Position */ +#define EPWM_INTEN0_CMPDIEN2_Msk (0x1ul << EPWM_INTEN0_CMPDIEN2_Pos) /*!< EPWM_T::INTEN0: CMPDIEN2 Mask */ + +#define EPWM_INTEN0_CMPDIEN3_Pos (27) /*!< EPWM_T::INTEN0: CMPDIEN3 Position */ +#define EPWM_INTEN0_CMPDIEN3_Msk (0x1ul << EPWM_INTEN0_CMPDIEN3_Pos) /*!< EPWM_T::INTEN0: CMPDIEN3 Mask */ + +#define EPWM_INTEN0_CMPDIEN4_Pos (28) /*!< EPWM_T::INTEN0: CMPDIEN4 Position */ +#define EPWM_INTEN0_CMPDIEN4_Msk (0x1ul << EPWM_INTEN0_CMPDIEN4_Pos) /*!< EPWM_T::INTEN0: CMPDIEN4 Mask */ + +#define EPWM_INTEN0_CMPDIEN5_Pos (29) /*!< EPWM_T::INTEN0: CMPDIEN5 Position */ +#define EPWM_INTEN0_CMPDIEN5_Msk (0x1ul << EPWM_INTEN0_CMPDIEN5_Pos) /*!< EPWM_T::INTEN0: CMPDIEN5 Mask */ + +#define EPWM_INTEN1_BRKEIEN0_1_Pos (0) /*!< EPWM_T::INTEN1: BRKEIEN0_1 Position */ +#define EPWM_INTEN1_BRKEIEN0_1_Msk (0x1ul << EPWM_INTEN1_BRKEIEN0_1_Pos) /*!< EPWM_T::INTEN1: BRKEIEN0_1 Mask */ + +#define EPWM_INTEN1_BRKEIEN2_3_Pos (1) /*!< EPWM_T::INTEN1: BRKEIEN2_3 Position */ +#define EPWM_INTEN1_BRKEIEN2_3_Msk (0x1ul << EPWM_INTEN1_BRKEIEN2_3_Pos) /*!< EPWM_T::INTEN1: BRKEIEN2_3 Mask */ + +#define EPWM_INTEN1_BRKEIEN4_5_Pos (2) /*!< EPWM_T::INTEN1: BRKEIEN4_5 Position */ +#define EPWM_INTEN1_BRKEIEN4_5_Msk (0x1ul << EPWM_INTEN1_BRKEIEN4_5_Pos) /*!< EPWM_T::INTEN1: BRKEIEN4_5 Mask */ + +#define EPWM_INTEN1_BRKLIEN0_1_Pos (8) /*!< EPWM_T::INTEN1: BRKLIEN0_1 Position */ +#define EPWM_INTEN1_BRKLIEN0_1_Msk (0x1ul << EPWM_INTEN1_BRKLIEN0_1_Pos) /*!< EPWM_T::INTEN1: BRKLIEN0_1 Mask */ + +#define EPWM_INTEN1_BRKLIEN2_3_Pos (9) /*!< EPWM_T::INTEN1: BRKLIEN2_3 Position */ +#define EPWM_INTEN1_BRKLIEN2_3_Msk (0x1ul << EPWM_INTEN1_BRKLIEN2_3_Pos) /*!< EPWM_T::INTEN1: BRKLIEN2_3 Mask */ + +#define EPWM_INTEN1_BRKLIEN4_5_Pos (10) /*!< EPWM_T::INTEN1: BRKLIEN4_5 Position */ +#define EPWM_INTEN1_BRKLIEN4_5_Msk (0x1ul << EPWM_INTEN1_BRKLIEN4_5_Pos) /*!< EPWM_T::INTEN1: BRKLIEN4_5 Mask */ + +#define EPWM_INTSTS0_ZIF0_Pos (0) /*!< EPWM_T::INTSTS0: ZIF0 Position */ +#define EPWM_INTSTS0_ZIF0_Msk (0x1ul << EPWM_INTSTS0_ZIF0_Pos) /*!< EPWM_T::INTSTS0: ZIF0 Mask */ + +#define EPWM_INTSTS0_ZIF1_Pos (1) /*!< EPWM_T::INTSTS0: ZIF1 Position */ +#define EPWM_INTSTS0_ZIF1_Msk (0x1ul << EPWM_INTSTS0_ZIF1_Pos) /*!< EPWM_T::INTSTS0: ZIF1 Mask */ + +#define EPWM_INTSTS0_ZIF2_Pos (2) /*!< EPWM_T::INTSTS0: ZIF2 Position */ +#define EPWM_INTSTS0_ZIF2_Msk (0x1ul << EPWM_INTSTS0_ZIF2_Pos) /*!< EPWM_T::INTSTS0: ZIF2 Mask */ + +#define EPWM_INTSTS0_ZIF3_Pos (3) /*!< EPWM_T::INTSTS0: ZIF3 Position */ +#define EPWM_INTSTS0_ZIF3_Msk (0x1ul << EPWM_INTSTS0_ZIF3_Pos) /*!< EPWM_T::INTSTS0: ZIF3 Mask */ + +#define EPWM_INTSTS0_ZIF4_Pos (4) /*!< EPWM_T::INTSTS0: ZIF4 Position */ +#define EPWM_INTSTS0_ZIF4_Msk (0x1ul << EPWM_INTSTS0_ZIF4_Pos) /*!< EPWM_T::INTSTS0: ZIF4 Mask */ + +#define EPWM_INTSTS0_ZIF5_Pos (5) /*!< EPWM_T::INTSTS0: ZIF5 Position */ +#define EPWM_INTSTS0_ZIF5_Msk (0x1ul << EPWM_INTSTS0_ZIF5_Pos) /*!< EPWM_T::INTSTS0: ZIF5 Mask */ + +#define EPWM_INTSTS0_PIF0_Pos (8) /*!< EPWM_T::INTSTS0: PIF0 Position */ +#define EPWM_INTSTS0_PIF0_Msk (0x1ul << EPWM_INTSTS0_PIF0_Pos) /*!< EPWM_T::INTSTS0: PIF0 Mask */ + +#define EPWM_INTSTS0_PIF1_Pos (9) /*!< EPWM_T::INTSTS0: PIF1 Position */ +#define EPWM_INTSTS0_PIF1_Msk (0x1ul << EPWM_INTSTS0_PIF1_Pos) /*!< EPWM_T::INTSTS0: PIF1 Mask */ + +#define EPWM_INTSTS0_PIF2_Pos (10) /*!< EPWM_T::INTSTS0: PIF2 Position */ +#define EPWM_INTSTS0_PIF2_Msk (0x1ul << EPWM_INTSTS0_PIF2_Pos) /*!< EPWM_T::INTSTS0: PIF2 Mask */ + +#define EPWM_INTSTS0_PIF3_Pos (11) /*!< EPWM_T::INTSTS0: PIF3 Position */ +#define EPWM_INTSTS0_PIF3_Msk (0x1ul << EPWM_INTSTS0_PIF3_Pos) /*!< EPWM_T::INTSTS0: PIF3 Mask */ + +#define EPWM_INTSTS0_PIF4_Pos (12) /*!< EPWM_T::INTSTS0: PIF4 Position */ +#define EPWM_INTSTS0_PIF4_Msk (0x1ul << EPWM_INTSTS0_PIF4_Pos) /*!< EPWM_T::INTSTS0: PIF4 Mask */ + +#define EPWM_INTSTS0_PIF5_Pos (13) /*!< EPWM_T::INTSTS0: PIF5 Position */ +#define EPWM_INTSTS0_PIF5_Msk (0x1ul << EPWM_INTSTS0_PIF5_Pos) /*!< EPWM_T::INTSTS0: PIF5 Mask */ + +#define EPWM_INTSTS0_CMPUIF0_Pos (16) /*!< EPWM_T::INTSTS0: CMPUIF0 Position */ +#define EPWM_INTSTS0_CMPUIF0_Msk (0x1ul << EPWM_INTSTS0_CMPUIF0_Pos) /*!< EPWM_T::INTSTS0: CMPUIF0 Mask */ + +#define EPWM_INTSTS0_CMPUIF1_Pos (17) /*!< EPWM_T::INTSTS0: CMPUIF1 Position */ +#define EPWM_INTSTS0_CMPUIF1_Msk (0x1ul << EPWM_INTSTS0_CMPUIF1_Pos) /*!< EPWM_T::INTSTS0: CMPUIF1 Mask */ + +#define EPWM_INTSTS0_CMPUIF2_Pos (18) /*!< EPWM_T::INTSTS0: CMPUIF2 Position */ +#define EPWM_INTSTS0_CMPUIF2_Msk (0x1ul << EPWM_INTSTS0_CMPUIF2_Pos) /*!< EPWM_T::INTSTS0: CMPUIF2 Mask */ + +#define EPWM_INTSTS0_CMPUIF3_Pos (19) /*!< EPWM_T::INTSTS0: CMPUIF3 Position */ +#define EPWM_INTSTS0_CMPUIF3_Msk (0x1ul << EPWM_INTSTS0_CMPUIF3_Pos) /*!< EPWM_T::INTSTS0: CMPUIF3 Mask */ + +#define EPWM_INTSTS0_CMPUIF4_Pos (20) /*!< EPWM_T::INTSTS0: CMPUIF4 Position */ +#define EPWM_INTSTS0_CMPUIF4_Msk (0x1ul << EPWM_INTSTS0_CMPUIF4_Pos) /*!< EPWM_T::INTSTS0: CMPUIF4 Mask */ + +#define EPWM_INTSTS0_CMPUIF5_Pos (21) /*!< EPWM_T::INTSTS0: CMPUIF5 Position */ +#define EPWM_INTSTS0_CMPUIF5_Msk (0x1ul << EPWM_INTSTS0_CMPUIF5_Pos) /*!< EPWM_T::INTSTS0: CMPUIF5 Mask */ + +#define EPWM_INTSTS0_CMPDIF0_Pos (24) /*!< EPWM_T::INTSTS0: CMPDIF0 Position */ +#define EPWM_INTSTS0_CMPDIF0_Msk (0x1ul << EPWM_INTSTS0_CMPDIF0_Pos) /*!< EPWM_T::INTSTS0: CMPDIF0 Mask */ + +#define EPWM_INTSTS0_CMPDIF1_Pos (25) /*!< EPWM_T::INTSTS0: CMPDIF1 Position */ +#define EPWM_INTSTS0_CMPDIF1_Msk (0x1ul << EPWM_INTSTS0_CMPDIF1_Pos) /*!< EPWM_T::INTSTS0: CMPDIF1 Mask */ + +#define EPWM_INTSTS0_CMPDIF2_Pos (26) /*!< EPWM_T::INTSTS0: CMPDIF2 Position */ +#define EPWM_INTSTS0_CMPDIF2_Msk (0x1ul << EPWM_INTSTS0_CMPDIF2_Pos) /*!< EPWM_T::INTSTS0: CMPDIF2 Mask */ + +#define EPWM_INTSTS0_CMPDIF3_Pos (27) /*!< EPWM_T::INTSTS0: CMPDIF3 Position */ +#define EPWM_INTSTS0_CMPDIF3_Msk (0x1ul << EPWM_INTSTS0_CMPDIF3_Pos) /*!< EPWM_T::INTSTS0: CMPDIF3 Mask */ + +#define EPWM_INTSTS0_CMPDIF4_Pos (28) /*!< EPWM_T::INTSTS0: CMPDIF4 Position */ +#define EPWM_INTSTS0_CMPDIF4_Msk (0x1ul << EPWM_INTSTS0_CMPDIF4_Pos) /*!< EPWM_T::INTSTS0: CMPDIF4 Mask */ + +#define EPWM_INTSTS0_CMPDIF5_Pos (29) /*!< EPWM_T::INTSTS0: CMPDIF5 Position */ +#define EPWM_INTSTS0_CMPDIF5_Msk (0x1ul << EPWM_INTSTS0_CMPDIF5_Pos) /*!< EPWM_T::INTSTS0: CMPDIF5 Mask */ + +#define EPWM_INTSTS1_BRKEIF0_Pos (0) /*!< EPWM_T::INTSTS1: BRKEIF0 Position */ +#define EPWM_INTSTS1_BRKEIF0_Msk (0x1ul << EPWM_INTSTS1_BRKEIF0_Pos) /*!< EPWM_T::INTSTS1: BRKEIF0 Mask */ + +#define EPWM_INTSTS1_BRKEIF1_Pos (1) /*!< EPWM_T::INTSTS1: BRKEIF1 Position */ +#define EPWM_INTSTS1_BRKEIF1_Msk (0x1ul << EPWM_INTSTS1_BRKEIF1_Pos) /*!< EPWM_T::INTSTS1: BRKEIF1 Mask */ + +#define EPWM_INTSTS1_BRKEIF2_Pos (2) /*!< EPWM_T::INTSTS1: BRKEIF2 Position */ +#define EPWM_INTSTS1_BRKEIF2_Msk (0x1ul << EPWM_INTSTS1_BRKEIF2_Pos) /*!< EPWM_T::INTSTS1: BRKEIF2 Mask */ + +#define EPWM_INTSTS1_BRKEIF3_Pos (3) /*!< EPWM_T::INTSTS1: BRKEIF3 Position */ +#define EPWM_INTSTS1_BRKEIF3_Msk (0x1ul << EPWM_INTSTS1_BRKEIF3_Pos) /*!< EPWM_T::INTSTS1: BRKEIF3 Mask */ + +#define EPWM_INTSTS1_BRKEIF4_Pos (4) /*!< EPWM_T::INTSTS1: BRKEIF4 Position */ +#define EPWM_INTSTS1_BRKEIF4_Msk (0x1ul << EPWM_INTSTS1_BRKEIF4_Pos) /*!< EPWM_T::INTSTS1: BRKEIF4 Mask */ + +#define EPWM_INTSTS1_BRKEIF5_Pos (5) /*!< EPWM_T::INTSTS1: BRKEIF5 Position */ +#define EPWM_INTSTS1_BRKEIF5_Msk (0x1ul << EPWM_INTSTS1_BRKEIF5_Pos) /*!< EPWM_T::INTSTS1: BRKEIF5 Mask */ + +#define EPWM_INTSTS1_BRKLIF0_Pos (8) /*!< EPWM_T::INTSTS1: BRKLIF0 Position */ +#define EPWM_INTSTS1_BRKLIF0_Msk (0x1ul << EPWM_INTSTS1_BRKLIF0_Pos) /*!< EPWM_T::INTSTS1: BRKLIF0 Mask */ + +#define EPWM_INTSTS1_BRKLIF1_Pos (9) /*!< EPWM_T::INTSTS1: BRKLIF1 Position */ +#define EPWM_INTSTS1_BRKLIF1_Msk (0x1ul << EPWM_INTSTS1_BRKLIF1_Pos) /*!< EPWM_T::INTSTS1: BRKLIF1 Mask */ + +#define EPWM_INTSTS1_BRKLIF2_Pos (10) /*!< EPWM_T::INTSTS1: BRKLIF2 Position */ +#define EPWM_INTSTS1_BRKLIF2_Msk (0x1ul << EPWM_INTSTS1_BRKLIF2_Pos) /*!< EPWM_T::INTSTS1: BRKLIF2 Mask */ + +#define EPWM_INTSTS1_BRKLIF3_Pos (11) /*!< EPWM_T::INTSTS1: BRKLIF3 Position */ +#define EPWM_INTSTS1_BRKLIF3_Msk (0x1ul << EPWM_INTSTS1_BRKLIF3_Pos) /*!< EPWM_T::INTSTS1: BRKLIF3 Mask */ + +#define EPWM_INTSTS1_BRKLIF4_Pos (12) /*!< EPWM_T::INTSTS1: BRKLIF4 Position */ +#define EPWM_INTSTS1_BRKLIF4_Msk (0x1ul << EPWM_INTSTS1_BRKLIF4_Pos) /*!< EPWM_T::INTSTS1: BRKLIF4 Mask */ + +#define EPWM_INTSTS1_BRKLIF5_Pos (13) /*!< EPWM_T::INTSTS1: BRKLIF5 Position */ +#define EPWM_INTSTS1_BRKLIF5_Msk (0x1ul << EPWM_INTSTS1_BRKLIF5_Pos) /*!< EPWM_T::INTSTS1: BRKLIF5 Mask */ + +#define EPWM_INTSTS1_BRKESTS0_Pos (16) /*!< EPWM_T::INTSTS1: BRKESTS0 Position */ +#define EPWM_INTSTS1_BRKESTS0_Msk (0x1ul << EPWM_INTSTS1_BRKESTS0_Pos) /*!< EPWM_T::INTSTS1: BRKESTS0 Mask */ + +#define EPWM_INTSTS1_BRKESTS1_Pos (17) /*!< EPWM_T::INTSTS1: BRKESTS1 Position */ +#define EPWM_INTSTS1_BRKESTS1_Msk (0x1ul << EPWM_INTSTS1_BRKESTS1_Pos) /*!< EPWM_T::INTSTS1: BRKESTS1 Mask */ + +#define EPWM_INTSTS1_BRKESTS2_Pos (18) /*!< EPWM_T::INTSTS1: BRKESTS2 Position */ +#define EPWM_INTSTS1_BRKESTS2_Msk (0x1ul << EPWM_INTSTS1_BRKESTS2_Pos) /*!< EPWM_T::INTSTS1: BRKESTS2 Mask */ + +#define EPWM_INTSTS1_BRKESTS3_Pos (19) /*!< EPWM_T::INTSTS1: BRKESTS3 Position */ +#define EPWM_INTSTS1_BRKESTS3_Msk (0x1ul << EPWM_INTSTS1_BRKESTS3_Pos) /*!< EPWM_T::INTSTS1: BRKESTS3 Mask */ + +#define EPWM_INTSTS1_BRKESTS4_Pos (20) /*!< EPWM_T::INTSTS1: BRKESTS4 Position */ +#define EPWM_INTSTS1_BRKESTS4_Msk (0x1ul << EPWM_INTSTS1_BRKESTS4_Pos) /*!< EPWM_T::INTSTS1: BRKESTS4 Mask */ + +#define EPWM_INTSTS1_BRKESTS5_Pos (21) /*!< EPWM_T::INTSTS1: BRKESTS5 Position */ +#define EPWM_INTSTS1_BRKESTS5_Msk (0x1ul << EPWM_INTSTS1_BRKESTS5_Pos) /*!< EPWM_T::INTSTS1: BRKESTS5 Mask */ + +#define EPWM_INTSTS1_BRKLSTS0_Pos (24) /*!< EPWM_T::INTSTS1: BRKLSTS0 Position */ +#define EPWM_INTSTS1_BRKLSTS0_Msk (0x1ul << EPWM_INTSTS1_BRKLSTS0_Pos) /*!< EPWM_T::INTSTS1: BRKLSTS0 Mask */ + +#define EPWM_INTSTS1_BRKLSTS1_Pos (25) /*!< EPWM_T::INTSTS1: BRKLSTS1 Position */ +#define EPWM_INTSTS1_BRKLSTS1_Msk (0x1ul << EPWM_INTSTS1_BRKLSTS1_Pos) /*!< EPWM_T::INTSTS1: BRKLSTS1 Mask */ + +#define EPWM_INTSTS1_BRKLSTS2_Pos (26) /*!< EPWM_T::INTSTS1: BRKLSTS2 Position */ +#define EPWM_INTSTS1_BRKLSTS2_Msk (0x1ul << EPWM_INTSTS1_BRKLSTS2_Pos) /*!< EPWM_T::INTSTS1: BRKLSTS2 Mask */ + +#define EPWM_INTSTS1_BRKLSTS3_Pos (27) /*!< EPWM_T::INTSTS1: BRKLSTS3 Position */ +#define EPWM_INTSTS1_BRKLSTS3_Msk (0x1ul << EPWM_INTSTS1_BRKLSTS3_Pos) /*!< EPWM_T::INTSTS1: BRKLSTS3 Mask */ + +#define EPWM_INTSTS1_BRKLSTS4_Pos (28) /*!< EPWM_T::INTSTS1: BRKLSTS4 Position */ +#define EPWM_INTSTS1_BRKLSTS4_Msk (0x1ul << EPWM_INTSTS1_BRKLSTS4_Pos) /*!< EPWM_T::INTSTS1: BRKLSTS4 Mask */ + +#define EPWM_INTSTS1_BRKLSTS5_Pos (29) /*!< EPWM_T::INTSTS1: BRKLSTS5 Position */ +#define EPWM_INTSTS1_BRKLSTS5_Msk (0x1ul << EPWM_INTSTS1_BRKLSTS5_Pos) /*!< EPWM_T::INTSTS1: BRKLSTS5 Mask */ + +#define EPWM_DACTRGEN_ZTE0_Pos (0) /*!< EPWM_T::DACTRGEN: ZTE0 Position */ +#define EPWM_DACTRGEN_ZTE0_Msk (0x1ul << EPWM_DACTRGEN_ZTE0_Pos) /*!< EPWM_T::DACTRGEN: ZTE0 Mask */ + +#define EPWM_DACTRGEN_ZTE1_Pos (1) /*!< EPWM_T::DACTRGEN: ZTE1 Position */ +#define EPWM_DACTRGEN_ZTE1_Msk (0x1ul << EPWM_DACTRGEN_ZTE1_Pos) /*!< EPWM_T::DACTRGEN: ZTE1 Mask */ + +#define EPWM_DACTRGEN_ZTE2_Pos (2) /*!< EPWM_T::DACTRGEN: ZTE2 Position */ +#define EPWM_DACTRGEN_ZTE2_Msk (0x1ul << EPWM_DACTRGEN_ZTE2_Pos) /*!< EPWM_T::DACTRGEN: ZTE2 Mask */ + +#define EPWM_DACTRGEN_ZTE3_Pos (3) /*!< EPWM_T::DACTRGEN: ZTE3 Position */ +#define EPWM_DACTRGEN_ZTE3_Msk (0x1ul << EPWM_DACTRGEN_ZTE3_Pos) /*!< EPWM_T::DACTRGEN: ZTE3 Mask */ + +#define EPWM_DACTRGEN_ZTE4_Pos (4) /*!< EPWM_T::DACTRGEN: ZTE4 Position */ +#define EPWM_DACTRGEN_ZTE4_Msk (0x1ul << EPWM_DACTRGEN_ZTE4_Pos) /*!< EPWM_T::DACTRGEN: ZTE4 Mask */ + +#define EPWM_DACTRGEN_ZTE5_Pos (5) /*!< EPWM_T::DACTRGEN: ZTE5 Position */ +#define EPWM_DACTRGEN_ZTE5_Msk (0x1ul << EPWM_DACTRGEN_ZTE5_Pos) /*!< EPWM_T::DACTRGEN: ZTE5 Mask */ + +#define EPWM_DACTRGEN_PTE0_Pos (8) /*!< EPWM_T::DACTRGEN: PTE0 Position */ +#define EPWM_DACTRGEN_PTE0_Msk (0x1ul << EPWM_DACTRGEN_PTE0_Pos) /*!< EPWM_T::DACTRGEN: PTE0 Mask */ + +#define EPWM_DACTRGEN_PTE1_Pos (9) /*!< EPWM_T::DACTRGEN: PTE1 Position */ +#define EPWM_DACTRGEN_PTE1_Msk (0x1ul << EPWM_DACTRGEN_PTE1_Pos) /*!< EPWM_T::DACTRGEN: PTE1 Mask */ + +#define EPWM_DACTRGEN_PTE2_Pos (10) /*!< EPWM_T::DACTRGEN: PTE2 Position */ +#define EPWM_DACTRGEN_PTE2_Msk (0x1ul << EPWM_DACTRGEN_PTE2_Pos) /*!< EPWM_T::DACTRGEN: PTE2 Mask */ + +#define EPWM_DACTRGEN_PTE3_Pos (11) /*!< EPWM_T::DACTRGEN: PTE3 Position */ +#define EPWM_DACTRGEN_PTE3_Msk (0x1ul << EPWM_DACTRGEN_PTE3_Pos) /*!< EPWM_T::DACTRGEN: PTE3 Mask */ + +#define EPWM_DACTRGEN_PTE4_Pos (12) /*!< EPWM_T::DACTRGEN: PTE4 Position */ +#define EPWM_DACTRGEN_PTE4_Msk (0x1ul << EPWM_DACTRGEN_PTE4_Pos) /*!< EPWM_T::DACTRGEN: PTE4 Mask */ + +#define EPWM_DACTRGEN_PTE5_Pos (13) /*!< EPWM_T::DACTRGEN: PTE5 Position */ +#define EPWM_DACTRGEN_PTE5_Msk (0x1ul << EPWM_DACTRGEN_PTE5_Pos) /*!< EPWM_T::DACTRGEN: PTE5 Mask */ + +#define EPWM_DACTRGEN_CUTRGE0_Pos (16) /*!< EPWM_T::DACTRGEN: CUTRGE0 Position */ +#define EPWM_DACTRGEN_CUTRGE0_Msk (0x1ul << EPWM_DACTRGEN_CUTRGE0_Pos) /*!< EPWM_T::DACTRGEN: CUTRGE0 Mask */ + +#define EPWM_DACTRGEN_CUTRGE1_Pos (17) /*!< EPWM_T::DACTRGEN: CUTRGE1 Position */ +#define EPWM_DACTRGEN_CUTRGE1_Msk (0x1ul << EPWM_DACTRGEN_CUTRGE1_Pos) /*!< EPWM_T::DACTRGEN: CUTRGE1 Mask */ + +#define EPWM_DACTRGEN_CUTRGE2_Pos (18) /*!< EPWM_T::DACTRGEN: CUTRGE2 Position */ +#define EPWM_DACTRGEN_CUTRGE2_Msk (0x1ul << EPWM_DACTRGEN_CUTRGE2_Pos) /*!< EPWM_T::DACTRGEN: CUTRGE2 Mask */ + +#define EPWM_DACTRGEN_CUTRGE3_Pos (19) /*!< EPWM_T::DACTRGEN: CUTRGE3 Position */ +#define EPWM_DACTRGEN_CUTRGE3_Msk (0x1ul << EPWM_DACTRGEN_CUTRGE3_Pos) /*!< EPWM_T::DACTRGEN: CUTRGE3 Mask */ + +#define EPWM_DACTRGEN_CUTRGE4_Pos (20) /*!< EPWM_T::DACTRGEN: CUTRGE4 Position */ +#define EPWM_DACTRGEN_CUTRGE4_Msk (0x1ul << EPWM_DACTRGEN_CUTRGE4_Pos) /*!< EPWM_T::DACTRGEN: CUTRGE4 Mask */ + +#define EPWM_DACTRGEN_CUTRGE5_Pos (21) /*!< EPWM_T::DACTRGEN: CUTRGE5 Position */ +#define EPWM_DACTRGEN_CUTRGE5_Msk (0x1ul << EPWM_DACTRGEN_CUTRGE5_Pos) /*!< EPWM_T::DACTRGEN: CUTRGE5 Mask */ + +#define EPWM_DACTRGEN_CDTRGE0_Pos (24) /*!< EPWM_T::DACTRGEN: CDTRGE0 Position */ +#define EPWM_DACTRGEN_CDTRGE0_Msk (0x1ul << EPWM_DACTRGEN_CDTRGE0_Pos) /*!< EPWM_T::DACTRGEN: CDTRGE0 Mask */ + +#define EPWM_DACTRGEN_CDTRGE1_Pos (25) /*!< EPWM_T::DACTRGEN: CDTRGE1 Position */ +#define EPWM_DACTRGEN_CDTRGE1_Msk (0x1ul << EPWM_DACTRGEN_CDTRGE1_Pos) /*!< EPWM_T::DACTRGEN: CDTRGE1 Mask */ + +#define EPWM_DACTRGEN_CDTRGE2_Pos (26) /*!< EPWM_T::DACTRGEN: CDTRGE2 Position */ +#define EPWM_DACTRGEN_CDTRGE2_Msk (0x1ul << EPWM_DACTRGEN_CDTRGE2_Pos) /*!< EPWM_T::DACTRGEN: CDTRGE2 Mask */ + +#define EPWM_DACTRGEN_CDTRGE3_Pos (27) /*!< EPWM_T::DACTRGEN: CDTRGE3 Position */ +#define EPWM_DACTRGEN_CDTRGE3_Msk (0x1ul << EPWM_DACTRGEN_CDTRGE3_Pos) /*!< EPWM_T::DACTRGEN: CDTRGE3 Mask */ + +#define EPWM_DACTRGEN_CDTRGE4_Pos (28) /*!< EPWM_T::DACTRGEN: CDTRGE4 Position */ +#define EPWM_DACTRGEN_CDTRGE4_Msk (0x1ul << EPWM_DACTRGEN_CDTRGE4_Pos) /*!< EPWM_T::DACTRGEN: CDTRGE4 Mask */ + +#define EPWM_DACTRGEN_CDTRGE5_Pos (29) /*!< EPWM_T::DACTRGEN: CDTRGE5 Position */ +#define EPWM_DACTRGEN_CDTRGE5_Msk (0x1ul << EPWM_DACTRGEN_CDTRGE5_Pos) /*!< EPWM_T::DACTRGEN: CDTRGE5 Mask */ + +#define EPWM_EADCTS0_TRGSEL0_Pos (0) /*!< EPWM_T::EADCTS0: TRGSEL0 Position */ +#define EPWM_EADCTS0_TRGSEL0_Msk (0xful << EPWM_EADCTS0_TRGSEL0_Pos) /*!< EPWM_T::EADCTS0: TRGSEL0 Mask */ + +#define EPWM_EADCTS0_TRGEN0_Pos (7) /*!< EPWM_T::EADCTS0: TRGEN0 Position */ +#define EPWM_EADCTS0_TRGEN0_Msk (0x1ul << EPWM_EADCTS0_TRGEN0_Pos) /*!< EPWM_T::EADCTS0: TRGEN0 Mask */ + +#define EPWM_EADCTS0_TRGSEL1_Pos (8) /*!< EPWM_T::EADCTS0: TRGSEL1 Position */ +#define EPWM_EADCTS0_TRGSEL1_Msk (0xful << EPWM_EADCTS0_TRGSEL1_Pos) /*!< EPWM_T::EADCTS0: TRGSEL1 Mask */ + +#define EPWM_EADCTS0_TRGEN1_Pos (15) /*!< EPWM_T::EADCTS0: TRGEN1 Position */ +#define EPWM_EADCTS0_TRGEN1_Msk (0x1ul << EPWM_EADCTS0_TRGEN1_Pos) /*!< EPWM_T::EADCTS0: TRGEN1 Mask */ + +#define EPWM_EADCTS0_TRGSEL2_Pos (16) /*!< EPWM_T::EADCTS0: TRGSEL2 Position */ +#define EPWM_EADCTS0_TRGSEL2_Msk (0xful << EPWM_EADCTS0_TRGSEL2_Pos) /*!< EPWM_T::EADCTS0: TRGSEL2 Mask */ + +#define EPWM_EADCTS0_TRGEN2_Pos (23) /*!< EPWM_T::EADCTS0: TRGEN2 Position */ +#define EPWM_EADCTS0_TRGEN2_Msk (0x1ul << EPWM_EADCTS0_TRGEN2_Pos) /*!< EPWM_T::EADCTS0: TRGEN2 Mask */ + +#define EPWM_EADCTS0_TRGSEL3_Pos (24) /*!< EPWM_T::EADCTS0: TRGSEL3 Position */ +#define EPWM_EADCTS0_TRGSEL3_Msk (0xful << EPWM_EADCTS0_TRGSEL3_Pos) /*!< EPWM_T::EADCTS0: TRGSEL3 Mask */ + +#define EPWM_EADCTS0_TRGEN3_Pos (31) /*!< EPWM_T::EADCTS0: TRGEN3 Position */ +#define EPWM_EADCTS0_TRGEN3_Msk (0x1ul << EPWM_EADCTS0_TRGEN3_Pos) /*!< EPWM_T::EADCTS0: TRGEN3 Mask */ + +#define EPWM_EADCTS1_TRGSEL4_Pos (0) /*!< EPWM_T::EADCTS1: TRGSEL4 Position */ +#define EPWM_EADCTS1_TRGSEL4_Msk (0xful << EPWM_EADCTS1_TRGSEL4_Pos) /*!< EPWM_T::EADCTS1: TRGSEL4 Mask */ + +#define EPWM_EADCTS1_TRGEN4_Pos (7) /*!< EPWM_T::EADCTS1: TRGEN4 Position */ +#define EPWM_EADCTS1_TRGEN4_Msk (0x1ul << EPWM_EADCTS1_TRGEN4_Pos) /*!< EPWM_T::EADCTS1: TRGEN4 Mask */ + +#define EPWM_EADCTS1_TRGSEL5_Pos (8) /*!< EPWM_T::EADCTS1: TRGSEL5 Position */ +#define EPWM_EADCTS1_TRGSEL5_Msk (0xful << EPWM_EADCTS1_TRGSEL5_Pos) /*!< EPWM_T::EADCTS1: TRGSEL5 Mask */ + +#define EPWM_EADCTS1_TRGEN5_Pos (15) /*!< EPWM_T::EADCTS1: TRGEN5 Position */ +#define EPWM_EADCTS1_TRGEN5_Msk (0x1ul << EPWM_EADCTS1_TRGEN5_Pos) /*!< EPWM_T::EADCTS1: TRGEN5 Mask */ + +#define EPWM_FTCMPDAT0_1_FTCMP_Pos (0) /*!< EPWM_T::FTCMPDAT0_1: FTCMP Position */ +#define EPWM_FTCMPDAT0_1_FTCMP_Msk (0xfffful << EPWM_FTCMPDAT0_1_FTCMP_Pos) /*!< EPWM_T::FTCMPDAT0_1: FTCMP Mask */ + +#define EPWM_FTCMPDAT2_3_FTCMP_Pos (0) /*!< EPWM_T::FTCMPDAT2_3: FTCMP Position */ +#define EPWM_FTCMPDAT2_3_FTCMP_Msk (0xfffful << EPWM_FTCMPDAT2_3_FTCMP_Pos) /*!< EPWM_T::FTCMPDAT2_3: FTCMP Mask */ + +#define EPWM_FTCMPDAT4_5_FTCMP_Pos (0) /*!< EPWM_T::FTCMPDAT4_5: FTCMP Position */ +#define EPWM_FTCMPDAT4_5_FTCMP_Msk (0xfffful << EPWM_FTCMPDAT4_5_FTCMP_Pos) /*!< EPWM_T::FTCMPDAT4_5: FTCMP Mask */ + +#define EPWM_SSCTL_SSEN0_Pos (0) /*!< EPWM_T::SSCTL: SSEN0 Position */ +#define EPWM_SSCTL_SSEN0_Msk (0x1ul << EPWM_SSCTL_SSEN0_Pos) /*!< EPWM_T::SSCTL: SSEN0 Mask */ + +#define EPWM_SSCTL_SSEN1_Pos (1) /*!< EPWM_T::SSCTL: SSEN1 Position */ +#define EPWM_SSCTL_SSEN1_Msk (0x1ul << EPWM_SSCTL_SSEN1_Pos) /*!< EPWM_T::SSCTL: SSEN1 Mask */ + +#define EPWM_SSCTL_SSEN2_Pos (2) /*!< EPWM_T::SSCTL: SSEN2 Position */ +#define EPWM_SSCTL_SSEN2_Msk (0x1ul << EPWM_SSCTL_SSEN2_Pos) /*!< EPWM_T::SSCTL: SSEN2 Mask */ + +#define EPWM_SSCTL_SSEN3_Pos (3) /*!< EPWM_T::SSCTL: SSEN3 Position */ +#define EPWM_SSCTL_SSEN3_Msk (0x1ul << EPWM_SSCTL_SSEN3_Pos) /*!< EPWM_T::SSCTL: SSEN3 Mask */ + +#define EPWM_SSCTL_SSEN4_Pos (4) /*!< EPWM_T::SSCTL: SSEN4 Position */ +#define EPWM_SSCTL_SSEN4_Msk (0x1ul << EPWM_SSCTL_SSEN4_Pos) /*!< EPWM_T::SSCTL: SSEN4 Mask */ + +#define EPWM_SSCTL_SSEN5_Pos (5) /*!< EPWM_T::SSCTL: SSEN5 Position */ +#define EPWM_SSCTL_SSEN5_Msk (0x1ul << EPWM_SSCTL_SSEN5_Pos) /*!< EPWM_T::SSCTL: SSEN5 Mask */ + +#define EPWM_SSCTL_SSRC_Pos (8) /*!< EPWM_T::SSCTL: SSRC Position */ +#define EPWM_SSCTL_SSRC_Msk (0x3ul << EPWM_SSCTL_SSRC_Pos) /*!< EPWM_T::SSCTL: SSRC Mask */ + +#define EPWM_SSTRG_CNTSEN_Pos (0) /*!< EPWM_T::SSTRG: CNTSEN Position */ +#define EPWM_SSTRG_CNTSEN_Msk (0x1ul << EPWM_SSTRG_CNTSEN_Pos) /*!< EPWM_T::SSTRG: CNTSEN Mask */ + +#define EPWM_LEBCTL_LEBEN_Pos (0) /*!< EPWM_T::LEBCTL: LEBEN Position */ +#define EPWM_LEBCTL_LEBEN_Msk (0x1ul << EPWM_LEBCTL_LEBEN_Pos) /*!< EPWM_T::LEBCTL: LEBEN Mask */ + +#define EPWM_LEBCTL_SRCEN0_Pos (8) /*!< EPWM_T::LEBCTL: SRCEN0 Position */ +#define EPWM_LEBCTL_SRCEN0_Msk (0x1ul << EPWM_LEBCTL_SRCEN0_Pos) /*!< EPWM_T::LEBCTL: SRCEN0 Mask */ + +#define EPWM_LEBCTL_SRCEN2_Pos (9) /*!< EPWM_T::LEBCTL: SRCEN2 Position */ +#define EPWM_LEBCTL_SRCEN2_Msk (0x1ul << EPWM_LEBCTL_SRCEN2_Pos) /*!< EPWM_T::LEBCTL: SRCEN2 Mask */ + +#define EPWM_LEBCTL_SRCEN4_Pos (10) /*!< EPWM_T::LEBCTL: SRCEN4 Position */ +#define EPWM_LEBCTL_SRCEN4_Msk (0x1ul << EPWM_LEBCTL_SRCEN4_Pos) /*!< EPWM_T::LEBCTL: SRCEN4 Mask */ + +#define EPWM_LEBCTL_TRGTYPE_Pos (16) /*!< EPWM_T::LEBCTL: TRGTYPE Position */ +#define EPWM_LEBCTL_TRGTYPE_Msk (0x3ul << EPWM_LEBCTL_TRGTYPE_Pos) /*!< EPWM_T::LEBCTL: TRGTYPE Mask */ + +#define EPWM_LEBCNT_LEBCNT_Pos (0) /*!< EPWM_T::LEBCNT: LEBCNT Position */ +#define EPWM_LEBCNT_LEBCNT_Msk (0x1fful << EPWM_LEBCNT_LEBCNT_Pos) /*!< EPWM_T::LEBCNT: LEBCNT Mask */ + +#define EPWM_STATUS_CNTMAXF0_Pos (0) /*!< EPWM_T::STATUS: CNTMAXF0 Position */ +#define EPWM_STATUS_CNTMAXF0_Msk (0x1ul << EPWM_STATUS_CNTMAXF0_Pos) /*!< EPWM_T::STATUS: CNTMAXF0 Mask */ + +#define EPWM_STATUS_CNTMAXF1_Pos (1) /*!< EPWM_T::STATUS: CNTMAXF1 Position */ +#define EPWM_STATUS_CNTMAXF1_Msk (0x1ul << EPWM_STATUS_CNTMAXF1_Pos) /*!< EPWM_T::STATUS: CNTMAXF1 Mask */ + +#define EPWM_STATUS_CNTMAXF2_Pos (2) /*!< EPWM_T::STATUS: CNTMAXF2 Position */ +#define EPWM_STATUS_CNTMAXF2_Msk (0x1ul << EPWM_STATUS_CNTMAXF2_Pos) /*!< EPWM_T::STATUS: CNTMAXF2 Mask */ + +#define EPWM_STATUS_CNTMAXF3_Pos (3) /*!< EPWM_T::STATUS: CNTMAXF3 Position */ +#define EPWM_STATUS_CNTMAXF3_Msk (0x1ul << EPWM_STATUS_CNTMAXF3_Pos) /*!< EPWM_T::STATUS: CNTMAXF3 Mask */ + +#define EPWM_STATUS_CNTMAXF4_Pos (4) /*!< EPWM_T::STATUS: CNTMAXF4 Position */ +#define EPWM_STATUS_CNTMAXF4_Msk (0x1ul << EPWM_STATUS_CNTMAXF4_Pos) /*!< EPWM_T::STATUS: CNTMAXF4 Mask */ + +#define EPWM_STATUS_CNTMAXF5_Pos (5) /*!< EPWM_T::STATUS: CNTMAXF5 Position */ +#define EPWM_STATUS_CNTMAXF5_Msk (0x1ul << EPWM_STATUS_CNTMAXF5_Pos) /*!< EPWM_T::STATUS: CNTMAXF5 Mask */ + +#define EPWM_STATUS_SYNCINF0_Pos (8) /*!< EPWM_T::STATUS: SYNCINF0 Position */ +#define EPWM_STATUS_SYNCINF0_Msk (0x1ul << EPWM_STATUS_SYNCINF0_Pos) /*!< EPWM_T::STATUS: SYNCINF0 Mask */ + +#define EPWM_STATUS_SYNCINF2_Pos (9) /*!< EPWM_T::STATUS: SYNCINF2 Position */ +#define EPWM_STATUS_SYNCINF2_Msk (0x1ul << EPWM_STATUS_SYNCINF2_Pos) /*!< EPWM_T::STATUS: SYNCINF2 Mask */ + +#define EPWM_STATUS_SYNCINF4_Pos (10) /*!< EPWM_T::STATUS: SYNCINF4 Position */ +#define EPWM_STATUS_SYNCINF4_Msk (0x1ul << EPWM_STATUS_SYNCINF4_Pos) /*!< EPWM_T::STATUS: SYNCINF4 Mask */ + +#define EPWM_STATUS_EADCTRGF0_Pos (16) /*!< EPWM_T::STATUS: EADCTRGF0 Position */ +#define EPWM_STATUS_EADCTRGF0_Msk (0x1ul << EPWM_STATUS_EADCTRGF0_Pos) /*!< EPWM_T::STATUS: EADCTRGF0 Mask */ + +#define EPWM_STATUS_EADCTRGF1_Pos (17) /*!< EPWM_T::STATUS: EADCTRGF1 Position */ +#define EPWM_STATUS_EADCTRGF1_Msk (0x1ul << EPWM_STATUS_EADCTRGF1_Pos) /*!< EPWM_T::STATUS: EADCTRGF1 Mask */ + +#define EPWM_STATUS_EADCTRGF2_Pos (18) /*!< EPWM_T::STATUS: EADCTRGF2 Position */ +#define EPWM_STATUS_EADCTRGF2_Msk (0x1ul << EPWM_STATUS_EADCTRGF2_Pos) /*!< EPWM_T::STATUS: EADCTRGF2 Mask */ + +#define EPWM_STATUS_EADCTRGF3_Pos (19) /*!< EPWM_T::STATUS: EADCTRGF3 Position */ +#define EPWM_STATUS_EADCTRGF3_Msk (0x1ul << EPWM_STATUS_EADCTRGF3_Pos) /*!< EPWM_T::STATUS: EADCTRGF3 Mask */ + +#define EPWM_STATUS_EADCTRGF4_Pos (20) /*!< EPWM_T::STATUS: EADCTRGF4 Position */ +#define EPWM_STATUS_EADCTRGF4_Msk (0x1ul << EPWM_STATUS_EADCTRGF4_Pos) /*!< EPWM_T::STATUS: EADCTRGF4 Mask */ + +#define EPWM_STATUS_EADCTRGF5_Pos (21) /*!< EPWM_T::STATUS: EADCTRGF5 Position */ +#define EPWM_STATUS_EADCTRGF5_Msk (0x1ul << EPWM_STATUS_EADCTRGF5_Pos) /*!< EPWM_T::STATUS: EADCTRGF5 Mask */ + +#define EPWM_STATUS_DACTRGF_Pos (24) /*!< EPWM_T::STATUS: DACTRGF Position */ +#define EPWM_STATUS_DACTRGF_Msk (0x1ul << EPWM_STATUS_DACTRGF_Pos) /*!< EPWM_T::STATUS: DACTRGF Mask */ + +#define EPWM_IFA0_IFACNT_Pos (0) /*!< EPWM_T::IFA0: IFACNT Position */ +#define EPWM_IFA0_IFACNT_Msk (0xfffful << EPWM_IFA0_IFACNT_Pos) /*!< EPWM_T::IFA0: IFACNT Mask */ + +#define EPWM_IFA0_STPMOD_Pos (24) /*!< EPWM_T::IFA0: STPMOD Position */ +#define EPWM_IFA0_STPMOD_Msk (0x1ul << EPWM_IFA0_STPMOD_Pos) /*!< EPWM_T::IFA0: STPMOD Mask */ + +#define EPWM_IFA0_IFASEL_Pos (28) /*!< EPWM_T::IFA0: IFASEL Position */ +#define EPWM_IFA0_IFASEL_Msk (0x3ul << EPWM_IFA0_IFASEL_Pos) /*!< EPWM_T::IFA0: IFASEL Mask */ + +#define EPWM_IFA0_IFAEN_Pos (31) /*!< EPWM_T::IFA0: IFAEN Position */ +#define EPWM_IFA0_IFAEN_Msk (0x1ul << EPWM_IFA0_IFAEN_Pos) /*!< EPWM_T::IFA0: IFAEN Mask */ + +#define EPWM_IFA1_IFACNT_Pos (0) /*!< EPWM_T::IFA1: IFACNT Position */ +#define EPWM_IFA1_IFACNT_Msk (0xfffful << EPWM_IFA1_IFACNT_Pos) /*!< EPWM_T::IFA1: IFACNT Mask */ + +#define EPWM_IFA1_STPMOD_Pos (24) /*!< EPWM_T::IFA1: STPMOD Position */ +#define EPWM_IFA1_STPMOD_Msk (0x1ul << EPWM_IFA1_STPMOD_Pos) /*!< EPWM_T::IFA1: STPMOD Mask */ + +#define EPWM_IFA1_IFASEL_Pos (28) /*!< EPWM_T::IFA1: IFASEL Position */ +#define EPWM_IFA1_IFASEL_Msk (0x3ul << EPWM_IFA1_IFASEL_Pos) /*!< EPWM_T::IFA1: IFASEL Mask */ + +#define EPWM_IFA1_IFAEN_Pos (31) /*!< EPWM_T::IFA1: IFAEN Position */ +#define EPWM_IFA1_IFAEN_Msk (0x1ul << EPWM_IFA1_IFAEN_Pos) /*!< EPWM_T::IFA1: IFAEN Mask */ + +#define EPWM_IFA2_IFACNT_Pos (0) /*!< EPWM_T::IFA2: IFACNT Position */ +#define EPWM_IFA2_IFACNT_Msk (0xfffful << EPWM_IFA2_IFACNT_Pos) /*!< EPWM_T::IFA2: IFACNT Mask */ + +#define EPWM_IFA2_STPMOD_Pos (24) /*!< EPWM_T::IFA2: STPMOD Position */ +#define EPWM_IFA2_STPMOD_Msk (0x1ul << EPWM_IFA2_STPMOD_Pos) /*!< EPWM_T::IFA2: STPMOD Mask */ + +#define EPWM_IFA2_IFASEL_Pos (28) /*!< EPWM_T::IFA2: IFASEL Position */ +#define EPWM_IFA2_IFASEL_Msk (0x3ul << EPWM_IFA2_IFASEL_Pos) /*!< EPWM_T::IFA2: IFASEL Mask */ + +#define EPWM_IFA2_IFAEN_Pos (31) /*!< EPWM_T::IFA2: IFAEN Position */ +#define EPWM_IFA2_IFAEN_Msk (0x1ul << EPWM_IFA2_IFAEN_Pos) /*!< EPWM_T::IFA2: IFAEN Mask */ + +#define EPWM_IFA3_IFACNT_Pos (0) /*!< EPWM_T::IFA3: IFACNT Position */ +#define EPWM_IFA3_IFACNT_Msk (0xfffful << EPWM_IFA3_IFACNT_Pos) /*!< EPWM_T::IFA3: IFACNT Mask */ + +#define EPWM_IFA3_STPMOD_Pos (24) /*!< EPWM_T::IFA3: STPMOD Position */ +#define EPWM_IFA3_STPMOD_Msk (0x1ul << EPWM_IFA3_STPMOD_Pos) /*!< EPWM_T::IFA3: STPMOD Mask */ + +#define EPWM_IFA3_IFASEL_Pos (28) /*!< EPWM_T::IFA3: IFASEL Position */ +#define EPWM_IFA3_IFASEL_Msk (0x3ul << EPWM_IFA3_IFASEL_Pos) /*!< EPWM_T::IFA3: IFASEL Mask */ + +#define EPWM_IFA3_IFAEN_Pos (31) /*!< EPWM_T::IFA3: IFAEN Position */ +#define EPWM_IFA3_IFAEN_Msk (0x1ul << EPWM_IFA3_IFAEN_Pos) /*!< EPWM_T::IFA3: IFAEN Mask */ + +#define EPWM_IFA4_IFACNT_Pos (0) /*!< EPWM_T::IFA4: IFACNT Position */ +#define EPWM_IFA4_IFACNT_Msk (0xfffful << EPWM_IFA4_IFACNT_Pos) /*!< EPWM_T::IFA4: IFACNT Mask */ + +#define EPWM_IFA4_STPMOD_Pos (24) /*!< EPWM_T::IFA4: STPMOD Position */ +#define EPWM_IFA4_STPMOD_Msk (0x1ul << EPWM_IFA4_STPMOD_Pos) /*!< EPWM_T::IFA4: STPMOD Mask */ + +#define EPWM_IFA4_IFASEL_Pos (28) /*!< EPWM_T::IFA4: IFASEL Position */ +#define EPWM_IFA4_IFASEL_Msk (0x3ul << EPWM_IFA4_IFASEL_Pos) /*!< EPWM_T::IFA4: IFASEL Mask */ + +#define EPWM_IFA4_IFAEN_Pos (31) /*!< EPWM_T::IFA4: IFAEN Position */ +#define EPWM_IFA4_IFAEN_Msk (0x1ul << EPWM_IFA4_IFAEN_Pos) /*!< EPWM_T::IFA4: IFAEN Mask */ + +#define EPWM_IFA5_IFACNT_Pos (0) /*!< EPWM_T::IFA5: IFACNT Position */ +#define EPWM_IFA5_IFACNT_Msk (0xfffful << EPWM_IFA5_IFACNT_Pos) /*!< EPWM_T::IFA5: IFACNT Mask */ + +#define EPWM_IFA5_STPMOD_Pos (24) /*!< EPWM_T::IFA5: STPMOD Position */ +#define EPWM_IFA5_STPMOD_Msk (0x1ul << EPWM_IFA5_STPMOD_Pos) /*!< EPWM_T::IFA5: STPMOD Mask */ + +#define EPWM_IFA5_IFASEL_Pos (28) /*!< EPWM_T::IFA5: IFASEL Position */ +#define EPWM_IFA5_IFASEL_Msk (0x3ul << EPWM_IFA5_IFASEL_Pos) /*!< EPWM_T::IFA5: IFASEL Mask */ + +#define EPWM_IFA5_IFAEN_Pos (31) /*!< EPWM_T::IFA5: IFAEN Position */ +#define EPWM_IFA5_IFAEN_Msk (0x1ul << EPWM_IFA5_IFAEN_Pos) /*!< EPWM_T::IFA5: IFAEN Mask */ + +#define EPWM_AINTSTS_IFAIF0_Pos (0) /*!< EPWM_T::AINTSTS: IFAIF0 Position */ +#define EPWM_AINTSTS_IFAIF0_Msk (0x1ul << EPWM_AINTSTS_IFAIF0_Pos) /*!< EPWM_T::AINTSTS: IFAIF0 Mask */ + +#define EPWM_AINTSTS_IFAIF1_Pos (1) /*!< EPWM_T::AINTSTS: IFAIF1 Position */ +#define EPWM_AINTSTS_IFAIF1_Msk (0x1ul << EPWM_AINTSTS_IFAIF1_Pos) /*!< EPWM_T::AINTSTS: IFAIF1 Mask */ + +#define EPWM_AINTSTS_IFAIF2_Pos (2) /*!< EPWM_T::AINTSTS: IFAIF2 Position */ +#define EPWM_AINTSTS_IFAIF2_Msk (0x1ul << EPWM_AINTSTS_IFAIF2_Pos) /*!< EPWM_T::AINTSTS: IFAIF2 Mask */ + +#define EPWM_AINTSTS_IFAIF3_Pos (3) /*!< EPWM_T::AINTSTS: IFAIF3 Position */ +#define EPWM_AINTSTS_IFAIF3_Msk (0x1ul << EPWM_AINTSTS_IFAIF3_Pos) /*!< EPWM_T::AINTSTS: IFAIF3 Mask */ + +#define EPWM_AINTSTS_IFAIF4_Pos (4) /*!< EPWM_T::AINTSTS: IFAIF4 Position */ +#define EPWM_AINTSTS_IFAIF4_Msk (0x1ul << EPWM_AINTSTS_IFAIF4_Pos) /*!< EPWM_T::AINTSTS: IFAIF4 Mask */ + +#define EPWM_AINTSTS_IFAIF5_Pos (5) /*!< EPWM_T::AINTSTS: IFAIF5 Position */ +#define EPWM_AINTSTS_IFAIF5_Msk (0x1ul << EPWM_AINTSTS_IFAIF5_Pos) /*!< EPWM_T::AINTSTS: IFAIF5 Mask */ + +#define EPWM_AINTEN_IFAIEN0_Pos (0) /*!< EPWM_T::AINTEN: IFAIEN0 Position */ +#define EPWM_AINTEN_IFAIEN0_Msk (0x1ul << EPWM_AINTEN_IFAIEN0_Pos) /*!< EPWM_T::AINTEN: IFAIEN0 Mask */ + +#define EPWM_AINTEN_IFAIEN1_Pos (1) /*!< EPWM_T::AINTEN: IFAIEN1 Position */ +#define EPWM_AINTEN_IFAIEN1_Msk (0x1ul << EPWM_AINTEN_IFAIEN1_Pos) /*!< EPWM_T::AINTEN: IFAIEN1 Mask */ + +#define EPWM_AINTEN_IFAIEN2_Pos (2) /*!< EPWM_T::AINTEN: IFAIEN2 Position */ +#define EPWM_AINTEN_IFAIEN2_Msk (0x1ul << EPWM_AINTEN_IFAIEN2_Pos) /*!< EPWM_T::AINTEN: IFAIEN2 Mask */ + +#define EPWM_AINTEN_IFAIEN3_Pos (3) /*!< EPWM_T::AINTEN: IFAIEN3 Position */ +#define EPWM_AINTEN_IFAIEN3_Msk (0x1ul << EPWM_AINTEN_IFAIEN3_Pos) /*!< EPWM_T::AINTEN: IFAIEN3 Mask */ + +#define EPWM_AINTEN_IFAIEN4_Pos (4) /*!< EPWM_T::AINTEN: IFAIEN4 Position */ +#define EPWM_AINTEN_IFAIEN4_Msk (0x1ul << EPWM_AINTEN_IFAIEN4_Pos) /*!< EPWM_T::AINTEN: IFAIEN4 Mask */ + +#define EPWM_AINTEN_IFAIEN5_Pos (5) /*!< EPWM_T::AINTEN: IFAIEN5 Position */ +#define EPWM_AINTEN_IFAIEN5_Msk (0x1ul << EPWM_AINTEN_IFAIEN5_Pos) /*!< EPWM_T::AINTEN: IFAIEN5 Mask */ + +#define EPWM_APDMACTL_APDMAEN0_Pos (0) /*!< EPWM_T::APDMACTL: APDMAEN0 Position */ +#define EPWM_APDMACTL_APDMAEN0_Msk (0x1ul << EPWM_APDMACTL_APDMAEN0_Pos) /*!< EPWM_T::APDMACTL: APDMAEN0 Mask */ + +#define EPWM_APDMACTL_APDMAEN1_Pos (1) /*!< EPWM_T::APDMACTL: APDMAEN1 Position */ +#define EPWM_APDMACTL_APDMAEN1_Msk (0x1ul << EPWM_APDMACTL_APDMAEN1_Pos) /*!< EPWM_T::APDMACTL: APDMAEN1 Mask */ + +#define EPWM_APDMACTL_APDMAEN2_Pos (2) /*!< EPWM_T::APDMACTL: APDMAEN2 Position */ +#define EPWM_APDMACTL_APDMAEN2_Msk (0x1ul << EPWM_APDMACTL_APDMAEN2_Pos) /*!< EPWM_T::APDMACTL: APDMAEN2 Mask */ + +#define EPWM_APDMACTL_APDMAEN3_Pos (3) /*!< EPWM_T::APDMACTL: APDMAEN3 Position */ +#define EPWM_APDMACTL_APDMAEN3_Msk (0x1ul << EPWM_APDMACTL_APDMAEN3_Pos) /*!< EPWM_T::APDMACTL: APDMAEN3 Mask */ + +#define EPWM_APDMACTL_APDMAEN4_Pos (4) /*!< EPWM_T::APDMACTL: APDMAEN4 Position */ +#define EPWM_APDMACTL_APDMAEN4_Msk (0x1ul << EPWM_APDMACTL_APDMAEN4_Pos) /*!< EPWM_T::APDMACTL: APDMAEN4 Mask */ + +#define EPWM_APDMACTL_APDMAEN5_Pos (5) /*!< EPWM_T::APDMACTL: APDMAEN5 Position */ +#define EPWM_APDMACTL_APDMAEN5_Msk (0x1ul << EPWM_APDMACTL_APDMAEN5_Pos) /*!< EPWM_T::APDMACTL: APDMAEN5 Mask */ + +#define EPWM_FDEN_FDEN0_Pos (0) /*!< EPWM_T::FDEN: FDEN0 Position */ +#define EPWM_FDEN_FDEN0_Msk (0x1ul << EPWM_FDEN_FDEN0_Pos) /*!< EPWM_T::FDEN: FDEN0 Mask */ + +#define EPWM_FDEN_FDEN1_Pos (1) /*!< EPWM_T::FDEN: FDEN1 Position */ +#define EPWM_FDEN_FDEN1_Msk (0x1ul << EPWM_FDEN_FDEN1_Pos) /*!< EPWM_T::FDEN: FDEN1 Mask */ + +#define EPWM_FDEN_FDEN2_Pos (2) /*!< EPWM_T::FDEN: FDEN2 Position */ +#define EPWM_FDEN_FDEN2_Msk (0x1ul << EPWM_FDEN_FDEN2_Pos) /*!< EPWM_T::FDEN: FDEN2 Mask */ + +#define EPWM_FDEN_FDEN3_Pos (3) /*!< EPWM_T::FDEN: FDEN3 Position */ +#define EPWM_FDEN_FDEN3_Msk (0x1ul << EPWM_FDEN_FDEN3_Pos) /*!< EPWM_T::FDEN: FDEN3 Mask */ + +#define EPWM_FDEN_FDEN4_Pos (4) /*!< EPWM_T::FDEN: FDEN4 Position */ +#define EPWM_FDEN_FDEN4_Msk (0x1ul << EPWM_FDEN_FDEN4_Pos) /*!< EPWM_T::FDEN: FDEN4 Mask */ + +#define EPWM_FDEN_FDEN5_Pos (5) /*!< EPWM_T::FDEN: FDEN5 Position */ +#define EPWM_FDEN_FDEN5_Msk (0x1ul << EPWM_FDEN_FDEN5_Pos) /*!< EPWM_T::FDEN: FDEN5 Mask */ + +#define EPWM_FDEN_FDODIS0_Pos (8) /*!< EPWM_T::FDEN: FDODIS0 Position */ +#define EPWM_FDEN_FDODIS0_Msk (0x1ul << EPWM_FDEN_FDODIS0_Pos) /*!< EPWM_T::FDEN: FDODIS0 Mask */ + +#define EPWM_FDEN_FDODIS1_Pos (9) /*!< EPWM_T::FDEN: FDODIS1 Position */ +#define EPWM_FDEN_FDODIS1_Msk (0x1ul << EPWM_FDEN_FDODIS1_Pos) /*!< EPWM_T::FDEN: FDODIS1 Mask */ + +#define EPWM_FDEN_FDODIS2_Pos (10) /*!< EPWM_T::FDEN: FDODIS2 Position */ +#define EPWM_FDEN_FDODIS2_Msk (0x1ul << EPWM_FDEN_FDODIS2_Pos) /*!< EPWM_T::FDEN: FDODIS2 Mask */ + +#define EPWM_FDEN_FDODIS3_Pos (11) /*!< EPWM_T::FDEN: FDODIS3 Position */ +#define EPWM_FDEN_FDODIS3_Msk (0x1ul << EPWM_FDEN_FDODIS3_Pos) /*!< EPWM_T::FDEN: FDODIS3 Mask */ + +#define EPWM_FDEN_FDODIS4_Pos (12) /*!< EPWM_T::FDEN: FDODIS4 Position */ +#define EPWM_FDEN_FDODIS4_Msk (0x1ul << EPWM_FDEN_FDODIS4_Pos) /*!< EPWM_T::FDEN: FDODIS4 Mask */ + +#define EPWM_FDEN_FDODIS5_Pos (13) /*!< EPWM_T::FDEN: FDODIS5 Position */ +#define EPWM_FDEN_FDODIS5_Msk (0x1ul << EPWM_FDEN_FDODIS5_Pos) /*!< EPWM_T::FDEN: FDODIS5 Mask */ + +#define EPWM_FDEN_FDCKS0_Pos (16) /*!< EPWM_T::FDEN: FDCKS0 Position */ +#define EPWM_FDEN_FDCKS0_Msk (0x1ul << EPWM_FDEN_FDCKS0_Pos) /*!< EPWM_T::FDEN: FDCKS0 Mask */ + +#define EPWM_FDEN_FDCKS1_Pos (17) /*!< EPWM_T::FDEN: FDCKS1 Position */ +#define EPWM_FDEN_FDCKS1_Msk (0x1ul << EPWM_FDEN_FDCKS1_Pos) /*!< EPWM_T::FDEN: FDCKS1 Mask */ + +#define EPWM_FDEN_FDCKS2_Pos (18) /*!< EPWM_T::FDEN: FDCKS2 Position */ +#define EPWM_FDEN_FDCKS2_Msk (0x1ul << EPWM_FDEN_FDCKS2_Pos) /*!< EPWM_T::FDEN: FDCKS2 Mask */ + +#define EPWM_FDEN_FDCKS3_Pos (19) /*!< EPWM_T::FDEN: FDCKS3 Position */ +#define EPWM_FDEN_FDCKS3_Msk (0x1ul << EPWM_FDEN_FDCKS3_Pos) /*!< EPWM_T::FDEN: FDCKS3 Mask */ + +#define EPWM_FDEN_FDCKS4_Pos (20) /*!< EPWM_T::FDEN: FDCKS4 Position */ +#define EPWM_FDEN_FDCKS4_Msk (0x1ul << EPWM_FDEN_FDCKS4_Pos) /*!< EPWM_T::FDEN: FDCKS4 Mask */ + +#define EPWM_FDEN_FDCKS5_Pos (21) /*!< EPWM_T::FDEN: FDCKS5 Position */ +#define EPWM_FDEN_FDCKS5_Msk (0x1ul << EPWM_FDEN_FDCKS5_Pos) /*!< EPWM_T::FDEN: FDCKS5 Mask */ + +#define EPWM_FDCTL0_TRMSKCNT_Pos (0) /*!< EPWM_T::FDCTL0: TRMSKCNT Position */ +#define EPWM_FDCTL0_TRMSKCNT_Msk (0x7ful << EPWM_FDCTL0_TRMSKCNT_Pos) /*!< EPWM_T::FDCTL0: TRMSKCNT Mask */ + +#define EPWM_FDCTL0_FDMSKEN_Pos (15) /*!< EPWM_T::FDCTL0: FDMSKEN Position */ +#define EPWM_FDCTL0_FDMSKEN_Msk (0x1ul << EPWM_FDCTL0_FDMSKEN_Pos) /*!< EPWM_T::FDCTL0: FDMSKEN Mask */ + +#define EPWM_FDCTL0_DGSMPCYC_Pos (16) /*!< EPWM_T::FDCTL0: DGSMPCYC Position */ +#define EPWM_FDCTL0_DGSMPCYC_Msk (0x7ul << EPWM_FDCTL0_DGSMPCYC_Pos) /*!< EPWM_T::FDCTL0: DGSMPCYC Mask */ + +#define EPWM_FDCTL0_FDCKSEL_Pos (28) /*!< EPWM_T::FDCTL0: FDCKSEL Position */ +#define EPWM_FDCTL0_FDCKSEL_Msk (0x3ul << EPWM_FDCTL0_FDCKSEL_Pos) /*!< EPWM_T::FDCTL0: FDCKSEL Mask */ + +#define EPWM_FDCTL0_FDDGEN_Pos (31) /*!< EPWM_T::FDCTL0: FDDGEN Position */ +#define EPWM_FDCTL0_FDDGEN_Msk (0x1ul << EPWM_FDCTL0_FDDGEN_Pos) /*!< EPWM_T::FDCTL0: FDDGEN Mask */ + +#define EPWM_FDCTL1_TRMSKCNT_Pos (0) /*!< EPWM_T::FDCTL1: TRMSKCNT Position */ +#define EPWM_FDCTL1_TRMSKCNT_Msk (0x7ful << EPWM_FDCTL1_TRMSKCNT_Pos) /*!< EPWM_T::FDCTL1: TRMSKCNT Mask */ + +#define EPWM_FDCTL1_FDMSKEN_Pos (15) /*!< EPWM_T::FDCTL1: FDMSKEN Position */ +#define EPWM_FDCTL1_FDMSKEN_Msk (0x1ul << EPWM_FDCTL1_FDMSKEN_Pos) /*!< EPWM_T::FDCTL1: FDMSKEN Mask */ + +#define EPWM_FDCTL1_DGSMPCYC_Pos (16) /*!< EPWM_T::FDCTL1: DGSMPCYC Position */ +#define EPWM_FDCTL1_DGSMPCYC_Msk (0x7ul << EPWM_FDCTL1_DGSMPCYC_Pos) /*!< EPWM_T::FDCTL1: DGSMPCYC Mask */ + +#define EPWM_FDCTL1_FDCKSEL_Pos (28) /*!< EPWM_T::FDCTL1: FDCKSEL Position */ +#define EPWM_FDCTL1_FDCKSEL_Msk (0x3ul << EPWM_FDCTL1_FDCKSEL_Pos) /*!< EPWM_T::FDCTL1: FDCKSEL Mask */ + +#define EPWM_FDCTL1_FDDGEN_Pos (31) /*!< EPWM_T::FDCTL1: FDDGEN Position */ +#define EPWM_FDCTL1_FDDGEN_Msk (0x1ul << EPWM_FDCTL1_FDDGEN_Pos) /*!< EPWM_T::FDCTL1: FDDGEN Mask */ + +#define EPWM_FDCTL2_TRMSKCNT_Pos (0) /*!< EPWM_T::FDCTL2: TRMSKCNT Position */ +#define EPWM_FDCTL2_TRMSKCNT_Msk (0x7ful << EPWM_FDCTL2_TRMSKCNT_Pos) /*!< EPWM_T::FDCTL2: TRMSKCNT Mask */ + +#define EPWM_FDCTL2_FDMSKEN_Pos (15) /*!< EPWM_T::FDCTL2: FDMSKEN Position */ +#define EPWM_FDCTL2_FDMSKEN_Msk (0x1ul << EPWM_FDCTL2_FDMSKEN_Pos) /*!< EPWM_T::FDCTL2: FDMSKEN Mask */ + +#define EPWM_FDCTL2_DGSMPCYC_Pos (16) /*!< EPWM_T::FDCTL2: DGSMPCYC Position */ +#define EPWM_FDCTL2_DGSMPCYC_Msk (0x7ul << EPWM_FDCTL2_DGSMPCYC_Pos) /*!< EPWM_T::FDCTL2: DGSMPCYC Mask */ + +#define EPWM_FDCTL2_FDCKSEL_Pos (28) /*!< EPWM_T::FDCTL2: FDCKSEL Position */ +#define EPWM_FDCTL2_FDCKSEL_Msk (0x3ul << EPWM_FDCTL2_FDCKSEL_Pos) /*!< EPWM_T::FDCTL2: FDCKSEL Mask */ + +#define EPWM_FDCTL2_FDDGEN_Pos (31) /*!< EPWM_T::FDCTL2: FDDGEN Position */ +#define EPWM_FDCTL2_FDDGEN_Msk (0x1ul << EPWM_FDCTL2_FDDGEN_Pos) /*!< EPWM_T::FDCTL2: FDDGEN Mask */ + +#define EPWM_FDCTL3_TRMSKCNT_Pos (0) /*!< EPWM_T::FDCTL3: TRMSKCNT Position */ +#define EPWM_FDCTL3_TRMSKCNT_Msk (0x7ful << EPWM_FDCTL3_TRMSKCNT_Pos) /*!< EPWM_T::FDCTL3: TRMSKCNT Mask */ + +#define EPWM_FDCTL3_FDMSKEN_Pos (15) /*!< EPWM_T::FDCTL3: FDMSKEN Position */ +#define EPWM_FDCTL3_FDMSKEN_Msk (0x1ul << EPWM_FDCTL3_FDMSKEN_Pos) /*!< EPWM_T::FDCTL3: FDMSKEN Mask */ + +#define EPWM_FDCTL3_DGSMPCYC_Pos (16) /*!< EPWM_T::FDCTL3: DGSMPCYC Position */ +#define EPWM_FDCTL3_DGSMPCYC_Msk (0x7ul << EPWM_FDCTL3_DGSMPCYC_Pos) /*!< EPWM_T::FDCTL3: DGSMPCYC Mask */ + +#define EPWM_FDCTL3_FDCKSEL_Pos (28) /*!< EPWM_T::FDCTL3: FDCKSEL Position */ +#define EPWM_FDCTL3_FDCKSEL_Msk (0x3ul << EPWM_FDCTL3_FDCKSEL_Pos) /*!< EPWM_T::FDCTL3: FDCKSEL Mask */ + +#define EPWM_FDCTL3_FDDGEN_Pos (31) /*!< EPWM_T::FDCTL3: FDDGEN Position */ +#define EPWM_FDCTL3_FDDGEN_Msk (0x1ul << EPWM_FDCTL3_FDDGEN_Pos) /*!< EPWM_T::FDCTL3: FDDGEN Mask */ + +#define EPWM_FDCTL4_TRMSKCNT_Pos (0) /*!< EPWM_T::FDCTL4: TRMSKCNT Position */ +#define EPWM_FDCTL4_TRMSKCNT_Msk (0x7ful << EPWM_FDCTL4_TRMSKCNT_Pos) /*!< EPWM_T::FDCTL4: TRMSKCNT Mask */ + +#define EPWM_FDCTL4_FDMSKEN_Pos (15) /*!< EPWM_T::FDCTL4: FDMSKEN Position */ +#define EPWM_FDCTL4_FDMSKEN_Msk (0x1ul << EPWM_FDCTL4_FDMSKEN_Pos) /*!< EPWM_T::FDCTL4: FDMSKEN Mask */ + +#define EPWM_FDCTL4_DGSMPCYC_Pos (16) /*!< EPWM_T::FDCTL4: DGSMPCYC Position */ +#define EPWM_FDCTL4_DGSMPCYC_Msk (0x7ul << EPWM_FDCTL4_DGSMPCYC_Pos) /*!< EPWM_T::FDCTL4: DGSMPCYC Mask */ + +#define EPWM_FDCTL4_FDCKSEL_Pos (28) /*!< EPWM_T::FDCTL4: FDCKSEL Position */ +#define EPWM_FDCTL4_FDCKSEL_Msk (0x3ul << EPWM_FDCTL4_FDCKSEL_Pos) /*!< EPWM_T::FDCTL4: FDCKSEL Mask */ + +#define EPWM_FDCTL4_FDDGEN_Pos (31) /*!< EPWM_T::FDCTL4: FDDGEN Position */ +#define EPWM_FDCTL4_FDDGEN_Msk (0x1ul << EPWM_FDCTL4_FDDGEN_Pos) /*!< EPWM_T::FDCTL4: FDDGEN Mask */ + +#define EPWM_FDCTL5_TRMSKCNT_Pos (0) /*!< EPWM_T::FDCTL5: TRMSKCNT Position */ +#define EPWM_FDCTL5_TRMSKCNT_Msk (0x7ful << EPWM_FDCTL5_TRMSKCNT_Pos) /*!< EPWM_T::FDCTL5: TRMSKCNT Mask */ + +#define EPWM_FDCTL5_FDMSKEN_Pos (15) /*!< EPWM_T::FDCTL5: FDMSKEN Position */ +#define EPWM_FDCTL5_FDMSKEN_Msk (0x1ul << EPWM_FDCTL5_FDMSKEN_Pos) /*!< EPWM_T::FDCTL5: FDMSKEN Mask */ + +#define EPWM_FDCTL5_DGSMPCYC_Pos (16) /*!< EPWM_T::FDCTL5: DGSMPCYC Position */ +#define EPWM_FDCTL5_DGSMPCYC_Msk (0x7ul << EPWM_FDCTL5_DGSMPCYC_Pos) /*!< EPWM_T::FDCTL5: DGSMPCYC Mask */ + +#define EPWM_FDCTL5_FDCKSEL_Pos (28) /*!< EPWM_T::FDCTL5: FDCKSEL Position */ +#define EPWM_FDCTL5_FDCKSEL_Msk (0x3ul << EPWM_FDCTL5_FDCKSEL_Pos) /*!< EPWM_T::FDCTL5: FDCKSEL Mask */ + +#define EPWM_FDCTL5_FDDGEN_Pos (31) /*!< EPWM_T::FDCTL5: FDDGEN Position */ +#define EPWM_FDCTL5_FDDGEN_Msk (0x1ul << EPWM_FDCTL5_FDDGEN_Pos) /*!< EPWM_T::FDCTL5: FDDGEN Mask */ + +#define EPWM_FDIEN_FDIEN0_Pos (0) /*!< EPWM_T::FDIEN: FDIEN0 Position */ +#define EPWM_FDIEN_FDIEN0_Msk (0x1ul << EPWM_FDIEN_FDIEN0_Pos) /*!< EPWM_T::FDIEN: FDIEN0 Mask */ + +#define EPWM_FDIEN_FDIEN1_Pos (1) /*!< EPWM_T::FDIEN: FDIEN1 Position */ +#define EPWM_FDIEN_FDIEN1_Msk (0x1ul << EPWM_FDIEN_FDIEN1_Pos) /*!< EPWM_T::FDIEN: FDIEN1 Mask */ + +#define EPWM_FDIEN_FDIEN2_Pos (2) /*!< EPWM_T::FDIEN: FDIEN2 Position */ +#define EPWM_FDIEN_FDIEN2_Msk (0x1ul << EPWM_FDIEN_FDIEN2_Pos) /*!< EPWM_T::FDIEN: FDIEN2 Mask */ + +#define EPWM_FDIEN_FDIEN3_Pos (3) /*!< EPWM_T::FDIEN: FDIEN3 Position */ +#define EPWM_FDIEN_FDIEN3_Msk (0x1ul << EPWM_FDIEN_FDIEN3_Pos) /*!< EPWM_T::FDIEN: FDIEN3 Mask */ + +#define EPWM_FDIEN_FDIEN4_Pos (4) /*!< EPWM_T::FDIEN: FDIEN4 Position */ +#define EPWM_FDIEN_FDIEN4_Msk (0x1ul << EPWM_FDIEN_FDIEN4_Pos) /*!< EPWM_T::FDIEN: FDIEN4 Mask */ + +#define EPWM_FDIEN_FDIEN5_Pos (5) /*!< EPWM_T::FDIEN: FDIEN5 Position */ +#define EPWM_FDIEN_FDIEN5_Msk (0x1ul << EPWM_FDIEN_FDIEN5_Pos) /*!< EPWM_T::FDIEN: FDIEN5 Mask */ + +#define EPWM_FDSTS_FDIF0_Pos (0) /*!< EPWM_T::FDSTS: FDIF0 Position */ +#define EPWM_FDSTS_FDIF0_Msk (0x1ul << EPWM_FDSTS_FDIF0_Pos) /*!< EPWM_T::FDSTS: FDIF0 Mask */ + +#define EPWM_FDSTS_FDIF1_Pos (1) /*!< EPWM_T::FDSTS: FDIF1 Position */ +#define EPWM_FDSTS_FDIF1_Msk (0x1ul << EPWM_FDSTS_FDIF1_Pos) /*!< EPWM_T::FDSTS: FDIF1 Mask */ + +#define EPWM_FDSTS_FDIF2_Pos (2) /*!< EPWM_T::FDSTS: FDIF2 Position */ +#define EPWM_FDSTS_FDIF2_Msk (0x1ul << EPWM_FDSTS_FDIF2_Pos) /*!< EPWM_T::FDSTS: FDIF2 Mask */ + +#define EPWM_FDSTS_FDIF3_Pos (3) /*!< EPWM_T::FDSTS: FDIF3 Position */ +#define EPWM_FDSTS_FDIF3_Msk (0x1ul << EPWM_FDSTS_FDIF3_Pos) /*!< EPWM_T::FDSTS: FDIF3 Mask */ + +#define EPWM_FDSTS_FDIF4_Pos (4) /*!< EPWM_T::FDSTS: FDIF4 Position */ +#define EPWM_FDSTS_FDIF4_Msk (0x1ul << EPWM_FDSTS_FDIF4_Pos) /*!< EPWM_T::FDSTS: FDIF4 Mask */ + +#define EPWM_FDSTS_FDIF5_Pos (5) /*!< EPWM_T::FDSTS: FDIF5 Position */ +#define EPWM_FDSTS_FDIF5_Msk (0x1ul << EPWM_FDSTS_FDIF5_Pos) /*!< EPWM_T::FDSTS: FDIF5 Mask */ + +#define EPWM_EADCPSCCTL_PSCEN0_Pos (0) /*!< EPWM_T::EADCPSCCTL: PSCEN0 Position */ +#define EPWM_EADCPSCCTL_PSCEN0_Msk (0x1ul << EPWM_EADCPSCCTL_PSCEN0_Pos) /*!< EPWM_T::EADCPSCCTL: PSCEN0 Mask */ + +#define EPWM_EADCPSCCTL_PSCEN1_Pos (1) /*!< EPWM_T::EADCPSCCTL: PSCEN1 Position */ +#define EPWM_EADCPSCCTL_PSCEN1_Msk (0x1ul << EPWM_EADCPSCCTL_PSCEN1_Pos) /*!< EPWM_T::EADCPSCCTL: PSCEN1 Mask */ + +#define EPWM_EADCPSCCTL_PSCEN2_Pos (2) /*!< EPWM_T::EADCPSCCTL: PSCEN2 Position */ +#define EPWM_EADCPSCCTL_PSCEN2_Msk (0x1ul << EPWM_EADCPSCCTL_PSCEN2_Pos) /*!< EPWM_T::EADCPSCCTL: PSCEN2 Mask */ + +#define EPWM_EADCPSCCTL_PSCEN3_Pos (3) /*!< EPWM_T::EADCPSCCTL: PSCEN3 Position */ +#define EPWM_EADCPSCCTL_PSCEN3_Msk (0x1ul << EPWM_EADCPSCCTL_PSCEN3_Pos) /*!< EPWM_T::EADCPSCCTL: PSCEN3 Mask */ + +#define EPWM_EADCPSCCTL_PSCEN4_Pos (4) /*!< EPWM_T::EADCPSCCTL: PSCEN4 Position */ +#define EPWM_EADCPSCCTL_PSCEN4_Msk (0x1ul << EPWM_EADCPSCCTL_PSCEN4_Pos) /*!< EPWM_T::EADCPSCCTL: PSCEN4 Mask */ + +#define EPWM_EADCPSCCTL_PSCEN5_Pos (5) /*!< EPWM_T::EADCPSCCTL: PSCEN5 Position */ +#define EPWM_EADCPSCCTL_PSCEN5_Msk (0x1ul << EPWM_EADCPSCCTL_PSCEN5_Pos) /*!< EPWM_T::EADCPSCCTL: PSCEN5 Mask */ + +#define EPWM_EADCPSC0_EADCPSC0_Pos (0) /*!< EPWM_T::EADCPSC0: EADCPSC0 Position */ +#define EPWM_EADCPSC0_EADCPSC0_Msk (0xful << EPWM_EADCPSC0_EADCPSC0_Pos) /*!< EPWM_T::EADCPSC0: EADCPSC0 Mask */ + +#define EPWM_EADCPSC0_EADCPSC1_Pos (8) /*!< EPWM_T::EADCPSC0: EADCPSC1 Position */ +#define EPWM_EADCPSC0_EADCPSC1_Msk (0xful << EPWM_EADCPSC0_EADCPSC1_Pos) /*!< EPWM_T::EADCPSC0: EADCPSC1 Mask */ + +#define EPWM_EADCPSC0_EADCPSC2_Pos (16) /*!< EPWM_T::EADCPSC0: EADCPSC2 Position */ +#define EPWM_EADCPSC0_EADCPSC2_Msk (0xful << EPWM_EADCPSC0_EADCPSC2_Pos) /*!< EPWM_T::EADCPSC0: EADCPSC2 Mask */ + +#define EPWM_EADCPSC0_EADCPSC3_Pos (24) /*!< EPWM_T::EADCPSC0: EADCPSC3 Position */ +#define EPWM_EADCPSC0_EADCPSC3_Msk (0xful << EPWM_EADCPSC0_EADCPSC3_Pos) /*!< EPWM_T::EADCPSC0: EADCPSC3 Mask */ + +#define EPWM_EADCPSC1_EADCPSC4_Pos (0) /*!< EPWM_T::EADCPSC1: EADCPSC4 Position */ +#define EPWM_EADCPSC1_EADCPSC4_Msk (0xful << EPWM_EADCPSC1_EADCPSC4_Pos) /*!< EPWM_T::EADCPSC1: EADCPSC4 Mask */ + +#define EPWM_EADCPSC1_EADCPSC5_Pos (8) /*!< EPWM_T::EADCPSC1: EADCPSC5 Position */ +#define EPWM_EADCPSC1_EADCPSC5_Msk (0xful << EPWM_EADCPSC1_EADCPSC5_Pos) /*!< EPWM_T::EADCPSC1: EADCPSC5 Mask */ + +#define EPWM_EADCPSCNT0_PSCNT0_Pos (0) /*!< EPWM_T::EADCPSCNT0: PSCNT0 Position */ +#define EPWM_EADCPSCNT0_PSCNT0_Msk (0xful << EPWM_EADCPSCNT0_PSCNT0_Pos) /*!< EPWM_T::EADCPSCNT0: PSCNT0 Mask */ + +#define EPWM_EADCPSCNT0_PSCNT1_Pos (8) /*!< EPWM_T::EADCPSCNT0: PSCNT1 Position */ +#define EPWM_EADCPSCNT0_PSCNT1_Msk (0xful << EPWM_EADCPSCNT0_PSCNT1_Pos) /*!< EPWM_T::EADCPSCNT0: PSCNT1 Mask */ + +#define EPWM_EADCPSCNT0_PSCNT2_Pos (16) /*!< EPWM_T::EADCPSCNT0: PSCNT2 Position */ +#define EPWM_EADCPSCNT0_PSCNT2_Msk (0xful << EPWM_EADCPSCNT0_PSCNT2_Pos) /*!< EPWM_T::EADCPSCNT0: PSCNT2 Mask */ + +#define EPWM_EADCPSCNT0_PSCNT3_Pos (24) /*!< EPWM_T::EADCPSCNT0: PSCNT3 Position */ +#define EPWM_EADCPSCNT0_PSCNT3_Msk (0xful << EPWM_EADCPSCNT0_PSCNT3_Pos) /*!< EPWM_T::EADCPSCNT0: PSCNT3 Mask */ + +#define EPWM_EADCPSCNT1_PSCNT4_Pos (0) /*!< EPWM_T::EADCPSCNT1: PSCNT4 Position */ +#define EPWM_EADCPSCNT1_PSCNT4_Msk (0xful << EPWM_EADCPSCNT1_PSCNT4_Pos) /*!< EPWM_T::EADCPSCNT1: PSCNT4 Mask */ + +#define EPWM_EADCPSCNT1_PSCNT5_Pos (8) /*!< EPWM_T::EADCPSCNT1: PSCNT5 Position */ +#define EPWM_EADCPSCNT1_PSCNT5_Msk (0xful << EPWM_EADCPSCNT1_PSCNT5_Pos) /*!< EPWM_T::EADCPSCNT1: PSCNT5 Mask */ + +#define EPWM_CAPINEN_CAPINEN0_Pos (0) /*!< EPWM_T::CAPINEN: CAPINEN0 Position */ +#define EPWM_CAPINEN_CAPINEN0_Msk (0x1ul << EPWM_CAPINEN_CAPINEN0_Pos) /*!< EPWM_T::CAPINEN: CAPINEN0 Mask */ + +#define EPWM_CAPINEN_CAPINEN1_Pos (1) /*!< EPWM_T::CAPINEN: CAPINEN1 Position */ +#define EPWM_CAPINEN_CAPINEN1_Msk (0x1ul << EPWM_CAPINEN_CAPINEN1_Pos) /*!< EPWM_T::CAPINEN: CAPINEN1 Mask */ + +#define EPWM_CAPINEN_CAPINEN2_Pos (2) /*!< EPWM_T::CAPINEN: CAPINEN2 Position */ +#define EPWM_CAPINEN_CAPINEN2_Msk (0x1ul << EPWM_CAPINEN_CAPINEN2_Pos) /*!< EPWM_T::CAPINEN: CAPINEN2 Mask */ + +#define EPWM_CAPINEN_CAPINEN3_Pos (3) /*!< EPWM_T::CAPINEN: CAPINEN3 Position */ +#define EPWM_CAPINEN_CAPINEN3_Msk (0x1ul << EPWM_CAPINEN_CAPINEN3_Pos) /*!< EPWM_T::CAPINEN: CAPINEN3 Mask */ + +#define EPWM_CAPINEN_CAPINEN4_Pos (4) /*!< EPWM_T::CAPINEN: CAPINEN4 Position */ +#define EPWM_CAPINEN_CAPINEN4_Msk (0x1ul << EPWM_CAPINEN_CAPINEN4_Pos) /*!< EPWM_T::CAPINEN: CAPINEN4 Mask */ + +#define EPWM_CAPINEN_CAPINEN5_Pos (5) /*!< EPWM_T::CAPINEN: CAPINEN5 Position */ +#define EPWM_CAPINEN_CAPINEN5_Msk (0x1ul << EPWM_CAPINEN_CAPINEN5_Pos) /*!< EPWM_T::CAPINEN: CAPINEN5 Mask */ + +#define EPWM_CAPCTL_CAPEN0_Pos (0) /*!< EPWM_T::CAPCTL: CAPEN0 Position */ +#define EPWM_CAPCTL_CAPEN0_Msk (0x1ul << EPWM_CAPCTL_CAPEN0_Pos) /*!< EPWM_T::CAPCTL: CAPEN0 Mask */ + +#define EPWM_CAPCTL_CAPEN1_Pos (1) /*!< EPWM_T::CAPCTL: CAPEN1 Position */ +#define EPWM_CAPCTL_CAPEN1_Msk (0x1ul << EPWM_CAPCTL_CAPEN1_Pos) /*!< EPWM_T::CAPCTL: CAPEN1 Mask */ + +#define EPWM_CAPCTL_CAPEN2_Pos (2) /*!< EPWM_T::CAPCTL: CAPEN2 Position */ +#define EPWM_CAPCTL_CAPEN2_Msk (0x1ul << EPWM_CAPCTL_CAPEN2_Pos) /*!< EPWM_T::CAPCTL: CAPEN2 Mask */ + +#define EPWM_CAPCTL_CAPEN3_Pos (3) /*!< EPWM_T::CAPCTL: CAPEN3 Position */ +#define EPWM_CAPCTL_CAPEN3_Msk (0x1ul << EPWM_CAPCTL_CAPEN3_Pos) /*!< EPWM_T::CAPCTL: CAPEN3 Mask */ + +#define EPWM_CAPCTL_CAPEN4_Pos (4) /*!< EPWM_T::CAPCTL: CAPEN4 Position */ +#define EPWM_CAPCTL_CAPEN4_Msk (0x1ul << EPWM_CAPCTL_CAPEN4_Pos) /*!< EPWM_T::CAPCTL: CAPEN4 Mask */ + +#define EPWM_CAPCTL_CAPEN5_Pos (5) /*!< EPWM_T::CAPCTL: CAPEN5 Position */ +#define EPWM_CAPCTL_CAPEN5_Msk (0x1ul << EPWM_CAPCTL_CAPEN5_Pos) /*!< EPWM_T::CAPCTL: CAPEN5 Mask */ + +#define EPWM_CAPCTL_CAPINV0_Pos (8) /*!< EPWM_T::CAPCTL: CAPINV0 Position */ +#define EPWM_CAPCTL_CAPINV0_Msk (0x1ul << EPWM_CAPCTL_CAPINV0_Pos) /*!< EPWM_T::CAPCTL: CAPINV0 Mask */ + +#define EPWM_CAPCTL_CAPINV1_Pos (9) /*!< EPWM_T::CAPCTL: CAPINV1 Position */ +#define EPWM_CAPCTL_CAPINV1_Msk (0x1ul << EPWM_CAPCTL_CAPINV1_Pos) /*!< EPWM_T::CAPCTL: CAPINV1 Mask */ + +#define EPWM_CAPCTL_CAPINV2_Pos (10) /*!< EPWM_T::CAPCTL: CAPINV2 Position */ +#define EPWM_CAPCTL_CAPINV2_Msk (0x1ul << EPWM_CAPCTL_CAPINV2_Pos) /*!< EPWM_T::CAPCTL: CAPINV2 Mask */ + +#define EPWM_CAPCTL_CAPINV3_Pos (11) /*!< EPWM_T::CAPCTL: CAPINV3 Position */ +#define EPWM_CAPCTL_CAPINV3_Msk (0x1ul << EPWM_CAPCTL_CAPINV3_Pos) /*!< EPWM_T::CAPCTL: CAPINV3 Mask */ + +#define EPWM_CAPCTL_CAPINV4_Pos (12) /*!< EPWM_T::CAPCTL: CAPINV4 Position */ +#define EPWM_CAPCTL_CAPINV4_Msk (0x1ul << EPWM_CAPCTL_CAPINV4_Pos) /*!< EPWM_T::CAPCTL: CAPINV4 Mask */ + +#define EPWM_CAPCTL_CAPINV5_Pos (13) /*!< EPWM_T::CAPCTL: CAPINV5 Position */ +#define EPWM_CAPCTL_CAPINV5_Msk (0x1ul << EPWM_CAPCTL_CAPINV5_Pos) /*!< EPWM_T::CAPCTL: CAPINV5 Mask */ + +#define EPWM_CAPCTL_RCRLDEN0_Pos (16) /*!< EPWM_T::CAPCTL: RCRLDEN0 Position */ +#define EPWM_CAPCTL_RCRLDEN0_Msk (0x1ul << EPWM_CAPCTL_RCRLDEN0_Pos) /*!< EPWM_T::CAPCTL: RCRLDEN0 Mask */ + +#define EPWM_CAPCTL_RCRLDEN1_Pos (17) /*!< EPWM_T::CAPCTL: RCRLDEN1 Position */ +#define EPWM_CAPCTL_RCRLDEN1_Msk (0x1ul << EPWM_CAPCTL_RCRLDEN1_Pos) /*!< EPWM_T::CAPCTL: RCRLDEN1 Mask */ + +#define EPWM_CAPCTL_RCRLDEN2_Pos (18) /*!< EPWM_T::CAPCTL: RCRLDEN2 Position */ +#define EPWM_CAPCTL_RCRLDEN2_Msk (0x1ul << EPWM_CAPCTL_RCRLDEN2_Pos) /*!< EPWM_T::CAPCTL: RCRLDEN2 Mask */ + +#define EPWM_CAPCTL_RCRLDEN3_Pos (19) /*!< EPWM_T::CAPCTL: RCRLDEN3 Position */ +#define EPWM_CAPCTL_RCRLDEN3_Msk (0x1ul << EPWM_CAPCTL_RCRLDEN3_Pos) /*!< EPWM_T::CAPCTL: RCRLDEN3 Mask */ + +#define EPWM_CAPCTL_RCRLDEN4_Pos (20) /*!< EPWM_T::CAPCTL: RCRLDEN4 Position */ +#define EPWM_CAPCTL_RCRLDEN4_Msk (0x1ul << EPWM_CAPCTL_RCRLDEN4_Pos) /*!< EPWM_T::CAPCTL: RCRLDEN4 Mask */ + +#define EPWM_CAPCTL_RCRLDEN5_Pos (21) /*!< EPWM_T::CAPCTL: RCRLDEN5 Position */ +#define EPWM_CAPCTL_RCRLDEN5_Msk (0x1ul << EPWM_CAPCTL_RCRLDEN5_Pos) /*!< EPWM_T::CAPCTL: RCRLDEN5 Mask */ + +#define EPWM_CAPCTL_FCRLDEN0_Pos (24) /*!< EPWM_T::CAPCTL: FCRLDEN0 Position */ +#define EPWM_CAPCTL_FCRLDEN0_Msk (0x1ul << EPWM_CAPCTL_FCRLDEN0_Pos) /*!< EPWM_T::CAPCTL: FCRLDEN0 Mask */ + +#define EPWM_CAPCTL_FCRLDEN1_Pos (25) /*!< EPWM_T::CAPCTL: FCRLDEN1 Position */ +#define EPWM_CAPCTL_FCRLDEN1_Msk (0x1ul << EPWM_CAPCTL_FCRLDEN1_Pos) /*!< EPWM_T::CAPCTL: FCRLDEN1 Mask */ + +#define EPWM_CAPCTL_FCRLDEN2_Pos (26) /*!< EPWM_T::CAPCTL: FCRLDEN2 Position */ +#define EPWM_CAPCTL_FCRLDEN2_Msk (0x1ul << EPWM_CAPCTL_FCRLDEN2_Pos) /*!< EPWM_T::CAPCTL: FCRLDEN2 Mask */ + +#define EPWM_CAPCTL_FCRLDEN3_Pos (27) /*!< EPWM_T::CAPCTL: FCRLDEN3 Position */ +#define EPWM_CAPCTL_FCRLDEN3_Msk (0x1ul << EPWM_CAPCTL_FCRLDEN3_Pos) /*!< EPWM_T::CAPCTL: FCRLDEN3 Mask */ + +#define EPWM_CAPCTL_FCRLDEN4_Pos (28) /*!< EPWM_T::CAPCTL: FCRLDEN4 Position */ +#define EPWM_CAPCTL_FCRLDEN4_Msk (0x1ul << EPWM_CAPCTL_FCRLDEN4_Pos) /*!< EPWM_T::CAPCTL: FCRLDEN4 Mask */ + +#define EPWM_CAPCTL_FCRLDEN5_Pos (29) /*!< EPWM_T::CAPCTL: FCRLDEN5 Position */ +#define EPWM_CAPCTL_FCRLDEN5_Msk (0x1ul << EPWM_CAPCTL_FCRLDEN5_Pos) /*!< EPWM_T::CAPCTL: FCRLDEN5 Mask */ + +#define EPWM_CAPSTS_CRLIFOV0_Pos (0) /*!< EPWM_T::CAPSTS: CRLIFOV0 Position */ +#define EPWM_CAPSTS_CRLIFOV0_Msk (0x1ul << EPWM_CAPSTS_CRLIFOV0_Pos) /*!< EPWM_T::CAPSTS: CRLIFOV0 Mask */ + +#define EPWM_CAPSTS_CRLIFOV1_Pos (1) /*!< EPWM_T::CAPSTS: CRLIFOV1 Position */ +#define EPWM_CAPSTS_CRLIFOV1_Msk (0x1ul << EPWM_CAPSTS_CRLIFOV1_Pos) /*!< EPWM_T::CAPSTS: CRLIFOV1 Mask */ + +#define EPWM_CAPSTS_CRLIFOV2_Pos (2) /*!< EPWM_T::CAPSTS: CRLIFOV2 Position */ +#define EPWM_CAPSTS_CRLIFOV2_Msk (0x1ul << EPWM_CAPSTS_CRLIFOV2_Pos) /*!< EPWM_T::CAPSTS: CRLIFOV2 Mask */ + +#define EPWM_CAPSTS_CRLIFOV3_Pos (3) /*!< EPWM_T::CAPSTS: CRLIFOV3 Position */ +#define EPWM_CAPSTS_CRLIFOV3_Msk (0x1ul << EPWM_CAPSTS_CRLIFOV3_Pos) /*!< EPWM_T::CAPSTS: CRLIFOV3 Mask */ + +#define EPWM_CAPSTS_CRLIFOV4_Pos (4) /*!< EPWM_T::CAPSTS: CRLIFOV4 Position */ +#define EPWM_CAPSTS_CRLIFOV4_Msk (0x1ul << EPWM_CAPSTS_CRLIFOV4_Pos) /*!< EPWM_T::CAPSTS: CRLIFOV4 Mask */ + +#define EPWM_CAPSTS_CRLIFOV5_Pos (5) /*!< EPWM_T::CAPSTS: CRLIFOV5 Position */ +#define EPWM_CAPSTS_CRLIFOV5_Msk (0x1ul << EPWM_CAPSTS_CRLIFOV5_Pos) /*!< EPWM_T::CAPSTS: CRLIFOV5 Mask */ + +#define EPWM_CAPSTS_CFLIFOV0_Pos (8) /*!< EPWM_T::CAPSTS: CFLIFOV0 Position */ +#define EPWM_CAPSTS_CFLIFOV0_Msk (0x1ul << EPWM_CAPSTS_CFLIFOV0_Pos) /*!< EPWM_T::CAPSTS: CFLIFOV0 Mask */ + +#define EPWM_CAPSTS_CFLIFOV1_Pos (9) /*!< EPWM_T::CAPSTS: CFLIFOV1 Position */ +#define EPWM_CAPSTS_CFLIFOV1_Msk (0x1ul << EPWM_CAPSTS_CFLIFOV1_Pos) /*!< EPWM_T::CAPSTS: CFLIFOV1 Mask */ + +#define EPWM_CAPSTS_CFLIFOV2_Pos (10) /*!< EPWM_T::CAPSTS: CFLIFOV2 Position */ +#define EPWM_CAPSTS_CFLIFOV2_Msk (0x1ul << EPWM_CAPSTS_CFLIFOV2_Pos) /*!< EPWM_T::CAPSTS: CFLIFOV2 Mask */ + +#define EPWM_CAPSTS_CFLIFOV3_Pos (11) /*!< EPWM_T::CAPSTS: CFLIFOV3 Position */ +#define EPWM_CAPSTS_CFLIFOV3_Msk (0x1ul << EPWM_CAPSTS_CFLIFOV3_Pos) /*!< EPWM_T::CAPSTS: CFLIFOV3 Mask */ + +#define EPWM_CAPSTS_CFLIFOV4_Pos (12) /*!< EPWM_T::CAPSTS: CFLIFOV4 Position */ +#define EPWM_CAPSTS_CFLIFOV4_Msk (0x1ul << EPWM_CAPSTS_CFLIFOV4_Pos) /*!< EPWM_T::CAPSTS: CFLIFOV4 Mask */ + +#define EPWM_CAPSTS_CFLIFOV5_Pos (13) /*!< EPWM_T::CAPSTS: CFLIFOV5 Position */ +#define EPWM_CAPSTS_CFLIFOV5_Msk (0x1ul << EPWM_CAPSTS_CFLIFOV5_Pos) /*!< EPWM_T::CAPSTS: CFLIFOV5 Mask */ + +#define EPWM_RCAPDAT0_RCAPDAT_Pos (0) /*!< EPWM_T::RCAPDAT0: RCAPDAT Position */ +#define EPWM_RCAPDAT0_RCAPDAT_Msk (0xfffful << EPWM_RCAPDAT0_RCAPDAT_Pos) /*!< EPWM_T::RCAPDAT0: RCAPDAT Mask */ + +#define EPWM_FCAPDAT0_FCAPDAT_Pos (0) /*!< EPWM_T::FCAPDAT0: FCAPDAT Position */ +#define EPWM_FCAPDAT0_FCAPDAT_Msk (0xfffful << EPWM_FCAPDAT0_FCAPDAT_Pos) /*!< EPWM_T::FCAPDAT0: FCAPDAT Mask */ + +#define EPWM_RCAPDAT1_RCAPDAT_Pos (0) /*!< EPWM_T::RCAPDAT1: RCAPDAT Position */ +#define EPWM_RCAPDAT1_RCAPDAT_Msk (0xfffful << EPWM_RCAPDAT1_RCAPDAT_Pos) /*!< EPWM_T::RCAPDAT1: RCAPDAT Mask */ + +#define EPWM_FCAPDAT1_FCAPDAT_Pos (0) /*!< EPWM_T::FCAPDAT1: FCAPDAT Position */ +#define EPWM_FCAPDAT1_FCAPDAT_Msk (0xfffful << EPWM_FCAPDAT1_FCAPDAT_Pos) /*!< EPWM_T::FCAPDAT1: FCAPDAT Mask */ + +#define EPWM_RCAPDAT2_RCAPDAT_Pos (0) /*!< EPWM_T::RCAPDAT2: RCAPDAT Position */ +#define EPWM_RCAPDAT2_RCAPDAT_Msk (0xfffful << EPWM_RCAPDAT2_RCAPDAT_Pos) /*!< EPWM_T::RCAPDAT2: RCAPDAT Mask */ + +#define EPWM_FCAPDAT2_FCAPDAT_Pos (0) /*!< EPWM_T::FCAPDAT2: FCAPDAT Position */ +#define EPWM_FCAPDAT2_FCAPDAT_Msk (0xfffful << EPWM_FCAPDAT2_FCAPDAT_Pos) /*!< EPWM_T::FCAPDAT2: FCAPDAT Mask */ + +#define EPWM_RCAPDAT3_RCAPDAT_Pos (0) /*!< EPWM_T::RCAPDAT3: RCAPDAT Position */ +#define EPWM_RCAPDAT3_RCAPDAT_Msk (0xfffful << EPWM_RCAPDAT3_RCAPDAT_Pos) /*!< EPWM_T::RCAPDAT3: RCAPDAT Mask */ + +#define EPWM_FCAPDAT3_FCAPDAT_Pos (0) /*!< EPWM_T::FCAPDAT3: FCAPDAT Position */ +#define EPWM_FCAPDAT3_FCAPDAT_Msk (0xfffful << EPWM_FCAPDAT3_FCAPDAT_Pos) /*!< EPWM_T::FCAPDAT3: FCAPDAT Mask */ + +#define EPWM_RCAPDAT4_RCAPDAT_Pos (0) /*!< EPWM_T::RCAPDAT4: RCAPDAT Position */ +#define EPWM_RCAPDAT4_RCAPDAT_Msk (0xfffful << EPWM_RCAPDAT4_RCAPDAT_Pos) /*!< EPWM_T::RCAPDAT4: RCAPDAT Mask */ + +#define EPWM_FCAPDAT4_FCAPDAT_Pos (0) /*!< EPWM_T::FCAPDAT4: FCAPDAT Position */ +#define EPWM_FCAPDAT4_FCAPDAT_Msk (0xfffful << EPWM_FCAPDAT4_FCAPDAT_Pos) /*!< EPWM_T::FCAPDAT4: FCAPDAT Mask */ + +#define EPWM_RCAPDAT5_RCAPDAT_Pos (0) /*!< EPWM_T::RCAPDAT5: RCAPDAT Position */ +#define EPWM_RCAPDAT5_RCAPDAT_Msk (0xfffful << EPWM_RCAPDAT5_RCAPDAT_Pos) /*!< EPWM_T::RCAPDAT5: RCAPDAT Mask */ + +#define EPWM_FCAPDAT5_FCAPDAT_Pos (0) /*!< EPWM_T::FCAPDAT5: FCAPDAT Position */ +#define EPWM_FCAPDAT5_FCAPDAT_Msk (0xfffful << EPWM_FCAPDAT5_FCAPDAT_Pos) /*!< EPWM_T::FCAPDAT5: FCAPDAT Mask */ + +#define EPWM_PDMACTL_CHEN0_1_Pos (0) /*!< EPWM_T::PDMACTL: CHEN0_1 Position */ +#define EPWM_PDMACTL_CHEN0_1_Msk (0x1ul << EPWM_PDMACTL_CHEN0_1_Pos) /*!< EPWM_T::PDMACTL: CHEN0_1 Mask */ + +#define EPWM_PDMACTL_CAPMOD0_1_Pos (1) /*!< EPWM_T::PDMACTL: CAPMOD0_1 Position */ +#define EPWM_PDMACTL_CAPMOD0_1_Msk (0x3ul << EPWM_PDMACTL_CAPMOD0_1_Pos) /*!< EPWM_T::PDMACTL: CAPMOD0_1 Mask */ + +#define EPWM_PDMACTL_CAPORD0_1_Pos (3) /*!< EPWM_T::PDMACTL: CAPORD0_1 Position */ +#define EPWM_PDMACTL_CAPORD0_1_Msk (0x1ul << EPWM_PDMACTL_CAPORD0_1_Pos) /*!< EPWM_T::PDMACTL: CAPORD0_1 Mask */ + +#define EPWM_PDMACTL_CHSEL0_1_Pos (4) /*!< EPWM_T::PDMACTL: CHSEL0_1 Position */ +#define EPWM_PDMACTL_CHSEL0_1_Msk (0x1ul << EPWM_PDMACTL_CHSEL0_1_Pos) /*!< EPWM_T::PDMACTL: CHSEL0_1 Mask */ + +#define EPWM_PDMACTL_CHEN2_3_Pos (8) /*!< EPWM_T::PDMACTL: CHEN2_3 Position */ +#define EPWM_PDMACTL_CHEN2_3_Msk (0x1ul << EPWM_PDMACTL_CHEN2_3_Pos) /*!< EPWM_T::PDMACTL: CHEN2_3 Mask */ + +#define EPWM_PDMACTL_CAPMOD2_3_Pos (9) /*!< EPWM_T::PDMACTL: CAPMOD2_3 Position */ +#define EPWM_PDMACTL_CAPMOD2_3_Msk (0x3ul << EPWM_PDMACTL_CAPMOD2_3_Pos) /*!< EPWM_T::PDMACTL: CAPMOD2_3 Mask */ + +#define EPWM_PDMACTL_CAPORD2_3_Pos (11) /*!< EPWM_T::PDMACTL: CAPORD2_3 Position */ +#define EPWM_PDMACTL_CAPORD2_3_Msk (0x1ul << EPWM_PDMACTL_CAPORD2_3_Pos) /*!< EPWM_T::PDMACTL: CAPORD2_3 Mask */ + +#define EPWM_PDMACTL_CHSEL2_3_Pos (12) /*!< EPWM_T::PDMACTL: CHSEL2_3 Position */ +#define EPWM_PDMACTL_CHSEL2_3_Msk (0x1ul << EPWM_PDMACTL_CHSEL2_3_Pos) /*!< EPWM_T::PDMACTL: CHSEL2_3 Mask */ + +#define EPWM_PDMACTL_CHEN4_5_Pos (16) /*!< EPWM_T::PDMACTL: CHEN4_5 Position */ +#define EPWM_PDMACTL_CHEN4_5_Msk (0x1ul << EPWM_PDMACTL_CHEN4_5_Pos) /*!< EPWM_T::PDMACTL: CHEN4_5 Mask */ + +#define EPWM_PDMACTL_CAPMOD4_5_Pos (17) /*!< EPWM_T::PDMACTL: CAPMOD4_5 Position */ +#define EPWM_PDMACTL_CAPMOD4_5_Msk (0x3ul << EPWM_PDMACTL_CAPMOD4_5_Pos) /*!< EPWM_T::PDMACTL: CAPMOD4_5 Mask */ + +#define EPWM_PDMACTL_CAPORD4_5_Pos (19) /*!< EPWM_T::PDMACTL: CAPORD4_5 Position */ +#define EPWM_PDMACTL_CAPORD4_5_Msk (0x1ul << EPWM_PDMACTL_CAPORD4_5_Pos) /*!< EPWM_T::PDMACTL: CAPORD4_5 Mask */ + +#define EPWM_PDMACTL_CHSEL4_5_Pos (20) /*!< EPWM_T::PDMACTL: CHSEL4_5 Position */ +#define EPWM_PDMACTL_CHSEL4_5_Msk (0x1ul << EPWM_PDMACTL_CHSEL4_5_Pos) /*!< EPWM_T::PDMACTL: CHSEL4_5 Mask */ + +#define EPWM_PDMACAP0_1_CAPBUF_Pos (0) /*!< EPWM_T::PDMACAP0_1: CAPBUF Position */ +#define EPWM_PDMACAP0_1_CAPBUF_Msk (0xfffful << EPWM_PDMACAP0_1_CAPBUF_Pos) /*!< EPWM_T::PDMACAP0_1: CAPBUF Mask */ + +#define EPWM_PDMACAP2_3_CAPBUF_Pos (0) /*!< EPWM_T::PDMACAP2_3: CAPBUF Position */ +#define EPWM_PDMACAP2_3_CAPBUF_Msk (0xfffful << EPWM_PDMACAP2_3_CAPBUF_Pos) /*!< EPWM_T::PDMACAP2_3: CAPBUF Mask */ + +#define EPWM_PDMACAP4_5_CAPBUF_Pos (0) /*!< EPWM_T::PDMACAP4_5: CAPBUF Position */ +#define EPWM_PDMACAP4_5_CAPBUF_Msk (0xfffful << EPWM_PDMACAP4_5_CAPBUF_Pos) /*!< EPWM_T::PDMACAP4_5: CAPBUF Mask */ + +#define EPWM_CAPIEN_CAPRIEN0_Pos (0) /*!< EPWM_T::CAPIEN: CAPRIEN0 Position */ +#define EPWM_CAPIEN_CAPRIEN0_Msk (0x1ul << EPWM_CAPIEN_CAPRIEN0_Pos) /*!< EPWM_T::CAPIEN: CAPRIEN0 Mask */ + +#define EPWM_CAPIEN_CAPRIEN1_Pos (1) /*!< EPWM_T::CAPIEN: CAPRIEN1 Position */ +#define EPWM_CAPIEN_CAPRIEN1_Msk (0x1ul << EPWM_CAPIEN_CAPRIEN1_Pos) /*!< EPWM_T::CAPIEN: CAPRIEN1 Mask */ + +#define EPWM_CAPIEN_CAPRIEN2_Pos (2) /*!< EPWM_T::CAPIEN: CAPRIEN2 Position */ +#define EPWM_CAPIEN_CAPRIEN2_Msk (0x1ul << EPWM_CAPIEN_CAPRIEN2_Pos) /*!< EPWM_T::CAPIEN: CAPRIEN2 Mask */ + +#define EPWM_CAPIEN_CAPRIEN3_Pos (3) /*!< EPWM_T::CAPIEN: CAPRIEN3 Position */ +#define EPWM_CAPIEN_CAPRIEN3_Msk (0x1ul << EPWM_CAPIEN_CAPRIEN3_Pos) /*!< EPWM_T::CAPIEN: CAPRIEN3 Mask */ + +#define EPWM_CAPIEN_CAPRIEN4_Pos (4) /*!< EPWM_T::CAPIEN: CAPRIEN4 Position */ +#define EPWM_CAPIEN_CAPRIEN4_Msk (0x1ul << EPWM_CAPIEN_CAPRIEN4_Pos) /*!< EPWM_T::CAPIEN: CAPRIEN4 Mask */ + +#define EPWM_CAPIEN_CAPRIEN5_Pos (5) /*!< EPWM_T::CAPIEN: CAPRIEN5 Position */ +#define EPWM_CAPIEN_CAPRIEN5_Msk (0x1ul << EPWM_CAPIEN_CAPRIEN5_Pos) /*!< EPWM_T::CAPIEN: CAPRIEN5 Mask */ + +#define EPWM_CAPIEN_CAPFIEN0_Pos (8) /*!< EPWM_T::CAPIEN: CAPFIEN0 Position */ +#define EPWM_CAPIEN_CAPFIEN0_Msk (0x1ul << EPWM_CAPIEN_CAPFIEN0_Pos) /*!< EPWM_T::CAPIEN: CAPFIEN0 Mask */ + +#define EPWM_CAPIEN_CAPFIEN1_Pos (9) /*!< EPWM_T::CAPIEN: CAPFIEN1 Position */ +#define EPWM_CAPIEN_CAPFIEN1_Msk (0x1ul << EPWM_CAPIEN_CAPFIEN1_Pos) /*!< EPWM_T::CAPIEN: CAPFIEN1 Mask */ + +#define EPWM_CAPIEN_CAPFIEN2_Pos (10) /*!< EPWM_T::CAPIEN: CAPFIEN2 Position */ +#define EPWM_CAPIEN_CAPFIEN2_Msk (0x1ul << EPWM_CAPIEN_CAPFIEN2_Pos) /*!< EPWM_T::CAPIEN: CAPFIEN2 Mask */ + +#define EPWM_CAPIEN_CAPFIEN3_Pos (11) /*!< EPWM_T::CAPIEN: CAPFIEN3 Position */ +#define EPWM_CAPIEN_CAPFIEN3_Msk (0x1ul << EPWM_CAPIEN_CAPFIEN3_Pos) /*!< EPWM_T::CAPIEN: CAPFIEN3 Mask */ + +#define EPWM_CAPIEN_CAPFIEN4_Pos (12) /*!< EPWM_T::CAPIEN: CAPFIEN4 Position */ +#define EPWM_CAPIEN_CAPFIEN4_Msk (0x1ul << EPWM_CAPIEN_CAPFIEN4_Pos) /*!< EPWM_T::CAPIEN: CAPFIEN4 Mask */ + +#define EPWM_CAPIEN_CAPFIEN5_Pos (13) /*!< EPWM_T::CAPIEN: CAPFIEN5 Position */ +#define EPWM_CAPIEN_CAPFIEN5_Msk (0x1ul << EPWM_CAPIEN_CAPFIEN5_Pos) /*!< EPWM_T::CAPIEN: CAPFIEN5 Mask */ + +#define EPWM_CAPIF_CRLIF0_Pos (0) /*!< EPWM_T::CAPIF: CRLIF0 Position */ +#define EPWM_CAPIF_CRLIF0_Msk (0x1ul << EPWM_CAPIF_CRLIF0_Pos) /*!< EPWM_T::CAPIF: CRLIF0 Mask */ + +#define EPWM_CAPIF_CRLIF1_Pos (1) /*!< EPWM_T::CAPIF: CRLIF1 Position */ +#define EPWM_CAPIF_CRLIF1_Msk (0x1ul << EPWM_CAPIF_CRLIF1_Pos) /*!< EPWM_T::CAPIF: CRLIF1 Mask */ + +#define EPWM_CAPIF_CRLIF2_Pos (2) /*!< EPWM_T::CAPIF: CRLIF2 Position */ +#define EPWM_CAPIF_CRLIF2_Msk (0x1ul << EPWM_CAPIF_CRLIF2_Pos) /*!< EPWM_T::CAPIF: CRLIF2 Mask */ + +#define EPWM_CAPIF_CRLIF3_Pos (3) /*!< EPWM_T::CAPIF: CRLIF3 Position */ +#define EPWM_CAPIF_CRLIF3_Msk (0x1ul << EPWM_CAPIF_CRLIF3_Pos) /*!< EPWM_T::CAPIF: CRLIF3 Mask */ + +#define EPWM_CAPIF_CRLIF4_Pos (4) /*!< EPWM_T::CAPIF: CRLIF4 Position */ +#define EPWM_CAPIF_CRLIF4_Msk (0x1ul << EPWM_CAPIF_CRLIF4_Pos) /*!< EPWM_T::CAPIF: CRLIF4 Mask */ + +#define EPWM_CAPIF_CRLIF5_Pos (5) /*!< EPWM_T::CAPIF: CRLIF5 Position */ +#define EPWM_CAPIF_CRLIF5_Msk (0x1ul << EPWM_CAPIF_CRLIF5_Pos) /*!< EPWM_T::CAPIF: CRLIF5 Mask */ + +#define EPWM_CAPIF_CFLIF0_Pos (8) /*!< EPWM_T::CAPIF: CFLIF0 Position */ +#define EPWM_CAPIF_CFLIF0_Msk (0x1ul << EPWM_CAPIF_CFLIF0_Pos) /*!< EPWM_T::CAPIF: CFLIF0 Mask */ + +#define EPWM_CAPIF_CFLIF1_Pos (9) /*!< EPWM_T::CAPIF: CFLIF1 Position */ +#define EPWM_CAPIF_CFLIF1_Msk (0x1ul << EPWM_CAPIF_CFLIF1_Pos) /*!< EPWM_T::CAPIF: CFLIF1 Mask */ + +#define EPWM_CAPIF_CFLIF2_Pos (10) /*!< EPWM_T::CAPIF: CFLIF2 Position */ +#define EPWM_CAPIF_CFLIF2_Msk (0x1ul << EPWM_CAPIF_CFLIF2_Pos) /*!< EPWM_T::CAPIF: CFLIF2 Mask */ + +#define EPWM_CAPIF_CFLIF3_Pos (11) /*!< EPWM_T::CAPIF: CFLIF3 Position */ +#define EPWM_CAPIF_CFLIF3_Msk (0x1ul << EPWM_CAPIF_CFLIF3_Pos) /*!< EPWM_T::CAPIF: CFLIF3 Mask */ + +#define EPWM_CAPIF_CFLIF4_Pos (12) /*!< EPWM_T::CAPIF: CFLIF4 Position */ +#define EPWM_CAPIF_CFLIF4_Msk (0x1ul << EPWM_CAPIF_CFLIF4_Pos) /*!< EPWM_T::CAPIF: CFLIF4 Mask */ + +#define EPWM_CAPIF_CFLIF5_Pos (13) /*!< EPWM_T::CAPIF: CFLIF5 Position */ +#define EPWM_CAPIF_CFLIF5_Msk (0x1ul << EPWM_CAPIF_CFLIF5_Pos) /*!< EPWM_T::CAPIF: CFLIF5 Mask */ + +#define EPWM_PBUF0_PBUF_Pos (0) /*!< EPWM_T::PBUF0: PBUF Position */ +#define EPWM_PBUF0_PBUF_Msk (0xfffful << EPWM_PBUF0_PBUF_Pos) /*!< EPWM_T::PBUF0: PBUF Mask */ + +#define EPWM_PBUF1_PBUF_Pos (0) /*!< EPWM_T::PBUF1: PBUF Position */ +#define EPWM_PBUF1_PBUF_Msk (0xfffful << EPWM_PBUF1_PBUF_Pos) /*!< EPWM_T::PBUF1: PBUF Mask */ + +#define EPWM_PBUF2_PBUF_Pos (0) /*!< EPWM_T::PBUF2: PBUF Position */ +#define EPWM_PBUF2_PBUF_Msk (0xfffful << EPWM_PBUF2_PBUF_Pos) /*!< EPWM_T::PBUF2: PBUF Mask */ + +#define EPWM_PBUF3_PBUF_Pos (0) /*!< EPWM_T::PBUF3: PBUF Position */ +#define EPWM_PBUF3_PBUF_Msk (0xfffful << EPWM_PBUF3_PBUF_Pos) /*!< EPWM_T::PBUF3: PBUF Mask */ + +#define EPWM_PBUF4_PBUF_Pos (0) /*!< EPWM_T::PBUF4: PBUF Position */ +#define EPWM_PBUF4_PBUF_Msk (0xfffful << EPWM_PBUF4_PBUF_Pos) /*!< EPWM_T::PBUF4: PBUF Mask */ + +#define EPWM_PBUF5_PBUF_Pos (0) /*!< EPWM_T::PBUF5: PBUF Position */ +#define EPWM_PBUF5_PBUF_Msk (0xfffful << EPWM_PBUF5_PBUF_Pos) /*!< EPWM_T::PBUF5: PBUF Mask */ + +#define EPWM_CMPBUF0_CMPBUF_Pos (0) /*!< EPWM_T::CMPBUF0: CMPBUF Position */ +#define EPWM_CMPBUF0_CMPBUF_Msk (0xfffful << EPWM_CMPBUF0_CMPBUF_Pos) /*!< EPWM_T::CMPBUF0: CMPBUF Mask */ + +#define EPWM_CMPBUF1_CMPBUF_Pos (0) /*!< EPWM_T::CMPBUF1: CMPBUF Position */ +#define EPWM_CMPBUF1_CMPBUF_Msk (0xfffful << EPWM_CMPBUF1_CMPBUF_Pos) /*!< EPWM_T::CMPBUF1: CMPBUF Mask */ + +#define EPWM_CMPBUF2_CMPBUF_Pos (0) /*!< EPWM_T::CMPBUF2: CMPBUF Position */ +#define EPWM_CMPBUF2_CMPBUF_Msk (0xfffful << EPWM_CMPBUF2_CMPBUF_Pos) /*!< EPWM_T::CMPBUF2: CMPBUF Mask */ + +#define EPWM_CMPBUF3_CMPBUF_Pos (0) /*!< EPWM_T::CMPBUF3: CMPBUF Position */ +#define EPWM_CMPBUF3_CMPBUF_Msk (0xfffful << EPWM_CMPBUF3_CMPBUF_Pos) /*!< EPWM_T::CMPBUF3: CMPBUF Mask */ + +#define EPWM_CMPBUF4_CMPBUF_Pos (0) /*!< EPWM_T::CMPBUF4: CMPBUF Position */ +#define EPWM_CMPBUF4_CMPBUF_Msk (0xfffful << EPWM_CMPBUF4_CMPBUF_Pos) /*!< EPWM_T::CMPBUF4: CMPBUF Mask */ + +#define EPWM_CMPBUF5_CMPBUF_Pos (0) /*!< EPWM_T::CMPBUF5: CMPBUF Position */ +#define EPWM_CMPBUF5_CMPBUF_Msk (0xfffful << EPWM_CMPBUF5_CMPBUF_Pos) /*!< EPWM_T::CMPBUF5: CMPBUF Mask */ + +#define EPWM_CPSCBUF0_1_CPSCBUF_Pos (0) /*!< EPWM_T::CPSCBUF0_1: CPSCBUF Position */ +#define EPWM_CPSCBUF0_1_CPSCBUF_Msk (0xffful << EPWM_CPSCBUF0_1_CPSCBUF_Pos) /*!< EPWM_T::CPSCBUF0_1: CPSCBUF Mask */ + +#define EPWM_CPSCBUF2_3_CPSCBUF_Pos (0) /*!< EPWM_T::CPSCBUF2_3: CPSCBUF Position */ +#define EPWM_CPSCBUF2_3_CPSCBUF_Msk (0xffful << EPWM_CPSCBUF2_3_CPSCBUF_Pos) /*!< EPWM_T::CPSCBUF2_3: CPSCBUF Mask */ + +#define EPWM_CPSCBUF4_5_CPSCBUF_Pos (0) /*!< EPWM_T::CPSCBUF4_5: CPSCBUF Position */ +#define EPWM_CPSCBUF4_5_CPSCBUF_Msk (0xffful << EPWM_CPSCBUF4_5_CPSCBUF_Pos) /*!< EPWM_T::CPSCBUF4_5: CPSCBUF Mask */ + +#define EPWM_FTCBUF0_1_FTCMPBUF_Pos (0) /*!< EPWM_T::FTCBUF0_1: FTCMPBUF Position */ +#define EPWM_FTCBUF0_1_FTCMPBUF_Msk (0xfffful << EPWM_FTCBUF0_1_FTCMPBUF_Pos) /*!< EPWM_T::FTCBUF0_1: FTCMPBUF Mask */ + +#define EPWM_FTCBUF2_3_FTCMPBUF_Pos (0) /*!< EPWM_T::FTCBUF2_3: FTCMPBUF Position */ +#define EPWM_FTCBUF2_3_FTCMPBUF_Msk (0xfffful << EPWM_FTCBUF2_3_FTCMPBUF_Pos) /*!< EPWM_T::FTCBUF2_3: FTCMPBUF Mask */ + +#define EPWM_FTCBUF4_5_FTCMPBUF_Pos (0) /*!< EPWM_T::FTCBUF4_5: FTCMPBUF Position */ +#define EPWM_FTCBUF4_5_FTCMPBUF_Msk (0xfffful << EPWM_FTCBUF4_5_FTCMPBUF_Pos) /*!< EPWM_T::FTCBUF4_5: FTCMPBUF Mask */ + +#define EPWM_FTCI_FTCMU0_Pos (0) /*!< EPWM_T::FTCI: FTCMU0 Position */ +#define EPWM_FTCI_FTCMU0_Msk (0x1ul << EPWM_FTCI_FTCMU0_Pos) /*!< EPWM_T::FTCI: FTCMU0 Mask */ + +#define EPWM_FTCI_FTCMU2_Pos (1) /*!< EPWM_T::FTCI: FTCMU2 Position */ +#define EPWM_FTCI_FTCMU2_Msk (0x1ul << EPWM_FTCI_FTCMU2_Pos) /*!< EPWM_T::FTCI: FTCMU2 Mask */ + +#define EPWM_FTCI_FTCMU4_Pos (2) /*!< EPWM_T::FTCI: FTCMU4 Position */ +#define EPWM_FTCI_FTCMU4_Msk (0x1ul << EPWM_FTCI_FTCMU4_Pos) /*!< EPWM_T::FTCI: FTCMU4 Mask */ + +#define EPWM_FTCI_FTCMD0_Pos (8) /*!< EPWM_T::FTCI: FTCMD0 Position */ +#define EPWM_FTCI_FTCMD0_Msk (0x1ul << EPWM_FTCI_FTCMD0_Pos) /*!< EPWM_T::FTCI: FTCMD0 Mask */ + +#define EPWM_FTCI_FTCMD2_Pos (9) /*!< EPWM_T::FTCI: FTCMD2 Position */ +#define EPWM_FTCI_FTCMD2_Msk (0x1ul << EPWM_FTCI_FTCMD2_Pos) /*!< EPWM_T::FTCI: FTCMD2 Mask */ + +#define EPWM_FTCI_FTCMD4_Pos (10) /*!< EPWM_T::FTCI: FTCMD4 Position */ +#define EPWM_FTCI_FTCMD4_Msk (0x1ul << EPWM_FTCI_FTCMD4_Pos) /*!< EPWM_T::FTCI: FTCMD4 Mask */ + +/**@}*/ /* EPWM_CONST */ +/**@}*/ /* end of EPWM register group */ +/**@}*/ /* end of REGISTER group */ + + + +#endif /* __EPWM_REG_H__ */ diff --git a/Ubiquitous/XiZi/board/nuvoton-m2354/third_party_driver/include/Regs/ewdt_reg.h b/Ubiquitous/XiZi/board/nuvoton-m2354/third_party_driver/include/Regs/ewdt_reg.h new file mode 100644 index 0000000..b8585af --- /dev/null +++ b/Ubiquitous/XiZi/board/nuvoton-m2354/third_party_driver/include/Regs/ewdt_reg.h @@ -0,0 +1,178 @@ +/**************************************************************************//** + * @file ewdt_reg.h + * @version V1.00 + * @brief EWDT register definition header file + * + * @copyright SPDX-License-Identifier: Apache-2.0 + * @copyright Copyright (C) 2020 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ +#ifndef __EWDT_REG_H__ +#define __EWDT_REG_H__ + +/** + @addtogroup REGISTER Control Register + + @{ + +*/ + + +/*---------------------- Extra Watch Dog Timer Controller -------------------------*/ +/** + @addtogroup EWDT Extra Watch Dog Timer Controller(EWDT) + Memory Mapped Structure for EWDT Controller + @{ +*/ + +typedef struct +{ + + + /** + * @var EWDT_T::CTL + * Offset: 0x00 EWDT Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[1] |RSTEN |EWDT Time-out Reset Enable Control (Write Protect) + * | | |Setting this bit will enable the EWDT time-out reset system function If the EWDT up counter value has not been cleared after the specific EWDT reset delay period expires. + * | | |0 = EWDT time-out reset system function Disabled. + * | | |1 = EWDT time-out reset system function Enabled. + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * |[2] |RSTF |EWDT Time-out Reset Flag + * | | |This bit indicates the system has been reset by EWDT time-out reset system event or not. + * | | |0 = EWDT time-out reset system event did not occur. + * | | |1 = EWDT time-out reset system event has been occurred. + * | | |Note: This bit is cleared by writing 1 to it. + * |[3] |IF |EWDT Time-out Interrupt Flag + * | | |This bit will set to 1 while EWDT up counter value reaches the selected EWDT time-out interval + * | | |0 = EWDT time-out interrupt event interrupt did not occur. + * | | |1 = EWDT time-out interrupt interrupt event occurred. + * | | |Note: This bit is cleared by writing 1 to it. + * |[4] |WKEN |EWDT Time-out Wake-up Function Control (Write Protect) + * | | |If this bit is set to 1, while EWDT time-out interrupt flag IF (EWDT_CTL[3]) is generated to 1 and interrupt enable bit INTEN (EWDT_CTL[6]) is enabled, the EWDT time-out interrupt signal will generate a event to trigger CPU wake-up trigger event to chip. + * | | |0 = Trigger Wake-up trigger event function Disabled if EWDT time-out interrupt signal generated. + * | | |1 = Trigger Wake-up trigger event function Enabled if EWDT time-out interrupt signal generated. + * | | |Note1: This bit is write protected. Refer to the SYS_REGLCTL register. + * | | |Note2: Chip can be woken-up by while EWDT time-out interrupt signal generated only if EWDT clock source is selected to LIRC or LXT (32 kHz). + * |[5] |WKF |EWDT Time-out Wake-up Flag (Write Protect) + * | | |This bit indicates the EWDT time-out event has triggered interrupt chip wake-up or not.flag status of EWDT + * | | |0 = WDT does not cause chip wake-up. + * | | |1 = Chip wake-up from Idle or Power-down mode if when WDT time-out interrupt signal is generated. + * | | |Note1: This bit is write protected. Refer to the SYS_REGLCTL register. + * | | |Note2: This bit is cleared by writing 1 to it. + * |[6] |INTEN |WDT Time-out Interrupt Enable Control (Write Protect) + * | | |If this bit is enabled, when WDT time-out event occurs, the IF (WDT_CTL[3]) will be set to 1 and the WDT time-out interrupt signal is generated and inform to CPU. + * | | |0 = WDT time-out interrupt Disabled. + * | | |1 = WDT time-out interrupt Enabled. + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * |[7] |WDTEN |WDT Enable Control (Write Protect) + * | | |0 = Set WDT counter stop Disabled, and (This action will reset the internal up counter value will be reset also). + * | | |1 = Set WDT counter start Enabled. + * | | |Note1: This bit is write protected. Refer to the SYS_REGLCTL register. + * | | |Note2: Perform enable or disable WDTEN bit needs 2 * WDT_CLK period to become active, user can read SYNC (WDT_CTL[30]) to check enable/disable command is completed or not. + * | | |Note32: If CWDTEN[2:0] (combined by with Config0[31] and Config0[4:3]) bits is not configure to 0x111, this bit is forced as 1 and user cannot change this bit to 0. + * | | |Note3: This bit disabled needs 2 * WDT_CLK. + * |[11:8] |TOUTSEL |WDT Time-out Interval Selection (Write Protect) + * | | |These three bits select the time-out interval period after for the WDT starts counting. + * | | |000 = 2^4 * WDT_CLK. + * | | |001 = 2^6 * WDT_CLK. + * | | |010 = 2^8 * WDT_CLK. + * | | |011 = 2^10 * WDT_CLK. + * | | |100 = 2^12 * WDT_CLK. + * | | |101 = 2^14 * WDT_CLK. + * | | |110 = 2^16 * WDT_CLK. + * | | |111 = 2^18 * WDT_CLK. + * | | |111 = 2^20 * WDT_CLK. + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * |[30] |SYNC |WDT Enable Control SYNC SYNC Flag Indicator (Read Only) + * | | |If use to synchronization, software er can check execute enable/disable this flag after enable WDTEN (WDT_CTL[7]), this flag can be indicated enable/disable WDTEN function is become completed or not active or not.. + * | | |SYNC delay is + * | | |0 = Set WDTEN bit is WDT enable control synccompletedhronizing is completion. + * | | |1 = Set WDTEN bit WDT enable control is synchronizing and not become active yet.. + * | | |Note: Perform enable or disable WDTEN bit + * | | |This bit enabled needs 2 * WDT_CLK period to become active. + * |[31] |ICEDEBUG |ICE Debug Mode Acknowledge Disable Control (Write Protect) + * | | |0 = ICE debug mode acknowledgment affects WDT counting. + * | | |WDT up counter will be held while CPU is held by ICE. + * | | |1 = ICE debug mode acknowledgment Disabled. + * | | |WDT up counter will keep going no matter CPU is held by ICE or not. + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * @var EWDT_T::ALTCTL + * Offset: 0x04 EWDT Alternative Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[1:0] |RSTDSEL |WDT Reset Delay Period Selection (Write Protect) + * | | |When WDT time-out event happened, user has a time named WDT Reset Delay Period to clear execute WDT counter by setting RSTCNT (WDT_CTL[0]) reset to prevent WDT time-out reset system occurred happened + * | | |User can select a suitable setting of RSTDSEL for different application program WDT Reset Delay Period. + * | | |00 = WDT Reset Delay Period is 1026 * WDT_CLK. + * | | |01 = WDT Reset Delay Period is 130 * WDT_CLK. + * | | |10 = WDT Reset Delay Period is 18 * WDT_CLK. + * | | |11 = WDT Reset Delay Period is 3 * WDT_CLK. + * | | |Note1: This bit is write protected. Refer to the SYS_REGLCTL register. + * | | |Note2: This register will be reset to 0 if WDT time-out reset system event occurred happened. + * @var EWDT_T::RSTCNT + * Offset: 0x08 EWDT Reset Counter Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |RSTCNT |WDT Reset Counter Register + * | | |Writing 0x00005AA5 to this register field will reset the internal 18-bit WDT up counter value to 0. + * | | |Note: This WDT_RSTCNT is not write protected, but this RSTCNT (WDT_CTL[0]) is write protected. + * | | |Note: Perform RSTCNT to reset counter needs 2 * WDT_CLK period to become active. + */ + __IO uint32_t CTL; /*!< [0x0000] EWDT Control Register */ + __IO uint32_t ALTCTL; /*!< [0x0004] EWDT Alternative Control Register */ + __O uint32_t RSTCNT; /*!< [0x0008] EWDT Reset Counter Register */ + +} EWDT_T; + +/** + @addtogroup EWDT_CONST WDT Bit Field Definition + Constant Definitions for EWDT Controller + @{ +*/ + +#define EWDT_CTL_RSTEN_Pos (1) /*!< EWDT_T::CTL: RSTEN Position */ +#define EWDT_CTL_RSTEN_Msk (0x1ul << EWDT_CTL_RSTEN_Pos) /*!< EWDT_T::CTL: RSTEN Mask */ + +#define EWDT_CTL_RSTF_Pos (2) /*!< EWDT_T::CTL: RSTF Position */ +#define EWDT_CTL_RSTF_Msk (0x1ul << EWDT_CTL_RSTF_Pos) /*!< EWDT_T::CTL: RSTF Mask */ + +#define EWDT_CTL_IF_Pos (3) /*!< EWDT_T::CTL: IF Position */ +#define EWDT_CTL_IF_Msk (0x1ul << EWDT_CTL_IF_Pos) /*!< EWDT_T::CTL: IF Mask */ + +#define EWDT_CTL_WKEN_Pos (4) /*!< EWDT_T::CTL: WKEN Position */ +#define EWDT_CTL_WKEN_Msk (0x1ul << EWDT_CTL_WKEN_Pos) /*!< EWDT_T::CTL: WKEN Mask */ + +#define EWDT_CTL_WKF_Pos (5) /*!< EWDT_T::CTL: WKF Position */ +#define EWDT_CTL_WKF_Msk (0x1ul << EWDT_CTL_WKF_Pos) /*!< EWDT_T::CTL: WKF Mask */ + +#define EWDT_CTL_INTEN_Pos (6) /*!< EWDT_T::CTL: INTEN Position */ +#define EWDT_CTL_INTEN_Msk (0x1ul << EWDT_CTL_INTEN_Pos) /*!< EWDT_T::CTL: INTEN Mask */ + +#define EWDT_CTL_WDTEN_Pos (7) /*!< EWDT_T::CTL: WDTEN Position */ +#define EWDT_CTL_WDTEN_Msk (0x1ul << EWDT_CTL_WDTEN_Pos) /*!< EWDT_T::CTL: WDTEN Mask */ + +#define EWDT_CTL_TOUTSEL_Pos (8) /*!< EWDT_T::CTL: TOUTSEL Position */ +#define EWDT_CTL_TOUTSEL_Msk (0xful << EWDT_CTL_TOUTSEL_Pos) /*!< EWDT_T::CTL: TOUTSEL Mask */ + +#define EWDT_CTL_SYNC_Pos (30) /*!< EWDT_T::CTL: SYNC Position */ +#define EWDT_CTL_SYNC_Msk (0x1ul << EWDT_CTL_SYNC_Pos) /*!< EWDT_T::CTL: SYNC Mask */ + +#define EWDT_CTL_ICEDEBUG_Pos (31) /*!< EWDT_T::CTL: ICEDEBUG Position */ +#define EWDT_CTL_ICEDEBUG_Msk (0x1ul << EWDT_CTL_ICEDEBUG_Pos) /*!< EWDT_T::CTL: ICEDEBUG Mask */ + +#define EWDT_ALTCTL_RSTDSEL_Pos (0) /*!< EWDT_T::ALTCTL: RSTDSEL Position */ +#define EWDT_ALTCTL_RSTDSEL_Msk (0x3ul << EWDT_ALTCTL_RSTDSEL_Pos) /*!< EWDT_T::ALTCTL: RSTDSEL Mask */ + +#define EWDT_RSTCNT_RSTCNT_Pos (0) /*!< EWDT_T::RSTCNT: RSTCNT Position */ +#define EWDT_RSTCNT_RSTCNT_Msk (0xfffffffful << EWDT_RSTCNT_RSTCNT_Pos) /*!< EWDT_T::RSTCNT: RSTCNT Mask */ + + +/**@}*/ /* EWDT_CONST */ +/**@}*/ /* end of EWDT register group */ +/**@}*/ /* end of REGISTER group */ + +#endif /* __EWDT_REG_H__ */ diff --git a/Ubiquitous/XiZi/board/nuvoton-m2354/third_party_driver/include/Regs/ewwdt_reg.h b/Ubiquitous/XiZi/board/nuvoton-m2354/third_party_driver/include/Regs/ewwdt_reg.h new file mode 100644 index 0000000..3331ccb --- /dev/null +++ b/Ubiquitous/XiZi/board/nuvoton-m2354/third_party_driver/include/Regs/ewwdt_reg.h @@ -0,0 +1,148 @@ +/**************************************************************************//** + * @file ewwdt_reg.h + * @version V1.00 + * @brief EWWDT register definition header file + * + * @copyright SPDX-License-Identifier: Apache-2.0 + * @copyright Copyright (C) 2020 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ +#ifndef __EWWDT_REG_H__ +#define __EWWDT_REG_H__ + +/** @addtogroup REGISTER Control Register + + @{ + +*/ + + +/*---------------------- Extra Window Watchdog Timer -------------------------*/ +/** + @addtogroup EWWDT Extra Window Watchdog Timer(EWWDT) + Memory Mapped Structure for EWWDT Controller + @{ +*/ + +typedef struct +{ + + + /** + * @var EWWDT_T::RLDCNT + * Offset: 0x00 WWDT Reload Counter Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |RLDCNT |WWDT Reload Counter Register + * | | |Writing only 0x00005AA5 to this register will reload the WWDT counter value to 0x3F. + * | | |Note1: User can only write execute WWDT_RLDCNT register to the reload WWDT counter value command when current current WWDT counter value CNTDAT (WWDT_CNT[5:0]) is between 10 and CMPDAT (WWDT_CTL[21:16]) + * | | |If user writes 0x00005AA5 in WWDT_RLDCNT register when current current CNTDATWWDT counter value is larger than CMPDAT, WWDT reset signal system event will be generated immediately. + * | | |Note2: Execute WWDT counter reload always needs (WWDT_CLK *3) period to reload CNTDAT to 0x3F and internal prescale counter will be reset also. + * @var EWWDT_T::CTL + * Offset: 0x04 WWDT Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |WWDTEN |WWDT Enable Control Bit + * | | |Set this bit to enable start WWDT counter counting. + * | | |0 = WWDT counter is stopped. + * | | |1 = WWDT counter is starting counting. + * |[1] |INTEN |WWDT Interrupt Enable Control Bit + * | | |If this bit is enabled, when WWDTIF (WWDT_STATUS[0]) is set to 1, the WWDT counter compare match interrupt signal is generated and inform to CPU. + * | | |0 = WWDT counter compare match interrupt Disabled. + * | | |1 = WWDT counter compare match interrupt Enabled. + * |[11:8] |PSCSEL |WWDT Counter Prescale Period Selection + * | | |0000 = Pre-scale is 1; Max time-out period is 1 * 64 * WWDT_CLK. + * | | |0001 = Pre-scale is 2; Max time-out period is 2 * 64 * WWDT_CLK. + * | | |0010 = Pre-scale is 4; Max time-out period is 4 * 64 * WWDT_CLK. + * | | |0011 = Pre-scale is 8; Max time-out period is 8 * 64 * WWDT_CLK. + * | | |0100 = Pre-scale is 16; Max time-out period is 16 * 64 * WWDT_CLK. + * | | |0101 = Pre-scale is 32; Max time-out period is 32 * 64 * WWDT_CLK. + * | | |0110 = Pre-scale is 64; Max time-out period is 64 * 64 * WWDT_CLK. + * | | |0111 = Pre-scale is 128; Max time-out period is 128 * 64 * WWDT_CLK. + * | | |1000 = Pre-scale is 192; Max time-out period is 192 * 64 * WWDT_CLK. + * | | |1001 = Pre-scale is 256; Max time-out period is 256 * 64 * WWDT_CLK. + * | | |1010 = Pre-scale is 384; Max time-out period is 384 * 64 * WWDT_CLK. + * | | |1011 = Pre-scale is 512; Max time-out period is 512 * 64 * WWDT_CLK. + * | | |1100 = Pre-scale is 768; Max time-out period is 768 * 64 * WWDT_CLK. + * | | |1101 = Pre-scale is 1024; Max time-out period is 1024 * 64 * WWDT_CLK. + * | | |1110 = Pre-scale is 1536; Max time-out period is 1536 * 64 * WWDT_CLK. + * | | |1111 = Pre-scale is 2048; Max time-out period is 2048 * 64 * WWDT_CLK. + * |[21:16] |CMPDAT |WWDT Window Compare Register Value + * | | |Set this register field to adjust the valid reload window interval when WWDTIF (WWDT_STATUS[0]) is generated.. + * | | |Note: User can only write WWDT_RLDCNT register to reload WWDT counter value when current WWDT CNTDAT (WWDT_CNT[5:]) is counter value between 10 and CMPDAT + * | | |If user writes 0x00005AA5 in WWDT_RLDCNT register when current WWDT counter value CNTDAT is larger than CMPDAT, WWDT reset system event signal will be generated immediately. + * |[31] |ICEDEBUG |ICE Debug Mode Acknowledge Disable Control + * | | |0 = ICE debug mode acknowledgment effects WWDT counter counting. + * | | |WWDT down counter will be held while CPU is held by ICE. + * | | |1 = ICE debug mode acknowledgment Disabled. + * | | |WWDT down counter will keep going counting no matter CPU is held by ICE or not. + * @var EWWDT_T::STATUS + * Offset: 0x08 WWDT Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |WWDTIF |WWDT Compare Match Interrupt Flag + * | | |This bit indicates the that current CNTDAT (WWDT_CNT[5:0]) matches the CMPDAT (WWDT_CTL[21:16])interrupt flag status of WWDT while WWDT counter value matches CMPDAT (WWDT_CTL[21:16]). + * | | |0 = No effect. + * | | |1 = WWDT WWDT CNTDAT counter value matches the CMPDAT. + * | | |Note: This bit is cleared by writing 1 to it. + * |[1] |WWDTRF |WWDT Timer-out Reset System Flag + * | | |If this bit is set to 1, it This bit indicates the that system has been reset by WWDT counter time-out reset system event.or not. + * | | |0 = WWDT time-out reset system event did not occur. + * | | |1 = WWDT time-out reset system event occurred. + * | | |Note: This bit is cleared by writing 1 to it. + * @var EWWDT_T::CNT + * Offset: 0x0C WWDT Counter Value Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[5:0] |CNTDAT |WWDT Counter Value + * | | |CNTDAT will be updated continuously to monitor 6-bit WWDT down counter value. + */ + __O uint32_t RLDCNT; /*!< [0x0000] EWWDT Reload Counter Register */ + __IO uint32_t CTL; /*!< [0x0004] EWWDT Control Register */ + __IO uint32_t STATUS; /*!< [0x0008] EWWDT Status Register */ + __I uint32_t CNT; /*!< [0x000c] EWWDT Counter Value Register */ + +} EWWDT_T; + + +/** + @addtogroup WWDT_CONST WWDT Bit Field Definition + Constant Definitions for WWDT Controller + @{ +*/ + +#define EWWDT_RLDCNT_RLDCNT_Pos (0) /*!< EWWDT_T::RLDCNT: RLDCNT Position */ +#define EWWDT_RLDCNT_RLDCNT_Msk (0xfffffffful << EWWDT_RLDCNT_RLDCNT_Pos) /*!< EWWDT_T::RLDCNT: RLDCNT Mask */ + +#define EWWDT_CTL_WWDTEN_Pos (0) /*!< EWWDT_T::CTL: WWDTEN Position */ +#define EWWDT_CTL_WWDTEN_Msk (0x1ul << EWWDT_CTL_WWDTEN_Pos) /*!< EWWDT_T::CTL: WWDTEN Mask */ + +#define EWWDT_CTL_INTEN_Pos (1) /*!< EWWDT_T::CTL: INTEN Position */ +#define EWWDT_CTL_INTEN_Msk (0x1ul << EWWDT_CTL_INTEN_Pos) /*!< EWWDT_T::CTL: INTEN Mask */ + +#define EWWDT_CTL_PSCSEL_Pos (8) /*!< EWWDT_T::CTL: PSCSEL Position */ +#define EWWDT_CTL_PSCSEL_Msk (0xful << EWWDT_CTL_PSCSEL_Pos) /*!< EWWDT_T::CTL: PSCSEL Mask */ + +#define EWWDT_CTL_CMPDAT_Pos (16) /*!< EWWDT_T::CTL: CMPDAT Position */ +#define EWWDT_CTL_CMPDAT_Msk (0x3ful << EWWDT_CTL_CMPDAT_Pos) /*!< EWWDT_T::CTL: CMPDAT Mask */ + +#define EWWDT_CTL_ICEDEBUG_Pos (31) /*!< EWWDT_T::CTL: ICEDEBUG Position */ +#define EWWDT_CTL_ICEDEBUG_Msk (0x1ul << EWWDT_CTL_ICEDEBUG_Pos) /*!< EWWDT_T::CTL: ICEDEBUG Mask */ + +#define EWWDT_STATUS_WWDTIF_Pos (0) /*!< EWWDT_T::STATUS: WWDTIF Position */ +#define EWWDT_STATUS_WWDTIF_Msk (0x1ul << EWWDT_STATUS_WWDTIF_Pos) /*!< EWWDT_T::STATUS: WWDTIF Mask */ + +#define EWWDT_STATUS_WWDTRF_Pos (1) /*!< EWWDT_T::STATUS: WWDTRF Position */ +#define EWWDT_STATUS_WWDTRF_Msk (0x1ul << EWWDT_STATUS_WWDTRF_Pos) /*!< EWWDT_T::STATUS: WWDTRF Mask */ + +#define EWWDT_CNT_CNTDAT_Pos (0) /*!< EWWDT_T::CNT: CNTDAT Position */ +#define EWWDT_CNT_CNTDAT_Msk (0x3ful << EWWDT_CNT_CNTDAT_Pos) /*!< EWWDT_T::CNT: CNTDAT Mask */ + +/**@}*/ /* EWWDT_CONST */ +/**@}*/ /* end of EWWDT register group */ +/**@}*/ /* end of REGISTER group */ + +#endif /* __EWWDT_REG_H__ */ diff --git a/Ubiquitous/XiZi/board/nuvoton-m2354/third_party_driver/include/Regs/fmc_reg.h b/Ubiquitous/XiZi/board/nuvoton-m2354/third_party_driver/include/Regs/fmc_reg.h new file mode 100644 index 0000000..95cde7b --- /dev/null +++ b/Ubiquitous/XiZi/board/nuvoton-m2354/third_party_driver/include/Regs/fmc_reg.h @@ -0,0 +1,628 @@ +/**************************************************************************//** + * @file fmc_reg.h + * @version V1.00 + * @brief FMC register definition header file + * + * @copyright SPDX-License-Identifier: Apache-2.0 + * @copyright Copyright (C) 2020 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ +#ifndef __FMC_REG_H__ +#define __FMC_REG_H__ + +/** @addtogroup REGISTER Control Register + + @{ + +*/ + + +/*---------------------- Flash Memory Controller -------------------------*/ +/** + @addtogroup FMC Flash Memory Controller(FMC) + Memory Mapped Structure for FMC Controller + @{ +*/ + +typedef struct +{ + + + /** + * @var FMC_T::ISPCTL + * Offset: 0x00 ISP Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |ISPEN |ISP Enable Bit (Write Protect) + * | | |ISP function enable bit. Set this bit to enable ISP function. + * | | |0 = ISP function Disabled. + * | | |1 = ISP function Enabled. + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * |[1] |BS |Boot Select (Write Protect) + * | | |When MBS in CONFIG0 is 1, set/clear this bit to select next booting from LDROM/APROM, respectively + * | | |This bit also functions as chip booting status flag, which can be used to check where chip booted from + * | | |This bit is initiated with the inverse value of CBS[1] (CONFIG0[7]) after any reset is happened except CPU reset (CPU is 1) or system reset (SYS) is happened + * | | |0 = Booting from APROM when MBS (CONFIG0[5]) is 1. + * | | |1 = Booting from LDROM when MBS (CONFIG0[5]) is 1. + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * |[3] |APUEN |APROM Update Enable Bit (Write Protect) + * | | |0 = APROM cannot be updated when the chip runs in APROM. + * | | |1 = APROM can be updated when the chip runs in APROM. + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * |[4] |CFGUEN |CONFIG Update Enable Bit (Write Protect) + * | | |0 = CONFIG cannot be updated. + * | | |1 = CONFIG can be updated. + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * |[5] |LDUEN |LDROM Update Enable Bit (Write Protect) + * | | |LDROM update enable bit. + * | | |0 = LDROM cannot be updated. + * | | |1 = LDROM can be updated. + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * |[6] |ISPFF |ISP Fail Flag (Write Protect) + * | | |This bit is set by hardware when a triggered ISP meets any of the following conditions: + * | | |This bit needs to be cleared by writing 1 to it. + * | | |(1) APROM writes to itself if APUEN is set to 0. + * | | |(2) LDROM writes to itself if LDUEN is set to 0. + * | | |(3) CONFIG is erased/programmed if CFGUEN is set to 0. + * | | |(4) Page Erase command at LOCK mode with ICE connection + * | | |(5) Erase or Program command at brown-out detected + * | | |(6) Destination address is illegal, such as over an available range. + * | | |(7) Invalid ISP commands + * | | |(8) KPROM is erased/programmed if KEYLOCK is set to 1 + * | | |(9) APROM is erased/programmed if KEYLOCK is set to 1 + * | | |(10) LDROM is erased/programmed if KEYLOCK is set to 1 + * | | |(11) CONFIG is erased/programmed if KEYLOCK is set to 1 and KEYENROM[0] is 0 + * | | |(12) Read any content of boot loader with ICE connection + * | | |(13) The address of block erase and bank erase is not in APROM + * | | |(14) ISP CMD in XOM region, except mass erase, page erase and chksum command + * | | |(15) The wrong setting of page erase ISP CMD in XOM + * | | |(16) Violate XOM setting one time protection + * | | |(17) Page erase ISP CMD in Secure/Non-secure region setting page + * | | |(18) Mass erase when MERASE (CFG0[13]) is disable + * | | |(19) Page erase, mass erase , multi-word program or 64-bit word program in OTP + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * |[16] |BL |Boot Loader Booting (Write Protect) + * | | |This bit is initiated with the inverses value of MBS (CONFIG0[5]) + * | | |Any reset, except CPU reset (CPU is 1) or system reset (SYS), BL will be reloaded + * | | |This bit is used to check chip boot from Boot Loader or not + * | | |User should keep original value of this bit when updating FMC_ISPCTL register. + * | | |0 = Booting from APROM or LDROM. + * | | |1 = Booting from Boot Loader. + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * |[24] |INTEN |Interrupt Enable (Write Protect) + * | | |0 = ISP INT Disabled. + * | | |1 = ISP INT Enabled. + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. Before use INT, user need to clear the INTFLAG(FMC_ISPSTS[24]) make sure INT happen at correct time. + * @var FMC_T::ISPADDR + * Offset: 0x04 ISP Address Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |ISPADDR |ISP Address + * | | |The NuMicro M2355 series is equipped with embedded flash + * | | |ISPADDR[1:0] must be kept 00 for ISP 32-bit operation + * | | |ISPADDR[2:0] must be kept 000 for ISP 64-bit operation. + * | | |For CRC32 Checksum Calculation command, this field is the flash starting address for checksum calculation, 2 KBytes alignment is necessary for CRC32 checksum calculation. + * | | |For FLASH 32-bit Program, ISP address needs word alignment (4-byte) + * | | |For FLASH 64-bit Program, ISP address needs double word alignment (8-byte). + * @var FMC_T::ISPDAT + * Offset: 0x08 ISP Data Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |ISPDAT |ISP Data + * | | |Write data to this register before ISP program operation. + * | | |Read data from this register after ISP read operation. + * | | |When ISPFF (FMC_ISPCTL[6]) is 1, ISPDAT = 0xffff_ffff + * | | |For Run CRC32 Checksum Calculation command, ISPDAT is the memory size (byte) and 2 KBytes alignment + * | | |For ISP Read CRC32 Checksum command, ISPDAT is the checksum result + * | | |If ISPDAT = 0x0000_0000, it means that (1) the checksum calculation is in progress, or (2) the memory range for checksum calculation is incorrect + * | | |For XOM page erase function, , ISPDAT = 0x0055_aa03. + * @var FMC_T::ISPCMD + * Offset: 0x0C ISP Command Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[6:0] |CMD |ISP Command + * | | |ISP command table is shown below: + * | | |0x00= FLASH Read. + * | | |0x04= Read Unique ID. + * | | |0x08= Read Flash All-One Result. + * | | |0x0B= Read Company ID. + * | | |0x0C= Read Device ID. + * | | |0x0D= Read Checksum. + * | | |0x21= FLASH 32-bit Program. + * | | |0x22= FLASH Page Erase. Erase any page in two banks, except for OTP. + * | | |0x23= FLASH Bank Erase. Erase all pages of APROM in BANK0 or BANK1. + * | | |0x25= FLASH Block Erase Erase four pages alignment of APROM in BANK0 or BANK1.. + * | | |0x27= FLASH Multi-Word Program. + * | | |0x28= Run Flash All-One Verification. + * | | |0x2D= Run Checksum Calculation. + * | | |0x2E= Vector Remap. + * | | |0x40= FLASH 64-bit Read. + * | | |0x61= FLASH 64-bit Program. + * | | |The other commands are invalid. + * @var FMC_T::ISPTRG + * Offset: 0x10 ISP Trigger Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |ISPGO |ISP Start Trigger (Write Protect) + * | | |Write 1 to start ISP operation and this bit will be cleared to 0 by hardware automatically when ISP operation is finished + * | | |When ISPGO=1, the operation of accessing value from address FMC_BA+0x00 to FMC_BA+0x68 would halt CPU still ISPGO =0 + * | | |If user want to monitor whether ISP finish or not,user can access FMC_MPSTS[0] MPBUSY. + * | | |0 = ISP operation is finished. + * | | |1 = ISP is progressed. + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * @var FMC_T::ISPSTS + * Offset: 0x40 ISP Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |ISPBUSY |ISP Busy Flag (Read Only) + * | | |Write 1 to start ISP operation and this bit will be cleared to 0 by hardware automatically when ISP operation is finished. + * | | |This bit is the mirror of ISPGO(FMC_ISPTRG[0]). + * | | |0 = ISP operation is finished. + * | | |1 = ISP is progressed. + * |[2] |CBS |Boot Selection of CONFIG (Read Only) + * | | |This bit is initiated with the CBS (CONFIG0[7]) after any reset is happened except CPU reset (CPU is 1) or system reset (SYS) is happened. + * | | |The following function is valid when MBS (FMC_ISPSTS[3])= 1. + * | | |0 = LDROM with IAP mode. + * | | |1 = APROM with IAP mode. + * |[3] |MBS |Boot From Boot Loader Selection Flag (Read Only) + * | | |This bit is initiated with the MBS (CONFIG0[5]) after any reset is happened except CPU reset (CPU is 1) or system reset (SYS) is happened + * | | |0 = Booting from Boot Loader. + * | | |1 = Booting from LDROM/APROM.(.see CBS bit setting) + * |[4] |FCYCDIS |Flash Access Cycle Auto-tuning Disabled Flag (Read Only) + * | | |This bit is set if flash access cycle auto-tuning function is disabled + * | | |The auto-tuning function is disabled by FADIS(FMC_CYCCTL[8]) or HIRC clock is not ready. + * | | |0 = Flash access cycle auto-tuning is Enabled. + * | | |1 = Flash access cycle auto-tuning is Disabled. + * |[5] |PGFF |Flash Program with Fast Verification Flag (Read Only) + * | | |This bit is set if data is mismatched at ISP programming verification + * | | |This bit is clear by performing ISP flash erase or ISP read CID operation + * | | |0 = Flash Program is success. + * | | |1 = Flash Program is fail. Program data is different with data in the flash memory + * |[6] |ISPFF |ISP Fail Flag (Write Protect) + * | | |This bit is the mirror of ISPFF (FMC_ISPCTL[6]), it needs to be cleared by writing 1 to FMC_ISPCTL[6] or FMC_ISPSTS[6] if this bit is set. + * | | |This bit is set by hardware when a triggered ISP meets any of the following conditions: + * | | |(1) APROM writes to itself if APUEN is set to 0. + * | | |(2) LDROM writes to itself if LDUEN is set to 0. + * | | |(3) CONFIG is erased/programmed if CFGUEN is set to 0. + * | | |(4) Page Erase command at LOCK mode with ICE connection + * | | |(5) Erase or Program command at brown-out detected + * | | |(6) Destination address is illegal, such as over an available range. + * | | |(7) Invalid ISP commands + * | | |(8) KPROM is erased/programmed if KEYLOCK is set to 1 + * | | |(9) APROM is erased/programmed if KEYLOCK is set to 1 + * | | |(10) LDROM is erased/programmed if KEYLOCK is set to 1 + * | | |(11) CONFIG is erased/programmed if KEYLOCK is set to 1 and KEYENROM[0] is 0. + * | | |(12) Read any content of boot loader with ICE connection + * | | |(13) The address of block erase and bank erase is not in APROM + * | | |(14) ISP CMD in XOM region, except mass erase, page erase and chksum command + * | | |(15) The wrong setting of page erase ISP CMD in XOM + * | | |(16) Violate XOM setting one time protection + * | | |(17) Page erase ISP CMD in Secure/Non-secure region setting page + * | | |(18) Mass erase when MERASE (CFG0[13]) is disable + * | | |(19) Page erase, mass erase , multi-word program or 64-bit word program in OTP + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * |[7] |ALLONE |Flash All-one Verification Flag + * | | |This bit is set by hardware if all of flash bits are 1, and clear if flash bits are not all 1 after Run Flash All-One Verification complete; this bit also can be clear by writing 1 + * | | |0 = All of flash bits are 1 after Run Flash All-One Verification complete. + * | | |1 = Flash bits are not all 1 after Run Flash All-One Verification complete. + * |[23:9] |VECMAP |Vector Page Mapping Address (Read Only) + * | | |All access to 0x0000_0000~0x0000_01FF is remapped to the flash memory address {VECMAP[14:0], 9'h000} ~ {VECMAP[14:0], 9'h1FF} + * |[24] |INTFLAG |Interrupt Flag + * | | |0 = ISP is not finish. + * | | |1 = ISP done or ISPFF set. + * @var FMC_T::CYCCTL + * Offset: 0x4C Flash Access Cycle Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[3:0] |CYCLE |Flash Access Cycle Control (Write Protect) + * | | |This register is updated automatically by hardware while FCYCDIS (FMC_ISPSTS[4]) is 0, and updated by software while auto-tuning function disabled ( FADIS (FMC_CYCTL[8]) is 1). + * | | |When auto-tuning function disabled, user needs to check the speed of HCLK and set the cycle >0. + * | | |0000 = CPU access with zero wait cycle ; Flash access cycle is 1. The HCLK working frequency range is <27MHz; Cache is disabled by hardware. + * | | |0001 = CPU access with one wait cycle if cache miss; Flash access cycle is 1. The HCLK working frequency range range is<27MHz. + * | | |0010 = CPU access with two wait cycles if cache miss; Flash access cycle is 2. The optimized HCLK working frequency range is 25~52 MHz. + * | | |0011 = CPU access with three wait cycles if cache miss; Flash access cycle is 3. The optimized HCLK working frequency range is 49~79MHz. + * | | |Others = Reserved. + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * |[8] |FADIS |Flash Access Cycle Auto-tuning Disabled Control (Write Protect) + * | | |Set this bit to disable flash access cycle auto-tuning function + * | | |0 = Flash access cycle auto-tuning is enabled. + * | | |1 = Flash access cycle auto-tuning is disabled. + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * @var FMC_T::MPDAT0 + * Offset: 0x80 ISP Data0 Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |ISPDAT0 |ISP Data 0 + * | | |This register is the first 32-bit data for 32-bit/64-bit/multi-word programming, and it is also the mirror of FMC_ISPDAT, both registers keep the same data + * @var FMC_T::MPDAT1 + * Offset: 0x84 ISP Data1 Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |ISPDAT1 |ISP Data 1 + * | | |This register is the second 32-bit data for 64-bit/multi-word programming. + * @var FMC_T::MPDAT2 + * Offset: 0x88 ISP Data2 Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |ISPDAT2 |ISP Data 2 + * | | |This register is the third 32-bit data for multi-word programming. + * @var FMC_T::MPDAT3 + * Offset: 0x8C ISP Data3 Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |ISPDAT3 |ISP Data 3 + * | | |This register is the fourth 32-bit data for multi-word programming. + * @var FMC_T::MPSTS + * Offset: 0xC0 ISP Multi-Program Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |MPBUSY |ISP Multi-word Program Busy Flag (Read Only) + * | | |Write 1 to start ISP Multi-Word program operation and this bit will be cleared to 0 by hardware automatically when ISP Multi-Word program operation is finished. + * | | |This bit is the mirror of ISPGO(FMC_ISPTRG[0]). + * | | |0 = ISP Multi-Word program operation is finished. + * | | |1 = ISP Multi-Word program operation is progressed. + * |[1] |PPGO |ISP Multi-program Status (Read Only) + * | | |0 = ISP multi-word program operation is not active. + * | | |1 = ISP multi-word program operation is in progress. + * |[2] |ISPFF |ISP Fail Flag (Read Only) + * | | |This bit is the mirror of ISPFF (FMC_ISPCTL[6]), it needs to be cleared by writing 1 to FMC_ISPCTL[6] or FMC_ISPSTS[6] + * | | |This bit is set by hardware when a triggered ISP meets any of the following conditions: + * | | |(1) APROM writes to itself if APUEN is set to 0. + * | | |(2) LDROM writes to itself if LDUEN is set to 0. + * | | |(3) CONFIG is erased/programmed if CFGUEN is set to 0. + * | | |(4) Page Erase command at LOCK mode with ICE connection + * | | |(5) Erase or Program command at brown-out detected + * | | |(6) Destination address is illegal, such as over an available range. + * | | |(7) Invalid ISP commands + * |[4] |D0 |ISP DATA 0 Flag (Read Only) + * | | |This bit is set when FMC_MPDAT0 is written and auto-clear to 0 when the FMC_MPDAT0 data is programmed to flash complete. + * | | |0 = FMC_MPDAT0 register is empty, or program to flash complete. + * | | |1 = FMC_MPDAT0 register has been written, and not program to flash complete. + * |[5] |D1 |ISP DATA 1 Flag (Read Only) + * | | |This bit is set when FMC_MPDAT1 is written and auto-clear to 0 when the FMC_MPDAT1 data is programmed to flash complete. + * | | |0 = FMC_MPDAT1 register is empty, or program to flash complete. + * | | |1 = FMC_MPDAT1 register has been written, and not program to flash complete. + * |[6] |D2 |ISP DATA 2 Flag (Read Only) + * | | |This bit is set when FMC_MPDAT2 is written and auto-clear to 0 when the FMC_MPDAT2 data is programmed to flash complete. + * | | |0 = FMC_MPDAT2 register is empty, or program to flash complete. + * | | |1 = FMC_MPDAT2 register has been written, and not program to flash complete. + * |[7] |D3 |ISP DATA 3 Flag (Read Only) + * | | |This bit is set when FMC_MPDAT3 is written and auto-clear to 0 when the FMC_MPDAT3 data is programmed to flash complete. + * | | |0 = FMC_MPDAT3 register is empty, or program to flash complete. + * | | |1 = FMC_MPDAT3 register has been written, and not program to flash complete. + * @var FMC_T::MPADDR + * Offset: 0xC4 ISP Multi-Program Address Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |MPADDR |ISP Multi-word Program Address + * | | |MPADDR is the address of ISP multi-word program operation when ISPGO flag is 1. + * | | |MPADDR will keep the final ISP address when ISP multi-word program is complete. + * @var FMC_T::XOMR0STS + * Offset: 0xD0 XOM Region 0 Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[7:0] |SIZE |XOM Region 0 Size (Page-aligned) + * | | |SIZE is the page number of XOM Region 0. + * |[31:8] |BASE |XOM Region 0 Base Address (Page-aligned) + * | | |BASE is the base address of XOM Region 0. + * @var FMC_T::XOMR1STS + * Offset: 0xD4 XOM Region 1 Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[7:0] |SIZE |XOM Region 1 Size (Page-aligned) + * | | |SIZE is the page number of XOM Region 1. + * |[31:8] |BASE |XOM Region 1 Base Address (Page-aligned) + * | | |BASE is the base address of XOM Region 1. + * @var FMC_T::XOMR2STS + * Offset: 0xD8 XOM Region 2 Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[7:0] |SIZE |XOM Region 2 Size (Page-aligned) + * | | |SIZE is the page number of XOM Region 2. + * |[31:8] |BASE |XOM Region 2 Base Address (Page-aligned) + * | | |BASE is the base address of XOM Region 2. + * @var FMC_T::XOMR3STS + * Offset: 0xDC XOM Region 3 Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[7:0] |SIZE |XOM Region 3 Size (Page-aligned) + * | | |SIZE is the page number of XOM Region 3. + * |[31:8] |BASE |XOM Region 3 Base Address (Page-aligned) + * | | |BASE is the base address of XOM Region 3. + * @var FMC_T::XOMSTS + * Offset: 0xE0 XOM Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |XOMR0ON |XOM Region 0 On + * | | |XOM Region 0 active status. + * | | |0 = No active. + * | | |1 = XOM region 0 is active. + * |[1] |XOMR1ON |XOM Region 1 On + * | | |XOM Region 1 active status. + * | | |0 = No active. + * | | |1 = XOM region 1 is active. + * |[2] |XOMR2ON |XOM Region 2 On + * | | |XOM Region 2 active status. + * | | |0 = No active. + * | | |1 = XOM region 2 is active. + * |[3] |XOMR3ON |XOM Region 3 On + * | | |XOM Region 3 active status. + * | | |0 = No active. + * | | |1 = XOM region 3 is active. + * |[4] |XOMPEF |XOM Page Erase Function Fail + * | | |XOM page erase function status. If XOMPEF is set to 1, user needs to erase XOM region again. + * | | |0 = Success. + * | | |1 = Fail. + */ + __IO uint32_t ISPCTL; /*!< [0x0000] ISP Control Register */ + __IO uint32_t ISPADDR; /*!< [0x0004] ISP Address Register */ + __IO uint32_t ISPDAT; /*!< [0x0008] ISP Data Register */ + __IO uint32_t ISPCMD; /*!< [0x000c] ISP Command Register */ + __IO uint32_t ISPTRG; /*!< [0x0010] ISP Trigger Control Register */ + __I uint32_t RESERVE0[11]; + __IO uint32_t ISPSTS; /*!< [0x0040] ISP Status Register */ + __I uint32_t RESERVE1[2]; + __IO uint32_t CYCCTL; /*!< [0x004c] Flash Access Cycle Control Register */ + __I uint32_t RESERVE2[12]; + __IO uint32_t MPDAT0; /*!< [0x0080] ISP Data0 Register */ + __IO uint32_t MPDAT1; /*!< [0x0084] ISP Data1 Register */ + __IO uint32_t MPDAT2; /*!< [0x0088] ISP Data2 Register */ + __IO uint32_t MPDAT3; /*!< [0x008c] ISP Data3 Register */ + __I uint32_t RESERVE3[12]; + __I uint32_t MPSTS; /*!< [0x00c0] ISP Multi-Program Status Register */ + __I uint32_t MPADDR; /*!< [0x00c4] ISP Multi-Program Address Register */ + __I uint32_t RESERVE4[2]; + __I uint32_t XOMR0STS; /*!< [0x00d0] XOM Region 0 Status Register */ + __I uint32_t XOMR1STS; /*!< [0x00d4] XOM Region 1 Status Register */ + __I uint32_t XOMR2STS; /*!< [0x00d8] XOM Region 2 Status Register */ + __I uint32_t XOMR3STS; /*!< [0x00dc] XOM Region 3 Status Register */ + __I uint32_t XOMSTS; /*!< [0x00e0] XOM Status Register */ + __I uint32_t RESERVE5[7]; + __IO uint32_t DFCTL; /*!< [0x0100] Data Flash Function Control Register */ + __I uint32_t RESERVE6; + __IO uint32_t DFSTS; /*!< [0x0108] Data Flash Status Register */ + __O uint32_t SCRKEY; /*!< [0x010c] Data Flash Scrambling Key Register */ + +} FMC_T; + +/** + @addtogroup FMC_CONST FMC Bit Field Definition + Constant Definitions for FMC Controller + @{ +*/ + +#define FMC_ISPCTL_ISPEN_Pos (0) /*!< FMC_T::ISPCTL: ISPEN Position */ +#define FMC_ISPCTL_ISPEN_Msk (0x1ul << FMC_ISPCTL_ISPEN_Pos) /*!< FMC_T::ISPCTL: ISPEN Mask */ + +#define FMC_ISPCTL_APUEN_Pos (3) /*!< FMC_T::ISPCTL: APUEN Position */ +#define FMC_ISPCTL_APUEN_Msk (0x1ul << FMC_ISPCTL_APUEN_Pos) /*!< FMC_T::ISPCTL: APUEN Mask */ + +#define FMC_ISPCTL_CFGUEN_Pos (4) /*!< FMC_T::ISPCTL: CFGUEN Position */ +#define FMC_ISPCTL_CFGUEN_Msk (0x1ul << FMC_ISPCTL_CFGUEN_Pos) /*!< FMC_T::ISPCTL: CFGUEN Mask */ + +#define FMC_ISPCTL_LDUEN_Pos (5) /*!< FMC_T::ISPCTL: LDUEN Position */ +#define FMC_ISPCTL_LDUEN_Msk (0x1ul << FMC_ISPCTL_LDUEN_Pos) /*!< FMC_T::ISPCTL: LDUEN Mask */ + +#define FMC_ISPCTL_ISPFF_Pos (6) /*!< FMC_T::ISPCTL: ISPFF Position */ +#define FMC_ISPCTL_ISPFF_Msk (0x1ul << FMC_ISPCTL_ISPFF_Pos) /*!< FMC_T::ISPCTL: ISPFF Mask */ + +#define FMC_ISPCTL_INTEN_Pos (24) /*!< FMC_T::ISPCTL: INTEN Position */ +#define FMC_ISPCTL_INTEN_Msk (0x1ul << FMC_ISPCTL_INTEN_Pos) /*!< FMC_T::ISPCTL: INTEN Mask */ + +#define FMC_ISPADDR_ISPADDR_Pos (0) /*!< FMC_T::ISPADDR: ISPADDR Position */ +#define FMC_ISPADDR_ISPADDR_Msk (0xfffffffful << FMC_ISPADDR_ISPADDR_Pos) /*!< FMC_T::ISPADDR: ISPADDR Mask */ + +#define FMC_ISPDAT_ISPDAT_Pos (0) /*!< FMC_T::ISPDAT: ISPDAT Position */ +#define FMC_ISPDAT_ISPDAT_Msk (0xfffffffful << FMC_ISPDAT_ISPDAT_Pos) /*!< FMC_T::ISPDAT: ISPDAT Mask */ + +#define FMC_ISPCMD_CMD_Pos (0) /*!< FMC_T::ISPCMD: CMD Position */ +#define FMC_ISPCMD_CMD_Msk (0x7ful << FMC_ISPCMD_CMD_Pos) /*!< FMC_T::ISPCMD: CMD Mask */ + +#define FMC_ISPTRG_ISPGO_Pos (0) /*!< FMC_T::ISPTRG: ISPGO Position */ +#define FMC_ISPTRG_ISPGO_Msk (0x1ul << FMC_ISPTRG_ISPGO_Pos) /*!< FMC_T::ISPTRG: ISPGO Mask */ + +#define FMC_ISPSTS_ISPBUSY_Pos (0) /*!< FMC_T::ISPSTS: ISPBUSY Position */ +#define FMC_ISPSTS_ISPBUSY_Msk (0x1ul << FMC_ISPSTS_ISPBUSY_Pos) /*!< FMC_T::ISPSTS: ISPBUSY Mask */ + +#define FMC_ISPSTS_CBS_Pos (2) /*!< FMC_T::ISPSTS: CBS Position */ +#define FMC_ISPSTS_CBS_Msk (0x1ul << FMC_ISPSTS_CBS_Pos) /*!< FMC_T::ISPSTS: CBS Mask */ + +#define FMC_ISPSTS_MBS_Pos (3) /*!< FMC_T::ISPSTS: MBS Position */ +#define FMC_ISPSTS_MBS_Msk (0x1ul << FMC_ISPSTS_MBS_Pos) /*!< FMC_T::ISPSTS: MBS Mask */ + +#define FMC_ISPSTS_FCYCDIS_Pos (4) /*!< FMC_T::ISPSTS: FCYCDIS Position */ +#define FMC_ISPSTS_FCYCDIS_Msk (0x1ul << FMC_ISPSTS_FCYCDIS_Pos) /*!< FMC_T::ISPSTS: FCYCDIS Mask */ + +#define FMC_ISPSTS_PGFF_Pos (5) /*!< FMC_T::ISPSTS: PGFF Position */ +#define FMC_ISPSTS_PGFF_Msk (0x1ul << FMC_ISPSTS_PGFF_Pos) /*!< FMC_T::ISPSTS: PGFF Mask */ + +#define FMC_ISPSTS_ISPFF_Pos (6) /*!< FMC_T::ISPSTS: ISPFF Position */ +#define FMC_ISPSTS_ISPFF_Msk (0x1ul << FMC_ISPSTS_ISPFF_Pos) /*!< FMC_T::ISPSTS: ISPFF Mask */ + +#define FMC_ISPSTS_ALLONE_Pos (7) /*!< FMC_T::ISPSTS: ALLONE Position */ +#define FMC_ISPSTS_ALLONE_Msk (0x1ul << FMC_ISPSTS_ALLONE_Pos) /*!< FMC_T::ISPSTS: ALLONE Mask */ + +#define FMC_ISPSTS_VECMAP_Pos (9) /*!< FMC_T::ISPSTS: VECMAP Position */ +#define FMC_ISPSTS_VECMAP_Msk (0x7ffful << FMC_ISPSTS_VECMAP_Pos) /*!< FMC_T::ISPSTS: VECMAP Mask */ + +#define FMC_ISPSTS_INTFLAG_Pos (24) /*!< FMC_T::ISPSTS: INTFLAG Position */ +#define FMC_ISPSTS_INTFLAG_Msk (0x1ul << FMC_ISPSTS_INTFLAG_Pos) /*!< FMC_T::ISPSTS: INTFLAG Mask */ + +#define FMC_ISPSTS_ISPCERR_Pos (28) /*!< FMC_T::ISPSTS: ISPCERR Position */ +#define FMC_ISPSTS_ISPCERR_Msk (0x1ul << FMC_ISPSTS_ISPCERR_Pos) /*!< FMC_T::ISPSTS: ISPCERR Mask */ + +#define FMC_ISPSTS_MIRBOUND_Pos (29) /*!< FMC_T::ISPSTS: MIRBOUND Position */ +#define FMC_ISPSTS_MIRBOUND_Msk (0x1ul << FMC_ISPSTS_MIRBOUND_Pos) /*!< FMC_T::ISPSTS: MIRBOUND Mask */ + +#define FMC_ISPSTS_FBS_Pos (30) /*!< FMC_T::ISPSTS: FBS Position */ +#define FMC_ISPSTS_FBS_Msk (0x1ul << FMC_ISPSTS_FBS_Pos) /*!< FMC_T::ISPSTS: FBS Mask */ + +#define FMC_CYCCTL_CYCLE_Pos (0) /*!< FMC_T::CYCCTL: CYCLE Position */ +#define FMC_CYCCTL_CYCLE_Msk (0xful << FMC_CYCCTL_CYCLE_Pos) /*!< FMC_T::CYCCTL: CYCLE Mask */ + +#define FMC_CYCCTL_FADIS_Pos (8) /*!< FMC_T::CYCCTL: FADIS Position */ +#define FMC_CYCCTL_FADIS_Msk (0x1ul << FMC_CYCCTL_FADIS_Pos) /*!< FMC_T::CYCCTL: FADIS Mask */ + +#define FMC_KPKEY0_KPKEY0_Pos (0) /*!< FMC_T::KPKEY0: KPKEY0 Position */ +#define FMC_KPKEY0_KPKEY0_Msk (0xfffffffful << FMC_KPKEY0_KPKEY0_Pos) /*!< FMC_T::KPKEY0: KPKEY0 Mask */ + +#define FMC_KPKEY1_KPKEY1_Pos (0) /*!< FMC_T::KPKEY1: KPKEY1 Position */ +#define FMC_KPKEY1_KPKEY1_Msk (0xfffffffful << FMC_KPKEY1_KPKEY1_Pos) /*!< FMC_T::KPKEY1: KPKEY1 Mask */ + +#define FMC_KPKEY2_KPKEY2_Pos (0) /*!< FMC_T::KPKEY2: KPKEY2 Position */ +#define FMC_KPKEY2_KPKEY2_Msk (0xfffffffful << FMC_KPKEY2_KPKEY2_Pos) /*!< FMC_T::KPKEY2: KPKEY2 Mask */ + +#define FMC_KPKEYTRG_KPKEYGO_Pos (0) /*!< FMC_T::KPKEYTRG: KPKEYGO Position */ +#define FMC_KPKEYTRG_KPKEYGO_Msk (0x1ul << FMC_KPKEYTRG_KPKEYGO_Pos) /*!< FMC_T::KPKEYTRG: KPKEYGO Mask */ + +#define FMC_KPKEYTRG_TCEN_Pos (1) /*!< FMC_T::KPKEYTRG: TCEN Position */ +#define FMC_KPKEYTRG_TCEN_Msk (0x1ul << FMC_KPKEYTRG_TCEN_Pos) /*!< FMC_T::KPKEYTRG: TCEN Mask */ + +#define FMC_KPKEYSTS_KEYBUSY_Pos (0) /*!< FMC_T::KPKEYSTS: KEYBUSY Position */ +#define FMC_KPKEYSTS_KEYBUSY_Msk (0x1ul << FMC_KPKEYSTS_KEYBUSY_Pos) /*!< FMC_T::KPKEYSTS: KEYBUSY Mask */ + +#define FMC_KPKEYSTS_KEYLOCK_Pos (1) /*!< FMC_T::KPKEYSTS: KEYLOCK Position */ +#define FMC_KPKEYSTS_KEYLOCK_Msk (0x1ul << FMC_KPKEYSTS_KEYLOCK_Pos) /*!< FMC_T::KPKEYSTS: KEYLOCK Mask */ + +#define FMC_KPKEYSTS_KEYMATCH_Pos (2) /*!< FMC_T::KPKEYSTS: KEYMATCH Position */ +#define FMC_KPKEYSTS_KEYMATCH_Msk (0x1ul << FMC_KPKEYSTS_KEYMATCH_Pos) /*!< FMC_T::KPKEYSTS: KEYMATCH Mask */ + +#define FMC_KPKEYSTS_FORBID_Pos (3) /*!< FMC_T::KPKEYSTS: FORBID Position */ +#define FMC_KPKEYSTS_FORBID_Msk (0x1ul << FMC_KPKEYSTS_FORBID_Pos) /*!< FMC_T::KPKEYSTS: FORBID Mask */ + +#define FMC_KPKEYSTS_KEYFLAG_Pos (4) /*!< FMC_T::KPKEYSTS: KEYFLAG Position */ +#define FMC_KPKEYSTS_KEYFLAG_Msk (0x1ul << FMC_KPKEYSTS_KEYFLAG_Pos) /*!< FMC_T::KPKEYSTS: KEYFLAG Mask */ + +#define FMC_KPKEYSTS_CFGFLAG_Pos (5) /*!< FMC_T::KPKEYSTS: CFGFLAG Position */ +#define FMC_KPKEYSTS_CFGFLAG_Msk (0x1ul << FMC_KPKEYSTS_CFGFLAG_Pos) /*!< FMC_T::KPKEYSTS: CFGFLAG Mask */ + +#define FMC_KPKEYSTS_SBKPBUSY_Pos (8) /*!< FMC_T::KPKEYSTS: SBKPBUSY Position */ +#define FMC_KPKEYSTS_SBKPBUSY_Msk (0x1ul << FMC_KPKEYSTS_SBKPBUSY_Pos) /*!< FMC_T::KPKEYSTS: SBKPBUSY Mask */ + +#define FMC_KPKEYSTS_SBKPFLAG_Pos (9) /*!< FMC_T::KPKEYSTS: SBKPFLAG Position */ +#define FMC_KPKEYSTS_SBKPFLAG_Msk (0x1ul << FMC_KPKEYSTS_SBKPFLAG_Pos) /*!< FMC_T::KPKEYSTS: SBKPFLAG Mask */ + +#define FMC_KPKEYCNT_KPKECNT_Pos (0) /*!< FMC_T::KPKEYCNT: KPKECNT Position */ +#define FMC_KPKEYCNT_KPKECNT_Msk (0x3ful << FMC_KPKEYCNT_KPKECNT_Pos) /*!< FMC_T::KPKEYCNT: KPKECNT Mask */ + +#define FMC_KPKEYCNT_KPKEMAX_Pos (8) /*!< FMC_T::KPKEYCNT: KPKEMAX Position */ +#define FMC_KPKEYCNT_KPKEMAX_Msk (0x3ful << FMC_KPKEYCNT_KPKEMAX_Pos) /*!< FMC_T::KPKEYCNT: KPKEMAX Mask */ + +#define FMC_KPCNT_KPCNT_Pos (0) /*!< FMC_T::KPCNT: KPCNT Position */ +#define FMC_KPCNT_KPCNT_Msk (0xful << FMC_KPCNT_KPCNT_Pos) /*!< FMC_T::KPCNT: KPCNT Mask */ + +#define FMC_KPCNT_KPMAX_Pos (8) /*!< FMC_T::KPCNT: KPMAX Position */ +#define FMC_KPCNT_KPMAX_Msk (0xful << FMC_KPCNT_KPMAX_Pos) /*!< FMC_T::KPCNT: KPMAX Mask */ + +#define FMC_MPDAT0_ISPDAT0_Pos (0) /*!< FMC_T::MPDAT0: ISPDAT0 Position */ +#define FMC_MPDAT0_ISPDAT0_Msk (0xfffffffful << FMC_MPDAT0_ISPDAT0_Pos) /*!< FMC_T::MPDAT0: ISPDAT0 Mask */ + +#define FMC_MPDAT1_ISPDAT1_Pos (0) /*!< FMC_T::MPDAT1: ISPDAT1 Position */ +#define FMC_MPDAT1_ISPDAT1_Msk (0xfffffffful << FMC_MPDAT1_ISPDAT1_Pos) /*!< FMC_T::MPDAT1: ISPDAT1 Mask */ + +#define FMC_MPDAT2_ISPDAT2_Pos (0) /*!< FMC_T::MPDAT2: ISPDAT2 Position */ +#define FMC_MPDAT2_ISPDAT2_Msk (0xfffffffful << FMC_MPDAT2_ISPDAT2_Pos) /*!< FMC_T::MPDAT2: ISPDAT2 Mask */ + +#define FMC_MPDAT3_ISPDAT3_Pos (0) /*!< FMC_T::MPDAT3: ISPDAT3 Position */ +#define FMC_MPDAT3_ISPDAT3_Msk (0xfffffffful << FMC_MPDAT3_ISPDAT3_Pos) /*!< FMC_T::MPDAT3: ISPDAT3 Mask */ + +#define FMC_MPSTS_MPBUSY_Pos (0) /*!< FMC_T::MPSTS: MPBUSY Position */ +#define FMC_MPSTS_MPBUSY_Msk (0x1ul << FMC_MPSTS_MPBUSY_Pos) /*!< FMC_T::MPSTS: MPBUSY Mask */ + +#define FMC_MPSTS_PPGO_Pos (1) /*!< FMC_T::MPSTS: PPGO Position */ +#define FMC_MPSTS_PPGO_Msk (0x1ul << FMC_MPSTS_PPGO_Pos) /*!< FMC_T::MPSTS: PPGO Mask */ + +#define FMC_MPSTS_ISPFF_Pos (2) /*!< FMC_T::MPSTS: ISPFF Position */ +#define FMC_MPSTS_ISPFF_Msk (0x1ul << FMC_MPSTS_ISPFF_Pos) /*!< FMC_T::MPSTS: ISPFF Mask */ + +#define FMC_MPSTS_D0_Pos (4) /*!< FMC_T::MPSTS: D0 Position */ +#define FMC_MPSTS_D0_Msk (0x1ul << FMC_MPSTS_D0_Pos) /*!< FMC_T::MPSTS: D0 Mask */ + +#define FMC_MPSTS_D1_Pos (5) /*!< FMC_T::MPSTS: D1 Position */ +#define FMC_MPSTS_D1_Msk (0x1ul << FMC_MPSTS_D1_Pos) /*!< FMC_T::MPSTS: D1 Mask */ + +#define FMC_MPSTS_D2_Pos (6) /*!< FMC_T::MPSTS: D2 Position */ +#define FMC_MPSTS_D2_Msk (0x1ul << FMC_MPSTS_D2_Pos) /*!< FMC_T::MPSTS: D2 Mask */ + +#define FMC_MPSTS_D3_Pos (7) /*!< FMC_T::MPSTS: D3 Position */ +#define FMC_MPSTS_D3_Msk (0x1ul << FMC_MPSTS_D3_Pos) /*!< FMC_T::MPSTS: D3 Mask */ + +#define FMC_MPADDR_MPADDR_Pos (0) /*!< FMC_T::MPADDR: MPADDR Position */ +#define FMC_MPADDR_MPADDR_Msk (0xfffffffful << FMC_MPADDR_MPADDR_Pos) /*!< FMC_T::MPADDR: MPADDR Mask */ + +#define FMC_XOMR0STS_SIZE_Pos (0) /*!< FMC_T::XOMR0STS: SIZE Position */ +#define FMC_XOMR0STS_SIZE_Msk (0xfful << FMC_XOMR0STS_SIZE_Pos) /*!< FMC_T::XOMR0STS: SIZE Mask */ + +#define FMC_XOMR0STS_BASE_Pos (8) /*!< FMC_T::XOMR0STS: BASE Position */ +#define FMC_XOMR0STS_BASE_Msk (0xfffffful << FMC_XOMR0STS_BASE_Pos) /*!< FMC_T::XOMR0STS: BASE Mask */ + +#define FMC_XOMR1STS_SIZE_Pos (0) /*!< FMC_T::XOMR1STS: SIZE Position */ +#define FMC_XOMR1STS_SIZE_Msk (0xfful << FMC_XOMR1STS_SIZE_Pos) /*!< FMC_T::XOMR1STS: SIZE Mask */ + +#define FMC_XOMR1STS_BASE_Pos (8) /*!< FMC_T::XOMR1STS: BASE Position */ +#define FMC_XOMR1STS_BASE_Msk (0xfffffful << FMC_XOMR1STS_BASE_Pos) /*!< FMC_T::XOMR1STS: BASE Mask */ + +#define FMC_XOMR2STS_SIZE_Pos (0) /*!< FMC_T::XOMR2STS: SIZE Position */ +#define FMC_XOMR2STS_SIZE_Msk (0xfful << FMC_XOMR2STS_SIZE_Pos) /*!< FMC_T::XOMR2STS: SIZE Mask */ + +#define FMC_XOMR2STS_BASE_Pos (8) /*!< FMC_T::XOMR2STS: BASE Position */ +#define FMC_XOMR2STS_BASE_Msk (0xfffffful << FMC_XOMR2STS_BASE_Pos) /*!< FMC_T::XOMR2STS: BASE Mask */ + +#define FMC_XOMR3STS_SIZE_Pos (0) /*!< FMC_T::XOMR3STS: SIZE Position */ +#define FMC_XOMR3STS_SIZE_Msk (0xfful << FMC_XOMR3STS_SIZE_Pos) /*!< FMC_T::XOMR3STS: SIZE Mask */ + +#define FMC_XOMR3STS_BASE_Pos (8) /*!< FMC_T::XOMR3STS: BASE Position */ +#define FMC_XOMR3STS_BASE_Msk (0xfffffful << FMC_XOMR3STS_BASE_Pos) /*!< FMC_T::XOMR3STS: BASE Mask */ + +#define FMC_XOMSTS_XOMR0ON_Pos (0) /*!< FMC_T::XOMSTS: XOMR0ON Position */ +#define FMC_XOMSTS_XOMR0ON_Msk (0x1ul << FMC_XOMSTS_XOMR0ON_Pos) /*!< FMC_T::XOMSTS: XOMR0ON Mask */ + +#define FMC_XOMSTS_XOMR1ON_Pos (1) /*!< FMC_T::XOMSTS: XOMR1ON Position */ +#define FMC_XOMSTS_XOMR1ON_Msk (0x1ul << FMC_XOMSTS_XOMR1ON_Pos) /*!< FMC_T::XOMSTS: XOMR1ON Mask */ + +#define FMC_XOMSTS_XOMR2ON_Pos (2) /*!< FMC_T::XOMSTS: XOMR2ON Position */ +#define FMC_XOMSTS_XOMR2ON_Msk (0x1ul << FMC_XOMSTS_XOMR2ON_Pos) /*!< FMC_T::XOMSTS: XOMR2ON Mask */ + +#define FMC_XOMSTS_XOMR3ON_Pos (3) /*!< FMC_T::XOMSTS: XOMR3ON Position */ +#define FMC_XOMSTS_XOMR3ON_Msk (0x1ul << FMC_XOMSTS_XOMR3ON_Pos) /*!< FMC_T::XOMSTS: XOMR3ON Mask */ + +#define FMC_XOMSTS_XOMPEF_Pos (4) /*!< FMC_T::XOMSTS: XOMPEF Position */ +#define FMC_XOMSTS_XOMPEF_Msk (0x1ul << FMC_XOMSTS_XOMPEF_Pos) /*!< FMC_T::XOMSTS: XOMPEF Mask */ + +#define FMC_DFCTL_SCRAMEN_Pos (0) /*!< FMC_T::DFCTL: SCRAMEN Position */ +#define FMC_DFCTL_SCRAMEN_Msk (0x1ul << FMC_DFCTL_SCRAMEN_Pos) /*!< FMC_T::DFCTL: SCRAMEN Mask */ + +#define FMC_DFCTL_SILENTEN_Pos (1) /*!< FMC_T::DFCTL: SILENTEN Position */ +#define FMC_DFCTL_SILENTEN_Msk (0x1ul << FMC_DFCTL_SILENTEN_Pos) /*!< FMC_T::DFCTL: SILENTEN Mask */ + +#define FMC_DFSTS_TMPCLRDONE_Pos (0) /*!< FMC_T::DFSTS: TMPCLRDONE Position */ +#define FMC_DFSTS_TMPCLRDONE_Msk (0x1ul << FMC_DFSTS_TMPCLRDONE_Pos) /*!< FMC_T::DFSTS: TMPCLRDONE Mask */ + +#define FMC_DFSTS_TMPCLRBUSY_Pos (1) /*!< FMC_T::DFSTS: TMPCLRBUSY Position */ +#define FMC_DFSTS_TMPCLRBUSY_Msk (0x1ul << FMC_DFSTS_TMPCLRBUSY_Pos) /*!< FMC_T::DFSTS: TMPCLRBUSY Mask */ + +#define FMC_SCRKEY_SCRKEY_Pos (0) /*!< FMC_T::SCRKEY: SCRKEY Position */ +#define FMC_SCRKEY_SCRKEY_Msk (0xfffffffful << FMC_SCRKEY_SCRKEY_Pos) /*!< FMC_T::SCRKEY: SCRKEY Mask */ + +/**@}*/ /* FMC_CONST */ +/**@}*/ /* end of FMC register group */ +/**@}*/ /* end of REGISTER group */ + +#endif /* __FMC_REG_H__ */ diff --git a/Ubiquitous/XiZi/board/nuvoton-m2354/third_party_driver/include/Regs/gpio_reg.h b/Ubiquitous/XiZi/board/nuvoton-m2354/third_party_driver/include/Regs/gpio_reg.h new file mode 100644 index 0000000..65cdf43 --- /dev/null +++ b/Ubiquitous/XiZi/board/nuvoton-m2354/third_party_driver/include/Regs/gpio_reg.h @@ -0,0 +1,888 @@ +/**************************************************************************//** + * @file gpio_reg.h + * @version V1.00 + * @brief GPIO register definition header file + * + * @copyright SPDX-License-Identifier: Apache-2.0 + * @copyright Copyright (C) 2020 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ +#ifndef __GPIO_REG_H__ +#define __GPIO_REG_H__ + +/** @addtogroup REGISTER Control Register + + @{ + +*/ + +/*---------------------- General Purpose Input/Output Controller -------------------------*/ +/** + @addtogroup GPIO General Purpose Input/Output Controller(GPIO) + Memory Mapped Structure for GPIO Controller + @{ +*/ + +typedef struct +{ + + + /** + * @var GPIO_T::MODE + * Offset: 0x00/0x40/0x80/0xC0/0x100/0x140/0x180/0x1C0 PA-H I/O Mode Control + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[2n+1:2n]|MODEn |Port A-H I/O Pin[n] Mode Control + * | | |Determine each I/O mode of Px.n pins. + * | | |00 = Px.n is in Input mode. + * | | |01 = Px.n is in Push-pull Output mode. + * | | |10 = Px.n is in Open-drain Output mode. + * | | |11 = Px.n is in Quasi-bidirectional mode. + * | | |Note 1: The initial value of this field is defined by CIOINI (CONFIG0 [10]). + * | | |If CIOINI is set to 0, the default value is 0xFFFF_FFFF and all pins will be quasi-bidirectional mode after chip powered on. + * | | |If CIOINI is set to 1, the default value is 0x0000_0000 and all pins will be input mode after chip powered on. + * | | |Note 2: The PC.14/ PC.15/ PD.13/ PD.15/ PF.12~15/ PG.0/ PG.1/ PG.5~8/ PH.0~3/ PH.12~15 pin is ignored. + * @var GPIO_T::DINOFF + * Offset: 0x04/0x44/0x84/0xC4/0x104/0x144/0x184/0x1C4 PA-H Digital Input Path Disable Control + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[n+16] |DINOFFn |Port A-H Pin[n] Digital Input Path Disable Control + * | | |Each of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. + * | | |If input is analog signal, users can disable Px.n digital input path to avoid input current leakage. + * | | |0 = Px.n digital input path Enabled. + * | | |1 = Px.n digital input path Disabled (digital input tied to low). + * | | |Note: The PC.14/ PC.15/ PD.13/ PD.15/ PF.12~15/ PG.0/ PG.1/ PG.5~8/ PH.0~3/ PH.12~15 pin is ignored. + * @var GPIO_T::DOUT + * Offset: 0x08/0x48/0x88/0xC8/0x108/0x148/0x188/0x1C8 PA-H Data Output Value + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[n] |DOUTn |Port A-H Pin[n] Output Value + * | | |Each of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode. + * | | |0 = Px.n will drive Low if the Px.n pin is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode. + * | | |1 = Px.n will drive High if the Px.n pin is configured as Push-pull output or Quasi-bidirectional mode. + * | | |Note: The PC.14/ PC.15/ PD.13/ PD.15/ PF.12~15/ PG.0/ PG.1/ PG.5~8/ PH.0~3/ PH.12~15 pin is ignored. + * @var GPIO_T::DATMSK + * Offset: 0x0C/0x4C/0x8C/0xCC/0x10C/0x14C/0x18C/0x1CC PA-H Data Output Write Mask + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[n] |DATMSKn |Port A-H Pin[n] Data Output Write Mask + * | | |These bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. + * | | |When the DATMSK (Px_DATMSK[n]) bit is set to 1, the corresponding DOUT (Px_DOUT[n]) bit is protected. + * | | |If the write signal is masked, writing data to the protect bit is ignored. + * | | |0 = Corresponding DOUT (Px_DOUT[n]) bit can be updated. + * | | |1 = Corresponding DOUT (Px_DOUT[n]) bit protected. + * | | |Note 1: This function only protects the corresponding DOUT (Px_DOUT[n]) bit, and will not protect the corresponding PDIO (Pxn_PDIO[0]) bit. + * | | |Note 2: The PC.14/ PC.15/ PD.13/ PD.15/ PF.12~15/ PG.0/ PG.1/ PG.5~8/ PH.0~3/ PH.12~15 pin is ignored. + * @var GPIO_T::PIN + * Offset: 0x10/0x50/0x90/0xD0/0x110/0x150/0x190/0x1D0 PA-H Pin Value + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[n] |PINn |Port A-H Pin[n] Pin Value + * | | |Each bit of the register reflects the actual status of the respective Px.n pin. + * | | |0 = The corresponding pin status is low. + * | | |1 = The corresponding pin status is high. + * | | |Note: The PC.14/ PC.15/ PD.13/ PD.15/ PF.12~15/ PG.0/ PG.1/ PG.5~8/ PH.0~3/ PH.12~15 pin is ignored. + * @var GPIO_T::DBEN + * Offset: 0x14/0x54/0x94/0xD4/0x114/0x154/0x194/0x1D4 PA-H De-Bounce Enable Control + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[n] |DBENn |Port A-H Pin[n] Input Signal De-bounce Enable Bit + * | | |The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. + * | | |If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the interrupt. + * | | |The de-bounce clock source is controlled by DBCLKSRC (Px_DBCTL [4]), one de-bounce sample cycle period is controlled by DBCLKSEL (Px_DBCTL [3:0]). + * | | |0 = Px.n de-bounce function Disabled. + * | | |1 = Px.n de-bounce function Enabled. + * | | |The de-bounce function is valid only for edge triggered interrupt. + * | | |If the interrupt mode is level triggered, the de-bounce enable bit is ignored. + * | | |Note: The PC.14/ PC.15/ PD.13/ PD.15/ PF.12~15/ PG.0/ PG.1/ PG.5~8/ PH.0~3/ PH.12~15 pin is ignored. + * @var GPIO_T::INTTYPE + * Offset: 0x18/0x58/0x98/0xD8/0x118/0x158/0x198/0x1D8 PA-H Interrupt Trigger Type Control + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[n] |TYPEn |Port A-H Pin[n] Edge or Level Detection Interrupt Trigger Type Control + * | | |TYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. + * | | |If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. + * | | |If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt. + * | | |0 = Edge trigger interrupt. + * | | |1 = Level trigger interrupt. + * | | |If the pin is set as the level trigger interrupt, only one level can be set on the registers RHIEN (Px_INTEN[n+16])/FLIEN (Px_INTEN[n]). + * | | |If both levels to trigger interrupt are set, the setting is ignored and no interrupt will occur. + * | | |The de-bounce function is valid only for edge triggered interrupt. + * | | |If the interrupt mode is level triggered, the de-bounce enable bit is ignored. + * | | |Note: The PC.14/ PC.15/ PD.13/ PD.15/ PF.12~15/ PG.0/ PG.1/ PG.5~8/ PH.0~3/ PH.12~15 pin is ignored. + * @var GPIO_T::INTEN + * Offset: 0x1C/0x5C/0x9C/0xDC/0x11C/0x15C/0x19C/0x1DC PA-H Interrupt Enable Control + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[n] |FLIENn |Port A-H Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit + * | | |The FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. + * | | |Set bit to 1 also enable the pin wake-up function. + * | | |When setting the FLIEN (Px_INTEN[n]) bit to 1 : + * | | |If the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at low level. + * | | |If the interrupt is edge trigger(TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from high to low. + * | | |0 = Px.n level low or high to low interrupt Disabled. + * | | |1 = Px.n level low or high to low interrupt Enabled. + * | | |Note: The PC.14/ PC.15/ PD.13/ PD.15/ PF.12~15/ PG.0/ PG.1/ PG.5~8/ PH.0~3/ PH.12~15 pin is ignored. + * |[n+16] |RHIENn |Port A-H Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit + * | | |The RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. + * | | |Set bit to 1 also enable the pin wake-up function. + * | | |When setting the RHIEN (Px_INTEN[n+16]) bit to 1 : + * | | |If the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at high level. + * | | |If the interrupt is edge trigger (TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from low to high. + * | | |0 = Px.n level high or low to high interrupt Disabled. + * | | |1 = Px.n level high or low to high interrupt Enabled. + * | | |Note: The PC.14/ PC.15/ PD.13/ PD.15/ PF.12~15/ PG.0/ PG.1/ PG.5~8/ PH.0~3/ PH.12~15 pin is ignored. + * @var GPIO_T::INTSRC + * Offset: 0x20/0x60/0xA0/0xE0/0x120/0x160/0x1A0/0x1E0 PA-H Interrupt Source Flag + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[n] |INTSRCn |Port A-H Pin[n] Interrupt Source Flag + * | | |Write Operation : + * | | |0 = No action. + * | | |1 = Clear the corresponding pending interrupt. + * | | |Read Operation : + * | | |0 = No interrupt at Px.n. + * | | |1 = Px.n generates an interrupt. + * | | |Note: The PC.14/ PC.15/ PD.13/ PD.15/ PF.12~15/ PG.0/ PG.1/ PG.5~8/ PH.0~3/ PH.12~15 pin is ignored. + * @var GPIO_T::SMTEN + * Offset: 0x24/0x64/0xA4/0xE4/0x124/0x164/0x1A4/0x1E4 PA-H Input Schmitt Trigger Enable + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[n] |SMTENn |Port A-H Pin[n] Input Schmitt Trigger Enable Bit + * | | |0 = Px.n input Schmitt trigger function Disabled. + * | | |1 = Px.n input Schmitt trigger function Enabled. + * | | |Note: The PC.14/ PC.15/ PD.13/ PD.15/ PF.12~15/ PG.0/ PG.1/ PG.5~8/ PH.0~3/ PH.12~15 pin is ignored. + * @var GPIO_T::SLEWCTL + * Offset: 0x28/0x68/0xA8/0xE8/0x128/0x168/0x1A8/0x1E8 PA-H High Slew Rate Control + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[2n+1:2n]|HSRENn |Port A-H Pin[n] High Slew Rate Control + * | | |00 = Px.n output with normal slew rate mode (maximum 40 MHz at 2.7V). + * | | |01 = Px.n output with high slew rate mode (maximum 80 MHz at 2.7V). + * | | |10 = Px.n output with fast slew rate mode (maximum 100 MHz at 2.7V. + * | | |11 = Reserved. + * | | |Note: The PC.14/ PC.15/ PD.13/ PD.15/ PF.12~15/ PG.0/ PG.1/ PG.5~8/ PH.0~3/ PH.12~15 pin is ignored. + * @var GPIO_T::PUSEL + * Offset: 0x30/0x70/0xB0/0xF0/0x130/0x170/0x1B0/0x1F0 PA-H Pull-up and Pull-down Selection Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[2n+1:2n]|PUSELn |Port A-H Pin[n] Pull-up and Pull-down Enable Register + * | | |Determine each I/O Pull-up/pull-down of Px.n pins. + * | | |00 = Px.n pull-up and pull-down disabled. + * | | |01 = Px.n pull-up enabled. + * | | |10 = Px.n pull-down enabled. + * | | |11 = Px.n pull-up and pull-down disabled. + * | | |Note 1: + * | | |Basically, the pull-up control and pull-down control has following behavior limitation. + * | | |The independent pull-up control register only valid when MODEn (Px_MODE[2n+1:2n]) set as tri-state and open-drain mode. + * | | |The independent pull-down control register only valid when MODEn (Px_MODE[2n+1:2n]) set as tri-state mode. + * | | |When both pull-up pull-down is set as 1 at tri-state mode, keep I/O in tri-state mode. + * | | |Note 2: The PC.14/ PC.15/ PD.13/ PD.15/ PF.12~15/ PG.0/ PG.1/ PG.5~8/ PH.0~3/ PH.12~15 pin is ignored. + * @var GPIO_T::DBCTL + * Offset: 0x34/0x74/0xB4/0xF4/0x134/0x174/0x1B4/0x1F4 PA-H Interrupt De-bounce Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[3:0] |DBCLKSEL |De-bounce Sampling Cycle Selection + * | | |0000 = Sample interrupt input once per 1 clocks. + * | | |0001 = Sample interrupt input once per 2 clocks. + * | | |0010 = Sample interrupt input once per 4 clocks. + * | | |0011 = Sample interrupt input once per 8 clocks. + * | | |0100 = Sample interrupt input once per 16 clocks. + * | | |0101 = Sample interrupt input once per 32 clocks. + * | | |0110 = Sample interrupt input once per 64 clocks. + * | | |0111 = Sample interrupt input once per 128 clocks. + * | | |1000 = Sample interrupt input once per 256 clocks. + * | | |1001 = Sample interrupt input once per 2*256 clocks. + * | | |1010 = Sample interrupt input once per 4*256 clocks. + * | | |1011 = Sample interrupt input once per 8*256 clocks. + * | | |1100 = Sample interrupt input once per 16*256 clocks. + * | | |1101 = Sample interrupt input once per 32*256 clocks. + * | | |1110 = Sample interrupt input once per 64*256 clocks. + * | | |1111 = Sample interrupt input once per 128*256 clocks. + * |[4] |DBCLKSRC |De-bounce Counter Clock Source Selection + * | | |0 = De-bounce counter clock source is the HCLK. + * | | |1 = De-bounce counter clock source is the 32 kHz internal low speed RC oscillator (LIRC). + * |[5] |ICLKON |Interrupt Clock on Mode + * | | |0 = Edge detection circuit is active only if I/O pin corresponding RHIEN (Px_INTEN[n+16])/FLIEN (Px_INTEN[n]) bit is set to 1. + * | | |1 = All I/O pins edge detection circuit is always active after reset. + * | | |Note: It is recommended to disable this bit to save system power if no special application concern. + */ + + + __IO uint32_t MODE; /*!< [0x00/0x40/0x80/0xC0/0x100/0x140/0x180/0x1C0] Port A-H I/O Mode Control */ + __IO uint32_t DINOFF; /*!< [0x04/0x44/0x84/0xC4/0x104/0x144/0x184/0x1C4] Port A-H Digital Input Path Disable Control */ + __IO uint32_t DOUT; /*!< [0x08/0x48/0x88/0xC8/0x108/0x148/0x188/0x1C8] Port A-H Data Output Value */ + __IO uint32_t DATMSK; /*!< [0x0C/0x4C/0x8C/0xCC/0x10C/0x14C/0x18C/0x1CC] Port A-H Data Output Write Mask */ + __I uint32_t PIN; /*!< [0x10/0x50/0x90/0xD0/0x110/0x150/0x190/0x1D0] Port A-H Pin Value */ + __IO uint32_t DBEN; /*!< [0x14/0x54/0x94/0xD4/0x114/0x154/0x194/0x1D4] Port A-H De-Bounce Enable Control */ + __IO uint32_t INTTYPE; /*!< [0x18/0x58/0x98/0xD8/0x118/0x158/0x198/0x1D8] Port A-H Interrupt Trigger Type Control */ + __IO uint32_t INTEN; /*!< [0x1C/0x5C/0x9C/0xDC/0x11C/0x15C/0x19C/0x1DC] Port A-H Interrupt Enable Control */ + __IO uint32_t INTSRC; /*!< [0x20/0x60/0xA0/0xE0/0x120/0x160/0x1A0/0x1E0] Port A-H Interrupt Source Flag */ + __IO uint32_t SMTEN; /*!< [0x24/0x64/0xA4/0xE4/0x124/0x164/0x1A4/0x1E4] Port A-H Input Schmitt Trigger Enable */ + __IO uint32_t SLEWCTL; /*!< [0x28/0x68/0xA8/0xE8/0x128/0x168/0x1A8/0x1E8] Port A-H High Slew Rate Control */ + __I uint32_t RESERVE0[1]; + __IO uint32_t PUSEL; /*!< [0x30/0x70/0xB0/0xF0/0x130/0x170/0x1B0/0x1F0] Port A-H Pull-up and Pull-down Selection Register */ + __IO uint32_t DBCTL; /*!< [0x34/0x74/0xB4/0xF4/0x134/0x174/0x1B4/0x1F4] Port A-H Interrupt De-bounce Control */ + +} GPIO_T; + + + +/** + @addtogroup GPIO_CONST GPIO Bit Field Definition + Constant Definitions for GPIO Controller + @{ +*/ + +#define GPIO_MODE_MODE0_Pos (0) /*!< GPIO_T::MODE: MODE0 Position */ +#define GPIO_MODE_MODE0_Msk (0x3ul << GPIO_MODE_MODE0_Pos) /*!< GPIO_T::MODE: MODE0 Mask */ + +#define GPIO_MODE_MODE1_Pos (2) /*!< GPIO_T::MODE: MODE1 Position */ +#define GPIO_MODE_MODE1_Msk (0x3ul << GPIO_MODE_MODE1_Pos) /*!< GPIO_T::MODE: MODE1 Mask */ + +#define GPIO_MODE_MODE2_Pos (4) /*!< GPIO_T::MODE: MODE2 Position */ +#define GPIO_MODE_MODE2_Msk (0x3ul << GPIO_MODE_MODE2_Pos) /*!< GPIO_T::MODE: MODE2 Mask */ + +#define GPIO_MODE_MODE3_Pos (6) /*!< GPIO_T::MODE: MODE3 Position */ +#define GPIO_MODE_MODE3_Msk (0x3ul << GPIO_MODE_MODE3_Pos) /*!< GPIO_T::MODE: MODE3 Mask */ + +#define GPIO_MODE_MODE4_Pos (8) /*!< GPIO_T::MODE: MODE4 Position */ +#define GPIO_MODE_MODE4_Msk (0x3ul << GPIO_MODE_MODE4_Pos) /*!< GPIO_T::MODE: MODE4 Mask */ + +#define GPIO_MODE_MODE5_Pos (10) /*!< GPIO_T::MODE: MODE5 Position */ +#define GPIO_MODE_MODE5_Msk (0x3ul << GPIO_MODE_MODE5_Pos) /*!< GPIO_T::MODE: MODE5 Mask */ + +#define GPIO_MODE_MODE6_Pos (12) /*!< GPIO_T::MODE: MODE6 Position */ +#define GPIO_MODE_MODE6_Msk (0x3ul << GPIO_MODE_MODE6_Pos) /*!< GPIO_T::MODE: MODE6 Mask */ + +#define GPIO_MODE_MODE7_Pos (14) /*!< GPIO_T::MODE: MODE7 Position */ +#define GPIO_MODE_MODE7_Msk (0x3ul << GPIO_MODE_MODE7_Pos) /*!< GPIO_T::MODE: MODE7 Mask */ + +#define GPIO_MODE_MODE8_Pos (16) /*!< GPIO_T::MODE: MODE8 Position */ +#define GPIO_MODE_MODE8_Msk (0x3ul << GPIO_MODE_MODE8_Pos) /*!< GPIO_T::MODE: MODE8 Mask */ + +#define GPIO_MODE_MODE9_Pos (18) /*!< GPIO_T::MODE: MODE9 Position */ +#define GPIO_MODE_MODE9_Msk (0x3ul << GPIO_MODE_MODE9_Pos) /*!< GPIO_T::MODE: MODE9 Mask */ + +#define GPIO_MODE_MODE10_Pos (20) /*!< GPIO_T::MODE: MODE10 Position */ +#define GPIO_MODE_MODE10_Msk (0x3ul << GPIO_MODE_MODE10_Pos) /*!< GPIO_T::MODE: MODE10 Mask */ + +#define GPIO_MODE_MODE11_Pos (22) /*!< GPIO_T::MODE: MODE11 Position */ +#define GPIO_MODE_MODE11_Msk (0x3ul << GPIO_MODE_MODE11_Pos) /*!< GPIO_T::MODE: MODE11 Mask */ + +#define GPIO_MODE_MODE12_Pos (24) /*!< GPIO_T::MODE: MODE12 Position */ +#define GPIO_MODE_MODE12_Msk (0x3ul << GPIO_MODE_MODE12_Pos) /*!< GPIO_T::MODE: MODE12 Mask */ + +#define GPIO_MODE_MODE13_Pos (26) /*!< GPIO_T::MODE: MODE13 Position */ +#define GPIO_MODE_MODE13_Msk (0x3ul << GPIO_MODE_MODE13_Pos) /*!< GPIO_T::MODE: MODE13 Mask */ + +#define GPIO_MODE_MODE14_Pos (28) /*!< GPIO_T::MODE: MODE14 Position */ +#define GPIO_MODE_MODE14_Msk (0x3ul << GPIO_MODE_MODE14_Pos) /*!< GPIO_T::MODE: MODE14 Mask */ + +#define GPIO_MODE_MODE15_Pos (30) /*!< GPIO_T::MODE: MODE15 Position */ +#define GPIO_MODE_MODE15_Msk (0x3ul << GPIO_MODE_MODE15_Pos) /*!< GPIO_T::MODE: MODE15 Mask */ + +#define GPIO_DINOFF_DINOFF0_Pos (16) /*!< GPIO_T::DINOFF: DINOFF0 Position */ +#define GPIO_DINOFF_DINOFF0_Msk (0x1ul << GPIO_DINOFF_DINOFF0_Pos) /*!< GPIO_T::DINOFF: DINOFF0 Mask */ + +#define GPIO_DINOFF_DINOFF1_Pos (17) /*!< GPIO_T::DINOFF: DINOFF1 Position */ +#define GPIO_DINOFF_DINOFF1_Msk (0x1ul << GPIO_DINOFF_DINOFF1_Pos) /*!< GPIO_T::DINOFF: DINOFF1 Mask */ + +#define GPIO_DINOFF_DINOFF2_Pos (18) /*!< GPIO_T::DINOFF: DINOFF2 Position */ +#define GPIO_DINOFF_DINOFF2_Msk (0x1ul << GPIO_DINOFF_DINOFF2_Pos) /*!< GPIO_T::DINOFF: DINOFF2 Mask */ + +#define GPIO_DINOFF_DINOFF3_Pos (19) /*!< GPIO_T::DINOFF: DINOFF3 Position */ +#define GPIO_DINOFF_DINOFF3_Msk (0x1ul << GPIO_DINOFF_DINOFF3_Pos) /*!< GPIO_T::DINOFF: DINOFF3 Mask */ + +#define GPIO_DINOFF_DINOFF4_Pos (20) /*!< GPIO_T::DINOFF: DINOFF4 Position */ +#define GPIO_DINOFF_DINOFF4_Msk (0x1ul << GPIO_DINOFF_DINOFF4_Pos) /*!< GPIO_T::DINOFF: DINOFF4 Mask */ + +#define GPIO_DINOFF_DINOFF5_Pos (21) /*!< GPIO_T::DINOFF: DINOFF5 Position */ +#define GPIO_DINOFF_DINOFF5_Msk (0x1ul << GPIO_DINOFF_DINOFF5_Pos) /*!< GPIO_T::DINOFF: DINOFF5 Mask */ + +#define GPIO_DINOFF_DINOFF6_Pos (22) /*!< GPIO_T::DINOFF: DINOFF6 Position */ +#define GPIO_DINOFF_DINOFF6_Msk (0x1ul << GPIO_DINOFF_DINOFF6_Pos) /*!< GPIO_T::DINOFF: DINOFF6 Mask */ + +#define GPIO_DINOFF_DINOFF7_Pos (23) /*!< GPIO_T::DINOFF: DINOFF7 Position */ +#define GPIO_DINOFF_DINOFF7_Msk (0x1ul << GPIO_DINOFF_DINOFF7_Pos) /*!< GPIO_T::DINOFF: DINOFF7 Mask */ + +#define GPIO_DINOFF_DINOFF8_Pos (24) /*!< GPIO_T::DINOFF: DINOFF8 Position */ +#define GPIO_DINOFF_DINOFF8_Msk (0x1ul << GPIO_DINOFF_DINOFF8_Pos) /*!< GPIO_T::DINOFF: DINOFF8 Mask */ + +#define GPIO_DINOFF_DINOFF9_Pos (25) /*!< GPIO_T::DINOFF: DINOFF9 Position */ +#define GPIO_DINOFF_DINOFF9_Msk (0x1ul << GPIO_DINOFF_DINOFF9_Pos) /*!< GPIO_T::DINOFF: DINOFF9 Mask */ + +#define GPIO_DINOFF_DINOFF10_Pos (26) /*!< GPIO_T::DINOFF: DINOFF10 Position */ +#define GPIO_DINOFF_DINOFF10_Msk (0x1ul << GPIO_DINOFF_DINOFF10_Pos) /*!< GPIO_T::DINOFF: DINOFF10 Mask */ + +#define GPIO_DINOFF_DINOFF11_Pos (27) /*!< GPIO_T::DINOFF: DINOFF11 Position */ +#define GPIO_DINOFF_DINOFF11_Msk (0x1ul << GPIO_DINOFF_DINOFF11_Pos) /*!< GPIO_T::DINOFF: DINOFF11 Mask */ + +#define GPIO_DINOFF_DINOFF12_Pos (28) /*!< GPIO_T::DINOFF: DINOFF12 Position */ +#define GPIO_DINOFF_DINOFF12_Msk (0x1ul << GPIO_DINOFF_DINOFF12_Pos) /*!< GPIO_T::DINOFF: DINOFF12 Mask */ + +#define GPIO_DINOFF_DINOFF13_Pos (29) /*!< GPIO_T::DINOFF: DINOFF13 Position */ +#define GPIO_DINOFF_DINOFF13_Msk (0x1ul << GPIO_DINOFF_DINOFF13_Pos) /*!< GPIO_T::DINOFF: DINOFF13 Mask */ + +#define GPIO_DINOFF_DINOFF14_Pos (30) /*!< GPIO_T::DINOFF: DINOFF14 Position */ +#define GPIO_DINOFF_DINOFF14_Msk (0x1ul << GPIO_DINOFF_DINOFF14_Pos) /*!< GPIO_T::DINOFF: DINOFF14 Mask */ + +#define GPIO_DINOFF_DINOFF15_Pos (31) /*!< GPIO_T::DINOFF: DINOFF15 Position */ +#define GPIO_DINOFF_DINOFF15_Msk (0x1ul << GPIO_DINOFF_DINOFF15_Pos) /*!< GPIO_T::DINOFF: DINOFF15 Mask */ + +#define GPIO_DOUT_DOUT0_Pos (0) /*!< GPIO_T::DOUT: DOUT0 Position */ +#define GPIO_DOUT_DOUT0_Msk (0x1ul << GPIO_DOUT_DOUT0_Pos) /*!< GPIO_T::DOUT: DOUT0 Mask */ + +#define GPIO_DOUT_DOUT1_Pos (1) /*!< GPIO_T::DOUT: DOUT1 Position */ +#define GPIO_DOUT_DOUT1_Msk (0x1ul << GPIO_DOUT_DOUT1_Pos) /*!< GPIO_T::DOUT: DOUT1 Mask */ + +#define GPIO_DOUT_DOUT2_Pos (2) /*!< GPIO_T::DOUT: DOUT2 Position */ +#define GPIO_DOUT_DOUT2_Msk (0x1ul << GPIO_DOUT_DOUT2_Pos) /*!< GPIO_T::DOUT: DOUT2 Mask */ + +#define GPIO_DOUT_DOUT3_Pos (3) /*!< GPIO_T::DOUT: DOUT3 Position */ +#define GPIO_DOUT_DOUT3_Msk (0x1ul << GPIO_DOUT_DOUT3_Pos) /*!< GPIO_T::DOUT: DOUT3 Mask */ + +#define GPIO_DOUT_DOUT4_Pos (4) /*!< GPIO_T::DOUT: DOUT4 Position */ +#define GPIO_DOUT_DOUT4_Msk (0x1ul << GPIO_DOUT_DOUT4_Pos) /*!< GPIO_T::DOUT: DOUT4 Mask */ + +#define GPIO_DOUT_DOUT5_Pos (5) /*!< GPIO_T::DOUT: DOUT5 Position */ +#define GPIO_DOUT_DOUT5_Msk (0x1ul << GPIO_DOUT_DOUT5_Pos) /*!< GPIO_T::DOUT: DOUT5 Mask */ + +#define GPIO_DOUT_DOUT6_Pos (6) /*!< GPIO_T::DOUT: DOUT6 Position */ +#define GPIO_DOUT_DOUT6_Msk (0x1ul << GPIO_DOUT_DOUT6_Pos) /*!< GPIO_T::DOUT: DOUT6 Mask */ + +#define GPIO_DOUT_DOUT7_Pos (7) /*!< GPIO_T::DOUT: DOUT7 Position */ +#define GPIO_DOUT_DOUT7_Msk (0x1ul << GPIO_DOUT_DOUT7_Pos) /*!< GPIO_T::DOUT: DOUT7 Mask */ + +#define GPIO_DOUT_DOUT8_Pos (8) /*!< GPIO_T::DOUT: DOUT8 Position */ +#define GPIO_DOUT_DOUT8_Msk (0x1ul << GPIO_DOUT_DOUT8_Pos) /*!< GPIO_T::DOUT: DOUT8 Mask */ + +#define GPIO_DOUT_DOUT9_Pos (9) /*!< GPIO_T::DOUT: DOUT9 Position */ +#define GPIO_DOUT_DOUT9_Msk (0x1ul << GPIO_DOUT_DOUT9_Pos) /*!< GPIO_T::DOUT: DOUT9 Mask */ + +#define GPIO_DOUT_DOUT10_Pos (10) /*!< GPIO_T::DOUT: DOUT10 Position */ +#define GPIO_DOUT_DOUT10_Msk (0x1ul << GPIO_DOUT_DOUT10_Pos) /*!< GPIO_T::DOUT: DOUT10 Mask */ + +#define GPIO_DOUT_DOUT11_Pos (11) /*!< GPIO_T::DOUT: DOUT11 Position */ +#define GPIO_DOUT_DOUT11_Msk (0x1ul << GPIO_DOUT_DOUT11_Pos) /*!< GPIO_T::DOUT: DOUT11 Mask */ + +#define GPIO_DOUT_DOUT12_Pos (12) /*!< GPIO_T::DOUT: DOUT12 Position */ +#define GPIO_DOUT_DOUT12_Msk (0x1ul << GPIO_DOUT_DOUT12_Pos) /*!< GPIO_T::DOUT: DOUT12 Mask */ + +#define GPIO_DOUT_DOUT13_Pos (13) /*!< GPIO_T::DOUT: DOUT13 Position */ +#define GPIO_DOUT_DOUT13_Msk (0x1ul << GPIO_DOUT_DOUT13_Pos) /*!< GPIO_T::DOUT: DOUT13 Mask */ + +#define GPIO_DOUT_DOUT14_Pos (14) /*!< GPIO_T::DOUT: DOUT14 Position */ +#define GPIO_DOUT_DOUT14_Msk (0x1ul << GPIO_DOUT_DOUT14_Pos) /*!< GPIO_T::DOUT: DOUT14 Mask */ + +#define GPIO_DOUT_DOUT15_Pos (15) /*!< GPIO_T::DOUT: DOUT15 Position */ +#define GPIO_DOUT_DOUT15_Msk (0x1ul << GPIO_DOUT_DOUT15_Pos) /*!< GPIO_T::DOUT: DOUT15 Mask */ + +#define GPIO_DATMSK_DATMSK0_Pos (0) /*!< GPIO_T::DATMSK: DATMSK0 Position */ +#define GPIO_DATMSK_DATMSK0_Msk (0x1ul << GPIO_DATMSK_DATMSK0_Pos) /*!< GPIO_T::DATMSK: DATMSK0 Mask */ + +#define GPIO_DATMSK_DATMSK1_Pos (1) /*!< GPIO_T::DATMSK: DATMSK1 Position */ +#define GPIO_DATMSK_DATMSK1_Msk (0x1ul << GPIO_DATMSK_DATMSK1_Pos) /*!< GPIO_T::DATMSK: DATMSK1 Mask */ + +#define GPIO_DATMSK_DATMSK2_Pos (2) /*!< GPIO_T::DATMSK: DATMSK2 Position */ +#define GPIO_DATMSK_DATMSK2_Msk (0x1ul << GPIO_DATMSK_DATMSK2_Pos) /*!< GPIO_T::DATMSK: DATMSK2 Mask */ + +#define GPIO_DATMSK_DATMSK3_Pos (3) /*!< GPIO_T::DATMSK: DATMSK3 Position */ +#define GPIO_DATMSK_DATMSK3_Msk (0x1ul << GPIO_DATMSK_DATMSK3_Pos) /*!< GPIO_T::DATMSK: DATMSK3 Mask */ + +#define GPIO_DATMSK_DATMSK4_Pos (4) /*!< GPIO_T::DATMSK: DATMSK4 Position */ +#define GPIO_DATMSK_DATMSK4_Msk (0x1ul << GPIO_DATMSK_DATMSK4_Pos) /*!< GPIO_T::DATMSK: DATMSK4 Mask */ + +#define GPIO_DATMSK_DATMSK5_Pos (5) /*!< GPIO_T::DATMSK: DATMSK5 Position */ +#define GPIO_DATMSK_DATMSK5_Msk (0x1ul << GPIO_DATMSK_DATMSK5_Pos) /*!< GPIO_T::DATMSK: DATMSK5 Mask */ + +#define GPIO_DATMSK_DATMSK6_Pos (6) /*!< GPIO_T::DATMSK: DATMSK6 Position */ +#define GPIO_DATMSK_DATMSK6_Msk (0x1ul << GPIO_DATMSK_DATMSK6_Pos) /*!< GPIO_T::DATMSK: DATMSK6 Mask */ + +#define GPIO_DATMSK_DATMSK7_Pos (7) /*!< GPIO_T::DATMSK: DATMSK7 Position */ +#define GPIO_DATMSK_DATMSK7_Msk (0x1ul << GPIO_DATMSK_DATMSK7_Pos) /*!< GPIO_T::DATMSK: DATMSK7 Mask */ + +#define GPIO_DATMSK_DATMSK8_Pos (8) /*!< GPIO_T::DATMSK: DATMSK8 Position */ +#define GPIO_DATMSK_DATMSK8_Msk (0x1ul << GPIO_DATMSK_DATMSK8_Pos) /*!< GPIO_T::DATMSK: DATMSK8 Mask */ + +#define GPIO_DATMSK_DATMSK9_Pos (9) /*!< GPIO_T::DATMSK: DATMSK9 Position */ +#define GPIO_DATMSK_DATMSK9_Msk (0x1ul << GPIO_DATMSK_DATMSK9_Pos) /*!< GPIO_T::DATMSK: DATMSK9 Mask */ + +#define GPIO_DATMSK_DATMSK10_Pos (10) /*!< GPIO_T::DATMSK: DATMSK10 Position */ +#define GPIO_DATMSK_DATMSK10_Msk (0x1ul << GPIO_DATMSK_DATMSK10_Pos) /*!< GPIO_T::DATMSK: DATMSK10 Mask */ + +#define GPIO_DATMSK_DATMSK11_Pos (11) /*!< GPIO_T::DATMSK: DATMSK11 Position */ +#define GPIO_DATMSK_DATMSK11_Msk (0x1ul << GPIO_DATMSK_DATMSK11_Pos) /*!< GPIO_T::DATMSK: DATMSK11 Mask */ + +#define GPIO_DATMSK_DATMSK12_Pos (12) /*!< GPIO_T::DATMSK: DATMSK12 Position */ +#define GPIO_DATMSK_DATMSK12_Msk (0x1ul << GPIO_DATMSK_DATMSK12_Pos) /*!< GPIO_T::DATMSK: DATMSK12 Mask */ + +#define GPIO_DATMSK_DATMSK13_Pos (13) /*!< GPIO_T::DATMSK: DATMSK13 Position */ +#define GPIO_DATMSK_DATMSK13_Msk (0x1ul << GPIO_DATMSK_DATMSK13_Pos) /*!< GPIO_T::DATMSK: DATMSK13 Mask */ + +#define GPIO_DATMSK_DATMSK14_Pos (14) /*!< GPIO_T::DATMSK: DATMSK14 Position */ +#define GPIO_DATMSK_DATMSK14_Msk (0x1ul << GPIO_DATMSK_DATMSK14_Pos) /*!< GPIO_T::DATMSK: DATMSK14 Mask */ + +#define GPIO_DATMSK_DATMSK15_Pos (15) /*!< GPIO_T::DATMSK: DATMSK15 Position */ +#define GPIO_DATMSK_DATMSK15_Msk (0x1ul << GPIO_DATMSK_DATMSK15_Pos) /*!< GPIO_T::DATMSK: DATMSK15 Mask */ + +#define GPIO_PIN_PIN0_Pos (0) /*!< GPIO_T::PIN: PIN0 Position */ +#define GPIO_PIN_PIN0_Msk (0x1ul << GPIO_PIN_PIN0_Pos) /*!< GPIO_T::PIN: PIN0 Mask */ + +#define GPIO_PIN_PIN1_Pos (1) /*!< GPIO_T::PIN: PIN1 Position */ +#define GPIO_PIN_PIN1_Msk (0x1ul << GPIO_PIN_PIN1_Pos) /*!< GPIO_T::PIN: PIN1 Mask */ + +#define GPIO_PIN_PIN2_Pos (2) /*!< GPIO_T::PIN: PIN2 Position */ +#define GPIO_PIN_PIN2_Msk (0x1ul << GPIO_PIN_PIN2_Pos) /*!< GPIO_T::PIN: PIN2 Mask */ + +#define GPIO_PIN_PIN3_Pos (3) /*!< GPIO_T::PIN: PIN3 Position */ +#define GPIO_PIN_PIN3_Msk (0x1ul << GPIO_PIN_PIN3_Pos) /*!< GPIO_T::PIN: PIN3 Mask */ + +#define GPIO_PIN_PIN4_Pos (4) /*!< GPIO_T::PIN: PIN4 Position */ +#define GPIO_PIN_PIN4_Msk (0x1ul << GPIO_PIN_PIN4_Pos) /*!< GPIO_T::PIN: PIN4 Mask */ + +#define GPIO_PIN_PIN5_Pos (5) /*!< GPIO_T::PIN: PIN5 Position */ +#define GPIO_PIN_PIN5_Msk (0x1ul << GPIO_PIN_PIN5_Pos) /*!< GPIO_T::PIN: PIN5 Mask */ + +#define GPIO_PIN_PIN6_Pos (6) /*!< GPIO_T::PIN: PIN6 Position */ +#define GPIO_PIN_PIN6_Msk (0x1ul << GPIO_PIN_PIN6_Pos) /*!< GPIO_T::PIN: PIN6 Mask */ + +#define GPIO_PIN_PIN7_Pos (7) /*!< GPIO_T::PIN: PIN7 Position */ +#define GPIO_PIN_PIN7_Msk (0x1ul << GPIO_PIN_PIN7_Pos) /*!< GPIO_T::PIN: PIN7 Mask */ + +#define GPIO_PIN_PIN8_Pos (8) /*!< GPIO_T::PIN: PIN8 Position */ +#define GPIO_PIN_PIN8_Msk (0x1ul << GPIO_PIN_PIN8_Pos) /*!< GPIO_T::PIN: PIN8 Mask */ + +#define GPIO_PIN_PIN9_Pos (9) /*!< GPIO_T::PIN: PIN9 Position */ +#define GPIO_PIN_PIN9_Msk (0x1ul << GPIO_PIN_PIN9_Pos) /*!< GPIO_T::PIN: PIN9 Mask */ + +#define GPIO_PIN_PIN10_Pos (10) /*!< GPIO_T::PIN: PIN10 Position */ +#define GPIO_PIN_PIN10_Msk (0x1ul << GPIO_PIN_PIN10_Pos) /*!< GPIO_T::PIN: PIN10 Mask */ + +#define GPIO_PIN_PIN11_Pos (11) /*!< GPIO_T::PIN: PIN11 Position */ +#define GPIO_PIN_PIN11_Msk (0x1ul << GPIO_PIN_PIN11_Pos) /*!< GPIO_T::PIN: PIN11 Mask */ + +#define GPIO_PIN_PIN12_Pos (12) /*!< GPIO_T::PIN: PIN12 Position */ +#define GPIO_PIN_PIN12_Msk (0x1ul << GPIO_PIN_PIN12_Pos) /*!< GPIO_T::PIN: PIN12 Mask */ + +#define GPIO_PIN_PIN13_Pos (13) /*!< GPIO_T::PIN: PIN13 Position */ +#define GPIO_PIN_PIN13_Msk (0x1ul << GPIO_PIN_PIN13_Pos) /*!< GPIO_T::PIN: PIN13 Mask */ + +#define GPIO_PIN_PIN14_Pos (14) /*!< GPIO_T::PIN: PIN14 Position */ +#define GPIO_PIN_PIN14_Msk (0x1ul << GPIO_PIN_PIN14_Pos) /*!< GPIO_T::PIN: PIN14 Mask */ + +#define GPIO_PIN_PIN15_Pos (15) /*!< GPIO_T::PIN: PIN15 Position */ +#define GPIO_PIN_PIN15_Msk (0x1ul << GPIO_PIN_PIN15_Pos) /*!< GPIO_T::PIN: PIN15 Mask */ + +#define GPIO_DBEN_DBEN0_Pos (0) /*!< GPIO_T::DBEN: DBEN0 Position */ +#define GPIO_DBEN_DBEN0_Msk (0x1ul << GPIO_DBEN_DBEN0_Pos) /*!< GPIO_T::DBEN: DBEN0 Mask */ + +#define GPIO_DBEN_DBEN1_Pos (1) /*!< GPIO_T::DBEN: DBEN1 Position */ +#define GPIO_DBEN_DBEN1_Msk (0x1ul << GPIO_DBEN_DBEN1_Pos) /*!< GPIO_T::DBEN: DBEN1 Mask */ + +#define GPIO_DBEN_DBEN2_Pos (2) /*!< GPIO_T::DBEN: DBEN2 Position */ +#define GPIO_DBEN_DBEN2_Msk (0x1ul << GPIO_DBEN_DBEN2_Pos) /*!< GPIO_T::DBEN: DBEN2 Mask */ + +#define GPIO_DBEN_DBEN3_Pos (3) /*!< GPIO_T::DBEN: DBEN3 Position */ +#define GPIO_DBEN_DBEN3_Msk (0x1ul << GPIO_DBEN_DBEN3_Pos) /*!< GPIO_T::DBEN: DBEN3 Mask */ + +#define GPIO_DBEN_DBEN4_Pos (4) /*!< GPIO_T::DBEN: DBEN4 Position */ +#define GPIO_DBEN_DBEN4_Msk (0x1ul << GPIO_DBEN_DBEN4_Pos) /*!< GPIO_T::DBEN: DBEN4 Mask */ + +#define GPIO_DBEN_DBEN5_Pos (5) /*!< GPIO_T::DBEN: DBEN5 Position */ +#define GPIO_DBEN_DBEN5_Msk (0x1ul << GPIO_DBEN_DBEN5_Pos) /*!< GPIO_T::DBEN: DBEN5 Mask */ + +#define GPIO_DBEN_DBEN6_Pos (6) /*!< GPIO_T::DBEN: DBEN6 Position */ +#define GPIO_DBEN_DBEN6_Msk (0x1ul << GPIO_DBEN_DBEN6_Pos) /*!< GPIO_T::DBEN: DBEN6 Mask */ + +#define GPIO_DBEN_DBEN7_Pos (7) /*!< GPIO_T::DBEN: DBEN7 Position */ +#define GPIO_DBEN_DBEN7_Msk (0x1ul << GPIO_DBEN_DBEN7_Pos) /*!< GPIO_T::DBEN: DBEN7 Mask */ + +#define GPIO_DBEN_DBEN8_Pos (8) /*!< GPIO_T::DBEN: DBEN8 Position */ +#define GPIO_DBEN_DBEN8_Msk (0x1ul << GPIO_DBEN_DBEN8_Pos) /*!< GPIO_T::DBEN: DBEN8 Mask */ + +#define GPIO_DBEN_DBEN9_Pos (9) /*!< GPIO_T::DBEN: DBEN9 Position */ +#define GPIO_DBEN_DBEN9_Msk (0x1ul << GPIO_DBEN_DBEN9_Pos) /*!< GPIO_T::DBEN: DBEN9 Mask */ + +#define GPIO_DBEN_DBEN10_Pos (10) /*!< GPIO_T::DBEN: DBEN10 Position */ +#define GPIO_DBEN_DBEN10_Msk (0x1ul << GPIO_DBEN_DBEN10_Pos) /*!< GPIO_T::DBEN: DBEN10 Mask */ + +#define GPIO_DBEN_DBEN11_Pos (11) /*!< GPIO_T::DBEN: DBEN11 Position */ +#define GPIO_DBEN_DBEN11_Msk (0x1ul << GPIO_DBEN_DBEN11_Pos) /*!< GPIO_T::DBEN: DBEN11 Mask */ + +#define GPIO_DBEN_DBEN12_Pos (12) /*!< GPIO_T::DBEN: DBEN12 Position */ +#define GPIO_DBEN_DBEN12_Msk (0x1ul << GPIO_DBEN_DBEN12_Pos) /*!< GPIO_T::DBEN: DBEN12 Mask */ + +#define GPIO_DBEN_DBEN13_Pos (13) /*!< GPIO_T::DBEN: DBEN13 Position */ +#define GPIO_DBEN_DBEN13_Msk (0x1ul << GPIO_DBEN_DBEN13_Pos) /*!< GPIO_T::DBEN: DBEN13 Mask */ + +#define GPIO_DBEN_DBEN14_Pos (14) /*!< GPIO_T::DBEN: DBEN14 Position */ +#define GPIO_DBEN_DBEN14_Msk (0x1ul << GPIO_DBEN_DBEN14_Pos) /*!< GPIO_T::DBEN: DBEN14 Mask */ + +#define GPIO_DBEN_DBEN15_Pos (15) /*!< GPIO_T::DBEN: DBEN15 Position */ +#define GPIO_DBEN_DBEN15_Msk (0x1ul << GPIO_DBEN_DBEN15_Pos) /*!< GPIO_T::DBEN: DBEN15 Mask */ + +#define GPIO_INTTYPE_TYPE0_Pos (0) /*!< GPIO_T::INTTYPE: TYPE0 Position */ +#define GPIO_INTTYPE_TYPE0_Msk (0x1ul << GPIO_INTTYPE_TYPE0_Pos) /*!< GPIO_T::INTTYPE: TYPE0 Mask */ + +#define GPIO_INTTYPE_TYPE1_Pos (1) /*!< GPIO_T::INTTYPE: TYPE1 Position */ +#define GPIO_INTTYPE_TYPE1_Msk (0x1ul << GPIO_INTTYPE_TYPE1_Pos) /*!< GPIO_T::INTTYPE: TYPE1 Mask */ + +#define GPIO_INTTYPE_TYPE2_Pos (2) /*!< GPIO_T::INTTYPE: TYPE2 Position */ +#define GPIO_INTTYPE_TYPE2_Msk (0x1ul << GPIO_INTTYPE_TYPE2_Pos) /*!< GPIO_T::INTTYPE: TYPE2 Mask */ + +#define GPIO_INTTYPE_TYPE3_Pos (3) /*!< GPIO_T::INTTYPE: TYPE3 Position */ +#define GPIO_INTTYPE_TYPE3_Msk (0x1ul << GPIO_INTTYPE_TYPE3_Pos) /*!< GPIO_T::INTTYPE: TYPE3 Mask */ + +#define GPIO_INTTYPE_TYPE4_Pos (4) /*!< GPIO_T::INTTYPE: TYPE4 Position */ +#define GPIO_INTTYPE_TYPE4_Msk (0x1ul << GPIO_INTTYPE_TYPE4_Pos) /*!< GPIO_T::INTTYPE: TYPE4 Mask */ + +#define GPIO_INTTYPE_TYPE5_Pos (5) /*!< GPIO_T::INTTYPE: TYPE5 Position */ +#define GPIO_INTTYPE_TYPE5_Msk (0x1ul << GPIO_INTTYPE_TYPE5_Pos) /*!< GPIO_T::INTTYPE: TYPE5 Mask */ + +#define GPIO_INTTYPE_TYPE6_Pos (6) /*!< GPIO_T::INTTYPE: TYPE6 Position */ +#define GPIO_INTTYPE_TYPE6_Msk (0x1ul << GPIO_INTTYPE_TYPE6_Pos) /*!< GPIO_T::INTTYPE: TYPE6 Mask */ + +#define GPIO_INTTYPE_TYPE7_Pos (7) /*!< GPIO_T::INTTYPE: TYPE7 Position */ +#define GPIO_INTTYPE_TYPE7_Msk (0x1ul << GPIO_INTTYPE_TYPE7_Pos) /*!< GPIO_T::INTTYPE: TYPE7 Mask */ + +#define GPIO_INTTYPE_TYPE8_Pos (8) /*!< GPIO_T::INTTYPE: TYPE8 Position */ +#define GPIO_INTTYPE_TYPE8_Msk (0x1ul << GPIO_INTTYPE_TYPE8_Pos) /*!< GPIO_T::INTTYPE: TYPE8 Mask */ + +#define GPIO_INTTYPE_TYPE9_Pos (9) /*!< GPIO_T::INTTYPE: TYPE9 Position */ +#define GPIO_INTTYPE_TYPE9_Msk (0x1ul << GPIO_INTTYPE_TYPE9_Pos) /*!< GPIO_T::INTTYPE: TYPE9 Mask */ + +#define GPIO_INTTYPE_TYPE10_Pos (10) /*!< GPIO_T::INTTYPE: TYPE10 Position */ +#define GPIO_INTTYPE_TYPE10_Msk (0x1ul << GPIO_INTTYPE_TYPE10_Pos) /*!< GPIO_T::INTTYPE: TYPE10 Mask */ + +#define GPIO_INTTYPE_TYPE11_Pos (11) /*!< GPIO_T::INTTYPE: TYPE11 Position */ +#define GPIO_INTTYPE_TYPE11_Msk (0x1ul << GPIO_INTTYPE_TYPE11_Pos) /*!< GPIO_T::INTTYPE: TYPE11 Mask */ + +#define GPIO_INTTYPE_TYPE12_Pos (12) /*!< GPIO_T::INTTYPE: TYPE12 Position */ +#define GPIO_INTTYPE_TYPE12_Msk (0x1ul << GPIO_INTTYPE_TYPE12_Pos) /*!< GPIO_T::INTTYPE: TYPE12 Mask */ + +#define GPIO_INTTYPE_TYPE13_Pos (13) /*!< GPIO_T::INTTYPE: TYPE13 Position */ +#define GPIO_INTTYPE_TYPE13_Msk (0x1ul << GPIO_INTTYPE_TYPE13_Pos) /*!< GPIO_T::INTTYPE: TYPE13 Mask */ + +#define GPIO_INTTYPE_TYPE14_Pos (14) /*!< GPIO_T::INTTYPE: TYPE14 Position */ +#define GPIO_INTTYPE_TYPE14_Msk (0x1ul << GPIO_INTTYPE_TYPE14_Pos) /*!< GPIO_T::INTTYPE: TYPE14 Mask */ + +#define GPIO_INTTYPE_TYPE15_Pos (15) /*!< GPIO_T::INTTYPE: TYPE15 Position */ +#define GPIO_INTTYPE_TYPE15_Msk (0x1ul << GPIO_INTTYPE_TYPE15_Pos) /*!< GPIO_T::INTTYPE: TYPE15 Mask */ + +#define GPIO_INTEN_FLIEN0_Pos (0) /*!< GPIO_T::INTEN: FLIEN0 Position */ +#define GPIO_INTEN_FLIEN0_Msk (0x1ul << GPIO_INTEN_FLIEN0_Pos) /*!< GPIO_T::INTEN: FLIEN0 Mask */ + +#define GPIO_INTEN_FLIEN1_Pos (1) /*!< GPIO_T::INTEN: FLIEN1 Position */ +#define GPIO_INTEN_FLIEN1_Msk (0x1ul << GPIO_INTEN_FLIEN1_Pos) /*!< GPIO_T::INTEN: FLIEN1 Mask */ + +#define GPIO_INTEN_FLIEN2_Pos (2) /*!< GPIO_T::INTEN: FLIEN2 Position */ +#define GPIO_INTEN_FLIEN2_Msk (0x1ul << GPIO_INTEN_FLIEN2_Pos) /*!< GPIO_T::INTEN: FLIEN2 Mask */ + +#define GPIO_INTEN_FLIEN3_Pos (3) /*!< GPIO_T::INTEN: FLIEN3 Position */ +#define GPIO_INTEN_FLIEN3_Msk (0x1ul << GPIO_INTEN_FLIEN3_Pos) /*!< GPIO_T::INTEN: FLIEN3 Mask */ + +#define GPIO_INTEN_FLIEN4_Pos (4) /*!< GPIO_T::INTEN: FLIEN4 Position */ +#define GPIO_INTEN_FLIEN4_Msk (0x1ul << GPIO_INTEN_FLIEN4_Pos) /*!< GPIO_T::INTEN: FLIEN4 Mask */ + +#define GPIO_INTEN_FLIEN5_Pos (5) /*!< GPIO_T::INTEN: FLIEN5 Position */ +#define GPIO_INTEN_FLIEN5_Msk (0x1ul << GPIO_INTEN_FLIEN5_Pos) /*!< GPIO_T::INTEN: FLIEN5 Mask */ + +#define GPIO_INTEN_FLIEN6_Pos (6) /*!< GPIO_T::INTEN: FLIEN6 Position */ +#define GPIO_INTEN_FLIEN6_Msk (0x1ul << GPIO_INTEN_FLIEN6_Pos) /*!< GPIO_T::INTEN: FLIEN6 Mask */ + +#define GPIO_INTEN_FLIEN7_Pos (7) /*!< GPIO_T::INTEN: FLIEN7 Position */ +#define GPIO_INTEN_FLIEN7_Msk (0x1ul << GPIO_INTEN_FLIEN7_Pos) /*!< GPIO_T::INTEN: FLIEN7 Mask */ + +#define GPIO_INTEN_FLIEN8_Pos (8) /*!< GPIO_T::INTEN: FLIEN8 Position */ +#define GPIO_INTEN_FLIEN8_Msk (0x1ul << GPIO_INTEN_FLIEN8_Pos) /*!< GPIO_T::INTEN: FLIEN8 Mask */ + +#define GPIO_INTEN_FLIEN9_Pos (9) /*!< GPIO_T::INTEN: FLIEN9 Position */ +#define GPIO_INTEN_FLIEN9_Msk (0x1ul << GPIO_INTEN_FLIEN9_Pos) /*!< GPIO_T::INTEN: FLIEN9 Mask */ + +#define GPIO_INTEN_FLIEN10_Pos (10) /*!< GPIO_T::INTEN: FLIEN10 Position */ +#define GPIO_INTEN_FLIEN10_Msk (0x1ul << GPIO_INTEN_FLIEN10_Pos) /*!< GPIO_T::INTEN: FLIEN10 Mask */ + +#define GPIO_INTEN_FLIEN11_Pos (11) /*!< GPIO_T::INTEN: FLIEN11 Position */ +#define GPIO_INTEN_FLIEN11_Msk (0x1ul << GPIO_INTEN_FLIEN11_Pos) /*!< GPIO_T::INTEN: FLIEN11 Mask */ + +#define GPIO_INTEN_FLIEN12_Pos (12) /*!< GPIO_T::INTEN: FLIEN12 Position */ +#define GPIO_INTEN_FLIEN12_Msk (0x1ul << GPIO_INTEN_FLIEN12_Pos) /*!< GPIO_T::INTEN: FLIEN12 Mask */ + +#define GPIO_INTEN_FLIEN13_Pos (13) /*!< GPIO_T::INTEN: FLIEN13 Position */ +#define GPIO_INTEN_FLIEN13_Msk (0x1ul << GPIO_INTEN_FLIEN13_Pos) /*!< GPIO_T::INTEN: FLIEN13 Mask */ + +#define GPIO_INTEN_FLIEN14_Pos (14) /*!< GPIO_T::INTEN: FLIEN14 Position */ +#define GPIO_INTEN_FLIEN14_Msk (0x1ul << GPIO_INTEN_FLIEN14_Pos) /*!< GPIO_T::INTEN: FLIEN14 Mask */ + +#define GPIO_INTEN_FLIEN15_Pos (15) /*!< GPIO_T::INTEN: FLIEN15 Position */ +#define GPIO_INTEN_FLIEN15_Msk (0x1ul << GPIO_INTEN_FLIEN15_Pos) /*!< GPIO_T::INTEN: FLIEN15 Mask */ + +#define GPIO_INTEN_RHIEN0_Pos (16) /*!< GPIO_T::INTEN: RHIEN0 Position */ +#define GPIO_INTEN_RHIEN0_Msk (0x1ul << GPIO_INTEN_RHIEN0_Pos) /*!< GPIO_T::INTEN: RHIEN0 Mask */ + +#define GPIO_INTEN_RHIEN1_Pos (17) /*!< GPIO_T::INTEN: RHIEN1 Position */ +#define GPIO_INTEN_RHIEN1_Msk (0x1ul << GPIO_INTEN_RHIEN1_Pos) /*!< GPIO_T::INTEN: RHIEN1 Mask */ + +#define GPIO_INTEN_RHIEN2_Pos (18) /*!< GPIO_T::INTEN: RHIEN2 Position */ +#define GPIO_INTEN_RHIEN2_Msk (0x1ul << GPIO_INTEN_RHIEN2_Pos) /*!< GPIO_T::INTEN: RHIEN2 Mask */ + +#define GPIO_INTEN_RHIEN3_Pos (19) /*!< GPIO_T::INTEN: RHIEN3 Position */ +#define GPIO_INTEN_RHIEN3_Msk (0x1ul << GPIO_INTEN_RHIEN3_Pos) /*!< GPIO_T::INTEN: RHIEN3 Mask */ + +#define GPIO_INTEN_RHIEN4_Pos (20) /*!< GPIO_T::INTEN: RHIEN4 Position */ +#define GPIO_INTEN_RHIEN4_Msk (0x1ul << GPIO_INTEN_RHIEN4_Pos) /*!< GPIO_T::INTEN: RHIEN4 Mask */ + +#define GPIO_INTEN_RHIEN5_Pos (21) /*!< GPIO_T::INTEN: RHIEN5 Position */ +#define GPIO_INTEN_RHIEN5_Msk (0x1ul << GPIO_INTEN_RHIEN5_Pos) /*!< GPIO_T::INTEN: RHIEN5 Mask */ + +#define GPIO_INTEN_RHIEN6_Pos (22) /*!< GPIO_T::INTEN: RHIEN6 Position */ +#define GPIO_INTEN_RHIEN6_Msk (0x1ul << GPIO_INTEN_RHIEN6_Pos) /*!< GPIO_T::INTEN: RHIEN6 Mask */ + +#define GPIO_INTEN_RHIEN7_Pos (23) /*!< GPIO_T::INTEN: RHIEN7 Position */ +#define GPIO_INTEN_RHIEN7_Msk (0x1ul << GPIO_INTEN_RHIEN7_Pos) /*!< GPIO_T::INTEN: RHIEN7 Mask */ + +#define GPIO_INTEN_RHIEN8_Pos (24) /*!< GPIO_T::INTEN: RHIEN8 Position */ +#define GPIO_INTEN_RHIEN8_Msk (0x1ul << GPIO_INTEN_RHIEN8_Pos) /*!< GPIO_T::INTEN: RHIEN8 Mask */ + +#define GPIO_INTEN_RHIEN9_Pos (25) /*!< GPIO_T::INTEN: RHIEN9 Position */ +#define GPIO_INTEN_RHIEN9_Msk (0x1ul << GPIO_INTEN_RHIEN9_Pos) /*!< GPIO_T::INTEN: RHIEN9 Mask */ + +#define GPIO_INTEN_RHIEN10_Pos (26) /*!< GPIO_T::INTEN: RHIEN10 Position */ +#define GPIO_INTEN_RHIEN10_Msk (0x1ul << GPIO_INTEN_RHIEN10_Pos) /*!< GPIO_T::INTEN: RHIEN10 Mask */ + +#define GPIO_INTEN_RHIEN11_Pos (27) /*!< GPIO_T::INTEN: RHIEN11 Position */ +#define GPIO_INTEN_RHIEN11_Msk (0x1ul << GPIO_INTEN_RHIEN11_Pos) /*!< GPIO_T::INTEN: RHIEN11 Mask */ + +#define GPIO_INTEN_RHIEN12_Pos (28) /*!< GPIO_T::INTEN: RHIEN12 Position */ +#define GPIO_INTEN_RHIEN12_Msk (0x1ul << GPIO_INTEN_RHIEN12_Pos) /*!< GPIO_T::INTEN: RHIEN12 Mask */ + +#define GPIO_INTEN_RHIEN13_Pos (29) /*!< GPIO_T::INTEN: RHIEN13 Position */ +#define GPIO_INTEN_RHIEN13_Msk (0x1ul << GPIO_INTEN_RHIEN13_Pos) /*!< GPIO_T::INTEN: RHIEN13 Mask */ + +#define GPIO_INTEN_RHIEN14_Pos (30) /*!< GPIO_T::INTEN: RHIEN14 Position */ +#define GPIO_INTEN_RHIEN14_Msk (0x1ul << GPIO_INTEN_RHIEN14_Pos) /*!< GPIO_T::INTEN: RHIEN14 Mask */ + +#define GPIO_INTEN_RHIEN15_Pos (31) /*!< GPIO_T::INTEN: RHIEN15 Position */ +#define GPIO_INTEN_RHIEN15_Msk (0x1ul << GPIO_INTEN_RHIEN15_Pos) /*!< GPIO_T::INTEN: RHIEN15 Mask */ + +#define GPIO_INTSRC_INTSRC0_Pos (0) /*!< GPIO_T::INTSRC: INTSRC0 Position */ +#define GPIO_INTSRC_INTSRC0_Msk (0x1ul << GPIO_INTSRC_INTSRC0_Pos) /*!< GPIO_T::INTSRC: INTSRC0 Mask */ + +#define GPIO_INTSRC_INTSRC1_Pos (1) /*!< GPIO_T::INTSRC: INTSRC1 Position */ +#define GPIO_INTSRC_INTSRC1_Msk (0x1ul << GPIO_INTSRC_INTSRC1_Pos) /*!< GPIO_T::INTSRC: INTSRC1 Mask */ + +#define GPIO_INTSRC_INTSRC2_Pos (2) /*!< GPIO_T::INTSRC: INTSRC2 Position */ +#define GPIO_INTSRC_INTSRC2_Msk (0x1ul << GPIO_INTSRC_INTSRC2_Pos) /*!< GPIO_T::INTSRC: INTSRC2 Mask */ + +#define GPIO_INTSRC_INTSRC3_Pos (3) /*!< GPIO_T::INTSRC: INTSRC3 Position */ +#define GPIO_INTSRC_INTSRC3_Msk (0x1ul << GPIO_INTSRC_INTSRC3_Pos) /*!< GPIO_T::INTSRC: INTSRC3 Mask */ + +#define GPIO_INTSRC_INTSRC4_Pos (4) /*!< GPIO_T::INTSRC: INTSRC4 Position */ +#define GPIO_INTSRC_INTSRC4_Msk (0x1ul << GPIO_INTSRC_INTSRC4_Pos) /*!< GPIO_T::INTSRC: INTSRC4 Mask */ + +#define GPIO_INTSRC_INTSRC5_Pos (5) /*!< GPIO_T::INTSRC: INTSRC5 Position */ +#define GPIO_INTSRC_INTSRC5_Msk (0x1ul << GPIO_INTSRC_INTSRC5_Pos) /*!< GPIO_T::INTSRC: INTSRC5 Mask */ + +#define GPIO_INTSRC_INTSRC6_Pos (6) /*!< GPIO_T::INTSRC: INTSRC6 Position */ +#define GPIO_INTSRC_INTSRC6_Msk (0x1ul << GPIO_INTSRC_INTSRC6_Pos) /*!< GPIO_T::INTSRC: INTSRC6 Mask */ + +#define GPIO_INTSRC_INTSRC7_Pos (7) /*!< GPIO_T::INTSRC: INTSRC7 Position */ +#define GPIO_INTSRC_INTSRC7_Msk (0x1ul << GPIO_INTSRC_INTSRC7_Pos) /*!< GPIO_T::INTSRC: INTSRC7 Mask */ + +#define GPIO_INTSRC_INTSRC8_Pos (8) /*!< GPIO_T::INTSRC: INTSRC8 Position */ +#define GPIO_INTSRC_INTSRC8_Msk (0x1ul << GPIO_INTSRC_INTSRC8_Pos) /*!< GPIO_T::INTSRC: INTSRC8 Mask */ + +#define GPIO_INTSRC_INTSRC9_Pos (9) /*!< GPIO_T::INTSRC: INTSRC9 Position */ +#define GPIO_INTSRC_INTSRC9_Msk (0x1ul << GPIO_INTSRC_INTSRC9_Pos) /*!< GPIO_T::INTSRC: INTSRC9 Mask */ + +#define GPIO_INTSRC_INTSRC10_Pos (10) /*!< GPIO_T::INTSRC: INTSRC10 Position */ +#define GPIO_INTSRC_INTSRC10_Msk (0x1ul << GPIO_INTSRC_INTSRC10_Pos) /*!< GPIO_T::INTSRC: INTSRC10 Mask */ + +#define GPIO_INTSRC_INTSRC11_Pos (11) /*!< GPIO_T::INTSRC: INTSRC11 Position */ +#define GPIO_INTSRC_INTSRC11_Msk (0x1ul << GPIO_INTSRC_INTSRC11_Pos) /*!< GPIO_T::INTSRC: INTSRC11 Mask */ + +#define GPIO_INTSRC_INTSRC12_Pos (12) /*!< GPIO_T::INTSRC: INTSRC12 Position */ +#define GPIO_INTSRC_INTSRC12_Msk (0x1ul << GPIO_INTSRC_INTSRC12_Pos) /*!< GPIO_T::INTSRC: INTSRC12 Mask */ + +#define GPIO_INTSRC_INTSRC13_Pos (13) /*!< GPIO_T::INTSRC: INTSRC13 Position */ +#define GPIO_INTSRC_INTSRC13_Msk (0x1ul << GPIO_INTSRC_INTSRC13_Pos) /*!< GPIO_T::INTSRC: INTSRC13 Mask */ + +#define GPIO_INTSRC_INTSRC14_Pos (14) /*!< GPIO_T::INTSRC: INTSRC14 Position */ +#define GPIO_INTSRC_INTSRC14_Msk (0x1ul << GPIO_INTSRC_INTSRC14_Pos) /*!< GPIO_T::INTSRC: INTSRC14 Mask */ + +#define GPIO_INTSRC_INTSRC15_Pos (15) /*!< GPIO_T::INTSRC: INTSRC15 Position */ +#define GPIO_INTSRC_INTSRC15_Msk (0x1ul << GPIO_INTSRC_INTSRC15_Pos) /*!< GPIO_T::INTSRC: INTSRC15 Mask */ + +#define GPIO_SMTEN_SMTEN0_Pos (0) /*!< GPIO_T::SMTEN: SMTEN0 Position */ +#define GPIO_SMTEN_SMTEN0_Msk (0x1ul << GPIO_SMTEN_SMTEN0_Pos) /*!< GPIO_T::SMTEN: SMTEN0 Mask */ + +#define GPIO_SMTEN_SMTEN1_Pos (1) /*!< GPIO_T::SMTEN: SMTEN1 Position */ +#define GPIO_SMTEN_SMTEN1_Msk (0x1ul << GPIO_SMTEN_SMTEN1_Pos) /*!< GPIO_T::SMTEN: SMTEN1 Mask */ + +#define GPIO_SMTEN_SMTEN2_Pos (2) /*!< GPIO_T::SMTEN: SMTEN2 Position */ +#define GPIO_SMTEN_SMTEN2_Msk (0x1ul << GPIO_SMTEN_SMTEN2_Pos) /*!< GPIO_T::SMTEN: SMTEN2 Mask */ + +#define GPIO_SMTEN_SMTEN3_Pos (3) /*!< GPIO_T::SMTEN: SMTEN3 Position */ +#define GPIO_SMTEN_SMTEN3_Msk (0x1ul << GPIO_SMTEN_SMTEN3_Pos) /*!< GPIO_T::SMTEN: SMTEN3 Mask */ + +#define GPIO_SMTEN_SMTEN4_Pos (4) /*!< GPIO_T::SMTEN: SMTEN4 Position */ +#define GPIO_SMTEN_SMTEN4_Msk (0x1ul << GPIO_SMTEN_SMTEN4_Pos) /*!< GPIO_T::SMTEN: SMTEN4 Mask */ + +#define GPIO_SMTEN_SMTEN5_Pos (5) /*!< GPIO_T::SMTEN: SMTEN5 Position */ +#define GPIO_SMTEN_SMTEN5_Msk (0x1ul << GPIO_SMTEN_SMTEN5_Pos) /*!< GPIO_T::SMTEN: SMTEN5 Mask */ + +#define GPIO_SMTEN_SMTEN6_Pos (6) /*!< GPIO_T::SMTEN: SMTEN6 Position */ +#define GPIO_SMTEN_SMTEN6_Msk (0x1ul << GPIO_SMTEN_SMTEN6_Pos) /*!< GPIO_T::SMTEN: SMTEN6 Mask */ + +#define GPIO_SMTEN_SMTEN7_Pos (7) /*!< GPIO_T::SMTEN: SMTEN7 Position */ +#define GPIO_SMTEN_SMTEN7_Msk (0x1ul << GPIO_SMTEN_SMTEN7_Pos) /*!< GPIO_T::SMTEN: SMTEN7 Mask */ + +#define GPIO_SMTEN_SMTEN8_Pos (8) /*!< GPIO_T::SMTEN: SMTEN8 Position */ +#define GPIO_SMTEN_SMTEN8_Msk (0x1ul << GPIO_SMTEN_SMTEN8_Pos) /*!< GPIO_T::SMTEN: SMTEN8 Mask */ + +#define GPIO_SMTEN_SMTEN9_Pos (9) /*!< GPIO_T::SMTEN: SMTEN9 Position */ +#define GPIO_SMTEN_SMTEN9_Msk (0x1ul << GPIO_SMTEN_SMTEN9_Pos) /*!< GPIO_T::SMTEN: SMTEN9 Mask */ + +#define GPIO_SMTEN_SMTEN10_Pos (10) /*!< GPIO_T::SMTEN: SMTEN10 Position */ +#define GPIO_SMTEN_SMTEN10_Msk (0x1ul << GPIO_SMTEN_SMTEN10_Pos) /*!< GPIO_T::SMTEN: SMTEN10 Mask */ + +#define GPIO_SMTEN_SMTEN11_Pos (11) /*!< GPIO_T::SMTEN: SMTEN11 Position */ +#define GPIO_SMTEN_SMTEN11_Msk (0x1ul << GPIO_SMTEN_SMTEN11_Pos) /*!< GPIO_T::SMTEN: SMTEN11 Mask */ + +#define GPIO_SMTEN_SMTEN12_Pos (12) /*!< GPIO_T::SMTEN: SMTEN12 Position */ +#define GPIO_SMTEN_SMTEN12_Msk (0x1ul << GPIO_SMTEN_SMTEN12_Pos) /*!< GPIO_T::SMTEN: SMTEN12 Mask */ + +#define GPIO_SMTEN_SMTEN13_Pos (13) /*!< GPIO_T::SMTEN: SMTEN13 Position */ +#define GPIO_SMTEN_SMTEN13_Msk (0x1ul << GPIO_SMTEN_SMTEN13_Pos) /*!< GPIO_T::SMTEN: SMTEN13 Mask */ + +#define GPIO_SMTEN_SMTEN14_Pos (14) /*!< GPIO_T::SMTEN: SMTEN14 Position */ +#define GPIO_SMTEN_SMTEN14_Msk (0x1ul << GPIO_SMTEN_SMTEN14_Pos) /*!< GPIO_T::SMTEN: SMTEN14 Mask */ + +#define GPIO_SMTEN_SMTEN15_Pos (15) /*!< GPIO_T::SMTEN: SMTEN15 Position */ +#define GPIO_SMTEN_SMTEN15_Msk (0x1ul << GPIO_SMTEN_SMTEN15_Pos) /*!< GPIO_T::SMTEN: SMTEN15 Mask */ + +#define GPIO_SLEWCTL_HSREN0_Pos (0) /*!< GPIO_T::SLEWCTL: HSREN0 Position */ +#define GPIO_SLEWCTL_HSREN0_Msk (0x1ul << GPIO_SLEWCTL_HSREN0_Pos) /*!< GPIO_T::SLEWCTL: HSREN0 Mask */ + +#define GPIO_SLEWCTL_HSREN1_Pos (1) /*!< GPIO_T::SLEWCTL: HSREN1 Position */ +#define GPIO_SLEWCTL_HSREN1_Msk (0x1ul << GPIO_SLEWCTL_HSREN1_Pos) /*!< GPIO_T::SLEWCTL: HSREN1 Mask */ + +#define GPIO_SLEWCTL_HSREN2_Pos (2) /*!< GPIO_T::SLEWCTL: HSREN2 Position */ +#define GPIO_SLEWCTL_HSREN2_Msk (0x1ul << GPIO_SLEWCTL_HSREN2_Pos) /*!< GPIO_T::SLEWCTL: HSREN2 Mask */ + +#define GPIO_SLEWCTL_HSREN3_Pos (3) /*!< GPIO_T::SLEWCTL: HSREN3 Position */ +#define GPIO_SLEWCTL_HSREN3_Msk (0x1ul << GPIO_SLEWCTL_HSREN3_Pos) /*!< GPIO_T::SLEWCTL: HSREN3 Mask */ + +#define GPIO_SLEWCTL_HSREN4_Pos (4) /*!< GPIO_T::SLEWCTL: HSREN4 Position */ +#define GPIO_SLEWCTL_HSREN4_Msk (0x1ul << GPIO_SLEWCTL_HSREN4_Pos) /*!< GPIO_T::SLEWCTL: HSREN4 Mask */ + +#define GPIO_SLEWCTL_HSREN5_Pos (5) /*!< GPIO_T::SLEWCTL: HSREN5 Position */ +#define GPIO_SLEWCTL_HSREN5_Msk (0x1ul << GPIO_SLEWCTL_HSREN5_Pos) /*!< GPIO_T::SLEWCTL: HSREN5 Mask */ + +#define GPIO_SLEWCTL_HSREN6_Pos (6) /*!< GPIO_T::SLEWCTL: HSREN6 Position */ +#define GPIO_SLEWCTL_HSREN6_Msk (0x1ul << GPIO_SLEWCTL_HSREN6_Pos) /*!< GPIO_T::SLEWCTL: HSREN6 Mask */ + +#define GPIO_SLEWCTL_HSREN7_Pos (7) /*!< GPIO_T::SLEWCTL: HSREN7 Position */ +#define GPIO_SLEWCTL_HSREN7_Msk (0x1ul << GPIO_SLEWCTL_HSREN7_Pos) /*!< GPIO_T::SLEWCTL: HSREN7 Mask */ + +#define GPIO_SLEWCTL_HSREN8_Pos (8) /*!< GPIO_T::SLEWCTL: HSREN8 Position */ +#define GPIO_SLEWCTL_HSREN8_Msk (0x1ul << GPIO_SLEWCTL_HSREN8_Pos) /*!< GPIO_T::SLEWCTL: HSREN8 Mask */ + +#define GPIO_SLEWCTL_HSREN9_Pos (9) /*!< GPIO_T::SLEWCTL: HSREN9 Position */ +#define GPIO_SLEWCTL_HSREN9_Msk (0x1ul << GPIO_SLEWCTL_HSREN9_Pos) /*!< GPIO_T::SLEWCTL: HSREN9 Mask */ + +#define GPIO_SLEWCTL_HSREN10_Pos (10) /*!< GPIO_T::SLEWCTL: HSREN10 Position */ +#define GPIO_SLEWCTL_HSREN10_Msk (0x1ul << GPIO_SLEWCTL_HSREN10_Pos) /*!< GPIO_T::SLEWCTL: HSREN10 Mask */ + +#define GPIO_SLEWCTL_HSREN11_Pos (11) /*!< GPIO_T::SLEWCTL: HSREN11 Position */ +#define GPIO_SLEWCTL_HSREN11_Msk (0x1ul << GPIO_SLEWCTL_HSREN11_Pos) /*!< GPIO_T::SLEWCTL: HSREN11 Mask */ + +#define GPIO_SLEWCTL_HSREN12_Pos (12) /*!< GPIO_T::SLEWCTL: HSREN12 Position */ +#define GPIO_SLEWCTL_HSREN12_Msk (0x1ul << GPIO_SLEWCTL_HSREN12_Pos) /*!< GPIO_T::SLEWCTL: HSREN12 Mask */ + +#define GPIO_SLEWCTL_HSREN13_Pos (13) /*!< GPIO_T::SLEWCTL: HSREN13 Position */ +#define GPIO_SLEWCTL_HSREN13_Msk (0x1ul << GPIO_SLEWCTL_HSREN13_Pos) /*!< GPIO_T::SLEWCTL: HSREN13 Mask */ + +#define GPIO_SLEWCTL_HSREN14_Pos (14) /*!< GPIO_T::SLEWCTL: HSREN14 Position */ +#define GPIO_SLEWCTL_HSREN14_Msk (0x1ul << GPIO_SLEWCTL_HSREN14_Pos) /*!< GPIO_T::SLEWCTL: HSREN14 Mask */ + +#define GPIO_SLEWCTL_HSREN15_Pos (15) /*!< GPIO_T::SLEWCTL: HSREN15 Position */ +#define GPIO_SLEWCTL_HSREN15_Msk (0x1ul << GPIO_SLEWCTL_HSREN15_Pos) /*!< GPIO_T::SLEWCTL: HSREN15 Mask */ + +#define GPIO_PUSEL_PUSEL0_Pos (0) /*!< GPIO_T::PUSEL: PUSEL0 Position */ +#define GPIO_PUSEL_PUSEL0_Msk (0x3ul << GPIO_PUSEL_PUSEL0_Pos) /*!< GPIO_T::PUSEL: PUSEL0 Mask */ + +#define GPIO_PUSEL_PUSEL1_Pos (2) /*!< GPIO_T::PUSEL: PUSEL1 Position */ +#define GPIO_PUSEL_PUSEL1_Msk (0x3ul << GPIO_PUSEL_PUSEL1_Pos) /*!< GPIO_T::PUSEL: PUSEL1 Mask */ + +#define GPIO_PUSEL_PUSEL2_Pos (4) /*!< GPIO_T::PUSEL: PUSEL2 Position */ +#define GPIO_PUSEL_PUSEL2_Msk (0x3ul << GPIO_PUSEL_PUSEL2_Pos) /*!< GPIO_T::PUSEL: PUSEL2 Mask */ + +#define GPIO_PUSEL_PUSEL3_Pos (6) /*!< GPIO_T::PUSEL: PUSEL3 Position */ +#define GPIO_PUSEL_PUSEL3_Msk (0x3ul << GPIO_PUSEL_PUSEL3_Pos) /*!< GPIO_T::PUSEL: PUSEL3 Mask */ + +#define GPIO_PUSEL_PUSEL4_Pos (8) /*!< GPIO_T::PUSEL: PUSEL4 Position */ +#define GPIO_PUSEL_PUSEL4_Msk (0x3ul << GPIO_PUSEL_PUSEL4_Pos) /*!< GPIO_T::PUSEL: PUSEL4 Mask */ + +#define GPIO_PUSEL_PUSEL5_Pos (10) /*!< GPIO_T::PUSEL: PUSEL5 Position */ +#define GPIO_PUSEL_PUSEL5_Msk (0x3ul << GPIO_PUSEL_PUSEL5_Pos) /*!< GPIO_T::PUSEL: PUSEL5 Mask */ + +#define GPIO_PUSEL_PUSEL6_Pos (12) /*!< GPIO_T::PUSEL: PUSEL6 Position */ +#define GPIO_PUSEL_PUSEL6_Msk (0x3ul << GPIO_PUSEL_PUSEL6_Pos) /*!< GPIO_T::PUSEL: PUSEL6 Mask */ + +#define GPIO_PUSEL_PUSEL7_Pos (14) /*!< GPIO_T::PUSEL: PUSEL7 Position */ +#define GPIO_PUSEL_PUSEL7_Msk (0x3ul << GPIO_PUSEL_PUSEL7_Pos) /*!< GPIO_T::PUSEL: PUSEL7 Mask */ + +#define GPIO_PUSEL_PUSEL8_Pos (16) /*!< GPIO_T::PUSEL: PUSEL8 Position */ +#define GPIO_PUSEL_PUSEL8_Msk (0x3ul << GPIO_PUSEL_PUSEL8_Pos) /*!< GPIO_T::PUSEL: PUSEL8 Mask */ + +#define GPIO_PUSEL_PUSEL9_Pos (18) /*!< GPIO_T::PUSEL: PUSEL9 Position */ +#define GPIO_PUSEL_PUSEL9_Msk (0x3ul << GPIO_PUSEL_PUSEL9_Pos) /*!< GPIO_T::PUSEL: PUSEL9 Mask */ + +#define GPIO_PUSEL_PUSEL10_Pos (20) /*!< GPIO_T::PUSEL: PUSEL10 Position */ +#define GPIO_PUSEL_PUSEL10_Msk (0x3ul << GPIO_PUSEL_PUSEL10_Pos) /*!< GPIO_T::PUSEL: PUSEL10 Mask */ + +#define GPIO_PUSEL_PUSEL11_Pos (22) /*!< GPIO_T::PUSEL: PUSEL11 Position */ +#define GPIO_PUSEL_PUSEL11_Msk (0x3ul << GPIO_PUSEL_PUSEL11_Pos) /*!< GPIO_T::PUSEL: PUSEL11 Mask */ + +#define GPIO_PUSEL_PUSEL12_Pos (24) /*!< GPIO_T::PUSEL: PUSEL12 Position */ +#define GPIO_PUSEL_PUSEL12_Msk (0x3ul << GPIO_PUSEL_PUSEL12_Pos) /*!< GPIO_T::PUSEL: PUSEL12 Mask */ + +#define GPIO_PUSEL_PUSEL13_Pos (26) /*!< GPIO_T::PUSEL: PUSEL13 Position */ +#define GPIO_PUSEL_PUSEL13_Msk (0x3ul << GPIO_PUSEL_PUSEL13_Pos) /*!< GPIO_T::PUSEL: PUSEL13 Mask */ + +#define GPIO_PUSEL_PUSEL14_Pos (28) /*!< GPIO_T::PUSEL: PUSEL14 Position */ +#define GPIO_PUSEL_PUSEL14_Msk (0x3ul << GPIO_PUSEL_PUSEL14_Pos) /*!< GPIO_T::PUSEL: PUSEL14 Mask */ + +#define GPIO_PUSEL_PUSEL15_Pos (30) /*!< GPIO_T::PUSEL: PUSEL15 Position */ +#define GPIO_PUSEL_PUSEL15_Msk (0x3ul << GPIO_PUSEL_PUSEL15_Pos) /*!< GPIO_T::PUSEL: PUSEL15 Mask */ + +#define GPIO_DBCTL_DBCLKSEL_Pos (0) /*!< GPIO_T::DBCTL: DBCLKSEL Position */ +#define GPIO_DBCTL_DBCLKSEL_Msk (0xful << GPIO_DBCTL_DBCLKSEL_Pos) /*!< GPIO_T::DBCTL: DBCLKSEL Mask */ + +#define GPIO_DBCTL_DBCLKSRC_Pos (4) /*!< GPIO_T::DBCTL: DBCLKSRC Position */ +#define GPIO_DBCTL_DBCLKSRC_Msk (0x1ul << GPIO_DBCTL_DBCLKSRC_Pos) /*!< GPIO_T::DBCTL: DBCLKSRC Mask */ + +#define GPIO_DBCTL_ICLKON_Pos (5) /*!< GPIO_T::DBCTL: ICLKON Position */ +#define GPIO_DBCTL_ICLKON_Msk (0x1ul << GPIO_DBCTL_ICLKON_Pos) /*!< GPIO_T::DBCTL: ICLKON Mask */ + + +/**@}*/ /* GPIO_CONST */ +/**@}*/ /* end of GPIO register group */ +/**@}*/ /* end of REGISTER group */ + + +#endif /* __GPIO_REG_H__ */ diff --git a/Ubiquitous/XiZi/board/nuvoton-m2354/third_party_driver/include/Regs/hdiv_reg.h b/Ubiquitous/XiZi/board/nuvoton-m2354/third_party_driver/include/Regs/hdiv_reg.h new file mode 100644 index 0000000..3ed7696 --- /dev/null +++ b/Ubiquitous/XiZi/board/nuvoton-m2354/third_party_driver/include/Regs/hdiv_reg.h @@ -0,0 +1,114 @@ +/**************************************************************************//** + * @file hdiv_reg.h + * @version V1.00 + * @brief HDIV register definition header file + * + * @copyright SPDX-License-Identifier: Apache-2.0 + * @copyright Copyright (C) 2020 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ +#ifndef __HDIV_REG_H__ +#define __HDIV_REG_H__ + +/** @addtogroup REGISTER Control Register + + @{ + +*/ + +/*---------------------- Hardware Divider --------------------------------*/ +/** + @addtogroup HDIV Hardware Divider(HDIV) + Memory Mapped Structure for HDIV Controller + @{ +*/ + +typedef struct +{ + + + /** + * @var HDIV_T::DIVIDEND + * Offset: 0x00 Dividend Source Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |DIVIDEND |Dividend Source + * | | |This register is given the dividend of divider before calculation starting. + * @var HDIV_T::DIVISOR + * Offset: 0x04 Divisor Source Resister + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |DIVISOR |Divisor Source + * | | |This register is given the divisor of divider before calculation starts. + * | | |Note: When this register is written, hardware divider will start calculate. + * @var HDIV_T::DIVQUO + * Offset: 0x08 Quotient Result Resister + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |QUOTIENT |Quotient Result + * | | |This register holds the quotient result of divider after calculation complete. + * @var HDIV_T::DIVREM + * Offset: 0x0C Remainder Result Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |REMAINDER |Remainder Result + * | | |The remainder of hardware divider is 16-bit sign integer (REMAINDER[15:0]), which holds the remainder result of divider after calculation complete. + * | | |The remainder of hardware divider with sign extension (REMAINDER[31:16]) to 32-bit integer. + * | | |This register holds the remainder result of divider after calculation complete. + * @var HDIV_T::DIVSTS + * Offset: 0x10 Divider Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |FINISH |Division Finish Flag + * | | |0 = Under Calculation. + * | | |1 = Calculation finished. + * | | |The flag will become low when the divider is in calculation. + * | | |The flag will go back to high once the calculation finished. + * |[1] |DIV0 |Divisor Zero Warning + * | | |0 = The divisor is not 0. + * | | |1 = The divisor is 0. + * | | |Note: The DIV0 flag is used to indicate divide-by-zero situation and updated whenever DIVISOR is written + * | | |This register is read only. + */ + __IO uint32_t DIVIDEND; /*!< [0x0000] Dividend Source Register */ + __IO uint32_t DIVISOR; /*!< [0x0004] Divisor Source Resister */ + __IO uint32_t DIVQUO; /*!< [0x0008] Quotient Result Resister */ + __IO uint32_t DIVREM; /*!< [0x000c] Remainder Result Register */ + __I uint32_t DIVSTS; /*!< [0x0010] Divider Status Register */ + +} HDIV_T; + +/** + @addtogroup HDIV_CONST HDIV Bit Field Definition + Constant Definitions for HDIV Controller + @{ +*/ + +#define HDIV_DIVIDEND_DIVIDEND_Pos (0) /*!< HDIV_T::DIVIDEND: DIVIDEND Position */ +#define HDIV_DIVIDEND_DIVIDEND_Msk (0xfffffffful << HDIV_DIVIDEND_DIVIDEND_Pos) /*!< HDIV_T::DIVIDEND: DIVIDEND Mask */ + +#define HDIV_DIVISOR_DIVISOR_Pos (0) /*!< HDIV_T::DIVISOR: DIVISOR Position */ +#define HDIV_DIVISOR_DIVISOR_Msk (0xfffful << HDIV_DIVISOR_DIVISOR_Pos) /*!< HDIV_T::DIVISOR: DIVISOR Mask */ + +#define HDIV_DIVQUO_QUOTIENT_Pos (0) /*!< HDIV_T::DIVQUO: QUOTIENT Position */ +#define HDIV_DIVQUO_QUOTIENT_Msk (0xfffffffful << HDIV_DIVQUO_QUOTIENT_Pos) /*!< HDIV_T::DIVQUO: QUOTIENT Mask */ + +#define HDIV_DIVREM_REMAINDER_Pos (0) /*!< HDIV_T::DIVREM: REMAINDER Position */ +#define HDIV_DIVREM_REMAINDER_Msk (0xfffffffful << HDIV_DIVREM_REMAINDER_Pos) /*!< HDIV_T::DIVREM: REMAINDER Mask */ + +#define HDIV_DIVSTS_FINISH_Pos (0) /*!< HDIV_T::DIVSTS: FINISH Position */ +#define HDIV_DIVSTS_FINISH_Msk (0x1ul << HDIV_DIVSTS_FINISH_Pos) /*!< HDIV_T::DIVSTS: FINISH Mask */ + +#define HDIV_DIVSTS_DIV0_Pos (1) /*!< HDIV_T::DIVSTS: DIV0 Position */ +#define HDIV_DIVSTS_DIV0_Msk (0x1ul << HDIV_DIVSTS_DIV0_Pos) /*!< HDIV_T::DIVSTS: DIV0 Mask */ + +/**@}*/ /* HDIV_CONST */ +/**@}*/ /* end of HDIV register group */ +/**@}*/ /* end of REGISTER group */ + + +#endif /* __HDIV_REG_H__ */ diff --git a/Ubiquitous/XiZi/board/nuvoton-m2354/third_party_driver/include/Regs/i2c_reg.h b/Ubiquitous/XiZi/board/nuvoton-m2354/third_party_driver/include/Regs/i2c_reg.h new file mode 100644 index 0000000..6435a0e --- /dev/null +++ b/Ubiquitous/XiZi/board/nuvoton-m2354/third_party_driver/include/Regs/i2c_reg.h @@ -0,0 +1,717 @@ +/**************************************************************************//** + * @file i2c_reg.h + * @version V1.00 + * @brief I2C register definition header file + * + * @copyright SPDX-License-Identifier: Apache-2.0 + * @copyright Copyright (C) 2020 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ +#ifndef __I2C_REG_H__ +#define __I2C_REG_H__ + +/** @addtogroup REGISTER Control Register + + @{ + +*/ + +/*---------------------- Inter-IC Bus Controller -------------------------*/ +/** + @addtogroup I2C Inter-IC Bus Controller(I2C) + Memory Mapped Structure for I2C Controller + @{ +*/ + +typedef struct +{ + + + /** + * @var I2C_T::CTL0 + * Offset: 0x00 I2C Control Register 0 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[2] |AA |Assert Acknowledge Control + * | | |When AA =1 prior to address or data is received, an acknowledged (low level to SDA) will be returned during the acknowledge clock pulse on the SCL line when 1.) A slave is acknowledging the address sent from master, 2.) The receiver devices are acknowledging the data sent by transmitter + * | | |When AA=0 prior to address or data received, a Not acknowledged (high level to SDA) will be returned during the acknowledge clock pulse on the SCL line + * |[3] |SI |I2C Interrupt Flag + * | | |When a new I2C state is present in the I2C_STATUS register, the SI flag is set by hardware + * | | |If bit INTEN (I2C_CTL [7]) is set, the I2C interrupt is requested + * | | |SI must be cleared by software + * | | |Clear SI by writing 1 to this bit. + * | | |For ACKMEN is set in slave read mode, the SI flag is set in 8th clock period for user to confirm the acknowledge bit and 9th clock period for user to read the data in the data buffer. + * |[4] |STO |I2C STOP Control + * | | |In Master mode, setting STO to transmit a STOP condition to bus then I2C controller will check the bus condition if a STOP condition is detected + * | | |This bit will be cleared by hardware automatically. + * |[5] |STA |I2C START Control + * | | |Setting STA to logic 1 to enter Master mode, the I2C hardware sends a START or repeat START condition to bus when the bus is free. + * |[6] |I2CEN |I2C Controller Enable Bit + * | | |Set to enable I2C serial function controller + * | | |When I2CEN=1 the I2C serial function enable + * | | |The multi-function pin function must set to SDA, and SCL of I2C function first. + * | | |0 = I2C controller Disabled. + * | | |1 = I2C controller Enabled. + * |[7] |INTEN |Enable Interrupt + * | | |0 = I2C interrupt Disabled. + * | | |1 = I2C interrupt Enabled. + * @var I2C_T::ADDR0 + * Offset: 0x04 I2C Slave Address Register0 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |GC |General Call Function + * | | |0 = General Call Function Disabled. + * | | |1 = General Call Function Enabled. + * |[10:1] |ADDR |I2C Address + * | | |The content of this register is irrelevant when I2C is in Master mode + * | | |In the slave mode, the seven most significant bits must be loaded with the chip's own address + * | | |The I2C hardware will react if either of the address is matched. + * @var I2C_T::DAT + * Offset: 0x08 I2C Data Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[7:0] |DAT |I2C Data + * | | |Bit [7:0] is located with the 8-bit transferred/received data of I2C serial port. + * @var I2C_T::STATUS0 + * Offset: 0x0C I2C Status Register 0 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[7:0] |STATUS |I2C Status + * | | |The three least significant bits are always 0 + * | | |The five most significant bits contain the status code + * | | |There are 28 possible status codes + * | | |When the content of I2C_STATUS0 is F8H, no serial interrupt is requested + * | | |Others I2C_STATUS0 values correspond to defined I2C states + * | | |When each of these states is entered, a status interrupt is requested (SI = 1) + * | | |A valid status code is present in I2C_STATUS0 one cycle after SI is set by hardware and is still present one cycle after SI has been reset by software + * | | |In addition, states 00H stands for a Bus Error + * | | |A Bus Error occurs when a START or STOP condition is present at an illegal position in the formation frame + * | | |Example of illegal position are during the serial transfer of an address byte, a data byte or an acknowledge bit. + * @var I2C_T::CLKDIV + * Offset: 0x10 I2C Clock Divided Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[9:0] |DIVIDER |I2C Clock Divided + * | | |Indicates the I2C clock rate: Data Baud Rate of I2C = (system clock) / (4x (I2C_CLKDIV+1)). + * | | |Note: The minimum value of I2C_CLKDIV is 4. + * @var I2C_T::TOCTL + * Offset: 0x14 I2C Time-out Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |TOIF |Time-out Flag + * | | |This bit is set by hardware when I2C time-out happened and it can interrupt CPU if I2C interrupt enable bit (INTEN) is set to 1. + * | | |Note: Software can write 1 to clear this bit. + * |[1] |TOCDIV4 |Time-out Counter Input Clock Divided by 4 + * | | |When Enabled, The time-out period is extend 4 times. + * | | |0 = Time-out period is extend 4 times Disabled. + * | | |1 = Time-out period is extend 4 times Enabled. + * |[2] |TOCEN |Time-out Counter Enable Bit + * | | |When Enabled, the 14-bit time-out counter will start counting when SI is clear + * | | |Setting flag SI to u20181' will reset counter and re-start up counting after SI is cleared. + * | | |0 = Time-out counter Disabled. + * | | |1 = Time-out counter Enabled. + * @var I2C_T::ADDR1 + * Offset: 0x18 I2C Slave Address Register1 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |GC |General Call Function + * | | |0 = General Call Function Disabled. + * | | |1 = General Call Function Enabled. + * |[10:1] |ADDR |I2C Address + * | | |The content of this register is irrelevant when I2C is in Master mode + * | | |In the slave mode, the seven most significant bits must be loaded with the chip's own address + * | | |The I2C hardware will react if either of the address is matched. + * @var I2C_T::ADDR2 + * Offset: 0x1C I2C Slave Address Register2 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |GC |General Call Function + * | | |0 = General Call Function Disabled. + * | | |1 = General Call Function Enabled. + * |[10:1] |ADDR |I2C Address + * | | |The content of this register is irrelevant when I2C is in Master mode + * | | |In the slave mode, the seven most significant bits must be loaded with the chip's own address + * | | |The I2C hardware will react if either of the address is matched. + * @var I2C_T::ADDR3 + * Offset: 0x20 I2C Slave Address Register3 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |GC |General Call Function + * | | |0 = General Call Function Disabled. + * | | |1 = General Call Function Enabled. + * |[10:1] |ADDR |I2C Address + * | | |The content of this register is irrelevant when I2C is in Master mode + * | | |In the slave mode, the seven most significant bits must be loaded with the chip's own address + * | | |The I2C hardware will react if either of the address is matched. + * @var I2C_T::ADDRMSK0 + * Offset: 0x24 I2C Slave Address Mask Register0 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[10:1] |ADDRMSK |I2C Address Mask + * | | |0 = Mask Disabled (the received corresponding register bit should be exact the same as address register.). + * | | |1 = Mask Enabled (the received corresponding address bit is don't care.). + * | | |I2C bus controllers support multiple address recognition with four address mask register + * | | |When the bit in the address mask register is set to one, it means the received corresponding address bit is don't-care + * | | |If the bit is set to zero, that means the received corresponding register bit should be exact the same as address register. + * | | |Note: The wake-up function can not use address mask. + * @var I2C_T::ADDRMSK1 + * Offset: 0x28 I2C Slave Address Mask Register1 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[10:1] |ADDRMSK |I2C Address Mask + * | | |0 = Mask Disabled (the received corresponding register bit should be exact the same as address register.). + * | | |1 = Mask Enabled (the received corresponding address bit is don't care.). + * | | |I2C bus controllers support multiple address recognition with four address mask register + * | | |When the bit in the address mask register is set to one, it means the received corresponding address bit is don't-care + * | | |If the bit is set to zero, that means the received corresponding register bit should be exact the same as address register. + * | | |Note: The wake-up function can not use address mask. + * @var I2C_T::ADDRMSK2 + * Offset: 0x2C I2C Slave Address Mask Register2 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[10:1] |ADDRMSK |I2C Address Mask + * | | |0 = Mask Disabled (the received corresponding register bit should be exact the same as address register.). + * | | |1 = Mask Enabled (the received corresponding address bit is don't care.). + * | | |I2C bus controllers support multiple address recognition with four address mask register + * | | |When the bit in the address mask register is set to one, it means the received corresponding address bit is don't-care + * | | |If the bit is set to zero, that means the received corresponding register bit should be exact the same as address register. + * | | |Note: The wake-up function can not use address mask. + * @var I2C_T::ADDRMSK3 + * Offset: 0x30 I2C Slave Address Mask Register3 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[10:1] |ADDRMSK |I2C Address Mask + * | | |0 = Mask Disabled (the received corresponding register bit should be exact the same as address register.). + * | | |1 = Mask Enabled (the received corresponding address bit is don't care.). + * | | |I2C bus controllers support multiple address recognition with four address mask register + * | | |When the bit in the address mask register is set to one, it means the received corresponding address bit is don't-care + * | | |If the bit is set to zero, that means the received corresponding register bit should be exact the same as address register. + * | | |Note: The wake-up function can not use address mask. + * @var I2C_T::WKCTL + * Offset: 0x3C I2C Wake-up Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |WKEN |I2C Wake-up Enable Bit + * | | |0 = I2C wake-up function Disabled. + * | | |1= I2C wake-up function Enabled. + * |[7] |NHDBUSEN |I2C No Hold BUS Enable Bit + * | | |0 = I2C don't hold bus after wake-up disable. + * | | |1= I2C don't hold bus after wake-up enable. + * | | |Note: I2C controller could response when WKIF event is not clear, it may cause error data transmitted or received + * | | |If data transmitted or received when WKIF event is not clear, user must reset I2C controller and execute the original operation again. + * @var I2C_T::WKSTS + * Offset: 0x40 I2C Wake-up Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |WKIF |I2C Wake-up Flag + * | | |When chip is woken up from Power-down mode by I2C, this bit is set to 1 + * | | |Software can write 1 to clear this bit. + * |[1] |WKAKDONE |Wakeup Address Frame Acknowledge Bit Done + * | | |0 = The ACK bit cycle of address match frame isn't done. + * | | |1 = The ACK bit cycle of address match frame is done in power-down. + * | | |Note: This bit can't release WKIF. Software can write 1 to clear this bit. + * |[2] |WRSTSWK |Read/Write Status Bit in Address Wakeup Frame + * | | |0 = Write command be record on the address match wakeup frame. + * | | |1 = Read command be record on the address match wakeup frame. + * | | |Note: This bit will be cleared when software can write 1 to WKAKDONE bit. + * @var I2C_T::CTL1 + * Offset: 0x44 I2C Control Register 1 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |TXPDMAEN |PDMA Transmit Channel Available + * | | |0 = Transmit PDMA function disable. + * | | |1 = Transmit PDMA function enable. + * |[1] |RXPDMAEN |PDMA Receive Channel Available + * | | |0 = Receive PDMA function disable. + * | | |1 = Receive PDMA function enable. + * |[2] |PDMARST |PDMA Reset + * | | |0 = No effect. + * | | |1 = Reset the I2C request to PDMA. This bit will be cleared to 0 automatically. + * |[8] |PDMASTR |PDMA Stretch Bit + * | | |0 = I2C send STOP automatically after PDMA transfer done. (only master TX) + * | | |1 = I2C SCL bus is stretched by hardware after PDMA transfer done if the SI is not cleared + * | | |(only master TX) + * |[9] |ADDR10EN |Address 10-bit Function Enable + * | | |0 = Address match 10-bit function is disabled. + * | | |1 = Address match 10-bit function is enabled. + * @var I2C_T::STATUS1 + * Offset: 0x48 I2C Status Register 1 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |ADMAT0 |I2C Address 0 Match Status Register + * | | |When address 0 is matched, hardware will inform which address used + * | | |This bit will set to 1, and software can write 1 to clear this bit. + * |[1] |ADMAT1 |I2C Address 1 Match Status Register + * | | |When address 1 is matched, hardware will inform which address used + * | | |This bit will set to 1, and software can write 1 to clear this bit. + * |[2] |ADMAT2 |I2C Address 2 Match Status Register + * | | |When address 2 is matched, hardware will inform which address used + * | | |This bit will set to 1, and software can write 1 to clear this bit. + * |[3] |ADMAT3 |I2C Address 3 Match Status Register + * | | |When address 3 is matched, hardware will inform which address used + * | | |This bit will set to 1, and software can write 1 to clear this bit. + * |[8] |ONBUSY |On Bus Busy + * | | |Indicates that a communication is in progress on the bus + * | | |It is set by hardware when a START condition is detected + * | | |It is cleared by hardware when a STOP condition is detected. + * | | |0 = The bus is IDLE (both SCLK and SDA High). + * | | |1 = The bus is busy. + * | | |Note:This bit is read only. + * @var I2C_T::TMCTL + * Offset: 0x4C I2C Timing Configure Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[8:0] |STCTL |Setup Time Configure Control Register + * | | |This field is used to generate a delay timing between SDA falling edge and SCL rising edge in transmission mode. + * | | |The delay setup time is numbers of peripheral clock = STCTL x PCLK. + * | | |Note: Setup time setting should not make SCL output less than three PCLKs. + * |[24:16] |HTCTL |Hold Time Configure Control Register + * | | |This field is used to generate the delay timing between SCL falling edge and SDA rising edge in transmission mode. + * | | |The delay hold time is numbers of peripheral clock = HTCTL x PCLK. + * @var I2C_T::BUSCTL + * Offset: 0x50 I2C Bus Management Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |ACKMEN |Acknowledge Control by Manual + * | | |In order to allow ACK control in slave reception including the command and data, slave byte control mode must be enabled by setting the ACKMEN bit. + * | | |0 = Slave byte control Disabled. + * | | |1 = Slave byte control Enabled + * | | |The 9th bit can response the ACK or NACK according the received data by user + * | | |When the byte is received, stretching the SCLK signal low between the 8th and 9th SCLK pulse. + * | | |Note: If the BMDEN =1 and this bit is enabled, the information of I2C_STATUS will be fixed as 0xF0 in slave receive condition. + * |[1] |PECEN |Packet Error Checking Calculation Enable Bit + * | | |0 = Packet Error Checking Calculation Disabled. + * | | |1 = Packet Error Checking Calculation Enabled. + * | | |Note: When I2C enter power down mode, the bit should be enabled after wake-up if needed PEC calculation. + * |[2] |BMDEN |Bus Management Device Default Address Enable Bit + * | | |0 = Device default address Disable + * | | |When the address 0'b1100001x coming and the both of BMDEN and ACKMEN are enabled, the device responses NACKed + * | | |1 = Device default address Enabled + * | | |When the address 0'b1100001x coming and the both of BMDEN and ACKMEN are enabled, the device responses ACKed. + * |[3] |BMHEN |Bus Management Host Enable Bit + * | | |0 = Host function Disabled. + * | | |1 = Host function Enabled. + * |[4] |ALERTEN |Bus Management Alert Enable Bit + * | | |Device Mode (BMHEN =0). + * | | |0 = Release the BM_ALERT pin high and Alert Response Header disabled: 0001100x followed by NACK if both of BMDEN and ACKMEN are enabled. + * | | |1 = Drive BM_ALERT pin low and Alert Response Address Header enables: 0001100x followed by ACK if both of BMDEN and ACKMEN are enabled. + * | | |Host Mode (BMHEN =1). + * | | |0 = BM_ALERT pin not supported. + * | | |1 = BM_ALERT pin supported. + * |[5] |SCTLOSTS |Suspend/Control Data Output Status + * | | |0 = The output of SUSCON pin is low. + * | | |1 = The output of SUSCON pin is high. + * |[6] |SCTLOEN |Suspend or Control Pin Output Enable Bit + * | | |0 = The SUSCON pin in input. + * | | |1 = The output enable is active on the SUSCON pin. + * |[7] |BUSEN |BUS Enable Bit + * | | |0 = The system management function is Disabled. + * | | |1 = The system management function is Enable. + * | | |Note: When the bit is enabled, the internal 14-bit counter is used to calculate the time out event of clock low condition. + * |[8] |PECTXEN |Packet Error Checking Byte Transmission/Reception + * | | |0 = No PEC transfer. + * | | |1 = PEC transmission is requested. + * | | |Note: 1.This bit has no effect in slave mode when ACKMEN =0. + * |[9] |TIDLE |Timer Check in Idle State + * | | |The BUSTOUT is used to calculate the time-out of clock low in bus active and the idle period in bus Idle + * | | |This bit is used to define which condition is enabled. + * | | |0 = The BUSTOUT is used to calculate the clock low period in bus active. + * | | |1 = The BUSTOUT is used to calculate the IDLE period in bus Idle. + * | | |Note: The BUSY (I2C_BUSSTS[0]) indicate the current bus state. + * |[10] |PECCLR |PEC Clear at Repeat Start + * | | |The calculation of PEC starts when PECEN is set to 1 and it is clear when the STA or STO bit is detected + * | | |This PECCLR bit is used to enable the condition of REPEAT START can clear the PEC calculation. + * | | |0 = The PEC calculation is cleared by Repeat Start function is Disabled. + * | | |1 = The PEC calculation is cleared by Repeat Start function is Enabled. + * |[11] |ACKM9SI |Acknowledge Manual Enable Extra SI Interrupt + * | | |0 = There is no SI interrupt in the 9th clock cycle when the BUSEN =1 and ACKMEN =1. + * | | |1 = There is SI interrupt in the 9th clock cycle when the BUSEN =1 and ACKMEN =1. + * |[12] |BCDIEN |Packet Error Checking Byte Count Done Interrupt Enable Bit + * | | |0 = Indicates the byte count done interrupt is Disabled. + * | | |1 = Indicates the byte count done interrupt is Enabled. + * | | |Note: This bit is used in PECEN =1. + * |[13] |PECDIEN |Packet Error Checking Byte Transfer Done Interrupt Enable Bit + * | | |0 = Indicates the PEC transfer done interrupt is Disabled. + * | | |1 = Indicates the PEC transfer done interrupt is Enabled. + * | | |Note: This bit is used in PECEN =1. + * @var I2C_T::BUSTCTL + * Offset: 0x54 I2C Bus Management Timer Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |BUSTOEN |Bus Time Out Enable Bit + * | | |0 = Indicates the bus clock low time-out detection is Disabled. + * | | |1 = Indicates the bus clock low time-out detection is Enabled (bus clock is low for more than Time-out (in BIDLE=0) or high more than Time-out(in BIDLE =1) + * |[1] |CLKTOEN |Cumulative Clock Low Time Out Enable Bit + * | | |0 = Indicates the cumulative clock low time-out detection is Disabled. + * | | |1 = Indicates the cumulative clock low time-out detection is Enabled. + * | | |For Master, it calculates the period from START to ACK + * | | |For Slave, it calculates the period from START to STOP + * |[2] |BUSTOIEN |Time-out Interrupt Enable Bit + * | | |BUSY =1. + * | | |0 = Indicates the SCLK low time-out interrupt is Disabled. + * | | |1 = Indicates the SCLK low time-out interrupt is Enabled. + * | | |BUSY =0. + * | | |0 = Indicates the bus IDLE time-out interrupt is Disabled. + * | | |1 = Indicates the bus IDLE time-out interrupt is Enabled. + * |[3] |CLKTOIEN |Extended Clock Time Out Interrupt Enable Bit + * | | |0 = Indicates the clock time out interrupt is Disabled. + * | | |1 = Indicates the clock time out interrupt is Enabled. + * |[4] |TORSTEN |Time Out Reset Enable Bit + * | | |0 = Indicates the I2C state machine reset is Disable. + * | | |1 = Indicates the I2C state machine reset is Enable. (The clock and data bus will be released to high) + * @var I2C_T::BUSSTS + * Offset: 0x58 I2C Bus Management Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |BUSY |Bus Busy + * | | |Indicates that a communication is in progress on the bus + * | | |It is set by hardware when a START condition is detected + * | | |It is cleared by hardware when a STOP condition is detected + * | | |0 = The bus is IDLE (both SCLK and SDA High). + * | | |1 = The bus is busy. + * |[1] |BCDONE |Byte Count Transmission/Receive Done + * | | |0 = Indicates the byte count transmission/ receive is not finished when the PECEN is set. + * | | |1 = Indicates the byte count transmission/ receive is finished when the PECEN is set. + * | | |Note: Software can write 1 to clear this bit. + * |[2] |PECERR |PEC Error in Reception + * | | |0 = Indicates the PEC value equal the received PEC data packet. + * | | |1 = Indicates the PEC value doesn't match the receive PEC data packet. + * | | |Note: Software can write 1 to clear this bit. + * |[3] |ALERT |SMBus Alert Status + * | | |Device Mode (BMHEN =0). + * | | |0 = Indicates SMBALERT pin state is low. + * | | |1 = Indicates SMBALERT pin state is high. + * | | |Host Mode (BMHEN =1). + * | | |0 = No SMBALERT event. + * | | |1 = Indicates there is SMBALERT event (falling edge) is detected in SMALERT pin when the BMHEN = 1 (SMBus host configuration) and the ALERTEN = 1. + * | | |Note: 1 + * | | |The SMBALERT pin is an open-drain pin, the pull-high resistor is must in the system + * | | |2 + * | | |Software can write 1 to clear this bit. + * |[4] |SCTLDIN |Bus Suspend or Control Signal Input Status + * | | |0 = The input status of SUSCON pin is 0. + * | | |1 = The input status of SUSCON pin is 1. + * |[5] |BUSTO |Bus Time-out Status + * | | |0 = Indicates that there is no any time-out or external clock time-out. + * | | |1 = Indicates that a time-out or external clock time-out occurred. + * | | |In bus busy, the bit indicates the total clock low time-out event occurred otherwise, it indicates the bus idle time-out event occurred. + * | | |Note: Software can write 1 to clear this bit. + * |[6] |CLKTO |Clock Low Accumulate Time-out Status + * | | |0 = Indicates that the cumulative clock low is no any time-out. + * | | |1 = Indicates that the cumulative clock low time-out occurred. + * | | |Note: Software can write 1 to clear this bit. + * |[7] |PECDONE |PEC Byte Transmission/Receive Done + * | | |0 = Indicates the PEC transmission/ receive is not finished when the PECEN is set. + * | | |1 = Indicates the PEC transmission/ receive is finished when the PECEN is set. + * | | |Note: Software can write 1 to clear this bit. + * @var I2C_T::PKTSIZE + * Offset: 0x5C I2C Packet Error Checking Byte Number Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[8:0] |PLDSIZE |Transfer Byte Number + * | | |The transmission or receive byte number in one transaction when the PECEN is set + * | | |The maximum transaction or receive byte is 256 Bytes. + * | | |Notice: The byte number counting includes address, command code, and data frame. + * @var I2C_T::PKTCRC + * Offset: 0x60 I2C Packet Error Checking Byte Value Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[7:0] |PECCRC |Packet Error Checking Byte Value + * | | |This byte indicates the packet error checking content after transmission or receive byte count by using the C(x) = X8 + X2 + X + 1 + * | | |It is read only. + * @var I2C_T::BUSTOUT + * Offset: 0x64 I2C Bus Management Timer Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[7:0] |BUSTO |Bus Management Time-out Value + * | | |Indicate the bus time-out value in bus is IDLE or SCLK low. + * | | |Note: If the user wants to revise the value of BUSTOUT, the TORSTEN (I2C_BUSTCTL[4]) bit shall be set to 1 and clear to 0 first in the BUSEN(I2C_BUSCTL[7]) is set. + * @var I2C_T::CLKTOUT + * Offset: 0x68 I2C Bus Management Clock Low Timer Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[7:0] |CLKTO |Bus Clock Low Timer + * | | |The field is used to configure the cumulative clock extension time-out. + * | | |Note: If the user wants to revise the value of CLKLTOUT, the TORSTEN bit shall be set to 1 and clear to 0 first in the BUSEN is set. + */ + __IO uint32_t CTL0; /*!< [0x0000] I2C Control Register 0 */ + __IO uint32_t ADDR0; /*!< [0x0004] I2C Slave Address Register0 */ + __IO uint32_t DAT; /*!< [0x0008] I2C Data Register */ + __I uint32_t STATUS0; /*!< [0x000c] I2C Status Register 0 */ + __IO uint32_t CLKDIV; /*!< [0x0010] I2C Clock Divided Register */ + __IO uint32_t TOCTL; /*!< [0x0014] I2C Time-out Control Register */ + __IO uint32_t ADDR1; /*!< [0x0018] I2C Slave Address Register1 */ + __IO uint32_t ADDR2; /*!< [0x001c] I2C Slave Address Register2 */ + __IO uint32_t ADDR3; /*!< [0x0020] I2C Slave Address Register3 */ + __IO uint32_t ADDRMSK0; /*!< [0x0024] I2C Slave Address Mask Register0 */ + __IO uint32_t ADDRMSK1; /*!< [0x0028] I2C Slave Address Mask Register1 */ + __IO uint32_t ADDRMSK2; /*!< [0x002c] I2C Slave Address Mask Register2 */ + __IO uint32_t ADDRMSK3; /*!< [0x0030] I2C Slave Address Mask Register3 */ + __I uint32_t RESERVE0[2]; + __IO uint32_t WKCTL; /*!< [0x003c] I2C Wake-up Control Register */ + __IO uint32_t WKSTS; /*!< [0x0040] I2C Wake-up Status Register */ + __IO uint32_t CTL1; /*!< [0x0044] I2C Control Register 1 */ + __IO uint32_t STATUS1; /*!< [0x0048] I2C Status Register 1 */ + __IO uint32_t TMCTL; /*!< [0x004c] I2C Timing Configure Control Register */ + __IO uint32_t BUSCTL; /*!< [0x0050] I2C Bus Management Control Register */ + __IO uint32_t BUSTCTL; /*!< [0x0054] I2C Bus Management Timer Control Register */ + __IO uint32_t BUSSTS; /*!< [0x0058] I2C Bus Management Status Register */ + __IO uint32_t PKTSIZE; /*!< [0x005c] I2C Packet Error Checking Byte Number Register */ + __I uint32_t PKTCRC; /*!< [0x0060] I2C Packet Error Checking Byte Value Register */ + __IO uint32_t BUSTOUT; /*!< [0x0064] I2C Bus Management Timer Register */ + __IO uint32_t CLKTOUT; /*!< [0x0068] I2C Bus Management Clock Low Timer Register */ + +} I2C_T; + +/** + @addtogroup I2C_CONST I2C Bit Field Definition + Constant Definitions for I2C Controller + @{ +*/ + +#define I2C_CTL0_AA_Pos (2) /*!< I2C_T::CTL0: AA Position */ +#define I2C_CTL0_AA_Msk (0x1ul << I2C_CTL0_AA_Pos) /*!< I2C_T::CTL0: AA Mask */ + +#define I2C_CTL0_SI_Pos (3) /*!< I2C_T::CTL0: SI Position */ +#define I2C_CTL0_SI_Msk (0x1ul << I2C_CTL0_SI_Pos) /*!< I2C_T::CTL0: SI Mask */ + +#define I2C_CTL0_STO_Pos (4) /*!< I2C_T::CTL0: STO Position */ +#define I2C_CTL0_STO_Msk (0x1ul << I2C_CTL0_STO_Pos) /*!< I2C_T::CTL0: STO Mask */ + +#define I2C_CTL0_STA_Pos (5) /*!< I2C_T::CTL0: STA Position */ +#define I2C_CTL0_STA_Msk (0x1ul << I2C_CTL0_STA_Pos) /*!< I2C_T::CTL0: STA Mask */ + +#define I2C_CTL0_I2CEN_Pos (6) /*!< I2C_T::CTL0: I2CEN Position */ +#define I2C_CTL0_I2CEN_Msk (0x1ul << I2C_CTL0_I2CEN_Pos) /*!< I2C_T::CTL0: I2CEN Mask */ + +#define I2C_CTL0_INTEN_Pos (7) /*!< I2C_T::CTL0: INTEN Position */ +#define I2C_CTL0_INTEN_Msk (0x1ul << I2C_CTL0_INTEN_Pos) /*!< I2C_T::CTL0: INTEN Mask */ + +#define I2C_ADDR0_GC_Pos (0) /*!< I2C_T::ADDR0: GC Position */ +#define I2C_ADDR0_GC_Msk (0x1ul << I2C_ADDR0_GC_Pos) /*!< I2C_T::ADDR0: GC Mask */ + +#define I2C_ADDR0_ADDR_Pos (1) /*!< I2C_T::ADDR0: ADDR Position */ +#define I2C_ADDR0_ADDR_Msk (0x3fful << I2C_ADDR0_ADDR_Pos) /*!< I2C_T::ADDR0: ADDR Mask */ + +#define I2C_DAT_DAT_Pos (0) /*!< I2C_T::DAT: DAT Position */ +#define I2C_DAT_DAT_Msk (0xfful << I2C_DAT_DAT_Pos) /*!< I2C_T::DAT: DAT Mask */ + +#define I2C_STATUS0_STATUS_Pos (0) /*!< I2C_T::STATUS0: STATUS Position */ +#define I2C_STATUS0_STATUS_Msk (0xfful << I2C_STATUS0_STATUS_Pos) /*!< I2C_T::STATUS0: STATUS Mask */ + +#define I2C_CLKDIV_DIVIDER_Pos (0) /*!< I2C_T::CLKDIV: DIVIDER Position */ +#define I2C_CLKDIV_DIVIDER_Msk (0x3fful << I2C_CLKDIV_DIVIDER_Pos) /*!< I2C_T::CLKDIV: DIVIDER Mask */ + +#define I2C_TOCTL_TOIF_Pos (0) /*!< I2C_T::TOCTL: TOIF Position */ +#define I2C_TOCTL_TOIF_Msk (0x1ul << I2C_TOCTL_TOIF_Pos) /*!< I2C_T::TOCTL: TOIF Mask */ + +#define I2C_TOCTL_TOCDIV4_Pos (1) /*!< I2C_T::TOCTL: TOCDIV4 Position */ +#define I2C_TOCTL_TOCDIV4_Msk (0x1ul << I2C_TOCTL_TOCDIV4_Pos) /*!< I2C_T::TOCTL: TOCDIV4 Mask */ + +#define I2C_TOCTL_TOCEN_Pos (2) /*!< I2C_T::TOCTL: TOCEN Position */ +#define I2C_TOCTL_TOCEN_Msk (0x1ul << I2C_TOCTL_TOCEN_Pos) /*!< I2C_T::TOCTL: TOCEN Mask */ + +#define I2C_ADDR1_GC_Pos (0) /*!< I2C_T::ADDR1: GC Position */ +#define I2C_ADDR1_GC_Msk (0x1ul << I2C_ADDR1_GC_Pos) /*!< I2C_T::ADDR1: GC Mask */ + +#define I2C_ADDR1_ADDR_Pos (1) /*!< I2C_T::ADDR1: ADDR Position */ +#define I2C_ADDR1_ADDR_Msk (0x3fful << I2C_ADDR1_ADDR_Pos) /*!< I2C_T::ADDR1: ADDR Mask */ + +#define I2C_ADDR2_GC_Pos (0) /*!< I2C_T::ADDR2: GC Position */ +#define I2C_ADDR2_GC_Msk (0x1ul << I2C_ADDR2_GC_Pos) /*!< I2C_T::ADDR2: GC Mask */ + +#define I2C_ADDR2_ADDR_Pos (1) /*!< I2C_T::ADDR2: ADDR Position */ +#define I2C_ADDR2_ADDR_Msk (0x3fful << I2C_ADDR2_ADDR_Pos) /*!< I2C_T::ADDR2: ADDR Mask */ + +#define I2C_ADDR3_GC_Pos (0) /*!< I2C_T::ADDR3: GC Position */ +#define I2C_ADDR3_GC_Msk (0x1ul << I2C_ADDR3_GC_Pos) /*!< I2C_T::ADDR3: GC Mask */ + +#define I2C_ADDR3_ADDR_Pos (1) /*!< I2C_T::ADDR3: ADDR Position */ +#define I2C_ADDR3_ADDR_Msk (0x3fful << I2C_ADDR3_ADDR_Pos) /*!< I2C_T::ADDR3: ADDR Mask */ + +#define I2C_ADDRMSK0_ADDRMSK_Pos (1) /*!< I2C_T::ADDRMSK0: ADDRMSK Position */ +#define I2C_ADDRMSK0_ADDRMSK_Msk (0x3fful << I2C_ADDRMSK0_ADDRMSK_Pos) /*!< I2C_T::ADDRMSK0: ADDRMSK Mask */ + +#define I2C_ADDRMSK1_ADDRMSK_Pos (1) /*!< I2C_T::ADDRMSK1: ADDRMSK Position */ +#define I2C_ADDRMSK1_ADDRMSK_Msk (0x3fful << I2C_ADDRMSK1_ADDRMSK_Pos) /*!< I2C_T::ADDRMSK1: ADDRMSK Mask */ + +#define I2C_ADDRMSK2_ADDRMSK_Pos (1) /*!< I2C_T::ADDRMSK2: ADDRMSK Position */ +#define I2C_ADDRMSK2_ADDRMSK_Msk (0x3fful << I2C_ADDRMSK2_ADDRMSK_Pos) /*!< I2C_T::ADDRMSK2: ADDRMSK Mask */ + +#define I2C_ADDRMSK3_ADDRMSK_Pos (1) /*!< I2C_T::ADDRMSK3: ADDRMSK Position */ +#define I2C_ADDRMSK3_ADDRMSK_Msk (0x3fful << I2C_ADDRMSK3_ADDRMSK_Pos) /*!< I2C_T::ADDRMSK3: ADDRMSK Mask */ + +#define I2C_WKCTL_WKEN_Pos (0) /*!< I2C_T::WKCTL: WKEN Position */ +#define I2C_WKCTL_WKEN_Msk (0x1ul << I2C_WKCTL_WKEN_Pos) /*!< I2C_T::WKCTL: WKEN Mask */ + +#define I2C_WKCTL_NHDBUSEN_Pos (7) /*!< I2C_T::WKCTL: NHDBUSEN Position */ +#define I2C_WKCTL_NHDBUSEN_Msk (0x1ul << I2C_WKCTL_NHDBUSEN_Pos) /*!< I2C_T::WKCTL: NHDBUSEN Mask */ + +#define I2C_WKSTS_WKIF_Pos (0) /*!< I2C_T::WKSTS: WKIF Position */ +#define I2C_WKSTS_WKIF_Msk (0x1ul << I2C_WKSTS_WKIF_Pos) /*!< I2C_T::WKSTS: WKIF Mask */ + +#define I2C_WKSTS_WKAKDONE_Pos (1) /*!< I2C_T::WKSTS: WKAKDONE Position */ +#define I2C_WKSTS_WKAKDONE_Msk (0x1ul << I2C_WKSTS_WKAKDONE_Pos) /*!< I2C_T::WKSTS: WKAKDONE Mask */ + +#define I2C_WKSTS_WRSTSWK_Pos (2) /*!< I2C_T::WKSTS: WRSTSWK Position */ +#define I2C_WKSTS_WRSTSWK_Msk (0x1ul << I2C_WKSTS_WRSTSWK_Pos) /*!< I2C_T::WKSTS: WRSTSWK Mask */ + +#define I2C_CTL1_TXPDMAEN_Pos (0) /*!< I2C_T::CTL1: TXPDMAEN Position */ +#define I2C_CTL1_TXPDMAEN_Msk (0x1ul << I2C_CTL1_TXPDMAEN_Pos) /*!< I2C_T::CTL1: TXPDMAEN Mask */ + +#define I2C_CTL1_RXPDMAEN_Pos (1) /*!< I2C_T::CTL1: RXPDMAEN Position */ +#define I2C_CTL1_RXPDMAEN_Msk (0x1ul << I2C_CTL1_RXPDMAEN_Pos) /*!< I2C_T::CTL1: RXPDMAEN Mask */ + +#define I2C_CTL1_PDMARST_Pos (2) /*!< I2C_T::CTL1: PDMARST Position */ +#define I2C_CTL1_PDMARST_Msk (0x1ul << I2C_CTL1_PDMARST_Pos) /*!< I2C_T::CTL1: PDMARST Mask */ + +#define I2C_CTL1_PDMASTR_Pos (8) /*!< I2C_T::CTL1: PDMASTR Position */ +#define I2C_CTL1_PDMASTR_Msk (0x1ul << I2C_CTL1_PDMASTR_Pos) /*!< I2C_T::CTL1: PDMASTR Mask */ + +#define I2C_CTL1_ADDR10EN_Pos (9) /*!< I2C_T::CTL1: ADDR10EN Position */ +#define I2C_CTL1_ADDR10EN_Msk (0x1ul << I2C_CTL1_ADDR10EN_Pos) /*!< I2C_T::CTL1: ADDR10EN Mask */ + +#define I2C_STATUS1_ADMAT0_Pos (0) /*!< I2C_T::STATUS1: ADMAT0 Position */ +#define I2C_STATUS1_ADMAT0_Msk (0x1ul << I2C_STATUS1_ADMAT0_Pos) /*!< I2C_T::STATUS1: ADMAT0 Mask */ + +#define I2C_STATUS1_ADMAT1_Pos (1) /*!< I2C_T::STATUS1: ADMAT1 Position */ +#define I2C_STATUS1_ADMAT1_Msk (0x1ul << I2C_STATUS1_ADMAT1_Pos) /*!< I2C_T::STATUS1: ADMAT1 Mask */ + +#define I2C_STATUS1_ADMAT2_Pos (2) /*!< I2C_T::STATUS1: ADMAT2 Position */ +#define I2C_STATUS1_ADMAT2_Msk (0x1ul << I2C_STATUS1_ADMAT2_Pos) /*!< I2C_T::STATUS1: ADMAT2 Mask */ + +#define I2C_STATUS1_ADMAT3_Pos (3) /*!< I2C_T::STATUS1: ADMAT3 Position */ +#define I2C_STATUS1_ADMAT3_Msk (0x1ul << I2C_STATUS1_ADMAT3_Pos) /*!< I2C_T::STATUS1: ADMAT3 Mask */ + +#define I2C_STATUS1_ONBUSY_Pos (8) /*!< I2C_T::STATUS1: ONBUSY Position */ +#define I2C_STATUS1_ONBUSY_Msk (0x1ul << I2C_STATUS1_ONBUSY_Pos) /*!< I2C_T::STATUS1: ONBUSY Mask */ + +#define I2C_TMCTL_STCTL_Pos (0) /*!< I2C_T::TMCTL: STCTL Position */ +#define I2C_TMCTL_STCTL_Msk (0x1fful << I2C_TMCTL_STCTL_Pos) /*!< I2C_T::TMCTL: STCTL Mask */ + +#define I2C_TMCTL_HTCTL_Pos (16) /*!< I2C_T::TMCTL: HTCTL Position */ +#define I2C_TMCTL_HTCTL_Msk (0x1fful << I2C_TMCTL_HTCTL_Pos) /*!< I2C_T::TMCTL: HTCTL Mask */ + +#define I2C_BUSCTL_ACKMEN_Pos (0) /*!< I2C_T::BUSCTL: ACKMEN Position */ +#define I2C_BUSCTL_ACKMEN_Msk (0x1ul << I2C_BUSCTL_ACKMEN_Pos) /*!< I2C_T::BUSCTL: ACKMEN Mask */ + +#define I2C_BUSCTL_PECEN_Pos (1) /*!< I2C_T::BUSCTL: PECEN Position */ +#define I2C_BUSCTL_PECEN_Msk (0x1ul << I2C_BUSCTL_PECEN_Pos) /*!< I2C_T::BUSCTL: PECEN Mask */ + +#define I2C_BUSCTL_BMDEN_Pos (2) /*!< I2C_T::BUSCTL: BMDEN Position */ +#define I2C_BUSCTL_BMDEN_Msk (0x1ul << I2C_BUSCTL_BMDEN_Pos) /*!< I2C_T::BUSCTL: BMDEN Mask */ + +#define I2C_BUSCTL_BMHEN_Pos (3) /*!< I2C_T::BUSCTL: BMHEN Position */ +#define I2C_BUSCTL_BMHEN_Msk (0x1ul << I2C_BUSCTL_BMHEN_Pos) /*!< I2C_T::BUSCTL: BMHEN Mask */ + +#define I2C_BUSCTL_ALERTEN_Pos (4) /*!< I2C_T::BUSCTL: ALERTEN Position */ +#define I2C_BUSCTL_ALERTEN_Msk (0x1ul << I2C_BUSCTL_ALERTEN_Pos) /*!< I2C_T::BUSCTL: ALERTEN Mask */ + +#define I2C_BUSCTL_SCTLOSTS_Pos (5) /*!< I2C_T::BUSCTL: SCTLOSTS Position */ +#define I2C_BUSCTL_SCTLOSTS_Msk (0x1ul << I2C_BUSCTL_SCTLOSTS_Pos) /*!< I2C_T::BUSCTL: SCTLOSTS Mask */ + +#define I2C_BUSCTL_SCTLOEN_Pos (6) /*!< I2C_T::BUSCTL: SCTLOEN Position */ +#define I2C_BUSCTL_SCTLOEN_Msk (0x1ul << I2C_BUSCTL_SCTLOEN_Pos) /*!< I2C_T::BUSCTL: SCTLOEN Mask */ + +#define I2C_BUSCTL_BUSEN_Pos (7) /*!< I2C_T::BUSCTL: BUSEN Position */ +#define I2C_BUSCTL_BUSEN_Msk (0x1ul << I2C_BUSCTL_BUSEN_Pos) /*!< I2C_T::BUSCTL: BUSEN Mask */ + +#define I2C_BUSCTL_PECTXEN_Pos (8) /*!< I2C_T::BUSCTL: PECTXEN Position */ +#define I2C_BUSCTL_PECTXEN_Msk (0x1ul << I2C_BUSCTL_PECTXEN_Pos) /*!< I2C_T::BUSCTL: PECTXEN Mask */ + +#define I2C_BUSCTL_TIDLE_Pos (9) /*!< I2C_T::BUSCTL: TIDLE Position */ +#define I2C_BUSCTL_TIDLE_Msk (0x1ul << I2C_BUSCTL_TIDLE_Pos) /*!< I2C_T::BUSCTL: TIDLE Mask */ + +#define I2C_BUSCTL_PECCLR_Pos (10) /*!< I2C_T::BUSCTL: PECCLR Position */ +#define I2C_BUSCTL_PECCLR_Msk (0x1ul << I2C_BUSCTL_PECCLR_Pos) /*!< I2C_T::BUSCTL: PECCLR Mask */ + +#define I2C_BUSCTL_ACKM9SI_Pos (11) /*!< I2C_T::BUSCTL: ACKM9SI Position */ +#define I2C_BUSCTL_ACKM9SI_Msk (0x1ul << I2C_BUSCTL_ACKM9SI_Pos) /*!< I2C_T::BUSCTL: ACKM9SI Mask */ + +#define I2C_BUSCTL_BCDIEN_Pos (12) /*!< I2C_T::BUSCTL: BCDIEN Position */ +#define I2C_BUSCTL_BCDIEN_Msk (0x1ul << I2C_BUSCTL_BCDIEN_Pos) /*!< I2C_T::BUSCTL: BCDIEN Mask */ + +#define I2C_BUSCTL_PECDIEN_Pos (13) /*!< I2C_T::BUSCTL: PECDIEN Position */ +#define I2C_BUSCTL_PECDIEN_Msk (0x1ul << I2C_BUSCTL_PECDIEN_Pos) /*!< I2C_T::BUSCTL: PECDIEN Mask */ + +#define I2C_BUSTCTL_BUSTOEN_Pos (0) /*!< I2C_T::BUSTCTL: BUSTOEN Position */ +#define I2C_BUSTCTL_BUSTOEN_Msk (0x1ul << I2C_BUSTCTL_BUSTOEN_Pos) /*!< I2C_T::BUSTCTL: BUSTOEN Mask */ + +#define I2C_BUSTCTL_CLKTOEN_Pos (1) /*!< I2C_T::BUSTCTL: CLKTOEN Position */ +#define I2C_BUSTCTL_CLKTOEN_Msk (0x1ul << I2C_BUSTCTL_CLKTOEN_Pos) /*!< I2C_T::BUSTCTL: CLKTOEN Mask */ + +#define I2C_BUSTCTL_BUSTOIEN_Pos (2) /*!< I2C_T::BUSTCTL: BUSTOIEN Position */ +#define I2C_BUSTCTL_BUSTOIEN_Msk (0x1ul << I2C_BUSTCTL_BUSTOIEN_Pos) /*!< I2C_T::BUSTCTL: BUSTOIEN Mask */ + +#define I2C_BUSTCTL_CLKTOIEN_Pos (3) /*!< I2C_T::BUSTCTL: CLKTOIEN Position */ +#define I2C_BUSTCTL_CLKTOIEN_Msk (0x1ul << I2C_BUSTCTL_CLKTOIEN_Pos) /*!< I2C_T::BUSTCTL: CLKTOIEN Mask */ + +#define I2C_BUSTCTL_TORSTEN_Pos (4) /*!< I2C_T::BUSTCTL: TORSTEN Position */ +#define I2C_BUSTCTL_TORSTEN_Msk (0x1ul << I2C_BUSTCTL_TORSTEN_Pos) /*!< I2C_T::BUSTCTL: TORSTEN Mask */ + +#define I2C_BUSSTS_BUSY_Pos (0) /*!< I2C_T::BUSSTS: BUSY Position */ +#define I2C_BUSSTS_BUSY_Msk (0x1ul << I2C_BUSSTS_BUSY_Pos) /*!< I2C_T::BUSSTS: BUSY Mask */ + +#define I2C_BUSSTS_BCDONE_Pos (1) /*!< I2C_T::BUSSTS: BCDONE Position */ +#define I2C_BUSSTS_BCDONE_Msk (0x1ul << I2C_BUSSTS_BCDONE_Pos) /*!< I2C_T::BUSSTS: BCDONE Mask */ + +#define I2C_BUSSTS_PECERR_Pos (2) /*!< I2C_T::BUSSTS: PECERR Position */ +#define I2C_BUSSTS_PECERR_Msk (0x1ul << I2C_BUSSTS_PECERR_Pos) /*!< I2C_T::BUSSTS: PECERR Mask */ + +#define I2C_BUSSTS_ALERT_Pos (3) /*!< I2C_T::BUSSTS: ALERT Position */ +#define I2C_BUSSTS_ALERT_Msk (0x1ul << I2C_BUSSTS_ALERT_Pos) /*!< I2C_T::BUSSTS: ALERT Mask */ + +#define I2C_BUSSTS_SCTLDIN_Pos (4) /*!< I2C_T::BUSSTS: SCTLDIN Position */ +#define I2C_BUSSTS_SCTLDIN_Msk (0x1ul << I2C_BUSSTS_SCTLDIN_Pos) /*!< I2C_T::BUSSTS: SCTLDIN Mask */ + +#define I2C_BUSSTS_BUSTO_Pos (5) /*!< I2C_T::BUSSTS: BUSTO Position */ +#define I2C_BUSSTS_BUSTO_Msk (0x1ul << I2C_BUSSTS_BUSTO_Pos) /*!< I2C_T::BUSSTS: BUSTO Mask */ + +#define I2C_BUSSTS_CLKTO_Pos (6) /*!< I2C_T::BUSSTS: CLKTO Position */ +#define I2C_BUSSTS_CLKTO_Msk (0x1ul << I2C_BUSSTS_CLKTO_Pos) /*!< I2C_T::BUSSTS: CLKTO Mask */ + +#define I2C_BUSSTS_PECDONE_Pos (7) /*!< I2C_T::BUSSTS: PECDONE Position */ +#define I2C_BUSSTS_PECDONE_Msk (0x1ul << I2C_BUSSTS_PECDONE_Pos) /*!< I2C_T::BUSSTS: PECDONE Mask */ + +#define I2C_PKTSIZE_PLDSIZE_Pos (0) /*!< I2C_T::PKTSIZE: PLDSIZE Position */ +#define I2C_PKTSIZE_PLDSIZE_Msk (0x1fful << I2C_PKTSIZE_PLDSIZE_Pos) /*!< I2C_T::PKTSIZE: PLDSIZE Mask */ + +#define I2C_PKTCRC_PECCRC_Pos (0) /*!< I2C_T::PKTCRC: PECCRC Position */ +#define I2C_PKTCRC_PECCRC_Msk (0xfful << I2C_PKTCRC_PECCRC_Pos) /*!< I2C_T::PKTCRC: PECCRC Mask */ + +#define I2C_BUSTOUT_BUSTO_Pos (0) /*!< I2C_T::BUSTOUT: BUSTO Position */ +#define I2C_BUSTOUT_BUSTO_Msk (0xfful << I2C_BUSTOUT_BUSTO_Pos) /*!< I2C_T::BUSTOUT: BUSTO Mask */ + +#define I2C_CLKTOUT_CLKTO_Pos (0) /*!< I2C_T::CLKTOUT: CLKTO Position */ +#define I2C_CLKTOUT_CLKTO_Msk (0xfful << I2C_CLKTOUT_CLKTO_Pos) /*!< I2C_T::CLKTOUT: CLKTO Mask */ + +/**@}*/ /* I2C_CONST */ +/**@}*/ /* end of I2C register group */ +/**@}*/ /* end of REGISTER group */ + + +#endif /* __I2C_REG_H__ */ diff --git a/Ubiquitous/XiZi/board/nuvoton-m2354/third_party_driver/include/Regs/i2s_reg.h b/Ubiquitous/XiZi/board/nuvoton-m2354/third_party_driver/include/Regs/i2s_reg.h new file mode 100644 index 0000000..5dc3951 --- /dev/null +++ b/Ubiquitous/XiZi/board/nuvoton-m2354/third_party_driver/include/Regs/i2s_reg.h @@ -0,0 +1,701 @@ +/**************************************************************************//** + * @file i2s_reg.h + * @version V1.00 + * @brief I2S register definition header file + * + * @copyright SPDX-License-Identifier: Apache-2.0 + * @copyright Copyright (C) 2020 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ +#ifndef __I2S_REG_H__ +#define __I2S_REG_H__ + +/** @addtogroup REGISTER Control Register + + @{ + +*/ + +/*---------------------- I2S Interface Controller -------------------------*/ +/** + @addtogroup I2S I2S Interface Controller(I2S) + Memory Mapped Structure for I2S Controller + @{ +*/ + +typedef struct +{ + + + /** + * @var I2S_T::CTL0 + * Offset: 0x00 I2S Control Register 0 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |I2SEN |I2S Controller Enable Control + * | | |0 = I2S controller Disabled. + * | | |1 = I2S controller Enabled. + * |[1] |TXEN |Transmit Enable Control + * | | |0 = Data transmission Disabled. + * | | |1 = Data transmission Enabled. + * |[2] |RXEN |Receive Enable Control + * | | |0 = Data receiving Disabled. + * | | |1 = Data receiving Enabled. + * |[3] |MUTE |Transmit Mute Enable Control + * | | |0 = Transmit data is shifted from buffer. + * | | |1 = Send zero on transmit channel. + * |[5:4] |DATWIDTH |Data Width + * | | |This bit field is used to define the bit-width of data word in each audio channel + * | | |00 = The bit-width of data word is 8-bit. + * | | |01 = The bit-width of data word is 16-bit. + * | | |10 = The bit-width of data word is 24-bit. + * | | |11 = The bit-width of data word is 32-bit. + * |[6] |MONO |Monaural Data Control + * | | |0 = Data is stereo format. + * | | |1 = Data is monaural format. + * | | |Note: when chip records data, RXLCH (I2S_CTL0[23]) indicates which channel data will be saved if monaural format is selected. + * |[7] |ORDER |Stereo Data Order in FIFO + * | | |In 8-bit/16-bit data width, this bit is used to select whether the even or odd channel data is stored in higher byte + * | | |In 24-bit data width, this is used to select the left/right alignment method of audio data which is stored in data memory consisted of 32-bit FIFO entries. + * | | |0 = Even channel data at high byte in 8-bit/16-bit data width. + * | | |LSB of 24-bit audio data in each channel is aligned to right side in 32-bit FIFO entries. + * | | |1 = Even channel data at low byte. + * | | | MSB of 24-bit audio data in each channel is aligned to left side in 32-bit FIFO entries. + * |[8] |SLAVE |Slave Mode Enable Control + * | | |0 = Master mode. + * | | |1 = Slave mode. + * | | |Note: I2S can operate as master or slave + * | | |For Master mode, I2S_BCLK and I2S_LRCLK pins are output mode and send out bit clock to Audio CODEC chip + * | | |In Slave mode, I2S_BCLK and I2S_LRCLK pins are input mode and I2S_BCLK and I2S_LRCLK signals are received from outer Audio CODEC chip. + * |[15] |MCLKEN |Master Clock Enable Control + * | | |If MCLKEN is set to 1, I2S controller will generate master clock on I2S_MCLK pin for external audio devices. + * | | |0 = Master clock Disabled. + * | | |1 = Master clock Enabled. + * |[18] |TXFBCLR |Transmit FIFO Buffer Clear + * | | |0 = No Effect. + * | | |1 = Clear TX FIFO. + * | | |Note 1: Write 1 to clear transmit FIFO, internal pointer is reset to FIFO start point, and TXCNT (I2S_STATUS1[12:8]) returns 0 and transmit FIFO becomes empty but data in transmit FIFO is not changed. + * | | |Note 2: This bit is clear by hardware automatically, read it return zero. + * |[19] |RXFBCLR |Receive FIFO Buffer Clear + * | | |0 = No Effect. + * | | |1 = Clear RX FIFO. + * | | |Note 1: Write 1 to clear receive FIFO, internal pointer is reset to FIFO start point, and RXCNT (I2S_STATUS1[20:16]) returns 0 and receive FIFO becomes empty. + * | | |Note 2: This bit is cleared by hardware automatically, read it return zero. + * |[20] |TXPDMAEN |Transmit PDMA Enable Control + * | | |0 = Transmit PDMA function Disabled. + * | | |1 = Transmit PDMA function Enabled. + * |[21] |RXPDMAEN |Receive PDMA Enable Control + * | | |0 = Receiver PDMA function Disabled. + * | | |1 = Receiver PDMA function Enabled. + * |[23] |RXLCH |Receive Left Channel Enable Control + * | | |When monaural format is selected (MONO = 1), I2S will receive channel1 data if RXLCH is set to 0, and receive channel0 data if RXLCH is set to 1. + * | | |0 = Receives channel1 data in MONO mode. + * | | |1 = Receives channel0 data in MONO mode. + * |[26:24] |FORMAT |Data Format Selection + * | | |000 = I2S standard data format. + * | | |001 = I2S with MSB justified. + * | | |010 = I2S with LSB justified. + * | | |011 = Reserved. + * | | |100 = PCM standard data format. + * | | |101 = PCM with MSB justified. + * | | |110 = PCM with LSB justified. + * | | |111 = Reserved. + * |[27] |PCMSYNC |PCM Synchronization Pulse Length Selection + * | | |This bit field is used to select the high pulse length of frame synchronization signal in PCM protocol. + * | | |0 = One BCLK period. + * | | |1 = One channel period. + * | | |Note: This bit is only available in master mode. + * |[29:28] |CHWIDTH |Channel Width + * | | |This bit fields are used to define the length of audio channel + * | | |If CHWIDTH < DATWIDTH, the hardware will set the real channel length as the bit-width of audio data which is defined by DATWIDTH. + * | | |00 = The bit-width of each audio channel is 8-bit. + * | | |01 = The bit-width of each audio channel is 16-bit. + * | | |10 = The bit-width of each audio channel is 24-bit. + * | | |11 = The bit-width of each audio channel is 32-bit. + * |[31:30] |TDMCHNUM |TDM Channel Number + * | | |This bit fields are used to define the TDM channel number in one audio frame while PCM mode (FORMAT[2] = 1). + * | | |00 = 2 channels in audio frame. + * | | |01 = 4 channels in audio frame. + * | | |10 = 6 channels in audio frame. + * | | |11 = 8 channels in audio frame. + * @var I2S_T::CLKDIV + * Offset: 0x04 I2S Clock Divider Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[5:0] |MCLKDIV |Master Clock Divider + * | | |If chip external crystal frequency is (2 x MCLKDIV) x 256fs then software can program these bits to generate 256fs clock frequency to audio codec chip + * | | |If MCLKDIV is set to 0, MCLK is the same as external clock input. + * | | |For example, sampling rate is 24 kHz and chip external crystal clock is 12.288 MHz, set MCLKDIV = 1. + * | | |F_MCLK = F_I2SCLK/(2 x MCLKDIV) (When MCLKDIV is >= 1 ). + * | | |F_MCLK = F_I2SCLK (When MCLKDIV is set to 0 ). + * | | |Note: F_MCLK is the frequency of MCLK, and F_I2SCLK is the frequency of the I2S_CLK. + * |[16:8] |BCLKDIV |Bit Clock Divider + * | | |The I2S controller will generate bit clock in Master mode + * | | |Software can program these bit fields to generate sampling rate clock frequency. + * | | |F_BCLK= F_I2SCLK / (2 x (BCLKDIV + 1)). + * | | |Note: F_BCLK is the frequency of BCLK and F_I2SCLK is the frequency of I2S_CLK. + * @var I2S_T::IEN + * Offset: 0x08 I2S Interrupt Enable Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |RXUDFIEN |Receive FIFO Underflow Interrupt Enable Control + * | | |0 = Interrupt Disabled. + * | | |1 = Interrupt Enabled. + * | | |Note: If software reads receive FIFO when it is empty then RXUDIF (I2S_STATUS0[8]) flag is set to 1. + * |[1] |RXOVFIEN |Receive FIFO Overflow Interrupt Enable Control + * | | |0 = Interrupt Disabled. + * | | |1 = Interrupt Enabled. + * | | |Note: Interrupt occurs if this bit is set to 1 and RXOVIF (I2S_STATUS0[9]) flag is set to 1. + * |[2] |RXTHIEN |Receive FIFO Threshold Level Interrupt Enable Control + * | | |0 = Interrupt Disabled. + * | | |1 = Interrupt Enabled. + * | | |Note: When data word in receive FIFO is equal or higher than RXTH (I2S_CTL1[19:16]) and the RXTHIF (I2S_STATUS0[10]) bit is set to 1 + * | | |If RXTHIEN bit is enabled, interrupt occur. + * |[8] |TXUDFIEN |Transmit FIFO Underflow Interrupt Enable Control + * | | |0 = Interrupt Disabled. + * | | |1 = Interrupt Enabled. + * | | |Note: Interrupt occur if this bit is set to 1 and TXUDIF (I2S_STATUS0[16]) flag is set to 1. + * |[9] |TXOVFIEN |Transmit FIFO Overflow Interrupt Enable Control + * | | |0 = Interrupt Disabled. + * | | |1 = Interrupt Enabled. + * | | |Note: Interrupt occurs if this bit is set to 1 and TXOVIF (I2S_STATUS0[17]) flag is set to 1. + * |[10] |TXTHIEN |Transmit FIFO Threshold Level Interrupt Enable Control + * | | |0 = Interrupt Disabled. + * | | |1 = Interrupt Enabled. + * | | |Note: Interrupt occurs if this bit is set to 1 and data words in transmit FIFO is less than TXTH (I2S_CTL1[11:8]). + * |[16] |CH0ZCIEN |Channel0 Zero-cross Interrupt Enable Control + * | | |0 = Interrupt Disabled. + * | | |1 = Interrupt Enabled. + * | | |Note 1: Interrupt occurs if this bit is set to 1 and channel0 zero-cross. + * | | |Note 2: Channel0 also means left audio channel while I2S (FORMAT[2]=0) or 2-channel PCM mode. + * |[17] |CH1ZCIEN |Channel1 Zero-cross Interrupt Enable Control + * | | |0 = Interrupt Disabled. + * | | |1 = Interrupt Enabled. + * | | |Note 1: Interrupt occurs if this bit is set to 1 and channel1 zero-cross. + * | | |Note 2: Channel1 also means right audio channel while I2S (FORMAT[2]=0) or 2-channel PCM mode. + * |[18] |CH2ZCIEN |Channel2 Zero-cross Interrupt Enable Control + * | | |0 = Interrupt Disabled. + * | | |1 = Interrupt Enabled. + * | | |Note 1: Interrupt occurs if this bit is set to 1 and channel2 zero-cross. + * | | |Note 2: This bit is available while multi-channel PCM mode and TDMCHNUM (I2S_CTL0[31:30]) = 0x1, 0x2, 0x3. + * |[19] |CH3ZCIEN |Channel3 Zero-cross Interrupt Enable Control + * | | |0 = Interrupt Disabled. + * | | |1 = Interrupt Enabled. + * | | |Note 1: Interrupt occurs if this bit is set to 1 and channel3 zero-cross. + * | | |Note 2: This bit is available while multi-channel PCM mode and TDMCHNUM (I2S_CTL0[31:30]) = 0x1, 0x2, 0x3. + * |[20] |CH4ZCIEN |Channel4 Zero-cross Interrupt Enable Control + * | | |0 = Interrupt Disabled. + * | | |1 = Interrupt Enabled. + * | | |Note 1: Interrupt occurs if this bit is set to 1 and channel4 zero-cross. + * | | |Note 2: This bit is available while multi-channel PCM mode and TDMCHNUM (I2S_CTL0[31:30]) = 0x1, 0x2, 0x3. + * |[21] |CH5ZCIEN |Channel5 Zero-cross Interrupt Enable Control + * | | |0 = Interrupt Disabled. + * | | |1 = Interrupt Enabled. + * | | |Note 1: Interrupt occurs if this bit is set to 1 and channel5 zero-cross. + * | | |Note 2: This bit is available while multi-channel PCM mode and TDMCHNUM (I2S_CTL0[31:30]) = 0x1, 0x2, 0x3. + * |[22] |CH6ZCIEN |Channel6 Zero-cross Interrupt Enable Control + * | | |0 = Interrupt Disabled. + * | | |1 = Interrupt Enabled. + * | | |Note 1: Interrupt occurs if this bit is set to 1 and channel6 zero-cross. + * | | |Note 2: This bit is available while multi-channel PCM mode and TDMCHNUM (I2S_CTL0[31:30]) = 0x1, 0x2, 0x3. + * |[23] |CH7ZCIEN |Channel7 Zero-cross Interrupt Enable Control + * | | |0 = Interrupt Disabled. + * | | |1 = Interrupt Enabled. + * | | |Note 1: Interrupt occurs if this bit is set to 1 and channel7 zero-cross. + * | | |Note 2: This bit is available while multi-channel PCM mode and TDMCHNUM (I2S_CTL0[31:30]) = 0x1, 0x2, 0x3. + * @var I2S_T::STATUS0 + * Offset: 0x0C I2S Status Register 0 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |I2SINT |I2S Interrupt Flag (Read Only) + * | | |0 = No I2S interrupt. + * | | |1 = I2S interrupt. + * | | |Note: It is wire-OR of I2STXINT and I2SRXINT bits. + * |[1] |I2SRXINT |I2S Receive Interrupt (Read Only) + * | | |0 = No receive interrupt. + * | | |1 = Receive interrupt. + * |[2] |I2STXINT |I2S Transmit Interrupt (Read Only) + * | | |0 = No transmit interrupt. + * | | |1 = Transmit interrupt. + * |[5:3] |DATACH |Transmission Data Channel (Read Only) + * | | |This bit fields are used to indicate which audio channel is current transmit data belong. + * | | |000 = channel0 (means left channel while 2-channel I2S/PCM mode). + * | | |001 = channel1 (means right channel while 2-channel I2S/PCM mode). + * | | |010 = channel2 (available while 4-channel TDM PCM mode). + * | | |011 = channel3 (available while 4-channel TDM PCM mode). + * | | |100 = channel4 (available while 6-channel TDM PCM mode). + * | | |101 = channel5 (available while 6-channel TDM PCM mode). + * | | |110 = channel6 (available while 8-channel TDM PCM mode). + * | | |111 = channel7 (available while 8-channel TDM PCM mode). + * |[8] |RXUDIF |Receive FIFO Underflow Interrupt Flag + * | | |0 = No underflow occur. + * | | |1 = Underflow occur. + * | | |Note 1: When receive FIFO is empty, and software reads the receive FIFO again + * | | |This bit will be set to 1, and it indicates underflow situation occurs. + * | | |Note 2: Write 1 to clear this bit to zero + * |[9] |RXOVIF |Receive FIFO Overflow Interrupt Flag + * | | |0 = No overflow occur. + * | | |1 = Overflow occur. + * | | |Note 1: When receive FIFO is full and receive hardware attempt to write data into receive FIFO then this bit is set to 1, data in 1st buffer is overwrote. + * | | |Note 2: Write 1 to clear this bit to 0. + * |[10] |RXTHIF |Receive FIFO Threshold Interrupt Flag (Read Only) + * | | |0 = Data word(s) in FIFO is not higher than threshold level. + * | | |1 = Data word(s) in FIFO is higher than threshold level. + * | | |Note: When data word(s) in receive FIFO is higher than threshold value set in RXTH (I2S_CTL1[19:16]) the RXTHIF bit becomes to 1 + * | | |It keeps at 1 till RXCNT (I2S_STATUS1[20:16]) is not higher than RXTH (I2S_CTL1[19:16]) after software read RXFIFO register. + * |[11] |RXFULL |Receive FIFO Full (Read Only) + * | | |0 = Not full. + * | | |1 = Full. + * | | |Note: This bit reflects data words number in receive FIFO is 16. + * |[12] |RXEMPTY |Receive FIFO Empty (Read Only) + * | | |0 = Not empty. + * | | |1 = Empty. + * | | |Note: This bit reflects data words number in receive FIFO is 0. + * |[16] |TXUDIF |Transmit FIFO Underflow Interrupt Flag + * | | |0 = No underflow. + * | | |1 = Underflow. + * | | |Note 1: This bit will be set to 1 when shift logic hardware read data from transmitting FIFO and the filling data level in transmitting FIFO is not enough for one audio frame. + * | | |Note 2: Write 1 to clear this bit to 0. + * |[17] |TXOVIF |Transmit FIFO Overflow Interrupt Flag + * | | |0 = No overflow. + * | | |1 = Overflow. + * | | |Note 1: Write data to transmit FIFO when it is full and this bit set to 1. + * | | |Note 2: Write 1 to clear this bit to 0. + * |[18] |TXTHIF |Transmit FIFO Threshold Interrupt Flag (Read Only) + * | | |0 = Data word(s) in FIFO is higher than threshold level. + * | | |1 = Data word(s) in FIFO is equal or lower than threshold level. + * | | |Note: When data word(s) in transmit FIFO is equal or lower than threshold value set in TXTH (I2S_CTL1[11:8]) the TXTHIF bit becomes to 1 + * | | |It keeps at 1 till TXCNT (I2S_STATUS1[12:8]) is higher than TXTH (I2S_CTL1[11:8]) after software write TXFIFO register. + * |[19] |TXFULL |Transmit FIFO Full (Read Only) + * | | |0 = Not full. + * | | |1 = Full. + * | | |Note: This bit reflects data words number in transmit FIFO is 16. + * |[20] |TXEMPTY |Transmit FIFO Empty (Read Only) + * | | |0 = Not empty. + * | | |1 = Empty. + * | | |Note: This bit reflects data words number in transmit FIFO is 0. + * |[21] |TXBUSY |Transmit Busy (Read Only) + * | | |0 = Transmit shift buffer is empty. + * | | |1 = Transmit shift buffer is busy. + * | | |Note: This bit is cleared to 0 when all data in transmit FIFO and shift buffer is shifted out + * | | |And set to 1 when 1st data is load to shift buffer + * @var I2S_T::TXFIFO + * Offset: 0x10 I2S Transmit FIFO Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |TXFIFO |Transmit FIFO Bits + * | | |I2S contains 16 words (16x32 bit) data buffer for data transmit + * | | |Write data to this register to prepare data for transmit + * | | |The remaining word number is indicated by TXCNT (I2S_STATUS1[12:8]). + * @var I2S_T::RXFIFO + * Offset: 0x14 I2S Receive FIFO Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |RXFIFO |Receive FIFO Bits + * | | |I2S contains 16 words (16x32 bit) data buffer for data receive + * | | |Read this register to get data in FIFO + * | | |The remaining data word number is indicated by RXCNT (I2S_STATUS1[20:16]). + * @var I2S_T::CTL1 + * Offset: 0x20 I2S Control Register 1 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |CH0ZCEN |Channel0 Zero-cross Detection Enable Control + * | | |0 = channel0 zero-cross detect Disabled. + * | | |1 = channel0 zero-cross detect Enabled. + * | | |Note 1: Channel0 also means left audio channel while I2S (FORMAT[2]=0) or 2-channel PCM mode. + * | | |Note 2: If this bit is set to 1, when channel0 data sign bit change or next shift data bits are all zero then CH0ZCIF(I2S_STATUS1[0]) flag is set to 1. + * | | |Note 3: If CH0ZCIF Flag is set to 1, the channel0 will be mute. + * |[1] |CH1ZCEN |Channel1 Zero-cross Detect Enable Control + * | | |0 = channel1 zero-cross detect Disabled. + * | | |1 = channel1 zero-cross detect Enabled. + * | | |Note 1: Channel1 also means right audio channel while I2S (FORMAT[2]=0) or 2-channel PCM mode. + * | | |Note 2: If this bit is set to 1, when channel1 data sign bit change or next shift data bits are all zero then CH1ZCIF(I2S_STATUS1[1]) flag is set to 1. + * | | |Note 3: If CH1ZCIF Flag is set to 1, the channel1 will be mute. + * |[2] |CH2ZCEN |Channel2 Zero-cross Detect Enable Control + * | | |0 = channel2 zero-cross detect Disabled. + * | | |1 = channel2 zero-cross detect Enabled. + * | | |Note 1: This bit is available while multi-channel PCM mode and TDMCHNUM (I2S_CTL0[31:30]) = 0x1, 0x2, 0x3. + * | | |Note 2: If this bit is set to 1, when channel2 data sign bit change or next shift data bits are all zero then CH2ZCIF(I2S_STATUS1[2]) flag is set to 1. + * | | |Note 3: If CH2ZCIF Flag is set to 1, the channel2 will be mute. + * |[3] |CH3ZCEN |Channel3 Zero-cross Detect Enable Control + * | | |0 = channel3 zero-cross detect Disabled. + * | | |1 = channel3 zero-cross detect Enabled. + * | | |Note 1: This bit is available while multi-channel PCM mode and TDMCHNUM (I2S_CTL0[31:30]) = 0x1, 0x2, 0x3. + * | | |Note 2: If this bit is set to 1, when channel3 data sign bit change or next shift data bits are all zero then CH3ZCIF(I2S_STATUS1[3]) flag is set to 1. + * | | |Note 3: If CH3ZCIF Flag is set to 1, the channel3 will be mute. + * |[4] |CH4ZCEN |Channel4 Zero-cross Detect Enable Control + * | | |0 = channel4 zero-cross detect Disabled. + * | | |1 = channel4 zero-cross detect Enabled. + * | | |Note 1: This bit is available while multi-channel PCM mode and TDMCHNUM (I2S_CTL0[31:30]) = 0x1, 0x2, 0x3. + * | | |Note 2: If this bit is set to 1, when channel4 data sign bit change or next shift data bits are all zero then CH4ZCIF(I2S_STATUS1[4]) flag is set to 1. + * | | |Note 3: If CH4ZCIF Flag is set to 1, the channel4 will be mute. + * |[5] |CH5ZCEN |Channel5 Zero-cross Detect Enable Control + * | | |0 = channel5 zero-cross detect Disabled. + * | | |1 = channel5 zero-cross detect Enabled. + * | | |Note 1: This bit is available while multi-channel PCM mode and TDMCHNUM (I2S_CTL0[31:30]) = 0x1, 0x2, 0x3. + * | | |Note 2: If this bit is set to 1, when channel5 data sign bit change or next shift data bits are all zero then CH5ZCIF(I2S_STATUS1[5]) flag is set to 1. + * | | |Note 3: If CH5ZCIF Flag is set to 1, the channel5 will be mute. + * |[6] |CH6ZCEN |Channel6 Zero-cross Detect Enable Control + * | | |0 = channel6 zero-cross detect Disabled. + * | | |1 = channel6 zero-cross detect Enabled. + * | | |Note 1: This bit is available while multi-channel PCM mode and TDMCHNUM (I2S_CTL0[31:30]) = 0x1, 0x2, 0x3. + * | | |Note 2: If this bit is set to 1, when channel6 data sign bit change or next shift data bits are all zero then CH6ZCIF(I2S_STATUS1[6]) flag is set to 1. + * | | |Note 3: If CH6ZCIF Flag is set to 1, the channel6 will be mute. + * |[7] |CH7ZCEN |Channel7 Zero-cross Detect Enable Control + * | | |0 = channel7 zero-cross detect Disabled. + * | | |1 = channel7 zero-cross detect Enabled. + * | | |Note 1: This bit is available while multi-channel PCM mode and TDMCHNUM (I2S_CTL0[31:30]) = 0x1, 0x2, 0x3. + * | | |Note 2: If this bit is set to 1, when channel7 data sign bit change or next shift data bits are all zero then CH7ZCIF (I2S_STATUS1[7]) flag is set to 1. + * | | |Note 3: If CH7ZCIF Flag is set to 1, the channel7 will be mute. + * |[11:8] |TXTH |Transmit FIFO Threshold Level + * | | |0000 = 0 data word in transmit FIFO. + * | | |0001 = 1 data word in transmit FIFO. + * | | |0010 = 2 data words in transmit FIFO. + * | | |... + * | | |1110 = 14 data words in transmit FIFO. + * | | |1111 = 15 data words in transmit FIFO. + * | | |Note: If remain data word number in transmit FIFO is the same or less than threshold level then TXTHIF (I2S_STATUS0[18]) flag is set. + * |[19:16] |RXTH |Receive FIFO Threshold Level + * | | |0000 = 1 data word in receive FIFO. + * | | |0001 = 2 data words in receive FIFO. + * | | |0010 = 3 data words in receive FIFO. + * | | |... + * | | |1110 = 15 data words in receive FIFO. + * | | |1111 = 16 data words in receive FIFO. + * | | |Note: When received data word number in receive buffer is greater than threshold level then RXTHIF (I2S_STATUS0[10]) flag is set. + * |[24] |PBWIDTH |Peripheral Bus Data Width Selection + * | | |This bit is used to choice the available data width of APB bus + * | | |It must be set to 1 while PDMA function is enable and it is set to 16-bit transmission mode + * | | |0 = 32 bits data width. + * | | |1 = 16 bits data width. + * | | |Note 1: If PBWIDTH=1, the low 16 bits of 32-bit data bus are available. + * | | |Note 2: If PBWIDTH=1, the transmitting FIFO level will be increased after two FIFO write operations. + * | | |Note 3: If PBWIDTH=1, the receiving FIFO level will be decreased after two FIFO read operations. + * |[25] |PB16ORD |FIFO Read/Write Order in 16-bit Width of Peripheral Bus + * | | |When PBWIDTH = 1, the data FIFO will be increased or decreased by two peripheral bus access + * | | |This bit is used to select the order of FIFO access operations to meet the 32-bit transmitting/receiving FIFO entries. + * | | |0 = Low 16-bit read/write access first. + * | | |1 = High 16-bit read/write access first. + * | | |Note: This bit is available while PBWIDTH = 1. + * @var I2S_T::STATUS1 + * Offset: 0x24 I2S Status Register 1 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |CH0ZCIF |Channel0 Zero-cross Interrupt Flag + * | | |It indicates channel0 next sample data sign bit is changed or all data bits are zero. + * | | |0 = No zero-cross in channel0. + * | | |1 = Channel0 zero-cross is detected. + * | | |Note 1: Write 1 to clear this bit to 0. + * | | |Note 2: Channel0 also means left audio channel while I2S (FORMAT[2]=0) or 2-channel PCM mode. + * |[1] |CH1ZCIF |Channel1 Zero-cross Interrupt Flag + * | | |It indicates channel1 next sample data sign bit is changed or all data bits are zero. + * | | |0 = No zero-cross in channel1. + * | | |1 = Channel1 zero-cross is detected. + * | | |Note 1: Write 1 to clear this bit to 0. + * | | |Note 2: Channel1 also means right audio channel while I2S (FORMAT[2]=0) or 2-channel PCM mode. + * |[2] |CH2ZCIF |Channel2 Zero-cross Interrupt Flag + * | | |It indicates channel2 next sample data sign bit is changed or all data bits are zero. + * | | |0 = No zero-cross in channel2. + * | | |1 = Channel2 zero-cross is detected. + * | | |Note 1: Write 1 to clear this bit to 0. + * | | |Note 2: This bit is available while multi-channel PCM mode and TDMCHNUM (I2S_CTL0[31:30]) = 0x1, 0x2, 0x3. + * |[3] |CH3ZCIF |Channel3 Zero-cross Interrupt Flag + * | | |It indicates channel3 next sample data sign bit is changed or all data bits are zero. + * | | |0 = No zero-cross in channel3. + * | | |1 = Channel3 zero-cross is detected. + * | | |Note 1: Write 1 to clear this bit to 0. + * | | |Note 2: This bit is available while multi-channel PCM mode and TDMCHNUM (I2S_CTL0[31:30]) = 0x1, 0x2, 0x3. + * |[4] |CH4ZCIF |Channel4 Zero-cross Interrupt Flag + * | | |It indicates channel4 next sample data sign bit is changed or all data bits are zero. + * | | |0 = No zero-cross in channel4. + * | | |1 = Channel4 zero-cross is detected. + * | | |Note 1: Write 1 to clear this bit to 0. + * | | |Note 2: This bit is available while multi-channel PCM mode and TDMCHNUM (I2S_CTL0[31:30]) = 0x1, 0x2, 0x3. + * |[5] |CH5ZCIF |Channel5 Zero-cross Interrupt Flag + * | | |It indicates channel5 next sample data sign bit is changed or all data bits are zero. + * | | |0 = No zero-cross in channel5. + * | | |1 = Channel5 zero-cross is detected. + * | | |Note 1: Write 1 to clear this bit to 0. + * | | |Note 2: This bit is available while multi-channel PCM mode and TDMCHNUM (I2S_CTL0[31:30]) = 0x1, 0x2, 0x3. + * |[6] |CH6ZCIF |Channel6 Zero-cross Interrupt Flag + * | | |It indicates channel6 next sample data sign bit is changed or all data bits are zero. + * | | |0 = No zero-cross in channel6. + * | | |1 = Channel6 zero-cross is detected. + * | | |Note 1: Write 1 to clear this bit to 0. + * | | |Note 2: This bit is available while multi-channel PCM mode and TDMCHNUM (I2S_CTL0[31:30]) = 0x1, 0x2, 0x3. + * |[7] |CH7ZCIF |Channel7 Zero-cross Interrupt Flag + * | | |It indicates channel7 next sample data sign bit is changed or all data bits are zero. + * | | |0 = No zero-cross in channel7. + * | | |1 = Channel7 zero-cross is detected. + * | | |Note 1: Write 1 to clear this bit to 0. + * | | |Note 2: This bit is available while multi-channel PCM mode and TDMCHNUM (I2S_CTL0[31:30]) = 0x1, 0x2, 0x3. + * |[12:8] |TXCNT |Transmit FIFO Level (Read Only) + * | | |These bits indicate the number of available entries in transmit FIFO. + * | | |00000 = No data. + * | | |00001 = 1 word in transmit FIFO. + * | | |00010 = 2 words in transmit FIFO. + * | | |... + * | | |01110 = 14 words in transmit FIFO. + * | | |01111 = 15 words in transmit FIFO. + * | | |10000 = 16 words in transmit FIFO. + * | | |Others are reserved. + * |[20:16] |RXCNT |Receive FIFO Level (Read Only) + * | | |These bits indicate the number of available entries in receive FIFO. + * | | |00000 = No data. + * | | |00001 = 1 word in receive FIFO. + * | | |00010 = 2 words in receive FIFO. + * | | |... + * | | |01110 = 14 words in receive FIFO. + * | | |01111 = 15 words in receive FIFO. + * | | |10000 = 16 words in receive FIFO. + * | | |Others are reserved. + */ + __IO uint32_t CTL0; /*!< [0x0000] I2S Control Register 0 */ + __IO uint32_t CLKDIV; /*!< [0x0004] I2S Clock Divider Register */ + __IO uint32_t IEN; /*!< [0x0008] I2S Interrupt Enable Register */ + __IO uint32_t STATUS0; /*!< [0x000c] I2S Status Register 0 */ + __O uint32_t TXFIFO; /*!< [0x0010] I2S Transmit FIFO Register */ + __I uint32_t RXFIFO; /*!< [0x0014] I2S Receive FIFO Register */ + __I uint32_t RESERVE0[2]; + __IO uint32_t CTL1; /*!< [0x0020] I2S Control Register 1 */ + __IO uint32_t STATUS1; /*!< [0x0024] I2S Status Register 1 */ + +} I2S_T; + +/** + @addtogroup I2S_CONST I2S Bit Field Definition + Constant Definitions for I2S Controller + @{ +*/ + +#define I2S_CTL0_I2SEN_Pos (0) /*!< I2S_T::CTL0: I2SEN Position */ +#define I2S_CTL0_I2SEN_Msk (0x1ul << I2S_CTL0_I2SEN_Pos) /*!< I2S_T::CTL0: I2SEN Mask */ + +#define I2S_CTL0_TXEN_Pos (1) /*!< I2S_T::CTL0: TXEN Position */ +#define I2S_CTL0_TXEN_Msk (0x1ul << I2S_CTL0_TXEN_Pos) /*!< I2S_T::CTL0: TXEN Mask */ + +#define I2S_CTL0_RXEN_Pos (2) /*!< I2S_T::CTL0: RXEN Position */ +#define I2S_CTL0_RXEN_Msk (0x1ul << I2S_CTL0_RXEN_Pos) /*!< I2S_T::CTL0: RXEN Mask */ + +#define I2S_CTL0_MUTE_Pos (3) /*!< I2S_T::CTL0: MUTE Position */ +#define I2S_CTL0_MUTE_Msk (0x1ul << I2S_CTL0_MUTE_Pos) /*!< I2S_T::CTL0: MUTE Mask */ + +#define I2S_CTL0_DATWIDTH_Pos (4) /*!< I2S_T::CTL0: DATWIDTH Position */ +#define I2S_CTL0_DATWIDTH_Msk (0x3ul << I2S_CTL0_DATWIDTH_Pos) /*!< I2S_T::CTL0: DATWIDTH Mask */ + +#define I2S_CTL0_MONO_Pos (6) /*!< I2S_T::CTL0: MONO Position */ +#define I2S_CTL0_MONO_Msk (0x1ul << I2S_CTL0_MONO_Pos) /*!< I2S_T::CTL0: MONO Mask */ + +#define I2S_CTL0_ORDER_Pos (7) /*!< I2S_T::CTL0: ORDER Position */ +#define I2S_CTL0_ORDER_Msk (0x1ul << I2S_CTL0_ORDER_Pos) /*!< I2S_T::CTL0: ORDER Mask */ + +#define I2S_CTL0_SLAVE_Pos (8) /*!< I2S_T::CTL0: SLAVE Position */ +#define I2S_CTL0_SLAVE_Msk (0x1ul << I2S_CTL0_SLAVE_Pos) /*!< I2S_T::CTL0: SLAVE Mask */ + +#define I2S_CTL0_MCLKEN_Pos (15) /*!< I2S_T::CTL0: MCLKEN Position */ +#define I2S_CTL0_MCLKEN_Msk (0x1ul << I2S_CTL0_MCLKEN_Pos) /*!< I2S_T::CTL0: MCLKEN Mask */ + +#define I2S_CTL0_TXFBCLR_Pos (18) /*!< I2S_T::CTL0: TXFBCLR Position */ +#define I2S_CTL0_TXFBCLR_Msk (0x1ul << I2S_CTL0_TXFBCLR_Pos) /*!< I2S_T::CTL0: TXFBCLR Mask */ + +#define I2S_CTL0_RXFBCLR_Pos (19) /*!< I2S_T::CTL0: RXFBCLR Position */ +#define I2S_CTL0_RXFBCLR_Msk (0x1ul << I2S_CTL0_RXFBCLR_Pos) /*!< I2S_T::CTL0: RXFBCLR Mask */ + +#define I2S_CTL0_TXPDMAEN_Pos (20) /*!< I2S_T::CTL0: TXPDMAEN Position */ +#define I2S_CTL0_TXPDMAEN_Msk (0x1ul << I2S_CTL0_TXPDMAEN_Pos) /*!< I2S_T::CTL0: TXPDMAEN Mask */ + +#define I2S_CTL0_RXPDMAEN_Pos (21) /*!< I2S_T::CTL0: RXPDMAEN Position */ +#define I2S_CTL0_RXPDMAEN_Msk (0x1ul << I2S_CTL0_RXPDMAEN_Pos) /*!< I2S_T::CTL0: RXPDMAEN Mask */ + +#define I2S_CTL0_RXLCH_Pos (23) /*!< I2S_T::CTL0: RXLCH Position */ +#define I2S_CTL0_RXLCH_Msk (0x1ul << I2S_CTL0_RXLCH_Pos) /*!< I2S_T::CTL0: RXLCH Mask */ + +#define I2S_CTL0_FORMAT_Pos (24) /*!< I2S_T::CTL0: FORMAT Position */ +#define I2S_CTL0_FORMAT_Msk (0x7ul << I2S_CTL0_FORMAT_Pos) /*!< I2S_T::CTL0: FORMAT Mask */ + +#define I2S_CTL0_PCMSYNC_Pos (27) /*!< I2S_T::CTL0: PCMSYNC Position */ +#define I2S_CTL0_PCMSYNC_Msk (0x1ul << I2S_CTL0_PCMSYNC_Pos) /*!< I2S_T::CTL0: PCMSYNC Mask */ + +#define I2S_CTL0_CHWIDTH_Pos (28) /*!< I2S_T::CTL0: CHWIDTH Position */ +#define I2S_CTL0_CHWIDTH_Msk (0x3ul << I2S_CTL0_CHWIDTH_Pos) /*!< I2S_T::CTL0: CHWIDTH Mask */ + +#define I2S_CTL0_TDMCHNUM_Pos (30) /*!< I2S_T::CTL0: TDMCHNUM Position */ +#define I2S_CTL0_TDMCHNUM_Msk (0x3ul << I2S_CTL0_TDMCHNUM_Pos) /*!< I2S_T::CTL0: TDMCHNUM Mask */ + +#define I2S_CLKDIV_MCLKDIV_Pos (0) /*!< I2S_T::CLKDIV: MCLKDIV Position */ +#define I2S_CLKDIV_MCLKDIV_Msk (0x3ful << I2S_CLKDIV_MCLKDIV_Pos) /*!< I2S_T::CLKDIV: MCLKDIV Mask */ + +#define I2S_CLKDIV_BCLKDIV_Pos (8) /*!< I2S_T::CLKDIV: BCLKDIV Position */ +#define I2S_CLKDIV_BCLKDIV_Msk (0x1fful << I2S_CLKDIV_BCLKDIV_Pos) /*!< I2S_T::CLKDIV: BCLKDIV Mask */ + +#define I2S_IEN_RXUDFIEN_Pos (0) /*!< I2S_T::IEN: RXUDFIEN Position */ +#define I2S_IEN_RXUDFIEN_Msk (0x1ul << I2S_IEN_RXUDFIEN_Pos) /*!< I2S_T::IEN: RXUDFIEN Mask */ + +#define I2S_IEN_RXOVFIEN_Pos (1) /*!< I2S_T::IEN: RXOVFIEN Position */ +#define I2S_IEN_RXOVFIEN_Msk (0x1ul << I2S_IEN_RXOVFIEN_Pos) /*!< I2S_T::IEN: RXOVFIEN Mask */ + +#define I2S_IEN_RXTHIEN_Pos (2) /*!< I2S_T::IEN: RXTHIEN Position */ +#define I2S_IEN_RXTHIEN_Msk (0x1ul << I2S_IEN_RXTHIEN_Pos) /*!< I2S_T::IEN: RXTHIEN Mask */ + +#define I2S_IEN_TXUDFIEN_Pos (8) /*!< I2S_T::IEN: TXUDFIEN Position */ +#define I2S_IEN_TXUDFIEN_Msk (0x1ul << I2S_IEN_TXUDFIEN_Pos) /*!< I2S_T::IEN: TXUDFIEN Mask */ + +#define I2S_IEN_TXOVFIEN_Pos (9) /*!< I2S_T::IEN: TXOVFIEN Position */ +#define I2S_IEN_TXOVFIEN_Msk (0x1ul << I2S_IEN_TXOVFIEN_Pos) /*!< I2S_T::IEN: TXOVFIEN Mask */ + +#define I2S_IEN_TXTHIEN_Pos (10) /*!< I2S_T::IEN: TXTHIEN Position */ +#define I2S_IEN_TXTHIEN_Msk (0x1ul << I2S_IEN_TXTHIEN_Pos) /*!< I2S_T::IEN: TXTHIEN Mask */ + +#define I2S_IEN_CH0ZCIEN_Pos (16) /*!< I2S_T::IEN: CH0ZCIEN Position */ +#define I2S_IEN_CH0ZCIEN_Msk (0x1ul << I2S_IEN_CH0ZCIEN_Pos) /*!< I2S_T::IEN: CH0ZCIEN Mask */ + +#define I2S_IEN_CH1ZCIEN_Pos (17) /*!< I2S_T::IEN: CH1ZCIEN Position */ +#define I2S_IEN_CH1ZCIEN_Msk (0x1ul << I2S_IEN_CH1ZCIEN_Pos) /*!< I2S_T::IEN: CH1ZCIEN Mask */ + +#define I2S_IEN_CH2ZCIEN_Pos (18) /*!< I2S_T::IEN: CH2ZCIEN Position */ +#define I2S_IEN_CH2ZCIEN_Msk (0x1ul << I2S_IEN_CH2ZCIEN_Pos) /*!< I2S_T::IEN: CH2ZCIEN Mask */ + +#define I2S_IEN_CH3ZCIEN_Pos (19) /*!< I2S_T::IEN: CH3ZCIEN Position */ +#define I2S_IEN_CH3ZCIEN_Msk (0x1ul << I2S_IEN_CH3ZCIEN_Pos) /*!< I2S_T::IEN: CH3ZCIEN Mask */ + +#define I2S_IEN_CH4ZCIEN_Pos (20) /*!< I2S_T::IEN: CH4ZCIEN Position */ +#define I2S_IEN_CH4ZCIEN_Msk (0x1ul << I2S_IEN_CH4ZCIEN_Pos) /*!< I2S_T::IEN: CH4ZCIEN Mask */ + +#define I2S_IEN_CH5ZCIEN_Pos (21) /*!< I2S_T::IEN: CH5ZCIEN Position */ +#define I2S_IEN_CH5ZCIEN_Msk (0x1ul << I2S_IEN_CH5ZCIEN_Pos) /*!< I2S_T::IEN: CH5ZCIEN Mask */ + +#define I2S_IEN_CH6ZCIEN_Pos (22) /*!< I2S_T::IEN: CH6ZCIEN Position */ +#define I2S_IEN_CH6ZCIEN_Msk (0x1ul << I2S_IEN_CH6ZCIEN_Pos) /*!< I2S_T::IEN: CH6ZCIEN Mask */ + +#define I2S_IEN_CH7ZCIEN_Pos (23) /*!< I2S_T::IEN: CH7ZCIEN Position */ +#define I2S_IEN_CH7ZCIEN_Msk (0x1ul << I2S_IEN_CH7ZCIEN_Pos) /*!< I2S_T::IEN: CH7ZCIEN Mask */ + +#define I2S_STATUS0_I2SINT_Pos (0) /*!< I2S_T::STATUS0: I2SINT Position */ +#define I2S_STATUS0_I2SINT_Msk (0x1ul << I2S_STATUS0_I2SINT_Pos) /*!< I2S_T::STATUS0: I2SINT Mask */ + +#define I2S_STATUS0_I2SRXINT_Pos (1) /*!< I2S_T::STATUS0: I2SRXINT Position */ +#define I2S_STATUS0_I2SRXINT_Msk (0x1ul << I2S_STATUS0_I2SRXINT_Pos) /*!< I2S_T::STATUS0: I2SRXINT Mask */ + +#define I2S_STATUS0_I2STXINT_Pos (2) /*!< I2S_T::STATUS0: I2STXINT Position */ +#define I2S_STATUS0_I2STXINT_Msk (0x1ul << I2S_STATUS0_I2STXINT_Pos) /*!< I2S_T::STATUS0: I2STXINT Mask */ + +#define I2S_STATUS0_DATACH_Pos (3) /*!< I2S_T::STATUS0: DATACH Position */ +#define I2S_STATUS0_DATACH_Msk (0x7ul << I2S_STATUS0_DATACH_Pos) /*!< I2S_T::STATUS0: DATACH Mask */ + +#define I2S_STATUS0_RXUDIF_Pos (8) /*!< I2S_T::STATUS0: RXUDIF Position */ +#define I2S_STATUS0_RXUDIF_Msk (0x1ul << I2S_STATUS0_RXUDIF_Pos) /*!< I2S_T::STATUS0: RXUDIF Mask */ + +#define I2S_STATUS0_RXOVIF_Pos (9) /*!< I2S_T::STATUS0: RXOVIF Position */ +#define I2S_STATUS0_RXOVIF_Msk (0x1ul << I2S_STATUS0_RXOVIF_Pos) /*!< I2S_T::STATUS0: RXOVIF Mask */ + +#define I2S_STATUS0_RXTHIF_Pos (10) /*!< I2S_T::STATUS0: RXTHIF Position */ +#define I2S_STATUS0_RXTHIF_Msk (0x1ul << I2S_STATUS0_RXTHIF_Pos) /*!< I2S_T::STATUS0: RXTHIF Mask */ + +#define I2S_STATUS0_RXFULL_Pos (11) /*!< I2S_T::STATUS0: RXFULL Position */ +#define I2S_STATUS0_RXFULL_Msk (0x1ul << I2S_STATUS0_RXFULL_Pos) /*!< I2S_T::STATUS0: RXFULL Mask */ + +#define I2S_STATUS0_RXEMPTY_Pos (12) /*!< I2S_T::STATUS0: RXEMPTY Position */ +#define I2S_STATUS0_RXEMPTY_Msk (0x1ul << I2S_STATUS0_RXEMPTY_Pos) /*!< I2S_T::STATUS0: RXEMPTY Mask */ + +#define I2S_STATUS0_TXUDIF_Pos (16) /*!< I2S_T::STATUS0: TXUDIF Position */ +#define I2S_STATUS0_TXUDIF_Msk (0x1ul << I2S_STATUS0_TXUDIF_Pos) /*!< I2S_T::STATUS0: TXUDIF Mask */ + +#define I2S_STATUS0_TXOVIF_Pos (17) /*!< I2S_T::STATUS0: TXOVIF Position */ +#define I2S_STATUS0_TXOVIF_Msk (0x1ul << I2S_STATUS0_TXOVIF_Pos) /*!< I2S_T::STATUS0: TXOVIF Mask */ + +#define I2S_STATUS0_TXTHIF_Pos (18) /*!< I2S_T::STATUS0: TXTHIF Position */ +#define I2S_STATUS0_TXTHIF_Msk (0x1ul << I2S_STATUS0_TXTHIF_Pos) /*!< I2S_T::STATUS0: TXTHIF Mask */ + +#define I2S_STATUS0_TXFULL_Pos (19) /*!< I2S_T::STATUS0: TXFULL Position */ +#define I2S_STATUS0_TXFULL_Msk (0x1ul << I2S_STATUS0_TXFULL_Pos) /*!< I2S_T::STATUS0: TXFULL Mask */ + +#define I2S_STATUS0_TXEMPTY_Pos (20) /*!< I2S_T::STATUS0: TXEMPTY Position */ +#define I2S_STATUS0_TXEMPTY_Msk (0x1ul << I2S_STATUS0_TXEMPTY_Pos) /*!< I2S_T::STATUS0: TXEMPTY Mask */ + +#define I2S_STATUS0_TXBUSY_Pos (21) /*!< I2S_T::STATUS0: TXBUSY Position */ +#define I2S_STATUS0_TXBUSY_Msk (0x1ul << I2S_STATUS0_TXBUSY_Pos) /*!< I2S_T::STATUS0: TXBUSY Mask */ + +#define I2S_TXFIFO_TXFIFO_Pos (0) /*!< I2S_T::TXFIFO: TXFIFO Position */ +#define I2S_TXFIFO_TXFIFO_Msk (0xfffffffful << I2S_TXFIFO_TXFIFO_Pos) /*!< I2S_T::TXFIFO: TXFIFO Mask */ + +#define I2S_RXFIFO_RXFIFO_Pos (0) /*!< I2S_T::RXFIFO: RXFIFO Position */ +#define I2S_RXFIFO_RXFIFO_Msk (0xfffffffful << I2S_RXFIFO_RXFIFO_Pos) /*!< I2S_T::RXFIFO: RXFIFO Mask */ + +#define I2S_CTL1_CH0ZCEN_Pos (0) /*!< I2S_T::CTL1: CH0ZCEN Position */ +#define I2S_CTL1_CH0ZCEN_Msk (0x1ul << I2S_CTL1_CH0ZCEN_Pos) /*!< I2S_T::CTL1: CH0ZCEN Mask */ + +#define I2S_CTL1_CH1ZCEN_Pos (1) /*!< I2S_T::CTL1: CH1ZCEN Position */ +#define I2S_CTL1_CH1ZCEN_Msk (0x1ul << I2S_CTL1_CH1ZCEN_Pos) /*!< I2S_T::CTL1: CH1ZCEN Mask */ + +#define I2S_CTL1_CH2ZCEN_Pos (2) /*!< I2S_T::CTL1: CH2ZCEN Position */ +#define I2S_CTL1_CH2ZCEN_Msk (0x1ul << I2S_CTL1_CH2ZCEN_Pos) /*!< I2S_T::CTL1: CH2ZCEN Mask */ + +#define I2S_CTL1_CH3ZCEN_Pos (3) /*!< I2S_T::CTL1: CH3ZCEN Position */ +#define I2S_CTL1_CH3ZCEN_Msk (0x1ul << I2S_CTL1_CH3ZCEN_Pos) /*!< I2S_T::CTL1: CH3ZCEN Mask */ + +#define I2S_CTL1_CH4ZCEN_Pos (4) /*!< I2S_T::CTL1: CH4ZCEN Position */ +#define I2S_CTL1_CH4ZCEN_Msk (0x1ul << I2S_CTL1_CH4ZCEN_Pos) /*!< I2S_T::CTL1: CH4ZCEN Mask */ + +#define I2S_CTL1_CH5ZCEN_Pos (5) /*!< I2S_T::CTL1: CH5ZCEN Position */ +#define I2S_CTL1_CH5ZCEN_Msk (0x1ul << I2S_CTL1_CH5ZCEN_Pos) /*!< I2S_T::CTL1: CH5ZCEN Mask */ + +#define I2S_CTL1_CH6ZCEN_Pos (6) /*!< I2S_T::CTL1: CH6ZCEN Position */ +#define I2S_CTL1_CH6ZCEN_Msk (0x1ul << I2S_CTL1_CH6ZCEN_Pos) /*!< I2S_T::CTL1: CH6ZCEN Mask */ + +#define I2S_CTL1_CH7ZCEN_Pos (7) /*!< I2S_T::CTL1: CH7ZCEN Position */ +#define I2S_CTL1_CH7ZCEN_Msk (0x1ul << I2S_CTL1_CH7ZCEN_Pos) /*!< I2S_T::CTL1: CH7ZCEN Mask */ + +#define I2S_CTL1_TXTH_Pos (8) /*!< I2S_T::CTL1: TXTH Position */ +#define I2S_CTL1_TXTH_Msk (0xful << I2S_CTL1_TXTH_Pos) /*!< I2S_T::CTL1: TXTH Mask */ + +#define I2S_CTL1_RXTH_Pos (16) /*!< I2S_T::CTL1: RXTH Position */ +#define I2S_CTL1_RXTH_Msk (0xful << I2S_CTL1_RXTH_Pos) /*!< I2S_T::CTL1: RXTH Mask */ + +#define I2S_CTL1_PBWIDTH_Pos (24) /*!< I2S_T::CTL1: PBWIDTH Position */ +#define I2S_CTL1_PBWIDTH_Msk (0x1ul << I2S_CTL1_PBWIDTH_Pos) /*!< I2S_T::CTL1: PBWIDTH Mask */ + +#define I2S_CTL1_PB16ORD_Pos (25) /*!< I2S_T::CTL1: PB16ORD Position */ +#define I2S_CTL1_PB16ORD_Msk (0x1ul << I2S_CTL1_PB16ORD_Pos) /*!< I2S_T::CTL1: PB16ORD Mask */ + +#define I2S_STATUS1_CH0ZCIF_Pos (0) /*!< I2S_T::STATUS1: CH0ZCIF Position */ +#define I2S_STATUS1_CH0ZCIF_Msk (0x1ul << I2S_STATUS1_CH0ZCIF_Pos) /*!< I2S_T::STATUS1: CH0ZCIF Mask */ + +#define I2S_STATUS1_CH1ZCIF_Pos (1) /*!< I2S_T::STATUS1: CH1ZCIF Position */ +#define I2S_STATUS1_CH1ZCIF_Msk (0x1ul << I2S_STATUS1_CH1ZCIF_Pos) /*!< I2S_T::STATUS1: CH1ZCIF Mask */ + +#define I2S_STATUS1_CH2ZCIF_Pos (2) /*!< I2S_T::STATUS1: CH2ZCIF Position */ +#define I2S_STATUS1_CH2ZCIF_Msk (0x1ul << I2S_STATUS1_CH2ZCIF_Pos) /*!< I2S_T::STATUS1: CH2ZCIF Mask */ + +#define I2S_STATUS1_CH3ZCIF_Pos (3) /*!< I2S_T::STATUS1: CH3ZCIF Position */ +#define I2S_STATUS1_CH3ZCIF_Msk (0x1ul << I2S_STATUS1_CH3ZCIF_Pos) /*!< I2S_T::STATUS1: CH3ZCIF Mask */ + +#define I2S_STATUS1_CH4ZCIF_Pos (4) /*!< I2S_T::STATUS1: CH4ZCIF Position */ +#define I2S_STATUS1_CH4ZCIF_Msk (0x1ul << I2S_STATUS1_CH4ZCIF_Pos) /*!< I2S_T::STATUS1: CH4ZCIF Mask */ + +#define I2S_STATUS1_CH5ZCIF_Pos (5) /*!< I2S_T::STATUS1: CH5ZCIF Position */ +#define I2S_STATUS1_CH5ZCIF_Msk (0x1ul << I2S_STATUS1_CH5ZCIF_Pos) /*!< I2S_T::STATUS1: CH5ZCIF Mask */ + +#define I2S_STATUS1_CH6ZCIF_Pos (6) /*!< I2S_T::STATUS1: CH6ZCIF Position */ +#define I2S_STATUS1_CH6ZCIF_Msk (0x1ul << I2S_STATUS1_CH6ZCIF_Pos) /*!< I2S_T::STATUS1: CH6ZCIF Mask */ + +#define I2S_STATUS1_CH7ZCIF_Pos (7) /*!< I2S_T::STATUS1: CH7ZCIF Position */ +#define I2S_STATUS1_CH7ZCIF_Msk (0x1ul << I2S_STATUS1_CH7ZCIF_Pos) /*!< I2S_T::STATUS1: CH7ZCIF Mask */ + +#define I2S_STATUS1_TXCNT_Pos (8) /*!< I2S_T::STATUS1: TXCNT Position */ +#define I2S_STATUS1_TXCNT_Msk (0x1ful << I2S_STATUS1_TXCNT_Pos) /*!< I2S_T::STATUS1: TXCNT Mask */ + +#define I2S_STATUS1_RXCNT_Pos (16) /*!< I2S_T::STATUS1: RXCNT Position */ +#define I2S_STATUS1_RXCNT_Msk (0x1ful << I2S_STATUS1_RXCNT_Pos) /*!< I2S_T::STATUS1: RXCNT Mask */ + +/**@}*/ /* I2S_CONST */ +/**@}*/ /* end of I2S register group */ +/**@}*/ /* end of REGISTER group */ + +#endif /* __I2S_REG_H__ */ diff --git a/Ubiquitous/XiZi/board/nuvoton-m2354/third_party_driver/include/Regs/keystore_reg.h b/Ubiquitous/XiZi/board/nuvoton-m2354/third_party_driver/include/Regs/keystore_reg.h new file mode 100644 index 0000000..f7d20ad --- /dev/null +++ b/Ubiquitous/XiZi/board/nuvoton-m2354/third_party_driver/include/Regs/keystore_reg.h @@ -0,0 +1,384 @@ +/**************************************************************************//** + * @file keystore_reg.h + * @version V1.00 + * @brief Key store register definition header file + * + * @copyright SPDX-License-Identifier: Apache-2.0 + * @copyright Copyright (C) 2020 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ +#ifndef __KEYSTORE_REG_H__ +#define __KEYSTORE_REG_H__ + + +/** @addtogroup REGISTER Control Register + + @{ + +*/ + + +/*---------------------- Key Store -------------------------*/ +/** + @addtogroup KS Key Store(KS) + Memory Mapped Structure for KS Controller + @{ +*/ + +typedef struct +{ + + + /** + * @var KS_T::CTL + * Offset: 0x00 Key Store Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |START |Key Store Start Control Bit + * | | |0 = No operation. + * | | |1 = Start the setted operation. + * |[3:1] |OPMODE |Key Store Operation Mode + * | | |000 = Read operation. + * | | |001 = Create operation. + * | | |010 = Erase one key operation (only for key is in SRAM). + * | | |011 = Erase all keys operation (only for SRAM and Flash). + * | | |100 = Revoke key operation. + * | | |101 = Data Remanence prevention opertation (only for SRAM). + * | | |Others = reserved. + * |[7] |CONT |Read/Write Key Continue Bit + * | | |0 = Read/Write key operation is not continuous to previous operation. + * | | |1 = Read/Write key operation is continuous to previous operation. + * |[8] |INIT |Key Store Initialization + * | | |User should to check BUSY(KS_STS[2]) is 0, and then write 1 to this bit and START(KS_CTL[0[), the Key Store will start to be initialized. + * | | |After KeyStore is initialized, INIT will be cleared. + * | | |Note: Before executing INIT, user must to checks KS(SYS_SRAMPC1) is 00. + * |[10] |SILENT |Silent Access Enable Bit + * | | |0 = Silent Access Disabled. + * | | |1 = Silent Access Enabled. + * |[11] |SCMB |Data Scramble Enable Bit + * | | |0 = Data Scramble Disabled. + * | | |1 = Data Scramble Enabled. + * |[15] |IEN |Key Store Interrupt Enable Bit + * | | |0 = Key Store Interrupt Disabled. + * | | |1 = Key Store Interrupt Enabled. + * @var KS_T::METADATA + * Offset: 0x04 Key Store Metadata Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |SEC |Secure Key Selection Bit + * | | |0 = Set key as the non-secure key. + * | | |1 = Set key as the secure key. + * |[1] |PRIV |Privilege Key Selection Bit + * | | |0 = Set key as the non-privilege key. + * | | |1 = Set key as the privilege key. + * |[2] |READABLE |Key Readable Control Bit + * | | |0 = key is un-readable. + * | | |1 = key is readable. + * |[3] |RVK |Key Revoke Control Bit + * | | |0 = Key current selected will not be changed. + * | | |1 = key current selected will be change to revoked state. + * |[4] |BS |Booting State Selection Bit + * | | |0 = Set key used at all state. + * | | |1 = Set key used at boot loader state 1 (BL1 state). + * |[12:8] |SIZE |Key Size Selection Bits + * | | |00000 = 128 bits. + * | | |00001 = 163 bits. + * | | |00010 = 192 bits. + * | | |00011 = 224 bits. + * | | |00100 = 233 bits. + * | | |00101 = 255 bits. + * | | |00110 = 256 bits. + * | | |00111 = 283 bits. + * | | |01000 = 384 bits. + * | | |01001 = 409 bits. + * | | |01010 = 512 bits. + * | | |01011 = 521 bits. + * | | |01100 = 571 bits. + * | | |10000 = 1024 bits. + * | | |10001 = 1536 bits. + * | | |10010 = 2048 bits. + * | | |10011 = 3072 bits. + * | | |10100 = 4096 bits. + * | | |Others = reserved. + * |[18:16] |OWNER |Key Owner Selection Bits + * | | |000 = Only for AES used. + * | | |001 = Only for HMAC engine used. + * | | |010 = Only for RSA engine exponential used (private key). + * | | |011 = Only for RSA engine middle data used. + * | | |100 = Only for ECC engine used. + * | | |101 = Only for CPU engine use. + * | | |Others = reserved. + * |[25:20] |NUMBER |Key Number + * | | |Before read or erase one key operation starts, user should write the key number to be operated + * | | |When create operation is finished, user can read these bits to get its key number. + * |[31:30] |DST |Key Location Selection Bits + * | | |00 = Key is in SRAM. + * | | |01 = Key is in Flash. + * | | |10 = Key is in OTP. + * | | |Others = reserved. + * @var KS_T::STS + * Offset: 0x08 Key Store Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |IF |Key Store Finish Interrupt Flag + * | | |This bit is cleared by writing 1 and it has no effect by writing 0. + * | | |0 = No Key Store interrupt. + * | | |1 = Key Store operation done interrupt. + * |[1] |EIF |Key Store Error Flag + * | | |This bit is cleared by writing 1 and it has no effect by writing 0. + * | | |0 = No Key Store error. + * | | |1 = Key Store error interrupt. + * |[2] |BUSY |Key Store Busy Flag (RO) + * | | |0 = KeyStore is idle or finished. + * | | |1 = KeyStore is busy. + * |[3] |SRAMFULL |Key Storage at SRAM Full Status Bit (RO) + * | | |0 = Key Storage at SRAM is not full. + * | | |1 = Key Storage at SRAM is full. + * |[4] |FLASHFULL |Key Storage at Flash Full Status Bit (RO) + * | | |0 = Key Storage at Flash is not full. + * | | |1 = Key Storage at Flash is full. + * |[7] |INITDONE |Key Store Initialization Done Status (RO) + * | | |0 = Key Store is un-initialized. + * | | |1 = Key Store is initialized. + * |[8] |RAMINV |Key Store SRAM Invert Status (RO) + * | | |0 = Key Store key in SRAM is normal. + * | | |1 = Key Store key in SRAM is inverted. + * @var KS_T::REMAIN + * Offset: 0x0C Key Store Remaining Space Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[12:0] |RRMNG |Key Store SRAM Remaining Space + * | | |The RRMNG shows the remaining byte count space for SRAM. + * |[27:16] |FRMNG |Key Store Flash Remaining Space + * | | |The FRMNG shows the remaining byte count space for Flash. + * @var KS_T::SCMBKEY + * Offset: 0x10-0x1C Key Store Scramble Key Word Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |SCMBKEY |Key Store Scramble Key + * | | |When SCMB(KS_CTL[]) is set to 1, user should write the scramble key in this register before new key stores in Key Store + * | | |If user does not write the scramble key in this register, the Key Store will use previous scramble key to execute data scramble function. + * @var KS_T::KEY + * Offset: 0x20-0x3C Key Store Entry Key Word Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |KEY |Key Data + * | | |The register will be cleared if the Key Store executes the write operation or CPU completes the reading key. + * @var KS_T::OTPSTS + * Offset: 0x40 Key Store OTP Keys Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |KEY0 |OTP Key 0 Used Status + * | | |0 = OTP key 0 is unused. + * | | |1 = OTP key 0 is used. + * | | |Note: If chip is changed to RMA stage, the existing key will be revoked after initialization. + * |[1] |KEY1 |OTP Key 1 Used Status + * | | |0 = OTP key 1 is unused. + * | | |1 = OTP key 1 is used. + * | | |Note: If chip is changed to RMA stage, the existing key will be revoked after initialization. + * |[2] |KEY2 |OTP Key 2 Used Status + * | | |0 = OTP key 2 is unused. + * | | |1 = OTP key 2 is used. + * | | |Note: If chip is changed to RMA stage, the existing key will be revoked after initialization. + * |[3] |KEY3 |OTP Key 3 Used Status + * | | |0 = OTP key 3 is unused. + * | | |1 = OTP key 3 is used. + * | | |Note: If chip is changed to RMA stage, the existing key will be revoked after initialization. + * |[4] |KEY4 |OTP Key 4 Used Status + * | | |0 = OTP key 4 is unused. + * | | |1 = OTP key 4 is used. + * | | |Note: If chip is changed to RMA stage, existing key will be revoked after initialization. + * |[5] |KEY5 |OTP Key 5 Used Status + * | | |0 = OTP key 5 is unused. + * | | |1 = OTP key 5 is used. + * | | |Note: If chip is changed to RMA stage, the existing key will be revoked after initialization. + * |[6] |KEY6 |OTP Key 6 Used Status + * | | |0 = OTP key 6 is unused. + * | | |1 = OTP key 6 is used. + * | | |Note: If chip is changed to RMA stage, the existing key will be revoked after initialization. + * |[7] |KEY7 |OTP Key 7 Used Status + * | | |0 = OTP key 7 is unused. + * | | |1 = OTP key 7 is used. + * | | |Note: If chip is changed to RMA stage, the existing key will be revoked after initialization. + * @var KS_T::REMKCNT + * Offset: 0x44 Key Store Remaining Key Count Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[5:0] |RRMKCNT |Key Store SRAM Remaining Key Count + * | | |The RRMKCNT shows the remaining key count for SRAM. + * |[21:16] |FRMKCNT |Key Store Flash Remaining Key Count + * | | |The FRMKCNT shows the remaining key count for Flash. + */ + __IO uint32_t CTL; /*!< [0x0000] Key Store Control Register */ + __IO uint32_t METADATA; /*!< [0x0004] Key Store Metadata Register */ + __IO uint32_t STS; /*!< [0x0008] Key Store Status Register */ + __I uint32_t REMAIN; /*!< [0x000c] Key Store Remaining Space Register */ + __IO uint32_t SCMBKEY[4]; /*!< [0x0010 ~ 0x001c] Key Store Scramble Key Word 0 Register */ + __IO uint32_t KEY[8]; /*!< [0x0020 ~ 0x003c] Key Store Entry Key Word 0 Register */ + __I uint32_t OTPSTS; /*!< [0x0040] Key Store OTP Keys Status Register */ + __I uint32_t REMKCNT; /*!< [0x0044] Key Store Remaining Key Count Register */ + +} KS_T; + +/** + @addtogroup KS_CONST KS Bit Field Definition + Constant Definitions for KS Controller + @{ +*/ + +#define KS_CTL_START_Pos (0) /*!< KS_T::CTL: START Position */ +#define KS_CTL_START_Msk (0x1ul << KS_CTL_START_Pos) /*!< KS_T::CTL: START Mask */ + +#define KS_CTL_OPMODE_Pos (1) /*!< KS_T::CTL: OPMODE Position */ +#define KS_CTL_OPMODE_Msk (0x7ul << KS_CTL_OPMODE_Pos) /*!< KS_T::CTL: OPMODE Mask */ + +#define KS_CTL_CONT_Pos (7) /*!< KS_T::CTL: CONT Position */ +#define KS_CTL_CONT_Msk (0x1ul << KS_CTL_CONT_Pos) /*!< KS_T::CTL: CONT Mask */ + +#define KS_CTL_INIT_Pos (8) /*!< KS_T::CTL: INIT Position */ +#define KS_CTL_INIT_Msk (0x1ul << KS_CTL_INIT_Pos) /*!< KS_T::CTL: INIT Mask */ + +#define KS_CTL_SILENT_Pos (10) /*!< KS_T::CTL: SILENT Position */ +#define KS_CTL_SILENT_Msk (0x1ul << KS_CTL_SILENT_Pos) /*!< KS_T::CTL: SILENT Mask */ + +#define KS_CTL_SCMB_Pos (11) /*!< KS_T::CTL: SCMB Position */ +#define KS_CTL_SCMB_Msk (0x1ul << KS_CTL_SCMB_Pos) /*!< KS_T::CTL: SCMB Mask */ + +#define KS_CTL_IEN_Pos (15) /*!< KS_T::CTL: IEN Position */ +#define KS_CTL_IEN_Msk (0x1ul << KS_CTL_IEN_Pos) /*!< KS_T::CTL: IEN Mask */ + +#define KS_METADATA_SEC_Pos (0) /*!< KS_T::METADATA: SEC Position */ +#define KS_METADATA_SEC_Msk (0x1ul << KS_METADATA_SEC_Pos) /*!< KS_T::METADATA: SEC Mask */ + +#define KS_METADATA_PRIV_Pos (1) /*!< KS_T::METADATA: PRIV Position */ +#define KS_METADATA_PRIV_Msk (0x1ul << KS_METADATA_PRIV_Pos) /*!< KS_T::METADATA: PRIV Mask */ + +#define KS_METADATA_READABLE_Pos (2) /*!< KS_T::METADATA: READABLE Position */ +#define KS_METADATA_READABLE_Msk (0x1ul << KS_METADATA_READABLE_Pos) /*!< KS_T::METADATA: READABLE Mask */ + +#define KS_METADATA_RVK_Pos (3) /*!< KS_T::METADATA: RVK Position */ +#define KS_METADATA_RVK_Msk (0x1ul << KS_METADATA_RVK_Pos) /*!< KS_T::METADATA: RVK Mask */ + +#define KS_METADATA_BS_Pos (4) /*!< KS_T::METADATA: BS Position */ +#define KS_METADATA_BS_Msk (0x1ul << KS_METADATA_BS_Pos) /*!< KS_T::METADATA: BS Mask */ + +#define KS_METADATA_SIZE_Pos (8) /*!< KS_T::METADATA: SIZE Position */ +#define KS_METADATA_SIZE_Msk (0x1ful << KS_METADATA_SIZE_Pos) /*!< KS_T::METADATA: SIZE Mask */ + +#define KS_METADATA_OWNER_Pos (16) /*!< KS_T::METADATA: OWNER Position */ +#define KS_METADATA_OWNER_Msk (0x7ul << KS_METADATA_OWNER_Pos) /*!< KS_T::METADATA: OWNER Mask */ + +#define KS_METADATA_NUMBER_Pos (20) /*!< KS_T::METADATA: NUMBER Position */ +#define KS_METADATA_NUMBER_Msk (0x3ful << KS_METADATA_NUMBER_Pos) /*!< KS_T::METADATA: NUMBER Mask */ + +#define KS_METADATA_DST_Pos (30) /*!< KS_T::METADATA: DST Position */ +#define KS_METADATA_DST_Msk (0x3ul << KS_METADATA_DST_Pos) /*!< KS_T::METADATA: DST Mask */ + +#define KS_STS_IF_Pos (0) /*!< KS_T::STS: IF Position */ +#define KS_STS_IF_Msk (0x1ul << KS_STS_IF_Pos) /*!< KS_T::STS: IF Mask */ + +#define KS_STS_EIF_Pos (1) /*!< KS_T::STS: EIF Position */ +#define KS_STS_EIF_Msk (0x1ul << KS_STS_EIF_Pos) /*!< KS_T::STS: EIF Mask */ + +#define KS_STS_BUSY_Pos (2) /*!< KS_T::STS: BUSY Position */ +#define KS_STS_BUSY_Msk (0x1ul << KS_STS_BUSY_Pos) /*!< KS_T::STS: BUSY Mask */ + +#define KS_STS_SRAMFULL_Pos (3) /*!< KS_T::STS: SRAMFULL Position */ +#define KS_STS_SRAMFULL_Msk (0x1ul << KS_STS_SRAMFULL_Pos) /*!< KS_T::STS: SRAMFULL Mask */ + +#define KS_STS_FLASHFULL_Pos (4) /*!< KS_T::STS: FLASHFULL Position */ +#define KS_STS_FLASHFULL_Msk (0x1ul << KS_STS_FLASHFULL_Pos) /*!< KS_T::STS: FLASHFULL Mask */ + +#define KS_STS_INITDONE_Pos (7) /*!< KS_T::STS: INITDONE Position */ +#define KS_STS_INITDONE_Msk (0x1ul << KS_STS_INITDONE_Pos) /*!< KS_T::STS: INITDONE Mask */ + +#define KS_STS_RAMINV_Pos (8) /*!< KS_T::STS: RAMINV Position */ +#define KS_STS_RAMINV_Msk (0x1ul << KS_STS_RAMINV_Pos) /*!< KS_T::STS: RAMINV Mask */ + +#define KS_REMAIN_RRMNG_Pos (0) /*!< KS_T::REMAIN: RRMNG Position */ +#define KS_REMAIN_RRMNG_Msk (0x1ffful << KS_REMAIN_RRMNG_Pos) /*!< KS_T::REMAIN: RRMNG Mask */ + +#define KS_REMAIN_FRMNG_Pos (16) /*!< KS_T::REMAIN: FRMNG Position */ +#define KS_REMAIN_FRMNG_Msk (0xffful << KS_REMAIN_FRMNG_Pos) /*!< KS_T::REMAIN: FRMNG Mask */ + +#define KS_SCMBKEY0_SCMBKEY_Pos (0) /*!< KS_T::SCMBKEY0: SCMBKEY Position */ +#define KS_SCMBKEY0_SCMBKEY_Msk (0xfffffffful << KS_SCMBKEY0_SCMBKEY_Pos) /*!< KS_T::SCMBKEY0: SCMBKEY Mask */ + +#define KS_SCMBKEY1_SCMBKEY_Pos (0) /*!< KS_T::SCMBKEY1: SCMBKEY Position */ +#define KS_SCMBKEY1_SCMBKEY_Msk (0xfffffffful << KS_SCMBKEY1_SCMBKEY_Pos) /*!< KS_T::SCMBKEY1: SCMBKEY Mask */ + +#define KS_SCMBKEY2_SCMBKEY_Pos (0) /*!< KS_T::SCMBKEY2: SCMBKEY Position */ +#define KS_SCMBKEY2_SCMBKEY_Msk (0xfffffffful << KS_SCMBKEY2_SCMBKEY_Pos) /*!< KS_T::SCMBKEY2: SCMBKEY Mask */ + +#define KS_SCMBKEY3_SCMBKEY_Pos (0) /*!< KS_T::SCMBKEY3: SCMBKEY Position */ +#define KS_SCMBKEY3_SCMBKEY_Msk (0xfffffffful << KS_SCMBKEY3_SCMBKEY_Pos) /*!< KS_T::SCMBKEY3: SCMBKEY Mask */ + +#define KS_KEY0_KEY_Pos (0) /*!< KS_T::KEY0: KEY Position */ +#define KS_KEY0_KEY_Msk (0xfffffffful << KS_KEY0_KEY_Pos) /*!< KS_T::KEY0: KEY Mask */ + +#define KS_KEY1_KEY_Pos (0) /*!< KS_T::KEY1: KEY Position */ +#define KS_KEY1_KEY_Msk (0xfffffffful << KS_KEY1_KEY_Pos) /*!< KS_T::KEY1: KEY Mask */ + +#define KS_KEY2_KEY_Pos (0) /*!< KS_T::KEY2: KEY Position */ +#define KS_KEY2_KEY_Msk (0xfffffffful << KS_KEY2_KEY_Pos) /*!< KS_T::KEY2: KEY Mask */ + +#define KS_KEY3_KEY_Pos (0) /*!< KS_T::KEY3: KEY Position */ +#define KS_KEY3_KEY_Msk (0xfffffffful << KS_KEY3_KEY_Pos) /*!< KS_T::KEY3: KEY Mask */ + +#define KS_KEY4_KEY_Pos (0) /*!< KS_T::KEY4: KEY Position */ +#define KS_KEY4_KEY_Msk (0xfffffffful << KS_KEY4_KEY_Pos) /*!< KS_T::KEY4: KEY Mask */ + +#define KS_KEY5_KEY_Pos (0) /*!< KS_T::KEY5: KEY Position */ +#define KS_KEY5_KEY_Msk (0xfffffffful << KS_KEY5_KEY_Pos) /*!< KS_T::KEY5: KEY Mask */ + +#define KS_KEY6_KEY_Pos (0) /*!< KS_T::KEY6: KEY Position */ +#define KS_KEY6_KEY_Msk (0xfffffffful << KS_KEY6_KEY_Pos) /*!< KS_T::KEY6: KEY Mask */ + +#define KS_KEY7_KEY_Pos (0) /*!< KS_T::KEY7: KEY Position */ +#define KS_KEY7_KEY_Msk (0xfffffffful << KS_KEY7_KEY_Pos) /*!< KS_T::KEY7: KEY Mask */ + +#define KS_OTPSTS_KEY0_Pos (0) /*!< KS_T::OTPSTS: KEY0 Position */ +#define KS_OTPSTS_KEY0_Msk (0x1ul << KS_OTPSTS_KEY0_Pos) /*!< KS_T::OTPSTS: KEY0 Mask */ + +#define KS_OTPSTS_KEY1_Pos (1) /*!< KS_T::OTPSTS: KEY1 Position */ +#define KS_OTPSTS_KEY1_Msk (0x1ul << KS_OTPSTS_KEY1_Pos) /*!< KS_T::OTPSTS: KEY1 Mask */ + +#define KS_OTPSTS_KEY2_Pos (2) /*!< KS_T::OTPSTS: KEY2 Position */ +#define KS_OTPSTS_KEY2_Msk (0x1ul << KS_OTPSTS_KEY2_Pos) /*!< KS_T::OTPSTS: KEY2 Mask */ + +#define KS_OTPSTS_KEY3_Pos (3) /*!< KS_T::OTPSTS: KEY3 Position */ +#define KS_OTPSTS_KEY3_Msk (0x1ul << KS_OTPSTS_KEY3_Pos) /*!< KS_T::OTPSTS: KEY3 Mask */ + +#define KS_OTPSTS_KEY4_Pos (4) /*!< KS_T::OTPSTS: KEY4 Position */ +#define KS_OTPSTS_KEY4_Msk (0x1ul << KS_OTPSTS_KEY4_Pos) /*!< KS_T::OTPSTS: KEY4 Mask */ + +#define KS_OTPSTS_KEY5_Pos (5) /*!< KS_T::OTPSTS: KEY5 Position */ +#define KS_OTPSTS_KEY5_Msk (0x1ul << KS_OTPSTS_KEY5_Pos) /*!< KS_T::OTPSTS: KEY5 Mask */ + +#define KS_OTPSTS_KEY6_Pos (6) /*!< KS_T::OTPSTS: KEY6 Position */ +#define KS_OTPSTS_KEY6_Msk (0x1ul << KS_OTPSTS_KEY6_Pos) /*!< KS_T::OTPSTS: KEY6 Mask */ + +#define KS_OTPSTS_KEY7_Pos (7) /*!< KS_T::OTPSTS: KEY7 Position */ +#define KS_OTPSTS_KEY7_Msk (0x1ul << KS_OTPSTS_KEY7_Pos) /*!< KS_T::OTPSTS: KEY7 Mask */ + +#define KS_REMKCNT_RRMKCNT_Pos (0) /*!< KS_T::REMKCNT: RRMKCNT Position */ +#define KS_REMKCNT_RRMKCNT_Msk (0x3ful << KS_REMKCNT_RRMKCNT_Pos) /*!< KS_T::REMKCNT: RRMKCNT Mask */ + +#define KS_REMKCNT_FRMKCNT_Pos (16) /*!< KS_T::REMKCNT: FRMKCNT Position */ +#define KS_REMKCNT_FRMKCNT_Msk (0x3ful << KS_REMKCNT_FRMKCNT_Pos) /*!< KS_T::REMKCNT: FRMKCNT Mask */ + + +/**@}*/ /* KS_CONST */ +/**@}*/ /* end of KS register group */ + + +/**@}*/ /* end of REGISTER group */ + +#endif /* __KEYSTORE_REG_H__ */ diff --git a/Ubiquitous/XiZi/board/nuvoton-m2354/third_party_driver/include/Regs/lcd_reg.h b/Ubiquitous/XiZi/board/nuvoton-m2354/third_party_driver/include/Regs/lcd_reg.h new file mode 100644 index 0000000..2198e86 --- /dev/null +++ b/Ubiquitous/XiZi/board/nuvoton-m2354/third_party_driver/include/Regs/lcd_reg.h @@ -0,0 +1,1050 @@ +/**************************************************************************//** + * @file lcd_reg.h + * @version V1.00 + * @brief LCD register definition header file + * + * @copyright SPDX-License-Identifier: Apache-2.0 + * @copyright Copyright (C) 2020 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ +#ifndef __LCD_REG_H__ +#define __LCD_REG_H__ + + +/** @addtogroup REGISTER Control Register + + @{ + +*/ + + +/*---------------------- Liquid-Crystal Display -------------------------*/ +/** + @addtogroup LCD Liquid-Crystal Display(LCD) + Memory Mapped Structure for LCD Controller + @{ +*/ + +typedef struct +{ + + + /** + * @var LCD_T::CTL + * Offset: 0x00 LCD Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |EN |LCD Display Enable Bit + * | | |0 = LCD display function Disabled + * | | |1 = LCD display function Enabled + * | | |Note 1: When software writes 1 to this bit, the LCD Controller needs some synchronizing time to completely enable the LCD display function. Before that, the read value of this bit is still 0. + * | | |Note 2: When software writes 0 to this bit, the LCD Controller needs some synchronizing time to completely disable the LCD display function. Before that, the read value of this bit is still 1. + * |[31] |SYNC |LCD Enable/Disable Synchronizing Indicator (Read Only) + * | | |When software writes 0/1 to EN bit (LCD_CTL[0]), the LCD Controller needs some synchronizing time to completely disable/enable the LCD display function. During this time, this bit keeps at 1. + * | | |0 = LCD display function is completely Disabled/Enabled + * | | |1 = LCD display function is not yet completely Disabled/Enabled + * | | |Note 1: The synchronizing time to enable LCD display function is not constant. It is between one and two cycles of LCD_CLK. + * | | |Note 2: The LCD display function cannot be disabled until the end of a frame. So the maximum synchronizing time to disable LCD display function could be as long as one frame time. + * @var LCD_T::PCTL + * Offset: 0x04 LCD Panel Control Registerr + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[1:0] |BIAS |LCD Bias Level Selection + * | | |This field is used to select the bias level. + * | | |0 = Reserved + * | | |1 = 1/2 Bias + * | | |2 = 1/3 Bias + * | | |3 = 1/4 Bias + * |[4:2] |DUTY |LCD Duty Ratio Selection + * | | |This field is used to select the duty ratio. + * | | |0 = 1/1 Duty + * | | |1 = 1/2 Duty + * | | |2 = 1/3 Duty + * | | |3 = 1/4 Duty + * | | |4 = 1/5 Duty + * | | |5 = 1/6 Duty + * | | |6 = 1/7 Duty + * | | |7 = 1/8 Duty + * |[5] |TYPE |LCD Waveform Type Selection + * | | |This bit is used to select the waveform type. + * | | |0 = Type A + * | | |1 = Type B + * |[6] |INV |LCD Waveform Inverse + * | | |This bit is used to set the inverse LCD waveform. + * | | |0 = COM/SEG waveform is normal + * | | |1 = COM/SEG waveform is inversed + * |[17:8] |FREQDIV |LCD Operating Frequency Divider + * | | |The field is used to divide LCD_CLK to generate the LCD operating frequency. + * | | |LCD Operating Frequency = (LCD_CLK Frequency) / (FRRQDIV + 1). + * | | |Note 1: FREQDIV can be set from 0 to 1023, therefore, the fastest LCD operating frequency is equal to LCD_CLK frequency, + * | | |and the lowest LCD operating frequency is equal to LCD_CLK frequency divided by 1024. + * | | |Note 2: LCD frame rate is + * | | |(LCD Operating Frequency) x (Duty Ratio) x 1/2 for type A waveform, and + * | | |(LCD Operating Frequency) x (Duty Ratio) for type B waveform. + * | | |Example: Assume LCD operating frequency is 1 kHz, duty ratio is 1/4, then the LCD frame rate is + * | | |1 kHz x (1/4) x (1/2) = 128 Hz for type A waveform, and + * | | |1 kHz x (1/4) = 256 Hz for type B waveform. + * |[20:18] |CPVSEL |LCD Operating Voltage (VLCD) Select (For Charge Pump Only) + * | | |This field is used to select the LCD operating voltage. + * | | |0 = 2.6 V + * | | |1 = 2.8 V + * | | |2 = 3.0 V + * | | |3 = 3.2 V + * | | |4 = 3.4 V + * | | |5 = 3.6 V + * | | |Others = (Reserved) + * | | |Note: This field is meaningful only if the VLCD source is the charge pump. Otherwise, this field is ignored. + * |[27:24] |CPVTUNE |LCD Operating Voltage (VLCD) Fine Tuning (For Charge Pump Only) + * | | |This field is used to fine tune the LCD operating voltage. + * | | |0 = No tuning + * | | |1 = decrease by 1 unit of voltage + * | | |2 = decrease by 2 unit of voltage + * | | |3 = decrease by 3 unit of voltage + * | | |4 = decrease by 4 unit of voltage + * | | |5 = decrease by 5 unit of voltage + * | | |6 = decrease by 6 unit of voltage + * | | |7 = decrease by 7 unit of voltage + * | | |8 = increase by 8 units of voltage + * | | |9 = increase by 7 units of voltage + * | | |10 = increase by 6 units of voltage + * | | |11 = increase by 5 units of voltage + * | | |12 = increase by 4 units of voltage + * | | |13 = increase by 3 units of voltage + * | | |14 = increase by 2 units of voltage + * | | |15 = increase by 1 unit of voltage + * | | |Note 1: A unit of voltage is about 0.03 V. + * | | |Note 2: This field is meaningful only if the VLCD source is the charge pump. Otherwise, this field is ignored. + * @var LCD_T::FCTL + * Offset: 0x08 LCD Frame Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |BLINK |LCD Blinking Enable Bit + * | | |0 = LCD blinking function Disabled + * | | |1 = LCD blinking function Enabled + * |[17:8] |FCV |Frame Counting Value + * | | |This field indicates the maximum value that the frame counter can reach. + * | | |Note 1: The frame counter automatically increases by 1 at the end of every frame. When the counter reaches FCV, it will recounts from 0 at the end of the next frame. + * | | |At this moment, the hardware sets a dedicated flag to 1, and triggers a dedicated interrupt if it is enabled. + * | | |Note 2: For type B waveform, the frame counter increases at the end of odd frames, not even frames. + * |[27:24] |NFTIME |Null Frame Time + * | | |This field is used to configure the length of a null frame. + * | | |One null frame time is (1 / LCD_FREQ) x NFTIME. + * | | |Note: All COM and SEG output voltages are 0 V during a null frame. + * |[31:28] |NFNUM |Number of Frames Inserted By One Null Frame + * | | |This field is used to specify the number of continuous normal frames inserted by one null frame. + * | | |The number of continuous normal frames is (NFNUM + 1) frames. + * @var LCD_T::DCTL + * Offset: 0x0C LCD Driving Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[1:0] |VSRC |LCD Operating Voltage (VLCD) Source + * | | |0 = VLCD Power + * | | |1 = AVDD Power + * | | |2 = Built-In Charge Pump + * | | |3 = None + * | | |Note: Whenever the LCD controller is disabled, all VLCD sources are automatically cut off. + * |[2] |RESMODE |Resistive Network Driving Mode + * | | |0 = Low-Drive Mode + * | | |1 = High-Drive Mode + * |[3] |BUFEN |Voltage Buffer Enable Bit + * | | |0 = Voltage Buffer Disabled + * | | |1 = Voltage Buffer Enabled + * | | |Note: When RESMODE = 1, the voltage buffers are automatically disabled. The setting of BUFEN bit is ignored. + * |[4] |PSVEN |Power Saving Mode Enable Bit + * | | |0 = Power Saving Mode Disabled + * | | |1 = Power Saving Mode Enabled + * | | |Note: when RESMODE = 0 and BUFEN = 0, the output drivers consumes the least driving current. In this case, the power saving mode is automatically disabled. The setting of PSVEN bit is ignored. + * |[5] |PSVREV |Power Saving Timing Reverse + * | | |When the timing is reversed, the original powe-saving period becomes no-power-saving, and the original no-power-saving period becomes power-saving. + * | | |0 = Timing of power saving is normal + * | | |1 = Timing of power saving is reversed + * |[11:8] |PSVT1 |Power Saving "Enable Time" Setting + * | | |The "Enable Time" of the power saving mode is calculated as "Enable Time" = 15.26 us x (PSVT1 + 1), + * | | |where 15.26 us is the half-cycle time of LCD_CLK, whose frequency is about 32 kHz. + * | | |PSVT1 can be set as 0, 1, 2, ..., 15, so the minimum "Enable Time" is about 15.26 us, and the maximum "Enable Time" is about 15.26 x 16 = 244.14 us. + * | | |Note: In the following two cases, the power saving mode is disabled. The setting of PSVT1 bits is ignored. + * | | |1. PSVEN = 0 + * | | |2. RESMODE = 0 and BUFEN = 0 + * |[15:12] |PSVT2 |Power Saving "On Time" Setting + * | | |The "On Time" of the power saving mode is calculated as "On Time" = 15.26 us x (PSVT2 + 1), + * | | |where 15.26 us is the half-cycle time of LCD_CLK, whose frequency is about 32 kHz. + * | | |PSVT2 can be set as 0, 1, 2, ..., 15, so the minimum "On Time" is about 15.26 us, and the maximum "On Time" is about 15.26 x 16 = 244.14 us. + * | | |Note: In the following two cases, the power saving mode is disabled. The setting of PSVT2 bits is ignored. + * | | |1. PSVEN = 0 + * |[28:16] |CTOTIME |Charging Timer Timeout Time + * | | |This field is used to specify the timeout value for the charging timer. When the charging timer reaches this timeout value, a status bit or an interrupt will occur. + * | | |The timeout is calculated by the following formula: Timeout = 30.52 us x (CTOTIME + 1), where 30.52 us is the cycle time of LCD_CLK, whose frequency is about 32 kHz. + * | | |CTOTIME can be set as 0, 1, 2, ..., 8191, so the minimum timeout is 30.52 us, and the maximum timeout is 30.52 x 8192 = 256 ms. + * @var LCD_T::PKGSEL + * Offset: 0x10 LCD Package Selection Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |PKG |Device Package Type Selection + * | | |0 = 128-Pin Package + * | | |1 = 64-Pin Package + * @var LCD_T::STS + * Offset: 0x14 LCD Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |FCEF |End of Frame-Counting Flag + * | | |This flag is automatically set by hardware at the end of a frame, and the frame counter value must be equal to FCV (LCD_FCTL[17:8], Frame Counting Value). + * | | |0 = End of Frame-Counting did not occur + * | | |1 = End of Frame-Counting occurred + * | | |Note 1: User can clear this bit by writing 1 to it. + * | | |Note 2: For type B waveform, this flag is set only at the end of an odd frame. + * |[1] |FEF |End of Frame Flag + * | | |This flag is automatically set by hardware at the end of a frame. + * | | |0 = End of Frame did not occur + * | | |1 = End of Frame occurred + * | | |Note 1: User can clear this bit by writing 1 to it. + * | | |Note 2: For type B waveform, this flag is set only at the end of an odd frame. + * |[2] |CTOF |Charging Timeout Flag + * | | |This flag is automatically set by hardware when the charging timer reaches the timeout value. + * | | |0 = Charging Timeout did not occur + * | | |1 = Charging Timeout occurred + * | | |Note: User can clear this bit by writing 1 to it. + * |[28:16] |CTIME |Charging Timer Value (Read Only) + * | | |The field contains the value of the charging timer. It records the charging time of the charge pump. + * | | |The charging timer stops counting when the charge pump stops charging or a timeout occurs. At this moment, the hardware dumps the current charging timer value into this field. + * | | |Charging Time = 30.52 us x (CTIME + 1), where 30.52 us is the cycle time of LCD_CLK, whose frequency is about 32 kHz. + * @var LCD_T::INTEN + * Offset: 0x18 LCD Interrupt Enable Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |FCEIEN |End of Frame-Counting Interrupt Enable Bit + * | | |An interrupt occurs at the end of a frame, and the frame counter value must be equal to FCV (LCD_FCTL[17:8], Frame Counting Value). + * | | |0 = End of Frame-Counting Interrupt Disabled + * | | |1 = End of Frame-Counting Interrupt Enabled + * | | |Note: For type B waveform, the interrupt occurs only at the end of an odd frame. + * |[1] |FEIEN |End of Frame Interrupt Enable Bit + * | | |An interrupt occurs at the end of a frame. + * | | |0 = End of Frame Interrupt Disabled + * | | |1 = End of Frame Interrupt Enabled + * | | |Note: For type B waveform, the interrupt occurs only at the end of an odd frame. + * |[2] |CTOIEN |Charging Timeout Interrupt Enable Bit + * | | |An interrupt occurs when the charging timer reaches the timeout value. + * | | |0 = Charging Timeout Interrupt Disabled + * | | |1 = Charging Timeout Interrupt Enabled + * @var LCD_T::DATA + * Offset: 0x20 LCD Segment Display Data Register 0 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[7:0] |DD0 |Display Data of Segments S, where S is (4 x N) + 0, and N is 0, 1, 2, ..., 10 + * | | |Each bit specifies the brightness of each pixel in a segment. + * | | |0 = The pixel is light + * | | |1 = The pixel is dark + * | | |Note 1: DD0 corresponds to SEG00, SEG04, SEG08, SEG12, SEG16, SEG20, SEG24, SEG28, SEG32, SEG36, and SEG40. + * | | |Note 2: Each bit, DD0[n], corresponds to COMn, n= 0 ~ 7. + * | | |[Example] Assume 1/4 Duty, and DD0 (= LCD_DATA07[7:0]) = 1001_0110, LCD_DATA07[7:0] corresponds to SEG28 (4 x 7 + 0 = 28), + * | | |the pixel SEG28-COM0 is light (LCD_DATA07[0] = 0), + * | | |the pixel SEG28-COM1 is dark (LCD_DATA07[1] = 1), + * | | |the pixel SEG28-COM2 is dark (LCD_DATA07[2] = 1), + * | | |the pixel SEG28-COM3 is light (LCD_DATA07[3] = 0), + * | | |LCD_DATA07[7:4] are ignored, since COMs from 4 to 7 are not used. + * |[15:8] |DD1 |Display Data of Segments S, where S is (4 x N) + 1, and N is 0, 1, 2, ..., 10 + * | | |Each bit specifies the brightness of each pixel in a segment. + * | | |0 = The pixel is light + * | | |1 = The pixel is dark + * | | |Note 1: DD1 corresponds to SEG01, SEG05, SEG09, SEG13, SEG17, SEG21, SEG25, SEG29, SEG33, SEG37, and SEG41. + * | | |Note 2: Each bit, DD1[n], corresponds to COMn, n= 0 ~ 7. + * | | |[Example] Assume 1/4 Duty, and DD1 (= LCD_DATA07[15:8]) = 1001_0110, LCD_DATA07[15:8] corresponds to SEG29 (4 x 7 + 1 = 29), + * | | |the pixel SEG29-COM0 is light (LCD_DATA07[8] = 0), + * | | |the pixel SEG29-COM1 is dark (LCD_DATA07[9] = 1), + * | | |the pixel SEG29-COM2 is dark (LCD_DATA07[10] = 1), + * | | |the pixel SEG29-COM3 is light (LCD_DATA07[11] = 0), + * | | |LCD_DATA07[15:12] are ignored, since COMs from 4 to 7 are not used. + * |[23:16] |DD2 |Display Data of Segments S, where S is (4 x N) + 2, and N is 0, 1, 2, ..., 10 + * | | |Each bit specifies the brightness of each pixel in a segment. + * | | |0 = The pixel is light + * | | |1 = The pixel is dark + * | | |Note 1: DD2 corresponds to SEG02, SEG06, SEG10, SEG14, SEG18, SEG22, SEG26, SEG30, SEG34, SEG38, and SEG42. + * | | |Note 2: Each bit, DD2[n], corresponds to COMn, n= 0 ~ 7. + * | | |[Example] Assume 1/4 Duty, and DD2 (= LCD_DATA07[23:16]) = 1001_0110, LCD_DATA07[23:16] corresponds to SEG31 (4 x 7 + 2 = 30), + * | | |the pixel SEG30-COM0 is light (LCD_DATA07[16] = 0), + * | | |the pixel SEG30-COM1 is dark (LCD_DATA07[17] = 1), + * | | |the pixel SEG30-COM2 is dark (LCD_DATA07[18] = 1), + * | | |the pixel SEG30-COM3 is light (LCD_DATA07[19] = 0), + * | | |LCD_DATA07[23:20] are ignored, since COMs from 4 to 7 are not used. + * |[31:24] |DD3 |Display Data of Segments S, where S is (4 x N) + 3, and N is 0, 1, 2, ..., 10 + * | | |Each bit specifies the brightness of each pixel in a segment. + * | | |0 = The pixel is light + * | | |1 = The pixel is dark + * | | |Note 1: DD3 corresponds to SEG03, SEG07, SEG11, SEG15, SEG19, SEG23, SEG27, SEG31, SEG35, SEG39, and SEG43. + * | | |Note 2: Each bit, DD3[n], corresponds to COMn, n= 0 ~ 7. + * | | |[Example] Assume 1/4 Duty, and DD3 (= LCD_DATA07[31:24]) = 1001_0110, LCD_DATA07[31:24] corresponds to SEG31 (4 x 7 + 3 = 31), + * | | |the pixel SEG31-COM0 is light (LCD_DATA07[24] = 0), + * | | |the pixel SEG31-COM1 is dark (LCD_DATA07[25] = 1), + * | | |the pixel SEG31-COM2 is dark (LCD_DATA07[26] = 1), + * | | |the pixel SEG31-COM3 is light (LCD_DATA07[27] = 0), + * | | |LCD_DATA07[31:28] are ignored, since COMs from 4 to 7 are not used. + * Offset: 0x24 LCD Segment Display Data Register 1 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[7:0] |DD0 |Display Data of Segments S, where S is (4 x N) + 0, and N is 0, 1, 2, ..., 10 + * | | |Each bit specifies the brightness of each pixel in a segment. + * | | |0 = The pixel is light + * | | |1 = The pixel is dark + * | | |Note 1: DD0 corresponds to SEG00, SEG04, SEG08, SEG12, SEG16, SEG20, SEG24, SEG28, SEG32, SEG36, and SEG40. + * | | |Note 2: Each bit, DD0[n], corresponds to COMn, n= 0 ~ 7. + * | | |[Example] Assume 1/4 Duty, and DD0 (= LCD_DATA07[7:0]) = 1001_0110, LCD_DATA07[7:0] corresponds to SEG28 (4 x 7 + 0 = 28), + * | | |the pixel SEG28-COM0 is light (LCD_DATA07[0] = 0), + * | | |the pixel SEG28-COM1 is dark (LCD_DATA07[1] = 1), + * | | |the pixel SEG28-COM2 is dark (LCD_DATA07[2] = 1), + * | | |the pixel SEG28-COM3 is light (LCD_DATA07[3] = 0), + * | | |LCD_DATA07[7:4] are ignored, since COMs from 4 to 7 are not used. + * |[15:8] |DD1 |Display Data of Segments S, where S is (4 x N) + 1, and N is 0, 1, 2, ..., 10 + * | | |Each bit specifies the brightness of each pixel in a segment. + * | | |0 = The pixel is light + * | | |1 = The pixel is dark + * | | |Note 1: DD1 corresponds to SEG01, SEG05, SEG09, SEG13, SEG17, SEG21, SEG25, SEG29, SEG33, SEG37, and SEG41. + * | | |Note 2: Each bit, DD1[n], corresponds to COMn, n= 0 ~ 7. + * | | |[Example] Assume 1/4 Duty, and DD1 (= LCD_DATA07[15:8]) = 1001_0110, LCD_DATA07[15:8] corresponds to SEG29 (4 x 7 + 1 = 29), + * | | |the pixel SEG29-COM0 is light (LCD_DATA07[8] = 0), + * | | |the pixel SEG29-COM1 is dark (LCD_DATA07[9] = 1), + * | | |the pixel SEG29-COM2 is dark (LCD_DATA07[10] = 1), + * | | |the pixel SEG29-COM3 is light (LCD_DATA07[11] = 0), + * | | |LCD_DATA07[15:12] are ignored, since COMs from 4 to 7 are not used. + * |[23:16] |DD2 |Display Data of Segments S, where S is (4 x N) + 2, and N is 0, 1, 2, ..., 10 + * | | |Each bit specifies the brightness of each pixel in a segment. + * | | |0 = The pixel is light + * | | |1 = The pixel is dark + * | | |Note 1: DD2 corresponds to SEG02, SEG06, SEG10, SEG14, SEG18, SEG22, SEG26, SEG30, SEG34, SEG38, and SEG42. + * | | |Note 2: Each bit, DD2[n], corresponds to COMn, n= 0 ~ 7. + * | | |[Example] Assume 1/4 Duty, and DD2 (= LCD_DATA07[23:16]) = 1001_0110, LCD_DATA07[23:16] corresponds to SEG31 (4 x 7 + 2 = 30), + * | | |the pixel SEG30-COM0 is light (LCD_DATA07[16] = 0), + * | | |the pixel SEG30-COM1 is dark (LCD_DATA07[17] = 1), + * | | |the pixel SEG30-COM2 is dark (LCD_DATA07[18] = 1), + * | | |the pixel SEG30-COM3 is light (LCD_DATA07[19] = 0), + * | | |LCD_DATA07[23:20] are ignored, since COMs from 4 to 7 are not used. + * |[31:24] |DD3 |Display Data of Segments S, where S is (4 x N) + 3, and N is 0, 1, 2, ..., 10 + * | | |Each bit specifies the brightness of each pixel in a segment. + * | | |0 = The pixel is light + * | | |1 = The pixel is dark + * | | |Note 1: DD3 corresponds to SEG03, SEG07, SEG11, SEG15, SEG19, SEG23, SEG27, SEG31, SEG35, SEG39, and SEG43. + * | | |Note 2: Each bit, DD3[n], corresponds to COMn, n= 0 ~ 7. + * | | |[Example] Assume 1/4 Duty, and DD3 (= LCD_DATA07[31:24]) = 1001_0110, LCD_DATA07[31:24] corresponds to SEG31 (4 x 7 + 3 = 31), + * | | |the pixel SEG31-COM0 is light (LCD_DATA07[24] = 0), + * | | |the pixel SEG31-COM1 is dark (LCD_DATA07[25] = 1), + * | | |the pixel SEG31-COM2 is dark (LCD_DATA07[26] = 1), + * | | |the pixel SEG31-COM3 is light (LCD_DATA07[27] = 0), + * | | |LCD_DATA07[31:28] are ignored, since COMs from 4 to 7 are not used. + * Offset: 0x28 LCD Segment Display Data Register 2 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[7:0] |DD0 |Display Data of Segments S, where S is (4 x N) + 0, and N is 0, 1, 2, ..., 10 + * | | |Each bit specifies the brightness of each pixel in a segment. + * | | |0 = The pixel is light + * | | |1 = The pixel is dark + * | | |Note 1: DD0 corresponds to SEG00, SEG04, SEG08, SEG12, SEG16, SEG20, SEG24, SEG28, SEG32, SEG36, and SEG40. + * | | |Note 2: Each bit, DD0[n], corresponds to COMn, n= 0 ~ 7. + * | | |[Example] Assume 1/4 Duty, and DD0 (= LCD_DATA07[7:0]) = 1001_0110, LCD_DATA07[7:0] corresponds to SEG28 (4 x 7 + 0 = 28), + * | | |the pixel SEG28-COM0 is light (LCD_DATA07[0] = 0), + * | | |the pixel SEG28-COM1 is dark (LCD_DATA07[1] = 1), + * | | |the pixel SEG28-COM2 is dark (LCD_DATA07[2] = 1), + * | | |the pixel SEG28-COM3 is light (LCD_DATA07[3] = 0), + * | | |LCD_DATA07[7:4] are ignored, since COMs from 4 to 7 are not used. + * |[15:8] |DD1 |Display Data of Segments S, where S is (4 x N) + 1, and N is 0, 1, 2, ..., 10 + * | | |Each bit specifies the brightness of each pixel in a segment. + * | | |0 = The pixel is light + * | | |1 = The pixel is dark + * | | |Note 1: DD1 corresponds to SEG01, SEG05, SEG09, SEG13, SEG17, SEG21, SEG25, SEG29, SEG33, SEG37, and SEG41. + * | | |Note 2: Each bit, DD1[n], corresponds to COMn, n= 0 ~ 7. + * | | |[Example] Assume 1/4 Duty, and DD1 (= LCD_DATA07[15:8]) = 1001_0110, LCD_DATA07[15:8] corresponds to SEG29 (4 x 7 + 1 = 29), + * | | |the pixel SEG29-COM0 is light (LCD_DATA07[8] = 0), + * | | |the pixel SEG29-COM1 is dark (LCD_DATA07[9] = 1), + * | | |the pixel SEG29-COM2 is dark (LCD_DATA07[10] = 1), + * | | |the pixel SEG29-COM3 is light (LCD_DATA07[11] = 0), + * | | |LCD_DATA07[15:12] are ignored, since COMs from 4 to 7 are not used. + * |[23:16] |DD2 |Display Data of Segments S, where S is (4 x N) + 2, and N is 0, 1, 2, ..., 10 + * | | |Each bit specifies the brightness of each pixel in a segment. + * | | |0 = The pixel is light + * | | |1 = The pixel is dark + * | | |Note 1: DD2 corresponds to SEG02, SEG06, SEG10, SEG14, SEG18, SEG22, SEG26, SEG30, SEG34, SEG38, and SEG42. + * | | |Note 2: Each bit, DD2[n], corresponds to COMn, n= 0 ~ 7. + * | | |[Example] Assume 1/4 Duty, and DD2 (= LCD_DATA07[23:16]) = 1001_0110, LCD_DATA07[23:16] corresponds to SEG31 (4 x 7 + 2 = 30), + * | | |the pixel SEG30-COM0 is light (LCD_DATA07[16] = 0), + * | | |the pixel SEG30-COM1 is dark (LCD_DATA07[17] = 1), + * | | |the pixel SEG30-COM2 is dark (LCD_DATA07[18] = 1), + * | | |the pixel SEG30-COM3 is light (LCD_DATA07[19] = 0), + * | | |LCD_DATA07[23:20] are ignored, since COMs from 4 to 7 are not used. + * |[31:24] |DD3 |Display Data of Segments S, where S is (4 x N) + 3, and N is 0, 1, 2, ..., 10 + * | | |Each bit specifies the brightness of each pixel in a segment. + * | | |0 = The pixel is light + * | | |1 = The pixel is dark + * | | |Note 1: DD3 corresponds to SEG03, SEG07, SEG11, SEG15, SEG19, SEG23, SEG27, SEG31, SEG35, SEG39, and SEG43. + * | | |Note 2: Each bit, DD3[n], corresponds to COMn, n= 0 ~ 7. + * | | |[Example] Assume 1/4 Duty, and DD3 (= LCD_DATA07[31:24]) = 1001_0110, LCD_DATA07[31:24] corresponds to SEG31 (4 x 7 + 3 = 31), + * | | |the pixel SEG31-COM0 is light (LCD_DATA07[24] = 0), + * | | |the pixel SEG31-COM1 is dark (LCD_DATA07[25] = 1), + * | | |the pixel SEG31-COM2 is dark (LCD_DATA07[26] = 1), + * | | |the pixel SEG31-COM3 is light (LCD_DATA07[27] = 0), + * | | |LCD_DATA07[31:28] are ignored, since COMs from 4 to 7 are not used. + * Offset: 0x2C LCD Segment Display Data Register 3 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[7:0] |DD0 |Display Data of Segments S, where S is (4 x N) + 0, and N is 0, 1, 2, ..., 10 + * | | |Each bit specifies the brightness of each pixel in a segment. + * | | |0 = The pixel is light + * | | |1 = The pixel is dark + * | | |Note 1: DD0 corresponds to SEG00, SEG04, SEG08, SEG12, SEG16, SEG20, SEG24, SEG28, SEG32, SEG36, and SEG40. + * | | |Note 2: Each bit, DD0[n], corresponds to COMn, n= 0 ~ 7. + * | | |[Example] Assume 1/4 Duty, and DD0 (= LCD_DATA07[7:0]) = 1001_0110, LCD_DATA07[7:0] corresponds to SEG28 (4 x 7 + 0 = 28), + * | | |the pixel SEG28-COM0 is light (LCD_DATA07[0] = 0), + * | | |the pixel SEG28-COM1 is dark (LCD_DATA07[1] = 1), + * | | |the pixel SEG28-COM2 is dark (LCD_DATA07[2] = 1), + * | | |the pixel SEG28-COM3 is light (LCD_DATA07[3] = 0), + * | | |LCD_DATA07[7:4] are ignored, since COMs from 4 to 7 are not used. + * |[15:8] |DD1 |Display Data of Segments S, where S is (4 x N) + 1, and N is 0, 1, 2, ..., 10 + * | | |Each bit specifies the brightness of each pixel in a segment. + * | | |0 = The pixel is light + * | | |1 = The pixel is dark + * | | |Note 1: DD1 corresponds to SEG01, SEG05, SEG09, SEG13, SEG17, SEG21, SEG25, SEG29, SEG33, SEG37, and SEG41. + * | | |Note 2: Each bit, DD1[n], corresponds to COMn, n= 0 ~ 7. + * | | |[Example] Assume 1/4 Duty, and DD1 (= LCD_DATA07[15:8]) = 1001_0110, LCD_DATA07[15:8] corresponds to SEG29 (4 x 7 + 1 = 29), + * | | |the pixel SEG29-COM0 is light (LCD_DATA07[8] = 0), + * | | |the pixel SEG29-COM1 is dark (LCD_DATA07[9] = 1), + * | | |the pixel SEG29-COM2 is dark (LCD_DATA07[10] = 1), + * | | |the pixel SEG29-COM3 is light (LCD_DATA07[11] = 0), + * | | |LCD_DATA07[15:12] are ignored, since COMs from 4 to 7 are not used. + * |[23:16] |DD2 |Display Data of Segments S, where S is (4 x N) + 2, and N is 0, 1, 2, ..., 10 + * | | |Each bit specifies the brightness of each pixel in a segment. + * | | |0 = The pixel is light + * | | |1 = The pixel is dark + * | | |Note 1: DD2 corresponds to SEG02, SEG06, SEG10, SEG14, SEG18, SEG22, SEG26, SEG30, SEG34, SEG38, and SEG42. + * | | |Note 2: Each bit, DD2[n], corresponds to COMn, n= 0 ~ 7. + * | | |[Example] Assume 1/4 Duty, and DD2 (= LCD_DATA07[23:16]) = 1001_0110, LCD_DATA07[23:16] corresponds to SEG31 (4 x 7 + 2 = 30), + * | | |the pixel SEG30-COM0 is light (LCD_DATA07[16] = 0), + * | | |the pixel SEG30-COM1 is dark (LCD_DATA07[17] = 1), + * | | |the pixel SEG30-COM2 is dark (LCD_DATA07[18] = 1), + * | | |the pixel SEG30-COM3 is light (LCD_DATA07[19] = 0), + * | | |LCD_DATA07[23:20] are ignored, since COMs from 4 to 7 are not used. + * |[31:24] |DD3 |Display Data of Segments S, where S is (4 x N) + 3, and N is 0, 1, 2, ..., 10 + * | | |Each bit specifies the brightness of each pixel in a segment. + * | | |0 = The pixel is light + * | | |1 = The pixel is dark + * | | |Note 1: DD3 corresponds to SEG03, SEG07, SEG11, SEG15, SEG19, SEG23, SEG27, SEG31, SEG35, SEG39, and SEG43. + * | | |Note 2: Each bit, DD3[n], corresponds to COMn, n= 0 ~ 7. + * | | |[Example] Assume 1/4 Duty, and DD3 (= LCD_DATA07[31:24]) = 1001_0110, LCD_DATA07[31:24] corresponds to SEG31 (4 x 7 + 3 = 31), + * | | |the pixel SEG31-COM0 is light (LCD_DATA07[24] = 0), + * | | |the pixel SEG31-COM1 is dark (LCD_DATA07[25] = 1), + * | | |the pixel SEG31-COM2 is dark (LCD_DATA07[26] = 1), + * | | |the pixel SEG31-COM3 is light (LCD_DATA07[27] = 0), + * | | |LCD_DATA07[31:28] are ignored, since COMs from 4 to 7 are not used. + * Offset: 0x30 LCD Segment Display Data Register 4 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[7:0] |DD0 |Display Data of Segments S, where S is (4 x N) + 0, and N is 0, 1, 2, ..., 10 + * | | |Each bit specifies the brightness of each pixel in a segment. + * | | |0 = The pixel is light + * | | |1 = The pixel is dark + * | | |Note 1: DD0 corresponds to SEG00, SEG04, SEG08, SEG12, SEG16, SEG20, SEG24, SEG28, SEG32, SEG36, and SEG40. + * | | |Note 2: Each bit, DD0[n], corresponds to COMn, n= 0 ~ 7. + * | | |[Example] Assume 1/4 Duty, and DD0 (= LCD_DATA07[7:0]) = 1001_0110, LCD_DATA07[7:0] corresponds to SEG28 (4 x 7 + 0 = 28), + * | | |the pixel SEG28-COM0 is light (LCD_DATA07[0] = 0), + * | | |the pixel SEG28-COM1 is dark (LCD_DATA07[1] = 1), + * | | |the pixel SEG28-COM2 is dark (LCD_DATA07[2] = 1), + * | | |the pixel SEG28-COM3 is light (LCD_DATA07[3] = 0), + * | | |LCD_DATA07[7:4] are ignored, since COMs from 4 to 7 are not used. + * |[15:8] |DD1 |Display Data of Segments S, where S is (4 x N) + 1, and N is 0, 1, 2, ..., 10 + * | | |Each bit specifies the brightness of each pixel in a segment. + * | | |0 = The pixel is light + * | | |1 = The pixel is dark + * | | |Note 1: DD1 corresponds to SEG01, SEG05, SEG09, SEG13, SEG17, SEG21, SEG25, SEG29, SEG33, SEG37, and SEG41. + * | | |Note 2: Each bit, DD1[n], corresponds to COMn, n= 0 ~ 7. + * | | |[Example] Assume 1/4 Duty, and DD1 (= LCD_DATA07[15:8]) = 1001_0110, LCD_DATA07[15:8] corresponds to SEG29 (4 x 7 + 1 = 29), + * | | |the pixel SEG29-COM0 is light (LCD_DATA07[8] = 0), + * | | |the pixel SEG29-COM1 is dark (LCD_DATA07[9] = 1), + * | | |the pixel SEG29-COM2 is dark (LCD_DATA07[10] = 1), + * | | |the pixel SEG29-COM3 is light (LCD_DATA07[11] = 0), + * | | |LCD_DATA07[15:12] are ignored, since COMs from 4 to 7 are not used. + * |[23:16] |DD2 |Display Data of Segments S, where S is (4 x N) + 2, and N is 0, 1, 2, ..., 10 + * | | |Each bit specifies the brightness of each pixel in a segment. + * | | |0 = The pixel is light + * | | |1 = The pixel is dark + * | | |Note 1: DD2 corresponds to SEG02, SEG06, SEG10, SEG14, SEG18, SEG22, SEG26, SEG30, SEG34, SEG38, and SEG42. + * | | |Note 2: Each bit, DD2[n], corresponds to COMn, n= 0 ~ 7. + * | | |[Example] Assume 1/4 Duty, and DD2 (= LCD_DATA07[23:16]) = 1001_0110, LCD_DATA07[23:16] corresponds to SEG31 (4 x 7 + 2 = 30), + * | | |the pixel SEG30-COM0 is light (LCD_DATA07[16] = 0), + * | | |the pixel SEG30-COM1 is dark (LCD_DATA07[17] = 1), + * | | |the pixel SEG30-COM2 is dark (LCD_DATA07[18] = 1), + * | | |the pixel SEG30-COM3 is light (LCD_DATA07[19] = 0), + * | | |LCD_DATA07[23:20] are ignored, since COMs from 4 to 7 are not used. + * |[31:24] |DD3 |Display Data of Segments S, where S is (4 x N) + 3, and N is 0, 1, 2, ..., 10 + * | | |Each bit specifies the brightness of each pixel in a segment. + * | | |0 = The pixel is light + * | | |1 = The pixel is dark + * | | |Note 1: DD3 corresponds to SEG03, SEG07, SEG11, SEG15, SEG19, SEG23, SEG27, SEG31, SEG35, SEG39, and SEG43. + * | | |Note 2: Each bit, DD3[n], corresponds to COMn, n= 0 ~ 7. + * | | |[Example] Assume 1/4 Duty, and DD3 (= LCD_DATA07[31:24]) = 1001_0110, LCD_DATA07[31:24] corresponds to SEG31 (4 x 7 + 3 = 31), + * | | |the pixel SEG31-COM0 is light (LCD_DATA07[24] = 0), + * | | |the pixel SEG31-COM1 is dark (LCD_DATA07[25] = 1), + * | | |the pixel SEG31-COM2 is dark (LCD_DATA07[26] = 1), + * | | |the pixel SEG31-COM3 is light (LCD_DATA07[27] = 0), + * | | |LCD_DATA07[31:28] are ignored, since COMs from 4 to 7 are not used. + * Offset: 0x34 LCD Segment Display Data Register 5 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[7:0] |DD0 |Display Data of Segments S, where S is (4 x N) + 0, and N is 0, 1, 2, ..., 10 + * | | |Each bit specifies the brightness of each pixel in a segment. + * | | |0 = The pixel is light + * | | |1 = The pixel is dark + * | | |Note 1: DD0 corresponds to SEG00, SEG04, SEG08, SEG12, SEG16, SEG20, SEG24, SEG28, SEG32, SEG36, and SEG40. + * | | |Note 2: Each bit, DD0[n], corresponds to COMn, n= 0 ~ 7. + * | | |[Example] Assume 1/4 Duty, and DD0 (= LCD_DATA07[7:0]) = 1001_0110, LCD_DATA07[7:0] corresponds to SEG28 (4 x 7 + 0 = 28), + * | | |the pixel SEG28-COM0 is light (LCD_DATA07[0] = 0), + * | | |the pixel SEG28-COM1 is dark (LCD_DATA07[1] = 1), + * | | |the pixel SEG28-COM2 is dark (LCD_DATA07[2] = 1), + * | | |the pixel SEG28-COM3 is light (LCD_DATA07[3] = 0), + * | | |LCD_DATA07[7:4] are ignored, since COMs from 4 to 7 are not used. + * |[15:8] |DD1 |Display Data of Segments S, where S is (4 x N) + 1, and N is 0, 1, 2, ..., 10 + * | | |Each bit specifies the brightness of each pixel in a segment. + * | | |0 = The pixel is light + * | | |1 = The pixel is dark + * | | |Note 1: DD1 corresponds to SEG01, SEG05, SEG09, SEG13, SEG17, SEG21, SEG25, SEG29, SEG33, SEG37, and SEG41. + * | | |Note 2: Each bit, DD1[n], corresponds to COMn, n= 0 ~ 7. + * | | |[Example] Assume 1/4 Duty, and DD1 (= LCD_DATA07[15:8]) = 1001_0110, LCD_DATA07[15:8] corresponds to SEG29 (4 x 7 + 1 = 29), + * | | |the pixel SEG29-COM0 is light (LCD_DATA07[8] = 0), + * | | |the pixel SEG29-COM1 is dark (LCD_DATA07[9] = 1), + * | | |the pixel SEG29-COM2 is dark (LCD_DATA07[10] = 1), + * | | |the pixel SEG29-COM3 is light (LCD_DATA07[11] = 0), + * | | |LCD_DATA07[15:12] are ignored, since COMs from 4 to 7 are not used. + * |[23:16] |DD2 |Display Data of Segments S, where S is (4 x N) + 2, and N is 0, 1, 2, ..., 10 + * | | |Each bit specifies the brightness of each pixel in a segment. + * | | |0 = The pixel is light + * | | |1 = The pixel is dark + * | | |Note 1: DD2 corresponds to SEG02, SEG06, SEG10, SEG14, SEG18, SEG22, SEG26, SEG30, SEG34, SEG38, and SEG42. + * | | |Note 2: Each bit, DD2[n], corresponds to COMn, n= 0 ~ 7. + * | | |[Example] Assume 1/4 Duty, and DD2 (= LCD_DATA07[23:16]) = 1001_0110, LCD_DATA07[23:16] corresponds to SEG31 (4 x 7 + 2 = 30), + * | | |the pixel SEG30-COM0 is light (LCD_DATA07[16] = 0), + * | | |the pixel SEG30-COM1 is dark (LCD_DATA07[17] = 1), + * | | |the pixel SEG30-COM2 is dark (LCD_DATA07[18] = 1), + * | | |the pixel SEG30-COM3 is light (LCD_DATA07[19] = 0), + * | | |LCD_DATA07[23:20] are ignored, since COMs from 4 to 7 are not used. + * |[31:24] |DD3 |Display Data of Segments S, where S is (4 x N) + 3, and N is 0, 1, 2, ..., 10 + * | | |Each bit specifies the brightness of each pixel in a segment. + * | | |0 = The pixel is light + * | | |1 = The pixel is dark + * | | |Note 1: DD3 corresponds to SEG03, SEG07, SEG11, SEG15, SEG19, SEG23, SEG27, SEG31, SEG35, SEG39, and SEG43. + * | | |Note 2: Each bit, DD3[n], corresponds to COMn, n= 0 ~ 7. + * | | |[Example] Assume 1/4 Duty, and DD3 (= LCD_DATA07[31:24]) = 1001_0110, LCD_DATA07[31:24] corresponds to SEG31 (4 x 7 + 3 = 31), + * | | |the pixel SEG31-COM0 is light (LCD_DATA07[24] = 0), + * | | |the pixel SEG31-COM1 is dark (LCD_DATA07[25] = 1), + * | | |the pixel SEG31-COM2 is dark (LCD_DATA07[26] = 1), + * | | |the pixel SEG31-COM3 is light (LCD_DATA07[27] = 0), + * | | |LCD_DATA07[31:28] are ignored, since COMs from 4 to 7 are not used. + * Offset: 0x38 LCD Segment Display Data Register 6 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[7:0] |DD0 |Display Data of Segments S, where S is (4 x N) + 0, and N is 0, 1, 2, ..., 10 + * | | |Each bit specifies the brightness of each pixel in a segment. + * | | |0 = The pixel is light + * | | |1 = The pixel is dark + * | | |Note 1: DD0 corresponds to SEG00, SEG04, SEG08, SEG12, SEG16, SEG20, SEG24, SEG28, SEG32, SEG36, and SEG40. + * | | |Note 2: Each bit, DD0[n], corresponds to COMn, n= 0 ~ 7. + * | | |[Example] Assume 1/4 Duty, and DD0 (= LCD_DATA07[7:0]) = 1001_0110, LCD_DATA07[7:0] corresponds to SEG28 (4 x 7 + 0 = 28), + * | | |the pixel SEG28-COM0 is light (LCD_DATA07[0] = 0), + * | | |the pixel SEG28-COM1 is dark (LCD_DATA07[1] = 1), + * | | |the pixel SEG28-COM2 is dark (LCD_DATA07[2] = 1), + * | | |the pixel SEG28-COM3 is light (LCD_DATA07[3] = 0), + * | | |LCD_DATA07[7:4] are ignored, since COMs from 4 to 7 are not used. + * |[15:8] |DD1 |Display Data of Segments S, where S is (4 x N) + 1, and N is 0, 1, 2, ..., 10 + * | | |Each bit specifies the brightness of each pixel in a segment. + * | | |0 = The pixel is light + * | | |1 = The pixel is dark + * | | |Note 1: DD1 corresponds to SEG01, SEG05, SEG09, SEG13, SEG17, SEG21, SEG25, SEG29, SEG33, SEG37, and SEG41. + * | | |Note 2: Each bit, DD1[n], corresponds to COMn, n= 0 ~ 7. + * | | |[Example] Assume 1/4 Duty, and DD1 (= LCD_DATA07[15:8]) = 1001_0110, LCD_DATA07[15:8] corresponds to SEG29 (4 x 7 + 1 = 29), + * | | |the pixel SEG29-COM0 is light (LCD_DATA07[8] = 0), + * | | |the pixel SEG29-COM1 is dark (LCD_DATA07[9] = 1), + * | | |the pixel SEG29-COM2 is dark (LCD_DATA07[10] = 1), + * | | |the pixel SEG29-COM3 is light (LCD_DATA07[11] = 0), + * | | |LCD_DATA07[15:12] are ignored, since COMs from 4 to 7 are not used. + * |[23:16] |DD2 |Display Data of Segments S, where S is (4 x N) + 2, and N is 0, 1, 2, ..., 10 + * | | |Each bit specifies the brightness of each pixel in a segment. + * | | |0 = The pixel is light + * | | |1 = The pixel is dark + * | | |Note 1: DD2 corresponds to SEG02, SEG06, SEG10, SEG14, SEG18, SEG22, SEG26, SEG30, SEG34, SEG38, and SEG42. + * | | |Note 2: Each bit, DD2[n], corresponds to COMn, n= 0 ~ 7. + * | | |[Example] Assume 1/4 Duty, and DD2 (= LCD_DATA07[23:16]) = 1001_0110, LCD_DATA07[23:16] corresponds to SEG31 (4 x 7 + 2 = 30), + * | | |the pixel SEG30-COM0 is light (LCD_DATA07[16] = 0), + * | | |the pixel SEG30-COM1 is dark (LCD_DATA07[17] = 1), + * | | |the pixel SEG30-COM2 is dark (LCD_DATA07[18] = 1), + * | | |the pixel SEG30-COM3 is light (LCD_DATA07[19] = 0), + * | | |LCD_DATA07[23:20] are ignored, since COMs from 4 to 7 are not used. + * |[31:24] |DD3 |Display Data of Segments S, where S is (4 x N) + 3, and N is 0, 1, 2, ..., 10 + * | | |Each bit specifies the brightness of each pixel in a segment. + * | | |0 = The pixel is light + * | | |1 = The pixel is dark + * | | |Note 1: DD3 corresponds to SEG03, SEG07, SEG11, SEG15, SEG19, SEG23, SEG27, SEG31, SEG35, SEG39, and SEG43. + * | | |Note 2: Each bit, DD3[n], corresponds to COMn, n= 0 ~ 7. + * | | |[Example] Assume 1/4 Duty, and DD3 (= LCD_DATA07[31:24]) = 1001_0110, LCD_DATA07[31:24] corresponds to SEG31 (4 x 7 + 3 = 31), + * | | |the pixel SEG31-COM0 is light (LCD_DATA07[24] = 0), + * | | |the pixel SEG31-COM1 is dark (LCD_DATA07[25] = 1), + * | | |the pixel SEG31-COM2 is dark (LCD_DATA07[26] = 1), + * | | |the pixel SEG31-COM3 is light (LCD_DATA07[27] = 0), + * | | |LCD_DATA07[31:28] are ignored, since COMs from 4 to 7 are not used. + * Offset: 0x3C LCD Segment Display Data Register 7 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[7:0] |DD0 |Display Data of Segments S, where S is (4 x N) + 0, and N is 0, 1, 2, ..., 10 + * | | |Each bit specifies the brightness of each pixel in a segment. + * | | |0 = The pixel is light + * | | |1 = The pixel is dark + * | | |Note 1: DD0 corresponds to SEG00, SEG04, SEG08, SEG12, SEG16, SEG20, SEG24, SEG28, SEG32, SEG36, and SEG40. + * | | |Note 2: Each bit, DD0[n], corresponds to COMn, n= 0 ~ 7. + * | | |[Example] Assume 1/4 Duty, and DD0 (= LCD_DATA07[7:0]) = 1001_0110, LCD_DATA07[7:0] corresponds to SEG28 (4 x 7 + 0 = 28), + * | | |the pixel SEG28-COM0 is light (LCD_DATA07[0] = 0), + * | | |the pixel SEG28-COM1 is dark (LCD_DATA07[1] = 1), + * | | |the pixel SEG28-COM2 is dark (LCD_DATA07[2] = 1), + * | | |the pixel SEG28-COM3 is light (LCD_DATA07[3] = 0), + * | | |LCD_DATA07[7:4] are ignored, since COMs from 4 to 7 are not used. + * |[15:8] |DD1 |Display Data of Segments S, where S is (4 x N) + 1, and N is 0, 1, 2, ..., 10 + * | | |Each bit specifies the brightness of each pixel in a segment. + * | | |0 = The pixel is light + * | | |1 = The pixel is dark + * | | |Note 1: DD1 corresponds to SEG01, SEG05, SEG09, SEG13, SEG17, SEG21, SEG25, SEG29, SEG33, SEG37, and SEG41. + * | | |Note 2: Each bit, DD1[n], corresponds to COMn, n= 0 ~ 7. + * | | |[Example] Assume 1/4 Duty, and DD1 (= LCD_DATA07[15:8]) = 1001_0110, LCD_DATA07[15:8] corresponds to SEG29 (4 x 7 + 1 = 29), + * | | |the pixel SEG29-COM0 is light (LCD_DATA07[8] = 0), + * | | |the pixel SEG29-COM1 is dark (LCD_DATA07[9] = 1), + * | | |the pixel SEG29-COM2 is dark (LCD_DATA07[10] = 1), + * | | |the pixel SEG29-COM3 is light (LCD_DATA07[11] = 0), + * | | |LCD_DATA07[15:12] are ignored, since COMs from 4 to 7 are not used. + * |[23:16] |DD2 |Display Data of Segments S, where S is (4 x N) + 2, and N is 0, 1, 2, ..., 10 + * | | |Each bit specifies the brightness of each pixel in a segment. + * | | |0 = The pixel is light + * | | |1 = The pixel is dark + * | | |Note 1: DD2 corresponds to SEG02, SEG06, SEG10, SEG14, SEG18, SEG22, SEG26, SEG30, SEG34, SEG38, and SEG42. + * | | |Note 2: Each bit, DD2[n], corresponds to COMn, n= 0 ~ 7. + * | | |[Example] Assume 1/4 Duty, and DD2 (= LCD_DATA07[23:16]) = 1001_0110, LCD_DATA07[23:16] corresponds to SEG31 (4 x 7 + 2 = 30), + * | | |the pixel SEG30-COM0 is light (LCD_DATA07[16] = 0), + * | | |the pixel SEG30-COM1 is dark (LCD_DATA07[17] = 1), + * | | |the pixel SEG30-COM2 is dark (LCD_DATA07[18] = 1), + * | | |the pixel SEG30-COM3 is light (LCD_DATA07[19] = 0), + * | | |LCD_DATA07[23:20] are ignored, since COMs from 4 to 7 are not used. + * |[31:24] |DD3 |Display Data of Segments S, where S is (4 x N) + 3, and N is 0, 1, 2, ..., 10 + * | | |Each bit specifies the brightness of each pixel in a segment. + * | | |0 = The pixel is light + * | | |1 = The pixel is dark + * | | |Note 1: DD3 corresponds to SEG03, SEG07, SEG11, SEG15, SEG19, SEG23, SEG27, SEG31, SEG35, SEG39, and SEG43. + * | | |Note 2: Each bit, DD3[n], corresponds to COMn, n= 0 ~ 7. + * | | |[Example] Assume 1/4 Duty, and DD3 (= LCD_DATA07[31:24]) = 1001_0110, LCD_DATA07[31:24] corresponds to SEG31 (4 x 7 + 3 = 31), + * | | |the pixel SEG31-COM0 is light (LCD_DATA07[24] = 0), + * | | |the pixel SEG31-COM1 is dark (LCD_DATA07[25] = 1), + * | | |the pixel SEG31-COM2 is dark (LCD_DATA07[26] = 1), + * | | |the pixel SEG31-COM3 is light (LCD_DATA07[27] = 0), + * | | |LCD_DATA07[31:28] are ignored, since COMs from 4 to 7 are not used. + * Offset: 0x40 LCD Segment Display Data Register 8 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[7:0] |DD0 |Display Data of Segments S, where S is (4 x N) + 0, and N is 0, 1, 2, ..., 10 + * | | |Each bit specifies the brightness of each pixel in a segment. + * | | |0 = The pixel is light + * | | |1 = The pixel is dark + * | | |Note 1: DD0 corresponds to SEG00, SEG04, SEG08, SEG12, SEG16, SEG20, SEG24, SEG28, SEG32, SEG36, and SEG40. + * | | |Note 2: Each bit, DD0[n], corresponds to COMn, n= 0 ~ 7. + * | | |[Example] Assume 1/4 Duty, and DD0 (= LCD_DATA07[7:0]) = 1001_0110, LCD_DATA07[7:0] corresponds to SEG28 (4 x 7 + 0 = 28), + * | | |the pixel SEG28-COM0 is light (LCD_DATA07[0] = 0), + * | | |the pixel SEG28-COM1 is dark (LCD_DATA07[1] = 1), + * | | |the pixel SEG28-COM2 is dark (LCD_DATA07[2] = 1), + * | | |the pixel SEG28-COM3 is light (LCD_DATA07[3] = 0), + * | | |LCD_DATA07[7:4] are ignored, since COMs from 4 to 7 are not used. + * |[15:8] |DD1 |Display Data of Segments S, where S is (4 x N) + 1, and N is 0, 1, 2, ..., 10 + * | | |Each bit specifies the brightness of each pixel in a segment. + * | | |0 = The pixel is light + * | | |1 = The pixel is dark + * | | |Note 1: DD1 corresponds to SEG01, SEG05, SEG09, SEG13, SEG17, SEG21, SEG25, SEG29, SEG33, SEG37, and SEG41. + * | | |Note 2: Each bit, DD1[n], corresponds to COMn, n= 0 ~ 7. + * | | |[Example] Assume 1/4 Duty, and DD1 (= LCD_DATA07[15:8]) = 1001_0110, LCD_DATA07[15:8] corresponds to SEG29 (4 x 7 + 1 = 29), + * | | |the pixel SEG29-COM0 is light (LCD_DATA07[8] = 0), + * | | |the pixel SEG29-COM1 is dark (LCD_DATA07[9] = 1), + * | | |the pixel SEG29-COM2 is dark (LCD_DATA07[10] = 1), + * | | |the pixel SEG29-COM3 is light (LCD_DATA07[11] = 0), + * | | |LCD_DATA07[15:12] are ignored, since COMs from 4 to 7 are not used. + * |[23:16] |DD2 |Display Data of Segments S, where S is (4 x N) + 2, and N is 0, 1, 2, ..., 10 + * | | |Each bit specifies the brightness of each pixel in a segment. + * | | |0 = The pixel is light + * | | |1 = The pixel is dark + * | | |Note 1: DD2 corresponds to SEG02, SEG06, SEG10, SEG14, SEG18, SEG22, SEG26, SEG30, SEG34, SEG38, and SEG42. + * | | |Note 2: Each bit, DD2[n], corresponds to COMn, n= 0 ~ 7. + * | | |[Example] Assume 1/4 Duty, and DD2 (= LCD_DATA07[23:16]) = 1001_0110, LCD_DATA07[23:16] corresponds to SEG31 (4 x 7 + 2 = 30), + * | | |the pixel SEG30-COM0 is light (LCD_DATA07[16] = 0), + * | | |the pixel SEG30-COM1 is dark (LCD_DATA07[17] = 1), + * | | |the pixel SEG30-COM2 is dark (LCD_DATA07[18] = 1), + * | | |the pixel SEG30-COM3 is light (LCD_DATA07[19] = 0), + * | | |LCD_DATA07[23:20] are ignored, since COMs from 4 to 7 are not used. + * |[31:24] |DD3 |Display Data of Segments S, where S is (4 x N) + 3, and N is 0, 1, 2, ..., 10 + * | | |Each bit specifies the brightness of each pixel in a segment. + * | | |0 = The pixel is light + * | | |1 = The pixel is dark + * | | |Note 1: DD3 corresponds to SEG03, SEG07, SEG11, SEG15, SEG19, SEG23, SEG27, SEG31, SEG35, SEG39, and SEG43. + * | | |Note 2: Each bit, DD3[n], corresponds to COMn, n= 0 ~ 7. + * | | |[Example] Assume 1/4 Duty, and DD3 (= LCD_DATA07[31:24]) = 1001_0110, LCD_DATA07[31:24] corresponds to SEG31 (4 x 7 + 3 = 31), + * | | |the pixel SEG31-COM0 is light (LCD_DATA07[24] = 0), + * | | |the pixel SEG31-COM1 is dark (LCD_DATA07[25] = 1), + * | | |the pixel SEG31-COM2 is dark (LCD_DATA07[26] = 1), + * | | |the pixel SEG31-COM3 is light (LCD_DATA07[27] = 0), + * | | |LCD_DATA07[31:28] are ignored, since COMs from 4 to 7 are not used. + * Offset: 0x44 LCD Segment Display Data Register 9 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[7:0] |DD0 |Display Data of Segments S, where S is (4 x N) + 0, and N is 0, 1, 2, ..., 10 + * | | |Each bit specifies the brightness of each pixel in a segment. + * | | |0 = The pixel is light + * | | |1 = The pixel is dark + * | | |Note 1: DD0 corresponds to SEG00, SEG04, SEG08, SEG12, SEG16, SEG20, SEG24, SEG28, SEG32, SEG36, and SEG40. + * | | |Note 2: Each bit, DD0[n], corresponds to COMn, n= 0 ~ 7. + * | | |[Example] Assume 1/4 Duty, and DD0 (= LCD_DATA07[7:0]) = 1001_0110, LCD_DATA07[7:0] corresponds to SEG28 (4 x 7 + 0 = 28), + * | | |the pixel SEG28-COM0 is light (LCD_DATA07[0] = 0), + * | | |the pixel SEG28-COM1 is dark (LCD_DATA07[1] = 1), + * | | |the pixel SEG28-COM2 is dark (LCD_DATA07[2] = 1), + * | | |the pixel SEG28-COM3 is light (LCD_DATA07[3] = 0), + * | | |LCD_DATA07[7:4] are ignored, since COMs from 4 to 7 are not used. + * |[15:8] |DD1 |Display Data of Segments S, where S is (4 x N) + 1, and N is 0, 1, 2, ..., 10 + * | | |Each bit specifies the brightness of each pixel in a segment. + * | | |0 = The pixel is light + * | | |1 = The pixel is dark + * | | |Note 1: DD1 corresponds to SEG01, SEG05, SEG09, SEG13, SEG17, SEG21, SEG25, SEG29, SEG33, SEG37, and SEG41. + * | | |Note 2: Each bit, DD1[n], corresponds to COMn, n= 0 ~ 7. + * | | |[Example] Assume 1/4 Duty, and DD1 (= LCD_DATA07[15:8]) = 1001_0110, LCD_DATA07[15:8] corresponds to SEG29 (4 x 7 + 1 = 29), + * | | |the pixel SEG29-COM0 is light (LCD_DATA07[8] = 0), + * | | |the pixel SEG29-COM1 is dark (LCD_DATA07[9] = 1), + * | | |the pixel SEG29-COM2 is dark (LCD_DATA07[10] = 1), + * | | |the pixel SEG29-COM3 is light (LCD_DATA07[11] = 0), + * | | |LCD_DATA07[15:12] are ignored, since COMs from 4 to 7 are not used. + * |[23:16] |DD2 |Display Data of Segments S, where S is (4 x N) + 2, and N is 0, 1, 2, ..., 10 + * | | |Each bit specifies the brightness of each pixel in a segment. + * | | |0 = The pixel is light + * | | |1 = The pixel is dark + * | | |Note 1: DD2 corresponds to SEG02, SEG06, SEG10, SEG14, SEG18, SEG22, SEG26, SEG30, SEG34, SEG38, and SEG42. + * | | |Note 2: Each bit, DD2[n], corresponds to COMn, n= 0 ~ 7. + * | | |[Example] Assume 1/4 Duty, and DD2 (= LCD_DATA07[23:16]) = 1001_0110, LCD_DATA07[23:16] corresponds to SEG31 (4 x 7 + 2 = 30), + * | | |the pixel SEG30-COM0 is light (LCD_DATA07[16] = 0), + * | | |the pixel SEG30-COM1 is dark (LCD_DATA07[17] = 1), + * | | |the pixel SEG30-COM2 is dark (LCD_DATA07[18] = 1), + * | | |the pixel SEG30-COM3 is light (LCD_DATA07[19] = 0), + * | | |LCD_DATA07[23:20] are ignored, since COMs from 4 to 7 are not used. + * |[31:24] |DD3 |Display Data of Segments S, where S is (4 x N) + 3, and N is 0, 1, 2, ..., 10 + * | | |Each bit specifies the brightness of each pixel in a segment. + * | | |0 = The pixel is light + * | | |1 = The pixel is dark + * | | |Note 1: DD3 corresponds to SEG03, SEG07, SEG11, SEG15, SEG19, SEG23, SEG27, SEG31, SEG35, SEG39, and SEG43. + * | | |Note 2: Each bit, DD3[n], corresponds to COMn, n= 0 ~ 7. + * | | |[Example] Assume 1/4 Duty, and DD3 (= LCD_DATA07[31:24]) = 1001_0110, LCD_DATA07[31:24] corresponds to SEG31 (4 x 7 + 3 = 31), + * | | |the pixel SEG31-COM0 is light (LCD_DATA07[24] = 0), + * | | |the pixel SEG31-COM1 is dark (LCD_DATA07[25] = 1), + * | | |the pixel SEG31-COM2 is dark (LCD_DATA07[26] = 1), + * | | |the pixel SEG31-COM3 is light (LCD_DATA07[27] = 0), + * | | |LCD_DATA07[31:28] are ignored, since COMs from 4 to 7 are not used. + * Offset: 0x48 LCD Segment Display Data Register 10 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[7:0] |DD0 |Display Data of Segments S, where S is (4 x N) + 0, and N is 0, 1, 2, ..., 10 + * | | |Each bit specifies the brightness of each pixel in a segment. + * | | |0 = The pixel is light + * | | |1 = The pixel is dark + * | | |Note 1: DD0 corresponds to SEG00, SEG04, SEG08, SEG12, SEG16, SEG20, SEG24, SEG28, SEG32, SEG36, and SEG40. + * | | |Note 2: Each bit, DD0[n], corresponds to COMn, n= 0 ~ 7. + * | | |[Example] Assume 1/4 Duty, and DD0 (= LCD_DATA07[7:0]) = 1001_0110, LCD_DATA07[7:0] corresponds to SEG28 (4 x 7 + 0 = 28), + * | | |the pixel SEG28-COM0 is light (LCD_DATA07[0] = 0), + * | | |the pixel SEG28-COM1 is dark (LCD_DATA07[1] = 1), + * | | |the pixel SEG28-COM2 is dark (LCD_DATA07[2] = 1), + * | | |the pixel SEG28-COM3 is light (LCD_DATA07[3] = 0), + * | | |LCD_DATA07[7:4] are ignored, since COMs from 4 to 7 are not used. + * |[15:8] |DD1 |Display Data of Segments S, where S is (4 x N) + 1, and N is 0, 1, 2, ..., 10 + * | | |Each bit specifies the brightness of each pixel in a segment. + * | | |0 = The pixel is light + * | | |1 = The pixel is dark + * | | |Note 1: DD1 corresponds to SEG01, SEG05, SEG09, SEG13, SEG17, SEG21, SEG25, SEG29, SEG33, SEG37, and SEG41. + * | | |Note 2: Each bit, DD1[n], corresponds to COMn, n= 0 ~ 7. + * | | |[Example] Assume 1/4 Duty, and DD1 (= LCD_DATA07[15:8]) = 1001_0110, LCD_DATA07[15:8] corresponds to SEG29 (4 x 7 + 1 = 29), + * | | |the pixel SEG29-COM0 is light (LCD_DATA07[8] = 0), + * | | |the pixel SEG29-COM1 is dark (LCD_DATA07[9] = 1), + * | | |the pixel SEG29-COM2 is dark (LCD_DATA07[10] = 1), + * | | |the pixel SEG29-COM3 is light (LCD_DATA07[11] = 0), + * | | |LCD_DATA07[15:12] are ignored, since COMs from 4 to 7 are not used. + * |[23:16] |DD2 |Display Data of Segments S, where S is (4 x N) + 2, and N is 0, 1, 2, ..., 10 + * | | |Each bit specifies the brightness of each pixel in a segment. + * | | |0 = The pixel is light + * | | |1 = The pixel is dark + * | | |Note 1: DD2 corresponds to SEG02, SEG06, SEG10, SEG14, SEG18, SEG22, SEG26, SEG30, SEG34, SEG38, and SEG42. + * | | |Note 2: Each bit, DD2[n], corresponds to COMn, n= 0 ~ 7. + * | | |[Example] Assume 1/4 Duty, and DD2 (= LCD_DATA07[23:16]) = 1001_0110, LCD_DATA07[23:16] corresponds to SEG31 (4 x 7 + 2 = 30), + * | | |the pixel SEG30-COM0 is light (LCD_DATA07[16] = 0), + * | | |the pixel SEG30-COM1 is dark (LCD_DATA07[17] = 1), + * | | |the pixel SEG30-COM2 is dark (LCD_DATA07[18] = 1), + * | | |the pixel SEG30-COM3 is light (LCD_DATA07[19] = 0), + * | | |LCD_DATA07[23:20] are ignored, since COMs from 4 to 7 are not used. + * |[31:24] |DD3 |Display Data of Segments S, where S is (4 x N) + 3, and N is 0, 1, 2, ..., 10 + * | | |Each bit specifies the brightness of each pixel in a segment. + * | | |0 = The pixel is light + * | | |1 = The pixel is dark + * | | |Note 1: DD3 corresponds to SEG03, SEG07, SEG11, SEG15, SEG19, SEG23, SEG27, SEG31, SEG35, SEG39, and SEG43. + * | | |Note 2: Each bit, DD3[n], corresponds to COMn, n= 0 ~ 7. + * | | |[Example] Assume 1/4 Duty, and DD3 (= LCD_DATA07[31:24]) = 1001_0110, LCD_DATA07[31:24] corresponds to SEG31 (4 x 7 + 3 = 31), + * | | |the pixel SEG31-COM0 is light (LCD_DATA07[24] = 0), + * | | |the pixel SEG31-COM1 is dark (LCD_DATA07[25] = 1), + * | | |the pixel SEG31-COM2 is dark (LCD_DATA07[26] = 1), + * | | |the pixel SEG31-COM3 is light (LCD_DATA07[27] = 0), + * | | |LCD_DATA07[31:28] are ignored, since COMs from 4 to 7 are not used. + */ + __IO uint32_t CTL; /*!< [0x0000] LCD Control Register */ + __IO uint32_t PCTL; /*!< [0x0004] LCD Panel Control Register */ + __IO uint32_t FCTL; /*!< [0x0008] LCD Frame Control Register */ + __IO uint32_t DCTL; /*!< [0x000C] LCD Driving Control Register */ + __IO uint32_t PKGSEL; /*!< [0x0010] LCD Package Selection Register */ + __IO uint32_t STS; /*!< [0x0014] LCD Status Register */ + __IO uint32_t INTEN; /*!< [0x0018] LCD Interrupt Enable Register */ + __I uint32_t RESERVED0; /*!< [0x001C] Reserved 0 */ + __IO uint32_t DATA[11]; /*!< [0x0020] ~ [0x0048] LCD Segment Display Data Register 0 ~ 10 */ + +} LCD_T; + +/** + @addtogroup LCD_CONST LCD Bit Field Definition + Constant Definitions for LCD Controller + @{ +*/ + +#define LCD_CTL_EN_Pos (0) /*!< LCD_T::CTL: EN Position */ +#define LCD_CTL_EN_Msk (0x1ul << LCD_CTL_EN_Pos) /*!< LCD_T::CTL: EN Mask */ + +#define LCD_CTL_SYNC_Pos (31) /*!< LCD_T::CTL: SYNC Position */ +#define LCD_CTL_SYNC_Msk (0x1ul << LCD_CTL_SYNC_Pos) /*!< LCD_T::CTL: SYNC Mask */ + +#define LCD_PCTL_BIAS_Pos (0) /*!< LCD_T::PCTL: BIAS Position */ +#define LCD_PCTL_BIAS_Msk (0x3ul << LCD_PCTL_BIAS_Pos) /*!< LCD_T::PCTL: BIAS Mask */ + +#define LCD_PCTL_DUTY_Pos (2) /*!< LCD_T::PCTL: DUTY Position */ +#define LCD_PCTL_DUTY_Msk (0x7ul << LCD_PCTL_DUTY_Pos) /*!< LCD_T::PCTL: DUTY Mask */ + +#define LCD_PCTL_TYPE_Pos (5) /*!< LCD_T::PCTL: TYPE Position */ +#define LCD_PCTL_TYPE_Msk (0x1ul << LCD_PCTL_TYPE_Pos) /*!< LCD_T::PCTL: TYPE Mask */ + +#define LCD_PCTL_INV_Pos (6) /*!< LCD_T::PCTL: INV Position */ +#define LCD_PCTL_INV_Msk (0x1ul << LCD_PCTL_INV_Pos) /*!< LCD_T::PCTL: INV Mask */ + +#define LCD_PCTL_FREQDIV_Pos (8) /*!< LCD_T::PCTL: FREQDIV Position */ +#define LCD_PCTL_FREQDIV_Msk (0x3fful << LCD_PCTL_FREQDIV_Pos) /*!< LCD_T::PCTL: FREQDIV Mask */ + +#define LCD_PCTL_CPVSEL_Pos (18) /*!< LCD_T::PCTL: CPVSEL Position */ +#define LCD_PCTL_CPVSEL_Msk (0x7ul << LCD_PCTL_CPVSEL_Pos) /*!< LCD_T::PCTL: CPVSEL Mask */ + +#define LCD_PCTL_CPVTUNE_Pos (24) /*!< LCD_T::PCTL: CPVTUNE Position */ +#define LCD_PCTL_CPVTUNE_Msk (0xful << LCD_PCTL_CPVTUNE_Pos) /*!< LCD_T::PCTL: CPVTUNE Mask */ + +#define LCD_FCTL_BLINK_Pos (0) /*!< LCD_T::FCTL: BLINK Position */ +#define LCD_FCTL_BLINK_Msk (0x1ul << LCD_FCTL_BLINK_Pos) /*!< LCD_T::FCTL: BLINK Mask */ + +#define LCD_FCTL_FCV_Pos (8) /*!< LCD_T::FCTL: FCV Position */ +#define LCD_FCTL_FCV_Msk (0x3fful << LCD_FCTL_FCV_Pos) /*!< LCD_T::FCTL: FCV Mask */ + +#define LCD_FCTL_NFTIME_Pos (24) /*!< LCD_T::FCTL: NFTIME Position */ +#define LCD_FCTL_NFTIME_Msk (0xful << LCD_FCTL_NFTIME_Pos) /*!< LCD_T::FCTL: NFTIME Mask */ + +#define LCD_FCTL_NFNUM_Pos (28) /*!< LCD_T::FCTL: NFNUM Position */ +#define LCD_FCTL_NFNUM_Msk (0xful << LCD_FCTL_NFNUM_Pos) /*!< LCD_T::FCTL: NFNUM Mask */ + +#define LCD_DCTL_VSRC_Pos (0) /*!< LCD_T::DCTL: VSRC Position */ +#define LCD_DCTL_VSRC_Msk (0x3ul << LCD_DCTL_VSRC_Pos) /*!< LCD_T::DCTL: VSRC Mask */ + +#define LCD_DCTL_RESMODE_Pos (2) /*!< LCD_T::DCTL: RESMODE Position */ +#define LCD_DCTL_RESMODE_Msk (0x1ul << LCD_DCTL_RESMODE_Pos) /*!< LCD_T::DCTL: RESMODE Mask */ + +#define LCD_DCTL_BUFEN_Pos (3) /*!< LCD_T::DCTL: BUFEN Position */ +#define LCD_DCTL_BUFEN_Msk (0x1ul << LCD_DCTL_BUFEN_Pos) /*!< LCD_T::DCTL: BUFEN Mask */ + +#define LCD_DCTL_PSVEN_Pos (4) /*!< LCD_T::DCTL: PSVEN Position */ +#define LCD_DCTL_PSVEN_Msk (0x1ul << LCD_DCTL_PSVEN_Pos) /*!< LCD_T::DCTL: PSVEN Mask */ + +#define LCD_DCTL_PSVREV_Pos (5) /*!< LCD_T::DCTL: PSVREV Position */ +#define LCD_DCTL_PSVREV_Msk (0x1ul << LCD_DCTL_PSVREV_Pos) /*!< LCD_T::DCTL: PSVREV Mask */ + +#define LCD_DCTL_PSVT1_Pos (8) /*!< LCD_T::DCTL: PSVT1 Position */ +#define LCD_DCTL_PSVT1_Msk (0xful << LCD_DCTL_PSVT1_Pos) /*!< LCD_T::DCTL: PSVT1 Mask */ + +#define LCD_DCTL_PSVT2_Pos (12) /*!< LCD_T::DCTL: PSVT2 Position */ +#define LCD_DCTL_PSVT2_Msk (0xful << LCD_DCTL_PSVT2_Pos) /*!< LCD_T::DCTL: PSVT2 Mask */ + +#define LCD_DCTL_CTOTIME_Pos (16) /*!< LCD_T::DCTL: CTOTIME Position */ +#define LCD_DCTL_CTOTIME_Msk (0x1ffful << LCD_DCTL_CTOTIME_Pos) /*!< LCD_T::DCTL: CTOTIME Mask */ + +#define LCD_PKGSEL_PKG_Pos (0) /*!< LCD_T::PKGSEL: PKG Position */ +#define LCD_PKGSEL_PKG_Msk (0x1ul << LCD_PKGSEL_PKG_Pos) /*!< LCD_T::PKGSEL: PKG Mask */ + +#define LCD_STS_FCEF_Pos (0) /*!< LCD_T::STS: FCEF Position */ +#define LCD_STS_FCEF_Msk (0x1ul << LCD_STS_FCEF_Pos) /*!< LCD_T::STS: FCEF Mask */ + +#define LCD_STS_FEF_Pos (1) /*!< LCD_T::STS: FEF Position */ +#define LCD_STS_FEF_Msk (0x1ul << LCD_STS_FEF_Pos) /*!< LCD_T::STS: FEF Mask */ + +#define LCD_STS_CTOF_Pos (2) /*!< LCD_T::STS: CTOF Position */ +#define LCD_STS_CTOF_Msk (0x1ul << LCD_STS_CTOF_Pos) /*!< LCD_T::STS: CTOF Mask */ + +#define LCD_STS_CTIME_Pos (16) /*!< LCD_T::STS: CTIME Position */ +#define LCD_STS_CTIME_Msk (0x1ffful << LCD_STS_CTIME_Pos) /*!< LCD_T::STS: CTIME Mask */ + +#define LCD_INTEN_FCEIEN_Pos (0) /*!< LCD_T::INTEN: FCEIEN Position */ +#define LCD_INTEN_FCEIEN_Msk (0x1ul << LCD_INTEN_FCEIEN_Pos) /*!< LCD_T::INTEN: FCEIEN Mask */ + +#define LCD_INTEN_FEIEN_Pos (1) /*!< LCD_T::INTEN: FEIEN Position */ +#define LCD_INTEN_FEIEN_Msk (0x1ul << LCD_INTEN_FEIEN_Pos) /*!< LCD_T::INTEN: FEIEN Mask */ + +#define LCD_INTEN_CTOIEN_Pos (2) /*!< LCD_T::INTEN: CYOIEN Position */ +#define LCD_INTEN_CTOIEN_Msk (0x1ul << LCD_INTEN_CTOIEN_Pos) /*!< LCD_T::INTEN: CTOIEN Mask */ + +#define LCD_DATA00_DD0_Pos (0) /*!< LCD_T::DATA00: DD0 Position */ +#define LCD_DATA00_DD0_Msk (0xfful << LCD_DATA00_DD0_Pos) /*!< LCD_T::DATA00: DD0 Mask */ + +#define LCD_DATA00_DD1_Pos (8) /*!< LCD_T::DATA00: DD1 Position */ +#define LCD_DATA00_DD1_Msk (0xfful << LCD_DATA00_DD1_Pos) /*!< LCD_T::DATA00: DD1 Mask */ + +#define LCD_DATA00_DD2_Pos (16) /*!< LCD_T::DATA00: DD2 Position */ +#define LCD_DATA00_DD2_Msk (0xfful << LCD_DATA00_DD2_Pos) /*!< LCD_T::DATA00: DD2 Mask */ + +#define LCD_DATA00_DD3_Pos (24) /*!< LCD_T::DATA00: DD3 Position */ +#define LCD_DATA00_DD3_Msk (0xfful << LCD_DATA00_DD3_Pos) /*!< LCD_T::DATA00: DD3 Mask */ + +#define LCD_DATA01_DD0_Pos (0) /*!< LCD_T::DATA01: DD0 Position */ +#define LCD_DATA01_DD0_Msk (0xfful << LCD_DATA01_DD0_Pos) /*!< LCD_T::DATA01: DD0 Mask */ + +#define LCD_DATA01_DD1_Pos (8) /*!< LCD_T::DATA01: DD1 Position */ +#define LCD_DATA01_DD1_Msk (0xfful << LCD_DATA01_DD1_Pos) /*!< LCD_T::DATA01: DD1 Mask */ + +#define LCD_DATA01_DD2_Pos (16) /*!< LCD_T::DATA01: DD2 Position */ +#define LCD_DATA01_DD2_Msk (0xfful << LCD_DATA01_DD2_Pos) /*!< LCD_T::DATA01: DD2 Mask */ + +#define LCD_DATA01_DD3_Pos (24) /*!< LCD_T::DATA01: DD3 Position */ +#define LCD_DATA01_DD3_Msk (0xfful << LCD_DATA01_DD3_Pos) /*!< LCD_T::DATA01: DD3 Mask */ + +#define LCD_DATA02_DD0_Pos (0) /*!< LCD_T::DATA02: DD0 Position */ +#define LCD_DATA02_DD0_Msk (0xfful << LCD_DATA02_DD0_Pos) /*!< LCD_T::DATA02: DD0 Mask */ + +#define LCD_DATA02_DD1_Pos (8) /*!< LCD_T::DATA02: DD1 Position */ +#define LCD_DATA02_DD1_Msk (0xfful << LCD_DATA02_DD1_Pos) /*!< LCD_T::DATA02: DD1 Mask */ + +#define LCD_DATA02_DD2_Pos (16) /*!< LCD_T::DATA02: DD2 Position */ +#define LCD_DATA02_DD2_Msk (0xfful << LCD_DATA02_DD2_Pos) /*!< LCD_T::DATA02: DD2 Mask */ + +#define LCD_DATA02_DD3_Pos (24) /*!< LCD_T::DATA02: DD3 Position */ +#define LCD_DATA02_DD3_Msk (0xfful << LCD_DATA02_DD3_Pos) /*!< LCD_T::DATA02: DD3 Mask */ + +#define LCD_DATA03_DD0_Pos (0) /*!< LCD_T::DATA03: DD0 Position */ +#define LCD_DATA03_DD0_Msk (0xfful << LCD_DATA03_DD0_Pos) /*!< LCD_T::DATA03: DD0 Mask */ + +#define LCD_DATA03_DD1_Pos (8) /*!< LCD_T::DATA03: DD1 Position */ +#define LCD_DATA03_DD1_Msk (0xfful << LCD_DATA03_DD1_Pos) /*!< LCD_T::DATA03: DD1 Mask */ + +#define LCD_DATA03_DD2_Pos (16) /*!< LCD_T::DATA03: DD2 Position */ +#define LCD_DATA03_DD2_Msk (0xfful << LCD_DATA03_DD2_Pos) /*!< LCD_T::DATA03: DD2 Mask */ + +#define LCD_DATA03_DD3_Pos (24) /*!< LCD_T::DATA03: DD3 Position */ +#define LCD_DATA03_DD3_Msk (0xfful << LCD_DATA03_DD3_Pos) /*!< LCD_T::DATA03: DD3 Mask */ + +#define LCD_DATA04_DD0_Pos (0) /*!< LCD_T::DATA04: DD0 Position */ +#define LCD_DATA04_DD0_Msk (0xfful << LCD_DATA04_DD0_Pos) /*!< LCD_T::DATA04: DD0 Mask */ + +#define LCD_DATA04_DD1_Pos (8) /*!< LCD_T::DATA04: DD1 Position */ +#define LCD_DATA04_DD1_Msk (0xfful << LCD_DATA04_DD1_Pos) /*!< LCD_T::DATA04: DD1 Mask */ + +#define LCD_DATA04_DD2_Pos (16) /*!< LCD_T::DATA04: DD2 Position */ +#define LCD_DATA04_DD2_Msk (0xfful << LCD_DATA04_DD2_Pos) /*!< LCD_T::DATA04: DD2 Mask */ + +#define LCD_DATA04_DD3_Pos (24) /*!< LCD_T::DATA04: DD3 Position */ +#define LCD_DATA04_DD3_Msk (0xfful << LCD_DATA04_DD3_Pos) /*!< LCD_T::DATA04: DD3 Mask */ + +#define LCD_DATA05_DD0_Pos (0) /*!< LCD_T::DATA05: DD0 Position */ +#define LCD_DATA05_DD0_Msk (0xfful << LCD_DATA05_DD0_Pos) /*!< LCD_T::DATA05: DD0 Mask */ + +#define LCD_DATA05_DD1_Pos (8) /*!< LCD_T::DATA05: DD1 Position */ +#define LCD_DATA05_DD1_Msk (0xfful << LCD_DATA05_DD1_Pos) /*!< LCD_T::DATA05: DD1 Mask */ + +#define LCD_DATA05_DD2_Pos (16) /*!< LCD_T::DATA05: DD2 Position */ +#define LCD_DATA05_DD2_Msk (0xfful << LCD_DATA05_DD2_Pos) /*!< LCD_T::DATA05: DD2 Mask */ + +#define LCD_DATA05_DD3_Pos (24) /*!< LCD_T::DATA05: DD3 Position */ +#define LCD_DATA05_DD3_Msk (0xfful << LCD_DATA05_DD3_Pos) /*!< LCD_T::DATA05: DD3 Mask */ + +#define LCD_DATA06_DD0_Pos (0) /*!< LCD_T::DATA06: DD0 Position */ +#define LCD_DATA06_DD0_Msk (0xfful << LCD_DATA06_DD0_Pos) /*!< LCD_T::DATA06: DD0 Mask */ + +#define LCD_DATA06_DD1_Pos (8) /*!< LCD_T::DATA06: DD1 Position */ +#define LCD_DATA06_DD1_Msk (0xfful << LCD_DATA06_DD1_Pos) /*!< LCD_T::DATA06: DD1 Mask */ + +#define LCD_DATA06_DD2_Pos (16) /*!< LCD_T::DATA06: DD2 Position */ +#define LCD_DATA06_DD2_Msk (0xfful << LCD_DATA06_DD2_Pos) /*!< LCD_T::DATA06: DD2 Mask */ + +#define LCD_DATA06_DD3_Pos (24) /*!< LCD_T::DATA06: DD3 Position */ +#define LCD_DATA06_DD3_Msk (0xfful << LCD_DATA06_DD3_Pos) /*!< LCD_T::DATA06: DD3 Mask */ + +#define LCD_DATA07_DD0_Pos (0) /*!< LCD_T::DATA07: DD0 Position */ +#define LCD_DATA07_DD0_Msk (0xfful << LCD_DATA07_DD0_Pos) /*!< LCD_T::DATA07: DD0 Mask */ + +#define LCD_DATA07_DD1_Pos (8) /*!< LCD_T::DATA07: DD1 Position */ +#define LCD_DATA07_DD1_Msk (0xfful << LCD_DATA07_DD1_Pos) /*!< LCD_T::DATA07: DD1 Mask */ + +#define LCD_DATA07_DD2_Pos (16) /*!< LCD_T::DATA07: DD2 Position */ +#define LCD_DATA07_DD2_Msk (0xfful << LCD_DATA07_DD2_Pos) /*!< LCD_T::DATA07: DD2 Mask */ + +#define LCD_DATA07_DD3_Pos (24) /*!< LCD_T::DATA07: DD3 Position */ +#define LCD_DATA07_DD3_Msk (0xfful << LCD_DATA07_DD3_Pos) /*!< LCD_T::DATA07: DD3 Mask */ + +#define LCD_DATA08_DD0_Pos (0) /*!< LCD_T::DATA08: DD0 Position */ +#define LCD_DATA08_DD0_Msk (0xfful << LCD_DATA08_DD0_Pos) /*!< LCD_T::DATA08: DD0 Mask */ + +#define LCD_DATA08_DD1_Pos (8) /*!< LCD_T::DATA08: DD1 Position */ +#define LCD_DATA08_DD1_Msk (0xfful << LCD_DATA08_DD1_Pos) /*!< LCD_T::DATA08: DD1 Mask */ + +#define LCD_DATA08_DD2_Pos (16) /*!< LCD_T::DATA08: DD2 Position */ +#define LCD_DATA08_DD2_Msk (0xfful << LCD_DATA08_DD2_Pos) /*!< LCD_T::DATA08: DD2 Mask */ + +#define LCD_DATA08_DD3_Pos (24) /*!< LCD_T::DATA08: DD3 Position */ +#define LCD_DATA08_DD3_Msk (0xfful << LCD_DATA08_DD3_Pos) /*!< LCD_T::DATA08: DD3 Mask */ + +#define LCD_DATA09_DD0_Pos (0) /*!< LCD_T::DATA09: DD0 Position */ +#define LCD_DATA09_DD0_Msk (0xfful << LCD_DATA09_DD0_Pos) /*!< LCD_T::DATA09: DD0 Mask */ + +#define LCD_DATA09_DD1_Pos (8) /*!< LCD_T::DATA09: DD1 Position */ +#define LCD_DATA09_DD1_Msk (0xfful << LCD_DATA09_DD1_Pos) /*!< LCD_T::DATA09: DD1 Mask */ + +#define LCD_DATA09_DD2_Pos (16) /*!< LCD_T::DATA09: DD2 Position */ +#define LCD_DATA09_DD2_Msk (0xfful << LCD_DATA09_DD2_Pos) /*!< LCD_T::DATA09: DD2 Mask */ + +#define LCD_DATA09_DD3_Pos (24) /*!< LCD_T::DATA09: DD3 Position */ +#define LCD_DATA09_DD3_Msk (0xfful << LCD_DATA09_DD3_Pos) /*!< LCD_T::DATA09: DD3 Mask */ + +#define LCD_DATA10_DD0_Pos (0) /*!< LCD_T::DATA10: DD0 Position */ +#define LCD_DATA10_DD0_Msk (0xfful << LCD_DATA10_DD0_Pos) /*!< LCD_T::DATA10: DD0 Mask */ + +#define LCD_DATA10_DD1_Pos (8) /*!< LCD_T::DATA10: DD1 Position */ +#define LCD_DATA10_DD1_Msk (0xfful << LCD_DATA10_DD1_Pos) /*!< LCD_T::DATA10: DD1 Mask */ + +#define LCD_DATA10_DD2_Pos (16) /*!< LCD_T::DATA10: DD2 Position */ +#define LCD_DATA10_DD2_Msk (0xfful << LCD_DATA10_DD2_Pos) /*!< LCD_T::DATA10: DD2 Mask */ + +#define LCD_DATA10_DD3_Pos (24) /*!< LCD_T::DATA10: DD3 Position */ +#define LCD_DATA10_DD3_Msk (0xfful << LCD_DATA10_DD3_Pos) /*!< LCD_T::DATA10: DD3 Mask */ + +/**@}*/ /* LCD_CONST */ +/**@}*/ /* end of LCD register group */ +/**@}*/ /* end of REGISTER group */ + + +#endif /* __LCD_REG_H__ */ diff --git a/Ubiquitous/XiZi/board/nuvoton-m2354/third_party_driver/include/Regs/otg_reg.h b/Ubiquitous/XiZi/board/nuvoton-m2354/third_party_driver/include/Regs/otg_reg.h new file mode 100644 index 0000000..1c7274b --- /dev/null +++ b/Ubiquitous/XiZi/board/nuvoton-m2354/third_party_driver/include/Regs/otg_reg.h @@ -0,0 +1,394 @@ +/**************************************************************************//** + * @file otg_reg.h + * @version V1.00 + * @brief OTG register definition header file + * + * @copyright SPDX-License-Identifier: Apache-2.0 + * @copyright Copyright (C) 2020 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ +#ifndef __OTG_REG_H__ +#define __OTG_REG_H__ + +/** @addtogroup REGISTER Control Register + + @{ + +*/ + +/*---------------------- USB On-The-Go Controller -------------------------*/ +/** + @addtogroup OTG USB On-The-Go Controller(OTG) + Memory Mapped Structure for OTG Controller + @{ +*/ + +typedef struct +{ + + + /** + * @var OTG_T::CTL + * Offset: 0x00 OTG Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |VBUSDROP |Drop VBUS Control + * | | |If user application running on this OTG A-device wants to conserve power, set this bit to drop VBUS + * | | |BUSREQ (OTG_CTL[1]) will be also cleared no matter A-device or B-device. + * | | |0 = Not drop the VBUS. + * | | |1 = Drop the VBUS. + * |[1] |BUSREQ |OTG Bus Request + * | | |If OTG A-device wants to do data transfers via USB bus, setting this bit will drive VBUS high to detect USB device connection + * | | |If user won't use the bus any more, clearing this bit will drop VBUS to save power + * | | |This bit will be cleared when A-device goes to A_wait_vfall state + * | | |This bit will be also cleared if VBUSDROP (OTG_CTL[0]) bit is set or IDSTS (OTG_STATUS[1]) changed. + * | | |If user of an OTG-B Device wants to request VBUS, setting this bit will run SRP protocol + * | | |This bit will be cleared if SRP failure (OTG A-device does not provide VBUS after B-device issues SRP in specified interval, defined in OTG specification) + * | | |This bit will be also cleared if VBUSDROP (OTG_CTL[0]) bit is set or IDSTS (OTG_STATUS[1]) changed. + * | | |0 = Not launch VBUS in OTG A-device or not request SRP in OTG B-device. + * | | |1 = Launch VBUS in OTG A-device or request SRP in OTG B-device. + * |[2] |HNPREQEN |OTG HNP Request Enable Bit + * | | |When USB frame as A-device, set this bit when A-device allows to process HNP protocol -- A-device changes role from Host to Peripheral + * | | |This bit will be cleared when OTG state changes from a_suspend to a_peripheral or goes back to a_idle state + * | | |When USB frame as B-device, set this bit after the OTG A-device successfully sends a SetFeature (b_hnp_enable) command to the OTG B-device to start role change -- B-device changes role from Peripheral to Host + * | | |This bit will be cleared when OTG state changes from b_peripheral to b_wait_acon or goes back to b_idle state. + * | | |0 = HNP request Disabled. + * | | |1 = HNP request Enabled (A-device can change role from Host to Peripheral or B-device can change role from Peripheral to Host). + * | | |Note: Refer to OTG specification to get a_suspend, a_peripheral, a_idle and b_idle state. + * |[4] |OTGEN |OTG Function Enable Bit + * | | |User needs to set this bit to enable OTG function while USB frame configured as OTG device + * | | |When USB frame is not configured as OTG device, this bit must be low. + * | | |0= OTG function Disabled. + * | | |1 = OTG function Enabled. + * |[5] |WKEN |OTG ID Pin Wake-up Enable Bit + * | | |0 = OTG ID pin status change wake-up function Disabled. + * | | |1 = OTG ID pin status change wake-up function Enabled. + * @var OTG_T::PHYCTL + * Offset: 0x04 OTG PHY Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |OTGPHYEN |OTG PHY Enable Bit + * | | |When USB frame is configured as OTG device or ID dependent, user needs to set this bit before using OTG function + * | | |If device is not configured as OTG device nor ID dependent , this bit is "don't care". + * | | |0 = OTG PHY Disabled. + * | | |1 = OTG PHY Enabled. + * |[1] |IDDETEN |ID Detection Enable Bit + * | | |0 = Detect ID pin status Disabled. + * | | |1 = Detect ID pin status Enabled. + * |[4] |VBENPOL |Off-chip USB VBUS Power Switch Enable Polarity + * | | |The OTG controller will enable off-chip USB VBUS power switch to provide VBUS power when need + * | | |A USB_VBUS_EN pin is used to control the off-chip USB VBUS power switch. + * | | |The polarity of enabling off-chip USB VBUS power switch (high active or low active) depends on the selected component + * | | |Set this bit as following according to the polarity of off-chip USB VBUS power switch. + * | | |0 = The off-chip USB VBUS power switch enable is active high. + * | | |1 = The off-chip USB VBUS power switch enable is active low. + * |[5] |VBSTSPOL |Off-chip USB VBUS Power Switch Status Polarity + * | | |The polarity of off-chip USB VBUS power switch valid signal depends on the selected component + * | | |A USB_VBUS_ST pin is used to monitor the valid signal of the off-chip USB VBUS power switch + * | | |Set this bit as following according to the polarity of off-chip USB VBUS power switch. + * | | |0 = The polarity of off-chip USB VBUS power switch valid status is high. + * | | |1 = The polarity of off-chip USB VBUS power switch valid status is low. + * @var OTG_T::INTEN + * Offset: 0x08 OTG Interrupt Enable Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |ROLECHGIEN|Role (Host or Peripheral) Changed Interrupt Enable Bit + * | | |0 = Interrupt Disabled. + * | | |1 = Interrupt Enabled. + * |[1] |VBEIEN |VBUS Error Interrupt Enable Bit + * | | |0 = Interrupt Disabled. + * | | |1 = Interrupt Enabled. + * | | |Note: VBUS error means going to a_vbus_err state. Please refer to A-device state diagram in OTG specification. + * |[2] |SRPFIEN |SRP Fail Interrupt Enable Bit + * | | |0 = Interrupt Disabled. + * | | |1 = Interrupt Enabled. + * |[3] |HNPFIEN |HNP Fail Interrupt Enable Bit + * | | |0 = Interrupt Disabled. + * | | |1 = Interrupt Enabled. + * |[4] |GOIDLEIEN |OTG Device Goes to IDLE State Interrupt Enable Bit + * | | |0 = Interrupt Disabled. + * | | |1 = Interrupt Enabled. + * | | |Note: Going to idle state means going to a_idle or b_idle state + * | | |Please refer to A-device state diagram and B-device state diagram in OTG spec. + * |[5] |IDCHGIEN |IDSTS Changed Interrupt Enable Bit + * | | |If this bit is set to 1 and IDSTS (OTG_STATUS[1]) status is changed from high to low or from low to high, an interrupt will be asserted. + * | | |0 = Interrupt Disabled. + * | | |1 = Interrupt Enabled. + * |[6] |PDEVIEN |Act As Peripheral Interrupt Enable Bit + * | | |If this bit is set to 1 and the device is changed as a peripheral, an interrupt will be asserted. + * | | |0 = This device as a peripheral interrupt Disabled. + * | | |1 = This device as a peripheral interrupt Enabled. + * |[7] |HOSTIEN |Act As Host Interrupt Enable Bit + * | | |If this bit is set to 1 and the device is changed as a host, an interrupt will be asserted. + * | | |0 = This device as a host interrupt Disabled. + * | | |1 = This device as a host interrupt Enabled. + * |[8] |BVLDCHGIEN|B-device Session Valid Status Changed Interrupt Enable Bit + * | | |If this bit is set to 1 and BVLD (OTG_STATUS[3]) status is changed from high to low or from low to high, an interrupt will be asserted. + * | | |0 = Interrupt Disabled. + * | | |1 = Interrupt Enabled. + * |[9] |AVLDCHGIEN|A-device Session Valid Status Changed Interrupt Enable Bit + * | | |If this bit is set to 1 and AVLD (OTG_STATUS[4]) status is changed from high to low or from low to high, an interrupt will be asserted. + * | | |0 = Interrupt Disabled. + * | | |1 = Interrupt Enabled. + * |[10] |VBCHGIEN |VBUSVLD Status Changed Interrupt Enable Bit + * | | |If this bit is set to 1 and VBUSVLD (OTG_STATUS[5]) status is changed from high to low or from low to high, an interrupt will be asserted. + * | | |0 = Interrupt Disabled. + * | | |1 = Interrupt Enabled. + * |[11] |SECHGIEN |SESSEND Status Changed Interrupt Enable Bit + * | | |If this bit is set to 1 and SESSEND (OTG_STATUS[2]) status is changed from high to low or from low to high, an interrupt will be asserted. + * | | |0 = Interrupt Disabled. + * | | |1 = Interrupt Enabled. + * |[13] |SRPDETIEN |SRP Detected Interrupt Enable Bit + * | | |0 = Interrupt Disabled. + * | | |1 = Interrupt Enabled. + * @var OTG_T::INTSTS + * Offset: 0x0C OTG Interrupt Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |ROLECHGIF |OTG Role Change Interrupt Status + * | | |This flag is set when the role of an OTG device changed from a host to a peripheral, or changed from a peripheral to a host while USB_ID pin status does not change. + * | | |0 = OTG device role not changed. + * | | |1 = OTG device role changed. + * | | |Note: Write 1 to clear this flag. + * |[1] |VBEIF |VBUS Error Interrupt Status + * | | |This bit will be set when voltage on VBUS cannot reach a minimum valid threshold 4.4V within a maximum time of 100ms after OTG A-device starting to drive VBUS high. + * | | |0 = OTG A-device drives VBUS over threshold voltage before this interval expires. + * | | |1 = OTG A-device cannot drive VBUS over threshold voltage before this interval expires. + * | | |Note: Write 1 to clear this flag and recover from the VBUS error state. + * |[2] |SRPFIF |SRP Fail Interrupt Status + * | | |After initiating SRP, an OTG B-device will wait for the OTG A-device to drive VBUS high at least TB_SRP_FAIL minimum, defined in OTG specification + * | | |This flag is set when the OTG B-device does not get VBUS high after this interval. + * | | |0 = OTG B-device gets VBUS high before this interval. + * | | |1 = OTG B-device does not get VBUS high before this interval. + * | | |Note: Write 1 to clear this flag. + * |[3] |HNPFIF |HNP Fail Interrupt Status + * | | |When A-device has granted B-device to be host and USB bus is in SE0 (both USB_D+ and USB_D- low) state, this bit will be set when A-device does not connect after specified interval expires. + * | | |0 = A-device connects to B-device before specified interval expires. + * | | |1 = A-device does not connect to B-device before specified interval expires. + * | | |Note: Write 1 to clear this flag. + * |[4] |GOIDLEIF |OTG Device Goes to IDLE Interrupt Status + * | | |Flag is set if the OTG device transfers from non-idle state to idle state + * | | |The OTG device will be neither a host nor a peripheral. + * | | |0 = OTG device does not go back to idle state (a_idle or b_idle). + * | | |1 = OTG device goes back to idle state(a_idle or b_idle). + * | | |Note 1: Going to idle state means going to a_idle or b_idle state. Please refer to OTG specification. + * | | |Note 2: Write 1 to clear this flag. + * |[5] |IDCHGIF |ID State Change Interrupt Status + * | | |0 = IDSTS (OTG_STATUS[1]) not toggled. + * | | |1 = IDSTS (OTG_STATUS[1]) from high to low or from low to high. + * | | |Note: Write 1 to clear this flag. + * |[6] |PDEVIF |Act As Peripheral Interrupt Status + * | | |0= This device does not act as a peripheral. + * | | |1 = This device acts as a peripheral. + * | | |Note: Write 1 to clear this flag. + * |[7] |HOSTIF |Act As Host Interrupt Status + * | | |0= This device does not act as a host. + * | | |1 = This device acts as a host. + * | | |Note: Write 1 to clear this flag. + * |[8] |BVLDCHGIF |B-device Session Valid State Change Interrupt Status + * | | |0 = BVLD (OTG_STATUS[3]) is not toggled. + * | | |1 = BVLD (OTG_STATUS[3]) from high to low or low to high. + * | | |Note: Write 1 to clear this status. + * |[9] |AVLDCHGIF |A-device Session Valid State Change Interrupt Status + * | | |0 = AVLD (OTG_STATUS[4]) not toggled. + * | | |1 = AVLD (OTG_STATUS[4]) from high to low or low to high. + * | | |Note: Write 1 to clear this status. + * |[10] |VBCHGIF |VBUSVLD State Change Interrupt Status + * | | |0 = VBUSVLD (OTG_STATUS[5]) not toggled. + * | | |1 = VBUSVLD (OTG_STATUS[5]) from high to low or from low to high. + * | | |Note: Write 1 to clear this status. + * |[11] |SECHGIF |SESSEND State Change Interrupt Status + * | | |0 = SESSEND (OTG_STATUS[2]) not toggled. + * | | |1 = SESSEND (OTG_STATUS[2]) from high to low or from low to high. + * | | |Note: Write 1 to clear this flag. + * |[13] |SRPDETIF |SRP Detected Interrupt Status + * | | |0 = SRP not detected. + * | | |1 = SRP detected. + * | | |Note: Write 1 to clear this status. + * @var OTG_T::STATUS + * Offset: 0x10 OTG Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |OVERCUR |Over Current Condition + * | | |The voltage on VBUS cannot reach a minimum VBUS valid threshold, 4.4V minimum, within a maximum time of 100ms after OTG A-device drives VBUS high. + * | | |0 = OTG A-device drives VBUS successfully. + * | | |1 = OTG A-device cannot drives VBUS high in this interval. + * |[1] |IDSTS |USB_ID Pin State of Mini-/Micro- Plug + * | | |0 = Mini-A/Micro-A plug is attached. + * | | |1 = Mini-B/Micro-B plug is attached. + * |[2] |SESSEND |Session End Status + * | | |When VBUS voltage is lower than 0.4V, this bit will be set to 1 + * | | |Session end means no meaningful power on VBUS. + * | | |0 = Session is not end. + * | | |1 = Session is end. + * |[3] |BVLD |B-device Session Valid Status + * | | |0 = B-device session is not valid. + * | | |1 = B-device session is valid. + * |[4] |AVLD |A-device Session Valid Status + * | | |0 = A-device session is not valid. + * | | |1 = A-device session is valid. + * |[5] |VBUSVLD |VBUS Valid Status + * | | |When VBUS is larger than 4.7V, this bit will be set to 1. + * | | |0 = VBUS is not valid. + * | | |1 = VBUS is valid. + * |[6] |ASPERI |As Peripheral Status + * | | |When OTG as peripheral, this bit is set. + * | | |0: OTG not as peripheral + * | | |1: OTG as peripheral + * |[7] |ASHOST |As Host Status + * | | |When OTG as Host, this bit is set. + * | | |0: OTG not as Host + * | | |1: OTG as Host + */ + __IO uint32_t CTL; /*!< [0x0000] OTG Control Register */ + __IO uint32_t PHYCTL; /*!< [0x0004] OTG PHY Control Register */ + __IO uint32_t INTEN; /*!< [0x0008] OTG Interrupt Enable Register */ + __IO uint32_t INTSTS; /*!< [0x000c] OTG Interrupt Status Register */ + __I uint32_t STATUS; /*!< [0x0010] OTG Status Register */ + +} OTG_T; + +/** + @addtogroup OTG_CONST OTG Bit Field Definition + Constant Definitions for OTG Controller + @{ +*/ + +#define OTG_CTL_VBUSDROP_Pos (0) /*!< OTG_T::CTL: VBUSDROP Position */ +#define OTG_CTL_VBUSDROP_Msk (0x1ul << OTG_CTL_VBUSDROP_Pos) /*!< OTG_T::CTL: VBUSDROP Mask */ + +#define OTG_CTL_BUSREQ_Pos (1) /*!< OTG_T::CTL: BUSREQ Position */ +#define OTG_CTL_BUSREQ_Msk (0x1ul << OTG_CTL_BUSREQ_Pos) /*!< OTG_T::CTL: BUSREQ Mask */ + +#define OTG_CTL_HNPREQEN_Pos (2) /*!< OTG_T::CTL: HNPREQEN Position */ +#define OTG_CTL_HNPREQEN_Msk (0x1ul << OTG_CTL_HNPREQEN_Pos) /*!< OTG_T::CTL: HNPREQEN Mask */ + +#define OTG_CTL_OTGEN_Pos (4) /*!< OTG_T::CTL: OTGEN Position */ +#define OTG_CTL_OTGEN_Msk (0x1ul << OTG_CTL_OTGEN_Pos) /*!< OTG_T::CTL: OTGEN Mask */ + +#define OTG_CTL_WKEN_Pos (5) /*!< OTG_T::CTL: WKEN Position */ +#define OTG_CTL_WKEN_Msk (0x1ul << OTG_CTL_WKEN_Pos) /*!< OTG_T::CTL: WKEN Mask */ + +#define OTG_PHYCTL_OTGPHYEN_Pos (0) /*!< OTG_T::PHYCTL: OTGPHYEN Position */ +#define OTG_PHYCTL_OTGPHYEN_Msk (0x1ul << OTG_PHYCTL_OTGPHYEN_Pos) /*!< OTG_T::PHYCTL: OTGPHYEN Mask */ + +#define OTG_PHYCTL_IDDETEN_Pos (1) /*!< OTG_T::PHYCTL: IDDETEN Position */ +#define OTG_PHYCTL_IDDETEN_Msk (0x1ul << OTG_PHYCTL_IDDETEN_Pos) /*!< OTG_T::PHYCTL: IDDETEN Mask */ + +#define OTG_PHYCTL_VBENPOL_Pos (4) /*!< OTG_T::PHYCTL: VBENPOL Position */ +#define OTG_PHYCTL_VBENPOL_Msk (0x1ul << OTG_PHYCTL_VBENPOL_Pos) /*!< OTG_T::PHYCTL: VBENPOL Mask */ + +#define OTG_PHYCTL_VBSTSPOL_Pos (5) /*!< OTG_T::PHYCTL: VBSTSPOL Position */ +#define OTG_PHYCTL_VBSTSPOL_Msk (0x1ul << OTG_PHYCTL_VBSTSPOL_Pos) /*!< OTG_T::PHYCTL: VBSTSPOL Mask */ + +#define OTG_INTEN_ROLECHGIEN_Pos (0) /*!< OTG_T::INTEN: ROLECHGIEN Position */ +#define OTG_INTEN_ROLECHGIEN_Msk (0x1ul << OTG_INTEN_ROLECHGIEN_Pos) /*!< OTG_T::INTEN: ROLECHGIEN Mask */ + +#define OTG_INTEN_VBEIEN_Pos (1) /*!< OTG_T::INTEN: VBEIEN Position */ +#define OTG_INTEN_VBEIEN_Msk (0x1ul << OTG_INTEN_VBEIEN_Pos) /*!< OTG_T::INTEN: VBEIEN Mask */ + +#define OTG_INTEN_SRPFIEN_Pos (2) /*!< OTG_T::INTEN: SRPFIEN Position */ +#define OTG_INTEN_SRPFIEN_Msk (0x1ul << OTG_INTEN_SRPFIEN_Pos) /*!< OTG_T::INTEN: SRPFIEN Mask */ + +#define OTG_INTEN_HNPFIEN_Pos (3) /*!< OTG_T::INTEN: HNPFIEN Position */ +#define OTG_INTEN_HNPFIEN_Msk (0x1ul << OTG_INTEN_HNPFIEN_Pos) /*!< OTG_T::INTEN: HNPFIEN Mask */ + +#define OTG_INTEN_GOIDLEIEN_Pos (4) /*!< OTG_T::INTEN: GOIDLEIEN Position */ +#define OTG_INTEN_GOIDLEIEN_Msk (0x1ul << OTG_INTEN_GOIDLEIEN_Pos) /*!< OTG_T::INTEN: GOIDLEIEN Mask */ + +#define OTG_INTEN_IDCHGIEN_Pos (5) /*!< OTG_T::INTEN: IDCHGIEN Position */ +#define OTG_INTEN_IDCHGIEN_Msk (0x1ul << OTG_INTEN_IDCHGIEN_Pos) /*!< OTG_T::INTEN: IDCHGIEN Mask */ + +#define OTG_INTEN_PDEVIEN_Pos (6) /*!< OTG_T::INTEN: PDEVIEN Position */ +#define OTG_INTEN_PDEVIEN_Msk (0x1ul << OTG_INTEN_PDEVIEN_Pos) /*!< OTG_T::INTEN: PDEVIEN Mask */ + +#define OTG_INTEN_HOSTIEN_Pos (7) /*!< OTG_T::INTEN: HOSTIEN Position */ +#define OTG_INTEN_HOSTIEN_Msk (0x1ul << OTG_INTEN_HOSTIEN_Pos) /*!< OTG_T::INTEN: HOSTIEN Mask */ + +#define OTG_INTEN_BVLDCHGIEN_Pos (8) /*!< OTG_T::INTEN: BVLDCHGIEN Position */ +#define OTG_INTEN_BVLDCHGIEN_Msk (0x1ul << OTG_INTEN_BVLDCHGIEN_Pos) /*!< OTG_T::INTEN: BVLDCHGIEN Mask */ + +#define OTG_INTEN_AVLDCHGIEN_Pos (9) /*!< OTG_T::INTEN: AVLDCHGIEN Position */ +#define OTG_INTEN_AVLDCHGIEN_Msk (0x1ul << OTG_INTEN_AVLDCHGIEN_Pos) /*!< OTG_T::INTEN: AVLDCHGIEN Mask */ + +#define OTG_INTEN_VBCHGIEN_Pos (10) /*!< OTG_T::INTEN: VBCHGIEN Position */ +#define OTG_INTEN_VBCHGIEN_Msk (0x1ul << OTG_INTEN_VBCHGIEN_Pos) /*!< OTG_T::INTEN: VBCHGIEN Mask */ + +#define OTG_INTEN_SECHGIEN_Pos (11) /*!< OTG_T::INTEN: SECHGIEN Position */ +#define OTG_INTEN_SECHGIEN_Msk (0x1ul << OTG_INTEN_SECHGIEN_Pos) /*!< OTG_T::INTEN: SECHGIEN Mask */ + +#define OTG_INTEN_SRPDETIEN_Pos (13) /*!< OTG_T::INTEN: SRPDETIEN Position */ +#define OTG_INTEN_SRPDETIEN_Msk (0x1ul << OTG_INTEN_SRPDETIEN_Pos) /*!< OTG_T::INTEN: SRPDETIEN Mask */ + +#define OTG_INTSTS_ROLECHGIF_Pos (0) /*!< OTG_T::INTSTS: ROLECHGIF Position */ +#define OTG_INTSTS_ROLECHGIF_Msk (0x1ul << OTG_INTSTS_ROLECHGIF_Pos) /*!< OTG_T::INTSTS: ROLECHGIF Mask */ + +#define OTG_INTSTS_VBEIF_Pos (1) /*!< OTG_T::INTSTS: VBEIF Position */ +#define OTG_INTSTS_VBEIF_Msk (0x1ul << OTG_INTSTS_VBEIF_Pos) /*!< OTG_T::INTSTS: VBEIF Mask */ + +#define OTG_INTSTS_SRPFIF_Pos (2) /*!< OTG_T::INTSTS: SRPFIF Position */ +#define OTG_INTSTS_SRPFIF_Msk (0x1ul << OTG_INTSTS_SRPFIF_Pos) /*!< OTG_T::INTSTS: SRPFIF Mask */ + +#define OTG_INTSTS_HNPFIF_Pos (3) /*!< OTG_T::INTSTS: HNPFIF Position */ +#define OTG_INTSTS_HNPFIF_Msk (0x1ul << OTG_INTSTS_HNPFIF_Pos) /*!< OTG_T::INTSTS: HNPFIF Mask */ + +#define OTG_INTSTS_GOIDLEIF_Pos (4) /*!< OTG_T::INTSTS: GOIDLEIF Position */ +#define OTG_INTSTS_GOIDLEIF_Msk (0x1ul << OTG_INTSTS_GOIDLEIF_Pos) /*!< OTG_T::INTSTS: GOIDLEIF Mask */ + +#define OTG_INTSTS_IDCHGIF_Pos (5) /*!< OTG_T::INTSTS: IDCHGIF Position */ +#define OTG_INTSTS_IDCHGIF_Msk (0x1ul << OTG_INTSTS_IDCHGIF_Pos) /*!< OTG_T::INTSTS: IDCHGIF Mask */ + +#define OTG_INTSTS_PDEVIF_Pos (6) /*!< OTG_T::INTSTS: PDEVIF Position */ +#define OTG_INTSTS_PDEVIF_Msk (0x1ul << OTG_INTSTS_PDEVIF_Pos) /*!< OTG_T::INTSTS: PDEVIF Mask */ + +#define OTG_INTSTS_HOSTIF_Pos (7) /*!< OTG_T::INTSTS: HOSTIF Position */ +#define OTG_INTSTS_HOSTIF_Msk (0x1ul << OTG_INTSTS_HOSTIF_Pos) /*!< OTG_T::INTSTS: HOSTIF Mask */ + +#define OTG_INTSTS_BVLDCHGIF_Pos (8) /*!< OTG_T::INTSTS: BVLDCHGIF Position */ +#define OTG_INTSTS_BVLDCHGIF_Msk (0x1ul << OTG_INTSTS_BVLDCHGIF_Pos) /*!< OTG_T::INTSTS: BVLDCHGIF Mask */ + +#define OTG_INTSTS_AVLDCHGIF_Pos (9) /*!< OTG_T::INTSTS: AVLDCHGIF Position */ +#define OTG_INTSTS_AVLDCHGIF_Msk (0x1ul << OTG_INTSTS_AVLDCHGIF_Pos) /*!< OTG_T::INTSTS: AVLDCHGIF Mask */ + +#define OTG_INTSTS_VBCHGIF_Pos (10) /*!< OTG_T::INTSTS: VBCHGIF Position */ +#define OTG_INTSTS_VBCHGIF_Msk (0x1ul << OTG_INTSTS_VBCHGIF_Pos) /*!< OTG_T::INTSTS: VBCHGIF Mask */ + +#define OTG_INTSTS_SECHGIF_Pos (11) /*!< OTG_T::INTSTS: SECHGIF Position */ +#define OTG_INTSTS_SECHGIF_Msk (0x1ul << OTG_INTSTS_SECHGIF_Pos) /*!< OTG_T::INTSTS: SECHGIF Mask */ + +#define OTG_INTSTS_SRPDETIF_Pos (13) /*!< OTG_T::INTSTS: SRPDETIF Position */ +#define OTG_INTSTS_SRPDETIF_Msk (0x1ul << OTG_INTSTS_SRPDETIF_Pos) /*!< OTG_T::INTSTS: SRPDETIF Mask */ + +#define OTG_STATUS_OVERCUR_Pos (0) /*!< OTG_T::STATUS: OVERCUR Position */ +#define OTG_STATUS_OVERCUR_Msk (0x1ul << OTG_STATUS_OVERCUR_Pos) /*!< OTG_T::STATUS: OVERCUR Mask */ + +#define OTG_STATUS_IDSTS_Pos (1) /*!< OTG_T::STATUS: IDSTS Position */ +#define OTG_STATUS_IDSTS_Msk (0x1ul << OTG_STATUS_IDSTS_Pos) /*!< OTG_T::STATUS: IDSTS Mask */ + +#define OTG_STATUS_SESSEND_Pos (2) /*!< OTG_T::STATUS: SESSEND Position */ +#define OTG_STATUS_SESSEND_Msk (0x1ul << OTG_STATUS_SESSEND_Pos) /*!< OTG_T::STATUS: SESSEND Mask */ + +#define OTG_STATUS_BVLD_Pos (3) /*!< OTG_T::STATUS: BVLD Position */ +#define OTG_STATUS_BVLD_Msk (0x1ul << OTG_STATUS_BVLD_Pos) /*!< OTG_T::STATUS: BVLD Mask */ + +#define OTG_STATUS_AVLD_Pos (4) /*!< OTG_T::STATUS: AVLD Position */ +#define OTG_STATUS_AVLD_Msk (0x1ul << OTG_STATUS_AVLD_Pos) /*!< OTG_T::STATUS: AVLD Mask */ + +#define OTG_STATUS_VBUSVLD_Pos (5) /*!< OTG_T::STATUS: VBUSVLD Position */ +#define OTG_STATUS_VBUSVLD_Msk (0x1ul << OTG_STATUS_VBUSVLD_Pos) /*!< OTG_T::STATUS: VBUSVLD Mask */ + +#define OTG_STATUS_ASPERI_Pos (6) /*!< OTG_T::STATUS: ASPERI Position */ +#define OTG_STATUS_ASPERI_Msk (0x1ul << OTG_STATUS_ASPERI_Pos) /*!< OTG_T::STATUS: ASPERI Mask */ + +#define OTG_STATUS_ASHOST_Pos (7) /*!< OTG_T::STATUS: ASHOST Position */ +#define OTG_STATUS_ASHOST_Msk (0x1ul << OTG_STATUS_ASHOST_Pos) /*!< OTG_T::STATUS: ASHOST Mask */ + +/**@}*/ /* OTG_CONST */ +/**@}*/ /* end of OTG register group */ +/**@}*/ /* end of REGISTER group */ + +#endif /* __OTG_REG_H__ */ diff --git a/Ubiquitous/XiZi/board/nuvoton-m2354/third_party_driver/include/Regs/pdma_reg.h b/Ubiquitous/XiZi/board/nuvoton-m2354/third_party_driver/include/Regs/pdma_reg.h new file mode 100644 index 0000000..9ef68cb --- /dev/null +++ b/Ubiquitous/XiZi/board/nuvoton-m2354/third_party_driver/include/Regs/pdma_reg.h @@ -0,0 +1,814 @@ +/**************************************************************************//** + * @file pdma_reg.h + * @version V1.00 + * @brief PDMA register definition header file + * + * @copyright SPDX-License-Identifier: Apache-2.0 + * @copyright Copyright (C) 2020 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ +#ifndef __PDMA_REG_H__ +#define __PDMA_REG_H__ + +/** @addtogroup REGISTER Control Register + + @{ + +*/ + +/*---------------------- Peripheral Direct Memory Access Controller -------------------------*/ +/** + @addtogroup PDMA Peripheral Direct Memory Access Controller(PDMA) + Memory Mapped Structure for PDMA Controller + @{ +*/ + + + +typedef struct +{ + /** + * @var DSCT_T::CTL + * Offset: 0x00/0x10/0x20/0x30/0x40/0x50/0x60/0x70 Descriptor Table Control Register of PDMA Channel 0~7 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[1:0] |OPMODE |PDMA Operation Mode Selection + * | | |00 = Idle state: Channel is stopped or this table is complete, when PDMA finish channel table task, OPMODE will be cleared to idle state automatically. + * | | |01 = Basic mode: The descriptor table only has one task + * | | |When this task is finished, the TDIF(PDMA_INTSTS[1]) will be asserted. + * | | |10 = Scatter-Gather mode: When operating in this mode, user must give the first descriptor table address in PDMA_DSCT_FIRST register; PDMA controller will ignore this task, then load the next task to execute. + * | | |11 = Reserved. + * | | |Note: Before filling transfer task in the Descriptor Table, user must check if the descriptor table is complete. + * |[2] |TXTYPE |Transfer Type + * | | |0 = Burst transfer type. + * | | |1 = Single transfer type. + * |[6:4] |BURSIZE |Burst Size + * | | |This field is used for peripheral to determine the burst size or used for determine the re-arbitration size. + * | | |000 = 128 Transfers. + * | | |001 = 64 Transfers. + * | | |010 = 32 Transfers. + * | | |011 = 16 Transfers. + * | | |100 = 8 Transfers. + * | | |101 = 4 Transfers. + * | | |110 = 2 Transfers. + * | | |111 = 1 Transfers. + * | | |Note: This field is only useful in burst transfer type. + * |[7] |TBINTDIS |Table Interrupt Disable Bit + * | | |This field can be used to decide whether to enable table interrupt or not + * | | |If the TBINTDIS bit is enabled when PDMA controller finishes transfer task, it will not generates transfer done interrupt. + * | | |0 = Table interrupt Enabled. + * | | |1 = Table interrupt Disabled. + * | | |Note: If this bit set to 1, the TEMPTYF will not be set. + * |[9:8] |SAINC |Source Address Increment + * | | |This field is used to set the source address increment size. + * | | |11 = No increment (fixed address). + * | | |Others = Increment and size is depended on TXWIDTH selection. + * |[11:10] |DAINC |Destination Address Increment + * | | |This field is used to set the destination address increment size. + * | | |11 = No increment (fixed address). + * | | |Others = Increment and size is depended on TXWIDTH selection. + * |[13:12] |TXWIDTH |Transfer Width Selection + * | | |This field is used for transfer width. + * | | |00 = One byte (8 bit) is transferred for every operation. + * | | |01 = One half-word (16 bit) is transferred for every operation. + * | | |10 = One word (32-bit) is transferred for every operation. + * | | |11 = Reserved. + * | | |Note: The PDMA transfer source address (PDMA_DSCT_SA) and PDMA transfer destination address (PDMA_DSCT_DA) should be alignment under the TXWIDTH selection + * | | |For example, if source address is 0x2000_0202, but TXWIDTH is word transfer, the source address is not word alignment + * | | |The source address is aligned when TXWIDTH is byte or half-word transfer. + * |[14] |TXACK |Transfer Acknowledge Selection + * | | |0 = transfer ack when transfer done. + * | | |1 = transfer ack when PDMA get transfer data. + * |[15] |STRIDEEN |Stride Mode Enable Bit + * | | |0 = Stride transfer mode Disabled. + * | | |1 = Stride transfer mode Enabled. + * |[31:16] |TXCNT |Transfer Count + * | | |The TXCNT represents the required number of PDMA transfer, the real transfer count is (TXCNT + 1); The maximum transfer count is 65536, every transfer may be byte, half-word or word that is dependent on TXWIDTH field. + * | | |Note: When PDMA finish each transfer data, this field will be decrease immediately. + * @var DSCT_T::SA + * Offset: 0x04/0x14/0x24/0x34/0x44/0x54/0x64/0x74 Source Address Register of PDMA Channel 0~7 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |SA |PDMA Transfer Source Address Register + * | | |This field indicates a 32-bit source address of PDMA controller. + * | | |Note: The PDMA transfer source address should be aligned with the TXWIDTH(PDMA_DSCTn_CTL[13:12], n=0,1..7) selection. + * @var DSCT_T::DA + * Offset: 0x08/0x18/0x28/0x38/0x48/0x58/0x68/0x78 Destination Address Register of PDMA Channel 0~7 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |DA |PDMA Transfer Destination Address Register + * | | |This field indicates a 32-bit destination address of PDMA controller. + * | | |Note: The PDMA transfer destination address should be aligned with the TXWIDTH(PDMA_DSCTn_CTL[13:12], n=0,1..7) selection. + * @var DSCT_T::NEXT + * Offset: 0x0C/0x1C/0x2C/0x3C/0x4C/0x5C/0x6C/0x7C First Scatter-Gather Descriptor Table Offset of PDMA Channel 0~7 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |FIRST |PDMA First Descriptor Table Offset + * | | |This field indicates the offset of the first descriptor table address in system memory. + * | | |Write Operation: + * | | |If the system memory based address is 0x2000_0000 (PDMA_SCATBA), and the first descriptor table is start from 0x2000_0100, then this field must fill in 0x0100. + * | | |Read Operation: + * | | |When operating in scatter-gather mode, the last two bits FIRST[1:0] will become reserved. + * | | |Note1: The first descriptor table address must be word boundary. + * | | |Note2: Before filled transfer task in the descriptor table, user must check if the descriptor table is complete. + * |[31:16] |NEXT |PDMA Next Descriptor Table Offset + * | | |This field indicates the offset of next descriptor table address in system memory. + * | | |Note: write operation is useless in this field. + */ + + __IO uint32_t CTL; /*!< [0x00/0x10/0x20/0x30/0x40/0x50/0x60/0x70] Descriptor Table Control Register of PDMA Channel 0~7 */ + __IO uint32_t SA; /*!< [0x04/0x14/0x24/0x34/0x44/0x54/0x64/0x74] Source Address Register of PDMA Channel 0~7 */ + __IO uint32_t DA; /*!< [0x08/0x18/0x28/0x38/0x48/0x58/0x68/0x78] Destination Address Register of PDMA Channel 0~7 */ + __IO uint32_t NEXT; /*!< [0x0C/0x1C/0x2C/0x3C/0x4C/0x5C/0x6C/0x7C]Next Scatter-Gather Descriptor Table Offset */ + +} DSCT_T; + +typedef struct +{ + /** + * @var STRIDE_T::STCR + * Offset: 0x500/0x508/0x510/0x518/0x520/0x528 Stride Transfer Count Register of PDMA Channel 0~5 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |STC |PDMA Stride Transfer Count + * | | |The 16-bit register defines the stride transfer count of each row. + * @var STRIDE_T::ASOCR + * Offset: 0x504/0x50C/0x514/0x51C/0x524/0x52C Address Stride Offset Register of PDMA Channel 0~5 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |SASOL |VDMA Source Address Stride Offset Length + * | | |The 16-bit register defines the source address stride transfer offset count of each row. + * |[31:16] |DASOL |VDMA Destination Address Stride Offset Length + * | | |The 16-bit register defines the destination address stride transfer offset count of each row. + */ + __IO uint32_t STCR; /*!< [0x0500/0x508/0x510/0x518/0x520/0x528] Stride Transfer Count Register of PDMA Channel 0~7 */ + __IO uint32_t ASOCR; /*!< [0x0504/0x50C/0x514/0x51C/0x524/0x52C] Address Stride Offset Register of PDMA Channel 0 */ +} STRIDE_T; + +typedef struct +{ + /** + * @var REPEAT_T::AICTL + * Offset: 0x600 Address Interval Control Register of PDMA Channel n + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |SAICNT |PDMA Source Address Interval Count + * | | |The 16-bit register defines the source address interval count of each row. + * |[31:16] |DAICNT |PDMA Destination Address Interval Count + * | | |The 16-bit register defines the destination address interval count of each row. + * @var REPEAT_T::RCNT + * Offset: 0x604 Repeat Count Register of PDMA Channe n + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |RCNT |PDMA Repeat Count + * | | |The 16-bit register defines the repeat times of block transfer. + */ + __IO uint32_t AICTL; /*!< [0x0600] Address Interval Control Register of PDMA Channel 0 */ + __IO uint32_t RCNT; /*!< [0x0604] Repeat Count Register of PDMA Channel 0 */ +} REPEAT_T; + +typedef struct +{ + + + /** + * @var PDMA_T::CURSCAT + * Offset: 0x80/0x84/0x88/0x8C/0x90/0x94/0x98/0x9C Current Scatter-Gather Descriptor Table Address of PDMA Channel 0~7 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |CURADDR |PDMA Current Description Address Register (Read Only) + * | | |This field indicates a 32-bit current external description address of PDMA controller. + * | | |Note: This field is read only and only used for Scatter-Gather mode to indicate the current external description address. + * @var PDMA_T::CHCTL + * Offset: 0x400 PDMA Channel Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |CHENn |PDMA Channel Enable Bit + * | | |Set this bit to 1 to enable PDMAn operation. Channel cannot be active if it is not set as enabled. + * | | |0 = PDMA channel [n] Disabled. + * | | |1 = PDMA channel [n] Enabled. + * | | |Note: Set corresponding bit of PDMA_PAUSE or PDMA_CHRST register will also clear this bit. + * @var PDMA_T::PAUSE + * Offset: 0x404 PDMA Transfer Pause Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |PAUSEn |PDMA Transfer Pause Control Register (Write Only) + * | | |User can set PAUSEn bit field to pause the PDMA transfer + * | | |When user sets PAUSEn bit, the PDMA controller will pause the on-going transfer, then clear the channel enable bit CHEN(PDMA_CHCTL [n], n=0,1..7) and clear request active flag + * | | |If re-enable the paused channel again, the remaining transfers will be processed. + * | | |0 = No effect. + * | | |1 = Pause PDMA channel n transfer. + * @var PDMA_T::SWREQ + * Offset: 0x408 PDMA Software Request Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |SWREQn |PDMA Software Request Register (Write Only) + * | | |Set this bit to 1 to generate a software request to PDMA [n]. + * | | |0 = No effect. + * | | |1 = Generate a software request. + * | | |Note1: User can read PDMA_TRGSTS register to know which channel is on active + * | | |Active flag may be triggered by software request or peripheral request. + * | | |Note2: If user does not enable corresponding PDMA channel, the software request will be ignored. + * @var PDMA_T::TRGSTS + * Offset: 0x40C PDMA Channel Request Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |REQSTSn |PDMA Channel Request Status (Read Only) + * | | |This flag indicates whether channel[n] have a request or not, no matter request from software or peripheral + * | | |When PDMA controller finishes channel transfer, this bit will be cleared automatically. + * | | |0 = PDMA Channel n has no request. + * | | |1 = PDMA Channel n has a request. + * | | |Note: If user pauses or resets each PDMA transfer by setting PDMA_PAUSE or PDMA_CHRST register respectively, this bit will be cleared automatically after finishing current transfer. + * @var PDMA_T::PRISET + * Offset: 0x410 PDMA Fixed Priority Setting Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |FPRISETn |PDMA Fixed Priority Setting Register + * | | |Set this bit to 1 to enable fixed priority level. + * | | |Write Operation: + * | | |0 = No effect. + * | | |1 = Set PDMA channel [n] to fixed priority channel. + * | | |Read Operation: + * | | |0 = Corresponding PDMA channel is round-robin priority. + * | | |1 = Corresponding PDMA channel is fixed priority. + * | | |Note: This field only set to fixed priority, clear fixed priority use PDMA_PRICLR register. + * @var PDMA_T::PRICLR + * Offset: 0x414 PDMA Fixed Priority Clear Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |FPRICLRn |PDMA Fixed Priority Clear Register (Write Only) + * | | |Set this bit to 1 to clear fixed priority level. + * | | |0 = No effect. + * | | |1 = Clear PDMA channel [n] fixed priority setting. + * | | |Note: User can read PDMA_PRISET register to know the channel priority. + * @var PDMA_T::INTEN + * Offset: 0x418 PDMA Interrupt Enable Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |INTENn |PDMA Interrupt Enable Register + * | | |This field is used for enabling PDMA channel[n] interrupt. + * | | |0 = PDMA channel n interrupt Disabled. + * | | |1 = PDMA channel n interrupt Enabled. + * @var PDMA_T::INTSTS + * Offset: 0x41C PDMA Interrupt Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |ABTIF |PDMA Read/Write Target Abort Interrupt Flag (Read Only) + * | | |This bit indicates that PDMA has target abort error; Software can read PDMA_ABTSTS register to find which channel has target abort error. + * | | |0 = No AHB bus ERROR response received. + * | | |1 = AHB bus ERROR response received. + * |[1] |TDIF |Transfer Done Interrupt Flag (Read Only) + * | | |This bit indicates that PDMA controller has finished transmission; User can read PDMA_TDSTS register to indicate which channel finished transfer. + * | | |0 = Not finished yet. + * | | |1 = PDMA channel has finished transmission. + * |[2] |ALIGNF |Transfer Alignment Interrupt Flag (Read Only) + * | | |0 = PDMA channel source address and destination address both follow transfer width setting. + * | | |1 = PDMA channel source address or destination address is not follow transfer width setting. + * |[8] |REQTOF0 |Request Time-out Flag for Channel 0 + * | | |This flag indicates that PDMA controller has waited peripheral request for a period defined by PDMA_TOC0, user can write 1 to clear these bits. + * | | |0 = No request time-out. + * | | |1 = Peripheral request time-out. + * |[9] |REQTOF1 |Request Time-out Flag for Channel 1 + * | | |This flag indicates that PDMA controller has waited peripheral request for a period defined by PDMA_TOC1, user can write 1 to clear these bits. + * | | |0 = No request time-out. + * | | |1 = Peripheral request time-out. + * @var PDMA_T::ABTSTS + * Offset: 0x420 PDMA Channel Read/Write Target Abort Flag Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |ABTIFn |PDMA Read/Write Target Abort Interrupt Status Flag + * | | |This bit indicates which PDMA controller has target abort error; User can write 1 to clear these bits. + * | | |0 = No AHB bus ERROR response received when channel n transfer. + * | | |1 = AHB bus ERROR response received when channel n transfer. + * @var PDMA_T::TDSTS + * Offset: 0x424 PDMA Channel Transfer Done Flag Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |TDIFn |Transfer Done Flag Register + * | | |This bit indicates whether PDMA controller channel transfer has been finished or not, user can write 1 to clear these bits. + * | | |0 = PDMA channel transfer has not finished. + * | | |1 = PDMA channel has finished transmission. + * @var PDMA_T::ALIGN + * Offset: 0x428 PDMA Transfer Alignment Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |ALIGNn |Transfer Alignment Flag Register + * | | |0 = PDMA channel source address and destination address both follow transfer width setting. + * | | |1 = PDMA channel source address or destination address is not follow transfer width setting. + * @var PDMA_T::TACTSTS + * Offset: 0x42C PDMA Transfer Active Flag Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |TXACTFn |Transfer on Active Flag Register (Read Only) + * | | |This bit indicates which PDMA channel is in active. + * | | |0 = PDMA channel is not finished. + * | | |1 = PDMA channel is active. + * @var PDMA_T::TOUTPSC + * Offset: 0x430 PDMA Time-out Prescaler Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[2:0] |TOUTPSC0 |PDMA Channel 0 Time-out Clock Source Prescaler Bits + * | | |000 = PDMA channel 0 time-out clock source is HCLK/2^8. + * | | |001 = PDMA channel 0 time-out clock source is HCLK/2^9. + * | | |010 = PDMA channel 0 time-out clock source is HCLK/2^10. + * | | |011 = PDMA channel 0 time-out clock source is HCLK/2^11. + * | | |100 = PDMA channel 0 time-out clock source is HCLK/2^12. + * | | |101 = PDMA channel 0 time-out clock source is HCLK/2^13. + * | | |110 = PDMA channel 0 time-out clock source is HCLK/2^14. + * | | |111 = PDMA channel 0 time-out clock source is HCLK/2^15. + * |[6:4] |TOUTPSC1 |PDMA Channel 1 Time-out Clock Source Prescaler Bits + * | | |000 = PDMA channel 1 time-out clock source is HCLK/2^8. + * | | |001 = PDMA channel 1 time-out clock source is HCLK/2^9. + * | | |010 = PDMA channel 1 time-out clock source is HCLK/2^10. + * | | |011 = PDMA channel 1 time-out clock source is HCLK/2^11. + * | | |100 = PDMA channel 1 time-out clock source is HCLK/2^12. + * | | |101 = PDMA channel 1 time-out clock source is HCLK/2^13. + * | | |110 = PDMA channel 1 time-out clock source is HCLK/2^14. + * | | |111 = PDMA channel 1 time-out clock source is HCLK/2^15. + * @var PDMA_T::TOUTEN + * Offset: 0x434 PDMA Time-out Enable Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |TOUTEN0 |PDMA Channel 0 Time-out Enable Bit + * | | |0 = PDMA Channel 0 time-out function Disable. + * | | |1 = PDMA Channel 0 time-out function Enable. + * |[1] |TOUTEN1 |PDMA Channel 1 Time-out Enable Bit + * | | |0 = PDMA Channel 1 time-out function Disable. + * | | |1 = PDMA Channel 1 time-out function Enable. + * @var PDMA_T::TOUTIEN + * Offset: 0x438 PDMA Time-out Interrupt Enable Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |TOUTIEN0 |PDMA Channel 0 Time-out Interrupt Enable Bit + * | | |0 = PDMA Channel 0 time-out interrupt Disable. + * | | |1 = PDMA Channel 0 time-out interrupt Enable. + * |[1] |TOUTIEN1 |PDMA Channel 1 Time-out Interrupt Enable Bit + * | | |0 = PDMA Channel 1 time-out interrupt Disable. + * | | |1 = PDMA Channel 1 time-out interrupt Enable. + * @var PDMA_T::SCATBA + * Offset: 0x43C PDMA Scatter-Gather Descriptor Table Base Address Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:16] |SCATBA |PDMA Scatter-gather Descriptor Table Address Register + * | | |In Scatter-Gather mode, this is the base address for calculating the next link - list address + * | | |The next link address equation is + * | | |Next Link Address = PDMA_SCATBA + PDMA_DSCT_NEXT. + * | | |Note: Only useful in Scatter-Gather mode. + * @var PDMA_T::TOC0_1 + * Offset: 0x440 PDMA Channel 0 and Channel 1 Time-out Counter Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |TOC0 |Time-out Counter for Channel 0 + * | | |This controls the period of time-out function for channel 0 + * | | |The calculation unit is based on TOUTPSC0 (PDMA_TOUTPSC[2:0]) clock. + * | | |Time-out period = (Period of time-out clock) * (16-bit TOCn),n = 0,1. + * |[31:16] |TOC1 |Time-out Counter for Channel 1 + * | | |This controls the period of time-out function for channel 1 + * | | |The calculation unit is based on TOUTPSC1 (PDMA_TOUTPSC[5:3]) clock + * | | |The example of time-out period can refer TOC0 bit description. + * @var PDMA_T::CHRST + * Offset: 0x460 PDMA Channel Reset Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |CHnRST |Channel N Reset + * | | |0 = corresponding channel n not reset. + * | | |1 = corresponding channel n is reset. + * @var PDMA_T::REQSEL0_3 + * Offset: 0x480 PDMA Channel 0 to Channel 3 Request Source Select Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[6:0] |REQSRC0 |Channel 0 Request Source Selection + * | | |This filed defines which peripheral is connected to PDMA channel 0 + * | | |User can configure the peripheral by setting REQSRC0. + * | | |0 = Disable PDMA. + * | | |1 = Reserved. + * | | |2 = Channel connects to USB_TX. + * | | |3 = Channel connects to USB_RX. + * | | |4 = Channel connects to UART0_TX. + * | | |5 = Channel connects to UART0_RX. + * | | |6 = Channel connects to UART1_TX. + * | | |7 = Channel connects to UART1_RX. + * | | |8 = Channel connects to UART2_TX. + * | | |9 = Channel connects to UART2_RX. + * | | |10 = Channel connects to UART3_TX. + * | | |11 = Channel connects to UART3_RX. + * | | |12 = Channel connects to UART4_TX. + * | | |13 = Channel connects to UART4_RX. + * | | |14 = Channel connects to UART5_TX. + * | | |15 = Channel connects to UART5_RX. + * | | |16 = Channel connects to USCI0_TX. + * | | |17 = Channel connects to USCI0_RX. + * | | |18 = Channel connects to USCI1_TX. + * | | |19 = Channel connects to USCI1_RX. + * | | |20 = Channel connects to QSPI0_TX. + * | | |21 = Channel connects to QSPI0_RX. + * | | |22 = Channel connects to SPI0_TX. + * | | |23 = Channel connects to SPI0_RX. + * | | |24 = Channel connects to SPI1_TX. + * | | |25 = Channel connects to SPI1_RX. + * | | |26 = Channel connects to SPI2_TX. + * | | |27 = Channel connects to SPI2_RX. + * | | |28 = Channel connects to SPI3_TX. + * | | |29 = Channel connects to SPI3_RX. + * | | |30 = Channel connects to ADC_RX. + * | | |32 = Channel connects to EPWM0_P1_RX. + * | | |33 = Channel connects to EPWM0_P2_RX. + * | | |34 = Channel connects to EPWM0_P3_RX. + * | | |35 = Channel connects to EPWM1_P1_RX. + * | | |36 = Channel connects to EPWM1_P2_RX. + * | | |37 = Channel connects to EPWM1_P3_RX. + * | | |38 = Channel connects to I2C0_TX. + * | | |39 = Channel connects to I2C0_RX. + * | | |40 = Channel connects to I2C1_TX. + * | | |41 = Channel connects to I2C1_RX. + * | | |42 = Channel connects to I2C2_TX. + * | | |43 = Channel connects to I2C2_RX. + * | | |44 = Channel connects to I2S0_TX. + * | | |45 = Channel connects to I2S0_RX. + * | | |46 = Channel connects to TMR0. + * | | |47 = Channel connects to TMR1. + * | | |48 = Channel connects to TMR2. + * | | |49 = Channel connects to TMR3. + * | | |50 = Channel connects to TMR4. + * | | |51 = Channel connects to TMR5. + * | | |52 = Channel connects to DAC0_TX. + * | | |53 = Channel connects to DAC1_TX. + * | | |54 = Channel connects to EPWM0_CH0_TX. + * | | |55 = Channel connects to EPWM0_CH1_TX. + * | | |56 = Channel connects to EPWM0_CH2_TX. + * | | |57 = Channel connects to EPWM0_CH3_TX. + * | | |58 = Channel connects to EPWM0_CH4_TX. + * | | |59 = Channel connects to EPWM0_CH5_TX. + * | | |60 = Channel connects to EPWM1_CH0_TX. + * | | |61 = Channel connects to EPWM1_CH1_TX. + * | | |62 = Channel connects to EPWM1_CH2_TX. + * | | |63 = Channel connects to EPWM1_CH3_TX. + * | | |64 = Channel connects to EPWM1_CH4_TX. + * | | |65 = Channel connects to EPWM1_CH5_TX. + * | | |Others = Reserved. + * | | |Note 1: A request source cannot assign to two channels at the same time. + * | | |Note 2: This field is useless when transfer between memory and memory. + * |[14:8] |REQSRC1 |Channel 1 Request Source Selection + * | | |This filed defines which peripheral is connected to PDMA channel 1 + * | | |User can configure the peripheral setting by REQSRC1. + * | | |Note: The channel configuration is the same as REQSRC0 field + * | | |Please refer to the explanation of REQSRC0. + * |[22:16] |REQSRC2 |Channel 2 Request Source Selection + * | | |This filed defines which peripheral is connected to PDMA channel 2 + * | | |User can configure the peripheral setting by REQSRC2. + * | | |Note: The channel configuration is the same as REQSRC0 field + * | | |Please refer to the explanation of REQSRC0. + * |[30:24] |REQSRC3 |Channel 3 Request Source Selection + * | | |This filed defines which peripheral is connected to PDMA channel 3 + * | | |User can configure the peripheral setting by REQSRC3. + * | | |Note: The channel configuration is the same as REQSRC0 field + * | | |Please refer to the explanation of REQSRC0. + * @var PDMA_T::REQSEL4_7 + * Offset: 0x484 PDMA Request Source Select Register 1 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[6:0] |REQSRC4 |Channel 4 Request Source Selection + * | | |This filed defines which peripheral is connected to PDMA channel 4 + * | | |User can configure the peripheral setting by REQSRC4. + * | | |Note: The channel configuration is the same as REQSRC0 field + * | | |Please refer to the explanation of REQSRC0. + * |[14:8] |REQSRC5 |Channel 5 Request Source Selection + * | | |This filed defines which peripheral is connected to PDMA channel 5 + * | | |User can configure the peripheral setting by REQSRC5. + * | | |Note: The channel configuration is the same as REQSRC0 field + * | | |Please refer to the explanation of REQSRC0. + * |[22:16] |REQSRC6 |Channel 6 Request Source Selection + * | | |This filed defines which peripheral is connected to PDMA channel 6 + * | | |User can configure the peripheral setting by REQSRC6. + * | | |Note: The channel configuration is the same as REQSRC0 field + * | | |Please refer to the explanation of REQSRC0. + * |[30:24] |REQSRC7 |Channel 7 Request Source Selection + * | | |This filed defines which peripheral is connected to PDMA channel 7 + * | | |User can configure the peripheral setting by REQSRC7. + * | | |Note: The channel configuration is the same as REQSRC0 field + * | | |Please refer to the explanation of REQSRC0. + */ + + DSCT_T DSCT[8]; /*!< [0x0000 ~ 0x007C] DMA Embedded Description Table 0~7 */ + __I uint32_t CURSCAT[8]; /*!< [0x0080~0x009C] Current Scatter-Gather Descriptor Table Address of PDMA Channel 0~7 */ + __I uint32_t RESERVE0[216]; + __IO uint32_t CHCTL; /*!< [0x0400] PDMA Channel Control Register */ + __O uint32_t PAUSE; /*!< [0x0404] PDMA Transfer Pause Control Register */ + __O uint32_t SWREQ; /*!< [0x0408] PDMA Software Request Register */ + __I uint32_t TRGSTS; /*!< [0x040c] PDMA Channel Request Status Register */ + __IO uint32_t PRISET; /*!< [0x0410] PDMA Fixed Priority Setting Register */ + __O uint32_t PRICLR; /*!< [0x0414] PDMA Fixed Priority Clear Register */ + __IO uint32_t INTEN; /*!< [0x0418] PDMA Interrupt Enable Register */ + __IO uint32_t INTSTS; /*!< [0x041c] PDMA Interrupt Status Register */ + __IO uint32_t ABTSTS; /*!< [0x0420] PDMA Channel Read/Write Target Abort Flag Register */ + __IO uint32_t TDSTS; /*!< [0x0424] PDMA Channel Transfer Done Flag Register */ + __IO uint32_t ALIGN; /*!< [0x0428] PDMA Transfer Alignment Status Register */ + __I uint32_t TACTSTS; /*!< [0x042c] PDMA Transfer Active Flag Register */ + __IO uint32_t TOUTPSC; /*!< [0x0430] PDMA Time-out Prescaler Register */ + __IO uint32_t TOUTEN; /*!< [0x0434] PDMA Time-out Enable Register */ + __IO uint32_t TOUTIEN; /*!< [0x0438] PDMA Time-out Interrupt Enable Register */ + __IO uint32_t SCATBA; /*!< [0x043c] PDMA Scatter-Gather Descriptor Table Base Address Register */ + __IO uint32_t TOC0_1; /*!< [0x0440] PDMA Channel 0 and Channel 1 Time-out Counter Register */ + __I uint32_t RESERVE1[7]; + __IO uint32_t CHRST; /*!< [0x0460] PDMA Channel Reset Register */ + __I uint32_t RESERVE2[7]; + __IO uint32_t REQSEL0_3; /*!< [0x0480] PDMA Channel 0 to Channel 3 Request Source Select Register */ + __IO uint32_t REQSEL4_7; /*!< [0x0484] PDMA Channel 4 to Channel 7 Request Source Select Register */ + __I uint32_t RESERVE4[30]; + STRIDE_T STRIDE[6]; /*!< [0x0500 ~ 0x052C] Stride function control register of PDMA Channel 0 ~ 5 */ + __IO uint32_t RESERVE5[52]; + REPEAT_T REPEAT[2]; /*!< [0x0600 ~ 0x060C] Repeat Count Function Control Register of PDMA Channel 0 ~ 1 */ +} PDMA_T; + + + + +/** + @addtogroup PDMA_CONST PDMA Bit Field Definition + Constant Definitions for PDMA Controller + @{ +*/ + +#define PDMA_DSCT_CTL_OPMODE_Pos (0) /*!< PDMA_T::DSCT_CTL: OPMODE Position */ +#define PDMA_DSCT_CTL_OPMODE_Msk (0x3ul << PDMA_DSCT_CTL_OPMODE_Pos) /*!< PDMA_T::DSCT_CTL: OPMODE Mask */ + +#define PDMA_DSCT_CTL_TXTYPE_Pos (2) /*!< PDMA_T::DSCT_CTL: TXTYPE Position */ +#define PDMA_DSCT_CTL_TXTYPE_Msk (0x1ul << PDMA_DSCT_CTL_TXTYPE_Pos) /*!< PDMA_T::DSCT_CTL: TXTYPE Mask */ + +#define PDMA_DSCT_CTL_BURSIZE_Pos (4) /*!< PDMA_T::DSCT_CTL: BURSIZE Position */ +#define PDMA_DSCT_CTL_BURSIZE_Msk (0x7ul << PDMA_DSCT_CTL_BURSIZE_Pos) /*!< PDMA_T::DSCT_CTL: BURSIZE Mask */ + +#define PDMA_DSCT_CTL_TBINTDIS_Pos (7) /*!< PDMA_T::DSCT_CTL: TBINTDIS Position */ +#define PDMA_DSCT_CTL_TBINTDIS_Msk (0x1ul << PDMA_DSCT_CTL_TBINTDIS_Pos) /*!< PDMA_T::DSCT_CTL: TBINTDIS Mask */ + +#define PDMA_DSCT_CTL_SAINC_Pos (8) /*!< PDMA_T::DSCT_CTL: SAINC Position */ +#define PDMA_DSCT_CTL_SAINC_Msk (0x3ul << PDMA_DSCT_CTL_SAINC_Pos) /*!< PDMA_T::DSCT_CTL: SAINC Mask */ + +#define PDMA_DSCT_CTL_DAINC_Pos (10) /*!< PDMA_T::DSCT_CTL: DAINC Position */ +#define PDMA_DSCT_CTL_DAINC_Msk (0x3ul << PDMA_DSCT_CTL_DAINC_Pos) /*!< PDMA_T::DSCT_CTL: DAINC Mask */ + +#define PDMA_DSCT_CTL_TXWIDTH_Pos (12) /*!< PDMA_T::DSCT_CTL: TXWIDTH Position */ +#define PDMA_DSCT_CTL_TXWIDTH_Msk (0x3ul << PDMA_DSCT_CTL_TXWIDTH_Pos) /*!< PDMA_T::DSCT_CTL: TXWIDTH Mask */ + +#define PDMA_DSCT_CTL_TXACK_Pos (14) /*!< PDMA_T::DSCT_CTL: TXACK Position */ +#define PDMA_DSCT_CTL_TXACK_Msk (0x1ul << PDMA_DSCT_CTL_TXACK_Pos) /*!< PDMA_T::DSCT_CTL: TXACK Mask */ + +#define PDMA_DSCT_CTL_STRIDEEN_Pos (15) /*!< PDMA_T::DSCT_CTL: STRIDEEN Position */ +#define PDMA_DSCT_CTL_STRIDEEN_Msk (0x1ul << PDMA_DSCT_CTL_STRIDEEN_Pos) /*!< PDMA_T::DSCT_CTL: STRIDEEN Mask */ + +#define PDMA_DSCT_CTL_TXCNT_Pos (16) /*!< PDMA_T::DSCT_CTL: TXCNT Position */ +#define PDMA_DSCT_CTL_TXCNT_Msk (0xfffful << PDMA_DSCT_CTL_TXCNT_Pos) /*!< PDMA_T::DSCT_CTL: TXCNT Mask */ + +#define PDMA_DSCT_SA_SA_Pos (0) /*!< PDMA_T::DSCT_SA: SA Position */ +#define PDMA_DSCT_SA_SA_Msk (0xfffffffful << PDMA_DSCT_SA_SA_Pos) /*!< PDMA_T::DSCT_SA: SA Mask */ + +#define PDMA_DSCT_DA_DA_Pos (0) /*!< PDMA_T::DSCT_DA: DA Position */ +#define PDMA_DSCT_DA_DA_Msk (0xfffffffful << PDMA_DSCT_DA_DA_Pos) /*!< PDMA_T::DSCT_DA: DA Mask */ + +#define PDMA_DSCT_NEXT_NEXT_Pos (0) /*!< PDMA_T::DSCT_NEXT: NEXT Position */ +#define PDMA_DSCT_NEXT_NEXT_Msk (0xfffful << PDMA_DSCT_NEXT_NEXT_Pos) /*!< PDMA_T::DSCT_NEXT: NEXT Mask */ + +#define PDMA_DSCT_NEXT_EXENEXT_Pos (16) /*!< PDMA_T::DSCT_FIRST: NEXT Position */ +#define PDMA_DSCT_NEXT_EXENEXT_Msk (0xfffful << PDMA_DSCT_NEXT_EXENEXT_Pos) /*!< PDMA_T::DSCT_FIRST: NEXT Mask */ + +#define PDMA_CURSCAT_CURADDR_Pos (0) /*!< PDMA_T::CURSCAT: CURADDR Position */ +#define PDMA_CURSCAT_CURADDR_Msk (0xfffffffful << PDMA_CURSCAT_CURADDR_Pos) /*!< PDMA_T::CURSCAT: CURADDR Mask */ + +#define PDMA_CHCTL_CHENn_Pos (0) /*!< PDMA_T::CHCTL: CHENn Position */ +#define PDMA_CHCTL_CHENn_Msk (0xfffful << PDMA_CHCTL_CHENn_Pos) /*!< PDMA_T::CHCTL: CHENn Mask */ + +#define PDMA_PAUSE_PAUSEn_Pos (0) /*!< PDMA_T::PAUSE: PAUSEn Position */ +#define PDMA_PAUSE_PAUSEn_Msk (0xfffful << PDMA_PAUSE_PAUSEn_Pos) /*!< PDMA_T::PAUSE: PAUSEn Mask */ + +#define PDMA_SWREQ_SWREQn_Pos (0) /*!< PDMA_T::SWREQ: SWREQn Position */ +#define PDMA_SWREQ_SWREQn_Msk (0xfffful << PDMA_SWREQ_SWREQn_Pos) /*!< PDMA_T::SWREQ: SWREQn Mask */ + +#define PDMA_TRGSTS_REQSTSn_Pos (0) /*!< PDMA_T::TRGSTS: REQSTSn Position */ +#define PDMA_TRGSTS_REQSTSn_Msk (0xfffful << PDMA_TRGSTS_REQSTSn_Pos) /*!< PDMA_T::TRGSTS: REQSTSn Mask */ + +#define PDMA_PRISET_FPRISETn_Pos (0) /*!< PDMA_T::PRISET: FPRISETn Position */ +#define PDMA_PRISET_FPRISETn_Msk (0xfffful << PDMA_PRISET_FPRISETn_Pos) /*!< PDMA_T::PRISET: FPRISETn Mask */ + +#define PDMA_PRICLR_FPRICLRn_Pos (0) /*!< PDMA_T::PRICLR: FPRICLRn Position */ +#define PDMA_PRICLR_FPRICLRn_Msk (0xfffful << PDMA_PRICLR_FPRICLRn_Pos) /*!< PDMA_T::PRICLR: FPRICLRn Mask */ + +#define PDMA_INTEN_INTENn_Pos (0) /*!< PDMA_T::INTEN: INTENn Position */ +#define PDMA_INTEN_INTENn_Msk (0xfffful << PDMA_INTEN_INTENn_Pos) /*!< PDMA_T::INTEN: INTENn Mask */ + +#define PDMA_INTSTS_ABTIF_Pos (0) /*!< PDMA_T::INTSTS: ABTIF Position */ +#define PDMA_INTSTS_ABTIF_Msk (0x1ul << PDMA_INTSTS_ABTIF_Pos) /*!< PDMA_T::INTSTS: ABTIF Mask */ + +#define PDMA_INTSTS_TDIF_Pos (1) /*!< PDMA_T::INTSTS: TDIF Position */ +#define PDMA_INTSTS_TDIF_Msk (0x1ul << PDMA_INTSTS_TDIF_Pos) /*!< PDMA_T::INTSTS: TDIF Mask */ + +#define PDMA_INTSTS_ALIGNF_Pos (2) /*!< PDMA_T::INTSTS: ALIGNF Position */ +#define PDMA_INTSTS_ALIGNF_Msk (0x1ul << PDMA_INTSTS_ALIGNF_Pos) /*!< PDMA_T::INTSTS: ALIGNF Mask */ + +#define PDMA_INTSTS_REQTOF0_Pos (8) /*!< PDMA_T::INTSTS: REQTOF0 Position */ +#define PDMA_INTSTS_REQTOF0_Msk (0x1ul << PDMA_INTSTS_REQTOF0_Pos) /*!< PDMA_T::INTSTS: REQTOF0 Mask */ + +#define PDMA_INTSTS_REQTOF1_Pos (9) /*!< PDMA_T::INTSTS: REQTOF1 Position */ +#define PDMA_INTSTS_REQTOF1_Msk (0x1ul << PDMA_INTSTS_REQTOF1_Pos) /*!< PDMA_T::INTSTS: REQTOF1 Mask */ + +#define PDMA_ABTSTS_ABTIF0_Pos (0) /*!< PDMA_T::ABTSTS: ABTIF0 Position */ +#define PDMA_ABTSTS_ABTIF0_Msk (0x1ul << PDMA_ABTSTS_ABTIF0_Pos) /*!< PDMA_T::ABTSTS: ABTIF0 Mask */ + +#define PDMA_ABTSTS_ABTIF1_Pos (1) /*!< PDMA_T::ABTSTS: ABTIF1 Position */ +#define PDMA_ABTSTS_ABTIF1_Msk (0x1ul << PDMA_ABTSTS_ABTIF1_Pos) /*!< PDMA_T::ABTSTS: ABTIF1 Mask */ + +#define PDMA_ABTSTS_ABTIF2_Pos (2) /*!< PDMA_T::ABTSTS: ABTIF2 Position */ +#define PDMA_ABTSTS_ABTIF2_Msk (0x1ul << PDMA_ABTSTS_ABTIF2_Pos) /*!< PDMA_T::ABTSTS: ABTIF2 Mask */ + +#define PDMA_ABTSTS_ABTIF3_Pos (3) /*!< PDMA_T::ABTSTS: ABTIF3 Position */ +#define PDMA_ABTSTS_ABTIF3_Msk (0x1ul << PDMA_ABTSTS_ABTIF3_Pos) /*!< PDMA_T::ABTSTS: ABTIF3 Mask */ + +#define PDMA_ABTSTS_ABTIF4_Pos (4) /*!< PDMA_T::ABTSTS: ABTIF4 Position */ +#define PDMA_ABTSTS_ABTIF4_Msk (0x1ul << PDMA_ABTSTS_ABTIF4_Pos) /*!< PDMA_T::ABTSTS: ABTIF4 Mask */ + +#define PDMA_ABTSTS_ABTIF5_Pos (5) /*!< PDMA_T::ABTSTS: ABTIF5 Position */ +#define PDMA_ABTSTS_ABTIF5_Msk (0x1ul << PDMA_ABTSTS_ABTIF5_Pos) /*!< PDMA_T::ABTSTS: ABTIF5 Mask */ + +#define PDMA_ABTSTS_ABTIF6_Pos (6) /*!< PDMA_T::ABTSTS: ABTIF6 Position */ +#define PDMA_ABTSTS_ABTIF6_Msk (0x1ul << PDMA_ABTSTS_ABTIF6_Pos) /*!< PDMA_T::ABTSTS: ABTIF6 Mask */ + +#define PDMA_ABTSTS_ABTIF7_Pos (7) /*!< PDMA_T::ABTSTS: ABTIF7 Position */ +#define PDMA_ABTSTS_ABTIF7_Msk (0x1ul << PDMA_ABTSTS_ABTIF7_Pos) /*!< PDMA_T::ABTSTS: ABTIF7 Mask */ + +#define PDMA_ABTSTS_ABTIF8_Pos (8) /*!< PDMA_T::ABTSTS: ABTIF8 Position */ +#define PDMA_ABTSTS_ABTIF8_Msk (0x1ul << PDMA_ABTSTS_ABTIF8_Pos) /*!< PDMA_T::ABTSTS: ABTIF8 Mask */ + +#define PDMA_ABTSTS_ABTIF9_Pos (9) /*!< PDMA_T::ABTSTS: ABTIF9 Position */ +#define PDMA_ABTSTS_ABTIF9_Msk (0x1ul << PDMA_ABTSTS_ABTIF9_Pos) /*!< PDMA_T::ABTSTS: ABTIF9 Mask */ + +#define PDMA_ABTSTS_ABTIF10_Pos (10) /*!< PDMA_T::ABTSTS: ABTIF10 Position */ +#define PDMA_ABTSTS_ABTIF10_Msk (0x1ul << PDMA_ABTSTS_ABTIF10_Pos) /*!< PDMA_T::ABTSTS: ABTIF10 Mask */ + +#define PDMA_ABTSTS_ABTIF11_Pos (11) /*!< PDMA_T::ABTSTS: ABTIF11 Position */ +#define PDMA_ABTSTS_ABTIF11_Msk (0x1ul << PDMA_ABTSTS_ABTIF11_Pos) /*!< PDMA_T::ABTSTS: ABTIF11 Mask */ + +#define PDMA_ABTSTS_ABTIF12_Pos (12) /*!< PDMA_T::ABTSTS: ABTIF12 Position */ +#define PDMA_ABTSTS_ABTIF12_Msk (0x1ul << PDMA_ABTSTS_ABTIF12_Pos) /*!< PDMA_T::ABTSTS: ABTIF12 Mask */ + +#define PDMA_ABTSTS_ABTIF13_Pos (13) /*!< PDMA_T::ABTSTS: ABTIF13 Position */ +#define PDMA_ABTSTS_ABTIF13_Msk (0x1ul << PDMA_ABTSTS_ABTIF13_Pos) /*!< PDMA_T::ABTSTS: ABTIF13 Mask */ + +#define PDMA_ABTSTS_ABTIF14_Pos (14) /*!< PDMA_T::ABTSTS: ABTIF14 Position */ +#define PDMA_ABTSTS_ABTIF14_Msk (0x1ul << PDMA_ABTSTS_ABTIF14_Pos) /*!< PDMA_T::ABTSTS: ABTIF14 Mask */ + +#define PDMA_ABTSTS_ABTIF15_Pos (15) /*!< PDMA_T::ABTSTS: ABTIF15 Position */ +#define PDMA_ABTSTS_ABTIF15_Msk (0x1ul << PDMA_ABTSTS_ABTIF15_Pos) /*!< PDMA_T::ABTSTS: ABTIF15 Mask */ + +#define PDMA_TDSTS_TDIF0_Pos (0) /*!< PDMA_T::TDSTS: TDIF0 Position */ +#define PDMA_TDSTS_TDIF0_Msk (0x1ul << PDMA_TDSTS_TDIF0_Pos) /*!< PDMA_T::TDSTS: TDIF0 Mask */ + +#define PDMA_TDSTS_TDIF1_Pos (1) /*!< PDMA_T::TDSTS: TDIF1 Position */ +#define PDMA_TDSTS_TDIF1_Msk (0x1ul << PDMA_TDSTS_TDIF1_Pos) /*!< PDMA_T::TDSTS: TDIF1 Mask */ + +#define PDMA_TDSTS_TDIF2_Pos (2) /*!< PDMA_T::TDSTS: TDIF2 Position */ +#define PDMA_TDSTS_TDIF2_Msk (0x1ul << PDMA_TDSTS_TDIF2_Pos) /*!< PDMA_T::TDSTS: TDIF2 Mask */ + +#define PDMA_TDSTS_TDIF3_Pos (3) /*!< PDMA_T::TDSTS: TDIF3 Position */ +#define PDMA_TDSTS_TDIF3_Msk (0x1ul << PDMA_TDSTS_TDIF3_Pos) /*!< PDMA_T::TDSTS: TDIF3 Mask */ + +#define PDMA_TDSTS_TDIF4_Pos (4) /*!< PDMA_T::TDSTS: TDIF4 Position */ +#define PDMA_TDSTS_TDIF4_Msk (0x1ul << PDMA_TDSTS_TDIF4_Pos) /*!< PDMA_T::TDSTS: TDIF4 Mask */ + +#define PDMA_TDSTS_TDIF5_Pos (5) /*!< PDMA_T::TDSTS: TDIF5 Position */ +#define PDMA_TDSTS_TDIF5_Msk (0x1ul << PDMA_TDSTS_TDIF5_Pos) /*!< PDMA_T::TDSTS: TDIF5 Mask */ + +#define PDMA_TDSTS_TDIF6_Pos (6) /*!< PDMA_T::TDSTS: TDIF6 Position */ +#define PDMA_TDSTS_TDIF6_Msk (0x1ul << PDMA_TDSTS_TDIF6_Pos) /*!< PDMA_T::TDSTS: TDIF6 Mask */ + +#define PDMA_TDSTS_TDIF7_Pos (7) /*!< PDMA_T::TDSTS: TDIF7 Position */ +#define PDMA_TDSTS_TDIF7_Msk (0x1ul << PDMA_TDSTS_TDIF7_Pos) /*!< PDMA_T::TDSTS: TDIF7 Mask */ + +#define PDMA_TDSTS_TDIF8_Pos (8) /*!< PDMA_T::TDSTS: TDIF8 Position */ +#define PDMA_TDSTS_TDIF8_Msk (0x1ul << PDMA_TDSTS_TDIF8_Pos) /*!< PDMA_T::TDSTS: TDIF8 Mask */ + +#define PDMA_TDSTS_TDIF9_Pos (9) /*!< PDMA_T::TDSTS: TDIF9 Position */ +#define PDMA_TDSTS_TDIF9_Msk (0x1ul << PDMA_TDSTS_TDIF9_Pos) /*!< PDMA_T::TDSTS: TDIF9 Mask */ + +#define PDMA_TDSTS_TDIF10_Pos (10) /*!< PDMA_T::TDSTS: TDIF10 Position */ +#define PDMA_TDSTS_TDIF10_Msk (0x1ul << PDMA_TDSTS_TDIF10_Pos) /*!< PDMA_T::TDSTS: TDIF10 Mask */ + +#define PDMA_TDSTS_TDIF11_Pos (11) /*!< PDMA_T::TDSTS: TDIF11 Position */ +#define PDMA_TDSTS_TDIF11_Msk (0x1ul << PDMA_TDSTS_TDIF11_Pos) /*!< PDMA_T::TDSTS: TDIF11 Mask */ + +#define PDMA_TDSTS_TDIF12_Pos (12) /*!< PDMA_T::TDSTS: TDIF12 Position */ +#define PDMA_TDSTS_TDIF12_Msk (0x1ul << PDMA_TDSTS_TDIF12_Pos) /*!< PDMA_T::TDSTS: TDIF12 Mask */ + +#define PDMA_TDSTS_TDIF13_Pos (13) /*!< PDMA_T::TDSTS: TDIF13 Position */ +#define PDMA_TDSTS_TDIF13_Msk (0x1ul << PDMA_TDSTS_TDIF13_Pos) /*!< PDMA_T::TDSTS: TDIF13 Mask */ + +#define PDMA_TDSTS_TDIF14_Pos (14) /*!< PDMA_T::TDSTS: TDIF14 Position */ +#define PDMA_TDSTS_TDIF14_Msk (0x1ul << PDMA_TDSTS_TDIF14_Pos) /*!< PDMA_T::TDSTS: TDIF14 Mask */ + +#define PDMA_TDSTS_TDIF15_Pos (15) /*!< PDMA_T::TDSTS: TDIF15 Position */ +#define PDMA_TDSTS_TDIF15_Msk (0x1ul << PDMA_TDSTS_TDIF15_Pos) /*!< PDMA_T::TDSTS: TDIF15 Mask */ + +#define PDMA_ALIGN_ALIGNn_Pos (0) /*!< PDMA_T::ALIGN: ALIGNn Position */ +#define PDMA_ALIGN_ALIGNn_Msk (0xfffful << PDMA_ALIGN_ALIGNn_Pos) /*!< PDMA_T::ALIGN: ALIGNn Mask */ + +#define PDMA_TACTSTS_TXACTFn_Pos (0) /*!< PDMA_T::TACTSTS: TXACTFn Position */ +#define PDMA_TACTSTS_TXACTFn_Msk (0xfffful << PDMA_TACTSTS_TXACTFn_Pos) /*!< PDMA_T::TACTSTS: TXACTFn Mask */ + +#define PDMA_TOUTPSC_TOUTPSC0_Pos (0) /*!< PDMA_T::TOUTPSC: TOUTPSC0 Position */ +#define PDMA_TOUTPSC_TOUTPSC0_Msk (0x7ul << PDMA_TOUTPSC_TOUTPSC0_Pos) /*!< PDMA_T::TOUTPSC: TOUTPSC0 Mask */ + +#define PDMA_TOUTPSC_TOUTPSC1_Pos (4) /*!< PDMA_T::TOUTPSC: TOUTPSC1 Position */ +#define PDMA_TOUTPSC_TOUTPSC1_Msk (0x7ul << PDMA_TOUTPSC_TOUTPSC1_Pos) /*!< PDMA_T::TOUTPSC: TOUTPSC1 Mask */ + +#define PDMA_TOUTEN_TOUTENn_Pos (0) /*!< PDMA_T::TOUTEN: TOUTENn Position */ +#define PDMA_TOUTEN_TOUTENn_Msk (0x3ul << PDMA_TOUTEN_TOUTENn_Pos) /*!< PDMA_T::TOUTEN: TOUTENn Mask */ + +#define PDMA_TOUTIEN_TOUTIENn_Pos (0) /*!< PDMA_T::TOUTIEN: TOUTIENn Position */ +#define PDMA_TOUTIEN_TOUTIENn_Msk (0x3ul << PDMA_TOUTIEN_TOUTIENn_Pos) /*!< PDMA_T::TOUTIEN: TOUTIENn Mask */ + +#define PDMA_SCATBA_SCATBA_Pos (16) /*!< PDMA_T::SCATBA: SCATBA Position */ +#define PDMA_SCATBA_SCATBA_Msk (0xfffful << PDMA_SCATBA_SCATBA_Pos) /*!< PDMA_T::SCATBA: SCATBA Mask */ + +#define PDMA_TOC0_1_TOC0_Pos (0) /*!< PDMA_T::TOC0_1: TOC0 Position */ +#define PDMA_TOC0_1_TOC0_Msk (0xfffful << PDMA_TOC0_1_TOC0_Pos) /*!< PDMA_T::TOC0_1: TOC0 Mask */ + +#define PDMA_TOC0_1_TOC1_Pos (16) /*!< PDMA_T::TOC0_1: TOC1 Position */ +#define PDMA_TOC0_1_TOC1_Msk (0xfffful << PDMA_TOC0_1_TOC1_Pos) /*!< PDMA_T::TOC0_1: TOC1 Mask */ + +#define PDMA_CHRST_CHnRST_Pos (0) /*!< PDMA_T::CHRST: CHnRST Position */ +#define PDMA_CHRST_CHnRST_Msk (0xfffful << PDMA_CHRST_CHnRST_Pos) /*!< PDMA_T::CHRST: CHnRST Mask */ + +#define PDMA_REQSEL0_3_REQSRC0_Pos (0) /*!< PDMA_T::REQSEL0_3: REQSRC0 Position */ +#define PDMA_REQSEL0_3_REQSRC0_Msk (0x7ful << PDMA_REQSEL0_3_REQSRC0_Pos) /*!< PDMA_T::REQSEL0_3: REQSRC0 Mask */ + +#define PDMA_REQSEL0_3_REQSRC1_Pos (8) /*!< PDMA_T::REQSEL0_3: REQSRC1 Position */ +#define PDMA_REQSEL0_3_REQSRC1_Msk (0x7ful << PDMA_REQSEL0_3_REQSRC1_Pos) /*!< PDMA_T::REQSEL0_3: REQSRC1 Mask */ + +#define PDMA_REQSEL0_3_REQSRC2_Pos (16) /*!< PDMA_T::REQSEL0_3: REQSRC2 Position */ +#define PDMA_REQSEL0_3_REQSRC2_Msk (0x7ful << PDMA_REQSEL0_3_REQSRC2_Pos) /*!< PDMA_T::REQSEL0_3: REQSRC2 Mask */ + +#define PDMA_REQSEL0_3_REQSRC3_Pos (24) /*!< PDMA_T::REQSEL0_3: REQSRC3 Position */ +#define PDMA_REQSEL0_3_REQSRC3_Msk (0x7ful << PDMA_REQSEL0_3_REQSRC3_Pos) /*!< PDMA_T::REQSEL0_3: REQSRC3 Mask */ + +#define PDMA_REQSEL4_7_REQSRC4_Pos (0) /*!< PDMA_T::REQSEL4_7: REQSRC4 Position */ +#define PDMA_REQSEL4_7_REQSRC4_Msk (0x7ful << PDMA_REQSEL4_7_REQSRC4_Pos) /*!< PDMA_T::REQSEL4_7: REQSRC4 Mask */ + +#define PDMA_REQSEL4_7_REQSRC5_Pos (8) /*!< PDMA_T::REQSEL4_7: REQSRC5 Position */ +#define PDMA_REQSEL4_7_REQSRC5_Msk (0x7ful << PDMA_REQSEL4_7_REQSRC5_Pos) /*!< PDMA_T::REQSEL4_7: REQSRC5 Mask */ + +#define PDMA_REQSEL4_7_REQSRC6_Pos (16) /*!< PDMA_T::REQSEL4_7: REQSRC6 Position */ +#define PDMA_REQSEL4_7_REQSRC6_Msk (0x7ful << PDMA_REQSEL4_7_REQSRC6_Pos) /*!< PDMA_T::REQSEL4_7: REQSRC6 Mask */ + +#define PDMA_REQSEL4_7_REQSRC7_Pos (24) /*!< PDMA_T::REQSEL4_7: REQSRC7 Position */ +#define PDMA_REQSEL4_7_REQSRC7_Msk (0x7ful << PDMA_REQSEL4_7_REQSRC7_Pos) /*!< PDMA_T::REQSEL4_7: REQSRC7 Mask */ + +#define PDMA_STCRn_STC_Pos (0) /*!< PDMA_T::STCRn: STC Position */ +#define PDMA_STCRn_STC_Msk (0xfffful << PDMA_STCRn_STC_Pos) /*!< PDMA_T::STCRn: STC Mask */ + +#define PDMA_ASOCRn_SASOL_Pos (0) /*!< PDMA_T::ASOCRn: SASOL Position */ +#define PDMA_ASOCRn_SASOL_Msk (0xfffful << PDMA_ASOCRn_SASOL_Pos) /*!< PDMA_T::ASOCRn: SASOL Mask */ + +#define PDMA_ASOCRn_DASOL_Pos (16) /*!< PDMA_T::ASOCRn: DASOL Position */ +#define PDMA_ASOCRn_DASOL_Msk (0xfffful << PDMA_ASOCRn_DASOL_Pos) /*!< PDMA_T::ASOCRn: DASOL Mask */ + +#define PDMA_AICTLn_SAICNT_Pos (0) /*!< PDMA_T::AICTLn: SAICNT Position */ +#define PDMA_AICTLn_SAICNT_Msk (0xfffful << PDMA_ASOCRn_SASOL_Pos) /*!< PDMA_T::AICTLn: SAICNT Mask */ + +#define PDMA_AICTLn_DAICNT_Pos (16) /*!< PDMA_T::AICTLn: DAICNT Position */ +#define PDMA_AICTLn_DAICNT_Msk (0xfffful << PDMA_ASOCRn_DASOL_Pos) /*!< PDMA_T::AICTLn: DAICNT Mask */ + +#define PDMA_RCNTn_RCNT_Pos (0) /*!< PDMA_T::RCNTn: RCNT Position */ +#define PDMA_RCNTn_RCNT_Msk (0xfffful << PDMA_STCRn_RCNT_Pos) /*!< PDMA_T::RCNTn: RCNT Mask */ + +/**@}*/ /* PDMA_CONST */ +/**@}*/ /* end of PDMA register group */ +/**@}*/ /* end of REGISTER group */ + + +#endif /* __PDMA_REG_H__ */ diff --git a/Ubiquitous/XiZi/board/nuvoton-m2354/third_party_driver/include/Regs/qei_reg.h b/Ubiquitous/XiZi/board/nuvoton-m2354/third_party_driver/include/Regs/qei_reg.h new file mode 100644 index 0000000..42a14c9 --- /dev/null +++ b/Ubiquitous/XiZi/board/nuvoton-m2354/third_party_driver/include/Regs/qei_reg.h @@ -0,0 +1,308 @@ +/**************************************************************************//** + * @file qei_reg.h + * @version V1.00 + * @brief QEI register definition header file + * + * @copyright SPDX-License-Identifier: Apache-2.0 + * @copyright Copyright (C) 2020 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ +#ifndef __QEI_REG_H__ +#define __QEI_REG_H__ + +/** @addtogroup REGISTER Control Register + + @{ + +*/ + +/*---------------------- Quadrature Encoder Interface -------------------------*/ +/** + @addtogroup QEI Quadrature Encoder Interface(QEI) + Memory Mapped Structure for QEI Controller + @{ +*/ + +typedef struct +{ + + + /** + * @var QEI_T::CNT + * Offset: 0x00 QEI Counter Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |CNT |Quadrature Encoder Interface Counter + * | | |A 32-bit up/down counter + * | | |When an effective phase pulse is detected, this counter is increased by one if the bit DIRF (QEI_STATUS[8]) is one or decreased by one if the bit DIRF is zero + * | | |This register performs an integrator which count value is proportional to the encoder position + * | | |The pulse counter may be initialized to a predetermined value by one of three events occurs: + * | | |1. Software is written if QEIEN (QEI_CTL[29]) = 0. + * | | |2. Compare-match event if QEIEN=1 and QEI is in compare-counting mode. + * | | |3. Index signal change if QEIEN=1 and IDXRLDEN (QEI_CTL[27])=1. + * @var QEI_T::CNTHOLD + * Offset: 0x04 QEI Counter Hold Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |CNTHOLD |Quadrature Encoder Interface Counter Hold + * | | |When bit HOLDCNT (QEI_CTL[24]) goes from low to high, the CNT(QEI_CNT[31:0]) is copied into CNTHOLD (QEI_CNTHOLD[31:0]) register. + * @var QEI_T::CNTLATCH + * Offset: 0x08 QEI Counter Index Latch Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |CNTLATCH |Quadrature Encoder Interface Counter Index Latch + * | | |When the IDXF (QEI_STATUS[0]) bit is set, the CNT(QEI_CNT[31:0]) is copied into CNTLATCH (QEI_CNTLATCH[31:0]) register. + * @var QEI_T::CNTCMP + * Offset: 0x0C QEI Counter Compare Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |CNTCMP |Quadrature Encoder Interface Counter Compare + * | | |If the QEI controller is in the compare-counting mode CMPEN (QEI_CTL[28]) =1, when the value of CNT(QEI_CNT[31:0]) matches CNTCMP(QEI_CNTCMP[31:0]), CMPF will be set + * | | |This register is software writable. + * @var QEI_T::CNTMAX + * Offset: 0x14 QEI Pre-set Maximum Count Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |CNTMAX |Quadrature Encoder Interface Preset Maximum Count + * | | |This register value determined by user stores the maximum value which may be the number of the QEI counter for the QEI controller compare-counting mode + * @var QEI_T::CTL + * Offset: 0x18 QEI Controller Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[2:0] |NFCLKSEL |Noise Filter Clock Pre-divide Selection + * | | |To determine the sampling frequency of the Noise Filter clock . + * | | |000 = QEI_CLK. + * | | |001 = QEI_CLK/2. + * | | |010 = QEI_CLK/4. + * | | |011 = QEI_CLK/16. + * | | |100 = QEI_CLK/32. + * | | |101 = QEI_CLK/64. + * |[3] |NFDIS |QEI Controller Input Noise Filter Disable Bit + * | | |0 = The noise filter of QEI controller Enabled. + * | | |1 = The noise filter of QEI controller Disabled. + * |[4] |CHAEN |QEA Input to QEI Controller Enable Bit + * | | |0 = QEA input to QEI Controller Disabled. + * | | |1 = QEA input to QEI Controller Enabled. + * |[5] |CHBEN |QEB Input to QEI Controller Enable Bit + * | | |0 = QEB input to QEI Controller Disabled. + * | | |1 = QEB input to QEI Controller Enabled. + * |[6] |IDXEN |IDX Input to QEI Controller Enable Bit + * | | |0 = IDX input to QEI Controller Disabled. + * | | |1 = IDX input to QEI Controller Enabled. + * |[9:8] |MODE |QEI Counting Mode Selection + * | | |There are four quadrature encoder pulse counter operation modes. + * | | |00 = X4 Free-counting Mode. + * | | |01 = X2 Free-counting Mode. + * | | |10 = X4 Compare-counting Mode. + * | | |11 = X2 Compare-counting Mode. + * |[12] |CHAINV |Inverse QEA Input Polarity + * | | |0 = Not inverse QEA input polarity. + * | | |1 = QEA input polarity is inverse to QEI controller. + * |[13] |CHBINV |Inverse QEB Input Polarity + * | | |0 = Not inverse QEB input polarity. + * | | |1 = QEB input polarity is inverse to QEI controller. + * |[14] |IDXINV |Inverse IDX Input Polarity + * | | |0 = Not inverse IDX input polarity. + * | | |1 = IDX input polarity is inverse to QEI controller. + * |[16] |OVUNIEN |OVUNF Trigger QEI Interrupt Enable Bit + * | | |0 = OVUNF can trigger QEI controller interrupt Disabled. + * | | |1 = OVUNF can trigger QEI controller interrupt Enabled. + * |[17] |DIRIEN |DIRCHGF Trigger QEI Interrupt Enable Bit + * | | |0 = DIRCHGF can trigger QEI controller interrupt Disabled. + * | | |1 = DIRCHGF can trigger QEI controller interrupt Enabled. + * |[18] |CMPIEN |CMPF Trigger QEI Interrupt Enable Bit + * | | |0 = CMPF can trigger QEI controller interrupt Disabled. + * | | |1 = CMPF can trigger QEI controller interrupt Enabled. + * |[19] |IDXIEN |IDXF Trigger QEI Interrupt Enable Bit + * | | |0 = The IDXF can trigger QEI interrupt Disabled. + * | | |1 = The IDXF can trigger QEI interrupt Enabled. + * |[20] |HOLDTMR0 |Hold QEI_CNT by Timer 0 + * | | |0 = TIF (TIMER0_INTSTS[0]) has no effect on HOLDCNT. + * | | |1 = A rising edge of bit TIF(TIMER0_INTSTS[0]) in timer 0 sets HOLDCNT to 1. + * |[21] |HOLDTMR1 |Hold QEI_CNT by Timer 1 + * | | |0 = TIF(TIMER1_INTSTS[0]) has no effect on HOLDCNT. + * | | |1 = A rising edge of bit TIF (TIMER1_INTSTS[0]) in timer 1 sets HOLDCNT to 1. + * |[22] |HOLDTMR2 |Hold QEI_CNT by Timer 2 + * | | |0 = TIF(TIMER2_INTSTS[0]) has no effect on HOLDCNT. + * | | |1 = A rising edge of bit TIF(TIMER2_INTSTS[0]) in timer 2 sets HOLDCNT to 1. + * |[23] |HOLDTMR3 |Hold QEI_CNT by Timer 3 + * | | |0 = TIF (TIMER3_INTSTS[0]) has no effect on HOLDCNT. + * | | |1 = A rising edge of bit TIF(TIMER3_INTSTS[0]) in timer 3 sets HOLDCNT to 1. + * |[24] |HOLDCNT |Hold QEI_CNT Control + * | | |When this bit is set from low to high, the CNT(QEI_CNT[31:0]) is copied into QEI_CNTHOLD + * | | |This bit may be set by writing 1 to it or Timer0~Timer3 interrupt flag TIF (TIMERx_INTSTS[0]). + * | | |0 = No operation. + * | | |1 = QEI_CNT content is captured and stored in QEI_CNTHOLD. + * | | |Note: This bit is automatically cleared after QEI_CNTHOLD holds QEI_CNT value. + * |[25] |IDXLATEN |Index Latch QEI_CNT Enable Bit + * | | |If this bit is set to high, the QEI_CNT content will be latched into QEI_CNTLATCH at every rising on signal CHX. + * | | |0 = The index signal latch QEI counter function Disabled. + * | | |1 = The index signal latch QEI counter function Enabled. + * |[27] |IDXRLDEN |Index Trigger QEI_CNT Reload Enable Bit + * | | |When this bit is high and a rising edge comes on signal CHX, the QEI_CNT will be reset to zero if the counter is in up-counting type (DIRF = 1); while the QEI_CNT will be reloaded with CNTMAX (QEI_CNTMAX[31:0]) content if the counter is in down-counting type (DIRF = 0). + * | | |0 = Reload function Disabled. + * | | |1 = QEI_CNT re-initialized by Index signal Enabled. + * |[28] |CMPEN |the Compare Function Enable Bit + * | | |The compare function in QEI controller is to compare the dynamic counting QEI_CNT with the compare register CNTCMP( QEI_CNTCMP[31:0]), if CNT(QEI_CNT[31:0]) reaches CNTCMP( QEI_CNTCMP[31:0]), the flag CMPF will be set. + * | | |0 = Compare function Disabled. + * | | |1 = Compare function Enabled. + * |[29] |QEIEN |Quadrature Encoder Interface Controller Enable Bit + * | | |0 = QEI controller function Disabled. + * | | |1 = QEI controller function Enabled. + * @var QEI_T::STATUS + * Offset: 0x2C QEI Controller Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |IDXF |IDX Detected Flag + * | | |When the QEI controller detects a rising edge on signal CHX it will set flag IDXF to high. + * | | |0 = No rising edge detected on signal CHX. + * | | |1 = A rising edge occurs on signal CHX. + * | | |Note: This bit is only cleared by writing 1 to it. + * |[1] |CMPF |Compare-match Flag + * | | |If the QEI compare function is enabled, the flag is set by hardware while QEI counter up or down counts and reach to the CNTCMP(QEI_CNTCMP[31:0]). + * | | |0 = QEI counter does not match with CNTCMP(QEI_CNTCMP[31:0]). + * | | |1 = QEI counter counts to the same as CNTCMP(QEI_CNTCMP[31:0]). + * | | |Note: This bit is only cleared by writing 1 to it. + * |[2] |OVUNF |QEI Counter Overflow or Underflow Flag + * | | |Flag is set by hardware while QEI_CNT overflows from 0xFFFF_FFFF to zero in free-counting mode or from the CNTMAX (QEI_CNTMAX[31:0]) to zero in compare-counting mode + * | | |Similarly, the flag is set wile QEI counter underflow from zero to 0xFFFF_FFFF or CNTMAX (QEI_CNTMAX[31:0]). + * | | |0 = No overflow or underflow occurs in QEI counter. + * | | |1 = QEI counter occurs counting overflow or underflow. + * | | |Note: This bit is only cleared by writing 1 to it. + * |[3] |DIRCHGF |Direction Change Flag + * | | |Flag is set by hardware while QEI counter counting direction is changed + * | | |Software can clear this bit by writing 1 to it. + * | | |0 = No change in QEI counter counting direction. + * | | |1 = QEI counter counting direction is changed. + * | | |Note: This bit is only cleared by writing 1 to it. + * |[8] |DIRF |QEI Counter Counting Direction Indication + * | | |0 = QEI Counter is in down-counting. + * | | |1 = QEI Counter is in up-counting. + * | | |Note: This bit is set/reset by hardware according to the phase detection between CHA and CHB. + */ + __IO uint32_t CNT; /*!< [0x0000] QEI Counter Register */ + __IO uint32_t CNTHOLD; /*!< [0x0004] QEI Counter Hold Register */ + __IO uint32_t CNTLATCH; /*!< [0x0008] QEI Counter Index Latch Register */ + __IO uint32_t CNTCMP; /*!< [0x000c] QEI Counter Compare Register */ + __I uint32_t RESERVE0[1]; + __IO uint32_t CNTMAX; /*!< [0x0014] QEI Pre-set Maximum Count Register */ + __IO uint32_t CTL; /*!< [0x0018] QEI Controller Control Register */ + __I uint32_t RESERVE1[4]; + __IO uint32_t STATUS; /*!< [0x002c] QEI Controller Status Register */ + +} QEI_T; + +/** + @addtogroup QEI_CONST QEI Bit Field Definition + Constant Definitions for QEI Controller + @{ +*/ + +#define QEI_CNT_CNT_Pos (0) /*!< QEI_T::CNT: CNT Position */ +#define QEI_CNT_CNT_Msk (0xfffffffful << QEI_CNT_CNT_Pos) /*!< QEI_T::CNT: CNT Mask */ + +#define QEI_CNTHOLD_CNTHOLD_Pos (0) /*!< QEI_T::CNTHOLD: CNTHOLD Position */ +#define QEI_CNTHOLD_CNTHOLD_Msk (0xfffffffful << QEI_CNTHOLD_CNTHOLD_Pos) /*!< QEI_T::CNTHOLD: CNTHOLD Mask */ + +#define QEI_CNTLATCH_CNTLATCH_Pos (0) /*!< QEI_T::CNTLATCH: CNTLATCH Position */ +#define QEI_CNTLATCH_CNTLATCH_Msk (0xfffffffful << QEI_CNTLATCH_CNTLATCH_Pos) /*!< QEI_T::CNTLATCH: CNTLATCH Mask */ + +#define QEI_CNTCMP_CNTCMP_Pos (0) /*!< QEI_T::CNTCMP: CNTCMP Position */ +#define QEI_CNTCMP_CNTCMP_Msk (0xfffffffful << QEI_CNTCMP_CNTCMP_Pos) /*!< QEI_T::CNTCMP: CNTCMP Mask */ + +#define QEI_CNTMAX_CNTMAX_Pos (0) /*!< QEI_T::CNTMAX: CNTMAX Position */ +#define QEI_CNTMAX_CNTMAX_Msk (0xfffffffful << QEI_CNTMAX_CNTMAX_Pos) /*!< QEI_T::CNTMAX: CNTMAX Mask */ + +#define QEI_CTL_NFCLKSEL_Pos (0) /*!< QEI_T::CTL: NFCLKSEL Position */ +#define QEI_CTL_NFCLKSEL_Msk (0x7ul << QEI_CTL_NFCLKSEL_Pos) /*!< QEI_T::CTL: NFCLKSEL Mask */ + +#define QEI_CTL_NFDIS_Pos (3) /*!< QEI_T::CTL: NFDIS Position */ +#define QEI_CTL_NFDIS_Msk (0x1ul << QEI_CTL_NFDIS_Pos) /*!< QEI_T::CTL: NFDIS Mask */ + +#define QEI_CTL_CHAEN_Pos (4) /*!< QEI_T::CTL: CHAEN Position */ +#define QEI_CTL_CHAEN_Msk (0x1ul << QEI_CTL_CHAEN_Pos) /*!< QEI_T::CTL: CHAEN Mask */ + +#define QEI_CTL_CHBEN_Pos (5) /*!< QEI_T::CTL: CHBEN Position */ +#define QEI_CTL_CHBEN_Msk (0x1ul << QEI_CTL_CHBEN_Pos) /*!< QEI_T::CTL: CHBEN Mask */ + +#define QEI_CTL_IDXEN_Pos (6) /*!< QEI_T::CTL: IDXEN Position */ +#define QEI_CTL_IDXEN_Msk (0x1ul << QEI_CTL_IDXEN_Pos) /*!< QEI_T::CTL: IDXEN Mask */ + +#define QEI_CTL_MODE_Pos (8) /*!< QEI_T::CTL: MODE Position */ +#define QEI_CTL_MODE_Msk (0x3ul << QEI_CTL_MODE_Pos) /*!< QEI_T::CTL: MODE Mask */ + +#define QEI_CTL_CHAINV_Pos (12) /*!< QEI_T::CTL: CHAINV Position */ +#define QEI_CTL_CHAINV_Msk (0x1ul << QEI_CTL_CHAINV_Pos) /*!< QEI_T::CTL: CHAINV Mask */ + +#define QEI_CTL_CHBINV_Pos (13) /*!< QEI_T::CTL: CHBINV Position */ +#define QEI_CTL_CHBINV_Msk (0x1ul << QEI_CTL_CHBINV_Pos) /*!< QEI_T::CTL: CHBINV Mask */ + +#define QEI_CTL_IDXINV_Pos (14) /*!< QEI_T::CTL: IDXINV Position */ +#define QEI_CTL_IDXINV_Msk (0x1ul << QEI_CTL_IDXINV_Pos) /*!< QEI_T::CTL: IDXINV Mask */ + +#define QEI_CTL_OVUNIEN_Pos (16) /*!< QEI_T::CTL: OVUNIEN Position */ +#define QEI_CTL_OVUNIEN_Msk (0x1ul << QEI_CTL_OVUNIEN_Pos) /*!< QEI_T::CTL: OVUNIEN Mask */ + +#define QEI_CTL_DIRIEN_Pos (17) /*!< QEI_T::CTL: DIRIEN Position */ +#define QEI_CTL_DIRIEN_Msk (0x1ul << QEI_CTL_DIRIEN_Pos) /*!< QEI_T::CTL: DIRIEN Mask */ + +#define QEI_CTL_CMPIEN_Pos (18) /*!< QEI_T::CTL: CMPIEN Position */ +#define QEI_CTL_CMPIEN_Msk (0x1ul << QEI_CTL_CMPIEN_Pos) /*!< QEI_T::CTL: CMPIEN Mask */ + +#define QEI_CTL_IDXIEN_Pos (19) /*!< QEI_T::CTL: IDXIEN Position */ +#define QEI_CTL_IDXIEN_Msk (0x1ul << QEI_CTL_IDXIEN_Pos) /*!< QEI_T::CTL: IDXIEN Mask */ + +#define QEI_CTL_HOLDTMR0_Pos (20) /*!< QEI_T::CTL: HOLDTMR0 Position */ +#define QEI_CTL_HOLDTMR0_Msk (0x1ul << QEI_CTL_HOLDTMR0_Pos) /*!< QEI_T::CTL: HOLDTMR0 Mask */ + +#define QEI_CTL_HOLDTMR1_Pos (21) /*!< QEI_T::CTL: HOLDTMR1 Position */ +#define QEI_CTL_HOLDTMR1_Msk (0x1ul << QEI_CTL_HOLDTMR1_Pos) /*!< QEI_T::CTL: HOLDTMR1 Mask */ + +#define QEI_CTL_HOLDTMR2_Pos (22) /*!< QEI_T::CTL: HOLDTMR2 Position */ +#define QEI_CTL_HOLDTMR2_Msk (0x1ul << QEI_CTL_HOLDTMR2_Pos) /*!< QEI_T::CTL: HOLDTMR2 Mask */ + +#define QEI_CTL_HOLDTMR3_Pos (23) /*!< QEI_T::CTL: HOLDTMR3 Position */ +#define QEI_CTL_HOLDTMR3_Msk (0x1ul << QEI_CTL_HOLDTMR3_Pos) /*!< QEI_T::CTL: HOLDTMR3 Mask */ + +#define QEI_CTL_HOLDCNT_Pos (24) /*!< QEI_T::CTL: HOLDCNT Position */ +#define QEI_CTL_HOLDCNT_Msk (0x1ul << QEI_CTL_HOLDCNT_Pos) /*!< QEI_T::CTL: HOLDCNT Mask */ + +#define QEI_CTL_IDXLATEN_Pos (25) /*!< QEI_T::CTL: IDXLATEN Position */ +#define QEI_CTL_IDXLATEN_Msk (0x1ul << QEI_CTL_IDXLATEN_Pos) /*!< QEI_T::CTL: IDXLATEN Mask */ + +#define QEI_CTL_IDXRLDEN_Pos (27) /*!< QEI_T::CTL: IDXRLDEN Position */ +#define QEI_CTL_IDXRLDEN_Msk (0x1ul << QEI_CTL_IDXRLDEN_Pos) /*!< QEI_T::CTL: IDXRLDEN Mask */ + +#define QEI_CTL_CMPEN_Pos (28) /*!< QEI_T::CTL: CMPEN Position */ +#define QEI_CTL_CMPEN_Msk (0x1ul << QEI_CTL_CMPEN_Pos) /*!< QEI_T::CTL: CMPEN Mask */ + +#define QEI_CTL_QEIEN_Pos (29) /*!< QEI_T::CTL: QEIEN Position */ +#define QEI_CTL_QEIEN_Msk (0x1ul << QEI_CTL_QEIEN_Pos) /*!< QEI_T::CTL: QEIEN Mask */ + +#define QEI_STATUS_IDXF_Pos (0) /*!< QEI_T::STATUS: IDXF Position */ +#define QEI_STATUS_IDXF_Msk (0x1ul << QEI_STATUS_IDXF_Pos) /*!< QEI_T::STATUS: IDXF Mask */ + +#define QEI_STATUS_CMPF_Pos (1) /*!< QEI_T::STATUS: CMPF Position */ +#define QEI_STATUS_CMPF_Msk (0x1ul << QEI_STATUS_CMPF_Pos) /*!< QEI_T::STATUS: CMPF Mask */ + +#define QEI_STATUS_OVUNF_Pos (2) /*!< QEI_T::STATUS: OVUNF Position */ +#define QEI_STATUS_OVUNF_Msk (0x1ul << QEI_STATUS_OVUNF_Pos) /*!< QEI_T::STATUS: OVUNF Mask */ + +#define QEI_STATUS_DIRCHGF_Pos (3) /*!< QEI_T::STATUS: DIRCHGF Position */ +#define QEI_STATUS_DIRCHGF_Msk (0x1ul << QEI_STATUS_DIRCHGF_Pos) /*!< QEI_T::STATUS: DIRCHGF Mask */ + +#define QEI_STATUS_DIRF_Pos (8) /*!< QEI_T::STATUS: DIRF Position */ +#define QEI_STATUS_DIRF_Msk (0x1ul << QEI_STATUS_DIRF_Pos) /*!< QEI_T::STATUS: DIRF Mask */ + +/**@}*/ /* QEI_CONST */ +/**@}*/ /* end of QEI register group */ +/**@}*/ /* end of REGISTER group */ + + +#endif /* __QEI_REG_H__ */ diff --git a/Ubiquitous/XiZi/board/nuvoton-m2354/third_party_driver/include/Regs/qspi_reg.h b/Ubiquitous/XiZi/board/nuvoton-m2354/third_party_driver/include/Regs/qspi_reg.h new file mode 100644 index 0000000..23e18e0 --- /dev/null +++ b/Ubiquitous/XiZi/board/nuvoton-m2354/third_party_driver/include/Regs/qspi_reg.h @@ -0,0 +1,622 @@ +/**************************************************************************//** + * @file qspi_reg.h + * @version V1.00 + * @brief QSPI register definition header file + * + * @copyright SPDX-License-Identifier: Apache-2.0 + * @copyright Copyright (C) 2020 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ +#ifndef __QSPI_REG_H__ +#define __QSPI_REG_H__ + +/** @addtogroup REGISTER Control Register + + @{ + +*/ + +/*---------------------- Quad Serial Peripheral Interface Controller -------------------------*/ +/** + @addtogroup QSPI Quad Serial Peripheral Interface Controller(QSPI) + Memory Mapped Structure for QSPI Controller + @{ +*/ + +typedef struct +{ + + + /** + * @var QSPI_T::CTL + * Offset: 0x00 QSPI Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |SPIEN |QSPI Transfer Control Enable Bit + * | | |In Master mode, the transfer will start when there is data in the FIFO buffer after this bit is set to 1 + * | | |In Slave mode, this device is ready to receive data when this bit is set to 1. + * | | |0 = Transfer control Disabled. + * | | |1 = Transfer control Enabled. + * | | |Note: Before changing the configurations of QSPIx_CTL, QSPIx_CLKDIV, QSPIx_SSCTL and QSPIx_FIFOCTL registers, user shall clear the SPIEN (QSPIx_CTL[0]) and confirm the SPIENSTS (QSPIx_STATUS[15]) is 0. + * |[1] |RXNEG |Receive on Negative Edge + * | | |0 = Received data input signal is latched on the rising edge of QSPI bus clock. + * | | |1 = Received data input signal is latched on the falling edge of QSPI bus clock. + * |[2] |TXNEG |Transmit on Negative Edge + * | | |0 = Transmitted data output signal is changed on the rising edge of QSPI bus clock. + * | | |1 = Transmitted data output signal is changed on the falling edge of QSPI bus clock. + * | | |Note: In TX DTR mode, TXNEG equals to CLKPOL (QSPIx_CTL[3]). + * |[3] |CLKPOL |Clock Polarity + * | | |0 = QSPI bus clock is idle low. + * | | |1 = QSPI bus clock is idle high. + * |[7:4] |SUSPITV |Suspend Interval + * | | |The four bits provide configurable suspend interval between two successive transmit/receive transaction in a Master transfer + * | | |The definition of the suspend interval is the interval between the last clock edge of the preceding transaction word and the first clock edge of the following transaction word + * | | |The default value is 0x3 + * | | |The period of the suspend interval is obtained according to the following equation. + * | | |(SUSPITV[3:0] + 0.5) * period of QSPICLK clock cycle + * | | |Example: + * | | |SUSPITV = 0x0 .... 0.5 QSPICLK clock cycle. + * | | |SUSPITV = 0x1 .... 1.5 QSPICLK clock cycle. + * | | |..... + * | | |SUSPITV = 0xE .... 14.5 QSPICLK clock cycle. + * | | |SUSPITV = 0xF .... 15.5 QSPICLK clock cycle. + * | | |Note: In TX DTR mode, SUSPITV equals to 0x0. + * |[12:8] |DWIDTH |Data Width + * | | |This field specifies how many bits can be transmitted / received in one transaction + * | | |The minimum bit length is 8 bits and can up to 32 bits. + * | | |DWIDTH = 0x08 .... 8 bits. + * | | |DWIDTH = 0x09 .... 9 bits. + * | | |..... + * | | |DWIDTH = 0x1F .... 31 bits. + * | | |DWIDTH = 0x00 .... 32 bits. + * | | |Note: For QSPI0~QSPI3, this bit field will decide the depth of TX/RX FIFO configuration in QSPI mode + * | | |Therefore, changing this bit field will clear TX/RX FIFO by hardware automatically in QSPI0~QSPI3. + * |[13] |LSB |Send LSB First + * | | |0 = The MSB, which bit of transmit/receive register depends on the setting of DWIDTH, is transmitted/received first. + * | | |1 = The LSB, bit 0 of the QSPI TX register, is sent first to the QSPI data output pin, and the first bit received from the QSPI data input pin will be put in the LSB position of the RX register (bit 0 of QSPI_RX). + * |[14] |HALFDPX |QSPI Half-duplex Transfer Enable Bit + * | | |This bit is used to select full-duplex or half-duplex for QSPI transfer + * | | |The bit field DATDIR (QSPIx_CTL[20]) can be used to set the data direction in half-duplex transfer. + * | | |0 = QSPI operates in full-duplex transfer. + * | | |1 = QSPI operates in half-duplex transfer. + * |[15] |RXONLY |Receive-only Mode Enable Bit + * | | |This bit field is only available in Master mode + * | | |In receive-only mode, QSPI Master will generate QSPI bus clock continuously for receiving data bit from QSPI slave device and assert the BUSY status. + * | | |0 = Receive-only mode Disabled. + * | | |1 = Receive-only mode Enabled. + * |[16] |TWOBIT |2-bit Transfer Mode Enable Bit + * | | |0 = 2-Bit Transfer mode Disabled. + * | | |1 = 2-Bit Transfer mode Enabled. + * | | |Note: When 2-Bit Transfer mode is enabled, the first serial transmitted bit data is from the first FIFO buffer data, and the 2nd serial transmitted bit data is from the second FIFO buffer data + * | | |As the same as transmitted function, the first received bit data is stored into the first FIFO buffer and the 2nd received bit data is stored into the second FIFO buffer at the same time. + * |[17] |UNITIEN |Unit Transfer Interrupt Enable Bit + * | | |0 = QSPI unit transfer interrupt Disabled. + * | | |1 = QSPI unit transfer interrupt Enabled. + * |[18] |SLAVE |Slave Mode Control + * | | |0 = Master mode. + * | | |1 = Slave mode. + * |[19] |REORDER |Byte Reorder Function Enable Bit + * | | |0 = Byte Reorder function Disabled. + * | | |1 = Byte Reorder function Enabled + * | | |A byte suspend interval will be inserted among each byte + * | | |The period of the byte suspend interval depends on the setting of SUSPITV. + * | | |Note: Byte Reorder function is only available if DWIDTH is defined as 16, 24, and 32 bits. + * |[20] |DATDIR |Data Port Direction Control + * | | |This bit is used to select the data input/output direction in half-duplex transfer and Dual/Quad transfer + * | | |0 = QSPI data is input direction. + * | | |1 = QSPI data is output direction. + * |[21] |DUALIOEN |Dual I/O Mode Enable Bit + * | | |0 = Dual I/O mode Disabled. + * | | |1 = Dual I/O mode Enabled. + * |[22] |QUADIOEN |Quad I/O Mode Enable Bit + * | | |0 = Quad I/O mode Disabled. + * | | |1 = Quad I/O mode Enabled. + * |[23] |TXDTREN |Transmit Double Transfer Rate Mode Enable Bit + * | | |0 = TX DTR mode Disabled. + * | | |1 = TX DTR mode Enabled. + * | | |Note: QSPI Master mode supports TXDTR (Transmit Double Transfer Rate) mode, and QSPI Slave mode does not support this mode. + * @var QSPI_T::CLKDIV + * Offset: 0x04 QSPI Clock Divider Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[8:0] |DIVIDER |Clock Divider + * | | |The value in this field is the frequency divider for generating the peripheral clock, fspi_eclk, and the QSPI bus clock of QSPI Master + * | | |The frequency is obtained according to the following equation. + * | | |where + * | | |is the peripheral clock source, which is defined in the clock control register, CLK_CLKSEL2. + * | | |Note: The time interval must be larger than or equal 5 peripheral clock cycles between releasing QSPI IP software reset and setting this clock divider register. + * @var QSPI_T::SSCTL + * Offset: 0x08 QSPI Slave Select Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |SS |Slave Selection Control + * | | |If AUTOSS bit is cleared to 0, + * | | |0 = Set the QSPIx_SS line to inactive state. + * | | |1 = Set the QSPIx_SS line to active state. + * | | |If the AUTOSS bit is set to 1, + * | | |0 = Keep the QSPIx_SS line at inactive state. + * | | |1 = QSPIx_SS line will be automatically driven to active state for the duration of data transfer, and will be driven to inactive state for the rest of the time + * | | |The active state of QSPIx_SS is specified in SSACTPOL (QSPIx_SSCTL[2]). + * | | |Note: Master mode only. + * |[2] |SSACTPOL |Slave Selection Active Polarity + * | | |This bit defines the active polarity of slave selection signal (QSPIx_SS). + * | | |0 = The slave selection signal QSPIx_SS is active low. + * | | |1 = The slave selection signal QSPIx_SS is active high. + * |[3] |AUTOSS |Automatic Slave Selection Function Enable Bit + * | | |0 = Automatic slave selection function Disabled + * | | |Slave selection signal will be asserted/de-asserted according to SS (QSPIx_SSCTL[0]). + * | | |1 = Automatic slave selection function Enabled. + * | | |Note: Master mode only. + * |[4] |SLV3WIRE |Slave 3-wire Mode Enable Bit + * | | |In Slave 3-wire mode, the QSPI controller can work with 3-wire interface including QSPI0_CLK, QSPI0_MISO and QSPI0_MOSI pins. + * | | |0 = 4-wire bi-direction interface. + * | | |1 = 3-wire bi-direction interface. + * |[5] |SLVTOIEN |Slave Mode Time-out Interrupt Enable Bit + * | | |0 = Slave mode time-out interrupt Disabled. + * | | |1 = Slave mode time-out interrupt Enabled. + * |[6] |SLVTORST |Slave Mode Time-out Reset Control + * | | |0 = When Slave mode time-out event occurs, the TX and RX control circuit will not be reset. + * | | |1 = When Slave mode time-out event occurs, the TX and RX control circuit will be reset by hardware. + * |[8] |SLVBEIEN |Slave Mode Bit Count Error Interrupt Enable Bit + * | | |0 = Slave mode bit count error interrupt Disabled. + * | | |1 = Slave mode bit count error interrupt Enabled. + * |[9] |SLVURIEN |Slave Mode TX Under Run Interrupt Enable Bit + * | | |0 = Slave mode TX under run interrupt Disabled. + * | | |1 = Slave mode TX under run interrupt Enabled. + * |[12] |SSACTIEN |Slave Select Active Interrupt Enable Bit + * | | |0 = Slave select active interrupt Disabled. + * | | |1 = Slave select active interrupt Enabled. + * |[13] |SSINAIEN |Slave Select Inactive Interrupt Enable Bit + * | | |0 = Slave select inactive interrupt Disabled. + * | | |1 = Slave select inactive interrupt Enabled. + * |[31:16] |SLVTOCNT |Slave Mode Time-out Period + * | | |In Slave mode, these bits indicate the time-out period when there is bus clock input during slave select active + * | | |The clock source of the time-out counter is Slave peripheral clock + * | | |If the value is 0, it indicates the slave mode time-out function is disabled. + * @var QSPI_T::PDMACTL + * Offset: 0x0C QSPI PDMA Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |TXPDMAEN |Transmit PDMA Enable Bit + * | | |0 = Transmit PDMA function Disabled. + * | | |1 = Transmit PDMA function Enabled. + * | | |Note: In QSPI Master mode with full duplex transfer, if both TX and RX PDMA functions are enabled, RX PDMA function cannot be enabled prior to TX PDMA function + * | | |User can enable TX PDMA function firstly or enable both functions simultaneously. + * |[1] |RXPDMAEN |Receive PDMA Enable Bit + * | | |0 = Receive PDMA function Disabled. + * | | |1 = Receive PDMA function Enabled. + * |[2] |PDMARST |PDMA Reset + * | | |0 = No effect. + * | | |1 = Reset the PDMA control logic of the QSPI controller. This bit will be automatically cleared to 0. + * @var QSPI_T::FIFOCTL + * Offset: 0x10 QSPI FIFO Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |RXRST |Receive Reset + * | | |0 = No effect. + * | | |1 = Reset receive FIFO pointer and receive circuit + * | | |The RXFULL bit will be cleared to 0 and the RXEMPTY bit will be set to 1 + * | | |This bit will be cleared to 0 by hardware about 3 system clock cycles + 2 peripheral clock cycles after it is set to 1 + * | | |User can read TXRXRST (QSPIx_STATUS[23]) to check if reset is accomplished or not. + * |[1] |TXRST |Transmit Reset + * | | |0 = No effect. + * | | |1 = Reset transmit FIFO pointer and transmit circuit + * | | |The TXFULL bit will be cleared to 0 and the TXEMPTY bit will be set to 1 + * | | |This bit will be cleared to 0 by hardware about 3 system clock cycles + 2 peripheral clock cycles after it is set to 1 + * | | |User can read TXRXRST (QSPIx_STATUS[23]) to check if reset is accomplished or not. + * | | |Note: If TX underflow event occurs in QSPI Slave mode, this bit can be used to make QSPI return to idle state. + * |[2] |RXTHIEN |Receive FIFO Threshold Interrupt Enable Bit + * | | |0 = RX FIFO threshold interrupt Disabled. + * | | |1 = RX FIFO threshold interrupt Enabled. + * |[3] |TXTHIEN |Transmit FIFO Threshold Interrupt Enable Bit + * | | |0 = TX FIFO threshold interrupt Disabled. + * | | |1 = TX FIFO threshold interrupt Enabled. + * |[4] |RXTOIEN |Receive Time-out Interrupt Enable Bit + * | | |0 = Receive time-out interrupt Disabled. + * | | |1 = Receive time-out interrupt Enabled. + * |[5] |RXOVIEN |Receive FIFO Overrun Interrupt Enable Bit + * | | |0 = Receive FIFO overrun interrupt Disabled. + * | | |1 = Receive FIFO overrun interrupt Enabled. + * |[6] |TXUFPOL |TX Underflow Data Polarity + * | | |0 = The QSPI data out is kept 0 if there is TX underflow event in Slave mode. + * | | |1 = The QSPI data out is kept 1 if there is TX underflow event in Slave mode. + * | | |Note: + * | | |1. The TX underflow event occurs if there is no any data in TX FIFO when the slave selection signal is active. + * | | |2. When TX underflow event occurs, QSPIx_MISO pin state will be determined by this setting even though TX FIFO is not empty afterward + * | | |Data stored in TX FIFO will be sent through QSPIx_MISO pin in the next transfer frame. + * |[7] |TXUFIEN |TX Underflow Interrupt Enable Bit + * | | |When TX underflow event occurs in Slave mode, TXUFIF (QSPIx_STATUS[19]) will be set to 1 + * | | |This bit is used to enable the TX underflow interrupt. + * | | |0 = Slave TX underflow interrupt Disabled. + * | | |1 = Slave TX underflow interrupt Enabled. + * |[8] |RXFBCLR |Receive FIFO Buffer Clear + * | | |0 = No effect. + * | | |1 = Clear receive FIFO pointer + * | | |The RXFULL bit will be cleared to 0 and the RXEMPTY bit will be set to 1 + * | | |This bit will be cleared to 0 by hardware about 1 system clock after it is set to 1. + * | | |Note: The RX shift register will not be cleared. + * |[9] |TXFBCLR |Transmit FIFO Buffer Clear + * | | |0 = No effect. + * | | |1 = Clear transmit FIFO pointer + * | | |The TXFULL bit will be cleared to 0 and the TXEMPTY bit will be set to 1 + * | | |This bit will be cleared to 0 by hardware about 1 system clock after it is set to 1. + * | | |Note: The TX shift register will not be cleared. + * |[10] |SLVBERX |RX FIFO Write Data Enable Bit When Slave Mode Bit Count Error + * | | |0 = Uncompleted RX data will be dropped from RX FIFO when bit count error event happened in QSPI Slave mode. + * | | |1 = Uncompleted RX data will be written into RX FIFO when bit count error event happened in QSPI Slave mode + * | | |User can read SLVBENUM (QSPIx_STATUS2[29:24]) to know that the effective bit number of uncompleted RX data when SPI slave bit count error happened. + * | | |Note: Slave mode only. + * |[26:24] |RXTH |Receive FIFO Threshold + * | | |If the valid data count of the receive FIFO buffer is larger than the RXTH setting, the RXTHIF bit will be set to 1, else the RXTHIF bit will be cleared to 0 + * | | |For QSPI0~QSPI3, the MSB of this bit field is only meaningful while QSPI mode 8~16 bits of data length. + * |[30:28] |TXTH |Transmit FIFO Threshold + * | | |If the valid data count of the transmit FIFO buffer is less than or equal to the TXTH setting, the TXTHIF bit will be set to 1, else the TXTHIF bit will be cleared to 0 + * | | |For QSPI0~QSPI3, the MSB of this bit field is only meaningful while QSPI mode 8~16 bits of data length. + * @var QSPI_T::STATUS + * Offset: 0x14 QSPI Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |BUSY |Busy Status (Read Only) + * | | |0 = QSPI controller is in idle state. + * | | |1 = QSPI controller is in busy state. + * | | |The following listing are the bus busy conditions: + * | | |a. QSPIx_CTL[0] = 1 and TXEMPTY = 0. + * | | |b + * | | |For QSPI Master mode, QSPIx_CTL[0] = 1 and TXEMPTY = 1 but the current transaction is not finished yet. + * | | |c. For QSPI Master mode, QSPIx_CTL[0] = 1 and RXONLY = 1. + * | | |d. + * | | |For QSPI Slave mode, the QSPIx_CTL[0] = 1 and there is serial clock input into the QSPI core logic when slave select is active. + * | | |e. + * | | |For QSPI Slave mode, the QSPIx_CTL[0] = 1 and the transmit buffer or transmit shift register is not empty even if the slave select is inactive. + * | | |Note: By applications, this QSPI busy flag should be used with other status registers in QSPIx_STATUS such as TXCNT, RXCNT, TXTHIF, TXFULL, TXEMPTY, RXTHIF, RXFULL, RXEMPTY, and UNITIF + * | | |Therefore the QSPI transfer done events of TX/RX operations can be obtained at correct timing point. + * |[1] |UNITIF |Unit Transfer Interrupt Flag + * | | |0 = No transaction has been finished since this bit was cleared to 0. + * | | |1 = QSPI controller has finished one unit transfer. + * | | |Note: This bit will be cleared by writing 1 to it. + * |[2] |SSACTIF |Slave Select Active Interrupt Flag + * | | |0 = Slave select active interrupt was cleared or not occurred. + * | | |1 = Slave select active interrupt event occurred. + * | | |Note: Only available in Slave mode. This bit will be cleared by writing 1 to it. + * |[3] |SSINAIF |Slave Select Inactive Interrupt Flag + * | | |0 = Slave select inactive interrupt was cleared or not occurred. + * | | |1 = Slave select inactive interrupt event occurred. + * | | |Note: Only available in Slave mode. This bit will be cleared by writing 1 to it. + * |[4] |SSLINE |Slave Select Line Bus Status (Read Only) + * | | |0 = The slave select line status is 0. + * | | |1 = The slave select line status is 1. + * | | |Note: This bit is only available in Slave mode + * | | |If SSACTPOL (QSPIx_SSCTL[2]) is set 0, and the SSLINE is 1, the QSPI slave select is in inactive status. + * |[5] |SLVTOIF |Slave Time-out Interrupt Flag + * | | |When the slave select is active and the value of SLVTOCNT is not 0, if the bus clock is detected, the slave time-out counter in QSPI controller logic will be started + * | | |When the value of time-out counter is greater than or equal to the value of SLVTOCNT (QSPI_SSCTL[31:16]) before one transaction is done, the slave time-out interrupt event will be asserted. + * | | |0 = Slave time-out is not active. + * | | |1 = Slave time-out is active. + * | | |Note: This bit will be cleared by writing 1 to it. + * |[6] |SLVBEIF |Slave Mode Bit Count Error Interrupt Flag + * | | |In Slave mode, when the slave select line goes to inactive state, if bit counter is mismatch with DWIDTH, this interrupt flag will be set to 1. + * | | |0 = No Slave mode bit count error event. + * | | |1 = Slave mode bit count error event occurs. + * | | |Note: If the slave select active but there is no any bus clock input, the SLVBEIF also active when the slave select goes to inactive state + * | | |This bit will be cleared by writing 1 to it. + * |[7] |SLVURIF |Slave Mode TX Under Run Interrupt Flag + * | | |In Slave mode, if TX underflow event occurs and the slave select line goes to inactive state, this interrupt flag will be set to 1. + * | | |0 = No Slave TX under run event. + * | | |1 = Slave TX under run event occurs. + * | | |Note: This bit will be cleared by writing 1 to it. + * |[8] |RXEMPTY |Receive FIFO Buffer Empty Indicator (Read Only) + * | | |0 = Receive FIFO buffer is not empty. + * | | |1 = Receive FIFO buffer is empty. + * |[9] |RXFULL |Receive FIFO Buffer Full Indicator (Read Only) + * | | |0 = Receive FIFO buffer is not full. + * | | |1 = Receive FIFO buffer is full. + * |[10] |RXTHIF |Receive FIFO Threshold Interrupt Flag (Read Only) + * | | |0 = The valid data count within the receive FIFO buffer is smaller than or equal to the setting value of RXTH. + * | | |1 = The valid data count within the receive FIFO buffer is larger than the setting value of RXTH. + * |[11] |RXOVIF |Receive FIFO Overrun Interrupt Flag + * | | |When the receive FIFO buffer is full, the follow-up data will be dropped and this bit will be set to 1. + * | | |0 = No FIFO is overrun. + * | | |1 = Receive FIFO is overrun. + * | | |Note: This bit will be cleared by writing 1 to it. + * |[12] |RXTOIF |Receive Time-out Interrupt Flag + * | | |0 = No receive FIFO time-out event. + * | | |1 = Receive FIFO buffer is not empty and no read operation on receive FIFO buffer over 64 QSPI peripheral clock periods in Master mode or over 576 QSPI peripheral clock periods in Slave mode + * | | |When the received FIFO buffer is read by software, the time-out status will be cleared automatically. + * | | |Note: This bit will be cleared by writing 1 to it. + * |[15] |SPIENSTS |QSPI Enable Status (Read Only) + * | | |0 = The QSPI controller is disabled. + * | | |1 = The QSPI controller is enabled. + * | | |Note: The QSPI peripheral clock is asynchronous with the system clock + * | | |In order to make sure the QSPI control logic is disabled, this bit indicates the real status of QSPI controller. + * |[16] |TXEMPTY |Transmit FIFO Buffer Empty Indicator (Read Only) + * | | |0 = Transmit FIFO buffer is not empty. + * | | |1 = Transmit FIFO buffer is empty. + * |[17] |TXFULL |Transmit FIFO Buffer Full Indicator (Read Only) + * | | |0 = Transmit FIFO buffer is not full. + * | | |1 = Transmit FIFO buffer is full. + * |[18] |TXTHIF |Transmit FIFO Threshold Interrupt Flag (Read Only) + * | | |0 = The valid data count within the transmit FIFO buffer is larger than the setting value of TXTH. + * | | |1 = The valid data count within the transmit FIFO buffer is less than or equal to the setting value of TXTH. + * |[19] |TXUFIF |TX Underflow Interrupt Flag + * | | |When the TX underflow event occurs, this bit will be set to 1, the state of data output pin depends on the setting of TXUFPOL. + * | | |0 = No effect. + * | | |1 = No data in Transmit FIFO and TX shift register when the slave selection signal is active. + * | | |Note 1: This bit will be cleared by writing 1 to it. + * | | |Note 2: If reset slave's transmission circuit when slave selection signal is active, this flag will be set to 1 after 2 peripheral clock cycles + 3 system clock cycles since the reset operation is done. + * |[23] |TXRXRST |TX or RX Reset Status (Read Only) + * | | |0 = The reset function of TXRST or RXRST is done. + * | | |1 = Doing the reset function of TXRST or RXRST. + * | | |Note: Both the reset operations of TXRST and RXRST need 3 system clock cycles + 2 peripheral clock cycles + * | | |User can check the status of this bit to monitor the reset function is doing or done. + * |[27:24] |RXCNT |Receive FIFO Data Count (Read Only) + * | | |This bit field indicates the valid data count of receive FIFO buffer. + * |[31:28] |TXCNT |Transmit FIFO Data Count (Read Only) + * | | |This bit field indicates the valid data count of transmit FIFO buffer. + * @var QSPI_T::STATUS2 + * Offset: 0x18 QSPI Status2 Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[29:24] |SLVBENUM |Effective Bit Number of Uncompleted RX Data + * | | |This status register indicates that effective bit number of uncompleted RX data when SLVBERX (QSPIx_FIFOCTL[10]) is enabled and RX bit count error event happen in QSPI Slave mode + * | | |This status register will be fixed to 0x0 when SLVBERX (QSPIx_FIFOCTL[10]) is disabled. + * | | |Note 1: This register will be cleared to 0x0 when user writes 0x1 to SLVBEIF (QSPIx_STATUS[6]). + * | | |Note 2: Slave mode only. + * @var QSPI_T::TX + * Offset: 0x20 QSPI Data Transmit Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |TX |Data Transmit Register + * | | |The data transmit registers pass through the transmitted data into the 8-level transmit FIFO buffers + * | | |The number of valid bits depends on the setting of DWIDTH (QSPIx_CTL[12:8]) in QSPI mode. + * | | |In QSPI mode, if DWIDTH is set to 0x08, the bits TX[7:0] will be transmitted. + * | | |If DWIDTH is set to 0x00 , the QSPI controller will perform a 32-bit transfer. + * | | |Note: In Master mode, QSPI controller will start to transfer the QSPI bus clock after 1 APB clock and 6 peripheral clock cycles after user writes to this register. + * @var QSPI_T::RX + * Offset: 0x30 QSPI Data Receive Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |RX |Data Receive Register (Read Only) + * | | |There are 8-level FIFO buffers in this controller. + * | | |The data receive register holds the data received from QSPI data input pin. + * | | |If the RXEMPTY (QSPIx_STATUS[8]) is not set to 1, the receive FIFO buffers can be accessed through software by reading this register. + */ + __IO uint32_t CTL; /*!< [0x0000] QSPI Control Register */ + __IO uint32_t CLKDIV; /*!< [0x0004] QSPI Clock Divider Register */ + __IO uint32_t SSCTL; /*!< [0x0008] QSPI Slave Select Control Register */ + __IO uint32_t PDMACTL; /*!< [0x000c] QSPI PDMA Control Register */ + __IO uint32_t FIFOCTL; /*!< [0x0010] QSPI FIFO Control Register */ + __IO uint32_t STATUS; /*!< [0x0014] QSPI Status Register */ + __I uint32_t STATUS2; /*!< [0x0018] QSPI Status2 Register */ + __I uint32_t RESERVE0[1]; + __O uint32_t TX; /*!< [0x0020] QSPI Data Transmit Register */ + __I uint32_t RESERVE1[3]; + __I uint32_t RX; /*!< [0x0030] QSPI Data Receive Register */ + +} QSPI_T; + +/** + @addtogroup QSPI_CONST QSPI Bit Field Definition + Constant Definitions for QSPI Controller + @{ +*/ + +#define QSPI_CTL_SPIEN_Pos (0) /*!< QSPI_T::CTL: SPIEN Position */ +#define QSPI_CTL_SPIEN_Msk (0x1ul << QSPI_CTL_SPIEN_Pos) /*!< QSPI_T::CTL: SPIEN Mask */ + +#define QSPI_CTL_RXNEG_Pos (1) /*!< QSPI_T::CTL: RXNEG Position */ +#define QSPI_CTL_RXNEG_Msk (0x1ul << QSPI_CTL_RXNEG_Pos) /*!< QSPI_T::CTL: RXNEG Mask */ + +#define QSPI_CTL_TXNEG_Pos (2) /*!< QSPI_T::CTL: TXNEG Position */ +#define QSPI_CTL_TXNEG_Msk (0x1ul << QSPI_CTL_TXNEG_Pos) /*!< QSPI_T::CTL: TXNEG Mask */ + +#define QSPI_CTL_CLKPOL_Pos (3) /*!< QSPI_T::CTL: CLKPOL Position */ +#define QSPI_CTL_CLKPOL_Msk (0x1ul << QSPI_CTL_CLKPOL_Pos) /*!< QSPI_T::CTL: CLKPOL Mask */ + +#define QSPI_CTL_SUSPITV_Pos (4) /*!< QSPI_T::CTL: SUSPITV Position */ +#define QSPI_CTL_SUSPITV_Msk (0xful << QSPI_CTL_SUSPITV_Pos) /*!< QSPI_T::CTL: SUSPITV Mask */ + +#define QSPI_CTL_DWIDTH_Pos (8) /*!< QSPI_T::CTL: DWIDTH Position */ +#define QSPI_CTL_DWIDTH_Msk (0x1ful << QSPI_CTL_DWIDTH_Pos) /*!< QSPI_T::CTL: DWIDTH Mask */ + +#define QSPI_CTL_LSB_Pos (13) /*!< QSPI_T::CTL: LSB Position */ +#define QSPI_CTL_LSB_Msk (0x1ul << QSPI_CTL_LSB_Pos) /*!< QSPI_T::CTL: LSB Mask */ + +#define QSPI_CTL_HALFDPX_Pos (14) /*!< QSPI_T::CTL: HALFDPX Position */ +#define QSPI_CTL_HALFDPX_Msk (0x1ul << QSPI_CTL_HALFDPX_Pos) /*!< QSPI_T::CTL: HALFDPX Mask */ + +#define QSPI_CTL_RXONLY_Pos (15) /*!< QSPI_T::CTL: RXONLY Position */ +#define QSPI_CTL_RXONLY_Msk (0x1ul << QSPI_CTL_RXONLY_Pos) /*!< QSPI_T::CTL: RXONLY Mask */ + +#define QSPI_CTL_TWOBIT_Pos (16) /*!< QSPI_T::CTL: TWOBIT Position */ +#define QSPI_CTL_TWOBIT_Msk (0x1ul << QSPI_CTL_TWOBIT_Pos) /*!< QSPI_T::CTL: TWOBIT Mask */ + +#define QSPI_CTL_UNITIEN_Pos (17) /*!< QSPI_T::CTL: UNITIEN Position */ +#define QSPI_CTL_UNITIEN_Msk (0x1ul << QSPI_CTL_UNITIEN_Pos) /*!< QSPI_T::CTL: UNITIEN Mask */ + +#define QSPI_CTL_SLAVE_Pos (18) /*!< QSPI_T::CTL: SLAVE Position */ +#define QSPI_CTL_SLAVE_Msk (0x1ul << QSPI_CTL_SLAVE_Pos) /*!< QSPI_T::CTL: SLAVE Mask */ + +#define QSPI_CTL_REORDER_Pos (19) /*!< QSPI_T::CTL: REORDER Position */ +#define QSPI_CTL_REORDER_Msk (0x1ul << QSPI_CTL_REORDER_Pos) /*!< QSPI_T::CTL: REORDER Mask */ + +#define QSPI_CTL_DATDIR_Pos (20) /*!< QSPI_T::CTL: DATDIR Position */ +#define QSPI_CTL_DATDIR_Msk (0x1ul << QSPI_CTL_DATDIR_Pos) /*!< QSPI_T::CTL: DATDIR Mask */ + +#define QSPI_CTL_DUALIOEN_Pos (21) /*!< QSPI_T::CTL: DUALIOEN Position */ +#define QSPI_CTL_DUALIOEN_Msk (0x1ul << QSPI_CTL_DUALIOEN_Pos) /*!< QSPI_T::CTL: DUALIOEN Mask */ + +#define QSPI_CTL_QUADIOEN_Pos (22) /*!< QSPI_T::CTL: QUADIOEN Position */ +#define QSPI_CTL_QUADIOEN_Msk (0x1ul << QSPI_CTL_QUADIOEN_Pos) /*!< QSPI_T::CTL: QUADIOEN Mask */ + +#define QSPI_CTL_TXDTREN_Pos (23) /*!< QSPI_T::CTL: TXDTREN Position */ +#define QSPI_CTL_TXDTREN_Msk (0x1ul << QSPI_CTL_TXDTREN_Pos) /*!< QSPI_T::CTL: TXDTREN Mask */ + +#define QSPI_CLKDIV_DIVIDER_Pos (0) /*!< QSPI_T::CLKDIV: DIVIDER Position */ +#define QSPI_CLKDIV_DIVIDER_Msk (0x1fful << QSPI_CLKDIV_DIVIDER_Pos) /*!< QSPI_T::CLKDIV: DIVIDER Mask */ + +#define QSPI_SSCTL_SS_Pos (0) /*!< QSPI_T::SSCTL: SS Position */ +#define QSPI_SSCTL_SS_Msk (0x1ul << QSPI_SSCTL_SS_Pos) /*!< QSPI_T::SSCTL: SS Mask */ + +#define QSPI_SSCTL_SSACTPOL_Pos (2) /*!< QSPI_T::SSCTL: SSACTPOL Position */ +#define QSPI_SSCTL_SSACTPOL_Msk (0x1ul << QSPI_SSCTL_SSACTPOL_Pos) /*!< QSPI_T::SSCTL: SSACTPOL Mask */ + +#define QSPI_SSCTL_AUTOSS_Pos (3) /*!< QSPI_T::SSCTL: AUTOSS Position */ +#define QSPI_SSCTL_AUTOSS_Msk (0x1ul << QSPI_SSCTL_AUTOSS_Pos) /*!< QSPI_T::SSCTL: AUTOSS Mask */ + +#define QSPI_SSCTL_SLV3WIRE_Pos (4) /*!< QSPI_T::SSCTL: SLV3WIRE Position */ +#define QSPI_SSCTL_SLV3WIRE_Msk (0x1ul << QSPI_SSCTL_SLV3WIRE_Pos) /*!< QSPI_T::SSCTL: SLV3WIRE Mask */ + +#define QSPI_SSCTL_SLVTOIEN_Pos (5) /*!< QSPI_T::SSCTL: SLVTOIEN Position */ +#define QSPI_SSCTL_SLVTOIEN_Msk (0x1ul << QSPI_SSCTL_SLVTOIEN_Pos) /*!< QSPI_T::SSCTL: SLVTOIEN Mask */ + +#define QSPI_SSCTL_SLVTORST_Pos (6) /*!< QSPI_T::SSCTL: SLVTORST Position */ +#define QSPI_SSCTL_SLVTORST_Msk (0x1ul << QSPI_SSCTL_SLVTORST_Pos) /*!< QSPI_T::SSCTL: SLVTORST Mask */ + +#define QSPI_SSCTL_SLVBEIEN_Pos (8) /*!< QSPI_T::SSCTL: SLVBEIEN Position */ +#define QSPI_SSCTL_SLVBEIEN_Msk (0x1ul << QSPI_SSCTL_SLVBEIEN_Pos) /*!< QSPI_T::SSCTL: SLVBEIEN Mask */ + +#define QSPI_SSCTL_SLVURIEN_Pos (9) /*!< QSPI_T::SSCTL: SLVURIEN Position */ +#define QSPI_SSCTL_SLVURIEN_Msk (0x1ul << QSPI_SSCTL_SLVURIEN_Pos) /*!< QSPI_T::SSCTL: SLVURIEN Mask */ + +#define QSPI_SSCTL_SSACTIEN_Pos (12) /*!< QSPI_T::SSCTL: SSACTIEN Position */ +#define QSPI_SSCTL_SSACTIEN_Msk (0x1ul << QSPI_SSCTL_SSACTIEN_Pos) /*!< QSPI_T::SSCTL: SSACTIEN Mask */ + +#define QSPI_SSCTL_SSINAIEN_Pos (13) /*!< QSPI_T::SSCTL: SSINAIEN Position */ +#define QSPI_SSCTL_SSINAIEN_Msk (0x1ul << QSPI_SSCTL_SSINAIEN_Pos) /*!< QSPI_T::SSCTL: SSINAIEN Mask */ + +#define QSPI_SSCTL_SLVTOCNT_Pos (16) /*!< QSPI_T::SSCTL: SLVTOCNT Position */ +#define QSPI_SSCTL_SLVTOCNT_Msk (0xfffful << QSPI_SSCTL_SLVTOCNT_Pos) /*!< QSPI_T::SSCTL: SLVTOCNT Mask */ + +#define QSPI_PDMACTL_TXPDMAEN_Pos (0) /*!< QSPI_T::PDMACTL: TXPDMAEN Position */ +#define QSPI_PDMACTL_TXPDMAEN_Msk (0x1ul << QSPI_PDMACTL_TXPDMAEN_Pos) /*!< QSPI_T::PDMACTL: TXPDMAEN Mask */ + +#define QSPI_PDMACTL_RXPDMAEN_Pos (1) /*!< QSPI_T::PDMACTL: RXPDMAEN Position */ +#define QSPI_PDMACTL_RXPDMAEN_Msk (0x1ul << QSPI_PDMACTL_RXPDMAEN_Pos) /*!< QSPI_T::PDMACTL: RXPDMAEN Mask */ + +#define QSPI_PDMACTL_PDMARST_Pos (2) /*!< QSPI_T::PDMACTL: PDMARST Position */ +#define QSPI_PDMACTL_PDMARST_Msk (0x1ul << QSPI_PDMACTL_PDMARST_Pos) /*!< QSPI_T::PDMACTL: PDMARST Mask */ + +#define QSPI_FIFOCTL_RXRST_Pos (0) /*!< QSPI_T::FIFOCTL: RXRST Position */ +#define QSPI_FIFOCTL_RXRST_Msk (0x1ul << QSPI_FIFOCTL_RXRST_Pos) /*!< QSPI_T::FIFOCTL: RXRST Mask */ + +#define QSPI_FIFOCTL_TXRST_Pos (1) /*!< QSPI_T::FIFOCTL: TXRST Position */ +#define QSPI_FIFOCTL_TXRST_Msk (0x1ul << QSPI_FIFOCTL_TXRST_Pos) /*!< QSPI_T::FIFOCTL: TXRST Mask */ + +#define QSPI_FIFOCTL_RXTHIEN_Pos (2) /*!< QSPI_T::FIFOCTL: RXTHIEN Position */ +#define QSPI_FIFOCTL_RXTHIEN_Msk (0x1ul << QSPI_FIFOCTL_RXTHIEN_Pos) /*!< QSPI_T::FIFOCTL: RXTHIEN Mask */ + +#define QSPI_FIFOCTL_TXTHIEN_Pos (3) /*!< QSPI_T::FIFOCTL: TXTHIEN Position */ +#define QSPI_FIFOCTL_TXTHIEN_Msk (0x1ul << QSPI_FIFOCTL_TXTHIEN_Pos) /*!< QSPI_T::FIFOCTL: TXTHIEN Mask */ + +#define QSPI_FIFOCTL_RXTOIEN_Pos (4) /*!< QSPI_T::FIFOCTL: RXTOIEN Position */ +#define QSPI_FIFOCTL_RXTOIEN_Msk (0x1ul << QSPI_FIFOCTL_RXTOIEN_Pos) /*!< QSPI_T::FIFOCTL: RXTOIEN Mask */ + +#define QSPI_FIFOCTL_RXOVIEN_Pos (5) /*!< QSPI_T::FIFOCTL: RXOVIEN Position */ +#define QSPI_FIFOCTL_RXOVIEN_Msk (0x1ul << QSPI_FIFOCTL_RXOVIEN_Pos) /*!< QSPI_T::FIFOCTL: RXOVIEN Mask */ + +#define QSPI_FIFOCTL_TXUFPOL_Pos (6) /*!< QSPI_T::FIFOCTL: TXUFPOL Position */ +#define QSPI_FIFOCTL_TXUFPOL_Msk (0x1ul << QSPI_FIFOCTL_TXUFPOL_Pos) /*!< QSPI_T::FIFOCTL: TXUFPOL Mask */ + +#define QSPI_FIFOCTL_TXUFIEN_Pos (7) /*!< QSPI_T::FIFOCTL: TXUFIEN Position */ +#define QSPI_FIFOCTL_TXUFIEN_Msk (0x1ul << QSPI_FIFOCTL_TXUFIEN_Pos) /*!< QSPI_T::FIFOCTL: TXUFIEN Mask */ + +#define QSPI_FIFOCTL_RXFBCLR_Pos (8) /*!< QSPI_T::FIFOCTL: RXFBCLR Position */ +#define QSPI_FIFOCTL_RXFBCLR_Msk (0x1ul << QSPI_FIFOCTL_RXFBCLR_Pos) /*!< QSPI_T::FIFOCTL: RXFBCLR Mask */ + +#define QSPI_FIFOCTL_TXFBCLR_Pos (9) /*!< QSPI_T::FIFOCTL: TXFBCLR Position */ +#define QSPI_FIFOCTL_TXFBCLR_Msk (0x1ul << QSPI_FIFOCTL_TXFBCLR_Pos) /*!< QSPI_T::FIFOCTL: TXFBCLR Mask */ + +#define QSPI_FIFOCTL_SLVBERX_Pos (10) /*!< QSPI_T::FIFOCTL: SLVBERX Position */ +#define QSPI_FIFOCTL_SLVBERX_Msk (0x1ul << QSPI_FIFOCTL_SLVBERX_Pos) /*!< QSPI_T::FIFOCTL: SLVBERX Mask */ + +#define QSPI_FIFOCTL_RXTH_Pos (24) /*!< QSPI_T::FIFOCTL: RXTH Position */ +#define QSPI_FIFOCTL_RXTH_Msk (0x7ul << QSPI_FIFOCTL_RXTH_Pos) /*!< QSPI_T::FIFOCTL: RXTH Mask */ + +#define QSPI_FIFOCTL_TXTH_Pos (28) /*!< QSPI_T::FIFOCTL: TXTH Position */ +#define QSPI_FIFOCTL_TXTH_Msk (0x7ul << QSPI_FIFOCTL_TXTH_Pos) /*!< QSPI_T::FIFOCTL: TXTH Mask */ + +#define QSPI_STATUS_BUSY_Pos (0) /*!< QSPI_T::STATUS: BUSY Position */ +#define QSPI_STATUS_BUSY_Msk (0x1ul << QSPI_STATUS_BUSY_Pos) /*!< QSPI_T::STATUS: BUSY Mask */ + +#define QSPI_STATUS_UNITIF_Pos (1) /*!< QSPI_T::STATUS: UNITIF Position */ +#define QSPI_STATUS_UNITIF_Msk (0x1ul << QSPI_STATUS_UNITIF_Pos) /*!< QSPI_T::STATUS: UNITIF Mask */ + +#define QSPI_STATUS_SSACTIF_Pos (2) /*!< QSPI_T::STATUS: SSACTIF Position */ +#define QSPI_STATUS_SSACTIF_Msk (0x1ul << QSPI_STATUS_SSACTIF_Pos) /*!< QSPI_T::STATUS: SSACTIF Mask */ + +#define QSPI_STATUS_SSINAIF_Pos (3) /*!< QSPI_T::STATUS: SSINAIF Position */ +#define QSPI_STATUS_SSINAIF_Msk (0x1ul << QSPI_STATUS_SSINAIF_Pos) /*!< QSPI_T::STATUS: SSINAIF Mask */ + +#define QSPI_STATUS_SSLINE_Pos (4) /*!< QSPI_T::STATUS: SSLINE Position */ +#define QSPI_STATUS_SSLINE_Msk (0x1ul << QSPI_STATUS_SSLINE_Pos) /*!< QSPI_T::STATUS: SSLINE Mask */ + +#define QSPI_STATUS_SLVTOIF_Pos (5) /*!< QSPI_T::STATUS: SLVTOIF Position */ +#define QSPI_STATUS_SLVTOIF_Msk (0x1ul << QSPI_STATUS_SLVTOIF_Pos) /*!< QSPI_T::STATUS: SLVTOIF Mask */ + +#define QSPI_STATUS_SLVBEIF_Pos (6) /*!< QSPI_T::STATUS: SLVBEIF Position */ +#define QSPI_STATUS_SLVBEIF_Msk (0x1ul << QSPI_STATUS_SLVBEIF_Pos) /*!< QSPI_T::STATUS: SLVBEIF Mask */ + +#define QSPI_STATUS_SLVURIF_Pos (7) /*!< QSPI_T::STATUS: SLVURIF Position */ +#define QSPI_STATUS_SLVURIF_Msk (0x1ul << QSPI_STATUS_SLVURIF_Pos) /*!< QSPI_T::STATUS: SLVURIF Mask */ + +#define QSPI_STATUS_RXEMPTY_Pos (8) /*!< QSPI_T::STATUS: RXEMPTY Position */ +#define QSPI_STATUS_RXEMPTY_Msk (0x1ul << QSPI_STATUS_RXEMPTY_Pos) /*!< QSPI_T::STATUS: RXEMPTY Mask */ + +#define QSPI_STATUS_RXFULL_Pos (9) /*!< QSPI_T::STATUS: RXFULL Position */ +#define QSPI_STATUS_RXFULL_Msk (0x1ul << QSPI_STATUS_RXFULL_Pos) /*!< QSPI_T::STATUS: RXFULL Mask */ + +#define QSPI_STATUS_RXTHIF_Pos (10) /*!< QSPI_T::STATUS: RXTHIF Position */ +#define QSPI_STATUS_RXTHIF_Msk (0x1ul << QSPI_STATUS_RXTHIF_Pos) /*!< QSPI_T::STATUS: RXTHIF Mask */ + +#define QSPI_STATUS_RXOVIF_Pos (11) /*!< QSPI_T::STATUS: RXOVIF Position */ +#define QSPI_STATUS_RXOVIF_Msk (0x1ul << QSPI_STATUS_RXOVIF_Pos) /*!< QSPI_T::STATUS: RXOVIF Mask */ + +#define QSPI_STATUS_RXTOIF_Pos (12) /*!< QSPI_T::STATUS: RXTOIF Position */ +#define QSPI_STATUS_RXTOIF_Msk (0x1ul << QSPI_STATUS_RXTOIF_Pos) /*!< QSPI_T::STATUS: RXTOIF Mask */ + +#define QSPI_STATUS_SPIENSTS_Pos (15) /*!< QSPI_T::STATUS: SPIENSTS Position */ +#define QSPI_STATUS_SPIENSTS_Msk (0x1ul << QSPI_STATUS_SPIENSTS_Pos) /*!< QSPI_T::STATUS: SPIENSTS Mask */ + +#define QSPI_STATUS_TXEMPTY_Pos (16) /*!< QSPI_T::STATUS: TXEMPTY Position */ +#define QSPI_STATUS_TXEMPTY_Msk (0x1ul << QSPI_STATUS_TXEMPTY_Pos) /*!< QSPI_T::STATUS: TXEMPTY Mask */ + +#define QSPI_STATUS_TXFULL_Pos (17) /*!< QSPI_T::STATUS: TXFULL Position */ +#define QSPI_STATUS_TXFULL_Msk (0x1ul << QSPI_STATUS_TXFULL_Pos) /*!< QSPI_T::STATUS: TXFULL Mask */ + +#define QSPI_STATUS_TXTHIF_Pos (18) /*!< QSPI_T::STATUS: TXTHIF Position */ +#define QSPI_STATUS_TXTHIF_Msk (0x1ul << QSPI_STATUS_TXTHIF_Pos) /*!< QSPI_T::STATUS: TXTHIF Mask */ + +#define QSPI_STATUS_TXUFIF_Pos (19) /*!< QSPI_T::STATUS: TXUFIF Position */ +#define QSPI_STATUS_TXUFIF_Msk (0x1ul << QSPI_STATUS_TXUFIF_Pos) /*!< QSPI_T::STATUS: TXUFIF Mask */ + +#define QSPI_STATUS_TXRXRST_Pos (23) /*!< QSPI_T::STATUS: TXRXRST Position */ +#define QSPI_STATUS_TXRXRST_Msk (0x1ul << QSPI_STATUS_TXRXRST_Pos) /*!< QSPI_T::STATUS: TXRXRST Mask */ + +#define QSPI_STATUS_RXCNT_Pos (24) /*!< QSPI_T::STATUS: RXCNT Position */ +#define QSPI_STATUS_RXCNT_Msk (0xful << QSPI_STATUS_RXCNT_Pos) /*!< QSPI_T::STATUS: RXCNT Mask */ + +#define QSPI_STATUS_TXCNT_Pos (28) /*!< QSPI_T::STATUS: TXCNT Position */ +#define QSPI_STATUS_TXCNT_Msk (0xful << QSPI_STATUS_TXCNT_Pos) /*!< QSPI_T::STATUS: TXCNT Mask */ + +#define QSPI_STATUS2_SLVBENUM_Pos (24) /*!< QSPI_T::STATUS2: SLVBENUM Position */ +#define QSPI_STATUS2_SLVBENUM_Msk (0x3ful << QSPI_STATUS2_SLVBENUM_Pos) /*!< QSPI_T::STATUS2: SLVBENUM Mask */ + +#define QSPI_TX_TX_Pos (0) /*!< QSPI_T::TX: TX Position */ +#define QSPI_TX_TX_Msk (0xfffffffful << QSPI_TX_TX_Pos) /*!< QSPI_T::TX: TX Mask */ + +#define QSPI_RX_RX_Pos (0) /*!< QSPI_T::RX: RX Position */ +#define QSPI_RX_RX_Msk (0xfffffffful << QSPI_RX_RX_Pos) /*!< QSPI_T::RX: RX Mask */ + +/**@}*/ /* QSPI_CONST */ +/**@}*/ /* end of QSPI register group */ +/**@}*/ /* end of REGISTER group */ + +#endif /* __QSPI_REG_H__ */ diff --git a/Ubiquitous/XiZi/board/nuvoton-m2354/third_party_driver/include/Regs/rtc_reg.h b/Ubiquitous/XiZi/board/nuvoton-m2354/third_party_driver/include/Regs/rtc_reg.h new file mode 100644 index 0000000..5af6ce5 --- /dev/null +++ b/Ubiquitous/XiZi/board/nuvoton-m2354/third_party_driver/include/Regs/rtc_reg.h @@ -0,0 +1,1302 @@ +/**************************************************************************//** + * @file rtc_reg.h + * @version V1.00 + * @brief RTC register definition header file + * + * @copyright SPDX-License-Identifier: Apache-2.0 + * @copyright Copyright (C) 2020 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ +#ifndef __RTC_REG_H__ +#define __RTC_REG_H__ + +/** @addtogroup REGISTER Control Register + + @{ + +*/ + +/*---------------------- Real Time Clock Controller -------------------------*/ +/** + @addtogroup RTC Real Time Clock Controller(RTC) + Memory Mapped Structure for RTC Controller + @{ +*/ + +typedef struct +{ + + + /** + * @var RTC_T::INIT + * Offset: 0x00 RTC Initiation Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |INIT_ACTIVE|RTC Active Status (Read Only) + * | | |0 = RTC is at reset state. + * | | |1 = RTC is at normal active state. + * |[31:1] |INIT |RTC Initiation (Write Only) + * | | |When RTC block is powered on, RTC is at reset state. + * | | |User has to write a number (0xa5eb1357) to INIT to make RTC leave reset state. + * | | |Once the INIT is written as 0xa5eb1357, the RTC will be in un-reset state permanently. + * | | |The INIT is a write-only field and read value will be always 0. + * @var RTC_T::FREQADJ + * Offset: 0x08 RTC Frequency Compensation Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[5:0] |FRACTION |Fraction Part + * | | |Formula: FRACTION = (fraction part of detected value) X 64. + * | | |Note: Digit in FCR must be expressed as hexadecimal number. + * |[12:8] |INTEGER |Integer Part + * | | |00000 = Integer part of detected value is 32752. + * | | |00001 = Integer part of detected value is 32753. + * | | |00010 = Integer part of detected value is 32754. + * | | |00011 = Integer part of detected value is 32755. + * | | |00100 = Integer part of detected value is 32756. + * | | |00101 = Integer part of detected value is 32757. + * | | |00110 = Integer part of detected value is 32758. + * | | |00111 = Integer part of detected value is 32759. + * | | |01000 = Integer part of detected value is 32760. + * | | |01001 = Integer part of detected value is 32761. + * | | |01010 = Integer part of detected value is 32762. + * | | |01011 = Integer part of detected value is 32763. + * | | |01100 = Integer part of detected value is 32764. + * | | |01101 = Integer part of detected value is 32765. + * | | |01110 = Integer part of detected value is 32766. + * | | |01111 = Integer part of detected value is 32767. + * | | |10000 = Integer part of detected value is 32768. + * | | |10001 = Integer part of detected value is 32769. + * | | |10010 = Integer part of detected value is 32770. + * | | |10011 = Integer part of detected value is 32771. + * | | |10100 = Integer part of detected value is 32772. + * | | |10101 = Integer part of detected value is 32773. + * | | |10110 = Integer part of detected value is 32774. + * | | |10111 = Integer part of detected value is 32775. + * | | |11000 = Integer part of detected value is 32776. + * | | |11001 = Integer part of detected value is 32777. + * | | |11010 = Integer part of detected value is 32778. + * | | |11011 = Integer part of detected value is 32779. + * | | |11100 = Integer part of detected value is 32780. + * | | |11101 = Integer part of detected value is 32781. + * | | |11110 = Integer part of detected value is 32782. + * | | |11111 = Integer part of detected value is 32783. + * |[31] |FCRBUSY |Frequency Compensation Register Write Operation Busy (Read Only) + * | | |0 = The new register write operation is acceptable. + * | | |1 = The last write operation is in progress and new register write operation prohibited. + * | | |Note: This bit is only used when DCOMPEN(RTC_CLKFMT[16]) is enabled. + * @var RTC_T::TIME + * Offset: 0x0C RTC Time Loading Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[3:0] |SEC |1-Sec Time Digit (0~9) + * |[6:4] |TENSEC |10-Sec Time Digit (0~5) + * |[11:8] |MIN |1-Min Time Digit (0~9) + * |[14:12] |TENMIN |10-Min Time Digit (0~5) + * |[19:16] |HR |1-Hour Time Digit (0~9) + * |[21:20] |TENHR |10-Hour Time Digit (0~2) + * | | |When RTC runs as 12-hour time scale mode, RTC_TIME[21] (the high bit of TENHR[1:0]) means AM/PM indication (If RTC_TIME[21] is 1, it indicates PM time message.) + * @var RTC_T::CAL + * Offset: 0x10 RTC Calendar Loading Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[3:0] |DAY |1-Day Calendar Digit (0~9) + * |[5:4] |TENDAY |10-Day Calendar Digit (0~3) + * |[11:8] |MON |1-Month Calendar Digit (0~9) + * |[12] |TENMON |10-Month Calendar Digit (0~1) + * |[19:16] |YEAR |1-Year Calendar Digit (0~9) + * |[23:20] |TENYEAR |10-Year Calendar Digit (0~9) + * @var RTC_T::CLKFMT + * Offset: 0x14 RTC Time Scale Selection Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |24HEN |24-hour / 12-hour Time Scale Selection + * | | |The RTC_TIME and RTC_TALM are in 24-hour time scale or 12-hour time scale. + * | | |0 = 12-hour time scale with AM and PM indication selected. + * | | |1 = 24-hour time scale selected. + * |[16] |DCOMPEN |Dynamic Compensation Enable Bit + * | | |0 = Dynamic Compensation Disabled. + * | | |1 = Dynamic Compensation Enabled. + * @var RTC_T::WEEKDAY + * Offset: 0x18 RTC Day of the Week Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[2:0] |WEEKDAY |Day of the Week Register + * | | |000 = Sunday. + * | | |001 = Monday. + * | | |010 = Tuesday. + * | | |011 = Wednesday. + * | | |100 = Thursday. + * | | |101 = Friday. + * | | |110 = Saturday. + * | | |111 = Reserved. + * @var RTC_T::TALM + * Offset: 0x1C RTC Time Alarm Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[3:0] |SEC |1-Sec Time Digit of Alarm Setting (0~9) + * |[6:4] |TENSEC |10-Sec Time Digit of Alarm Setting (0~5) + * |[11:8] |MIN |1-Min Time Digit of Alarm Setting (0~9) + * |[14:12] |TENMIN |10-Min Time Digit of Alarm Setting (0~5) + * |[19:16] |HR |1-Hour Time Digit of Alarm Setting (0~9) + * |[21:20] |TENHR |10-Hour Time Digit of Alarm Setting (0~2) + * | | |When RTC runs as 12-hour time scale mode, RTC_TIME[21] (the high bit of TENHR[1:0]) means AM/PM indication (If RTC_TIME[21] is 1, it indicates PM time message.) + * @var RTC_T::CALM + * Offset: 0x20 RTC Calendar Alarm Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[3:0] |DAY |1-Day Calendar Digit of Alarm Setting (0~9) + * |[5:4] |TENDAY |10-Day Calendar Digit of Alarm Setting (0~3) + * |[11:8] |MON |1-Month Calendar Digit of Alarm Setting (0~9) + * |[12] |TENMON |10-Month Calendar Digit of Alarm Setting (0~1) + * |[19:16] |YEAR |1-Year Calendar Digit of Alarm Setting (0~9) + * |[23:20] |TENYEAR |10-Year Calendar Digit of Alarm Setting (0~9) + * @var RTC_T::LEAPYEAR + * Offset: 0x24 RTC Leap Year Indicator Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |LEAPYEAR |Leap Year Indication (Read Only) + * | | |0 = This year is not a leap year. + * | | |1 = This year is leap year. + * @var RTC_T::INTEN + * Offset: 0x28 RTC Interrupt Enable Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |ALMIEN |Alarm Interrupt Enable Bit + * | | |Set ALMIEN to 1 can also enable chip wake-up function when RTC alarm interrupt event is generated. + * | | |0 = RTC Alarm interrupt Disabled. + * | | |1 = RTC Alarm interrupt Enabled. + * |[1] |TICKIEN |Time Tick Interrupt Enable Bit + * | | |Set TICKIEN to 1 can also enable chip wake-up function when RTC tick interrupt event is generated. + * | | |0 = RTC Time Tick interrupt Disabled. + * | | |1 = RTC Time Tick interrupt Enabled. + * |[8] |TAMP0IEN |Tamper 0 Interrupt Enable Bit + * | | |Set TAMP0IEN to 1 can also enable chip wake-up function when tamper 0 interrupt event is generated. + * | | |0 = Tamper 0 interrupt Disabled. + * | | |1 = Tamper 0 interrupt Enabled. + * |[9] |TAMP1IEN |Tamper 1 or Pair 0 Interrupt Enable Bit + * | | |Set TAMP1IEN to 1 can also enable chip wake-up function when tamper 1 interrupt event is generated. + * | | |0 = Tamper 1 or Pair 0 interrupt Disabled. + * | | |1 = Tamper 1 or Pair 0 interrupt Enabled. + * |[10] |TAMP2IEN |Tamper 2 Interrupt Enable Bit + * | | |Set TAMP2IEN to 1 can also enable chip wake-up function when tamper 2 interrupt event is generated. + * | | |0 = Tamper 2 interrupt Disabled. + * | | |1 = Tamper 2 interrupt Enabled. + * |[11] |TAMP3IEN |Tamper 3 or Pair 1 Interrupt Enable Bit + * | | |Set TAMP3IEN to 1 can also enable chip wake-up function when tamper 3 interrupt event is generated. + * | | |0 = Tamper 3 or Pair 1 interrupt Disabled. + * | | |1 = Tamper 3 or Pair 1 interrupt Enabled. + * |[12] |TAMP4IEN |Tamper 4 Interrupt Enable Bit + * | | |Set TAMP4IEN to 1 can also enable chip wake-up function when tamper 4 interrupt event is generated. + * | | |0 = Tamper 4 interrupt Disabled. + * | | |1 = Tamper 4 interrupt Enabled. + * |[13] |TAMP5IEN |Tamper 5 or Pair 2 Interrupt Enable Bit + * | | |Set TAMP5IEN to 1 can also enable chip wake-up function when tamper 5 interrupt event is generated. + * | | |0 = Tamper 5 or Pair 2 interrupt Disabled. + * | | |1 = Tamper 5 or Pair 2 interrupt Enabled. + * |[24] |CLKFIEN |LXT Clock Frequency Monitor Fail Interrupt Enable Bit + * | | |0 = LXT Frequency Fail interrupt Disabled. + * | | |1 = LXT Frequency Fail interrupt Enabled. + * |[25] |CLKSTIEN |LXT Clock Frequency Monitor Stop Interrupt Enable Bit + * | | |0 = LXT Frequency Stop interrupt Disabled. + * | | |1 = LXT Frequency Stop interrupt Enabled. + * @var RTC_T::INTSTS + * Offset: 0x2C RTC Interrupt Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |ALMIF |RTC Alarm Interrupt Flag + * | | |0 = Alarm condition is not matched. + * | | |1 = Alarm condition is matched. + * | | |Note: Write 1 to clear this bit. + * |[1] |TICKIF |RTC Time Tick Interrupt Flag + * | | |0 = Tick condition does not occur. + * | | |1 = Tick condition occur. + * | | |Note: Write 1 to clear this bit. + * |[8] |TAMP0IF |Tamper 0 Interrupt Flag + * | | |This bit is set when TAMP0_PIN detected level non-equal TAMP0LV (RTC_TAMPCTL[9]). + * | | |0 = No Tamper 0 interrupt flag is generated. + * | | |1 = Tamper 0 interrupt flag is generated. + * | | |Note1: Write 1 to clear this bit. + * | | |Note2: This interrupt flag will be generated again when Tamper setting condition is not restoration. + * | | |Note3: Need to clear all TAMPxIF, after that, new RTC_TAMPTIME and RTC_TAMPCAL values are loaded while a tamper event occurred. + * |[9] |TAMP1IF |Tamper 1 or Pair 0 Interrupt Flag + * | | |This bit is set when TAMP1_PIN detected level non-equal TAMP1LV (RTC_TAMPCTL[13]) or TAMP0_PIN and TAMP1_PIN disconnected during DYNPR0EN (RTC_TAMPCTL[15]) is activated. + * | | |0 = No Tamper 1 or Pair 0 interrupt flag is generated. + * | | |1 = Tamper 1 or Pair 0 interrupt flag is generated. + * | | |Note1: Write 1 to clear this bit. + * | | |Note2: This interrupt flag will be generated again when Tamper setting condition is not restoration. + * | | |Note3: Need to clear all TAMPxIF, after that, new RTC_TAMPTIME and RTC_TAMPCAL values are loaded while a tamper event occurred. + * |[10] |TAMP2IF |Tamper 2 Interrupt Flag + * | | |This bit is set when TAMP2_PIN detected level non-equal TAMP2LV (RTC_TAMPCTL[17]). + * | | |0 = No Tamper 2 interrupt flag is generated. + * | | |1 = Tamper 2 interrupt flag is generated. + * | | |Note1: Write 1 to clear this bit. + * | | |Note2: This interrupt flag will be generated again when Tamper setting condition is not restoration. + * | | |Note3: Need to clear all TAMPxIF, after that, new RTC_TAMPTIME and RTC_TAMPCAL values are loaded while a tamper event occurred. + * |[11] |TAMP3IF |Tamper 3 or Pair 1 Interrupt Flag + * | | |This bit is set when TAMP3_PIN detected level non-equal TAMP3LV (RTC_TAMPCTL[21]) or TAMP2_PIN and TAMP3_PIN disconnected during DYNPR1EN (RTC_TAMPCTL[23]) is activated or + * | | |TAMP0_PIN and TAMP3_PIN disconnected during DYNPR1EN (RTC_TAMPCTL[23]) and DYN1ISS (RTC_TAMPCTL[0]) are activated. + * | | |0 = No Tamper 3 or Pair 1 interrupt flag is generated. + * | | |1 = Tamper 3 or Pair 1 interrupt flag is generated. + * | | |Note1: Write 1 to clear this bit. + * | | |Note2: This interrupt flag will be generated again when Tamper setting condition is not restoration. + * | | |Note3: Need to clear all TAMPxIF, after that, new RTC_TAMPTIME and RTC_TAMPCAL values are loaded while a tamper event occurred. + * |[12] |TAMP4IF |Tamper 4 Interrupt Flag + * | | |This bit is set when TAMP4_PIN detected level non-equal TAMP4LV (RTC_TAMPCTL[25]). + * | | |0 = No Tamper 4 interrupt flag is generated. + * | | |1 = Tamper 4 interrupt flag is generated. + * | | |Note1: Write 1 to clear this bit. + * | | |Note2: This interrupt flag will be generated again when Tamper setting condition is not restoration. + * | | |Note3: Need to clear all TAMPxIF, after that, new RTC_TAMPTIME and RTC_TAMPCAL values are loaded while a tamper event occurred. + * |[13] |TAMP5IF |Tamper 5 or Pair 2 Interrupt Flag + * | | |This bit is set when TAMP5_PIN detected level non-equal TAMP5LV (RTC_TAMPCTL[29]) or TAMP4_PIN and TAMP5_PIN disconnected during DYNPR2EN (RTC_TAMPCTL[31]) is activated or + * | | |TAMP0_PIN and TAMP5_PIN disconnected during DYNPR2EN (RTC_TAMPCTL[31]) and DYN2ISS (RTC_TAMPCTL[1]) are activated. + * | | |0 = No Tamper 5 or Pair 2 interrupt flag is generated. + * | | |1 = Tamper 5 or Pair 2 interrupt flag is generated. + * | | |Note1: Write 1 to clear this bit. + * | | |Note2: This interrupt flag will be generated again when Tamper setting condition is not restoration. + * | | |Note3: Need to clear all TAMPxIF, after that, new RTC_TAMPTIME and RTC_TAMPCAL values are loaded while a tamper event occurred. + * |[24] |CLKFIF |LXT Clock Frequency Monitor Fail Interrupt Flag + * | | |0 = LXT frequency is normal. + * | | |1 = LXT frequency is abnormal. + * | | |Note1: Write 1 to clear the bit to 0. + * | | |Note2: LXT detector will automatic disable when Fail/Stop Flag rise, resume after Fail/Stop Flag clear. + * |[25] |CLKSTIF |LXT Clock Frequency Monitor Stop Interrupt Flag + * | | |0 = LXT frequency is normal. + * | | |1 = LXT frequency is almost stop. + * | | |Note1: Write 1 to clear the bit to 0. + * | | |Note2: LXT detector will automatic disable when Fail/Stop Flag rise, resume after Fail/Stop Flag clear. + * @var RTC_T::TICK + * Offset: 0x30 RTC Time Tick Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[2:0] |TICK |Time Tick Register + * | | |These bits are used to select RTC time tick period for Periodic Time Tick Interrupt request. + * | | |000 = Time tick is 1 second. + * | | |001 = Time tick is 1/2 second. + * | | |010 = Time tick is 1/4 second. + * | | |011 = Time tick is 1/8 second. + * | | |100 = Time tick is 1/16 second. + * | | |101 = Time tick is 1/32 second. + * | | |110 = Time tick is 1/64 second. + * | | |111 = Time tick is 1/128 second. + * @var RTC_T::TAMSK + * Offset: 0x34 RTC Time Alarm Mask Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |MSEC |Mask 1-Sec Time Digit of Alarm Setting (0~9) + * |[1] |MTENSEC |Mask 10-Sec Time Digit of Alarm Setting (0~5) + * |[2] |MMIN |Mask 1-Min Time Digit of Alarm Setting (0~9) + * |[3] |MTENMIN |Mask 10-Min Time Digit of Alarm Setting (0~5) + * |[4] |MHR |Mask 1-Hour Time Digit of Alarm Setting (0~9) + * | | |Note: MHR function is only for 24-hour time scale mode. + * |[5] |MTENHR |Mask 10-Hour Time Digit of Alarm Setting (0~2) + * | | |Note: MTENHR function is only for 24-hour time scale mode. + * @var RTC_T::CAMSK + * Offset: 0x38 RTC Calendar Alarm Mask Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |MDAY |Mask 1-Day Calendar Digit of Alarm Setting (0~9) + * |[1] |MTENDAY |Mask 10-Day Calendar Digit of Alarm Setting (0~3) + * |[2] |MMON |Mask 1-Month Calendar Digit of Alarm Setting (0~9) + * |[3] |MTENMON |Mask 10-Month Calendar Digit of Alarm Setting (0~1) + * |[4] |MYEAR |Mask 1-Year Calendar Digit of Alarm Setting (0~9) + * |[5] |MTENYEAR |Mask 10-Year Calendar Digit of Alarm Setting (0~9) + * @var RTC_T::SPRCTL + * Offset: 0x3C RTC Spare Functional Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[2] |SPRRWEN |Spare Register Enable Bit + * | | |0 = Spare register Disabled. + * | | |1 = Spare register Enabled. + * | | |Note: When spare register is disabled, RTC_SPR0 ~ RTC_SPR19 cannot be accessed. + * |[5] |SPRCSTS |SPR Clear Flag + * | | |This bit indicates if the RTC_SPR0 ~ RTC_SPR19 content is cleared when specify tamper event is detected. + * | | |0 = Spare register content is not cleared. + * | | |1 = Spare register content is cleared. + * | | |Note 1: Writes 1 to clear this bit. + * | | |Note 2: This bit keep 1 when RTC_INTSTS[13:8] or RTC_INTSTS[25:24] are not equal zero. + * |[16] |LXTFCLR |LXT Clock Fail/Stop to Clear Spare Enable Bit + * | | |0 = LXT Fail/Stop to clear Spare register content Disabled. + * | | |1 = LXT Fail/Stop to clear Spare register content Enabled. + * @var RTC_T::SPR[20] + * Offset: 0x40 ~ 0x8C RTC Spare Register 0 ~ 19 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |SPARE |Spare Register + * | | |This field is used to store back-up information defined by user. + * | | |This field will be cleared by hardware automatically in the following conditions, a tamper pin event is detected, + * | | |LXT clock fail/stop event occurs if LXTFCLR(RTC_SPRCTL[16]) is 1, or after Flash mass operation. + * @var RTC_T::LXTCTL + * Offset: 0x100 RTC 32.768 kHz Oscillator Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |LIRC32KEN |Enable LIRC32K Source + * | | |0 = LIRC32K Disabled. + * | | |1 = LIRC32K Enabled. + * |[3:1] |GAIN |Oscillator Gain Option + * | | |User can select oscillator gain according to crystal external loading and operating temperature range. + * | | |The larger gain value corresponding to stronger driving capability and higher power consumption. + * | | |000 = L0 mode. + * | | |001 = L1 mode. + * | | |010 = L2 mode. + * | | |011 = L3 mode. + * | | |100 = L4 mode. + * | | |101 = L5 mode. + * | | |110 = L6 mode. + * | | |111 = L7 mode (Default). + * |[6] |C32KSEL |Clock 32K Source Selection + * | | |0 = Clock source from external low speed crystal oscillator (LXT). + * | | |1 = Clock source from internal low speed RC 32K oscillator (LIRC32K). + * |[7] |RTCCKSEL |RTC Clock Source Selection + * | | |0 = Clock source from external low speed crystal oscillator (LXT) or internal low speed RC 32K oscillator (LIRC32K) depended on C32KSEL value. + * | | |1 = Clock source from internal low speed RC oscillator (LIRC). + * |[8] |IOCTLSEL |IO Pin Backup Control Selection + * | | |When low speed 32 kHz oscillator is disabled or TAMPxEN is disabled, + * | | |PF.4 pin (X32KO pin), PF.5 pin (X32KI pin) or PF.6~11 pin (TAMPERx pin) can be used as GPIO function. + * | | |User can program IOCTLSEL to decide PF.4~11 I/O function is controlled by system power domain GPIO module or VBAT power domain RTC_GPIOCTL0/1 control register. + * | | |0 = PF.4~11 pin I/O function is controlled by GPIO module. + * | | |1 = PF.4~11 pin I/O function is controlled by VBAT power domain. + * | | |Note: IOCTLSEL will automatically be set by hardware to 1 when system power is off and any writable RTC registers has been written at RTCCKEN(CLK_APBCLK0[1]) enabled. + * @var RTC_T::GPIOCTL0 + * Offset: 0x104 RTC GPIO Control 0 Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[1:0] |OPMODE0 |IO Operation Mode + * | | |00 = PF.4 is input only mode. + * | | |01 = PF.4 is output push pull mode. + * | | |10 = PF.4 is open drain mode. + * | | |11 = PF.4 is quasi-bidirectional mod. + * |[2] |DOUT0 |IO Output Data + * | | |0 = PF.4 output low. + * | | |1 = PF.4 output high. + * |[3] |DINOFF0 |IO Pin Digital Input Path Disable Bit + * | | |0 = PF.4 digital input path Enabled. + * | | |1 = PF.4 digital input path Disabled (digital input tied to low). + * |[5:4] |PUSEL0 |IO Pull-up and Pull-down Enable Bits + * | | |Determine PF.4 I/O pull-up or pull-down. + * | | |00 = PF.4 pull-up and pull-down Disabled. + * | | |01 = PF.4 pull-up Enabled. + * | | |10 = PF.4 pull-down Enabled. + * | | |11 = PF.4 pull-up and pull-down Disabled. + * | | |Note: Basically, the pull-up control and pull-down control has following behavior limitation. + * | | |The independent pull-up/pull-down control register is only valid when OPMODE0 is set as input tri-state and open-drain mode. + * |[9:8] |OPMODE1 |IO Operation Mode + * | | |00 = PF.5 is input only mode. + * | | |01 = PF.5 is output push pull mode. + * | | |10 = PF.5 is open drain mode. + * | | |11 = PF.5 is quasi-bidirectional mod. + * |[10] |DOUT1 |IO Output Data + * | | |0 = PF.5 output low. + * | | |1 = PF.5 output high. + * |[11 |DINOFF1 |IO Pin Digital Input Path Disable Bit + * | | |0 = PF.5 digital input path Enabled. + * | | |1 = PF.5 digital input path Disabled (digital input tied to low). + * |[13:12] |PUSEL1 |IO Pull-up and Pull-down Enable Bits + * | | |Determine PF.5 I/O pull-up or pull-down. + * | | |00 = PF.5 pull-up and pull-down Disabled. + * | | |01 = PF.5 pull-up Enabled. + * | | |10 = PF.5 pull-down Enabled. + * | | |11 = PF.5 pull-up and pull-down Disabled. + * | | |Note: Basically, the pull-up control and pull-down control has following behavior limitation. + * | | |The independent pull-up/pull-down control register is only valid when OPMODE1 is set as input tri-state and open-drain mode. + * |[17:16] |OPMODE2 |IO Operation Mode + * | | |00 = PF.6 is input only mode. + * | | |01 = PF.6 is output push pull mode. + * | | |10 = PF.6 is open drain mode. + * | | |11 = PF.6 is quasi-bidirectional mod. + * |[18] |DOUT2 |IO Output Data + * | | |0 = PF.6 output low. + * | | |1 = PF.6 output high. + * |[19 |DINOFF2 |IO Pin Digital Input Path Disable Bit + * | | |0 = PF.6 digital input path Enabled. + * | | |1 = PF.6 digital input path Disabled (digital input tied to low). + * |[21:20] |PUSEL2 |IO Pull-up and Pull-down Enable Bits + * | | |Determine PF.6 I/O pull-up or pull-down. + * | | |00 = PF.6 pull-up and pull-down Disabled. + * | | |01 = PF.6 pull-up Enabled. + * | | |10 = PF.6 pull-down Enabled. + * | | |11 = PF.6 pull-up and pull-down Disabled. + * | | |Note: Basically, the pull-up control and pull-down control has following behavior limitation. + * | | |The independent pull-up/pull-down control register is only valid when OPMODE2 is set as input tri-state and open-drain mode. + * |[25:24] |OPMODE3 |IO Operation Mode + * | | |00 = PF.7 is input only mode. + * | | |01 = PF.7 is output push pull mode. + * | | |10 = PF.7 is open drain mode. + * | | |11 = PF.7 is quasi-bidirectional mod. + * |[26] |DOUT3 |IO Output Data + * | | |0 = PF.7 output low. + * | | |1 = PF.7 output high. + * |[27 |DINOFF3 |IO Pin Digital Input Path Disable Bit + * | | |0 = PF.7 digital input path Enabled. + * | | |1 = PF.7 digital input path Disabled (digital input tied to low). + * |[29:28] |PUSEL3 |IO Pull-up and Pull-down Enable Bits + * | | |Determine PF.7 I/O pull-up or pull-down. + * | | |00 = PF.7 pull-up and pull-down Disabled. + * | | |01 = PF.7 pull-up Enabled. + * | | |10 = PF.7 pull-down Enabled. + * | | |11 = PF.7 pull-up and pull-down Disabled. + * | | |Note: Basically, the pull-up control and pull-down control has following behavior limitation. + * | | |The independent pull-up/pull-down control register is only valid when OPMODE3 is set as input tri-state and open-drain mode. + * @var RTC_T::GPIOCTL1 + * Offset: 0x108 RTC GPIO Control 1 Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[1:0] |OPMODE4 |IO Operation Mode + * | | |00 = PF.8 is input only mode. + * | | |01 = PF.8 is output push pull mode. + * | | |10 = PF.8 is open drain mode. + * | | |11 = PF.8 is quasi-bidirectional mod. + * |[2] |DOUT4 |IO Output Data + * | | |0 = PF.8 output low. + * | | |1 = PF.8 output high. + * |[3] |DINOFF4 |IO Pin Digital Input Path Disable Bit + * | | |0 = PF.8 digital input path Enabled. + * | | |1 = PF.8 digital input path Disabled (digital input tied to low). + * |[5:4] |PUSEL4 |IO Pull-up and Pull-down Enable Bits + * | | |Determine PF.8 I/O pull-up or pull-down. + * | | |00 = PF.8 pull-up and pull-down Disabled. + * | | |01 = PF.8 pull-up Enabled. + * | | |10 = PF.8 pull-down Enabled. + * | | |11 = PF.8 pull-up and pull-down Disabled. + * | | |Note: Basically, the pull-up control and pull-down control has following behavior limitation. + * | | |The independent pull-up/pull-down control register is only valid when OPMODE4 is set as input tri-state and open-drain mode. + * |[9:8] |OPMODE5 |IO Operation Mode + * | | |00 = PF.9 is input only mode. + * | | |01 = PF.9 is output push pull mode. + * | | |10 = PF.9 is open drain mode. + * | | |11 = PF.9 is quasi-bidirectional mod. + * |[10] |DOUT5 |IO Output Data + * | | |0 = PF.9 output low. + * | | |1 = PF.9 output high. + * |[11 |DINOFF5 |IO Pin Digital Input Path Disable Bit + * | | |0 = PF.9 digital input path Enabled. + * | | |1 = PF.9 digital input path Disabled (digital input tied to low). + * |[13:12] |PUSEL5 |IO Pull-up and Pull-down Enable Bits + * | | |Determine PF.9 I/O pull-up or pull-down. + * | | |00 = PF.9 pull-up and pull-down Disabled. + * | | |01 = PF.9 pull-up Enabled. + * | | |10 = PF.9 pull-down Enabled. + * | | |11 = PF.9 pull-up and pull-down Disabled. + * | | |Note: Basically, the pull-up control and pull-down control has following behavior limitation. + * | | |The independent pull-up/pull-down control register is only valid when OPMODE5 is set as input tri-state and open-drain mode. + * |[17:16] |OPMODE6 |IO Operation Mode + * | | |00 = PF.10 is input only mode. + * | | |01 = PF.10 is output push pull mode. + * | | |10 = PF.10 is open drain mode. + * | | |11 = PF.10 is quasi-bidirectional mod. + * |[18] |DOUT6 |IO Output Data + * | | |0 = PF.10 output low. + * | | |1 = PF.10 output high. + * |[19 |DINOFF6 |IO Pin Digital Input Path Disable Bit + * | | |0 = PF.10 digital input path Enabled. + * | | |1 = PF.10 digital input path Disabled (digital input tied to low). + * |[21:20] |PUSEL6 |IO Pull-up and Pull-down Enable Bits + * | | |Determine PF.10 I/O pull-up or pull-down. + * | | |00 = PF.10 pull-up and pull-down Disabled. + * | | |01 = PF.10 pull-up Enabled. + * | | |10 = PF.10 pull-down Enabled. + * | | |11 = PF.10 pull-up and pull-down Disabled. + * | | |Note: Basically, the pull-up control and pull-down control has following behavior limitation. + * | | |The independent pull-up/pull-down control register is only valid when OPMODE6 is set as input tri-state and open-drain mode. + * |[25:24] |OPMODE7 |IO Operation Mode + * | | |00 = PF.11 is input only mode. + * | | |01 = PF.11 is output push pull mode. + * | | |10 = PF.11 is open drain mode. + * | | |11 = PF.11 is quasi-bidirectional mod. + * |[26] |DOUT7 |IO Output Data + * | | |0 = PF.11 output low. + * | | |1 = PF.11 output high. + * |[27 |DINOFF7 |IO Pin Digital Input Path Disable Bit + * | | |0 = PF.11 digital input path Enabled. + * | | |1 = PF.11 digital input path Disabled (digital input tied to low). + * |[29:28] |PUSEL7 |IO Pull-up and Pull-down Enable Bits + * | | |Determine PF.11 I/O pull-up or pull-down. + * | | |00 = PF.11 pull-up and pull-down Disabled. + * | | |01 = PF.11 pull-up Enabled. + * | | |10 = PF.11 pull-down Enabled. + * | | |11 = PF.11 pull-up and pull-down Disabled. + * | | |Note: Basically, the pull-up control and pull-down control has following behavior limitation. + * | | |The independent pull-up/pull-down control register is only valid when OPMODE7 is set as input tri-state and open-drain mode. + * @var RTC_T::DSTCTL + * Offset: 0x110 RTC Daylight Saving Time Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |ADDHR |Add 1 Hour + * | | |0 = No effect. + * | | |1 = Indicates RTC hour digit has been added one hour for summer time change. + * |[1] |SUBHR |Subtract 1 Hour + * | | |0 = No effect. + * | | |1 = Indicates RTC hour digit has been subtracted one hour for winter time change. + * |[2] |DSBAK |Daylight Saving Back + * | | |0 = Daylight Saving Change is not performed. + * | | |1 = Daylight Saving Change is performed. + * @var RTC_T::TAMPCTL + * Offset: 0x120 RTC Tamper Pin Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |DYN1ISS |Dynamic Pair 1 Input Source Select + * | | |This bit determine Tamper 3 input is from Tamper 2 or Tamper 0 in dynamic mode. + * | | |0 = Tamper input is from Tamper 2. + * | | |1 = Tamper input is from Tamper 0. + * | | |Note: This bit is effective only when DYNPR1EN (RTC_TAMPCTL[23]) and DYNPR0EN (RTC_TAMPCTL[15]) are set. + * |[1] |DYN2ISS |Dynamic Pair 2 Input Source Select + * | | |This bit determine Tamper 5 input is from Tamper 4 or Tamper 0 in dynamic mode. + * | | |0 = Tamper input is from Tamper 4. + * | | |1 = Tamper input is from Tamper 0. + * | | |Note: This bit is effective only when DYNPR2EN (RTC_TAMPCTL[31]) and DYNPR0EN (RTC_TAMPCTL[15]) are set. + * |[3] |DYNSRC |Dynamic Reference Pattern + * | | |This fields determine the new reference pattern when current pattern run out in dynamic pair mode. + * | | |0 = The new reference pattern is generated by random number generator when the reference pattern run out. + * | | |1 = The new reference pattern is repeated from SEED (RTC_TAMPSEED[31:0]) when the reference pattern run out. + * | | |Note: After this bit is modified, the SEEDRLD (RTC_TAMPCTL[4]) should be set. + * |[4] |SEEDRLD |Reload New Seed for PRNG Engine + * | | |Setting this bit, the tamper configuration will be reload. + * | | |0 = Generating key based on the current seed. + * | | |1 = Reload new seed. + * | | |Note 1: Before this bit is set, the tamper configuration should be set to complete and this bit will be auto clear to 0 after reload new seed completed. + * | | |Note 2: The reference is RTC clock. Tamper detector need sync 2 ~ 3 RTC clock. + * |[7:5] |DYNRATE |Dynamic Change Rate + * | | |This item is choice the dynamic tamper output change rate. + * | | |000 = 2^10 * RTC_CLK. + * | | |001 = 2^11 * RTC_CLK. + * | | |010 = 2^12 * RTC_CLK. + * | | |011 = 2^13 * RTC_CLK. + * | | |100 = 2^14 * RTC_CLK. + * | | |101 = 2^15 * RTC_CLK. + * | | |110 = 2^16 * RTC_CLK. + * | | |111 = 2^17 * RTC_CLK. + * | | |Note: After revising this field, set SEEDRLD (RTC_TAMPCTL[4]) can reload change rate immediately. + * |[8] |TAMP0EN |Tamper0 Detect Enable Bit + * | | |0 = Tamper 0 detect Disabled. + * | | |1 = Tamper 0 detect Enabled. + * | | |Note1: The reference is RTC clock. Tamper detector need sync 2 ~ 3 RTC clock. + * |[9] |TAMP0LV |Tamper 0 Level + * | | |This bit depend on level attribute of tamper pin for static tamper detection. + * | | |0 = Detect voltage level is low. + * | | |1 = Detect voltage level is high. + * |[10] |TAMP0DBEN |Tamper 0 De-bounce Enable Bit + * | | |0 = Tamper 0 de-bounce Disabled. + * | | |1 = Tamper 0 de-bounce Enabled. + * |[12] |TAMP1EN |Tamper 1 Detect Enable Bit + * | | |0 = Tamper 1 detect Disabled. + * | | |1 = Tamper 1 detect Enabled. + * | | |Note1: The reference is RTC clock. Tamper detector need sync 2 ~ 3 RTC clock. + * |[13] |TAMP1LV |Tamper 1 Level + * | | |This bit depend on level attribute of tamper pin for static tamper detection. + * | | |0 = Detect voltage level is low. + * | | |1 = Detect voltage level is high. + * |[14] |TAMP1DBEN |Tamper 1 De-bounce Enable Bit + * | | |0 = Tamper 1 de-bounce Disabled. + * | | |1 = Tamper 1 de-bounce Enabled. + * |[15] |DYNPR0EN |Dynamic Pair 0 Enable Bit + * | | |0 = Static detect. + * | | |1 = Dynamic detect. + * |[16] |TAMP2EN |Tamper 2 Detect Enable Bit + * | | |0 = Tamper 2 detect Disabled. + * | | |1 = Tamper 2 detect Enabled. + * | | |Note1: The reference is RTC clock. Tamper detector need sync 2 ~ 3 RTC clock. + * |[17] |TAMP2LV |Tamper 2 Level + * | | |This bit depend on level attribute of tamper pin for static tamper detection. + * | | |0 = Detect voltage level is low. + * | | |1 = Detect voltage level is high. + * |[18] |TAMP2DBEN |Tamper 2 De-bounce Enable Bit + * | | |0 = Tamper 2 de-bounce Disabled. + * | | |1 = Tamper 2 de-bounce Enabled. + * |[20] |TAMP3EN |Tamper 3 Detect Enable Bit + * | | |0 = Tamper 3 detect Disabled. + * | | |1 = Tamper 3 detect Enabled. + * | | |Note1: The reference is RTC clock. Tamper detector need sync 2 ~ 3 RTC clock. + * |[21] |TAMP3LV |Tamper 3 Level + * | | |This bit depend on level attribute of tamper pin for static tamper detection. + * | | |0 = Detect voltage level is low. + * | | |1 = Detect voltage level is high. + * |[22] |TAMP3DBEN |Tamper 3 De-bounce Enable Bit + * | | |0 = Tamper 3 de-bounce Disabled. + * | | |1 = Tamper 3 de-bounce Enabled. + * |[23] |DYNPR1EN |Dynamic Pair 1 Enable Bit + * | | |0 = Static detect. + * | | |1 = Dynamic detect. + * |[24] |TAMP4EN |Tamper4 Detect Enable Bit + * | | |0 = Tamper 4 detect Disabled. + * | | |1 = Tamper 4 detect Enabled. + * | | |Note1: The reference is RTC clock. Tamper detector need sync 2 ~ 3 RTC clock. + * |[25] |TAMP4LV |Tamper 4 Level + * | | |This bit depend on level attribute of tamper pin for static tamper detection. + * | | |0 = Detect voltage level is low. + * | | |1 = Detect voltage level is high. + * |[26] |TAMP4DBEN |Tamper 4 De-bounce Enable Bit + * | | |0 = Tamper 4 de-bounce Disabled. + * | | |1 = Tamper 4 de-bounce Enabled. + * |[28] |TAMP5EN |Tamper 5 Detect Enable Bit + * | | |0 = Tamper 5 detect Disabled. + * | | |1 = Tamper 5 detect Enabled. + * | | |Note1: The reference is RTC clock. Tamper detector need sync 2 ~ 3 RTC clock. + * |[29] |TAMP5LV |Tamper 5 Level + * | | |This bit depend on level attribute of tamper pin for static tamper detection. + * | | |0 = Detect voltage level is low. + * | | |1 = Detect voltage level is high. + * |[30] |TAMP5DBEN |Tamper 5 De-bounce Enable Bit + * | | |0 = Tamper 5 de-bounce Disabled. + * | | |1 = Tamper 5 de-bounce Enabled. + * |[31] |DYNPR2EN |Dynamic Pair 2 Enable Bit + * | | |0 = Static detect. + * | | |1 = Dynamic detect. + * @var RTC_T::TAMPSEED + * Offset: 0x128 RTC Tamper Dynamic Seed Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |SEED |Seed Value + * @var RTC_T::TAMPTIME + * Offset: 0x130 RTC Tamper Time Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[3:0] |SEC |1-Sec Time Digit of TAMPER Time (0~9) + * |[6:4] |TENSEC |10-Sec Time Digit of TAMPER Time (0~5) + * |[11:8] |MIN |1-Min Time Digit of TAMPER Time (0~9) + * |[14:12] |TENMIN |10-Min Time Digit of TAMPER Time (0~5) + * |[19:16] |HR |1-Hour Time Digit of TAMPER Time (0~9) + * |[21:20] |TENHR |10-Hour Time Digit of TAMPER Time (0~2) + * | | |Note: 24-hour time scale only. + * @var RTC_T::TAMPCAL + * Offset: 0x134 RTC Tamper Calendar Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[3:0] |DAY |1-Day Calendar Digit of TAMPER Calendar (0~9) + * |[5:4] |TENDAY |10-Day Calendar Digit of TAMPER Calendar (0~3) + * |[11:8] |MON |1-Month Calendar Digit of TAMPER Calendar (0~9) + * |[12] |TENMON |10-Month Calendar Digit of TAMPER Calendar (0~1) + * |[19:16] |YEAR |1-Year Calendar Digit of TAMPER Calendar (0~9) + * |[23:20] |TENYEAR |10-Year Calendar Digit of TAMPER Calendar (0~9) + * @var RTC_T::CLKDCTL + * Offset: 0x140 RTC Clock Fail Detector Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |LXTFDEN |LXT Clock Fail/Stop Detector Enable Bit + * | | |0 = LXT clock Fail/Stop detector Disabled. + * | | |1 = LXT clock Fail/Stop detector Enabled. + * | | |Note: LXT detector will automatic disable when Fail/Stop Flag rise, resume after Fail/Stop Flag clear. + * |[1] |LXTFSW |LXT Clock Fail Detector Switch LIRC32K Enable Bit + * | | |0 = LXT clock Fail switch LIRC32K Disabled. + * | | |1 = LXT clock Fail detector rise, RTC clock source switch from LIRC32K. + * | | |If LXT clock fail detector flag CLKFIF (RTC_INTSTS[24]) is generated, RTC clock source will switch to LIRC32K automatically. + * |[2] |LXTSTSW |LXT Clock Stop Detector Switch LIRC32K Enable Bit + * | | |0 = LXT clock Stop switch LIRC32K Disabled. + * | | |1 = LXT clock Stop detector rise, RTC clock source switch from LIRC32K. + * | | |If LXT clock stop detector flag CLKSTIF (RTC_INTSTS[25]) is generated, RTC clock source will switch to LIRC32K automatically + * |[16] |SWLIRCF |LXT Clock Detector Fail/Stop Switch LIRC32K Flag (Read Only) + * | | |0 = Indicate RTC clock source from LXT. + * | | |1 = Indicate RTC clock source from LIRC32K. + * |[17] |LXTSLOWF |LXT Slower Than LIRC32K Flag (Read Only) + * | | |0 = LXT frequency faster than LIRC32K. + * | | |1 = LXT frequency is slowly. + * | | |Note: LXTSLOWF is vaild during CLKSTIF (RTC_INTSTS[25]) or CLKFIF (RTC_INTSTS[24]) rising. + * @var RTC_T::CDBR + * Offset: 0x144 RTC Clock Frequency Detector Boundary Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[7:0] |STOPBD |LXT Clock Stop Frequency Detector Stop Boundary + * | | |These bits define the stop value of frequency monitor window. + * | | |When LXT frequency monitor counter lower than STOPBD, the LXT frequency detect Stop interrupt flag will set to 1. + * | | |Note: The boundary is defined as the maximum value of LXT among 256 LIRC32K clock time. + * |[23:16] |FAILBD |LXT Clock Frequency Detector Fail Boundary + * | | |These bits define the fail value of frequency monitor window. + * | | |When LXT frequency monitor counter lower than FAILBD, the LXT frequency detect fail interrupt flag will set to 1. + * | | |Note: The boundary is defined as the maximum value of LXT among 256 LIRC32K clock time. + */ + __IO uint32_t INIT; /*!< [0x0000] RTC Initiation Register */ + __I uint32_t RESERVE0[1]; /* 0x4 */ + __IO uint32_t FREQADJ; /*!< [0x0008] RTC Frequency Compensation Register */ + __IO uint32_t TIME; /*!< [0x000c] RTC Time Loading Register */ + __IO uint32_t CAL; /*!< [0x0010] RTC Calendar Loading Register */ + __IO uint32_t CLKFMT; /*!< [0x0014] RTC Time Scale Selection Register */ + __IO uint32_t WEEKDAY; /*!< [0x0018] RTC Day of the Week Register */ + __IO uint32_t TALM; /*!< [0x001c] RTC Time Alarm Register */ + __IO uint32_t CALM; /*!< [0x0020] RTC Calendar Alarm Register */ + __I uint32_t LEAPYEAR; /*!< [0x0024] RTC Leap Year Indicator Register */ + __IO uint32_t INTEN; /*!< [0x0028] RTC Interrupt Enable Register */ + __IO uint32_t INTSTS; /*!< [0x002c] RTC Interrupt Status Register */ + __IO uint32_t TICK; /*!< [0x0030] RTC Time Tick Register */ + __IO uint32_t TAMSK; /*!< [0x0034] RTC Time Alarm Mask Register */ + __IO uint32_t CAMSK; /*!< [0x0038] RTC Calendar Alarm Mask Register */ + __IO uint32_t SPRCTL; /*!< [0x003c] RTC Spare Functional Control Register */ + __IO uint32_t SPR[20]; /*!< [0x0040] ~ [0x008C] RTC Spare Register 0 ~ 19 */ + __I uint32_t RESERVE1[28]; /* 0x90 ~ 0xfc */ + __IO uint32_t LXTCTL; /*!< [0x0100] RTC 32.768 kHz Oscillator Control Register */ + __IO uint32_t GPIOCTL0; /*!< [0x0104] RTC GPIO Control 0 Register */ + __IO uint32_t GPIOCTL1; /*!< [0x0108] RTC GPIO Control 1 Register */ + __I uint32_t RESERVE2[1]; /* 0x10c */ + __IO uint32_t DSTCTL; /*!< [0x0110] RTC Daylight Saving Time Control Register */ + __I uint32_t RESERVE3[3]; /* 0x114 ~ 0x11c */ + __IO uint32_t TAMPCTL; /*!< [0x0120] RTC Tamper Pin Control Register */ + __I uint32_t RESERVE4[1]; /* 0x124 */ + __IO uint32_t TAMPSEED; /*!< [0x0128] RTC Tamper Dynamic Seed Register */ + __I uint32_t RESERVE5[1]; /* 0x12c */ + __I uint32_t TAMPTIME; /*!< [0x0130] RTC Tamper Time Register */ + __I uint32_t TAMPCAL; /*!< [0x0134] RTC Tamper Calendar Register */ + __I uint32_t RESERVE6[2]; /* 0x138 ~ 0x13c */ + __IO uint32_t CLKDCTL; /*!< [0x0140] RTC Clock Fail Detector Control Register */ + __IO uint32_t CDBR; /*!< [0x0144] RTC Clock Frequency Detector Boundary Register */ + +} RTC_T; + +/** + @addtogroup RTC_CONST RTC Bit Field Definition + Constant Definitions for RTC Controller + @{ +*/ + +#define RTC_INIT_ACTIVE_Pos (0) /*!< RTC_T::INIT: ACTIVE Position */ +#define RTC_INIT_ACTIVE_Msk (0x1ul << RTC_INIT_ACTIVE_Pos) /*!< RTC_T::INIT: ACTIVE Mask */ + +#define RTC_INIT_INIT_Pos (1) /*!< RTC_T::INIT: INIT Position */ +#define RTC_INIT_INIT_Msk (0x7ffffffful << RTC_INIT_INIT_Pos) /*!< RTC_T::INIT: INIT Mask */ + +#define RTC_FREQADJ_FRACTION_Pos (0) /*!< RTC_T::FREQADJ: FRACTION Position */ +#define RTC_FREQADJ_FRACTION_Msk (0x3ful << RTC_FREQADJ_FRACTION_Pos) /*!< RTC_T::FREQADJ: FRACTION Mask */ + +#define RTC_FREQADJ_INTEGER_Pos (8) /*!< RTC_T::FREQADJ: INTEGER Position */ +#define RTC_FREQADJ_INTEGER_Msk (0x1ful << RTC_FREQADJ_INTEGER_Pos) /*!< RTC_T::FREQADJ: INTEGER Mask */ + +#define RTC_FREQADJ_FCRBUSY_Pos (31) /*!< RTC_T::FREQADJ: FCRBUSY Position */ +#define RTC_FREQADJ_FCRBUSY_Msk (0x1ul << RTC_FREQADJ_FCRBUSY_Pos) /*!< RTC_T::FREQADJ: FCRBUSY Mask */ + +#define RTC_TIME_SEC_Pos (0) /*!< RTC_T::TIME: SEC Position */ +#define RTC_TIME_SEC_Msk (0xful << RTC_TIME_SEC_Pos) /*!< RTC_T::TIME: SEC Mask */ + +#define RTC_TIME_TENSEC_Pos (4) /*!< RTC_T::TIME: TENSEC Position */ +#define RTC_TIME_TENSEC_Msk (0x7ul << RTC_TIME_TENSEC_Pos) /*!< RTC_T::TIME: TENSEC Mask */ + +#define RTC_TIME_MIN_Pos (8) /*!< RTC_T::TIME: MIN Position */ +#define RTC_TIME_MIN_Msk (0xful << RTC_TIME_MIN_Pos) /*!< RTC_T::TIME: MIN Mask */ + +#define RTC_TIME_TENMIN_Pos (12) /*!< RTC_T::TIME: TENMIN Position */ +#define RTC_TIME_TENMIN_Msk (0x7ul << RTC_TIME_TENMIN_Pos) /*!< RTC_T::TIME: TENMIN Mask */ + +#define RTC_TIME_HR_Pos (16) /*!< RTC_T::TIME: HR Position */ +#define RTC_TIME_HR_Msk (0xful << RTC_TIME_HR_Pos) /*!< RTC_T::TIME: HR Mask */ + +#define RTC_TIME_TENHR_Pos (20) /*!< RTC_T::TIME: TENHR Position */ +#define RTC_TIME_TENHR_Msk (0x3ul << RTC_TIME_TENHR_Pos) /*!< RTC_T::TIME: TENHR Mask */ + +#define RTC_CAL_DAY_Pos (0) /*!< RTC_T::CAL: DAY Position */ +#define RTC_CAL_DAY_Msk (0xful << RTC_CAL_DAY_Pos) /*!< RTC_T::CAL: DAY Mask */ + +#define RTC_CAL_TENDAY_Pos (4) /*!< RTC_T::CAL: TENDAY Position */ +#define RTC_CAL_TENDAY_Msk (0x3ul << RTC_CAL_TENDAY_Pos) /*!< RTC_T::CAL: TENDAY Mask */ + +#define RTC_CAL_MON_Pos (8) /*!< RTC_T::CAL: MON Position */ +#define RTC_CAL_MON_Msk (0xful << RTC_CAL_MON_Pos) /*!< RTC_T::CAL: MON Mask */ + +#define RTC_CAL_TENMON_Pos (12) /*!< RTC_T::CAL: TENMON Position */ +#define RTC_CAL_TENMON_Msk (0x1ul << RTC_CAL_TENMON_Pos) /*!< RTC_T::CAL: TENMON Mask */ + +#define RTC_CAL_YEAR_Pos (16) /*!< RTC_T::CAL: YEAR Position */ +#define RTC_CAL_YEAR_Msk (0xful << RTC_CAL_YEAR_Pos) /*!< RTC_T::CAL: YEAR Mask */ + +#define RTC_CAL_TENYEAR_Pos (20) /*!< RTC_T::CAL: TENYEAR Position */ +#define RTC_CAL_TENYEAR_Msk (0xful << RTC_CAL_TENYEAR_Pos) /*!< RTC_T::CAL: TENYEAR Mask */ + +#define RTC_CLKFMT_24HEN_Pos (0) /*!< RTC_T::CLKFMT: 24HEN Position */ +#define RTC_CLKFMT_24HEN_Msk (0x1ul << RTC_CLKFMT_24HEN_Pos) /*!< RTC_T::CLKFMT: 24HEN Mask */ + +#define RTC_CLKFMT_DCOMPEN_Pos (16) /*!< RTC_T::CLKFMT: DCOMPEN Position */ +#define RTC_CLKFMT_DCOMPEN_Msk (0x1ul << RTC_CLKFMT_DCOMPEN_Pos) /*!< RTC_T::CLKFMT: DCOMPEN Mask */ + +#define RTC_WEEKDAY_WEEKDAY_Pos (0) /*!< RTC_T::WEEKDAY: WEEKDAY Position */ +#define RTC_WEEKDAY_WEEKDAY_Msk (0x7ul << RTC_WEEKDAY_WEEKDAY_Pos) /*!< RTC_T::WEEKDAY: WEEKDAY Mask */ + +#define RTC_TALM_SEC_Pos (0) /*!< RTC_T::TALM: SEC Position */ +#define RTC_TALM_SEC_Msk (0xful << RTC_TALM_SEC_Pos) /*!< RTC_T::TALM: SEC Mask */ + +#define RTC_TALM_TENSEC_Pos (4) /*!< RTC_T::TALM: TENSEC Position */ +#define RTC_TALM_TENSEC_Msk (0x7ul << RTC_TALM_TENSEC_Pos) /*!< RTC_T::TALM: TENSEC Mask */ + +#define RTC_TALM_MIN_Pos (8) /*!< RTC_T::TALM: MIN Position */ +#define RTC_TALM_MIN_Msk (0xful << RTC_TALM_MIN_Pos) /*!< RTC_T::TALM: MIN Mask */ + +#define RTC_TALM_TENMIN_Pos (12) /*!< RTC_T::TALM: TENMIN Position */ +#define RTC_TALM_TENMIN_Msk (0x7ul << RTC_TALM_TENMIN_Pos) /*!< RTC_T::TALM: TENMIN Mask */ + +#define RTC_TALM_HR_Pos (16) /*!< RTC_T::TALM: HR Position */ +#define RTC_TALM_HR_Msk (0xful << RTC_TALM_HR_Pos) /*!< RTC_T::TALM: HR Mask */ + +#define RTC_TALM_TENHR_Pos (20) /*!< RTC_T::TALM: TENHR Position */ +#define RTC_TALM_TENHR_Msk (0x3ul << RTC_TALM_TENHR_Pos) /*!< RTC_T::TALM: TENHR Mask */ + +#define RTC_CALM_DAY_Pos (0) /*!< RTC_T::CALM: DAY Position */ +#define RTC_CALM_DAY_Msk (0xful << RTC_CALM_DAY_Pos) /*!< RTC_T::CALM: DAY Mask */ + +#define RTC_CALM_TENDAY_Pos (4) /*!< RTC_T::CALM: TENDAY Position */ +#define RTC_CALM_TENDAY_Msk (0x3ul << RTC_CALM_TENDAY_Pos) /*!< RTC_T::CALM: TENDAY Mask */ + +#define RTC_CALM_MON_Pos (8) /*!< RTC_T::CALM: MON Position */ +#define RTC_CALM_MON_Msk (0xful << RTC_CALM_MON_Pos) /*!< RTC_T::CALM: MON Mask */ + +#define RTC_CALM_TENMON_Pos (12) /*!< RTC_T::CALM: TENMON Position */ +#define RTC_CALM_TENMON_Msk (0x1ul << RTC_CALM_TENMON_Pos) /*!< RTC_T::CALM: TENMON Mask */ + +#define RTC_CALM_YEAR_Pos (16) /*!< RTC_T::CALM: YEAR Position */ +#define RTC_CALM_YEAR_Msk (0xful << RTC_CALM_YEAR_Pos) /*!< RTC_T::CALM: YEAR Mask */ + +#define RTC_CALM_TENYEAR_Pos (20) /*!< RTC_T::CALM: TENYEAR Position */ +#define RTC_CALM_TENYEAR_Msk (0xful << RTC_CALM_TENYEAR_Pos) /*!< RTC_T::CALM: TENYEAR Mask */ + +#define RTC_LEAPYEAR_LEAPYEAR_Pos (0) /*!< RTC_T::LEAPYEAR: LEAPYEAR Position */ +#define RTC_LEAPYEAR_LEAPYEAR_Msk (0x1ul << RTC_LEAPYEAR_LEAPYEAR_Pos) /*!< RTC_T::LEAPYEAR: LEAPYEAR Mask */ + +#define RTC_INTEN_ALMIEN_Pos (0) /*!< RTC_T::INTEN: ALMIEN Position */ +#define RTC_INTEN_ALMIEN_Msk (0x1ul << RTC_INTEN_ALMIEN_Pos) /*!< RTC_T::INTEN: ALMIEN Mask */ + +#define RTC_INTEN_TICKIEN_Pos (1) /*!< RTC_T::INTEN: TICKIEN Position */ +#define RTC_INTEN_TICKIEN_Msk (0x1ul << RTC_INTEN_TICKIEN_Pos) /*!< RTC_T::INTEN: TICKIEN Mask */ + +#define RTC_INTEN_TAMP0IEN_Pos (8) /*!< RTC_T::INTEN: TAMP0IEN Position */ +#define RTC_INTEN_TAMP0IEN_Msk (0x1ul << RTC_INTEN_TAMP0IEN_Pos) /*!< RTC_T::INTEN: TAMP0IEN Mask */ + +#define RTC_INTEN_TAMP1IEN_Pos (9) /*!< RTC_T::INTEN: TAMP1IEN Position */ +#define RTC_INTEN_TAMP1IEN_Msk (0x1ul << RTC_INTEN_TAMP1IEN_Pos) /*!< RTC_T::INTEN: TAMP1IEN Mask */ + +#define RTC_INTEN_TAMP2IEN_Pos (10) /*!< RTC_T::INTEN: TAMP2IEN Position */ +#define RTC_INTEN_TAMP2IEN_Msk (0x1ul << RTC_INTEN_TAMP2IEN_Pos) /*!< RTC_T::INTEN: TAMP2IEN Mask */ + +#define RTC_INTEN_TAMP3IEN_Pos (11) /*!< RTC_T::INTEN: TAMP3IEN Position */ +#define RTC_INTEN_TAMP3IEN_Msk (0x1ul << RTC_INTEN_TAMP3IEN_Pos) /*!< RTC_T::INTEN: TAMP3IEN Mask */ + +#define RTC_INTEN_TAMP4IEN_Pos (12) /*!< RTC_T::INTEN: TAMP4IEN Position */ +#define RTC_INTEN_TAMP4IEN_Msk (0x1ul << RTC_INTEN_TAMP4IEN_Pos) /*!< RTC_T::INTEN: TAMP4IEN Mask */ + +#define RTC_INTEN_TAMP5IEN_Pos (13) /*!< RTC_T::INTEN: TAMP5IEN Position */ +#define RTC_INTEN_TAMP5IEN_Msk (0x1ul << RTC_INTEN_TAMP5IEN_Pos) /*!< RTC_T::INTEN: TAMP5IEN Mask */ + +#define RTC_INTEN_CLKFIEN_Pos (24) /*!< RTC_T::INTEN: CLKFIEN Position */ +#define RTC_INTEN_CLKFIEN_Msk (0x1ul << RTC_INTEN_CLKFIEN_Pos) /*!< RTC_T::INTEN: CLKFIEN Mask */ + +#define RTC_INTEN_CLKSTIEN_Pos (25) /*!< RTC_T::INTEN: CLKSTIEN Position */ +#define RTC_INTEN_CLKSTIEN_Msk (0x1ul << RTC_INTEN_CLKSTIEN_Pos) /*!< RTC_T::INTEN: CLKSTIEN Mask */ + +#define RTC_INTSTS_ALMIF_Pos (0) /*!< RTC_T::INTSTS: ALMIF Position */ +#define RTC_INTSTS_ALMIF_Msk (0x1ul << RTC_INTSTS_ALMIF_Pos) /*!< RTC_T::INTSTS: ALMIF Mask */ + +#define RTC_INTSTS_TICKIF_Pos (1) /*!< RTC_T::INTSTS: TICKIF Position */ +#define RTC_INTSTS_TICKIF_Msk (0x1ul << RTC_INTSTS_TICKIF_Pos) /*!< RTC_T::INTSTS: TICKIF Mask */ + +#define RTC_INTSTS_TAMP0IF_Pos (8) /*!< RTC_T::INTSTS: TAMP0IF Position */ +#define RTC_INTSTS_TAMP0IF_Msk (0x1ul << RTC_INTSTS_TAMP0IF_Pos) /*!< RTC_T::INTSTS: TAMP0IF Mask */ + +#define RTC_INTSTS_TAMP1IF_Pos (9) /*!< RTC_T::INTSTS: TAMP1IF Position */ +#define RTC_INTSTS_TAMP1IF_Msk (0x1ul << RTC_INTSTS_TAMP1IF_Pos) /*!< RTC_T::INTSTS: TAMP1IF Mask */ + +#define RTC_INTSTS_TAMP2IF_Pos (10) /*!< RTC_T::INTSTS: TAMP2IF Position */ +#define RTC_INTSTS_TAMP2IF_Msk (0x1ul << RTC_INTSTS_TAMP2IF_Pos) /*!< RTC_T::INTSTS: TAMP2IF Mask */ + +#define RTC_INTSTS_TAMP3IF_Pos (11) /*!< RTC_T::INTSTS: TAMP3IF Position */ +#define RTC_INTSTS_TAMP3IF_Msk (0x1ul << RTC_INTSTS_TAMP3IF_Pos) /*!< RTC_T::INTSTS: TAMP3IF Mask */ + +#define RTC_INTSTS_TAMP4IF_Pos (12) /*!< RTC_T::INTSTS: TAMP4IF Position */ +#define RTC_INTSTS_TAMP4IF_Msk (0x1ul << RTC_INTSTS_TAMP4IF_Pos) /*!< RTC_T::INTSTS: TAMP4IF Mask */ + +#define RTC_INTSTS_TAMP5IF_Pos (13) /*!< RTC_T::INTSTS: TAMP5IF Position */ +#define RTC_INTSTS_TAMP5IF_Msk (0x1ul << RTC_INTSTS_TAMP5IF_Pos) /*!< RTC_T::INTSTS: TAMP5IF Mask */ + +#define RTC_INTSTS_CLKFIF_Pos (24) /*!< RTC_T::INTSTS: CLKFIF Position */ +#define RTC_INTSTS_CLKFIF_Msk (0x1ul << RTC_INTSTS_CLKFIF_Pos) /*!< RTC_T::INTSTS: CLKFIF Mask */ + +#define RTC_INTSTS_CLKSTIF_Pos (25) /*!< RTC_T::INTSTS: CLKSTIF Position */ +#define RTC_INTSTS_CLKSTIF_Msk (0x1ul << RTC_INTSTS_CLKSTIF_Pos) /*!< RTC_T::INTSTS: CLKSTIF Mask */ + +#define RTC_TICK_TICK_Pos (0) /*!< RTC_T::TICK: TICK Position */ +#define RTC_TICK_TICK_Msk (0x7ul << RTC_TICK_TICK_Pos) /*!< RTC_T::TICK: TICK Mask */ + +#define RTC_TAMSK_MSEC_Pos (0) /*!< RTC_T::TAMSK: MSEC Position */ +#define RTC_TAMSK_MSEC_Msk (0x1ul << RTC_TAMSK_MSEC_Pos) /*!< RTC_T::TAMSK: MSEC Mask */ + +#define RTC_TAMSK_MTENSEC_Pos (1) /*!< RTC_T::TAMSK: MTENSEC Position */ +#define RTC_TAMSK_MTENSEC_Msk (0x1ul << RTC_TAMSK_MTENSEC_Pos) /*!< RTC_T::TAMSK: MTENSEC Mask */ + +#define RTC_TAMSK_MMIN_Pos (2) /*!< RTC_T::TAMSK: MMIN Position */ +#define RTC_TAMSK_MMIN_Msk (0x1ul << RTC_TAMSK_MMIN_Pos) /*!< RTC_T::TAMSK: MMIN Mask */ + +#define RTC_TAMSK_MTENMIN_Pos (3) /*!< RTC_T::TAMSK: MTENMIN Position */ +#define RTC_TAMSK_MTENMIN_Msk (0x1ul << RTC_TAMSK_MTENMIN_Pos) /*!< RTC_T::TAMSK: MTENMIN Mask */ + +#define RTC_TAMSK_MHR_Pos (4) /*!< RTC_T::TAMSK: MHR Position */ +#define RTC_TAMSK_MHR_Msk (0x1ul << RTC_TAMSK_MHR_Pos) /*!< RTC_T::TAMSK: MHR Mask */ + +#define RTC_TAMSK_MTENHR_Pos (5) /*!< RTC_T::TAMSK: MTENHR Position */ +#define RTC_TAMSK_MTENHR_Msk (0x1ul << RTC_TAMSK_MTENHR_Pos) /*!< RTC_T::TAMSK: MTENHR Mask */ + +#define RTC_CAMSK_MDAY_Pos (0) /*!< RTC_T::CAMSK: MDAY Position */ +#define RTC_CAMSK_MDAY_Msk (0x1ul << RTC_CAMSK_MDAY_Pos) /*!< RTC_T::CAMSK: MDAY Mask */ + +#define RTC_CAMSK_MTENDAY_Pos (1) /*!< RTC_T::CAMSK: MTENDAY Position */ +#define RTC_CAMSK_MTENDAY_Msk (0x1ul << RTC_CAMSK_MTENDAY_Pos) /*!< RTC_T::CAMSK: MTENDAY Mask */ + +#define RTC_CAMSK_MMON_Pos (2) /*!< RTC_T::CAMSK: MMON Position */ +#define RTC_CAMSK_MMON_Msk (0x1ul << RTC_CAMSK_MMON_Pos) /*!< RTC_T::CAMSK: MMON Mask */ + +#define RTC_CAMSK_MTENMON_Pos (3) /*!< RTC_T::CAMSK: MTENMON Position */ +#define RTC_CAMSK_MTENMON_Msk (0x1ul << RTC_CAMSK_MTENMON_Pos) /*!< RTC_T::CAMSK: MTENMON Mask */ + +#define RTC_CAMSK_MYEAR_Pos (4) /*!< RTC_T::CAMSK: MYEAR Position */ +#define RTC_CAMSK_MYEAR_Msk (0x1ul << RTC_CAMSK_MYEAR_Pos) /*!< RTC_T::CAMSK: MYEAR Mask */ + +#define RTC_CAMSK_MTENYEAR_Pos (5) /*!< RTC_T::CAMSK: MTENYEAR Position */ +#define RTC_CAMSK_MTENYEAR_Msk (0x1ul << RTC_CAMSK_MTENYEAR_Pos) /*!< RTC_T::CAMSK: MTENYEAR Mask */ + +#define RTC_SPRCTL_SPRRWEN_Pos (2) /*!< RTC_T::SPRCTL: SPRRWEN Position */ +#define RTC_SPRCTL_SPRRWEN_Msk (0x1ul << RTC_SPRCTL_SPRRWEN_Pos) /*!< RTC_T::SPRCTL: SPRRWEN Mask */ + +#define RTC_SPRCTL_SPRCSTS_Pos (5) /*!< RTC_T::SPRCTL: SPRCSTS Position */ +#define RTC_SPRCTL_SPRCSTS_Msk (0x1ul << RTC_SPRCTL_SPRCSTS_Pos) /*!< RTC_T::SPRCTL: SPRCSTS Mask */ + +#define RTC_SPRCTL_LXTFCLR_Pos (16) /*!< RTC_T::SPRCTL: LXTFCLR Position */ +#define RTC_SPRCTL_LXTFCLR_Msk (0x1ul << RTC_SPRCTL_LXTFCLR_Pos) /*!< RTC_T::SPRCTL: LXTFCLR Mask */ + +#define RTC_SPR0_SPARE_Pos (0) /*!< RTC_T::SPR0: SPARE Position */ +#define RTC_SPR0_SPARE_Msk (0xfffffffful << RTC_SPR0_SPARE_Pos) /*!< RTC_T::SPR0: SPARE Mask */ + +#define RTC_SPR1_SPARE_Pos (0) /*!< RTC_T::SPR1: SPARE Position */ +#define RTC_SPR1_SPARE_Msk (0xfffffffful << RTC_SPR1_SPARE_Pos) /*!< RTC_T::SPR1: SPARE Mask */ + +#define RTC_SPR2_SPARE_Pos (0) /*!< RTC_T::SPR2: SPARE Position */ +#define RTC_SPR2_SPARE_Msk (0xfffffffful << RTC_SPR2_SPARE_Pos) /*!< RTC_T::SPR2: SPARE Mask */ + +#define RTC_SPR3_SPARE_Pos (0) /*!< RTC_T::SPR3: SPARE Position */ +#define RTC_SPR3_SPARE_Msk (0xfffffffful << RTC_SPR3_SPARE_Pos) /*!< RTC_T::SPR3: SPARE Mask */ + +#define RTC_SPR4_SPARE_Pos (0) /*!< RTC_T::SPR4: SPARE Position */ +#define RTC_SPR4_SPARE_Msk (0xfffffffful << RTC_SPR4_SPARE_Pos) /*!< RTC_T::SPR4: SPARE Mask */ + +#define RTC_SPR5_SPARE_Pos (0) /*!< RTC_T::SPR5: SPARE Position */ +#define RTC_SPR5_SPARE_Msk (0xfffffffful << RTC_SPR5_SPARE_Pos) /*!< RTC_T::SPR5: SPARE Mask */ + +#define RTC_SPR6_SPARE_Pos (0) /*!< RTC_T::SPR6: SPARE Position */ +#define RTC_SPR6_SPARE_Msk (0xfffffffful << RTC_SPR6_SPARE_Pos) /*!< RTC_T::SPR6: SPARE Mask */ + +#define RTC_SPR7_SPARE_Pos (0) /*!< RTC_T::SPR7: SPARE Position */ +#define RTC_SPR7_SPARE_Msk (0xfffffffful << RTC_SPR7_SPARE_Pos) /*!< RTC_T::SPR7: SPARE Mask */ + +#define RTC_SPR8_SPARE_Pos (0) /*!< RTC_T::SPR8: SPARE Position */ +#define RTC_SPR8_SPARE_Msk (0xfffffffful << RTC_SPR8_SPARE_Pos) /*!< RTC_T::SPR8: SPARE Mask */ + +#define RTC_SPR9_SPARE_Pos (0) /*!< RTC_T::SPR9: SPARE Position */ +#define RTC_SPR9_SPARE_Msk (0xfffffffful << RTC_SPR9_SPARE_Pos) /*!< RTC_T::SPR9: SPARE Mask */ + +#define RTC_SPR10_SPARE_Pos (0) /*!< RTC_T::SPR10: SPARE Position */ +#define RTC_SPR10_SPARE_Msk (0xfffffffful << RTC_SPR10_SPARE_Pos) /*!< RTC_T::SPR10: SPARE Mask */ + +#define RTC_SPR11_SPARE_Pos (0) /*!< RTC_T::SPR11: SPARE Position */ +#define RTC_SPR11_SPARE_Msk (0xfffffffful << RTC_SPR11_SPARE_Pos) /*!< RTC_T::SPR11: SPARE Mask */ + +#define RTC_SPR12_SPARE_Pos (0) /*!< RTC_T::SPR12: SPARE Position */ +#define RTC_SPR12_SPARE_Msk (0xfffffffful << RTC_SPR12_SPARE_Pos) /*!< RTC_T::SPR12: SPARE Mask */ + +#define RTC_SPR13_SPARE_Pos (0) /*!< RTC_T::SPR13: SPARE Position */ +#define RTC_SPR13_SPARE_Msk (0xfffffffful << RTC_SPR13_SPARE_Pos) /*!< RTC_T::SPR13: SPARE Mask */ + +#define RTC_SPR14_SPARE_Pos (0) /*!< RTC_T::SPR14: SPARE Position */ +#define RTC_SPR14_SPARE_Msk (0xfffffffful << RTC_SPR14_SPARE_Pos) /*!< RTC_T::SPR14: SPARE Mask */ + +#define RTC_SPR15_SPARE_Pos (0) /*!< RTC_T::SPR15: SPARE Position */ +#define RTC_SPR15_SPARE_Msk (0xfffffffful << RTC_SPR15_SPARE_Pos) /*!< RTC_T::SPR15: SPARE Mask */ + +#define RTC_SPR16_SPARE_Pos (0) /*!< RTC_T::SPR16: SPARE Position */ +#define RTC_SPR16_SPARE_Msk (0xfffffffful << RTC_SPR16_SPARE_Pos) /*!< RTC_T::SPR16: SPARE Mask */ + +#define RTC_SPR17_SPARE_Pos (0) /*!< RTC_T::SPR17: SPARE Position */ +#define RTC_SPR17_SPARE_Msk (0xfffffffful << RTC_SPR17_SPARE_Pos) /*!< RTC_T::SPR17: SPARE Mask */ + +#define RTC_SPR18_SPARE_Pos (0) /*!< RTC_T::SPR18: SPARE Position */ +#define RTC_SPR18_SPARE_Msk (0xfffffffful << RTC_SPR18_SPARE_Pos) /*!< RTC_T::SPR18: SPARE Mask */ + +#define RTC_SPR19_SPARE_Pos (0) /*!< RTC_T::SPR19: SPARE Position */ +#define RTC_SPR19_SPARE_Msk (0xfffffffful << RTC_SPR19_SPARE_Pos) /*!< RTC_T::SPR19: SPARE Mask */ + +#define RTC_LXTCTL_LIRC32KEN_Pos (0) /*!< RTC_T::LXTCTL: LIRC32KEN Position */ +#define RTC_LXTCTL_LIRC32KEN_Msk (0x1ul << RTC_LXTCTL_LIRC32KEN_Pos) /*!< RTC_T::LXTCTL: LIRC32KEN Mask */ + +#define RTC_LXTCTL_GAIN_Pos (1) /*!< RTC_T::LXTCTL: GAIN Position */ +#define RTC_LXTCTL_GAIN_Msk (0x7ul << RTC_LXTCTL_GAIN_Pos) /*!< RTC_T::LXTCTL: GAIN Mask */ + +#define RTC_LXTCTL_C32KSEL_Pos (6) /*!< RTC_T::LXTCTL: C32KSEL Position */ +#define RTC_LXTCTL_C32KSEL_Msk (0x1ul << RTC_LXTCTL_C32KSEL_Pos) /*!< RTC_T::LXTCTL: C32KSEL Mask */ + +#define RTC_LXTCTL_RTCCKSEL_Pos (7) /*!< RTC_T::LXTCTL: RTCCKSEL Position */ +#define RTC_LXTCTL_RTCCKSEL_Msk (0x1ul << RTC_LXTCTL_RTCCKSEL_Pos) /*!< RTC_T::LXTCTL: RTCCKSEL Mask */ + +#define RTC_LXTCTL_IOCTLSEL_Pos (8) /*!< RTC_T::LXTCTL: IOCTLSEL Position */ +#define RTC_LXTCTL_IOCTLSEL_Msk (0x1ul << RTC_LXTCTL_IOCTLSEL_Pos) /*!< RTC_T::LXTCTL: IOCTLSEL Mask */ + +#define RTC_GPIOCTL0_OPMODE0_Pos (0) /*!< RTC_T::GPIOCTL0: OPMODE0 Position */ +#define RTC_GPIOCTL0_OPMODE0_Msk (0x3ul << RTC_GPIOCTL0_OPMODE0_Pos) /*!< RTC_T::GPIOCTL0: OPMODE0 Mask */ + +#define RTC_GPIOCTL0_DOUT0_Pos (2) /*!< RTC_T::GPIOCTL0: DOUT0 Position */ +#define RTC_GPIOCTL0_DOUT0_Msk (0x1ul << RTC_GPIOCTL0_DOUT0_Pos) /*!< RTC_T::GPIOCTL0: DOUT0 Mask */ + +#define RTC_GPIOCTL0_DINOFF0_Pos (3) /*!< RTC_T::GPIOCTL0: DINOFF0 Position */ +#define RTC_GPIOCTL0_DINOFF0_Msk (0x1ul << RTC_GPIOCTL0_DINOFF0_Pos) /*!< RTC_T::GPIOCTL0: DINOFF0 Mask */ + +#define RTC_GPIOCTL0_PUSEL0_Pos (4) /*!< RTC_T::GPIOCTL0: PUSEL0 Position */ +#define RTC_GPIOCTL0_PUSEL0_Msk (0x3ul << RTC_GPIOCTL0_PUSEL0_Pos) /*!< RTC_T::GPIOCTL0: PUSEL0 Mask */ + +#define RTC_GPIOCTL0_OPMODE1_Pos (8) /*!< RTC_T::GPIOCTL0: OPMODE1 Position */ +#define RTC_GPIOCTL0_OPMODE1_Msk (0x3ul << RTC_GPIOCTL0_OPMODE1_Pos) /*!< RTC_T::GPIOCTL0: OPMODE1 Mask */ + +#define RTC_GPIOCTL0_DOUT1_Pos (10) /*!< RTC_T::GPIOCTL0: DOUT1 Position */ +#define RTC_GPIOCTL0_DOUT1_Msk (0x1ul << RTC_GPIOCTL0_DOUT1_Pos) /*!< RTC_T::GPIOCTL0: DOUT1 Mask */ + +#define RTC_GPIOCTL0_DINOFF1_Pos (11) /*!< RTC_T::GPIOCTL0: DINOFF1 Position */ +#define RTC_GPIOCTL0_DINOFF1_Msk (0x1ul << RTC_GPIOCTL0_DINOFF1_Pos) /*!< RTC_T::GPIOCTL0: DINOFF1 Mask */ + +#define RTC_GPIOCTL0_PUSEL1_Pos (12) /*!< RTC_T::GPIOCTL0: PUSEL1 Position */ +#define RTC_GPIOCTL0_PUSEL1_Msk (0x3ul << RTC_GPIOCTL0_PUSEL1_Pos) /*!< RTC_T::GPIOCTL0: PUSEL1 Mask */ + +#define RTC_GPIOCTL0_OPMODE2_Pos (16) /*!< RTC_T::GPIOCTL0: OPMODE2 Position */ +#define RTC_GPIOCTL0_OPMODE2_Msk (0x3ul << RTC_GPIOCTL0_OPMODE2_Pos) /*!< RTC_T::GPIOCTL0: OPMODE2 Mask */ + +#define RTC_GPIOCTL0_DOUT2_Pos (18) /*!< RTC_T::GPIOCTL0: DOUT2 Position */ +#define RTC_GPIOCTL0_DOUT2_Msk (0x1ul << RTC_GPIOCTL0_DOUT2_Pos) /*!< RTC_T::GPIOCTL0: DOUT2 Mask */ + +#define RTC_GPIOCTL0_DINOFF2_Pos (19) /*!< RTC_T::GPIOCTL0: DINOFF2 Position */ +#define RTC_GPIOCTL0_DINOFF2_Msk (0x1ul << RTC_GPIOCTL0_DINOFF2_Pos) /*!< RTC_T::GPIOCTL0: DINOFF2 Mask */ + +#define RTC_GPIOCTL0_PUSEL2_Pos (20) /*!< RTC_T::GPIOCTL0: PUSEL2 Position */ +#define RTC_GPIOCTL0_PUSEL2_Msk (0x3ul << RTC_GPIOCTL0_PUSEL2_Pos) /*!< RTC_T::GPIOCTL0: PUSEL2 Mask */ + +#define RTC_GPIOCTL0_OPMODE3_Pos (24) /*!< RTC_T::GPIOCTL0: OPMODE3 Position */ +#define RTC_GPIOCTL0_OPMODE3_Msk (0x3ul << RTC_GPIOCTL0_OPMODE3_Pos) /*!< RTC_T::GPIOCTL0: OPMODE3 Mask */ + +#define RTC_GPIOCTL0_DOUT3_Pos (26) /*!< RTC_T::GPIOCTL0: DOUT3 Position */ +#define RTC_GPIOCTL0_DOUT3_Msk (0x1ul << RTC_GPIOCTL0_DOUT3_Pos) /*!< RTC_T::GPIOCTL0: DOUT3 Mask */ + +#define RTC_GPIOCTL0_DINOFF3_Pos (27) /*!< RTC_T::GPIOCTL0: DINOFF3 Position */ +#define RTC_GPIOCTL0_DINOFF3_Msk (0x1ul << RTC_GPIOCTL0_DINOFF3_Pos) /*!< RTC_T::GPIOCTL0: DINOFF3 Mask */ + +#define RTC_GPIOCTL0_PUSEL3_Pos (28) /*!< RTC_T::GPIOCTL0: PUSEL3 Position */ +#define RTC_GPIOCTL0_PUSEL3_Msk (0x3ul << RTC_GPIOCTL0_PUSEL3_Pos) /*!< RTC_T::GPIOCTL0: PUSEL3 Mask */ + +#define RTC_GPIOCTL1_OPMODE4_Pos (0) /*!< RTC_T::GPIOCTL1: OPMODE4 Position */ +#define RTC_GPIOCTL1_OPMODE4_Msk (0x3ul << RTC_GPIOCTL1_OPMODE4_Pos) /*!< RTC_T::GPIOCTL1: OPMODE4 Mask */ + +#define RTC_GPIOCTL1_DOUT4_Pos (2) /*!< RTC_T::GPIOCTL1: DOUT4 Position */ +#define RTC_GPIOCTL1_DOUT4_Msk (0x1ul << RTC_GPIOCTL1_DOUT4_Pos) /*!< RTC_T::GPIOCTL1: DOUT4 Mask */ + +#define RTC_GPIOCTL0_DINOFF4_Pos (3) /*!< RTC_T::GPIOCTL1: DINOFF4 Position */ +#define RTC_GPIOCTL0_DINOFF4_Msk (0x1ul << RTC_GPIOCTL0_DINOFF4_Pos) /*!< RTC_T::GPIOCTL1: DINOFF4 Mask */ + +#define RTC_GPIOCTL1_PUSEL4_Pos (4) /*!< RTC_T::GPIOCTL1: PUSEL4 Position */ +#define RTC_GPIOCTL1_PUSEL4_Msk (0x3ul << RTC_GPIOCTL1_PUSEL4_Pos) /*!< RTC_T::GPIOCTL1: PUSEL4 Mask */ + +#define RTC_GPIOCTL1_OPMODE5_Pos (8) /*!< RTC_T::GPIOCTL1: OPMODE5 Position */ +#define RTC_GPIOCTL1_OPMODE5_Msk (0x3ul << RTC_GPIOCTL1_OPMODE5_Pos) /*!< RTC_T::GPIOCTL1: OPMODE5 Mask */ + +#define RTC_GPIOCTL1_DOUT5_Pos (10) /*!< RTC_T::GPIOCTL1: DOUT5 Position */ +#define RTC_GPIOCTL1_DOUT5_Msk (0x1ul << RTC_GPIOCTL1_DOUT5_Pos) /*!< RTC_T::GPIOCTL1: DOUT5 Mask */ + +#define RTC_GPIOCTL0_DINOFF5_Pos (11) /*!< RTC_T::GPIOCTL1: DINOFF5 Position */ +#define RTC_GPIOCTL0_DINOFF5_Msk (0x1ul << RTC_GPIOCTL0_DINOFF5_Pos) /*!< RTC_T::GPIOCTL1: DINOFF5 Mask */ + +#define RTC_GPIOCTL1_PUSEL5_Pos (12) /*!< RTC_T::GPIOCTL1: PUSEL5 Position */ +#define RTC_GPIOCTL1_PUSEL5_Msk (0x3ul << RTC_GPIOCTL1_PUSEL5_Pos) /*!< RTC_T::GPIOCTL1: PUSEL5 Mask */ + +#define RTC_GPIOCTL1_OPMODE6_Pos (16) /*!< RTC_T::GPIOCTL1: OPMODE6 Position */ +#define RTC_GPIOCTL1_OPMODE6_Msk (0x3ul << RTC_GPIOCTL1_OPMODE6_Pos) /*!< RTC_T::GPIOCTL1: OPMODE6 Mask */ + +#define RTC_GPIOCTL1_DOUT6_Pos (18) /*!< RTC_T::GPIOCTL1: DOUT6 Position */ +#define RTC_GPIOCTL1_DOUT6_Msk (0x1ul << RTC_GPIOCTL1_DOUT6_Pos) /*!< RTC_T::GPIOCTL1: DOUT6 Mask */ + +#define RTC_GPIOCTL0_DINOFF6_Pos (19) /*!< RTC_T::GPIOCTL1: DINOFF6 Position */ +#define RTC_GPIOCTL0_DINOFF6_Msk (0x1ul << RTC_GPIOCTL0_DINOFF6_Pos) /*!< RTC_T::GPIOCTL1: DINOFF6 Mask */ + +#define RTC_GPIOCTL1_PUSEL6_Pos (20) /*!< RTC_T::GPIOCTL1: PUSEL6 Position */ +#define RTC_GPIOCTL1_PUSEL6_Msk (0x3ul << RTC_GPIOCTL1_PUSEL6_Pos) /*!< RTC_T::GPIOCTL1: PUSEL6 Mask */ + +#define RTC_GPIOCTL1_OPMODE7_Pos (24) /*!< RTC_T::GPIOCTL1: OPMODE7 Position */ +#define RTC_GPIOCTL1_OPMODE7_Msk (0x3ul << RTC_GPIOCTL1_OPMODE7_Pos) /*!< RTC_T::GPIOCTL1: OPMODE7 Mask */ + +#define RTC_GPIOCTL1_DOUT7_Pos (26) /*!< RTC_T::GPIOCTL1: DOUT7 Position */ +#define RTC_GPIOCTL1_DOUT7_Msk (0x1ul << RTC_GPIOCTL1_DOUT7_Pos) /*!< RTC_T::GPIOCTL1: DOUT7 Mask */ + +#define RTC_GPIOCTL0_DINOFF7_Pos (27) /*!< RTC_T::GPIOCTL1: DINOFF7 Position */ +#define RTC_GPIOCTL0_DINOFF7_Msk (0x1ul << RTC_GPIOCTL0_DINOFF7_Pos) /*!< RTC_T::GPIOCTL1: DINOFF7 Mask */ + +#define RTC_GPIOCTL1_PUSEL7_Pos (28) /*!< RTC_T::GPIOCTL1: PUSEL7 Position */ +#define RTC_GPIOCTL1_PUSEL7_Msk (0x3ul << RTC_GPIOCTL1_PUSEL7_Pos) /*!< RTC_T::GPIOCTL1: PUSEL7 Mask */ + +#define RTC_DSTCTL_ADDHR_Pos (0) /*!< RTC_T::DSTCTL: ADDHR Position */ +#define RTC_DSTCTL_ADDHR_Msk (0x1ul << RTC_DSTCTL_ADDHR_Pos) /*!< RTC_T::DSTCTL: ADDHR Mask */ + +#define RTC_DSTCTL_SUBHR_Pos (1) /*!< RTC_T::DSTCTL: SUBHR Position */ +#define RTC_DSTCTL_SUBHR_Msk (0x1ul << RTC_DSTCTL_SUBHR_Pos) /*!< RTC_T::DSTCTL: SUBHR Mask */ + +#define RTC_DSTCTL_DSBAK_Pos (2) /*!< RTC_T::DSTCTL: DSBAK Position */ +#define RTC_DSTCTL_DSBAK_Msk (0x1ul << RTC_DSTCTL_DSBAK_Pos) /*!< RTC_T::DSTCTL: DSBAK Mask */ + +#define RTC_TAMPCTL_DYN1ISS_Pos (0) /*!< RTC_T::TAMPCTL: DYN1ISS Position */ +#define RTC_TAMPCTL_DYN1ISS_Msk (0x1ul << RTC_TAMPCTL_DYN1ISS_Pos) /*!< RTC_T::TAMPCTL: DYN1ISS Mask */ + +#define RTC_TAMPCTL_DYN2ISS_Pos (1) /*!< RTC_T::TAMPCTL: DYN2ISS Position */ +#define RTC_TAMPCTL_DYN2ISS_Msk (0x1ul << RTC_TAMPCTL_DYN2ISS_Pos) /*!< RTC_T::TAMPCTL: DYN2ISS Mask */ + +#define RTC_TAMPCTL_DYNSRC_Pos (3) /*!< RTC_T::TAMPCTL: DYNSRC Position */ +#define RTC_TAMPCTL_DYNSRC_Msk (0x1ul << RTC_TAMPCTL_DYNSRC_Pos) /*!< RTC_T::TAMPCTL: DYNSRC Mask */ + +#define RTC_TAMPCTL_SEEDRLD_Pos (4) /*!< RTC_T::TAMPCTL: SEEDRLD Position */ +#define RTC_TAMPCTL_SEEDRLD_Msk (0x1ul << RTC_TAMPCTL_SEEDRLD_Pos) /*!< RTC_T::TAMPCTL: SEEDRLD Mask */ + +#define RTC_TAMPCTL_DYNRATE_Pos (5) /*!< RTC_T::TAMPCTL: DYNRATE Position */ +#define RTC_TAMPCTL_DYNRATE_Msk (0x7ul << RTC_TAMPCTL_DYNRATE_Pos) /*!< RTC_T::TAMPCTL: DYNRATE Mask */ + +#define RTC_TAMPCTL_TAMP0EN_Pos (8) /*!< RTC_T::TAMPCTL: TAMP0EN Position */ +#define RTC_TAMPCTL_TAMP0EN_Msk (0x1ul << RTC_TAMPCTL_TAMP0EN_Pos) /*!< RTC_T::TAMPCTL: TAMP0EN Mask */ + +#define RTC_TAMPCTL_TAMP0LV_Pos (9) /*!< RTC_T::TAMPCTL: TAMP0LV Position */ +#define RTC_TAMPCTL_TAMP0LV_Msk (0x1ul << RTC_TAMPCTL_TAMP0LV_Pos) /*!< RTC_T::TAMPCTL: TAMP0LV Mask */ + +#define RTC_TAMPCTL_TAMP0DBEN_Pos (10) /*!< RTC_T::TAMPCTL: TAMP0DBEN Position */ +#define RTC_TAMPCTL_TAMP0DBEN_Msk (0x1ul << RTC_TAMPCTL_TAMP0DBEN_Pos) /*!< RTC_T::TAMPCTL: TAMP0DBEN Mask */ + +#define RTC_TAMPCTL_TAMP1EN_Pos (12) /*!< RTC_T::TAMPCTL: TAMP1EN Position */ +#define RTC_TAMPCTL_TAMP1EN_Msk (0x1ul << RTC_TAMPCTL_TAMP1EN_Pos) /*!< RTC_T::TAMPCTL: TAMP1EN Mask */ + +#define RTC_TAMPCTL_TAMP1LV_Pos (13) /*!< RTC_T::TAMPCTL: TAMP1LV Position */ +#define RTC_TAMPCTL_TAMP1LV_Msk (0x1ul << RTC_TAMPCTL_TAMP1LV_Pos) /*!< RTC_T::TAMPCTL: TAMP1LV Mask */ + +#define RTC_TAMPCTL_TAMP1DBEN_Pos (14) /*!< RTC_T::TAMPCTL: TAMP1DBEN Position */ +#define RTC_TAMPCTL_TAMP1DBEN_Msk (0x1ul << RTC_TAMPCTL_TAMP1DBEN_Pos) /*!< RTC_T::TAMPCTL: TAMP1DBEN Mask */ + +#define RTC_TAMPCTL_DYNPR0EN_Pos (15) /*!< RTC_T::TAMPCTL: DYNPR0EN Position */ +#define RTC_TAMPCTL_DYNPR0EN_Msk (0x1ul << RTC_TAMPCTL_DYNPR0EN_Pos) /*!< RTC_T::TAMPCTL: DYNPR0EN Mask */ + +#define RTC_TAMPCTL_TAMP2EN_Pos (16) /*!< RTC_T::TAMPCTL: TAMP2EN Position */ +#define RTC_TAMPCTL_TAMP2EN_Msk (0x1ul << RTC_TAMPCTL_TAMP2EN_Pos) /*!< RTC_T::TAMPCTL: TAMP2EN Mask */ + +#define RTC_TAMPCTL_TAMP2LV_Pos (17) /*!< RTC_T::TAMPCTL: TAMP2LV Position */ +#define RTC_TAMPCTL_TAMP2LV_Msk (0x1ul << RTC_TAMPCTL_TAMP2LV_Pos) /*!< RTC_T::TAMPCTL: TAMP2LV Mask */ + +#define RTC_TAMPCTL_TAMP2DBEN_Pos (18) /*!< RTC_T::TAMPCTL: TAMP2DBEN Position */ +#define RTC_TAMPCTL_TAMP2DBEN_Msk (0x1ul << RTC_TAMPCTL_TAMP2DBEN_Pos) /*!< RTC_T::TAMPCTL: TAMP2DBEN Mask */ + +#define RTC_TAMPCTL_TAMP3EN_Pos (20) /*!< RTC_T::TAMPCTL: TAMP3EN Position */ +#define RTC_TAMPCTL_TAMP3EN_Msk (0x1ul << RTC_TAMPCTL_TAMP3EN_Pos) /*!< RTC_T::TAMPCTL: TAMP3EN Mask */ + +#define RTC_TAMPCTL_TAMP3LV_Pos (21) /*!< RTC_T::TAMPCTL: TAMP3LV Position */ +#define RTC_TAMPCTL_TAMP3LV_Msk (0x1ul << RTC_TAMPCTL_TAMP3LV_Pos) /*!< RTC_T::TAMPCTL: TAMP3LV Mask */ + +#define RTC_TAMPCTL_TAMP3DBEN_Pos (22) /*!< RTC_T::TAMPCTL: TAMP3DBEN Position */ +#define RTC_TAMPCTL_TAMP3DBEN_Msk (0x1ul << RTC_TAMPCTL_TAMP3DBEN_Pos) /*!< RTC_T::TAMPCTL: TAMP3DBEN Mask */ + +#define RTC_TAMPCTL_DYNPR1EN_Pos (23) /*!< RTC_T::TAMPCTL: DYNPR1EN Position */ +#define RTC_TAMPCTL_DYNPR1EN_Msk (0x1ul << RTC_TAMPCTL_DYNPR1EN_Pos) /*!< RTC_T::TAMPCTL: DYNPR1EN Mask */ + +#define RTC_TAMPCTL_TAMP4EN_Pos (24) /*!< RTC_T::TAMPCTL: TAMP4EN Position */ +#define RTC_TAMPCTL_TAMP4EN_Msk (0x1ul << RTC_TAMPCTL_TAMP4EN_Pos) /*!< RTC_T::TAMPCTL: TAMP4EN Mask */ + +#define RTC_TAMPCTL_TAMP4LV_Pos (25) /*!< RTC_T::TAMPCTL: TAMP4LV Position */ +#define RTC_TAMPCTL_TAMP4LV_Msk (0x1ul << RTC_TAMPCTL_TAMP4LV_Pos) /*!< RTC_T::TAMPCTL: TAMP4LV Mask */ + +#define RTC_TAMPCTL_TAMP4DBEN_Pos (26) /*!< RTC_T::TAMPCTL: TAMP4DBEN Position */ +#define RTC_TAMPCTL_TAMP4DBEN_Msk (0x1ul << RTC_TAMPCTL_TAMP4DBEN_Pos) /*!< RTC_T::TAMPCTL: TAMP4DBEN Mask */ + +#define RTC_TAMPCTL_TAMP5EN_Pos (28) /*!< RTC_T::TAMPCTL: TAMP5EN Position */ +#define RTC_TAMPCTL_TAMP5EN_Msk (0x1ul << RTC_TAMPCTL_TAMP5EN_Pos) /*!< RTC_T::TAMPCTL: TAMP5EN Mask */ + +#define RTC_TAMPCTL_TAMP5LV_Pos (29) /*!< RTC_T::TAMPCTL: TAMP5LV Position */ +#define RTC_TAMPCTL_TAMP5LV_Msk (0x1ul << RTC_TAMPCTL_TAMP5LV_Pos) /*!< RTC_T::TAMPCTL: TAMP5LV Mask */ + +#define RTC_TAMPCTL_TAMP5DBEN_Pos (30) /*!< RTC_T::TAMPCTL: TAMP5DBEN Position */ +#define RTC_TAMPCTL_TAMP5DBEN_Msk (0x1ul << RTC_TAMPCTL_TAMP5DBEN_Pos) /*!< RTC_T::TAMPCTL: TAMP5DBEN Mask */ + +#define RTC_TAMPCTL_DYNPR2EN_Pos (31) /*!< RTC_T::TAMPCTL: DYNPR2EN Position */ +#define RTC_TAMPCTL_DYNPR2EN_Msk (0x1ul << RTC_TAMPCTL_DYNPR2EN_Pos) /*!< RTC_T::TAMPCTL: DYNPR2EN Mask */ + +#define RTC_TAMPSEED_SEED_Pos (0) /*!< RTC_T::TAMPSEED: SEED Position */ +#define RTC_TAMPSEED_SEED_Msk (0xfffffffful << RTC_TAMPSEED_SEED_Pos) /*!< RTC_T::TAMPSEED: SEED Mask */ + +#define RTC_TAMPTIME_SEC_Pos (0) /*!< RTC_T::TAMPTIME: SEC Position */ +#define RTC_TAMPTIME_SEC_Msk (0xful << RTC_TAMPTIME_SEC_Pos) /*!< RTC_T::TAMPTIME: SEC Mask */ + +#define RTC_TAMPTIME_TENSEC_Pos (4) /*!< RTC_T::TAMPTIME: TENSEC Position */ +#define RTC_TAMPTIME_TENSEC_Msk (0x7ul << RTC_TAMPTIME_TENSEC_Pos) /*!< RTC_T::TAMPTIME: TENSEC Mask */ + +#define RTC_TAMPTIME_MIN_Pos (8) /*!< RTC_T::TAMPTIME: MIN Position */ +#define RTC_TAMPTIME_MIN_Msk (0xful << RTC_TAMPTIME_MIN_Pos) /*!< RTC_T::TAMPTIME: MIN Mask */ + +#define RTC_TAMPTIME_TENMIN_Pos (12) /*!< RTC_T::TAMPTIME: TENMIN Position */ +#define RTC_TAMPTIME_TENMIN_Msk (0x7ul << RTC_TAMPTIME_TENMIN_Pos) /*!< RTC_T::TAMPTIME: TENMIN Mask */ + +#define RTC_TAMPTIME_HR_Pos (16) /*!< RTC_T::TAMPTIME: HR Position */ +#define RTC_TAMPTIME_HR_Msk (0xful << RTC_TAMPTIME_HR_Pos) /*!< RTC_T::TAMPTIME: HR Mask */ + +#define RTC_TAMPTIME_TENHR_Pos (20) /*!< RTC_T::TAMPTIME: TENHR Position */ +#define RTC_TAMPTIME_TENHR_Msk (0x3ul << RTC_TAMPTIME_TENHR_Pos) /*!< RTC_T::TAMPTIME: TENHR Mask */ + +#define RTC_TAMPCAL_DAY_Pos (0) /*!< RTC_T::TAMPCAL: DAY Position */ +#define RTC_TAMPCAL_DAY_Msk (0xful << RTC_TAMPCAL_DAY_Pos) /*!< RTC_T::TAMPCAL: DAY Mask */ + +#define RTC_TAMPCAL_TENDAY_Pos (4) /*!< RTC_T::TAMPCAL: TENDAY Position */ +#define RTC_TAMPCAL_TENDAY_Msk (0x3ul << RTC_TAMPCAL_TENDAY_Pos) /*!< RTC_T::TAMPCAL: TENDAY Mask */ + +#define RTC_TAMPCAL_MON_Pos (8) /*!< RTC_T::TAMPCAL: MON Position */ +#define RTC_TAMPCAL_MON_Msk (0xful << RTC_TAMPCAL_MON_Pos) /*!< RTC_T::TAMPCAL: MON Mask */ + +#define RTC_TAMPCAL_TENMON_Pos (12) /*!< RTC_T::TAMPCAL: TENMON Position */ +#define RTC_TAMPCAL_TENMON_Msk (0x1ul << RTC_TAMPCAL_TENMON_Pos) /*!< RTC_T::TAMPCAL: TENMON Mask */ + +#define RTC_TAMPCAL_YEAR_Pos (16) /*!< RTC_T::TAMPCAL: YEAR Position */ +#define RTC_TAMPCAL_YEAR_Msk (0xful << RTC_TAMPCAL_YEAR_Pos) /*!< RTC_T::TAMPCAL: YEAR Mask */ + +#define RTC_TAMPCAL_TENYEAR_Pos (20) /*!< RTC_T::TAMPCAL: TENYEAR Position */ +#define RTC_TAMPCAL_TENYEAR_Msk (0xful << RTC_TAMPCAL_TENYEAR_Pos) /*!< RTC_T::TAMPCAL: TENYEAR Mask */ + +#define RTC_CLKDCTL_LXTFDEN_Pos (0) /*!< RTC_T::CLKDCTL: LXTFDEN Position */ +#define RTC_CLKDCTL_LXTFDEN_Msk (0x1ul << RTC_CLKDCTL_LXTFDEN_Pos) /*!< RTC_T::CLKDCTL: LXTFDEN Mask */ + +#define RTC_CLKDCTL_LXTFSW_Pos (1) /*!< RTC_T::CLKDCTL: LXTFSW Position */ +#define RTC_CLKDCTL_LXTFSW_Msk (0x1ul << RTC_CLKDCTL_LXTFSW_Pos) /*!< RTC_T::CLKDCTL: LXTFSW Mask */ + +#define RTC_CLKDCTL_LXTSTSW_Pos (2) /*!< RTC_T::CLKDCTL: LXTSTSW Position */ +#define RTC_CLKDCTL_LXTSTSW_Msk (0x1ul << RTC_CLKDCTL_LXTSTSW_Pos) /*!< RTC_T::CLKDCTL: LXTSTSW Mask */ + +#define RTC_CLKDCTL_SWLIRCF_Pos (16) /*!< RTC_T::CLKDCTL: SWLIRCF Position */ +#define RTC_CLKDCTL_SWLIRCF_Msk (0x1ul << RTC_CLKDCTL_SWLIRCF_Pos) /*!< RTC_T::CLKDCTL: SWLIRCF Mask */ + +#define RTC_CLKDCTL_LXTSLOWF_Pos (17) /*!< RTC_T::CLKDCTL: LXTSLOWF Position */ +#define RTC_CLKDCTL_LXTSLOWF_Msk (0x1ul << RTC_CLKDCTL_LXTSLOWF_Pos) /*!< RTC_T::CLKDCTL: LXTSLOWF Mask */ + +#define RTC_CDBR_STOPBD_Pos (0) /*!< RTC_T::CDBR: STOPBD Position */ +#define RTC_CDBR_STOPBD_Msk (0xfful << RTC_CDBR_STOPBD_Pos) /*!< RTC_T::CDBR: STOPBD Mask */ + +#define RTC_CDBR_FAILBD_Pos (16) /*!< RTC_T::CDBR: FAILBD Position */ +#define RTC_CDBR_FAILBD_Msk (0xfful << RTC_CDBR_FAILBD_Pos) /*!< RTC_T::CDBR: FAILBD Mask */ + +/**@}*/ /* RTC_CONST */ +/**@}*/ /* end of RTC register group */ +/**@}*/ /* end of REGISTER group */ + +#endif /* __RTC_REG_H__ */ diff --git a/Ubiquitous/XiZi/board/nuvoton-m2354/third_party_driver/include/Regs/sc_reg.h b/Ubiquitous/XiZi/board/nuvoton-m2354/third_party_driver/include/Regs/sc_reg.h new file mode 100644 index 0000000..4b69e96 --- /dev/null +++ b/Ubiquitous/XiZi/board/nuvoton-m2354/third_party_driver/include/Regs/sc_reg.h @@ -0,0 +1,980 @@ +/**************************************************************************//** + * @file sc_reg.h + * @version V1.00 + * @brief SC register definition header file + * + * @copyright SPDX-License-Identifier: Apache-2.0 + * @copyright Copyright (C) 2020 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ +#ifndef __SC_REG_H__ +#define __SC_REG_H__ + +/** @addtogroup REGISTER Control Register + + @{ + +*/ + +/*---------------------- Smart Card Host Interface Controller -------------------------*/ +/** + @addtogroup SC Smart Card Host Interface Controller(SC) + Memory Mapped Structure for SC Controller + @{ +*/ + +typedef struct +{ + + + /** + * @var SC_T::DAT + * Offset: 0x00 SC Receive/Transmit Holding Buffer Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[7:0] |DAT |Receive/Transmit Holding Buffer + * | | |Write Operation: + * | | |By writing data to DAT, the SC will send out an 8-bit data. + * | | |Note: If SCEN (SCn_CTL[0]) is not enabled, DAT cannot be programmed. + * | | |Read Operation: + * | | |By reading DAT, the SC will return an 8-bit received data. + * @var SC_T::CTL + * Offset: 0x04 SC Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |SCEN |SC Controller Enable Bit + * | | |Set this bit to 1 to enable SC operation. + * | | |0 = SC will force all transition to IDLE state. + * | | |1 = SC controller is enabled and all function can work correctly. + * | | |Note1: SCEN must be set to 1 before filling in other SC registers, or smart card will not work properly. + * |[1] |RXOFF |RX Transition Disable Control Bit + * | | |This bit is used for disable Rx transition function. + * | | |0 = The receiver Enabled. + * | | |1 = The receiver Disabled. + * | | |Note1: If AUTOCEN (SCn_CTL[3]) is enabled, this field is ignored. + * |[2] |TXOFF |TX Transition Disable Control Bit + * | | |This bit is used for disable Tx transition function. + * | | |0 = The transceiver Enabled. + * | | |1 = The transceiver Disabled. + * |[3] |AUTOCEN |Auto Convention Enable Bit + * | | |This bit is used for enable auto convention function. + * | | |0 = Auto-convention Disabled. + * | | |1 = Auto-convention Enabled. + * | | |If user enables auto convention function, the setting step must be done before Answer to Reset (ATR) state and the first data must be 0x3B or 0x3F + * | | |After hardware received first data and stored it at buffer, hardware will decided the convention and change the CONSEL (SCn_CTL[5:4]) bits automatically when received first data is 0x3B or 0x3F + * | | |If received first byte is 0x3B, TS is direct convention, CONSEL (SCn_CTL[5:4]) will be set to 00 automatically, otherwise the TS is inverse convention, and CONSEL (SCn_CTL[5:4]) will be set to 11. + * | | |If the first data is not 0x3B or 0x3F, hardware will set ACERRIF (SCn_INTSTS[10]) and generate an interrupt to CPU when ACERRIEN (SCn_INTEN[10]) is enabled. + * |[5:4] |CONSEL |Convention Selection + * | | |00 = Direct convention. + * | | |01 = Reserved. + * | | |10 = Reserved. + * | | |11 = Inverse convention. + * | | |Note: If AUTOCEN (SCn_CTL[3]) is enabled, this field is ignored. + * |[7:6] |RXTRGLV |Rx Buffer Trigger Level + * | | |When the number of bytes in the receiving buffer equals the RXTRGLV, the RDAIF will be set + * | | |If RDAIEN (SCn_INTEN[0]) is enabled, an interrupt will be generated to CPU. + * | | |00 = Rx Buffer Trigger Level with 01 bytes. + * | | |01 = Rx Buffer Trigger Level with 02 bytes. + * | | |10 = Rx Buffer Trigger Level with 03 bytes. + * | | |11 = Reserved. + * |[12:8] |BGT |Block Guard Time (BGT) + * | | |Block guard time means the minimum interval between the leading edges of two consecutive characters between different transfer directions + * | | |This field indicates the counter for the bit length of block guard time + * | | |According to ISO 7816-3, in T = 0 mode, user must fill 15 (real block guard time = 16.5) to this field; in T = 1 mode, user must fill 21 (real block guard time = 22.5) to it. + * | | |Note: The real block guard time is BGT + 1. + * |[14:13] |TMRSEL |Timer Channel Selection + * | | |00 = All internal timer function Disabled. + * | | |. + * | | |11 = Internal 24 bit timer and two 8 bit timers Enabled + * | | |User can configure them by setting SCn_TMRCTL0[23:0], SCn_TMRCTL1[7:0] and SCn_TMRCTL2[7:0]. + * | | |Other configurations are reserve + * |[15] |NSB |Stop Bit Length + * | | |This field indicates the length of stop bit. + * | | |0 = The stop bit length is 2 ETU.(for ISO 7816-3 T=0 mode). + * | | |1= The stop bit length is 1 ETU.(for ISO 7816-3 T=1 mode). + * | | |Note1: The default stop bit length is 2. SC and UART adopts NSB to program the stop bit length. + * | | |Note2: In UART mode, RX can receive the data sequence in 1 stop bit or 2 stop bits with NSB is set to 0. + * |[18:16] |RXRTY |RX Error Retry Count Number + * | | |This field indicates the maximum number of receiver retries that are allowed when parity error has occurred + * | | |Note1: The real retry number is RXRTY + 1, so 8 is the maximum retry number. + * | | |Note2: This field cannot be changed when RXRTYEN enabled + * | | |The change flow is to disable RXRTYEN first and then fill in new retry value. + * |[19] |RXRTYEN |RX Error Retry Enable Bit + * | | |This bit enables receiver retry function when parity error has occurred. + * | | |0 = RX error retry function Disabled. + * | | |1 = RX error retry function Enabled. + * | | |Note: User must fill in the RXRTY value before enabling this bit. + * |[22:20] |TXRTY |TX Error Retry Count Number + * | | |This field indicates the maximum number of transmitter retries that are allowed when parity error has occurred. + * | | |Note1: The real retry number is TXRTY + 1, so 8 is the maximum retry number. + * | | |Note2: This field cannot be changed when TXRTYEN enabled + * | | |The change flow is to disable TXRTYEN first and then fill in new retry value. + * |[23] |TXRTYEN |TX Error Retry Enable Bit + * | | |This bit enables transmitter retry function when parity error has occurred. + * | | |0 = TX error retry function Disabled. + * | | |1 = TX error retry function Enabled. + * |[25:24] |CDDBSEL |Card Detect De-bounce Selection + * | | |This field indicates the card detect de-bounce selection. + * | | |00 = De-bounce sample card insert once per 384 (128 * 3) SC module clocks and de-bounce sample card removal once per 128 SC module clocks. + * | | |Other configurations are reserved. + * |[26] |CDLV |Card Detect Level Selection + * | | |0 = When hardware detects the card detect pin (SCn_CD) from high to low, it indicates a card is detected. + * | | |1 = When hardware detects the card detect pin (SCn_CD) from low to high, it indicates a card is detected. + * | | |Note: User must select card detect level before Smart Card controller enabled. + * |[30] |SYNC |SYNC Flag Indicator (Read Only) + * | | |Due to synchronization, user should check this bit before writing a new value to RXRTY and TXRTY fields. + * | | |0 = Synchronizing is completion, user can write new data to RXRTY and TXRTY. + * | | |1 = Last value is synchronizing. + * @var SC_T::ALTCTL + * Offset: 0x08 SC Alternate Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |TXRST |TX Software Reset + * | | |When TXRST is set, all the bytes in the transmit buffer and TX internal state machine will be cleared. + * | | |0 = No effect. + * | | |1 = Reset the TX internal state machine and pointers. + * | | |Note: This bit will be auto cleared after reset is complete. + * |[1] |RXRST |Rx Software Reset + * | | |When RXRST is set, all the bytes in the receive buffer and Rx internal state machine will be cleared. + * | | |0 = No effect. + * | | |1 = Reset the Rx internal state machine and pointers. + * | | |Note: This bit will be auto cleared after reset is complete. + * |[2] |DACTEN |Deactivation Sequence Generator Enable Bit + * | | |This bit enables SC controller to initiate the card by deactivation sequence. + * | | |0 = No effect. + * | | |1 = Deactivation sequence generator Enabled. + * | | |Note1: When the deactivation sequence completed, this bit will be cleared automatically and the INITIF (SCn_INTSTS[8]) will be set to 1. + * | | |Note2: This field will be cleared by TXRST (SCn_ALTCTL[0]) and RXRST (SCn_ALTCTL[1]) + * | | |Thus, do not fill in this bit DACTEN, TXRST and RXRST at the same time. + * | | |Note3: If SCEN (SCn_CTL[0]) is not enabled, this filed cannot be programmed. + * |[3] |ACTEN |Activation Sequence Generator Enable Bit + * | | |This bit enables SC controller to initiate the card by activation sequence. + * | | |0 = No effect. + * | | |1 = Activation sequence generator Enabled. + * | | |Note1: When the activation sequence completed, this bit will be cleared automatically and the INITIF (SCn_INTSTS[8]) will be set to 1. + * | | |Note2: This field will be cleared by TXRST (SCn_ALTCTL[0]) and RXRST (SCn_ALTCTL[1]) + * | | |Thus, do not fill in this bit ACTEN, TXRST and RXRST at the same time. + * | | |Note3: If SCEN (SCn_CTL[0]) is not enabled, this filed cannot be programmed. + * | | |Note4: During the activation sequence, RX is disabled automatically and can not receive data + * | | |After the activation sequence completion, RXOFF (SCn_CTL[1]) keeps the state before hardware activation. + * |[4] |WARSTEN |Warm Reset Sequence Generator Enable Bit + * | | |This bit enables SC controller to initiate the card by warm reset sequence. + * | | |0 = No effect. + * | | |1 = Warm reset sequence generator Enabled. + * | | |Note1: When the warm reset sequence completed, this bit will be cleared automatically and the INITIF (SCn_INTSTS[8]) will be set to 1. + * | | |Note2: This field will be cleared by TXRST (SCn_ALTCTL[0]) and RXRST (SCn_ALTCTL[1]) + * | | |Thus, do not fill in this bit WARSTEN, TXRST and RXRST at the same time. + * | | |Note3: If SCEN (SCn_CTL[0]) is not enabled, this filed cannot be programmed. + * | | |Note4: During the warm reset sequence, RX is disabled automatically and can not receive data + * | | |After the warm reset sequence completion, RXOFF (SCn_CTL[1]) keeps the state before perform warm reset sequence. + * |[5] |CNTEN0 |Internal Timer0 Start Enable Bit + * | | |This bit enables Timer 0 to start counting + * | | |User can fill 0 to stop it and set 1 to reload and count + * | | |The counter unit is ETU base. + * | | |0 = Stops counting. + * | | |1 = Start counting. + * | | |Note1: This field is used for internal 24 bit timer when TMRSEL (SCn_CTL[14:13]) is 11 only. + * | | |Note2: If the operation mode is not in auto-reload mode (SCn_TMRCTL0[26] = 0), this bit will be auto-cleared by hardware. + * | | |Note3: If SCEN (SCn_CTL[0]) is not enabled, this filed cannot be programmed + * |[6] |CNTEN1 |Internal Timer1 Start Enable Bit + * | | |This bit enables Timer 1 to start counting + * | | |User can fill 0 to stop it and set 1 to reload and count + * | | |The counter unit is ETU base. + * | | |0 = Stops counting. + * | | |1 = Start counting. + * | | |Note1: This field is used for internal 8 bit timer when TMRSEL(SCn_CTL[14:13]) is 11 only + * | | |Do not fill CNTEN1 when TMRSEL (SCn_CTL[14:13]) is not equal to 11. + * | | |Note2: If the operation mode is not in auto-reload mode (SCn_TMRCTL1[26] = 0), this bit will be auto-cleared by hardware. + * | | |Note3: If SCEN (SCn_CTL[0]) is not enabled, this filed cannot be programmed. + * |[7] |CNTEN2 |Internal Timer2 Start Enable Bit + * | | |This bit enables Timer 2 to start counting + * | | |User can fill 0 to stop it and set 1 to reload and count + * | | |The counter unit is ETU base. + * | | |0 = Stops counting. + * | | |1 = Start counting. + * | | |Note1: This field is used for internal 8 bit timer when TMRSEL (SCn_CTL[14:13]) is 11 only + * | | |Do not fill in CNTEN2 when TMRSEL (SCn_CTL[14:13]) is not equal to 11. + * | | |Note2: If the operation mode is not in auto-reload mode (SCn_TMRCTL2[26] = 0), this bit will be auto-cleared by hardware. + * | | |Note3: If SCEN (SCn_CTL[0]) is not enabled, this filed cannot be programmed. + * |[9:8] |INITSEL |Initial Timing Selection + * | | |This fields indicates the initial timing of hardware activation, warm-reset or deactivation. + * | | |The unit of initial timing is SC module clock. + * | | |Activation: refer to SC Activation Sequence in Figure 6.17-4 SC Activation Sequence. + * | | |Warm-reset: refer to Warm-Reset Sequence in Figure 6.17-5 SC Warm Reset Sequence. + * | | |Deactivation: refer to Deactivation Sequence in Figure 6.17-6 SC Deactivation Sequence. + * | | |Note: When set activation and warm reset in Timer0 operation mode 0011, it may have deviation at most 128 SC module clock cycles. + * |[11] |ADACEN |Auto Deactivation When Card Removal + * | | |This bit is used for enable hardware auto deactivation when smart card is removed. + * | | |0 = Auto deactivation Disabled. + * | | |1 = Auto deactivation Enabled. + * | | |Note: When the card is removed, hardware will stop any process and then do deactivation sequence if this bit is set + * | | |If auto deactivation process completes, hardware will set INITIF (SCn_INTSTS[8]) also. + * |[12] |RXBGTEN |Receiver Block Guard Time Function Enable Bit + * | | |This bit enables the receiver block guard time function. + * | | |0 = Receiver block guard time function Disabled. + * | | |1 = Receiver block guard time function Enabled. + * |[13] |ACTSTS0 |Internal Timer0 Active Status (Read Only) + * | | |This bit indicates the timer counter status of timer0. + * | | |0 = Timer0 is not active. + * | | |1 = Timer0 is active. + * | | |Note: Timer0 is active does not always mean timer0 is counting the CNT (SCn_TMRCTL0[23:0]). + * |[14] |ACTSTS1 |Internal Timer1 Active Status (Read Only) + * | | |This bit indicates the timer counter status of timer1. + * | | |0 = Timer1 is not active. + * | | |1 = Timer1 is active. + * | | |Note: Timer1 is active does not always mean timer1 is counting the CNT (SCn_TMRCTL1[7:0]). + * |[15] |ACTSTS2 |Internal Timer2 Active Status (Read Only) + * | | |This bit indicates the timer counter status of timer2. + * | | |0 = Timer2 is not active. + * | | |1 = Timer2 is active. + * | | |Note: Timer2 is active does not always mean timer2 is counting the CNT (SCn_TMRCTL2[7:0]). + * |[31] |SYNC |SYNC Flag Indicator (Read Only) + * | | |Due to synchronization, user should check this bit when writing a new value to SCn_ALTCTL register. + * | | |0 = Synchronizing is completion, user can write new data to SCn_ALTCTL register. + * | | |1 = Last value is synchronizing. + * @var SC_T::EGT + * Offset: 0x0C SC Extra Guard Time Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[7:0] |EGT |Extra Guard Time + * | | |This field indicates the extra guard time value. + * | | |Note: The extra guard time unit is ETU base. + * @var SC_T::RXTOUT + * Offset: 0x10 SC Receive Buffer Time-out Counter Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[8:0] |RFTM |SC Receiver FIFO Time-out Counter + * | | |The time-out down counter resets and starts counting whenever the RX buffer received a new data + * | | |Once the counter decrease to 1 and no new data is received or CPU does not read data by reading SCn_DAT, a receiver time-out flag RXTOIF (SCn_INTSTS[9]) will be set, and hardware will generate an interrupt to CPU when RXTOIEN (SCn_INTEN[9]) is enabled. + * | | |Note1: The counter unit is ETU based and the interval of time-out is RFTM + 0.5. + * | | |Note2: Filling in all 0 to this field indicates to disable this function. + * @var SC_T::ETUCTL + * Offset: 0x14 SC Element Time Unit Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[11:0] |ETURDIV |ETU Rate Divider + * | | |The field is used for ETU clock rate divider. + * | | |The real ETU is ETURDIV + 1. + * | | |Note: User can configure this field, but this field must be greater than 0x04. + * @var SC_T::INTEN + * Offset: 0x18 SC Interrupt Enable Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |RDAIEN |Receive Data Reach Interrupt Enable Bit + * | | |This field is used to enable received data reaching trigger level RXTRGLV (SCn_CTL[7:6]) interrupt. + * | | |0 = Receive data reach trigger level interrupt Disabled. + * | | |1 = Receive data reach trigger level interrupt Enabled. + * |[1] |TBEIEN |Transmit Buffer Empty Interrupt Enable Bit + * | | |This field is used to enable transmit buffer empty interrupt. + * | | |0 = Transmit buffer empty interrupt Disabled. + * | | |1 = Transmit buffer empty interrupt Enabled. + * |[2] |TERRIEN |Transfer Error Interrupt Enable Bit + * | | |This field is used to enable transfer error interrupt + * | | |The transfer error states is at SCn_STATUS register which includes receiver break error BEF (SCn_STATUS[6]), frame error FEF (SCn_STATUS[5]), parity error PEF (SCn_STATUS[4]), receive buffer overflow error RXOV (SCn_STATUS[0]), transmit buffer overflow error TXOV (SCn_STATUS[8]), receiver retry over limit error RXOVERR (SCn_STATUS[22]) and transmitter retry over limit error TXOVERR (SCn_STATUS[30]). + * | | |0 = Transfer error interrupt Disabled. + * | | |1 = Transfer error interrupt Enabled. + * |[3] |TMR0IEN |Timer0 Interrupt Enable Bit + * | | |This field is used to enable Timer0 interrupt function. + * | | |0 = Timer0 interrupt Disabled. + * | | |1 = Timer0 interrupt Enabled. + * |[4] |TMR1IEN |Timer1 Interrupt Enable Bit + * | | |This field is used to enable the Timer1 interrupt function. + * | | |0 = Timer1 interrupt Disabled. + * | | |1 = Timer1 interrupt Enabled. + * |[5] |TMR2IEN |Timer2 Interrupt Enable Bit + * | | |This field is used to enable Timer2 interrupt function. + * | | |0 = Timer2 interrupt Disabled. + * | | |1 = Timer2 interrupt Enabled. + * |[6] |BGTIEN |Block Guard Time Interrupt Enable Bit + * | | |This field is used to enable block guard time interrupt in receive direction. + * | | |0 = Block guard time interrupt Disabled. + * | | |1 = Block guard time interrupt Enabled. + * | | |Note: This bit is valid only for receive receive direction block guard time. + * |[7] |CDIEN |Card Detect Interrupt Enable Bit + * | | |This field is used to enable card detect interrupt + * | | |The card detect status is CDPINSTS (SCn_STATUS[13]). + * | | |0 = Card detect interrupt Disabled. + * | | |1 = Card detect interrupt Enabled. + * |[8] |INITIEN |Initial End Interrupt Enable Bit + * | | |This field is used to enable activation (ACTEN (SCn_ALTCTL[3] = 1)), deactivation (DACTEN (SCn_ALTCTL[2] = 1)) and warm reset (WARSTEN (SCn_ALTCTL [4])) sequence complete interrupt. + * | | |0 = Initial end interrupt Disabled. + * | | |1 = Initial end interrupt Enabled. + * |[9] |RXTOIEN |Receiver Buffer Time-out Interrupt Enable Bit + * | | |This field is used to enable receiver buffer time-out interrupt. + * | | |0 = Receiver buffer time-out interrupt Disabled. + * | | |1 = Receiver buffer time-out interrupt Enabled. + * |[10] |ACERRIEN |Auto Convention Error Interrupt Enable Bit + * | | |This field is used to enable auto-convention error interrupt. + * | | |0 = Auto-convention error interrupt Disabled. + * | | |1 = Auto-convention error interrupt Enabled. + * @var SC_T::INTSTS + * Offset: 0x1C SC Interrupt Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |RDAIF |Receive Data Reach Interrupt Status Flag (Read Only) + * | | |This field is used for received data reaching trigger level RXTRGLV (SCn_CTL[7:6]) interrupt status flag. + * | | |0 = Number of receive buffer is less than RXTRGLV setting. + * | | |1 = Number of receive buffer data equals the RXTRGLV setting. + * | | |Note: This bit is read only + * | | |If user reads data from SCn_DAT and receiver buffer data byte number is less than RXTRGLV, this bit will be cleared automatically. + * |[1] |TBEIF |Transmit Buffer Empty Interrupt Status Flag (Read Only) + * | | |This field is used for transmit buffer empty interrupt status flag. + * | | |0 = Transmit buffer is not empty. + * | | |1 = Transmit buffer is empty. + * | | |Note: This bit is read only + * | | |If user wants to clear this bit, user must write data to DAT (SCn_DAT[7:0]) and then this bit will be cleared automatically. + * |[2] |TERRIF |Transfer Error Interrupt Status Flag + * | | |This field is used for transfer error interrupt status flag + * | | |The transfer error states is at SCn_STATUS register which includes receiver break error BEF (SCn_STATUS[6]), frame error FEF (SCn_STATUS[5], parity error PEF (SCn_STATUS[4] and receive buffer overflow error RXOV (SCn_STATUS[0]), transmit buffer overflow error TXOV (SCn_STATUS[8]), receiver retry over limit error RXOVERR (SCn_STATUS[22] or transmitter retry over limit error TXOVERR (SCn_STATUS[30]). + * | | |0 = Transfer error interrupt did not occur. + * | | |1 = Transfer error interrupt occurred. + * | | |Note1: This field is the status flag of BEF, FEF, PEF, RXOV, TXOV, RXOVERR or TXOVERR. + * | | |Note2: This bit can be cleared by writing 1 to it. + * |[3] |TMR0IF |Timer0 Interrupt Status Flag + * | | |This field is used for Timer0 interrupt status flag. + * | | |0 = Timer0 interrupt did not occur. + * | | |1 = Timer0 interrupt occurred. + * | | |Note: This bit can be cleared by writing 1 to it. + * |[4] |TMR1IF |Timer1 Interrupt Status Flag + * | | |This field is used for Timer1 interrupt status flag. + * | | |0 = Timer1 interrupt did not occur. + * | | |1 = Timer1 interrupt occurred. + * | | |Note: This bit can be cleared by writing 1 to it. + * |[5] |TMR2IF |Timer2 Interrupt Status Flag + * | | |This field is used for Timer2 interrupt status flag. + * | | |0 = Timer2 interrupt did not occur. + * | | |1 = Timer2 interrupt occurred. + * | | |Note: This bit can be cleared by writing 1 to it. + * |[6] |BGTIF |Block Guard Time Interrupt Status Flag + * | | |This field is used for indicate block guard time interrupt status flag in receive direction. + * | | |0 = Block guard time interrupt did not occur. + * | | |1 = Block guard time interrupt occurred. + * | | |Note1: This bit is valid only when RXBGTEN (SCn_ALTCTL[12]) is enabled. + * | | |Note2: This bit can be cleared by writing 1 to it. + * |[7] |CDIF |Card Detect Interrupt Status Flag (Read Only) + * | | |This field is used for card detect interrupt status flag + * | | |The card detect status is CINSERT (SCn_STATUS[12]) and CREMOVE (SCn_STATUS[11]). + * | | |0 = Card detect event did not occur. + * | | |1 = Card detect event occurred. + * | | |Note: This bit is read only, user must to clear CINSERT or CREMOVE status to clear it. + * |[8] |INITIF |Initial End Interrupt Status Flag + * | | |This field is used for activation (ACTEN (SCn_ALTCTL[3])), deactivation (DACTEN (SCn_ALTCTL[2])) and warm reset (WARSTEN (SCn_ALTCTL[4])) sequence interrupt status flag. + * | | |0 = Initial sequence is not complete. + * | | |1 = Initial sequence is completed. + * | | |Note: This bit can be cleared by writing 1 to it. + * |[9] |RXTOIF |Receive Buffer Time-out Interrupt Status Flag (Read Only) + * | | |This field is used for indicate receive buffer time-out interrupt status flag. + * | | |0 = Receive buffer time-out interrupt did not occur. + * | | |1 = Receive buffer time-out interrupt occurred. + * | | |Note: This bit is read only, user must read all receive buffer remaining data by reading SCn_DAT register to clear it. + * |[10] |ACERRIF |Auto Convention Error Interrupt Status Flag + * | | |This field indicates auto convention sequence error. + * | | |0 = Received TS at ATR state is 0x3B or 0x3F. + * | | |1 = Received TS at ATR state is neither 0x3B nor 0x3F. + * | | |Note: This bit can be cleared by writing 1 to it. + * @var SC_T::STATUS + * Offset: 0x20 SC Transfer Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |RXOV |Receive Overflow Error Status Flag + * | | |This bit is set when Rx buffer overflow. + * | | |0 = Rx buffer is not overflow. + * | | |1 = Rx buffer is overflow when the number of received bytes is greater than Rx buffer size (4 bytes). + * | | |Note: This bit can be cleared by writing 1 to it. + * |[1] |RXEMPTY |Receive Buffer Empty Status Flag (Read Only) + * | | |This bit indicates Rx buffer empty or not. + * | | |0 = Rx buffer is not empty. + * | | |1 = Rx buffer is empty, it means the last byte of Rx buffer has read from DAT (SCn_DAT[7:0]) by CPU. + * |[2] |RXFULL |Receive Buffer Full Status Flag (Read Only) + * | | |This bit indicates Rx buffer full or not. + * | | |0 = Rx buffer count is less than 4. + * | | |1 = Rx buffer count equals to 4. + * |[4] |PEF |Receiver Parity Error Status Flag + * | | |This bit is set to logic 1 whenever the received character does not have a valid parity bit. + * | | |0 = Receiver parity error flag did not occur. + * | | |1 = Receiver parity error flag occurred. + * | | |Note1: This bit can be cleared by writing 1 to it. + * | | |Note2: If CPU sets receiver retries function by setting RXRTYEN (SCn_CTL[19]), hardware will not set this flag. + * |[5] |FEF |Receiver Frame Error Status Flag + * | | |This bit is set to logic 1 whenever the received character does not have a valid stop bit (that is, the stop bit following the last data bit or parity bit is detected as logic 0). + * | | |0 = Receiver frame error flag did not occur. + * | | |1 = Receiver frame error flag occurred. + * | | |Note1: This bit can be cleared by writing 1 to it. + * | | |Note2: If CPU sets receiver retries function by setting RXRTYEN (SCn_CTL[19]), hardware will not set this flag. + * |[6] |BEF |Receiver Break Error Status Flag + * | | |This bit is set to logic 1 whenever the received data input (Rx) held in the spacing state (logic 0) is longer than a full word transmission time (that is, the total time of start bit + data bits + parity bit + stop bits). + * | | |0 = Receiver break error flag did not occur. + * | | |1 = Receiver break error flag occurred. + * | | |Note1: This bit can be cleared by writing 1 to it. + * | | |Note2: If CPU sets receiver retries function by setting RXRTYEN (SCn_CTL[19]), hardware will not set this flag. + * |[8] |TXOV |Transmit Overflow Error Interrupt Status Flag + * | | |This bit is set when Tx buffer overflow. + * | | |0 = Tx buffer is not overflow. + * | | |1 = Tx buffer is overflow when Tx buffer is full and an additional write operation to DAT (SCn_DAT[7:0]). + * | | |Note: This bit can be cleared by writing 1 to it. + * |[9] |TXEMPTY |Transmit Buffer Empty Status Flag (Read Only) + * | | |This bit indicates TX buffer empty or not. + * | | |0 = Tx buffer is not empty. + * | | |1 = Tx buffer is empty, it means the last byte of Tx buffer has been transferred to Transmitter Shift Register. + * | | |Note: This bit will be cleared when writing data into DAT (SCn_DAT[7:0]). + * |[10] |TXFULL |Transmit Buffer Full Status Flag (Read Only) + * | | |This bit indicates Tx buffer full or not. + * | | |0 = Tx buffer count is less than 4. + * | | |1 = Tx buffer count equals to 4. + * |[11] |CREMOVE |Card Removal Status of SCn_CD Pin + * | | |This bit is set whenever card has been removal. + * | | |0 = No effect. + * | | |1 = Card removed. + * | | |Note1: This bit can be cleared by writing 1 to it. + * | | |Note2: Card detect function will start after SCEN (SCn_CTL[0]) set. + * |[12] |CINSERT |Card Insert Status of SCn_CD Pin + * | | |This bit is set whenever card has been inserted. + * | | |0 = No effect. + * | | |1 = Card insert. + * | | |Note1: This bit can be cleared by writing 1 to it. + * | | |Note2: The card detect function will start after SCEN (SCn_CTL[0]) set. + * |[13] |CDPINSTS |Card Detect Pin Status (Read Only) + * | | |This bit is the pin status of SCn_CD. + * | | |0 = The SCn_CD pin state at low. + * | | |1 = The SCn_CD pin state at high. + * |[18:16] |RXPOINT |Receive Buffer Pointer Status (Read Only) + * | | |This field indicates the Rx buffer pointer status + * | | |When SC controller receives one byte from external device, RXPOINT increases one + * | | |When one byte of Rx buffer is read by CPU, RXPOINT decreases one. + * |[21] |RXRERR |Receiver Retry Error + * | | |This bit is used for receiver error retry and set by hardware. + * | | |0 = No Rx retry transfer. + * | | |1 = Rx has any error and retries transfer. + * | | |Note1: This bit can be cleared by writing 1 to it. + * | | |Note2 This bit is a flag and cannot generate any interrupt to CPU. + * | | |Note3: If CPU enables receiver retries function by setting RXRTYEN (SCn_CTL[19]), hardware will not set this flag. + * |[22] |RXOVERR |Receiver over Retry Error + * | | |This bit is used for receiver retry counts over than retry number limitation. + * | | |0 = Receiver retries counts is not over than RXRTY (SCn_CTL[18:16]) + 1. + * | | |1 = Receiver retries counts over than RXRTY (SCn_CTL[18:16]) + 1. + * | | |Note1: This bit can be cleared by writing 1 to it. + * | | |Note2: If CPU enables receiver retries function by setting RXRTYEN (SCn_CTL[19]), hardware will not set this flag. + * |[23] |RXACT |Receiver in Active Status Flag (Read Only) + * | | |This bit indicates Rx transfer status. + * | | |0 = This bit is cleared automatically when Rx transfer is finished. + * | | |1 = This bit is set by hardware when Rx transfer is in active. + * | | |Note: This bit is read only. + * | | |Note2: + * |[26:24] |TXPOINT |Transmit Buffer Pointer Status (Read Only) + * | | |This field indicates the Tx buffer pointer status + * | | |When CPU writes data into SCn_DAT, TXPOINT increases one + * | | |When one byte of Tx buffer is transferred to transmitter shift register, TXPOINT decreases one. + * |[29] |TXRERR |Transmitter Retry Error + * | | |This bit is used for indicate transmitter error retry and set by hardware.. + * | | |0 = No Tx retry transfer. + * | | |1 = Tx has any error and retries transfer. + * | | |Note1: This bit can be cleared by writing 1 to it. + * | | |Note2: This bit is a flag and cannot generate any interrupt to CPU. + * |[30] |TXOVERR |Transmitter over Retry Error + * | | |This bit is used for transmitter retry counts over than retry number limitation. + * | | |0 = Transmitter retries counts is not over than TXRTY (SCn_CTL[22:20]) + 1. + * | | |1 = Transmitter retries counts over than TXRTY (SCn_CTL[22:20]) + 1. + * | | |Note: This bit can be cleared by writing 1 to it. + * |[31] |TXACT |Transmit in Active Status Flag (Read Only) + * | | |This bit indicates Tx transmit status. + * | | |0 = This bit is cleared automatically when Tx transfer is finished or the last byte transmission has completed. + * | | |1 = Transmit is active and this bit is set by hardware when Tx transfer is in active and the STOP bit of the last byte has not been transmitted. + * | | |Note: This bit is read only. + * @var SC_T::PINCTL + * Offset: 0x24 SC Pin Control State Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |PWREN |SCn_PWR Pin Signal + * | | |User can set PWRINV (SCn_PINCTL[11]) and PWREN (SCn_PINCTL[0]) to decide SCn_PWR pin is in high or low level. + * | | |Write this field to drive SCn_PWR pin + * | | |Refer PWRINV (SCn_PINCTL[11]) description for programming SCn_PWR pin voltage level. + * | | |Read this field to get SCn_PWR signal status. + * | | |0 = SCn_PWR signal status is low. + * | | |1 = SCn_PWR signal status is high. + * | | |Note: When operating at activation, warm reset or deactivation mode, this bit will be changed automatically + * | | |Thus, do not fill in this field when operating in these modes. + * |[1] |RSTEN |SCn_RST Pin Signal + * | | |User can set RSTEN (SCn_PINCTL[1]) to decide SCn_RST pin is in high or low level. + * | | |Write this field to drive SCn_RST pin. + * | | |0 = Drive SCn_RST pin to low. + * | | |1 = Drive SCn_RST pin to high. + * | | |Read this field to get SCn_RST signal status. + * | | |0 = SCn_RST signal status is low. + * | | |1 = SCn_RST signal status is high. + * | | |Note: When operating at activation, warm reset or deactivation mode, this bit will be changed automatically + * | | |Thus, do not fill in this field when operating in these modes. + * |[5] |CSTOPLV |SCn_CLK Pin Stop Level + * | | |This field indicates the SCn_CLK pin status when SC clock in clock stop mode. + * | | |0 = SCn_CLK pin keeps at low when SC clock stopped. + * | | |1 = SCn_CLK pin keeps at high when SC clock stopped. + * |[6] |CLKKEEP |SC Clock Enable Bit + * | | |0 = SC clock generation Disabled. + * | | |1 = SC clock always keeps free running. + * | | |Note: When operating in activation, warm reset or deactivation mode, this bit will be changed automatically + * | | |Thus, do not fill in this field when operating in these modes. + * |[9] |SCDATA |SCn_DATA Pin Signal + * | | |This bit is the signal status of SCn_DATA but user can drive SCn_DATA pin to high or low by setting this bit. + * | | |0 = Drive SCn_DATA pin to low. + * | | |1 = Drive SCn_DATA pin to high. + * | | |Read this field to get SCn_DATA signal status. + * | | |0 = SCn_DATA signal status is low. + * | | |1 = SCn_DATA signal status is high. + * | | |Note: When SC is at activation, warm reset or deactivation mode, this bit will be changed automatically + * | | |Thus, do not fill in this field when SC is in these modes. + * |[11] |PWRINV |SCn_PWR Pin Inverse + * | | |This bit is used for inverse the SCn_PWR pin. + * | | |There are four kinds of combination for SCn_PWR pin setting by PWRINV (SCn_PINCTL[11]) and PWREN (SCn_PINCTL[0]). + * | | |0 = SCn_PWR pin inverse Disabled + * | | |If PWREN is 1, SCn_PWR pin status is 1; if PWREN is 0, SCn_PWR pin status is 0. + * | | |1 = SCn_PWR pin inverse Enabled + * | | |If PWREN is 1, SCn_PWR pin status is 0; if PWREN is 0, SCn_PWR pin status is 1. + * | | |Note: User must select PWRINV (SCn_PINCTL[11]) before smart card is enabled by SCEN (SCn_CTL[0]). + * |[16] |DATASTS |SCn_DATA Pin Status (Read Only) + * | | |This bit is the pin status of SCn_DATA. + * | | |0 = The SCn_DATA pin status is low. + * | | |1 = The SCn_DATA pin status is high. + * | | |Note: + * |[17] |PWRSTS |SCn_PWR Pin Status (Read Only) + * | | |This bit is the pin status of SCn_PWR. + * | | |0 = SCn_PWR pin to low. + * | | |1 = SCn_PWR pin to high. + * |[18] |RSTSTS |SCn_RST Pin Status (Read Only) + * | | |This bit is the pin status of SCn_RST. + * | | |0 = SCn_RST pin is low. + * | | |1 = SCn_RST pin is high. + * |[30] |SYNC |SYNC Flag Indicator (Read Only) + * | | |Due to synchronization, user should check this bit when writing a new value to SCn_PINCTL register. + * | | |0 = Synchronizing is completion, user can write new data to SCn_PINCTL register. + * | | |1 = Last value is synchronizing. + * @var SC_T::TMRCTL0 + * Offset: 0x28 SC Internal Timer0 Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[23:0] |CNT |Timer0 Counter Value + * | | |This field indicates the internal Timer0 counter values. + * | | |Note: Unit of Timer0 counter is ETU base. + * |[27:24] |OPMODE |Timer0 Operation Mode Selection + * | | |This field indicates the internal 24-bit Timer0 operation selection. + * | | |Refer to Table 6.17-3 Timer0/Timer1/Timer2 Operation Mode for programming Timer0. + * |[31] |SYNC |SYNC Flag Indicator (Read Only) + * | | |Due to synchronization, user should check this bit when writing a new value to the SCn_TMRCTL0 register. + * | | |0 = Synchronizing is completion, user can write new data to SCn_TMRCTL0 register. + * | | |1 = Last value is synchronizing. + * @var SC_T::TMRCTL1 + * Offset: 0x2C SC Internal Timer1 Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[7:0] |CNT |Timer 1 Counter Value + * | | |This field indicates the internal Timer1 counter values. + * | | |Note: Unit of Timer1 counter is ETU base. + * |[27:24] |OPMODE |Timer 1 Operation Mode Selection + * | | |This field indicates the internal 8-bit Timer1 operation selection. + * | | |Refer to Table 6.17-3 Timer0/Timer1/Timer2 Operation Mode for programming Timer1. + * |[31] |SYNC |SYNC Flag Indicator (Read Only) + * | | |Due to synchronization, software should check this bit when writing a new value to SCn_TMRCTL1 register. + * | | |0 = Synchronizing is completion, user can write new data to SCn_TMRCTL1 register. + * | | |1 = Last value is synchronizing. + * @var SC_T::TMRCTL2 + * Offset: 0x30 SC Internal Timer2 Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[7:0] |CNT |Timer 2 Counter Value + * | | |This field indicates the internal Timer2 counter values. + * | | |Note: Unit of Timer2 counter is ETU base. + * |[27:24] |OPMODE |Timer 2 Operation Mode Selection + * | | |This field indicates the internal 8-bit Timer2 operation selection + * | | |Refer to Table 6.17-3 Timer0/Timer1/Timer2 Operation Mode for programming Timer2. + * |[31] |SYNC |SYNC Flag Indicator (Read Only) + * | | |Due to synchronization, user should check this bit when writing a new value to SCn_TMRCTL2 register. + * | | |0 = Synchronizing is completion, user can write new data to SCn_TMRCTL2 register. + * | | |1 = Last value is synchronizing. + * @var SC_T::UARTCTL + * Offset: 0x34 SC UART Mode Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |UARTEN |UART Mode Enable Bit + * | | |Sets this bit to enable UART mode function. + * | | |0 = Smart Card mode. + * | | |1 = UART mode. + * | | |Note1: When operating in UART mode, user must set CONSEL (SCn_CTL[5:4]) = 00 and AUTOCEN (SCn_CTL[3]) = 0. + * | | |Note2: When operating in Smart Card mode, user must set UARTEN (SCn_UARTCTL[0]) = 0. + * | | |Note3: When UART mode is enabled, hardware will generate a reset to reset FIFO and internal state machine. + * |[5:4] |WLS |Word Length Selection + * | | |This field is used for select UART data length. + * | | |00 = Word length is 8 bits. + * | | |01 = Word length is 7 bits. + * | | |10 = Word length is 6 bits. + * | | |11 = Word length is 5 bits. + * | | |Note: In smart card mode, this WLS must be u201800'. + * |[6] |PBOFF |Parity Bit Disable Control + * | | |Sets this bit is used for disable parity check function. + * | | |0 = Parity bit is generated or checked between the last data word bit and stop bit of the serial data. + * | | |1 = Parity bit is not generated (transmitting data) or checked (receiving data) during transfer. + * | | |Note: In smart card mode, this field must be u20180' (default setting is with parity bit). + * |[7] |OPE |Odd Parity Enable Bit + * | | |This is used for odd/even parity selection. + * | | |0 = Even number of logic 1's are transmitted or check the data word and parity bits in receiving mode. + * | | |1 = Odd number of logic 1's are transmitted or check the data word and parity bits in receiving mode. + * | | |Note: This bit has effect only when PBOFF bit is u20180'. + * @var SC_T::ACTCTL + * Offset: 0x4C SC Activation Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[4:0] |T1EXT |T1 Extend Time of Hardware Activation + * | | |This field provide the configurable cycles to extend the activation time T1 period. + * | | |The cycle scaling factor is 2048. + * | | |Extend cycles = (filled value * 2048) cycles. + * | | |Refer to SC activation sequence in Figure 6.17-4 SC Activation Sequence. + * | | |For example, + * | | |SCLK = 4MHz, each cycle = 0.25us,. + * | | |Filled 20 to this field + * | | |Extend time = 20 * 2048 * 0.25us = 10.24 ms. + * | | |Note: Setting 0 to this field conforms to the protocol ISO/IEC 7816-3 + */ + __IO uint32_t DAT; /*!< [0x0000] SC Receive/Transmit Holding Buffer Register */ + __IO uint32_t CTL; /*!< [0x0004] SC Control Register */ + __IO uint32_t ALTCTL; /*!< [0x0008] SC Alternate Control Register */ + __IO uint32_t EGT; /*!< [0x000c] SC Extra Guard Time Register */ + __IO uint32_t RXTOUT; /*!< [0x0010] SC Receive Buffer Time-out Counter Register */ + __IO uint32_t ETUCTL; /*!< [0x0014] SC Element Time Unit Control Register */ + __IO uint32_t INTEN; /*!< [0x0018] SC Interrupt Enable Control Register */ + __IO uint32_t INTSTS; /*!< [0x001c] SC Interrupt Status Register */ + __IO uint32_t STATUS; /*!< [0x0020] SC Transfer Status Register */ + __IO uint32_t PINCTL; /*!< [0x0024] SC Pin Control State Register */ + __IO uint32_t TMRCTL0; /*!< [0x0028] SC Internal Timer0 Control Register */ + __IO uint32_t TMRCTL1; /*!< [0x002c] SC Internal Timer1 Control Register */ + __IO uint32_t TMRCTL2; /*!< [0x0030] SC Internal Timer2 Control Register */ + __IO uint32_t UARTCTL; /*!< [0x0034] SC UART Mode Control Register */ + __I uint32_t RESERVE0[5]; + __IO uint32_t ACTCTL; /*!< [0x004c] SC Activation Control Register */ + +} SC_T; + +/** + @addtogroup SC_CONST SC Bit Field Definition + Constant Definitions for SC Controller + @{ +*/ + +#define SC_DAT_DAT_Pos (0) /*!< SC_T::DAT: DAT Position */ +#define SC_DAT_DAT_Msk (0xfful << SC_DAT_DAT_Pos) /*!< SC_T::DAT: DAT Mask */ + +#define SC_CTL_SCEN_Pos (0) /*!< SC_T::CTL: SCEN Position */ +#define SC_CTL_SCEN_Msk (0x1ul << SC_CTL_SCEN_Pos) /*!< SC_T::CTL: SCEN Mask */ + +#define SC_CTL_RXOFF_Pos (1) /*!< SC_T::CTL: RXOFF Position */ +#define SC_CTL_RXOFF_Msk (0x1ul << SC_CTL_RXOFF_Pos) /*!< SC_T::CTL: RXOFF Mask */ + +#define SC_CTL_TXOFF_Pos (2) /*!< SC_T::CTL: TXOFF Position */ +#define SC_CTL_TXOFF_Msk (0x1ul << SC_CTL_TXOFF_Pos) /*!< SC_T::CTL: TXOFF Mask */ + +#define SC_CTL_AUTOCEN_Pos (3) /*!< SC_T::CTL: AUTOCEN Position */ +#define SC_CTL_AUTOCEN_Msk (0x1ul << SC_CTL_AUTOCEN_Pos) /*!< SC_T::CTL: AUTOCEN Mask */ + +#define SC_CTL_CONSEL_Pos (4) /*!< SC_T::CTL: CONSEL Position */ +#define SC_CTL_CONSEL_Msk (0x3ul << SC_CTL_CONSEL_Pos) /*!< SC_T::CTL: CONSEL Mask */ + +#define SC_CTL_RXTRGLV_Pos (6) /*!< SC_T::CTL: RXTRGLV Position */ +#define SC_CTL_RXTRGLV_Msk (0x3ul << SC_CTL_RXTRGLV_Pos) /*!< SC_T::CTL: RXTRGLV Mask */ + +#define SC_CTL_BGT_Pos (8) /*!< SC_T::CTL: BGT Position */ +#define SC_CTL_BGT_Msk (0x1ful << SC_CTL_BGT_Pos) /*!< SC_T::CTL: BGT Mask */ + +#define SC_CTL_TMRSEL_Pos (13) /*!< SC_T::CTL: TMRSEL Position */ +#define SC_CTL_TMRSEL_Msk (0x3ul << SC_CTL_TMRSEL_Pos) /*!< SC_T::CTL: TMRSEL Mask */ + +#define SC_CTL_NSB_Pos (15) /*!< SC_T::CTL: NSB Position */ +#define SC_CTL_NSB_Msk (0x1ul << SC_CTL_NSB_Pos) /*!< SC_T::CTL: NSB Mask */ + +#define SC_CTL_RXRTY_Pos (16) /*!< SC_T::CTL: RXRTY Position */ +#define SC_CTL_RXRTY_Msk (0x7ul << SC_CTL_RXRTY_Pos) /*!< SC_T::CTL: RXRTY Mask */ + +#define SC_CTL_RXRTYEN_Pos (19) /*!< SC_T::CTL: RXRTYEN Position */ +#define SC_CTL_RXRTYEN_Msk (0x1ul << SC_CTL_RXRTYEN_Pos) /*!< SC_T::CTL: RXRTYEN Mask */ + +#define SC_CTL_TXRTY_Pos (20) /*!< SC_T::CTL: TXRTY Position */ +#define SC_CTL_TXRTY_Msk (0x7ul << SC_CTL_TXRTY_Pos) /*!< SC_T::CTL: TXRTY Mask */ + +#define SC_CTL_TXRTYEN_Pos (23) /*!< SC_T::CTL: TXRTYEN Position */ +#define SC_CTL_TXRTYEN_Msk (0x1ul << SC_CTL_TXRTYEN_Pos) /*!< SC_T::CTL: TXRTYEN Mask */ + +#define SC_CTL_CDDBSEL_Pos (24) /*!< SC_T::CTL: CDDBSEL Position */ +#define SC_CTL_CDDBSEL_Msk (0x3ul << SC_CTL_CDDBSEL_Pos) /*!< SC_T::CTL: CDDBSEL Mask */ + +#define SC_CTL_CDLV_Pos (26) /*!< SC_T::CTL: CDLV Position */ +#define SC_CTL_CDLV_Msk (0x1ul << SC_CTL_CDLV_Pos) /*!< SC_T::CTL: CDLV Mask */ + +#define SC_CTL_SYNC_Pos (30) /*!< SC_T::CTL: SYNC Position */ +#define SC_CTL_SYNC_Msk (0x1ul << SC_CTL_SYNC_Pos) /*!< SC_T::CTL: SYNC Mask */ + +#define SC_ALTCTL_TXRST_Pos (0) /*!< SC_T::ALTCTL: TXRST Position */ +#define SC_ALTCTL_TXRST_Msk (0x1ul << SC_ALTCTL_TXRST_Pos) /*!< SC_T::ALTCTL: TXRST Mask */ + +#define SC_ALTCTL_RXRST_Pos (1) /*!< SC_T::ALTCTL: RXRST Position */ +#define SC_ALTCTL_RXRST_Msk (0x1ul << SC_ALTCTL_RXRST_Pos) /*!< SC_T::ALTCTL: RXRST Mask */ + +#define SC_ALTCTL_DACTEN_Pos (2) /*!< SC_T::ALTCTL: DACTEN Position */ +#define SC_ALTCTL_DACTEN_Msk (0x1ul << SC_ALTCTL_DACTEN_Pos) /*!< SC_T::ALTCTL: DACTEN Mask */ + +#define SC_ALTCTL_ACTEN_Pos (3) /*!< SC_T::ALTCTL: ACTEN Position */ +#define SC_ALTCTL_ACTEN_Msk (0x1ul << SC_ALTCTL_ACTEN_Pos) /*!< SC_T::ALTCTL: ACTEN Mask */ + +#define SC_ALTCTL_WARSTEN_Pos (4) /*!< SC_T::ALTCTL: WARSTEN Position */ +#define SC_ALTCTL_WARSTEN_Msk (0x1ul << SC_ALTCTL_WARSTEN_Pos) /*!< SC_T::ALTCTL: WARSTEN Mask */ + +#define SC_ALTCTL_CNTEN0_Pos (5) /*!< SC_T::ALTCTL: CNTEN0 Position */ +#define SC_ALTCTL_CNTEN0_Msk (0x1ul << SC_ALTCTL_CNTEN0_Pos) /*!< SC_T::ALTCTL: CNTEN0 Mask */ + +#define SC_ALTCTL_CNTEN1_Pos (6) /*!< SC_T::ALTCTL: CNTEN1 Position */ +#define SC_ALTCTL_CNTEN1_Msk (0x1ul << SC_ALTCTL_CNTEN1_Pos) /*!< SC_T::ALTCTL: CNTEN1 Mask */ + +#define SC_ALTCTL_CNTEN2_Pos (7) /*!< SC_T::ALTCTL: CNTEN2 Position */ +#define SC_ALTCTL_CNTEN2_Msk (0x1ul << SC_ALTCTL_CNTEN2_Pos) /*!< SC_T::ALTCTL: CNTEN2 Mask */ + +#define SC_ALTCTL_INITSEL_Pos (8) /*!< SC_T::ALTCTL: INITSEL Position */ +#define SC_ALTCTL_INITSEL_Msk (0x3ul << SC_ALTCTL_INITSEL_Pos) /*!< SC_T::ALTCTL: INITSEL Mask */ + +#define SC_ALTCTL_ADACEN_Pos (11) /*!< SC_T::ALTCTL: ADACEN Position */ +#define SC_ALTCTL_ADACEN_Msk (0x1ul << SC_ALTCTL_ADACEN_Pos) /*!< SC_T::ALTCTL: ADACEN Mask */ + +#define SC_ALTCTL_RXBGTEN_Pos (12) /*!< SC_T::ALTCTL: RXBGTEN Position */ +#define SC_ALTCTL_RXBGTEN_Msk (0x1ul << SC_ALTCTL_RXBGTEN_Pos) /*!< SC_T::ALTCTL: RXBGTEN Mask */ + +#define SC_ALTCTL_ACTSTS0_Pos (13) /*!< SC_T::ALTCTL: ACTSTS0 Position */ +#define SC_ALTCTL_ACTSTS0_Msk (0x1ul << SC_ALTCTL_ACTSTS0_Pos) /*!< SC_T::ALTCTL: ACTSTS0 Mask */ + +#define SC_ALTCTL_ACTSTS1_Pos (14) /*!< SC_T::ALTCTL: ACTSTS1 Position */ +#define SC_ALTCTL_ACTSTS1_Msk (0x1ul << SC_ALTCTL_ACTSTS1_Pos) /*!< SC_T::ALTCTL: ACTSTS1 Mask */ + +#define SC_ALTCTL_ACTSTS2_Pos (15) /*!< SC_T::ALTCTL: ACTSTS2 Position */ +#define SC_ALTCTL_ACTSTS2_Msk (0x1ul << SC_ALTCTL_ACTSTS2_Pos) /*!< SC_T::ALTCTL: ACTSTS2 Mask */ + +#define SC_ALTCTL_SYNC_Pos (31) /*!< SC_T::ALTCTL: SYNC Position */ +#define SC_ALTCTL_SYNC_Msk (0x1ul << SC_ALTCTL_SYNC_Pos) /*!< SC_T::ALTCTL: SYNC Mask */ + +#define SC_EGT_EGT_Pos (0) /*!< SC_T::EGT: EGT Position */ +#define SC_EGT_EGT_Msk (0xfful << SC_EGT_EGT_Pos) /*!< SC_T::EGT: EGT Mask */ + +#define SC_RXTOUT_RFTM_Pos (0) /*!< SC_T::RXTOUT: RFTM Position */ +#define SC_RXTOUT_RFTM_Msk (0x1fful << SC_RXTOUT_RFTM_Pos) /*!< SC_T::RXTOUT: RFTM Mask */ + +#define SC_ETUCTL_ETURDIV_Pos (0) /*!< SC_T::ETUCTL: ETURDIV Position */ +#define SC_ETUCTL_ETURDIV_Msk (0xffful << SC_ETUCTL_ETURDIV_Pos) /*!< SC_T::ETUCTL: ETURDIV Mask */ + +#define SC_INTEN_RDAIEN_Pos (0) /*!< SC_T::INTEN: RDAIEN Position */ +#define SC_INTEN_RDAIEN_Msk (0x1ul << SC_INTEN_RDAIEN_Pos) /*!< SC_T::INTEN: RDAIEN Mask */ + +#define SC_INTEN_TBEIEN_Pos (1) /*!< SC_T::INTEN: TBEIEN Position */ +#define SC_INTEN_TBEIEN_Msk (0x1ul << SC_INTEN_TBEIEN_Pos) /*!< SC_T::INTEN: TBEIEN Mask */ + +#define SC_INTEN_TERRIEN_Pos (2) /*!< SC_T::INTEN: TERRIEN Position */ +#define SC_INTEN_TERRIEN_Msk (0x1ul << SC_INTEN_TERRIEN_Pos) /*!< SC_T::INTEN: TERRIEN Mask */ + +#define SC_INTEN_TMR0IEN_Pos (3) /*!< SC_T::INTEN: TMR0IEN Position */ +#define SC_INTEN_TMR0IEN_Msk (0x1ul << SC_INTEN_TMR0IEN_Pos) /*!< SC_T::INTEN: TMR0IEN Mask */ + +#define SC_INTEN_TMR1IEN_Pos (4) /*!< SC_T::INTEN: TMR1IEN Position */ +#define SC_INTEN_TMR1IEN_Msk (0x1ul << SC_INTEN_TMR1IEN_Pos) /*!< SC_T::INTEN: TMR1IEN Mask */ + +#define SC_INTEN_TMR2IEN_Pos (5) /*!< SC_T::INTEN: TMR2IEN Position */ +#define SC_INTEN_TMR2IEN_Msk (0x1ul << SC_INTEN_TMR2IEN_Pos) /*!< SC_T::INTEN: TMR2IEN Mask */ + +#define SC_INTEN_BGTIEN_Pos (6) /*!< SC_T::INTEN: BGTIEN Position */ +#define SC_INTEN_BGTIEN_Msk (0x1ul << SC_INTEN_BGTIEN_Pos) /*!< SC_T::INTEN: BGTIEN Mask */ + +#define SC_INTEN_CDIEN_Pos (7) /*!< SC_T::INTEN: CDIEN Position */ +#define SC_INTEN_CDIEN_Msk (0x1ul << SC_INTEN_CDIEN_Pos) /*!< SC_T::INTEN: CDIEN Mask */ + +#define SC_INTEN_INITIEN_Pos (8) /*!< SC_T::INTEN: INITIEN Position */ +#define SC_INTEN_INITIEN_Msk (0x1ul << SC_INTEN_INITIEN_Pos) /*!< SC_T::INTEN: INITIEN Mask */ + +#define SC_INTEN_RXTOIEN_Pos (9) /*!< SC_T::INTEN: RXTOIEN Position */ +#define SC_INTEN_RXTOIEN_Msk (0x1ul << SC_INTEN_RXTOIEN_Pos) /*!< SC_T::INTEN: RXTOIEN Mask */ + +#define SC_INTEN_ACERRIEN_Pos (10) /*!< SC_T::INTEN: ACERRIEN Position */ +#define SC_INTEN_ACERRIEN_Msk (0x1ul << SC_INTEN_ACERRIEN_Pos) /*!< SC_T::INTEN: ACERRIEN Mask */ + +#define SC_INTSTS_RDAIF_Pos (0) /*!< SC_T::INTSTS: RDAIF Position */ +#define SC_INTSTS_RDAIF_Msk (0x1ul << SC_INTSTS_RDAIF_Pos) /*!< SC_T::INTSTS: RDAIF Mask */ + +#define SC_INTSTS_TBEIF_Pos (1) /*!< SC_T::INTSTS: TBEIF Position */ +#define SC_INTSTS_TBEIF_Msk (0x1ul << SC_INTSTS_TBEIF_Pos) /*!< SC_T::INTSTS: TBEIF Mask */ + +#define SC_INTSTS_TERRIF_Pos (2) /*!< SC_T::INTSTS: TERRIF Position */ +#define SC_INTSTS_TERRIF_Msk (0x1ul << SC_INTSTS_TERRIF_Pos) /*!< SC_T::INTSTS: TERRIF Mask */ + +#define SC_INTSTS_TMR0IF_Pos (3) /*!< SC_T::INTSTS: TMR0IF Position */ +#define SC_INTSTS_TMR0IF_Msk (0x1ul << SC_INTSTS_TMR0IF_Pos) /*!< SC_T::INTSTS: TMR0IF Mask */ + +#define SC_INTSTS_TMR1IF_Pos (4) /*!< SC_T::INTSTS: TMR1IF Position */ +#define SC_INTSTS_TMR1IF_Msk (0x1ul << SC_INTSTS_TMR1IF_Pos) /*!< SC_T::INTSTS: TMR1IF Mask */ + +#define SC_INTSTS_TMR2IF_Pos (5) /*!< SC_T::INTSTS: TMR2IF Position */ +#define SC_INTSTS_TMR2IF_Msk (0x1ul << SC_INTSTS_TMR2IF_Pos) /*!< SC_T::INTSTS: TMR2IF Mask */ + +#define SC_INTSTS_BGTIF_Pos (6) /*!< SC_T::INTSTS: BGTIF Position */ +#define SC_INTSTS_BGTIF_Msk (0x1ul << SC_INTSTS_BGTIF_Pos) /*!< SC_T::INTSTS: BGTIF Mask */ + +#define SC_INTSTS_CDIF_Pos (7) /*!< SC_T::INTSTS: CDIF Position */ +#define SC_INTSTS_CDIF_Msk (0x1ul << SC_INTSTS_CDIF_Pos) /*!< SC_T::INTSTS: CDIF Mask */ + +#define SC_INTSTS_INITIF_Pos (8) /*!< SC_T::INTSTS: INITIF Position */ +#define SC_INTSTS_INITIF_Msk (0x1ul << SC_INTSTS_INITIF_Pos) /*!< SC_T::INTSTS: INITIF Mask */ + +#define SC_INTSTS_RXTOIF_Pos (9) /*!< SC_T::INTSTS: RXTOIF Position */ +#define SC_INTSTS_RXTOIF_Msk (0x1ul << SC_INTSTS_RXTOIF_Pos) /*!< SC_T::INTSTS: RXTOIF Mask */ + +#define SC_INTSTS_ACERRIF_Pos (10) /*!< SC_T::INTSTS: ACERRIF Position */ +#define SC_INTSTS_ACERRIF_Msk (0x1ul << SC_INTSTS_ACERRIF_Pos) /*!< SC_T::INTSTS: ACERRIF Mask */ + +#define SC_STATUS_RXOV_Pos (0) /*!< SC_T::STATUS: RXOV Position */ +#define SC_STATUS_RXOV_Msk (0x1ul << SC_STATUS_RXOV_Pos) /*!< SC_T::STATUS: RXOV Mask */ + +#define SC_STATUS_RXEMPTY_Pos (1) /*!< SC_T::STATUS: RXEMPTY Position */ +#define SC_STATUS_RXEMPTY_Msk (0x1ul << SC_STATUS_RXEMPTY_Pos) /*!< SC_T::STATUS: RXEMPTY Mask */ + +#define SC_STATUS_RXFULL_Pos (2) /*!< SC_T::STATUS: RXFULL Position */ +#define SC_STATUS_RXFULL_Msk (0x1ul << SC_STATUS_RXFULL_Pos) /*!< SC_T::STATUS: RXFULL Mask */ + +#define SC_STATUS_PEF_Pos (4) /*!< SC_T::STATUS: PEF Position */ +#define SC_STATUS_PEF_Msk (0x1ul << SC_STATUS_PEF_Pos) /*!< SC_T::STATUS: PEF Mask */ + +#define SC_STATUS_FEF_Pos (5) /*!< SC_T::STATUS: FEF Position */ +#define SC_STATUS_FEF_Msk (0x1ul << SC_STATUS_FEF_Pos) /*!< SC_T::STATUS: FEF Mask */ + +#define SC_STATUS_BEF_Pos (6) /*!< SC_T::STATUS: BEF Position */ +#define SC_STATUS_BEF_Msk (0x1ul << SC_STATUS_BEF_Pos) /*!< SC_T::STATUS: BEF Mask */ + +#define SC_STATUS_TXOV_Pos (8) /*!< SC_T::STATUS: TXOV Position */ +#define SC_STATUS_TXOV_Msk (0x1ul << SC_STATUS_TXOV_Pos) /*!< SC_T::STATUS: TXOV Mask */ + +#define SC_STATUS_TXEMPTY_Pos (9) /*!< SC_T::STATUS: TXEMPTY Position */ +#define SC_STATUS_TXEMPTY_Msk (0x1ul << SC_STATUS_TXEMPTY_Pos) /*!< SC_T::STATUS: TXEMPTY Mask */ + +#define SC_STATUS_TXFULL_Pos (10) /*!< SC_T::STATUS: TXFULL Position */ +#define SC_STATUS_TXFULL_Msk (0x1ul << SC_STATUS_TXFULL_Pos) /*!< SC_T::STATUS: TXFULL Mask */ + +#define SC_STATUS_CREMOVE_Pos (11) /*!< SC_T::STATUS: CREMOVE Position */ +#define SC_STATUS_CREMOVE_Msk (0x1ul << SC_STATUS_CREMOVE_Pos) /*!< SC_T::STATUS: CREMOVE Mask */ + +#define SC_STATUS_CINSERT_Pos (12) /*!< SC_T::STATUS: CINSERT Position */ +#define SC_STATUS_CINSERT_Msk (0x1ul << SC_STATUS_CINSERT_Pos) /*!< SC_T::STATUS: CINSERT Mask */ + +#define SC_STATUS_CDPINSTS_Pos (13) /*!< SC_T::STATUS: CDPINSTS Position */ +#define SC_STATUS_CDPINSTS_Msk (0x1ul << SC_STATUS_CDPINSTS_Pos) /*!< SC_T::STATUS: CDPINSTS Mask */ + +#define SC_STATUS_RXPOINT_Pos (16) /*!< SC_T::STATUS: RXPOINT Position */ +#define SC_STATUS_RXPOINT_Msk (0x7ul << SC_STATUS_RXPOINT_Pos) /*!< SC_T::STATUS: RXPOINT Mask */ + +#define SC_STATUS_RXRERR_Pos (21) /*!< SC_T::STATUS: RXRERR Position */ +#define SC_STATUS_RXRERR_Msk (0x1ul << SC_STATUS_RXRERR_Pos) /*!< SC_T::STATUS: RXRERR Mask */ + +#define SC_STATUS_RXOVERR_Pos (22) /*!< SC_T::STATUS: RXOVERR Position */ +#define SC_STATUS_RXOVERR_Msk (0x1ul << SC_STATUS_RXOVERR_Pos) /*!< SC_T::STATUS: RXOVERR Mask */ + +#define SC_STATUS_RXACT_Pos (23) /*!< SC_T::STATUS: RXACT Position */ +#define SC_STATUS_RXACT_Msk (0x1ul << SC_STATUS_RXACT_Pos) /*!< SC_T::STATUS: RXACT Mask */ + +#define SC_STATUS_TXPOINT_Pos (24) /*!< SC_T::STATUS: TXPOINT Position */ +#define SC_STATUS_TXPOINT_Msk (0x7ul << SC_STATUS_TXPOINT_Pos) /*!< SC_T::STATUS: TXPOINT Mask */ + +#define SC_STATUS_TXRERR_Pos (29) /*!< SC_T::STATUS: TXRERR Position */ +#define SC_STATUS_TXRERR_Msk (0x1ul << SC_STATUS_TXRERR_Pos) /*!< SC_T::STATUS: TXRERR Mask */ + +#define SC_STATUS_TXOVERR_Pos (30) /*!< SC_T::STATUS: TXOVERR Position */ +#define SC_STATUS_TXOVERR_Msk (0x1ul << SC_STATUS_TXOVERR_Pos) /*!< SC_T::STATUS: TXOVERR Mask */ + +#define SC_STATUS_TXACT_Pos (31) /*!< SC_T::STATUS: TXACT Position */ +#define SC_STATUS_TXACT_Msk (0x1ul << SC_STATUS_TXACT_Pos) /*!< SC_T::STATUS: TXACT Mask */ + +#define SC_PINCTL_PWREN_Pos (0) /*!< SC_T::PINCTL: PWREN Position */ +#define SC_PINCTL_PWREN_Msk (0x1ul << SC_PINCTL_PWREN_Pos) /*!< SC_T::PINCTL: PWREN Mask */ + +#define SC_PINCTL_RSTEN_Pos (1) /*!< SC_T::PINCTL: RSTEN Position */ +#define SC_PINCTL_RSTEN_Msk (0x1ul << SC_PINCTL_RSTEN_Pos) /*!< SC_T::PINCTL: RSTEN Mask */ + +#define SC_PINCTL_CSTOPLV_Pos (5) /*!< SC_T::PINCTL: CSTOPLV Position */ +#define SC_PINCTL_CSTOPLV_Msk (0x1ul << SC_PINCTL_CSTOPLV_Pos) /*!< SC_T::PINCTL: CSTOPLV Mask */ + +#define SC_PINCTL_CLKKEEP_Pos (6) /*!< SC_T::PINCTL: CLKKEEP Position */ +#define SC_PINCTL_CLKKEEP_Msk (0x1ul << SC_PINCTL_CLKKEEP_Pos) /*!< SC_T::PINCTL: CLKKEEP Mask */ + +#define SC_PINCTL_SCDATA_Pos (9) /*!< SC_T::PINCTL: SCDATA Position */ +#define SC_PINCTL_SCDATA_Msk (0x1ul << SC_PINCTL_SCDATA_Pos) /*!< SC_T::PINCTL: SCDATA Mask */ + +#define SC_PINCTL_PWRINV_Pos (11) /*!< SC_T::PINCTL: PWRINV Position */ +#define SC_PINCTL_PWRINV_Msk (0x1ul << SC_PINCTL_PWRINV_Pos) /*!< SC_T::PINCTL: PWRINV Mask */ + +#define SC_PINCTL_DATASTS_Pos (16) /*!< SC_T::PINCTL: DATASTS Position */ +#define SC_PINCTL_DATASTS_Msk (0x1ul << SC_PINCTL_DATASTS_Pos) /*!< SC_T::PINCTL: DATASTS Mask */ + +#define SC_PINCTL_PWRSTS_Pos (17) /*!< SC_T::PINCTL: PWRSTS Position */ +#define SC_PINCTL_PWRSTS_Msk (0x1ul << SC_PINCTL_PWRSTS_Pos) /*!< SC_T::PINCTL: PWRSTS Mask */ + +#define SC_PINCTL_RSTSTS_Pos (18) /*!< SC_T::PINCTL: RSTSTS Position */ +#define SC_PINCTL_RSTSTS_Msk (0x1ul << SC_PINCTL_RSTSTS_Pos) /*!< SC_T::PINCTL: RSTSTS Mask */ + +#define SC_PINCTL_SYNC_Pos (30) /*!< SC_T::PINCTL: SYNC Position */ +#define SC_PINCTL_SYNC_Msk (0x1ul << SC_PINCTL_SYNC_Pos) /*!< SC_T::PINCTL: SYNC Mask */ + +#define SC_TMRCTL0_CNT_Pos (0) /*!< SC_T::TMRCTL0: CNT Position */ +#define SC_TMRCTL0_CNT_Msk (0xfffffful << SC_TMRCTL0_CNT_Pos) /*!< SC_T::TMRCTL0: CNT Mask */ + +#define SC_TMRCTL0_OPMODE_Pos (24) /*!< SC_T::TMRCTL0: OPMODE Position */ +#define SC_TMRCTL0_OPMODE_Msk (0xful << SC_TMRCTL0_OPMODE_Pos) /*!< SC_T::TMRCTL0: OPMODE Mask */ + +#define SC_TMRCTL0_SYNC_Pos (31) /*!< SC_T::TMRCTL0: SYNC Position */ +#define SC_TMRCTL0_SYNC_Msk (0x1ul << SC_TMRCTL0_SYNC_Pos) /*!< SC_T::TMRCTL0: SYNC Mask */ + +#define SC_TMRCTL1_CNT_Pos (0) /*!< SC_T::TMRCTL1: CNT Position */ +#define SC_TMRCTL1_CNT_Msk (0xfful << SC_TMRCTL1_CNT_Pos) /*!< SC_T::TMRCTL1: CNT Mask */ + +#define SC_TMRCTL1_OPMODE_Pos (24) /*!< SC_T::TMRCTL1: OPMODE Position */ +#define SC_TMRCTL1_OPMODE_Msk (0xful << SC_TMRCTL1_OPMODE_Pos) /*!< SC_T::TMRCTL1: OPMODE Mask */ + +#define SC_TMRCTL1_SYNC_Pos (31) /*!< SC_T::TMRCTL1: SYNC Position */ +#define SC_TMRCTL1_SYNC_Msk (0x1ul << SC_TMRCTL1_SYNC_Pos) /*!< SC_T::TMRCTL1: SYNC Mask */ + +#define SC_TMRCTL2_CNT_Pos (0) /*!< SC_T::TMRCTL2: CNT Position */ +#define SC_TMRCTL2_CNT_Msk (0xfful << SC_TMRCTL2_CNT_Pos) /*!< SC_T::TMRCTL2: CNT Mask */ + +#define SC_TMRCTL2_OPMODE_Pos (24) /*!< SC_T::TMRCTL2: OPMODE Position */ +#define SC_TMRCTL2_OPMODE_Msk (0xful << SC_TMRCTL2_OPMODE_Pos) /*!< SC_T::TMRCTL2: OPMODE Mask */ + +#define SC_TMRCTL2_SYNC_Pos (31) /*!< SC_T::TMRCTL2: SYNC Position */ +#define SC_TMRCTL2_SYNC_Msk (0x1ul << SC_TMRCTL2_SYNC_Pos) /*!< SC_T::TMRCTL2: SYNC Mask */ + +#define SC_UARTCTL_UARTEN_Pos (0) /*!< SC_T::UARTCTL: UARTEN Position */ +#define SC_UARTCTL_UARTEN_Msk (0x1ul << SC_UARTCTL_UARTEN_Pos) /*!< SC_T::UARTCTL: UARTEN Mask */ + +#define SC_UARTCTL_WLS_Pos (4) /*!< SC_T::UARTCTL: WLS Position */ +#define SC_UARTCTL_WLS_Msk (0x3ul << SC_UARTCTL_WLS_Pos) /*!< SC_T::UARTCTL: WLS Mask */ + +#define SC_UARTCTL_PBOFF_Pos (6) /*!< SC_T::UARTCTL: PBOFF Position */ +#define SC_UARTCTL_PBOFF_Msk (0x1ul << SC_UARTCTL_PBOFF_Pos) /*!< SC_T::UARTCTL: PBOFF Mask */ + +#define SC_UARTCTL_OPE_Pos (7) /*!< SC_T::UARTCTL: OPE Position */ +#define SC_UARTCTL_OPE_Msk (0x1ul << SC_UARTCTL_OPE_Pos) /*!< SC_T::UARTCTL: OPE Mask */ + +#define SC_ACTCTL_T1EXT_Pos (0) /*!< SC_T::ACTCTL: T1EXT Position */ +#define SC_ACTCTL_T1EXT_Msk (0x1ful << SC_ACTCTL_T1EXT_Pos) /*!< SC_T::ACTCTL: T1EXT Mask */ + +/**@}*/ /* SC_CONST */ +/**@}*/ /* end of SC register group */ +/**@}*/ /* end of REGISTER group */ + +#endif /* __SC_REG_H__ */ diff --git a/Ubiquitous/XiZi/board/nuvoton-m2354/third_party_driver/include/Regs/scu_reg.h b/Ubiquitous/XiZi/board/nuvoton-m2354/third_party_driver/include/Regs/scu_reg.h new file mode 100644 index 0000000..3ba0b96 --- /dev/null +++ b/Ubiquitous/XiZi/board/nuvoton-m2354/third_party_driver/include/Regs/scu_reg.h @@ -0,0 +1,2699 @@ +/**************************************************************************//** + * @file scu_reg.h + * @version V1.00 + * @brief SCU register definition header file + * + * @copyright SPDX-License-Identifier: Apache-2.0 + * @copyright Copyright (C) 2020 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ +#ifndef __SCU_REG_H__ +#define __SCU_REG_H__ + +/******************************************************************************/ +/* Device Specific Peripheral registers structures */ +/******************************************************************************/ + +/** @addtogroup REGISTER Control Register + + @{ + +*/ + + +/*---------------------- Booting Flag -------------------------*/ +/** + @addtogroup BTF Booting Flag + Memory Mapped Structure for BTF Controller + @{ +*/ + +typedef struct +{ + + + /** + * @var BTF_T::BTF + * Offset: 0x00 Booting Flag Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |BL2 |BL2 Flag + * | | |Indicating the CPU is running at BL2 + */ + __IO uint32_t BTF; /*!< [0x0000] Booting Flag Register */ + +} BTF_T; + +/** + @addtogroup BTF_CONST BTF Bit Field Definition + Constant Definitions for BTF Controller + @{ +*/ + +#define BTF_BTF_BL2_Pos (0) /*!< BTF_T::BTF: BL2 Position */ +#define BTF_BTF_BL2_Msk (0x1ul << BTF_BTF_BL2_Pos) /*!< BTF_T::BTF: BL2 Mask */ + +/**@}*/ /* BTF_CONST */ +/**@}*/ /* end of BTF register group */ + + +/*---------------------- Debug Protection Mechanism -------------------------*/ +/** + @addtogroup DPM Debug Protection Mechanism(DPM) + Memory Mapped Structure for DPM Controller + @{ +*/ + +typedef struct +{ + + + /** + * @var DPM_T::CTL + * Offset: 0x00 Secure DPM Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |DBGDIS |Set Secure DPM Debug Disable Bit + * | | |When this bit is read as zero, it can be write to one to configure the Secure DPM DBGDIS bit (DBGDISS). + * | | |When write: + * | | |0 = No operation. + * | | |1 = Trigger the process to set DBGDISS configuration bit. + * | | |Note: This bit can be set to 1 but cannot be cleared to 0. + * |[1] |LOCK |Set Secure DPM Debug Lock Bit + * | | |When this bit is read as zero, it can be write to one to configure the Secure DPM LOCK bit (LOCKS). + * | | |When write: + * | | |0 = No operation. + * | | |1 = Trigger the process to set LOCKS configuration bit. + * | | |Note: This bit can be set to 1 but cannot be cleared to 0. + * |[2] |PWCMP |Secure DPM Password Compare Bit + * | | |Set to enter the process of compare Secure DPM password. + * | | |0 = No operation. + * | | |1 = Compare Secure DPM password. + * | | |Note: This bit will be cleared after the comparison process is finished. + * |[3] |PWUPD |Secure DPM Password Update Bit + * | | |Set to enter the process of updating Secure DPM password. + * | | |0 = No operation. + * | | |1 = Update Secure DPM password. + * | | |Note 1: This bit should be set with PWCMP equal to 0. + * | | |Note 2: This bit will be cleared after the update process is finished. + * |[8] |INTEN |DPM Interrupt Enable Bit + * | | |0 = DPM interrupt function Enabled. + * | | |1 = DPM interrupt function Disabled. + * |[12] |DACCWDIS |Secure DPM Debug Write Access Disable Bit + * | | |This bit disables the writability of external debugger to Secure DPM registers for debug authentication. + * | | |0 = External debugger can write Secure DPM registers. + * | | |1 = External debugger cannot write Secure DPM registers. + * |[13] |DACCDIS |Debug Access Disable Bit + * | | |This bit disables the accessibility of external debugger to all DPM registers. + * | | |0 = External debugger can read/write DPM registers. + * | | |1 = External debugger cannot read/write DPM registers. + * |[31:24] |WVCODE |Write Verify Code and Read Verify Code + * | |RVCODE |Read operation: + * | | |0xA5 = The read access for DPM_CTL is correct. + * | | |Others = The read access for DPM_CTL is incorrect. + * | | |Write operation: + * | | |0x5A = The write verify code, 0x5A, is needed to do a valid write to DPM_CTL. + * | | |Others = Invalid write verify code. + * @var DPM_T::STS + * Offset: 0x04 Secure DPM Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |BUSY |DPM Busy Flag (Read Only) + * | | |This bit indicates the DPM is busy. + * | | |0 = DPM is not busy and writing to any register is accepted. + * | | |1 = DPM is busy and other bits in DPM_STS register are not valid and writing to any register is ignored. + * |[1] |INT |DPM Interrupt Flag (Read Only) + * | | |This bit indicates the interrupt is triggered. + * | | |0 = Interrupt is not enabled or no password comparison flag is set. + * | | |1 = Interrupt is enabled and PWCERR flag in either DPM_STS or DPM_NSSTS register is not cleared. + * | | |Note: This bit is cleared automatically when PWCERR flag in both DPM_STS and DPM_NSSTS are zero. + * |[4] |PWCERR |Secure DPM Password Compared Error Flag + * | | |This bit indicates the result of Secure DPM password comparison. + * | | |When read: + * | | |0 = The result of Secure DPM password is correct. + * | | |1 = The result of Seucre DPM password is incorrect. + * | | |Note: This flag is write-one-clear. + * |[5] |PWUOK |Secure DPM Password Updated Flag + * | | |This bit indicates Secure DPM password has been updated successfully. + * | | |When read: + * | | |0 = No successful updating process has happened. + * | | |1 = There is at least one successful updating process since last clearing of this bit. + * | | |Note: This flag is write-one-clear. + * |[6] |PWFMAX |Secure DPM Password Fail Times Maximum Reached Flag (Read Only) + * | | |This bit indicates if the fail times of comparing Secure DPM password reached max times. + * | | |0 = Max time has not reached and Secure DPM password comparison can be triggered. + * | | |1 = Max time reached and Secure DPM password comparison cannot be processed anymore. + * |[10:8] |PWUCNT |Secure DPM Password Updated Times (Read Only) + * | | |This bit indicates how many times of secure password has been updated. + * | | |The max value is 7. If PWUCNT reached the max value, Secure DPM password cannot be updated anymore. + * |[16] |DBGDIS |Secure Debug Disable Flag (Read Only) + * | | |This bit indicates the current value of Secure DPM DBGDIS bit (DBGDISS). + * | | |{PWOK, LOCK, DBGDIS} bits define the current state of DPM. + * | | |x00 = DEFAULT state. + * | | |x1x = LOCKED state. + * | | |001 = CLOSE state. + * | | |101 = OPEN state. + * | | |Others = Unknown. + * |[17] |LOCK |Secure Debug Lock Flag (Read Only) + * | | |This bit indicates the current value of Secure DPM LOCK bit (LOCKS). + * |[18] |PWOK |Secure Password OK Flag (Read Only) + * | | |This bit indicates the Secure DPM password has been checked and is correct. + * | | |0 = The Secure DPM password has not been checked pass, yet. + * | | |1 = The Secure DPM password has been checked pass since last cold reset. + * @var DPM_T::SPW + * Offset: 0x10 Secure DPM Password 0 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |PW |Password + * | | |Write password[31:0] to this register to update or compare Secure DPM password. + * | | |It is write-only and always read as 0xFFFFFFFF. + * Offset: 0x14 Secure DPM Password 1 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |PW |Password + * | | |Write password[63:32] to this register to update or compare Secure DPM password + * | | |It is write-only and always read as 0xFFFFFFFF. + * Offset: 0x18 Secure DPM Password 2 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |PW |Password + * | | |Write password[95:64] to this register to update or compare Secure DPM password. + * | | |It is write-only and always read as 0xFFFFFFFF. + * Offset: 0x1C Secure DPM Password 3 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |PW |Password + * | | |Write password[127:96] to this register to update or compare Secure DPM password. + * | | |It is write-only and always read as 0xFFFFFFFF. + * @var DPM_T::NSCTL + * Offset: 0x50 Non-secure DPM Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |DBGDIS |Set Non-secure DPM Debug Disable Bit + * | | |When this bit is read as zero, it can be write to one to configure the Non-secure DPM DBGDIS bit (DBGDISNS). + * | | |When write: + * | | |0 = No operation. + * | | |1 = Trigger the process to set DBGDISNS configuration bit. + * | | |Note: This bit can be set to 1 but cannot be cleared to 0. + * |[1] |LOCK |Set Non-secure DPM Debug Lock Bit + * | | |When this bit is read as zero, it can be write to one to configure the Non-secure DPM LOCK bit (LOCKNS). + * | | |When write: + * | | |0 = No operation. + * | | |1 = Trigger the process to set LOCKNS configuration bit. + * | | |Note: This bit can be set to 1 but cannot be cleared to 0. + * |[2] |PWCMP |Non-secure DPM Password Compare Bit + * | | |Set to enter the process of compare Non-secure DPM password. + * | | |0 = No operation. + * | | |1 = Compare Non-secure DPM password. + * | | |Note: This bit will be cleared after the comparison process is finished. + * |[3] |PWUPD |Non-secure DPM Password Update Bit + * | | |Set to enter the process of updating Non-secure DPM password. + * | | |0 = No operation. + * | | |1 = Update Non-secure DPM password. + * | | |Note 1: This bit should be set with PWCMP equal to 0. + * | | |Note 2: This bit will be cleared after the update process is finished. + * |[12] |DACCWDIS |Debug Write Access Disable Bit + * | | |This bit disables the writability of external debugger to Non-secure DPM registers for debug authentication. + * | | |0 = External debugger can write Non-secure DPM registers. + * | | |1 = External debugger cannot write Non-secure DPM registers. + * |[31:24] |WVCODE |Write Verify Code and Read Verify Code + * | |RVCODE |Read operation: + * | | |0xA5 = The read access for DPM_NSCTL is correct. + * | | |Others = The read access for DPM_NSCTL is incorrect. + * | | |Write operation: + * | | |0x5A = The write verify code, 0x5A, is needed to do a valid write to DPM_NSCTL. + * | | |Others = Invalid write verify code. + * @var DPM_T::NSSTS + * Offset: 0x54 Non-secure DPM Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |BUSY |DPM Busy Flag (Read Only) + * | | |This bit indicates the DPM is busy. + * | | |0 = DPM is not busy and writing to any register is accepted. + * | | |1 = DPM is busy and other bits in DPM_NSSTS register are not valid and writing to any register is ignored. + * |[4] |PWCERR |Non-secure DPM Password Compared Error Flag + * | | |This bit indicates the result of Non-secure DPM password comparison. + * | | |0 = The result of Non-secure DPM password is correct. + * | | |1 = The result of Non-seucre DPM password is incorrect. + * | | |Note: This flag is write-one-clear. + * |[5] |PWUOK |Non-secure DPM Password Updated Flag + * | | |This bit indicates Non-secure DPM password has been updated correctly. + * | | |When read: + * | | |0 = No successful updating process has happened. + * | | |1 = There is at least one successful updating process since last clearing of this bit. + * | | |Note: This flag is write-one-clear. + * |[6] |PWFMAX |Non-secure DPM Password Fail Times Maximum Reached Flag (Read Only) + * | | |This bit indicates if the fail times of comparing Non-secure DPM password reached max times. + * | | |0 = Max time has not reached and Non-secure DPM password comparison can be triggered. + * | | |1 = Max time reached and Non-secure DPM password comparison cannot be processed anymore. + * |[10:8] |PWUCNT |Non-secure DPM Password Updated Times (Read Only) + * | | |This bit indicates how many times of non-secure password has been updated. + * | | |The max value is 7. If PWUCNT reached the max value, Non-secure DPM password cannot be updated anymore. + * |[16] |DBGDIS |Non-secure Debug Disable Flag (Read Only) + * | | |This bit indicates the current value of of Non-secure DPM DBGDIS bit (DBGDISNS). + * | | |{PWOK, LOCK, DBGDIS} bits define the current state of DPM. + * | | |x00 = DEFAULT state. + * | | |x1x = LOCKED state. + * | | |001 = CLOSE state. + * | | |101 = OPEN state. + * | | |Others = Unknown. + * |[17] |LOCK |Non-secure Debug Lock Flag (Read Only) + * | | |This bit indicates the current value of Non-secure DPM DBGDIS bit (LOCKNS). + * |[18] |PWOK |Non-secure Password OK Flag (Read Only) + * | | |This bit indicates the Non-secure DPM password has been checked and is correct. + * | | |0 = The Non-secure DPM password has not been checked pass, yet. + * | | |1 = The Non-secure DPM password has been checked pass since last cold reset. + * @var DPM_T::NSPW + * Offset: 0x60 Non-secure DPM Password 0 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |PW |Password + * | | |Write password[31:0] to this register to update or compare Non-secure DPM password. + * | | |It is write-only and always read as 0xFFFFFFFF. + * Offset: 0x64 Non-secure DPM Password 1 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |PW |Password + * | | |Write password[63:32] to this register to update or compare Non-secure DPM password. + * | | |It is write-only and always read as 0xFFFFFFFF. + * Offset: 0x68 Non-secure DPM Password 2 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |PW |Password + * | | |Write password[95:64] to this register to update or compare Non-secure DPM password. + * | | |It is write-only and always read as 0xFFFFFFFF. + * Offset: 0x6C Non-secure DPM Password 3 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |PW |Password + * | | |Write password[127:96] to this register to update or compare Non-secure DPM password. + * | | |It is write-only and always read as 0xFFFFFFFF. + */ + __IO uint32_t CTL; /*!< [0x0000] Secure DPM Control Register */ + __IO uint32_t STS; /*!< [0x0004] Secure DPM Status Register */ + __I uint32_t RESERVE0[2]; + __O uint32_t SPW[4]; /*!< [0x0010/0x0014/0x0018/0x001c] Secure DPM Password 0/1/2/3 */ + __I uint32_t RESERVE1[12]; + __IO uint32_t NSCTL; /*!< [0x0050] Non-secure DPM Control Register */ + __IO uint32_t NSSTS; /*!< [0x0054] Non-secure DPM Status Register */ + __I uint32_t RESERVE2[2]; + __O uint32_t NSPW[4]; /*!< [0x00600/0x0064/0x0068/0x006c] Non-secure DPM Password 0/1/2/3 */ + + +} DPM_T; + +/** + @addtogroup DPM_CONST DPM Bit Field Definition + Constant Definitions for DPM Controller + @{ +*/ + +#define DPM_CTL_DBGDIS_Pos (0) /*!< DPM_T::CTL: DBGDIS Position */ +#define DPM_CTL_DBGDIS_Msk (0x1ul << DPM_CTL_DBGDIS_Pos) /*!< DPM_T::CTL: DBGDIS Mask */ + +#define DPM_CTL_LOCK_Pos (1) /*!< DPM_T::CTL: LOCK Position */ +#define DPM_CTL_LOCK_Msk (0x1ul << DPM_CTL_LOCK_Pos) /*!< DPM_T::CTL: LOCK Mask */ + +#define DPM_CTL_PWCMP_Pos (2) /*!< DPM_T::CTL: PWCMP Position */ +#define DPM_CTL_PWCMP_Msk (0x1ul << DPM_CTL_PWCMP_Pos) /*!< DPM_T::CTL: PWCMP Mask */ + +#define DPM_CTL_PWUPD_Pos (3) /*!< DPM_T::CTL: PWUPD Position */ +#define DPM_CTL_PWUPD_Msk (0x1ul << DPM_CTL_PWUPD_Pos) /*!< DPM_T::CTL: PWUPD Mask */ + +#define DPM_CTL_INTEN_Pos (8) /*!< DPM_T::CTL: INTEN Position */ +#define DPM_CTL_INTEN_Msk (0x1ul << DPM_CTL_INTEN_Pos) /*!< DPM_T::CTL: INTEN Mask */ + +#define DPM_CTL_DACCWDIS_Pos (12) /*!< DPM_T::CTL: DACCWDIS Position */ +#define DPM_CTL_DACCWDIS_Msk (0x1ul << DPM_CTL_DACCWDIS_Pos) /*!< DPM_T::CTL: DACCWDIS Mask */ + +#define DPM_CTL_DACCDIS_Pos (13) /*!< DPM_T::CTL: DACCDIS Position */ +#define DPM_CTL_DACCDIS_Msk (0x1ul << DPM_CTL_DACCDIS_Pos) /*!< DPM_T::CTL: DACCDIS Mask */ + +#define DPM_CTL_WVCODE_Pos (24) /*!< DPM_T::CTL: WVCODE Position */ +#define DPM_CTL_WVCODE_Msk (0xfful << DPM_CTL_WVCODE_Pos) /*!< DPM_T::CTL: WVCODE Mask */ + +#define DPM_CTL_RVCODE_Pos (24) /*!< DPM_T::CTL: RVCODE Position */ +#define DPM_CTL_RVCODE_Msk (0xfful << DPM_CTL_RVCODE_Pos) /*!< DPM_T::CTL: RVCODE Mask */ + +#define DPM_STS_BUSY_Pos (0) /*!< DPM_T::STS: BUSY Position */ +#define DPM_STS_BUSY_Msk (0x1ul << DPM_STS_BUSY_Pos) /*!< DPM_T::STS: BUSY Mask */ + +#define DPM_STS_INT_Pos (1) /*!< DPM_T::STS: INT Position */ +#define DPM_STS_INT_Msk (0x1ul << DPM_STS_INT_Pos) /*!< DPM_T::STS: INT Mask */ + +#define DPM_STS_PWCERR_Pos (4) /*!< DPM_T::STS: PWCERR Position */ +#define DPM_STS_PWCERR_Msk (0x1ul << DPM_STS_PWCERR_Pos) /*!< DPM_T::STS: PWCERR Mask */ + +#define DPM_STS_PWUOK_Pos (5) /*!< DPM_T::STS: PWUOK Position */ +#define DPM_STS_PWUOK_Msk (0x1ul << DPM_STS_PWUOK_Pos) /*!< DPM_T::STS: PWUOK Mask */ + +#define DPM_STS_PWFMAX_Pos (6) /*!< DPM_T::STS: PWFMAX Position */ +#define DPM_STS_PWFMAX_Msk (0x1ul << DPM_STS_PWFMAX_Pos) /*!< DPM_T::STS: PWFMAX Mask */ + +#define DPM_STS_PWUCNT_Pos (8) /*!< DPM_T::STS: PWUCNT Position */ +#define DPM_STS_PWUCNT_Msk (0x7ul << DPM_STS_PWUCNT_Pos) /*!< DPM_T::STS: PWUCNT Mask */ + +#define DPM_STS_DBGDIS_Pos (16) /*!< DPM_T::STS: DBGDIS Position */ +#define DPM_STS_DBGDIS_Msk (0x1ul << DPM_STS_DBGDIS_Pos) /*!< DPM_T::STS: DBGDIS Mask */ + +#define DPM_STS_LOCK_Pos (17) /*!< DPM_T::STS: LOCK Position */ +#define DPM_STS_LOCK_Msk (0x1ul << DPM_STS_LOCK_Pos) /*!< DPM_T::STS: LOCK Mask */ + +#define DPM_STS_PWOK_Pos (18) /*!< DPM_T::STS: PWOK Position */ +#define DPM_STS_PWOK_Msk (0x1ul << DPM_STS_PWOK_Pos) /*!< DPM_T::STS: PWOK Mask */ + +#define DPM_SPW0_PW_Pos (0) /*!< DPM_T::SPW0: PW Position */ +#define DPM_SPW0_PW_Msk (0xfffffffful << DPM_SPW0_PW_Pos) /*!< DPM_T::SPW0: PW Mask */ + +#define DPM_SPW1_PW_Pos (0) /*!< DPM_T::SPW1: PW Position */ +#define DPM_SPW1_PW_Msk (0xfffffffful << DPM_SPW1_PW_Pos) /*!< DPM_T::SPW1: PW Mask */ + +#define DPM_SPW2_PW_Pos (0) /*!< DPM_T::SPW2: PW Position */ +#define DPM_SPW2_PW_Msk (0xfffffffful << DPM_SPW2_PW_Pos) /*!< DPM_T::SPW2: PW Mask */ + +#define DPM_SPW3_PW_Pos (0) /*!< DPM_T::SPW3: PW Position */ +#define DPM_SPW3_PW_Msk (0xfffffffful << DPM_SPW3_PW_Pos) /*!< DPM_T::SPW3: PW Mask */ + +#define DPM_NSCTL_DBGDIS_Pos (0) /*!< DPM_T::NSCTL: DBGDIS Position */ +#define DPM_NSCTL_DBGDIS_Msk (0x1ul << DPM_NSCTL_DBGDIS_Pos) /*!< DPM_T::NSCTL: DBGDIS Mask */ + +#define DPM_NSCTL_LOCK_Pos (1) /*!< DPM_T::NSCTL: LOCK Position */ +#define DPM_NSCTL_LOCK_Msk (0x1ul << DPM_NSCTL_LOCK_Pos) /*!< DPM_T::NSCTL: LOCK Mask */ + +#define DPM_NSCTL_PWCMP_Pos (2) /*!< DPM_T::NSCTL: PWCMP Position */ +#define DPM_NSCTL_PWCMP_Msk (0x1ul << DPM_NSCTL_PWCMP_Pos) /*!< DPM_T::NSCTL: PWCMP Mask */ + +#define DPM_NSCTL_PWUPD_Pos (3) /*!< DPM_T::NSCTL: PWUPD Position */ +#define DPM_NSCTL_PWUPD_Msk (0x1ul << DPM_NSCTL_PWUPD_Pos) /*!< DPM_T::NSCTL: PWUPD Mask */ + +#define DPM_NSCTL_DACCWDIS_Pos (12) /*!< DPM_T::NSCTL: DACCWDIS Position */ +#define DPM_NSCTL_DACCWDIS_Msk (0x1ul << DPM_NSCTL_DACCWDIS_Pos) /*!< DPM_T::NSCTL: DACCWDIS Mask */ + +#define DPM_NSCTL_WVCODE_Pos (24) /*!< DPM_T::NSCTL: WVCODE Position */ +#define DPM_NSCTL_WVCODE_Msk (0xfful << DPM_NSCTL_WVCODE_Pos) /*!< DPM_T::NSCTL: WVCODE Mask */ + +#define DPM_NSCTL_RVCODE_Pos (24) /*!< DPM_T::NSCTL: RVCODE Position */ +#define DPM_NSCTL_RVCODE_Msk (0xfful << DPM_NSCTL_RVCODE_Pos) /*!< DPM_T::NSCTL: RVCODE Mask */ + +#define DPM_NSSTS_BUSY_Pos (0) /*!< DPM_T::NSSTS: BUSY Position */ +#define DPM_NSSTS_BUSY_Msk (0x1ul << DPM_NSSTS_BUSY_Pos) /*!< DPM_T::NSSTS: BUSY Mask */ + +#define DPM_NSSTS_PWCERR_Pos (4) /*!< DPM_T::NSSTS: PWCERR Position */ +#define DPM_NSSTS_PWCERR_Msk (0x1ul << DPM_NSSTS_PWCERR_Pos) /*!< DPM_T::NSSTS: PWCERR Mask */ + +#define DPM_NSSTS_PWUOK_Pos (5) /*!< DPM_T::NSSTS: PWUOK Position */ +#define DPM_NSSTS_PWUOK_Msk (0x1ul << DPM_NSSTS_PWUOK_Pos) /*!< DPM_T::NSSTS: PWUOK Mask */ + +#define DPM_NSSTS_PWFMAX_Pos (6) /*!< DPM_T::NSSTS: PWFMAX Position */ +#define DPM_NSSTS_PWFMAX_Msk (0x1ul << DPM_NSSTS_PWFMAX_Pos) /*!< DPM_T::NSSTS: PWFMAX Mask */ + +#define DPM_NSSTS_PWUCNT_Pos (8) /*!< DPM_T::NSSTS: PWUCNT Position */ +#define DPM_NSSTS_PWUCNT_Msk (0x7ul << DPM_NSSTS_PWUCNT_Pos) /*!< DPM_T::NSSTS: PWUCNT Mask */ + +#define DPM_NSSTS_DBGDIS_Pos (16) /*!< DPM_T::NSSTS: DBGDIS Position */ +#define DPM_NSSTS_DBGDIS_Msk (0x1ul << DPM_NSSTS_DBGDIS_Pos) /*!< DPM_T::NSSTS: DBGDIS Mask */ + +#define DPM_NSSTS_LOCK_Pos (17) /*!< DPM_T::NSSTS: LOCK Position */ +#define DPM_NSSTS_LOCK_Msk (0x1ul << DPM_NSSTS_LOCK_Pos) /*!< DPM_T::NSSTS: LOCK Mask */ + +#define DPM_NSSTS_PWOK_Pos (18) /*!< DPM_T::NSSTS: PWOK Position */ +#define DPM_NSSTS_PWOK_Msk (0x1ul << DPM_NSSTS_PWOK_Pos) /*!< DPM_T::NSSTS: PWOK Mask */ + +#define DPM_NSPW0_PW_Pos (0) /*!< DPM_T::NSPW0: PW Position */ +#define DPM_NSPW0_PW_Msk (0xfffffffful << DPM_NSPW0_PW_Pos) /*!< DPM_T::NSPW0: PW Mask */ + +#define DPM_NSPW1_PW_Pos (0) /*!< DPM_T::NSPW1: PW Position */ +#define DPM_NSPW1_PW_Msk (0xfffffffful << DPM_NSPW1_PW_Pos) /*!< DPM_T::NSPW1: PW Mask */ + +#define DPM_NSPW2_PW_Pos (0) /*!< DPM_T::NSPW2: PW Position */ +#define DPM_NSPW2_PW_Msk (0xfffffffful << DPM_NSPW2_PW_Pos) /*!< DPM_T::NSPW2: PW Mask */ + +#define DPM_NSPW3_PW_Pos (0) /*!< DPM_T::NSPW3: PW Position */ +#define DPM_NSPW3_PW_Msk (0xfffffffful << DPM_NSPW3_PW_Pos) /*!< DPM_T::NSPW3: PW Mask */ + + +/**@}*/ /* DPM_CONST */ +/**@}*/ /* end of DPM register group */ + + + +/*---------------------- Firmware Version Counter -------------------------*/ +/** + @addtogroup FVC Firmware Version Counter(FVC) + Memory Mapped Structure for FVC Controller +@{ */ + +typedef struct +{ + + + /** + * @var FVC_T::CTL + * Offset: 0x00 FVC Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |INIT |FVC Init Bit + * | | |Set to 1 to enable FVC + * | | |This bit is writable when FVC is at Reset state. + * | | |Note: After set to 1, this bit is cleared to 0 automatically when FVC is back to Reset state. + * |[1] |MONOEN |Monotonic Enable Bit + * | | |Set to 1 to enable the monotonic mechanism of FVC. + * | | |Note: This bit can be set to1 but cannot be cleared to 0. + * |[31:16] |WVCODE |Verification Code + * | | |When written, this field must be 0x7710 + * @var FVC_T::STS + * Offset: 0x04 FVC Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |BUSY |FVC Busy Bit + * | | |Indicates the FVC is at busy state. + * |[1] |RDY |FVC Ready Bit + * | | |Indicates the FVC is ready after the initial process. + * @var FVC_T::NVC0 + * Offset: 0x10 Non-volatile Version Counter Control Register0 BL2 Firmware + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |FWVER |Firmware Version + * | | |Read: Indicates the current firmware version of FVC0. + * | | |Write: Updates the firmware version of FVC0. + * | | |The maximum value of this field is 63. + * | | |Indicating number of 1 in Fuse OTP or number of 0 in Flash + * |[31:16] |WVCODE |Verification Code + * | | |When written, this field must be the current firmware version number + * @var FVC_T::NVC1 + * Offset: 0x14 Non-volatile Version Counter Control Register1 BL32 Firmware + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |FWVER |Firmware Version + * | | |Read: Indicates the current firmware version of NVC1. + * | | |Write: Updates the firmware version of NVC1. + * | | |The maximum value of this field is 63. + * | | |Indicating number of 1 in Fuse OTP or number of 0 in Flash + * |[31:16] |WVCODE |Verification Code + * | | |When written, this field must be the current firmware version number + * @var FVC_T::NVC4 + * Offset: 0x20 Non-volatile Version Counter Control Register4 BL33 Firmware + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |FWVER |Firmware Version + * | | |Read: Indicates the current firmware version of NVC4. + * | | |Write: Updates the firmware version of NVC4. + * | | |The maximum value of this field is 255. + * | | |Indicating number of 1 in Fuse OTP or number of 0 in Flash + * |[31:16] |WVCODE |Verification Code + * | | |When written, this field must be the current firmware version number + * @var FVC_T::NVC5 + * Offset: 0x24 Non-volatile Version Counter Control Register5 User-defined Firmware + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |FWVER |Firmware Version + * | | |Read: Indicates the current firmware version of NVC5. + * | | |Write: Updates the firmware version of NVC5. + * | | |The maximum value of this field is 255. + * | | |Indicating number of 1 in Fuse OTP or number of 0 in Flash + * |[31:16] |WVCODE |Verification Code + * | | |When written, this field must be the current firmware version number + */ + __IO uint32_t CTL; /*!< [0x0000] FVC Control Register */ + __I uint32_t STS; /*!< [0x0004] FVC Status Register */ + __I uint32_t RESERVE0[2]; + __IO uint32_t NVC[6]; /*!< [0x0010-0x24] Non-volatile Version Counter Control Register Firmware. NVC[2], NVC[3] is reserved */ +} FVC_T; + +/** + @addtogroup FVC_CONST FVC Bit Field Definition + Constant Definitions for FVC Controller +@{ */ + +#define FVC_CTL_INIT_Pos (0) /*!< FVC_T::CTL: INIT Position */ +#define FVC_CTL_INIT_Msk (0x1ul << FVC_CTL_INIT_Pos) /*!< FVC_T::CTL: INIT Mask */ + +#define FVC_CTL_MONOEN_Pos (1) /*!< FVC_T::CTL: MONOEN Position */ +#define FVC_CTL_MONOEN_Msk (0x1ul << FVC_CTL_MONOEN_Pos) /*!< FVC_T::CTL: MONOEN Mask */ + +#define FVC_CTL_WVCODE_Pos (16) /*!< FVC_T::CTL: WVCODE Position */ +#define FVC_CTL_WVCODE_Msk (0xfffful << FVC_CTL_WVCODE_Pos) /*!< FVC_T::CTL: WVCODE Mask */ + +#define FVC_STS_BUSY_Pos (0) /*!< FVC_T::STS: BUSY Position */ +#define FVC_STS_BUSY_Msk (0x1ul << FVC_STS_BUSY_Pos) /*!< FVC_T::STS: BUSY Mask */ + +#define FVC_STS_RDY_Pos (1) /*!< FVC_T::STS: RDY Position */ +#define FVC_STS_RDY_Msk (0x1ul << FVC_STS_RDY_Pos) /*!< FVC_T::STS: RDY Mask */ + +#define FVC_NVC_FWVER_Pos (0) /*!< FVC_T::NVC: FWVER Position */ +#define FVC_NVC_FWVER_Msk (0xfffful << FVC_NVC_FWVER_Pos) /*!< FVC_T::NVC: FWVER Mask */ + +/**@}*/ /* FVC_CONST */ +/**@}*/ /* end of FVC register group */ + + +/*---------------------- Product Life-cycle Manager -------------------------*/ +/** + @addtogroup PLM Product Life-cycle Manager(PLM) + Memory Mapped Structure for PLM Controller + @{ +*/ + +typedef struct +{ + + + /** + * @var PLM_T::CTL + * Offset: 0x00 Product Life-cycle Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[2:0] |STAGE |Life-cycle Stage Update Bits + * | | |Bits to update PLM stage. All bits can be set to one but cannot be cleared to zero. + * | | |001 = progress to OEM stage. + * | | |011 = progress to Deployed stage. + * | | |111 = progress to RMA stage. + * | | |Other value will be ignored. + * |[31:16] |WVCODE |Write Verify Code + * | | |The code is 0x475A for a valid write to this register. + * @var PLM_T::STS + * Offset: 0x04 Product Life-cycle Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[2:0] |STAGE |Life-cycle Stage (Read Only) + * | | |Indicates the current stage of PLM. + * | | |000 = Vendor Stage. + * | | |001 = OEM Stage. + * | | |011 = Deployed Stage. + * | | |111 = RMA Stage. + * | | |Others = ERROR Stage. + * |[8] |DIRTY |DIRTY Bit (Read Only) + * | | |Indicate the life-cycle stage has been progressed after last cold-reset + * | | |Value of STAGE bits is not Current stage of PLM + * | | |It needs a cold reset to make it work. + */ + __IO uint32_t CTL; /*!< [0x0000] Product Life-cycle Control Register */ + __I uint32_t STS; /*!< [0x0004] Product Life-cycle Status Register */ + +} PLM_T; + +/** + @addtogroup PLM_CONST PLM Bit Field Definition + Constant Definitions for PLM Controller + @{ +*/ + +#define PLM_CTL_STAGE_Pos (0) /*!< PLM_T::CTL: STAGE Position */ +#define PLM_CTL_STAGE_Msk (0x7ul << PLM_CTL_STAGE_Pos) /*!< PLM_T::CTL: STAGE Mask */ + +#define PLM_CTL_WVCODE_Pos (16) /*!< PLM_T::CTL: WVCODE Position */ +#define PLM_CTL_WVCODE_Msk (0xfffful << PLM_CTL_WVCODE_Pos) /*!< PLM_T::CTL: WVCODE Mask */ + +#define PLM_STS_STAGE_Pos (0) /*!< PLM_T::STS: STAGE Position */ +#define PLM_STS_STAGE_Msk (0x7ul << PLM_STS_STAGE_Pos) /*!< PLM_T::STS: STAGE Mask */ + +#define PLM_STS_DIRTY_Pos (8) /*!< PLM_T::STS: DIRTY Position */ +#define PLM_STS_DIRTY_Msk (0x1ul << PLM_STS_DIRTY_Pos) /*!< PLM_T::STS: DIRTY Mask */ + +/**@}*/ /* PLM_CONST */ +/**@}*/ /* end of PLM register group */ + + +/*---------------------- Secure configuration Unit -------------------------*/ +/** + @addtogroup SCU Secure configuration Unit(SCU) + Memory Mapped Structure for SCU Controller + @{ +*/ + +typedef struct +{ + + + /** + * @var SCU_T::PNSSET + * Offset: 0x00 Peripheral Non-secure Attribution Set Register0 (0x4000_0000~0x4001_FFFF) + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[9] |USBH |Set USBH to Non-secure State + * | | |Write 1 to set USBH to non-secure state. Write 0 has no effect. + * | | |0 = USBH is a secure module (default). + * | | |1 = USBH is a non-secure module. + * |[13] |SDH0 |Set SDH0 to Non-secure State + * | | |Write 1 to set SDH0 to non-secure state. Write 0 has no effect. + * | | |0 = SDH0 is a secure module (default). + * | | |1 = SDH0 is a non-secure module. + * |[16] |EBI |Set EBI to Non-secure State + * | | |Write 1 to set EBI to non-secure state. Write 0 has no effect. + * | | |0 = EBI is a secure module (default). + * | | |1 = EBI is a non-secure module. + * |[24] |PDMA1 |Set PDMA1 to Non-secure State + * | | |Write 1 to set PDMA1 to non-secure state. Write 0 has no effect. + * | | |0 = PDMA1 is a secure module (default). + * | | |1 = PDMA1 is a non-secure module. + * Offset: 0x04 Peripheral Non-secure Attribution Set Register1 (0x4002_0000~0x4003_FFFF) + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[17] |CRC |Set CRC to Non-secure State + * | | |Write 1 to set CRC to non-secure state. Write 0 has no effect. + * | | |0 = CRC is a secure module (default). + * | | |1 = CRC is a non-secure module. + * |[18] |CRPT |Set CRPT to Non-secure State + * | | |0 = CRPT is a secure module (default). + * | | |1 = CRPT is a non-secure module. + * Offset: 0x08 Peripheral Non-secure Attribution Set Register2 (0x4004_0000~0x4005_FFFF) + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[2] |EWDT |Set EWDT to Non-secure State + * | | |Write 1 to set EWDT to non-secure state. Write 0 has no effect. + * | | |0 = EWDT is a secure module (default). + * | | |1 = EWDT is a non-secure module. + * |[3] |EADC |Set EADC to Non-secure State + * | | |Write 1 to set EADC to non-secure state. Write 0 has no effect. + * | | |0 = EADC is a secure module (default). + * | | |1 = EADC is a non-secure module. + * |[5] |ACMP01 |Set ACMP01 to Non-secure State + * | | |Write 1 to set ACMP0, ACMP1 to non-secure state. Write 0 has no effect. + * | | |0 = ACMP0, ACMP1 are secure modules (default). + * | | |1 = ACMP0, ACMP1 are non-secure modules. + * |[7] |DAC |Set DAC to Non-secure State + * | | |Write 1 to set DAC to non-secure state. Write 0 has no effect. + * | | |0 = DAC is a secure module (default). + * | | |1 = DAC is a non-secure module. + * |[8] |I2S0 |Set I2S0 to Non-secure State + * | | |Write 1 to set I2S0 to non-secure state. Write 0 has no effect. + * | | |0 = I2S0 is a secure module (default). + * | | |1 = I2S0 is a non-secure module. + * |[13] |OTG |Set OTG to Non-secure State + * | | |Write 1 to set OTG to non-secure state. Write 0 has no effect. + * | | |0 = OTG is a secure module (default). + * | | |1 = OTG is a non-secure module. + * |[17] |TMR23 |Set TMR23 to Non-secure State + * | | |Write 1 to set TMR23 to non-secure state. Write 0 has no effect. + * | | |0 = TMR23 is a secure module (default). + * | | |1 = TMR23 is a non-secure module. + * |[24] |EPWM0 |Set EPWM0 to Non-secure State + * | | |Write 1 to set EPWM0 to non-secure state. Write 0 has no effect. + * | | |0 = EPWM0 is a secure module (default). + * | | |1 = EPWM0 is a non-secure module. + * |[25] |EPWM1 |Set EPWM1 to Non-secure State + * | | |Write 1 to set EPWM1 to non-secure state. Write 0 has no effect. + * | | |0 = EPWM1 is a secure module (default). + * | | |1 = EPWM1 is a non-secure module. + * |[26] |BPWM0 |Set BPWM0 to Non-secure State + * | | |Write 1 to set BPWM0 to non-secure state. Write 0 has no effect. + * | | |0 = BPWM0 is a secure module (default). + * | | |1 = BPWM0 is a non-secure module. + * |[27] |BPWM1 |Set BPWM1 to Non-secure State + * | | |Write 1 to set BPWM1 to non-secure state. Write 0 has no effect. + * | | |0 = BPWM1 is a secure module (default). + * | | |1 = BPWM1 is a non-secure module. + * Offset: 0x0C Peripheral Non-secure Attribution Set Register3 (0x4006_0000~0x4007_FFFF) + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |QSPI0 |Set QSPI0 to Non-secure State + * | | |Write 1 to set QSPI0 to non-secure state. Write 0 has no effect. + * | | |0 = QSPI0 is a secure module (default). + * | | |1 = QSPI0 is a non-secure module. + * |[1] |SPI0 |Set SPI0 to Non-secure State + * | | |Write 1 to set SPI0 to non-secure state. Write 0 has no effect. + * | | |0 = SPI0 is a secure module (default). + * | | |1 = SPI0 is a non-secure module. + * |[2] |SPI1 |Set SPI1 to Non-secure State + * | | |Write 1 to set SPI1 to non-secure state. Write 0 has no effect. + * | | |0 = SPI1 is a secure module (default). + * | | |1 = SPI1 is a non-secure module. + * |[3] |SPI2 |Set SPI2 to Non-secure State + * | | |Write 1 to set SPI2 to non-secure state. Write 0 has no effect. + * | | |0 = SPI2 is a secure module (default). + * | | |1 = SPI2 is a non-secure module. + * |[4] |SPI3 |Set SPI3 to Non-secure State + * | | |Write 1 to set SPI3 to non-secure state. Write 0 has no effect. + * | | |0 = SPI3 is a secure module (default). + * | | |1 = SPI3 is a non-secure module. + * |[16] |UART0 |Set UART0 to Non-secure State + * | | |Write 1 to set UART0 to non-secure state. Write 0 has no effect. + * | | |0 = UART0 is a secure module (default). + * | | |1 = UART0 is a non-secure module. + * |[17] |UART1 |Set UART1 to Non-secure State + * | | |Write 1 to set UART1 to non-secure state. Write 0 has no effect. + * | | |0 = UART1 is a secure module (default). + * | | |1 = UART1 is a non-secure module. + * |[18] |UART2 |Set UART2 to Non-secure State + * | | |Write 1 to set UART2 to non-secure state. Write 0 has no effect. + * | | |0 = UART2 is a secure module (default). + * | | |1 = UART2 is a non-secure module. + * |[19] |UART3 |Set UART3 to Non-secure State + * | | |Write 1 to set UART3 to non-secure state. Write 0 has no effect. + * | | |0 = UART3 is a secure module (default). + * | | |1 = UART3 is a non-secure module. + * |[20] |UART4 |Set UART4 to Non-secure State + * | | |Write 1 to set UART4 to non-secure state. Write 0 has no effect. + * | | |0 = UART4 is a secure module (default). + * | | |1 = UART4 is a non-secure module. + * |[21] |UART5 |Set UART5 to Non-secure State + * | | |Write 1 to set UART5 to non-secure state. Write 0 has no effect. + * | | |0 = UART5 is a secure module (default). + * | | |1 = UART5 is a non-secure module. + * Offset: 0x10 Peripheral Non-secure Attribution Set Register4 (0x4008_0000~0x4009_FFFF) + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |I2C0 |Set I2C0 to Non-secure State + * | | |Write 1 to set I2C0 to non-secure state. Write 0 has no effect. + * | | |0 = I2C0 is a secure module (default). + * | | |1 = I2C0 is a non-secure module. + * |[1] |I2C1 |Set I2C1 to Non-secure State + * | | |Write 1 to set I2C1 to non-secure state. Write 0 has no effect. + * | | |0 = I2C1 is a secure module (default). + * | | |1 = I2C1 is a non-secure module. + * |[2] |I2C2 |Set I2C2 to Non-secure State + * | | |Write 1 to set I2C2 to non-secure state. Write 0 has no effect. + * | | |0 = I2C2 is a secure module (default). + * | | |1 = I2C2 is a non-secure module. + * |[16] |SC0 |Set SC0 to Non-secure State + * | | |Write 1 to set SC0 to non-secure state. Write 0 has no effect. + * | | |0 = SC0 is a secure module (default). + * | | |1 = SC0 is a non-secure module. + * |[17] |SC1 |Set SC1 to Non-secure State + * | | |Write 1 to set SC1 to non-secure state. Write 0 has no effect. + * | | |0 = SC1 is a secure module (default). + * | | |1 = SC1 is a non-secure module. + * |[18] |SC2 |Set SC2 to Non-secure State + * | | |Write 1 to set SC2 to non-secure state. Write 0 has no effect. + * | | |0 = SC2 is a secure module (default). + * | | |1 = SC2 is a non-secure module. + * Offset: 0x14 Peripheral Non-secure Attribution Set Register5 (0x400A_0000~0x400B_FFFF) + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |CAN0 |Set CAN0 to Non-secure State + * | | |Write 1 to set CAN0 to non-secure state. Write 0 has no effect. + * | | |0 = CAN0 is a secure module (default). + * | | |1 = CAN0 is a non-secure module. + * |[16] |QEI0 |Set QEI0 to Non-secure State + * | | |Write 1 to set QEI0 to non-secure state. Write 0 has no effect. + * | | |0 = QEI0 is a secure module (default). + * | | |1 = QEI0 is a non-secure module. + * |[17] |QEI1 |Set QEI1 to Non-secure State + * | | |Write 1 to set QEI1 to non-secure state. Write 0 has no effect. + * | | |0 = QEI1 is a secure module (default). + * | | |1 = QEI1 is a non-secure module. + * |[20] |ECAP0 |Set ECAP0 to Non-secure State + * | | |Write 1 to set ECAP0 to non-secure state. Write 0 has no effect. + * | | |0 = ECAP0 is a secure module (default). + * | | |1 = ECAP0 is a non-secure module. + * |[21] |ECAP1 |Set ECAP1 to Non-secure State + * | | |Write 1 to set ECAP1 to non-secure state. Write 0 has no effect. + * | | |0 = ECAP1 is a secure module (default). + * | | |1 = ECAP1 is a non-secure module. + * |[25] |TRNG |Set TRNG to Non-secure State + * | | |Write 1 to set TRNG to non-secure state. Write 0 has no effect. + * | | |0 = TRNG is a secure module (default). + * | | |1 = TRNG is a non-secure module. + * |[27] |LCD |Set LCD to Non-secure State + * | | |Write 1 to set LCD to non-secure state. Write 0 has no effect. + * | | |0 = LCD is a secure module (default). + * | | |1 = LCD is a non-secure module. + * Offset: 0x18 Peripheral Non-secure Attribution Set Register6 (0x400C_0000~0x400D_FFFF) + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |USBD |Set USBD to Non-secure State + * | | |Write 1 to set USBD to non-secure state. Write 0 has no effect. + * | | |0 = USBD is a secure module (default). + * | | |1 = USBD is a non-secure module. + * |[16] |USCI0 |Set USCI0 to Non-secure State + * | | |Write 1 to set USCI0 to non-secure state. Write 0 has no effect. + * | | |0 = USCI0 is a secure module (default). + * | | |1 = USCI0 is a non-secure module. + * |[17] |USCI1 |Set USCI1 to Non-secure State + * | | |Write 1 to set USCI1 to non-secure state. Write 0 has no effect. + * | | |0 = USCI1 is a secure module (default). + * | | |1 = USCI1 is a non-secure module. + * @var SCU_T::IONSSET + * Offset: 0x20 IO Non-secure Attribution Set Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |PA |Set GPIO Port a to Non-scecure State + * | | |Write 1 to set PA to non-secure state. Write 0 has no effect. + * | | |0 = GPIO port A is secure (default). + * | | |1 = GPIO port A is non-secure. + * |[1] |PB |Set GPIO Port B to Non-scecure State + * | | |Write 1 to set PB to non-secure state. Write 0 has no effect. + * | | |0 = GPIO port B is secure (default). + * | | |1 = GPIO port B is non-secure. + * |[2] |PC |Set GPIO Port C to Non-scecure State + * | | |Write 1 to set PC to non-secure state. Write 0 has no effect. + * | | |0 = GPIO port C is secure (default). + * | | |1 = GPIO port C is non-secure. + * |[3] |PD |Set GPIO Port D to Non-scecure State + * | | |Write 1 to set PD to non-secure state. Write 0 has no effect. + * | | |0 = GPIO port D is secure (default). + * | | |1 = GPIO port D is non-secure. + * |[4] |PE |Set GPIO Port E to Non-scecure State + * | | |Write 1 to set PE to non-secure state. Write 0 has no effect. + * | | |0 = GPIO port E is secure (default). + * | | |1 = GPIO port E is non-secure. + * |[5] |PF |Set GPIO Port F to Non-scecure State + * | | |Write 1 to set PF to non-secure state. Write 0 has no effect. + * | | |0 = GPIO port F is secure (default). + * | | |1 = GPIO port F is non-secure. + * |[6] |PG |Set GPIO Port G to Non-scecure State + * | | |Write 1 to set PG to non-secure state. Write 0 has no effect. + * | | |0 = GPIO port G is secure (default). + * | | |1 = GPIO port G is non-secure. + * |[7] |PH |Set GPIO Port H to Non-scecure State + * | | |Write 1 to set PH to non-secure state. Write 0 has no effect. + * | | |0 = GPIO port H is secure (default). + * | | |1 = GPIO port H is non-secure. + * @var SCU_T::SRAMNSSET + * Offset: 0x24 SRAM Non-secure Attribution Set Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[11:0] |SECn |Set SRAM Section n to Non-scecure State + * | | |Write 1 to set SRAM section n to non-secure state. Write 0 is ignored. + * | | |0 = SRAM Section n is secure (default). + * | | |1 = SRAM Section n is non-secure. + * | | |Size per section is 16 Kbytes. + * | | |Secure SRAM section n is 0x2000_0000+0x4000*n to 0x2000_0000+0x4000*(n+1)-0x1 + * | | |Non-secure SRAM section n is 0x3000_0000+0x4000*n to 0x3000_0000+0x4000*(n+1)-0x1 + * @var SCU_T::FNSADDR + * Offset: 0x28 Flash Non-secure Boundary Address Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |FNSADDR |Flash Non-secure Boundary Address + * | | |Indicate the base address of Non-secure region set in user configuration + * | | |Refer to FMC section for more details. + * @var SCU_T::SVIOIEN + * Offset: 0x2C Security Violation Interrupt Enable Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |APB0IEN |APB0 Security Violation Interrupt Enable Bit + * | | |0 = Interrupt triggered from security violation of APB0 Disabled. + * | | |1 = Interrupt triggered from security violation of APB0 Enabled. + * |[1] |APB1IEN |APB1 Security Violation Interrupt Enable Bit + * | | |0 = Interrupt triggered from security violation of APB1 Disabled. + * | | |1 = Interrupt triggered from security violation of APB1 Enabled. + * |[4] |GPIOIEN |GPIO Security Violation Interrupt Enable Bit + * | | |0 = Interrupt triggered from security violation of GPIO Disabled. + * | | |1 = Interrupt triggered from security violation of GPIO Enabled. + * |[5] |EBIIEN |EBI Security Violation Interrupt Enable Bit + * | | |0 = Interrupt triggered from security violation of EBI Disabled. + * | | |1 = Interrupt triggered from security violation of EBI Enabled. + * |[6] |USBHIEN |USBH Security Violation Interrupt Enable Bit + * | | |0 = Interrupt triggered from security violation of USB host Disabled. + * | | |1 = Interrupt triggered from security violation of USB host Enabled. + * |[7] |CRCIEN |CRC Security Violation Interrupt Enable Bit + * | | |0 = Interrupt triggered from security violation of CRC Disabled. + * | | |1 = Interrupt triggered from security violation of CRC Enabled. + * |[8] |SDH0IEN |SDH0 Security Violation Interrupt Enable Bit + * | | |0 = Interrupt triggered from security violation of SD host 0 Disabled. + * | | |1 = Interrupt triggered from security violation of SD host 0 Enabled. + * |[10] |PDMA0IEN |PDMA0 Security Violation Interrupt Enable Bit + * | | |0 = Interrupt triggered from security violation of PDMA0 Disabled. + * | | |1 = Interrupt triggered from security violation of PDMA0 Enabled. + * |[11] |PDMA1IEN |PDMA1 Security Violation Interrupt Enable Bit + * | | |0 = Interrupt triggered from security violation of PDMA1 Disabled. + * | | |1 = Interrupt triggered from security violation of PDMA1 Enabled. + * |[12] |SRAM0IEN |SRAM Bank 0 Security Violation Interrupt Enable Bit + * | | |0 = Interrupt triggered from security violation of SRAM bank0 Disabled. + * | | |1 = Interrupt triggered from security violation of SRAM bank0 Enabled. + * |[13] |SRAM1IEN |SRAM Bank 1 Security Violation Interrupt Enable Bit + * | | |0 = Interrupt triggered from security violation of SRAM bank1 Disabled. + * | | |1 = Interrupt triggered from security violation of SRAM bank1 Enabled. + * |[14] |FMCIEN |FMC Security Violation Interrupt Enable Bit + * | | |0 = Interrupt triggered from security violation of FMC Disabled. + * | | |1 = Interrupt triggered from security violation of FMC Enabled. + * |[15] |FLASHIEN |FLASH Security Violation Interrupt Enable Bit + * | | |0 = Interrupt triggered from security violation of Flash data Disabled. + * | | |1 = Interrupt triggered from security violation of Flash data Enabled. + * |[16] |SCUIEN |SCU Security Violation Interrupt Enable Bit + * | | |0 = Interrupt triggered from security violation of SCU Disabled. + * | | |1 = Interrupt triggered from security violation of SCU Enabled. + * |[17] |SYSIEN |SYS Security Violation Interrupt Enable Bit + * | | |0 = Interrupt triggered from security violation of system manager Disabled. + * | | |1 = Interrupt triggered from security violation of system manager Enabled. + * |[18] |CRPTIEN |CRPT Security Violation Interrupt Enable Bit + * | | |0 = Interrupt triggered from security violation of crypto Disabled. + * | | |1 = Interrupt triggered from security violation of crypto Enabled. + * |[19] |KSIEN |KS Security Violation Interrupt Enable Bit + * | | |0 = Interrupt triggered from security violation of keystore Disabled. + * | | |1 = Interrupt triggered from security violation of keystore Enabled. + * @var SCU_T::SVINTSTS + * Offset: 0x30 Security Violation Interrupt Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |APB0IF |APB0 Security Violation Interrupt Status + * | | |0 = No APB0 violation interrupt event. + * | | |1 = There is APB0 violation interrupt event. + * | | |Note: Write 1 to clear the interrupt flag. + * |[1] |APB1IF |APB1 Security Violation Interrupt Status + * | | |0 = No APB1 violation interrupt event. + * | | |1 = There is APB1 violation interrupt event. + * | | |Note: Write 1 to clear the interrupt flag. + * |[4] |GPIOIF |GPIO Security Violation Interrupt Status + * | | |0 = No GPIO violation interrupt event. + * | | |1 = There is GPIO violation interrupt event. + * | | |Note: Write 1 to clear the interrupt flag. + * |[5] |EBIIF |EBI Security Violation Interrupt Status + * | | |0 = No EBI violation interrupt event. + * | | |1 = There is EBI violation interrupt event. + * | | |Note: Write 1 to clear the interrupt flag. + * |[6] |USBHIF |USBH Security Violation Interrupt Status + * | | |0 = No USBH violation interrupt event. + * | | |1 = There is USBH violation interrupt event. + * | | |Note: Write 1 to clear the interrupt flag. + * |[7] |CRCIF |CRC Security Violation Interrupt Status + * | | |0 = No CRC violation interrupt event. + * | | |1 = There is CRC violation interrupt event. + * | | |Note: Write 1 to clear the interrupt flag. + * |[8] |SDH0IF |SDH0 Security Violation Interrupt Status + * | | |0 = No SDH0 violation interrupt event. + * | | |1 = There is SDH0 violation interrupt event. + * | | |Note: Write 1 to clear the interrupt flag. + * |[10] |PDMA0IF |PDMA0 Security Violation Interrupt Status + * | | |0 = No PDMA0 violation interrupt event. + * | | |1 = There is PDMA0 violation interrupt event. + * | | |Note: Write 1 to clear the interrupt flag. + * |[11] |PDMA1IF |PDMA1 Security Violation Interrupt Status + * | | |0 = No PDMA1 violation interrupt event. + * | | |1 = There is PDMA1 violation interrupt event. + * | | |Note: Write 1 to clear the interrupt flag. + * |[12] |SRAM0IF |SRAM0 Security Violation Interrupt Status + * | | |0 = No SRAM0 violation interrupt event. + * | | |1 = There is SRAM0 violation interrupt event. + * | | |Note: Write 1 to clear the interrupt flag. + * |[13] |SRAM1IF |SRAM Bank 1 Security Violation Interrupt Status + * | | |0 = No SRAM1 violation interrupt event. + * | | |1 = There is SRAM1 violation interrupt event. + * | | |Note: Write 1 to clear the interrupt flag. + * |[14] |FMCIF |FMC Security Violation Interrupt Status + * | | |0 = No FMC violation interrupt event. + * | | |1 = There is FMC violation interrupt event. + * | | |Note: Write 1 to clear the interrupt flag. + * |[15] |FLASHIF |FLASH Security Violation Interrupt Status + * | | |0 = No FLASH violation interrupt event. + * | | |1 = There is FLASH violation interrupt event. + * | | |Note: Write 1 to clear the interrupt flag. + * |[16] |SCUIF |SCU Security Violation Interrupt Status + * | | |0 = No SCU violation interrupt event. + * | | |1 = There is SCU violation interrupt event. + * | | |Note: Write 1 to clear the interrupt flag. + * |[17] |SYSIF |SYS Security Violation Interrupt Status + * | | |0 = No SYS violation interrupt event. + * | | |1 = There is SYS violation interrupt event. + * | | |Note: Write 1 to clear the interrupt flag. + * |[18] |CRPTIF |CRPT Security Violation Interrupt Status + * | | |0 = No CRPT violation interrupt event. + * | | |1 = There is CRPT violation interrupt event. + * | | |Note: Write 1 to clear the interrupt flag. + * |[19] |KSIF |KS Security Violation Interrupt Status + * | | |0 = No KS violation interrupt event. + * | | |1 = There is KS violation interrupt event. + * | | |Note: Write 1 to clear the interrupt flag. + * @var SCU_T::APB0VSRC + * Offset: 0x34 APB0 Security Policy Violation Source + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[3:0] |MASTER |Master Violating Security Policy + * | | |Indicate which master invokes the security violation. + * | | |0x0 = core processor. + * | | |0x3 = PDMA0. + * | | |0x4 = SDH0. + * | | |0x5 = CRYPTO. + * | | |0x6 = USH. + * | | |0xB = PDMA1. + * | | |Others is undefined. + * @var SCU_T::APB0VA + * Offset: 0x38 APB0 Violation Address + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |VIOADDR |Violation Address + * | | |Indicate the target address of the access, which invokes the security violation. + * @var SCU_T::APB1VSRC + * Offset: 0x3C APB1 Security Policy Violation Source + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[3:0] |MASTER |Master Violating Security Policy + * | | |Indicate which master invokes the security violation. + * | | |0x0 = core processor. + * | | |0x3 = PDMA0. + * | | |0x4 = SDH0. + * | | |0x5 = CRYPTO. + * | | |0x6 = USH. + * | | |0xB = PDMA1. + * | | |Others is undefined. + * @var SCU_T::APB1VA + * Offset: 0x40 APB1 Violation Address + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |VIOADDR |Violation Address + * | | |Indicate the target address of the access, which invokes the security violation. + * @var SCU_T::GPIOVSRC + * Offset: 0x44 GPIO Security Policy Violation Source + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[3:0] |MASTER |Master Violating Security Policy + * | | |Indicate which master invokes the security violation. + * | | |0x0 = core processor. + * | | |0x3 = PDMA0. + * | | |0x4 = SDH0. + * | | |0x5 = CRYPTO. + * | | |0x6 = USH. + * | | |0xB = PDMA1. + * | | |Others is undefined. + * @var SCU_T::GPIOVA + * Offset: 0x48 GPIO Violation Address + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |VIOADDR |Violation Address + * | | |Indicate the target address of the access, which invokes the security violation. + * @var SCU_T::EBIVSRC + * Offset: 0x4C EBI Security Policy Violation Source + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[3:0] |MASTER |Master Violating Security Policy + * | | |Indicate which master invokes the security violation. + * | | |0x0 = core processor. + * | | |0x3 = PDMA0. + * | | |0x4 = SDH0. + * | | |0x5 = CRYPTO. + * | | |0x6 = USH. + * | | |0xB = PDMA1. + * | | |Others is undefined. + * @var SCU_T::EBIVA + * Offset: 0x50 EBI Violation Address + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |VIOADDR |Violation Address + * | | |Indicate the target address of the access, which invokes the security violation. + * @var SCU_T::USBHVSRC + * Offset: 0x54 USBH Security Policy Violation Source + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[3:0] |MASTER |Master Violating Security Policy + * | | |Indicate which master invokes the security violation. + * | | |0x0 = core processor. + * | | |0x3 = PDMA0. + * | | |0x4 = SDH0. + * | | |0x5 = CRYPTO. + * | | |0x6 = USH. + * | | |0xB = PDMA1. + * | | |Others is undefined. + * @var SCU_T::USBHVA + * Offset: 0x58 USBH Violation Address + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |VIOADDR |Violation Address + * | | |Indicate the target address of the access, which invokes the security violation. + * @var SCU_T::CRCVSRC + * Offset: 0x5C CRC Security Policy Violation Source + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[3:0] |MASTER |Master Violating Security Policy + * | | |Indicate which master invokes the security violation. + * | | |0x0 = core processor. + * | | |0x3 = PDMA0. + * | | |0x4 = SDH0. + * | | |0x5 = CRYPTO. + * | | |0x6 = USH. + * | | |0xB = PDMA1. + * | | |Others is undefined. + * @var SCU_T::CRCVA + * Offset: 0x60 CRC Violation Address + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |VIOADDR |Violation Address + * | | |Indicate the target address of the access, which invokes the security violation. + * @var SCU_T::SD0VSRC + * Offset: 0x64 SDH0 Security Policy Violation Source + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[3:0] |MASTER |Master Violating Security Policy + * | | |Indicate which master invokes the security violation. + * | | |0x0 = core processor. + * | | |0x3 = PDMA0. + * | | |0x4 = SDH0. + * | | |0x5 = CRYPTO. + * | | |0x6 = USH. + * | | |0xB = PDMA1. + * | | |Others is undefined. + * @var SCU_T::SD0VA + * Offset: 0x68 SDH0 Violation Address + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |VIOADDR |Violation Address + * | | |Indicate the target address of the access, which invokes the security violation. + * @var SCU_T::PDMA0VSRC + * Offset: 0x74 PDMA0 Security Policy Violation Source + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[3:0] |MASTER |Master Violating Security Policy + * | | |Indicate which master invokes the security violation. + * | | |0x0 = core processor. + * | | |0x3 = PDMA0. + * | | |0x4 = SDH0. + * | | |0x5 = CRYPTO. + * | | |0x6 = USH. + * | | |0xB = PDMA1. + * | | |Others is undefined. + * @var SCU_T::PDMA0VA + * Offset: 0x78 PDMA0 Violation Address + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |VIOADDR |Violation Address + * | | |Indicate the target address of the access, which invokes the security violation. + * @var SCU_T::PDMA1VSRC + * Offset: 0x7C PDMA1 Security Policy Violation Source + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[3:0] |MASTER |Master Violating Security Policy + * | | |Indicate which master invokes the security violation. + * | | |0x0 = core processor. + * | | |0x3 = PDMA0. + * | | |0x4 = SDH0. + * | | |0x5 = CRYPTO. + * | | |0x6 = USH. + * | | |0xB = PDMA1. + * | | |Others is undefined. + * @var SCU_T::PDMA1VA + * Offset: 0x80 PDMA1 Violation Address + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |VIOADDR |Violation Address + * | | |Indicate the target address of the access, which invokes the security violation. + * @var SCU_T::SRAM0VSRC + * Offset: 0x84 SRAM0 Security Policy Violation Source + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[3:0] |MASTER |Master Violating Security Policy + * | | |Indicate which master invokes the security violation. + * | | |0x0 = core processor. + * | | |0x3 = PDMA0. + * | | |0x4 = SDH0. + * | | |0x5 = CRYPTO. + * | | |0x6 = USH. + * | | |0xB = PDMA1. + * | | |Others is undefined. + * @var SCU_T::SRAM0VA + * Offset: 0x88 SRAM0 Violation Address + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |VIOADDR |Violation Address + * | | |Indicate the target address of the access, which invokes the security violation. + * @var SCU_T::SRAM1VSRC + * Offset: 0x8C SRAM1 Security Policy Violation Source + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[3:0] |MASTER |Master Violating Security Policy + * | | |Indicate which master invokes the security violation. + * | | |0x0 = core processor. + * | | |0x3 = PDMA0. + * | | |0x4 = SDH0. + * | | |0x5 = CRYPTO. + * | | |0x6 = USH. + * | | |0xB = PDMA1. + * | | |Others is undefined. + * @var SCU_T::SRAM1VA + * Offset: 0x90 SRAM1 Violation Address + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |VIOADDR |Violation Address + * | | |Indicate the target address of the access, which invokes the security violation. + * @var SCU_T::FMCVSRC + * Offset: 0x94 FMC Security Policy Violation Source + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[3:0] |MASTER |Master Violating Security Policy + * | | |Indicate which master invokes the security violation. + * | | |0x0 = core processor. + * | | |0x3 = PDMA0. + * | | |0x4 = SDH0. + * | | |0x5 = CRYPTO. + * | | |0x6 = USH. + * | | |0xB = PDMA1. + * | | |Others is undefined. + * @var SCU_T::FMCVA + * Offset: 0x98 FMC Violation Address + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |VIOADDR |Violation Address + * | | |Indicate the target address of the access, which invokes the security violation. + * @var SCU_T::FLASHVSRC + * Offset: 0x9C Flash Security Policy Violation Source + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[3:0] |MASTER |Master Violating Security Policy + * | | |Indicate which master invokes the security violation. + * | | |0x0 = core processor. + * | | |0x3 = PDMA0. + * | | |0x4 = SDH0. + * | | |0x5 = CRYPTO. + * | | |0x6 = USH. + * | | |0xB = PDMA1. + * | | |Others is undefined. + * @var SCU_T::FLASHVA + * Offset: 0xA0 Flash Violation Address + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |VIOADDR |Violation Address + * | | |Indicate the target address of the access, which invokes the security violation. + * @var SCU_T::SCUVSRC + * Offset: 0xA4 SCU Security Policy Violation Source + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[3:0] |MASTER |Master Violating Security Policy + * | | |Indicate which master invokes the security violation. + * | | |0x0 = core processor. + * | | |0x3 = PDMA0. + * | | |0x4 = SDH0. + * | | |0x5 = CRYPTO. + * | | |0x6 = USH. + * | | |0xB = PDMA1. + * | | |Others is undefined. + * @var SCU_T::SCUVA + * Offset: 0xA8 SCU Violation Address + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |VIOADDR |Violation Address + * | | |Indicate the target address of the access, which invokes the security violation. + * @var SCU_T::SYSVSRC + * Offset: 0xAC System(GMISC) Security Policy Violation Source + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[3:0] |MASTER |Master Violating Security Policy + * | | |Indicate which master invokes the security violation. + * | | |0x0 = core processor. + * | | |0x3 = PDMA0. + * | | |0x4 = SDH0. + * | | |0x5 = CRYPTO. + * | | |0x6 = USH. + * | | |0xB = PDMA1. + * | | |Others is undefined. + * @var SCU_T::SYSVA + * Offset: 0xB0 System(GMISC) Violation Address + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |VIOADDR |Violation Address + * | | |Indicate the target address of the access, which invokes the security violation. + * @var SCU_T::CRPTVSRC + * Offset: 0xB4 Crypto Security Policy Violation Source + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[3:0] |MASTER |Master Violating Security Policy + * | | |Indicate which master invokes the security violation. + * | | |0x0 = core processor. + * | | |0x3 = PDMA0. + * | | |0x4 = SDH0. + * | | |0x5 = CRYPTO. + * | | |0x6 = USH. + * | | |0xB = PDMA1. + * | | |Others is undefined. + * @var SCU_T::CRPTVA + * Offset: 0xB8 Crypto Violation Address + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |VIOADDR |Violation Address + * | | |Indicate the target address of the access, which invokes the security violation. + * @var SCU_T::KSVSRC + * Offset: 0xBC KS Security Policy Violation Source + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[3:0] |MASTER |Master Violating Security Policy + * | | |Indicate which master invokes the security violation. + * | | |0x0 = core processor. + * | | |0x3 = PDMA0. + * | | |0x4 = SDH0. + * | | |0x5 = CRYPTO. + * | | |0x6 = USH. + * | | |0xB = PDMA1. + * | | |Others is undefined. + * @var SCU_T::KSVA + * Offset: 0xC0 KS Violation Address + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |VIOADDR |Violation Address + * | | |Indicate the target address of the access, which invokes the security violation. + * @var SCU_T::SRAM2VSRC + * Offset: 0xC4 SRAM2 Security Policy Violation Source + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[3:0] |MASTER |Master Violating Security Policy + * | | |Indicate which master invokes the security violation. + * | | |0x0 = core processor. + * | | |0x3 = PDMA0. + * | | |0x4 = SDH0. + * | | |0x5 = CRYPTO. + * | | |0x6 = USH. + * | | |0xB = PDMA1. + * | | |Others is undefined. + * @var SCU_T::SRAM2VA + * Offset: 0xC8 SRAM2 Violation Address + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |VIOADDR |Violation Address + * | | |Indicate the target address of the access, which invokes the security violation. + * @var SCU_T::SINFAEN + * Offset: 0xF0 Shared Information Access Enable Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |SCUSIAEN |SCU Shared Information Access Enable Bit + * | | |0 = Non-secure CPU access SCU Shared information Disabled. + * | | |1 = Non-secure CPU access SCU Shared information Enabled. + * |[1] |SYSSIAEN |SYS Shared Information Access Enable Bit + * | | |0 = Non-secure CPU access SYS Shared information Disabled. + * | | |1 = Non-secure CPU access SYS Shared information Enabled. + * | | |Note:Include clock information. + * |[2] |FMCSIAEN |FMC Shared Information Access Enable Bit + * | | |0 = Non-secure CPU access FMC Shared information Disabled. + * | | |1 = Non-secure CPU access FMC Shared information Enabled. + * @var SCU_T::PNPSET + * Offset: 0x100 Peripheral Non-privileged Attribution Set Register0 (0x4000_0000~0x4001_FFFF) + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |SYS |Set SYS to Non-privileged State + * | | |0 = SYS is a privileged module (default). + * | | |1 = SYS is a non-privileged module. + * |[8] |PDMA0 |Set PDMA0 to Non-privileged State + * | | |0 = PDMA0 is a privileged module (default). + * | | |1 = PDMA0 is a non-privileged module. + * |[9] |USBH |Set USBH to Non-privileged State + * | | |0 = USBH is a privileged module (default). + * | | |1 = USBH is a non-privileged module. + * |[12] |FMC |Set FMC to Non-privileged State + * | | |0 = FMC is a privileged module (default). + * | | |1 = FMC is a non-privileged module. + * |[13] |SDH0 |Set SDH0 to Non-privileged State + * | | |0 = SDH0 is a privileged module (default). + * | | |1 = SDH0 is a non-privileged module. + * |[16] |EBI |Set EBI to Non-privileged State + * | | |0 = EBI is a privileged module (default). + * | | |1 = EBI is a non-privileged module. + * |[24] |PDMA1 |Set PDMA1 to Non-privileged State + * | | |0 = PDMA1 is a privileged module (default). + * | | |1 = PDMA1 is a non-privileged module. + * Offset: 0x104 Peripheral Non-privileged Attribution Set Register1 (0x4002_0000~0x4003_FFFF) + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15] |SCU |Set SCU to Non-privileged State + * | | |0 = SCU is a privileged module (default). + * | | |1 = SCU is a non-privileged module. + * |[17] |CRC |Set CRC to Non-privileged State + * | | |0 = CRC is a privileged module (default). + * | | |1 = CRC is a non-privileged module. + * |[18] |CRPT |Set CRPT to Non-privileged State + * | | |0 = CRPT is a privileged module (default). + * | | |1 = CRPT is a non-privileged module. + * |[21] |KS |Set KS to Non-privileged State + * | | |0 = KS is a privileged module (default). + * | | |1 = KS is a non-privileged module. + * Offset: 0x108 Peripheral Non-privileged Attribution Set Register2 (0x4004_0000~0x4005_FFFF) + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |WDT |Set WDT to Non-privileged State + * | | |0 = WDT is a privileged module (default). + * | | |1 = WDT is a non-privileged module. + * |[1] |RTC |Set RTC to Non-privileged State + * | | |0 = RTC is a privileged module (default). + * | | |1 = RTC is a non-privileged module. + * |[2] |EWDT |Set EWDT to Non-privileged State + * | | |0 = EWDT is a privileged module (default). + * | | |1 = EWDT is a non-privileged module. + * |[3] |EADC |Set EADC to Non-privileged State + * | | |0 = EADC is a privileged module (default). + * | | |1 = EADC is a non-privileged module. + * |[5] |ACMP01 |Set ACMP01 to Non-privileged State + * | | |0 = ACMP0, ACMP1 are privileged modules (default). + * | | |1 = ACMP0, ACMP1 are non-privileged modules. + * |[7] |DAC |Set DAC to Non-privileged State + * | | |0 = DAC is a privileged module (default). + * | | |1 = DAC is a non-privileged module. + * |[8] |I2S0 |Set I2S0 to Non-privileged State + * | | |0 = I2S0 is a privileged module (default). + * | | |1 = I2S0 is a non-privileged module. + * |[13] |OTG |Set OTG to Non-privileged State + * | | |0 = OTG is a privileged module (default). + * | | |1 = OTG is a non-privileged module. + * |[16:14] |TMR01 |Set TMR01 to Non-privileged State + * | | |0 = TMR01 is a privileged module (default). + * | | |1 = TMR01 is a non-privileged module. + * |[17] |TMR23 |Set TMR23 to Non-privileged State + * | | |0 = TMR23 is a privileged module (default). + * | | |1 = TMR23 is a non-privileged module. + * |[24] |EPWM0 |Set EPWM0 to Non-privileged State + * | | |0 = EPWM0 is a privileged module (default). + * | | |1 = EPWM0 is a non-privileged module. + * |[25] |EPWM1 |Set EPWM1 to Non-privileged State + * | | |0 = EPWM1 is a privileged module (default). + * | | |1 = EPWM1 is a non-privileged module. + * |[26] |BPWM0 |Set BPWM0 to Non-privileged State + * | | |0 = BPWM0 is a privileged module (default). + * | | |1 = BPWM0 is a non-privileged module. + * |[27] |BPWM1 |Set BPWM1 to Non-privileged State + * | | |0 = BPWM1 is a privileged module (default). + * | | |1 = BPWM1 is a non-privileged module. + * Offset: 0x10C Peripheral Non-privileged Attribution Set Register3 (0x4006_0000~0x4007_FFFF) + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |QSPI0 |Set QSPI0 to Non-privileged State + * | | |0 = QSPI0 is a privileged module (default). + * | | |1 = QSPI0 is a non-privileged module. + * |[1] |SPI0 |Set SPI0 to Non-privileged State + * | | |0 = SPI0 is a privileged module (default). + * | | |1 = SPI0 is a non-privileged module. + * |[2] |SPI1 |Set SPI1 to Non-privileged State + * | | |0 = SPI1 is a privileged module (default). + * | | |1 = SPI1 is a non-privileged module. + * |[3] |SPI2 |Set SPI2 to Non-privileged State + * | | |0 = SPI2 is a privileged module (default). + * | | |1 = SPI2 is a non-privileged module. + * |[4] |SPI3 |Set SPI3 to Non-privileged State + * | | |0 = SPI3 is a privileged module (default). + * | | |1 = SPI3 is a non-privileged module. + * |[16] |UART0 |Set UART0 to Non-privileged State + * | | |0 = UART0 is a privileged module (default). + * | | |1 = UART0 is a non-privileged module. + * |[17] |UART1 |Set UART1 to Non-privileged State + * | | |0 = UART1 is a privileged module (default). + * | | |1 = UART1 is a non-privileged module. + * |[18] |UART2 |Set UART2 to Non-privileged State + * | | |0 = UART2 is a privileged module (default). + * | | |1 = UART2 is a non-privileged module. + * |[19] |UART3 |Set UART3 to Non-privileged State + * | | |0 = UART3 is a privileged module (default). + * | | |1 = UART3 is a non-privileged module. + * |[20] |UART4 |Set UART4 to Non-privileged State + * | | |0 = UART4 is a privileged module (default). + * | | |1 = UART4 is a non-privileged module. + * |[21] |UART5 |Set UART5 to Non-privileged State + * | | |0 = UART5 is a privileged module (default). + * | | |1 = UART5 is a non-privileged module. + * Offset: 0x110 Peripheral Non-privileged Attribution Set Register4 (0x4008_0000~0x4009_FFFF) + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |I2C0 |Set I2C0 to Non-privileged State + * | | |0 = I2C0 is a privileged module (default). + * | | |1 = I2C0 is a non-privileged module. + * |[1] |I2C1 |Set I2C1 to Non-privileged State + * | | |0 = I2C1 is a privileged module (default). + * | | |1 = I2C1 is a non-privileged module. + * |[2] |I2C2 |Set I2C2 to Non-privileged State + * | | |0 = I2C2 is a privileged module (default). + * | | |1 = I2C2 is a non-privileged module. + * |[16] |SC0 |Set SC0 to Non-privileged State + * | | |0 = SC0 is a privileged module (default). + * | | |1 = SC0 is a non-privileged module. + * |[17] |SC1 |Set SC1 to Non-privileged State + * | | |0 = SC1 is a privileged module (default). + * | | |1 = SC1 is a non-privileged module. + * |[18] |SC2 |Set SC2 to Non-privileged State + * | | |0 = SC2 is a privileged module (default). + * | | |1 = SC2 is a non-privileged module. + * Offset: 0x114 Peripheral Non-privileged Attribution Set Register5 (0x400A_0000~0x400B_FFFF) + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |CAN0 |Set CAN0 to Non-privileged State + * | | |0 = CAN0 is a privileged module (default). + * | | |1 = CAN0 is a non-privileged module. + * |[16] |QEI0 |Set QEI0 to Non-privileged State + * | | |0 = QEI0 is a privileged module (default). + * | | |1 = QEI0 is a non-privileged module. + * |[17] |QEI1 |Set QEI1 to Non-privileged State + * | | |0 = QEI1 is a privileged module (default). + * | | |1 = QEI1 is a non-privileged module. + * |[20] |ECAP0 |Set ECAP0 to Non-privileged State + * | | |0 = ECAP0 is a privileged module (default). + * | | |1 = ECAP0 is a non-privileged module. + * |[21] |ECAP1 |Set ECAP1 to Non-privileged State + * | | |0 = ECAP1 is a privileged module (default). + * | | |1 = ECAP1 is a non-privileged module. + * |[25] |TRNG |Set TRNG to Non-privileged State + * | | |0 = TRNG is a privileged module (default). + * | | |1 = TRNG is a non-privileged module. + * |[27] |LCD |Set LCD to Non-privileged State + * | | |0 = LCD is a privileged module (default). + * | | |1 = LCD is a non-privileged module. + * |[29] |TAMPER |Set TAMPER to Non-privileged State + * | | |0 = TAMPER is a privileged module (default). + * | | |1 = TAMPER is a non-privileged module. + * Offset: 0x118 Peripheral Non-privileged Attribution Set Register6 (0x400C_0000~0x400D_FFFF) + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |USBD |Set USBD to Non-privileged State + * | | |0 = USBD is a privileged module (default). + * | | |1 = USBD is a non-privileged module. + * |[16] |USCI0 |Set USCI0 to Non-privileged State + * | | |0 = USCI0 is a privileged module (default). + * | | |1 = USCI0 is a non-privileged module. + * |[17] |USCI1 |Set USCI1 to Non-privileged State + * | | |0 = USCI1 is a privileged module (default). + * | | |1 = USCI1 is a non-privileged module. + * @var SCU_T::IONPSET + * Offset: 0x120 IO Non-privileged Attribution Set Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |PA |Set GPIO Port a to Non-privileged State + * | | |0 = GPIO port A is privileged (default). + * | | |1 = GPIO port A is non-privileged. + * |[1] |PB |Set GPIO Port B to Non-privileged State + * | | |0 = GPIO port B is privileged (default). + * | | |1 = GPIO port B is non-privileged. + * |[2] |PC |Set GPIO Port C to Non-privileged State + * | | |0 = GPIO port C is privileged (default). + * | | |1 = GPIO port C is non-privileged. + * |[3] |PD |Set GPIO Port D to Non-privileged State + * | | |0 = GPIO port D is privileged (default). + * | | |1 = GPIO port D is non-privileged. + * |[4] |PE |Set GPIO Port E to Nonj-privileged State + * | | |0 = GPIO port E is privileged (default). + * | | |1 = GPIO port E is non-privileged. + * |[5] |PF |Set GPIO Port F to Non-privileged State + * | | |0 = GPIO port F is privileged (default). + * | | |1 = GPIO port F is non-privileged. + * |[6] |PG |Set GPIO Port G to Non-privileged State + * | | |0 = GPIO port G is privileged (default). + * | | |1 = GPIO port G is non-privileged. + * |[7] |PH |Set GPIO Port H to Non-privileged State + * | | |0 = GPIO port H is privileged (default). + * | | |1 = GPIO port H is non-privileged. + * @var SCU_T::SRAMNPSET + * Offset: 0x124 SRAM Non-privileged Attribution Set Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[19:0] |SECn |Set SRAM Section n to Non-privileged State + * | | |0 = SRAM Section n is privileged (default). + * | | |1 = SRAM Section n is non-privileged. + * | | |Size per section is 16 Kbytes. + * | | |Secure SRAM section n is 0x2000_0000+0x4000*n to 0x2000_0000+0x4000*(n+1)-0x1 + * | | |Non-secure SRAM section n is 0x3000_0000+0x4000*n to 0x3000_0000+0x4000*(n+1)-0x1 + * @var SCU_T::MEMNPSET + * Offset: 0x128 Other Memory Non-privileged Attribution Set Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |FLASH |Set Flash to Non-privileged State + * | | |Set the privileged state of memory ranging from 0x0000_0000 to 0x1FFF_FFFF. + * | | |0 = Flash is setting to privileged (default). + * | | |1 = Flash is setting to non-privileged. + * |[1] |EXTMEM |Set External Memory (EBI Memory) to Non-privileged State + * | | |Set the privileged state of memory ranging from 0x6000_0000 to 0x7FFF_FFFF. + * | | |0 = External Memory is setting to privileged (default). + * | | |1 = External Memory is setting to non-privileged. + * @var SCU_T::PVIOIEN + * Offset: 0x12C Privileged Violation Interrupt Enable Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |APB0IEN |APB0 Privileged Violation Interrupt Enable Bit + * | | |0 = Interrupt triggered from privileged violation of APB0 Disabled. + * | | |1 = Interrupt triggered from privileged violation of APB0 Enabled. + * |[1] |APB1IEN |APB1 Privileged Violation Interrupt Enable Bit + * | | |0 = Interrupt triggered from privileged violation of APB1 Disabled. + * | | |1 = Interrupt triggered from privileged violation of APB1 Enabled. + * |[4] |GPIOIEN |GPIO Privileged Violation Interrupt Enable Bit + * | | |0 = Interrupt triggered from privileged violation of GPIO Disabled. + * | | |1 = Interrupt triggered from privileged violation of GPIO Enabled. + * |[5] |EBIIEN |EBI Privileged Violation Interrupt Enable Bit + * | | |0 = Interrupt triggered from privileged violation of EBI Disabled. + * | | |1 = Interrupt triggered from privileged violation of EBI Enabled. + * |[6] |USBHIEN |USBH Privileged Violation Interrupt Enable Bit + * | | |0 = Interrupt triggered from privileged violation of USB host Disabled. + * | | |1 = Interrupt triggered from privileged violation of USB host Enabled. + * |[7] |CRCIEN |CRC Privileged Violation Interrupt Enable Bit + * | | |0 = Interrupt triggered from privileged violation of CRC Disabled. + * | | |1 = Interrupt triggered from privileged violation of CRC Enabled. + * |[8] |SDH0IEN |SDH0 Privileged Violation Interrupt Enable Bit + * | | |0 = Interrupt triggered from privileged violation of SD host 0 Disabled. + * | | |1 = Interrupt triggered from privileged violation of SD host 0 Enabled. + * |[10] |PDMA0IEN |PDMA0 Privileged Violation Interrupt Enable Bit + * | | |0 = Interrupt triggered from privileged violation of PDMA0 Disabled. + * | | |1 = Interrupt triggered from privileged violation of PDMA0 Enabled. + * |[11] |PDMA1IEN |PDMA1 Privileged Violation Interrupt Enable Bit + * | | |0 = Interrupt triggered from privileged violation of PDMA1 Disabled. + * | | |1 = Interrupt triggered from privileged violation of PDMA1 Enabled. + * |[12] |SRAM0IEN |SRAM Bank 0 Privileged Violation Interrupt Enable Bit + * | | |0 = Interrupt triggered from privileged violation of SRAM bank0 Disabled. + * | | |1 = Interrupt triggered from privileged violation of SRAM bank0 Enabled. + * |[13] |SRAM1IEN |SRAM Bank 1 Privileged Violation Interrupt Enable Bit + * | | |0 = Interrupt triggered from privileged violation of SRAM bank1 Disabled. + * | | |1 = Interrupt triggered from privileged violation of SRAM bank1 Enabled. + * |[14] |FMCIEN |FMC Privileged Violation Interrupt Enable Bit + * | | |0 = Interrupt triggered from privileged violation of FMC Disabled. + * | | |1 = Interrupt triggered from privileged violation of FMC Enabled. + * |[15] |FLASHIEN |FLASH Privileged Violation Interrupt Enable Bit + * | | |0 = Interrupt triggered from privileged violation of Flash data Disabled. + * | | |1 = Interrupt triggered from privileged violation of Flash data Enabled. + * |[16] |SCUIEN |SCU Privileged Violation Interrupt Enable Bit + * | | |0 = Interrupt triggered from privileged violation of SCU Disabled. + * | | |1 = Interrupt triggered from privileged violation of SCU Enabled. + * |[17] |SYSIEN |SYS Privileged Violation Interrupt Enable Bit + * | | |0 = Interrupt triggered from privileged violation of system manager Disabled. + * | | |1 = Interrupt triggered from privileged violation of system manager Enabled. + * |[18] |CRPTIEN |CRPT Privileged Violation Interrupt Enable Bit + * | | |0 = Interrupt triggered from privileged violation of crypto Disabled. + * | | |1 = Interrupt triggered from privileged violation of crypto Enabled. + * |[19] |KSIEN |KS Privileged Violation Interrupt Enale Bit + * | | |0 = Interrupt triggered from privileged violation of keystore Disabled. + * | | |1 = Interrupt triggered from privileged violation of keystore Enabled. + * @var SCU_T::PVINTSTS + * Offset: 0x130 Privileged Violation Interrupt Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |APB0IF |APB0 Privileged Violation Interrupt Status + * | | |0 = No APB0 violation interrupt event. + * | | |1 = There is APB0 violation interrupt event. + * | | |Note: Write 1 to clear the interrupt flag. + * |[1] |APB1IF |APB1 Privileged Violation Interrupt Status + * | | |0 = No APB1 violation interrupt event. + * | | |1 = There is APB1 violation interrupt event. + * | | |Note: Write 1 to clear the interrupt flag. + * |[4] |GPIOIF |GPIO Privileged Violation Interrupt Status + * | | |0 = No GPIO violation interrupt event. + * | | |1 = There is GPIO violation interrupt event. + * | | |Note: Write 1 to clear the interrupt flag. + * |[5] |EBIIF |EBI Privileged Violation Interrupt Status + * | | |0 = No EBI violation interrupt event. + * | | |1 = There is EBI violation interrupt event. + * | | |Note: Write 1 to clear the interrupt flag. + * |[6] |USBHIF |USBH Privileged Violation Interrupt Status + * | | |0 = No USBH violation interrupt event. + * | | |1 = There is USBH violation interrupt event. + * | | |Note: Write 1 to clear the interrupt flag. + * |[7] |CRCIF |CRC Privileged Violation Interrupt Status + * | | |0 = No CRC violation interrupt event. + * | | |1 = There is CRC violation interrupt event. + * | | |Note: Write 1 to clear the interrupt flag. + * |[8] |SDH0IF |SDH0 Privileged Violation Interrupt Status + * | | |0 = No SDH0 violation interrupt event. + * | | |1 = There is SDH0 violation interrupt event. + * | | |Note: Write 1 to clear the interrupt flag. + * |[10] |PDMA0IF |PDMA0 Privileged Violation Interrupt Status + * | | |0 = No PDMA0 violation interrupt event. + * | | |1 = There is PDMA0 violation interrupt event. + * | | |Note: Write 1 to clear the interrupt flag. + * |[11] |PDMA1IF |PDMA1 Privileged Violation Interrupt Status + * | | |0 = No PDMA1 violation interrupt event. + * | | |1 = There is PDMA1 violation interrupt event. + * | | |Note: Write 1 to clear the interrupt flag. + * |[12] |SRAM0IF |SRAM0 Privileged Violation Interrupt Status + * | | |0 = No SRAM0 violation interrupt event. + * | | |1 = There is SRAM0 violation interrupt event. + * | | |Note: Write 1 to clear the interrupt flag. + * |[13] |SRAM1IF |SRAM Bank 1 Privileged Violation Interrupt Status + * | | |0 = No SRAM1 violation interrupt event. + * | | |1 = There is SRAM1 violation interrupt event. + * | | |Note: Write 1 to clear the interrupt flag. + * |[14] |FMCIF |FMC Privileged Violation Interrupt Status + * | | |0 = No FMC violation interrupt event. + * | | |1 = There is FMC violation interrupt event. + * | | |Note: Write 1 to clear the interrupt flag. + * |[15] |FLASHIF |FLASH Privileged Violation Interrupt Status + * | | |0 = No FLASH violation interrupt event. + * | | |1 = There is FLASH violation interrupt event. + * | | |Note: Write 1 to clear the interrupt flag. + * |[16] |SCUIF |SCU Privileged Violation Interrupt Status + * | | |0 = No SCU violation interrupt event. + * | | |1 = There is SCU violation interrupt event. + * | | |Note: Write 1 to clear the interrupt flag. + * |[17] |SYSIF |SYS Privileged Violation Interrupt Status + * | | |0 = No SYS violation interrupt event. + * | | |1 = There is SYS violation interrupt event. + * | | |Note: Write 1 to clear the interrupt flag. + * |[18] |CRPTIF |CRPT Privileged Violation Interrupt Status + * | | |0 = No CRPT violation interrupt event. + * | | |1 = There is CRPT violation interrupt event. + * | | |Note: Write 1 to clear the interrupt flag. + * |[19] |KSIF |KS Privileged Violation Interrupt Status + * | | |0 = No KS violation interrupt event. + * | | |1 = There is KS violation interrupt event. + * | | |Note: Write 1 to clear the interrupt flag. + * @var SCU_T::NSMCTL + * Offset: 0x200 Non-secure State Monitor Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[7:0] |PRESCALE |Pre-scale Value of Non-secure State Monitor Counter + * | | |0 = Counter Disabled. + * | | |Others = Counter Enabled and the counter clock source = HCLK/PRESCALE. + * |[8] |NSMIEN |Non-secure State Monitor Interrupt Enable Bit + * | | |0 = Non-secure state monitor interrupt Disabled. + * | | |1 = Non-secure state monitor interrupt Enabled. + * |[9] |AUTORLD |Auto Reload Non-secure State Monitor Counter When CURRNS Changing to 1 + * | | |0 = Disable clearing non-secure state monitor counter automtically (default). + * | | |1 = Enable clearing non-secure state monitor counter automatically when the core processor changes from secure state to non-secure state + * | | |(i.e.when CURRNS chagned from 0 to 1). + * |[10] |TMRMOD |Non-secure Monitor Mode Enable Bit + * | | |0 = Monitor mode. The counter will count down when the core processor is in non-secure state. (default) + * | | |1 = Free-counting mode + * | | |The counter will keep counting no mater the core processor is in secure or non-secure state. + * |[12] |IDLEON |Monitor Counter Keep Counting When the Chip Is in Idle Mode Enable Bit + * | | |0 = The counter will be halted when the chip is in idle mode. + * | | |1 = The counter will keep counting when the chip is in idle mode. (default) + * | | |Note: In monitor mode, the counter is always halted when the core processor is in secure state. + * |[13] |DBGON |Monitor Counter Keep Counting When the Chip Is in Debug Mode Enable Bit + * | | |0 = The counter will be halted when the core processor is halted by ICE. (default) + * | | |1 = The counter will keep counting when the core processor is halted by ICE. + * @var SCU_T::NSMLOAD + * Offset: 0x204 Non-secure State Monitor Reload Value Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[23:0] |RELOAD |Reload Value for Non-secure State Monitor Counter + * | | |The RELOAD value will be reloaded to the counter whenever the counter counts down to 0. + * @var SCU_T::NSMVAL + * Offset: 0x208 Non-secure State Monitor Counter Value Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[23:0] |VALUE |Counter Value of Non-secure State Monitor Counter + * | | |Current value of non-secure state monitor counter + * | | |This is down counter and counts down only when CURRNS = 1 + * | | |When counting down to 0, VALUE will automatically be reloaded from NSMLOAD register. + * | | |A write of any value clears the VALUE to 0 and also clears NSMIF. + * @var SCU_T::NSMSTS + * Offset: 0x20C Non-secure State Monitor Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |CURRNS |Current Core Processor Secure/Non-secure State (Read Only) + * | | |0 = Core processor is in secure state. + * | | |1 = Core processor is in non-secure state. + * | | |Note: This bit can be used to monitor the current secure/non-secure state of the core processor, even if the non-secure state monitor counter is disabled. + * |[1] |NSMIF |Non-secure State Monitor Interrupt Flag + * | | |0 = Counter doesnu2019t count down to 0 since the last NSMIF has been cleared. + * | | |1 = Counter counts down to 0. + * | | |Note: This bit is cleared by writing 1. + * @var SCU_T::BBE + * Offset: 0x300 Block Bus Error Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |BBEEN |Block Bus-error Enable Bit + * | | |0 = Disable Blocking Bus Error to the core processor. + * | | |1 = Enable Blocking Bus Error to the core processor. + * | | |This bit is double write-protected, WRVERY and SYS_REGLCTL register. + * |[31:8] |WVERY |Write Verify Code + * | | |In order to write BBEEN bit, the code should be set as 0x59475A. + * | | |When read access, the return value of this field is always 0. + * @var SCU_T::IDAUANS + * Offset: 0x304 IDAU All Non-secure Set Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |IDAUANSEN |IDAU All Non-secure Enable Bit + * | | |0 = Disable IDAU sets all region Non-secure. + * | | |1 = Enable IDAU sets all region Non-secure. + * | | |This bit is double write-protected, WRVERY and SYS_REGLCTL register. + * |[31:8] |WVERY |Write Verify Code + * | | |In order to write BBEEN bit, the code should be set as 0x59475A. + * | | |When read access, the return value of this field is always 0. + * @var SCU_T::VERSION + * Offset: 0xFFC SCU RTL Design Version Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |MINOR |SCU RTL Design Minor Version + * | | |Minor version number is dependent on ECO version control. + * |[23:16] |SUB |SCU RTL Design Sub Version Number + * | | |Major version number is correlated to product line. + * |[31:24] |MAJOR |SCU RTL Design Major Version Number + * | | |Major version number is correlated to product line. + */ + __IO uint32_t PNSSET[7]; /*!< [0x0000:0x0018] Peripheral Non-secure Attribution Set Register0 (0x4000_0000~0x400D_FFFF) */ + __I uint32_t RESERVE0[2]; + __IO uint32_t SRAMNSSET; /*!< [0x0024] SRAM Non-secure Attribution Set Register */ + __I uint32_t FNSADDR; /*!< [0x0028] Flash Non-secure Boundary Address Register */ + __IO uint32_t SVIOIEN; /*!< [0x002c] Security Violation Interrupt Enable Register */ + __IO uint32_t SVINTSTS; /*!< [0x0030] Security Violation Interrupt Status Register */ + __I uint32_t APB0VSRC; /*!< [0x0034] APB0 Security Policy Violation Source */ + __I uint32_t APB0VA; /*!< [0x0038] APB0 Violation Address */ + __I uint32_t APB1VSRC; /*!< [0x003c] APB1 Security Policy Violation Source */ + __I uint32_t APB1VA; /*!< [0x0040] APB1 Violation Address */ + __I uint32_t GPIOVSRC; /*!< [0x0044] GPIO Security Policy Violation Source */ + __I uint32_t GPIOVA; /*!< [0x0048] GPIO Violation Address */ + __I uint32_t EBIVSRC; /*!< [0x004c] EBI Security Policy Violation Source */ + __I uint32_t EBIVA; /*!< [0x0050] EBI Violation Address */ + __I uint32_t USBHVSRC; /*!< [0x0054] USBH Security Policy Violation Source */ + __I uint32_t USBHVA; /*!< [0x0058] USBH Violation Address */ + __I uint32_t CRCVSRC; /*!< [0x005c] CRC Security Policy Violation Source */ + __I uint32_t CRCVA; /*!< [0x0060] CRC Violation Address */ + __I uint32_t SD0VSRC; /*!< [0x0064] SDH0 Security Policy Violation Source */ + __I uint32_t SD0VA; /*!< [0x0068] SDH0 Violation Address */ + __I uint32_t RESERVE1[2]; + __I uint32_t PDMA0VSRC; /*!< [0x0074] PDMA0 Security Policy Violation Source */ + __I uint32_t PDMA0VA; /*!< [0x0078] PDMA0 Violation Address */ + __I uint32_t PDMA1VSRC; /*!< [0x007c] PDMA1 Security Policy Violation Source */ + __I uint32_t PDMA1VA; /*!< [0x0080] PDMA1 Violation Address */ + __I uint32_t SRAM0VSRC; /*!< [0x0084] SRAM0 Security Policy Violation Source */ + __I uint32_t SRAM0VA; /*!< [0x0088] SRAM0 Violation Address */ + __I uint32_t SRAM1VSRC; /*!< [0x008c] SRAM1 Security Policy Violation Source */ + __I uint32_t SRAM1VA; /*!< [0x0090] SRAM1 Violation Address */ + __I uint32_t FMCVSRC; /*!< [0x0094] FMC Security Policy Violation Source */ + __I uint32_t FMCVA; /*!< [0x0098] FMC Violation Address */ + __I uint32_t FLASHVSRC; /*!< [0x009c] Flash Security Policy Violation Source */ + __I uint32_t FLASHVA; /*!< [0x00a0] Flash Violation Address */ + __I uint32_t SCUVSRC; /*!< [0x00a4] SCU Security Policy Violation Source */ + __I uint32_t SCUVA; /*!< [0x00a8] SCU Violation Address */ + __I uint32_t SYSVSRC; /*!< [0x00ac] System(GMISC) Security Policy Violation Source */ + __I uint32_t SYSVA; /*!< [0x00b0] System(GMISC) Violation Address */ + __I uint32_t CRPTVSRC; /*!< [0x00b4] Crypto Security Policy Violation Source */ + __I uint32_t CRPTVA; /*!< [0x00b8] Crypto Violation Address */ + __I uint32_t KSVSRC; /*!< [0x00bc] KS Security Policy Violation Source */ + __I uint32_t KSVA; /*!< [0x00c0] KS Violation Address */ + __I uint32_t SRAM2VSRC; /*!< [0x00c4] SRAM2 Security Policy Violation Source */ + __I uint32_t SRAM2VA; /*!< [0x00c8] SRAM2 Violation Address */ + __I uint32_t RESERVE2[9]; + __IO uint32_t SINFAEN; /*!< [0x00f0] Shared Information Access Enable Register */ + __I uint32_t RESERVE3[3]; + __IO uint32_t PNPSET[7]; /*!< [0x0100:0x0118] Peripheral Non-privileged Attribution Set Register0 (0x4000_0000~0x400D_FFFF) */ + __I uint32_t RESERVE4[1]; + __IO uint32_t IONPSET; /*!< [0x0120] IO Non-privileged Attribution Set Register */ + __IO uint32_t SRAMNPSET; /*!< [0x0124] SRAM Non-privileged Attribution Set Register */ + __IO uint32_t MEMNPSET; /*!< [0x0128] Other Memory Non-privileged Attribution Set Register */ + __IO uint32_t PVIOIEN; /*!< [0x012c] Privileged Violation Interrupt Enable Register */ + __IO uint32_t PVINTSTS; /*!< [0x0130] Privileged Violation Interrupt Status Register */ + __I uint32_t RESERVE5[3]; + __IO uint32_t IONSSET[8]; /*!< [0x0140:0x015C] IO Non-secure Attribution Set Register */ + __I uint32_t RESERVE6[40]; + __IO uint32_t NSMCTL; /*!< [0x0200] Non-secure State Monitor Control Register */ + __IO uint32_t NSMLOAD; /*!< [0x0204] Non-secure State Monitor Reload Value Register */ + __IO uint32_t NSMVAL; /*!< [0x0208] Non-secure State Monitor Counter Value Register */ + __IO uint32_t NSMSTS; /*!< [0x020c] Non-secure State Monitor Status Register */ + __I uint32_t RESERVE7[60]; + __IO uint32_t BBE; /*!< [0x0300] Block Bus Error Register */ + __IO uint32_t IDAUANS; /*!< [0x0304] IDAU All Non-secure Set Register */ + __I uint32_t RESERVE8[829]; + __I uint32_t VERSION; /*!< [0x0ffc] SCU RTL Design Version Register */ + +} SCU_T; + +/** + @addtogroup SCU_CONST SCU Bit Field Definition + Constant Definitions for SCU Controller + @{ +*/ + +#define SCU_PNSSET0_USBH_Pos (9) /*!< SCU_T::PNSSET0: USBH Position */ +#define SCU_PNSSET0_USBH_Msk (0x1ul << SCU_PNSSET0_USBH_Pos) /*!< SCU_T::PNSSET0: USBH Mask */ + +#define SCU_PNSSET0_SDH0_Pos (13) /*!< SCU_T::PNSSET0: SDH0 Position */ +#define SCU_PNSSET0_SDH0_Msk (0x1ul << SCU_PNSSET0_SDH0_Pos) /*!< SCU_T::PNSSET0: SDH0 Mask */ + +#define SCU_PNSSET0_EBI_Pos (16) /*!< SCU_T::PNSSET0: EBI Position */ +#define SCU_PNSSET0_EBI_Msk (0x1ul << SCU_PNSSET0_EBI_Pos) /*!< SCU_T::PNSSET0: EBI Mask */ + +#define SCU_PNSSET0_PDMA1_Pos (24) /*!< SCU_T::PNSSET0: PDMA1 Position */ +#define SCU_PNSSET0_PDMA1_Msk (0x1ul << SCU_PNSSET0_PDMA1_Pos) /*!< SCU_T::PNSSET0: PDMA1 Mask */ + +#define SCU_PNSSET1_CRC_Pos (17) /*!< SCU_T::PNSSET1: CRC Position */ +#define SCU_PNSSET1_CRC_Msk (0x1ul << SCU_PNSSET1_CRC_Pos) /*!< SCU_T::PNSSET1: CRC Mask */ + +#define SCU_PNSSET1_CRPT_Pos (18) /*!< SCU_T::PNSSET1: CRPT Position */ +#define SCU_PNSSET1_CRPT_Msk (0x1ul << SCU_PNSSET1_CRPT_Pos) /*!< SCU_T::PNSSET1: CRPT Mask */ + +#define SCU_PNSSET2_EWDT_Pos (2) /*!< SCU_T::PNSSET2: EWDT Position */ +#define SCU_PNSSET2_EWDT_Msk (0x1ul << SCU_PNSSET2_EWDT_Pos) /*!< SCU_T::PNSSET2: EWDT Mask */ + +#define SCU_PNSSET2_EADC_Pos (3) /*!< SCU_T::PNSSET2: EADC Position */ +#define SCU_PNSSET2_EADC_Msk (0x1ul << SCU_PNSSET2_EADC_Pos) /*!< SCU_T::PNSSET2: EADC Mask */ + +#define SCU_PNSSET2_ACMP01_Pos (5) /*!< SCU_T::PNSSET2: ACMP01 Position */ +#define SCU_PNSSET2_ACMP01_Msk (0x1ul << SCU_PNSSET2_ACMP01_Pos) /*!< SCU_T::PNSSET2: ACMP01 Mask */ + +#define SCU_PNSSET2_DAC_Pos (7) /*!< SCU_T::PNSSET2: DAC Position */ +#define SCU_PNSSET2_DAC_Msk (0x1ul << SCU_PNSSET2_DAC_Pos) /*!< SCU_T::PNSSET2: DAC Mask */ + +#define SCU_PNSSET2_I2S0_Pos (8) /*!< SCU_T::PNSSET2: I2S0 Position */ +#define SCU_PNSSET2_I2S0_Msk (0x1ul << SCU_PNSSET2_I2S0_Pos) /*!< SCU_T::PNSSET2: I2S0 Mask */ + +#define SCU_PNSSET2_OTG_Pos (13) /*!< SCU_T::PNSSET2: OTG Position */ +#define SCU_PNSSET2_OTG_Msk (0x1ul << SCU_PNSSET2_OTG_Pos) /*!< SCU_T::PNSSET2: OTG Mask */ + +#define SCU_PNSSET2_TMR23_Pos (17) /*!< SCU_T::PNSSET2: TMR23 Position */ +#define SCU_PNSSET2_TMR23_Msk (0x1ul << SCU_PNSSET2_TMR23_Pos) /*!< SCU_T::PNSSET2: TMR23 Mask */ + +#define SCU_PNSSET2_EPWM0_Pos (24) /*!< SCU_T::PNSSET2: EPWM0 Position */ +#define SCU_PNSSET2_EPWM0_Msk (0x1ul << SCU_PNSSET2_EPWM0_Pos) /*!< SCU_T::PNSSET2: EPWM0 Mask */ + +#define SCU_PNSSET2_EPWM1_Pos (25) /*!< SCU_T::PNSSET2: EPWM1 Position */ +#define SCU_PNSSET2_EPWM1_Msk (0x1ul << SCU_PNSSET2_EPWM1_Pos) /*!< SCU_T::PNSSET2: EPWM1 Mask */ + +#define SCU_PNSSET2_BPWM0_Pos (26) /*!< SCU_T::PNSSET2: BPWM0 Position */ +#define SCU_PNSSET2_BPWM0_Msk (0x1ul << SCU_PNSSET2_BPWM0_Pos) /*!< SCU_T::PNSSET2: BPWM0 Mask */ + +#define SCU_PNSSET2_BPWM1_Pos (27) /*!< SCU_T::PNSSET2: BPWM1 Position */ +#define SCU_PNSSET2_BPWM1_Msk (0x1ul << SCU_PNSSET2_BPWM1_Pos) /*!< SCU_T::PNSSET2: BPWM1 Mask */ + +#define SCU_PNSSET3_QSPI0_Pos (0) /*!< SCU_T::PNSSET3: QSPI0 Position */ +#define SCU_PNSSET3_QSPI0_Msk (0x1ul << SCU_PNSSET3_QSPI0_Pos) /*!< SCU_T::PNSSET3: QSPI0 Mask */ + +#define SCU_PNSSET3_SPI0_Pos (1) /*!< SCU_T::PNSSET3: SPI0 Position */ +#define SCU_PNSSET3_SPI0_Msk (0x1ul << SCU_PNSSET3_SPI0_Pos) /*!< SCU_T::PNSSET3: SPI0 Mask */ + +#define SCU_PNSSET3_SPI1_Pos (2) /*!< SCU_T::PNSSET3: SPI1 Position */ +#define SCU_PNSSET3_SPI1_Msk (0x1ul << SCU_PNSSET3_SPI1_Pos) /*!< SCU_T::PNSSET3: SPI1 Mask */ + +#define SCU_PNSSET3_SPI2_Pos (3) /*!< SCU_T::PNSSET3: SPI2 Position */ +#define SCU_PNSSET3_SPI2_Msk (0x1ul << SCU_PNSSET3_SPI2_Pos) /*!< SCU_T::PNSSET3: SPI2 Mask */ + +#define SCU_PNSSET3_SPI3_Pos (4) /*!< SCU_T::PNSSET3: SPI3 Position */ +#define SCU_PNSSET3_SPI3_Msk (0x1ul << SCU_PNSSET3_SPI3_Pos) /*!< SCU_T::PNSSET3: SPI3 Mask */ + +#define SCU_PNSSET3_UART0_Pos (16) /*!< SCU_T::PNSSET3: UART0 Position */ +#define SCU_PNSSET3_UART0_Msk (0x1ul << SCU_PNSSET3_UART0_Pos) /*!< SCU_T::PNSSET3: UART0 Mask */ + +#define SCU_PNSSET3_UART1_Pos (17) /*!< SCU_T::PNSSET3: UART1 Position */ +#define SCU_PNSSET3_UART1_Msk (0x1ul << SCU_PNSSET3_UART1_Pos) /*!< SCU_T::PNSSET3: UART1 Mask */ + +#define SCU_PNSSET3_UART2_Pos (18) /*!< SCU_T::PNSSET3: UART2 Position */ +#define SCU_PNSSET3_UART2_Msk (0x1ul << SCU_PNSSET3_UART2_Pos) /*!< SCU_T::PNSSET3: UART2 Mask */ + +#define SCU_PNSSET3_UART3_Pos (19) /*!< SCU_T::PNSSET3: UART3 Position */ +#define SCU_PNSSET3_UART3_Msk (0x1ul << SCU_PNSSET3_UART3_Pos) /*!< SCU_T::PNSSET3: UART3 Mask */ + +#define SCU_PNSSET3_UART4_Pos (20) /*!< SCU_T::PNSSET3: UART4 Position */ +#define SCU_PNSSET3_UART4_Msk (0x1ul << SCU_PNSSET3_UART4_Pos) /*!< SCU_T::PNSSET3: UART4 Mask */ + +#define SCU_PNSSET3_UART5_Pos (21) /*!< SCU_T::PNSSET3: UART5 Position */ +#define SCU_PNSSET3_UART5_Msk (0x1ul << SCU_PNSSET3_UART5_Pos) /*!< SCU_T::PNSSET3: UART5 Mask */ + +#define SCU_PNSSET4_I2C0_Pos (0) /*!< SCU_T::PNSSET4: I2C0 Position */ +#define SCU_PNSSET4_I2C0_Msk (0x1ul << SCU_PNSSET4_I2C0_Pos) /*!< SCU_T::PNSSET4: I2C0 Mask */ + +#define SCU_PNSSET4_I2C1_Pos (1) /*!< SCU_T::PNSSET4: I2C1 Position */ +#define SCU_PNSSET4_I2C1_Msk (0x1ul << SCU_PNSSET4_I2C1_Pos) /*!< SCU_T::PNSSET4: I2C1 Mask */ + +#define SCU_PNSSET4_I2C2_Pos (2) /*!< SCU_T::PNSSET4: I2C2 Position */ +#define SCU_PNSSET4_I2C2_Msk (0x1ul << SCU_PNSSET4_I2C2_Pos) /*!< SCU_T::PNSSET4: I2C2 Mask */ + +#define SCU_PNSSET4_SC0_Pos (16) /*!< SCU_T::PNSSET4: SC0 Position */ +#define SCU_PNSSET4_SC0_Msk (0x1ul << SCU_PNSSET4_SC0_Pos) /*!< SCU_T::PNSSET4: SC0 Mask */ + +#define SCU_PNSSET4_SC1_Pos (17) /*!< SCU_T::PNSSET4: SC1 Position */ +#define SCU_PNSSET4_SC1_Msk (0x1ul << SCU_PNSSET4_SC1_Pos) /*!< SCU_T::PNSSET4: SC1 Mask */ + +#define SCU_PNSSET4_SC2_Pos (18) /*!< SCU_T::PNSSET4: SC2 Position */ +#define SCU_PNSSET4_SC2_Msk (0x1ul << SCU_PNSSET4_SC2_Pos) /*!< SCU_T::PNSSET4: SC2 Mask */ + +#define SCU_PNSSET5_CAN0_Pos (0) /*!< SCU_T::PNSSET5: CAN0 Position */ +#define SCU_PNSSET5_CAN0_Msk (0x1ul << SCU_PNSSET5_CAN0_Pos) /*!< SCU_T::PNSSET5: CAN0 Mask */ + +#define SCU_PNSSET5_QEI0_Pos (16) /*!< SCU_T::PNSSET5: QEI0 Position */ +#define SCU_PNSSET5_QEI0_Msk (0x1ul << SCU_PNSSET5_QEI0_Pos) /*!< SCU_T::PNSSET5: QEI0 Mask */ + +#define SCU_PNSSET5_QEI1_Pos (17) /*!< SCU_T::PNSSET5: QEI1 Position */ +#define SCU_PNSSET5_QEI1_Msk (0x1ul << SCU_PNSSET5_QEI1_Pos) /*!< SCU_T::PNSSET5: QEI1 Mask */ + +#define SCU_PNSSET5_ECAP0_Pos (20) /*!< SCU_T::PNSSET5: ECAP0 Position */ +#define SCU_PNSSET5_ECAP0_Msk (0x1ul << SCU_PNSSET5_ECAP0_Pos) /*!< SCU_T::PNSSET5: ECAP0 Mask */ + +#define SCU_PNSSET5_ECAP1_Pos (21) /*!< SCU_T::PNSSET5: ECAP1 Position */ +#define SCU_PNSSET5_ECAP1_Msk (0x1ul << SCU_PNSSET5_ECAP1_Pos) /*!< SCU_T::PNSSET5: ECAP1 Mask */ + +#define SCU_PNSSET5_TRNG_Pos (25) /*!< SCU_T::PNSSET5: TRNG Position */ +#define SCU_PNSSET5_TRNG_Msk (0x1ul << SCU_PNSSET5_TRNG_Pos) /*!< SCU_T::PNSSET5: TRNG Mask */ + +#define SCU_PNSSET5_LCD_Pos (27) /*!< SCU_T::PNSSET5: LCD Position */ +#define SCU_PNSSET5_LCD_Msk (0x1ul << SCU_PNSSET5_LCD_Pos) /*!< SCU_T::PNSSET5: LCD Mask */ + +#define SCU_PNSSET6_USBD_Pos (0) /*!< SCU_T::PNSSET6: USBD Position */ +#define SCU_PNSSET6_USBD_Msk (0x1ul << SCU_PNSSET6_USBD_Pos) /*!< SCU_T::PNSSET6: USBD Mask */ + +#define SCU_PNSSET6_USCI0_Pos (16) /*!< SCU_T::PNSSET6: USCI0 Position */ +#define SCU_PNSSET6_USCI0_Msk (0x1ul << SCU_PNSSET6_USCI0_Pos) /*!< SCU_T::PNSSET6: USCI0 Mask */ + +#define SCU_PNSSET6_USCI1_Pos (17) /*!< SCU_T::PNSSET6: USCI1 Position */ +#define SCU_PNSSET6_USCI1_Msk (0x1ul << SCU_PNSSET6_USCI1_Pos) /*!< SCU_T::PNSSET6: USCI1 Mask */ + +#define SCU_IONSSET_PA_Pos (0) /*!< SCU_T::IONSSET: PA Position */ +#define SCU_IONSSET_PA_Msk (0x1ul << SCU_IONSSET_PA_Pos) /*!< SCU_T::IONSSET: PA Mask */ + +#define SCU_IONSSET_PB_Pos (1) /*!< SCU_T::IONSSET: PB Position */ +#define SCU_IONSSET_PB_Msk (0x1ul << SCU_IONSSET_PB_Pos) /*!< SCU_T::IONSSET: PB Mask */ + +#define SCU_IONSSET_PC_Pos (2) /*!< SCU_T::IONSSET: PC Position */ +#define SCU_IONSSET_PC_Msk (0x1ul << SCU_IONSSET_PC_Pos) /*!< SCU_T::IONSSET: PC Mask */ + +#define SCU_IONSSET_PD_Pos (3) /*!< SCU_T::IONSSET: PD Position */ +#define SCU_IONSSET_PD_Msk (0x1ul << SCU_IONSSET_PD_Pos) /*!< SCU_T::IONSSET: PD Mask */ + +#define SCU_IONSSET_PE_Pos (4) /*!< SCU_T::IONSSET: PE Position */ +#define SCU_IONSSET_PE_Msk (0x1ul << SCU_IONSSET_PE_Pos) /*!< SCU_T::IONSSET: PE Mask */ + +#define SCU_IONSSET_PF_Pos (5) /*!< SCU_T::IONSSET: PF Position */ +#define SCU_IONSSET_PF_Msk (0x1ul << SCU_IONSSET_PF_Pos) /*!< SCU_T::IONSSET: PF Mask */ + +#define SCU_IONSSET_PG_Pos (6) /*!< SCU_T::IONSSET: PG Position */ +#define SCU_IONSSET_PG_Msk (0x1ul << SCU_IONSSET_PG_Pos) /*!< SCU_T::IONSSET: PG Mask */ + +#define SCU_IONSSET_PH_Pos (7) /*!< SCU_T::IONSSET: PH Position */ +#define SCU_IONSSET_PH_Msk (0x1ul << SCU_IONSSET_PH_Pos) /*!< SCU_T::IONSSET: PH Mask */ + +#define SCU_SRAMNSSET_SECn_Pos (0) /*!< SCU_T::SRAMNSSET: SECn Position */ +#define SCU_SRAMNSSET_SECn_Msk (0xffful << SCU_SRAMNSSET_SECn_Pos) /*!< SCU_T::SRAMNSSET: SECn Mask */ + +#define SCU_FNSADDR_FNSADDR_Pos (0) /*!< SCU_T::FNSADDR: FNSADDR Position */ +#define SCU_FNSADDR_FNSADDR_Msk (0xfffffffful << SCU_FNSADDR_FNSADDR_Pos) /*!< SCU_T::FNSADDR: FNSADDR Mask */ + +#define SCU_SVIOIEN_APB0IEN_Pos (0) /*!< SCU_T::SVIOIEN: APB0IEN Position */ +#define SCU_SVIOIEN_APB0IEN_Msk (0x1ul << SCU_SVIOIEN_APB0IEN_Pos) /*!< SCU_T::SVIOIEN: APB0IEN Mask */ + +#define SCU_SVIOIEN_APB1IEN_Pos (1) /*!< SCU_T::SVIOIEN: APB1IEN Position */ +#define SCU_SVIOIEN_APB1IEN_Msk (0x1ul << SCU_SVIOIEN_APB1IEN_Pos) /*!< SCU_T::SVIOIEN: APB1IEN Mask */ + +#define SCU_SVIOIEN_GPIOIEN_Pos (4) /*!< SCU_T::SVIOIEN: GPIOIEN Position */ +#define SCU_SVIOIEN_GPIOIEN_Msk (0x1ul << SCU_SVIOIEN_GPIOIEN_Pos) /*!< SCU_T::SVIOIEN: GPIOIEN Mask */ + +#define SCU_SVIOIEN_EBIIEN_Pos (5) /*!< SCU_T::SVIOIEN: EBIIEN Position */ +#define SCU_SVIOIEN_EBIIEN_Msk (0x1ul << SCU_SVIOIEN_EBIIEN_Pos) /*!< SCU_T::SVIOIEN: EBIIEN Mask */ + +#define SCU_SVIOIEN_USBHIEN_Pos (6) /*!< SCU_T::SVIOIEN: USBHIEN Position */ +#define SCU_SVIOIEN_USBHIEN_Msk (0x1ul << SCU_SVIOIEN_USBHIEN_Pos) /*!< SCU_T::SVIOIEN: USBHIEN Mask */ + +#define SCU_SVIOIEN_CRCIEN_Pos (7) /*!< SCU_T::SVIOIEN: CRCIEN Position */ +#define SCU_SVIOIEN_CRCIEN_Msk (0x1ul << SCU_SVIOIEN_CRCIEN_Pos) /*!< SCU_T::SVIOIEN: CRCIEN Mask */ + +#define SCU_SVIOIEN_SDH0IEN_Pos (8) /*!< SCU_T::SVIOIEN: SDH0IEN Position */ +#define SCU_SVIOIEN_SDH0IEN_Msk (0x1ul << SCU_SVIOIEN_SDH0IEN_Pos) /*!< SCU_T::SVIOIEN: SDH0IEN Mask */ + +#define SCU_SVIOIEN_PDMA0IEN_Pos (10) /*!< SCU_T::SVIOIEN: PDMA0IEN Position */ +#define SCU_SVIOIEN_PDMA0IEN_Msk (0x1ul << SCU_SVIOIEN_PDMA0IEN_Pos) /*!< SCU_T::SVIOIEN: PDMA0IEN Mask */ + +#define SCU_SVIOIEN_PDMA1IEN_Pos (11) /*!< SCU_T::SVIOIEN: PDMA1IEN Position */ +#define SCU_SVIOIEN_PDMA1IEN_Msk (0x1ul << SCU_SVIOIEN_PDMA1IEN_Pos) /*!< SCU_T::SVIOIEN: PDMA1IEN Mask */ + +#define SCU_SVIOIEN_SRAM0IEN_Pos (12) /*!< SCU_T::SVIOIEN: SRAM0IEN Position */ +#define SCU_SVIOIEN_SRAM0IEN_Msk (0x1ul << SCU_SVIOIEN_SRAM0IEN_Pos) /*!< SCU_T::SVIOIEN: SRAM0IEN Mask */ + +#define SCU_SVIOIEN_SRAM1IEN_Pos (13) /*!< SCU_T::SVIOIEN: SRAM1IEN Position */ +#define SCU_SVIOIEN_SRAM1IEN_Msk (0x1ul << SCU_SVIOIEN_SRAM1IEN_Pos) /*!< SCU_T::SVIOIEN: SRAM1IEN Mask */ + +#define SCU_SVIOIEN_FMCIEN_Pos (14) /*!< SCU_T::SVIOIEN: FMCIEN Position */ +#define SCU_SVIOIEN_FMCIEN_Msk (0x1ul << SCU_SVIOIEN_FMCIEN_Pos) /*!< SCU_T::SVIOIEN: FMCIEN Mask */ + +#define SCU_SVIOIEN_FLASHIEN_Pos (15) /*!< SCU_T::SVIOIEN: FLASHIEN Position */ +#define SCU_SVIOIEN_FLASHIEN_Msk (0x1ul << SCU_SVIOIEN_FLASHIEN_Pos) /*!< SCU_T::SVIOIEN: FLASHIEN Mask */ + +#define SCU_SVIOIEN_SCUIEN_Pos (16) /*!< SCU_T::SVIOIEN: SCUIEN Position */ +#define SCU_SVIOIEN_SCUIEN_Msk (0x1ul << SCU_SVIOIEN_SCUIEN_Pos) /*!< SCU_T::SVIOIEN: SCUIEN Mask */ + +#define SCU_SVIOIEN_SYSIEN_Pos (17) /*!< SCU_T::SVIOIEN: SYSIEN Position */ +#define SCU_SVIOIEN_SYSIEN_Msk (0x1ul << SCU_SVIOIEN_SYSIEN_Pos) /*!< SCU_T::SVIOIEN: SYSIEN Mask */ + +#define SCU_SVIOIEN_CRPTIEN_Pos (18) /*!< SCU_T::SVIOIEN: CRPTIEN Position */ +#define SCU_SVIOIEN_CRPTIEN_Msk (0x1ul << SCU_SVIOIEN_CRPTIEN_Pos) /*!< SCU_T::SVIOIEN: CRPTIEN Mask */ + +#define SCU_SVIOIEN_KSIEN_Pos (19) /*!< SCU_T::SVIOIEN: KSIEN Position */ +#define SCU_SVIOIEN_KSIEN_Msk (0x1ul << SCU_SVIOIEN_KSIEN_Pos) /*!< SCU_T::SVIOIEN: KSIEN Mask */ + +#define SCU_SVINTSTS_APB0IF_Pos (0) /*!< SCU_T::SVINTSTS: APB0IF Position */ +#define SCU_SVINTSTS_APB0IF_Msk (0x1ul << SCU_SVINTSTS_APB0IF_Pos) /*!< SCU_T::SVINTSTS: APB0IF Mask */ + +#define SCU_SVINTSTS_APB1IF_Pos (1) /*!< SCU_T::SVINTSTS: APB1IF Position */ +#define SCU_SVINTSTS_APB1IF_Msk (0x1ul << SCU_SVINTSTS_APB1IF_Pos) /*!< SCU_T::SVINTSTS: APB1IF Mask */ + +#define SCU_SVINTSTS_GPIOIF_Pos (4) /*!< SCU_T::SVINTSTS: GPIOIF Position */ +#define SCU_SVINTSTS_GPIOIF_Msk (0x1ul << SCU_SVINTSTS_GPIOIF_Pos) /*!< SCU_T::SVINTSTS: GPIOIF Mask */ + +#define SCU_SVINTSTS_EBIIF_Pos (5) /*!< SCU_T::SVINTSTS: EBIIF Position */ +#define SCU_SVINTSTS_EBIIF_Msk (0x1ul << SCU_SVINTSTS_EBIIF_Pos) /*!< SCU_T::SVINTSTS: EBIIF Mask */ + +#define SCU_SVINTSTS_USBHIF_Pos (6) /*!< SCU_T::SVINTSTS: USBHIF Position */ +#define SCU_SVINTSTS_USBHIF_Msk (0x1ul << SCU_SVINTSTS_USBHIF_Pos) /*!< SCU_T::SVINTSTS: USBHIF Mask */ + +#define SCU_SVINTSTS_CRCIF_Pos (7) /*!< SCU_T::SVINTSTS: CRCIF Position */ +#define SCU_SVINTSTS_CRCIF_Msk (0x1ul << SCU_SVINTSTS_CRCIF_Pos) /*!< SCU_T::SVINTSTS: CRCIF Mask */ + +#define SCU_SVINTSTS_SDH0IF_Pos (8) /*!< SCU_T::SVINTSTS: SDH0IF Position */ +#define SCU_SVINTSTS_SDH0IF_Msk (0x1ul << SCU_SVINTSTS_SDH0IF_Pos) /*!< SCU_T::SVINTSTS: SDH0IF Mask */ + +#define SCU_SVINTSTS_PDMA0IF_Pos (10) /*!< SCU_T::SVINTSTS: PDMA0IF Position */ +#define SCU_SVINTSTS_PDMA0IF_Msk (0x1ul << SCU_SVINTSTS_PDMA0IF_Pos) /*!< SCU_T::SVINTSTS: PDMA0IF Mask */ + +#define SCU_SVINTSTS_PDMA1IF_Pos (11) /*!< SCU_T::SVINTSTS: PDMA1IF Position */ +#define SCU_SVINTSTS_PDMA1IF_Msk (0x1ul << SCU_SVINTSTS_PDMA1IF_Pos) /*!< SCU_T::SVINTSTS: PDMA1IF Mask */ + +#define SCU_SVINTSTS_SRAM0IF_Pos (12) /*!< SCU_T::SVINTSTS: SRAM0IF Position */ +#define SCU_SVINTSTS_SRAM0IF_Msk (0x1ul << SCU_SVINTSTS_SRAM0IF_Pos) /*!< SCU_T::SVINTSTS: SRAM0IF Mask */ + +#define SCU_SVINTSTS_SRAM1IF_Pos (13) /*!< SCU_T::SVINTSTS: SRAM1IF Position */ +#define SCU_SVINTSTS_SRAM1IF_Msk (0x1ul << SCU_SVINTSTS_SRAM1IF_Pos) /*!< SCU_T::SVINTSTS: SRAM1IF Mask */ + +#define SCU_SVINTSTS_FMCIF_Pos (14) /*!< SCU_T::SVINTSTS: FMCIF Position */ +#define SCU_SVINTSTS_FMCIF_Msk (0x1ul << SCU_SVINTSTS_FMCIF_Pos) /*!< SCU_T::SVINTSTS: FMCIF Mask */ + +#define SCU_SVINTSTS_FLASHIF_Pos (15) /*!< SCU_T::SVINTSTS: FLASHIF Position */ +#define SCU_SVINTSTS_FLASHIF_Msk (0x1ul << SCU_SVINTSTS_FLASHIF_Pos) /*!< SCU_T::SVINTSTS: FLASHIF Mask */ + +#define SCU_SVINTSTS_SCUIF_Pos (16) /*!< SCU_T::SVINTSTS: SCUIF Position */ +#define SCU_SVINTSTS_SCUIF_Msk (0x1ul << SCU_SVINTSTS_SCUIF_Pos) /*!< SCU_T::SVINTSTS: SCUIF Mask */ + +#define SCU_SVINTSTS_SYSIF_Pos (17) /*!< SCU_T::SVINTSTS: SYSIF Position */ +#define SCU_SVINTSTS_SYSIF_Msk (0x1ul << SCU_SVINTSTS_SYSIF_Pos) /*!< SCU_T::SVINTSTS: SYSIF Mask */ + +#define SCU_SVINTSTS_CRPTIF_Pos (18) /*!< SCU_T::SVINTSTS: CRPTIF Position */ +#define SCU_SVINTSTS_CRPTIF_Msk (0x1ul << SCU_SVINTSTS_CRPTIF_Pos) /*!< SCU_T::SVINTSTS: CRPTIF Mask */ + +#define SCU_SVINTSTS_KSIF_Pos (19) /*!< SCU_T::SVINTSTS: KSIF Position */ +#define SCU_SVINTSTS_KSIF_Msk (0x1ul << SCU_SVINTSTS_KSIF_Pos) /*!< SCU_T::SVINTSTS: KSIF Mask */ + +#define SCU_APB0VSRC_MASTER_Pos (0) /*!< SCU_T::APB0VSRC: MASTER Position */ +#define SCU_APB0VSRC_MASTER_Msk (0xful << SCU_APB0VSRC_MASTER_Pos) /*!< SCU_T::APB0VSRC: MASTER Mask */ + +#define SCU_APB0VA_VIOADDR_Pos (0) /*!< SCU_T::APB0VA: VIOADDR Position */ +#define SCU_APB0VA_VIOADDR_Msk (0xfffffffful << SCU_APB0VA_VIOADDR_Pos) /*!< SCU_T::APB0VA: VIOADDR Mask */ + +#define SCU_APB1VSRC_MASTER_Pos (0) /*!< SCU_T::APB1VSRC: MASTER Position */ +#define SCU_APB1VSRC_MASTER_Msk (0xful << SCU_APB1VSRC_MASTER_Pos) /*!< SCU_T::APB1VSRC: MASTER Mask */ + +#define SCU_APB1VA_VIOADDR_Pos (0) /*!< SCU_T::APB1VA: VIOADDR Position */ +#define SCU_APB1VA_VIOADDR_Msk (0xfffffffful << SCU_APB1VA_VIOADDR_Pos) /*!< SCU_T::APB1VA: VIOADDR Mask */ + +#define SCU_GPIOVSRC_MASTER_Pos (0) /*!< SCU_T::GPIOVSRC: MASTER Position */ +#define SCU_GPIOVSRC_MASTER_Msk (0xful << SCU_GPIOVSRC_MASTER_Pos) /*!< SCU_T::GPIOVSRC: MASTER Mask */ + +#define SCU_GPIOVA_VIOADDR_Pos (0) /*!< SCU_T::GPIOVA: VIOADDR Position */ +#define SCU_GPIOVA_VIOADDR_Msk (0xfffffffful << SCU_GPIOVA_VIOADDR_Pos) /*!< SCU_T::GPIOVA: VIOADDR Mask */ + +#define SCU_EBIVSRC_MASTER_Pos (0) /*!< SCU_T::EBIVSRC: MASTER Position */ +#define SCU_EBIVSRC_MASTER_Msk (0xful << SCU_EBIVSRC_MASTER_Pos) /*!< SCU_T::EBIVSRC: MASTER Mask */ + +#define SCU_EBIVA_VIOADDR_Pos (0) /*!< SCU_T::EBIVA: VIOADDR Position */ +#define SCU_EBIVA_VIOADDR_Msk (0xfffffffful << SCU_EBIVA_VIOADDR_Pos) /*!< SCU_T::EBIVA: VIOADDR Mask */ + +#define SCU_USBHVSRC_MASTER_Pos (0) /*!< SCU_T::USBHVSRC: MASTER Position */ +#define SCU_USBHVSRC_MASTER_Msk (0xful << SCU_USBHVSRC_MASTER_Pos) /*!< SCU_T::USBHVSRC: MASTER Mask */ + +#define SCU_USBHVA_VIOADDR_Pos (0) /*!< SCU_T::USBHVA: VIOADDR Position */ +#define SCU_USBHVA_VIOADDR_Msk (0xfffffffful << SCU_USBHVA_VIOADDR_Pos) /*!< SCU_T::USBHVA: VIOADDR Mask */ + +#define SCU_CRCVSRC_MASTER_Pos (0) /*!< SCU_T::CRCVSRC: MASTER Position */ +#define SCU_CRCVSRC_MASTER_Msk (0xful << SCU_CRCVSRC_MASTER_Pos) /*!< SCU_T::CRCVSRC: MASTER Mask */ + +#define SCU_CRCVA_VIOADDR_Pos (0) /*!< SCU_T::CRCVA: VIOADDR Position */ +#define SCU_CRCVA_VIOADDR_Msk (0xfffffffful << SCU_CRCVA_VIOADDR_Pos) /*!< SCU_T::CRCVA: VIOADDR Mask */ + +#define SCU_SD0VSRC_MASTER_Pos (0) /*!< SCU_T::SD0VSRC: MASTER Position */ +#define SCU_SD0VSRC_MASTER_Msk (0xful << SCU_SD0VSRC_MASTER_Pos) /*!< SCU_T::SD0VSRC: MASTER Mask */ + +#define SCU_SD0VA_VIOADDR_Pos (0) /*!< SCU_T::SD0VA: VIOADDR Position */ +#define SCU_SD0VA_VIOADDR_Msk (0xfffffffful << SCU_SD0VA_VIOADDR_Pos) /*!< SCU_T::SD0VA: VIOADDR Mask */ + +#define SCU_PDMA0VSRC_MASTER_Pos (0) /*!< SCU_T::PDMA0VSRC: MASTER Position */ +#define SCU_PDMA0VSRC_MASTER_Msk (0xful << SCU_PDMA0VSRC_MASTER_Pos) /*!< SCU_T::PDMA0VSRC: MASTER Mask */ + +#define SCU_PDMA0VA_VIOADDR_Pos (0) /*!< SCU_T::PDMA0VA: VIOADDR Position */ +#define SCU_PDMA0VA_VIOADDR_Msk (0xfffffffful << SCU_PDMA0VA_VIOADDR_Pos) /*!< SCU_T::PDMA0VA: VIOADDR Mask */ + +#define SCU_PDMA1VSRC_MASTER_Pos (0) /*!< SCU_T::PDMA1VSRC: MASTER Position */ +#define SCU_PDMA1VSRC_MASTER_Msk (0xful << SCU_PDMA1VSRC_MASTER_Pos) /*!< SCU_T::PDMA1VSRC: MASTER Mask */ + +#define SCU_PDMA1VA_VIOADDR_Pos (0) /*!< SCU_T::PDMA1VA: VIOADDR Position */ +#define SCU_PDMA1VA_VIOADDR_Msk (0xfffffffful << SCU_PDMA1VA_VIOADDR_Pos) /*!< SCU_T::PDMA1VA: VIOADDR Mask */ + +#define SCU_SRAM0VSRC_MASTER_Pos (0) /*!< SCU_T::SRAM0VSRC: MASTER Position */ +#define SCU_SRAM0VSRC_MASTER_Msk (0xful << SCU_SRAM0VSRC_MASTER_Pos) /*!< SCU_T::SRAM0VSRC: MASTER Mask */ + +#define SCU_SRAM0VA_VIOADDR_Pos (0) /*!< SCU_T::SRAM0VA: VIOADDR Position */ +#define SCU_SRAM0VA_VIOADDR_Msk (0xfffffffful << SCU_SRAM0VA_VIOADDR_Pos) /*!< SCU_T::SRAM0VA: VIOADDR Mask */ + +#define SCU_SRAM1VSRC_MASTER_Pos (0) /*!< SCU_T::SRAM1VSRC: MASTER Position */ +#define SCU_SRAM1VSRC_MASTER_Msk (0xful << SCU_SRAM1VSRC_MASTER_Pos) /*!< SCU_T::SRAM1VSRC: MASTER Mask */ + +#define SCU_SRAM1VA_VIOADDR_Pos (0) /*!< SCU_T::SRAM1VA: VIOADDR Position */ +#define SCU_SRAM1VA_VIOADDR_Msk (0xfffffffful << SCU_SRAM1VA_VIOADDR_Pos) /*!< SCU_T::SRAM1VA: VIOADDR Mask */ + +#define SCU_FMCVSRC_MASTER_Pos (0) /*!< SCU_T::FMCVSRC: MASTER Position */ +#define SCU_FMCVSRC_MASTER_Msk (0xful << SCU_FMCVSRC_MASTER_Pos) /*!< SCU_T::FMCVSRC: MASTER Mask */ + +#define SCU_FMCVA_VIOADDR_Pos (0) /*!< SCU_T::FMCVA: VIOADDR Position */ +#define SCU_FMCVA_VIOADDR_Msk (0xfffffffful << SCU_FMCVA_VIOADDR_Pos) /*!< SCU_T::FMCVA: VIOADDR Mask */ + +#define SCU_FLASHVSRC_MASTER_Pos (0) /*!< SCU_T::FLASHVSRC: MASTER Position */ +#define SCU_FLASHVSRC_MASTER_Msk (0xful << SCU_FLASHVSRC_MASTER_Pos) /*!< SCU_T::FLASHVSRC: MASTER Mask */ + +#define SCU_FLASHVA_VIOADDR_Pos (0) /*!< SCU_T::FLASHVA: VIOADDR Position */ +#define SCU_FLASHVA_VIOADDR_Msk (0xfffffffful << SCU_FLASHVA_VIOADDR_Pos) /*!< SCU_T::FLASHVA: VIOADDR Mask */ + +#define SCU_SCUVSRC_MASTER_Pos (0) /*!< SCU_T::SCUVSRC: MASTER Position */ +#define SCU_SCUVSRC_MASTER_Msk (0xful << SCU_SCUVSRC_MASTER_Pos) /*!< SCU_T::SCUVSRC: MASTER Mask */ + +#define SCU_SCUVA_VIOADDR_Pos (0) /*!< SCU_T::SCUVA: VIOADDR Position */ +#define SCU_SCUVA_VIOADDR_Msk (0xfffffffful << SCU_SCUVA_VIOADDR_Pos) /*!< SCU_T::SCUVA: VIOADDR Mask */ + +#define SCU_SYSVSRC_MASTER_Pos (0) /*!< SCU_T::SYSVSRC: MASTER Position */ +#define SCU_SYSVSRC_MASTER_Msk (0xful << SCU_SYSVSRC_MASTER_Pos) /*!< SCU_T::SYSVSRC: MASTER Mask */ + +#define SCU_SYSVA_VIOADDR_Pos (0) /*!< SCU_T::SYSVA: VIOADDR Position */ +#define SCU_SYSVA_VIOADDR_Msk (0xfffffffful << SCU_SYSVA_VIOADDR_Pos) /*!< SCU_T::SYSVA: VIOADDR Mask */ + +#define SCU_CRPTVSRC_MASTER_Pos (0) /*!< SCU_T::CRPTVSRC: MASTER Position */ +#define SCU_CRPTVSRC_MASTER_Msk (0xful << SCU_CRPTVSRC_MASTER_Pos) /*!< SCU_T::CRPTVSRC: MASTER Mask */ + +#define SCU_CRPTVA_VIOADDR_Pos (0) /*!< SCU_T::CRPTVA: VIOADDR Position */ +#define SCU_CRPTVA_VIOADDR_Msk (0xfffffffful << SCU_CRPTVA_VIOADDR_Pos) /*!< SCU_T::CRPTVA: VIOADDR Mask */ + +#define SCU_KSVSRC_MASTER_Pos (0) /*!< SCU_T::KSVSRC: MASTER Position */ +#define SCU_KSVSRC_MASTER_Msk (0xful << SCU_KSVSRC_MASTER_Pos) /*!< SCU_T::KSVSRC: MASTER Mask */ + +#define SCU_KSVA_VIOADDR_Pos (0) /*!< SCU_T::KSVA: VIOADDR Position */ +#define SCU_KSVA_VIOADDR_Msk (0xfffffffful << SCU_KSVA_VIOADDR_Pos) /*!< SCU_T::KSVA: VIOADDR Mask */ + +#define SCU_SRAM2VSRC_MASTER_Pos (0) /*!< SCU_T::SRAM2VSRC: MASTER Position */ +#define SCU_SRAM2VSRC_MASTER_Msk (0xful << SCU_SRAM2VSRC_MASTER_Pos) /*!< SCU_T::SRAM2VSRC: MASTER Mask */ + +#define SCU_SRAM2VA_VIOADDR_Pos (0) /*!< SCU_T::SRAM2VA: VIOADDR Position */ +#define SCU_SRAM2VA_VIOADDR_Msk (0xfffffffful << SCU_SRAM2VA_VIOADDR_Pos) /*!< SCU_T::SRAM2VA: VIOADDR Mask */ + +#define SCU_SINFAEN_SCUSIAEN_Pos (0) /*!< SCU_T::SINFAEN: SCUSIAEN Position */ +#define SCU_SINFAEN_SCUSIAEN_Msk (0x1ul << SCU_SINFAEN_SCUSIAEN_Pos) /*!< SCU_T::SINFAEN: SCUSIAEN Mask */ + +#define SCU_SINFAEN_SYSSIAEN_Pos (1) /*!< SCU_T::SINFAEN: SYSSIAEN Position */ +#define SCU_SINFAEN_SYSSIAEN_Msk (0x1ul << SCU_SINFAEN_SYSSIAEN_Pos) /*!< SCU_T::SINFAEN: SYSSIAEN Mask */ + +#define SCU_SINFAEN_FMCSIAEN_Pos (2) /*!< SCU_T::SINFAEN: FMCSIAEN Position */ +#define SCU_SINFAEN_FMCSIAEN_Msk (0x1ul << SCU_SINFAEN_FMCSIAEN_Pos) /*!< SCU_T::SINFAEN: FMCSIAEN Mask */ + +#define SCU_PNPSET0_SYS_Pos (0) /*!< SCU_T::PNPSET0: SYS Position */ +#define SCU_PNPSET0_SYS_Msk (0x1ul << SCU_PNPSET0_SYS_Pos) /*!< SCU_T::PNPSET0: SYS Mask */ + +#define SCU_PNPSET0_PDMA0_Pos (8) /*!< SCU_T::PNPSET0: PDMA0 Position */ +#define SCU_PNPSET0_PDMA0_Msk (0x1ul << SCU_PNPSET0_PDMA0_Pos) /*!< SCU_T::PNPSET0: PDMA0 Mask */ + +#define SCU_PNPSET0_USBH_Pos (9) /*!< SCU_T::PNPSET0: USBH Position */ +#define SCU_PNPSET0_USBH_Msk (0x1ul << SCU_PNPSET0_USBH_Pos) /*!< SCU_T::PNPSET0: USBH Mask */ + +#define SCU_PNPSET0_FMC_Pos (12) /*!< SCU_T::PNPSET0: FMC Position */ +#define SCU_PNPSET0_FMC_Msk (0x1ul << SCU_PNPSET0_FMC_Pos) /*!< SCU_T::PNPSET0: FMC Mask */ + +#define SCU_PNPSET0_SDH0_Pos (13) /*!< SCU_T::PNPSET0: SDH0 Position */ +#define SCU_PNPSET0_SDH0_Msk (0x1ul << SCU_PNPSET0_SDH0_Pos) /*!< SCU_T::PNPSET0: SDH0 Mask */ + +#define SCU_PNPSET0_EBI_Pos (16) /*!< SCU_T::PNPSET0: EBI Position */ +#define SCU_PNPSET0_EBI_Msk (0x1ul << SCU_PNPSET0_EBI_Pos) /*!< SCU_T::PNPSET0: EBI Mask */ + +#define SCU_PNPSET0_PDMA1_Pos (24) /*!< SCU_T::PNPSET0: PDMA1 Position */ +#define SCU_PNPSET0_PDMA1_Msk (0x1ul << SCU_PNPSET0_PDMA1_Pos) /*!< SCU_T::PNPSET0: PDMA1 Mask */ + +#define SCU_PNPSET1_SCU_Pos (15) /*!< SCU_T::PNPSET1: SCU Position */ +#define SCU_PNPSET1_SCU_Msk (0x1ul << SCU_PNPSET1_SCU_Pos) /*!< SCU_T::PNPSET1: SCU Mask */ + +#define SCU_PNPSET1_CRC_Pos (17) /*!< SCU_T::PNPSET1: CRC Position */ +#define SCU_PNPSET1_CRC_Msk (0x1ul << SCU_PNPSET1_CRC_Pos) /*!< SCU_T::PNPSET1: CRC Mask */ + +#define SCU_PNPSET1_CRPT_Pos (18) /*!< SCU_T::PNPSET1: CRPT Position */ +#define SCU_PNPSET1_CRPT_Msk (0x1ul << SCU_PNPSET1_CRPT_Pos) /*!< SCU_T::PNPSET1: CRPT Mask */ + +#define SCU_PNPSET1_KS_Pos (21) /*!< SCU_T::PNPSET1: KS Position */ +#define SCU_PNPSET1_KS_Msk (0x1ul << SCU_PNPSET1_KS_Pos) /*!< SCU_T::PNPSET1: KS Mask */ + +#define SCU_PNPSET2_WDT_Pos (0) /*!< SCU_T::PNPSET2: WDT Position */ +#define SCU_PNPSET2_WDT_Msk (0x1ul << SCU_PNPSET2_WDT_Pos) /*!< SCU_T::PNPSET2: WDT Mask */ + +#define SCU_PNPSET2_RTC_Pos (1) /*!< SCU_T::PNPSET2: RTC Position */ +#define SCU_PNPSET2_RTC_Msk (0x1ul << SCU_PNPSET2_RTC_Pos) /*!< SCU_T::PNPSET2: RTC Mask */ + +#define SCU_PNPSET2_EWDT_Pos (2) /*!< SCU_T::PNPSET2: EWDT Position */ +#define SCU_PNPSET2_EWDT_Msk (0x1ul << SCU_PNPSET2_EWDT_Pos) /*!< SCU_T::PNPSET2: EWDT Mask */ + +#define SCU_PNPSET2_EADC_Pos (3) /*!< SCU_T::PNPSET2: EADC Position */ +#define SCU_PNPSET2_EADC_Msk (0x1ul << SCU_PNPSET2_EADC_Pos) /*!< SCU_T::PNPSET2: EADC Mask */ + +#define SCU_PNPSET2_ACMP01_Pos (5) /*!< SCU_T::PNPSET2: ACMP01 Position */ +#define SCU_PNPSET2_ACMP01_Msk (0x1ul << SCU_PNPSET2_ACMP01_Pos) /*!< SCU_T::PNPSET2: ACMP01 Mask */ + +#define SCU_PNPSET2_DAC_Pos (7) /*!< SCU_T::PNPSET2: DAC Position */ +#define SCU_PNPSET2_DAC_Msk (0x1ul << SCU_PNPSET2_DAC_Pos) /*!< SCU_T::PNPSET2: DAC Mask */ + +#define SCU_PNPSET2_I2S0_Pos (8) /*!< SCU_T::PNPSET2: I2S0 Position */ +#define SCU_PNPSET2_I2S0_Msk (0x1ul << SCU_PNPSET2_I2S0_Pos) /*!< SCU_T::PNPSET2: I2S0 Mask */ + +#define SCU_PNPSET2_OTG_Pos (13) /*!< SCU_T::PNPSET2: OTG Position */ +#define SCU_PNPSET2_OTG_Msk (0x1ul << SCU_PNPSET2_OTG_Pos) /*!< SCU_T::PNPSET2: OTG Mask */ + +#define SCU_PNPSET2_TMR01_Pos (14) /*!< SCU_T::PNPSET2: TMR01 Position */ +#define SCU_PNPSET2_TMR01_Msk (0x7ul << SCU_PNPSET2_TMR01_Pos) /*!< SCU_T::PNPSET2: TMR01 Mask */ + +#define SCU_PNPSET2_TMR23_Pos (17) /*!< SCU_T::PNPSET2: TMR23 Position */ +#define SCU_PNPSET2_TMR23_Msk (0x1ul << SCU_PNPSET2_TMR23_Pos) /*!< SCU_T::PNPSET2: TMR23 Mask */ + +#define SCU_PNPSET2_EPWM0_Pos (24) /*!< SCU_T::PNPSET2: EPWM0 Position */ +#define SCU_PNPSET2_EPWM0_Msk (0x1ul << SCU_PNPSET2_EPWM0_Pos) /*!< SCU_T::PNPSET2: EPWM0 Mask */ + +#define SCU_PNPSET2_EPWM1_Pos (25) /*!< SCU_T::PNPSET2: EPWM1 Position */ +#define SCU_PNPSET2_EPWM1_Msk (0x1ul << SCU_PNPSET2_EPWM1_Pos) /*!< SCU_T::PNPSET2: EPWM1 Mask */ + +#define SCU_PNPSET2_BPWM0_Pos (26) /*!< SCU_T::PNPSET2: BPWM0 Position */ +#define SCU_PNPSET2_BPWM0_Msk (0x1ul << SCU_PNPSET2_BPWM0_Pos) /*!< SCU_T::PNPSET2: BPWM0 Mask */ + +#define SCU_PNPSET2_BPWM1_Pos (27) /*!< SCU_T::PNPSET2: BPWM1 Position */ +#define SCU_PNPSET2_BPWM1_Msk (0x1ul << SCU_PNPSET2_BPWM1_Pos) /*!< SCU_T::PNPSET2: BPWM1 Mask */ + +#define SCU_PNPSET3_QSPI0_Pos (0) /*!< SCU_T::PNPSET3: QSPI0 Position */ +#define SCU_PNPSET3_QSPI0_Msk (0x1ul << SCU_PNPSET3_QSPI0_Pos) /*!< SCU_T::PNPSET3: QSPI0 Mask */ + +#define SCU_PNPSET3_SPI0_Pos (1) /*!< SCU_T::PNPSET3: SPI0 Position */ +#define SCU_PNPSET3_SPI0_Msk (0x1ul << SCU_PNPSET3_SPI0_Pos) /*!< SCU_T::PNPSET3: SPI0 Mask */ + +#define SCU_PNPSET3_SPI1_Pos (2) /*!< SCU_T::PNPSET3: SPI1 Position */ +#define SCU_PNPSET3_SPI1_Msk (0x1ul << SCU_PNPSET3_SPI1_Pos) /*!< SCU_T::PNPSET3: SPI1 Mask */ + +#define SCU_PNPSET3_SPI2_Pos (3) /*!< SCU_T::PNPSET3: SPI2 Position */ +#define SCU_PNPSET3_SPI2_Msk (0x1ul << SCU_PNPSET3_SPI2_Pos) /*!< SCU_T::PNPSET3: SPI2 Mask */ + +#define SCU_PNPSET3_SPI3_Pos (4) /*!< SCU_T::PNPSET3: SPI3 Position */ +#define SCU_PNPSET3_SPI3_Msk (0x1ul << SCU_PNPSET3_SPI3_Pos) /*!< SCU_T::PNPSET3: SPI3 Mask */ + +#define SCU_PNPSET3_UART0_Pos (16) /*!< SCU_T::PNPSET3: UART0 Position */ +#define SCU_PNPSET3_UART0_Msk (0x1ul << SCU_PNPSET3_UART0_Pos) /*!< SCU_T::PNPSET3: UART0 Mask */ + +#define SCU_PNPSET3_UART1_Pos (17) /*!< SCU_T::PNPSET3: UART1 Position */ +#define SCU_PNPSET3_UART1_Msk (0x1ul << SCU_PNPSET3_UART1_Pos) /*!< SCU_T::PNPSET3: UART1 Mask */ + +#define SCU_PNPSET3_UART2_Pos (18) /*!< SCU_T::PNPSET3: UART2 Position */ +#define SCU_PNPSET3_UART2_Msk (0x1ul << SCU_PNPSET3_UART2_Pos) /*!< SCU_T::PNPSET3: UART2 Mask */ + +#define SCU_PNPSET3_UART3_Pos (19) /*!< SCU_T::PNPSET3: UART3 Position */ +#define SCU_PNPSET3_UART3_Msk (0x1ul << SCU_PNPSET3_UART3_Pos) /*!< SCU_T::PNPSET3: UART3 Mask */ + +#define SCU_PNPSET3_UART4_Pos (20) /*!< SCU_T::PNPSET3: UART4 Position */ +#define SCU_PNPSET3_UART4_Msk (0x1ul << SCU_PNPSET3_UART4_Pos) /*!< SCU_T::PNPSET3: UART4 Mask */ + +#define SCU_PNPSET3_UART5_Pos (21) /*!< SCU_T::PNPSET3: UART5 Position */ +#define SCU_PNPSET3_UART5_Msk (0x1ul << SCU_PNPSET3_UART5_Pos) /*!< SCU_T::PNPSET3: UART5 Mask */ + +#define SCU_PNPSET4_I2C0_Pos (0) /*!< SCU_T::PNPSET4: I2C0 Position */ +#define SCU_PNPSET4_I2C0_Msk (0x1ul << SCU_PNPSET4_I2C0_Pos) /*!< SCU_T::PNPSET4: I2C0 Mask */ + +#define SCU_PNPSET4_I2C1_Pos (1) /*!< SCU_T::PNPSET4: I2C1 Position */ +#define SCU_PNPSET4_I2C1_Msk (0x1ul << SCU_PNPSET4_I2C1_Pos) /*!< SCU_T::PNPSET4: I2C1 Mask */ + +#define SCU_PNPSET4_I2C2_Pos (2) /*!< SCU_T::PNPSET4: I2C2 Position */ +#define SCU_PNPSET4_I2C2_Msk (0x1ul << SCU_PNPSET4_I2C2_Pos) /*!< SCU_T::PNPSET4: I2C2 Mask */ + +#define SCU_PNPSET4_SC0_Pos (16) /*!< SCU_T::PNPSET4: SC0 Position */ +#define SCU_PNPSET4_SC0_Msk (0x1ul << SCU_PNPSET4_SC0_Pos) /*!< SCU_T::PNPSET4: SC0 Mask */ + +#define SCU_PNPSET4_SC1_Pos (17) /*!< SCU_T::PNPSET4: SC1 Position */ +#define SCU_PNPSET4_SC1_Msk (0x1ul << SCU_PNPSET4_SC1_Pos) /*!< SCU_T::PNPSET4: SC1 Mask */ + +#define SCU_PNPSET4_SC2_Pos (18) /*!< SCU_T::PNPSET4: SC2 Position */ +#define SCU_PNPSET4_SC2_Msk (0x1ul << SCU_PNPSET4_SC2_Pos) /*!< SCU_T::PNPSET4: SC2 Mask */ + +#define SCU_PNPSET5_CAN0_Pos (0) /*!< SCU_T::PNPSET5: CAN0 Position */ +#define SCU_PNPSET5_CAN0_Msk (0x1ul << SCU_PNPSET5_CAN0_Pos) /*!< SCU_T::PNPSET5: CAN0 Mask */ + +#define SCU_PNPSET5_QEI0_Pos (16) /*!< SCU_T::PNPSET5: QEI0 Position */ +#define SCU_PNPSET5_QEI0_Msk (0x1ul << SCU_PNPSET5_QEI0_Pos) /*!< SCU_T::PNPSET5: QEI0 Mask */ + +#define SCU_PNPSET5_QEI1_Pos (17) /*!< SCU_T::PNPSET5: QEI1 Position */ +#define SCU_PNPSET5_QEI1_Msk (0x1ul << SCU_PNPSET5_QEI1_Pos) /*!< SCU_T::PNPSET5: QEI1 Mask */ + +#define SCU_PNPSET5_ECAP0_Pos (20) /*!< SCU_T::PNPSET5: ECAP0 Position */ +#define SCU_PNPSET5_ECAP0_Msk (0x1ul << SCU_PNPSET5_ECAP0_Pos) /*!< SCU_T::PNPSET5: ECAP0 Mask */ + +#define SCU_PNPSET5_ECAP1_Pos (21) /*!< SCU_T::PNPSET5: ECAP1 Position */ +#define SCU_PNPSET5_ECAP1_Msk (0x1ul << SCU_PNPSET5_ECAP1_Pos) /*!< SCU_T::PNPSET5: ECAP1 Mask */ + +#define SCU_PNPSET5_TRNG_Pos (25) /*!< SCU_T::PNPSET5: TRNG Position */ +#define SCU_PNPSET5_TRNG_Msk (0x1ul << SCU_PNPSET5_TRNG_Pos) /*!< SCU_T::PNPSET5: TRNG Mask */ + +#define SCU_PNPSET5_LCD_Pos (27) /*!< SCU_T::PNPSET5: LCD Position */ +#define SCU_PNPSET5_LCD_Msk (0x1ul << SCU_PNPSET5_LCD_Pos) /*!< SCU_T::PNPSET5: LCD Mask */ + +#define SCU_PNPSET5_TAMPER_Pos (29) /*!< SCU_T::PNPSET5: TAMPER Position */ +#define SCU_PNPSET5_TAMPER_Msk (0x1ul << SCU_PNPSET5_TAMPER_Pos) /*!< SCU_T::PNPSET5: TAMPER Mask */ + +#define SCU_PNPSET6_USBD_Pos (0) /*!< SCU_T::PNPSET6: USBD Position */ +#define SCU_PNPSET6_USBD_Msk (0x1ul << SCU_PNPSET6_USBD_Pos) /*!< SCU_T::PNPSET6: USBD Mask */ + +#define SCU_PNPSET6_USCI0_Pos (16) /*!< SCU_T::PNPSET6: USCI0 Position */ +#define SCU_PNPSET6_USCI0_Msk (0x1ul << SCU_PNPSET6_USCI0_Pos) /*!< SCU_T::PNPSET6: USCI0 Mask */ + +#define SCU_PNPSET6_USCI1_Pos (17) /*!< SCU_T::PNPSET6: USCI1 Position */ +#define SCU_PNPSET6_USCI1_Msk (0x1ul << SCU_PNPSET6_USCI1_Pos) /*!< SCU_T::PNPSET6: USCI1 Mask */ + +#define SCU_IONPSET_PA_Pos (0) /*!< SCU_T::IONPSET: PA Position */ +#define SCU_IONPSET_PA_Msk (0x1ul << SCU_IONPSET_PA_Pos) /*!< SCU_T::IONPSET: PA Mask */ + +#define SCU_IONPSET_PB_Pos (1) /*!< SCU_T::IONPSET: PB Position */ +#define SCU_IONPSET_PB_Msk (0x1ul << SCU_IONPSET_PB_Pos) /*!< SCU_T::IONPSET: PB Mask */ + +#define SCU_IONPSET_PC_Pos (2) /*!< SCU_T::IONPSET: PC Position */ +#define SCU_IONPSET_PC_Msk (0x1ul << SCU_IONPSET_PC_Pos) /*!< SCU_T::IONPSET: PC Mask */ + +#define SCU_IONPSET_PD_Pos (3) /*!< SCU_T::IONPSET: PD Position */ +#define SCU_IONPSET_PD_Msk (0x1ul << SCU_IONPSET_PD_Pos) /*!< SCU_T::IONPSET: PD Mask */ + +#define SCU_IONPSET_PE_Pos (4) /*!< SCU_T::IONPSET: PE Position */ +#define SCU_IONPSET_PE_Msk (0x1ul << SCU_IONPSET_PE_Pos) /*!< SCU_T::IONPSET: PE Mask */ + +#define SCU_IONPSET_PF_Pos (5) /*!< SCU_T::IONPSET: PF Position */ +#define SCU_IONPSET_PF_Msk (0x1ul << SCU_IONPSET_PF_Pos) /*!< SCU_T::IONPSET: PF Mask */ + +#define SCU_IONPSET_PG_Pos (6) /*!< SCU_T::IONPSET: PG Position */ +#define SCU_IONPSET_PG_Msk (0x1ul << SCU_IONPSET_PG_Pos) /*!< SCU_T::IONPSET: PG Mask */ + +#define SCU_IONPSET_PH_Pos (7) /*!< SCU_T::IONPSET: PH Position */ +#define SCU_IONPSET_PH_Msk (0x1ul << SCU_IONPSET_PH_Pos) /*!< SCU_T::IONPSET: PH Mask */ + +#define SCU_SRAMNPSET_SECn_Pos (0) /*!< SCU_T::SRAMNPSET: SECn Position */ +#define SCU_SRAMNPSET_SECn_Msk (0xffffful << SCU_SRAMNPSET_SECn_Pos) /*!< SCU_T::SRAMNPSET: SECn Mask */ + +#define SCU_MEMNPSET_FLASH_Pos (0) /*!< SCU_T::MEMNPSET: FLASH Position */ +#define SCU_MEMNPSET_FLASH_Msk (0x1ul << SCU_MEMNPSET_FLASH_Pos) /*!< SCU_T::MEMNPSET: FLASH Mask */ + +#define SCU_MEMNPSET_EXTMEM_Pos (1) /*!< SCU_T::MEMNPSET: EXTMEM Position */ +#define SCU_MEMNPSET_EXTMEM_Msk (0x1ul << SCU_MEMNPSET_EXTMEM_Pos) /*!< SCU_T::MEMNPSET: EXTMEM Mask */ + +#define SCU_PVIOIEN_APB0IEN_Pos (0) /*!< SCU_T::PVIOIEN: APB0IEN Position */ +#define SCU_PVIOIEN_APB0IEN_Msk (0x1ul << SCU_PVIOIEN_APB0IEN_Pos) /*!< SCU_T::PVIOIEN: APB0IEN Mask */ + +#define SCU_PVIOIEN_APB1IEN_Pos (1) /*!< SCU_T::PVIOIEN: APB1IEN Position */ +#define SCU_PVIOIEN_APB1IEN_Msk (0x1ul << SCU_PVIOIEN_APB1IEN_Pos) /*!< SCU_T::PVIOIEN: APB1IEN Mask */ + +#define SCU_PVIOIEN_GPIOIEN_Pos (4) /*!< SCU_T::PVIOIEN: GPIOIEN Position */ +#define SCU_PVIOIEN_GPIOIEN_Msk (0x1ul << SCU_PVIOIEN_GPIOIEN_Pos) /*!< SCU_T::PVIOIEN: GPIOIEN Mask */ + +#define SCU_PVIOIEN_EBIIEN_Pos (5) /*!< SCU_T::PVIOIEN: EBIIEN Position */ +#define SCU_PVIOIEN_EBIIEN_Msk (0x1ul << SCU_PVIOIEN_EBIIEN_Pos) /*!< SCU_T::PVIOIEN: EBIIEN Mask */ + +#define SCU_PVIOIEN_USBHIEN_Pos (6) /*!< SCU_T::PVIOIEN: USBHIEN Position */ +#define SCU_PVIOIEN_USBHIEN_Msk (0x1ul << SCU_PVIOIEN_USBHIEN_Pos) /*!< SCU_T::PVIOIEN: USBHIEN Mask */ + +#define SCU_PVIOIEN_CRCIEN_Pos (7) /*!< SCU_T::PVIOIEN: CRCIEN Position */ +#define SCU_PVIOIEN_CRCIEN_Msk (0x1ul << SCU_PVIOIEN_CRCIEN_Pos) /*!< SCU_T::PVIOIEN: CRCIEN Mask */ + +#define SCU_PVIOIEN_SDH0IEN_Pos (8) /*!< SCU_T::PVIOIEN: SDH0IEN Position */ +#define SCU_PVIOIEN_SDH0IEN_Msk (0x1ul << SCU_PVIOIEN_SDH0IEN_Pos) /*!< SCU_T::PVIOIEN: SDH0IEN Mask */ + +#define SCU_PVIOIEN_PDMA0IEN_Pos (10) /*!< SCU_T::PVIOIEN: PDMA0IEN Position */ +#define SCU_PVIOIEN_PDMA0IEN_Msk (0x1ul << SCU_PVIOIEN_PDMA0IEN_Pos) /*!< SCU_T::PVIOIEN: PDMA0IEN Mask */ + +#define SCU_PVIOIEN_PDMA1IEN_Pos (11) /*!< SCU_T::PVIOIEN: PDMA1IEN Position */ +#define SCU_PVIOIEN_PDMA1IEN_Msk (0x1ul << SCU_PVIOIEN_PDMA1IEN_Pos) /*!< SCU_T::PVIOIEN: PDMA1IEN Mask */ + +#define SCU_PVIOIEN_SRAM0IEN_Pos (12) /*!< SCU_T::PVIOIEN: SRAM0IEN Position */ +#define SCU_PVIOIEN_SRAM0IEN_Msk (0x1ul << SCU_PVIOIEN_SRAM0IEN_Pos) /*!< SCU_T::PVIOIEN: SRAM0IEN Mask */ + +#define SCU_PVIOIEN_SRAM1IEN_Pos (13) /*!< SCU_T::PVIOIEN: SRAM1IEN Position */ +#define SCU_PVIOIEN_SRAM1IEN_Msk (0x1ul << SCU_PVIOIEN_SRAM1IEN_Pos) /*!< SCU_T::PVIOIEN: SRAM1IEN Mask */ + +#define SCU_PVIOIEN_FMCIEN_Pos (14) /*!< SCU_T::PVIOIEN: FMCIEN Position */ +#define SCU_PVIOIEN_FMCIEN_Msk (0x1ul << SCU_PVIOIEN_FMCIEN_Pos) /*!< SCU_T::PVIOIEN: FMCIEN Mask */ + +#define SCU_PVIOIEN_FLASHIEN_Pos (15) /*!< SCU_T::PVIOIEN: FLASHIEN Position */ +#define SCU_PVIOIEN_FLASHIEN_Msk (0x1ul << SCU_PVIOIEN_FLASHIEN_Pos) /*!< SCU_T::PVIOIEN: FLASHIEN Mask */ + +#define SCU_PVIOIEN_SCUIEN_Pos (16) /*!< SCU_T::PVIOIEN: SCUIEN Position */ +#define SCU_PVIOIEN_SCUIEN_Msk (0x1ul << SCU_PVIOIEN_SCUIEN_Pos) /*!< SCU_T::PVIOIEN: SCUIEN Mask */ + +#define SCU_PVIOIEN_SYSIEN_Pos (17) /*!< SCU_T::PVIOIEN: SYSIEN Position */ +#define SCU_PVIOIEN_SYSIEN_Msk (0x1ul << SCU_PVIOIEN_SYSIEN_Pos) /*!< SCU_T::PVIOIEN: SYSIEN Mask */ + +#define SCU_PVIOIEN_CRPTIEN_Pos (18) /*!< SCU_T::PVIOIEN: CRPTIEN Position */ +#define SCU_PVIOIEN_CRPTIEN_Msk (0x1ul << SCU_PVIOIEN_CRPTIEN_Pos) /*!< SCU_T::PVIOIEN: CRPTIEN Mask */ + +#define SCU_PVIOIEN_KSIEN_Pos (19) /*!< SCU_T::PVIOIEN: KSIEN Position */ +#define SCU_PVIOIEN_KSIEN_Msk (0x1ul << SCU_PVIOIEN_KSIEN_Pos) /*!< SCU_T::PVIOIEN: KSIEN Mask */ + +#define SCU_PVINTSTS_APB0IF_Pos (0) /*!< SCU_T::PVINTSTS: APB0IF Position */ +#define SCU_PVINTSTS_APB0IF_Msk (0x1ul << SCU_PVINTSTS_APB0IF_Pos) /*!< SCU_T::PVINTSTS: APB0IF Mask */ + +#define SCU_PVINTSTS_APB1IF_Pos (1) /*!< SCU_T::PVINTSTS: APB1IF Position */ +#define SCU_PVINTSTS_APB1IF_Msk (0x1ul << SCU_PVINTSTS_APB1IF_Pos) /*!< SCU_T::PVINTSTS: APB1IF Mask */ + +#define SCU_PVINTSTS_GPIOIF_Pos (4) /*!< SCU_T::PVINTSTS: GPIOIF Position */ +#define SCU_PVINTSTS_GPIOIF_Msk (0x1ul << SCU_PVINTSTS_GPIOIF_Pos) /*!< SCU_T::PVINTSTS: GPIOIF Mask */ + +#define SCU_PVINTSTS_EBIIF_Pos (5) /*!< SCU_T::PVINTSTS: EBIIF Position */ +#define SCU_PVINTSTS_EBIIF_Msk (0x1ul << SCU_PVINTSTS_EBIIF_Pos) /*!< SCU_T::PVINTSTS: EBIIF Mask */ + +#define SCU_PVINTSTS_USBHIF_Pos (6) /*!< SCU_T::PVINTSTS: USBHIF Position */ +#define SCU_PVINTSTS_USBHIF_Msk (0x1ul << SCU_PVINTSTS_USBHIF_Pos) /*!< SCU_T::PVINTSTS: USBHIF Mask */ + +#define SCU_PVINTSTS_CRCIF_Pos (7) /*!< SCU_T::PVINTSTS: CRCIF Position */ +#define SCU_PVINTSTS_CRCIF_Msk (0x1ul << SCU_PVINTSTS_CRCIF_Pos) /*!< SCU_T::PVINTSTS: CRCIF Mask */ + +#define SCU_PVINTSTS_SDH0IF_Pos (8) /*!< SCU_T::PVINTSTS: SDH0IF Position */ +#define SCU_PVINTSTS_SDH0IF_Msk (0x1ul << SCU_PVINTSTS_SDH0IF_Pos) /*!< SCU_T::PVINTSTS: SDH0IF Mask */ + +#define SCU_PVINTSTS_PDMA0IF_Pos (10) /*!< SCU_T::PVINTSTS: PDMA0IF Position */ +#define SCU_PVINTSTS_PDMA0IF_Msk (0x1ul << SCU_PVINTSTS_PDMA0IF_Pos) /*!< SCU_T::PVINTSTS: PDMA0IF Mask */ + +#define SCU_PVINTSTS_PDMA1IF_Pos (11) /*!< SCU_T::PVINTSTS: PDMA1IF Position */ +#define SCU_PVINTSTS_PDMA1IF_Msk (0x1ul << SCU_PVINTSTS_PDMA1IF_Pos) /*!< SCU_T::PVINTSTS: PDMA1IF Mask */ + +#define SCU_PVINTSTS_SRAM0IF_Pos (12) /*!< SCU_T::PVINTSTS: SRAM0IF Position */ +#define SCU_PVINTSTS_SRAM0IF_Msk (0x1ul << SCU_PVINTSTS_SRAM0IF_Pos) /*!< SCU_T::PVINTSTS: SRAM0IF Mask */ + +#define SCU_PVINTSTS_SRAM1IF_Pos (13) /*!< SCU_T::PVINTSTS: SRAM1IF Position */ +#define SCU_PVINTSTS_SRAM1IF_Msk (0x1ul << SCU_PVINTSTS_SRAM1IF_Pos) /*!< SCU_T::PVINTSTS: SRAM1IF Mask */ + +#define SCU_PVINTSTS_FMCIF_Pos (14) /*!< SCU_T::PVINTSTS: FMCIF Position */ +#define SCU_PVINTSTS_FMCIF_Msk (0x1ul << SCU_PVINTSTS_FMCIF_Pos) /*!< SCU_T::PVINTSTS: FMCIF Mask */ + +#define SCU_PVINTSTS_FLASHIF_Pos (15) /*!< SCU_T::PVINTSTS: FLASHIF Position */ +#define SCU_PVINTSTS_FLASHIF_Msk (0x1ul << SCU_PVINTSTS_FLASHIF_Pos) /*!< SCU_T::PVINTSTS: FLASHIF Mask */ + +#define SCU_PVINTSTS_SCUIF_Pos (16) /*!< SCU_T::PVINTSTS: SCUIF Position */ +#define SCU_PVINTSTS_SCUIF_Msk (0x1ul << SCU_PVINTSTS_SCUIF_Pos) /*!< SCU_T::PVINTSTS: SCUIF Mask */ + +#define SCU_PVINTSTS_SYSIF_Pos (17) /*!< SCU_T::PVINTSTS: SYSIF Position */ +#define SCU_PVINTSTS_SYSIF_Msk (0x1ul << SCU_PVINTSTS_SYSIF_Pos) /*!< SCU_T::PVINTSTS: SYSIF Mask */ + +#define SCU_PVINTSTS_CRPTIF_Pos (18) /*!< SCU_T::PVINTSTS: CRPTIF Position */ +#define SCU_PVINTSTS_CRPTIF_Msk (0x1ul << SCU_PVINTSTS_CRPTIF_Pos) /*!< SCU_T::PVINTSTS: CRPTIF Mask */ + +#define SCU_PVINTSTS_KSIF_Pos (19) /*!< SCU_T::PVINTSTS: KSIF Position */ +#define SCU_PVINTSTS_KSIF_Msk (0x1ul << SCU_PVINTSTS_KSIF_Pos) /*!< SCU_T::PVINTSTS: KSIF Mask */ + +#define SCU_NSMCTL_PRESCALE_Pos (0) /*!< SCU_T::NSMCTL: PRESCALE Position */ +#define SCU_NSMCTL_PRESCALE_Msk (0xfful << SCU_NSMCTL_PRESCALE_Pos) /*!< SCU_T::NSMCTL: PRESCALE Mask */ + +#define SCU_NSMCTL_NSMIEN_Pos (8) /*!< SCU_T::NSMCTL: NSMIEN Position */ +#define SCU_NSMCTL_NSMIEN_Msk (0x1ul << SCU_NSMCTL_NSMIEN_Pos) /*!< SCU_T::NSMCTL: NSMIEN Mask */ + +#define SCU_NSMCTL_AUTORLD_Pos (9) /*!< SCU_T::NSMCTL: AUTORLD Position */ +#define SCU_NSMCTL_AUTORLD_Msk (0x1ul << SCU_NSMCTL_AUTORLD_Pos) /*!< SCU_T::NSMCTL: AUTORLD Mask */ + +#define SCU_NSMCTL_TMRMOD_Pos (10) /*!< SCU_T::NSMCTL: TMRMOD Position */ +#define SCU_NSMCTL_TMRMOD_Msk (0x1ul << SCU_NSMCTL_TMRMOD_Pos) /*!< SCU_T::NSMCTL: TMRMOD Mask */ + +#define SCU_NSMCTL_IDLEON_Pos (12) /*!< SCU_T::NSMCTL: IDLEON Position */ +#define SCU_NSMCTL_IDLEON_Msk (0x1ul << SCU_NSMCTL_IDLEON_Pos) /*!< SCU_T::NSMCTL: IDLEON Mask */ + +#define SCU_NSMCTL_DBGON_Pos (13) /*!< SCU_T::NSMCTL: DBGON Position */ +#define SCU_NSMCTL_DBGON_Msk (0x1ul << SCU_NSMCTL_DBGON_Pos) /*!< SCU_T::NSMCTL: DBGON Mask */ + +#define SCU_NSMLOAD_RELOAD_Pos (0) /*!< SCU_T::NSMLOAD: RELOAD Position */ +#define SCU_NSMLOAD_RELOAD_Msk (0xfffffful << SCU_NSMLOAD_RELOAD_Pos) /*!< SCU_T::NSMLOAD: RELOAD Mask */ + +#define SCU_NSMVAL_VALUE_Pos (0) /*!< SCU_T::NSMVAL: VALUE Position */ +#define SCU_NSMVAL_VALUE_Msk (0xfffffful << SCU_NSMVAL_VALUE_Pos) /*!< SCU_T::NSMVAL: VALUE Mask */ + +#define SCU_NSMSTS_CURRNS_Pos (0) /*!< SCU_T::NSMSTS: CURRNS Position */ +#define SCU_NSMSTS_CURRNS_Msk (0x1ul << SCU_NSMSTS_CURRNS_Pos) /*!< SCU_T::NSMSTS: CURRNS Mask */ + +#define SCU_NSMSTS_NSMIF_Pos (1) /*!< SCU_T::NSMSTS: NSMIF Position */ +#define SCU_NSMSTS_NSMIF_Msk (0x1ul << SCU_NSMSTS_NSMIF_Pos) /*!< SCU_T::NSMSTS: NSMIF Mask */ + +#define SCU_BBE_BBEEN_Pos (0) /*!< SCU_T::BBE: BBEEN Position */ +#define SCU_BBE_BBEEN_Msk (0x1ul << SCU_BBE_BBEEN_Pos) /*!< SCU_T::BBE: BBEEN Mask */ + +#define SCU_BBE_WVERY_Pos (8) /*!< SCU_T::BBE: WVERY Position */ +#define SCU_BBE_WVERY_Msk (0xfffffful << SCU_BBE_WVERY_Pos) /*!< SCU_T::BBE: WVERY Mask */ + +#define SCU_IDAUANS_IDAUANSEN_Pos (0) /*!< SCU_T::IDAUANS: IDAUANSEN Position */ +#define SCU_IDAUANS_IDAUANSEN_Msk (0x1ul << SCU_IDAUANS_IDAUANSEN_Pos) /*!< SCU_T::IDAUANS: IDAUANSEN Mask */ + +#define SCU_IDAUANS_WVERY_Pos (8) /*!< SCU_T::IDAUANS: WVERY Position */ +#define SCU_IDAUANS_WVERY_Msk (0xfffffful << SCU_IDAUANS_WVERY_Pos) /*!< SCU_T::IDAUANS: WVERY Mask */ + +#define SCU_VERSION_MINOR_Pos (0) /*!< SCU_T::VERSION: MINOR Position */ +#define SCU_VERSION_MINOR_Msk (0xfffful << SCU_VERSION_MINOR_Pos) /*!< SCU_T::VERSION: MINOR Mask */ + +#define SCU_VERSION_SUB_Pos (16) /*!< SCU_T::VERSION: SUB Position */ +#define SCU_VERSION_SUB_Msk (0xfful << SCU_VERSION_SUB_Pos) /*!< SCU_T::VERSION: SUB Mask */ + +#define SCU_VERSION_MAJOR_Pos (24) /*!< SCU_T::VERSION: MAJOR Position */ +#define SCU_VERSION_MAJOR_Msk (0xfful << SCU_VERSION_MAJOR_Pos) /*!< SCU_T::VERSION: MAJOR Mask */ + +/**@}*/ /* SCU_CONST */ +/**@}*/ /* end of SCU register group */ + + +/**@}*/ /* end of REGISTER group */ +#endif /* __SCU_REG_H__ */ diff --git a/Ubiquitous/XiZi/board/nuvoton-m2354/third_party_driver/include/Regs/sdh_reg.h b/Ubiquitous/XiZi/board/nuvoton-m2354/third_party_driver/include/Regs/sdh_reg.h new file mode 100644 index 0000000..2ce64f3 --- /dev/null +++ b/Ubiquitous/XiZi/board/nuvoton-m2354/third_party_driver/include/Regs/sdh_reg.h @@ -0,0 +1,528 @@ +/**************************************************************************//** + * @file sdh_reg.h + * @version V1.00 + * @brief SDH register definition header file + * + * @copyright SPDX-License-Identifier: Apache-2.0 + * @copyright Copyright (C) 2020 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ +#ifndef __SDH_REG_H__ +#define __SDH_REG_H__ + +/** @addtogroup REGISTER Control Register + + @{ + +*/ + +/*---------------------- SD Card Host Interface -------------------------*/ +/** + @addtogroup SDH SD Card Host Interface(SDH) + Memory Mapped Structure for SDH Controller + @{ +*/ + +typedef struct +{ + + /** + * @var SDH_T::FB + * Offset: 0x00~0x7C Shared Buffer (FIFO) + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |BUFFER |Shared Buffer + * | | |Buffer for DMA transfer + * @var SDH_T::DMACTL + * Offset: 0x400 DMA Control and Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |DMAEN |DMA Engine Enable Bit + * | | |If this bit is cleared, DMA will ignore all requests from SD host and force bus master into IDLE state. + * | | |0 = DMA Disabled. + * | | |1 = DMA Enabled. + * | | |Note: If target abort is occurred, DMAEN will be cleared. + * |[1] |DMARST |Software Engine Reset + * | | |0 = No effect. + * | | |1 = Reset internal state machine and pointers + * | | |The contents of control register will not be cleared + * | | |This bit will auto be cleared after few clock cycles. + * | | |Note: The software reset DMA related registers. + * |[3] |SGEN |Scatter-gather Function Enable Bit + * | | |0 = Scatter-gather function Disabled (DMA will treat the starting address in DMASAR as starting pointer of a single block memory). + * | | |1 = Scatter-gather function Enabled (DMA will treat the starting address in DMASAR as a starting address of Physical Address Descriptor (PAD) table + * | | |The format of these Pads' will be described later). + * |[9] |DMABUSY |DMA Transfer Is in Progress + * | | |This bit indicates if SD Host is granted and doing DMA transfer or not. + * | | |0 = DMA transfer is not in progress. + * | | |1 = DMA transfer is in progress. + * @var SDH_T::DMASA + * Offset: 0x408 DMA Transfer Starting Address Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |ORDER |Determined to the PAD Table Fetching Is in Order or Out of Order + * | | |0 = PAD table is fetched in order. + * | | |1 = PAD table is fetched out of order. + * | | |Note: the bit0 is valid in scatter-gather mode when SGEN = 1. + * |[31:1] |DMASA |DMA Transfer Starting Address + * | | |This field pads 0 as least significant bit indicates a 32-bit starting address of system memory (SRAM) for DMA to retrieve or fill in data. + * | | |If DMA is not in normal mode, this field will be interpreted as a starting address of Physical Address Descriptor (PAD) table. + * | | |Note: Starting address of the SRAM must be word aligned, for example, 0x0000_0000, 0x0000_0004. + * @var SDH_T::DMABCNT + * Offset: 0x40C DMA Transfer Byte Count Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[25:0] |BCNT |DMA Transfer Byte Count (Read Only) + * | | |This field indicates the remained byte count of DMA transfer + * | | |The value of this field is valid only when DMA is busy; otherwise, it is 0. + * @var SDH_T::DMAINTEN + * Offset: 0x410 DMA Interrupt Enable Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |ABORTIEN |DMA Read/Write Target Abort Interrupt Enable Bit + * | | |0 = Target abort interrupt generation Disabled during DMA transfer. + * | | |1 = Target abort interrupt generation Enabled during DMA transfer. + * |[1] |WEOTIEN |Wrong EOT Encountered Interrupt Enable Bit + * | | |0 = Interrupt generation Disabled when wrong EOT is encountered. + * | | |1 = Interrupt generation Enabled when wrong EOT is encountered. + * @var SDH_T::DMAINTSTS + * Offset: 0x414 DMA Interrupt Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |ABORTIF |DMA Read/Write Target Abort Interrupt Flag + * | | |0 = No bus ERROR response received. + * | | |1 = Bus ERROR response received. + * | | |Note1: This bit is read only, but can be cleared by writing '1' to it. + * | | |Note2: When DMA's bus master received ERROR response, it means that target abort is happened + * | | |DMA will stop transfer and respond this event and then go to IDLE state + * | | |When target abort occurred or WEOTIF is set, software must reset DMA and SD host, and then transfer those data again. + * |[1] |WEOTIF |Wrong EOT Encountered Interrupt Flag + * | | |When DMA Scatter-Gather function is enabled, and EOT of the descriptor is encountered before DMA transfer finished (that means the total sector count of all PAD is less than the sector count of SD host), this bit will be set. + * | | |0 = No EOT encountered before DMA transfer finished. + * | | |1 = EOT encountered before DMA transfer finished. + * | | |Note: This bit is read only, but can be cleared by writing '1' to it. + * @var SDH_T::GCTL + * Offset: 0x800 Global Control and Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |GCTLRST |Software Engine Reset + * | | |0 = No effect. + * | | |1 = Reset SD host + * | | |The contents of control register will not be cleared + * | | |This bit will auto cleared after reset complete. + * |[1] |SDEN |Secure Digital Functionality Enable Bit + * | | |0 = SD functionality disabled. + * | | |1 = SD functionality enabled. + * @var SDH_T::GINTEN + * Offset: 0x804 Global Interrupt Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |DTAIEN |DMA READ/WRITE Target Abort Interrupt Enable Bit + * | | |0 = DMA READ/WRITE target abort interrupt generation disabled. + * | | |1 = DMA READ/WRITE target abort interrupt generation enabled. + * @var SDH_T::GINTSTS + * Offset: 0x808 Global Interrupt Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |DTAIF |DMA READ/WRITE Target Abort Interrupt Flag (Read Only) + * | | |This bit indicates DMA received an ERROR response from internal AHB bus during DMA read/write operation + * | | |When Target Abort is occurred, please reset all engine. + * | | |0 = No bus ERROR response received. + * | | |1 = Bus ERROR response received. + * | | |Note: This bit is read only, but can be cleared by writing '1' to it. + * @var SDH_T::CTL + * Offset: 0x820 SD Control and Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |COEN |Command Output Enable Bit + * | | |0 = No effect. (Please use DMARST (SDH_CTL [0]) to clear this bit.) + * | | |1 = Enabled, SD host will output a command to SD card. + * | | |Note: When operation is finished, this bit will be cleared automatically, so don't write 0 to this bit (the controller will be abnormal). + * |[1] |RIEN |Response Input Enable Bit + * | | |0 = No effect. (Please use DMARST (SDH_CTL [0]) to clear this bit.) + * | | |1 = Enabled, SD host will wait to receive a response from SD card. + * | | |Note: When operation is finished, this bit will be cleared automatically, so don't write 0 to this bit (the controller will be abnormal). + * |[2] |DIEN |Data Input Enable Bit + * | | |0 = No effect. (Please use DMARST (SDH_CTL [0]) to clear this bit.) + * | | |1 = Enabled, SD host will wait to receive block data and the CRC16 value from SD card. + * | | |Note: When operation is finished, this bit will be cleared automatically, so don't write 0 to this bit (the controller will be abnormal). + * |[3] |DOEN |Data Output Enable Bit + * | | |0 = No effect. (Please use DMARST (SDH_CTL [0]) to clear this bit.) + * | | |1 = Enabled, SD host will transfer block data and the CRC16 value to SD card. + * | | |Note: When operation is finished, this bit will be cleared automatically, so don't write 0 to this bit (the controller will be abnormal). + * |[4] |R2EN |Response R2 Input Enable Bit + * | | |0 = No effect. (Please use DMARST (SDH_CTL [0]) to clear this bit.) + * | | |1 = Enabled, SD host will wait to receive a response R2 from SD card and store the response data into DMC's flash buffer (exclude CRC7). + * | | |Note: When operation is finished, this bit will be cleared automatically, so don't write 0 to this bit (the controller will be abnormal). + * |[5] |CLK74OEN |Initial 74 Clock Cycles Output Enable Bit + * | | |0 = No effect. (Please use DMARST (SDH_CTL [0]) to clear this bit.) + * | | |1 = Enabled, SD host will output 74 clock cycles to SD card. + * | | |Note: When operation is finished, this bit will be cleared automatically, so don't write 0 to this bit (the controller will be abnormal). + * |[6] |CLK8OEN |Generating 8 Clock Cycles Output Enable Bit + * | | |0 = No effect. (Please use DMARST (SDH_CTL [0]) to clear this bit.) + * | | |1 = Enabled, SD host will output 8 clock cycles. + * | | |Note: When operation is finished, this bit will be cleared automatically, so don't write 0 to this bit (the controller will be abnormal). + * |[7] |CLKKEEP0 |SD Clock Enable Control for Port 0 + * | | |0 = SD host decided when to output clock and when to disable clock output automatically. + * | | |1 = SD clock always keeps free running. + * |[13:8] |CMDCODE |SD Command Code + * | | |This register contains the SD command code (0x00 ~ 0x3F). + * |[14] |CTLRST |Software Engine Reset + * | | |0 = No effect. + * | | |1 = Reset the internal state machine and counters + * | | |The contents of control register will not be cleared (but RIEN, DIEN, DOEN and R2EN will be cleared) + * | | |This bit will be auto cleared after few clock cycles. + * |[15] |DBW |SD Data Bus Width (for 1-bit / 4-bit Selection) + * | | |0 = Data bus width is 1-bit. + * | | |1 = Data bus width is 4-bit. + * |[23:16] |BLKCNT |Block Counts to Be Transferred or Received + * | | |This field contains the block counts for data-in and data-out transfer + * | | |For READ_MULTIPLE_BLOCK and WRITE_MULTIPLE_BLOCK command, software can use this function to accelerate data transfer and improve performance + * | | |Don't fill 0x0 to this field. + * | | |Note: For READ_MULTIPLE_BLOCK and WRITE_MULTIPLE_BLOCK command, the actual total length is BLKCNT * (BLKLEN +1). + * |[27:24] |SDNWR |NWR Parameter for Block Write Operation + * | | |This value indicates the NWR parameter for data block write operation in SD clock counts + * | | |The actual clock cycle will be SDNWR+1. + * @var SDH_T::CMDARG + * Offset: 0x824 SD Command Argument Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |ARGUMENT |SD Command Argument + * | | |This register contains a 32-bit value specifies the argument of SD command from host controller to SD card + * | | |Before trigger COEN (SDH_CTL [0]), software should fill argument in this field. + * @var SDH_T::INTEN + * Offset: 0x828 SD Interrupt Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |BLKDIEN |Block Transfer Done Interrupt Enable Bit + * | | |0 = SD host will not generate interrupt when data-in (out) transfer done. + * | | |1 = SD host will generate interrupt when data-in (out) transfer done. + * |[1] |CRCIEN |CRC7, CRC16 and CRC Status Error Interrupt Enable Bit + * | | |0 = SD host will not generate interrupt when CRC7, CRC16 and CRC status is error. + * | | |1 = SD host will generate interrupt when CRC7, CRC16 and CRC status is error. + * |[8] |CDIEN0 |SD0 Card Detection Interrupt Enable Bit + * | | |Enable/Disable interrupts generation of SD controller when card 0 is inserted or removed. + * | | |0 = SD card detection interrupt Disabled. + * | | |1 = SD card detection interrupt Enabled. + * |[12] |RTOIEN |Response Time-out Interrupt Enable Bit + * | | |Enable/Disable interrupts generation of SD controller when receiving response or R2 time-out + * | | |Time-out value is specified at TOUT register. + * | | |0 = Response time-out interrupt Disabled. + * | | |1 = Response time-out interrupt Enabled. + * |[13] |DITOIEN |Data Input Time-out Interrupt Enable Bit + * | | |Enable/Disable interrupts generation of SD controller when data input time-out + * | | |Time-out value is specified at TOUT register. + * | | |0 = Data input time-out interrupt Disabled. + * | | |1 = Data input time-out interrupt Enabled. + * |[14] |WKIEN |Wake-up Signal Generating Enable Bit + * | | |Enable/Disable wake-up signal generating of SD host when current using SD card issues an interrupt (wake-up) via DAT [1] to host. + * | | |0 = Wake-up signal generating Disabled. + * | | |1 = Wake-up signal generating Enabled. + * |[30] |CDSRC0 |SD0 Card Detect Source Selection + * | | |0 = From SD0 card's DAT3 pin. + * | | |Host need clock to got data on pin DAT3 + * | | |Please make sure CLKKEEP0 (SDH_CTL[7]) is 1 in order to generate free running clock for DAT3 pin. + * | | |1 = From GPIO pin. + * @var SDH_T::INTSTS + * Offset: 0x82C SD Interrupt Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |BLKDIF |Block Transfer Done Interrupt Flag (Read Only) + * | | |This bit indicates that SD host has finished all data-in or data-out block transfer + * | | |If there is a CRC16 error or incorrect CRC status during multiple block data transfer, the transfer will be broken and this bit will also be set. + * | | |0 = Not finished yet. + * | | |1 = Done. + * | | |Note: This bit is read only, but can be cleared by writing '1' to it. + * |[1] |CRCIF |CRC7, CRC16 and CRC Status Error Interrupt Flag (Read Only) + * | | |This bit indicates that SD host has occurred CRC error during response in, data-in or data-out (CRC status error) transfer + * | | |When CRC error is occurred, software should reset SD engine + * | | |Some response (ex + * | | |R3) doesn't have CRC7 information with it; SD host will still calculate CRC7, get CRC error and set this flag + * | | |In this condition, software should ignore CRC error and clears this bit manually. + * | | |0 = No CRC error is occurred. + * | | |1 = CRC error is occurred. + * | | |Note: This bit is read only, but can be cleared by writing '1' to it. + * |[2] |CRC7 |CRC7 Check Status (Read Only) + * | | |SD host will check CRC7 correctness during each response in + * | | |If that response does not contain CRC7 information (ex + * | | |R3), then software should turn off CRCIEN (SDH_INTEN[1]) and ignore this bit. + * | | |0 = Fault. + * | | |1 = OK. + * |[3] |CRC16 |CRC16 Check Status of Data-in Transfer (Read Only) + * | | |SD host will check CRC16 correctness after data-in transfer. + * | | |0 = Fault. + * | | |1 = OK. + * |[6:4] |CRCSTS |CRC Status Value of Data-out Transfer (Read Only) + * | | |SD host will record CRC status of data-out transfer + * | | |Software could use this value to identify what type of error is during data-out transfer. + * | | |010 = Positive CRC status. + * | | |101 = Negative CRC status. + * | | |111 = SD card programming error occurs. + * |[7] |DAT0STS |DAT0 Pin Status of Current Selected SD Port (Read Only) + * | | |This bit is the DAT0 pin status of current selected SD port. + * |[8] |CDIF0 |SD0 Card Detection Interrupt Flag (Read Only) + * | | |This bit indicates that SD card 0 is inserted or removed + * | | |Only when CDIEN0 (SDH_INTEN[8]) is set to 1, this bit is active. + * | | |0 = No card is inserted or removed. + * | | |1 = There is a card inserted in or removed from SD0. + * | | |Note: This bit is read only, but can be cleared by writing '1' to it. + * |[12] |RTOIF |Response Time-out Interrupt Flag (Read Only) + * | | |This bit indicates that SD host counts to time-out value when receiving response or R2 (waiting start bit). + * | | |0 = Not time-out. + * | | |1 = Response time-out. + * | | |Note: This bit is read only, but can be cleared by writing '1' to it. + * |[13] |DITOIF |Data Input Time-out Interrupt Flag (Read Only) + * | | |This bit indicates that SD host counts to time-out value when receiving data (waiting start bit). + * | | |0 = Not time-out. + * | | |1 = Data input time-out. + * | | |Note: This bit is read only, but can be cleared by writing '1' to it. + * |[16] |CDSTS0 |Card Detect Status of SD0 (Read Only) + * | | |This bit indicates the card detect pin status of SD0, and is used for card detection + * | | |When there is a card inserted in or removed from SD0, software should check this bit to confirm if there is really a card insertion or removal. + * | | |If CDSRC0 (SDH_INTEN[30]) = 0, to select DAT3 for card detection:. + * | | |0 = Card removed. + * | | |1 = Card inserted. + * | | |If CDSRC0 (SDH_INTEN[30]) = 1, to select GPIO for card detection:. + * | | |0 = Card inserted. + * | | |1 = Card removed. + * |[18] |DAT1STS |DAT1 Pin Status of SD Port (Read Only) + * | | |This bit indicates the DAT1 pin status of SD port. + * @var SDH_T::RESP0 + * Offset: 0x830 SD Receiving Response Token Register 0 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |RESPTK0 |SD Receiving Response Token 0 + * | | |SD host controller will receive a response token for getting a reply from SD card when RIEN (SDH_CTL[1]) is set + * | | |This field contains response bit 47-16 of the response token. + * @var SDH_T::RESP1 + * Offset: 0x834 SD Receiving Response Token Register 1 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[7:0] |RESPTK1 |SD Receiving Response Token 1 + * | | |SD host controller will receive a response token for getting a reply from SD card when RIEN (SDH_CTL[1]) is set + * | | |This register contains the bit 15-8 of the response token. + * @var SDH_T::BLEN + * Offset: 0x838 SD Block Length Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[10:0] |BLKLEN |SD BLOCK LENGTH in Byte Unit + * | | |An 11-bit value specifies the SD transfer byte count of a block + * | | |The actual byte count is equal to BLKLEN+1. + * | | |Note: The default SD block length is 512 bytes + * @var SDH_T::TOUT + * Offset: 0x83C SD Response/Data-in Time-out Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[23:0] |TOUT |SD Response/Data-in Time-out Value + * | | |A 24-bit value specifies the time-out counts of response and data input + * | | |SD host controller will wait start bit of response or data-in until this value reached + * | | |The time period depends on SD engine clock frequency + * | | |Do not write a small number into this field, or you may never get response or data due to time-out. + * | | |Note: Filling 0x0 into this field will disable hardware time-out function. + */ + + __IO uint32_t FB[32]; /*!< Shared Buffer (FIFO) */ + __I uint32_t RESERVE0[224]; + __IO uint32_t DMACTL; /*!< [0x0400] DMA Control and Status Register */ + __I uint32_t RESERVE1[1]; + __IO uint32_t DMASA; /*!< [0x0408] DMA Transfer Starting Address Register */ + __I uint32_t DMABCNT; /*!< [0x040c] DMA Transfer Byte Count Register */ + __IO uint32_t DMAINTEN; /*!< [0x0410] DMA Interrupt Enable Control Register */ + __IO uint32_t DMAINTSTS; /*!< [0x0414] DMA Interrupt Status Register */ + __I uint32_t RESERVE2[250]; + __IO uint32_t GCTL; /*!< [0x0800] Global Control and Status Register */ + __IO uint32_t GINTEN; /*!< [0x0804] Global Interrupt Control Register */ + __IO uint32_t GINTSTS; /*!< [0x0808] Global Interrupt Status Register */ + __I uint32_t RESERVE3[5]; + __IO uint32_t CTL; /*!< [0x0820] SD Control and Status Register */ + __IO uint32_t CMDARG; /*!< [0x0824] SD Command Argument Register */ + __IO uint32_t INTEN; /*!< [0x0828] SD Interrupt Control Register */ + __IO uint32_t INTSTS; /*!< [0x082c] SD Interrupt Status Register */ + __I uint32_t RESP0; /*!< [0x0830] SD Receiving Response Token Register 0 */ + __I uint32_t RESP1; /*!< [0x0834] SD Receiving Response Token Register 1 */ + __IO uint32_t BLEN; /*!< [0x0838] SD Block Length Register */ + __IO uint32_t TOUT; /*!< [0x083c] SD Response/Data-in Time-out Register */ + +} SDH_T; + +/** + @addtogroup SDH_CONST SDH Bit Field Definition + Constant Definitions for SDH Controller + @{ +*/ + +#define SDH_DMACTL_DMAEN_Pos (0) /*!< SDH_T::DMACTL: DMAEN Position */ +#define SDH_DMACTL_DMAEN_Msk (0x1ul << SDH_DMACTL_DMAEN_Pos) /*!< SDH_T::DMACTL: DMAEN Mask */ + +#define SDH_DMACTL_DMARST_Pos (1) /*!< SDH_T::DMACTL: DMARST Position */ +#define SDH_DMACTL_DMARST_Msk (0x1ul << SDH_DMACTL_DMARST_Pos) /*!< SDH_T::DMACTL: DMARST Mask */ + +#define SDH_DMACTL_SGEN_Pos (3) /*!< SDH_T::DMACTL: SGEN Position */ +#define SDH_DMACTL_SGEN_Msk (0x1ul << SDH_DMACTL_SGEN_Pos) /*!< SDH_T::DMACTL: SGEN Mask */ + +#define SDH_DMACTL_DMABUSY_Pos (9) /*!< SDH_T::DMACTL: DMABUSY Position */ +#define SDH_DMACTL_DMABUSY_Msk (0x1ul << SDH_DMACTL_DMABUSY_Pos) /*!< SDH_T::DMACTL: DMABUSY Mask */ + +#define SDH_DMASA_ORDER_Pos (0) /*!< SDH_T::DMASA: ORDER Position */ +#define SDH_DMASA_ORDER_Msk (0x1ul << SDH_DMASA_ORDER_Pos) /*!< SDH_T::DMASA: ORDER Mask */ + +#define SDH_DMASA_DMASA_Pos (1) /*!< SDH_T::DMASA: DMASA Position */ +#define SDH_DMASA_DMASA_Msk (0x7ffffffful << SDH_DMASA_DMASA_Pos) /*!< SDH_T::DMASA: DMASA Mask */ + +#define SDH_DMABCNT_BCNT_Pos (0) /*!< SDH_T::DMABCNT: BCNT Position */ +#define SDH_DMABCNT_BCNT_Msk (0x3fffffful << SDH_DMABCNT_BCNT_Pos) /*!< SDH_T::DMABCNT: BCNT Mask */ + +#define SDH_DMAINTEN_ABORTIEN_Pos (0) /*!< SDH_T::DMAINTEN: ABORTIEN Position */ +#define SDH_DMAINTEN_ABORTIEN_Msk (0x1ul << SDH_DMAINTEN_ABORTIEN_Pos) /*!< SDH_T::DMAINTEN: ABORTIEN Mask */ + +#define SDH_DMAINTEN_WEOTIEN_Pos (1) /*!< SDH_T::DMAINTEN: WEOTIEN Position */ +#define SDH_DMAINTEN_WEOTIEN_Msk (0x1ul << SDH_DMAINTEN_WEOTIEN_Pos) /*!< SDH_T::DMAINTEN: WEOTIEN Mask */ + +#define SDH_DMAINTSTS_ABORTIF_Pos (0) /*!< SDH_T::DMAINTSTS: ABORTIF Position */ +#define SDH_DMAINTSTS_ABORTIF_Msk (0x1ul << SDH_DMAINTSTS_ABORTIF_Pos) /*!< SDH_T::DMAINTSTS: ABORTIF Mask */ + +#define SDH_DMAINTSTS_WEOTIF_Pos (1) /*!< SDH_T::DMAINTSTS: WEOTIF Position */ +#define SDH_DMAINTSTS_WEOTIF_Msk (0x1ul << SDH_DMAINTSTS_WEOTIF_Pos) /*!< SDH_T::DMAINTSTS: WEOTIF Mask */ + +#define SDH_GCTL_GCTLRST_Pos (0) /*!< SDH_T::GCTL: GCTLRST Position */ +#define SDH_GCTL_GCTLRST_Msk (0x1ul << SDH_GCTL_GCTLRST_Pos) /*!< SDH_T::GCTL: GCTLRST Mask */ + +#define SDH_GCTL_SDEN_Pos (1) /*!< SDH_T::GCTL: SDEN Position */ +#define SDH_GCTL_SDEN_Msk (0x1ul << SDH_GCTL_SDEN_Pos) /*!< SDH_T::GCTL: SDEN Mask */ + +#define SDH_GINTEN_DTAIEN_Pos (0) /*!< SDH_T::GINTEN: DTAIEN Position */ +#define SDH_GINTEN_DTAIEN_Msk (0x1ul << SDH_GINTEN_DTAIEN_Pos) /*!< SDH_T::GINTEN: DTAIEN Mask */ + +#define SDH_GINTSTS_DTAIF_Pos (0) /*!< SDH_T::GINTSTS: DTAIF Position */ +#define SDH_GINTSTS_DTAIF_Msk (0x1ul << SDH_GINTSTS_DTAIF_Pos) /*!< SDH_T::GINTSTS: DTAIF Mask */ + +#define SDH_CTL_COEN_Pos (0) /*!< SDH_T::CTL: COEN Position */ +#define SDH_CTL_COEN_Msk (0x1ul << SDH_CTL_COEN_Pos) /*!< SDH_T::CTL: COEN Mask */ + +#define SDH_CTL_RIEN_Pos (1) /*!< SDH_T::CTL: RIEN Position */ +#define SDH_CTL_RIEN_Msk (0x1ul << SDH_CTL_RIEN_Pos) /*!< SDH_T::CTL: RIEN Mask */ + +#define SDH_CTL_DIEN_Pos (2) /*!< SDH_T::CTL: DIEN Position */ +#define SDH_CTL_DIEN_Msk (0x1ul << SDH_CTL_DIEN_Pos) /*!< SDH_T::CTL: DIEN Mask */ + +#define SDH_CTL_DOEN_Pos (3) /*!< SDH_T::CTL: DOEN Position */ +#define SDH_CTL_DOEN_Msk (0x1ul << SDH_CTL_DOEN_Pos) /*!< SDH_T::CTL: DOEN Mask */ + +#define SDH_CTL_R2EN_Pos (4) /*!< SDH_T::CTL: R2EN Position */ +#define SDH_CTL_R2EN_Msk (0x1ul << SDH_CTL_R2EN_Pos) /*!< SDH_T::CTL: R2EN Mask */ + +#define SDH_CTL_CLK74OEN_Pos (5) /*!< SDH_T::CTL: CLK74OEN Position */ +#define SDH_CTL_CLK74OEN_Msk (0x1ul << SDH_CTL_CLK74OEN_Pos) /*!< SDH_T::CTL: CLK74OEN Mask */ + +#define SDH_CTL_CLK8OEN_Pos (6) /*!< SDH_T::CTL: CLK8OEN Position */ +#define SDH_CTL_CLK8OEN_Msk (0x1ul << SDH_CTL_CLK8OEN_Pos) /*!< SDH_T::CTL: CLK8OEN Mask */ + +#define SDH_CTL_CLKKEEP_Pos (7) /*!< SDH_T::CTL: CLKKEEP Position */ +#define SDH_CTL_CLKKEEP_Msk (0x1ul << SDH_CTL_CLKKEEP_Pos) /*!< SDH_T::CTL: CLKKEEP Mask */ + +#define SDH_CTL_CMDCODE_Pos (8) /*!< SDH_T::CTL: CMDCODE Position */ +#define SDH_CTL_CMDCODE_Msk (0x3ful << SDH_CTL_CMDCODE_Pos) /*!< SDH_T::CTL: CMDCODE Mask */ + +#define SDH_CTL_CTLRST_Pos (14) /*!< SDH_T::CTL: CTLRST Position */ +#define SDH_CTL_CTLRST_Msk (0x1ul << SDH_CTL_CTLRST_Pos) /*!< SDH_T::CTL: CTLRST Mask */ + +#define SDH_CTL_DBW_Pos (15) /*!< SDH_T::CTL: DBW Position */ +#define SDH_CTL_DBW_Msk (0x1ul << SDH_CTL_DBW_Pos) /*!< SDH_T::CTL: DBW Mask */ + +#define SDH_CTL_BLKCNT_Pos (16) /*!< SDH_T::CTL: BLKCNT Position */ +#define SDH_CTL_BLKCNT_Msk (0xfful << SDH_CTL_BLKCNT_Pos) /*!< SDH_T::CTL: BLKCNT Mask */ + +#define SDH_CTL_SDNWR_Pos (24) /*!< SDH_T::CTL: SDNWR Position */ +#define SDH_CTL_SDNWR_Msk (0xful << SDH_CTL_SDNWR_Pos) /*!< SDH_T::CTL: SDNWR Mask */ + +#define SDH_CMDARG_ARGUMENT_Pos (0) /*!< SDH_T::CMDARG: ARGUMENT Position */ +#define SDH_CMDARG_ARGUMENT_Msk (0xfffffffful << SDH_CMDARG_ARGUMENT_Pos) /*!< SDH_T::CMDARG: ARGUMENT Mask */ + +#define SDH_INTEN_BLKDIEN_Pos (0) /*!< SDH_T::INTEN: BLKDIEN Position */ +#define SDH_INTEN_BLKDIEN_Msk (0x1ul << SDH_INTEN_BLKDIEN_Pos) /*!< SDH_T::INTEN: BLKDIEN Mask */ + +#define SDH_INTEN_CRCIEN_Pos (1) /*!< SDH_T::INTEN: CRCIEN Position */ +#define SDH_INTEN_CRCIEN_Msk (0x1ul << SDH_INTEN_CRCIEN_Pos) /*!< SDH_T::INTEN: CRCIEN Mask */ + +#define SDH_INTEN_CDIEN_Pos (8) /*!< SDH_T::INTEN: CDIEN Position */ +#define SDH_INTEN_CDIEN_Msk (0x1ul << SDH_INTEN_CDIEN_Pos) /*!< SDH_T::INTEN: CDIEN Mask */ + +#define SDH_INTEN_RTOIEN_Pos (12) /*!< SDH_T::INTEN: RTOIEN Position */ +#define SDH_INTEN_RTOIEN_Msk (0x1ul << SDH_INTEN_RTOIEN_Pos) /*!< SDH_T::INTEN: RTOIEN Mask */ + +#define SDH_INTEN_DITOIEN_Pos (13) /*!< SDH_T::INTEN: DITOIEN Position */ +#define SDH_INTEN_DITOIEN_Msk (0x1ul << SDH_INTEN_DITOIEN_Pos) /*!< SDH_T::INTEN: DITOIEN Mask */ + +#define SDH_INTEN_WKIEN_Pos (14) /*!< SDH_T::INTEN: WKIEN Position */ +#define SDH_INTEN_WKIEN_Msk (0x1ul << SDH_INTEN_WKIEN_Pos) /*!< SDH_T::INTEN: WKIEN Mask */ + +#define SDH_INTEN_CDSRC_Pos (30) /*!< SDH_T::INTEN: CDSRC Position */ +#define SDH_INTEN_CDSRC_Msk (0x1ul << SDH_INTEN_CDSRC_Pos) /*!< SDH_T::INTEN: CDSRC Mask */ + +#define SDH_INTSTS_BLKDIF_Pos (0) /*!< SDH_T::INTSTS: BLKDIF Position */ +#define SDH_INTSTS_BLKDIF_Msk (0x1ul << SDH_INTSTS_BLKDIF_Pos) /*!< SDH_T::INTSTS: BLKDIF Mask */ + +#define SDH_INTSTS_CRCIF_Pos (1) /*!< SDH_T::INTSTS: CRCIF Position */ +#define SDH_INTSTS_CRCIF_Msk (0x1ul << SDH_INTSTS_CRCIF_Pos) /*!< SDH_T::INTSTS: CRCIF Mask */ + +#define SDH_INTSTS_CRC7_Pos (2) /*!< SDH_T::INTSTS: CRC7 Position */ +#define SDH_INTSTS_CRC7_Msk (0x1ul << SDH_INTSTS_CRC7_Pos) /*!< SDH_T::INTSTS: CRC7 Mask */ + +#define SDH_INTSTS_CRC16_Pos (3) /*!< SDH_T::INTSTS: CRC16 Position */ +#define SDH_INTSTS_CRC16_Msk (0x1ul << SDH_INTSTS_CRC16_Pos) /*!< SDH_T::INTSTS: CRC16 Mask */ + +#define SDH_INTSTS_CRCSTS_Pos (4) /*!< SDH_T::INTSTS: CRCSTS Position */ +#define SDH_INTSTS_CRCSTS_Msk (0x7ul << SDH_INTSTS_CRCSTS_Pos) /*!< SDH_T::INTSTS: CRCSTS Mask */ + +#define SDH_INTSTS_DAT0STS_Pos (7) /*!< SDH_T::INTSTS: DAT0STS Position */ +#define SDH_INTSTS_DAT0STS_Msk (0x1ul << SDH_INTSTS_DAT0STS_Pos) /*!< SDH_T::INTSTS: DAT0STS Mask */ + +#define SDH_INTSTS_CDIF_Pos (8) /*!< SDH_T::INTSTS: CDIF Position */ +#define SDH_INTSTS_CDIF_Msk (0x1ul << SDH_INTSTS_CDIF_Pos) /*!< SDH_T::INTSTS: CDIF Mask */ + +#define SDH_INTSTS_RTOIF_Pos (12) /*!< SDH_T::INTSTS: RTOIF Position */ +#define SDH_INTSTS_RTOIF_Msk (0x1ul << SDH_INTSTS_RTOIF_Pos) /*!< SDH_T::INTSTS: RTOIF Mask */ + +#define SDH_INTSTS_DITOIF_Pos (13) /*!< SDH_T::INTSTS: DITOIF Position */ +#define SDH_INTSTS_DITOIF_Msk (0x1ul << SDH_INTSTS_DITOIF_Pos) /*!< SDH_T::INTSTS: DITOIF Mask */ + +#define SDH_INTSTS_CDSTS_Pos (16) /*!< SDH_T::INTSTS: CDSTS Position */ +#define SDH_INTSTS_CDSTS_Msk (0x1ul << SDH_INTSTS_CDSTS_Pos) /*!< SDH_T::INTSTS: CDSTS Mask */ + +#define SDH_INTSTS_DAT1STS_Pos (18) /*!< SDH_T::INTSTS: DAT1STS Position */ +#define SDH_INTSTS_DAT1STS_Msk (0x1ul << SDH_INTSTS_DAT1STS_Pos) /*!< SDH_T::INTSTS: DAT1STS Mask */ + +#define SDH_RESP0_RESPTK0_Pos (0) /*!< SDH_T::RESP0: RESPTK0 Position */ +#define SDH_RESP0_RESPTK0_Msk (0xfffffffful << SDH_RESP0_RESPTK0_Pos) /*!< SDH_T::RESP0: RESPTK0 Mask */ + +#define SDH_RESP1_RESPTK1_Pos (0) /*!< SDH_T::RESP1: RESPTK1 Position */ +#define SDH_RESP1_RESPTK1_Msk (0xfful << SDH_RESP1_RESPTK1_Pos) /*!< SDH_T::RESP1: RESPTK1 Mask */ + +#define SDH_BLEN_BLKLEN_Pos (0) /*!< SDH_T::BLEN: BLKLEN Position */ +#define SDH_BLEN_BLKLEN_Msk (0x7fful << SDH_BLEN_BLKLEN_Pos) /*!< SDH_T::BLEN: BLKLEN Mask */ + +#define SDH_TOUT_TOUT_Pos (0) /*!< SDH_T::TOUT: TOUT Position */ +#define SDH_TOUT_TOUT_Msk (0xfffffful << SDH_TOUT_TOUT_Pos) /*!< SDH_T::TOUT: TOUT Mask */ + +/**@}*/ /* SDH_CONST */ +/**@}*/ /* end of SDH register group */ +/**@}*/ /* end of REGISTER group */ + + +#endif /* __SDH_REG_H__ */ diff --git a/Ubiquitous/XiZi/board/nuvoton-m2354/third_party_driver/include/Regs/spi_reg.h b/Ubiquitous/XiZi/board/nuvoton-m2354/third_party_driver/include/Regs/spi_reg.h new file mode 100644 index 0000000..343b623 --- /dev/null +++ b/Ubiquitous/XiZi/board/nuvoton-m2354/third_party_driver/include/Regs/spi_reg.h @@ -0,0 +1,854 @@ +/**************************************************************************//** + * @file spi_reg.h + * @version V1.00 + * @brief SPI register definition header file + * + * @copyright SPDX-License-Identifier: Apache-2.0 + * @copyright Copyright (C) 2020 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ +#ifndef __SPI_REG_H__ +#define __SPI_REG_H__ + +/** @addtogroup REGISTER Control Register + + @{ + +*/ + +/*---------------------- Serial Peripheral Interface Controller -------------------------*/ +/** + @addtogroup SPI Serial Peripheral Interface Controller(SPI) + Memory Mapped Structure for SPI Controller + @{ +*/ + +typedef struct +{ + + + /** + * @var SPI_T::CTL + * Offset: 0x00 SPI Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |SPIEN |SPI Transfer Control Enable Bit + * | | |In Master mode, the transfer will start when there is data in the FIFO buffer after this bit is set to 1 + * | | |In Slave mode, this device is ready to receive data when this bit is set to 1. + * | | |0 = Transfer control Disabled. + * | | |1 = Transfer control Enabled. + * | | |Note: Before changing the configurations of SPIx_CTL, SPIx_CLKDIV, SPIx_SSCTL and SPIx_FIFOCTL registers, user shall clear the SPIEN (SPIx_CTL[0]) and confirm the SPIENSTS (SPIx_STATUS[15]) is 0. + * |[1] |RXNEG |Receive on Negative Edge + * | | |0 = Received data input signal is latched on the rising edge of SPI bus clock. + * | | |1 = Received data input signal is latched on the falling edge of SPI bus clock. + * |[2] |TXNEG |Transmit on Negative Edge + * | | |0 = Transmitted data output signal is changed on the rising edge of SPI bus clock. + * | | |1 = Transmitted data output signal is changed on the falling edge of SPI bus clock. + * |[3] |CLKPOL |Clock Polarity + * | | |0 = SPI bus clock is idle low. + * | | |1 = SPI bus clock is idle high. + * |[7:4] |SUSPITV |Suspend Interval (Master Only) + * | | |The four bits provide configurable suspend interval between two successive transmit/receive transaction in a transfer + * | | |The definition of the suspend interval is the interval between the last clock edge of the preceding transaction word and the first clock edge of the following transaction word + * | | |The default value is 0x3 + * | | |The period of the suspend interval is obtained according to the following equation. + * | | |(SUSPITV[3:0] + 0.5) * period of SPICLK clock cycle + * | | |Example: + * | | |SUSPITV = 0x0 .... 0.5 SPICLK clock cycle. + * | | |SUSPITV = 0x1 .... 1.5 SPICLK clock cycle. + * | | |..... + * | | |SUSPITV = 0xE .... 14.5 SPICLK clock cycle. + * | | |SUSPITV = 0xF .... 15.5 SPICLK clock cycle. + * |[12:8] |DWIDTH |Data Width + * | | |This field specifies how many bits can be transmitted / received in one transaction + * | | |The minimum bit length is 8 bits and can up to 32 bits. + * | | |DWIDTH = 0x08 .... 8 bits. + * | | |DWIDTH = 0x09 .... 9 bits. + * | | |..... + * | | |DWIDTH = 0x1F .... 31 bits. + * | | |DWIDTH = 0x00 .... 32 bits. + * | | |Note: For SPI0~SPI3, this bit field will decide the depth of TX/RX FIFO configuration in SPI mode + * | | |Therefore, changing this bit field will clear TX/RX FIFO by hardware automatically in SPI0~SPI3. + * |[13] |LSB |Send LSB First + * | | |0 = The MSB, which bit of transmit/receive register depends on the setting of DWIDTH, is transmitted/received first. + * | | |1 = The LSB, bit 0 of the SPI TX register, is sent first to the SPI data output pin, and the first bit received from the SPI data input pin will be put in the LSB position of the RX register (bit 0 of SPI_RX). + * |[14] |HALFDPX |SPI Half-duplex Transfer Enable Bit + * | | |This bit is used to select full-duplex or half-duplex for SPI transfer + * | | |The bit field DATDIR (SPIx_CTL[20]) can be used to set the data direction in half-duplex transfer. + * | | |0 = SPI operates in full-duplex transfer. + * | | |1 = SPI operates in half-duplex transfer. + * |[15] |RXONLY |Receive-only Mode Enable Bit (Master Only) + * | | |This bit field is only available in Master mode + * | | |In receive-only mode, SPI Master will generate SPI bus clock continuously for receiving data bit from SPI slave device and assert the BUSY status. + * | | |0 = Receive-only mode Disabled. + * | | |1 = Receive-only mode Enabled. + * |[17] |UNITIEN |Unit Transfer Interrupt Enable Bit + * | | |0 = SPI unit transfer interrupt Disabled. + * | | |1 = SPI unit transfer interrupt Enabled. + * |[18] |SLAVE |Slave Mode Control + * | | |0 = Master mode. + * | | |1 = Slave mode. + * |[19] |REORDER |Byte Reorder Function Enable Bit + * | | |0 = Byte Reorder function Disabled. + * | | |1 = Byte Reorder function Enabled + * | | |A byte suspend interval will be inserted among each byte + * | | |The period of the byte suspend interval depends on the setting of SUSPITV. + * | | |Note: Byte Reorder function is only available if DWIDTH is defined as 16, 24, and 32 bits. + * |[20] |DATDIR |Data Port Direction Control + * | | |This bit is used to select the data input/output direction in half-duplex transfer and Dual/Quad transfer + * | | |0 = SPI data is input direction. + * | | |1 = SPI data is output direction. + * @var SPI_T::CLKDIV + * Offset: 0x04 SPI Clock Divider Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[8:0] |DIVIDER |Clock Divider + * | | |The value in this field is the frequency divider for generating the peripheral clock, fspi_eclk, and the SPI bus clock of SPI Master + * | | |The frequency is obtained according to the following equation. + * | | |where + * | | |is the peripheral clock source, which is defined in the clock control register, CLK_CLKSEL2. + * | | |Note 1: Not supported in I2S mode. + * | | |Note 2: The time interval must be larger than or equal 5 peripheral clock cycles between releasing SPI IP software reset and setting this clock divider register. + * @var SPI_T::SSCTL + * Offset: 0x08 SPI Slave Select Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |SS |Slave Selection Control + * | | |If AUTOSS bit is cleared to 0, + * | | |0 = set the SPIx_SS line to inactive state. + * | | |1 = set the SPIx_SS line to active state. + * | | |If the AUTOSS bit is set to 1, + * | | |0 = Keep the SPIx_SS line at inactive state. + * | | |1 = SPIx_SS line will be automatically driven to active state for the duration of data transfer, and will be driven to inactive state for the rest of the time + * | | |The active state of SPIx_SS is specified in SSACTPOL (SPIx_SSCTL[2]). + * | | |Note: Master mode only. + * |[2] |SSACTPOL |Slave Selection Active Polarity + * | | |This bit defines the active polarity of slave selection signal (SPIx_SS). + * | | |0 = The slave selection signal SPIx_SS is active low. + * | | |1 = The slave selection signal SPIx_SS is active high. + * |[3] |AUTOSS |Automatic Slave Selection Function Enable Bit (Master Only) + * | | |0 = Automatic slave selection function Disabled + * | | |Slave selection signal will be asserted/de-asserted according to SS (SPIx_SSCTL[0]). + * | | |1 = Automatic slave selection function Enabled. + * | | |Note: Master mode only. + * |[4] |SLV3WIRE |Slave 3-wire Mode Enable Bit + * | | |In Slave 3-wire mode, the SPI controller can work with 3-wire interface including SPIx_CLK, SPIx_MISO and SPIx_MOSI pins. + * | | |0 = 4-wire bi-direction interface. + * | | |1 = 3-wire bi-direction interface. + * | | |Note: The value of this register equals to control register SLAVE (SPIx_I2SCTL[8]) when I2S mode is enabled. + * |[8] |SLVBEIEN |Slave Mode Bit Count Error Interrupt Enable Bit + * | | |0 = Slave mode bit count error interrupt Disabled. + * | | |1 = Slave mode bit count error interrupt Enabled. + * |[9] |SLVURIEN |Slave Mode TX Under Run Interrupt Enable Bit + * | | |0 = Slave mode TX under run interrupt Disabled. + * | | |1 = Slave mode TX under run interrupt Enabled. + * |[12] |SSACTIEN |Slave Select Active Interrupt Enable Bit + * | | |0 = Slave select active interrupt Disabled. + * | | |1 = Slave select active interrupt Enabled. + * |[13] |SSINAIEN |Slave Select Inactive Interrupt Enable Bit + * | | |0 = Slave select inactive interrupt Disabled. + * | | |1 = Slave select inactive interrupt Enabled. + * @var SPI_T::PDMACTL + * Offset: 0x0C SPI PDMA Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |TXPDMAEN |Transmit PDMA Enable Bit + * | | |0 = Transmit PDMA function Disabled. + * | | |1 = Transmit PDMA function Enabled. + * | | |Note: In SPI Master mode with full duplex transfer, if both TX and RX PDMA functions are enabled, RX PDMA function cannot be enabled prior to TX PDMA function + * | | |User can enable TX PDMA function firstly or enable both functions simultaneously. + * |[1] |RXPDMAEN |Receive PDMA Enable Bit + * | | |0 = Receive PDMA function Disabled. + * | | |1 = Receive PDMA function Enabled. + * |[2] |PDMARST |PDMA Reset + * | | |0 = No effect. + * | | |1 = Reset the PDMA control logic of the SPI controller. This bit will be automatically cleared to 0. + * @var SPI_T::FIFOCTL + * Offset: 0x10 SPI FIFO Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |RXRST |Receive Reset + * | | |0 = No effect. + * | | |1 = Reset receive FIFO pointer and receive circuit + * | | |The RXFULL bit will be cleared to 0 and the RXEMPTY bit will be set to 1 + * | | |This bit will be cleared to 0 by hardware about 3 system clock cycles + 2 peripheral clock cycles after it is set to 1 + * | | |User can read TXRXRST (SPIx_STATUS[23]) to check if reset is accomplished or not. + * |[1] |TXRST |Transmit Reset + * | | |0 = No effect. + * | | |1 = Reset transmit FIFO pointer and transmit circuit + * | | |The TXFULL bit will be cleared to 0 and the TXEMPTY bit will be set to 1 + * | | |This bit will be cleared to 0 by hardware about 3 system clock cycles + 2 peripheral clock cycles after it is set to 1 + * | | |User can read TXRXRST (SPIx_STATUS[23]) to check if reset is accomplished or not. + * | | |Note: If TX underflow event occurs in SPI Slave mode, this bit can be used to make SPI return to idle state. + * |[2] |RXTHIEN |Receive FIFO Threshold Interrupt Enable Bit + * | | |0 = RX FIFO threshold interrupt Disabled. + * | | |1 = RX FIFO threshold interrupt Enabled. + * |[3] |TXTHIEN |Transmit FIFO Threshold Interrupt Enable Bit + * | | |0 = TX FIFO threshold interrupt Disabled. + * | | |1 = TX FIFO threshold interrupt Enabled. + * |[4] |RXTOIEN |Receive Time-out Interrupt Enable Bit + * | | |0 = Receive time-out interrupt Disabled. + * | | |1 = Receive time-out interrupt Enabled. + * |[5] |RXOVIEN |Receive FIFO Overrun Interrupt Enable Bit + * | | |0 = Receive FIFO overrun interrupt Disabled. + * | | |1 = Receive FIFO overrun interrupt Enabled. + * |[6] |TXUFPOL |TX Underflow Data Polarity + * | | |0 = The SPI data out is keep 0 if there is TX underflow event in Slave mode. + * | | |1 = The SPI data out is keep 1 if there is TX underflow event in Slave mode. + * | | |Note: + * | | |1. The TX underflow event occurs if there is no any data in TX FIFO when the slave selection signal is active. + * | | |2. This bit should be set as 0 in I2S mode. + * | | |3. When TX underflow event occurs, SPIx_MISO pin state will be determined by this setting even though TX FIFO is not empty afterward + * | | |Data stored in TX FIFO will be sent through SPIx_MISO pin in the next transfer frame. + * |[7] |TXUFIEN |TX Underflow Interrupt Enable Bit + * | | |When TX underflow event occurs in Slave mode, TXUFIF (SPIx_STATUS[19]) will be set to 1 + * | | |This bit is used to enable the TX underflow interrupt. + * | | |0 = Slave TX underflow interrupt Disabled. + * | | |1 = Slave TX underflow interrupt Enabled. + * |[8] |RXFBCLR |Receive FIFO Buffer Clear + * | | |0 = No effect. + * | | |1 = Clear receive FIFO pointer + * | | |The RXFULL bit will be cleared to 0 and the RXEMPTY bit will be set to 1 + * | | |This bit will be cleared to 0 by hardware about 1 system clock after it is set to 1. + * | | |Note: The RX shift register will not be cleared. + * |[9] |TXFBCLR |Transmit FIFO Buffer Clear + * | | |0 = No effect. + * | | |1 = Clear transmit FIFO pointer + * | | |The TXFULL bit will be cleared to 0 and the TXEMPTY bit will be set to 1 + * | | |This bit will be cleared to 0 by hardware about 1 system clock after it is set to 1. + * | | |Note: The TX shift register will not be cleared. + * |[10] |SLVBERX |RX FIFO Write Data Enable Bit When Slave Mode Bit Count Error + * | | |0 = Uncompleted RX data will be dropped from RX FIFO when bit count error event happened in SPI Slave mode. + * | | |1 = Uncompleted RX data will be written into RX FIFO when bit count error event happened in SPI Slave mode + * | | |User can read SLVBENUM (SPIx_STATUS2[29:24]) to know that the effective bit number of uncompleted RX data when SPI slave bit count error happened. + * | | |Note: Slave mode only. + * |[26:24] |RXTH |Receive FIFO Threshold + * | | |If the valid data count of the receive FIFO buffer is larger than the RXTH setting, the RXTHIF bit will be set to 1, else the RXTHIF bit will be cleared to 0 + * | | |For SPI0~SPI3, the MSB of this bit field is only meaningful while SPI mode 8~16 bits of data length. + * |[30:28] |TXTH |Transmit FIFO Threshold + * | | |If the valid data count of the transmit FIFO buffer is less than or equal to the TXTH setting, the TXTHIF bit will be set to 1, else the TXTHIF bit will be cleared to 0 + * | | |For SPI0~SPI3, the MSB of this bit field is only meaningful while SPI mode 8~16 bits of data length. + * @var SPI_T::STATUS + * Offset: 0x14 SPI Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |BUSY |Busy Status (Read Only) + * | | |0 = SPI controller is in idle state. + * | | |1 = SPI controller is in busy state. + * | | |The following listing are the bus busy conditions: + * | | |a. SPIx_CTL[0] = 1 and TXEMPTY = 0. + * | | |b + * | | |For SPI Master mode, SPIx_CTL[0] = 1 and TXEMPTY = 1 but the current transaction is not finished yet. + * | | |c. For SPI Master mode, SPIx_CTL[0] = 1 and RXONLY = 1. + * | | |d. + * | | |For SPI Slave mode, the SPIx_CTL[0] = 1 and there is serial clock input into the SPI core logic when slave select is active. + * | | |e. + * | | |For SPI Slave mode, the SPIx_CTL[0] = 1 and the transmit buffer or transmit shift register is not empty even if the slave select is inactive. + * | | |Note: By applications, this SPI busy flag should be used with other status registers in SPIx_STATUS such as TXCNT, RXCNT, TXTHIF, TXFULL, TXEMPTY, RXTHIF, RXFULL, RXEMPTY, and UNITIF + * | | |Therefore the SPI transfer done events of TX/RX operations can be obtained at correct timing point. + * |[1] |UNITIF |Unit Transfer Interrupt Flag + * | | |0 = No transaction has been finished since this bit was cleared to 0. + * | | |1 = SPI controller has finished one unit transfer. + * | | |Note: This bit will be cleared by writing 1 to it. + * |[2] |SSACTIF |Slave Select Active Interrupt Flag + * | | |0 = Slave select active interrupt was cleared or not occurred. + * | | |1 = Slave select active interrupt event occurred. + * | | |Note: Only available in Slave mode. This bit will be cleared by writing 1 to it. + * |[3] |SSINAIF |Slave Select Inactive Interrupt Flag + * | | |0 = Slave select inactive interrupt was cleared or not occurred. + * | | |1 = Slave select inactive interrupt event occurred. + * | | |Note: Only available in Slave mode. This bit will be cleared by writing 1 to it. + * |[4] |SSLINE |Slave Select Line Bus Status (Read Only) + * | | |0 = The slave select line status is 0. + * | | |1 = The slave select line status is 1. + * | | |Note: This bit is only available in Slave mode + * | | |If SSACTPOL (SPIx_SSCTL[2]) is set 0, and the SSLINE is 1, the SPI slave select is in inactive status. + * |[6] |SLVBEIF |Slave Mode Bit Count Error Interrupt Flag + * | | |In Slave mode, when the slave select line goes to inactive state, if bit counter is mismatch with DWIDTH, this interrupt flag will be set to 1. + * | | |0 = No Slave mode bit count error event. + * | | |1 = Slave mode bit count error event occurs. + * | | |Note: If the slave select active but there is no any bus clock input, the SLVBEIF also active when the slave select goes to inactive state + * | | |This bit will be cleared by writing 1 to it. + * |[7] |SLVURIF |Slave Mode TX Under Run Interrupt Flag + * | | |In Slave mode, if TX underflow event occurs and the slave select line goes to inactive state, this interrupt flag will be set to 1. + * | | |0 = No Slave TX under run event. + * | | |1 = Slave TX under run event occurs. + * | | |Note: This bit will be cleared by writing 1 to it. + * |[8] |RXEMPTY |Receive FIFO Buffer Empty Indicator (Read Only) + * | | |0 = Receive FIFO buffer is not empty. + * | | |1 = Receive FIFO buffer is empty. + * |[9] |RXFULL |Receive FIFO Buffer Full Indicator (Read Only) + * | | |0 = Receive FIFO buffer is not full. + * | | |1 = Receive FIFO buffer is full. + * |[10] |RXTHIF |Receive FIFO Threshold Interrupt Flag (Read Only) + * | | |0 = The valid data count within the receive FIFO buffer is smaller than or equal to the setting value of RXTH. + * | | |1 = The valid data count within the receive FIFO buffer is larger than the setting value of RXTH. + * |[11] |RXOVIF |Receive FIFO Overrun Interrupt Flag + * | | |When the receive FIFO buffer is full, the follow-up data will be dropped and this bit will be set to 1. + * | | |0 = No FIFO is overrun. + * | | |1 = Receive FIFO is overrun. + * | | |Note: This bit will be cleared by writing 1 to it. + * |[12] |RXTOIF |Receive Time-out Interrupt Flag + * | | |0 = No receive FIFO time-out event. + * | | |1 = Receive FIFO buffer is not empty and no read operation on receive FIFO buffer over 64 SPI peripheral clock periods in Master mode or over 576 SPI peripheral clock periods in Slave mode + * | | |When the received FIFO buffer is read by software, the time-out status will be cleared automatically. + * | | |Note: This bit will be cleared by writing 1 to it. + * |[15] |SPIENSTS |SPI Enable Status (Read Only) + * | | |0 = The SPI controller is disabled. + * | | |1 = The SPI controller is enabled. + * | | |Note: The SPI peripheral clock is asynchronous with the system clock + * | | |In order to make sure the SPI control logic is disabled, this bit indicates the real status of SPI controller. + * |[16] |TXEMPTY |Transmit FIFO Buffer Empty Indicator (Read Only) + * | | |0 = Transmit FIFO buffer is not empty. + * | | |1 = Transmit FIFO buffer is empty. + * |[17] |TXFULL |Transmit FIFO Buffer Full Indicator (Read Only) + * | | |0 = Transmit FIFO buffer is not full. + * | | |1 = Transmit FIFO buffer is full. + * |[18] |TXTHIF |Transmit FIFO Threshold Interrupt Flag (Read Only) + * | | |0 = The valid data count within the transmit FIFO buffer is larger than the setting value of TXTH. + * | | |1 = The valid data count within the transmit FIFO buffer is less than or equal to the setting value of TXTH. + * |[19] |TXUFIF |TX Underflow Interrupt Flag + * | | |When the TX underflow event occurs, this bit will be set to 1, the state of data output pin depends on the setting of TXUFPOL. + * | | |0 = No effect. + * | | |1 = No data in Transmit FIFO and TX shift register when the slave selection signal is active. + * | | |Note 1: This bit will be cleared by writing 1 to it. + * | | |Note 2: If reset slave's transmission circuit when slave selection signal is active, this flag will be set to 1 after 2 peripheral clock cycles + 3 system clock cycles since the reset operation is done. + * |[23] |TXRXRST |TX or RX Reset Status (Read Only) + * | | |0 = The reset function of TXRST or RXRST is done. + * | | |1 = Doing the reset function of TXRST or RXRST. + * | | |Note: Both the reset operations of TXRST and RXRST need 3 system clock cycles + 2 peripheral clock cycles + * | | |User can check the status of this bit to monitor the reset function is doing or done. + * |[27:24] |RXCNT |Receive FIFO Data Count (Read Only) + * | | |This bit field indicates the valid data count of receive FIFO buffer. + * |[31:28] |TXCNT |Transmit FIFO Data Count (Read Only) + * | | |This bit field indicates the valid data count of transmit FIFO buffer. + * @var SPI_T::STATUS2 + * Offset: 0x18 SPI Status2 Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[29:24] |SLVBENUM |Effective Bit Number of Uncompleted RX Data + * | | |This status register indicates that effective bit number of uncompleted RX data when SLVBERX (SPIx_FIFOCTL[10]) is enabled and RX bit count error event happen in SPI Slave mode + * | | |This status register will be fixed to 0x0 when SLVBERX (SPIx_FIFOCTL[10]) is disabled. + * | | |Note 1: This register will be cleared to 0x0 when user writes 0x1 to SLVBEIF (SPIx_STATUS[6]). + * | | |Note 2: Slave mode only. + * @var SPI_T::TX + * Offset: 0x20 SPI Data Transmit Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |TX |Data Transmit Register + * | | |The data transmit registers pass through the transmitted data into the 4-level transmit FIFO buffers + * | | |The number of valid bits depends on the setting of DWIDTH (SPIx_CTL[12:8]) in SPI mode or WDWIDTH (SPIx_I2SCTL[5:4]) in I2S mode. + * | | |In SPI mode, if DWIDTH is set to 0x08, the bits TX[7:0] will be transmitted + * | | |If DWIDTH is set to 0x00 , the SPI controller will perform a 32-bit transfer. + * | | |In I2S mode, if WDWIDTH (SPIx_I2SCTL[5:4]) is set to 0x2, the data width of audio channel is 24-bit and corresponding to TX[23:0] + * | | |If WDWIDTH is set as 0x0, 0x1, or 0x3, all bits of this field are valid and referred to the data arrangement in I2S mode FIFO operation section + * | | |Note: In Master mode, SPI controller will start to transfer the SPI bus clock after 1 APB clock and 6 peripheral clock cycles after user writes to this register. + * @var SPI_T::RX + * Offset: 0x30 SPI Data Receive Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |RX |Data Receive Register (Read Only) + * | | |There are 4-level FIFO buffers in this controller. + * | | |The data receive register holds the data received from SPI data input pin. + * | | |If the RXEMPTY (SPIx_STATUS[8] or SPIx_I2SSTS[8]) is not set to 1, the receive FIFO buffers can be accessed through software by reading this register. + * @var SPI_T::I2SCTL + * Offset: 0x60 I2S Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |I2SEN |I2S Controller Enable Bit + * | | |0 = Disabled I2S mode. + * | | |1 = Enabled I2S mode. + * | | |Note: + * | | |1. If enable this bit, I2Sx_BCLK will start to output in Master mode. + * | | |2 + * | | |Before changing the configurations of SPIx_I2SCTL, SPIx_I2SCLK, and SPIx_FIFOCTL registers, user shall clear the I2SEN (SPIx_I2SCTL[0]) and confirm the I2SENSTS (SPIx_I2SSTS[15]) is 0. + * |[1] |TXEN |Transmit Enable Bit + * | | |0 = Data transmit Disabled. + * | | |1 = Data transmit Enabled. + * |[2] |RXEN |Receive Enable Bit + * | | |0 = Data receive Disabled. + * | | |1 = Data receive Enabled. + * |[3] |MUTE |Transmit Mute Enable Bit + * | | |0 = Transmit data is shifted from buffer. + * | | |1 = Transmit channel zero. + * |[5:4] |WDWIDTH |Word Width + * | | |00 = data size is 8-bit. + * | | |01 = data size is 16-bit. + * | | |10 = data size is 24-bit. + * | | |11 = data size is 32-bit. + * |[6] |MONO |Monaural Data + * | | |0 = Data is stereo format. + * | | |1 = Data is monaural format. + * |[7] |ORDER |Stereo Data Order in FIFO + * | | |0 = Left channel data at high byte. + * | | |1 = Left channel data at low byte. + * |[8] |SLAVE |Slave Mode + * | | |I2S can operate as master or slave + * | | |For Master mode, I2Sx_BCLK and I2Sx_LRCLK pins are output mode and send bit clock from NuMicro M2354 series to audio CODEC chip + * | | |In Slave mode, I2Sx_BCLK and I2Sx_LRCLK pins are input mode and I2Sx_BCLK and I2Sx_LRCLK signals are received from outer audio CODEC chip. + * | | |0 = Master mode. + * | | |1 = Slave mode. + * |[15] |MCLKEN |Master Clock Enable Bit + * | | |If MCLKEN is set to 1, I2S controller will generate master clock on SPIx_I2SMCLK pin for external audio devices. + * | | |0 = Master clock Disabled. + * | | |1 = Master clock Enabled. + * |[16] |RZCEN |Right Channel Zero Cross Detection Enable Bit + * | | |If this bit is set to 1, when right channel data sign bit change or next shift data bits are all 0 then RZCIF flag in SPIx_I2SSTS register is set to 1 + * | | |This function is only available in transmit operation. + * | | |0 = Right channel zero cross detection Disabled. + * | | |1 = Right channel zero cross detection Enabled. + * |[17] |LZCEN |Left Channel Zero Cross Detection Enable Bit + * | | |If this bit is set to 1, when left channel data sign bit changes or next shift data bits are all 0 then LZCIF flag in SPIx_I2SSTS register is set to 1 + * | | |This function is only available in transmit operation. + * | | |0 = Left channel zero cross detection Disabled. + * | | |1 = Left channel zero cross detection Enabled. + * |[23] |RXLCH |Receive Left Channel Enable Bit + * | | |When monaural format is selected (MONO = 1), I2S controller will receive right channel data if RXLCH is set to 0, and receive left channel data if RXLCH is set to 1. + * | | |0 = Receive right channel data in Mono mode. + * | | |1 = Receive left channel data in Mono mode. + * |[24] |RZCIEN |Right Channel Zero Cross Interrupt Enable Bit + * | | |Interrupt occurs if this bit is set to 1 and right channel zero cross event occurs. + * | | |0 = Interrupt Disabled. + * | | |1 = Interrupt Enabled. + * |[25] |LZCIEN |Left Channel Zero Cross Interrupt Enable Bit + * | | |Interrupt occurs if this bit is set to 1 and left channel zero cross event occurs. + * | | |0 = Interrupt Disabled. + * | | |1 = Interrupt Enabled. + * |[29:28] |FORMAT |Data Format Selection + * | | |00 = I2S data format. + * | | |01 = MSB justified data format. + * | | |10 = PCM mode A. + * | | |11 = PCM mode B. + * |[31] |SLVERRIEN |Bit Clock Loss Interrupt Enable Bit for Slave Mode + * | | |Interrupt occurs if this bit is set to 1 and bit clock loss event occurs. + * | | |0 = Interrupt Disabled. + * | | |1 = Interrupt Enabled. + * @var SPI_T::I2SCLK + * Offset: 0x64 I2S Clock Divider Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[6:0] |MCLKDIV |Master Clock Divider + * | | |If MCLKEN is set to 1, I2S controller will generate master clock for external audio devices. + * | | |The frequency of master clock, F_MCLK, is determined by the following expressions: + * | | |If MCLKDIV >= 1, F_MCLK = F_I2SCLK/(2x(MCLKDIV)). + * | | |If MCLKDIV = 0, F_MCLK = F_I2SCLK. + * | | |where + * | | |is the frequency of I2S peripheral clock source, which is defined in the clock control register CLK_CLKSEL2. + * | | |F_I2SCLK is the frequency of I2S peripheral clock. + * | | |In general, the master clock rate is 256 times sampling clock rate. + * |[17:8] |BCLKDIV |Bit Clock Divider + * | | |The I2S controller will generate bit clock in Master mode. + * | | |The clock frequency of bit clock, F_BCLK, is determined by the following expression: + * | | |F_BCLK = F_I2SCLK/(2x(BCLKDIV + 1)), + * | | |where + * | | |F_I2SCLK is the frequency of I2S peripheral clock source, which is defined in the clock control register CLK_CLKSEL2. + * | | |In I2S Slave mode, this field is used to define the frequency of peripheral clock and it's determined by F_I2SCLK/(BCLKDIV/2 + 1). + * | | |The peripheral clock frequency in I2S Slave mode must be equal to or faster than 6 times of input bit clock. + * |[24] |I2SMODE |I2S Clock Divider Number Selection for I2S Mode and SPI Mode + * | | |User sets I2SMODE to set frequency of peripheral clock of I2S mode or SPI mode when BCLKDIV (SPIx_I2SCLK[17:8]) or DIVIDER (SPIx_CLKDIV[8:0]) is set. + * | | |User needs to set I2SMODE before I2SEN (SPIx_I2SCTL[0]) or SPIEN (SPIx_CTL[0]) is enabled. + * | | |0 = The frequency of peripheral clock is set to SPI mode. + * | | |1 = The frequency of peripheral clock is set to I2S mode. + * |[25] |I2SSLAVE |I2S Clock Divider Number Selection for I2S Slave Mode and I2S Master Mode + * | | |User sets I2SSLAVE to set frequency of peripheral clock of I2S master mode and I2S slave mode when BCLKDIV (SPIx_I2SCLK[17:8]) is set. + * | | |I2SSLAVE needs to set before I2SEN (SPIx_I2SCTL[0]) is enabled. + * | | |0 = The frequency of peripheral clock is set to I2S Master mode. + * | | |1 = The frequency of peripheral clock is set to I2S Slave mode. + * @var SPI_T::I2SSTS + * Offset: 0x68 I2S Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[4] |RIGHT |Right Channel (Read Only) + * | | |This bit indicates the current transmit data is belong to which channel. + * | | |0 = Left channel. + * | | |1 = Right channel. + * |[8] |RXEMPTY |Receive FIFO Buffer Empty Indicator (Read Only) + * | | |0 = Receive FIFO buffer is not empty. + * | | |1 = Receive FIFO buffer is empty. + * |[9] |RXFULL |Receive FIFO Buffer Full Indicator (Read Only) + * | | |0 = Receive FIFO buffer is not full. + * | | |1 = Receive FIFO buffer is full. + * |[10] |RXTHIF |Receive FIFO Threshold Interrupt Flag (Read Only) + * | | |0 = The valid data count within the receive FIFO buffer is smaller than or equal to the setting value of RXTH. + * | | |1 = The valid data count within the receive FIFO buffer is larger than the setting value of RXTH. + * | | |Note: If RXTHIEN = 1 and RXTHIF = 1, the SPI/I2S controller will generate a SPI interrupt request. + * |[11] |RXOVIF |Receive FIFO Overrun Interrupt Flag + * | | |When the receive FIFO buffer is full, the follow-up data will be dropped and this bit will be set to 1. + * | | |Note: This bit will be cleared by writing 1 to it. + * |[12] |RXTOIF |Receive Time-out Interrupt Flag + * | | |0 = No receive FIFO time-out event. + * | | |1 = Receive FIFO buffer is not empty and no read operation on receive FIFO buffer over 64 SPI peripheral clock period in Master mode or over 576 SPI peripheral clock period in Slave mode + * | | |When the received FIFO buffer is read by software, the time-out status will be cleared automatically. + * | | |Note: This bit will be cleared by writing 1 to it. + * |[15] |I2SENSTS |I2S Enable Status (Read Only) + * | | |0 = The SPI/I2S control logic is disabled. + * | | |1 = The SPI/I2S control logic is enabled. + * | | |Note: The SPI peripheral clock is asynchronous with the system clock + * | | |In order to make sure the SPI/I2S control logic is disabled, this bit indicates the real status of SPI/I2S control logic for user. + * |[16] |TXEMPTY |Transmit FIFO Buffer Empty Indicator (Read Only) + * | | |0 = Transmit FIFO buffer is not empty. + * | | |1 = Transmit FIFO buffer is empty. + * |[17] |TXFULL |Transmit FIFO Buffer Full Indicator (Read Only) + * | | |0 = Transmit FIFO buffer is not full. + * | | |1 = Transmit FIFO buffer is full. + * |[18] |TXTHIF |Transmit FIFO Threshold Interrupt Flag (Read Only) + * | | |0 = The valid data count within the transmit FIFO buffer is larger than the setting value of TXTH. + * | | |1 = The valid data count within the transmit FIFO buffer is less than or equal to the setting value of TXTH. + * | | |Note: If TXTHIEN = 1 and TXTHIF = 1, the SPI/I2S controller will generate a SPI interrupt request. + * |[19] |TXUFIF |Transmit FIFO Underflow Interrupt Flag + * | | |When the transmit FIFO buffer is empty and there is no datum written into the FIFO buffer, if there is more bus clock input, this bit will be set to 1. + * | | |Note: This bit will be cleared by writing 1 to it. + * |[20] |RZCIF |Right Channel Zero Cross Interrupt Flag + * | | |0 = No zero cross event occurred on right channel. + * | | |1 = Zero cross event occurred on right channel. + * |[21] |LZCIF |Left Channel Zero Cross Interrupt Flag + * | | |0 = No zero cross event occurred on left channel. + * | | |1 = Zero cross event occurred on left channel. + * |[22] |SLVERRIF |Bit Clock Loss Interrupt Flag for Slave Mode + * | | |0 = No bit clock loss event occurred. + * | | |1 = Bit clock loss event occurred. + * | | |Note: This bit will be cleared by writing 1 to it. + * |[23] |TXRXRST |TX or RX Reset Status (Read Only) + * | | |0 = The reset function of TXRST or RXRST is done. + * | | |1 = Doing the reset function of TXRST or RXRST. + * | | |Note: Both the reset operations of TXRST and RXRST need 3 system clock cycles + 2 peripheral clock cycles + * | | |User can check the status of this bit to monitor the reset function is doing or done. + * |[26:24] |RXCNT |Receive FIFO Data Count (Read Only) + * | | |This bit field indicates the valid data count of receive FIFO buffer. + * |[30:28] |TXCNT |Transmit FIFO Data Count (Read Only) + * | | |This bit field indicates the valid data count of transmit FIFO buffer. + */ + __IO uint32_t CTL; /*!< [0x0000] SPI Control Register */ + __IO uint32_t CLKDIV; /*!< [0x0004] SPI Clock Divider Register */ + __IO uint32_t SSCTL; /*!< [0x0008] SPI Slave Select Control Register */ + __IO uint32_t PDMACTL; /*!< [0x000c] SPI PDMA Control Register */ + __IO uint32_t FIFOCTL; /*!< [0x0010] SPI FIFO Control Register */ + __IO uint32_t STATUS; /*!< [0x0014] SPI Status Register */ + __I uint32_t STATUS2; /*!< [0x0018] SPI Status2 Register */ + __I uint32_t RESERVE0[1]; + __O uint32_t TX; /*!< [0x0020] SPI Data Transmit Register */ + __I uint32_t RESERVE1[3]; + __I uint32_t RX; /*!< [0x0030] SPI Data Receive Register */ + __I uint32_t RESERVE2[11]; + __IO uint32_t I2SCTL; /*!< [0x0060] I2S Control Register */ + __IO uint32_t I2SCLK; /*!< [0x0064] I2S Clock Divider Control Register */ + __IO uint32_t I2SSTS; /*!< [0x0068] I2S Status Register */ + +} SPI_T; + +/** + @addtogroup SPI_CONST SPI Bit Field Definition + Constant Definitions for SPI Controller + @{ +*/ + +#define SPI_CTL_SPIEN_Pos (0) /*!< SPI_T::CTL: SPIEN Position */ +#define SPI_CTL_SPIEN_Msk (0x1ul << SPI_CTL_SPIEN_Pos) /*!< SPI_T::CTL: SPIEN Mask */ + +#define SPI_CTL_RXNEG_Pos (1) /*!< SPI_T::CTL: RXNEG Position */ +#define SPI_CTL_RXNEG_Msk (0x1ul << SPI_CTL_RXNEG_Pos) /*!< SPI_T::CTL: RXNEG Mask */ + +#define SPI_CTL_TXNEG_Pos (2) /*!< SPI_T::CTL: TXNEG Position */ +#define SPI_CTL_TXNEG_Msk (0x1ul << SPI_CTL_TXNEG_Pos) /*!< SPI_T::CTL: TXNEG Mask */ + +#define SPI_CTL_CLKPOL_Pos (3) /*!< SPI_T::CTL: CLKPOL Position */ +#define SPI_CTL_CLKPOL_Msk (0x1ul << SPI_CTL_CLKPOL_Pos) /*!< SPI_T::CTL: CLKPOL Mask */ + +#define SPI_CTL_SUSPITV_Pos (4) /*!< SPI_T::CTL: SUSPITV Position */ +#define SPI_CTL_SUSPITV_Msk (0xful << SPI_CTL_SUSPITV_Pos) /*!< SPI_T::CTL: SUSPITV Mask */ + +#define SPI_CTL_DWIDTH_Pos (8) /*!< SPI_T::CTL: DWIDTH Position */ +#define SPI_CTL_DWIDTH_Msk (0x1ful << SPI_CTL_DWIDTH_Pos) /*!< SPI_T::CTL: DWIDTH Mask */ + +#define SPI_CTL_LSB_Pos (13) /*!< SPI_T::CTL: LSB Position */ +#define SPI_CTL_LSB_Msk (0x1ul << SPI_CTL_LSB_Pos) /*!< SPI_T::CTL: LSB Mask */ + +#define SPI_CTL_HALFDPX_Pos (14) /*!< SPI_T::CTL: HALFDPX Position */ +#define SPI_CTL_HALFDPX_Msk (0x1ul << SPI_CTL_HALFDPX_Pos) /*!< SPI_T::CTL: HALFDPX Mask */ + +#define SPI_CTL_RXONLY_Pos (15) /*!< SPI_T::CTL: RXONLY Position */ +#define SPI_CTL_RXONLY_Msk (0x1ul << SPI_CTL_RXONLY_Pos) /*!< SPI_T::CTL: RXONLY Mask */ + +#define SPI_CTL_UNITIEN_Pos (17) /*!< SPI_T::CTL: UNITIEN Position */ +#define SPI_CTL_UNITIEN_Msk (0x1ul << SPI_CTL_UNITIEN_Pos) /*!< SPI_T::CTL: UNITIEN Mask */ + +#define SPI_CTL_SLAVE_Pos (18) /*!< SPI_T::CTL: SLAVE Position */ +#define SPI_CTL_SLAVE_Msk (0x1ul << SPI_CTL_SLAVE_Pos) /*!< SPI_T::CTL: SLAVE Mask */ + +#define SPI_CTL_REORDER_Pos (19) /*!< SPI_T::CTL: REORDER Position */ +#define SPI_CTL_REORDER_Msk (0x1ul << SPI_CTL_REORDER_Pos) /*!< SPI_T::CTL: REORDER Mask */ + +#define SPI_CTL_DATDIR_Pos (20) /*!< SPI_T::CTL: DATDIR Position */ +#define SPI_CTL_DATDIR_Msk (0x1ul << SPI_CTL_DATDIR_Pos) /*!< SPI_T::CTL: DATDIR Mask */ + +#define SPI_CLKDIV_DIVIDER_Pos (0) /*!< SPI_T::CLKDIV: DIVIDER Position */ +#define SPI_CLKDIV_DIVIDER_Msk (0x1fful << SPI_CLKDIV_DIVIDER_Pos) /*!< SPI_T::CLKDIV: DIVIDER Mask */ + +#define SPI_SSCTL_SS_Pos (0) /*!< SPI_T::SSCTL: SS Position */ +#define SPI_SSCTL_SS_Msk (0x1ul << SPI_SSCTL_SS_Pos) /*!< SPI_T::SSCTL: SS Mask */ + +#define SPI_SSCTL_SSACTPOL_Pos (2) /*!< SPI_T::SSCTL: SSACTPOL Position */ +#define SPI_SSCTL_SSACTPOL_Msk (0x1ul << SPI_SSCTL_SSACTPOL_Pos) /*!< SPI_T::SSCTL: SSACTPOL Mask */ + +#define SPI_SSCTL_AUTOSS_Pos (3) /*!< SPI_T::SSCTL: AUTOSS Position */ +#define SPI_SSCTL_AUTOSS_Msk (0x1ul << SPI_SSCTL_AUTOSS_Pos) /*!< SPI_T::SSCTL: AUTOSS Mask */ + +#define SPI_SSCTL_SLV3WIRE_Pos (4) /*!< SPI_T::SSCTL: SLV3WIRE Position */ +#define SPI_SSCTL_SLV3WIRE_Msk (0x1ul << SPI_SSCTL_SLV3WIRE_Pos) /*!< SPI_T::SSCTL: SLV3WIRE Mask */ + +#define SPI_SSCTL_SLVBEIEN_Pos (8) /*!< SPI_T::SSCTL: SLVBEIEN Position */ +#define SPI_SSCTL_SLVBEIEN_Msk (0x1ul << SPI_SSCTL_SLVBEIEN_Pos) /*!< SPI_T::SSCTL: SLVBEIEN Mask */ + +#define SPI_SSCTL_SLVURIEN_Pos (9) /*!< SPI_T::SSCTL: SLVURIEN Position */ +#define SPI_SSCTL_SLVURIEN_Msk (0x1ul << SPI_SSCTL_SLVURIEN_Pos) /*!< SPI_T::SSCTL: SLVURIEN Mask */ + +#define SPI_SSCTL_SSACTIEN_Pos (12) /*!< SPI_T::SSCTL: SSACTIEN Position */ +#define SPI_SSCTL_SSACTIEN_Msk (0x1ul << SPI_SSCTL_SSACTIEN_Pos) /*!< SPI_T::SSCTL: SSACTIEN Mask */ + +#define SPI_SSCTL_SSINAIEN_Pos (13) /*!< SPI_T::SSCTL: SSINAIEN Position */ +#define SPI_SSCTL_SSINAIEN_Msk (0x1ul << SPI_SSCTL_SSINAIEN_Pos) /*!< SPI_T::SSCTL: SSINAIEN Mask */ + +#define SPI_PDMACTL_TXPDMAEN_Pos (0) /*!< SPI_T::PDMACTL: TXPDMAEN Position */ +#define SPI_PDMACTL_TXPDMAEN_Msk (0x1ul << SPI_PDMACTL_TXPDMAEN_Pos) /*!< SPI_T::PDMACTL: TXPDMAEN Mask */ + +#define SPI_PDMACTL_RXPDMAEN_Pos (1) /*!< SPI_T::PDMACTL: RXPDMAEN Position */ +#define SPI_PDMACTL_RXPDMAEN_Msk (0x1ul << SPI_PDMACTL_RXPDMAEN_Pos) /*!< SPI_T::PDMACTL: RXPDMAEN Mask */ + +#define SPI_PDMACTL_PDMARST_Pos (2) /*!< SPI_T::PDMACTL: PDMARST Position */ +#define SPI_PDMACTL_PDMARST_Msk (0x1ul << SPI_PDMACTL_PDMARST_Pos) /*!< SPI_T::PDMACTL: PDMARST Mask */ + +#define SPI_FIFOCTL_RXRST_Pos (0) /*!< SPI_T::FIFOCTL: RXRST Position */ +#define SPI_FIFOCTL_RXRST_Msk (0x1ul << SPI_FIFOCTL_RXRST_Pos) /*!< SPI_T::FIFOCTL: RXRST Mask */ + +#define SPI_FIFOCTL_TXRST_Pos (1) /*!< SPI_T::FIFOCTL: TXRST Position */ +#define SPI_FIFOCTL_TXRST_Msk (0x1ul << SPI_FIFOCTL_TXRST_Pos) /*!< SPI_T::FIFOCTL: TXRST Mask */ + +#define SPI_FIFOCTL_RXTHIEN_Pos (2) /*!< SPI_T::FIFOCTL: RXTHIEN Position */ +#define SPI_FIFOCTL_RXTHIEN_Msk (0x1ul << SPI_FIFOCTL_RXTHIEN_Pos) /*!< SPI_T::FIFOCTL: RXTHIEN Mask */ + +#define SPI_FIFOCTL_TXTHIEN_Pos (3) /*!< SPI_T::FIFOCTL: TXTHIEN Position */ +#define SPI_FIFOCTL_TXTHIEN_Msk (0x1ul << SPI_FIFOCTL_TXTHIEN_Pos) /*!< SPI_T::FIFOCTL: TXTHIEN Mask */ + +#define SPI_FIFOCTL_RXTOIEN_Pos (4) /*!< SPI_T::FIFOCTL: RXTOIEN Position */ +#define SPI_FIFOCTL_RXTOIEN_Msk (0x1ul << SPI_FIFOCTL_RXTOIEN_Pos) /*!< SPI_T::FIFOCTL: RXTOIEN Mask */ + +#define SPI_FIFOCTL_RXOVIEN_Pos (5) /*!< SPI_T::FIFOCTL: RXOVIEN Position */ +#define SPI_FIFOCTL_RXOVIEN_Msk (0x1ul << SPI_FIFOCTL_RXOVIEN_Pos) /*!< SPI_T::FIFOCTL: RXOVIEN Mask */ + +#define SPI_FIFOCTL_TXUFPOL_Pos (6) /*!< SPI_T::FIFOCTL: TXUFPOL Position */ +#define SPI_FIFOCTL_TXUFPOL_Msk (0x1ul << SPI_FIFOCTL_TXUFPOL_Pos) /*!< SPI_T::FIFOCTL: TXUFPOL Mask */ + +#define SPI_FIFOCTL_TXUFIEN_Pos (7) /*!< SPI_T::FIFOCTL: TXUFIEN Position */ +#define SPI_FIFOCTL_TXUFIEN_Msk (0x1ul << SPI_FIFOCTL_TXUFIEN_Pos) /*!< SPI_T::FIFOCTL: TXUFIEN Mask */ + +#define SPI_FIFOCTL_RXFBCLR_Pos (8) /*!< SPI_T::FIFOCTL: RXFBCLR Position */ +#define SPI_FIFOCTL_RXFBCLR_Msk (0x1ul << SPI_FIFOCTL_RXFBCLR_Pos) /*!< SPI_T::FIFOCTL: RXFBCLR Mask */ + +#define SPI_FIFOCTL_TXFBCLR_Pos (9) /*!< SPI_T::FIFOCTL: TXFBCLR Position */ +#define SPI_FIFOCTL_TXFBCLR_Msk (0x1ul << SPI_FIFOCTL_TXFBCLR_Pos) /*!< SPI_T::FIFOCTL: TXFBCLR Mask */ + +#define SPI_FIFOCTL_SLVBERX_Pos (10) /*!< SPI_T::FIFOCTL: SLVBERX Position */ +#define SPI_FIFOCTL_SLVBERX_Msk (0x1ul << SPI_FIFOCTL_SLVBERX_Pos) /*!< SPI_T::FIFOCTL: SLVBERX Mask */ + +#define SPI_FIFOCTL_RXTH_Pos (24) /*!< SPI_T::FIFOCTL: RXTH Position */ +#define SPI_FIFOCTL_RXTH_Msk (0x7ul << SPI_FIFOCTL_RXTH_Pos) /*!< SPI_T::FIFOCTL: RXTH Mask */ + +#define SPI_FIFOCTL_TXTH_Pos (28) /*!< SPI_T::FIFOCTL: TXTH Position */ +#define SPI_FIFOCTL_TXTH_Msk (0x7ul << SPI_FIFOCTL_TXTH_Pos) /*!< SPI_T::FIFOCTL: TXTH Mask */ + +#define SPI_STATUS_BUSY_Pos (0) /*!< SPI_T::STATUS: BUSY Position */ +#define SPI_STATUS_BUSY_Msk (0x1ul << SPI_STATUS_BUSY_Pos) /*!< SPI_T::STATUS: BUSY Mask */ + +#define SPI_STATUS_UNITIF_Pos (1) /*!< SPI_T::STATUS: UNITIF Position */ +#define SPI_STATUS_UNITIF_Msk (0x1ul << SPI_STATUS_UNITIF_Pos) /*!< SPI_T::STATUS: UNITIF Mask */ + +#define SPI_STATUS_SSACTIF_Pos (2) /*!< SPI_T::STATUS: SSACTIF Position */ +#define SPI_STATUS_SSACTIF_Msk (0x1ul << SPI_STATUS_SSACTIF_Pos) /*!< SPI_T::STATUS: SSACTIF Mask */ + +#define SPI_STATUS_SSINAIF_Pos (3) /*!< SPI_T::STATUS: SSINAIF Position */ +#define SPI_STATUS_SSINAIF_Msk (0x1ul << SPI_STATUS_SSINAIF_Pos) /*!< SPI_T::STATUS: SSINAIF Mask */ + +#define SPI_STATUS_SSLINE_Pos (4) /*!< SPI_T::STATUS: SSLINE Position */ +#define SPI_STATUS_SSLINE_Msk (0x1ul << SPI_STATUS_SSLINE_Pos) /*!< SPI_T::STATUS: SSLINE Mask */ + +#define SPI_STATUS_SLVBEIF_Pos (6) /*!< SPI_T::STATUS: SLVBEIF Position */ +#define SPI_STATUS_SLVBEIF_Msk (0x1ul << SPI_STATUS_SLVBEIF_Pos) /*!< SPI_T::STATUS: SLVBEIF Mask */ + +#define SPI_STATUS_SLVURIF_Pos (7) /*!< SPI_T::STATUS: SLVURIF Position */ +#define SPI_STATUS_SLVURIF_Msk (0x1ul << SPI_STATUS_SLVURIF_Pos) /*!< SPI_T::STATUS: SLVURIF Mask */ + +#define SPI_STATUS_RXEMPTY_Pos (8) /*!< SPI_T::STATUS: RXEMPTY Position */ +#define SPI_STATUS_RXEMPTY_Msk (0x1ul << SPI_STATUS_RXEMPTY_Pos) /*!< SPI_T::STATUS: RXEMPTY Mask */ + +#define SPI_STATUS_RXFULL_Pos (9) /*!< SPI_T::STATUS: RXFULL Position */ +#define SPI_STATUS_RXFULL_Msk (0x1ul << SPI_STATUS_RXFULL_Pos) /*!< SPI_T::STATUS: RXFULL Mask */ + +#define SPI_STATUS_RXTHIF_Pos (10) /*!< SPI_T::STATUS: RXTHIF Position */ +#define SPI_STATUS_RXTHIF_Msk (0x1ul << SPI_STATUS_RXTHIF_Pos) /*!< SPI_T::STATUS: RXTHIF Mask */ + +#define SPI_STATUS_RXOVIF_Pos (11) /*!< SPI_T::STATUS: RXOVIF Position */ +#define SPI_STATUS_RXOVIF_Msk (0x1ul << SPI_STATUS_RXOVIF_Pos) /*!< SPI_T::STATUS: RXOVIF Mask */ + +#define SPI_STATUS_RXTOIF_Pos (12) /*!< SPI_T::STATUS: RXTOIF Position */ +#define SPI_STATUS_RXTOIF_Msk (0x1ul << SPI_STATUS_RXTOIF_Pos) /*!< SPI_T::STATUS: RXTOIF Mask */ + +#define SPI_STATUS_SPIENSTS_Pos (15) /*!< SPI_T::STATUS: SPIENSTS Position */ +#define SPI_STATUS_SPIENSTS_Msk (0x1ul << SPI_STATUS_SPIENSTS_Pos) /*!< SPI_T::STATUS: SPIENSTS Mask */ + +#define SPI_STATUS_TXEMPTY_Pos (16) /*!< SPI_T::STATUS: TXEMPTY Position */ +#define SPI_STATUS_TXEMPTY_Msk (0x1ul << SPI_STATUS_TXEMPTY_Pos) /*!< SPI_T::STATUS: TXEMPTY Mask */ + +#define SPI_STATUS_TXFULL_Pos (17) /*!< SPI_T::STATUS: TXFULL Position */ +#define SPI_STATUS_TXFULL_Msk (0x1ul << SPI_STATUS_TXFULL_Pos) /*!< SPI_T::STATUS: TXFULL Mask */ + +#define SPI_STATUS_TXTHIF_Pos (18) /*!< SPI_T::STATUS: TXTHIF Position */ +#define SPI_STATUS_TXTHIF_Msk (0x1ul << SPI_STATUS_TXTHIF_Pos) /*!< SPI_T::STATUS: TXTHIF Mask */ + +#define SPI_STATUS_TXUFIF_Pos (19) /*!< SPI_T::STATUS: TXUFIF Position */ +#define SPI_STATUS_TXUFIF_Msk (0x1ul << SPI_STATUS_TXUFIF_Pos) /*!< SPI_T::STATUS: TXUFIF Mask */ + +#define SPI_STATUS_TXRXRST_Pos (23) /*!< SPI_T::STATUS: TXRXRST Position */ +#define SPI_STATUS_TXRXRST_Msk (0x1ul << SPI_STATUS_TXRXRST_Pos) /*!< SPI_T::STATUS: TXRXRST Mask */ + +#define SPI_STATUS_RXCNT_Pos (24) /*!< SPI_T::STATUS: RXCNT Position */ +#define SPI_STATUS_RXCNT_Msk (0xful << SPI_STATUS_RXCNT_Pos) /*!< SPI_T::STATUS: RXCNT Mask */ + +#define SPI_STATUS_TXCNT_Pos (28) /*!< SPI_T::STATUS: TXCNT Position */ +#define SPI_STATUS_TXCNT_Msk (0xful << SPI_STATUS_TXCNT_Pos) /*!< SPI_T::STATUS: TXCNT Mask */ + +#define SPI_STATUS2_SLVBENUM_Pos (24) /*!< SPI_T::STATUS2: SLVBENUM Position */ +#define SPI_STATUS2_SLVBENUM_Msk (0x3ful << SPI_STATUS2_SLVBENUM_Pos) /*!< SPI_T::STATUS2: SLVBENUM Mask */ + +#define SPI_TX_TX_Pos (0) /*!< SPI_T::TX: TX Position */ +#define SPI_TX_TX_Msk (0xfffffffful << SPI_TX_TX_Pos) /*!< SPI_T::TX: TX Mask */ + +#define SPI_RX_RX_Pos (0) /*!< SPI_T::RX: RX Position */ +#define SPI_RX_RX_Msk (0xfffffffful << SPI_RX_RX_Pos) /*!< SPI_T::RX: RX Mask */ + +#define SPI_I2SCTL_I2SEN_Pos (0) /*!< SPI_T::I2SCTL: I2SEN Position */ +#define SPI_I2SCTL_I2SEN_Msk (0x1ul << SPI_I2SCTL_I2SEN_Pos) /*!< SPI_T::I2SCTL: I2SEN Mask */ + +#define SPI_I2SCTL_TXEN_Pos (1) /*!< SPI_T::I2SCTL: TXEN Position */ +#define SPI_I2SCTL_TXEN_Msk (0x1ul << SPI_I2SCTL_TXEN_Pos) /*!< SPI_T::I2SCTL: TXEN Mask */ + +#define SPI_I2SCTL_RXEN_Pos (2) /*!< SPI_T::I2SCTL: RXEN Position */ +#define SPI_I2SCTL_RXEN_Msk (0x1ul << SPI_I2SCTL_RXEN_Pos) /*!< SPI_T::I2SCTL: RXEN Mask */ + +#define SPI_I2SCTL_MUTE_Pos (3) /*!< SPI_T::I2SCTL: MUTE Position */ +#define SPI_I2SCTL_MUTE_Msk (0x1ul << SPI_I2SCTL_MUTE_Pos) /*!< SPI_T::I2SCTL: MUTE Mask */ + +#define SPI_I2SCTL_WDWIDTH_Pos (4) /*!< SPI_T::I2SCTL: WDWIDTH Position */ +#define SPI_I2SCTL_WDWIDTH_Msk (0x3ul << SPI_I2SCTL_WDWIDTH_Pos) /*!< SPI_T::I2SCTL: WDWIDTH Mask */ + +#define SPI_I2SCTL_MONO_Pos (6) /*!< SPI_T::I2SCTL: MONO Position */ +#define SPI_I2SCTL_MONO_Msk (0x1ul << SPI_I2SCTL_MONO_Pos) /*!< SPI_T::I2SCTL: MONO Mask */ + +#define SPI_I2SCTL_ORDER_Pos (7) /*!< SPI_T::I2SCTL: ORDER Position */ +#define SPI_I2SCTL_ORDER_Msk (0x1ul << SPI_I2SCTL_ORDER_Pos) /*!< SPI_T::I2SCTL: ORDER Mask */ + +#define SPI_I2SCTL_SLAVE_Pos (8) /*!< SPI_T::I2SCTL: SLAVE Position */ +#define SPI_I2SCTL_SLAVE_Msk (0x1ul << SPI_I2SCTL_SLAVE_Pos) /*!< SPI_T::I2SCTL: SLAVE Mask */ + +#define SPI_I2SCTL_MCLKEN_Pos (15) /*!< SPI_T::I2SCTL: MCLKEN Position */ +#define SPI_I2SCTL_MCLKEN_Msk (0x1ul << SPI_I2SCTL_MCLKEN_Pos) /*!< SPI_T::I2SCTL: MCLKEN Mask */ + +#define SPI_I2SCTL_RZCEN_Pos (16) /*!< SPI_T::I2SCTL: RZCEN Position */ +#define SPI_I2SCTL_RZCEN_Msk (0x1ul << SPI_I2SCTL_RZCEN_Pos) /*!< SPI_T::I2SCTL: RZCEN Mask */ + +#define SPI_I2SCTL_LZCEN_Pos (17) /*!< SPI_T::I2SCTL: LZCEN Position */ +#define SPI_I2SCTL_LZCEN_Msk (0x1ul << SPI_I2SCTL_LZCEN_Pos) /*!< SPI_T::I2SCTL: LZCEN Mask */ + +#define SPI_I2SCTL_RXLCH_Pos (23) /*!< SPI_T::I2SCTL: RXLCH Position */ +#define SPI_I2SCTL_RXLCH_Msk (0x1ul << SPI_I2SCTL_RXLCH_Pos) /*!< SPI_T::I2SCTL: RXLCH Mask */ + +#define SPI_I2SCTL_RZCIEN_Pos (24) /*!< SPI_T::I2SCTL: RZCIEN Position */ +#define SPI_I2SCTL_RZCIEN_Msk (0x1ul << SPI_I2SCTL_RZCIEN_Pos) /*!< SPI_T::I2SCTL: RZCIEN Mask */ + +#define SPI_I2SCTL_LZCIEN_Pos (25) /*!< SPI_T::I2SCTL: LZCIEN Position */ +#define SPI_I2SCTL_LZCIEN_Msk (0x1ul << SPI_I2SCTL_LZCIEN_Pos) /*!< SPI_T::I2SCTL: LZCIEN Mask */ + +#define SPI_I2SCTL_FORMAT_Pos (28) /*!< SPI_T::I2SCTL: FORMAT Position */ +#define SPI_I2SCTL_FORMAT_Msk (0x3ul << SPI_I2SCTL_FORMAT_Pos) /*!< SPI_T::I2SCTL: FORMAT Mask */ + +#define SPI_I2SCTL_SLVERRIEN_Pos (31) /*!< SPI_T::I2SCTL: SLVERRIEN Position */ +#define SPI_I2SCTL_SLVERRIEN_Msk (0x1ul << SPI_I2SCTL_SLVERRIEN_Pos) /*!< SPI_T::I2SCTL: SLVERRIEN Mask */ + +#define SPI_I2SCLK_MCLKDIV_Pos (0) /*!< SPI_T::I2SCLK: MCLKDIV Position */ +#define SPI_I2SCLK_MCLKDIV_Msk (0x7ful << SPI_I2SCLK_MCLKDIV_Pos) /*!< SPI_T::I2SCLK: MCLKDIV Mask */ + +#define SPI_I2SCLK_BCLKDIV_Pos (8) /*!< SPI_T::I2SCLK: BCLKDIV Position */ +#define SPI_I2SCLK_BCLKDIV_Msk (0x3fful << SPI_I2SCLK_BCLKDIV_Pos) /*!< SPI_T::I2SCLK: BCLKDIV Mask */ + +#define SPI_I2SCLK_I2SMODE_Pos (24) /*!< SPI_T::I2SCLK: I2SMODE Position */ +#define SPI_I2SCLK_I2SMODE_Msk (0x1ul << SPI_I2SCLK_I2SMODE_Pos) /*!< SPI_T::I2SCLK: I2SMODE Mask */ + +#define SPI_I2SCLK_I2SSLAVE_Pos (25) /*!< SPI_T::I2SCLK: I2SSLAVE Position */ +#define SPI_I2SCLK_I2SSLAVE_Msk (0x1ul << SPI_I2SCLK_I2SSLAVE_Pos) /*!< SPI_T::I2SCLK: I2SSLAVE Mask */ + +#define SPI_I2SSTS_RIGHT_Pos (4) /*!< SPI_T::I2SSTS: RIGHT Position */ +#define SPI_I2SSTS_RIGHT_Msk (0x1ul << SPI_I2SSTS_RIGHT_Pos) /*!< SPI_T::I2SSTS: RIGHT Mask */ + +#define SPI_I2SSTS_RXEMPTY_Pos (8) /*!< SPI_T::I2SSTS: RXEMPTY Position */ +#define SPI_I2SSTS_RXEMPTY_Msk (0x1ul << SPI_I2SSTS_RXEMPTY_Pos) /*!< SPI_T::I2SSTS: RXEMPTY Mask */ + +#define SPI_I2SSTS_RXFULL_Pos (9) /*!< SPI_T::I2SSTS: RXFULL Position */ +#define SPI_I2SSTS_RXFULL_Msk (0x1ul << SPI_I2SSTS_RXFULL_Pos) /*!< SPI_T::I2SSTS: RXFULL Mask */ + +#define SPI_I2SSTS_RXTHIF_Pos (10) /*!< SPI_T::I2SSTS: RXTHIF Position */ +#define SPI_I2SSTS_RXTHIF_Msk (0x1ul << SPI_I2SSTS_RXTHIF_Pos) /*!< SPI_T::I2SSTS: RXTHIF Mask */ + +#define SPI_I2SSTS_RXOVIF_Pos (11) /*!< SPI_T::I2SSTS: RXOVIF Position */ +#define SPI_I2SSTS_RXOVIF_Msk (0x1ul << SPI_I2SSTS_RXOVIF_Pos) /*!< SPI_T::I2SSTS: RXOVIF Mask */ + +#define SPI_I2SSTS_RXTOIF_Pos (12) /*!< SPI_T::I2SSTS: RXTOIF Position */ +#define SPI_I2SSTS_RXTOIF_Msk (0x1ul << SPI_I2SSTS_RXTOIF_Pos) /*!< SPI_T::I2SSTS: RXTOIF Mask */ + +#define SPI_I2SSTS_I2SENSTS_Pos (15) /*!< SPI_T::I2SSTS: I2SENSTS Position */ +#define SPI_I2SSTS_I2SENSTS_Msk (0x1ul << SPI_I2SSTS_I2SENSTS_Pos) /*!< SPI_T::I2SSTS: I2SENSTS Mask */ + +#define SPI_I2SSTS_TXEMPTY_Pos (16) /*!< SPI_T::I2SSTS: TXEMPTY Position */ +#define SPI_I2SSTS_TXEMPTY_Msk (0x1ul << SPI_I2SSTS_TXEMPTY_Pos) /*!< SPI_T::I2SSTS: TXEMPTY Mask */ + +#define SPI_I2SSTS_TXFULL_Pos (17) /*!< SPI_T::I2SSTS: TXFULL Position */ +#define SPI_I2SSTS_TXFULL_Msk (0x1ul << SPI_I2SSTS_TXFULL_Pos) /*!< SPI_T::I2SSTS: TXFULL Mask */ + +#define SPI_I2SSTS_TXTHIF_Pos (18) /*!< SPI_T::I2SSTS: TXTHIF Position */ +#define SPI_I2SSTS_TXTHIF_Msk (0x1ul << SPI_I2SSTS_TXTHIF_Pos) /*!< SPI_T::I2SSTS: TXTHIF Mask */ + +#define SPI_I2SSTS_TXUFIF_Pos (19) /*!< SPI_T::I2SSTS: TXUFIF Position */ +#define SPI_I2SSTS_TXUFIF_Msk (0x1ul << SPI_I2SSTS_TXUFIF_Pos) /*!< SPI_T::I2SSTS: TXUFIF Mask */ + +#define SPI_I2SSTS_RZCIF_Pos (20) /*!< SPI_T::I2SSTS: RZCIF Position */ +#define SPI_I2SSTS_RZCIF_Msk (0x1ul << SPI_I2SSTS_RZCIF_Pos) /*!< SPI_T::I2SSTS: RZCIF Mask */ + +#define SPI_I2SSTS_LZCIF_Pos (21) /*!< SPI_T::I2SSTS: LZCIF Position */ +#define SPI_I2SSTS_LZCIF_Msk (0x1ul << SPI_I2SSTS_LZCIF_Pos) /*!< SPI_T::I2SSTS: LZCIF Mask */ + +#define SPI_I2SSTS_SLVERRIF_Pos (22) /*!< SPI_T::I2SSTS: SLVERRIF Position */ +#define SPI_I2SSTS_SLVERRIF_Msk (0x1ul << SPI_I2SSTS_SLVERRIF_Pos) /*!< SPI_T::I2SSTS: SLVERRIF Mask */ + +#define SPI_I2SSTS_TXRXRST_Pos (23) /*!< SPI_T::I2SSTS: TXRXRST Position */ +#define SPI_I2SSTS_TXRXRST_Msk (0x1ul << SPI_I2SSTS_TXRXRST_Pos) /*!< SPI_T::I2SSTS: TXRXRST Mask */ + +#define SPI_I2SSTS_RXCNT_Pos (24) /*!< SPI_T::I2SSTS: RXCNT Position */ +#define SPI_I2SSTS_RXCNT_Msk (0x7ul << SPI_I2SSTS_RXCNT_Pos) /*!< SPI_T::I2SSTS: RXCNT Mask */ + +#define SPI_I2SSTS_TXCNT_Pos (28) /*!< SPI_T::I2SSTS: TXCNT Position */ +#define SPI_I2SSTS_TXCNT_Msk (0x7ul << SPI_I2SSTS_TXCNT_Pos) /*!< SPI_T::I2SSTS: TXCNT Mask */ + +/**@}*/ /* SPI_CONST */ +/**@}*/ /* end of SPI register group */ +/**@}*/ /* end of REGISTER group */ + +#endif /* __SPI_REG_H__ */ diff --git a/Ubiquitous/XiZi/board/nuvoton-m2354/third_party_driver/include/Regs/sys_reg.h b/Ubiquitous/XiZi/board/nuvoton-m2354/third_party_driver/include/Regs/sys_reg.h new file mode 100644 index 0000000..4dfc39f --- /dev/null +++ b/Ubiquitous/XiZi/board/nuvoton-m2354/third_party_driver/include/Regs/sys_reg.h @@ -0,0 +1,2617 @@ +/**************************************************************************//** + * @file sys_reg.h + * @version V1.00 + * @brief SYS register definition header file + * + * @copyright SPDX-License-Identifier: Apache-2.0 + * @copyright Copyright (C) 2020 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ +#ifndef __SYS_REG_H__ +#define __SYS_REG_H__ + +/** @addtogroup REGISTER Control Register + + @{ + +*/ + +/*---------------------- System Manger Controller -------------------------*/ +/** + @addtogroup SYS System Manger Controller(SYS) + Memory Mapped Structure for SYS Controller + @{ +*/ + +typedef struct +{ + + + /** + * @var SYS_T::PDID + * Offset: 0x00 Part Device Identification Number Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |PDID |Part Device Identification Number (Read Only) + * | | |This register reflects device part number code. + * | | |Software can read this register to identify which device is used. + * @var SYS_T::RSTSTS + * Offset: 0x04 System Reset Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |PORF |POR Reset Flag + * | | |The POR reset flag is set by the "Reset Signal" from the Power-on Reset (POR) Controller or bit CHIPRST (SYS_IPRST0[0]) to indicate the previous reset source. + * | | |0 = No reset from POR or CHIPRST. + * | | |1 = Power-on Reset (POR) or CHIPRST had issued the reset signal to reset the system. + * | | |Note: Write 1 to clear this bit to 0. + * |[1] |PINRF |nRESET Pin Reset Flag + * | | |The nRESET pin reset flag is set by the "Reset Signal" from the nRESET Pin to indicate the previous reset source. + * | | |0 = No reset from nRESET pin. + * | | |1 = Pin nRESET had issued the reset signal to reset the system. + * | | |Note: Write 1 to clear this bit to 0. + * |[2] |WDTRF |WDT Reset Flag + * | | |The WDT reset flag is set by the "Reset Signal" from the Watchdog Timer or Window Watchdog Timer to indicate the previous reset source. + * | | |0 = No reset from watchdog timer or window watchdog timer. + * | | |1 = The watchdog timer or window watchdog timer had issued the reset signal to reset the system. + * | | |Note 1: Write 1 to clear this bit to 0. + * | | |Note 2: Watchdog Timer register RSTF(WDT_CTL[2]) bit is set if the system has been reset by WDT time-out reset. + * | | |Window Watchdog Timer register WWDTRF(WWDT_STATUS[1]) bit is set if the system has been reset by WWDT time-out reset. + * | | |Note 3: Extra Watchdog Timer register RSTF(EWDT_CTL[2]) bit is set if the system has been reset by EWDT time-out reset. + * | | |Extra Window Watchdog Timer register WWDTRF(EWWDT_STATUS[1]) bit is set if the system has been reset by EWWDT time-out reset. + * |[3] |LVRF |LVR Reset Flag + * | | |The LVR reset flag is set by the "Reset Signal" from the Low Voltage Reset Controller to indicate the previous reset source. + * | | |0 = No reset from LVR. + * | | |1 = LVR controller had issued the reset signal to reset the system. + * | | |Note: Write 1 to clear this bit to 0. + * |[4] |BODRF |BOD Reset Flag + * | | |The BOD reset flag is set by the "Reset Signal" from the Brown-out Detector to indicate the previous reset source. + * | | |0 = No reset from BOD. + * | | |1 = The BOD had issued the reset signal to reset the system. + * | | |Note: Write 1 to clear this bit to 0. + * |[5] |SYSRF |System Reset Flag + * | | |The system reset flag is set by the "Reset Signal" from the Cortex-M23 Core to indicate the previous reset source. + * | | |0 = No reset from Cortex-M23. + * | | |1 = The Cortex-M23 had issued the reset signal to reset the system by writing 1 to the bit SYSRESETREQ(AIRCR[2], Application Interrupt and Reset Control Register, address = 0xE000ED0C) in system control registers of Cortex-M23 core. + * | | |Note: Write 1 to clear this bit to 0. + * |[7] |CPURF |CPU Reset Flag + * | | |The CPU reset flag is set by hardware if software writes CPURST (SYS_IPRST0[1]) 1 to reset Cortex-M23 Core and Flash Memory Controller (FMC). + * | | |0 = No reset from CPU. + * | | |1 = The Cortex-M23 Core and FMC are reset by software setting CPURST to 1. + * | | |Note: Write 1 to clear this bit to 0. + * |[8] |CPULKRF |CPU Lockup Reset Flag + * | | |The CPULK reset flag is set by hardware if Cortex-M23 lockup happened. + * | | |0 = No reset from CPU lockup happened. + * | | |1 = The Cortex-M23 lockup happened and chip is reset. + * | | |Note1: Write 1 to clear this bit to 0. + * | | |Note2: When CPU lockup happened under ICE is connected, This flag will set to 1 but chip will not reset. + * @var SYS_T::IPRST0 + * Offset: 0x08 Peripheral Reset Control Register 0 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |CHIPRST |Chip One-shot Reset (Write Protect) + * | | |Setting this bit will reset the whole chip, including Processor core and all peripherals, and this bit will automatically return to 0 after the 2 clock cycles. + * | | |The CHIPRST is same as the POR reset, all the chip controllers is reset and the chip setting from flash are also reload. + * | | |0 = Chip normal operation. + * | | |1 = Chip one-shot reset. + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * |[1] |CPURST |Processor Core One-shot Reset (Write Protect) + * | | |Setting this bit will only reset the processor core and Flash Memory Controller(FMC), and this bit will automatically return to 0 after the 2 clock cycles. + * | | |0 = Processor core normal operation. + * | | |1 = Processor core one-shot reset. + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * |[2] |PDMA0RST |PDMA0 Controller Reset (Write Protect) + * | | |Setting this bit to 1 will generate a reset signal to the PDMA0 (always secure). + * | | |User needs to set this bit to 0 to release from reset state. + * | | |0 = PDMA0 controller normal operation. + * | | |1 = PDMA0 controller reset. + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * |[3] |EBIRST |EBI Controller Reset (Write Protect) + * | | |Set this bit to 1 will generate a reset signal to the EBI + * | | |User needs to set this bit to 0 to release from the reset state. + * | | |0 = EBI controller normal operation. + * | | |1 = EBI controller reset. + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * |[4] |USBHRST |USB Host Controller Reset (Write Protect) + * | | |Set this bit to 1 will generate a reset signal to the USB Host. + * | | |User needs to set this bit to 0 to release from the reset state. + * | | |0 = USB Host controller normal operation. + * | | |1 = USB Host controller reset. + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * |[6] |SDH0RST |SDHOST0 Controller Reset (Write Protect) + * | | |Setting this bit to 1 will generate a reset signal to the SDHOST0 controller + * | | |User needs to set this bit to 0 to release from the reset state. + * | | |0 = SDHOST0 controller normal operation. + * | | |1 = SDHOST0 controller reset. + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * |[7] |CRCRST |CRC Calculation Controller Reset (Write Protect) + * | | |Set this bit to 1 will generate a reset signal to the CRC calculation controller + * | | |User needs to set this bit to 0 to release from the reset state. + * | | |0 = CRC calculation controller normal operation. + * | | |1 = CRC calculation controller reset. + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * |[12] |CRPTRST |CRYPTO Controller Reset (Write Protect) + * | | |Setting this bit to 1 will generate a reset signal to the CRYPTO controller. + * | | |User needs to set this bit to 0 to release from the reset state. + * | | |0 = CRYPTO controller normal operation. + * | | |1 = CRYPTO controller reset. + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * |[13] |KSRST |Key Store Controller Reset (Write Protect) + * | | |Setting this bit to 1 will generate a reset signal to the CRYPTO controller. + * | | |User needs to set this bit to 0 to release from the reset state. + * | | |0 = Key Store controller normal operation. + * | | |1 = Key Store controller reset. + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * |[29] |PDMA1RST |PDMA1 Controller Reset (Write Protect) + * | | |Setting this bit to 1 will generate a reset signal to the PDMA1. + * | | |User needs to set this bit to 0 to release from reset state. + * | | |0 = PDMA1 controller normal operation. + * | | |1 = PDMA1 controller reset. + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * @var SYS_T::IPRST1 + * Offset: 0x0C Peripheral Reset Control Register 1 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[1] |GPIORST |GPIO Controller Reset + * | | |0 = GPIO controller normal operation. + * | | |1 = GPIO controller reset. + * |[2] |TMR0RST |Timer0 Controller Reset + * | | |0 = Timer0 controller normal operation. + * | | |1 = Timer0 controller reset. + * |[3] |TMR1RST |Timer1 Controller Reset + * | | |0 = Timer1 controller normal operation. + * | | |1 = Timer1 controller reset. + * |[4] |TMR2RST |Timer2 Controller Reset + * | | |0 = Timer2 controller normal operation. + * | | |1 = Timer2 controller reset. + * |[5] |TMR3RST |Timer3 Controller Reset + * | | |0 = Timer3 controller normal operation. + * | | |1 = Timer3 controller reset. + * |[7] |ACMP01RST |Analog Comparator 0/1 Controller Reset + * | | |0 = Analog Comparator 0/1 controller normal operation. + * | | |1 = Analog Comparator 0/1 controller reset. + * |[8] |I2C0RST |I2C0 Controller Reset + * | | |0 = I2C0 controller normal operation. + * | | |1 = I2C0 controller reset. + * |[9] |I2C1RST |I2C1 Controller Reset + * | | |0 = I2C1 controller normal operation. + * | | |1 = I2C1 controller reset. + * |[10] |I2C2RST |I2C2 Controller Reset + * | | |0 = I2C2 controller normal operation. + * | | |1 = I2C2 controller reset. + * |[12] |QSPI0RST |QSPI0 Controller Reset + * | | |0 = QSPI0 controller normal operation. + * | | |1 = QSPI0 controller reset. + * |[13] |SPI0RST |SPI0 Controller Reset + * | | |0 = SPI0 controller normal operation. + * | | |1 = SPI0 controller reset. + * |[14] |SPI1RST |SPI1 Controller Reset + * | | |0 = SPI1 controller normal operation. + * | | |1 = SPI1 controller reset. + * |[15] |SPI2RST |SPI2 Controller Reset + * | | |0 = SPI2 controller normal operation. + * | | |1 = SPI2 controller reset. + * |[16] |UART0RST |UART0 Controller Reset + * | | |0 = UART0 controller normal operation. + * | | |1 = UART0 controller reset. + * |[17] |UART1RST |UART1 Controller Reset + * | | |0 = UART1 controller normal operation. + * | | |1 = UART1 controller reset. + * |[18] |UART2RST |UART2 Controller Reset + * | | |0 = UART2 controller normal operation. + * | | |1 = UART2 controller reset. + * |[19] |UART3RST |UART3 Controller Reset + * | | |0 = UART3 controller normal operation. + * | | |1 = UART3 controller reset. + * |[20] |UART4RST |UART4 Controller Reset + * | | |0 = UART4 controller normal operation. + * | | |1 = UART4 controller reset. + * |[21] |UART5RST |UART5 Controller Reset + * | | |0 = UART5 controller normal operation. + * | | |1 = UART5 controller reset. + * |[24] |CAN0RST |CAN0 Controller Reset + * | | |0 = CAN0 controller normal operation. + * | | |1 = CAN0 controller reset. + * |[26] |OTGRST |OTG Controller Reset + * | | |0 = OTG controller normal operation. + * | | |1 = OTG controller reset. + * |[27] |USBDRST |USBD Controller Reset + * | | |0 = USBD controller normal operation. + * | | |1 = USBD controller reset. + * |[28] |EADCRST |EADC Controller Reset + * | | |0 = EADC controller normal operation. + * | | |1 = EADC controller reset. + * |[29] |I2S0RST |I2S0 Controller Reset + * | | |0 = I2S0 controller normal operation. + * | | |1 = I2S0 controller reset. + * |[30] |LCDRST |LCD Controller Reset + * | | |0 = LCD controller normal operation. + * | | |1 = LCD controller reset. + * |[31] |TRNGRST |TRNG Controller Reset + * | | |0 = TRNG controller normal operation. + * | | |1 = TRNG controller reset. + * @var SYS_T::IPRST2 + * Offset: 0x10 Peripheral Reset Control Register 2 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |SC0RST |SC0 Controller Reset + * | | |0 = SC0 controller normal operation. + * | | |1 = SC0 controller reset. + * |[1] |SC1RST |SC1 Controller Reset + * | | |0 = SC1 controller normal operation. + * | | |1 = SC1 controller reset. + * |[2] |SC2RST |SC2 Controller Reset + * | | |0 = SC2 controller normal operation. + * | | |1 = SC2 controller reset. + * |[6] |SPI3RST |SPI3 Controller Reset + * | | |0 = SPI3 controller normal operation. + * | | |1 = SPI3 controller reset. + * |[8] |USCI0RST |USCI0 Controller Reset + * | | |0 = USCI0 controller normal operation. + * | | |1 = USCI0 controller reset. + * |[9] |USCI1RST |USCI1 Controller Reset + * | | |0 = USCI1 controller normal operation. + * | | |1 = USCI1 controller reset. + * |[12] |DACRST |DAC Controller Reset + * | | |0 = DAC controller normal operation. + * | | |1 = DAC controller reset. + * |[16] |EPWM0RST |EPWM0 Controller Reset + * | | |0 = EPWM0 controller normal operation. + * | | |1 = EPWM0 controller reset. + * |[17] |EPWM1RST |EPWM1 Controller Reset + * | | |0 = EPWM1 controller normal operation. + * | | |1 = EPWM1 controller reset. + * |[18] |BPWM0RST |BPWM0 Controller Reset + * | | |0 = BPWM0 controller normal operation. + * | | |1 = BPWM0 controller reset. + * |[19] |BPWM1RST |BPWM1 Controller Reset + * | | |0 = BPWM1 controller normal operation. + * | | |1 = BPWM1 controller reset. + * |[20] |TMR4RST |Timer4 Controller Reset + * | | |0 = Timer4 controller normal operation. + * | | |1 = Timer4 controller reset. + * |[21] |TMR5RST |Timer5 Controller Reset + * | | |0 = Timer5 controller normal operation. + * | | |1 = Timer5 controller reset. + * |[22] |QEI0RST |QEI0 Controller Reset + * | | |0 = QEI0 controller normal operation. + * | | |1 = QEI0 controller reset. + * |[23] |QEI1RST |QEI1 Controller Reset + * | | |0 = QEI1 controller normal operation. + * | | |1 = QEI1 controller reset. + * |[26] |ECAP0RST |ECAP0 Controller Reset + * | | |0 = ECAP0 controller normal operation. + * | | |1 = ECAP0 controller reset. + * |[27] |ECAP1RST |ECAP1 Controller Reset + * | | |0 = ECAP1 controller normal operation. + * | | |1 = ECAP1 controller reset. + * @var SYS_T::BODCTL + * Offset: 0x18 Brown-out Detector Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |BODEN |Brown-out Detector Enable Bit (Write Protect) + * | | |The default value is set by flash controller user configuration register CBODEN (CONFIG0 [23]). + * | | |0 = Brown-out Detector function Disabled. + * | | |1 = Brown-out Detector function Enabled. + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * |[3] |BODRSTEN |Brown-out Reset Enable Bit (Write Protect) + * | | |The default value is set by flash controller user configuration register CBORST(CONFIG0[20]) bit . + * | | |0 = Brown-out INTERRUPT function Enabled. + * | | |1 = Brown-out RESET function Enabled. + * | | |Note1: + * | | |While the Brown-out Detector function is enabled (BODEN high) and BOD reset function is enabled (BODRSTEN high), BOD will assert a signal to reset chip when the detected voltage is lower than the threshold (BODOUT high). + * | | |While the BOD function is enabled (BODEN high) and BOD interrupt function is enabled (BODRSTEN low), BOD will assert an interrupt if AVDD high.than BODVL, BOD interrupt will keep till to the BODIF set to 0. + * | | |BOD interrupt can be blocked by disabling the NVIC BOD interrupt or disabling BOD function (set BODEN low). + * | | |Note2: This bit is write protected. Refer to the SYS_REGLCTL register. + * |[4] |BODIF |Brown-out Detector Interrupt Flag + * | | |0 = Brown-out Detector does not detect any voltage draft at VDD down through or up through the voltage of BODVL setting. + * | | |1 = When Brown-out Detector detects the VDD is dropped down through the voltage of BODVL setting or the VDD is raised up through the voltage of BODVL setting, this bit is set to 1 and the brown-out interrupt is requested if brown-out interrupt is enabled. + * | | |Note: Write 1 to clear this bit to 0. + * |[6] |BODOUT |Brown-out Detector Output Status + * | | |0 = Brown-out Detector output status is 0. + * | | |It means the detected voltage is higher than BODVL setting or BODEN is 0. + * | | |1 = Brown-out Detector output status is 1. + * | | |It means the detected voltage is lower than BODVL setting. + * | | |If the BODEN is 0, BOD function disabled , this bit always responds 0. + * |[7] |LVREN |Low Voltage Reset Enable Bit (Write Protect) + * | | |The LVR function resets the chip when the input power voltage is lower than LVR circuit setting. + * | | |LVR function is enabled by default. + * | | |0 = Low Voltage Reset function Disabled. + * | | |1 = Low Voltage Reset function Enabled. + * | | |Note1: After enabling the bit, the LVR function will be active with 200us delay for LVR output stable (default). + * | | |Note2: This bit is write protected. Refer to the SYS_REGLCTL register. + * |[10:8] |BODDGSEL |Brown-out Detector Output De-glitch Time Select (Write Protect) + * | | |000 = BOD output is sampled by LIRC clock. + * | | |001 = 4 system clock (HCLK). + * | | |010 = 8 system clock (HCLK). + * | | |011 = 16 system clock (HCLK). + * | | |100 = 32 system clock (HCLK). + * | | |101 = 64 system clock (HCLK). + * | | |110 = 128 system clock (HCLK). + * | | |111 = 256 system clock (HCLK). + * | | |Note: These bits are write protected. Refer to the SYS_REGLCTL register. + * |[14:12] |LVRDGSEL |LVR Output De-glitch Time Select (Write Protect) + * | | |000 = Without de-glitch function. + * | | |001 = 4 system clock (HCLK). + * | | |010 = 8 system clock (HCLK). + * | | |011 = 16 system clock (HCLK). + * | | |100 = 32 system clock (HCLK). + * | | |101 = 64 system clock (HCLK). + * | | |110 = 128 system clock (HCLK). + * | | |111 = 256 system clock (HCLK). + * | | |Note: These bits are write protected. Refer to the SYS_REGLCTL register. + * |[23] |STB |Circuit Stable Flag (Read Only) + * | | |This bit indicates LVR and BOD already stable, system cannot detect LVR and BOD event when this bit is not set. + * | | |0 = LVR and BOD is not stable. + * | | |1 = LVR and BOD already stable. + * |[18:16] |BODVL |Brown-out Detector Threshold Voltage Selection (Write Protect) + * | | |The default value is set by flash controller user configuration register CBOV (CONFIG0 [23:21]). + * | | |000 = Brown-out Detector threshold voltage is 1.6V. + * | | |001 = Brown-out Detector threshold voltage is 1.8V. + * | | |010 = Brown-out Detector threshold voltage is 2.0V. + * | | |011 = Brown-out Detector threshold voltage is 2.2V. + * | | |100 = Brown-out Detector threshold voltage is 2.4V. + * | | |101 = Brown-out Detector threshold voltage is 2.6V. + * | | |110 = Brown-out Detector threshold voltage is 2.8V. + * | | |111 = Brown-out Detector threshold voltage is 3.0V. + * | | |Note: These bits are write protected. Refer to the SYS_REGLCTL register. + * |[31] |WRBUSY |Write Busy Flag (Read Only) + * | | |If SYS_BODCTL is written, this bit is asserted automatically by hardware, and is de-asserted when write procedure is finished. + * | | |0 = SYS_BODCTL register is ready for write operation. + * | | |1 = SYS_BODCTL register is busy on the last write operation. Other write operations are ignored. + * @var SYS_T::IVSCTL + * Offset: 0x1C Internal Voltage Source Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |VTEMPEN |Temperature Sensor Enable Bit + * | | |This bit is used to enable/disable temperature sensor function. + * | | |0 = Temperature sensor function Disabled (default). + * | | |1 = Temperature sensor function Enabled. + * | | |Note: After this bit is set to 1, the value of temperature sensor output can be obtained through GPC.9. + * |[1] |VBATUGEN |VBAT Unity Gain Buffer Enable Bit + * | | |This bit is used to enable/disable VBAT unity gain buffer function. + * | | |0 = VBAT unity gain buffer function Disabled (default). + * | | |1 = VBAT unity gain buffer function Enabled. + * | | |Note: After this bit is set to 1, the value of VBAT unity gain buffer output voltage can be obtained from ADC conversion result. + * @var SYS_T::PORCTL0 + * Offset: 0x24 Power-on Reset Controller Register 0 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |PORMASK |Power-on Reset Mask Enable Bit (Write Protect) + * | | |When powered on, the POR circuit generates a reset signal to reset the whole chip function, but noise on the power may cause the POR active again. + * | | |User can mask internal POR signal to avoid unpredictable noise to cause chip reset by writing 0x5AA5 to this field. + * | | |The POR function will be active again when this field is set to another value or chip is reset by other reset source, including: + * | | |nRESET, Watchdog, LVR reset, BOD reset, ICE reset command and the software-chip reset function. + * | | |Note: These bits are write protected. Refer to the SYS_REGLCTL register. + * @var SYS_T::VREFCTL + * Offset: 0x28 VREF Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[4:0] |VREFCTL |VREF Control Bits (Write Protect) + * | | |00000 = VREF is from external pin. + * | | |00011 = VREF is internal 1.6V. + * | | |00111 = VREF is internal 2.0V. + * | | |01011 = VREF is internal 2.5V. + * | | |01111 = VREF is internal 3.0V. + * | | |Others = Reserved. + * | | |Note: These bits are write protected. Refer to the SYS_REGLCTL register. + * |[5] |IBIASSEL |VREF Bias Current Selection (Write Protect) + * | | |0 = Bias current from MEGBIAS. + * | | |1 = Bias current from internal. + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * |[7:6] |PRELOADSEL|Pre-load Timing Selection (Write Protect) + * | | |00 = pre-load time is 60us for 0.1uF Capacitor. + * | | |01 = pre-load time is 310us for 1uF Capacitor. + * | | |10 = pre-load time is 1270us for 4.7uF Capacitor. + * | | |11 = pre-load time is 2650us for 10uF Capacitor. + * | | |Note: These bits are write protected. Refer to the SYS_REGLCTL register. + * @var SYS_T::USBPHY + * Offset: 0x2C USB PHY Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[1:0] |USBROLE |USB Role Option (Write Protect) + * | | |These two bits are used to select the role of USB. + * | | |00 = Standard USB Device mode. + * | | |01 = Standard USB Host mode. + * | | |10 = ID dependent mode. + * | | |11 = On-The-Go device mode (default). + * | | |Note: These bits are write protected. Refer to the SYS_REGLCTL register. + * |[2] |SBO |Note: This bit must always be kept 1. If set to 0, the result is unpredictable. + * |[8] |OTGPHYEN |USB OTG PHY Enable + * | | |This bit is used to enable/disable OTG PHY function. + * | | |0 = OTG PHY function Disabled (default). + * | | |1 = OTG PHY function Enabled. + * @var SYS_T::GPA_MFPL + * Offset: 0x30 GPIOA Low Byte Multiple Function Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[3:0] |PA0MFP |PA.0 Multi-function Pin Selection + * |[7:4] |PA1MFP |PA.1 Multi-function Pin Selection + * |[11:8] |PA2MFP |PA.2 Multi-function Pin Selection + * |[15:12] |PA3MFP |PA.3 Multi-function Pin Selection + * |[19:16] |PA4MFP |PA.4 Multi-function Pin Selection + * |[23:20] |PA5MFP |PA.5 Multi-function Pin Selection + * |[27:24] |PA6MFP |PA.6 Multi-function Pin Selection + * |[31:28] |PA7MFP |PA.7 Multi-function Pin Selection + * @var SYS_T::GPA_MFPH + * Offset: 0x34 GPIOA High Byte Multiple Function Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[3:0] |PA8MFP |PA.8 Multi-function Pin Selection + * |[7:4] |PA9MFP |PA.9 Multi-function Pin Selection + * |[11:8] |PA10MFP |PA.10 Multi-function Pin Selection + * |[15:12] |PA11MFP |PA.11 Multi-function Pin Selection + * |[19:16] |PA12MFP |PA.12 Multi-function Pin Selection + * |[23:20] |PA13MFP |PA.13 Multi-function Pin Selection + * |[27:24] |PA14MFP |PA.14 Multi-function Pin Selection + * |[31:28] |PA15MFP |PA.15 Multi-function Pin Selection + * @var SYS_T::GPB_MFPL + * Offset: 0x38 GPIOB Low Byte Multiple Function Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[3:0] |PB0MFP |PB.0 Multi-function Pin Selection + * |[7:4] |PB1MFP |PB.1 Multi-function Pin Selection + * |[11:8] |PB2MFP |PB.2 Multi-function Pin Selection + * |[15:12] |PB3MFP |PB.3 Multi-function Pin Selection + * |[19:16] |PB4MFP |PB.4 Multi-function Pin Selection + * |[23:20] |PB5MFP |PB.5 Multi-function Pin Selection + * |[27:24] |PB6MFP |PB.6 Multi-function Pin Selection + * |[31:28] |PB7MFP |PB.7 Multi-function Pin Selection + * @var SYS_T::GPB_MFPH + * Offset: 0x3C GPIOB High Byte Multiple Function Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[3:0] |PB8MFP |PB.8 Multi-function Pin Selection + * |[7:4] |PB9MFP |PB.9 Multi-function Pin Selection + * |[11:8] |PB10MFP |PB.10 Multi-function Pin Selection + * |[15:12] |PB11MFP |PB.11 Multi-function Pin Selection + * |[19:16] |PB12MFP |PB.12 Multi-function Pin Selection + * |[23:20] |PB13MFP |PB.13 Multi-function Pin Selection + * |[27:24] |PB14MFP |PB.14 Multi-function Pin Selection + * |[31:28] |PB15MFP |PB.15 Multi-function Pin Selection + * @var SYS_T::GPC_MFPL + * Offset: 0x40 GPIOC Low Byte Multiple Function Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[3:0] |PC0MFP |PC.0 Multi-function Pin Selection + * |[7:4] |PC1MFP |PC.1 Multi-function Pin Selection + * |[11:8] |PC2MFP |PC.2 Multi-function Pin Selection + * |[15:12] |PC3MFP |PC.3 Multi-function Pin Selection + * |[19:16] |PC4MFP |PC.4 Multi-function Pin Selection + * |[23:20] |PC5MFP |PC.5 Multi-function Pin Selection + * |[27:24] |PC6MFP |PC.6 Multi-function Pin Selection + * |[31:28] |PC7MFP |PC.7 Multi-function Pin Selection + * @var SYS_T::GPC_MFPH + * Offset: 0x44 GPIOC High Byte Multiple Function Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[3:0] |PC8MFP |PC.8 Multi-function Pin Selection + * |[7:4] |PC9MFP |PC.9 Multi-function Pin Selection + * |[11:8] |PC10MFP |PC.10 Multi-function Pin Selection + * |[15:12] |PC11MFP |PC.11 Multi-function Pin Selection + * |[19:16] |PC12MFP |PC.12 Multi-function Pin Selection + * |[23:20] |PC13MFP |PC.13 Multi-function Pin Selection + * @var SYS_T::GPD_MFPL + * Offset: 0x48 GPIOD Low Byte Multiple Function Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[3:0] |PD0MFP |PD.0 Multi-function Pin Selection + * |[7:4] |PD1MFP |PD.1 Multi-function Pin Selection + * |[11:8] |PD2MFP |PD.2 Multi-function Pin Selection + * |[15:12] |PD3MFP |PD.3 Multi-function Pin Selection + * |[19:16] |PD4MFP |PD.4 Multi-function Pin Selection + * |[23:20] |PD5MFP |PD.5 Multi-function Pin Selection + * |[27:24] |PD6MFP |PD.6 Multi-function Pin Selection + * |[31:28] |PD7MFP |PD.7 Multi-function Pin Selection + * @var SYS_T::GPD_MFPH + * Offset: 0x4C GPIOD High Byte Multiple Function Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[3:0] |PD8MFP |PD.8 Multi-function Pin Selection + * |[7:4] |PD9MFP |PD.9 Multi-function Pin Selection + * |[11:8] |PD10MFP |PD.10 Multi-function Pin Selection + * |[15:12] |PD11MFP |PD.11 Multi-function Pin Selection + * |[19:16] |PD12MFP |PD.12 Multi-function Pin Selection + * |[27:24] |PD14MFP |PD.14 Multi-function Pin Selection + * @var SYS_T::GPE_MFPL + * Offset: 0x50 GPIOE Low Byte Multiple Function Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[3:0] |PE0MFP |PE.0 Multi-function Pin Selection + * |[7:4] |PE1MFP |PE.1 Multi-function Pin Selection + * |[11:8] |PE2MFP |PE.2 Multi-function Pin Selection + * |[15:12] |PE3MFP |PE.3 Multi-function Pin Selection + * |[19:16] |PE4MFP |PE.4 Multi-function Pin Selection + * |[23:20] |PE5MFP |PE.5 Multi-function Pin Selection + * |[27:24] |PE6MFP |PE.6 Multi-function Pin Selection + * |[31:28] |PE7MFP |PE.7 Multi-function Pin Selection + * @var SYS_T::GPE_MFPH + * Offset: 0x54 GPIOE High Byte Multiple Function Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[3:0] |PE8MFP |PE.8 Multi-function Pin Selection + * |[7:4] |PE9MFP |PE.9 Multi-function Pin Selection + * |[11:8] |PE10MFP |PE.10 Multi-function Pin Selection + * |[15:12] |PE11MFP |PE.11 Multi-function Pin Selection + * |[19:16] |PE12MFP |PE.12 Multi-function Pin Selection + * |[23:20] |PE13MFP |PE.13 Multi-function Pin Selection + * |[27:24] |PE14MFP |PE.14 Multi-function Pin Selection + * |[31:28] |PE15MFP |PE.15 Multi-function Pin Selection + * @var SYS_T::GPF_MFPL + * Offset: 0x58 GPIOF Low Byte Multiple Function Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[3:0] |PF0MFP |PF.0 Multi-function Pin Selection + * |[7:4] |PF1MFP |PF.1 Multi-function Pin Selection + * |[11:8] |PF2MFP |PF.2 Multi-function Pin Selection + * |[15:12] |PF3MFP |PF.3 Multi-function Pin Selection + * |[19:16] |PF4MFP |PF.4 Multi-function Pin Selection + * |[23:20] |PF5MFP |PF.5 Multi-function Pin Selection + * |[27:24] |PF6MFP |PF.6 Multi-function Pin Selection + * |[31:28] |PF7MFP |PF.7 Multi-function Pin Selection + * @var SYS_T::GPF_MFPH + * Offset: 0x5C GPIOF High Byte Multiple Function Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[3:0] |PF8MFP |PF.8 Multi-function Pin Selection + * |[7:4] |PF9MFP |PF.9 Multi-function Pin Selection + * |[11:8] |PF10MFP |PF.10 Multi-function Pin Selection + * |[15:12] |PF11MFP |PF.11 Multi-function Pin Selection + * @var SYS_T::GPG_MFPL + * Offset: 0x60 GPIOG Low Byte Multiple Function Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[11:8] |PG2MFP |PG.2 Multi-function Pin Selection + * |[15:12] |PG3MFP |PG.3 Multi-function Pin Selection + * |[19:16] |PG4MFP |PG.4 Multi-function Pin Selection + * @var SYS_T::GPG_MFPH + * Offset: 0x64 GPIOG High Byte Multiple Function Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[7:4] |PG9MFP |PG.9 Multi-function Pin Selection + * |[11:8] |PG10MFP |PG.10 Multi-function Pin Selection + * |[15:12] |PG11MFP |PG.11 Multi-function Pin Selection + * |[19:16] |PG12MFP |PG.12 Multi-function Pin Selection + * |[23:20] |PG13MFP |PG.13 Multi-function Pin Selection + * |[27:24] |PG14MFP |PG.14 Multi-function Pin Selection + * |[31:28] |PG15MFP |PG.15 Multi-function Pin Selection + * @var SYS_T::GPH_MFPL + * Offset: 0x68 GPIOH Low Byte Multiple Function Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[19:16] |PH4MFP |PH.4 Multi-function Pin Selection + * |[23:20] |PH5MFP |PH.5 Multi-function Pin Selection + * |[27:24] |PH6MFP |PH.6 Multi-function Pin Selection + * |[31:28] |PH7MFP |PH.7 Multi-function Pin Selection + * @var SYS_T::GPH_MFPH + * Offset: 0x6C GPIOH High Byte Multiple Function Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[3:0] |PH8MFP |PH.8 Multi-function Pin Selection + * |[7:4] |PH9MFP |PH.9 Multi-function Pin Selection + * |[11:8] |PH10MFP |PH.10 Multi-function Pin Selection + * |[15:12] |PH11MFP |PH.11 Multi-function Pin Selection + * @var SYS_T::VTORSET + * Offset: 0xA0 VTOR Setting Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |VTORSET |VTOR Setting After SPD Wakeup (Write Protect) + * | | |This is the register to set the address of vector table after chip is waked up from SPD Power-down mode. + * | | |The value will be loaded to Vector Table Offset Register, which is at the address 0xE000ED08, when chip wake up from SPD mode. + * | | |Note: These bits are write protected. Refer to the SYS_REGLCTL register. + * @var SYS_T::SRAMICTL + * Offset: 0xC0 System SRAM Parity Error Interrupt Enable Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |PERRIEN |SRAM Parity Check Error Interrupt Enable Bit + * | | |0 = SRAM parity check error interrupt Disabled. + * | | |1 = SRAM parity check error interrupt Enabled. + * @var SYS_T::SRAMSTS + * Offset: 0xC4 System SRAM Parity Check Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |PERRIF |SRAM Parity Check Error Flag + * | | |This bit indicates the System SRAM parity error occurred. Write 1 to clear this to 0. + * | | |0 = No System SRAM parity error. + * | | |1 = System SRAM parity error occur. + * @var SYS_T::SRAMEADR + * Offset: 0xC8 System SRAM Parity Check Error Address Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |ERRADDR |System SRAM Parity Error Address + * | | |This register shows system SRAM parity error byte address. + * @var SYS_T::SRAMPC0 + * Offset: 0xDC SRAM Power Mode Control Register 0 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[1:0] |SRAM0PM0 |Bank0 SRAM Power Mode Select 0 (Write Protect) + * | | |This field can control SRAM bank0 selection 0 (4k) power mode for range 0x2000_0000 - 0x2000_0FFF. + * | | |00 = Normal mode. + * | | |01 = Retention mode. + * | | |10 = Power shut down mode. + * | | |11 = Reserved (Write Ignore). + * | | |Note 1: These bits are write protected. Refer to the SYS_REGLCTL register. + * | | |Note 2: Write ignore when PCBUSY is 1. + * |[3:2] |SRAM0PM1 |Bank0 SRAM Power Mode Select 1 (Write Protect) + * | | |This field can control SRAM bank0 selection 1 power mode for range 0x2000_1000 - 0x2000_1FFF. + * | | |00 = Normal mode. + * | | |01 = Retention mode. + * | | |10 = Power shut down mode. + * | | |11 = Reserved (Write Ignore). + * | | |Note 1: These bits are write protected. Refer to the SYS_REGLCTL register. + * | | |Note 2: Write ignore when PCBUSY is 1. + * |[5:4] |SRAM0PM2 |Bank0 SRAM Power Mode Select 2 (Write Protect) + * | | |This field can control SRAM bank0 selection 2 (8k) power mode for range 0x2000_2000 - 0x2000_3FFF. + * | | |00 = Normal mode. + * | | |01 = Retention mode. + * | | |10 = Power shut down mode. + * | | |11 = Reserved (Write Ignore). + * | | |Note 1: These bits are write protected. Refer to the SYS_REGLCTL register. + * | | |Note 2: Write ignore when PCBUSY is 1. + * |[7:6] |SRAM0PM3 |Bank0 SRAM Power Mode Select 3 (Write Protect) + * | | |This field can control SRAM bank0 selection 3 (8k) power mode for range 0x2000_4000 - 0x2000_5FFF. + * | | |00 = Normal mode. + * | | |01 = Retention mode. + * | | |10 = Power shut down mode. + * | | |11 = Reserved (Write Ignore). + * | | |Note 1: These bits are write protected. Refer to the SYS_REGLCTL register. + * | | |Note 2: Write ignore when PCBUSY is 1. + * |[9:8] |SRAM0PM4 |Bank0 SRAM Power Mode Select 4 (Write Protect) + * | | |This field can control SRAM0 bank0 selection 4 (8k) power mode for range 0x2000_6000 - 0x2000_7FFF. + * | | |00 = Normal mode. + * | | |01 = Retention mode. + * | | |10 = Power shut down mode. + * | | |11 = Reserved (Write Ignore). + * | | |Note 1: These bits are write protected. Refer to the SYS_REGLCTL register. + * | | |Note 2: Write ignore when PCBUSY is 1. + * |[11:10] |SRAM1PM0 |Bank1 SRAM Power Mode Select 0 (Write Protect) + * | | |This field can control SRAM bank1 selection 0 (16k) power mode for range 0x2000_8000 - 0x2000_BFFF. + * | | |00 = Normal mode. + * | | |01 = Retention mode. + * | | |10 = Power shut down mode. + * | | |11 = Reserved (Write Ignore). + * | | |Note 1: These bits are write protected. Refer to the SYS_REGLCTL register. + * | | |Note 2: Write ignore when PCBUSY is 1. + * |[13:12] |SRAM1PM1 |Bank1 SRAM Power Mode Select 1 (Write Protect) + * | | |This field can control SRAM bank1 selection 1 (16k) power mode for range 0x2000_C000 - 0x2000_FFFF. + * | | |00 = Normal mode. + * | | |01 = Retention mode. + * | | |10 = Power shut down mode. + * | | |11 = Reserved (Write Ignore). + * | | |Note 1: These bits are write protected. Refer to the SYS_REGLCTL register. + * | | |Note 2: Write ignore when PCBUSY is 1. + * |[15:14] |SRAM1PM2 |Bank1 SRAM Power Mode Select 2 (Write Protect) + * | | |This field can control SRAM bank1 selection 2 (16k) power mode for range 0x2001_0000 - 0x2001_3FFF. + * | | |00 = Normal mode. + * | | |01 = Retention mode. + * | | |10 = Power shut down mode. + * | | |11 = Reserved (Write Ignore). + * | | |Note 1: These bits are write protected. Refer to the SYS_REGLCTL register. + * | | |Note 2: Write ignore when PCBUSY is 1. + * |[17:16] |SRAM1PM3 |Bank1 SRAM Power Mode Select 3 (Write Protect) + * | | |This field can control SRAM bank1 selection 3 (16k) power mode for range 0x2001_4000 - 0x2001_7FFF. + * | | |00 = Normal mode. + * | | |01 = Retention mode. + * | | |10 = Power shut down mode. + * | | |11 = Reserved (Write Ignore). + * | | |Note 1: These bits are write protected. Refer to the SYS_REGLCTL register. + * | | |Note 2: Write ignore when PCBUSY is 1. + * |[19:18] |SRAM1PM4 |Bank1 SRAM Power Mode Select 4 (Write Protect) + * | | |This field can control SRAM bank1 selection 4 (16k) power mode for range 0x2001_8000 - 0x2001_BFFF. + * | | |00 = Normal mode. + * | | |01 = Retention mode. + * | | |10 = Power shut down mode. + * | | |11 = Reserved (Write Ignore). + * | | |Note 1: These bits are write protected. Refer to the SYS_REGLCTL register. + * | | |Note 2: Write ignore when PCBUSY is 1. + * |[21:20] |SRAM1PM5 |Bank1 SRAM Power Mode Select 5 (Write Protect) + * | | |This field can control SRAM bank1 selection 5 (16k) power mode for range 0x2001_C000 - 0x2001_FFFF. + * | | |00 = Normal mode. + * | | |01 = Retention mode. + * | | |10 = Power shut down mode. + * | | |11 = Reserved (Write Ignore). + * | | |Note 1: These bits are write protected. Refer to the SYS_REGLCTL register. + * | | |Note 2: Write ignore when PCBUSY is 1. + * |[23:22] |SRAM1PM6 |Bank1 SRAM Power Mode Select 6 (Write Protect) + * | | |This field can control SRAM bank1 selection 6 (16k) power mode for range 0x2002_0000 - 0x2002_3FFF. + * | | |00 = Normal mode. + * | | |01 = Retention mode. + * | | |10 = Power shut down mode. + * | | |11 = Reserved (Write Ignore). + * | | |Note 1: These bits are write protected. Refer to the SYS_REGLCTL register. + * | | |Note 2: Write ignore when PCBUSY is 1. + * |[25:24] |SRAM1PM7 |Bank1 SRAM Power Mode Select 7 (Write Protect) + * | | |This field can control SRAM bank1 selection 7 (16k) power mode for range 0x2002_4000 - 0x2002_7FFF. + * | | |00 = Normal mode. + * | | |01 = Retention mode. + * | | |10 = Power shut down mode. + * | | |11 = Reserved (Write Ignore). + * | | |Note 1: These bits are write protected. Refer to the SYS_REGLCTL register. + * | | |Note 2: Write ignore when PCBUSY is 1. + * |[27:26] |SRAM2PM0 |Bank2 SRAM Power Mode Select 0 (Write Protect) + * | | |This field can control SRAM bank2 selection 0 (16k) power mode for range 0x2002_8000 - 0x2002_BFFF. + * | | |00 = Normal mode. + * | | |01 = Retention mode. + * | | |10 = Power shut down mode. + * | | |11 = Reserved (Write Ignore). + * | | |Note 1: These bits are write protected. Refer to the SYS_REGLCTL register. + * | | |Note 2: Write ignore when PCBUSY is 1. + * |[29:28] |SRAM2PM1 |Bank2 SRAM Power Mode Select 1 (Write Protect) + * | | |This field can control SRAM bank2 selection 1 (16k) power mode for range 0x2002_C000 - 0x2002_FFFF. + * | | |00 = Normal mode. + * | | |01 = Retention mode. + * | | |10 = Power shut down mode. + * | | |11 = Reserved (Write Ignore). + * | | |Note 1: These bits are write protected. Refer to the SYS_REGLCTL register. + * | | |Note 2: Write ignore when PCBUSY is 1. + * |[31] |PCBUSY |Power Changing Busy Flag (Read Only) + * | | |This bit indicate SRAM power changing. + * | | |0 = SRAM power change finish. + * | | |1 = SRAM power changing. + * @var SYS_T::SRAMPC1 + * Offset: 0xE0 SRAM Power Mode Control Register 1 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[1:0] |SRAM2PM2 |Bank2 SRAM Power Mode Select 2 (Write Protect) + * | | |This field can control SRAM bank2 selection 2 (16k) power mode for range 0x2003_0000 - 0x2003_3FFF. + * | | |00 = Normal mode. + * | | |01 = Retention mode. + * | | |10 = Power shut down mode. + * | | |11 = Reserved (Write Ignore). + * | | |Note 1: These bits are write protected. Refer to the SYS_REGLCTL register. + * | | |Note 2: Write ignore when PCBUSY is 1. + * |[3:2] |SRAM2PM3 |Bank2 SRAM Power Mode Select 3 (Write Protect) + * | | |This field can control bank2 sram3 (16k) power mode for range 0x2003_4000 - 0x2003_7FFF. + * | | |00 = Normal mode. + * | | |01 = Retention mode. + * | | |10 = Power shut down mode. + * | | |11 = Reserved (Write Ignore). + * | | |Note 1: These bits are write protected. Refer to the SYS_REGLCTL register. + * | | |Note 2: Write ignore when PCBUSY is 1. + * |[5:4] |SRAM2PM4 |Bank2 SRAM Power Mode Select 4 (Write Protect) + * | | |This field can control SRAM bank2 selection 4 (16k) power mode for range 0x2003_8000 - 0x2003_BFFF. + * | | |00 = Normal mode. + * | | |01 = Retention mode. + * | | |10 = Power shut down mode. + * | | |11 = Reserved (Write Ignore). + * | | |Note 1: These bits are write protected. Refer to the SYS_REGLCTL register. + * | | |Note 2: Write ignore when PCBUSY is 1. + * |[7:6] |SRAM2PM5 |Bank2 SRAM Power Mode Select 5 (Write Protect) + * | | |This field can control SRAM bank2 selection 5 (16k) power mode for range 0x2003_C000 - 0x2003_FFFF. + * | | |00 = Normal mode. + * | | |01 = Retention mode. + * | | |10 = Power shut down mode. + * | | |11 = Reserved (Write Ignore). + * | | |Note 1: These bits are write protected. Refer to the SYS_REGLCTL register. + * | | |Note 2: Write ignore when PCBUSY is 1. + * |[17:16] |CAN |CAN SRAM Power Mode Select (Write Protect) + * | | |This field can control CAN sram power mode. + * | | |00 = Normal mode. + * | | |01 = Retention mode. + * | | |10 = Power shut down mode. + * | | |11 = Reserved. + * | | |Note 1: These bits are write protected. Refer to the SYS_REGLCTL register. + * | | |Note 2: Write ignore when PCBUSY is 1. + * |[19:18] |USBD |USB Device SRAM Power Mode Select (Write Protect) + * | | |This field can control USB device sram power mode. + * | | |00 = Normal mode. + * | | |01 = Retention mode. + * | | |10 = Power shut down mode. + * | | |11 = Reserved (Write Ignore). + * | | |Note 1: These bits are write protected. Refer to the SYS_REGLCTL register. + * | | |Note 2: Write ignore when PCBUSY is 1. + * |[21:20] |PDMA0 |PDMA SRAM Power Mode Select (Write Protect) + * | | |This field can control PDMA0 (always secure) sram power mode. + * | | |00 = Normal mode. + * | | |01 = Retention mode. + * | | |10 = Power shut down mode. + * | | |11 = Reserved (Write Ignore). + * | | |Note 1: These bits are write protected. Refer to the SYS_REGLCTL register. + * | | |Note 2: Write ignore when PCBUSY is 1. + * |[23:22] |PDMA1 |PDMA SRAM Power Mode Select (Write Protect) + * | | |This field can control PDMA1 sram power mode. + * | | |00 = Normal mode. + * | | |01 = Retention mode. + * | | |10 = Power shut down mode. + * | | |11 = Reserved (Write Ignore). + * | | |Note 1: These bits are write protected. Refer to the SYS_REGLCTL register. + * | | |Note 2: Write ignore when PCBUSY is 1. + * |[25:24] |FMCCACHE |FMC Cache SRAM Power Mode Select (Write Protect) + * | | |This field can control FMC cache sram power mode. + * | | |00 = Normal mode. + * | | |01 = Retention mode. + * | | |10 = Power shut down mode. + * | | |11 = Reserved (Write Ignore). + * | | |Note 1: These bits are write protected. Refer to the SYS_REGLCTL register. + * | | |Note 2: Write ignore when PCBUSY is 1. + * |[27:26] |RSA |RSA SRAM Power Mode Select (Write Protect) + * | | |This field can control RSA sram power mode. + * | | |00 = Normal mode. + * | | |01 = Retention mode. + * | | |10 = Power shut down mode. + * | | |11 = Reserved (Write Ignore). + * | | |Note 1: These bits are write protected. Refer to the SYS_REGLCTL register. + * | | |Note 2: Write ignore when PCBUSY is 1. + * | | |Note 3: If CRPTPWREN of SYS_PSWCTL is set to 1, RSA SRAM is auto set to normal mode by hardware. + * |[29:28] |KS |Key Store SRAM Power Mode Select (Write Protect) + * | | |This field can control Key Store sram power mode. + * | | |00 = Normal mode. + * | | |01 = Retention mode. + * | | |10 = Power shut down mode. + * | | |11 = Reserved (Write Ignore). + * | | |Note 1: These bits are write protected. Refer to the SYS_REGLCTL register. + * | | |Note 2: Write ignore when PCBUSY is 1. + * |[31] |PCBUSY |Power Changing Busy Flag (Read Only) + * | | |This bit indicate SRAM power changing. + * | | |0 = SRAM power change finish. + * | | |1 = SRAM power changing. + * @var SYS_T::TCTL48M + * Offset: 0xE4 HIRC 48M Trim Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[1:0] |FREQSEL |Trim Frequency Selection + * | | |This field indicates the target frequency of 48 MHz internal high speed RC oscillator (HIRC48) auto trim. + * | | |During auto trim operation, if clock error detected with CESTOPEN is set to 1 or trim retry limitation count reached, this field will be cleared to 00 automatically. + * | | |00 = Disable HIRC auto trim function. + * | | |01 = Enable HIRC auto trim function and trim HIRC to 48 MHz. + * | | |10 = Reserved. + * | | |11 = Reserved. + * |[5:4] |LOOPSEL |Trim Calculation Loop Selection + * | | |This field defines that trim value calculation is based on how many reference clocks. + * | | |00 = Trim value calculation is based on average difference in 4 clocks of reference clock. + * | | |01 = Trim value calculation is based on average difference in 8 clocks of reference clock. + * | | |10 = Trim value calculation is based on average difference in 16 clocks of reference clock. + * | | |11 = Trim value calculation is based on average difference in 32 clocks of reference clock. + * | | |Note: For example, if LOOPSEL is set as 00, auto trim circuit will calculate trim value based on the average frequency difference in 4 clocks of reference clock. + * |[7:6] |RETRYCNT |Trim Value Update Limitation Count + * | | |This field defines that how many times the auto trim circuit will try to update the HIRC trim value before the frequency of HIRC locked. + * | | |Once the HIRC locked, the internal trim value update counter will be reset. + * | | |If the trim value update counter reached this limitation value and frequency of HIRC still doesn't lock, the auto trim operation will be disabled and FREQSEL will be cleared to 00. + * | | |00 = Trim retry count limitation is 64 loops. + * | | |01 = Trim retry count limitation is 128 loops. + * | | |10 = Trim retry count limitation is 256 loops. + * | | |11 = Trim retry count limitation is 512 loops. + * |[9] |BOUNDEN |Boundary Enable Bit + * | | |0 = Boundary function is disable. + * | | |1 = Boundary function is enable. + * |[8] |CESTOPEN |Clock Error Stop Enable Bit + * | | |0 = The trim operation is keep going if clock is inaccuracy. + * | | |1 = The trim operation is stopped if clock is inaccuracy. + * |[10] |REFCKSEL |Reference Clock Selection + * | | |0 = HIRC trim 48M reference clock is from external 32.768 kHz crystal oscillator. + * | | |1 = HIRC trim 48M reference clock is from internal USB synchronous mode. + * |[20:16] |BOUNDARY |Boundary Selection + * | | |Fill the boundary range from 0x1 to 0x31, 0x0 is reserved. + * | | |Note: This field is effective only when the BOUNDEN(SYS_TCTL48M [9]) is enable. + * @var SYS_T::TIEN48M + * Offset: 0xE8 HIRC 48M Trim Interrupt Enable Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[1] |TFAILIEN |Trim Failure Interrupt Enable Bit + * | | |This bit controls if an interrupt will be triggered while HIRC trim value update limitation count reached and HIRC frequency still not locked on target frequency set by FREQSEL(SYS_TCTL48M[1:0]). + * | | |If this bit is high and TFAILIF(SYS_TISTS48M[1]) is set during auto trim operation, an interrupt will be triggered to notify that HIRC trim value update limitation count was reached. + * | | |0 = Disable TFAILIF(SYS_TISTS48M[1]) status to trigger an interrupt to CPU. + * | | |1 = Enable TFAILIF(SYS_TISTS48MM[1]) status to trigger an interrupt to CPU. + * |[2] |CLKEIEN |Clock Error Interrupt Enable Bit + * | | |This bit controls if CPU would get an interrupt while clock is inaccuracy during auto trim operation. + * | | |If this bit is set to1, and CLKERRIF(SYS_TISTS48M[2]) is set during auto trim operation, an interrupt will be triggered to notify the clock frequency is inaccuracy. + * | | |0 = Disable CLKERRIF(SYS_TISTS48M[2]) status to trigger an interrupt to CPU. + * | | |1 = Enable CLKERRIF(SYS_TISTS48M[2]) status to trigger an interrupt to CPU. + * @var SYS_T::TISTS48M + * Offset: 0xEC HIRC 48M Trim Interrupt Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |FREQLOCK |HIRC Frequency Lock Status + * | | |This bit indicates the HIRC frequency is locked. + * | | |This is a status bit and doesn't trigger any interrupt. + * | | |Write 1 to clear this to 0. + * | | |This bit will be set automatically, if the frequency is lock and the RC_TRIM is enabled. + * | | |0 = The internal high-speed oscillator frequency doesn't lock at 48 MHz yet. + * | | |1 = The internal high-speed oscillator frequency locked at 48 MHz. + * |[1] |TFAILIF |Trim Failure Interrupt Status + * | | |This bit indicates that HIRC trim value update limitation count reached and the HIRC clock frequency still doesn't be locked. + * | | |Once this bit is set, the auto trim operation stopped and FREQSEL(SYS_TCTL48M[1:0]) will be cleared to 00 by hardware automatically. + * | | |If this bit is set and TFAILIEN(SYS_TIEN48M[1]) is high, an interrupt will be triggered to notify that HIRC trim value update limitation count was reached. + * | | |Write 1 to clear this to 0. + * | | |0 = Trim value update limitation count does not reach. + * | | |1 = Trim value update limitation count reached and HIRC frequency still not locked. + * |[2] |CLKERRIF |Clock Error Interrupt Status + * | | |When the frequency of 32.768 kHz external low speed crystal oscillator (LXT) or 48MHz internal high speed RC oscillator (HIRC48) is shift larger to unreasonable value, this bit will be set and to be an indicate that clock frequency is inaccuracy + * | | |Once this bit is set to 1, the auto trim operation stopped and FREQSEL(SYS_TICTL48M[1:0]) will be cleared to 00 by hardware automatically if CESTOPEN(SYS_TCTL48M[8]) is set to 1. + * | | |If this bit is set and CLKEIEN(SYS_TIEN48M[2]) is high, an interrupt will be triggered to notify the clock frequency is inaccuracy. + * | | |Write 1 to clear this to 0. + * | | |0 = Clock frequency is accuracy. + * | | |1 = Clock frequency is inaccuracy. + * |[3] |OVBDIF |Over Boundary Status + * | | |When the over boundary function is set, if there occurs the over boundary condition, this flag will be set. + * | | |0 = Over boundary condition did not occur. + * | | |1 = Over boundary condition occurred. + * | | |Note: Write 1 to clear this flag. + * @var SYS_T::TCTL12M + * Offset: 0xF0 HIRC 12M Trim Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[1:0] |FREQSEL |Trim Frequency Selection + * | | |This field indicates the target frequency of 12 MHz internal high speed RC oscillator (HIRC) auto trim. + * | | |During auto trim operation, if clock error detected with CESTOPEN is set to 1 or trim retry limitation count reached, this field will be cleared to 00 automatically. + * | | |00 = Disable HIRC auto trim function. + * | | |01 = Enable HIRC auto trim function and trim HIRC to 12 MHz. + * | | |10 = Reserved. + * | | |11 = Reserved. + * |[5:4] |LOOPSEL |Trim Calculation Loop Selection + * | | |This field defines that trim value calculation is based on how many reference clocks. + * | | |00 = Trim value calculation is based on average difference in 4 clocks of reference clock. + * | | |01 = Trim value calculation is based on average difference in 8 clocks of reference clock. + * | | |10 = Trim value calculation is based on average difference in 16 clocks of reference clock. + * | | |11 = Trim value calculation is based on average difference in 32 clocks of reference clock. + * | | |Note: For example, if LOOPSEL is set as 00, auto trim circuit will calculate trim value based on the average frequency difference in 4 clocks of reference clock. + * |[7:6] |RETRYCNT |Trim Value Update Limitation Count + * | | |This field defines that how many times the auto trim circuit will try to update the HIRC trim value before the frequency of HIRC locked. + * | | |Once the HIRC locked, the internal trim value update counter will be reset. + * | | |If the trim value update counter reached this limitation value and frequency of HIRC still doesn't lock, the auto trim operation will be disabled and FREQSEL will be cleared to 00. + * | | |00 = Trim retry count limitation is 64 loops. + * | | |01 = Trim retry count limitation is 128 loops. + * | | |10 = Trim retry count limitation is 256 loops. + * | | |11 = Trim retry count limitation is 512 loops. + * |[9] |BOUNDEN |Boundary Enable Bit + * | | |0 = Boundary function is disable. + * | | |1 = Boundary function is enable. + * |[8] |CESTOPEN |Clock Error Stop Enable Bit + * | | |0 = The trim operation is keep going if clock is inaccuracy. + * | | |1 = The trim operation is stopped if clock is inaccuracy. + * |[10] |REFCKSEL |Reference Clock Selection + * | | |0 = HIRC trim reference clock is from external 32.768 kHz crystal oscillator. + * | | |1 = HIRC trim reference clock is from internal USB synchronous mode. + * |[20:16] |BOUNDARY |Boundary Selection + * | | |Fill the boundary range from 0x1 to 0x31, 0x0 is reserved. + * | | |Note: This field is effective only when the BOUNDEN(SYS_TCTL12M[9]) is enabled. + * @var SYS_T::TIEN12M + * Offset: 0xF4 HIRC 12M Trim Interrupt Enable Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[1] |TFAILIEN |Trim Failure Interrupt Enable Bit + * | | |This bit controls if an interrupt will be triggered while HIRC trim value update limitation count reached and HIRC frequency still not locked on target frequency set by FREQSEL(SYS_TCTL12M[1:0]). + * | | |If this bit is high and TFAILIF(SYS_TISTS12M[1]) is set during auto trim operation, an interrupt will be triggered to notify that HIRC trim value update limitation count was reached. + * | | |0 = Disable TFAILIF(SYS_TISTS12M[1]) status to trigger an interrupt to CPU. + * | | |1 = Enable TFAILIF(SYS_TISTS12M[1]) status to trigger an interrupt to CPU. + * |[2] |CLKEIEN |Clock Error Interrupt Enable Bit + * | | |This bit controls if CPU would get an interrupt while clock is inaccuracy during auto trim operation. + * | | |If this bit is set to1, and CLKERRIF(SYS_TISTS12M[2]) is set during auto trim operation, an interrupt will be triggered to notify the clock frequency is inaccuracy. + * | | |0 = Disable CLKERRIF(SYS_TISTS12M[2]) status to trigger an interrupt to CPU. + * | | |1 = Enable CLKERRIF(SYS_TISTS12M[2]) status to trigger an interrupt to CPU. + * @var SYS_T::TISTS12M + * Offset: 0xF8 HIRC 12M Trim Interrupt Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |FREQLOCK |HIRC Frequency Lock Status + * | | |This bit indicates the HIRC frequency is locked. + * | | |This is a status bit and doesn't trigger any interrupt. + * | | |Write 1 to clear this to 0. + * | | |This bit will be set automatically, if the frequency is lock and the RC_TRIM is enabled. + * | | |0 = The internal high-speed oscillator frequency doesn't lock at 12 MHz yet. + * | | |1 = The internal high-speed oscillator frequency locked at 12 MHz. + * |[1] |TFAILIF |Trim Failure Interrupt Status + * | | |This bit indicates that HIRC trim value update limitation count reached and the HIRC clock frequency still doesn't be locked. + * | | |Once this bit is set, the auto trim operation stopped and FREQSEL(SYS_TCTL12M[1:0]) will be cleared to 00 by hardware automatically. + * | | |If this bit is set and TFAILIEN(SYS_TIEN12M[1]) is high, an interrupt will be triggered to notify that HIRC trim value update limitation count was reached. + * | | |Write 1 to clear this to 0. + * | | |0 = Trim value update limitation count does not reach. + * | | |1 = Trim value update limitation count reached and HIRC frequency still not locked. + * |[2] |CLKERRIF |Clock Error Interrupt Status + * | | |When the frequency of 32.768 kHz external low speed crystal oscillator (LXT) or 12MHz internal high speed RC oscillator (HIRC) is shift larger to unreasonable value, this bit will be set and to be an indicate that clock frequency is inaccuracy + * | | |Once this bit is set to 1, the auto trim operation stopped and FREQSEL(SYS_TICTL12M[1:0]) will be cleared to 00 by hardware automatically if CESTOPEN(SYS_TCTL12M[8]) is set to 1. + * | | |If this bit is set and CLKEIEN(SYS_TIEN12M[2]) is high, an interrupt will be triggered to notify the clock frequency is inaccuracy. + * | | |Write 1 to clear this to 0. + * | | |0 = Clock frequency is accuracy. + * | | |1 = Clock frequency is inaccuracy. + * |[3] |OVBDIF |Over Boundary Status + * | | |When the over boundary function is set, if there occurs the over boundary condition, this flag will be set. + * | | |0 = Over boundary condition did not occur. + * | | |1 = Over boundary condition occurred. + * | | |Note: Write 1 to clear this flag. + * @var SYS_T::REGLCTL + * Offset: 0x100 Register Lock Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[7:0] |REGLCTL |Register Lock Control Code (Write Only) + * | | |Some registers have write-protection function + * | | |Writing these registers have to disable the protected function by writing the sequence value 59h, 16h, 88h to this field. + * | | |After this sequence is completed, the REGLCTL bit will be set to 1 and write-protection registers can be normal write. + * |[0] |REGLCTL[0]|Register Lock Control Disable Index (Read Only) + * | | |0 = Write-protection Enabled for writing protected registers. + * | | |Any write to the protected register is ignored. + * | | |1 = Write-protection Disabled for writing protected registers. + * @var SYS_T::CPUCFG + * Offset: 0x1D8 CPU General Configuration Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |INTRTEN |CPU Interrupt Realtime Enable Bit + * | | |When this bit is 0, the latency of CPU entering interrupt service routine (ISR) will be various but shorter. + * | | |When this bit is 1, the latency of CPU entering ISR will be kept constant. + * | | |0 = CPU Interrupt Realtime Disabled. + * | | |1 = CPU Interrupt Realtime Enabled. + * @var SYS_T::PORCTL1 + * Offset: 0x1EC Power-on Reset Controller Register 1 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |POROFF |Power-on Reset Enable Bit (Write Protect) + * | | |When powered on, the POR circuit generates a reset signal to reset the whole chip function, but noise on the power may cause the POR active again. + * | | |User can disable internal POR circuit to avoid unpredictable noise to cause chip reset by writing 0x5AA5 to this field. + * | | |The POR function will be active again when this field is set to another value or chip is reset by other reset source, including: + * | | |nRESET, Watchdog, LVR reset, BOD reset, ICE reset command and the software-chip reset function. + * | | |Note: These bits are write protected. Refer to the SYS_REGLCTL register. + * @var SYS_T::PSWCTL + * Offset: 0x1F4 Power Switch Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[12] |CRPTPWREN |Cryptographic Accelerator Power Switch Enable Bit (Write Protect) + * | | |0 = Cryptographic accelerator power supply Disabled. + * | | |1 = Cryptographic accelerator power supply Enabled. + * | | |Note 1: If this bit is set 1, RSA of SYS_SRAMPC1 is set to normal mode by hardware. + * | | |Note 2: Write ignored when PCBUSY(SYS_SRAMPC1[31]) is 1. + * | | |Note 3: This bit is write protected. Refer to the SYS_REGLCTL register. + * @var SYS_T::PLCTL + * Offset: 0x1F8 Power Level Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[1:0] |PLSEL |Power Level Select (Write Protect) + * | | |00 = Set to Power level 0 (PL0). Support system clock up to 96MHz. + * | | |01 = Set to Power level 1 (PL1). Support system clock up to 84MHz. + * | | |10 = Set to Power level 2 (PL2). Support system clock up to 64MHz. + * | | |11 = Set to Power level 3 (PL3). Support system clock up to 4MHz. + * | | |Note 1: These bits are write protected. Refer to the SYS_REGLCTL register. + * | | |Note 2: These bits not be reset when wake-up from Standby Power-down mode(SPD). + * |[4] |MVRS |Main Voltage Regulator Type Select (Write Protect) + * | | |This bit filed sets main voltage regulator type. + * | | |After setting main voltage regulator type to DCDC (MVRS (SYS_PLCTL[4]) = 1) system will set main voltage regulator type change busy flag MVRCBUSY(SYS_PLSTS[1]), detect inductor connection and update inductor connection status LCONS (SYS_PLSTS[3]). + * | | |If inductor exist LCONS will be cleared and main voltage regulator type can switch to DCDC (CURMVRS (SYS_PLSTS[12])=1). + * | | |0 = Set main voltage regulator to LDO. + * | | |1 = Set main voltage regulator to DCDC. + * | | |Note 1: This bit is write protected. Refer to the SYS_REGLCTL register. + * | | |Note 2: This bit not be reset when wake-up from Standby Power-down mode(SPD). + * |[7] |WRBUSY |Write Busy Flag + * | | |If SYS_PLCTL be written, this bit be asserted automatic by hardware, and be de-asserted when write procedure finish. + * | | |0 = SYS_PLCTL register is ready for write operation. + * | | |1 = SYS_PLCTL register is busy on the last write operation. Other write operations are ignored. + * |[21:16] |LVSSTEP |LDO Voltage Scaling Step (Write Protect) + * | | |The LVSSTEP value is LDO voltage rising step. + * | | |LDO voltage scaling step = (LVSSTEP + 1) * 10mV. + * | | |Note: These bits are write protected. Refer to the SYS_REGLCTL register. + * |[31:24] |LVSPRD |LDO Voltage Scaling Period (Write Protect) + * | | |The LVSPRD value is the period of each LDO voltage rising step. + * | | |LDO voltage scaling period = (LVSPRD + 1) * 1us. + * | | |Note: These bits are write protected. Refer to the SYS_REGLCTL register. + * @var SYS_T::PLSTS + * Offset: 0x1FC Power Level Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |PLCBUSY |Power Level Change Busy Bit (Read Only) + * | | |This bit is set by hardware when power level is changing. + * | | |After power level change is completed, this bit will be cleared automatically by hardware. + * | | |0 = Power level change is completed. + * | | |1 = Power level change is ongoing. + * |[1] |MVRCBUSY |Main Voltage Regulator Type Change Busy Bit (Read Only) + * | | |This bit is set by hardware when main voltage regulator type is changing. + * | | |After main voltage regulator type change is completed, this bit will be cleared automatically by hardware. + * | | |0 = Main voltage regulator type change is completed. + * | | |1 = Main voltage regulator type change is ongoing. + * |[2] |MVRCERR |Main Voltage Regulator Type Change Error Bit (Write Protect) + * | | |This bit is set to 1 when main voltage regulator type change from LDO to DCDC error, the following conditions will cause change errors: + * | | |1.System change to DC-DC mode but LDO change voltage process not finish. + * | | |2.Detect inductor fail. + * | | |Read: + * | | |0 = No main voltage regulator type change error. + * | | |1 = Main voltage regulator type change to DCDC error occurred. + * | | |Write: + * | | |0 = No effect. + * | | |1 = Clears MVRCERR to 0. + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * |[3] |LCONS |Inductor for DC-DC Connect Status (Read Only) + * | | |0 = Inductor connect between Vsw and LDO_CAP pin. + * | | |This bit is valid when current main voltage regulator type is DCDC (CURMVRS (SYS_PLSTS[12])=1). + * | | |If current main voltage regulator type is LDO (CURMVRS (SYS_PLSTS[12])=0), this bit is set to 1. + * | | |0 = Inductor connect between Vsw and LDO_CAP pin. + * | | |1 = No Inductor connect between Vsw and LDO_CAP pin. + * | | |Note: This bit is 1 when main voltage regulator is LDO. + * |[9:8] |PLSTATUS |Power Level Status (Read Only) + * | | |This bit field reflect the current power level. + * | | |00 = Power level is PL0. Support system clock up to 96MHz. + * | | |01 = Power level is PL1. Support system clock up to 84MHz. + * | | |10 = Power level is PL2. Support system clock up to 48MHz. + * | | |11 = Power level is PL3. Support system clock up to 4MHz. + * |[12] |CURMVR |Current Main Voltage Regulator Type (Read Only) + * | | |This bit field reflects current main voltage regulator type. + * | | |0 = Current main voltage regulator in active and Idle mode is LDO. + * | | |1 = Current main voltage regulator in active and Idle mode is DCDC. + * @var SYS_T::AHBMCTL + * Offset: 0x400 AHB Bus Matrix Priority Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |INTACTEN |Highest AHB Bus Priority of Cortex-M23 Core Enable Bit (Write Protect) + * | | |Enable Cortex-M23 core with highest AHB bus priority in AHB bus matrix. + * | | |0 = Run robin mode. + * | | |1 = Cortex-M23 CPU with highest bus priority when interrupt occurs. + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + */ + + __I uint32_t PDID; /*!< [0x0000] Part Device Identification Number Register */ + __IO uint32_t RSTSTS; /*!< [0x0004] System Reset Status Register */ + __IO uint32_t IPRST0; /*!< [0x0008] Peripheral Reset Control Register 0 */ + __IO uint32_t IPRST1; /*!< [0x000c] Peripheral Reset Control Register 1 */ + __IO uint32_t IPRST2; /*!< [0x0010] Peripheral Reset Control Register 2 */ + __I uint32_t RESERVE0[1]; + __IO uint32_t BODCTL; /*!< [0x0018] Brown-out Detector Control Register */ + __IO uint32_t IVSCTL; /*!< [0x001c] Internal Voltage Source Control Register */ + __I uint32_t RESERVE1[1]; + __IO uint32_t PORCTL0; /*!< [0x0024] Power-on Reset Controller Register 0 */ + __IO uint32_t VREFCTL; /*!< [0x0028] VREF Control Register */ + __IO uint32_t USBPHY; /*!< [0x002C] USB PHY Control Register */ + __IO uint32_t GPA_MFPL; /*!< [0x0030] GPIOA Low Byte Multiple Function Control Register */ + __IO uint32_t GPA_MFPH; /*!< [0x0034] GPIOA High Byte Multiple Function Control Register */ + __IO uint32_t GPB_MFPL; /*!< [0x0038] GPIOB Low Byte Multiple Function Control Register */ + __IO uint32_t GPB_MFPH; /*!< [0x003c] GPIOB High Byte Multiple Function Control Register */ + __IO uint32_t GPC_MFPL; /*!< [0x0040] GPIOC Low Byte Multiple Function Control Register */ + __IO uint32_t GPC_MFPH; /*!< [0x0044] GPIOC High Byte Multiple Function Control Register */ + __IO uint32_t GPD_MFPL; /*!< [0x0048] GPIOD Low Byte Multiple Function Control Register */ + __IO uint32_t GPD_MFPH; /*!< [0x004c] GPIOD High Byte Multiple Function Control Register */ + __IO uint32_t GPE_MFPL; /*!< [0x0050] GPIOE Low Byte Multiple Function Control Register */ + __IO uint32_t GPE_MFPH; /*!< [0x0054] GPIOE High Byte Multiple Function Control Register */ + __IO uint32_t GPF_MFPL; /*!< [0x0058] GPIOF Low Byte Multiple Function Control Register */ + __IO uint32_t GPF_MFPH; /*!< [0x005C] GPIOF High Byte Multiple Function Control Register */ + __IO uint32_t GPG_MFPL; /*!< [0x0060] GPIOG Low Byte Multiple Function Control Register */ + __IO uint32_t GPG_MFPH; /*!< [0x0064] GPIOG High Byte Multiple Function Control Register */ + __IO uint32_t GPH_MFPL; /*!< [0x0068] GPIOH Low Byte Multiple Function Control Register */ + __IO uint32_t GPH_MFPH; /*!< [0x006C] GPIOH High Byte Multiple Function Control Register */ + __I uint32_t RESERVE2[4]; + __IO uint32_t GPA_MFOS; /*!< [0x0080] GPIOA Multiple Function Output Select Register */ + __IO uint32_t GPB_MFOS; /*!< [0x0084] GPIOB Multiple Function Output Select Register */ + __IO uint32_t GPC_MFOS; /*!< [0x0088] GPIOC Multiple Function Output Select Register */ + __IO uint32_t GPD_MFOS; /*!< [0x008c] GPIOD Multiple Function Output Select Register */ + __IO uint32_t GPE_MFOS; /*!< [0x0090] GPIOE Multiple Function Output Select Register */ + __IO uint32_t GPF_MFOS; /*!< [0x0094] GPIOF Multiple Function Output Select Register */ + __IO uint32_t GPG_MFOS; /*!< [0x0098] GPIOG Multiple Function Output Select Register */ + __IO uint32_t GPH_MFOS; /*!< [0x009c] GPIOH Multiple Function Output Select Register */ + __IO uint32_t VTORSET; /*!< [0x00A0] VTOR Setting Register */ + __I uint32_t RESERVE3[7]; + __IO uint32_t SRAMICTL; /*!< [0x00C0] System SRAM Interrupt Enable Control Register */ + __I uint32_t SRAMSTS; /*!< [0x00C4] System SRAM Parity Error Status Register */ + __I uint32_t SRAMEADR; /*!< [0x00C8] System SRAM Parity Check Error Address Register */ + __IO uint32_t RESERVE4[4]; + __IO uint32_t SRAMPC0; /*!< [0x00DC] SRAM Power Mode Control Register 0 */ + __IO uint32_t SRAMPC1; /*!< [0x00E0] SRAM Power Mode Control Register 1 */ + __IO uint32_t TCTL48M; /*!< [0x00E4] HIRC 48M Trim Control Register */ + __IO uint32_t TIEN48M; /*!< [0x00E8] HIRC 48M Trim Interrupt Enable Register */ + __IO uint32_t TISTS48M; /*!< [0x00EC] HIRC 48M Trim Interrupt Status Register */ + __IO uint32_t TCTL12M; /*!< [0x00F0] HIRC 12M Trim Control Register */ + __IO uint32_t TIEN12M; /*!< [0x00F4] HIRC 12M Trim Interrupt Enable Register */ + __IO uint32_t TISTS12M; /*!< [0x00F8] HIRC 12M Trim Interrupt Status Register */ + __I uint32_t RESERVE6[1]; + __IO uint32_t REGLCTL; /*!< [0x0100] Register Lock Control Register */ + __I uint32_t RESERVE7[53]; + __IO uint32_t CPUCFG; /*!< [0x01D8] CPU General Configuration Register */ + __IO uint32_t BATLDCTL; /*!< [0x01DC] Battery Loss Detector Control Register */ + __IO uint32_t OVDCTL; /*!< [0x01E0] Over Voltage Detector Control Register */ + __I uint32_t RESERVE8[2]; + __IO uint32_t PORCTL1; /*!< [0x01EC] Power-on Reset Controller Register 1 */ + __I uint32_t RESERVE9[1]; + __IO uint32_t PSWCTL; /*!< [0x01F4] Power Switch Control Register */ + __IO uint32_t PLCTL; /*!< [0x01F8] Power Level Control Register */ + __IO uint32_t PLSTS; /*!< [0x01FC] Power Level Status Register */ + __I uint32_t RESERVE10[128]; + __IO uint32_t AHBMCTL; /*!< [0x0400] AHB Bus Matrix Priority Control Register */ + + +} SYS_T; + +/** + @addtogroup SYS_CONST SYS Bit Field Definition + Constant Definitions for SYS Controller + @{ +*/ + +#define SYS_PDID_PDID_Pos (0) /*!< SYS_T::PDID: PDID Position */ +#define SYS_PDID_PDID_Msk (0xfffffffful << SYS_PDID_PDID_Pos) /*!< SYS_T::PDID: PDID Mask */ + +#define SYS_RSTSTS_PORF_Pos (0) /*!< SYS_T::RSTSTS: PORF Position */ +#define SYS_RSTSTS_PORF_Msk (0x1ul << SYS_RSTSTS_PORF_Pos) /*!< SYS_T::RSTSTS: PORF Mask */ + +#define SYS_RSTSTS_PINRF_Pos (1) /*!< SYS_T::RSTSTS: PINRF Position */ +#define SYS_RSTSTS_PINRF_Msk (0x1ul << SYS_RSTSTS_PINRF_Pos) /*!< SYS_T::RSTSTS: PINRF Mask */ + +#define SYS_RSTSTS_WDTRF_Pos (2) /*!< SYS_T::RSTSTS: WDTRF Position */ +#define SYS_RSTSTS_WDTRF_Msk (0x1ul << SYS_RSTSTS_WDTRF_Pos) /*!< SYS_T::RSTSTS: WDTRF Mask */ + +#define SYS_RSTSTS_LVRF_Pos (3) /*!< SYS_T::RSTSTS: LVRF Position */ +#define SYS_RSTSTS_LVRF_Msk (0x1ul << SYS_RSTSTS_LVRF_Pos) /*!< SYS_T::RSTSTS: LVRF Mask */ + +#define SYS_RSTSTS_BODRF_Pos (4) /*!< SYS_T::RSTSTS: BODRF Position */ +#define SYS_RSTSTS_BODRF_Msk (0x1ul << SYS_RSTSTS_BODRF_Pos) /*!< SYS_T::RSTSTS: BODRF Mask */ + +#define SYS_RSTSTS_SYSRF_Pos (5) /*!< SYS_T::RSTSTS: SYSRF Position */ +#define SYS_RSTSTS_SYSRF_Msk (0x1ul << SYS_RSTSTS_SYSRF_Pos) /*!< SYS_T::RSTSTS: SYSRF Mask */ + +#define SYS_RSTSTS_CPURF_Pos (7) /*!< SYS_T::RSTSTS: CPURF Position */ +#define SYS_RSTSTS_CPURF_Msk (0x1ul << SYS_RSTSTS_CPURF_Pos) /*!< SYS_T::RSTSTS: CPURF Mask */ + +#define SYS_RSTSTS_CPULKRF_Pos (8) /*!< SYS_T::RSTSTS: CPULKRF Position */ +#define SYS_RSTSTS_CPULKRF_Msk (0x1ul << SYS_RSTSTS_CPULKRF_Pos) /*!< SYS_T::RSTSTS: CPULKRF Mask */ + +#define SYS_IPRST0_CHIPRST_Pos (0) /*!< SYS_T::IPRST0: CHIPRST Position */ +#define SYS_IPRST0_CHIPRST_Msk (0x1ul << SYS_IPRST0_CHIPRST_Pos) /*!< SYS_T::IPRST0: CHIPRST Mask */ + +#define SYS_IPRST0_CPURST_Pos (1) /*!< SYS_T::IPRST0: CPURST Position */ +#define SYS_IPRST0_CPURST_Msk (0x1ul << SYS_IPRST0_CPURST_Pos) /*!< SYS_T::IPRST0: CPURST Mask */ + +#define SYS_IPRST0_PDMA0RST_Pos (2) /*!< SYS_T::IPRST0: PDMA0RST Position */ +#define SYS_IPRST0_PDMA0RST_Msk (0x1ul << SYS_IPRST0_PDMA0RST_Pos) /*!< SYS_T::IPRST0: PDMA0RST Mask */ + +#define SYS_IPRST0_EBIRST_Pos (3) /*!< SYS_T::IPRST0: EBIRST Position */ +#define SYS_IPRST0_EBIRST_Msk (0x1ul << SYS_IPRST0_EBIRST_Pos) /*!< SYS_T::IPRST0: EBIRST Mask */ + +#define SYS_IPRST0_USBHRST_Pos (4) /*!< SYS_T::IPRST0: USBHRST Position */ +#define SYS_IPRST0_USBHRST_Msk (0x1ul << SYS_IPRST0_USBHRST_Pos) /*!< SYS_T::IPRST0: USBHRST Mask */ + +#define SYS_IPRST0_SDH0RST_Pos (6) /*!< SYS_T::IPRST0: SDH0RST Position */ +#define SYS_IPRST0_SDH0RST_Msk (0x1ul << SYS_IPRST0_SDH0RST_Pos) /*!< SYS_T::IPRST0: SDH0RST Mask */ + +#define SYS_IPRST0_CRCRST_Pos (7) /*!< SYS_T::IPRST0: CRCRST Position */ +#define SYS_IPRST0_CRCRST_Msk (0x1ul << SYS_IPRST0_CRCRST_Pos) /*!< SYS_T::IPRST0: CRCRST Mask */ + +#define SYS_IPRST0_CRPTRST_Pos (12) /*!< SYS_T::IPRST0: CRPTRST Position */ +#define SYS_IPRST0_CRPTRST_Msk (0x1ul << SYS_IPRST0_CRPTRST_Pos) /*!< SYS_T::IPRST0: CRPTRST Mask */ + +#define SYS_IPRST0_KSRST_Pos (13) /*!< SYS_T::IPRST0: KSRST Position */ +#define SYS_IPRST0_KSRST_Msk (0x1ul << SYS_IPRST0_KSRST_Pos) /*!< SYS_T::IPRST0: KSRST Mask */ + +#define SYS_IPRST0_PDMA1RST_Pos (29) /*!< SYS_T::IPRST0: PDMA1RST Position */ +#define SYS_IPRST0_PDMA1RST_Msk (0x1ul << SYS_IPRST0_PDMA1RST_Pos) /*!< SYS_T::IPRST0: PDMA1RST Mask */ + +#define SYS_IPRST1_GPIORST_Pos (1) /*!< SYS_T::IPRST1: GPIORST Position */ +#define SYS_IPRST1_GPIORST_Msk (0x1ul << SYS_IPRST1_GPIORST_Pos) /*!< SYS_T::IPRST1: GPIORST Mask */ + +#define SYS_IPRST1_TMR0RST_Pos (2) /*!< SYS_T::IPRST1: TMR0RST Position */ +#define SYS_IPRST1_TMR0RST_Msk (0x1ul << SYS_IPRST1_TMR0RST_Pos) /*!< SYS_T::IPRST1: TMR0RST Mask */ + +#define SYS_IPRST1_TMR1RST_Pos (3) /*!< SYS_T::IPRST1: TMR1RST Position */ +#define SYS_IPRST1_TMR1RST_Msk (0x1ul << SYS_IPRST1_TMR1RST_Pos) /*!< SYS_T::IPRST1: TMR1RST Mask */ + +#define SYS_IPRST1_TMR2RST_Pos (4) /*!< SYS_T::IPRST1: TMR2RST Position */ +#define SYS_IPRST1_TMR2RST_Msk (0x1ul << SYS_IPRST1_TMR2RST_Pos) /*!< SYS_T::IPRST1: TMR2RST Mask */ + +#define SYS_IPRST1_TMR3RST_Pos (5) /*!< SYS_T::IPRST1: TMR3RST Position */ +#define SYS_IPRST1_TMR3RST_Msk (0x1ul << SYS_IPRST1_TMR3RST_Pos) /*!< SYS_T::IPRST1: TMR3RST Mask */ + +#define SYS_IPRST1_ACMP01RST_Pos (7) /*!< SYS_T::IPRST1: ACMP01RST Position */ +#define SYS_IPRST1_ACMP01RST_Msk (0x1ul << SYS_IPRST1_ACMP01RST_Pos) /*!< SYS_T::IPRST1: ACMP01RST Mask */ + +#define SYS_IPRST1_I2C0RST_Pos (8) /*!< SYS_T::IPRST1: I2C0RST Position */ +#define SYS_IPRST1_I2C0RST_Msk (0x1ul << SYS_IPRST1_I2C0RST_Pos) /*!< SYS_T::IPRST1: I2C0RST Mask */ + +#define SYS_IPRST1_I2C1RST_Pos (9) /*!< SYS_T::IPRST1: I2C1RST Position */ +#define SYS_IPRST1_I2C1RST_Msk (0x1ul << SYS_IPRST1_I2C1RST_Pos) /*!< SYS_T::IPRST1: I2C1RST Mask */ + +#define SYS_IPRST1_I2C2RST_Pos (10) /*!< SYS_T::IPRST1: I2C2RST Position */ +#define SYS_IPRST1_I2C2RST_Msk (0x1ul << SYS_IPRST1_I2C2RST_Pos) /*!< SYS_T::IPRST1: I2C2RST Mask */ + +#define SYS_IPRST1_QSPI0RST_Pos (12) /*!< SYS_T::IPRST1: QSPI0RST Position */ +#define SYS_IPRST1_QSPI0RST_Msk (0x1ul << SYS_IPRST1_QSPI0RST_Pos) /*!< SYS_T::IPRST1: QSPI0RST Mask */ + +#define SYS_IPRST1_SPI0RST_Pos (13) /*!< SYS_T::IPRST1: SPI0RST Position */ +#define SYS_IPRST1_SPI0RST_Msk (0x1ul << SYS_IPRST1_SPI0RST_Pos) /*!< SYS_T::IPRST1: SPI0RST Mask */ + +#define SYS_IPRST1_SPI1RST_Pos (14) /*!< SYS_T::IPRST1: SPI1RST Position */ +#define SYS_IPRST1_SPI1RST_Msk (0x1ul << SYS_IPRST1_SPI1RST_Pos) /*!< SYS_T::IPRST1: SPI1RST Mask */ + +#define SYS_IPRST1_SPI2RST_Pos (15) /*!< SYS_T::IPRST1: SPI2RST Position */ +#define SYS_IPRST1_SPI2RST_Msk (0x1ul << SYS_IPRST1_SPI2RST_Pos) /*!< SYS_T::IPRST1: SPI2RST Mask */ + +#define SYS_IPRST1_UART0RST_Pos (16) /*!< SYS_T::IPRST1: UART0RST Position */ +#define SYS_IPRST1_UART0RST_Msk (0x1ul << SYS_IPRST1_UART0RST_Pos) /*!< SYS_T::IPRST1: UART0RST Mask */ + +#define SYS_IPRST1_UART1RST_Pos (17) /*!< SYS_T::IPRST1: UART1RST Position */ +#define SYS_IPRST1_UART1RST_Msk (0x1ul << SYS_IPRST1_UART1RST_Pos) /*!< SYS_T::IPRST1: UART1RST Mask */ + +#define SYS_IPRST1_UART2RST_Pos (18) /*!< SYS_T::IPRST1: UART2RST Position */ +#define SYS_IPRST1_UART2RST_Msk (0x1ul << SYS_IPRST1_UART2RST_Pos) /*!< SYS_T::IPRST1: UART2RST Mask */ + +#define SYS_IPRST1_UART3RST_Pos (19) /*!< SYS_T::IPRST1: UART3RST Position */ +#define SYS_IPRST1_UART3RST_Msk (0x1ul << SYS_IPRST1_UART3RST_Pos) /*!< SYS_T::IPRST1: UART3RST Mask */ + +#define SYS_IPRST1_UART4RST_Pos (20) /*!< SYS_T::IPRST1: UART4RST Position */ +#define SYS_IPRST1_UART4RST_Msk (0x1ul << SYS_IPRST1_UART4RST_Pos) /*!< SYS_T::IPRST1: UART4RST Mask */ + +#define SYS_IPRST1_UART5RST_Pos (21) /*!< SYS_T::IPRST1: UART5RST Position */ +#define SYS_IPRST1_UART5RST_Msk (0x1ul << SYS_IPRST1_UART5RST_Pos) /*!< SYS_T::IPRST1: UART5RST Mask */ + +#define SYS_IPRST1_CAN0RST_Pos (24) /*!< SYS_T::IPRST1: CAN0RST Position */ +#define SYS_IPRST1_CAN0RST_Msk (0x1ul << SYS_IPRST1_CAN0RST_Pos) /*!< SYS_T::IPRST1: CAN0RST Mask */ + +#define SYS_IPRST1_OTGRST_Pos (26) /*!< SYS_T::IPRST1: OTGRST Position */ +#define SYS_IPRST1_OTGRST_Msk (0x1ul << SYS_IPRST1_OTGRST_Pos) /*!< SYS_T::IPRST1: OTGRST Mask */ + +#define SYS_IPRST1_USBDRST_Pos (27) /*!< SYS_T::IPRST1: USBDRST Position */ +#define SYS_IPRST1_USBDRST_Msk (0x1ul << SYS_IPRST1_USBDRST_Pos) /*!< SYS_T::IPRST1: USBDRST Mask */ + +#define SYS_IPRST1_EADCRST_Pos (28) /*!< SYS_T::IPRST1: EADCRST Position */ +#define SYS_IPRST1_EADCRST_Msk (0x1ul << SYS_IPRST1_EADCRST_Pos) /*!< SYS_T::IPRST1: EADCRST Mask */ + +#define SYS_IPRST1_I2S0RST_Pos (29) /*!< SYS_T::IPRST1: I2S0RST Position */ +#define SYS_IPRST1_I2S0RST_Msk (0x1ul << SYS_IPRST1_I2S0RST_Pos) /*!< SYS_T::IPRST1: I2S0RST Mask */ + +#define SYS_IPRST1_LCDRST_Pos (30) /*!< SYS_T::IPRST1: LCDRST Position */ +#define SYS_IPRST1_LCDRST_Msk (0x1ul << SYS_IPRST1_LCDRST_Pos) /*!< SYS_T::IPRST1: LCDRST Mask */ + +#define SYS_IPRST1_TRNGRST_Pos (31) /*!< SYS_T::IPRST1: TRNGRST Position */ +#define SYS_IPRST1_TRNGRST_Msk (0x1ul << SYS_IPRST1_TRNGRST_Pos) /*!< SYS_T::IPRST1: TRNGRST Mask */ + +#define SYS_IPRST2_SC0RST_Pos (0) /*!< SYS_T::IPRST2: SC0RST Position */ +#define SYS_IPRST2_SC0RST_Msk (0x1ul << SYS_IPRST2_SC0RST_Pos) /*!< SYS_T::IPRST2: SC0RST Mask */ + +#define SYS_IPRST2_SC1RST_Pos (1) /*!< SYS_T::IPRST2: SC1RST Position */ +#define SYS_IPRST2_SC1RST_Msk (0x1ul << SYS_IPRST2_SC1RST_Pos) /*!< SYS_T::IPRST2: SC1RST Mask */ + +#define SYS_IPRST2_SC2RST_Pos (2) /*!< SYS_T::IPRST2: SC2RST Position */ +#define SYS_IPRST2_SC2RST_Msk (0x1ul << SYS_IPRST2_SC2RST_Pos) /*!< SYS_T::IPRST2: SC2RST Mask */ + +#define SYS_IPRST2_SPI3RST_Pos (6) /*!< SYS_T::IPRST2: SPI3RST Position */ +#define SYS_IPRST2_SPI3RST_Msk (0x1ul << SYS_IPRST2_SPI3RST_Pos) /*!< SYS_T::IPRST2: SPI3RST Mask */ + +#define SYS_IPRST2_USCI0RST_Pos (8) /*!< SYS_T::IPRST2: USCI0RST Position */ +#define SYS_IPRST2_USCI0RST_Msk (0x1ul << SYS_IPRST2_USCI0RST_Pos) /*!< SYS_T::IPRST2: USCI0RST Mask */ + +#define SYS_IPRST2_USCI1RST_Pos (9) /*!< SYS_T::IPRST2: USCI1RST Position */ +#define SYS_IPRST2_USCI1RST_Msk (0x1ul << SYS_IPRST2_USCI1RST_Pos) /*!< SYS_T::IPRST2: USCI1RST Mask */ + +#define SYS_IPRST2_DACRST_Pos (12) /*!< SYS_T::IPRST2: DACRST Position */ +#define SYS_IPRST2_DACRST_Msk (0x1ul << SYS_IPRST2_DACRST_Pos) /*!< SYS_T::IPRST2: DACRST Mask */ + +#define SYS_IPRST2_EPWM0RST_Pos (16) /*!< SYS_T::IPRST2: EPWM0RST Position */ +#define SYS_IPRST2_EPWM0RST_Msk (0x1ul << SYS_IPRST2_EPWM0RST_Pos) /*!< SYS_T::IPRST2: EPWM0RST Mask */ + +#define SYS_IPRST2_EPWM1RST_Pos (17) /*!< SYS_T::IPRST2: EPWM1RST Position */ +#define SYS_IPRST2_EPWM1RST_Msk (0x1ul << SYS_IPRST2_EPWM1RST_Pos) /*!< SYS_T::IPRST2: EPWM1RST Mask */ + +#define SYS_IPRST2_BPWM0RST_Pos (18) /*!< SYS_T::IPRST2: BPWM0RST Position */ +#define SYS_IPRST2_BPWM0RST_Msk (0x1ul << SYS_IPRST2_BPWM0RST_Pos) /*!< SYS_T::IPRST2: BPWM0RST Mask */ + +#define SYS_IPRST2_BPWM1RST_Pos (19) /*!< SYS_T::IPRST2: BPWM1RST Position */ +#define SYS_IPRST2_BPWM1RST_Msk (0x1ul << SYS_IPRST2_BPWM1RST_Pos) /*!< SYS_T::IPRST2: BPWM1RST Mask */ + +#define SYS_IPRST2_TMR4RST_Pos (20) /*!< SYS_T::IPRST2: TMR4RST Position */ +#define SYS_IPRST2_TMR4RST_Msk (0x1ul << SYS_IPRST2_TMR4RST_Pos) /*!< SYS_T::IPRST2: TMR4RST Mask */ + +#define SYS_IPRST2_TMR5RST_Pos (21) /*!< SYS_T::IPRST2: TMR5RST Position */ +#define SYS_IPRST2_TMR5RST_Msk (0x1ul << SYS_IPRST2_TMR5RST_Pos) /*!< SYS_T::IPRST2: TMR5RST Mask */ + +#define SYS_IPRST2_QEI0RST_Pos (22) /*!< SYS_T::IPRST2: QEI0RST Position */ +#define SYS_IPRST2_QEI0RST_Msk (0x1ul << SYS_IPRST2_QEI0RST_Pos) /*!< SYS_T::IPRST2: QEI0RST Mask */ + +#define SYS_IPRST2_QEI1RST_Pos (23) /*!< SYS_T::IPRST2: QEI1RST Position */ +#define SYS_IPRST2_QEI1RST_Msk (0x1ul << SYS_IPRST2_QEI1RST_Pos) /*!< SYS_T::IPRST2: QEI1RST Mask */ + +#define SYS_IPRST2_ECAP0RST_Pos (26) /*!< SYS_T::IPRST2: ECAP0RST Position */ +#define SYS_IPRST2_ECAP0RST_Msk (0x1ul << SYS_IPRST2_ECAP0RST_Pos) /*!< SYS_T::IPRST2: ECAP0RST Mask */ + +#define SYS_IPRST2_ECAP1RST_Pos (27) /*!< SYS_T::IPRST2: ECAP1RST Position */ +#define SYS_IPRST2_ECAP1RST_Msk (0x1ul << SYS_IPRST2_ECAP1RST_Pos) /*!< SYS_T::IPRST2: ECAP1RST Mask */ + +#define SYS_BODCTL_BODEN_Pos (0) /*!< SYS_T::BODCTL: BODEN Position */ +#define SYS_BODCTL_BODEN_Msk (0x1ul << SYS_BODCTL_BODEN_Pos) /*!< SYS_T::BODCTL: BODEN Mask */ + +#define SYS_BODCTL_BODRSTEN_Pos (3) /*!< SYS_T::BODCTL: BODRSTEN Position */ +#define SYS_BODCTL_BODRSTEN_Msk (0x1ul << SYS_BODCTL_BODRSTEN_Pos) /*!< SYS_T::BODCTL: BODRSTEN Mask */ + +#define SYS_BODCTL_BODIF_Pos (4) /*!< SYS_T::BODCTL: BODIF Position */ +#define SYS_BODCTL_BODIF_Msk (0x1ul << SYS_BODCTL_BODIF_Pos) /*!< SYS_T::BODCTL: BODIF Mask */ + +#define SYS_BODCTL_BODOUT_Pos (6) /*!< SYS_T::BODCTL: BODOUT Position */ +#define SYS_BODCTL_BODOUT_Msk (0x1ul << SYS_BODCTL_BODOUT_Pos) /*!< SYS_T::BODCTL: BODOUT Mask */ + +#define SYS_BODCTL_LVREN_Pos (7) /*!< SYS_T::BODCTL: LVREN Position */ +#define SYS_BODCTL_LVREN_Msk (0x1ul << SYS_BODCTL_LVREN_Pos) /*!< SYS_T::BODCTL: LVREN Mask */ + +#define SYS_BODCTL_BODDGSEL_Pos (8) /*!< SYS_T::BODCTL: BODDGSEL Position */ +#define SYS_BODCTL_BODDGSEL_Msk (0x7ul << SYS_BODCTL_BODDGSEL_Pos) /*!< SYS_T::BODCTL: BODDGSEL Mask */ + +#define SYS_BODCTL_LVRDGSEL_Pos (12) /*!< SYS_T::BODCTL: LVRDGSEL Position */ +#define SYS_BODCTL_LVRDGSEL_Msk (0x7ul << SYS_BODCTL_LVRDGSEL_Pos) /*!< SYS_T::BODCTL: LVRDGSEL Mask */ + +#define SYS_BODCTL_BODVL_Pos (16) /*!< SYS_T::BODCTL: BODVL Position */ +#define SYS_BODCTL_BODVL_Msk (0x7ul << SYS_BODCTL_BODVL_Pos) /*!< SYS_T::BODCTL: BODVL Mask */ + +#define SYS_BODCTL_STB_Pos (23) /*!< SYS_T::BODCTL: STB Position */ +#define SYS_BODCTL_STB_Msk (0x1ul << SYS_BODCTL_STB_Pos) /*!< SYS_T::BODCTL: STB Mask */ + +#define SYS_BODCTL_WRBUSY_Pos (31) /*!< SYS_T::BODCTL: WRBUSY Position */ +#define SYS_BODCTL_WRBUSY_Msk (0x1ul << SYS_BODCTL_WRBUSY_Pos) /*!< SYS_T::BODCTL: WRBUSY Mask */ + +#define SYS_IVSCTL_VTEMPEN_Pos (0) /*!< SYS_T::IVSCTL: VTEMPEN Position */ +#define SYS_IVSCTL_VTEMPEN_Msk (0x1ul << SYS_IVSCTL_VTEMPEN_Pos) /*!< SYS_T::IVSCTL: VTEMPEN Mask */ + +#define SYS_IVSCTL_VBATUGEN_Pos (1) /*!< SYS_T::IVSCTL: VBATUGEN Position */ +#define SYS_IVSCTL_VBATUGEN_Msk (0x1ul << SYS_IVSCTL_VBATUGEN_Pos) /*!< SYS_T::IVSCTL: VBATUGEN Mask */ + +#define SYS_PORCTL0_PORMASK_Pos (0) /*!< SYS_T::PORCTL0: PORMASK Position */ +#define SYS_PORCTL0_PORMASK_Msk (0xfffful << SYS_PORCTL0_PORMASK_Pos) /*!< SYS_T::PORCTL0: PORMASK Mask */ + +#define SYS_VREFCTL_VREFCTL_Pos (0) /*!< SYS_T::VREFCTL: VREFCTL Position */ +#define SYS_VREFCTL_VREFCTL_Msk (0x1ful << SYS_VREFCTL_VREFCTL_Pos) /*!< SYS_T::VREFCTL: VREFCTL Mask */ + +#define SYS_VREFCTL_IBIASSEL_Pos (5) /*!< SYS_T::VREFCTL: IBIASSEL Position */ +#define SYS_VREFCTL_IBIASSEL_Msk (0x1ul << SYS_VREFCTL_IBIASSEL_Pos) /*!< SYS_T::VREFCTL: IBIASSEL Mask */ + +#define SYS_VREFCTL_PRELOADSEL_Pos (6) /*!< SYS_T::VREFCTL: PRELOADSEL Position */ +#define SYS_VREFCTL_PRELOADSEL_Msk (0x3ul << SYS_VREFCTL_PRELOADSEL_Pos) /*!< SYS_T::VREFCTL: PRELOADSEL Mask */ + +#define SYS_USBPHY_USBROLE_Pos (0) /*!< SYS_T::USBPHY: USBROLE Position */ +#define SYS_USBPHY_USBROLE_Msk (0x3ul << SYS_USBPHY_USBROLE_Pos) /*!< SYS_T::USBPHY: USBROLE Mask */ + +#define SYS_USBPHY_SBO_Pos (2) /*!< SYS_T::USBPHY: SBO Position */ +#define SYS_USBPHY_SBO_Msk (0x1ul << SYS_USBPHY_SBO_Pos) /*!< SYS_T::USBPHY: SBO Mask */ + +#define SYS_USBPHY_OTGPHYEN_Pos (8) /*!< SYS_T::USBPHY: OTGPHYEN Position */ +#define SYS_USBPHY_OTGPHYEN_Msk (0x1ul << SYS_USBPHY_OTGPHYEN_Pos) /*!< SYS_T::USBPHY: OTGPHYEN Mask */ + +#define SYS_GPA_MFPL_PA0MFP_Pos (0) /*!< SYS_T::GPA_MFPL: PA0MFP Position */ +#define SYS_GPA_MFPL_PA0MFP_Msk (0xful << SYS_GPA_MFPL_PA0MFP_Pos) /*!< SYS_T::GPA_MFPL: PA0MFP Mask */ + +#define SYS_GPA_MFPL_PA1MFP_Pos (4) /*!< SYS_T::GPA_MFPL: PA1MFP Position */ +#define SYS_GPA_MFPL_PA1MFP_Msk (0xful << SYS_GPA_MFPL_PA1MFP_Pos) /*!< SYS_T::GPA_MFPL: PA1MFP Mask */ + +#define SYS_GPA_MFPL_PA2MFP_Pos (8) /*!< SYS_T::GPA_MFPL: PA2MFP Position */ +#define SYS_GPA_MFPL_PA2MFP_Msk (0xful << SYS_GPA_MFPL_PA2MFP_Pos) /*!< SYS_T::GPA_MFPL: PA2MFP Mask */ + +#define SYS_GPA_MFPL_PA3MFP_Pos (12) /*!< SYS_T::GPA_MFPL: PA3MFP Position */ +#define SYS_GPA_MFPL_PA3MFP_Msk (0xful << SYS_GPA_MFPL_PA3MFP_Pos) /*!< SYS_T::GPA_MFPL: PA3MFP Mask */ + +#define SYS_GPA_MFPL_PA4MFP_Pos (16) /*!< SYS_T::GPA_MFPL: PA4MFP Position */ +#define SYS_GPA_MFPL_PA4MFP_Msk (0xful << SYS_GPA_MFPL_PA4MFP_Pos) /*!< SYS_T::GPA_MFPL: PA4MFP Mask */ + +#define SYS_GPA_MFPL_PA5MFP_Pos (20) /*!< SYS_T::GPA_MFPL: PA5MFP Position */ +#define SYS_GPA_MFPL_PA5MFP_Msk (0xful << SYS_GPA_MFPL_PA5MFP_Pos) /*!< SYS_T::GPA_MFPL: PA5MFP Mask */ + +#define SYS_GPA_MFPL_PA6MFP_Pos (24) /*!< SYS_T::GPA_MFPL: PA6MFP Position */ +#define SYS_GPA_MFPL_PA6MFP_Msk (0xful << SYS_GPA_MFPL_PA6MFP_Pos) /*!< SYS_T::GPA_MFPL: PA6MFP Mask */ + +#define SYS_GPA_MFPL_PA7MFP_Pos (28) /*!< SYS_T::GPA_MFPL: PA7MFP Position */ +#define SYS_GPA_MFPL_PA7MFP_Msk (0xful << SYS_GPA_MFPL_PA7MFP_Pos) /*!< SYS_T::GPA_MFPL: PA7MFP Mask */ + +#define SYS_GPA_MFPH_PA8MFP_Pos (0) /*!< SYS_T::GPA_MFPH: PA8MFP Position */ +#define SYS_GPA_MFPH_PA8MFP_Msk (0xful << SYS_GPA_MFPH_PA8MFP_Pos) /*!< SYS_T::GPA_MFPH: PA8MFP Mask */ + +#define SYS_GPA_MFPH_PA9MFP_Pos (4) /*!< SYS_T::GPA_MFPH: PA9MFP Position */ +#define SYS_GPA_MFPH_PA9MFP_Msk (0xful << SYS_GPA_MFPH_PA9MFP_Pos) /*!< SYS_T::GPA_MFPH: PA9MFP Mask */ + +#define SYS_GPA_MFPH_PA10MFP_Pos (8) /*!< SYS_T::GPA_MFPH: PA10MFP Position */ +#define SYS_GPA_MFPH_PA10MFP_Msk (0xful << SYS_GPA_MFPH_PA10MFP_Pos) /*!< SYS_T::GPA_MFPH: PA10MFP Mask */ + +#define SYS_GPA_MFPH_PA11MFP_Pos (12) /*!< SYS_T::GPA_MFPH: PA11MFP Position */ +#define SYS_GPA_MFPH_PA11MFP_Msk (0xful << SYS_GPA_MFPH_PA11MFP_Pos) /*!< SYS_T::GPA_MFPH: PA11MFP Mask */ + +#define SYS_GPA_MFPH_PA12MFP_Pos (16) /*!< SYS_T::GPA_MFPH: PA12MFP Position */ +#define SYS_GPA_MFPH_PA12MFP_Msk (0xful << SYS_GPA_MFPH_PA12MFP_Pos) /*!< SYS_T::GPA_MFPH: PA12MFP Mask */ + +#define SYS_GPA_MFPH_PA13MFP_Pos (20) /*!< SYS_T::GPA_MFPH: PA13MFP Position */ +#define SYS_GPA_MFPH_PA13MFP_Msk (0xful << SYS_GPA_MFPH_PA13MFP_Pos) /*!< SYS_T::GPA_MFPH: PA13MFP Mask */ + +#define SYS_GPA_MFPH_PA14MFP_Pos (24) /*!< SYS_T::GPA_MFPH: PA14MFP Position */ +#define SYS_GPA_MFPH_PA14MFP_Msk (0xful << SYS_GPA_MFPH_PA14MFP_Pos) /*!< SYS_T::GPA_MFPH: PA14MFP Mask */ + +#define SYS_GPA_MFPH_PA15MFP_Pos (28) /*!< SYS_T::GPA_MFPH: PA15MFP Position */ +#define SYS_GPA_MFPH_PA15MFP_Msk (0xful << SYS_GPA_MFPH_PA15MFP_Pos) /*!< SYS_T::GPA_MFPH: PA15MFP Mask */ + +#define SYS_GPB_MFPL_PB0MFP_Pos (0) /*!< SYS_T::GPB_MFPL: PB0MFP Position */ +#define SYS_GPB_MFPL_PB0MFP_Msk (0xful << SYS_GPB_MFPL_PB0MFP_Pos) /*!< SYS_T::GPB_MFPL: PB0MFP Mask */ + +#define SYS_GPB_MFPL_PB1MFP_Pos (4) /*!< SYS_T::GPB_MFPL: PB1MFP Position */ +#define SYS_GPB_MFPL_PB1MFP_Msk (0xful << SYS_GPB_MFPL_PB1MFP_Pos) /*!< SYS_T::GPB_MFPL: PB1MFP Mask */ + +#define SYS_GPB_MFPL_PB2MFP_Pos (8) /*!< SYS_T::GPB_MFPL: PB2MFP Position */ +#define SYS_GPB_MFPL_PB2MFP_Msk (0xful << SYS_GPB_MFPL_PB2MFP_Pos) /*!< SYS_T::GPB_MFPL: PB2MFP Mask */ + +#define SYS_GPB_MFPL_PB3MFP_Pos (12) /*!< SYS_T::GPB_MFPL: PB3MFP Position */ +#define SYS_GPB_MFPL_PB3MFP_Msk (0xful << SYS_GPB_MFPL_PB3MFP_Pos) /*!< SYS_T::GPB_MFPL: PB3MFP Mask */ + +#define SYS_GPB_MFPL_PB4MFP_Pos (16) /*!< SYS_T::GPB_MFPL: PB4MFP Position */ +#define SYS_GPB_MFPL_PB4MFP_Msk (0xful << SYS_GPB_MFPL_PB4MFP_Pos) /*!< SYS_T::GPB_MFPL: PB4MFP Mask */ + +#define SYS_GPB_MFPL_PB5MFP_Pos (20) /*!< SYS_T::GPB_MFPL: PB5MFP Position */ +#define SYS_GPB_MFPL_PB5MFP_Msk (0xful << SYS_GPB_MFPL_PB5MFP_Pos) /*!< SYS_T::GPB_MFPL: PB5MFP Mask */ + +#define SYS_GPB_MFPL_PB6MFP_Pos (24) /*!< SYS_T::GPB_MFPL: PB6MFP Position */ +#define SYS_GPB_MFPL_PB6MFP_Msk (0xful << SYS_GPB_MFPL_PB6MFP_Pos) /*!< SYS_T::GPB_MFPL: PB6MFP Mask */ + +#define SYS_GPB_MFPL_PB7MFP_Pos (28) /*!< SYS_T::GPB_MFPL: PB7MFP Position */ +#define SYS_GPB_MFPL_PB7MFP_Msk (0xful << SYS_GPB_MFPL_PB7MFP_Pos) /*!< SYS_T::GPB_MFPL: PB7MFP Mask */ + +#define SYS_GPB_MFPH_PB8MFP_Pos (0) /*!< SYS_T::GPB_MFPH: PB8MFP Position */ +#define SYS_GPB_MFPH_PB8MFP_Msk (0xful << SYS_GPB_MFPH_PB8MFP_Pos) /*!< SYS_T::GPB_MFPH: PB8MFP Mask */ + +#define SYS_GPB_MFPH_PB9MFP_Pos (4) /*!< SYS_T::GPB_MFPH: PB9MFP Position */ +#define SYS_GPB_MFPH_PB9MFP_Msk (0xful << SYS_GPB_MFPH_PB9MFP_Pos) /*!< SYS_T::GPB_MFPH: PB9MFP Mask */ + +#define SYS_GPB_MFPH_PB10MFP_Pos (8) /*!< SYS_T::GPB_MFPH: PB10MFP Position */ +#define SYS_GPB_MFPH_PB10MFP_Msk (0xful << SYS_GPB_MFPH_PB10MFP_Pos) /*!< SYS_T::GPB_MFPH: PB10MFP Mask */ + +#define SYS_GPB_MFPH_PB11MFP_Pos (12) /*!< SYS_T::GPB_MFPH: PB11MFP Position */ +#define SYS_GPB_MFPH_PB11MFP_Msk (0xful << SYS_GPB_MFPH_PB11MFP_Pos) /*!< SYS_T::GPB_MFPH: PB11MFP Mask */ + +#define SYS_GPB_MFPH_PB12MFP_Pos (16) /*!< SYS_T::GPB_MFPH: PB12MFP Position */ +#define SYS_GPB_MFPH_PB12MFP_Msk (0xful << SYS_GPB_MFPH_PB12MFP_Pos) /*!< SYS_T::GPB_MFPH: PB12MFP Mask */ + +#define SYS_GPB_MFPH_PB13MFP_Pos (20) /*!< SYS_T::GPB_MFPH: PB13MFP Position */ +#define SYS_GPB_MFPH_PB13MFP_Msk (0xful << SYS_GPB_MFPH_PB13MFP_Pos) /*!< SYS_T::GPB_MFPH: PB13MFP Mask */ + +#define SYS_GPB_MFPH_PB14MFP_Pos (24) /*!< SYS_T::GPB_MFPH: PB14MFP Position */ +#define SYS_GPB_MFPH_PB14MFP_Msk (0xful << SYS_GPB_MFPH_PB14MFP_Pos) /*!< SYS_T::GPB_MFPH: PB14MFP Mask */ + +#define SYS_GPB_MFPH_PB15MFP_Pos (28) /*!< SYS_T::GPB_MFPH: PB15MFP Position */ +#define SYS_GPB_MFPH_PB15MFP_Msk (0xful << SYS_GPB_MFPH_PB15MFP_Pos) /*!< SYS_T::GPB_MFPH: PB15MFP Mask */ + +#define SYS_GPC_MFPL_PC0MFP_Pos (0) /*!< SYS_T::GPC_MFPL: PC0MFP Position */ +#define SYS_GPC_MFPL_PC0MFP_Msk (0xful << SYS_GPC_MFPL_PC0MFP_Pos) /*!< SYS_T::GPC_MFPL: PC0MFP Mask */ + +#define SYS_GPC_MFPL_PC1MFP_Pos (4) /*!< SYS_T::GPC_MFPL: PC1MFP Position */ +#define SYS_GPC_MFPL_PC1MFP_Msk (0xful << SYS_GPC_MFPL_PC1MFP_Pos) /*!< SYS_T::GPC_MFPL: PC1MFP Mask */ + +#define SYS_GPC_MFPL_PC2MFP_Pos (8) /*!< SYS_T::GPC_MFPL: PC2MFP Position */ +#define SYS_GPC_MFPL_PC2MFP_Msk (0xful << SYS_GPC_MFPL_PC2MFP_Pos) /*!< SYS_T::GPC_MFPL: PC2MFP Mask */ + +#define SYS_GPC_MFPL_PC3MFP_Pos (12) /*!< SYS_T::GPC_MFPL: PC3MFP Position */ +#define SYS_GPC_MFPL_PC3MFP_Msk (0xful << SYS_GPC_MFPL_PC3MFP_Pos) /*!< SYS_T::GPC_MFPL: PC3MFP Mask */ + +#define SYS_GPC_MFPL_PC4MFP_Pos (16) /*!< SYS_T::GPC_MFPL: PC4MFP Position */ +#define SYS_GPC_MFPL_PC4MFP_Msk (0xful << SYS_GPC_MFPL_PC4MFP_Pos) /*!< SYS_T::GPC_MFPL: PC4MFP Mask */ + +#define SYS_GPC_MFPL_PC5MFP_Pos (20) /*!< SYS_T::GPC_MFPL: PC5MFP Position */ +#define SYS_GPC_MFPL_PC5MFP_Msk (0xful << SYS_GPC_MFPL_PC5MFP_Pos) /*!< SYS_T::GPC_MFPL: PC5MFP Mask */ + +#define SYS_GPC_MFPL_PC6MFP_Pos (24) /*!< SYS_T::GPC_MFPL: PC6MFP Position */ +#define SYS_GPC_MFPL_PC6MFP_Msk (0xful << SYS_GPC_MFPL_PC6MFP_Pos) /*!< SYS_T::GPC_MFPL: PC6MFP Mask */ + +#define SYS_GPC_MFPL_PC7MFP_Pos (28) /*!< SYS_T::GPC_MFPL: PC7MFP Position */ +#define SYS_GPC_MFPL_PC7MFP_Msk (0xful << SYS_GPC_MFPL_PC7MFP_Pos) /*!< SYS_T::GPC_MFPL: PC7MFP Mask */ + +#define SYS_GPC_MFPH_PC8MFP_Pos (0) /*!< SYS_T::GPC_MFPH: PC8MFP Position */ +#define SYS_GPC_MFPH_PC8MFP_Msk (0xful << SYS_GPC_MFPH_PC8MFP_Pos) /*!< SYS_T::GPC_MFPH: PC8MFP Mask */ + +#define SYS_GPC_MFPH_PC9MFP_Pos (4) /*!< SYS_T::GPC_MFPH: PC9MFP Position */ +#define SYS_GPC_MFPH_PC9MFP_Msk (0xful << SYS_GPC_MFPH_PC9MFP_Pos) /*!< SYS_T::GPC_MFPH: PC9MFP Mask */ + +#define SYS_GPC_MFPH_PC10MFP_Pos (8) /*!< SYS_T::GPC_MFPH: PC10MFP Position */ +#define SYS_GPC_MFPH_PC10MFP_Msk (0xful << SYS_GPC_MFPH_PC10MFP_Pos) /*!< SYS_T::GPC_MFPH: PC10MFP Mask */ + +#define SYS_GPC_MFPH_PC11MFP_Pos (12) /*!< SYS_T::GPC_MFPH: PC11MFP Position */ +#define SYS_GPC_MFPH_PC11MFP_Msk (0xful << SYS_GPC_MFPH_PC11MFP_Pos) /*!< SYS_T::GPC_MFPH: PC11MFP Mask */ + +#define SYS_GPC_MFPH_PC12MFP_Pos (16) /*!< SYS_T::GPC_MFPH: PC12MFP Position */ +#define SYS_GPC_MFPH_PC12MFP_Msk (0xful << SYS_GPC_MFPH_PC12MFP_Pos) /*!< SYS_T::GPC_MFPH: PC12MFP Mask */ + +#define SYS_GPC_MFPH_PC13MFP_Pos (20) /*!< SYS_T::GPC_MFPH: PC13MFP Position */ +#define SYS_GPC_MFPH_PC13MFP_Msk (0xful << SYS_GPC_MFPH_PC13MFP_Pos) /*!< SYS_T::GPC_MFPH: PC13MFP Mask */ + +#define SYS_GPD_MFPL_PD0MFP_Pos (0) /*!< SYS_T::GPD_MFPL: PD0MFP Position */ +#define SYS_GPD_MFPL_PD0MFP_Msk (0xful << SYS_GPD_MFPL_PD0MFP_Pos) /*!< SYS_T::GPD_MFPL: PD0MFP Mask */ + +#define SYS_GPD_MFPL_PD1MFP_Pos (4) /*!< SYS_T::GPD_MFPL: PD1MFP Position */ +#define SYS_GPD_MFPL_PD1MFP_Msk (0xful << SYS_GPD_MFPL_PD1MFP_Pos) /*!< SYS_T::GPD_MFPL: PD1MFP Mask */ + +#define SYS_GPD_MFPL_PD2MFP_Pos (8) /*!< SYS_T::GPD_MFPL: PD2MFP Position */ +#define SYS_GPD_MFPL_PD2MFP_Msk (0xful << SYS_GPD_MFPL_PD2MFP_Pos) /*!< SYS_T::GPD_MFPL: PD2MFP Mask */ + +#define SYS_GPD_MFPL_PD3MFP_Pos (12) /*!< SYS_T::GPD_MFPL: PD3MFP Position */ +#define SYS_GPD_MFPL_PD3MFP_Msk (0xful << SYS_GPD_MFPL_PD3MFP_Pos) /*!< SYS_T::GPD_MFPL: PD3MFP Mask */ + +#define SYS_GPD_MFPL_PD4MFP_Pos (16) /*!< SYS_T::GPD_MFPL: PD4MFP Position */ +#define SYS_GPD_MFPL_PD4MFP_Msk (0xful << SYS_GPD_MFPL_PD4MFP_Pos) /*!< SYS_T::GPD_MFPL: PD4MFP Mask */ + +#define SYS_GPD_MFPL_PD5MFP_Pos (20) /*!< SYS_T::GPD_MFPL: PD5MFP Position */ +#define SYS_GPD_MFPL_PD5MFP_Msk (0xful << SYS_GPD_MFPL_PD5MFP_Pos) /*!< SYS_T::GPD_MFPL: PD5MFP Mask */ + +#define SYS_GPD_MFPL_PD6MFP_Pos (24) /*!< SYS_T::GPD_MFPL: PD6MFP Position */ +#define SYS_GPD_MFPL_PD6MFP_Msk (0xful << SYS_GPD_MFPL_PD6MFP_Pos) /*!< SYS_T::GPD_MFPL: PD6MFP Mask */ + +#define SYS_GPD_MFPL_PD7MFP_Pos (28) /*!< SYS_T::GPD_MFPL: PD7MFP Position */ +#define SYS_GPD_MFPL_PD7MFP_Msk (0xful << SYS_GPD_MFPL_PD7MFP_Pos) /*!< SYS_T::GPD_MFPL: PD7MFP Mask */ + +#define SYS_GPD_MFPH_PD8MFP_Pos (0) /*!< SYS_T::GPD_MFPH: PD8MFP Position */ +#define SYS_GPD_MFPH_PD8MFP_Msk (0xful << SYS_GPD_MFPH_PD8MFP_Pos) /*!< SYS_T::GPD_MFPH: PD8MFP Mask */ + +#define SYS_GPD_MFPH_PD9MFP_Pos (4) /*!< SYS_T::GPD_MFPH: PD9MFP Position */ +#define SYS_GPD_MFPH_PD9MFP_Msk (0xful << SYS_GPD_MFPH_PD9MFP_Pos) /*!< SYS_T::GPD_MFPH: PD9MFP Mask */ + +#define SYS_GPD_MFPH_PD10MFP_Pos (8) /*!< SYS_T::GPD_MFPH: PD10MFP Position */ +#define SYS_GPD_MFPH_PD10MFP_Msk (0xful << SYS_GPD_MFPH_PD10MFP_Pos) /*!< SYS_T::GPD_MFPH: PD10MFP Mask */ + +#define SYS_GPD_MFPH_PD11MFP_Pos (12) /*!< SYS_T::GPD_MFPH: PD11MFP Position */ +#define SYS_GPD_MFPH_PD11MFP_Msk (0xful << SYS_GPD_MFPH_PD11MFP_Pos) /*!< SYS_T::GPD_MFPH: PD11MFP Mask */ + +#define SYS_GPD_MFPH_PD12MFP_Pos (16) /*!< SYS_T::GPD_MFPH: PD12MFP Position */ +#define SYS_GPD_MFPH_PD12MFP_Msk (0xful << SYS_GPD_MFPH_PD12MFP_Pos) /*!< SYS_T::GPD_MFPH: PD12MFP Mask */ + +#define SYS_GPD_MFPH_PD14MFP_Pos (24) /*!< SYS_T::GPD_MFPH: PD14MFP Position */ +#define SYS_GPD_MFPH_PD14MFP_Msk (0xful << SYS_GPD_MFPH_PD14MFP_Pos) /*!< SYS_T::GPD_MFPH: PD14MFP Mask */ + +#define SYS_GPE_MFPL_PE0MFP_Pos (0) /*!< SYS_T::GPE_MFPL: PE0MFP Position */ +#define SYS_GPE_MFPL_PE0MFP_Msk (0xful << SYS_GPE_MFPL_PE0MFP_Pos) /*!< SYS_T::GPE_MFPL: PE0MFP Mask */ + +#define SYS_GPE_MFPL_PE1MFP_Pos (4) /*!< SYS_T::GPE_MFPL: PE1MFP Position */ +#define SYS_GPE_MFPL_PE1MFP_Msk (0xful << SYS_GPE_MFPL_PE1MFP_Pos) /*!< SYS_T::GPE_MFPL: PE1MFP Mask */ + +#define SYS_GPE_MFPL_PE2MFP_Pos (8) /*!< SYS_T::GPE_MFPL: PE2MFP Position */ +#define SYS_GPE_MFPL_PE2MFP_Msk (0xful << SYS_GPE_MFPL_PE2MFP_Pos) /*!< SYS_T::GPE_MFPL: PE2MFP Mask */ + +#define SYS_GPE_MFPL_PE3MFP_Pos (12) /*!< SYS_T::GPE_MFPL: PE3MFP Position */ +#define SYS_GPE_MFPL_PE3MFP_Msk (0xful << SYS_GPE_MFPL_PE3MFP_Pos) /*!< SYS_T::GPE_MFPL: PE3MFP Mask */ + +#define SYS_GPE_MFPL_PE4MFP_Pos (16) /*!< SYS_T::GPE_MFPL: PE4MFP Position */ +#define SYS_GPE_MFPL_PE4MFP_Msk (0xful << SYS_GPE_MFPL_PE4MFP_Pos) /*!< SYS_T::GPE_MFPL: PE4MFP Mask */ + +#define SYS_GPE_MFPL_PE5MFP_Pos (20) /*!< SYS_T::GPE_MFPL: PE5MFP Position */ +#define SYS_GPE_MFPL_PE5MFP_Msk (0xful << SYS_GPE_MFPL_PE5MFP_Pos) /*!< SYS_T::GPE_MFPL: PE5MFP Mask */ + +#define SYS_GPE_MFPL_PE6MFP_Pos (24) /*!< SYS_T::GPE_MFPL: PE6MFP Position */ +#define SYS_GPE_MFPL_PE6MFP_Msk (0xful << SYS_GPE_MFPL_PE6MFP_Pos) /*!< SYS_T::GPE_MFPL: PE6MFP Mask */ + +#define SYS_GPE_MFPL_PE7MFP_Pos (28) /*!< SYS_T::GPE_MFPL: PE7MFP Position */ +#define SYS_GPE_MFPL_PE7MFP_Msk (0xful << SYS_GPE_MFPL_PE7MFP_Pos) /*!< SYS_T::GPE_MFPL: PE7MFP Mask */ + +#define SYS_GPE_MFPH_PE8MFP_Pos (0) /*!< SYS_T::GPE_MFPH: PE8MFP Position */ +#define SYS_GPE_MFPH_PE8MFP_Msk (0xful << SYS_GPE_MFPH_PE8MFP_Pos) /*!< SYS_T::GPE_MFPH: PE8MFP Mask */ + +#define SYS_GPE_MFPH_PE9MFP_Pos (4) /*!< SYS_T::GPE_MFPH: PE9MFP Position */ +#define SYS_GPE_MFPH_PE9MFP_Msk (0xful << SYS_GPE_MFPH_PE9MFP_Pos) /*!< SYS_T::GPE_MFPH: PE9MFP Mask */ + +#define SYS_GPE_MFPH_PE10MFP_Pos (8) /*!< SYS_T::GPE_MFPH: PE10MFP Position */ +#define SYS_GPE_MFPH_PE10MFP_Msk (0xful << SYS_GPE_MFPH_PE10MFP_Pos) /*!< SYS_T::GPE_MFPH: PE10MFP Mask */ + +#define SYS_GPE_MFPH_PE11MFP_Pos (12) /*!< SYS_T::GPE_MFPH: PE11MFP Position */ +#define SYS_GPE_MFPH_PE11MFP_Msk (0xful << SYS_GPE_MFPH_PE11MFP_Pos) /*!< SYS_T::GPE_MFPH: PE11MFP Mask */ + +#define SYS_GPE_MFPH_PE12MFP_Pos (16) /*!< SYS_T::GPE_MFPH: PE12MFP Position */ +#define SYS_GPE_MFPH_PE12MFP_Msk (0xful << SYS_GPE_MFPH_PE12MFP_Pos) /*!< SYS_T::GPE_MFPH: PE12MFP Mask */ + +#define SYS_GPE_MFPH_PE13MFP_Pos (20) /*!< SYS_T::GPE_MFPH: PE13MFP Position */ +#define SYS_GPE_MFPH_PE13MFP_Msk (0xful << SYS_GPE_MFPH_PE13MFP_Pos) /*!< SYS_T::GPE_MFPH: PE13MFP Mask */ + +#define SYS_GPE_MFPH_PE14MFP_Pos (24) /*!< SYS_T::GPE_MFPH: PE14MFP Position */ +#define SYS_GPE_MFPH_PE14MFP_Msk (0xful << SYS_GPE_MFPH_PE14MFP_Pos) /*!< SYS_T::GPE_MFPH: PE14MFP Mask */ + +#define SYS_GPE_MFPH_PE15MFP_Pos (28) /*!< SYS_T::GPE_MFPH: PE15MFP Position */ +#define SYS_GPE_MFPH_PE15MFP_Msk (0xful << SYS_GPE_MFPH_PE15MFP_Pos) /*!< SYS_T::GPE_MFPH: PE15MFP Mask */ + +#define SYS_GPF_MFPL_PF0MFP_Pos (0) /*!< SYS_T::GPF_MFPL: PF0MFP Position */ +#define SYS_GPF_MFPL_PF0MFP_Msk (0xful << SYS_GPF_MFPL_PF0MFP_Pos) /*!< SYS_T::GPF_MFPL: PF0MFP Mask */ + +#define SYS_GPF_MFPL_PF1MFP_Pos (4) /*!< SYS_T::GPF_MFPL: PF1MFP Position */ +#define SYS_GPF_MFPL_PF1MFP_Msk (0xful << SYS_GPF_MFPL_PF1MFP_Pos) /*!< SYS_T::GPF_MFPL: PF1MFP Mask */ + +#define SYS_GPF_MFPL_PF2MFP_Pos (8) /*!< SYS_T::GPF_MFPL: PF2MFP Position */ +#define SYS_GPF_MFPL_PF2MFP_Msk (0xful << SYS_GPF_MFPL_PF2MFP_Pos) /*!< SYS_T::GPF_MFPL: PF2MFP Mask */ + +#define SYS_GPF_MFPL_PF3MFP_Pos (12) /*!< SYS_T::GPF_MFPL: PF3MFP Position */ +#define SYS_GPF_MFPL_PF3MFP_Msk (0xful << SYS_GPF_MFPL_PF3MFP_Pos) /*!< SYS_T::GPF_MFPL: PF3MFP Mask */ + +#define SYS_GPF_MFPL_PF4MFP_Pos (16) /*!< SYS_T::GPF_MFPL: PF4MFP Position */ +#define SYS_GPF_MFPL_PF4MFP_Msk (0xful << SYS_GPF_MFPL_PF4MFP_Pos) /*!< SYS_T::GPF_MFPL: PF4MFP Mask */ + +#define SYS_GPF_MFPL_PF5MFP_Pos (20) /*!< SYS_T::GPF_MFPL: PF5MFP Position */ +#define SYS_GPF_MFPL_PF5MFP_Msk (0xful << SYS_GPF_MFPL_PF5MFP_Pos) /*!< SYS_T::GPF_MFPL: PF5MFP Mask */ + +#define SYS_GPF_MFPL_PF6MFP_Pos (24) /*!< SYS_T::GPF_MFPL: PF6MFP Position */ +#define SYS_GPF_MFPL_PF6MFP_Msk (0xful << SYS_GPF_MFPL_PF6MFP_Pos) /*!< SYS_T::GPF_MFPL: PF6MFP Mask */ + +#define SYS_GPF_MFPL_PF7MFP_Pos (28) /*!< SYS_T::GPF_MFPL: PF7MFP Position */ +#define SYS_GPF_MFPL_PF7MFP_Msk (0xful << SYS_GPF_MFPL_PF7MFP_Pos) /*!< SYS_T::GPF_MFPL: PF7MFP Mask */ + +#define SYS_GPF_MFPH_PF8MFP_Pos (0) /*!< SYS_T::GPF_MFPH: PF8MFP Position */ +#define SYS_GPF_MFPH_PF8MFP_Msk (0xful << SYS_GPF_MFPH_PF8MFP_Pos) /*!< SYS_T::GPF_MFPH: PF8MFP Mask */ + +#define SYS_GPF_MFPH_PF9MFP_Pos (4) /*!< SYS_T::GPF_MFPH: PF9MFP Position */ +#define SYS_GPF_MFPH_PF9MFP_Msk (0xful << SYS_GPF_MFPH_PF9MFP_Pos) /*!< SYS_T::GPF_MFPH: PF9MFP Mask */ + +#define SYS_GPF_MFPH_PF10MFP_Pos (8) /*!< SYS_T::GPF_MFPH: PF10MFP Position */ +#define SYS_GPF_MFPH_PF10MFP_Msk (0xful << SYS_GPF_MFPH_PF10MFP_Pos) /*!< SYS_T::GPF_MFPH: PF10MFP Mask */ + +#define SYS_GPF_MFPH_PF11MFP_Pos (12) /*!< SYS_T::GPF_MFPH: PF11MFP Position */ +#define SYS_GPF_MFPH_PF11MFP_Msk (0xful << SYS_GPF_MFPH_PF11MFP_Pos) /*!< SYS_T::GPF_MFPH: PF11MFP Mask */ + +#define SYS_GPG_MFPL_PG2MFP_Pos (8) /*!< SYS_T::GPG_MFPL: PG2MFP Position */ +#define SYS_GPG_MFPL_PG2MFP_Msk (0xful << SYS_GPG_MFPL_PG2MFP_Pos) /*!< SYS_T::GPG_MFPL: PG2MFP Mask */ + +#define SYS_GPG_MFPL_PG3MFP_Pos (12) /*!< SYS_T::GPG_MFPL: PG3MFP Position */ +#define SYS_GPG_MFPL_PG3MFP_Msk (0xful << SYS_GPG_MFPL_PG3MFP_Pos) /*!< SYS_T::GPG_MFPL: PG3MFP Mask */ + +#define SYS_GPG_MFPL_PG4MFP_Pos (16) /*!< SYS_T::GPG_MFPL: PG4MFP Position */ +#define SYS_GPG_MFPL_PG4MFP_Msk (0xful << SYS_GPG_MFPL_PG4MFP_Pos) /*!< SYS_T::GPG_MFPL: PG4MFP Mask */ + +#define SYS_GPG_MFPH_PG9MFP_Pos (4) /*!< SYS_T::GPG_MFPH: PG9MFP Position */ +#define SYS_GPG_MFPH_PG9MFP_Msk (0xful << SYS_GPG_MFPH_PG9MFP_Pos) /*!< SYS_T::GPG_MFPH: PG9MFP Mask */ + +#define SYS_GPG_MFPH_PG10MFP_Pos (8) /*!< SYS_T::GPG_MFPH: PG10MFP Position */ +#define SYS_GPG_MFPH_PG10MFP_Msk (0xful << SYS_GPG_MFPH_PG10MFP_Pos) /*!< SYS_T::GPG_MFPH: PG10MFP Mask */ + +#define SYS_GPG_MFPH_PG11MFP_Pos (12) /*!< SYS_T::GPG_MFPH: PG11MFP Position */ +#define SYS_GPG_MFPH_PG11MFP_Msk (0xful << SYS_GPG_MFPH_PG11MFP_Pos) /*!< SYS_T::GPG_MFPH: PG11MFP Mask */ + +#define SYS_GPG_MFPH_PG12MFP_Pos (16) /*!< SYS_T::GPG_MFPH: PG12MFP Position */ +#define SYS_GPG_MFPH_PG12MFP_Msk (0xful << SYS_GPG_MFPH_PG12MFP_Pos) /*!< SYS_T::GPG_MFPH: PG12MFP Mask */ + +#define SYS_GPG_MFPH_PG13MFP_Pos (20) /*!< SYS_T::GPG_MFPH: PG13MFP Position */ +#define SYS_GPG_MFPH_PG13MFP_Msk (0xful << SYS_GPG_MFPH_PG13MFP_Pos) /*!< SYS_T::GPG_MFPH: PG13MFP Mask */ + +#define SYS_GPG_MFPH_PG14MFP_Pos (24) /*!< SYS_T::GPG_MFPH: PG14MFP Position */ +#define SYS_GPG_MFPH_PG14MFP_Msk (0xful << SYS_GPG_MFPH_PG14MFP_Pos) /*!< SYS_T::GPG_MFPH: PG14MFP Mask */ + +#define SYS_GPG_MFPH_PG15MFP_Pos (28) /*!< SYS_T::GPG_MFPH: PG15MFP Position */ +#define SYS_GPG_MFPH_PG15MFP_Msk (0xful << SYS_GPG_MFPH_PG15MFP_Pos) /*!< SYS_T::GPG_MFPH: PG15MFP Mask */ + +#define SYS_GPH_MFPL_PH4MFP_Pos (16) /*!< SYS_T::GPH_MFPL: PH4MFP Position */ +#define SYS_GPH_MFPL_PH4MFP_Msk (0xful << SYS_GPH_MFPL_PH4MFP_Pos) /*!< SYS_T::GPH_MFPL: PH4MFP Mask */ + +#define SYS_GPH_MFPL_PH5MFP_Pos (20) /*!< SYS_T::GPH_MFPL: PH5MFP Position */ +#define SYS_GPH_MFPL_PH5MFP_Msk (0xful << SYS_GPH_MFPL_PH5MFP_Pos) /*!< SYS_T::GPH_MFPL: PH5MFP Mask */ + +#define SYS_GPH_MFPL_PH6MFP_Pos (24) /*!< SYS_T::GPH_MFPL: PH6MFP Position */ +#define SYS_GPH_MFPL_PH6MFP_Msk (0xful << SYS_GPH_MFPL_PH6MFP_Pos) /*!< SYS_T::GPH_MFPL: PH6MFP Mask */ + +#define SYS_GPH_MFPL_PH7MFP_Pos (28) /*!< SYS_T::GPH_MFPL: PH7MFP Position */ +#define SYS_GPH_MFPL_PH7MFP_Msk (0xful << SYS_GPH_MFPL_PH7MFP_Pos) /*!< SYS_T::GPH_MFPL: PH7MFP Mask */ + +#define SYS_GPH_MFPH_PH8MFP_Pos (0) /*!< SYS_T::GPH_MFPH: PH8MFP Position */ +#define SYS_GPH_MFPH_PH8MFP_Msk (0xful << SYS_GPH_MFPH_PH8MFP_Pos) /*!< SYS_T::GPH_MFPH: PH8MFP Mask */ + +#define SYS_GPH_MFPH_PH9MFP_Pos (4) /*!< SYS_T::GPH_MFPH: PH9MFP Position */ +#define SYS_GPH_MFPH_PH9MFP_Msk (0xful << SYS_GPH_MFPH_PH9MFP_Pos) /*!< SYS_T::GPH_MFPH: PH9MFP Mask */ + +#define SYS_GPH_MFPH_PH10MFP_Pos (8) /*!< SYS_T::GPH_MFPH: PH10MFP Position */ +#define SYS_GPH_MFPH_PH10MFP_Msk (0xful << SYS_GPH_MFPH_PH10MFP_Pos) /*!< SYS_T::GPH_MFPH: PH10MFP Mask */ + +#define SYS_GPH_MFPH_PH11MFP_Pos (12) /*!< SYS_T::GPH_MFPH: PH11MFP Position */ +#define SYS_GPH_MFPH_PH11MFP_Msk (0xful << SYS_GPH_MFPH_PH11MFP_Pos) /*!< SYS_T::GPH_MFPH: PH11MFP Mask */ + +#define SYS_GPA_MFOS_MFOS0_Pos (0) /*!< SYS_T::GPA_MFOS: MFOS0 Position */ +#define SYS_GPA_MFOS_MFOS0_Msk (0x1ul << SYS_GPA_MFOS_MFOS0_Pos) /*!< SYS_T::GPA_MFOS: MFOS0 Mask */ + +#define SYS_GPA_MFOS_MFOS1_Pos (1) /*!< SYS_T::GPA_MFOS: MFOS1 Position */ +#define SYS_GPA_MFOS_MFOS1_Msk (0x1ul << SYS_GPA_MFOS_MFOS1_Pos) /*!< SYS_T::GPA_MFOS: MFOS1 Mask */ + +#define SYS_GPA_MFOS_MFOS2_Pos (2) /*!< SYS_T::GPA_MFOS: MFOS2 Position */ +#define SYS_GPA_MFOS_MFOS2_Msk (0x1ul << SYS_GPA_MFOS_MFOS2_Pos) /*!< SYS_T::GPA_MFOS: MFOS2 Mask */ + +#define SYS_GPA_MFOS_MFOS3_Pos (3) /*!< SYS_T::GPA_MFOS: MFOS3 Position */ +#define SYS_GPA_MFOS_MFOS3_Msk (0x1ul << SYS_GPA_MFOS_MFOS3_Pos) /*!< SYS_T::GPA_MFOS: MFOS3 Mask */ + +#define SYS_GPA_MFOS_MFOS4_Pos (4) /*!< SYS_T::GPA_MFOS: MFOS4 Position */ +#define SYS_GPA_MFOS_MFOS4_Msk (0x1ul << SYS_GPA_MFOS_MFOS4_Pos) /*!< SYS_T::GPA_MFOS: MFOS4 Mask */ + +#define SYS_GPA_MFOS_MFOS5_Pos (5) /*!< SYS_T::GPA_MFOS: MFOS5 Position */ +#define SYS_GPA_MFOS_MFOS5_Msk (0x1ul << SYS_GPA_MFOS_MFOS5_Pos) /*!< SYS_T::GPA_MFOS: MFOS5 Mask */ + +#define SYS_GPA_MFOS_MFOS6_Pos (6) /*!< SYS_T::GPA_MFOS: MFOS6 Position */ +#define SYS_GPA_MFOS_MFOS6_Msk (0x1ul << SYS_GPA_MFOS_MFOS6_Pos) /*!< SYS_T::GPA_MFOS: MFOS6 Mask */ + +#define SYS_GPA_MFOS_MFOS7_Pos (7) /*!< SYS_T::GPA_MFOS: MFOS7 Position */ +#define SYS_GPA_MFOS_MFOS7_Msk (0x1ul << SYS_GPA_MFOS_MFOS7_Pos) /*!< SYS_T::GPA_MFOS: MFOS7 Mask */ + +#define SYS_GPA_MFOS_MFOS8_Pos (8) /*!< SYS_T::GPA_MFOS: MFOS8 Position */ +#define SYS_GPA_MFOS_MFOS8_Msk (0x1ul << SYS_GPA_MFOS_MFOS8_Pos) /*!< SYS_T::GPA_MFOS: MFOS8 Mask */ + +#define SYS_GPA_MFOS_MFOS9_Pos (9) /*!< SYS_T::GPA_MFOS: MFOS9 Position */ +#define SYS_GPA_MFOS_MFOS9_Msk (0x1ul << SYS_GPA_MFOS_MFOS9_Pos) /*!< SYS_T::GPA_MFOS: MFOS9 Mask */ + +#define SYS_GPA_MFOS_MFOS10_Pos (10) /*!< SYS_T::GPA_MFOS: MFOS10 Position */ +#define SYS_GPA_MFOS_MFOS10_Msk (0x1ul << SYS_GPA_MFOS_MFOS10_Pos) /*!< SYS_T::GPA_MFOS: MFOS10 Mask */ + +#define SYS_GPA_MFOS_MFOS11_Pos (11) /*!< SYS_T::GPA_MFOS: MFOS11 Position */ +#define SYS_GPA_MFOS_MFOS11_Msk (0x1ul << SYS_GPA_MFOS_MFOS11_Pos) /*!< SYS_T::GPA_MFOS: MFOS11 Mask */ + +#define SYS_GPA_MFOS_MFOS12_Pos (12) /*!< SYS_T::GPA_MFOS: MFOS12 Position */ +#define SYS_GPA_MFOS_MFOS12_Msk (0x1ul << SYS_GPA_MFOS_MFOS12_Pos) /*!< SYS_T::GPA_MFOS: MFOS12 Mask */ + +#define SYS_GPA_MFOS_MFOS13_Pos (13) /*!< SYS_T::GPA_MFOS: MFOS13 Position */ +#define SYS_GPA_MFOS_MFOS13_Msk (0x1ul << SYS_GPA_MFOS_MFOS13_Pos) /*!< SYS_T::GPA_MFOS: MFOS13 Mask */ + +#define SYS_GPA_MFOS_MFOS14_Pos (14) /*!< SYS_T::GPA_MFOS: MFOS14 Position */ +#define SYS_GPA_MFOS_MFOS14_Msk (0x1ul << SYS_GPA_MFOS_MFOS14_Pos) /*!< SYS_T::GPA_MFOS: MFOS14 Mask */ + +#define SYS_GPA_MFOS_MFOS15_Pos (15) /*!< SYS_T::GPA_MFOS: MFOS15 Position */ +#define SYS_GPA_MFOS_MFOS15_Msk (0x1ul << SYS_GPA_MFOS_MFOS15_Pos) /*!< SYS_T::GPA_MFOS: MFOS15 Mask */ + +#define SYS_GPB_MFOS_MFOS0_Pos (0) /*!< SYS_T::GPB_MFOS: MFOS0 Position */ +#define SYS_GPB_MFOS_MFOS0_Msk (0x1ul << SYS_GPB_MFOS_MFOS0_Pos) /*!< SYS_T::GPB_MFOS: MFOS0 Mask */ + +#define SYS_GPB_MFOS_MFOS1_Pos (1) /*!< SYS_T::GPB_MFOS: MFOS1 Position */ +#define SYS_GPB_MFOS_MFOS1_Msk (0x1ul << SYS_GPB_MFOS_MFOS1_Pos) /*!< SYS_T::GPB_MFOS: MFOS1 Mask */ + +#define SYS_GPB_MFOS_MFOS2_Pos (2) /*!< SYS_T::GPB_MFOS: MFOS2 Position */ +#define SYS_GPB_MFOS_MFOS2_Msk (0x1ul << SYS_GPB_MFOS_MFOS2_Pos) /*!< SYS_T::GPB_MFOS: MFOS2 Mask */ + +#define SYS_GPB_MFOS_MFOS3_Pos (3) /*!< SYS_T::GPB_MFOS: MFOS3 Position */ +#define SYS_GPB_MFOS_MFOS3_Msk (0x1ul << SYS_GPB_MFOS_MFOS3_Pos) /*!< SYS_T::GPB_MFOS: MFOS3 Mask */ + +#define SYS_GPB_MFOS_MFOS4_Pos (4) /*!< SYS_T::GPB_MFOS: MFOS4 Position */ +#define SYS_GPB_MFOS_MFOS4_Msk (0x1ul << SYS_GPB_MFOS_MFOS4_Pos) /*!< SYS_T::GPB_MFOS: MFOS4 Mask */ + +#define SYS_GPB_MFOS_MFOS5_Pos (5) /*!< SYS_T::GPB_MFOS: MFOS5 Position */ +#define SYS_GPB_MFOS_MFOS5_Msk (0x1ul << SYS_GPB_MFOS_MFOS5_Pos) /*!< SYS_T::GPB_MFOS: MFOS5 Mask */ + +#define SYS_GPB_MFOS_MFOS6_Pos (6) /*!< SYS_T::GPB_MFOS: MFOS6 Position */ +#define SYS_GPB_MFOS_MFOS6_Msk (0x1ul << SYS_GPB_MFOS_MFOS6_Pos) /*!< SYS_T::GPB_MFOS: MFOS6 Mask */ + +#define SYS_GPB_MFOS_MFOS7_Pos (7) /*!< SYS_T::GPB_MFOS: MFOS7 Position */ +#define SYS_GPB_MFOS_MFOS7_Msk (0x1ul << SYS_GPB_MFOS_MFOS7_Pos) /*!< SYS_T::GPB_MFOS: MFOS7 Mask */ + +#define SYS_GPB_MFOS_MFOS8_Pos (8) /*!< SYS_T::GPB_MFOS: MFOS8 Position */ +#define SYS_GPB_MFOS_MFOS8_Msk (0x1ul << SYS_GPB_MFOS_MFOS8_Pos) /*!< SYS_T::GPB_MFOS: MFOS8 Mask */ + +#define SYS_GPB_MFOS_MFOS9_Pos (9) /*!< SYS_T::GPB_MFOS: MFOS9 Position */ +#define SYS_GPB_MFOS_MFOS9_Msk (0x1ul << SYS_GPB_MFOS_MFOS9_Pos) /*!< SYS_T::GPB_MFOS: MFOS9 Mask */ + +#define SYS_GPB_MFOS_MFOS10_Pos (10) /*!< SYS_T::GPB_MFOS: MFOS10 Position */ +#define SYS_GPB_MFOS_MFOS10_Msk (0x1ul << SYS_GPB_MFOS_MFOS10_Pos) /*!< SYS_T::GPB_MFOS: MFOS10 Mask */ + +#define SYS_GPB_MFOS_MFOS11_Pos (11) /*!< SYS_T::GPB_MFOS: MFOS11 Position */ +#define SYS_GPB_MFOS_MFOS11_Msk (0x1ul << SYS_GPB_MFOS_MFOS11_Pos) /*!< SYS_T::GPB_MFOS: MFOS11 Mask */ + +#define SYS_GPB_MFOS_MFOS12_Pos (12) /*!< SYS_T::GPB_MFOS: MFOS12 Position */ +#define SYS_GPB_MFOS_MFOS12_Msk (0x1ul << SYS_GPB_MFOS_MFOS12_Pos) /*!< SYS_T::GPB_MFOS: MFOS12 Mask */ + +#define SYS_GPB_MFOS_MFOS13_Pos (13) /*!< SYS_T::GPB_MFOS: MFOS13 Position */ +#define SYS_GPB_MFOS_MFOS13_Msk (0x1ul << SYS_GPB_MFOS_MFOS13_Pos) /*!< SYS_T::GPB_MFOS: MFOS13 Mask */ + +#define SYS_GPB_MFOS_MFOS14_Pos (14) /*!< SYS_T::GPB_MFOS: MFOS14 Position */ +#define SYS_GPB_MFOS_MFOS14_Msk (0x1ul << SYS_GPB_MFOS_MFOS14_Pos) /*!< SYS_T::GPB_MFOS: MFOS14 Mask */ + +#define SYS_GPB_MFOS_MFOS15_Pos (15) /*!< SYS_T::GPB_MFOS: MFOS15 Position */ +#define SYS_GPB_MFOS_MFOS15_Msk (0x1ul << SYS_GPB_MFOS_MFOS15_Pos) /*!< SYS_T::GPB_MFOS: MFOS15 Mask */ + +#define SYS_GPC_MFOS_MFOS0_Pos (0) /*!< SYS_T::GPC_MFOS: MFOS0 Position */ +#define SYS_GPC_MFOS_MFOS0_Msk (0x1ul << SYS_GPC_MFOS_MFOS0_Pos) /*!< SYS_T::GPC_MFOS: MFOS0 Mask */ + +#define SYS_GPC_MFOS_MFOS1_Pos (1) /*!< SYS_T::GPC_MFOS: MFOS1 Position */ +#define SYS_GPC_MFOS_MFOS1_Msk (0x1ul << SYS_GPC_MFOS_MFOS1_Pos) /*!< SYS_T::GPC_MFOS: MFOS1 Mask */ + +#define SYS_GPC_MFOS_MFOS2_Pos (2) /*!< SYS_T::GPC_MFOS: MFOS2 Position */ +#define SYS_GPC_MFOS_MFOS2_Msk (0x1ul << SYS_GPC_MFOS_MFOS2_Pos) /*!< SYS_T::GPC_MFOS: MFOS2 Mask */ + +#define SYS_GPC_MFOS_MFOS3_Pos (3) /*!< SYS_T::GPC_MFOS: MFOS3 Position */ +#define SYS_GPC_MFOS_MFOS3_Msk (0x1ul << SYS_GPC_MFOS_MFOS3_Pos) /*!< SYS_T::GPC_MFOS: MFOS3 Mask */ + +#define SYS_GPC_MFOS_MFOS4_Pos (4) /*!< SYS_T::GPC_MFOS: MFOS4 Position */ +#define SYS_GPC_MFOS_MFOS4_Msk (0x1ul << SYS_GPC_MFOS_MFOS4_Pos) /*!< SYS_T::GPC_MFOS: MFOS4 Mask */ + +#define SYS_GPC_MFOS_MFOS5_Pos (5) /*!< SYS_T::GPC_MFOS: MFOS5 Position */ +#define SYS_GPC_MFOS_MFOS5_Msk (0x1ul << SYS_GPC_MFOS_MFOS5_Pos) /*!< SYS_T::GPC_MFOS: MFOS5 Mask */ + +#define SYS_GPC_MFOS_MFOS6_Pos (6) /*!< SYS_T::GPC_MFOS: MFOS6 Position */ +#define SYS_GPC_MFOS_MFOS6_Msk (0x1ul << SYS_GPC_MFOS_MFOS6_Pos) /*!< SYS_T::GPC_MFOS: MFOS6 Mask */ + +#define SYS_GPC_MFOS_MFOS7_Pos (7) /*!< SYS_T::GPC_MFOS: MFOS7 Position */ +#define SYS_GPC_MFOS_MFOS7_Msk (0x1ul << SYS_GPC_MFOS_MFOS7_Pos) /*!< SYS_T::GPC_MFOS: MFOS7 Mask */ + +#define SYS_GPC_MFOS_MFOS8_Pos (8) /*!< SYS_T::GPC_MFOS: MFOS8 Position */ +#define SYS_GPC_MFOS_MFOS8_Msk (0x1ul << SYS_GPC_MFOS_MFOS8_Pos) /*!< SYS_T::GPC_MFOS: MFOS8 Mask */ + +#define SYS_GPC_MFOS_MFOS9_Pos (9) /*!< SYS_T::GPC_MFOS: MFOS9 Position */ +#define SYS_GPC_MFOS_MFOS9_Msk (0x1ul << SYS_GPC_MFOS_MFOS9_Pos) /*!< SYS_T::GPC_MFOS: MFOS9 Mask */ + +#define SYS_GPC_MFOS_MFOS10_Pos (10) /*!< SYS_T::GPC_MFOS: MFOS10 Position */ +#define SYS_GPC_MFOS_MFOS10_Msk (0x1ul << SYS_GPC_MFOS_MFOS10_Pos) /*!< SYS_T::GPC_MFOS: MFOS10 Mask */ + +#define SYS_GPC_MFOS_MFOS11_Pos (11) /*!< SYS_T::GPC_MFOS: MFOS11 Position */ +#define SYS_GPC_MFOS_MFOS11_Msk (0x1ul << SYS_GPC_MFOS_MFOS11_Pos) /*!< SYS_T::GPC_MFOS: MFOS11 Mask */ + +#define SYS_GPC_MFOS_MFOS12_Pos (12) /*!< SYS_T::GPC_MFOS: MFOS12 Position */ +#define SYS_GPC_MFOS_MFOS12_Msk (0x1ul << SYS_GPC_MFOS_MFOS12_Pos) /*!< SYS_T::GPC_MFOS: MFOS12 Mask */ + +#define SYS_GPC_MFOS_MFOS13_Pos (13) /*!< SYS_T::GPC_MFOS: MFOS13 Position */ +#define SYS_GPC_MFOS_MFOS13_Msk (0x1ul << SYS_GPC_MFOS_MFOS13_Pos) /*!< SYS_T::GPC_MFOS: MFOS13 Mask */ + +#define SYS_GPD_MFOS_MFOS0_Pos (0) /*!< SYS_T::GPD_MFOS: MFOS0 Position */ +#define SYS_GPD_MFOS_MFOS0_Msk (0x1ul << SYS_GPD_MFOS_MFOS0_Pos) /*!< SYS_T::GPD_MFOS: MFOS0 Mask */ + +#define SYS_GPD_MFOS_MFOS1_Pos (1) /*!< SYS_T::GPD_MFOS: MFOS1 Position */ +#define SYS_GPD_MFOS_MFOS1_Msk (0x1ul << SYS_GPD_MFOS_MFOS1_Pos) /*!< SYS_T::GPD_MFOS: MFOS1 Mask */ + +#define SYS_GPD_MFOS_MFOS2_Pos (2) /*!< SYS_T::GPD_MFOS: MFOS2 Position */ +#define SYS_GPD_MFOS_MFOS2_Msk (0x1ul << SYS_GPD_MFOS_MFOS2_Pos) /*!< SYS_T::GPD_MFOS: MFOS2 Mask */ + +#define SYS_GPD_MFOS_MFOS3_Pos (3) /*!< SYS_T::GPD_MFOS: MFOS3 Position */ +#define SYS_GPD_MFOS_MFOS3_Msk (0x1ul << SYS_GPD_MFOS_MFOS3_Pos) /*!< SYS_T::GPD_MFOS: MFOS3 Mask */ + +#define SYS_GPD_MFOS_MFOS4_Pos (4) /*!< SYS_T::GPD_MFOS: MFOS4 Position */ +#define SYS_GPD_MFOS_MFOS4_Msk (0x1ul << SYS_GPD_MFOS_MFOS4_Pos) /*!< SYS_T::GPD_MFOS: MFOS4 Mask */ + +#define SYS_GPD_MFOS_MFOS5_Pos (5) /*!< SYS_T::GPD_MFOS: MFOS5 Position */ +#define SYS_GPD_MFOS_MFOS5_Msk (0x1ul << SYS_GPD_MFOS_MFOS5_Pos) /*!< SYS_T::GPD_MFOS: MFOS5 Mask */ + +#define SYS_GPD_MFOS_MFOS6_Pos (6) /*!< SYS_T::GPD_MFOS: MFOS6 Position */ +#define SYS_GPD_MFOS_MFOS6_Msk (0x1ul << SYS_GPD_MFOS_MFOS6_Pos) /*!< SYS_T::GPD_MFOS: MFOS6 Mask */ + +#define SYS_GPD_MFOS_MFOS7_Pos (7) /*!< SYS_T::GPD_MFOS: MFOS7 Position */ +#define SYS_GPD_MFOS_MFOS7_Msk (0x1ul << SYS_GPD_MFOS_MFOS7_Pos) /*!< SYS_T::GPD_MFOS: MFOS7 Mask */ + +#define SYS_GPD_MFOS_MFOS8_Pos (8) /*!< SYS_T::GPD_MFOS: MFOS8 Position */ +#define SYS_GPD_MFOS_MFOS8_Msk (0x1ul << SYS_GPD_MFOS_MFOS8_Pos) /*!< SYS_T::GPD_MFOS: MFOS8 Mask */ + +#define SYS_GPD_MFOS_MFOS9_Pos (9) /*!< SYS_T::GPD_MFOS: MFOS9 Position */ +#define SYS_GPD_MFOS_MFOS9_Msk (0x1ul << SYS_GPD_MFOS_MFOS9_Pos) /*!< SYS_T::GPD_MFOS: MFOS9 Mask */ + +#define SYS_GPD_MFOS_MFOS10_Pos (10) /*!< SYS_T::GPD_MFOS: MFOS10 Position */ +#define SYS_GPD_MFOS_MFOS10_Msk (0x1ul << SYS_GPD_MFOS_MFOS10_Pos) /*!< SYS_T::GPD_MFOS: MFOS10 Mask */ + +#define SYS_GPD_MFOS_MFOS11_Pos (11) /*!< SYS_T::GPD_MFOS: MFOS11 Position */ +#define SYS_GPD_MFOS_MFOS11_Msk (0x1ul << SYS_GPD_MFOS_MFOS11_Pos) /*!< SYS_T::GPD_MFOS: MFOS11 Mask */ + +#define SYS_GPD_MFOS_MFOS12_Pos (12) /*!< SYS_T::GPD_MFOS: MFOS12 Position */ +#define SYS_GPD_MFOS_MFOS12_Msk (0x1ul << SYS_GPD_MFOS_MFOS12_Pos) /*!< SYS_T::GPD_MFOS: MFOS12 Mask */ + +#define SYS_GPD_MFOS_MFOS14_Pos (14) /*!< SYS_T::GPD_MFOS: MFOS14 Position */ +#define SYS_GPD_MFOS_MFOS14_Msk (0x1ul << SYS_GPD_MFOS_MFOS14_Pos) /*!< SYS_T::GPD_MFOS: MFOS14 Mask */ + +#define SYS_GPE_MFOS_MFOS0_Pos (0) /*!< SYS_T::GPE_MFOS: MFOS0 Position */ +#define SYS_GPE_MFOS_MFOS0_Msk (0x1ul << SYS_GPE_MFOS_MFOS0_Pos) /*!< SYS_T::GPE_MFOS: MFOS0 Mask */ + +#define SYS_GPE_MFOS_MFOS1_Pos (1) /*!< SYS_T::GPE_MFOS: MFOS1 Position */ +#define SYS_GPE_MFOS_MFOS1_Msk (0x1ul << SYS_GPE_MFOS_MFOS1_Pos) /*!< SYS_T::GPE_MFOS: MFOS1 Mask */ + +#define SYS_GPE_MFOS_MFOS2_Pos (2) /*!< SYS_T::GPE_MFOS: MFOS2 Position */ +#define SYS_GPE_MFOS_MFOS2_Msk (0x1ul << SYS_GPE_MFOS_MFOS2_Pos) /*!< SYS_T::GPE_MFOS: MFOS2 Mask */ + +#define SYS_GPE_MFOS_MFOS3_Pos (3) /*!< SYS_T::GPE_MFOS: MFOS3 Position */ +#define SYS_GPE_MFOS_MFOS3_Msk (0x1ul << SYS_GPE_MFOS_MFOS3_Pos) /*!< SYS_T::GPE_MFOS: MFOS3 Mask */ + +#define SYS_GPE_MFOS_MFOS4_Pos (4) /*!< SYS_T::GPE_MFOS: MFOS4 Position */ +#define SYS_GPE_MFOS_MFOS4_Msk (0x1ul << SYS_GPE_MFOS_MFOS4_Pos) /*!< SYS_T::GPE_MFOS: MFOS4 Mask */ + +#define SYS_GPE_MFOS_MFOS5_Pos (5) /*!< SYS_T::GPE_MFOS: MFOS5 Position */ +#define SYS_GPE_MFOS_MFOS5_Msk (0x1ul << SYS_GPE_MFOS_MFOS5_Pos) /*!< SYS_T::GPE_MFOS: MFOS5 Mask */ + +#define SYS_GPE_MFOS_MFOS6_Pos (6) /*!< SYS_T::GPE_MFOS: MFOS6 Position */ +#define SYS_GPE_MFOS_MFOS6_Msk (0x1ul << SYS_GPE_MFOS_MFOS6_Pos) /*!< SYS_T::GPE_MFOS: MFOS6 Mask */ + +#define SYS_GPE_MFOS_MFOS7_Pos (7) /*!< SYS_T::GPE_MFOS: MFOS7 Position */ +#define SYS_GPE_MFOS_MFOS7_Msk (0x1ul << SYS_GPE_MFOS_MFOS7_Pos) /*!< SYS_T::GPE_MFOS: MFOS7 Mask */ + +#define SYS_GPE_MFOS_MFOS8_Pos (8) /*!< SYS_T::GPE_MFOS: MFOS8 Position */ +#define SYS_GPE_MFOS_MFOS8_Msk (0x1ul << SYS_GPE_MFOS_MFOS8_Pos) /*!< SYS_T::GPE_MFOS: MFOS8 Mask */ + +#define SYS_GPE_MFOS_MFOS9_Pos (9) /*!< SYS_T::GPE_MFOS: MFOS9 Position */ +#define SYS_GPE_MFOS_MFOS9_Msk (0x1ul << SYS_GPE_MFOS_MFOS9_Pos) /*!< SYS_T::GPE_MFOS: MFOS9 Mask */ + +#define SYS_GPE_MFOS_MFOS10_Pos (10) /*!< SYS_T::GPE_MFOS: MFOS10 Position */ +#define SYS_GPE_MFOS_MFOS10_Msk (0x1ul << SYS_GPE_MFOS_MFOS10_Pos) /*!< SYS_T::GPE_MFOS: MFOS10 Mask */ + +#define SYS_GPE_MFOS_MFOS11_Pos (11) /*!< SYS_T::GPE_MFOS: MFOS11 Position */ +#define SYS_GPE_MFOS_MFOS11_Msk (0x1ul << SYS_GPE_MFOS_MFOS11_Pos) /*!< SYS_T::GPE_MFOS: MFOS11 Mask */ + +#define SYS_GPE_MFOS_MFOS12_Pos (12) /*!< SYS_T::GPE_MFOS: MFOS12 Position */ +#define SYS_GPE_MFOS_MFOS12_Msk (0x1ul << SYS_GPE_MFOS_MFOS12_Pos) /*!< SYS_T::GPE_MFOS: MFOS12 Mask */ + +#define SYS_GPE_MFOS_MFOS13_Pos (13) /*!< SYS_T::GPE_MFOS: MFOS13 Position */ +#define SYS_GPE_MFOS_MFOS13_Msk (0x1ul << SYS_GPE_MFOS_MFOS13_Pos) /*!< SYS_T::GPE_MFOS: MFOS13 Mask */ + +#define SYS_GPE_MFOS_MFOS14_Pos (14) /*!< SYS_T::GPE_MFOS: MFOS14 Position */ +#define SYS_GPE_MFOS_MFOS14_Msk (0x1ul << SYS_GPE_MFOS_MFOS14_Pos) /*!< SYS_T::GPE_MFOS: MFOS14 Mask */ + +#define SYS_GPE_MFOS_MFOS15_Pos (15) /*!< SYS_T::GPE_MFOS: MFOS15 Position */ +#define SYS_GPE_MFOS_MFOS15_Msk (0x1ul << SYS_GPE_MFOS_MFOS15_Pos) /*!< SYS_T::GPE_MFOS: MFOS15 Mask */ + +#define SYS_GPF_MFOS_MFOS0_Pos (0) /*!< SYS_T::GPF_MFOS: MFOS0 Position */ +#define SYS_GPF_MFOS_MFOS0_Msk (0x1ul << SYS_GPF_MFOS_MFOS0_Pos) /*!< SYS_T::GPF_MFOS: MFOS0 Mask */ + +#define SYS_GPF_MFOS_MFOS1_Pos (1) /*!< SYS_T::GPF_MFOS: MFOS1 Position */ +#define SYS_GPF_MFOS_MFOS1_Msk (0x1ul << SYS_GPF_MFOS_MFOS1_Pos) /*!< SYS_T::GPF_MFOS: MFOS1 Mask */ + +#define SYS_GPF_MFOS_MFOS2_Pos (2) /*!< SYS_T::GPF_MFOS: MFOS2 Position */ +#define SYS_GPF_MFOS_MFOS2_Msk (0x1ul << SYS_GPF_MFOS_MFOS2_Pos) /*!< SYS_T::GPF_MFOS: MFOS2 Mask */ + +#define SYS_GPF_MFOS_MFOS3_Pos (3) /*!< SYS_T::GPF_MFOS: MFOS3 Position */ +#define SYS_GPF_MFOS_MFOS3_Msk (0x1ul << SYS_GPF_MFOS_MFOS3_Pos) /*!< SYS_T::GPF_MFOS: MFOS3 Mask */ + +#define SYS_GPF_MFOS_MFOS4_Pos (4) /*!< SYS_T::GPF_MFOS: MFOS4 Position */ +#define SYS_GPF_MFOS_MFOS4_Msk (0x1ul << SYS_GPF_MFOS_MFOS4_Pos) /*!< SYS_T::GPF_MFOS: MFOS4 Mask */ + +#define SYS_GPF_MFOS_MFOS5_Pos (5) /*!< SYS_T::GPF_MFOS: MFOS5 Position */ +#define SYS_GPF_MFOS_MFOS5_Msk (0x1ul << SYS_GPF_MFOS_MFOS5_Pos) /*!< SYS_T::GPF_MFOS: MFOS5 Mask */ + +#define SYS_GPF_MFOS_MFOS6_Pos (6) /*!< SYS_T::GPF_MFOS: MFOS6 Position */ +#define SYS_GPF_MFOS_MFOS6_Msk (0x1ul << SYS_GPF_MFOS_MFOS6_Pos) /*!< SYS_T::GPF_MFOS: MFOS6 Mask */ + +#define SYS_GPF_MFOS_MFOS7_Pos (7) /*!< SYS_T::GPF_MFOS: MFOS7 Position */ +#define SYS_GPF_MFOS_MFOS7_Msk (0x1ul << SYS_GPF_MFOS_MFOS7_Pos) /*!< SYS_T::GPF_MFOS: MFOS7 Mask */ + +#define SYS_GPF_MFOS_MFOS8_Pos (8) /*!< SYS_T::GPF_MFOS: MFOS8 Position */ +#define SYS_GPF_MFOS_MFOS8_Msk (0x1ul << SYS_GPF_MFOS_MFOS8_Pos) /*!< SYS_T::GPF_MFOS: MFOS8 Mask */ + +#define SYS_GPF_MFOS_MFOS9_Pos (9) /*!< SYS_T::GPF_MFOS: MFOS9 Position */ +#define SYS_GPF_MFOS_MFOS9_Msk (0x1ul << SYS_GPF_MFOS_MFOS9_Pos) /*!< SYS_T::GPF_MFOS: MFOS9 Mask */ + +#define SYS_GPF_MFOS_MFOS10_Pos (10) /*!< SYS_T::GPF_MFOS: MFOS10 Position */ +#define SYS_GPF_MFOS_MFOS10_Msk (0x1ul << SYS_GPF_MFOS_MFOS10_Pos) /*!< SYS_T::GPF_MFOS: MFOS10 Mask */ + +#define SYS_GPF_MFOS_MFOS11_Pos (11) /*!< SYS_T::GPF_MFOS: MFOS11 Position */ +#define SYS_GPF_MFOS_MFOS11_Msk (0x1ul << SYS_GPF_MFOS_MFOS11_Pos) /*!< SYS_T::GPF_MFOS: MFOS11 Mask */ + +#define SYS_GPG_MFOS_MFOS2_Pos (2) /*!< SYS_T::GPG_MFOS: MFOS2 Position */ +#define SYS_GPG_MFOS_MFOS2_Msk (0x1ul << SYS_GPG_MFOS_MFOS2_Pos) /*!< SYS_T::GPG_MFOS: MFOS2 Mask */ + +#define SYS_GPG_MFOS_MFOS3_Pos (3) /*!< SYS_T::GPG_MFOS: MFOS3 Position */ +#define SYS_GPG_MFOS_MFOS3_Msk (0x1ul << SYS_GPG_MFOS_MFOS3_Pos) /*!< SYS_T::GPG_MFOS: MFOS3 Mask */ + +#define SYS_GPG_MFOS_MFOS4_Pos (4) /*!< SYS_T::GPG_MFOS: MFOS4 Position */ +#define SYS_GPG_MFOS_MFOS4_Msk (0x1ul << SYS_GPG_MFOS_MFOS4_Pos) /*!< SYS_T::GPG_MFOS: MFOS4 Mask */ + +#define SYS_GPG_MFOS_MFOS9_Pos (9) /*!< SYS_T::GPG_MFOS: MFOS9 Position */ +#define SYS_GPG_MFOS_MFOS9_Msk (0x1ul << SYS_GPG_MFOS_MFOS9_Pos) /*!< SYS_T::GPG_MFOS: MFOS9 Mask */ + +#define SYS_GPG_MFOS_MFOS10_Pos (10) /*!< SYS_T::GPG_MFOS: MFOS10 Position */ +#define SYS_GPG_MFOS_MFOS10_Msk (0x1ul << SYS_GPG_MFOS_MFOS10_Pos) /*!< SYS_T::GPG_MFOS: MFOS10 Mask */ + +#define SYS_GPG_MFOS_MFOS11_Pos (11) /*!< SYS_T::GPG_MFOS: MFOS11 Position */ +#define SYS_GPG_MFOS_MFOS11_Msk (0x1ul << SYS_GPG_MFOS_MFOS11_Pos) /*!< SYS_T::GPG_MFOS: MFOS11 Mask */ + +#define SYS_GPG_MFOS_MFOS12_Pos (12) /*!< SYS_T::GPG_MFOS: MFOS12 Position */ +#define SYS_GPG_MFOS_MFOS12_Msk (0x1ul << SYS_GPG_MFOS_MFOS12_Pos) /*!< SYS_T::GPG_MFOS: MFOS12 Mask */ + +#define SYS_GPG_MFOS_MFOS13_Pos (13) /*!< SYS_T::GPG_MFOS: MFOS13 Position */ +#define SYS_GPG_MFOS_MFOS13_Msk (0x1ul << SYS_GPG_MFOS_MFOS13_Pos) /*!< SYS_T::GPG_MFOS: MFOS13 Mask */ + +#define SYS_GPG_MFOS_MFOS14_Pos (14) /*!< SYS_T::GPG_MFOS: MFOS14 Position */ +#define SYS_GPG_MFOS_MFOS14_Msk (0x1ul << SYS_GPG_MFOS_MFOS14_Pos) /*!< SYS_T::GPG_MFOS: MFOS14 Mask */ + +#define SYS_GPG_MFOS_MFOS15_Pos (15) /*!< SYS_T::GPG_MFOS: MFOS15 Position */ +#define SYS_GPG_MFOS_MFOS15_Msk (0x1ul << SYS_GPG_MFOS_MFOS15_Pos) /*!< SYS_T::GPG_MFOS: MFOS15 Mask */ + +#define SYS_GPH_MFOS_MFOS4_Pos (4) /*!< SYS_T::GPH_MFOS: MFOS4 Position */ +#define SYS_GPH_MFOS_MFOS4_Msk (0x1ul << SYS_GPH_MFOS_MFOS4_Pos) /*!< SYS_T::GPH_MFOS: MFOS4 Mask */ + +#define SYS_GPH_MFOS_MFOS5_Pos (5) /*!< SYS_T::GPH_MFOS: MFOS5 Position */ +#define SYS_GPH_MFOS_MFOS5_Msk (0x1ul << SYS_GPH_MFOS_MFOS5_Pos) /*!< SYS_T::GPH_MFOS: MFOS5 Mask */ + +#define SYS_GPH_MFOS_MFOS6_Pos (6) /*!< SYS_T::GPH_MFOS: MFOS6 Position */ +#define SYS_GPH_MFOS_MFOS6_Msk (0x1ul << SYS_GPH_MFOS_MFOS6_Pos) /*!< SYS_T::GPH_MFOS: MFOS6 Mask */ + +#define SYS_GPH_MFOS_MFOS7_Pos (7) /*!< SYS_T::GPH_MFOS: MFOS7 Position */ +#define SYS_GPH_MFOS_MFOS7_Msk (0x1ul << SYS_GPH_MFOS_MFOS7_Pos) /*!< SYS_T::GPH_MFOS: MFOS7 Mask */ + +#define SYS_GPH_MFOS_MFOS8_Pos (8) /*!< SYS_T::GPH_MFOS: MFOS8 Position */ +#define SYS_GPH_MFOS_MFOS8_Msk (0x1ul << SYS_GPH_MFOS_MFOS8_Pos) /*!< SYS_T::GPH_MFOS: MFOS8 Mask */ + +#define SYS_GPH_MFOS_MFOS9_Pos (9) /*!< SYS_T::GPH_MFOS: MFOS9 Position */ +#define SYS_GPH_MFOS_MFOS9_Msk (0x1ul << SYS_GPH_MFOS_MFOS9_Pos) /*!< SYS_T::GPH_MFOS: MFOS9 Mask */ + +#define SYS_GPH_MFOS_MFOS10_Pos (10) /*!< SYS_T::GPH_MFOS: MFOS10 Position */ +#define SYS_GPH_MFOS_MFOS10_Msk (0x1ul << SYS_GPH_MFOS_MFOS10_Pos) /*!< SYS_T::GPH_MFOS: MFOS10 Mask */ + +#define SYS_GPH_MFOS_MFOS11_Pos (11) /*!< SYS_T::GPH_MFOS: MFOS11 Position */ +#define SYS_GPH_MFOS_MFOS11_Msk (0x1ul << SYS_GPH_MFOS_MFOS11_Pos) /*!< SYS_T::GPH_MFOS: MFOS11 Mask */ + +#define SYS_VTORSET_VTORSET_Pos (11) /*!< SYS_T::VTORSET: VTORSET Position */ +#define SYS_VTORSET_VTORSET_Msk (0x3fffful << SYS_VTORSET_VTORSET_Pos) /*!< SYS_T::VTORSET: VTORSET Mask */ + +#define SYS_SRAMICTL_PERRIEN_Pos (0) /*!< SYS_T::SRAMICTL: PERRIEN Position */ +#define SYS_SRAMICTL_PERRIEN_Msk (0x1ul << SYS_SRAMICTL_PERRIEN_Pos) /*!< SYS_T::SRAMICTL: PERRIEN Mask */ + +#define SYS_SRAMSTS_PERRIF_Pos (0) /*!< SYS_T::SRAMSTS: PERRIF Position */ +#define SYS_SRAMSTS_PERRIF_Msk (0x1ul << SYS_SRAMSTS_PERRIF_Pos) /*!< SYS_T::SRAMSTS: PERRIF Mask */ + +#define SYS_SRAMEADR_ERRADDR_Pos (0) /*!< SYS_T::SRAMEADR: ERRADDR Position */ +#define SYS_SRAMEADR_ERRADDR_Msk (0xfffffffful << SYS_SRAMEADR_ERRADDR_Pos) /*!< SYS_T::SRAMEADR: ERRADDR Mask */ + +#define SYS_SRAMPC0_SRAM0PM0_Pos (0) /*!< SYS_T::SRAMPC0: SRAM0PM0 Position */ +#define SYS_SRAMPC0_SRAM0PM0_Msk (0x3ul << SYS_SRAMPC0_SRAM0PM0_Pos) /*!< SYS_T::SRAMPC0: SRAM0PM0 Mask */ + +#define SYS_SRAMPC0_SRAM0PM1_Pos (2) /*!< SYS_T::SRAMPC0: SRAM0PM1 Position */ +#define SYS_SRAMPC0_SRAM0PM1_Msk (0x3ul << SYS_SRAMPC0_SRAM0PM1_Pos) /*!< SYS_T::SRAMPC0: SRAM0PM1 Mask */ + +#define SYS_SRAMPC0_SRAM0PM2_Pos (4) /*!< SYS_T::SRAMPC0: SRAM0PM2 Position */ +#define SYS_SRAMPC0_SRAM0PM2_Msk (0x3ul << SYS_SRAMPC0_SRAM0PM2_Pos) /*!< SYS_T::SRAMPC0: SRAM0PM2 Mask */ + +#define SYS_SRAMPC0_SRAM0PM3_Pos (6) /*!< SYS_T::SRAMPC0: SRAM0PM3 Position */ +#define SYS_SRAMPC0_SRAM0PM3_Msk (0x3ul << SYS_SRAMPC0_SRAM0PM3_Pos) /*!< SYS_T::SRAMPC0: SRAM0PM3 Mask */ + +#define SYS_SRAMPC0_SRAM0PM4_Pos (8) /*!< SYS_T::SRAMPC0: SRAM0PM4 Position */ +#define SYS_SRAMPC0_SRAM0PM4_Msk (0x3ul << SYS_SRAMPC0_SRAM0PM4_Pos) /*!< SYS_T::SRAMPC0: SRAM0PM4 Mask */ + +#define SYS_SRAMPC0_SRAM1PM0_Pos (10) /*!< SYS_T::SRAMPC0: SRAM1PM0 Position */ +#define SYS_SRAMPC0_SRAM1PM0_Msk (0x3ul << SYS_SRAMPC0_SRAM1PM0_Pos) /*!< SYS_T::SRAMPC0: SRAM1PM0 Mask */ + +#define SYS_SRAMPC0_SRAM1PM1_Pos (12) /*!< SYS_T::SRAMPC0: SRAM1PM1 Position */ +#define SYS_SRAMPC0_SRAM1PM1_Msk (0x3ul << SYS_SRAMPC0_SRAM1PM1_Pos) /*!< SYS_T::SRAMPC0: SRAM1PM1 Mask */ + +#define SYS_SRAMPC0_SRAM1PM2_Pos (14) /*!< SYS_T::SRAMPC0: SRAM1PM2 Position */ +#define SYS_SRAMPC0_SRAM1PM2_Msk (0x3ul << SYS_SRAMPC0_SRAM1PM2_Pos) /*!< SYS_T::SRAMPC0: SRAM1PM2 Mask */ + +#define SYS_SRAMPC0_SRAM1PM3_Pos (16) /*!< SYS_T::SRAMPC0: SRAM1PM3 Position */ +#define SYS_SRAMPC0_SRAM1PM3_Msk (0x3ul << SYS_SRAMPC0_SRAM1PM3_Pos) /*!< SYS_T::SRAMPC0: SRAM1PM3 Mask */ + +#define SYS_SRAMPC0_SRAM1PM4_Pos (18) /*!< SYS_T::SRAMPC0: SRAM1PM4 Position */ +#define SYS_SRAMPC0_SRAM1PM4_Msk (0x3ul << SYS_SRAMPC0_SRAM1PM4_Pos) /*!< SYS_T::SRAMPC0: SRAM1PM4 Mask */ + +#define SYS_SRAMPC0_SRAM1PM5_Pos (20) /*!< SYS_T::SRAMPC0: SRAM1PM5 Position */ +#define SYS_SRAMPC0_SRAM1PM5_Msk (0x3ul << SYS_SRAMPC0_SRAM1PM5_Pos) /*!< SYS_T::SRAMPC0: SRAM1PM5 Mask */ + +#define SYS_SRAMPC0_SRAM1PM6_Pos (22) /*!< SYS_T::SRAMPC0: SRAM1PM6 Position */ +#define SYS_SRAMPC0_SRAM1PM6_Msk (0x3ul << SYS_SRAMPC0_SRAM1PM6_Pos) /*!< SYS_T::SRAMPC0: SRAM1PM6 Mask */ + +#define SYS_SRAMPC0_SRAM1PM7_Pos (24) /*!< SYS_T::SRAMPC0: SRAM1PM7 Position */ +#define SYS_SRAMPC0_SRAM1PM7_Msk (0x3ul << SYS_SRAMPC0_SRAM1PM7_Pos) /*!< SYS_T::SRAMPC0: SRAM1PM7 Mask */ + +#define SYS_SRAMPC0_SRAM2PM0_Pos (26) /*!< SYS_T::SRAMPC0: SRAM2PM0 Position */ +#define SYS_SRAMPC0_SRAM2PM0_Msk (0x3ul << SYS_SRAMPC0_SRAM2PM0_Pos) /*!< SYS_T::SRAMPC0: SRAM2PM0 Mask */ + +#define SYS_SRAMPC0_SRAM2PM1_Pos (28) /*!< SYS_T::SRAMPC0: SRAM2PM1 Position */ +#define SYS_SRAMPC0_SRAM2PM1_Msk (0x3ul << SYS_SRAMPC0_SRAM2PM1_Pos) /*!< SYS_T::SRAMPC0: SRAM2PM1 Mask */ + +#define SYS_SRAMPC0_PCBUSY_Pos (31) /*!< SYS_T::SRAMPC0: PCBUSY Position */ +#define SYS_SRAMPC0_PCBUSY_Msk (0x1ul << SYS_SRAMPC0_PCBUSY_Pos) /*!< SYS_T::SRAMPC0: PCBUSY Mask */ + +#define SYS_SRAMPC1_SRAM2PM2_Pos (0) /*!< SYS_T::SRAMPC1: SRAM2PM2 Position */ +#define SYS_SRAMPC1_SRAM2PM2_Msk (0x3ul << SYS_SRAMPC1_SRAM2PM2_Pos) /*!< SYS_T::SRAMPC1: SRAM2PM2 Mask */ + +#define SYS_SRAMPC1_SRAM2PM3_Pos (2) /*!< SYS_T::SRAMPC1: SRAM2PM3 Position */ +#define SYS_SRAMPC1_SRAM2PM3_Msk (0x3ul << SYS_SRAMPC1_SRAM2PM3_Pos) /*!< SYS_T::SRAMPC1: SRAM2PM3 Mask */ + +#define SYS_SRAMPC1_SRAM2PM4_Pos (4) /*!< SYS_T::SRAMPC1: SRAM2PM4 Position */ +#define SYS_SRAMPC1_SRAM2PM4_Msk (0x3ul << SYS_SRAMPC1_SRAM2PM4_Pos) /*!< SYS_T::SRAMPC1: SRAM2PM4 Mask */ + +#define SYS_SRAMPC1_SRAM2PM5_Pos (6) /*!< SYS_T::SRAMPC1: SRAM2PM5 Position */ +#define SYS_SRAMPC1_SRAM2PM5_Msk (0x3ul << SYS_SRAMPC1_SRAM2PM5_Pos) /*!< SYS_T::SRAMPC1: SRAM2PM5 Mask */ + +#define SYS_SRAMPC1_CAN_Pos (16) /*!< SYS_T::SRAMPC1: CAN Position */ +#define SYS_SRAMPC1_CAN_Msk (0x3ul << SYS_SRAMPC1_CAN_Pos) /*!< SYS_T::SRAMPC1: CAN Mask */ + +#define SYS_SRAMPC1_USBD_Pos (18) /*!< SYS_T::SRAMPC1: USBD Position */ +#define SYS_SRAMPC1_USBD_Msk (0x3ul << SYS_SRAMPC1_USBD_Pos) /*!< SYS_T::SRAMPC1: USBD Mask */ + +#define SYS_SRAMPC1_PDMA0_Pos (20) /*!< SYS_T::SRAMPC1: PDMA0 Position */ +#define SYS_SRAMPC1_PDMA0_Msk (0x3ul << SYS_SRAMPC1_PDMA0_Pos) /*!< SYS_T::SRAMPC1: PDMA0 Mask */ + +#define SYS_SRAMPC1_PDMA1_Pos (22) /*!< SYS_T::SRAMPC1: PDMA1 Position */ +#define SYS_SRAMPC1_PDMA1_Msk (0x3ul << SYS_SRAMPC1_PDMA1_Pos) /*!< SYS_T::SRAMPC1: PDMA1 Mask */ + +#define SYS_SRAMPC1_FMCCACHE_Pos (24) /*!< SYS_T::SRAMPC1: FMCCACHE Position */ +#define SYS_SRAMPC1_FMCCACHE_Msk (0x3ul << SYS_SRAMPC1_FMCCACHE_Pos) /*!< SYS_T::SRAMPC1: FMCCACHE Mask */ + +#define SYS_SRAMPC1_RSA_Pos (26) /*!< SYS_T::SRAMPC1: RSA Position */ +#define SYS_SRAMPC1_RSA_Msk (0x3ul << SYS_SRAMPC1_RSA_Pos) /*!< SYS_T::SRAMPC1: RSA Mask */ + +#define SYS_SRAMPC1_KS_Pos (28) /*!< SYS_T::SRAMPC1: KS Position */ +#define SYS_SRAMPC1_KS_Msk (0x3ul << SYS_SRAMPC1_KS_Pos) /*!< SYS_T::SRAMPC1: KS Mask */ + +#define SYS_SRAMPC1_PCBUSY_Pos (31) /*!< SYS_T::SRAMPC1: PCBUSY Position */ +#define SYS_SRAMPC1_PCBUSY_Msk (0x1ul << SYS_SRAMPC1_PCBUSY_Pos) /*!< SYS_T::SRAMPC1: PCBUSY Mask */ + +#define SYS_TCTL48M_FREQSEL_Pos (0) /*!< SYS_T::TCTL48M: FREQSEL Position */ +#define SYS_TCTL48M_FREQSEL_Msk (0x3ul << SYS_TCTL48M_FREQSEL_Pos) /*!< SYS_T::TCTL48M: FREQSEL Mask */ + +#define SYS_TCTL48M_LOOPSEL_Pos (4) /*!< SYS_T::TCTL48M: LOOPSEL Position */ +#define SYS_TCTL48M_LOOPSEL_Msk (0x3ul << SYS_TCTL48M_LOOPSEL_Pos) /*!< SYS_T::TCTL48M: LOOPSEL Mask */ + +#define SYS_TCTL48M_RETRYCNT_Pos (6) /*!< SYS_T::TCTL48M: RETRYCNT Position */ +#define SYS_TCTL48M_RETRYCNT_Msk (0x3ul << SYS_TCTL48M_RETRYCNT_Pos) /*!< SYS_T::TCTL48M: RETRYCNT Mask */ + +#define SYS_TCTL48M_CESTOPEN_Pos (8) /*!< SYS_T::TCTL48M: CESTOPEN Position */ +#define SYS_TCTL48M_CESTOPEN_Msk (0x1ul << SYS_TCTL48M_CESTOPEN_Pos) /*!< SYS_T::TCTL48M: CESTOPEN Mask */ + +#define SYS_TCTL48M_BOUNDEN_Pos (9) /*!< SYS_T::TCTL48M: BOUNDEN Position */ +#define SYS_TCTL48M_BOUNDEN_Msk (0x1ul << SYS_TCTL48M_BOUNDEN_Pos) /*!< SYS_T::TCTL48M: BOUNDEN Mask */ + +#define SYS_TCTL48M_REFCKSEL_Pos (10) /*!< SYS_T::TCTL48M: REFCKSEL Position */ +#define SYS_TCTL48M_REFCKSEL_Msk (0x1ul << SYS_TCTL48M_REFCKSEL_Pos) /*!< SYS_T::TCTL48M: REFCKSEL Mask */ + +#define SYS_TCTL48M_BOUNDARY_Pos (16) /*!< SYS_T::TCTL48M: BOUNDARY Position */ +#define SYS_TCTL48M_BOUNDARY_Msk (0x1ful << SYS_TCTL48M_BOUNDARY_Pos) /*!< SYS_T::TCTL48M: BOUNDARY Mask */ + +#define SYS_TIEN48M_TFAILIEN_Pos (1) /*!< SYS_T::TIEN48M: TFAILIEN Position */ +#define SYS_TIEN48M_TFAILIEN_Msk (0x1ul << SYS_TIEN48M_TFAILIEN_Pos) /*!< SYS_T::TIEN48M: TFAILIEN Mask */ + +#define SYS_TIEN48M_CLKEIEN_Pos (2) /*!< SYS_T::TIEN48M: CLKEIEN Position */ +#define SYS_TIEN48M_CLKEIEN_Msk (0x1ul << SYS_TIEN48M_CLKEIEN_Pos) /*!< SYS_T::TIEN48M: CLKEIEN Mask */ + +#define SYS_TISTS48M_FREQLOCK_Pos (0) /*!< SYS_T::TISTS48M: FREQLOCK Position */ +#define SYS_TISTS48M_FREQLOCK_Msk (0x1ul << SYS_TISTS48M_FREQLOCK_Pos) /*!< SYS_T::TISTS48M: FREQLOCK Mask */ + +#define SYS_TISTS48M_TFAILIF_Pos (1) /*!< SYS_T::TISTS48M: TFAILIF Position */ +#define SYS_TISTS48M_TFAILIF_Msk (0x1ul << SYS_TISTS48M_TFAILIF_Pos) /*!< SYS_T::TISTS48M: TFAILIF Mask */ + +#define SYS_TISTS48M_CLKERRIF_Pos (2) /*!< SYS_T::TISTS48M: CLKERRIF Position */ +#define SYS_TISTS48M_CLKERRIF_Msk (0x1ul << SYS_TISTS48M_CLKERRIF_Pos) /*!< SYS_T::TISTS48M: CLKERRIF Mask */ + +#define SYS_TISTS48M_OVBDIF_Pos (3) /*!< SYS_T::TISTS48M: OVBDIF Position */ +#define SYS_TISTS48M_OVBDIF_Msk (0x1ul << SYS_TISTS48M_OVBDIF_Pos) /*!< SYS_T::TISTS48M: OVBDIF Mask */ + +#define SYS_TCTL12M_FREQSEL_Pos (0) /*!< SYS_T::TCTL12M: FREQSEL Position */ +#define SYS_TCTL12M_FREQSEL_Msk (0x3ul << SYS_TCTL12M_FREQSEL_Pos) /*!< SYS_T::TCTL12M: FREQSEL Mask */ + +#define SYS_TCTL12M_LOOPSEL_Pos (4) /*!< SYS_T::TCTL12M: LOOPSEL Position */ +#define SYS_TCTL12M_LOOPSEL_Msk (0x3ul << SYS_TCTL12M_LOOPSEL_Pos) /*!< SYS_T::TCTL12M: LOOPSEL Mask */ + +#define SYS_TCTL12M_RETRYCNT_Pos (6) /*!< SYS_T::TCTL12M: RETRYCNT Position */ +#define SYS_TCTL12M_RETRYCNT_Msk (0x3ul << SYS_TCTL12M_RETRYCNT_Pos) /*!< SYS_T::TCTL12M: RETRYCNT Mask */ + +#define SYS_TCTL12M_CESTOPEN_Pos (8) /*!< SYS_T::TCTL12M: CESTOPEN Position */ +#define SYS_TCTL12M_CESTOPEN_Msk (0x1ul << SYS_TCTL12M_CESTOPEN_Pos) /*!< SYS_T::TCTL12M: CESTOPEN Mask */ + +#define SYS_TCTL12M_BOUNDEN_Pos (9) /*!< SYS_T::TCTL12M: BOUNDEN Position */ +#define SYS_TCTL12M_BOUNDEN_Msk (0x1ul << SYS_TCTL12M_BOUNDEN_Pos) /*!< SYS_T::TCTL12M: BOUNDEN Mask */ + +#define SYS_TCTL12M_REFCKSEL_Pos (10) /*!< SYS_T::TCTL12M: REFCKSEL Position */ +#define SYS_TCTL12M_REFCKSEL_Msk (0x1ul << SYS_TCTL12M_REFCKSEL_Pos) /*!< SYS_T::TCTL12M: REFCKSEL Mask */ + +#define SYS_TCTL12M_BOUNDARY_Pos (16) /*!< SYS_T::TCTL12M: BOUNDARY Position */ +#define SYS_TCTL12M_BOUNDARY_Msk (0x1ful << SYS_TCTL12M_BOUNDARY_Pos) /*!< SYS_T::TCTL12M: BOUNDARY Mask */ + +#define SYS_TIEN12M_TFAILIEN_Pos (1) /*!< SYS_T::TIEN12M: TFAILIEN Position */ +#define SYS_TIEN12M_TFAILIEN_Msk (0x1ul << SYS_TIEN12M_TFAILIEN_Pos) /*!< SYS_T::TIEN12M: TFAILIEN Mask */ + +#define SYS_TIEN12M_CLKEIEN_Pos (2) /*!< SYS_T::TIEN12M: CLKEIEN Position */ +#define SYS_TIEN12M_CLKEIEN_Msk (0x1ul << SYS_TIEN12M_CLKEIEN_Pos) /*!< SYS_T::TIEN12M: CLKEIEN Mask */ + +#define SYS_TISTS12M_FREQLOCK_Pos (0) /*!< SYS_T::TISTS12M: FREQLOCK Position */ +#define SYS_TISTS12M_FREQLOCK_Msk (0x1ul << SYS_TISTS12M_FREQLOCK_Pos) /*!< SYS_T::TISTS12M: FREQLOCK Mask */ + +#define SYS_TISTS12M_TFAILIF_Pos (1) /*!< SYS_T::TISTS12M: TFAILIF Position */ +#define SYS_TISTS12M_TFAILIF_Msk (0x1ul << SYS_TISTS12M_TFAILIF_Pos) /*!< SYS_T::TISTS12M: TFAILIF Mask */ + +#define SYS_TISTS12M_CLKERRIF_Pos (2) /*!< SYS_T::TISTS12M: CLKERRIF Position */ +#define SYS_TISTS12M_CLKERRIF_Msk (0x1ul << SYS_TISTS12M_CLKERRIF_Pos) /*!< SYS_T::TISTS12M: CLKERRIF Mask */ + +#define SYS_TISTS12M_OVBDIF_Pos (3) /*!< SYS_T::TISTS12M: OVBDIF Position */ +#define SYS_TISTS12M_OVBDIF_Msk (0x1ul << SYS_TISTS12M_OVBDIF_Pos) /*!< SYS_T::TISTS12M: OVBDIF Mask */ + +#define SYS_REGLCTL_REGLCTL_Pos (0) /*!< SYS_T::REGLCTL: REGLCTL Position */ +#define SYS_REGLCTL_REGLCTL_Msk (0xfful << SYS_REGLCTL_REGLCTL_Pos) /*!< SYS_T::REGLCTL: REGLCTL Mask */ + +#define SYS_CPUCFG_INTRTEN_Pos (0) /*!< SYS_T::CPUCFG: INTRTEN Position */ +#define SYS_CPUCFG_INTRTEN_Msk (0x1ul << SYS_CPUCFG_INTRTEN_Pos) /*!< SYS_T::CPUCFG: INTRTEN Mask */ + +#define SYS_OVDCTL_OVDEN_Pos (0) /*!< SYS_T::OVDCTL: OVDEN Position */ +#define SYS_OVDCTL_OVDEN_Msk (0x1ul << SYS_OVDCTL_OVDEN_Pos) /*!< SYS_T::OVDCTL: OVDEN Mask */ + +#define SYS_OVDCTL_OVDSTB_Pos (31) /*!< SYS_T::OVDCTL: OVDSTB Position */ +#define SYS_OVDCTL_OVDSTB_Msk (0x1ul << SYS_OVDCTL_OVDSTB_Pos) /*!< SYS_T::OVDCTL: OVDSTB Mask */ + +#define SYS_PORCTL1_POROFF_Pos (0) /*!< SYS_T::PORCTL1: POROFF Position */ +#define SYS_PORCTL1_POROFF_Msk (0xfffful << SYS_PORCTL1_POROFF_Pos) /*!< SYS_T::PORCTL1: POROFF Mask */ + +#define SYS_PSWCTL_CRPTPWREN_Pos (12) /*!< SYS_T::PSWCTL: CRPTPWREN Position */ +#define SYS_PSWCTL_CRPTPWREN_Msk (0x1ul << SYS_PSWCTL_CRPTPWREN_Pos) /*!< SYS_T::PSWCTL: CRPTPWREN Mask */ + +#define SYS_PLCTL_PLSEL_Pos (0) /*!< SYS_T::PLCTL: PLSEL Position */ +#define SYS_PLCTL_PLSEL_Msk (0x3ul << SYS_PLCTL_PLSEL_Pos) /*!< SYS_T::PLCTL: PLSEL Mask */ + +#define SYS_PLCTL_MVRS_Pos (4) /*!< SYS_T::PLCTL: MVRS Position */ +#define SYS_PLCTL_MVRS_Msk (0x1ul << SYS_PLCTL_MVRS_Pos) /*!< SYS_T::PLCTL: MVRS Mask */ + +#define SYS_PLCTL_WRBUSY_Pos (7) /*!< SYS_T::PLCTL: WRBUSY Position */ +#define SYS_PLCTL_WRBUSY_Msk (0x1ul << SYS_PLCTL_WRBUSY_Pos) /*!< SYS_T::PLCTL: WRBUSY Mask */ + +#define SYS_PLCTL_LVSSTEP_Pos (16) /*!< SYS_T::PLCTL: LVSSTEP Position */ +#define SYS_PLCTL_LVSSTEP_Msk (0x3ful << SYS_PLCTL_LVSSTP_Pos) /*!< SYS_T::PLCTL: LVSSTEP Mask */ + +#define SYS_PLCTL_LVSPRD_Pos (24) /*!< SYS_T::PLCTL: LVSPRD Position */ +#define SYS_PLCTL_LVSPRD_Msk (0xfful << SYS_PLCTL_LVSPRD_Pos) /*!< SYS_T::PLCTL: LVSPRD Mask */ + +#define SYS_PLSTS_PLCBUSY_Pos (0) /*!< SYS_T::PLSTS: PLCBUSY Position */ +#define SYS_PLSTS_PLCBUSY_Msk (0x1ul << SYS_PLSTS_PLCBUSY_Pos) /*!< SYS_T::PLSTS: PLCBUSY Mask */ + +#define SYS_PLSTS_MVRCBUSY_Pos (1) /*!< SYS_T::PLSTS: MVRCBUSY Position */ +#define SYS_PLSTS_MVRCBUSY_Msk (0x1ul << SYS_PLSTS_MVRCBUSY_Pos) /*!< SYS_T::PLSTS: MVRCBUSY Mask */ + +#define SYS_PLSTS_MVRCERR_Pos (2) /*!< SYS_T::PLSTS: MVRCERR Position */ +#define SYS_PLSTS_MVRCERR_Msk (0x1ul << SYS_PLSTS_MVRCERR_Pos) /*!< SYS_T::PLSTS: MVRCERR Mask */ + +#define SYS_PLSTS_LCONS_Pos (3) /*!< SYS_T::PLSTS: LCONS Position */ +#define SYS_PLSTS_LCONS_Msk (0x1ul << SYS_PLSTS_LCONS_Pos) /*!< SYS_T::PLSTS: LCONS Mask */ + +#define SYS_PLSTS_PLSTATUS_Pos (8) /*!< SYS_T::PLSTS: PLSTATUS Position */ +#define SYS_PLSTS_PLSTATUS_Msk (0x3ul << SYS_PLSTS_PLSTATUS_Pos) /*!< SYS_T::PLSTS: PLSTATUS Mask */ + +#define SYS_PLSTS_CURMVR_Pos (12) /*!< SYS_T::PLSTS: CURMVR Position */ +#define SYS_PLSTS_CURMVR_Msk (0x1ul << SYS_PLSTS_CURMVR_Pos) /*!< SYS_T::PLSTS: CURMVR Mask */ + +#define SYS_AHBMCTL_INTACTEN_Pos (0) /*!< SYS_T::AHBMCTL: INTACTEN Position */ +#define SYS_AHBMCTL_INTACTEN_Msk (0x1ul << SYS_AHBMCTL_INTACTEN_Pos) /*!< SYS_T::AHBMCTL: INTACTEN Mask */ + + +/**@}*/ /* SYS_CONST */ +typedef struct +{ + + /** + * @var SYS_INT_T::NMIEN + * Offset: 0x00 NMI Source Interrupt Enable Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |BODOUT |BOD NMI Source Enable (Write Protect) + * | | |0 = BOD NMI source Disabled. + * | | |1 = BOD NMI source Enabled. + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * |[1] |IRCINT |IRC TRIM NMI Source Enable (Write Protect) + * | | |0 = IRC TRIM NMI source Disabled. + * | | |1 = IRC TRIM NMI source Enabled. + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * |[2] |PWRWUINT |Power-down Mode Wake-up NMI Source Enable (Write Protect) + * | | |0 = Power-down mode wake-up NMI source Disabled. + * | | |1 = Power-down mode wake-up NMI source Enabled. + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * |[3] |SRAMPERR |SRAM Parity Check Error NMI Source Enable (Write Protect) + * | | |0 = SRAM parity check error NMI source Disabled. + * | | |1 = SRAM parity check error NMI source Enabled. + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * |[4] |CLKFAIL |Clock Fail Detected NMI Source Enable (Write Protect) + * | | |0 = Clock fail detected interrupt NMI source Disabled. + * | | |1 = Clock fail detected interrupt NMI source Enabled. + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * |[6] |RTCINT |RTC NMI Source Enable (Write Protect) + * | | |0 = RTC NMI source Disabled. + * | | |1 = RTC NMI source Enabled. + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * |[7] |TAMPERINT |Tamper Interrupt NMI Source Enable (Write Protect) + * | | |0 = Backup register tamper detected interrupt NMI source Disabled. + * | | |1 = Backup register tamper detected interrupt NMI source Enabled. + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * |[8] |EINT0 |External Interrupt From PA.6, or PB.5 Pin NMI Source Enable (Write Protect) + * | | |0 = External interrupt from PA.6, or PB.5 pin NMI source Disabled. + * | | |1 = External interrupt from PA.6, or PB.5 pin NMI source Enabled. + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * |[9] |EINT1 |External Interrupt From PA.7 or PB.4 Pin NMI Source Enable (Write Protect) + * | | |0 = External interrupt from PA.7 or PB.4 pin NMI source Disabled. + * | | |1 = External interrupt from PA.7 or P4.4 pin NMI source Enabled. + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * |[10] |EINT2 |External Interrupt From PB.3 or PC.6 Pin NMI Source Enable (Write Protect) + * | | |0 = External interrupt from PB.3 or PC.6 pin NMI source Disabled. + * | | |1 = External interrupt from PB.3 or PC.6 pin NMI source Enabled. + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * |[11] |EINT3 |External Interrupt From PB.2 or PC.7 Pin NMI Source Enable (Write Protect) + * | | |0 = External interrupt from PB.2 or PC.7pin NMI source Disabled. + * | | |1 = External interrupt from PB.2 or PC.7 pin NMI source Enabled. + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * |[12] |EINT4 |External Interrupt From PA.8 or PB.6 Pin NMI Source Enable (Write Protect) + * | | |0 = External interrupt from PA.8 or PB.6 pin NMI source Disabled. + * | | |1 = External interrupt from PA.8 or PB.6 pin NMI source Enabled. + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * |[13] |EINT5 |External Interrupt From PB.7 or PD.12 Pin NMI Source Enable (Write Protect) + * | | |0 = External interrupt from PB.7 or PD.12 pin NMI source Disabled. + * | | |1 = External interrupt from PB.7 or PD.12 pin NMI source Enabled. + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * |[14] |UART0INT |UART0 NMI Source Enable (Write Protect) + * | | |0 = UART0 NMI source Disabled. + * | | |1 = UART0 NMI source Enabled. + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * |[15] |UART1INT |UART1 NMI Source Enable (Write Protect) + * | | |0 = UART1 NMI source Disabled. + * | | |1 = UART1 NMI source Enabled. + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * |[16] |EINT6 |External Interrupt From PB.8 or PD.11 Pin NMI Source Enable (Write Protect) + * | | |0 = External interrupt from PB.8 or PD.11 pin NMI source Disabled. + * | | |1 = External interrupt from PB.8 or PD.11 pin NMI source Enabled. + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * |[17] |EINT7 |External Interrupt From PB.9 or PD.10 Pin NMI Source Enable (Write Protect) + * | | |0 = External interrupt from PB.9 or PD.10 pin NMI source Disabled. + * | | |1 = External interrupt from PB.9 or PD.10 pin NMI source Enabled. + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * @var SYS_INT_T::NMISTS + * Offset: 0x04 NMI source interrupt Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |BODOUT |BOD Interrupt Flag (Read Only) + * | | |0 = BOD interrupt is de-asserted. + * | | |1 = BOD interrupt is asserted. + * |[1] |IRCINT |IRC TRIM Interrupt Flag (Read Only) + * | | |0 = HIRC TRIM interrupt is de-asserted. + * | | |1 = HIRC TRIM interrupt is asserted. + * |[2] |PWRWUINT |Power-down Mode Wake-up Interrupt Flag (Read Only) + * | | |0 = Power-down mode wake-up interrupt is de-asserted. + * | | |1 = Power-down mode wake-up interrupt is asserted. + * |[3] |SRAMPERR |SRAM Parity Check Error Interrupt Flag (Read Only) + * | | |0 = SRAM parity check error interrupt is de-asserted. + * | | |1 = SRAM parity check error interrupt is asserted. + * |[4] |CLKFAIL |Clock Fail Detected Interrupt Flag (Read Only) + * | | |0 = Clock fail detected interrupt is de-asserted. + * | | |1 = Clock fail detected interrupt is asserted. + * |[6] |RTCINT |RTC Interrupt Flag (Read Only) + * | | |0 = RTC interrupt is de-asserted. + * | | |1 = RTC interrupt is asserted. + * |[7] |TAMPERINT |Tamper Interrupt Flag (Read Only) + * | | |0 = Backup register tamper detected interrupt is de-asserted. + * | | |1 = Backup register tamper detected interrupt is asserted. + * |[8] |EINT0 |External Interrupt From PA.6, or PB.5 Pin Interrupt Flag (Read Only) + * | | |0 = External Interrupt from PA.6, or PB.5 interrupt is deasserted. + * | | |1 = External Interrupt from PA.6, or PB.5 interrupt is asserted. + * |[9] |EINT1 |External Interrupt From PA.7, or PB.4 Pin Interrupt Flag (Read Only) + * | | |0 = External Interrupt from PA.7, or PB.4 interrupt is deasserted. + * | | |1 = External Interrupt from PA.7, or PB.4 interrupt is asserted. + * |[10] |EINT2 |External Interrupt From PB.3 or PC.6 Pin Interrupt Flag (Read Only) + * | | |0 = External Interrupt from PB.3 or PC.6 interrupt is deasserted. + * | | |1 = External Interrupt from PB.3 or PC.6 interrupt is asserted. + * |[11] |EINT3 |External Interrupt From PB.2 or PC.7 Pin Interrupt Flag (Read Only) + * | | |0 = External Interrupt from PB.2 or PC.7 interrupt is deasserted. + * | | |1 = External Interrupt from PB.2 or PC.7 interrupt is asserted. + * |[12] |EINT4 |External Interrupt From PA.8 or PB.6 Pin Interrupt Flag (Read Only) + * | | |0 = External Interrupt from PA.8 or PB.6 interrupt is deasserted. + * | | |1 = External Interrupt from PA.8 or PB.6 interrupt is asserted. + * |[13] |EINT5 |External Interrupt From PB.7 or PD.12 Pin Interrupt Flag (Read Only) + * | | |0 = External Interrupt from PB.7 or PD.12 interrupt is deasserted. + * | | |1 = External Interrupt from PB.7 or PD.12 interrupt is asserted. + * |[14] |UART0INT |UART0 Interrupt Flag (Read Only) + * | | |0 = UART1 interrupt is de-asserted. + * | | |1 = UART1 interrupt is asserted. + * |[15] |UART1INT |UART1 Interrupt Flag (Read Only) + * | | |0 = UART1 interrupt is de-asserted. + * | | |1 = UART1 interrupt is asserted. + * |[16] |EINT6 |External Interrupt From PB.8 or PD.11 Pin Interrupt Flag (Read Only) + * | | |0 = External Interrupt from PB.8 or PD.11 interrupt is deasserted. + * | | |1 = External Interrupt from PB.8 or PD.11 interrupt is asserted. + * |[17] |EINT7 |External Interrupt From PB.9 or PD.10 Pin Interrupt Flag (Read Only) + * | | |0 = External Interrupt from PB.9 or PD.10 interrupt is deasserted. + * | | |1 = External Interrupt from PB.9 or PD.10 interrupt is asserted. + */ + + __IO uint32_t NMIEN; /* Offset: 0x00 NMI Source Interrupt Enable Register */ + __I uint32_t NMISTS; /* Offset: 0x04 NMI source interrupt Status Register */ + +} SYS_INT_T; +/** + @addtogroup INT_CONST INT Bit Field Definition + Constant Definitions for INT Controller + @{ +*/ + +#define SYS_NMIEN_BODOUT_Pos (0) /*!< SYS_INT_T::NMIEN: BODOUT Position */ +#define SYS_NMIEN_BODOUT_Msk (0x1ul << SYS_NMIEN_BODOUT_Pos ) /*!< SYS_INT_T::NMIEN: BODOUT Mask */ + +#define SYS_NMIEN_IRCINT_Pos (1) /*!< SYS_INT_T::NMIEN: IRCINT Position */ +#define SYS_NMIEN_IRCINT_Msk (0x1ul << SYS_NMIEN_IRCINT_Pos ) /*!< SYS_INT_T::NMIEN: IRCINT Mask */ + +#define SYS_NMIEN_PWRWUINT_Pos (2) /*!< SYS_INT_T::NMIEN: PWRWUINT Position */ +#define SYS_NMIEN_PWRWUINT_Msk (0x1ul << SYS_NMIEN_PWRWUINT_Pos ) /*!< SYS_INT_T::NMIEN: PWRWUINT Mask */ + +#define SYS_NMIEN_SRAMPERR_Pos (3) /*!< SYS_INT_T::NMIEN: SRAMPERR Position */ +#define SYS_NMIEN_SRAMPERR_Msk (0x1ul << SYS_NMIEN_SRAMPERR_Pos ) /*!< SYS_INT_T::NMIEN: SRAMPERR Mask */ + +#define SYS_NMIEN_CLKFAIL_Pos (4) /*!< SYS_INT_T::NMIEN: CLKFAIL Position */ +#define SYS_NMIEN_CLKFAIL_Msk (0x1ul << SYS_NMIEN_CLKFAIL_Pos ) /*!< SYS_INT_T::NMIEN: CLKFAIL Mask */ + +#define SYS_NMIEN_RTCINT_Pos (6) /*!< SYS_INT_T::NMIEN: RTCINT Position */ +#define SYS_NMIEN_RTCINT_Msk (0x1ul << SYS_NMIEN_RTCINT_Pos ) /*!< SYS_INT_T::NMIEN: RTCINT Mask */ + +#define SYS_NMIEN_TAMPERINT_Pos (7) /*!< SYS_INT_T::NMIEN: TAMPERINT Position */ +#define SYS_NMIEN_TAMPERINT_Msk (0x1ul << SYS_NMIEN_TAMPERINT_Pos ) /*!< SYS_INT_T::NMIEN: TAMPERINT Mask */ + +#define SYS_NMIEN_EINT0_Pos (8) /*!< SYS_INT_T::NMIEN: EINT0 Position */ +#define SYS_NMIEN_EINT0_Msk (0x1ul << SYS_NMIEN_EINT0_Pos ) /*!< SYS_INT_T::NMIEN: EINT0 Mask */ + +#define SYS_NMIEN_EINT1_Pos (9) /*!< SYS_INT_T::NMIEN: EINT1 Position */ +#define SYS_NMIEN_EINT1_Msk (0x1ul << SYS_NMIEN_EINT1_Pos ) /*!< SYS_INT_T::NMIEN: EINT1 Mask */ + +#define SYS_NMIEN_EINT2_Pos (10) /*!< SYS_INT_T::NMIEN: EINT2 Position */ +#define SYS_NMIEN_EINT2_Msk (0x1ul << SYS_NMIEN_EINT2_Pos ) /*!< SYS_INT_T::NMIEN: EINT2 Mask */ + +#define SYS_NMIEN_EINT3_Pos (11) /*!< SYS_INT_T::NMIEN: EINT3 Position */ +#define SYS_NMIEN_EINT3_Msk (0x1ul << SYS_NMIEN_EINT3_Pos ) /*!< SYS_INT_T::NMIEN: EINT3 Mask */ + +#define SYS_NMIEN_EINT4_Pos (12) /*!< SYS_INT_T::NMIEN: EINT4 Position */ +#define SYS_NMIEN_EINT4_Msk (0x1ul << SYS_NMIEN_EINT4_Pos ) /*!< SYS_INT_T::NMIEN: EINT4 Mask */ + +#define SYS_NMIEN_EINT5_Pos (13) /*!< SYS_INT_T::NMIEN: EINT5 Position */ +#define SYS_NMIEN_EINT5_Msk (0x1ul << SYS_NMIEN_EINT5_Pos ) /*!< SYS_INT_T::NMIEN: EINT5 Mask */ + +#define SYS_NMIEN_UART0INT_Pos (14) /*!< SYS_INT_T::NMIEN: UART0INT Position */ +#define SYS_NMIEN_UART0INT_Msk (0x1ul << SYS_NMIEN_UART0INT_Pos ) /*!< SYS_INT_T::NMIEN: UART0INT Mask */ + +#define SYS_NMIEN_UART1INT_Pos (15) /*!< SYS_INT_T::NMIEN: UART1INT Position */ +#define SYS_NMIEN_UART1INT_Msk (0x1ul << SYS_NMIEN_UART1INT_Pos ) /*!< SYS_INT_T::NMIEN: UART1INT Mask */ + +#define SYS_NMIEN_EINT6_Pos (16) /*!< SYS_INT_T::NMIEN: EINT6 Position */ +#define SYS_NMIEN_EINT6_Msk (0x1ul << SYS_NMIEN_EINT6_Pos ) /*!< SYS_INT_T::NMIEN: EINT6 Mask */ + +#define SYS_NMIEN_EINT7_Pos (17) /*!< SYS_INT_T::NMIEN: EINT7 Position */ +#define SYS_NMIEN_EINT7_Msk (0x1ul << SYS_NMIEN_EINT7_Pos ) /*!< SYS_INT_T::NMIEN: EINT7 Mask */ + +#define SYS_NMISTS_BODOUT_Pos (0) /*!< SYS_INT_T::NMISTS: BODOUT Position */ +#define SYS_NMISTS_BODOUT_Msk (0x1ul << SYS_NMISTS_BODOUT_Pos ) /*!< SYS_INT_T::NMISTS: BODOUT Mask */ + +#define SYS_NMISTS_IRCINT_Pos (1) /*!< SYS_INT_T::NMISTS: IRCINT Position */ +#define SYS_NMISTS_IRCINT_Msk (0x1ul << SYS_NMISTS_IRCINT_Pos ) /*!< SYS_INT_T::NMISTS: IRCINT Mask */ + +#define SYS_NMISTS_PWRWUINT_Pos (2) /*!< SYS_INT_T::NMISTS: PWRWUINT Position */ +#define SYS_NMISTS_PWRWUINT_Msk (0x1ul << SYS_NMISTS_PWRWUINT_Pos ) /*!< SYS_INT_T::NMISTS: PWRWUINT Mask */ + +#define SYS_NMISTS_SRAMPERR_Pos (3) /*!< SYS_INT_T::NMISTS: SRAMPERR Position */ +#define SYS_NMISTS_SRAMPERR_Msk (0x1ul << SYS_NMISTS_SRAMPERR_Pos ) /*!< SYS_INT_T::NMISTS: SRAMPERR Mask */ + +#define SYS_NMISTS_CLKFAIL_Pos (4) /*!< SYS_INT_T::NMISTS: CLKFAIL Position */ +#define SYS_NMISTS_CLKFAIL_Msk (0x1ul << SYS_NMISTS_CLKFAIL_Pos ) /*!< SYS_INT_T::NMISTS: CLKFAIL Mask */ + +#define SYS_NMISTS_RTCINT_Pos (6) /*!< SYS_INT_T::NMISTS: RTCINT Position */ +#define SYS_NMISTS_RTCINT_Msk (0x1ul << SYS_NMISTS_RTCINT_Pos ) /*!< SYS_INT_T::NMISTS: RTCINT Mask */ + +#define SYS_NMISTS_TAMPERINT_Pos (7) /*!< SYS_INT_T::NMISTS: TAMPERINT Position */ +#define SYS_NMISTS_TAMPERINT_Msk (0x1ul << SYS_NMISTS_TAMPERINT_Pos ) /*!< SYS_INT_T::NMISTS: TAMPERINT Mask */ + +#define SYS_NMISTS_EINT0_Pos (8) /*!< SYS_INT_T::NMISTS: EINT0 Position */ +#define SYS_NMISTS_EINT0_Msk (0x1ul << SYS_NMISTS_EINT0_Pos ) /*!< SYS_INT_T::NMISTS: EINT0 Mask */ + +#define SYS_NMISTS_EINT1_Pos (9) /*!< SYS_INT_T::NMISTS: EINT1 Position */ +#define SYS_NMISTS_EINT1_Msk (0x1ul << SYS_NMISTS_EINT1_Pos ) /*!< SYS_INT_T::NMISTS: EINT1 Mask */ + +#define SYS_NMISTS_EINT2_Pos (10) /*!< SYS_INT_T::NMISTS: EINT2 Position */ +#define SYS_NMISTS_EINT2_Msk (0x1ul << SYS_NMISTS_EINT2_Pos ) /*!< SYS_INT_T::NMISTS: EINT2 Mask */ + +#define SYS_NMISTS_EINT3_Pos (11) /*!< SYS_INT_T::NMISTS: EINT3 Position */ +#define SYS_NMISTS_EINT3_Msk (0x1ul << SYS_NMISTS_EINT3_Pos ) /*!< SYS_INT_T::NMISTS: EINT3 Mask */ + +#define SYS_NMISTS_EINT4_Pos (12) /*!< SYS_INT_T::NMISTS: EINT4 Position */ +#define SYS_NMISTS_EINT4_Msk (0x1ul << SYS_NMISTS_EINT4_Pos ) /*!< SYS_INT_T::NMISTS: EINT4 Mask */ + +#define SYS_NMISTS_EINT5_Pos (13) /*!< SYS_INT_T::NMISTS: EINT5 Position */ +#define SYS_NMISTS_EINT5_Msk (0x1ul << SYS_NMISTS_EINT5_Pos ) /*!< SYS_INT_T::NMISTS: EINT5 Mask */ + +#define SYS_NMISTS_UART0INT_Pos (14) /*!< SYS_INT_T::NMISTS: UART0_INT Position */ +#define SYS_NMISTS_UART0INT_Msk (0x1ul << SYS_NMISTS_UART0INT_Pos ) /*!< SYS_INT_T::NMISTS: UART0_INT Mask */ + +#define SYS_NMISTS_UART1INT_Pos (15) /*!< SYS_INT_T::NMISTS: UART1_INT Position */ +#define SYS_NMISTS_UART1INT_Msk (0x1ul << SYS_NMISTS_UART1INT_Pos ) /*!< SYS_INT_T::NMISTS: UART1_INT Mask */ + +#define SYS_NMISTS_EINT6_Pos (16) /*!< SYS_INT_T::NMISTS: EINT6 Position */ +#define SYS_NMISTS_EINT6_Msk (0x1ul << SYS_NMISTS_EINT6_Pos ) /*!< SYS_INT_T::NMISTS: EINT6 Mask */ + +#define SYS_NMISTS_EINT7_Pos (17) /*!< SYS_INT_T::NMISTS: EINT7 Position */ +#define SYS_NMISTS_EINT7_Msk (0x1ul << SYS_NMISTS_EINT7_Pos ) /*!< SYS_INT_T::NMISTS: EINT7 Mask */ + + +/**@}*/ /* INT_CONST */ +/**@}*/ /* end of SYS register group */ +/**@}*/ /* end of REGISTER group */ + + +#endif /* __SYS_REG_H__ */ diff --git a/Ubiquitous/XiZi/board/nuvoton-m2354/third_party_driver/include/Regs/system_M2354.h b/Ubiquitous/XiZi/board/nuvoton-m2354/third_party_driver/include/Regs/system_M2354.h new file mode 100644 index 0000000..edf1e3e --- /dev/null +++ b/Ubiquitous/XiZi/board/nuvoton-m2354/third_party_driver/include/Regs/system_M2354.h @@ -0,0 +1,148 @@ +/**************************************************************************//** + * @file system_M2354.h + * @version V3.00 + * @brief System Setting Header File + * + * @copyright SPDX-License-Identifier: Apache-2.0 + * @copyright Copyright (C) 2020 Nuvoton Technology Corp. All rights reserved. + ******************************************************************************/ +#ifndef __SYSTEM_M2354_H__ +#define __SYSTEM_M2354_H__ + +#ifdef __cplusplus +extern "C" { +#endif +/*---------------------------------------------------------------------------------------------------------*/ +/* Macro Definition */ +/*---------------------------------------------------------------------------------------------------------*/ +#ifndef DEBUG_PORT +# define DEBUG_PORT UART0 /*!< Select Debug Port which is used for retarget.c to output debug message to UART */ +#endif + + +/* Init ETM Interface Multi-function Pins */ +#define ETM_INIT() { \ + SYS->GPC_MFPL &= ~(SYS_GPC_MFPL_PC0MFP_ETM_TRACE_Msk | SYS_GPC_MFPL_PC1MFP_ETM_TRACE_Msk | \ + SYS_GPC_MFPL_PC2MFP_ETM_TRACE_Msk | SYS_GPC_MFPL_PC3MFP_ETM_TRACE_Msk | \ + SYS_GPC_MFPL_PC4MFP_ETM_TRACE_Msk); \ + SYS->GPC_MFPL |= SYS_GPC_MFPL_PC0MFP_ETM_TRACE_CLK | SYS_GPC_MFPL_PC1MFP_ETM_TRACE_DATA0 | \ + SYS_GPC_MFPL_PC2MFP_ETM_TRACE_DATA1 | SYS_GPC_MFPL_PC3MFP_ETM_TRACE_DATA2 | \ + SYS_GPC_MFPL_PC4MFP_ETM_TRACE_DATA3;} + + + + + +/** + * + * @details This is used to enable PLL to speed up booting at startup. Remove it will cause system using + * default clock source (External crystal or internal 22.1184MHz IRC). + * Enable this option will cause system booting in 72MHz(By XTAL) or 71.8848MHz(By IRC22M) according to + * user configuration setting in CONFIG0 + * + */ + +/* +#define INIT_SYSCLK_AT_BOOTING +*/ + +/*---------------------------------------------------------------------------- + Define SYSCLK + *----------------------------------------------------------------------------*/ +#ifndef __HXT +#define __HXT (12000000UL) /*!< External Crystal Clock Frequency */ +#endif + +#define __LIRC (32000UL) /*!< Internal 32K RC Oscillator Frequency */ +#define __HIRC (12000000UL) /*!< Internal 12M RC Oscillator Frequency */ + +#ifndef __LXT +#define __LXT (32768UL) /*!< External Crystal Clock Frequency 32.768KHz */ +#endif + +#ifndef __HSI +#define __HSI (48000000UL) /*!< PLL Output Clock Frequency */ +#endif + +#define __HIRC48 (48000000UL) /*!< Internal 48M RC Oscillator Frequency */ +#define __LIRC32 (32000UL) /*!< Internal 32K RC Oscillator Frequency */ +#define __MIRC (4000000UL) /*!< Internal 4M RC Oscillator Frequency */ + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3L) +# if defined (__ICCARM__) +# define __NONSECURE_ENTRY __cmse_nonsecure_entry +# define __NONSECURE_ENTRY_WEAK __cmse_nonsecure_entry //__weak +# define __NONSECURE_CALL __cmse_nonsecure_call +# else +# define __NONSECURE_ENTRY __attribute__((cmse_nonsecure_entry)) +# define __NONSECURE_ENTRY_WEAK __attribute__((cmse_nonsecure_entry,weak)) +# define __NONSECURE_CALL __attribute__((cmse_nonsecure_call)) +# endif +#else +# define __NONSECURE_ENTRY +# define __NONSECURE_ENTRY_WEAK +# define __NONSECURE_CALL +#endif + + + +extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */ +extern uint32_t CyclesPerUs; /*!< Cycles per micro second */ +extern uint32_t PllClock; /*!< PLL Output Clock Frequency */ +extern uint32_t __PC(void); /*!< Return the current program counter value */ + +#if USE_ASSERT +/** + * @brief Assert Function + * + * @param[in] expr Expression to be evaluated + * + * @details If the expression is false, an error message will be printed out + * from debug port (UART0 or UART1). + */ +#define ASSERT_PARAM(expr) { if (!(expr)) { AssertError((uint8_t*)__FILE__, __LINE__); } } + +void AssertError(uint8_t *file, uint32_t line); +#else +#define ASSERT_PARAM(expr) +#endif + +#define assert_param(expr) ASSERT_PARAM(expr) + + +/** + * @brief System Initialization + * + * @details The necessary initialization of system. + */ +extern void SystemInit(void); + + +/** + * @brief Update the Variable SystemCoreClock + * + * @details This function is used to update the variable SystemCoreClock + * and must be called whenever the core clock is changed. + */ +extern void SystemCoreClockUpdate(void); + + + + +#if (defined(__ICCARM__) && (__VER__ >= 7080000) && (__VER__ < 8020000)) +uint32_t __TZ_get_PSP_NS(void); +void __TZ_set_PSP_NS(uint32_t topOfProcStack); +int32_t __TZ_get_MSP_NS(void); +void __TZ_set_MSP_NS(uint32_t topOfMainStack); +uint32_t __TZ_get_PRIMASK_NS(void); +void __TZ_set_PRIMASK_NS(uint32_t priMask); +#endif + + + +#ifdef __cplusplus +} +#endif + +#endif /* __SYSTEM_M2354_H__ */ diff --git a/Ubiquitous/XiZi/board/nuvoton-m2354/third_party_driver/include/Regs/tamper_reg.h b/Ubiquitous/XiZi/board/nuvoton-m2354/third_party_driver/include/Regs/tamper_reg.h new file mode 100644 index 0000000..147bef8 --- /dev/null +++ b/Ubiquitous/XiZi/board/nuvoton-m2354/third_party_driver/include/Regs/tamper_reg.h @@ -0,0 +1,1042 @@ +/**************************************************************************//** + * @file tamper_reg.h + * @version V1.00 + * @brief Tamper register definition header file + * + * @copyright SPDX-License-Identifier: Apache-2.0 + * @copyright Copyright (C) 2020 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ +#ifndef __TAMPER_REG_H__ +#define __TAMPER_REG_H__ + +/** @addtogroup REGISTER Control Register + + @{ + +*/ + + +/*---------------------------- Tamper Controller ----------------------------*/ +/** + @addtogroup Tamper Controller(TAMPER) + Memory Mapped Structure for Tamper Controller + @{ +*/ + +typedef struct +{ + + + /** + * @var TAMPER_T::INIT + * Offset: 0x00 Tamper Function Initiation Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |TCORERST |Tamper Core Reset + * | | |0 = Write 0x5500; the Tamper core block reset will be released. + * | | |1 = Write 0x55AA; the Tamper core block will be reset. + * |[31] |TLDORDY |Voltage Regulator Power Ready (Read Only) + * | | |0 = The power status of voltage regulator is not ready. + * | | |1 = The power status of voltage regulator is ready. + * @var TAMPER_T::FUNEN + * Offset: 0x04 Tamper Block Function Enable Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |LXTDETEN |LXT Clock Detection Enable Bit + * | | |0 = Write 0x40; the LXT clock detection Disabled. + * | | |1 = Write 0x44; the LXT clock detection Enabled. + * |[13:8] |TMPIOSEL |Tamper I/O Detection Selection Bit + * | | |0 = Write 0x90/0xA0/0xB0/0xC0/0xD0/0xE0 for tamper I/O 0~5; the I/O tamper function is detected through RTC block. + * | | |1 = Write 0x94/0xA4/0xB4/0xC4/0xD4/0xE4 for tamper I/O 0~5; the I/O tamper function is detected through Tamper block. + * |[23:16] |HIRC48MEN |HIRC48M Enable Bit + * | | |The HIRC48M is disabled when these bits equal 0x5A, otherwise it will be enabled with any other values. + * |[24] |VGCHEN0 |Voltage Glitch Channel 0 Enable Bit + * | | |0 = Voltage glitch channel 0 Disabled. + * | | |1 = Voltage glitch channel 0 Enabled. + * | | |Note: To avoid the voltage glitch when the voltage channel is enabled, it is better to detect the voltage glitch about 150us after the channel is enabled. + * |[25] |VGCHEN1 |Voltage Glitch Channel 1 Enable Bit + * | | |0 = Voltage glitch channel 1 Disabled. + * | | |1 = Voltage glitch channel 1 Enabled. + * | | |Note: To avoid the voltage glitch when the voltage channel is enabled, it is better to detect the voltage glitch about 150us after the channel is enabled. + * |[26] |VGCHEN2 |Voltage Glitch Channel 2 Enable Bit + * | | |0 = Voltage glitch channel 2 Disabled. + * | | |1 = Voltage glitch channel 2 Enabled. + * | | |Note: To avoid the voltage glitch when the voltage channel is enabled, it is better to detect the voltage glitch about 150us after the channel is enabled. + * |[27] |VGCHEN3 |Voltage Glitch Channel 3 Enable Bit + * | | |0 = Voltage glitch channel 3 Disabled. + * | | |1 = Voltage glitch channel 3 Enabled. + * | | |Note: To avoid the voltage glitch when the voltage channel is enabled, it is better to detect the voltage glitch about 150us after the channel is enabled. + * @var TAMPER_T::TRIEN + * Offset: 0x08 Tamper Trigger Enable Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[1] |KSTRIGEN |Key Store Trigger Enable Bit + * | | |0 = Tamper event is detected and to trigger Key Store Disabled. + * | | |1 = Tamper event is detected and to trigger Key Store Enabled. + * |[2] |WAKEUPEN |Wakeup Enable Bit + * | | |0 = Tamper wakeup event Disabled. + * | | |1 = Tamper wakeup event Enabled. + * |[3] |CRYPTOEN |Crypto Enable Bit + * | | |0 = Tamper event clear Crypto Disabled. + * | | |1 = Tamper event clear Crypto Enabled. + * |[4] |CHIPRSTEN |Chip Reset Enable Bit + * | | |0 = Tamper event trigger chip reset Disabled. + * | | |1 = Tamper event trigger chip reset Enabled. + * |[5] |RTCSPCLREN|RTC Spare Register Clear Enable Bit + * | | |0 = Tamper event trigger RTC spare register reset Disabled. + * | | |1 = Tamper event trigger RTC spare register reset Enabled. + * @var TAMPER_T::INTEN + * Offset: 0x0C Tamper Event Interrupt Enable Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |TAMP0IEN |Tamper 0 Event Interrupt Enable Bit + * | | |0 = Tamper 0 event interrupt Disabled. + * | | |1 = Tamper 0 event interrupt Enabled. + * |[1] |TAMP1IEN |Tamper 1 or Pair 0 Event Interrupt Enable Bit + * | | |0 = Tamper 1 or Pair 0 event interrupt Disabled. + * | | |1 = Tamper 1 or Pair 0 event interrupt Enabled. + * |[2] |TAMP2IEN |Tamper 2 Event Interrupt Enable Bit + * | | |0 = Tamper 2 event interrupt Disabled. + * | | |1 = Tamper 2 event interrupt Enabled. + * |[3] |TAMP3IEN |Tamper 3 or Pair 1 Event Interrupt Enable Bit + * | | |0 = Tamper 3 or Pair 1 event interrupt Disabled. + * | | |1 = Tamper 3 or Pair 1 event interrupt Enabled. + * |[4] |TAMP4IEN |Tamper 4 Event Interrupt Enable Bit + * | | |0 = Tamper 4 event interrupt Disabled. + * | | |1 = Tamper 4 event interrupt Enabled. + * |[5] |TAMP5IEN |Tamper 5 or Pair 2 Event Interrupt Enable Bit + * | | |0 = Tamper 5 or Pair 2 event interrupt Disabled. + * | | |1 = Tamper 5 or Pair 2 event interrupt Enabled. + * |[6] |CLKFIEN |LXT Clock Frequency Monitor Fail Event Interrupt Enable Bit + * | | |0 = LXT frequency fail event interrupt Disabled. + * | | |1 = LXT frequency fail event interrupt Enabled. + * |[7] |CLKSTOPIEN|LXT Clock Frequency Monitor Stop Event Interrupt Enable Bit + * | | |0 = LXT frequency stop event interrupt Disabled. + * | | |1 = LXT frequency stop event interrupt Enabled. + * |[8] |OVPIEN |VDD Over Voltage Protect Detection Interrupt Enable Bit + * | | |0 = Detect VDD over voltage protect detection interrupt Disabled. + * | | |1 = Detect VDD over voltage protect detection interrupt Enabled. + * | | |Note: The function enable of the over voltage detection is defined in system manager. + * |[9] |VGPIEN |Voltage Glitch Positive Detection Event Interrupt Enable Bit + * | | |0 = LDO_CAP positive glitch event interrupt Disabled. + * | | |1 = LDO_CAP positive glitch event interrupt Enabled. + * |[10] |VGNIEN |Voltage Glitch Negative Detection Event Interrupt Enable Bit + * | | |0 = LDO_CAP negative glitch event interrupt Disabled. + * | | |1 = LDO_CAP negative glitch event interrupt Enabled. + * |[11] |ACTSIEN |Active Shield Event Interrupt Enable Bit + * | | |0 = Active shield event interrupt Disabled. + * | | |1 = Active shield event interrupt Enabled. + * |[16] |RTCLVRIEN |RTC Low Voltage Detection Event Interrupt Enable Bit + * | | |0 = VBAT low voltage detection event interrupt Disabled. + * | | |1 = VBAT low voltage detection event interrupt Enabled. + * |[17] |RTCIOIEN |RTC Tamper I/O Event Interrupt Enable Bit + * | | |0 = RTC tamper I/O detection event interrupt Disabled. + * | | |1 = RTC tamper I/O detection event interrupt Enabled. + * |[18] |RTCLKIEN |RTC Clock Monitor Detection Event Interrupt Enable Bit + * | | |0 = RTC clock monitor event interrupt Disabled. + * | | |1 = RTC clock monitor event interrupt Enabled. + * |[22] |BODIEN |BOD Event Interrupt Enable Bit + * | | |0 = Brown-out event interrupt Disabled. + * | | |1 = Brown-out event interrupt Enabled. + * @var TAMPER_T::INTSTS + * Offset: 0x10 Tamper Interrupt Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |TAMP0IF |Tamper 0 Event Interrupt Flag + * | | |0 = No Tamper 0 event interrupt flag is generated. + * | | |1 = Tamper 0 event interrupt flag is generated. + * | | |Note: Write 1 to clear this bit. + * |[1] |TAMP1IF |Tamper 1 Event Interrupt Flag + * | | |0 = No Tamper 1 event interrupt flag is generated. + * | | |1 = Tamper 1 event interrupt flag is generated. + * | | |Note: Write 1 to clear this bit. + * |[2] |TAMP2IF |Tamper 2 Event Interrupt Flag + * | | |0 = No Tamper 2 event interrupt flag is generated. + * | | |1 = Tamper 2 event interrupt flag is generated. + * | | |Note: Write 1 to clear this bit. + * |[3] |TAMP3IF |Tamper 3 Event Interrupt Flag + * | | |0 = No Tamper 3 event interrupt flag is generated. + * | | |1 = Tamper 3 event interrupt flag is generated. + * | | |Note: Write 1 to clear this bit. + * |[4] |TAMP4IF |Tamper 4 Event Interrupt Flag + * | | |0 = No Tamper 4 event interrupt flag is generated. + * | | |1 = Tamper 4 event interrupt flag is generated. + * | | |Note: Write 1 to clear this bit. + * |[5] |TAMP5IF |Tamper 5 Event Interrupt Flag + * | | |0 = No Tamper 5 event interrupt flag is generated. + * | | |1 = Tamper 5 event interrupt flag is generated. + * | | |Note: Write 1 to clear this bit. + * |[6] |CLKFAILIF |LXT Clock Frequency Monitor Fail Event Interrupt Flag + * | | |0 = LXT frequency is normal. + * | | |1 = LXT frequency is abnormal. + * | | |Note 1: Write 1 to clear this bit to 0. + * | | |Note 2: LXT detector will be automatically disabled when Fail/Stop flag rises, and resumes after Fail/Stop flag is cleared. + * |[7] |CLKSTOPIF |LXT Clock Frequency Monitor Stop Event Interrupt Flag + * | | |0 = LXT frequency is normal. + * | | |1 = LXT frequency is almost stopped. + * | | |Note 1: Write 1 to clear this bit to 0. + * | | |Note 2: LXT detector will be automatically disabled when Fail/Stop flag rises, and resumes after Fail/Stop flag is cleared. + * |[8] |OVPOUTIF |VDD Over Voltage Event Interrupt Flag + * | | |0 = VDD no over voltage is detected. + * | | |1 = VDD over voltage is detected. + * | | |Note: Write 1 to clear this bit. + * |[9] |VGPEVIF |Voltage Glitch Positive Detection Interrupt Flag + * | | |0 = LDO_CAP positive glitch is not detected. + * | | |1 = LDO_CAP positive glitch is detected. + * | | |Note: It can be written 1 to clear only (No clear by TCORERST) + * |[10] |VGNEVIF |Voltage Glitch Negative Detection Interrupt Flag + * | | |0 = LDO_CAP negative glitch is not detected. + * | | |1 = LDO_CAP negative glitch is detected. + * | | |Note: It can be written 1 to clear only (No clear by TCORERST) + * |[11] |ACTSEIF |Active Shield Event Detection Interrupt Flag + * | | |0 = Active shield event interrupt flag is not detected. + * | | |1 = Active shield event interrupt flag is detected including the voltage of voltage regulator and GND attack. + * | | |Note: Write 1 to clear this bit after all of ACTSTxIF bits have been cleaned. + * |[13] |ACTST5IF |Active Shield Tamper 5 Event Interrupt Flag + * | | |0 = No Active shield Tamper 5 event interrupt flag is generated. + * | | |1 = Active shield Tamper 5 event interrupt flag is generated. + * | | |Note: Write 1 to clear this bit. + * |[15] |ACTST25IF |Active Shield Tamper 5 Event Interrupt Flag + * | | |0 = No Active shield Tamper 5 event interrupt flag is generated. + * | | |1 = 2th Active shield Tamper 5 event interrupt flag is generated. + * | | |Note: Write 1 to clear this bit. + * |[16] |RTCLVRIF |RTC Low Voltage Detection Event Interrupt Flag + * | | |0 = VBAT low voltage detection event interrupt flag is not detected. + * | | |1 = VBAT low voltage detection event interrupt flag is detected. + * |[17] |RIOTRIGIF |RTC Tamper I/O Event Interrupt Flag + * | | |0 = There is no RTC tamper I/O detection event interrupt flag. + * | | |1 = There is RTC tamper I/O detection event interrupt flag. + * |[18] |RCLKTRIGIF|RTC Clock Monitor Detection Event Interrupt Flag + * | | |0 = There is no RTC clock monitor detection event interrupt flag. + * | | |1 = There is RTC clock monitor detection event interrupt flag. + * |[22] |BODIF |BOD Event Interrupt Flag + * | | |0 = Brown-out event interrupt flag is no detected. + * | | |1 = Brown-out interrupt flag is detected. + * | | |Note: It is used to detect the LDO_CAP. Write 1 to clear this bit. + * |[25] |ACTST1IF |Active Shield Tamper 1 Event Interrupt Flag + * | | |0 = No Active shield Tamper 1 event interrupt flag is generated. + * | | |1 = Active shield Tamper 1 event interrupt flag is generated. + * | | |Note: Write 1 to clear this bit. + * |[27] |ACTST3IF |Active Shield Tamper 3 Event Interrupt Flag + * | | |0 = No Active shield Tamper 3 event interrupt flag is generated. + * | | |1 = Active shield Tamper 3 event interrupt flag is generated. + * | | |Note: Write 1 to clear this bit. + * |[29] |ACTST21IF |2th Active Shield Tamper 1 Event Interrupt Flag + * | | |0 = No Active shield Tamper 1 event interrupt flag is generated. + * | | |1 = 2th Active shield Tamper 1 event interrupt flag is generated. + * | | |Note: Write 1 to clear this bit. + * |[31] |ACTST23IF |2th Active Shield Tamper 3 Event Interrupt Flag + * | | |0 = No Active shield Tamper 3 event interrupt flag is generated. + * | | |1 = 2th Active shield Tamper 3 event interrupt flag is generated. + * | | |Note: Write 1 to clear this bit. + * @var TAMPER_T::LIRCTL + * Offset: 0x14 Tamper LIRC Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[8:0] |TLRCTRIM |Tamper TLIRC32K Trim Value + * | | |TLIRC32K trim value setting + * |[10:9] |TRIMMOS |Tamper TLIRC32K Trim MOS Value + * | | |TLIRC32K trim MOS value setting + * @var TAMPER_T::TIOCTL + * Offset: 0x18 Tamper I/O Function Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |DYN1ISS |Dynamic Pair 1 Input Source Select + * | | |This bit determines Tamper 3 input is from Tamper 2 or Tamper 0 in dynamic mode. + * | | |0 = Tamper input is from Tamper 2. + * | | |1 = Tamper input is from Tamper 0. + * | | |Note: This bit is effective only when DYNPR1EN (TAMPER_TIOCTL[23]) and DYNPR0EN (TAMPER_TIOCTL[15]) are set. + * |[1] |DYN2ISS |Dynamic Pair 2 Input Source Select + * | | |This bit determines Tamper 5 input is from Tamper 4 or Tamper 0 in dynamic mode. + * | | |0 = Tamper input is from Tamper 4. + * | | |1 = Tamper input is from Tamper 0. + * | | |Note: This bit has effect only when DYNPR2EN (TAMPER_TIOCTL[31]) and DYNPR0EN (TAMPER_TIOCTL[15]) are set. + * |[3] |DYNSRC |Dynamic Reference Pattern + * | | |This field determines the new reference pattern when current pattern run out in dynamic pair mode. + * | | |0 = The new reference pattern is generated by random number generator when the reference pattern run out. + * | | |1 = The new reference pattern is repeated from SEED (TAMPER_SEED[31:0]) when the reference pattern run out. + * | | |Note: After this bit is modified, the SEEDRLD (TAMPER_TIOCTL[4]) should be set. + * |[4] |SEEDRLD |Reload New Seed for PRNG Engine + * | | |Setting this bit, the tamper configuration will be reloaded. + * | | |0 = Generating key based on the current seed. + * | | |1 = Reload new seed. + * | | |Note 1: Before this bit is set, the tamper configuration should be set to complete and this bit will be auto clear to 0 after reload new seed completed. + * | | |Note 2: The reference is RTC-clock. Tamper detector needs sync 2 ~ 3 RTC-clock. + * |[7:5] |DYNRATE |Dynamic Change Rate + * | | |This item is choice the dynamic tamper output change rate. + * | | |000 = 26 * RTC_CLK. + * | | |001 = 27 * RTC_CLK. + * | | |010 = 28 * RTC_CLK. + * | | |011 = 29 * RTC_CLK. + * | | |100 = 210 * RTC_CLK. + * | | |101 = 211 * RTC_CLK. + * | | |110 = 212 * RTC_CLK. + * | | |111 = 213 * RTC_CLK. + * | | |Note: After revising this field, setting SEEDRLD (TAMPER_TIOCTL[4]) can reload change rate immediately. + * |[8] |TAMP0EN |Tamper0 Detect Enable Bit + * | | |0 = Tamper 0 detect Disabled. + * | | |1 = Tamper 0 detect Enabled. + * | | |Note: The reference is RTC-clock. Tamper detector needs sync 2 ~ 3 RTC-clock. + * |[9] |TAMP0LV |Tamper 0 Level + * | | |This bit depends on level attribute of tamper pin for static tamper detection. + * | | |0 = Detect voltage level is low. + * | | |1 = Detect voltage level is high. + * |[10] |TAMP0DBEN |Tamper 0 De-bounce Enable Bit + * | | |0 = Tamper 0 de-bounce Disabled. + * | | |1 = Tamper 0 de-bounce Enabled. Tamper detection pin will sync 1 RTC clock. + * |[12] |TAMP1EN |Tamper 1 Detect Enable Bit + * | | |0 = Tamper 1 detect Disabled. + * | | |1 = Tamper 1 detect Enabled. + * | | |Note: The reference is RTC-clock. Tamper detector needs sync 2 ~ 3 RTC-clock. + * |[13] |TAMP1LV |Tamper 1 Level + * | | |This bit depends on level attribute of tamper pin for static tamper detection. + * | | |0 = Detect voltage level is low. + * | | |1 = Detect voltage level is high. + * |[14] |TAMP1DBEN |Tamper 1 De-bounce Enable Bit + * | | |0 = Tamper 1 de-bounce Disabled. + * | | |1 = Tamper 1 de-bounce Enabled, tamper detection pin will sync 1 RTC clock. + * |[15] |DYNPR0EN |Dynamic Pair 0 Enable Bit + * | | |0 = Static detect. + * | | |1 = Dynamic detect. + * |[16] |TAMP2EN |Tamper 2 Detect Enable Bit + * | | |0 = Tamper 2 detect Disabled. + * | | |1 = Tamper 2 detect Enabled. + * | | |Note: The reference is RTC-clock. Tamper detector need sync 2 ~ 3 RTC-clock. + * |[17] |TAMP2LV |Tamper 2 Level + * | | |This bit depends on level attribute of tamper pin for static tamper detection. + * | | |0 = Detect voltage level is low. + * | | |1 = Detect voltage level is high. + * |[18] |TAMP2DBEN |Tamper 2 De-bounce Enable Bit + * | | |0 = Tamper 2 de-bounce Disabled. + * | | |1 = Tamper 2 de-bounce Enabled. Tamper detection pin will sync 1 RTC clock. + * |[20] |TAMP3EN |Tamper 3 Detect Enable Bit + * | | |0 = Tamper 3 detect Disabled. + * | | |1 = Tamper 3 detect Enabled. + * | | |Note: The reference is RTC-clock. Tamper detector needs sync 2 ~ 3 RTC-clock. + * |[21] |TAMP3LV |Tamper 3 Level + * | | |This bit depends on level attribute of tamper pin for static tamper detection. + * | | |0 = Detect voltage level is low. + * | | |1 = Detect voltage level is high. + * |[22] |TAMP3DBEN |Tamper 3 De-bounce Enable Bit + * | | |0 = Tamper 3 de-bounce Disabled. + * | | |1 = Tamper 3 de-bounce Enabled. Tamper detection pin will sync 1 RTC clock. + * |[23] |DYNPR1EN |Dynamic Pair 1 Enable Bit + * | | |0 = Static detect. + * | | |1 = Dynamic detect. + * |[24] |TAMP4EN |Tamper4 Detect Enable Bit + * | | |0 = Tamper 4 detect Disabled. + * | | |1 = Tamper 4 detect Enabled. + * | | |Note: The reference is RTC-clock. Tamper detector needs sync 2 ~ 3 RTC-clock. + * |[25] |TAMP4LV |Tamper 4 Level + * | | |This bit depends on level attribute of tamper pin for static tamper detection. + * | | |0 = Detect voltage level is low. + * | | |1 = Detect voltage level is high. + * |[26] |TAMP4DBEN |Tamper 4 De-bounce Enable Bit + * | | |0 = Tamper 4 de-bounce Disabled. + * | | |1 = Tamper 4 de-bounce Enabled. Tamper detection pin will sync 1 RTC clock. + * |[28] |TAMP5EN |Tamper 5 Detect Enable Bit + * | | |0 = Tamper 5 detect Disabled. + * | | |1 = Tamper 5 detect Enabled. + * | | |Note: The reference is RTC-clock. Tamper detector needs sync 2 ~ 3 RTC-clock. + * |[29] |TAMP5LV |Tamper 5 Level + * | | |This bit depends on level attribute of tamper pin for static tamper detection. + * | | |0 = Detect voltage level is low. + * | | |1 = Detect voltage level is high. + * |[30] |TAMP5DBEN |Tamper 5 De-bounce Enable Bit + * | | |0 = Tamper 5 de-bounce Disabled. + * | | |1 = Tamper 5 de-bounce Enabled. Tamper detection pin will sync 1 RTC clock. + * |[31] |DYNPR2EN |Dynamic Pair 2 Enable Bit + * | | |0 = Static detect. + * | | |1 = Dynamic detect. + * @var TAMPER_T::SEED + * Offset: 0x1C Tamper Seed Value Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |SEED |Seed value. + * @var TAMPER_T::SEED2 + * Offset: 0x20 Tamper 2nd Seed Value Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |SEED2 |Seed value. These seed value are used for 2nd active shield I/O. + * @var TAMPER_T::ACTSTIOCTL1 + * Offset: 0x24 Tamper Active Shield Tamper I/O Function Control Register 1 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |ADYN1ISS |Active Shied Dynamic Pair 1 Input Source Select + * | | |This bit determines Tamper 3 input is from Tamper 2 or Tamper 0 in dynamic mode. + * | | |0 = Tamper input is from Tamper 2. + * | | |1 = Tamper input is from Tamper 0. + * | | |Note: This bit is effective only when ADYNPR1EN (TAMPER_ACTSTIOCTL1[23]) and ADYNPR0EN (TAMPER_ACTSTIOCTL1[15]) are set. + * |[3] |ADYNSRC |Active Shied Dynamic Reference Pattern + * | | |This field determines the new reference pattern when current pattern run out in dynamic pair mode. + * | | |0 = The new reference pattern is generated by random number generator when the reference pattern run out. + * | | |1 = The new reference pattern is repeated from SEED (TAMPER_SEED[31:0]) when the reference pattern run out. + * | | |Note: After this bit is modified, the SEEDRLD (TAMPER_TIOCTL[4]) should be set. + * |[7:5] |ADYNRATE |Active Shied Dynamic Change Rate + * | | |Use the bits to choose the dynamic tamper output change rate. + * | | |000 = 210 * TLIRC32K. + * | | |001 = 211 * TLIRC32K. + * | | |010 = 212 * TLIRC32K. + * | | |011 = 213 * TLIRC32K. + * | | |100 = 214 * TLIRC32K. + * | | |101 = 215 * TLIRC32K. + * | | |110 = 216 * TLIRC32K. + * | | |111 = 217 * TLIRC32K. + * | | |Note: After this field is modified, setting SEEDRLD (TAMPER_TIOCTL[4]) can reload the change rate immediately. + * |[8] |ATAMP0EN |Active Shied Tamper0 Detect Enable Bit + * | | |0 = Tamper 0 detect Disabled. + * | | |1 = Tamper 0 detect Enabled. + * | | |Note: The reference is TLIRC 32K-clock. Tamper detector need sync 2 ~ 3 TLIRC 32K-clock. + * |[12] |ATAMP1EN |Active Shied Tamper 1 Detect Enable Bit + * | | |0 = Tamper 1 detect Disabled. + * | | |1 = Tamper 1 detect Enabled. + * | | |Note: The reference is TLIRC 32K-clock. Tamper detector needs sync 2 ~ 3 TLIRC 32K-clock. + * |[15] |ADYNPR0EN |Active Shied Dynamic Pair 0 Enable Bit + * | | |0 = Static detect (Not supported). + * | | |1 = Dynamic detect. + * |[16] |ATAMP2EN |Active Shied Tamper 2 Detect Enable Bit + * | | |0 = Tamper 2 detect Disabled. + * | | |1 = Tamper 2 detect Enabled. + * | | |Note: The reference is TLIRC 32K-clock. Tamper detector needs sync 2 ~ 3 TLIRC 32K-clock. + * |[20] |ATAMP3EN |Active Shied Tamper 3 Detect Enable Bit + * | | |0 = Tamper 3 detect Disabled. + * | | |1 = Tamper 3 detect Enabled. + * | | |Note: The reference is TLIRC 32K-clock. Tamper detector needs sync 2 ~ 3 TLIRC 32K-clock. + * |[23] |ADYNPR1EN |Active Shied Dynamic Pair 1 Enable Bit + * | | |0 = Static detect (Not supported). + * | | |1 = Dynamic detect. + * |[24] |ATAMP4EN |Active Tamper4 Detect Enable Bit + * | | |0 = Tamper 4 detect Disabled. + * | | |1 = Tamper 4 detect Enabled. + * | | |Note: The reference is TLIRC 32K-clock. Tamper detector need sync 2 ~ 3 TLIRC 32K-clock. + * |[28] |ATAMP5EN |Active Tamper 5 Detect Enable Bit + * | | |0 = Tamper 5 detect Disabled. + * | | |1 = Tamper 5 detect Enabled. + * | | |Note: The reference is TLIRC 32K-clock. Tamper detector need sync 2 ~ 3 TLIRC 32K-clock. + * |[31] |ADYNPR2EN |Active Shied Dynamic Pair 2 Enable Bit + * | | |0 = Static detect (Not supported). + * | | |1 = Dynamic detect. + * @var TAMPER_T::ACTSTIOCTL2 + * Offset: 0x28 Tamper Active Shield Tamper I/O Function Control Register 2 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |ADYN1ISS2 |Active Shied Dynamic Pair 1 Input Source Select 2 + * | | |This bit determines if Tamper 3 input is from Tamper 2 or Tamper 0 in dynamic mode. + * | | |0 = Tamper input is from Tamper 2. + * | | |1 = Tamper input is from Tamper 0. + * | | |Note: This bit is effective only when ADYNPR1EN2 (TAMPER_ACTSTIOCTL2[23]) and ADYNPR0EN2 (TAMPER_ACTSTIOCTL2[15]) are set. + * |[3] |ADYNSRC2 |Active Shied Dynamic Reference Pattern 2 + * | | |This field determines the new reference pattern when current pattern run out in dynamic pair mode. + * | | |0 = The new reference pattern is generated by random number generator when the reference pattern run out. + * | | |1 = The new reference pattern is repeated from SEED2 (TAMPER_SEED2[31:0]) when the reference pattern run out. + * | | |Note: After this bit is modified, the SEEDRLD2 (TAMPER_ACTSTIOCTL2[4]) should be set. + * |[4] |SEEDRLD2 |Reload New Seed for PRNG Engine 2 + * | | |Setting this bit, the tamper configuration will be reloaded. + * | | |0 = Generating key based on the current seed. + * | | |1 = Reload new seed. + * | | |Note 1: Before this bit is set, the tamper configuration should be set to complete and this bit will be auto clear to 0 after reload new seed completed. + * | | |Note 2: The reference is TLIRC 32K-clock. Tamper detector needs sync 2 ~ 3 TLIRC 32K-clock. + * |[7:5] |ADYNRATE2 |Active Shied Dynamic Change Rate 2 + * | | |Use the bits to choose the dynamic tamper output change rate. + * | | |000 = 210 * TLIRC32K. + * | | |001 = 211 * TLIRC32K. + * | | |010 = 212 * TLIRC32K. + * | | |011 = 213 * TLIRC32K. + * | | |100 = 214 * TLIRC32K. + * | | |101 = 215 * TLIRC32K. + * | | |110 = 216 * TLIRC32K. + * | | |111 = 217 * TLIRC32K. + * | | |Note: After this field is modified, setting SEEDRLD2 (TAMPER_ACTSTIOCTL2[4]) can reload change rate immediately. + * |[8] |ATAMP0EN2 |Active Shied Tamper0 Detect Enable Bit 2 + * | | |0 = Tamper 0 detect Disabled. + * | | |1 = Tamper 0 detect Enabled. + * | | |Note: The reference is TLIRC 32K-clock. Tamper detector needs sync 2 ~ 3 TLIRC 32K-clock. + * |[12] |ATAMP1EN2 |Active Shied Tamper 1 Detect Enable Bit 2 + * | | |0 = Tamper 1 detect Disabled. + * | | |1 = Tamper 1 detect Enabled. + * | | |Note: The reference is TLIRC 32K-clock. Tamper detector needs sync 2 ~ 3 TLIRC 32K-clock. + * |[15] |ADYNPR0EN2|Active Shied Dynamic Pair 0 Enable Bit 2 + * | | |0 = Static detect (Not supported). + * | | |1 = Dynamic detect. + * |[16] |ATAMP2EN2 |Active Shied Tamper 2 Detect Enable Bit 2 + * | | |0 = Tamper 2 detect Disabled. + * | | |1 = Tamper 2 detect Enabled. + * | | |Note: The reference is TLIRC 32K-clock. Tamper detector needs sync 2 ~ 3 TLIRC 32K-clock. + * |[20] |ATAMP3EN2 |Active Shied Tamper 3 Detect Enable Bit 2 + * | | |0 = Tamper 3 detect Disabled. + * | | |1 = Tamper 3 detect Enabled. + * | | |Note: The reference is TLIRC 32K-clock. Tamper detector needs sync 2 ~ 3 TLIRC 32K-clock. + * |[23] |ADYNPR1EN2|Active Shied Dynamic Pair 1 Enable Bit 2 + * | | |0 = Static detect (Not supported). + * | | |1 = Dynamic detect. + * |[24] |ATAMP4EN2 |Active Shied Tamper4 Detect Enable Bit 2 + * | | |0 = Tamper 4 detect Disabled. + * | | |1 = Tamper 4 detect Enabled. + * | | |Note: The reference is TLIRC 32K-clock. Tamper detector need sync 2 ~ 3 TLIRC 32K-clock. + * |[28] |ATAMP5EN2 |Active Tamper 5 Detect Enable Bit 2 + * | | |0 = Tamper 5 detect Disabled. + * | | |1 = Tamper 5 detect Enabled. + * | | |Note: The reference is TLIRC 32K-clock. Tamper detector need sync 2 ~ 3 TLIRC 32K-clock. + * |[31] |ADYNPR2EN2|Active Shied Dynamic Pair 2 Enable Bit 2 + * | | |0 = Static detect (Not supported). + * | | |1 = Dynamic detect. + * @var TAMPER_T::CDBR + * Offset: 0x2C Tamper Clock Frequency Detector Boundary Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[7:0] |STOPBD |LXT Clock Frequency Detector Stop Boundary + * | | |The bits define the stop value of frequency monitor window. + * | | |When LXT frequency monitor counter lower than Clock Frequency Detector Stop Boundary, the LXT frequency detect stop interrupt flag will set to 1. + * | | |Note: The boundary is defined as the maximum value of LXT among 256 Tamper clock time. + * |[23:16] |FAILBD |LXT Clock Frequency Detector Fail Boundary + * | | |The bits define the fail value of frequency monitor window. + * | | |When LXT frequency monitor counter lower than Clock Frequency Detector Fail Boundary, the LXT frequency detect fail interrupt flag will set to 1. + * | | |Note: The boundary is defined as the minimum value of LXT among 256 Tamper clock time. + * @var TAMPER_T::VG + * Offset: 0x30 Tamper Voltage Glitch Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[3:0] |PCLKSEL0 |PL0 Positive Clock Trim Range + * | | |The setting value of the positive clock tolerance. + * | | |One step is about 2.5% tolerance. The maximum tolerance is 20%. + * | | |Note: PL0 means the power level is 1.26V + * | | |The power level is controlled in system manager + * |[7:4] |NCLKSEL0 |PL0 Negative Clock Trim Range + * | | |The setting value of the negative clock tolerance. + * | | |One step is about 2.5% tolerance. The maximum tolerance is 20%. + * |[11:8] |PDATSEL0 |PL0 Positive Data Trim Range + * | | |The setting value of the positive data tolerance. + * | | |One step is about 2.5% tolerance. The maximum tolerance is 20%. + * |[15:12] |NDATSEL0 |PL0 Negative Data Trim Range + * | | |The setting value of the negative data tolerance. + * | | |One step is about 2.5% tolerance. The maximum tolerance is 20%. + * |[19:16] |PCLKSEL1 |PL1 Positive Clock Trim Range + * | | |The setting value of the positive clock tolerance. + * | | |One step is about 2.5% tolerance. The maximum tolerance is 20%. + * | | |Note: PL1 means the power level is 1.2V + * |[23:20] |NCLKSEL1 |PL1 Negative Clock Trim Range + * | | |The setting value of the negative clock tolerance. + * | | |One step is about 2.5% tolerance. The maximum tolerance is 20%. + * |[27:24] |PDATSEL1 |PL1 Positive Data Trim Range + * | | |The setting value of the positive data tolerance. + * | | |One step is about 2.5% tolerance. The maximum tolerance is 20%. + * |[31:28] |NDATSEL1 |PL1 Negative Data Trim Range + * | | |The setting value of the negative data tolerance. + * | | |One step is about 2.5% tolerance. The maximum tolerance is 20%. + * @var TAMPER_T::VGEV + * Offset: 0x34 Tamper Voltage Glitch Event Tolerance Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[7:0] |VGECNTP |Positive Voltage Glitch Error Tolerance + * | | |The value indicates the tolerance count for positive voltage glitch event. + * |[15:8] |VGECNTN |Negative Voltage Glitch Error Tolerance + * | | |The value indicates the tolerance count for negative voltage glitch event. + * @var TAMPER_T::LDOTRIM + * Offset: 0x38 Tamper LDO Trim Value Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[3:0] |TLDOTRIM |Voltage Regulator Output Voltage Trim + * | | |The value indicates the trim value of the voltage regulator output voltage. + * |[9:8] |TLDOIQSEL |Voltage Regulator Qu Current Selection + * | | |Indicates the Qu current selection of voltage regulator. + * @var TAMPER_T::LBSTRIM + * Offset: 0x3C Tamper LDO BIAS Trim Value Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[2:0] |TLVDSEL |Under-shoot Detect Level Trim Bits + * | | |The value indicates the trim value of the under-shoot detection level + * |[4] |TOVDSEL |Over-shoot Detect Level Trim Bits + * | | |The value indicates the trim value of the over-shoot detection level + * |[9:8] |BSCMPLV |Under-shoot Detect Comparator Current Trim Bits + * | | |The value indicates the trim value of the under-shoot detection comparator current trim level + * |[11:10] |BSCMPOV |Over-shoot Detect Comparator Current Trim Bits + * | | |The value indicates the trim value of the over-shoot detection comparator current trim level + * |[13:12] |HYSCMPLV |Under-shoot Detect Comparator Hysteresis Trim Bits + * | | |The value indicates the trim value of the under-shoot detection comparator of hysteresis trim level + * |[15:14] |HYSCMPOV |Over-shoot Detect Comparator Hysteresis Trim Bits + * | | |The value indicates the trim value of the over-shoot detection comparator of hysteresis trim level + * @var TAMPER_T::VG2 + * Offset: 0x40 Tamper Voltage Glitch Control Register 2 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[3:0] |PCLKSEL2 |PL2 Positive Clock Trim Range + * | | |The setting value of the positive clock tolerance. + * | | |One step is about 2.5% tolerance. The maximum tolerance is 20%. + * | | |Note: PL2 means the power level is 1.1V + * | | |The power level is controlled in system manager. + * |[7:4] |NCLKSEL2 |PL2 Negative Clock Trim Range + * | | |The setting value of the negative clock tolerance. + * | | |One step is about 2.5% tolerance. The maximum tolerance is 20%. + * |[11:8] |PDATSEL2 |PL2 Positive Data Trim Range + * | | |The setting value of the positive data tolerance. + * | | |One step is about 2.5% tolerance. The maximum tolerance is 20%. + * |[15:12] |NDATSEL2 |PL2 Negative Data Trim Range + * | | |The setting value of the negative data tolerance. + * | | |One step is about 2.5% tolerance. The maximum tolerance is 20%. + * |[19:16] |PCLKSEL3 |PL3 Positive Clock Trim Range + * | | |The setting value of the positive clock tolerance. + * | | |One step is about 2.5% tolerance. The maximum tolerance is 20%. + * | | |Note: PL3 means the power level is 0.9V + * |[23:20] |NCLKSEL3 |PL3 Negative Clock Trim Range + * | | |The setting value of the negative clock tolerance. + * | | |One step is about 2.5% tolerance. The maximum tolerance is 20%. + * |[27:24] |PDATSEL3 |PL3 Positive Data Trim Range + * | | |The setting value of the positive data tolerance. + * | | |One step is about 2.5% tolerance. The maximum tolerance is 20%. + * |[31:28] |NDATSEL3 |PL3 Negative Data Trim Range + * | | |The setting value of the negative data tolerance. + * | | |One step is about 2.5% tolerance. The maximum tolerance is 20%. + */ + __IO uint32_t INIT; /*!< [0x0000] Tamper Function Initiation Register */ + __IO uint32_t FUNEN; /*!< [0x0004] Tamper Block Function Enable Register */ + __IO uint32_t TRIEN; /*!< [0x0008] Tamper Trigger Enable Register */ + __IO uint32_t INTEN; /*!< [0x000c] Tamper Event Interrupt Enable Register */ + __IO uint32_t INTSTS; /*!< [0x0010] Tamper Interrupt Status Register */ + __IO uint32_t LIRCTL; /*!< [0x0014] Tamper LIRC Control Register */ + __IO uint32_t TIOCTL; /*!< [0x0018] Tamper I/O Function Control Register */ + __IO uint32_t SEED; /*!< [0x001c] Tamper Seed Value Control Register */ + __IO uint32_t SEED2; /*!< [0x0020] Tamper 2nd Seed Value Control Register */ + __IO uint32_t ACTSTIOCTL1; /*!< [0x0024] Tamper Active Shield Tamper I/O Function Control Register 1 */ + __IO uint32_t ACTSTIOCTL2; /*!< [0x0028] Tamper Active Shield Tamper I/O Function Control Register 2 */ + __IO uint32_t CDBR; /*!< [0x002c] Tamper Clock Frequency Detector Boundary Register */ + __IO uint32_t VG; /*!< [0x0030] Tamper Voltage Glitch Control Register */ + __IO uint32_t VGEV; /*!< [0x0034] Tamper Voltage Glitch Event Tolerance Control Register */ + __IO uint32_t LDOTRIM; /*!< [0x0038] Tamper LDO Trim Value Control Register */ + __IO uint32_t LBSTRIM; /*!< [0x003c] Tamper LDO BIAS Trim Value Control Register */ + __IO uint32_t VG2; /*!< [0x0040] Tamper Voltage Glitch Control Register 2 */ + +} TAMPER_T; + +/** + @addtogroup TAMPER_CONST Tamper Bit Field Definition + Constant Definitions for Tamper Controller + @{ +*/ + +#define TAMPER_INIT_TCORERST_Pos (0) /*!< TAMPER_T::INIT: TCORERST Position */ +#define TAMPER_INIT_TCORERST_Msk (0x1ul << TAMPER_INIT_TCORERST_Pos) /*!< TAMPER_T::INIT: TCORERST Mask */ + +#define TAMPER_INIT_TLDORDY_Pos (31) /*!< TAMPER_T::INIT: TLDORDY Position */ +#define TAMPER_INIT_TLDORDY_Msk (0x1ul << TAMPER_INIT_TLDORDY_Pos) /*!< TAMPER_T::INIT: TLDORDY Mask */ + +#define TAMPER_FUNEN_LXTDETEN_Pos (0) /*!< TAMPER_T::FUNEN: LXTDETEN Position */ +#define TAMPER_FUNEN_LXTDETEN_Msk (0x1ul << TAMPER_FUNEN_LXTDETEN_Pos) /*!< TAMPER_T::FUNEN: LXTDETEN Mask */ + +#define TAMPER_FUNEN_TMPIOSEL_Pos (8) /*!< TAMPER_T::FUNEN: TMPIOSEL Position */ +#define TAMPER_FUNEN_TMPIOSEL_Msk (0x3ful << TAMPER_FUNEN_TMPIOSEL_Pos) /*!< TAMPER_T::FUNEN: TMPIOSEL Mask */ + +#define TAMPER_FUNEN_HIRC48MEN_Pos (16) /*!< TAMPER_T::FUNEN: HIRC48MEN Position */ +#define TAMPER_FUNEN_HIRC48MEN_Msk (0xfful << TAMPER_FUNEN_HIRC48MEN_Pos) /*!< TAMPER_T::FUNEN: HIRC48MEN Mask */ + +#define TAMPER_FUNEN_VGCHEN0_Pos (24) /*!< TAMPER_T::FUNEN: VGCHEN0 Position */ +#define TAMPER_FUNEN_VGCHEN0_Msk (0x1ul << TAMPER_FUNEN_VGCHEN0_Pos) /*!< TAMPER_T::FUNEN: VGCHEN0 Mask */ + +#define TAMPER_FUNEN_VGCHEN1_Pos (25) /*!< TAMPER_T::FUNEN: VGCHEN1 Position */ +#define TAMPER_FUNEN_VGCHEN1_Msk (0x1ul << TAMPER_FUNEN_VGCHEN1_Pos) /*!< TAMPER_T::FUNEN: VGCHEN1 Mask */ + +#define TAMPER_FUNEN_VGCHEN2_Pos (26) /*!< TAMPER_T::FUNEN: VGCHEN2 Position */ +#define TAMPER_FUNEN_VGCHEN2_Msk (0x1ul << TAMPER_FUNEN_VGCHEN2_Pos) /*!< TAMPER_T::FUNEN: VGCHEN2 Mask */ + +#define TAMPER_FUNEN_VGCHEN3_Pos (27) /*!< TAMPER_T::FUNEN: VGCHEN3 Position */ +#define TAMPER_FUNEN_VGCHEN3_Msk (0x1ul << TAMPER_FUNEN_VGCHEN3_Pos) /*!< TAMPER_T::FUNEN: VGCHEN3 Mask */ + +#define TAMPER_TRIEN_KSTRIGEN_Pos (1) /*!< TAMPER_T::TRIEN: KSTRIGEN Position */ +#define TAMPER_TRIEN_KSTRIGEN_Msk (0x1ul << TAMPER_TRIEN_KSTRIGEN_Pos) /*!< TAMPER_T::TRIEN: KSTRIGEN Mask */ + +#define TAMPER_TRIEN_WAKEUPEN_Pos (2) /*!< TAMPER_T::TRIEN: WAKEUPEN Position */ +#define TAMPER_TRIEN_WAKEUPEN_Msk (0x1ul << TAMPER_TRIEN_WAKEUPEN_Pos) /*!< TAMPER_T::TRIEN: WAKEUPEN Mask */ + +#define TAMPER_TRIEN_CRYPTOEN_Pos (3) /*!< TAMPER_T::TRIEN: CRYPTOEN Position */ +#define TAMPER_TRIEN_CRYPTOEN_Msk (0x1ul << TAMPER_TRIEN_CRYPTOEN_Pos) /*!< TAMPER_T::TRIEN: CRYPTOEN Mask */ + +#define TAMPER_TRIEN_CHIPRSTEN_Pos (4) /*!< TAMPER_T::TRIEN: CHIPRSTEN Position */ +#define TAMPER_TRIEN_CHIPRSTEN_Msk (0x1ul << TAMPER_TRIEN_CHIPRSTEN_Pos) /*!< TAMPER_T::TRIEN: CHIPRSTEN Mask */ + +#define TAMPER_TRIEN_RTCSPCLREN_Pos (5) /*!< TAMPER_T::TRIEN: RTCSPCLREN Position */ +#define TAMPER_TRIEN_RTCSPCLREN_Msk (0x1ul << TAMPER_TRIEN_RTCSPCLREN_Pos) /*!< TAMPER_T::TRIEN: RTCSPCLREN Mask */ + +#define TAMPER_INTEN_TAMP0IEN_Pos (0) /*!< TAMPER_T::INTEN: TAMP0IEN Position */ +#define TAMPER_INTEN_TAMP0IEN_Msk (0x1ul << TAMPER_INTEN_TAMP0IEN_Pos) /*!< TAMPER_T::INTEN: TAMP0IEN Mask */ + +#define TAMPER_INTEN_TAMP1IEN_Pos (1) /*!< TAMPER_T::INTEN: TAMP1IEN Position */ +#define TAMPER_INTEN_TAMP1IEN_Msk (0x1ul << TAMPER_INTEN_TAMP1IEN_Pos) /*!< TAMPER_T::INTEN: TAMP1IEN Mask */ + +#define TAMPER_INTEN_TAMP2IEN_Pos (2) /*!< TAMPER_T::INTEN: TAMP2IEN Position */ +#define TAMPER_INTEN_TAMP2IEN_Msk (0x1ul << TAMPER_INTEN_TAMP2IEN_Pos) /*!< TAMPER_T::INTEN: TAMP2IEN Mask */ + +#define TAMPER_INTEN_TAMP3IEN_Pos (3) /*!< TAMPER_T::INTEN: TAMP3IEN Position */ +#define TAMPER_INTEN_TAMP3IEN_Msk (0x1ul << TAMPER_INTEN_TAMP3IEN_Pos) /*!< TAMPER_T::INTEN: TAMP3IEN Mask */ + +#define TAMPER_INTEN_TAMP4IEN_Pos (4) /*!< TAMPER_T::INTEN: TAMP4IEN Position */ +#define TAMPER_INTEN_TAMP4IEN_Msk (0x1ul << TAMPER_INTEN_TAMP4IEN_Pos) /*!< TAMPER_T::INTEN: TAMP4IEN Mask */ + +#define TAMPER_INTEN_TAMP5IEN_Pos (5) /*!< TAMPER_T::INTEN: TAMP5IEN Position */ +#define TAMPER_INTEN_TAMP5IEN_Msk (0x1ul << TAMPER_INTEN_TAMP5IEN_Pos) /*!< TAMPER_T::INTEN: TAMP5IEN Mask */ + +#define TAMPER_INTEN_CLKFIEN_Pos (6) /*!< TAMPER_T::INTEN: CLKFIEN Position */ +#define TAMPER_INTEN_CLKFIEN_Msk (0x1ul << TAMPER_INTEN_CLKFIEN_Pos) /*!< TAMPER_T::INTEN: CLKFIEN Mask */ + +#define TAMPER_INTEN_CLKSTOPIEN_Pos (7) /*!< TAMPER_T::INTEN: CLKSTOPIEN Position */ +#define TAMPER_INTEN_CLKSTOPIEN_Msk (0x1ul << TAMPER_INTEN_CLKSTOPIEN_Pos) /*!< TAMPER_T::INTEN: CLKSTOPIEN Mask */ + +#define TAMPER_INTEN_OVPIEN_Pos (8) /*!< TAMPER_T::INTEN: OVPIEN Position */ +#define TAMPER_INTEN_OVPIEN_Msk (0x1ul << TAMPER_INTEN_OVPIEN_Pos) /*!< TAMPER_T::INTEN: OVPIEN Mask */ + +#define TAMPER_INTEN_VGPIEN_Pos (9) /*!< TAMPER_T::INTEN: VGPIEN Position */ +#define TAMPER_INTEN_VGPIEN_Msk (0x1ul << TAMPER_INTEN_VGPIEN_Pos) /*!< TAMPER_T::INTEN: VGPIEN Mask */ + +#define TAMPER_INTEN_VGNIEN_Pos (10) /*!< TAMPER_T::INTEN: VGNIEN Position */ +#define TAMPER_INTEN_VGNIEN_Msk (0x1ul << TAMPER_INTEN_VGNIEN_Pos) /*!< TAMPER_T::INTEN: VGNIEN Mask */ + +#define TAMPER_INTEN_ACTSIEN_Pos (11) /*!< TAMPER_T::INTEN: ACTSIEN Position */ +#define TAMPER_INTEN_ACTSIEN_Msk (0x1ul << TAMPER_INTEN_ACTSIEN_Pos) /*!< TAMPER_T::INTEN: ACTSIEN Mask */ + +#define TAMPER_INTEN_RTCLVRIEN_Pos (16) /*!< TAMPER_T::INTEN: RTCLVRIEN Position */ +#define TAMPER_INTEN_RTCLVRIEN_Msk (0x1ul << TAMPER_INTEN_RTCLVRIEN_Pos) /*!< TAMPER_T::INTEN: RTCLVRIEN Mask */ + +#define TAMPER_INTEN_RTCIOIEN_Pos (17) /*!< TAMPER_T::INTEN: RTCIOIEN Position */ +#define TAMPER_INTEN_RTCIOIEN_Msk (0x1ul << TAMPER_INTEN_RTCIOIEN_Pos) /*!< TAMPER_T::INTEN: RTCIOIEN Mask */ + +#define TAMPER_INTEN_RTCLKIEN_Pos (18) /*!< TAMPER_T::INTEN: RTCLKIEN Position */ +#define TAMPER_INTEN_RTCLKIEN_Msk (0x1ul << TAMPER_INTEN_RTCLKIEN_Pos) /*!< TAMPER_T::INTEN: RTCLKIEN Mask */ + +#define TAMPER_INTEN_BODIEN_Pos (22) /*!< TAMPER_T::INTEN: BODIEN Position */ +#define TAMPER_INTEN_BODIEN_Msk (0x1ul << TAMPER_INTEN_BODIEN_Pos) /*!< TAMPER_T::INTEN: BODIEN Mask */ + +#define TAMPER_INTSTS_TAMP0IF_Pos (0) /*!< TAMPER_T::INTSTS: TAMP0IF Position */ +#define TAMPER_INTSTS_TAMP0IF_Msk (0x1ul << TAMPER_INTSTS_TAMP0IF_Pos) /*!< TAMPER_T::INTSTS: TAMP0IF Mask */ + +#define TAMPER_INTSTS_TAMP1IF_Pos (1) /*!< TAMPER_T::INTSTS: TAMP1IF Position */ +#define TAMPER_INTSTS_TAMP1IF_Msk (0x1ul << TAMPER_INTSTS_TAMP1IF_Pos) /*!< TAMPER_T::INTSTS: TAMP1IF Mask */ + +#define TAMPER_INTSTS_TAMP2IF_Pos (2) /*!< TAMPER_T::INTSTS: TAMP2IF Position */ +#define TAMPER_INTSTS_TAMP2IF_Msk (0x1ul << TAMPER_INTSTS_TAMP2IF_Pos) /*!< TAMPER_T::INTSTS: TAMP2IF Mask */ + +#define TAMPER_INTSTS_TAMP3IF_Pos (3) /*!< TAMPER_T::INTSTS: TAMP3IF Position */ +#define TAMPER_INTSTS_TAMP3IF_Msk (0x1ul << TAMPER_INTSTS_TAMP3IF_Pos) /*!< TAMPER_T::INTSTS: TAMP3IF Mask */ + +#define TAMPER_INTSTS_TAMP4IF_Pos (4) /*!< TAMPER_T::INTSTS: TAMP4IF Position */ +#define TAMPER_INTSTS_TAMP4IF_Msk (0x1ul << TAMPER_INTSTS_TAMP4IF_Pos) /*!< TAMPER_T::INTSTS: TAMP4IF Mask */ + +#define TAMPER_INTSTS_TAMP5IF_Pos (5) /*!< TAMPER_T::INTSTS: TAMP5IF Position */ +#define TAMPER_INTSTS_TAMP5IF_Msk (0x1ul << TAMPER_INTSTS_TAMP5IF_Pos) /*!< TAMPER_T::INTSTS: TAMP5IF Mask */ + +#define TAMPER_INTSTS_CLKFAILIF_Pos (6) /*!< TAMPER_T::INTSTS: CLKFAILIF Position */ +#define TAMPER_INTSTS_CLKFAILIF_Msk (0x1ul << TAMPER_INTSTS_CLKFAILIF_Pos) /*!< TAMPER_T::INTSTS: CLKFAILIF Mask */ + +#define TAMPER_INTSTS_CLKSTOPIF_Pos (7) /*!< TAMPER_T::INTSTS: CLKSTOPIF Position */ +#define TAMPER_INTSTS_CLKSTOPIF_Msk (0x1ul << TAMPER_INTSTS_CLKSTOPIF_Pos) /*!< TAMPER_T::INTSTS: CLKSTOPIF Mask */ + +#define TAMPER_INTSTS_OVPOUTIF_Pos (8) /*!< TAMPER_T::INTSTS: OVPOUTIF Position */ +#define TAMPER_INTSTS_OVPOUTIF_Msk (0x1ul << TAMPER_INTSTS_OVPOUTIF_Pos) /*!< TAMPER_T::INTSTS: OVPOUTIF Mask */ + +#define TAMPER_INTSTS_VGPEVIF_Pos (9) /*!< TAMPER_T::INTSTS: VGPEVIF Position */ +#define TAMPER_INTSTS_VGPEVIF_Msk (0x1ul << TAMPER_INTSTS_VGPEVIF_Pos) /*!< TAMPER_T::INTSTS: VGPEVIF Mask */ + +#define TAMPER_INTSTS_VGNEVIF_Pos (10) /*!< TAMPER_T::INTSTS: VGNEVIF Position */ +#define TAMPER_INTSTS_VGNEVIF_Msk (0x1ul << TAMPER_INTSTS_VGNEVIF_Pos) /*!< TAMPER_T::INTSTS: VGNEVIF Mask */ + +#define TAMPER_INTSTS_ACTSEIF_Pos (11) /*!< TAMPER_T::INTSTS: ACTSEIF Position */ +#define TAMPER_INTSTS_ACTSEIF_Msk (0x1ul << TAMPER_INTSTS_ACTSEIF_Pos) /*!< TAMPER_T::INTSTS: ACTSEIF Mask */ + +#define TAMPER_INTSTS_ACTST5IF_Pos (13) /*!< TAMPER_T::INTSTS: ACTST5IF Position */ +#define TAMPER_INTSTS_ACTST5IF_Msk (0x1ul << TAMPER_INTSTS_ACTST5IF_Pos) /*!< TAMPER_T::INTSTS: ACTST5IF Mask */ + +#define TAMPER_INTSTS_ACTST25IF_Pos (15) /*!< TAMPER_T::INTSTS: ACTST25IF Position */ +#define TAMPER_INTSTS_ACTST25IF_Msk (0x1ul << TAMPER_INTSTS_ACTST25IF_Pos) /*!< TAMPER_T::INTSTS: ACTST25IF Mask */ + +#define TAMPER_INTSTS_RTCLVRIF_Pos (16) /*!< TAMPER_T::INTSTS: RTCLVRIF Position */ +#define TAMPER_INTSTS_RTCLVRIF_Msk (0x1ul << TAMPER_INTSTS_RTCLVRIF_Pos) /*!< TAMPER_T::INTSTS: RTCLVRIF Mask */ + +#define TAMPER_INTSTS_RIOTRIGIF_Pos (17) /*!< TAMPER_T::INTSTS: RIOTRIGIF Position */ +#define TAMPER_INTSTS_RIOTRIGIF_Msk (0x1ul << TAMPER_INTSTS_RIOTRIGIF_Pos) /*!< TAMPER_T::INTSTS: RIOTRIGIF Mask */ + +#define TAMPER_INTSTS_RCLKTRIGIF_Pos (18) /*!< TAMPER_T::INTSTS: RCLKTRIGIF Position */ +#define TAMPER_INTSTS_RCLKTRIGIF_Msk (0x1ul << TAMPER_INTSTS_RCLKTRIGIF_Pos) /*!< TAMPER_T::INTSTS: RCLKTRIGIF Mask */ + +#define TAMPER_INTSTS_BODIF_Pos (22) /*!< TAMPER_T::INTSTS: BODIF Position */ +#define TAMPER_INTSTS_BODIF_Msk (0x1ul << TAMPER_INTSTS_BODIF_Pos) /*!< TAMPER_T::INTSTS: BODIF Mask */ + +#define TAMPER_INTSTS_ACTST1IF_Pos (25) /*!< TAMPER_T::INTSTS: ACTST1IF Position */ +#define TAMPER_INTSTS_ACTST1IF_Msk (0x1ul << TAMPER_INTSTS_ACTST1IF_Pos) /*!< TAMPER_T::INTSTS: ACTST1IF Mask */ + +#define TAMPER_INTSTS_ACTST3IF_Pos (27) /*!< TAMPER_T::INTSTS: ACTST3IF Position */ +#define TAMPER_INTSTS_ACTST3IF_Msk (0x1ul << TAMPER_INTSTS_ACTST3IF_Pos) /*!< TAMPER_T::INTSTS: ACTST3IF Mask */ + +#define TAMPER_INTSTS_ACTST21IF_Pos (29) /*!< TAMPER_T::INTSTS: ACTST21IF Position */ +#define TAMPER_INTSTS_ACTST21IF_Msk (0x1ul << TAMPER_INTSTS_ACTST21IF_Pos) /*!< TAMPER_T::INTSTS: ACTST21IF Mask */ + +#define TAMPER_INTSTS_ACTST23IF_Pos (31) /*!< TAMPER_T::INTSTS: ACTST23IF Position */ +#define TAMPER_INTSTS_ACTST23IF_Msk (0x1ul << TAMPER_INTSTS_ACTST23IF_Pos) /*!< TAMPER_T::INTSTS: ACTST23IF Mask */ + +#define TAMPER_LIRCTL_TLRCTRIM_Pos (0) /*!< TAMPER_T::LIRCTL: TLRCTRIM Position */ +#define TAMPER_LIRCTL_TLRCTRIM_Msk (0x1fful << TAMPER_LIRCTL_TLRCTRIM_Pos) /*!< TAMPER_T::LIRCTL: TLRCTRIM Mask */ + +#define TAMPER_LIRCTL_TRIMMOS_Pos (9) /*!< TAMPER_T::LIRCTL: TRIMMOS Position */ +#define TAMPER_LIRCTL_TRIMMOS_Msk (0x3ul << TAMPER_LIRCTL_TRIMMOS_Pos) /*!< TAMPER_T::LIRCTL: TRIMMOS Mask */ + +#define TAMPER_TIOCTL_DYN1ISS_Pos (0) /*!< TAMPER_T::TIOCTL: DYN1ISS Position */ +#define TAMPER_TIOCTL_DYN1ISS_Msk (0x1ul << TAMPER_TIOCTL_DYN1ISS_Pos) /*!< TAMPER_T::TIOCTL: DYN1ISS Mask */ + +#define TAMPER_TIOCTL_DYN2ISS_Pos (1) /*!< TAMPER_T::TIOCTL: DYN2ISS Position */ +#define TAMPER_TIOCTL_DYN2ISS_Msk (0x1ul << TAMPER_TIOCTL_DYN2ISS_Pos) /*!< TAMPER_T::TIOCTL: DYN2ISS Mask */ + +#define TAMPER_TIOCTL_DYNSRC_Pos (3) /*!< TAMPER_T::TIOCTL: DYNSRC Position */ +#define TAMPER_TIOCTL_DYNSRC_Msk (0x1ul << TAMPER_TIOCTL_DYNSRC_Pos) /*!< TAMPER_T::TIOCTL: DYNSRC Mask */ + +#define TAMPER_TIOCTL_SEEDRLD_Pos (4) /*!< TAMPER_T::TIOCTL: SEEDRLD Position */ +#define TAMPER_TIOCTL_SEEDRLD_Msk (0x1ul << TAMPER_TIOCTL_SEEDRLD_Pos) /*!< TAMPER_T::TIOCTL: SEEDRLD Mask */ + +#define TAMPER_TIOCTL_DYNRATE_Pos (5) /*!< TAMPER_T::TIOCTL: DYNRATE Position */ +#define TAMPER_TIOCTL_DYNRATE_Msk (0x7ul << TAMPER_TIOCTL_DYNRATE_Pos) /*!< TAMPER_T::TIOCTL: DYNRATE Mask */ + +#define TAMPER_TIOCTL_TAMP0EN_Pos (8) /*!< TAMPER_T::TIOCTL: TAMP0EN Position */ +#define TAMPER_TIOCTL_TAMP0EN_Msk (0x1ul << TAMPER_TIOCTL_TAMP0EN_Pos) /*!< TAMPER_T::TIOCTL: TAMP0EN Mask */ + +#define TAMPER_TIOCTL_TAMP0LV_Pos (9) /*!< TAMPER_T::TIOCTL: TAMP0LV Position */ +#define TAMPER_TIOCTL_TAMP0LV_Msk (0x1ul << TAMPER_TIOCTL_TAMP0LV_Pos) /*!< TAMPER_T::TIOCTL: TAMP0LV Mask */ + +#define TAMPER_TIOCTL_TAMP0DBEN_Pos (10) /*!< TAMPER_T::TIOCTL: TAMP0DBEN Position */ +#define TAMPER_TIOCTL_TAMP0DBEN_Msk (0x1ul << TAMPER_TIOCTL_TAMP0DBEN_Pos) /*!< TAMPER_T::TIOCTL: TAMP0DBEN Mask */ + +#define TAMPER_TIOCTL_TAMP1EN_Pos (12) /*!< TAMPER_T::TIOCTL: TAMP1EN Position */ +#define TAMPER_TIOCTL_TAMP1EN_Msk (0x1ul << TAMPER_TIOCTL_TAMP1EN_Pos) /*!< TAMPER_T::TIOCTL: TAMP1EN Mask */ + +#define TAMPER_TIOCTL_TAMP1LV_Pos (13) /*!< TAMPER_T::TIOCTL: TAMP1LV Position */ +#define TAMPER_TIOCTL_TAMP1LV_Msk (0x1ul << TAMPER_TIOCTL_TAMP1LV_Pos) /*!< TAMPER_T::TIOCTL: TAMP1LV Mask */ + +#define TAMPER_TIOCTL_TAMP1DBEN_Pos (14) /*!< TAMPER_T::TIOCTL: TAMP1DBEN Position */ +#define TAMPER_TIOCTL_TAMP1DBEN_Msk (0x1ul << TAMPER_TIOCTL_TAMP1DBEN_Pos) /*!< TAMPER_T::TIOCTL: TAMP1DBEN Mask */ + +#define TAMPER_TIOCTL_DYNPR0EN_Pos (15) /*!< TAMPER_T::TIOCTL: DYNPR0EN Position */ +#define TAMPER_TIOCTL_DYNPR0EN_Msk (0x1ul << TAMPER_TIOCTL_DYNPR0EN_Pos) /*!< TAMPER_T::TIOCTL: DYNPR0EN Mask */ + +#define TAMPER_TIOCTL_TAMP2EN_Pos (16) /*!< TAMPER_T::TIOCTL: TAMP2EN Position */ +#define TAMPER_TIOCTL_TAMP2EN_Msk (0x1ul << TAMPER_TIOCTL_TAMP2EN_Pos) /*!< TAMPER_T::TIOCTL: TAMP2EN Mask */ + +#define TAMPER_TIOCTL_TAMP2LV_Pos (17) /*!< TAMPER_T::TIOCTL: TAMP2LV Position */ +#define TAMPER_TIOCTL_TAMP2LV_Msk (0x1ul << TAMPER_TIOCTL_TAMP2LV_Pos) /*!< TAMPER_T::TIOCTL: TAMP2LV Mask */ + +#define TAMPER_TIOCTL_TAMP2DBEN_Pos (18) /*!< TAMPER_T::TIOCTL: TAMP2DBEN Position */ +#define TAMPER_TIOCTL_TAMP2DBEN_Msk (0x1ul << TAMPER_TIOCTL_TAMP2DBEN_Pos) /*!< TAMPER_T::TIOCTL: TAMP2DBEN Mask */ + +#define TAMPER_TIOCTL_TAMP3EN_Pos (20) /*!< TAMPER_T::TIOCTL: TAMP3EN Position */ +#define TAMPER_TIOCTL_TAMP3EN_Msk (0x1ul << TAMPER_TIOCTL_TAMP3EN_Pos) /*!< TAMPER_T::TIOCTL: TAMP3EN Mask */ + +#define TAMPER_TIOCTL_TAMP3LV_Pos (21) /*!< TAMPER_T::TIOCTL: TAMP3LV Position */ +#define TAMPER_TIOCTL_TAMP3LV_Msk (0x1ul << TAMPER_TIOCTL_TAMP3LV_Pos) /*!< TAMPER_T::TIOCTL: TAMP3LV Mask */ + +#define TAMPER_TIOCTL_TAMP3DBEN_Pos (22) /*!< TAMPER_T::TIOCTL: TAMP3DBEN Position */ +#define TAMPER_TIOCTL_TAMP3DBEN_Msk (0x1ul << TAMPER_TIOCTL_TAMP3DBEN_Pos) /*!< TAMPER_T::TIOCTL: TAMP3DBEN Mask */ + +#define TAMPER_TIOCTL_DYNPR1EN_Pos (23) /*!< TAMPER_T::TIOCTL: DYNPR1EN Position */ +#define TAMPER_TIOCTL_DYNPR1EN_Msk (0x1ul << TAMPER_TIOCTL_DYNPR1EN_Pos) /*!< TAMPER_T::TIOCTL: DYNPR1EN Mask */ + +#define TAMPER_TIOCTL_TAMP4EN_Pos (24) /*!< TAMPER_T::TIOCTL: TAMP4EN Position */ +#define TAMPER_TIOCTL_TAMP4EN_Msk (0x1ul << TAMPER_TIOCTL_TAMP4EN_Pos) /*!< TAMPER_T::TIOCTL: TAMP4EN Mask */ + +#define TAMPER_TIOCTL_TAMP4LV_Pos (25) /*!< TAMPER_T::TIOCTL: TAMP4LV Position */ +#define TAMPER_TIOCTL_TAMP4LV_Msk (0x1ul << TAMPER_TIOCTL_TAMP4LV_Pos) /*!< TAMPER_T::TIOCTL: TAMP4LV Mask */ + +#define TAMPER_TIOCTL_TAMP4DBEN_Pos (26) /*!< TAMPER_T::TIOCTL: TAMP4DBEN Position */ +#define TAMPER_TIOCTL_TAMP4DBEN_Msk (0x1ul << TAMPER_TIOCTL_TAMP4DBEN_Pos) /*!< TAMPER_T::TIOCTL: TAMP4DBEN Mask */ + +#define TAMPER_TIOCTL_TAMP5EN_Pos (28) /*!< TAMPER_T::TIOCTL: TAMP5EN Position */ +#define TAMPER_TIOCTL_TAMP5EN_Msk (0x1ul << TAMPER_TIOCTL_TAMP5EN_Pos) /*!< TAMPER_T::TIOCTL: TAMP5EN Mask */ + +#define TAMPER_TIOCTL_TAMP5LV_Pos (29) /*!< TAMPER_T::TIOCTL: TAMP5LV Position */ +#define TAMPER_TIOCTL_TAMP5LV_Msk (0x1ul << TAMPER_TIOCTL_TAMP5LV_Pos) /*!< TAMPER_T::TIOCTL: TAMP5LV Mask */ + +#define TAMPER_TIOCTL_TAMP5DBEN_Pos (30) /*!< TAMPER_T::TIOCTL: TAMP5DBEN Position */ +#define TAMPER_TIOCTL_TAMP5DBEN_Msk (0x1ul << TAMPER_TIOCTL_TAMP5DBEN_Pos) /*!< TAMPER_T::TIOCTL: TAMP5DBEN Mask */ + +#define TAMPER_TIOCTL_DYNPR2EN_Pos (31) /*!< TAMPER_T::TIOCTL: DYNPR2EN Position */ +#define TAMPER_TIOCTL_DYNPR2EN_Msk (0x1ul << TAMPER_TIOCTL_DYNPR2EN_Pos) /*!< TAMPER_T::TIOCTL: DYNPR2EN Mask */ + +#define TAMPER_SEED_SEED_Pos (0) /*!< TAMPER_T::SEED: SEED Position */ +#define TAMPER_SEED_SEED_Msk (0xfffffffful << TAMPER_SEED_SEED_Pos) /*!< TAMPER_T::SEED: SEED Mask */ + +#define TAMPER_SEED2_SEED2_Pos (0) /*!< TAMPER_T::SEED2: SEED2 Position */ +#define TAMPER_SEED2_SEED2_Msk (0xfffffffful << TAMPER_SEED2_SEED2_Pos) /*!< TAMPER_T::SEED2: SEED2 Mask */ + +#define TAMPER_ACTSTIOCTL1_ADYN1ISS_Pos (0) /*!< TAMPER_T::ACTSTIOCTL1: ADYN1ISS Position*/ +#define TAMPER_ACTSTIOCTL1_ADYN1ISS_Msk (0x1ul << TAMPER_ACTSTIOCTL1_ADYN1ISS_Pos) /*!< TAMPER_T::ACTSTIOCTL1: ADYN1ISS Mask */ + +#define TAMPER_ACTSTIOCTL1_ADYNSRC_Pos (3) /*!< TAMPER_T::ACTSTIOCTL1: ADYNSRC Position*/ +#define TAMPER_ACTSTIOCTL1_ADYNSRC_Msk (0x1ul << TAMPER_ACTSTIOCTL1_ADYNSRC_Pos) /*!< TAMPER_T::ACTSTIOCTL1: ADYNSRC Mask */ + +#define TAMPER_ACTSTIOCTL1_ADYNRATE_Pos (5) /*!< TAMPER_T::ACTSTIOCTL1: ADYNRATE Position*/ +#define TAMPER_ACTSTIOCTL1_ADYNRATE_Msk (0x7ul << TAMPER_ACTSTIOCTL1_ADYNRATE_Pos) /*!< TAMPER_T::ACTSTIOCTL1: ADYNRATE Mask */ + +#define TAMPER_ACTSTIOCTL1_ATAMP0EN_Pos (8) /*!< TAMPER_T::ACTSTIOCTL1: ATAMP0EN Position*/ +#define TAMPER_ACTSTIOCTL1_ATAMP0EN_Msk (0x1ul << TAMPER_ACTSTIOCTL1_ATAMP0EN_Pos) /*!< TAMPER_T::ACTSTIOCTL1: ATAMP0EN Mask */ + +#define TAMPER_ACTSTIOCTL1_ATAMP1EN_Pos (12) /*!< TAMPER_T::ACTSTIOCTL1: ATAMP1EN Position*/ +#define TAMPER_ACTSTIOCTL1_ATAMP1EN_Msk (0x1ul << TAMPER_ACTSTIOCTL1_ATAMP1EN_Pos) /*!< TAMPER_T::ACTSTIOCTL1: ATAMP1EN Mask */ + +#define TAMPER_ACTSTIOCTL1_ADYNPR0EN_Pos (15) /*!< TAMPER_T::ACTSTIOCTL1: ADYNPR0EN Position*/ +#define TAMPER_ACTSTIOCTL1_ADYNPR0EN_Msk (0x1ul << TAMPER_ACTSTIOCTL1_ADYNPR0EN_Pos) /*!< TAMPER_T::ACTSTIOCTL1: ADYNPR0EN Mask */ + +#define TAMPER_ACTSTIOCTL1_ATAMP2EN_Pos (16) /*!< TAMPER_T::ACTSTIOCTL1: ATAMP2EN Position*/ +#define TAMPER_ACTSTIOCTL1_ATAMP2EN_Msk (0x1ul << TAMPER_ACTSTIOCTL1_ATAMP2EN_Pos) /*!< TAMPER_T::ACTSTIOCTL1: ATAMP2EN Mask */ + +#define TAMPER_ACTSTIOCTL1_ATAMP3EN_Pos (20) /*!< TAMPER_T::ACTSTIOCTL1: ATAMP3EN Position*/ +#define TAMPER_ACTSTIOCTL1_ATAMP3EN_Msk (0x1ul << TAMPER_ACTSTIOCTL1_ATAMP3EN_Pos) /*!< TAMPER_T::ACTSTIOCTL1: ATAMP3EN Mask */ + +#define TAMPER_ACTSTIOCTL1_ADYNPR1EN_Pos (23) /*!< TAMPER_T::ACTSTIOCTL1: ADYNPR1EN Position*/ +#define TAMPER_ACTSTIOCTL1_ADYNPR1EN_Msk (0x1ul << TAMPER_ACTSTIOCTL1_ADYNPR1EN_Pos) /*!< TAMPER_T::ACTSTIOCTL1: ADYNPR1EN Mask */ + +#define TAMPER_ACTSTIOCTL1_ATAMP4EN_Pos (24) /*!< TAMPER_T::ACTSTIOCTL1: ATAMP4EN Position*/ +#define TAMPER_ACTSTIOCTL1_ATAMP4EN_Msk (0x1ul << TAMPER_ACTSTIOCTL1_ATAMP4EN_Pos) /*!< TAMPER_T::ACTSTIOCTL1: ATAMP4EN Mask */ + +#define TAMPER_ACTSTIOCTL1_ATAMP5EN_Pos (28) /*!< TAMPER_T::ACTSTIOCTL1: ATAMP5EN Position*/ +#define TAMPER_ACTSTIOCTL1_ATAMP5EN_Msk (0x1ul << TAMPER_ACTSTIOCTL1_ATAMP5EN_Pos) /*!< TAMPER_T::ACTSTIOCTL1: ATAMP5EN Mask */ + +#define TAMPER_ACTSTIOCTL1_ADYNPR2EN_Pos (31) /*!< TAMPER_T::ACTSTIOCTL1: ADYNPR2EN Position*/ +#define TAMPER_ACTSTIOCTL1_ADYNPR2EN_Msk (0x1ul << TAMPER_ACTSTIOCTL1_ADYNPR2EN_Pos) /*!< TAMPER_T::ACTSTIOCTL1: ADYNPR2EN Mask */ + +#define TAMPER_ACTSTIOCTL2_ADYN1ISS2_Pos (0) /*!< TAMPER_T::ACTSTIOCTL2: ADYN1ISS2 Position*/ +#define TAMPER_ACTSTIOCTL2_ADYN1ISS2_Msk (0x1ul << TAMPER_ACTSTIOCTL2_ADYN1ISS2_Pos) /*!< TAMPER_T::ACTSTIOCTL2: ADYN1ISS2 Mask */ + +#define TAMPER_ACTSTIOCTL2_ADYNSRC2_Pos (3) /*!< TAMPER_T::ACTSTIOCTL2: ADYNSRC2 Position*/ +#define TAMPER_ACTSTIOCTL2_ADYNSRC2_Msk (0x1ul << TAMPER_ACTSTIOCTL2_ADYNSRC2_Pos) /*!< TAMPER_T::ACTSTIOCTL2: ADYNSRC2 Mask */ + +#define TAMPER_ACTSTIOCTL2_SEEDRLD2_Pos (4) /*!< TAMPER_T::ACTSTIOCTL2: SEEDRLD2 Position*/ +#define TAMPER_ACTSTIOCTL2_SEEDRLD2_Msk (0x1ul << TAMPER_ACTSTIOCTL2_SEEDRLD2_Pos) /*!< TAMPER_T::ACTSTIOCTL2: SEEDRLD2 Mask */ + +#define TAMPER_ACTSTIOCTL2_ADYNRATE2_Pos (5) /*!< TAMPER_T::ACTSTIOCTL2: ADYNRATE2 Position*/ +#define TAMPER_ACTSTIOCTL2_ADYNRATE2_Msk (0x7ul << TAMPER_ACTSTIOCTL2_ADYNRATE2_Pos) /*!< TAMPER_T::ACTSTIOCTL2: ADYNRATE2 Mask */ + +#define TAMPER_ACTSTIOCTL2_ATAMP0EN2_Pos (8) /*!< TAMPER_T::ACTSTIOCTL2: ATAMP0EN2 Position*/ +#define TAMPER_ACTSTIOCTL2_ATAMP0EN2_Msk (0x1ul << TAMPER_ACTSTIOCTL2_ATAMP0EN2_Pos) /*!< TAMPER_T::ACTSTIOCTL2: ATAMP0EN2 Mask */ + +#define TAMPER_ACTSTIOCTL2_ATAMP1EN2_Pos (12) /*!< TAMPER_T::ACTSTIOCTL2: ATAMP1EN2 Position*/ +#define TAMPER_ACTSTIOCTL2_ATAMP1EN2_Msk (0x1ul << TAMPER_ACTSTIOCTL2_ATAMP1EN2_Pos) /*!< TAMPER_T::ACTSTIOCTL2: ATAMP1EN2 Mask */ + +#define TAMPER_ACTSTIOCTL2_ADYNPR0EN2_Pos (15) /*!< TAMPER_T::ACTSTIOCTL2: ADYNPR0EN2 Position*/ +#define TAMPER_ACTSTIOCTL2_ADYNPR0EN2_Msk (0x1ul << TAMPER_ACTSTIOCTL2_ADYNPR0EN2_Pos) /*!< TAMPER_T::ACTSTIOCTL2: ADYNPR0EN2 Mask */ + +#define TAMPER_ACTSTIOCTL2_ATAMP2EN2_Pos (16) /*!< TAMPER_T::ACTSTIOCTL2: ATAMP2EN2 Position*/ +#define TAMPER_ACTSTIOCTL2_ATAMP2EN2_Msk (0x1ul << TAMPER_ACTSTIOCTL2_ATAMP2EN2_Pos) /*!< TAMPER_T::ACTSTIOCTL2: ATAMP2EN2 Mask */ + +#define TAMPER_ACTSTIOCTL2_ATAMP3EN2_Pos (20) /*!< TAMPER_T::ACTSTIOCTL2: ATAMP3EN2 Position*/ +#define TAMPER_ACTSTIOCTL2_ATAMP3EN2_Msk (0x1ul << TAMPER_ACTSTIOCTL2_ATAMP3EN2_Pos) /*!< TAMPER_T::ACTSTIOCTL2: ATAMP3EN2 Mask */ + +#define TAMPER_ACTSTIOCTL2_ADYNPR1EN2_Pos (23) /*!< TAMPER_T::ACTSTIOCTL2: ADYNPR1EN2 Position*/ +#define TAMPER_ACTSTIOCTL2_ADYNPR1EN2_Msk (0x1ul << TAMPER_ACTSTIOCTL2_ADYNPR1EN2_Pos) /*!< TAMPER_T::ACTSTIOCTL2: ADYNPR1EN2 Mask */ + +#define TAMPER_ACTSTIOCTL2_ATAMP4EN2_Pos (24) /*!< TAMPER_T::ACTSTIOCTL2: ATAMP4EN2 Position*/ +#define TAMPER_ACTSTIOCTL2_ATAMP4EN2_Msk (0x1ul << TAMPER_ACTSTIOCTL2_ATAMP4EN2_Pos) /*!< TAMPER_T::ACTSTIOCTL2: ATAMP4EN2 Mask */ + +#define TAMPER_ACTSTIOCTL2_ATAMP5EN2_Pos (28) /*!< TAMPER_T::ACTSTIOCTL2: ATAMP5EN2 Position*/ +#define TAMPER_ACTSTIOCTL2_ATAMP5EN2_Msk (0x1ul << TAMPER_ACTSTIOCTL2_ATAMP5EN2_Pos) /*!< TAMPER_T::ACTSTIOCTL2: ATAMP5EN2 Mask */ + +#define TAMPER_ACTSTIOCTL2_ADYNPR2EN2_Pos (31) /*!< TAMPER_T::ACTSTIOCTL2: ADYNPR2EN2 Position*/ +#define TAMPER_ACTSTIOCTL2_ADYNPR2EN2_Msk (0x1ul << TAMPER_ACTSTIOCTL2_ADYNPR2EN2_Pos) /*!< TAMPER_T::ACTSTIOCTL2: ADYNPR2EN2 Mask */ + +#define TAMPER_CDBR_STOPBD_Pos (0) /*!< TAMPER_T::CDBR: STOPBD Position */ +#define TAMPER_CDBR_STOPBD_Msk (0xfful << TAMPER_CDBR_STOPBD_Pos) /*!< TAMPER_T::CDBR: STOPBD Mask */ + +#define TAMPER_CDBR_FAILBD_Pos (16) /*!< TAMPER_T::CDBR: FAILBD Position */ +#define TAMPER_CDBR_FAILBD_Msk (0xfful << TAMPER_CDBR_FAILBD_Pos) /*!< TAMPER_T::CDBR: FAILBD Mask */ + +#define TAMPER_VG_PCLKSEL0_Pos (0) /*!< TAMPER_T::VG: PCLKSEL0 Position */ +#define TAMPER_VG_PCLKSEL0_Msk (0xful << TAMPER_VG_PCLKSEL0_Pos) /*!< TAMPER_T::VG: PCLKSEL0 Mask */ + +#define TAMPER_VG_NCLKSEL0_Pos (4) /*!< TAMPER_T::VG: NCLKSEL0 Position */ +#define TAMPER_VG_NCLKSEL0_Msk (0xful << TAMPER_VG_NCLKSEL0_Pos) /*!< TAMPER_T::VG: NCLKSEL0 Mask */ + +#define TAMPER_VG_PDATSEL0_Pos (8) /*!< TAMPER_T::VG: PDATSEL0 Position */ +#define TAMPER_VG_PDATSEL0_Msk (0xful << TAMPER_VG_PDATSEL0_Pos) /*!< TAMPER_T::VG: PDATSEL0 Mask */ + +#define TAMPER_VG_NDATSEL0_Pos (12) /*!< TAMPER_T::VG: NDATSEL0 Position */ +#define TAMPER_VG_NDATSEL0_Msk (0xful << TAMPER_VG_NDATSEL0_Pos) /*!< TAMPER_T::VG: NDATSEL0 Mask */ + +#define TAMPER_VG_PCLKSEL1_Pos (16) /*!< TAMPER_T::VG: PCLKSEL1 Position */ +#define TAMPER_VG_PCLKSEL1_Msk (0xful << TAMPER_VG_PCLKSEL1_Pos) /*!< TAMPER_T::VG: PCLKSEL1 Mask */ + +#define TAMPER_VG_NCLKSEL1_Pos (20) /*!< TAMPER_T::VG: NCLKSEL1 Position */ +#define TAMPER_VG_NCLKSEL1_Msk (0xful << TAMPER_VG_NCLKSEL1_Pos) /*!< TAMPER_T::VG: NCLKSEL1 Mask */ + +#define TAMPER_VG_PDATSEL1_Pos (24) /*!< TAMPER_T::VG: PDATSEL1 Position */ +#define TAMPER_VG_PDATSEL1_Msk (0xful << TAMPER_VG_PDATSEL1_Pos) /*!< TAMPER_T::VG: PDATSEL1 Mask */ + +#define TAMPER_VG_NDATSEL1_Pos (28) /*!< TAMPER_T::VG: NDATSEL1 Position */ +#define TAMPER_VG_NDATSEL1_Msk (0xful << TAMPER_VG_NDATSEL1_Pos) /*!< TAMPER_T::VG: NDATSEL1 Mask */ + +#define TAMPER_VGEV_VGECNTP_Pos (0) /*!< TAMPER_T::VGEV: VGECNTP Position */ +#define TAMPER_VGEV_VGECNTP_Msk (0xfful << TAMPER_VGEV_VGECNTP_Pos) /*!< TAMPER_T::VGEV: VGECNTP Mask */ + +#define TAMPER_VGEV_VGECNTN_Pos (8) /*!< TAMPER_T::VGEV: VGECNTN Position */ +#define TAMPER_VGEV_VGECNTN_Msk (0xfful << TAMPER_VGEV_VGECNTN_Pos) /*!< TAMPER_T::VGEV: VGECNTN Mask */ + +#define TAMPER_LDOTRIM_TLDOTRIM_Pos (0) /*!< TAMPER_T::LDOTRIM: TLDOTRIM Position */ +#define TAMPER_LDOTRIM_TLDOTRIM_Msk (0xful << TAMPER_LDOTRIM_TLDOTRIM_Pos) /*!< TAMPER_T::LDOTRIM: TLDOTRIM Mask */ + +#define TAMPER_LDOTRIM_TLDOIQSEL_Pos (8) /*!< TAMPER_T::LDOTRIM: TLDOIQSEL Position */ +#define TAMPER_LDOTRIM_TLDOIQSEL_Msk (0x3ul << TAMPER_LDOTRIM_TLDOIQSEL_Pos) /*!< TAMPER_T::LDOTRIM: TLDOIQSEL Mask */ + +#define TAMPER_LBSTRIM_TLVDSEL_Pos (0) /*!< TAMPER_T::LBSTRIM: TLVDSEL Position */ +#define TAMPER_LBSTRIM_TLVDSEL_Msk (0x7ul << TAMPER_LBSTRIM_TLVDSEL_Pos) /*!< TAMPER_T::LBSTRIM: TLVDSEL Mask */ + +#define TAMPER_LBSTRIM_TOVDSEL_Pos (4) /*!< TAMPER_T::LBSTRIM: TOVDSEL Position */ +#define TAMPER_LBSTRIM_TOVDSEL_Msk (0x1ul << TAMPER_LBSTRIM_TOVDSEL_Pos) /*!< TAMPER_T::LBSTRIM: TOVDSEL Mask */ + +#define TAMPER_LBSTRIM_BSCMPLV_Pos (8) /*!< TAMPER_T::LBSTRIM: BSCMPLV Position */ +#define TAMPER_LBSTRIM_BSCMPLV_Msk (0x3ul << TAMPER_LBSTRIM_BSCMPLV_Pos) /*!< TAMPER_T::LBSTRIM: BSCMPLV Mask */ + +#define TAMPER_LBSTRIM_BSCMPOV_Pos (10) /*!< TAMPER_T::LBSTRIM: BSCMPOV Position */ +#define TAMPER_LBSTRIM_BSCMPOV_Msk (0x3ul << TAMPER_LBSTRIM_BSCMPOV_Pos) /*!< TAMPER_T::LBSTRIM: BSCMPOV Mask */ + +#define TAMPER_LBSTRIM_HYSCMPLV_Pos (12) /*!< TAMPER_T::LBSTRIM: HYSCMPLV Position */ +#define TAMPER_LBSTRIM_HYSCMPLV_Msk (0x3ul << TAMPER_LBSTRIM_HYSCMPLV_Pos) /*!< TAMPER_T::LBSTRIM: HYSCMPLV Mask */ + +#define TAMPER_LBSTRIM_HYSCMPOV_Pos (14) /*!< TAMPER_T::LBSTRIM: HYSCMPOV Position */ +#define TAMPER_LBSTRIM_HYSCMPOV_Msk (0x3ul << TAMPER_LBSTRIM_HYSCMPOV_Pos) /*!< TAMPER_T::LBSTRIM: HYSCMPOV Mask */ + +#define TAMPER_VG2_PCLKSEL2_Pos (0) /*!< TAMPER_T::VG2: PCLKSEL2 Position */ +#define TAMPER_VG2_PCLKSEL2_Msk (0xful << TAMPER_VG2_PCLKSEL2_Pos) /*!< TAMPER_T::VG2: PCLKSEL2 Mask */ + +#define TAMPER_VG2_NCLKSEL2_Pos (4) /*!< TAMPER_T::VG2: NCLKSEL2 Position */ +#define TAMPER_VG2_NCLKSEL2_Msk (0xful << TAMPER_VG2_NCLKSEL2_Pos) /*!< TAMPER_T::VG2: NCLKSEL2 Mask */ + +#define TAMPER_VG2_PDATSEL2_Pos (8) /*!< TAMPER_T::VG2: PDATSEL2 Position */ +#define TAMPER_VG2_PDATSEL2_Msk (0xful << TAMPER_VG2_PDATSEL2_Pos) /*!< TAMPER_T::VG2: PDATSEL2 Mask */ + +#define TAMPER_VG2_NDATSEL2_Pos (12) /*!< TAMPER_T::VG2: NDATSEL2 Position */ +#define TAMPER_VG2_NDATSEL2_Msk (0xful << TAMPER_VG2_NDATSEL2_Pos) /*!< TAMPER_T::VG2: NDATSEL2 Mask */ + +#define TAMPER_VG2_PCLKSEL3_Pos (16) /*!< TAMPER_T::VG2: PCLKSEL3 Position */ +#define TAMPER_VG2_PCLKSEL3_Msk (0xful << TAMPER_VG2_PCLKSEL3_Pos) /*!< TAMPER_T::VG2: PCLKSEL3 Mask */ + +#define TAMPER_VG2_NCLKSEL3_Pos (20) /*!< TAMPER_T::VG2: NCLKSEL3 Position */ +#define TAMPER_VG2_NCLKSEL3_Msk (0xful << TAMPER_VG2_NCLKSEL3_Pos) /*!< TAMPER_T::VG2: NCLKSEL3 Mask */ + +#define TAMPER_VG2_PDATSEL3_Pos (24) /*!< TAMPER_T::VG2: PDATSEL3 Position */ +#define TAMPER_VG2_PDATSEL3_Msk (0xful << TAMPER_VG2_PDATSEL3_Pos) /*!< TAMPER_T::VG2: PDATSEL3 Mask */ + +#define TAMPER_VG2_NDATSEL3_Pos (28) /*!< TAMPER_T::VG2: NDATSEL3 Position */ +#define TAMPER_VG2_NDATSEL3_Msk (0xful << TAMPER_VG2_NDATSEL3_Pos) /*!< TAMPER_T::VG2: NDATSEL3 Mask */ + +/**@}*/ /* TAMPER_CONST */ +/**@}*/ /* end of TAMPER register group */ +/**@}*/ /* end of REGISTER group */ + +#endif /* __TAMPER_REG_H__ */ diff --git a/Ubiquitous/XiZi/board/nuvoton-m2354/third_party_driver/include/Regs/timer_reg.h b/Ubiquitous/XiZi/board/nuvoton-m2354/third_party_driver/include/Regs/timer_reg.h new file mode 100644 index 0000000..39cf4fa --- /dev/null +++ b/Ubiquitous/XiZi/board/nuvoton-m2354/third_party_driver/include/Regs/timer_reg.h @@ -0,0 +1,1168 @@ +/**************************************************************************//** + * @file timer_reg.h + * @version V1.00 + * @brief TIMER register definition header file + * + * @copyright SPDX-License-Identifier: Apache-2.0 + * @copyright Copyright (C) 2020 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ +#ifndef __TIMER_REG_H__ +#define __TIMER_REG_H__ + +/** @addtogroup REGISTER Control Register + + @{ + +*/ + +/*---------------------- Timer Controller -------------------------*/ +/** + @addtogroup TIMER Timer Controller(TIMER) + Memory Mapped Structure for TIMER Controller + @{ +*/ + +typedef struct +{ + + + /** + * @var TIMER_T::CTL + * Offset: 0x00 Timer Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[7:0] |PSC |Prescale Counter + * | | |Timer input clock or event source is divided by (PSC+1) before it is fed to the timer up counter + * | | |If this field is 0 (PSC = 0), then there is no scaling. + * | | |Note: Update prescale counter value will reset internal 8-bit prescale counter and 24-bit up counter value. + * |[15] |FUNCSEL |Function Selection + * | | |This bit sets the operation mode of Timer4 and Timer5 to PWM function. + * | | |0 = Timer controller is used as timer function. + * | | |1 = Timer controller is used as PWM function. + * | | |Note: The Timer0 ~ Timer3 function selection is controlled in TIMERx_ALTCTL[0], x= 0~3. + * |[19] |INTRGEN |Inter-timer Trigger Mode Enable Control + * | | |Setting this bit will enable the inter-timer trigger capture function. + * | | |The Timer0/2/4 will be in event counter mode and counting with external clock source or event + * | | |Also, Timer1/3/5 will be in trigger-counting mode of capture function. + * | | |0 = Inter-Timer Trigger Capture mode Disabled. + * | | |1 = Inter-Timer Trigger Capture mode Enabled. + * | | |Note: For Timer1/3/5, this bit is ignored and the read back value is always 0. + * |[20] |PERIOSEL |Periodic Mode Behavior Selection Enable Bit + * | | |0 = The behavior selection in periodic mode is Disabled. + * | | |When user updates CMPDAT while timer is running in periodic mode, CNT will be reset to default value. + * | | |1 = The behavior selection in periodic mode is Enabled. + * | | |When user update CMPDAT while timer is running in periodic mode, the limitations as bellows list, + * | | |If updated CMPDAT value > CNT, CMPDAT will be updated and CNT keep running continually. + * | | |If updated CMPDAT value = CNT, timer time-out interrupt will be asserted immediately. + * | | |If updated CMPDAT value < CNT, CNT will be reset to default value. + * |[21] |TGLPINSEL |Toggle-output Pin Select + * | | |0 = Toggle mode output to TMx (Timer Event Counter Pin). + * | | |1 = Toggle mode output to TMx_EXT (Timer External Capture Pin). + * |[22] |CAPSRC |Capture Pin Source Selection + * | | |0 = Capture Function source is from TMx_EXT (x= 0~5) pin. + * | | |1 = Capture Function source is from internal ACMP output signal, internal clock source (HIRC, LIRC, MIRC) or external clock (HXT, LXT). + * | | |Note1: When CAPSRC = 1, user can set INTERCAPSEL (TIMERx_EXTCTL[10:8]) to decide which internal ACMP output signal or which clock is as timer capture source. + * | | |Note2: MIRC clock source is only available in Timer4 ~ Timer5. + * |[23] |WKEN |Wake-up Function Enable Bit + * | | |If this bit is set to 1, while timer interrupt flag TIF (TIMERx_INTSTS[0]) is 1 and INTEN (TIMERx_CTL[29]) is enabled, the timer interrupt signal will generate a wake-up trigger event to CPU. + * | | |0 = Wake-up function Disabled if timer interrupt signal generated. + * | | |1 = Wake-up function Enabled if timer interrupt signal generated. + * |[24] |EXTCNTEN |Event Counter Mode Enable Bit + * | | |This bit is for external counting pin function enabled. + * | | |0 = Event counter mode Disabled. + * | | |1 = Event counter mode Enabled. + * | | |Note: When timer is used as an event counter, this bit should be set to 1 and select PCLK as timer clock source. + * |[25] |ACTSTS |Timer Active Status Bit (Read Only) + * | | |This bit indicates the 24-bit up counter status. + * | | |0 = 24-bit up counter is not active. + * | | |1 = 24-bit up counter is active. + * | | |Note: This bit may active when CNT 0 transition to CNT 1. + * |[28:27] |OPMODE |Timer Counting Mode Select + * | | |00 = The Timer controller is operated in One-shot mode. + * | | |01 = The Timer controller is operated in Periodic mode. + * | | |10 = The Timer controller is operated in Toggle-output mode. + * | | |11 = The Timer controller is operated in Continuous Counting mode. + * |[29] |INTEN |Timer Interrupt Enable Bit + * | | |0 = Timer time-out interrupt Disabled. + * | | |1 = Timer time-out interrupt Enabled. + * | | |Note: If this bit is enabled, when the timer time-out interrupt flag TIF is set to 1, the timer interrupt signal is generated and inform to CPU. + * |[30] |CNTEN |Timer Counting Enable Bit + * | | |0 = Stops/Suspends counting. + * | | |1 = Starts counting. + * | | |Note1: In stop status, and then set CNTEN to 1 will enable the 24-bit up counter to keep counting from the last stop counting value. + * | | |Note2: This bit is auto-cleared by hardware in one-shot mode (TIMER_CTL[28:27] = 00) when the timer time-out interrupt flag TIF (TIMERx_INTSTS[0]) is generated. + * | | |Note3: Set enable/disable this bit needs 2 * TMR_CLK period to become active, user can read ACTSTS (TIMERx_CTL[25]) to check enable/disable command is completed or not. + * |[31] |ICEDEBUG |ICE Debug Mode Acknowledge Disable Control (Write Protect) + * | | |0 = ICE debug mode acknowledgment effects TIMER counting. + * | | |TIMER counter will be held while CPU is held by ICE. + * | | |1 = ICE debug mode acknowledgment Disabled. + * | | |TIMER counter will keep going no matter CPU is held by ICE or not. + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * @var TIMER_T::CMP + * Offset: 0x04 Timer Comparator Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[23:0] |CMPDAT |Timer Comparator Value + * | | |CMPDAT is a 24-bit compared value register. + * | | |When the internal 24-bit up counter value is equal to CMPDAT value, the TIF (TIMERx_INTSTS[0] Timer Interrupt Flag) will set to 1. + * | | |Time-out period = (Period of timer clock input) * (8-bit PSC + 1) * (24-bit CMPDAT). + * | | |Note1: Never write 0x0 or 0x1 in CMPDAT field, or the core will run into unknown state. + * | | |Note2: When timer is operating at continuous counting mode, the 24-bit up counter will keep counting continuously even if user writes a new value into CMPDAT field. + * | | |But if timer is operating at other modes, the 24-bit up counter will restart counting from 0 and using newest CMPDAT value to be the timer compared value while user writes a new value into CMPDAT field. + * @var TIMER_T::INTSTS + * Offset: 0x08 Timer Interrupt Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |TIF |Timer Interrupt Flag + * | | |This bit indicates the interrupt flag status of Timer while 24-bit timer up counter CNT (TIMERx_CNT[23:0]) value reaches to CMPDAT (TIMERx_CMP[23:0]) value. + * | | |0 = No effect. + * | | |1 = CNT value matches the CMPDAT value. + * | | |Note: This bit is cleared by writing 1 to it. + * |[1] |TWKF |Timer Wake-up Flag + * | | |This bit indicates the interrupt wake-up flag status of timer. + * | | |0 = Timer does not cause CPU wake-up. + * | | |1 = CPU wake-up from Idle or Power-down mode if timer time-out interrupt signal generated. + * | | |Note: This bit is cleared by writing 1 to it. + * @var TIMER_T::CNT + * Offset: 0x0C Timer Data Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[23:0] |CNT |Timer Data Register + * | | |Read operation. + * | | |Read this register to get CNT value. For example: + * | | |If EXTCNTEN (TIMERx_CTL[24]) is 0, user can read CNT value for getting current 24-bit counter value. + * | | |If EXTCNTEN (TIMERx_CTL[24]) is 1, user can read CNT value for getting current 24-bit event input counter value. + * | | |Write operation. + * | | |Writing any value to this register will reset current CNT value to 0 and reload internal 8-bit prescale counter. + * |[31] |RSTACT |Timer Data Register Reset Active (Read Only) + * | | |This bit indicates if the counter reset operation active. + * | | |When user writes this CNT register, timer starts to reset its internal 24-bit timer up-counter to 0 and reload 8-bit pre-scale counter. + * | | |At the same time, timer set this flag to 1 to indicate the counter reset operation is in progress. + * | | |Once the counter reset operation done, timer clear this bit to 0 automatically. + * | | |0 = Reset operation is done. + * | | |1 = Reset operation triggered by writing TIMERx_CNT is in progress. + * | | |Note: This bit is read only. + * @var TIMER_T::CAP + * Offset: 0x10 Timer Capture Data Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[23:0] |CAPDAT |Timer Capture Data Register + * | | |When CAPEN (TIMERx_EXTCTL[3]) bit is set, the transition on the capture source matches the CAPEDGE (TIMERx_EXTCTL[14:12]) setting, + * | | |CAPIF (TIMERx_EINTSTS[0]) will set to 1 and the current timer counter value CNT (TIMERx_CNT[23:0]) will be auto-loaded into this CAPDAT field. + * @var TIMER_T::EXTCTL + * Offset: 0x14 Timer External Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |CNTPHASE |Timer External Count Phase + * | | |This bit indicates the detection phase of external counting pin TMx (x= 0~5). + * | | |0 = A falling edge of external counting pin will be counted. + * | | |1 = A rising edge of external counting pin will be counted. + * |[3] |CAPEN |Timer Capture Function Enable Bit + * | | |This bit enables the capture input function. + * | | |0 = Timer capture function Disabled. + * | | |1 = Timer capture function Enabled. + * |[4] |CAPFUNCS |Capture Function Selection + * | | |0 = Capture Mode Enabled. + * | | |1 = Reset Mode Enabled. + * | | |Note1: When CAPFUNCS is 0 and CAPIF becomes 1, the current 24-bit timer counter value (CNT value) will be saved to CAPDAT field. + * | | |Note2: When CAPFUNCS is 1 and CAPIF becomes 1, the current 24-bit timer counter value (CNT value) will be saved to CAPDAT field then CNT value will be reset immediately. + * |[5] |CAPIEN |Timer Capture Interrupt Enable Bit + * | | |0 = TMx_EXT (x= 0~5), ACMP, internal clock, or external clock detection Interrupt Disabled. + * | | |1 = TMx_EXT (x= 0~5), ACMP, internal clock, or external clock detection Interrupt Enabled. + * | | |Note: CAPIEN is used to enable timer capture interrupt. + * | | |If CAPIEN enabled, timer will rise an interrupt when CAPIF (TIMERx_EINTSTS[0]) is 1. + * | | |For example, while CAPIEN = 1, CAPEN = 1, and CAPEDGE = 00, a 1 to 0 transition on the TMx_EXT pin, ACMP, internal clock, or external clock + * | | |will cause the CAPIF to be set then the interrupt signal is generated and sent to NVIC to inform CPU. + * |[6] |CAPDBEN |Timer Capture De-bounce Enable Bit + * | | |0 = TMx_EXT (x= 0~5) pin de-bounce or ACMP output de-bounce Disabled. + * | | |1 = TMx_EXT (x= 0~5) pin de-bounce or ACMP output de-bounce Enabled. + * | | |Note: If this bit is enabled, the edge detection of TMx_EXT pin or ACMP output is detected with de-bounce circuit. + * |[7] |CNTDBEN |Timer External Counter Pin De-bounce Enable Bit + * | | |0 = TMx (x= 0~5) pin de-bounce Disabled. + * | | |1 = TMx (x= 0~5) pin de-bounce Enabled. + * | | |Note: If this bit is enabled, the edge detection of TMx pin is detected with de-bounce circuit. + * |[10:8] |INTERCAPSEL|Internal Capture Source Select + * | | |000 = Capture Function source is from internal ACMP0 output signal. + * | | |001 = Capture Function source is from internal ACMP1 output signal. + * | | |010 = Capture Function source is from HXT. + * | | |011 = Capture Function source is from LXT. + * | | |100 = Capture Function source is from HIRC. + * | | |101 = Capture Function source is from LIRC. + * | | |101 = Capture Function source is from LIRC. + * | | |110 = Capture Function source is from MIRC, only available in Timer4 and Timer5. + * | | |111 = Reserved. + * | | |Note: These bits only available when CAPSRC (TIMERx_CTL[22]) is 1. + * |[14:12] |CAPEDGE |Timer Capture Edge Detect + * | | |When first capture event is generated, the CNT (TIMERx_CNT[23:0]) will be reset to 0 and first CAPDAT (TIMERx_CAP[23:0]) should be to 0. + * | | |000 = Capture event occurred when detect falling edge transfer on capture source. + * | | |001 = Capture event occurred when detect rising edge transfer on capture source. + * | | |010 = Capture event occurred when detect both falling and rising edge transfer on capture source, and the first capture event occurred at falling edge transfer. + * | | |011 = Capture event occurred when detect both rising and falling edge transfer on capture source, and the first capture event occurred at rising edge transfer. + * | | |110 = First capture event occurred at falling edge, follows capture events are at rising edge transfer on capture source. + * | | |111 = First capture event occurred at rising edge, follows capture events are at falling edge transfer on capture source. + * | | |100, 101 = Reserved. + * | | |Note: Set CAPSRC (TIMERx_CTL[22]) and INTERCAPSEL (TIMERx_EXTCTL[10:8]) to select capture source. + * |[16] |ECNTSSEL |Event Counter Source Selection to Trigger Event Counter Function + * | | |0 = Event Counter input source is from TMx (x= 0~5) pin. + * | | |1 = Event Counter input source is from USB internal SOF output signal. + * |[31:28] |CAPDIVSCL |Timer Capture Source Divider Scale + * | | |This bits indicate the divide scale for capture source divider. + * | | |0000 = Capture source/1. + * | | |0001 = Capture source/2. + * | | |0010 = Capture source/4. + * | | |0011 = Capture source/8. + * | | |0100 = Capture source/16. + * | | |0101 = Capture source/32. + * | | |0110 = Capture source/64. + * | | |0111 = Capture source/128. + * | | |1000 = Capture source/256. + * | | |1001~1111 = Reserved. + * | | |Note: Sets INTERCAPSEL (TIMERx_EXTCTL[10:8]) and CAPSRC (TIMERx_CTL[22]) to select capture source. + * @var TIMER_T::EINTSTS + * Offset: 0x18 Timer External Interrupt Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |CAPIF |Timer Capture Interrupt Flag + * | | |This bit indicates the timer capture interrupt flag status. + * | | |0 = TMx_EXT (x= 0~5) pin, ACMP, internal clock, or external clock capture interrupt did not occur. + * | | |1 = TMx_EXT (x= 0~5) pin, ACMP, internal clock, or external clock capture interrupt occurred. + * | | |Note1: This bit is cleared by writing 1 to it. + * | | |Note2: When CAPEN (TIMERx_EXTCTL[3]) bit is set, the transition on the capture source matches the CAPEDGE (TIMERx_EXTCTL[14:12]) setting, this bit will set to 1 by hardware. + * | | |Note3: There is a new incoming capture event detected before CPU clearing the CAPIF status. + * | | |If the above condition occurred, the timer will keep register TIMERx_CAP unchanged and drop the new capture value. + * @var TIMER_T::TRGCTL + * Offset: 0x1C Timer Trigger Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |TRGSSEL |Trigger Source Select Bit + * | | |This bit is used to select internal trigger source is form timer time-out interrupt signal or capture interrupt signal. + * | | |0 = Time-out interrupt signal is used to internal trigger EPWM/BPWM, PDMA, DAC, and EADC. + * | | |1 = Capture interrupt signal is used to internal trigger EPWM/BPWM, PDMA, DAC, and EADC. + * |[1] |TRGPWM |Trigger EPWM and BPWM Enable Bit + * | | |If this bit is set to 1, each timer time-out event or capture event can be as EPWM and BPWM counter clock source. + * | | |0 = Timer interrupt trigger EPWM and BPWM Disabled. + * | | |1 = Timer interrupt trigger EPWM and BPWM Enabled. + * | | |Note1: This bit is not available in Timer4 and Timer5. + * | | |Note2: If TRGSSEL (TIMERx_TRGCTL[0]) = 0, time-out interrupt signal as EPWM and BPWM counter clock source. + * | | |If TRGSSEL (TIMERx_TRGCTL[0]) = 1, capture interrupt signal as EPWM and BPWM counter clock source. + * |[2] |TRGEADC |Trigger EADC Enable Bit + * | | |If this bit is set to 1, each timer time-out event or capture event can be triggered EADC conversion. + * | | |0 = Timer interrupt trigger EADC Disabled. + * | | |1 = Timer interrupt trigger EADC Enabled. + * | | |Note: If TRGSSEL (TIMERx_TRGCTL[0]) = 0, time-out interrupt signal will trigger EADC conversion. + * | | |If TRGSSEL (TIMERx_TRGCTL[0]) = 1, capture interrupt signal will trigger EADC conversion. + * |[3] |TRGDAC |Trigger DAC Enable Bit + * | | |If this bit is set to 1, each timer time-out event or capture event can be triggered DAC. + * | | |0 = Timer interrupt trigger DAC Disabled. + * | | |1 = Timer interrupt trigger DAC Enabled. + * | | |Note1: This bit is not available in Timer4 and Timer5. + * | | |Note2: If TRGSSEL (TIMERx_TRGCTL[0]) = 0, time-out interrupt signal will trigger DAC. + * | | |If TRGSSEL (TIMERx_TRGCTL[0]) = 1, capture interrupt signal will trigger DAC. + * |[4] |TRGPDMA |Trigger PDMA Enable Bit + * | | |If this bit is set to 1, each timer time-out event or capture event can be triggered PDMA transfer. + * | | |0 = Timer interrupt trigger PDMA Disabled. + * | | |1 = Timer interrupt trigger PDMA Enabled. + * | | |Note: If TRGSSEL (TIMERx_TRGCTL[0]) = 0, time-out interrupt signal will trigger PDMA transfer. + * | | |If TRGSSEL (TIMERx_TRGCTL[0]) = 1, capture interrupt signal will trigger PDMA transfer. + * @var TIMER_T::ALTCTL + * Offset: 0x20 Timer Alternative Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |FUNCSEL |Function Selection + * | | |This bit sets the operation mode of Timer0 ~ Timer3 to PWM function. + * | | |0 = Timer controller is used as timer function. + * | | |1 = Timer controller is used as PWM function. + * | | |Note1: The Timer4 and Timer5 function selection is controlled in TIMERx_CTL[15], x= 4~5. + * | | |Note2: When timer is used as PWM, the clock source of time controller will be forced to PCLKx automatically. + * @var TIMER_T::PWMCTL + * Offset: 0x40 Timer PWM Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |CNTEN |PWM Counter Enable Bit + * | | |0 = PWM counter and clock prescale Stop Running. + * | | |1 = PWM counter and clock prescale Start Running. + * |[2:1] |CNTTYPE |PWM Counter Behavior Type + * | | |These bits are used to set the count type of Timer0 ~ Timer3. The count type of Timer4 and Timer5 is fixed as the up count type. + * | | |00 = Up count type. + * | | |01 = Down count type. + * | | |10 = Up-down count type. + * | | |11 = Reserved. + * | | |Note: These bits are not available in Timer4 and Timer5. + * |[3] |CNTMODE |PWM Counter Mode + * | | |0 = Auto-reload mode. + * | | |1 = One-shot mode. + * |[8] |CTRLD |Center Re-load + * | | |In up-down count type, PERIOD will load to PBUF when current PWM period is completed always and CMP will load to CMPBUF at the center point of current period. + * | | |Note: This bit is not available in Timer4 and Timer5. + * |[9] |IMMLDEN |Immediately Load Enable Bit + * | | |0 = PERIOD will load to PBUF when current PWM period is completed no matter CTRLD is enabled/disabled. + * | | |If CTRLD is disabled, CMP will load to CMPBUF when current PWM period is completed; if CTRLD is enabled in up-down count type, CMP will load to CMPBUF at the center point of current period. + * | | |1 = PERIOD/CMP will load to PBUF/CMPBUF immediately when user update PERIOD/CMP. + * | | |Note1: This bit is not available in Timer4 and Timer5. + * | | |Note2: If IMMLDEN is enabled, CTRLD will be invalid. + * |[12] |WKEN |PWM Wake-up Enable Bit + * | | |If this bit is set to 1, the Timer4 and Timer5 PWM interrupt eventl will generate a wake-up trigger event to CPU. + * | | |0 = PWM interrupt wake-up Disabled. + * | | |1 = PWM interrupt wake-up Enabled. + * | | |Note: This bit is only available in Timer4 and Timer5. + * |[16] |OUTMODE |PWM Output Mode + * | | |This bit controls the output mode of corresponding PWM channel. + * | | |0 = PWM independent mode. + * | | |1 = PWM complementary mode. + * | | |Note: This bit is not available in Timer4 and Timer5. + * |[30] |DBGHALT |ICE Debug Mode Counter Halt (Write Protect) + * | | |If debug mode counter halt is enabled, PWM counter will keep current value until exit ICE debug mode. + * | | |0 = ICE debug mode counter halt disable. + * | | |1 = ICE debug mode counter halt enable. + * | | |Note: This bit is write protected. Refer to SYS_REGLCTL register. + * |[31] |DBGTRIOFF |ICE Debug Mode Acknowledge Disable Bit (Write Protect) + * | | |0 = ICE debug mode acknowledgment effects PWM output. + * | | |PWM output pin will be forced as tri-state while ICE debug mode acknowledged. + * | | |1 = ICE debug mode acknowledgment disabled. + * | | |PWM output pin will keep output no matter ICE debug mode acknowledged or not. + * | | |Note: This bit is write protected. Refer to SYS_REGLCTL register. + * @var TIMER_T::PWMCLKSRC + * Offset: 0x44 Timer PWM Counter Clock Source Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[2:0] |CLKSRC |PWM Counter Clock Source Select + * | | |The PWM counter clock source can be selected from TMRx_CLK or internal timer time-out or capture event in Timer0 ~ Timer3. + * | | |000 = TMRx_CLK. + * | | |001 = Internal TIMER0 time-out or capture event. + * | | |010 = Internal TIMER1 time-out or capture event. + * | | |011 = Internal TIMER2 time-out or capture event. + * | | |100 = Internal TIMER3 time-out or capture event. + * | | |Others = Reserved. + * | | |Note1: These bits are not available in Timer4 and Timer5. + * | | |Note2: If TIMER0 PWM function is enabled, the PWM counter clock source can be selected from TMR0_CLK, TIMER1 interrupt events, TIMER2 interrupt events, or TIMER3 interrupt events. + * @var TIMER_T::PWMCLKPSC + * Offset: 0x48 Timer PWM Counter Clock Pre-scale Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[11:0] |CLKPSC |PWM Counter Clock Pre-scale + * | | |The active clock of PWM counter is decided by counter clock prescale and divided by (CLKPSC + 1). + * | | |If CLKPSC is 0, then there is no scaling in PWM counter clock source. + * | | |Note: The valid value is 12-bit TIMERx_PWMCLKPSC[11:0] in Timer0 ~ Timer3, and 8-bit TIMERx_PWMCLKPSC[7:0] in Timer4 and Timer5. + * @var TIMER_T::PWMCNTCLR + * Offset: 0x4C Timer PWM Clear Counter Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |CNTCLR |Clear PWM Counter Control Bit + * | | |It is automatically cleared by hardware. + * | | |0 = No effect. + * | | |1 = In Timer0 ~ Timer3, clears 16-bit PWM counter to 0x10000 in up and up-down count type and reset counter value to PERIOD in down count type. + * | | |In Timer4 and Timer5, clears 16-bit PWM counter to 0x0 in up count type. + * @var TIMER_T::PWMPERIOD + * Offset: 0x50 Timer PWM Period Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |PERIOD |PWM Period Register + * | | |In up count type: PWM counter counts from 0 to PERIOD, and restarts from 0. + * | | |In down count type: PWM counter counts from PERIOD to 0, and restarts from PERIOD. + * | | |In up-down count type: PWM counter counts from 0 to PERIOD, then decrements to 0 and repeats again. + * | | |In up and down count type: + * | | |PWM period time = (PERIOD + 1) * (CLKPSC + 1) * TMRx_PWMCLK. + * | | |In up-down count type: + * | | |PWM period time = 2 * PERIOD * (CLKPSC+ 1) * TMRx_PWMCLK. + * | | |Note1: The count type of Timer4 and Timer5 is fixed as up count type. + * | | |Note2: User should take care DIRF (TIMERx_PWMCNT[16]) bit in up/down/up-down count type to monitor current counter direction in each count type in Timer0 ~ Timer3. + * @var TIMER_T::PWMCMPDAT + * Offset: 0x54 Timer PWM Comparator Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |CMP |PWM Comparator Register + * | | |PWM CMP is used to compare with PWM CNT to generate PWM output waveform, interrupt events and trigger EADC and PDMA to start conversion. + * @var TIMER_T::PWMDTCTL + * Offset: 0x58 Timer PWM Dead-Time Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[11:0] |DTCNT |Dead-time Counter (Write Protect) + * | | |The dead-time can be calculated from the following two formulas: + * | | |Dead-time = (DTCNT[11:0] + 1) * TMRx_PWMCLK, if DTCKSEL is 0. + * | | |Dead-time = (DTCNT[11:0] + 1) * TMRx_PWMCLK * (CLKPSC + 1), if DTCKSEL is 1. + * | | |Note: These bits are write protected. Refer to SYS_REGLCTL register. + * |[16] |DTEN |Enable Dead-time Insertion for PWMx_CH0 and PWMx_CH1 (Write Protect) + * | | |Dead-time insertion function is only active when PWM complementary mode is enabled. + * | | |If dead-time insertion is inactive, the outputs of PWMx_CH0 and PWMx_CH1 are complementary without any delay. + * | | |0 = Dead-time insertion Disabled on the pin pair. + * | | |1 = Dead-time insertion Enabled on the pin pair. + * | | |Note: This bit is write protected. Refer to SYS_REGLCTL register. + * |[24] |DTCKSEL |Dead-time Clock Select (Write Protect) + * | | |0 = Dead-time clock source from TMRx_PWMCLK without counter clock prescale. + * | | |1 = Dead-time clock source from TMRx_PWMCLK with counter clock prescale. + * | | |Note: This bit is write protected. Refer to SYS_REGLCTL register. + * @var TIMER_T::PWMCNT + * Offset: 0x5C Timer PWM Counter Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |CNT |PWM Counter Value Register (Read Only) + * | | |User can monitor CNT to know the current counter value in 16-bit period counter. + * |[16] |DIRF |PWM Counter Direction Indicator Flag (Read Only) + * | | |0 = Counter is active in down count. + * | | |1 = Counter is active up count. + * | | |Note1: This indicator flag is used for Timer0 ~ Timer3 only. + * | | |Note2: Since the count type of Timer4 ~ Timer5 is fixed as up count, this bit is fixed 0 in Timer4 and Timer5. + * @var TIMER_T::PWMMSKEN + * Offset: 0x60 Timer PWM Output Mask Enable Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |MSKEN0 |PWMx_CH0 Output Mask Enable Bit + * | | |The PWMx_CH0 output signal will be masked when this bit is enabled. + * | | |The PWMx_CH0 will output MSKDAT0 (TIMERx_PWMMSK[0]) data. + * | | |0 = PWMx_CH0 output signal is non-masked. + * | | |1 = PWMx_CH0 output signal is masked and output MSKDAT0 data. + * |[1] |MSKEN1 |PWMx_CH1 Output Mask Enable Bit + * | | |The PWMx_CH1 output signal will be masked when this bit is enabled. + * | | |The PWMx_CH1 will output MSKDAT1 (TIMERx_PWMMSK[1]) data. + * | | |0 = PWMx_CH1 output signal is non-masked. + * | | |1 = PWMx_CH1 output signal is masked and output MSKDAT1 data. + * @var TIMER_T::PWMMSK + * Offset: 0x64 Timer PWM Output Mask Data Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |MSKDAT0 |PWMx_CH0 Output Mask Data Control Bit + * | | |This bit is used to control the output state of PWMx_CH0 pin when PWMx_CH0 output mask function is enabled (MSKEN0 = 1). + * | | |0 = Output logic Low to PWMx_CH0. + * | | |1 = Output logic High to PWMx_CH0. + * |[1] |MSKDAT1 |PWMx_CH1 Output Mask Data Control Bit + * | | |This bit is used to control the output state of PWMx_CH1 pin when PWMx_CH1 output mask function is enabled (MSKEN1 = 1). + * | | |0 = Output logic Low to PWMx_CH1. + * | | |1 = Output logic High to PWMx_CH1. + * @var TIMER_T::PWMBNF + * Offset: 0x68 Timer PWM Brake Pin Noise Filter Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |BRKNFEN |Brake Pin Noise Filter Enable Bit + * | | |0 = Pin noise filter detect of PWMx_BRAKEy Disabled. + * | | |1 = Pin noise filter detect of PWMx_BRAKEy Enabled. + * |[3:1] |BRKNFSEL |Brake Pin Noise Filter Clock Selection + * | | |000 = Noise filter clock is PCLKx. + * | | |001 = Noise filter clock is PCLKx/2. + * | | |010 = Noise filter clock is PCLKx/4. + * | | |011 = Noise filter clock is PCLKx/8. + * | | |100 = Noise filter clock is PCLKx/16. + * | | |101 = Noise filter clock is PCLKx/32. + * | | |110 = Noise filter clock is PCLKx/64. + * | | |111 = Noise filter clock is PCLKx/128. + * |[6:4] |BRKFCNT |Brake Pin Noise Filter Count + * | | |The fields is used to control the active noise filter sample time. + * | | |Once noise filter sample time = (Period time of BRKNFSEL) * (BRKFCNT + 1). + * |[7] |BRKPINV |Brake Pin Detection Control Bit + * | | |0 = Brake pin event will be detected if PWMx_BRAKEy pin status transfer from low to high in edge-detect, or pin status is high in level-detect. + * | | |1 = Brake pin event will be detected if PWMx_BRAKEy pin status transfer from high to low in edge-detect, or pin status is low in level-detect . + * |[17:16] |BKPINSRC |Brake Pin Source Select + * | | |00 = Brake pin source comes from PWM0_BRAKE0 pin. + * | | |01 = Brake pin source comes from PWM0_BRAKE1 pin. + * | | |10 = Brake pin source comes from PWM1_BRAKE0 pin. + * | | |11 = Brake pin source comes from PWM1_BRAKE1 pin. + * @var TIMER_T::PWMFAILBRK + * Offset: 0x6C Timer PWM System Fail Brake Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |CSSBRKEN |Clock Security System Detection Trigger PWM Brake Function Enable Bit + * | | |0 = Brake Function triggered by clock fail detection Disabled. + * | | |1 = Brake Function triggered by clock fail detection Enabled. + * |[1] |BODBRKEN |Brown-out Detection Trigger PWM Brake Function Enable Bit + * | | |0 = Brake Function triggered by BOD event Disabled. + * | | |1 = Brake Function triggered by BOD event Enabled. + * |[2] |RAMBRKEN |SRAM Parity Error Detection Trigger PWM Brake Function Enable Bit + * | | |0 = Brake Function triggered by SRAM parity error detection Disabled. + * | | |1 = Brake Function triggered by SRAM parity error detection Enabled. + * |[3] |CORBRKEN |Core Lockup Detection Trigger PWM Brake Function Enable Bit + * | | |0 = Brake Function triggered by core lockup event Disabled. + * | | |1 = Brake Function triggered by core lockup event Enabled. + * @var TIMER_T::PWMBRKCTL + * Offset: 0x70 Timer PWM Brake Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |CPO0EBEN |Enable Internal ACMP0_O Digital Output As Edge-detect Brake Source (Write Protect) + * | | |0 = Internal ACMP0_O signal as edge-detect brake source Disabled. + * | | |1 = Internal ACMP0_O signal as edge-detect brake source Enabled. + * | | |Note1: Only internal ACMP0_O signal from low to high will be detected as brake event. + * | | |Note2: This bit is write protected. Refer to SYS_REGLCTL register. + * |[1] |CPO1EBEN |Enable Internal ACMP1_O Digital Output As Edge-detect Brake Source (Write Protect) + * | | |0 = Internal ACMP1_O signal as edge-detect brake source Disabled. + * | | |1 = Internal ACMP1_O signal as edge-detect brake source Enabled. + * | | |Note1: Only internal ACMP1_O signal from low to high will be detected as brake event. + * | | |Note2: This bit is write protected. Refer to SYS_REGLCTL register. + * |[4] |BRKPEEN |Enable TM_BRAKEx Pin As Edge-detect Brake Source (Write Protect) + * | | |0 = PWMx_BRAKEy pin event as edge-detect brake source Disabled. + * | | |1 = PWMx_BRAKEy pin event as edge-detect brake source Enabled. + * | | |Note: This bit is write protected. Refer to SYS_REGLCTL register. + * |[7] |SYSEBEN |Enable System Fail As Edge-detect Brake Source (Write Protect) + * | | |0 = System fail condition as edge-detect brake source Disabled. + * | | |1 = System fail condition as edge-detect brake source Enabled. + * | | |Note: This bit is write protected. Refer to SYS_REGLCTL register. + * |[8] |CPO0LBEN |Enable Internal ACMP0_O Digital Output As Level-detect Brake Source (Write Protect) + * | | |0 = Internal ACMP0_O signal as level-detect brake source Disabled. + * | | |1 = Internal ACMP0_O signal as level-detect brake source Enabled. + * | | |Note1: Only internal ACMP0_O signal from low to high will be detected as brake event. + * | | |Note2: This bit is write protected. Refer to SYS_REGLCTL register. + * |[9] |CPO1LBEN |Enable Internal ACMP1_O Digital Output As Level-detect Brake Source (Write Protect) + * | | |0 = Internal ACMP1_O signal as level-detect brake source Disabled. + * | | |1 = Internal ACMP1_O signal as level-detect brake source Enabled. + * | | |Note1: Only internal ACMP1_O signal from low to high will be detected as brake event. + * | | |Note: This bit is write protected. Refer to SYS_REGLCTL register. + * |[12] |BRKPLEN |Enable TM_BRAKEx Pin As Level-detect Brake Source (Write Protect) + * | | |0 = PWMx_BRAKEy pin event as level-detect brake source Disabled. + * | | |1 = PWMx_BRAKEy pin event as level-detect brake source Enabled. + * | | |Note: This bit is write protected. Refer to SYS_REGLCTL register. + * |[15] |SYSLBEN |Enable System Fail As Level-detect Brake Source (Write Protect) + * | | |0 = System fail condition as level-detect brake source Disabled. + * | | |1 = System fail condition as level-detect brake source Enabled. + * | | |Note: This bit is write protected. Refer to SYS_REGLCTL register. + * |[17:16] |BRKAEVEN |PWM Brake Action Select for PWMx_CH0 (Write Protect) + * | | |00 = PWMx_BRAKEy brake event will not affect PWMx_CH0 output. + * | | |01 = PWMx_CH0 output tri-state when PWMx_BRAKEy brake event happened. + * | | |10 = PWMx_CH0 output low level when PWMx_BRAKEy brake event happened. + * | | |11 = PWMx_CH0 output high level when PWMx_BRAKEy brake event happened. + * | | |Note: These bits are write protected. Refer to SYS_REGLCTL register. + * |[19:18] |BRKAODD |PWM Brake Action Select for PWMx_CH1 (Write Protect) + * | | |00 = PWMx_BRAKEy brake event will not affect PWMx_CH1 output. + * | | |01 = PWMx_CH1 output tri-state when PWMx_BRAKEy brake event happened. + * | | |10 = PWMx_CH1 output low level when PWMx_BRAKEy brake event happened. + * | | |11 = PWMx_CH1 output high level when PWMx_BRAKEy brake event happened. + * | | |Note: These bits are write protected. Refer to SYS_REGLCTL register. + * @var TIMER_T::PWMPOLCTL + * Offset: 0x74 Timer PWM Pin Output Polar Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |PINV0 |PWMx_CH0 Output Pin Polar Control Bit + * | | |The bit is used to control polarity state of PWMx_CH0 output pin. + * | | |0 = PWMx_CH0 output pin polar inverse Disabled. + * | | |1 = PWMx_CH0 output pin polar inverse Enabled. + * | | |Note: In Timer4 and Timer5, the PWMx_CH0 output pin can be selected as TMx or TMx_EXT pin by POSEL (TIMERx_PWMPOEN[8]), x= 4~5. + * |[1] |PINV1 |PWMx_CH1 Output Pin Polar Control Bit + * | | |The bit is used to control polarity state of PWMx_CH1 output pin. + * | | |0 = PWMx_CH1 output pin polar inverse Disabled. + * | | |1 = PWMx_CH1 output pin polar inverse Enabled. + * | | |Note: This bit is not available in Timer4 and Timer5. + * @var TIMER_T::PWMPOEN + * Offset: 0x78 Timer PWM Pin Output Enable Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |POEN0 |PWMx_CH0 Output Pin Enable Bit + * | | |0 = PWMx_CH0 pin at tri-state mode. + * | | |1 = PWMx_CH0 pin in output mode. + * | | |Note: In Timer4 and Timer5, the PWMx_CH0 output pin can be selected as TMx or TMx_EXT pin by POSEL (TIMERx_PWMPOEN[8]), x= 4~5. + * |[1] |POEN1 |PWMx_CH1 Output Pin Enable Bit + * | | |0 = PWMx_CH1 pin at tri-state mode. + * | | |1 = PWMx_CH1 pin in output mode. + * | | |Note: This bit is not available in Timer4 and Timer5. + * |[8] |POSEL |PWMx_CH0 Output Pin Select + * | | |This bit is used to select the output channel of Timer4 and Timer5 PWM. + * | | |0 = PWMx_CH0 pin is TMx. + * | | |1 = PWMx_CH0 pin is TMx_EXT. + * | | |Note: This bit is only available in Timer4 and Timer5. + * @var TIMER_T::PWMSWBRK + * Offset: 0x7C Timer PWM Software Trigger Brake Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |BRKETRG |Software Trigger Edge-detect Brake Source (Write Only) (Write Protect) + * | | |Write 1 to this bit will trigger PWM edge-detect brake source, then BRKEIF0 and BRKEIF1 will set to 1 automatically in TIMERx_PWMINTSTS1 register. + * | | |Note: This bit is write protected. Refer to SYS_REGLCTL register. + * |[8] |BRKLTRG |Software Trigger Level-detect Brake Source (Write Only) (Write Protect) + * | | |Write 1 to this bit will trigger PWM level-detect brake source, then BRKLIF0 and BRKLIF1 will set to 1 automatically in TIMERx_PWMINTSTS1 register. + * | | |Note: This bit is write protected. Refer to SYS_REGLCTL register. + * @var TIMER_T::PWMINTEN0 + * Offset: 0x80 Timer PWM Interrupt Enable Register 0 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |ZIEN |PWM Zero Point Interrupt Enable Bit + * | | |0 = Zero point interrupt Disabled. + * | | |1 = Zero point interrupt Enabled. + * | | |Note: This bit is not available in Timer4 and Timer5. + * |[1] |PIEN |PWM Period Point Interrupt Enable Bit + * | | |0 = Period point interrupt Disabled. + * | | |1 = Period point interrupt Enabled. + * | | |Note: In up-down count type, period point means the center point of current PWM period. + * |[2] |CMPUIEN |PWM Compare Up Count Interrupt Enable Bit + * | | |0 = Compare up count interrupt Disabled. + * | | |1 = Compare up count interrupt Enabled. + * |[3] |CMPDIEN |PWM Compare Down Count Interrupt Enable Bit + * | | |0 = Compare down count interrupt Disabled. + * | | |1 = Compare down count interrupt Enabled. + * | | |Note: This bit is not available in Timer4 and Timer5. + * @var TIMER_T::PWMINTEN1 + * Offset: 0x84 Timer PWM Interrupt Enable Register 1 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |BRKEIEN |PWM Edge-detect Brake Interrupt Enable (Write Protect) + * | | |0 = PWM edge-detect brake interrupt Disabled. + * | | |1 = PWM edge-detect brake interrupt Enabled. + * | | |Note: This bit is write protected. Refer to SYS_REGLCTL register. + * |[8] |BRKLIEN |PWM Level-detect Brake Interrupt Enable (Write Protect) + * | | |0 = PWM level-detect brake interrupt Disabled. + * | | |1 = PWM level-detect brake interrupt Enabled. + * | | |Note: This bit is write protected. Refer to SYS_REGLCTL register. + * @var TIMER_T::PWMINTSTS0 + * Offset: 0x88 Timer PWM Interrupt Status Register 0 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |ZIF |PWM Zero Point Interrupt Flag + * | | |This bit is set by hardware when TIMERx_PWM counter reaches zero. + * | | |Note1: This bit is not available in Timer4 and Timer5. + * | | |Note2: This bit is cleared by writing 1 to it. + * |[1] |PIF |PWM Period Point Interrupt Flag + * | | |This bit is set by hardware when TIMERx_PWM counter reaches PERIOD. + * | | |Note1: In up-down count type, PIF flag means the center point flag of current PWM period. + * | | |Note2: This bit is cleared by writing 1 to it. + * |[2] |CMPUIF |PWM Compare Up Count Interrupt Flag + * | | |This bit is set by hardware when TIMERx_PWM counter in up count direction and reaches CMP. + * | | |Note1: If CMP equal to PERIOD, there is no CMPUIF flag in up count type and up-down count type.. + * | | |Note2: This bit is cleared by writing 1 to it. + * |[3] |CMPDIF |PWM Compare Down Count Interrupt Flag + * | | |This bit is set by hardware when TIMERx_PWM counter in down count direction and reaches CMP. + * | | |Note1: This bit is not available in Timer4 and Timer5. + * | | |Note2: If CMP equal to PERIOD, there is no CMPDIF flag in down count type. + * | | |Note3: This bit is cleared by writing 1 to it. + * @var TIMER_T::PWMINTSTS1 + * Offset: 0x8C Timer PWM Interrupt Status Register 1 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |BRKEIF0 |Edge-detect Brake Interrupt Flag on PWMx_CH0 (Write Protect) + * | | |0 = PWMx_CH0 edge-detect brake event do not happened. + * | | |1 = PWMx_CH0 edge-detect brake event happened. + * | | |Note1: This bit is cleared by writing 1 to it. + * | | |Note2: This bit is write protected. Refer to SYS_REGLCTL register. + * |[1] |BRKEIF1 |Edge-detect Brake Interrupt Flag PWMx_CH1 (Write Protect) + * | | |0 = PWMx_CH1 edge-detect brake event do not happened. + * | | |1 = PWMx_CH1 edge-detect brake event happened. + * | | |Note1: This bit is cleared by writing 1 to it. + * | | |Note2: This bit is write protected. Refer to SYS_REGLCTL register. + * |[8] |BRKLIF0 |Level-detect Brake Interrupt Flag on PWMx_CH0 (Write Protect) + * | | |0 = PWMx_CH0 level-detect brake event do not happened. + * | | |1 = PWMx_CH0 level-detect brake event happened. + * | | |Note1: This bit is cleared by writing 1 to it. + * | | |Note2: This bit is write protected. Refer to SYS_REGLCTL register. + * |[9] |BRKLIF1 |Level-detect Brake Interrupt Flag on PWMx_CH1 (Write Protect) + * | | |0 = PWMx_CH1 level-detect brake event do not happened. + * | | |1 = PWMx_CH1 level-detect brake event happened. + * | | |Note1: This bit is cleared by writing 1 to it. + * | | |Note2: This bit is write protected. Refer to SYS_REGLCTL register. + * |[16] |BRKESTS0 |Edge -detect Brake Status of PWMx_CH0 (Read Only) + * | | |0 = PWMx_CH0 edge-detect brake state is released. + * | | |1 = PWMx_CH0 at edge-detect brake state. + * | | |Note: User can set BRKEIF0 1 to clear BRKEIF0 flag and PWMx_CH0 will release brake state when current PWM period finished and resume PWMx_CH0 output waveform start from next full PWM period. + * |[17] |BRKESTS1 |Edge-detect Brake Status of PWMx_CH1 (Read Only) + * | | |0 = PWMx_CH1 edge-detect brake state is released. + * | | |1 = PWMx_CH1 at edge-detect brake state. + * | | |Note: User can set BRKEIF1 1 to clear BRKEIF1 flag and PWMx_CH1 will release brake state when current PWM period finished and resume PWMx_CH1 output waveform start from next full PWM period. + * |[24] |BRKLSTS0 |Level-detect Brake Status of PWMx_CH0 (Read Only) + * | | |0 = PWMx_CH0 level-detect brake state is released. + * | | |1 = PWMx_CH0 at level-detect brake state. + * | | |Note: If TIMERx_PWM level-detect brake source has released, both PWMx_CH0 and PWMx_CH1 will release brake state when current PWM period finished and resume PWMx_CH0 and PWMx_CH1 output waveform start from next full PWM period. + * |[25] |BRKLSTS1 |Level-detect Brake Status of PWMx_CH1 (Read Only) + * | | |0 = PWMx_CH1 level-detect brake state is released. + * | | |1 = PWMx_CH1 at level-detect brake state. + * | | |Note: If TIMERx_PWM level-detect brake source has released, both PWMx_CH0 and PWMx_CH1 will release brake state when current PWM period finished and resume PWMx_CH0 and PWMx_CH1 output waveform start from next full PWM period. + * @var TIMER_T::PWMTRGCTL + * Offset: 0x90 Timer PWM Trigger Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[2:0] |TRGSEL |PWM Counter Event Source Select to Trigger Conversion + * | | |In Timer0 ~ Timer3, + * | | |000 = Trigger conversion at zero point (ZIF). + * | | |001 = Trigger conversion at period point (PIF). + * | | |010 = Trigger conversion at zero or period point (ZIF or PIF). + * | | |011 = Trigger conversion at compare up count point (CMPUIF). + * | | |100 = Trigger conversion at compare down count point (CMPDIF). + * | | |In Timer4 and Timer5, + * | | |001 = Trigger conversion at period point (PIF). + * | | |011 = Trigger conversion at compare up count point (CMPUIF). + * | | |101 = Trigger conversion at period or compare up count point (PIF or CMPUIF). + * | | |Others = Reserved. + * |[7] |TRGEADC |PWM Counter Event Trigger EADC Conversion Enable Bit + * | | |0 = PWM counter event trigger EADC conversion Disabled. + * | | |1 = PWM counter event trigger EADC conversion Enabled. + * | | |Note: Set TRGSEL (TIMERx_PWMTRGCTL[2:0]) to select PWM trigger conversion source. + * |[9] |TRGPDMA |PWM Counter Event Trigger PDMA Conversion Enable Bit + * | | |0 = PWM counter event trigger PDMA conversion Disabled. + * | | |1 = PWM counter event trigger PDMA conversion Enabled. + * | | |Note: Set TRGSEL (TIMERx_PWMTRGCTL[2:0]) to select PWM trigger conversion source. + * @var TIMER_T::PWMSCTL + * Offset: 0x94 Timer PWM Synchronous Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[1:0] |SYNCMODE |PWM Synchronous Mode Enable Select + * | | |00 = PWM synchronous function Disabled. + * | | |01 = PWM synchronous counter start function Enabled. + * | | |10 = Reserved. + * | | |11 = PWM synchronous counter clear function Enabled. + * |[8] |SYNCSRC |PWM Synchronous Counter Start/Clear Source Select + * | | |0 = Counter synchronous start/clear by trigger TIMER0_PWMSTRG STRGEN. + * | | |1 = Counter synchronous start/clear by trigger TIMER2_PWMSTRG STRGEN. + * | | |Note1: If TIMER0/1/2/3 PWM counter synchronous source are from TIMER0, TIMER0_PWMSCTL[8], TIMER1_PWMSCTL[8], TIMER2_PWMSCTL[8] and TIMER3_PWMSCTL[8] should be 0. + * | | |Note2: If TIMER0/1/ PWM counter synchronous source are from TIMER0, TIMER0_PWMSCTL[8] and TIMER1_PWMSCTL[8] should be set 0, and TIMER2/3/ PWM counter synchronous source are from TIMER2, TIME2_PWMSCTL[8] and TIMER3_PWMSCTL[8] should be set 1. + * @var TIMER_T::PWMSTRG + * Offset: 0x98 Timer PWM Synchronous Trigger Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |STRGEN |PWM Counter Synchronous Trigger Enable Bit (Write Only) + * | | |PMW counter synchronous function is used to make selected PWM channels (include TIMER0/1/2/3 PWM, TIMER0/1 PWM and TIMER2/3 PWM) start counting or clear counter at the same time according to TIMERx_PWMSCTL setting. + * | | |Note: This bit is only available in TIMER0 and TIMER2. + * @var TIMER_T::PWMSTATUS + * Offset: 0x9C Timer PWM Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |CNTMAXF |PWM Counter Equal to 0xFFFF Flag + * | | |0 = The PWM counter value never reached its maximum value 0xFFFF. + * | | |1 = The PWM counter value has reached its maximum value. + * | | |Note: This bit is cleared by writing 1 to it. + * |[8] |WKF |PWM Wake-up Flag + * | | |0 = PWM interrupt wake-up has not occurred. + * | | |1 = PWM interrupt wake-up has occurred. + * | | |Note1: This bit is only available in Timer4 and Timer5. + * | | |Note2: This bit is cleared by writing 1 to it. + * |[16] |EADCTRGF |Trigger EADC Start Conversion Flag + * | | |0 = PWM counter event trigger EADC start conversion is not occurred. + * | | |1 = PWM counter event trigger EADC start conversion has occurred. + * | | |Note: This bit is cleared by writing 1 to it. + * |[19] |PDMATRGF |Trigger PDMA Start Conversion Flag + * | | |0 = PWM counter event trigger PDMA start conversion is not occurred. + * | | |1 = PWM counter event trigger PDMA start conversion has occurred. + * | | |Note1: This bit is only available in Timer4 and Timer5. + * | | |Note2: This bit is cleared by writing 1 to it. + * @var TIMER_T::PWMPBUF + * Offset: 0xA0 Timer PWM Period Buffer Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |PBUF |PWM Period Buffer Register (Read Only) + * | | |Used as PERIOD active register. + * @var TIMER_T::PWMCMPBUF + * Offset: 0xA4 Timer PWM Comparator Buffer Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |CMPBUF |PWM Comparator Buffer Register (Read Only) + * | | |Used as CMP active register. + */ + __IO uint32_t CTL; /*!< [0x0000] Timer Control Register */ + __IO uint32_t CMP; /*!< [0x0004] Timer Comparator Register */ + __IO uint32_t INTSTS; /*!< [0x0008] Timer Interrupt Status Register */ + __IO uint32_t CNT; /*!< [0x000c] Timer Data Register */ + __I uint32_t CAP; /*!< [0x0010] Timer Capture Data Register */ + __IO uint32_t EXTCTL; /*!< [0x0014] Timer External Control Register */ + __IO uint32_t EINTSTS; /*!< [0x0018] Timer External Interrupt Status Register */ + __IO uint32_t TRGCTL; /*!< [0x001c] Timer Trigger Control Register */ + __IO uint32_t ALTCTL; /*!< [0x0020] Timer Alternative Control Register */ + __I uint32_t RESERVE0[7]; + __IO uint32_t PWMCTL; /*!< [0x0040] Timer PWM Control Register */ + __IO uint32_t PWMCLKSRC; /*!< [0x0044] Timer PWM Counter Clock Source Register */ + __IO uint32_t PWMCLKPSC; /*!< [0x0048] Timer PWM Counter Clock Pre-scale Register */ + __IO uint32_t PWMCNTCLR; /*!< [0x004c] Timer PWM Clear Counter Register */ + __IO uint32_t PWMPERIOD; /*!< [0x0050] Timer PWM Period Register */ + __IO uint32_t PWMCMPDAT; /*!< [0x0054] Timer PWM Comparator Register */ + __IO uint32_t PWMDTCTL; /*!< [0x0058] Timer PWM Dead-Time Control Register */ + __I uint32_t PWMCNT; /*!< [0x005c] Timer PWM Counter Register */ + __IO uint32_t PWMMSKEN; /*!< [0x0060] Timer PWM Output Mask Enable Register */ + __IO uint32_t PWMMSK; /*!< [0x0064] Timer PWM Output Mask Data Control Register */ + __IO uint32_t PWMBNF; /*!< [0x0068] Timer PWM Brake Pin Noise Filter Register */ + __IO uint32_t PWMFAILBRK; /*!< [0x006c] Timer PWM System Fail Brake Control Register */ + __IO uint32_t PWMBRKCTL; /*!< [0x0070] Timer PWM Brake Control Register */ + __IO uint32_t PWMPOLCTL; /*!< [0x0074] Timer PWM Pin Output Polar Control Register */ + __IO uint32_t PWMPOEN; /*!< [0x0078] Timer PWM Pin Output Enable Register */ + __O uint32_t PWMSWBRK; /*!< [0x007c] Timer PWM Software Trigger Brake Control Register */ + __IO uint32_t PWMINTEN0; /*!< [0x0080] Timer PWM Interrupt Enable Register 0 */ + __IO uint32_t PWMINTEN1; /*!< [0x0084] Timer PWM Interrupt Enable Register 1 */ + __IO uint32_t PWMINTSTS0; /*!< [0x0088] Timer PWM Interrupt Status Register 0 */ + __IO uint32_t PWMINTSTS1; /*!< [0x008c] Timer PWM Interrupt Status Register 1 */ + __IO uint32_t PWMTRGCTL; /*!< [0x0090] Timer PWM Trigger Control Register */ + __IO uint32_t PWMSCTL; /*!< [0x0094] Timer PWM Synchronous Control Register */ + __O uint32_t PWMSTRG; /*!< [0x0098] Timer PWM Synchronous Trigger Register */ + __IO uint32_t PWMSTATUS; /*!< [0x009c] Timer PWM Status Register */ + __I uint32_t PWMPBUF; /*!< [0x00a0] Timer PWM Period Buffer Register */ + __I uint32_t PWMCMPBUF; /*!< [0x00a4] Timer PWM Comparator Buffer Register */ + +} TIMER_T; + +/** + @addtogroup TIMER_CONST TIMER Bit Field Definition + Constant Definitions for TIMER Controller + @{ +*/ + +#define TIMER_CTL_PSC_Pos (0) /*!< TIMER_T::CTL: PSC Position */ +#define TIMER_CTL_PSC_Msk (0xfful << TIMER_CTL_PSC_Pos) /*!< TIMER_T::CTL: PSC Mask */ + +#define TIMER_CTL_FUNCSEL_Pos (15) /*!< TIMER_T::CTL: FUNCSEL Position */ +#define TIMER_CTL_FUNCSEL_Msk (0x1ul << TIMER_CTL_FUNCSEL_Pos) /*!< TIMER_T::CTL: FUNCSEL Mask */ + +#define TIMER_CTL_INTRGEN_Pos (19) /*!< TIMER_T::CTL: INTRGEN Position */ +#define TIMER_CTL_INTRGEN_Msk (0x1ul << TIMER_CTL_INTRGEN_Pos) /*!< TIMER_T::CTL: INTRGEN Mask */ + +#define TIMER_CTL_PERIOSEL_Pos (20) /*!< TIMER_T::CTL: PERIOSEL Position */ +#define TIMER_CTL_PERIOSEL_Msk (0x1ul << TIMER_CTL_PERIOSEL_Pos) /*!< TIMER_T::CTL: PERIOSEL Mask */ + +#define TIMER_CTL_TGLPINSEL_Pos (21) /*!< TIMER_T::CTL: TGLPINSEL Position */ +#define TIMER_CTL_TGLPINSEL_Msk (0x1ul << TIMER_CTL_TGLPINSEL_Pos) /*!< TIMER_T::CTL: TGLPINSEL Mask */ + +#define TIMER_CTL_CAPSRC_Pos (22) /*!< TIMER_T::CTL: CAPSRC Position */ +#define TIMER_CTL_CAPSRC_Msk (0x1ul << TIMER_CTL_CAPSRC_Pos) /*!< TIMER_T::CTL: CAPSRC Mask */ + +#define TIMER_CTL_WKEN_Pos (23) /*!< TIMER_T::CTL: WKEN Position */ +#define TIMER_CTL_WKEN_Msk (0x1ul << TIMER_CTL_WKEN_Pos) /*!< TIMER_T::CTL: WKEN Mask */ + +#define TIMER_CTL_EXTCNTEN_Pos (24) /*!< TIMER_T::CTL: EXTCNTEN Position */ +#define TIMER_CTL_EXTCNTEN_Msk (0x1ul << TIMER_CTL_EXTCNTEN_Pos) /*!< TIMER_T::CTL: EXTCNTEN Mask */ + +#define TIMER_CTL_ACTSTS_Pos (25) /*!< TIMER_T::CTL: ACTSTS Position */ +#define TIMER_CTL_ACTSTS_Msk (0x1ul << TIMER_CTL_ACTSTS_Pos) /*!< TIMER_T::CTL: ACTSTS Mask */ + +#define TIMER_CTL_OPMODE_Pos (27) /*!< TIMER_T::CTL: OPMODE Position */ +#define TIMER_CTL_OPMODE_Msk (0x3ul << TIMER_CTL_OPMODE_Pos) /*!< TIMER_T::CTL: OPMODE Mask */ + +#define TIMER_CTL_INTEN_Pos (29) /*!< TIMER_T::CTL: INTEN Position */ +#define TIMER_CTL_INTEN_Msk (0x1ul << TIMER_CTL_INTEN_Pos) /*!< TIMER_T::CTL: INTEN Mask */ + +#define TIMER_CTL_CNTEN_Pos (30) /*!< TIMER_T::CTL: CNTEN Position */ +#define TIMER_CTL_CNTEN_Msk (0x1ul << TIMER_CTL_CNTEN_Pos) /*!< TIMER_T::CTL: CNTEN Mask */ + +#define TIMER_CTL_ICEDEBUG_Pos (31) /*!< TIMER_T::CTL: ICEDEBUG Position */ +#define TIMER_CTL_ICEDEBUG_Msk (0x1ul << TIMER_CTL_ICEDEBUG_Pos) /*!< TIMER_T::CTL: ICEDEBUG Mask */ + +#define TIMER_CMP_CMPDAT_Pos (0) /*!< TIMER_T::CMP: CMPDAT Position */ +#define TIMER_CMP_CMPDAT_Msk (0xfffffful << TIMER_CMP_CMPDAT_Pos) /*!< TIMER_T::CMP: CMPDAT Mask */ + +#define TIMER_INTSTS_TIF_Pos (0) /*!< TIMER_T::INTSTS: TIF Position */ +#define TIMER_INTSTS_TIF_Msk (0x1ul << TIMER_INTSTS_TIF_Pos) /*!< TIMER_T::INTSTS: TIF Mask */ + +#define TIMER_INTSTS_TWKF_Pos (1) /*!< TIMER_T::INTSTS: TWKF Position */ +#define TIMER_INTSTS_TWKF_Msk (0x1ul << TIMER_INTSTS_TWKF_Pos) /*!< TIMER_T::INTSTS: TWKF Mask */ + +#define TIMER_CNT_CNT_Pos (0) /*!< TIMER_T::CNT: CNT Position */ +#define TIMER_CNT_CNT_Msk (0xfffffful << TIMER_CNT_CNT_Pos) /*!< TIMER_T::CNT: CNT Mask */ + +#define TIMER_CNT_RSTACT_Pos (31) /*!< TIMER_T::CNT: RSTACT Position */ +#define TIMER_CNT_RSTACT_Msk (0x1ul << TIMER_CNT_RSTACT_Pos) /*!< TIMER_T::CNT: RSTACT Mask */ + +#define TIMER_CAP_CAPDAT_Pos (0) /*!< TIMER_T::CAP: CAPDAT Position */ +#define TIMER_CAP_CAPDAT_Msk (0xfffffful << TIMER_CAP_CAPDAT_Pos) /*!< TIMER_T::CAP: CAPDAT Mask */ + +#define TIMER_EXTCTL_CNTPHASE_Pos (0) /*!< TIMER_T::EXTCTL: CNTPHASE Position */ +#define TIMER_EXTCTL_CNTPHASE_Msk (0x1ul << TIMER_EXTCTL_CNTPHASE_Pos) /*!< TIMER_T::EXTCTL: CNTPHASE Mask */ + +#define TIMER_EXTCTL_CAPEN_Pos (3) /*!< TIMER_T::EXTCTL: CAPEN Position */ +#define TIMER_EXTCTL_CAPEN_Msk (0x1ul << TIMER_EXTCTL_CAPEN_Pos) /*!< TIMER_T::EXTCTL: CAPEN Mask */ + +#define TIMER_EXTCTL_CAPFUNCS_Pos (4) /*!< TIMER_T::EXTCTL: CAPFUNCS Position */ +#define TIMER_EXTCTL_CAPFUNCS_Msk (0x1ul << TIMER_EXTCTL_CAPFUNCS_Pos) /*!< TIMER_T::EXTCTL: CAPFUNCS Mask */ + +#define TIMER_EXTCTL_CAPIEN_Pos (5) /*!< TIMER_T::EXTCTL: CAPIEN Position */ +#define TIMER_EXTCTL_CAPIEN_Msk (0x1ul << TIMER_EXTCTL_CAPIEN_Pos) /*!< TIMER_T::EXTCTL: CAPIEN Mask */ + +#define TIMER_EXTCTL_CAPDBEN_Pos (6) /*!< TIMER_T::EXTCTL: CAPDBEN Position */ +#define TIMER_EXTCTL_CAPDBEN_Msk (0x1ul << TIMER_EXTCTL_CAPDBEN_Pos) /*!< TIMER_T::EXTCTL: CAPDBEN Mask */ + +#define TIMER_EXTCTL_CNTDBEN_Pos (7) /*!< TIMER_T::EXTCTL: CNTDBEN Position */ +#define TIMER_EXTCTL_CNTDBEN_Msk (0x1ul << TIMER_EXTCTL_CNTDBEN_Pos) /*!< TIMER_T::EXTCTL: CNTDBEN Mask */ + +#define TIMER_EXTCTL_INTERCAPSEL_Pos (8) /*!< TIMER_T::EXTCTL: INTERCAPSEL Position */ +#define TIMER_EXTCTL_INTERCAPSEL_Msk (0x7ul << TIMER_EXTCTL_INTERCAPSEL_Pos) /*!< TIMER_T::EXTCTL: INTERCAPSEL Mask */ + +#define TIMER_EXTCTL_CAPEDGE_Pos (12) /*!< TIMER_T::EXTCTL: CAPEDGE Position */ +#define TIMER_EXTCTL_CAPEDGE_Msk (0x7ul << TIMER_EXTCTL_CAPEDGE_Pos) /*!< TIMER_T::EXTCTL: CAPEDGE Mask */ + +#define TIMER_EXTCTL_ECNTSSEL_Pos (16) /*!< TIMER_T::EXTCTL: ECNTSSEL Position */ +#define TIMER_EXTCTL_ECNTSSEL_Msk (0x1ul << TIMER_EXTCTL_ECNTSSEL_Pos) /*!< TIMER_T::EXTCTL: ECNTSSEL Mask */ + +#define TIMER_EXTCTL_CAPDIVSCL_Pos (28) /*!< TIMER_T::EXTCTL: CAPDIVSCL Position */ +#define TIMER_EXTCTL_CAPDIVSCL_Msk (0xful << TIMER_EXTCTL_CAPDIVSCL_Pos) /*!< TIMER_T::EXTCTL: CAPDIVSCL Mask */ + +#define TIMER_EINTSTS_CAPIF_Pos (0) /*!< TIMER_T::EINTSTS: CAPIF Position */ +#define TIMER_EINTSTS_CAPIF_Msk (0x1ul << TIMER_EINTSTS_CAPIF_Pos) /*!< TIMER_T::EINTSTS: CAPIF Mask */ + +#define TIMER_TRGCTL_TRGSSEL_Pos (0) /*!< TIMER_T::TRGCTL: TRGSSEL Position */ +#define TIMER_TRGCTL_TRGSSEL_Msk (0x1ul << TIMER_TRGCTL_TRGSSEL_Pos) /*!< TIMER_T::TRGCTL: TRGSSEL Mask */ + +#define TIMER_TRGCTL_TRGPWM_Pos (1) /*!< TIMER_T::TRGCTL: TRGPWM Position */ +#define TIMER_TRGCTL_TRGPWM_Msk (0x1ul << TIMER_TRGCTL_TRGPWM_Pos) /*!< TIMER_T::TRGCTL: TRGPWM Mask */ + +#define TIMER_TRGCTL_TRGEADC_Pos (2) /*!< TIMER_T::TRGCTL: TRGEADC Position */ +#define TIMER_TRGCTL_TRGEADC_Msk (0x1ul << TIMER_TRGCTL_TRGEADC_Pos) /*!< TIMER_T::TRGCTL: TRGEADC Mask */ + +#define TIMER_TRGCTL_TRGDAC_Pos (3) /*!< TIMER_T::TRGCTL: TRGDAC Position */ +#define TIMER_TRGCTL_TRGDAC_Msk (0x1ul << TIMER_TRGCTL_TRGDAC_Pos) /*!< TIMER_T::TRGCTL: TRGDAC Mask */ + +#define TIMER_TRGCTL_TRGPDMA_Pos (4) /*!< TIMER_T::TRGCTL: TRGPDMA Position */ +#define TIMER_TRGCTL_TRGPDMA_Msk (0x1ul << TIMER_TRGCTL_TRGPDMA_Pos) /*!< TIMER_T::TRGCTL: TRGPDMA Mask */ + +#define TIMER_ALTCTL_FUNCSEL_Pos (0) /*!< TIMER_T::ALTCTL: FUNCSEL Position */ +#define TIMER_ALTCTL_FUNCSEL_Msk (0x1ul << TIMER_ALTCTL_FUNCSEL_Pos) /*!< TIMER_T::ALTCTL: FUNCSEL Mask */ + +#define TIMER_PWMCTL_CNTEN_Pos (0) /*!< TIMER_T::PWMCTL: CNTEN Position */ +#define TIMER_PWMCTL_CNTEN_Msk (0x1ul << TIMER_PWMCTL_CNTEN_Pos) /*!< TIMER_T::PWMCTL: CNTEN Mask */ + +#define TIMER_PWMCTL_CNTTYPE_Pos (1) /*!< TIMER_T::PWMCTL: CNTTYPE Position */ +#define TIMER_PWMCTL_CNTTYPE_Msk (0x3ul << TIMER_PWMCTL_CNTTYPE_Pos) /*!< TIMER_T::PWMCTL: CNTTYPE Mask */ + +#define TIMER_PWMCTL_CNTMODE_Pos (3) /*!< TIMER_T::PWMCTL: CNTMODE Position */ +#define TIMER_PWMCTL_CNTMODE_Msk (0x1ul << TIMER_PWMCTL_CNTMODE_Pos) /*!< TIMER_T::PWMCTL: CNTMODE Mask */ + +#define TIMER_PWMCTL_CTRLD_Pos (8) /*!< TIMER_T::PWMCTL: CTRLD Position */ +#define TIMER_PWMCTL_CTRLD_Msk (0x1ul << TIMER_PWMCTL_CTRLD_Pos) /*!< TIMER_T::PWMCTL: CTRLD Mask */ + +#define TIMER_PWMCTL_IMMLDEN_Pos (9) /*!< TIMER_T::PWMCTL: IMMLDEN Position */ +#define TIMER_PWMCTL_IMMLDEN_Msk (0x1ul << TIMER_PWMCTL_IMMLDEN_Pos) /*!< TIMER_T::PWMCTL: IMMLDEN Mask */ + +#define TIMER_PWMCTL_WKEN_Pos (12) /*!< TIMER_T::PWMCTL: WKEN Position */ +#define TIMER_PWMCTL_WKEN_Msk (0x1ul << TIMER_PWMCTL_WKEN_Pos) /*!< TIMER_T::PWMCTL: WKEN Mask */ + +#define TIMER_PWMCTL_OUTMODE_Pos (16) /*!< TIMER_T::PWMCTL: OUTMODE Position */ +#define TIMER_PWMCTL_OUTMODE_Msk (0x1ul << TIMER_PWMCTL_OUTMODE_Pos) /*!< TIMER_T::PWMCTL: OUTMODE Mask */ + +#define TIMER_PWMCTL_DBGHALT_Pos (30) /*!< TIMER_T::PWMCTL: DBGHALT Position */ +#define TIMER_PWMCTL_DBGHALT_Msk (0x1ul << TIMER_PWMCTL_DBGHALT_Pos) /*!< TIMER_T::PWMCTL: DBGHALT Mask */ + +#define TIMER_PWMCTL_DBGTRIOFF_Pos (31) /*!< TIMER_T::PWMCTL: DBGTRIOFF Position */ +#define TIMER_PWMCTL_DBGTRIOFF_Msk (0x1ul << TIMER_PWMCTL_DBGTRIOFF_Pos) /*!< TIMER_T::PWMCTL: DBGTRIOFF Mask */ + +#define TIMER_PWMCLKSRC_CLKSRC_Pos (0) /*!< TIMER_T::PWMCLKSRC: CLKSRC Position */ +#define TIMER_PWMCLKSRC_CLKSRC_Msk (0x7ul << TIMER_PWMCLKSRC_CLKSRC_Pos) /*!< TIMER_T::PWMCLKSRC: CLKSRC Mask */ + +#define TIMER_PWMCLKPSC_CLKPSC_Pos (0) /*!< TIMER_T::PWMCLKPSC: CLKPSC Position */ +#define TIMER_PWMCLKPSC_CLKPSC_Msk (0xffful << TIMER_PWMCLKPSC_CLKPSC_Pos) /*!< TIMER_T::PWMCLKPSC: CLKPSC Mask */ + +#define TIMER_PWMCNTCLR_CNTCLR_Pos (0) /*!< TIMER_T::PWMCNTCLR: CNTCLR Position */ +#define TIMER_PWMCNTCLR_CNTCLR_Msk (0x1ul << TIMER_PWMCNTCLR_CNTCLR_Pos) /*!< TIMER_T::PWMCNTCLR: CNTCLR Mask */ + +#define TIMER_PWMPERIOD_PERIOD_Pos (0) /*!< TIMER_T::PWMPERIOD: PERIOD Position */ +#define TIMER_PWMPERIOD_PERIOD_Msk (0xfffful << TIMER_PWMPERIOD_PERIOD_Pos) /*!< TIMER_T::PWMPERIOD: PERIOD Mask */ + +#define TIMER_PWMCMPDAT_CMP_Pos (0) /*!< TIMER_T::PWMCMPDAT: CMP Position */ +#define TIMER_PWMCMPDAT_CMP_Msk (0xfffful << TIMER_PWMCMPDAT_CMP_Pos) /*!< TIMER_T::PWMCMPDAT: CMP Mask */ + +#define TIMER_PWMDTCTL_DTCNT_Pos (0) /*!< TIMER_T::PWMDTCTL: DTCNT Position */ +#define TIMER_PWMDTCTL_DTCNT_Msk (0xffful << TIMER_PWMDTCTL_DTCNT_Pos) /*!< TIMER_T::PWMDTCTL: DTCNT Mask */ + +#define TIMER_PWMDTCTL_DTEN_Pos (16) /*!< TIMER_T::PWMDTCTL: DTEN Position */ +#define TIMER_PWMDTCTL_DTEN_Msk (0x1ul << TIMER_PWMDTCTL_DTEN_Pos) /*!< TIMER_T::PWMDTCTL: DTEN Mask */ + +#define TIMER_PWMDTCTL_DTCKSEL_Pos (24) /*!< TIMER_T::PWMDTCTL: DTCKSEL Position */ +#define TIMER_PWMDTCTL_DTCKSEL_Msk (0x1ul << TIMER_PWMDTCTL_DTCKSEL_Pos) /*!< TIMER_T::PWMDTCTL: DTCKSEL Mask */ + +#define TIMER_PWMCNT_CNT_Pos (0) /*!< TIMER_T::PWMCNT: CNT Position */ +#define TIMER_PWMCNT_CNT_Msk (0xfffful << TIMER_PWMCNT_CNT_Pos) /*!< TIMER_T::PWMCNT: CNT Mask */ + +#define TIMER_PWMCNT_DIRF_Pos (16) /*!< TIMER_T::PWMCNT: DIRF Position */ +#define TIMER_PWMCNT_DIRF_Msk (0x1ul << TIMER_PWMCNT_DIRF_Pos) /*!< TIMER_T::PWMCNT: DIRF Mask */ + +#define TIMER_PWMMSKEN_MSKEN0_Pos (0) /*!< TIMER_T::PWMMSKEN: MSKEN0 Position */ +#define TIMER_PWMMSKEN_MSKEN0_Msk (0x1ul << TIMER_PWMMSKEN_MSKEN0_Pos) /*!< TIMER_T::PWMMSKEN: MSKEN0 Mask */ + +#define TIMER_PWMMSKEN_MSKEN1_Pos (1) /*!< TIMER_T::PWMMSKEN: MSKEN1 Position */ +#define TIMER_PWMMSKEN_MSKEN1_Msk (0x1ul << TIMER_PWMMSKEN_MSKEN1_Pos) /*!< TIMER_T::PWMMSKEN: MSKEN1 Mask */ + +#define TIMER_PWMMSK_MSKDAT0_Pos (0) /*!< TIMER_T::PWMMSK: MSKDAT0 Position */ +#define TIMER_PWMMSK_MSKDAT0_Msk (0x1ul << TIMER_PWMMSK_MSKDAT0_Pos) /*!< TIMER_T::PWMMSK: MSKDAT0 Mask */ + +#define TIMER_PWMMSK_MSKDAT1_Pos (1) /*!< TIMER_T::PWMMSK: MSKDAT1 Position */ +#define TIMER_PWMMSK_MSKDAT1_Msk (0x1ul << TIMER_PWMMSK_MSKDAT1_Pos) /*!< TIMER_T::PWMMSK: MSKDAT1 Mask */ + +#define TIMER_PWMBNF_BRKNFEN_Pos (0) /*!< TIMER_T::PWMBNF: BRKNFEN Position */ +#define TIMER_PWMBNF_BRKNFEN_Msk (0x1ul << TIMER_PWMBNF_BRKNFEN_Pos) /*!< TIMER_T::PWMBNF: BRKNFEN Mask */ + +#define TIMER_PWMBNF_BRKNFSEL_Pos (1) /*!< TIMER_T::PWMBNF: BRKNFSEL Position */ +#define TIMER_PWMBNF_BRKNFSEL_Msk (0x7ul << TIMER_PWMBNF_BRKNFSEL_Pos) /*!< TIMER_T::PWMBNF: BRKNFSEL Mask */ + +#define TIMER_PWMBNF_BRKFCNT_Pos (4) /*!< TIMER_T::PWMBNF: BRKFCNT Position */ +#define TIMER_PWMBNF_BRKFCNT_Msk (0x7ul << TIMER_PWMBNF_BRKFCNT_Pos) /*!< TIMER_T::PWMBNF: BRKFCNT Mask */ + +#define TIMER_PWMBNF_BRKPINV_Pos (7) /*!< TIMER_T::PWMBNF: BRKPINV Position */ +#define TIMER_PWMBNF_BRKPINV_Msk (0x1ul << TIMER_PWMBNF_BRKPINV_Pos) /*!< TIMER_T::PWMBNF: BRKPINV Mask */ + +#define TIMER_PWMBNF_BKPINSRC_Pos (16) /*!< TIMER_T::PWMBNF: BKPINSRC Position */ +#define TIMER_PWMBNF_BKPINSRC_Msk (0x3ul << TIMER_PWMBNF_BKPINSRC_Pos) /*!< TIMER_T::PWMBNF: BKPINSRC Mask */ + +#define TIMER_PWMFAILBRK_CSSBRKEN_Pos (0) /*!< TIMER_T::PWMFAILBRK: CSSBRKEN Position */ +#define TIMER_PWMFAILBRK_CSSBRKEN_Msk (0x1ul << TIMER_PWMFAILBRK_CSSBRKEN_Pos) /*!< TIMER_T::PWMFAILBRK: CSSBRKEN Mask */ + +#define TIMER_PWMFAILBRK_BODBRKEN_Pos (1) /*!< TIMER_T::PWMFAILBRK: BODBRKEN Position */ +#define TIMER_PWMFAILBRK_BODBRKEN_Msk (0x1ul << TIMER_PWMFAILBRK_BODBRKEN_Pos) /*!< TIMER_T::PWMFAILBRK: BODBRKEN Mask */ + +#define TIMER_PWMFAILBRK_RAMBRKEN_Pos (2) /*!< TIMER_T::PWMFAILBRK: RAMBRKEN Position */ +#define TIMER_PWMFAILBRK_RAMBRKEN_Msk (0x1ul << TIMER_PWMFAILBRK_RAMBRKEN_Pos) /*!< TIMER_T::PWMFAILBRK: RAMBRKEN Mask */ + +#define TIMER_PWMFAILBRK_CORBRKEN_Pos (3) /*!< TIMER_T::PWMFAILBRK: CORBRKEN Position */ +#define TIMER_PWMFAILBRK_CORBRKEN_Msk (0x1ul << TIMER_PWMFAILBRK_CORBRKEN_Pos) /*!< TIMER_T::PWMFAILBRK: CORBRKEN Mask */ + +#define TIMER_PWMBRKCTL_CPO0EBEN_Pos (0) /*!< TIMER_T::PWMBRKCTL: CPO0EBEN Position */ +#define TIMER_PWMBRKCTL_CPO0EBEN_Msk (0x1ul << TIMER_PWMBRKCTL_CPO0EBEN_Pos) /*!< TIMER_T::PWMBRKCTL: CPO0EBEN Mask */ + +#define TIMER_PWMBRKCTL_CPO1EBEN_Pos (1) /*!< TIMER_T::PWMBRKCTL: CPO1EBEN Position */ +#define TIMER_PWMBRKCTL_CPO1EBEN_Msk (0x1ul << TIMER_PWMBRKCTL_CPO1EBEN_Pos) /*!< TIMER_T::PWMBRKCTL: CPO1EBEN Mask */ + +#define TIMER_PWMBRKCTL_BRKPEEN_Pos (4) /*!< TIMER_T::PWMBRKCTL: BRKPEEN Position */ +#define TIMER_PWMBRKCTL_BRKPEEN_Msk (0x1ul << TIMER_PWMBRKCTL_BRKPEEN_Pos) /*!< TIMER_T::PWMBRKCTL: BRKPEEN Mask */ + +#define TIMER_PWMBRKCTL_SYSEBEN_Pos (7) /*!< TIMER_T::PWMBRKCTL: SYSEBEN Position */ +#define TIMER_PWMBRKCTL_SYSEBEN_Msk (0x1ul << TIMER_PWMBRKCTL_SYSEBEN_Pos) /*!< TIMER_T::PWMBRKCTL: SYSEBEN Mask */ + +#define TIMER_PWMBRKCTL_CPO0LBEN_Pos (8) /*!< TIMER_T::PWMBRKCTL: CPO0LBEN Position */ +#define TIMER_PWMBRKCTL_CPO0LBEN_Msk (0x1ul << TIMER_PWMBRKCTL_CPO0LBEN_Pos) /*!< TIMER_T::PWMBRKCTL: CPO0LBEN Mask */ + +#define TIMER_PWMBRKCTL_CPO1LBEN_Pos (9) /*!< TIMER_T::PWMBRKCTL: CPO1LBEN Position */ +#define TIMER_PWMBRKCTL_CPO1LBEN_Msk (0x1ul << TIMER_PWMBRKCTL_CPO1LBEN_Pos) /*!< TIMER_T::PWMBRKCTL: CPO1LBEN Mask */ + +#define TIMER_PWMBRKCTL_BRKPLEN_Pos (12) /*!< TIMER_T::PWMBRKCTL: BRKPLEN Position */ +#define TIMER_PWMBRKCTL_BRKPLEN_Msk (0x1ul << TIMER_PWMBRKCTL_BRKPLEN_Pos) /*!< TIMER_T::PWMBRKCTL: BRKPLEN Mask */ + +#define TIMER_PWMBRKCTL_SYSLBEN_Pos (15) /*!< TIMER_T::PWMBRKCTL: SYSLBEN Position */ +#define TIMER_PWMBRKCTL_SYSLBEN_Msk (0x1ul << TIMER_PWMBRKCTL_SYSLBEN_Pos) /*!< TIMER_T::PWMBRKCTL: SYSLBEN Mask */ + +#define TIMER_PWMBRKCTL_BRKAEVEN_Pos (16) /*!< TIMER_T::PWMBRKCTL: BRKAEVEN Position */ +#define TIMER_PWMBRKCTL_BRKAEVEN_Msk (0x3ul << TIMER_PWMBRKCTL_BRKAEVEN_Pos) /*!< TIMER_T::PWMBRKCTL: BRKAEVEN Mask */ + +#define TIMER_PWMBRKCTL_BRKAODD_Pos (18) /*!< TIMER_T::PWMBRKCTL: BRKAODD Position */ +#define TIMER_PWMBRKCTL_BRKAODD_Msk (0x3ul << TIMER_PWMBRKCTL_BRKAODD_Pos) /*!< TIMER_T::PWMBRKCTL: BRKAODD Mask */ + +#define TIMER_PWMPOLCTL_PINV0_Pos (0) /*!< TIMER_T::PWMPOLCTL: PINV0 Position */ +#define TIMER_PWMPOLCTL_PINV0_Msk (0x1ul << TIMER_PWMPOLCTL_PINV0_Pos) /*!< TIMER_T::PWMPOLCTL: PINV0 Mask */ + +#define TIMER_PWMPOLCTL_PINV1_Pos (1) /*!< TIMER_T::PWMPOLCTL: PINV1 Position */ +#define TIMER_PWMPOLCTL_PINV1_Msk (0x1ul << TIMER_PWMPOLCTL_PINV1_Pos) /*!< TIMER_T::PWMPOLCTL: PINV1 Mask */ + +#define TIMER_PWMPOEN_POEN0_Pos (0) /*!< TIMER_T::PWMPOEN: POEN0 Position */ +#define TIMER_PWMPOEN_POEN0_Msk (0x1ul << TIMER_PWMPOEN_POEN0_Pos) /*!< TIMER_T::PWMPOEN: POEN0 Mask */ + +#define TIMER_PWMPOEN_POEN1_Pos (1) /*!< TIMER_T::PWMPOEN: POEN1 Position */ +#define TIMER_PWMPOEN_POEN1_Msk (0x1ul << TIMER_PWMPOEN_POEN1_Pos) /*!< TIMER_T::PWMPOEN: POEN1 Mask */ + +#define TIMER_PWMPOEN_POSEL_Pos (8) /*!< TIMER_T::PWMPOEN: POSEL Position */ +#define TIMER_PWMPOEN_POSEL_Msk (0x1ul << TIMER_PWMPOEN_POSEL_Pos) /*!< TIMER_T::PWMPOEN: POSEL Mask */ + +#define TIMER_PWMSWBRK_BRKETRG_Pos (0) /*!< TIMER_T::PWMSWBRK: BRKETRG Position */ +#define TIMER_PWMSWBRK_BRKETRG_Msk (0x1ul << TIMER_PWMSWBRK_BRKETRG_Pos) /*!< TIMER_T::PWMSWBRK: BRKETRG Mask */ + +#define TIMER_PWMSWBRK_BRKLTRG_Pos (8) /*!< TIMER_T::PWMSWBRK: BRKLTRG Position */ +#define TIMER_PWMSWBRK_BRKLTRG_Msk (0x1ul << TIMER_PWMSWBRK_BRKLTRG_Pos) /*!< TIMER_T::PWMSWBRK: BRKLTRG Mask */ + +#define TIMER_PWMINTEN0_ZIEN_Pos (0) /*!< TIMER_T::PWMINTEN0: ZIEN Position */ +#define TIMER_PWMINTEN0_ZIEN_Msk (0x1ul << TIMER_PWMINTEN0_ZIEN_Pos) /*!< TIMER_T::PWMINTEN0: ZIEN Mask */ + +#define TIMER_PWMINTEN0_PIEN_Pos (1) /*!< TIMER_T::PWMINTEN0: PIEN Position */ +#define TIMER_PWMINTEN0_PIEN_Msk (0x1ul << TIMER_PWMINTEN0_PIEN_Pos) /*!< TIMER_T::PWMINTEN0: PIEN Mask */ + +#define TIMER_PWMINTEN0_CMPUIEN_Pos (2) /*!< TIMER_T::PWMINTEN0: CMPUIEN Position */ +#define TIMER_PWMINTEN0_CMPUIEN_Msk (0x1ul << TIMER_PWMINTEN0_CMPUIEN_Pos) /*!< TIMER_T::PWMINTEN0: CMPUIEN Mask */ + +#define TIMER_PWMINTEN0_CMPDIEN_Pos (3) /*!< TIMER_T::PWMINTEN0: CMPDIEN Position */ +#define TIMER_PWMINTEN0_CMPDIEN_Msk (0x1ul << TIMER_PWMINTEN0_CMPDIEN_Pos) /*!< TIMER_T::PWMINTEN0: CMPDIEN Mask */ + +#define TIMER_PWMINTEN1_BRKEIEN_Pos (0) /*!< TIMER_T::PWMINTEN1: BRKEIEN Position */ +#define TIMER_PWMINTEN1_BRKEIEN_Msk (0x1ul << TIMER_PWMINTEN1_BRKEIEN_Pos) /*!< TIMER_T::PWMINTEN1: BRKEIEN Mask */ + +#define TIMER_PWMINTEN1_BRKLIEN_Pos (8) /*!< TIMER_T::PWMINTEN1: BRKLIEN Position */ +#define TIMER_PWMINTEN1_BRKLIEN_Msk (0x1ul << TIMER_PWMINTEN1_BRKLIEN_Pos) /*!< TIMER_T::PWMINTEN1: BRKLIEN Mask */ + +#define TIMER_PWMINTSTS0_ZIF_Pos (0) /*!< TIMER_T::PWMINTSTS0: ZIF Position */ +#define TIMER_PWMINTSTS0_ZIF_Msk (0x1ul << TIMER_PWMINTSTS0_ZIF_Pos) /*!< TIMER_T::PWMINTSTS0: ZIF Mask */ + +#define TIMER_PWMINTSTS0_PIF_Pos (1) /*!< TIMER_T::PWMINTSTS0: PIF Position */ +#define TIMER_PWMINTSTS0_PIF_Msk (0x1ul << TIMER_PWMINTSTS0_PIF_Pos) /*!< TIMER_T::PWMINTSTS0: PIF Mask */ + +#define TIMER_PWMINTSTS0_CMPUIF_Pos (2) /*!< TIMER_T::PWMINTSTS0: CMPUIF Position */ +#define TIMER_PWMINTSTS0_CMPUIF_Msk (0x1ul << TIMER_PWMINTSTS0_CMPUIF_Pos) /*!< TIMER_T::PWMINTSTS0: CMPUIF Mask */ + +#define TIMER_PWMINTSTS0_CMPDIF_Pos (3) /*!< TIMER_T::PWMINTSTS0: CMPDIF Position */ +#define TIMER_PWMINTSTS0_CMPDIF_Msk (0x1ul << TIMER_PWMINTSTS0_CMPDIF_Pos) /*!< TIMER_T::PWMINTSTS0: CMPDIF Mask */ + +#define TIMER_PWMINTSTS1_BRKEIF0_Pos (0) /*!< TIMER_T::PWMINTSTS1: BRKEIF0 Position */ +#define TIMER_PWMINTSTS1_BRKEIF0_Msk (0x1ul << TIMER_PWMINTSTS1_BRKEIF0_Pos) /*!< TIMER_T::PWMINTSTS1: BRKEIF0 Mask */ + +#define TIMER_PWMINTSTS1_BRKEIF1_Pos (1) /*!< TIMER_T::PWMINTSTS1: BRKEIF1 Position */ +#define TIMER_PWMINTSTS1_BRKEIF1_Msk (0x1ul << TIMER_PWMINTSTS1_BRKEIF1_Pos) /*!< TIMER_T::PWMINTSTS1: BRKEIF1 Mask */ + +#define TIMER_PWMINTSTS1_BRKLIF0_Pos (8) /*!< TIMER_T::PWMINTSTS1: BRKLIF0 Position */ +#define TIMER_PWMINTSTS1_BRKLIF0_Msk (0x1ul << TIMER_PWMINTSTS1_BRKLIF0_Pos) /*!< TIMER_T::PWMINTSTS1: BRKLIF0 Mask */ + +#define TIMER_PWMINTSTS1_BRKLIF1_Pos (9) /*!< TIMER_T::PWMINTSTS1: BRKLIF1 Position */ +#define TIMER_PWMINTSTS1_BRKLIF1_Msk (0x1ul << TIMER_PWMINTSTS1_BRKLIF1_Pos) /*!< TIMER_T::PWMINTSTS1: BRKLIF1 Mask */ + +#define TIMER_PWMINTSTS1_BRKESTS0_Pos (16) /*!< TIMER_T::PWMINTSTS1: BRKESTS0 Position */ +#define TIMER_PWMINTSTS1_BRKESTS0_Msk (0x1ul << TIMER_PWMINTSTS1_BRKESTS0_Pos) /*!< TIMER_T::PWMINTSTS1: BRKESTS0 Mask */ + +#define TIMER_PWMINTSTS1_BRKESTS1_Pos (17) /*!< TIMER_T::PWMINTSTS1: BRKESTS1 Position */ +#define TIMER_PWMINTSTS1_BRKESTS1_Msk (0x1ul << TIMER_PWMINTSTS1_BRKESTS1_Pos) /*!< TIMER_T::PWMINTSTS1: BRKESTS1 Mask */ + +#define TIMER_PWMINTSTS1_BRKLSTS0_Pos (24) /*!< TIMER_T::PWMINTSTS1: BRKLSTS0 Position */ +#define TIMER_PWMINTSTS1_BRKLSTS0_Msk (0x1ul << TIMER_PWMINTSTS1_BRKLSTS0_Pos) /*!< TIMER_T::PWMINTSTS1: BRKLSTS0 Mask */ + +#define TIMER_PWMINTSTS1_BRKLSTS1_Pos (25) /*!< TIMER_T::PWMINTSTS1: BRKLSTS1 Position */ +#define TIMER_PWMINTSTS1_BRKLSTS1_Msk (0x1ul << TIMER_PWMINTSTS1_BRKLSTS1_Pos) /*!< TIMER_T::PWMINTSTS1: BRKLSTS1 Mask */ + +#define TIMER_PWMTRGCTL_TRGSEL_Pos (0) /*!< TIMER_T::PWMTRGCTL: TRGSEL Position */ +#define TIMER_PWMTRGCTL_TRGSEL_Msk (0x7ul << TIMER_PWMTRGCTL_TRGSEL_Pos) /*!< TIMER_T::PWMTRGCTL: TRGSEL Mask */ + +#define TIMER_PWMTRGCTL_TRGEADC_Pos (7) /*!< TIMER_T::PWMTRGCTL: TRGEADC Position */ +#define TIMER_PWMTRGCTL_TRGEADC_Msk (0x1ul << TIMER_PWMTRGCTL_TRGEADC_Pos) /*!< TIMER_T::PWMTRGCTL: TRGEADC Mask */ + +#define TIMER_PWMTRGCTL_TRGPDMA_Pos (9) /*!< TIMER_T::PWMTRGCTL: TRGPDMA Position */ +#define TIMER_PWMTRGCTL_TRGPDMA_Msk (0x1ul << TIMER_PWMTRGCTL_TRGPDMA_Pos) /*!< TIMER_T::PWMTRGCTL: TRGPDMA Mask */ + +#define TIMER_PWMSCTL_SYNCMODE_Pos (0) /*!< TIMER_T::PWMSCTL: SYNCMODE Position */ +#define TIMER_PWMSCTL_SYNCMODE_Msk (0x3ul << TIMER_PWMSCTL_SYNCMODE_Pos) /*!< TIMER_T::PWMSCTL: SYNCMODE Mask */ + +#define TIMER_PWMSCTL_SYNCSRC_Pos (8) /*!< TIMER_T::PWMSCTL: SYNCSRC Position */ +#define TIMER_PWMSCTL_SYNCSRC_Msk (0x1ul << TIMER_PWMSCTL_SYNCSRC_Pos) /*!< TIMER_T::PWMSCTL: SYNCSRC Mask */ + +#define TIMER_PWMSTRG_STRGEN_Pos (0) /*!< TIMER_T::PWMSTRG: STRGEN Position */ +#define TIMER_PWMSTRG_STRGEN_Msk (0x1ul << TIMER_PWMSTRG_STRGEN_Pos) /*!< TIMER_T::PWMSTRG: STRGEN Mask */ + +#define TIMER_PWMSTATUS_CNTMAXF_Pos (0) /*!< TIMER_T::PWMSTATUS: CNTMAXF Position */ +#define TIMER_PWMSTATUS_CNTMAXF_Msk (0x1ul << TIMER_PWMSTATUS_CNTMAXF_Pos) /*!< TIMER_T::PWMSTATUS: CNTMAXF Mask */ + +#define TIMER_PWMSTATUS_WKF_Pos (8) /*!< TIMER_T::PWMSTATUS: WKF Position */ +#define TIMER_PWMSTATUS_WKF_Msk (0x1ul << TIMER_PWMSTATUS_WKF_Pos) /*!< TIMER_T::PWMSTATUS: WKF Mask */ + +#define TIMER_PWMSTATUS_EADCTRGF_Pos (16) /*!< TIMER_T::PWMSTATUS: EADCTRGF Position */ +#define TIMER_PWMSTATUS_EADCTRGF_Msk (0x1ul << TIMER_PWMSTATUS_EADCTRGF_Pos) /*!< TIMER_T::PWMSTATUS: EADCTRGF Mask */ + +#define TIMER_PWMSTATUS_PDMATRGF_Pos (18) /*!< TIMER_T::PWMSTATUS: PDMATRGF Position */ +#define TIMER_PWMSTATUS_PDMATRGF_Msk (0x1ul << TIMER_PWMSTATUS_PDMATRGF_Pos) /*!< TIMER_T::PWMSTATUS: PDMATRGF Mask */ + +#define TIMER_PWMPBUF_PBUF_Pos (0) /*!< TIMER_T::PWMPBUF: PBUF Position */ +#define TIMER_PWMPBUF_PBUF_Msk (0xfffful << TIMER_PWMPBUF_PBUF_Pos) /*!< TIMER_T::PWMPBUF: PBUF Mask */ + +#define TIMER_PWMCMPBUF_CMPBUF_Pos (0) /*!< TIMER_T::PWMCMPBUF: CMPBUF Position */ +#define TIMER_PWMCMPBUF_CMPBUF_Msk (0xfffful << TIMER_PWMCMPBUF_CMPBUF_Pos) /*!< TIMER_T::PWMCMPBUF: CMPBUF Mask */ + +/**@}*/ /* TIMER_CONST */ +/**@}*/ /* end of TIMER register group */ +/**@}*/ /* end of REGISTER group */ + +#endif /* __TIMER_REG_H__ */ diff --git a/Ubiquitous/XiZi/board/nuvoton-m2354/third_party_driver/include/Regs/trng_reg.h b/Ubiquitous/XiZi/board/nuvoton-m2354/third_party_driver/include/Regs/trng_reg.h new file mode 100644 index 0000000..a10ecfc --- /dev/null +++ b/Ubiquitous/XiZi/board/nuvoton-m2354/third_party_driver/include/Regs/trng_reg.h @@ -0,0 +1,156 @@ +/**************************************************************************//** + * @file trng_reg.h + * @version V1.00 + * @brief TRNG register definition header file + * + * @copyright SPDX-License-Identifier: Apache-2.0 + * @copyright Copyright (C) 2020 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ +#ifndef __TRNG_REG_H__ +#define __TRNG_REG_H__ + +/** @addtogroup REGISTER Control Register + + @{ + +*/ + +/*---------------------- True Random Number Generator -------------------------*/ +/** + @addtogroup TRNG True Random Number Generator(TRNG) + Memory Mapped Structure for TRNG Controller + @{ +*/ + +typedef struct +{ + + + /** + * @var TRNG_T::CTL + * Offset: 0x00 TRNG Control Register and Status + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |TRNGEN |Random Number Generator Enable Bit + * | | |This bit can be set to 1 only after ACT (TRNG_ACT[7]) bit was set to 1 and READY (TRNG_CTL[7]) bit became to 1. + * | | |0 = TRNG Disabled. + * | | |1 = TRNG Enabled. + * | | |Note: TRNGEN is an enable bit of digital part + * | | |When TRNG is not required to generate random number, TRNGEN bit and ACT (TRNG_ACT[7]) bit should be set to 0 to reduce power consumption. + * |[1] |DVIF |Data Valid (Read Only) + * | | |0 = Data is not valid. Reading from RNGD returns 0x00000000. + * | | |1 = Data is valid. A valid random number can be read form RNGD. + * | | |This bit is cleared to u20180u2019 by read TRNG_DATA. + * |[5:2] |CLKPSC |Clock Prescaler + * | | |The CLKP is the peripheral clock frequency range for the selected value , the CLKP must higher than or equal to the actual peripheral clock frequency (for correct random bit generation) + * | | |To change the CLKP contents, first set TRNGEN bit to 0 and then change CLKP; finally, set TRNGEN bit to 1 to re-enable the TRNG module. + * | | |0000 = 80 ~ 100 MHz. + * | | |0001 = 60 ~ 80 MHz. + * | | |0010 = 50 ~60 MHz. + * | | |0011 = 40 ~50 MHz. + * | | |0100 = 30 ~40 MHz. + * | | |0101 = 25 ~30 MHz. + * | | |0110 = 20 ~25 MHz. + * | | |0111 = 15 ~20 MHz. + * | | |1000 = 12 ~15 MHz. + * | | |1001 = 9 ~12 MHz. + * | | |1010 = 7 ~9 MHz. + * | | |1011 = 6 ~7 MHz. + * | | |1100 = 5 ~6 MHz. + * | | |1101 = 4 ~5 MHz. + * | | |1111 = Reserved. + * |[6] |DVIEN |Data Valid Interrupt Enable Bit + * | | |0 = Interrupt Disabled. + * | | |1 = Interrupt Enabled. + * |[7] |READY |Random Number Generator Ready (Read Only) + * | | |After ACT (TRNG_ACT[7]) bit is set, the READY bit become to 1 after a delay of 90us~120us. + * | | |0 = RNG is not ready or was not activated. + * | | |1 = RNG is ready to be enabled.. + * |[8] |SEEDGEN |Random Number Seed Generator Enable Bit [for TRNG+PRNG] + * | | |This bit can be set to 1 only after ACT (TRNG_ACT[7]) bit was set to 1 and READY (TRNG_CTL[7]) bit became to 1. + * | | |0 = Seed generator disabled. + * | | |1 = Seed generator enabled. + * | | |Note: If users want to execute TRNG+PRNG mode, they should set SEEDGEN to 1 + * | | |When SEEDGEN was set to 1, users canu2019t read the data from TRNG Data Register. + * |[9] |SEEDRDY |Random Number Seed Ready (Read Only) [for TRNG+PRNG] + * | | |0 = Seed is not ready or was not activated. + * | | |1 = Seed is ready for PRNG. + * | | |Note 1:This bit is cleared to u20180u2019 when SEEDGEN is 1. + * | | |Note 2: If SEEDRDY become to 1, then SEEDGEN will be cleared to 0. + * |[31:10] |Reversed |Reversed + * @var TRNG_T::DATA + * Offset: 0x04 TRNG Data Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[7:0] |DATA |Random Number Generator Data (Read Only) + * | | |The DATA store the random number generated by TRNG and can be read only once. + * @var TRNG_T::ACT + * Offset: 0x0C TRNG Activation Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[6:0] |VER |TRNG Version + * | | |TRNG version number is dependent on TRNG module. + * | | |0x02:(Current Version Number) + * |[7] |ACT |Random Number Generator Activation + * | | |After enabling the ACT bit, it will active the TRNG module and wait the READY (TRNG_CTL[7]) bit to become 1. + * | | |0 = TRNG inactive. + * | | |1 = TRNG active. + * | | |Note: ACT is an enable bit of analog part + * | | |When TRNG is not required to generate random number, TRNGEN (TRNG_CTL[0]) bit and ACT bit should be set to 0 to reduce power consumption. + */ + __IO uint32_t CTL; /*!< [0x0000] TRNG Control Register and Status */ + __I uint32_t DATA; /*!< [0x0004] TRNG Data Register */ + __I uint32_t RESERVE0[1]; + __IO uint32_t ACT; /*!< [0x000c] TRNG Activation Register */ + +} TRNG_T; + +/** + @addtogroup TRNG_CONST TRNG Bit Field Definition + Constant Definitions for TRNG Controller + @{ +*/ + +#define TRNG_CTL_TRNGEN_Pos (0) /*!< TRNG_T::CTL: TRNGEN Position */ +#define TRNG_CTL_TRNGEN_Msk (0x1ul << TRNG_CTL_TRNGEN_Pos) /*!< TRNG_T::CTL: TRNGEN Mask */ + +#define TRNG_CTL_DVIF_Pos (1) /*!< TRNG_T::CTL: DVIF Position */ +#define TRNG_CTL_DVIF_Msk (0x1ul << TRNG_CTL_DVIF_Pos) /*!< TRNG_T::CTL: DVIF Mask */ + +#define TRNG_CTL_CLKPSC_Pos (2) /*!< TRNG_T::CTL: CLKPSC Position */ +#define TRNG_CTL_CLKPSC_Msk (0xful << TRNG_CTL_CLKPSC_Pos) /*!< TRNG_T::CTL: CLKPSC Mask */ + +#define TRNG_CTL_DVIEN_Pos (6) /*!< TRNG_T::CTL: DVIEN Position */ +#define TRNG_CTL_DVIEN_Msk (0x1ul << TRNG_CTL_DVIEN_Pos) /*!< TRNG_T::CTL: DVIEN Mask */ + +#define TRNG_CTL_READY_Pos (7) /*!< TRNG_T::CTL: READY Position */ +#define TRNG_CTL_READY_Msk (0x1ul << TRNG_CTL_READY_Pos) /*!< TRNG_T::CTL: READY Mask */ + +#define TRNG_CTL_SEEDGEN_Pos (8) /*!< TRNG_T::CTL: SEEDGEN Position */ +#define TRNG_CTL_SEEDGEN_Msk (0x1ul << TRNG_CTL_SEEDGEN_Pos) /*!< TRNG_T::CTL: SEEDGEN Mask */ + +#define TRNG_CTL_SEEDRDY_Pos (9) /*!< TRNG_T::CTL: SEEDRDY Position */ +#define TRNG_CTL_SEEDRDY_Msk (0x1ul << TRNG_CTL_SEEDRDY_Pos) /*!< TRNG_T::CTL: SEEDRDY Mask */ + +#define TRNG_CTL_Reversed_Pos (10) /*!< TRNG_T::CTL: Reversed Position */ +#define TRNG_CTL_Reversed_Msk (0x3ffffful << TRNG_CTL_Reversed_Pos) /*!< TRNG_T::CTL: Reversed Mask */ + +#define TRNG_DATA_DATA_Pos (0) /*!< TRNG_T::DATA: DATA Position */ +#define TRNG_DATA_DATA_Msk (0xfful << TRNG_DATA_DATA_Pos) /*!< TRNG_T::DATA: DATA Mask */ + +#define TRNG_ACT_VER_Pos (0) /*!< TRNG_T::ACT: VER Position */ +#define TRNG_ACT_VER_Msk (0x7ful << TRNG_ACT_VER_Pos) /*!< TRNG_T::ACT: VER Mask */ + +#define TRNG_ACT_ACT_Pos (7) /*!< TRNG_T::ACT: ACT Position */ +#define TRNG_ACT_ACT_Msk (0x1ul << TRNG_ACT_ACT_Pos) /*!< TRNG_T::ACT: ACT Mask */ + +/**@}*/ /* TRNG_CONST */ +/**@}*/ /* end of TRNG register group */ + +/**@}*/ /* end of REGISTER group */ + + +#endif /* __TRNG_REG_H__ */ diff --git a/Ubiquitous/XiZi/board/nuvoton-m2354/third_party_driver/include/Regs/uart_reg.h b/Ubiquitous/XiZi/board/nuvoton-m2354/third_party_driver/include/Regs/uart_reg.h new file mode 100644 index 0000000..0db25a1 --- /dev/null +++ b/Ubiquitous/XiZi/board/nuvoton-m2354/third_party_driver/include/Regs/uart_reg.h @@ -0,0 +1,1284 @@ +/**************************************************************************//** + * @file uart_reg.h + * @version V1.00 + * @brief UART register definition header file + * + * @copyright SPDX-License-Identifier: Apache-2.0 + * @copyright Copyright (C) 2020 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ +#ifndef __UART_REG_H__ +#define __UART_REG_H__ + +/** @addtogroup REGISTER Control Register + + @{ + +*/ + + +/*---------------------- Universal Asynchronous Receiver/Transmitter Controller -------------------------*/ +/** + @addtogroup UART Universal Asynchronous Receiver/Transmitter Controller(UART) + Memory Mapped Structure for UART Controller + @{ +*/ + +typedef struct +{ + + + /** + * @var UART_T::DAT + * Offset: 0x00 UART Receive/Transmit Buffer Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[7:0] |DAT |Data Receive/Transmit Buffer + * | | |Write Operation: + * | | |By writing one byte to this register, the data byte will be stored in transmitter FIFO. + * | | |The UART controller will send out the data stored in transmitter FIFO top location through the UART_TXD. + * | | |Read Operation: + * | | |By reading this register, the UART controller will return an 8-bit data received from receiver FIFO. + * |[8] |PARITY |Parity Bit Receive/Transmit Buffer + * | | |Write Operation: + * | | |By writing to this bit, the parity bit will be stored in transmitter FIFO. + * | | |If PBE (UART_LINE[3]) and PSS (UART_LINE[7]) are set, the UART controller will send out this bit follow the DAT (UART_DAT[7:0]) through the UART_TXD. + * | | |Read Operation: + * | | |If PBE (UART_LINE[3]) and PSS (UART_LINE[7]) are enabled, the parity bit can be read by this bit. + * | | |Note: This bit has effect only when PBE (UART_LINE[3]) and PSS (UART_LINE[7]) are set. + * @var UART_T::INTEN + * Offset: 0x04 UART Interrupt Enable Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |RDAIEN |Receive Data Available Interrupt Enable Bit + * | | |0 = Receive data available interrupt Disabled. + * | | |1 = Receive data available interrupt Enabled. + * |[1] |THREIEN |Transmit Holding Register Empty Interrupt Enable Bit + * | | |0 = Transmit holding register empty interrupt Disabled. + * | | |1 = Transmit holding register empty interrupt Enabled. + * |[2] |RLSIEN |Receive Line Status Interrupt Enable Bit + * | | |0 = Receive Line Status interrupt Disabled. + * | | |1 = Receive Line Status interrupt Enabled. + * |[3] |MODEMIEN |Modem Status Interrupt Enable Bit + * | | |0 = Modem status interrupt Disabled. + * | | |1 = Modem status interrupt Enabled. + * |[4] |RXTOIEN |RX Time-out Interrupt Enable Bit + * | | |0 = RX time-out interrupt Disabled. + * | | |1 = RX time-out interrupt Enabled. + * |[5] |BUFERRIEN |Buffer Error Interrupt Enable Bit + * | | |0 = Buffer error interrupt Disabled. + * | | |1 = Buffer error interrupt Enabled. + * |[6] |WKIEN |Wake-up Interrupt Enable Bit + * | | |0 = Wake-up Interrupt Disabled. + * | | |1 = Wake-up Interrupt Enabled. + * |[8] |LINIEN |LIN Bus Interrupt Enable Bit + * | | |0 = LIN bus interrupt Disabled. + * | | |1 = LIN bus interrupt Enabled. + * | | |Note: This bit is used for LIN function mode. + * |[11] |TOCNTEN |Receive Buffer Time-out Counter Enable Bit + * | | |0 = Receive Buffer Time-out counter Disabled. + * | | |1 = Receive Buffer Time-out counter Enabled. + * |[12] |ATORTSEN |nRTS Auto-flow Control Enable Bit + * | | |0 = nRTS auto-flow control Disabled. + * | | |1 = nRTS auto-flow control Enabled. + * | | |Note: When nRTS auto-flow is enabled, if the number of bytes in the RX FIFO equals the RTSTRGLV (UART_FIFO[19:16]), the UART will de-assert nRTS signal. + * |[13] |ATOCTSEN |nCTS Auto-flow Control Enable Bit + * | | |0 = nCTS auto-flow control Disabled. + * | | |1 = nCTS auto-flow control Enabled. + * | | |Note: When nCTS auto-flow is enabled, the UART will send data to external device if nCTS input assert (UART will not send data to device until nCTS is asserted). + * |[14] |TXPDMAEN |TX PDMA Enable Bit + * | | |This bit can enable or disable TX PDMA service. + * | | |0 = TX PDMA Disabled. + * | | |1 = TX PDMA Enabled. + * |[15] |RXPDMAEN |RX PDMA Enable Bit + * | | |This bit can enable or disable RX PDMA service. + * | | |0 = RX PDMA Disabled. + * | | |1 = RX PDMA Enabled. + * | | |Note: If RLSIEN (UART_INTEN[2]) is enabled and HWRLSINT (UART_INTSTS[26]) is set to 1, the RLS (Receive Line Status) Interrupt is caused. + * | | |If RLS interrupt is caused by Break Error Flag BIF(UART_FIFOSTS[6]), Frame Error Flag FEF(UART_FIFO[5]) or Parity Error Flag PEF(UART_FIFOSTS[4]), UART PDMA receive request operation is stop. + * | | |Clear Break Error Flag BIF or Frame Error Flag FEF or Parity Error Flag PEF by writing 1 to corresponding BIF, FEF and PEF to make UART PDMA receive request operation continue. + * |[16] |SWBEIEN |Single-wire Bit Error Detection Interrupt Enable Bit + * | | |Set this bit, the Single-wire Half Duplex Bit Error Detection Interrupt SWBEINT(UART_INTSTS[24]) is generated when Single-wire Bit Error Detection SWBEIF(UART_INTSTS[16]) is set. + * | | |0 = Single-wire Bit Error Detect Interrupt Disabled. + * | | |1 = Single-wire Bit Error Detect Interrupt Enabled. + * | | |Note: This bit is valid when FUNCSEL (UART_FUNCSEL[2:0]) is select UART Single-wire mode. + * |[18] |ABRIEN |Auto-baud Rate Interrupt Enable Bit + * | | |0 = Auto-baud rate interrupt Disabled. + * | | |1 = Auto-baud rate interrupt Enabled. + * |[22] |TXENDIEN |Transmitter Empty Interrupt Enable Bit + * | | |If TXENDIEN (UART_INTEN[22]) is enabled, the Transmitter Empty interrupt TXENDINT (UART_INTSTS[30]) will be generated when TXENDIF (UART_INTSTS[22]) is set (TX FIFO (UART_DAT) is empty and the STOP bit of the last byte has been transmitted). + * | | |0 = Transmitter empty interrupt Disabled. + * | | |1 = Transmitter empty interrupt Enabled. + * @var UART_T::FIFO + * Offset: 0x08 UART FIFO Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[1] |RXRST |RX Field Software Reset + * | | |When RXRST (UART_FIFO[1]) is set, all the byte in the receiver FIFO and RX internal state machine are cleared. + * | | |0 = No effect. + * | | |1 = Reset the RX internal state machine and pointers. + * | | |Note1: This bit will automatically clear at least 3 UART peripheral clock cycles. + * | | |Note2: Before setting this bit, it should wait for the RXIDLE (UART_FIFOSTS[29]) be set. + * |[2] |TXRST |TX Field Software Reset + * | | |When TXRST (UART_FIFO[2]) is set, all the byte in the transmit FIFO and TX internal state machine are cleared. + * | | |0 = No effect. + * | | |1 = Reset the TX internal state machine and pointers. + * | | |Note1: This bit will automatically clear at least 3 UART peripheral clock cycles. + * | | |Note2: Before setting this bit, it should wait for the TXEMPTYF (UART_FIFOSTS[28]) be set. + * |[7:4] |RFITL |RX FIFO Interrupt Trigger Level + * | | |When the number of bytes in the receive FIFO equals the RFITL, the RDAIF (UART_INTSTS[0]) will be set (if RDAIEN (UART_INTEN [0]) enabled, and an interrupt will be generated). + * | | |0000 = RX FIFO Interrupt Trigger Level is 1 byte. + * | | |0001 = RX FIFO Interrupt Trigger Level is 4 bytes. + * | | |0010 = RX FIFO Interrupt Trigger Level is 8 bytes. + * | | |0011 = RX FIFO Interrupt Trigger Level is 14 bytes. + * | | |Others = Reserved. + * |[8] |RXOFF |Receiver Disable Bit + * | | |The receiver is disabled or not (set 1 to disable receiver). + * | | |0 = Receiver Enabled. + * | | |1 = Receiver Disabled. + * | | |Note: This bit is used for RS-485 Normal Multi-drop mode. + * | | |It should be programmed before RS485NMM (UART_ALTCTL [8]) is programmed. + * |[19:16] |RTSTRGLV |nRTS Trigger Level for Auto-flow Control Use + * | | |0000 = nRTS Trigger Level is 1 byte. + * | | |0001 = nRTS Trigger Level is 4 bytes. + * | | |0010 = nRTS Trigger Level is 8 bytes. + * | | |0011 = nRTS Trigger Level is 14 bytes. + * | | |Others = Reserved. + * | | |Note: This field is used for auto nRTS flow control. + * @var UART_T::LINE + * Offset: 0x0C UART Line Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[1:0] |WLS |Word Length Selection + * | | |This field sets UART word length. + * | | |00 = 5 bits. + * | | |01 = 6 bits. + * | | |10 = 7 bits. + * | | |11 = 8 bits. + * |[2] |NSB |Number of STOP Bit + * | | |0 = One STOP bit is generated in the transmitted data. + * | | |1 = When select 5-bit word length, 1.5 STOP bit is generated in the transmitted data. + * | | |When select 6-, 7- and 8-bit word length, 2 STOP bit is generated in the transmitted data. + * |[3] |PBE |Parity Bit Enable Bit + * | | |0 = Parity bit generated Disabled. + * | | |1 = Parity bit generated Enabled. + * | | |Note: Parity bit is generated on each outgoing character and is checked on each incoming data. + * |[4] |EPE |Even Parity Enable Bit + * | | |0 = Odd number of logic 1's is transmitted and checked in each word. + * | | |1 = Even number of logic 1's is transmitted and checked in each word. + * | | |Note: This bit has effect only when PBE (UART_LINE[3]) is set. + * |[5] |SPE |Stick Parity Enable Bit + * | | |0 = Stick parity Disabled. + * | | |1 = Stick parity Enabled. + * | | |Note: If PBE (UART_LINE[3]) and EPE (UART_LINE[4]) are logic 1, the parity bit is transmitted and checked as logic 0. + * | | |If PBE (UART_LINE[3]) is 1 and EPE (UART_LINE[4]) is 0 then the parity bit is transmitted and checked as 1. + * |[6] |BCB |Break Control Bit + * | | |0 = Break Control Disabled. + * | | |1 = Break Control Enabled. + * | | |Note: When this bit is set to logic 1, the transmitted serial data output (TX) is forced to the Spacing State (logic 0) + * | | |This bit acts only on TX line and has no effect on the transmitter logic. + * |[7] |PSS |Parity Bit Source Selection + * | | |The parity bit can be selected to be generated and checked automatically or by software. + * | | |0 = Parity bit is generated by EPE (UART_LINE[4]) and SPE (UART_LINE[5]) setting and checked automatically. + * | | |1 = Parity bit generated and checked by software. + * | | |Note1: This bit has effect only when PBE (UART_LINE[3]) is set. + * | | |Note2: If PSS is 0, the parity bit is transmitted and checked automatically. + * | | |If PSS is 1, the transmitted parity bit value can be determined by writing PARITY (UART_DAT[8]) and the parity bit can be read by reading PARITY (UART_DAT[8]). + * |[8] |TXDINV |TX Data Inverted + * | | |0 = Transmitted data signal inverted Disabled. + * | | |1 = Transmitted data signal inverted Enabled. + * | | |Note1: Before setting this bit, TXRXDIS (UART_FUNCSEL[3]) should be set then waited for TXRXACT (UART_FIFOSTS[31]) is cleared. + * | | |When the configuration is done, cleared TXRXDIS (UART_FUNCSEL[3]) to activate UART controller. + * | | |Note2: This bit is valid when FUNCSEL (UART_FUNCSEL[1:0]) is select UART, LIN or RS485 function. + * |[9] |RXDINV |RX Data Inverted + * | | |0 = Received data signal inverted Disabled. + * | | |1 = Received data signal inverted Enabled. + * | | |Note1: Before setting this bit, TXRXDIS (UART_FUNCSEL[3]) should be set then waited for TXRXACT (UART_FIFOSTS[31]) is cleared. + * | | |When the configuration is done, cleared TXRXDIS (UART_FUNCSEL[3]) to activate UART controller. + * | | |Note2: This bit is valid when FUNCSEL (UART_FUNCSEL[1:0]) is select UART, LIN or RS485 function. + * @var UART_T::MODEM + * Offset: 0x10 UART Modem Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[1] |RTS |nRTS (Request-to-send) Signal Control + * | | |This bit is direct control internal nRTS signal active or not, and then drive the nRTS pin output with RTSACTLV bit configuration. + * | | |0 = nRTS signal is active. + * | | |1 = nRTS signal is inactive. + * | | |Note1: This nRTS signal control bit is not effective when nRTS auto-flow control is enabled in UART function mode. + * | | |Note2: This nRTS signal control bit is not effective when RS-485 auto direction mode (AUD) is enabled in RS-485 function mode. + * |[9] |RTSACTLV |nRTS Pin Active Level + * | | |This bit defines the active level state of nRTS pin output. + * | | |0 = nRTS pin output is high level active. + * | | |1 = nRTS pin output is low level active. (Default) + * | | |Note: Before setting this bit, TXRXDIS (UART_FUNCSEL[3]) should be set then waited for TXRXACT (UART_FIFOSTS[31]) is cleared. + * | | |When the configuration is done, cleared TXRXDIS (UART_FUNCSEL[3]) to activate UART controller. + * |[13] |RTSSTS |nRTS Pin Status (Read Only) + * | | |This bit mirror from nRTS pin output of voltage logic status. + * | | |0 = nRTS pin output is low level voltage logic state. + * | | |1 = nRTS pin output is high level voltage logic state. + * @var UART_T::MODEMSTS + * Offset: 0x14 UART Modem Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |CTSDETF |Detect nCTS State Change Flag + * | | |This bit is set whenever nCTS input has change state, and it will generate Modem interrupt to CPU when MODEMIEN (UART_INTEN [3]) is set to 1. + * | | |0 = nCTS input has not change state. + * | | |1 = nCTS input has change state. + * | | |Note: This bit can be cleared by writing 1 to it. + * |[4] |CTSSTS |nCTS Pin Status (Read Only) + * | | |This bit mirror from nCTS pin input of voltage logic status. + * | | |0 = nCTS pin input is low level voltage logic state. + * | | |1 = nCTS pin input is high level voltage logic state. + * | | |Note: This bit echoes when UART controller peripheral clock is enabled, and nCTS multi-function port is selected. + * |[8] |CTSACTLV |nCTS Pin Active Level + * | | |This bit defines the active level state of nCTS pin input. + * | | |0 = nCTS pin input is high level active. + * | | |1 = nCTS pin input is low level active. (Default) + * | | |Note: Before setting this bit, TXRXDIS (UART_FUNCSEL[3]) should be set then waited for TXRXACT (UART_FIFOSTS[31]) is cleared. + * | | |When the configuration is done, cleared TXRXDIS (UART_FUNCSEL[3]) to activate UART controller. + * @var UART_T::FIFOSTS + * Offset: 0x18 UART FIFO Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |RXOVIF |RX Overflow Error Interrupt Flag + * | | |This bit is set when RX FIFO overflow. + * | | |If the number of bytes of received data is greater than RX_FIFO (UART_DAT) size 16 bytes, this bit will be set. + * | | |0 = RX FIFO is not overflow. + * | | |1 = RX FIFO is overflow. + * | | |Note: This bit can be cleared by writing 1 to it. + * |[1] |ABRDIF |Auto-baud Rate Detect Interrupt Flag + * | | |This bit is set to logic 1 when auto-baud rate detect function is finished. + * | | |0 = Auto-baud rate detect function is not finished. + * | | |1 = Auto-baud rate detect function is finished. + * | | |Note: This bit can be cleared by writing 1 to it. + * |[2] |ABRDTOIF |Auto-baud Rate Detect Time-out Interrupt Flag + * | | |This bit is set to logic 1 in Auto-baud Rate Detect mode when the baud rate counter is overflow. + * | | |0 = Auto-baud rate counter is underflow. + * | | |1 = Auto-baud rate counter is overflow. + * | | |Note: This bit can be cleared by writing 1 to it. + * |[3] |ADDRDETF |RS-485 Address Byte Detect Flag + * | | |0 = Receiver detects a data that is not an address bit (bit 9 ='0'). + * | | |1 = Receiver detects a data that is an address bit (bit 9 ='1'). + * | | |Note1: This field is used for RS-485 function mode and ADDRDEN (UART_ALTCTL[15]) is set to 1 to enable Address detection mode. + * | | |Note2: This bit can be cleared by writing 1 to it. + * |[4] |PEF |Parity Error Flag + * | | |This bit is set to logic 1 whenever the received character does not have a valid parity bit. + * | | |0 = No parity error is generated. + * | | |1 = Parity error is generated. + * | | |Note: This bit can be cleared by writing 1 to it. + * |[5] |FEF |Framing Error Flag + * | | |This bit is set to logic 1 whenever the received character does not have a valid stop bit (that is, the stop bit following the last data bit or parity bit is detected as logic 0). + * | | |0 = No framing error is generated. + * | | |1 = Framing error is generated. + * | | |Note: This bit can be cleared by writing 1 to it. + * |[6] |BIF |Break Interrupt Flag + * | | |This bit is set to logic 1 whenever the received data input (RX) is held in the spacing state (logic 0) for longer than a full word transmission time (that is, the total time of start bit + data bits + parity + stop bits). + * | | |0 = No Break interrupt is generated. + * | | |1 = Break interrupt is generated. + * | | |Note: This bit can be cleared by writing 1 to it. + * |[13:8] |RXPTR |RX FIFO Pointer (Read Only) + * | | |This field indicates the RX FIFO Buffer Pointer. + * | | |When UART receives one byte from external device, RXPTR increases one. + * | | |When one byte of RX FIFO is read by CPU, RXPTR decreases one. + * | | |The Maximum value shown in RXPTR is 15 + * | | |When the using level of RX FIFO Buffer equal to 16, the RXFULL bit is set to 1 and RXPTR will show 0. + * | | |As one byte of RX FIFO is read by CPU, the RXFULL bit is cleared to 0 and RXPTR will show 15. + * |[14] |RXEMPTY |Receiver FIFO Empty (Read Only) + * | | |This bit initiate RX FIFO empty or not. + * | | |0 = RX FIFO is not empty. + * | | |1 = RX FIFO is empty. + * | | |Note: When the last byte of RX FIFO has been read by CPU, hardware sets this bit high. + * | | |It will be cleared when UART receives any new data. + * |[15] |RXFULL |Receiver FIFO Full (Read Only) + * | | |This bit initiates RX FIFO full or not. + * | | |0 = RX FIFO is not full. + * | | |1 = RX FIFO is full. + * | | |Note: This bit is set when the number of usage in RX FIFO Buffer is equal to 16, otherwise it is cleared by hardware. + * |[21:16] |TXPTR |TX FIFO Pointer (Read Only) + * | | |This field indicates the TX FIFO Buffer Pointer. + * | | |When CPU writes one byte into UART_DAT, TXPTR increases one. + * | | |When one byte of TX FIFO is transferred to Transmitter Shift Register, TXPTR decreases one. + * | | |The Maximum value shown in TXPTR is 15. + * | | |When the using level of TX FIFO Buffer equal to 16, the TXFULL bit is set to 1 and TXPTR will show 0. + * | | |As one byte of TX FIFO is transferred to Transmitter Shift Register, the TXFULL bit is cleared to 0 and TXPTR will show 15. + * |[22] |TXEMPTY |Transmitter FIFO Empty (Read Only) + * | | |This bit indicates TX FIFO empty or not. + * | | |0 = TX FIFO is not empty. + * | | |1 = TX FIFO is empty. + * | | |Note: When the last byte of TX FIFO has been transferred to Transmitter Shift Register, hardware sets this bit high. + * | | |It will be cleared when writing data into UART_DAT (TX FIFO not empty). + * |[23] |TXFULL |Transmitter FIFO Full (Read Only) + * | | |This bit indicates TX FIFO full or not. + * | | |0 = TX FIFO is not full. + * | | |1 = TX FIFO is full. + * | | |Note: This bit is set when the number of usage in TX FIFO Buffer is equal to 16, otherwise it is cleared by hardware. + * |[24] |TXOVIF |TX Overflow Error Interrupt Flag + * | | |If TX FIFO (UART_DAT) is full, an additional write to UART_DAT will cause this bit to logic 1. + * | | |0 = TX FIFO is not overflow. + * | | |1 = TX FIFO is overflow. + * | | |Note: This bit can be cleared by writing 1 to it. + * |[28] |TXEMPTYF |Transmitter Empty Flag (Read Only) + * | | |This bit is set by hardware when TX FIFO (UART_DAT) is empty and the STOP bit of the last byte has been transmitted. + * | | |0 = TX FIFO is not empty or the STOP bit of the last byte has been not transmitted. + * | | |1 = TX FIFO is empty and the STOP bit of the last byte has been transmitted. + * | | |Note: This bit is cleared automatically when TX FIFO is not empty or the last byte transmission has not completed. + * |[29] |RXIDLE |RX Idle Status (Read Only) + * | | |This bit is set by hardware when RX is idle. + * | | |0 = RX is busy. + * | | |1 = RX is idle. (Default) + * |[31] |TXRXACT |TX and RX Active Status (Read Only) + * | | |This bit indicates TX and RX are active or inactive. + * | | |0 = TX and RX are inactive. + * | | |1 = TX and RX are active. (Default) + * | | |Note: When TXRXDIS (UART_FUNCSEL[3]) is set and both TX and RX are in idle state, this bit is cleared. + * | | |The UART controller can not transmit or receive data at this moment. + * | | |Otherwise this bit is set. + * @var UART_T::INTSTS + * Offset: 0x1C UART Interrupt Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |RDAIF |Receive Data Available Interrupt Flag + * | | |When the number of bytes in the RX FIFO equals the RFITL then the RDAIF(UART_INTSTS[0]) will be set. + * | | |If RDAIEN (UART_INTEN [0]) is enabled, the RDA interrupt will be generated. + * | | |0 = No RDA interrupt flag is generated. + * | | |1 = RDA interrupt flag is generated. + * | | |Note: This bit is read only and it will be cleared when the number of unread bytes of RX FIFO drops below the threshold level (RFITL(UART_FIFO[7:4]). + * |[1] |THREIF |Transmit Holding Register Empty Interrupt Flag + * | | |This bit is set when the last data of TX FIFO is transferred to Transmitter Shift Register. + * | | |If THREIEN (UART_INTEN[1]) is enabled, the THRE interrupt will be generated. + * | | |0 = No THRE interrupt flag is generated. + * | | |1 = THRE interrupt flag is generated. + * | | |Note: This bit is read only and it will be cleared when writing data into UART_DAT (TX FIFO not empty). + * |[2] |RLSIF |Receive Line Interrupt Flag (Read Only) + * | | |This bit is set when the RX receive data have parity error, frame error or break error (at least one of 3 bits, BIF(UART_FIFOSTS[6]), FEF(UART_FIFOSTS[5]) and PEF(UART_FIFOSTS[4]), is set). + * | | |If RLSIEN (UART_INTEN [2]) is enabled, the RLS interrupt will be generated. + * | | |0 = No RLS interrupt flag is generated. + * | | |1 = RLS interrupt flag is generated. + * | | |Note1: In RS-485 function mode, this field is set include receiver detect and received address byte character (bit9 = 1) bit. + * | | |At the same time, the bit of ADDRDETF (UART_FIFOSTS[3]) is also set. + * | | |Note2: This bit is read only and reset to 0 when all bits of BIF (UART_FIFOSTS[6]), FEF(UART_FIFOSTS[5]) and PEF(UART_FIFOSTS[4]) are cleared. + * | | |Note3: In RS-485 function mode, this bit is read only and reset to 0 when all bits of BIF (UART_FIFOSTS[6]) , FEF(UART_FIFOSTS[5]), PEF(UART_FIFOSTS[4]) and ADDRDETF (UART_FIFOSTS[3]) are cleared. + * |[3] |MODEMIF |MODEM Interrupt Flag (Read Only) + * | | |This bit is set when the nCTS pin has state change (CTSDETF (UART_MODEMSTS[0]) = 1). + * | | |If MODEMIEN (UART_INTEN [3]) is enabled, the Modem interrupt will be generated. + * | | |0 = No Modem interrupt flag is generated. + * | | |1 = Modem interrupt flag is generated. + * | | |Note: This bit is read only and reset to 0 when bit CTSDETF is cleared by a write 1 on CTSDETF(UART_MODEMSTS[0]). + * |[4] |RXTOIF |RX Time-out Interrupt Flag (Read Only) + * | | |This bit is set when the RX FIFO is not empty and no activities occurred in the RX FIFO and the time-out counter equal to TOIC (UART_TOUT[7:0]). + * | | |If RXTOIEN (UART_INTEN [4]) is enabled, the RX time-out interrupt will be generated. + * | | |0 = No RX time-out interrupt flag is generated. + * | | |1 = RX time-out interrupt flag is generated. + * | | |Note: This bit is read only and user can read UART_DAT (RX is in active) to clear it. + * |[5] |BUFERRIF |Buffer Error Interrupt Flag (Read Only) + * | | |This bit is set when the TX FIFO or RX FIFO overflows (TXOVIF (UART_FIFOSTS[24]) or RXOVIF (UART_FIFOSTS[0]) is set). + * | | |When BUFERRIF (UART_INTSTS[5]) is set, the transfer is not correct. + * | | |If BUFERRIEN (UART_INTEN [5]) is enabled, the buffer error interrupt will be generated. + * | | |0 = No buffer error interrupt flag is generated. + * | | |1 = Buffer error interrupt flag is generated. + * | | |Note: This bit is cleared if both of RXOVIF(UART_FIFOSTS[0]) and TXOVIF(UART_FIFOSTS[24]) are cleared to 0 by writing 1 to RXOVIF(UART_FIFOSTS[0]) and TXOVIF(UART_FIFOSTS[24]). + * |[6] |WKIF |UART Wake-up Interrupt Flag (Read Only) + * | | |This bit is set when TOUTWKF (UART_WKSTS[4]), RS485WKF (UART_WKSTS[3]), RFRTWKF (UART_WKSTS[2]), DATWKF (UART_WKSTS[1]) or CTSWKF(UART_WKSTS[0]) is set to 1. + * | | |0 = No UART wake-up interrupt flag is generated. + * | | |1 = UART wake-up interrupt flag is generated. + * | | |Note: This bit is cleared if all of TOUTWKF, RS485WKF, RFRTWKF, DATWKF and CTSWKF are cleared to 0 by writing 1 to the corresponding interrupt flag. + * |[7] |LINIF |LIN Bus Interrupt Flag + * | | |This bit is set when LIN slave header detect (SLVHDETF (UART_LINSTS[0]=1)), LIN break detect (BRKDETF(UART_LINSTS[8]=1)), bit error detect (BITEF(UART_LINSTS[9]=1)), LIN slave ID parity error (SLVIDPEF(UART_LINSTS[2] = 1)) or LIN slave header error detect (SLVHEF (UART_LINSTS[1])) + * | | |If LINIEN (UART_INTEN [8]) is enabled the LIN interrupt will be generated. + * | | |0 = None of SLVHDETF, BRKDETF, BITEF, SLVIDPEF and SLVHEF is generated. + * | | |1 = At least one of SLVHDETF, BRKDETF, BITEF, SLVIDPEF and SLVHEF is generated. + * | | |Note: This bit is cleared when SLVHDETF(UART_LINSTS[0]), BRKDETF(UART_LINSTS[8]), BITEF(UART_LINSTS[9]), SLVIDPEF (UART_LINSTS[2]) and SLVHEF(UART_LINSTS[1]) all are cleared and software writing 1 to LINIF(UART_INTSTS[7]). + * |[8] |RDAINT |Receive Data Available Interrupt Indicator (Read Only) + * | | |This bit is set if RDAIEN (UART_INTEN[0]) and RDAIF (UART_INTSTS[0]) are both set to 1. + * | | |0 = No RDA interrupt is generated. + * | | |1 = RDA interrupt is generated. + * |[9] |THREINT |Transmit Holding Register Empty Interrupt Indicator (Read Only) + * | | |This bit is set if THREIEN (UART_INTEN[1]) and THREIF(UART_INTSTS[1]) are both set to 1. + * | | |0 = No THRE interrupt is generated. + * | | |1 = THRE interrupt is generated. + * |[10] |RLSINT |Receive Line Status Interrupt Indicator (Read Only) + * | | |This bit is set if RLSIEN (UART_INTEN[2]) and RLSIF(UART_INTSTS[2]) are both set to 1. + * | | |0 = No RLS interrupt is generated. + * | | |1 = RLS interrupt is generated. + * |[11] |MODEMINT |MODEM Status Interrupt Indicator (Read Only) + * | | |This bit is set if MODEMIEN(UART_INTEN[3]) and MODEMIF(UART_INTSTS[3]) are both set to 1 + * | | |0 = No Modem interrupt is generated. + * | | |1 = Modem interrupt is generated.. + * |[12] |RXTOINT |RX Time-out Interrupt Indicator (Read Only) + * | | |This bit is set if RXTOIEN (UART_INTEN[4]) and RXTOIF(UART_INTSTS[4]) are both set to 1. + * | | |0 = No RX time-out interrupt is generated. + * | | |1 = RX time-out interrupt is generated. + * |[13] |BUFERRINT |Buffer Error Interrupt Indicator (Read Only) + * | | |This bit is set if BUFERRIEN(UART_INTEN[5]) and BUFERRIF(UART_ INTSTS[5]) are both set to 1. + * | | |0 = No buffer error interrupt is generated. + * | | |1 = Buffer error interrupt is generated. + * |[14] |WKINT |UART Wake-up Interrupt Indicator (Read Only) + * | | |This bit is set if WKIEN (UART_INTEN[6]) and WKIF (UART_INTSTS[6]) are both set to 1. + * | | |0 = No UART wake-up interrupt is generated. + * | | |1 = UART wake-up interrupt is generated. + * |[15] |LININT |LIN Bus Interrupt Indicator (Read Only) + * | | |This bit is set if LINIEN (UART_INTEN[8]) and LINIF(UART_INTSTS[7]) are both set to 1. + * | | |0 = No LIN Bus interrupt is generated. + * | | |1 = The LIN Bus interrupt is generated. + * |[16] |SWBEIF |Single-wire Bit Error Detection Interrupt Flag + * | | |This bit is set when the single wire bus state not equals to UART controller TX state in Single-wire mode. + * | | |0 = No single-wire bit error detection interrupt flag is generated. + * | | |1 = Single-wire bit error detection interrupt flag is generated. + * | | |Note 1: This bit is active when FUNCSEL (UART_FUNCSEL[2:0]) is select UART Single-wire mode. + * | | |Note 2: This bit can be cleared by writing "1" to it. + * |[18] |HWRLSIF |PDMA Mode Receive Line Status Flag (Read Only) + * | | |This bit is set when the RX receive data have parity error, frame error or break error (at least one of 3 bits, BIF (UART_FIFOSTS[6]), FEF (UART_FIFOSTS[5]) and PEF (UART_FIFOSTS[4]) is set). + * | | |If RLSIEN (UART_INTEN [2]) is enabled, the RLS interrupt will be generated. + * | | |0 = No RLS interrupt flag is generated in PDMA mode. + * | | |1 = RLS interrupt flag is generated in PDMA mode. + * | | |Note1: In RS-485 function mode, this field include receiver detect any address byte received address byte character (bit9 = 1) bit. + * | | |Note2: In UART function mode, this bit is read only and reset to 0 when all bits of BIF(UART_FIFOSTS[6]) , FEF(UART_FIFOSTS[5]) and PEF(UART_FIFOSTS[4]) are cleared. + * | | |Note3: In RS-485 function mode, this bit is read only and reset to 0 when all bits of BIF(UART_FIFOSTS[6]), FEF(UART_FIFOSTS[5]), PEF(UART_FIFOSTS[4]) and ADDRDETF (UART_FIFOSTS[3]) are cleared. + * |[19] |HWMODIF |PDMA Mode MODEM Interrupt Flag (Read Only) + * | | |This bit is set when the nCTS pin has state change (CTSDETF (UART_MODEMSTS[0]=1)). + * | | |If MODEMIEN (UART_INTEN [3]) is enabled, the Modem interrupt will be generated. + * | | |0 = No Modem interrupt flag is generated in PDMA mode. + * | | |1 = Modem interrupt flag is generated in PDMA mode. + * | | |Note: This bit is read only and reset to 0 when the bit CTSDETF (UART_MODEMSTS[0]) is cleared by writing 1 on CTSDETF (UART_MODEMSTS [0]). + * |[20] |HWTOIF |PDMA Mode RX Time-out Interrupt Flag (Read Only) + * | | |This bit is set when the RX FIFO is not empty and no activities occurred in the RX FIFO and the time-out counter equal to TOIC (UART_TOUT[7:0]). + * | | |If RXTOIEN (UART_INTEN [4]) is enabled, the RX time-out interrupt will be generated. + * | | |0 = No RX time-out interrupt flag is generated in PDMA mode. + * | | |1 = RX time-out interrupt flag is generated in PDMA mode. + * | | |Note: This bit is read only and user can read UART_DAT (RX is in active) to clear it. + * |[21] |HWBUFEIF |PDMA Mode Buffer Error Interrupt Flag (Read Only) + * | | |This bit is set when the TX or RX FIFO overflows (TXOVIF (UART_FIFOSTS [24]) or RXOVIF (UART_FIFOSTS[0]) is set). + * | | |When BUFERRIF (UART_INTSTS[5]) is set, the transfer maybe is not correct. + * | | |If BUFERRIEN (UART_INTEN [5]) is enabled, the buffer error interrupt will be generated. + * | | |0 = No buffer error interrupt flag is generated in PDMA mode. + * | | |1 = Buffer error interrupt flag is generated in PDMA mode. + * | | |Note: This bit is cleared when both TXOVIF (UART_FIFOSTS[24]]) and RXOVIF (UART_FIFOSTS[0]) are cleared. + * |[22] |TXENDIF |Transmitter Empty Interrupt Flag + * | | |This bit is set when TX FIFO (UART_DAT) is empty and the STOP bit of the last byte has been transmitted (TXEMPTYF (UART_FIFOSTS[28]) is set). + * | | |If TXENDIEN (UART_INTEN[22]) is enabled, the Transmitter Empty interrupt will be generated. + * | | |0 = No transmitter empty interrupt flag is generated. + * | | |1 = Transmitter empty interrupt flag is generated. + * | | |Note: This bit is cleared automatically when TX FIFO is not empty or the last byte transmission has not completed. + * |[24] |SWBEINT |Single-wire Bit Error Detect Interrupt Indicator (Read Only) + * | | |This bit is set if SWBEIEN (UART_INTEN[16]) and SWBEIF (UART_INTSTS[16]) are both set to 1. + * | | |0 = No Single-wire Bit Error Detection Interrupt generated. + * | | |1 = Single-wire Bit Error Detection Interrupt generated. + * |[26] |HWRLSINT |PDMA Mode Receive Line Status Interrupt Indicator (Read Only) + * | | |This bit is set if RLSIEN (UART_INTEN[2]) and HWRLSIF(UART_INTSTS[18]) are both set to 1. + * | | |0 = No RLS interrupt is generated in PDMA mode. + * | | |1 = RLS interrupt is generated in PDMA mode. + * |[27] |HWMODINT |PDMA Mode MODEM Status Interrupt Indicator (Read Only) + * | | |This bit is set if MODEMIEN (UART_INTEN[3]) and HWMODIF(UART_INTSTS[19]) are both set to 1. + * | | |0 = No Modem interrupt is generated in PDMA mode. + * | | |1 = Modem interrupt is generated in PDMA mode. + * |[28] |HWTOINT |PDMA Mode RX Time-out Interrupt Indicator (Read Only) + * | | |This bit is set if RXTOIEN (UART_INTEN[4]) and HWTOIF(UART_INTSTS[20]) are both set to 1. + * | | |0 = No RX time-out interrupt is generated in PDMA mode. + * | | |1 = RX time-out interrupt is generated in PDMA mode. + * |[29] |HWBUFEINT |PDMA Mode Buffer Error Interrupt Indicator (Read Only) + * | | |This bit is set if BUFERRIEN (UART_INTEN[5]) and HWBUFEIF (UART_INTSTS[21]) are both set to 1. + * | | |0 = No buffer error interrupt is generated in PDMA mode. + * | | |1 = Buffer error interrupt is generated in PDMA mode. + * |[30] |TXENDINT |Transmitter Empty Interrupt Indicator (Read Only) + * | | |This bit is set if TXENDIEN (UART_INTEN[22]) and TXENDIF(UART_INTSTS[22]) are both set to 1. + * | | |0 = No Transmitter Empty interrupt is generated. + * | | |1 = Transmitter Empty interrupt is generated. + * |[31] |ABRINT |Auto-baud Rate Interrupt Indicator (Read Only) + * | | |This bit is set if ABRIEN (UART_INTEN[18]) and ABRIF (UART_ALTCTL[17]) are both set to 1. + * | | |0 = No Auto-baud Rate interrupt is generated. + * | | |1 = The Auto-baud Rate interrupt is generated. + * @var UART_T::TOUT + * Offset: 0x20 UART Time-out Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[7:0] |TOIC |Time-out Interrupt Comparator + * | | |The time-out counter resets and starts counting (the counting clock = baud rate) whenever the RX FIFO receives a new data word if time out counter is enabled by setting TOCNTEN (UART_INTEN[11]). + * | | |Once the content of time-out counter is equal to that of time-out interrupt comparator (TOIC (UART_TOUT[7:0])), a receiver time-out interrupt (RXTOINT(UART_INTSTS[12])) is generated if RXTOIEN (UART_INTEN [4]) enabled. + * | | |A new incoming data word or RX FIFO empty will clear RXTOIF (UART_INTSTS[4]). + * | | |In order to avoid receiver time-out interrupt generation immediately during one character is being received, TOIC value should be set between 40 and 255. + * | | |So, for example, if TOIC is set with 40, the time-out interrupt is generated after four characters are not received when 1 stop bit and no parity check is set for UART transfer. + * |[15:8] |DLY |TX Delay Time Value + * | | |This field is used to programming the transfer delay time between the last stop bit and next start bit. + * | | |The unit is bit time. + * @var UART_T::BAUD + * Offset: 0x24 UART Baud Rate Divider Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |BRD |Baud Rate Divider + * | | |The field indicates the baud rate divider. + * | | |This filed is used in baud rate calculation. + * |[27:24] |EDIVM1 |Extra Divider for BAUD Rate Mode 1 + * | | |This field is used for baud rate calculation in mode 1 and has no effect for baud rate calculation in mode 0 and mode 2. + * |[28] |BAUDM0 |BAUD Rate Mode Selection Bit 0 + * | | |This bit is baud rate mode selection bit 0 + * | | |UART provides three baud rate calculation modes. + * | | |This bit combines with BAUDM1 (UART_BAUD[29]) to select baud rate calculation mode. + * |[29] |BAUDM1 |BAUD Rate Mode Selection Bit 1 + * | | |This bit is baud rate mode selection bit 1. + * | | |UART provides three baud rate calculation modes. + * | | |This bit combines with BAUDM0 (UART_BAUD[28]) to select baud rate calculation mode. + * | | |Note: In IrDA mode must be operated in mode 0. + * @var UART_T::IRDA + * Offset: 0x28 UART IrDA Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[1] |TXEN |IrDA Receiver/Transmitter Selection Enable Bit + * | | |0 = IrDA Transmitter Disabled and Receiver Enabled. (Default) + * | | |1 = IrDA Transmitter Enabled and Receiver Disabled. + * |[5] |TXINV |IrDA Inverse Transmitting Output Signal + * | | |0 = None inverse transmitting signal. (Default). + * | | |1 = Inverse transmitting output signal. + * | | |Note1: Before setting this bit, TXRXDIS (UART_FUNCSEL[3]) should be set then waited for TXRXACT (UART_FIFOSTS[31]) is cleared. + * | | |When the configuration is done, cleared TXRXDIS (UART_FUNCSEL[3]) to activate UART controller. + * | | |Note2: This bit is valid when FUNCSEL (UART_FUNCSEL[1:0]) is select IrDA function. + * |[6] |RXINV |IrDA Inverse Receive Input Signal + * | | |0 = None inverse receiving input signal. + * | | |1 = Inverse receiving input signal. (Default) + * | | |Note1: Before setting this bit, TXRXDIS (UART_FUNCSEL[3]) should be set then waited for TXRXACT (UART_FIFOSTS[31]) is cleared. + * | | |When the configuration is done, cleared TXRXDIS (UART_FUNCSEL[3]) to activate UART controller. + * | | |Note2: This bit is valid when FUNCSEL (UART_FUNCSEL[1:0]) is select IrDA function. + * @var UART_T::ALTCTL + * Offset: 0x2C UART Alternate Control/Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[3:0] |BRKFL |UART LIN Break Field Length + * | | |This field indicates a 4-bit LIN TX break field count. + * | | |Note1: This break field length is BRKFL + 1. + * | | |Note2: According to LIN spec, the reset value is 0xC (break field length = 13). + * |[6] |LINRXEN |LIN RX Enable Bit + * | | |0 = LIN RX mode Disabled. + * | | |1 = LIN RX mode Enabled. + * |[7] |LINTXEN |LIN TX Break Mode Enable Bit + * | | |0 = LIN TX Break mode Disabled. + * | | |1 = LIN TX Break mode Enabled. + * | | |Note: When TX break field transfer operation finished, this bit will be cleared automatically. + * |[8] |RS485NMM |RS-485 Normal Multi-drop Operation Mode (NMM) + * | | |0 = RS-485 Normal Multi-drop Operation mode (NMM) Disabled. + * | | |1 = RS-485 Normal Multi-drop Operation mode (NMM) Enabled. + * | | |Note: It cannot be active with RS-485_AAD operation mode. + * |[9] |RS485AAD |RS-485 Auto Address Detection Operation Mode (AAD) + * | | |0 = RS-485 Auto Address Detection Operation mode (AAD) Disabled. + * | | |1 = RS-485 Auto Address Detection Operation mode (AAD) Enabled. + * | | |Note: It cannot be active with RS-485_NMM operation mode. + * |[10] |RS485AUD |RS-485 Auto Direction Function (AUD) + * | | |0 = RS-485 Auto Direction Operation function (AUD) Disabled. + * | | |1 = RS-485 Auto Direction Operation function (AUD) Enabled. + * | | |Note: It can be active with RS-485_AAD or RS-485_NMM operation mode. + * |[15] |ADDRDEN |RS-485 Address Detection Enable Bit + * | | |This bit is used to enable RS-485 Address Detection mode. + * | | |0 = Address detection mode Disabled. + * | | |1 = Address detection mode Enabled. + * | | |Note: This bit is used for RS-485 any operation mode. + * |[17] |ABRIF |Auto-baud Rate Interrupt Flag (Read Only) + * | | |This bit is set when auto-baud rate detection function finished or the auto-baud rate counter was overflow and if ABRIEN(UART_INTEN [18]) is set then the auto-baud rate interrupt will be generated. + * | | |0 = No auto-baud rate interrupt flag is generated. + * | | |1 = Auto-baud rate interrupt flag is generated. + * | | |Note: This bit is read only, but it can be cleared by writing 1 to ABRDTOIF (UART_FIFOSTS[2]) and ABRDIF(UART_FIFOSTS[1]). + * |[18] |ABRDEN |Auto-baud Rate Detect Enable Bit + * | | |0 = Auto-baud rate detect function Disabled. + * | | |1 = Auto-baud rate detect function Enabled. + * | | |Note : This bit is cleared automatically after auto-baud detection is finished. + * |[20:19] |ABRDBITS |Auto-baud Rate Detect Bit Length + * | | |00 = 1-bit time from Start bit to the 1st rising edge. The input pattern shall be 0x01. + * | | |01 = 2-bit time from Start bit to the 1st rising edge. The input pattern shall be 0x02. + * | | |10 = 4-bit time from Start bit to the 1st rising edge. The input pattern shall be 0x08. + * | | |11 = 8-bit time from Start bit to the 1st rising edge. The input pattern shall be 0x80. + * | | |Note : The calculation of bit number includes the START bit. + * |[31:24] |ADDRMV |Address Match Value + * | | |This field contains the RS-485 address match values. + * | | |Note: This field is used for RS-485 auto address detection mode. + * @var UART_T::FUNCSEL + * Offset: 0x30 UART Function Select Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[2:0] |FUNCSEL |Function Select + * | | |000 = UART function. + * | | |001 = LIN function. + * | | |010 = IrDA function. + * | | |011 = RS-485 function. + * | | |100 = UART Single-wire function. + * | | |Others = Reserved. + * |[3] |TXRXDIS |TX and RX Disable Bit + * | | |Setting this bit can disable TX and RX. + * | | |0 = TX and RX Enabled. + * | | |1 = TX and RX Disabled. + * | | |Note: The TX and RX will not disable immediately when this bit is set. + * | | |The TX and RX complete current task before disable TX and RX. + * | | |When TX and RX disable, the TXRXACT (UART_FIFOSTS[31]) is cleared. + * |[6] |DGE |Deglitch Enable Bit + * | | |0 = Deglitch Disabled. + * | | |1 = Deglitch Enabled. + * | | |Note: When this bit is set to logic 1, any pulse width less than about 300 ns will be considered a glitch and will be removed in the serial data input (RX). + * | | |This bit acts only on RX line and has no effect on the transmitter logic. + * @var UART_T::LINCTL + * Offset: 0x34 UART LIN Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |SLVEN |LIN Slave Mode Enable Bit + * | | |0 = LIN slave mode Disabled. + * | | |1 = LIN slave mode Enabled. + * |[1] |SLVHDEN |LIN Slave Header Detection Enable Bit + * | | |0 = LIN slave header detection Disabled. + * | | |1 = LIN slave header detection Enabled. + * | | |Note1: This bit only valid when in LIN slave mode (SLVEN (UART_LINCTL[0]) = 1). + * | | |Note2: In LIN function mode, when detect header field (break + sync + frame ID), SLVHDETF (UART_LINSTS [0]) flag will be asserted. + * | | |If the LINIEN (UART_INTEN[8]) = 1, an interrupt will be generated. + * |[2] |SLVAREN |LIN Slave Automatic Resynchronization Mode Enable Bit + * | | |0 = LIN automatic resynchronization Disabled. + * | | |1 = LIN automatic resynchronization Enabled. + * | | |Note1: This bit only valid when in LIN slave mode (SLVEN (UART_LINCTL[0]) = 1). + * | | |Note2: When operation in Automatic Resynchronization mode, the baud rate setting must be mode2 (BAUDM1 (UART_BAUD [29]) and BAUDM0 (UART_BAUD [28]) must be 1). + * |[3] |SLVDUEN |LIN Slave Divider Update Method Enable Bit + * | | |0 = UART_BAUD updated is written by software (if no automatic resynchronization update occurs at the same time). + * | | |1 = UART_BAUD is updated at the next received character + * | | |User must set the bit before checksum reception. + * | | |Note1: This bit only valid when in LIN slave mode (SLVEN (UART_LINCTL[0]) = 1). + * | | |Note2: This bit used for LIN Slave Automatic Resynchronization mode. (for Non-Automatic Resynchronization mode, this bit should be kept cleared) + * |[4] |MUTE |LIN Mute Mode Enable Bit + * | | |0 = LIN mute mode Disabled. + * | | |1 = LIN mute mode Enabled. + * | | |Note: The exit from mute mode condition and each control and interactions of this field are explained in 6.16.5.10 (LIN slave mode). + * |[8] |SENDH |LIN TX Send Header Enable Bit + * | | |The LIN TX header can be break field or break and sync field or break, sync and frame ID field, it is depend on setting HSEL (UART_LINCTL[23:22]). + * | | |0 = Send LIN TX header Disabled. + * | | |1 = Send LIN TX header Enabled. + * | | |Note1: This bit is shadow bit of LINTXEN (UART_ALTCTL [7]); user can read/write it by setting LINTXEN (UART_ALTCTL [7]) or SENDH (UART_LINCTL [8]). + * | | |Note2: When transmitter header field (it may be break or break + sync or break + sync + frame ID selected by HSEL (UART_LINCTL[23:22]) field) transfer operation finished, this bit will be cleared automatically. + * |[9] |IDPEN |LIN ID Parity Enable Bit + * | | |0 = LIN frame ID parity Disabled. + * | | |1 = LIN frame ID parity Enabled. + * | | |Note1: This bit can be used for LIN master to sending header field (SENDH (UART_LINCTL[8])) = 1 and HSEL (UART_LINCTL[23:22]) = 10 or be used for enable LIN slave received frame ID parity checked. + * | | |Note2: This bit is only used when the operation header transmitter is in HSEL (UART_LINCTL[23:22]) = 10. + * |[10] |BRKDETEN |LIN Break Detection Enable Bit + * | | |When detect consecutive dominant greater than 11 bits, and are followed by a delimiter character, the BRKDETF (UART_LINSTS[8]) flag is set at the end of break field. + * | | |If the LINIEN (UART_INTEN [8])=1, an interrupt will be generated. + * | | |0 = LIN break detection Disabled . + * | | |1 = LIN break detection Enabled. + * |[11] |LINRXOFF |LIN Receiver Disable Bit + * | | |If the receiver is enabled (RXOFF (UART_LINCTL[11] ) = 0), all received byte data will be accepted and stored in the RX FIFO, and if the receiver is disabled (RXOFF (UART_LINCTL[11] = 1), all received byte data will be ignore. + * | | |0 = LIN receiver Enabled. + * | | |1 = LIN receiver Disabled. + * | | |Note: This bit is only valid when operating in LIN function mode (FUNCSEL (UART_FUNCSEL[1:0]) = 01). + * |[12] |BITERREN |Bit Error Detect Enable Bit + * | | |0 = Bit error detection function Disabled. + * | | |1 = Bit error detection function Enabled. + * | | |Note: In LIN function mode, when occur bit error, the BITEF (UART_LINSTS[9]) flag will be asserted. + * | | |If the LINIEN (UART_INTEN[8]) = 1, an interrupt will be generated. + * |[19:16] |BRKFL |LIN Break Field Length + * | | |This field indicates a 4-bit LIN TX break field count. + * | | |Note1: These registers are shadow registers of BRKFL (UART_ALTCTL[3:0]), User can read/write it by setting BRKFL (UART_ALTCTL[3:0]) or BRKFL (UART_LINCTL[19:16]). + * | | |Note2: This break field length is BRKFL + 1. + * | | |Note3: According to LIN spec, the reset value is 12 (break field length = 13). + * |[21:20] |BSL |LIN Break/Sync Delimiter Length + * | | |00 = The LIN break/sync delimiter length is 1-bit time. + * | | |01 = The LIN break/sync delimiter length is 2-bit time. + * | | |10 = The LIN break/sync delimiter length is 3-bit time. + * | | |11 = The LIN break/sync delimiter length is 4-bit time. + * | | |Note: This bit used for LIN master to sending header field. + * |[23:22] |HSEL |LIN Header Select + * | | |00 = The LIN header includes break field. + * | | |01 = The LIN header includes break field and sync field. + * | | |10 = The LIN header includes break field, sync field and frame ID field. + * | | |11 = Reserved. + * | | |Note: This bit is used to master mode for LIN to send header field (SENDH (UART_LINCTL [8]) = 1) or used to slave to indicates exit from mute mode condition (MUTE (UART_LINCTL[4] = 1). + * |[31:24] |PID |LIN PID Bits + * | | |This field contains the LIN frame ID value when in LIN function mode, the frame ID parity can be generated by software or hardware depends on IDPEN (UART_LINCTL[9]) = 1. + * | | |If the parity generated by hardware, user fill ID0~ID5 (PID [29:24] ), hardware will calculate P0 (PID[30]) and P1 (PID[31]), otherwise user must filled frame ID and parity in this field. + * | | |Note1: User can fill any 8-bit value to this field and the bit 24 indicates ID0 (LSB first). + * | | |Note2: This field can be used for LIN master mode or slave mode. + * @var UART_T::LINSTS + * Offset: 0x38 UART LIN Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |SLVHDETF |LIN Slave Header Detection Flag + * | | |This bit is set by hardware when a LIN header is detected in LIN slave mode and be cleared by writing 1 to it. + * | | |0 = LIN header not detected. + * | | |1 = LIN header detected (break + sync + frame ID). + * | | |Note1: This bit can be cleared by writing 1 to it. + * | | |Note2: This bit is only valid when in LIN slave mode (SLVEN (UART_LINCTL [0]) = 1) and enable LIN slave header detection function (SLVHDEN (UART_LINCTL [1])). + * | | |Note3: When enable ID parity check IDPEN (UART_LINCTL [9]), if hardware detect complete header (break + sync + frame ID), the SLVHDETF will be set whether the frame ID correct or not. + * |[1] |SLVHEF |LIN Slave Header Error Flag + * | | |This bit is set by hardware when a LIN header error is detected in LIN slave mode and be cleared by writing 1 to it + * | | |The header errors include break delimiter is too short (less than 0.5 bit time), frame error in sync field or Identifier field, sync field data is not 0x55 in Non-Automatic Resynchronization mode, sync field deviation error with Automatic Resynchronization mode, sync field measure time-out with Automatic Resynchronization mode and LIN header reception time-out. + * | | |0 = LIN header error not detected. + * | | |1 = LIN header error detected. + * | | |Note1: This bit can be cleared by writing 1 to it. + * | | |Note2: This bit is only valid when UART is operated in LIN slave mode (SLVEN (UART_LINCTL [0]) = 1) and enables LIN slave header detection function (SLVHDEN (UART_LINCTL [1])). + * |[2] |SLVIDPEF |LIN Slave ID Parity Error Flag + * | | |This bit is set by hardware when receipted frame ID parity is not correct. + * | | |0 = No active. + * | | |1 = Receipted frame ID parity is not correct. + * | | |Note1: This bit can be cleared by writing 1 to it. + * | | |Note2: This bit is only valid when in LIN slave mode (SLVEN (UART_LINCTL [0]) = 1) and enable LIN frame ID parity check function IDPEN (UART_LINCTL [9]). + * |[3] |SLVSYNCF |LIN Slave Sync Field + * | | |This bit indicates that the LIN sync field is being analyzed in Automatic Resynchronization mode. + * | | |When the receiver header have some error been detect, user must reset the internal circuit to re-search new frame header by writing 1 to this bit. + * | | |0 = The current character is not at LIN sync state. + * | | |1 = The current character is at LIN sync state. + * | | |Note1: This bit is only valid when in LIN Slave mode (SLVEN(UART_LINCTL[0]) = 1). + * | | |Note2: This bit can be cleared by writing 1 to it. + * | | |Note3: When writing 1 to it, hardware will reload the initial baud rate and re-search a new frame header. + * |[8] |BRKDETF |LIN Break Detection Flag + * | | |This bit is set by hardware when a break is detected and be cleared by writing 1 to it through software. + * | | |0 = LIN break not detected. + * | | |1 = LIN break detected. + * | | |Note1: This bit can be cleared by writing 1 to it. + * | | |Note2: This bit is only valid when LIN break detection function is enabled (BRKDETEN (UART_LINCTL[10]) = 1). + * |[9] |BITEF |Bit Error Detect Status Flag + * | | |At TX transfer state, hardware will monitor the bus state, if the input pin (UART_RXD) state not equals to the output pin (UART_TXD) state, BITEF (UART_LINSTS[9]) will be set. + * | | |When occur bit error, if the LINIEN (UART_INTEN[8]) = 1, an interrupt will be generated. + * | | |0 = Bit error not detected. + * | | |1 = Bit error detected. + * | | |Note1: This bit can be cleared by writing 1 to it. + * | | |Note2: This bit is only valid when enable bit error detection function (BITERREN (UART_LINCTL [12]) = 1). + * @var UART_T::BRCOMP + * Offset: 0x3C UART Baud Rate Compensation Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[8:0] |BRCOMP |Baud Rate Compensation Patten + * | | |These 9-bits are used to define the relative bit is compensated or not. + * | | |BRCOMP[7:0] is used to define the compensation of UART_DAT[7:0] and BRCOMP[8] is used to define the parity bit. + * |[31] |BRCOMPDEC |Baud Rate Compensation Decrease + * | | |0 = Positive (increase one module clock) compensation for each compensated bit. + * | | |1 = Negative (decrease one module clock) compensation for each compensated bit. + * @var UART_T::WKCTL + * Offset: 0x40 UART Wake-up Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |WKCTSEN |nCTS Wake-up Enable Bit + * | | |0 = nCTS Wake-up system function Disabled. + * | | |1 = nCTS Wake-up system function Enabled, when the system is in Power-down mode, an external. + * | | |nCTS change will wake-up system from Power-down mode. + * |[1] |WKDATEN |Incoming Data Wake-up Enable Bit + * | | |0 = Incoming data wake-up system function Disabled. + * | | |1 = Incoming data wake-up system function Enabled, when the system is in Power-down mode,. + * | | |incoming data will wake-up system from Power-down mode. + * |[2] |WKRFRTEN |Received Data FIFO Reached Threshold Wake-up Enable Bit + * | | |0 = Received Data FIFO reached threshold wake-up system function Disabled. + * | | |1 = Received Data FIFO reached threshold wake-up system function Enabled, when the system is. + * | | |in Power-down mode, Received Data FIFO reached threshold will wake-up system from + * | | |Power-down mode. + * |[3] |WKRS485EN |RS-485 Address Match (AAD Mode) Wake-up Enable Bit + * | | |0 = RS-485 Address Match (AAD mode) wake-up system function Disabled. + * | | |1 = RS-485 Address Match (AAD mode) wake-up system function Enabled, when the system is in Power-down mode, RS-485 Address Match will wake-up system from Power-down mode. + * | | |Note: This bit is used for RS-485 Auto Address Detection (AAD) mode in RS-485 function mode and ADDRDEN (UART_ALTCTL[15]) is set to 1. + * |[4] |WKTOUTEN |Received Data FIFO Reached Threshold Time-out Wake-up Enable Bit + * | | |0 = Received Data FIFO reached threshold time-out wake-up system function Disabled. + * | | |1 = Received Data FIFO reached threshold time-out wake-up system function Enabled, when the system is in Power-down mode, Received Data FIFO reached threshold time-out will wake-up system from Power-down mode. + * | | |Note: It is suggest the function is enabled when the WKRFRTEN (UART_WKCTL[2]) is set to 1. + * @var UART_T::WKSTS + * Offset: 0x44 UART Wake-up Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |CTSWKF |nCTS Wake-up Flag + * | | |This bit is set if chip wake-up from power-down state by nCTS wake-up. + * | | |0 = Chip stays in power-down state. + * | | |1 = Chip wake-up from power-down state by nCTS wake-up. + * | | |Note1: If WKCTSEN (UART_WKCTL[0]) is enabled, the nCTS wake-up cause this bit is set to 1. + * | | |Note2: This bit can be cleared by writing 1 to it. + * |[1] |DATWKF |Incoming Data Wake-up Flag + * | | |This bit is set if chip wake-up from power-down state by data wake-up. + * | | |0 = Chip stays in power-down state. + * | | |1 = Chip wake-up from power-down state by Incoming Data wake-up. + * | | |Note1: If WKDATEN (UART_WKCTL[1]) is enabled, the Incoming Data wake-up cause this bit is set to 1. + * | | |Note2: This bit can be cleared by writing 1 to it. + * |[2] |RFRTWKF |Received Data FIFO Reached Threshold Wake-up Flag + * | | |This bit is set if chip wake-up from power-down state by Received Data FIFO reached threshold wake-up. + * | | |0 = Chip stays in power-down state. + * | | |1 = Chip wake-up from power-down state by Received Data FIFO Reached Threshold wake-up. + * | | |Note1: If WKRFRTEN (UART_WKCTL[2]) is enabled, the Received Data FIFO Reached Threshold wake-up cause this bit is set to 1. + * | | |Note2: This bit can be cleared by writing 1 to it. + * |[3] |RS485WKF |RS-485 Address Match (AAD Mode) Wake-up Flag + * | | |This bit is set if chip wake-up from power-down state by RS-485 Address Match (AAD mode). + * | | |0 = Chip stays in power-down state. + * | | |1 = Chip wake-up from power-down state by RS-485 Address Match (AAD mode) wake-up. + * | | |Note1: If WKRS485EN (UART_WKCTL[3]) is enabled, the RS-485 Address Match (AAD mode) wake-up cause this bit is set to 1. + * | | |Note2: This bit can be cleared by writing 1 to it. + * |[4] |TOUTWKF |Received Data FIFO Threshold Time-out Wake-up Flag + * | | |This bit is set if chip wake-up from power-down state by Received Data FIFO Threshold Time-out wake-up. + * | | |0 = Chip stays in power-down state. + * | | |1 = Chip wake-up from power-down state by Received Data FIFO reached threshold time-out wake-up. + * | | |Note1: If WKTOUTEN (UART_WKCTL[4]) is enabled, the Received Data FIFO reached threshold time-out wake-up cause this bit is set to 1. + * | | |Note2: This bit can be cleared by writing 1 to it. + * @var UART_T::DWKCOMP + * Offset: 0x48 UART Incoming Data Wake-up Compensation Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |STCOMP |Start Bit Compensation Value + * | | |These bits field indicate how many clock cycle selected by UART_CLK do the UART controller can get the 1st bit (start bit) when the device is wake-up from power-down mode. + * | | |Note: It is valid only when WKDATEN (UART_WKCTL[1]) is set. + */ + + + __IO uint32_t DAT; /*!< [0x0000] UART Receive/Transmit Buffer Register */ + __IO uint32_t INTEN; /*!< [0x0004] UART Interrupt Enable Register */ + __IO uint32_t FIFO; /*!< [0x0008] UART FIFO Control Register */ + __IO uint32_t LINE; /*!< [0x000c] UART Line Control Register */ + __IO uint32_t MODEM; /*!< [0x0010] UART Modem Control Register */ + __IO uint32_t MODEMSTS; /*!< [0x0014] UART Modem Status Register */ + __IO uint32_t FIFOSTS; /*!< [0x0018] UART FIFO Status Register */ + __IO uint32_t INTSTS; /*!< [0x001c] UART Interrupt Status Register */ + __IO uint32_t TOUT; /*!< [0x0020] UART Time-out Register */ + __IO uint32_t BAUD; /*!< [0x0024] UART Baud Rate Divider Register */ + __IO uint32_t IRDA; /*!< [0x0028] UART IrDA Control Register */ + __IO uint32_t ALTCTL; /*!< [0x002c] UART Alternate Control/Status Register */ + __IO uint32_t FUNCSEL; /*!< [0x0030] UART Function Select Register */ + __IO uint32_t LINCTL; /*!< [0x0034] UART LIN Control Register */ + __IO uint32_t LINSTS; /*!< [0x0038] UART LIN Status Register */ + __IO uint32_t BRCOMP; /*!< [0x003c] UART Baud Rate Compensation Register */ + __IO uint32_t WKCTL; /*!< [0x0040] UART Wake-up Control Register */ + __IO uint32_t WKSTS; /*!< [0x0044] UART Wake-up Status Register */ + __IO uint32_t DWKCOMP; /*!< [0x0048] UART Incoming Data Wake-up Compensation Register */ + + +} UART_T; + +/** + @addtogroup UART_CONST UART Bit Field Definition + Constant Definitions for UART Controller + @{ +*/ + +#define UART_DAT_DAT_Pos (0) /*!< UART_T::DAT: DAT Position */ +#define UART_DAT_DAT_Msk (0xfful << UART_DAT_DAT_Pos) /*!< UART_T::DAT: DAT Mask */ + +#define UART_DAT_PARITY_Pos (8) /*!< UART_T::DAT: PARITY Position */ +#define UART_DAT_PARITY_Msk (0x1ul << UART_DAT_PARITY_Pos) /*!< UART_T::DAT: PARITY Mask */ + +#define UART_INTEN_RDAIEN_Pos (0) /*!< UART_T::INTEN: RDAIEN Position */ +#define UART_INTEN_RDAIEN_Msk (0x1ul << UART_INTEN_RDAIEN_Pos) /*!< UART_T::INTEN: RDAIEN Mask */ + +#define UART_INTEN_THREIEN_Pos (1) /*!< UART_T::INTEN: THREIEN Position */ +#define UART_INTEN_THREIEN_Msk (0x1ul << UART_INTEN_THREIEN_Pos) /*!< UART_T::INTEN: THREIEN Mask */ + +#define UART_INTEN_RLSIEN_Pos (2) /*!< UART_T::INTEN: RLSIEN Position */ +#define UART_INTEN_RLSIEN_Msk (0x1ul << UART_INTEN_RLSIEN_Pos) /*!< UART_T::INTEN: RLSIEN Mask */ + +#define UART_INTEN_MODEMIEN_Pos (3) /*!< UART_T::INTEN: MODEMIEN Position */ +#define UART_INTEN_MODEMIEN_Msk (0x1ul << UART_INTEN_MODEMIEN_Pos) /*!< UART_T::INTEN: MODEMIEN Mask */ + +#define UART_INTEN_RXTOIEN_Pos (4) /*!< UART_T::INTEN: RXTOIEN Position */ +#define UART_INTEN_RXTOIEN_Msk (0x1ul << UART_INTEN_RXTOIEN_Pos) /*!< UART_T::INTEN: RXTOIEN Mask */ + +#define UART_INTEN_BUFERRIEN_Pos (5) /*!< UART_T::INTEN: BUFERRIEN Position */ +#define UART_INTEN_BUFERRIEN_Msk (0x1ul << UART_INTEN_BUFERRIEN_Pos) /*!< UART_T::INTEN: BUFERRIEN Mask */ + +#define UART_INTEN_WKIEN_Pos (6) /*!< UART_T::INTEN: WKIEN Position */ +#define UART_INTEN_WKIEN_Msk (0x1ul << UART_INTEN_WKIEN_Pos) /*!< UART_T::INTEN: WKIEN Mask */ + +#define UART_INTEN_LINIEN_Pos (8) /*!< UART_T::INTEN: LINIEN Position */ +#define UART_INTEN_LINIEN_Msk (0x1ul << UART_INTEN_LINIEN_Pos) /*!< UART_T::INTEN: LINIEN Mask */ + +#define UART_INTEN_TOCNTEN_Pos (11) /*!< UART_T::INTEN: TOCNTEN Position */ +#define UART_INTEN_TOCNTEN_Msk (0x1ul << UART_INTEN_TOCNTEN_Pos) /*!< UART_T::INTEN: TOCNTEN Mask */ + +#define UART_INTEN_ATORTSEN_Pos (12) /*!< UART_T::INTEN: ATORTSEN Position */ +#define UART_INTEN_ATORTSEN_Msk (0x1ul << UART_INTEN_ATORTSEN_Pos) /*!< UART_T::INTEN: ATORTSEN Mask */ + +#define UART_INTEN_ATOCTSEN_Pos (13) /*!< UART_T::INTEN: ATOCTSEN Position */ +#define UART_INTEN_ATOCTSEN_Msk (0x1ul << UART_INTEN_ATOCTSEN_Pos) /*!< UART_T::INTEN: ATOCTSEN Mask */ + +#define UART_INTEN_TXPDMAEN_Pos (14) /*!< UART_T::INTEN: TXPDMAEN Position */ +#define UART_INTEN_TXPDMAEN_Msk (0x1ul << UART_INTEN_TXPDMAEN_Pos) /*!< UART_T::INTEN: TXPDMAEN Mask */ + +#define UART_INTEN_RXPDMAEN_Pos (15) /*!< UART_T::INTEN: RXPDMAEN Position */ +#define UART_INTEN_RXPDMAEN_Msk (0x1ul << UART_INTEN_RXPDMAEN_Pos) /*!< UART_T::INTEN: RXPDMAEN Mask */ + +#define UART_INTEN_SWBEIEN_Pos (16) /*!< UART_T::INTEN: SWBEIEN Position */ +#define UART_INTEN_SWBEIEN_Msk (0x1ul << UART_INTEN_SWBEIEN_Pos) /*!< UART_T::INTEN: SWBEIEN Mask */ + +#define UART_INTEN_ABRIEN_Pos (18) /*!< UART_T::INTEN: ABRIEN Position */ +#define UART_INTEN_ABRIEN_Msk (0x1ul << UART_INTEN_ABRIEN_Pos) /*!< UART_T::INTEN: ABRIEN Mask */ + +#define UART_INTEN_TXENDIEN_Pos (22) /*!< UART_T::INTEN: TXENDIEN Position */ +#define UART_INTEN_TXENDIEN_Msk (0x1ul << UART_INTEN_TXENDIEN_Pos) /*!< UART_T::INTEN: TXENDIEN Mask */ + +#define UART_FIFO_RXRST_Pos (1) /*!< UART_T::FIFO: RXRST Position */ +#define UART_FIFO_RXRST_Msk (0x1ul << UART_FIFO_RXRST_Pos) /*!< UART_T::FIFO: RXRST Mask */ + +#define UART_FIFO_TXRST_Pos (2) /*!< UART_T::FIFO: TXRST Position */ +#define UART_FIFO_TXRST_Msk (0x1ul << UART_FIFO_TXRST_Pos) /*!< UART_T::FIFO: TXRST Mask */ + +#define UART_FIFO_RFITL_Pos (4) /*!< UART_T::FIFO: RFITL Position */ +#define UART_FIFO_RFITL_Msk (0xful << UART_FIFO_RFITL_Pos) /*!< UART_T::FIFO: RFITL Mask */ + +#define UART_FIFO_RXOFF_Pos (8) /*!< UART_T::FIFO: RXOFF Position */ +#define UART_FIFO_RXOFF_Msk (0x1ul << UART_FIFO_RXOFF_Pos) /*!< UART_T::FIFO: RXOFF Mask */ + +#define UART_FIFO_RTSTRGLV_Pos (16) /*!< UART_T::FIFO: RTSTRGLV Position */ +#define UART_FIFO_RTSTRGLV_Msk (0xful << UART_FIFO_RTSTRGLV_Pos) /*!< UART_T::FIFO: RTSTRGLV Mask */ + +#define UART_LINE_WLS_Pos (0) /*!< UART_T::LINE: WLS Position */ +#define UART_LINE_WLS_Msk (0x3ul << UART_LINE_WLS_Pos) /*!< UART_T::LINE: WLS Mask */ + +#define UART_LINE_NSB_Pos (2) /*!< UART_T::LINE: NSB Position */ +#define UART_LINE_NSB_Msk (0x1ul << UART_LINE_NSB_Pos) /*!< UART_T::LINE: NSB Mask */ + +#define UART_LINE_PBE_Pos (3) /*!< UART_T::LINE: PBE Position */ +#define UART_LINE_PBE_Msk (0x1ul << UART_LINE_PBE_Pos) /*!< UART_T::LINE: PBE Mask */ + +#define UART_LINE_EPE_Pos (4) /*!< UART_T::LINE: EPE Position */ +#define UART_LINE_EPE_Msk (0x1ul << UART_LINE_EPE_Pos) /*!< UART_T::LINE: EPE Mask */ + +#define UART_LINE_SPE_Pos (5) /*!< UART_T::LINE: SPE Position */ +#define UART_LINE_SPE_Msk (0x1ul << UART_LINE_SPE_Pos) /*!< UART_T::LINE: SPE Mask */ + +#define UART_LINE_BCB_Pos (6) /*!< UART_T::LINE: BCB Position */ +#define UART_LINE_BCB_Msk (0x1ul << UART_LINE_BCB_Pos) /*!< UART_T::LINE: BCB Mask */ + +#define UART_LINE_PSS_Pos (7) /*!< UART_T::LINE: PSS Position */ +#define UART_LINE_PSS_Msk (0x1ul << UART_LINE_PSS_Pos) /*!< UART_T::LINE: PSS Mask */ + +#define UART_LINE_TXDINV_Pos (8) /*!< UART_T::LINE: TXDINV Position */ +#define UART_LINE_TXDINV_Msk (0x1ul << UART_LINE_TXDINV_Pos) /*!< UART_T::LINE: TXDINV Mask */ + +#define UART_LINE_RXDINV_Pos (9) /*!< UART_T::LINE: RXDINV Position */ +#define UART_LINE_RXDINV_Msk (0x1ul << UART_LINE_RXDINV_Pos) /*!< UART_T::LINE: RXDINV Mask */ + +#define UART_MODEM_RTS_Pos (1) /*!< UART_T::MODEM: RTS Position */ +#define UART_MODEM_RTS_Msk (0x1ul << UART_MODEM_RTS_Pos) /*!< UART_T::MODEM: RTS Mask */ + +#define UART_MODEM_RTSACTLV_Pos (9) /*!< UART_T::MODEM: RTSACTLV Position */ +#define UART_MODEM_RTSACTLV_Msk (0x1ul << UART_MODEM_RTSACTLV_Pos) /*!< UART_T::MODEM: RTSACTLV Mask */ + +#define UART_MODEM_RTSSTS_Pos (13) /*!< UART_T::MODEM: RTSSTS Position */ +#define UART_MODEM_RTSSTS_Msk (0x1ul << UART_MODEM_RTSSTS_Pos) /*!< UART_T::MODEM: RTSSTS Mask */ + +#define UART_MODEMSTS_CTSDETF_Pos (0) /*!< UART_T::MODEMSTS: CTSDETF Position */ +#define UART_MODEMSTS_CTSDETF_Msk (0x1ul << UART_MODEMSTS_CTSDETF_Pos) /*!< UART_T::MODEMSTS: CTSDETF Mask */ + +#define UART_MODEMSTS_CTSSTS_Pos (4) /*!< UART_T::MODEMSTS: CTSSTS Position */ +#define UART_MODEMSTS_CTSSTS_Msk (0x1ul << UART_MODEMSTS_CTSSTS_Pos) /*!< UART_T::MODEMSTS: CTSSTS Mask */ + +#define UART_MODEMSTS_CTSACTLV_Pos (8) /*!< UART_T::MODEMSTS: CTSACTLV Position */ +#define UART_MODEMSTS_CTSACTLV_Msk (0x1ul << UART_MODEMSTS_CTSACTLV_Pos) /*!< UART_T::MODEMSTS: CTSACTLV Mask */ + +#define UART_FIFOSTS_RXOVIF_Pos (0) /*!< UART_T::FIFOSTS: RXOVIF Position */ +#define UART_FIFOSTS_RXOVIF_Msk (0x1ul << UART_FIFOSTS_RXOVIF_Pos) /*!< UART_T::FIFOSTS: RXOVIF Mask */ + +#define UART_FIFOSTS_ABRDIF_Pos (1) /*!< UART_T::FIFOSTS: ABRDIF Position */ +#define UART_FIFOSTS_ABRDIF_Msk (0x1ul << UART_FIFOSTS_ABRDIF_Pos) /*!< UART_T::FIFOSTS: ABRDIF Mask */ + +#define UART_FIFOSTS_ABRDTOIF_Pos (2) /*!< UART_T::FIFOSTS: ABRDTOIF Position */ +#define UART_FIFOSTS_ABRDTOIF_Msk (0x1ul << UART_FIFOSTS_ABRDTOIF_Pos) /*!< UART_T::FIFOSTS: ABRDTOIF Mask */ + +#define UART_FIFOSTS_ADDRDETF_Pos (3) /*!< UART_T::FIFOSTS: ADDRDETF Position */ +#define UART_FIFOSTS_ADDRDETF_Msk (0x1ul << UART_FIFOSTS_ADDRDETF_Pos) /*!< UART_T::FIFOSTS: ADDRDETF Mask */ + +#define UART_FIFOSTS_PEF_Pos (4) /*!< UART_T::FIFOSTS: PEF Position */ +#define UART_FIFOSTS_PEF_Msk (0x1ul << UART_FIFOSTS_PEF_Pos) /*!< UART_T::FIFOSTS: PEF Mask */ + +#define UART_FIFOSTS_FEF_Pos (5) /*!< UART_T::FIFOSTS: FEF Position */ +#define UART_FIFOSTS_FEF_Msk (0x1ul << UART_FIFOSTS_FEF_Pos) /*!< UART_T::FIFOSTS: FEF Mask */ + +#define UART_FIFOSTS_BIF_Pos (6) /*!< UART_T::FIFOSTS: BIF Position */ +#define UART_FIFOSTS_BIF_Msk (0x1ul << UART_FIFOSTS_BIF_Pos) /*!< UART_T::FIFOSTS: BIF Mask */ + +#define UART_FIFOSTS_RXPTR_Pos (8) /*!< UART_T::FIFOSTS: RXPTR Position */ +#define UART_FIFOSTS_RXPTR_Msk (0x3ful << UART_FIFOSTS_RXPTR_Pos) /*!< UART_T::FIFOSTS: RXPTR Mask */ + +#define UART_FIFOSTS_RXEMPTY_Pos (14) /*!< UART_T::FIFOSTS: RXEMPTY Position */ +#define UART_FIFOSTS_RXEMPTY_Msk (0x1ul << UART_FIFOSTS_RXEMPTY_Pos) /*!< UART_T::FIFOSTS: RXEMPTY Mask */ + +#define UART_FIFOSTS_RXFULL_Pos (15) /*!< UART_T::FIFOSTS: RXFULL Position */ +#define UART_FIFOSTS_RXFULL_Msk (0x1ul << UART_FIFOSTS_RXFULL_Pos) /*!< UART_T::FIFOSTS: RXFULL Mask */ + +#define UART_FIFOSTS_TXPTR_Pos (16) /*!< UART_T::FIFOSTS: TXPTR Position */ +#define UART_FIFOSTS_TXPTR_Msk (0x3ful << UART_FIFOSTS_TXPTR_Pos) /*!< UART_T::FIFOSTS: TXPTR Mask */ + +#define UART_FIFOSTS_TXEMPTY_Pos (22) /*!< UART_T::FIFOSTS: TXEMPTY Position */ +#define UART_FIFOSTS_TXEMPTY_Msk (0x1ul << UART_FIFOSTS_TXEMPTY_Pos) /*!< UART_T::FIFOSTS: TXEMPTY Mask */ + +#define UART_FIFOSTS_TXFULL_Pos (23) /*!< UART_T::FIFOSTS: TXFULL Position */ +#define UART_FIFOSTS_TXFULL_Msk (0x1ul << UART_FIFOSTS_TXFULL_Pos) /*!< UART_T::FIFOSTS: TXFULL Mask */ + +#define UART_FIFOSTS_TXOVIF_Pos (24) /*!< UART_T::FIFOSTS: TXOVIF Position */ +#define UART_FIFOSTS_TXOVIF_Msk (0x1ul << UART_FIFOSTS_TXOVIF_Pos) /*!< UART_T::FIFOSTS: TXOVIF Mask */ + +#define UART_FIFOSTS_TXEMPTYF_Pos (28) /*!< UART_T::FIFOSTS: TXEMPTYF Position */ +#define UART_FIFOSTS_TXEMPTYF_Msk (0x1ul << UART_FIFOSTS_TXEMPTYF_Pos) /*!< UART_T::FIFOSTS: TXEMPTYF Mask */ + +#define UART_FIFOSTS_RXIDLE_Pos (29) /*!< UART_T::FIFOSTS: RXIDLE Position */ +#define UART_FIFOSTS_RXIDLE_Msk (0x1ul << UART_FIFOSTS_RXIDLE_Pos) /*!< UART_T::FIFOSTS: RXIDLE Mask */ + +#define UART_FIFOSTS_TXRXACT_Pos (31) /*!< UART_T::FIFOSTS: TXRXACT Position */ +#define UART_FIFOSTS_TXRXACT_Msk (0x1ul << UART_FIFOSTS_TXRXACT_Pos) /*!< UART_T::FIFOSTS: TXRXACT Mask */ + +#define UART_INTSTS_RDAIF_Pos (0) /*!< UART_T::INTSTS: RDAIF Position */ +#define UART_INTSTS_RDAIF_Msk (0x1ul << UART_INTSTS_RDAIF_Pos) /*!< UART_T::INTSTS: RDAIF Mask */ + +#define UART_INTSTS_THREIF_Pos (1) /*!< UART_T::INTSTS: THREIF Position */ +#define UART_INTSTS_THREIF_Msk (0x1ul << UART_INTSTS_THREIF_Pos) /*!< UART_T::INTSTS: THREIF Mask */ + +#define UART_INTSTS_RLSIF_Pos (2) /*!< UART_T::INTSTS: RLSIF Position */ +#define UART_INTSTS_RLSIF_Msk (0x1ul << UART_INTSTS_RLSIF_Pos) /*!< UART_T::INTSTS: RLSIF Mask */ + +#define UART_INTSTS_MODEMIF_Pos (3) /*!< UART_T::INTSTS: MODEMIF Position */ +#define UART_INTSTS_MODEMIF_Msk (0x1ul << UART_INTSTS_MODEMIF_Pos) /*!< UART_T::INTSTS: MODEMIF Mask */ + +#define UART_INTSTS_RXTOIF_Pos (4) /*!< UART_T::INTSTS: RXTOIF Position */ +#define UART_INTSTS_RXTOIF_Msk (0x1ul << UART_INTSTS_RXTOIF_Pos) /*!< UART_T::INTSTS: RXTOIF Mask */ + +#define UART_INTSTS_BUFERRIF_Pos (5) /*!< UART_T::INTSTS: BUFERRIF Position */ +#define UART_INTSTS_BUFERRIF_Msk (0x1ul << UART_INTSTS_BUFERRIF_Pos) /*!< UART_T::INTSTS: BUFERRIF Mask */ + +#define UART_INTSTS_WKIF_Pos (6) /*!< UART_T::INTSTS: WKIF Position */ +#define UART_INTSTS_WKIF_Msk (0x1ul << UART_INTSTS_WKIF_Pos) /*!< UART_T::INTSTS: WKIF Mask */ + +#define UART_INTSTS_LINIF_Pos (7) /*!< UART_T::INTSTS: LINIF Position */ +#define UART_INTSTS_LINIF_Msk (0x1ul << UART_INTSTS_LINIF_Pos) /*!< UART_T::INTSTS: LINIF Mask */ + +#define UART_INTSTS_RDAINT_Pos (8) /*!< UART_T::INTSTS: RDAINT Position */ +#define UART_INTSTS_RDAINT_Msk (0x1ul << UART_INTSTS_RDAINT_Pos) /*!< UART_T::INTSTS: RDAINT Mask */ + +#define UART_INTSTS_THREINT_Pos (9) /*!< UART_T::INTSTS: THREINT Position */ +#define UART_INTSTS_THREINT_Msk (0x1ul << UART_INTSTS_THREINT_Pos) /*!< UART_T::INTSTS: THREINT Mask */ + +#define UART_INTSTS_RLSINT_Pos (10) /*!< UART_T::INTSTS: RLSINT Position */ +#define UART_INTSTS_RLSINT_Msk (0x1ul << UART_INTSTS_RLSINT_Pos) /*!< UART_T::INTSTS: RLSINT Mask */ + +#define UART_INTSTS_MODEMINT_Pos (11) /*!< UART_T::INTSTS: MODEMINT Position */ +#define UART_INTSTS_MODEMINT_Msk (0x1ul << UART_INTSTS_MODEMINT_Pos) /*!< UART_T::INTSTS: MODEMINT Mask */ + +#define UART_INTSTS_RXTOINT_Pos (12) /*!< UART_T::INTSTS: RXTOINT Position */ +#define UART_INTSTS_RXTOINT_Msk (0x1ul << UART_INTSTS_RXTOINT_Pos) /*!< UART_T::INTSTS: RXTOINT Mask */ + +#define UART_INTSTS_BUFERRINT_Pos (13) /*!< UART_T::INTSTS: BUFERRINT Position */ +#define UART_INTSTS_BUFERRINT_Msk (0x1ul << UART_INTSTS_BUFERRINT_Pos) /*!< UART_T::INTSTS: BUFERRINT Mask */ + +#define UART_INTSTS_WKINT_Pos (14) /*!< UART_T::INTSTS: WKINT Position */ +#define UART_INTSTS_WKINT_Msk (0x1ul << UART_INTSTS_WKINT_Pos) /*!< UART_T::INTSTS: WKINT Mask */ + +#define UART_INTSTS_LININT_Pos (15) /*!< UART_T::INTSTS: LININT Position */ +#define UART_INTSTS_LININT_Msk (0x1ul << UART_INTSTS_LININT_Pos) /*!< UART_T::INTSTS: LININT Mask */ + +#define UART_INTSTS_SWBEIF_Pos (16) /*!< UART_T::INTSTS: SWBEIF Position */ +#define UART_INTSTS_SWBEIF_Msk (0x1ul << UART_INTSTS_SWBEIF_Pos) /*!< UART_T::INTSTS: SWBEIF Mask */ + +#define UART_INTSTS_HWRLSIF_Pos (18) /*!< UART_T::INTSTS: HWRLSIF Position */ +#define UART_INTSTS_HWRLSIF_Msk (0x1ul << UART_INTSTS_HWRLSIF_Pos) /*!< UART_T::INTSTS: HWRLSIF Mask */ + +#define UART_INTSTS_HWMODIF_Pos (19) /*!< UART_T::INTSTS: HWMODIF Position */ +#define UART_INTSTS_HWMODIF_Msk (0x1ul << UART_INTSTS_HWMODIF_Pos) /*!< UART_T::INTSTS: HWMODIF Mask */ + +#define UART_INTSTS_HWTOIF_Pos (20) /*!< UART_T::INTSTS: HWTOIF Position */ +#define UART_INTSTS_HWTOIF_Msk (0x1ul << UART_INTSTS_HWTOIF_Pos) /*!< UART_T::INTSTS: HWTOIF Mask */ + +#define UART_INTSTS_HWBUFEIF_Pos (21) /*!< UART_T::INTSTS: HWBUFEIF Position */ +#define UART_INTSTS_HWBUFEIF_Msk (0x1ul << UART_INTSTS_HWBUFEIF_Pos) /*!< UART_T::INTSTS: HWBUFEIF Mask */ + +#define UART_INTSTS_TXENDIF_Pos (22) /*!< UART_T::INTSTS: TXENDIF Position */ +#define UART_INTSTS_TXENDIF_Msk (0x1ul << UART_INTSTS_TXENDIF_Pos) /*!< UART_T::INTSTS: TXENDIF Mask */ + +#define UART_INTSTS_SWBEINT_Pos (24) /*!< UART_T::INTSTS: SWBEINT Position */ +#define UART_INTSTS_SWBEINT_Msk (0x1ul << UART_INTSTS_SWBEINT_Pos) /*!< UART_T::INTSTS: SWBEINT Mask */ + +#define UART_INTSTS_HWRLSINT_Pos (26) /*!< UART_T::INTSTS: HWRLSINT Position */ +#define UART_INTSTS_HWRLSINT_Msk (0x1ul << UART_INTSTS_HWRLSINT_Pos) /*!< UART_T::INTSTS: HWRLSINT Mask */ + +#define UART_INTSTS_HWMODINT_Pos (27) /*!< UART_T::INTSTS: HWMODINT Position */ +#define UART_INTSTS_HWMODINT_Msk (0x1ul << UART_INTSTS_HWMODINT_Pos) /*!< UART_T::INTSTS: HWMODINT Mask */ + +#define UART_INTSTS_HWTOINT_Pos (28) /*!< UART_T::INTSTS: HWTOINT Position */ +#define UART_INTSTS_HWTOINT_Msk (0x1ul << UART_INTSTS_HWTOINT_Pos) /*!< UART_T::INTSTS: HWTOINT Mask */ + +#define UART_INTSTS_HWBUFEINT_Pos (29) /*!< UART_T::INTSTS: HWBUFEINT Position */ +#define UART_INTSTS_HWBUFEINT_Msk (0x1ul << UART_INTSTS_HWBUFEINT_Pos) /*!< UART_T::INTSTS: HWBUFEINT Mask */ + +#define UART_INTSTS_TXENDINT_Pos (30) /*!< UART_T::INTSTS: TXENDINT Position */ +#define UART_INTSTS_TXENDINT_Msk (0x1ul << UART_INTSTS_TXENDINT_Pos) /*!< UART_T::INTSTS: TXENDINT Mask */ + +#define UART_INTSTS_ABRINT_Pos (31) /*!< UART_T::INTSTS: ABRINT Position */ +#define UART_INTSTS_ABRINT_Msk (0x1ul << UART_INTSTS_ABRINT_Pos) /*!< UART_T::INTSTS: ABRINT Mask */ + +#define UART_TOUT_TOIC_Pos (0) /*!< UART_T::TOUT: TOIC Position */ +#define UART_TOUT_TOIC_Msk (0xfful << UART_TOUT_TOIC_Pos) /*!< UART_T::TOUT: TOIC Mask */ + +#define UART_TOUT_DLY_Pos (8) /*!< UART_T::TOUT: DLY Position */ +#define UART_TOUT_DLY_Msk (0xfful << UART_TOUT_DLY_Pos) /*!< UART_T::TOUT: DLY Mask */ + +#define UART_BAUD_BRD_Pos (0) /*!< UART_T::BAUD: BRD Position */ +#define UART_BAUD_BRD_Msk (0xfffful << UART_BAUD_BRD_Pos) /*!< UART_T::BAUD: BRD Mask */ + +#define UART_BAUD_EDIVM1_Pos (24) /*!< UART_T::BAUD: EDIVM1 Position */ +#define UART_BAUD_EDIVM1_Msk (0xful << UART_BAUD_EDIVM1_Pos) /*!< UART_T::BAUD: EDIVM1 Mask */ + +#define UART_BAUD_BAUDM0_Pos (28) /*!< UART_T::BAUD: BAUDM0 Position */ +#define UART_BAUD_BAUDM0_Msk (0x1ul << UART_BAUD_BAUDM0_Pos) /*!< UART_T::BAUD: BAUDM0 Mask */ + +#define UART_BAUD_BAUDM1_Pos (29) /*!< UART_T::BAUD: BAUDM1 Position */ +#define UART_BAUD_BAUDM1_Msk (0x1ul << UART_BAUD_BAUDM1_Pos) /*!< UART_T::BAUD: BAUDM1 Mask */ + +#define UART_IRDA_TXEN_Pos (1) /*!< UART_T::IRDA: TXEN Position */ +#define UART_IRDA_TXEN_Msk (0x1ul << UART_IRDA_TXEN_Pos) /*!< UART_T::IRDA: TXEN Mask */ + +#define UART_IRDA_TXINV_Pos (5) /*!< UART_T::IRDA: TXINV Position */ +#define UART_IRDA_TXINV_Msk (0x1ul << UART_IRDA_TXINV_Pos) /*!< UART_T::IRDA: TXINV Mask */ + +#define UART_IRDA_RXINV_Pos (6) /*!< UART_T::IRDA: RXINV Position */ +#define UART_IRDA_RXINV_Msk (0x1ul << UART_IRDA_RXINV_Pos) /*!< UART_T::IRDA: RXINV Mask */ + +#define UART_ALTCTL_BRKFL_Pos (0) /*!< UART_T::ALTCTL: BRKFL Position */ +#define UART_ALTCTL_BRKFL_Msk (0xful << UART_ALTCTL_BRKFL_Pos) /*!< UART_T::ALTCTL: BRKFL Mask */ + +#define UART_ALTCTL_LINRXEN_Pos (6) /*!< UART_T::ALTCTL: LINRXEN Position */ +#define UART_ALTCTL_LINRXEN_Msk (0x1ul << UART_ALTCTL_LINRXEN_Pos) /*!< UART_T::ALTCTL: LINRXEN Mask */ + +#define UART_ALTCTL_LINTXEN_Pos (7) /*!< UART_T::ALTCTL: LINTXEN Position */ +#define UART_ALTCTL_LINTXEN_Msk (0x1ul << UART_ALTCTL_LINTXEN_Pos) /*!< UART_T::ALTCTL: LINTXEN Mask */ + +#define UART_ALTCTL_RS485NMM_Pos (8) /*!< UART_T::ALTCTL: RS485NMM Position */ +#define UART_ALTCTL_RS485NMM_Msk (0x1ul << UART_ALTCTL_RS485NMM_Pos) /*!< UART_T::ALTCTL: RS485NMM Mask */ + +#define UART_ALTCTL_RS485AAD_Pos (9) /*!< UART_T::ALTCTL: RS485AAD Position */ +#define UART_ALTCTL_RS485AAD_Msk (0x1ul << UART_ALTCTL_RS485AAD_Pos) /*!< UART_T::ALTCTL: RS485AAD Mask */ + +#define UART_ALTCTL_RS485AUD_Pos (10) /*!< UART_T::ALTCTL: RS485AUD Position */ +#define UART_ALTCTL_RS485AUD_Msk (0x1ul << UART_ALTCTL_RS485AUD_Pos) /*!< UART_T::ALTCTL: RS485AUD Mask */ + +#define UART_ALTCTL_ADDRDEN_Pos (15) /*!< UART_T::ALTCTL: ADDRDEN Position */ +#define UART_ALTCTL_ADDRDEN_Msk (0x1ul << UART_ALTCTL_ADDRDEN_Pos) /*!< UART_T::ALTCTL: ADDRDEN Mask */ + +#define UART_ALTCTL_ABRIF_Pos (17) /*!< UART_T::ALTCTL: ABRIF Position */ +#define UART_ALTCTL_ABRIF_Msk (0x1ul << UART_ALTCTL_ABRIF_Pos) /*!< UART_T::ALTCTL: ABRIF Mask */ + +#define UART_ALTCTL_ABRDEN_Pos (18) /*!< UART_T::ALTCTL: ABRDEN Position */ +#define UART_ALTCTL_ABRDEN_Msk (0x1ul << UART_ALTCTL_ABRDEN_Pos) /*!< UART_T::ALTCTL: ABRDEN Mask */ + +#define UART_ALTCTL_ABRDBITS_Pos (19) /*!< UART_T::ALTCTL: ABRDBITS Position */ +#define UART_ALTCTL_ABRDBITS_Msk (0x3ul << UART_ALTCTL_ABRDBITS_Pos) /*!< UART_T::ALTCTL: ABRDBITS Mask */ + +#define UART_ALTCTL_ADDRMV_Pos (24) /*!< UART_T::ALTCTL: ADDRMV Position */ +#define UART_ALTCTL_ADDRMV_Msk (0xfful << UART_ALTCTL_ADDRMV_Pos) /*!< UART_T::ALTCTL: ADDRMV Mask */ + +#define UART_FUNCSEL_FUNCSEL_Pos (0) /*!< UART_T::FUNCSEL: FUNCSEL Position */ +#define UART_FUNCSEL_FUNCSEL_Msk (0x7ul << UART_FUNCSEL_FUNCSEL_Pos) /*!< UART_T::FUNCSEL: FUNCSEL Mask */ + +#define UART_FUNCSEL_TXRXDIS_Pos (3) /*!< UART_T::FUNCSEL: TXRXDIS Position */ +#define UART_FUNCSEL_TXRXDIS_Msk (0x1ul << UART_FUNCSEL_TXRXDIS_Pos) /*!< UART_T::FUNCSEL: TXRXDIS Mask */ + +#define UART_FUNCSEL_DGE_Pos (6) /*!< UART_T::FUNCSEL: DGE Position */ +#define UART_FUNCSEL_DGE_Msk (0x1ul << UART_FUNCSEL_DGE_Pos) /*!< UART_T::FUNCSEL: DGE Mask */ + +#define UART_LINCTL_SLVEN_Pos (0) /*!< UART_T::LINCTL: SLVEN Position */ +#define UART_LINCTL_SLVEN_Msk (0x1ul << UART_LINCTL_SLVEN_Pos) /*!< UART_T::LINCTL: SLVEN Mask */ + +#define UART_LINCTL_SLVHDEN_Pos (1) /*!< UART_T::LINCTL: SLVHDEN Position */ +#define UART_LINCTL_SLVHDEN_Msk (0x1ul << UART_LINCTL_SLVHDEN_Pos) /*!< UART_T::LINCTL: SLVHDEN Mask */ + +#define UART_LINCTL_SLVAREN_Pos (2) /*!< UART_T::LINCTL: SLVAREN Position */ +#define UART_LINCTL_SLVAREN_Msk (0x1ul << UART_LINCTL_SLVAREN_Pos) /*!< UART_T::LINCTL: SLVAREN Mask */ + +#define UART_LINCTL_SLVDUEN_Pos (3) /*!< UART_T::LINCTL: SLVDUEN Position */ +#define UART_LINCTL_SLVDUEN_Msk (0x1ul << UART_LINCTL_SLVDUEN_Pos) /*!< UART_T::LINCTL: SLVDUEN Mask */ + +#define UART_LINCTL_MUTE_Pos (4) /*!< UART_T::LINCTL: MUTE Position */ +#define UART_LINCTL_MUTE_Msk (0x1ul << UART_LINCTL_MUTE_Pos) /*!< UART_T::LINCTL: MUTE Mask */ + +#define UART_LINCTL_SENDH_Pos (8) /*!< UART_T::LINCTL: SENDH Position */ +#define UART_LINCTL_SENDH_Msk (0x1ul << UART_LINCTL_SENDH_Pos) /*!< UART_T::LINCTL: SENDH Mask */ + +#define UART_LINCTL_IDPEN_Pos (9) /*!< UART_T::LINCTL: IDPEN Position */ +#define UART_LINCTL_IDPEN_Msk (0x1ul << UART_LINCTL_IDPEN_Pos) /*!< UART_T::LINCTL: IDPEN Mask */ + +#define UART_LINCTL_BRKDETEN_Pos (10) /*!< UART_T::LINCTL: BRKDETEN Position */ +#define UART_LINCTL_BRKDETEN_Msk (0x1ul << UART_LINCTL_BRKDETEN_Pos) /*!< UART_T::LINCTL: BRKDETEN Mask */ + +#define UART_LINCTL_LINRXOFF_Pos (11) /*!< UART_T::LINCTL: LINRXOFF Position */ +#define UART_LINCTL_LINRXOFF_Msk (0x1ul << UART_LINCTL_LINRXOFF_Pos) /*!< UART_T::LINCTL: LINRXOFF Mask */ + +#define UART_LINCTL_BITERREN_Pos (12) /*!< UART_T::LINCTL: BITERREN Position */ +#define UART_LINCTL_BITERREN_Msk (0x1ul << UART_LINCTL_BITERREN_Pos) /*!< UART_T::LINCTL: BITERREN Mask */ + +#define UART_LINCTL_BRKFL_Pos (16) /*!< UART_T::LINCTL: BRKFL Position */ +#define UART_LINCTL_BRKFL_Msk (0xful << UART_LINCTL_BRKFL_Pos) /*!< UART_T::LINCTL: BRKFL Mask */ + +#define UART_LINCTL_BSL_Pos (20) /*!< UART_T::LINCTL: BSL Position */ +#define UART_LINCTL_BSL_Msk (0x3ul << UART_LINCTL_BSL_Pos) /*!< UART_T::LINCTL: BSL Mask */ + +#define UART_LINCTL_HSEL_Pos (22) /*!< UART_T::LINCTL: HSEL Position */ +#define UART_LINCTL_HSEL_Msk (0x3ul << UART_LINCTL_HSEL_Pos) /*!< UART_T::LINCTL: HSEL Mask */ + +#define UART_LINCTL_PID_Pos (24) /*!< UART_T::LINCTL: PID Position */ +#define UART_LINCTL_PID_Msk (0xfful << UART_LINCTL_PID_Pos) /*!< UART_T::LINCTL: PID Mask */ + +#define UART_LINSTS_SLVHDETF_Pos (0) /*!< UART_T::LINSTS: SLVHDETF Position */ +#define UART_LINSTS_SLVHDETF_Msk (0x1ul << UART_LINSTS_SLVHDETF_Pos) /*!< UART_T::LINSTS: SLVHDETF Mask */ + +#define UART_LINSTS_SLVHEF_Pos (1) /*!< UART_T::LINSTS: SLVHEF Position */ +#define UART_LINSTS_SLVHEF_Msk (0x1ul << UART_LINSTS_SLVHEF_Pos) /*!< UART_T::LINSTS: SLVHEF Mask */ + +#define UART_LINSTS_SLVIDPEF_Pos (2) /*!< UART_T::LINSTS: SLVIDPEF Position */ +#define UART_LINSTS_SLVIDPEF_Msk (0x1ul << UART_LINSTS_SLVIDPEF_Pos) /*!< UART_T::LINSTS: SLVIDPEF Mask */ + +#define UART_LINSTS_SLVSYNCF_Pos (3) /*!< UART_T::LINSTS: SLVSYNCF Position */ +#define UART_LINSTS_SLVSYNCF_Msk (0x1ul << UART_LINSTS_SLVSYNCF_Pos) /*!< UART_T::LINSTS: SLVSYNCF Mask */ + +#define UART_LINSTS_BRKDETF_Pos (8) /*!< UART_T::LINSTS: BRKDETF Position */ +#define UART_LINSTS_BRKDETF_Msk (0x1ul << UART_LINSTS_BRKDETF_Pos) /*!< UART_T::LINSTS: BRKDETF Mask */ + +#define UART_LINSTS_BITEF_Pos (9) /*!< UART_T::LINSTS: BITEF Position */ +#define UART_LINSTS_BITEF_Msk (0x1ul << UART_LINSTS_BITEF_Pos) /*!< UART_T::LINSTS: BITEF Mask */ + +#define UART_BRCOMP_BRCOMP_Pos (0) /*!< UART_T::BRCOMP: BRCOMP Position */ +#define UART_BRCOMP_BRCOMP_Msk (0x1fful << UART_BRCOMP_BRCOMP_Pos) /*!< UART_T::BRCOMP: BRCOMP Mask */ + +#define UART_BRCOMP_BRCOMPDEC_Pos (31) /*!< UART_T::BRCOMP: BRCOMPDEC Position */ +#define UART_BRCOMP_BRCOMPDEC_Msk (0x1ul << UART_BRCOMP_BRCOMPDEC_Pos) /*!< UART_T::BRCOMP: BRCOMPDEC Mask */ + +#define UART_WKCTL_WKCTSEN_Pos (0) /*!< UART_T::WKCTL: WKCTSEN Position */ +#define UART_WKCTL_WKCTSEN_Msk (0x1ul << UART_WKCTL_WKCTSEN_Pos) /*!< UART_T::WKCTL: WKCTSEN Mask */ + +#define UART_WKCTL_WKDATEN_Pos (1) /*!< UART_T::WKCTL: WKDATEN Position */ +#define UART_WKCTL_WKDATEN_Msk (0x1ul << UART_WKCTL_WKDATEN_Pos) /*!< UART_T::WKCTL: WKDATEN Mask */ + +#define UART_WKCTL_WKRFRTEN_Pos (2) /*!< UART_T::WKCTL: WKRFRTEN Position */ +#define UART_WKCTL_WKRFRTEN_Msk (0x1ul << UART_WKCTL_WKRFRTEN_Pos) /*!< UART_T::WKCTL: WKRFRTEN Mask */ + +#define UART_WKCTL_WKRS485EN_Pos (3) /*!< UART_T::WKCTL: WKRS485EN Position */ +#define UART_WKCTL_WKRS485EN_Msk (0x1ul << UART_WKCTL_WKRS485EN_Pos) /*!< UART_T::WKCTL: WKRS485EN Mask */ + +#define UART_WKCTL_WKTOUTEN_Pos (4) /*!< UART_T::WKCTL: WKTOUTEN Position */ +#define UART_WKCTL_WKTOUTEN_Msk (0x1ul << UART_WKCTL_WKTOUTEN_Pos) /*!< UART_T::WKCTL: WKTOUTEN Mask */ + +#define UART_WKSTS_CTSWKF_Pos (0) /*!< UART_T::WKSTS: CTSWKF Position */ +#define UART_WKSTS_CTSWKF_Msk (0x1ul << UART_WKSTS_CTSWKF_Pos) /*!< UART_T::WKSTS: CTSWKF Mask */ + +#define UART_WKSTS_DATWKF_Pos (1) /*!< UART_T::WKSTS: DATWKF Position */ +#define UART_WKSTS_DATWKF_Msk (0x1ul << UART_WKSTS_DATWKF_Pos) /*!< UART_T::WKSTS: DATWKF Mask */ + +#define UART_WKSTS_RFRTWKF_Pos (2) /*!< UART_T::WKSTS: RFRTWKF Position */ +#define UART_WKSTS_RFRTWKF_Msk (0x1ul << UART_WKSTS_RFRTWKF_Pos) /*!< UART_T::WKSTS: RFRTWKF Mask */ + +#define UART_WKSTS_RS485WKF_Pos (3) /*!< UART_T::WKSTS: RS485WKF Position */ +#define UART_WKSTS_RS485WKF_Msk (0x1ul << UART_WKSTS_RS485WKF_Pos) /*!< UART_T::WKSTS: RS485WKF Mask */ + +#define UART_WKSTS_TOUTWKF_Pos (4) /*!< UART_T::WKSTS: TOUTWKF Position */ +#define UART_WKSTS_TOUTWKF_Msk (0x1ul << UART_WKSTS_TOUTWKF_Pos) /*!< UART_T::WKSTS: TOUTWKF Mask */ + +#define UART_DWKCOMP_STCOMP_Pos (0) /*!< UART_T::DWKCOMP: STCOMP Position */ +#define UART_DWKCOMP_STCOMP_Msk (0xfffful << UART_DWKCOMP_STCOMP_Pos) /*!< UART_T::DWKCOMP: STCOMP Mask */ + +/**@}*/ /* UART_CONST */ +/**@}*/ /* end of UART register group */ +/**@}*/ /* end of REGISTER group */ + +#endif /* __UART_REG_H__ */ diff --git a/Ubiquitous/XiZi/board/nuvoton-m2354/third_party_driver/include/Regs/ui2c_reg.h b/Ubiquitous/XiZi/board/nuvoton-m2354/third_party_driver/include/Regs/ui2c_reg.h new file mode 100644 index 0000000..a2728bf --- /dev/null +++ b/Ubiquitous/XiZi/board/nuvoton-m2354/third_party_driver/include/Regs/ui2c_reg.h @@ -0,0 +1,568 @@ +/**************************************************************************//** + * @file ui2c_reg.h + * @version V1.00 + * @brief UI2C register definition header file + * + * @copyright SPDX-License-Identifier: Apache-2.0 + * @copyright Copyright (C) 2020 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ +#ifndef __UI2C_REG_H__ +#define __UI2C_REG_H__ + +/** @addtogroup REGISTER Control Register + + @{ + +*/ + +/*---------------------- I2C Mode of USCI Controller -------------------------*/ +/** + @addtogroup UI2C I2C Mode of USCI Controller(UI2C) + Memory Mapped Structure for UI2C Controller + @{ +*/ + +typedef struct +{ + + + /** + * @var UI2C_T::CTL + * Offset: 0x00 USCI Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[2:0] |FUNMODE |Function Mode + * | | |This bit field selects the protocol for this USCI controller + * | | |Selecting a protocol that is not available or a reserved combination disables the USCI + * | | |When switching between two protocols, the USCI has to be disabled before selecting a new protocol + * | | |Simultaneously, the USCI will be reset when user write 000 to FUNMODE. + * | | |000 = The USCI is disabled. All protocol related state machines are set to idle state. + * | | |001 = The SPI protocol is selected. + * | | |010 = The UART protocol is selected. + * | | |100 = The I2C protocol is selected. + * | | |Note: Other bit combinations are reserved. + * @var UI2C_T::BRGEN + * Offset: 0x08 USCI Baud Rate Generator Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |RCLKSEL |Reference Clock Source Selection + * | | |This bit selects the source signal of reference clock (fREF_CLK). + * | | |0 = Peripheral device clock fPCLK. + * | | |1 = Reserved. + * |[1] |PTCLKSEL |Protocol Clock Source Selection + * | | |This bit selects the source signal of protocol clock (fPROT_CLK). + * | | |0 = Reference clock fREF_CLK. + * | | |1 = fREF_CLK2 (its frequency is half of fREF_CLK). + * |[3:2] |SPCLKSEL |Sample Clock Source Selection + * | | |This bit field used for the clock source selection of a sample clock (fSAMP_CLK) for the protocol processor. + * | | |00 = fSAMP_CLK = fDIV_CLK. + * | | |01 = fSAMP_CLK = fPROT_CLK. + * | | |10 = fSAMP_CLK = fSCLK. + * | | |11 = fSAMP_CLK = fREF_CLK. + * |[4] |TMCNTEN |Time Measurement Counter Enable Bit + * | | |This bit enables the 10-bit timing measurement counter. + * | | |0 = Time measurement counter is Disabled. + * | | |1 = Time measurement counter is Enabled. + * |[5] |TMCNTSRC |Time Measurement Counter Clock Source Selection + * | | |0 = Time measurement counter with fPROT_CLK. + * | | |1 = Time measurement counter with fDIV_CLK. + * |[9:8] |PDSCNT |Pre-divider for Sample Counter + * | | |This bit field defines the divide ratio of the clock division from sample clock fSAMP_CLK + * | | |The divided frequency fPDS_CNT = fSAMP_CLK / (PDSCNT+1). + * |[14:10] |DSCNT |Denominator for Sample Counter + * | | |This bit field defines the divide ratio of the sample clock fSAMP_CLK. + * | | |The divided frequency fDS_CNT = fPDS_CNT / (DSCNT+1). + * | | |Note: The maximum value of DSCNT is 0xF on UART mode and suggest to set over 4 to confirm the receiver data is sampled in right value + * |[25:16] |CLKDIV |Clock Divider + * | | |This bit field defines the ratio between the protocol clock frequency fPROT_CLK and the clock divider frequency fDIV_CLK (fDIV_CLK = fPROT_CLK / (CLKDIV+1) ). + * | | |Note: In UART function, it can be updated by hardware in the 4th falling edge of the input data 0x55 when the auto baud rate function (ABREN(UI2C_PROTCTL[6])) is enabled + * | | |The revised value is the average bit time between bit 5 and bit 6 + * | | |The user can use revised CLKDIV and new BRDETITV (UI2C_PROTCTL[24:16]) to calculate the precise baud rate. + * @var UI2C_T::LINECTL + * Offset: 0x2C USCI Line Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |LSB |LSB First Transmission Selection + * | | |0 = The MSB, which bit of transmit/receive data buffer depends on the setting of DWIDTH, is transmitted/received first. + * | | |1 = The LSB, the bit 0 of data buffer, will be transmitted/received first. + * |[11:8] |DWIDTH |Word Length of Transmission + * | | |This bit field defines the data word length (amount of bits) for reception and transmission + * | | |The data word is always right-aligned in the data buffer + * | | |USCI support word length from 4 to 16 bits. + * | | |0x0: The data word contains 16 bits located at bit positions [15:0]. + * | | |0x1: Reserved. + * | | |0x2: Reserved. + * | | |0x3: Reserved. + * | | |0x4: The data word contains 4 bits located at bit positions [3:0]. + * | | |0x5: The data word contains 5 bits located at bit positions [4:0]. + * | | |... + * | | |0xF: The data word contains 15 bits located at bit positions [14:0]. + * | | |Note: In UART protocol, the length can be configured as 6~13 bits. + * @var UI2C_T::TXDAT + * Offset: 0x30 USCI Transmit Data Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |TXDAT |Transmit Data + * | | |Software can use this bit field to write 16-bit transmit data for transmission. + * @var UI2C_T::RXDAT + * Offset: 0x34 USCI Receive Data Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |RXDAT |Received Data + * | | |This bit field monitors the received data which stored in receive data buffer. + * | | |Note 1: In I2C protocol, RXDAT[12:8] indicate the different transmission conditions which defined in I2C. + * | | |Note 2: In UART protocol, RXDAT[15:13] indicate the same frame status of BREAK, FRMERR and PARITYERR (UI2C_PROTSTS[7:5]). + * @var UI2C_T::DEVADDR0 + * Offset: 0x44 USCI Device Address Register 0 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[9:0] |DEVADDR |Device Address + * | | |In I2C protocol, this bit field contains the programmed slave address + * | | |If the first received address byte are 1111 0AAXB, the AA bits are compared to the bits DEVADDR[9:8] to check for address match, where the X is R/W bit + * | | |Then the second address byte is also compared to DEVADDR[7:0]. + * | | |Note: The DEVADDR [9:7] must be set 3'b000 when I2C operating in 7-bit address mode. + * @var UI2C_T::DEVADDR1 + * Offset: 0x48 USCI Device Address Register 1 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[9:0] |DEVADDR |Device Address + * | | |In I2C protocol, this bit field contains the programmed slave address + * | | |If the first received address byte are 1111 0AAXB, the AA bits are compared to the bits DEVADDR[9:8] to check for address match, where the X is R/W bit + * | | |Then the second address byte is also compared to DEVADDR[7:0]. + * | | |Note: The DEVADDR [9:7] must be set 3'b000 when I2C operating in 7-bit address mode. + * @var UI2C_T::ADDRMSK0 + * Offset: 0x4C USCI Device Address Mask Register 0 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[9:0] |ADDRMSK |USCI Device Address Mask + * | | |0 = Mask Disabled (the received corresponding register bit should be exact the same as address register.). + * | | |1 = Mask Enabled (the received corresponding address bit is don't care.). + * | | |USCI support multiple address recognition with two address mask register + * | | |When the bit in the address mask register is set to one, it means the received corresponding address bit is don't-care + * | | |If the bit is set to zero, that means the received corresponding register bit should be exact the same as address register. + * | | |Note: The wake-up function can not set address mask. + * @var UI2C_T::ADDRMSK1 + * Offset: 0x50 USCI Device Address Mask Register 1 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[9:0] |ADDRMSK |USCI Device Address Mask + * | | |0 = Mask Disabled (the received corresponding register bit should be exact the same as address register.). + * | | |1 = Mask Enabled (the received corresponding address bit is don't care.). + * | | |USCI support multiple address recognition with two address mask register + * | | |When the bit in the address mask register is set to one, it means the received corresponding address bit is don't-care + * | | |If the bit is set to zero, that means the received corresponding register bit should be exact the same as address register. + * | | |Note: The wake-up function can not set address mask. + * @var UI2C_T::WKCTL + * Offset: 0x54 USCI Wake-up Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |WKEN |Wake-up Enable Bit + * | | |0 = Wake-up function Disabled. + * | | |1 = Wake-up function Enabled. + * |[1] |WKADDREN |Wake-up Address Match Enable Bit + * | | |0 = The chip is woken up according data toggle. + * | | |1 = The chip is woken up according address match. + * @var UI2C_T::WKSTS + * Offset: 0x58 USCI Wake-up Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |WKF |Wake-up Flag + * | | |When chip is woken up from Power-down mode, this bit is set to 1 + * | | |Software can write 1 to clear this bit. + * @var UI2C_T::PROTCTL + * Offset: 0x5C USCI Protocol Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |GCFUNC |General Call Function + * | | |0 = General Call Function Disabled. + * | | |1 = General Call Function Enabled. + * |[1] |AA |Assert Acknowledge Control + * | | |When AA =1 prior to address or data received, an acknowledged (low level to SDA) will be returned during the acknowledge clock pulse on the SCL line when 1.) A slave is acknowledging the address sent from master, 2.) The receiver devices are acknowledging the data sent by transmitter + * | | |When AA=0 prior to address or data received, a Not acknowledged (high level to SDA) will be returned during the acknowledge clock pulse on the SCL line. + * |[2] |STO |I2C STOP Control + * | | |In Master mode, setting STO to transmit a STOP condition to bus then I2C hardware will check the bus condition if a STOP condition is detected this bit will be cleared by hardware automatically + * | | |In a slave mode, setting STO resets I2C hardware to the defined not addressed slave mode when bus error (UI2C_PROTSTS.ERRIF = 1). + * |[3] |STA |I2C START Control + * | | |Setting STA to logic 1 to enter Master mode, the I2C hardware sends a START or repeat START condition to bus when the bus is free. + * |[4] |ADDR10EN |Address 10-bit Function Enable Bit + * | | |0 = Address match 10 bit function is disabled. + * | | |1 = Address match 10 bit function is enabled. + * |[5] |PTRG |I2C Protocol Trigger (Write Only) + * | | |When a new state is present in the UI2C_PROTSTS register, if the related interrupt enable bits are set, the I2C interrupt is requested + * | | |It must write one by software to this bit after the related interrupt flags are set to 1 and the I2C protocol function will go ahead until the STOP is active or the PROTEN is disabled. + * | | |0 = I2C's stretch disabled and the I2C protocol function will go ahead. + * | | |1 = I2C's stretch active. + * |[8] |SCLOUTEN |SCL Output Enable Bit + * | | |This bit enables monitor pulling SCL to low + * | | |This monitor will pull SCL to low until it has had time to respond to an I2C interrupt. + * | | |0 = SCL output will be forced high due to open drain mechanism. + * | | |1 = I2C module may act as a slave peripheral just like in normal operation, the I2C holds the clock line low until it has had time to clear I2C interrupt. + * |[9] |MONEN |Monitor Mode Enable Bit + * | | |This bit enables monitor mode + * | | |In monitor mode the SDA output will be put in high impedance mode + * | | |This prevents the I2C module from outputting data of any kind (including ACK) onto the I2C data bus. + * | | |0 = The monitor mode is disabled. + * | | |1 = The monitor mode is enabled. + * | | |Note: Depending on the state of the SCLOUTEN bit, the SCL output may be also forced high, preventing the module from having control over the I2C clock line. + * |[25:16] |TOCNT |Time-out Clock Cycle + * | | |This bit field indicates how many clock cycle selected by TMCNTSRC (UI2C_BRGEN [5]) when each interrupt flags are clear + * | | |The time-out is enable when TOCNT bigger than 0. + * | | |Note: The TMCNTSRC (UI2C_BRGEN [5]) must be set zero on I2C mode. + * |[31] |PROTEN |I2C Protocol Enable Bit + * | | |0 = I2C Protocol disable. + * | | |1 = I2C Protocol enable. + * @var UI2C_T::PROTIEN + * Offset: 0x60 USCI Protocol Interrupt Enable Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |TOIEN |Time-out Interrupt Enable Control + * | | |In I2C protocol, this bit enables the interrupt generation in case of a time-out event. + * | | |0 = The time-out interrupt is disabled. + * | | |1 = The time-out interrupt is enabled. + * |[1] |STARIEN |Start Condition Received Interrupt Enable Control + * | | |This bit enables the generation of a protocol interrupt if a start condition is detected. + * | | |0 = The start condition interrupt is disabled. + * | | |1 = The start condition interrupt is enabled. + * |[2] |STORIEN |Stop Condition Received Interrupt Enable Control + * | | |This bit enables the generation of a protocol interrupt if a stop condition is detected. + * | | |0 = The stop condition interrupt is disabled. + * | | |1 = The stop condition interrupt is enabled. + * |[3] |NACKIEN |Non - Acknowledge Interrupt Enable Control + * | | |This bit enables the generation of a protocol interrupt if a non - acknowledge is detected by a master. + * | | |0 = The non - acknowledge interrupt is disabled. + * | | |1 = The non - acknowledge interrupt is enabled. + * |[4] |ARBLOIEN |Arbitration Lost Interrupt Enable Control + * | | |This bit enables the generation of a protocol interrupt if an arbitration lost event is detected. + * | | |0 = The arbitration lost interrupt is disabled. + * | | |1 = The arbitration lost interrupt is enabled. + * |[5] |ERRIEN |Error Interrupt Enable Control + * | | |This bit enables the generation of a protocol interrupt if an I2C error condition is detected (indicated by ERR (UI2C_PROTSTS [16])). + * | | |0 = The error interrupt is disabled. + * | | |1 = The error interrupt is enabled. + * |[6] |ACKIEN |Acknowledge Interrupt Enable Control + * | | |This bit enables the generation of a protocol interrupt if an acknowledge is detected by a master. + * | | |0 = The acknowledge interrupt is disabled. + * | | |1 = The acknowledge interrupt is enabled. + * @var UI2C_T::PROTSTS + * Offset: 0x64 USCI Protocol Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[5] |TOIF |Time-out Interrupt Flag + * | | |0 = A time-out interrupt status has not occurred. + * | | |1 = A time-out interrupt status has occurred. + * | | |Note: It is cleared by software writing one into this bit + * |[6] |ONBUSY |On Bus Busy + * | | |Indicates that a communication is in progress on the bus + * | | |It is set by hardware when a START condition is detected + * | | |It is cleared by hardware when a STOP condition is detected + * | | |0 = The bus is IDLE (both SCLK and SDA High). + * | | |1 = The bus is busy. + * |[8] |STARIF |Start Condition Received Interrupt Flag + * | | |This bit indicates that a start condition or repeated start condition has been detected on master mode + * | | |However, this bit also indicates that a repeated start condition has been detected on slave mode. + * | | |A protocol interrupt can be generated if UI2C_PROTCTL.STARIEN = 1. + * | | |0 = A start condition has not yet been detected. + * | | |1 = A start condition has been detected. + * | | |It is cleared by software writing one into this bit + * |[9] |STORIF |Stop Condition Received Interrupt Flag + * | | |This bit indicates that a stop condition has been detected on the I2C bus lines + * | | |A protocol interrupt can be generated if UI2C_PROTCTL.STORIEN = 1. + * | | |0 = A stop condition has not yet been detected. + * | | |1 = A stop condition has been detected. + * | | |It is cleared by software writing one into this bit + * | | |Note: This bit is set when slave RX mode. + * |[10] |NACKIF |Non - Acknowledge Received Interrupt Flag + * | | |This bit indicates that a non - acknowledge has been received in master mode + * | | |A protocol interrupt can be generated if UI2C_PROTCTL.NACKIEN = 1. + * | | |0 = A non - acknowledge has not been received. + * | | |1 = A non - acknowledge has been received. + * | | |It is cleared by software writing one into this bit + * |[11] |ARBLOIF |Arbitration Lost Interrupt Flag + * | | |This bit indicates that an arbitration has been lost + * | | |A protocol interrupt can be generated if UI2C_PROTCTL.ARBLOIEN = 1. + * | | |0 = An arbitration has not been lost. + * | | |1 = An arbitration has been lost. + * | | |It is cleared by software writing one into this bit + * |[12] |ERRIF |Error Interrupt Flag + * | | |This bit indicates that a Bus Error occurs when a START or STOP condition is present at an illegal position in the formation frame + * | | |Example of illegal position are during the serial transfer of an address byte, a data byte or an acknowledge bit + * | | |A protocol interrupt can be generated if UI2C_PROTCTL.ERRIEN = 1. + * | | |0 = An I2C error has not been detected. + * | | |1 = An I2C error has been detected. + * | | |It is cleared by software writing one into this bit + * | | |Note: This bit is set when slave mode, user must write one into STO register to the defined not addressed slave mode. + * |[13] |ACKIF |Acknowledge Received Interrupt Flag + * | | |This bit indicates that an acknowledge has been received in master mode + * | | |A protocol interrupt can be generated if UI2C_PROTCTL.ACKIEN = 1. + * | | |0 = An acknowledge has not been received. + * | | |1 = An acknowledge has been received. + * | | |It is cleared by software writing one into this bit + * |[14] |SLASEL |Slave Select Status + * | | |This bit indicates that this device has been selected as slave. + * | | |0 = The device is not selected as slave. + * | | |1 = The device is selected as slave. + * | | |Note: This bit has no interrupt signal, and it will be cleared automatically by hardware. + * |[15] |SLAREAD |Slave Read Request Status + * | | |This bit indicates that a slave read request has been detected. + * | | |0 = A slave R/W bit is 1 has not been detected. + * | | |1 = A slave R/W bit is 1 has been detected. + * | | |Note: This bit has no interrupt signal, and it will be cleared automatically by hardware. + * |[16] |WKAKDONE |Wakeup Address Frame Acknowledge Bit Done + * | | |0 = The ACK bit cycle of address match frame isn't done. + * | | |1 = The ACK bit cycle of address match frame is done in power-down. + * | | |Note: This bit can't release when WKUPIF is set. + * |[17] |WRSTSWK |Read/Write Status Bit in Address Wakeup Frame + * | | |0 = Write command be record on the address match wakeup frame. + * | | |1 = Read command be record on the address match wakeup frame. + * |[18] |BUSHANG |Bus Hang-up + * | | |This bit indicates bus hang-up status + * | | |There is 4-bit counter count when SCL hold high and refer fSAMP_CLK + * | | |The hang-up counter will count to overflow and set this bit when SDA is low + * | | |The counter will be reset by falling edge of SCL signal. + * | | |0 = The bus is normal status for transmission. + * | | |1 = The bus is hang-up status for transmission. + * | | |Note: This bit has no interrupt signal, and it will be cleared automatically by hardware when a START condition is present. + * |[19] |ERRARBLO |Error Arbitration Lost + * | | |This bit indicates bus arbitration lost due to bigger noise which is can't be filtered by input processor + * | | |The I2C can send start condition when ERRARBLO is set + * | | |Thus this bit doesn't be cared on slave mode. + * | | |0 = The bus is normal status for transmission. + * | | |1 = The bus is error arbitration lost status for transmission. + * | | |Note: This bit has no interrupt signal, and it will be cleared automatically by hardware when a START condition is present. + * @var UI2C_T::ADMAT + * Offset: 0x88 I2C Slave Match Address Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |ADMAT0 |USCI Address 0 Match Status Register + * | | |When address 0 is matched, hardware will inform which address used + * | | |This bit will set to 1, and software can write 1 to clear this bit. + * |[1] |ADMAT1 |USCI Address 1 Match Status Register + * | | |When address 1 is matched, hardware will inform which address used + * | | |This bit will set to 1, and software can write 1 to clear this bit. + * @var UI2C_T::TMCTL + * Offset: 0x8C I2C Timing Configure Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[8:0] |STCTL |Setup Time Configure Control Register + * | | |This field is used to generate a delay timing between SDA edge and SCL rising edge in transmission mode.. + * | | |The delay setup time is numbers of peripheral clock = STCTL x fPCLK. + * |[24:16] |HTCTL |Hold Time Configure Control Register + * | | |This field is used to generate the delay timing between SCL falling edge SDA edge in + * | | |transmission mode. + * | | |The delay hold time is numbers of peripheral clock = HTCTL x fPCLK. + */ + __IO uint32_t CTL; /*!< [0x0000] USCI Control Register */ + __I uint32_t RESERVE0[1]; + __IO uint32_t BRGEN; /*!< [0x0008] USCI Baud Rate Generator Register */ + __I uint32_t RESERVE1[8]; + __IO uint32_t LINECTL; /*!< [0x002c] USCI Line Control Register */ + __O uint32_t TXDAT; /*!< [0x0030] USCI Transmit Data Register */ + __I uint32_t RXDAT; /*!< [0x0034] USCI Receive Data Register */ + __I uint32_t RESERVE2[3]; + __IO uint32_t DEVADDR0; /*!< [0x0044] USCI Device Address Register 0 */ + __IO uint32_t DEVADDR1; /*!< [0x0048] USCI Device Address Register 1 */ + __IO uint32_t ADDRMSK0; /*!< [0x004c] USCI Device Address Mask Register 0 */ + __IO uint32_t ADDRMSK1; /*!< [0x0050] USCI Device Address Mask Register 1 */ + __IO uint32_t WKCTL; /*!< [0x0054] USCI Wake-up Control Register */ + __IO uint32_t WKSTS; /*!< [0x0058] USCI Wake-up Status Register */ + __IO uint32_t PROTCTL; /*!< [0x005c] USCI Protocol Control Register */ + __IO uint32_t PROTIEN; /*!< [0x0060] USCI Protocol Interrupt Enable Register */ + __IO uint32_t PROTSTS; /*!< [0x0064] USCI Protocol Status Register */ + __I uint32_t RESERVE3[8]; + __IO uint32_t ADMAT; /*!< [0x0088] I2C Slave Match Address Register */ + __IO uint32_t TMCTL; /*!< [0x008c] I2C Timing Configure Control Register */ + +} UI2C_T; + +/** + @addtogroup UI2C_CONST UI2C Bit Field Definition + Constant Definitions for UI2C Controller + @{ +*/ + +#define UI2C_CTL_FUNMODE_Pos (0) /*!< UI2C_T::CTL: FUNMODE Position */ +#define UI2C_CTL_FUNMODE_Msk (0x7ul << UI2C_CTL_FUNMODE_Pos) /*!< UI2C_T::CTL: FUNMODE Mask */ + +#define UI2C_BRGEN_RCLKSEL_Pos (0) /*!< UI2C_T::BRGEN: RCLKSEL Position */ +#define UI2C_BRGEN_RCLKSEL_Msk (0x1ul << UI2C_BRGEN_RCLKSEL_Pos) /*!< UI2C_T::BRGEN: RCLKSEL Mask */ + +#define UI2C_BRGEN_PTCLKSEL_Pos (1) /*!< UI2C_T::BRGEN: PTCLKSEL Position */ +#define UI2C_BRGEN_PTCLKSEL_Msk (0x1ul << UI2C_BRGEN_PTCLKSEL_Pos) /*!< UI2C_T::BRGEN: PTCLKSEL Mask */ + +#define UI2C_BRGEN_SPCLKSEL_Pos (2) /*!< UI2C_T::BRGEN: SPCLKSEL Position */ +#define UI2C_BRGEN_SPCLKSEL_Msk (0x3ul << UI2C_BRGEN_SPCLKSEL_Pos) /*!< UI2C_T::BRGEN: SPCLKSEL Mask */ + +#define UI2C_BRGEN_TMCNTEN_Pos (4) /*!< UI2C_T::BRGEN: TMCNTEN Position */ +#define UI2C_BRGEN_TMCNTEN_Msk (0x1ul << UI2C_BRGEN_TMCNTEN_Pos) /*!< UI2C_T::BRGEN: TMCNTEN Mask */ + +#define UI2C_BRGEN_TMCNTSRC_Pos (5) /*!< UI2C_T::BRGEN: TMCNTSRC Position */ +#define UI2C_BRGEN_TMCNTSRC_Msk (0x1ul << UI2C_BRGEN_TMCNTSRC_Pos) /*!< UI2C_T::BRGEN: TMCNTSRC Mask */ + +#define UI2C_BRGEN_PDSCNT_Pos (8) /*!< UI2C_T::BRGEN: PDSCNT Position */ +#define UI2C_BRGEN_PDSCNT_Msk (0x3ul << UI2C_BRGEN_PDSCNT_Pos) /*!< UI2C_T::BRGEN: PDSCNT Mask */ + +#define UI2C_BRGEN_DSCNT_Pos (10) /*!< UI2C_T::BRGEN: DSCNT Position */ +#define UI2C_BRGEN_DSCNT_Msk (0x1ful << UI2C_BRGEN_DSCNT_Pos) /*!< UI2C_T::BRGEN: DSCNT Mask */ + +#define UI2C_BRGEN_CLKDIV_Pos (16) /*!< UI2C_T::BRGEN: CLKDIV Position */ +#define UI2C_BRGEN_CLKDIV_Msk (0x3fful << UI2C_BRGEN_CLKDIV_Pos) /*!< UI2C_T::BRGEN: CLKDIV Mask */ + +#define UI2C_LINECTL_LSB_Pos (0) /*!< UI2C_T::LINECTL: LSB Position */ +#define UI2C_LINECTL_LSB_Msk (0x1ul << UI2C_LINECTL_LSB_Pos) /*!< UI2C_T::LINECTL: LSB Mask */ + +#define UI2C_LINECTL_DWIDTH_Pos (8) /*!< UI2C_T::LINECTL: DWIDTH Position */ +#define UI2C_LINECTL_DWIDTH_Msk (0xful << UI2C_LINECTL_DWIDTH_Pos) /*!< UI2C_T::LINECTL: DWIDTH Mask */ + +#define UI2C_TXDAT_TXDAT_Pos (0) /*!< UI2C_T::TXDAT: TXDAT Position */ +#define UI2C_TXDAT_TXDAT_Msk (0xfffful << UI2C_TXDAT_TXDAT_Pos) /*!< UI2C_T::TXDAT: TXDAT Mask */ + +#define UI2C_RXDAT_RXDAT_Pos (0) /*!< UI2C_T::RXDAT: RXDAT Position */ +#define UI2C_RXDAT_RXDAT_Msk (0xfffful << UI2C_RXDAT_RXDAT_Pos) /*!< UI2C_T::RXDAT: RXDAT Mask */ + +#define UI2C_DEVADDR0_DEVADDR_Pos (0) /*!< UI2C_T::DEVADDR0: DEVADDR Position */ +#define UI2C_DEVADDR0_DEVADDR_Msk (0x3fful << UI2C_DEVADDR0_DEVADDR_Pos) /*!< UI2C_T::DEVADDR0: DEVADDR Mask */ + +#define UI2C_DEVADDR1_DEVADDR_Pos (0) /*!< UI2C_T::DEVADDR1: DEVADDR Position */ +#define UI2C_DEVADDR1_DEVADDR_Msk (0x3fful << UI2C_DEVADDR1_DEVADDR_Pos) /*!< UI2C_T::DEVADDR1: DEVADDR Mask */ + +#define UI2C_ADDRMSK0_ADDRMSK_Pos (0) /*!< UI2C_T::ADDRMSK0: ADDRMSK Position */ +#define UI2C_ADDRMSK0_ADDRMSK_Msk (0x3fful << UI2C_ADDRMSK0_ADDRMSK_Pos) /*!< UI2C_T::ADDRMSK0: ADDRMSK Mask */ + +#define UI2C_ADDRMSK1_ADDRMSK_Pos (0) /*!< UI2C_T::ADDRMSK1: ADDRMSK Position */ +#define UI2C_ADDRMSK1_ADDRMSK_Msk (0x3fful << UI2C_ADDRMSK1_ADDRMSK_Pos) /*!< UI2C_T::ADDRMSK1: ADDRMSK Mask */ + +#define UI2C_WKCTL_WKEN_Pos (0) /*!< UI2C_T::WKCTL: WKEN Position */ +#define UI2C_WKCTL_WKEN_Msk (0x1ul << UI2C_WKCTL_WKEN_Pos) /*!< UI2C_T::WKCTL: WKEN Mask */ + +#define UI2C_WKCTL_WKADDREN_Pos (1) /*!< UI2C_T::WKCTL: WKADDREN Position */ +#define UI2C_WKCTL_WKADDREN_Msk (0x1ul << UI2C_WKCTL_WKADDREN_Pos) /*!< UI2C_T::WKCTL: WKADDREN Mask */ + +#define UI2C_WKSTS_WKF_Pos (0) /*!< UI2C_T::WKSTS: WKF Position */ +#define UI2C_WKSTS_WKF_Msk (0x1ul << UI2C_WKSTS_WKF_Pos) /*!< UI2C_T::WKSTS: WKF Mask */ + +#define UI2C_PROTCTL_GCFUNC_Pos (0) /*!< UI2C_T::PROTCTL: GCFUNC Position */ +#define UI2C_PROTCTL_GCFUNC_Msk (0x1ul << UI2C_PROTCTL_GCFUNC_Pos) /*!< UI2C_T::PROTCTL: GCFUNC Mask */ + +#define UI2C_PROTCTL_AA_Pos (1) /*!< UI2C_T::PROTCTL: AA Position */ +#define UI2C_PROTCTL_AA_Msk (0x1ul << UI2C_PROTCTL_AA_Pos) /*!< UI2C_T::PROTCTL: AA Mask */ + +#define UI2C_PROTCTL_STO_Pos (2) /*!< UI2C_T::PROTCTL: STO Position */ +#define UI2C_PROTCTL_STO_Msk (0x1ul << UI2C_PROTCTL_STO_Pos) /*!< UI2C_T::PROTCTL: STO Mask */ + +#define UI2C_PROTCTL_STA_Pos (3) /*!< UI2C_T::PROTCTL: STA Position */ +#define UI2C_PROTCTL_STA_Msk (0x1ul << UI2C_PROTCTL_STA_Pos) /*!< UI2C_T::PROTCTL: STA Mask */ + +#define UI2C_PROTCTL_ADDR10EN_Pos (4) /*!< UI2C_T::PROTCTL: ADDR10EN Position */ +#define UI2C_PROTCTL_ADDR10EN_Msk (0x1ul << UI2C_PROTCTL_ADDR10EN_Pos) /*!< UI2C_T::PROTCTL: ADDR10EN Mask */ + +#define UI2C_PROTCTL_PTRG_Pos (5) /*!< UI2C_T::PROTCTL: PTRG Position */ +#define UI2C_PROTCTL_PTRG_Msk (0x1ul << UI2C_PROTCTL_PTRG_Pos) /*!< UI2C_T::PROTCTL: PTRG Mask */ + +#define UI2C_PROTCTL_SCLOUTEN_Pos (8) /*!< UI2C_T::PROTCTL: SCLOUTEN Position */ +#define UI2C_PROTCTL_SCLOUTEN_Msk (0x1ul << UI2C_PROTCTL_SCLOUTEN_Pos) /*!< UI2C_T::PROTCTL: SCLOUTEN Mask */ + +#define UI2C_PROTCTL_MONEN_Pos (9) /*!< UI2C_T::PROTCTL: MONEN Position */ +#define UI2C_PROTCTL_MONEN_Msk (0x1ul << UI2C_PROTCTL_MONEN_Pos) /*!< UI2C_T::PROTCTL: MONEN Mask */ + +#define UI2C_PROTCTL_TOCNT_Pos (16) /*!< UI2C_T::PROTCTL: TOCNT Position */ +#define UI2C_PROTCTL_TOCNT_Msk (0x3fful << UI2C_PROTCTL_TOCNT_Pos) /*!< UI2C_T::PROTCTL: TOCNT Mask */ + +#define UI2C_PROTCTL_PROTEN_Pos (31) /*!< UI2C_T::PROTCTL: PROTEN Position */ +#define UI2C_PROTCTL_PROTEN_Msk (0x1ul << UI2C_PROTCTL_PROTEN_Pos) /*!< UI2C_T::PROTCTL: PROTEN Mask */ + +#define UI2C_PROTIEN_TOIEN_Pos (0) /*!< UI2C_T::PROTIEN: TOIEN Position */ +#define UI2C_PROTIEN_TOIEN_Msk (0x1ul << UI2C_PROTIEN_TOIEN_Pos) /*!< UI2C_T::PROTIEN: TOIEN Mask */ + +#define UI2C_PROTIEN_STARIEN_Pos (1) /*!< UI2C_T::PROTIEN: STARIEN Position */ +#define UI2C_PROTIEN_STARIEN_Msk (0x1ul << UI2C_PROTIEN_STARIEN_Pos) /*!< UI2C_T::PROTIEN: STARIEN Mask */ + +#define UI2C_PROTIEN_STORIEN_Pos (2) /*!< UI2C_T::PROTIEN: STORIEN Position */ +#define UI2C_PROTIEN_STORIEN_Msk (0x1ul << UI2C_PROTIEN_STORIEN_Pos) /*!< UI2C_T::PROTIEN: STORIEN Mask */ + +#define UI2C_PROTIEN_NACKIEN_Pos (3) /*!< UI2C_T::PROTIEN: NACKIEN Position */ +#define UI2C_PROTIEN_NACKIEN_Msk (0x1ul << UI2C_PROTIEN_NACKIEN_Pos) /*!< UI2C_T::PROTIEN: NACKIEN Mask */ + +#define UI2C_PROTIEN_ARBLOIEN_Pos (4) /*!< UI2C_T::PROTIEN: ARBLOIEN Position */ +#define UI2C_PROTIEN_ARBLOIEN_Msk (0x1ul << UI2C_PROTIEN_ARBLOIEN_Pos) /*!< UI2C_T::PROTIEN: ARBLOIEN Mask */ + +#define UI2C_PROTIEN_ERRIEN_Pos (5) /*!< UI2C_T::PROTIEN: ERRIEN Position */ +#define UI2C_PROTIEN_ERRIEN_Msk (0x1ul << UI2C_PROTIEN_ERRIEN_Pos) /*!< UI2C_T::PROTIEN: ERRIEN Mask */ + +#define UI2C_PROTIEN_ACKIEN_Pos (6) /*!< UI2C_T::PROTIEN: ACKIEN Position */ +#define UI2C_PROTIEN_ACKIEN_Msk (0x1ul << UI2C_PROTIEN_ACKIEN_Pos) /*!< UI2C_T::PROTIEN: ACKIEN Mask */ + +#define UI2C_PROTSTS_TOIF_Pos (5) /*!< UI2C_T::PROTSTS: TOIF Position */ +#define UI2C_PROTSTS_TOIF_Msk (0x1ul << UI2C_PROTSTS_TOIF_Pos) /*!< UI2C_T::PROTSTS: TOIF Mask */ + +#define UI2C_PROTSTS_ONBUSY_Pos (6) /*!< UI2C_T::PROTSTS: ONBUSY Position */ +#define UI2C_PROTSTS_ONBUSY_Msk (0x1ul << UI2C_PROTSTS_ONBUSY_Pos) /*!< UI2C_T::PROTSTS: ONBUSY Mask */ + +#define UI2C_PROTSTS_STARIF_Pos (8) /*!< UI2C_T::PROTSTS: STARIF Position */ +#define UI2C_PROTSTS_STARIF_Msk (0x1ul << UI2C_PROTSTS_STARIF_Pos) /*!< UI2C_T::PROTSTS: STARIF Mask */ + +#define UI2C_PROTSTS_STORIF_Pos (9) /*!< UI2C_T::PROTSTS: STORIF Position */ +#define UI2C_PROTSTS_STORIF_Msk (0x1ul << UI2C_PROTSTS_STORIF_Pos) /*!< UI2C_T::PROTSTS: STORIF Mask */ + +#define UI2C_PROTSTS_NACKIF_Pos (10) /*!< UI2C_T::PROTSTS: NACKIF Position */ +#define UI2C_PROTSTS_NACKIF_Msk (0x1ul << UI2C_PROTSTS_NACKIF_Pos) /*!< UI2C_T::PROTSTS: NACKIF Mask */ + +#define UI2C_PROTSTS_ARBLOIF_Pos (11) /*!< UI2C_T::PROTSTS: ARBLOIF Position */ +#define UI2C_PROTSTS_ARBLOIF_Msk (0x1ul << UI2C_PROTSTS_ARBLOIF_Pos) /*!< UI2C_T::PROTSTS: ARBLOIF Mask */ + +#define UI2C_PROTSTS_ERRIF_Pos (12) /*!< UI2C_T::PROTSTS: ERRIF Position */ +#define UI2C_PROTSTS_ERRIF_Msk (0x1ul << UI2C_PROTSTS_ERRIF_Pos) /*!< UI2C_T::PROTSTS: ERRIF Mask */ + +#define UI2C_PROTSTS_ACKIF_Pos (13) /*!< UI2C_T::PROTSTS: ACKIF Position */ +#define UI2C_PROTSTS_ACKIF_Msk (0x1ul << UI2C_PROTSTS_ACKIF_Pos) /*!< UI2C_T::PROTSTS: ACKIF Mask */ + +#define UI2C_PROTSTS_SLASEL_Pos (14) /*!< UI2C_T::PROTSTS: SLASEL Position */ +#define UI2C_PROTSTS_SLASEL_Msk (0x1ul << UI2C_PROTSTS_SLASEL_Pos) /*!< UI2C_T::PROTSTS: SLASEL Mask */ + +#define UI2C_PROTSTS_SLAREAD_Pos (15) /*!< UI2C_T::PROTSTS: SLAREAD Position */ +#define UI2C_PROTSTS_SLAREAD_Msk (0x1ul << UI2C_PROTSTS_SLAREAD_Pos) /*!< UI2C_T::PROTSTS: SLAREAD Mask */ + +#define UI2C_PROTSTS_WKAKDONE_Pos (16) /*!< UI2C_T::PROTSTS: WKAKDONE Position */ +#define UI2C_PROTSTS_WKAKDONE_Msk (0x1ul << UI2C_PROTSTS_WKAKDONE_Pos) /*!< UI2C_T::PROTSTS: WKAKDONE Mask */ + +#define UI2C_PROTSTS_WRSTSWK_Pos (17) /*!< UI2C_T::PROTSTS: WRSTSWK Position */ +#define UI2C_PROTSTS_WRSTSWK_Msk (0x1ul << UI2C_PROTSTS_WRSTSWK_Pos) /*!< UI2C_T::PROTSTS: WRSTSWK Mask */ + +#define UI2C_PROTSTS_BUSHANG_Pos (18) /*!< UI2C_T::PROTSTS: BUSHANG Position */ +#define UI2C_PROTSTS_BUSHANG_Msk (0x1ul << UI2C_PROTSTS_BUSHANG_Pos) /*!< UI2C_T::PROTSTS: BUSHANG Mask */ + +#define UI2C_PROTSTS_ERRARBLO_Pos (19) /*!< UI2C_T::PROTSTS: ERRARBLO Position */ +#define UI2C_PROTSTS_ERRARBLO_Msk (0x1ul << UI2C_PROTSTS_ERRARBLO_Pos) /*!< UI2C_T::PROTSTS: ERRARBLO Mask */ + +#define UI2C_ADMAT_ADMAT0_Pos (0) /*!< UI2C_T::ADMAT: ADMAT0 Position */ +#define UI2C_ADMAT_ADMAT0_Msk (0x1ul << UI2C_ADMAT_ADMAT0_Pos) /*!< UI2C_T::ADMAT: ADMAT0 Mask */ + +#define UI2C_ADMAT_ADMAT1_Pos (1) /*!< UI2C_T::ADMAT: ADMAT1 Position */ +#define UI2C_ADMAT_ADMAT1_Msk (0x1ul << UI2C_ADMAT_ADMAT1_Pos) /*!< UI2C_T::ADMAT: ADMAT1 Mask */ + +#define UI2C_TMCTL_STCTL_Pos (0) /*!< UI2C_T::TMCTL: STCTL Position */ +#define UI2C_TMCTL_STCTL_Msk (0x1fful << UI2C_TMCTL_STCTL_Pos) /*!< UI2C_T::TMCTL: STCTL Mask */ + +#define UI2C_TMCTL_HTCTL_Pos (16) /*!< UI2C_T::TMCTL: HTCTL Position */ +#define UI2C_TMCTL_HTCTL_Msk (0x1fful << UI2C_TMCTL_HTCTL_Pos) /*!< UI2C_T::TMCTL: HTCTL Mask */ + +/**@}*/ /* UI2C_CONST */ +/**@}*/ /* end of UI2C register group */ +/**@}*/ /* end of REGISTER group */ + +#endif /* __UI2C_REG_H__ */ diff --git a/Ubiquitous/XiZi/board/nuvoton-m2354/third_party_driver/include/Regs/usbd_reg.h b/Ubiquitous/XiZi/board/nuvoton-m2354/third_party_driver/include/Regs/usbd_reg.h new file mode 100644 index 0000000..e544931 --- /dev/null +++ b/Ubiquitous/XiZi/board/nuvoton-m2354/third_party_driver/include/Regs/usbd_reg.h @@ -0,0 +1,658 @@ +/**************************************************************************//** + * @file usbd_reg.h + * @version V1.00 + * @brief USBD register definition header file + * + * @copyright SPDX-License-Identifier: Apache-2.0 + * @copyright Copyright (C) 2020 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ +#ifndef __USBD_REG_H__ +#define __USBD_REG_H__ + +/** @addtogroup REGISTER Control Register + + @{ + +*/ + +/*---------------------- USB Device Controller -------------------------*/ +/** + @addtogroup USBD USB Device Controller(USBD) + Memory Mapped Structure for USBD Controller + @{ +*/ + + + +/** + * @brief USBD endpoints register + */ +typedef struct +{ + /** + * @var USBD_EP_T::BUFSEG + * Offset: 0x500/0x510/0x520/0x530/0x540/0x550/0x560/0x570/0x580/0x590/0x5A0/0x5B0 Endpoint Buffer Segmentation Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[8:3] |BUFSEG |Endpoint Buffer Segmentation + * | | |It is used to indicate the offset address for each endpoint with the USB SRAM starting address The effective starting address of the endpoint is + * | | |USBD_SRAM address + {BUFSEG, 3'b000} + * | | |Where the USBD_SRAM address = USBD_BA+0x100h. + * | | |Refer to the section 6.32.5.7 for the endpoint SRAM structure and its description. + * @var USBD_EP_T::MXPLD + * Offset: 0x504/0x514/0x524/0x534/0x544/0x554/0x564/0x574/0x584/0x594/0x5A4/0x5B4 Endpoint Maximal Payload Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[8:0] |MXPLD |Maximal Payload + * | | |Define the data length which is transmitted to host (IN token) or the actual data length which is received from the host (OUT token) + * | | |It also used to indicate that the endpoint is ready to be transmitted in IN token or received in OUT token. + * | | |(1) When the register is written by CPU, + * | | |For IN token, the value of MXPLD is used to define the data length to be transmitted and indicate the data buffer is ready. + * | | |For OUT token, it means that the controller is ready to receive data from the host and the value of MXPLD is the maximal data length comes from host. + * | | |(2) When the register is read by CPU, + * | | |For IN token, the value of MXPLD is indicated by the data length be transmitted to host. + * | | |For OUT token, the value of MXPLD is indicated the actual data length receiving from host. + * | | |Note: Once MXPLD is written, the data packets will be transmitted/received immediately after IN/OUT token arrived. + * @var USBD_EP_T::CFG + * Offset: 0x508/0x518/0x528/0x538/0x548/0x558/0x568/0x578/0x588/0x598/0x5A8/0x5B8 Endpoint Configuration Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[3:0] |EPNUM |Endpoint Number + * | | |These bits are used to define the endpoint number of the current endpoint. + * |[4] |ISOCH |Isochronous Endpoint + * | | |This bit is used to set the endpoint as Isochronous endpoint, no handshake. + * | | |0 = No Isochronous endpoint. + * | | |1 = Isochronous endpoint. + * |[6:5] |STATE |Endpoint State + * | | |00 = Endpoint Disabled. + * | | |01 = Out endpoint. + * | | |10 = IN endpoint. + * | | |11 = Undefined. + * |[7] |DSQSYNC |Data Sequence Synchronization + * | | |0 = DATA0 PID. + * | | |1 = DATA1 PID. + * | | |For IN token, DSQSYNC specify DATA0 or DATA1 PID in transfer data packet. + * | | |For OUT token, DSQSYNC specify DATA0 or DATA1 PID in received data packet. + * | | |DSQSYNC will be toggled automatically by hardware when IN or OUT token transfer successfully in single buffer mode, but won’t be toggled in double buffer mode. + * | | |Note 1: When double buffer is enabled, hardware will automatically write 0 to DSQSYNC with active double buffer and write 1 to DSQSYNC with inactive double buffer. + * | | |Note 2: It won’t be toggled by hardware when DBEN = 1. USB data toggle will be guaranteed by changing endpoint. + * |[9] |CSTALL |Clear STALL Response + * | | |0 = Disable the device to clear the STALL handshake in setup stage. + * | | |1 = Clear the device to response STALL handshake in setup stage. + * |[10] |DBTGACTIVE|Double Buffer Toggle Active Bit + * | | |0 = Inactive in double buffer mode. + * | | |1 = Active in double buffer mode. + * | | |When DBEN = 1 and endpoint successful transfer, DBTGACTIVE of each double buffer will be toggled automatically by hardware. + * |[11] |DBEN |Double Buffer Enable + * | | |0 = Single buffer mode. + * | | |1 = Double buffer mode. + * @var USBD_EP_T::CFGP + * Offset: 0x50C/0x51C/0x52C/0x53C/0x54C/0x55C/0x56C/0x57C/0x58C/0x59C/0x5AC/0x5BC Endpoint Set Stall and Clear In/Out Ready Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |CLRRDY |Clear Ready + * | | |When the USBD_MXPLDx register is set by user, it means that the endpoint is ready to transmit or receive data + * | | |If the user wants to disable this transaction before the transaction start, users can set this bit to 1 to disable it and it is automatically cleared to 0. + * | | |For IN token, write '1' to clear the IN token had ready to transmit the data to USB. + * | | |For OUT token, write '1' to clear the OUT token had ready to receive the data from USB. + * | | |This bit is written 1 only and is always 0 when it is read back. + * |[1] |SSTALL |Set STALL + * | | |0 = Disable the device to response STALL. + * | | |1 = Set the device to respond STALL automatically. + */ + __IO uint32_t BUFSEG; /*!< [0x0000] Endpoint Buffer Segmentation Register */ + __IO uint32_t MXPLD; /*!< [0x0004] Endpoint Maximal Payload Register */ + __IO uint32_t CFG; /*!< [0x0008] Endpoint Configuration Register */ + __IO uint32_t CFGP; /*!< [0x000c] Endpoint Set Stall and Clear In/Out Ready Control Register */ + +} USBD_EP_T; + +typedef struct +{ + + + /** + * @var USBD_T::INTEN + * Offset: 0x00 USB Device Interrupt Enable Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |BUSIEN |Bus Event Interrupt Enable Bit + * | | |0 = BUS event interrupt Disabled. + * | | |1 = BUS event interrupt Enabled. + * |[1] |USBIEN |USB Event Interrupt Enable Bit + * | | |0 = USB event interrupt Disabled. + * | | |1 = USB event interrupt Enabled. + * |[2] |VBDETIEN |VBUS Detection Interrupt Enable Bit + * | | |0 = VBUS detection Interrupt Disabled. + * | | |1 = VBUS detection Interrupt Enabled. + * |[3] |NEVWKIEN |USB No-event-wake-up Interrupt Enable Bit + * | | |0 = No-event-wake-up Interrupt Disabled. + * | | |1 = No-event-wake-up Interrupt Enabled. + * |[4] |SOFIEN |Start of Frame Interrupt Enable Bit + * | | |0 = SOF Interrupt Disabled. + * | | |1 = SOF Interrupt Enabled. + * |[8] |WKEN |Wake-up Function Enable Bit + * | | |0 = USB wake-up function Disabled. + * | | |1 = USB wake-up function Enabled. + * |[15] |INNAKEN |Active NAK Function and Its Status in IN Token + * | | |0 = When device responds NAK after receiving IN token, IN NAK status will not be updated to USBD_EPSTS0 and USBD_EPSTS1register, so that the USB interrupt event will not be asserted. + * | | |1 = IN NAK status will be updated to USBD_EPSTS0 and USBD_EPSTS1 register and the USB interrupt event will be asserted, when the device responds NAK after receiving IN token. + * @var USBD_T::INTSTS + * Offset: 0x04 USB Device Interrupt Event Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |BUSIF |BUS Interrupt Status + * | | |The BUS event means that there is one of the suspense or the resume function in the bus. + * | | |0 = No BUS event occurred. + * | | |1 = Bus event occurred. Check USBD_ATTR[3:0] to know which kind of bus event was occurred, cleared by writing 1 to USBD_INTSTS[0]. + * |[1] |USBIF |USB Event Interrupt Status + * | | |The USB event includes the SETUP Token, IN Token, OUT ACK, ISO IN, or ISO OUT events in the bus. + * | | |0 = No USB event occurred. + * | | |1 = USB event occurred. Check EPSTS0~11[3:0] to know which kind of USB event was occurred, cleared by writing 1 to USBD_INTSTS[1] or EPSTS0~11 and SETUP (USBD_INTSTS[31]). + * |[2] |VBDETIF |VBUS Detection Interrupt Status + * | | |0 = There is no attached/detached event in the USB. + * | | |1 = There is attached/detached event in the USB bus and it is cleared by writing 1 to USBD_INTSTS[2]. + * |[3] |NEVWKIF |No-event-wake-up Interrupt Status + * | | |0 = NEVWK event did not occur. + * | | |1 = No-event-wake-up event occurred, cleared by writing 1 to USBD_INTSTS[3]. + * |[4] |SOFIF |Start of Frame Interrupt Status + * | | |0 = SOF event did not occur. + * | | |1 = SOF event occurred, cleared by writing 1 to USBD_INTSTS[4]. + * |[16] |EPEVT0 |Endpoint 0's USB Event Status + * | | |0 = No event occurred in endpoint 0. + * | | |1 = USB event occurred on Endpoint 0. Check USBD_EPSTS0[3:0] to know which kind of USB event was occurred, cleared by writing 1 to USBD_INTSTS[16] or USBD_INTSTS[1]. + * |[17] |EPEVT1 |Endpoint 1's USB Event Status + * | | |0 = No event occurred in endpoint 1. + * | | |1 = USB event occurred on Endpoint 1. Check USBD_EPSTS0[7:4] to know which kind of USB event was occurred, cleared by writing 1 to USBD_INTSTS[17] or USBD_INTSTS[1]. + * |[18] |EPEVT2 |Endpoint 2's USB Event Status + * | | |0 = No event occurred in endpoint 2. + * | | |1 = USB event occurred on Endpoint 2. Check USBD_EPSTS0[11:8] to know which kind of USB event was occurred, cleared by writing 1 to USBD_INTSTS[18] or USBD_INTSTS[1]. + * |[19] |EPEVT3 |Endpoint 3's USB Event Status + * | | |0 = No event occurred in endpoint 3. + * | | |1 = USB event occurred on Endpoint 3. Check USBD_EPSTS0[15:12] to know which kind of USB event was occurred, cleared by writing 1 to USBD_INTSTS[19] or USBD_INTSTS[1]. + * |[20] |EPEVT4 |Endpoint 4's USB Event Status + * | | |0 = No event occurred in endpoint 4. + * | | |1 = USB event occurred on Endpoint 4. Check USBD_EPSTS0[19:16] to know which kind of USB event was occurred, cleared by writing 1 to USBD_INTSTS[20] or USBD_INTSTS[1]. + * |[21] |EPEVT5 |Endpoint 5's USB Event Status + * | | |0 = No event occurred in endpoint 5. + * | | |1 = USB event occurred on Endpoint 5. Check USBD_EPSTS0[23:20] to know which kind of USB event was occurred, cleared by writing 1 to USBD_INTSTS[21] or USBD_INTSTS[1]. + * |[22] |EPEVT6 |Endpoint 6's USB Event Status + * | | |0 = No event occurred in endpoint 6. + * | | |1 = USB event occurred on Endpoint 6. Check USBD_EPSTS0[27:24] to know which kind of USB event was occurred, cleared by writing 1 to USBD_INTSTS[22] or USBD_INTSTS[1]. + * |[23] |EPEVT7 |Endpoint 7's USB Event Status + * | | |0 = No event occurred in endpoint 7. + * | | |1 = USB event occurred on Endpoint 7. Check USBD_EPSTS0[31:28] to know which kind of USB event was occurred, cleared by writing 1 to USBD_INTSTS[23] or USBD_INTSTS[1]. + * |[24] |EPEVT8 |Endpoint 8's USB Event Status + * | | |0 = No event occurred in endpoint 8. + * | | |1 = USB event occurred on Endpoint 8. Check USBD_EPSTS1[3:0] to know which kind of USB event was occurred, cleared by writing 1 to USBD_INTSTS[24] or USBD_INTSTS[1]. + * |[25] |EPEVT9 |Endpoint 9's USB Event Status + * | | |0 = No event occurred in endpoint 9. + * | | |1 = USB event occurred on Endpoint 9. Check USBD_EPSTS1[7:4] to know which kind of USB event was occurred, cleared by writing 1 to USBD_INTSTS[25] or USBD_INTSTS[1]. + * |[26] |EPEVT10 |Endpoint 10's USB Event Status + * | | |0 = No event occurred in endpoint 10. + * | | |1 = USB event occurred on Endpoint 10. Check USBD_EPSTS1[11:8] to know which kind of USB event was occurred, cleared by writing 1 to USBD_INTSTS[26] or USBD_INTSTS[1]. + * |[27] |EPEVT11 |Endpoint 11's USB Event Status + * | | |0 = No event occurred in endpoint 11. + * | | |1 = USB event occurred on Endpoint 11. Check USBD_EPSTS1[15:12] to know which kind of USB event was occurred, cleared by writing 1 to USBD_INTSTS[27] or USBD_INTSTS[1]. + * |[31] |SETUP |Setup Event Status + * | | |0 = No Setup event. + * | | |1 = Setup event occurred, cleared by writing 1 to USBD_INTSTS[31]. + * @var USBD_T::FADDR + * Offset: 0x08 USB Device Function Address Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[6:0] |FADDR |USB Device Function Address + * @var USBD_T::EPSTS + * Offset: 0x0C USB Device Endpoint Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[7] |OV |Overrun + * | | |It indicates that the received data is over the maximum payload number or not. + * | | |0 = No overrun. + * | | |1 = Out Data is more than the Max Payload in MXPLD register or the Setup Data is more than 8 bytes. + * @var USBD_T::ATTR + * Offset: 0x10 USB Device Bus Status and Attribution Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |USBRST |USB Reset Status (Read Only) + * | | |0 = Bus no reset. + * | | |1 = Bus reset when SE0 (single-ended 0) more than 2.5us. + * |[1] |SUSPEND |Suspend Status (Read Only) + * | | |0 = Bus no suspend. + * | | |1 = Bus idle more than 3ms, either cable is plugged-out or host is sleeping. + * |[2] |RESUME |Resume Status (Read Only) + * | | |0 = No bus resume. + * | | |1 = Resume from suspend. + * |[3] |TOUT |Time-out Status (Read Only) + * | | |0 = No time-out. + * | | |1 = No Bus response more than 18 bits time. + * |[4] |PHYEN |PHY Transceiver Function Enable Bit + * | | |0 = PHY transceiver function Disabled. + * | | |1 = PHY transceiver function Enabled. + * |[5] |RWAKEUP |Remote Wake-up + * | | |0 = Release the USB bus from K state. + * | | |1 = Force USB bus to K (USB_D+ low, USB_D-: high) state, used for remote wake-up. + * |[7] |USBEN |USB Controller Enable Bit + * | | |0 = USB Controller Disabled. + * | | |1 = USB Controller Enabled. + * |[8] |DPPUEN |Pull-up Resistor on USB_DP Enable Bit + * | | |0 = Pull-up resistor in USB_D+ bus Disabled. + * | | |1 = Pull-up resistor in USB_D+ bus Active. + * |[10] |BYTEM |CPU Access USB SRAM Size Mode Selection + * | | |0 = Word mode: The size of the transfer from CPU to USB SRAM can be Word only. + * | | |1 = Byte mode: The size of the transfer from CPU to USB SRAM can be Byte only. + * |[11] |LPMACK |LPM Token Acknowledge Enable Bit + * | | |The NYET/ACK will be returned only on a successful LPM transaction if no errors in both the EXT token and the LPM token and a valid bLinkState = 0001 (L1) is received, else ERROR and STALL will be returned automatically, respectively. + * | | |0= The valid LPM Token will be NYET. + * | | |1= The valid LPM Token will be ACK. + * |[12] |L1SUSPEND |LPM L1 Suspend (Read Only) + * | | |0 = Bus no L1 state suspend. + * | | |1 = This bit is set by the hardware when LPM command to enter the L1 state is successfully received and acknowledged. + * |[13] |L1RESUME |LPM L1 Resume (Read Only) + * | | |0 = Bus no LPM L1 state resume. + * | | |1 = LPM L1 state resume from LPM L1 state suspend. + * @var USBD_T::VBUSDET + * Offset: 0x14 USB Device VBUS Detection Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |VBUSDET |Device VBUS Detection + * | | |0 = Controller is not attached to the USB host. + * | | |1 = Controller is attached to the USB host. + * @var USBD_T::STBUFSEG + * Offset: 0x18 SETUP Token Buffer Segmentation Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[8:3] |STBUFSEG |SETUP Token Buffer Segmentation + * | | |It is used to indicate the offset address for the SETUP token with the USB Device SRAM starting address The effective starting address is + * | | |USBD_SRAM address + {STBUFSEG, 3'b000} + * | | |Where the USBD_SRAM address = USBD_BA+0x100h. + * | | |Note: It is used for SETUP token only. + * @var USBD_T::EPSTS0 + * Offset: 0x20 USB Device Endpoint Status Register 0 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[3:0] |EPSTS0 |Endpoint 0 Status + * | | |These bits are used to indicate the current status of this endpoint. + * | | |0000 = In ACK. + * | | |0001 = In NAK. + * | | |0010 = Out Packet Data0 ACK. + * | | |0110 = Out Packet Data1 ACK. + * | | |0111 = Isochronous transfer end. + * |[7:4] |EPSTS1 |Endpoint 1 Status + * | | |These bits are used to indicate the current status of this endpoint. + * | | |0000 = In ACK. + * | | |0001 = In NAK. + * | | |0010 = Out Packet Data0 ACK. + * | | |0110 = Out Packet Data1 ACK. + * | | |0111 = Isochronous transfer end. + * |[11:8] |EPSTS2 |Endpoint 2 Status + * | | |These bits are used to indicate the current status of this endpoint. + * | | |0000 = In ACK. + * | | |0001 = In NAK. + * | | |0010 = Out Packet Data0 ACK. + * | | |0110 = Out Packet Data1 ACK. + * | | |0111 = Isochronous transfer end. + * |[15:12] |EPSTS3 |Endpoint 3 Status + * | | |These bits are used to indicate the current status of this endpoint. + * | | |0000 = In ACK. + * | | |0001 = In NAK. + * | | |0010 = Out Packet Data0 ACK. + * | | |0110 = Out Packet Data1 ACK. + * | | |0111 = Isochronous transfer end. + * |[19:16] |EPSTS4 |Endpoint 4 Status + * | | |These bits are used to indicate the current status of this endpoint. + * | | |0000 = In ACK. + * | | |0001 = In NAK. + * | | |0010 = Out Packet Data0 ACK. + * | | |0110 = Out Packet Data1 ACK. + * | | |0111 = Isochronous transfer end. + * |[23:20] |EPSTS5 |Endpoint 5 Status + * | | |These bits are used to indicate the current status of this endpoint. + * | | |0000 = In ACK. + * | | |0001 = In NAK. + * | | |0010 = Out Packet Data0 ACK. + * | | |0110 = Out Packet Data1 ACK. + * | | |0111 = Isochronous transfer end. + * |[27:24] |EPSTS6 |Endpoint 6 Status + * | | |These bits are used to indicate the current status of this endpoint. + * | | |0000 = In ACK. + * | | |0001 = In NAK. + * | | |0010 = Out Packet Data0 ACK. + * | | |0110 = Out Packet Data1 ACK. + * | | |0111 = Isochronous transfer end. + * |[31:28] |EPSTS7 |Endpoint 7 Status + * | | |These bits are used to indicate the current status of this endpoint. + * | | |0000 = In ACK. + * | | |0001 = In NAK. + * | | |0010 = Out Packet Data0 ACK. + * | | |0110 = Out Packet Data1 ACK. + * | | |0111 = Isochronous transfer end. + * @var USBD_T::EPSTS1 + * Offset: 0x24 USB Device Endpoint Status Register 1 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[3:0] |EPSTS8 |Endpoint 8 Status + * | | |These bits are used to indicate the current status of this endpoint. + * | | |0000 = In ACK. + * | | |0001 = In NAK. + * | | |0010 = Out Packet Data0 ACK. + * | | |0110 = Out Packet Data1 ACK. + * | | |0111 = Isochronous transfer end. + * |[7:4] |EPSTS9 |Endpoint 9 Status + * | | |These bits are used to indicate the current status of this endpoint. + * | | |0000 = In ACK. + * | | |0001 = In NAK. + * | | |0010 = Out Packet Data0 ACK. + * | | |0110 = Out Packet Data1 ACK. + * | | |0111 = Isochronous transfer end. + * |[11:8] |EPSTS10 |Endpoint 10 Status + * | | |These bits are used to indicate the current status of this endpoint. + * | | |0000 = In ACK. + * | | |0001 = In NAK. + * | | |0010 = Out Packet Data0 ACK. + * | | |0110 = Out Packet Data1 ACK. + * | | |0111 = Isochronous transfer end. + * |[15:12] |EPSTS11 |Endpoint 11 Status + * | | |These bits are used to indicate the current status of this endpoint. + * | | |0000 = In ACK. + * | | |0001 = In NAK. + * | | |0010 = Out Packet Data0 ACK. + * | | |0110 = Out Packet Data1 ACK. + * | | |0111 = Isochronous transfer end. + * @var USBD_T::LPMATTR + * Offset: 0x88 USB LPM Attribution Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[3:0] |LPMLINKSTS|LPM Link State + * | | |These bits contain the bLinkState received with last ACK LPM Token. + * | | |0000 = Reserve. + * | | |0001 = L1 (Sleep). + * | | |0010 - 1111 = Reserve. + * |[7:4] |LPMBESL |LPM Best Effort Service Latency + * | | |These bits contain the BESL value received with last ACK LPM Token. + * | | |0000 = 125us. + * | | |0001 = 150us. + * | | |0010 = 200us. + * | | |0011 = 300us. + * | | |0100 = 400us. + * | | |0101 = 500us. + * | | |0110 = 1000us. + * | | |0111 = 2000us. + * | | |1000 = 3000us. + * | | |1001 = 4000us. + * | | |1010 = 5000us. + * | | |1011 = 6000us. + * | | |1100 = 7000us. + * | | |1101 = 8000us. + * | | |1110 = 9000us. + * | | |1111 = 10000us. + * |[8] |LPMRWAKUP |LPM Remote Wakeup + * | | |This bit contains the bRemoteWake value received with last ACK LPM Token. + * @var USBD_T::FN + * Offset: 0x8C USB Frame Number Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[10:0] |FN |Frame Number + * | | |These bits contain the 11-bits frame number in the last received SOF packet. + * @var USBD_T::SE0 + * Offset: 0x90 USB Device Drive SE0 Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |SE0 |Drive Single Ended Zero in USB Bus + * | | |The Single Ended Zero (SE0) is when both lines (USB_D+ and USB_D-) are being pulled low. + * | | |0 = Normal operation. + * | | |1 = Force USB PHY transceiver to drive SE0. + */ + __IO uint32_t INTEN; /*!< [0x0000] USB Device Interrupt Enable Register */ + __IO uint32_t INTSTS; /*!< [0x0004] USB Device Interrupt Event Status Register */ + __IO uint32_t FADDR; /*!< [0x0008] USB Device Function Address Register */ + __I uint32_t EPSTS; /*!< [0x000c] USB Device Endpoint Status Register */ + __IO uint32_t ATTR; /*!< [0x0010] USB Device Bus Status and Attribution Register */ + __I uint32_t VBUSDET; /*!< [0x0014] USB Device VBUS Detection Register */ + __IO uint32_t STBUFSEG; /*!< [0x0018] SETUP Token Buffer Segmentation Register */ + __I uint32_t RESERVE0[1]; + __I uint32_t EPSTS0; /*!< [0x0020] USB Device Endpoint Status Register 0 */ + __I uint32_t EPSTS1; /*!< [0x0024] USB Device Endpoint Status Register 1 */ + __I uint32_t RESERVE1[24]; + __I uint32_t LPMATTR; /*!< [0x0088] USB LPM Attribution Register */ + __I uint32_t FN; /*!< [0x008c] USB Frame Number Register */ + __IO uint32_t SE0; /*!< [0x0090] USB Device Drive SE0 Control Register */ + __I uint32_t RESERVE2[283]; + USBD_EP_T EP[12]; /*!< [0x500~0x5bc] USB End Point 0 ~ 11 Configuration Register */ + +} USBD_T; + +/** + @addtogroup USBD_CONST USBD Bit Field Definition + Constant Definitions for USBD Controller + @{ +*/ + +#define USBD_INTEN_BUSIEN_Pos (0) /*!< USBD_T::INTEN: BUSIEN Position */ +#define USBD_INTEN_BUSIEN_Msk (0x1ul << USBD_INTEN_BUSIEN_Pos) /*!< USBD_T::INTEN: BUSIEN Mask */ + +#define USBD_INTEN_USBIEN_Pos (1) /*!< USBD_T::INTEN: USBIEN Position */ +#define USBD_INTEN_USBIEN_Msk (0x1ul << USBD_INTEN_USBIEN_Pos) /*!< USBD_T::INTEN: USBIEN Mask */ + +#define USBD_INTEN_VBDETIEN_Pos (2) /*!< USBD_T::INTEN: VBDETIEN Position */ +#define USBD_INTEN_VBDETIEN_Msk (0x1ul << USBD_INTEN_VBDETIEN_Pos) /*!< USBD_T::INTEN: VBDETIEN Mask */ + +#define USBD_INTEN_NEVWKIEN_Pos (3) /*!< USBD_T::INTEN: NEVWKIEN Position */ +#define USBD_INTEN_NEVWKIEN_Msk (0x1ul << USBD_INTEN_NEVWKIEN_Pos) /*!< USBD_T::INTEN: NEVWKIEN Mask */ + +#define USBD_INTEN_SOFIEN_Pos (4) /*!< USBD_T::INTEN: SOFIEN Position */ +#define USBD_INTEN_SOFIEN_Msk (0x1ul << USBD_INTEN_SOFIEN_Pos) /*!< USBD_T::INTEN: SOFIEN Mask */ + +#define USBD_INTEN_WKEN_Pos (8) /*!< USBD_T::INTEN: WKEN Position */ +#define USBD_INTEN_WKEN_Msk (0x1ul << USBD_INTEN_WKEN_Pos) /*!< USBD_T::INTEN: WKEN Mask */ + +#define USBD_INTEN_INNAKEN_Pos (15) /*!< USBD_T::INTEN: INNAKEN Position */ +#define USBD_INTEN_INNAKEN_Msk (0x1ul << USBD_INTEN_INNAKEN_Pos) /*!< USBD_T::INTEN: INNAKEN Mask */ + +#define USBD_INTSTS_BUSIF_Pos (0) /*!< USBD_T::INTSTS: BUSIF Position */ +#define USBD_INTSTS_BUSIF_Msk (0x1ul << USBD_INTSTS_BUSIF_Pos) /*!< USBD_T::INTSTS: BUSIF Mask */ + +#define USBD_INTSTS_USBIF_Pos (1) /*!< USBD_T::INTSTS: USBIF Position */ +#define USBD_INTSTS_USBIF_Msk (0x1ul << USBD_INTSTS_USBIF_Pos) /*!< USBD_T::INTSTS: USBIF Mask */ + +#define USBD_INTSTS_VBDETIF_Pos (2) /*!< USBD_T::INTSTS: VBDETIF Position */ +#define USBD_INTSTS_VBDETIF_Msk (0x1ul << USBD_INTSTS_VBDETIF_Pos) /*!< USBD_T::INTSTS: VBDETIF Mask */ + +#define USBD_INTSTS_NEVWKIF_Pos (3) /*!< USBD_T::INTSTS: NEVWKIF Position */ +#define USBD_INTSTS_NEVWKIF_Msk (0x1ul << USBD_INTSTS_NEVWKIF_Pos) /*!< USBD_T::INTSTS: NEVWKIF Mask */ + +#define USBD_INTSTS_SOFIF_Pos (4) /*!< USBD_T::INTSTS: SOFIF Position */ +#define USBD_INTSTS_SOFIF_Msk (0x1ul << USBD_INTSTS_SOFIF_Pos) /*!< USBD_T::INTSTS: SOFIF Mask */ + +#define USBD_INTSTS_EPEVT0_Pos (16) /*!< USBD_T::INTSTS: EPEVT0 Position */ +#define USBD_INTSTS_EPEVT0_Msk (0x1ul << USBD_INTSTS_EPEVT0_Pos) /*!< USBD_T::INTSTS: EPEVT0 Mask */ + +#define USBD_INTSTS_EPEVT1_Pos (17) /*!< USBD_T::INTSTS: EPEVT1 Position */ +#define USBD_INTSTS_EPEVT1_Msk (0x1ul << USBD_INTSTS_EPEVT1_Pos) /*!< USBD_T::INTSTS: EPEVT1 Mask */ + +#define USBD_INTSTS_EPEVT2_Pos (18) /*!< USBD_T::INTSTS: EPEVT2 Position */ +#define USBD_INTSTS_EPEVT2_Msk (0x1ul << USBD_INTSTS_EPEVT2_Pos) /*!< USBD_T::INTSTS: EPEVT2 Mask */ + +#define USBD_INTSTS_EPEVT3_Pos (19) /*!< USBD_T::INTSTS: EPEVT3 Position */ +#define USBD_INTSTS_EPEVT3_Msk (0x1ul << USBD_INTSTS_EPEVT3_Pos) /*!< USBD_T::INTSTS: EPEVT3 Mask */ + +#define USBD_INTSTS_EPEVT4_Pos (20) /*!< USBD_T::INTSTS: EPEVT4 Position */ +#define USBD_INTSTS_EPEVT4_Msk (0x1ul << USBD_INTSTS_EPEVT4_Pos) /*!< USBD_T::INTSTS: EPEVT4 Mask */ + +#define USBD_INTSTS_EPEVT5_Pos (21) /*!< USBD_T::INTSTS: EPEVT5 Position */ +#define USBD_INTSTS_EPEVT5_Msk (0x1ul << USBD_INTSTS_EPEVT5_Pos) /*!< USBD_T::INTSTS: EPEVT5 Mask */ + +#define USBD_INTSTS_EPEVT6_Pos (22) /*!< USBD_T::INTSTS: EPEVT6 Position */ +#define USBD_INTSTS_EPEVT6_Msk (0x1ul << USBD_INTSTS_EPEVT6_Pos) /*!< USBD_T::INTSTS: EPEVT6 Mask */ + +#define USBD_INTSTS_EPEVT7_Pos (23) /*!< USBD_T::INTSTS: EPEVT7 Position */ +#define USBD_INTSTS_EPEVT7_Msk (0x1ul << USBD_INTSTS_EPEVT7_Pos) /*!< USBD_T::INTSTS: EPEVT7 Mask */ + +#define USBD_INTSTS_EPEVT8_Pos (24) /*!< USBD_T::INTSTS: EPEVT8 Position */ +#define USBD_INTSTS_EPEVT8_Msk (0x1ul << USBD_INTSTS_EPEVT8_Pos) /*!< USBD_T::INTSTS: EPEVT8 Mask */ + +#define USBD_INTSTS_EPEVT9_Pos (25) /*!< USBD_T::INTSTS: EPEVT9 Position */ +#define USBD_INTSTS_EPEVT9_Msk (0x1ul << USBD_INTSTS_EPEVT9_Pos) /*!< USBD_T::INTSTS: EPEVT9 Mask */ + +#define USBD_INTSTS_EPEVT10_Pos (26) /*!< USBD_T::INTSTS: EPEVT10 Position */ +#define USBD_INTSTS_EPEVT10_Msk (0x1ul << USBD_INTSTS_EPEVT10_Pos) /*!< USBD_T::INTSTS: EPEVT10 Mask */ + +#define USBD_INTSTS_EPEVT11_Pos (27) /*!< USBD_T::INTSTS: EPEVT11 Position */ +#define USBD_INTSTS_EPEVT11_Msk (0x1ul << USBD_INTSTS_EPEVT11_Pos) /*!< USBD_T::INTSTS: EPEVT11 Mask */ + +#define USBD_INTSTS_SETUP_Pos (31) /*!< USBD_T::INTSTS: SETUP Position */ +#define USBD_INTSTS_SETUP_Msk (0x1ul << USBD_INTSTS_SETUP_Pos) /*!< USBD_T::INTSTS: SETUP Mask */ + +#define USBD_FADDR_FADDR_Pos (0) /*!< USBD_T::FADDR: FADDR Position */ +#define USBD_FADDR_FADDR_Msk (0x7ful << USBD_FADDR_FADDR_Pos) /*!< USBD_T::FADDR: FADDR Mask */ + +#define USBD_EPSTS_OV_Pos (7) /*!< USBD_T::EPSTS: OV Position */ +#define USBD_EPSTS_OV_Msk (0x1ul << USBD_EPSTS_OV_Pos) /*!< USBD_T::EPSTS: OV Mask */ + +#define USBD_ATTR_USBRST_Pos (0) /*!< USBD_T::ATTR: USBRST Position */ +#define USBD_ATTR_USBRST_Msk (0x1ul << USBD_ATTR_USBRST_Pos) /*!< USBD_T::ATTR: USBRST Mask */ + +#define USBD_ATTR_SUSPEND_Pos (1) /*!< USBD_T::ATTR: SUSPEND Position */ +#define USBD_ATTR_SUSPEND_Msk (0x1ul << USBD_ATTR_SUSPEND_Pos) /*!< USBD_T::ATTR: SUSPEND Mask */ + +#define USBD_ATTR_RESUME_Pos (2) /*!< USBD_T::ATTR: RESUME Position */ +#define USBD_ATTR_RESUME_Msk (0x1ul << USBD_ATTR_RESUME_Pos) /*!< USBD_T::ATTR: RESUME Mask */ + +#define USBD_ATTR_TOUT_Pos (3) /*!< USBD_T::ATTR: TOUT Position */ +#define USBD_ATTR_TOUT_Msk (0x1ul << USBD_ATTR_TOUT_Pos) /*!< USBD_T::ATTR: TOUT Mask */ + +#define USBD_ATTR_PHYEN_Pos (4) /*!< USBD_T::ATTR: PHYEN Position */ +#define USBD_ATTR_PHYEN_Msk (0x1ul << USBD_ATTR_PHYEN_Pos) /*!< USBD_T::ATTR: PHYEN Mask */ + +#define USBD_ATTR_RWAKEUP_Pos (5) /*!< USBD_T::ATTR: RWAKEUP Position */ +#define USBD_ATTR_RWAKEUP_Msk (0x1ul << USBD_ATTR_RWAKEUP_Pos) /*!< USBD_T::ATTR: RWAKEUP Mask */ + +#define USBD_ATTR_USBEN_Pos (7) /*!< USBD_T::ATTR: USBEN Position */ +#define USBD_ATTR_USBEN_Msk (0x1ul << USBD_ATTR_USBEN_Pos) /*!< USBD_T::ATTR: USBEN Mask */ + +#define USBD_ATTR_DPPUEN_Pos (8) /*!< USBD_T::ATTR: DPPUEN Position */ +#define USBD_ATTR_DPPUEN_Msk (0x1ul << USBD_ATTR_DPPUEN_Pos) /*!< USBD_T::ATTR: DPPUEN Mask */ + +#define USBD_ATTR_BYTEM_Pos (10) /*!< USBD_T::ATTR: BYTEM Position */ +#define USBD_ATTR_BYTEM_Msk (0x1ul << USBD_ATTR_BYTEM_Pos) /*!< USBD_T::ATTR: BYTEM Mask */ + +#define USBD_ATTR_LPMACK_Pos (11) /*!< USBD_T::ATTR: LPMACK Position */ +#define USBD_ATTR_LPMACK_Msk (0x1ul << USBD_ATTR_LPMACK_Pos) /*!< USBD_T::ATTR: LPMACK Mask */ + +#define USBD_ATTR_L1SUSPEND_Pos (12) /*!< USBD_T::ATTR: L1SUSPEND Position */ +#define USBD_ATTR_L1SUSPEND_Msk (0x1ul << USBD_ATTR_L1SUSPEND_Pos) /*!< USBD_T::ATTR: L1SUSPEND Mask */ + +#define USBD_ATTR_L1RESUME_Pos (13) /*!< USBD_T::ATTR: L1RESUME Position */ +#define USBD_ATTR_L1RESUME_Msk (0x1ul << USBD_ATTR_L1RESUME_Pos) /*!< USBD_T::ATTR: L1RESUME Mask */ + +#define USBD_VBUSDET_VBUSDET_Pos (0) /*!< USBD_T::VBUSDET: VBUSDET Position */ +#define USBD_VBUSDET_VBUSDET_Msk (0x1ul << USBD_VBUSDET_VBUSDET_Pos) /*!< USBD_T::VBUSDET: VBUSDET Mask */ + +#define USBD_STBUFSEG_STBUFSEG_Pos (3) /*!< USBD_T::STBUFSEG: STBUFSEG Position */ +#define USBD_STBUFSEG_STBUFSEG_Msk (0x3ful << USBD_STBUFSEG_STBUFSEG_Pos) /*!< USBD_T::STBUFSEG: STBUFSEG Mask */ + +#define USBD_EPSTS0_EPSTS0_Pos (0) /*!< USBD_T::EPSTS0: EPSTS0 Position */ +#define USBD_EPSTS0_EPSTS0_Msk (0xful << USBD_EPSTS0_EPSTS0_Pos) /*!< USBD_T::EPSTS0: EPSTS0 Mask */ + +#define USBD_EPSTS0_EPSTS1_Pos (4) /*!< USBD_T::EPSTS0: EPSTS1 Position */ +#define USBD_EPSTS0_EPSTS1_Msk (0xful << USBD_EPSTS0_EPSTS1_Pos) /*!< USBD_T::EPSTS0: EPSTS1 Mask */ + +#define USBD_EPSTS0_EPSTS2_Pos (8) /*!< USBD_T::EPSTS0: EPSTS2 Position */ +#define USBD_EPSTS0_EPSTS2_Msk (0xful << USBD_EPSTS0_EPSTS2_Pos) /*!< USBD_T::EPSTS0: EPSTS2 Mask */ + +#define USBD_EPSTS0_EPSTS3_Pos (12) /*!< USBD_T::EPSTS0: EPSTS3 Position */ +#define USBD_EPSTS0_EPSTS3_Msk (0xful << USBD_EPSTS0_EPSTS3_Pos) /*!< USBD_T::EPSTS0: EPSTS3 Mask */ + +#define USBD_EPSTS0_EPSTS4_Pos (16) /*!< USBD_T::EPSTS0: EPSTS4 Position */ +#define USBD_EPSTS0_EPSTS4_Msk (0xful << USBD_EPSTS0_EPSTS4_Pos) /*!< USBD_T::EPSTS0: EPSTS4 Mask */ + +#define USBD_EPSTS0_EPSTS5_Pos (20) /*!< USBD_T::EPSTS0: EPSTS5 Position */ +#define USBD_EPSTS0_EPSTS5_Msk (0xful << USBD_EPSTS0_EPSTS5_Pos) /*!< USBD_T::EPSTS0: EPSTS5 Mask */ + +#define USBD_EPSTS0_EPSTS6_Pos (24) /*!< USBD_T::EPSTS0: EPSTS6 Position */ +#define USBD_EPSTS0_EPSTS6_Msk (0xful << USBD_EPSTS0_EPSTS6_Pos) /*!< USBD_T::EPSTS0: EPSTS6 Mask */ + +#define USBD_EPSTS0_EPSTS7_Pos (28) /*!< USBD_T::EPSTS0: EPSTS7 Position */ +#define USBD_EPSTS0_EPSTS7_Msk (0xful << USBD_EPSTS0_EPSTS7_Pos) /*!< USBD_T::EPSTS0: EPSTS7 Mask */ + +#define USBD_EPSTS1_EPSTS8_Pos (0) /*!< USBD_T::EPSTS1: EPSTS8 Position */ +#define USBD_EPSTS1_EPSTS8_Msk (0xful << USBD_EPSTS1_EPSTS8_Pos) /*!< USBD_T::EPSTS1: EPSTS8 Mask */ + +#define USBD_EPSTS1_EPSTS9_Pos (4) /*!< USBD_T::EPSTS1: EPSTS9 Position */ +#define USBD_EPSTS1_EPSTS9_Msk (0xful << USBD_EPSTS1_EPSTS9_Pos) /*!< USBD_T::EPSTS1: EPSTS9 Mask */ + +#define USBD_EPSTS1_EPSTS10_Pos (8) /*!< USBD_T::EPSTS1: EPSTS10 Position */ +#define USBD_EPSTS1_EPSTS10_Msk (0xful << USBD_EPSTS1_EPSTS10_Pos) /*!< USBD_T::EPSTS1: EPSTS10 Mask */ + +#define USBD_EPSTS1_EPSTS11_Pos (12) /*!< USBD_T::EPSTS1: EPSTS11 Position */ +#define USBD_EPSTS1_EPSTS11_Msk (0xful << USBD_EPSTS1_EPSTS11_Pos) /*!< USBD_T::EPSTS1: EPSTS11 Mask */ + +#define USBD_LPMATTR_LPMLINKSTS_Pos (0) /*!< USBD_T::LPMATTR: LPMLINKSTS Position */ +#define USBD_LPMATTR_LPMLINKSTS_Msk (0xful << USBD_LPMATTR_LPMLINKSTS_Pos) /*!< USBD_T::LPMATTR: LPMLINKSTS Mask */ + +#define USBD_LPMATTR_LPMBESL_Pos (4) /*!< USBD_T::LPMATTR: LPMBESL Position */ +#define USBD_LPMATTR_LPMBESL_Msk (0xful << USBD_LPMATTR_LPMBESL_Pos) /*!< USBD_T::LPMATTR: LPMBESL Mask */ + +#define USBD_LPMATTR_LPMRWAKUP_Pos (8) /*!< USBD_T::LPMATTR: LPMRWAKUP Position */ +#define USBD_LPMATTR_LPMRWAKUP_Msk (0x1ul << USBD_LPMATTR_LPMRWAKUP_Pos) /*!< USBD_T::LPMATTR: LPMRWAKUP Mask */ + +#define USBD_FN_FN_Pos (0) /*!< USBD_T::FN: FN Position */ +#define USBD_FN_FN_Msk (0x7fful << USBD_FN_FN_Pos) /*!< USBD_T::FN: FN Mask */ + +#define USBD_SE0_SE0_Pos (0) /*!< USBD_T::SE0: SE0 Position */ +#define USBD_SE0_SE0_Msk (0x1ul << USBD_SE0_SE0_Pos) /*!< USBD_T::SE0: SE0 Mask */ + +#define USBD_BUFSEG_BUFSEG_Pos (3) /*!< USBD_EP_T::BUFSEG: BUFSEG Position */ +#define USBD_BUFSEG_BUFSEG_Msk (0x3ful << USBD_BUFSEG_BUFSEG_Pos) /*!< USBD_EP_T::BUFSEG: BUFSEG Mask */ + +#define USBD_MXPLD_MXPLD_Pos (0) /*!< USBD_EP_T::MXPLD: MXPLD Position */ +#define USBD_MXPLD_MXPLD_Msk (0x1fful << USBD_MXPLD_MXPLD_Pos) /*!< USBD_EP_T::MXPLD: MXPLD Mask */ + +#define USBD_CFG_EPNUM_Pos (0) /*!< USBD_EP_T::CFG: EPNUM Position */ +#define USBD_CFG_EPNUM_Msk (0xful << USBD_CFG_EPNUM_Pos) /*!< USBD_EP_T::CFG: EPNUM Mask */ + +#define USBD_CFG_ISOCH_Pos (4) /*!< USBD_EP_T::CFG: ISOCH Position */ +#define USBD_CFG_ISOCH_Msk (0x1ul << USBD_CFG_ISOCH_Pos) /*!< USBD_EP_T::CFG: ISOCH Mask */ + +#define USBD_CFG_STATE_Pos (5) /*!< USBD_EP_T::CFG: STATE Position */ +#define USBD_CFG_STATE_Msk (0x3ul << USBD_CFG_STATE_Pos) /*!< USBD_EP_T::CFG: STATE Mask */ + +#define USBD_CFG_DSQSYNC_Pos (7) /*!< USBD_EP_T::CFG: DSQSYNC Position */ +#define USBD_CFG_DSQSYNC_Msk (0x1ul << USBD_CFG_DSQSYNC_Pos) /*!< USBD_EP_T::CFG: DSQSYNC Mask */ + +#define USBD_CFG_CSTALL_Pos (9) /*!< USBD_EP_T::CFG: CSTALL Position */ +#define USBD_CFG_CSTALL_Msk (0x1ul << USBD_CFG_CSTALL_Pos) /*!< USBD_EP_T::CFG: CSTALL Mask */ + +#define USBD_CFG_DBTGACTIVE_Pos (10) /*!< USBD_EP_T::CFG: DBTGACTIVE Position */ +#define USBD_CFG_DBTGACTIVE_Msk (0x1ul << USBD_CFG_DBTGACTIVE_Pos) /*!< USBD_EP_T::CFG: DBTGACTIVE Mask */ + +#define USBD_CFG_DBEN_Pos (11) /*!< USBD_EP_T::CFG: DBEN Position */ +#define USBD_CFG_DBEN_Msk (0x1ul << USBD_CFG_DBEN_Pos) /*!< USBD_EP_T::CFG: DBEN Mask */ + +#define USBD_CFGP_CLRRDY_Pos (0) /*!< USBD_EP_T::CFGP: CLRRDY Position */ +#define USBD_CFGP_CLRRDY_Msk (0x1ul << USBD_CFGP_CLRRDY_Pos) /*!< USBD_EP_T::CFGP: CLRRDY Mask */ + +#define USBD_CFGP_SSTALL_Pos (1) /*!< USBD_EP_T::CFGP: SSTALL Position */ +#define USBD_CFGP_SSTALL_Msk (0x1ul << USBD_CFGP_SSTALL_Pos) /*!< USBD_EP_T::CFGP: SSTALL Mask */ + +/**@}*/ /* USBD_CONST */ +/**@}*/ /* end of USBD register group */ +/**@}*/ /* end of REGISTER group */ + +#endif /* __USBD_REG_H__ */ diff --git a/Ubiquitous/XiZi/board/nuvoton-m2354/third_party_driver/include/Regs/usbh_reg.h b/Ubiquitous/XiZi/board/nuvoton-m2354/third_party_driver/include/Regs/usbh_reg.h new file mode 100644 index 0000000..38df8f4 --- /dev/null +++ b/Ubiquitous/XiZi/board/nuvoton-m2354/third_party_driver/include/Regs/usbh_reg.h @@ -0,0 +1,799 @@ +/**************************************************************************//** + * @file usbh_reg.h + * @version V1.00 + * @brief USBH register definition header file + * + * @copyright SPDX-License-Identifier: Apache-2.0 + * @copyright Copyright (C) 2020 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ +#ifndef __USBH_REG_H__ +#define __USBH_REG_H__ + +/** @addtogroup REGISTER Control Register + + @{ + +*/ + +/*---------------------- USB Host Controller -------------------------*/ +/** + @addtogroup USBH USB Host Controller(USBH) + Memory Mapped Structure for USBH Controller + @{ +*/ + +typedef struct +{ + + + /** + * @var USBH_T::HcRevision + * Offset: 0x00 Host Controller Revision Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[7:0] |REV |Revision Number + * | | |Indicates the Open HCI Specification revision number implemented by the Hardware + * | | |Host Controller supports 1.1 specification. + * | | |(X.Y = XYh). + * @var USBH_T::HcControl + * Offset: 0x04 Host Controller Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[1:0] |CBSR |Control Bulk Service Ratio + * | | |This specifies the service ratio between Control and Bulk EDs + * | | |Before processing any of the non-periodic lists, HC must compare the ratio specified with its internal count on how many nonempty Control EDs have been processed, in determining whether to continue serving another Control ED or switching to Bulk EDs + * | | |The internal count will be retained when crossing the frame boundary + * | | |In case of reset, HCD is responsible for restoring this value. + * | | |00 = Number of Control EDs over Bulk EDs served is 1:1. + * | | |01 = Number of Control EDs over Bulk EDs served is 2:1. + * | | |10 = Number of Control EDs over Bulk EDs served is 3:1. + * | | |11 = Number of Control EDs over Bulk EDs served is 4:1. + * |[2] |PLE |Periodic List Enable Bit + * | | |When set, this bit enables processing of the Periodic (interrupt and isochronous) list + * | | |The Host Controller checks this bit prior to attempting any periodic transfers in a frame. + * | | |0 = Processing of the Periodic (Interrupt and Isochronous) list after next SOF (Start-Of-Frame) Disabled. + * | | |1 = Processing of the Periodic (Interrupt and Isochronous) list in the next frame Enabled. + * | | |Note: To enable the processing of the Isochronous list, user has to set both PLE and IE (HcControl[3]) high. + * |[3] |IE |Isochronous List Enable Bit + * | | |Both IE and PLE (HcControl[2]) high enables Host Controller to process the Isochronous list + * | | |Either IE or PLE (HcControl[2]) is low disables Host Controller to process the Isochronous list. + * | | |0 = Processing of the Isochronous list after next SOF (Start-Of-Frame) Disabled. + * | | |1 = Processing of the Isochronous list in the next frame Enabled, if the PLE (HcControl[2]) is high, too. + * |[4] |CLE |Control List Enable Bit + * | | |0 = Processing of the Control list after next SOF (Start-Of-Frame) Disabled. + * | | |1 = Processing of the Control list in the next frame Enabled. + * |[5] |BLE |Bulk List Enable Bit + * | | |0 = Processing of the Bulk list after next SOF (Start-Of-Frame) Disabled. + * | | |1 = Processing of the Bulk list in the next frame Enabled. + * |[7:6] |HCFS |Host Controller Functional State + * | | |This field sets the Host Controller state + * | | |The Controller may force a state change from USBSUSPEND to USBRESUME after detecting resume signaling from a downstream port + * | | |States are: + * | | |00 = USBRESET. + * | | |01 = USBRESUME. + * | | |10 = USBOPERATIONAL. + * | | |11 = USBSUSPEND. + * @var USBH_T::HcCommandStatus + * Offset: 0x08 Host Controller Command Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |HCR |Host Controller Reset + * | | |This bit is set to initiate the software reset of Host Controller + * | | |This bit is cleared by the Host Controller, upon completed of the reset operation. + * | | |This bit, when set, didn't reset the Root Hub and no subsequent reset signaling be asserted to its downstream ports. + * | | |0 = Host Controller is not in software reset state. + * | | |1 = Host Controller is in software reset state. + * |[1] |CLF |Control List Filled + * | | |Set high to indicate there is an active TD on the Control List + * | | |It may be set by either software or the Host Controller and cleared by the Host Controller each time it begins processing the head of the Control List. + * | | |0 = No active TD found or Host Controller begins to process the head of the Control list. + * | | |1 = An active TD added or found on the Control list. + * |[2] |BLF |Bulk List Filled + * | | |Set high to indicate there is an active TD on the Bulk list + * | | |This bit may be set by either software or the Host Controller and cleared by the Host Controller each time it begins processing the head of the Bulk list. + * | | |0 = No active TD found or Host Controller begins to process the head of the Bulk list. + * | | |1 = An active TD added or found on the Bulk list. + * |[17:16] |SOC |Schedule Overrun Count (Read-Only) + * | | |These bits are incremented on each scheduling overrun error + * | | |It is initialized to 00b and wraps around at 11b + * | | |This will be incremented when a scheduling overrun is detected even if SO (HcInterruptStatus[0]) has already been set. + * @var USBH_T::HcInterruptStatus + * Offset: 0x0C Host Controller Interrupt Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |SO |Scheduling Overrun + * | | |Set when the List Processor determines a Schedule Overrun has occurred. + * | | |0 = Schedule Overrun didn't occur. + * | | |1 = Schedule Overrun has occurred. + * | | |Note: This bit is cleared by writing 1 to it. + * |[1] |WDH |Write Back Done Head + * | | |Set after the Host Controller has written HcDoneHead to HccaDoneHead + * | | |Further updates of the HccaDoneHead will not occur until this bit has been cleared. + * | | |0 = Host Controller didn't update HccaDoneHead. + * | | |1 = Host Controller has written HcDoneHead to HccaDoneHead. + * | | |Note: This bit is cleared by writing 1 to it. + * |[2] |SF |Start of Frame + * | | |Set when the Frame Management functional block signals a u2018Start of Frame' event + * | | |Host Control generates a SOF token at the same time. + * | | |0 = Not the start of a frame. + * | | |1 = Indicate the start of a frame and Host Controller generates a SOF token. + * | | |Note: This bit is cleared by writing 1 to it. + * |[3] |RD |Resume Detected + * | | |Set when Host Controller detects resume signaling on a downstream port. + * | | |0 = No resume signaling detected on a downstream port. + * | | |1 = Resume signaling detected on a downstream port. + * | | |Note: This bit is cleared by writing 1 to it. + * |[5] |FNO |Frame Number Overflow + * | | |This bit is set when bit 15 of Frame Number changes from 1 to 0 or from 0 to 1. + * | | |0 = The bit 15 of Frame Number didn't change. + * | | |1 = The bit 15 of Frame Number changes from 1 to 0 or from 0 to 1. + * | | |Note: This bit is cleared by writing 1 to it. + * |[6] |RHSC |Root Hub Status Change + * | | |This bit is set when the content of HcRhStatus or the content of HcRhPortStatus register has changed. + * | | |0 = The content of HcRhStatus and the content of HcRhPortStatus register didn't change. + * | | |1 = The content of HcRhStatus or the content of HcRhPortStatus register has changed. + * | | |Note: This bit is cleared by writing ‘1Fh’ to HcRhPortStatus1[20:16]. + * @var USBH_T::HcInterruptEnable + * Offset: 0x10 Host Controller Interrupt Enable Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |SO |Scheduling Overrun Enable Bit + * | | |Write Operation: + * | | |0 = No effect. + * | | |1 = Interrupt generation due to SO (HcInterruptStatus[0]) Enabled. + * | | |Read Operation: + * | | |0 = Interrupt generation due to SO (HcInterruptStatus[0]) Disabled. + * | | |1 = Interrupt generation due to SO (HcInterruptStatus[0]) Enabled. + * |[1] |WDH |Write Back Done Head Enable Bit + * | | |Write Operation: + * | | |0 = No effect. + * | | |1 = Interrupt generation due to WDH (HcInterruptStatus[1]) Enabled. + * | | |Read Operation: + * | | |0 = Interrupt generation due to WDH (HcInterruptStatus[1]) Disabled. + * | | |1 = Interrupt generation due to WDH (HcInterruptStatus[1]) Enabled. + * |[2] |SF |Start of Frame Enable Bit + * | | |Write Operation: + * | | |0 = No effect. + * | | |1 = Interrupt generation due to SF (HcInterruptStatus[2]) Enabled. + * | | |Read Operation: + * | | |0 = Interrupt generation due to SF (HcInterruptStatus[2]) Disabled. + * | | |1 = Interrupt generation due to SF (HcInterruptStatus[2]) Enabled. + * |[3] |RD |Resume Detected Enable Bit + * | | |Write Operation: + * | | |0 = No effect. + * | | |1 = Interrupt generation due to RD (HcInterruptStatus[3]) Enabled. + * | | |Read Operation: + * | | |0 = Interrupt generation due to RD (HcInterruptStatus[3]) Disabled. + * | | |1 = Interrupt generation due to RD (HcInterruptStatus[3]) Enabled. + * |[5] |FNO |Frame Number Overflow Enable Bit + * | | |Write Operation: + * | | |0 = No effect. + * | | |1 = Interrupt generation due to FNO (HcInterruptStatus[5]) Enabled. + * | | |Read Operation: + * | | |0 = Interrupt generation due to FNO (HcInterruptStatus[5]) Disabled. + * | | |1 = Interrupt generation due to FNO (HcInterruptStatus[5]) Enabled. + * |[6] |RHSC |Root Hub Status Change Enable Bit + * | | |Write Operation: + * | | |0 = No effect. + * | | |1 = Interrupt generation due to RHSC (HcInterruptStatus[6]) Enabled. + * | | |Read Operation: + * | | |0 = Interrupt generation due to RHSC (HcInterruptStatus[6]) Disabled. + * | | |1 = Interrupt generation due to RHSC (HcInterruptStatus[6]) Enabled. + * |[31] |MIE |Master Interrupt Enable Bit + * | | |This bit is a global interrupt enable + * | | |A write of u20181' allows interrupts to be enabled via the specific enable bits listed above. + * | | |Write Operation: + * | | |0 = No effect. + * | | |1 = Interrupt generation due to RHSC (HcInterruptStatus[6]), FNO (HcInterruptStatus[5]), RD (HcInterruptStatus[3]), SF (HcInterruptStatus[2]), WDH (HcInterruptStatus[1]) or SO (HcInterruptStatus[0]) Enabled if the corresponding bit in HcInterruptEnable is high. + * | | |Read Operation: + * | | |0 = Interrupt generation due to RHSC (HcInterruptStatus[6]), FNO (HcInterruptStatus[5]), RD (HcInterruptStatus[3]), SF (HcInterruptStatus[2]), WDH (HcInterruptStatus[1]) or SO (HcInterruptStatus[0]) Disabled even if the corresponding bit in HcInterruptEnable is high. + * | | |1 = Interrupt generation due to RHSC (HcInterruptStatus[6]), FNO (HcInterruptStatus[5]), RD (HcInterruptStatus[3]), SF (HcInterruptStatus[2]), WDH (HcInterruptStatus[1]) or SO (HcInterruptStatus[0]) Enabled if the corresponding bit in HcInterruptEnable is high. + * @var USBH_T::HcInterruptDisable + * Offset: 0x14 Host Controller Interrupt Disable Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |SO |Scheduling Overrun Disable Bit + * | | |Write Operation: + * | | |0 = No effect. + * | | |1 = Interrupt generation due to SO (HcInterruptStatus[0]) Disabled. + * | | |Read Operation: + * | | |0 = Interrupt generation due to SO (HcInterruptStatus[0]) Disabled. + * | | |1 = Interrupt generation due to SO (HcInterruptStatus[0]) Enabled. + * |[1] |WDH |Write Back Done Head Disable Bit + * | | |Write Operation: + * | | |0 = No effect. + * | | |1 = Interrupt generation due to WDH (HcInterruptStatus[1]) Disabled. + * | | |Read Operation: + * | | |0 = Interrupt generation due to WDH (HcInterruptStatus[1]) Disabled. + * | | |1 = Interrupt generation due to WDH (HcInterruptStatus[1]) Enabled. + * |[2] |SF |Start of Frame Disable Bit + * | | |Write Operation: + * | | |0 = No effect. + * | | |1 = Interrupt generation due to SF (HcInterruptStatus[2]) Disabled. + * | | |Read Operation: + * | | |0 = Interrupt generation due to SF (HcInterruptStatus[2]) Disabled. + * | | |1 = Interrupt generation due to SF (HcInterruptStatus[2]) Enabled. + * |[3] |RD |Resume Detected Disable Bit + * | | |Write Operation: + * | | |0 = No effect. + * | | |1 = Interrupt generation due to RD (HcInterruptStatus[3]) Disabled. + * | | |Read Operation: + * | | |0 = Interrupt generation due to RD (HcInterruptStatus[3]) Disabled. + * | | |1 = Interrupt generation due to RD (HcInterruptStatus[3]) Enabled. + * |[5] |FNO |Frame Number Overflow Disable Bit + * | | |Write Operation: + * | | |0 = No effect. + * | | |1 = Interrupt generation due to FNO (HcInterruptStatus[5]) Disabled. + * | | |Read Operation: + * | | |0 = Interrupt generation due to FNO (HcInterruptStatus[5]) Disabled. + * | | |1 = Interrupt generation due to FNO (HcInterruptStatus[5]) Enabled. + * |[6] |RHSC |Root Hub Status Change Disable Bit + * | | |Write Operation: + * | | |0 = No effect. + * | | |1 = Interrupt generation due to RHSC (HcInterruptStatus[6]) Disabled. + * | | |Read Operation: + * | | |0 = Interrupt generation due to RHSC (HcInterruptStatus[6]) Disabled. + * | | |1 = Interrupt generation due to RHSC (HcInterruptStatus[6]) Enabled. + * |[31] |MIE |Master Interrupt Disable Bit + * | | |Global interrupt disable. Writing u20181' to disable all interrupts. + * | | |Write Operation: + * | | |0 = No effect. + * | | |1 = Interrupt generation due to RHSC (HcInterruptStatus[6]), FNO (HcInterruptStatus[5]), RD (HcInterruptStatus[3]), SF (HcInterruptStatus[2]), WDH (HcInterruptStatus[1]) or SO (HcInterruptStatus[0]) Disabled if the corresponding bit in HcInterruptEnable is high. + * | | |Read Operation: + * | | |0 = Interrupt generation due to RHSC (HcInterruptStatus[6]), FNO (HcInterruptStatus[5]), RD (HcInterruptStatus[3]), SF (HcInterruptStatus[2]), WDH (HcInterruptStatus[1]) or SO (HcInterruptStatus[0]) Disabled even if the corresponding bit in HcInterruptEnable is high. + * | | |1 = Interrupt generation due to RHSC (HcInterruptStatus[6]), FNO (HcInterruptStatus[5]), RD (HcInterruptStatus[3]), SF (HcInterruptStatus[2]), WDH (HcInterruptStatus[1]) or SO (HcInterruptStatus[0]) Enabled if the corresponding bit in HcInterruptEnable is high. + * @var USBH_T::HcHCCA + * Offset: 0x18 Host Controller Communication Area Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:8] |HCCA |Host Controller Communication Area + * | | |Pointer to indicate the base address of the Host Controller Communication Area (HCCA). + * @var USBH_T::HcPeriodCurrentED + * Offset: 0x1C Host Controller Period Current ED Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:4] |PCED |Periodic Current ED + * | | |Pointer to indicate the physical address of the current Isochronous or Interrupt Endpoint Descriptor. + * @var USBH_T::HcControlHeadED + * Offset: 0x20 Host Controller Control ED Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:4] |CHED |Control Head ED + * | | |Pointer to indicate the physical address of the first Endpoint Descriptor of the Control list. + * @var USBH_T::HcControlCurrentED + * Offset: 0x24 Host Controller Control Current ED Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:4] |CCED |Control Current Head ED + * | | |Pointer to indicate the physical address of the current Endpoint Descriptor of the Control list. + * @var USBH_T::HcBulkHeadED + * Offset: 0x28 Host Controller Bulk Head ED Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:4] |BHED |Bulk Head ED + * | | |Pointer to indicate the physical address of the first Endpoint Descriptor of the Bulk list. + * @var USBH_T::HcBulkCurrentED + * Offset: 0x2C Host Controller Bulk Current ED Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:4] |BCED |Bulk Current Head ED + * | | |Pointer to indicate the physical address of the current endpoint of the Bulk list. + * @var USBH_T::HcDoneHead + * Offset: 0x30 Host Controller Done Head Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:4] |DH |Done Head + * | | |Pointer to indicate the physical address of the last completed Transfer Descriptor that was added to the Done queue. + * @var USBH_T::HcFmInterval + * Offset: 0x34 Host Controller Frame Interval Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[13:0] |FI |Frame Interval + * | | |This field specifies the length of a frame as (bit times - 1) + * | | |For 12,000 bit times in a frame, a value of 11,999 is stored here. + * |[29:16] |FSMPS |FS Largest Data Packet + * | | |This field specifies a value that is loaded into the Largest Data Packet Counter at the beginning of each frame. + * |[31] |FIT |Frame Interval Toggle + * | | |This bit is toggled by Host Controller Driver when it loads a new value into FI (HcFmInterval[13:0]). + * | | |0 = Host Controller Driver didn't load new value into FI (HcFmInterval[13:0]). + * | | |1 = Host Controller Driver loads a new value into FI (HcFmInterval[13:0]). + * @var USBH_T::HcFmRemaining + * Offset: 0x38 Host Controller Frame Remaining Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[13:0] |FR |Frame Remaining + * | | |When the Host Controller is in the USBOPERATIONAL state, this 14-bit field decrements each 12 MHz clock period + * | | |When the count reaches 0, (end of frame) the counter reloads with Frame Interval + * | | |In addition, the counter loads when the Host Controller transitions into USBOPERATIONAL. + * |[31] |FRT |Frame Remaining Toggle + * | | |This bit is loaded from the FIT (HcFmInterval[31]) whenever FR (HcFmRemaining[13:0]) reaches 0. + * @var USBH_T::HcFmNumber + * Offset: 0x3C Host Controller Frame Number Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |FN |Frame Number + * | | |This 16-bit incrementing counter field is incremented coincident with the re-load of FR (HcFmRemaining[13:0]) + * | | |The count rolls over from u2018FFFFh' to u20180h.' + * @var USBH_T::HcPeriodicStart + * Offset: 0x40 Host Controller Periodic Start Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[13:0] |PS |Periodic Start + * | | |This field contains a value used by the List Processor to determine where in a frame the Periodic List processing must begin. + * @var USBH_T::HcLSThreshold + * Offset: 0x44 Host Controller Low-speed Threshold Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[11:0] |LST |Low-speed Threshold + * | | |This field contains a value which is compared to the FR (HcFmRemaining[13:0]) field prior to initiating a Low-speed transaction + * | | |The transaction is started only if FR (HcFmRemaining[13:0]) >= this field + * | | |The value is calculated by Host Controller Driver with the consideration of transmission and setup overhead. + * @var USBH_T::HcRhDescriptorA + * Offset: 0x48 Host Controller Root Hub Descriptor A Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[7:0] |NDP |Number Downstream Ports + * | | |USB host control supports two downstream ports and only one port is available in this series of chip. + * | | |Note: NDP = 1 in this series of chip. + * |[8] |PSM |Power Switching Mode + * | | |This bit is used to specify how the power switching of the Root Hub ports is controlled. + * | | |0 = Global switching. + * | | |1 = Individual switching. + * |[11] |OCPM |Over Current Protection Mode + * | | |This bit describes how the over current status for the Root Hub ports reported + * | | |This bit is only valid when NOCP (HcRhDescriptorA[12]) is cleared. + * | | |0 = Global over current. + * | | |1 = Individual over current. + * |[12] |NOCP |No Over Current Protection + * | | |This bit describes how the over current status for the Root Hub ports reported. + * | | |0 = Over current status is reported. + * | | |1 = Over current status is not reported. + * @var USBH_T::HcRhDescriptorB + * Offset: 0x4C Host Controller Root Hub Descriptor B Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:16] |PPCM |Port Power Control Mask + * | | |Global power switching + * | | |This field is only valid if Power Switching Mode is set (individual port switching) + * | | |When set, the port only responds to individual port power switching commands (Set/Clear Port Power) + * | | |When cleared, the port only responds to global power switching commands (Set/Clear Global Power). + * | | |0 = Port power controlled by global power switching. + * | | |1 = Port power controlled by port power switching. + * | | |Note: PPCM[15:2] and PPCM[0] are reserved. + * @var USBH_T::HcRhStatus + * Offset: 0x50 Host Controller Root Hub Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |LPS |Clear Global Power + * | | |In global power mode (PSM (HcRhDescriptorA[8]) = 0), this bit is written to one to clear all ports' power. + * | | |This bit always read as zero. + * | | |Write Operation: + * | | |0 = No effect. + * | | |1 = Clear global power. + * |[1] |OCI |Over Current Indicator (Read-Only) + * | | |This bit reflects the state of the over current status pin + * | | |This field is only valid if NOCP (HcRhDescriptorA[12]) and OCPM (HcRhDescriptorA[11]) are cleared. + * | | |0 = No over current condition. + * | | |1 = Over current condition. + * |[15] |DRWE |Device Remote Wakeup Enable Bit + * | | |This bit controls if port's Connect Status Change as a remote wake-up event. + * | | |Write Operation: + * | | |0 = No effect. + * | | |1 = Connect Status Change as a remote wake-up event Enabled. + * | | |Read Operation: + * | | |0 = Connect Status Change as a remote wake-up event Disabled. + * | | |1 = Connect Status Change as a remote wake-up event Enabled. + * |[16] |LPSC |Set Global Power + * | | |In global power mode (PSM (HcRhDescriptorA[8]) = 0), this bit is written to one to enable power to all ports. + * | | |This bit always read as zero. + * | | |Write Operation: + * | | |0 = No effect. + * | | |1 = Set global power. + * |[17] |OCIC |Over Current Indicator Change + * | | |This bit is set by hardware when a change has occurred in OCI (HcRhStatus[1]). + * | | |Write 1 to clear this bit to zero. + * | | |0 = OCI (HcRhStatus[1]) didn't change. + * | | |1 = OCI (HcRhStatus[1]) change. + * |[31] |CRWE |Clear Remote Wake-up Enable Bit + * | | |This bit is use to clear DRWE (HcRhStatus[15]). + * | | |This bit always read as zero. + * | | |Write Operation: + * | | |0 = No effect. + * | | |1 = Clear DRWE (HcRhStatus[15]). + * @var USBH_T::HcRhPortStatus[2] + * Offset: 0x54 Host Controller Root Hub Port Status + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |CCS |Current Connect Status (Read) or Clear Port Enable (Write) + * | | |Write Operation: + * | | |0 = No effect. + * | | |1 = Clear port enable. + * | | |Read Operation: + * | | |0 = No device connected. + * | | |1 = Device connected. + * |[1] |PES |Port Enable Status (Read) or Set Port Enable (Write) + * | | |Write Operation: + * | | |0 = No effect. + * | | |1 = Set port enable. + * | | |Read Operation: + * | | |0 = Port Disabled. + * | | |1 = Port Enabled. + * |[2] |PSS |Port Suspend Status (Read) or Set Port Suspend (Write) + * | | |This bit indicates the port is suspended + * | | |Write Operation: + * | | |0 = No effect. + * | | |1 = Set port suspend. + * | | |Read Operation: + * | | |0 = Port is not suspended. + * | | |1 = Port is selectively suspended. + * |[3] |POCI |Port Over Current Indicator (Read) or Clear Port Suspend (Write) + * | | |This bit reflects the state of the over current status pin dedicated to this port + * | | |This field is only valid if NOCP (HcRhDescriptorA[12]) is cleared and OCPM (HcRhDescriptorA[11]) is set. + * | | |This bit is also used to initiate the selective result sequence for the port. + * | | |Write Operation: + * | | |0 = No effect. + * | | |1 = Clear port suspend. + * | | |Read Operation: + * | | |0 = No over current condition. + * | | |1 = Over current condition. + * |[4] |PRS |Port Reset Status (Read) or Set Port Reset (Write) + * | | |This bit reflects the reset state of the port. + * | | |Write Operation: + * | | |0 = No effect. + * | | |1 = Set port reset. + * | | |Read Operation + * | | |0 = Port reset signal is not active. + * | | |1 = Port reset signal is active. + * |[8] |PPS |Port Power Status (Read) or Set Port Power (Write) + * | | |This bit reflects the power state of the port regardless of the power switching mode. + * | | |Write Operation: + * | | |0 = No effect. + * | | |1 = Port Power Enabled. + * | | |Read Operation: + * | | |0 = Port power is Disabled. + * | | |1 = Port power is Enabled. + * |[9] |LSDA |Low Speed Device Attached (Read) or Clear Port Power (Write) + * | | |This bit defines the speed (and bus idle) of the attached device + * | | |It is only valid when CCS (HcRhPortStatus[0]) is set. + * | | |This bit is also used to clear port power. + * | | |Write Operation: + * | | |0 = No effect. + * | | |1 = Clear PPS (HcRhPortStatus[8]). + * | | |Read Operation: + * | | |0 = Full Speed device. + * | | |1 = Low-speed device. + * |[16] |CSC |Connect Status Change + * | | |This bit indicates connect or disconnect event has been detected (CCS (HcRhPortStatus[0]) changed). + * | | |Write 1 to clear this bit to zero. + * | | |0 = No connect/disconnect event (CCS (HcRhPortStatus[0]) didn't change). + * | | |1 = Hardware detection of connect/disconnect event (CCS (HcRhPortStatus[0]) changed). + * |[17] |PESC |Port Enable Status Change + * | | |This bit indicates that the port has been disabled (PES (HcRhPortStatus[1]) cleared) due to a hardware event. + * | | |Write 1 to clear this bit to zero. + * | | |0 = PES (HcRhPortStatus[1]) didn't change. + * | | |1 = PES (HcRhPortStatus[1]) changed. + * |[18] |PSSC |Port Suspend Status Change + * | | |This bit indicates the completion of the selective resume sequence for the port. + * | | |Write 1 to clear this bit to zero. + * | | |0 = Port resume is not complete. + * | | |1 = Port resume complete. + * |[19] |OCIC |Port Over Current Indicator Change + * | | |This bit is set when POCI (HcRhPortStatus[3]) changes. + * | | |Write 1 to clear this bit to zero. + * | | |0 = POCI (HcRhPortStatus[3]) didn't change. + * | | |1 = POCI (HcRhPortStatus[3]) changes. + * |[20] |PRSC |Port Reset Status Change + * | | |This bit indicates that the port reset signal has completed. + * | | |Write 1 to clear this bit to zero. + * | | |0 = Port reset is not complete. + * | | |1 = Port reset is complete. + * @var USBH_T::HcPhyControl + * Offset: 0x200 Host Controller PHY Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[27] |STBYEN |USB Transceiver Standby Enable Bit + * | | |This bit controls if USB transceiver could enter the standby mode to reduce power consumption. + * | | |0 = The USB transceiver would never enter the standby mode. + * | | |1 = The USB transceiver will enter standby mode while port is in power off state (port power is inactive). + * @var USBH_T::HcMiscControl + * Offset: 0x204 Host Controller Miscellaneous Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[1] |ABORT |AHB Bus Error Response + * | | |This bit indicates there is an Error response received in AHB bus. + * | | |0 = No Error response received. + * | | |1 = Error response received. + * | | |Note: This bit is cleared by writing 1 to it. + * |[3] |OCAL |over Current Active Low + * | | |This bit controls the polarity of over current flag from external power IC. + * | | |0 = Over current flag is high active. + * | | |1 = Over current flag is low active. + * |[16] |DPRT1 |Disable Port 1 + * | | |This bit controls if the connection between USB host controller and transceiver of port 1 is disabled + * | | |If the connection is disabled, the USB host controller will not recognize any event of USB bus. + * | | |Set this bit high, the transceiver of port 1 will also be forced into the standby mode no matter what USB host controller operation is. + * | | |0 = The connection between USB host controller and transceiver of port 1 Enabled. + * | | |1 = The connection between USB host controller and transceiver of port 1 Disabled and the transceiver of port 1 will also be forced into the standby mode. + */ + __I uint32_t HcRevision; /*!< [0x0000] Host Controller Revision Register */ + __IO uint32_t HcControl; /*!< [0x0004] Host Controller Control Register */ + __IO uint32_t HcCommandStatus; /*!< [0x0008] Host Controller Command Status Register */ + __IO uint32_t HcInterruptStatus; /*!< [0x000c] Host Controller Interrupt Status Register */ + __IO uint32_t HcInterruptEnable; /*!< [0x0010] Host Controller Interrupt Enable Register */ + __IO uint32_t HcInterruptDisable; /*!< [0x0014] Host Controller Interrupt Disable Register */ + __IO uint32_t HcHCCA; /*!< [0x0018] Host Controller Communication Area Register */ + __IO uint32_t HcPeriodCurrentED; /*!< [0x001c] Host Controller Period Current ED Register */ + __IO uint32_t HcControlHeadED; /*!< [0x0020] Host Controller Control Head ED Register */ + __IO uint32_t HcControlCurrentED; /*!< [0x0024] Host Controller Control Current ED Register */ + __IO uint32_t HcBulkHeadED; /*!< [0x0028] Host Controller Bulk Head ED Register */ + __IO uint32_t HcBulkCurrentED; /*!< [0x002c] Host Controller Bulk Current ED Register */ + __IO uint32_t HcDoneHead; /*!< [0x0030] Host Controller Done Head Register */ + __IO uint32_t HcFmInterval; /*!< [0x0034] Host Controller Frame Interval Register */ + __I uint32_t HcFmRemaining; /*!< [0x0038] Host Controller Frame Remaining Register */ + __I uint32_t HcFmNumber; /*!< [0x003c] Host Controller Frame Number Register */ + __IO uint32_t HcPeriodicStart; /*!< [0x0040] Host Controller Periodic Start Register */ + __IO uint32_t HcLSThreshold; /*!< [0x0044] Host Controller Low-speed Threshold Register */ + __IO uint32_t HcRhDescriptorA; /*!< [0x0048] Host Controller Root Hub Descriptor A Register */ + __IO uint32_t HcRhDescriptorB; /*!< [0x004c] Host Controller Root Hub Descriptor B Register */ + __IO uint32_t HcRhStatus; /*!< [0x0050] Host Controller Root Hub Status Register */ + __IO uint32_t HcRhPortStatus[2]; /*!< [0x0054] Host Controller Root Hub Port Status */ + __I uint32_t RESERVE0[105]; + __IO uint32_t HcPhyControl; /*!< [0x0200] Host Controller PHY Control Register */ + __IO uint32_t HcMiscControl; /*!< [0x0204] Host Controller Miscellaneous Control Register */ + +} USBH_T; + +/** + @addtogroup USBH_CONST USBH Bit Field Definition + Constant Definitions for USBH Controller + @{ +*/ + +#define USBH_HcRevision_REV_Pos (0) /*!< USBH_T::HcRevision: REV Position */ +#define USBH_HcRevision_REV_Msk (0xfful << USBH_HcRevision_REV_Pos) /*!< USBH_T::HcRevision: REV Mask */ + +#define USBH_HcControl_CBSR_Pos (0) /*!< USBH_T::HcControl: CBSR Position */ +#define USBH_HcControl_CBSR_Msk (0x3ul << USBH_HcControl_CBSR_Pos) /*!< USBH_T::HcControl: CBSR Mask */ + +#define USBH_HcControl_PLE_Pos (2) /*!< USBH_T::HcControl: PLE Position */ +#define USBH_HcControl_PLE_Msk (0x1ul << USBH_HcControl_PLE_Pos) /*!< USBH_T::HcControl: PLE Mask */ + +#define USBH_HcControl_IE_Pos (3) /*!< USBH_T::HcControl: IE Position */ +#define USBH_HcControl_IE_Msk (0x1ul << USBH_HcControl_IE_Pos) /*!< USBH_T::HcControl: IE Mask */ + +#define USBH_HcControl_CLE_Pos (4) /*!< USBH_T::HcControl: CLE Position */ +#define USBH_HcControl_CLE_Msk (0x1ul << USBH_HcControl_CLE_Pos) /*!< USBH_T::HcControl: CLE Mask */ + +#define USBH_HcControl_BLE_Pos (5) /*!< USBH_T::HcControl: BLE Position */ +#define USBH_HcControl_BLE_Msk (0x1ul << USBH_HcControl_BLE_Pos) /*!< USBH_T::HcControl: BLE Mask */ + +#define USBH_HcControl_HCFS_Pos (6) /*!< USBH_T::HcControl: HCFS Position */ +#define USBH_HcControl_HCFS_Msk (0x3ul << USBH_HcControl_HCFS_Pos) /*!< USBH_T::HcControl: HCFS Mask */ + +#define USBH_HcCommandStatus_HCR_Pos (0) /*!< USBH_T::HcCommandStatus: HCR Position */ +#define USBH_HcCommandStatus_HCR_Msk (0x1ul << USBH_HcCommandStatus_HCR_Pos) /*!< USBH_T::HcCommandStatus: HCR Mask */ + +#define USBH_HcCommandStatus_CLF_Pos (1) /*!< USBH_T::HcCommandStatus: CLF Position */ +#define USBH_HcCommandStatus_CLF_Msk (0x1ul << USBH_HcCommandStatus_CLF_Pos) /*!< USBH_T::HcCommandStatus: CLF Mask */ + +#define USBH_HcCommandStatus_BLF_Pos (2) /*!< USBH_T::HcCommandStatus: BLF Position */ +#define USBH_HcCommandStatus_BLF_Msk (0x1ul << USBH_HcCommandStatus_BLF_Pos) /*!< USBH_T::HcCommandStatus: BLF Mask */ + +#define USBH_HcCommandStatus_SOC_Pos (16) /*!< USBH_T::HcCommandStatus: SOC Position */ +#define USBH_HcCommandStatus_SOC_Msk (0x3ul << USBH_HcCommandStatus_SOC_Pos) /*!< USBH_T::HcCommandStatus: SOC Mask */ + +#define USBH_HcInterruptStatus_SO_Pos (0) /*!< USBH_T::HcInterruptStatus: SO Position */ +#define USBH_HcInterruptStatus_SO_Msk (0x1ul << USBH_HcInterruptStatus_SO_Pos) /*!< USBH_T::HcInterruptStatus: SO Mask */ + +#define USBH_HcInterruptStatus_WDH_Pos (1) /*!< USBH_T::HcInterruptStatus: WDH Position*/ +#define USBH_HcInterruptStatus_WDH_Msk (0x1ul << USBH_HcInterruptStatus_WDH_Pos) /*!< USBH_T::HcInterruptStatus: WDH Mask */ + +#define USBH_HcInterruptStatus_SF_Pos (2) /*!< USBH_T::HcInterruptStatus: SF Position */ +#define USBH_HcInterruptStatus_SF_Msk (0x1ul << USBH_HcInterruptStatus_SF_Pos) /*!< USBH_T::HcInterruptStatus: SF Mask */ + +#define USBH_HcInterruptStatus_RD_Pos (3) /*!< USBH_T::HcInterruptStatus: RD Position */ +#define USBH_HcInterruptStatus_RD_Msk (0x1ul << USBH_HcInterruptStatus_RD_Pos) /*!< USBH_T::HcInterruptStatus: RD Mask */ + +#define USBH_HcInterruptStatus_FNO_Pos (5) /*!< USBH_T::HcInterruptStatus: FNO Position*/ +#define USBH_HcInterruptStatus_FNO_Msk (0x1ul << USBH_HcInterruptStatus_FNO_Pos) /*!< USBH_T::HcInterruptStatus: FNO Mask */ + +#define USBH_HcInterruptStatus_RHSC_Pos (6) /*!< USBH_T::HcInterruptStatus: RHSC Position*/ +#define USBH_HcInterruptStatus_RHSC_Msk (0x1ul << USBH_HcInterruptStatus_RHSC_Pos) /*!< USBH_T::HcInterruptStatus: RHSC Mask */ + +#define USBH_HcInterruptEnable_SO_Pos (0) /*!< USBH_T::HcInterruptEnable: SO Position */ +#define USBH_HcInterruptEnable_SO_Msk (0x1ul << USBH_HcInterruptEnable_SO_Pos) /*!< USBH_T::HcInterruptEnable: SO Mask */ + +#define USBH_HcInterruptEnable_WDH_Pos (1) /*!< USBH_T::HcInterruptEnable: WDH Position*/ +#define USBH_HcInterruptEnable_WDH_Msk (0x1ul << USBH_HcInterruptEnable_WDH_Pos) /*!< USBH_T::HcInterruptEnable: WDH Mask */ + +#define USBH_HcInterruptEnable_SF_Pos (2) /*!< USBH_T::HcInterruptEnable: SF Position */ +#define USBH_HcInterruptEnable_SF_Msk (0x1ul << USBH_HcInterruptEnable_SF_Pos) /*!< USBH_T::HcInterruptEnable: SF Mask */ + +#define USBH_HcInterruptEnable_RD_Pos (3) /*!< USBH_T::HcInterruptEnable: RD Position */ +#define USBH_HcInterruptEnable_RD_Msk (0x1ul << USBH_HcInterruptEnable_RD_Pos) /*!< USBH_T::HcInterruptEnable: RD Mask */ + +#define USBH_HcInterruptEnable_FNO_Pos (5) /*!< USBH_T::HcInterruptEnable: FNO Position*/ +#define USBH_HcInterruptEnable_FNO_Msk (0x1ul << USBH_HcInterruptEnable_FNO_Pos) /*!< USBH_T::HcInterruptEnable: FNO Mask */ + +#define USBH_HcInterruptEnable_RHSC_Pos (6) /*!< USBH_T::HcInterruptEnable: RHSC Position*/ +#define USBH_HcInterruptEnable_RHSC_Msk (0x1ul << USBH_HcInterruptEnable_RHSC_Pos) /*!< USBH_T::HcInterruptEnable: RHSC Mask */ + +#define USBH_HcInterruptEnable_MIE_Pos (31) /*!< USBH_T::HcInterruptEnable: MIE Position*/ +#define USBH_HcInterruptEnable_MIE_Msk (0x1ul << USBH_HcInterruptEnable_MIE_Pos) /*!< USBH_T::HcInterruptEnable: MIE Mask */ + +#define USBH_HcInterruptDisable_SO_Pos (0) /*!< USBH_T::HcInterruptDisable: SO Position*/ +#define USBH_HcInterruptDisable_SO_Msk (0x1ul << USBH_HcInterruptDisable_SO_Pos) /*!< USBH_T::HcInterruptDisable: SO Mask */ + +#define USBH_HcInterruptDisable_WDH_Pos (1) /*!< USBH_T::HcInterruptDisable: WDH Position*/ +#define USBH_HcInterruptDisable_WDH_Msk (0x1ul << USBH_HcInterruptDisable_WDH_Pos) /*!< USBH_T::HcInterruptDisable: WDH Mask */ + +#define USBH_HcInterruptDisable_SF_Pos (2) /*!< USBH_T::HcInterruptDisable: SF Position*/ +#define USBH_HcInterruptDisable_SF_Msk (0x1ul << USBH_HcInterruptDisable_SF_Pos) /*!< USBH_T::HcInterruptDisable: SF Mask */ + +#define USBH_HcInterruptDisable_RD_Pos (3) /*!< USBH_T::HcInterruptDisable: RD Position*/ +#define USBH_HcInterruptDisable_RD_Msk (0x1ul << USBH_HcInterruptDisable_RD_Pos) /*!< USBH_T::HcInterruptDisable: RD Mask */ + +#define USBH_HcInterruptDisable_FNO_Pos (5) /*!< USBH_T::HcInterruptDisable: FNO Position*/ +#define USBH_HcInterruptDisable_FNO_Msk (0x1ul << USBH_HcInterruptDisable_FNO_Pos) /*!< USBH_T::HcInterruptDisable: FNO Mask */ + +#define USBH_HcInterruptDisable_RHSC_Pos (6) /*!< USBH_T::HcInterruptDisable: RHSC Position*/ +#define USBH_HcInterruptDisable_RHSC_Msk (0x1ul << USBH_HcInterruptDisable_RHSC_Pos) /*!< USBH_T::HcInterruptDisable: RHSC Mask */ + +#define USBH_HcInterruptDisable_MIE_Pos (31) /*!< USBH_T::HcInterruptDisable: MIE Position*/ +#define USBH_HcInterruptDisable_MIE_Msk (0x1ul << USBH_HcInterruptDisable_MIE_Pos) /*!< USBH_T::HcInterruptDisable: MIE Mask */ + +#define USBH_HcHCCA_HCCA_Pos (8) /*!< USBH_T::HcHCCA: HCCA Position */ +#define USBH_HcHCCA_HCCA_Msk (0xfffffful << USBH_HcHCCA_HCCA_Pos) /*!< USBH_T::HcHCCA: HCCA Mask */ + +#define USBH_HcPeriodCurrentED_PCED_Pos (4) /*!< USBH_T::HcPeriodCurrentED: PCED Position*/ +#define USBH_HcPeriodCurrentED_PCED_Msk (0xffffffful << USBH_HcPeriodCurrentED_PCED_Pos) /*!< USBH_T::HcPeriodCurrentED: PCED Mask */ + +#define USBH_HcControlHeadED_CHED_Pos (4) /*!< USBH_T::HcControlHeadED: CHED Position */ +#define USBH_HcControlHeadED_CHED_Msk (0xffffffful << USBH_HcControlHeadED_CHED_Pos) /*!< USBH_T::HcControlHeadED: CHED Mask */ + +#define USBH_HcControlCurrentED_CCED_Pos (4) /*!< USBH_T::HcControlCurrentED: CCED Position*/ +#define USBH_HcControlCurrentED_CCED_Msk (0xffffffful << USBH_HcControlCurrentED_CCED_Pos) /*!< USBH_T::HcControlCurrentED: CCED Mask */ + +#define USBH_HcBulkHeadED_BHED_Pos (4) /*!< USBH_T::HcBulkHeadED: BHED Position */ +#define USBH_HcBulkHeadED_BHED_Msk (0xffffffful << USBH_HcBulkHeadED_BHED_Pos) /*!< USBH_T::HcBulkHeadED: BHED Mask */ + +#define USBH_HcBulkCurrentED_BCED_Pos (4) /*!< USBH_T::HcBulkCurrentED: BCED Position */ +#define USBH_HcBulkCurrentED_BCED_Msk (0xffffffful << USBH_HcBulkCurrentED_BCED_Pos) /*!< USBH_T::HcBulkCurrentED: BCED Mask */ + +#define USBH_HcDoneHead_DH_Pos (4) /*!< USBH_T::HcDoneHead: DH Position */ +#define USBH_HcDoneHead_DH_Msk (0xffffffful << USBH_HcDoneHead_DH_Pos) /*!< USBH_T::HcDoneHead: DH Mask */ + +#define USBH_HcFmInterval_FI_Pos (0) /*!< USBH_T::HcFmInterval: FI Position */ +#define USBH_HcFmInterval_FI_Msk (0x3ffful << USBH_HcFmInterval_FI_Pos) /*!< USBH_T::HcFmInterval: FI Mask */ + +#define USBH_HcFmInterval_FSMPS_Pos (16) /*!< USBH_T::HcFmInterval: FSMPS Position */ +#define USBH_HcFmInterval_FSMPS_Msk (0x3ffful << USBH_HcFmInterval_FSMPS_Pos) /*!< USBH_T::HcFmInterval: FSMPS Mask */ + +#define USBH_HcFmInterval_FIT_Pos (31) /*!< USBH_T::HcFmInterval: FIT Position */ +#define USBH_HcFmInterval_FIT_Msk (0x1ul << USBH_HcFmInterval_FIT_Pos) /*!< USBH_T::HcFmInterval: FIT Mask */ + +#define USBH_HcFmRemaining_FR_Pos (0) /*!< USBH_T::HcFmRemaining: FR Position */ +#define USBH_HcFmRemaining_FR_Msk (0x3ffful << USBH_HcFmRemaining_FR_Pos) /*!< USBH_T::HcFmRemaining: FR Mask */ + +#define USBH_HcFmRemaining_FRT_Pos (31) /*!< USBH_T::HcFmRemaining: FRT Position */ +#define USBH_HcFmRemaining_FRT_Msk (0x1ul << USBH_HcFmRemaining_FRT_Pos) /*!< USBH_T::HcFmRemaining: FRT Mask */ + +#define USBH_HcFmNumber_FN_Pos (0) /*!< USBH_T::HcFmNumber: FN Position */ +#define USBH_HcFmNumber_FN_Msk (0xfffful << USBH_HcFmNumber_FN_Pos) /*!< USBH_T::HcFmNumber: FN Mask */ + +#define USBH_HcPeriodicStart_PS_Pos (0) /*!< USBH_T::HcPeriodicStart: PS Position */ +#define USBH_HcPeriodicStart_PS_Msk (0x3ffful << USBH_HcPeriodicStart_PS_Pos) /*!< USBH_T::HcPeriodicStart: PS Mask */ + +#define USBH_HcLSThreshold_LST_Pos (0) /*!< USBH_T::HcLSThreshold: LST Position */ +#define USBH_HcLSThreshold_LST_Msk (0xffful << USBH_HcLSThreshold_LST_Pos) /*!< USBH_T::HcLSThreshold: LST Mask */ + +#define USBH_HcRhDescriptorA_NDP_Pos (0) /*!< USBH_T::HcRhDescriptorA: NDP Position */ +#define USBH_HcRhDescriptorA_NDP_Msk (0xfful << USBH_HcRhDescriptorA_NDP_Pos) /*!< USBH_T::HcRhDescriptorA: NDP Mask */ + +#define USBH_HcRhDescriptorA_PSM_Pos (8) /*!< USBH_T::HcRhDescriptorA: PSM Position */ +#define USBH_HcRhDescriptorA_PSM_Msk (0x1ul << USBH_HcRhDescriptorA_PSM_Pos) /*!< USBH_T::HcRhDescriptorA: PSM Mask */ + +#define USBH_HcRhDescriptorA_OCPM_Pos (11) /*!< USBH_T::HcRhDescriptorA: OCPM Position */ +#define USBH_HcRhDescriptorA_OCPM_Msk (0x1ul << USBH_HcRhDescriptorA_OCPM_Pos) /*!< USBH_T::HcRhDescriptorA: OCPM Mask */ + +#define USBH_HcRhDescriptorA_NOCP_Pos (12) /*!< USBH_T::HcRhDescriptorA: NOCP Position */ +#define USBH_HcRhDescriptorA_NOCP_Msk (0x1ul << USBH_HcRhDescriptorA_NOCP_Pos) /*!< USBH_T::HcRhDescriptorA: NOCP Mask */ + +#define USBH_HcRhDescriptorB_PPCM_Pos (16) /*!< USBH_T::HcRhDescriptorB: PPCM Position */ +#define USBH_HcRhDescriptorB_PPCM_Msk (0xfffful << USBH_HcRhDescriptorB_PPCM_Pos) /*!< USBH_T::HcRhDescriptorB: PPCM Mask */ + +#define USBH_HcRhStatus_LPS_Pos (0) /*!< USBH_T::HcRhStatus: LPS Position */ +#define USBH_HcRhStatus_LPS_Msk (0x1ul << USBH_HcRhStatus_LPS_Pos) /*!< USBH_T::HcRhStatus: LPS Mask */ + +#define USBH_HcRhStatus_OCI_Pos (1) /*!< USBH_T::HcRhStatus: OCI Position */ +#define USBH_HcRhStatus_OCI_Msk (0x1ul << USBH_HcRhStatus_OCI_Pos) /*!< USBH_T::HcRhStatus: OCI Mask */ + +#define USBH_HcRhStatus_DRWE_Pos (15) /*!< USBH_T::HcRhStatus: DRWE Position */ +#define USBH_HcRhStatus_DRWE_Msk (0x1ul << USBH_HcRhStatus_DRWE_Pos) /*!< USBH_T::HcRhStatus: DRWE Mask */ + +#define USBH_HcRhStatus_LPSC_Pos (16) /*!< USBH_T::HcRhStatus: LPSC Position */ +#define USBH_HcRhStatus_LPSC_Msk (0x1ul << USBH_HcRhStatus_LPSC_Pos) /*!< USBH_T::HcRhStatus: LPSC Mask */ + +#define USBH_HcRhStatus_OCIC_Pos (17) /*!< USBH_T::HcRhStatus: OCIC Position */ +#define USBH_HcRhStatus_OCIC_Msk (0x1ul << USBH_HcRhStatus_OCIC_Pos) /*!< USBH_T::HcRhStatus: OCIC Mask */ + +#define USBH_HcRhStatus_CRWE_Pos (31) /*!< USBH_T::HcRhStatus: CRWE Position */ +#define USBH_HcRhStatus_CRWE_Msk (0x1ul << USBH_HcRhStatus_CRWE_Pos) /*!< USBH_T::HcRhStatus: CRWE Mask */ + +#define USBH_HcRhPortStatus_CCS_Pos (0) /*!< USBH_T::HcRhPortStatus: CCS Position */ +#define USBH_HcRhPortStatus_CCS_Msk (0x1ul << USBH_HcRhPortStatus_CCS_Pos) /*!< USBH_T::HcRhPortStatus: CCS Mask */ + +#define USBH_HcRhPortStatus_PES_Pos (1) /*!< USBH_T::HcRhPortStatus: PES Position */ +#define USBH_HcRhPortStatus_PES_Msk (0x1ul << USBH_HcRhPortStatus_PES_Pos) /*!< USBH_T::HcRhPortStatus: PES Mask */ + +#define USBH_HcRhPortStatus_PSS_Pos (2) /*!< USBH_T::HcRhPortStatus: PSS Position */ +#define USBH_HcRhPortStatus_PSS_Msk (0x1ul << USBH_HcRhPortStatus_PSS_Pos) /*!< USBH_T::HcRhPortStatus: PSS Mask */ + +#define USBH_HcRhPortStatus_POCI_Pos (3) /*!< USBH_T::HcRhPortStatus: POCI Position */ +#define USBH_HcRhPortStatus_POCI_Msk (0x1ul << USBH_HcRhPortStatus_POCI_Pos) /*!< USBH_T::HcRhPortStatus: POCI Mask */ + +#define USBH_HcRhPortStatus_PRS_Pos (4) /*!< USBH_T::HcRhPortStatus: PRS Position */ +#define USBH_HcRhPortStatus_PRS_Msk (0x1ul << USBH_HcRhPortStatus_PRS_Pos) /*!< USBH_T::HcRhPortStatus: PRS Mask */ + +#define USBH_HcRhPortStatus_PPS_Pos (8) /*!< USBH_T::HcRhPortStatus: PPS Position */ +#define USBH_HcRhPortStatus_PPS_Msk (0x1ul << USBH_HcRhPortStatus_PPS_Pos) /*!< USBH_T::HcRhPortStatus: PPS Mask */ + +#define USBH_HcRhPortStatus_LSDA_Pos (9) /*!< USBH_T::HcRhPortStatus: LSDA Position */ +#define USBH_HcRhPortStatus_LSDA_Msk (0x1ul << USBH_HcRhPortStatus_LSDA_Pos) /*!< USBH_T::HcRhPortStatus: LSDA Mask */ + +#define USBH_HcRhPortStatus_CSC_Pos (16) /*!< USBH_T::HcRhPortStatus: CSC Position */ +#define USBH_HcRhPortStatus_CSC_Msk (0x1ul << USBH_HcRhPortStatus_CSC_Pos) /*!< USBH_T::HcRhPortStatus: CSC Mask */ + +#define USBH_HcRhPortStatus_PESC_Pos (17) /*!< USBH_T::HcRhPortStatus: PESC Position */ +#define USBH_HcRhPortStatus_PESC_Msk (0x1ul << USBH_HcRhPortStatus_PESC_Pos) /*!< USBH_T::HcRhPortStatus: PESC Mask */ + +#define USBH_HcRhPortStatus_PSSC_Pos (18) /*!< USBH_T::HcRhPortStatus: PSSC Position */ +#define USBH_HcRhPortStatus_PSSC_Msk (0x1ul << USBH_HcRhPortStatus_PSSC_Pos) /*!< USBH_T::HcRhPortStatus: PSSC Mask */ + +#define USBH_HcRhPortStatus_OCIC_Pos (19) /*!< USBH_T::HcRhPortStatus: OCIC Position */ +#define USBH_HcRhPortStatus_OCIC_Msk (0x1ul << USBH_HcRhPortStatus_OCIC_Pos) /*!< USBH_T::HcRhPortStatus: OCIC Mask */ + +#define USBH_HcRhPortStatus_PRSC_Pos (20) /*!< USBH_T::HcRhPortStatus: PRSC Position */ +#define USBH_HcRhPortStatus_PRSC_Msk (0x1ul << USBH_HcRhPortStatus_PRSC_Pos) /*!< USBH_T::HcRhPortStatus: PRSC Mask */ + +#define USBH_HcPhyControl_STBYEN_Pos (27) /*!< USBH_T::HcPhyControl: STBYEN Position */ +#define USBH_HcPhyControl_STBYEN_Msk (0x1ul << USBH_HcPhyControl_STBYEN_Pos) /*!< USBH_T::HcPhyControl: STBYEN Mask */ + +#define USBH_HcMiscControl_ABORT_Pos (1) /*!< USBH_T::HcMiscControl: ABORT Position */ +#define USBH_HcMiscControl_ABORT_Msk (0x1ul << USBH_HcMiscControl_ABORT_Pos) /*!< USBH_T::HcMiscControl: ABORT Mask */ + +#define USBH_HcMiscControl_OCAL_Pos (3) /*!< USBH_T::HcMiscControl: OCAL Position */ +#define USBH_HcMiscControl_OCAL_Msk (0x1ul << USBH_HcMiscControl_OCAL_Pos) /*!< USBH_T::HcMiscControl: OCAL Mask */ + +#define USBH_HcMiscControl_DPRT1_Pos (16) /*!< USBH_T::HcMiscControl: DPRT1 Position */ +#define USBH_HcMiscControl_DPRT1_Msk (0x1ul << USBH_HcMiscControl_DPRT1_Pos) /*!< USBH_T::HcMiscControl: DPRT1 Mask */ + +/**@}*/ /* USBH_CONST */ +/**@}*/ /* end of USBH register group */ +/**@}*/ /* end of REGISTER group */ + +#endif /* __USBH_REG_H__ */ diff --git a/Ubiquitous/XiZi/board/nuvoton-m2354/third_party_driver/include/Regs/uspi_reg.h b/Ubiquitous/XiZi/board/nuvoton-m2354/third_party_driver/include/Regs/uspi_reg.h new file mode 100644 index 0000000..2d3d530 --- /dev/null +++ b/Ubiquitous/XiZi/board/nuvoton-m2354/third_party_driver/include/Regs/uspi_reg.h @@ -0,0 +1,666 @@ +/**************************************************************************//** + * @file uspi_reg.h + * @version V1.00 + * @brief USPI register definition header file + * + * @copyright SPDX-License-Identifier: Apache-2.0 + * @copyright Copyright (C) 2020 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ +#ifndef __USPI_REG_H__ +#define __USPI_REG_H__ + +/** @addtogroup REGISTER Control Register + + @{ + +*/ + +/*---------------------- SPI Mode of USCI Controller -------------------------*/ +/** + @addtogroup USPI SPI Mode of USCI Controller(USPI) + Memory Mapped Structure for USPI Controller + @{ +*/ + +typedef struct +{ + + + /** + * @var USPI_T::CTL + * Offset: 0x00 USCI Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[2:0] |FUNMODE |Function Mode + * | | |This bit field selects the protocol for this USCI controller + * | | |Selecting a protocol that is not available or a reserved combination disables the USCI + * | | |When switching between two protocols, the USCI has to be disabled before selecting a new protocol + * | | |Simultaneously, the USCI will be reset when user write 000 to FUNMODE. + * | | |000 = The USCI is disabled. All protocol related state machines are set to idle state. + * | | |001 = The SPI protocol is selected. + * | | |010 = The UART protocol is selected. + * | | |100 = The I2C protocol is selected. + * | | |Note: Other bit combinations are reserved. + * @var USPI_T::INTEN + * Offset: 0x04 USCI Interrupt Enable Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[1] |TXSTIEN |Transmit Start Interrupt Enable Bit + * | | |This bit enables the interrupt generation in case of a transmit start event. + * | | |0 = The transmit start interrupt is disabled. + * | | |1 = The transmit start interrupt is enabled. + * |[2] |TXENDIEN |Transmit End Interrupt Enable Bit + * | | |This bit enables the interrupt generation in case of a transmit finish event. + * | | |0 = The transmit finish interrupt is disabled. + * | | |1 = The transmit finish interrupt is enabled. + * |[3] |RXSTIEN |Receive Start Interrupt Enable Bit + * | | |This bit enables the interrupt generation in case of a receive start event. + * | | |0 = The receive start interrupt is disabled. + * | | |1 = The receive start interrupt is enabled. + * |[4] |RXENDIEN |Receive End Interrupt Enable Bit + * | | |This bit enables the interrupt generation in case of a receive finish event. + * | | |0 = The receive end interrupt is disabled. + * | | |1 = The receive end interrupt is enabled. + * @var USPI_T::BRGEN + * Offset: 0x08 USCI Baud Rate Generator Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |RCLKSEL |Reference Clock Source Selection + * | | |This bit selects the source of reference clock (fREF_CLK). + * | | |0 = Peripheral device clock fPCLK. + * | | |1 = Reserved. + * |[1] |PTCLKSEL |Protocol Clock Source Selection + * | | |This bit selects the source of protocol clock (fPROT_CLK). + * | | |0 = Reference clock fREF_CLK. + * | | |1 = fREF_CLK2 (its frequency is half of fREF_CLK). + * |[3:2] |SPCLKSEL |Sample Clock Source Selection + * | | |This bit field used for the clock source selection of sample clock (fSAMP_CLK) for the protocol processor. + * | | |00 = fDIV_CLK. + * | | |01 = fPROT_CLK. + * | | |10 = fSCLK. + * | | |11 = fREF_CLK. + * |[4] |TMCNTEN |Time Measurement Counter Enable Bit + * | | |This bit enables the 10-bit timing measurement counter. + * | | |0 = Time measurement counter is Disabled. + * | | |1 = Time measurement counter is Enabled. + * |[5] |TMCNTSRC |Time Measurement Counter Clock Source Selection + * | | |0 = Time measurement counter with fPROT_CLK. + * | | |1 = Time measurement counter with fDIV_CLK. + * |[25:16] |CLKDIV |Clock Divider + * | | |This bit field defines the ratio between the protocol clock frequency fPROT_CLK and the clock divider frequency fDIV_CLK (fDIV_CLK = fPROT_CLK / (CLKDIV+1) ). + * | | |Note: In UART function, it can be updated by hardware in the 4th falling edge of the input data 0x55 when the auto baud rate function (ABREN(USPI_PROTCTL[6])) is enabled + * | | |The revised value is the average bit time between bit 5 and bit 6 + * | | |The user can use revised CLKDIV and new BRDETITV (USPI_PROTCTL[24:16]) to calculate the precise baud rate. + * @var USPI_T::DATIN0 + * Offset: 0x10 USCI Input Data Signal Configuration Register 0 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |SYNCSEL |Input Signal Synchronization Selection + * | | |This bit selects if the un-synchronized input signal (with optionally inverted) or the synchronized (and optionally filtered) signal can be used as input for the data shift unit. + * | | |0 = The un-synchronized signal can be taken as input for the data shift unit. + * | | |1 = The synchronized signal can be taken as input for the data shift unit. + * | | |Note: In SPI protocol, it is suggested this bit should be set as 0. + * |[2] |ININV |Input Signal Inverse Selection + * | | |This bit defines the inverter enable of the input asynchronous signal. + * | | |0 = The un-synchronized input signal will not be inverted. + * | | |1 = The un-synchronized input signal will be inverted. + * | | |Note: In SPI protocol, it is suggested this bit should be set as 0. + * @var USPI_T::CTLIN0 + * Offset: 0x20 USCI Input Control Signal Configuration Register 0 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |SYNCSEL |Input Synchronization Signal Selection + * | | |This bit selects if the un-synchronized input signal (with optionally inverted) or the synchronized (and optionally filtered) signal can be used as input for the data shift unit. + * | | |0 = The un-synchronized signal can be taken as input for the data shift unit. + * | | |1 = The synchronized signal can be taken as input for the data shift unit. + * | | |Note: In SPI protocol, it is suggested this bit should be set as 0. + * |[2] |ININV |Input Signal Inverse Selection + * | | |This bit defines the inverter enable of the input asynchronous signal. + * | | |0 = The un-synchronized input signal will not be inverted. + * | | |1 = The un-synchronized input signal will be inverted. + * @var USPI_T::CLKIN + * Offset: 0x28 USCI Input Clock Signal Configuration Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |SYNCSEL |Input Synchronization Signal Selection + * | | |This bit selects if the un-synchronized input signal or the synchronized (and optionally filtered) signal can be used as input for the data shift unit. + * | | |0 = The un-synchronized signal can be taken as input for the data shift unit. + * | | |1 = The synchronized signal can be taken as input for the data shift unit. + * | | |Note: In SPI protocol, it is suggested this bit should be set as 0. + * @var USPI_T::LINECTL + * Offset: 0x2C USCI Line Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |LSB |LSB First Transmission Selection + * | | |0 = The MSB, which bit of transmit/receive data buffer depends on the setting of DWIDTH, is transmitted/received first. + * | | |1 = The LSB, the bit 0 of data buffer, will be transmitted/received first. + * |[5] |DATOINV |Data Output Inverse Selection + * | | |This bit defines the relation between the internal shift data value and the output data signal of USCIx_DAT0/1 pin. + * | | |0 = Data output level is not inverted. + * | | |1 = Data output level is inverted. + * |[7] |CTLOINV |Control Signal Output Inverse Selection + * | | |This bit defines the relation between the internal control signal and the output control signal. + * | | |0 = No effect. + * | | |1 = The control signal will be inverted before its output. + * | | |Note: The control signal has different definitions in different protocol + * | | |In SPI protocol, the control signal means slave select signal + * |[11:8] |DWIDTH |Word Length of Transmission + * | | |This bit field defines the data word length (amount of bits) for reception and transmission + * | | |The data word is always right-aligned in the data buffer + * | | |USCI support word length from 4 to 16 bits. + * | | |0x0: The data word contains 16 bits located at bit positions [15:0]. + * | | |0x1: Reserved. + * | | |0x2: Reserved. + * | | |0x3: Reserved. + * | | |0x4: The data word contains 4 bits located at bit positions [3:0]. + * | | |0x5: The data word contains 5 bits located at bit positions [4:0]. + * | | |... + * | | |0xF: The data word contains 15 bits located at bit positions [14:0]. + * @var USPI_T::TXDAT + * Offset: 0x30 USCI Transmit Data Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |TXDAT |Transmit Data + * | | |Software can use this bit field to write 16-bit transmit data for transmission + * | | |In order to avoid overwriting the transmit data, user have to check TXEMPTY (USPI_BUFSTS[8]) status before writing transmit data into this bit field. + * |[16] |PORTDIR |Port Direction Control + * | | |This bit field is only available while USCI operates in SPI protocol (FUNMODE = 0x1) with half-duplex transfer + * | | |It is used to define the direction of the data port pin + * | | |When software writes USPI_TXDAT register, the transmit data and its port direction are settled simultaneously. + * | | |0 = The data pin is configured as output mode. + * | | |1 = The data pin is configured as input mode. + * @var USPI_T::RXDAT + * Offset: 0x34 USCI Receive Data Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |RXDAT |Received Data + * | | |This bit field monitors the received data which stored in receive data buffer. + * @var USPI_T::BUFCTL + * Offset: 0x38 USCI Transmit/Receive Buffer Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[6] |TXUDRIEN |Slave Transmit Under-run Interrupt Enable Bit + * | | |0 = Transmit under-run interrupt Disabled. + * | | |1 = Transmit under-run interrupt Enabled. + * |[7] |TXCLR |Clear Transmit Buffer + * | | |0 = No effect. + * | | |1 = The transmit buffer is cleared + * | | |Should only be used while the buffer is not taking part in data traffic. + * | | |Note: It is cleared automatically after one PCLK cycle. + * |[14] |RXOVIEN |Receive Buffer Overrun Interrupt Enable Bit + * | | |0 = Receive overrun interrupt Disabled. + * | | |1 = Receive overrun interrupt Enabled. + * |[15] |RXCLR |Clear Receive Buffer + * | | |0 = No effect. + * | | |1 = The receive buffer is cleared + * | | |Should only be used while the buffer is not taking part in data traffic. + * | | |Note: It is cleared automatically after one PCLK cycle. + * |[16] |TXRST |Transmit Reset + * | | |0 = No effect. + * | | |1 = Reset the transmit-related counters, state machine, and the content of transmit shift register and data buffer. + * | | |Note 1: It is cleared automatically after one PCLK cycle. + * | | |Note 2: Write 1 to this bit will set the output data pin to zero if USPI_PROTCTL[28]=0. + * |[17] |RXRST |Receive Reset + * | | |0 = No effect. + * | | |1 = Reset the receive-related counters, state machine, and the content of receive shift register and data buffer. + * | | |Note: It is cleared automatically after one PCLK cycle. + * @var USPI_T::BUFSTS + * Offset: 0x3C USCI Transmit/Receive Buffer Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |RXEMPTY |Receive Buffer Empty Indicator (Read Only) + * | | |0 = Receive buffer is not empty. + * | | |1 = Receive buffer is empty. + * |[1] |RXFULL |Receive Buffer Full Indicator (Read Only) + * | | |0 = Receive buffer is not full. + * | | |1 = Receive buffer is full. + * |[3] |RXOVIF |Receive Buffer Overrun Interrupt Status + * | | |This bit indicates that a receive buffer overrun event has been detected + * | | |If RXOVIEN (USPI_BUFCTL[14]) is enabled, the corresponding interrupt request is activated + * | | |It is cleared by software writes 1 to this bit. + * | | |0 = A receive buffer overrun event has not been detected. + * | | |1 = A receive buffer overrun event has been detected. + * |[8] |TXEMPTY |Transmit Buffer Empty Indicator (Read Only) + * | | |0 = Transmit buffer is not empty. + * | | |1 = Transmit buffer is empty and available for the next transmission datum. + * |[9] |TXFULL |Transmit Buffer Full Indicator (Read Only) + * | | |0 = Transmit buffer is not full. + * | | |1 = Transmit buffer is full. + * |[11] |TXUDRIF |Transmit Buffer Under-run Interrupt Status + * | | |This bit indicates that a transmit buffer under-run event has been detected + * | | |If enabled by TXUDRIEN (USPI_BUFCTL[6]), the corresponding interrupt request is activated + * | | |It is cleared by software writes 1 to this bit + * | | |0 = A transmit buffer under-run event has not been detected. + * | | |1 = A transmit buffer under-run event has been detected. + * @var USPI_T::PDMACTL + * Offset: 0x40 USCI PDMA Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |PDMARST |PDMA Reset + * | | |0 = No effect. + * | | |1 = Reset the USCI's PDMA control logic. This bit will be cleared to 0 automatically. + * |[1] |TXPDMAEN |PDMA Transmit Channel Available + * | | |0 = Transmit PDMA function Disabled. + * | | |1 = Transmit PDMA function Enabled. + * |[2] |RXPDMAEN |PDMA Receive Channel Available + * | | |0 = Receive PDMA function Disabled. + * | | |1 = Receive PDMA function Enabled. + * |[3] |PDMAEN |PDMA Mode Enable Bit + * | | |0 = PDMA function Disabled. + * | | |1 = PDMA function Enabled. + * | | |Note: The I2C is not supporting PDMA function. + * @var USPI_T::WKCTL + * Offset: 0x54 USCI Wake-up Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |WKEN |Wake-up Enable Bit + * | | |0 = Wake-up function Disabled. + * | | |1 = Wake-up function Enabled. + * |[1] |WKADDREN |Wake-up Address Match Enable Bit + * | | |0 = The chip is woken up according data toggle. + * | | |1 = The chip is woken up according address match. + * |[2] |PDBOPT |Power Down Blocking Option + * | | |0 = If user attempts to enter Power-down mode by executing WFI while the protocol is in transferring, MCU will stop the transfer and enter Power-down mode immediately. + * | | |1 = If user attempts to enter Power-down mode by executing WFI while the protocol is in transferring, the on-going transfer will not be stopped and MCU will enter idle mode immediately. + * @var USPI_T::WKSTS + * Offset: 0x58 USCI Wake-up Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |WKF |Wake-up Flag + * | | |When chip is woken up from Power-down mode, this bit is set to 1 + * | | |Software can write 1 to clear this bit. + * @var USPI_T::PROTCTL + * Offset: 0x5C USCI Protocol Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |SLAVE |Slave Mode Selection + * | | |0 = Master mode. + * | | |1 = Slave mode. + * |[1] |SLV3WIRE |Slave 3-wire Mode Selection (Slave Only) + * | | |The SPI protocol can work with 3-wire interface (without slave select signal) in Slave mode. + * | | |0 = 4-wire bi-direction interface. + * | | |1 = 3-wire bi-direction interface. + * |[2] |SS |Slave Select Control (Master Only) + * | | |If AUTOSS bit is cleared, setting this bit to 1 will set the slave select signal to active state, and setting this bit to 0 will set the slave select signal back to inactive state. + * | | |If the AUTOSS function is enabled (AUTOSS = 1), the setting value of this bit will not affect the current state of slave select signal. + * | | |Note: In SPI protocol, the internal slave select signal is active high. + * |[3] |AUTOSS |Automatic Slave Select Function Enable (Master Only) + * | | |0 = Slave select signal will be controlled by the setting value of SS (USPI_PROTCTL[2]) bit. + * | | |1 = Slave select signal will be generated automatically + * | | |The slave select signal will be asserted by the SPI controller when transmit/receive is started, and will be de-asserted after each transmit/receive is finished. + * |[7:6] |SCLKMODE |Serial Bus Clock Mode + * | | |This bit field defines the SCLK idle status, data transmit, and data receive edge. + * | | |00 = MODE0. The idle state of SPI clock is low level. + * | | |Data is transmitted with falling edge and received with rising edge. + * | | |01 = MODE1. The idle state of SPI clock is low level. + * | | |Data is transmitted with rising edge and received with falling edge. + * | | |10 = MODE2. The idle state of SPI clock is high level. + * | | |Data is transmitted with rising edge and received with falling edge. + * | | |11 = MODE3. The idle state of SPI clock is high level. + * | | |Data is transmitted with falling edge and received with rising edge. + * |[11:8] |SUSPITV |Suspend Interval (Master Only) + * | | |This bit field provides the configurable suspend interval between two successive transmit/receive transaction in a transfer + * | | |The definition of the suspend interval is the interval between the last clock edge of the preceding transaction word and the first clock edge of the following transaction word + * | | |The default value is 0x3 + * | | |The period of the suspend interval is obtained according to the following equation. + * | | |(SUSPITV[3:0] + 0.5) * period of SPI_CLK clock cycle + * | | |Example: + * | | |SUSPITV = 0x0 ... 0.5 SPI_CLK clock cycle. + * | | |SUSPITV = 0x1 ... 1.5 SPI_CLK clock cycle. + * | | |..... + * | | |SUSPITV = 0xE ... 14.5 SPI_CLK clock cycle. + * | | |SUSPITV = 0xF ... 15.5 SPI_CLK clock cycle. + * |[14:12] |TSMSEL |Transmit Data Mode Selection + * | | |This bit field describes how receive and transmit data is shifted in and out. + * | | |TSMSEL = 000b: Full-duplex SPI. + * | | |TSMSEL = 100b: Half-duplex SPI. + * | | |Others = Reserved. + * | | |Note: Changing the value of this bit field will produce the TXRST and RXRST to clear the TX/RX data buffer automatically. + * |[25:16] |SLVTOCNT |Slave Mode Time-out Period (Slave Only) + * | | |In Slave mode, this bit field is used for Slave time-out period + * | | |This bit field indicates how many clock periods (selected by TMCNTSRC, USPI_BRGEN[5]) between the two edges of input SCLK will assert the Slave time-out event + * | | |Writing 0x0 into this bit field will disable the Slave time-out function. + * | | |Example: Assume SLVTOCNT is 0x0A and TMCNTSRC (USPI_BRGEN[5]) is 1, it means the time-out event will occur if the state of SPI bus clock pin is not changed more than (10+1) periods of fDIV_CLK. + * |[28] |TXUDRPOL |Transmit Under-run Data Polarity (Slave Only) + * | | |This bit defines the transmitting data level when no data is available for transferring. + * | | |0 = The output data level is 0 if TX under-run event occurs. + * | | |1 = The output data level is 1 if TX under-run event occurs. + * |[31] |PROTEN |SPI Protocol Enable Bit + * | | |0 = SPI Protocol Disabled. + * | | |1 = SPI Protocol Enabled. + * @var USPI_T::PROTIEN + * Offset: 0x60 USCI Protocol Interrupt Enable Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |SSINAIEN |Slave Select Inactive Interrupt Enable Bit + * | | |This bit enables/disables the generation of a slave select interrupt if the slave select changes to inactive. + * | | |0 = Slave select inactive interrupt generation Disabled. + * | | |1 = Slave select inactive interrupt generation Enabled. + * |[1] |SSACTIEN |Slave Select Active Interrupt Enable Bit + * | | |This bit enables/disables the generation of a slave select interrupt if the slave select changes to active. + * | | |0 = Slave select active interrupt generation Disabled. + * | | |1 = Slave select active interrupt generation Enabled. + * |[2] |SLVTOIEN |Slave Time-out Interrupt Enable Bit + * | | |In SPI protocol, this bit enables the interrupt generation in case of a Slave time-out event. + * | | |0 = The Slave time-out interrupt Disabled. + * | | |1 = The Slave time-out interrupt Enabled. + * |[3] |SLVBEIEN |Slave Mode Bit Count Error Interrupt Enable Bit + * | | |If data transfer is terminated by slave time-out or slave select inactive event in Slave mode, so that the transmit/receive data bit count does not match the setting of DWIDTH (USPI_LINECTL[11:8]) + * | | |Bit count error event occurs. + * | | |0 = The Slave mode bit count error interrupt Disabled. + * | | |1 = The Slave mode bit count error interrupt Enabled. + * @var USPI_T::PROTSTS + * Offset: 0x64 USCI Protocol Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[1] |TXSTIF |Transmit Start Interrupt Flag + * | | |0 = Transmit start event did not occur. + * | | |1 = Transmit start event occurred. + * | | |Note: It is cleared by software write 1 to this bit + * |[2] |TXENDIF |Transmit End Interrupt Flag + * | | |0 = Transmit end event did not occur. + * | | |1 = Transmit end event occurred. + * | | |Note: It is cleared by software write 1 to this bit + * |[3] |RXSTIF |Receive Start Interrupt Flag + * | | |0 = Receive start event did not occur. + * | | |1 = Receive start event occurred. + * | | |Note: It is cleared by software write 1 to this bit + * |[4] |RXENDIF |Receive End Interrupt Flag + * | | |0 = Receive end event did not occur. + * | | |1 = Receive end event occurred. + * | | |Note: It is cleared by software write 1 to this bit + * |[5] |SLVTOIF |Slave Time-out Interrupt Flag (Slave Only) + * | | |0 = Slave time-out event did not occur. + * | | |1 = Slave time-out event occurred. + * | | |Note: It is cleared by software write 1 to this bit + * |[6] |SLVBEIF |Slave Bit Count Error Interrupt Flag (Slave Only) + * | | |0 = Slave bit count error event did not occur. + * | | |1 = Slave bit count error event occurred. + * | | |Note: It is cleared by software write 1 to this bit. + * |[8] |SSINAIF |Slave Select Inactive Interrupt Flag (Slave Only) + * | | |This bit indicates that the internal slave select signal has changed to inactive + * | | |It is cleared by software writes 1 to this bit + * | | |0 = The slave select signal has not changed to inactive. + * | | |1 = The slave select signal has changed to inactive. + * | | |Note: The internal slave select signal is active high. + * |[9] |SSACTIF |Slave Select Active Interrupt Flag (Slave Only) + * | | |This bit indicates that the internal slave select signal has changed to active + * | | |It is cleared by software writes one to this bit + * | | |0 = The slave select signal has not changed to active. + * | | |1 = The slave select signal has changed to active. + * | | |Note: The internal slave select signal is active high. + * |[16] |SSLINE |Slave Select Line Bus Status (Read Only) + * | | |This bit is only available in Slave mode + * | | |It used to monitor the current status of the input slave select signal on the bus. + * | | |0 = The slave select line status is 0. + * | | |1 = The slave select line status is 1. + * |[17] |BUSY |Busy Status (Read Only) + * | | |0 = SPI is in idle state. + * | | |1 = SPI is in busy state. + * | | |The following listing are the bus busy conditions: + * | | |a. USPI_PROTCTL[31] = 1 and the TXEMPTY = 0. + * | | |b. For SPI Master mode, the TXEMPTY = 1 but the current transaction is not finished yet. + * | | |c. For SPI Slave mode, the USPI_PROTCTL[31] = 1 and there is serial clock input into the SPI core logic when slave select is active. + * | | |d. For SPI Slave mode, the USPI_PROTCTL[31] = 1 and the transmit buffer or transmit shift register is not empty even if the slave select is inactive. + * |[18] |SLVUDR |Slave Mode Transmit Under-run Status (Read Only) + * | | |In Slave mode, if there is no available transmit data in buffer while transmit data shift out caused by input serial bus clock, this status flag will be set to 1 + * | | |This bit indicates whether the current shift-out data of word transmission is switched to TXUDRPOL (USPI_PROTCTL[28]) or not. + * | | |0 = Slave transmit under-run event did not occur. + * | | |1 = Slave transmit under-run event occurred. + */ + __IO uint32_t CTL; /*!< [0x0000] USCI Control Register */ + __IO uint32_t INTEN; /*!< [0x0004] USCI Interrupt Enable Register */ + __IO uint32_t BRGEN; /*!< [0x0008] USCI Baud Rate Generator Register */ + __I uint32_t RESERVE0[1]; + __IO uint32_t DATIN0; /*!< [0x0010] USCI Input Data Signal Configuration Register 0 */ + __I uint32_t RESERVE1[3]; + __IO uint32_t CTLIN0; /*!< [0x0020] USCI Input Control Signal Configuration Register 0 */ + __I uint32_t RESERVE2[1]; + __IO uint32_t CLKIN; /*!< [0x0028] USCI Input Clock Signal Configuration Register */ + __IO uint32_t LINECTL; /*!< [0x002c] USCI Line Control Register */ + __O uint32_t TXDAT; /*!< [0x0030] USCI Transmit Data Register */ + __I uint32_t RXDAT; /*!< [0x0034] USCI Receive Data Register */ + __IO uint32_t BUFCTL; /*!< [0x0038] USCI Transmit/Receive Buffer Control Register */ + __IO uint32_t BUFSTS; /*!< [0x003c] USCI Transmit/Receive Buffer Status Register */ + __IO uint32_t PDMACTL; /*!< [0x0040] USCI PDMA Control Register */ + __I uint32_t RESERVE3[4]; + __IO uint32_t WKCTL; /*!< [0x0054] USCI Wake-up Control Register */ + __IO uint32_t WKSTS; /*!< [0x0058] USCI Wake-up Status Register */ + __IO uint32_t PROTCTL; /*!< [0x005c] USCI Protocol Control Register */ + __IO uint32_t PROTIEN; /*!< [0x0060] USCI Protocol Interrupt Enable Register */ + __IO uint32_t PROTSTS; /*!< [0x0064] USCI Protocol Status Register */ + +} USPI_T; + +/** + @addtogroup USPI_CONST USPI Bit Field Definition + Constant Definitions for USPI Controller + @{ +*/ + +#define USPI_CTL_FUNMODE_Pos (0) /*!< USPI_T::CTL: FUNMODE Position */ +#define USPI_CTL_FUNMODE_Msk (0x7ul << USPI_CTL_FUNMODE_Pos) /*!< USPI_T::CTL: FUNMODE Mask */ + +#define USPI_INTEN_TXSTIEN_Pos (1) /*!< USPI_T::INTEN: TXSTIEN Position */ +#define USPI_INTEN_TXSTIEN_Msk (0x1ul << USPI_INTEN_TXSTIEN_Pos) /*!< USPI_T::INTEN: TXSTIEN Mask */ + +#define USPI_INTEN_TXENDIEN_Pos (2) /*!< USPI_T::INTEN: TXENDIEN Position */ +#define USPI_INTEN_TXENDIEN_Msk (0x1ul << USPI_INTEN_TXENDIEN_Pos) /*!< USPI_T::INTEN: TXENDIEN Mask */ + +#define USPI_INTEN_RXSTIEN_Pos (3) /*!< USPI_T::INTEN: RXSTIEN Position */ +#define USPI_INTEN_RXSTIEN_Msk (0x1ul << USPI_INTEN_RXSTIEN_Pos) /*!< USPI_T::INTEN: RXSTIEN Mask */ + +#define USPI_INTEN_RXENDIEN_Pos (4) /*!< USPI_T::INTEN: RXENDIEN Position */ +#define USPI_INTEN_RXENDIEN_Msk (0x1ul << USPI_INTEN_RXENDIEN_Pos) /*!< USPI_T::INTEN: RXENDIEN Mask */ + +#define USPI_BRGEN_RCLKSEL_Pos (0) /*!< USPI_T::BRGEN: RCLKSEL Position */ +#define USPI_BRGEN_RCLKSEL_Msk (0x1ul << USPI_BRGEN_RCLKSEL_Pos) /*!< USPI_T::BRGEN: RCLKSEL Mask */ + +#define USPI_BRGEN_PTCLKSEL_Pos (1) /*!< USPI_T::BRGEN: PTCLKSEL Position */ +#define USPI_BRGEN_PTCLKSEL_Msk (0x1ul << USPI_BRGEN_PTCLKSEL_Pos) /*!< USPI_T::BRGEN: PTCLKSEL Mask */ + +#define USPI_BRGEN_SPCLKSEL_Pos (2) /*!< USPI_T::BRGEN: SPCLKSEL Position */ +#define USPI_BRGEN_SPCLKSEL_Msk (0x3ul << USPI_BRGEN_SPCLKSEL_Pos) /*!< USPI_T::BRGEN: SPCLKSEL Mask */ + +#define USPI_BRGEN_TMCNTEN_Pos (4) /*!< USPI_T::BRGEN: TMCNTEN Position */ +#define USPI_BRGEN_TMCNTEN_Msk (0x1ul << USPI_BRGEN_TMCNTEN_Pos) /*!< USPI_T::BRGEN: TMCNTEN Mask */ + +#define USPI_BRGEN_TMCNTSRC_Pos (5) /*!< USPI_T::BRGEN: TMCNTSRC Position */ +#define USPI_BRGEN_TMCNTSRC_Msk (0x1ul << USPI_BRGEN_TMCNTSRC_Pos) /*!< USPI_T::BRGEN: TMCNTSRC Mask */ + +#define USPI_BRGEN_CLKDIV_Pos (16) /*!< USPI_T::BRGEN: CLKDIV Position */ +#define USPI_BRGEN_CLKDIV_Msk (0x3fful << USPI_BRGEN_CLKDIV_Pos) /*!< USPI_T::BRGEN: CLKDIV Mask */ + +#define USPI_DATIN0_SYNCSEL_Pos (0) /*!< USPI_T::DATIN0: SYNCSEL Position */ +#define USPI_DATIN0_SYNCSEL_Msk (0x1ul << USPI_DATIN0_SYNCSEL_Pos) /*!< USPI_T::DATIN0: SYNCSEL Mask */ + +#define USPI_DATIN0_ININV_Pos (2) /*!< USPI_T::DATIN0: ININV Position */ +#define USPI_DATIN0_ININV_Msk (0x1ul << USPI_DATIN0_ININV_Pos) /*!< USPI_T::DATIN0: ININV Mask */ + +#define USPI_CTLIN0_SYNCSEL_Pos (0) /*!< USPI_T::CTLIN0: SYNCSEL Position */ +#define USPI_CTLIN0_SYNCSEL_Msk (0x1ul << USPI_CTLIN0_SYNCSEL_Pos) /*!< USPI_T::CTLIN0: SYNCSEL Mask */ + +#define USPI_CTLIN0_ININV_Pos (2) /*!< USPI_T::CTLIN0: ININV Position */ +#define USPI_CTLIN0_ININV_Msk (0x1ul << USPI_CTLIN0_ININV_Pos) /*!< USPI_T::CTLIN0: ININV Mask */ + +#define USPI_CLKIN_SYNCSEL_Pos (0) /*!< USPI_T::CLKIN: SYNCSEL Position */ +#define USPI_CLKIN_SYNCSEL_Msk (0x1ul << USPI_CLKIN_SYNCSEL_Pos) /*!< USPI_T::CLKIN: SYNCSEL Mask */ + +#define USPI_LINECTL_LSB_Pos (0) /*!< USPI_T::LINECTL: LSB Position */ +#define USPI_LINECTL_LSB_Msk (0x1ul << USPI_LINECTL_LSB_Pos) /*!< USPI_T::LINECTL: LSB Mask */ + +#define USPI_LINECTL_DATOINV_Pos (5) /*!< USPI_T::LINECTL: DATOINV Position */ +#define USPI_LINECTL_DATOINV_Msk (0x1ul << USPI_LINECTL_DATOINV_Pos) /*!< USPI_T::LINECTL: DATOINV Mask */ + +#define USPI_LINECTL_CTLOINV_Pos (7) /*!< USPI_T::LINECTL: CTLOINV Position */ +#define USPI_LINECTL_CTLOINV_Msk (0x1ul << USPI_LINECTL_CTLOINV_Pos) /*!< USPI_T::LINECTL: CTLOINV Mask */ + +#define USPI_LINECTL_DWIDTH_Pos (8) /*!< USPI_T::LINECTL: DWIDTH Position */ +#define USPI_LINECTL_DWIDTH_Msk (0xful << USPI_LINECTL_DWIDTH_Pos) /*!< USPI_T::LINECTL: DWIDTH Mask */ + +#define USPI_TXDAT_TXDAT_Pos (0) /*!< USPI_T::TXDAT: TXDAT Position */ +#define USPI_TXDAT_TXDAT_Msk (0xfffful << USPI_TXDAT_TXDAT_Pos) /*!< USPI_T::TXDAT: TXDAT Mask */ + +#define USPI_TXDAT_PORTDIR_Pos (16) /*!< USPI_T::TXDAT: PORTDIR Position */ +#define USPI_TXDAT_PORTDIR_Msk (0x1ul << USPI_TXDAT_PORTDIR_Pos) /*!< USPI_T::TXDAT: PORTDIR Mask */ + +#define USPI_RXDAT_RXDAT_Pos (0) /*!< USPI_T::RXDAT: RXDAT Position */ +#define USPI_RXDAT_RXDAT_Msk (0xfffful << USPI_RXDAT_RXDAT_Pos) /*!< USPI_T::RXDAT: RXDAT Mask */ + +#define USPI_BUFCTL_TXUDRIEN_Pos (6) /*!< USPI_T::BUFCTL: TXUDRIEN Position */ +#define USPI_BUFCTL_TXUDRIEN_Msk (0x1ul << USPI_BUFCTL_TXUDRIEN_Pos) /*!< USPI_T::BUFCTL: TXUDRIEN Mask */ + +#define USPI_BUFCTL_TXCLR_Pos (7) /*!< USPI_T::BUFCTL: TXCLR Position */ +#define USPI_BUFCTL_TXCLR_Msk (0x1ul << USPI_BUFCTL_TXCLR_Pos) /*!< USPI_T::BUFCTL: TXCLR Mask */ + +#define USPI_BUFCTL_RXOVIEN_Pos (14) /*!< USPI_T::BUFCTL: RXOVIEN Position */ +#define USPI_BUFCTL_RXOVIEN_Msk (0x1ul << USPI_BUFCTL_RXOVIEN_Pos) /*!< USPI_T::BUFCTL: RXOVIEN Mask */ + +#define USPI_BUFCTL_RXCLR_Pos (15) /*!< USPI_T::BUFCTL: RXCLR Position */ +#define USPI_BUFCTL_RXCLR_Msk (0x1ul << USPI_BUFCTL_RXCLR_Pos) /*!< USPI_T::BUFCTL: RXCLR Mask */ + +#define USPI_BUFCTL_TXRST_Pos (16) /*!< USPI_T::BUFCTL: TXRST Position */ +#define USPI_BUFCTL_TXRST_Msk (0x1ul << USPI_BUFCTL_TXRST_Pos) /*!< USPI_T::BUFCTL: TXRST Mask */ + +#define USPI_BUFCTL_RXRST_Pos (17) /*!< USPI_T::BUFCTL: RXRST Position */ +#define USPI_BUFCTL_RXRST_Msk (0x1ul << USPI_BUFCTL_RXRST_Pos) /*!< USPI_T::BUFCTL: RXRST Mask */ + +#define USPI_BUFSTS_RXEMPTY_Pos (0) /*!< USPI_T::BUFSTS: RXEMPTY Position */ +#define USPI_BUFSTS_RXEMPTY_Msk (0x1ul << USPI_BUFSTS_RXEMPTY_Pos) /*!< USPI_T::BUFSTS: RXEMPTY Mask */ + +#define USPI_BUFSTS_RXFULL_Pos (1) /*!< USPI_T::BUFSTS: RXFULL Position */ +#define USPI_BUFSTS_RXFULL_Msk (0x1ul << USPI_BUFSTS_RXFULL_Pos) /*!< USPI_T::BUFSTS: RXFULL Mask */ + +#define USPI_BUFSTS_RXOVIF_Pos (3) /*!< USPI_T::BUFSTS: RXOVIF Position */ +#define USPI_BUFSTS_RXOVIF_Msk (0x1ul << USPI_BUFSTS_RXOVIF_Pos) /*!< USPI_T::BUFSTS: RXOVIF Mask */ + +#define USPI_BUFSTS_TXEMPTY_Pos (8) /*!< USPI_T::BUFSTS: TXEMPTY Position */ +#define USPI_BUFSTS_TXEMPTY_Msk (0x1ul << USPI_BUFSTS_TXEMPTY_Pos) /*!< USPI_T::BUFSTS: TXEMPTY Mask */ + +#define USPI_BUFSTS_TXFULL_Pos (9) /*!< USPI_T::BUFSTS: TXFULL Position */ +#define USPI_BUFSTS_TXFULL_Msk (0x1ul << USPI_BUFSTS_TXFULL_Pos) /*!< USPI_T::BUFSTS: TXFULL Mask */ + +#define USPI_BUFSTS_TXUDRIF_Pos (11) /*!< USPI_T::BUFSTS: TXUDRIF Position */ +#define USPI_BUFSTS_TXUDRIF_Msk (0x1ul << USPI_BUFSTS_TXUDRIF_Pos) /*!< USPI_T::BUFSTS: TXUDRIF Mask */ + +#define USPI_PDMACTL_PDMARST_Pos (0) /*!< USPI_T::PDMACTL: PDMARST Position */ +#define USPI_PDMACTL_PDMARST_Msk (0x1ul << USPI_PDMACTL_PDMARST_Pos) /*!< USPI_T::PDMACTL: PDMARST Mask */ + +#define USPI_PDMACTL_TXPDMAEN_Pos (1) /*!< USPI_T::PDMACTL: TXPDMAEN Position */ +#define USPI_PDMACTL_TXPDMAEN_Msk (0x1ul << USPI_PDMACTL_TXPDMAEN_Pos) /*!< USPI_T::PDMACTL: TXPDMAEN Mask */ + +#define USPI_PDMACTL_RXPDMAEN_Pos (2) /*!< USPI_T::PDMACTL: RXPDMAEN Position */ +#define USPI_PDMACTL_RXPDMAEN_Msk (0x1ul << USPI_PDMACTL_RXPDMAEN_Pos) /*!< USPI_T::PDMACTL: RXPDMAEN Mask */ + +#define USPI_PDMACTL_PDMAEN_Pos (3) /*!< USPI_T::PDMACTL: PDMAEN Position */ +#define USPI_PDMACTL_PDMAEN_Msk (0x1ul << USPI_PDMACTL_PDMAEN_Pos) /*!< USPI_T::PDMACTL: PDMAEN Mask */ + +#define USPI_WKCTL_WKEN_Pos (0) /*!< USPI_T::WKCTL: WKEN Position */ +#define USPI_WKCTL_WKEN_Msk (0x1ul << USPI_WKCTL_WKEN_Pos) /*!< USPI_T::WKCTL: WKEN Mask */ + +#define USPI_WKCTL_WKADDREN_Pos (1) /*!< USPI_T::WKCTL: WKADDREN Position */ +#define USPI_WKCTL_WKADDREN_Msk (0x1ul << USPI_WKCTL_WKADDREN_Pos) /*!< USPI_T::WKCTL: WKADDREN Mask */ + +#define USPI_WKCTL_PDBOPT_Pos (2) /*!< USPI_T::WKCTL: PDBOPT Position */ +#define USPI_WKCTL_PDBOPT_Msk (0x1ul << USPI_WKCTL_PDBOPT_Pos) /*!< USPI_T::WKCTL: PDBOPT Mask */ + +#define USPI_WKSTS_WKF_Pos (0) /*!< USPI_T::WKSTS: WKF Position */ +#define USPI_WKSTS_WKF_Msk (0x1ul << USPI_WKSTS_WKF_Pos) /*!< USPI_T::WKSTS: WKF Mask */ + +#define USPI_PROTCTL_SLAVE_Pos (0) /*!< USPI_T::PROTCTL: SLAVE Position */ +#define USPI_PROTCTL_SLAVE_Msk (0x1ul << USPI_PROTCTL_SLAVE_Pos) /*!< USPI_T::PROTCTL: SLAVE Mask */ + +#define USPI_PROTCTL_SLV3WIRE_Pos (1) /*!< USPI_T::PROTCTL: SLV3WIRE Position */ +#define USPI_PROTCTL_SLV3WIRE_Msk (0x1ul << USPI_PROTCTL_SLV3WIRE_Pos) /*!< USPI_T::PROTCTL: SLV3WIRE Mask */ + +#define USPI_PROTCTL_SS_Pos (2) /*!< USPI_T::PROTCTL: SS Position */ +#define USPI_PROTCTL_SS_Msk (0x1ul << USPI_PROTCTL_SS_Pos) /*!< USPI_T::PROTCTL: SS Mask */ + +#define USPI_PROTCTL_AUTOSS_Pos (3) /*!< USPI_T::PROTCTL: AUTOSS Position */ +#define USPI_PROTCTL_AUTOSS_Msk (0x1ul << USPI_PROTCTL_AUTOSS_Pos) /*!< USPI_T::PROTCTL: AUTOSS Mask */ + +#define USPI_PROTCTL_SCLKMODE_Pos (6) /*!< USPI_T::PROTCTL: SCLKMODE Position */ +#define USPI_PROTCTL_SCLKMODE_Msk (0x3ul << USPI_PROTCTL_SCLKMODE_Pos) /*!< USPI_T::PROTCTL: SCLKMODE Mask */ + +#define USPI_PROTCTL_SUSPITV_Pos (8) /*!< USPI_T::PROTCTL: SUSPITV Position */ +#define USPI_PROTCTL_SUSPITV_Msk (0xful << USPI_PROTCTL_SUSPITV_Pos) /*!< USPI_T::PROTCTL: SUSPITV Mask */ + +#define USPI_PROTCTL_TSMSEL_Pos (12) /*!< USPI_T::PROTCTL: TSMSEL Position */ +#define USPI_PROTCTL_TSMSEL_Msk (0x7ul << USPI_PROTCTL_TSMSEL_Pos) /*!< USPI_T::PROTCTL: TSMSEL Mask */ + +#define USPI_PROTCTL_SLVTOCNT_Pos (16) /*!< USPI_T::PROTCTL: SLVTOCNT Position */ +#define USPI_PROTCTL_SLVTOCNT_Msk (0x3fful << USPI_PROTCTL_SLVTOCNT_Pos) /*!< USPI_T::PROTCTL: SLVTOCNT Mask */ + +#define USPI_PROTCTL_TXUDRPOL_Pos (28) /*!< USPI_T::PROTCTL: TXUDRPOL Position */ +#define USPI_PROTCTL_TXUDRPOL_Msk (0x1ul << USPI_PROTCTL_TXUDRPOL_Pos) /*!< USPI_T::PROTCTL: TXUDRPOL Mask */ + +#define USPI_PROTCTL_PROTEN_Pos (31) /*!< USPI_T::PROTCTL: PROTEN Position */ +#define USPI_PROTCTL_PROTEN_Msk (0x1ul << USPI_PROTCTL_PROTEN_Pos) /*!< USPI_T::PROTCTL: PROTEN Mask */ + +#define USPI_PROTIEN_SSINAIEN_Pos (0) /*!< USPI_T::PROTIEN: SSINAIEN Position */ +#define USPI_PROTIEN_SSINAIEN_Msk (0x1ul << USPI_PROTIEN_SSINAIEN_Pos) /*!< USPI_T::PROTIEN: SSINAIEN Mask */ + +#define USPI_PROTIEN_SSACTIEN_Pos (1) /*!< USPI_T::PROTIEN: SSACTIEN Position */ +#define USPI_PROTIEN_SSACTIEN_Msk (0x1ul << USPI_PROTIEN_SSACTIEN_Pos) /*!< USPI_T::PROTIEN: SSACTIEN Mask */ + +#define USPI_PROTIEN_SLVTOIEN_Pos (2) /*!< USPI_T::PROTIEN: SLVTOIEN Position */ +#define USPI_PROTIEN_SLVTOIEN_Msk (0x1ul << USPI_PROTIEN_SLVTOIEN_Pos) /*!< USPI_T::PROTIEN: SLVTOIEN Mask */ + +#define USPI_PROTIEN_SLVBEIEN_Pos (3) /*!< USPI_T::PROTIEN: SLVBEIEN Position */ +#define USPI_PROTIEN_SLVBEIEN_Msk (0x1ul << USPI_PROTIEN_SLVBEIEN_Pos) /*!< USPI_T::PROTIEN: SLVBEIEN Mask */ + +#define USPI_PROTSTS_TXSTIF_Pos (1) /*!< USPI_T::PROTSTS: TXSTIF Position */ +#define USPI_PROTSTS_TXSTIF_Msk (0x1ul << USPI_PROTSTS_TXSTIF_Pos) /*!< USPI_T::PROTSTS: TXSTIF Mask */ + +#define USPI_PROTSTS_TXENDIF_Pos (2) /*!< USPI_T::PROTSTS: TXENDIF Position */ +#define USPI_PROTSTS_TXENDIF_Msk (0x1ul << USPI_PROTSTS_TXENDIF_Pos) /*!< USPI_T::PROTSTS: TXENDIF Mask */ + +#define USPI_PROTSTS_RXSTIF_Pos (3) /*!< USPI_T::PROTSTS: RXSTIF Position */ +#define USPI_PROTSTS_RXSTIF_Msk (0x1ul << USPI_PROTSTS_RXSTIF_Pos) /*!< USPI_T::PROTSTS: RXSTIF Mask */ + +#define USPI_PROTSTS_RXENDIF_Pos (4) /*!< USPI_T::PROTSTS: RXENDIF Position */ +#define USPI_PROTSTS_RXENDIF_Msk (0x1ul << USPI_PROTSTS_RXENDIF_Pos) /*!< USPI_T::PROTSTS: RXENDIF Mask */ + +#define USPI_PROTSTS_SLVTOIF_Pos (5) /*!< USPI_T::PROTSTS: SLVTOIF Position */ +#define USPI_PROTSTS_SLVTOIF_Msk (0x1ul << USPI_PROTSTS_SLVTOIF_Pos) /*!< USPI_T::PROTSTS: SLVTOIF Mask */ + +#define USPI_PROTSTS_SLVBEIF_Pos (6) /*!< USPI_T::PROTSTS: SLVBEIF Position */ +#define USPI_PROTSTS_SLVBEIF_Msk (0x1ul << USPI_PROTSTS_SLVBEIF_Pos) /*!< USPI_T::PROTSTS: SLVBEIF Mask */ + +#define USPI_PROTSTS_SSINAIF_Pos (8) /*!< USPI_T::PROTSTS: SSINAIF Position */ +#define USPI_PROTSTS_SSINAIF_Msk (0x1ul << USPI_PROTSTS_SSINAIF_Pos) /*!< USPI_T::PROTSTS: SSINAIF Mask */ + +#define USPI_PROTSTS_SSACTIF_Pos (9) /*!< USPI_T::PROTSTS: SSACTIF Position */ +#define USPI_PROTSTS_SSACTIF_Msk (0x1ul << USPI_PROTSTS_SSACTIF_Pos) /*!< USPI_T::PROTSTS: SSACTIF Mask */ + +#define USPI_PROTSTS_SSLINE_Pos (16) /*!< USPI_T::PROTSTS: SSLINE Position */ +#define USPI_PROTSTS_SSLINE_Msk (0x1ul << USPI_PROTSTS_SSLINE_Pos) /*!< USPI_T::PROTSTS: SSLINE Mask */ + +#define USPI_PROTSTS_BUSY_Pos (17) /*!< USPI_T::PROTSTS: BUSY Position */ +#define USPI_PROTSTS_BUSY_Msk (0x1ul << USPI_PROTSTS_BUSY_Pos) /*!< USPI_T::PROTSTS: BUSY Mask */ + +#define USPI_PROTSTS_SLVUDR_Pos (18) /*!< USPI_T::PROTSTS: SLVUDR Position */ +#define USPI_PROTSTS_SLVUDR_Msk (0x1ul << USPI_PROTSTS_SLVUDR_Pos) /*!< USPI_T::PROTSTS: SLVUDR Mask */ + +/**@}*/ /* USPI_CONST */ +/**@}*/ /* end of USPI register group */ +/**@}*/ /* end of REGISTER group */ + +#endif /* __USPI_REG_H__ */ diff --git a/Ubiquitous/XiZi/board/nuvoton-m2354/third_party_driver/include/Regs/uuart_reg.h b/Ubiquitous/XiZi/board/nuvoton-m2354/third_party_driver/include/Regs/uuart_reg.h new file mode 100644 index 0000000..75a14cf --- /dev/null +++ b/Ubiquitous/XiZi/board/nuvoton-m2354/third_party_driver/include/Regs/uuart_reg.h @@ -0,0 +1,670 @@ +/**************************************************************************//** + * @file uuart_reg.h + * @version V1.00 + * @brief UUART register definition header file + * + * @copyright SPDX-License-Identifier: Apache-2.0 + * @copyright Copyright (C) 2020 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ +#ifndef __UUART_REG_H__ +#define __UUART_REG_H__ + +/** @addtogroup REGISTER Control Register + + @{ + +*/ + + +/*---------------------- UART Mode of USCI Controller -------------------------*/ +/** + @addtogroup UUART UART Mode of USCI Controller(UUART) + Memory Mapped Structure for UUART Controller + @{ +*/ + +typedef struct +{ + + + /** + * @var UUART_T::CTL + * Offset: 0x00 USCI Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[2:0] |FUNMODE |Function Mode + * | | |This bit field selects the protocol for this USCI controller. + * | | |Selecting a protocol that is not available or a reserved combination disables the USCI. + * | | |When switching between two protocols, the USCI has to be disabled before selecting a new protocol. + * | | |Simultaneously, the USCI will be reset when user write 000 to FUNMODE. + * | | |000 = The USCI is disabled. All protocol related state machines are set to idle state. + * | | |001 = The SPI protocol is selected. + * | | |010 = The UART protocol is selected. + * | | |100 = The I2C protocol is selected. + * | | |Others = Reserved. + * @var UUART_T::INTEN + * Offset: 0x04 USCI Interrupt Enable Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[1] |TXSTIEN |Transmit Start Interrupt Enable Bit + * | | |This bit enables the interrupt generation in case of a transmit start event. + * | | |0 = The transmit start interrupt is disabled. + * | | |1 = The transmit start interrupt is enabled. + * |[2] |TXENDIEN |Transmit End Interrupt Enable Bit + * | | |This bit enables the interrupt generation in case of a transmit finish event. + * | | |0 = The transmit finish interrupt is disabled. + * | | |1 = The transmit finish interrupt is enabled. + * |[3] |RXSTIEN |Receive Start Interrupt Enable Bit + * | | |This bit enables the interrupt generation in case of a receive start event. + * | | |0 = The receive start interrupt is disabled. + * | | |1 = The receive start interrupt is enabled. + * |[4] |RXENDIEN |Receive End Interrupt Enable Bit + * | | |This bit enables the interrupt generation in case of a receive finish event. + * | | |0 = The receive end interrupt is disabled. + * | | |1 = The receive end interrupt is enabled. + * @var UUART_T::BRGEN + * Offset: 0x08 USCI Baud Rate Generator Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |RCLKSEL |Reference Clock Source Selection + * | | |This bit selects the source signal of reference clock (fREF_CLK). + * | | |0 = Peripheral device clock fPCLK. + * | | |1 = Reserved. + * |[1] |PTCLKSEL |Protocol Clock Source Selection + * | | |This bit selects the source signal of protocol clock (fPROT_CLK). + * | | |0 = Reference clock fREF_CLK. + * | | |1 = fREF_CLK2 (its frequency is half of fREF_CLK). + * |[3:2] |SPCLKSEL |Sample Clock Source Selection + * | | |This bit field used for the clock source selection of a sample clock (fSAMP_CLK) for the protocol processor. + * | | |00 = fSAMP_CLK frequency is fDIV_CLK. + * | | |01 = fSAMP_CLK frequency is from fPROT_CLK. + * | | |10 = fSAMP_CLK frequency is from fSCLK. + * | | |11 = fSAMP_CLK frequency is from fREF_CLK. + * |[4] |TMCNTEN |Timing Measurement Counter Enable Bit + * | | |This bit enables the 10-bit timing measurement counter. + * | | |0 = Timing measurement counter is Disabled. + * | | |1 = Timing measurement counter is Enabled. + * |[5] |TMCNTSRC |Timing Measurement Counter Clock Source Selection + * | | |0 = Timing measurement counter with fPROT_CLK. + * | | |1 = Timing measurement counter with fDIV_CLK. + * |[9:8] |PDSCNT |Pre-divider for Sample Counter + * | | |This bit field defines the divide ratio of the clock division from sample clock fSAMP_CLK. + * | | |The divided frequency fPDS_CNT = fSAMP_CLK / (PDSCNT+1). + * |[14:10] |DSCNT |Denominator for Sample Counter + * | | |This bit field defines the divide ratio of the sample clock fSAMP_CLK. + * | | |The divided frequency fDS_CNT = fPDS_CNT / (DSCNT+1). + * | | |Note: The maximum value of DSCNT is 0xF on UART mode and suggest to set over 4 to confirm the receiver data is sampled in right value. + * |[25:16] |CLKDIV |Clock Divider + * | | |This bit field defines the ratio between the protocol clock frequency fPROT_CLK and the clock divider frequency fDIV_CLK (fDIV_CLK = fPROT_CLK / (CLKDIV+1) ). + * | | |Note: In UART function, it can be updated by hardware in the 4th falling edge of the input data 0x55 when the auto baud rate function (ABREN(UUART_PROTCTL[6])) is enabled. + * | | |The revised value is the average bit time between bit 5 and bit 6. + * | | |The user can use revised CLKDIV and new BRDETITV (UUART_PROTCTL[24:16]) to calculate the precise baud rate. + * @var UUART_T::DATIN0 + * Offset: 0x10 USCI Input Data Signal Configuration Register 0 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |SYNCSEL |Input Signal Synchronization Selection + * | | |This bit selects if the un-synchronized input signal (with optionally inverted) or the synchronized (and optionally filtered) signal can be used as input for the data shift unit. + * | | |0 = The un-synchronized signal can be taken as input for the data shift unit. + * | | |1 = The synchronized signal can be taken as input for the data shift unit. + * |[2] |ININV |Input Signal Inverse Selection + * | | |This bit defines the inverter enable of the input asynchronous signal. + * | | |0 = The un-synchronized input signal will not be inverted. + * | | |1 = The un-synchronized input signal will be inverted. + * |[4:3] |EDGEDET |Input Signal Edge Detection Mode + * | | |This bit field selects which edge actives the trigger event of input data signal. + * | | |00 = The trigger event activation is disabled. + * | | |01 = A rising edge activates the trigger event of input data signal. + * | | |10 = A falling edge activates the trigger event of input data signal. + * | | |11 = Both edges activate the trigger event of input data signal. + * | | |Note: In UART function mode, it is suggested to set this bit field as 10. + * @var UUART_T::CTLIN0 + * Offset: 0x20 USCI Input Control Signal Configuration Register 0 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |SYNCSEL |Input Synchronization Signal Selection + * | | |This bit selects if the un-synchronized input signal (with optionally inverted) or the synchronized (and optionally filtered) signal can be used as input for the data shift unit. + * | | |0 = The un-synchronized signal can be taken as input for the data shift unit. + * | | |1 = The synchronized signal can be taken as input for the data shift unit. + * |[2] |ININV |Input Signal Inverse Selection + * | | |This bit defines the inverter enable of the input asynchronous signal. + * | | |0 = The un-synchronized input signal will not be inverted. + * | | |1 = The un-synchronized input signal will be inverted. + * @var UUART_T::CLKIN + * Offset: 0x28 USCI Input Clock Signal Configuration Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |SYNCSEL |Input Synchronization Signal Selection + * | | |This bit selects if the un-synchronized input signal or the synchronized (and optionally filtered) signal can be used as input for the data shift unit. + * | | |0 = The un-synchronized signal can be taken as input for the data shift unit. + * | | |1 = The synchronized signal can be taken as input for the data shift unit. + * @var UUART_T::LINECTL + * Offset: 0x2C USCI Line Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |LSB |LSB First Transmission Selection + * | | |0 = The MSB, which bit of transmit/receive data buffer depends on the setting of DWIDTH, is transmitted/received first. + * | | |1 = The LSB, the bit 0 of data buffer, will be transmitted/received first. + * |[5] |DATOINV |Data Output Inverse Selection + * | | |This bit defines the relation between the internal shift data value and the output data signal of USCIx_DAT1 pin. + * | | |0 = The value of USCIx_DAT1 is equal to the data shift register. + * | | |1 = The value of USCIx_DAT1 is the inversion of data shift register. + * |[7] |CTLOINV |Control Signal Output Inverse Selection + * | | |This bit defines the relation between the internal control signal and the output control signal. + * | | |0 = No effect. + * | | |1 = The control signal will be inverted before its output. + * | | |Note: In UART protocol, the control signal means nRTS signal. + * |[11:8] |DWIDTH |Word Length of Transmission + * | | |This bit field defines the data word length (amount of bits) for reception and transmission + * | | |The data word is always right-aligned in the data buffer + * | | |USCI support word length from 4 to 16 bits. + * | | |0x0 = The data word contains 16 bits located at bit positions [15:0]. + * | | |0x1 = Reserved. + * | | |0x2 = Reserved. + * | | |0x3 = Reserved. + * | | |0x4 = The data word contains 4 bits located at bit positions [3:0]. + * | | |0x5 = The data word contains 5 bits located at bit positions [4:0]. + * | | |... + * | | |0xF = The data word contains 15 bits located at bit positions [14:0]. + * | | |Note: In UART protocol, the length can be configured as 6~13 bits. + * @var UUART_T::TXDAT + * Offset: 0x30 USCI Transmit Data Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |TXDAT |Transmit Data + * | | |Software can use this bit field to write 16-bit transmit data for transmission. + * @var UUART_T::RXDAT + * Offset: 0x34 USCI Receive Data Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |RXDAT |Received Data + * | | |This bit field monitors the received data which stored in receive data buffer. + * | | |Note: RXDAT[15:13] indicate the same frame status of BREAK, FRMERR and PARITYERR (UUART_PROTSTS[7:5]). + * @var UUART_T::BUFCTL + * Offset: 0x38 USCI Transmit/Receive Buffer Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[7] |TXCLR |Clear Transmit Buffer + * | | |0 = No effect. + * | | |1 = The transmit buffer is cleared (filling level is cleared and output pointer is set to input pointer value). + * | | |Should only be used while the buffer is not taking part in data traffic. + * | | |Note: It is cleared automatically after one PCLK cycle. + * |[14] |RXOVIEN |Receive Buffer Overrun Error Interrupt Enable Control + * | | |0 = Receive overrun interrupt Disabled. + * | | |1 = Receive overrun interrupt Enabled. + * |[15] |RXCLR |Clear Receive Buffer + * | | |0 = No effect. + * | | |1 = The receive buffer is cleared (filling level is cleared and output pointer is set to input pointer value). + * | | |Should only be used while the buffer is not taking part in data traffic. + * | | |Note: It is cleared automatically after one PCLK cycle. + * |[16] |TXRST |Transmit Reset + * | | |0 = No effect. + * | | |1 = Reset the transmit-related counters, state machine, and the content of transmit shift register and data buffer. + * | | |Note: It is cleared automatically after one PCLK cycle. + * |[17] |RXRST |Receive Reset + * | | |0 = No effect. + * | | |1 = Reset the receive-related counters, state machine, and the content of receive shift register and data buffer. + * | | |Note1: It is cleared automatically after one PCLK cycle. + * | | |Note2: It is suggest to check the RXBUSY (UUART_PROTSTS[10]) before this bit will be set to 1. + * @var UUART_T::BUFSTS + * Offset: 0x3C USCI Transmit/Receive Buffer Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |RXEMPTY |Receive Buffer Empty Indicator + * | | |0 = Receive buffer is not empty. + * | | |1 = Receive buffer is empty. + * |[1] |RXFULL |Receive Buffer Full Indicator + * | | |0 = Receive buffer is not full. + * | | |1 = Receive buffer is full. + * |[3] |RXOVIF |Receive Buffer Over-run Error Interrupt Status + * | | |This bit indicates that a receive buffer overrun error event has been detected. + * | | |If RXOVIEN (UUART_BUFCTL[14]) is enabled, the corresponding interrupt request is activated. + * | | |It is cleared by software writes 1 to this bit. + * | | |0 = A receive buffer overrun error event has not been detected. + * | | |1 = A receive buffer overrun error event has been detected. + * |[8] |TXEMPTY |Transmit Buffer Empty Indicator + * | | |0 = Transmit buffer is not empty. + * | | |1 = Transmit buffer is empty. + * |[9] |TXFULL |Transmit Buffer Full Indicator + * | | |0 = Transmit buffer is not full. + * | | |1 = Transmit buffer is full. + * @var UUART_T::PDMACTL + * Offset: 0x40 USCI PDMA Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |PDMARST |PDMA Reset + * | | |0 = No effect. + * | | |1 = Reset the USCI PDMA control logic. This bit will be cleared to 0 automatically. + * |[1] |TXPDMAEN |PDMA Transmit Channel Available + * | | |0 = Transmit PDMA function Disabled. + * | | |1 = Transmit PDMA function Enabled. + * |[2] |RXPDMAEN |PDMA Receive Channel Available + * | | |0 = Receive PDMA function Disabled. + * | | |1 = Receive PDMA function Enabled. + * |[3] |PDMAEN |PDMA Mode Enable Bit + * | | |0 = PDMA function Disabled. + * | | |1 = PDMA function Enabled. + * @var UUART_T::WKCTL + * Offset: 0x54 USCI Wake-up Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |WKEN |Wake-up Enable Bit + * | | |0 = Wake-up function Disabled. + * | | |1 = Wake-up function Enabled. + * |[2] |PDBOPT |Power Down Blocking Option + * | | |0 = If user attempts to enter Power-down mode by executing WFI while the protocol is in transferring, MCU will stop the transfer and enter Power-down mode immediately. + * | | |1 = If user attempts to enter Power-down mode by executing WFI while the protocol is in transferring, the on-going transfer will not be stopped and MCU will enter idle mode immediately. + * @var UUART_T::WKSTS + * Offset: 0x58 USCI Wake-up Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |WKF |Wake-up Flag + * | | |When chip is woken up from Power-down mode, this bit is set to 1 + * | | |Software can write 1 to clear this bit. + * @var UUART_T::PROTCTL + * Offset: 0x5C USCI Protocol Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |STOPB |Stop Bits + * | | |This bit defines the number of stop bits in an UART frame. + * | | |0 = The number of stop bits is 1. + * | | |1 = The number of stop bits is 2. + * |[1] |PARITYEN |Parity Enable Bit + * | | |This bit defines the parity bit is enabled in an UART frame. + * | | |0 = The parity bit Disabled. + * | | |1 = The parity bit Enabled. + * |[2] |EVENPARITY|Even Parity Enable Bit + * | | |0 = Odd number of logic 1's is transmitted and checked in each word. + * | | |1 = Even number of logic 1's is transmitted and checked in each word. + * | | |Note: This bit has effect only when PARITYEN is set. + * |[3] |RTSAUTOEN |nRTS Auto-flow Control Enable Bit + * | | |When nRTS auto-flow is enabled, if the receiver buffer is full (RXFULL (UUART_BUFSTS[1] = 1)), the UART will de-assert nRTS signal. + * | | |0 = nRTS auto-flow control Disabled. + * | | |1 = nRTS auto-flow control Enabled. + * | | |Note: This bit has effect only when the RTSAUDIREN is not set. + * |[4] |CTSAUTOEN |nCTS Auto-flow Control Enable Bit + * | | |When nCTS auto-flow is enabled, the UART will send data to external device when nCTS input assert (UART will not send data to device if nCTS input is dis-asserted). + * | | |0 = nCTS auto-flow control Disabled. + * | | |1 = nCTS auto-flow control Enabled. + * |[5] |RTSAUDIREN|nRTS Auto Direction Enable Bit + * | | |When nRTS auto direction is enabled, if the transmitted bytes in the TX buffer is empty, the nRTS signal is inactive. + * | | |0 = nRTS auto direction control Disabled. + * | | |1 = nRTS auto direction control Enabled. + * | | |Note1: This bit is used for nRTS auto direction control for RS485. + * | | |Note2: This bit has effect only when the RTSAUTOEN is not set. + * |[6] |ABREN |Auto-baud Rate Detect Enable Bit + * | | |0 = Auto-baud rate detect function Disabled. + * | | |1 = Auto-baud rate detect function Enabled. + * | | |Note: When the auto - baud rate detect operation finishes, hardware will clear this bit. + * | | |The associated interrupt ABRDETIF (UUART_PROTSTS[9]) will be generated (If ARBIEN (UUART_PROTIEN [1]) is enabled). + * |[9] |DATWKEN |Data Wake-up Mode Enable Bit + * | | |0 = Data wake-up mode Disabled. + * | | |1 = Data wake-up mode Enabled. + * |[10] |CTSWKEN |nCTS Wake-up Mode Enable Bit + * | | |0 = nCTS wake-up mode Disabled. + * | | |1 = nCTS wake-up mode Enabled. + * |[14:11] |WAKECNT |Wake-up Counter + * | | |These bits field indicate how many clock cycle selected by fPDS_CNT do the slave can get the 1st bit (start bit) when the device is wake-up from Power-down mode. + * |[24:16] |BRDETITV |Baud Rate Detection Interval + * | | |This bit fields indicate how many clock cycle selected by TMCNTSRC (UUART_BRGEN [5]) does the slave calculates the baud rate in one bits. + * | | |The order of the bus shall be 1 and 0 step by step (e.g + * | | |the input data pattern shall be 0x55) + * | | |The user can read the value to know the current input baud rate of the bus whenever the ABRDETIF (UUART_PROTCTL[9]) is set. + * | | |Note: This bit can be cleared to 0 by software writing 1 to the BRDETITV. + * |[26] |STICKEN |Stick Parity Enable Bit + * | | |0 = Stick parity Disabled. + * | | |1 = Stick parity Enabled. + * | | |Note: Refer to RS-485 Support section for detail information. + * |[29] |BCEN |Transmit Break Control Enable Bit + * | | |0 = Transmit Break Control Disabled. + * | | |1 = Transmit Break Control Enabled. + * | | |Note: When this bit is set to logic 1, the serial data output (TX) is forced to the Spacing State (logic 0). + * | | |This bit acts only on TX line and has no effect on the transmitter logic. + * |[30] |DGE |Deglitch Enable Bit + * | | |0 = Deglitch Disabled. + * | | |1 = Deglitch Enabled. + * | | |Note: When this bit is set to logic 1, any pulse width less than about 300 ns will be considered a glitch and will be removed in the serial data input (RX). + * | | |This bit acts only on RX line and has no effect on the transmitter logic. + * |[31] |PROTEN |UART Protocol Enable Bit + * | | |0 = UART Protocol Disabled. + * | | |1 = UART Protocol Enabled. + * @var UUART_T::PROTIEN + * Offset: 0x60 USCI Protocol Interrupt Enable Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[1] |ABRIEN |Auto-baud Rate Interrupt Enable Bit + * | | |0 = Auto-baud rate interrupt Disabled. + * | | |1 = Auto-baud rate interrupt Enabled. + * |[2] |RLSIEN |Receive Line Status Interrupt Enable Bit + * | | |0 = Receive line status interrupt Disabled. + * | | |1 = Receive line status interrupt Enabled. + * | | |Note: UUART_PROTSTS[7:5] indicates the current interrupt event for receive line status interrupt. + * @var UUART_T::PROTSTS + * Offset: 0x64 USCI Protocol Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[1] |TXSTIF |Transmit Start Interrupt Flag + * | | |0 = A transmit start interrupt status has not occurred. + * | | |1 = A transmit start interrupt status has occurred. + * | | |Note1: It is cleared by software writing one into this bit. + * | | |Note2: Used for user to load next transmit data when there is no data in transmit buffer. + * |[2] |TXENDIF |Transmit End Interrupt Flag + * | | |0 = A transmit end interrupt status has not occurred. + * | | |1 = A transmit end interrupt status has occurred. + * | | |Note: It is cleared by software writing one into this bit. + * |[3] |RXSTIF |Receive Start Interrupt Flag + * | | |0 = A receive start interrupt status has not occurred. + * | | |1 = A receive start interrupt status has occurred. + * | | |Note: It is cleared by software writing one into this bit. + * |[4] |RXENDIF |Receive End Interrupt Flag + * | | |0 = A receive finish interrupt status has not occurred. + * | | |1 = A receive finish interrupt status has occurred. + * | | |Note: It is cleared by software writing one into this bit. + * |[5] |PARITYERR |Parity Error Flag + * | | |This bit is set to logic 1 whenever the received character does not have a valid parity bit. + * | | |0 = No parity error is generated. + * | | |1 = Parity error is generated. + * | | |Note: This bit can be cleared by write 1 among the BREAK, FRMERR and PARITYERR bits. + * |[6] |FRMERR |Framing Error Flag + * | | |This bit is set to logic 1 whenever the received character does not have a valid stop bit (that is, the stop bit following the last data bit or parity bit is detected as logic 0). + * | | |0 = No framing error is generated. + * | | |1 = Framing error is generated. + * | | |Note: This bit can be cleared by write 1 among the BREAK, FRMERR and PARITYERR bits. + * |[7] |BREAK |Break Flag + * | | |This bit is set to logic 1 whenever the received data input (RX) is held in the spacing state (logic 0) for longer than a full word transmission time (that is, the total time of start bit + data bits + parity + stop bits). + * | | |0 = No Break is generated. + * | | |1 = Break is generated in the receiver bus. + * | | |Note: This bit can be cleared by write 1 among the BREAK, FRMERR and PARITYERR bits. + * |[9] |ABRDETIF |Auto-baud Rate Interrupt Flag + * | | |This bit is set when auto-baud rate detection is done among the falling edge of the input data. + * | | |If the ABRIEN (UUART_PROTCTL[6]) is set, the auto-baud rate interrupt will be generated. + * | | |This bit can be set 4 times when the input data pattern is 0x55 and it is cleared before the next falling edge of the input bus. + * | | |0 = Auto-baud rate detect function is not done. + * | | |1 = One Bit auto-baud rate detect function is done. + * | | |Note: This bit can be cleared by writing 1 to it. + * |[10] |RXBUSY |RX Bus Status Flag (Read Only) + * | | |This bit indicates the busy status of the receiver. + * | | |0 = The receiver is Idle. + * | | |1 = The receiver is BUSY. + * |[11] |ABERRSTS |Auto-baud Rate Error Status + * | | |This bit is set when auto-baud rate detection counter overrun. + * | | |When the auto-baud rate counter overrun, the user shall revise the CLKDIV (UUART_BRGEN[25:16]) value and enable ABREN (UUART_PROTCTL[6]) to detect the correct baud rate again. + * | | |0 = Auto-baud rate detect counter is not overrun. + * | | |1 = Auto-baud rate detect counter is overrun. + * | | |Note1: This bit is set at the same time of ABRDETIF. + * | | |Note2: This bit can be cleared by writing 1 to ABRDETIF or ABERRSTS. + * |[16] |CTSSYNCLV |nCTS Synchronized Level Status (Read Only) + * | | |This bit used to indicate the current status of the internal synchronized nCTS signal. + * | | |0 = The internal synchronized nCTS is low. + * | | |1 = The internal synchronized nCTS is high. + * |[17] |CTSLV |nCTS Pin Status (Read Only) + * | | |This bit used to monitor the current status of nCTS pin input. + * | | |0 = nCTS pin input is low level voltage logic state. + * | | |1 = nCTS pin input is high level voltage logic state. + */ + + __IO uint32_t CTL; /*!< [0x0000] USCI Control Register */ + __IO uint32_t INTEN; /*!< [0x0004] USCI Interrupt Enable Register */ + __IO uint32_t BRGEN; /*!< [0x0008] USCI Baud Rate Generator Register */ + __I uint32_t RESERVE0[1]; + __IO uint32_t DATIN0; /*!< [0x0010] USCI Input Data Signal Configuration Register 0 */ + __I uint32_t RESERVE1[3]; + __IO uint32_t CTLIN0; /*!< [0x0020] USCI Input Control Signal Configuration Register 0 */ + __I uint32_t RESERVE2[1]; + __IO uint32_t CLKIN; /*!< [0x0028] USCI Input Clock Signal Configuration Register */ + __IO uint32_t LINECTL; /*!< [0x002c] USCI Line Control Register */ + __O uint32_t TXDAT; /*!< [0x0030] USCI Transmit Data Register */ + __I uint32_t RXDAT; /*!< [0x0034] USCI Receive Data Register */ + __IO uint32_t BUFCTL; /*!< [0x0038] USCI Transmit/Receive Buffer Control Register */ + __IO uint32_t BUFSTS; /*!< [0x003c] USCI Transmit/Receive Buffer Status Register */ + __IO uint32_t PDMACTL; /*!< [0x0040] USCI PDMA Control Register */ + __I uint32_t RESERVE3[4]; + __IO uint32_t WKCTL; /*!< [0x0054] USCI Wake-up Control Register */ + __IO uint32_t WKSTS; /*!< [0x0058] USCI Wake-up Status Register */ + __IO uint32_t PROTCTL; /*!< [0x005c] USCI Protocol Control Register */ + __IO uint32_t PROTIEN; /*!< [0x0060] USCI Protocol Interrupt Enable Register */ + __IO uint32_t PROTSTS; /*!< [0x0064] USCI Protocol Status Register */ + +} UUART_T; + +/** + @addtogroup UUART_CONST UUART Bit Field Definition + Constant Definitions for UUART Controller + @{ +*/ + +#define UUART_CTL_FUNMODE_Pos (0) /*!< UUART_T::CTL: FUNMODE Position */ +#define UUART_CTL_FUNMODE_Msk (0x7ul << UUART_CTL_FUNMODE_Pos) /*!< UUART_T::CTL: FUNMODE Mask */ + +#define UUART_INTEN_TXSTIEN_Pos (1) /*!< UUART_T::INTEN: TXSTIEN Position */ +#define UUART_INTEN_TXSTIEN_Msk (0x1ul << UUART_INTEN_TXSTIEN_Pos) /*!< UUART_T::INTEN: TXSTIEN Mask */ + +#define UUART_INTEN_TXENDIEN_Pos (2) /*!< UUART_T::INTEN: TXENDIEN Position */ +#define UUART_INTEN_TXENDIEN_Msk (0x1ul << UUART_INTEN_TXENDIEN_Pos) /*!< UUART_T::INTEN: TXENDIEN Mask */ + +#define UUART_INTEN_RXSTIEN_Pos (3) /*!< UUART_T::INTEN: RXSTIEN Position */ +#define UUART_INTEN_RXSTIEN_Msk (0x1ul << UUART_INTEN_RXSTIEN_Pos) /*!< UUART_T::INTEN: RXSTIEN Mask */ + +#define UUART_INTEN_RXENDIEN_Pos (4) /*!< UUART_T::INTEN: RXENDIEN Position */ +#define UUART_INTEN_RXENDIEN_Msk (0x1ul << UUART_INTEN_RXENDIEN_Pos) /*!< UUART_T::INTEN: RXENDIEN Mask */ + +#define UUART_BRGEN_RCLKSEL_Pos (0) /*!< UUART_T::BRGEN: RCLKSEL Position */ +#define UUART_BRGEN_RCLKSEL_Msk (0x1ul << UUART_BRGEN_RCLKSEL_Pos) /*!< UUART_T::BRGEN: RCLKSEL Mask */ + +#define UUART_BRGEN_PTCLKSEL_Pos (1) /*!< UUART_T::BRGEN: PTCLKSEL Position */ +#define UUART_BRGEN_PTCLKSEL_Msk (0x1ul << UUART_BRGEN_PTCLKSEL_Pos) /*!< UUART_T::BRGEN: PTCLKSEL Mask */ + +#define UUART_BRGEN_SPCLKSEL_Pos (2) /*!< UUART_T::BRGEN: SPCLKSEL Position */ +#define UUART_BRGEN_SPCLKSEL_Msk (0x3ul << UUART_BRGEN_SPCLKSEL_Pos) /*!< UUART_T::BRGEN: SPCLKSEL Mask */ + +#define UUART_BRGEN_TMCNTEN_Pos (4) /*!< UUART_T::BRGEN: TMCNTEN Position */ +#define UUART_BRGEN_TMCNTEN_Msk (0x1ul << UUART_BRGEN_TMCNTEN_Pos) /*!< UUART_T::BRGEN: TMCNTEN Mask */ + +#define UUART_BRGEN_TMCNTSRC_Pos (5) /*!< UUART_T::BRGEN: TMCNTSRC Position */ +#define UUART_BRGEN_TMCNTSRC_Msk (0x1ul << UUART_BRGEN_TMCNTSRC_Pos) /*!< UUART_T::BRGEN: TMCNTSRC Mask */ + +#define UUART_BRGEN_PDSCNT_Pos (8) /*!< UUART_T::BRGEN: PDSCNT Position */ +#define UUART_BRGEN_PDSCNT_Msk (0x3ul << UUART_BRGEN_PDSCNT_Pos) /*!< UUART_T::BRGEN: PDSCNT Mask */ + +#define UUART_BRGEN_DSCNT_Pos (10) /*!< UUART_T::BRGEN: DSCNT Position */ +#define UUART_BRGEN_DSCNT_Msk (0x1ful << UUART_BRGEN_DSCNT_Pos) /*!< UUART_T::BRGEN: DSCNT Mask */ + +#define UUART_BRGEN_CLKDIV_Pos (16) /*!< UUART_T::BRGEN: CLKDIV Position */ +#define UUART_BRGEN_CLKDIV_Msk (0x3fful << UUART_BRGEN_CLKDIV_Pos) /*!< UUART_T::BRGEN: CLKDIV Mask */ + +#define UUART_DATIN0_SYNCSEL_Pos (0) /*!< UUART_T::DATIN0: SYNCSEL Position */ +#define UUART_DATIN0_SYNCSEL_Msk (0x1ul << UUART_DATIN0_SYNCSEL_Pos) /*!< UUART_T::DATIN0: SYNCSEL Mask */ + +#define UUART_DATIN0_ININV_Pos (2) /*!< UUART_T::DATIN0: ININV Position */ +#define UUART_DATIN0_ININV_Msk (0x1ul << UUART_DATIN0_ININV_Pos) /*!< UUART_T::DATIN0: ININV Mask */ + +#define UUART_DATIN0_EDGEDET_Pos (3) /*!< UUART_T::DATIN0: EDGEDET Position */ +#define UUART_DATIN0_EDGEDET_Msk (0x3ul << UUART_DATIN0_EDGEDET_Pos) /*!< UUART_T::DATIN0: EDGEDET Mask */ + +#define UUART_CTLIN0_SYNCSEL_Pos (0) /*!< UUART_T::CTLIN0: SYNCSEL Position */ +#define UUART_CTLIN0_SYNCSEL_Msk (0x1ul << UUART_CTLIN0_SYNCSEL_Pos) /*!< UUART_T::CTLIN0: SYNCSEL Mask */ + +#define UUART_CTLIN0_ININV_Pos (2) /*!< UUART_T::CTLIN0: ININV Position */ +#define UUART_CTLIN0_ININV_Msk (0x1ul << UUART_CTLIN0_ININV_Pos) /*!< UUART_T::CTLIN0: ININV Mask */ + +#define UUART_CLKIN_SYNCSEL_Pos (0) /*!< UUART_T::CLKIN: SYNCSEL Position */ +#define UUART_CLKIN_SYNCSEL_Msk (0x1ul << UUART_CLKIN_SYNCSEL_Pos) /*!< UUART_T::CLKIN: SYNCSEL Mask */ + +#define UUART_LINECTL_LSB_Pos (0) /*!< UUART_T::LINECTL: LSB Position */ +#define UUART_LINECTL_LSB_Msk (0x1ul << UUART_LINECTL_LSB_Pos) /*!< UUART_T::LINECTL: LSB Mask */ + +#define UUART_LINECTL_DATOINV_Pos (5) /*!< UUART_T::LINECTL: DATOINV Position */ +#define UUART_LINECTL_DATOINV_Msk (0x1ul << UUART_LINECTL_DATOINV_Pos) /*!< UUART_T::LINECTL: DATOINV Mask */ + +#define UUART_LINECTL_CTLOINV_Pos (7) /*!< UUART_T::LINECTL: CTLOINV Position */ +#define UUART_LINECTL_CTLOINV_Msk (0x1ul << UUART_LINECTL_CTLOINV_Pos) /*!< UUART_T::LINECTL: CTLOINV Mask */ + +#define UUART_LINECTL_DWIDTH_Pos (8) /*!< UUART_T::LINECTL: DWIDTH Position */ +#define UUART_LINECTL_DWIDTH_Msk (0xful << UUART_LINECTL_DWIDTH_Pos) /*!< UUART_T::LINECTL: DWIDTH Mask */ + +#define UUART_TXDAT_TXDAT_Pos (0) /*!< UUART_T::TXDAT: TXDAT Position */ +#define UUART_TXDAT_TXDAT_Msk (0xfffful << UUART_TXDAT_TXDAT_Pos) /*!< UUART_T::TXDAT: TXDAT Mask */ + +#define UUART_RXDAT_RXDAT_Pos (0) /*!< UUART_T::RXDAT: RXDAT Position */ +#define UUART_RXDAT_RXDAT_Msk (0xfffful << UUART_RXDAT_RXDAT_Pos) /*!< UUART_T::RXDAT: RXDAT Mask */ + +#define UUART_BUFCTL_TXCLR_Pos (7) /*!< UUART_T::BUFCTL: TXCLR Position */ +#define UUART_BUFCTL_TXCLR_Msk (0x1ul << UUART_BUFCTL_TXCLR_Pos) /*!< UUART_T::BUFCTL: TXCLR Mask */ + +#define UUART_BUFCTL_RXOVIEN_Pos (14) /*!< UUART_T::BUFCTL: RXOVIEN Position */ +#define UUART_BUFCTL_RXOVIEN_Msk (0x1ul << UUART_BUFCTL_RXOVIEN_Pos) /*!< UUART_T::BUFCTL: RXOVIEN Mask */ + +#define UUART_BUFCTL_RXCLR_Pos (15) /*!< UUART_T::BUFCTL: RXCLR Position */ +#define UUART_BUFCTL_RXCLR_Msk (0x1ul << UUART_BUFCTL_RXCLR_Pos) /*!< UUART_T::BUFCTL: RXCLR Mask */ + +#define UUART_BUFCTL_TXRST_Pos (16) /*!< UUART_T::BUFCTL: TXRST Position */ +#define UUART_BUFCTL_TXRST_Msk (0x1ul << UUART_BUFCTL_TXRST_Pos) /*!< UUART_T::BUFCTL: TXRST Mask */ + +#define UUART_BUFCTL_RXRST_Pos (17) /*!< UUART_T::BUFCTL: RXRST Position */ +#define UUART_BUFCTL_RXRST_Msk (0x1ul << UUART_BUFCTL_RXRST_Pos) /*!< UUART_T::BUFCTL: RXRST Mask */ + +#define UUART_BUFSTS_RXEMPTY_Pos (0) /*!< UUART_T::BUFSTS: RXEMPTY Position */ +#define UUART_BUFSTS_RXEMPTY_Msk (0x1ul << UUART_BUFSTS_RXEMPTY_Pos) /*!< UUART_T::BUFSTS: RXEMPTY Mask */ + +#define UUART_BUFSTS_RXFULL_Pos (1) /*!< UUART_T::BUFSTS: RXFULL Position */ +#define UUART_BUFSTS_RXFULL_Msk (0x1ul << UUART_BUFSTS_RXFULL_Pos) /*!< UUART_T::BUFSTS: RXFULL Mask */ + +#define UUART_BUFSTS_RXOVIF_Pos (3) /*!< UUART_T::BUFSTS: RXOVIF Position */ +#define UUART_BUFSTS_RXOVIF_Msk (0x1ul << UUART_BUFSTS_RXOVIF_Pos) /*!< UUART_T::BUFSTS: RXOVIF Mask */ + +#define UUART_BUFSTS_TXEMPTY_Pos (8) /*!< UUART_T::BUFSTS: TXEMPTY Position */ +#define UUART_BUFSTS_TXEMPTY_Msk (0x1ul << UUART_BUFSTS_TXEMPTY_Pos) /*!< UUART_T::BUFSTS: TXEMPTY Mask */ + +#define UUART_BUFSTS_TXFULL_Pos (9) /*!< UUART_T::BUFSTS: TXFULL Position */ +#define UUART_BUFSTS_TXFULL_Msk (0x1ul << UUART_BUFSTS_TXFULL_Pos) /*!< UUART_T::BUFSTS: TXFULL Mask */ + +#define UUART_PDMACTL_PDMARST_Pos (0) /*!< UUART_T::PDMACTL: PDMARST Position */ +#define UUART_PDMACTL_PDMARST_Msk (0x1ul << UUART_PDMACTL_PDMARST_Pos) /*!< UUART_T::PDMACTL: PDMARST Mask */ + +#define UUART_PDMACTL_TXPDMAEN_Pos (1) /*!< UUART_T::PDMACTL: TXPDMAEN Position */ +#define UUART_PDMACTL_TXPDMAEN_Msk (0x1ul << UUART_PDMACTL_TXPDMAEN_Pos) /*!< UUART_T::PDMACTL: TXPDMAEN Mask */ + +#define UUART_PDMACTL_RXPDMAEN_Pos (2) /*!< UUART_T::PDMACTL: RXPDMAEN Position */ +#define UUART_PDMACTL_RXPDMAEN_Msk (0x1ul << UUART_PDMACTL_RXPDMAEN_Pos) /*!< UUART_T::PDMACTL: RXPDMAEN Mask */ + +#define UUART_PDMACTL_PDMAEN_Pos (3) /*!< UUART_T::PDMACTL: PDMAEN Position */ +#define UUART_PDMACTL_PDMAEN_Msk (0x1ul << UUART_PDMACTL_PDMAEN_Pos) /*!< UUART_T::PDMACTL: PDMAEN Mask */ + +#define UUART_WKCTL_WKEN_Pos (0) /*!< UUART_T::WKCTL: WKEN Position */ +#define UUART_WKCTL_WKEN_Msk (0x1ul << UUART_WKCTL_WKEN_Pos) /*!< UUART_T::WKCTL: WKEN Mask */ + +#define UUART_WKCTL_PDBOPT_Pos (2) /*!< UUART_T::WKCTL: PDBOPT Position */ +#define UUART_WKCTL_PDBOPT_Msk (0x1ul << UUART_WKCTL_PDBOPT_Pos) /*!< UUART_T::WKCTL: PDBOPT Mask */ + +#define UUART_WKSTS_WKF_Pos (0) /*!< UUART_T::WKSTS: WKF Position */ +#define UUART_WKSTS_WKF_Msk (0x1ul << UUART_WKSTS_WKF_Pos) /*!< UUART_T::WKSTS: WKF Mask */ + +#define UUART_PROTCTL_STOPB_Pos (0) /*!< UUART_T::PROTCTL: STOPB Position */ +#define UUART_PROTCTL_STOPB_Msk (0x1ul << UUART_PROTCTL_STOPB_Pos) /*!< UUART_T::PROTCTL: STOPB Mask */ + +#define UUART_PROTCTL_PARITYEN_Pos (1) /*!< UUART_T::PROTCTL: PARITYEN Position */ +#define UUART_PROTCTL_PARITYEN_Msk (0x1ul << UUART_PROTCTL_PARITYEN_Pos) /*!< UUART_T::PROTCTL: PARITYEN Mask */ + +#define UUART_PROTCTL_EVENPARITY_Pos (2) /*!< UUART_T::PROTCTL: EVENPARITY Position */ +#define UUART_PROTCTL_EVENPARITY_Msk (0x1ul << UUART_PROTCTL_EVENPARITY_Pos) /*!< UUART_T::PROTCTL: EVENPARITY Mask */ + +#define UUART_PROTCTL_RTSAUTOEN_Pos (3) /*!< UUART_T::PROTCTL: RTSAUTOEN Position */ +#define UUART_PROTCTL_RTSAUTOEN_Msk (0x1ul << UUART_PROTCTL_RTSAUTOEN_Pos) /*!< UUART_T::PROTCTL: RTSAUTOEN Mask */ + +#define UUART_PROTCTL_CTSAUTOEN_Pos (4) /*!< UUART_T::PROTCTL: CTSAUTOEN Position */ +#define UUART_PROTCTL_CTSAUTOEN_Msk (0x1ul << UUART_PROTCTL_CTSAUTOEN_Pos) /*!< UUART_T::PROTCTL: CTSAUTOEN Mask */ + +#define UUART_PROTCTL_RTSAUDIREN_Pos (5) /*!< UUART_T::PROTCTL: RTSAUDIREN Position */ +#define UUART_PROTCTL_RTSAUDIREN_Msk (0x1ul << UUART_PROTCTL_RTSAUDIREN_Pos) /*!< UUART_T::PROTCTL: RTSAUDIREN Mask */ + +#define UUART_PROTCTL_ABREN_Pos (6) /*!< UUART_T::PROTCTL: ABREN Position */ +#define UUART_PROTCTL_ABREN_Msk (0x1ul << UUART_PROTCTL_ABREN_Pos) /*!< UUART_T::PROTCTL: ABREN Mask */ + +#define UUART_PROTCTL_DATWKEN_Pos (9) /*!< UUART_T::PROTCTL: DATWKEN Position */ +#define UUART_PROTCTL_DATWKEN_Msk (0x1ul << UUART_PROTCTL_DATWKEN_Pos) /*!< UUART_T::PROTCTL: DATWKEN Mask */ + +#define UUART_PROTCTL_CTSWKEN_Pos (10) /*!< UUART_T::PROTCTL: CTSWKEN Position */ +#define UUART_PROTCTL_CTSWKEN_Msk (0x1ul << UUART_PROTCTL_CTSWKEN_Pos) /*!< UUART_T::PROTCTL: CTSWKEN Mask */ + +#define UUART_PROTCTL_WAKECNT_Pos (11) /*!< UUART_T::PROTCTL: WAKECNT Position */ +#define UUART_PROTCTL_WAKECNT_Msk (0xful << UUART_PROTCTL_WAKECNT_Pos) /*!< UUART_T::PROTCTL: WAKECNT Mask */ + +#define UUART_PROTCTL_BRDETITV_Pos (16) /*!< UUART_T::PROTCTL: BRDETITV Position */ +#define UUART_PROTCTL_BRDETITV_Msk (0x1fful << UUART_PROTCTL_BRDETITV_Pos) /*!< UUART_T::PROTCTL: BRDETITV Mask */ + +#define UUART_PROTCTL_STICKEN_Pos (26) /*!< UUART_T::PROTCTL: STICKEN Position */ +#define UUART_PROTCTL_STICKEN_Msk (0x1ul << UUART_PROTCTL_STICKEN_Pos) /*!< UUART_T::PROTCTL: STICKEN Mask */ + +#define UUART_PROTCTL_BCEN_Pos (29) /*!< UUART_T::PROTCTL: BCEN Position */ +#define UUART_PROTCTL_BCEN_Msk (0x1ul << UUART_PROTCTL_BCEN_Pos) /*!< UUART_T::PROTCTL: BCEN Mask */ + +#define UUART_PROTCTL_DGE_Pos (30) /*!< UUART_T::PROTCTL: DGE Position */ +#define UUART_PROTCTL_DGE_Msk (0x1ul << UUART_PROTCTL_DGE_Pos) /*!< UUART_T::PROTCTL: DGE Mask */ + +#define UUART_PROTCTL_PROTEN_Pos (31) /*!< UUART_T::PROTCTL: PROTEN Position */ +#define UUART_PROTCTL_PROTEN_Msk (0x1ul << UUART_PROTCTL_PROTEN_Pos) /*!< UUART_T::PROTCTL: PROTEN Mask */ + +#define UUART_PROTIEN_ABRIEN_Pos (1) /*!< UUART_T::PROTIEN: ABRIEN Position */ +#define UUART_PROTIEN_ABRIEN_Msk (0x1ul << UUART_PROTIEN_ABRIEN_Pos) /*!< UUART_T::PROTIEN: ABRIEN Mask */ + +#define UUART_PROTIEN_RLSIEN_Pos (2) /*!< UUART_T::PROTIEN: RLSIEN Position */ +#define UUART_PROTIEN_RLSIEN_Msk (0x1ul << UUART_PROTIEN_RLSIEN_Pos) /*!< UUART_T::PROTIEN: RLSIEN Mask */ + +#define UUART_PROTSTS_TXSTIF_Pos (1) /*!< UUART_T::PROTSTS: TXSTIF Position */ +#define UUART_PROTSTS_TXSTIF_Msk (0x1ul << UUART_PROTSTS_TXSTIF_Pos) /*!< UUART_T::PROTSTS: TXSTIF Mask */ + +#define UUART_PROTSTS_TXENDIF_Pos (2) /*!< UUART_T::PROTSTS: TXENDIF Position */ +#define UUART_PROTSTS_TXENDIF_Msk (0x1ul << UUART_PROTSTS_TXENDIF_Pos) /*!< UUART_T::PROTSTS: TXENDIF Mask */ + +#define UUART_PROTSTS_RXSTIF_Pos (3) /*!< UUART_T::PROTSTS: RXSTIF Position */ +#define UUART_PROTSTS_RXSTIF_Msk (0x1ul << UUART_PROTSTS_RXSTIF_Pos) /*!< UUART_T::PROTSTS: RXSTIF Mask */ + +#define UUART_PROTSTS_RXENDIF_Pos (4) /*!< UUART_T::PROTSTS: RXENDIF Position */ +#define UUART_PROTSTS_RXENDIF_Msk (0x1ul << UUART_PROTSTS_RXENDIF_Pos) /*!< UUART_T::PROTSTS: RXENDIF Mask */ + +#define UUART_PROTSTS_PARITYERR_Pos (5) /*!< UUART_T::PROTSTS: PARITYERR Position */ +#define UUART_PROTSTS_PARITYERR_Msk (0x1ul << UUART_PROTSTS_PARITYERR_Pos) /*!< UUART_T::PROTSTS: PARITYERR Mask */ + +#define UUART_PROTSTS_FRMERR_Pos (6) /*!< UUART_T::PROTSTS: FRMERR Position */ +#define UUART_PROTSTS_FRMERR_Msk (0x1ul << UUART_PROTSTS_FRMERR_Pos) /*!< UUART_T::PROTSTS: FRMERR Mask */ + +#define UUART_PROTSTS_BREAK_Pos (7) /*!< UUART_T::PROTSTS: BREAK Position */ +#define UUART_PROTSTS_BREAK_Msk (0x1ul << UUART_PROTSTS_BREAK_Pos) /*!< UUART_T::PROTSTS: BREAK Mask */ + +#define UUART_PROTSTS_ABRDETIF_Pos (9) /*!< UUART_T::PROTSTS: ABRDETIF Position */ +#define UUART_PROTSTS_ABRDETIF_Msk (0x1ul << UUART_PROTSTS_ABRDETIF_Pos) /*!< UUART_T::PROTSTS: ABRDETIF Mask */ + +#define UUART_PROTSTS_RXBUSY_Pos (10) /*!< UUART_T::PROTSTS: RXBUSY Position */ +#define UUART_PROTSTS_RXBUSY_Msk (0x1ul << UUART_PROTSTS_RXBUSY_Pos) /*!< UUART_T::PROTSTS: RXBUSY Mask */ + +#define UUART_PROTSTS_ABERRSTS_Pos (11) /*!< UUART_T::PROTSTS: ABERRSTS Position */ +#define UUART_PROTSTS_ABERRSTS_Msk (0x1ul << UUART_PROTSTS_ABERRSTS_Pos) /*!< UUART_T::PROTSTS: ABERRSTS Mask */ + +#define UUART_PROTSTS_CTSSYNCLV_Pos (16) /*!< UUART_T::PROTSTS: CTSSYNCLV Position */ +#define UUART_PROTSTS_CTSSYNCLV_Msk (0x1ul << UUART_PROTSTS_CTSSYNCLV_Pos) /*!< UUART_T::PROTSTS: CTSSYNCLV Mask */ + +#define UUART_PROTSTS_CTSLV_Pos (17) /*!< UUART_T::PROTSTS: CTSLV Position */ +#define UUART_PROTSTS_CTSLV_Msk (0x1ul << UUART_PROTSTS_CTSLV_Pos) /*!< UUART_T::PROTSTS: CTSLV Mask */ + +/**@}*/ /* UUART_CONST */ +/**@}*/ /* end of UUART register group */ +/**@}*/ /* end of REGISTER group */ + +#endif /* __UUART_REG_H__ */ diff --git a/Ubiquitous/XiZi/board/nuvoton-m2354/third_party_driver/include/Regs/wdt_reg.h b/Ubiquitous/XiZi/board/nuvoton-m2354/third_party_driver/include/Regs/wdt_reg.h new file mode 100644 index 0000000..4d4b79c --- /dev/null +++ b/Ubiquitous/XiZi/board/nuvoton-m2354/third_party_driver/include/Regs/wdt_reg.h @@ -0,0 +1,177 @@ +/**************************************************************************//** + * @file wdt_reg.h + * @version V1.00 + * @brief WDT register definition header file + * + * @copyright SPDX-License-Identifier: Apache-2.0 + * @copyright Copyright (C) 2020 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ +#ifndef __WDT_REG_H__ +#define __WDT_REG_H__ + +/** @addtogroup REGISTER Control Register + + @{ + +*/ + + +/*---------------------- Watch Dog Timer Controller -------------------------*/ +/** + @addtogroup WDT Watch Dog Timer Controller(WDT) + Memory Mapped Structure for WDT Controller + @{ +*/ + +typedef struct +{ + + + /** + * @var WDT_T::CTL + * Offset: 0x00 WDT Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[1] |RSTEN |WDT Time-out Reset Enable Control (Write Protect) + * | | |Setting this bit will enable the WDT time-out reset system function If the WDT up counter value has not been cleared after the specific WDT reset delay period expires. + * | | |0 = WDT time-out reset system function Disabled. + * | | |1 = WDT time-out reset system function Enabled. + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * |[2] |RSTF |WDT Time-out Reset Flag + * | | |This bit indicates the system has been reset by WDT time-out reset system event or not. + * | | |0 = WDT time-out reset system event did not occur. + * | | |1 = WDT time-out reset system event has been occurred. + * | | |Note: This bit is cleared by writing 1 to it. + * |[3] |IF |WDT Time-out Interrupt Flag + * | | |This bit will set to 1 while WDT up counter value reaches the selected WDT time-out interval + * | | |0 = WDT time-out interrupt event interrupt did not occur. + * | | |1 = WDT time-out interrupt interrupt event occurred. + * | | |Note: This bit is cleared by writing 1 to it. + * |[4] |WKEN |WDT Time-out Wake-up Function Control (Write Protect) + * | | |If this bit is set to 1, while WDT time-out interrupt flag IF (WDT_CTL[3]) is generated to 1 and interrupt enable bit INTEN (WDT_CTL[6]) is enabled, the WDT time-out interrupt signal will generate a event to trigger CPU wake-up trigger event to chip. + * | | |0 = Trigger wWake-up trigger event function Disabled if WDT time-out interrupt signal generated. + * | | |1 = Trigger Wake-up trigger event function Enabled if WDT time-out interrupt signal generated. + * | | |Note1: This bit is write protected. Refer to the SYS_REGLCTL register. + * | | |Note2: Chip can be woken-up by while WDT time-out interrupt signal generated only if WDT clock source is selected to LIRC or LXT (32 kHz). + * |[5] |WKF |WDT Time-out Wake-up Flag (Write Protect) + * | | |This bit indicates the WDT time-out event has triggered interrupt chip wake-up or not.flag status of WDT + * | | |0 = WDT does not cause chip wake-up. + * | | |1 = Chip wake-up from Idle or Power-down mode if when WDT time-out interrupt signal is generated. + * | | |Note1: This bit is write protected. Refer to the SYS_REGLCTL register. + * | | |Note2: This bit is cleared by writing 1 to it. + * |[6] |INTEN |WDT Time-out Interrupt Enable Control (Write Protect) + * | | |If this bit is enabled, when WDT time-out event occurs, the IF (WDT_CTL[3]) will be set to 1 and the WDT time-out interrupt signal is generated and inform to CPU. + * | | |0 = WDT time-out interrupt Disabled. + * | | |1 = WDT time-out interrupt Enabled. + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * |[7] |WDTEN |WDT Enable Control (Write Protect) + * | | |0 = Set WDT counter stop Disabled, and (This action will reset the internal up counter value will be reset also). + * | | |1 = Set WDT counter start Enabled. + * | | |Note1: This bit is write protected. Refer to the SYS_REGLCTL register. + * | | |Note2: Perform enable or disable WDTEN bit needs 2 * WDT_CLK period to become active, user can read SYNC (WDT_CTL[30]) to check enable/disable command is completed or not. + * | | |Note32: If CWDTEN[2:0] (combined by with Config0[31] and Config0[4:3]) bits is not configure to 0x111, this bit is forced as 1 and user cannot change this bit to 0. + * | | |Note3: This bit disabled needs 2 * WDT_CLK. + * |[11:8] |TOUTSEL |WDT Time-out Interval Selection (Write Protect) + * | | |These three bits select the time-out interval period after for the WDT starts counting. + * | | |000 = 2^4 * WDT_CLK. + * | | |001 = 2^6 * WDT_CLK. + * | | |010 = 2^8 * WDT_CLK. + * | | |011 = 2^10 * WDT_CLK. + * | | |100 = 2^12 * WDT_CLK. + * | | |101 = 2^14 * WDT_CLK. + * | | |110 = 2^16 * WDT_CLK. + * | | |111 = 2^18 * WDT_CLK. + * | | |111 = 2^20 * WDT_CLK. + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * |[30] |SYNC |WDT Enable Control SYNC SYNC Flag Indicator (Read Only) + * | | |If use to synchronization, software er can check execute enable/disable this flag after enable WDTEN (WDT_CTL[7]), this flag can be indicated enable/disable WDTEN function is become completed or not active or not.. + * | | |SYNC delay is + * | | |0 = Set WDTEN bit is WDT enable control synccompletedhronizing is completion. + * | | |1 = Set WDTEN bit WDT enable control is synchronizing and not become active yet.. + * | | |Note: Perform enable or disable WDTEN bit + * | | |This bit enabled needs 2 * WDT_CLK period to become active. + * |[31] |ICEDEBUG |ICE Debug Mode Acknowledge Disable Control (Write Protect) + * | | |0 = ICE debug mode acknowledgment affects WDT counting. + * | | |WDT up counter will be held while CPU is held by ICE. + * | | |1 = ICE debug mode acknowledgment Disabled. + * | | |WDT up counter will keep going no matter CPU is held by ICE or not. + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * @var WDT_T::ALTCTL + * Offset: 0x04 WDT Alternative Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[1:0] |RSTDSEL |WDT Reset Delay Period Selection (Write Protect) + * | | |When WDT time-out event happened, user has a time named WDT Reset Delay Period to clear execute WDT counter by setting RSTCNT (WDT_CTL[0]) reset to prevent WDT time-out reset system occurred happened + * | | |User can select a suitable setting of RSTDSEL for different application program WDT Reset Delay Period. + * | | |00 = WDT Reset Delay Period is 1026 * WDT_CLK. + * | | |01 = WDT Reset Delay Period is 130 * WDT_CLK. + * | | |10 = WDT Reset Delay Period is 18 * WDT_CLK. + * | | |11 = WDT Reset Delay Period is 3 * WDT_CLK. + * | | |Note1: This bit is write protected. Refer to the SYS_REGLCTL register. + * | | |Note2: This register will be reset to 0 if WDT time-out reset system event occurred happened. + * @var WDT_T::RSTCNT + * Offset: 0x08 WDT Reset Counter Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |RSTCNT |WDT Reset Counter Register + * | | |Writing 0x00005AA5 to this register field will reset the internal 18-bit WDT up counter value to 0. + * | | |Note: This WDT_RSTCNT is not write protected, but this RSTCNT (WDT_CTL[0]) is write protected. + * | | |Note: Perform RSTCNT to reset counter needs 2 * WDT_CLK period to become active. + */ + __IO uint32_t CTL; /*!< [0x0000] WDT Control Register */ + __IO uint32_t ALTCTL; /*!< [0x0004] WDT Alternative Control Register */ + __O uint32_t RSTCNT; /*!< [0x0008] WDT Reset Counter Register */ + +} WDT_T; + +/** + @addtogroup WDT_CONST WDT Bit Field Definition + Constant Definitions for WDT Controller + @{ +*/ + +#define WDT_CTL_RSTEN_Pos (1) /*!< WDT_T::CTL: RSTEN Position */ +#define WDT_CTL_RSTEN_Msk (0x1ul << WDT_CTL_RSTEN_Pos) /*!< WDT_T::CTL: RSTEN Mask */ + +#define WDT_CTL_RSTF_Pos (2) /*!< WDT_T::CTL: RSTF Position */ +#define WDT_CTL_RSTF_Msk (0x1ul << WDT_CTL_RSTF_Pos) /*!< WDT_T::CTL: RSTF Mask */ + +#define WDT_CTL_IF_Pos (3) /*!< WDT_T::CTL: IF Position */ +#define WDT_CTL_IF_Msk (0x1ul << WDT_CTL_IF_Pos) /*!< WDT_T::CTL: IF Mask */ + +#define WDT_CTL_WKEN_Pos (4) /*!< WDT_T::CTL: WKEN Position */ +#define WDT_CTL_WKEN_Msk (0x1ul << WDT_CTL_WKEN_Pos) /*!< WDT_T::CTL: WKEN Mask */ + +#define WDT_CTL_WKF_Pos (5) /*!< WDT_T::CTL: WKF Position */ +#define WDT_CTL_WKF_Msk (0x1ul << WDT_CTL_WKF_Pos) /*!< WDT_T::CTL: WKF Mask */ + +#define WDT_CTL_INTEN_Pos (6) /*!< WDT_T::CTL: INTEN Position */ +#define WDT_CTL_INTEN_Msk (0x1ul << WDT_CTL_INTEN_Pos) /*!< WDT_T::CTL: INTEN Mask */ + +#define WDT_CTL_WDTEN_Pos (7) /*!< WDT_T::CTL: WDTEN Position */ +#define WDT_CTL_WDTEN_Msk (0x1ul << WDT_CTL_WDTEN_Pos) /*!< WDT_T::CTL: WDTEN Mask */ + +#define WDT_CTL_TOUTSEL_Pos (8) /*!< WDT_T::CTL: TOUTSEL Position */ +#define WDT_CTL_TOUTSEL_Msk (0xful << WDT_CTL_TOUTSEL_Pos) /*!< WDT_T::CTL: TOUTSEL Mask */ + +#define WDT_CTL_SYNC_Pos (30) /*!< WDT_T::CTL: SYNC Position */ +#define WDT_CTL_SYNC_Msk (0x1ul << WDT_CTL_SYNC_Pos) /*!< WDT_T::CTL: SYNC Mask */ + +#define WDT_CTL_ICEDEBUG_Pos (31) /*!< WDT_T::CTL: ICEDEBUG Position */ +#define WDT_CTL_ICEDEBUG_Msk (0x1ul << WDT_CTL_ICEDEBUG_Pos) /*!< WDT_T::CTL: ICEDEBUG Mask */ + +#define WDT_ALTCTL_RSTDSEL_Pos (0) /*!< WDT_T::ALTCTL: RSTDSEL Position */ +#define WDT_ALTCTL_RSTDSEL_Msk (0x3ul << WDT_ALTCTL_RSTDSEL_Pos) /*!< WDT_T::ALTCTL: RSTDSEL Mask */ + +#define WDT_RSTCNT_RSTCNT_Pos (0) /*!< WDT_T::RSTCNT: RSTCNT Position */ +#define WDT_RSTCNT_RSTCNT_Msk (0xfffffffful << WDT_RSTCNT_RSTCNT_Pos) /*!< WDT_T::RSTCNT: RSTCNT Mask */ + + +/**@}*/ /* WDT_CONST */ +/**@}*/ /* end of WDT register group */ +/**@}*/ /* end of REGISTER group */ + +#endif /* __WDT_REG_H__ */ diff --git a/Ubiquitous/XiZi/board/nuvoton-m2354/third_party_driver/include/Regs/wwdt_reg.h b/Ubiquitous/XiZi/board/nuvoton-m2354/third_party_driver/include/Regs/wwdt_reg.h new file mode 100644 index 0000000..048fea1 --- /dev/null +++ b/Ubiquitous/XiZi/board/nuvoton-m2354/third_party_driver/include/Regs/wwdt_reg.h @@ -0,0 +1,148 @@ +/**************************************************************************//** + * @file wwdt_reg.h + * @version V1.00 + * @brief WWDT register definition header file + * + * @copyright SPDX-License-Identifier: Apache-2.0 + * @copyright Copyright (C) 2020 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ +#ifndef __WWDT_REG_H__ +#define __WWDT_REG_H__ + +/** @addtogroup REGISTER Control Register + + @{ + +*/ + + +/*---------------------- Window Watchdog Timer -------------------------*/ +/** + @addtogroup WWDT Window Watchdog Timer(WWDT) + Memory Mapped Structure for WWDT Controller + @{ +*/ + +typedef struct +{ + + + /** + * @var WWDT_T::RLDCNT + * Offset: 0x00 WWDT Reload Counter Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |RLDCNT |WWDT Reload Counter Register + * | | |Writing only 0x00005AA5 to this register will reload the WWDT counter value to 0x3F. + * | | |Note1: User can only write execute WWDT_RLDCNT register to the reload WWDT counter value command when current current WWDT counter value CNTDAT (WWDT_CNT[5:0]) is between 10 and CMPDAT (WWDT_CTL[21:16]) + * | | |If user writes 0x00005AA5 in WWDT_RLDCNT register when current current CNTDATWWDT counter value is larger than CMPDAT, WWDT reset signal system event will be generated immediately. + * | | |Note2: Execute WWDT counter reload always needs (WWDT_CLK *3) period to reload CNTDAT to 0x3F and internal prescale counter will be reset also. + * @var WWDT_T::CTL + * Offset: 0x04 WWDT Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |WWDTEN |WWDT Enable Control Bit + * | | |Set this bit to enable start WWDT counter counting. + * | | |0 = WWDT counter is stopped. + * | | |1 = WWDT counter is starting counting. + * |[1] |INTEN |WWDT Interrupt Enable Control Bit + * | | |If this bit is enabled, when WWDTIF (WWDT_STATUS[0]) is set to 1, the WWDT counter compare match interrupt signal is generated and inform to CPU. + * | | |0 = WWDT counter compare match interrupt Disabled. + * | | |1 = WWDT counter compare match interrupt Enabled. + * |[11:8] |PSCSEL |WWDT Counter Prescale Period Selection + * | | |0000 = Pre-scale is 1; Max time-out period is 1 * 64 * WWDT_CLK. + * | | |0001 = Pre-scale is 2; Max time-out period is 2 * 64 * WWDT_CLK. + * | | |0010 = Pre-scale is 4; Max time-out period is 4 * 64 * WWDT_CLK. + * | | |0011 = Pre-scale is 8; Max time-out period is 8 * 64 * WWDT_CLK. + * | | |0100 = Pre-scale is 16; Max time-out period is 16 * 64 * WWDT_CLK. + * | | |0101 = Pre-scale is 32; Max time-out period is 32 * 64 * WWDT_CLK. + * | | |0110 = Pre-scale is 64; Max time-out period is 64 * 64 * WWDT_CLK. + * | | |0111 = Pre-scale is 128; Max time-out period is 128 * 64 * WWDT_CLK. + * | | |1000 = Pre-scale is 192; Max time-out period is 192 * 64 * WWDT_CLK. + * | | |1001 = Pre-scale is 256; Max time-out period is 256 * 64 * WWDT_CLK. + * | | |1010 = Pre-scale is 384; Max time-out period is 384 * 64 * WWDT_CLK. + * | | |1011 = Pre-scale is 512; Max time-out period is 512 * 64 * WWDT_CLK. + * | | |1100 = Pre-scale is 768; Max time-out period is 768 * 64 * WWDT_CLK. + * | | |1101 = Pre-scale is 1024; Max time-out period is 1024 * 64 * WWDT_CLK. + * | | |1110 = Pre-scale is 1536; Max time-out period is 1536 * 64 * WWDT_CLK. + * | | |1111 = Pre-scale is 2048; Max time-out period is 2048 * 64 * WWDT_CLK. + * |[21:16] |CMPDAT |WWDT Window Compare Register Value + * | | |Set this register field to adjust the valid reload window interval when WWDTIF (WWDT_STATUS[0]) is generated.. + * | | |Note: User can only write WWDT_RLDCNT register to reload WWDT counter value when current WWDT CNTDAT (WWDT_CNT[5:]) is counter value between 10 and CMPDAT + * | | |If user writes 0x00005AA5 in WWDT_RLDCNT register when current WWDT counter value CNTDAT is larger than CMPDAT, WWDT reset system event signal will be generated immediately. + * |[31] |ICEDEBUG |ICE Debug Mode Acknowledge Disable Control + * | | |0 = ICE debug mode acknowledgment effects WWDT counter counting. + * | | |WWDT down counter will be held while CPU is held by ICE. + * | | |1 = ICE debug mode acknowledgment Disabled. + * | | |WWDT down counter will keep going counting no matter CPU is held by ICE or not. + * @var WWDT_T::STATUS + * Offset: 0x08 WWDT Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |WWDTIF |WWDT Compare Match Interrupt Flag + * | | |This bit indicates the that current CNTDAT (WWDT_CNT[5:0]) matches the CMPDAT (WWDT_CTL[21:16])interrupt flag status of WWDT while WWDT counter value matches CMPDAT (WWDT_CTL[21:16]). + * | | |0 = No effect. + * | | |1 = WWDT WWDT CNTDAT counter value matches the CMPDAT. + * | | |Note: This bit is cleared by writing 1 to it. + * |[1] |WWDTRF |WWDT Timer-out Reset System Flag + * | | |If this bit is set to 1, it This bit indicates the that system has been reset by WWDT counter time-out reset system event.or not. + * | | |0 = WWDT time-out reset system event did not occur. + * | | |1 = WWDT time-out reset system event occurred. + * | | |Note: This bit is cleared by writing 1 to it. + * @var WWDT_T::CNT + * Offset: 0x0C WWDT Counter Value Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[5:0] |CNTDAT |WWDT Counter Value + * | | |CNTDAT will be updated continuously to monitor 6-bit WWDT down counter value. + */ + __O uint32_t RLDCNT; /*!< [0x0000] WWDT Reload Counter Register */ + __IO uint32_t CTL; /*!< [0x0004] WWDT Control Register */ + __IO uint32_t STATUS; /*!< [0x0008] WWDT Status Register */ + __I uint32_t CNT; /*!< [0x000c] WWDT Counter Value Register */ + +} WWDT_T; + + +/** + @addtogroup WWDT_CONST WWDT Bit Field Definition + Constant Definitions for WWDT Controller + @{ +*/ + +#define WWDT_RLDCNT_RLDCNT_Pos (0) /*!< WWDT_T::RLDCNT: RLDCNT Position */ +#define WWDT_RLDCNT_RLDCNT_Msk (0xfffffffful << WWDT_RLDCNT_RLDCNT_Pos) /*!< WWDT_T::RLDCNT: RLDCNT Mask */ + +#define WWDT_CTL_WWDTEN_Pos (0) /*!< WWDT_T::CTL: WWDTEN Position */ +#define WWDT_CTL_WWDTEN_Msk (0x1ul << WWDT_CTL_WWDTEN_Pos) /*!< WWDT_T::CTL: WWDTEN Mask */ + +#define WWDT_CTL_INTEN_Pos (1) /*!< WWDT_T::CTL: INTEN Position */ +#define WWDT_CTL_INTEN_Msk (0x1ul << WWDT_CTL_INTEN_Pos) /*!< WWDT_T::CTL: INTEN Mask */ + +#define WWDT_CTL_PSCSEL_Pos (8) /*!< WWDT_T::CTL: PSCSEL Position */ +#define WWDT_CTL_PSCSEL_Msk (0xful << WWDT_CTL_PSCSEL_Pos) /*!< WWDT_T::CTL: PSCSEL Mask */ + +#define WWDT_CTL_CMPDAT_Pos (16) /*!< WWDT_T::CTL: CMPDAT Position */ +#define WWDT_CTL_CMPDAT_Msk (0x3ful << WWDT_CTL_CMPDAT_Pos) /*!< WWDT_T::CTL: CMPDAT Mask */ + +#define WWDT_CTL_ICEDEBUG_Pos (31) /*!< WWDT_T::CTL: ICEDEBUG Position */ +#define WWDT_CTL_ICEDEBUG_Msk (0x1ul << WWDT_CTL_ICEDEBUG_Pos) /*!< WWDT_T::CTL: ICEDEBUG Mask */ + +#define WWDT_STATUS_WWDTIF_Pos (0) /*!< WWDT_T::STATUS: WWDTIF Position */ +#define WWDT_STATUS_WWDTIF_Msk (0x1ul << WWDT_STATUS_WWDTIF_Pos) /*!< WWDT_T::STATUS: WWDTIF Mask */ + +#define WWDT_STATUS_WWDTRF_Pos (1) /*!< WWDT_T::STATUS: WWDTRF Position */ +#define WWDT_STATUS_WWDTRF_Msk (0x1ul << WWDT_STATUS_WWDTRF_Pos) /*!< WWDT_T::STATUS: WWDTRF Mask */ + +#define WWDT_CNT_CNTDAT_Pos (0) /*!< WWDT_T::CNT: CNTDAT Position */ +#define WWDT_CNT_CNTDAT_Msk (0x3ful << WWDT_CNT_CNTDAT_Pos) /*!< WWDT_T::CNT: CNTDAT Mask */ + +/**@}*/ /* WWDT_CONST */ +/**@}*/ /* end of WWDT register group */ +/**@}*/ /* end of REGISTER group */ + +#endif /* __WWDT_REG_H__ */ diff --git a/Ubiquitous/XiZi/board/nuvoton-m2354/third_party_driver/include/connect_uart.h b/Ubiquitous/XiZi/board/nuvoton-m2354/third_party_driver/include/connect_uart.h new file mode 100644 index 0000000..86bb90e --- /dev/null +++ b/Ubiquitous/XiZi/board/nuvoton-m2354/third_party_driver/include/connect_uart.h @@ -0,0 +1,44 @@ +/* +* Copyright (c) 2020 AIIT XUOS Lab +* XiUOS is licensed under Mulan PSL v2. +* You can use this software according to the terms and conditions of the Mulan PSL v2. +* You may obtain a copy of Mulan PSL v2 at: +* http://license.coscl.org.cn/MulanPSL2 +* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, +* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, +* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. +* See the Mulan PSL v2 for more details. +*/ + +/** +* @file connect_uart.h +* @brief define nuvoton-m2354 uart function and struct +* @version 1.1 +* @author AIIT XUOS Lab +* @date 2022-02-24 +*/ + +#ifndef CONNECT_UART_H +#define CONNECT_UART_H + +#include +#include +#include +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +#define KERNEL_CONSOLE_BUS_NAME SERIAL_BUS_NAME_0 +#define KERNEL_CONSOLE_DRV_NAME SERIAL_DRV_NAME_0 +#define KERNEL_CONSOLE_DEVICE_NAME SERIAL_0_DEVICE_NAME_0 + +int M2354HwUartInit(void); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/Ubiquitous/XiZi/board/nuvoton-m2354/third_party_driver/uart/Kconfig b/Ubiquitous/XiZi/board/nuvoton-m2354/third_party_driver/uart/Kconfig new file mode 100644 index 0000000..c664c04 --- /dev/null +++ b/Ubiquitous/XiZi/board/nuvoton-m2354/third_party_driver/uart/Kconfig @@ -0,0 +1,14 @@ +menuconfig BSP_USING_UART0 + bool "Enable UART0" + default y + if BSP_USING_UART0 + config SERIAL_BUS_NAME_0 + string "serial bus 0 name" + default "uart0" + config SERIAL_DRV_NAME_0 + string "serial bus 0 driver name" + default "uart0_drv" + config SERIAL_0_DEVICE_NAME_0 + string "serial bus 0 device name" + default "uart0_dev0" + endif diff --git a/Ubiquitous/XiZi/board/nuvoton-m2354/third_party_driver/uart/Makefile b/Ubiquitous/XiZi/board/nuvoton-m2354/third_party_driver/uart/Makefile new file mode 100644 index 0000000..b515f58 --- /dev/null +++ b/Ubiquitous/XiZi/board/nuvoton-m2354/third_party_driver/uart/Makefile @@ -0,0 +1,3 @@ +SRC_FILES := connect_uart.c + +include $(KERNEL_ROOT)/compiler.mk diff --git a/Ubiquitous/XiZi/board/nuvoton-m2354/third_party_driver/uart/connect_uart.c b/Ubiquitous/XiZi/board/nuvoton-m2354/third_party_driver/uart/connect_uart.c new file mode 100644 index 0000000..a435870 --- /dev/null +++ b/Ubiquitous/XiZi/board/nuvoton-m2354/third_party_driver/uart/connect_uart.c @@ -0,0 +1,389 @@ +/* +* Copyright (c) 2020 AIIT XUOS Lab +* XiUOS is licensed under Mulan PSL v2. +* You can use this software according to the terms and conditions of the Mulan PSL v2. +* You may obtain a copy of Mulan PSL v2 at: +* http://license.coscl.org.cn/MulanPSL2 +* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, +* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, +* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. +* See the Mulan PSL v2 for more details. +*/ + +/** +* @file connect_uart.c +* @brief support nuvoton_m2354 board uart function and register to bus framework +* @version 1.1 +* @author AIIT XUOS Lab +* @date 2022-02-24 +*/ + +#include +#include + +struct M2354UartHwCfg +{ + UART_T *uart_handle; + uint32 uart_rst_index; + IRQn_Type irq_type; +}; + +#ifdef BSP_USING_UART0 +static struct SerialBus serial_bus_0; +static struct SerialDriver serial_driver_0; +static struct SerialHardwareDevice serial_device_0; +#endif + +static void SerialCfgParamCheck(struct SerialCfgParam *serial_cfg_default, struct SerialCfgParam *serial_cfg_new) +{ + struct SerialDataCfg *data_cfg_default = &serial_cfg_default->data_cfg; + struct SerialDataCfg *data_cfg_new = &serial_cfg_new->data_cfg; + + if ((data_cfg_default->serial_baud_rate != data_cfg_new->serial_baud_rate) && (data_cfg_new->serial_baud_rate)) { + data_cfg_default->serial_baud_rate = data_cfg_new->serial_baud_rate; + } + + if ((data_cfg_default->serial_bit_order != data_cfg_new->serial_bit_order) && (data_cfg_new->serial_bit_order)) { + data_cfg_default->serial_bit_order = data_cfg_new->serial_bit_order; + } + + if ((data_cfg_default->serial_buffer_size != data_cfg_new->serial_buffer_size) && (data_cfg_new->serial_buffer_size)) { + data_cfg_default->serial_buffer_size = data_cfg_new->serial_buffer_size; + } + + if ((data_cfg_default->serial_data_bits != data_cfg_new->serial_data_bits) && (data_cfg_new->serial_data_bits)) { + data_cfg_default->serial_data_bits = data_cfg_new->serial_data_bits; + } + + if ((data_cfg_default->serial_invert_mode != data_cfg_new->serial_invert_mode) && (data_cfg_new->serial_invert_mode)) { + data_cfg_default->serial_invert_mode = data_cfg_new->serial_invert_mode; + } + + if ((data_cfg_default->serial_parity_mode != data_cfg_new->serial_parity_mode) && (data_cfg_new->serial_parity_mode)) { + data_cfg_default->serial_parity_mode = data_cfg_new->serial_parity_mode; + } + + if ((data_cfg_default->serial_stop_bits != data_cfg_new->serial_stop_bits) && (data_cfg_new->serial_stop_bits)) { + data_cfg_default->serial_stop_bits = data_cfg_new->serial_stop_bits; + } +} + +static void UartHandler(struct SerialBus *serial_bus, struct SerialDriver *serial_drv) +{ + struct SerialHardwareDevice *serial_dev = (struct SerialHardwareDevice *)serial_bus->bus.owner_haldev; + struct SerialCfgParam *serial_cfg = (struct SerialCfgParam *)serial_drv->private_data; + struct M2354UartHwCfg *serial_hw_cfg = (struct M2354UartHwCfg *)serial_cfg->hw_cfg.private_data; + + /* Get interrupt event */ + uint32 u32IntSts = serial_hw_cfg->uart_handle->INTSTS; + uint32 u32FIFOSts = serial_hw_cfg->uart_handle->FIFOSTS; + + /* Handle RX event */ + if (u32IntSts & (UART_INTSTS_RDAINT_Msk | UART_INTSTS_RXTOINT_Msk)) { + SerialSetIsr(serial_dev, SERIAL_EVENT_RX_IND); + } + serial_hw_cfg->uart_handle->INTSTS = u32IntSts; + serial_hw_cfg->uart_handle->FIFOSTS = u32FIFOSts; +} + +#ifdef BSP_USING_UART0 +void UART0_IRQHandler(int irqn, void *arg) +{ + x_base lock = 0; + + lock = DISABLE_INTERRUPT(); + + UartHandler(&serial_bus_0, &serial_driver_0); + + ENABLE_INTERRUPT(lock); +} +//DECLARE_HW_IRQ(UART0_IRQ_NUM, UART0_IRQHandler, NONE); +#endif + +static uint32 SerialInit(struct SerialDriver *serial_drv, struct BusConfigureInfo *configure_info) +{ + NULL_PARAM_CHECK(serial_drv); + + uint32 uart_word_len = 0; + uint32 uart_stop_bit = 0; + uint32 uart_parity = 0; + + struct SerialCfgParam *serial_cfg = (struct SerialCfgParam *)serial_drv->private_data; + struct M2354UartHwCfg *serial_hw_cfg = (struct M2354UartHwCfg *)serial_cfg->hw_cfg.private_data; + + if (configure_info->private_data) { + struct SerialCfgParam *serial_cfg_new = (struct SerialCfgParam *)configure_info->private_data; + SerialCfgParamCheck(serial_cfg, serial_cfg_new); + } + + switch (serial_cfg->data_cfg.serial_data_bits) + { + case DATA_BITS_5: + uart_word_len = UART_WORD_LEN_5; + break; + case DATA_BITS_6: + uart_word_len = UART_WORD_LEN_6; + break; + case DATA_BITS_7: + uart_word_len = UART_WORD_LEN_7; + break; + case DATA_BITS_8: + uart_word_len = UART_WORD_LEN_8; + break; + default: + KPrintf("SerialInit Unsupported serial_data_bits %u\n", serial_cfg->data_cfg.serial_data_bits); + return ERROR; + } + + switch (serial_cfg->data_cfg.serial_stop_bits) + { + case STOP_BITS_1: + uart_stop_bit = UART_STOP_BIT_1; + break; + case STOP_BITS_2: + uart_stop_bit = UART_STOP_BIT_2; + break; + default: + KPrintf("SerialInit Unsupported serial_stop_bits %u\n", serial_cfg->data_cfg.serial_stop_bits); + return ERROR; + } + + switch (serial_cfg->data_cfg.serial_parity_mode) + { + case PARITY_NONE: + uart_parity = UART_PARITY_NONE; + break; + case PARITY_ODD: + uart_parity = UART_PARITY_ODD; + break; + case PARITY_EVEN: + uart_parity = UART_PARITY_EVEN; + break; + default: + KPrintf("SerialInit Unsupported serial_parity_mode %u\n", serial_cfg->data_cfg.serial_parity_mode); + return ERROR; + } + + /* Reset this module */ + SYS_ResetModule(serial_hw_cfg->uart_rst_index); + + /* Open Uart and set UART Baudrate */ + UART_Open(serial_hw_cfg->uart_handle, serial_cfg->data_cfg.serial_baud_rate); + + /* Set line configuration. */ + UART_SetLineConfig(serial_hw_cfg->uart_handle, 0, uart_word_len, uart_parity, uart_stop_bit); + + /* Enable NVIC interrupt. */ + NVIC_EnableIRQ(serial_hw_cfg->irq_type); + + return EOK; +} + +static uint32 SerialConfigure(struct SerialDriver *serial_drv, int serial_operation_cmd) +{ + NULL_PARAM_CHECK(serial_drv); + + struct SerialHardwareDevice *serial_dev = (struct SerialHardwareDevice *)serial_drv->driver.owner_bus->owner_haldev; + struct SerialCfgParam *serial_cfg = (struct SerialCfgParam *)serial_drv->private_data; + struct M2354UartHwCfg *serial_hw_cfg = (struct M2354UartHwCfg *)serial_cfg->hw_cfg.private_data; + struct SerialDevParam *serial_dev_param = (struct SerialDevParam *)serial_dev->haldev.private_data; + + if (OPER_CLR_INT == serial_operation_cmd) { + if (SIGN_OPER_INT_RX & serial_dev_param->serial_work_mode) { + UART_DISABLE_INT(serial_hw_cfg->uart_handle, UART_INTEN_RDAIEN_Msk | UART_INTEN_RXTOIEN_Msk | UART_INTEN_TOCNTEN_Msk); + } + } else if (OPER_SET_INT == serial_operation_cmd) { + UART_ENABLE_INT(serial_hw_cfg->uart_handle, UART_INTEN_RDAIEN_Msk | UART_INTEN_RXTOIEN_Msk | UART_INTEN_TOCNTEN_Msk); + } + + return EOK; +} + +static uint32 SerialDrvConfigure(void *drv, struct BusConfigureInfo *configure_info) +{ + NULL_PARAM_CHECK(drv); + NULL_PARAM_CHECK(configure_info); + + x_err_t ret = EOK; + int serial_operation_cmd; + struct SerialDriver *serial_drv = (struct SerialDriver *)drv; + + switch (configure_info->configure_cmd) + { + case OPE_INT: + ret = SerialInit(serial_drv, configure_info); + break; + case OPE_CFG: + serial_operation_cmd = *(int *)configure_info->private_data; + ret = SerialConfigure(serial_drv, serial_operation_cmd); + break; + default: + break; + } + + return ret; +} + +static int SerialPutChar(struct SerialHardwareDevice *serial_dev, char c) +{ + struct SerialCfgParam *serial_cfg = (struct SerialCfgParam *)serial_dev->private_data; + struct M2354UartHwCfg *serial_hw_cfg = (struct M2354UartHwCfg *)serial_cfg->hw_cfg.private_data; + + /* Waiting if TX-FIFO is full. */ + while (UART_IS_TX_FULL(serial_hw_cfg->uart_handle)); + + /* Put char into TX-FIFO */ + UART_WRITE(serial_hw_cfg->uart_handle, c); + + return EOK; +} + +static int SerialGetChar(struct SerialHardwareDevice *serial_dev) +{ + struct SerialCfgParam *serial_cfg = (struct SerialCfgParam *)serial_dev->private_data; + struct M2354UartHwCfg *serial_hw_cfg = (struct M2354UartHwCfg *)serial_cfg->hw_cfg.private_data; + + /* Return failure if RX-FIFO is empty. */ + if (UART_GET_RX_EMPTY(serial_hw_cfg->uart_handle)) { + return -1; + } + + /* Get char from RX-FIFO */ + return UART_READ(serial_hw_cfg->uart_handle); +} + +static const struct SerialDataCfg data_cfg_init = +{ + .serial_baud_rate = BAUD_RATE_115200, + .serial_data_bits = DATA_BITS_8, + .serial_stop_bits = STOP_BITS_1, + .serial_parity_mode = PARITY_NONE, + .serial_bit_order = BIT_ORDER_LSB, + .serial_invert_mode = NRZ_NORMAL, + .serial_buffer_size = SERIAL_RB_BUFSZ, +}; + +/*manage the serial device operations*/ +static const struct SerialDrvDone drv_done = +{ + .init = SerialInit, + .configure = SerialConfigure, +}; + +/*manage the serial device hal operations*/ +static struct SerialHwDevDone hwdev_done = +{ + .put_char = SerialPutChar, + .get_char = SerialGetChar, +}; + +static int BoardSerialBusInit(struct SerialBus *serial_bus, struct SerialDriver *serial_driver, const char *bus_name, const char *drv_name) +{ + x_err_t ret = EOK; + + /*Init the serial bus */ + ret = SerialBusInit(serial_bus, bus_name); + if (EOK != ret) { + KPrintf("M2354HwUartInit SerialBusInit error %d\n", ret); + return ERROR; + } + + /*Init the serial driver*/ + ret = SerialDriverInit(serial_driver, drv_name); + if (EOK != ret) { + KPrintf("M2354HwUartInit SerialDriverInit error %d\n", ret); + return ERROR; + } + + /*Attach the serial driver to the serial bus*/ + ret = SerialDriverAttachToBus(drv_name, bus_name); + if (EOK != ret) { + KPrintf("M2354HwUartInit SerialDriverAttachToBus error %d\n", ret); + return ERROR; + } + + return ret; +} + +/*Attach the serial device to the serial bus*/ +static int BoardSerialDevBend(struct SerialHardwareDevice *serial_device, void *serial_param, const char *bus_name, const char *dev_name) +{ + x_err_t ret = EOK; + + ret = SerialDeviceRegister(serial_device, serial_param, dev_name); + if (EOK != ret) { + KPrintf("M2354HwUartInit SerialDeviceInit device %s error %d\n", dev_name, ret); + return ERROR; + } + + ret = SerialDeviceAttachToBus(dev_name, bus_name); + if (EOK != ret) { + KPrintf("M2354HwUartInit SerialDeviceAttachToBus device %s error %d\n", dev_name, ret); + return ERROR; + } + + return ret; +} + +int M2354HwUartInit(void) +{ + x_err_t ret = EOK; + +#ifdef BSP_USING_UART0 + memset(&serial_bus_0, 0, sizeof(struct SerialBus)); + memset(&serial_driver_0, 0, sizeof(struct SerialDriver)); + memset(&serial_device_0, 0, sizeof(struct SerialHardwareDevice)); + + static struct SerialCfgParam serial_cfg_0; + memset(&serial_cfg_0, 0, sizeof(struct SerialCfgParam)); + + static struct M2354UartHwCfg serial_hw_cfg_0; + memset(&serial_hw_cfg_0, 0, sizeof(struct M2354UartHwCfg)); + + static struct SerialDevParam serial_dev_param_0; + memset(&serial_dev_param_0, 0, sizeof(struct SerialDevParam)); + + serial_driver_0.drv_done = &drv_done; + serial_driver_0.configure = SerialDrvConfigure; + serial_device_0.hwdev_done = &hwdev_done; + + serial_cfg_0.data_cfg = data_cfg_init; + + serial_cfg_0.hw_cfg.private_data = (void *)&serial_hw_cfg_0; + serial_hw_cfg_0.uart_handle = UART0; + serial_hw_cfg_0.uart_rst_index = UART0_RST; + serial_hw_cfg_0.irq_type = UART0_IRQn; + serial_driver_0.private_data = (void *)&serial_cfg_0; + + serial_dev_param_0.serial_work_mode = SIGN_OPER_INT_RX; + serial_device_0.haldev.private_data = (void *)&serial_dev_param_0; + + ret = BoardSerialBusInit(&serial_bus_0, &serial_driver_0, SERIAL_BUS_NAME_0, SERIAL_DRV_NAME_0); + if (EOK != ret) { + KPrintf("InitHwUart uarths error ret %u\n", ret); + return ERROR; + } + + ret = BoardSerialDevBend(&serial_device_0, (void *)&serial_cfg_0, SERIAL_BUS_NAME_0, SERIAL_0_DEVICE_NAME_0); + if (EOK != ret) { + KPrintf("InitHwUart uarths error ret %u\n", ret); + return ERROR; + } +#endif + + return ret; +} + + + + + + + + + + + + + + diff --git a/Ubiquitous/XiZi/board/ok1052-c/Kconfig b/Ubiquitous/XiZi/board/ok1052-c/Kconfig new file mode 100644 index 0000000..62afaf4 --- /dev/null +++ b/Ubiquitous/XiZi/board/ok1052-c/Kconfig @@ -0,0 +1,58 @@ +mainmenu "XiZi Project Configuration" + +config BSP_DIR + string + option env="BSP_ROOT" + default "." + +config KERNEL_DIR + string + option env="KERNEL_ROOT" + default "../.." + +config BOARD_CORTEX_M7_EVB + bool + select ARCH_ARM + default y + + +source "$KERNEL_DIR/arch/Kconfig" + +menu "ok1052-c feature" + source "$BSP_DIR/third_party_driver/Kconfig" + + menu "config default board resources" + menu "config board app name" + config BOARD_APP_NAME + string "config board app name" + default "/XiUOS_ok1052C_app.bin" + endmenu + + menu "config board service table" + config SERVICE_TABLE_ADDRESS + hex "board service table address" + default 0x2007F0000 + endmenu + + endmenu + + config __STACKSIZE__ + int "stack size for interrupt" + default 4096 + + menu "config board peripheral" + config MOUNT_SDCARD + bool "mount cd card" + default n + endmenu + +endmenu + + +menu "Hardware feature" +source "$KERNEL_DIR/resources/Kconfig" +endmenu + +source "$KERNEL_DIR/Kconfig" + + diff --git a/Ubiquitous/XiZi/board/ok1052-c/Makefile b/Ubiquitous/XiZi/board/ok1052-c/Makefile new file mode 100644 index 0000000..c50f207 --- /dev/null +++ b/Ubiquitous/XiZi/board/ok1052-c/Makefile @@ -0,0 +1,5 @@ +SRC_DIR := third_party_driver xip + +SRC_FILES := board.c + +include $(KERNEL_ROOT)/compiler.mk \ No newline at end of file diff --git a/Ubiquitous/XiZi/board/ok1052-c/README.md b/Ubiquitous/XiZi/board/ok1052-c/README.md new file mode 100644 index 0000000..4e489f0 --- /dev/null +++ b/Ubiquitous/XiZi/board/ok1052-c/README.md @@ -0,0 +1,175 @@ +# 从零开始构建矽璓工业物联操作系统：使用ARM架构的ok1052-c + +# ok1052-c + +[XiUOS](http://xuos.io/) (X Industrial Ubiquitous Operating System) 矽璓XiUOS是一款面向智慧车间的工业物联网操作系统，主要由一个极简的微型实时操作系统内核和其上的工业物联框架构成，通过高效管理工业物联网设备、支撑工业物联应用，在生产车间内实现智能化的“感知环境、联网传输、知悉识别、控制调整”，促进以工业设备和工业控制系统为核心的人、机、物深度互联，帮助提升生产线的数字化和智能化水平。 + +## 1. 简介 + +| 硬件 | 描述 | +| -- | -- | +|芯片型号| MIMXRT1052DVL6A | +|架构| cortex-m7 | +|主频| 600MHz | +|片内SRAM| 512KB shared with TCM | +|外设支持| UART GPIO I2C RTC SDIO SEMC SPI USB ADC| + +XiUOS板级当前支持使用UART、GPIO、I2C、RTC、SDIO、SEMC、SPI、USB、ADC。 + +## 2. 开发环境搭建 + +### 推荐使用： + +**操作系统：** ubuntu18.04 [https://ubuntu.com/download/desktop](https://ubuntu.com/download/desktop) + +更新`ubuntu 18.04`源的方法:（根据自身情况而定，可以不更改） + +第一步:打开sources.list文件 + +```c +sudo vim /etc/apt/sources.list +``` + +第二步:将以下内容复制到sources.list文件 + +```c +deb http://mirrors.aliyun.com/ubuntu/ bionic main restricted universe multiverse +deb http://mirrors.aliyun.com/ubuntu/ bionic-security main restricted universe multiverse +deb http://mirrors.aliyun.com/ubuntu/ bionic-updates main restricted universe multiverse +deb http://mirrors.aliyun.com/ubuntu/ bionic-proposed main restricted universe multiverse +deb http://mirrors.aliyun.com/ubuntu/ bionic-backports main restricted universe multiverse +deb-src http://mirrors.aliyun.com/ubuntu/ bionic main restricted universe multiverse +deb-src http://mirrors.aliyun.com/ubuntu/ bionic-security main restricted universe multiverse +deb-src http://mirrors.aliyun.com/ubuntu/ bionic-updates main restricted universe multiverse +deb-src http://mirrors.aliyun.com/ubuntu/ bionic-proposed main restricted universe multiverse +deb-src http://mirrors.aliyun.com/ubuntu/ bionic-backports main restricted universe multiverse +``` + +第三步:更新源和系统软件 + +```c +sudo apt-get update +sudo apt-get upgrade +``` + +**开发工具推荐使用 VSCode ，VScode下载地址为：** VSCode [https://code.visualstudio.com/](https://code.visualstudio.com/)，推荐下载地址为 [http://vscode.cdn.azure.cn/stable/3c4e3df9e89829dce27b7b5c24508306b151f30d/code_1.55.2-1618307277_amd64.deb](http://vscode.cdn.azure.cn/stable/3c4e3df9e89829dce27b7b5c24508306b151f30d/code_1.55.2-1618307277_amd64.deb) + +### 依赖包安装： + +``` +$ sudo apt install build-essential pkg-config git +$ sudo apt install gcc make libncurses5-dev openssl libssl-dev bison flex libelf-dev autoconf libtool gperf libc6-dev +``` + +**XiUOS操作系统源码下载：** XiUOS [https://www.gitlink.org.cn/xuos/xiuos](https://www.gitlink.org.cn/xuos/xiuos) + +新建一个空文件夹并进入文件夹中，并下载源码，具体命令如下： + +```c +mkdir test && cd test +git clone https://gitlink.org.cn/xuos/xiuos.git +``` + +1、打开XiUOS源码文件包可以看到以下目录： +| 名称 | 说明 | +| -- | -- | +| APP_Framework | 应用代码 | +| Ubiquitous | 板级支持包,支持NuttX、RT-Thread和XiZi内核 | + +2、打开XiZi内核源码文件包可以看到以下目录： +| 名称 | 说明 | +| -- | -- | +| arch | 架构代码 | +| board | 板级支持包 | +| fs | 文件系统 | +| kernel | 内核源码 | +| lib | 第三方库源码 | +| resources | 驱动文件 | +| tool | 系统工具 | + +使用VScode打开代码，具体操作步骤为：在源码文件夹下打开系统终端，输入`code .`即可打开VScode开发环境，如下图所示： + +
+ +
+ +### 裁减配置工具的下载 + +裁减配置工具： + +**工具地址：** kconfig-frontends [https://www.gitlink.org.cn/xuos/kconfig-frontends](https://www.gitlink.org.cn/xuos/kconfig-frontends)，下载与安装的具体命令如下： + +```c +mkdir kfrontends && cd kfrontends +git clone https://gitlink.org.cn/xuos/kconfig-frontends.git +``` + +下载源码后按以下步骤执行软件安装： + +```c +cd kconfig-frontends +./xs_build.sh +``` + +### 编译工具链： + +ARM： arm-none-eabi(`gcc version 6.3.1`)，默认安装到Ubuntu的/usr/bin/arm-none-eabi-，使用如下命令行下载和安装。 + +```shell +$ sudo apt install gcc-arm-none-eabi +``` + +## 编译说明 + +### 编辑环境：`Ubuntu18.04` + +### 编译工具链：`arm-none-eabi-gcc` +使用`VScode`打开工程的方法有多种，本文介绍一种快捷键，在项目目录下将`code .`输入linux系统命令终端即可打开目标项目 + + +编译步骤： + +1.在VScode命令终端中执行以下命令，生成配置文件 + +```c +cd ./Ubiquitous/XiZi +make BOARD=ok1052-c distclean +make BOARD=ok1052-c menuconfig +``` + +2.在menuconfig界面配置需要关闭和开启的功能，按回车键进入下级菜单，按Y键选中需要开启的功能，按N键选中需要关闭的功能，配置结束后保存并退出（本例旨在演示简单的输出例程，所以没有需要配置的选项，双击快捷键ESC退出配置） + +![menuconfig](./img/menuconfig.png) + +退出时选择`yes`保存上面所配置的内容，如下图所示： + +![menuconfig1](./img/menuconfig1.png) + +3.继续执行以下命令，进行编译 + +``` +make BOARD=ok1052-c +``` + +4.如果编译正确无误，会产生XiZi_ok1052-c.elf、XiZi_ok1052-c.bin文件。 + +## 3. 烧写及运行 + +### 3.1 烧写 +1、烧写工具：NXP MCU Boot Utility，可参考[https://github.com/JayHeng/NXP-MCUBootUtility](https://github.com/JayHeng/NXP-MCUBootUtility) + +2、ok1052-c开发板支持micro usb口烧写程序，打开NXP MCU Boot Utility后，选择好芯片类型为i.MXRT105x，开发板上电，使用usb线将开发板和PC连接，拨码开关设置为1 on 2 on 3 off 4 off，按下复位键K1后，若连接成功，可见Vendor ID和Product ID均有数字显示，点击reconnect，等待NXP MCU Boot Utility中红色显示变成蓝色显示，则表示已正确识别并连接到了开发板。如下图所示： +![NXPBootUtility_1](./img/NXPBootUtility_1.png) + +3、同时需要匹配ok1052-c开发板所使用的Flash型号，点击Boot Device Configuration，在Use Typical Device中选择Winbond_W25QxxxJV，然后点击ok。如下图所示： +![flashconfig](./img/flashconfig.png) + +4、选择编译生成的XiZi_ok1052-c.elf或bin文件路径，按照图示步骤，将文件烧写至Flash中（link.lds中已构造Flash Bootable image，如有修改Flash相关配置需求，可修改/xip目录内相关文件，无需NXPBootUtility再次构造），若烧写无误，则下列绿色进度条会执行到底。如下图所示： +![NXPBootUtility_2](./img/NXPBootUtility_2.png) + +### 3.2 运行结果 + +1、开发板支持rs232串口连接，使用rs232串口线或rs232转usb线将开发板和PC连接，使用串口终端工具可识别并连接开发板 + +2、按照3.1烧写步骤执行后，将拨码开关设置为1 off 2 off 3 off 4 off，按下复位键K1后，若程序正常，则串口终端上会显示启动信息打印输出。如下图所示： +![terminal](./img/terminal.png) diff --git a/Ubiquitous/XiZi/board/ok1052-c/config.mk b/Ubiquitous/XiZi/board/ok1052-c/config.mk new file mode 100644 index 0000000..f57b787 --- /dev/null +++ b/Ubiquitous/XiZi/board/ok1052-c/config.mk @@ -0,0 +1,22 @@ +export CROSS_COMPILE ?=/usr/bin/arm-none-eabi- + +export CFLAGS := -mcpu=cortex-m7 -mthumb -ffunction-sections -fdata-sections -Dgcc -O0 -gdwarf-2 -g -fgnu89-inline -Wa,-mimplicit-it=thumb +export AFLAGS := -c -mcpu=cortex-m7 -mthumb -ffunction-sections -fdata-sections -x assembler-with-cpp -Wa,-mimplicit-it=thumb -gdwarf-2 + +### if use USB function, use special lds file because USB uses ITCM + +ifeq ($(CONFIG_BSP_USING_USB),y) +export LFLAGS := -mcpu=cortex-m7 -mthumb -ffunction-sections -fdata-sections -Wl,--gc-sections,-Map=XiZi_ok1052-c.map,-cref,-u,Reset_Handler -T $(BSP_ROOT)/link-usb.lds +else +export LFLAGS := -mcpu=cortex-m7 -mthumb -ffunction-sections -fdata-sections -Wl,--gc-sections,-Map=XiZi_ok1052-c.map,-cref,-u,Reset_Handler -T $(BSP_ROOT)/link.lds +endif + +export CXXFLAGS := -mcpu=cortex-m7 -mthumb -ffunction-sections -fdata-sections -Dgcc -O0 -gdwarf-2 -g + +export APPLFLAGS := -mcpu=cortex-m7 -mthumb -ffunction-sections -fdata-sections -Wl,--gc-sections,-Map=XiZi_app.map,-cref,-u, -T $(BSP_ROOT)/link_userspace.lds + + +export DEFINES := -DHAVE_CCONFIG_H -DCPU_MIMXRT1052CVL5B -DSKIP_SYSCLK_INIT -DEVK_MCIMXRM -DFSL_SDK_ENABLE_DRIVER_CACHE_CONTROL=1 -DXIP_EXTERNAL_FLASH=1 -D__STARTUP_INITIALIZE_NONCACHEDATA -D__STARTUP_CLEAR_BSS + +export ARCH = arm +export MCU = cortex-m7 diff --git a/Ubiquitous/XiZi/board/ok1052-c/img/NXPBootUtility_1.png b/Ubiquitous/XiZi/board/ok1052-c/img/NXPBootUtility_1.png new file mode 100644 index 0000000..734f038 Binary files /dev/null and b/Ubiquitous/XiZi/board/ok1052-c/img/NXPBootUtility_1.png differ diff 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diff --git a/Ubiquitous/XiZi/board/ok1052-c/img/terminal.png b/Ubiquitous/XiZi/board/ok1052-c/img/terminal.png new file mode 100644 index 0000000..8dad4f4 Binary files /dev/null and b/Ubiquitous/XiZi/board/ok1052-c/img/terminal.png differ diff --git a/Ubiquitous/XiZi/board/ok1052-c/img/vscode.jpg b/Ubiquitous/XiZi/board/ok1052-c/img/vscode.jpg new file mode 100644 index 0000000..b9bacff Binary files /dev/null and b/Ubiquitous/XiZi/board/ok1052-c/img/vscode.jpg differ diff --git a/Ubiquitous/XiZi/board/ok1052-c/link-usb.lds b/Ubiquitous/XiZi/board/ok1052-c/link-usb.lds new file mode 100755 index 0000000..0af5e16 --- /dev/null +++ b/Ubiquitous/XiZi/board/ok1052-c/link-usb.lds @@ -0,0 +1,264 @@ +/* +** ################################################################### +** Processors: MIMXRT1052CVJ5B +** MIMXRT1052CVL5B +** MIMXRT1052DVJ6B +** MIMXRT1052DVL6B +** +** Compiler: GNU C Compiler +** Reference manual: IMXRT1050RM Rev.1, 03/2018 +** Version: rev. 1.0, 2018-09-21 +** Build: b180921 +** +** Abstract: +** Linker file for the GNU C Compiler +** +** Copyright 2016 Freescale Semiconductor, Inc. +** Copyright 2016-2018 NXP +** All rights reserved. +** +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** ################################################################### +*/ + + +/** +* @file link.lds +* @brief ok1052-c board Linker script +* @version 1.0 +* @author AIIT XUOS Lab +* @date 2021-05-28 +*/ + +/************************************************* +File name: link.lds +Description: ok1052-c board Linker script +Others: take MIMXRT1052xxxxx_flexspi_nor.ld for references +History: +1. Date: 2021-05-28 +Author: AIIT XUOS Lab +Modification: +1. add shell cmd table and g_service_table +*************************************************/ + +/* Entry Point */ +ENTRY(Reset_Handler) + +HEAP_SIZE = DEFINED(__heap_size__) ? __heap_size__ : 0x0400; +STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x1000; + +/* Specify the memory areas */ +MEMORY +{ + m_boot_data (RX) : ORIGIN = 0x60000000, LENGTH = 0x00001000 + m_image_vertor_table (RX) : ORIGIN = 0x60001000, LENGTH = 0x00001000 + + m_interrupts (RX) : ORIGIN = 0x60002000, LENGTH = 0x00000400 + m_text (RX) : ORIGIN = 0x60002400, LENGTH = 0x03FFDC00 + m_data (RW) : ORIGIN = 0x20000000, LENGTH = 0x00020000 + m_data2 (RW) : ORIGIN = 0x20200000, LENGTH = 0x00060000 +} + +/* Define output sections */ +SECTIONS +{ + .boot_data : + { + KEEP(*(.boot_hdr.conf)) + } > m_boot_data + + .image_vertor_table : + { + KEEP(*(.boot_hdr.ivt)) + KEEP(*(.boot_hdr.boot_data)) + KEEP(*(.boot_hdr.dcd_data)) + } > m_image_vertor_table + + /* The startup code goes first into internal RAM */ + .interrupts : + { + __VECTOR_TABLE = .; + . = ALIGN(4); + KEEP(*(.isr_vector)) /* Startup code */ + . = ALIGN(4); + } > m_interrupts + + __VECTOR_RAM = __VECTOR_TABLE; + __RAM_VECTOR_TABLE_SIZE_BYTES = 0x0; + + /* The program code and other data goes into internal RAM */ + .text : + { + . = ALIGN(4); + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + KEEP (*(.init)) + KEEP (*(.fini)) + . = ALIGN(4); + + + /* section information for shell */ + . = ALIGN(4); + _shell_command_start = .; + KEEP (*(shellCommand)) + _shell_command_end = .; + . = ALIGN(4); + + __isrtbl_idx_start = .; + KEEP(*(.isrtbl.idx)) + __isrtbl_start = .; + KEEP(*(.isrtbl)) + __isrtbl_end = .; + . = ALIGN(4); + + PROVIDE(g_service_table_start = ABSOLUTE(.)); + KEEP(*(.g_service_table)) + PROVIDE(g_service_table_end = ABSOLUTE(.)); + } > m_text + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > m_text + + .ARM : + { + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + } > m_text + + .ctors : + { + __CTOR_LIST__ = .; + /* gcc uses crtbegin.o to find the start of + the constructors, so we make sure it is + first. Because this is a wildcard, it + doesn't matter if the user does not + actually link against crtbegin.o; the + linker won't look for a file to match a + wildcard. The wildcard also means that it + doesn't matter which directory crtbegin.o + is in. */ + KEEP (*crtbegin.o(.ctors)) + KEEP (*crtbegin?.o(.ctors)) + /* We don't want to include the .ctor section from + from the crtend.o file until after the sorted ctors. + The .ctor section from the crtend file contains the + end of ctors marker and it must be last */ + KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*(.ctors)) + __CTOR_END__ = .; + } > m_text + + .dtors : + { + __DTOR_LIST__ = .; + KEEP (*crtbegin.o(.dtors)) + KEEP (*crtbegin?.o(.dtors)) + KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*(.dtors)) + __DTOR_END__ = .; + } > m_text + + .preinit_array : + { + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + } > m_text + + .init_array : + { + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + } > m_text + + .fini_array : + { + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array*)) + PROVIDE_HIDDEN (__fini_array_end = .); + } > m_text + + __etext = .; /* define a global symbol at end of code */ + __DATA_ROM = .; /* Symbol is used by startup for data initialization */ + + .data : AT(__DATA_ROM) + { + . = ALIGN(4); + __DATA_RAM = .; + __data_start__ = .; /* create a global symbol at data start */ + *(m_usb_dma_init_data) + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + KEEP(*(.jcr*)) + . = ALIGN(4); + __data_end__ = .; /* define a global symbol at data end */ + } > m_data + + __NDATA_ROM = __DATA_ROM + (__data_end__ - __data_start__); + .ncache.init : AT(__NDATA_ROM) + { + __noncachedata_start__ = .; /* create a global symbol at ncache data start */ + *(NonCacheable.init) + . = ALIGN(4); + __noncachedata_init_end__ = .; /* create a global symbol at initialized ncache data end */ + } > m_data + . = __noncachedata_init_end__; + .ncache : + { + *(NonCacheable) + . = ALIGN(4); + __noncachedata_end__ = .; /* define a global symbol at ncache data end */ + } > m_data + + __DATA_END = __NDATA_ROM + (__noncachedata_init_end__ - __noncachedata_start__); + text_end = ORIGIN(m_text) + LENGTH(m_text); + ASSERT(__DATA_END <= text_end, "region m_text overflowed with text and data") + + /* Uninitialized data section */ + .bss : + { + /* This is used by the startup in order to initialize the .bss section */ + . = ALIGN(4); + __START_BSS = .; + __bss_start__ = .; + *(m_usb_dma_noninit_data) + *(.bss) + *(.bss*) + *(COMMON) + . = ALIGN(4); + __bss_end__ = .; + __END_BSS = .; + } > m_data + + .stack : + { + . = ALIGN(8); + stack_start = .; + . += STACK_SIZE; + stack_end = .; + __StackTop = .; + heap_start = .; + } > m_data + + PROVIDE(heap_end = ORIGIN(m_data) + LENGTH(m_data)); + + .ARM.attributes 0 : { *(.ARM.attributes) } +} + diff --git a/Ubiquitous/XiZi/board/ok1052-c/link.lds b/Ubiquitous/XiZi/board/ok1052-c/link.lds new file mode 100644 index 0000000..d9fce95 --- /dev/null +++ b/Ubiquitous/XiZi/board/ok1052-c/link.lds @@ -0,0 +1,264 @@ +/* +** ################################################################### +** Processors: MIMXRT1052CVJ5B +** MIMXRT1052CVL5B +** MIMXRT1052DVJ6B +** MIMXRT1052DVL6B +** +** Compiler: GNU C Compiler +** Reference manual: IMXRT1050RM Rev.1, 03/2018 +** Version: rev. 1.0, 2018-09-21 +** Build: b180921 +** +** Abstract: +** Linker file for the GNU C Compiler +** +** Copyright 2016 Freescale Semiconductor, Inc. +** Copyright 2016-2018 NXP +** All rights reserved. +** +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** ################################################################### +*/ + + +/** +* @file link.lds +* @brief ok1052-c board Linker script +* @version 1.0 +* @author AIIT XUOS Lab +* @date 2021-05-28 +*/ + +/************************************************* +File name: link.lds +Description: ok1052-c board Linker script +Others: take MIMXRT1052xxxxx_flexspi_nor.ld for references +History: +1. Date: 2021-05-28 +Author: AIIT XUOS Lab +Modification: +1. add shell cmd table and g_service_table +*************************************************/ + +/* Entry Point */ +ENTRY(Reset_Handler) + +HEAP_SIZE = DEFINED(__heap_size__) ? __heap_size__ : 0x0400; +STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x1000; + +/* Specify the memory areas */ +MEMORY +{ + m_boot_data (RX) : ORIGIN = 0x60000000, LENGTH = 0x00001000 + m_image_vertor_table (RX) : ORIGIN = 0x60001000, LENGTH = 0x00001000 + + m_interrupts (RX) : ORIGIN = 0x60002000, LENGTH = 0x00000400 + m_text (RX) : ORIGIN = 0x60002400, LENGTH = 0x03FFDC00 + m_data (RW) : ORIGIN = 0x20000000, LENGTH = 0x00020000 + m_data2 (RW) : ORIGIN = 0x20200000, LENGTH = 0x00060000 +} + +/* Define output sections */ +SECTIONS +{ + .boot_data : + { + KEEP(*(.boot_hdr.conf)) + } > m_boot_data + + .image_vertor_table : + { + KEEP(*(.boot_hdr.ivt)) + KEEP(*(.boot_hdr.boot_data)) + KEEP(*(.boot_hdr.dcd_data)) + } > m_image_vertor_table + + /* The startup code goes first into internal RAM */ + .interrupts : + { + __VECTOR_TABLE = .; + . = ALIGN(4); + KEEP(*(.isr_vector)) /* Startup code */ + . = ALIGN(4); + } > m_interrupts + + __VECTOR_RAM = __VECTOR_TABLE; + __RAM_VECTOR_TABLE_SIZE_BYTES = 0x0; + + /* The program code and other data goes into internal RAM */ + .text : + { + . = ALIGN(4); + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + KEEP (*(.init)) + KEEP (*(.fini)) + . = ALIGN(4); + + + /* section information for shell */ + . = ALIGN(4); + _shell_command_start = .; + KEEP (*(shellCommand)) + _shell_command_end = .; + . = ALIGN(4); + + __isrtbl_idx_start = .; + KEEP(*(.isrtbl.idx)) + __isrtbl_start = .; + KEEP(*(.isrtbl)) + __isrtbl_end = .; + . = ALIGN(4); + + PROVIDE(g_service_table_start = ABSOLUTE(.)); + KEEP(*(.g_service_table)) + PROVIDE(g_service_table_end = ABSOLUTE(.)); + } > m_text + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > m_text + + .ARM : + { + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + } > m_text + + .ctors : + { + __CTOR_LIST__ = .; + /* gcc uses crtbegin.o to find the start of + the constructors, so we make sure it is + first. Because this is a wildcard, it + doesn't matter if the user does not + actually link against crtbegin.o; the + linker won't look for a file to match a + wildcard. The wildcard also means that it + doesn't matter which directory crtbegin.o + is in. */ + KEEP (*crtbegin.o(.ctors)) + KEEP (*crtbegin?.o(.ctors)) + /* We don't want to include the .ctor section from + from the crtend.o file until after the sorted ctors. + The .ctor section from the crtend file contains the + end of ctors marker and it must be last */ + KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*(.ctors)) + __CTOR_END__ = .; + } > m_text + + .dtors : + { + __DTOR_LIST__ = .; + KEEP (*crtbegin.o(.dtors)) + KEEP (*crtbegin?.o(.dtors)) + KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*(.dtors)) + __DTOR_END__ = .; + } > m_text + + .preinit_array : + { + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + } > m_text + + .init_array : + { + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + } > m_text + + .fini_array : + { + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array*)) + PROVIDE_HIDDEN (__fini_array_end = .); + } > m_text + + __etext = .; /* define a global symbol at end of code */ + __DATA_ROM = .; /* Symbol is used by startup for data initialization */ + + .data : AT(__DATA_ROM) + { + . = ALIGN(4); + __DATA_RAM = .; + __data_start__ = .; /* create a global symbol at data start */ + *(m_usb_dma_init_data) + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + KEEP(*(.jcr*)) + . = ALIGN(4); + __data_end__ = .; /* define a global symbol at data end */ + } > m_data + + __NDATA_ROM = __DATA_ROM + (__data_end__ - __data_start__); + .ncache.init : AT(__NDATA_ROM) + { + __noncachedata_start__ = .; /* create a global symbol at ncache data start */ + *(NonCacheable.init) + . = ALIGN(4); + __noncachedata_init_end__ = .; /* create a global symbol at initialized ncache data end */ + } > m_data + . = __noncachedata_init_end__; + .ncache : + { + *(NonCacheable) + . = ALIGN(4); + __noncachedata_end__ = .; /* define a global symbol at ncache data end */ + } > m_data + + __DATA_END = __NDATA_ROM + (__noncachedata_init_end__ - __noncachedata_start__); + text_end = ORIGIN(m_text) + LENGTH(m_text); + ASSERT(__DATA_END <= text_end, "region m_text overflowed with text and data") + + /* Uninitialized data section */ + .bss : + { + /* This is used by the startup in order to initialize the .bss section */ + . = ALIGN(4); + __START_BSS = .; + __bss_start__ = .; + *(m_usb_dma_noninit_data) + *(.bss) + *(.bss*) + *(COMMON) + . = ALIGN(4); + __bss_end__ = .; + __END_BSS = .; + } > m_data + + .stack : + { + . = ALIGN(8); + stack_start = .; + . += STACK_SIZE; + stack_end = .; + __StackTop = .; + heap_start = .; + } > m_data2 + + PROVIDE(heap_end = ORIGIN(m_data2) + LENGTH(m_data2)); + + .ARM.attributes 0 : { *(.ARM.attributes) } +} + diff --git a/Ubiquitous/XiZi/board/ok1052-c/third_party_driver/Kconfig b/Ubiquitous/XiZi/board/ok1052-c/third_party_driver/Kconfig new file mode 100644 index 0000000..0ec9c3a --- /dev/null +++ b/Ubiquitous/XiZi/board/ok1052-c/third_party_driver/Kconfig @@ -0,0 +1,79 @@ +menuconfig BSP_USING_LPUART + bool "Using UART device" + default y + select RESOURCES_SERIAL + if BSP_USING_LPUART + source "$BSP_DIR/third_party_driver/uart/Kconfig" + endif + +menuconfig BSP_USING_LWIP + bool "Using LwIP device" + default n + select RESOURCES_LWIP + +menuconfig BSP_USING_GPIO + bool "Using GPIO device " + default y + select RESOURCES_PIN + + if BSP_USING_GPIO + source "$BSP_DIR/third_party_driver/gpio/Kconfig" + endif + +menuconfig BSP_USING_I2C + bool "Using I2C device" + default n + select RESOURCES_I2C + + if BSP_USING_I2C + source "$BSP_DIR/third_party_driver/i2c/Kconfig" + endif + +menuconfig BSP_USING_ADC + bool "Using ADC device" + default n + select RESOURCES_ADC + + if BSP_USING_ADC + source "$BSP_DIR/third_party_driver/adc/Kconfig" + endif + +menuconfig BSP_USING_SPI + bool "Using SPI device" + default n + select RESOURCES_SPI + + if BSP_USING_SPI + source "$BSP_DIR/third_party_driver/spi/Kconfig" + endif + +menuconfig BSP_USING_RTC + bool "Using RTC device" + default n + select RESOURCES_RTC + if BSP_USING_RTC + source "$BSP_DIR/third_party_driver/rtc/Kconfig" + endif + +menuconfig BSP_USING_SEMC + bool "Using SEMC device" + default n + if BSP_USING_SEMC + source "$BSP_DIR/third_party_driver/semc/Kconfig" + endif + +menuconfig BSP_USING_SDIO + bool "Using SD card device" + default n + select RESOURCES_SDIO + if BSP_USING_SDIO + source "$BSP_DIR/third_party_driver/sdio/Kconfig" + endif + +menuconfig BSP_USING_USB + bool "Using USB device" + default n + select RESOURCES_USB + if BSP_USING_USB + source "$BSP_DIR/third_party_driver/usb/Kconfig" + endif diff --git a/Ubiquitous/XiZi/board/ok1052-c/third_party_driver/Makefile b/Ubiquitous/XiZi/board/ok1052-c/third_party_driver/Makefile new file mode 100644 index 0000000..81e730f --- /dev/null +++ b/Ubiquitous/XiZi/board/ok1052-c/third_party_driver/Makefile @@ -0,0 +1,39 @@ +SRC_DIR := common gpio + +ifeq ($(CONFIG_BSP_USING_LPUART),y) + SRC_DIR += uart +endif + +ifeq ($(CONFIG_BSP_USING_LWIP),y) + SRC_DIR += ethernet +endif + +ifeq ($(CONFIG_BSP_USING_I2C),y) + SRC_DIR += i2c +endif + +ifeq ($(CONFIG_BSP_USING_ADC),y) + SRC_DIR += adc +endif + +ifeq ($(CONFIG_BSP_USING_SPI),y) + SRC_DIR += spi +endif + +ifeq ($(CONFIG_BSP_USING_SEMC),y) + SRC_DIR += semc +endif + +ifeq ($(CONFIG_BSP_USING_RTC),y) + SRC_DIR += rtc +endif + +ifeq ($(CONFIG_BSP_USING_SDIO),y) + SRC_DIR += sdio +endif + +ifeq ($(CONFIG_BSP_USING_USB),y) + SRC_DIR += usb +endif + +include $(KERNEL_ROOT)/compiler.mk diff --git a/Ubiquitous/XiZi/board/ok1052-c/third_party_driver/adc/Kconfig b/Ubiquitous/XiZi/board/ok1052-c/third_party_driver/adc/Kconfig new file mode 100755 index 0000000..dc26d70 --- /dev/null +++ b/Ubiquitous/XiZi/board/ok1052-c/third_party_driver/adc/Kconfig @@ -0,0 +1,29 @@ +config BSP_USING_ADC1 +bool "Enable ADC1" +default y +if BSP_USING_ADC1 + config ADC_BUS_NAME_1 + string "adc bus 1 name" + default "adc1" + config ADC_DRV_NAME_1 + string "adc bus 1 driver name" + default "adc1_drv" + config ADC_1_DEVICE_NAME_0 + string "adc bus 1 device name" + default "adc1_dev" +endif + +config BSP_USING_ADC2 +bool "Enable ADC2" +default y +if BSP_USING_ADC2 + config ADC_BUS_NAME_2 + string "adc bus 2 name" + default "adc2" + config ADC_DRV_NAME_2 + string "adc bus 2 driver name" + default "adc2_drv" + config ADC_2_DEVICE_NAME_0 + string "adc bus 2 device name" + default "adc2_dev" +endif diff --git a/Ubiquitous/XiZi/board/ok1052-c/third_party_driver/adc/Makefile b/Ubiquitous/XiZi/board/ok1052-c/third_party_driver/adc/Makefile new file mode 100755 index 0000000..154646c --- /dev/null +++ b/Ubiquitous/XiZi/board/ok1052-c/third_party_driver/adc/Makefile @@ -0,0 +1,3 @@ +SRC_FILES := fsl_adc.c connect_adc.c + +include $(KERNEL_ROOT)/compiler.mk diff --git a/Ubiquitous/XiZi/board/ok1052-c/third_party_driver/adc/connect_adc.c b/Ubiquitous/XiZi/board/ok1052-c/third_party_driver/adc/connect_adc.c new file mode 100755 index 0000000..21b5d49 --- /dev/null +++ b/Ubiquitous/XiZi/board/ok1052-c/third_party_driver/adc/connect_adc.c @@ -0,0 +1,295 @@ +/* +* Copyright (c) 2022 AIIT XUOS Lab +* XiUOS is licensed under Mulan PSL v2. +* You can use this software according to the terms and conditions of the Mulan PSL v2. +* You may obtain a copy of Mulan PSL v2 at: +* http://license.coscl.org.cn/MulanPSL2 +* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, +* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, +* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. +* See the Mulan PSL v2 for more details. +*/ + +/** + * @file connect_adc.c + * @brief Demo for ADC function + * @version 1.0 + * @author AIIT XUOS Lab + * @date 2022.1.18 + */ + +#include "board.h" +#include "fsl_adc.h" +#include "fsl_common.h" +#include "dev_adc.h" +#include "bus_adc.h" +#include "connect_adc.h" + +#define ADC1_BASE_ADDR ADC1 +#define ADC1_IRQ ADC1_IRQn +#define ADC1_USER_CHANNEL 3U +#define ADC1_CHANNEL_GROUP 0U + +#define ADC2_BASE_ADDR ADC2 +#define ADC2_IRQ ADC2_IRQn +#define ADC2_USER_CHANNEL 4U +#define ADC2_CHANNEL_GROUP 0U + +#define adc_print KPrintf + +volatile bool adc1_flag; +volatile uint32_t adc1_val; +volatile uint32_t adc1_irq_cnt; +volatile bool adc2_flag; +volatile uint32_t adc2_val; +volatile uint32_t adc2_irq_cnt; + +/******************************************************************************* + * Code + ******************************************************************************/ + +void ADC1_IRQHandler(int vector, void *param) +{ + adc1_flag = true; + /* Read conversion result to clear the conversion completed flag. */ + adc1_val = ADC_GetChannelConversionValue(ADC1_BASE_ADDR, ADC1_CHANNEL_GROUP); + adc1_irq_cnt++; +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} + +DECLARE_HW_IRQ(ADC1_IRQn, ADC1_IRQHandler, NONE); + +void ADC2_IRQHandler(int vector, void *param) +{ + adc2_flag = true; + /* Read conversion result to clear the conversion completed flag. */ + adc2_val = ADC_GetChannelConversionValue(ADC2_BASE_ADDR, ADC2_CHANNEL_GROUP); + adc2_irq_cnt++; +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} + +DECLARE_HW_IRQ(ADC2_IRQn, ADC2_IRQHandler, NONE); + +uint32 Imxrt1052AdcOpen(void *dev) +{ + struct AdcHardwareDevice *adc_dev = (struct AdcHardwareDevice *)dev; + adc_config_t adc_cfg; + +#ifdef BSP_USING_ADC1 + if (0 == strncmp(adc_dev->haldev.dev_name, ADC_1_DEVICE_NAME_0, NAME_NUM_MAX)) { + EnableIRQ(ADC1_IRQn); + ADC_GetDefaultConfig(&adc_cfg); + ADC_Init(ADC1, &adc_cfg); +#if !(defined(FSL_FEATURE_ADC_SUPPORT_HARDWARE_TRIGGER_REMOVE) && FSL_FEATURE_ADC_SUPPORT_HARDWARE_TRIGGER_REMOVE) + ADC_EnableHardwareTrigger(ADC1, false); +#endif + /* Do auto hardware calibration. */ + if (kStatus_Success == ADC_DoAutoCalibration(ADC1)) + { + adc_print("ADC_DoAntoCalibration() Done.\r\n"); + } + else + { + adc_print("ADC_DoAutoCalibration() Failed.\r\n"); + } + } +#endif + +#ifdef BSP_USING_ADC2 + if (0 == strncmp(adc_dev->haldev.dev_name, ADC_2_DEVICE_NAME_0, NAME_NUM_MAX)) { + EnableIRQ(ADC2_IRQn); + ADC_GetDefaultConfig(&adc_cfg); + ADC_Init(ADC2, &adc_cfg); +#if !(defined(FSL_FEATURE_ADC_SUPPORT_HARDWARE_TRIGGER_REMOVE) && FSL_FEATURE_ADC_SUPPORT_HARDWARE_TRIGGER_REMOVE) + ADC_EnableHardwareTrigger(ADC2, false); +#endif + /* Do auto hardware calibration. */ + if (kStatus_Success == ADC_DoAutoCalibration(ADC2)) + { + adc_print("ADC_DoAntoCalibration() Done.\r\n"); + } + else + { + adc_print("ADC_DoAutoCalibration() Failed.\r\n"); + } + } +#endif + + return EOK; +} + +uint32 Imxrt1052AdcClose(void *dev) +{ + return EOK; +} + +uint32 Imxrt1052AdcRead(void *dev, struct BusBlockReadParam *read_param) +{ + struct AdcHardwareDevice *adc_dev = (struct AdcHardwareDevice *)dev; + adc_channel_config_t ch_cfg; + +#ifdef BSP_USING_ADC1 + if (0 == strncmp(adc_dev->haldev.dev_name, ADC_1_DEVICE_NAME_0, NAME_NUM_MAX)) { + /* Configure the user channel and interrupt. */ + ch_cfg.channelNumber = ADC1_USER_CHANNEL; + ch_cfg.enableInterruptOnConversionCompleted = true; + adc1_irq_cnt = 0U; /* Clear the interrupt counter. */ + adc1_flag = false; + ADC_SetChannelConfig(ADC1, ADC1_CHANNEL_GROUP, &ch_cfg); + while (adc1_flag == false); + + adc_print("ADC Value: %d\r\n", adc1_val); + adc_print("ADC Interrupt Counter: %d\r\n", adc1_irq_cnt); + } +#endif + +#ifdef BSP_USING_ADC2 + if (0 == strncmp(adc_dev->haldev.dev_name, ADC_2_DEVICE_NAME_0, NAME_NUM_MAX)) { + /* Configure the user channel and interrupt. */ + ch_cfg.channelNumber = ADC2_USER_CHANNEL; + ch_cfg.enableInterruptOnConversionCompleted = true; + adc2_irq_cnt = 0U; /* Clear the interrupt counter. */ + adc2_flag = false; + ADC_SetChannelConfig(ADC2, ADC2_CHANNEL_GROUP, &ch_cfg); + while (adc2_flag == false); + + adc_print("ADC Value: %d\r\n", adc2_val); + adc_print("ADC Interrupt Counter: %d\r\n", adc2_irq_cnt); + } +#endif + + return adc1_val; +} + +static uint32 Imxrt1052AdcDrvConfigure(void *drv, struct BusConfigureInfo *configure_info) +{ + NULL_PARAM_CHECK(drv); + NULL_PARAM_CHECK(configure_info); + + x_err_t ret = EOK; + uint8 adc_channel; + + struct AdcDriver *adc_drv = (struct AdcDriver *)drv; + struct AdcHardwareDevice *adc_dev = (struct AdcHardwareDevice *)adc_drv->driver.owner_bus->owner_haldev; + struct Imxrt1052HwAdc *adc_cfg = (struct Imxrt1052HwAdc *)adc_dev->haldev.private_data; + + switch (configure_info->configure_cmd) + { + case OPE_CFG: + adc_cfg->adc_channel = *(uint8 *)configure_info->private_data; + if (adc_cfg->adc_channel > 18) { + KPrintf("Imxrt1052AdcDrvConfigure set adc channel(0-18) %u error!", adc_cfg->adc_channel); + adc_cfg->adc_channel = 0; + ret = ERROR; + } + break; + default: + break; + } + + return ret; +} + +static const struct AdcDevDone dev_done = +{ + Imxrt1052AdcOpen, + Imxrt1052AdcClose, + NONE, + Imxrt1052AdcRead, +}; + +int Imxrt1052HwAdcInit(void) +{ + x_err_t ret = EOK; + +#ifdef BSP_USING_ADC1 + static struct AdcBus adc1_bus; + static struct AdcDriver adc1_drv; + static struct AdcHardwareDevice adc1_dev; + static struct Imxrt1052HwAdc adc1_cfg; + + adc1_drv.configure = Imxrt1052AdcDrvConfigure; + + ret = AdcBusInit(&adc1_bus, ADC_BUS_NAME_1); + if (ret != EOK) { + KPrintf("ADC1 bus init error %d\n", ret); + return ERROR; + } + + ret = AdcDriverInit(&adc1_drv, ADC_DRV_NAME_1); + if (ret != EOK) { + KPrintf("ADC1 driver init error %d\n", ret); + return ERROR; + } + ret = AdcDriverAttachToBus(ADC_DRV_NAME_1, ADC_BUS_NAME_1); + if (ret != EOK) { + KPrintf("ADC1 driver attach error %d\n", ret); + return ERROR; + } + + adc1_dev.adc_dev_done = &dev_done; + + ret = AdcDeviceRegister(&adc1_dev, (void *)&adc1_cfg, ADC_1_DEVICE_NAME_0); + if (ret != EOK) { + KPrintf("ADC1 device register error %d\n", ret); + return ERROR; + } + + ret = AdcDeviceAttachToBus(ADC_1_DEVICE_NAME_0, ADC_BUS_NAME_1); + if (ret != EOK) { + KPrintf("ADC1 device register error %d\n", ret); + return ERROR; + } +#endif + +#ifdef BSP_USING_ADC2 + static struct AdcBus adc2_bus; + static struct AdcDriver adc2_drv; + static struct AdcHardwareDevice adc2_dev; + static struct Imxrt1052HwAdc adc2_cfg; + + adc2_drv.configure = Imxrt1052AdcDrvConfigure; + + ret = AdcBusInit(&adc2_bus, ADC_BUS_NAME_2); + if (ret != EOK) { + KPrintf("ADC2 bus init error %d\n", ret); + return ERROR; + } + + ret = AdcDriverInit(&adc2_drv, ADC_DRV_NAME_2); + if (ret != EOK) { + KPrintf("ADC2 driver init error %d\n", ret); + return ERROR; + } + ret = AdcDriverAttachToBus(ADC_DRV_NAME_2, ADC_BUS_NAME_2); + if (ret != EOK) { + KPrintf("ADC2 driver attach error %d\n", ret); + return ERROR; + } + + adc2_dev.adc_dev_done = &dev_done; + + ret = AdcDeviceRegister(&adc2_dev, (void *)&adc2_cfg, ADC_2_DEVICE_NAME_0); + if (ret != EOK) { + KPrintf("ADC2 device register error %d\n", ret); + return ERROR; + } + + ret = AdcDeviceAttachToBus(ADC_2_DEVICE_NAME_0, ADC_BUS_NAME_2); + if (ret != EOK) { + KPrintf("ADC2 device register error %d\n", ret); + return ERROR; + } +#endif + + return ret; +} + diff --git a/Ubiquitous/XiZi/board/ok1052-c/third_party_driver/i2c/Kconfig b/Ubiquitous/XiZi/board/ok1052-c/third_party_driver/i2c/Kconfig new file mode 100755 index 0000000..ddc5990 --- /dev/null +++ b/Ubiquitous/XiZi/board/ok1052-c/third_party_driver/i2c/Kconfig @@ -0,0 +1,12 @@ +if BSP_USING_I2C + config I2C_BUS_NAME_1 + string "i2c bus 1 name" + default "i2c1" + config I2C_DRV_NAME_1 + string "i2c bus 1 driver name" + default "i2c1_drv" + config I2C_1_DEVICE_NAME_0 + string "i2c bus 1 device 0 name" + default "i2c1_dev0" +endif + diff --git a/Ubiquitous/XiZi/board/ok1052-c/third_party_driver/i2c/Makefile b/Ubiquitous/XiZi/board/ok1052-c/third_party_driver/i2c/Makefile new file mode 100755 index 0000000..0ece1cd --- /dev/null +++ b/Ubiquitous/XiZi/board/ok1052-c/third_party_driver/i2c/Makefile @@ -0,0 +1,3 @@ +SRC_FILES := connect_i2c.c connect_i2c_eeprom.c hardware_i2c.c fsl_lpi2c.c + +include $(KERNEL_ROOT)/compiler.mk diff --git a/Ubiquitous/XiZi/board/ok1052-c/third_party_driver/i2c/connect_i2c.c b/Ubiquitous/XiZi/board/ok1052-c/third_party_driver/i2c/connect_i2c.c new file mode 100755 index 0000000..85d6672 --- /dev/null +++ b/Ubiquitous/XiZi/board/ok1052-c/third_party_driver/i2c/connect_i2c.c @@ -0,0 +1,179 @@ +/* +* Copyright (c) 2022 AIIT XUOS Lab +* XiUOS is licensed under Mulan PSL v2. +* You can use this software according to the terms and conditions of the Mulan PSL v2. +* You may obtain a copy of Mulan PSL v2 at: +* http://license.coscl.org.cn/MulanPSL2 +* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, +* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, +* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. +* See the Mulan PSL v2 for more details. +*/ + +/** +* @file connect_i2c.c +* @brief support ok1052-c board i2c function and register to bus framework +* @version 1.0 +* @author AIIT XUOS Lab +* @date 2022-03-01 +*/ + +#include +#include "bus_serial.h" +#include "connect_i2c.h" +#include "fsl_lpi2c.h" + +static uint32 I2cWriteData(struct I2cHardwareDevice *i2c_dev, struct I2cDataStandard *msg) +{ + status_t ret; + Stm32I2cType *param = (Stm32I2cType *)i2c_dev->haldev.private_data; + ret = I2cHardwareWrite(param->base, param->slave_addr, param->sub_addr, msg->buf, msg->len); + if(kStatus_Success == ret) + return 1; + return 0; +} + +static uint32 I2cReadData(struct I2cHardwareDevice *i2c_dev, struct I2cDataStandard *msg) +{ + status_t ret; + Stm32I2cType *param = (Stm32I2cType *)i2c_dev->haldev.private_data; + ret = I2cHardwareRead(param->base, i2c_dev->i2c_dev_addr, param->sub_addr, msg->buf, msg->len); + if(kStatus_Success == ret) + return 1; + return 0; +} + +static uint32 I2cInit(struct I2cDriver *i2c_drv, struct BusConfigureInfo *configure_info) +{ + NULL_PARAM_CHECK(i2c_drv); + + struct I2cHardwareDevice *i2c_dev = (struct I2cHardwareDevice *)i2c_drv->driver.owner_bus->owner_haldev; + + if (configure_info->private_data) { + i2c_dev->i2c_dev_addr = *((uint16 *)configure_info->private_data); + return EOK; + } + + i2c_print("I2cInit need set i2c dev addr\n"); + return ERROR; +} + +static uint32 I2cDrvConfigure(void *drv, struct BusConfigureInfo *configure_info) +{ + NULL_PARAM_CHECK(drv); + NULL_PARAM_CHECK(configure_info); + + x_err_t ret = EOK; + struct I2cDriver *i2c_drv = (struct I2cDriver *)drv; + + switch (configure_info->configure_cmd) + { + case OPE_INT: + ret = I2cInit(i2c_drv, configure_info); + break; + default: + break; + } + + return ret; +} + +/*manage the i2c device operations*/ +static const struct I2cDevDone i2c_dev_done = +{ + .dev_open = NONE, + .dev_close = NONE, + .dev_write = I2cWriteData, + .dev_read = I2cReadData, +}; + +/*Init i2c bus*/ +static int BoardI2cBusInit(struct I2cBus *i2c_bus, struct I2cDriver *i2c_driver) +{ + x_err_t ret = EOK; + + /*Init the i2c bus */ + i2c_bus->private_data = (void *)NULL; + ret = I2cBusInit(i2c_bus, I2C_BUS_NAME_1); + if (EOK != ret) { + i2c_print("BoardI2cBusInit I2cBusInit error %d\n", ret); + return ERROR; + } + + /*Init the i2c driver*/ + i2c_driver->private_data = (void *)NULL; + ret = I2cDriverInit(i2c_driver, I2C_DRV_NAME_1); + if (EOK != ret) { + i2c_print("BoardI2cBusInit I2cDriverInit error %d\n", ret); + return ERROR; + } + + /*Attach the i2c driver to the i2c bus*/ + ret = I2cDriverAttachToBus(I2C_DRV_NAME_1, I2C_BUS_NAME_1); + if (EOK != ret) { + i2c_print("BoardI2cBusInit I2cDriverAttachToBus error %d\n", ret); + return ERROR; + } + + return ret; +} + +/*Attach the i2c device to the i2c bus*/ +static int BoardI2cDevBend(void) +{ + x_err_t ret = EOK; + static struct I2cHardwareDevice i2c_device0; + memset(&i2c_device0, 0, sizeof(struct I2cHardwareDevice)); + + i2c_device0.i2c_dev_done = &i2c_dev_done; + + ret = I2cDeviceRegister(&i2c_device0, NONE, I2C_1_DEVICE_NAME_0); + if (EOK != ret) { + i2c_print("BoardI2cDevBend I2cDeviceInit device %s error %d\n", I2C_1_DEVICE_NAME_0, ret); + return ERROR; + } + + ret = I2cDeviceAttachToBus(I2C_1_DEVICE_NAME_0, I2C_BUS_NAME_1); + if (EOK != ret) { + i2c_print("BoardI2cDevBend I2cDeviceAttachToBus device %s error %d\n", I2C_1_DEVICE_NAME_0, ret); + return ERROR; + } + + return ret; +} + +/*BOARD I2C INIT*/ +int Imxrt1052HwI2cInit(void) +{ + static int init_flag = 0; + x_err_t ret = EOK; + + if(init_flag) + { + return ret; + } + init_flag = 1; + + static struct I2cBus i2c_bus; + memset(&i2c_bus, 0, sizeof(struct I2cBus)); + static struct I2cDriver i2c_driver; + memset(&i2c_driver, 0, sizeof(struct I2cDriver)); + +#ifdef BSP_USING_I2C + i2c_driver.configure = I2cDrvConfigure; + + ret = BoardI2cBusInit(&i2c_bus, &i2c_driver); + if (EOK != ret) { + i2c_print("board_i2c_Init error ret %u\n", ret); + return ERROR; + } + + ret = BoardI2cDevBend(); + if (EOK != ret) { + i2c_print("board_i2c_Init error ret %u\n", ret); + return ERROR; + } +#endif + + return ret; +} diff --git a/Ubiquitous/XiZi/board/ok1052-c/third_party_driver/i2c/connect_i2c_eeprom.c b/Ubiquitous/XiZi/board/ok1052-c/third_party_driver/i2c/connect_i2c_eeprom.c new file mode 100755 index 0000000..792a192 --- /dev/null +++ b/Ubiquitous/XiZi/board/ok1052-c/third_party_driver/i2c/connect_i2c_eeprom.c @@ -0,0 +1,76 @@ +/* +* Copyright (c) 2022 AIIT XUOS Lab +* XiUOS is licensed under Mulan PSL v2. +* You can use this software according to the terms and conditions of the Mulan PSL v2. +* You may obtain a copy of Mulan PSL v2 at: +* http://license.coscl.org.cn/MulanPSL2 +* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, +* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, +* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. +* See the Mulan PSL v2 for more details. +*/ + +/** +* @file connect_i2c_eeprom.h +* @brief ok1052-c board eeprom relative codes +* @version 1.0 +* @author AIIT XUOS Lab +* @date 2022-03-01 +*/ + +#include "board.h" +#include "connect_i2c.h" +#include "fsl_lpi2c.h" +#include "pin_mux.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +#define I2C_EEPROM_BASE LPI2C1 +#define I2C_EEPROM_ADDR (0xA0 >> 1) + +/******************************************************************************* + * Code + ******************************************************************************/ + +void I2cEEpromTestWrite(void) +{ + uint8_t dat[8] = {0}; + + if(I2cHardwareRead(I2C_EEPROM_BASE, I2C_EEPROM_ADDR, 0, dat, 8) == kStatus_Success) + { + i2c_print("Read from EEPROM %d %d %d %d %d %d %d %d\r\n", + dat[0], dat[1], dat[2], dat[3], dat[4], dat[5], dat[6], dat[7]); + } + + for(uint8_t i = 0; i < 8; i++) + { + dat[i] ++; + } + + if(I2cHardwareWrite(I2C_EEPROM_BASE, I2C_EEPROM_ADDR, 0, dat, 8) == kStatus_Success) + { + i2c_print("Write to EEPROM %d %d %d %d %d %d %d %d\r\n", + dat[0], dat[1], dat[2], dat[3], dat[4], dat[5], dat[6], dat[7]); + } + + memset(dat, 0, 8); + if(I2cHardwareRead(I2C_EEPROM_BASE, I2C_EEPROM_ADDR, 0, dat, 8) == kStatus_Success) + { + i2c_print("Read from EEPROM %d %d %d %d %d %d %d %d\r\n", + dat[0], dat[1], dat[2], dat[3], dat[4], dat[5], dat[6], dat[7]); + } +} + +int I2cEEpromTest(void) +{ + BOARD_InitI2C1Pins(); + I2cHardwareInit(); + I2cEEpromTestWrite(); + return 0; +} + +SHELL_EXPORT_CMD(SHELL_CMD_PERMISSION(0)| SHELL_CMD_TYPE(SHELL_TYPE_CMD_MAIN)| SHELL_CMD_PARAM_NUM(0), + eeprom, I2cEEpromTest, test i2c eeprom); + diff --git a/Ubiquitous/XiZi/board/ok1052-c/third_party_driver/rtc/Kconfig b/Ubiquitous/XiZi/board/ok1052-c/third_party_driver/rtc/Kconfig new file mode 100755 index 0000000..e853dd4 --- /dev/null +++ b/Ubiquitous/XiZi/board/ok1052-c/third_party_driver/rtc/Kconfig @@ -0,0 +1,11 @@ +if BSP_USING_RTC + config RTC_BUS_NAME + string "rtc bus name" + default "rtc" + config RTC_DRV_NAME + string "rtc bus driver name" + default "rtc_drv" + config RTC_DEVICE_NAME + string "rtc bus device name" + default "rtc_dev" +endif diff --git a/Ubiquitous/XiZi/board/ok1052-c/third_party_driver/rtc/Makefile b/Ubiquitous/XiZi/board/ok1052-c/third_party_driver/rtc/Makefile new file mode 100755 index 0000000..15d4676 --- /dev/null +++ b/Ubiquitous/XiZi/board/ok1052-c/third_party_driver/rtc/Makefile @@ -0,0 +1,3 @@ +SRC_FILES := hardware_rtc.c connect_rtc.c + +include $(KERNEL_ROOT)/compiler.mk diff --git a/Ubiquitous/XiZi/board/ok1052-c/third_party_driver/rtc/connect_rtc.c b/Ubiquitous/XiZi/board/ok1052-c/third_party_driver/rtc/connect_rtc.c new file mode 100755 index 0000000..3112e23 --- /dev/null +++ b/Ubiquitous/XiZi/board/ok1052-c/third_party_driver/rtc/connect_rtc.c @@ -0,0 +1,453 @@ +/* + * The Clear BSD License + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted (subject to the limitations in the disclaimer below) provided + * that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/** +* @file connect_rtc.c +* @brief ok1052-c board rtc function and structure +* @version 1.0 +* @author AIIT XUOS Lab +* @date 2022-03-01 +*/ + +/************************************************* +File name: connect_rtc.c +Description: support ok1052-c board rtc configure and spi bus register function + +History: +1. Date: 2022-03-01 +Author: AIIT XUOS Lab +Modification: +1. change command for XUOS +2. add module codes for XUOS +*************************************************/ + +#include "board.h" +#include "bus_rtc.h" +#include "pin_mux.h" +#include "dev_rtc.h" +#include "connect_rtc.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +#define rtc_print KPrintf + +#define MAX_TIME_STR_SIZE 50 + +///////////RX8010/////////// + +#define RX8010_SEC 0x10 +#define RX8010_MIN 0x11 +#define RX8010_HOUR 0x12 +#define RX8010_WDAY 0x13 +#define RX8010_MDAY 0x14 +#define RX8010_MONTH 0x15 +#define RX8010_YEAR 0x16 +#define RX8010_YEAR 0x16 +#define RX8010_RESV17 0x17 +#define RX8010_ALMIN 0x18 +#define RX8010_ALHOUR 0x19 +#define RX8010_ALWDAY 0x1A +#define RX8010_TCOUNT0 0x1B +#define RX8010_TCOUNT1 0x1C +#define RX8010_EXT 0x1D +#define RX8010_FLAG 0x1E +#define RX8010_CTRL 0x1F + +/* 0x20 to 0x2F are user registers */ +#define RX8010_RESV30 0x30 +#define RX8010_RESV31 0x31 +#define RX8010_IRQ 0x32 + +#define RX8010_EXT_WADA 0x04 //BIT(3) + +#define RX8010_FLAG_VLF 0x02 //BIT(1) +#define RX8010_FLAG_AF 0x04 //BIT(3) +#define RX8010_FLAG_TF 0x08 //BIT(4) +#define RX8010_FLAG_UF 0x10 //BIT(5) + +#define RX8010_CTRL_AIE 0x04 //BIT(3) +#define RX8010_CTRL_UIE 0x10 //BIT(5) +#define RX8010_CTRL_STOP 0x20 //BIT(6) +#define RX8010_CTRL_TEST 0x40 //BIT(7) + +#define RX8010_ALARM_AE 0x40 //BIT(7) + +#define RX8010_TEST_TIME 10000 + +#define BCD_DATA_LEN 20 + +// change BIN format to BCD format +#define TO_BCD(_n) (((_n / 10) << 4) | (_n % 10)) + +/******************************************************************************* + * Prototypes + ******************************************************************************/ +/******************************************************************************* + * Variables + ******************************************************************************/ +/******************************************************************************* + * Code + ******************************************************************************/ + +// change BCD format date to BIN format +uint8_t bcd2bin(uint8_t data) +{ + int i = 0; + uint8_t ret = 0; + uint8_t mask[4] = {0x01, 0x02, 0x04, 0x08}; + + //LOW + for(i = 0; i < 4; i++) + { + if(mask[i] & data) + { + ret += mask[i]; + } + } + + //HIGH + for(i = 0; i < 4; i++) + { + if(mask[i] & (data >> 4)) + { + ret += (mask[i] * 10); + } + } + + return ret; +} + +// 8010 initialization +int RtcInit(void) +{ + uint8_t flag = 0; + uint8_t data = 0; + uint8_t ctrl[2]; + int need_clear = 0, err = 0; + err = RtcI2cRead(I2C_RTC_BASE, RX8010_FLAG, &flag, 1); + flag &= ~(RX8010_FLAG_VLF); + err = RtcI2cWrite(I2C_RTC_BASE, RX8010_FLAG, &flag, 1); + /* Initialize reserved registers as specified in datasheet */ + data = 0xD8; + err = RtcI2cWrite(I2C_RTC_BASE, RX8010_RESV17, &data, 1); + data = 0x00; + err = RtcI2cWrite(I2C_RTC_BASE, RX8010_RESV30, &data, 1); + data = 0x08; + err = RtcI2cWrite(I2C_RTC_BASE, RX8010_RESV31, &data, 1); + data = 0x00; + err = RtcI2cWrite(I2C_RTC_BASE, RX8010_IRQ, &data, 1); + err = RtcI2cRead(I2C_RTC_BASE, RX8010_FLAG, ctrl, 2); + + if(ctrl[0] & RX8010_FLAG_VLF) + { + rtc_print("\r\n Frequency stop was detected\r\n"); + } + + if(ctrl[0] & RX8010_FLAG_AF) + { + rtc_print("\r\n Alarm was detected\r\n"); + need_clear = 1; + } + + if(ctrl[0] & RX8010_FLAG_TF) + { + need_clear = 1; + } + + if(ctrl[0] & RX8010_FLAG_UF) + { + need_clear = 1; + } + + if(need_clear) + { + ctrl[0] &= ~(RX8010_FLAG_AF | RX8010_FLAG_TF | RX8010_FLAG_UF); + err = RtcI2cWrite(I2C_RTC_BASE, RX8010_FLAG, ctrl,1); + + if(!err) + { + return err; + } + } + + return err; +} + +// check format and get BCD format date like 2018-06-21 16:29:30 +int RtcGetBcdDate(uint8_t* date, uint8_t* bcd_date) +{ + int i; + int temp_date[6]; + + if(sscanf(date, "20%2d-%2d-%2d %2d:%2d:%2d", + &temp_date[5], + &temp_date[4], + &temp_date[3], + &temp_date[2], + &temp_date[1], + &temp_date[0]) == EOF) + { + rtc_print("i2c %s failed\n", __func__); + return -1; + } + + for(i = 0; i < 6; i++) + { + bcd_date[i] = TO_BCD(temp_date[i]); + } + + return 0; +} + +// setup time +int RtcSetTime(uint8_t* asc_date) +{ + uint8_t bcd_date[6]; + int ret, err; + + if(RtcGetBcdDate(asc_date, bcd_date)) + { + rtc_print("\r\n Date format error! \r\n"); + return -1; + } + + err = RtcI2cWrite(I2C_RTC_BASE, RX8010_SEC, bcd_date, 3); + err |= RtcI2cWrite(I2C_RTC_BASE, RX8010_MDAY, &bcd_date[3], 3); + return err; +} + +// get rx8010 time +int RtcGetTime(struct tm *ct) +{ + uint8_t rtc_data[7]; + uint8_t time_str[7]; + uint8_t flag_reg; + int err; + err = RtcI2cRead(I2C_RTC_BASE, RX8010_FLAG, &flag_reg, 1); + + if(flag_reg & RX8010_FLAG_VLF) + { + rtc_print("\r\n Frequency stop was detected\r\n"); + return 1; + } + + err = RtcI2cRead(I2C_RTC_BASE, RX8010_SEC, rtc_data, 7); + time_str[0] = bcd2bin(rtc_data[RX8010_SEC - RX8010_SEC] & 0x7f); + time_str[1] = bcd2bin(rtc_data[RX8010_MIN - RX8010_SEC] & 0x7f); + time_str[2] = bcd2bin(rtc_data[RX8010_HOUR - RX8010_SEC] & 0x3f); + time_str[4] = bcd2bin(rtc_data[RX8010_MDAY - RX8010_SEC] & 0x3f); + time_str[5] = bcd2bin(rtc_data[RX8010_MONTH - RX8010_SEC] & 0x1f); + time_str[6] = bcd2bin(rtc_data[RX8010_YEAR - RX8010_SEC]); + time_str[3] = rtc_data[RX8010_WDAY - RX8010_SEC] & 0x7f; + + rtc_print("RX8010 Time: 20%d%d-%d%d-%d%d %d%d:%d%d:%d%d\r\n", + time_str[6]/10, time_str[6]%10, time_str[5]/10, time_str[5]%10, time_str[4]/10, time_str[4]%10, + time_str[2]/10, time_str[2]%10, time_str[1]/10, time_str[1]%10, time_str[0]/10, time_str[0]%10); + + ct->tm_year = time_str[6]; + ct->tm_mon = time_str[5]; + ct->tm_mday = time_str[4]; + ct->tm_wday = time_str[3]; + ct->tm_hour = time_str[2]; + ct->tm_min = time_str[1]; + ct->tm_sec = time_str[0]; + return 0; +} + +static int GetWeekDay(int year, int month, int day) +{ + if(month==1||month==2) + { + year -=1; + month +=12; + } + + return (day+1+2*month+3*(month+1)/5+year+(year/4)-year/100+year/400)%7+1; +} + +static uint32 RtcConfigure(void* drv, struct BusConfigureInfo* configure_info) +{ + NULL_PARAM_CHECK(drv); + struct RtcDriver* rtc_drv = (struct RtcDriver*)drv; + struct RtcDrvConfigureParam* drv_param = (struct RtcDrvConfigureParam*)configure_info->private_data; + int cmd = drv_param->rtc_operation_cmd; + time_t* time = drv_param->time; + + switch(cmd) + { + case OPER_RTC_GET_TIME: + { + struct tm ct; + RtcGetTime(&ct); + *time = mktime(&ct); + } + break; + + case OPER_RTC_SET_TIME: + { + char time_str[MAX_TIME_STR_SIZE] = {0}; + struct tm *ct = localtime(time); + strftime(time_str, MAX_TIME_STR_SIZE, "%y-%m-%d %H:%M:%S", ct); + RtcSetTime(time_str); + } + break; + } + + return EOK; +} + +int RtcConfiguration(void) +{ + BOARD_InitI2C1Pins(); + RtcI2cInit(); + RtcInit(); + return 0; +} + +/*manage the rtc device operations*/ +static const struct RtcDevDone dev_done = +{ + .open = NONE, + .close = NONE, + .write = NONE, + .read = NONE, +}; + +static int BoardRtcBusInit(struct RtcBus* rtc_bus, struct RtcDriver* rtc_driver) +{ + x_err_t ret = EOK; + /*Init the rtc bus */ + ret = RtcBusInit(rtc_bus, RTC_BUS_NAME); + + if(EOK != ret) + { + KPrintf("hw_rtc_init RtcBusInit error %d\n", ret); + return ERROR; + } + + /*Init the rtc driver*/ + ret = RtcDriverInit(rtc_driver, RTC_DRV_NAME); + + if(EOK != ret) + { + KPrintf("hw_rtc_init RtcDriverInit error %d\n", ret); + return ERROR; + } + + /*Attach the rtc driver to the rtc bus*/ + ret = RtcDriverAttachToBus(RTC_DRV_NAME, RTC_BUS_NAME); + + if(EOK != ret) + { + KPrintf("hw_rtc_init RtcDriverAttachToBus error %d\n", ret); + return ERROR; + } + + return ret; +} + +/*Attach the rtc device to the rtc bus*/ +static int BoardRtcDevBend(void) +{ + x_err_t ret = EOK; + static struct RtcHardwareDevice rtc_device; + memset(&rtc_device, 0, sizeof(struct RtcHardwareDevice)); + rtc_device.dev_done = &(dev_done); + ret = RtcDeviceRegister(&rtc_device, NONE, RTC_DEVICE_NAME); + + if(EOK != ret) + { + KPrintf("hw_rtc_init RtcDeviceInit device %s error %d\n", RTC_DEVICE_NAME, ret); + return ERROR; + } + + ret = RtcDeviceAttachToBus(RTC_DEVICE_NAME, RTC_BUS_NAME); + + if(EOK != ret) + { + KPrintf("hw_rtc_init RtcDeviceAttachToBus device %s error %d\n", RTC_DEVICE_NAME, ret); + return ERROR; + } + + return ret; +} + +int Imxrt1052HwRtcInit(void) +{ + x_err_t ret = EOK; + static struct RtcBus rtc_bus; + memset(&rtc_bus, 0, sizeof(struct RtcBus)); + static struct RtcDriver rtc_driver; + memset(&rtc_driver, 0, sizeof(struct RtcDriver)); + rtc_driver.configure = &(RtcConfigure); + ret = BoardRtcBusInit(&rtc_bus, &rtc_driver); + + if(EOK != ret) + { + KPrintf("hw_rtc_init error ret %u\n", ret); + return ERROR; + } + + ret = BoardRtcDevBend(); + + if(EOK != ret) + { + KPrintf("hw_rtc_init error ret %u\n", ret); + return ERROR; + } + + RtcConfiguration(); + return ret; +} + +void RtcTestRx8010(int argc, char* argv[]) +{ + if(argc == 2) + { + if(RtcSetTime(argv[1]) == 0) + { + RtcGetTime(NULL); + } + } + else + { + RtcGetTime(NULL); + } +} + +SHELL_EXPORT_CMD(SHELL_CMD_PERMISSION(0)| SHELL_CMD_TYPE(SHELL_TYPE_CMD_MAIN)| SHELL_CMD_PARAM_NUM(3), + rtc, RtcTestRx8010, i2c rtc "date time"); + diff --git a/Ubiquitous/XiZi/board/ok1052-c/third_party_driver/sdio/Kconfig b/Ubiquitous/XiZi/board/ok1052-c/third_party_driver/sdio/Kconfig new file mode 100644 index 0000000..c2ceb30 --- /dev/null +++ b/Ubiquitous/XiZi/board/ok1052-c/third_party_driver/sdio/Kconfig @@ -0,0 +1,24 @@ +if BSP_USING_SDIO + config SDIO_BUS_NAME + string "sdio bus name" + default "sdio" + + config SDIO_DRIVER_NAME + string "sdio driver name" + default "sdio_drv" + + config SDIO_DEVICE_NAME + string "sdio device name" + default "sdio_dev" + + config MOUNT_SDCARD_FS + bool "mount cd card file system" + default n + select MOUNT_SDCARD + + if MOUNT_SDCARD_FS + config MOUNT_SDCARD_FS_TYPE + int "choose file system type : FATFS(0) LWEXT4(3)" + default 0 + endif +endif diff --git a/Ubiquitous/XiZi/board/ok1052-c/third_party_driver/sdio/Makefile b/Ubiquitous/XiZi/board/ok1052-c/third_party_driver/sdio/Makefile new file mode 100644 index 0000000..7e45190 --- /dev/null +++ b/Ubiquitous/XiZi/board/ok1052-c/third_party_driver/sdio/Makefile @@ -0,0 +1,5 @@ +SRC_DIR := sdmmc + +SRC_FILES := connect_sdio.c + +include $(KERNEL_ROOT)/compiler.mk diff --git a/Ubiquitous/XiZi/board/ok1052-c/third_party_driver/sdio/connect_sdio.c b/Ubiquitous/XiZi/board/ok1052-c/third_party_driver/sdio/connect_sdio.c new file mode 100644 index 0000000..bebbce7 --- /dev/null +++ b/Ubiquitous/XiZi/board/ok1052-c/third_party_driver/sdio/connect_sdio.c @@ -0,0 +1,460 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +/** +* @file connect_sdio.c +* @brief support sdio function using bus driver framework on OK1052 board +* @version 2.0 +* @author AIIT XUOS Lab +* @date 2022-01-24 +*/ + +/************************************************* +File name: connect_sdio.c +Description: support ok1052-c board sd card configure and sdio bus register function +Others: take SDK_2.6.1_MIMXRT1052xxxxB/boards/evkbimxrt1050/driver_examples/sdcard/polling/sdcard_polling.c for references +History: +1. Date: 2022-01-24 +Author: AIIT XUOS Lab +Modification: +1. support ok1052-c board sdio configure, write and read +2. support ok1052-c board sdio bus device and driver register +*************************************************/ + +#include + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +#define SDCARD_POWER_CTRL_FUNCTION_EXIST + +/*! @brief Data block count accessed in card */ +#define DATA_BLOCK_COUNT (5U) +/*! @brief Start data block number accessed in card */ +#define DATA_BLOCK_START (2U) +/*! @brief Data buffer size. */ +#define DATA_BUFFER_SIZE (FSL_SDMMC_DEFAULT_BLOCK_SIZE * DATA_BLOCK_COUNT) + +#define BOARD_USDHC_SDCARD_POWER_CONTROL(state) \ + (GPIO_PinWrite(BOARD_SD_POWER_RESET_GPIO, BOARD_SD_POWER_RESET_GPIO_PIN, state)) + +/******************************************************************************* + * Prototypes + ******************************************************************************/ +static void BoardPowerOffSdCard(void); +static void BoardPowerOnSdCard(void); + +/*! + * @brief printf the card information log. + * + * @param card Card descriptor. + */ +static void CardInformationLog(sd_card_t *card); + +/******************************************************************************* + * Variables + ******************************************************************************/ + +/* @brief decription about the read/write buffer + * The size of the read/write buffer should be a multiple of 512, since SDHC/SDXC card uses 512-byte fixed + * block length and this driver example is enabled with a SDHC/SDXC card.If you are using a SDSC card, you + * can define the block length by yourself if the card supports partial access. + * The address of the read/write buffer should align to the specific DMA data buffer address align value if + * DMA transfer is used, otherwise the buffer address is not important. + * At the same time buffer address/size should be aligned to the cache line size if cache is supported. + */ +/*! @brief Data written to the card */ +SDK_ALIGN(uint8_t g_data_write[SDK_SIZEALIGN(DATA_BUFFER_SIZE, SDMMC_DATA_BUFFER_ALIGN_CACHE)], + MAX(SDMMC_DATA_BUFFER_ALIGN_CACHE, SDMMCHOST_DMA_BUFFER_ADDR_ALIGN)); +/*! @brief Data read from the card */ +SDK_ALIGN(uint8_t g_data_read[SDK_SIZEALIGN(DATA_BUFFER_SIZE, SDMMC_DATA_BUFFER_ALIGN_CACHE)], + MAX(SDMMC_DATA_BUFFER_ALIGN_CACHE, SDMMCHOST_DMA_BUFFER_ADDR_ALIGN)); + +/*! @brief SDMMC host detect card configuration */ +static const sdmmchost_detect_card_t s_sdcard_detect = { +#ifndef BOARD_SD_DETECT_TYPE + .cdType = kSDMMCHOST_DetectCardByGpioCD, +#else + .cdType = BOARD_SD_DETECT_TYPE, +#endif + .cdTimeOut_ms = (~0U), +}; + +/*! @brief SDMMC card power control configuration */ +#if defined SDCARD_POWER_CTRL_FUNCTION_EXIST +static const sdmmchost_pwr_card_t s_sdcard_pwr_ctrl = { + .powerOn = BoardPowerOnSdCard, + .powerOnDelay_ms = 0U, + .powerOff = BoardPowerOffSdCard, + .powerOffDelay_ms = 0U, +}; +#endif + +/*! @brief SDMMC card power control configuration */ +#if defined SDCARD_SWITCH_VOLTAGE_FUNCTION_EXIST +static const sdmmchost_card_switch_voltage_func_t s_sdcard_voltage_switch = { + .cardSignalLine1V8 = BOARD_USDHC_Switch_VoltageTo1V8, + .cardSignalLine3V3 = BOARD_USDHC_Switch_VoltageTo3V3, +}; +#endif + +/*! @brief Card descriptor. */ +static sd_card_t g_sd; +static int sd_lock = -1; + +static void BoardUSDHCClockConfiguration(void) +{ + CLOCK_InitSysPll(&sysPllConfig_BOARD_BootClockRUN); + /*configure system pll PFD0 fractional divider to 24, output clock is 528MHZ * 18 / 24 = 396 MHZ*/ + CLOCK_InitSysPfd(kCLOCK_Pfd0, 24U); + /* Configure USDHC clock source and divider */ + CLOCK_SetDiv(kCLOCK_Usdhc1Div, 0U); + CLOCK_SetMux(kCLOCK_Usdhc1Mux, 1U); +} + +static void BoardPowerOffSdCard(void) +{ + /* + Do nothing here. + + SD card will not be detected correctly if the card VDD is power off, + the reason is caused by card VDD supply to the card detect circuit, this issue is exist on EVK board rev A1 and + A2. + + If power off function is not implemented after soft reset and prior to SD Host initialization without + remove/insert card, + a UHS-I card may not reach its highest speed mode during the second card initialization. + Application can avoid this issue by toggling the SD_VDD (GPIO) before the SD host initialization. + */ +} + +static void BoardPowerOnSdCard(void) +{ + BOARD_USDHC_SDCARD_POWER_CONTROL(1); +} + +static void CardInformationLog(sd_card_t *card) +{ + NULL_PARAM_CHECK(card); + + KPrintf("\r\nCard size %d * %d bytes\r\n", card->blockCount, card->blockSize); + KPrintf("\r\nWorking condition:\r\n"); + if (card->operationVoltage == kCARD_OperationVoltage330V) { + KPrintf("\r\n Voltage : 3.3V\r\n"); + } else if (card->operationVoltage == kCARD_OperationVoltage180V) { + KPrintf("\r\n Voltage : 1.8V\r\n"); + } + + if (card->currentTiming == kSD_TimingSDR12DefaultMode) { + if (card->operationVoltage == kCARD_OperationVoltage330V) { + KPrintf("\r\n Timing mode: Default mode\r\n"); + } else if (card->operationVoltage == kCARD_OperationVoltage180V) { + KPrintf("\r\n Timing mode: SDR12 mode\r\n"); + } + } else if (card->currentTiming == kSD_TimingSDR25HighSpeedMode) { + if (card->operationVoltage == kCARD_OperationVoltage180V) { + KPrintf("\r\n Timing mode: SDR25\r\n"); + } else { + KPrintf("\r\n Timing mode: High Speed\r\n"); + } + } else if (card->currentTiming == kSD_TimingSDR50Mode) { + KPrintf("\r\n Timing mode: SDR50\r\n"); + } else if (card->currentTiming == kSD_TimingSDR104Mode) { + KPrintf("\r\n Timing mode: SDR104\r\n"); + } else if (card->currentTiming == kSD_TimingDDR50Mode) { + KPrintf("\r\n Timing mode: DDR50\r\n"); + } + + KPrintf("\r\n Freq : %d HZ\r\n", card->busClock_Hz); +} + +static uint32 SdioConfigure(void *drv, struct BusConfigureInfo *configure_info) +{ + NULL_PARAM_CHECK(drv); + NULL_PARAM_CHECK(configure_info); + + if (configure_info->configure_cmd == OPER_BLK_GETGEOME) { + NULL_PARAM_CHECK(configure_info->private_data); + struct DeviceBlockArrange *args = (struct DeviceBlockArrange *)configure_info->private_data; + + args->size_perbank = g_sd.blockSize; + args->block_size = g_sd.blockSize; + args->bank_num = g_sd.blockCount; + } + + return EOK; +} + +static uint32 SdioOpen(void *dev) +{ + NULL_PARAM_CHECK(dev); + + if(sd_lock >= 0) { + KSemaphoreDelete(sd_lock); + } + sd_lock = KSemaphoreCreate(1); + if (sd_lock < 0){ + return ERROR; + } + + return EOK; +} + +static uint32 SdioClose(void *dev) +{ + NULL_PARAM_CHECK(dev); + + KSemaphoreDelete(sd_lock); + + return EOK; +} + +static uint32 SdioRead(void *dev, struct BusBlockReadParam *read_param) +{ + uint8 ret = EOK; + uint32 sector = read_param->pos; + uint32 block_num = read_param->size; + uint8 *read_buffer = (uint8 *)read_param->buffer; + + KSemaphoreObtain(sd_lock, WAITING_FOREVER); + + if (kStatus_Success != SD_ReadBlocks(&g_sd, read_buffer, sector, block_num)) { + KPrintf("Read multiple data blocks failed.\r\n"); + return 0; + } + + KSemaphoreAbandon(sd_lock); + + return read_param->size; +} + +static uint32 SdioWrite(void *dev, struct BusBlockWriteParam *write_param) +{ + uint8 ret = EOK; + uint32 sector = write_param->pos; + uint32 block_num = write_param->size; + const uint8 *write_buffer = (uint8 *)write_param->buffer; + + KSemaphoreObtain(sd_lock, WAITING_FOREVER); + + if (kStatus_Success != SD_WriteBlocks(&g_sd, write_buffer, sector, block_num)) { + KPrintf("Write multiple data blocks failed.\r\n"); + return 0; + } + + KSemaphoreAbandon(sd_lock); + + return write_param->size; +} + +static int SdioControl(struct HardwareDev *dev, struct HalDevBlockParam *block_param) +{ + NULL_PARAM_CHECK(dev); + + if (OPER_BLK_GETGEOME == block_param->cmd) { + block_param->dev_block.size_perbank = g_sd.blockSize; + block_param->dev_block.block_size = g_sd.blockSize; + block_param->dev_block.bank_num = g_sd.blockCount; + } + + return EOK; +} + +static struct SdioDevDone dev_done = +{ + SdioOpen, + SdioClose, + SdioWrite, + SdioRead, +}; + +#if defined(FS_VFS) && defined(MOUNT_SDCARD_FS) +#include + +int sd_mount_flag = 0; + +/** + * @description: Mount SD card + * @return 0 + */ +static int MountSDCardFs(enum FilesystemType fs_type) +{ + if (MountFilesystem(SDIO_BUS_NAME, SDIO_DEVICE_NAME, SDIO_DRIVER_NAME, fs_type, "/") == 0) { + sd_mount_flag = 1; + KPrintf("Sd card mount to '/'"); + } else { + KPrintf("Sd card mount to '/' failed!"); + } + + return 0; +} +#endif + +static void SdCardAttach(void) +{ + bool is_read_only; + static sd_card_t *card = &g_sd; + + KPrintf("\r\nCard inserted.\r\n"); + /* reset host once card re-plug in */ + SD_HostReset(&(card->host)); + /* power on the card */ + SD_PowerOnCard(card->host.base, card->usrParam.pwr); + KPrintf("Power on done\n"); + + /* Init card. */ + if (SD_CardInit(card)) { + KPrintf("\r\nSD card init failed.\r\n"); + return; + } + + /* card information log */ + CardInformationLog(card); + + /* Check if card is readonly. */ + is_read_only = SD_CheckReadOnly(card); + +#ifdef MOUNT_SDCARD_FS + /*mount file system*/ + MountSDCardFs(MOUNT_SDCARD_FS_TYPE); +#endif +} + +static void SdCardDetach(void) +{ + /*unmount file system*/ + KPrintf("\r\nCard detect extracted.\r\n"); + +#ifdef MOUNT_SDCARD_FS + UnmountFileSystem("/"); +#endif +} + +static uint8 SdCardReadCd(void) +{ + BusType pin; + + pin = BusFind(PIN_BUS_NAME); + + pin->owner_haldev = BusFindDevice(pin, PIN_DEVICE_NAME); + + struct PinStat PinStat; + + struct BusBlockReadParam read_param; + read_param.buffer = (void *)&PinStat; + + PinStat.pin = IMXRT_GET_PIN(2, 28); + + return BusDevReadData(pin->owner_haldev, &read_param); +} + +static void SdCardTask(void* parameter) +{ + static int sd_card_status = 0; + + while (1) { + if (!SdCardReadCd()) { + if (!sd_card_status) { + SdCardAttach(); + sd_card_status = 1; + } + } else { + if (sd_card_status) { + SdCardDetach(); + sd_card_status = 0; + } + } + } +} + +#ifdef MOUNT_SDCARD +int MountSDCard() +{ + int sd_card_task = 0; + sd_card_task = KTaskCreate("sd_card", SdCardTask, NONE, + SD_CARD_STACK_SIZE, 8); + if(sd_card_task < 0) { + KPrintf("sd_card_task create failed ...%s %d.\n", __FUNCTION__,__LINE__); + return ERROR; + } + + StartupKTask(sd_card_task); + + return EOK; +} +#endif + + +int Imxrt1052HwSdioInit(void) +{ + x_err_t ret = EOK; + + static struct SdioBus sdio_bus; + static struct SdioDriver sdio_drv; + static struct SdioHardwareDevice sdio_dev; + static sd_card_t *card = &g_sd; + + memset(&sdio_bus, 0, sizeof(struct SdioBus)); + memset(&sdio_drv, 0, sizeof(struct SdioDriver)); + memset(&sdio_dev, 0, sizeof(struct SdioHardwareDevice)); + + BoardUSDHCClockConfiguration(); + + card->host.base = SD_HOST_BASEADDR; + card->host.sourceClock_Hz = SD_HOST_CLK_FREQ; + + /* card detect type */ + card->usrParam.cd = &s_sdcard_detect; + +#if defined SDCARD_POWER_CTRL_FUNCTION_EXIST + card->usrParam.pwr = &s_sdcard_pwr_ctrl; +#endif + +#if defined DEMO_SDCARD_SWITCH_VOLTAGE_FUNCTION_EXIST + card->usrParam.cardVoltage = &s_sdcard_voltage_switch; +#endif + + /* SD host init function */ + if (SD_HostInit(card) != kStatus_Success) { + KPrintf("\r\nSD host init fail\r\n"); + return ERROR; + } + + ret = SdioBusInit(&sdio_bus, SDIO_BUS_NAME); + if (ret != EOK) { + KPrintf("Sdio bus init error %d\n", ret); + return ERROR; + } + + ret = SdioDriverInit(&sdio_drv, SDIO_DRIVER_NAME); + if (ret != EOK) { + KPrintf("Sdio driver init error %d\n", ret); + return ERROR; + } + ret = SdioDriverAttachToBus(SDIO_DRIVER_NAME, SDIO_BUS_NAME); + if (ret != EOK) { + KPrintf("Sdio driver attach error %d\n", ret); + return ERROR; + } + + sdio_dev.dev_done = &dev_done; + sdio_dev.haldev.dev_block_control = SdioControl; + ret = SdioDeviceRegister(&sdio_dev, SDIO_DEVICE_NAME); + if (ret != EOK) { + KPrintf("Sdio device register error %d\n", ret); + return ERROR; + } + ret = SdioDeviceAttachToBus(SDIO_DEVICE_NAME, SDIO_BUS_NAME); + if (ret != EOK) { + KPrintf("Sdio device register error %d\n", ret); + return ERROR; + } + + return ret; +} diff --git a/Ubiquitous/XiZi/board/ok1052-c/third_party_driver/semc/Kconfig b/Ubiquitous/XiZi/board/ok1052-c/third_party_driver/semc/Kconfig new file mode 100644 index 0000000..f081299 --- /dev/null +++ b/Ubiquitous/XiZi/board/ok1052-c/third_party_driver/semc/Kconfig @@ -0,0 +1,9 @@ +config BSP_USING_EXTSRAM + bool "config semc extern sram" + default n + select MEM_EXTERN_SRAM + if BSP_USING_EXTSRAM + config EXTSRAM_MAX_NUM + int "config extsram chip num" + default 4 + endif diff --git a/Ubiquitous/XiZi/board/ok1052-c/third_party_driver/semc/Makefile b/Ubiquitous/XiZi/board/ok1052-c/third_party_driver/semc/Makefile new file mode 100644 index 0000000..6438aa6 --- /dev/null +++ b/Ubiquitous/XiZi/board/ok1052-c/third_party_driver/semc/Makefile @@ -0,0 +1,3 @@ +SRC_FILES := connect_semc.c fsl_semc.c semc_externsdram_test.c + +include $(KERNEL_ROOT)/compiler.mk diff --git a/Ubiquitous/XiZi/board/ok1052-c/third_party_driver/semc/connect_semc.c b/Ubiquitous/XiZi/board/ok1052-c/third_party_driver/semc/connect_semc.c new file mode 100644 index 0000000..2477fb2 --- /dev/null +++ b/Ubiquitous/XiZi/board/ok1052-c/third_party_driver/semc/connect_semc.c @@ -0,0 +1,57 @@ +#include "fsl_semc.h" +#include "clock_config.h" +#include + +#define EXAMPLE_SEMC SEMC +#define EXAMPLE_SEMC_START_ADDRESS (0x80000000U) +#define EXAMPLE_SEMC_CLK_FREQ CLOCK_GetFreq(kCLOCK_SemcClk) +#define SEMC_SRAM_SIZE (32 * 1024 * 1024) + +status_t BOARD_InitSEMC(void) +{ + semc_config_t config; + semc_sdram_config_t sdramconfig; + uint32_t clockFrq = EXAMPLE_SEMC_CLK_FREQ; + + /* Initializes the MAC configure structure to zero. */ + memset(&config, 0, sizeof(semc_config_t)); + memset(&sdramconfig, 0, sizeof(semc_sdram_config_t)); + + /* Initialize SEMC. */ + SEMC_GetDefaultConfig(&config); + config.dqsMode = kSEMC_Loopbackdqspad; /* For more accurate timing. */ + SEMC_Init(SEMC, &config); + + /* Configure SDRAM. */ + sdramconfig.csxPinMux = kSEMC_MUXCSX0; + sdramconfig.address = 0x80000000; + sdramconfig.memsize_kbytes = 32 * 1024; /* 32MB = 32*1024*1KBytes*/ + sdramconfig.portSize = kSEMC_PortSize16Bit; + sdramconfig.burstLen = kSEMC_Sdram_BurstLen8; + sdramconfig.columnAddrBitNum = kSEMC_SdramColunm_9bit; + sdramconfig.casLatency = kSEMC_LatencyThree; + sdramconfig.tPrecharge2Act_Ns = 18; /* Trp 18ns */ + sdramconfig.tAct2ReadWrite_Ns = 18; /* Trcd 18ns */ + sdramconfig.tRefreshRecovery_Ns = 67; /* Use the maximum of the (Trfc , Txsr). */ + sdramconfig.tWriteRecovery_Ns = 12; /* 12ns */ + sdramconfig.tCkeOff_Ns = + 42; /* The minimum cycle of SDRAM CLK off state. CKE is off in self refresh at a minimum period tRAS.*/ + sdramconfig.tAct2Prechage_Ns = 42; /* Tras 42ns */ + sdramconfig.tSelfRefRecovery_Ns = 67; + sdramconfig.tRefresh2Refresh_Ns = 60; + sdramconfig.tAct2Act_Ns = 60; + sdramconfig.tPrescalePeriod_Ns = 160 * (1000000000 / clockFrq); + sdramconfig.refreshPeriod_nsPerRow = 64 * 1000000 / 8192; /* 64ms/8192 */ + sdramconfig.refreshUrgThreshold = sdramconfig.refreshPeriod_nsPerRow; + sdramconfig.refreshBurstLen = 1; + return SEMC_ConfigureSDRAM(SEMC, kSEMC_SDRAM_CS0, &sdramconfig, clockFrq); +} + +#ifdef BSP_USING_EXTSRAM +int ExtSramInit(void) +{ + extern void ExtSramInitBoardMemory(void *start_phy_address, void *end_phy_address, uint8 extsram_idx); + ExtSramInitBoardMemory((void*)(EXAMPLE_SEMC_START_ADDRESS), (void*)((EXAMPLE_SEMC_START_ADDRESS + SEMC_SRAM_SIZE)), kSEMC_SDRAM_CS0); + return 0; +} +#endif \ No newline at end of file diff --git a/Ubiquitous/XiZi/board/ok1052-c/third_party_driver/semc/semc_externsdram_test.c b/Ubiquitous/XiZi/board/ok1052-c/third_party_driver/semc/semc_externsdram_test.c new file mode 100644 index 0000000..c09b6dc --- /dev/null +++ b/Ubiquitous/XiZi/board/ok1052-c/third_party_driver/semc/semc_externsdram_test.c @@ -0,0 +1,180 @@ +/* + * Copyright 2017 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#include "board.h" + +#define EXAMPLE_SEMC_START_ADDRESS (0x80000000U) + +#define SEMC_EXAMPLE_DATALEN (0x1000U) + +/******************************************************************************* + * Prototypes + ******************************************************************************/ +static void SEMC_SDRAMReadWrite32Bit(void); +static void SEMC_SDRAMReadWrite16Bit(void); +static void SEMC_SDRAMReadWrite8Bit(void); +/******************************************************************************* + * Variables + ******************************************************************************/ + +uint32_t sdram_writeBuffer[SEMC_EXAMPLE_DATALEN]; +uint32_t sdram_readBuffer[SEMC_EXAMPLE_DATALEN]; + +/*! + * @brief Main function + */ +int semc_externsram_test(void) +{ + KPrintf("\r\n SEMC SDRAM Example Start!\r\n"); + + /* 32Bit data read and write. */ + SEMC_SDRAMReadWrite32Bit(); + /* 16Bit data read and write. */ + SEMC_SDRAMReadWrite16Bit(); + /* 8Bit data read and write. */ + SEMC_SDRAMReadWrite8Bit(); + + KPrintf("\r\n SEMC SDRAM Example End.\r\n"); + +} +SHELL_EXPORT_CMD(SHELL_CMD_PERMISSION(0)|SHELL_CMD_TYPE(SHELL_TYPE_CMD_FUNC)|SHELL_CMD_PARAM_NUM(0),semc_externsram_test, semc_externsram_test, semc_externsram_test ); + +void SEMC_SDRAMReadWrite32Bit(void) +{ + uint32_t index; + uint32_t datalen = SEMC_EXAMPLE_DATALEN; + uint32_t *sdram = (uint32_t *)EXAMPLE_SEMC_START_ADDRESS; /* SDRAM start address. */ + int result = 0; + + KPrintf("\r\n SEMC SDRAM Memory 32 bit Write Start, Start Address 0x%x, Data Length %d !\r\n", sdram, datalen); + /* Prepare data and write to SDRAM. */ + for (index = 0; index < datalen; index++) + { + sdram_writeBuffer[index] = index; + sdram[index] = sdram_writeBuffer[index]; + } + + KPrintf("\r\n SEMC SDRAM Read 32 bit Data Start, Start Address 0x%x, Data Length %d !\r\n", sdram, datalen); + /* Read data from the SDRAM. */ + for (index = 0; index < datalen; index++) + { + sdram_readBuffer[index] = sdram[index]; + } + + KPrintf("\r\n SEMC SDRAM 32 bit Data Write and Read Compare Start!\r\n"); + /* Compare the two buffers. */ + while (datalen--) + { + if (sdram_writeBuffer[datalen] != sdram_readBuffer[datalen]) + { + result = -1; + break; + } + } + + if (result < 0) + { + KPrintf("\r\n SEMC SDRAM 32 bit Data Write and Read Compare Failed!\r\n"); + } + else + { + KPrintf("\r\n SEMC SDRAM 32 bit Data Write and Read Compare Succeed!\r\n"); + } +} + +static void SEMC_SDRAMReadWrite16Bit(void) +{ + uint32_t index; + uint32_t datalen = SEMC_EXAMPLE_DATALEN; + uint16_t *sdram = (uint16_t *)EXAMPLE_SEMC_START_ADDRESS; /* SDRAM start address. */ + int result = 0; + + KPrintf("\r\n SEMC SDRAM Memory 16 bit Write Start, Start Address 0x%x, Data Length %d !\r\n", sdram, datalen); + + memset(sdram_writeBuffer, 0, sizeof(sdram_writeBuffer)); + memset(sdram_readBuffer, 0, sizeof(sdram_readBuffer)); + + /* Prepare data and write to SDRAM. */ + for (index = 0; index < datalen; index++) + { + sdram_writeBuffer[index] = index % 0xFFFF; + sdram[index] = sdram_writeBuffer[index]; + } + + KPrintf("\r\n SEMC SDRAM Read 16 bit Data Start, Start Address 0x%x, Data Length %d !\r\n", sdram, datalen); + /* Read data from the SDRAM. */ + for (index = 0; index < datalen; index++) + { + sdram_readBuffer[index] = sdram[index]; + } + + KPrintf("\r\n SEMC SDRAM 16 bit Data Write and Read Compare Start!\r\n"); + /* Compare the two buffers. */ + while (datalen--) + { + if (sdram_writeBuffer[datalen] != sdram_readBuffer[datalen]) + { + result = -1; + break; + } + } + + if (result < 0) + { + KPrintf("\r\n SEMC SDRAM 16 bit Data Write and Read Compare Failed!\r\n"); + } + else + { + KPrintf("\r\n SEMC SDRAM 16 bit Data Write and Read Compare Succeed!\r\n"); + } +} + +static void SEMC_SDRAMReadWrite8Bit(void) +{ + uint32_t index; + uint32_t datalen = SEMC_EXAMPLE_DATALEN; + uint8_t *sdram = (uint8_t *)EXAMPLE_SEMC_START_ADDRESS; /* SDRAM start address. */ + int result = 0; + + KPrintf("\r\n SEMC SDRAM Memory 8 bit Write Start, Start Address 0x%x, Data Length %d !\r\n", sdram, datalen); + + memset(sdram_writeBuffer, 0, sizeof(sdram_writeBuffer)); + memset(sdram_readBuffer, 0, sizeof(sdram_readBuffer)); + + /* Prepare data and write to SDRAM. */ + for (index = 0; index < datalen; index++) + { + sdram_writeBuffer[index] = index % 0x100; + sdram[index] = sdram_writeBuffer[index]; + } + + KPrintf("\r\n SEMC SDRAM Read 8 bit Data Start, Start Address 0x%x, Data Length %d !\r\n", sdram, datalen); + /* Read data from the SDRAM. */ + for (index = 0; index < datalen; index++) + { + sdram_readBuffer[index] = sdram[index]; + } + + KPrintf("\r\n SEMC SDRAM 8 bit Data Write and Read Compare Start!\r\n"); + /* Compare the two buffers. */ + while (datalen--) + { + if (sdram_writeBuffer[datalen] != sdram_readBuffer[datalen]) + { + result = -1; + break; + } + } + + if (result < 0) + { + KPrintf("\r\n SEMC SDRAM 8 bit Data Write and Read Compare Failed!\r\n"); + } + else + { + KPrintf("\r\n SEMC SDRAM 8 bit Data Write and Read Compare Succeed!\r\n"); + } +} diff --git a/Ubiquitous/XiZi/board/ok1052-c/third_party_driver/spi/Kconfig b/Ubiquitous/XiZi/board/ok1052-c/third_party_driver/spi/Kconfig new file mode 100755 index 0000000..d28e13d --- /dev/null +++ b/Ubiquitous/XiZi/board/ok1052-c/third_party_driver/spi/Kconfig @@ -0,0 +1,45 @@ +config BSP_USING_SPI1 +bool "Enable SPI1" +default y +if BSP_USING_SPI1 + config SPI_1_BUS_NAME + string "spi1 bus name" + default "spi1" + config SPI_1_DRV_NAME + string "spi bus 1 driver name" + default "spi1_drv" + config SPI_1_DEV_NAME_0 + string "spi bus 1 device name" + default "spi1_dev" +endif + +config BSP_USING_SPI2 +bool "Enable SPI2" +default y +if BSP_USING_SPI2 + config SPI_2_BUS_NAME + string "spi2 bus name" + default "spi2" + config SPI_2_DRV_NAME + string "spi bus 2 driver name" + default "spi2_drv" + config SPI_2_DEV_NAME_0 + string "spi bus 2 device name" + default "spi2_dev" +endif + +config BSP_USING_SPI3 +bool "Enable SPI3" +default y +if BSP_USING_SPI3 + config SPI_3_BUS_NAME + string "spi3 bus name" + default "spi3" + config SPI_3_DRV_NAME + string "spi bus 3 driver name" + default "spi3_drv" + config SPI_3_DEV_NAME_0 + string "spi bus 3 device name" + default "spi3_dev" +endif + diff --git a/Ubiquitous/XiZi/board/ok1052-c/third_party_driver/spi/Makefile b/Ubiquitous/XiZi/board/ok1052-c/third_party_driver/spi/Makefile new file mode 100755 index 0000000..8765fda --- /dev/null +++ b/Ubiquitous/XiZi/board/ok1052-c/third_party_driver/spi/Makefile @@ -0,0 +1,7 @@ +SRC_FILES := fsl_lpspi.c connect_spi.c + +ifeq ($(CONFIG_RESOURCES_SPI_SFUD),y) + SRC_FILES += connect_flash_spi.c +endif + +include $(KERNEL_ROOT)/compiler.mk diff --git a/Ubiquitous/XiZi/board/ok1052-c/third_party_driver/spi/connect_flash_spi.c b/Ubiquitous/XiZi/board/ok1052-c/third_party_driver/spi/connect_flash_spi.c new file mode 100755 index 0000000..2050937 --- /dev/null +++ b/Ubiquitous/XiZi/board/ok1052-c/third_party_driver/spi/connect_flash_spi.c @@ -0,0 +1,39 @@ +/* + * Copyright (c) 2022 RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2018-11-27 SummerGift add spi flash port file + */ + +/** +* @file connect_flash_spi.c +* @brief support ok1052-c board spi flash function and register to bus framework +* @version 1.0 +* @author AIIT XUOS Lab +* @date 2022-03-01 +*/ + +/************************************************* +File name: connect_flash_spi.c +Description: support ok1052-c board spi flash bus register function +Others: take RT-Thread v4.0.2/bsp/stm32/stm32f407-atk-explorer/board/ports/spi-flash-init.c + https://github.com/RT-Thread/rt-thread/tree/v4.0.2 +History: +1. Date: 2022-03-01 +Author: AIIT XUOS Lab +Modification: +1. for ok1052-c board compilation +*************************************************/ + +#include "flash_spi.h" + +int FlashW25qxxSpiDeviceInit(void) +{ +#ifdef BSP_USING_SPI1 + +#endif + return EOK; +} \ No newline at end of file diff --git a/Ubiquitous/XiZi/board/ok1052-c/third_party_driver/spi/connect_spi.c b/Ubiquitous/XiZi/board/ok1052-c/third_party_driver/spi/connect_spi.c new file mode 100755 index 0000000..5e23f02 --- /dev/null +++ b/Ubiquitous/XiZi/board/ok1052-c/third_party_driver/spi/connect_spi.c @@ -0,0 +1,958 @@ +/* + * Copyright (c) 2020 RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2018-11-5 SummerGift first version + * 2018-12-11 greedyhao Porting for stm32f7xx + * 2019-01-03 zylx modify DMA initialization and spixfer function + * 2020-01-15 whj4674672 Porting for stm32h7xx + * 2020-06-18 thread-liu Porting for stm32mp1xx + * 2020-10-14 Dozingfiretruck Porting for stm32wbxx + */ + +/** +* @file connect_spi.c +* @brief support ok1052-c board spi function and register to bus framework +* @version 1.0 +* @author AIIT XUOS Lab +* @date 2022-03-01 +*/ + +/************************************************* +File name: connect_spi.c +Description: support ok1052-c board spi configure and spi bus register function +Others: take RT-Thread v4.0.2/bsp/stm32/libraries/HAL_Drivers/drv_spi.c for references + https://github.com/RT-Thread/rt-thread/tree/v4.0.2 +History: +1. Date: 2022-03-01 +Author: AIIT XUOS Lab +Modification: +1. support ok1052-c board spi configure, write and read +2. support ok1052-c board spi bus device and driver register +3. add ok1052-c board spi test letter command +*************************************************/ + +#include "board.h" +#include "connect_spi.h" +#include "fsl_lpspi.h" +#include "pin_mux.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +#define SPI_PCS_FOR_INIT (kLPSPI_Pcs0) + +/* Select USB1 PLL PFD0 (720 MHz) as lpspi clock source */ +#define SPI_CLOCK_SOURCE_SELECT (1U) + +/* Clock divider for master lpspi clock source */ +#define SPI_CLOCK_SOURCE_DIVIDER (7U) + +#define SPI_CLOCK_FREQ (CLOCK_GetFreq(kCLOCK_Usb1PllPfd0Clk) / (SPI_CLOCK_SOURCE_DIVIDER + 1U)) + +#define TRANSFER_SIZE (512U) /*! Transfer dataSize .*/ +#define TRANSFER_BAUDRATE (500000U) /*! Transfer baudrate - 500k */ + +#define spi_print KPrintf + +typedef struct __spi_transfer_t +{ + uint32_t size; + volatile uint32_t cnt; + uint8_t water; + uint8_t fifo; + volatile bool completed; + uint8_t buf[TRANSFER_SIZE]; +}spi_transfer_t; + +#if defined(BSP_USING_SPI1) +struct Stm32Spi spi1; +spi_transfer_t spi1_rx_data; +spi_transfer_t spi1_tx_data; +#endif + +#if defined(BSP_USING_SPI2) +struct Stm32Spi spi2; +spi_transfer_t spi2_rx_data; +spi_transfer_t spi2_tx_data; +#endif + +#if defined(BSP_USING_SPI3) +struct Stm32Spi spi3; +spi_transfer_t spi3_rx_data; +spi_transfer_t spi3_tx_data; +#endif + +/******************************************************************************* + * Code + ******************************************************************************/ + +void LPSPI1_IRQHandler(int vector, void *param) +{ + LPSPI_Type *spi_base = LPSPI1; + int rx_size = spi1_rx_data.size < TRANSFER_SIZE ? spi1_rx_data.size : TRANSFER_SIZE; + int tx_size = spi1_tx_data.size < TRANSFER_SIZE ? spi1_tx_data.size : TRANSFER_SIZE; + + if (spi1_rx_data.cnt < rx_size) + { + /* First, disable the interrupts to avoid potentially triggering another interrupt + * while reading out the RX FIFO as more data may be coming into the RX FIFO. We'll + * re-enable the interrupts on the LPSPI state after reading out the FIFO. + */ + LPSPI_DisableInterrupts(spi_base, kLPSPI_RxInterruptEnable); + + while (LPSPI_GetRxFifoCount(spi_base)) + { + /*Read out the data*/ + spi1_rx_data.buf[spi1_rx_data.cnt] = LPSPI_ReadData(spi_base); + spi1_rx_data.cnt++; + + if (spi1_rx_data.cnt == rx_size) + { + break; + } + } + + /* Re-enable the interrupts only if rxCount indicates there is more data to receive, + * else we may get a spurious interrupt. + * */ + if (spi1_rx_data.cnt < rx_size) + { + /* Set the TDF and RDF interrupt enables simultaneously to avoid race conditions */ + LPSPI_EnableInterrupts(spi_base, kLPSPI_RxInterruptEnable); + } + } + + /*Update rxWatermark. There isn't RX interrupt for the last datas if the RX count is not greater than rxWatermark.*/ + if ((rx_size - spi1_rx_data.cnt) <= spi1_rx_data.water) + { + spi_base->FCR = + (spi_base->FCR & (~LPSPI_FCR_RXWATER_MASK)) | + LPSPI_FCR_RXWATER(((rx_size - spi1_rx_data.cnt) > 1) ? ((rx_size - spi1_rx_data.cnt) - 1U) : (0U)); + } + + if (spi1_tx_data.cnt < tx_size) + { + while ((LPSPI_GetTxFifoCount(spi_base) < spi1_tx_data.fifo) && + (spi1_tx_data.cnt - spi1_rx_data.cnt < spi1_tx_data.fifo)) + { + /*Write the word to TX register*/ + LPSPI_WriteData(spi_base, spi1_tx_data.buf[spi1_tx_data.cnt]); + spi1_tx_data.cnt++; + + if (spi1_tx_data.cnt == tx_size) + { + spi1_tx_data.completed = true; + /* Complete the transfer and disable the interrupts */ + LPSPI_DisableInterrupts(spi_base, kLPSPI_AllInterruptEnable); + break; + } + } + } + + /* Check if we're done with this transfer.*/ + if ((spi1_tx_data.cnt == tx_size) && (spi1_rx_data.cnt == tx_size)) + { + spi1_tx_data.completed = true; + /* Complete the transfer and disable the interrupts */ + LPSPI_DisableInterrupts(spi_base, kLPSPI_AllInterruptEnable); + } +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} + +DECLARE_HW_IRQ(LPSPI1_IRQn, LPSPI1_IRQHandler, NONE); + +void LPSPI2_IRQHandler(int vector, void *param) +{ + LPSPI_Type *spi_base = LPSPI2; + int rx_size = spi2_rx_data.size < TRANSFER_SIZE ? spi2_rx_data.size : TRANSFER_SIZE; + int tx_size = spi2_tx_data.size < TRANSFER_SIZE ? spi2_tx_data.size : TRANSFER_SIZE; + + if (spi2_rx_data.cnt < rx_size) + { + /* First, disable the interrupts to avoid potentially triggering another interrupt + * while reading out the RX FIFO as more data may be coming into the RX FIFO. We'll + * re-enable the interrupts on the LPSPI state after reading out the FIFO. + */ + LPSPI_DisableInterrupts(spi_base, kLPSPI_RxInterruptEnable); + + while (LPSPI_GetRxFifoCount(spi_base)) + { + /*Read out the data*/ + spi2_rx_data.buf[spi2_rx_data.cnt] = LPSPI_ReadData(spi_base); + spi2_rx_data.cnt++; + + if (spi2_rx_data.cnt == rx_size) + { + break; + } + } + + /* Re-enable the interrupts only if rxCount indicates there is more data to receive, + * else we may get a spurious interrupt. + * */ + if (spi2_rx_data.cnt < rx_size) + { + /* Set the TDF and RDF interrupt enables simultaneously to avoid race conditions */ + LPSPI_EnableInterrupts(spi_base, kLPSPI_RxInterruptEnable); + } + } + + /*Update rxWatermark. There isn't RX interrupt for the last datas if the RX count is not greater than rxWatermark.*/ + if ((rx_size - spi2_rx_data.cnt) <= spi2_rx_data.water) + { + spi_base->FCR = + (spi_base->FCR & (~LPSPI_FCR_RXWATER_MASK)) | + LPSPI_FCR_RXWATER(((rx_size - spi2_rx_data.cnt) > 1) ? ((rx_size - spi2_rx_data.cnt) - 1U) : (0U)); + } + + if (spi2_tx_data.cnt < tx_size) + { + while ((LPSPI_GetTxFifoCount(spi_base) < spi2_tx_data.fifo) && + (spi2_tx_data.cnt - spi2_rx_data.cnt < spi2_tx_data.fifo)) + { + /*Write the word to TX register*/ + LPSPI_WriteData(spi_base, spi2_tx_data.buf[spi2_tx_data.cnt]); + spi2_tx_data.cnt++; + + if (spi2_tx_data.cnt == tx_size) + { + spi2_tx_data.completed = true; + /* Complete the transfer and disable the interrupts */ + LPSPI_DisableInterrupts(spi_base, kLPSPI_AllInterruptEnable); + break; + } + } + } + + /* Check if we're done with this transfer.*/ + if ((spi2_tx_data.cnt == tx_size) && (spi2_rx_data.cnt == tx_size)) + { + spi2_tx_data.completed = true; + /* Complete the transfer and disable the interrupts */ + LPSPI_DisableInterrupts(spi_base, kLPSPI_AllInterruptEnable); + } +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} + +DECLARE_HW_IRQ(LPSPI2_IRQn, LPSPI2_IRQHandler, NONE); + +void LPSPI3_IRQHandler(int vector, void *param) +{ + LPSPI_Type *spi_base = LPSPI3; + int rx_size = spi3_rx_data.size < TRANSFER_SIZE ? spi3_rx_data.size : TRANSFER_SIZE; + int tx_size = spi3_tx_data.size < TRANSFER_SIZE ? spi3_tx_data.size : TRANSFER_SIZE; + + if (spi3_rx_data.cnt < rx_size) + { + /* First, disable the interrupts to avoid potentially triggering another interrupt + * while reading out the RX FIFO as more data may be coming into the RX FIFO. We'll + * re-enable the interrupts on the LPSPI state after reading out the FIFO. + */ + LPSPI_DisableInterrupts(spi_base, kLPSPI_RxInterruptEnable); + + while (LPSPI_GetRxFifoCount(spi_base)) + { + /*Read out the data*/ + spi3_rx_data.buf[spi3_rx_data.cnt] = LPSPI_ReadData(spi_base); + spi3_rx_data.cnt++; + + if (spi3_rx_data.cnt == rx_size) + { + break; + } + } + + /* Re-enable the interrupts only if rxCount indicates there is more data to receive, + * else we may get a spurious interrupt. + * */ + if (spi3_rx_data.cnt < rx_size) + { + /* Set the TDF and RDF interrupt enables simultaneously to avoid race conditions */ + LPSPI_EnableInterrupts(spi_base, kLPSPI_RxInterruptEnable); + } + } + + /*Update rxWatermark. There isn't RX interrupt for the last datas if the RX count is not greater than rxWatermark.*/ + if ((rx_size - spi3_rx_data.cnt) <= spi3_rx_data.water) + { + spi_base->FCR = + (spi_base->FCR & (~LPSPI_FCR_RXWATER_MASK)) | + LPSPI_FCR_RXWATER(((rx_size - spi3_rx_data.cnt) > 1) ? ((rx_size - spi3_rx_data.cnt) - 1U) : (0U)); + } + + if (spi3_tx_data.cnt < tx_size) + { + while ((LPSPI_GetTxFifoCount(spi_base) < spi3_tx_data.fifo) && + (spi3_tx_data.cnt - spi3_rx_data.cnt < spi3_tx_data.fifo)) + { + /*Write the word to TX register*/ + LPSPI_WriteData(spi_base, spi3_tx_data.buf[spi3_tx_data.cnt]); + spi3_tx_data.cnt++; + + if (spi3_tx_data.cnt == tx_size) + { + spi3_tx_data.completed = true; + /* Complete the transfer and disable the interrupts */ + LPSPI_DisableInterrupts(spi_base, kLPSPI_AllInterruptEnable); + break; + } + } + } + + /* Check if we're done with this transfer.*/ + if ((spi3_tx_data.cnt == tx_size) && (spi3_rx_data.cnt == tx_size)) + { + spi3_tx_data.completed = true; + /* Complete the transfer and disable the interrupts */ + LPSPI_DisableInterrupts(spi_base, kLPSPI_AllInterruptEnable); + } +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} + +DECLARE_HW_IRQ(LPSPI3_IRQn, LPSPI3_IRQHandler, NONE); + +void SpiMasterInit(LPSPI_Type *base) +{ + lpspi_master_config_t cfg; + + /*Master config*/ + cfg.baudRate = TRANSFER_BAUDRATE; + cfg.bitsPerFrame = 8; + cfg.cpol = kLPSPI_ClockPolarityActiveHigh; + cfg.cpha = kLPSPI_ClockPhaseFirstEdge; + cfg.direction = kLPSPI_MsbFirst; + + cfg.pcsToSckDelayInNanoSec = 1000000000 / cfg.baudRate; + cfg.lastSckToPcsDelayInNanoSec = 1000000000 / cfg.baudRate; + cfg.betweenTransferDelayInNanoSec = 1000000000 / cfg.baudRate; + + cfg.whichPcs = SPI_PCS_FOR_INIT; + cfg.pcsActiveHighOrLow = kLPSPI_PcsActiveLow; + + cfg.pinCfg = kLPSPI_SdiInSdoOut; + cfg.dataOutConfig = kLpspiDataOutRetained; + + LPSPI_MasterInit(base, &cfg, SPI_CLOCK_FREQ); +} + +void SpiSlaveInit(LPSPI_Type *base) +{ + lpspi_slave_config_t cfg; + + /*Slave config*/ + cfg.bitsPerFrame = 8; + cfg.cpol = kLPSPI_ClockPolarityActiveHigh; + cfg.cpha = kLPSPI_ClockPhaseFirstEdge; + cfg.direction = kLPSPI_MsbFirst; + + cfg.whichPcs = SPI_PCS_FOR_INIT; + cfg.pcsActiveHighOrLow = kLPSPI_PcsActiveLow; + + cfg.pinCfg = kLPSPI_SdiInSdoOut; + cfg.dataOutConfig = kLpspiDataOutRetained; + + LPSPI_SlaveInit(base, &cfg); +} + +int SpiHwParamInit(struct Stm32HwSpi *spi_param) +{ + LPSPI_Type *spi_base = spi_param->base; + uint32_t whichPcs = kLPSPI_Pcs0; + uint8_t fifo_size, tx_water, rx_water; + + /*The TX and RX FIFO sizes are always the same*/ + fifo_size = LPSPI_GetRxFifoSize(spi_base); + + /*Set the RX and TX watermarks to reduce the ISR times.*/ + if (fifo_size > 1) + { + tx_water = 1; + rx_water = fifo_size - 2; + } + else + { + tx_water = 0; + rx_water = 0; + } + + LPSPI_SetFifoWatermarks(spi_base, tx_water, rx_water); + + LPSPI_Enable(spi_base, false); + spi_base->CFGR1 &= (~LPSPI_CFGR1_NOSTALL_MASK); + LPSPI_Enable(spi_base, true); + + /*Flush FIFO , clear status , disable all the inerrupts.*/ + LPSPI_FlushFifo(spi_base, true, true); + LPSPI_ClearStatusFlags(spi_base, kLPSPI_AllStatusFlag); + LPSPI_DisableInterrupts(spi_base, kLPSPI_AllInterruptEnable); + + spi_base->TCR = + (spi_base->TCR & + ~(LPSPI_TCR_CONT_MASK | LPSPI_TCR_CONTC_MASK | LPSPI_TCR_RXMSK_MASK | LPSPI_TCR_PCS_MASK)) | + LPSPI_TCR_CONT(0) | LPSPI_TCR_CONTC(0) | LPSPI_TCR_RXMSK(0) | LPSPI_TCR_TXMSK(0) | LPSPI_TCR_PCS(whichPcs); + + /* Enable the NVIC for LPSPI peripheral. Note that below code is useless if the LPSPI interrupt is in INTMUX , + * and you should also enable the INTMUX interupt in your application. + */ + EnableIRQ(spi_param->irq); + LPSPI_EnableInterrupts(spi_base, kLPSPI_RxInterruptEnable); +} + +int SpiReadData(struct Stm32HwSpi *spi_param, uint8_t *buf, int len) +{ + int fifo_size; + int timeout = 50; // wait for read SPI data + LPSPI_Type *spi_base = spi_param->base; + + BOARD_InitSPIPins(); + + /*Set clock source for LPSPI*/ + CLOCK_SetMux(kCLOCK_LpspiMux, SPI_CLOCK_SOURCE_SELECT); + CLOCK_SetDiv(kCLOCK_LpspiDiv, SPI_CLOCK_SOURCE_DIVIDER); + + uint32_t errorCount; + uint32_t i; + uint32_t whichPcs; + uint8_t txWatermark; + + BOARD_InitSPIPins(); + + /*Set clock source for LPSPI*/ + CLOCK_SetMux(kCLOCK_LpspiMux, SPI_CLOCK_SOURCE_SELECT); + CLOCK_SetDiv(kCLOCK_LpspiDiv, SPI_CLOCK_SOURCE_DIVIDER); + + /*Set up the transfer data*/ + for (i = 0; i < TRANSFER_SIZE; i++) + { + spi1_rx_data.buf[i] = 0; + } + + SpiSlaveInit(spi_base); + + /******************Set up slave first ******************/ + spi1_rx_data.completed = false; + spi1_rx_data.cnt = 0; + spi1_rx_data.size = len; + whichPcs = SPI_PCS_FOR_INIT; + + /*The TX and RX FIFO sizes are always the same*/ + spi1_rx_data.fifo = LPSPI_GetRxFifoSize(spi_base); + + /*Set the RX and TX watermarks to reduce the ISR times.*/ + if (spi1_rx_data.fifo > 1) + { + txWatermark = 1; + spi1_rx_data.water = spi1_rx_data.fifo - 2; + } + else + { + txWatermark = 0; + spi1_rx_data.water = 0; + } + + LPSPI_SetFifoWatermarks(spi_base, txWatermark, spi1_rx_data.water); + + LPSPI_Enable(spi_base, false); + spi_base->CFGR1 &= (~LPSPI_CFGR1_NOSTALL_MASK); + LPSPI_Enable(spi_base, true); + + /*Flush FIFO , clear status , disable all the interrupts.*/ + LPSPI_FlushFifo(spi_base, true, true); + LPSPI_ClearStatusFlags(spi_base, kLPSPI_AllStatusFlag); + LPSPI_DisableInterrupts(spi_base, kLPSPI_AllInterruptEnable); + + spi_base->TCR = + (spi_base->TCR & + ~(LPSPI_TCR_CONT_MASK | LPSPI_TCR_CONTC_MASK | LPSPI_TCR_RXMSK_MASK | LPSPI_TCR_PCS_MASK)) | + LPSPI_TCR_CONT(0) | LPSPI_TCR_CONTC(0) | LPSPI_TCR_RXMSK(0) | LPSPI_TCR_TXMSK(0) | LPSPI_TCR_PCS(whichPcs); + + /* Enable the NVIC for LPSPI peripheral. Note that below code is useless if the LPSPI interrupt is in INTMUX , + * and you should also enable the INTMUX interrupt in your application. + */ + EnableIRQ(spi_param->irq); + LPSPI_EnableInterrupts(spi_base, kLPSPI_RxInterruptEnable); + + /******************Wait for slave transfer completed.******************/ + while((spi1_rx_data.cnt < (len - 1)) && (timeout--)) + { + MdelayKTask(100); + } + + if(buf && (len <= TRANSFER_SIZE)) + { + memcpy(buf, spi1_rx_data.buf, len); + } + + LPSPI_Deinit(spi_base); +} + +void SpiWriteData(struct Stm32HwSpi *spi_param, const uint8_t *buf, uint16_t len) +{ + uint32_t errorCount; + uint32_t i; + uint32_t whichPcs; + uint8_t txWatermark; + LPSPI_Type *spi_base = spi_param->base; + int timeout = 1000; // wait for write SPI data + + BOARD_InitSPIPins(); + + /*Set clock source for LPSPI*/ + CLOCK_SetMux(kCLOCK_LpspiMux, SPI_CLOCK_SOURCE_SELECT); + CLOCK_SetDiv(kCLOCK_LpspiDiv, SPI_CLOCK_SOURCE_DIVIDER); + /*Set up the transfer data*/ + memcpy(spi1_tx_data.buf, buf, len); + + SpiMasterInit(spi_base); + + spi1_rx_data.size = len; + spi1_tx_data.size = len; + spi1_tx_data.completed = false; + spi1_tx_data.cnt = 0; + spi1_rx_data.cnt = 0; + whichPcs = SPI_PCS_FOR_INIT; + + /*The TX and RX FIFO sizes are always the same*/ + spi1_tx_data.fifo = LPSPI_GetRxFifoSize(spi_base); + + /*Set the RX and TX watermarks to reduce the ISR times.*/ + if (spi1_tx_data.fifo > 1) + { + txWatermark = 1; + spi1_rx_data.water = spi1_tx_data.fifo - 2; + } + else + { + txWatermark = 0; + spi1_rx_data.water = 0; + } + + LPSPI_SetFifoWatermarks(spi_base, txWatermark, spi1_rx_data.water); + + LPSPI_Enable(spi_base, false); + spi_base->CFGR1 &= (~LPSPI_CFGR1_NOSTALL_MASK); + LPSPI_Enable(spi_base, true); + + /*Flush FIFO , clear status , disable all the inerrupts.*/ + LPSPI_FlushFifo(spi_base, true, true); + LPSPI_ClearStatusFlags(spi_base, kLPSPI_AllStatusFlag); + LPSPI_DisableInterrupts(spi_base, kLPSPI_AllInterruptEnable); + + spi_base->TCR = + (spi_base->TCR & + ~(LPSPI_TCR_CONT_MASK | LPSPI_TCR_CONTC_MASK | LPSPI_TCR_RXMSK_MASK | LPSPI_TCR_PCS_MASK)) | + LPSPI_TCR_CONT(0) | LPSPI_TCR_CONTC(0) | LPSPI_TCR_RXMSK(0) | LPSPI_TCR_TXMSK(0) | LPSPI_TCR_PCS(whichPcs); + + /* Enable the NVIC for LPSPI peripheral. Note that below code is useless if the LPSPI interrupt is in INTMUX , + * and you should also enable the INTMUX interupt in your application. + */ + EnableIRQ(spi_param->irq); + LPSPI_EnableInterrupts(spi_base, kLPSPI_AllInterruptEnable); + + while((spi1_tx_data.cnt < (spi1_tx_data.size - 1)) && (timeout--)) + { + MdelayKTask(10); + } + + spi_print("SPI: master rx %d tx %d size %d completed s %d m %d!\r\n", spi1_rx_data.cnt, + spi1_tx_data.cnt, spi1_tx_data.size, spi1_rx_data.completed, spi1_tx_data.completed); + + LPSPI_Deinit(spi_base); +} + +static uint32 Stm32SpiWriteData(struct SpiHardwareDevice *spi_dev, struct SpiDataStandard *spi_datacfg) +{ + int state; + x_size_t message_length, already_send_length; + uint16 send_length; + const uint8 *write_buf; + + NULL_PARAM_CHECK(spi_dev); + NULL_PARAM_CHECK(spi_datacfg); + + struct Stm32Spi *StmSpi = CONTAINER_OF(spi_dev->haldev.owner_bus, struct Stm32Spi, spi_bus); + struct Stm32HwSpi *StmCfg = (struct Stm32HwSpi *) spi_dev->haldev.private_data; + + while(NONE != spi_datacfg) { + + message_length = spi_datacfg->length; + write_buf = spi_datacfg->tx_buff; + while (message_length) { + if (message_length > 65535){ + send_length = 65535; + message_length = message_length - 65535; + } else { + send_length = message_length; + message_length = 0; + } + + /* calculate the start address */ + already_send_length = spi_datacfg->length - send_length - message_length; + write_buf = (uint8 *)spi_datacfg->tx_buff + already_send_length; + + if (spi_datacfg->tx_buff) { + SpiWriteData(StmCfg, spi_datacfg->tx_buff, send_length); + } + + if (state != 0) { + KPrintf("spi write error : %d\n", state); + spi_datacfg->length = 0; + } + } + + spi_datacfg = spi_datacfg->next; + } + + return EOK; +} + +static uint32 Stm32SpiReadData(struct SpiHardwareDevice *spi_dev, struct SpiDataStandard *spi_datacfg) +{ + int state; + x_size_t message_length, already_send_length; + uint16 read_length, spi_read_length = 0; + uint8 *read_buf; + + NULL_PARAM_CHECK(spi_dev); + NULL_PARAM_CHECK(spi_datacfg); + + struct Stm32Spi *StmSpi = CONTAINER_OF(spi_dev->haldev.owner_bus, struct Stm32Spi, spi_bus); + struct Stm32HwSpi *StmCfg = (struct Stm32HwSpi *) spi_dev->haldev.private_data; + + while (NONE != spi_datacfg) { + message_length = spi_datacfg->length; + read_buf = spi_datacfg->rx_buff; + while (message_length) { + if (message_length > 65535) { + read_length = 65535; + message_length = message_length - 65535; + } else { + read_length = message_length; + message_length = 0; + } + + /* calculate the start address */ + already_send_length = spi_datacfg->length - read_length - message_length; + read_buf = (uint8 *)spi_datacfg->rx_buff + already_send_length; + + if (spi_datacfg->rx_buff) { + memset(read_buf, 0xff, read_length); + SpiReadData(StmCfg, read_buf, read_length); + } + + if (state != 0) { + KPrintf("spi read error : %d\n", state); + spi_datacfg->length = 0; + } + } + + spi_read_length += spi_datacfg->length; + spi_datacfg = spi_datacfg->next; + } + + return spi_read_length; +} + +static const struct SpiDevDone spi_dev_done = +{ + .dev_open = NONE, + .dev_close = NONE, + .dev_write = Stm32SpiWriteData, + .dev_read = Stm32SpiReadData, +}; + +static x_err_t Stm32SpiInit(struct Stm32Spi *spi_drv, struct SpiMasterParam *cfg) +{ + NULL_PARAM_CHECK(spi_drv); + NULL_PARAM_CHECK(cfg); +} + +static uint32 SpiDrvInit(struct SpiDriver *spi_drv) +{ + NULL_PARAM_CHECK(spi_drv); + + SpiDeviceParam *dev_param = (SpiDeviceParam *)(spi_drv->driver.private_data); + + struct Stm32Spi *StmSpi = CONTAINER_OF(spi_drv->driver.owner_bus, struct Stm32Spi, spi_bus); + + return Stm32SpiInit(StmSpi, dev_param->spi_master_param); +} + +static uint32 SpiDrvConfigure(struct SpiDriver *spi_drv, struct SpiMasterParam *spi_param) +{ + NULL_PARAM_CHECK(spi_drv); + NULL_PARAM_CHECK(spi_param); + + SpiDeviceParam *dev_param = (SpiDeviceParam *)(spi_drv->driver.private_data); + + dev_param->spi_master_param = spi_param; + dev_param->spi_master_param->spi_work_mode = dev_param->spi_master_param->spi_work_mode & SPI_MODE_MASK; + + return EOK; +} + +/*Configure the spi device param, make sure struct (configure_info->private_data) = (SpiMasterParam)*/ +static uint32 Stm32SpiDrvConfigure(void *drv, struct BusConfigureInfo *configure_info) +{ + NULL_PARAM_CHECK(drv); + NULL_PARAM_CHECK(configure_info); + + x_err_t ret = EOK; + struct SpiDriver *spi_drv = (struct SpiDriver *)drv; + struct SpiMasterParam *spi_param; + + switch (configure_info->configure_cmd) + { + case OPE_INT: + ret = SpiDrvInit(spi_drv); + break; + case OPE_CFG: + spi_param = (struct SpiMasterParam *)configure_info->private_data; + ret = SpiDrvConfigure(spi_drv, spi_param); + break; + default: + break; + } + + return ret; +} + +static int BoardSpiBusInit(struct Stm32Spi *stm32spi_bus, struct SpiDriver *spi_driver, char* drv_name) +{ + x_err_t ret = EOK; + + /*Init the spi bus */ + ret = SpiBusInit(&stm32spi_bus->spi_bus, stm32spi_bus->bus_name); + if (EOK != ret) { + KPrintf("Board_Spi_init SpiBusInit error %d\n", ret); + return ERROR; + } + + /*Init the spi driver*/ + ret = SpiDriverInit(spi_driver, drv_name); + if (EOK != ret) { + KPrintf("Board_Spi_init SpiDriverInit error %d\n", ret); + return ERROR; + } + + /*Attach the spi driver to the spi bus*/ + ret = SpiDriverAttachToBus(drv_name, stm32spi_bus->bus_name); + if (EOK != ret) { + KPrintf("Board_Spi_init SpiDriverAttachToBus error %d\n", ret); + return ERROR; + } + + return ret; +} + +static int Stm32HwSpiBusInit(void) +{ + x_err_t ret = EOK; + struct Stm32Spi *StmSpiBus; + +#ifdef BSP_USING_SPI1 + StmSpiBus = &spi1; + StmSpiBus->instance = LPSPI1; + StmSpiBus->bus_name = SPI_1_BUS_NAME; + StmSpiBus->spi_bus.private_data = &spi1; + + static struct SpiDriver spi_driver_1; + memset(&spi_driver_1, 0, sizeof(struct SpiDriver)); + + spi_driver_1.configure = &(Stm32SpiDrvConfigure); + + ret = BoardSpiBusInit(StmSpiBus, &spi_driver_1, SPI_1_DRV_NAME); + if (EOK != ret) { + KPrintf("Board_Spi_Init spi_bus_init %s error ret %u\n", StmSpiBus->bus_name, ret); + return ERROR; + } + + static struct SpiHardwareDevice spi1_dev; + static struct Stm32HwSpi spi1_cfg; + + spi1_cfg.base = StmSpiBus->instance; + spi1_cfg.irq = LPSPI1_IRQn; + spi1_dev.spi_dev_done = &spi_dev_done; + + ret = SpiDeviceRegister(&spi1_dev, (void *)&spi1_cfg, SPI_1_DEV_NAME_0); + if (ret != EOK) { + KPrintf("ADC1 device register error %d\n", ret); + return ERROR; + } + + ret = SpiDeviceAttachToBus(SPI_1_DEV_NAME_0, SPI_1_BUS_NAME); + if (ret != EOK) { + KPrintf("ADC1 device register error %d\n", ret); + return ERROR; + } +#endif + +#ifdef BSP_USING_SPI2 + StmSpiBus = &spi2; + StmSpiBus->instance = LPSPI2; + StmSpiBus->bus_name = SPI_2_BUS_NAME; + StmSpiBus->spi_bus.private_data = &spi2; + + static struct SpiDriver spi_driver_2; + memset(&spi_driver_2, 0, sizeof(struct SpiDriver)); + + spi_driver_2.configure = &(Stm32SpiDrvConfigure); + + ret = BoardSpiBusInit(StmSpiBus, &spi_driver_2, SPI_2_DRV_NAME); + if (EOK != ret) { + KPrintf("Board_Spi_Init spi_bus_init %s error ret %u\n", StmSpiBus->bus_name, ret); + return ERROR; + } + + static struct SpiHardwareDevice spi2_dev; + static struct Stm32HwSpi spi2_cfg; + + spi2_cfg.base = StmSpiBus->instance; + spi2_cfg.irq = LPSPI2_IRQn; + spi2_dev.spi_dev_done = &spi_dev_done; + + ret = SpiDeviceRegister(&spi2_dev, (void *)&spi2_cfg, SPI_2_DEV_NAME_0); + if (ret != EOK) { + KPrintf("ADC1 device register error %d\n", ret); + return ERROR; + } + + ret = SpiDeviceAttachToBus(SPI_2_DEV_NAME_0, SPI_2_BUS_NAME); + if (ret != EOK) { + KPrintf("ADC1 device register error %d\n", ret); + return ERROR; + } +#endif + +#ifdef BSP_USING_SPI3 + StmSpiBus = &spi3; + StmSpiBus->instance = LPSPI3; + StmSpiBus->bus_name = SPI_3_BUS_NAME; + StmSpiBus->spi_bus.private_data = &spi3; + + static struct SpiDriver spi_driver_3; + memset(&spi_driver_3, 0, sizeof(struct SpiDriver)); + + spi_driver_3.configure = &(Stm32SpiDrvConfigure); + + ret = BoardSpiBusInit(StmSpiBus, &spi_driver_3, SPI_3_DRV_NAME); + if (EOK != ret) { + KPrintf("Board_Spi_Init spi_bus_init %s error ret %u\n", StmSpiBus->bus_name, ret); + return ERROR; + } + + static struct SpiHardwareDevice spi3_dev; + static struct Stm32HwSpi spi3_cfg; + + spi3_cfg.base = StmSpiBus->instance; + spi3_cfg.irq = LPSPI3_IRQn; + spi3_dev.spi_dev_done = &spi_dev_done; + + ret = SpiDeviceRegister(&spi3_dev, (void *)&spi3_cfg, SPI_3_DEV_NAME_0); + if (ret != EOK) { + KPrintf("ADC1 device register error %d\n", ret); + return ERROR; + } + + ret = SpiDeviceAttachToBus(SPI_3_DEV_NAME_0, SPI_3_BUS_NAME); + if (ret != EOK) { + KPrintf("ADC1 device register error %d\n", ret); + return ERROR; + } +#endif + + return EOK; +} + +x_err_t HwSpiDeviceAttach(const char *bus_name, const char *device_name) +{ + NULL_PARAM_CHECK(bus_name); + NULL_PARAM_CHECK(device_name); + + x_err_t result; + struct SpiHardwareDevice *spi_device; + static SpiDeviceParam spi_dev_param; + memset(&spi_dev_param, 0, sizeof(SpiDeviceParam)); + + /* attach the device to spi bus*/ + spi_device = (struct SpiHardwareDevice *)x_malloc(sizeof(struct SpiHardwareDevice)); + CHECK(spi_device); + memset(spi_device, 0, sizeof(struct SpiHardwareDevice)); + + spi_device->spi_dev_done = &spi_dev_done; + + result = SpiDeviceRegister(spi_device, (void *)&spi_dev_param, device_name); + if (result != EOK) { + SYS_ERR("%s device %p register faild, %d\n", device_name, spi_device, result); + } + + result = SpiDeviceAttachToBus(device_name, bus_name); + if (result != EOK) { + SYS_ERR("%s attach to %s faild, %d\n", device_name, bus_name, result); + } + + CHECK(result == EOK); + + return result; +} + +int Imxrt1052HwSpiInit(void) +{ + return Stm32HwSpiBusInit(); +} + +void SpiReadTest(void *arg) +{ + uint32_t i; + uint8_t test_buf[32] = {0}; + struct Stm32HwSpi spi_param; + spi_param.base = LPSPI1; + spi_param.irq = LPSPI1_IRQn; + + SpiReadData(&spi_param, test_buf, 32); + + for(i = 0; i < sizeof(test_buf) ;i ++) + { + spi_print("%d - %x\n", i, test_buf[i]); + } +} + +SHELL_EXPORT_CMD (SHELL_CMD_PERMISSION(0) | SHELL_CMD_TYPE(SHELL_TYPE_CMD_MAIN) | SHELL_CMD_PARAM_NUM(0), + spiread, SpiReadTest, SPI Read); + +void SpiWriteTest(void *arg) +{ + uint32_t i; + uint8_t test_buf[100] = {0}; + struct Stm32HwSpi spi_param; + spi_param.base = LPSPI1; + spi_param.irq = LPSPI1_IRQn; + + for(i = 0; i < sizeof(test_buf) ;i ++) + { + test_buf[i] = i; + } + + SpiWriteData(&spi_param, test_buf, 100); +} + +SHELL_EXPORT_CMD (SHELL_CMD_PERMISSION(0) | SHELL_CMD_TYPE(SHELL_TYPE_CMD_MAIN) | SHELL_CMD_PARAM_NUM(0), + spiwrite, SpiWriteTest, SPI Write ); + diff --git a/Ubiquitous/XiZi/board/ok1052-c/third_party_driver/uart/Kconfig b/Ubiquitous/XiZi/board/ok1052-c/third_party_driver/uart/Kconfig new file mode 100644 index 0000000..93c86b3 --- /dev/null +++ b/Ubiquitous/XiZi/board/ok1052-c/third_party_driver/uart/Kconfig @@ -0,0 +1,29 @@ +config BSP_USING_LPUART1 +bool "Enable LPUART1" +default y +if BSP_USING_LPUART1 + config SERIAL_BUS_NAME_1 + string "serial bus 1 name" + default "uart1" + config SERIAL_DRV_NAME_1 + string "serial bus 1 driver name" + default "uart1_drv" + config SERIAL_1_DEVICE_NAME_0 + string "serial bus 1 device name" + default "uart1_dev1" +endif + +config BSP_USING_LPUART2 +bool "Enable LPUART2" +default y +if BSP_USING_LPUART2 + config SERIAL_BUS_NAME_2 + string "serial bus 2 name" + default "uart2" + config SERIAL_DRV_NAME_2 + string "serial bus 2 driver name" + default "uart2_drv" + config SERIAL_2_DEVICE_NAME_0 + string "serial bus 2 device name" + default "uart2_dev2" +endif diff --git a/Ubiquitous/XiZi/board/ok1052-c/third_party_driver/uart/Makefile b/Ubiquitous/XiZi/board/ok1052-c/third_party_driver/uart/Makefile new file mode 100644 index 0000000..1631643 --- /dev/null +++ b/Ubiquitous/XiZi/board/ok1052-c/third_party_driver/uart/Makefile @@ -0,0 +1,3 @@ +SRC_FILES := connect_uart.c fsl_lpuart.c + +include $(KERNEL_ROOT)/compiler.mk diff --git a/Ubiquitous/XiZi/board/ok1052-c/third_party_driver/usb/Kconfig b/Ubiquitous/XiZi/board/ok1052-c/third_party_driver/usb/Kconfig new file mode 100644 index 0000000..a1f439c --- /dev/null +++ b/Ubiquitous/XiZi/board/ok1052-c/third_party_driver/usb/Kconfig @@ -0,0 +1,15 @@ +config BSP_USING_NXP_USBH + bool "Using usb host by NXP library" + default n + if BSP_USING_NXP_USBH + config USB_BUS_NAME + string "usb bus name" + default "usb" + config USB_DRIVER_NAME + string "usb bus driver name" + default "usb_drv" + config USB_DEVICE_NAME + string "usb bus device name" + default "usb_dev" + endif + diff --git a/Ubiquitous/XiZi/board/ok1052-c/third_party_driver/usb/Makefile b/Ubiquitous/XiZi/board/ok1052-c/third_party_driver/usb/Makefile new file mode 100644 index 0000000..01f068d --- /dev/null +++ b/Ubiquitous/XiZi/board/ok1052-c/third_party_driver/usb/Makefile @@ -0,0 +1,5 @@ +SRC_DIR := nxp_usb_driver + +SRC_FILES := connect_usb.c + +include $(KERNEL_ROOT)/compiler.mk diff --git a/Ubiquitous/XiZi/board/ok1052-c/third_party_driver/usb/connect_usb.c b/Ubiquitous/XiZi/board/ok1052-c/third_party_driver/usb/connect_usb.c new file mode 100644 index 0000000..28d4320 --- /dev/null +++ b/Ubiquitous/XiZi/board/ok1052-c/third_party_driver/usb/connect_usb.c @@ -0,0 +1,296 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +/** +* @file connect_usb.c +* @brief support usb host function using bus driver framework on OK1052 board +* @version 2.0 +* @author AIIT XUOS Lab +* @date 2022-02-09 +*/ + +/************************************************* +File name: connect_usb.c +Description: support ok1052-c board usb host configure and sdio bus register function +Others: take SDK_2.6.1_MIMXRT1052xxxxB/boards/evkbimxrt1050/usb_examples/usb_host_msd_command for references +History: +1. Date: 2022-02-09 +Author: AIIT XUOS Lab +Modification: +1. support ok1052-c board usb host configure, write and read +2. support ok1052-c board usb host bus device and driver register +*************************************************/ +#include +#include + +#define BSP_USING_NXP_USBH +#ifdef BSP_USING_NXP_USBH + +/*! @brief USB host msd command instance global variable */ +extern usb_host_msd_command_instance_t g_MsdCommandInstance; +usb_host_handle g_HostHandle; + +extern usb_status_t USB_HostMsdReadApi(usb_host_msd_command_instance_t *msdCommandInstance, uint8_t *buffer, uint32_t pos, uint32_t block_size, uint32_t block_num); +extern usb_status_t USB_HostMsdWriteApi(usb_host_msd_command_instance_t *msdCommandInstance, const uint8_t *buffer, uint32_t pos, uint32_t block_size, uint32_t block_num); + +//USB HOST ISR +void UsbOtg2IrqHandler(int irqn, void *arg) +{ + x_base lock = 0; + lock = DISABLE_INTERRUPT(); + + USB_HostEhciIsrFunction(g_HostHandle); + + ENABLE_INTERRUPT(lock); +} +DECLARE_HW_IRQ(USB2_IRQn, UsbOtg2IrqHandler, NONE); + +void UsbHostClockInit(void) +{ + usb_phy_config_struct_t phyConfig = { + BOARD_USB_PHY_D_CAL, + BOARD_USB_PHY_TXCAL45DP, + BOARD_USB_PHY_TXCAL45DM, + }; + + if (CONTROLLER_ID == kUSB_ControllerEhci0) { + CLOCK_EnableUsbhs0PhyPllClock(kCLOCK_Usbphy480M, 480000000U); + CLOCK_EnableUsbhs0Clock(kCLOCK_Usb480M, 480000000U); + } else { + CLOCK_EnableUsbhs1PhyPllClock(kCLOCK_Usbphy480M, 480000000U); + CLOCK_EnableUsbhs1Clock(kCLOCK_Usb480M, 480000000U); + } + USB_EhciPhyInit(CONTROLLER_ID, BOARD_XTAL0_CLK_HZ, &phyConfig); +} + +void UsbHostIsrEnable(void) +{ + uint8_t irqNumber; + + uint8_t usbHOSTEhciIrq[] = USBHS_IRQS; + irqNumber = usbHOSTEhciIrq[CONTROLLER_ID - kUSB_ControllerEhci0]; +/* USB_HOST_CONFIG_EHCI */ + +/* Install isr, set priority, and enable IRQ. */ + NVIC_SetPriority((IRQn_Type)irqNumber, USB_HOST_INTERRUPT_PRIORITY); + EnableIRQ((IRQn_Type)irqNumber); +} + +void UsbHostTaskFn(void *param) +{ + USB_HostEhciTaskFunction(param); +} + +/*! + * @brief USB isr function. + */ +static usb_status_t UsbHostEvent(usb_device_handle deviceHandle, + usb_host_configuration_handle configurationHandle, + uint32_t eventCode) +{ + usb_status_t status = kStatus_USB_Success; + switch (eventCode) + { + case kUSB_HostEventAttach: + KPrintf("usb device attached\n"); + status = USB_HostMsdEvent(deviceHandle, configurationHandle, eventCode); + break; + + case kUSB_HostEventNotSupported: + KPrintf("device not supported.\r\n"); + break; + + case kUSB_HostEventEnumerationDone: + status = USB_HostMsdEvent(deviceHandle, configurationHandle, eventCode); + break; + + case kUSB_HostEventDetach: + KPrintf("usb device detached\n"); + status = USB_HostMsdEvent(deviceHandle, configurationHandle, eventCode); + break; + + default: + break; + } + return status; +} + +static void UsbHostApplicationInit(void) +{ + usb_status_t status = kStatus_USB_Success; + + UsbHostClockInit(); + + status = USB_HostInit(CONTROLLER_ID, &g_HostHandle, UsbHostEvent); + if (status != kStatus_USB_Success) { + KPrintf("host init error\r\n"); + return; + } + UsbHostIsrEnable(); + + KPrintf("host init done\r\n"); +} + +#if defined(FS_VFS) +void UsbMountFileSystem() +{ + if (MountFilesystem(USB_BUS_NAME, USB_DEVICE_NAME, USB_DRIVER_NAME, FSTYPE_FATFS, UDISK_MOUNTPOINT) == 0) + KPrintf("Mount FAT on Udisk successful.\n"); + else + KPrintf("Mount FAT on Udisk failed.\n"); +} + +void UsbUnmountFileSystem() +{ + UnmountFileSystem(UDISK_MOUNTPOINT); +} +#endif + +static uint32 UsbHostOpen(void *dev) +{ + return EOK; +} + +static uint32 UsbHostClose(void *dev) +{ + return EOK; +} + +static uint32 UsbHostRead(void *dev, struct BusBlockReadParam *read_param) +{ + usb_status_t status; + + status = USB_HostMsdReadApi(&g_MsdCommandInstance, (uint8 *)read_param->buffer, read_param->pos, USB_SINGLE_BLOCK_SIZE, read_param->size); + if (kStatus_USB_Success == status) { + return read_param->size; + } + + return 0; +} + +static uint32 UsbHostWrite(void *dev, struct BusBlockWriteParam *write_param) +{ + usb_status_t status; + + status = USB_HostMsdWriteApi(&g_MsdCommandInstance, (const uint8 *)write_param->buffer, write_param->pos, USB_SINGLE_BLOCK_SIZE, write_param->size); + if (kStatus_USB_Success == status) { + return write_param->size; + } + + return 0; +} + +/*manage the usb device operations*/ +static const struct UsbDevDone dev_done = +{ + .open = UsbHostOpen, + .close = UsbHostClose, + .write = UsbHostWrite, + .read = UsbHostRead, +}; + +static void UsbHostTask(void* parameter) +{ + while (1) { + UsbHostTaskFn(g_HostHandle); + USB_HostMsdTask(&g_MsdCommandInstance); + } +} + +/*Init usb host bus driver*/ +static int BoardUsbBusInit(struct UsbBus *usb_bus, struct UsbDriver *usb_driver) +{ + x_err_t ret = EOK; + + /*Init the usb bus */ + ret = UsbBusInit(usb_bus, USB_BUS_NAME); + if (EOK != ret) { + KPrintf("board_usb_init UsbBusInit error %d\n", ret); + return ERROR; + } + + /*Init the usb driver*/ + ret = UsbDriverInit(usb_driver, USB_DRIVER_NAME); + if (EOK != ret){ + KPrintf("board_usb_init UsbDriverInit error %d\n", ret); + return ERROR; + } + + /*Attach the usb driver to the usb bus*/ + ret = UsbDriverAttachToBus(USB_DRIVER_NAME, USB_BUS_NAME); + if (EOK != ret) { + KPrintf("board_usb_init USEDriverAttachToBus error %d\n", ret); + return ERROR; + } + + return ret; +} + +/*Attach the usb device to the usb bus*/ +static int BoardUsbDevBend(void) +{ + x_err_t ret = EOK; + static struct UsbHardwareDevice usb_device; + memset(&usb_device, 0, sizeof(struct UsbHardwareDevice)); + + usb_device.dev_done = &dev_done; + + ret = USBDeviceRegister(&usb_device, NONE, USB_DEVICE_NAME); + if (EOK != ret) { + KPrintf("USBDeviceRegister device %s error %d\n", USB_DEVICE_NAME, ret); + return ERROR; + } + + ret = USBDeviceAttachToBus(USB_DEVICE_NAME, USB_BUS_NAME); + if (EOK != ret) { + KPrintf("USBDeviceAttachToBus device %s error %d\n", USB_DEVICE_NAME, ret); + return ERROR; + } + + return ret; +} + +/*OK1052-C BOARD USB INIT*/ +int Imxrt1052HwUsbHostInit(void) +{ + x_err_t ret = EOK; + int32 usb_host_task = 0; + + static struct UsbBus usb_bus; + memset(&usb_bus, 0, sizeof(struct UsbBus)); + + static struct UsbDriver usb_driver; + memset(&usb_driver, 0, sizeof(struct UsbDriver)); + + UsbHostApplicationInit(); + + ret = BoardUsbBusInit(&usb_bus, &usb_driver); + if (EOK != ret) { + KPrintf("BoardUsbBusInit error ret %u\n", ret); + return ERROR; + } + + ret = BoardUsbDevBend(); + if (EOK != ret) { + KPrintf("BoardUsbDevBend error ret %u\n", ret); + return ERROR; + } + + usb_host_task = KTaskCreate("usbh", UsbHostTask, NONE, + USB_HOST_STACK_SIZE, 8); + if(usb_host_task < 0) { + KPrintf("usb_host_task create failed ...%s %d.\n", __FUNCTION__,__LINE__); + return ERROR; + } + + StartupKTask(usb_host_task); + + return ret; +} + +#endif diff --git a/Ubiquitous/XiZi/board/rv32m1_vega/Kconfig b/Ubiquitous/XiZi/board/rv32m1_vega/Kconfig new file mode 100755 index 0000000..8ed3d63 --- /dev/null +++ b/Ubiquitous/XiZi/board/rv32m1_vega/Kconfig @@ -0,0 +1,31 @@ +mainmenu "XiZi Project Configuration" + +config BSP_DIR + string + option env="BSP_ROOT" + default "." + +config KERNEL_DIR + string + option env="KERNEL_ROOT" + default "../.." + +config BOARD_RV32M1_VEGA + bool + select ARCH_RISCV + default y + +source "$KERNEL_DIR/arch/Kconfig" + +menu "rv32m1_vega feature" + source "$BSP_DIR/third_party_driver/Kconfig" +endmenu + + +menu "Hardware feature" + source "$KERNEL_DIR/resources/Kconfig" +endmenu + +source "$KERNEL_DIR/Kconfig" + + diff --git a/Ubiquitous/XiZi/board/rv32m1_vega/Makefile b/Ubiquitous/XiZi/board/rv32m1_vega/Makefile new file mode 100755 index 0000000..12f4148 --- /dev/null +++ b/Ubiquitous/XiZi/board/rv32m1_vega/Makefile @@ -0,0 +1,6 @@ +SRC_FILES := board.c + +SRC_DIR := third_party_driver + + +include $(KERNEL_ROOT)/compiler.mk diff --git a/Ubiquitous/XiZi/board/rv32m1_vega/README.md b/Ubiquitous/XiZi/board/rv32m1_vega/README.md new file mode 100755 index 0000000..7fdc0aa --- /dev/null +++ b/Ubiquitous/XiZi/board/rv32m1_vega/README.md @@ -0,0 +1,193 @@ +# 从零开始构建矽璓工业物联操作系统：使用risc-v架构的rv32m1_vega 开发板 + +[XiUOS](http://xuos.io/) (X Industrial Ubiquitous Operating System) 矽璓工业物联操作系统是一款面向工业物联场景的泛在操作系统，来自泛在操作系统研究计划。所谓泛在操作系统(UOS: Ubiquitous Operating Systems)，是支持互联网时代人机物融合泛在计算应用模式的新型操作系统，是传统操作系统概念的泛化与延伸。在泛在操作系统技术体系中，不同的泛在计算设备和泛在应用场景需要符合各自特性的不同UOS，XiUOS即是面向工业物联场景的一种UOS，主要由一个极简的微型实时操作系统(RTOS)内核和其上的智能工业物联框架构成，支持工业物联网(IIoT: Industrial Internet of Things)应用。 + + +## 开发环境搭建 + +### 推荐使用： + +**操作系统：** ubuntu18.04 [https://ubuntu.com/download/desktop](https://ubuntu.com/download/desktop) + +**开发工具推荐使用 VSCode ，VScode下载地址为：** VSCode [https://code.visualstudio.com/](https://code.visualstudio.com/)，推荐下载地址为 [http://vscode.cdn.azure.cn/stable/3c4e3df9e89829dce27b7b5c24508306b151f30d/code_1.55.2-1618307277_amd64.deb](http://vscode.cdn.azure.cn/stable/3c4e3df9e89829dce27b7b5c24508306b151f30d/code_1.55.2-1618307277_amd64.deb) + +### 依赖包安装： + +``` +$ sudo apt install build-essential pkg-config +$ sudo apt install gcc make libncurses5-dev openssl libssl-dev bison flex libelf-dev autoconf libtool gperf libc6-dev git +``` + +**源码下载：** XiUOS [https://www.gitlink.org.cn/xuos/xiuos](https://www.gitlink.org.cn/xuos/xiuos) + +新建一个空文件夹并进入文件夹中，并下载源码，具体命令如下： + +```c +mkdir test && cd test +git clone https://gitlink.org.cn/xuos/xiuos.git +``` + +1、打开XiUOS源码文件包可以看到以下目录： +| 名称 | 说明 | +| -- | -- | +| APP_Framework | 应用代码 | +| Ubiquitous | 板级支持包,支持NuttX、RT-Thread和XiZi内核 | + +2、打开XiZi内核源码文件包可以看到以下目录： +| 名称 | 说明 | +| -- | -- | +| arch | 架构代码 | +| board | 板级支持包 | +| fs | 文件系统 | +| kernel | 内核源码 | +| lib | 第三方库源码 | +| resources | 驱动文件 | +| tool | 系统工具 | + +使用VScode打开代码，具体操作步骤为：在源码文件夹下打开系统终端，输入`code .`即可打开VScode开发环境，如下图所示： + +![vscode](img/vscode.jpg) + +### 裁减配置工具的下载 + +裁减配置工具： + +**工具地址：** kconfig-frontends [https://www.gitlink.org.cn/xuos/kconfig-frontends](https://www.gitlink.org.cn/xuos/kconfig-frontends) + +```c +mkdir kfrontends && cd kfrontends +git clone https://gitlink.org.cn/xuos/kconfig-frontends.git +``` + +下载源码后按以下步骤执行软件安装： + +```c +cd kconfig-frontends +./xs_build.sh +``` + +### 编译工具链： + +RISC-V: riscv-none-embed-，默认安装到Ubuntu的/opt/，下载并解压。[下载网址 https://open-isa.org/downloads/] +![gnu](img/riscv_gnu.png) + + + +将上述解压的编译工具链的路径添加到board/rv32m1_vega/config.mk文件当中，例如： + +``` +export CROSS_COMPILE ?=/opt/gnu-mcu-eclipse/riscv-none-gcc/8.2.0-2.1-20190425-1021/bin/riscv-none-embed- +``` + +若已存在`export CROSS_COMPILE ?=xxxx` 应该将原有的语句注释，再写入上面的语句。 + +# 在rv32m1_vega board 上创建第一个应用 + +## 1.rv32m1_vega board 简介 + +| 硬件 | 描述 | +| -- | -- | +|芯片型号| RV32M1 | +|架构| RV32IMAC | +|主频| 48MHz | +|片内SRAM| 1.25 MB Flash 384 KB SRAM | +| 外设 | BLK FSK/GFSK | + +XiUOS板级当前支持使用UART。 + +## 2. 代码编写与编译说明 + +编辑环境：`VScode` + +编译工具链：`riscv-none-embed-gcc` + +使用`VScode`打开工程的方法有多种，本文介绍一种快捷键，在项目目录下将`code .`输入终端即可打开目标项目 + +修改`APP_Framework/Applications`文件夹下`main.c` + +在输出函数中写入 Hello, world! \n 完成代码编辑。 + + +编译步骤： + +1.在VScode终端下执行以下命令，生成配置文件 + +``` +cd ./Ubiquitous/XiZi +make BOARD=rm32v1_vega distclean +make BOARD=rm32v1_vega menuconfig +``` + +2.在menuconfig界面配置需要关闭和开启的功能，按回车键进入下级菜单，按Y键选中需要开启的功能，按N键选中需要关闭的功能，配置结束后选择Exit保存并退出 + +![menuconfig](img/menuconfig.png) + +3.继续执行以下命令，进行编译 + +``` +make BOARD=rv32m1_vega +``` + +4.如果编译正确无误，build文件夹下会产生XiZi_rv32m1_vega.elf、XiZi_rv32m1_vega.bin文件。 + +>注：最后可以执行以下命令，清除配置文件和编译生成的文件 + +``` +make BOARD=rv32m1_vega distclean +``` + +## 3. 烧写及调试执行 +rv32m1_vega开发板启动模式说明:参考文档[RV32M1_VEGA_Quick_Start_Guide.pdf](./doc/RV32M1_VEGA_Board_User_Guide.pdf) +![openocd](./img/multicore.jpg) + + +### 3.1 openocd gdb 调试方法 +请使用JLink接入到RV32M1_VEGA开发板的RISC-V核的JTAG接口上，同时把JLink在PC上的驱动更改为WinUSB模式。JTAG接口位于RV32M1芯片和天线座子旁边，小的20pin JTAG接口。 +参考文档：[RV32M1_VEGA_Quick_Start_Guide.pdf](./doc/RV32M1_VEGA_Quick_Start_Guide.pdf) + +rv32m1_vega支持openocd，可以通过openocd和gdb进行调试。 +调试需要下载openocd和sdk,下载配置方法参见以下文档： +https://github.com/open-isa-org/open-isa.org/blob/master/RV32M1_Vega_Develop_Environment_Setup.pdf + +openocd安装完成以后，按照如下步骤进行调试： + +1、进入xiuos目录路径下 +``` +cd ~/xiuos/Ubiquitous/XiZi +``` + +2、编译生成elf文件 + + +3、使用USB先和串口连接好开发板，进入openocd目录下，再在当前终端输入 +``` +cd /vega_rv32/sdk + +Openocd -f \boards\rv32m1_vega\vega_ri5cy.cfg +``` +在当前终端连接openocd，连接如下图所示： +![openocd](./img/openocd.png) + +4、打开一个新的终端，输入以下命令打开终端串口： +``` +sudo apt install screen +screen /dev/ttyUSB0 115200 +``` + +5、打开一个新的终端，进入编译生成的elf路径,输入例如： +``` +riscv-none-embed-gdb build/XiZi_rv32m1_vega.elf -ex "target remote localhost:3333" +``` +结果如下图所示： +![gdb](./img/gdb_load.png) + +6、再输入load，最后输入continue命令即可在串口终端看到系统运行界面，如下图所示： +![terminal](./img/terminal.png) + + +### 3.2 板载的串口调试 +1、Windows 需要安装jlink驱动 +2、开发板需要修改固件为RISCV启动，具体参考： +https://www.cnblogs.com/whik/p/10952292.html + +https://open-isa.cn/community/topic/%E7%BB%87%E5%A5%B3%E6%98%9F%E5%BC%80%E5%8F%91%E6%9D%BF%E8%B0%83%E8%AF%95%E5%99%A8%E5%8D%87%E7%BA%A7%E4%B8%BAJlink%E5%9B%BA%E4%BB%B6/ \ No newline at end of file diff --git a/Ubiquitous/XiZi/board/rv32m1_vega/board.c b/Ubiquitous/XiZi/board/rv32m1_vega/board.c new file mode 100644 index 0000000..02a596c --- /dev/null +++ b/Ubiquitous/XiZi/board/rv32m1_vega/board.c @@ -0,0 +1,75 @@ + +/** +* @file board.c +* @brief support vega init configure and start-up +* @version 1.0 +* @author AIIT XUOS Lab +* @date 2022-02-16 +*/ + +#include +#include +#include + +#include "pin_mux.h" +#include "clock_config.h" + +#include +#include + +extern int InitHwUart(); +extern void entry(void); + +void Rv32m1VgeaStart(void) +{ + entry(); +} + +void LPIT0_IRQHandler(void) +{ + TickAndTaskTimesliceUpdate(); + + SystemClearSystickFlag(); +} + +int InitHwTick(void) +{ + CLOCK_SetIpSrc(kCLOCK_Lpit0, kCLOCK_IpSrcFircAsync); + + SystemSetupSystick (TICK_PER_SECOND, 0); + SystemClearSystickFlag(); + + return 0; +} + +const scg_lpfll_config_t g_appScgLpFllConfig_BOARD_BootClockRUN = { + .enableMode = kSCG_LpFllEnable, /* LPFLL clock disabled */ + .div1 = kSCG_AsyncClkDivBy1, /* Low Power FLL Clock Divider 1: Clock output is disabled */ + .div2 = kSCG_AsyncClkDisable, /* Low Power FLL Clock Divider 2: Clock output is disabled */ + .div3 = kSCG_AsyncClkDisable, /* Low Power FLL Clock Divider 3: Clock output is disabled */ + .range = kSCG_LpFllRange72M, /* LPFLL is trimmed to 72MHz */ + .trimConfig = NULL, +}; + +void InitBoardHardware(void) +{ + BOARD_InitPins(); + BOARD_BootClockRUN(); + /* Init LPFLL */ + CLOCK_InitLpFll(&g_appScgLpFllConfig_BOARD_BootClockRUN); + + INTMUX_Init(INTMUX0); + INTMUX_EnableInterrupt(INTMUX0, 0, PORTC_IRQn); + + InitHwUart(); + InitHwTick(); + + InitBoardMemory(MEMORY_START_ADDRESS, MEMORY_END_ADDRESS); + + InstallConsole("uart0", "uart0_drv", "uart0_dev0"); + KPrintf("console init completed.\n"); + + KPrintf("memory address range: [0x%08x - 0x%08x], size: %d\n", (x_ubase) MEMORY_START_ADDRESS, (x_ubase) MEMORY_END_ADDRESS, RV32M1VEGA_SRAM_SIZE); + KPrintf("board init done.\n"); + KPrintf("start kernel...\n"); +} diff --git a/Ubiquitous/XiZi/board/rv32m1_vega/board.h b/Ubiquitous/XiZi/board/rv32m1_vega/board.h new file mode 100644 index 0000000..65a332b --- /dev/null +++ b/Ubiquitous/XiZi/board/rv32m1_vega/board.h @@ -0,0 +1,65 @@ +/* +* Copyright (c) 2020 AIIT XUOS Lab +* XiUOS is licensed under Mulan PSL v2. +* You can use this software according to the terms and conditions of the Mulan PSL v2. +* You may obtain a copy of Mulan PSL v2 at: +* http://license.coscl.org.cn/MulanPSL2 +* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, +* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, +* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. +* See the Mulan PSL v2 for more details. +*/ + +/** +* @file board.h +* @brief define rvstar-board init configure and start-up function +* @version 1.0 +* @author AIIT XUOS Lab +* @date 2021-09-02 +*/ + +/************************************************* +File name: board.h +Description: define vega-board init configure and start-up function +Others: +History: +1. Date: 2022-02-16 +Author: AIIT XUOS Lab +Modification: +1. define rvstar-board InitBoardHardware +2. define rvstar-board data and bss struct +*************************************************/ +#ifndef BOARD_H__ +#define BOARD_H__ + +#include +#include + +#ifndef __ASSEMBLY__ + +#undef EXTERN +#if defined(__cplusplus) +#define EXTERN extern "C" +extern "C" +{ +#else +#define EXTERN extern +#endif + +extern unsigned int __bss_start__; +extern unsigned int __bss_end__; +extern unsigned int _end; +extern unsigned int __stack_end__; + +#define MEMORY_START_ADDRESS (void*)(&_end) +#define RV32M1VEGA_SRAM_SIZE 0x00030000 - 0x1800 +#define MEMORY_END_ADDRESS (void*)(0x20000000 + RV32M1VEGA_SRAM_SIZE) + + +#undef EXTERN +#if defined(__cplusplus) +} +#endif +#endif + +#endif diff --git a/Ubiquitous/XiZi/board/rv32m1_vega/config.mk b/Ubiquitous/XiZi/board/rv32m1_vega/config.mk new file mode 100755 index 0000000..98582e4 --- /dev/null +++ b/Ubiquitous/XiZi/board/rv32m1_vega/config.mk @@ -0,0 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a/Ubiquitous/XiZi/board/rv32m1_vega/link.lds b/Ubiquitous/XiZi/board/rv32m1_vega/link.lds new file mode 100644 index 0000000..08b6b4b --- /dev/null +++ b/Ubiquitous/XiZi/board/rv32m1_vega/link.lds @@ -0,0 +1,142 @@ +/* Entry Point */ +OUTPUT_ARCH( "riscv" ) + +STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x1000; + +/* Specify the memory areas */ +MEMORY +{ + m_vector (RX) : ORIGIN = 0x000FFF00, LENGTH = 0x00000100 + m_text (RX) : ORIGIN = 0x00000000, LENGTH = 0x000FFF00 + m_data (RW) : ORIGIN = 0x20000000, LENGTH = 0x00030000 - 0x1800 +} + +/* Define output sections */ +SECTIONS +{ + .vectors : ALIGN(4) + { + __VECTOR_TABLE = .; + KEEP(*(.vectors)) + } > m_vector + + /* The program code and other data goes into internal flash */ + .text : + { + . = ALIGN(4); + KEEP(*(.startup)) + . = ALIGN(4); + __user_vector = .; + KEEP(*(user_vectors)) + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + *(.srodata .srodata.*) + *(.eh_frame) + *(.init) + *(.fini) + + /* section information for shell */ + . = ALIGN(4); + _shell_command_start = .; + KEEP (*(shellCommand)) + _shell_command_end = .; + . = ALIGN(4); + + __isrtbl_idx_start = .; + KEEP(*(.isrtbl.idx)) + __isrtbl_start = .; + KEEP(*(.isrtbl)) + __isrtbl_end = .; + . = ALIGN(4); + + PROVIDE(g_service_table_start = ABSOLUTE(.)); + KEEP(*(.g_service_table)) + PROVIDE(g_service_table_end = ABSOLUTE(.)); + . = ALIGN(4); + + } > m_text + + .preinit_array : + { + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + } > m_text + + .init_array : + { + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + } > m_text + + .fini_array : + { + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array*)) + PROVIDE_HIDDEN (__fini_array_end = .); + } > m_text + + __etext = .; /* define a global symbol at end of code */ + __global_pointer = .; /* define a global symbol at end of code */ + __DATA_ROM = .; /* Symbol is used by startup for data initialization */ + + .data : AT(__DATA_ROM) + { + . = ALIGN(4); + __DATA_RAM = .; + __data_start__ = .; /* create a global symbol at data start */ + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + *(.sdata .sdata.*) + *(.heapsram*) /* This is only for the pulpino official test code. */ + __noncachedata_start__ = .; /* create a global symbol at ncache data start */ + *(NonCacheable) + __noncachedata_end__ = .; /* define a global symbol at ncache data end */ + KEEP(*(.jcr*)) + . = ALIGN(4); + __data_end__ = .; /* define a global symbol at data end */ + } > m_data + + __DATA_END = __DATA_ROM + (__data_end__ - __data_start__); + text_end = ORIGIN(m_text) + LENGTH(m_text); + ASSERT(__DATA_END <= text_end, "region m_text overflowed with text and data") + + _edata = .; + + .stack : + { + . = ALIGN(8); + __StackLimit = .; + . += STACK_SIZE; + __StackTop = .; + } > m_data + + /* Initializes stack on the end of block */ + PROVIDE(__stack = __StackTop); + + /* Uninitialized data section */ + .bss : + { + /* This is used by the startup in order to initialize the .bss section */ + . = ALIGN(4); + __START_BSS = .; + __bss_start__ = .; + *(.bss) + *(.bss*) + *(.sbss) + *(.sbss*) + *(COMMON) + . = ALIGN(4); + __bss_end__ = .; + __END_BSS = .; + } > m_data + + /* End of uninitalized data segement */ + _end = .; + PROVIDE(end = .); +} diff --git a/Ubiquitous/XiZi/board/rv32m1_vega/third_party_driver/Kconfig b/Ubiquitous/XiZi/board/rv32m1_vega/third_party_driver/Kconfig new file mode 100755 index 0000000..cee6d37 --- /dev/null +++ b/Ubiquitous/XiZi/board/rv32m1_vega/third_party_driver/Kconfig @@ -0,0 +1,25 @@ +menuconfig BSP_USING_GPIO + bool "Using GPIO device" + default y + select RESOURCES_PIN + if BSP_USING_GPIO + source "$BSP_DIR/third_party_driver/gpio/Kconfig" + endif + +menuconfig BSP_USING_SYSCLOCK + bool "Using SYSCLOCK device" + default y + if BSP_USING_SYSCLOCK + source "$BSP_DIR/third_party_driver/sys_clock/Kconfig" + endif + +menuconfig BSP_USING_UART + bool "Using UART device" + default y + select RESOURCES_SERIAL + if BSP_USING_UART + source "$BSP_DIR/third_party_driver/uart/Kconfig" + endif + + + \ No newline at end of file diff --git a/Ubiquitous/XiZi/board/rv32m1_vega/third_party_driver/Makefile b/Ubiquitous/XiZi/board/rv32m1_vega/third_party_driver/Makefile new file mode 100755 index 0000000..a9a918d --- /dev/null +++ b/Ubiquitous/XiZi/board/rv32m1_vega/third_party_driver/Makefile @@ -0,0 +1,17 @@ +SRC_FILES := fsl_intmux.c fsl_clock.c +SRC_DIR := + +ifeq ($(CONFIG_BSP_USING_GPIO),y) + SRC_DIR += gpio +endif + +ifeq ($(CONFIG_BSP_USING_SYSCLOCK),y) + SRC_DIR += sys_clock +endif + +ifeq ($(CONFIG_BSP_USING_UART),y) + SRC_DIR += uart +endif + + +include $(KERNEL_ROOT)/compiler.mk diff --git a/Ubiquitous/XiZi/board/rv32m1_vega/third_party_driver/gpio/Kconfig b/Ubiquitous/XiZi/board/rv32m1_vega/third_party_driver/gpio/Kconfig new file mode 100755 index 0000000..35dce73 --- /dev/null +++ b/Ubiquitous/XiZi/board/rv32m1_vega/third_party_driver/gpio/Kconfig @@ -0,0 +1,11 @@ +config PIN_BUS_NAME + string "pin bus name" + default "pin" + +config PIN_DRIVER_NAME + string "pin driver name" + default "pin_drv" + +config PIN_DEVICE_NAME + string "pin device name" + default "pin_dev" diff --git a/Ubiquitous/XiZi/board/rv32m1_vega/third_party_driver/gpio/Makefile b/Ubiquitous/XiZi/board/rv32m1_vega/third_party_driver/gpio/Makefile new file mode 100755 index 0000000..0894fb0 --- /dev/null +++ b/Ubiquitous/XiZi/board/rv32m1_vega/third_party_driver/gpio/Makefile @@ -0,0 +1,3 @@ +SRC_FILES := pin_mux.c + +include $(KERNEL_ROOT)/compiler.mk diff --git a/Ubiquitous/XiZi/board/rv32m1_vega/third_party_driver/uart/Kconfig b/Ubiquitous/XiZi/board/rv32m1_vega/third_party_driver/uart/Kconfig new file mode 100755 index 0000000..3da44cd --- /dev/null +++ b/Ubiquitous/XiZi/board/rv32m1_vega/third_party_driver/uart/Kconfig @@ -0,0 +1,14 @@ +menuconfig BSP_USING_UART0 + bool "Enable UART0" + default y + if BSP_USING_UART0 + config SERIAL_BUS_NAME_0 + string "serial bus name" + default "uart0" + config SERIAL_DRV_NAME_0 + string "serial bus driver name" + default "uart0_drv" + config SERIAL_0_DEVICE_NAME_0 + string "serial bus device name" + default "uart0_dev0" + endif diff --git a/Ubiquitous/XiZi/board/rv32m1_vega/third_party_driver/uart/Makefile b/Ubiquitous/XiZi/board/rv32m1_vega/third_party_driver/uart/Makefile new file mode 100755 index 0000000..9c2ea62 --- /dev/null +++ b/Ubiquitous/XiZi/board/rv32m1_vega/third_party_driver/uart/Makefile @@ -0,0 +1,4 @@ +SRC_FILES := connect_uart.c fsl_lpuart.c + + +include $(KERNEL_ROOT)/compiler.mk diff --git a/Ubiquitous/XiZi/board/rv32m1_vega/third_party_driver/uart/connect_uart.c b/Ubiquitous/XiZi/board/rv32m1_vega/third_party_driver/uart/connect_uart.c new file mode 100755 index 0000000..db3ad14 --- /dev/null +++ b/Ubiquitous/XiZi/board/rv32m1_vega/third_party_driver/uart/connect_uart.c @@ -0,0 +1,342 @@ +/* +* Copyright (c) 2020 AIIT XUOS Lab +* XiUOS is licensed under Mulan PSL v2. +* You can use this software according to the terms and conditions of the Mulan PSL v2. +* You may obtain a copy of Mulan PSL v2 at: +* http://license.coscl.org.cn/MulanPSL2 +* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, +* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, +* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. +* See the Mulan PSL v2 for more details. +*/ + +/** +* @file connect_usart.c +* @brief support vega-board uart function and register to bus framework +* @version 1.0 +* @author AIIT XUOS Lab +* @date 2022-02-16 +*/ + +#include +#include +#include +#include "connect_uart.h" +#include "fsl_lpuart.h" + + +static void SerialCfgParamCheck(struct SerialCfgParam *serial_cfg_default, struct SerialCfgParam *serial_cfg_new) +{ + struct SerialDataCfg *data_cfg_default = &serial_cfg_default->data_cfg; + struct SerialDataCfg *data_cfg_new = &serial_cfg_new->data_cfg; + + if ((data_cfg_default->serial_baud_rate != data_cfg_new->serial_baud_rate) && (data_cfg_new->serial_baud_rate)) { + data_cfg_default->serial_baud_rate = data_cfg_new->serial_baud_rate; + } + + if ((data_cfg_default->serial_bit_order != data_cfg_new->serial_bit_order) && (data_cfg_new->serial_bit_order)) { + data_cfg_default->serial_bit_order = data_cfg_new->serial_bit_order; + } + + if ((data_cfg_default->serial_buffer_size != data_cfg_new->serial_buffer_size) && (data_cfg_new->serial_buffer_size)) { + data_cfg_default->serial_buffer_size = data_cfg_new->serial_buffer_size; + } + + if ((data_cfg_default->serial_data_bits != data_cfg_new->serial_data_bits) && (data_cfg_new->serial_data_bits)) { + data_cfg_default->serial_data_bits = data_cfg_new->serial_data_bits; + } + + if ((data_cfg_default->serial_invert_mode != data_cfg_new->serial_invert_mode) && (data_cfg_new->serial_invert_mode)) { + data_cfg_default->serial_invert_mode = data_cfg_new->serial_invert_mode; + } + + if ((data_cfg_default->serial_parity_mode != data_cfg_new->serial_parity_mode) && (data_cfg_new->serial_parity_mode)) { + data_cfg_default->serial_parity_mode = data_cfg_new->serial_parity_mode; + } + + if ((data_cfg_default->serial_stop_bits != data_cfg_new->serial_stop_bits) && (data_cfg_new->serial_stop_bits)) { + data_cfg_default->serial_stop_bits = data_cfg_new->serial_stop_bits; + } +} + +static void UartIsr(struct SerialDriver *serial_drv, struct SerialHardwareDevice *serial_dev) +{ + struct SerialCfgParam *serial_cfg = (struct SerialCfgParam *)serial_drv->private_data; + LPUART_Type *uart_base = (LPUART_Type *)serial_cfg->hw_cfg.serial_register_base; + + /* UART in mode Receiver */ + if (LPUART_GetStatusFlags(uart_base) & kLPUART_RxDataRegFullFlag) + { + SerialSetIsr(serial_dev, SERIAL_EVENT_RX_IND); + } + + /* If RX overrun. */ + if (LPUART_STAT_OR_MASK & uart_base->STAT) + { + /* Clear overrun flag, otherwise the RX does not work. */ + uart_base->STAT = ((uart_base->STAT & 0x3FE00000U) | LPUART_STAT_OR_MASK); + } + +} + +static uint32 SerialInit(struct SerialDriver *serial_drv, struct BusConfigureInfo *configure_info) +{ + lpuart_config_t config; + + NULL_PARAM_CHECK(serial_drv); + struct SerialCfgParam *serial_cfg = (struct SerialCfgParam *)serial_drv->private_data; + + LPUART_GetDefaultConfig(&config); + config.baudRate_Bps = serial_cfg->data_cfg.serial_baud_rate; + + switch (serial_cfg->data_cfg.serial_data_bits) + { +#if defined(FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT) && FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT + case DATA_BITS_7: + config.dataBitsCount = kLPUART_SevenDataBits; + break; +#endif + + default: + config.dataBitsCount = kLPUART_EightDataBits; + break; + } + + switch (serial_cfg->data_cfg.serial_stop_bits) + { + case STOP_BITS_2: + config.stopBitCount = kLPUART_TwoStopBit; + break; + default: + config.stopBitCount = kLPUART_OneStopBit; + break; + } + + switch (serial_cfg->data_cfg.serial_parity_mode) + { + case PARITY_ODD: + config.parityMode = kLPUART_ParityOdd; + break; + case PARITY_EVEN: + config.parityMode = kLPUART_ParityEven; + break; + default: + config.parityMode = kLPUART_ParityDisabled; + break; + } + + config.enableTx = 1; + config.enableRx = 1; + + CLOCK_SetIpSrc(kCLOCK_Lpuart0, kCLOCK_IpSrcFircAsync); + + uint32_t uartClkSrcFreq0 = CLOCK_GetIpFreq(kCLOCK_Lpuart0); + LPUART_Init((LPUART_Type *)serial_cfg->hw_cfg.serial_register_base, &config, uartClkSrcFreq0); + LPUART_EnableInterrupts((LPUART_Type *)serial_cfg->hw_cfg.serial_register_base, kLPUART_RxDataRegFullInterruptEnable); + + CLOCK_SetIpSrc(kCLOCK_Lpuart1, kCLOCK_IpSrcFircAsync); + + uint32_t uartClkSrcFreq1 = CLOCK_GetIpFreq(kCLOCK_Lpuart1); + LPUART_Init((LPUART_Type *)serial_cfg->hw_cfg.serial_register_base, &config, uartClkSrcFreq1); + LPUART_EnableInterrupts((LPUART_Type *)serial_cfg->hw_cfg.serial_register_base, kLPUART_RxDataRegFullInterruptEnable); + + + return EOK; +} + +static uint32 SerialConfigure(struct SerialDriver *serial_drv, int serial_operation_cmd) +{ + NULL_PARAM_CHECK(serial_drv); + + struct SerialCfgParam *serial_cfg = (struct SerialCfgParam *)serial_drv->private_data; + + switch (serial_operation_cmd) + { + case OPER_CLR_INT: + DisableIRQ(serial_cfg->hw_cfg.serial_irq_interrupt); + break; + case OPER_SET_INT: + EnableIRQ(serial_cfg->hw_cfg.serial_irq_interrupt); + break; + } + + return EOK; +} + +static uint32 SerialDrvConfigure(void *drv, struct BusConfigureInfo *configure_info) +{ + NULL_PARAM_CHECK(drv); + NULL_PARAM_CHECK(configure_info); + + x_err_t ret = EOK; + int serial_operation_cmd; + struct SerialDriver *serial_drv = (struct SerialDriver *)drv; + + switch (configure_info->configure_cmd) + { + case OPE_INT: + ret = SerialInit(serial_drv, configure_info); + break; + case OPE_CFG: + serial_operation_cmd = *(int *)configure_info->private_data; + ret = SerialConfigure(serial_drv, serial_operation_cmd); + break; + default: + break; + } + + return ret; +} + +static int SerialPutChar(struct SerialHardwareDevice *serial_dev, char c) +{ + struct SerialCfgParam *serial_cfg = (struct SerialCfgParam *)serial_dev->private_data; + + LPUART_WriteByte((LPUART_Type *)serial_cfg->hw_cfg.serial_register_base, (uint8_t) c); + while (!(LPUART_GetStatusFlags((LPUART_Type *)serial_cfg->hw_cfg.serial_register_base) & kLPUART_TxDataRegEmptyFlag)); + + return 0; +} + +static int SerialGetChar(struct SerialHardwareDevice *serial_dev) +{ + int ch = -1; + struct SerialCfgParam *serial_cfg = (struct SerialCfgParam *)serial_dev->private_data; + + if (LPUART_GetStatusFlags((LPUART_Type *)serial_cfg->hw_cfg.serial_register_base) & kLPUART_RxDataRegFullFlag) + ch = LPUART_ReadByte((LPUART_Type *)serial_cfg->hw_cfg.serial_register_base); + + return ch; +} + +static const struct SerialDataCfg data_cfg_init = +{ + .serial_baud_rate = BAUD_RATE_115200, + .serial_data_bits = DATA_BITS_8, + .serial_stop_bits = STOP_BITS_1, + .serial_parity_mode = PARITY_NONE, + .serial_bit_order = BIT_ORDER_LSB, + .serial_invert_mode = NRZ_NORMAL, + .serial_buffer_size = SERIAL_RB_BUFSZ, +}; + + + +/*manage the serial device operations*/ +static const struct SerialDrvDone drv_done = +{ + .init = SerialInit, + .configure = SerialConfigure, +}; + +/*manage the serial device hal operations*/ +static struct SerialHwDevDone hwdev_done = +{ + .put_char = SerialPutChar, + .get_char = SerialGetChar, +}; + +static int BoardSerialBusInit(struct SerialBus *serial_bus, struct SerialDriver *serial_driver, const char *bus_name, const char *drv_name) +{ + x_err_t ret = EOK; + + /*Init the serial bus */ + ret = SerialBusInit(serial_bus, bus_name); + if (EOK != ret) { + KPrintf("InitHwUart SerialBusInit error %d\n", ret); + return -ERROR; + } + + /*Init the serial driver*/ + ret = SerialDriverInit(serial_driver, drv_name); + if (EOK != ret) { + KPrintf("InitHwUart SerialDriverInit error %d\n", ret); + return -ERROR; + } + + /*Attach the serial driver to the serial bus*/ + ret = SerialDriverAttachToBus(drv_name, bus_name); + if (EOK != ret) { + KPrintf("InitHwUart SerialDriverAttachToBus error %d\n", ret); + return -ERROR; + } + + return ret; +} + +/*Attach the serial device to the serial bus*/ +static int BoardSerialDevBend(struct SerialHardwareDevice *serial_device, void *serial_param, const char *bus_name, const char *dev_name) +{ + x_err_t ret = EOK; + + ret = SerialDeviceRegister(serial_device, serial_param, dev_name); + if (EOK != ret) { + KPrintf("InitHwUart SerialDeviceInit device %s error %d\n", dev_name, ret); + return ERROR; + } + + ret = SerialDeviceAttachToBus(dev_name, bus_name); + if (EOK != ret) { + KPrintf("InitHwUart SerialDeviceAttachToBus device %s error %d\n", dev_name, ret); + return -ERROR; + } + + return ret; +} +#ifdef BSP_USING_UART0 +struct SerialDriver serial_driver_0; +struct SerialHardwareDevice serial_device_0; + +void LPUART0_IRQHandler(int irq_num, void *arg) +{ + UartIsr(&serial_driver_0, &serial_device_0); +} +#endif + +int InitHwUart(void) +{ + x_err_t ret = EOK; + +#ifdef BSP_USING_UART0 + static struct SerialBus serial_bus; + memset(&serial_bus, 0, sizeof(struct SerialBus)); + + memset(&serial_driver_0, 0, sizeof(struct SerialDriver)); + + memset(&serial_device_0, 0, sizeof(struct SerialHardwareDevice)); + + static struct SerialCfgParam serial_cfg; + memset(&serial_cfg, 0, sizeof(struct SerialCfgParam)); + + static struct SerialDevParam serial_dev_param; + memset(&serial_dev_param, 0, sizeof(struct SerialDevParam)); + + serial_driver_0.drv_done = &drv_done; + serial_driver_0.configure = &SerialDrvConfigure; + serial_device_0.hwdev_done = &hwdev_done; + + serial_cfg.data_cfg = data_cfg_init; + + serial_cfg.hw_cfg.serial_register_base = (uint32)LPUART0; + serial_cfg.hw_cfg.serial_irq_interrupt = LPUART0_IRQn; + + serial_driver_0.private_data = (void *)&serial_cfg; + + serial_dev_param.serial_work_mode = SIGN_OPER_INT_RX; + serial_device_0.haldev.private_data = (void *)&serial_dev_param; + + ret = BoardSerialBusInit(&serial_bus, &serial_driver_0, SERIAL_BUS_NAME_0, SERIAL_DRV_NAME_0); + if (EOK != ret) { + KPrintf("InitHwUart uarths error ret %u\n", ret); + return -ERROR; + } + + ret = BoardSerialDevBend(&serial_device_0, (void *)&serial_cfg, SERIAL_BUS_NAME_0, SERIAL_0_DEVICE_NAME_0); + if (EOK != ret) { + KPrintf("InitHwUart uarths error ret %u\n", ret); + return -ERROR; + } +#endif + + return ret; +} diff --git a/Ubiquitous/XiZi/board/stm32f103-nano/.defconfig b/Ubiquitous/XiZi/board/stm32f103-nano/.defconfig new file mode 100644 index 0000000..76957e6 --- /dev/null +++ b/Ubiquitous/XiZi/board/stm32f103-nano/.defconfig @@ -0,0 +1,218 @@ +# +# Automatically generated file; DO NOT EDIT. +# XiZi Project Configuration +# +CONFIG_BOARD_STM32F103_NANO=y +CONFIG_KERNEL_CONSOLE_DEVICE_NAME="uart1" +CONFIG_ARCH_ARM=y + +# +# stm32f103-nano feature +# +# CONFIG_BSP_USING_DMA is not set +# CONFIG_BSP_USING_GPIO is not set +# CONFIG_BSP_USING_I2C is not set +# CONFIG_BSP_USING_LCD is not set +# CONFIG_BSP_USING_EXTMEM is not set +# CONFIG_BSP_USING_SDIO is not set +# CONFIG_BSP_USING_RTC is not set +# CONFIG_BSP_USING_SPI is not set +# CONFIG_BSP_USING_HWTIMER is not set +# CONFIG_BSP_USING_WDT is not set +CONFIG_BSP_USING_UART=y +CONFIG_BSP_USING_UART1=y +# CONFIG_BSP_USING_UART2 is not set +# CONFIG_BSP_USING_UART3 is not set +# CONFIG_BSP_USING_UART4 is not set +# CONFIG_BSP_USING_UART5 is not set +# CONFIG_BSP_USING_USB is not set +# CONFIG_BSP_USING_STM32_USBH is not set + +# +# Hardware feature +# +CONFIG_RESOURCES_SERIAL=y +# CONFIG_SERIAL_USING_DMA is not set +# CONFIG_SERIAL_RB_BUFSZ is not set +# CONFIG_RESOURCES_CAN is not set +# CONFIG_RESOURCES_HWTIMER is not set +# CONFIG_RESOURCES_I2C is not set +# CONFIG_RESOURCES_LCD is not set +# CONFIG_RESOURCES_SDIO is not set +# CONFIG_RESOURCES_TOUCH is not set +CONFIG_RESOURCES_PIN=y +# CONFIG_RESOURCES_RTC is not set +# CONFIG_RESOURCES_SPI is not set +# CONFIG_RESOURCES_SPI_SD is not set +# CONFIG_RESOURCES_SPI_SFUD is not set +# SFUD_USING_SFDP is not set +# SFUD_USING_FLASH_INFO_TABLE is not set +# SFUD_DEBUG_LOG is not set +# CONFIG_RESOURCES_WDT is not set +# CONFIG_RESOURCES_USB is not set +# CONFIG_RESOURCES_USB_HOST is not set +# CONFIG_UDISK_MOUNTPOINT is not set +# CONFIG_USBH_MSTORAGE is not set +# CONFIG_RESOURCES_USB_DEVICE is not set +# CONFIG_USBD_THREAD_STACK_SZ is not set + +# +# Kernel feature +# +# CONFIG_SEPARATE_COMPILE is not set +# CONFIG_COMPILER_APP is not set +# CONFIG_COMPILER_KERNEL is not set +# +# Kernel Device Object +# +CONFIG_KERNEL_DEVICE=y +CONFIG_KERNEL_CONSOLE=y +CONFIG_KERNEL_CONSOLEBUF_SIZE=128 + +# +# Task feature +# +CONFIG_SCHED_POLICY_RR_REMAINSLICE=y +# CONFIG_SCHED_POLICY_RR is not set +# CONFIG_SCHED_POLICY_FIFO is not set + +# +# Inter-Task communication +# +CONFIG_KERNEL_SEMAPHORE=y +CONFIG_KERNEL_MUTEX=y +CONFIG_KERNEL_EVENT=y +CONFIG_KERNEL_MESSAGEQUEUE=y +# CONFIG_KTASK_PRIORITY_8 is not set +CONFIG_KTASK_PRIORITY_32=y +# CONFIG_KTASK_PRIORITY_256 is not set +CONFIG_KTASK_PRIORITY_MAX=32 +CONFIG_TICK_PER_SECOND=1000 +CONFIG_KERNEL_STACK_OVERFLOW_CHECK=y +CONFIG_KERNEL_BANNER=y +# CONFIG_KERNEL_HOOK is not set +CONFIG_KERNEL_SOFTTIMER=y +CONFIG_KERNEL_IDLE_HOOK=y +CONFIG_IDEL_HOOK_LIST_SIZE=4 +CONFIG_IDLE_KTASK_STACKSIZE=256 +CONFIG_USER_APPLICATION=y +# CONFIG_TASK_ISOLATION is not set + +# +# Memory Management +# +# CONFIG_KERNEL_MEMBLOCK is not set + +# +# Command shell +# +CONFIG_TOOL_SHELL=y +CONFIG_SHELL_ENTER_CR=y +CONFIG_SHELL_ENTER_LF=y +CONFIG_SHELL_ENTER_CR_AND_LF=y +# CONFIG_SHELL_ENTER_CRLF is not set + +# +# User Control +# +CONFIG_SHELL_DEFAULT_USER="letter" +CONFIG_SHELL_DEFAULT_USER_PASSWORD="" +CONFIG_SHELL_LOCK_TIMEOUT=10000 +CONFIG_SHELL_TASK_STACK_SIZE=4096 +CONFIG_SHELL_TASK_PRIORITY=20 +CONFIG_SHELL_MAX_NUMBER=5 +CONFIG_SHELL_PARAMETER_MAX_NUMBER=8 +CONFIG_SHELL_HISTORY_MAX_NUMBER=5 +CONFIG_SHELL_PRINT_BUFFER=128 +CONFIG_SHELL_USING_CMD_EXPORT=y +CONFIG_SHELL_HELP_SHOW_PERMISSION=y +# CONFIG_SHELL_HELP_LIST_USER is not set +# CONFIG_SHELL_HELP_LIST_VAR is not set +# CONFIG_SHELL_HELP_LIST_KEY is not set +CONFIG_KERNEL_QUEUEMANAGE=y +CONFIG_KERNEL_WORKQUEUE=y +# CONFIG_WORKQUEUE_KTASK_STACKSIZE is not set +# CONFIG_WORKQUEUE_KTASK_PRIORITY is not set +CONFIG_KERNEL_WAITQUEUE=y +CONFIG_KERNEL_DATAQUEUE=y +# CONFIG_KERNEL_CIRCULAR_AREA is not set +# CONFIG_KERNEL_AVL_TREE is not set +CONFIG_NAME_MAX=8 +CONFIG_ALIGN_SIZE=4 +CONFIG_KERNEL_COMPONENTS_INIT=y +CONFIG_KERNEL_USER_MAIN=y +CONFIG_MAIN_KTASK_STACK_SIZE=256 +CONFIG_ENV_INIT_KTASK_STACK_SIZE=1024 +CONFIG_MAIN_KTASK_PRIORITY=10 +# CONFIG_USER_TEST is not set +# CONFIG_TOOL_TEST_SEM is not set +# CONFIG_TOOL_TEST_MUTEX is not set +# CONFIG_TOOL_TEST_EVENT is not set +# CONFIG_TOOL_TEST_MSG is not set +# CONFIG_TOOL_TEST_AVLTREE is not set +# CONFIG_TEST_CRICULAR_AREA is not set +# CONFIG_TOOL_TEST_MEM is not set +# CONFIG_TOOL_TEST_TIMER is not set +# CONFIG_TOOL_TEST_IWG is not set +# CONFIG_TOOL_TEST_REALTIME is not set +# CONFIG_TOOL_TEST_DBG is not set +# CONFIG_TOOL_TEST_SCHED is not set +# CONFIG_KERNEL_DEBUG is not set +CONFIG_DEBUG_INIT_CONFIG=y +CONFIG_DBG_INIT=1 +# CONFIG_ARCH_SMP is not set + +# +# File system +# +# CONFIG_FS_VFS is not set +# CONFIG_VFS_USING_WORKDIR is not set +# CONFIG_FS_VFS_DEVFS is not set + +# +# Fat filesystem +# + +# +# IOT-Device File system +# + +# +# Lwext4 filesystem +# + +# +# APP Framework +# + +# +# connection +# +# CONFIG_CONNECTION_AT is not set +# CONFIG_CONNECTION_MQTT is not set + +# +# medium communication +# + + +# +# Intelligence +# + +# +# Control +# + +# +# Lib +# +CONFIG_LIB=y +CONFIG_LIB_POSIX=y +CONFIG_LIB_NEWLIB=y + +CONFIG_LITTLEVGL2RTT_USING_DEMO=y + +# +# Security +# diff --git a/Ubiquitous/XiZi/board/stm32f103-nano/Kconfig b/Ubiquitous/XiZi/board/stm32f103-nano/Kconfig new file mode 100644 index 0000000..6067167 --- /dev/null +++ b/Ubiquitous/XiZi/board/stm32f103-nano/Kconfig @@ -0,0 +1,45 @@ +mainmenu "XiZi Project Configuration" + +config BSP_DIR + string + option env="BSP_ROOT" + default "." + +config KERNEL_DIR + string + option env="KERNEL_ROOT" + default "../.." + +config BOARD_STM32F103_NANO + bool + select ARCH_ARM + default y + +source "$KERNEL_DIR/arch/Kconfig" + +menu "stm32f103-nano feature" + source "$BSP_DIR/third_party_driver/Kconfig" + + menu "config default board resources" + menu "config board app name" + config BOARD_APP_NAME + string "config board app name" + default "/XiUOS_stm32f103nano_app.bin" + endmenu + + menu "config board service table" + config SERVICE_TABLE_ADDRESS + hex "board service table address" + default 0x20000000 + endmenu + + endmenu + +endmenu + + +menu "Hardware feature" +source "$KERNEL_DIR/resources/Kconfig" +endmenu + +source "$KERNEL_DIR/Kconfig" diff --git a/Ubiquitous/XiZi/board/stm32f103-nano/Makefile b/Ubiquitous/XiZi/board/stm32f103-nano/Makefile new file mode 100644 index 0000000..683e42a --- /dev/null +++ b/Ubiquitous/XiZi/board/stm32f103-nano/Makefile @@ -0,0 +1,8 @@ +SRC_FILES := board.c + +SRC_DIR := third_party_driver + + + + +include $(KERNEL_ROOT)/compiler.mk \ No newline at end of file diff --git a/Ubiquitous/XiZi/board/stm32f103-nano/README.md b/Ubiquitous/XiZi/board/stm32f103-nano/README.md new file mode 100644 index 0000000..e2c87ed --- /dev/null +++ b/Ubiquitous/XiZi/board/stm32f103-nano/README.md @@ -0,0 +1,229 @@ +# 从零开始构建矽璓工业物联操作系统：使用ARM架构的STM32F103-nano开发板 + +[XiUOS](http://xuos.io/) (X Industrial Ubiquitous Operating System) 矽璓工业物联操作系统是一款面向工业物联场景的泛在操作系统，来自泛在操作系统研究计划。所谓泛在操作系统(UOS: Ubiquitous Operating Systems)，是支持互联网时代人机物融合泛在计算应用模式的新型操作系统，是传统操作系统概念的泛化与延伸。在泛在操作系统技术体系中，不同的泛在计算设备和泛在应用场景需要符合各自特性的不同UOS，XiUOS即是面向工业物联场景的一种UOS，主要由一个极简的微型实时操作系统(RTOS)内核和其上的智能工业物联框架构成，支持工业物联网(IIoT: Industrial Internet of Things)应用。 + +## 开发环境搭建 + +### 推荐使用： + +**操作系统：** ubuntu18.04 [https://ubuntu.com/download/desktop](https://ubuntu.com/download/desktop) + +更新`ubuntu 18.04`源的方法:（根据自身情况而定，可以不更改） + +第一步:打开sources.list文件 + +```c +sudo vim /etc/apt/sources.list +``` + +第二步:将以下内容复制到sources.list文件 + +```c +deb http://mirrors.aliyun.com/ubuntu/ bionic main restricted universe multiverse +deb http://mirrors.aliyun.com/ubuntu/ bionic-security main restricted universe multiverse +deb http://mirrors.aliyun.com/ubuntu/ bionic-updates main restricted universe multiverse +deb http://mirrors.aliyun.com/ubuntu/ bionic-proposed main restricted universe multiverse +deb http://mirrors.aliyun.com/ubuntu/ bionic-backports main restricted universe multiverse +deb-src http://mirrors.aliyun.com/ubuntu/ bionic main restricted universe multiverse +deb-src http://mirrors.aliyun.com/ubuntu/ bionic-security main restricted universe multiverse +deb-src http://mirrors.aliyun.com/ubuntu/ bionic-updates main restricted universe multiverse +deb-src http://mirrors.aliyun.com/ubuntu/ bionic-proposed main restricted universe multiverse +deb-src http://mirrors.aliyun.com/ubuntu/ bionic-backports main restricted universe multiverse +``` + +第三步:更新源和系统软件 + +```c +sudo apt-get update +sudo apt-get upgrade +``` + +**开发工具推荐使用 VSCode ，VScode下载地址为：** VSCode [https://code.visualstudio.com/](https://code.visualstudio.com/)，推荐下载地址为 [http://vscode.cdn.azure.cn/stable/3c4e3df9e89829dce27b7b5c24508306b151f30d/code_1.55.2-1618307277_amd64.deb](http://vscode.cdn.azure.cn/stable/3c4e3df9e89829dce27b7b5c24508306b151f30d/code_1.55.2-1618307277_amd64.deb) + +### 依赖包安装： + +``` +$ sudo apt install build-essential pkg-config git +$ sudo apt install gcc make libncurses5-dev openssl libssl-dev bison flex libelf-dev autoconf libtool gperf libc6-dev +``` + +**XiUOS操作系统源码下载：** XiUOS [https://www.gitlink.org.cn/xuos/xiuos](https://www.gitlink.org.cn/xuos/xiuos) + +新建一个空文件夹并进入文件夹中，并下载源码，具体命令如下： + +```c +mkdir test && cd test +git clone https://gitlink.org.cn/xuos/xiuos.git +``` + +1、打开XiUOS源码文件包可以看到以下目录： +| 名称 | 说明 | +| -- | -- | +| APP_Framework | 应用代码 | +| Ubiquitous | 板级支持包,支持NuttX、RT-Thread和XiZi内核 | + +2、打开XiZi内核源码文件包可以看到以下目录： +| 名称 | 说明 | +| -- | -- | +| arch | 架构代码 | +| board | 板级支持包 | +| fs | 文件系统 | +| kernel | 内核源码 | +| lib | 第三方库源码 | +| resources | 驱动文件 | +| tool | 系统工具 | + +使用VScode打开代码，具体操作步骤为：在源码文件夹下打开系统终端，输入`code .`即可打开VScode开发环境，如下图所示： + +

+ +### 裁减配置工具的下载 + +裁减配置工具： + +**工具地址：** kconfig-frontends [https://www.gitlink.org.cn/xuos/kconfig-frontends](https://www.gitlink.org.cn/xuos/kconfig-frontends)，下载与安装的具体命令如下： + +```c +mkdir kfrontends && cd kfrontends +git clone https://gitlink.org.cn/xuos/kconfig-frontends.git +``` + +下载源码后按以下步骤执行软件安装： + +```c +cd kconfig-frontends +./xs_build.sh +``` + +### 编译工具链： + +ARM： arm-none-eabi(`gcc version 6.3.1`)，默认安装到Ubuntu的/usr/bin/arm-none-eabi-，使用如下命令行下载和安装。 + +```shell +$ sudo apt install gcc-arm-none-eabi +``` + +# 在STM32F103-nano上创建第一个应用 --helloworld + +## 1. 简介 + +| 硬件 | 描述 | +| -- | -- | +|芯片型号| Stm32F103RBT6| +|CPU|arm cortex-m3| +|主频| 72MHz | +|片内SRAM| 20KB | +|片上FLASH| 128KB | +| 外设 | -- | +| | ADC、DAC、USB、GPIO、UART、SPI、SDIO、RTC、CAN、DMA、MAC、I²C、WDT、Timer等 | + +XiUOS板级驱动当前支持使用GPIO、UART。 + +## 2. 编译说明 + +### 编辑环境：`Ubuntu18.04` + +### 编译工具链：`arm-none-eabi-gcc` +使用`VScode`打开工程的方法有多种，本文介绍一种快捷键，在项目目录下将`code .`输入linux系统命令终端即可打开目标项目 + +修改`APP_Framework/Applications`文件夹下`main.c` +在输出函数中写入 `Hello, world!`完成代码编辑。 + +![main](img/main.png) + +编译步骤： + +1.在VScode命令终端中执行以下命令，生成配置文件。 + +```c +cd ./Ubiquitous/XiZi +make BOARD=stm32f103-nano distclean +make BOARD=stm32f103-nano menuconfig +``` + +2.在menuconfig界面配置需要关闭和开启的功能，按回车键进入下级菜单，按Y键选中需要开启的功能，按N键选中需要关闭的功能，配置结束后保存并退出（本例旨在演示简单的输出例程，所以没有需要配置的选项，双击快捷键ESC退出配置）。 + +![menuconfig1](img/menuconfig1.png) + +退出时选择`yes`保存上面所配置的内容，如下图所示： + +![menuconfig2](img/menuconfig2.png) + +3.需要注意的是，stm32f103-nano开发板中CPU RAM大小为20KB，需要调整XiUOS中堆栈相关配置的默认值，避免出现超出堆栈大小而无法正常启动。 + +（1）ID hash table配置，ID num配置为16，减少.bss段大小; + +![ID_HASH_TABLE](img/ID_HASH_TABLE.png) + +（2）IPC feature配置，保留信号量、互斥锁等必需的进程间通信，关闭队列等未用到的方式; + +![IPC_FEATURE](img/IPC_FEATURE.png) + +（3）ENV task配置，该线程栈大小配置为1024; + +![KTASK_SIZE](img/KTASK_SIZE.png) + +（4）MAIN task配置，该线程栈大小配置为256; + +![MAIN_STACK_SIZE](img/MAIN_STACK_SIZE.png) + +（5）大内存分配页对齐配置，页对齐配置为1KB，减少页对齐后优化的ram空间，增加可分配的堆大小; + +![MEMORY_PAGE_SIZE](img/MEMORY_PAGE_SIZE.png) + +（6）SHELL task配置，该线程栈大小配置为4096，建议无优化空间时再选择减少SHELL线程栈大小，避免出现SHELL工作异常的情况; + +![SHELL_STACK_SIZE](img/SHELL_STACK_SIZE.png) + +（7）WORKQUEUE配置，若未用到工作队列，可关闭该功能，减少堆栈空间申请; + +![WORKQUEUE](img/WORKQUEUE.png) + +（7）ZOMBIE RECYCLE task配置 ，僵尸线程回收线程栈大小同样在无优化空间时可选择减少。 + +![ZOMBIE_STACK_SIZE](img/ZOMBIE_STACK_SIZE.png) + +4.继续执行以下命令，进行编译 + +```c +make BOARD=stm32f103-nano +``` + +5.如果编译正确无误，会产生XiZi_stm32f103-nano.elf、XiZi_stm32f103-nano.bin文件。其中XiZi_stm32f103-nano.bin需要烧写到设备中进行运行。 + +## 3. 烧写及执行 + +stm32f103-nano开发板内置板载st-link SWD下载接口，连接USB后便可使用st-flash工具进行烧写bin文件。 + +![stm32f103-nano](img/stm32f103-nano.png) + +### 烧写工具 + +ARM：ST-LINK, stm32f103-nano 板卡内置st-link SWD, 因此无需额外外接工具，只需安装st-flash相关依赖驱动即可。 + +下载并以下执行命令以下命令安装st-link工具(本文使用v1.5.1版本)。 + +``` +sudo apt install libusb-dev +sudo apt install libusb-1.0-0-dev +sudo apt install cmake +cd stlink +make +cd build/Release && make install DESTDIR=_install +``` + +将生成的st-flash（在stlink/build/Release/bin文件夹下）复制到/usr/bin下就可使用了 + +代码根目录下执行st-flash工具烧录 + +``` +sudo st-flash write build/XiZi_stm32f103-nano.bin 0x8000000 +``` + +### 3.1 运行结果 + +如果编译 & 烧写无误，将会在串口终端上看到信息打印输出。 + +![terminal](img/terminal.png) diff --git a/Ubiquitous/XiZi/board/stm32f103-nano/board.h b/Ubiquitous/XiZi/board/stm32f103-nano/board.h new file mode 100644 index 0000000..0ea895e --- /dev/null +++ b/Ubiquitous/XiZi/board/stm32f103-nano/board.h @@ -0,0 +1,35 @@ +/* +* Copyright (c) 2020 AIIT XUOS Lab +* XiUOS is licensed under Mulan PSL v2. +* You can use this software according to the terms and conditions of the Mulan PSL v2. +* You may obtain a copy of Mulan PSL v2 at: +* http://license.coscl.org.cn/MulanPSL2 +* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, +* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, +* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. +* See the Mulan PSL v2 for more details. +*/ + +/** +* @file board.h +* @brief define stm32f103-nano init configure and start-up function +* @version 1.0 +* @author AIIT XUOS Lab +* @date 2021-11-25 +*/ + +#ifndef __BOARD_H__ +#define __BOARD_H__ + +#include +#include + +extern void *__bss_end; +extern void *_heap_end; + +#define HEAP_START ((void *)&__bss_end) +#define HEAP_END ((void *)&_heap_end) + +void SystemClock_Config(void); + +#endif diff --git a/Ubiquitous/XiZi/board/stm32f103-nano/config.mk b/Ubiquitous/XiZi/board/stm32f103-nano/config.mk new file mode 100644 index 0000000..fcfe247 --- /dev/null +++ b/Ubiquitous/XiZi/board/stm32f103-nano/config.mk @@ -0,0 +1,14 @@ +export CROSS_COMPILE ?=/usr/bin/arm-none-eabi- + +export CFLAGS := -mcpu=cortex-m3 -mthumb -ffunction-sections -fdata-sections -Dgcc -O0 -gdwarf-2 -g -fgnu89-inline -Wa,-mimplicit-it=thumb +export AFLAGS := -c -mcpu=cortex-m3 -mthumb -ffunction-sections -fdata-sections -x assembler-with-cpp -Wa,-mimplicit-it=thumb -gdwarf-2 +export LFLAGS := -mcpu=cortex-m3 -mthumb -ffunction-sections -fdata-sections -Wl,--gc-sections,-Map=XiZi_stm32f103-nano.map,-cref,-u,Reset_Handler -T $(BSP_ROOT)/link.lds +export CXXFLAGS := -mcpu=cortex-m3 -mthumb -ffunction-sections -fdata-sections -Dgcc -O0 -gdwarf-2 -g + +export APPLFLAGS := -mcpu=cortex-m3 -mthumb -ffunction-sections -fdata-sections -Wl,--gc-sections,-Map=XiZi_app.map,-cref,-u, -T $(BSP_ROOT)/link_userspace.lds + + +export DEFINES := -DHAVE_CCONFIG_H + +export ARCH = arm +export MCU = cortex-m3 diff --git a/Ubiquitous/XiZi/board/stm32f103-nano/img/ID_HASH_TABLE.png b/Ubiquitous/XiZi/board/stm32f103-nano/img/ID_HASH_TABLE.png new file mode 100644 index 0000000..4a4bb5b Binary files /dev/null and b/Ubiquitous/XiZi/board/stm32f103-nano/img/ID_HASH_TABLE.png differ diff --git a/Ubiquitous/XiZi/board/stm32f103-nano/img/IPC_FEATURE.png b/Ubiquitous/XiZi/board/stm32f103-nano/img/IPC_FEATURE.png new file mode 100644 index 0000000..723afb7 Binary files /dev/null and b/Ubiquitous/XiZi/board/stm32f103-nano/img/IPC_FEATURE.png differ diff --git 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--git a/Ubiquitous/XiZi/board/stm32f103-nano/link.lds b/Ubiquitous/XiZi/board/stm32f103-nano/link.lds new file mode 100644 index 0000000..183b303 --- /dev/null +++ b/Ubiquitous/XiZi/board/stm32f103-nano/link.lds @@ -0,0 +1,107 @@ +/* + * linker script for STM32F10x with GNU ld + */ + +/* Program Entry, set to mark it as "used" and avoid gc */ +MEMORY +{ + flash (rx) : ORIGIN = 0x08000000, LENGTH = 128k /* 128KB flash */ + sram (rw) : ORIGIN = 0x20000000, LENGTH = 20k /* 20K sram */ +} +OUTPUT_ARCH(arm) + +ENTRY(Reset_Handler) +_system_stack_size = 0x200; + +SECTIONS +{ + .text : + { + . = ALIGN(4); + KEEP(*(.isr_vector)) /* Startup code */ + + . = ALIGN(4); + *(.text) /* remaining code */ + *(.text.*) /* remaining code */ + *(.rodata) /* read-only data (constants) */ + *(.rodata*) + *(.glue_7) + *(.glue_7t) + + /* section information for shell */ + . = ALIGN(4); + _shell_command_start = .; + KEEP (*(shellCommand)) + _shell_command_end = .; + . = ALIGN(4); + + __isrtbl_idx_start = .; + KEEP(*(.isrtbl.idx)) + __isrtbl_start = .; + KEEP(*(.isrtbl)) + __isrtbl_end = .; + . = ALIGN(4); + + PROVIDE(g_service_table_start = ABSOLUTE(.)); + KEEP(*(.g_service_table)) + PROVIDE(g_service_table_end = ABSOLUTE(.)); + + PROVIDE(_etext = ABSOLUTE(.)); + + _etext = .; + } > flash = 0 + + /* .ARM.exidx is sorted, so has to go in its own output section. */ + __exidx_start = .; + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + + /* This is used by the startup in order to initialize the .data secion */ + _sidata = .; + } > flash + __exidx_end = .; + + /* .data section which is used for initialized data */ + + .data : AT (_sidata) + { + . = ALIGN(4); + /* This is used by the startup in order to initialize the .data secion */ + _sdata = . ; + + *(.data) + *(.data.*) + + . = ALIGN(4); + /* This is used by the startup in order to initialize the .data secion */ + _edata = . ; + } >sram + + __bss_start = .; + .bss : + { + . = ALIGN(4); + /* This is used by the startup in order to initialize the .bss secion */ + _sbss = .; + + *(.bss) + *(.bss.*) + *(COMMON) + + . = ALIGN(4); + /* This is used by the startup in order to initialize the .bss secion */ + _ebss = . ; + } > sram + __bss_end = .; + + _end = .; + + .stack ORIGIN(sram) + LENGTH(sram) - _system_stack_size : + { + PROVIDE( _heap_end = . ); + . = _system_stack_size; + PROVIDE( _sp = . ); + } >sram + +} diff --git a/Ubiquitous/XiZi/board/stm32f103-nano/third_party_driver/Kconfig b/Ubiquitous/XiZi/board/stm32f103-nano/third_party_driver/Kconfig new file mode 100755 index 0000000..85a7dfe --- /dev/null +++ b/Ubiquitous/XiZi/board/stm32f103-nano/third_party_driver/Kconfig @@ -0,0 +1,7 @@ +menuconfig BSP_USING_UART +bool "Using UART device" +default y +select RESOURCES_SERIAL +if BSP_USING_UART +source "$BSP_DIR/third_party_driver/uart/Kconfig" +endif diff --git a/Ubiquitous/XiZi/board/stm32f103-nano/third_party_driver/Makefile b/Ubiquitous/XiZi/board/stm32f103-nano/third_party_driver/Makefile new file mode 100644 index 0000000..6c51254 --- /dev/null +++ b/Ubiquitous/XiZi/board/stm32f103-nano/third_party_driver/Makefile @@ -0,0 +1,7 @@ +SRC_DIR := libraries + +ifeq ($(CONFIG_BSP_USING_UART),y) + SRC_DIR += uart +endif + +include $(KERNEL_ROOT)/compiler.mk diff --git a/Ubiquitous/XiZi/board/stm32f103-nano/third_party_driver/include/connect_uart.h b/Ubiquitous/XiZi/board/stm32f103-nano/third_party_driver/include/connect_uart.h new file mode 100644 index 0000000..611d701 --- /dev/null +++ b/Ubiquitous/XiZi/board/stm32f103-nano/third_party_driver/include/connect_uart.h @@ -0,0 +1,51 @@ +/* +* Copyright (c) 2020 AIIT XUOS Lab +* XiUOS is licensed under Mulan PSL v2. +* You can use this software according to the terms and conditions of the Mulan PSL v2. +* You may obtain a copy of Mulan PSL v2 at: +* http://license.coscl.org.cn/MulanPSL2 +* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, +* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, +* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. +* See the Mulan PSL v2 for more details. +*/ + +/** +* @file connect_uart.h +* @brief define stm32f103-nano-board uart function and struct +* @version 1.0 +* @author AIIT XUOS Lab +* @date 2021-11-25 +*/ + +#ifndef CONNECT_UART_H +#define CONNECT_UART_H + +#include +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +#define UART_INSTANCE_CLEAR_FUNCTION __HAL_UART_CLEAR_FLAG + +struct Stm32UartHwCfg +{ + UART_HandleTypeDef uart_handle; + USART_TypeDef *uart_device; + IRQn_Type irq_type; +}; + +#define KERNEL_CONSOLE_BUS_NAME SERIAL_BUS_NAME_1 +#define KERNEL_CONSOLE_DRV_NAME SERIAL_DRV_NAME_1 +#define KERNEL_CONSOLE_DEVICE_NAME SERIAL_1_DEVICE_NAME_0 + +int InitHwUart(void); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/Ubiquitous/XiZi/board/stm32f103-nano/third_party_driver/uart/Kconfig b/Ubiquitous/XiZi/board/stm32f103-nano/third_party_driver/uart/Kconfig new file mode 100644 index 0000000..dd0013b --- /dev/null +++ b/Ubiquitous/XiZi/board/stm32f103-nano/third_party_driver/uart/Kconfig @@ -0,0 +1,30 @@ +menuconfig BSP_USING_UART1 + bool "Enable UART1" + default y + if BSP_USING_UART1 + config SERIAL_BUS_NAME_1 + string "serial bus 1 name" + default "uart1" + config SERIAL_DRV_NAME_1 + string "serial bus 1 driver name" + default "uart1_drv" + config SERIAL_1_DEVICE_NAME_0 + string "serial bus 1 device name" + default "uart1_dev1" + endif + +menuconfig BSP_USING_UART2 + bool "Enable UART2" + default n + if BSP_USING_UART2 + config SERIAL_BUS_NAME_2 + string "serial bus 2 name" + default "uart2" + config SERIAL_DRV_NAME_2 + string "serial bus 2 driver name" + default "uart2_drv" + config SERIAL_2_DEVICE_NAME_0 + string "serial bus 2 device name" + default "uart2_dev2" + endif + diff --git a/Ubiquitous/XiZi/board/stm32f103-nano/third_party_driver/uart/Makefile b/Ubiquitous/XiZi/board/stm32f103-nano/third_party_driver/uart/Makefile new file mode 100644 index 0000000..b515f58 --- /dev/null +++ b/Ubiquitous/XiZi/board/stm32f103-nano/third_party_driver/uart/Makefile @@ -0,0 +1,3 @@ +SRC_FILES := connect_uart.c + +include $(KERNEL_ROOT)/compiler.mk diff --git a/Ubiquitous/XiZi/board/stm32f103-nano/third_party_driver/uart/connect_uart.c b/Ubiquitous/XiZi/board/stm32f103-nano/third_party_driver/uart/connect_uart.c new file mode 100644 index 0000000..456a065 --- /dev/null +++ b/Ubiquitous/XiZi/board/stm32f103-nano/third_party_driver/uart/connect_uart.c @@ -0,0 +1,427 @@ +/* +* Copyright (c) 2020 AIIT XUOS Lab +* XiUOS is licensed under Mulan PSL v2. +* You can use this software according to the terms and conditions of the Mulan PSL v2. +* You may obtain a copy of Mulan PSL v2 at: +* http://license.coscl.org.cn/MulanPSL2 +* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, +* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, +* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. +* See the Mulan PSL v2 for more details. +*/ + +/** +* @file connect_uart.c +* @brief support stm32f103_nano board uart function and register to bus framework +* @version 1.1 +* @author AIIT XUOS Lab +* @date 2021-11-25 +*/ + +#include +#include + +#ifdef BSP_USING_UART1 +static struct SerialBus serial_bus_1; +static struct SerialDriver serial_driver_1; +static struct SerialHardwareDevice serial_device_1; +#endif +#ifdef BSP_USING_UART2 +static struct SerialBus serial_bus_2; +static struct SerialDriver serial_driver_2; +static struct SerialHardwareDevice serial_device_2; +#endif + +static void SerialCfgParamCheck(struct SerialCfgParam *serial_cfg_default, struct SerialCfgParam *serial_cfg_new) +{ + struct SerialDataCfg *data_cfg_default = &serial_cfg_default->data_cfg; + struct SerialDataCfg *data_cfg_new = &serial_cfg_new->data_cfg; + + if ((data_cfg_default->serial_baud_rate != data_cfg_new->serial_baud_rate) && (data_cfg_new->serial_baud_rate)) { + data_cfg_default->serial_baud_rate = data_cfg_new->serial_baud_rate; + } + + if ((data_cfg_default->serial_bit_order != data_cfg_new->serial_bit_order) && (data_cfg_new->serial_bit_order)) { + data_cfg_default->serial_bit_order = data_cfg_new->serial_bit_order; + } + + if ((data_cfg_default->serial_buffer_size != data_cfg_new->serial_buffer_size) && (data_cfg_new->serial_buffer_size)) { + data_cfg_default->serial_buffer_size = data_cfg_new->serial_buffer_size; + } + + if ((data_cfg_default->serial_data_bits != data_cfg_new->serial_data_bits) && (data_cfg_new->serial_data_bits)) { + data_cfg_default->serial_data_bits = data_cfg_new->serial_data_bits; + } + + if ((data_cfg_default->serial_invert_mode != data_cfg_new->serial_invert_mode) && (data_cfg_new->serial_invert_mode)) { + data_cfg_default->serial_invert_mode = data_cfg_new->serial_invert_mode; + } + + if ((data_cfg_default->serial_parity_mode != data_cfg_new->serial_parity_mode) && (data_cfg_new->serial_parity_mode)) { + data_cfg_default->serial_parity_mode = data_cfg_new->serial_parity_mode; + } + + if ((data_cfg_default->serial_stop_bits != data_cfg_new->serial_stop_bits) && (data_cfg_new->serial_stop_bits)) { + data_cfg_default->serial_stop_bits = data_cfg_new->serial_stop_bits; + } +} + +static void UartHandler(struct SerialBus *serial_bus, struct SerialDriver *serial_drv) +{ + struct SerialHardwareDevice *serial_dev = (struct SerialHardwareDevice *)serial_bus->bus.owner_haldev; + struct SerialCfgParam *serial_cfg = (struct SerialCfgParam *)serial_drv->private_data; + struct Stm32UartHwCfg *serial_hw_cfg = (struct Stm32UartHwCfg *)serial_cfg->hw_cfg.private_data; + + /* UART in mode Receiver -------------------------------------------------*/ + if ((__HAL_UART_GET_FLAG(&(serial_hw_cfg->uart_handle), UART_FLAG_RXNE) != RESET) && + (__HAL_UART_GET_IT_SOURCE(&(serial_hw_cfg->uart_handle), UART_IT_RXNE) != RESET)) + { + SerialSetIsr(serial_dev, SERIAL_EVENT_RX_IND); + } + else + { + if (__HAL_UART_GET_FLAG(&(serial_hw_cfg->uart_handle), UART_FLAG_ORE) != RESET) + { + __HAL_UART_CLEAR_OREFLAG(&serial_hw_cfg->uart_handle); + } + if (__HAL_UART_GET_FLAG(&(serial_hw_cfg->uart_handle), UART_FLAG_NE) != RESET) + { + __HAL_UART_CLEAR_NEFLAG(&serial_hw_cfg->uart_handle); + } + if (__HAL_UART_GET_FLAG(&(serial_hw_cfg->uart_handle), UART_FLAG_FE) != RESET) + { + __HAL_UART_CLEAR_FEFLAG(&serial_hw_cfg->uart_handle); + } + if (__HAL_UART_GET_FLAG(&(serial_hw_cfg->uart_handle), UART_FLAG_PE) != RESET) + { + __HAL_UART_CLEAR_PEFLAG(&serial_hw_cfg->uart_handle); + } + } +} + +#ifdef BSP_USING_UART1 +void UartIsr1(int vector, void *param) +{ + /* get serial bus 1 */ + UartHandler(&serial_bus_1, &serial_driver_1); +} +#endif + +#ifdef BSP_USING_UART2 +void UartIsr2(int vector, void *param) +{ + /* get serial bus 2 */ + UartHandler(&serial_bus_2, &serial_driver_2); +} +#endif + +static uint32 SerialInit(struct SerialDriver *serial_drv, struct BusConfigureInfo *configure_info) +{ + NULL_PARAM_CHECK(serial_drv); + + struct SerialCfgParam *serial_cfg = (struct SerialCfgParam *)serial_drv->private_data; + struct Stm32UartHwCfg *serial_hw_cfg = (struct Stm32UartHwCfg *)serial_cfg->hw_cfg.private_data; + + if (configure_info->private_data) { + struct SerialCfgParam *serial_cfg_new = (struct SerialCfgParam *)configure_info->private_data; + SerialCfgParamCheck(serial_cfg, serial_cfg_new); + } + + serial_hw_cfg->uart_handle.Instance = serial_hw_cfg->uart_device; + serial_hw_cfg->uart_handle.Init.BaudRate = serial_cfg->data_cfg.serial_baud_rate; + serial_hw_cfg->uart_handle.Init.HwFlowCtl = UART_HWCONTROL_NONE; + serial_hw_cfg->uart_handle.Init.Mode = UART_MODE_TX_RX; + serial_hw_cfg->uart_handle.Init.OverSampling = UART_OVERSAMPLING_16; + + switch (serial_cfg->data_cfg.serial_data_bits) + { + case DATA_BITS_8: + if (serial_cfg->data_cfg.serial_parity_mode == PARITY_ODD || serial_cfg->data_cfg.serial_parity_mode == PARITY_EVEN) + serial_hw_cfg->uart_handle.Init.WordLength = UART_WORDLENGTH_9B; + else + serial_hw_cfg->uart_handle.Init.WordLength = UART_WORDLENGTH_8B; + break; + case DATA_BITS_9: + serial_hw_cfg->uart_handle.Init.WordLength = UART_WORDLENGTH_9B; + break; + default: + serial_hw_cfg->uart_handle.Init.WordLength = UART_WORDLENGTH_8B; + break; + } + + switch (serial_cfg->data_cfg.serial_stop_bits) + { + case STOP_BITS_1: + serial_hw_cfg->uart_handle.Init.StopBits = UART_STOPBITS_1; + break; + case STOP_BITS_2: + serial_hw_cfg->uart_handle.Init.StopBits = UART_STOPBITS_2; + break; + default: + serial_hw_cfg->uart_handle.Init.StopBits = UART_STOPBITS_1; + break; + } + + switch (serial_cfg->data_cfg.serial_parity_mode) + { + case PARITY_NONE: + serial_hw_cfg->uart_handle.Init.Parity = UART_PARITY_NONE; + break; + case PARITY_ODD: + serial_hw_cfg->uart_handle.Init.Parity = UART_PARITY_ODD; + break; + case PARITY_EVEN: + serial_hw_cfg->uart_handle.Init.Parity = UART_PARITY_EVEN; + break; + default: + serial_hw_cfg->uart_handle.Init.Parity = UART_PARITY_NONE; + break; + } + + if (HAL_UART_Init(&serial_hw_cfg->uart_handle) != HAL_OK) + { + return ERROR; + } + + return EOK; +} + +static uint32 SerialConfigure(struct SerialDriver *serial_drv, int serial_operation_cmd) +{ + NULL_PARAM_CHECK(serial_drv); + + struct SerialHardwareDevice *serial_dev = (struct SerialHardwareDevice *)serial_drv->driver.owner_bus->owner_haldev; + struct SerialCfgParam *serial_cfg = (struct SerialCfgParam *)serial_drv->private_data; + struct Stm32UartHwCfg *serial_hw_cfg = (struct Stm32UartHwCfg *)serial_cfg->hw_cfg.private_data; + struct SerialDevParam *serial_dev_param = (struct SerialDevParam *)serial_dev->haldev.private_data; + + if (OPER_CLR_INT == serial_operation_cmd) { + if (SIGN_OPER_INT_RX & serial_dev_param->serial_work_mode) { + /* disable rx irq */ + NVIC_DisableIRQ(serial_hw_cfg->irq_type); + /* disable interrupt */ + __HAL_UART_DISABLE_IT(&(serial_hw_cfg->uart_handle), UART_IT_RXNE); + } + } else if (OPER_SET_INT == serial_operation_cmd) { + /* enable rx irq */ + HAL_NVIC_SetPriority(serial_hw_cfg->irq_type, 1, 0); + HAL_NVIC_EnableIRQ(serial_hw_cfg->irq_type); + /* enable interrupt */ + __HAL_UART_ENABLE_IT(&(serial_hw_cfg->uart_handle), UART_IT_RXNE); + } + + return EOK; +} + +static uint32 SerialDrvConfigure(void *drv, struct BusConfigureInfo *configure_info) +{ + NULL_PARAM_CHECK(drv); + NULL_PARAM_CHECK(configure_info); + + x_err_t ret = EOK; + int serial_operation_cmd; + struct SerialDriver *serial_drv = (struct SerialDriver *)drv; + + switch (configure_info->configure_cmd) + { + case OPE_INT: + ret = SerialInit(serial_drv, configure_info); + break; + case OPE_CFG: + serial_operation_cmd = *(int *)configure_info->private_data; + ret = SerialConfigure(serial_drv, serial_operation_cmd); + break; + default: + break; + } + + return ret; +} + +static int SerialPutChar(struct SerialHardwareDevice *serial_dev, char c) +{ + struct SerialCfgParam *serial_cfg = (struct SerialCfgParam *)serial_dev->private_data; + struct Stm32UartHwCfg *serial_hw_cfg = (struct Stm32UartHwCfg *)serial_cfg->hw_cfg.private_data; + + UART_INSTANCE_CLEAR_FUNCTION(&(serial_hw_cfg->uart_handle), UART_FLAG_TC); + + serial_hw_cfg->uart_handle.Instance->DR = c; + while (__HAL_UART_GET_FLAG(&(serial_hw_cfg->uart_handle), UART_FLAG_TC) == RESET); + + return EOK; +} + +static int SerialGetChar(struct SerialHardwareDevice *serial_dev) +{ + struct SerialCfgParam *serial_cfg = (struct SerialCfgParam *)serial_dev->private_data; + struct Stm32UartHwCfg *serial_hw_cfg = (struct Stm32UartHwCfg *)serial_cfg->hw_cfg.private_data; + + int ch = -1; + if (__HAL_UART_GET_FLAG(&(serial_hw_cfg->uart_handle), UART_FLAG_RXNE) != RESET) + { + ch = serial_hw_cfg->uart_handle.Instance->DR & 0xff; + } + return ch; +} + +static const struct SerialDataCfg data_cfg_init = +{ + .serial_baud_rate = BAUD_RATE_115200, + .serial_data_bits = DATA_BITS_8, + .serial_stop_bits = STOP_BITS_1, + .serial_parity_mode = PARITY_NONE, + .serial_bit_order = BIT_ORDER_LSB, + .serial_invert_mode = NRZ_NORMAL, + .serial_buffer_size = SERIAL_RB_BUFSZ, +}; + +/*manage the serial device operations*/ +static const struct SerialDrvDone drv_done = +{ + .init = SerialInit, + .configure = SerialConfigure, +}; + +/*manage the serial device hal operations*/ +static struct SerialHwDevDone hwdev_done = +{ + .put_char = SerialPutChar, + .get_char = SerialGetChar, +}; + +static int BoardSerialBusInit(struct SerialBus *serial_bus, struct SerialDriver *serial_driver, const char *bus_name, const char *drv_name) +{ + x_err_t ret = EOK; + + /*Init the serial bus */ + ret = SerialBusInit(serial_bus, bus_name); + if (EOK != ret) { + KPrintf("InitHwUart SerialBusInit error %d\n", ret); + return ERROR; + } + + /*Init the serial driver*/ + ret = SerialDriverInit(serial_driver, drv_name); + if (EOK != ret) { + KPrintf("InitHwUart SerialDriverInit error %d\n", ret); + return ERROR; + } + + /*Attach the serial driver to the serial bus*/ + ret = SerialDriverAttachToBus(drv_name, bus_name); + if (EOK != ret) { + KPrintf("InitHwUart SerialDriverAttachToBus error %d\n", ret); + return ERROR; + } + + return ret; +} + +/*Attach the serial device to the serial bus*/ +static int BoardSerialDevBend(struct SerialHardwareDevice *serial_device, void *serial_param, const char *bus_name, const char *dev_name) +{ + x_err_t ret = EOK; + + ret = SerialDeviceRegister(serial_device, serial_param, dev_name); + if (EOK != ret) { + KPrintf("InitHwUart SerialDeviceInit device %s error %d\n", dev_name, ret); + return ERROR; + } + + ret = SerialDeviceAttachToBus(dev_name, bus_name); + if (EOK != ret) { + KPrintf("InitHwUart SerialDeviceAttachToBus device %s error %d\n", dev_name, ret); + return ERROR; + } + + return ret; +} + +int InitHwUart(void) +{ + x_err_t ret = EOK; + +#ifdef BSP_USING_UART1 + memset(&serial_bus_1, 0, sizeof(struct SerialBus)); + memset(&serial_driver_1, 0, sizeof(struct SerialDriver)); + memset(&serial_device_1, 0, sizeof(struct SerialHardwareDevice)); + + static struct SerialCfgParam serial_cfg_1; + memset(&serial_cfg_1, 0, sizeof(struct SerialCfgParam)); + + static struct Stm32UartHwCfg serial_hw_cfg_1; + memset(&serial_hw_cfg_1, 0, sizeof(struct Stm32UartHwCfg)); + + static struct SerialDevParam serial_dev_param_1; + memset(&serial_dev_param_1, 0, sizeof(struct SerialDevParam)); + + serial_driver_1.drv_done = &drv_done; + serial_driver_1.configure = &SerialDrvConfigure; + serial_device_1.hwdev_done = &hwdev_done; + + serial_cfg_1.data_cfg = data_cfg_init; + + serial_cfg_1.hw_cfg.private_data = (void *)&serial_hw_cfg_1; + serial_hw_cfg_1.uart_device = USART1; + serial_hw_cfg_1.irq_type = USART1_IRQn; + serial_driver_1.private_data = (void *)&serial_cfg_1; + + serial_dev_param_1.serial_work_mode = SIGN_OPER_INT_RX; + serial_device_1.haldev.private_data = (void *)&serial_dev_param_1; + + ret = BoardSerialBusInit(&serial_bus_1, &serial_driver_1, SERIAL_BUS_NAME_1, SERIAL_DRV_NAME_1); + if (EOK != ret) { + KPrintf("InitHwUart uarths error ret %u\n", ret); + return ERROR; + } + + ret = BoardSerialDevBend(&serial_device_1, (void *)&serial_cfg_1, SERIAL_BUS_NAME_1, SERIAL_1_DEVICE_NAME_0); + if (EOK != ret) { + KPrintf("InitHwUart uarths error ret %u\n", ret); + return ERROR; + } +#endif + +#ifdef BSP_USING_UART2 + memset(&serial_bus_2, 0, sizeof(struct SerialBus)); + memset(&serial_driver_2, 0, sizeof(struct SerialDriver)); + memset(&serial_device_2, 0, sizeof(struct SerialHardwareDevice)); + + static struct SerialCfgParam serial_cfg_2; + memset(&serial_cfg_2, 0, sizeof(struct SerialCfgParam)); + + static struct Stm32UartHwCfg serial_hw_cfg_2; + memset(&serial_hw_cfg_2, 0, sizeof(struct Stm32UartHwCfg)); + + static struct SerialDevParam serial_dev_param_2; + memset(&serial_dev_param_2, 0, sizeof(struct SerialDevParam)); + + serial_driver_2.drv_done = &drv_done; + serial_driver_2.configure = &SerialDrvConfigure; + serial_device_2.hwdev_done = &hwdev_done; + + serial_cfg_2.data_cfg = data_cfg_init; + + serial_cfg_2.hw_cfg.private_data = (void *)&serial_hw_cfg_2; + serial_hw_cfg_2.uart_device = USART2; + serial_hw_cfg_2.irq_type = USART2_IRQn; + serial_driver_2.private_data = (void *)&serial_cfg_2; + + serial_dev_param_2.serial_work_mode = SIGN_OPER_INT_RX; + serial_device_2.haldev.private_data = (void *)&serial_dev_param_2; + + ret = BoardSerialBusInit(&serial_bus_2, &serial_driver_2, SERIAL_BUS_NAME_2, SERIAL_DRV_NAME_2); + if (EOK != ret) { + KPrintf("InitHwUart uarths error ret %u\n", ret); + return ERROR; + } + + ret = BoardSerialDevBend(&serial_device_2, (void *)&serial_cfg_2, SERIAL_BUS_NAME_2, SERIAL_2_DEVICE_NAME_0); + if (EOK != ret) { + KPrintf("InitHwUart uarths error ret %u\n", ret); + return ERROR; + } +#endif + + return ret; +} diff --git a/Ubiquitous/XiZi/board/stm32f407-st-discovery/.defconfig b/Ubiquitous/XiZi/board/stm32f407-st-discovery/.defconfig new file mode 100644 index 0000000..215a59c --- /dev/null +++ b/Ubiquitous/XiZi/board/stm32f407-st-discovery/.defconfig @@ -0,0 +1,218 @@ +# +# Automatically generated file; DO NOT EDIT. +# XiZi Project Configuration +# +CONFIG_BOARD_STM32F407_EVB=y +CONFIG_KERNEL_CONSOLE_DEVICE_NAME="uart1" +CONFIG_ARCH_ARM=y + +# +# stm32f407-st-discovery feature +# +CONFIG_BSP_USING_DMA=y +CONFIG_BSP_USING_GPIO=y +# CONFIG_BSP_USING_I2C is not set +# CONFIG_BSP_USING_LCD is not set +# CONFIG_BSP_USING_EXTMEM is not set +# CONFIG_BSP_USING_SDIO is not set +# CONFIG_BSP_USING_RTC is not set +# CONFIG_BSP_USING_SPI is not set +# CONFIG_BSP_USING_HWTIMER is not set +CONFIG_BSP_USING_WDT=y +CONFIG_BSP_USING_UART=y +CONFIG_BSP_USING_UART1=y +CONFIG_BSP_USING_UART2=y +CONFIG_BSP_USING_UART3=y +# CONFIG_BSP_USING_UART4 is not set +# CONFIG_BSP_USING_UART5 is not set +#CONFIG_BSP_USING_USB is not set +#CONFIG_BSP_USING_STM32_USBH is not set + +# +# Hardware feature +# +CONFIG_RESOURCES_SERIAL=y +CONFIG_SERIAL_USING_DMA=y +# CONFIG_SERIAL_RB_BUFSZ is not set +# CONFIG_RESOURCES_CAN is not set +# CONFIG_RESOURCES_HWTIMER is not set +# CONFIG_RESOURCES_I2C is not set +# CONFIG_RESOURCES_LCD is not set +# CONFIG_RESOURCES_SDIO is not set +# CONFIG_RESOURCES_TOUCH is not set +CONFIG_RESOURCES_PIN=y +# CONFIG_RESOURCES_RTC is not set +# CONFIG_RESOURCES_SPI is not set +# CONFIG_RESOURCES_SPI_SD is not set +# CONFIG_RESOURCES_SPI_SFUD is not set +# SFUD_USING_SFDP is not set +# SFUD_USING_FLASH_INFO_TABLE is not set +# SFUD_DEBUG_LOG is not set +CONFIG_RESOURCES_WDT=y +# CONFIG_RESOURCES_USB is not set +# CONFIG_RESOURCES_USB_HOST is not set +# CONFIG_UDISK_MOUNTPOINT is not set +# CONFIG_USBH_MSTORAGE is not set +#CONFIG_RESOURCES_USB_DEVICE is not set +# CONFIG_USBD_THREAD_STACK_SZ is not set + +# +# Kernel feature +# +# CONFIG_SEPARATE_COMPILE is not set +# CONFIG_COMPILER_APP is not set +# CONFIG_COMPILER_KERNEL is not set +# +# Kernel Device Object +# +CONFIG_KERNEL_DEVICE=y +CONFIG_KERNEL_CONSOLE=y +CONFIG_KERNEL_CONSOLEBUF_SIZE=128 + +# +# Task feature +# +CONFIG_SCHED_POLICY_RR_REMAINSLICE=y +# CONFIG_SCHED_POLICY_RR is not set +# CONFIG_SCHED_POLICY_FIFO is not set + +# +# Inter-Task communication +# +CONFIG_KERNEL_SEMAPHORE=y +CONFIG_KERNEL_MUTEX=y +CONFIG_KERNEL_EVENT=y +CONFIG_KERNEL_MESSAGEQUEUE=y +# CONFIG_KTASK_PRIORITY_8 is not set +CONFIG_KTASK_PRIORITY_32=y +# CONFIG_KTASK_PRIORITY_256 is not set +CONFIG_KTASK_PRIORITY_MAX=32 +CONFIG_TICK_PER_SECOND=1000 +CONFIG_KERNEL_STACK_OVERFLOW_CHECK=y +CONFIG_KERNEL_BANNER=y +# CONFIG_KERNEL_HOOK is not set +CONFIG_KERNEL_SOFTTIMER=y +CONFIG_KERNEL_IDLE_HOOK=y +CONFIG_IDEL_HOOK_LIST_SIZE=4 +CONFIG_IDLE_KTASK_STACKSIZE=256 +CONFIG_USER_APPLICATION=y +# CONFIG_TASK_ISOLATION is not set + +# +# Memory Management +# +# CONFIG_KERNEL_MEMBLOCK is not set + +# +# Command shell +# +CONFIG_TOOL_SHELL=y +CONFIG_SHELL_ENTER_CR=y +CONFIG_SHELL_ENTER_LF=y +CONFIG_SHELL_ENTER_CR_AND_LF=y +# CONFIG_SHELL_ENTER_CRLF is not set + +# +# User Control +# +CONFIG_SHELL_DEFAULT_USER="letter" +CONFIG_SHELL_DEFAULT_USER_PASSWORD="" +CONFIG_SHELL_LOCK_TIMEOUT=10000 +CONFIG_SHELL_TASK_STACK_SIZE=4096 +CONFIG_SHELL_TASK_PRIORITY=20 +CONFIG_SHELL_MAX_NUMBER=5 +CONFIG_SHELL_PARAMETER_MAX_NUMBER=8 +CONFIG_SHELL_HISTORY_MAX_NUMBER=5 +CONFIG_SHELL_PRINT_BUFFER=128 +CONFIG_SHELL_USING_CMD_EXPORT=y +CONFIG_SHELL_HELP_SHOW_PERMISSION=y +# CONFIG_SHELL_HELP_LIST_USER is not set +# CONFIG_SHELL_HELP_LIST_VAR is not set +# CONFIG_SHELL_HELP_LIST_KEY is not set +CONFIG_KERNEL_QUEUEMANAGE=y +CONFIG_KERNEL_WORKQUEUE=y +CONFIG_WORKQUEUE_KTASK_STACKSIZE=512 +CONFIG_WORKQUEUE_KTASK_PRIORITY=23 +CONFIG_KERNEL_WAITQUEUE=y +CONFIG_KERNEL_DATAQUEUE=y +# CONFIG_KERNEL_CIRCULAR_AREA is not set +# CONFIG_KERNEL_AVL_TREE is not set +CONFIG_NAME_MAX=8 +CONFIG_ALIGN_SIZE=4 +CONFIG_KERNEL_COMPONENTS_INIT=y +CONFIG_KERNEL_USER_MAIN=y +CONFIG_MAIN_KTASK_STACK_SIZE=2048 +CONFIG_ENV_INIT_KTASK_STACK_SIZE=8192 +CONFIG_MAIN_KTASK_PRIORITY=10 +# CONFIG_USER_TEST is not set +# CONFIG_TOOL_TEST_SEM is not set +# CONFIG_TOOL_TEST_MUTEX is not set +# CONFIG_TOOL_TEST_EVENT is not set +# CONFIG_TOOL_TEST_MSG is not set +# CONFIG_TOOL_TEST_AVLTREE is not set +# CONFIG_TEST_CRICULAR_AREA is not set +# CONFIG_TOOL_TEST_MEM is not set +# CONFIG_TOOL_TEST_TIMER is not set +# CONFIG_TOOL_TEST_IWG is not set +# CONFIG_TOOL_TEST_REALTIME is not set +# CONFIG_TOOL_TEST_DBG is not set +# CONFIG_TOOL_TEST_SCHED is not set +# CONFIG_KERNEL_DEBUG is not set +CONFIG_DEBUG_INIT_CONFIG=y +CONFIG_DBG_INIT=1 +# CONFIG_ARCH_SMP is not set + +# +# File system +# +CONFIG_FS_VFS=y +CONFIG_VFS_USING_WORKDIR=y +CONFIG_FS_VFS_DEVFS=y + +# +# Fat filesystem +# + +# +# IOT-Device File system +# + +# +# Lwext4 filesystem +# + +# +# APP Framework +# + +# +# connection +# +# CONFIG_CONNECTION_AT is not set +# CONFIG_CONNECTION_MQTT is not set + +# +# medium communication +# + + +# +# Intelligence +# + +# +# Control +# + +# +# Lib +# +CONFIG_LIB=y +CONFIG_LIB_POSIX=y +CONFIG_LIB_NEWLIB=y + +CONFIG_LITTLEVGL2RTT_USING_DEMO=y + +# +# Security +# diff --git a/Ubiquitous/XiZi/board/stm32f407-st-discovery/Kconfig b/Ubiquitous/XiZi/board/stm32f407-st-discovery/Kconfig new file mode 100644 index 0000000..3ce31dd --- /dev/null +++ b/Ubiquitous/XiZi/board/stm32f407-st-discovery/Kconfig @@ -0,0 +1,59 @@ +mainmenu "XiZi Project Configuration" + +config BSP_DIR + string + option env="BSP_ROOT" + default "." + +config KERNEL_DIR + string + option env="KERNEL_ROOT" + default "../.." + +config BOARD_STM32F407_EVB + bool + select ARCH_ARM + default y + +source "$KERNEL_DIR/arch/Kconfig" + +menu "stm32f407-st-discovery feature" + source "$BSP_DIR/third_party_driver/Kconfig" + + menu "config default board resources" + menu "config board app name" + config BOARD_APP_NAME + string "config board app name" + default "/XiUOS_stm32f407-st-discovery_app.bin" + endmenu + + menu "config board service table" + config SERVICE_TABLE_ADDRESS + hex "board service table address" + default 0x20000000 + endmenu + + menu "config hardware resources for connection" + if CONNECTION_COMMUNICATION_ETHERNET + config ETHERNET_UART_NAME + string "ethernet uart name" + default "/dev/usart3_dev3" + endif + if CONNECTION_COMMUNICATION_WIFI + config WIFI_UART_NAME + string "wifi uart name" + default "/dev/usart3_dev3" + endif + + endmenu + + endmenu + +endmenu + + +menu "Hardware feature" +source "$KERNEL_DIR/resources/Kconfig" +endmenu + +source "$KERNEL_DIR/Kconfig" diff --git a/Ubiquitous/XiZi/board/stm32f407-st-discovery/Makefile b/Ubiquitous/XiZi/board/stm32f407-st-discovery/Makefile new file mode 100644 index 0000000..683e42a --- /dev/null +++ b/Ubiquitous/XiZi/board/stm32f407-st-discovery/Makefile @@ -0,0 +1,8 @@ +SRC_FILES := board.c + +SRC_DIR := third_party_driver + + + + +include $(KERNEL_ROOT)/compiler.mk \ No newline at end of file diff --git a/Ubiquitous/XiZi/board/stm32f407-st-discovery/README.md b/Ubiquitous/XiZi/board/stm32f407-st-discovery/README.md new file mode 100644 index 0000000..dca0647 --- /dev/null +++ b/Ubiquitous/XiZi/board/stm32f407-st-discovery/README.md @@ -0,0 +1,221 @@ +# 从零开始构建矽璓工业物联操作系统：使用ARM架构的STM32F407-discovery开发板 + +[XiUOS](http://xuos.io/) (X Industrial Ubiquitous Operating System) 矽璓工业物联操作系统是一款面向工业物联场景的泛在操作系统，来自泛在操作系统研究计划。所谓泛在操作系统(UOS: Ubiquitous Operating Systems)，是支持互联网时代人机物融合泛在计算应用模式的新型操作系统，是传统操作系统概念的泛化与延伸。在泛在操作系统技术体系中，不同的泛在计算设备和泛在应用场景需要符合各自特性的不同UOS，XiUOS即是面向工业物联场景的一种UOS，主要由一个极简的微型实时操作系统(RTOS)内核和其上的智能工业物联框架构成，支持工业物联网(IIoT: Industrial Internet of Things)应用。 + +>注：最新版README请访问[从零开始构建矽璓工业物联操作系统：使用ARM架构的STM32F407-discovery开发板](https://blog.csdn.net/AIIT_Ubiquitous/article/details/116209686)，如博客内容与本地文档有差异，以网站内容为准。 + +## 开发环境搭建 + +### 推荐使用： + +**操作系统：** ubuntu18.04 [https://ubuntu.com/download/desktop](https://ubuntu.com/download/desktop) + +更新`ubuntu 18.04`源的方法:（根据自身情况而定，可以不更改） + +第一步:打开sources.list文件 + +```c +sudo vim /etc/apt/sources.list +``` + +第二步:将以下内容复制到sources.list文件 + +```c +deb http://mirrors.aliyun.com/ubuntu/ bionic main restricted universe multiverse +deb http://mirrors.aliyun.com/ubuntu/ bionic-security main restricted universe multiverse +deb http://mirrors.aliyun.com/ubuntu/ bionic-updates main restricted universe multiverse +deb http://mirrors.aliyun.com/ubuntu/ bionic-proposed main restricted universe multiverse +deb http://mirrors.aliyun.com/ubuntu/ bionic-backports main restricted universe multiverse +deb-src http://mirrors.aliyun.com/ubuntu/ bionic main restricted universe multiverse +deb-src http://mirrors.aliyun.com/ubuntu/ bionic-security main restricted universe multiverse +deb-src http://mirrors.aliyun.com/ubuntu/ bionic-updates main restricted universe multiverse +deb-src http://mirrors.aliyun.com/ubuntu/ bionic-proposed main restricted universe multiverse +deb-src http://mirrors.aliyun.com/ubuntu/ bionic-backports main restricted universe multiverse +``` + +第三步:更新源和系统软件 + +```c +sudo apt-get update +sudo apt-get upgrade +``` + +**开发工具推荐使用 VSCode ，VScode下载地址为：** VSCode [https://code.visualstudio.com/](https://code.visualstudio.com/)，推荐下载地址为 [http://vscode.cdn.azure.cn/stable/3c4e3df9e89829dce27b7b5c24508306b151f30d/code_1.55.2-1618307277_amd64.deb](http://vscode.cdn.azure.cn/stable/3c4e3df9e89829dce27b7b5c24508306b151f30d/code_1.55.2-1618307277_amd64.deb) + +### 依赖包安装： + +``` +$ sudo apt install build-essential pkg-config git +$ sudo apt install gcc make libncurses5-dev openssl libssl-dev bison flex libelf-dev autoconf libtool gperf libc6-dev +``` + +**XiUOS操作系统源码下载：** XiUOS [https://www.gitlink.org.cn/xuos/xiuos](https://www.gitlink.org.cn/xuos/xiuos) + +新建一个空文件夹并进入文件夹中，并下载源码，具体命令如下： + +```c +mkdir test && cd test +git clone https://gitlink.org.cn/xuos/xiuos.git +``` + +1、打开XiUOS源码文件包可以看到以下目录： +| 名称 | 说明 | +| -- | -- | +| APP_Framework | 应用代码 | +| Ubiquitous | 板级支持包,支持NuttX、RT-Thread和XiZi内核 | + +2、打开XiZi内核源码文件包可以看到以下目录： +| 名称 | 说明 | +| -- | -- | +| arch | 架构代码 | +| board | 板级支持包 | +| fs | 文件系统 | +| kernel | 内核源码 | +| lib | 第三方库源码 | +| resources | 驱动文件 | +| tool | 系统工具 | + +使用VScode打开代码，具体操作步骤为：在源码文件夹下打开系统终端，输入`code .`即可打开VScode开发环境，如下图所示： + +
+ +
+ +### 裁减配置工具的下载 + +裁减配置工具： + +**工具地址：** kconfig-frontends [https://www.gitlink.org.cn/xuos/kconfig-frontends](https://www.gitlink.org.cn/xuos/kconfig-frontends)，下载与安装的具体命令如下： + +```c +mkdir kfrontends && cd kfrontends +git clone https://gitlink.org.cn/xuos/kconfig-frontends.git +``` + +下载源码后按以下步骤执行软件安装： + +```c +cd kconfig-frontends +./xs_build.sh +``` + +### 编译工具链： + +ARM： arm-none-eabi(`gcc version 6.3.1`)，默认安装到Ubuntu的/usr/bin/arm-none-eabi-，使用如下命令行下载和安装。 + +```shell +$ sudo apt install gcc-arm-none-eabi +``` + +# 在STM32F407-DISCOVERY上创建第一个应用 --helloworld + +## 1. 简介 + +| 硬件 | 描述 | +| -- | -- | +|芯片型号| Stm32F407VGT6| +|CPU|arm cortex-m| +|主频| 168MHz | +|片内SRAM| 192KB | +|片上FLASH| 1MB | +| 外设 | -- | +| | ADC、DAC、USB、GPIO、UART、SPI、SDIO、RTC、CAN、DMA、MAC、I²C、WDT、Timer等 | + +XiUOS板级驱动当前支持使用GPIO、I2C、LCD、USB、RTC、SPI、Timer、UART和WDT等。 + +## 2. 编译说明 + +### 编辑环境：`Ubuntu18.04` + +### 编译工具链：`arm-none-eabi-gcc` +使用`VScode`打开工程的方法有多种，本文介绍一种快捷键，在项目目录下将`code .`输入linux系统命令终端即可打开目标项目 + +修改`APP_Framework/Applications`文件夹下`main.c` +在输出函数中写入 `Hello, world!!! \n Running on stm32f407-st-discovery`完成代码编辑。 + +![main](img/main.png) + +编译步骤： + +1.在VScode命令终端中执行以下命令，生成配置文件 + +```c +cd ./Ubiquitous/XiZi +make BOARD=stm32f407-st-discovery distclean +make BOARD=stm32f407-st-discovery menuconfig +``` + +2.在menuconfig界面配置需要关闭和开启的功能，按回车键进入下级菜单，按Y键选中需要开启的功能，按N键选中需要关闭的功能，配置结束后保存并退出（本例旨在演示简单的输出例程，所以没有需要配置的选项，双击快捷键ESC退出配置） + +![menuconfig1](img/menuconfig1.png) + +退出时选择`yes`保存上面所配置的内容，如下图所示： + +![menuconfig2](img/menuconfig2.jpg) + +3.继续执行以下命令，进行编译 + +```c +make BOARD=stm32f407-st-discovery +``` + +4.如果编译正确无误，会产生XiZi_stm32f407-st-discovery.elf、XiZi_stm32f407-st-discovery.bin文件。其中XiZi_stm32f407-st-discovery.bin需要烧写到设备中进行运行。 + +## 3. 烧写及执行 + +将 BOARD=stm32f407-st-discovery开发板SWD经 st-link 转接到USB接口，然后使用st-flash工具进行烧写bin文件。 + +![stm32f407-st-discovery](img/stm32f407-st-discovery.png) + +### 烧写工具 + +ARM：ST-LINK（ST-LINK V2实物如图，可在购物网站搜索关键字购买） + +![st-link](img/st-link.png) + +下载并以下执行命令以下命令安装st-link工具(本文使用v1.5.1版本)，下载地址为：[http://101.36.126.201:8011/stlink.zip](http://101.36.126.201:8011/stlink.zip) + +``` +sudo apt install libusb-dev +sudo apt install libusb-1.0-0-dev +sudo apt install cmake +cd stlink +make +cd build/Release && make install DESTDIR=_install +``` + +将生成的st-flash（在stlink/build/Release/bin文件夹下）复制到/usr/bin下就可使用了 + +代码根目录下执行st-flash工具烧录 + +``` +sudo st-flash write build/XiZi_stm32f407-st-discovery.bin 0x8000000 +``` + +此外，推荐用户使用putty作为终端工具，安装命令如下： + +```c +sudo apt install putty +``` + +打开putty配置串口信息 + +```c +sudo puty +``` + +选择ttyUSB0（这个端口号根据具体情况而定），配置波特率为115200。 + +![putty](img/putty.png) + +注意：选择正确的终端端口号，最后可以执行以下命令，清除配置文件和编译生成的文件 + +```c +make BOARD=stm32f407-st-discovery distclean +``` + +### 3.1 运行结果 + +如果编译 & 烧写无误，将会在串口终端上看到信息打印输出，(终端串口引脚为PB6、PB7)。 + +![terminal](img/terminal.png) diff --git a/Ubiquitous/XiZi/board/stm32f407-st-discovery/board.c b/Ubiquitous/XiZi/board/stm32f407-st-discovery/board.c new file mode 100644 index 0000000..491e612 --- /dev/null +++ b/Ubiquitous/XiZi/board/stm32f407-st-discovery/board.c @@ -0,0 +1,180 @@ +/* +* Copyright (c) 2020 AIIT XUOS Lab +* XiUOS is licensed under Mulan PSL v2. +* You can use this software according to the terms and conditions of the Mulan PSL v2. +* You may obtain a copy of Mulan PSL v2 at: +* http://license.coscl.org.cn/MulanPSL2 +* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, +* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, +* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. +* See the Mulan PSL v2 for more details. +*/ + +/** +* @file board.c +* @brief support stm32f407-st-discovery-board init configure and start-up +* @version 1.0 +* @author AIIT XUOS Lab +* @date 2021-04-25 +*/ + +/************************************************* +File name: board.c +Description: support stm32f407-st-discovery-board init configure and driver/task/... init +Others: +History: +1. Date: 2021-04-25 +Author: AIIT XUOS Lab +Modification: +1. support stm32f407-st-discovery-board InitBoardHardware +*************************************************/ + +#include +#include "stm32f4xx.h" +#include "hardware_rcc.h" +#include "board.h" +#include "connect_usart.h" +#include "connect_gpio.h" +#include "misc.h" +#include "connect_hwtimer.h" +#include + +extern void entry(void); +extern int Stm32HwPinInit(void); +extern int Stm32HwTimerInit(void); +extern int Stm32HwSpiInit(void); +extern int HwWdtInit(void); +extern int Stm32HwI2cInit(void); +extern int Stm32HwUsartInit(); +extern int Stm32HwRtcInit(); +extern int HwSdioInit(); +extern int Stm32HwAdcInit(void); +extern int Stm32HwDacInit(void); + +static void ClockConfiguration() +{ + int cr,cfgr,pllcfgr; + int cr1,cfgr1,pllcfgr1; + RCC->APB1ENR |= RCC_APB1ENR_PWREN; + PWR->CR |= PWR_CR_VOS; + RCC_HSEConfig(RCC_HSE_ON); + if (RCC_WaitForHSEStartUp() == SUCCESS) + { + RCC_HCLKConfig(RCC_SYSCLK_Div1); + RCC_PCLK2Config(RCC_HCLK_Div2); + RCC_PCLK1Config(RCC_HCLK_Div4); + RCC_PLLConfig(RCC_PLLSource_HSE, 8, 336, 2, 7); + + RCC_PLLCmd(ENABLE); + while (RCC_GetFlagStatus(RCC_FLAG_PLLRDY) == RESET); + + FLASH->ACR = FLASH_ACR_ICEN |FLASH_ACR_DCEN |FLASH_ACR_LATENCY_5WS; + RCC_SYSCLKConfig(RCC_SYSCLKSource_PLLCLK); + + while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS ) != RCC_CFGR_SWS_PLL); + } + SystemCoreClockUpdate(); +} + +void NVIC_Configuration(void) +{ +#ifdef VECT_TAB_RAM + NVIC_SetVectorTable(NVIC_VectTab_RAM, 0x0); +#else + NVIC_SetVectorTable(NVIC_VectTab_FLASH, 0x0); +#endif + + NVIC_PriorityGroupConfig(NVIC_PriorityGroup_2); +} + +void SysTickConfiguration(void) +{ + RCC_ClocksTypeDef rcc_clocks; + uint32 cnts; + + RCC_GetClocksFreq(&rcc_clocks); + + cnts = (uint32)rcc_clocks.HCLK_Frequency / TICK_PER_SECOND; + cnts = cnts / 8; + + SysTick_Config(cnts); + SysTick_CLKSourceConfig(SysTick_CLKSource_HCLK_Div8); +} + +void SysTick_Handler(int irqn, void *arg) +{ + + TickAndTaskTimesliceUpdate(); + +} +DECLARE_HW_IRQ(SysTick_IRQn, SysTick_Handler, NONE); + +void stm32f407_start() +{ + entry(); +} +struct InitSequenceDesc _board_init[] = +{ +#ifdef BSP_USING_GPIO + { "hw pin", Stm32HwGpioInit }, +#endif +#ifdef BSP_USING_HWTIMER + { "hw timer", Stm32HwTimerInit }, +#endif +#ifdef BSP_USING_SPI + { "hw spi", Stm32HwSpiInit }, +#endif +#ifdef BSP_USING_WDT + { "hw wdg", HwWdtInit }, +#endif +#ifdef BSP_USING_I2C + { "hw i2c", Stm32HwI2cInit }, +#endif +#ifdef BSP_USING_RTC + { "hw rtc", Stm32HwRtcInit}, +#endif +#ifdef BSP_USING_SDIO + {"hw sdcard init", HwSdioInit}, +#endif +#ifdef BSP_USING_ADC + {"hw adc init", Stm32HwAdcInit}, +#endif +#ifdef BSP_USING_DAC + {"hw dac init", Stm32HwDacInit}, +#endif + { " NONE ",NONE }, +}; +void InitBoardHardware() +{ + int i = 0; + int ret = 0; + ClockConfiguration(); + + NVIC_Configuration(); + + SysTickConfiguration(); +#ifdef BSP_USING_UART + Stm32HwUsartInit(); +#endif + + InitBoardMemory((void*)MEMORY_START_ADDRESS, (void*)MEMORY_END_ADDRESS); + +#ifdef KERNEL_CONSOLE + InstallConsole(KERNEL_CONSOLE_BUS_NAME, KERNEL_CONSOLE_DRV_NAME, KERNEL_CONSOLE_DEVICE_NAME); + + RCC_ClocksTypeDef rcc_clocks; + RCC_GetClocksFreq(&rcc_clocks); + KPrintf("HCLK_Frequency %d, PCLK1_Frequency %d, PCLK2_Frequency %d, SYSCLK_Frequency %d\n", rcc_clocks.HCLK_Frequency, rcc_clocks.PCLK1_Frequency, rcc_clocks.PCLK2_Frequency, rcc_clocks.SYSCLK_Frequency); + + KPrintf("\nconsole init completed.\n"); + KPrintf("board initialization......\n"); +#endif + + for(i = 0; _board_init[i].fn != NONE; i++) { + ret = _board_init[i].fn(); + KPrintf("initialize %s %s\n",_board_init[i].fn_name, ret == 0 ? "success" : "failed"); + } + + KPrintf("board init done.\n"); + KPrintf("start kernel...\n"); +} diff --git a/Ubiquitous/XiZi/board/stm32f407-st-discovery/board.h b/Ubiquitous/XiZi/board/stm32f407-st-discovery/board.h new file mode 100644 index 0000000..c79e601 --- /dev/null +++ b/Ubiquitous/XiZi/board/stm32f407-st-discovery/board.h @@ -0,0 +1,91 @@ +/* +* Copyright (c) 2020 AIIT XUOS Lab +* XiUOS is licensed under Mulan PSL v2. +* You can use this software according to the terms and conditions of the Mulan PSL v2. +* You may obtain a copy of Mulan PSL v2 at: +* http://license.coscl.org.cn/MulanPSL2 +* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, +* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, +* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. +* See the Mulan PSL v2 for more details. +*/ + +/** +* @file board.h +* @brief define stm32f407-st-discovery-board init configure and start-up function +* @version 1.0 +* @author AIIT XUOS Lab +* @date 2021-04-25 +*/ + +/************************************************* +File name: board.h +Description: define stm32f407-st-discovery-board board init function and struct +Others: +History: +1. Date: 2021-04-25 +Author: AIIT XUOS Lab +Modification: +1. define stm32f407-st-discovery-board InitBoardHardware +2. define stm32f407-st-discovery-board data and bss struct +*************************************************/ + +#ifndef BOARD_H +#define BOARD_H + +#include +#include + +extern int __stack_end__; +extern unsigned int g_service_table_start; +extern unsigned int g_service_table_end; + +#define STM32_USE_SDIO 0 + +#define STM32_EXT_SRAM 0 +#define STM32_EXT_SRAM_BEGIN 0x68000000 +#define STM32_EXT_SRAM_END 0x68080000 + +#define SURPORT_MPU + +#ifdef __ICCARM__ +extern char __ICFEDIT_region_RAM_end__; +#define STM32_SRAM_END &__ICFEDIT_region_RAM_end__ +#else + +#define MEMORY_START_ADDRESS (&__stack_end__) +#define STM32_SRAM_SIZE 128 +#define MEMORY_END_ADDRESS (0x20000000 + STM32_SRAM_SIZE * 1024) + +#ifdef SEPARATE_COMPILE +typedef int (*main_t)(int argc, char *argv[]); +typedef void (*exit_t)(void); +struct userspace_s +{ + main_t us_entrypoint; + exit_t us_taskquit; + uintptr_t us_textstart; + uintptr_t us_textend; + uintptr_t us_datasource; + uintptr_t us_datastart; + uintptr_t us_dataend; + uintptr_t us_bssstart; + uintptr_t us_bssend; + uintptr_t us_heapend; +}; +#define USERSPACE (( struct userspace_s *)(0x08080000)) + +#ifndef SERVICE_TABLE_ADDRESS +#define SERVICE_TABLE_ADDRESS (0x20000000) +#endif + +#define USER_SRAM_SIZE 64 +#define USER_MEMORY_START_ADDRESS (USERSPACE->us_bssend) +#define USER_MEMORY_END_ADDRESS (0x10000000 + USER_SRAM_SIZE * 1024) +#endif +#endif + +void InitBoardHardware(void); +void stm32f407_start(void); + +#endif \ No newline at end of file diff --git a/Ubiquitous/XiZi/board/stm32f407-st-discovery/config.mk b/Ubiquitous/XiZi/board/stm32f407-st-discovery/config.mk new file mode 100644 index 0000000..fc9af77 --- /dev/null +++ b/Ubiquitous/XiZi/board/stm32f407-st-discovery/config.mk @@ -0,0 +1,17 @@ +export CROSS_COMPILE ?=/usr/bin/arm-none-eabi- + +export CFLAGS := -mcpu=cortex-m4 -mthumb -mfpu=fpv4-sp-d16 -mfloat-abi=hard -ffunction-sections -fdata-sections -Dgcc -O0 -gdwarf-2 -g -fgnu89-inline -Wa,-mimplicit-it=thumb -Werror +export AFLAGS := -c -mcpu=cortex-m4 -mthumb -mfpu=fpv4-sp-d16 -mfloat-abi=hard -ffunction-sections -fdata-sections -x assembler-with-cpp -Wa,-mimplicit-it=thumb -gdwarf-2 +export LFLAGS := -mcpu=cortex-m4 -mthumb -mfpu=fpv4-sp-d16 -mfloat-abi=hard -ffunction-sections -fdata-sections -Wl,--gc-sections,-Map=XiZi_stm32f407-st-discovery.map,-cref,-u,Reset_Handler -T $(BSP_ROOT)/link.lds +export CXXFLAGS := -mcpu=cortex-m4 -mthumb -mfpu=fpv4-sp-d16 -mfloat-abi=hard -ffunction-sections -fdata-sections -Dgcc -O0 -gdwarf-2 -g -Werror + +export APPLFLAGS := -mcpu=cortex-m4 -mthumb -mfpu=fpv4-sp-d16 -mfloat-abi=hard -ffunction-sections -fdata-sections -Wl,--gc-sections,-Map=XiZi_app.map,-cref,-u, -T $(BSP_ROOT)/link_userspace.lds + + +export DEFINES := -DHAVE_CCONFIG_H -DSTM32F407xx -DUSE_HAL_DRIVER -DHAVE_SIGINFO + +export USING_NEWLIB =1 +export USING_VFS = 1 +export USING_SPI = 1 +export ARCH = arm +export USING_LORA = 1 diff --git a/Ubiquitous/XiZi/board/stm32f407-st-discovery/img/main.png b/Ubiquitous/XiZi/board/stm32f407-st-discovery/img/main.png new file mode 100644 index 0000000..d19d92c Binary files /dev/null and b/Ubiquitous/XiZi/board/stm32f407-st-discovery/img/main.png differ diff --git a/Ubiquitous/XiZi/board/stm32f407-st-discovery/img/menuconfig1.png b/Ubiquitous/XiZi/board/stm32f407-st-discovery/img/menuconfig1.png new file mode 100644 index 0000000..d150ebc Binary files /dev/null and b/Ubiquitous/XiZi/board/stm32f407-st-discovery/img/menuconfig1.png differ diff --git a/Ubiquitous/XiZi/board/stm32f407-st-discovery/img/menuconfig2.jpg b/Ubiquitous/XiZi/board/stm32f407-st-discovery/img/menuconfig2.jpg new file mode 100644 index 0000000..e5529e4 Binary files /dev/null and b/Ubiquitous/XiZi/board/stm32f407-st-discovery/img/menuconfig2.jpg differ diff --git a/Ubiquitous/XiZi/board/stm32f407-st-discovery/img/putty.png b/Ubiquitous/XiZi/board/stm32f407-st-discovery/img/putty.png new file mode 100644 index 0000000..3acd6c8 Binary files /dev/null and b/Ubiquitous/XiZi/board/stm32f407-st-discovery/img/putty.png differ diff --git a/Ubiquitous/XiZi/board/stm32f407-st-discovery/img/st-link.png b/Ubiquitous/XiZi/board/stm32f407-st-discovery/img/st-link.png new file mode 100644 index 0000000..4284399 Binary files /dev/null and b/Ubiquitous/XiZi/board/stm32f407-st-discovery/img/st-link.png differ diff --git a/Ubiquitous/XiZi/board/stm32f407-st-discovery/img/stm32f407-st-discovery.png b/Ubiquitous/XiZi/board/stm32f407-st-discovery/img/stm32f407-st-discovery.png new file mode 100644 index 0000000..473bf77 Binary files /dev/null and b/Ubiquitous/XiZi/board/stm32f407-st-discovery/img/stm32f407-st-discovery.png differ diff --git a/Ubiquitous/XiZi/board/stm32f407-st-discovery/img/terminal.png b/Ubiquitous/XiZi/board/stm32f407-st-discovery/img/terminal.png new file mode 100644 index 0000000..a1bd89a Binary files /dev/null and b/Ubiquitous/XiZi/board/stm32f407-st-discovery/img/terminal.png differ diff --git a/Ubiquitous/XiZi/board/stm32f407-st-discovery/img/vscode.jpg b/Ubiquitous/XiZi/board/stm32f407-st-discovery/img/vscode.jpg new file mode 100644 index 0000000..b9bacff Binary files /dev/null and b/Ubiquitous/XiZi/board/stm32f407-st-discovery/img/vscode.jpg differ diff --git a/Ubiquitous/XiZi/board/stm32f407-st-discovery/link.lds b/Ubiquitous/XiZi/board/stm32f407-st-discovery/link.lds new file mode 100644 index 0000000..b329954 --- /dev/null +++ b/Ubiquitous/XiZi/board/stm32f407-st-discovery/link.lds @@ -0,0 +1,109 @@ +/* +* Copyright (c) 2020 AIIT XUOS Lab +* XiUOS is licensed under Mulan PSL v2. +* You can use this software according to the terms and conditions of the Mulan PSL v2. +* You may obtain a copy of Mulan PSL v2 at: +* http://license.coscl.org.cn/MulanPSL2 +* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, +* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, +* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. +* See the Mulan PSL v2 for more details. +*/ + +__SYSTEM_STACKSIZE__ = 0x400; + +OUTPUT_ARCH(arm) + +MEMORY +{ + flash (rx) : ORIGIN = 0x08000000, LENGTH = 512k /* 512KB flash */ + sram (rw) : ORIGIN = 0x20001000, LENGTH = 124k /* 124k sram */ +} + +ENTRY(Reset_Handler) +SECTIONS +{ + .text : + { + . = ALIGN(4); + PROVIDE(_stext = ABSOLUTE(.)); + KEEP(*(.isr_vector)) /* Startup code */ + + + . = ALIGN(4); + *(.text .text.*) /* Normal code */ + *(.rodata .rodata*) /* read-only data (constants) */ + + *(.glue_7) + *(.glue_7t) + + /* section information for shell */ + . = ALIGN(4); + _shell_command_start = .; + KEEP (*(shellCommand)) + _shell_command_end = .; + . = ALIGN(4); + + PROVIDE(__ctors_start__ = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array)) + PROVIDE(__ctors_end__ = .); + + . = ALIGN(4); + + __isrtbl_idx_start = .; + KEEP(*(.isrtbl.idx)) + __isrtbl_start = .; + KEEP(*(.isrtbl)) + __isrtbl_end = .; + . = ALIGN(4); + + PROVIDE(g_service_table_start = ABSOLUTE(.)); + KEEP(*(.g_service_table)) + PROVIDE(g_service_table_end = ABSOLUTE(.)); + + PROVIDE(_etext = ABSOLUTE(.)); + } > flash + + /* .ARM.exidx is sorted, so has to go in its own output section. */ + __exidx_start = .; + .ARM.exidx : + { + PROVIDE(__exidx_start = ABSOLUTE(.)); + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + _sidata = .; + PROVIDE(__exidx_end = ABSOLUTE(.)); + } > flash + + .data : AT(__exidx_end) + { + . = ALIGN(4); + PROVIDE(_sdata = ABSOLUTE(.)); + *(.data .data.*) + PROVIDE(_edata = ABSOLUTE(.)); + } > sram + + .bss : + { + . = ALIGN(4); + __bss_start = ABSOLUTE(.); + + *(.bss .bss.*) + *(COMMON) + + . = ALIGN(4); + __bss_end = ABSOLUTE(.); + } > sram + + .stack : + { + . = ALIGN(4); + PROVIDE(__stack_start__ = ABSOLUTE(.)); + /* cpu stack */ + . = . + __SYSTEM_STACKSIZE__; + __stack_tp = .; + PROVIDE(__stack_end__ = ABSOLUTE(.)); + } > sram + + _end = ABSOLUTE(.); +} diff --git a/Ubiquitous/XiZi/board/stm32f407-st-discovery/link_userspace.lds b/Ubiquitous/XiZi/board/stm32f407-st-discovery/link_userspace.lds new file mode 100644 index 0000000..aa67511 --- /dev/null +++ b/Ubiquitous/XiZi/board/stm32f407-st-discovery/link_userspace.lds @@ -0,0 +1,72 @@ +/* +* Copyright (c) 2020 AIIT XUOS Lab +* XiUOS is licensed under Mulan PSL v2. +* You can use this software according to the terms and conditions of the Mulan PSL v2. +* You may obtain a copy of Mulan PSL v2 at: +* http://license.coscl.org.cn/MulanPSL2 +* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, +* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, +* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. +* See the Mulan PSL v2 for more details. +*/ + +OUTPUT_ARCH(arm) + +MEMORY +{ + uflash (rx) : ORIGIN = 0x08080000, LENGTH = 512k /* 512KB uflash */ + usram (rw) : ORIGIN = 0x10000000, LENGTH = 64k /* 64K usram */ +} + +SECTIONS +{ + .userspace : + { + _ustext = ABSOLUTE(.); + . = ALIGN(4); + KEEP(*(.userspace)) + } > uflash + + .text : + { + *(.text .text.*) + *(.rodata .rodata*) + *(.glue_7) + *(.glue_7t) + PROVIDE(_uetext = ABSOLUTE(.)); + } > uflash + + .init_section : { + _sinit = ABSOLUTE(.); + KEEP(*(.init_array .init_array.*)) + _einit = ABSOLUTE(.); + } > uflash + + __uexidx_start = ABSOLUTE(.); + + .ARM.exidx : + { + PROVIDE(__uexidx_start = ABSOLUTE(.)); + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + PROVIDE(__uexidx_end = ABSOLUTE(.)); + } > uflash + + _ueronly = ABSOLUTE(.); + + .data : AT(_ueronly) + { + _usdata = ABSOLUTE(.); + *(.data .data.*) + . = ALIGN(4); + _uedata = ABSOLUTE(.); + } > usram + + .bss : { + . = ALIGN(4); + _usbss = ABSOLUTE(.); + *(.bss .bss.*) + *(.sbss .sbss.*) + . = ALIGN(4); + _uebss = ABSOLUTE(.); + } > usram +} \ No newline at end of file diff --git a/Ubiquitous/XiZi/board/stm32f407-st-discovery/third_party_driver/Kconfig b/Ubiquitous/XiZi/board/stm32f407-st-discovery/third_party_driver/Kconfig new file mode 100755 index 0000000..283313b --- /dev/null +++ b/Ubiquitous/XiZi/board/stm32f407-st-discovery/third_party_driver/Kconfig @@ -0,0 +1,121 @@ +menuconfig BSP_USING_ADC +bool "Using ADC device" +default n +select RESOURCES_ADC +if BSP_USING_ADC +source "$BSP_DIR/third_party_driver/adc/Kconfig" +endif + +menuconfig BSP_USING_CAN +bool "Using CAN device" +default n +select RESOURCES_CAN +if BSP_USING_CAN +source "$BSP_DIR/third_party_driver/can/Kconfig" +endif + +menuconfig BSP_USING_DAC +bool "Using DAC device" +default n +select RESOURCES_DAC +if BSP_USING_DAC +source "$BSP_DIR/third_party_driver/dac/Kconfig" +endif + +menuconfig BSP_USING_DMA +bool "Using DMA device" +default y +if BSP_USING_DMA +source "$BSP_DIR/third_party_driver/common/Kconfig" +endif + +menuconfig BSP_USING_GPIO +bool "Using GPIO device " +default y +select RESOURCES_PIN +if BSP_USING_GPIO +source "$BSP_DIR/third_party_driver/gpio/Kconfig" +endif + +menuconfig BSP_USING_I2C +bool "Using I2C device" +default n +select RESOURCES_I2C +if BSP_USING_I2C +source "$BSP_DIR/third_party_driver/i2c/Kconfig" +endif + +menuconfig BSP_USING_LCD +bool "Using LCD device" +default n +select BSP_USING_SPI1 +select RESOURCES_LCD +if BSP_USING_LCD +source "$BSP_DIR/third_party_driver/lcd/Kconfig" +endif + +menuconfig BSP_USING_RTC +bool "Using RTC device" +default n +select RESOURCES_RTC +if BSP_USING_RTC +source "$BSP_DIR/third_party_driver/rtc/Kconfig" +endif + +menuconfig BSP_USING_SDIO +bool "Using SDIO device" +default n +select RESOURCES_SDIO +if BSP_USING_SDIO +source "$BSP_DIR/third_party_driver/sdio/Kconfig" +endif + +menuconfig BSP_USING_SPI +bool "Using SPI device" +default n +select RESOURCES_SPI +select BSP_USING_DMA +if BSP_USING_SPI +source "$BSP_DIR/third_party_driver/spi/Kconfig" +endif + +menuconfig BSP_USING_HWTIMER +bool "Using HWTIMER device" +default n +select RESOURCES_HWTIMER +if BSP_USING_HWTIMER +source "$BSP_DIR/third_party_driver/timer/Kconfig" +endif + +menuconfig BSP_USING_UART +bool "Using UART device" +default y +select RESOURCES_SERIAL +if BSP_USING_UART +source "$BSP_DIR/third_party_driver/uart/Kconfig" +endif + +menuconfig BSP_USING_USB +bool "Using USB device" +default n +select BSP_USING_STM32_USBH +select RESOURCES_USB +select RESOURCES_USB_HOST +select USBH_MSTORAGE +select RESOURCES_USB_DEVICE +if BSP_USING_USB +source "$BSP_DIR/third_party_driver/usb/Kconfig" +endif + +menuconfig BSP_USING_LWIP +bool "Using LwIP device" +default n +select RESOURCES_LWIP + +menuconfig BSP_USING_WDT +bool "Using WATCHDOG device" +default y +select RESOURCES_WDT +if BSP_USING_WDT +source "$BSP_DIR/third_party_driver/watchdog/Kconfig" +endif diff --git a/Ubiquitous/XiZi/board/stm32f407-st-discovery/third_party_driver/Makefile b/Ubiquitous/XiZi/board/stm32f407-st-discovery/third_party_driver/Makefile new file mode 100644 index 0000000..13a71f6 --- /dev/null +++ b/Ubiquitous/XiZi/board/stm32f407-st-discovery/third_party_driver/Makefile @@ -0,0 +1,60 @@ + +SRC_DIR := common + +ifeq ($(CONFIG_BSP_USING_ADC),y) + SRC_DIR += adc +endif + +ifeq ($(CONFIG_BSP_USING_CAN),y) + SRC_DIR += can +endif + +ifeq ($(CONFIG_BSP_USING_DAC),y) + SRC_DIR += dac +endif + +ifeq ($(CONFIG_BSP_USING_GPIO),y) + SRC_DIR += gpio +endif + +ifeq ($(CONFIG_BSP_USING_I2C),y) + SRC_DIR += i2c +endif + +ifeq ($(CONFIG_BSP_USING_LCD),y) + SRC_DIR += lcd +endif + +ifeq ($(CONFIG_BSP_USING_RTC),y) + SRC_DIR += rtc +endif + +ifeq ($(CONFIG_BSP_USING_SDIO),y) + SRC_DIR += sdio +endif + +ifeq ($(CONFIG_BSP_USING_SPI),y) + SRC_DIR += spi +endif + +ifeq ($(CONFIG_BSP_USING_HWTIMER),y) + SRC_DIR += timer +endif + +ifeq ($(CONFIG_BSP_USING_UART),y) + SRC_DIR += uart +endif + +ifeq ($(CONFIG_BSP_USING_USB),y) + SRC_DIR += usb +endif + +ifeq ($(CONFIG_BSP_USING_WDT),y) + SRC_DIR += watchdog +endif + +ifeq ($(CONFIG_BSP_USING_LWIP),y) + SRC_DIR += ethernet +endif + +include $(KERNEL_ROOT)/compiler.mk diff --git a/Ubiquitous/XiZi/board/stm32f407-st-discovery/third_party_driver/adc/Kconfig b/Ubiquitous/XiZi/board/stm32f407-st-discovery/third_party_driver/adc/Kconfig new file mode 100644 index 0000000..ac7cd30 --- /dev/null +++ b/Ubiquitous/XiZi/board/stm32f407-st-discovery/third_party_driver/adc/Kconfig @@ -0,0 +1,76 @@ + + +menuconfig BSP_USING_ADC1 + bool "Enable ADC1" + default n + if BSP_USING_ADC1 + config ADC1_BUS_NAME + string "adc 1 bus name" + default "adc1" + + config ADC1_DRIVER_NAME + string "adc 1 driver name" + default "adc1_drv" + + config ADC1_DEVICE_NAME + string "adc 1 bus device name" + default "adc1_dev" + + config ADC1_GPIO_NUM + int "adc 1 gpio pin num" + default "0" + + config ADC1_GPIO_DEF + string "adc 1 gpio define type" + default "A" + endif + +menuconfig BSP_USING_ADC2 + bool "Enable ADC2" + default n + if BSP_USING_ADC2 + config ADC2_BUS_NAME + string "adc 2 bus name" + default "adc2" + + config ADC2_DRIVER_NAME + string "adc 2 driver name" + default "adc2_drv" + + config ADC2_DEVICE_NAME + string "adc 2 bus device name" + default "adc2_dev" + + config ADC2_GPIO_NUM + int "adc 2 gpio pin num" + default "6" + + config ADC2_GPIO_DEF + string "adc 2 gpio define type" + default "A" + endif + +menuconfig BSP_USING_ADC3 + bool "Enable ADC3" + default n + if BSP_USING_ADC3 + config ADC3_BUS_NAME + string "adc 3 bus name" + default "adc3" + + config ADC3_DRIVER_NAME + string "adc 3 driver name" + default "adc3_drv" + + config ADC3_DEVICE_NAME + string "adc 3 bus device name" + default "adc3_dev" + + config ADC3_GPIO_NUM + int "adc 3 gpio pin num" + default "0" + + config ADC3_GPIO_DEF + string "adc 3 gpio define type" + default "A" + endif diff --git a/Ubiquitous/XiZi/board/stm32f407-st-discovery/third_party_driver/adc/Makefile b/Ubiquitous/XiZi/board/stm32f407-st-discovery/third_party_driver/adc/Makefile new file mode 100644 index 0000000..c2dc54f --- /dev/null +++ b/Ubiquitous/XiZi/board/stm32f407-st-discovery/third_party_driver/adc/Makefile @@ -0,0 +1,3 @@ +SRC_FILES := connect_adc.c hardware_adc.c + +include $(KERNEL_ROOT)/compiler.mk \ No newline at end of file diff --git a/Ubiquitous/XiZi/board/stm32f407-st-discovery/third_party_driver/adc/connect_adc.c b/Ubiquitous/XiZi/board/stm32f407-st-discovery/third_party_driver/adc/connect_adc.c new file mode 100644 index 0000000..26f7e64 --- /dev/null +++ b/Ubiquitous/XiZi/board/stm32f407-st-discovery/third_party_driver/adc/connect_adc.c @@ -0,0 +1,433 @@ +/* +* Copyright (c) 2020 AIIT XUOS Lab +* XiUOS is licensed under Mulan PSL v2. +* You can use this software according to the terms and conditions of the Mulan PSL v2. +* You may obtain a copy of Mulan PSL v2 at: +* http://license.coscl.org.cn/MulanPSL2 +* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, +* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, +* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. +* See the Mulan PSL v2 for more details. +*/ + +/** +* @file connect_adc.c +* @brief support to register ADC pointer and function +* @version 1.1 +* @author AIIT XUOS Lab +* @date 2021-12-28 +*/ + +#include + +#define _ADC_CONS(string1, string2) string1##string2 +#define ADC_CONS(string1, string2) _ADC_CONS(string1, string2) + +#ifdef BSP_USING_ADC1 +#define ADC1_GPIO ADC_CONS(GPIO_Pin_, ADC1_GPIO_NUM) +#endif + +#ifdef BSP_USING_ADC2 +#define ADC2_GPIO ADC_CONS(GPIO_Pin_, ADC2_GPIO_NUM) +#endif + +#ifdef BSP_USING_ADC3 +#define ADC3_GPIO ADC_CONS(GPIO_Pin_, ADC3_GPIO_NUM) +#endif + +static int Stm32AdcUdelay(uint32 us) +{ + uint32 ticks; + uint32 told, tnow, tcnt = 0; + uint32 reload = SysTick->LOAD; + + ticks = us * reload / (1000000 / TICK_PER_SECOND); + told = SysTick->VAL; + while (1) { + tnow = SysTick->VAL; + if (tnow != told) { + if (tnow < told) { + tcnt += told - tnow; + } else { + tcnt += reload - tnow + told; + } + told = tnow; + if (tcnt >= ticks) { + return 0; + break; + } + } + } +} + +static GPIO_TypeDef* AdcGetGpioType(char *adc_gpio_def) +{ + if (0 == strncmp(adc_gpio_def, "A", 2)) { + return GPIOA; + } else if (0 == strncmp(adc_gpio_def, "B", 2)) { + return GPIOB; + } else if (0 == strncmp(adc_gpio_def, "C", 2)) { + return GPIOC; + } else if (0 == strncmp(adc_gpio_def, "F", 2)) { + return GPIOF; + } else { + printf("AdcGetGpioType do not support %s GPIO\n", adc_gpio_def); + return GPIOA; + } +} + +static uint32 AdcGetGpioRcc(char *adc_gpio_def) +{ + if (0 == strncmp(adc_gpio_def, "A", 2)) { + return RCC_AHB1Periph_GPIOA; + } else if (0 == strncmp(adc_gpio_def, "B", 2)) { + return RCC_AHB1Periph_GPIOB; + } else if (0 == strncmp(adc_gpio_def, "C", 2)) { + return RCC_AHB1Periph_GPIOC; + } else if (0 == strncmp(adc_gpio_def, "F", 2)) { + return RCC_AHB1Periph_GPIOF; + } else { + printf("AdcGetGpioRcc do not support %s GPIO\n", adc_gpio_def); + return RCC_AHB1Periph_GPIOA; + } +} + +static void AdcInit(struct AdcHardwareDevice *adc_dev) +{ + GPIO_InitTypeDef GPIO_InitStructure; + ADC_CommonInitTypeDef ADC_CommonInitStructure; + ADC_InitTypeDef ADC_InitStructure; + uint32_t RCC_AHB1Periph; + GPIO_TypeDef* GPIOx; + +#ifdef BSP_USING_ADC1 + if (0 == strncmp(adc_dev->haldev.dev_name, ADC1_DEVICE_NAME, NAME_NUM_MAX)) { + + GPIOx = AdcGetGpioType(ADC1_GPIO_DEF); + RCC_AHB1Periph = AdcGetGpioRcc(ADC1_GPIO_DEF); + + RCC_AHB1PeriphClockCmd(RCC_AHB1Periph, ENABLE);//enable GPIOA clock + RCC_APB2PeriphClockCmd(RCC_APB2Periph_ADC1, ENABLE);//enable ADC1 clock + + GPIO_InitStructure.GPIO_Pin = ADC1_GPIO; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AN;//analog input + GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL; + GPIO_Init(GPIOx, &GPIO_InitStructure); + + RCC_APB2PeriphResetCmd(RCC_APB2Periph_ADC1, ENABLE); + RCC_APB2PeriphResetCmd(RCC_APB2Periph_ADC1, DISABLE); + + ADC_CommonInitStructure.ADC_Mode = ADC_Mode_Independent; + ADC_CommonInitStructure.ADC_TwoSamplingDelay = ADC_TwoSamplingDelay_5Cycles; + ADC_CommonInitStructure.ADC_DMAAccessMode = ADC_DMAAccessMode_Disabled; + ADC_CommonInitStructure.ADC_Prescaler = ADC_Prescaler_Div4; + ADC_CommonInit(&ADC_CommonInitStructure); + + ADC_InitStructure.ADC_Resolution = ADC_Resolution_12b;//12 bit mode + ADC_InitStructure.ADC_ScanConvMode = DISABLE; + ADC_InitStructure.ADC_ContinuousConvMode = DISABLE; + ADC_InitStructure.ADC_ExternalTrigConvEdge = ADC_ExternalTrigConvEdge_None; + ADC_InitStructure.ADC_DataAlign = ADC_DataAlign_Right; + ADC_InitStructure.ADC_NbrOfConversion = 1; + ADC_Init(ADC1, &ADC_InitStructure); + + ADC_Cmd(ADC1, ENABLE); + } +#endif + +#ifdef BSP_USING_ADC2 + if (0 == strncmp(adc_dev->haldev.dev_name, ADC2_DEVICE_NAME, NAME_NUM_MAX)) { + + GPIOx = AdcGetGpioType(ADC2_GPIO_DEF); + RCC_AHB1Periph = AdcGetGpioRcc(ADC2_GPIO_DEF); + + RCC_AHB1PeriphClockCmd(RCC_AHB1Periph, ENABLE);//enable GPIOA clock + RCC_APB2PeriphClockCmd(RCC_APB2Periph_ADC2, ENABLE);//enable ADC2 clock + + GPIO_InitStructure.GPIO_Pin = ADC2_GPIO; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AN;//analog input + GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL; + GPIO_Init(GPIOx, &GPIO_InitStructure); + + RCC_APB2PeriphResetCmd(RCC_APB2Periph_ADC2, ENABLE); + RCC_APB2PeriphResetCmd(RCC_APB2Periph_ADC2, DISABLE); + + ADC_CommonInitStructure.ADC_Mode = ADC_Mode_Independent; + ADC_CommonInitStructure.ADC_TwoSamplingDelay = ADC_TwoSamplingDelay_5Cycles; + ADC_CommonInitStructure.ADC_DMAAccessMode = ADC_DMAAccessMode_Disabled; + ADC_CommonInitStructure.ADC_Prescaler = ADC_Prescaler_Div4; + ADC_CommonInit(&ADC_CommonInitStructure); + + ADC_InitStructure.ADC_Resolution = ADC_Resolution_12b;//12 bit mode + ADC_InitStructure.ADC_ScanConvMode = DISABLE; + ADC_InitStructure.ADC_ContinuousConvMode = DISABLE; + ADC_InitStructure.ADC_ExternalTrigConvEdge = ADC_ExternalTrigConvEdge_None; + ADC_InitStructure.ADC_DataAlign = ADC_DataAlign_Right; + ADC_InitStructure.ADC_NbrOfConversion = 1; + ADC_Init(ADC2, &ADC_InitStructure); + + ADC_Cmd(ADC2, ENABLE); + } +#endif + +#ifdef BSP_USING_ADC3 + if (0 == strncmp(adc_dev->haldev.dev_name, ADC3_DEVICE_NAME, NAME_NUM_MAX)) { + + GPIOx = AdcGetGpioType(ADC3_GPIO_DEF); + RCC_AHB1Periph = AdcGetGpioRcc(ADC3_GPIO_DEF); + + RCC_AHB1PeriphClockCmd(RCC_AHB1Periph, ENABLE);//enable GPIOA clock + RCC_APB2PeriphClockCmd(RCC_APB2Periph_ADC3, ENABLE);//enable ADC3 clock + + GPIO_InitStructure.GPIO_Pin = ADC3_GPIO; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AN;//analog input + GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL; + GPIO_Init(GPIOx, &GPIO_InitStructure); + + RCC_APB2PeriphResetCmd(RCC_APB2Periph_ADC3, ENABLE); + RCC_APB2PeriphResetCmd(RCC_APB2Periph_ADC3, DISABLE); + + ADC_CommonInitStructure.ADC_Mode = ADC_Mode_Independent; + ADC_CommonInitStructure.ADC_TwoSamplingDelay = ADC_TwoSamplingDelay_5Cycles; + ADC_CommonInitStructure.ADC_DMAAccessMode = ADC_DMAAccessMode_Disabled; + ADC_CommonInitStructure.ADC_Prescaler = ADC_Prescaler_Div4; + ADC_CommonInit(&ADC_CommonInitStructure); + + ADC_InitStructure.ADC_Resolution = ADC_Resolution_12b;//12 bit mode + ADC_InitStructure.ADC_ScanConvMode = DISABLE; + ADC_InitStructure.ADC_ContinuousConvMode = DISABLE; + ADC_InitStructure.ADC_ExternalTrigConvEdge = ADC_ExternalTrigConvEdge_None; + ADC_InitStructure.ADC_DataAlign = ADC_DataAlign_Right; + ADC_InitStructure.ADC_NbrOfConversion = 1; + ADC_Init(ADC3, &ADC_InitStructure); + + ADC_Cmd(ADC3, ENABLE); + } +#endif +} + +static uint16 GetAdcValue(ADC_TypeDef *ADCx, uint8 channel) +{ + //set ADCx channel, rank, sampletime + ADC_RegularChannelConfig(ADCx, channel, 1, ADC_SampleTime_480Cycles); + + ADC_SoftwareStartConv(ADCx); + + while(!ADC_GetFlagStatus(ADCx, ADC_FLAG_EOC)); + + return ADC_GetConversionValue(ADCx); +} + +static uint16 GetAdcAverageValue(ADC_TypeDef *ADCx, uint8 channel, uint8 times) +{ + uint32 temp_val = 0; + int i; + + for(i = 0;i < times;i ++) { + temp_val += GetAdcValue(ADCx, channel) & 0x0FFF; + KPrintf("GetAdcAverageValue val %u\n", GetAdcValue(ADCx, channel)); + Stm32AdcUdelay(5000); + } + return temp_val / times; +} + +static uint32 Stm32AdcOpen(void *dev) +{ + struct AdcHardwareDevice *adc_dev = (struct AdcHardwareDevice *)dev; + + AdcInit(adc_dev); + + return EOK; +} + +static uint32 Stm32AdcClose(void *dev) +{ + struct AdcHardwareDevice *adc_dev = (struct AdcHardwareDevice *)dev; + + ADC_DeInit(); + + return EOK; +} + +static uint32 Stm32AdcRead(void *dev, struct BusBlockReadParam *read_param) +{ + struct AdcHardwareDevice *adc_dev = (struct AdcHardwareDevice *)dev; + struct Stm32HwAdc *adc_cfg = (struct Stm32HwAdc *)adc_dev->haldev.private_data; + + uint16 adc_average_value = 0; + uint8 times = 20; + + adc_average_value = GetAdcAverageValue(adc_cfg->ADCx, adc_cfg->adc_channel, times); + + *(uint16 *)read_param->buffer = adc_average_value; + read_param->read_length = 2; + + return read_param->read_length; +} + +static uint32 Stm32AdcDrvConfigure(void *drv, struct BusConfigureInfo *configure_info) +{ + NULL_PARAM_CHECK(drv); + NULL_PARAM_CHECK(configure_info); + + x_err_t ret = EOK; + uint8 adc_channel; + + struct AdcDriver *adc_drv = (struct AdcDriver *)drv; + struct AdcHardwareDevice *adc_dev = (struct AdcHardwareDevice *)adc_drv->driver.owner_bus->owner_haldev; + struct Stm32HwAdc *adc_cfg = (struct Stm32HwAdc *)adc_dev->haldev.private_data; + + switch (configure_info->configure_cmd) + { + case OPE_CFG: + adc_cfg->adc_channel = *(uint8 *)configure_info->private_data; + if (adc_cfg->adc_channel > 18) { + KPrintf("Stm32AdcDrvConfigure set adc channel(0-18) %u error!", adc_cfg->adc_channel); + adc_cfg->adc_channel = 0; + ret = ERROR; + } + break; + default: + break; + } + + return ret; +} + +static const struct AdcDevDone dev_done = +{ + Stm32AdcOpen, + Stm32AdcClose, + NONE, + Stm32AdcRead, +}; + +int Stm32HwAdcInit(void) +{ + x_err_t ret = EOK; + +#ifdef BSP_USING_ADC1 + static struct AdcBus adc1_bus; + static struct AdcDriver adc1_drv; + static struct AdcHardwareDevice adc1_dev; + static struct Stm32HwAdc adc1_cfg; + + adc1_drv.configure = Stm32AdcDrvConfigure; + + ret = AdcBusInit(&adc1_bus, ADC1_BUS_NAME); + if (ret != EOK) { + KPrintf("ADC1 bus init error %d\n", ret); + return ERROR; + } + + ret = AdcDriverInit(&adc1_drv, ADC1_DRIVER_NAME); + if (ret != EOK) { + KPrintf("ADC1 driver init error %d\n", ret); + return ERROR; + } + ret = AdcDriverAttachToBus(ADC1_DRIVER_NAME, ADC1_BUS_NAME); + if (ret != EOK) { + KPrintf("ADC1 driver attach error %d\n", ret); + return ERROR; + } + + adc1_dev.adc_dev_done = &dev_done; + adc1_cfg.ADCx = ADC1; + adc1_cfg.adc_channel = 0; + + ret = AdcDeviceRegister(&adc1_dev, (void *)&adc1_cfg, ADC1_DEVICE_NAME); + if (ret != EOK) { + KPrintf("ADC1 device register error %d\n", ret); + return ERROR; + } + ret = AdcDeviceAttachToBus(ADC1_DEVICE_NAME, ADC1_BUS_NAME); + if (ret != EOK) { + KPrintf("ADC1 device register error %d\n", ret); + return ERROR; + } +#endif + +#ifdef BSP_USING_ADC2 + static struct AdcBus adc2_bus; + static struct AdcDriver adc2_drv; + static struct AdcHardwareDevice adc2_dev; + static struct Stm32HwAdc adc2_cfg; + + adc2_drv.configure = Stm32AdcDrvConfigure; + + ret = AdcBusInit(&adc2_bus, ADC2_BUS_NAME); + if (ret != EOK) { + KPrintf("ADC2 bus init error %d\n", ret); + return ERROR; + } + + ret = AdcDriverInit(&adc2_drv, ADC2_DRIVER_NAME); + if (ret != EOK) { + KPrintf("ADC2 driver init error %d\n", ret); + return ERROR; + } + ret = AdcDriverAttachToBus(ADC2_DRIVER_NAME, ADC2_BUS_NAME); + if (ret != EOK) { + KPrintf("ADC2 driver attach error %d\n", ret); + return ERROR; + } + + adc2_dev.adc_dev_done = &dev_done; + adc2_cfg.ADCx = ADC2; + adc2_cfg.adc_channel = 0; + + ret = AdcDeviceRegister(&adc2_dev, (void *)&adc2_cfg, ADC2_DEVICE_NAME); + if (ret != EOK) { + KPrintf("ADC2 device register error %d\n", ret); + return ERROR; + } + ret = AdcDeviceAttachToBus(ADC2_DEVICE_NAME, ADC2_BUS_NAME); + if (ret != EOK) { + KPrintf("ADC2 device register error %d\n", ret); + return ERROR; + } +#endif + +#ifdef BSP_USING_ADC3 + static struct AdcBus adc3_bus; + static struct AdcDriver adc3_drv; + static struct AdcHardwareDevice adc3_dev; + static struct Stm32HwAdc adc3_cfg; + + adc3_drv.configure = Stm32AdcDrvConfigure; + + ret = AdcBusInit(&adc3_bus, ADC3_BUS_NAME); + if (ret != EOK) { + KPrintf("ADC3 bus init error %d\n", ret); + return ERROR; + } + + ret = AdcDriverInit(&adc3_drv, ADC3_DRIVER_NAME); + if (ret != EOK) { + KPrintf("ADC3 driver init error %d\n", ret); + return ERROR; + } + ret = AdcDriverAttachToBus(ADC3_DRIVER_NAME, ADC3_BUS_NAME); + if (ret != EOK) { + KPrintf("ADC3 driver attach error %d\n", ret); + return ERROR; + } + + adc3_dev.adc_dev_done = &dev_done; + adc3_cfg.ADCx = ADC3; + adc3_cfg.adc_channel = 0; + + ret = AdcDeviceRegister(&adc3_dev, (void *)&adc3_cfg, ADC3_DEVICE_NAME); + if (ret != EOK) { + KPrintf("ADC3 device register error %d\n", ret); + return ERROR; + } + ret = AdcDeviceAttachToBus(ADC3_DEVICE_NAME, ADC3_BUS_NAME); + if (ret != EOK) { + KPrintf("ADC3 device register error %d\n", ret); + return ERROR; + } +#endif + + return ret; +} diff --git a/Ubiquitous/XiZi/board/stm32f407-st-discovery/third_party_driver/can/Kconfig b/Ubiquitous/XiZi/board/stm32f407-st-discovery/third_party_driver/can/Kconfig new file mode 100644 index 0000000..a6889b4 --- /dev/null +++ b/Ubiquitous/XiZi/board/stm32f407-st-discovery/third_party_driver/can/Kconfig @@ -0,0 +1,12 @@ + +config CAN_BUS_NAME_1 + string "can bus name" + default "can1" + +config CAN_DRIVER_NAME + string "can driver name" + default "can1_drv" + +config CAN_1_DEVICE_NAME_1 + string "can bus 1 device 1 name" + default "can1_dev1" \ No newline at end of file diff --git a/Ubiquitous/XiZi/board/stm32f407-st-discovery/third_party_driver/can/Makefile b/Ubiquitous/XiZi/board/stm32f407-st-discovery/third_party_driver/can/Makefile new file mode 100644 index 0000000..b7b2503 --- /dev/null +++ b/Ubiquitous/XiZi/board/stm32f407-st-discovery/third_party_driver/can/Makefile @@ -0,0 +1,4 @@ +SRC_FILES := hardware_can.c connect_can.c + + +include $(KERNEL_ROOT)/compiler.mk \ No newline at end of file diff --git a/Ubiquitous/XiZi/board/stm32f407-st-discovery/third_party_driver/dac/Kconfig b/Ubiquitous/XiZi/board/stm32f407-st-discovery/third_party_driver/dac/Kconfig new file mode 100644 index 0000000..a289b6c --- /dev/null +++ b/Ubiquitous/XiZi/board/stm32f407-st-discovery/third_party_driver/dac/Kconfig @@ -0,0 +1,17 @@ +if BSP_USING_DAC + config DAC_BUS_NAME + string "dac bus name" + default "dac" + + config DAC_DRIVER_NAME + string "dac driver name" + default "dac_drv" + + config DAC_DEVICE_NAME + string "dac bus device name" + default "dac_dev" + + config DAC_GPIO_NUM + int "dac gpio pin num(only support 4 or 5)" + default "4" +endif diff --git a/Ubiquitous/XiZi/board/stm32f407-st-discovery/third_party_driver/dac/Makefile b/Ubiquitous/XiZi/board/stm32f407-st-discovery/third_party_driver/dac/Makefile new file mode 100644 index 0000000..4bd1c0c --- /dev/null +++ b/Ubiquitous/XiZi/board/stm32f407-st-discovery/third_party_driver/dac/Makefile @@ -0,0 +1,3 @@ +SRC_FILES := connect_dac.c hardware_dac.c + +include $(KERNEL_ROOT)/compiler.mk diff --git a/Ubiquitous/XiZi/board/stm32f407-st-discovery/third_party_driver/dac/connect_dac.c b/Ubiquitous/XiZi/board/stm32f407-st-discovery/third_party_driver/dac/connect_dac.c new file mode 100644 index 0000000..6186b0a --- /dev/null +++ b/Ubiquitous/XiZi/board/stm32f407-st-discovery/third_party_driver/dac/connect_dac.c @@ -0,0 +1,168 @@ +/* +* Copyright (c) 2020 AIIT XUOS Lab +* XiUOS is licensed under Mulan PSL v2. +* You can use this software according to the terms and conditions of the Mulan PSL v2. +* You may obtain a copy of Mulan PSL v2 at: +* http://license.coscl.org.cn/MulanPSL2 +* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, +* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, +* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. +* See the Mulan PSL v2 for more details. +*/ + +/** +* @file connect_dac.c +* @brief support to register DAC pointer and function +* @version 2.0 +* @author AIIT XUOS Lab +* @date 2022-1-10 +*/ + +#include + +#define _DAC_CONS(string1, string2) string1##string2 +#define DAC_CONS(string1, string2) _DAC_CONS(string1, string2) + +#ifdef BSP_USING_DAC +#define DAC_GPIO DAC_CONS(GPIO_Pin_, DAC_GPIO_NUM) +#endif + +static void DacInit(struct DacHardwareDevice *dac_dev) +{ + GPIO_InitTypeDef GPIO_InitStructure; + DAC_InitTypeDef DAC_InitType; + +#ifdef BSP_USING_DAC + if (0 == strncmp(dac_dev->haldev.dev_name, DAC_DEVICE_NAME, NAME_NUM_MAX)) { + RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOA, ENABLE);//enable GPIOA clock + RCC_APB1PeriphClockCmd(RCC_APB1Periph_DAC, ENABLE);//enable DAC clock + + GPIO_InitStructure.GPIO_Pin = DAC_GPIO; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AN; + GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_DOWN; + GPIO_Init(GPIOA, &GPIO_InitStructure); + + DAC_InitType.DAC_Trigger = DAC_Trigger_None;//disable trigger function TEN1=0 + DAC_InitType.DAC_WaveGeneration = DAC_WaveGeneration_None;//disable wave generation function + DAC_InitType.DAC_LFSRUnmask_TriangleAmplitude = DAC_LFSRUnmask_Bit0;//mask and amplitude configure + DAC_InitType.DAC_OutputBuffer = DAC_OutputBuffer_Disable;//disable DAC1 output buffer BOFF1=1 + DAC_Init(DAC_Channel_1, &DAC_InitType); + + DAC_Cmd(DAC_Channel_1, ENABLE);//enable DAC channel 1 + + DAC_SetChannel1Data(DAC_Align_12b_R, 0);//12 bits、R-Align data format, default 0 + } +#endif +} + +static uint32 Stm32DacOpen(void *dev) +{ + struct DacHardwareDevice *dac_dev = (struct DacHardwareDevice *)dev; + + DacInit(dac_dev); + + return EOK; +} + +static uint32 Stm32DacClose(void *dev) +{ + struct DacHardwareDevice *dac_dev = (struct DacHardwareDevice *)dev; + + DAC_DeInit(); + + return EOK; +} + +static uint32 Stm32DacRead(void *dev, struct BusBlockReadParam *read_param) +{ + struct DacHardwareDevice *dac_dev = (struct DacHardwareDevice *)dev; + + uint16 dac_set_value = 0; + + dac_set_value = DAC_GetDataOutputValue(DAC_Channel_1); + + *(uint16 *)read_param->buffer = dac_set_value; + read_param->read_length = 2; + + return read_param->read_length; +} + +static uint32 Stm32DacDrvConfigure(void *drv, struct BusConfigureInfo *configure_info) +{ + NULL_PARAM_CHECK(drv); + NULL_PARAM_CHECK(configure_info); + + x_err_t ret = EOK; + + struct DacDriver *dac_drv = (struct DacDriver *)drv; + struct DacHardwareDevice *dac_dev = (struct DacHardwareDevice *)dac_drv->driver.owner_bus->owner_haldev; + struct Stm32HwDac *dac_cfg = (struct Stm32HwDac *)dac_dev->haldev.private_data; + + switch (configure_info->configure_cmd) + { + case OPE_CFG: + dac_cfg->digital_data = *(uint16 *)configure_info->private_data; + DAC_SetChannel1Data(DAC_Align_12b_R, dac_cfg->digital_data);//12 bits、R-Align data format, digital data + break; + default: + break; + } + + return ret; +} + +static const struct DacDevDone dev_done = +{ + Stm32DacOpen, + Stm32DacClose, + NONE, + Stm32DacRead, +}; + +int Stm32HwDacInit(void) +{ + x_err_t ret = EOK; + +#ifdef BSP_USING_DAC + static struct DacBus dac_bus; + static struct DacDriver dac_drv; + static struct DacHardwareDevice dac_dev; + static struct Stm32HwDac dac_cfg; + + dac_drv.configure = Stm32DacDrvConfigure; + + ret = DacBusInit(&dac_bus, DAC_BUS_NAME); + if (ret != EOK) { + KPrintf("DAC bus init error %d\n", ret); + return ERROR; + } + + ret = DacDriverInit(&dac_drv, DAC_DRIVER_NAME); + if (ret != EOK) { + KPrintf("DAC driver init error %d\n", ret); + return ERROR; + } + ret = DacDriverAttachToBus(DAC_DRIVER_NAME, DAC_BUS_NAME); + if (ret != EOK) { + KPrintf("DAC driver attach error %d\n", ret); + return ERROR; + } + + dac_dev.dac_dev_done = &dev_done; + dac_cfg.DACx = DAC; + dac_cfg.digital_data = 0; + + ret = DacDeviceRegister(&dac_dev, (void *)&dac_cfg, DAC_DEVICE_NAME); + if (ret != EOK) { + KPrintf("DAC device register error %d\n", ret); + return ERROR; + } + ret = DacDeviceAttachToBus(DAC_DEVICE_NAME, DAC_BUS_NAME); + if (ret != EOK) { + KPrintf("DAC device register error %d\n", ret); + return ERROR; + } +#endif + + return ret; +} diff --git a/Ubiquitous/XiZi/board/stm32f407-st-discovery/third_party_driver/ethernet/Kconfig b/Ubiquitous/XiZi/board/stm32f407-st-discovery/third_party_driver/ethernet/Kconfig new file mode 100644 index 0000000..a6889b4 --- /dev/null +++ b/Ubiquitous/XiZi/board/stm32f407-st-discovery/third_party_driver/ethernet/Kconfig @@ -0,0 +1,12 @@ + +config CAN_BUS_NAME_1 + string "can bus name" + default "can1" + +config CAN_DRIVER_NAME + string "can driver name" + default "can1_drv" + +config CAN_1_DEVICE_NAME_1 + string "can bus 1 device 1 name" + default "can1_dev1" \ No newline at end of file diff --git a/Ubiquitous/XiZi/board/stm32f407-st-discovery/third_party_driver/ethernet/Makefile b/Ubiquitous/XiZi/board/stm32f407-st-discovery/third_party_driver/ethernet/Makefile new file mode 100644 index 0000000..cf27edf --- /dev/null +++ b/Ubiquitous/XiZi/board/stm32f407-st-discovery/third_party_driver/ethernet/Makefile @@ -0,0 +1,4 @@ +SRC_FILES := hardware_ethernet.c connect_ethernet.c ethernetif.c + + +include $(KERNEL_ROOT)/compiler.mk \ No newline at end of file diff --git a/Ubiquitous/XiZi/board/stm32f407-st-discovery/third_party_driver/gpio/Kconfig b/Ubiquitous/XiZi/board/stm32f407-st-discovery/third_party_driver/gpio/Kconfig new file mode 100644 index 0000000..f284f60 --- /dev/null +++ b/Ubiquitous/XiZi/board/stm32f407-st-discovery/third_party_driver/gpio/Kconfig @@ -0,0 +1,12 @@ + +config PIN_BUS_NAME + string "pin bus name" + default "pin" + +config PIN_DRIVER_NAME + string "pin driver name" + default "pin_drv" + +config PIN_DEVICE_NAME + string "pin device name" + default "pin_dev" diff --git a/Ubiquitous/XiZi/board/stm32f407-st-discovery/third_party_driver/gpio/Makefile b/Ubiquitous/XiZi/board/stm32f407-st-discovery/third_party_driver/gpio/Makefile new file mode 100644 index 0000000..12e1dbe --- /dev/null +++ b/Ubiquitous/XiZi/board/stm32f407-st-discovery/third_party_driver/gpio/Makefile @@ -0,0 +1,3 @@ +SRC_FILES := connect_gpio.c hardware_gpio.c + +include $(KERNEL_ROOT)/compiler.mk diff --git a/Ubiquitous/XiZi/board/stm32f407-st-discovery/third_party_driver/i2c/Kconfig b/Ubiquitous/XiZi/board/stm32f407-st-discovery/third_party_driver/i2c/Kconfig new file mode 100644 index 0000000..e9e435d --- /dev/null +++ b/Ubiquitous/XiZi/board/stm32f407-st-discovery/third_party_driver/i2c/Kconfig @@ -0,0 +1,11 @@ +if BSP_USING_I2C + config I2C_BUS_NAME_1 + string "i2c bus 1 name" + default "i2c1" + config I2C_DRV_NAME_1 + string "i2c bus 1 driver name" + default "i2c1_drv" + config I2C_1_DEVICE_NAME_0 + string "i2c bus 1 device 0 name" + default "i2c1_dev0" +endif diff --git a/Ubiquitous/XiZi/board/stm32f407-st-discovery/third_party_driver/i2c/Makefile b/Ubiquitous/XiZi/board/stm32f407-st-discovery/third_party_driver/i2c/Makefile new file mode 100644 index 0000000..5f0faa5 --- /dev/null +++ b/Ubiquitous/XiZi/board/stm32f407-st-discovery/third_party_driver/i2c/Makefile @@ -0,0 +1,3 @@ +SRC_FILES := hardware_i2c.c connect_i2c.c + +include $(KERNEL_ROOT)/compiler.mk diff --git a/Ubiquitous/XiZi/board/stm32f407-st-discovery/third_party_driver/include/connect_adc.h b/Ubiquitous/XiZi/board/stm32f407-st-discovery/third_party_driver/include/connect_adc.h new file mode 100644 index 0000000..ffd3de7 --- /dev/null +++ b/Ubiquitous/XiZi/board/stm32f407-st-discovery/third_party_driver/include/connect_adc.h @@ -0,0 +1,37 @@ +/* +* Copyright (c) 2020 AIIT XUOS Lab +* XiUOS is licensed under Mulan PSL v2. +* You can use this software according to the terms and conditions of the Mulan PSL v2. +* You may obtain a copy of Mulan PSL v2 at: +* http://license.coscl.org.cn/MulanPSL2 +* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, +* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, +* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. +* See the Mulan PSL v2 for more details. +*/ + +/** +* @file connect_adc.h +* @brief define stm32f407-st-discovery adc function and struct +* @version 1.1 +* @author AIIT XUOS Lab +* @date 2021-12-28 +*/ + +#ifndef CONNECT_ADC_H +#define CONNECT_ADC_H + +#include +#include +#include +#include + +struct Stm32HwAdc +{ + ADC_TypeDef *ADCx; + uint8 adc_channel; +}; + +int Stm32HwAdcInit(void); + +#endif diff --git a/Ubiquitous/XiZi/board/stm32f407-st-discovery/third_party_driver/include/connect_can.h b/Ubiquitous/XiZi/board/stm32f407-st-discovery/third_party_driver/include/connect_can.h new file mode 100644 index 0000000..3036b80 --- /dev/null +++ b/Ubiquitous/XiZi/board/stm32f407-st-discovery/third_party_driver/include/connect_can.h @@ -0,0 +1,49 @@ +/* +* Copyright (c) 2020 AIIT XUOS Lab +* XiUOS is licensed under Mulan PSL v2. +* You can use this software according to the terms and conditions of the Mulan PSL v2. +* You may obtain a copy of Mulan PSL v2 at: +* http://license.coscl.org.cn/MulanPSL2 +* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, +* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, +* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. +* See the Mulan PSL v2 for more details. +*/ + +/** +* @file connect_can.h +* @brief define aiit-arm32-board can function and struct +* @version 1.0 +* @author AIIT XUOS Lab +* @date 2021-04-22 +*/ + +#ifndef CONNECT_CAN_H +#define CONNECT_CAN_H + +#include +#include "hardware_can.h" + +#ifdef __cplusplus +extern "C" { +#endif + +struct Stm32Can +{ + CAN_TypeDef *instance; + + char *bus_name; + + CAN_InitTypeDef init; + + uint8 can_flag; + struct CanBus can_bus; +}; + +int Stm32HwCanBusInit(void); + +#ifdef __cplusplus +} +#endif + +#endif \ No newline at end of file diff --git a/Ubiquitous/XiZi/board/stm32f407-st-discovery/third_party_driver/include/connect_dac.h b/Ubiquitous/XiZi/board/stm32f407-st-discovery/third_party_driver/include/connect_dac.h new file mode 100644 index 0000000..e5fa169 --- /dev/null +++ b/Ubiquitous/XiZi/board/stm32f407-st-discovery/third_party_driver/include/connect_dac.h @@ -0,0 +1,37 @@ +/* +* Copyright (c) 2020 AIIT XUOS Lab +* XiUOS is licensed under Mulan PSL v2. +* You can use this software according to the terms and conditions of the Mulan PSL v2. +* You may obtain a copy of Mulan PSL v2 at: +* http://license.coscl.org.cn/MulanPSL2 +* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, +* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, +* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. +* See the Mulan PSL v2 for more details. +*/ + +/** +* @file connect_dac.h +* @brief define stm32f407-st-discovery adc function and struct +* @version 2.0 +* @author AIIT XUOS Lab +* @date 2022-1-10 +*/ + +#ifndef CONNECT_DAC_H +#define CONNECT_DAC_H + +#include +#include +#include +#include + +struct Stm32HwDac +{ + DAC_TypeDef *DACx; + uint16 digital_data; +}; + +int Stm32HwDacInit(void); + +#endif diff --git a/Ubiquitous/XiZi/board/stm32f407-st-discovery/third_party_driver/include/connect_ethernet.h b/Ubiquitous/XiZi/board/stm32f407-st-discovery/third_party_driver/include/connect_ethernet.h new file mode 100644 index 0000000..25c7ce0 --- /dev/null +++ b/Ubiquitous/XiZi/board/stm32f407-st-discovery/third_party_driver/include/connect_ethernet.h @@ -0,0 +1,112 @@ +/** + ****************************************************************************** + * @file connect_ethernet.h + * @author MCD Application Team + * @version V1.0.0 + * @date 31-October-2011 + * @brief STM32F4x7 Ethernet hardware configuration. + ****************************************************************************** + * @attention + * + * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS + * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE + * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY + * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING + * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE + * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * + *

© COPYRIGHT 2011 STMicroelectronics

+ ****************************************************************************** + */ + + /* +* Copyright (c) 2020 AIIT XUOS Lab +* XiUOS is licensed under Mulan PSL v2. +* You can use this software according to the terms and conditions of the Mulan PSL v2. +* You may obtain a copy of Mulan PSL v2 at: +* http://license.coscl.org.cn/MulanPSL2 +* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, +* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, +* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. +* See the Mulan PSL v2 for more details. +*/ + +/** +* @file connect_ethernet.h +* @brief Adapted network software protocol stack and hardware operation functions +* @version 1.0 +* @author AIIT XUOS Lab +* @date 2021-05-29 +*/ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F4x7_ETH_BSP_H +#define __STM32F4x7_ETH_BSP_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ + + + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +#define DP83848_PHY_ADDRESS 0x01 /* Relative to STM324xG-EVAL Board */ + +/* Specific defines for EXTI line, used to manage Ethernet link status */ +#define ETH_LINK_EXTI_LINE EXTI_Line14 +#define ETH_LINK_EXTI_PORT_SOURCE EXTI_PortSourceGPIOB +#define ETH_LINK_EXTI_PIN_SOURCE EXTI_PinSource14 +#define ETH_LINK_EXTI_IRQn EXTI15_10_IRQn +/* PB14 */ +#define ETH_LINK_PIN GPIO_Pin_14 +#define ETH_LINK_GPIO_PORT GPIOB +#define ETH_LINK_GPIO_CLK RCC_AHB1Periph_GPIOB +/* PHY registers */ +#define PHY_MICR 0x11 /* MII Interrupt Control Register */ +#define PHY_MICR_INT_EN ((unsigned short)0x0002) /* PHY Enable interrupts */ +#define PHY_MICR_INT_OE ((unsigned short)0x0001) /* PHY Enable output interrupt events */ +#define PHY_MISR 0x12 /* MII Interrupt Status and Misc. Control Register */ +#define PHY_MISR_LINK_INT_EN ((unsigned short)0x0020) /* Enable Interrupt on change of link status */ +#define PHY_LINK_STATUS ((unsigned short)0x2000) /* PHY link status interrupt mask */ + + + + +#define RMII_MODE // User have to provide the 50 MHz clock by soldering a 50 MHz + // oscillator (ref SM7745HEV-50.0M or equivalent) on the U3 + // footprint located under CN3 and also removing jumper on JP5. + // This oscillator is not provided with the board. + // For more details, please refer to STM3240G-EVAL evaluation + // board User manual (UM1461). + + +//#define MII_MODE + +/* Uncomment the define below to clock the PHY from external 25MHz crystal (only for MII mode) */ +#ifdef MII_MODE + #define PHY_CLOCK_MCO +#endif + + + + + + +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions ------------------------------------------------------- */ +void ETH_BSP_Config(void); +uint32_t Eth_Link_PHYITConfig(uint16_t PHYAddress); +void Eth_Link_EXTIConfig(void); +void Eth_Link_ITHandler(unsigned short PHYAddress); + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F4x7_ETH_BSP_H */ + + +/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ diff --git a/Ubiquitous/XiZi/board/stm32f407-st-discovery/third_party_driver/include/connect_gpio.h b/Ubiquitous/XiZi/board/stm32f407-st-discovery/third_party_driver/include/connect_gpio.h new file mode 100644 index 0000000..3f3c3b0 --- /dev/null +++ b/Ubiquitous/XiZi/board/stm32f407-st-discovery/third_party_driver/include/connect_gpio.h @@ -0,0 +1,36 @@ +/* +* Copyright (c) 2022 AIIT XUOS Lab +* XiUOS is licensed under Mulan PSL v2. +* You can use this software according to the terms and conditions of the Mulan PSL v2. +* You may obtain a copy of Mulan PSL v2 at: +* http://license.coscl.org.cn/MulanPSL2 +* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, +* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, +* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. +* See the Mulan PSL v2 for more details. +*/ + +/** +* @file connect_gpio.h +* @brief define stm32f407-st-discovery-board gpio function and struct +* @version 1.0 +* @author AIIT XUOS Lab +* @date 2022-03-01 +*/ + +#ifndef __CONNECT_GPIO_H_ +#define __CONNECT_GPIO_H_ + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +int Stm32HwGpioInit(void); + +#ifdef __cplusplus +} +#endif + +#endif \ No newline at end of file diff --git a/Ubiquitous/XiZi/board/stm32f407-st-discovery/third_party_driver/include/connect_hwtimer.h b/Ubiquitous/XiZi/board/stm32f407-st-discovery/third_party_driver/include/connect_hwtimer.h new file mode 100644 index 0000000..4b2325a --- /dev/null +++ b/Ubiquitous/XiZi/board/stm32f407-st-discovery/third_party_driver/include/connect_hwtimer.h @@ -0,0 +1,36 @@ +/* +* Copyright (c) 2020 AIIT XUOS Lab +* XiUOS is licensed under Mulan PSL v2. +* You can use this software according to the terms and conditions of the Mulan PSL v2. +* You may obtain a copy of Mulan PSL v2 at: +* http://license.coscl.org.cn/MulanPSL2 +* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, +* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, +* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. +* See the Mulan PSL v2 for more details. +*/ + +/** +* @file connect_hwtimer.h +* @brief define stm32f407-st-discovery-board hwtimer function and struct +* @version 1.0 +* @author AIIT XUOS Lab +* @date 2021-04-25 +*/ + +#ifndef CONNECT_HWTIMER_H +#define CONNECT_HWTIMER_H + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +int Stm32HwTimerInit(void); + +#ifdef __cplusplus +} +#endif + +#endif \ No newline at end of file diff --git a/Ubiquitous/XiZi/board/stm32f407-st-discovery/third_party_driver/include/connect_i2c.h b/Ubiquitous/XiZi/board/stm32f407-st-discovery/third_party_driver/include/connect_i2c.h new file mode 100644 index 0000000..0355414 --- /dev/null +++ b/Ubiquitous/XiZi/board/stm32f407-st-discovery/third_party_driver/include/connect_i2c.h @@ -0,0 +1,37 @@ +/* +* Copyright (c) 2020 AIIT XUOS Lab +* XiUOS is licensed under Mulan PSL v2. +* You can use this software according to the terms and conditions of the Mulan PSL v2. +* You may obtain a copy of Mulan PSL v2 at: +* http://license.coscl.org.cn/MulanPSL2 +* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, +* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, +* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. +* See the Mulan PSL v2 for more details. +*/ + +/** +* @file connect_i2c.h +* @brief define stm32f407-st-discovery-board i2c function and struct +* @version 1.0 +* @author AIIT XUOS Lab +* @date 2021-04-25 +*/ + +#ifndef CONNECT_I2C_H +#define CONNECT_I2C_H + +#include + +#ifdef __cplusplus +extern "C" { +#endif + + +int Stm32HwI2cInit(void); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/Ubiquitous/XiZi/board/stm32f407-st-discovery/third_party_driver/include/connect_rtc.h b/Ubiquitous/XiZi/board/stm32f407-st-discovery/third_party_driver/include/connect_rtc.h new file mode 100644 index 0000000..ea0b7d3 --- /dev/null +++ b/Ubiquitous/XiZi/board/stm32f407-st-discovery/third_party_driver/include/connect_rtc.h @@ -0,0 +1,38 @@ +/* +* Copyright (c) 2020 AIIT XUOS Lab +* XiUOS is licensed under Mulan PSL v2. +* You can use this software according to the terms and conditions of the Mulan PSL v2. +* You may obtain a copy of Mulan PSL v2 at: +* http://license.coscl.org.cn/MulanPSL2 +* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, +* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, +* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. +* See the Mulan PSL v2 for more details. +*/ + +/** +* @file connect_rtc.h +* @brief define stm32f407-st-discovery-board rtc function and struct +* @version 1.0 +* @author AIIT XUOS Lab +* @date 2021-04-25 +*/ + +#ifndef CONNECT_RTC_H +#define CONNECT_RTC_H + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +#define RTC_CLOCK_SOURCE_LSI + +int Stm32HwRtcInit(void); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/Ubiquitous/XiZi/board/stm32f407-st-discovery/third_party_driver/include/connect_sdio.h b/Ubiquitous/XiZi/board/stm32f407-st-discovery/third_party_driver/include/connect_sdio.h new file mode 100644 index 0000000..8305c27 --- /dev/null +++ b/Ubiquitous/XiZi/board/stm32f407-st-discovery/third_party_driver/include/connect_sdio.h @@ -0,0 +1,38 @@ +/* +* Copyright (c) 2020 AIIT XUOS Lab +* XiUOS is licensed under Mulan PSL v2. +* You can use this software according to the terms and conditions of the Mulan PSL v2. +* You may obtain a copy of Mulan PSL v2 at: +* http://license.coscl.org.cn/MulanPSL2 +* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, +* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, +* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. +* See the Mulan PSL v2 for more details. +*/ + +/** +* @file connect_sdio.h +* @brief define stm32f407-st-discovery-board sdio function and struct +* @version 1.0 +* @author AIIT XUOS Lab +* @date 2021-04-25 +*/ + +#ifndef CONNECT_SDIO_H +#define CONNECT_SDIO_H + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +#define SDIO_DMA_MODE 1 + +int HwSdioInit(void); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/Ubiquitous/XiZi/board/stm32f407-st-discovery/third_party_driver/include/connect_spi.h b/Ubiquitous/XiZi/board/stm32f407-st-discovery/third_party_driver/include/connect_spi.h new file mode 100644 index 0000000..7c1a66c --- /dev/null +++ b/Ubiquitous/XiZi/board/stm32f407-st-discovery/third_party_driver/include/connect_spi.h @@ -0,0 +1,80 @@ +/* +* Copyright (c) 2020 AIIT XUOS Lab +* XiUOS is licensed under Mulan PSL v2. +* You can use this software according to the terms and conditions of the Mulan PSL v2. +* You may obtain a copy of Mulan PSL v2 at: +* http://license.coscl.org.cn/MulanPSL2 +* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, +* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, +* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. +* See the Mulan PSL v2 for more details. +*/ + +/** +* @file connect_spi.h +* @brief define stm32f407-st-discovery-board spi function and struct +* @version 1.0 +* @author AIIT XUOS Lab +* @date 2021-04-25 +*/ + +#ifndef CONNECT_SPI_H +#define CONNECT_SPI_H + +#include +#include + +#include "stm32f4xx.h" +#include "hardware_spi.h" +#include "hardware_dma.h" + +#ifdef __cplusplus +extern "C" { +#endif + +#define SPI_USING_RX_DMA_FLAG (1<<0) +#define SPI_USING_TX_DMA_FLAG (1<<1) + +struct Stm32HwSpiCs +{ + GPIO_TypeDef* GPIOx; + uint16_t GPIO_Pin; +}; + +struct Stm32SpiDma +{ + uint32_t dma_rcc; + DMA_Stream_TypeDef *instance; + uint32 channel; + IRQn_Type dma_irq; + DMA_InitTypeDef init; + x_size_t setting_len; + x_size_t last_index; +}; + +struct Stm32Spi +{ + SPI_TypeDef *instance; + + char *bus_name; + + SPI_InitTypeDef init; + + struct + { + struct Stm32SpiDma dma_rx; + struct Stm32SpiDma dma_tx; + }dma; + + uint8 spi_dma_flag; + struct SpiBus spi_bus; +}; + +int Stm32HwSpiInit(void); +x_err_t HwSpiDeviceAttach(const char *bus_name, const char *device_name, GPIO_TypeDef *cs_gpiox, uint16_t cs_gpio_pin); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/Ubiquitous/XiZi/board/stm32f407-st-discovery/third_party_driver/include/connect_usart.h b/Ubiquitous/XiZi/board/stm32f407-st-discovery/third_party_driver/include/connect_usart.h new file mode 100644 index 0000000..b1f15a2 --- /dev/null +++ b/Ubiquitous/XiZi/board/stm32f407-st-discovery/third_party_driver/include/connect_usart.h @@ -0,0 +1,63 @@ +/* +* Copyright (c) 2020 AIIT XUOS Lab +* XiUOS is licensed under Mulan PSL v2. +* You can use this software according to the terms and conditions of the Mulan PSL v2. +* You may obtain a copy of Mulan PSL v2 at: +* http://license.coscl.org.cn/MulanPSL2 +* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, +* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, +* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. +* See the Mulan PSL v2 for more details. +*/ + +/** +* @file connect_usart.h +* @brief define stm32f407-st-discovery-board usart function and struct +* @version 1.0 +* @author AIIT XUOS Lab +* @date 2021-04-25 +*/ + +#ifndef CONNECT_USART_H +#define CONNECT_USART_H + +#include +#include "hardware_usart.h" +#include "hardware_dma.h" + +#ifdef __cplusplus +extern "C" { +#endif + +#define KERNEL_CONSOLE_BUS_NAME SERIAL_BUS_NAME_1 +#define KERNEL_CONSOLE_DRV_NAME SERIAL_DRV_NAME_1 +#define KERNEL_CONSOLE_DEVICE_NAME SERIAL_1_DEVICE_NAME_0 + +struct UsartHwCfg +{ + USART_TypeDef *uart_device; + IRQn_Type irq; +}; + +struct Stm32Usart +{ + struct Stm32UsartDma + { + DMA_Stream_TypeDef *RxStream; + uint32 RxCh; + uint32 RxFlag; + uint8 RxIrqCh; + x_size_t SettingRecvLen; + x_size_t LastRecvIndex; + } dma; + + struct SerialBus serial_bus; +}; + +int Stm32HwUsartInit(void); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/Ubiquitous/XiZi/board/stm32f407-st-discovery/third_party_driver/include/connect_usb.h b/Ubiquitous/XiZi/board/stm32f407-st-discovery/third_party_driver/include/connect_usb.h new file mode 100644 index 0000000..013edef --- /dev/null +++ b/Ubiquitous/XiZi/board/stm32f407-st-discovery/third_party_driver/include/connect_usb.h @@ -0,0 +1,36 @@ +/* +* Copyright (c) 2020 AIIT XUOS Lab +* XiUOS is licensed under Mulan PSL v2. +* You can use this software according to the terms and conditions of the Mulan PSL v2. +* You may obtain a copy of Mulan PSL v2 at: +* http://license.coscl.org.cn/MulanPSL2 +* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, +* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, +* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. +* See the Mulan PSL v2 for more details. +*/ + +/** +* @file connect_usb.h +* @brief define stm32f407-st-discovery-board usb function and struct +* @version 1.0 +* @author AIIT XUOS Lab +* @date 2021-04-25 +*/ + +#ifndef CONNECT_USB_H +#define CONNECT_USB_H + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +int Stm32HwUsbInit(void); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/Ubiquitous/XiZi/board/stm32f407-st-discovery/third_party_driver/include/connect_wdg.h b/Ubiquitous/XiZi/board/stm32f407-st-discovery/third_party_driver/include/connect_wdg.h new file mode 100644 index 0000000..3b36322 --- /dev/null +++ b/Ubiquitous/XiZi/board/stm32f407-st-discovery/third_party_driver/include/connect_wdg.h @@ -0,0 +1,36 @@ +/* +* Copyright (c) 2020 AIIT XUOS Lab +* XiUOS is licensed under Mulan PSL v2. +* You can use this software according to the terms and conditions of the Mulan PSL v2. +* You may obtain a copy of Mulan PSL v2 at: +* http://license.coscl.org.cn/MulanPSL2 +* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, +* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, +* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. +* See the Mulan PSL v2 for more details. +*/ + +/** +* @file connect_wdg.h +* @brief define stm32f407-st-discovery-board watchdog function and struct +* @version 1.0 +* @author AIIT XUOS Lab +* @date 2021-04-25 +*/ + +#ifndef CONNECT_WDG_H +#define CONNECT_WDG_H + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +int HwWdtInit(void); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/Ubiquitous/XiZi/board/stm32f407-st-discovery/third_party_driver/lcd/Kconfig b/Ubiquitous/XiZi/board/stm32f407-st-discovery/third_party_driver/lcd/Kconfig new file mode 100644 index 0000000..8b13789 --- /dev/null +++ b/Ubiquitous/XiZi/board/stm32f407-st-discovery/third_party_driver/lcd/Kconfig @@ -0,0 +1 @@ + diff --git a/Ubiquitous/XiZi/board/stm32f407-st-discovery/third_party_driver/lcd/Makefile b/Ubiquitous/XiZi/board/stm32f407-st-discovery/third_party_driver/lcd/Makefile new file mode 100644 index 0000000..91904d5 --- /dev/null +++ b/Ubiquitous/XiZi/board/stm32f407-st-discovery/third_party_driver/lcd/Makefile @@ -0,0 +1,4 @@ +SRC_FILES := hardware_fsmc.c + + +include $(KERNEL_ROOT)/compiler.mk diff --git a/Ubiquitous/XiZi/board/stm32f407-st-discovery/third_party_driver/rtc/Kconfig b/Ubiquitous/XiZi/board/stm32f407-st-discovery/third_party_driver/rtc/Kconfig new file mode 100644 index 0000000..e853dd4 --- /dev/null +++ b/Ubiquitous/XiZi/board/stm32f407-st-discovery/third_party_driver/rtc/Kconfig @@ -0,0 +1,11 @@ +if BSP_USING_RTC + config RTC_BUS_NAME + string "rtc bus name" + default "rtc" + config RTC_DRV_NAME + string "rtc bus driver name" + default "rtc_drv" + config RTC_DEVICE_NAME + string "rtc bus device name" + default "rtc_dev" +endif diff --git a/Ubiquitous/XiZi/board/stm32f407-st-discovery/third_party_driver/rtc/Makefile b/Ubiquitous/XiZi/board/stm32f407-st-discovery/third_party_driver/rtc/Makefile new file mode 100644 index 0000000..15d4676 --- /dev/null +++ b/Ubiquitous/XiZi/board/stm32f407-st-discovery/third_party_driver/rtc/Makefile @@ -0,0 +1,3 @@ +SRC_FILES := hardware_rtc.c connect_rtc.c + +include $(KERNEL_ROOT)/compiler.mk diff --git a/Ubiquitous/XiZi/board/stm32f407-st-discovery/third_party_driver/rtc/connect_rtc.c b/Ubiquitous/XiZi/board/stm32f407-st-discovery/third_party_driver/rtc/connect_rtc.c new file mode 100644 index 0000000..9c79afe --- /dev/null +++ b/Ubiquitous/XiZi/board/stm32f407-st-discovery/third_party_driver/rtc/connect_rtc.c @@ -0,0 +1,268 @@ +/* +* Copyright (c) 2020 AIIT XUOS Lab +* XiUOS is licensed under Mulan PSL v2. +* You can use this software according to the terms and conditions of the Mulan PSL v2. +* You may obtain a copy of Mulan PSL v2 at: +* http://license.coscl.org.cn/MulanPSL2 +* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, +* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, +* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. +* See the Mulan PSL v2 for more details. +*/ + +/** +* @file connect_rtc.c +* @brief support stm32f407-st-discovery-board rtc function and register to bus framework +* @version 1.0 +* @author AIIT XUOS Lab +* @date 2021-04-25 +*/ + +#include +#include +#include "connect_rtc.h" +#include "hardware_rtc.h" +#include "hardware_rcc.h" +#include "hardware_pwr.h" + +#define RTC_BACKUP_REGISTER 0x32F2 + +static int GetWeekDay(int year, int month, int day) +{ + if (month==1||month==2) { + year -=1; + month +=12; + } + return (day+1+2*month+3*(month+1)/5+year+(year/4)-year/100+year/400)%7+1; +} + +static uint32 RtcConfigure(void *drv, struct BusConfigureInfo *configure_info) +{ + NULL_PARAM_CHECK(drv); + + struct RtcDriver *rtc_drv = (struct RtcDriver *)drv; + struct RtcDrvConfigureParam *drv_param = (struct RtcDrvConfigureParam *)configure_info->private_data; + + int cmd = drv_param->rtc_operation_cmd; + time_t *time = drv_param->time; + + switch (cmd) + { + case OPER_RTC_GET_TIME: + { + struct tm ct; + RTC_TimeTypeDef t; + RTC_DateTypeDef d; + + memset(&ct,0,sizeof(struct tm)); + RTC_GetTime(RTC_Format_BIN,&t); + RTC_GetDate(RTC_Format_BIN,&d); + + ct.tm_year = d.RTC_Year + 100; + ct.tm_mon = d.RTC_Month - 1; + ct.tm_mday = d.RTC_Date; + ct.tm_wday = d.RTC_WeekDay; + + ct.tm_hour = t.RTC_Hours; + ct.tm_min = t.RTC_Minutes; + ct.tm_sec = t.RTC_Seconds; + + *time = mktime(&ct); + } + break; + + case OPER_RTC_SET_TIME: + { + struct tm *ct; + struct tm tm_new; + x_base lock; + RTC_TimeTypeDef RTC_TimeStructure; + RTC_InitTypeDef RTC_InitStructure; + RTC_DateTypeDef RTC_DateStructure; + + lock = CriticalAreaLock(); + ct = localtime(time); + memcpy(&tm_new, ct, sizeof(struct tm)); + CriticalAreaUnLock(lock); + RCC_APB1PeriphClockCmd(RCC_APB1Periph_PWR, ENABLE); + PWR_BackupAccessCmd(ENABLE); + RTC_InitStructure.RTC_AsynchPrediv = 0x7F; + RTC_InitStructure.RTC_SynchPrediv = 0xFF; + RTC_InitStructure.RTC_HourFormat = RTC_HourFormat_24; + RTC_Init(&RTC_InitStructure); + RTC_DateStructure.RTC_Year = tm_new.tm_year - 100; + RTC_DateStructure.RTC_Month = tm_new.tm_mon + 1; + RTC_DateStructure.RTC_Date = tm_new.tm_mday; + RTC_DateStructure.RTC_WeekDay = GetWeekDay(tm_new.tm_year+1900,tm_new.tm_mon+1,tm_new.tm_mday); + RTC_SetDate(RTC_Format_BIN, &RTC_DateStructure); + if (tm_new.tm_hour > 11){ + RTC_TimeStructure.RTC_H12 = RTC_H12_PM; + } + else{ + RTC_TimeStructure.RTC_H12 = RTC_H12_AM; + } + RTC_TimeStructure.RTC_Hours = tm_new.tm_hour; + RTC_TimeStructure.RTC_Minutes = tm_new.tm_min; + RTC_TimeStructure.RTC_Seconds = tm_new.tm_sec; + + RTC_SetTime(RTC_Format_BIN, &RTC_TimeStructure); + + RTC_WriteBackupRegister(RTC_BKP_DR0, 0x32F2); + } + break; + } + + return EOK; +} + +int RtcConfiguration(void) +{ + RCC_APB1PeriphClockCmd(RCC_APB1Periph_PWR, ENABLE); + + PWR_BackupAccessCmd(ENABLE); + +#if defined (RTC_CLOCK_SOURCE_LSI) + RCC_LSICmd(ENABLE); + + while(RCC_GetFlagStatus(RCC_FLAG_LSIRDY) == RESET); + + RCC_RTCCLKConfig(RCC_RTCCLKSource_LSI); + + /* ck_spre(1Hz) = RTCCLK(LSI) /(uwAsynchPrediv + 1)*(uwSynchPrediv + 1)*/ + //uwSynchPrediv = 0xFF; + //uwAsynchPrediv = 0x7F; + +#elif defined (RTC_CLOCK_SOURCE_LSE) + RCC_LSEConfig(RCC_LSE_ON); + + while(RCC_GetFlagStatus(RCC_FLAG_LSERDY) == RESET); + RCC_RTCCLKConfig(RCC_RTCCLKSource_LSE); + +#else +#error Please select the RTC Clock source inside the main.c file +#endif + + RCC_RTCCLKCmd(ENABLE); + + RTC_WaitForSynchro(); + + return 0; +} + +/*manage the rtc device operations*/ +static const struct RtcDevDone dev_done = +{ + .open = NONE, + .close = NONE, + .write = NONE, + .read = NONE, +}; + +static int BoardRtcBusInit(struct RtcBus *rtc_bus, struct RtcDriver *rtc_driver) +{ + x_err_t ret = EOK; + + /*Init the rtc bus */ + ret = RtcBusInit(rtc_bus, RTC_BUS_NAME); + if (EOK != ret) { + KPrintf("hw_rtc_init RtcBusInit error %d\n", ret); + return ERROR; + } + + /*Init the rtc driver*/ + ret = RtcDriverInit(rtc_driver, RTC_DRV_NAME); + if (EOK != ret) { + KPrintf("hw_rtc_init RtcDriverInit error %d\n", ret); + return ERROR; + } + + /*Attach the rtc driver to the rtc bus*/ + ret = RtcDriverAttachToBus(RTC_DRV_NAME, RTC_BUS_NAME); + if (EOK != ret) { + KPrintf("hw_rtc_init RtcDriverAttachToBus error %d\n", ret); + return ERROR; + } + + return ret; +} + +/*Attach the rtc device to the rtc bus*/ +static int BoardRtcDevBend(void) +{ + x_err_t ret = EOK; + + static struct RtcHardwareDevice rtc_device; + memset(&rtc_device, 0, sizeof(struct RtcHardwareDevice)); + + rtc_device.dev_done = &(dev_done); + + ret = RtcDeviceRegister(&rtc_device, NONE, RTC_DEVICE_NAME); + if (EOK != ret) { + KPrintf("hw_rtc_init RtcDeviceInit device %s error %d\n", RTC_DEVICE_NAME, ret); + return ERROR; + } + + ret = RtcDeviceAttachToBus(RTC_DEVICE_NAME, RTC_BUS_NAME); + if (EOK != ret) { + KPrintf("hw_rtc_init RtcDeviceAttachToBus device %s error %d\n", RTC_DEVICE_NAME, ret); + return ERROR; + } + + return ret; +} + +int Stm32HwRtcInit(void) +{ + x_err_t ret = EOK; + + static struct RtcBus rtc_bus; + memset(&rtc_bus, 0, sizeof(struct RtcBus)); + + static struct RtcDriver rtc_driver; + memset(&rtc_driver, 0, sizeof(struct RtcDriver)); + + rtc_driver.configure = &(RtcConfigure); + + ret = BoardRtcBusInit(&rtc_bus, &rtc_driver); + if (EOK != ret) { + KPrintf("hw_rtc_init error ret %u\n", ret); + return ERROR; + } + + ret = BoardRtcDevBend(); + if (EOK != ret) { + KPrintf("hw_rtc_init error ret %u\n", ret); + return ERROR; + } + + if (RTC_BACKUP_REGISTER != RTC_ReadBackupRegister(RTC_BKP_DR0)) { + if (0 != RtcConfiguration()) { + KPrintf("hw_rtc_init RtcConfiguration error...\n"); + return ERROR; + } + } else { + RTC_WaitForSynchro(); + } + + return ret; +} + +#ifdef TOOL_SHELL +void ShowTime(void) +{ + RTC_TimeTypeDef time; + RTC_DateTypeDef date; + RTC_GetDate(RTC_Format_BIN,&date); + RTC_GetTime(RTC_Format_BIN, &time); + KPrintf("Now Time = 20%02d %02d %02d[%02d]-%0.2d:%0.2d:%0.2d \r\n", \ + date.RTC_Year, + date.RTC_Month, + date.RTC_Date, + date.RTC_WeekDay, + time.RTC_Hours, + time.RTC_Minutes, + time.RTC_Seconds); +} +SHELL_EXPORT_CMD(SHELL_CMD_PERMISSION(0)|SHELL_CMD_TYPE(SHELL_TYPE_CMD_FUNC)|SHELL_CMD_PARAM_NUM(0), + ShowTime, ShowTime, Arm test rtc function show time); +#endif diff --git a/Ubiquitous/XiZi/board/stm32f407-st-discovery/third_party_driver/sdio/Kconfig b/Ubiquitous/XiZi/board/stm32f407-st-discovery/third_party_driver/sdio/Kconfig new file mode 100644 index 0000000..a9d1dd3 --- /dev/null +++ b/Ubiquitous/XiZi/board/stm32f407-st-discovery/third_party_driver/sdio/Kconfig @@ -0,0 +1,13 @@ +if BSP_USING_SDIO +config SDIO_BUS_NAME + string "sdio bus name" + default "sdio" + +config SDIO_DRIVER_NAME + string "sdio driver name" + default "sdio_drv" + +config SDIO_DEVICE_NAME + string "sdio device name" + default "sdio_dev" +endif diff --git a/Ubiquitous/XiZi/board/stm32f407-st-discovery/third_party_driver/sdio/Makefile b/Ubiquitous/XiZi/board/stm32f407-st-discovery/third_party_driver/sdio/Makefile new file mode 100644 index 0000000..279499b --- /dev/null +++ b/Ubiquitous/XiZi/board/stm32f407-st-discovery/third_party_driver/sdio/Makefile @@ -0,0 +1,4 @@ +SRC_FILES := connect_sdio.c sdio_sd.c hardware_sdio.c + + +include $(KERNEL_ROOT)/compiler.mk diff --git a/Ubiquitous/XiZi/board/stm32f407-st-discovery/third_party_driver/spi/Kconfig b/Ubiquitous/XiZi/board/stm32f407-st-discovery/third_party_driver/spi/Kconfig new file mode 100644 index 0000000..8ff3c9f --- /dev/null +++ b/Ubiquitous/XiZi/board/stm32f407-st-discovery/third_party_driver/spi/Kconfig @@ -0,0 +1,66 @@ +config BSP_USING_SPI1 +bool "Using spi1 " +default y + + +if BSP_USING_SPI1 + config SPI_BUS_NAME_1 + string "spi bus 1 name" + default "spi1" + config SPI_1_DRV_NAME + string "spi bus 1 driver name" + default "spi1_drv" + config BSP_SPI1_CLK_PIN + int "spi1 clk pin number" + default 29 + config BSP_SPI1_D0_PIN + int "spi1 d0 pin number" + default 30 + config BSP_SPI1_D1_PIN + int "spi1 d1 pin number" + default 31 + menuconfig BSP_SPI1_USING_SS0 + bool "SPI1 Enable SS0" + default y + if BSP_SPI1_USING_SS0 + config SPI_1_DEVICE_NAME_0 + string "spi bus 1 device 0 name" + default "spi1_dev0" + config BSP_SPI1_SS0_PIN + int "spi1 ss0 pin number" + default 32 + endif + menuconfig BSP_SPI1_USING_SS1 + bool "SPI1 Enable SS1" + default y + if BSP_SPI1_USING_SS1 + config SPI_1_DEVICE_NAME_1 + string "spi bus 1 device 1 name" + default "spi1_dev1" + config BSP_SPI1_SS1_PIN + int "spi1 ss1 pin number" + default 33 + endif + menuconfig BSP_SPI1_USING_SS2 + bool "SPI1 Enable SS2" + default n + if BSP_SPI1_USING_SS2 + config SPI_1_DEVICE_NAME_2 + string "spi bus 1 device 2 name" + default "spi1_dev2" + config BSP_SPI1_SS2_PIN + int "spi1 ss2 pin number" + default 26 + endif + menuconfig BSP_SPI1_USING_SS3 + bool "SPI1 Enable SS3" + default n + if BSP_SPI1_USING_SS3 + config SPI_1_DEVICE_NAME_3 + string "spi bus 1 device 3 name" + default "spi1_dev3" + config BSP_SPI1_SS3_PIN + int "spi1 ss3 pin number" + default 27 + endif +endif diff --git a/Ubiquitous/XiZi/board/stm32f407-st-discovery/third_party_driver/spi/Makefile b/Ubiquitous/XiZi/board/stm32f407-st-discovery/third_party_driver/spi/Makefile new file mode 100644 index 0000000..006b43e --- /dev/null +++ b/Ubiquitous/XiZi/board/stm32f407-st-discovery/third_party_driver/spi/Makefile @@ -0,0 +1,7 @@ +SRC_FILES := hardware_spi.c connect_spi.c + +ifeq ($(CONFIG_RESOURCES_SPI_SFUD),y) + SRC_FILES += connect_flash_spi.c +endif + +include $(KERNEL_ROOT)/compiler.mk diff --git a/Ubiquitous/XiZi/board/stm32f407-st-discovery/third_party_driver/spi/connect_flash_spi.c b/Ubiquitous/XiZi/board/stm32f407-st-discovery/third_party_driver/spi/connect_flash_spi.c new file mode 100644 index 0000000..26dc2dd --- /dev/null +++ b/Ubiquitous/XiZi/board/stm32f407-st-discovery/third_party_driver/spi/connect_flash_spi.c @@ -0,0 +1,56 @@ +/* + * Copyright (c) 2020 RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2018-11-27 SummerGift add spi flash port file + */ + +/** +* @file connect_flash_spi.c +* @brief support stm32f407-st-discovery-board spi flash function and register to bus framework +* @version 1.0 +* @author AIIT XUOS Lab +* @date 2021-04-25 +*/ + +/************************************************* +File name: connect_flash_spi.c +Description: support stm32f407-st-discovery-board spi flash bus register function +Others: take RT-Thread v4.0.2/bsp/stm32/stm32f407-atk-explorer/board/ports/spi-flash-init.c + https://github.com/RT-Thread/rt-thread/tree/v4.0.2 +History: +1. Date: 2021-04-25 +Author: AIIT XUOS Lab +Modification: +1. support stm32f407-st-discovery-board spi flash register to spi bus +2. support stm32f407-st-discovery-board spi flash init +*************************************************/ + +#include "hardware_gpio.h" +#include "connect_spi.h" +#include "flash_spi.h" + +int FlashW25qxxSpiDeviceInit(void) +{ +#ifdef BSP_USING_SPI1 + + __IO uint32_t tmpreg = 0x00U; + RCC->AHB1ENR |= RCC_AHB1ENR_GPIOBEN; + tmpreg = RCC->AHB1ENR & RCC_AHB1ENR_GPIOBEN; + (void)tmpreg; + + if (EOK != HwSpiDeviceAttach(SPI_BUS_NAME_1, "spi1_dev0", GPIOB, GPIO_Pin_0)) { + return ERROR; + } + + if (NONE == SpiFlashInit(SPI_BUS_NAME_1, "spi1_dev0", SPI_1_DRV_NAME, "spi1_W25Q64")) { + return ERROR; + } + +#endif + + return EOK; +} \ No newline at end of file diff --git a/Ubiquitous/XiZi/board/stm32f407-st-discovery/third_party_driver/spi/connect_spi.c b/Ubiquitous/XiZi/board/stm32f407-st-discovery/third_party_driver/spi/connect_spi.c new file mode 100644 index 0000000..be515a4 --- /dev/null +++ b/Ubiquitous/XiZi/board/stm32f407-st-discovery/third_party_driver/spi/connect_spi.c @@ -0,0 +1,1639 @@ +/* + * Copyright (c) 2020 RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2018-11-5 SummerGift first version + * 2018-12-11 greedyhao Porting for stm32f7xx + * 2019-01-03 zylx modify DMA initialization and spixfer function + * 2020-01-15 whj4674672 Porting for stm32h7xx + * 2020-06-18 thread-liu Porting for stm32mp1xx + * 2020-10-14 Dozingfiretruck Porting for stm32wbxx + */ + +/** +* @file connect_spi.c +* @brief support stm32f407-st-discovery-board spi function and register to bus framework +* @version 1.0 +* @author AIIT XUOS Lab +* @date 2021-04-25 +*/ + +/************************************************* +File name: connect_spi.c +Description: support stm32f407-st-discovery-board spi configure and spi bus register function +Others: take RT-Thread v4.0.2/bsp/stm32/libraries/HAL_Drivers/drv_spi.c for references + https://github.com/RT-Thread/rt-thread/tree/v4.0.2 +History: +1. Date: 2021-04-25 +Author: AIIT XUOS Lab +Modification: +1. support stm32f407-st-discovery-board spi configure, write and read +2. support stm32f407-st-discovery-board spi bus device and driver register +*************************************************/ + +#include "stm32f4xx.h" +#include "connect_spi.h" +#include "board.h" +#include "misc.h" +#include "hardware_spi.h" +#include "hardware_dma.h" +#include "hardware_gpio.h" +#include "hardware_rcc.h" + +#include +#include + +/* SPI GPIO define */ +#ifdef BSP_USING_SPI1 +#define SPI1_GPIO_NSS GPIO_Pin_4 +#define SPI1_NSS_PIN_SOURCE GPIO_PinSource4 +#define SPI1_GPIO_SCK GPIO_Pin_5 +#define SPI1_SCK_PIN_SOURCE GPIO_PinSource5 +#define SPI1_GPIO_MISO GPIO_Pin_6 +#define SPI1_MISO_PIN_SOURCE GPIO_PinSource6 +#define SPI1_GPIO_MOSI GPIO_Pin_7 +#define SPI1_MOSI_PIN_SOURCE GPIO_PinSource7 +#define SPI1_GPIO GPIOA +#define SPI1_GPIO_RCC RCC_AHB1Periph_GPIOA +#define RCC_APBPeriph_SPI1 RCC_APB2Periph_SPI1 +#endif + +#ifdef BSP_USING_SPI2 +#define SPI2_GPIO_NSS GPIO_Pin_6 +#define SPI2_NSS_PIN_SOURCE GPIO_PinSource6 +#define SPI2_GPIO_SCK GPIO_Pin_13 +#define SPI2_SCK_PIN_SOURCE GPIO_PinSource13 +#define SPI2_GPIO_MISO GPIO_Pin_2 +#define SPI2_MISO_PIN_SOURCE GPIO_PinSource2 +#define SPI2_GPIO_MOSI GPIO_Pin_3 +#define SPI2_MOSI_PIN_SOURCE GPIO_PinSource3 +#define SPI2_GPIO GPIOC +#define SPI2_SCK GPIOB +#define SPI2_GPIO_RCC RCC_AHB1Periph_GPIOC +#define SPI2_GPIO_RCC_SCK RCC_AHB1Periph_GPIOB +#define RCC_APBPeriph_SPI2 RCC_APB1Periph_SPI2 +#endif + +#ifdef BSP_USING_SPI3 +#define SPI3_GPIO_NSS GPIO_Pin_15 +#define SPI3_NSS_PIN_SOURCE GPIO_PinSource15 +#define SPI3_GPIO_SCK GPIO_Pin_10 +#define SPI3_SCK_PIN_SOURCE GPIO_PinSource10 +#define SPI3_GPIO_MISO GPIO_Pin_11 +#define SPI3_MISO_PIN_SOURCE GPIO_PinSource11 +#define SPI3_GPIO_MOSI GPIO_Pin_12 +#define SPI3_MOSI_PIN_SOURCE GPIO_PinSource12 +#define SPI3_GPIO GPIOC +#define SPI3_NSS GPIOA +#define SPI3_GPIO_RCC RCC_AHB1Periph_GPIOC +#define SPI3_GPIO_RCC_NSS RCC_AHB1Periph_GPIOA +#define RCC_APBPeriph_SPI3 RCC_APB2Periph_SPI3 +#endif + +/** + * This function SPI device initialization + * + * @param spi_drv SPI device structure pointer + * + * @param cfg SPI device operating mode configuration structure pointer + * + * @return if successful return EOK + */ + +static x_err_t Stm32SpiInit(struct Stm32Spi *spi_drv, struct SpiMasterParam *cfg) +{ + NULL_PARAM_CHECK(spi_drv); + NULL_PARAM_CHECK(cfg); + + SPI_InitTypeDef *spi_init = &spi_drv->init; + + if (cfg->spi_work_mode & DEV_SPI_SLAVE){ + spi_init->SPI_Mode = SPI_Mode_Slave; + } + else{ + spi_init->SPI_Mode = SPI_Mode_Master; + } + + if (cfg->spi_work_mode & SPI_3WIRE){ + spi_init->SPI_Direction = SPI_Direction_1Line_Rx; + } + else{ + spi_init->SPI_Direction = SPI_Direction_2Lines_FullDuplex; + } + + if (cfg->spi_data_bit_width == 8){ + spi_init->SPI_DataSize = SPI_DataSize_8b; + } + else if (cfg->spi_data_bit_width == 16){ + spi_init->SPI_DataSize = SPI_DataSize_16b; + } + else{ + return EPIO; + } + + if (cfg->spi_work_mode & SPI_LINE_CPHA){ + spi_init->SPI_CPHA = SPI_CPHA_2Edge; + } + else { + spi_init->SPI_CPHA = SPI_CPHA_1Edge; + } + + if (cfg->spi_work_mode & SPI_LINE_CPOL) { + spi_init->SPI_CPOL = SPI_CPOL_High; + } + else{ + spi_init->SPI_CPOL = SPI_CPOL_Low; + } + + if (cfg->spi_work_mode & SPI_NO_CS) { + spi_init->SPI_NSS = SPI_NSS_Soft; + } + else{ + spi_init->SPI_NSS = SPI_NSS_Soft; + } + + uint32_t SPI_APB_CLOCK; + + SPI_APB_CLOCK = system_core_clock>>apb_presc_table[(RCC->CFGR & RCC_CFGR_PPRE2)>> 13U]; + + if (cfg->spi_maxfrequency >= SPI_APB_CLOCK / 2){ + spi_init->SPI_BaudRatePrescaler = SPI_BaudRatePrescaler_2; + } + else if (cfg->spi_maxfrequency >= SPI_APB_CLOCK / 4){ + spi_init->SPI_BaudRatePrescaler = SPI_BaudRatePrescaler_4; + } + else if (cfg->spi_maxfrequency >= SPI_APB_CLOCK / 8){ + spi_init->SPI_BaudRatePrescaler = SPI_BaudRatePrescaler_8; + } + else if (cfg->spi_maxfrequency >= SPI_APB_CLOCK / 16){ + spi_init->SPI_BaudRatePrescaler = SPI_BaudRatePrescaler_16; + } + else if (cfg->spi_maxfrequency >= SPI_APB_CLOCK / 32){ + spi_init->SPI_BaudRatePrescaler = SPI_BaudRatePrescaler_32; + } + else if (cfg->spi_maxfrequency >= SPI_APB_CLOCK / 64){ + spi_init->SPI_BaudRatePrescaler = SPI_BaudRatePrescaler_64; + } + else if (cfg->spi_maxfrequency >= SPI_APB_CLOCK / 128) { + spi_init->SPI_BaudRatePrescaler = SPI_BaudRatePrescaler_128; + } + else { + /* min prescaler 256 */ + spi_init->SPI_BaudRatePrescaler = SPI_BaudRatePrescaler_256; + } + RCC_ClocksTypeDef RCC_ClocksStatus; + RCC_GetClocksFreq(&RCC_ClocksStatus); + + if (cfg->spi_work_mode & SPI_MSB){ + spi_init->SPI_FirstBit = SPI_FirstBit_MSB; /*Highest bit transmit first*/ + } + else{ + spi_init->SPI_FirstBit = SPI_FirstBit_LSB; /*lowest bit transmit first*/ + } + + spi_init->SPI_CRCPolynomial = 7; + + SPI_Init(spi_drv->instance, spi_init); + + SPI_Cmd(spi_drv->instance, ENABLE); + + uint32_t prioritygroup = 0x00U; + /* DMA configuration */ + if (spi_drv->spi_dma_flag & SPI_USING_RX_DMA_FLAG){ + DMA_Init(spi_drv->dma.dma_rx.instance, &spi_drv->dma.dma_rx.init); + + prioritygroup = NVIC_GetPriorityGrouping(); + + NVIC_SetPriority(spi_drv->dma.dma_rx.dma_irq, NVIC_EncodePriority(prioritygroup, 0, 0)); + + NVIC_EnableIRQ(spi_drv->dma.dma_rx.dma_irq); + } + + if (spi_drv->spi_dma_flag & SPI_USING_TX_DMA_FLAG){ + DMA_Init(spi_drv->dma.dma_tx.instance, &spi_drv->dma.dma_tx.init); + + prioritygroup = NVIC_GetPriorityGrouping(); + + NVIC_SetPriority(spi_drv->dma.dma_tx.dma_irq, NVIC_EncodePriority(prioritygroup, 0, 1)); + + NVIC_EnableIRQ(spi_drv->dma.dma_tx.dma_irq); + } + + spi_drv->instance->CR1 |= SPI_CR1_SPE; + + return EOK; +} + +static void DmaSpiConfig(struct SpiBus *spi_bus, uint32_t setting_len, void *rx_base_addr, void *tx_base_addr) +{ + struct Stm32Spi *spi = (struct Stm32Spi *)spi_bus->private_data; + uint32 tmpreg = 0x00U; + NVIC_InitTypeDef NVIC_InitStructure; + + if(spi->spi_dma_flag & SPI_USING_RX_DMA_FLAG) + { + spi->dma.dma_rx.setting_len = setting_len; + DMA_DeInit(spi->dma.dma_rx.instance); + while(DMA_GetCmdStatus(spi->dma.dma_rx.instance) != DISABLE); + spi->dma.dma_rx.init.DMA_Channel = spi->dma.dma_rx.channel; + spi->dma.dma_rx.init.DMA_PeripheralBaseAddr = (uint32_t)&(spi->instance->DR); + spi->dma.dma_rx.init.DMA_Memory0BaseAddr = (uint32_t)rx_base_addr; + spi->dma.dma_rx.init.DMA_DIR = DMA_DIR_PeripheralToMemory; + spi->dma.dma_rx.init.DMA_BufferSize = spi->dma.dma_rx.setting_len; + spi->dma.dma_rx.init.DMA_PeripheralInc = DMA_PeripheralInc_Disable; + spi->dma.dma_rx.init.DMA_MemoryInc = DMA_MemoryInc_Enable; + spi->dma.dma_rx.init.DMA_PeripheralDataSize = DMA_PeripheralDataSize_Byte; + spi->dma.dma_rx.init.DMA_MemoryDataSize = DMA_MemoryDataSize_Byte; + spi->dma.dma_rx.init.DMA_Mode = DMA_Mode_Normal; + spi->dma.dma_rx.init.DMA_Priority = DMA_Priority_High; + spi->dma.dma_rx.init.DMA_FIFOMode = DMA_FIFOMode_Disable; + spi->dma.dma_rx.init.DMA_FIFOThreshold = DMA_FIFOThreshold_Full; + spi->dma.dma_rx.init.DMA_MemoryBurst = DMA_MemoryBurst_INC4; + spi->dma.dma_rx.init.DMA_PeripheralBurst = DMA_PeripheralBurst_INC4; + DMA_Init(spi->dma.dma_rx.instance, &spi->dma.dma_rx.init); + DMA_ITConfig(spi->dma.dma_rx.instance, DMA_IT_TC, ENABLE); + + RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_DMA1, ENABLE); + RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_DMA2, ENABLE); + + DMA_Cmd(spi->dma.dma_rx.instance, ENABLE); + + NVIC_InitStructure.NVIC_IRQChannel = spi->dma.dma_rx.dma_irq; + NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 0; + NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0; + NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE; + NVIC_Init(&NVIC_InitStructure); + + tmpreg = 0x00U; + RCC->AHB1ENR |= spi->dma.dma_rx.dma_rcc; + tmpreg = RCC->AHB1ENR & spi->dma.dma_rx.dma_rcc; + (void)tmpreg; + } + + if(spi->spi_dma_flag & SPI_USING_TX_DMA_FLAG) + { + spi->dma.dma_tx.setting_len = setting_len; + DMA_DeInit(spi->dma.dma_tx.instance); + while(DMA_GetCmdStatus(spi->dma.dma_tx.instance) != DISABLE); + spi->dma.dma_tx.init.DMA_PeripheralBaseAddr = (uint32_t)&(spi->instance->DR); + spi->dma.dma_tx.init.DMA_Memory0BaseAddr = (uint32_t)tx_base_addr; + spi->dma.dma_tx.init.DMA_DIR = DMA_DIR_MemoryToPeripheral; + spi->dma.dma_tx.init.DMA_BufferSize = spi->dma.dma_tx.setting_len; + spi->dma.dma_tx.init.DMA_PeripheralInc = DMA_PeripheralInc_Disable; + spi->dma.dma_tx.init.DMA_MemoryInc = DMA_MemoryInc_Enable; + spi->dma.dma_tx.init.DMA_PeripheralDataSize = DMA_PeripheralDataSize_Byte; + spi->dma.dma_tx.init.DMA_MemoryDataSize = DMA_MemoryDataSize_Byte; + spi->dma.dma_tx.init.DMA_Mode = DMA_Mode_Normal; + spi->dma.dma_tx.init.DMA_Priority = DMA_Priority_Low; + spi->dma.dma_tx.init.DMA_FIFOMode = DMA_FIFOMode_Disable; + spi->dma.dma_tx.init.DMA_FIFOThreshold = DMA_FIFOThreshold_Full; + spi->dma.dma_tx.init.DMA_MemoryBurst = DMA_MemoryBurst_INC4; + spi->dma.dma_tx.init.DMA_PeripheralBurst = DMA_PeripheralBurst_INC4; + DMA_Init(spi->dma.dma_tx.instance, &spi->dma.dma_tx.init); + DMA_ITConfig(spi->dma.dma_tx.instance, DMA_IT_TC, ENABLE); + + RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_DMA1, ENABLE); + RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_DMA2, ENABLE); + + DMA_Cmd(spi->dma.dma_tx.instance, ENABLE); + + NVIC_InitStructure.NVIC_IRQChannel = spi->dma.dma_tx.dma_irq; + NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 0; + NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0; + NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE; + NVIC_Init(&NVIC_InitStructure); + + tmpreg = 0x00U; + RCC->AHB1ENR |= spi->dma.dma_rx.dma_rcc; + tmpreg = RCC->AHB1ENR & spi->dma.dma_rx.dma_rcc; + (void)tmpreg; + } +} + + +static void DmaRxDoneIsr(struct SpiBus *spi_bus) +{ + struct Stm32Spi *spi = (struct Stm32Spi *) spi_bus->bus.private_data; + x_size_t recv_len; + x_base level; + + if (DMA_GetFlagStatus(spi->dma.dma_rx.instance, spi->spi_dma_flag) != RESET) + { + level = CriticalAreaLock(); + + recv_len = spi->dma.dma_rx.setting_len - spi->dma.dma_rx.last_index; + spi->dma.dma_rx.last_index = 0; + CriticalAreaUnLock(level); + DMA_ClearFlag(spi->dma.dma_rx.instance, spi->spi_dma_flag); + } +} + + +static void DmaTxDoneIsr(struct SpiBus *spi_bus) +{ + struct Stm32Spi *spi = (struct Stm32Spi *) spi_bus->bus.private_data; + x_size_t send_len; + x_base level; + + if (DMA_GetFlagStatus(spi->dma.dma_tx.instance, spi->spi_dma_flag) != RESET) + { + level = CriticalAreaLock(); + + send_len = spi->dma.dma_tx.setting_len - spi->dma.dma_tx.last_index; + spi->dma.dma_tx.last_index = 0; + CriticalAreaUnLock(level); + DMA_ClearFlag(spi->dma.dma_tx.instance, spi->spi_dma_flag); + } +} + + +static int SpiWaitUntilTimeout(SPI_InitTypeDef spi_init, SPI_TypeDef *spi_instance, uint32_t flag, uint32_t state, uint32_t time_out, uint32_t tick_start) +{ + while((((spi_instance->SR & flag) == (flag)) ? SET : RESET) != state) + { + if(time_out != 0xFFFFFFFFU) + { + if((time_out == 0U) || ((CurrentTicksGain() * 1000 / TICK_PER_SECOND-tick_start) >= time_out)) + { + spi_instance->CR2 &= (~(SPI_IT_TXE | SPI_IT_RXNE | SPI_IT_ERR)); + + if((spi_init.SPI_Mode == SPI_Mode_Master)&&((spi_init.SPI_Direction == SPI_Direction_1Line_Rx)||(spi_init.SPI_Direction == SPI_Direction_2Lines_RxOnly))) { + /* Disable SPI peripheral */ + spi_instance->CR1 &= (~SPI_CR1_SPE); + } + + return 3; + } + } + } + return 0; +} +/** + * This function SPI sends data through DMA + * + * @param spi_init SPI Init structure + * + * @param spi_instance SPI control handle + * + * @param dma_init DMA Init structure + * + * @param dma_instance DMA Controller + * + * @param p_data Send data buffer address + * + * @param size Amount of data sent + * + * @return if successful return EOK + */ +int SpiTransmitDma(SPI_InitTypeDef spi_init, SPI_TypeDef *spi_instance, DMA_InitTypeDef dma_init, DMA_Stream_TypeDef *dma_instance, uint8_t *p_data, uint16_t size) +{ + int errorcode = 0; + __IO uint16_t tx_xfer_count; + uint8_t *p_txbuff_ptr; + uint16_t tx_xfer_size; + + if((p_data == NONE) || (size == 0)){ + errorcode = 1; + goto error; + } + + tx_xfer_count = size; + p_txbuff_ptr = (uint8_t *)p_data; + tx_xfer_size = size; + + /* Configure communication direction : 1Line */ + if(spi_init.SPI_Direction == SPI_Direction_1Line_Rx){ + spi_instance->CR1 |= SPI_CR1_BIDIOE; + } + + /* Clear DBM bit */ + dma_instance->CR &= (uint32_t)(~DMA_SxCR_DBM); + + /* Configure DMA Stream data length */ + dma_instance->NDTR = tx_xfer_count; + + /* Memory to Peripheral */ + if((dma_init.DMA_DIR) == DMA_DIR_MemoryToPeripheral) + { + /* Configure DMA Stream destination address */ + dma_instance->PAR = spi_instance->DR; + + /* Configure DMA Stream source address */ + dma_instance->M0AR = *p_txbuff_ptr; + } + /* Peripheral to Memory */ + else + { + /* Configure DMA Stream source address */ + dma_instance->PAR = *p_txbuff_ptr; + + /* Configure DMA Stream destination address */ + dma_instance->M0AR = spi_instance->DR; + } + + /* Enable Common interrupts*/ + dma_instance->CR |= DMA_IT_TC | DMA_IT_TE | DMA_IT_DME | DMA_IT_HT; + dma_instance->FCR |= DMA_IT_FE; + dma_instance->CR |= DMA_SxCR_EN; + + /* Check if the SPI is already enabled */ + if((spi_instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE){ + /* Enable SPI peripheral */ + spi_instance->CR1 |= SPI_CR1_SPE; + } + + /* Enable the SPI Error Interrupt Bit */ + spi_instance->CR2 |= SPI_CR2_ERRIE; + + /* Enable Tx DMA Request */ + spi_instance->CR2 |=SPI_CR2_TXDMAEN; + +error : + return errorcode; +} +/** + * This function SPI carries out duplex communication through DMA + * + * @param spi_init SPI Init structure + * + * @param spi_instance SPI control handle + * + * @param dmarx_init DMA Init structure---Rx + * + * @param dmarx_instance DMA Controller + * + * @param dmatx_init DMA Init structure---Tx + * + * @param dmatx_instance DMA Controller + * + * @param p_txdata Send data buffer address + * + * @param p_rxdata Receive data buffer address + * + * @param size Amount of data + * + * @return if successful return EOK + */ +int SpiTransmitreceiveDma(SPI_InitTypeDef spi_init, SPI_TypeDef *spi_instance, DMA_InitTypeDef dmarx_init, DMA_Stream_TypeDef *dmarx_instance, DMA_InitTypeDef dmatx_init, DMA_Stream_TypeDef *dmatx_instance, uint8_t *p_txdata, uint8_t *p_rxdata, uint16_t size) +{ + uint32_t tmp = 0U; + int errorcode = 0; + __IO uint16_t tx_xfer_count; + __IO uint16_t rx_xfer_count; + uint8_t *p_txbuff_ptr; + uint8_t *p_rxbuff_ptr; + uint16_t tx_xfer_size; + uint16_t rx_xfer_size; + + tmp = spi_init.SPI_Mode; + if(!((tmp == SPI_Mode_Master) && (spi_init.SPI_Direction == SPI_Direction_2Lines_FullDuplex))) + { + errorcode = 2; + goto error; + } + + if((p_txdata == NONE ) || (p_rxdata == NONE ) || (size == 0)) + { + errorcode = 1; + goto error; + } + + /* Set the transaction information */ + p_txbuff_ptr = (uint8_t*)p_txdata; + tx_xfer_size = size; + tx_xfer_count = size; + p_rxbuff_ptr = (uint8_t*)p_rxdata; + rx_xfer_size = size; + rx_xfer_count = size; + + /* Clear DBM bit */ + dmarx_instance->CR &= (uint32_t)(~DMA_SxCR_DBM); + + /* Configure DMA Stream data length */ + dmarx_instance->NDTR = rx_xfer_count; + + /* Memory to Peripheral */ + if((dmarx_init.DMA_DIR) == DMA_DIR_MemoryToPeripheral) + { + /* Configure DMA Stream destination address */ + dmarx_instance->PAR = spi_instance->DR; + + /* Configure DMA Stream source address */ + dmarx_instance->M0AR = *p_rxbuff_ptr; + } + /* Peripheral to Memory */ + else + { + /* Configure DMA Stream source address */ + dmarx_instance->PAR = *p_rxbuff_ptr; + + /* Configure DMA Stream destination address */ + dmarx_instance->M0AR = spi_instance->DR; + } + + /* Enable Common interrupts*/ + dmarx_instance->CR |= DMA_IT_TC | DMA_IT_TE | DMA_IT_DME | DMA_IT_HT; + dmarx_instance->FCR |= DMA_IT_FE; + dmarx_instance->CR |= DMA_SxCR_EN; + + /* Enable Rx DMA Request */ + spi_instance->CR2 |= SPI_CR2_RXDMAEN; + + /* Clear DBM bit */ + dmatx_instance->CR &= (uint32_t)(~DMA_SxCR_DBM); + + /* Configure DMA Stream data length */ + dmatx_instance->NDTR = tx_xfer_count; + + /* Memory to Peripheral */ + if((dmatx_init.DMA_DIR) == DMA_DIR_MemoryToPeripheral) + { + /* Configure DMA Stream destination address */ + dmatx_instance->PAR = spi_instance->DR; + + /* Configure DMA Stream source address */ + dmatx_instance->M0AR = *p_txbuff_ptr; + } + /* Peripheral to Memory */ + else{ + /* Configure DMA Stream source address */ + dmatx_instance->PAR = *p_txbuff_ptr; + + /* Configure DMA Stream destination address */ + dmatx_instance->M0AR = spi_instance->DR; + } + + /* Enable Common interrupts*/ + dmatx_instance->CR |= DMA_IT_TC | DMA_IT_TE | DMA_IT_DME | DMA_IT_HT; + dmatx_instance->FCR |= DMA_IT_FE; + dmatx_instance->CR |= DMA_SxCR_EN; + + /* Check if the SPI is already enabled */ + if((spi_instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE){ + /* Enable SPI peripheral */ + spi_instance->CR1 |= SPI_CR1_SPE; + } + /* Enable the SPI Error Interrupt Bit */ + spi_instance->CR2 |= SPI_CR2_ERRIE; + + /* Enable Tx DMA Request */ + spi_instance->CR2 |= SPI_CR2_TXDMAEN; + +error : + return errorcode; +} +/** + * This function SPI receives data through DMA + * + * @param spi_init SPI Init structure + * + * @param spi_instance SPI control handle + * + * @param dmarx_init DMA Init structure---Rx + * + * @param dmarx_instance DMA Controller + * + * @param dmatx_init DMA Init structure---Tx + * + * @param dmatx_instance DMA Controller + * + * @param p_data Receive data buffer address + * + * @param size Amount of data + * + * @return if successful return EOK + */ +int SpiReceiveDma(SPI_InitTypeDef spi_init, SPI_TypeDef *spi_instance, DMA_InitTypeDef dmarx_init, DMA_Stream_TypeDef *dmarx_instance, DMA_InitTypeDef dmatx_init, DMA_Stream_TypeDef *dmatx_instance, uint8_t *p_data, uint16_t size) +{ + int errorcode = 0; + __IO uint16_t rx_xfer_count; + uint8_t *p_rxbuff_ptr; + uint16_t rx_xfer_size; + + if((spi_init.SPI_Direction == SPI_Direction_2Lines_FullDuplex)&&(spi_init.SPI_Mode == SPI_Mode_Master)) { + /* Call transmit-receive function to send Dummy data on Tx line and generate clock on CLK line */ + return SpiTransmitreceiveDma(spi_init, spi_instance, dmarx_init, dmarx_instance, dmatx_init, dmatx_instance, p_data, p_data, size); + } + + if((p_data == NONE) || (size == 0)) + { + errorcode = 1; + goto error; + } + + rx_xfer_count = size; + rx_xfer_size = size; + p_rxbuff_ptr = (uint8_t *)p_data; + + /* Configure communication direction : 1Line */ + if(spi_init.SPI_Direction == SPI_Direction_1Line_Rx) { + spi_instance->CR1 &= (~SPI_CR1_BIDIOE); + } + /* Clear DBM bit */ + dmarx_instance->CR &= (uint32_t)(~DMA_SxCR_DBM); + + /* Configure DMA Stream data length */ + dmarx_instance->NDTR = rx_xfer_count; + + /* Memory to Peripheral */ + if((dmarx_init.DMA_DIR) == DMA_DIR_MemoryToPeripheral){ + /* Configure DMA Stream destination address */ + dmarx_instance->PAR = spi_instance->DR; + /* Configure DMA Stream source address */ + dmarx_instance->M0AR = *p_rxbuff_ptr; + } + /* Peripheral to Memory */ + else + { + /* Configure DMA Stream source address */ + dmarx_instance->PAR = *p_rxbuff_ptr; + + /* Configure DMA Stream destination address */ + dmarx_instance->M0AR = spi_instance->DR; + } + + /* Enable Common interrupts*/ + dmarx_instance->CR |= DMA_IT_TC | DMA_IT_TE | DMA_IT_DME | DMA_IT_HT; + dmarx_instance->FCR |= DMA_IT_FE; + dmarx_instance->CR |= DMA_SxCR_EN; + + /* Check if the SPI is already enabled */ + if((spi_instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE){ + /* Enable SPI peripheral */ + spi_instance->CR1 |= SPI_CR1_SPE; + } + + /* Enable the SPI Error Interrupt Bit */ + spi_instance->CR2 |= SPI_CR2_ERRIE; + + /* Enable Rx DMA Request */ + spi_instance->CR2 |= SPI_CR2_RXDMAEN; + +error: + return errorcode; +} +/** + * This function SPI receives data + * + * @param spi_init SPI Init structure + * + * @param spi_instance SPI control handle + * + * @param p_data Transmit data buffer address + * + * @param size Amount of data + * + * @param Timeout waiting time + * + * @return if successful return EOK + */ +int SpiTransmit(SPI_InitTypeDef spi_init, SPI_TypeDef *spi_instance, uint8_t *p_data, uint16_t size, uint32_t Timeout) +{ + uint32_t tickstart = 0U; + int errorcode = 0; + __IO uint16_t tx_xfer_count; + __IO uint32_t SPITimeout; + + /* Init tickstart for timeout management*/ + tickstart = CurrentTicksGain() * 1000 / TICK_PER_SECOND; + + if((p_data == NONE ) || (size == 0)){ + errorcode = 1; + goto error; + } + + tx_xfer_count = size; + + /* Configure communication direction : 1Line */ + if(spi_init.SPI_Direction == SPI_Direction_1Line_Rx){ + spi_instance->CR1 |= SPI_CR1_BIDIOE; + } + + /* Check if the SPI is already enabled */ + if((spi_instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE){ + /* Enable SPI peripheral */ + spi_instance->CR1 |= SPI_CR1_SPE; + } + + /* Transmit data in 16 Bit mode */ + if(spi_init.SPI_DataSize == SPI_DataSize_16b) + { + if((spi_init.SPI_Mode == SPI_Mode_Slave) || (tx_xfer_count == 0x01)){ + spi_instance->DR = *((uint16_t *)p_data); + + p_data += sizeof(uint16_t); + tx_xfer_count--; + } + /* Transmit data in 16 Bit mode */ + while (tx_xfer_count > 0U) + { + SPITimeout = 0x1000; + /* Wait until TXE flag is set to send data */ + while (SPI_I2S_GetFlagStatus(spi_instance, SPI_I2S_FLAG_TXE) == RESET) + { + if((SPITimeout--) == 0) { + KPrintf("spi time out\n"); + errorcode = 3; + goto error; + } + } + /* Write to the data register and write the data to be written into the transmit buffer */ + spi_instance->DR = *((uint16_t *)p_data); + + p_data += sizeof(uint16_t); + tx_xfer_count--; + } + } + /* Transmit data in 8 Bit mode */ + else + { + if((spi_init.SPI_Mode == SPI_Mode_Slave) || (tx_xfer_count == 0x01U)){ + *((__IO uint8_t*)&spi_instance->DR) = (*p_data); + + p_data += sizeof(uint8_t); + tx_xfer_count--; + } + + while(tx_xfer_count > 0) + { + SPITimeout = 0x1000; + + /* Wait for the send buffer to be empty, TXE event*/ + while (SPI_I2S_GetFlagStatus(spi_instance, SPI_I2S_FLAG_TXE) == RESET) + { + if((SPITimeout--) == 0){ + KPrintf("spi time out\n"); + errorcode = 3; + goto error; + } + } + + /* Write to the data register and write the data to be written into the transmit buffer*/ + *((__IO uint8_t*)&spi_instance->DR) = (*p_data); + + p_data += sizeof(uint8_t); + tx_xfer_count--; + } +} + + /* Wait until TXE flag */ + if(SpiWaitUntilTimeout(spi_init, spi_instance, SPI_FLAG_TXE, SET, Timeout, tickstart) != 0){ + errorcode = 3; + goto error; + } + + /* Check Busy flag */ + if(SpiWaitUntilTimeout(spi_init, spi_instance, SPI_FLAG_BSY, RESET, Timeout, tickstart) != 0){ + errorcode = 1; + goto error; + } + +error: + return errorcode; +} +/** + * This function SPI Transmit and receive + * + * @param spi_init SPI Init structure + * + * @param spi_instance SPI control handle + * + * @param p_txdata Transmit data buffer address + * + * @param p_rxdata receive data buffer address + * + * @param size Amount of data + * + * @param Timeout waiting time + * + * @return if successful return EOK + */ +int SpiTransmitreceive(SPI_InitTypeDef spi_init, SPI_TypeDef *spi_instance, uint8_t *p_txdata, uint8_t *p_rxdata, uint16_t size, uint32_t Timeout) +{ + uint32_t tmp = 0U; + + uint32_t tickstart = 0U; + /* Variable used to alternate Rx and Tx during transfer */ + uint32_t txallowed = 1U; + int errorcode = 0; + __IO uint16_t tx_xfer_count; + __IO uint16_t rx_xfer_count; + + /* Init tickstart for timeout management*/ + tickstart = CurrentTicksGain() * 1000 / TICK_PER_SECOND; + + tmp = spi_init.SPI_Mode; + + if(!((tmp == SPI_Mode_Master) && (spi_init.SPI_Direction == SPI_Direction_2Lines_FullDuplex))){ + errorcode = 2; + goto error; + } + + if((p_txdata == NONE) || (p_rxdata == NONE) || (size == 0)){ + errorcode = 1; + goto error; + } + + tx_xfer_count = size; + rx_xfer_count = size; + + /* Check if the SPI is already enabled */ + if((spi_instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE) { + /* Enable SPI peripheral */ + spi_instance->CR1 |= SPI_CR1_SPE; + } + + /* Transmit and Receive data in 16 Bit mode */ + if(spi_init.SPI_DataSize == SPI_DataSize_16b) + { + if((spi_init.SPI_Mode == SPI_Mode_Slave) || (tx_xfer_count == 0x01U)) { + SPI_I2S_ReceiveData(spi_instance); + spi_instance->DR = *((uint16_t *)p_txdata); + + p_txdata += sizeof(uint16_t); + tx_xfer_count--; + } + while ((tx_xfer_count > 0U) || (rx_xfer_count > 0U)) + { + /* Check TXE flag */ + if(txallowed && (tx_xfer_count > 0U) && (SPI_I2S_GetFlagStatus(spi_instance, SPI_I2S_FLAG_TXE) == SET)) { + SPI_I2S_ReceiveData(spi_instance); + spi_instance->DR = *((uint16_t *)p_txdata); + p_txdata += sizeof(uint16_t); + tx_xfer_count--; + /* Next Data is a reception (Rx). Tx not allowed */ + txallowed = 0U; + } + + /* Check RXNE flag */ + if((rx_xfer_count > 0U) && (SPI_I2S_GetFlagStatus(spi_instance, SPI_I2S_FLAG_RXNE) == SET)) + { + *((uint16_t *)p_rxdata) = spi_instance->DR; + p_rxdata += sizeof(uint16_t); + rx_xfer_count--; + /* Next Data is a Transmission (Tx). Tx is allowed */ + txallowed = 1U; + } + if((Timeout != 0xFFFFFFFFU) && ((CurrentTicksGain() * 1000 / TICK_PER_SECOND-tickstart) >= Timeout)){ + errorcode = 3; + goto error; + } + } + } + /* Transmit and Receive data in 8 Bit mode */ + else + { + if((spi_init.SPI_Mode == SPI_Mode_Slave) || (tx_xfer_count == 0x01U)) + { + SPI_I2S_ReceiveData(spi_instance); + *((__IO uint8_t*)&spi_instance->DR) = (*p_txdata); + + p_txdata += sizeof(uint8_t); + tx_xfer_count--; + } + while((tx_xfer_count > 0U) || (rx_xfer_count > 0U)) + { + /* Wait for the send buffer to be empty, TXE event */ + if (txallowed && (tx_xfer_count > 0U) && (SPI_I2S_GetFlagStatus(spi_instance, SPI_I2S_FLAG_TXE) == SET)) + { + /* Write to the data register and write the data to be written into the transmit buffer */ + SPI_I2S_ReceiveData(spi_instance); + *((__IO uint8_t*)&spi_instance->DR) = (*p_txdata); + + p_txdata += sizeof(uint8_t); + tx_xfer_count--; + txallowed = 0U; + } + + if ((rx_xfer_count > 0U) && SPI_I2S_GetFlagStatus(spi_instance, SPI_I2S_FLAG_RXNE) == SET) + { + *(uint8_t *)p_rxdata = spi_instance->DR; + + p_rxdata += sizeof(uint8_t); + rx_xfer_count--; + txallowed = 1U; + } + if((Timeout != 0xFFFFFFFFU) && ((CurrentTicksGain() * 1000 / TICK_PER_SECOND-tickstart) >= Timeout)) { + errorcode = 3; + goto error; + } + } + } + + /* Wait until TXE flag */ + if(SpiWaitUntilTimeout(spi_init, spi_instance, SPI_FLAG_TXE, SET, Timeout, tickstart) != 0){ + errorcode = 3; + goto error; + } + + /* Check Busy flag */ + if(SpiWaitUntilTimeout(spi_init, spi_instance, SPI_FLAG_BSY, RESET, Timeout, tickstart) != 0){ + errorcode = 1; + goto error; + } + +error : + return errorcode; +} +/** + * This function SPI receive data + * + * @param spi_init SPI Init structure + * + * @param spi_instance SPI control handle + * + * @param p_data data buffer address + * + * @param size Amount of data + * + * @param Timeout waiting time + * + * @return if successful return EOK + */ +int SpiReceive(SPI_InitTypeDef spi_init, SPI_TypeDef *spi_instance, uint8_t *p_data, uint16_t size, uint32_t Timeout) +{ + uint32_t tickstart = 0U; + int errorcode = 0; + __IO uint16_t rx_xfer_count; + __IO uint32_t SPITimeout; + + if((spi_init.SPI_Mode == SPI_Mode_Master) && (spi_init.SPI_Direction == SPI_Direction_2Lines_FullDuplex)) { + /* Call transmit-receive function to send Dummy data on Tx line and generate clock on CLK line */ + return SpiTransmitreceive(spi_init, spi_instance,p_data,p_data,size,Timeout); + } + + /* Init tickstart for timeout management*/ + tickstart = CurrentTicksGain() * 1000 / TICK_PER_SECOND; + + if((p_data == NONE ) || (size == 0)){ + errorcode = 1; + goto error; + } + + rx_xfer_count = size; + + /* Configure communication direction: 1Line */ + if(spi_init.SPI_Direction == SPI_Direction_1Line_Rx){ + spi_instance->CR1 &= (~SPI_CR1_BIDIOE); + } + + /* Check if the SPI is already enabled */ + if((spi_instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE){ + /* Enable SPI peripheral */ + spi_instance->CR1 |= SPI_CR1_SPE; + } + + /* Receive data in 8 Bit mode */ + if(spi_init.SPI_DataSize == SPI_DataSize_8b) + { + /* Transfer loop */ + while(rx_xfer_count > 0U) + { + SPITimeout = 0x1000; + + /* Wait for the send buffer to be empty, TXE event*/ + while (SPI_I2S_GetFlagStatus(spi_instance, SPI_I2S_FLAG_RXNE) == RESET) + { + if((SPITimeout--) == 0){ + KPrintf("spi time out\n"); + errorcode = 3; + goto error; + } + } + + *(uint8_t *)p_data = spi_instance->DR; + + p_data += sizeof(uint8_t); + rx_xfer_count--; + } + } + else + { + /* Transfer loop */ + while(rx_xfer_count > 0U) + { + SPITimeout = 0x1000; + /* Check the RXNE flag */ + while (SPI_I2S_GetFlagStatus(spi_instance, SPI_I2S_FLAG_RXNE) == RESET) + { + if((SPITimeout--) == 0) + { + KPrintf("spi time out\n"); + errorcode = 3; + goto error; + } + } + *((uint16_t*)p_data) = spi_instance->DR; + p_data += sizeof(uint16_t); + rx_xfer_count--; + } + } + + /* Check the end of the transaction */ + if((spi_init.SPI_Mode == SPI_Mode_Master)&&((spi_init.SPI_Direction == SPI_Direction_1Line_Rx)||(spi_init.SPI_Direction == SPI_Direction_2Lines_RxOnly))) + { + /* Disable SPI peripheral */ + spi_instance->CR1 &= (~SPI_CR1_SPE); + } + +error : + return errorcode; +} + +/** + * This function SPI write data + * + * @param spi_dev SPI device structure handle + * + * @param spi_datacfg SPI device information structure handle + * + * @return datacfg length + */ +static uint32 Stm32SpiWriteData(struct SpiHardwareDevice *spi_dev, struct SpiDataStandard *spi_datacfg) +{ + int state; + x_size_t message_length, already_send_length; + uint16 send_length; + const uint8 *WriteBuf; + + NULL_PARAM_CHECK(spi_dev); + NULL_PARAM_CHECK(spi_datacfg); + + struct Stm32Spi *StmSpi = CONTAINER_OF(spi_dev->haldev.owner_bus, struct Stm32Spi, spi_bus); + SPI_TypeDef *spi_instance = StmSpi->instance; + SPI_InitTypeDef *spi_init = &StmSpi->init; + struct Stm32HwSpiCs *cs = (struct Stm32HwSpiCs *)spi_dev->private_data; + + while(NONE != spi_datacfg) { + if(spi_datacfg->spi_chip_select) { + GPIO_WriteBit(cs->GPIOx, cs->GPIO_Pin, Bit_RESET); + } + + message_length = spi_datacfg->length; + WriteBuf = spi_datacfg->tx_buff; + while (message_length) { + if (message_length > 65535){ + send_length = 65535; + message_length = message_length - 65535; + } else { + send_length = message_length; + message_length = 0; + } + + /* calculate the start address */ + already_send_length = spi_datacfg->length - send_length - message_length; + WriteBuf = (uint8 *)spi_datacfg->tx_buff + already_send_length; + + /* start once data exchange in DMA mode */ + if (spi_datacfg->tx_buff) { + if (StmSpi->spi_dma_flag & SPI_USING_TX_DMA_FLAG) { + state = SpiTransmitDma(*spi_init, spi_instance, StmSpi->dma.dma_tx.init, StmSpi->dma.dma_tx.instance, (uint8_t *)WriteBuf, send_length); + } else { + state = SpiTransmit(*spi_init, spi_instance, (uint8_t *)WriteBuf, send_length, 1000); + } + } + + if (state != 0) { + KPrintf("spi write error : %d\n", state); + spi_datacfg->length = 0; + } + } + + if (spi_datacfg->spi_cs_release) { + GPIO_WriteBit(cs->GPIOx, cs->GPIO_Pin, Bit_SET); + } + + spi_datacfg = spi_datacfg->next; + } + + return EOK; +} + +/** + * This function SPI read data + * + * @param spi_dev SPI device structure handle + * + * @param spi_datacfg SPI device information structure handle + * + * @return datacfg length + */ +static uint32 Stm32SpiReadData(struct SpiHardwareDevice *spi_dev, struct SpiDataStandard *spi_datacfg) +{ + int state; + x_size_t message_length, already_send_length; + uint16 read_length, spi_read_length = 0; + const uint8 *ReadBuf; + + NULL_PARAM_CHECK(spi_dev); + NULL_PARAM_CHECK(spi_datacfg); + + struct Stm32Spi *StmSpi = CONTAINER_OF(spi_dev->haldev.owner_bus, struct Stm32Spi, spi_bus); + SPI_TypeDef *spi_instance = StmSpi->instance; + SPI_InitTypeDef *spi_init = &StmSpi->init; + struct Stm32HwSpiCs *cs = (struct Stm32HwSpiCs *)spi_dev->private_data; + + while (NONE != spi_datacfg) { + if (spi_datacfg->spi_chip_select) { + GPIO_WriteBit(cs->GPIOx, cs->GPIO_Pin, Bit_RESET); + } + + message_length = spi_datacfg->length; + ReadBuf = spi_datacfg->rx_buff; + while (message_length) { + if (message_length > 65535) { + read_length = 65535; + message_length = message_length - 65535; + } else { + read_length = message_length; + message_length = 0; + } + + /* calculate the start address */ + already_send_length = spi_datacfg->length - read_length - message_length; + ReadBuf = (uint8 *)spi_datacfg->rx_buff + already_send_length; + + /* start once data exchange in DMA mode */ + if (spi_datacfg->rx_buff) { + //memset((uint8_t *)ReadBuf, 0xff, read_length); + if (StmSpi->spi_dma_flag & SPI_USING_RX_DMA_FLAG) { + state = SpiReceiveDma(*spi_init, spi_instance, StmSpi->dma.dma_rx.init, StmSpi->dma.dma_rx.instance, StmSpi->dma.dma_tx.init, StmSpi->dma.dma_tx.instance, (uint8_t *)ReadBuf, read_length); + } else { + state = SpiReceive(*spi_init, spi_instance, (uint8_t *)ReadBuf, read_length, 1000); + } + } + + if (state != 0) { + KPrintf("spi read error : %d\n", state); + spi_datacfg->length = 0; + } + } + + if (spi_datacfg->spi_cs_release) { + GPIO_WriteBit(cs->GPIOx, cs->GPIO_Pin, Bit_SET); + } + + spi_read_length += spi_datacfg->length; + spi_datacfg = spi_datacfg->next; + } + + return spi_read_length; +} + +/** + * This function SPI driver initialization function + * + * @param spi_drv SPI driver structure handle + * + * @return if successful return EOK + */ +static uint32 SpiDrvInit(struct SpiDriver *spi_drv) +{ + NULL_PARAM_CHECK(spi_drv); + + SpiDeviceParam *dev_param = (SpiDeviceParam *)(spi_drv->driver.private_data); + + struct Stm32Spi *StmSpi = CONTAINER_OF(spi_drv->driver.owner_bus, struct Stm32Spi, spi_bus); + + return Stm32SpiInit(StmSpi, dev_param->spi_master_param); +} + +/** + * This function SPI driver configuration param + * + * @param spi_drv SPI driver structure handle + * + * @param spi_param SPI master param structure handle + * + * @return if successful return EOK + */ +static uint32 SpiDrvConfigure(struct SpiDriver *spi_drv, struct SpiMasterParam *spi_param) +{ + NULL_PARAM_CHECK(spi_drv); + NULL_PARAM_CHECK(spi_param); + + SpiDeviceParam *dev_param = (SpiDeviceParam *)(spi_drv->driver.private_data); + + dev_param->spi_master_param = spi_param; + dev_param->spi_master_param->spi_work_mode = dev_param->spi_master_param->spi_work_mode & SPI_MODE_MASK; + + return EOK; +} + +/*Configure the spi device param, make sure struct (configure_info->private_data) = (SpiMasterParam)*/ +static uint32 Stm32SpiDrvConfigure(void *drv, struct BusConfigureInfo *configure_info) +{ + NULL_PARAM_CHECK(drv); + NULL_PARAM_CHECK(configure_info); + + x_err_t ret = EOK; + struct SpiDriver *spi_drv = (struct SpiDriver *)drv; + struct SpiMasterParam *spi_param; + + switch (configure_info->configure_cmd) + { + case OPE_INT: + ret = SpiDrvInit(spi_drv); + break; + case OPE_CFG: + spi_param = (struct SpiMasterParam *)configure_info->private_data; + ret = SpiDrvConfigure(spi_drv, spi_param); + break; + default: + break; + } + + return ret; +} + +/*manage the spi device operations*/ +static const struct SpiDevDone spi_dev_done = +{ + .dev_open = NONE, + .dev_close = NONE, + .dev_write = Stm32SpiWriteData, + .dev_read = Stm32SpiReadData, +}; + +#if defined(BSP_USING_SPI1) +struct Stm32Spi spi1; +#if defined(BSP_SPI1_TX_USING_DMA) +void DMA2_Stream3_IRQHandler(int irq_num, void *arg) +{ + DmaTxDoneIsr(&spi1.spi_bus); +} +DECLARE_HW_IRQ(DMA2_Stream3_IRQn, DMA2_Stream3_IRQHandler, NONE); +#endif + +#if defined(BSP_SPI1_RX_USING_DMA) +void DMA2_Stream0_IRQHandler(int irq_num, void *arg) +{ + DmaRxDoneIsr(&spi1.spi_bus); +} +DECLARE_HW_IRQ(DMA2_Stream0_IRQn, DMA2_Stream0_IRQHandler, NONE); +#endif +#endif + +#if defined(BSP_USING_SPI2) +struct Stm32Spi spi2; +#if defined(BSP_SPI2_TX_USING_DMA) +void DMA1_Stream4_IRQHandler(int irq_num, void *arg) +{ + DmaTxDoneIsr(&spi2.spi_bus); +} +DECLARE_HW_IRQ(DMA1_Stream4_IRQn, DMA1_Stream4_IRQHandler, NONE); +#endif + +#if defined(BSP_SPI2_RX_USING_DMA) +void DMA1_Stream3_IRQHandler(int irq_num, void *arg) +{ + DmaTxDoneIsr(&spi2.spi_bus); +} +DECLARE_HW_IRQ(DMA1_Stream3_IRQn, DMA1_Stream3_IRQHandler, NONE); +#endif +#endif + +#if defined(BSP_USING_SPI3) +struct Stm32Spi spi3; +#if defined(BSP_SPI3_TX_USING_DMA) +void DMA1_Stream7_IRQHandler(int irq_num, void *arg) +{ + DmaTxDoneIsr(&spi3.spi_bus); +} +DECLARE_HW_IRQ(DMA1_Stream7_IRQn, DMA1_Stream7_IRQHandler, NONE); +#endif + +#if defined(BSP_SPI3_RX_USING_DMA) +/** + * This function DMA2 Stream2 Interrupt service function + * + * @return none + */ +void DMA1_Stream2_IRQHandler(int irq_num, void *arg) +{ + DmaRxDoneIsr(&spi3.spi_bus); +} +DECLARE_HW_IRQ(DMA1_Stream2_IRQn, DMA1_Stream2_IRQHandler, NONE); +#endif +#endif + +/** + * This function RCC clock configuration function + * + * @return none + */ +static void RCCConfiguration(void) +{ +#ifdef BSP_USING_SPI1 + RCC_AHB1PeriphClockCmd(SPI1_GPIO_RCC, ENABLE); + + RCC_APB2PeriphClockCmd(RCC_APBPeriph_SPI1, ENABLE); +#endif + +#ifdef BSP_USING_SPI2 + RCC_AHB1PeriphClockCmd(SPI2_GPIO_RCC | SPI2_GPIO_RCC_SCK, ENABLE); + + RCC_APB1PeriphClockCmd(RCC_APBPeriph_SPI2, ENABLE); +#endif + +#ifdef BSP_USING_SPI3 + RCC_AHB1PeriphClockCmd(SPI3_GPIO_RCC | SPI3_GPIO_RCC_NSS, ENABLE); + + RCC_APB2PeriphClockCmd(RCC_APBPeriph_SPI3, ENABLE); +#endif +} +/** + * This function GPIO Configuration function + * + * @return none + */ +static void GPIOConfiguration(void) +{ + GPIO_InitTypeDef gpio_initstructure; + + gpio_initstructure.GPIO_Mode = GPIO_Mode_AF; /* Reuse function */ + gpio_initstructure.GPIO_OType = GPIO_OType_PP; /* Multiplex push-pull*/ + gpio_initstructure.GPIO_PuPd = GPIO_PuPd_UP; /* pull up */ + gpio_initstructure.GPIO_Speed = GPIO_Speed_2MHz; /* Level reversal speed */ + +#ifdef BSP_USING_SPI1 + gpio_initstructure.GPIO_Pin = SPI1_GPIO_NSS | SPI1_GPIO_SCK | SPI1_GPIO_MISO | SPI1_GPIO_MOSI; + /* Connect alternate function */ + GPIO_PinAFConfig(SPI1_GPIO, SPI1_NSS_PIN_SOURCE, GPIO_AF_SPI1); + GPIO_PinAFConfig(SPI1_GPIO, SPI1_SCK_PIN_SOURCE, GPIO_AF_SPI1); + GPIO_PinAFConfig(SPI1_GPIO, SPI1_MISO_PIN_SOURCE, GPIO_AF_SPI1); + GPIO_PinAFConfig(SPI1_GPIO, SPI1_MOSI_PIN_SOURCE, GPIO_AF_SPI1); + + GPIO_Init(SPI1_GPIO, &gpio_initstructure); /*SPI pin initialization*/ +#endif + +#ifdef BSP_USING_SPI2 + gpio_initstructure.GPIO_Pin = SPI2_GPIO_SCK; + /* Connect alternate function */ + GPIO_PinAFConfig(SPI2_SCK, SPI2_SCK_PIN_SOURCE, GPIO_AF_SPI2); + + GPIO_Init(SPI2_SCK, &gpio_initstructure); + + gpio_initstructure.GPIO_Pin = SPI2_GPIO_NSS | SPI2_GPIO_MISO | SPI2_GPIO_MOSI; + /* Connect alternate function */ + GPIO_PinAFConfig(SPI2_GPIO, SPI2_NSS_PIN_SOURCE, GPIO_AF_SPI2); + GPIO_PinAFConfig(SPI2_GPIO, SPI2_MISO_PIN_SOURCE, GPIO_AF_SPI2); + GPIO_PinAFConfig(SPI2_GPIO, SPI2_MOSI_PIN_SOURCE, GPIO_AF_SPI2); + + GPIO_Init(SPI2_GPIO, &gpio_initstructure); +#endif + +#ifdef BSP_USING_SPI3 + gpio_initstructure.GPIO_Pin = SPI3_GPIO_NSS; + /* Connect alternate function */ + GPIO_PinAFConfig(SPI3_NSS, SPI3_NSS_PIN_SOURCE, GPIO_AF_SPI3); + + GPIO_Init(SPI3_NSS, &gpio_initstructure); + + gpio_initstructure.GPIO_Pin = SPI3_GPIO_SCK | SPI3_GPIO_MISO | SPI3_GPIO_MOSI; + GPIO_PinAFConfig(SPI3_GPIO, SPI3_SCK_PIN_SOURCE, GPIO_AF_SPI3); + GPIO_PinAFConfig(SPI3_GPIO, SPI3_MISO_PIN_SOURCE, GPIO_AF_SPI3); + GPIO_PinAFConfig(SPI3_GPIO, SPI3_MOSI_PIN_SOURCE, GPIO_AF_SPI3); + + GPIO_Init(SPI3_GPIO, &gpio_initstructure); +#endif +} + +/** + * This function Init the spi bus 、spi driver and attach to the bus + * + * @param spi_bus Spi bus info pointer + * + * @param spi_driver Spi driver info pointer + * + * @return EOK + */ +static int BoardSpiBusInit(struct Stm32Spi *stm32spi_bus, struct SpiDriver *spi_driver, char* drv_name) +{ + x_err_t ret = EOK; + + /*Init the spi bus */ + ret = SpiBusInit(&stm32spi_bus->spi_bus, stm32spi_bus->bus_name); + if (EOK != ret) { + KPrintf("Board_Spi_init SpiBusInit error %d\n", ret); + return ERROR; + } + + /*Init the spi driver*/ + ret = SpiDriverInit(spi_driver, drv_name); + if (EOK != ret) { + KPrintf("Board_Spi_init SpiDriverInit error %d\n", ret); + return ERROR; + } + + /*Attach the spi driver to the spi bus*/ + ret = SpiDriverAttachToBus(drv_name, stm32spi_bus->bus_name); + if (EOK != ret) { + KPrintf("Board_Spi_init SpiDriverAttachToBus error %d\n", ret); + return ERROR; + } + + return ret; +} + + +/** + * This function SPI bus initialization + * + * @return EOK + */ +static int Stm32HwSpiBusInit(void) +{ + x_err_t ret = EOK; + struct Stm32Spi *StmSpiBus; + + RCCConfiguration(); + GPIOConfiguration(); + +#ifdef BSP_USING_SPI1 + StmSpiBus = &spi1; + StmSpiBus->instance = SPI1; + StmSpiBus->bus_name = SPI_BUS_NAME_1; + StmSpiBus->spi_bus.private_data = &spi1; + DmaSpiConfig(&StmSpiBus->spi_bus, 0, NONE, NONE); + + static struct SpiDriver spi_driver_1; + memset(&spi_driver_1, 0, sizeof(struct SpiDriver)); + + spi_driver_1.configure = &(Stm32SpiDrvConfigure); + + ret = BoardSpiBusInit(StmSpiBus, &spi_driver_1, SPI_1_DRV_NAME); + if (EOK != ret) { + KPrintf("Board_Spi_Init spi_bus_init %s error ret %u\n", StmSpiBus->bus_name, ret); + return ERROR; + } +#endif + +#ifdef BSP_USING_SPI2 + StmSpiBus = &spi2; + StmSpiBus->instance = SPI2; + StmSpiBus->bus_name = SPI_BUS_NAME_2; + StmSpiBus->spi_bus.private_data = &spi2; + DmaSpiConfig(&StmSpiBus->spi_bus, 0, NONE, NONE); + + static struct SpiDriver spi_driver_2; + memset(&spi_driver_2, 0, sizeof(struct SpiDriver)); + + spi_driver_2.configure = &(Stm32SpiDrvConfigure); + + ret = BoardSpiBusInit(StmSpiBus, &spi_driver_2, SPI_2_DRV_NAME); + if (EOK != ret) { + KPrintf("Board_Spi_Init spi_bus_init %s error ret %u\n", StmSpiBus->bus_name, ret); + return ERROR; + } +#endif + +#ifdef BSP_USING_SPI3 + StmSpiBus = &spi3; + StmSpiBus->instance = SPI3; + StmSpiBus->bus_name = SPI_BUS_NAME_3; + StmSpiBus->spi_bus.private_data = &spi3; + DmaSpiConfig(&StmSpiBus->spi_bus, 0, NONE, NONE); + + static struct SpiDriver spi_driver_3; + memset(&spi_driver_3, 0, sizeof(struct SpiDriver)); + + spi_driver_3.configure = &(Stm32SpiDrvConfigure); + + ret = BoardSpiBusInit(StmSpiBus, &spi_driver_3, SPI_3_DRV_NAME); + if (EOK != ret) { + KPrintf("Board_Spi_Init spi_bus_init %s error ret %u\n", StmSpiBus->bus_name, ret); + return ERROR; + } +#endif + return EOK; +} + +/** + * This function Mount the spi device to the bus + * + * @param bus_name Bus Name + * + * @param device_name spi device name + * + * @param cs_gpiox GPIO pin configuration handle + * + * @param cs_gpio_pin GPIO number + * + * @return EOK + */ +x_err_t HwSpiDeviceAttach(const char *bus_name, const char *device_name, GPIO_TypeDef *cs_gpiox, uint16_t cs_gpio_pin) + +{ + NULL_PARAM_CHECK(bus_name); + NULL_PARAM_CHECK(device_name); + + x_err_t result; + struct SpiHardwareDevice *spi_device; + struct Stm32HwSpiCs *cs_pin_param; + static SpiDeviceParam spi_dev_param; + memset(&spi_dev_param, 0, sizeof(SpiDeviceParam)); + + /* initialize the cs pin && select the slave*/ + GPIO_InitTypeDef GPIO_Initure; + GPIO_Initure.GPIO_Pin = cs_gpio_pin; + GPIO_Initure.GPIO_Mode = GPIO_Mode_OUT; + GPIO_Initure.GPIO_PuPd = GPIO_PuPd_UP; + GPIO_Initure.GPIO_Speed = GPIO_Speed_50MHz; + GPIO_Init(cs_gpiox, &GPIO_Initure); + GPIO_WriteBit(cs_gpiox, cs_gpio_pin, Bit_SET); + + /* attach the device to spi bus*/ + spi_device = (struct SpiHardwareDevice *)x_malloc(sizeof(struct SpiHardwareDevice)); + CHECK(spi_device); + memset(spi_device, 0, sizeof(struct SpiHardwareDevice)); + cs_pin_param = (struct Stm32HwSpiCs *)x_malloc(sizeof(struct Stm32HwSpiCs)); + CHECK(cs_pin_param); + memset(cs_pin_param, 0, sizeof(struct Stm32HwSpiCs)); + cs_pin_param->GPIOx = cs_gpiox; + cs_pin_param->GPIO_Pin = cs_gpio_pin; + + spi_device->spi_dev_done = &spi_dev_done; + spi_device->private_data = (void *)cs_pin_param; + + result = SpiDeviceRegister(spi_device, (void *)&spi_dev_param, device_name); + if (result != EOK) { + SYS_ERR("%s device %p register faild, %d\n", device_name, spi_device, result); + } + + result = SpiDeviceAttachToBus(device_name, bus_name); + if (result != EOK) { + SYS_ERR("%s attach to %s faild, %d\n", device_name, bus_name, result); + } + + CHECK(result == EOK); + + return result; +} + +/** + * This function Get DMA information + * + * @return none + */ +static void Stm32GetDmaInfo(void) +{ +#ifdef BSP_SPI1_RX_USING_DMA /*SPI1 uses DMA receive enable*/ + spi1.spi_dma_flag |= SPI_USING_RX_DMA_FLAG; + spi1.dma.dma_rx.instance = DMA2_Stream0; + spi1.dma.dma_rx.dma_rcc = RCC_AHB1ENR_DMA2EN; + spi1.dma.dma_rx.channel = DMA_Channel_3; + spi1.dma.dma_rx.dma_irq = DMA2_Stream0_IRQn; +#endif +#ifdef BSP_SPI1_TX_USING_DMA /*SPI1 uses DMA send enable*/ + spi1.spi_dma_flag |= SPI_USING_TX_DMA_FLAG; + spi1.dma.dma_tx.instance = DMA2_Stream3; + spi1.dma.dma_tx.dma_rcc = RCC_AHB1ENR_DMA2EN; + spi1.dma.dma_tx.channel = DMA_Channel_3; + spi1.dma.dma_tx.dma_irq = DMA2_Stream3_IRQn; +#endif + +#ifdef BSP_SPI2_RX_USING_DMA /*SPI2 uses DMA receive enable*/ + spi2.spi_dma_flag |= SPI_USING_RX_DMA_FLAG; + spi2.dma.dma_rx.instance = DMA1_Stream3; /* DMA1 Data stream 3*/ + spi2.dma.dma_rx.dma_rcc = RCC_AHB1ENR_DMA1EN; + spi2.dma.dma_rx.channel = DMA_Channel_0; + spi2.dma.dma_rx.dma_irq = DMA1_Stream3_IRQn; +#endif +#ifdef BSP_SPI2_TX_USING_DMA /*SPI2 uses DMA send enable*/ + spi2.spi_dma_flag |= SPI_USING_TX_DMA_FLAG; + spi2.dma.dma_tx.instance = DMA1_Stream4; /* DMA1 Data stream 4*/ + spi2.dma.dma_tx.dma_rcc = RCC_AHB1ENR_DMA1EN; + spi2.dma.dma_tx.channel = DMA_Channel_0; + spi2.dma.dma_tx.dma_irq = DMA1_Stream4_IRQn; /*Enable DMA interrupt line*/ +#endif + +#ifdef BSP_SPI3_RX_USING_DMA /*SPI3 uses DMA receive enable*/ + spi3.spi_dma_flag |= SPI_USING_RX_DMA_FLAG; + spi3.dma.dma_rx.instance = DMA1_Stream2; /* DMA1 Data stream 2*/ + spi3.dma.dma_rx.dma_rcc = RCC_AHB1ENR_DMA1EN; + spi3.dma.dma_rx.channel = DMA_Channel_0; + spi3.dma.dma_rx.dma_irq = DMA1_Stream2_IRQn; /*Enable DMA interrupt line*/ +#endif +#ifdef BSP_SPI3_TX_USING_DMA /*SPI3 uses DMA send enable*/ + spi3.spi_dma_flag |= SPI_USING_TX_DMA_FLAG; + spi3.dma.dma_tx.instance = DMA1_Stream7; /* DMA1 Data stream 7*/ + spi3.dma.dma_tx.dma_rcc = RCC_AHB1ENR_DMA1EN; + spi3.dma.dma_tx.channel = DMA_Channel_0; + spi3.dma.dma_tx.dma_irq = DMA1_Stream7_IRQn; /*Enable DMA interrupt line*/ +#endif +} + +/** + * This function hardware spi initialization + * + * @return EOK + */ +int Stm32HwSpiInit(void) +{ + Stm32GetDmaInfo(); + return Stm32HwSpiBusInit(); +} diff --git a/Ubiquitous/XiZi/board/stm32f407-st-discovery/third_party_driver/timer/Kconfig b/Ubiquitous/XiZi/board/stm32f407-st-discovery/third_party_driver/timer/Kconfig new file mode 100644 index 0000000..33f325e --- /dev/null +++ b/Ubiquitous/XiZi/board/stm32f407-st-discovery/third_party_driver/timer/Kconfig @@ -0,0 +1,19 @@ +if BSP_USING_HWTIMER + config HWTIMER_BUS_NAME_2 + string "hwtimer bus name" + default "hwtim2" + + menuconfig ENABLE_TIM2 + bool "enable TIM2" + default y + + if ENABLE_TIM2 + config HWTIMER_2_DEVICE_NAME_2 + string "TIM2 dev name" + default "hwtim2_dev2" + + config HWTIMER_DRIVER_NAME_2 + string "TIM2 drv name" + default "hwtim2_drv" + endif +endif diff --git a/Ubiquitous/XiZi/board/stm32f407-st-discovery/third_party_driver/timer/Makefile b/Ubiquitous/XiZi/board/stm32f407-st-discovery/third_party_driver/timer/Makefile new file mode 100644 index 0000000..344a8d9 --- /dev/null +++ b/Ubiquitous/XiZi/board/stm32f407-st-discovery/third_party_driver/timer/Makefile @@ -0,0 +1,3 @@ +SRC_FILES := connect_hwtimer.c hardware_tim.c + +include $(KERNEL_ROOT)/compiler.mk diff --git a/Ubiquitous/XiZi/board/stm32f407-st-discovery/third_party_driver/timer/connect_hwtimer.c b/Ubiquitous/XiZi/board/stm32f407-st-discovery/third_party_driver/timer/connect_hwtimer.c new file mode 100644 index 0000000..3c29054 --- /dev/null +++ b/Ubiquitous/XiZi/board/stm32f407-st-discovery/third_party_driver/timer/connect_hwtimer.c @@ -0,0 +1,186 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2018-12-10 zylx first version + * 2020-06-16 thread-liu Porting for stm32mp1 + * 2020-08-25 linyongkang Fix the timer clock frequency doubling problem + * 2020-10-14 Dozingfiretruck Porting for stm32wbxx + */ + +/** +* @file connect_hwtimer.c +* @brief support stm32f407-st-discovery-board hwtimer function and register to bus framework +* @version 1.0 +* @author AIIT XUOS Lab +* @date 2021-04-25 +*/ + +/************************************************* +File name: connect_hwtimer.c +Description: support stm32f407-st-discovery-board hwtimer configure and spi bus register function +Others: take RT-Thread v4.0.2/bsp/stm32/libraries/HAL_Drivers/drv_hwtimer.c for references + https://github.com/RT-Thread/rt-thread/tree/v4.0.2 +History: +1. Date: 2021-04-25 +Author: AIIT XUOS Lab +Modification: +1. support stm32f407-st-discovery-board hwtimer configure +2. support stm32f407-st-discovery-board hwtimer bus device and driver register +*************************************************/ + +#include +#include +#include +#include +#include +#include "connect_hwtimer.h" + +static struct HwtimerCallBackInfo *ptim2_cb_info = NULL; + +#ifdef ENABLE_TIM2 +void TIM2_IRQHandler(int irq_num, void *arg) +{ + TIM_ClearITPendingBit(TIM2, TIM_IT_Update); + KPrintf("hwtimer 2 ... come ...\n"); + + if (ptim2_cb_info) { + if (ptim2_cb_info->timeout_callback) { + ptim2_cb_info->timeout_callback(ptim2_cb_info->param); + } + } +} +DECLARE_HW_IRQ(TIM2_IRQn, TIM2_IRQHandler, NONE); +#endif + +uint32 HwtimerOpen(void *dev) +{ + struct HwtimerHardwareDevice *hwtimer_dev = dev; + + RCC_APB1PeriphClockCmd(RCC_APB1Periph_TIM2, ENABLE); + + TIM_DeInit(TIM2); + + TIM_TimeBaseInitTypeDef timer_def; + timer_def.TIM_Period = (hwtimer_dev->hwtimer_param.period_millisecond) * 10 - 1; + timer_def.TIM_Prescaler = 8400 - 1; + timer_def.TIM_CounterMode = TIM_CounterMode_Up; + timer_def.TIM_ClockDivision = TIM_CKD_DIV1; + timer_def.TIM_RepetitionCounter = 0; + TIM_TimeBaseInit(TIM2, &timer_def); + + NVIC_InitTypeDef NVIC_InitStructure; + NVIC_InitStructure.NVIC_IRQChannel = TIM2_IRQn; /*Configure the timer interrupt line*/ + NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 0x01; /*Configure preemption priority*/ + NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0x01; /*Configure sub-priority*/ + NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE; /*Enable interrupt line*/ + NVIC_Init(&NVIC_InitStructure); + + ptim2_cb_info = &hwtimer_dev->hwtimer_param.cb_info; + + TIM_ITConfig(TIM2, TIM_IT_Update, ENABLE); + + TIM_Cmd(TIM2, ENABLE); + return EOK; +} + +uint32 HwtimerClose(void *dev) +{ + TIM_Cmd(TIM2, DISABLE); + return EOK; +} + +/*manage the hwtimer device operations*/ +static const struct HwtimerDevDone dev_done = +{ + .open = HwtimerOpen, + .close = HwtimerClose, + .write = NONE, + .read = NONE, +}; + +/*Init hwtimer bus*/ +static int BoardHwtimerBusInit(struct HwtimerBus *hwtimer_bus, struct HwtimerDriver *hwtimer_driver) +{ + x_err_t ret = EOK; + + /*Init the hwtimer bus */ + ret = HwtimerBusInit(hwtimer_bus, HWTIMER_BUS_NAME_2); + if (EOK != ret) { + KPrintf("board_hwtimer_init HwtimerBusInit error %d\n", ret); + return ERROR; + } + + #ifdef ENABLE_TIM2 + /*Init the hwtimer driver*/ + hwtimer_driver->configure = NONE; + ret = HwtimerDriverInit(hwtimer_driver, HWTIMER_DRIVER_NAME_2); + if (EOK != ret) { + KPrintf("board_hwtimer_init HwtimerDriverInit error %d\n", ret); + return ERROR; + } + + /*Attach the hwtimer driver to the hwtimer bus*/ + ret = HwtimerDriverAttachToBus(HWTIMER_DRIVER_NAME_2, HWTIMER_BUS_NAME_2); + if (EOK != ret) { + KPrintf("board_hwtimer_init USEDriverAttachToBus error %d\n", ret); + return ERROR; + } + #endif + + return ret; +} + +/*Attach the hwtimer device to the hwtimer bus*/ +static int BoardHwtimerDevBend(void) +{ + #ifdef ENABLE_TIM2 + x_err_t ret = EOK; + static struct HwtimerHardwareDevice hwtimer_device_2; + memset(&hwtimer_device_2, 0, sizeof(struct HwtimerHardwareDevice)); + + hwtimer_device_2.dev_done = &dev_done; + + ret = HwtimerDeviceRegister(&hwtimer_device_2, NONE, HWTIMER_2_DEVICE_NAME_2); + if (EOK != ret) { + KPrintf("board_hwtimer_init HWTIMERDeviceInit device %s error %d\n", HWTIMER_2_DEVICE_NAME_2, ret); + return ERROR; + } + + ret = HwtimerDeviceAttachToBus(HWTIMER_2_DEVICE_NAME_2, HWTIMER_BUS_NAME_2); + if (EOK != ret) { + KPrintf("board_hwtimer_init HwtimerDeviceAttachToBus device %s error %d\n", HWTIMER_2_DEVICE_NAME_2, ret); + return ERROR; + } + + return ret; + #endif +} + +/*ARM-32 BOARD HWTIMER INIT*/ +int Stm32HwTimerInit(void) +{ + x_err_t ret = EOK; + static struct HwtimerBus hwtimer_bus; + memset(&hwtimer_bus, 0, sizeof(struct HwtimerBus)); + + static struct HwtimerDriver hwtimer_driver; + memset(&hwtimer_driver, 0, sizeof(struct HwtimerDriver)); + + ret = BoardHwtimerBusInit(&hwtimer_bus, &hwtimer_driver); + if (EOK != ret) { + KPrintf("board_hwtimer_Init error ret %u\n", ret); + return ERROR; + } + + ret = BoardHwtimerDevBend(); + if (EOK != ret) { + KPrintf("board_hwtimer_Init error ret %u\n", ret); + return ERROR; + } + + return ret; +} diff --git a/Ubiquitous/XiZi/board/stm32f407-st-discovery/third_party_driver/uart/Kconfig b/Ubiquitous/XiZi/board/stm32f407-st-discovery/third_party_driver/uart/Kconfig new file mode 100644 index 0000000..c9a07f3 --- /dev/null +++ b/Ubiquitous/XiZi/board/stm32f407-st-discovery/third_party_driver/uart/Kconfig @@ -0,0 +1,89 @@ +menuconfig BSP_USING_USART1 + bool "Enable USART1" + default y + if BSP_USING_USART1 + config SERIAL_BUS_NAME_1 + string "serial bus 1 name" + default "usart1" + config SERIAL_DRV_NAME_1 + string "serial bus 1 driver name" + default "usart1_drv" + config SERIAL_1_DEVICE_NAME_0 + string "serial bus 1 device 0 name" + default "usart1_dev1" + config USART1_USING_DMA + bool "usart1 using DMA" + default n + endif + +menuconfig BSP_USING_USART2 + bool "Enable USART2" + default y + if BSP_USING_USART2 + config SERIAL_BUS_NAME_2 + string "serial bus 2 name" + default "usart2" + config SERIAL_DRV_NAME_2 + string "serial bus 2 driver name" + default "usart2_drv" + config SERIAL_2_DEVICE_NAME_0 + string "serial bus 2 device 0 name" + default "usart2_dev2" + config USART2_USING_DMA + bool "usart2 using DMA" + default n + endif + +menuconfig BSP_USING_USART3 + bool "Enable USART3" + default y + if BSP_USING_USART3 + config SERIAL_BUS_NAME_3 + string "serial bus 3 name" + default "usart3" + config SERIAL_DRV_NAME_3 + string "serial bus 3 driver name" + default "usart3_drv" + config SERIAL_3_DEVICE_NAME_0 + string "serial bus 3 device 0 name" + default "usart3_dev3" + config USART3_USING_DMA + bool "usart3 using DMA" + default n + endif + +menuconfig BSP_USING_UART4 + bool "Enable UART4" + default n + if BSP_USING_UART4 + config SERIAL_BUS_NAME_4 + string "serial bus 4 name" + default "uart4" + config SERIAL_DRV_NAME_4 + string "serial bus 4 driver name" + default "uart4_drv" + config SERIAL_4_DEVICE_NAME_0 + string "serial bus 4 device 0 name" + default "uart4_dev4" + config USART4_USING_DMA + bool "usart4 using DMA" + default n + endif + +menuconfig BSP_USING_UART5 + bool "Enable UART5" + default n + if BSP_USING_UART5 + config SERIAL_BUS_NAME_5 + string "serial bus 5 name" + default "uart5" + config SERIAL_DRV_NAME_5 + string "serial bus 5 driver name" + default "uart5_drv" + config SERIAL_5_DEVICE_NAME_0 + string "serial bus 5 device 0 name" + default "uart5_dev5" + config USART5_USING_DMA + bool "usart5 using DMA" + default n + endif diff --git a/Ubiquitous/XiZi/board/stm32f407-st-discovery/third_party_driver/uart/Makefile b/Ubiquitous/XiZi/board/stm32f407-st-discovery/third_party_driver/uart/Makefile new file mode 100644 index 0000000..b05646e --- /dev/null +++ b/Ubiquitous/XiZi/board/stm32f407-st-discovery/third_party_driver/uart/Makefile @@ -0,0 +1,3 @@ +SRC_FILES := connect_usart.c hardware_usart.c + +include $(KERNEL_ROOT)/compiler.mk diff --git a/Ubiquitous/XiZi/board/stm32f407-st-discovery/third_party_driver/uart/connect_usart.c b/Ubiquitous/XiZi/board/stm32f407-st-discovery/third_party_driver/uart/connect_usart.c new file mode 100644 index 0000000..b10ea6c --- /dev/null +++ b/Ubiquitous/XiZi/board/stm32f407-st-discovery/third_party_driver/uart/connect_usart.c @@ -0,0 +1,880 @@ +/* + * Copyright (c) 2020 RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + */ + +/** +* @file connect_usart.c +* @brief support stm32f407-st-discovery-board usart function and register to bus framework +* @version 1.0 +* @author AIIT XUOS Lab +* @date 2021-04-25 +*/ + +/************************************************* +File name: connect_uart.c +Description: support stm32f407-st-discovery-board usart configure and uart bus register function +Others: take RT-Thread v4.0.2/bsp/stm32/libraries/HAL_Drivers/drv_usart.c for references + https://github.com/RT-Thread/rt-thread/tree/v4.0.2 +History: +1. Date: 2021-04-25 +Author: AIIT XUOS Lab +Modification: +1. support stm32f407-st-discovery-board usart configure, write and read +2. support stm32f407-st-discovery-board usart bus device and driver register +*************************************************/ + +#include "stm32f4xx.h" +#include "board.h" +#include "misc.h" +#include "connect_usart.h" +#include "hardware_gpio.h" +#include "hardware_rcc.h" + +/* UART GPIO define. */ +#define UART1_GPIO_TX GPIO_Pin_6 +#define UART1_TX_PIN_SOURCE GPIO_PinSource6 +#define UART1_GPIO_RX GPIO_Pin_7 +#define UART1_RX_PIN_SOURCE GPIO_PinSource7 +#define UART1_GPIO GPIOB +#define UART1_GPIO_RCC RCC_AHB1Periph_GPIOB +#define RCC_APBPeriph_UART1 RCC_APB2Periph_USART1 + +#define UART2_GPIO_TX GPIO_Pin_2 +#define UART2_TX_PIN_SOURCE GPIO_PinSource2 +#define UART2_GPIO_RX GPIO_Pin_3 +#define UART2_RX_PIN_SOURCE GPIO_PinSource3 +#define UART2_GPIO GPIOA +#define UART2_GPIO_RCC RCC_AHB1Periph_GPIOA +#define RCC_APBPeriph_UART2 RCC_APB1Periph_USART2 + +#define UART3_GPIO_TX GPIO_Pin_8 +#define UART3_TX_PIN_SOURCE GPIO_PinSource8 +#define UART3_GPIO_RX GPIO_Pin_9 +#define UART3_RX_PIN_SOURCE GPIO_PinSource9 +#define UART3_GPIO GPIOD +#define UART3_GPIO_RCC RCC_AHB1Periph_GPIOD +#define RCC_APBPeriph_UART3 RCC_APB1Periph_USART3 + +#define UART4_GPIO_TX GPIO_Pin_10 +#define UART4_TX_PIN_SOURCE GPIO_PinSource10 +#define UART4_GPIO_RX GPIO_Pin_11 +#define UART4_RX_PIN_SOURCE GPIO_PinSource11 +#define UART4_GPIO GPIOC +#define UART4_GPIO_RCC RCC_AHB1Periph_GPIOC +#define RCC_APBPeriph_UART4 RCC_APB1Periph_UART4 + +#define UART5_GPIO_TX GPIO_Pin_12 +#define UART5_TX_PIN_SOURCE GPIO_PinSource12 +#define UART5_GPIO_RX GPIO_Pin_2 +#define UART5_RX_PIN_SOURCE GPIO_PinSource2 +#define UART5_TX GPIOC +#define UART5_RX GPIOD +#define UART5_GPIO_RCC_TX RCC_AHB1Periph_GPIOC +#define UART5_GPIO_RCC_RX RCC_AHB1Periph_GPIOD +#define RCC_APBPeriph_UART5 RCC_APB1Periph_UART5 + +#define UART_ENABLE_IRQ(n) NVIC_EnableIRQ((n)) +#define UART_DISABLE_IRQ(n) NVIC_DisableIRQ((n)) + +static void RCCConfiguration(void) +{ +#ifdef BSP_USING_USART1 + RCC_AHB1PeriphClockCmd(UART1_GPIO_RCC, ENABLE); + RCC_APB2PeriphClockCmd(RCC_APBPeriph_UART1, ENABLE); +#endif + +#ifdef BSP_USING_USART2 + RCC_AHB1PeriphClockCmd(UART2_GPIO_RCC, ENABLE); + RCC_APB1PeriphClockCmd(RCC_APBPeriph_UART2, ENABLE); +#endif + +#ifdef BSP_USING_USART3 + RCC_AHB1PeriphClockCmd(UART3_GPIO_RCC, ENABLE); + RCC_APB1PeriphClockCmd(RCC_APBPeriph_UART3, ENABLE); +#endif + +#ifdef BSP_USING_UART4 + RCC_AHB1PeriphClockCmd(UART4_GPIO_RCC, ENABLE); + RCC_APB1PeriphClockCmd(RCC_APBPeriph_UART4, ENABLE); +#endif + +#ifdef BSP_USING_UART5 + RCC_AHB1PeriphClockCmd(UART5_GPIO_RCC_TX | UART5_GPIO_RCC_RX, ENABLE); + RCC_APB1PeriphClockCmd(RCC_APBPeriph_UART5, ENABLE); +#endif +} + +static void GPIOConfiguration(void) +{ + GPIO_InitTypeDef gpio_initstructure; + + gpio_initstructure.GPIO_Mode = GPIO_Mode_AF; + gpio_initstructure.GPIO_OType = GPIO_OType_PP; + gpio_initstructure.GPIO_PuPd = GPIO_PuPd_UP; + gpio_initstructure.GPIO_Speed = GPIO_Speed_2MHz; + +#ifdef BSP_USING_USART1 + gpio_initstructure.GPIO_Pin = UART1_GPIO_RX | UART1_GPIO_TX; + GPIO_PinAFConfig(UART1_GPIO, UART1_TX_PIN_SOURCE, GPIO_AF_USART1); + GPIO_PinAFConfig(UART1_GPIO, UART1_RX_PIN_SOURCE, GPIO_AF_USART1); + + GPIO_Init(UART1_GPIO, &gpio_initstructure); +#endif + +#ifdef BSP_USING_USART2 + gpio_initstructure.GPIO_Pin = UART2_GPIO_RX | UART2_GPIO_TX; + GPIO_PinAFConfig(UART2_GPIO, UART2_TX_PIN_SOURCE, GPIO_AF_USART2); + GPIO_PinAFConfig(UART2_GPIO, UART2_RX_PIN_SOURCE, GPIO_AF_USART2); + + GPIO_Init(UART2_GPIO, &gpio_initstructure); +#endif + +#ifdef BSP_USING_USART3 + gpio_initstructure.GPIO_Pin = UART3_GPIO_TX | UART3_GPIO_RX; + GPIO_PinAFConfig(UART3_GPIO, UART3_TX_PIN_SOURCE, GPIO_AF_USART3); + GPIO_PinAFConfig(UART3_GPIO, UART3_RX_PIN_SOURCE, GPIO_AF_USART3); + + GPIO_Init(UART3_GPIO, &gpio_initstructure); +#endif + +#ifdef BSP_USING_UART4 + gpio_initstructure.GPIO_Pin = UART4_GPIO_TX | UART4_GPIO_RX; + GPIO_PinAFConfig(UART4_GPIO, UART4_TX_PIN_SOURCE, GPIO_AF_UART4); + GPIO_PinAFConfig(UART4_GPIO, UART4_RX_PIN_SOURCE, GPIO_AF_UART4); + + GPIO_Init(UART4_GPIO, &gpio_initstructure); +#endif + +#ifdef BSP_USING_UART5 + gpio_initstructure.GPIO_Pin = UART5_GPIO_TX; + GPIO_PinAFConfig(UART5_TX, UART5_TX_PIN_SOURCE, GPIO_AF_UART5); + GPIO_Init(UART5_TX, &gpio_initstructure); + + gpio_initstructure.GPIO_Pin = UART5_GPIO_RX; + GPIO_PinAFConfig(UART5_RX, UART5_RX_PIN_SOURCE, GPIO_AF_UART5); + GPIO_Init(UART5_RX, &gpio_initstructure); +#endif +} + +static void NVIC_Configuration(IRQn_Type irq) +{ + NVIC_InitTypeDef NVIC_InitStructure; + + NVIC_InitStructure.NVIC_IRQChannel = irq; + NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 0; + NVIC_InitStructure.NVIC_IRQChannelSubPriority = 1; + NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE; + NVIC_Init(&NVIC_InitStructure); +} + +static void DmaUartConfig(struct Stm32UsartDma *dma, USART_TypeDef *uart_device, uint32_t SettingRecvLen, void *mem_base_addr) +{ + DMA_InitTypeDef DMA_InitStructure; + + dma->SettingRecvLen = SettingRecvLen; + DMA_DeInit(dma->RxStream); + while (DMA_GetCmdStatus(dma->RxStream) != DISABLE); + DMA_InitStructure.DMA_Channel = dma->RxCh; + DMA_InitStructure.DMA_PeripheralBaseAddr = (uint32_t) &(uart_device->DR); + DMA_InitStructure.DMA_Memory0BaseAddr = (uint32_t)mem_base_addr; + DMA_InitStructure.DMA_DIR = DMA_DIR_PeripheralToMemory; + DMA_InitStructure.DMA_BufferSize = dma->SettingRecvLen; + DMA_InitStructure.DMA_PeripheralInc = DMA_PeripheralInc_Disable; + DMA_InitStructure.DMA_MemoryInc = DMA_MemoryInc_Enable; + DMA_InitStructure.DMA_PeripheralDataSize = DMA_PeripheralDataSize_Byte; + DMA_InitStructure.DMA_MemoryDataSize = DMA_PeripheralDataSize_Byte; + DMA_InitStructure.DMA_Mode = DMA_Mode_Circular; + DMA_InitStructure.DMA_Priority = DMA_Priority_High; + DMA_InitStructure.DMA_FIFOMode = DMA_FIFOMode_Disable; + DMA_InitStructure.DMA_FIFOThreshold = DMA_FIFOThreshold_Full; + DMA_InitStructure.DMA_MemoryBurst = DMA_MemoryBurst_Single; + DMA_InitStructure.DMA_PeripheralBurst = DMA_PeripheralBurst_Single; + DMA_Init(dma->RxStream, &DMA_InitStructure); +} + +static void DMAConfiguration(struct SerialHardwareDevice *serial_dev, USART_TypeDef *uart_device) +{ + struct Stm32Usart *serial = CONTAINER_OF(serial_dev->haldev.owner_bus, struct Stm32Usart, serial_bus); + struct Stm32UsartDma *dma = &serial->dma; + struct SerialCfgParam *serial_cfg = (struct SerialCfgParam *)serial_dev->private_data; + + NVIC_InitTypeDef NVIC_InitStructure; + + USART_ITConfig(uart_device, USART_IT_IDLE , ENABLE); + + RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_DMA1, ENABLE); + RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_DMA2, ENABLE); + + DmaUartConfig(dma, uart_device, serial_cfg->data_cfg.serial_buffer_size, serial_dev->serial_fifo.serial_rx->serial_rx_buffer); + + DMA_ClearFlag(dma->RxStream, dma->RxFlag); + DMA_ITConfig(dma->RxStream, DMA_IT_TC, ENABLE); + USART_DMACmd(uart_device, USART_DMAReq_Rx, ENABLE); + DMA_Cmd(dma->RxStream, ENABLE); + + NVIC_InitStructure.NVIC_IRQChannel = dma->RxIrqCh; + NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 0; + NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0; + NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE; + NVIC_Init(&NVIC_InitStructure); +} + +static void SerialCfgParamCheck(struct SerialCfgParam *serial_cfg_default, struct SerialCfgParam *serial_cfg_new) +{ + struct SerialDataCfg *data_cfg_default = &serial_cfg_default->data_cfg; + struct SerialDataCfg *data_cfg_new = &serial_cfg_new->data_cfg; + + if((data_cfg_default->serial_baud_rate != data_cfg_new->serial_baud_rate) && (data_cfg_new->serial_baud_rate)) { + data_cfg_default->serial_baud_rate = data_cfg_new->serial_baud_rate; + } + + if((data_cfg_default->serial_bit_order != data_cfg_new->serial_bit_order) && (data_cfg_new->serial_bit_order)) { + data_cfg_default->serial_bit_order = data_cfg_new->serial_bit_order; + } + + if((data_cfg_default->serial_buffer_size != data_cfg_new->serial_buffer_size) && (data_cfg_new->serial_buffer_size)) { + data_cfg_default->serial_buffer_size = data_cfg_new->serial_buffer_size; + } + + if((data_cfg_default->serial_data_bits != data_cfg_new->serial_data_bits) && (data_cfg_new->serial_data_bits)) { + data_cfg_default->serial_data_bits = data_cfg_new->serial_data_bits; + } + + if((data_cfg_default->serial_invert_mode != data_cfg_new->serial_invert_mode) && (data_cfg_new->serial_invert_mode)) { + data_cfg_default->serial_invert_mode = data_cfg_new->serial_invert_mode; + } + + if((data_cfg_default->serial_parity_mode != data_cfg_new->serial_parity_mode) && (data_cfg_new->serial_parity_mode)) { + data_cfg_default->serial_parity_mode = data_cfg_new->serial_parity_mode; + } + + if((data_cfg_default->serial_stop_bits != data_cfg_new->serial_stop_bits) && (data_cfg_new->serial_stop_bits)) { + data_cfg_default->serial_stop_bits = data_cfg_new->serial_stop_bits; + } +} + +static uint32 Stm32SerialInit(struct SerialDriver *serial_drv, struct BusConfigureInfo *configure_info) +{ + NULL_PARAM_CHECK(serial_drv); + + struct SerialCfgParam *serial_cfg = (struct SerialCfgParam *)serial_drv->private_data; + struct UsartHwCfg *serial_hw_cfg = (struct UsartHwCfg *)serial_cfg->hw_cfg.private_data; + + if (configure_info->private_data) { + struct SerialCfgParam *serial_cfg_new = (struct SerialCfgParam *)configure_info->private_data; + SerialCfgParamCheck(serial_cfg, serial_cfg_new); + } + + USART_InitTypeDef USART_InitStructure; + + USART_InitStructure.USART_BaudRate = serial_cfg->data_cfg.serial_baud_rate; + + if (serial_cfg->data_cfg.serial_data_bits == DATA_BITS_8) { + USART_InitStructure.USART_WordLength = USART_WordLength_8b; + } else if (serial_cfg->data_cfg.serial_data_bits == DATA_BITS_9) { + USART_InitStructure.USART_WordLength = USART_WordLength_9b; + } + + if (serial_cfg->data_cfg.serial_stop_bits == STOP_BITS_1) { + USART_InitStructure.USART_StopBits = USART_StopBits_1; + } else if (serial_cfg->data_cfg.serial_stop_bits == STOP_BITS_2) { + USART_InitStructure.USART_StopBits = USART_StopBits_2; + } + + if (serial_cfg->data_cfg.serial_parity_mode == PARITY_NONE) { + USART_InitStructure.USART_Parity = USART_Parity_No; + } else if (serial_cfg->data_cfg.serial_parity_mode == PARITY_ODD) { + USART_InitStructure.USART_Parity = USART_Parity_Odd; + } else if (serial_cfg->data_cfg.serial_parity_mode == PARITY_EVEN) { + USART_InitStructure.USART_Parity = USART_Parity_Even; + } + + USART_InitStructure.USART_HardwareFlowControl = USART_HardwareFlowControl_None; + USART_InitStructure.USART_Mode = USART_Mode_Rx | USART_Mode_Tx; + USART_Init(serial_hw_cfg->uart_device, &USART_InitStructure); + + USART_Cmd(serial_hw_cfg->uart_device, ENABLE); + + return EOK; +} + +static uint32 Stm32SerialConfigure(struct SerialDriver *serial_drv, int serial_operation_cmd) +{ + NULL_PARAM_CHECK(serial_drv); + + struct SerialHardwareDevice *serial_dev = (struct SerialHardwareDevice *)serial_drv->driver.owner_bus->owner_haldev; + struct SerialCfgParam *serial_cfg = (struct SerialCfgParam *)serial_drv->private_data; + struct UsartHwCfg *serial_hw_cfg = (struct UsartHwCfg *)serial_cfg->hw_cfg.private_data; + struct SerialDevParam *serial_dev_param = (struct SerialDevParam *)serial_dev->haldev.private_data; + + switch (serial_operation_cmd) + { + case OPER_CLR_INT: + UART_DISABLE_IRQ(serial_hw_cfg->irq); + USART_ITConfig(serial_hw_cfg->uart_device, USART_IT_RXNE, DISABLE); + break; + case OPER_SET_INT: + UART_ENABLE_IRQ(serial_hw_cfg->irq); + USART_ITConfig(serial_hw_cfg->uart_device, USART_IT_RXNE, ENABLE); + break; + case OPER_CONFIG : + if (SIGN_OPER_DMA_RX == serial_dev_param->serial_set_mode) { + DMAConfiguration(serial_dev, serial_hw_cfg->uart_device); + } + } + + return EOK; +} + +static int Stm32SerialPutchar(struct SerialHardwareDevice *serial_dev, char c) +{ + struct SerialCfgParam *serial_cfg = (struct SerialCfgParam *)serial_dev->private_data; + struct UsartHwCfg *serial_hw_cfg = (struct UsartHwCfg *)serial_cfg->hw_cfg.private_data; + + while (!(serial_hw_cfg->uart_device->SR & USART_FLAG_TXE)); + serial_hw_cfg->uart_device->DR = c; + + return EOK; +} + +static int Stm32SerialGetchar(struct SerialHardwareDevice *serial_dev) +{ + struct SerialCfgParam *serial_cfg = (struct SerialCfgParam *)serial_dev->private_data; + struct UsartHwCfg *serial_hw_cfg = (struct UsartHwCfg *)serial_cfg->hw_cfg.private_data; + + int ch = -1; + if (serial_hw_cfg->uart_device->SR & USART_FLAG_RXNE) { + ch = serial_hw_cfg->uart_device->DR & 0xff; + } + + return ch; +} + +static void DmaUartRxIdleIsr(struct SerialHardwareDevice *serial_dev, struct Stm32UsartDma *dma, USART_TypeDef *uart_device) +{ + x_base level = CriticalAreaLock(); + + x_size_t recv_total_index = dma->SettingRecvLen - DMA_GetCurrDataCounter(dma->RxStream); + x_size_t recv_len = recv_total_index - dma->LastRecvIndex; + dma->LastRecvIndex = recv_total_index; + CriticalAreaUnLock(level); + + if (recv_len) SerialSetIsr(serial_dev, SERIAL_EVENT_RX_DMADONE | (recv_len << 8)); + + USART_ReceiveData(uart_device); +} + +static void DmaRxDoneIsr(struct Stm32Usart *serial, struct SerialDriver *serial_drv, struct SerialHardwareDevice *serial_dev) +{ + struct Stm32UsartDma *dma = &serial->dma; + struct SerialCfgParam *serial_cfg = (struct SerialCfgParam *)serial_drv->private_data; + struct UsartHwCfg *serial_hw_cfg = (struct UsartHwCfg *)serial_cfg->hw_cfg.private_data; + + if (DMA_GetFlagStatus(dma->RxStream, dma->RxFlag) != RESET) { + x_base level = CriticalAreaLock(); + + x_size_t recv_len; + + x_size_t recv_total_index = dma->SettingRecvLen - DMA_GetCurrDataCounter(dma->RxStream); + if (0 != recv_total_index) { + recv_len = recv_total_index - dma->LastRecvIndex; + } else { + recv_len = dma->SettingRecvLen - dma->LastRecvIndex; + } + dma->LastRecvIndex = recv_total_index; + + CriticalAreaUnLock(level); + + if (recv_len) SerialSetIsr(serial_dev, SERIAL_EVENT_RX_DMADONE | (recv_len << 8)); + + DMA_ClearFlag(dma->RxStream, dma->RxFlag); + } +} + +static void UartIsr(struct Stm32Usart *serial, struct SerialDriver *serial_drv, struct SerialHardwareDevice *serial_dev) +{ + struct Stm32UsartDma *dma = &serial->dma; + struct SerialCfgParam *serial_cfg = (struct SerialCfgParam *)serial_drv->private_data; + struct UsartHwCfg *serial_hw_cfg = (struct UsartHwCfg *)serial_cfg->hw_cfg.private_data; + + if (USART_GetITStatus(serial_hw_cfg->uart_device, USART_IT_RXNE) != RESET) { + SerialSetIsr(serial_dev, SERIAL_EVENT_RX_IND); + USART_ClearITPendingBit(serial_hw_cfg->uart_device, USART_IT_RXNE); + } else if (USART_GetITStatus(serial_hw_cfg->uart_device, USART_IT_IDLE) != RESET) { + DmaUartRxIdleIsr(serial_dev, dma, serial_hw_cfg->uart_device); + } else if (USART_GetITStatus(serial_hw_cfg->uart_device, USART_IT_TC) != RESET) { + USART_ClearITPendingBit(serial_hw_cfg->uart_device, USART_IT_TC); + } else { + if (USART_GetFlagStatus(serial_hw_cfg->uart_device, USART_FLAG_ORE) == SET) { + USART_ReceiveData(serial_hw_cfg->uart_device); + } + } +} + +#ifdef BSP_USING_USART1 +struct Stm32Usart serial_1; +struct SerialDriver serial_driver_1; +struct SerialHardwareDevice serial_device_1; + +static const struct Stm32UsartDma usart_dma_1 = +{ + DMA2_Stream5, + DMA_Channel_4, + DMA_FLAG_TCIF5, + DMA2_Stream5_IRQn, + 0, + 0, +}; + +void USART1_IRQHandler(int irq_num, void *arg) +{ + UartIsr(&serial_1, &serial_driver_1, &serial_device_1); +} +DECLARE_HW_IRQ(USART1_IRQn, USART1_IRQHandler, NONE); + +void DMA2_Stream5_IRQHandler(int irq_num, void *arg) { + DmaRxDoneIsr(&serial_1, &serial_driver_1, &serial_device_1); +} +DECLARE_HW_IRQ(DMA2_Stream5_IRQn, DMA2_Stream5_IRQHandler, NONE); +#endif + +#ifdef BSP_USING_USART2 +struct Stm32Usart serial_2; +struct SerialDriver serial_driver_2; +struct SerialHardwareDevice serial_device_2; + +static const struct Stm32UsartDma usart_dma_2 = +{ + DMA1_Stream5, + DMA_Channel_4, + DMA_FLAG_TCIF5, + DMA1_Stream5_IRQn, + 0, + 0, +}; + +void USART2_IRQHandler(int irq_num, void *arg) +{ + UartIsr(&serial_2, &serial_driver_2, &serial_device_2); +} +DECLARE_HW_IRQ(USART2_IRQn, USART2_IRQHandler, NONE); + +void DMA1_Stream5_IRQHandler(int irq_num, void *arg) { + DmaRxDoneIsr(&serial_2, &serial_driver_2, &serial_device_2); +} +DECLARE_HW_IRQ(DMA1_Stream5_IRQn, DMA1_Stream5_IRQHandler, NONE); +#endif + +#ifdef BSP_USING_USART3 +struct Stm32Usart serial_3; +struct SerialDriver serial_driver_3; +struct SerialHardwareDevice serial_device_3; + +static const struct Stm32UsartDma usart_dma_3 = +{ + DMA1_Stream1, + DMA_Channel_4, + DMA_FLAG_TCIF1, + DMA1_Stream1_IRQn, + 0, + 0, +}; + +void USART3_IRQHandler(int irq_num, void *arg) +{ + UartIsr(&serial_3, &serial_driver_3, &serial_device_3); +} +DECLARE_HW_IRQ(USART3_IRQn, USART3_IRQHandler, NONE); + +void DMA1_Stream1_IRQHandler(int irq_num, void *arg) { + DmaRxDoneIsr(&serial_3, &serial_driver_3, &serial_device_3); +} +DECLARE_HW_IRQ(DMA1_Stream1_IRQn, DMA1_Stream1_IRQHandler, NONE); +#endif + +#ifdef BSP_USING_UART4 +struct Stm32Usart serial_4; +struct SerialDriver serial_driver_4; +struct SerialHardwareDevice serial_device_4; + +static const struct Stm32UsartDma uart_dma_4 = +{ + DMA1_Stream2, + DMA_Channel_4, + DMA_FLAG_TCIF2, + DMA1_Stream2_IRQn, + 0, + 0, +}; + +void UART4_IRQHandler(int irq_num, void *arg) +{ + UartIsr(&serial_4, &serial_driver_4, &serial_device_4); +} +DECLARE_HW_IRQ(UART4_IRQn, UART4_IRQHandler, NONE); + +void DMA1_Stream2_IRQHandler(int irq_num, void *arg) { + DmaRxDoneIsr(&serial_4, &serial_driver_4, &serial_device_4); +} +DECLARE_HW_IRQ(DMA1_Stream2_IRQn, DMA1_Stream2_IRQHandler, NONE); +#endif + +#ifdef BSP_USING_UART5 +struct Stm32Usart serial_5; +struct SerialDriver serial_driver_5; +struct SerialHardwareDevice serial_device_5; + +static const struct Stm32UsartDma uart_dma_5 = +{ + DMA1_Stream0, + DMA_Channel_4, + DMA_FLAG_TCIF0, + DMA1_Stream0_IRQn, + 0, + 0, +}; + +void UART5_IRQHandler(int irq_num, void *arg) +{ + UartIsr(&serial_5, &serial_driver_5, &serial_device_5); +} +DECLARE_HW_IRQ(UART5_IRQn, UART5_IRQHandler, NONE); + +void DMA1_Stream0_IRQHandler(int irq_num, void *arg) { + DmaRxDoneIsr(&serial_5, &serial_driver_5, &serial_device_5); +} +DECLARE_HW_IRQ(DMA1_Stream0_IRQn, DMA1_Stream0_IRQHandler, NONE); +#endif + +static uint32 Stm32SerialDrvConfigure(void *drv, struct BusConfigureInfo *configure_info) +{ + NULL_PARAM_CHECK(drv); + NULL_PARAM_CHECK(configure_info); + + x_err_t ret = EOK; + int serial_operation_cmd; + struct SerialDriver *serial_drv = (struct SerialDriver *)drv; + + switch (configure_info->configure_cmd) + { + case OPE_INT: + ret = Stm32SerialInit(serial_drv, configure_info); + break; + case OPE_CFG: + serial_operation_cmd = *(int *)configure_info->private_data; + ret = Stm32SerialConfigure(serial_drv, serial_operation_cmd); + break; + default: + break; + } + + return ret; +} + +static const struct SerialDataCfg data_cfg_init = +{ + .serial_baud_rate = BAUD_RATE_115200, + .serial_data_bits = DATA_BITS_8, + .serial_stop_bits = STOP_BITS_1, + .serial_parity_mode = PARITY_NONE, + .serial_bit_order = BIT_ORDER_LSB, + .serial_invert_mode = NRZ_NORMAL, + .serial_buffer_size = SERIAL_RB_BUFSZ, +}; + +/*manage the serial device operations*/ +static const struct SerialDrvDone drv_done = +{ + .init = Stm32SerialInit, + .configure = Stm32SerialConfigure, +}; + +/*manage the serial device hal operations*/ +static struct SerialHwDevDone hwdev_done = +{ + .put_char = Stm32SerialPutchar, + .get_char = Stm32SerialGetchar, +}; + +static int BoardSerialBusInit(struct SerialBus *serial_bus, struct SerialDriver *serial_driver, const char *bus_name, const char *drv_name) +{ + x_err_t ret = EOK; + + /*Init the serial bus */ + ret = SerialBusInit(serial_bus, bus_name); + if (EOK != ret) { + KPrintf("hw_serial_init SerialBusInit error %d\n", ret); + return ERROR; + } + + /*Init the serial driver*/ + ret = SerialDriverInit(serial_driver, drv_name); + if (EOK != ret) { + KPrintf("hw_serial_init SerialDriverInit error %d\n", ret); + return ERROR; + } + + /*Attach the serial driver to the serial bus*/ + ret = SerialDriverAttachToBus(drv_name, bus_name); + if (EOK != ret) { + KPrintf("hw_serial_init SerialDriverAttachToBus error %d\n", ret); + return ERROR; + } + + return ret; +} + +/*Attach the serial device to the serial bus*/ +static int BoardSerialDevBend(struct SerialHardwareDevice *serial_device, void *serial_param, const char *bus_name, const char *dev_name) +{ + x_err_t ret = EOK; + + ret = SerialDeviceRegister(serial_device, serial_param, dev_name); + if (EOK != ret) { + KPrintf("hw_serial_init SerialDeviceInit device %s error %d\n", dev_name, ret); + return ERROR; + } + + ret = SerialDeviceAttachToBus(dev_name, bus_name); + if (EOK != ret) { + KPrintf("hw_serial_init SerialDeviceAttachToBus device %s error %d\n", dev_name, ret); + return ERROR; + } + + return ret; +} + +int Stm32HwUsartInit(void) +{ + x_err_t ret = EOK; + + RCCConfiguration(); + GPIOConfiguration(); + +#ifdef BSP_USING_USART1 + static struct SerialCfgParam serial_cfg_1; + memset(&serial_cfg_1, 0, sizeof(struct SerialCfgParam)); + + static struct UsartHwCfg serial_hw_cfg_1; + memset(&serial_hw_cfg_1, 0, sizeof(struct UsartHwCfg)); + + static struct SerialDevParam serial_dev_param_1; + memset(&serial_dev_param_1, 0, sizeof(struct SerialDevParam)); + + serial_1.dma = usart_dma_1; + + serial_driver_1.drv_done = &drv_done; + serial_driver_1.configure = &Stm32SerialDrvConfigure; + serial_device_1.hwdev_done = &hwdev_done; + + serial_cfg_1.data_cfg = data_cfg_init; + + serial_hw_cfg_1.uart_device = USART1; + serial_hw_cfg_1.irq = USART1_IRQn; + serial_cfg_1.hw_cfg.private_data = (void *)&serial_hw_cfg_1; + serial_driver_1.private_data = (void *)&serial_cfg_1; + + serial_dev_param_1.serial_work_mode = SIGN_OPER_INT_RX; +#ifdef USART1_USING_DMA + serial_dev_param_1.serial_work_mode = SIGN_OPER_DMA_RX; +#endif + serial_device_1.haldev.private_data = (void *)&serial_dev_param_1; + + NVIC_Configuration(serial_hw_cfg_1.irq); + + ret = BoardSerialBusInit(&serial_1.serial_bus, &serial_driver_1, SERIAL_BUS_NAME_1, SERIAL_DRV_NAME_1); + if (EOK != ret) { + KPrintf("Stm32HwUsartInit usart1 error ret %u\n", ret); + return ERROR; + } + + ret = BoardSerialDevBend(&serial_device_1, (void *)&serial_cfg_1, SERIAL_BUS_NAME_1, SERIAL_1_DEVICE_NAME_0); + if (EOK != ret) { + KPrintf("Stm32HwUsartInit usart1 error ret %u\n", ret); + return ERROR; + } +#endif + +#ifdef BSP_USING_USART2 + static struct SerialCfgParam serial_cfg_2; + memset(&serial_cfg_2, 0, sizeof(struct SerialCfgParam)); + + static struct UsartHwCfg serial_hw_cfg_2; + memset(&serial_hw_cfg_2, 0, sizeof(struct UsartHwCfg)); + + static struct SerialDevParam serial_dev_param_2; + memset(&serial_dev_param_2, 0, sizeof(struct SerialDevParam)); + + serial_2.dma = usart_dma_2; + + serial_driver_2.drv_done = &drv_done; + serial_driver_2.configure = &Stm32SerialDrvConfigure; + serial_device_2.hwdev_done = &hwdev_done; + + serial_cfg_2.data_cfg = data_cfg_init; + + serial_hw_cfg_2.uart_device = USART2; + serial_hw_cfg_2.irq = USART2_IRQn; + serial_cfg_2.hw_cfg.private_data = (void *)&serial_hw_cfg_2; + serial_driver_2.private_data = (void *)&serial_cfg_2; + + serial_dev_param_2.serial_work_mode = SIGN_OPER_INT_RX; +#ifdef USART2_USING_DMA + serial_dev_param_2.serial_work_mode = SIGN_OPER_DMA_RX; +#endif + serial_device_2.haldev.private_data = (void *)&serial_dev_param_2; + + NVIC_Configuration(serial_hw_cfg_2.irq); + + ret = BoardSerialBusInit(&serial_2.serial_bus, &serial_driver_2, SERIAL_BUS_NAME_2, SERIAL_DRV_NAME_2); + if (EOK != ret) { + KPrintf("Stm32HwUsartInit usart2 error ret %u\n", ret); + return ERROR; + } + + ret = BoardSerialDevBend(&serial_device_2, (void *)&serial_cfg_2, SERIAL_BUS_NAME_2, SERIAL_2_DEVICE_NAME_0); + if (EOK != ret) { + KPrintf("Stm32HwUsartInit usart2 error ret %u\n", ret); + return ERROR; + } +#endif + +#ifdef BSP_USING_USART3 + static struct SerialCfgParam serial_cfg_3; + memset(&serial_cfg_3, 0, sizeof(struct SerialCfgParam)); + + static struct UsartHwCfg serial_hw_cfg_3; + memset(&serial_hw_cfg_3, 0, sizeof(struct UsartHwCfg)); + + static struct SerialDevParam serial_dev_param_3; + memset(&serial_dev_param_3, 0, sizeof(struct SerialDevParam)); + + serial_3.dma = usart_dma_3; + + serial_driver_3.drv_done = &drv_done; + serial_driver_3.configure = &Stm32SerialDrvConfigure; + serial_device_3.hwdev_done = &hwdev_done; + + serial_cfg_3.data_cfg = data_cfg_init; + + serial_hw_cfg_3.uart_device = USART3; + serial_hw_cfg_3.irq = USART3_IRQn; + serial_cfg_3.hw_cfg.private_data = (void *)&serial_hw_cfg_3; + serial_driver_3.private_data = (void *)&serial_cfg_3; + + serial_dev_param_3.serial_work_mode = SIGN_OPER_INT_RX; +#ifdef USART3_USING_DMA + serial_dev_param_3.serial_work_mode = SIGN_OPER_DMA_RX; +#endif + serial_device_3.haldev.private_data = (void *)&serial_dev_param_3; + + NVIC_Configuration(serial_hw_cfg_3.irq); + + ret = BoardSerialBusInit(&serial_3.serial_bus, &serial_driver_3, SERIAL_BUS_NAME_3, SERIAL_DRV_NAME_3); + if (EOK != ret) { + KPrintf("Stm32HwUsartInit usart3 error ret %u\n", ret); + return ERROR; + } + + ret = BoardSerialDevBend(&serial_device_3, (void *)&serial_cfg_3, SERIAL_BUS_NAME_3, SERIAL_3_DEVICE_NAME_0); + if (EOK != ret) { + KPrintf("Stm32HwUsartInit usart3 error ret %u\n", ret); + return ERROR; + } +#endif + +#ifdef BSP_USING_UART4 + static struct SerialCfgParam serial_cfg_4; + memset(&serial_cfg_4, 0, sizeof(struct SerialCfgParam)); + + static struct UsartHwCfg serial_hw_cfg_4; + memset(&serial_hw_cfg_4, 0, sizeof(struct UsartHwCfg)); + + static struct SerialDevParam serial_dev_param_4; + memset(&serial_dev_param_4, 0, sizeof(struct SerialDevParam)); + + serial_4.dma = uart_dma_4; + + serial_driver_4.drv_done = &drv_done; + serial_driver_4.configure = &Stm32SerialDrvConfigure; + serial_device_4.hwdev_done = &hwdev_done; + + serial_cfg_4.data_cfg = data_cfg_init; + + serial_hw_cfg_4.uart_device = UART4; + serial_hw_cfg_4.irq = UART4_IRQn; + serial_cfg_4.hw_cfg.private_data = (void *)&serial_hw_cfg_4; + serial_driver_4.private_data = (void *)&serial_cfg_4; + + serial_dev_param_4.serial_work_mode = SIGN_OPER_INT_RX; +#ifdef USART4_USING_DMA + serial_dev_param_4.serial_work_mode = SIGN_OPER_DMA_RX; +#endif + serial_device_4.haldev.private_data = (void *)&serial_dev_param_4; + + NVIC_Configuration(serial_hw_cfg_4.irq); + + ret = BoardSerialBusInit(&serial_4.serial_bus, &serial_driver_4, SERIAL_BUS_NAME_4, SERIAL_DRV_NAME_4); + if (EOK != ret) { + KPrintf("Stm32HwUsartInit usart4 error ret %u\n", ret); + return ERROR; + } + + ret = BoardSerialDevBend(&serial_device_4, (void *)&serial_cfg_4, SERIAL_BUS_NAME_4, SERIAL_4_DEVICE_NAME_0); + if (EOK != ret) { + KPrintf("Stm32HwUsartInit usart4 error ret %u\n", ret); + return ERROR; + } +#endif + +#ifdef BSP_USING_UART5 + static struct SerialCfgParam serial_cfg_5; + memset(&serial_cfg_5, 0, sizeof(struct SerialCfgParam)); + + static struct UsartHwCfg serial_hw_cfg_5; + memset(&serial_hw_cfg_5, 0, sizeof(struct UsartHwCfg)); + + static struct SerialDevParam serial_dev_param_5; + memset(&serial_dev_param_5, 0, sizeof(struct SerialDevParam)); + + serial_5.dma = uart_dma_5; + + serial_driver_5.drv_done = &drv_done; + serial_driver_5.configure = &Stm32SerialDrvConfigure; + serial_device_5.hwdev_done = &hwdev_done; + + serial_cfg_5.data_cfg = data_cfg_init; + + serial_hw_cfg_5.uart_device = UART5; + serial_hw_cfg_5.irq = UART5_IRQn; + serial_cfg_5.hw_cfg.private_data = (void *)&serial_hw_cfg_5; + serial_driver_5.private_data = (void *)&serial_cfg_5; + + serial_dev_param_5.serial_work_mode = SIGN_OPER_INT_RX; +#ifdef USART5_USING_DMA + serial_dev_param_5.serial_work_mode = SIGN_OPER_DMA_RX; +#endif + serial_device_5.haldev.private_data = (void *)&serial_dev_param_5; + + NVIC_Configuration(serial_hw_cfg_5.irq); + + ret = BoardSerialBusInit(&serial_5.serial_bus, &serial_driver_5, SERIAL_BUS_NAME_5, SERIAL_DRV_NAME_5); + if (EOK != ret) { + KPrintf("Stm32HwUsartInit usart5 error ret %u\n", ret); + return ERROR; + } + + ret = BoardSerialDevBend(&serial_device_5, (void *)&serial_cfg_5, SERIAL_BUS_NAME_5, SERIAL_5_DEVICE_NAME_0); + if (EOK != ret) { + KPrintf("Stm32HwUsartInit usart5 error ret %u\n", ret); + return ERROR; + } +#endif + + return ret; +} diff --git a/Ubiquitous/XiZi/board/stm32f407-st-discovery/third_party_driver/usb/Kconfig b/Ubiquitous/XiZi/board/stm32f407-st-discovery/third_party_driver/usb/Kconfig new file mode 100644 index 0000000..69d2536 --- /dev/null +++ b/Ubiquitous/XiZi/board/stm32f407-st-discovery/third_party_driver/usb/Kconfig @@ -0,0 +1,12 @@ +config BSP_USING_STM32_USBH + bool "Using usb host" + default y + config USB_BUS_NAME + string "usb bus name" + default "usb" + config USB_DRIVER_NAME + string "usb bus driver name" + default "usb_drv" + config USB_DEVICE_NAME + string "usb bus device name" + default "usb_dev" \ No newline at end of file diff --git a/Ubiquitous/XiZi/board/stm32f407-st-discovery/third_party_driver/usb/Makefile b/Ubiquitous/XiZi/board/stm32f407-st-discovery/third_party_driver/usb/Makefile new file mode 100644 index 0000000..6331e6e --- /dev/null +++ b/Ubiquitous/XiZi/board/stm32f407-st-discovery/third_party_driver/usb/Makefile @@ -0,0 +1,4 @@ +SRC_FILES := usb_bsp.c usbh.c connect_usb.c +SRC_FILES += STM32_USB_OTG_Driver/src/usb_core.c STM32_USB_OTG_Driver/src/usb_hcd.c STM32_USB_OTG_Driver/src/usb_hcd_int.c + +include $(KERNEL_ROOT)/compiler.mk diff --git a/Ubiquitous/XiZi/board/stm32f407-st-discovery/third_party_driver/usb/connect_usb.c b/Ubiquitous/XiZi/board/stm32f407-st-discovery/third_party_driver/usb/connect_usb.c new file mode 100644 index 0000000..eb10628 --- /dev/null +++ b/Ubiquitous/XiZi/board/stm32f407-st-discovery/third_party_driver/usb/connect_usb.c @@ -0,0 +1,125 @@ +/* +* Copyright (c) 2020 AIIT XUOS Lab +* XiUOS is licensed under Mulan PSL v2. +* You can use this software according to the terms and conditions of the Mulan PSL v2. +* You may obtain a copy of Mulan PSL v2 at: +* http://license.coscl.org.cn/MulanPSL2 +* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, +* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, +* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. +* See the Mulan PSL v2 for more details. +*/ + +/** +* @file connect_usb.c +* @brief support stm32f407-st-discovery-board usb function and register to bus framework +* @version 1.0 +* @author AIIT XUOS Lab +* @date 2021-04-25 +*/ + +#include +#include "core_cm4.h" +#include "connect_usb.h" +#include "bus_usb.h" +#include "dev_usb.h" + +uint32 UdiskRead_new_api(void *dev, struct BusBlockReadParam *read_param); +uint32 UdiskWirte_new_api(void *dev, struct BusBlockWriteParam *write_param); + +static uint32 UdiskOpenNewApi(void *dev) +{ + return EOK; +} + +static uint32 UdiskCloseNewApi(void *dev) +{ + return EOK; +} + +/*manage the usb device operations*/ +static const struct UsbDevDone dev_done = +{ + .open = UdiskOpenNewApi, + .close = UdiskCloseNewApi, + .write = UdiskWirte_new_api, + .read = UdiskRead_new_api, +}; + +/*Init usb bus*/ +static int BoardUsbBusInit(struct UsbBus *usb_bus, struct UsbDriver *usb_driver) +{ + x_err_t ret = EOK; + + /*Init the usb bus */ + ret = UsbBusInit(usb_bus, USB_BUS_NAME); + if (EOK != ret) { + KPrintf("board_usb_init UsbBusInit error %d\n", ret); + return ERROR; + } + + /*Init the usb driver*/ + ret = UsbDriverInit(usb_driver, USB_DRIVER_NAME); + if (EOK != ret) { + KPrintf("board_usb_init UsbDriverInit error %d\n", ret); + return ERROR; + } + + /*Attach the usb driver to the usb bus*/ + ret = UsbDriverAttachToBus(USB_DRIVER_NAME, USB_BUS_NAME); + if (EOK != ret) { + KPrintf("board_usb_init USEDriverAttachToBus error %d\n", ret); + return ERROR; + } + + return ret; +} + +/*Attach the usb device to the usb bus*/ +static int BoardUsbDevBend(void) +{ + x_err_t ret = EOK; + static struct UsbHardwareDevice usb_device1; + memset(&usb_device1, 0, sizeof(struct UsbHardwareDevice)); + + usb_device1.dev_done = &dev_done; + + ret = USBDeviceRegister(&usb_device1, NONE, USB_DEVICE_NAME); + if (EOK != ret) { + KPrintf("board_usb_init USBDeviceInit device %s error %d\n", USB_DEVICE_NAME, ret); + return ERROR; + } + + ret = USBDeviceAttachToBus(USB_DEVICE_NAME, USB_BUS_NAME); + if (EOK != ret) { + KPrintf("board_usb_init USBDeviceAttachToBus device %s error %d\n", USB_DEVICE_NAME, ret); + return ERROR; + } + + return ret; +} + +/*ARM-32 BOARD USB INIT*/ +int Stm32HwUsbInit(void) +{ + x_err_t ret = EOK; + static struct UsbBus usb_bus; + memset(&usb_bus, 0, sizeof(struct UsbBus)); + + static struct UsbDriver usb_driver; + memset(&usb_driver, 0, sizeof(struct UsbDriver)); + + ret = BoardUsbBusInit(&usb_bus, &usb_driver); + if (EOK != ret) { + KPrintf("board_usb_Init error ret %u\n", ret); + return ERROR; + } + + ret = BoardUsbDevBend(); + if (EOK != ret) { + KPrintf("board_usb_Init error ret %u\n", ret); + return ERROR; + } + + return ret; +} diff --git a/Ubiquitous/XiZi/board/stm32f407-st-discovery/third_party_driver/usb/usb_bsp.c b/Ubiquitous/XiZi/board/stm32f407-st-discovery/third_party_driver/usb/usb_bsp.c new file mode 100644 index 0000000..d2e42d4 --- /dev/null +++ b/Ubiquitous/XiZi/board/stm32f407-st-discovery/third_party_driver/usb/usb_bsp.c @@ -0,0 +1,236 @@ +/** + ****************************************************************************** + * @file usb_bsp.c + * @author xiuos Team + * @version V1.0.0 + * @date 2020-9-3 + * @brief This file is based on usb_bsp.c + * This file is responsible to offer board support package and is + * configurable by user. + ****************************************************************************** + * @file usb_bsp.c + * @author MCD Application Team + * @version V1.0.0 + * @date 30-September-2011 + * ******************************************************************************** + * @attention + * + *

© Copyright (c) 2015 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under Ultimate Liberty license + * SLA0044, the "License"; You may not use this file except in compliance with + * the License. You may obtain a copy of the License at: + * + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "usb_bsp.h" + +#include +#include +#include +#include +#include + +/** @addtogroup USB_OTG_DRIVER +* @{ +*/ + +/** @defgroup USB_BSP + * @brief This file is responsible to offer board support package + * @{ + */ + +/** @defgroup USB_BSP_Private_Defines + * @{ + */ +/** + * @} + */ + + +/** @defgroup USB_BSP_Private_TypesDefinitions + * @{ + */ +/** + * @} + */ + + + + + +/** @defgroup USB_BSP_Private_Macros + * @{ + */ +/** + * @} + */ + +/** @defgroup USBH_BSP_Private_Variables + * @{ + */ + +/** + * @} + */ + +/** @defgroup USBH_BSP_Private_FunctionPrototypes + * @{ + */ +/** + * @} + */ + +/** @defgroup USB_BSP_Private_Functions + * @{ + */ + + +/** + * @brief USB_OTG_BSP_Init + * Initializes BSP configurations + * @param None + * @retval None + */ + +int USB_OTG_BSP_Init_count = 0; + +void USB_OTG_BSP_Init(USB_OTG_CORE_HANDLE *pdev) +{ + GPIO_InitTypeDef gpio_initstructure; + + RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOA, ENABLE); + RCC_AHB2PeriphClockCmd(RCC_AHB2Periph_OTG_FS, ENABLE); + + gpio_initstructure.GPIO_Pin = GPIO_Pin_11 | GPIO_Pin_12; + gpio_initstructure.GPIO_Mode = GPIO_Mode_AF; + gpio_initstructure.GPIO_OType = GPIO_OType_PP; + gpio_initstructure.GPIO_Speed = GPIO_Speed_100MHz; + gpio_initstructure.GPIO_PuPd = GPIO_PuPd_NOPULL; + GPIO_Init(GPIOA, &gpio_initstructure); + + GPIO_PinAFConfig(GPIOA,GPIO_PinSource11, GPIO_AF_OTG_FS); + GPIO_PinAFConfig(GPIOA,GPIO_PinSource12, GPIO_AF_OTG_FS); + + RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOC, ENABLE); + + gpio_initstructure.GPIO_Pin = GPIO_Pin_0; + gpio_initstructure.GPIO_Mode = GPIO_Mode_OUT; + gpio_initstructure.GPIO_OType = GPIO_OType_PP; + gpio_initstructure.GPIO_PuPd = GPIO_PuPd_NOPULL; + GPIO_Init(GPIOC, &gpio_initstructure); +} +/** + * @brief USB_OTG_BSP_ENABLE_INTERRUPT + * Enable USB Global interrupt + * @param None + * @retval None + */ +void USB_OTG_BSP_ENABLE_INTERRUPT(USB_OTG_CORE_HANDLE *pdev) +{ + isrManager.done->enableIrq(OTG_FS_IRQn); +} + +/** + * @brief BSP_Drive_VBUS + * Drives the Vbus signal through IO + * @param speed : Full, Low + * @param state : VBUS states + * @retval None + */ + +void USB_OTG_BSP_DriveVBUS(USB_OTG_CORE_HANDLE *pdev,uint8_t state) +{ + if (state == 1) + GPIO_ResetBits(GPIOC, GPIO_Pin_0); + else + GPIO_SetBits(GPIOC, GPIO_Pin_0); +} + +/** + * @brief USB_OTG_BSP_ConfigVBUS + * Configures the IO for the Vbus and OverCurrent + * @param Speed : Full, Low + * @retval None + */ + +void USB_OTG_BSP_ConfigVBUS(USB_OTG_CORE_HANDLE *pdev) +{ + +} + +/** + * @brief USB_OTG_BSP_TimeInit + * Initialises delay unit Systick timer /Timer2 + * @param None + * @retval None + */ +void USB_OTG_BSP_TimeInit ( void ) +{ + +} + +/** + * @brief USB_OTG_BSP_uDelay + * This function provides delay time in micro sec + * @param usec : Value of delay required in micro sec + * @retval None + */ +void USB_OTG_BSP_uDelay (const uint32_t usec) +{ + + uint32_t count = 0; + const uint32_t utime = (120 * usec / 7); + do { + if ( ++count > utime ) { + return ; + } + } + while (1); + +} + + +/** + * @brief USB_OTG_BSP_mDelay + * This function provides delay time in milli sec + * @param msec : Value of delay required in milli sec + * @retval None + */ +void USB_OTG_BSP_mDelay (const uint32_t msec) +{ + + DelayKTask(msec * TICK_PER_SECOND / 1000); + +} + + +/** + * @brief USB_OTG_BSP_TimerIRQ + * Time base IRQ + * @param None + * @retval None + */ + +void USB_OTG_BSP_TimerIRQ (void) +{ + +} + +/** +* @} +*/ + +/** +* @} +*/ + +/** +* @} +*/ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/Ubiquitous/XiZi/board/stm32f407-st-discovery/third_party_driver/usb/usbh.c b/Ubiquitous/XiZi/board/stm32f407-st-discovery/third_party_driver/usb/usbh.c new file mode 100644 index 0000000..cc5f77f --- /dev/null +++ b/Ubiquitous/XiZi/board/stm32f407-st-discovery/third_party_driver/usb/usbh.c @@ -0,0 +1,409 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2017-10-30 ZYH the first version + * 2019-12-19 tyustli port to stm32 series + */ + +/** +* @file usbh.c +* @brief support stm32f407-st-discovery-board usb function +* @version 1.0 +* @author AIIT XUOS Lab +* @date 2021-04-25 +*/ + +/************************************************* +File name: usbh.c +Description: support stm32f407-st-discovery-board usb configure +Others: take RT-Thread v4.0.2/bsp/stm32/libraries/HAL_Drivers/drv_usbh.c for references + https://github.com/RT-Thread/rt-thread/tree/v4.0.2 +History: +1. Date: 2021-04-25 +Author: AIIT XUOS Lab +Modification: +1. support stm32f407-st-discovery-board usb irq configure +2. support stm32f407-st-discovery-board usb host register +*************************************************/ + +#include +#include +#include +#include +#include +#include +#include "usb_bsp.h" +#include "usb_hcd.h" +#include "usb_hcd_int.h" + +static USB_OTG_CORE_HANDLE USB_OTG_Core; +static int UrbCompletionSem; + +void OTG_FS_IRQHandler(int irq_num, void *arg) +{ + USBH_OTG_ISR_Handler(&USB_OTG_Core); +} +DECLARE_HW_IRQ(OTG_FS_IRQn, OTG_FS_IRQHandler, NONE); + +static uint8_t SOF_cb(USB_OTG_CORE_HANDLE *pdev) +{ + return 0; +} + +static uint8_t DevConnected_cb(USB_OTG_CORE_HANDLE *pdev) +{ + UhcdPointer hcd = pdev->data; + + if (!pdev->host.ConnSts) { + pdev->host.ConnSts = 1; + UsbhRootHubConnectHandler(hcd, 1, RET_FALSE); + } + + return 0; +} + +static uint8_t DevDisconnected_cb(USB_OTG_CORE_HANDLE *pdev) +{ + UhcdPointer hcd = pdev->data; + + if (pdev->host.ConnSts) { + pdev->host.ConnSts = 0; + UsbhRootHubDisconnectHandler(hcd, 1); + } + + return 0; +} + +static uint8_t URBChangeNotify_cb(USB_OTG_CORE_HANDLE *pdev) +{ + KSemaphoreAbandon(UrbCompletionSem); + + return 0; +} + +static uint8_t DevPortEnabled_cb(USB_OTG_CORE_HANDLE *pdev) +{ + pdev->host.PortEnabled = 1; + + return 0; +} + +static uint8_t DevPortDisabled_cb(USB_OTG_CORE_HANDLE *pdev) +{ + pdev->host.PortEnabled = 0; + + return 0; +} + +static USBH_HCD_INT_cb_TypeDef USBH_HCD_INT_cb = { + .SOF = SOF_cb, + .DevConnected = DevConnected_cb, + .DevDisconnected = DevDisconnected_cb, + .DevPortEnabled = DevPortEnabled_cb, + .DevPortDisabled = DevPortDisabled_cb, + .URBChangeNotify = URBChangeNotify_cb, +}; +USBH_HCD_INT_cb_TypeDef *USBH_HCD_INT_fops = &USBH_HCD_INT_cb; + +static void STM32USBHostChannelOpen(USB_OTG_CORE_HANDLE *pdev, uint8_t hc_num, uint8_t epnum, + uint8_t dev_address, uint8_t speed, uint8_t ep_type, uint16_t mps) +{ + pdev->host.hc[hc_num].ep_num = epnum & 0x7F; + pdev->host.hc[hc_num].ep_is_in = (epnum & 0x80 ) == 0x80; + pdev->host.hc[hc_num].DevAddr = dev_address; + pdev->host.hc[hc_num].ep_type = ep_type; + pdev->host.hc[hc_num].max_packet = mps; + pdev->host.hc[hc_num].speed = speed; + pdev->host.hc[hc_num].toggle_in = 0; + pdev->host.hc[hc_num].toggle_out = 0; + if(speed == HPRT0_PRTSPD_HIGH_SPEED) { + pdev->host.hc[hc_num].do_ping = 1; + } + + USB_OTG_HC_Init(pdev, hc_num) ; +} + +static x_err_t STM32USBHostResetPort(uint8 port) +{ + SYS_KDEBUG_LOG(SYS_DEBUG_USB, ("reset port\n")); + HCD_ResetPort(&USB_OTG_Core); + + return EOK; +} + +x_err_t STM32USBHostChannelSubmitRequest(USB_OTG_CORE_HANDLE *hhcd, + uint8_t ch_num, + uint8_t direction, + uint8_t ep_type, + uint8_t token, + uint8_t *pbuff, + uint16_t length, + uint8_t do_ping) +{ + SYS_KDEBUG_LOG(SYS_DEBUG_USB, + ("%s: ch_num: %d, direction: %d, ", __func__, ch_num, direction)); + hhcd->host.hc[ch_num].ep_is_in = direction; + hhcd->host.hc[ch_num].ep_type = ep_type; + + if (token == 0U) + hhcd->host.hc[ch_num].data_pid = HC_PID_SETUP; + else + hhcd->host.hc[ch_num].data_pid = HC_PID_DATA1; + + /* Manage Data Toggle */ + switch (ep_type) { + case EP_TYPE_CTRL: + SYS_KDEBUG_LOG(SYS_DEBUG_USB, ("EP_TYPE_CTRL\n")); + if ((token == 1U) && (direction == 0U)) { + if (length == 0U) + hhcd->host.hc[ch_num].toggle_out = 1U; + + if (hhcd->host.hc[ch_num].toggle_out == 0U) + hhcd->host.hc[ch_num].data_pid = HC_PID_DATA0; + else + hhcd->host.hc[ch_num].data_pid = HC_PID_DATA1; + } + break; + + case EP_TYPE_BULK: + SYS_KDEBUG_LOG(SYS_DEBUG_USB, ("EP_TYPE_BULK\n")); + if (direction == 0U) { + if (hhcd->host.hc[ch_num].toggle_out == 0U) + hhcd->host.hc[ch_num].data_pid = HC_PID_DATA0; + else + hhcd->host.hc[ch_num].data_pid = HC_PID_DATA1; + } else { + if (hhcd->host.hc[ch_num].toggle_in == 0U) + hhcd->host.hc[ch_num].data_pid = HC_PID_DATA0; + else + hhcd->host.hc[ch_num].data_pid = HC_PID_DATA1; + } + break; + + case EP_TYPE_INTR: + SYS_KDEBUG_LOG(SYS_DEBUG_USB, ("EP_TYPE_INTR\n")); + if (direction == 0U) { + if (hhcd->host.hc[ch_num].toggle_out == 0U) + hhcd->host.hc[ch_num].data_pid = HC_PID_DATA0; + else + hhcd->host.hc[ch_num].data_pid = HC_PID_DATA1; + } else { + if (hhcd->host.hc[ch_num].toggle_in == 0U) + hhcd->host.hc[ch_num].data_pid = HC_PID_DATA0; + else + hhcd->host.hc[ch_num].data_pid = HC_PID_DATA1; + } + break; + + case EP_TYPE_ISOC: + SYS_KDEBUG_LOG(SYS_DEBUG_USB, ("EP_TYPE_ISOC\n")); + hhcd->host.hc[ch_num].data_pid = HC_PID_DATA0; + break; + + default: + break; + } + + hhcd->host.hc[ch_num].xfer_buff = pbuff; + hhcd->host.hc[ch_num].XferLen = length; + hhcd->host.HC_Status[ch_num] = HC_IDLE; + + return HCD_SubmitRequest(hhcd, ch_num); +} + +static int STM32USBHostPipeXfer(upipe_t pipe, uint8 token, void *buffer, int nbytes, int timeouts) +{ + int timeout = timeouts; + int interval = 1; + int retry = 0; + + while (1) { + if (!USB_OTG_Core.host.ConnSts) + return -1; + + // UrbCompletionSem = KSemaphoreCreate( 0); + KSemaphoreSetValue(UrbCompletionSem, 0); + STM32USBHostChannelSubmitRequest( + &USB_OTG_Core, + pipe->pipe_index, + (pipe->ep.bEndpointAddress & 0x80) >> 7, + pipe->ep.bmAttributes, + token, + buffer, + nbytes, + 0 + ); + + MdelayKTask(interval); + KSemaphoreObtain(UrbCompletionSem, timeout); + + if (HCD_GetHCState(&USB_OTG_Core, pipe->pipe_index) == HC_NAK) { + SYS_KDEBUG_LOG(SYS_DEBUG_USB, ("nak\n")); + if (pipe->ep.bmAttributes == USB_EP_ATTR_INT) + DelayKTask((pipe->ep.bInterval * TICK_PER_SECOND / 1000) > 0 ? (pipe->ep.bInterval * TICK_PER_SECOND / 1000) : 1); + if (interval < 10) { + interval += 1; + continue; + } + USB_OTG_HC_Halt(&USB_OTG_Core, pipe->pipe_index); + STM32USBHostChannelOpen( + &USB_OTG_Core, + pipe->pipe_index, + pipe->ep.bEndpointAddress, + pipe->inst->address, + USB_OTG_SPEED_FULL, + pipe->ep.bmAttributes, + pipe->ep.wMaxPacketSize + ); + if (++retry >= 10) { + SYS_KDEBUG_LOG(SYS_DEBUG_USB, ("NAK retry limit exceeded\n")); + return -1; + } + continue; + } else if (HCD_GetHCState(&USB_OTG_Core, pipe->pipe_index) == HC_STALL) { + SYS_KDEBUG_LOG(SYS_DEBUG_USB, ("stall\n")); + pipe->status = UPIPE_STATUS_STALL; + if (pipe->callback != NONE) + pipe->callback(pipe); + return -1; + } else if (HCD_GetHCState(&USB_OTG_Core, pipe->pipe_index) == URB_ERROR) { + SYS_KDEBUG_LOG(SYS_DEBUG_USB, ("error\n")); + pipe->status = UPIPE_STATUS_ERROR; + if (pipe->callback != NONE) + pipe->callback(pipe); + return -1; + } else if (URB_DONE == HCD_GetHCState(&USB_OTG_Core, pipe->pipe_index)) { + SYS_KDEBUG_LOG(SYS_DEBUG_USB, ("ok\n")); + pipe->status = UPIPE_STATUS_OK; + if (pipe->callback != NONE) + pipe->callback(pipe); + // size_t size = HAL_HCD_HC_GetXferCount(&USB_OTG_Core, pipe->pipe_index); + size_t size = USB_OTG_Core.host.XferCnt[pipe->pipe_index]; + if (pipe->ep.bEndpointAddress & 0x80) + return size; + else if (pipe->ep.bEndpointAddress & 0x00) + return size; + return nbytes; + } + + continue; + } +} + +static uint16 pipe_bitmap; + +static uint8 STM32USBHostAllocPipe() +{ + for (int i = 1; i < 16; i++) + if ((pipe_bitmap & (1 << i)) == 0) { + pipe_bitmap |= (1 << i); + return i; + } + + return 0xff; +} + +static void STM32USBHostFreePipe(int i) +{ + pipe_bitmap &= ~(1 << i); +} + +static x_err_t STM32USBHostOpenPipe(upipe_t pipe) +{ + pipe->pipe_index = STM32USBHostAllocPipe(); + + STM32USBHostChannelOpen(&USB_OTG_Core, pipe->pipe_index, pipe->ep.bEndpointAddress, + pipe->inst->address, USB_OTG_SPEED_FULL, pipe->ep.bmAttributes, + pipe->ep.wMaxPacketSize); + + if (USB_OTG_Core.host.hc[pipe->pipe_index].ep_is_in) + USB_OTG_Core.host.hc[pipe->pipe_index].toggle_in = 0; + else + USB_OTG_Core.host.hc[pipe->pipe_index].toggle_out = 0; + + return EOK; +} + +static x_err_t STM32USBHostClosePipe(upipe_t pipe) +{ + USB_OTG_HC_Halt(&USB_OTG_Core, pipe->pipe_index); + + STM32USBHostFreePipe(pipe->pipe_index); + + return EOK; +} + +/* implement these */ +static struct uhcd_ops USBHostOps = { + .reset_port = STM32USBHostResetPort, + .pipe_xfer = STM32USBHostPipeXfer, + .open_pipe = STM32USBHostOpenPipe, + .close_pipe = STM32USBHostClosePipe +}; + +static x_err_t STM32USBHostInit() +{ + KPrintf("\nINITIALIZING HOST......\n"); + + USB_OTG_BSP_Init(&USB_OTG_Core); + + HCD_Init(&USB_OTG_Core, USB_OTG_FS_CORE_ID); + + // RegisterHwIrq(OTG_FS_IRQn, OTG_FS_IRQHandler, NONE); + USB_OTG_BSP_ENABLE_INTERRUPT(&USB_OTG_Core); + + UrbCompletionSem = KSemaphoreCreate( 0); + + return EOK; +} + +int STM32USBHostRegister() +{ + UhcdPointer uhcd = (UhcdPointer)x_malloc(sizeof(struct uhcd)); + + memset(uhcd, 0, sizeof(struct uhcd)); + + uhcd->ops = &USBHostOps; + uhcd->NumPorts = 1; + + USB_OTG_Core.data = uhcd; + + UsbHostInit(uhcd); + STM32USBHostInit(); + + return EOK; +} + +long dump_usb_regs() +{ + volatile uint32_t *p = (volatile uint32_t *)0x50000000; + + while ((uint32_t)p < 0x50000000 + 80 * 4) { + KPrintf("0x%03X: 0x%08X\n", (uint32_t)p - 0x50000000, *p); + p++; + } + + return 0; +} +SHELL_EXPORT_CMD(SHELL_CMD_PERMISSION(0)|SHELL_CMD_TYPE(SHELL_TYPE_CMD_FUNC)|SHELL_CMD_PARAM_NUM(0),dump_usb_regs, dump_usb_regs, dump USB registers ); + +long dump_hc_regs() +{ + for (int i = 0; i < USB_OTG_MAX_TX_FIFOS; i++) { + USB_OTG_HC_REGS *regs = USB_OTG_Core.regs.HC_REGS[i]; + KPrintf("EP No.%d:\n", i); + KPrintf(" HCCHAR: 0x%08X\n", regs->HCCHAR); + KPrintf(" HCSPLT: 0x%08X\n", regs->HCSPLT); + KPrintf(" HCINT: 0x%08X\n", regs->HCINT); + KPrintf(" HCINTMSK: 0x%08X\n", regs->HCINTMSK); + KPrintf(" HCTSIZ: 0x%08X\n", regs->HCTSIZ); + KPrintf(" HCDMA: 0x%08X\n", regs->HCDMA); + } + + return 0; +} +SHELL_EXPORT_CMD(SHELL_CMD_PERMISSION(0)|SHELL_CMD_TYPE(SHELL_TYPE_CMD_FUNC)|SHELL_CMD_PARAM_NUM(0),dump_hc_regs, dump_hc_regs, dump_hc_regs ); diff --git a/Ubiquitous/XiZi/board/stm32f407-st-discovery/third_party_driver/watchdog/Kconfig b/Ubiquitous/XiZi/board/stm32f407-st-discovery/third_party_driver/watchdog/Kconfig new file mode 100644 index 0000000..59a4443 --- /dev/null +++ b/Ubiquitous/XiZi/board/stm32f407-st-discovery/third_party_driver/watchdog/Kconfig @@ -0,0 +1,14 @@ + +if BSP_USING_WDT +config WDT_BUS_NAME + string "watchdog bus name" + default "wdt" + +config WDT_DRIVER_NAME + string "watchdog driver name" + default "wdt_drv" + +config WDT_DEVICE_NAME + string "watchdog device name" + default "wdt_dev" +endif diff --git a/Ubiquitous/XiZi/board/stm32f407-st-discovery/third_party_driver/watchdog/Makefile b/Ubiquitous/XiZi/board/stm32f407-st-discovery/third_party_driver/watchdog/Makefile new file mode 100644 index 0000000..e141d69 --- /dev/null +++ b/Ubiquitous/XiZi/board/stm32f407-st-discovery/third_party_driver/watchdog/Makefile @@ -0,0 +1,5 @@ +SRC_FILES := hardware_wdg.c connect_wdg.c + + + +include $(KERNEL_ROOT)/compiler.mk diff --git a/Ubiquitous/XiZi/board/stm32f407-st-discovery/third_party_driver/watchdog/connect_wdg.c b/Ubiquitous/XiZi/board/stm32f407-st-discovery/third_party_driver/watchdog/connect_wdg.c new file mode 100644 index 0000000..bbbad0f --- /dev/null +++ b/Ubiquitous/XiZi/board/stm32f407-st-discovery/third_party_driver/watchdog/connect_wdg.c @@ -0,0 +1,132 @@ +/* +* Copyright (c) 2020 AIIT XUOS Lab +* XiUOS is licensed under Mulan PSL v2. +* You can use this software according to the terms and conditions of the Mulan PSL v2. +* You may obtain a copy of Mulan PSL v2 at: +* http://license.coscl.org.cn/MulanPSL2 +* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, +* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, +* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. +* See the Mulan PSL v2 for more details. +*/ + +/** +* @file connect_wdt.c +* @brief support stm32f407-st-discovery-board watchdog function and register to bus framework +* @version 1.0 +* @author AIIT XUOS Lab +* @date 2021-04-25 +*/ + +#include +#include "hardware_iwdg.h" +#include "connect_wdg.h" + +/** + * This function Watchdog configuration function + * + * @param arg Watchdog device Parameters + * + * @return EOK + */ +static int WdgSet(uint16_t arg) +{ + IWDG_Enable(); + IWDG_WriteAccessCmd(IWDG_WriteAccess_Enable); + IWDG_SetPrescaler(IWDG_Prescaler_16); + IWDG_SetReload(arg); + while(IWDG_GetFlagStatus(IWDG_FLAG_RVU) != RESET); + IWDG_ReloadCounter(); + return 0; +} +/** + * This function Watchdog initialization + * + * @param dev Watchdog driver structure handle + * + * @return EOK + */ +static uint32 WdtOpen(void *dev) +{ + WdgSet(4000); + return EOK; +} +/** + * This function Watchdog control function + * + * @param drv Watchdog driver structure handle + * + * @param args Watchdog driver Parameters + * + * @return EOK + */ +static uint32 WdtConfigure(void *drv, struct BusConfigureInfo *args) +{ + switch (args->configure_cmd) + { + case OPER_WDT_SET_TIMEOUT: + if (WdgSet((uint16_t)*(int *)args->private_data) != 0) { + return ERROR; + } + break; + case OPER_WDT_KEEPALIVE: + IWDG_ReloadCounter(); + break; + default: + return ERROR; + } + return EOK; +} + +static const struct WdtDevDone dev_done = +{ + WdtOpen, + NONE, + NONE, + NONE, +}; + +/** + * This function Watchdog initialization + * + * @return EOK + */ +int HwWdtInit(void) +{ + x_err_t ret = EOK; + + static struct WdtBus wdt; + static struct WdtDriver drv; + static struct WdtHardwareDevice dev; + + ret = WdtBusInit(&wdt, WDT_BUS_NAME); + if(ret != EOK){ + KPrintf("Watchdog bus init error %d\n", ret); + return ERROR; + } + + drv.configure = WdtConfigure; + ret = WdtDriverInit(&drv, WDT_DRIVER_NAME); + if (ret != EOK) { + KPrintf("Watchdog driver init error %d\n", ret); + return ERROR; + } + ret = WdtDriverAttachToBus(WDT_DRIVER_NAME, WDT_BUS_NAME); + if (ret != EOK) { + KPrintf("Watchdog driver attach error %d\n", ret); + return ERROR; + } + + dev.dev_done = &dev_done; + + ret = WdtDeviceRegister(&dev, WDT_DEVICE_NAME); + if (ret != EOK) { + KPrintf("Watchdog device register error %d\n", ret); + return ERROR; + } + ret = WdtDeviceAttachToBus(WDT_DEVICE_NAME, WDT_BUS_NAME); + if (ret != EOK) { + KPrintf("Watchdog device register error %d\n", ret); + return ERROR; + } +} diff --git a/Ubiquitous/XiZi/board/stm32f407zgt6/.defconfig b/Ubiquitous/XiZi/board/stm32f407zgt6/.defconfig new file mode 100644 index 0000000..70f621a --- /dev/null +++ b/Ubiquitous/XiZi/board/stm32f407zgt6/.defconfig @@ -0,0 +1,219 @@ +# +# Automatically generated file; DO NOT EDIT. +# XiZi Project Configuration +# +CONFIG_BOARD_STM32F407_EVB=y +CONFIG_KERNEL_CONSOLE_DEVICE_NAME="uart1" +CONFIG_ARCH_ARM=y + +# +# stm32f407zgt6 feature +# +CONFIG_BSP_USING_DMA=y +CONFIG_BSP_USING_GPIO=y +# CONFIG_BSP_USING_I2C is not set +# CONFIG_BSP_USING_LCD is not set +# CONFIG_BSP_USING_EXTMEM is not set +# CONFIG_BSP_USING_SDIO is not set +# CONFIG_BSP_USING_RTC is not set +# CONFIG_BSP_USING_SPI is not set +# CONFIG_BSP_USING_HWTIMER is not set +CONFIG_BSP_USING_WDT=y +CONFIG_BSP_USING_UART=y +CONFIG_BSP_USING_UART1=y +CONFIG_BSP_USING_UART2=y +CONFIG_BSP_USING_UART3=y +# CONFIG_BSP_USING_UART4 is not set +# CONFIG_BSP_USING_UART5 is not set +#CONFIG_BSP_USING_USB is not set +#CONFIG_BSP_USING_STM32_USBH is not set + +# +# Hardware feature +# +CONFIG_RESOURCES_SERIAL=y +CONFIG_SERIAL_USING_DMA=y +# CONFIG_SERIAL_RB_BUFSZ is not set +# CONFIG_RESOURCES_CAN is not set +# CONFIG_RESOURCES_HWTIMER is not set +# CONFIG_RESOURCES_I2C is not set +# CONFIG_RESOURCES_LCD is not set +# CONFIG_RESOURCES_SDIO is not set +# CONFIG_RESOURCES_TOUCH is not set +CONFIG_RESOURCES_PIN=y +# CONFIG_RESOURCES_RTC is not set +# CONFIG_RESOURCES_SPI is not set +# CONFIG_RESOURCES_SPI_SD is not set +# CONFIG_RESOURCES_SPI_SFUD is not set +# SFUD_USING_SFDP is not set +# SFUD_USING_FLASH_INFO_TABLE is not set +# SFUD_DEBUG_LOG is not set +CONFIG_RESOURCES_WDT=y +#CONFIG_RESOURCES_USB is not set +#CONFIG_RESOURCES_USB_HOST is not set +# CONFIG_UDISK_MOUNTPOINT is not set +# CONFIG_USBH_MSTORAGE is not set +#CONFIG_RESOURCES_USB_DEVICE is not set +# CONFIG_USBD_THREAD_STACK_SZ is not set + +# +# Kernel feature +# +# CONFIG_SEPARATE_COMPILE is not set +# CONFIG_COMPILER_APP is not set +# CONFIG_COMPILER_KERNEL is not set +# +# Kernel Device Object +# +CONFIG_KERNEL_DEVICE=y +CONFIG_KERNEL_CONSOLE=y +CONFIG_KERNEL_CONSOLEBUF_SIZE=128 + +# +# Task feature +# +CONFIG_SCHED_POLICY_RR_REMAINSLICE=y +# CONFIG_SCHED_POLICY_RR is not set +# CONFIG_SCHED_POLICY_FIFO is not set + +# +# Inter-Task communication +# +CONFIG_KERNEL_SEMAPHORE=y +CONFIG_KERNEL_MUTEX=y +CONFIG_KERNEL_EVENT=y +CONFIG_KERNEL_MESSAGEQUEUE=y +# CONFIG_KTASK_PRIORITY_8 is not set +CONFIG_KTASK_PRIORITY_32=y +# CONFIG_KTASK_PRIORITY_256 is not set +CONFIG_KTASK_PRIORITY_MAX=32 +CONFIG_TICK_PER_SECOND=1000 +CONFIG_KERNEL_STACK_OVERFLOW_CHECK=y +CONFIG_KERNEL_BANNER=y +# CONFIG_KERNEL_HOOK is not set +CONFIG_KERNEL_SOFTTIMER=y +CONFIG_KERNEL_IDLE_HOOK=y +CONFIG_IDEL_HOOK_LIST_SIZE=4 +CONFIG_IDLE_KTASK_STACKSIZE=256 +CONFIG_USER_APPLICATION=y +# CONFIG_TASK_ISOLATION is not set + +# +# Memory Management +# +# CONFIG_KERNEL_MEMBLOCK is not set + +# +# Command shell +# +CONFIG_TOOL_SHELL=y +CONFIG_SHELL_ENTER_CR=y +CONFIG_SHELL_ENTER_LF=y +CONFIG_SHELL_ENABLE_FILESYSTEM=y +CONFIG_SHELL_ENTER_CR_AND_LF=y +# CONFIG_SHELL_ENTER_CRLF is not set + +# +# User Control +# +CONFIG_SHELL_DEFAULT_USER="letter" +CONFIG_SHELL_DEFAULT_USER_PASSWORD="" +CONFIG_SHELL_LOCK_TIMEOUT=10000 +CONFIG_SHELL_TASK_STACK_SIZE=4096 +CONFIG_SHELL_TASK_PRIORITY=20 +CONFIG_SHELL_MAX_NUMBER=5 +CONFIG_SHELL_PARAMETER_MAX_NUMBER=8 +CONFIG_SHELL_HISTORY_MAX_NUMBER=5 +CONFIG_SHELL_PRINT_BUFFER=128 +CONFIG_SHELL_HELP_SHOW_PERMISSION=y +# CONFIG_SHELL_HELP_LIST_USER is not set +CONFIG_SHELL_HELP_LIST_VAR=y +# CONFIG_SHELL_HELP_LIST_KEY is not set +CONFIG_KERNEL_QUEUEMANAGE=y +CONFIG_KERNEL_WORKQUEUE=y +CONFIG_WORKQUEUE_KTASK_STACKSIZE=512 +CONFIG_WORKQUEUE_KTASK_PRIORITY=23 +CONFIG_KERNEL_WAITQUEUE=y +CONFIG_KERNEL_DATAQUEUE=y +# CONFIG_KERNEL_CIRCULAR_AREA is not set +# CONFIG_KERNEL_AVL_TREE is not set +CONFIG_NAME_NUM_MAX=32 +CONFIG_MEM_ALIGN_SIZE=8 +CONFIG_KERNEL_COMPONENTS_INIT=y +CONFIG_KERNEL_USER_MAIN=y +CONFIG_MAIN_KTASK_STACK_SIZE=2048 +CONFIG_ENV_INIT_KTASK_STACK_SIZE=8192 +CONFIG_MAIN_KTASK_PRIORITY=10 +# CONFIG_USER_TEST is not set +# CONFIG_TOOL_TEST_SEM is not set +# CONFIG_TOOL_TEST_MUTEX is not set +# CONFIG_TOOL_TEST_EVENT is not set +# CONFIG_TOOL_TEST_MSG is not set +# CONFIG_TOOL_TEST_AVLTREE is not set +# CONFIG_TEST_CRICULAR_AREA is not set +# CONFIG_TOOL_TEST_MEM is not set +# CONFIG_TOOL_TEST_TIMER is not set +# CONFIG_TOOL_TEST_IWG is not set +# CONFIG_TOOL_TEST_REALTIME is not set +# CONFIG_TOOL_TEST_DBG is not set +# CONFIG_TOOL_TEST_SCHED is not set +# CONFIG_KERNEL_DEBUG is not set +CONFIG_DEBUG_INIT_CONFIG=y +CONFIG_KDYN_LOG_DBG=y +CONFIG_DBG_INIT=1 +# CONFIG_ARCH_SMP is not set + +# +# File system +# +CONFIG_FS_VFS=y +CONFIG_VFS_USING_WORKDIR=y +CONFIG_FS_VFS_DEVFS=y + +# +# Fat filesystem +# + +# +# IOT-Device File system +# + +# +# Lwext4 filesystem +# + +# +# APP Framework +# + +# +# connection +# +# CONFIG_CONNECTION_AT is not set +# CONFIG_CONNECTION_MQTT is not set + +# +# medium communication +# + + +# +# Intelligence +# + +# +# Control +# + +# +# Lib +# +CONFIG_LIB=y +CONFIG_LIB_POSIX=y +CONFIG_LIB_NEWLIB=y + +CONFIG_LITTLEVGL2RTT_USING_DEMO=y + +# +# Security +# diff --git a/Ubiquitous/XiZi/board/stm32f407zgt6/Kconfig b/Ubiquitous/XiZi/board/stm32f407zgt6/Kconfig new file mode 100644 index 0000000..340dec6 --- /dev/null +++ b/Ubiquitous/XiZi/board/stm32f407zgt6/Kconfig @@ -0,0 +1,57 @@ +mainmenu "XiZi Project Configuration" + +config BSP_DIR + string + option env="BSP_ROOT" + default "." + +config KERNEL_DIR + string + option env="KERNEL_ROOT" + default "../.." + +config BOARD_STM32F407_EVB + bool + select ARCH_ARM + default y + +source "$KERNEL_DIR/arch/Kconfig" + +menu "stm32f407zgt6 feature" + source "$BSP_DIR/third_party_driver/Kconfig" + menu "config default board resources" + menu "config board app name" + config BOARD_APP_NAME + string "config board app name" + default "/XiUOS_stm32f407zgt6_app.bin" + endmenu + + menu "config board service table" + config SERVICE_TABLE_ADDRESS + hex "board service table address" + default 0x20000000 + endmenu + + menu "config hardware resources for connection" + if CONNECTION_COMMUNICATION_ETHERNET + config ETHERNET_UART_NAME + string "ethernet uart name" + default "/dev/usart3_dev3" + endif + if CONNECTION_COMMUNICATION_WIFI + config WIFI_UART_NAME + string "wifi uart name" + default "/dev/usart3_dev3" + endif + + endmenu + + endmenu +endmenu + + +menu "Hardware feature" +source "$KERNEL_DIR/resources/Kconfig" +endmenu + +source "$KERNEL_DIR/Kconfig" diff --git a/Ubiquitous/XiZi/board/stm32f407zgt6/Makefile b/Ubiquitous/XiZi/board/stm32f407zgt6/Makefile new file mode 100644 index 0000000..65bddea --- /dev/null +++ b/Ubiquitous/XiZi/board/stm32f407zgt6/Makefile @@ -0,0 +1,8 @@ +SRC_FILES := board.c + +SRC_DIR := third_party_driver + + + + +include $(KERNEL_ROOT)/compiler.mk diff --git a/Ubiquitous/XiZi/board/stm32f407zgt6/README.md b/Ubiquitous/XiZi/board/stm32f407zgt6/README.md new file mode 100644 index 0000000..7a519b8 --- /dev/null +++ b/Ubiquitous/XiZi/board/stm32f407zgt6/README.md @@ -0,0 +1,81 @@ +# Stm32F407zgt6-BOARD README + +## 1. 简介 + +| 硬件 | 描述 | +| -- | -- | +|芯片型号| Stm32F407zgt6| +|CPU|arm cortex-m| +|主频| 168MHz | +|片内SRAM| 192KB | +|扩展SRAM| 1MB | +|片上FLASH| 512KB | +| 外设 | 内嵌FPU处理器 | +| | DCMI、JTAG、OTG、ADC、DAC、USB、GPIO、UART、SPI、SDIO、RTC、I²S、CAN、DMA、MAC、I²C、WDT、Timer与PWM | + +XiUOS板级当前支持使用GPIO和UART。 + +## 2. 编译说明 + +### 编译环境：Ubuntu18.04 + +### 编译工具链：arm-none-eabi-gcc + +编译步骤： +> 1.ARM下编译需要安装arm-none-eabi编译工具, 安装到Ubuntu的默认路径/usr/bin/arm-none-eabi-，使用如下命令行下载 +``` +sudo apt-get install gcc-arm-none-eabi +``` +>2.在代码根目录下执行以下命令，生成配置文件 + +``` +cd ./Ubiquitous/XiZi +make BOARD=stm32f407zgt6 distclean +make BOARD=stm32f407zgt6 menuconfig +``` +>3.在menuconfig界面配置需要关闭和开启的功能，按回车键进入下级菜单，按Y键选中需要开启的功能，按N键选中需要关闭的功能，配置结束后保存并退出 + +![img](./img/menu.png ) + +>4.继续执行以下命令，进行编译 +``` +make BOARD=stm32f407zgt6 +``` +>5.如果编译正确无误，会产生XiZi_stm32f407zgt6.elf、XiZi_stm32f407zgt6.bin文件。其中XiZi_stm32f407zgt6.bin需要烧写到设备中进行运行。 +``` +sudo write build/XiZi_stm32f407zgt6.bin 0x8000000 +``` +>6.最后可以执行以下命令，清除配置文件和编译生成的文件 +``` +make BOARD=stm32f407zgt6 distclean +``` + +## 3. 烧写及执行 + +将 BOARD=stm32f407zgt6开发板SWD经 st-link 转接到USB接口，然后使用st-flash工具进行烧写bin文件。 + +执行以下命令下载st-link工具 +``` +git clone https://github.com/texane/stlink.git +``` + +开发板接口如下： +
+ +
+ + 实际连接图为： +
+ +
+ +在代码根目录下执行st-flash工具烧录 +``` +sudo st-flash write build/XiZi_stm32f407zgt6.bin 0x8000000 +``` +### 3.1 运行结果 + +如果编译 & 烧写无误，将会在串口终端上看到信息打印输出，(终端串口引脚为PB6、PB7)。 +
+ +
diff --git a/Ubiquitous/XiZi/board/stm32f407zgt6/board.c b/Ubiquitous/XiZi/board/stm32f407zgt6/board.c new file mode 100644 index 0000000..504b616 --- /dev/null +++ b/Ubiquitous/XiZi/board/stm32f407zgt6/board.c @@ -0,0 +1,146 @@ +/* +* Copyright (c) 2020 AIIT XUOS Lab +* XiUOS is licensed under Mulan PSL v2. +* You can use this software according to the terms and conditions of the Mulan PSL v2. +* You may obtain a copy of Mulan PSL v2 at: +* http://license.coscl.org.cn/MulanPSL2 +* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, +* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, +* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. +* See the Mulan PSL v2 for more details. +*/ + +/** +* @file board.c +* @brief support stm32f407zgt6-board init configure and start-up +* @version 1.0 +* @author AIIT XUOS Lab +* @date 2021-04-25 +*/ + +/************************************************* +File name: board.c +Description: support stm32f407zgt6-board init configure and driver/task/... init +Others: +History: +1. Date: 2021-04-25 +Author: AIIT XUOS Lab +Modification: +1. support stm32f407zgt6-board InitBoardHardware +*************************************************/ + +#include +#include "stm32f4xx.h" +#include "hardware_rcc.h" +#include "board.h" +#include "connect_usart.h" +#include "connect_gpio.h" +#include "connect_fsmc.h" +#include "misc.h" + +extern void entry(void); +extern int Stm32HwPinInit(void); +extern int Stm32HwUsartInit(); + +static void ClockConfiguration() +{ + RCC_HSEConfig(RCC_HSE_ON); + if (RCC_WaitForHSEStartUp() == SUCCESS) + { + RCC_HCLKConfig(RCC_SYSCLK_Div1); + RCC_PCLK2Config(RCC_HCLK_Div2); + RCC_PCLK1Config(RCC_HCLK_Div4); + RCC_PLLConfig(RCC_PLLSource_HSE, 8, 336, 2, 7); + + RCC_PLLCmd(ENABLE); + while (RCC_GetFlagStatus(RCC_FLAG_PLLRDY) == RESET); + + FLASH->ACR = FLASH_ACR_ICEN |FLASH_ACR_DCEN |FLASH_ACR_LATENCY_5WS; + RCC_SYSCLKConfig(RCC_SYSCLKSource_PLLCLK); + + while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS ) != RCC_CFGR_SWS_PLL); + + } + SystemCoreClockUpdate(); +} + +void NVIC_Configuration(void) +{ +#ifdef VECT_TAB_RAM + NVIC_SetVectorTable(NVIC_VectTab_RAM, 0x0); +#else + NVIC_SetVectorTable(NVIC_VectTab_FLASH, 0x0); +#endif + + NVIC_PriorityGroupConfig(NVIC_PriorityGroup_2); +} + +void SysTickConfiguration(void) +{ + RCC_ClocksTypeDef rcc_clocks; + uint32 cnts; + + RCC_GetClocksFreq(&rcc_clocks); + + cnts = (uint32)rcc_clocks.HCLK_Frequency / TICK_PER_SECOND; + cnts = cnts / 8; + + SysTick_Config(cnts); + SysTick_CLKSourceConfig(SysTick_CLKSource_HCLK_Div8); +} + +void SysTick_Handler(int irqn, void *arg) +{ + + TickAndTaskTimesliceUpdate(); + +} +DECLARE_HW_IRQ(SysTick_IRQn, SysTick_Handler, NONE); + +void stm32f407_start() +{ + entry(); +} +struct InitSequenceDesc _board_init[] = +{ +#ifdef BSP_USING_GPIO + { "hw pin", Stm32HwGpioInit }, +#endif +#ifdef BSP_USING_EXTMEM + { "hw extern sram", HwSramInit }, +#endif + { " NONE ",NONE }, +}; + +void InitBoardHardware() +{ + int i = 0; + int ret = 0; + ClockConfiguration(); + + NVIC_Configuration(); + + SysTickConfiguration(); + InitBoardMemory((void*)MEMORY_START_ADDRESS, (void*)MEMORY_END_ADDRESS); +#ifdef BSP_USING_UART + Stm32HwUsartInit(); +#endif +#ifdef KERNEL_CONSOLE + InstallConsole(KERNEL_CONSOLE_BUS_NAME, KERNEL_CONSOLE_DRV_NAME, KERNEL_CONSOLE_DEVICE_NAME); + KPrintf("\nconsole init completed.\n"); + KPrintf("board initialization......\n"); +#endif + +#ifdef SEPARATE_COMPILE + +#endif + + for(i = 0; _board_init[i].fn != NONE; i++) { + ret = _board_init[i].fn(); + KPrintf("initialize %s %s\n",_board_init[i].fn_name, ret == 0 ? "success" : "failed"); + } + + KPrintf("board init done.\n"); + KPrintf("start kernel...\n"); + +} \ No newline at end of file diff --git a/Ubiquitous/XiZi/board/stm32f407zgt6/board.h b/Ubiquitous/XiZi/board/stm32f407zgt6/board.h new file mode 100644 index 0000000..b374e82 --- /dev/null +++ b/Ubiquitous/XiZi/board/stm32f407zgt6/board.h @@ -0,0 +1,91 @@ +/* +* Copyright (c) 2020 AIIT XUOS Lab +* XiUOS is licensed under Mulan PSL v2. +* You can use this software according to the terms and conditions of the Mulan PSL v2. +* You may obtain a copy of Mulan PSL v2 at: +* http://license.coscl.org.cn/MulanPSL2 +* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, +* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, +* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. +* See the Mulan PSL v2 for more details. +*/ + +/** +* @file board.h +* @brief define stm32f407zgt6-board init configure and start-up function +* @version 1.0 +* @author AIIT XUOS Lab +* @date 2021-04-25 +*/ + +/************************************************* +File name: board.h +Description: define stm32f407zgt6-board board init function and struct +Others: +History: +1. Date: 2021-04-25 +Author: AIIT XUOS Lab +Modification: +1. define stm32f407zgt6-board InitBoardHardware +2. define stm32f407zgt6-board data and bss struct +*************************************************/ + +#ifndef BOARD_H +#define BOARD_H + +#include +#include + +extern int __stack_end__; +extern unsigned int g_service_table_start; +extern unsigned int g_service_table_end; + +#define STM32_USE_SDIO 0 + +#define STM32_EXT_SRAM 0 +#define STM32_EXT_SRAM_BEGIN 0x68000000 +#define STM32_EXT_SRAM_END 0x68080000 + +#define SURPORT_MPU + +#ifdef __ICCARM__ +extern char __ICFEDIT_region_RAM_end__; +#define STM32_SRAM_END &__ICFEDIT_region_RAM_end__ +#else + +#define MEMORY_START_ADDRESS (&__stack_end__) +#define STM32_SRAM_SIZE 128 +#define MEMORY_END_ADDRESS (0x20000000 + STM32_SRAM_SIZE * 1024) + +#ifdef SEPARATE_COMPILE +typedef int (*main_t)(int argc, char *argv[]); +typedef void (*exit_t)(void); +struct userspace_s +{ + main_t us_entrypoint; + exit_t us_taskquit; + uintptr_t us_textstart; + uintptr_t us_textend; + uintptr_t us_datasource; + uintptr_t us_datastart; + uintptr_t us_dataend; + uintptr_t us_bssstart; + uintptr_t us_bssend; + uintptr_t us_heapend; +}; +#define USERSPACE (( struct userspace_s *)(0x08040000)) + +#ifndef SERVICE_TABLE_ADDRESS +#define SERVICE_TABLE_ADDRESS (0x20000000) +#endif + +#define USER_SRAM_SIZE 64 +#define USER_MEMORY_START_ADDRESS (USERSPACE->us_bssend) +#define USER_MEMORY_END_ADDRESS (0x10000000 + USER_SRAM_SIZE * 1024) +#endif +#endif + +void InitBoardHardware(void); +void stm32f407_start(void); + +#endif \ No newline at end of file diff --git a/Ubiquitous/XiZi/board/stm32f407zgt6/config.mk b/Ubiquitous/XiZi/board/stm32f407zgt6/config.mk new file mode 100644 index 0000000..ceb9874 --- /dev/null +++ b/Ubiquitous/XiZi/board/stm32f407zgt6/config.mk @@ -0,0 +1,16 @@ +export CROSS_COMPILE ?=/usr/bin/arm-none-eabi- + +export CFLAGS := -mcpu=cortex-m4 -mthumb -mfpu=fpv4-sp-d16 -mfloat-abi=hard -ffunction-sections -fdata-sections -Dgcc -O0 -gdwarf-2 -g -fgnu89-inline -Wa,-mimplicit-it=thumb -Werror +export AFLAGS := -c -mcpu=cortex-m4 -mthumb -mfpu=fpv4-sp-d16 -mfloat-abi=hard -ffunction-sections -fdata-sections -x assembler-with-cpp -Wa,-mimplicit-it=thumb -gdwarf-2 +export LFLAGS := -mcpu=cortex-m4 -mthumb -mfpu=fpv4-sp-d16 -mfloat-abi=hard -ffunction-sections -fdata-sections -Wl,--gc-sections,-Map=XiZi.map,-cref,-u,Reset_Handler -T $(BSP_ROOT)/link.lds +export CXXFLAGS := -mcpu=cortex-m4 -mthumb -mfpu=fpv4-sp-d16 -mfloat-abi=hard -ffunction-sections -fdata-sections -Dgcc -O0 -gdwarf-2 -g -Werror + +export APPLFLAGS := -mcpu=cortex-m4 -mthumb -mfpu=fpv4-sp-d16 -mfloat-abi=hard -ffunction-sections -fdata-sections -Wl,--gc-sections,-Map=XiZi_app.map,-cref,-u, -T $(BSP_ROOT)/link_userspace.lds + +export DEFINES := -DHAVE_CCONFIG_H -DSTM32F407xx -DUSE_HAL_DRIVER -DHAVE_SIGINFO + +export USING_NEWLIB =1 +export USING_VFS = 1 +export USING_SPI = 1 +export ARCH = arm +export USING_LORA = 1 diff --git a/Ubiquitous/XiZi/board/stm32f407zgt6/img/interface.jpg b/Ubiquitous/XiZi/board/stm32f407zgt6/img/interface.jpg new file mode 100644 index 0000000..5b45ad1 Binary files /dev/null and b/Ubiquitous/XiZi/board/stm32f407zgt6/img/interface.jpg differ diff --git a/Ubiquitous/XiZi/board/stm32f407zgt6/img/menu.png b/Ubiquitous/XiZi/board/stm32f407zgt6/img/menu.png new file mode 100644 index 0000000..6a99f10 Binary files /dev/null and b/Ubiquitous/XiZi/board/stm32f407zgt6/img/menu.png differ diff --git a/Ubiquitous/XiZi/board/stm32f407zgt6/img/shell.png b/Ubiquitous/XiZi/board/stm32f407zgt6/img/shell.png new file mode 100644 index 0000000..055b163 Binary files /dev/null and b/Ubiquitous/XiZi/board/stm32f407zgt6/img/shell.png differ diff --git a/Ubiquitous/XiZi/board/stm32f407zgt6/img/total.jpg b/Ubiquitous/XiZi/board/stm32f407zgt6/img/total.jpg new file mode 100644 index 0000000..595639f Binary files /dev/null and b/Ubiquitous/XiZi/board/stm32f407zgt6/img/total.jpg differ diff --git a/Ubiquitous/XiZi/board/stm32f407zgt6/link.lds b/Ubiquitous/XiZi/board/stm32f407zgt6/link.lds new file mode 100644 index 0000000..8fa026c --- /dev/null +++ b/Ubiquitous/XiZi/board/stm32f407zgt6/link.lds @@ -0,0 +1,111 @@ +/* +* Copyright (c) 2020 AIIT XUOS Lab +* XiUOS is licensed under Mulan PSL v2. +* You can use this software according to the terms and conditions of the Mulan PSL v2. +* You may obtain a copy of Mulan PSL v2 at: +* http://license.coscl.org.cn/MulanPSL2 +* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, +* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, +* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. +* See the Mulan PSL v2 for more details. +*/ + +__SYSTEM_STACKSIZE__ = 0x400; + +OUTPUT_ARCH(arm) + +MEMORY +{ + flash (rx) : ORIGIN = 0x08000000, LENGTH = 256k /* 512KB flash */ + sram (rw) : ORIGIN = 0x20001000, LENGTH = 124k /* 124k sram */ +} + +ENTRY(Reset_Handler) +SECTIONS +{ + .text : + { + . = ALIGN(4); + PROVIDE(_stext = ABSOLUTE(.)); + KEEP(*(.isr_vector)) /* Startup code */ + + + . = ALIGN(4); + *(.text .text.*) /* Normal code */ + *(.rodata .rodata*) /* read-only data (constants) */ + + *(.glue_7) + *(.glue_7t) + + /* section information for shell */ + . = ALIGN(4); + _shell_command_start = .; + KEEP (*(shellCommand)) + _shell_command_end = .; + . = ALIGN(4); + + /* the work i did */ + PROVIDE(__ctors_start__ = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array)) + PROVIDE(__ctors_end__ = .); + + . = ALIGN(4); + /* the work i did */ + + __isrtbl_idx_start = .; + KEEP(*(.isrtbl.idx)) + __isrtbl_start = .; + KEEP(*(.isrtbl)) + __isrtbl_end = .; + . = ALIGN(4); + + PROVIDE(g_service_table_start = ABSOLUTE(.)); + KEEP(*(.g_service_table)) + PROVIDE(g_service_table_end = ABSOLUTE(.)); + + PROVIDE(_etext = ABSOLUTE(.)); + } > flash + + /* .ARM.exidx is sorted, so has to go in its own output section. */ + __exidx_start = .; + .ARM.exidx : + { + PROVIDE(__exidx_start = ABSOLUTE(.)); + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + _sidata = .; + PROVIDE(__exidx_end = ABSOLUTE(.)); + } > flash + + .data : AT(__exidx_end) + { + . = ALIGN(4); + PROVIDE(_sdata = ABSOLUTE(.)); + *(.data .data.*) + PROVIDE(_edata = ABSOLUTE(.)); + } > sram + + .bss : + { + . = ALIGN(4); + __bss_start = ABSOLUTE(.); + + *(.bss .bss.*) + *(COMMON) + + . = ALIGN(4); + __bss_end = ABSOLUTE(.); + } > sram + + .stack : + { + . = ALIGN(4); + PROVIDE(__stack_start__ = ABSOLUTE(.)); + /* cpu stack */ + . = . + __SYSTEM_STACKSIZE__; + __stack_tp = .; + PROVIDE(__stack_end__ = ABSOLUTE(.)); + } > sram + + _end = ABSOLUTE(.); +} diff --git a/Ubiquitous/XiZi/board/stm32f407zgt6/link_userspace.lds b/Ubiquitous/XiZi/board/stm32f407zgt6/link_userspace.lds new file mode 100644 index 0000000..17be4ca --- /dev/null +++ b/Ubiquitous/XiZi/board/stm32f407zgt6/link_userspace.lds @@ -0,0 +1,72 @@ +/* +* Copyright (c) 2020 AIIT XUOS Lab +* XiUOS is licensed under Mulan PSL v2. +* You can use this software according to the terms and conditions of the Mulan PSL v2. +* You may obtain a copy of Mulan PSL v2 at: +* http://license.coscl.org.cn/MulanPSL2 +* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, +* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, +* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. +* See the Mulan PSL v2 for more details. +*/ + +OUTPUT_ARCH(arm) + +MEMORY +{ + uflash (rx) : ORIGIN = 0x08040000, LENGTH = 256k /* 256KB uflash */ + usram (rw) : ORIGIN = 0x10000000, LENGTH = 64k /* 64K usram */ +} + +SECTIONS +{ + .userspace : + { + . = ALIGN(4); + KEEP(*(.userspace)) + } > uflash + + .text : + { + _ustext = ABSOLUTE(.); + *(.text .text.*) + *(.rodata .rodata*) + *(.glue_7) + *(.glue_7t) + PROVIDE(_uetext = ABSOLUTE(.)); + } > uflash + + .init_section : { + _sinit = ABSOLUTE(.); + KEEP(*(.init_array .init_array.*)) + _einit = ABSOLUTE(.); + } > uflash + + __uexidx_start = ABSOLUTE(.); + + .ARM.exidx : + { + PROVIDE(__uexidx_start = ABSOLUTE(.)); + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + PROVIDE(__uexidx_end = ABSOLUTE(.)); + } > uflash + + _ueronly = ABSOLUTE(.); + + .data : AT(_ueronly) + { + _usdata = ABSOLUTE(.); + *(.data .data.*) + . = ALIGN(4); + _uedata = ABSOLUTE(.); + } > usram + + .bss : { + . = ALIGN(4); + _usbss = ABSOLUTE(.); + *(.bss .bss.*) + *(.sbss .sbss.*) + . = ALIGN(4); + _uebss = ABSOLUTE(.); + } > usram +} \ No newline at end of file diff --git a/Ubiquitous/XiZi/board/stm32f407zgt6/third_party_driver/Kconfig b/Ubiquitous/XiZi/board/stm32f407zgt6/third_party_driver/Kconfig new file mode 100755 index 0000000..b83f2dd --- /dev/null +++ b/Ubiquitous/XiZi/board/stm32f407zgt6/third_party_driver/Kconfig @@ -0,0 +1,24 @@ + +menuconfig BSP_USING_GPIO +bool "Using GPIO device " +default y +select RESOURCES_PIN +if BSP_USING_GPIO +source "$BSP_DIR/third_party_driver/gpio/Kconfig" +endif + +menuconfig BSP_USING_UART +bool "Using UART device" +default y +select RESOURCES_SERIAL +if BSP_USING_UART +source "$BSP_DIR/third_party_driver/uart/Kconfig" +endif + +menuconfig BSP_USING_EXTMEM +bool "Using extern memory" +default n +select MEM_EXTERN_SRAM +if BSP_USING_EXTMEM +source "$BSP_DIR/third_party_driver/extmem/Kconfig" +endif diff --git a/Ubiquitous/XiZi/board/stm32f407zgt6/third_party_driver/Makefile b/Ubiquitous/XiZi/board/stm32f407zgt6/third_party_driver/Makefile new file mode 100644 index 0000000..36c8617 --- /dev/null +++ b/Ubiquitous/XiZi/board/stm32f407zgt6/third_party_driver/Makefile @@ -0,0 +1,16 @@ + +SRC_DIR := common + +ifeq ($(CONFIG_BSP_USING_GPIO),y) + SRC_DIR += gpio +endif + +ifeq ($(CONFIG_BSP_USING_UART),y) + SRC_DIR += uart +endif + +ifeq ($(CONFIG_BSP_USING_EXTMEM),y) + SRC_DIR += extmem +endif + +include $(KERNEL_ROOT)/compiler.mk diff --git a/Ubiquitous/XiZi/board/stm32f407zgt6/third_party_driver/extmem/Kconfig b/Ubiquitous/XiZi/board/stm32f407zgt6/third_party_driver/extmem/Kconfig new file mode 100644 index 0000000..27186cb --- /dev/null +++ b/Ubiquitous/XiZi/board/stm32f407zgt6/third_party_driver/extmem/Kconfig @@ -0,0 +1,17 @@ +if BSP_USING_EXTMEM + config EXTSRAM_MAX_NUM + int + default 4 + + config BSP_USING_FSMC_BANK1_NORSRAM3 + bool "config fsmc bank1 sram3" + default n + if BSP_USING_FSMC_BANK1_NORSRAM3 + config BANK1_NORSRAM3_SIZE + hex "config sram3 chip size" + default 0x100000 + config BANK1_NORSRAM3_DATA_WIDTH + int "config sram3 chip data width" + default 16 + endif +endif diff --git a/Ubiquitous/XiZi/board/stm32f407zgt6/third_party_driver/extmem/Makefile b/Ubiquitous/XiZi/board/stm32f407zgt6/third_party_driver/extmem/Makefile new file mode 100644 index 0000000..81594a1 --- /dev/null +++ b/Ubiquitous/XiZi/board/stm32f407zgt6/third_party_driver/extmem/Makefile @@ -0,0 +1,3 @@ +SRC_FILES := hardware_fsmc.c connect_fsmc.c + +include $(KERNEL_ROOT)/compiler.mk diff --git a/Ubiquitous/XiZi/board/stm32f407zgt6/third_party_driver/extmem/connect_fsmc.c b/Ubiquitous/XiZi/board/stm32f407zgt6/third_party_driver/extmem/connect_fsmc.c new file mode 100644 index 0000000..7431393 --- /dev/null +++ b/Ubiquitous/XiZi/board/stm32f407zgt6/third_party_driver/extmem/connect_fsmc.c @@ -0,0 +1,162 @@ +/* +* Copyright (c) 2020 AIIT XUOS Lab +* XiUOS is licensed under Mulan PSL v2. +* You can use this software according to the terms and conditions of the Mulan PSL v2. +* You may obtain a copy of Mulan PSL v2 at: +* http://license.coscl.org.cn/MulanPSL2 +* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, +* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, +* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. +* See the Mulan PSL v2 for more details. +*/ + +/** +* @file connect_fsmc.c +* @brief support extern memory by fsmc +* @version 1.0 +* @author AIIT XUOS Lab +* @date 2021-05-28 +*/ + +#include "connect_fsmc.h" +#include "hardware_fsmc.h" +#include "hardware_gpio.h" +#include "hardware_rcc.h" +#include +#include + +#define FSMC_BANK1_NORSRAM3_START_ADDRESS 0x68000000 + +static FSMC_NORSRAMInitTypeDef hsram3; +static FSMC_NORSRAMTimingInitTypeDef hsram_read3; +static FSMC_NORSRAMTimingInitTypeDef hsram_write3; + +extern void ExtSramInitBoardMemory(void *start_phy_address, void *end_phy_address, uint8 extsram_idx); + +int HwSramInit(void) +{ + GPIO_InitTypeDef GPIO_InitStructure; + + RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOD|RCC_AHB1Periph_GPIOE|RCC_AHB1Periph_GPIOF|RCC_AHB1Periph_GPIOG, ENABLE); + RCC_AHB3PeriphClockCmd(RCC_AHB3Periph_FSMC,ENABLE); + + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0 | GPIO_Pin_1 | GPIO_Pin_4 | GPIO_Pin_5 | GPIO_Pin_8 | GPIO_Pin_9 | GPIO_Pin_10 | GPIO_Pin_11 | GPIO_Pin_12 | GPIO_Pin_13 | GPIO_Pin_14 | GPIO_Pin_15; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF; + GPIO_InitStructure.GPIO_OType = GPIO_OType_PP; + GPIO_InitStructure.GPIO_Speed = GPIO_Speed_100MHz; + GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL; + GPIO_Init(GPIOD, &GPIO_InitStructure); + + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_7 | GPIO_Pin_8 | GPIO_Pin_9 | GPIO_Pin_10 | GPIO_Pin_11 | GPIO_Pin_12 | GPIO_Pin_13 | GPIO_Pin_14 | GPIO_Pin_15; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF; + GPIO_InitStructure.GPIO_OType = GPIO_OType_PP; + GPIO_InitStructure.GPIO_Speed = GPIO_Speed_100MHz; + GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL; + GPIO_Init(GPIOE, &GPIO_InitStructure); + + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0 | GPIO_Pin_1 | GPIO_Pin_2 | GPIO_Pin_3 | GPIO_Pin_4 | GPIO_Pin_5 | GPIO_Pin_12 | GPIO_Pin_13 | GPIO_Pin_14 | GPIO_Pin_15; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF; + GPIO_InitStructure.GPIO_OType = GPIO_OType_PP; + GPIO_InitStructure.GPIO_Speed = GPIO_Speed_100MHz; + GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL; + GPIO_Init(GPIOF, &GPIO_InitStructure); + + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0 | GPIO_Pin_1 | GPIO_Pin_2 | GPIO_Pin_3 | GPIO_Pin_4 | GPIO_Pin_5 | GPIO_Pin_10 | GPIO_Pin_12; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF; + GPIO_InitStructure.GPIO_OType = GPIO_OType_PP; + GPIO_InitStructure.GPIO_Speed = GPIO_Speed_100MHz; + GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL; + GPIO_Init(GPIOG, &GPIO_InitStructure); + + GPIO_PinAFConfig(GPIOD,GPIO_PinSource0,GPIO_AF_FSMC); + GPIO_PinAFConfig(GPIOD,GPIO_PinSource1,GPIO_AF_FSMC); + GPIO_PinAFConfig(GPIOD,GPIO_PinSource4,GPIO_AF_FSMC); + GPIO_PinAFConfig(GPIOD,GPIO_PinSource5,GPIO_AF_FSMC); + GPIO_PinAFConfig(GPIOD,GPIO_PinSource8,GPIO_AF_FSMC); + GPIO_PinAFConfig(GPIOD,GPIO_PinSource9,GPIO_AF_FSMC); + GPIO_PinAFConfig(GPIOD,GPIO_PinSource10,GPIO_AF_FSMC); + GPIO_PinAFConfig(GPIOD,GPIO_PinSource11,GPIO_AF_FSMC); + GPIO_PinAFConfig(GPIOD,GPIO_PinSource12,GPIO_AF_FSMC); + GPIO_PinAFConfig(GPIOD,GPIO_PinSource13,GPIO_AF_FSMC); + GPIO_PinAFConfig(GPIOD,GPIO_PinSource14,GPIO_AF_FSMC); + GPIO_PinAFConfig(GPIOD,GPIO_PinSource15,GPIO_AF_FSMC); + + GPIO_PinAFConfig(GPIOE,GPIO_PinSource7,GPIO_AF_FSMC); + GPIO_PinAFConfig(GPIOE,GPIO_PinSource8,GPIO_AF_FSMC); + GPIO_PinAFConfig(GPIOE,GPIO_PinSource9,GPIO_AF_FSMC); + GPIO_PinAFConfig(GPIOE,GPIO_PinSource10,GPIO_AF_FSMC); + GPIO_PinAFConfig(GPIOE,GPIO_PinSource11,GPIO_AF_FSMC); + GPIO_PinAFConfig(GPIOE,GPIO_PinSource12,GPIO_AF_FSMC); + GPIO_PinAFConfig(GPIOE,GPIO_PinSource13,GPIO_AF_FSMC); + GPIO_PinAFConfig(GPIOE,GPIO_PinSource14,GPIO_AF_FSMC); + GPIO_PinAFConfig(GPIOE,GPIO_PinSource15,GPIO_AF_FSMC); + + GPIO_PinAFConfig(GPIOF,GPIO_PinSource0,GPIO_AF_FSMC); + GPIO_PinAFConfig(GPIOF,GPIO_PinSource1,GPIO_AF_FSMC); + GPIO_PinAFConfig(GPIOF,GPIO_PinSource2,GPIO_AF_FSMC); + GPIO_PinAFConfig(GPIOF,GPIO_PinSource3,GPIO_AF_FSMC); + GPIO_PinAFConfig(GPIOF,GPIO_PinSource4,GPIO_AF_FSMC); + GPIO_PinAFConfig(GPIOF,GPIO_PinSource5,GPIO_AF_FSMC); + GPIO_PinAFConfig(GPIOF,GPIO_PinSource12,GPIO_AF_FSMC); + GPIO_PinAFConfig(GPIOF,GPIO_PinSource13,GPIO_AF_FSMC); + GPIO_PinAFConfig(GPIOF,GPIO_PinSource14,GPIO_AF_FSMC); + GPIO_PinAFConfig(GPIOF,GPIO_PinSource15,GPIO_AF_FSMC); + + GPIO_PinAFConfig(GPIOG,GPIO_PinSource0,GPIO_AF_FSMC); + GPIO_PinAFConfig(GPIOG,GPIO_PinSource1,GPIO_AF_FSMC); + GPIO_PinAFConfig(GPIOG,GPIO_PinSource2,GPIO_AF_FSMC); + GPIO_PinAFConfig(GPIOG,GPIO_PinSource3,GPIO_AF_FSMC); + GPIO_PinAFConfig(GPIOG,GPIO_PinSource4,GPIO_AF_FSMC); + GPIO_PinAFConfig(GPIOG,GPIO_PinSource5,GPIO_AF_FSMC); + GPIO_PinAFConfig(GPIOG,GPIO_PinSource10,GPIO_AF_FSMC); + GPIO_PinAFConfig(GPIOG,GPIO_PinSource12,GPIO_AF_FSMC); + + hsram3.FSMC_ReadWriteTimingStruct = &hsram_read3; + hsram3.FSMC_WriteTimingStruct = &hsram_write3; + + /* hsram3.Init */ + hsram3.FSMC_DataAddressMux = FSMC_DataAddressMux_Disable; + hsram3.FSMC_MemoryType = FSMC_MemoryType_SRAM; + hsram3.FSMC_BurstAccessMode = FSMC_BurstAccessMode_Disable; + hsram3.FSMC_WaitSignalPolarity = FSMC_WaitSignalPolarity_Low; + hsram3.FSMC_WrapMode = FSMC_WrapMode_Disable; + hsram3.FSMC_WaitSignalActive = FSMC_WaitSignalActive_BeforeWaitState; + hsram3.FSMC_WriteOperation = FSMC_WriteOperation_Enable; + hsram3.FSMC_WaitSignal = FSMC_WaitSignal_Disable; + hsram3.FSMC_ExtendedMode = FSMC_ExtendedMode_Disable; + hsram3.FSMC_WriteBurst = FSMC_WriteBurst_Disable; + + hsram_read3.FSMC_AddressSetupTime = 0; + hsram_read3.FSMC_AddressHoldTime = 0; + hsram_read3.FSMC_DataSetupTime = 8; + hsram_read3.FSMC_BusTurnAroundDuration = 0; + hsram_read3.FSMC_CLKDivision = 0; + hsram_read3.FSMC_DataLatency = 0; + hsram_read3.FSMC_AccessMode = FSMC_AccessMode_A; + + hsram_write3.FSMC_AddressSetupTime = 0; + hsram_write3.FSMC_AddressHoldTime = 0; + hsram_write3.FSMC_DataSetupTime = 8; + hsram_write3.FSMC_BusTurnAroundDuration = 0; + hsram_write3.FSMC_CLKDivision = 0; + hsram_write3.FSMC_DataLatency = 0; + hsram_write3.FSMC_AccessMode = FSMC_AccessMode_A; + +#ifdef BSP_USING_FSMC_BANK1_NORSRAM3 + hsram3.FSMC_Bank = FSMC_Bank1_NORSRAM3; +#if BANK1_NORSRAM3_DATA_WIDTH == 8 + hsram3.FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_8b; +#elif BANK1_NORSRAM3_DATA_WIDTH == 16 + hsram3.FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_16b; +#else + hsram3.FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_32b; +#endif + FSMC_NORSRAMInit(&hsram3); + FSMC_NORSRAMCmd(FSMC_Bank1_NORSRAM3, ENABLE); + + ExtSramInitBoardMemory((void*)(FSMC_BANK1_NORSRAM3_START_ADDRESS), (void*)((FSMC_BANK1_NORSRAM3_START_ADDRESS + BANK1_NORSRAM3_SIZE)), 2); + +#endif + + return 0; +} \ No newline at end of file diff --git a/Ubiquitous/XiZi/board/stm32f407zgt6/third_party_driver/gpio/Kconfig b/Ubiquitous/XiZi/board/stm32f407zgt6/third_party_driver/gpio/Kconfig new file mode 100644 index 0000000..f284f60 --- /dev/null +++ b/Ubiquitous/XiZi/board/stm32f407zgt6/third_party_driver/gpio/Kconfig @@ -0,0 +1,12 @@ + +config PIN_BUS_NAME + string "pin bus name" + default "pin" + +config PIN_DRIVER_NAME + string "pin driver name" + default "pin_drv" + +config PIN_DEVICE_NAME + string "pin device name" + default "pin_dev" diff --git a/Ubiquitous/XiZi/board/stm32f407zgt6/third_party_driver/gpio/Makefile b/Ubiquitous/XiZi/board/stm32f407zgt6/third_party_driver/gpio/Makefile new file mode 100644 index 0000000..12e1dbe --- /dev/null +++ b/Ubiquitous/XiZi/board/stm32f407zgt6/third_party_driver/gpio/Makefile @@ -0,0 +1,3 @@ +SRC_FILES := connect_gpio.c hardware_gpio.c + +include $(KERNEL_ROOT)/compiler.mk diff --git a/Ubiquitous/XiZi/board/stm32f407zgt6/third_party_driver/uart/Kconfig b/Ubiquitous/XiZi/board/stm32f407zgt6/third_party_driver/uart/Kconfig new file mode 100644 index 0000000..79ce089 --- /dev/null +++ b/Ubiquitous/XiZi/board/stm32f407zgt6/third_party_driver/uart/Kconfig @@ -0,0 +1,74 @@ +menuconfig BSP_USING_USART1 + bool "Enable USART1" + default y + if BSP_USING_USART1 + config SERIAL_BUS_NAME_1 + string "serial bus 1 name" + default "usart1" + config SERIAL_DRV_NAME_1 + string "serial bus 1 driver name" + default "usart1_drv" + config SERIAL_1_DEVICE_NAME_0 + string "serial bus 1 device 0 name" + default "usart1_dev1" + endif + +menuconfig BSP_USING_USART2 + bool "Enable USART2" + default y + if BSP_USING_USART2 + config SERIAL_BUS_NAME_2 + string "serial bus 2 name" + default "usart2" + config SERIAL_DRV_NAME_2 + string "serial bus 2 driver name" + default "usart2_drv" + config SERIAL_2_DEVICE_NAME_0 + string "serial bus 2 device 0 name" + default "usart2_dev2" + endif + +menuconfig BSP_USING_USART3 + bool "Enable USART3" + default y + if BSP_USING_USART3 + config SERIAL_BUS_NAME_3 + string "serial bus 3 name" + default "usart3" + config SERIAL_DRV_NAME_3 + string "serial bus 3 driver name" + default "usart3_drv" + config SERIAL_3_DEVICE_NAME_0 + string "serial bus 3 device 0 name" + default "usart3_dev3" + endif + +menuconfig BSP_USING_UART4 + bool "Enable UART4" + default n + if BSP_USING_UART4 + config SERIAL_BUS_NAME_4 + string "serial bus 4 name" + default "uart4" + config SERIAL_DRV_NAME_4 + string "serial bus 4 driver name" + default "uart4_drv" + config SERIAL_4_DEVICE_NAME_0 + string "serial bus 4 device 0 name" + default "uart4_dev4" + endif + +menuconfig BSP_USING_UART5 + bool "Enable UART5" + default n + if BSP_USING_UART5 + config SERIAL_BUS_NAME_5 + string "serial bus 5 name" + default "uart5" + config SERIAL_DRV_NAME_5 + string "serial bus 5 driver name" + default "uart5_drv" + config SERIAL_5_DEVICE_NAME_0 + string "serial bus 5 device 0 name" + default "uart5_dev5" + endif diff --git a/Ubiquitous/XiZi/board/stm32f407zgt6/third_party_driver/uart/Makefile b/Ubiquitous/XiZi/board/stm32f407zgt6/third_party_driver/uart/Makefile new file mode 100644 index 0000000..b05646e --- /dev/null +++ b/Ubiquitous/XiZi/board/stm32f407zgt6/third_party_driver/uart/Makefile @@ -0,0 +1,3 @@ +SRC_FILES := connect_usart.c hardware_usart.c + +include $(KERNEL_ROOT)/compiler.mk diff --git a/Ubiquitous/XiZi/board/xidatong/Kconfig b/Ubiquitous/XiZi/board/xidatong/Kconfig new file mode 100644 index 0000000..9653b48 --- /dev/null +++ b/Ubiquitous/XiZi/board/xidatong/Kconfig @@ -0,0 +1,58 @@ +mainmenu "XiZi Project Configuration" + +config BSP_DIR + string + option env="BSP_ROOT" + default "." + +config KERNEL_DIR + string + option env="KERNEL_ROOT" + default "../.." + +config BOARD_CORTEX_M7_EVB + bool + select ARCH_ARM + default y + + +source "$KERNEL_DIR/arch/Kconfig" + +menu "xidatong feature" + source "$BSP_DIR/third_party_driver/Kconfig" + + menu "config default board resources" + menu "config board app name" + config BOARD_APP_NAME + string "config board app name" + default "/XiUOS_xidatong_app.bin" + endmenu + + menu "config board service table" + config SERVICE_TABLE_ADDRESS + hex "board service table address" + default 0x2007F0000 + endmenu + + endmenu + + config __STACKSIZE__ + int "stack size for interrupt" + default 4096 + + menu "config board peripheral" + config MOUNT_SDCARD + bool "mount sd card" + default n + endmenu + +endmenu + + +menu "Hardware feature" +source "$KERNEL_DIR/resources/Kconfig" +endmenu + +source "$KERNEL_DIR/Kconfig" + + diff --git a/Ubiquitous/XiZi/board/xidatong/Makefile b/Ubiquitous/XiZi/board/xidatong/Makefile new file mode 100644 index 0000000..c50f207 --- /dev/null +++ b/Ubiquitous/XiZi/board/xidatong/Makefile @@ -0,0 +1,5 @@ +SRC_DIR := third_party_driver xip + +SRC_FILES := board.c + +include $(KERNEL_ROOT)/compiler.mk \ No newline at end of file diff --git a/Ubiquitous/XiZi/board/xidatong/README.md b/Ubiquitous/XiZi/board/xidatong/README.md new file mode 100644 index 0000000..5eddfd9 --- /dev/null +++ b/Ubiquitous/XiZi/board/xidatong/README.md @@ -0,0 +1,172 @@ +# 从零开始构建矽璓工业物联操作系统：使用ARM架构的矽达通 + +# xidatong + +[XiUOS](http://xuos.io/) (X Industrial Ubiquitous Operating System) 矽璓XiUOS是一款面向智慧车间的工业物联网操作系统，主要由一个极简的微型实时操作系统内核和其上的工业物联框架构成，通过高效管理工业物联网设备、支撑工业物联应用，在生产车间内实现智能化的“感知环境、联网传输、知悉识别、控制调整”，促进以工业设备和工业控制系统为核心的人、机、物深度互联，帮助提升生产线的数字化和智能化水平。 + +## 1. 简介 + +| 硬件 | 描述 | +| -- | -- | +|芯片型号| MIMXRT1052DVL6A | +|架构| cortex-m7 | +|主频| 600MHz | +|片内SRAM| 512KB shared with TCM | +|外设支持| UART | + +XiUOS板级当前支持使用UART。 + +## 2. 开发环境搭建 + +### 推荐使用： + +**操作系统：** ubuntu18.04 [https://ubuntu.com/download/desktop](https://ubuntu.com/download/desktop) + +更新`ubuntu 18.04`源的方法:（根据自身情况而定，可以不更改） + +第一步:打开sources.list文件 + +```c +sudo vim /etc/apt/sources.list +``` + +第二步:将以下内容复制到sources.list文件 + +```c +deb http://mirrors.aliyun.com/ubuntu/ bionic main restricted universe multiverse +deb http://mirrors.aliyun.com/ubuntu/ bionic-security main restricted universe multiverse +deb http://mirrors.aliyun.com/ubuntu/ bionic-updates main restricted universe multiverse +deb http://mirrors.aliyun.com/ubuntu/ bionic-proposed main restricted universe multiverse +deb http://mirrors.aliyun.com/ubuntu/ bionic-backports main restricted universe multiverse +deb-src http://mirrors.aliyun.com/ubuntu/ bionic main restricted universe multiverse +deb-src http://mirrors.aliyun.com/ubuntu/ bionic-security main restricted universe multiverse +deb-src http://mirrors.aliyun.com/ubuntu/ bionic-updates main restricted universe multiverse +deb-src http://mirrors.aliyun.com/ubuntu/ bionic-proposed main restricted universe multiverse +deb-src http://mirrors.aliyun.com/ubuntu/ bionic-backports main restricted universe multiverse +``` + +第三步:更新源和系统软件 + +```c +sudo apt-get update +sudo apt-get upgrade +``` + +**开发工具推荐使用 VSCode ，VScode下载地址为：** VSCode [https://code.visualstudio.com/](https://code.visualstudio.com/)，推荐下载地址为 [http://vscode.cdn.azure.cn/stable/3c4e3df9e89829dce27b7b5c24508306b151f30d/code_1.55.2-1618307277_amd64.deb](http://vscode.cdn.azure.cn/stable/3c4e3df9e89829dce27b7b5c24508306b151f30d/code_1.55.2-1618307277_amd64.deb) + +### 依赖包安装： + +``` +$ sudo apt install build-essential pkg-config git +$ sudo apt install gcc make libncurses5-dev openssl libssl-dev bison flex libelf-dev autoconf libtool gperf libc6-dev +``` + +**XiUOS操作系统源码下载：** XiUOS [https://www.gitlink.org.cn/xuos/xiuos](https://www.gitlink.org.cn/xuos/xiuos) + +新建一个空文件夹并进入文件夹中，并下载源码，具体命令如下： + +```c +mkdir test && cd test +git clone https://gitlink.org.cn/xuos/xiuos.git +``` + +1、打开XiUOS源码文件包可以看到以下目录： +| 名称 | 说明 | +| -- | -- | +| APP_Framework | 应用代码 | +| Ubiquitous | 板级支持包,支持NuttX、RT-Thread和XiZi内核 | + +2、打开XiZi内核源码文件包可以看到以下目录： +| 名称 | 说明 | +| -- | -- | +| arch | 架构代码 | +| board | 板级支持包 | +| fs | 文件系统 | +| kernel | 内核源码 | +| lib | 第三方库源码 | +| resources | 驱动文件 | +| tool | 系统工具 | + +使用VScode打开代码，具体操作步骤为：在源码文件夹下打开系统终端，输入`code .`即可打开VScode开发环境，如下图所示： + +
+ +
+ +### 裁减配置工具的下载 + +裁减配置工具： + +**工具地址：** kconfig-frontends [https://www.gitlink.org.cn/xuos/kconfig-frontends](https://www.gitlink.org.cn/xuos/kconfig-frontends)，下载与安装的具体命令如下： + +```c +mkdir kfrontends && cd kfrontends +git clone https://gitlink.org.cn/xuos/kconfig-frontends.git +``` + +下载源码后按以下步骤执行软件安装： + +```c +cd kconfig-frontends +./xs_build.sh +``` + +### 编译工具链： + +ARM： arm-none-eabi(`gcc version 6.3.1`)，默认安装到Ubuntu的/usr/bin/arm-none-eabi-，使用如下命令行下载和安装。 + +```shell +$ sudo apt install gcc-arm-none-eabi +``` + +## 编译说明 + +### 编辑环境：`Ubuntu18.04` + +### 编译工具链：`arm-none-eabi-gcc` +使用`VScode`打开工程的方法有多种，本文介绍一种快捷键，在项目目录下将`code .`输入linux系统命令终端即可打开目标项目 + + +编译步骤： + +1.在VScode命令终端中执行以下命令，生成配置文件 + +```c +cd ./Ubiquitous/XiZi +make BOARD=xidatong distclean +make BOARD=xidatong menuconfig +``` + +2.在menuconfig界面配置需要关闭和开启的功能，按回车键进入下级菜单，按Y键选中需要开启的功能，按N键选中需要关闭的功能，配置结束后保存并退出（本例旨在演示简单的输出例程，所以没有需要配置的选项，双击快捷键ESC退出配置） + +![menuconfig](./img/menuconfig.png) + +退出时选择`yes`保存上面所配置的内容，如下图所示： + +![menuconfig1](./img/menuconfig1.png) + +3.继续执行以下命令，进行编译 + +``` +make BOARD=xidatong +``` + +4.如果编译正确无误，会产生XiZi_xidatong.elf、XiZi_xidatong.bin文件。 + +## 3. 烧写及运行 + +### 3.1 烧写 +1、烧写工具：NXP MCU Boot Utility，可参考[https://github.com/JayHeng/NXP-MCUBootUtility](https://github.com/JayHeng/NXP-MCUBootUtility) + +2、xidatong开发板支持UART串口烧写程序，打开NXP MCU Boot Utility后，选择好芯片类型为i.MXRT105x，开发板上电，使用串口转USB线将开发板和PC连接，拨码开关设置为1 on 2 on 3 off 4 off，重新上电，选择对应的COM口和波特率（需关闭串口终端连接，确保该COM口空闲，否则会导致Utility工具连接失败），连接成功后，点击reconnect，等待NXP MCU Boot Utility中红色显示变成蓝色显示，则表示已正确识别并连接到了开发板。如下图所示： +![NXPBootUtility_1](./img/NXPBootUtility_1.png) + +3、同时需要匹配xidatong开发板所使用的Flash型号，点击Boot Device Configuration，在Use Typical Device中选择Winbond_W25QxxxJV，然后点击ok。如下图所示： +![flashconfig](./img/flashconfig.png) + +4、选择编译生成的XiZi_xidatong.elf或bin文件路径，按照图示步骤，将文件烧写至Flash中（link.lds中已构造Flash Bootable image，如有修改Flash相关配置需求，可修改/xip目录内相关文件，无需NXPBootUtility再次构造），若烧写无误，则下列绿色进度条会执行到底。如下图所示： +![NXPBootUtility_2](./img/NXPBootUtility_2.png) +### 3.2 运行结果 + +按照3.1烧写步骤执行后，将拨码开关设置为1 off 2 off 3 off 4 off，重新上电后，重新打开该COM口串口终端，若程序正常，则串口终端上会显示启动信息打印输出。如下图所示： +![terminal](./img/terminal.png) diff --git a/Ubiquitous/XiZi/board/xidatong/config.mk b/Ubiquitous/XiZi/board/xidatong/config.mk new file mode 100644 index 0000000..53f596d --- /dev/null +++ b/Ubiquitous/XiZi/board/xidatong/config.mk @@ -0,0 +1,22 @@ +export CROSS_COMPILE ?=/usr/bin/arm-none-eabi- + +export CFLAGS := -mcpu=cortex-m7 -mthumb -ffunction-sections -fdata-sections -Dgcc -O0 -gdwarf-2 -g -fgnu89-inline -Wa,-mimplicit-it=thumb +export AFLAGS := -c -mcpu=cortex-m7 -mthumb -ffunction-sections -fdata-sections -x assembler-with-cpp -Wa,-mimplicit-it=thumb -gdwarf-2 + +### if use USB function, use special lds file because USB uses ITCM + +ifeq ($(CONFIG_BSP_USING_USB),y) +export LFLAGS := -mcpu=cortex-m7 -mthumb -ffunction-sections -fdata-sections -Wl,--gc-sections,-Map=XiZi_xidatong.map,-cref,-u,Reset_Handler -T $(BSP_ROOT)/link-usb.lds +else +export LFLAGS := -mcpu=cortex-m7 -mthumb -ffunction-sections -fdata-sections -Wl,--gc-sections,-Map=XiZi_xidatong.map,-cref,-u,Reset_Handler -T $(BSP_ROOT)/link.lds +endif + +export CXXFLAGS := -mcpu=cortex-m7 -mthumb -ffunction-sections -fdata-sections -Dgcc -O0 -gdwarf-2 -g + +export APPLFLAGS := -mcpu=cortex-m7 -mthumb -ffunction-sections -fdata-sections -Wl,--gc-sections,-Map=XiZi_app.map,-cref,-u, -T $(BSP_ROOT)/link_userspace.lds + + +export DEFINES := -DHAVE_CCONFIG_H -DCPU_MIMXRT1052CVL5B -DSKIP_SYSCLK_INIT -DEVK_MCIMXRM -DFSL_SDK_ENABLE_DRIVER_CACHE_CONTROL=1 -DXIP_EXTERNAL_FLASH=1 -D__STARTUP_INITIALIZE_NONCACHEDATA -D__STARTUP_CLEAR_BSS + +export ARCH = arm +export MCU = cortex-m7 diff --git a/Ubiquitous/XiZi/board/xidatong/img/NXPBootUtility_1.png b/Ubiquitous/XiZi/board/xidatong/img/NXPBootUtility_1.png new file mode 100644 index 0000000..939f60f Binary files /dev/null and b/Ubiquitous/XiZi/board/xidatong/img/NXPBootUtility_1.png differ diff --git a/Ubiquitous/XiZi/board/xidatong/img/NXPBootUtility_2.png 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b/Ubiquitous/XiZi/board/xidatong/img/terminal.png new file mode 100644 index 0000000..75d214c Binary files /dev/null and b/Ubiquitous/XiZi/board/xidatong/img/terminal.png differ diff --git a/Ubiquitous/XiZi/board/xidatong/img/vscode.jpg b/Ubiquitous/XiZi/board/xidatong/img/vscode.jpg new file mode 100644 index 0000000..b9bacff Binary files /dev/null and b/Ubiquitous/XiZi/board/xidatong/img/vscode.jpg differ diff --git a/Ubiquitous/XiZi/board/xidatong/include/board.h b/Ubiquitous/XiZi/board/xidatong/include/board.h new file mode 100755 index 0000000..9e9e12d --- /dev/null +++ b/Ubiquitous/XiZi/board/xidatong/include/board.h @@ -0,0 +1,177 @@ +/* + * Copyright 2017-2018 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +/** +* @file board.h +* @brief define imxrt1052-board init configure and start-up function +* @version 1.0 +* @author AIIT XUOS Lab +* @date 2021-05-28 +*/ + +/************************************************* +File name: board.h +Description: define imxrt1052-board board init function and struct +Others: +History: +1. Date: 2021-05-28 +Author: AIIT XUOS Lab +Modification: +1. define imxrt-board InitBoardHardware +2. define imxrt-board heap struct +*************************************************/ + +#ifndef __BOARD_H__ +#define __BOARD_H__ + +#include "fsl_common.h" +#include "fsl_gpio.h" +#include "fsl_clock.h" +#include "fsl_enet.h" +#include "clock_config.h" +#include +#include + +extern int heap_start; +extern int heap_end; +#define HEAP_BEGIN (&heap_start) +#define HEAP_END (&heap_end) + +#define HEAP_SIZE ((uint32_t)HEAP_END - (uint32_t)HEAP_BEGIN) + +void InitBoardHardware(void); + +/******************************************************************************* + * Definitions + ******************************************************************************/ +/*! @brief The board name */ +#define BOARD_NAME "IMXRT1050" + +#define NVIC_PRIORITYGROUP_0 0x00000007U /*!< 0 bits for pre-emption priority + 4 bits for subpriority */ +#define NVIC_PRIORITYGROUP_1 0x00000006U /*!< 1 bits for pre-emption priority + 3 bits for subpriority */ +#define NVIC_PRIORITYGROUP_2 0x00000005U /*!< 2 bits for pre-emption priority + 2 bits for subpriority */ +#define NVIC_PRIORITYGROUP_3 0x00000004U /*!< 3 bits for pre-emption priority + 1 bits for subpriority */ +#define NVIC_PRIORITYGROUP_4 0x00000003U /*!< 4 bits for pre-emption priority*/ + +/*! @brief The ENET PHY address. */ +#define BOARD_ENET0_PHY_ADDRESS (0x0U) /* Phy address of enet port 0. */ + +/* USB PHY condfiguration */ +#define BOARD_USB_PHY_D_CAL (0x0CU) +#define BOARD_USB_PHY_TXCAL45DP (0x06U) +#define BOARD_USB_PHY_TXCAL45DM (0x06U) + +#define BOARD_ARDUINO_INT_IRQ (GPIO1_INT3_IRQn) +#define BOARD_ARDUINO_I2C_IRQ (LPI2C1_IRQn) +#define BOARD_ARDUINO_I2C_INDEX (1) +#define BOARD_USDHC1_BASEADDR USDHC1 +#define BOARD_USDHC2_BASEADDR USDHC2 +#define BOARD_USDHC_CD_GPIO_BASE GPIO2 +#define BOARD_USDHC_CD_GPIO_PIN 28 +#define BOARD_USDHC_CD_PORT_IRQ GPIO2_Combined_16_31_IRQn +#define BOARD_USDHC_CD_PORT_IRQ_HANDLER GPIO2_Combined_16_31_IRQHandler + +#define BOARD_USDHC_CD_STATUS() (GPIO_PinRead(BOARD_USDHC_CD_GPIO_BASE, BOARD_USDHC_CD_GPIO_PIN)) + +#define BOARD_USDHC_CD_INTERRUPT_STATUS() (GPIO_PortGetInterruptFlags(BOARD_USDHC_CD_GPIO_BASE)) +#define BOARD_USDHC_CD_CLEAR_INTERRUPT(flag) (GPIO_PortClearInterruptFlags(BOARD_USDHC_CD_GPIO_BASE, flag)) + +#define BOARD_USDHC_CD_GPIO_INIT() \ + { \ + gpio_pin_config_t sw_config = { \ + kGPIO_DigitalInput, \ + 0, \ + kGPIO_IntRisingOrFallingEdge, \ + }; \ + GPIO_PinInit(BOARD_USDHC_CD_GPIO_BASE, BOARD_USDHC_CD_GPIO_PIN, &sw_config); \ + GPIO_PortEnableInterrupts(BOARD_USDHC_CD_GPIO_BASE, 1U << BOARD_USDHC_CD_GPIO_PIN); \ + GPIO_PortClearInterruptFlags(BOARD_USDHC_CD_GPIO_BASE, ~0); \ + } +#define BOARD_HAS_SDCARD (1U) +#define BOARD_SD_POWER_RESET_GPIO (GPIO1) +#define BOARD_SD_POWER_RESET_GPIO_PIN (5U) + +#define BOARD_USDHC_CARD_INSERT_CD_LEVEL (0U) + +#define BOARD_USDHC_MMCCARD_POWER_CONTROL(state) + +#define BOARD_USDHC_MMCCARD_POWER_CONTROL_INIT() \ + { \ + gpio_pin_config_t sw_config = { \ + kGPIO_DigitalOutput, \ + 0, \ + kGPIO_NoIntmode, \ + }; \ + GPIO_PinInit(BOARD_SD_POWER_RESET_GPIO, BOARD_SD_POWER_RESET_GPIO_PIN, &sw_config); \ + GPIO_PinWrite(BOARD_SD_POWER_RESET_GPIO, BOARD_SD_POWER_RESET_GPIO_PIN, true); \ + } + +#define BOARD_USDHC_SDCARD_POWER_CONTROL_INIT() \ + { \ + gpio_pin_config_t sw_config = { \ + kGPIO_DigitalOutput, \ + 0, \ + kGPIO_NoIntmode, \ + }; \ + GPIO_PinInit(BOARD_SD_POWER_RESET_GPIO, BOARD_SD_POWER_RESET_GPIO_PIN, &sw_config); \ + } + +#define BOARD_USDHC_SDCARD_POWER_CONTROL(state) \ + (GPIO_PinWrite(BOARD_SD_POWER_RESET_GPIO, BOARD_SD_POWER_RESET_GPIO_PIN, state)) + +#define BOARD_USDHC1_CLK_FREQ (CLOCK_GetSysPfdFreq(kCLOCK_Pfd0) / (CLOCK_GetDiv(kCLOCK_Usdhc1Div) + 1U)) +#define BOARD_USDHC2_CLK_FREQ (CLOCK_GetSysPfdFreq(kCLOCK_Pfd0) / (CLOCK_GetDiv(kCLOCK_Usdhc2Div) + 1U)) + +#define BOARD_SD_HOST_BASEADDR BOARD_USDHC1_BASEADDR +#define BOARD_SD_HOST_CLK_FREQ BOARD_USDHC1_CLK_FREQ +#define BOARD_SD_HOST_IRQ USDHC1_IRQn + +#define BOARD_MMC_HOST_BASEADDR BOARD_USDHC2_BASEADDR +#define BOARD_MMC_HOST_CLK_FREQ BOARD_USDHC2_CLK_FREQ +#define BOARD_MMC_HOST_IRQ USDHC2_IRQn +#define BOARD_MMC_VCCQ_SUPPLY kMMC_VoltageWindow170to195 +#define BOARD_MMC_VCC_SUPPLY kMMC_VoltageWindows270to360 +/* we are using the BB SD socket to DEMO the MMC example,but the + * SD socket provide 4bit bus only, so we define this macro to avoid + * 8bit data bus test + */ +#define BOARD_MMC_SUPPORT_8BIT_BUS (1U) + +#define BOARD_SD_HOST_SUPPORT_SDR104_FREQ (200000000U) +#define BOARD_SD_HOST_SUPPORT_HS200_FREQ (180000000U) + +/* @Brief Board accelerator sensor configuration */ +#define BOARD_ACCEL_I2C_BASEADDR LPI2C1 +/* Select USB1 PLL (480 MHz) as LPI2C's clock source */ +#define BOARD_ACCEL_I2C_CLOCK_SOURCE_SELECT (0U) +/* Clock divider for LPI2C clock source */ +#define BOARD_ACCEL_I2C_CLOCK_SOURCE_DIVIDER (5U) +#define BOARD_ACCEL_I2C_CLOCK_FREQ (CLOCK_GetFreq(kCLOCK_Usb1PllClk) / 8 / (BOARD_ACCEL_I2C_CLOCK_SOURCE_DIVIDER + 1U)) + +#define BOARD_CODEC_I2C_BASEADDR LPI2C1 +#define BOARD_CODEC_I2C_INSTANCE 1U +#define BOARD_CODEC_I2C_CLOCK_SOURCE_SELECT (0U) +#define BOARD_CODEC_I2C_CLOCK_SOURCE_DIVIDER (5U) +#define BOARD_CODEC_I2C_CLOCK_FREQ (10000000U) + +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus */ + +void BOARD_ConfigMPU(void); +void BOARD_SD_Pin_Config(uint32_t speed, uint32_t strength); +void BOARD_MMC_Pin_Config(uint32_t speed, uint32_t strength); + +#if defined(__cplusplus) +} +#endif /* __cplusplus */ + +#endif /* _BOARD_H_ */ diff --git a/Ubiquitous/XiZi/board/xidatong/include/clock_config.h b/Ubiquitous/XiZi/board/xidatong/include/clock_config.h new file mode 100644 index 0000000..96d9691 --- /dev/null +++ b/Ubiquitous/XiZi/board/xidatong/include/clock_config.h @@ -0,0 +1,81 @@ +/* + * Copyright 2017-2019 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +/** +* @file clock_config.h +* @brief define imxrt1052-board clock configure +* @version 1.0 +* @author AIIT XUOS Lab +* @date 2021-05-29 +*/ + +#ifndef _CLOCK_CONFIG_H_ +#define _CLOCK_CONFIG_H_ + +#include "fsl_common.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ +#define BOARD_XTAL0_CLK_HZ 24000000U /*!< Board xtal0 frequency in Hz */ + +#define BOARD_XTAL32K_CLK_HZ 32768U /*!< Board xtal32k frequency in Hz */ +/******************************************************************************* + ************************ BOARD_InitBootClocks function ************************ + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus*/ + +/*! + * @brief This function executes default configuration of clocks. + * + */ +void BOARD_InitBootClocks(void); + +#if defined(__cplusplus) +} +#endif /* __cplusplus*/ + +/******************************************************************************* + ********************** Configuration BOARD_BootClockRUN *********************** + ******************************************************************************/ +/******************************************************************************* + * Definitions for BOARD_BootClockRUN configuration + ******************************************************************************/ +#define BOARD_BOOTCLOCKRUN_CORE_CLOCK 600000000U /*!< Core clock frequency: 600000000Hz */ + +/*! @brief Arm PLL set for BOARD_BootClockRUN configuration. + */ +extern const clock_arm_pll_config_t armPllConfig_BOARD_BootClockRUN; +/*! @brief Usb1 PLL set for BOARD_BootClockRUN configuration. + */ +extern const clock_usb_pll_config_t usb1PllConfig_BOARD_BootClockRUN; +/*! @brief Sys PLL for BOARD_BootClockRUN configuration. + */ +extern const clock_sys_pll_config_t sysPllConfig_BOARD_BootClockRUN; + +/******************************************************************************* + * API for BOARD_BootClockRUN configuration + ******************************************************************************/ +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus*/ + +/*! + * @brief This function executes configuration of clocks. + * + */ +void BOARD_BootClockRUN(void); + +#if defined(__cplusplus) +} +#endif /* __cplusplus*/ + +#endif /* _CLOCK_CONFIG_H_ */ + diff --git a/Ubiquitous/XiZi/board/xidatong/include/pin_mux.h b/Ubiquitous/XiZi/board/xidatong/include/pin_mux.h new file mode 100755 index 0000000..c7e6746 --- /dev/null +++ b/Ubiquitous/XiZi/board/xidatong/include/pin_mux.h @@ -0,0 +1,90 @@ +/* + * Copyright 2017-2019 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +/** +* @file pin_mux.h +* @brief define imxrt1052-board pin configure +* @version 1.0 +* @author AIIT XUOS Lab +* @date 2021-05-29 +*/ + +/*********************************************************************************************************************** + * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file + * will be overwritten if the respective MCUXpresso Config Tools is used to update this file. + **********************************************************************************************************************/ + +#ifndef _PIN_MUX_H_ +#define _PIN_MUX_H_ + +/*********************************************************************************************************************** + * Definitions + **********************************************************************************************************************/ + +/*! @brief Direction type */ +typedef enum _pin_mux_direction +{ + kPIN_MUX_DirectionInput = 0U, /* Input direction */ + kPIN_MUX_DirectionOutput = 1U, /* Output direction */ + kPIN_MUX_DirectionInputOrOutput = 2U /* Input or output direction */ +} pin_mux_direction_t; + +/*! + * @addtogroup pin_mux + * @{ + */ + +/*********************************************************************************************************************** + * API + **********************************************************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @brief Calls initialization functions. + * + */ +void BOARD_InitBootPins(void); + +/* GPIO_AD_B0_13 (coord L14), UART1_RXD */ +#define BOARD_INITPINS_UART1_RXD_PERIPHERAL LPUART1 /*!< Device name: LPUART1 */ +#define BOARD_INITPINS_UART1_RXD_SIGNAL RX /*!< LPUART1 signal: RX */ + +/* GPIO_AD_B0_12 (coord K14), UART1_TXD */ +#define BOARD_INITPINS_UART1_TXD_PERIPHERAL LPUART1 /*!< Device name: LPUART1 */ +#define BOARD_INITPINS_UART1_TXD_SIGNAL TX /*!< LPUART1 signal: TX */ + +/* GPIO_AD_B0_09 (coord F14), BSP_LED */ +#define BOARD_INITPINS_BSP_LED_GPIO GPIO1 /*!< GPIO device name: GPIO1 */ +#define BOARD_INITPINS_BSP_LED_PORT GPIO1 /*!< PORT device name: GPIO1 */ +#define BOARD_INITPINS_BSP_LED_PIN 9U /*!< GPIO1 pin index: 9 */ + + +/*! + * @brief Configures pin routing and optionally pin electrical features. + * + */ +void BOARD_InitPins(void); +void BOARD_InitI2C1Pins(void); +void BOARD_InitSPIPins(void); +void BOARD_InitUartPins(void); +void BOARD_InitCh438Pins(void); + +#if defined(__cplusplus) +} +#endif + +/*! + * @} + */ +#endif /* _PIN_MUX_H_ */ + +/*********************************************************************************************************************** + * EOF + **********************************************************************************************************************/ diff --git a/Ubiquitous/XiZi/board/xidatong/link-usb.lds b/Ubiquitous/XiZi/board/xidatong/link-usb.lds new file mode 100755 index 0000000..fc005fd --- /dev/null +++ b/Ubiquitous/XiZi/board/xidatong/link-usb.lds @@ -0,0 +1,262 @@ +/* +** ################################################################### +** Processors: MIMXRT1052CVJ5B +** MIMXRT1052CVL5B +** MIMXRT1052DVJ6B +** MIMXRT1052DVL6B +** +** Compiler: GNU C Compiler +** Reference manual: IMXRT1050RM Rev.1, 03/2018 +** Version: rev. 1.0, 2018-09-21 +** Build: b180921 +** +** Abstract: +** Linker file for the GNU C Compiler +** +** Copyright 2016 Freescale Semiconductor, Inc. +** Copyright 2016-2018 NXP +** All rights reserved. +** +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** ################################################################### +*/ + + +/** +* @file link.lds +* @brief xidatong Linker script +* @version 1.0 +* @author AIIT XUOS Lab +* @date 2021-05-28 +*/ + +/************************************************* +File name: link.lds +Description: xidatong Linker script +Others: take MIMXRT1052xxxxx_flexspi_nor.ld for references +History: +1. Date: 2021-05-28 +Author: AIIT XUOS Lab +Modification: +1. add shell cmd table and g_service_table +*************************************************/ + +/* Entry Point */ +ENTRY(Reset_Handler) + +HEAP_SIZE = DEFINED(__heap_size__) ? __heap_size__ : 0x0400; +STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x1000; + +/* Specify the memory areas */ +MEMORY +{ + m_boot_data (RX) : ORIGIN = 0x60000000, LENGTH = 0x00001000 + m_image_vertor_table (RX) : ORIGIN = 0x60001000, LENGTH = 0x00001000 + + m_interrupts (RX) : ORIGIN = 0x60002000, LENGTH = 0x00000400 + m_text (RX) : ORIGIN = 0x60002400, LENGTH = 0x03FFDC00 + m_data (RW) : ORIGIN = 0x20000000, LENGTH = 0x00020000 + m_data2 (RW) : ORIGIN = 0x20200000, LENGTH = 0x00060000 +} + +/* Define output sections */ +SECTIONS +{ + .boot_data : + { + KEEP(*(.boot_hdr.conf)) + } > m_boot_data + + .image_vertor_table : + { + KEEP(*(.boot_hdr.ivt)) + KEEP(*(.boot_hdr.boot_data)) + KEEP(*(.boot_hdr.dcd_data)) + } > m_image_vertor_table + + /* The startup code goes first into internal RAM */ + .interrupts : + { + __VECTOR_TABLE = .; + . = ALIGN(4); + KEEP(*(.isr_vector)) /* Startup code */ + . = ALIGN(4); + } > m_interrupts + + __VECTOR_RAM = __VECTOR_TABLE; + __RAM_VECTOR_TABLE_SIZE_BYTES = 0x0; + + /* The program code and other data goes into internal RAM */ + .text : + { + . = ALIGN(4); + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + KEEP (*(.init)) + KEEP (*(.fini)) + . = ALIGN(4); + + + /* section information for shell */ + . = ALIGN(4); + _shell_command_start = .; + KEEP (*(shellCommand)) + _shell_command_end = .; + . = ALIGN(4); + + __isrtbl_idx_start = .; + KEEP(*(.isrtbl.idx)) + __isrtbl_start = .; + KEEP(*(.isrtbl)) + __isrtbl_end = .; + . = ALIGN(4); + + PROVIDE(g_service_table_start = ABSOLUTE(.)); + KEEP(*(.g_service_table)) + PROVIDE(g_service_table_end = ABSOLUTE(.)); + } > m_text + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > m_text + + .ARM : + { + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + } > m_text + + .ctors : + { + __CTOR_LIST__ = .; + /* gcc uses crtbegin.o to find the start of + the constructors, so we make sure it is + first. Because this is a wildcard, it + doesn't matter if the user does not + actually link against crtbegin.o; the + linker won't look for a file to match a + wildcard. The wildcard also means that it + doesn't matter which directory crtbegin.o + is in. */ + KEEP (*crtbegin.o(.ctors)) + KEEP (*crtbegin?.o(.ctors)) + /* We don't want to include the .ctor section from + from the crtend.o file until after the sorted ctors. + The .ctor section from the crtend file contains the + end of ctors marker and it must be last */ + KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*(.ctors)) + __CTOR_END__ = .; + } > m_text + + .dtors : + { + __DTOR_LIST__ = .; + KEEP (*crtbegin.o(.dtors)) + KEEP (*crtbegin?.o(.dtors)) + KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*(.dtors)) + __DTOR_END__ = .; + } > m_text + + .preinit_array : + { + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + } > m_text + + .init_array : + { + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + } > m_text + + .fini_array : + { + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array*)) + PROVIDE_HIDDEN (__fini_array_end = .); + } > m_text + + __etext = .; /* define a global symbol at end of code */ + __DATA_ROM = .; /* Symbol is used by startup for data initialization */ + + .data : AT(__DATA_ROM) + { + . = ALIGN(4); + __DATA_RAM = .; + __data_start__ = .; /* create a global symbol at data start */ + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + KEEP(*(.jcr*)) + . = ALIGN(4); + __data_end__ = .; /* define a global symbol at data end */ + } > m_data + + __NDATA_ROM = __DATA_ROM + (__data_end__ - __data_start__); + .ncache.init : AT(__NDATA_ROM) + { + __noncachedata_start__ = .; /* create a global symbol at ncache data start */ + *(NonCacheable.init) + . = ALIGN(4); + __noncachedata_init_end__ = .; /* create a global symbol at initialized ncache data end */ + } > m_data + . = __noncachedata_init_end__; + .ncache : + { + *(NonCacheable) + . = ALIGN(4); + __noncachedata_end__ = .; /* define a global symbol at ncache data end */ + } > m_data + + __DATA_END = __NDATA_ROM + (__noncachedata_init_end__ - __noncachedata_start__); + text_end = ORIGIN(m_text) + LENGTH(m_text); + ASSERT(__DATA_END <= text_end, "region m_text overflowed with text and data") + + /* Uninitialized data section */ + .bss : + { + /* This is used by the startup in order to initialize the .bss section */ + . = ALIGN(4); + __START_BSS = .; + __bss_start__ = .; + *(.bss) + *(.bss*) + *(COMMON) + . = ALIGN(4); + __bss_end__ = .; + __END_BSS = .; + } > m_data + + .stack : + { + . = ALIGN(8); + stack_start = .; + . += STACK_SIZE; + stack_end = .; + __StackTop = .; + heap_start = .; + } > m_data + + PROVIDE(heap_end = ORIGIN(m_data) + LENGTH(m_data)); + + .ARM.attributes 0 : { *(.ARM.attributes) } +} + diff --git a/Ubiquitous/XiZi/board/xidatong/link.lds b/Ubiquitous/XiZi/board/xidatong/link.lds new file mode 100644 index 0000000..38d111b --- /dev/null +++ b/Ubiquitous/XiZi/board/xidatong/link.lds @@ -0,0 +1,262 @@ +/* +** ################################################################### +** Processors: MIMXRT1052CVJ5B +** MIMXRT1052CVL5B +** MIMXRT1052DVJ6B +** MIMXRT1052DVL6B +** +** Compiler: GNU C Compiler +** Reference manual: IMXRT1050RM Rev.1, 03/2018 +** Version: rev. 1.0, 2018-09-21 +** Build: b180921 +** +** Abstract: +** Linker file for the GNU C Compiler +** +** Copyright 2016 Freescale Semiconductor, Inc. +** Copyright 2016-2018 NXP +** All rights reserved. +** +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** ################################################################### +*/ + + +/** +* @file link.lds +* @brief xidatong Linker script +* @version 1.0 +* @author AIIT XUOS Lab +* @date 2021-05-28 +*/ + +/************************************************* +File name: link.lds +Description: xidatong Linker script +Others: take MIMXRT1052xxxxx_flexspi_nor.ld for references +History: +1. Date: 2021-05-28 +Author: AIIT XUOS Lab +Modification: +1. add shell cmd table and g_service_table +*************************************************/ + +/* Entry Point */ +ENTRY(Reset_Handler) + +HEAP_SIZE = DEFINED(__heap_size__) ? __heap_size__ : 0x0400; +STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x1000; + +/* Specify the memory areas */ +MEMORY +{ + m_boot_data (RX) : ORIGIN = 0x60000000, LENGTH = 0x00001000 + m_image_vertor_table (RX) : ORIGIN = 0x60001000, LENGTH = 0x00001000 + + m_interrupts (RX) : ORIGIN = 0x60002000, LENGTH = 0x00000400 + m_text (RX) : ORIGIN = 0x60002400, LENGTH = 0x03FFDC00 + m_data (RW) : ORIGIN = 0x20000000, LENGTH = 0x00020000 + m_data2 (RW) : ORIGIN = 0x20200000, LENGTH = 0x00060000 +} + +/* Define output sections */ +SECTIONS +{ + .boot_data : + { + KEEP(*(.boot_hdr.conf)) + } > m_boot_data + + .image_vertor_table : + { + KEEP(*(.boot_hdr.ivt)) + KEEP(*(.boot_hdr.boot_data)) + KEEP(*(.boot_hdr.dcd_data)) + } > m_image_vertor_table + + /* The startup code goes first into internal RAM */ + .interrupts : + { + __VECTOR_TABLE = .; + . = ALIGN(4); + KEEP(*(.isr_vector)) /* Startup code */ + . = ALIGN(4); + } > m_interrupts + + __VECTOR_RAM = __VECTOR_TABLE; + __RAM_VECTOR_TABLE_SIZE_BYTES = 0x0; + + /* The program code and other data goes into internal RAM */ + .text : + { + . = ALIGN(4); + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + KEEP (*(.init)) + KEEP (*(.fini)) + . = ALIGN(4); + + + /* section information for shell */ + . = ALIGN(4); + _shell_command_start = .; + KEEP (*(shellCommand)) + _shell_command_end = .; + . = ALIGN(4); + + __isrtbl_idx_start = .; + KEEP(*(.isrtbl.idx)) + __isrtbl_start = .; + KEEP(*(.isrtbl)) + __isrtbl_end = .; + . = ALIGN(4); + + PROVIDE(g_service_table_start = ABSOLUTE(.)); + KEEP(*(.g_service_table)) + PROVIDE(g_service_table_end = ABSOLUTE(.)); + } > m_text + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > m_text + + .ARM : + { + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + } > m_text + + .ctors : + { + __CTOR_LIST__ = .; + /* gcc uses crtbegin.o to find the start of + the constructors, so we make sure it is + first. Because this is a wildcard, it + doesn't matter if the user does not + actually link against crtbegin.o; the + linker won't look for a file to match a + wildcard. The wildcard also means that it + doesn't matter which directory crtbegin.o + is in. */ + KEEP (*crtbegin.o(.ctors)) + KEEP (*crtbegin?.o(.ctors)) + /* We don't want to include the .ctor section from + from the crtend.o file until after the sorted ctors. + The .ctor section from the crtend file contains the + end of ctors marker and it must be last */ + KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*(.ctors)) + __CTOR_END__ = .; + } > m_text + + .dtors : + { + __DTOR_LIST__ = .; + KEEP (*crtbegin.o(.dtors)) + KEEP (*crtbegin?.o(.dtors)) + KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*(.dtors)) + __DTOR_END__ = .; + } > m_text + + .preinit_array : + { + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + } > m_text + + .init_array : + { + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + } > m_text + + .fini_array : + { + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array*)) + PROVIDE_HIDDEN (__fini_array_end = .); + } > m_text + + __etext = .; /* define a global symbol at end of code */ + __DATA_ROM = .; /* Symbol is used by startup for data initialization */ + + .data : AT(__DATA_ROM) + { + . = ALIGN(4); + __DATA_RAM = .; + __data_start__ = .; /* create a global symbol at data start */ + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + KEEP(*(.jcr*)) + . = ALIGN(4); + __data_end__ = .; /* define a global symbol at data end */ + } > m_data + + __NDATA_ROM = __DATA_ROM + (__data_end__ - __data_start__); + .ncache.init : AT(__NDATA_ROM) + { + __noncachedata_start__ = .; /* create a global symbol at ncache data start */ + *(NonCacheable.init) + . = ALIGN(4); + __noncachedata_init_end__ = .; /* create a global symbol at initialized ncache data end */ + } > m_data + . = __noncachedata_init_end__; + .ncache : + { + *(NonCacheable) + . = ALIGN(4); + __noncachedata_end__ = .; /* define a global symbol at ncache data end */ + } > m_data + + __DATA_END = __NDATA_ROM + (__noncachedata_init_end__ - __noncachedata_start__); + text_end = ORIGIN(m_text) + LENGTH(m_text); + ASSERT(__DATA_END <= text_end, "region m_text overflowed with text and data") + + /* Uninitialized data section */ + .bss : + { + /* This is used by the startup in order to initialize the .bss section */ + . = ALIGN(4); + __START_BSS = .; + __bss_start__ = .; + *(.bss) + *(.bss*) + *(COMMON) + . = ALIGN(4); + __bss_end__ = .; + __END_BSS = .; + } > m_data + + .stack : + { + . = ALIGN(8); + stack_start = .; + . += STACK_SIZE; + stack_end = .; + __StackTop = .; + heap_start = .; + } > m_data2 + + PROVIDE(heap_end = ORIGIN(m_data2) + LENGTH(m_data2)); + + .ARM.attributes 0 : { *(.ARM.attributes) } +} + diff --git a/Ubiquitous/XiZi/board/xidatong/third_party_driver/CMSIS/Include/cmsis_compiler.h b/Ubiquitous/XiZi/board/xidatong/third_party_driver/CMSIS/Include/cmsis_compiler.h new file mode 100644 index 0000000..94212eb --- /dev/null +++ b/Ubiquitous/XiZi/board/xidatong/third_party_driver/CMSIS/Include/cmsis_compiler.h @@ -0,0 +1,266 @@ +/**************************************************************************//** + * @file cmsis_compiler.h + * @brief CMSIS compiler generic header file + * @version V5.0.4 + * @date 10. January 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __CMSIS_COMPILER_H +#define __CMSIS_COMPILER_H + +#include + +/* + * Arm Compiler 4/5 + */ +#if defined ( __CC_ARM ) + #include "cmsis_armcc.h" + + +/* + * Arm Compiler 6 (armclang) + */ +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #include "cmsis_armclang.h" + + +/* + * GNU Compiler + */ +#elif defined ( __GNUC__ ) + #include "cmsis_gcc.h" + + +/* + * IAR Compiler + */ +#elif defined ( __ICCARM__ ) + #include + + +/* + * TI Arm Compiler + */ +#elif defined ( __TI_ARM__ ) + #include + + #ifndef __ASM + #define __ASM __asm + #endif + #ifndef __INLINE + #define __INLINE inline + #endif + #ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline + #endif + #ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __STATIC_INLINE + #endif + #ifndef __NO_RETURN + #define __NO_RETURN __attribute__((noreturn)) + #endif + #ifndef __USED + #define __USED __attribute__((used)) + #endif + #ifndef __WEAK + #define __WEAK __attribute__((weak)) + #endif + #ifndef __PACKED + #define __PACKED __attribute__((packed)) + #endif + #ifndef __PACKED_STRUCT + #define __PACKED_STRUCT struct __attribute__((packed)) + #endif + #ifndef __PACKED_UNION + #define __PACKED_UNION union __attribute__((packed)) + #endif + #ifndef __UNALIGNED_UINT32 /* deprecated */ + struct __attribute__((packed)) T_UINT32 { uint32_t v; }; + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) + #endif + #ifndef __UNALIGNED_UINT16_WRITE + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void*)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT16_READ + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) + #endif + #ifndef __UNALIGNED_UINT32_WRITE + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT32_READ + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) + #endif + #ifndef __ALIGNED + #define __ALIGNED(x) __attribute__((aligned(x))) + #endif + #ifndef __RESTRICT + #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored. + #define __RESTRICT + #endif + + +/* + * TASKING Compiler + */ +#elif defined ( __TASKING__ ) + /* + * The CMSIS functions have been implemented as intrinsics in the compiler. + * Please use "carm -?i" to get an up to date list of all intrinsics, + * Including the CMSIS ones. + */ + + #ifndef __ASM + #define __ASM __asm + #endif + #ifndef __INLINE + #define __INLINE inline + #endif + #ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline + #endif + #ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __STATIC_INLINE + #endif + #ifndef __NO_RETURN + #define __NO_RETURN __attribute__((noreturn)) + #endif + #ifndef __USED + #define __USED __attribute__((used)) + #endif + #ifndef __WEAK + #define __WEAK __attribute__((weak)) + #endif + #ifndef __PACKED + #define __PACKED __packed__ + #endif + #ifndef __PACKED_STRUCT + #define __PACKED_STRUCT struct __packed__ + #endif + #ifndef __PACKED_UNION + #define __PACKED_UNION union __packed__ + #endif + #ifndef __UNALIGNED_UINT32 /* deprecated */ + struct __packed__ T_UINT32 { uint32_t v; }; + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) + #endif + #ifndef __UNALIGNED_UINT16_WRITE + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT16_READ + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) + #endif + #ifndef __UNALIGNED_UINT32_WRITE + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT32_READ + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) + #endif + #ifndef __ALIGNED + #define __ALIGNED(x) __align(x) + #endif + #ifndef __RESTRICT + #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored. + #define __RESTRICT + #endif + + +/* + * COSMIC Compiler + */ +#elif defined ( __CSMC__ ) + #include + + #ifndef __ASM + #define __ASM _asm + #endif + #ifndef __INLINE + #define __INLINE inline + #endif + #ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline + #endif + #ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __STATIC_INLINE + #endif + #ifndef __NO_RETURN + // NO RETURN is automatically detected hence no warning here + #define __NO_RETURN + #endif + #ifndef __USED + #warning No compiler specific solution for __USED. __USED is ignored. + #define __USED + #endif + #ifndef __WEAK + #define __WEAK __weak + #endif + #ifndef __PACKED + #define __PACKED @packed + #endif + #ifndef __PACKED_STRUCT + #define __PACKED_STRUCT @packed struct + #endif + #ifndef __PACKED_UNION + #define __PACKED_UNION @packed union + #endif + #ifndef __UNALIGNED_UINT32 /* deprecated */ + @packed struct T_UINT32 { uint32_t v; }; + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) + #endif + #ifndef __UNALIGNED_UINT16_WRITE + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT16_READ + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) + #endif + #ifndef __UNALIGNED_UINT32_WRITE + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT32_READ + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) + #endif + #ifndef __ALIGNED + #warning No compiler specific solution for __ALIGNED. __ALIGNED is ignored. + #define __ALIGNED(x) + #endif + #ifndef __RESTRICT + #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored. + #define __RESTRICT + #endif + + +#else + #error Unknown compiler. +#endif + + +#endif /* __CMSIS_COMPILER_H */ + diff --git a/Ubiquitous/XiZi/board/xidatong/third_party_driver/CMSIS/Include/cmsis_gcc.h b/Ubiquitous/XiZi/board/xidatong/third_party_driver/CMSIS/Include/cmsis_gcc.h new file mode 100644 index 0000000..5d0f07e --- /dev/null +++ b/Ubiquitous/XiZi/board/xidatong/third_party_driver/CMSIS/Include/cmsis_gcc.h @@ -0,0 +1,2088 @@ +/**************************************************************************//** + * @file cmsis_gcc.h + * @brief CMSIS compiler GCC header file + * @version V5.0.3 + * @date 16. January 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2017 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __CMSIS_GCC_H +#define __CMSIS_GCC_H + +/* ignore some GCC warnings */ +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wsign-conversion" +#pragma GCC diagnostic ignored "-Wconversion" +#pragma GCC diagnostic ignored "-Wunused-parameter" + +/* Fallback for __has_builtin */ +#ifndef __has_builtin + #define __has_builtin(x) (0) +#endif + +/* CMSIS compiler specific defines */ +#ifndef __ASM + #define __ASM __asm +#endif +#ifndef __INLINE + #define __INLINE inline +#endif +#ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline +#endif +#ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __attribute__((always_inline)) static inline +#endif +#ifndef __NO_RETURN + #define __NO_RETURN __attribute__((__noreturn__)) +#endif +#ifndef __USED + #define __USED __attribute__((used)) +#endif +#ifndef __WEAK + #define __WEAK __attribute__((weak)) +#endif +#ifndef __PACKED + #define __PACKED __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_STRUCT + #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_UNION + #define __PACKED_UNION union __attribute__((packed, aligned(1))) +#endif +#ifndef __UNALIGNED_UINT32 /* deprecated */ + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + struct __attribute__((packed)) T_UINT32 { uint32_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) +#endif +#ifndef __UNALIGNED_UINT16_WRITE + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT16_READ + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) +#endif +#ifndef __UNALIGNED_UINT32_WRITE + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT32_READ + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) +#endif +#ifndef __ALIGNED + #define __ALIGNED(x) __attribute__((aligned(x))) +#endif +#ifndef __RESTRICT + #define __RESTRICT __restrict +#endif + + +/* ########################### Core Function Access ########################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ + */ + +/** + \brief Enable IRQ Interrupts + \details Enables IRQ interrupts by clearing the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __enable_irq(void) +{ + __ASM volatile ("cpsie i" : : : "memory"); +} + + +/** + \brief Disable IRQ Interrupts + \details Disables IRQ interrupts by setting the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __disable_irq(void) +{ + __ASM volatile ("cpsid i" : : : "memory"); +} + + +/** + \brief Get Control Register + \details Returns the content of the Control Register. + \return Control Register value + */ +__STATIC_FORCEINLINE uint32_t __get_CONTROL(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Control Register (non-secure) + \details Returns the content of the non-secure Control Register when in secure mode. + \return non-secure Control Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Control Register + \details Writes the given value to the Control Register. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __set_CONTROL(uint32_t control) +{ + __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Control Register (non-secure) + \details Writes the given value to the non-secure Control Register when in secure state. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control) +{ + __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory"); +} +#endif + + +/** + \brief Get IPSR Register + \details Returns the content of the IPSR Register. + \return IPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_IPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get APSR Register + \details Returns the content of the APSR Register. + \return APSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_APSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, apsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get xPSR Register + \details Returns the content of the xPSR Register. + \return xPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_xPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get Process Stack Pointer + \details Returns the current value of the Process Stack Pointer (PSP). + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSP(void) +{ + register uint32_t result; + + __ASM volatile ("MRS %0, psp" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Process Stack Pointer (non-secure) + \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state. + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void) +{ + register uint32_t result; + + __ASM volatile ("MRS %0, psp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Process Stack Pointer + \details Assigns the given value to the Process Stack Pointer (PSP). + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : ); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Process Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state. + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : ); +} +#endif + + +/** + \brief Get Main Stack Pointer + \details Returns the current value of the Main Stack Pointer (MSP). + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSP(void) +{ + register uint32_t result; + + __ASM volatile ("MRS %0, msp" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Main Stack Pointer (non-secure) + \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state. + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void) +{ + register uint32_t result; + + __ASM volatile ("MRS %0, msp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Main Stack Pointer + \details Assigns the given value to the Main Stack Pointer (MSP). + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : ); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Main Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state. + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : ); +} +#endif + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Stack Pointer (non-secure) + \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state. + \return SP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void) +{ + register uint32_t result; + + __ASM volatile ("MRS %0, sp_ns" : "=r" (result) ); + return(result); +} + + +/** + \brief Set Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state. + \param [in] topOfStack Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack) +{ + __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : ); +} +#endif + + +/** + \brief Get Priority Mask + \details Returns the current state of the priority mask bit from the Priority Mask Register. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __get_PRIMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory"); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Priority Mask (non-secure) + \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask_ns" : "=r" (result) :: "memory"); + return(result); +} +#endif + + +/** + \brief Set Priority Mask + \details Assigns the given value to the Priority Mask Register. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask) +{ + __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Priority Mask (non-secure) + \details Assigns the given value to the non-secure Priority Mask Register when in secure state. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask) +{ + __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory"); +} +#endif + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) +/** + \brief Enable FIQ + \details Enables FIQ interrupts by clearing the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __enable_fault_irq(void) +{ + __ASM volatile ("cpsie f" : : : "memory"); +} + + +/** + \brief Disable FIQ + \details Disables FIQ interrupts by setting the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __disable_fault_irq(void) +{ + __ASM volatile ("cpsid f" : : : "memory"); +} + + +/** + \brief Get Base Priority + \details Returns the current value of the Base Priority register. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __get_BASEPRI(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Base Priority (non-secure) + \details Returns the current value of the non-secure Base Priority register when in secure state. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Base Priority + \details Assigns the given value to the Base Priority register. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri) +{ + __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Base Priority (non-secure) + \details Assigns the given value to the non-secure Base Priority register when in secure state. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory"); +} +#endif + + +/** + \brief Set Base Priority with condition + \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, + or the new value increases the BASEPRI priority level. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory"); +} + + +/** + \brief Get Fault Mask + \details Returns the current value of the Fault Mask register. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Fault Mask (non-secure) + \details Returns the current value of the non-secure Fault Mask register when in secure state. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Fault Mask + \details Assigns the given value to the Fault Mask register. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Fault Mask (non-secure) + \details Assigns the given value to the non-secure Fault Mask register when in secure state. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory"); +} +#endif + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) + +/** + \brief Get Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always in non-secure + mode. + + \details Returns the current value of the Process Stack Pointer Limit (PSPLIM). + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSPLIM(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + return 0U; +#else + register uint32_t result; + __ASM volatile ("MRS %0, psplim" : "=r" (result) ); + return result; +#endif +} + +#if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Process Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + return 0U; +#else + register uint32_t result; + __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) ); + return result; +#endif +} +#endif + + +/** + \brief Set Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored in non-secure + mode. + + \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM). + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit)); +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Process Stack Pointer (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit)); +#endif +} +#endif + + +/** + \brief Get Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always in non-secure + mode. + + \details Returns the current value of the Main Stack Pointer Limit (MSPLIM). + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSPLIM(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + return 0U; +#else + register uint32_t result; + __ASM volatile ("MRS %0, msplim" : "=r" (result) ); + return result; +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state. + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + return 0U; +#else + register uint32_t result; + __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) ); + return result; +#endif +} +#endif + + +/** + \brief Set Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored in non-secure + mode. + + \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM). + \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit)); +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state. + \param [in] MainStackPtrLimit Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit)); +#endif +} +#endif + +#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) + +/** + \brief Get FPSCR + \details Returns the current value of the Floating Point Status/Control register. + \return Floating Point Status/Control register value + */ +__STATIC_FORCEINLINE uint32_t __get_FPSCR(void) +{ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) +#if __has_builtin(__builtin_arm_get_fpscr) || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2) + /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */ + return __builtin_arm_get_fpscr(); +#else + uint32_t result; + + __ASM volatile ("VMRS %0, fpscr" : "=r" (result) ); + return(result); +#endif +#else + return(0U); +#endif +} + + +/** + \brief Set FPSCR + \details Assigns the given value to the Floating Point Status/Control register. + \param [in] fpscr Floating Point Status/Control value to set + */ +__STATIC_FORCEINLINE void __set_FPSCR(uint32_t fpscr) +{ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) +#if __has_builtin(__builtin_arm_set_fpscr) || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2) + /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */ + __builtin_arm_set_fpscr(fpscr); +#else + __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc", "memory"); +#endif +#else + (void)fpscr; +#endif +} + +#endif /* ((defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + + + +/*@} end of CMSIS_Core_RegAccFunctions */ + + +/* ########################## Core Instruction Access ######################### */ +/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface + Access to dedicated instructions + @{ +*/ + +/* Define macros for porting to both thumb1 and thumb2. + * For thumb1, use low register (r0-r7), specified by constraint "l" + * Otherwise, use general registers, specified by constraint "r" */ +#if defined (__thumb__) && !defined (__thumb2__) +#define __CMSIS_GCC_OUT_REG(r) "=l" (r) +#define __CMSIS_GCC_RW_REG(r) "+l" (r) +#define __CMSIS_GCC_USE_REG(r) "l" (r) +#else +#define __CMSIS_GCC_OUT_REG(r) "=r" (r) +#define __CMSIS_GCC_RW_REG(r) "+r" (r) +#define __CMSIS_GCC_USE_REG(r) "r" (r) +#endif + +/** + \brief No Operation + \details No Operation does nothing. This instruction can be used for code alignment purposes. + */ +#define __NOP() __ASM volatile ("nop") + +/** + \brief Wait For Interrupt + \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. + */ +#define __WFI() __ASM volatile ("wfi") + + +/** + \brief Wait For Event + \details Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +#define __WFE() __ASM volatile ("wfe") + + +/** + \brief Send Event + \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. + */ +#define __SEV() __ASM volatile ("sev") + + +/** + \brief Instruction Synchronization Barrier + \details Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or memory, + after the instruction has been completed. + */ +__STATIC_FORCEINLINE void __ISB(void) +{ + __ASM volatile ("isb 0xF":::"memory"); +} + + +/** + \brief Data Synchronization Barrier + \details Acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +__STATIC_FORCEINLINE void __DSB(void) +{ + __ASM volatile ("dsb 0xF":::"memory"); +} + + +/** + \brief Data Memory Barrier + \details Ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +__STATIC_FORCEINLINE void __DMB(void) +{ + __ASM volatile ("dmb 0xF":::"memory"); +} + + +/** + \brief Reverse byte order (32 bit) + \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412. + \param [in] value Value to reverse + \return Reversed value + */ +__STATIC_FORCEINLINE uint32_t __REV(uint32_t value) +{ +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5) + return __builtin_bswap32(value); +#else + uint32_t result; + + __ASM volatile ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return result; +#endif +} + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856. + \param [in] value Value to reverse + \return Reversed value + */ +__STATIC_FORCEINLINE uint32_t __REV16(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return result; +} + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000. + \param [in] value Value to reverse + \return Reversed value + */ +__STATIC_FORCEINLINE int16_t __REVSH(int16_t value) +{ +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + return (int16_t)__builtin_bswap16(value); +#else + int16_t result; + + __ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return result; +#endif +} + + +/** + \brief Rotate Right in unsigned value (32 bit) + \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + \param [in] op1 Value to rotate + \param [in] op2 Number of Bits to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2) +{ + op2 %= 32U; + if (op2 == 0U) + { + return op1; + } + return (op1 >> op2) | (op1 << (32U - op2)); +} + + +/** + \brief Breakpoint + \details Causes the processor to enter Debug state. + Debug tools can use this to investigate system state when the instruction at a particular address is reached. + \param [in] value is ignored by the processor. + If required, a debugger can use it to store additional information about the breakpoint. + */ +#define __BKPT(value) __ASM volatile ("bkpt "#value) + + +/** + \brief Reverse bit order of value + \details Reverses the bit order of the given value. + \param [in] value Value to reverse + \return Reversed value + */ +__STATIC_FORCEINLINE uint32_t __RBIT(uint32_t value) +{ + uint32_t result; + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) + __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); +#else + uint32_t s = (4U /*sizeof(v)*/ * 8U) - 1U; /* extra shift needed at end */ + + result = value; /* r will be reversed bits of v; first get LSB of v */ + for (value >>= 1U; value != 0U; value >>= 1U) + { + result <<= 1U; + result |= value & 1U; + s--; + } + result <<= s; /* shift when v's highest bits are zero */ +#endif + return result; +} + + +/** + \brief Count leading zeros + \details Counts the number of leading zeros of a data value. + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +#define __CLZ (uint8_t)__builtin_clz + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) +/** + \brief LDR Exclusive (8 bit) + \details Executes a exclusive LDR instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDREXB(volatile uint8_t *addr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); +#endif + return ((uint8_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDR Exclusive (16 bit) + \details Executes a exclusive LDR instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDREXH(volatile uint16_t *addr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); +#endif + return ((uint16_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDR Exclusive (32 bit) + \details Executes a exclusive LDR instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDREXW(volatile uint32_t *addr) +{ + uint32_t result; + + __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); + return(result); +} + + +/** + \brief STR Exclusive (8 bit) + \details Executes a exclusive STR instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr) +{ + uint32_t result; + + __ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) ); + return(result); +} + + +/** + \brief STR Exclusive (16 bit) + \details Executes a exclusive STR instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr) +{ + uint32_t result; + + __ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) ); + return(result); +} + + +/** + \brief STR Exclusive (32 bit) + \details Executes a exclusive STR instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr) +{ + uint32_t result; + + __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); + return(result); +} + + +/** + \brief Remove the exclusive lock + \details Removes the exclusive lock which is created by LDREX. + */ +__STATIC_FORCEINLINE void __CLREX(void) +{ + __ASM volatile ("clrex" ::: "memory"); +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] ARG1 Value to be saturated + \param [in] ARG2 Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT(ARG1,ARG2) \ +__extension__ \ +({ \ + int32_t __RES, __ARG1 = (ARG1); \ + __ASM ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] ARG1 Value to be saturated + \param [in] ARG2 Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT(ARG1,ARG2) \ + __extension__ \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + + +/** + \brief Rotate Right with Extend (32 bit) + \details Moves each bit of a bitstring right by one bit. + The carry input is shifted in at the left end of the bitstring. + \param [in] value Value to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __RRX(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return(result); +} + + +/** + \brief LDRT Unprivileged (8 bit) + \details Executes a Unprivileged LDRT instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDRBT(volatile uint8_t *ptr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrbt %0, [%1]" : "=r" (result) : "r" (ptr) : "memory" ); +#endif + return ((uint8_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (16 bit) + \details Executes a Unprivileged LDRT instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDRHT(volatile uint16_t *ptr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrht %0, [%1]" : "=r" (result) : "r" (ptr) : "memory" ); +#endif + return ((uint16_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (32 bit) + \details Executes a Unprivileged LDRT instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDRT(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) ); + return(result); +} + + +/** + \brief STRT Unprivileged (8 bit) + \details Executes a Unprivileged STRT instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRBT(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (16 bit) + \details Executes a Unprivileged STRT instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRHT(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (32 bit) + \details Executes a Unprivileged STRT instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRT(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) ); +} + +#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +__STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat) +{ + if ((sat >= 1U) && (sat <= 32U)) + { + const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); + const int32_t min = -1 - max ; + if (val > max) + { + return max; + } + else if (val < min) + { + return min; + } + } + return val; +} + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +__STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat) +{ + if (sat <= 31U) + { + const uint32_t max = ((1U << sat) - 1U); + if (val > (int32_t)max) + { + return max; + } + else if (val < 0) + { + return 0U; + } + } + return (uint32_t)val; +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) +/** + \brief Load-Acquire (8 bit) + \details Executes a LDAB instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDAB(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint8_t) result); +} + + +/** + \brief Load-Acquire (16 bit) + \details Executes a LDAH instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDAH(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint16_t) result); +} + + +/** + \brief Load-Acquire (32 bit) + \details Executes a LDA instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDA(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) ); + return(result); +} + + +/** + \brief Store-Release (8 bit) + \details Executes a STLB instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLB(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief Store-Release (16 bit) + \details Executes a STLH instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLH(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief Store-Release (32 bit) + \details Executes a STL instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief Load-Acquire Exclusive (8 bit) + \details Executes a LDAB exclusive instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDAEXB(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldaexb %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint8_t) result); +} + + +/** + \brief Load-Acquire Exclusive (16 bit) + \details Executes a LDAH exclusive instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDAEXH(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldaexh %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint16_t) result); +} + + +/** + \brief Load-Acquire Exclusive (32 bit) + \details Executes a LDA exclusive instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDAEX(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldaex %0, %1" : "=r" (result) : "Q" (*ptr) ); + return(result); +} + + +/** + \brief Store-Release Exclusive (8 bit) + \details Executes a STLB exclusive instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STLEXB(uint8_t value, volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("stlexb %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) ); + return(result); +} + + +/** + \brief Store-Release Exclusive (16 bit) + \details Executes a STLH exclusive instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STLEXH(uint16_t value, volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("stlexh %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) ); + return(result); +} + + +/** + \brief Store-Release Exclusive (32 bit) + \details Executes a STL exclusive instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STLEX(uint32_t value, volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("stlex %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) ); + return(result); +} + +#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + +/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ + + +/* ################### Compiler specific Intrinsics ########################### */ +/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics + Access to dedicated SIMD instructions + @{ +*/ + +#if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1)) + +__STATIC_FORCEINLINE uint32_t __SADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +__STATIC_FORCEINLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +__STATIC_FORCEINLINE uint32_t __SADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USAD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#define __SSAT16(ARG1,ARG2) \ +({ \ + int32_t __RES, __ARG1 = (ARG1); \ + __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + +#define __USAT16(ARG1,ARG2) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + +__STATIC_FORCEINLINE uint32_t __UXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1)); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1)); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint32_t __SEL (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE int32_t __QADD( int32_t op1, int32_t op2) +{ + int32_t result; + + __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE int32_t __QSUB( int32_t op1, int32_t op2) +{ + int32_t result; + + __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +#if 0 +#define __PKHBT(ARG1,ARG2,ARG3) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ + __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ + __RES; \ + }) + +#define __PKHTB(ARG1,ARG2,ARG3) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ + if (ARG3 == 0) \ + __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \ + else \ + __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ + __RES; \ + }) +#endif + +#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \ + ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) ) + +#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \ + ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) ) + +__STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3) +{ + int32_t result; + + __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#endif /* (__ARM_FEATURE_DSP == 1) */ +/*@} end of group CMSIS_SIMD_intrinsics */ + + +#pragma GCC diagnostic pop + +#endif /* __CMSIS_GCC_H */ diff --git a/Ubiquitous/XiZi/board/xidatong/third_party_driver/CMSIS/Include/cmsis_version.h b/Ubiquitous/XiZi/board/xidatong/third_party_driver/CMSIS/Include/cmsis_version.h new file mode 100644 index 0000000..660f612 --- /dev/null +++ b/Ubiquitous/XiZi/board/xidatong/third_party_driver/CMSIS/Include/cmsis_version.h @@ -0,0 +1,39 @@ +/**************************************************************************//** + * @file cmsis_version.h + * @brief CMSIS Core(M) Version definitions + * @version V5.0.2 + * @date 19. April 2017 + ******************************************************************************/ +/* + * Copyright (c) 2009-2017 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CMSIS_VERSION_H +#define __CMSIS_VERSION_H + +/* CMSIS Version definitions */ +#define __CM_CMSIS_VERSION_MAIN ( 5U) /*!< [31:16] CMSIS Core(M) main version */ +#define __CM_CMSIS_VERSION_SUB ( 1U) /*!< [15:0] CMSIS Core(M) sub version */ +#define __CM_CMSIS_VERSION ((__CM_CMSIS_VERSION_MAIN << 16U) | \ + __CM_CMSIS_VERSION_SUB ) /*!< CMSIS Core(M) version number */ +#endif diff --git a/Ubiquitous/XiZi/board/xidatong/third_party_driver/CMSIS/Include/core_cm7.h b/Ubiquitous/XiZi/board/xidatong/third_party_driver/CMSIS/Include/core_cm7.h new file mode 100644 index 0000000..1fe53bf --- /dev/null +++ b/Ubiquitous/XiZi/board/xidatong/third_party_driver/CMSIS/Include/core_cm7.h @@ -0,0 +1,2660 @@ +/**************************************************************************//** + * @file core_cm7.h + * @brief CMSIS Cortex-M7 Core Peripheral Access Layer Header File + * @version V5.0.5 + * @date 08. January 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2017 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM7_H_GENERIC +#define __CORE_CM7_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M7 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM7 definitions */ +#define __CM7_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM7_CMSIS_VERSION_SUB ( __CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM7_CMSIS_VERSION ((__CM7_CMSIS_VERSION_MAIN << 16U) | \ + __CM7_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (7U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. +*/ +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_PCS_VFP + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM7_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM7_H_DEPENDANT +#define __CORE_CM7_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM7_REV + #define __CM7_REV 0x0000U + #warning "__CM7_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __ICACHE_PRESENT + #define __ICACHE_PRESENT 0U + #warning "__ICACHE_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DCACHE_PRESENT + #define __DCACHE_PRESENT 0U + #warning "__DCACHE_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DTCM_PRESENT + #define __DTCM_PRESENT 0U + #warning "__DTCM_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M7 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core FPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + +#define APSR_GE_Pos 16U /*!< APSR: GE Position */ +#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:1; /*!< bit: 9 Reserved */ + uint32_t ICI_IT_1:6; /*!< bit: 10..15 ICI/IT part 1 */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit */ + uint32_t ICI_IT_2:2; /*!< bit: 25..26 ICI/IT part 2 */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_ICI_IT_2_Pos 25U /*!< xPSR: ICI/IT part 2 Position */ +#define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) /*!< xPSR: ICI/IT part 2 Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ +#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ + +#define xPSR_ICI_IT_1_Pos 10U /*!< xPSR: ICI/IT part 1 Position */ +#define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) /*!< xPSR: ICI/IT part 1 Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */ + uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ +#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ + +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[24U]; + __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[24U]; + __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[24U]; + __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[24U]; + __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[56U]; + __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED5[644U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ID_AFR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t ID_MFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ID_ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + uint32_t RESERVED0[1U]; + __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */ + __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */ + __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */ + __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ + uint32_t RESERVED3[93U]; + __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */ + uint32_t RESERVED4[15U]; + __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */ + uint32_t RESERVED5[1U]; + __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */ + uint32_t RESERVED6[1U]; + __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */ + __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */ + __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */ + __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */ + __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */ + __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */ + __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */ + __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */ + uint32_t RESERVED7[6U]; + __IOM uint32_t ITCMCR; /*!< Offset: 0x290 (R/W) Instruction Tightly-Coupled Memory Control Register */ + __IOM uint32_t DTCMCR; /*!< Offset: 0x294 (R/W) Data Tightly-Coupled Memory Control Registers */ + __IOM uint32_t AHBPCR; /*!< Offset: 0x298 (R/W) AHBP Control Register */ + __IOM uint32_t CACR; /*!< Offset: 0x29C (R/W) L1 Cache Control Register */ + __IOM uint32_t AHBSCR; /*!< Offset: 0x2A0 (R/W) AHB Slave Control Register */ + uint32_t RESERVED8[1U]; + __IOM uint32_t ABFSR; /*!< Offset: 0x2A8 (R/W) Auxiliary Bus Fault Status Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */ +#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: Branch prediction enable bit Position */ +#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: Branch prediction enable bit Mask */ + +#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: Instruction cache enable bit Position */ +#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: Instruction cache enable bit Mask */ + +#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: Cache enable bit Position */ +#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: Cache enable bit Mask */ + +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */ +#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ +#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ +#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/* SCB Cache Level ID Register Definitions */ +#define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */ +#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */ + +#define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */ +#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */ + +/* SCB Cache Type Register Definitions */ +#define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */ +#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */ + +#define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */ +#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */ + +#define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */ +#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */ + +#define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */ +#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */ + +#define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */ +#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */ + +/* SCB Cache Size ID Register Definitions */ +#define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */ +#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */ + +#define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */ +#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */ + +#define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */ +#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */ + +#define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */ +#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */ + +#define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */ +#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */ + +#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */ +#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */ + +#define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */ +#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */ + +/* SCB Cache Size Selection Register Definitions */ +#define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */ +#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */ + +#define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */ +#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */ + +/* SCB Software Triggered Interrupt Register Definitions */ +#define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */ +#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */ + +/* SCB D-Cache Invalidate by Set-way Register Definitions */ +#define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */ +#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */ + +#define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */ +#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */ + +/* SCB D-Cache Clean by Set-way Register Definitions */ +#define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */ +#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */ + +#define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */ +#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */ + +/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */ +#define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */ +#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */ + +#define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */ +#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */ + +/* Instruction Tightly-Coupled Memory Control Register Definitions */ +#define SCB_ITCMCR_SZ_Pos 3U /*!< SCB ITCMCR: SZ Position */ +#define SCB_ITCMCR_SZ_Msk (0xFUL << SCB_ITCMCR_SZ_Pos) /*!< SCB ITCMCR: SZ Mask */ + +#define SCB_ITCMCR_RETEN_Pos 2U /*!< SCB ITCMCR: RETEN Position */ +#define SCB_ITCMCR_RETEN_Msk (1UL << SCB_ITCMCR_RETEN_Pos) /*!< SCB ITCMCR: RETEN Mask */ + +#define SCB_ITCMCR_RMW_Pos 1U /*!< SCB ITCMCR: RMW Position */ +#define SCB_ITCMCR_RMW_Msk (1UL << SCB_ITCMCR_RMW_Pos) /*!< SCB ITCMCR: RMW Mask */ + +#define SCB_ITCMCR_EN_Pos 0U /*!< SCB ITCMCR: EN Position */ +#define SCB_ITCMCR_EN_Msk (1UL /*<< SCB_ITCMCR_EN_Pos*/) /*!< SCB ITCMCR: EN Mask */ + +/* Data Tightly-Coupled Memory Control Register Definitions */ +#define SCB_DTCMCR_SZ_Pos 3U /*!< SCB DTCMCR: SZ Position */ +#define SCB_DTCMCR_SZ_Msk (0xFUL << SCB_DTCMCR_SZ_Pos) /*!< SCB DTCMCR: SZ Mask */ + +#define SCB_DTCMCR_RETEN_Pos 2U /*!< SCB DTCMCR: RETEN Position */ +#define SCB_DTCMCR_RETEN_Msk (1UL << SCB_DTCMCR_RETEN_Pos) /*!< SCB DTCMCR: RETEN Mask */ + +#define SCB_DTCMCR_RMW_Pos 1U /*!< SCB DTCMCR: RMW Position */ +#define SCB_DTCMCR_RMW_Msk (1UL << SCB_DTCMCR_RMW_Pos) /*!< SCB DTCMCR: RMW Mask */ + +#define SCB_DTCMCR_EN_Pos 0U /*!< SCB DTCMCR: EN Position */ +#define SCB_DTCMCR_EN_Msk (1UL /*<< SCB_DTCMCR_EN_Pos*/) /*!< SCB DTCMCR: EN Mask */ + +/* AHBP Control Register Definitions */ +#define SCB_AHBPCR_SZ_Pos 1U /*!< SCB AHBPCR: SZ Position */ +#define SCB_AHBPCR_SZ_Msk (7UL << SCB_AHBPCR_SZ_Pos) /*!< SCB AHBPCR: SZ Mask */ + +#define SCB_AHBPCR_EN_Pos 0U /*!< SCB AHBPCR: EN Position */ +#define SCB_AHBPCR_EN_Msk (1UL /*<< SCB_AHBPCR_EN_Pos*/) /*!< SCB AHBPCR: EN Mask */ + +/* L1 Cache Control Register Definitions */ +#define SCB_CACR_FORCEWT_Pos 2U /*!< SCB CACR: FORCEWT Position */ +#define SCB_CACR_FORCEWT_Msk (1UL << SCB_CACR_FORCEWT_Pos) /*!< SCB CACR: FORCEWT Mask */ + +#define SCB_CACR_ECCEN_Pos 1U /*!< SCB CACR: ECCEN Position */ +#define SCB_CACR_ECCEN_Msk (1UL << SCB_CACR_ECCEN_Pos) /*!< SCB CACR: ECCEN Mask */ + +#define SCB_CACR_SIWT_Pos 0U /*!< SCB CACR: SIWT Position */ +#define SCB_CACR_SIWT_Msk (1UL /*<< SCB_CACR_SIWT_Pos*/) /*!< SCB CACR: SIWT Mask */ + +/* AHBS Control Register Definitions */ +#define SCB_AHBSCR_INITCOUNT_Pos 11U /*!< SCB AHBSCR: INITCOUNT Position */ +#define SCB_AHBSCR_INITCOUNT_Msk (0x1FUL << SCB_AHBPCR_INITCOUNT_Pos) /*!< SCB AHBSCR: INITCOUNT Mask */ + +#define SCB_AHBSCR_TPRI_Pos 2U /*!< SCB AHBSCR: TPRI Position */ +#define SCB_AHBSCR_TPRI_Msk (0x1FFUL << SCB_AHBPCR_TPRI_Pos) /*!< SCB AHBSCR: TPRI Mask */ + +#define SCB_AHBSCR_CTL_Pos 0U /*!< SCB AHBSCR: CTL Position*/ +#define SCB_AHBSCR_CTL_Msk (3UL /*<< SCB_AHBPCR_CTL_Pos*/) /*!< SCB AHBSCR: CTL Mask */ + +/* Auxiliary Bus Fault Status Register Definitions */ +#define SCB_ABFSR_AXIMTYPE_Pos 8U /*!< SCB ABFSR: AXIMTYPE Position*/ +#define SCB_ABFSR_AXIMTYPE_Msk (3UL << SCB_ABFSR_AXIMTYPE_Pos) /*!< SCB ABFSR: AXIMTYPE Mask */ + +#define SCB_ABFSR_EPPB_Pos 4U /*!< SCB ABFSR: EPPB Position*/ +#define SCB_ABFSR_EPPB_Msk (1UL << SCB_ABFSR_EPPB_Pos) /*!< SCB ABFSR: EPPB Mask */ + +#define SCB_ABFSR_AXIM_Pos 3U /*!< SCB ABFSR: AXIM Position*/ +#define SCB_ABFSR_AXIM_Msk (1UL << SCB_ABFSR_AXIM_Pos) /*!< SCB ABFSR: AXIM Mask */ + +#define SCB_ABFSR_AHBP_Pos 2U /*!< SCB ABFSR: AHBP Position*/ +#define SCB_ABFSR_AHBP_Msk (1UL << SCB_ABFSR_AHBP_Pos) /*!< SCB ABFSR: AHBP Mask */ + +#define SCB_ABFSR_DTCM_Pos 1U /*!< SCB ABFSR: DTCM Position*/ +#define SCB_ABFSR_DTCM_Msk (1UL << SCB_ABFSR_DTCM_Pos) /*!< SCB ABFSR: DTCM Mask */ + +#define SCB_ABFSR_ITCM_Pos 0U /*!< SCB ABFSR: ITCM Position*/ +#define SCB_ABFSR_ITCM_Msk (1UL /*<< SCB_ABFSR_ITCM_Pos*/) /*!< SCB ABFSR: ITCM Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/* Auxiliary Control Register Definitions */ +#define SCnSCB_ACTLR_DISITMATBFLUSH_Pos 12U /*!< ACTLR: DISITMATBFLUSH Position */ +#define SCnSCB_ACTLR_DISITMATBFLUSH_Msk (1UL << SCnSCB_ACTLR_DISITMATBFLUSH_Pos) /*!< ACTLR: DISITMATBFLUSH Mask */ + +#define SCnSCB_ACTLR_DISRAMODE_Pos 11U /*!< ACTLR: DISRAMODE Position */ +#define SCnSCB_ACTLR_DISRAMODE_Msk (1UL << SCnSCB_ACTLR_DISRAMODE_Pos) /*!< ACTLR: DISRAMODE Mask */ + +#define SCnSCB_ACTLR_FPEXCODIS_Pos 10U /*!< ACTLR: FPEXCODIS Position */ +#define SCnSCB_ACTLR_FPEXCODIS_Msk (1UL << SCnSCB_ACTLR_FPEXCODIS_Pos) /*!< ACTLR: FPEXCODIS Mask */ + +#define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */ +#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ + +#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */ +#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[29U]; + __OM uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */ + __IM uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */ + __IOM uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */ + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[6U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */ +#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Integration Write Register Definitions */ +#define ITM_IWR_ATVALIDM_Pos 0U /*!< ITM IWR: ATVALIDM Position */ +#define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */ + +/* ITM Integration Read Register Definitions */ +#define ITM_IRR_ATREADYM_Pos 0U /*!< ITM IRR: ATREADYM Position */ +#define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */ + +/* ITM Integration Mode Control Register Definitions */ +#define ITM_IMCR_INTEGRATION_Pos 0U /*!< ITM IMCR: INTEGRATION Position */ +#define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED0[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ + uint32_t RESERVED3[981U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( W) Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Mask Register Definitions */ +#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */ +#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */ +#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ + +#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */ +#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */ +#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ + +#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */ +#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ + +#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */ +#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ + +#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */ +#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ + +#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */ +#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IOM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */ + __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ + __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ + __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< @Deprecated TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< @Deprecated TPI ACPR: PRESCALER Mask */ + +#define TPI_ACPR_SWOSCALER_Pos 0U /*!< TPI ACPR: SWOSCALER Position */ +#define TPI_ACPR_SWOSCALER_Msk (0xFFFFUL /*<< TPI_ACPR_SWOSCALER_Pos*/) /*!< TPI ACPR: SWOSCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration ETM Data Register Definitions (FIFO0) */ +#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ +#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ + +#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ +#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ + +#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ +#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ + +#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ +#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ + +#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ +#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ + +#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ +#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ + +#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ +#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ + +/* TPI ITATBCTR2 Register Definitions */ +#define TPI_ITATBCTR2_ATREADY_Pos 0U /*!< TPI ITATBCTR2: ATREADY Position */ +#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) /*!< TPI ITATBCTR2: ATREADY Mask */ + +/* TPI Integration ITM Data Register Definitions (FIFO1) */ +#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ +#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ + +#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ +#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ + +#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ +#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ + +#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ +#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ + +#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ +#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ + +#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ +#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ + +#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ +#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ + +/* TPI ITATBCTR0 Register Definitions */ +#define TPI_ITATBCTR0_ATREADY_Pos 0U /*!< TPI ITATBCTR0: ATREADY Position */ +#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) /*!< TPI ITATBCTR0: ATREADY Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ +#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ + +#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ +#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_MajorType_Pos 4U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +#define TPI_DEVTYPE_SubType_Pos 0U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ + __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ + __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ + __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ +} MPU_Type; + +#define MPU_TYPE_RALIASES 4U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register Definitions */ +#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif /* defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_FPU Floating Point Unit (FPU) + \brief Type definitions for the Floating Point Unit (FPU) + @{ + */ + +/** + \brief Structure type to access the Floating Point Unit (FPU). + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ + __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ + __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ + __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x018 (R/ ) Media and FP Feature Register 2 */ +} FPU_Type; + +/* Floating-Point Context Control Register Definitions */ +#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ +#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ + +#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ +#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ + +#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ +#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ + +#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ +#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ + +#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ +#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ + +#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ +#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ + +#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ +#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ + +#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ +#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ + +#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ +#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ + +/* Floating-Point Context Address Register Definitions */ +#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ +#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ + +/* Floating-Point Default Status Control Register Definitions */ +#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ +#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ + +#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ +#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ + +#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ +#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ + +#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ +#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ + +/* Media and FP Feature Register 0 Definitions */ +#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */ +#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ + +#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */ +#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ + +#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */ +#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ + +#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */ +#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ + +#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */ +#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ + +#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */ +#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ + +#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */ +#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ + +#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */ +#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */ + +/* Media and FP Feature Register 1 Definitions */ +#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */ +#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ + +#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */ +#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ + +#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */ +#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ + +#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */ +#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ + +/* Media and FP Feature Register 2 Definitions */ + +/*@} end of group CMSIS_FPU */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ +#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ +#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ +#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ +#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ +#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ +#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ +#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +#define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ +#define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IP[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv7.h" + +#endif + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + uint32_t mvfr0; + + mvfr0 = SCB->MVFR0; + if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U) + { + return 2U; /* Double + Single precision FPU */ + } + else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U) + { + return 1U; /* Single precision FPU */ + } + else + { + return 0U; /* No FPU */ + } +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ########################## Cache functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_CacheFunctions Cache Functions + \brief Functions that configure Instruction and Data cache. + @{ + */ + +/* Cache Size ID Register Macros */ +#define CCSIDR_WAYS(x) (((x) & SCB_CCSIDR_ASSOCIATIVITY_Msk) >> SCB_CCSIDR_ASSOCIATIVITY_Pos) +#define CCSIDR_SETS(x) (((x) & SCB_CCSIDR_NUMSETS_Msk ) >> SCB_CCSIDR_NUMSETS_Pos ) + + +/** + \brief Enable I-Cache + \details Turns on I-Cache + */ +__STATIC_INLINE void SCB_EnableICache (void) +{ + #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U) + __DSB(); + __ISB(); + SCB->ICIALLU = 0UL; /* invalidate I-Cache */ + __DSB(); + __ISB(); + SCB->CCR |= (uint32_t)SCB_CCR_IC_Msk; /* enable I-Cache */ + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Disable I-Cache + \details Turns off I-Cache + */ +__STATIC_INLINE void SCB_DisableICache (void) +{ + #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U) + __DSB(); + __ISB(); + SCB->CCR &= ~(uint32_t)SCB_CCR_IC_Msk; /* disable I-Cache */ + SCB->ICIALLU = 0UL; /* invalidate I-Cache */ + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Invalidate I-Cache + \details Invalidates I-Cache + */ +__STATIC_INLINE void SCB_InvalidateICache (void) +{ + #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U) + __DSB(); + __ISB(); + SCB->ICIALLU = 0UL; + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Enable D-Cache + \details Turns on D-Cache + */ +__STATIC_INLINE void SCB_EnableDCache (void) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + SCB->CSSELR = 0U; /*(0U << 1U) | 0U;*/ /* Level 1 data cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* invalidate D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) | + ((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways-- != 0U); + } while(sets-- != 0U); + __DSB(); + + SCB->CCR |= (uint32_t)SCB_CCR_DC_Msk; /* enable D-Cache */ + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Disable D-Cache + \details Turns off D-Cache + */ +__STATIC_INLINE void SCB_DisableDCache (void) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + register uint32_t ccsidr; + register uint32_t sets; + register uint32_t ways; + + SCB->CSSELR = 0U; /*(0U << 1U) | 0U;*/ /* Level 1 data cache */ + __DSB(); + + SCB->CCR &= ~(uint32_t)SCB_CCR_DC_Msk; /* disable D-Cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* clean & invalidate D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCCISW = (((sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) | + ((ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways-- != 0U); + } while(sets-- != 0U); + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Invalidate D-Cache + \details Invalidates D-Cache + */ +__STATIC_INLINE void SCB_InvalidateDCache (void) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + SCB->CSSELR = 0U; /*(0U << 1U) | 0U;*/ /* Level 1 data cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* invalidate D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) | + ((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways-- != 0U); + } while(sets-- != 0U); + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Clean D-Cache + \details Cleans D-Cache + */ +__STATIC_INLINE void SCB_CleanDCache (void) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + SCB->CSSELR = 0U; /*(0U << 1U) | 0U;*/ /* Level 1 data cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* clean D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCCSW = (((sets << SCB_DCCSW_SET_Pos) & SCB_DCCSW_SET_Msk) | + ((ways << SCB_DCCSW_WAY_Pos) & SCB_DCCSW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways-- != 0U); + } while(sets-- != 0U); + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Clean & Invalidate D-Cache + \details Cleans and Invalidates D-Cache + */ +__STATIC_INLINE void SCB_CleanInvalidateDCache (void) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + SCB->CSSELR = 0U; /*(0U << 1U) | 0U;*/ /* Level 1 data cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* clean & invalidate D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCCISW = (((sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) | + ((ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways-- != 0U); + } while(sets-- != 0U); + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief D-Cache Invalidate by address + \details Invalidates D-Cache for the given address + \param[in] addr address (aligned to 32-byte boundary) + \param[in] dsize size of memory block (in number of bytes) +*/ +__STATIC_INLINE void SCB_InvalidateDCache_by_Addr (uint32_t *addr, int32_t dsize) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + int32_t op_size = dsize; + uint32_t op_addr = (uint32_t)addr; + int32_t linesize = 32; /* in Cortex-M7 size of cache line is fixed to 8 words (32 bytes) */ + + __DSB(); + + while (op_size > 0) { + SCB->DCIMVAC = op_addr; + op_addr += (uint32_t)linesize; + op_size -= linesize; + } + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief D-Cache Clean by address + \details Cleans D-Cache for the given address + \param[in] addr address (aligned to 32-byte boundary) + \param[in] dsize size of memory block (in number of bytes) +*/ +__STATIC_INLINE void SCB_CleanDCache_by_Addr (uint32_t *addr, int32_t dsize) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + int32_t op_size = dsize; + uint32_t op_addr = (uint32_t) addr; + int32_t linesize = 32; /* in Cortex-M7 size of cache line is fixed to 8 words (32 bytes) */ + + __DSB(); + + while (op_size > 0) { + SCB->DCCMVAC = op_addr; + op_addr += (uint32_t)linesize; + op_size -= linesize; + } + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief D-Cache Clean and Invalidate by address + \details Cleans and invalidates D_Cache for the given address + \param[in] addr address (aligned to 32-byte boundary) + \param[in] dsize size of memory block (in number of bytes) +*/ +__STATIC_INLINE void SCB_CleanInvalidateDCache_by_Addr (uint32_t *addr, int32_t dsize) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + int32_t op_size = dsize; + uint32_t op_addr = (uint32_t) addr; + int32_t linesize = 32; /* in Cortex-M7 size of cache line is fixed to 8 words (32 bytes) */ + + __DSB(); + + while (op_size > 0) { + SCB->DCCIMVAC = op_addr; + op_addr += (uint32_t)linesize; + op_size -= linesize; + } + + __DSB(); + __ISB(); + #endif +} + + +/*@} end of CMSIS_Core_CacheFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM7_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/Ubiquitous/XiZi/board/xidatong/third_party_driver/CMSIS/Include/mpu_armv7.h b/Ubiquitous/XiZi/board/xidatong/third_party_driver/CMSIS/Include/mpu_armv7.h new file mode 100644 index 0000000..aa180c9 --- /dev/null +++ b/Ubiquitous/XiZi/board/xidatong/third_party_driver/CMSIS/Include/mpu_armv7.h @@ -0,0 +1,197 @@ +/****************************************************************************** + * @file mpu_armv7.h + * @brief CMSIS MPU API for Armv7-M MPU + * @version V5.0.4 + * @date 10. January 2018 + ******************************************************************************/ +/* + * Copyright (c) 2017-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef ARM_MPU_ARMV7_H +#define ARM_MPU_ARMV7_H + +#define ARM_MPU_REGION_SIZE_32B ((uint8_t)0x04U) +#define ARM_MPU_REGION_SIZE_64B ((uint8_t)0x05U) +#define ARM_MPU_REGION_SIZE_128B ((uint8_t)0x06U) +#define ARM_MPU_REGION_SIZE_256B ((uint8_t)0x07U) +#define ARM_MPU_REGION_SIZE_512B ((uint8_t)0x08U) +#define ARM_MPU_REGION_SIZE_1KB ((uint8_t)0x09U) +#define ARM_MPU_REGION_SIZE_2KB ((uint8_t)0x0AU) +#define ARM_MPU_REGION_SIZE_4KB ((uint8_t)0x0BU) +#define ARM_MPU_REGION_SIZE_8KB ((uint8_t)0x0CU) +#define ARM_MPU_REGION_SIZE_16KB ((uint8_t)0x0DU) +#define ARM_MPU_REGION_SIZE_32KB ((uint8_t)0x0EU) +#define ARM_MPU_REGION_SIZE_64KB ((uint8_t)0x0FU) +#define ARM_MPU_REGION_SIZE_128KB ((uint8_t)0x10U) +#define ARM_MPU_REGION_SIZE_256KB ((uint8_t)0x11U) +#define ARM_MPU_REGION_SIZE_512KB ((uint8_t)0x12U) +#define ARM_MPU_REGION_SIZE_1MB ((uint8_t)0x13U) +#define ARM_MPU_REGION_SIZE_2MB ((uint8_t)0x14U) +#define ARM_MPU_REGION_SIZE_4MB ((uint8_t)0x15U) +#define ARM_MPU_REGION_SIZE_8MB ((uint8_t)0x16U) +#define ARM_MPU_REGION_SIZE_16MB ((uint8_t)0x17U) +#define ARM_MPU_REGION_SIZE_32MB ((uint8_t)0x18U) +#define ARM_MPU_REGION_SIZE_64MB ((uint8_t)0x19U) +#define ARM_MPU_REGION_SIZE_128MB ((uint8_t)0x1AU) +#define ARM_MPU_REGION_SIZE_256MB ((uint8_t)0x1BU) +#define ARM_MPU_REGION_SIZE_512MB ((uint8_t)0x1CU) +#define ARM_MPU_REGION_SIZE_1GB ((uint8_t)0x1DU) +#define ARM_MPU_REGION_SIZE_2GB ((uint8_t)0x1EU) +#define ARM_MPU_REGION_SIZE_4GB ((uint8_t)0x1FU) + +#define ARM_MPU_AP_NONE 0U +#define ARM_MPU_AP_PRIV 1U +#define ARM_MPU_AP_URO 2U +#define ARM_MPU_AP_FULL 3U +#define ARM_MPU_AP_PRO 5U +#define ARM_MPU_AP_RO 6U + +/** MPU Region Base Address Register Value +* +* \param Region The region to be configured, number 0 to 15. +* \param BaseAddress The base address for the region. +*/ +#define ARM_MPU_RBAR(Region, BaseAddress) \ + (((BaseAddress) & MPU_RBAR_ADDR_Msk) | \ + ((Region) & MPU_RBAR_REGION_Msk) | \ + (MPU_RBAR_VALID_Msk)) + +/** +* MPU Region Attribute and Size Register Value +* +* \param DisableExec Instruction access disable bit, 1= disable instruction fetches. +* \param AccessPermission Data access permissions, allows you to configure read/write access for User and Privileged mode. +* \param TypeExtField Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral. +* \param IsShareable Region is shareable between multiple bus masters. +* \param IsCacheable Region is cacheable, i.e. its value may be kept in cache. +* \param IsBufferable Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy. +* \param SubRegionDisable Sub-region disable field. +* \param Size Region size of the region to be configured, for example 4K, 8K. +*/ +#define ARM_MPU_RASR(DisableExec, AccessPermission, TypeExtField, IsShareable, IsCacheable, IsBufferable, SubRegionDisable, Size) \ + ((((DisableExec ) << MPU_RASR_XN_Pos) & MPU_RASR_XN_Msk) | \ + (((AccessPermission) << MPU_RASR_AP_Pos) & MPU_RASR_AP_Msk) | \ + (((TypeExtField ) << MPU_RASR_TEX_Pos) & MPU_RASR_TEX_Msk) | \ + (((IsShareable ) << MPU_RASR_S_Pos) & MPU_RASR_S_Msk) | \ + (((IsCacheable ) << MPU_RASR_C_Pos) & MPU_RASR_C_Msk) | \ + (((IsBufferable ) << MPU_RASR_B_Pos) & MPU_RASR_B_Msk) | \ + (((SubRegionDisable) << MPU_RASR_SRD_Pos) & MPU_RASR_SRD_Msk) | \ + (((Size ) << MPU_RASR_SIZE_Pos) & MPU_RASR_SIZE_Msk) | \ + (MPU_RASR_ENABLE_Msk)) + + +/** +* Struct for a single MPU Region +*/ +typedef struct { + uint32_t RBAR; //!< The region base address register value (RBAR) + uint32_t RASR; //!< The region attribute and size register value (RASR) \ref MPU_RASR +} ARM_MPU_Region_t; + +/** Enable the MPU. +* \param MPU_Control Default access permissions for unconfigured regions. +*/ +__STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control) +{ + __DSB(); + __ISB(); + MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk; +#ifdef SCB_SHCSR_MEMFAULTENA_Msk + SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk; +#endif +} + +/** Disable the MPU. +*/ +__STATIC_INLINE void ARM_MPU_Disable(void) +{ + __DSB(); + __ISB(); +#ifdef SCB_SHCSR_MEMFAULTENA_Msk + SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk; +#endif + MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk; +} + +/** Clear and disable the given MPU region. +* \param rnr Region number to be cleared. +*/ +__STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr) +{ + MPU->RNR = rnr; + MPU->RASR = 0U; +} + +/** Configure an MPU region. +* \param rbar Value for RBAR register. +* \param rsar Value for RSAR register. +*/ +__STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rbar, uint32_t rasr) +{ + MPU->RBAR = rbar; + MPU->RASR = rasr; +} + +/** Configure the given MPU region. +* \param rnr Region number to be configured. +* \param rbar Value for RBAR register. +* \param rsar Value for RSAR register. +*/ +__STATIC_INLINE void ARM_MPU_SetRegionEx(uint32_t rnr, uint32_t rbar, uint32_t rasr) +{ + MPU->RNR = rnr; + MPU->RBAR = rbar; + MPU->RASR = rasr; +} + +/** Memcopy with strictly ordered memory access, e.g. for register targets. +* \param dst Destination data is copied to. +* \param src Source data is copied from. +* \param len Amount of data words to be copied. +*/ +__STATIC_INLINE void orderedCpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len) +{ + uint32_t i; + for (i = 0U; i < len; ++i) + { + dst[i] = src[i]; + } +} + +/** Load the given number of MPU regions from a table. +* \param table Pointer to the MPU configuration table. +* \param cnt Amount of regions to be configured. +*/ +__STATIC_INLINE void ARM_MPU_Load(ARM_MPU_Region_t const* table, uint32_t cnt) +{ + const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U; + while (cnt > MPU_TYPE_RALIASES) { + orderedCpy(&(MPU->RBAR), &(table->RBAR), MPU_TYPE_RALIASES*rowWordSize); + table += MPU_TYPE_RALIASES; + cnt -= MPU_TYPE_RALIASES; + } + orderedCpy(&(MPU->RBAR), &(table->RBAR), cnt*rowWordSize); +} + +#endif diff --git a/Ubiquitous/XiZi/board/xidatong/third_party_driver/CMSIS/LICENSE.txt b/Ubiquitous/XiZi/board/xidatong/third_party_driver/CMSIS/LICENSE.txt new file mode 100644 index 0000000..8dada3e --- /dev/null +++ b/Ubiquitous/XiZi/board/xidatong/third_party_driver/CMSIS/LICENSE.txt @@ -0,0 +1,201 @@ + Apache License + Version 2.0, January 2004 + http://www.apache.org/licenses/ + + TERMS AND CONDITIONS FOR USE, REPRODUCTION, AND DISTRIBUTION + + 1. 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b/Ubiquitous/XiZi/board/xidatong/third_party_driver/Kconfig @@ -0,0 +1,50 @@ +menuconfig BSP_USING_LPUART + bool "Using UART device" + default y + select RESOURCES_SERIAL + if BSP_USING_LPUART + source "$BSP_DIR/third_party_driver/uart/Kconfig" + endif + +menuconfig BSP_USING_CH438 + bool "Using CH438 device" + default n + if BSP_USING_CH438 + source "$BSP_DIR/third_party_driver/ch438/Kconfig" + endif + +menuconfig BSP_USING_GPIO + bool "Using GPIO device " + default y + select RESOURCES_PIN + if BSP_USING_GPIO + source "$BSP_DIR/third_party_driver/gpio/Kconfig" + endif + +menuconfig BSP_USING_LWIP + bool "Using LwIP device" + default n + select RESOURCES_LWIP + +menuconfig BSP_USING_SEMC + bool "Using SEMC device" + default n + if BSP_USING_SEMC + source "$BSP_DIR/third_party_driver/semc/Kconfig" + endif + +menuconfig BSP_USING_SDIO + bool "Using SD card device" + default n + select RESOURCES_SDIO + if BSP_USING_SDIO + source "$BSP_DIR/third_party_driver/sdio/Kconfig" + endif + +menuconfig BSP_USING_USB + bool "Using USB device" + default n + select RESOURCES_USB + if BSP_USING_USB + source "$BSP_DIR/third_party_driver/usb/Kconfig" + endif diff --git a/Ubiquitous/XiZi/board/xidatong/third_party_driver/Makefile b/Ubiquitous/XiZi/board/xidatong/third_party_driver/Makefile new file mode 100644 index 0000000..b439cc9 --- /dev/null +++ b/Ubiquitous/XiZi/board/xidatong/third_party_driver/Makefile @@ -0,0 +1,27 @@ +SRC_DIR := common gpio + +ifeq ($(CONFIG_BSP_USING_LWIP),y) + SRC_DIR += ethernet +endif + +ifeq ($(CONFIG_BSP_USING_SEMC),y) + SRC_DIR += semc +endif + +ifeq ($(CONFIG_BSP_USING_LPUART),y) + SRC_DIR += uart +endif + +ifeq ($(CONFIG_BSP_USING_CH438),y) + SRC_DIR += ch438 +endif + +ifeq ($(CONFIG_BSP_USING_SDIO),y) + SRC_DIR += sdio +endif + +ifeq ($(CONFIG_BSP_USING_USB),y) + SRC_DIR += usb +endif + +include $(KERNEL_ROOT)/compiler.mk diff --git a/Ubiquitous/XiZi/board/xidatong/third_party_driver/ch438/Kconfig b/Ubiquitous/XiZi/board/xidatong/third_party_driver/ch438/Kconfig new file mode 100644 index 0000000..389b675 --- /dev/null +++ b/Ubiquitous/XiZi/board/xidatong/third_party_driver/ch438/Kconfig @@ -0,0 +1,39 @@ +config CH438_BUS_NAME + string + default "extuart" + +config CH438_DRIVER_NAME + string + default "extuart_drv" + +config CH438_DEVICE_NAME_0 + string + default "extuart_dev0" + +config CH438_DEVICE_NAME_1 + string + default "extuart_dev1" + +config CH438_DEVICE_NAME_2 + string + default "extuart_dev2" + +config CH438_DEVICE_NAME_3 + string + default "extuart_dev3" + +config CH438_DEVICE_NAME_4 + string + default "extuart_dev4" + +config CH438_DEVICE_NAME_5 + string + default "extuart_dev5" + +config CH438_DEVICE_NAME_6 + string + default "extuart_dev6" + +config CH438_DEVICE_NAME_7 + string + default "extuart_dev7" diff --git a/Ubiquitous/XiZi/board/xidatong/third_party_driver/ch438/Makefile b/Ubiquitous/XiZi/board/xidatong/third_party_driver/ch438/Makefile new file mode 100644 index 0000000..4796857 --- /dev/null +++ b/Ubiquitous/XiZi/board/xidatong/third_party_driver/ch438/Makefile @@ -0,0 +1,4 @@ +SRC_FILES := connect_ch438.c + + +include $(KERNEL_ROOT)/compiler.mk diff --git a/Ubiquitous/XiZi/board/xidatong/third_party_driver/ch438/connect_ch438.c b/Ubiquitous/XiZi/board/xidatong/third_party_driver/ch438/connect_ch438.c new file mode 100644 index 0000000..a022c32 --- /dev/null +++ b/Ubiquitous/XiZi/board/xidatong/third_party_driver/ch438/connect_ch438.c @@ -0,0 +1,1371 @@ +/* +* Copyright (c) 2020 AIIT XUOS Lab +* XiUOS is licensed under Mulan PSL v2. +* You can use this software according to the terms and conditions of the Mulan PSL v2. +* You may obtain a copy of Mulan PSL v2 at: +* http://license.coscl.org.cn/MulanPSL2 +* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, +* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, +* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. +* See the Mulan PSL v2 for more details. +*/ + +/** +* @file connect_ch438.c +* @brief support to register ch438 pointer and function +* @version 2.0 +* @author AIIT XUOS Lab +* @date 2022-03-17 +*/ + +#include + +static const uint8 offset_addr[] = {0x00,0x10,0x20,0x30,0x08,0x18,0x28,0x38,}; /* uart offset address*/ +static const uint8 interrupt_num[8] = {0x01,0x02,0x04,0x08,0x10,0x20,0x40,0x80,}; /* SSR register data*/ +static BusType ch438_pin; +static int ch438_sem = NONE; + +static void Ch438Irq(void *parameter) +{ + KSemaphoreAbandon(ch438_sem); +} + +/** + * The time delay function. + * + * @param microseconds. + */ +static void ImxrtUdelay(uint32 us) +{ + uint32 ticks; + uint32 told, tnow, tcnt = 0; + uint32 reload = SysTick->LOAD; + + ticks = us * reload / (1000000 / TICK_PER_SECOND); + told = SysTick->VAL; + while (1) { + tnow = SysTick->VAL; + if (tnow != told) { + if (tnow < told) { + tcnt += told - tnow; + } else { + tcnt += reload - tnow + told; + } + + told = tnow; + if (tcnt >= ticks) { + break; + } + } + } +} + +void CH438SetOutput(void) +{ + struct PinParam pin_cfg; + int ret = 0; + + struct BusConfigureInfo configure_info; + configure_info.configure_cmd = OPE_CFG; + configure_info.private_data = (void *)&pin_cfg; + + pin_cfg.cmd = GPIO_CONFIG_MODE; + pin_cfg.pin = CH438_D0_PIN; + pin_cfg.mode = GPIO_CFG_OUTPUT; + + ret = BusDrvConfigure(ch438_pin->owner_driver, &configure_info); + if (ret != EOK) { + KPrintf("config CH438_D0_PIN pin %d failed!\n", CH438_D0_PIN); + return ; + } + + pin_cfg.pin = CH438_D1_PIN; + ret = BusDrvConfigure(ch438_pin->owner_driver, &configure_info); + if (ret != EOK) { + KPrintf("config CH438_D1_PIN pin %d failed!\n", CH438_D1_PIN); + return ; + } + + pin_cfg.pin = CH438_D2_PIN; + ret = BusDrvConfigure(ch438_pin->owner_driver, &configure_info); + if (ret != EOK) { + KPrintf("config CH438_D2_PIN pin %d failed!\n", CH438_D2_PIN); + return ; + } + + pin_cfg.pin = CH438_D3_PIN; + ret = BusDrvConfigure(ch438_pin->owner_driver, &configure_info); + if (ret != EOK) { + KPrintf("config CH438_D3_PIN pin %d failed!\n", CH438_D3_PIN); + return ; + } + + pin_cfg.pin = CH438_D4_PIN; + ret = BusDrvConfigure(ch438_pin->owner_driver, &configure_info); + if (ret != EOK) { + KPrintf("config CH438_D4_PIN pin %d failed!\n", CH438_D4_PIN); + return ; + } + + pin_cfg.pin = CH438_D5_PIN; + ret = BusDrvConfigure(ch438_pin->owner_driver, &configure_info); + if (ret != EOK) { + KPrintf("config CH438_D5_PIN pin %d failed!\n", CH438_D5_PIN); + return ; + } + + pin_cfg.pin = CH438_D6_PIN; + ret = BusDrvConfigure(ch438_pin->owner_driver, &configure_info); + if (ret != EOK) { + KPrintf("config CH438_D6_PIN pin %d failed!\n", CH438_D6_PIN); + return ; + } + + pin_cfg.pin = CH438_D7_PIN; + ret = BusDrvConfigure(ch438_pin->owner_driver, &configure_info); + if (ret != EOK) { + KPrintf("config CH438_D7_PIN pin %d failed!\n", CH438_D7_PIN); + return ; + } +} + +void CH438SetInput(void) +{ + struct PinParam pin_cfg; + int ret = 0; + + struct BusConfigureInfo configure_info; + configure_info.configure_cmd = OPE_CFG; + configure_info.private_data = (void *)&pin_cfg; + + pin_cfg.cmd = GPIO_CONFIG_MODE; + pin_cfg.pin = CH438_D0_PIN; + pin_cfg.mode = GPIO_CFG_INPUT_PULLUP; + ret = BusDrvConfigure(ch438_pin->owner_driver, &configure_info); + if (ret != EOK) { + KPrintf("config CH438_D0_PIN pin %d INPUT_PULLUP failed!\n", CH438_D0_PIN); + return ; + } + + pin_cfg.pin = CH438_D1_PIN; + ret = BusDrvConfigure(ch438_pin->owner_driver, &configure_info); + if (ret != EOK) { + KPrintf("config CH438_D1_PIN pin %d INPUT_PULLUP failed!\n", CH438_D1_PIN); + return ; + } + + pin_cfg.pin = CH438_D2_PIN; + ret = BusDrvConfigure(ch438_pin->owner_driver, &configure_info); + if (ret != EOK) { + KPrintf("config CH438_D2_PIN pin %d INPUT_PULLUP failed!\n", CH438_D2_PIN); + return ; + } + + pin_cfg.pin = CH438_D3_PIN; + ret = BusDrvConfigure(ch438_pin->owner_driver, &configure_info); + if (ret != EOK) { + KPrintf("config CH438_D3_PIN pin %d INPUT_PULLUP failed!\n", CH438_D3_PIN); + return ; + } + + pin_cfg.pin = CH438_D4_PIN; + ret = BusDrvConfigure(ch438_pin->owner_driver, &configure_info); + if (ret != EOK) { + KPrintf("config CH438_D4_PIN pin %d INPUT_PULLUP failed!\n", CH438_D4_PIN); + return ; + } + + pin_cfg.pin = CH438_D5_PIN; + ret = BusDrvConfigure(ch438_pin->owner_driver, &configure_info); + if (ret != EOK) { + KPrintf("config CH438_D5_PIN pin %d INPUT_PULLUP failed!\n", CH438_D5_PIN); + return ; + } + + pin_cfg.pin = CH438_D6_PIN; + ret = BusDrvConfigure(ch438_pin->owner_driver, &configure_info); + if (ret != EOK) { + KPrintf("config CH438_D6_PIN pin %d INPUT_PULLUP failed!\n", CH438_D6_PIN); + return ; + } + + pin_cfg.pin = CH438_D7_PIN; + ret = BusDrvConfigure(ch438_pin->owner_driver, &configure_info); + if (ret != EOK) { + KPrintf("config CH438_D7_PIN pin %d INPUT_PULLUP failed!\n", CH438_D7_PIN); + return ; + } +} + +/********************************************************************************************************* +** Function name: ReadCH438Data +** Function: read data from CH438 +** input: address +** +** output: data +** +** date: 2011.8.26 +**------------------------------------------------------------------------------------------------------- +** modify: +** date: +**------------------------------------------------------------------------------------------------------- +********************************************************************************************************/ +uint8 ReadCH438Data( uint8 addr ) +{ +//read data api + +//ALE WR RD is high level when not busy, when reading data, put address on the serial port and put ALE low level for a few clock + +//switch input pin, put RD low level, delay a few clock, read the data from the serial port + +//put RD and ALE high level + uint8 dat; + struct PinStat pin_stat; + struct BusBlockWriteParam write_param; + struct BusBlockReadParam read_param; + write_param.buffer = (void *)&pin_stat; + read_param.buffer = (void *)&pin_stat; + + pin_stat.val = GPIO_HIGH; + + pin_stat.pin = CH438_NWR_PIN; + BusDevWriteData(ch438_pin->owner_haldev, &write_param); + + pin_stat.pin = CH438_NRD_PIN; + BusDevWriteData(ch438_pin->owner_haldev, &write_param); + + pin_stat.pin = CH438_ALE_PIN; + BusDevWriteData(ch438_pin->owner_haldev, &write_param); + + CH438SetOutput(); + ImxrtUdelay(1); + + if (addr &0x80) { + pin_stat.val = GPIO_HIGH; + pin_stat.pin = CH438_D7_PIN; + BusDevWriteData(ch438_pin->owner_haldev, &write_param); + } else { + pin_stat.val = GPIO_LOW; + pin_stat.pin = CH438_D7_PIN; + BusDevWriteData(ch438_pin->owner_haldev, &write_param); + } + + if (addr &0x40) { + pin_stat.val = GPIO_HIGH; + pin_stat.pin = CH438_D6_PIN; + BusDevWriteData(ch438_pin->owner_haldev, &write_param); + } else { + pin_stat.val = GPIO_LOW; + pin_stat.pin = CH438_D6_PIN; + BusDevWriteData(ch438_pin->owner_haldev, &write_param); + } + + if (addr &0x20) { + pin_stat.val = GPIO_HIGH; + pin_stat.pin = CH438_D5_PIN; + BusDevWriteData(ch438_pin->owner_haldev, &write_param); + } else { + pin_stat.val = GPIO_LOW; + pin_stat.pin = CH438_D5_PIN; + BusDevWriteData(ch438_pin->owner_haldev, &write_param); + } + + if (addr &0x10) { + pin_stat.val = GPIO_HIGH; + pin_stat.pin = CH438_D4_PIN; + BusDevWriteData(ch438_pin->owner_haldev, &write_param); + } else { + pin_stat.val = GPIO_LOW; + pin_stat.pin = CH438_D4_PIN; + BusDevWriteData(ch438_pin->owner_haldev, &write_param); + } + + if (addr &0x08) { + pin_stat.val = GPIO_HIGH; + pin_stat.pin = CH438_D3_PIN; + BusDevWriteData(ch438_pin->owner_haldev, &write_param); + } else { + pin_stat.val = GPIO_LOW; + pin_stat.pin = CH438_D3_PIN; + BusDevWriteData(ch438_pin->owner_haldev, &write_param); + } + + if (addr &0x04) { + pin_stat.val = GPIO_HIGH; + pin_stat.pin = CH438_D2_PIN; + BusDevWriteData(ch438_pin->owner_haldev, &write_param); + } else { + pin_stat.val = GPIO_LOW; + pin_stat.pin = CH438_D2_PIN; + BusDevWriteData(ch438_pin->owner_haldev, &write_param); + } + + if (addr &0x02) { + pin_stat.val = GPIO_HIGH; + pin_stat.pin = CH438_D1_PIN; + BusDevWriteData(ch438_pin->owner_haldev, &write_param); + } else { + pin_stat.val = GPIO_LOW; + pin_stat.pin = CH438_D1_PIN; + BusDevWriteData(ch438_pin->owner_haldev, &write_param); + } + + if (addr &0x01) { + pin_stat.val = GPIO_HIGH; + pin_stat.pin = CH438_D0_PIN; + BusDevWriteData(ch438_pin->owner_haldev, &write_param); + } else { + pin_stat.val = GPIO_LOW; + pin_stat.pin = CH438_D0_PIN; + BusDevWriteData(ch438_pin->owner_haldev, &write_param); + } + + ImxrtUdelay(1); + + pin_stat.val = GPIO_LOW; + pin_stat.pin = CH438_ALE_PIN; + BusDevWriteData(ch438_pin->owner_haldev, &write_param); + + ImxrtUdelay(1); + + CH438SetInput(); + ImxrtUdelay(1); + + pin_stat.val = GPIO_LOW; + pin_stat.pin = CH438_NRD_PIN; + BusDevWriteData(ch438_pin->owner_haldev, &write_param); + + ImxrtUdelay(1); + + dat = 0; + + pin_stat.pin = CH438_D7_PIN; + if(BusDevReadData(ch438_pin->owner_haldev, &read_param)) + dat |= 0x80; + + pin_stat.pin = CH438_D6_PIN; + if (BusDevReadData(ch438_pin->owner_haldev, &read_param)) + dat |= 0x40; + + pin_stat.pin = CH438_D5_PIN; + if (BusDevReadData(ch438_pin->owner_haldev, &read_param)) + dat |= 0x20; + + pin_stat.pin = CH438_D4_PIN; + if (BusDevReadData(ch438_pin->owner_haldev, &read_param)) + dat |= 0x10; + + pin_stat.pin = CH438_D3_PIN; + if (BusDevReadData(ch438_pin->owner_haldev, &read_param)) + dat |= 0x08; + + pin_stat.pin = CH438_D2_PIN; + if (BusDevReadData(ch438_pin->owner_haldev, &read_param)) + dat |= 0x04; + + pin_stat.pin = CH438_D1_PIN; + if (BusDevReadData(ch438_pin->owner_haldev, &read_param)) + dat |= 0x02; + + pin_stat.pin = CH438_D0_PIN; + if (BusDevReadData(ch438_pin->owner_haldev, &read_param)) + dat |= 0x01; + + pin_stat.val = GPIO_HIGH; + pin_stat.pin = CH438_NRD_PIN; + BusDevWriteData(ch438_pin->owner_haldev, &write_param); + + pin_stat.val = GPIO_HIGH; + pin_stat.pin = CH438_ALE_PIN; + BusDevWriteData(ch438_pin->owner_haldev, &write_param); + + ImxrtUdelay(1); + + return dat; +} + +void WriteCH438Data(uint8 addr, uint8 dat) +{ + struct PinStat pin_stat; + struct BusBlockWriteParam write_param; + write_param.buffer = (void *)&pin_stat; + + pin_stat.val = GPIO_HIGH; + pin_stat.pin = CH438_ALE_PIN; + BusDevWriteData(ch438_pin->owner_haldev, &write_param); + + pin_stat.val = GPIO_HIGH; + pin_stat.pin = CH438_NRD_PIN; + BusDevWriteData(ch438_pin->owner_haldev, &write_param); + + pin_stat.val = GPIO_HIGH; + pin_stat.pin = CH438_NWR_PIN; + BusDevWriteData(ch438_pin->owner_haldev, &write_param); + + CH438SetOutput(); + ImxrtUdelay(1); + + if (addr &0x80) { + pin_stat.val = GPIO_HIGH; + pin_stat.pin = CH438_D7_PIN; + BusDevWriteData(ch438_pin->owner_haldev, &write_param); + } else { + pin_stat.val = GPIO_LOW; + pin_stat.pin = CH438_D7_PIN; + BusDevWriteData(ch438_pin->owner_haldev, &write_param); + } + + if (addr &0x40) { + pin_stat.val = GPIO_HIGH; + pin_stat.pin = CH438_D6_PIN; + BusDevWriteData(ch438_pin->owner_haldev, &write_param); + } else { + pin_stat.val = GPIO_LOW; + pin_stat.pin = CH438_D6_PIN; + BusDevWriteData(ch438_pin->owner_haldev, &write_param); + } + + if (addr &0x20) { + pin_stat.val = GPIO_HIGH; + pin_stat.pin = CH438_D5_PIN; + BusDevWriteData(ch438_pin->owner_haldev, &write_param); + } else { + pin_stat.val = GPIO_LOW; + pin_stat.pin = CH438_D5_PIN; + BusDevWriteData(ch438_pin->owner_haldev, &write_param); + } + + if (addr &0x10) { + pin_stat.val = GPIO_HIGH; + pin_stat.pin = CH438_D4_PIN; + BusDevWriteData(ch438_pin->owner_haldev, &write_param); + } else { + pin_stat.val = GPIO_LOW; + pin_stat.pin = CH438_D4_PIN; + BusDevWriteData(ch438_pin->owner_haldev, &write_param); + } + + if (addr &0x08) { + pin_stat.val = GPIO_HIGH; + pin_stat.pin = CH438_D3_PIN; + BusDevWriteData(ch438_pin->owner_haldev, &write_param); + } else { + pin_stat.val = GPIO_LOW; + pin_stat.pin = CH438_D3_PIN; + BusDevWriteData(ch438_pin->owner_haldev, &write_param); + } + + if (addr &0x04) { + pin_stat.val = GPIO_HIGH; + pin_stat.pin = CH438_D2_PIN; + BusDevWriteData(ch438_pin->owner_haldev, &write_param); + } else { + pin_stat.val = GPIO_LOW; + pin_stat.pin = CH438_D2_PIN; + BusDevWriteData(ch438_pin->owner_haldev, &write_param); + } + + if (addr &0x02) { + pin_stat.val = GPIO_HIGH; + pin_stat.pin = CH438_D1_PIN; + BusDevWriteData(ch438_pin->owner_haldev, &write_param); + } else { + pin_stat.val = GPIO_LOW; + pin_stat.pin = CH438_D1_PIN; + BusDevWriteData(ch438_pin->owner_haldev, &write_param); + } + + if (addr &0x01) { + pin_stat.val = GPIO_HIGH; + pin_stat.pin = CH438_D0_PIN; + BusDevWriteData(ch438_pin->owner_haldev, &write_param); + } else { + pin_stat.val = GPIO_LOW; + pin_stat.pin = CH438_D0_PIN; + BusDevWriteData(ch438_pin->owner_haldev, &write_param); + } + + ImxrtUdelay(1); + + pin_stat.val = GPIO_LOW; + pin_stat.pin = CH438_ALE_PIN; + BusDevWriteData(ch438_pin->owner_haldev, &write_param); + + ImxrtUdelay(1); + + if (dat &0x80) { + pin_stat.val = GPIO_HIGH; + pin_stat.pin = CH438_D7_PIN; + BusDevWriteData(ch438_pin->owner_haldev, &write_param); + } else { + pin_stat.val = GPIO_LOW; + pin_stat.pin = CH438_D7_PIN; + BusDevWriteData(ch438_pin->owner_haldev, &write_param); + } + + if (dat &0x40) { + pin_stat.val = GPIO_HIGH; + pin_stat.pin = CH438_D6_PIN; + BusDevWriteData(ch438_pin->owner_haldev, &write_param); + } else { + pin_stat.val = GPIO_LOW; + pin_stat.pin = CH438_D6_PIN; + BusDevWriteData(ch438_pin->owner_haldev, &write_param); + } + + if (dat &0x20) { + pin_stat.val = GPIO_HIGH; + pin_stat.pin = CH438_D5_PIN; + BusDevWriteData(ch438_pin->owner_haldev, &write_param); + } else { + pin_stat.val = GPIO_LOW; + pin_stat.pin = CH438_D5_PIN; + BusDevWriteData(ch438_pin->owner_haldev, &write_param); + } + + if (dat &0x10) { + pin_stat.val = GPIO_HIGH; + pin_stat.pin = CH438_D4_PIN; + BusDevWriteData(ch438_pin->owner_haldev, &write_param); + } else { + pin_stat.val = GPIO_LOW; + pin_stat.pin = CH438_D4_PIN; + BusDevWriteData(ch438_pin->owner_haldev, &write_param); + } + + if (dat &0x08) { + pin_stat.val = GPIO_HIGH; + pin_stat.pin = CH438_D3_PIN; + BusDevWriteData(ch438_pin->owner_haldev, &write_param); + } else { + pin_stat.val = GPIO_LOW; + pin_stat.pin = CH438_D3_PIN; + BusDevWriteData(ch438_pin->owner_haldev, &write_param); + } + + if (dat &0x04) { + pin_stat.val = GPIO_HIGH; + pin_stat.pin = CH438_D2_PIN; + BusDevWriteData(ch438_pin->owner_haldev, &write_param); + } else { + pin_stat.val = GPIO_LOW; + pin_stat.pin = CH438_D2_PIN; + BusDevWriteData(ch438_pin->owner_haldev, &write_param); + } + + if (dat &0x02) { + pin_stat.val = GPIO_HIGH; + pin_stat.pin = CH438_D1_PIN; + BusDevWriteData(ch438_pin->owner_haldev, &write_param); + } else { + pin_stat.val = GPIO_LOW; + pin_stat.pin = CH438_D1_PIN; + BusDevWriteData(ch438_pin->owner_haldev, &write_param); + } + + if (dat &0x01) { + pin_stat.val = GPIO_HIGH; + pin_stat.pin = CH438_D0_PIN; + BusDevWriteData(ch438_pin->owner_haldev, &write_param); + } else { + pin_stat.val = GPIO_LOW; + pin_stat.pin = CH438_D0_PIN; + BusDevWriteData(ch438_pin->owner_haldev, &write_param); + } + + ImxrtUdelay(1); + + pin_stat.val = GPIO_LOW; + pin_stat.pin = CH438_NWR_PIN; + BusDevWriteData(ch438_pin->owner_haldev, &write_param); + + ImxrtUdelay(1); + + pin_stat.val = GPIO_HIGH; + pin_stat.pin = CH438_NWR_PIN; + BusDevWriteData(ch438_pin->owner_haldev, &write_param); + + pin_stat.val = GPIO_HIGH; + pin_stat.pin = CH438_ALE_PIN; + BusDevWriteData(ch438_pin->owner_haldev, &write_param); + + ImxrtUdelay(1); + + CH438SetInput(); + + return; +} + +/********************************************************************************************************* +** Function name: WriteCH438Block +** Function: write data to CH438 +** input: CH438 register address, data block length, data cache address +** +** output: +** +** date: 2011.8.26 +**------------------------------------------------------------------------------------------------------- +** modify: +** date: +**------------------------------------------------------------------------------------------------------- +********************************************************************************************************/ +void WriteCH438Block(uint8 maddr, uint8 mlen, uint8 *mbuf) +{ + while (mlen--) { + WriteCH438Data(maddr, *mbuf++); + } +} + +/********************************************************************************************************* +** Function name: Ch438UartSend +** Function: active FIFO mode, CH438 send multibyte data by uart 0, max length is 128 bytes a single time +** input: send data cache address, send data length +** +** output: +** +** date: 2011.8.26. +**------------------------------------------------------------------------------------------------------- +** modify: +** date: +**------------------------------------------------------------------------------------------------------- +********************************************************************************************************/ +void Ch438UartSend(uint8 ext_uart_no, uint8 *data, uint16 Num) +{ + uint8 REG_LSR_ADDR,REG_THR_ADDR; + + REG_LSR_ADDR = offset_addr[ext_uart_no] | REG_LSR0_ADDR; + REG_THR_ADDR = offset_addr[ext_uart_no] | REG_THR0_ADDR; + + while (1) { + while((ReadCH438Data(REG_LSR_ADDR) & BIT_LSR_TEMT) == 0); /* wait for sending data done, THR and TSR is NULL */ + + if (Num <= 128) { + WriteCH438Block(REG_THR_ADDR, Num, data); + break; + } else { + WriteCH438Block(REG_THR_ADDR, 128, data); + Num -= 128; + data += 128; + } + } +} + +/********************************************************************************************************* +** Function name: Ch438UartRcv +** Function: forbidden FIFO mode, CH438 receive multibyte data from uart 0 +** input: recv data address +** +** output: recv data length +** +** date: 2011.8.26 +**------------------------------------------------------------------------------------------------------- +** modify: +** date: +**------------------------------------------------------------------------------------------------------- +********************************************************************************************************/ +uint8 Ch438UartRcv(uint8 ext_uart_no, uint8 *buf, x_size_t size) +{ + uint8 rcv_num = 0; + uint8 dat = 0; + uint8 REG_LSR_ADDR,REG_RBR_ADDR; + uint8 *read_buffer; + x_size_t buffer_index = 0; + + read_buffer = buf; + + REG_LSR_ADDR = offset_addr[ext_uart_no] | REG_LSR0_ADDR; + REG_RBR_ADDR = offset_addr[ext_uart_no] | REG_RBR0_ADDR; + + while ((ReadCH438Data(REG_LSR_ADDR) & BIT_LSR_DATARDY) == 0); /* wait for data is ready */ + + while (((ReadCH438Data(REG_LSR_ADDR) & BIT_LSR_DATARDY) == 0x01) && (size != 0)) { + dat = ReadCH438Data(REG_RBR_ADDR); + + *read_buffer = dat; + read_buffer++; + buffer_index++; + + if (CH438_BUFFSIZE == buffer_index) { + buffer_index = 0; + read_buffer = buf; + } + + rcv_num = rcv_num + 1; + --size; + } + + return rcv_num; +} + +static void Timeout438Proc(void *parameter) +{ + uint8_t rbr,lsr; + + while( ( ReadCH438Data( REG_LSR0_ADDR ) & BIT_LSR_DATARDY ) == 0x01 ) { + rbr = ReadCH438Data( REG_RBR0_ADDR ); + KPrintf("0.RBR=%02x\r\n",rbr); + } + + while( ( ReadCH438Data( REG_LSR1_ADDR ) & BIT_LSR_DATARDY ) == 0x01 ) { + rbr = ReadCH438Data( REG_RBR1_ADDR ); + KPrintf("1.RBR=%02x\r\n",rbr); + } + + while( ( ReadCH438Data( REG_LSR2_ADDR ) & BIT_LSR_DATARDY ) == 0x01 ) { + rbr = ReadCH438Data( REG_RBR2_ADDR ); + KPrintf("2.RBR=%02x\r\n",rbr); + } + + while( ( ReadCH438Data( REG_LSR3_ADDR ) & BIT_LSR_DATARDY ) == 0x01 ) { + rbr = ReadCH438Data( REG_RBR3_ADDR ); + KPrintf("3.RBR=%02x\r\n",rbr); + } + + while( ( ReadCH438Data( REG_LSR4_ADDR ) & BIT_LSR_DATARDY ) == 0x01 ) { + rbr = ReadCH438Data( REG_RBR4_ADDR ); + KPrintf("4.RBR=%02x\r\n",rbr); + } + + while( ( ReadCH438Data( REG_LSR5_ADDR ) & BIT_LSR_DATARDY ) == 0x01 ) { + rbr = ReadCH438Data( REG_RBR5_ADDR ); + KPrintf("5.RBR=%02x\r\n",rbr); + } + + while( ( ReadCH438Data( REG_LSR6_ADDR ) & BIT_LSR_DATARDY ) == 0x01 ) { + rbr = ReadCH438Data( REG_RBR6_ADDR ); + KPrintf("6.RBR=%02x\r\n",rbr); + } + + while( ( ReadCH438Data( REG_LSR7_ADDR ) & BIT_LSR_DATARDY ) == 0x01 ) { + rbr = ReadCH438Data( REG_RBR7_ADDR ); + KPrintf("7.RBR=%02x\r\n",rbr); + } +} + +void Ch438PortInit(uint8 ext_uart_no, uint32 BaudRate ) +{ + uint32 div; + uint8 DLL,DLM,dlab; + uint8 REG_LCR_ADDR; + uint8 REG_DLL_ADDR; + uint8 REG_DLM_ADDR; + uint8 REG_IER_ADDR; + uint8 REG_MCR_ADDR; + uint8 REG_FCR_ADDR; + uint8 REG_RBR_ADDR; + uint8 REG_THR_ADDR; + uint8 REG_IIR_ADDR; + + REG_LCR_ADDR = offset_addr[ext_uart_no] | REG_LCR0_ADDR; + REG_DLL_ADDR = offset_addr[ext_uart_no] | REG_DLL0_ADDR; + REG_DLM_ADDR = offset_addr[ext_uart_no] | REG_DLM0_ADDR; + REG_IER_ADDR = offset_addr[ext_uart_no] | REG_IER0_ADDR; + REG_MCR_ADDR = offset_addr[ext_uart_no] | REG_MCR0_ADDR; + REG_FCR_ADDR = offset_addr[ext_uart_no] | REG_FCR0_ADDR; + REG_RBR_ADDR = offset_addr[ext_uart_no] | REG_RBR0_ADDR; + REG_THR_ADDR = offset_addr[ext_uart_no] | REG_THR0_ADDR; + REG_IIR_ADDR = offset_addr[ext_uart_no] | REG_IIR0_ADDR; + + WriteCH438Data(REG_IER_ADDR, BIT_IER_RESET); /* reset the uart */ + //MdelayKTask(50); + ImxrtUdelay(50000); + + dlab = ReadCH438Data(REG_IER_ADDR); + dlab &= 0xDF; + WriteCH438Data(REG_IER_ADDR, dlab); + + dlab = ReadCH438Data(REG_LCR_ADDR); + dlab |= 0x80; //set LCR register DLAB bit 1 + WriteCH438Data(REG_LCR_ADDR, dlab); + + div = (Fpclk >> 4) / BaudRate; + DLM = div >> 8; + DLL = div & 0xff; + WriteCH438Data(REG_DLL_ADDR, DLL); /* set bps */ + WriteCH438Data(REG_DLM_ADDR, DLM); + WriteCH438Data(REG_FCR_ADDR, BIT_FCR_RECVTG1 | BIT_FCR_RECVTG0 | BIT_FCR_FIFOEN); /* set FIFO mode, 112 bytes */ + + WriteCH438Data(REG_LCR_ADDR, BIT_LCR_WORDSZ1 | BIT_LCR_WORDSZ0); /* 8 bit word size, 1 bit stop bit, no crc */ + + WriteCH438Data(REG_IER_ADDR, BIT_IER_IERECV); /* enable interrupt */ + + WriteCH438Data(REG_MCR_ADDR, BIT_MCR_OUT2);// | BIT_MCR_RTS | BIT_MCR_DTR ); /* allow interrupt output, DTR and RTS is 1 */ + + WriteCH438Data(REG_FCR_ADDR, ReadCH438Data(REG_FCR_ADDR)| BIT_FCR_TFIFORST); /* release the data in FIFO */ +} + +void CH438PortInitParityCheck(uint8 ext_uart_no, uint32 BaudRate) +{ + uint32 div; + uint8 DLL,DLM,dlab; + uint8 REG_LCR_ADDR; + uint8 REG_DLL_ADDR; + uint8 REG_DLM_ADDR; + uint8 REG_IER_ADDR; + uint8 REG_MCR_ADDR; + uint8 REG_FCR_ADDR; + uint8 REG_RBR_ADDR; + uint8 REG_THR_ADDR; + uint8 REG_IIR_ADDR; + + REG_LCR_ADDR = offset_addr[ext_uart_no] | REG_LCR0_ADDR; + REG_DLL_ADDR = offset_addr[ext_uart_no] | REG_DLL0_ADDR; + REG_DLM_ADDR = offset_addr[ext_uart_no] | REG_DLM0_ADDR; + REG_IER_ADDR = offset_addr[ext_uart_no] | REG_IER0_ADDR; + REG_MCR_ADDR = offset_addr[ext_uart_no] | REG_MCR0_ADDR; + REG_FCR_ADDR = offset_addr[ext_uart_no] | REG_FCR0_ADDR; + REG_RBR_ADDR = offset_addr[ext_uart_no] | REG_RBR0_ADDR; + REG_THR_ADDR = offset_addr[ext_uart_no] | REG_THR0_ADDR; + REG_IIR_ADDR = offset_addr[ext_uart_no] | REG_IIR0_ADDR; + + WriteCH438Data(REG_IER_ADDR, BIT_IER_RESET); /* reset the uart */ + //MdelayKTask(50); + ImxrtUdelay(50000); + + dlab = ReadCH438Data(REG_IER_ADDR); + dlab &= 0xDF; + WriteCH438Data(REG_IER_ADDR, dlab); + + dlab = ReadCH438Data(REG_LCR_ADDR); + dlab |= 0x80; //set LCR register DLAB bit 1 + WriteCH438Data(REG_LCR_ADDR, dlab); + + div = (Fpclk >> 4) / BaudRate; + DLM = div >> 8; + DLL = div & 0xff; + WriteCH438Data(REG_DLL_ADDR, DLL); /* set bps */ + WriteCH438Data(REG_DLM_ADDR, DLM); + WriteCH438Data(REG_FCR_ADDR, BIT_FCR_RECVTG1 | BIT_FCR_FIFOEN); /* set FIFO mode, 64 bytes */ + + WriteCH438Data(REG_LCR_ADDR, BIT_LCR_WORDSZ1 | BIT_LCR_WORDSZ0 | BIT_LCR_PAREN | BIT_LCR_PARMODE0); /* 8 bit work size, 1 bit stop bit, even parity check */ + + WriteCH438Data(REG_IER_ADDR, BIT_IER_IERECV); /* enable interrupt */ + + WriteCH438Data(REG_MCR_ADDR, BIT_MCR_OUT2);// | BIT_MCR_RTS | BIT_MCR_DTR ); /* allow interrupt output, DTR and RTS is 1 */ + + WriteCH438Data(REG_FCR_ADDR, ReadCH438Data(REG_FCR_ADDR)| BIT_FCR_TFIFORST); /* release the data in FIFO */ +} + +static uint32 ImxrtCh438Configure(struct SerialCfgParam *ext_serial_cfg) +{ + NULL_PARAM_CHECK(ext_serial_cfg); + + switch (ext_serial_cfg->data_cfg.port_configure) + { + case PORT_CFG_INIT: + Ch438PortInit(ext_serial_cfg->data_cfg.ext_uart_no, ext_serial_cfg->data_cfg.serial_baud_rate); + break; + case PORT_CFG_PARITY_CHECK: + CH438PortInitParityCheck(ext_serial_cfg->data_cfg.ext_uart_no, ext_serial_cfg->data_cfg.serial_baud_rate); + break; + default: + KPrintf("ImxrtCh438Configure do not support configure %d\n", ext_serial_cfg->data_cfg.port_configure); + return ERROR; + break; + } + + return EOK; +} + +static uint32 ImxrtCh438Init(struct SerialDriver *serial_drv, struct SerialCfgParam *ext_serial_cfg) +{ + NULL_PARAM_CHECK(serial_drv); + + struct PinParam pin_cfg; + struct PinStat pin_stat; + int ret = 0; + + struct BusConfigureInfo configure_info; + configure_info.configure_cmd = OPE_CFG; + configure_info.private_data = (void *)&pin_cfg; + + struct BusBlockWriteParam write_param; + write_param.buffer = (void *)&pin_stat; + + ch438_pin = PinBusInitGet(); + + CH438SetOutput(); + + /* config NWR pin as output*/ + pin_cfg.cmd = GPIO_CONFIG_MODE; + pin_cfg.pin = CH438_NWR_PIN; + pin_cfg.mode = GPIO_CFG_OUTPUT; + + ret = BusDrvConfigure(ch438_pin->owner_driver, &configure_info); + if (ret != EOK) { + KPrintf("config NWR pin %d failed!\n", CH438_NWR_PIN); + return ERROR; + } + + /* config NRD pin as output*/ + pin_cfg.pin = CH438_NRD_PIN; + ret = BusDrvConfigure(ch438_pin->owner_driver, &configure_info); + if (ret != EOK) { + KPrintf("config NRD pin %d failed!\n", CH438_NRD_PIN); + return ERROR; + } + + /* config ALE pin as output*/ + pin_cfg.pin = CH438_ALE_PIN; + ret = BusDrvConfigure(ch438_pin->owner_driver, &configure_info); + if (ret != EOK) { + KPrintf("config ALE pin %d failed!\n", CH438_ALE_PIN); + return ERROR; + } + + /* set NWR pin as high*/ + pin_stat.pin = CH438_NWR_PIN; + pin_stat.val = GPIO_HIGH; + BusDevWriteData(ch438_pin->owner_haldev, &write_param); + + /* set NRD pin as high*/ + pin_stat.pin = CH438_NRD_PIN; + pin_stat.val = GPIO_HIGH; + BusDevWriteData(ch438_pin->owner_haldev, &write_param); + + /* set ALE pin as high*/ + pin_stat.pin = CH438_ALE_PIN; + pin_stat.val = GPIO_HIGH; + BusDevWriteData(ch438_pin->owner_haldev, &write_param); + + return ImxrtCh438Configure(ext_serial_cfg); +} + +static uint32 Ch438DrvConfigure(void *drv, struct BusConfigureInfo *configure_info) +{ + NULL_PARAM_CHECK(drv); + NULL_PARAM_CHECK(configure_info); + + x_err_t ret = EOK; + + struct SerialDriver *serial_drv = (struct SerialDriver *)drv; + struct SerialCfgParam *ext_serial_cfg = (struct SerialCfgParam *)configure_info->private_data; + + switch (configure_info->configure_cmd) + { + case OPE_INT: + ret = ImxrtCh438Init(serial_drv, ext_serial_cfg); + break; + default: + break; + } + + return ret; +} + +static uint32 ImxrtCh438WriteData(void *dev, struct BusBlockWriteParam *write_param) +{ + NULL_PARAM_CHECK(dev); + NULL_PARAM_CHECK(write_param); + + int write_len, write_len_continue; + int i, write_index; + uint8 *write_buffer; + + struct SerialHardwareDevice *serial_dev = (struct SerialHardwareDevice *)dev; + struct SerialDevParam *dev_param = (struct SerialDevParam *)serial_dev->haldev.private_data; + + write_len = write_param->size; + write_len_continue = write_param->size; + write_buffer = (uint8 *)write_param->buffer; + + if (write_len > 256) { + if (0 == write_len % 256) { + write_index = write_len / 256; + for (i = 0; i < write_index; i ++) { + Ch438UartSend(dev_param->ext_uart_no, write_buffer + i * 256, 256); + } + } else { + write_index = 0; + while (write_len_continue > 256) { + Ch438UartSend(dev_param->ext_uart_no, write_buffer + write_index * 256, 256); + write_index++; + write_len_continue = write_len - write_index * 256; + } + Ch438UartSend(dev_param->ext_uart_no, write_buffer + write_index * 256, write_len_continue); + } + } else { + Ch438UartSend(dev_param->ext_uart_no, write_buffer, write_len); + } + + return EOK; +} + +static uint32 ImxrtCh438ReadData(void *dev, struct BusBlockReadParam *read_param) +{ + NULL_PARAM_CHECK(dev); + NULL_PARAM_CHECK(read_param); + + x_err_t result; + uint8 rcv_num = 0; + uint8 gInterruptStatus; + uint8 interrupt_done = 0; + uint8 InterruptStatus; + static uint8 dat; + uint8 REG_LCR_ADDR; + uint8 REG_DLL_ADDR; + uint8 REG_DLM_ADDR; + uint8 REG_IER_ADDR; + uint8 REG_MCR_ADDR; + uint8 REG_FCR_ADDR; + uint8 REG_RBR_ADDR; + uint8 REG_THR_ADDR; + uint8 REG_IIR_ADDR; + uint8 REG_LSR_ADDR; + uint8 REG_MSR_ADDR; + + struct SerialHardwareDevice *serial_dev = (struct SerialHardwareDevice *)dev; + struct SerialDevParam *dev_param = (struct SerialDevParam *)serial_dev->haldev.private_data; + + while (!interrupt_done) { + result = KSemaphoreObtain(ch438_sem, WAITING_FOREVER); + if (EOK == result) { + gInterruptStatus = ReadCH438Data(REG_SSR_ADDR); + if (!gInterruptStatus) { + // dat = ReadCH438Data(REG_LCR0_ADDR); + // dat = ReadCH438Data(REG_IER0_ADDR); + // dat = ReadCH438Data(REG_MCR0_ADDR); + // dat = ReadCH438Data(REG_LSR0_ADDR); + // dat = ReadCH438Data(REG_MSR0_ADDR); + // dat = ReadCH438Data(REG_RBR0_ADDR); + // dat = ReadCH438Data(REG_THR0_ADDR); + // dat = ReadCH438Data(REG_IIR0_ADDR); + // dat = dat; + interrupt_done = 0; + } else { + if (gInterruptStatus & interrupt_num[dev_param->ext_uart_no]) { /* check which uart port triggers interrupt*/ + REG_LCR_ADDR = offset_addr[dev_param->ext_uart_no] | REG_LCR0_ADDR; + REG_DLL_ADDR = offset_addr[dev_param->ext_uart_no] | REG_DLL0_ADDR; + REG_DLM_ADDR = offset_addr[dev_param->ext_uart_no] | REG_DLM0_ADDR; + REG_IER_ADDR = offset_addr[dev_param->ext_uart_no] | REG_IER0_ADDR; + REG_MCR_ADDR = offset_addr[dev_param->ext_uart_no] | REG_MCR0_ADDR; + REG_FCR_ADDR = offset_addr[dev_param->ext_uart_no] | REG_FCR0_ADDR; + REG_RBR_ADDR = offset_addr[dev_param->ext_uart_no] | REG_RBR0_ADDR; + REG_THR_ADDR = offset_addr[dev_param->ext_uart_no] | REG_THR0_ADDR; + REG_IIR_ADDR = offset_addr[dev_param->ext_uart_no] | REG_IIR0_ADDR; + REG_LSR_ADDR = offset_addr[dev_param->ext_uart_no] | REG_LSR0_ADDR; + REG_MSR_ADDR = offset_addr[dev_param->ext_uart_no] | REG_MSR0_ADDR; + + InterruptStatus = ReadCH438Data( REG_IIR_ADDR ) & 0x0f; /* read the status of the uart port*/ + + if ((INT_RCV_OVERTIME == InterruptStatus) || (INT_RCV_SUCCESS == InterruptStatus)) { + rcv_num = Ch438UartRcv(dev_param->ext_uart_no, (uint8 *)read_param->buffer, read_param->size); + read_param->read_length = rcv_num; + + interrupt_done = 1; + + // int i; + // uint8 *buffer = (uint8 *)read_param->buffer; + // for (i = 0; i < rcv_num; i ++) { + // KPrintf("Ch438UartRcv i %u data 0x%x\n", i, buffer[i]); + // } + } + } + } + } + } + return rcv_num; +} + +static const struct SerialDevDone dev_done = +{ + NONE, + NONE, + ImxrtCh438WriteData, + ImxrtCh438ReadData, +}; + +static void Ch438InitDefault(struct SerialDriver *serial_drv) +{ + struct PinParam pin_cfg; + BusType ch438_pin; + + struct BusConfigureInfo configure_info; + + int ret = 0; + configure_info.configure_cmd = OPE_CFG; + configure_info.private_data = (void *)&pin_cfg; + + ch438_sem = KSemaphoreCreate(0); + if (ch438_sem < 0) { + KPrintf("Ch438InitDefault create sem failed .\n"); + return; + } + + ch438_pin = PinBusInitGet(); + + pin_cfg.cmd = GPIO_CONFIG_MODE; + pin_cfg.pin = CH438_INT_PIN; + pin_cfg.mode = GPIO_CFG_INPUT_PULLUP; + ret = BusDrvConfigure(ch438_pin->owner_driver, &configure_info); + if (ret != EOK) { + KPrintf("config BSP_CH438_INT_PIN pin %d failed!\n", CH438_INT_PIN); + return; + } + + pin_cfg.cmd = GPIO_IRQ_REGISTER; + pin_cfg.pin = CH438_INT_PIN; + pin_cfg.irq_set.irq_mode = GPIO_IRQ_EDGE_FALLING; + pin_cfg.irq_set.hdr = Ch438Irq; + pin_cfg.irq_set.args = NONE; + ret = BusDrvConfigure(ch438_pin->owner_driver, &configure_info); + if (ret != EOK) { + KPrintf("config BSP_CH438_INT_PIN GPIO_IRQ_REGISTER %d failed!\n", CH438_INT_PIN); + return; + } + + //disable ch438 int gpio irq + pin_cfg.cmd = GPIO_IRQ_DISABLE; + pin_cfg.pin = CH438_INT_PIN; + ret = BusDrvConfigure(ch438_pin->owner_driver, &configure_info); + if (ret != EOK) { + KPrintf("config BSP_CH438_INT_PIN GPIO_IRQ_DISABLE %d failed!\n", CH438_INT_PIN); + return; + } + + //enable ch438 int gpio irq + pin_cfg.cmd = GPIO_IRQ_ENABLE; + pin_cfg.pin = CH438_INT_PIN; + ret = BusDrvConfigure(ch438_pin->owner_driver, &configure_info); + if (ret != EOK) { + KPrintf("config BSP_CH438_INT_PIN GPIO_IRQ_ENABLE %d failed!\n", CH438_INT_PIN); + return; + } +} + +static uint32 ImxrtCh438DevRegister(struct SerialHardwareDevice *serial_dev, char *dev_name) +{ + x_err_t ret = EOK; + serial_dev->dev_done = &dev_done; + serial_dev->ext_serial_mode = RET_TRUE; + ret = SerialDeviceRegister(serial_dev, NONE, dev_name); + if (ret != EOK) { + KPrintf("ImxrtHwCh438Init Serial device %s register error %d\n", dev_name, ret); + return ERROR; + } + + ret = SerialDeviceAttachToBus(dev_name, CH438_BUS_NAME); + if (ret != EOK) { + KPrintf("ImxrtHwCh438Init Serial device %s register error %d\n", dev_name, ret); + return ERROR; + } + + return ret; +} + +int Imxrt1052HwCh438Init(void) +{ + static struct SerialBus serial_bus; + static struct SerialDriver serial_drv; + + x_err_t ret = EOK; + + ret = SerialBusInit(&serial_bus, CH438_BUS_NAME); + if (ret != EOK) { + KPrintf("ImxrtHwCh438Init Serial bus init error %d\n", ret); + return ERROR; + } + + serial_drv.configure = Ch438DrvConfigure; + ret = SerialDriverInit(&serial_drv, CH438_DRIVER_NAME); + if (ret != EOK) { + KPrintf("ImxrtHwCh438Init Serial driver init error %d\n", ret); + return ERROR; + } + + ret = SerialDriverAttachToBus(CH438_DRIVER_NAME, CH438_BUS_NAME); + if (ret != EOK) { + KPrintf("ImxrtHwCh438Init Serial driver attach error %d\n", ret); + return ERROR; + } + + static struct SerialHardwareDevice serial_dev_0; + static struct SerialDevParam dev_param_0; + dev_param_0.ext_uart_no = 0; + serial_dev_0.haldev.private_data = (void *)&dev_param_0; + ret = ImxrtCh438DevRegister(&serial_dev_0, CH438_DEVICE_NAME_0); + if (ret != EOK) { + KPrintf("ImxrtHwCh438Init ImxrtCh438DevRegister error %d\n", ret); + return ERROR; + } + + static struct SerialHardwareDevice serial_dev_1; + static struct SerialDevParam dev_param_1; + dev_param_1.ext_uart_no = 1; + serial_dev_1.haldev.private_data = (void *)&dev_param_1; + ret = ImxrtCh438DevRegister(&serial_dev_1, CH438_DEVICE_NAME_1); + if (ret != EOK) { + KPrintf("ImxrtHwCh438Init ImxrtCh438DevRegister error %d\n", ret); + return ERROR; + } + + static struct SerialHardwareDevice serial_dev_2; + static struct SerialDevParam dev_param_2; + dev_param_2.ext_uart_no = 2; + serial_dev_2.haldev.private_data = (void *)&dev_param_2; + ret = ImxrtCh438DevRegister(&serial_dev_2, CH438_DEVICE_NAME_2); + if (ret != EOK) { + KPrintf("ImxrtHwCh438Init ImxrtCh438DevRegister error %d\n", ret); + return ERROR; + } + + static struct SerialHardwareDevice serial_dev_3; + static struct SerialDevParam dev_param_3; + dev_param_3.ext_uart_no = 3; + serial_dev_3.haldev.private_data = (void *)&dev_param_3; + ret = ImxrtCh438DevRegister(&serial_dev_3, CH438_DEVICE_NAME_3); + if (ret != EOK) { + KPrintf("ImxrtHwCh438Init ImxrtCh438DevRegister error %d\n", ret); + return ERROR; + } + + static struct SerialHardwareDevice serial_dev_4; + static struct SerialDevParam dev_param_4; + dev_param_4.ext_uart_no = 4; + serial_dev_4.haldev.private_data = (void *)&dev_param_4; + ret = ImxrtCh438DevRegister(&serial_dev_4, CH438_DEVICE_NAME_4); + if (ret != EOK) { + KPrintf("ImxrtHwCh438Init ImxrtCh438DevRegister error %d\n", ret); + return ERROR; + } + + static struct SerialHardwareDevice serial_dev_5; + static struct SerialDevParam dev_param_5; + dev_param_5.ext_uart_no = 5; + serial_dev_5.haldev.private_data = (void *)&dev_param_5; + ret = ImxrtCh438DevRegister(&serial_dev_5, CH438_DEVICE_NAME_5); + if (ret != EOK) { + KPrintf("ImxrtHwCh438Init ImxrtCh438DevRegister error %d\n", ret); + return ERROR; + } + + static struct SerialHardwareDevice serial_dev_6; + static struct SerialDevParam dev_param_6; + dev_param_6.ext_uart_no = 6; + serial_dev_6.haldev.private_data = (void *)&dev_param_6; + ret = ImxrtCh438DevRegister(&serial_dev_6, CH438_DEVICE_NAME_6); + if (ret != EOK) { + KPrintf("ImxrtHwCh438Init ImxrtCh438DevRegister error %d\n", ret); + return ERROR; + } + + static struct SerialHardwareDevice serial_dev_7; + static struct SerialDevParam dev_param_7; + dev_param_7.ext_uart_no = 7; + serial_dev_7.haldev.private_data = (void *)&dev_param_7; + ret = ImxrtCh438DevRegister(&serial_dev_7, CH438_DEVICE_NAME_7); + if (ret != EOK) { + KPrintf("ImxrtHwCh438Init ImxrtCh438DevRegister error %d\n", ret); + return ERROR; + } + + Ch438InitDefault(&serial_drv); + + return ret; +} + +#ifdef CH438_EXTUART_TEST +static void CH438RegTest(unsigned char num)//for test +{ + uint8 dat; + + KPrintf("current test serial num: %02x \r\n",offset_addr[num]); + KPrintf("IER: 0x%02x\r\n",ReadCH438Data(offset_addr[num] | REG_IER0_ADDR));//IER + KPrintf("IIR: 0x%02x\r\n",ReadCH438Data(offset_addr[num] | REG_IIR0_ADDR));//IIR + KPrintf("LCR: 0x%02x\r\n",ReadCH438Data(offset_addr[num] | REG_LCR0_ADDR));//LCR + KPrintf("MCR: 0x%02x\r\n",ReadCH438Data(offset_addr[num] | REG_MCR0_ADDR));//MCR + KPrintf("LSR: 0x%02x\r\n",ReadCH438Data(offset_addr[num] | REG_LSR0_ADDR));//LSR + KPrintf("MSR: 0x%02x\r\n",ReadCH438Data(offset_addr[num] | REG_MSR0_ADDR));//MSR + KPrintf("FCR: 0x%02x\r\n",ReadCH438Data(offset_addr[num] | REG_FCR0_ADDR));//FCR + KPrintf("SSR: 0x%02x\r\n",ReadCH438Data(offset_addr[num] | REG_SSR_ADDR ));//SSR + + KPrintf("SCR0: 0x%02x\r\n",(unsigned short)ReadCH438Data(offset_addr[num] | REG_SCR0_ADDR));//SCR + dat = 0x55; + WriteCH438Data(offset_addr[num] | REG_SCR0_ADDR, dat); + KPrintf("SCR55: 0x%02x\r\n",(unsigned short)ReadCH438Data(offset_addr[num] | REG_SCR0_ADDR));//SCR + dat = 0xAA; + WriteCH438Data(offset_addr[num] | REG_SCR0_ADDR, dat); + KPrintf("SCRAA: 0x%02x\r\n",(unsigned short)ReadCH438Data(offset_addr[num] | REG_SCR0_ADDR));//SCR +} + +static struct Bus *bus; +static struct HardwareDev *dev; +static struct Driver *drv; + +static void Ch438Read(void *parameter) +{ + uint8 RevLen; + uint8 ext_uart_no = 0; + uint8 i, cnt = 0; + + struct BusBlockReadParam read_param; + static uint8 Ch438Buff[8][256]; + + struct BusBlockWriteParam write_param; + + while (1) + { + KPrintf("ready to read test_ch438 data\n"); + + read_param.buffer = Ch438Buff[ext_uart_no]; + RevLen = BusDevReadData(dev, &read_param); + + KPrintf("test_ch438 get data %u\n", RevLen); + + if (RevLen) { + for(i = 0 ; i < RevLen; i ++) { + KPrintf("i %u data 0x%x\n", i, Ch438Buff[ext_uart_no][i]); + Ch438Buff[ext_uart_no][i] = 0; + } + + cnt ++; + write_param.buffer = &cnt; + write_param.size = 1; + BusDevWriteData(dev, &write_param); + } + + } +} + +static void TestCh438Init(void) +{ + x_err_t flag; + + struct BusConfigureInfo configure_info; + + bus = BusFind(CH438_BUS_NAME); + drv = BusFindDriver(bus, CH438_DRIVER_NAME); + + dev = BusFindDevice(bus, CH438_DEVICE_NAME_0); + + struct SerialCfgParam serial_cfg; + memset(&serial_cfg, 0, sizeof(struct SerialCfgParam)); + configure_info.configure_cmd = OPE_INT; + configure_info.private_data = (void *)&serial_cfg; + + serial_cfg.data_cfg.port_configure = PORT_CFG_INIT; + + serial_cfg.data_cfg.ext_uart_no = 0; + serial_cfg.data_cfg.serial_baud_rate = 115200; + BusDrvConfigure(drv, &configure_info); + + KPrintf("ready to create test_ch438 task\n"); + + int32 task_CH438_read = KTaskCreate("task_CH438_read", Ch438Read, NONE, 2048, 10); + flag = StartupKTask(task_CH438_read); + if (flag != EOK) { + KPrintf("StartupKTask task_CH438_read failed .\n"); + return; + } +} + +void TestCh438(void) +{ + TestCh438Init(); + + CH438RegTest(0); +} +SHELL_EXPORT_CMD(SHELL_CMD_PERMISSION(0)|SHELL_CMD_TYPE(SHELL_TYPE_CMD_MAIN), + TestCh438, TestCh438, TestCh438 ); + +#endif diff --git a/Ubiquitous/XiZi/board/xidatong/third_party_driver/gpio/Kconfig b/Ubiquitous/XiZi/board/xidatong/third_party_driver/gpio/Kconfig new file mode 100755 index 0000000..f284f60 --- /dev/null +++ b/Ubiquitous/XiZi/board/xidatong/third_party_driver/gpio/Kconfig @@ -0,0 +1,12 @@ + +config PIN_BUS_NAME + string "pin bus name" + default "pin" + +config PIN_DRIVER_NAME + string "pin driver name" + default "pin_drv" + +config PIN_DEVICE_NAME + string "pin device name" + default "pin_dev" diff --git a/Ubiquitous/XiZi/board/xidatong/third_party_driver/gpio/Makefile b/Ubiquitous/XiZi/board/xidatong/third_party_driver/gpio/Makefile new file mode 100755 index 0000000..a696773 --- /dev/null +++ b/Ubiquitous/XiZi/board/xidatong/third_party_driver/gpio/Makefile @@ -0,0 +1,3 @@ +SRC_FILES := connect_gpio.c fsl_gpio.c + +include $(KERNEL_ROOT)/compiler.mk \ No newline at end of file diff --git a/Ubiquitous/XiZi/board/xidatong/third_party_driver/gpio/connect_gpio.c b/Ubiquitous/XiZi/board/xidatong/third_party_driver/gpio/connect_gpio.c new file mode 100755 index 0000000..ddf1ed8 --- /dev/null +++ b/Ubiquitous/XiZi/board/xidatong/third_party_driver/gpio/connect_gpio.c @@ -0,0 +1,779 @@ +/* + * Copyright (c) 2006-2021, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2018-4-30 misonyo the first version. + */ + +/** +* @file connect_gpio.c +* @brief support gpio function using bus driver framework +* @version 2.0 +* @author AIIT XUOS Lab +* @date 2022-03-16 +*/ + +/************************************************* +File name: connect_gpio.c +Description: support gpio configure and register to bus framework +Others: take RT-Thread v4.0.2/bsp/imxrt/libraries/drivers/drv_gpio.c for references + https://github.com/RT-Thread/rt-thread/tree/v4.0.2 +History: +1. Date: 2022-03-16 +Author: AIIT XUOS Lab +Modification: add bus driver framework support for gpio +*************************************************/ + +#include +#include +#include + +struct PinIndex +{ + int index; + GPIO_Type *gpio; + uint32_t pin; +}; + +struct PinIrq +{ + uint8 port_source; + uint8 pin_source; + enum IRQn irq_exti_channel; + uint32 exti_line; +}; + +struct PinMask +{ + GPIO_Type *gpio; + uint32 valid_mask; +}; + +static const IRQn_Type irq_tab[10] = +{ + GPIO1_Combined_0_15_IRQn, + GPIO1_Combined_16_31_IRQn, + GPIO2_Combined_0_15_IRQn, + GPIO2_Combined_16_31_IRQn, + GPIO3_Combined_0_15_IRQn, + GPIO3_Combined_16_31_IRQn, + GPIO4_Combined_0_15_IRQn, + GPIO4_Combined_16_31_IRQn, + GPIO5_Combined_0_15_IRQn, + GPIO5_Combined_16_31_IRQn +}; + +const struct PinMask pin_mask[] = +{ + {GPIO1, 0xFFFFFFFF}, /* GPIO1 */ + {GPIO2, 0xFFFFFFFF}, /* GPIO2 */ + {GPIO3, 0x0FFFFFFF}, /* GPIO3,28~31 not supported */ + {GPIO4, 0xFFFFFFFF}, /* GPIO4 */ + {GPIO5, 0x00000007} /* GPIO5,3~31 not supported */ +}; + +struct PinIrqHdr pin_irq_hdr_tab[] = +{ +/* GPIO1 */ + {-1, 0, NONE, NONE},//1 + {-1, 0, NONE, NONE}, + {-1, 0, NONE, NONE}, + {-1, 0, NONE, NONE}, + {-1, 0, NONE, NONE}, + {-1, 0, NONE, NONE}, + {-1, 0, NONE, NONE}, + {-1, 0, NONE, NONE}, + {-1, 0, NONE, NONE}, + {-1, 0, NONE, NONE}, + {-1, 0, NONE, NONE}, + {-1, 0, NONE, NONE}, + {-1, 0, NONE, NONE}, + {-1, 0, NONE, NONE}, + {-1, 0, NONE, NONE}, + {-1, 0, NONE, NONE}, + {-1, 0, NONE, NONE}, + {-1, 0, NONE, NONE}, + {-1, 0, NONE, NONE}, + {-1, 0, NONE, NONE}, + {-1, 0, NONE, NONE}, + {-1, 0, NONE, NONE}, + {-1, 0, NONE, NONE}, + {-1, 0, NONE, NONE}, + {-1, 0, NONE, NONE}, + {-1, 0, NONE, NONE}, + {-1, 0, NONE, NONE}, + {-1, 0, NONE, NONE}, + {-1, 0, NONE, NONE}, + {-1, 0, NONE, NONE}, + {-1, 0, NONE, NONE}, + {-1, 0, NONE, NONE},//32 + /* GPIO2 */ + {-1, 0, NONE, NONE},//33 + {-1, 0, NONE, NONE}, + {-1, 0, NONE, NONE}, + {-1, 0, NONE, NONE}, + {-1, 0, NONE, NONE}, + {-1, 0, NONE, NONE}, + {-1, 0, NONE, NONE}, + {-1, 0, NONE, NONE}, + {-1, 0, NONE, NONE}, + {-1, 0, NONE, NONE}, + {-1, 0, NONE, NONE}, + {-1, 0, NONE, NONE}, + {-1, 0, NONE, NONE}, + {-1, 0, NONE, NONE}, + {-1, 0, NONE, NONE}, + {-1, 0, NONE, NONE}, + {-1, 0, NONE, NONE}, + {-1, 0, NONE, NONE}, + {-1, 0, NONE, NONE}, + {-1, 0, NONE, NONE}, + {-1, 0, NONE, NONE}, + {-1, 0, NONE, NONE}, + {-1, 0, NONE, NONE}, + {-1, 0, NONE, NONE}, + {-1, 0, NONE, NONE}, + {-1, 0, NONE, NONE}, + {-1, 0, NONE, NONE}, + {-1, 0, NONE, NONE}, + {-1, 0, NONE, NONE}, + {-1, 0, NONE, NONE}, + {-1, 0, NONE, NONE}, + {-1, 0, NONE, NONE},//64 + /* GPIO3 */ + {-1, 0, NONE, NONE},//65 + {-1, 0, NONE, NONE}, + {-1, 0, NONE, NONE}, + {-1, 0, NONE, NONE}, + {-1, 0, NONE, NONE}, + {-1, 0, NONE, NONE}, + {-1, 0, NONE, NONE}, + {-1, 0, NONE, NONE}, + {-1, 0, NONE, NONE}, + {-1, 0, NONE, NONE}, + {-1, 0, NONE, NONE}, + {-1, 0, NONE, NONE}, + {-1, 0, NONE, NONE}, + {-1, 0, NONE, NONE}, + {-1, 0, NONE, NONE}, + {-1, 0, NONE, NONE}, + {-1, 0, NONE, NONE}, + {-1, 0, NONE, NONE}, + {-1, 0, NONE, NONE}, + {-1, 0, NONE, NONE}, + {-1, 0, NONE, NONE}, + {-1, 0, NONE, NONE}, + {-1, 0, NONE, NONE}, + {-1, 0, NONE, NONE}, + {-1, 0, NONE, NONE}, + {-1, 0, NONE, NONE}, + {-1, 0, NONE, NONE}, + {-1, 0, NONE, NONE}, + {-1, 0, NONE, NONE}, + {-1, 0, NONE, NONE}, + {-1, 0, NONE, NONE}, + {-1, 0, NONE, NONE},//96 + /* GPIO4 */ + {-1, 0, NONE, NONE}, + {-1, 0, NONE, NONE}, + {-1, 0, NONE, NONE}, + {-1, 0, NONE, NONE}, + {-1, 0, NONE, NONE}, + {-1, 0, NONE, NONE}, + {-1, 0, NONE, NONE}, + {-1, 0, NONE, NONE}, + {-1, 0, NONE, NONE}, + {-1, 0, NONE, NONE}, + {-1, 0, NONE, NONE}, + {-1, 0, NONE, NONE}, + {-1, 0, NONE, NONE}, + {-1, 0, NONE, NONE}, + {-1, 0, NONE, NONE}, + {-1, 0, NONE, NONE}, + {-1, 0, NONE, NONE}, + {-1, 0, NONE, NONE}, + {-1, 0, NONE, NONE}, + {-1, 0, NONE, NONE}, + {-1, 0, NONE, NONE}, + {-1, 0, NONE, NONE}, + {-1, 0, NONE, NONE}, + {-1, 0, NONE, NONE}, + {-1, 0, NONE, NONE}, + {-1, 0, NONE, NONE}, + {-1, 0, NONE, NONE}, + {-1, 0, NONE, NONE}, + {-1, 0, NONE, NONE}, + {-1, 0, NONE, NONE}, + {-1, 0, NONE, NONE}, + {-1, 0, NONE, NONE},//128 + /* GPIO5 */ + {-1, 0, NONE, NONE},//129 + {-1, 0, NONE, NONE}, + {-1, 0, NONE, NONE}, +}; + +#define MUX_BASE 0x401f8014 +#define CONFIG_BASE 0x401f8204 + +#define GPIO5_MUX_BASE 0x400A8000 +#define GPIO5_CONFIG_BASE 0x400A8018 + +const uint8_t reg_offset[] = +{ + 42, 43, 44, 45, 46, 47, 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, + 74, 75, 76, 77, 78, 79, 80, 81, 82, 83, 84, 85, 86, 87, 88, 89, 90, 91, 92, 93, 94, 95, 96, 97, 98, 99,100,101,102,103,104,105, + 112,113,114,115,116,117,118,119,120,121,122,123,106,107,108,109,110,111, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, -1, -1, -1, -1, + 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, +}; + +static int GetPin(struct PinIndex *pin_index, uint8_t pin) +{ + pin_index->index = pin >> 5;//0:GPIO1 1:GPIO2 2:GPIO3 3:GPIO4 4:GPIO5 + pin_index->pin = pin & 31;//each GPIOx support 32 io + + if ((pin_index->index > 4) || ((pin_mask[pin_index->index].valid_mask & (1 << pin_index->pin)) == 0)) { + KPrintf("GetPin unsupport pin index %u pin %u\n", pin_index->index, pin_index->pin); + return -1; + } + + pin_index->gpio = pin_mask[pin_index->index].gpio; + return 0; +} + +static int32 GpioConfigMode(int mode, struct PinIndex *pin_index, int32 pin) +{ + gpio_pin_config_t gpio_config; + uint32_t config_value = 0; + NULL_PARAM_CHECK(pin_index); + + gpio_config.outputLogic = 0; + gpio_config.interruptMode = kGPIO_NoIntmode; + + switch (mode) + { + case GPIO_CFG_OUTPUT: + gpio_config.direction = kGPIO_DigitalOutput; + config_value = 0x0030U; /* Drive Strength R0/6 */ + break; + case GPIO_CFG_INPUT: + gpio_config.direction = kGPIO_DigitalInput; + config_value = 0x0830U; /* Open Drain Enable */ + break; + case GPIO_CFG_INPUT_PULLUP: + gpio_config.direction = kGPIO_DigitalInput; + config_value = 0xB030U; /* 100K Ohm Pull Up */ + break; + case GPIO_CFG_INPUT_PULLDOWN: + gpio_config.direction = kGPIO_DigitalInput; + config_value = 0x3030U; /* 100K Ohm Pull Down */ + break; + case GPIO_CFG_OUTPUT_OD: + gpio_config.direction = kGPIO_DigitalOutput; + config_value = 0x0830U; /* Open Drain Enable */ + break; + default: + break; + } + + if (pin_mask[pin_index->index].gpio != GPIO5) { + CLOCK_EnableClock(kCLOCK_Iomuxc); + IOMUXC_SetPinMux(MUX_BASE + reg_offset[pin] * 4, 0x5U, 0, 0, CONFIG_BASE + reg_offset[pin] * 4, 1); + IOMUXC_SetPinConfig(MUX_BASE + reg_offset[pin] * 4, 0x5U, 0, 0, CONFIG_BASE + reg_offset[pin] * 4, config_value); + } else { + CLOCK_EnableClock(kCLOCK_IomuxcSnvs); + IOMUXC_SetPinMux(GPIO5_MUX_BASE + pin_index->pin * 4, 0x5U, 0, 0, GPIO5_CONFIG_BASE + pin_index->pin * 4, 1); + IOMUXC_SetPinConfig(GPIO5_MUX_BASE + pin_index->pin * 4, 0x5U, 0, 0, GPIO5_CONFIG_BASE + pin_index->pin * 4, config_value); + } + + GPIO_PinInit(pin_index->gpio, pin_index->pin, &gpio_config); + return EOK; +} + +static int32 GpioIrqRegister(int32 pin, int32 mode, void (*hdr)(void *args), void *args) +{ + struct PinIndex pin_index; + + if (GetPin(&pin_index, pin) < 0) { + return ERROR; + } + + x_base level = CriticalAreaLock(); + if (pin_irq_hdr_tab[pin].pin == pin && + pin_irq_hdr_tab[pin].hdr == hdr && + pin_irq_hdr_tab[pin].mode == mode && + pin_irq_hdr_tab[pin].args == args + ) + { + CriticalAreaUnLock(level); + return EOK; + } + + if (pin_irq_hdr_tab[pin].pin != -1) { + CriticalAreaUnLock(level); + return -EDEV_BUSY; + } + pin_irq_hdr_tab[pin].pin = pin; + pin_irq_hdr_tab[pin].hdr = hdr; + pin_irq_hdr_tab[pin].mode = mode; + pin_irq_hdr_tab[pin].args = args; + CriticalAreaUnLock(level); + + return EOK; +} + +static uint32 GpioIrqFree(int32 pin) +{ + struct PinIndex pin_index; + + if (GetPin(&pin_index, pin) < 0) { + return ERROR; + } + + x_base level = CriticalAreaLock(); + if (pin_irq_hdr_tab[pin].pin == -1){ + CriticalAreaUnLock(level); + return EOK; + } + pin_irq_hdr_tab[pin].pin = -1; + pin_irq_hdr_tab[pin].hdr = NONE; + pin_irq_hdr_tab[pin].mode = 0; + pin_irq_hdr_tab[pin].args = NONE; + CriticalAreaUnLock(level); + + return EOK; +} + +static int32 GpioIrqEnable(x_base pin) +{ + uint8_t irq_index; + gpio_interrupt_mode_t gpio_int_mode; + struct PinIndex pin_index; + + if (GetPin(&pin_index, pin) < 0) { + return ERROR; + } + + x_base level = CriticalAreaLock(); + if (pin_irq_hdr_tab[pin].pin == -1) { + CriticalAreaUnLock(level); + return -ENONESYS; + } + + switch (pin_irq_hdr_tab[pin].mode) + { + case GPIO_IRQ_EDGE_RISING: + gpio_int_mode = kGPIO_IntRisingEdge; + break; + case GPIO_IRQ_EDGE_FALLING: + gpio_int_mode = kGPIO_IntFallingEdge; + break; + case GPIO_IRQ_EDGE_BOTH: + gpio_int_mode = kGPIO_IntRisingOrFallingEdge; + break; + case GPIO_IRQ_LEVEL_HIGH: + gpio_int_mode = kGPIO_IntHighLevel; + break; + case GPIO_IRQ_LEVEL_LOW: + gpio_int_mode = kGPIO_IntLowLevel; + break; + default: + gpio_int_mode = kGPIO_IntRisingEdge; + break; + } + + irq_index = (pin_index.index << 1) + (pin_index.pin >> 4); + GPIO_PinSetInterruptConfig(pin_index.gpio, pin_index.pin, gpio_int_mode); + GPIO_PortEnableInterrupts(pin_index.gpio, 1U << pin_index.pin); + NVIC_SetPriority(irq_tab[irq_index], NVIC_EncodePriority(NVIC_GetPriorityGrouping(), 5, 0)); + EnableIRQ(irq_tab[irq_index]); + CriticalAreaUnLock(level); + return EOK; +} + +static int32 GpioIrqDisable(x_base pin) +{ + struct PinIndex pin_index; + + if (GetPin(&pin_index, pin) < 0) { + return ERROR; + } + + GPIO_PortDisableInterrupts(pin_index.gpio, 1U << pin_index.pin); + return EOK; +} + +static uint32 Imxrt1052PinConfigure(struct PinParam *param) +{ + NULL_PARAM_CHECK(param); + int ret = EOK; + + struct PinIndex pin_index; + + if (GetPin(&pin_index, param->pin) < 0) { + return ERROR; + } + + switch(param->cmd) + { + case GPIO_CONFIG_MODE: + GpioConfigMode(param->mode, &pin_index, param->pin); + break; + case GPIO_IRQ_REGISTER: + ret = GpioIrqRegister(param->pin, param->irq_set.irq_mode, param->irq_set.hdr, param->irq_set.args); + break; + case GPIO_IRQ_FREE: + ret = GpioIrqFree(param->pin); + break; + case GPIO_IRQ_ENABLE: + ret = GpioIrqEnable(param->pin); + break; + case GPIO_IRQ_DISABLE: + ret = GpioIrqDisable(param->pin); + break; + default: + ret = -EINVALED; + break; + } + + return ret; +} + +static uint32 Imxrt1052PinInit(void) +{ + static x_bool pin_init_flag = RET_FALSE; + + if (!pin_init_flag) { + pin_init_flag = RET_TRUE; + } + + return EOK; +} + +static uint32 Imxrt1052GpioDrvConfigure(void *drv, struct BusConfigureInfo *configure_info) +{ + NULL_PARAM_CHECK(drv); + NULL_PARAM_CHECK(configure_info); + + x_err_t ret = EOK; + struct PinParam *param; + + switch (configure_info->configure_cmd) + { + case OPE_INT: + ret = Imxrt1052PinInit(); + break; + case OPE_CFG: + param = (struct PinParam *)configure_info->private_data; + ret = Imxrt1052PinConfigure(param); + break; + default: + break; + } + + return ret; +} + +uint32 Imxrt1052PinWrite(void *dev, struct BusBlockWriteParam *write_param) +{ + NULL_PARAM_CHECK(dev); + NULL_PARAM_CHECK(write_param); + struct PinStat *pin_stat = (struct PinStat *)write_param->buffer; + struct PinIndex pin_index; + + if (GetPin(&pin_index, pin_stat->pin) < 0) { + return ERROR; + } + + if (GPIO_LOW == pin_stat->val) { + GPIO_PinWrite(pin_index.gpio, pin_index.pin, 0); + } else { + GPIO_PinWrite(pin_index.gpio, pin_index.pin, 1); + } + return EOK; +} + +uint32 Imxrt1052PinRead(void *dev, struct BusBlockReadParam *read_param) +{ + NULL_PARAM_CHECK(dev); + NULL_PARAM_CHECK(read_param); + struct PinStat *pin_stat = (struct PinStat *)read_param->buffer; + struct PinIndex pin_index; + + if (GetPin(&pin_index, pin_stat->pin) < 0) { + return ERROR; + } + + if(GPIO_LOW == GPIO_PinRead(pin_index.gpio, pin_index.pin)) { + pin_stat->val = GPIO_LOW; + } else { + pin_stat->val = GPIO_HIGH; + } + return pin_stat->val; +} + +static const struct PinDevDone dev_done = +{ + .open = NONE, + .close = NONE, + .write = Imxrt1052PinWrite, + .read = Imxrt1052PinRead, +}; + +int Imxrt1052HwGpioInit(void) +{ + x_err_t ret = EOK; + + static struct PinBus pin; + + ret = PinBusInit(&pin, PIN_BUS_NAME); + if (ret != EOK) { + KPrintf("gpio bus init error %d\n", ret); + return ERROR; + } + + static struct PinDriver drv; + drv.configure = Imxrt1052GpioDrvConfigure; + + ret = PinDriverInit(&drv, PIN_DRIVER_NAME, NONE); + if (ret != EOK) { + KPrintf("pin driver init error %d\n", ret); + return ERROR; + } + ret = PinDriverAttachToBus(PIN_DRIVER_NAME, PIN_BUS_NAME); + if (ret != EOK) { + KPrintf("pin driver attach error %d\n", ret); + return ERROR; + } + + static struct PinHardwareDevice dev; + dev.dev_done = &dev_done; + + ret = PinDeviceRegister(&dev, NONE, PIN_DEVICE_NAME); + if (ret != EOK) { + KPrintf("pin device register error %d\n", ret); + return ERROR; + } + ret = PinDeviceAttachToBus(PIN_DEVICE_NAME, PIN_BUS_NAME); + if (ret != EOK) { + KPrintf("pin device register error %d\n", ret); + return ERROR; + } + + return ret; +} + +static __inline void PinIrqHdr(uint32_t index_offset, uint8_t pin_start, GPIO_Type *gpio) +{ + int i; + uint32_t isr_status, pin; + struct PinIndex pin_index; + + isr_status = GPIO_PortGetInterruptFlags(gpio) & gpio->IMR; + + for (i = pin_start; i <= pin_start + 15 ; i ++) { + + if (GetPin(&pin_index, i + index_offset) < 0) { + continue; + } + + if (isr_status & (1 << i)) { + GPIO_PortClearInterruptFlags(gpio, (1 << i)); + + __DSB(); + + pin = index_offset + i; + if (pin_irq_hdr_tab[pin].hdr) { + pin_irq_hdr_tab[pin].hdr(pin_irq_hdr_tab[pin].args); + } + } + } +} + +void GPIO1_0_15_IRQHandler(int irq_num, void *arg) +{ + x_base lock = 0; + lock = DISABLE_INTERRUPT(); + + PinIrqHdr(0, 0, GPIO1); + + ENABLE_INTERRUPT(lock); +} +DECLARE_HW_IRQ(GPIO1_Combined_0_15_IRQn, GPIO1_0_15_IRQHandler, NONE); + +void GPIO1_16_31_IRQHandler(int irq_num, void *arg) +{ + x_base lock = 0; + lock = DISABLE_INTERRUPT(); + + PinIrqHdr(0, 15, GPIO1); + + ENABLE_INTERRUPT(lock); +} +DECLARE_HW_IRQ(GPIO1_Combined_16_31_IRQn, GPIO1_16_31_IRQHandler, NONE); + +void GPIO2_0_15_IRQHandler(int irq_num, void *arg) +{ + x_base lock = 0; + lock = DISABLE_INTERRUPT(); + + PinIrqHdr(32, 0, GPIO2); + + ENABLE_INTERRUPT(lock); +} +DECLARE_HW_IRQ(GPIO2_Combined_0_15_IRQn, GPIO2_0_15_IRQHandler, NONE); + +void GPIO2_16_31_IRQHandler(int irq_num, void *arg) +{ + x_base lock = 0; + lock = DISABLE_INTERRUPT(); + + PinIrqHdr(32, 15, GPIO2); + + ENABLE_INTERRUPT(lock); +} +DECLARE_HW_IRQ(GPIO2_Combined_16_31_IRQn, GPIO2_16_31_IRQHandler, NONE); + +void GPIO3_0_15_IRQHandler(int irq_num, void *arg) +{ + x_base lock = 0; + lock = DISABLE_INTERRUPT(); + + PinIrqHdr(64, 0, GPIO3); + + ENABLE_INTERRUPT(lock); +} +DECLARE_HW_IRQ(GPIO3_Combined_0_15_IRQn, GPIO3_0_15_IRQHandler, NONE); + +void GPIO3_16_31_IRQHandler(int irq_num, void *arg) +{ + x_base lock = 0; + lock = DISABLE_INTERRUPT(); + + PinIrqHdr(64, 15, GPIO3); + + ENABLE_INTERRUPT(lock); +} +DECLARE_HW_IRQ(GPIO3_Combined_16_31_IRQn, GPIO3_16_31_IRQHandler, NONE); + +void GPIO4_0_15_IRQHandler(int irq_num, void *arg) +{ + x_base lock = 0; + lock = DISABLE_INTERRUPT(); + + PinIrqHdr(96, 0, GPIO4); + + ENABLE_INTERRUPT(lock); +} +DECLARE_HW_IRQ(GPIO4_Combined_0_15_IRQn, GPIO4_0_15_IRQHandler, NONE); + +void GPIO4_16_31_IRQHandler(int irq_num, void *arg) +{ + x_base lock = 0; + lock = DISABLE_INTERRUPT(); + + PinIrqHdr(96, 15, GPIO4); + + ENABLE_INTERRUPT(lock); +} +DECLARE_HW_IRQ(GPIO4_Combined_16_31_IRQn, GPIO4_16_31_IRQHandler, NONE); + +void GPIO5_0_15_IRQHandler(int irq_num, void *arg) +{ + x_base lock = 0; + lock = DISABLE_INTERRUPT(); + + PinIrqHdr(128, 0, GPIO5); + + ENABLE_INTERRUPT(lock); +} +DECLARE_HW_IRQ(GPIO5_Combined_0_15_IRQn, GPIO5_0_15_IRQHandler, NONE); + +void GPIO5_16_31_IRQHandler(int irq_num, void *arg) +{ + x_base lock = 0; + lock = DISABLE_INTERRUPT(); + + PinIrqHdr(128, 15, GPIO5); + + ENABLE_INTERRUPT(lock); +} +DECLARE_HW_IRQ(GPIO5_Combined_16_31_IRQn, GPIO5_16_31_IRQHandler, NONE); + +#ifdef GPIO_LED_TEST +static void GpioLedDelay(void) +{ + volatile uint32_t i = 0; + for (i = 0; i < 8000000; ++i) + { + __asm("NOP"); /* delay */ + } +} + +void GpioLedTest(void) +{ + BusType pin; + struct BusConfigureInfo configure_info; + struct BusBlockWriteParam write_param; + + int ret = 0; + bool pinSet = 1; + + pin = BusFind(PIN_BUS_NAME); + if (!pin) { + KPrintf("find %s failed!\n", PIN_BUS_NAME); + return; + } + pin->owner_driver = BusFindDriver(pin, PIN_DRIVER_NAME); + pin->owner_haldev = BusFindDevice(pin, PIN_DEVICE_NAME); + + configure_info.configure_cmd = OPE_INT; + ret = BusDrvConfigure(pin->owner_driver, &configure_info); + if (ret != EOK) { + KPrintf("initialize %s failed!\n", PIN_BUS_NAME); + return; + } + + struct PinParam led_gpio_param; + struct PinStat led_gpio_stat; + + /* config led pin as output*/ + led_gpio_param.cmd = GPIO_CONFIG_MODE; + led_gpio_param.pin = IMXRT_GET_PIN(1, 9); + led_gpio_param.mode = GPIO_CFG_OUTPUT_OD; + + configure_info.configure_cmd = OPE_CFG; + configure_info.private_data = (void *)&led_gpio_param; + ret = BusDrvConfigure(pin->owner_driver, &configure_info); + if (ret != EOK) { + KPrintf("config pin %d failed!\n", IMXRT_GET_PIN(1, 9)); + return; + } + + while (1) { + + GpioLedDelay(); + + if (pinSet) { + /* set led pin as high*/ + led_gpio_stat.pin = IMXRT_GET_PIN(1, 9); + led_gpio_stat.val = GPIO_HIGH; + write_param.buffer = (void *)&led_gpio_stat; + BusDevWriteData(pin->owner_haldev, &write_param); + pinSet = 0; + } else { + /* set led pin as low*/ + led_gpio_stat.pin = IMXRT_GET_PIN(1, 9); + led_gpio_stat.val = GPIO_LOW; + write_param.buffer = (void *)&led_gpio_stat; + BusDevWriteData(pin->owner_haldev, &write_param); + pinSet = 1; + } + + } +} +SHELL_EXPORT_CMD(SHELL_CMD_PERMISSION(0)|SHELL_CMD_TYPE(SHELL_TYPE_CMD_MAIN), + GpioLedTest, GpioLedTest, GpioLedTest GPIO1 IO09 LED); +#endif diff --git a/Ubiquitous/XiZi/board/xidatong/third_party_driver/include/MIMXRT1052.h b/Ubiquitous/XiZi/board/xidatong/third_party_driver/include/MIMXRT1052.h new file mode 100755 index 0000000..552c36a --- /dev/null +++ b/Ubiquitous/XiZi/board/xidatong/third_party_driver/include/MIMXRT1052.h @@ -0,0 +1,42538 @@ +/* +** ################################################################### +** Processors: MIMXRT1052CVJ5B +** MIMXRT1052CVL5B +** MIMXRT1052DVJ6B +** MIMXRT1052DVL6B +** +** Compilers: Freescale C/C++ for Embedded ARM +** GNU C Compiler +** IAR ANSI C/C++ Compiler for ARM +** Keil ARM C/C++ Compiler +** MCUXpresso Compiler +** +** Reference manual: IMXRT1050RM Rev.2.1, 12/2018 +** Version: rev. 1.2, 2018-11-27 +** Build: b181205 +** +** Abstract: +** CMSIS Peripheral Access Layer for MIMXRT1052 +** +** Copyright 1997-2016 Freescale Semiconductor, Inc. +** Copyright 2016-2018 NXP +** All rights reserved. +** +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** Revisions: +** - rev. 0.1 (2017-01-10) +** Initial version. +** - rev. 1.0 (2018-09-21) +** Update interrupt vector table and dma request source. +** Update register BEE_ADDR_OFFSET1's bitfield name to ADDR_OFFSET1. +** Split GPIO_COMBINED_IRQS to GPIO_COMBINED_LOW_IRQS and GPIO_COMBINED_HIGH_IRQS. +** - rev. 1.1 (2018-11-16) +** Update header files to align with IMXRT1050RM Rev.1. +** - rev. 1.2 (2018-11-27) +** Update header files to align with IMXRT1050RM Rev.2.1. +** +** ################################################################### +*/ + +/*! + * @file MIMXRT1052.h + * @version 1.2 + * @date 2018-11-27 + * @brief CMSIS Peripheral Access Layer for MIMXRT1052 + * + * CMSIS Peripheral Access Layer for MIMXRT1052 + */ + +#ifndef _MIMXRT1052_H_ +#define _MIMXRT1052_H_ /**< Symbol preventing repeated inclusion */ + +/** Memory map major version (memory maps with equal major version number are + * compatible) */ +#define MCU_MEM_MAP_VERSION 0x0100U +/** Memory map minor version */ +#define MCU_MEM_MAP_VERSION_MINOR 0x0002U + + +/* ---------------------------------------------------------------------------- + -- Interrupt vector numbers + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup Interrupt_vector_numbers Interrupt vector numbers + * @{ + */ + +/** Interrupt Number Definitions */ +#define NUMBER_OF_INT_VECTORS 168 /**< Number of interrupts in the Vector table */ + +typedef enum IRQn { + /* Auxiliary constants */ + NotAvail_IRQn = -128, /**< Not available device specific interrupt */ + + /* Core interrupts */ + NonMaskableInt_IRQn = -14, /**< Non Maskable Interrupt */ + HardFault_IRQn = -13, /**< Cortex-M7 SV Hard Fault Interrupt */ + MemoryManagement_IRQn = -12, /**< Cortex-M7 Memory Management Interrupt */ + BusFault_IRQn = -11, /**< Cortex-M7 Bus Fault Interrupt */ + UsageFault_IRQn = -10, /**< Cortex-M7 Usage Fault Interrupt */ + SVCall_IRQn = -5, /**< Cortex-M7 SV Call Interrupt */ + DebugMonitor_IRQn = -4, /**< Cortex-M7 Debug Monitor Interrupt */ + PendSV_IRQn = -2, /**< Cortex-M7 Pend SV Interrupt */ + SysTick_IRQn = -1, /**< Cortex-M7 System Tick Interrupt */ + + /* Device specific interrupts */ + DMA0_DMA16_IRQn = 0, /**< DMA channel 0/16 transfer complete */ + DMA1_DMA17_IRQn = 1, /**< DMA channel 1/17 transfer complete */ + DMA2_DMA18_IRQn = 2, /**< DMA channel 2/18 transfer complete */ + DMA3_DMA19_IRQn = 3, /**< DMA channel 3/19 transfer complete */ + DMA4_DMA20_IRQn = 4, /**< DMA channel 4/20 transfer complete */ + DMA5_DMA21_IRQn = 5, /**< DMA channel 5/21 transfer complete */ + DMA6_DMA22_IRQn = 6, /**< DMA channel 6/22 transfer complete */ + DMA7_DMA23_IRQn = 7, /**< DMA channel 7/23 transfer complete */ + DMA8_DMA24_IRQn = 8, /**< DMA channel 8/24 transfer complete */ + DMA9_DMA25_IRQn = 9, /**< DMA channel 9/25 transfer complete */ + DMA10_DMA26_IRQn = 10, /**< DMA channel 10/26 transfer complete */ + DMA11_DMA27_IRQn = 11, /**< DMA channel 11/27 transfer complete */ + DMA12_DMA28_IRQn = 12, /**< DMA channel 12/28 transfer complete */ + DMA13_DMA29_IRQn = 13, /**< DMA channel 13/29 transfer complete */ + DMA14_DMA30_IRQn = 14, /**< DMA channel 14/30 transfer complete */ + DMA15_DMA31_IRQn = 15, /**< DMA channel 15/31 transfer complete */ + DMA_ERROR_IRQn = 16, /**< DMA error interrupt channels 0-15 / 16-31 */ + CTI0_ERROR_IRQn = 17, /**< CTI0_Error */ + CTI1_ERROR_IRQn = 18, /**< CTI1_Error */ + CORE_IRQn = 19, /**< CorePlatform exception IRQ */ + LPUART1_IRQn = 20, /**< LPUART1 TX interrupt and RX interrupt */ + LPUART2_IRQn = 21, /**< LPUART2 TX interrupt and RX interrupt */ + LPUART3_IRQn = 22, /**< LPUART3 TX interrupt and RX interrupt */ + LPUART4_IRQn = 23, /**< LPUART4 TX interrupt and RX interrupt */ + LPUART5_IRQn = 24, /**< LPUART5 TX interrupt and RX interrupt */ + LPUART6_IRQn = 25, /**< LPUART6 TX interrupt and RX interrupt */ + LPUART7_IRQn = 26, /**< LPUART7 TX interrupt and RX interrupt */ + LPUART8_IRQn = 27, /**< LPUART8 TX interrupt and RX interrupt */ + LPI2C1_IRQn = 28, /**< LPI2C1 interrupt */ + LPI2C2_IRQn = 29, /**< LPI2C2 interrupt */ + LPI2C3_IRQn = 30, /**< LPI2C3 interrupt */ + LPI2C4_IRQn = 31, /**< LPI2C4 interrupt */ + LPSPI1_IRQn = 32, /**< LPSPI1 single interrupt vector for all sources */ + LPSPI2_IRQn = 33, /**< LPSPI2 single interrupt vector for all sources */ + LPSPI3_IRQn = 34, /**< LPSPI3 single interrupt vector for all sources */ + LPSPI4_IRQn = 35, /**< LPSPI4 single interrupt vector for all sources */ + CAN1_IRQn = 36, /**< CAN1 interrupt */ + CAN2_IRQn = 37, /**< CAN2 interrupt */ + FLEXRAM_IRQn = 38, /**< FlexRAM address out of range Or access hit IRQ */ + KPP_IRQn = 39, /**< Keypad nterrupt */ + TSC_DIG_IRQn = 40, /**< TSC interrupt */ + GPR_IRQ_IRQn = 41, /**< GPR interrupt */ + LCDIF_IRQn = 42, /**< LCDIF interrupt */ + CSI_IRQn = 43, /**< CSI interrupt */ + PXP_IRQn = 44, /**< PXP interrupt */ + WDOG2_IRQn = 45, /**< WDOG2 interrupt */ + SNVS_HP_WRAPPER_IRQn = 46, /**< SRTC Consolidated Interrupt. Non TZ */ + SNVS_HP_WRAPPER_TZ_IRQn = 47, /**< SRTC Security Interrupt. TZ */ + SNVS_LP_WRAPPER_IRQn = 48, /**< ON-OFF button press shorter than 5 secs (pulse event) */ + CSU_IRQn = 49, /**< CSU interrupt */ + DCP_IRQn = 50, /**< DCP_IRQ interrupt */ + DCP_VMI_IRQn = 51, /**< DCP_VMI_IRQ interrupt */ + Reserved68_IRQn = 52, /**< Reserved interrupt */ + TRNG_IRQn = 53, /**< TRNG interrupt */ + SJC_IRQn = 54, /**< SJC interrupt */ + BEE_IRQn = 55, /**< BEE interrupt */ + SAI1_IRQn = 56, /**< SAI1 interrupt */ + SAI2_IRQn = 57, /**< SAI1 interrupt */ + SAI3_RX_IRQn = 58, /**< SAI3 interrupt */ + SAI3_TX_IRQn = 59, /**< SAI3 interrupt */ + SPDIF_IRQn = 60, /**< SPDIF interrupt */ + PMU_EVENT_IRQn = 61, /**< Brown-out event interrupt */ + Reserved78_IRQn = 62, /**< Reserved interrupt */ + TEMP_LOW_HIGH_IRQn = 63, /**< TempSensor low/high interrupt */ + TEMP_PANIC_IRQn = 64, /**< TempSensor panic interrupt */ + USB_PHY1_IRQn = 65, /**< USBPHY (UTMI0), Interrupt */ + USB_PHY2_IRQn = 66, /**< USBPHY (UTMI0), Interrupt */ + ADC1_IRQn = 67, /**< ADC1 interrupt */ + ADC2_IRQn = 68, /**< ADC2 interrupt */ + DCDC_IRQn = 69, /**< DCDC interrupt */ + Reserved86_IRQn = 70, /**< Reserved interrupt */ + Reserved87_IRQn = 71, /**< Reserved interrupt */ + GPIO1_INT0_IRQn = 72, /**< Active HIGH Interrupt from INT0 from GPIO */ + GPIO1_INT1_IRQn = 73, /**< Active HIGH Interrupt from INT1 from GPIO */ + GPIO1_INT2_IRQn = 74, /**< Active HIGH Interrupt from INT2 from GPIO */ + GPIO1_INT3_IRQn = 75, /**< Active HIGH Interrupt from INT3 from GPIO */ + GPIO1_INT4_IRQn = 76, /**< Active HIGH Interrupt from INT4 from GPIO */ + GPIO1_INT5_IRQn = 77, /**< Active HIGH Interrupt from INT5 from GPIO */ + GPIO1_INT6_IRQn = 78, /**< Active HIGH Interrupt from INT6 from GPIO */ + GPIO1_INT7_IRQn = 79, /**< Active HIGH Interrupt from INT7 from GPIO */ + GPIO1_Combined_0_15_IRQn = 80, /**< Combined interrupt indication for GPIO1 signal 0 throughout 15 */ + GPIO1_Combined_16_31_IRQn = 81, /**< Combined interrupt indication for GPIO1 signal 16 throughout 31 */ + GPIO2_Combined_0_15_IRQn = 82, /**< Combined interrupt indication for GPIO2 signal 0 throughout 15 */ + GPIO2_Combined_16_31_IRQn = 83, /**< Combined interrupt indication for GPIO2 signal 16 throughout 31 */ + GPIO3_Combined_0_15_IRQn = 84, /**< Combined interrupt indication for GPIO3 signal 0 throughout 15 */ + GPIO3_Combined_16_31_IRQn = 85, /**< Combined interrupt indication for GPIO3 signal 16 throughout 31 */ + GPIO4_Combined_0_15_IRQn = 86, /**< Combined interrupt indication for GPIO4 signal 0 throughout 15 */ + GPIO4_Combined_16_31_IRQn = 87, /**< Combined interrupt indication for GPIO4 signal 16 throughout 31 */ + GPIO5_Combined_0_15_IRQn = 88, /**< Combined interrupt indication for GPIO5 signal 0 throughout 15 */ + GPIO5_Combined_16_31_IRQn = 89, /**< Combined interrupt indication for GPIO5 signal 16 throughout 31 */ + FLEXIO1_IRQn = 90, /**< FLEXIO1 interrupt */ + FLEXIO2_IRQn = 91, /**< FLEXIO2 interrupt */ + WDOG1_IRQn = 92, /**< WDOG1 interrupt */ + RTWDOG_IRQn = 93, /**< RTWDOG interrupt */ + EWM_IRQn = 94, /**< EWM interrupt */ + CCM_1_IRQn = 95, /**< CCM IRQ1 interrupt */ + CCM_2_IRQn = 96, /**< CCM IRQ2 interrupt */ + GPC_IRQn = 97, /**< GPC interrupt */ + SRC_IRQn = 98, /**< SRC interrupt */ + Reserved115_IRQn = 99, /**< Reserved interrupt */ + GPT1_IRQn = 100, /**< GPT1 interrupt */ + GPT2_IRQn = 101, /**< GPT2 interrupt */ + PWM1_0_IRQn = 102, /**< PWM1 capture 0, compare 0, or reload 0 interrupt */ + PWM1_1_IRQn = 103, /**< PWM1 capture 1, compare 1, or reload 0 interrupt */ + PWM1_2_IRQn = 104, /**< PWM1 capture 2, compare 2, or reload 0 interrupt */ + PWM1_3_IRQn = 105, /**< PWM1 capture 3, compare 3, or reload 0 interrupt */ + PWM1_FAULT_IRQn = 106, /**< PWM1 fault or reload error interrupt */ + Reserved123_IRQn = 107, /**< Reserved interrupt */ + FLEXSPI_IRQn = 108, /**< FlexSPI0 interrupt */ + SEMC_IRQn = 109, /**< Reserved interrupt */ + USDHC1_IRQn = 110, /**< USDHC1 interrupt */ + USDHC2_IRQn = 111, /**< USDHC2 interrupt */ + USB_OTG2_IRQn = 112, /**< USBO2 USB OTG2 */ + USB_OTG1_IRQn = 113, /**< USBO2 USB OTG1 */ + ENET_IRQn = 114, /**< ENET interrupt */ + ENET_1588_Timer_IRQn = 115, /**< ENET_1588_Timer interrupt */ + XBAR1_IRQ_0_1_IRQn = 116, /**< XBAR1 interrupt */ + XBAR1_IRQ_2_3_IRQn = 117, /**< XBAR1 interrupt */ + ADC_ETC_IRQ0_IRQn = 118, /**< ADCETC IRQ0 interrupt */ + ADC_ETC_IRQ1_IRQn = 119, /**< ADCETC IRQ1 interrupt */ + ADC_ETC_IRQ2_IRQn = 120, /**< ADCETC IRQ2 interrupt */ + ADC_ETC_ERROR_IRQ_IRQn = 121, /**< ADCETC Error IRQ interrupt */ + PIT_IRQn = 122, /**< PIT interrupt */ + ACMP1_IRQn = 123, /**< ACMP interrupt */ + ACMP2_IRQn = 124, /**< ACMP interrupt */ + ACMP3_IRQn = 125, /**< ACMP interrupt */ + ACMP4_IRQn = 126, /**< ACMP interrupt */ + Reserved143_IRQn = 127, /**< Reserved interrupt */ + Reserved144_IRQn = 128, /**< Reserved interrupt */ + ENC1_IRQn = 129, /**< ENC1 interrupt */ + ENC2_IRQn = 130, /**< ENC2 interrupt */ + ENC3_IRQn = 131, /**< ENC3 interrupt */ + ENC4_IRQn = 132, /**< ENC4 interrupt */ + TMR1_IRQn = 133, /**< TMR1 interrupt */ + TMR2_IRQn = 134, /**< TMR2 interrupt */ + TMR3_IRQn = 135, /**< TMR3 interrupt */ + TMR4_IRQn = 136, /**< TMR4 interrupt */ + PWM2_0_IRQn = 137, /**< PWM2 capture 0, compare 0, or reload 0 interrupt */ + PWM2_1_IRQn = 138, /**< PWM2 capture 1, compare 1, or reload 0 interrupt */ + PWM2_2_IRQn = 139, /**< PWM2 capture 2, compare 2, or reload 0 interrupt */ + PWM2_3_IRQn = 140, /**< PWM2 capture 3, compare 3, or reload 0 interrupt */ + PWM2_FAULT_IRQn = 141, /**< PWM2 fault or reload error interrupt */ + PWM3_0_IRQn = 142, /**< PWM3 capture 0, compare 0, or reload 0 interrupt */ + PWM3_1_IRQn = 143, /**< PWM3 capture 1, compare 1, or reload 0 interrupt */ + PWM3_2_IRQn = 144, /**< PWM3 capture 2, compare 2, or reload 0 interrupt */ + PWM3_3_IRQn = 145, /**< PWM3 capture 3, compare 3, or reload 0 interrupt */ + PWM3_FAULT_IRQn = 146, /**< PWM3 fault or reload error interrupt */ + PWM4_0_IRQn = 147, /**< PWM4 capture 0, compare 0, or reload 0 interrupt */ + PWM4_1_IRQn = 148, /**< PWM4 capture 1, compare 1, or reload 0 interrupt */ + PWM4_2_IRQn = 149, /**< PWM4 capture 2, compare 2, or reload 0 interrupt */ + PWM4_3_IRQn = 150, /**< PWM4 capture 3, compare 3, or reload 0 interrupt */ + PWM4_FAULT_IRQn = 151 /**< PWM4 fault or reload error interrupt */ +} IRQn_Type; + +/*! + * @} + */ /* end of group Interrupt_vector_numbers */ + + +/* ---------------------------------------------------------------------------- + -- Cortex M7 Core Configuration + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup Cortex_Core_Configuration Cortex M7 Core Configuration + * @{ + */ + +#define __MPU_PRESENT 1 /**< Defines if an MPU is present or not */ +#define __ICACHE_PRESENT 1 /**< Defines if an ICACHE is present or not */ +#define __DCACHE_PRESENT 1 /**< Defines if an DCACHE is present or not */ +#define __DTCM_PRESENT 1 /**< Defines if an DTCM is present or not */ +#define __NVIC_PRIO_BITS 4 /**< Number of priority bits implemented in the NVIC */ +#define __Vendor_SysTickConfig 0 /**< Vendor specific implementation of SysTickConfig is defined */ +#define __FPU_PRESENT 1 /**< Defines if an FPU is present or not */ + +#include "core_cm7.h" /* Core Peripheral Access Layer */ +#include "system_MIMXRT1052.h" /* Device specific configuration file */ + +/*! + * @} + */ /* end of group Cortex_Core_Configuration */ + + +/* ---------------------------------------------------------------------------- + -- Mapping Information + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup Mapping_Information Mapping Information + * @{ + */ + +/** Mapping Information */ +/*! + * @addtogroup edma_request + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! + * @brief Structure for the DMA hardware request + * + * Defines the structure for the DMA hardware request collections. The user can configure the + * hardware request into DMAMUX to trigger the DMA transfer accordingly. The index + * of the hardware request varies according to the to SoC. + */ +typedef enum _dma_request_source +{ + kDmaRequestMuxFlexIO1Request0Request1 = 0|0x100U, /**< FlexIO1 Request0 and Request1 */ + kDmaRequestMuxFlexIO2Request0Request1 = 1|0x100U, /**< FlexIO2 Request0 and Request1 */ + kDmaRequestMuxLPUART1Tx = 2|0x100U, /**< LPUART1 Transmit */ + kDmaRequestMuxLPUART1Rx = 3|0x100U, /**< LPUART1 Receive */ + kDmaRequestMuxLPUART3Tx = 4|0x100U, /**< LPUART3 Transmit */ + kDmaRequestMuxLPUART3Rx = 5|0x100U, /**< LPUART3 Receive */ + kDmaRequestMuxLPUART5Tx = 6|0x100U, /**< LPUART5 Transmit */ + kDmaRequestMuxLPUART5Rx = 7|0x100U, /**< LPUART5 Receive */ + kDmaRequestMuxLPUART7Tx = 8|0x100U, /**< LPUART7 Transmit */ + kDmaRequestMuxLPUART7Rx = 9|0x100U, /**< LPUART7 Receive */ + kDmaRequestMuxCSI = 12|0x100U, /**< CSI */ + kDmaRequestMuxLPSPI1Rx = 13|0x100U, /**< LPSPI1 Receive */ + kDmaRequestMuxLPSPI1Tx = 14|0x100U, /**< LPSPI1 Transmit */ + kDmaRequestMuxLPSPI3Rx = 15|0x100U, /**< LPSPI3 Receive */ + kDmaRequestMuxLPSPI3Tx = 16|0x100U, /**< LPSPI3 Transmit */ + kDmaRequestMuxLPI2C1 = 17|0x100U, /**< LPI2C1 */ + kDmaRequestMuxLPI2C3 = 18|0x100U, /**< LPI2C3 */ + kDmaRequestMuxSai1Rx = 19|0x100U, /**< SAI1 Receive */ + kDmaRequestMuxSai1Tx = 20|0x100U, /**< SAI1 Transmit */ + kDmaRequestMuxSai2Rx = 21|0x100U, /**< SAI2 Receive */ + kDmaRequestMuxSai2Tx = 22|0x100U, /**< SAI2 Transmit */ + kDmaRequestMuxADC_ETC = 23|0x100U, /**< ADC_ETC */ + kDmaRequestMuxADC1 = 24|0x100U, /**< ADC1 */ + kDmaRequestMuxACMP1 = 25|0x100U, /**< ACMP1 */ + kDmaRequestMuxACMP3 = 26|0x100U, /**< ACMP3 */ + kDmaRequestMuxFlexSPIRx = 28|0x100U, /**< FlexSPI Receive */ + kDmaRequestMuxFlexSPITx = 29|0x100U, /**< FlexSPI Transmit */ + kDmaRequestMuxXBAR1Request0 = 30|0x100U, /**< XBAR1 Request 0 */ + kDmaRequestMuxXBAR1Request1 = 31|0x100U, /**< XBAR1 Request 1 */ + kDmaRequestMuxFlexPWM1CaptureSub0 = 32|0x100U, /**< FlexPWM1 Capture sub-module0 */ + kDmaRequestMuxFlexPWM1CaptureSub1 = 33|0x100U, /**< FlexPWM1 Capture sub-module1 */ + kDmaRequestMuxFlexPWM1CaptureSub2 = 34|0x100U, /**< FlexPWM1 Capture sub-module2 */ + kDmaRequestMuxFlexPWM1CaptureSub3 = 35|0x100U, /**< FlexPWM1 Capture sub-module3 */ + kDmaRequestMuxFlexPWM1ValueSub0 = 36|0x100U, /**< FlexPWM1 Value sub-module0 */ + kDmaRequestMuxFlexPWM1ValueSub1 = 37|0x100U, /**< FlexPWM1 Value sub-module1 */ + kDmaRequestMuxFlexPWM1ValueSub2 = 38|0x100U, /**< FlexPWM1 Value sub-module2 */ + kDmaRequestMuxFlexPWM1ValueSub3 = 39|0x100U, /**< FlexPWM1 Value sub-module3 */ + kDmaRequestMuxFlexPWM3CaptureSub0 = 40|0x100U, /**< FlexPWM3 Capture sub-module0 */ + kDmaRequestMuxFlexPWM3CaptureSub1 = 41|0x100U, /**< FlexPWM3 Capture sub-module1 */ + kDmaRequestMuxFlexPWM3CaptureSub2 = 42|0x100U, /**< FlexPWM3 Capture sub-module2 */ + kDmaRequestMuxFlexPWM3CaptureSub3 = 43|0x100U, /**< FlexPWM3 Capture sub-module3 */ + kDmaRequestMuxFlexPWM3ValueSub0 = 44|0x100U, /**< FlexPWM3 Value sub-module0 */ + kDmaRequestMuxFlexPWM3ValueSub1 = 45|0x100U, /**< FlexPWM3 Value sub-module1 */ + kDmaRequestMuxFlexPWM3ValueSub2 = 46|0x100U, /**< FlexPWM3 Value sub-module2 */ + kDmaRequestMuxFlexPWM3ValueSub3 = 47|0x100U, /**< FlexPWM3 Value sub-module3 */ + kDmaRequestMuxQTIMER1CaptTimer0 = 48|0x100U, /**< TMR1 Capture timer 0 */ + kDmaRequestMuxQTIMER1CaptTimer1 = 49|0x100U, /**< TMR1 Capture timer 1 */ + kDmaRequestMuxQTIMER1CaptTimer2 = 50|0x100U, /**< TMR1 Capture timer 2 */ + kDmaRequestMuxQTIMER1CaptTimer3 = 51|0x100U, /**< TMR1 Capture timer 3 */ + kDmaRequestMuxQTIMER1Cmpld1Timer0Cmpld2Timer1 = 52|0x100U, /**< TMR1 cmpld1 in timer 0 or cmpld2 in timer 1 */ + kDmaRequestMuxQTIMER1Cmpld1Timer1Cmpld2Timer0 = 53|0x100U, /**< TMR1 cmpld1 in timer 1 or cmpld2 in timer 0 */ + kDmaRequestMuxQTIMER1Cmpld1Timer2Cmpld2Timer3 = 54|0x100U, /**< TMR1 cmpld1 in timer 2 or cmpld2 in timer 3 */ + kDmaRequestMuxQTIMER1Cmpld1Timer3Cmpld2Timer2 = 55|0x100U, /**< TMR1 cmpld1 in timer 3 or cmpld2 in timer 2 */ + kDmaRequestMuxQTIMER3CaptTimer0Cmpld1Timer0Cmpld2Timer1 = 56|0x100U, /**< TMR3 capture timer 0, cmpld1 in timer 0 or cmpld2 in timer 1 */ + kDmaRequestMuxQTIMER3CaptTimer1Cmpld1Timer1Cmpld2Timer0 = 57|0x100U, /**< TMR3 capture timer 1, cmpld1 in timer 1 or cmpld2 in timer 0 */ + kDmaRequestMuxQTIMER3CaptTimer2Cmpld1Timer2Cmpld2Timer3 = 58|0x100U, /**< TMR3 capture timer 2, cmpld1 in timer 2 or cmpld2 in timer 3 */ + kDmaRequestMuxQTIMER3CaptTimer3Cmpld1Timer3Cmpld2Timer2 = 59|0x100U, /**< TMR3 capture timer 3, cmpld1 in timer 3 or cmpld2 in timer 2 */ + kDmaRequestMuxFlexIO1Request2Request3 = 64|0x100U, /**< FlexIO1 Request2 and Request3 */ + kDmaRequestMuxFlexIO2Request2Request3 = 65|0x100U, /**< FlexIO2 Request2 and Request3 */ + kDmaRequestMuxLPUART2Tx = 66|0x100U, /**< LPUART2 Transmit */ + kDmaRequestMuxLPUART2Rx = 67|0x100U, /**< LPUART2 Receive */ + kDmaRequestMuxLPUART4Tx = 68|0x100U, /**< LPUART4 Transmit */ + kDmaRequestMuxLPUART4Rx = 69|0x100U, /**< LPUART4 Receive */ + kDmaRequestMuxLPUART6Tx = 70|0x100U, /**< LPUART6 Transmit */ + kDmaRequestMuxLPUART6Rx = 71|0x100U, /**< LPUART6 Receive */ + kDmaRequestMuxLPUART8Tx = 72|0x100U, /**< LPUART8 Transmit */ + kDmaRequestMuxLPUART8Rx = 73|0x100U, /**< LPUART8 Receive */ + kDmaRequestMuxPxp = 75|0x100U, /**< PXP */ + kDmaRequestMuxLCDIF = 76|0x100U, /**< LCDIF */ + kDmaRequestMuxLPSPI2Rx = 77|0x100U, /**< LPSPI2 Receive */ + kDmaRequestMuxLPSPI2Tx = 78|0x100U, /**< LPSPI2 Transmit */ + kDmaRequestMuxLPSPI4Rx = 79|0x100U, /**< LPSPI4 Receive */ + kDmaRequestMuxLPSPI4Tx = 80|0x100U, /**< LPSPI4 Transmit */ + kDmaRequestMuxLPI2C2 = 81|0x100U, /**< LPI2C2 */ + kDmaRequestMuxLPI2C4 = 82|0x100U, /**< LPI2C4 */ + kDmaRequestMuxSai3Rx = 83|0x100U, /**< SAI3 Receive */ + kDmaRequestMuxSai3Tx = 84|0x100U, /**< SAI3 Transmit */ + kDmaRequestMuxSpdifRx = 85|0x100U, /**< SPDIF Receive */ + kDmaRequestMuxSpdifTx = 86|0x100U, /**< SPDIF Transmit */ + kDmaRequestMuxADC2 = 88|0x100U, /**< ADC2 */ + kDmaRequestMuxACMP2 = 89|0x100U, /**< ACMP2 */ + kDmaRequestMuxACMP4 = 90|0x100U, /**< ACMP4 */ + kDmaRequestMuxEnetTimer0 = 92|0x100U, /**< ENET Timer0 */ + kDmaRequestMuxEnetTimer1 = 93|0x100U, /**< ENET Timer1 */ + kDmaRequestMuxXBAR1Request2 = 94|0x100U, /**< XBAR1 Request 2 */ + kDmaRequestMuxXBAR1Request3 = 95|0x100U, /**< XBAR1 Request 3 */ + kDmaRequestMuxFlexPWM2CaptureSub0 = 96|0x100U, /**< FlexPWM2 Capture sub-module0 */ + kDmaRequestMuxFlexPWM2CaptureSub1 = 97|0x100U, /**< FlexPWM2 Capture sub-module1 */ + kDmaRequestMuxFlexPWM2CaptureSub2 = 98|0x100U, /**< FlexPWM2 Capture sub-module2 */ + kDmaRequestMuxFlexPWM2CaptureSub3 = 99|0x100U, /**< FlexPWM2 Capture sub-module3 */ + kDmaRequestMuxFlexPWM2ValueSub0 = 100|0x100U, /**< FlexPWM2 Value sub-module0 */ + kDmaRequestMuxFlexPWM2ValueSub1 = 101|0x100U, /**< FlexPWM2 Value sub-module1 */ + kDmaRequestMuxFlexPWM2ValueSub2 = 102|0x100U, /**< FlexPWM2 Value sub-module2 */ + kDmaRequestMuxFlexPWM2ValueSub3 = 103|0x100U, /**< FlexPWM2 Value sub-module3 */ + kDmaRequestMuxFlexPWM4CaptureSub0 = 104|0x100U, /**< FlexPWM4 Capture sub-module0 */ + kDmaRequestMuxFlexPWM4CaptureSub1 = 105|0x100U, /**< FlexPWM4 Capture sub-module1 */ + kDmaRequestMuxFlexPWM4CaptureSub2 = 106|0x100U, /**< FlexPWM4 Capture sub-module2 */ + kDmaRequestMuxFlexPWM4CaptureSub3 = 107|0x100U, /**< FlexPWM4 Capture sub-module3 */ + kDmaRequestMuxFlexPWM4ValueSub0 = 108|0x100U, /**< FlexPWM4 Value sub-module0 */ + kDmaRequestMuxFlexPWM4ValueSub1 = 109|0x100U, /**< FlexPWM4 Value sub-module1 */ + kDmaRequestMuxFlexPWM4ValueSub2 = 110|0x100U, /**< FlexPWM4 Value sub-module2 */ + kDmaRequestMuxFlexPWM4ValueSub3 = 111|0x100U, /**< FlexPWM4 Value sub-module3 */ + kDmaRequestMuxQTIMER2CaptTimer0 = 112|0x100U, /**< TMR2 Capture timer 0 */ + kDmaRequestMuxQTIMER2CaptTimer1 = 113|0x100U, /**< TMR2 Capture timer 1 */ + kDmaRequestMuxQTIMER2CaptTimer2 = 114|0x100U, /**< TMR2 Capture timer 2 */ + kDmaRequestMuxQTIMER2CaptTimer3 = 115|0x100U, /**< TMR2 Capture timer 3 */ + kDmaRequestMuxQTIMER2Cmpld1Timer0Cmpld2Timer1 = 116|0x100U, /**< TMR2 cmpld1 in timer 0 or cmpld2 in timer 1 */ + kDmaRequestMuxQTIMER2Cmpld1Timer1Cmpld2Timer0 = 117|0x100U, /**< TMR2 cmpld1 in timer 1 or cmpld2 in timer 0 */ + kDmaRequestMuxQTIMER2Cmpld1Timer2Cmpld2Timer3 = 118|0x100U, /**< TMR2 cmpld1 in timer 2 or cmpld2 in timer 3 */ + kDmaRequestMuxQTIMER2Cmpld1Timer3Cmpld2Timer2 = 119|0x100U, /**< TMR2 cmpld1 in timer 3 or cmpld2 in timer 2 */ + kDmaRequestMuxQTIMER4CaptTimer0Cmpld1Timer0Cmpld2Timer1 = 120|0x100U, /**< TMR4 capture timer 0, cmpld1 in timer 0 or cmpld2 in timer 1 */ + kDmaRequestMuxQTIMER4CaptTimer1Cmpld1Timer1Cmpld2Timer0 = 121|0x100U, /**< TMR4 capture timer 1, cmpld1 in timer 1 or cmpld2 in timer 0 */ + kDmaRequestMuxQTIMER4CaptTimer2Cmpld1Timer2Cmpld2Timer3 = 122|0x100U, /**< TMR4 capture timer 2, cmpld1 in timer 2 or cmpld2 in timer 3 */ + kDmaRequestMuxQTIMER4CaptTimer3Cmpld1Timer3Cmpld2Timer2 = 123|0x100U, /**< TMR4 capture timer 3, cmpld1 in timer 3 or cmpld2 in timer 2 */ +} dma_request_source_t; + +/* @} */ + +/*! + * @addtogroup iomuxc_pads + * @{ */ + +/******************************************************************************* + * Definitions +*******************************************************************************/ + +/*! + * @brief Enumeration for the IOMUXC SW_MUX_CTL_PAD + * + * Defines the enumeration for the IOMUXC SW_MUX_CTL_PAD collections. + */ +typedef enum _iomuxc_sw_mux_ctl_pad +{ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_00 = 0U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_01 = 1U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_02 = 2U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_03 = 3U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_04 = 4U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_05 = 5U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_06 = 6U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_07 = 7U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_08 = 8U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_09 = 9U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_10 = 10U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_11 = 11U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_12 = 12U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_13 = 13U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_14 = 14U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_15 = 15U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_16 = 16U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_17 = 17U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_18 = 18U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_19 = 19U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_20 = 20U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_21 = 21U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_22 = 22U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_23 = 23U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_24 = 24U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_25 = 25U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_26 = 26U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_27 = 27U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_28 = 28U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_29 = 29U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_30 = 30U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_31 = 31U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_32 = 32U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_33 = 33U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_34 = 34U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_35 = 35U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_36 = 36U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_37 = 37U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_38 = 38U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_39 = 39U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_40 = 40U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_41 = 41U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_00 = 42U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_01 = 43U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_02 = 44U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_03 = 45U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_04 = 46U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_05 = 47U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_06 = 48U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_07 = 49U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_08 = 50U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_09 = 51U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_10 = 52U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_11 = 53U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_12 = 54U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_13 = 55U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_14 = 56U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_15 = 57U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_00 = 58U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_01 = 59U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_02 = 60U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_03 = 61U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_04 = 62U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_05 = 63U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_06 = 64U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_07 = 65U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_08 = 66U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_09 = 67U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_10 = 68U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_11 = 69U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_12 = 70U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_13 = 71U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_14 = 72U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_15 = 73U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_B0_00 = 74U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_B0_01 = 75U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_B0_02 = 76U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_B0_03 = 77U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_B0_04 = 78U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_B0_05 = 79U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_B0_06 = 80U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_B0_07 = 81U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_B0_08 = 82U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_B0_09 = 83U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_B0_10 = 84U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_B0_11 = 85U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_B0_12 = 86U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_B0_13 = 87U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_B0_14 = 88U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_B0_15 = 89U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_00 = 90U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_01 = 91U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_02 = 92U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_03 = 93U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_04 = 94U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_05 = 95U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_06 = 96U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_07 = 97U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_08 = 98U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_09 = 99U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_10 = 100U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_11 = 101U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_12 = 102U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_13 = 103U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_14 = 104U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_15 = 105U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B0_00 = 106U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B0_01 = 107U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B0_02 = 108U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B0_03 = 109U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B0_04 = 110U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B0_05 = 111U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_00 = 112U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_01 = 113U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_02 = 114U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_03 = 115U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_04 = 116U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_05 = 117U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_06 = 118U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_07 = 119U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_08 = 120U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_09 = 121U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_10 = 122U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_11 = 123U, /**< IOMUXC SW_MUX_CTL_PAD index */ +} iomuxc_sw_mux_ctl_pad_t; + +/* @} */ + +/*! + * @addtogroup iomuxc_pads + * @{ */ + +/******************************************************************************* + * Definitions +*******************************************************************************/ + +/*! + * @brief Enumeration for the IOMUXC SW_PAD_CTL_PAD + * + * Defines the enumeration for the IOMUXC SW_PAD_CTL_PAD collections. + */ +typedef enum _iomuxc_sw_pad_ctl_pad +{ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_00 = 0U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_01 = 1U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_02 = 2U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_03 = 3U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_04 = 4U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_05 = 5U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_06 = 6U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_07 = 7U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_08 = 8U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_09 = 9U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_10 = 10U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_11 = 11U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_12 = 12U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_13 = 13U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_14 = 14U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_15 = 15U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_16 = 16U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_17 = 17U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_18 = 18U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_19 = 19U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_20 = 20U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_21 = 21U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_22 = 22U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_23 = 23U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_24 = 24U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_25 = 25U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_26 = 26U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_27 = 27U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_28 = 28U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_29 = 29U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_30 = 30U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_31 = 31U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_32 = 32U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_33 = 33U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_34 = 34U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_35 = 35U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_36 = 36U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_37 = 37U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_38 = 38U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_39 = 39U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_40 = 40U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_41 = 41U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_00 = 42U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_01 = 43U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_02 = 44U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_03 = 45U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_04 = 46U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_05 = 47U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_06 = 48U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_07 = 49U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_08 = 50U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_09 = 51U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_10 = 52U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_11 = 53U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_12 = 54U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_13 = 55U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_14 = 56U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_15 = 57U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_00 = 58U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_01 = 59U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_02 = 60U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_03 = 61U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_04 = 62U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_05 = 63U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_06 = 64U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_07 = 65U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_08 = 66U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_09 = 67U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_10 = 68U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_11 = 69U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_12 = 70U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_13 = 71U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_14 = 72U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_15 = 73U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_B0_00 = 74U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_B0_01 = 75U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_B0_02 = 76U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_B0_03 = 77U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_B0_04 = 78U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_B0_05 = 79U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_B0_06 = 80U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_B0_07 = 81U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_B0_08 = 82U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_B0_09 = 83U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_B0_10 = 84U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_B0_11 = 85U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_B0_12 = 86U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_B0_13 = 87U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_B0_14 = 88U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_B0_15 = 89U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_00 = 90U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_01 = 91U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_02 = 92U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_03 = 93U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_04 = 94U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_05 = 95U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_06 = 96U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_07 = 97U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_08 = 98U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_09 = 99U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_10 = 100U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_11 = 101U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_12 = 102U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_13 = 103U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_14 = 104U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_15 = 105U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B0_00 = 106U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B0_01 = 107U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B0_02 = 108U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B0_03 = 109U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B0_04 = 110U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B0_05 = 111U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_00 = 112U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_01 = 113U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_02 = 114U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_03 = 115U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_04 = 116U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_05 = 117U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_06 = 118U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_07 = 119U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_08 = 120U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_09 = 121U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_10 = 122U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_11 = 123U, /**< IOMUXC SW_PAD_CTL_PAD index */ +} iomuxc_sw_pad_ctl_pad_t; + +/* @} */ + +/*! + * @brief Enumeration for the IOMUXC select input + * + * Defines the enumeration for the IOMUXC select input collections. + */ +typedef enum _iomuxc_select_input +{ + kIOMUXC_ANATOP_USB_OTG1_ID_SELECT_INPUT = 0U, /**< IOMUXC select input index */ + kIOMUXC_ANATOP_USB_OTG2_ID_SELECT_INPUT = 1U, /**< IOMUXC select input index */ + kIOMUXC_CCM_PMIC_READY_SELECT_INPUT = 2U, /**< IOMUXC select input index */ + kIOMUXC_CSI_DATA02_SELECT_INPUT = 3U, /**< IOMUXC select input index */ + kIOMUXC_CSI_DATA03_SELECT_INPUT = 4U, /**< IOMUXC select input index */ + kIOMUXC_CSI_DATA04_SELECT_INPUT = 5U, /**< IOMUXC select input index */ + kIOMUXC_CSI_DATA05_SELECT_INPUT = 6U, /**< IOMUXC select input index */ + kIOMUXC_CSI_DATA06_SELECT_INPUT = 7U, /**< IOMUXC select input index */ + kIOMUXC_CSI_DATA07_SELECT_INPUT = 8U, /**< IOMUXC select input index */ + kIOMUXC_CSI_DATA08_SELECT_INPUT = 9U, /**< IOMUXC select input index */ + kIOMUXC_CSI_DATA09_SELECT_INPUT = 10U, /**< IOMUXC select input index */ + kIOMUXC_CSI_HSYNC_SELECT_INPUT = 11U, /**< IOMUXC select input index */ + kIOMUXC_CSI_PIXCLK_SELECT_INPUT = 12U, /**< IOMUXC select input index */ + kIOMUXC_CSI_VSYNC_SELECT_INPUT = 13U, /**< IOMUXC select input index */ + kIOMUXC_ENET_IPG_CLK_RMII_SELECT_INPUT = 14U, /**< IOMUXC select input index */ + kIOMUXC_ENET_MDIO_SELECT_INPUT = 15U, /**< IOMUXC select input index */ + kIOMUXC_ENET0_RXDATA_SELECT_INPUT = 16U, /**< IOMUXC select input index */ + kIOMUXC_ENET1_RXDATA_SELECT_INPUT = 17U, /**< IOMUXC select input index */ + kIOMUXC_ENET_RXEN_SELECT_INPUT = 18U, /**< IOMUXC select input index */ + kIOMUXC_ENET_RXERR_SELECT_INPUT = 19U, /**< IOMUXC select input index */ + kIOMUXC_ENET0_TIMER_SELECT_INPUT = 20U, /**< IOMUXC select input index */ + kIOMUXC_ENET_TXCLK_SELECT_INPUT = 21U, /**< IOMUXC select input index */ + kIOMUXC_FLEXCAN1_RX_SELECT_INPUT = 22U, /**< IOMUXC select input index */ + kIOMUXC_FLEXCAN2_RX_SELECT_INPUT = 23U, /**< IOMUXC select input index */ + kIOMUXC_FLEXPWM1_PWMA3_SELECT_INPUT = 24U, /**< IOMUXC select input index */ + kIOMUXC_FLEXPWM1_PWMA0_SELECT_INPUT = 25U, /**< IOMUXC select input index */ + kIOMUXC_FLEXPWM1_PWMA1_SELECT_INPUT = 26U, /**< IOMUXC select input index */ + kIOMUXC_FLEXPWM1_PWMA2_SELECT_INPUT = 27U, /**< IOMUXC select input index */ + kIOMUXC_FLEXPWM1_PWMB3_SELECT_INPUT = 28U, /**< IOMUXC select input index */ + kIOMUXC_FLEXPWM1_PWMB0_SELECT_INPUT = 29U, /**< IOMUXC select input index */ + kIOMUXC_FLEXPWM1_PWMB1_SELECT_INPUT = 30U, /**< IOMUXC select input index */ + kIOMUXC_FLEXPWM1_PWMB2_SELECT_INPUT = 31U, /**< IOMUXC select input index */ + kIOMUXC_FLEXPWM2_PWMA3_SELECT_INPUT = 32U, /**< IOMUXC select input index */ + kIOMUXC_FLEXPWM2_PWMA0_SELECT_INPUT = 33U, /**< IOMUXC select input index */ + kIOMUXC_FLEXPWM2_PWMA1_SELECT_INPUT = 34U, /**< IOMUXC select input index */ + kIOMUXC_FLEXPWM2_PWMA2_SELECT_INPUT = 35U, /**< IOMUXC select input index */ + kIOMUXC_FLEXPWM2_PWMB3_SELECT_INPUT = 36U, /**< IOMUXC select input index */ + kIOMUXC_FLEXPWM2_PWMB0_SELECT_INPUT = 37U, /**< IOMUXC select input index */ + kIOMUXC_FLEXPWM2_PWMB1_SELECT_INPUT = 38U, /**< IOMUXC select input index */ + kIOMUXC_FLEXPWM2_PWMB2_SELECT_INPUT = 39U, /**< IOMUXC select input index */ + kIOMUXC_FLEXPWM4_PWMA0_SELECT_INPUT = 40U, /**< IOMUXC select input index */ + kIOMUXC_FLEXPWM4_PWMA1_SELECT_INPUT = 41U, /**< IOMUXC select input index */ + kIOMUXC_FLEXPWM4_PWMA2_SELECT_INPUT = 42U, /**< IOMUXC select input index */ + kIOMUXC_FLEXPWM4_PWMA3_SELECT_INPUT = 43U, /**< IOMUXC select input index */ + kIOMUXC_FLEXSPIA_DQS_SELECT_INPUT = 44U, /**< IOMUXC select input index */ + kIOMUXC_FLEXSPIA_DATA0_SELECT_INPUT = 45U, /**< IOMUXC select input index */ + kIOMUXC_FLEXSPIA_DATA1_SELECT_INPUT = 46U, /**< IOMUXC select input index */ + kIOMUXC_FLEXSPIA_DATA2_SELECT_INPUT = 47U, /**< IOMUXC select input index */ + kIOMUXC_FLEXSPIA_DATA3_SELECT_INPUT = 48U, /**< IOMUXC select input index */ + kIOMUXC_FLEXSPIB_DATA0_SELECT_INPUT = 49U, /**< IOMUXC select input index */ + kIOMUXC_FLEXSPIB_DATA1_SELECT_INPUT = 50U, /**< IOMUXC select input index */ + kIOMUXC_FLEXSPIB_DATA2_SELECT_INPUT = 51U, /**< IOMUXC select input index */ + kIOMUXC_FLEXSPIB_DATA3_SELECT_INPUT = 52U, /**< IOMUXC select input index */ + kIOMUXC_FLEXSPIA_SCK_SELECT_INPUT = 53U, /**< IOMUXC select input index */ + kIOMUXC_LPI2C1_SCL_SELECT_INPUT = 54U, /**< IOMUXC select input index */ + kIOMUXC_LPI2C1_SDA_SELECT_INPUT = 55U, /**< IOMUXC select input index */ + kIOMUXC_LPI2C2_SCL_SELECT_INPUT = 56U, /**< IOMUXC select input index */ + kIOMUXC_LPI2C2_SDA_SELECT_INPUT = 57U, /**< IOMUXC select input index */ + kIOMUXC_LPI2C3_SCL_SELECT_INPUT = 58U, /**< IOMUXC select input index */ + kIOMUXC_LPI2C3_SDA_SELECT_INPUT = 59U, /**< IOMUXC select input index */ + kIOMUXC_LPI2C4_SCL_SELECT_INPUT = 60U, /**< IOMUXC select input index */ + kIOMUXC_LPI2C4_SDA_SELECT_INPUT = 61U, /**< IOMUXC select input index */ + kIOMUXC_LPSPI1_PCS0_SELECT_INPUT = 62U, /**< IOMUXC select input index */ + kIOMUXC_LPSPI1_SCK_SELECT_INPUT = 63U, /**< IOMUXC select input index */ + kIOMUXC_LPSPI1_SDI_SELECT_INPUT = 64U, /**< IOMUXC select input index */ + kIOMUXC_LPSPI1_SDO_SELECT_INPUT = 65U, /**< IOMUXC select input index */ + kIOMUXC_LPSPI2_PCS0_SELECT_INPUT = 66U, /**< IOMUXC select input index */ + kIOMUXC_LPSPI2_SCK_SELECT_INPUT = 67U, /**< IOMUXC select input index */ + kIOMUXC_LPSPI2_SDI_SELECT_INPUT = 68U, /**< IOMUXC select input index */ + kIOMUXC_LPSPI2_SDO_SELECT_INPUT = 69U, /**< IOMUXC select input index */ + kIOMUXC_LPSPI3_PCS0_SELECT_INPUT = 70U, /**< IOMUXC select input index */ + kIOMUXC_LPSPI3_SCK_SELECT_INPUT = 71U, /**< IOMUXC select input index */ + kIOMUXC_LPSPI3_SDI_SELECT_INPUT = 72U, /**< IOMUXC select input index */ + kIOMUXC_LPSPI3_SDO_SELECT_INPUT = 73U, /**< IOMUXC select input index */ + kIOMUXC_LPSPI4_PCS0_SELECT_INPUT = 74U, /**< IOMUXC select input index */ + kIOMUXC_LPSPI4_SCK_SELECT_INPUT = 75U, /**< IOMUXC select input index */ + kIOMUXC_LPSPI4_SDI_SELECT_INPUT = 76U, /**< IOMUXC select input index */ + kIOMUXC_LPSPI4_SDO_SELECT_INPUT = 77U, /**< IOMUXC select input index */ + kIOMUXC_LPUART2_RX_SELECT_INPUT = 78U, /**< IOMUXC select input index */ + kIOMUXC_LPUART2_TX_SELECT_INPUT = 79U, /**< IOMUXC select input index */ + kIOMUXC_LPUART3_CTS_B_SELECT_INPUT = 80U, /**< IOMUXC select input index */ + kIOMUXC_LPUART3_RX_SELECT_INPUT = 81U, /**< IOMUXC select input index */ + kIOMUXC_LPUART3_TX_SELECT_INPUT = 82U, /**< IOMUXC select input index */ + kIOMUXC_LPUART4_RX_SELECT_INPUT = 83U, /**< IOMUXC select input index */ + kIOMUXC_LPUART4_TX_SELECT_INPUT = 84U, /**< IOMUXC select input index */ + kIOMUXC_LPUART5_RX_SELECT_INPUT = 85U, /**< IOMUXC select input index */ + kIOMUXC_LPUART5_TX_SELECT_INPUT = 86U, /**< IOMUXC select input index */ + kIOMUXC_LPUART6_RX_SELECT_INPUT = 87U, /**< IOMUXC select input index */ + kIOMUXC_LPUART6_TX_SELECT_INPUT = 88U, /**< IOMUXC select input index */ + kIOMUXC_LPUART7_RX_SELECT_INPUT = 89U, /**< IOMUXC select input index */ + kIOMUXC_LPUART7_TX_SELECT_INPUT = 90U, /**< IOMUXC select input index */ + kIOMUXC_LPUART8_RX_SELECT_INPUT = 91U, /**< IOMUXC select input index */ + kIOMUXC_LPUART8_TX_SELECT_INPUT = 92U, /**< IOMUXC select input index */ + kIOMUXC_NMI_SELECT_INPUT = 93U, /**< IOMUXC select input index */ + kIOMUXC_QTIMER2_TIMER0_SELECT_INPUT = 94U, /**< IOMUXC select input index */ + kIOMUXC_QTIMER2_TIMER1_SELECT_INPUT = 95U, /**< IOMUXC select input index */ + kIOMUXC_QTIMER2_TIMER2_SELECT_INPUT = 96U, /**< IOMUXC select input index */ + kIOMUXC_QTIMER2_TIMER3_SELECT_INPUT = 97U, /**< IOMUXC select input index */ + kIOMUXC_QTIMER3_TIMER0_SELECT_INPUT = 98U, /**< IOMUXC select input index */ + kIOMUXC_QTIMER3_TIMER1_SELECT_INPUT = 99U, /**< IOMUXC select input index */ + kIOMUXC_QTIMER3_TIMER2_SELECT_INPUT = 100U, /**< IOMUXC select input index */ + kIOMUXC_QTIMER3_TIMER3_SELECT_INPUT = 101U, /**< IOMUXC select input index */ + kIOMUXC_SAI1_MCLK2_SELECT_INPUT = 102U, /**< IOMUXC select input index */ + kIOMUXC_SAI1_RX_BCLK_SELECT_INPUT = 103U, /**< IOMUXC select input index */ + kIOMUXC_SAI1_RX_DATA0_SELECT_INPUT = 104U, /**< IOMUXC select input index */ + kIOMUXC_SAI1_RX_DATA1_SELECT_INPUT = 105U, /**< IOMUXC select input index */ + kIOMUXC_SAI1_RX_DATA2_SELECT_INPUT = 106U, /**< IOMUXC select input index */ + kIOMUXC_SAI1_RX_DATA3_SELECT_INPUT = 107U, /**< IOMUXC select input index */ + kIOMUXC_SAI1_RX_SYNC_SELECT_INPUT = 108U, /**< IOMUXC select input index */ + kIOMUXC_SAI1_TX_BCLK_SELECT_INPUT = 109U, /**< IOMUXC select input index */ + kIOMUXC_SAI1_TX_SYNC_SELECT_INPUT = 110U, /**< IOMUXC select input index */ + kIOMUXC_SAI2_MCLK2_SELECT_INPUT = 111U, /**< IOMUXC select input index */ + kIOMUXC_SAI2_RX_BCLK_SELECT_INPUT = 112U, /**< IOMUXC select input index */ + kIOMUXC_SAI2_RX_DATA0_SELECT_INPUT = 113U, /**< IOMUXC select input index */ + kIOMUXC_SAI2_RX_SYNC_SELECT_INPUT = 114U, /**< IOMUXC select input index */ + kIOMUXC_SAI2_TX_BCLK_SELECT_INPUT = 115U, /**< IOMUXC select input index */ + kIOMUXC_SAI2_TX_SYNC_SELECT_INPUT = 116U, /**< IOMUXC select input index */ + kIOMUXC_SPDIF_IN_SELECT_INPUT = 117U, /**< IOMUXC select input index */ + kIOMUXC_USB_OTG2_OC_SELECT_INPUT = 118U, /**< IOMUXC select input index */ + kIOMUXC_USB_OTG1_OC_SELECT_INPUT = 119U, /**< IOMUXC select input index */ + kIOMUXC_USDHC1_CD_B_SELECT_INPUT = 120U, /**< IOMUXC select input index */ + kIOMUXC_USDHC1_WP_SELECT_INPUT = 121U, /**< IOMUXC select input index */ + kIOMUXC_USDHC2_CLK_SELECT_INPUT = 122U, /**< IOMUXC select input index */ + kIOMUXC_USDHC2_CD_B_SELECT_INPUT = 123U, /**< IOMUXC select input index */ + kIOMUXC_USDHC2_CMD_SELECT_INPUT = 124U, /**< IOMUXC select input index */ + kIOMUXC_USDHC2_DATA0_SELECT_INPUT = 125U, /**< IOMUXC select input index */ + kIOMUXC_USDHC2_DATA1_SELECT_INPUT = 126U, /**< IOMUXC select input index */ + kIOMUXC_USDHC2_DATA2_SELECT_INPUT = 127U, /**< IOMUXC select input index */ + kIOMUXC_USDHC2_DATA3_SELECT_INPUT = 128U, /**< IOMUXC select input index */ + kIOMUXC_USDHC2_DATA4_SELECT_INPUT = 129U, /**< IOMUXC select input index */ + kIOMUXC_USDHC2_DATA5_SELECT_INPUT = 130U, /**< IOMUXC select input index */ + kIOMUXC_USDHC2_DATA6_SELECT_INPUT = 131U, /**< IOMUXC select input index */ + kIOMUXC_USDHC2_DATA7_SELECT_INPUT = 132U, /**< IOMUXC select input index */ + kIOMUXC_USDHC2_WP_SELECT_INPUT = 133U, /**< IOMUXC select input index */ + kIOMUXC_XBAR1_IN02_SELECT_INPUT = 134U, /**< IOMUXC select input index */ + kIOMUXC_XBAR1_IN03_SELECT_INPUT = 135U, /**< IOMUXC select input index */ + kIOMUXC_XBAR1_IN04_SELECT_INPUT = 136U, /**< IOMUXC select input index */ + kIOMUXC_XBAR1_IN05_SELECT_INPUT = 137U, /**< IOMUXC select input index */ + kIOMUXC_XBAR1_IN06_SELECT_INPUT = 138U, /**< IOMUXC select input index */ + kIOMUXC_XBAR1_IN07_SELECT_INPUT = 139U, /**< IOMUXC select input index */ + kIOMUXC_XBAR1_IN08_SELECT_INPUT = 140U, /**< IOMUXC select input index */ + kIOMUXC_XBAR1_IN09_SELECT_INPUT = 141U, /**< IOMUXC select input index */ + kIOMUXC_XBAR1_IN17_SELECT_INPUT = 142U, /**< IOMUXC select input index */ + kIOMUXC_XBAR1_IN18_SELECT_INPUT = 143U, /**< IOMUXC select input index */ + kIOMUXC_XBAR1_IN20_SELECT_INPUT = 144U, /**< IOMUXC select input index */ + kIOMUXC_XBAR1_IN22_SELECT_INPUT = 145U, /**< IOMUXC select input index */ + kIOMUXC_XBAR1_IN23_SELECT_INPUT = 146U, /**< IOMUXC select input index */ + kIOMUXC_XBAR1_IN24_SELECT_INPUT = 147U, /**< IOMUXC select input index */ + kIOMUXC_XBAR1_IN14_SELECT_INPUT = 148U, /**< IOMUXC select input index */ + kIOMUXC_XBAR1_IN15_SELECT_INPUT = 149U, /**< IOMUXC select input index */ + kIOMUXC_XBAR1_IN16_SELECT_INPUT = 150U, /**< IOMUXC select input index */ + kIOMUXC_XBAR1_IN25_SELECT_INPUT = 151U, /**< IOMUXC select input index */ + kIOMUXC_XBAR1_IN19_SELECT_INPUT = 152U, /**< IOMUXC select input index */ + kIOMUXC_XBAR1_IN21_SELECT_INPUT = 153U, /**< IOMUXC select input index */ +} iomuxc_select_input_t; + +typedef enum _xbar_input_signal +{ + kXBARA1_InputLogicLow = 0|0x100U, /**< LOGIC_LOW output assigned to XBARA1_IN0 input. */ + kXBARA1_InputLogicHigh = 1|0x100U, /**< LOGIC_HIGH output assigned to XBARA1_IN1 input. */ + kXBARA1_InputIomuxXbarIn02 = 2|0x100U, /**< IOMUX_XBAR_IN02 output assigned to XBARA1_IN2 input. */ + kXBARA1_InputIomuxXbarIn03 = 3|0x100U, /**< IOMUX_XBAR_IN03 output assigned to XBARA1_IN3 input. */ + kXBARA1_InputIomuxXbarInout04 = 4|0x100U, /**< IOMUX_XBAR_INOUT04 output assigned to XBARA1_IN4 input. */ + kXBARA1_InputIomuxXbarInout05 = 5|0x100U, /**< IOMUX_XBAR_INOUT05 output assigned to XBARA1_IN5 input. */ + kXBARA1_InputIomuxXbarInout06 = 6|0x100U, /**< IOMUX_XBAR_INOUT06 output assigned to XBARA1_IN6 input. */ + kXBARA1_InputIomuxXbarInout07 = 7|0x100U, /**< IOMUX_XBAR_INOUT07 output assigned to XBARA1_IN7 input. */ + kXBARA1_InputIomuxXbarInout08 = 8|0x100U, /**< IOMUX_XBAR_INOUT08 output assigned to XBARA1_IN8 input. */ + kXBARA1_InputIomuxXbarInout09 = 9|0x100U, /**< IOMUX_XBAR_INOUT09 output assigned to XBARA1_IN9 input. */ + kXBARA1_InputIomuxXbarInout10 = 10|0x100U, /**< IOMUX_XBAR_INOUT10 output assigned to XBARA1_IN10 input. */ + kXBARA1_InputIomuxXbarInout11 = 11|0x100U, /**< IOMUX_XBAR_INOUT11 output assigned to XBARA1_IN11 input. */ + kXBARA1_InputIomuxXbarInout12 = 12|0x100U, /**< IOMUX_XBAR_INOUT12 output assigned to XBARA1_IN12 input. */ + kXBARA1_InputIomuxXbarInout13 = 13|0x100U, /**< IOMUX_XBAR_INOUT13 output assigned to XBARA1_IN13 input. */ + kXBARA1_InputIomuxXbarInout14 = 14|0x100U, /**< IOMUX_XBAR_INOUT14 output assigned to XBARA1_IN14 input. */ + kXBARA1_InputIomuxXbarInout15 = 15|0x100U, /**< IOMUX_XBAR_INOUT15 output assigned to XBARA1_IN15 input. */ + kXBARA1_InputIomuxXbarInout16 = 16|0x100U, /**< IOMUX_XBAR_INOUT16 output assigned to XBARA1_IN16 input. */ + kXBARA1_InputIomuxXbarInout17 = 17|0x100U, /**< IOMUX_XBAR_INOUT17 output assigned to XBARA1_IN17 input. */ + kXBARA1_InputIomuxXbarInout18 = 18|0x100U, /**< IOMUX_XBAR_INOUT18 output assigned to XBARA1_IN18 input. */ + kXBARA1_InputIomuxXbarInout19 = 19|0x100U, /**< IOMUX_XBAR_INOUT19 output assigned to XBARA1_IN19 input. */ + kXBARA1_InputIomuxXbarIn20 = 20|0x100U, /**< IOMUX_XBAR_IN20 output assigned to XBARA1_IN20 input. */ + kXBARA1_InputIomuxXbarIn21 = 21|0x100U, /**< IOMUX_XBAR_IN21 output assigned to XBARA1_IN21 input. */ + kXBARA1_InputIomuxXbarIn22 = 22|0x100U, /**< IOMUX_XBAR_IN22 output assigned to XBARA1_IN22 input. */ + kXBARA1_InputIomuxXbarIn23 = 23|0x100U, /**< IOMUX_XBAR_IN23 output assigned to XBARA1_IN23 input. */ + kXBARA1_InputIomuxXbarIn24 = 24|0x100U, /**< IOMUX_XBAR_IN24 output assigned to XBARA1_IN24 input. */ + kXBARA1_InputIomuxXbarIn25 = 25|0x100U, /**< IOMUX_XBAR_IN25 output assigned to XBARA1_IN25 input. */ + kXBARA1_InputAcmp1Out = 26|0x100U, /**< ACMP1_OUT output assigned to XBARA1_IN26 input. */ + kXBARA1_InputAcmp2Out = 27|0x100U, /**< ACMP2_OUT output assigned to XBARA1_IN27 input. */ + kXBARA1_InputAcmp3Out = 28|0x100U, /**< ACMP3_OUT output assigned to XBARA1_IN28 input. */ + kXBARA1_InputAcmp4Out = 29|0x100U, /**< ACMP4_OUT output assigned to XBARA1_IN29 input. */ + kXBARA1_InputRESERVED30 = 30|0x100U, /**< XBARA1_IN30 input is reserved. */ + kXBARA1_InputRESERVED31 = 31|0x100U, /**< XBARA1_IN31 input is reserved. */ + kXBARA1_InputQtimer3Tmr0Output = 32|0x100U, /**< QTIMER3_TMR0_OUTPUT output assigned to XBARA1_IN32 input. */ + kXBARA1_InputQtimer3Tmr1Output = 33|0x100U, /**< QTIMER3_TMR1_OUTPUT output assigned to XBARA1_IN33 input. */ + kXBARA1_InputQtimer3Tmr2Output = 34|0x100U, /**< QTIMER3_TMR2_OUTPUT output assigned to XBARA1_IN34 input. */ + kXBARA1_InputQtimer3Tmr3Output = 35|0x100U, /**< QTIMER3_TMR3_OUTPUT output assigned to XBARA1_IN35 input. */ + kXBARA1_InputQtimer4Tmr0Output = 36|0x100U, /**< QTIMER4_TMR0_OUTPUT output assigned to XBARA1_IN36 input. */ + kXBARA1_InputQtimer4Tmr1Output = 37|0x100U, /**< QTIMER4_TMR1_OUTPUT output assigned to XBARA1_IN37 input. */ + kXBARA1_InputQtimer4Tmr2Output = 38|0x100U, /**< QTIMER4_TMR2_OUTPUT output assigned to XBARA1_IN38 input. */ + kXBARA1_InputQtimer4Tmr3Output = 39|0x100U, /**< QTIMER4_TMR3_OUTPUT output assigned to XBARA1_IN39 input. */ + kXBARA1_InputFlexpwm1Pwm1OutTrig01 = 40|0x100U, /**< FLEXPWM1_PWM1_OUT_TRIG0_1 output assigned to XBARA1_IN40 input. */ + kXBARA1_InputFlexpwm1Pwm2OutTrig01 = 41|0x100U, /**< FLEXPWM1_PWM2_OUT_TRIG0_1 output assigned to XBARA1_IN41 input. */ + kXBARA1_InputFlexpwm1Pwm3OutTrig01 = 42|0x100U, /**< FLEXPWM1_PWM3_OUT_TRIG0_1 output assigned to XBARA1_IN42 input. */ + kXBARA1_InputFlexpwm1Pwm4OutTrig01 = 43|0x100U, /**< FLEXPWM1_PWM4_OUT_TRIG0_1 output assigned to XBARA1_IN43 input. */ + kXBARA1_InputFlexpwm2Pwm1OutTrig01 = 44|0x100U, /**< FLEXPWM2_PWM1_OUT_TRIG0_1 output assigned to XBARA1_IN44 input. */ + kXBARA1_InputFlexpwm2Pwm2OutTrig01 = 45|0x100U, /**< FLEXPWM2_PWM2_OUT_TRIG0_1 output assigned to XBARA1_IN45 input. */ + kXBARA1_InputFlexpwm2Pwm3OutTrig01 = 46|0x100U, /**< FLEXPWM2_PWM3_OUT_TRIG0_1 output assigned to XBARA1_IN46 input. */ + kXBARA1_InputFlexpwm2Pwm4OutTrig01 = 47|0x100U, /**< FLEXPWM2_PWM4_OUT_TRIG0_1 output assigned to XBARA1_IN47 input. */ + kXBARA1_InputFlexpwm3Pwm1OutTrig01 = 48|0x100U, /**< FLEXPWM3_PWM1_OUT_TRIG0_1 output assigned to XBARA1_IN48 input. */ + kXBARA1_InputFlexpwm3Pwm2OutTrig01 = 49|0x100U, /**< FLEXPWM3_PWM2_OUT_TRIG0_1 output assigned to XBARA1_IN49 input. */ + kXBARA1_InputFlexpwm3Pwm3OutTrig01 = 50|0x100U, /**< FLEXPWM3_PWM3_OUT_TRIG0_1 output assigned to XBARA1_IN50 input. */ + kXBARA1_InputFlexpwm3Pwm4OutTrig01 = 51|0x100U, /**< FLEXPWM3_PWM4_OUT_TRIG0_1 output assigned to XBARA1_IN51 input. */ + kXBARA1_InputFlexpwm4Pwm1OutTrig01 = 52|0x100U, /**< FLEXPWM4_PWM1_OUT_TRIG0_1 output assigned to XBARA1_IN52 input. */ + kXBARA1_InputFlexpwm4Pwm2OutTrig01 = 53|0x100U, /**< FLEXPWM4_PWM2_OUT_TRIG0_1 output assigned to XBARA1_IN53 input. */ + kXBARA1_InputFlexpwm4Pwm3OutTrig01 = 54|0x100U, /**< FLEXPWM4_PWM3_OUT_TRIG0_1 output assigned to XBARA1_IN54 input. */ + kXBARA1_InputFlexpwm4Pwm4OutTrig01 = 55|0x100U, /**< FLEXPWM4_PWM4_OUT_TRIG0_1 output assigned to XBARA1_IN55 input. */ + kXBARA1_InputPitTrigger0 = 56|0x100U, /**< PIT_TRIGGER0 output assigned to XBARA1_IN56 input. */ + kXBARA1_InputPitTrigger1 = 57|0x100U, /**< PIT_TRIGGER1 output assigned to XBARA1_IN57 input. */ + kXBARA1_InputPitTrigger2 = 58|0x100U, /**< PIT_TRIGGER2 output assigned to XBARA1_IN58 input. */ + kXBARA1_InputPitTrigger3 = 59|0x100U, /**< PIT_TRIGGER3 output assigned to XBARA1_IN59 input. */ + kXBARA1_InputEnc1PosMatch = 60|0x100U, /**< ENC1_POS_MATCH output assigned to XBARA1_IN60 input. */ + kXBARA1_InputEnc2PosMatch = 61|0x100U, /**< ENC2_POS_MATCH output assigned to XBARA1_IN61 input. */ + kXBARA1_InputEnc3PosMatch = 62|0x100U, /**< ENC3_POS_MATCH output assigned to XBARA1_IN62 input. */ + kXBARA1_InputEnc4PosMatch = 63|0x100U, /**< ENC4_POS_MATCH output assigned to XBARA1_IN63 input. */ + kXBARA1_InputDmaDone0 = 64|0x100U, /**< DMA_DONE0 output assigned to XBARA1_IN64 input. */ + kXBARA1_InputDmaDone1 = 65|0x100U, /**< DMA_DONE1 output assigned to XBARA1_IN65 input. */ + kXBARA1_InputDmaDone2 = 66|0x100U, /**< DMA_DONE2 output assigned to XBARA1_IN66 input. */ + kXBARA1_InputDmaDone3 = 67|0x100U, /**< DMA_DONE3 output assigned to XBARA1_IN67 input. */ + kXBARA1_InputDmaDone4 = 68|0x100U, /**< DMA_DONE4 output assigned to XBARA1_IN68 input. */ + kXBARA1_InputDmaDone5 = 69|0x100U, /**< DMA_DONE5 output assigned to XBARA1_IN69 input. */ + kXBARA1_InputDmaDone6 = 70|0x100U, /**< DMA_DONE6 output assigned to XBARA1_IN70 input. */ + kXBARA1_InputDmaDone7 = 71|0x100U, /**< DMA_DONE7 output assigned to XBARA1_IN71 input. */ + kXBARA1_InputAoi1Out0 = 72|0x100U, /**< AOI1_OUT0 output assigned to XBARA1_IN72 input. */ + kXBARA1_InputAoi1Out1 = 73|0x100U, /**< AOI1_OUT1 output assigned to XBARA1_IN73 input. */ + kXBARA1_InputAoi1Out2 = 74|0x100U, /**< AOI1_OUT2 output assigned to XBARA1_IN74 input. */ + kXBARA1_InputAoi1Out3 = 75|0x100U, /**< AOI1_OUT3 output assigned to XBARA1_IN75 input. */ + kXBARA1_InputAoi2Out0 = 76|0x100U, /**< AOI2_OUT0 output assigned to XBARA1_IN76 input. */ + kXBARA1_InputAoi2Out1 = 77|0x100U, /**< AOI2_OUT1 output assigned to XBARA1_IN77 input. */ + kXBARA1_InputAoi2Out2 = 78|0x100U, /**< AOI2_OUT2 output assigned to XBARA1_IN78 input. */ + kXBARA1_InputAoi2Out3 = 79|0x100U, /**< AOI2_OUT3 output assigned to XBARA1_IN79 input. */ + kXBARA1_InputAdcEtcXbar0Coco0 = 80|0x100U, /**< ADC_ETC_XBAR0_COCO0 output assigned to XBARA1_IN80 input. */ + kXBARA1_InputAdcEtcXbar0Coco1 = 81|0x100U, /**< ADC_ETC_XBAR0_COCO1 output assigned to XBARA1_IN81 input. */ + kXBARA1_InputAdcEtcXbar0Coco2 = 82|0x100U, /**< ADC_ETC_XBAR0_COCO2 output assigned to XBARA1_IN82 input. */ + kXBARA1_InputAdcEtcXbar0Coco3 = 83|0x100U, /**< ADC_ETC_XBAR0_COCO3 output assigned to XBARA1_IN83 input. */ + kXBARA1_InputAdcEtcXbar1Coco0 = 84|0x100U, /**< ADC_ETC_XBAR1_COCO0 output assigned to XBARA1_IN84 input. */ + kXBARA1_InputAdcEtcXbar1Coco1 = 85|0x100U, /**< ADC_ETC_XBAR1_COCO1 output assigned to XBARA1_IN85 input. */ + kXBARA1_InputAdcEtcXbar1Coco2 = 86|0x100U, /**< ADC_ETC_XBAR1_COCO2 output assigned to XBARA1_IN86 input. */ + kXBARA1_InputAdcEtcXbar1Coco3 = 87|0x100U, /**< ADC_ETC_XBAR1_COCO3 output assigned to XBARA1_IN87 input. */ + kXBARB2_InputLogicLow = 0|0x200U, /**< LOGIC_LOW output assigned to XBARB2_IN0 input. */ + kXBARB2_InputLogicHigh = 1|0x200U, /**< LOGIC_HIGH output assigned to XBARB2_IN1 input. */ + kXBARB2_InputRESERVED2 = 2|0x200U, /**< XBARB2_IN2 input is reserved. */ + kXBARB2_InputRESERVED3 = 3|0x200U, /**< XBARB2_IN3 input is reserved. */ + kXBARB2_InputRESERVED4 = 4|0x200U, /**< XBARB2_IN4 input is reserved. */ + kXBARB2_InputRESERVED5 = 5|0x200U, /**< XBARB2_IN5 input is reserved. */ + kXBARB2_InputAcmp1Out = 6|0x200U, /**< ACMP1_OUT output assigned to XBARB2_IN6 input. */ + kXBARB2_InputAcmp2Out = 7|0x200U, /**< ACMP2_OUT output assigned to XBARB2_IN7 input. */ + kXBARB2_InputAcmp3Out = 8|0x200U, /**< ACMP3_OUT output assigned to XBARB2_IN8 input. */ + kXBARB2_InputAcmp4Out = 9|0x200U, /**< ACMP4_OUT output assigned to XBARB2_IN9 input. */ + kXBARB2_InputRESERVED10 = 10|0x200U, /**< XBARB2_IN10 input is reserved. */ + kXBARB2_InputRESERVED11 = 11|0x200U, /**< XBARB2_IN11 input is reserved. */ + kXBARB2_InputQtimer3Tmr0Output = 12|0x200U, /**< QTIMER3_TMR0_OUTPUT output assigned to XBARB2_IN12 input. */ + kXBARB2_InputQtimer3Tmr1Output = 13|0x200U, /**< QTIMER3_TMR1_OUTPUT output assigned to XBARB2_IN13 input. */ + kXBARB2_InputQtimer3Tmr2Output = 14|0x200U, /**< QTIMER3_TMR2_OUTPUT output assigned to XBARB2_IN14 input. */ + kXBARB2_InputQtimer3Tmr3Output = 15|0x200U, /**< QTIMER3_TMR3_OUTPUT output assigned to XBARB2_IN15 input. */ + kXBARB2_InputQtimer4Tmr0Output = 16|0x200U, /**< QTIMER4_TMR0_OUTPUT output assigned to XBARB2_IN16 input. */ + kXBARB2_InputQtimer4Tmr1Output = 17|0x200U, /**< QTIMER4_TMR1_OUTPUT output assigned to XBARB2_IN17 input. */ + kXBARB2_InputQtimer4Tmr2Output = 18|0x200U, /**< QTIMER4_TMR2_OUTPUT output assigned to XBARB2_IN18 input. */ + kXBARB2_InputQtimer4Tmr3Output = 19|0x200U, /**< QTIMER4_TMR3_OUTPUT output assigned to XBARB2_IN19 input. */ + kXBARB2_InputFlexpwm1Pwm1OutTrig01 = 20|0x200U, /**< FLEXPWM1_PWM1_OUT_TRIG0_1 output assigned to XBARB2_IN20 input. */ + kXBARB2_InputFlexpwm1Pwm2OutTrig01 = 21|0x200U, /**< FLEXPWM1_PWM2_OUT_TRIG0_1 output assigned to XBARB2_IN21 input. */ + kXBARB2_InputFlexpwm1Pwm3OutTrig01 = 22|0x200U, /**< FLEXPWM1_PWM3_OUT_TRIG0_1 output assigned to XBARB2_IN22 input. */ + kXBARB2_InputFlexpwm1Pwm4OutTrig01 = 23|0x200U, /**< FLEXPWM1_PWM4_OUT_TRIG0_1 output assigned to XBARB2_IN23 input. */ + kXBARB2_InputFlexpwm2Pwm1OutTrig01 = 24|0x200U, /**< FLEXPWM2_PWM1_OUT_TRIG0_1 output assigned to XBARB2_IN24 input. */ + kXBARB2_InputFlexpwm2Pwm2OutTrig01 = 25|0x200U, /**< FLEXPWM2_PWM2_OUT_TRIG0_1 output assigned to XBARB2_IN25 input. */ + kXBARB2_InputFlexpwm2Pwm3OutTrig01 = 26|0x200U, /**< FLEXPWM2_PWM3_OUT_TRIG0_1 output assigned to XBARB2_IN26 input. */ + kXBARB2_InputFlexpwm2Pwm4OutTrig01 = 27|0x200U, /**< FLEXPWM2_PWM4_OUT_TRIG0_1 output assigned to XBARB2_IN27 input. */ + kXBARB2_InputFlexpwm3Pwm1OutTrig01 = 28|0x200U, /**< FLEXPWM3_PWM1_OUT_TRIG0_1 output assigned to XBARB2_IN28 input. */ + kXBARB2_InputFlexpwm3Pwm2OutTrig01 = 29|0x200U, /**< FLEXPWM3_PWM2_OUT_TRIG0_1 output assigned to XBARB2_IN29 input. */ + kXBARB2_InputFlexpwm3Pwm3OutTrig01 = 30|0x200U, /**< FLEXPWM3_PWM3_OUT_TRIG0_1 output assigned to XBARB2_IN30 input. */ + kXBARB2_InputFlexpwm3Pwm4OutTrig01 = 31|0x200U, /**< FLEXPWM3_PWM4_OUT_TRIG0_1 output assigned to XBARB2_IN31 input. */ + kXBARB2_InputFlexpwm4Pwm1OutTrig01 = 32|0x200U, /**< FLEXPWM4_PWM1_OUT_TRIG0_1 output assigned to XBARB2_IN32 input. */ + kXBARB2_InputFlexpwm4Pwm2OutTrig01 = 33|0x200U, /**< FLEXPWM4_PWM2_OUT_TRIG0_1 output assigned to XBARB2_IN33 input. */ + kXBARB2_InputFlexpwm4Pwm3OutTrig01 = 34|0x200U, /**< FLEXPWM4_PWM3_OUT_TRIG0_1 output assigned to XBARB2_IN34 input. */ + kXBARB2_InputFlexpwm4Pwm4OutTrig01 = 35|0x200U, /**< FLEXPWM4_PWM4_OUT_TRIG0_1 output assigned to XBARB2_IN35 input. */ + kXBARB2_InputPitTrigger0 = 36|0x200U, /**< PIT_TRIGGER0 output assigned to XBARB2_IN36 input. */ + kXBARB2_InputPitTrigger1 = 37|0x200U, /**< PIT_TRIGGER1 output assigned to XBARB2_IN37 input. */ + kXBARB2_InputAdcEtcXbar0Coco0 = 38|0x200U, /**< ADC_ETC_XBAR0_COCO0 output assigned to XBARB2_IN38 input. */ + kXBARB2_InputAdcEtcXbar0Coco1 = 39|0x200U, /**< ADC_ETC_XBAR0_COCO1 output assigned to XBARB2_IN39 input. */ + kXBARB2_InputAdcEtcXbar0Coco2 = 40|0x200U, /**< ADC_ETC_XBAR0_COCO2 output assigned to XBARB2_IN40 input. */ + kXBARB2_InputAdcEtcXbar0Coco3 = 41|0x200U, /**< ADC_ETC_XBAR0_COCO3 output assigned to XBARB2_IN41 input. */ + kXBARB2_InputAdcEtcXbar1Coco0 = 42|0x200U, /**< ADC_ETC_XBAR1_COCO0 output assigned to XBARB2_IN42 input. */ + kXBARB2_InputAdcEtcXbar1Coco1 = 43|0x200U, /**< ADC_ETC_XBAR1_COCO1 output assigned to XBARB2_IN43 input. */ + kXBARB2_InputAdcEtcXbar1Coco2 = 44|0x200U, /**< ADC_ETC_XBAR1_COCO2 output assigned to XBARB2_IN44 input. */ + kXBARB2_InputAdcEtcXbar1Coco3 = 45|0x200U, /**< ADC_ETC_XBAR1_COCO3 output assigned to XBARB2_IN45 input. */ + kXBARB2_InputEnc1PosMatch = 46|0x200U, /**< ENC1_POS_MATCH output assigned to XBARB2_IN46 input. */ + kXBARB2_InputEnc2PosMatch = 47|0x200U, /**< ENC2_POS_MATCH output assigned to XBARB2_IN47 input. */ + kXBARB2_InputEnc3PosMatch = 48|0x200U, /**< ENC3_POS_MATCH output assigned to XBARB2_IN48 input. */ + kXBARB2_InputEnc4PosMatch = 49|0x200U, /**< ENC4_POS_MATCH output assigned to XBARB2_IN49 input. */ + kXBARB2_InputDmaDone0 = 50|0x200U, /**< DMA_DONE0 output assigned to XBARB2_IN50 input. */ + kXBARB2_InputDmaDone1 = 51|0x200U, /**< DMA_DONE1 output assigned to XBARB2_IN51 input. */ + kXBARB2_InputDmaDone2 = 52|0x200U, /**< DMA_DONE2 output assigned to XBARB2_IN52 input. */ + kXBARB2_InputDmaDone3 = 53|0x200U, /**< DMA_DONE3 output assigned to XBARB2_IN53 input. */ + kXBARB2_InputDmaDone4 = 54|0x200U, /**< DMA_DONE4 output assigned to XBARB2_IN54 input. */ + kXBARB2_InputDmaDone5 = 55|0x200U, /**< DMA_DONE5 output assigned to XBARB2_IN55 input. */ + kXBARB2_InputDmaDone6 = 56|0x200U, /**< DMA_DONE6 output assigned to XBARB2_IN56 input. */ + kXBARB2_InputDmaDone7 = 57|0x200U, /**< DMA_DONE7 output assigned to XBARB2_IN57 input. */ + kXBARB3_InputLogicLow = 0|0x300U, /**< LOGIC_LOW output assigned to XBARB3_IN0 input. */ + kXBARB3_InputLogicHigh = 1|0x300U, /**< LOGIC_HIGH output assigned to XBARB3_IN1 input. */ + kXBARB3_InputRESERVED2 = 2|0x300U, /**< XBARB3_IN2 input is reserved. */ + kXBARB3_InputRESERVED3 = 3|0x300U, /**< XBARB3_IN3 input is reserved. */ + kXBARB3_InputRESERVED4 = 4|0x300U, /**< XBARB3_IN4 input is reserved. */ + kXBARB3_InputRESERVED5 = 5|0x300U, /**< XBARB3_IN5 input is reserved. */ + kXBARB3_InputAcmp1Out = 6|0x300U, /**< ACMP1_OUT output assigned to XBARB3_IN6 input. */ + kXBARB3_InputAcmp2Out = 7|0x300U, /**< ACMP2_OUT output assigned to XBARB3_IN7 input. */ + kXBARB3_InputAcmp3Out = 8|0x300U, /**< ACMP3_OUT output assigned to XBARB3_IN8 input. */ + kXBARB3_InputAcmp4Out = 9|0x300U, /**< ACMP4_OUT output assigned to XBARB3_IN9 input. */ + kXBARB3_InputRESERVED10 = 10|0x300U, /**< XBARB3_IN10 input is reserved. */ + kXBARB3_InputRESERVED11 = 11|0x300U, /**< XBARB3_IN11 input is reserved. */ + kXBARB3_InputQtimer3Tmr0Output = 12|0x300U, /**< QTIMER3_TMR0_OUTPUT output assigned to XBARB3_IN12 input. */ + kXBARB3_InputQtimer3Tmr1Output = 13|0x300U, /**< QTIMER3_TMR1_OUTPUT output assigned to XBARB3_IN13 input. */ + kXBARB3_InputQtimer3Tmr2Output = 14|0x300U, /**< QTIMER3_TMR2_OUTPUT output assigned to XBARB3_IN14 input. */ + kXBARB3_InputQtimer3Tmr3Output = 15|0x300U, /**< QTIMER3_TMR3_OUTPUT output assigned to XBARB3_IN15 input. */ + kXBARB3_InputQtimer4Tmr0Output = 16|0x300U, /**< QTIMER4_TMR0_OUTPUT output assigned to XBARB3_IN16 input. */ + kXBARB3_InputQtimer4Tmr1Output = 17|0x300U, /**< QTIMER4_TMR1_OUTPUT output assigned to XBARB3_IN17 input. */ + kXBARB3_InputQtimer4Tmr2Output = 18|0x300U, /**< QTIMER4_TMR2_OUTPUT output assigned to XBARB3_IN18 input. */ + kXBARB3_InputQtimer4Tmr3Output = 19|0x300U, /**< QTIMER4_TMR3_OUTPUT output assigned to XBARB3_IN19 input. */ + kXBARB3_InputFlexpwm1Pwm1OutTrig01 = 20|0x300U, /**< FLEXPWM1_PWM1_OUT_TRIG0_1 output assigned to XBARB3_IN20 input. */ + kXBARB3_InputFlexpwm1Pwm2OutTrig01 = 21|0x300U, /**< FLEXPWM1_PWM2_OUT_TRIG0_1 output assigned to XBARB3_IN21 input. */ + kXBARB3_InputFlexpwm1Pwm3OutTrig01 = 22|0x300U, /**< FLEXPWM1_PWM3_OUT_TRIG0_1 output assigned to XBARB3_IN22 input. */ + kXBARB3_InputFlexpwm1Pwm4OutTrig01 = 23|0x300U, /**< FLEXPWM1_PWM4_OUT_TRIG0_1 output assigned to XBARB3_IN23 input. */ + kXBARB3_InputFlexpwm2Pwm1OutTrig01 = 24|0x300U, /**< FLEXPWM2_PWM1_OUT_TRIG0_1 output assigned to XBARB3_IN24 input. */ + kXBARB3_InputFlexpwm2Pwm2OutTrig01 = 25|0x300U, /**< FLEXPWM2_PWM2_OUT_TRIG0_1 output assigned to XBARB3_IN25 input. */ + kXBARB3_InputFlexpwm2Pwm3OutTrig01 = 26|0x300U, /**< FLEXPWM2_PWM3_OUT_TRIG0_1 output assigned to XBARB3_IN26 input. */ + kXBARB3_InputFlexpwm2Pwm4OutTrig01 = 27|0x300U, /**< FLEXPWM2_PWM4_OUT_TRIG0_1 output assigned to XBARB3_IN27 input. */ + kXBARB3_InputFlexpwm3Pwm1OutTrig01 = 28|0x300U, /**< FLEXPWM3_PWM1_OUT_TRIG0_1 output assigned to XBARB3_IN28 input. */ + kXBARB3_InputFlexpwm3Pwm2OutTrig01 = 29|0x300U, /**< FLEXPWM3_PWM2_OUT_TRIG0_1 output assigned to XBARB3_IN29 input. */ + kXBARB3_InputFlexpwm3Pwm3OutTrig01 = 30|0x300U, /**< FLEXPWM3_PWM3_OUT_TRIG0_1 output assigned to XBARB3_IN30 input. */ + kXBARB3_InputFlexpwm3Pwm4OutTrig01 = 31|0x300U, /**< FLEXPWM3_PWM4_OUT_TRIG0_1 output assigned to XBARB3_IN31 input. */ + kXBARB3_InputFlexpwm4Pwm1OutTrig01 = 32|0x300U, /**< FLEXPWM4_PWM1_OUT_TRIG0_1 output assigned to XBARB3_IN32 input. */ + kXBARB3_InputFlexpwm4Pwm2OutTrig01 = 33|0x300U, /**< FLEXPWM4_PWM2_OUT_TRIG0_1 output assigned to XBARB3_IN33 input. */ + kXBARB3_InputFlexpwm4Pwm3OutTrig01 = 34|0x300U, /**< FLEXPWM4_PWM3_OUT_TRIG0_1 output assigned to XBARB3_IN34 input. */ + kXBARB3_InputFlexpwm4Pwm4OutTrig01 = 35|0x300U, /**< FLEXPWM4_PWM4_OUT_TRIG0_1 output assigned to XBARB3_IN35 input. */ + kXBARB3_InputPitTrigger0 = 36|0x300U, /**< PIT_TRIGGER0 output assigned to XBARB3_IN36 input. */ + kXBARB3_InputPitTrigger1 = 37|0x300U, /**< PIT_TRIGGER1 output assigned to XBARB3_IN37 input. */ + kXBARB3_InputAdcEtcXbar0Coco0 = 38|0x300U, /**< ADC_ETC_XBAR0_COCO0 output assigned to XBARB3_IN38 input. */ + kXBARB3_InputAdcEtcXbar0Coco1 = 39|0x300U, /**< ADC_ETC_XBAR0_COCO1 output assigned to XBARB3_IN39 input. */ + kXBARB3_InputAdcEtcXbar0Coco2 = 40|0x300U, /**< ADC_ETC_XBAR0_COCO2 output assigned to XBARB3_IN40 input. */ + kXBARB3_InputAdcEtcXbar0Coco3 = 41|0x300U, /**< ADC_ETC_XBAR0_COCO3 output assigned to XBARB3_IN41 input. */ + kXBARB3_InputAdcEtcXbar1Coco0 = 42|0x300U, /**< ADC_ETC_XBAR1_COCO0 output assigned to XBARB3_IN42 input. */ + kXBARB3_InputAdcEtcXbar1Coco1 = 43|0x300U, /**< ADC_ETC_XBAR1_COCO1 output assigned to XBARB3_IN43 input. */ + kXBARB3_InputAdcEtcXbar1Coco2 = 44|0x300U, /**< ADC_ETC_XBAR1_COCO2 output assigned to XBARB3_IN44 input. */ + kXBARB3_InputAdcEtcXbar1Coco3 = 45|0x300U, /**< ADC_ETC_XBAR1_COCO3 output assigned to XBARB3_IN45 input. */ + kXBARB3_InputEnc1PosMatch = 46|0x300U, /**< ENC1_POS_MATCH output assigned to XBARB3_IN46 input. */ + kXBARB3_InputEnc2PosMatch = 47|0x300U, /**< ENC2_POS_MATCH output assigned to XBARB3_IN47 input. */ + kXBARB3_InputEnc3PosMatch = 48|0x300U, /**< ENC3_POS_MATCH output assigned to XBARB3_IN48 input. */ + kXBARB3_InputEnc4PosMatch = 49|0x300U, /**< ENC4_POS_MATCH output assigned to XBARB3_IN49 input. */ + kXBARB3_InputDmaDone0 = 50|0x300U, /**< DMA_DONE0 output assigned to XBARB3_IN50 input. */ + kXBARB3_InputDmaDone1 = 51|0x300U, /**< DMA_DONE1 output assigned to XBARB3_IN51 input. */ + kXBARB3_InputDmaDone2 = 52|0x300U, /**< DMA_DONE2 output assigned to XBARB3_IN52 input. */ + kXBARB3_InputDmaDone3 = 53|0x300U, /**< DMA_DONE3 output assigned to XBARB3_IN53 input. */ + kXBARB3_InputDmaDone4 = 54|0x300U, /**< DMA_DONE4 output assigned to XBARB3_IN54 input. */ + kXBARB3_InputDmaDone5 = 55|0x300U, /**< DMA_DONE5 output assigned to XBARB3_IN55 input. */ + kXBARB3_InputDmaDone6 = 56|0x300U, /**< DMA_DONE6 output assigned to XBARB3_IN56 input. */ + kXBARB3_InputDmaDone7 = 57|0x300U, /**< DMA_DONE7 output assigned to XBARB3_IN57 input. */ +} xbar_input_signal_t; + +typedef enum _xbar_output_signal +{ + kXBARA1_OutputDmaChMuxReq30 = 0|0x100U, /**< XBARA1_OUT0 output assigned to DMA_CH_MUX_REQ30 */ + kXBARA1_OutputDmaChMuxReq31 = 1|0x100U, /**< XBARA1_OUT1 output assigned to DMA_CH_MUX_REQ31 */ + kXBARA1_OutputDmaChMuxReq94 = 2|0x100U, /**< XBARA1_OUT2 output assigned to DMA_CH_MUX_REQ94 */ + kXBARA1_OutputDmaChMuxReq95 = 3|0x100U, /**< XBARA1_OUT3 output assigned to DMA_CH_MUX_REQ95 */ + kXBARA1_OutputIomuxXbarInout04 = 4|0x100U, /**< XBARA1_OUT4 output assigned to IOMUX_XBAR_INOUT04 */ + kXBARA1_OutputIomuxXbarInout05 = 5|0x100U, /**< XBARA1_OUT5 output assigned to IOMUX_XBAR_INOUT05 */ + kXBARA1_OutputIomuxXbarInout06 = 6|0x100U, /**< XBARA1_OUT6 output assigned to IOMUX_XBAR_INOUT06 */ + kXBARA1_OutputIomuxXbarInout07 = 7|0x100U, /**< XBARA1_OUT7 output assigned to IOMUX_XBAR_INOUT07 */ + kXBARA1_OutputIomuxXbarInout08 = 8|0x100U, /**< XBARA1_OUT8 output assigned to IOMUX_XBAR_INOUT08 */ + kXBARA1_OutputIomuxXbarInout09 = 9|0x100U, /**< XBARA1_OUT9 output assigned to IOMUX_XBAR_INOUT09 */ + kXBARA1_OutputIomuxXbarInout10 = 10|0x100U, /**< XBARA1_OUT10 output assigned to IOMUX_XBAR_INOUT10 */ + kXBARA1_OutputIomuxXbarInout11 = 11|0x100U, /**< XBARA1_OUT11 output assigned to IOMUX_XBAR_INOUT11 */ + kXBARA1_OutputIomuxXbarInout12 = 12|0x100U, /**< XBARA1_OUT12 output assigned to IOMUX_XBAR_INOUT12 */ + kXBARA1_OutputIomuxXbarInout13 = 13|0x100U, /**< XBARA1_OUT13 output assigned to IOMUX_XBAR_INOUT13 */ + kXBARA1_OutputIomuxXbarInout14 = 14|0x100U, /**< XBARA1_OUT14 output assigned to IOMUX_XBAR_INOUT14 */ + kXBARA1_OutputIomuxXbarInout15 = 15|0x100U, /**< XBARA1_OUT15 output assigned to IOMUX_XBAR_INOUT15 */ + kXBARA1_OutputIomuxXbarInout16 = 16|0x100U, /**< XBARA1_OUT16 output assigned to IOMUX_XBAR_INOUT16 */ + kXBARA1_OutputIomuxXbarInout17 = 17|0x100U, /**< XBARA1_OUT17 output assigned to IOMUX_XBAR_INOUT17 */ + kXBARA1_OutputIomuxXbarInout18 = 18|0x100U, /**< XBARA1_OUT18 output assigned to IOMUX_XBAR_INOUT18 */ + kXBARA1_OutputIomuxXbarInout19 = 19|0x100U, /**< XBARA1_OUT19 output assigned to IOMUX_XBAR_INOUT19 */ + kXBARA1_OutputAcmp1Sample = 20|0x100U, /**< XBARA1_OUT20 output assigned to ACMP1_SAMPLE */ + kXBARA1_OutputAcmp2Sample = 21|0x100U, /**< XBARA1_OUT21 output assigned to ACMP2_SAMPLE */ + kXBARA1_OutputAcmp3Sample = 22|0x100U, /**< XBARA1_OUT22 output assigned to ACMP3_SAMPLE */ + kXBARA1_OutputAcmp4Sample = 23|0x100U, /**< XBARA1_OUT23 output assigned to ACMP4_SAMPLE */ + kXBARA1_OutputRESERVED24 = 24|0x100U, /**< XBARA1_OUT24 output is reserved. */ + kXBARA1_OutputRESERVED25 = 25|0x100U, /**< XBARA1_OUT25 output is reserved. */ + kXBARA1_OutputFlexpwm1Exta0 = 26|0x100U, /**< XBARA1_OUT26 output assigned to FLEXPWM1_EXTA0 */ + kXBARA1_OutputFlexpwm1Exta1 = 27|0x100U, /**< XBARA1_OUT27 output assigned to FLEXPWM1_EXTA1 */ + kXBARA1_OutputFlexpwm1Exta2 = 28|0x100U, /**< XBARA1_OUT28 output assigned to FLEXPWM1_EXTA2 */ + kXBARA1_OutputFlexpwm1Exta3 = 29|0x100U, /**< XBARA1_OUT29 output assigned to FLEXPWM1_EXTA3 */ + kXBARA1_OutputFlexpwm1ExtSync0 = 30|0x100U, /**< XBARA1_OUT30 output assigned to FLEXPWM1_EXT_SYNC0 */ + kXBARA1_OutputFlexpwm1ExtSync1 = 31|0x100U, /**< XBARA1_OUT31 output assigned to FLEXPWM1_EXT_SYNC1 */ + kXBARA1_OutputFlexpwm1ExtSync2 = 32|0x100U, /**< XBARA1_OUT32 output assigned to FLEXPWM1_EXT_SYNC2 */ + kXBARA1_OutputFlexpwm1ExtSync3 = 33|0x100U, /**< XBARA1_OUT33 output assigned to FLEXPWM1_EXT_SYNC3 */ + kXBARA1_OutputFlexpwm1ExtClk = 34|0x100U, /**< XBARA1_OUT34 output assigned to FLEXPWM1_EXT_CLK */ + kXBARA1_OutputFlexpwm1Fault0 = 35|0x100U, /**< XBARA1_OUT35 output assigned to FLEXPWM1_FAULT0 */ + kXBARA1_OutputFlexpwm1Fault1 = 36|0x100U, /**< XBARA1_OUT36 output assigned to FLEXPWM1_FAULT1 */ + kXBARA1_OutputFlexpwm1234Fault2 = 37|0x100U, /**< XBARA1_OUT37 output assigned to FLEXPWM1_2_3_4_FAULT2 */ + kXBARA1_OutputFlexpwm1234Fault3 = 38|0x100U, /**< XBARA1_OUT38 output assigned to FLEXPWM1_2_3_4_FAULT3 */ + kXBARA1_OutputFlexpwm1ExtForce = 39|0x100U, /**< XBARA1_OUT39 output assigned to FLEXPWM1_EXT_FORCE */ + kXBARA1_OutputFlexpwm234Exta0 = 40|0x100U, /**< XBARA1_OUT40 output assigned to FLEXPWM2_3_4_EXTA0 */ + kXBARA1_OutputFlexpwm234Exta1 = 41|0x100U, /**< XBARA1_OUT41 output assigned to FLEXPWM2_3_4_EXTA1 */ + kXBARA1_OutputFlexpwm234Exta2 = 42|0x100U, /**< XBARA1_OUT42 output assigned to FLEXPWM2_3_4_EXTA2 */ + kXBARA1_OutputFlexpwm234Exta3 = 43|0x100U, /**< XBARA1_OUT43 output assigned to FLEXPWM2_3_4_EXTA3 */ + kXBARA1_OutputFlexpwm2ExtSync0 = 44|0x100U, /**< XBARA1_OUT44 output assigned to FLEXPWM2_EXT_SYNC0 */ + kXBARA1_OutputFlexpwm2ExtSync1 = 45|0x100U, /**< XBARA1_OUT45 output assigned to FLEXPWM2_EXT_SYNC1 */ + kXBARA1_OutputFlexpwm2ExtSync2 = 46|0x100U, /**< XBARA1_OUT46 output assigned to FLEXPWM2_EXT_SYNC2 */ + kXBARA1_OutputFlexpwm2ExtSync3 = 47|0x100U, /**< XBARA1_OUT47 output assigned to FLEXPWM2_EXT_SYNC3 */ + kXBARA1_OutputFlexpwm234ExtClk = 48|0x100U, /**< XBARA1_OUT48 output assigned to FLEXPWM2_3_4_EXT_CLK */ + kXBARA1_OutputFlexpwm2Fault0 = 49|0x100U, /**< XBARA1_OUT49 output assigned to FLEXPWM2_FAULT0 */ + kXBARA1_OutputFlexpwm2Fault1 = 50|0x100U, /**< XBARA1_OUT50 output assigned to FLEXPWM2_FAULT1 */ + kXBARA1_OutputFlexpwm2ExtForce = 51|0x100U, /**< XBARA1_OUT51 output assigned to FLEXPWM2_EXT_FORCE */ + kXBARA1_OutputFlexpwm3ExtSync0 = 52|0x100U, /**< XBARA1_OUT52 output assigned to FLEXPWM3_EXT_SYNC0 */ + kXBARA1_OutputFlexpwm3ExtSync1 = 53|0x100U, /**< XBARA1_OUT53 output assigned to FLEXPWM3_EXT_SYNC1 */ + kXBARA1_OutputFlexpwm3ExtSync2 = 54|0x100U, /**< XBARA1_OUT54 output assigned to FLEXPWM3_EXT_SYNC2 */ + kXBARA1_OutputFlexpwm3ExtSync3 = 55|0x100U, /**< XBARA1_OUT55 output assigned to FLEXPWM3_EXT_SYNC3 */ + kXBARA1_OutputFlexpwm3Fault0 = 56|0x100U, /**< XBARA1_OUT56 output assigned to FLEXPWM3_FAULT0 */ + kXBARA1_OutputFlexpwm3Fault1 = 57|0x100U, /**< XBARA1_OUT57 output assigned to FLEXPWM3_FAULT1 */ + kXBARA1_OutputFlexpwm3ExtForce = 58|0x100U, /**< XBARA1_OUT58 output assigned to FLEXPWM3_EXT_FORCE */ + kXBARA1_OutputFlexpwm4ExtSync0 = 59|0x100U, /**< XBARA1_OUT59 output assigned to FLEXPWM4_EXT_SYNC0 */ + kXBARA1_OutputFlexpwm4ExtSync1 = 60|0x100U, /**< XBARA1_OUT60 output assigned to FLEXPWM4_EXT_SYNC1 */ + kXBARA1_OutputFlexpwm4ExtSync2 = 61|0x100U, /**< XBARA1_OUT61 output assigned to FLEXPWM4_EXT_SYNC2 */ + kXBARA1_OutputFlexpwm4ExtSync3 = 62|0x100U, /**< XBARA1_OUT62 output assigned to FLEXPWM4_EXT_SYNC3 */ + kXBARA1_OutputFlexpwm4Fault0 = 63|0x100U, /**< XBARA1_OUT63 output assigned to FLEXPWM4_FAULT0 */ + kXBARA1_OutputFlexpwm4Fault1 = 64|0x100U, /**< XBARA1_OUT64 output assigned to FLEXPWM4_FAULT1 */ + kXBARA1_OutputFlexpwm4ExtForce = 65|0x100U, /**< XBARA1_OUT65 output assigned to FLEXPWM4_EXT_FORCE */ + kXBARA1_OutputEnc1PhaseAInput = 66|0x100U, /**< XBARA1_OUT66 output assigned to ENC1_PHASE_A_INPUT */ + kXBARA1_OutputEnc1PhaseBInput = 67|0x100U, /**< XBARA1_OUT67 output assigned to ENC1_PHASE_B_INPUT */ + kXBARA1_OutputEnc1Index = 68|0x100U, /**< XBARA1_OUT68 output assigned to ENC1_INDEX */ + kXBARA1_OutputEnc1Home = 69|0x100U, /**< XBARA1_OUT69 output assigned to ENC1_HOME */ + kXBARA1_OutputEnc1Trigger = 70|0x100U, /**< XBARA1_OUT70 output assigned to ENC1_TRIGGER */ + kXBARA1_OutputEnc2PhaseAInput = 71|0x100U, /**< XBARA1_OUT71 output assigned to ENC2_PHASE_A_INPUT */ + kXBARA1_OutputEnc2PhaseBInput = 72|0x100U, /**< XBARA1_OUT72 output assigned to ENC2_PHASE_B_INPUT */ + kXBARA1_OutputEnc2Index = 73|0x100U, /**< XBARA1_OUT73 output assigned to ENC2_INDEX */ + kXBARA1_OutputEnc2Home = 74|0x100U, /**< XBARA1_OUT74 output assigned to ENC2_HOME */ + kXBARA1_OutputEnc2Trigger = 75|0x100U, /**< XBARA1_OUT75 output assigned to ENC2_TRIGGER */ + kXBARA1_OutputEnc3PhaseAInput = 76|0x100U, /**< XBARA1_OUT76 output assigned to ENC3_PHASE_A_INPUT */ + kXBARA1_OutputEnc3PhaseBInput = 77|0x100U, /**< XBARA1_OUT77 output assigned to ENC3_PHASE_B_INPUT */ + kXBARA1_OutputEnc3Index = 78|0x100U, /**< XBARA1_OUT78 output assigned to ENC3_INDEX */ + kXBARA1_OutputEnc3Home = 79|0x100U, /**< XBARA1_OUT79 output assigned to ENC3_HOME */ + kXBARA1_OutputEnc3Trigger = 80|0x100U, /**< XBARA1_OUT80 output assigned to ENC3_TRIGGER */ + kXBARA1_OutputEnc4PhaseAInput = 81|0x100U, /**< XBARA1_OUT81 output assigned to ENC4_PHASE_A_INPUT */ + kXBARA1_OutputEnc4PhaseBInput = 82|0x100U, /**< XBARA1_OUT82 output assigned to ENC4_PHASE_B_INPUT */ + kXBARA1_OutputEnc4Index = 83|0x100U, /**< XBARA1_OUT83 output assigned to ENC4_INDEX */ + kXBARA1_OutputEnc4Home = 84|0x100U, /**< XBARA1_OUT84 output assigned to ENC4_HOME */ + kXBARA1_OutputEnc4Trigger = 85|0x100U, /**< XBARA1_OUT85 output assigned to ENC4_TRIGGER */ + kXBARA1_OutputQtimer1Tmr0Input = 86|0x100U, /**< XBARA1_OUT86 output assigned to QTIMER1_TMR0_INPUT */ + kXBARA1_OutputQtimer1Tmr1Input = 87|0x100U, /**< XBARA1_OUT87 output assigned to QTIMER1_TMR1_INPUT */ + kXBARA1_OutputQtimer1Tmr2Input = 88|0x100U, /**< XBARA1_OUT88 output assigned to QTIMER1_TMR2_INPUT */ + kXBARA1_OutputQtimer1Tmr3Input = 89|0x100U, /**< XBARA1_OUT89 output assigned to QTIMER1_TMR3_INPUT */ + kXBARA1_OutputQtimer2Tmr0Input = 90|0x100U, /**< XBARA1_OUT90 output assigned to QTIMER2_TMR0_INPUT */ + kXBARA1_OutputQtimer2Tmr1Input = 91|0x100U, /**< XBARA1_OUT91 output assigned to QTIMER2_TMR1_INPUT */ + kXBARA1_OutputQtimer2Tmr2Input = 92|0x100U, /**< XBARA1_OUT92 output assigned to QTIMER2_TMR2_INPUT */ + kXBARA1_OutputQtimer2Tmr3Input = 93|0x100U, /**< XBARA1_OUT93 output assigned to QTIMER2_TMR3_INPUT */ + kXBARA1_OutputQtimer3Tmr0Input = 94|0x100U, /**< XBARA1_OUT94 output assigned to QTIMER3_TMR0_INPUT */ + kXBARA1_OutputQtimer3Tmr1Input = 95|0x100U, /**< XBARA1_OUT95 output assigned to QTIMER3_TMR1_INPUT */ + kXBARA1_OutputQtimer3Tmr2Input = 96|0x100U, /**< XBARA1_OUT96 output assigned to QTIMER3_TMR2_INPUT */ + kXBARA1_OutputQtimer3Tmr3Input = 97|0x100U, /**< XBARA1_OUT97 output assigned to QTIMER3_TMR3_INPUT */ + kXBARA1_OutputQtimer4Tmr0Input = 98|0x100U, /**< XBARA1_OUT98 output assigned to QTIMER4_TMR0_INPUT */ + kXBARA1_OutputQtimer4Tmr1Input = 99|0x100U, /**< XBARA1_OUT99 output assigned to QTIMER4_TMR1_INPUT */ + kXBARA1_OutputQtimer4Tmr2Input = 100|0x100U, /**< XBARA1_OUT100 output assigned to QTIMER4_TMR2_INPUT */ + kXBARA1_OutputQtimer4Tmr3Input = 101|0x100U, /**< XBARA1_OUT101 output assigned to QTIMER4_TMR3_INPUT */ + kXBARA1_OutputEwmEwmIn = 102|0x100U, /**< XBARA1_OUT102 output assigned to EWM_EWM_IN */ + kXBARA1_OutputAdcEtcXbar0Trig0 = 103|0x100U, /**< XBARA1_OUT103 output assigned to ADC_ETC_XBAR0_TRIG0 */ + kXBARA1_OutputAdcEtcXbar0Trig1 = 104|0x100U, /**< XBARA1_OUT104 output assigned to ADC_ETC_XBAR0_TRIG1 */ + kXBARA1_OutputAdcEtcXbar0Trig2 = 105|0x100U, /**< XBARA1_OUT105 output assigned to ADC_ETC_XBAR0_TRIG2 */ + kXBARA1_OutputAdcEtcXbar0Trig3 = 106|0x100U, /**< XBARA1_OUT106 output assigned to ADC_ETC_XBAR0_TRIG3 */ + kXBARA1_OutputAdcEtcXbar1Trig0 = 107|0x100U, /**< XBARA1_OUT107 output assigned to ADC_ETC_XBAR1_TRIG0 */ + kXBARA1_OutputAdcEtcXbar1Trig1 = 108|0x100U, /**< XBARA1_OUT108 output assigned to ADC_ETC_XBAR1_TRIG1 */ + kXBARA1_OutputAdcEtcXbar1Trig2 = 109|0x100U, /**< XBARA1_OUT109 output assigned to ADC_ETC_XBAR1_TRIG2 */ + kXBARA1_OutputAdcEtcXbar1Trig3 = 110|0x100U, /**< XBARA1_OUT110 output assigned to ADC_ETC_XBAR1_TRIG3 */ + kXBARA1_OutputLpi2c1TrgInput = 111|0x100U, /**< XBARA1_OUT111 output assigned to LPI2C1_TRG_INPUT */ + kXBARA1_OutputLpi2c2TrgInput = 112|0x100U, /**< XBARA1_OUT112 output assigned to LPI2C2_TRG_INPUT */ + kXBARA1_OutputLpi2c3TrgInput = 113|0x100U, /**< XBARA1_OUT113 output assigned to LPI2C3_TRG_INPUT */ + kXBARA1_OutputLpi2c4TrgInput = 114|0x100U, /**< XBARA1_OUT114 output assigned to LPI2C4_TRG_INPUT */ + kXBARA1_OutputLpspi1TrgInput = 115|0x100U, /**< XBARA1_OUT115 output assigned to LPSPI1_TRG_INPUT */ + kXBARA1_OutputLpspi2TrgInput = 116|0x100U, /**< XBARA1_OUT116 output assigned to LPSPI2_TRG_INPUT */ + kXBARA1_OutputLpspi3TrgInput = 117|0x100U, /**< XBARA1_OUT117 output assigned to LPSPI3_TRG_INPUT */ + kXBARA1_OutputLpspi4TrgInput = 118|0x100U, /**< XBARA1_OUT118 output assigned to LPSPI4_TRG_INPUT */ + kXBARA1_OutputLpuart1TrgInput = 119|0x100U, /**< XBARA1_OUT119 output assigned to LPUART1_TRG_INPUT */ + kXBARA1_OutputLpuart2TrgInput = 120|0x100U, /**< XBARA1_OUT120 output assigned to LPUART2_TRG_INPUT */ + kXBARA1_OutputLpuart3TrgInput = 121|0x100U, /**< XBARA1_OUT121 output assigned to LPUART3_TRG_INPUT */ + kXBARA1_OutputLpuart4TrgInput = 122|0x100U, /**< XBARA1_OUT122 output assigned to LPUART4_TRG_INPUT */ + kXBARA1_OutputLpuart5TrgInput = 123|0x100U, /**< XBARA1_OUT123 output assigned to LPUART5_TRG_INPUT */ + kXBARA1_OutputLpuart6TrgInput = 124|0x100U, /**< XBARA1_OUT124 output assigned to LPUART6_TRG_INPUT */ + kXBARA1_OutputLpuart7TrgInput = 125|0x100U, /**< XBARA1_OUT125 output assigned to LPUART7_TRG_INPUT */ + kXBARA1_OutputLpuart8TrgInput = 126|0x100U, /**< XBARA1_OUT126 output assigned to LPUART8_TRG_INPUT */ + kXBARA1_OutputFlexio1TriggerIn0 = 127|0x100U, /**< XBARA1_OUT127 output assigned to FLEXIO1_TRIGGER_IN0 */ + kXBARA1_OutputFlexio1TriggerIn1 = 128|0x100U, /**< XBARA1_OUT128 output assigned to FLEXIO1_TRIGGER_IN1 */ + kXBARA1_OutputFlexio2TriggerIn0 = 129|0x100U, /**< XBARA1_OUT129 output assigned to FLEXIO2_TRIGGER_IN0 */ + kXBARA1_OutputFlexio2TriggerIn1 = 130|0x100U, /**< XBARA1_OUT130 output assigned to FLEXIO2_TRIGGER_IN1 */ + kXBARB2_OutputAoi1In00 = 0|0x200U, /**< XBARB2_OUT0 output assigned to AOI1_IN00 */ + kXBARB2_OutputAoi1In01 = 1|0x200U, /**< XBARB2_OUT1 output assigned to AOI1_IN01 */ + kXBARB2_OutputAoi1In02 = 2|0x200U, /**< XBARB2_OUT2 output assigned to AOI1_IN02 */ + kXBARB2_OutputAoi1In03 = 3|0x200U, /**< XBARB2_OUT3 output assigned to AOI1_IN03 */ + kXBARB2_OutputAoi1In04 = 4|0x200U, /**< XBARB2_OUT4 output assigned to AOI1_IN04 */ + kXBARB2_OutputAoi1In05 = 5|0x200U, /**< XBARB2_OUT5 output assigned to AOI1_IN05 */ + kXBARB2_OutputAoi1In06 = 6|0x200U, /**< XBARB2_OUT6 output assigned to AOI1_IN06 */ + kXBARB2_OutputAoi1In07 = 7|0x200U, /**< XBARB2_OUT7 output assigned to AOI1_IN07 */ + kXBARB2_OutputAoi1In08 = 8|0x200U, /**< XBARB2_OUT8 output assigned to AOI1_IN08 */ + kXBARB2_OutputAoi1In09 = 9|0x200U, /**< XBARB2_OUT9 output assigned to AOI1_IN09 */ + kXBARB2_OutputAoi1In10 = 10|0x200U, /**< XBARB2_OUT10 output assigned to AOI1_IN10 */ + kXBARB2_OutputAoi1In11 = 11|0x200U, /**< XBARB2_OUT11 output assigned to AOI1_IN11 */ + kXBARB2_OutputAoi1In12 = 12|0x200U, /**< XBARB2_OUT12 output assigned to AOI1_IN12 */ + kXBARB2_OutputAoi1In13 = 13|0x200U, /**< XBARB2_OUT13 output assigned to AOI1_IN13 */ + kXBARB2_OutputAoi1In14 = 14|0x200U, /**< XBARB2_OUT14 output assigned to AOI1_IN14 */ + kXBARB2_OutputAoi1In15 = 15|0x200U, /**< XBARB2_OUT15 output assigned to AOI1_IN15 */ + kXBARB3_OutputAoi2In00 = 0|0x300U, /**< XBARB3_OUT0 output assigned to AOI2_IN00 */ + kXBARB3_OutputAoi2In01 = 1|0x300U, /**< XBARB3_OUT1 output assigned to AOI2_IN01 */ + kXBARB3_OutputAoi2In02 = 2|0x300U, /**< XBARB3_OUT2 output assigned to AOI2_IN02 */ + kXBARB3_OutputAoi2In03 = 3|0x300U, /**< XBARB3_OUT3 output assigned to AOI2_IN03 */ + kXBARB3_OutputAoi2In04 = 4|0x300U, /**< XBARB3_OUT4 output assigned to AOI2_IN04 */ + kXBARB3_OutputAoi2In05 = 5|0x300U, /**< XBARB3_OUT5 output assigned to AOI2_IN05 */ + kXBARB3_OutputAoi2In06 = 6|0x300U, /**< XBARB3_OUT6 output assigned to AOI2_IN06 */ + kXBARB3_OutputAoi2In07 = 7|0x300U, /**< XBARB3_OUT7 output assigned to AOI2_IN07 */ + kXBARB3_OutputAoi2In08 = 8|0x300U, /**< XBARB3_OUT8 output assigned to AOI2_IN08 */ + kXBARB3_OutputAoi2In09 = 9|0x300U, /**< XBARB3_OUT9 output assigned to AOI2_IN09 */ + kXBARB3_OutputAoi2In10 = 10|0x300U, /**< XBARB3_OUT10 output assigned to AOI2_IN10 */ + kXBARB3_OutputAoi2In11 = 11|0x300U, /**< XBARB3_OUT11 output assigned to AOI2_IN11 */ + kXBARB3_OutputAoi2In12 = 12|0x300U, /**< XBARB3_OUT12 output assigned to AOI2_IN12 */ + kXBARB3_OutputAoi2In13 = 13|0x300U, /**< XBARB3_OUT13 output assigned to AOI2_IN13 */ + kXBARB3_OutputAoi2In14 = 14|0x300U, /**< XBARB3_OUT14 output assigned to AOI2_IN14 */ + kXBARB3_OutputAoi2In15 = 15|0x300U, /**< XBARB3_OUT15 output assigned to AOI2_IN15 */ +} xbar_output_signal_t; + + +/*! + * @} + */ /* end of group Mapping_Information */ + + +/* ---------------------------------------------------------------------------- + -- Device Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup Peripheral_access_layer Device Peripheral Access Layer + * @{ + */ + + +/* +** Start of section using anonymous unions +*/ + +#if defined(__ARMCC_VERSION) + #if (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic push + #else + #pragma push + #pragma anon_unions + #endif +#elif defined(__CWCC__) + #pragma push + #pragma cpp_extensions on +#elif defined(__GNUC__) + /* anonymous unions are enabled by default */ +#elif defined(__IAR_SYSTEMS_ICC__) + #pragma language=extended +#else + #error Not supported compiler type +#endif + +/* ---------------------------------------------------------------------------- + -- ADC Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup ADC_Peripheral_Access_Layer ADC Peripheral Access Layer + * @{ + */ + +/** ADC - Register Layout Typedef */ +typedef struct { + __IO uint32_t HC[8]; /**< Control register for hardware triggers, array offset: 0x0, array step: 0x4 */ + __I uint32_t HS; /**< Status register for HW triggers, offset: 0x20 */ + __I uint32_t R[8]; /**< Data result register for HW triggers, array offset: 0x24, array step: 0x4 */ + __IO uint32_t CFG; /**< Configuration register, offset: 0x44 */ + __IO uint32_t GC; /**< General control register, offset: 0x48 */ + __IO uint32_t GS; /**< General status register, offset: 0x4C */ + __IO uint32_t CV; /**< Compare value register, offset: 0x50 */ + __IO uint32_t OFS; /**< Offset correction value register, offset: 0x54 */ + __IO uint32_t CAL; /**< Calibration value register, offset: 0x58 */ +} ADC_Type; + +/* ---------------------------------------------------------------------------- + -- ADC Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup ADC_Register_Masks ADC Register Masks + * @{ + */ + +/*! @name HC - Control register for hardware triggers */ +/*! @{ */ +#define ADC_HC_ADCH_MASK (0x1FU) +#define ADC_HC_ADCH_SHIFT (0U) +/*! ADCH - Input Channel Select + * 0b10000..External channel selection from ADC_ETC + * 0b11000..Reserved. + * 0b11001..VREFSH = internal channel, for ADC self-test, hard connected to VRH internally + * 0b11010..Reserved. + * 0b11011..Reserved. + * 0b11111..Conversion Disabled. Hardware Triggers will not initiate any conversion. + */ +#define ADC_HC_ADCH(x) (((uint32_t)(((uint32_t)(x)) << ADC_HC_ADCH_SHIFT)) & ADC_HC_ADCH_MASK) +#define ADC_HC_AIEN_MASK (0x80U) +#define ADC_HC_AIEN_SHIFT (7U) +/*! AIEN - Conversion Complete Interrupt Enable/Disable Control + * 0b1..Conversion complete interrupt enabled + * 0b0..Conversion complete interrupt disabled + */ +#define ADC_HC_AIEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_HC_AIEN_SHIFT)) & ADC_HC_AIEN_MASK) +/*! @} */ + +/* The count of ADC_HC */ +#define ADC_HC_COUNT (8U) + +/*! @name HS - Status register for HW triggers */ +/*! @{ */ +#define ADC_HS_COCO0_MASK (0x1U) +#define ADC_HS_COCO0_SHIFT (0U) +#define ADC_HS_COCO0(x) (((uint32_t)(((uint32_t)(x)) << ADC_HS_COCO0_SHIFT)) & ADC_HS_COCO0_MASK) +/*! @} */ + +/*! @name R - Data result register for HW triggers */ +/*! @{ */ +#define ADC_R_CDATA_MASK (0xFFFU) +#define ADC_R_CDATA_SHIFT (0U) +#define ADC_R_CDATA(x) (((uint32_t)(((uint32_t)(x)) << ADC_R_CDATA_SHIFT)) & ADC_R_CDATA_MASK) +/*! @} */ + +/* The count of ADC_R */ +#define ADC_R_COUNT (8U) + +/*! @name CFG - Configuration register */ +/*! @{ */ +#define ADC_CFG_ADICLK_MASK (0x3U) +#define ADC_CFG_ADICLK_SHIFT (0U) +/*! ADICLK - Input Clock Select + * 0b00..IPG clock + * 0b01..IPG clock divided by 2 + * 0b10..Reserved + * 0b11..Asynchronous clock (ADACK) + */ +#define ADC_CFG_ADICLK(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_ADICLK_SHIFT)) & ADC_CFG_ADICLK_MASK) +#define ADC_CFG_MODE_MASK (0xCU) +#define ADC_CFG_MODE_SHIFT (2U) +/*! MODE - Conversion Mode Selection + * 0b00..8-bit conversion + * 0b01..10-bit conversion + * 0b10..12-bit conversion + * 0b11..Reserved + */ +#define ADC_CFG_MODE(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_MODE_SHIFT)) & ADC_CFG_MODE_MASK) +#define ADC_CFG_ADLSMP_MASK (0x10U) +#define ADC_CFG_ADLSMP_SHIFT (4U) +/*! ADLSMP - Long Sample Time Configuration + * 0b0..Short sample mode. + * 0b1..Long sample mode. + */ +#define ADC_CFG_ADLSMP(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_ADLSMP_SHIFT)) & ADC_CFG_ADLSMP_MASK) +#define ADC_CFG_ADIV_MASK (0x60U) +#define ADC_CFG_ADIV_SHIFT (5U) +/*! ADIV - Clock Divide Select + * 0b00..Input clock + * 0b01..Input clock / 2 + * 0b10..Input clock / 4 + * 0b11..Input clock / 8 + */ +#define ADC_CFG_ADIV(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_ADIV_SHIFT)) & ADC_CFG_ADIV_MASK) +#define ADC_CFG_ADLPC_MASK (0x80U) +#define ADC_CFG_ADLPC_SHIFT (7U) +/*! ADLPC - Low-Power Configuration + * 0b0..ADC hard block not in low power mode. + * 0b1..ADC hard block in low power mode. + */ +#define ADC_CFG_ADLPC(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_ADLPC_SHIFT)) & ADC_CFG_ADLPC_MASK) +#define ADC_CFG_ADSTS_MASK (0x300U) +#define ADC_CFG_ADSTS_SHIFT (8U) +/*! ADSTS + * 0b00..Sample period (ADC clocks) = 2 if ADLSMP=0b Sample period (ADC clocks) = 12 if ADLSMP=1b + * 0b01..Sample period (ADC clocks) = 4 if ADLSMP=0b Sample period (ADC clocks) = 16 if ADLSMP=1b + * 0b10..Sample period (ADC clocks) = 6 if ADLSMP=0b Sample period (ADC clocks) = 20 if ADLSMP=1b + * 0b11..Sample period (ADC clocks) = 8 if ADLSMP=0b Sample period (ADC clocks) = 24 if ADLSMP=1b + */ +#define ADC_CFG_ADSTS(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_ADSTS_SHIFT)) & ADC_CFG_ADSTS_MASK) +#define ADC_CFG_ADHSC_MASK (0x400U) +#define ADC_CFG_ADHSC_SHIFT (10U) +/*! ADHSC - High Speed Configuration + * 0b0..Normal conversion selected. + * 0b1..High speed conversion selected. + */ +#define ADC_CFG_ADHSC(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_ADHSC_SHIFT)) & ADC_CFG_ADHSC_MASK) +#define ADC_CFG_REFSEL_MASK (0x1800U) +#define ADC_CFG_REFSEL_SHIFT (11U) +/*! REFSEL - Voltage Reference Selection + * 0b00..Selects VREFH/VREFL as reference voltage. + * 0b01..Reserved + * 0b10..Reserved + * 0b11..Reserved + */ +#define ADC_CFG_REFSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_REFSEL_SHIFT)) & ADC_CFG_REFSEL_MASK) +#define ADC_CFG_ADTRG_MASK (0x2000U) +#define ADC_CFG_ADTRG_SHIFT (13U) +/*! ADTRG - Conversion Trigger Select + * 0b0..Software trigger selected + * 0b1..Hardware trigger selected + */ +#define ADC_CFG_ADTRG(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_ADTRG_SHIFT)) & ADC_CFG_ADTRG_MASK) +#define ADC_CFG_AVGS_MASK (0xC000U) +#define ADC_CFG_AVGS_SHIFT (14U) +/*! AVGS - Hardware Average select + * 0b00..4 samples averaged + * 0b01..8 samples averaged + * 0b10..16 samples averaged + * 0b11..32 samples averaged + */ +#define ADC_CFG_AVGS(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_AVGS_SHIFT)) & ADC_CFG_AVGS_MASK) +#define ADC_CFG_OVWREN_MASK (0x10000U) +#define ADC_CFG_OVWREN_SHIFT (16U) +/*! OVWREN - Data Overwrite Enable + * 0b1..Enable the overwriting. + * 0b0..Disable the overwriting. Existing Data in Data result register will not be overwritten by subsequent converted data. + */ +#define ADC_CFG_OVWREN(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_OVWREN_SHIFT)) & ADC_CFG_OVWREN_MASK) +/*! @} */ + +/*! @name GC - General control register */ +/*! @{ */ +#define ADC_GC_ADACKEN_MASK (0x1U) +#define ADC_GC_ADACKEN_SHIFT (0U) +/*! ADACKEN - Asynchronous clock output enable + * 0b0..Asynchronous clock output disabled; Asynchronous clock only enabled if selected by ADICLK and a conversion is active. + * 0b1..Asynchronous clock and clock output enabled regardless of the state of the ADC + */ +#define ADC_GC_ADACKEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_GC_ADACKEN_SHIFT)) & ADC_GC_ADACKEN_MASK) +#define ADC_GC_DMAEN_MASK (0x2U) +#define ADC_GC_DMAEN_SHIFT (1U) +/*! DMAEN - DMA Enable + * 0b0..DMA disabled (default) + * 0b1..DMA enabled + */ +#define ADC_GC_DMAEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_GC_DMAEN_SHIFT)) & ADC_GC_DMAEN_MASK) +#define ADC_GC_ACREN_MASK (0x4U) +#define ADC_GC_ACREN_SHIFT (2U) +/*! ACREN - Compare Function Range Enable + * 0b0..Range function disabled. Only the compare value 1 of ADC_CV register (CV1) is compared. + * 0b1..Range function enabled. Both compare values of ADC_CV registers (CV1 and CV2) are compared. + */ +#define ADC_GC_ACREN(x) (((uint32_t)(((uint32_t)(x)) << ADC_GC_ACREN_SHIFT)) & ADC_GC_ACREN_MASK) +#define ADC_GC_ACFGT_MASK (0x8U) +#define ADC_GC_ACFGT_SHIFT (3U) +/*! ACFGT - Compare Function Greater Than Enable + * 0b0..Configures "Less Than Threshold, Outside Range Not Inclusive and Inside Range Not Inclusive" functionality based on the values placed in the ADC_CV register. + * 0b1..Configures "Greater Than Or Equal To Threshold, Outside Range Inclusive and Inside Range Inclusive" functionality based on the values placed in the ADC_CV registers. + */ +#define ADC_GC_ACFGT(x) (((uint32_t)(((uint32_t)(x)) << ADC_GC_ACFGT_SHIFT)) & ADC_GC_ACFGT_MASK) +#define ADC_GC_ACFE_MASK (0x10U) +#define ADC_GC_ACFE_SHIFT (4U) +/*! ACFE - Compare Function Enable + * 0b0..Compare function disabled + * 0b1..Compare function enabled + */ +#define ADC_GC_ACFE(x) (((uint32_t)(((uint32_t)(x)) << ADC_GC_ACFE_SHIFT)) & ADC_GC_ACFE_MASK) +#define ADC_GC_AVGE_MASK (0x20U) +#define ADC_GC_AVGE_SHIFT (5U) +/*! AVGE - Hardware average enable + * 0b0..Hardware average function disabled + * 0b1..Hardware average function enabled + */ +#define ADC_GC_AVGE(x) (((uint32_t)(((uint32_t)(x)) << ADC_GC_AVGE_SHIFT)) & ADC_GC_AVGE_MASK) +#define ADC_GC_ADCO_MASK (0x40U) +#define ADC_GC_ADCO_SHIFT (6U) +/*! ADCO - Continuous Conversion Enable + * 0b0..One conversion or one set of conversions if the hardware average function is enabled (AVGE=1) after initiating a conversion. + * 0b1..Continuous conversions or sets of conversions if the hardware average function is enabled (AVGE=1) after initiating a conversion. + */ +#define ADC_GC_ADCO(x) (((uint32_t)(((uint32_t)(x)) << ADC_GC_ADCO_SHIFT)) & ADC_GC_ADCO_MASK) +#define ADC_GC_CAL_MASK (0x80U) +#define ADC_GC_CAL_SHIFT (7U) +#define ADC_GC_CAL(x) (((uint32_t)(((uint32_t)(x)) << ADC_GC_CAL_SHIFT)) & ADC_GC_CAL_MASK) +/*! @} */ + +/*! @name GS - General status register */ +/*! @{ */ +#define ADC_GS_ADACT_MASK (0x1U) +#define ADC_GS_ADACT_SHIFT (0U) +/*! ADACT - Conversion Active + * 0b0..Conversion not in progress. + * 0b1..Conversion in progress. + */ +#define ADC_GS_ADACT(x) (((uint32_t)(((uint32_t)(x)) << ADC_GS_ADACT_SHIFT)) & ADC_GS_ADACT_MASK) +#define ADC_GS_CALF_MASK (0x2U) +#define ADC_GS_CALF_SHIFT (1U) +/*! CALF - Calibration Failed Flag + * 0b0..Calibration completed normally. + * 0b1..Calibration failed. ADC accuracy specifications are not guaranteed. + */ +#define ADC_GS_CALF(x) (((uint32_t)(((uint32_t)(x)) << ADC_GS_CALF_SHIFT)) & ADC_GS_CALF_MASK) +#define ADC_GS_AWKST_MASK (0x4U) +#define ADC_GS_AWKST_SHIFT (2U) +/*! AWKST - Asynchronous wakeup interrupt status + * 0b1..Asynchronous wake up interrupt occurred in stop mode. + * 0b0..No asynchronous interrupt. + */ +#define ADC_GS_AWKST(x) (((uint32_t)(((uint32_t)(x)) << ADC_GS_AWKST_SHIFT)) & ADC_GS_AWKST_MASK) +/*! @} */ + +/*! @name CV - Compare value register */ +/*! @{ */ +#define ADC_CV_CV1_MASK (0xFFFU) +#define ADC_CV_CV1_SHIFT (0U) +#define ADC_CV_CV1(x) (((uint32_t)(((uint32_t)(x)) << ADC_CV_CV1_SHIFT)) & ADC_CV_CV1_MASK) +#define ADC_CV_CV2_MASK (0xFFF0000U) +#define ADC_CV_CV2_SHIFT (16U) +#define ADC_CV_CV2(x) (((uint32_t)(((uint32_t)(x)) << ADC_CV_CV2_SHIFT)) & ADC_CV_CV2_MASK) +/*! @} */ + +/*! @name OFS - Offset correction value register */ +/*! @{ */ +#define ADC_OFS_OFS_MASK (0xFFFU) +#define ADC_OFS_OFS_SHIFT (0U) +#define ADC_OFS_OFS(x) (((uint32_t)(((uint32_t)(x)) << ADC_OFS_OFS_SHIFT)) & ADC_OFS_OFS_MASK) +#define ADC_OFS_SIGN_MASK (0x1000U) +#define ADC_OFS_SIGN_SHIFT (12U) +/*! SIGN - Sign bit + * 0b0..The offset value is added with the raw result + * 0b1..The offset value is subtracted from the raw converted value + */ +#define ADC_OFS_SIGN(x) (((uint32_t)(((uint32_t)(x)) << ADC_OFS_SIGN_SHIFT)) & ADC_OFS_SIGN_MASK) +/*! @} */ + +/*! @name CAL - Calibration value register */ +/*! @{ */ +#define ADC_CAL_CAL_CODE_MASK (0xFU) +#define ADC_CAL_CAL_CODE_SHIFT (0U) +#define ADC_CAL_CAL_CODE(x) (((uint32_t)(((uint32_t)(x)) << ADC_CAL_CAL_CODE_SHIFT)) & ADC_CAL_CAL_CODE_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group ADC_Register_Masks */ + + +/* ADC - Peripheral instance base addresses */ +/** Peripheral ADC1 base address */ +#define ADC1_BASE (0x400C4000u) +/** Peripheral ADC1 base pointer */ +#define ADC1 ((ADC_Type *)ADC1_BASE) +/** Peripheral ADC2 base address */ +#define ADC2_BASE (0x400C8000u) +/** Peripheral ADC2 base pointer */ +#define ADC2 ((ADC_Type *)ADC2_BASE) +/** Array initializer of ADC peripheral base addresses */ +#define ADC_BASE_ADDRS { 0u, ADC1_BASE, ADC2_BASE } +/** Array initializer of ADC peripheral base pointers */ +#define ADC_BASE_PTRS { (ADC_Type *)0u, ADC1, ADC2 } +/** Interrupt vectors for the ADC peripheral type */ +#define ADC_IRQS { NotAvail_IRQn, ADC1_IRQn, ADC2_IRQn } + +/*! + * @} + */ /* end of group ADC_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- ADC_ETC Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup ADC_ETC_Peripheral_Access_Layer ADC_ETC Peripheral Access Layer + * @{ + */ + +/** ADC_ETC - Register Layout Typedef */ +typedef struct { + __IO uint32_t CTRL; /**< ADC_ETC Global Control Register, offset: 0x0 */ + __IO uint32_t DONE0_1_IRQ; /**< ETC DONE0 and DONE1 IRQ State Register, offset: 0x4 */ + __IO uint32_t DONE2_ERR_IRQ; /**< ETC DONE_2 and DONE_ERR IRQ State Register, offset: 0x8 */ + __IO uint32_t DMA_CTRL; /**< ETC DMA control Register, offset: 0xC */ + struct { /* offset: 0x10, array step: 0x28 */ + __IO uint32_t TRIGn_CTRL; /**< ETC_TRIG0 Control Register..ETC_TRIG7 Control Register, array offset: 0x10, array step: 0x28 */ + __IO uint32_t TRIGn_COUNTER; /**< ETC_TRIG0 Counter Register..ETC_TRIG7 Counter Register, array offset: 0x14, array step: 0x28 */ + __IO uint32_t TRIGn_CHAIN_1_0; /**< ETC_TRIG Chain 0/1 Register, array offset: 0x18, array step: 0x28 */ + __IO uint32_t TRIGn_CHAIN_3_2; /**< ETC_TRIG Chain 2/3 Register, array offset: 0x1C, array step: 0x28 */ + __IO uint32_t TRIGn_CHAIN_5_4; /**< ETC_TRIG Chain 4/5 Register, array offset: 0x20, array step: 0x28 */ + __IO uint32_t TRIGn_CHAIN_7_6; /**< ETC_TRIG Chain 6/7 Register, array offset: 0x24, array step: 0x28 */ + __I uint32_t TRIGn_RESULT_1_0; /**< ETC_TRIG Result Data 1/0 Register, array offset: 0x28, array step: 0x28 */ + __I uint32_t TRIGn_RESULT_3_2; /**< ETC_TRIG Result Data 3/2 Register, array offset: 0x2C, array step: 0x28 */ + __I uint32_t TRIGn_RESULT_5_4; /**< ETC_TRIG Result Data 5/4 Register, array offset: 0x30, array step: 0x28 */ + __I uint32_t TRIGn_RESULT_7_6; /**< ETC_TRIG Result Data 7/6 Register, array offset: 0x34, array step: 0x28 */ + } TRIG[8]; +} ADC_ETC_Type; + +/* ---------------------------------------------------------------------------- + -- ADC_ETC Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup ADC_ETC_Register_Masks ADC_ETC Register Masks + * @{ + */ + +/*! @name CTRL - ADC_ETC Global Control Register */ +/*! @{ */ +#define ADC_ETC_CTRL_TRIG_ENABLE_MASK (0xFFU) +#define ADC_ETC_CTRL_TRIG_ENABLE_SHIFT (0U) +#define ADC_ETC_CTRL_TRIG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_CTRL_TRIG_ENABLE_SHIFT)) & ADC_ETC_CTRL_TRIG_ENABLE_MASK) +#define ADC_ETC_CTRL_EXT0_TRIG_ENABLE_MASK (0x100U) +#define ADC_ETC_CTRL_EXT0_TRIG_ENABLE_SHIFT (8U) +#define ADC_ETC_CTRL_EXT0_TRIG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_CTRL_EXT0_TRIG_ENABLE_SHIFT)) & ADC_ETC_CTRL_EXT0_TRIG_ENABLE_MASK) +#define ADC_ETC_CTRL_EXT0_TRIG_PRIORITY_MASK (0xE00U) +#define ADC_ETC_CTRL_EXT0_TRIG_PRIORITY_SHIFT (9U) +#define ADC_ETC_CTRL_EXT0_TRIG_PRIORITY(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_CTRL_EXT0_TRIG_PRIORITY_SHIFT)) & ADC_ETC_CTRL_EXT0_TRIG_PRIORITY_MASK) +#define ADC_ETC_CTRL_EXT1_TRIG_ENABLE_MASK (0x1000U) +#define ADC_ETC_CTRL_EXT1_TRIG_ENABLE_SHIFT (12U) +#define ADC_ETC_CTRL_EXT1_TRIG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_CTRL_EXT1_TRIG_ENABLE_SHIFT)) & ADC_ETC_CTRL_EXT1_TRIG_ENABLE_MASK) +#define ADC_ETC_CTRL_EXT1_TRIG_PRIORITY_MASK (0xE000U) +#define ADC_ETC_CTRL_EXT1_TRIG_PRIORITY_SHIFT (13U) +#define ADC_ETC_CTRL_EXT1_TRIG_PRIORITY(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_CTRL_EXT1_TRIG_PRIORITY_SHIFT)) & ADC_ETC_CTRL_EXT1_TRIG_PRIORITY_MASK) +#define ADC_ETC_CTRL_PRE_DIVIDER_MASK (0xFF0000U) +#define ADC_ETC_CTRL_PRE_DIVIDER_SHIFT (16U) +#define ADC_ETC_CTRL_PRE_DIVIDER(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_CTRL_PRE_DIVIDER_SHIFT)) & ADC_ETC_CTRL_PRE_DIVIDER_MASK) +#define ADC_ETC_CTRL_DMA_MODE_SEL_MASK (0x20000000U) +#define ADC_ETC_CTRL_DMA_MODE_SEL_SHIFT (29U) +#define ADC_ETC_CTRL_DMA_MODE_SEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_CTRL_DMA_MODE_SEL_SHIFT)) & ADC_ETC_CTRL_DMA_MODE_SEL_MASK) +#define ADC_ETC_CTRL_TSC_BYPASS_MASK (0x40000000U) +#define ADC_ETC_CTRL_TSC_BYPASS_SHIFT (30U) +#define ADC_ETC_CTRL_TSC_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_CTRL_TSC_BYPASS_SHIFT)) & ADC_ETC_CTRL_TSC_BYPASS_MASK) +#define ADC_ETC_CTRL_SOFTRST_MASK (0x80000000U) +#define ADC_ETC_CTRL_SOFTRST_SHIFT (31U) +#define ADC_ETC_CTRL_SOFTRST(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_CTRL_SOFTRST_SHIFT)) & ADC_ETC_CTRL_SOFTRST_MASK) +/*! @} */ + +/*! @name DONE0_1_IRQ - ETC DONE0 and DONE1 IRQ State Register */ +/*! @{ */ +#define ADC_ETC_DONE0_1_IRQ_TRIG0_DONE0_MASK (0x1U) +#define ADC_ETC_DONE0_1_IRQ_TRIG0_DONE0_SHIFT (0U) +#define ADC_ETC_DONE0_1_IRQ_TRIG0_DONE0(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG0_DONE0_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG0_DONE0_MASK) +#define ADC_ETC_DONE0_1_IRQ_TRIG1_DONE0_MASK (0x2U) +#define ADC_ETC_DONE0_1_IRQ_TRIG1_DONE0_SHIFT (1U) +#define ADC_ETC_DONE0_1_IRQ_TRIG1_DONE0(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG1_DONE0_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG1_DONE0_MASK) +#define ADC_ETC_DONE0_1_IRQ_TRIG2_DONE0_MASK (0x4U) +#define ADC_ETC_DONE0_1_IRQ_TRIG2_DONE0_SHIFT (2U) +#define ADC_ETC_DONE0_1_IRQ_TRIG2_DONE0(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG2_DONE0_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG2_DONE0_MASK) +#define ADC_ETC_DONE0_1_IRQ_TRIG3_DONE0_MASK (0x8U) +#define ADC_ETC_DONE0_1_IRQ_TRIG3_DONE0_SHIFT (3U) +#define ADC_ETC_DONE0_1_IRQ_TRIG3_DONE0(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG3_DONE0_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG3_DONE0_MASK) +#define ADC_ETC_DONE0_1_IRQ_TRIG4_DONE0_MASK (0x10U) +#define ADC_ETC_DONE0_1_IRQ_TRIG4_DONE0_SHIFT (4U) +#define ADC_ETC_DONE0_1_IRQ_TRIG4_DONE0(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG4_DONE0_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG4_DONE0_MASK) +#define ADC_ETC_DONE0_1_IRQ_TRIG5_DONE0_MASK (0x20U) +#define ADC_ETC_DONE0_1_IRQ_TRIG5_DONE0_SHIFT (5U) +#define ADC_ETC_DONE0_1_IRQ_TRIG5_DONE0(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG5_DONE0_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG5_DONE0_MASK) +#define ADC_ETC_DONE0_1_IRQ_TRIG6_DONE0_MASK (0x40U) +#define ADC_ETC_DONE0_1_IRQ_TRIG6_DONE0_SHIFT (6U) +#define ADC_ETC_DONE0_1_IRQ_TRIG6_DONE0(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG6_DONE0_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG6_DONE0_MASK) +#define ADC_ETC_DONE0_1_IRQ_TRIG7_DONE0_MASK (0x80U) +#define ADC_ETC_DONE0_1_IRQ_TRIG7_DONE0_SHIFT (7U) +#define ADC_ETC_DONE0_1_IRQ_TRIG7_DONE0(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG7_DONE0_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG7_DONE0_MASK) +#define ADC_ETC_DONE0_1_IRQ_TRIG0_DONE1_MASK (0x10000U) +#define ADC_ETC_DONE0_1_IRQ_TRIG0_DONE1_SHIFT (16U) +#define ADC_ETC_DONE0_1_IRQ_TRIG0_DONE1(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG0_DONE1_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG0_DONE1_MASK) +#define ADC_ETC_DONE0_1_IRQ_TRIG1_DONE1_MASK (0x20000U) +#define ADC_ETC_DONE0_1_IRQ_TRIG1_DONE1_SHIFT (17U) +#define ADC_ETC_DONE0_1_IRQ_TRIG1_DONE1(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG1_DONE1_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG1_DONE1_MASK) +#define ADC_ETC_DONE0_1_IRQ_TRIG2_DONE1_MASK (0x40000U) +#define ADC_ETC_DONE0_1_IRQ_TRIG2_DONE1_SHIFT (18U) +#define ADC_ETC_DONE0_1_IRQ_TRIG2_DONE1(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG2_DONE1_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG2_DONE1_MASK) +#define ADC_ETC_DONE0_1_IRQ_TRIG3_DONE1_MASK (0x80000U) +#define ADC_ETC_DONE0_1_IRQ_TRIG3_DONE1_SHIFT (19U) +#define ADC_ETC_DONE0_1_IRQ_TRIG3_DONE1(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG3_DONE1_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG3_DONE1_MASK) +#define ADC_ETC_DONE0_1_IRQ_TRIG4_DONE1_MASK (0x100000U) +#define ADC_ETC_DONE0_1_IRQ_TRIG4_DONE1_SHIFT (20U) +#define ADC_ETC_DONE0_1_IRQ_TRIG4_DONE1(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG4_DONE1_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG4_DONE1_MASK) +#define ADC_ETC_DONE0_1_IRQ_TRIG5_DONE1_MASK (0x200000U) +#define ADC_ETC_DONE0_1_IRQ_TRIG5_DONE1_SHIFT (21U) +#define ADC_ETC_DONE0_1_IRQ_TRIG5_DONE1(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG5_DONE1_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG5_DONE1_MASK) +#define ADC_ETC_DONE0_1_IRQ_TRIG6_DONE1_MASK (0x400000U) +#define ADC_ETC_DONE0_1_IRQ_TRIG6_DONE1_SHIFT (22U) +#define ADC_ETC_DONE0_1_IRQ_TRIG6_DONE1(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG6_DONE1_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG6_DONE1_MASK) +#define ADC_ETC_DONE0_1_IRQ_TRIG7_DONE1_MASK (0x800000U) +#define ADC_ETC_DONE0_1_IRQ_TRIG7_DONE1_SHIFT (23U) +#define ADC_ETC_DONE0_1_IRQ_TRIG7_DONE1(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG7_DONE1_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG7_DONE1_MASK) +/*! @} */ + +/*! @name DONE2_ERR_IRQ - ETC DONE_2 and DONE_ERR IRQ State Register */ +/*! @{ */ +#define ADC_ETC_DONE2_ERR_IRQ_TRIG0_DONE2_MASK (0x1U) +#define ADC_ETC_DONE2_ERR_IRQ_TRIG0_DONE2_SHIFT (0U) +#define ADC_ETC_DONE2_ERR_IRQ_TRIG0_DONE2(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_ERR_IRQ_TRIG0_DONE2_SHIFT)) & ADC_ETC_DONE2_ERR_IRQ_TRIG0_DONE2_MASK) +#define ADC_ETC_DONE2_ERR_IRQ_TRIG1_DONE2_MASK (0x2U) +#define ADC_ETC_DONE2_ERR_IRQ_TRIG1_DONE2_SHIFT (1U) +#define ADC_ETC_DONE2_ERR_IRQ_TRIG1_DONE2(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_ERR_IRQ_TRIG1_DONE2_SHIFT)) & ADC_ETC_DONE2_ERR_IRQ_TRIG1_DONE2_MASK) +#define ADC_ETC_DONE2_ERR_IRQ_TRIG2_DONE2_MASK (0x4U) +#define ADC_ETC_DONE2_ERR_IRQ_TRIG2_DONE2_SHIFT (2U) +#define ADC_ETC_DONE2_ERR_IRQ_TRIG2_DONE2(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_ERR_IRQ_TRIG2_DONE2_SHIFT)) & ADC_ETC_DONE2_ERR_IRQ_TRIG2_DONE2_MASK) +#define ADC_ETC_DONE2_ERR_IRQ_TRIG3_DONE2_MASK (0x8U) +#define ADC_ETC_DONE2_ERR_IRQ_TRIG3_DONE2_SHIFT (3U) +#define ADC_ETC_DONE2_ERR_IRQ_TRIG3_DONE2(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_ERR_IRQ_TRIG3_DONE2_SHIFT)) & ADC_ETC_DONE2_ERR_IRQ_TRIG3_DONE2_MASK) +#define ADC_ETC_DONE2_ERR_IRQ_TRIG4_DONE2_MASK (0x10U) +#define ADC_ETC_DONE2_ERR_IRQ_TRIG4_DONE2_SHIFT (4U) +#define ADC_ETC_DONE2_ERR_IRQ_TRIG4_DONE2(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_ERR_IRQ_TRIG4_DONE2_SHIFT)) & ADC_ETC_DONE2_ERR_IRQ_TRIG4_DONE2_MASK) +#define ADC_ETC_DONE2_ERR_IRQ_TRIG5_DONE2_MASK (0x20U) +#define ADC_ETC_DONE2_ERR_IRQ_TRIG5_DONE2_SHIFT (5U) +#define ADC_ETC_DONE2_ERR_IRQ_TRIG5_DONE2(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_ERR_IRQ_TRIG5_DONE2_SHIFT)) & ADC_ETC_DONE2_ERR_IRQ_TRIG5_DONE2_MASK) +#define ADC_ETC_DONE2_ERR_IRQ_TRIG6_DONE2_MASK (0x40U) +#define ADC_ETC_DONE2_ERR_IRQ_TRIG6_DONE2_SHIFT (6U) +#define ADC_ETC_DONE2_ERR_IRQ_TRIG6_DONE2(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_ERR_IRQ_TRIG6_DONE2_SHIFT)) & ADC_ETC_DONE2_ERR_IRQ_TRIG6_DONE2_MASK) +#define ADC_ETC_DONE2_ERR_IRQ_TRIG7_DONE2_MASK (0x80U) +#define ADC_ETC_DONE2_ERR_IRQ_TRIG7_DONE2_SHIFT (7U) +#define ADC_ETC_DONE2_ERR_IRQ_TRIG7_DONE2(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_ERR_IRQ_TRIG7_DONE2_SHIFT)) & ADC_ETC_DONE2_ERR_IRQ_TRIG7_DONE2_MASK) +#define ADC_ETC_DONE2_ERR_IRQ_TRIG0_ERR_MASK (0x10000U) +#define ADC_ETC_DONE2_ERR_IRQ_TRIG0_ERR_SHIFT (16U) +#define ADC_ETC_DONE2_ERR_IRQ_TRIG0_ERR(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_ERR_IRQ_TRIG0_ERR_SHIFT)) & ADC_ETC_DONE2_ERR_IRQ_TRIG0_ERR_MASK) +#define ADC_ETC_DONE2_ERR_IRQ_TRIG1_ERR_MASK (0x20000U) +#define ADC_ETC_DONE2_ERR_IRQ_TRIG1_ERR_SHIFT (17U) +#define ADC_ETC_DONE2_ERR_IRQ_TRIG1_ERR(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_ERR_IRQ_TRIG1_ERR_SHIFT)) & ADC_ETC_DONE2_ERR_IRQ_TRIG1_ERR_MASK) +#define ADC_ETC_DONE2_ERR_IRQ_TRIG2_ERR_MASK (0x40000U) +#define ADC_ETC_DONE2_ERR_IRQ_TRIG2_ERR_SHIFT (18U) +#define ADC_ETC_DONE2_ERR_IRQ_TRIG2_ERR(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_ERR_IRQ_TRIG2_ERR_SHIFT)) & ADC_ETC_DONE2_ERR_IRQ_TRIG2_ERR_MASK) +#define ADC_ETC_DONE2_ERR_IRQ_TRIG3_ERR_MASK (0x80000U) +#define ADC_ETC_DONE2_ERR_IRQ_TRIG3_ERR_SHIFT (19U) +#define ADC_ETC_DONE2_ERR_IRQ_TRIG3_ERR(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_ERR_IRQ_TRIG3_ERR_SHIFT)) & ADC_ETC_DONE2_ERR_IRQ_TRIG3_ERR_MASK) +#define ADC_ETC_DONE2_ERR_IRQ_TRIG4_ERR_MASK (0x100000U) +#define ADC_ETC_DONE2_ERR_IRQ_TRIG4_ERR_SHIFT (20U) +#define ADC_ETC_DONE2_ERR_IRQ_TRIG4_ERR(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_ERR_IRQ_TRIG4_ERR_SHIFT)) & ADC_ETC_DONE2_ERR_IRQ_TRIG4_ERR_MASK) +#define ADC_ETC_DONE2_ERR_IRQ_TRIG5_ERR_MASK (0x200000U) +#define ADC_ETC_DONE2_ERR_IRQ_TRIG5_ERR_SHIFT (21U) +#define ADC_ETC_DONE2_ERR_IRQ_TRIG5_ERR(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_ERR_IRQ_TRIG5_ERR_SHIFT)) & ADC_ETC_DONE2_ERR_IRQ_TRIG5_ERR_MASK) +#define ADC_ETC_DONE2_ERR_IRQ_TRIG6_ERR_MASK (0x400000U) +#define ADC_ETC_DONE2_ERR_IRQ_TRIG6_ERR_SHIFT (22U) +#define ADC_ETC_DONE2_ERR_IRQ_TRIG6_ERR(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_ERR_IRQ_TRIG6_ERR_SHIFT)) & ADC_ETC_DONE2_ERR_IRQ_TRIG6_ERR_MASK) +#define ADC_ETC_DONE2_ERR_IRQ_TRIG7_ERR_MASK (0x800000U) +#define ADC_ETC_DONE2_ERR_IRQ_TRIG7_ERR_SHIFT (23U) +#define ADC_ETC_DONE2_ERR_IRQ_TRIG7_ERR(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_ERR_IRQ_TRIG7_ERR_SHIFT)) & ADC_ETC_DONE2_ERR_IRQ_TRIG7_ERR_MASK) +/*! @} */ + +/*! @name DMA_CTRL - ETC DMA control Register */ +/*! @{ */ +#define ADC_ETC_DMA_CTRL_TRIG0_ENABLE_MASK (0x1U) +#define ADC_ETC_DMA_CTRL_TRIG0_ENABLE_SHIFT (0U) +#define ADC_ETC_DMA_CTRL_TRIG0_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG0_ENABLE_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG0_ENABLE_MASK) +#define ADC_ETC_DMA_CTRL_TRIG1_ENABLE_MASK (0x2U) +#define ADC_ETC_DMA_CTRL_TRIG1_ENABLE_SHIFT (1U) +#define ADC_ETC_DMA_CTRL_TRIG1_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG1_ENABLE_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG1_ENABLE_MASK) +#define ADC_ETC_DMA_CTRL_TRIG2_ENABLE_MASK (0x4U) +#define ADC_ETC_DMA_CTRL_TRIG2_ENABLE_SHIFT (2U) +#define ADC_ETC_DMA_CTRL_TRIG2_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG2_ENABLE_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG2_ENABLE_MASK) +#define ADC_ETC_DMA_CTRL_TRIG3_ENABLE_MASK (0x8U) +#define ADC_ETC_DMA_CTRL_TRIG3_ENABLE_SHIFT (3U) +#define ADC_ETC_DMA_CTRL_TRIG3_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG3_ENABLE_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG3_ENABLE_MASK) +#define ADC_ETC_DMA_CTRL_TRIG4_ENABLE_MASK (0x10U) +#define ADC_ETC_DMA_CTRL_TRIG4_ENABLE_SHIFT (4U) +#define ADC_ETC_DMA_CTRL_TRIG4_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG4_ENABLE_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG4_ENABLE_MASK) +#define ADC_ETC_DMA_CTRL_TRIG5_ENABLE_MASK (0x20U) +#define ADC_ETC_DMA_CTRL_TRIG5_ENABLE_SHIFT (5U) +#define ADC_ETC_DMA_CTRL_TRIG5_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG5_ENABLE_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG5_ENABLE_MASK) +#define ADC_ETC_DMA_CTRL_TRIG6_ENABLE_MASK (0x40U) +#define ADC_ETC_DMA_CTRL_TRIG6_ENABLE_SHIFT (6U) +#define ADC_ETC_DMA_CTRL_TRIG6_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG6_ENABLE_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG6_ENABLE_MASK) +#define ADC_ETC_DMA_CTRL_TRIG7_ENABLE_MASK (0x80U) +#define ADC_ETC_DMA_CTRL_TRIG7_ENABLE_SHIFT (7U) +#define ADC_ETC_DMA_CTRL_TRIG7_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG7_ENABLE_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG7_ENABLE_MASK) +#define ADC_ETC_DMA_CTRL_TRIG0_REQ_MASK (0x10000U) +#define ADC_ETC_DMA_CTRL_TRIG0_REQ_SHIFT (16U) +#define ADC_ETC_DMA_CTRL_TRIG0_REQ(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG0_REQ_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG0_REQ_MASK) +#define ADC_ETC_DMA_CTRL_TRIG1_REQ_MASK (0x20000U) +#define ADC_ETC_DMA_CTRL_TRIG1_REQ_SHIFT (17U) +#define ADC_ETC_DMA_CTRL_TRIG1_REQ(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG1_REQ_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG1_REQ_MASK) +#define ADC_ETC_DMA_CTRL_TRIG2_REQ_MASK (0x40000U) +#define ADC_ETC_DMA_CTRL_TRIG2_REQ_SHIFT (18U) +#define ADC_ETC_DMA_CTRL_TRIG2_REQ(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG2_REQ_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG2_REQ_MASK) +#define ADC_ETC_DMA_CTRL_TRIG3_REQ_MASK (0x80000U) +#define ADC_ETC_DMA_CTRL_TRIG3_REQ_SHIFT (19U) +#define ADC_ETC_DMA_CTRL_TRIG3_REQ(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG3_REQ_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG3_REQ_MASK) +#define ADC_ETC_DMA_CTRL_TRIG4_REQ_MASK (0x100000U) +#define ADC_ETC_DMA_CTRL_TRIG4_REQ_SHIFT (20U) +#define ADC_ETC_DMA_CTRL_TRIG4_REQ(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG4_REQ_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG4_REQ_MASK) +#define ADC_ETC_DMA_CTRL_TRIG5_REQ_MASK (0x200000U) +#define ADC_ETC_DMA_CTRL_TRIG5_REQ_SHIFT (21U) +#define ADC_ETC_DMA_CTRL_TRIG5_REQ(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG5_REQ_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG5_REQ_MASK) +#define ADC_ETC_DMA_CTRL_TRIG6_REQ_MASK (0x400000U) +#define ADC_ETC_DMA_CTRL_TRIG6_REQ_SHIFT (22U) +#define ADC_ETC_DMA_CTRL_TRIG6_REQ(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG6_REQ_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG6_REQ_MASK) +#define ADC_ETC_DMA_CTRL_TRIG7_REQ_MASK (0x800000U) +#define ADC_ETC_DMA_CTRL_TRIG7_REQ_SHIFT (23U) +#define ADC_ETC_DMA_CTRL_TRIG7_REQ(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG7_REQ_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG7_REQ_MASK) +/*! @} */ + +/*! @name TRIGn_CTRL - ETC_TRIG0 Control Register..ETC_TRIG7 Control Register */ +/*! @{ */ +#define ADC_ETC_TRIGn_CTRL_SW_TRIG_MASK (0x1U) +#define ADC_ETC_TRIGn_CTRL_SW_TRIG_SHIFT (0U) +#define ADC_ETC_TRIGn_CTRL_SW_TRIG(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CTRL_SW_TRIG_SHIFT)) & ADC_ETC_TRIGn_CTRL_SW_TRIG_MASK) +#define ADC_ETC_TRIGn_CTRL_TRIG_MODE_MASK (0x10U) +#define ADC_ETC_TRIGn_CTRL_TRIG_MODE_SHIFT (4U) +#define ADC_ETC_TRIGn_CTRL_TRIG_MODE(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CTRL_TRIG_MODE_SHIFT)) & ADC_ETC_TRIGn_CTRL_TRIG_MODE_MASK) +#define ADC_ETC_TRIGn_CTRL_TRIG_CHAIN_MASK (0x700U) +#define ADC_ETC_TRIGn_CTRL_TRIG_CHAIN_SHIFT (8U) +#define ADC_ETC_TRIGn_CTRL_TRIG_CHAIN(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CTRL_TRIG_CHAIN_SHIFT)) & ADC_ETC_TRIGn_CTRL_TRIG_CHAIN_MASK) +#define ADC_ETC_TRIGn_CTRL_TRIG_PRIORITY_MASK (0x7000U) +#define ADC_ETC_TRIGn_CTRL_TRIG_PRIORITY_SHIFT (12U) +#define ADC_ETC_TRIGn_CTRL_TRIG_PRIORITY(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CTRL_TRIG_PRIORITY_SHIFT)) & ADC_ETC_TRIGn_CTRL_TRIG_PRIORITY_MASK) +#define ADC_ETC_TRIGn_CTRL_SYNC_MODE_MASK (0x10000U) +#define ADC_ETC_TRIGn_CTRL_SYNC_MODE_SHIFT (16U) +#define ADC_ETC_TRIGn_CTRL_SYNC_MODE(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CTRL_SYNC_MODE_SHIFT)) & ADC_ETC_TRIGn_CTRL_SYNC_MODE_MASK) +/*! @} */ + +/* The count of ADC_ETC_TRIGn_CTRL */ +#define ADC_ETC_TRIGn_CTRL_COUNT (8U) + +/*! @name TRIGn_COUNTER - ETC_TRIG0 Counter Register..ETC_TRIG7 Counter Register */ +/*! @{ */ +#define ADC_ETC_TRIGn_COUNTER_INIT_DELAY_MASK (0xFFFFU) +#define ADC_ETC_TRIGn_COUNTER_INIT_DELAY_SHIFT (0U) +#define ADC_ETC_TRIGn_COUNTER_INIT_DELAY(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_COUNTER_INIT_DELAY_SHIFT)) & ADC_ETC_TRIGn_COUNTER_INIT_DELAY_MASK) +#define ADC_ETC_TRIGn_COUNTER_SAMPLE_INTERVAL_MASK (0xFFFF0000U) +#define ADC_ETC_TRIGn_COUNTER_SAMPLE_INTERVAL_SHIFT (16U) +#define ADC_ETC_TRIGn_COUNTER_SAMPLE_INTERVAL(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_COUNTER_SAMPLE_INTERVAL_SHIFT)) & ADC_ETC_TRIGn_COUNTER_SAMPLE_INTERVAL_MASK) +/*! @} */ + +/* The count of ADC_ETC_TRIGn_COUNTER */ +#define ADC_ETC_TRIGn_COUNTER_COUNT (8U) + +/*! @name TRIGn_CHAIN_1_0 - ETC_TRIG Chain 0/1 Register */ +/*! @{ */ +#define ADC_ETC_TRIGn_CHAIN_1_0_CSEL0_MASK (0xFU) +#define ADC_ETC_TRIGn_CHAIN_1_0_CSEL0_SHIFT (0U) +#define ADC_ETC_TRIGn_CHAIN_1_0_CSEL0(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_1_0_CSEL0_SHIFT)) & ADC_ETC_TRIGn_CHAIN_1_0_CSEL0_MASK) +#define ADC_ETC_TRIGn_CHAIN_1_0_HWTS0_MASK (0xFF0U) +#define ADC_ETC_TRIGn_CHAIN_1_0_HWTS0_SHIFT (4U) +#define ADC_ETC_TRIGn_CHAIN_1_0_HWTS0(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_1_0_HWTS0_SHIFT)) & ADC_ETC_TRIGn_CHAIN_1_0_HWTS0_MASK) +#define ADC_ETC_TRIGn_CHAIN_1_0_B2B0_MASK (0x1000U) +#define ADC_ETC_TRIGn_CHAIN_1_0_B2B0_SHIFT (12U) +#define ADC_ETC_TRIGn_CHAIN_1_0_B2B0(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_1_0_B2B0_SHIFT)) & ADC_ETC_TRIGn_CHAIN_1_0_B2B0_MASK) +#define ADC_ETC_TRIGn_CHAIN_1_0_IE0_MASK (0x6000U) +#define ADC_ETC_TRIGn_CHAIN_1_0_IE0_SHIFT (13U) +#define ADC_ETC_TRIGn_CHAIN_1_0_IE0(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_1_0_IE0_SHIFT)) & ADC_ETC_TRIGn_CHAIN_1_0_IE0_MASK) +#define ADC_ETC_TRIGn_CHAIN_1_0_CSEL1_MASK (0xF0000U) +#define ADC_ETC_TRIGn_CHAIN_1_0_CSEL1_SHIFT (16U) +#define ADC_ETC_TRIGn_CHAIN_1_0_CSEL1(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_1_0_CSEL1_SHIFT)) & ADC_ETC_TRIGn_CHAIN_1_0_CSEL1_MASK) +#define ADC_ETC_TRIGn_CHAIN_1_0_HWTS1_MASK (0xFF00000U) +#define ADC_ETC_TRIGn_CHAIN_1_0_HWTS1_SHIFT (20U) +#define ADC_ETC_TRIGn_CHAIN_1_0_HWTS1(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_1_0_HWTS1_SHIFT)) & ADC_ETC_TRIGn_CHAIN_1_0_HWTS1_MASK) +#define ADC_ETC_TRIGn_CHAIN_1_0_B2B1_MASK (0x10000000U) +#define ADC_ETC_TRIGn_CHAIN_1_0_B2B1_SHIFT (28U) +#define ADC_ETC_TRIGn_CHAIN_1_0_B2B1(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_1_0_B2B1_SHIFT)) & ADC_ETC_TRIGn_CHAIN_1_0_B2B1_MASK) +#define ADC_ETC_TRIGn_CHAIN_1_0_IE1_MASK (0x60000000U) +#define ADC_ETC_TRIGn_CHAIN_1_0_IE1_SHIFT (29U) +#define ADC_ETC_TRIGn_CHAIN_1_0_IE1(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_1_0_IE1_SHIFT)) & ADC_ETC_TRIGn_CHAIN_1_0_IE1_MASK) +/*! @} */ + +/* The count of ADC_ETC_TRIGn_CHAIN_1_0 */ +#define ADC_ETC_TRIGn_CHAIN_1_0_COUNT (8U) + +/*! @name TRIGn_CHAIN_3_2 - ETC_TRIG Chain 2/3 Register */ +/*! @{ */ +#define ADC_ETC_TRIGn_CHAIN_3_2_CSEL2_MASK (0xFU) +#define ADC_ETC_TRIGn_CHAIN_3_2_CSEL2_SHIFT (0U) +#define ADC_ETC_TRIGn_CHAIN_3_2_CSEL2(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_3_2_CSEL2_SHIFT)) & ADC_ETC_TRIGn_CHAIN_3_2_CSEL2_MASK) +#define ADC_ETC_TRIGn_CHAIN_3_2_HWTS2_MASK (0xFF0U) +#define ADC_ETC_TRIGn_CHAIN_3_2_HWTS2_SHIFT (4U) +#define ADC_ETC_TRIGn_CHAIN_3_2_HWTS2(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_3_2_HWTS2_SHIFT)) & ADC_ETC_TRIGn_CHAIN_3_2_HWTS2_MASK) +#define ADC_ETC_TRIGn_CHAIN_3_2_B2B2_MASK (0x1000U) +#define ADC_ETC_TRIGn_CHAIN_3_2_B2B2_SHIFT (12U) +#define ADC_ETC_TRIGn_CHAIN_3_2_B2B2(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_3_2_B2B2_SHIFT)) & ADC_ETC_TRIGn_CHAIN_3_2_B2B2_MASK) +#define ADC_ETC_TRIGn_CHAIN_3_2_IE2_MASK (0x6000U) +#define ADC_ETC_TRIGn_CHAIN_3_2_IE2_SHIFT (13U) +#define ADC_ETC_TRIGn_CHAIN_3_2_IE2(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_3_2_IE2_SHIFT)) & ADC_ETC_TRIGn_CHAIN_3_2_IE2_MASK) +#define ADC_ETC_TRIGn_CHAIN_3_2_CSEL3_MASK (0xF0000U) +#define ADC_ETC_TRIGn_CHAIN_3_2_CSEL3_SHIFT (16U) +#define ADC_ETC_TRIGn_CHAIN_3_2_CSEL3(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_3_2_CSEL3_SHIFT)) & ADC_ETC_TRIGn_CHAIN_3_2_CSEL3_MASK) +#define ADC_ETC_TRIGn_CHAIN_3_2_HWTS3_MASK (0xFF00000U) +#define ADC_ETC_TRIGn_CHAIN_3_2_HWTS3_SHIFT (20U) +#define ADC_ETC_TRIGn_CHAIN_3_2_HWTS3(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_3_2_HWTS3_SHIFT)) & ADC_ETC_TRIGn_CHAIN_3_2_HWTS3_MASK) +#define ADC_ETC_TRIGn_CHAIN_3_2_B2B3_MASK (0x10000000U) +#define ADC_ETC_TRIGn_CHAIN_3_2_B2B3_SHIFT (28U) +#define ADC_ETC_TRIGn_CHAIN_3_2_B2B3(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_3_2_B2B3_SHIFT)) & ADC_ETC_TRIGn_CHAIN_3_2_B2B3_MASK) +#define ADC_ETC_TRIGn_CHAIN_3_2_IE3_MASK (0x60000000U) +#define ADC_ETC_TRIGn_CHAIN_3_2_IE3_SHIFT (29U) +#define ADC_ETC_TRIGn_CHAIN_3_2_IE3(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_3_2_IE3_SHIFT)) & ADC_ETC_TRIGn_CHAIN_3_2_IE3_MASK) +/*! @} */ + +/* The count of ADC_ETC_TRIGn_CHAIN_3_2 */ +#define ADC_ETC_TRIGn_CHAIN_3_2_COUNT (8U) + +/*! @name TRIGn_CHAIN_5_4 - ETC_TRIG Chain 4/5 Register */ +/*! @{ */ +#define ADC_ETC_TRIGn_CHAIN_5_4_CSEL4_MASK (0xFU) +#define ADC_ETC_TRIGn_CHAIN_5_4_CSEL4_SHIFT (0U) +#define ADC_ETC_TRIGn_CHAIN_5_4_CSEL4(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_5_4_CSEL4_SHIFT)) & ADC_ETC_TRIGn_CHAIN_5_4_CSEL4_MASK) +#define ADC_ETC_TRIGn_CHAIN_5_4_HWTS4_MASK (0xFF0U) +#define ADC_ETC_TRIGn_CHAIN_5_4_HWTS4_SHIFT (4U) +#define ADC_ETC_TRIGn_CHAIN_5_4_HWTS4(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_5_4_HWTS4_SHIFT)) & ADC_ETC_TRIGn_CHAIN_5_4_HWTS4_MASK) +#define ADC_ETC_TRIGn_CHAIN_5_4_B2B4_MASK (0x1000U) +#define ADC_ETC_TRIGn_CHAIN_5_4_B2B4_SHIFT (12U) +#define ADC_ETC_TRIGn_CHAIN_5_4_B2B4(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_5_4_B2B4_SHIFT)) & ADC_ETC_TRIGn_CHAIN_5_4_B2B4_MASK) +#define ADC_ETC_TRIGn_CHAIN_5_4_IE4_MASK (0x6000U) +#define ADC_ETC_TRIGn_CHAIN_5_4_IE4_SHIFT (13U) +#define ADC_ETC_TRIGn_CHAIN_5_4_IE4(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_5_4_IE4_SHIFT)) & ADC_ETC_TRIGn_CHAIN_5_4_IE4_MASK) +#define ADC_ETC_TRIGn_CHAIN_5_4_CSEL5_MASK (0xF0000U) +#define ADC_ETC_TRIGn_CHAIN_5_4_CSEL5_SHIFT (16U) +#define ADC_ETC_TRIGn_CHAIN_5_4_CSEL5(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_5_4_CSEL5_SHIFT)) & ADC_ETC_TRIGn_CHAIN_5_4_CSEL5_MASK) +#define ADC_ETC_TRIGn_CHAIN_5_4_HWTS5_MASK (0xFF00000U) +#define ADC_ETC_TRIGn_CHAIN_5_4_HWTS5_SHIFT (20U) +#define ADC_ETC_TRIGn_CHAIN_5_4_HWTS5(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_5_4_HWTS5_SHIFT)) & ADC_ETC_TRIGn_CHAIN_5_4_HWTS5_MASK) +#define ADC_ETC_TRIGn_CHAIN_5_4_B2B5_MASK (0x10000000U) +#define ADC_ETC_TRIGn_CHAIN_5_4_B2B5_SHIFT (28U) +#define ADC_ETC_TRIGn_CHAIN_5_4_B2B5(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_5_4_B2B5_SHIFT)) & ADC_ETC_TRIGn_CHAIN_5_4_B2B5_MASK) +#define ADC_ETC_TRIGn_CHAIN_5_4_IE5_MASK (0x60000000U) +#define ADC_ETC_TRIGn_CHAIN_5_4_IE5_SHIFT (29U) +#define ADC_ETC_TRIGn_CHAIN_5_4_IE5(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_5_4_IE5_SHIFT)) & ADC_ETC_TRIGn_CHAIN_5_4_IE5_MASK) +/*! @} */ + +/* The count of ADC_ETC_TRIGn_CHAIN_5_4 */ +#define ADC_ETC_TRIGn_CHAIN_5_4_COUNT (8U) + +/*! @name TRIGn_CHAIN_7_6 - ETC_TRIG Chain 6/7 Register */ +/*! @{ */ +#define ADC_ETC_TRIGn_CHAIN_7_6_CSEL6_MASK (0xFU) +#define ADC_ETC_TRIGn_CHAIN_7_6_CSEL6_SHIFT (0U) +#define ADC_ETC_TRIGn_CHAIN_7_6_CSEL6(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_7_6_CSEL6_SHIFT)) & ADC_ETC_TRIGn_CHAIN_7_6_CSEL6_MASK) +#define ADC_ETC_TRIGn_CHAIN_7_6_HWTS6_MASK (0xFF0U) +#define ADC_ETC_TRIGn_CHAIN_7_6_HWTS6_SHIFT (4U) +#define ADC_ETC_TRIGn_CHAIN_7_6_HWTS6(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_7_6_HWTS6_SHIFT)) & ADC_ETC_TRIGn_CHAIN_7_6_HWTS6_MASK) +#define ADC_ETC_TRIGn_CHAIN_7_6_B2B6_MASK (0x1000U) +#define ADC_ETC_TRIGn_CHAIN_7_6_B2B6_SHIFT (12U) +#define ADC_ETC_TRIGn_CHAIN_7_6_B2B6(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_7_6_B2B6_SHIFT)) & ADC_ETC_TRIGn_CHAIN_7_6_B2B6_MASK) +#define ADC_ETC_TRIGn_CHAIN_7_6_IE6_MASK (0x6000U) +#define ADC_ETC_TRIGn_CHAIN_7_6_IE6_SHIFT (13U) +#define ADC_ETC_TRIGn_CHAIN_7_6_IE6(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_7_6_IE6_SHIFT)) & ADC_ETC_TRIGn_CHAIN_7_6_IE6_MASK) +#define ADC_ETC_TRIGn_CHAIN_7_6_CSEL7_MASK (0xF0000U) +#define ADC_ETC_TRIGn_CHAIN_7_6_CSEL7_SHIFT (16U) +#define ADC_ETC_TRIGn_CHAIN_7_6_CSEL7(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_7_6_CSEL7_SHIFT)) & ADC_ETC_TRIGn_CHAIN_7_6_CSEL7_MASK) +#define ADC_ETC_TRIGn_CHAIN_7_6_HWTS7_MASK (0xFF00000U) +#define ADC_ETC_TRIGn_CHAIN_7_6_HWTS7_SHIFT (20U) +#define ADC_ETC_TRIGn_CHAIN_7_6_HWTS7(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_7_6_HWTS7_SHIFT)) & ADC_ETC_TRIGn_CHAIN_7_6_HWTS7_MASK) +#define ADC_ETC_TRIGn_CHAIN_7_6_B2B7_MASK (0x10000000U) +#define ADC_ETC_TRIGn_CHAIN_7_6_B2B7_SHIFT (28U) +#define ADC_ETC_TRIGn_CHAIN_7_6_B2B7(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_7_6_B2B7_SHIFT)) & ADC_ETC_TRIGn_CHAIN_7_6_B2B7_MASK) +#define ADC_ETC_TRIGn_CHAIN_7_6_IE7_MASK (0x60000000U) +#define ADC_ETC_TRIGn_CHAIN_7_6_IE7_SHIFT (29U) +#define ADC_ETC_TRIGn_CHAIN_7_6_IE7(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_7_6_IE7_SHIFT)) & ADC_ETC_TRIGn_CHAIN_7_6_IE7_MASK) +/*! @} */ + +/* The count of ADC_ETC_TRIGn_CHAIN_7_6 */ +#define ADC_ETC_TRIGn_CHAIN_7_6_COUNT (8U) + +/*! @name TRIGn_RESULT_1_0 - ETC_TRIG Result Data 1/0 Register */ +/*! @{ */ +#define ADC_ETC_TRIGn_RESULT_1_0_DATA0_MASK (0xFFFU) +#define ADC_ETC_TRIGn_RESULT_1_0_DATA0_SHIFT (0U) +#define ADC_ETC_TRIGn_RESULT_1_0_DATA0(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_RESULT_1_0_DATA0_SHIFT)) & ADC_ETC_TRIGn_RESULT_1_0_DATA0_MASK) +#define ADC_ETC_TRIGn_RESULT_1_0_DATA1_MASK (0xFFF0000U) +#define ADC_ETC_TRIGn_RESULT_1_0_DATA1_SHIFT (16U) +#define ADC_ETC_TRIGn_RESULT_1_0_DATA1(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_RESULT_1_0_DATA1_SHIFT)) & ADC_ETC_TRIGn_RESULT_1_0_DATA1_MASK) +/*! @} */ + +/* The count of ADC_ETC_TRIGn_RESULT_1_0 */ +#define ADC_ETC_TRIGn_RESULT_1_0_COUNT (8U) + +/*! @name TRIGn_RESULT_3_2 - ETC_TRIG Result Data 3/2 Register */ +/*! @{ */ +#define ADC_ETC_TRIGn_RESULT_3_2_DATA2_MASK (0xFFFU) +#define ADC_ETC_TRIGn_RESULT_3_2_DATA2_SHIFT (0U) +#define ADC_ETC_TRIGn_RESULT_3_2_DATA2(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_RESULT_3_2_DATA2_SHIFT)) & ADC_ETC_TRIGn_RESULT_3_2_DATA2_MASK) +#define ADC_ETC_TRIGn_RESULT_3_2_DATA3_MASK (0xFFF0000U) +#define ADC_ETC_TRIGn_RESULT_3_2_DATA3_SHIFT (16U) +#define ADC_ETC_TRIGn_RESULT_3_2_DATA3(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_RESULT_3_2_DATA3_SHIFT)) & ADC_ETC_TRIGn_RESULT_3_2_DATA3_MASK) +/*! @} */ + +/* The count of ADC_ETC_TRIGn_RESULT_3_2 */ +#define ADC_ETC_TRIGn_RESULT_3_2_COUNT (8U) + +/*! @name TRIGn_RESULT_5_4 - ETC_TRIG Result Data 5/4 Register */ +/*! @{ */ +#define ADC_ETC_TRIGn_RESULT_5_4_DATA4_MASK (0xFFFU) +#define ADC_ETC_TRIGn_RESULT_5_4_DATA4_SHIFT (0U) +#define ADC_ETC_TRIGn_RESULT_5_4_DATA4(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_RESULT_5_4_DATA4_SHIFT)) & ADC_ETC_TRIGn_RESULT_5_4_DATA4_MASK) +#define ADC_ETC_TRIGn_RESULT_5_4_DATA5_MASK (0xFFF0000U) +#define ADC_ETC_TRIGn_RESULT_5_4_DATA5_SHIFT (16U) +#define ADC_ETC_TRIGn_RESULT_5_4_DATA5(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_RESULT_5_4_DATA5_SHIFT)) & ADC_ETC_TRIGn_RESULT_5_4_DATA5_MASK) +/*! @} */ + +/* The count of ADC_ETC_TRIGn_RESULT_5_4 */ +#define ADC_ETC_TRIGn_RESULT_5_4_COUNT (8U) + +/*! @name TRIGn_RESULT_7_6 - ETC_TRIG Result Data 7/6 Register */ +/*! @{ */ +#define ADC_ETC_TRIGn_RESULT_7_6_DATA6_MASK (0xFFFU) +#define ADC_ETC_TRIGn_RESULT_7_6_DATA6_SHIFT (0U) +#define ADC_ETC_TRIGn_RESULT_7_6_DATA6(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_RESULT_7_6_DATA6_SHIFT)) & ADC_ETC_TRIGn_RESULT_7_6_DATA6_MASK) +#define ADC_ETC_TRIGn_RESULT_7_6_DATA7_MASK (0xFFF0000U) +#define ADC_ETC_TRIGn_RESULT_7_6_DATA7_SHIFT (16U) +#define ADC_ETC_TRIGn_RESULT_7_6_DATA7(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_RESULT_7_6_DATA7_SHIFT)) & ADC_ETC_TRIGn_RESULT_7_6_DATA7_MASK) +/*! @} */ + +/* The count of ADC_ETC_TRIGn_RESULT_7_6 */ +#define ADC_ETC_TRIGn_RESULT_7_6_COUNT (8U) + + +/*! + * @} + */ /* end of group ADC_ETC_Register_Masks */ + + +/* ADC_ETC - Peripheral instance base addresses */ +/** Peripheral ADC_ETC base address */ +#define ADC_ETC_BASE (0x403B0000u) +/** Peripheral ADC_ETC base pointer */ +#define ADC_ETC ((ADC_ETC_Type *)ADC_ETC_BASE) +/** Array initializer of ADC_ETC peripheral base addresses */ +#define ADC_ETC_BASE_ADDRS { ADC_ETC_BASE } +/** Array initializer of ADC_ETC peripheral base pointers */ +#define ADC_ETC_BASE_PTRS { ADC_ETC } +/** Interrupt vectors for the ADC_ETC peripheral type */ +#define ADC_ETC_IRQS { { ADC_ETC_IRQ0_IRQn, ADC_ETC_IRQ1_IRQn, ADC_ETC_IRQ2_IRQn } } +#define ADC_ETC_FAULT_IRQS { ADC_ETC_ERROR_IRQ_IRQn } + +/*! + * @} + */ /* end of group ADC_ETC_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- AIPSTZ Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup AIPSTZ_Peripheral_Access_Layer AIPSTZ Peripheral Access Layer + * @{ + */ + +/** AIPSTZ - Register Layout Typedef */ +typedef struct { + __IO uint32_t MPR; /**< Master Priviledge Registers, offset: 0x0 */ + uint8_t RESERVED_0[60]; + __IO uint32_t OPACR; /**< Off-Platform Peripheral Access Control Registers, offset: 0x40 */ + __IO uint32_t OPACR1; /**< Off-Platform Peripheral Access Control Registers, offset: 0x44 */ + __IO uint32_t OPACR2; /**< Off-Platform Peripheral Access Control Registers, offset: 0x48 */ + __IO uint32_t OPACR3; /**< Off-Platform Peripheral Access Control Registers, offset: 0x4C */ + __IO uint32_t OPACR4; /**< Off-Platform Peripheral Access Control Registers, offset: 0x50 */ +} AIPSTZ_Type; + +/* ---------------------------------------------------------------------------- + -- AIPSTZ Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup AIPSTZ_Register_Masks AIPSTZ Register Masks + * @{ + */ + +/*! @name MPR - Master Priviledge Registers */ +/*! @{ */ +#define AIPSTZ_MPR_MPROT5_MASK (0xF00U) +#define AIPSTZ_MPR_MPROT5_SHIFT (8U) +/*! MPROT5 + * 0bxxx0..Accesses from this master are forced to user-mode (ips_supervisor_access is forced to zero) regardless of the hprot[1] access attribute. + * 0bxxx1..Accesses from this master are not forced to user-mode. The hprot[1] access attribute is used directly to determine ips_supervisor_access. + * 0bxx0x..This master is not trusted for write accesses. + * 0bxx1x..This master is trusted for write accesses. + * 0bx0xx..This master is not trusted for read accesses. + * 0bx1xx..This master is trusted for read accesses. + * 0b1xxx..Write accesses from this master are allowed to be buffered + */ +#define AIPSTZ_MPR_MPROT5(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_MPR_MPROT5_SHIFT)) & AIPSTZ_MPR_MPROT5_MASK) +#define AIPSTZ_MPR_MPROT3_MASK (0xF0000U) +#define AIPSTZ_MPR_MPROT3_SHIFT (16U) +/*! MPROT3 + * 0bxxx0..Accesses from this master are forced to user-mode (ips_supervisor_access is forced to zero) regardless of the hprot[1] access attribute. + * 0bxxx1..Accesses from this master are not forced to user-mode. The hprot[1] access attribute is used directly to determine ips_supervisor_access. + * 0bxx0x..This master is not trusted for write accesses. + * 0bxx1x..This master is trusted for write accesses. + * 0bx0xx..This master is not trusted for read accesses. + * 0bx1xx..This master is trusted for read accesses. + * 0b1xxx..Write accesses from this master are allowed to be buffered + */ +#define AIPSTZ_MPR_MPROT3(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_MPR_MPROT3_SHIFT)) & AIPSTZ_MPR_MPROT3_MASK) +#define AIPSTZ_MPR_MPROT2_MASK (0xF00000U) +#define AIPSTZ_MPR_MPROT2_SHIFT (20U) +/*! MPROT2 + * 0bxxx0..Accesses from this master are forced to user-mode (ips_supervisor_access is forced to zero) regardless of the hprot[1] access attribute. + * 0bxxx1..Accesses from this master are not forced to user-mode. The hprot[1] access attribute is used directly to determine ips_supervisor_access. + * 0bxx0x..This master is not trusted for write accesses. + * 0bxx1x..This master is trusted for write accesses. + * 0bx0xx..This master is not trusted for read accesses. + * 0bx1xx..This master is trusted for read accesses. + * 0b1xxx..Write accesses from this master are allowed to be buffered + */ +#define AIPSTZ_MPR_MPROT2(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_MPR_MPROT2_SHIFT)) & AIPSTZ_MPR_MPROT2_MASK) +#define AIPSTZ_MPR_MPROT1_MASK (0xF000000U) +#define AIPSTZ_MPR_MPROT1_SHIFT (24U) +/*! MPROT1 + * 0bxxx0..Accesses from this master are forced to user-mode (ips_supervisor_access is forced to zero) regardless of the hprot[1] access attribute. + * 0bxxx1..Accesses from this master are not forced to user-mode. The hprot[1] access attribute is used directly to determine ips_supervisor_access. + * 0bxx0x..This master is not trusted for write accesses. + * 0bxx1x..This master is trusted for write accesses. + * 0bx0xx..This master is not trusted for read accesses. + * 0bx1xx..This master is trusted for read accesses. + * 0b1xxx..Write accesses from this master are allowed to be buffered + */ +#define AIPSTZ_MPR_MPROT1(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_MPR_MPROT1_SHIFT)) & AIPSTZ_MPR_MPROT1_MASK) +#define AIPSTZ_MPR_MPROT0_MASK (0xF0000000U) +#define AIPSTZ_MPR_MPROT0_SHIFT (28U) +/*! MPROT0 + * 0bxxx0..Accesses from this master are forced to user-mode (ips_supervisor_access is forced to zero) regardless of the hprot[1] access attribute. + * 0bxxx1..Accesses from this master are not forced to user-mode. The hprot[1] access attribute is used directly to determine ips_supervisor_access. + * 0bxx0x..This master is not trusted for write accesses. + * 0bxx1x..This master is trusted for write accesses. + * 0bx0xx..This master is not trusted for read accesses. + * 0bx1xx..This master is trusted for read accesses. + * 0b1xxx..Write accesses from this master are allowed to be buffered + */ +#define AIPSTZ_MPR_MPROT0(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_MPR_MPROT0_SHIFT)) & AIPSTZ_MPR_MPROT0_MASK) +/*! @} */ + +/*! @name OPACR - Off-Platform Peripheral Access Control Registers */ +/*! @{ */ +#define AIPSTZ_OPACR_OPAC7_MASK (0xFU) +#define AIPSTZ_OPACR_OPAC7_SHIFT (0U) +/*! OPAC7 + * 0bxxx0..Accesses from an untrusted master are allowed. + * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + * 0bxx0x..This peripheral allows write accesses. + * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + * 0bx0xx..This peripheral does not require supervisor privilege level for accesses. + * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must be set. If not, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ. + */ +#define AIPSTZ_OPACR_OPAC7(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR_OPAC7_SHIFT)) & AIPSTZ_OPACR_OPAC7_MASK) +#define AIPSTZ_OPACR_OPAC6_MASK (0xF0U) +#define AIPSTZ_OPACR_OPAC6_SHIFT (4U) +/*! OPAC6 + * 0bxxx0..Accesses from an untrusted master are allowed. + * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + * 0bxx0x..This peripheral allows write accesses. + * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + * 0bx0xx..This peripheral does not require supervisor privilege level for accesses. + * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must be set. If not, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ. + */ +#define AIPSTZ_OPACR_OPAC6(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR_OPAC6_SHIFT)) & AIPSTZ_OPACR_OPAC6_MASK) +#define AIPSTZ_OPACR_OPAC5_MASK (0xF00U) +#define AIPSTZ_OPACR_OPAC5_SHIFT (8U) +/*! OPAC5 + * 0bxxx0..Accesses from an untrusted master are allowed. + * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + * 0bxx0x..This peripheral allows write accesses. + * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + * 0bx0xx..This peripheral does not require supervisor privilege level for accesses. + * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must be set. If not, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ. + */ +#define AIPSTZ_OPACR_OPAC5(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR_OPAC5_SHIFT)) & AIPSTZ_OPACR_OPAC5_MASK) +#define AIPSTZ_OPACR_OPAC4_MASK (0xF000U) +#define AIPSTZ_OPACR_OPAC4_SHIFT (12U) +/*! OPAC4 + * 0bxxx0..Accesses from an untrusted master are allowed. + * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + * 0bxx0x..This peripheral allows write accesses. + * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + * 0bx0xx..This peripheral does not require supervisor privilege level for accesses. + * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must be set. If not, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ. + */ +#define AIPSTZ_OPACR_OPAC4(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR_OPAC4_SHIFT)) & AIPSTZ_OPACR_OPAC4_MASK) +#define AIPSTZ_OPACR_OPAC3_MASK (0xF0000U) +#define AIPSTZ_OPACR_OPAC3_SHIFT (16U) +/*! OPAC3 + * 0bxxx0..Accesses from an untrusted master are allowed. + * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + * 0bxx0x..This peripheral allows write accesses. + * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + * 0bx0xx..This peripheral does not require supervisor privilege level for accesses. + * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must be set. If not, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ. + */ +#define AIPSTZ_OPACR_OPAC3(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR_OPAC3_SHIFT)) & AIPSTZ_OPACR_OPAC3_MASK) +#define AIPSTZ_OPACR_OPAC2_MASK (0xF00000U) +#define AIPSTZ_OPACR_OPAC2_SHIFT (20U) +/*! OPAC2 + * 0bxxx0..Accesses from an untrusted master are allowed. + * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + * 0bxx0x..This peripheral allows write accesses. + * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + * 0bx0xx..This peripheral does not require supervisor privilege level for accesses. + * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must be set. If not, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ. + */ +#define AIPSTZ_OPACR_OPAC2(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR_OPAC2_SHIFT)) & AIPSTZ_OPACR_OPAC2_MASK) +#define AIPSTZ_OPACR_OPAC1_MASK (0xF000000U) +#define AIPSTZ_OPACR_OPAC1_SHIFT (24U) +/*! OPAC1 + * 0bxxx0..Accesses from an untrusted master are allowed. + * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + * 0bxx0x..This peripheral allows write accesses. + * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + * 0bx0xx..This peripheral does not require supervisor privilege level for accesses. + * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must be set. If not, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ. + */ +#define AIPSTZ_OPACR_OPAC1(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR_OPAC1_SHIFT)) & AIPSTZ_OPACR_OPAC1_MASK) +#define AIPSTZ_OPACR_OPAC0_MASK (0xF0000000U) +#define AIPSTZ_OPACR_OPAC0_SHIFT (28U) +/*! OPAC0 + * 0bxxx0..Accesses from an untrusted master are allowed. + * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + * 0bxx0x..This peripheral allows write accesses. + * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + * 0bx0xx..This peripheral does not require supervisor privilege level for accesses. + * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must be set. If not, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ. + */ +#define AIPSTZ_OPACR_OPAC0(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR_OPAC0_SHIFT)) & AIPSTZ_OPACR_OPAC0_MASK) +/*! @} */ + +/*! @name OPACR1 - Off-Platform Peripheral Access Control Registers */ +/*! @{ */ +#define AIPSTZ_OPACR1_OPAC15_MASK (0xFU) +#define AIPSTZ_OPACR1_OPAC15_SHIFT (0U) +/*! OPAC15 + * 0bxxx0..Accesses from an untrusted master are allowed. + * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + * 0bxx0x..This peripheral allows write accesses. + * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + * 0bx0xx..This peripheral does not require supervisor privilege level for accesses. + * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must be set. If not, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ. + */ +#define AIPSTZ_OPACR1_OPAC15(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR1_OPAC15_SHIFT)) & AIPSTZ_OPACR1_OPAC15_MASK) +#define AIPSTZ_OPACR1_OPAC14_MASK (0xF0U) +#define AIPSTZ_OPACR1_OPAC14_SHIFT (4U) +/*! OPAC14 + * 0bxxx0..Accesses from an untrusted master are allowed. + * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + * 0bxx0x..This peripheral allows write accesses. + * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + * 0bx0xx..This peripheral does not require supervisor privilege level for accesses. + * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must be set. If not, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ. + */ +#define AIPSTZ_OPACR1_OPAC14(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR1_OPAC14_SHIFT)) & AIPSTZ_OPACR1_OPAC14_MASK) +#define AIPSTZ_OPACR1_OPAC13_MASK (0xF00U) +#define AIPSTZ_OPACR1_OPAC13_SHIFT (8U) +/*! OPAC13 + * 0bxxx0..Accesses from an untrusted master are allowed. + * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + * 0bxx0x..This peripheral allows write accesses. + * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + * 0bx0xx..This peripheral does not require supervisor privilege level for accesses. + * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must be set. If not, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ. + */ +#define AIPSTZ_OPACR1_OPAC13(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR1_OPAC13_SHIFT)) & AIPSTZ_OPACR1_OPAC13_MASK) +#define AIPSTZ_OPACR1_OPAC12_MASK (0xF000U) +#define AIPSTZ_OPACR1_OPAC12_SHIFT (12U) +/*! OPAC12 + * 0bxxx0..Accesses from an untrusted master are allowed. + * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + * 0bxx0x..This peripheral allows write accesses. + * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + * 0bx0xx..This peripheral does not require supervisor privilege level for accesses. + * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must be set. If not, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ. + */ +#define AIPSTZ_OPACR1_OPAC12(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR1_OPAC12_SHIFT)) & AIPSTZ_OPACR1_OPAC12_MASK) +#define AIPSTZ_OPACR1_OPAC11_MASK (0xF0000U) +#define AIPSTZ_OPACR1_OPAC11_SHIFT (16U) +/*! OPAC11 + * 0bxxx0..Accesses from an untrusted master are allowed. + * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + * 0bxx0x..This peripheral allows write accesses. + * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + * 0bx0xx..This peripheral does not require supervisor privilege level for accesses. + * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must be set. If not, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ. + */ +#define AIPSTZ_OPACR1_OPAC11(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR1_OPAC11_SHIFT)) & AIPSTZ_OPACR1_OPAC11_MASK) +#define AIPSTZ_OPACR1_OPAC10_MASK (0xF00000U) +#define AIPSTZ_OPACR1_OPAC10_SHIFT (20U) +/*! OPAC10 + * 0bxxx0..Accesses from an untrusted master are allowed. + * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + * 0bxx0x..This peripheral allows write accesses. + * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + * 0bx0xx..This peripheral does not require supervisor privilege level for accesses. + * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must be set. If not, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ. + */ +#define AIPSTZ_OPACR1_OPAC10(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR1_OPAC10_SHIFT)) & AIPSTZ_OPACR1_OPAC10_MASK) +#define AIPSTZ_OPACR1_OPAC9_MASK (0xF000000U) +#define AIPSTZ_OPACR1_OPAC9_SHIFT (24U) +/*! OPAC9 + * 0bxxx0..Accesses from an untrusted master are allowed. + * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + * 0bxx0x..This peripheral allows write accesses. + * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + * 0bx0xx..This peripheral does not require supervisor privilege level for accesses. + * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must be set. If not, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ. + */ +#define AIPSTZ_OPACR1_OPAC9(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR1_OPAC9_SHIFT)) & AIPSTZ_OPACR1_OPAC9_MASK) +#define AIPSTZ_OPACR1_OPAC8_MASK (0xF0000000U) +#define AIPSTZ_OPACR1_OPAC8_SHIFT (28U) +/*! OPAC8 + * 0bxxx0..Accesses from an untrusted master are allowed. + * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + * 0bxx0x..This peripheral allows write accesses. + * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + * 0bx0xx..This peripheral does not require supervisor privilege level for accesses. + * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must be set. If not, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ. + */ +#define AIPSTZ_OPACR1_OPAC8(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR1_OPAC8_SHIFT)) & AIPSTZ_OPACR1_OPAC8_MASK) +/*! @} */ + +/*! @name OPACR2 - Off-Platform Peripheral Access Control Registers */ +/*! @{ */ +#define AIPSTZ_OPACR2_OPAC23_MASK (0xFU) +#define AIPSTZ_OPACR2_OPAC23_SHIFT (0U) +/*! OPAC23 + * 0bxxx0..Accesses from an untrusted master are allowed. + * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + * 0bxx0x..This peripheral allows write accesses. + * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + * 0bx0xx..This peripheral does not require supervisor privilege level for accesses. + * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must be set. If not, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ. + */ +#define AIPSTZ_OPACR2_OPAC23(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR2_OPAC23_SHIFT)) & AIPSTZ_OPACR2_OPAC23_MASK) +#define AIPSTZ_OPACR2_OPAC22_MASK (0xF0U) +#define AIPSTZ_OPACR2_OPAC22_SHIFT (4U) +/*! OPAC22 + * 0bxxx0..Accesses from an untrusted master are allowed. + * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + * 0bxx0x..This peripheral allows write accesses. + * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + * 0bx0xx..This peripheral does not require supervisor privilege level for accesses. + * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must be set. If not, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ. + */ +#define AIPSTZ_OPACR2_OPAC22(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR2_OPAC22_SHIFT)) & AIPSTZ_OPACR2_OPAC22_MASK) +#define AIPSTZ_OPACR2_OPAC21_MASK (0xF00U) +#define AIPSTZ_OPACR2_OPAC21_SHIFT (8U) +/*! OPAC21 + * 0bxxx0..Accesses from an untrusted master are allowed. + * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + * 0bxx0x..This peripheral allows write accesses. + * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + * 0bx0xx..This peripheral does not require supervisor privilege level for accesses. + * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must be set. If not, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ. + */ +#define AIPSTZ_OPACR2_OPAC21(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR2_OPAC21_SHIFT)) & AIPSTZ_OPACR2_OPAC21_MASK) +#define AIPSTZ_OPACR2_OPAC20_MASK (0xF000U) +#define AIPSTZ_OPACR2_OPAC20_SHIFT (12U) +/*! OPAC20 + * 0bxxx0..Accesses from an untrusted master are allowed. + * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + * 0bxx0x..This peripheral allows write accesses. + * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + * 0bx0xx..This peripheral does not require supervisor privilege level for accesses. + * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must be set. If not, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ. + */ +#define AIPSTZ_OPACR2_OPAC20(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR2_OPAC20_SHIFT)) & AIPSTZ_OPACR2_OPAC20_MASK) +#define AIPSTZ_OPACR2_OPAC19_MASK (0xF0000U) +#define AIPSTZ_OPACR2_OPAC19_SHIFT (16U) +/*! OPAC19 + * 0bxxx0..Accesses from an untrusted master are allowed. + * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + * 0bxx0x..This peripheral allows write accesses. + * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + * 0bx0xx..This peripheral does not require supervisor privilege level for accesses. + * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must be set. If not, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ. + */ +#define AIPSTZ_OPACR2_OPAC19(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR2_OPAC19_SHIFT)) & AIPSTZ_OPACR2_OPAC19_MASK) +#define AIPSTZ_OPACR2_OPAC18_MASK (0xF00000U) +#define AIPSTZ_OPACR2_OPAC18_SHIFT (20U) +/*! OPAC18 + * 0bxxx0..Accesses from an untrusted master are allowed. + * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + * 0bxx0x..This peripheral allows write accesses. + * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + * 0bx0xx..This peripheral does not require supervisor privilege level for accesses. + * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must be set. If not, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ. + */ +#define AIPSTZ_OPACR2_OPAC18(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR2_OPAC18_SHIFT)) & AIPSTZ_OPACR2_OPAC18_MASK) +#define AIPSTZ_OPACR2_OPAC17_MASK (0xF000000U) +#define AIPSTZ_OPACR2_OPAC17_SHIFT (24U) +/*! OPAC17 + * 0bxxx0..Accesses from an untrusted master are allowed. + * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + * 0bxx0x..This peripheral allows write accesses. + * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + * 0bx0xx..This peripheral does not require supervisor privilege level for accesses. + * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must be set. If not, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ. + */ +#define AIPSTZ_OPACR2_OPAC17(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR2_OPAC17_SHIFT)) & AIPSTZ_OPACR2_OPAC17_MASK) +#define AIPSTZ_OPACR2_OPAC16_MASK (0xF0000000U) +#define AIPSTZ_OPACR2_OPAC16_SHIFT (28U) +/*! OPAC16 + * 0bxxx0..Accesses from an untrusted master are allowed. + * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + * 0bxx0x..This peripheral allows write accesses. + * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + * 0bx0xx..This peripheral does not require supervisor privilege level for accesses. + * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must be set. If not, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ. + */ +#define AIPSTZ_OPACR2_OPAC16(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR2_OPAC16_SHIFT)) & AIPSTZ_OPACR2_OPAC16_MASK) +/*! @} */ + +/*! @name OPACR3 - Off-Platform Peripheral Access Control Registers */ +/*! @{ */ +#define AIPSTZ_OPACR3_OPAC31_MASK (0xFU) +#define AIPSTZ_OPACR3_OPAC31_SHIFT (0U) +/*! OPAC31 + * 0bxxx0..Accesses from an untrusted master are allowed. + * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + * 0bxx0x..This peripheral allows write accesses. + * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + * 0bx0xx..This peripheral does not require supervisor privilege level for accesses. + * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must be set. If not, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ. + */ +#define AIPSTZ_OPACR3_OPAC31(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR3_OPAC31_SHIFT)) & AIPSTZ_OPACR3_OPAC31_MASK) +#define AIPSTZ_OPACR3_OPAC30_MASK (0xF0U) +#define AIPSTZ_OPACR3_OPAC30_SHIFT (4U) +/*! OPAC30 + * 0bxxx0..Accesses from an untrusted master are allowed. + * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + * 0bxx0x..This peripheral allows write accesses. + * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + * 0bx0xx..This peripheral does not require supervisor privilege level for accesses. + * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must be set. If not, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ. + */ +#define AIPSTZ_OPACR3_OPAC30(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR3_OPAC30_SHIFT)) & AIPSTZ_OPACR3_OPAC30_MASK) +#define AIPSTZ_OPACR3_OPAC29_MASK (0xF00U) +#define AIPSTZ_OPACR3_OPAC29_SHIFT (8U) +/*! OPAC29 + * 0bxxx0..Accesses from an untrusted master are allowed. + * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + * 0bxx0x..This peripheral allows write accesses. + * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + * 0bx0xx..This peripheral does not require supervisor privilege level for accesses. + * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must be set. If not, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ. + */ +#define AIPSTZ_OPACR3_OPAC29(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR3_OPAC29_SHIFT)) & AIPSTZ_OPACR3_OPAC29_MASK) +#define AIPSTZ_OPACR3_OPAC28_MASK (0xF000U) +#define AIPSTZ_OPACR3_OPAC28_SHIFT (12U) +/*! OPAC28 + * 0bxxx0..Accesses from an untrusted master are allowed. + * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + * 0bxx0x..This peripheral allows write accesses. + * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + * 0bx0xx..This peripheral does not require supervisor privilege level for accesses. + * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must be set. If not, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ. + */ +#define AIPSTZ_OPACR3_OPAC28(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR3_OPAC28_SHIFT)) & AIPSTZ_OPACR3_OPAC28_MASK) +#define AIPSTZ_OPACR3_OPAC27_MASK (0xF0000U) +#define AIPSTZ_OPACR3_OPAC27_SHIFT (16U) +/*! OPAC27 + * 0bxxx0..Accesses from an untrusted master are allowed. + * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + * 0bxx0x..This peripheral allows write accesses. + * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + * 0bx0xx..This peripheral does not require supervisor privilege level for accesses. + * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must be set. If not, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ. + */ +#define AIPSTZ_OPACR3_OPAC27(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR3_OPAC27_SHIFT)) & AIPSTZ_OPACR3_OPAC27_MASK) +#define AIPSTZ_OPACR3_OPAC26_MASK (0xF00000U) +#define AIPSTZ_OPACR3_OPAC26_SHIFT (20U) +/*! OPAC26 + * 0bxxx0..Accesses from an untrusted master are allowed. + * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + * 0bxx0x..This peripheral allows write accesses. + * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + * 0bx0xx..This peripheral does not require supervisor privilege level for accesses. + * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must be set. If not, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ. + */ +#define AIPSTZ_OPACR3_OPAC26(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR3_OPAC26_SHIFT)) & AIPSTZ_OPACR3_OPAC26_MASK) +#define AIPSTZ_OPACR3_OPAC25_MASK (0xF000000U) +#define AIPSTZ_OPACR3_OPAC25_SHIFT (24U) +/*! OPAC25 + * 0bxxx0..Accesses from an untrusted master are allowed. + * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + * 0bxx0x..This peripheral allows write accesses. + * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + * 0bx0xx..This peripheral does not require supervisor privilege level for accesses. + * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must be set. If not, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ. + */ +#define AIPSTZ_OPACR3_OPAC25(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR3_OPAC25_SHIFT)) & AIPSTZ_OPACR3_OPAC25_MASK) +#define AIPSTZ_OPACR3_OPAC24_MASK (0xF0000000U) +#define AIPSTZ_OPACR3_OPAC24_SHIFT (28U) +/*! OPAC24 + * 0bxxx0..Accesses from an untrusted master are allowed. + * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + * 0bxx0x..This peripheral allows write accesses. + * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + * 0bx0xx..This peripheral does not require supervisor privilege level for accesses. + * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must be set. If not, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ. + */ +#define AIPSTZ_OPACR3_OPAC24(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR3_OPAC24_SHIFT)) & AIPSTZ_OPACR3_OPAC24_MASK) +/*! @} */ + +/*! @name OPACR4 - Off-Platform Peripheral Access Control Registers */ +/*! @{ */ +#define AIPSTZ_OPACR4_OPAC33_MASK (0xF000000U) +#define AIPSTZ_OPACR4_OPAC33_SHIFT (24U) +/*! OPAC33 + * 0bxxx0..Accesses from an untrusted master are allowed. + * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + * 0bxx0x..This peripheral allows write accesses. + * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + * 0bx0xx..This peripheral does not require supervisor privilege level for accesses. + * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must be set. If not, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ. + */ +#define AIPSTZ_OPACR4_OPAC33(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR4_OPAC33_SHIFT)) & AIPSTZ_OPACR4_OPAC33_MASK) +#define AIPSTZ_OPACR4_OPAC32_MASK (0xF0000000U) +#define AIPSTZ_OPACR4_OPAC32_SHIFT (28U) +/*! OPAC32 + * 0bxxx0..Accesses from an untrusted master are allowed. + * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + * 0bxx0x..This peripheral allows write accesses. + * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + * 0bx0xx..This peripheral does not require supervisor privilege level for accesses. + * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must be set. If not, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ. + */ +#define AIPSTZ_OPACR4_OPAC32(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR4_OPAC32_SHIFT)) & AIPSTZ_OPACR4_OPAC32_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group AIPSTZ_Register_Masks */ + + +/* AIPSTZ - Peripheral instance base addresses */ +/** Peripheral AIPSTZ1 base address */ +#define AIPSTZ1_BASE (0x4007C000u) +/** Peripheral AIPSTZ1 base pointer */ +#define AIPSTZ1 ((AIPSTZ_Type *)AIPSTZ1_BASE) +/** Peripheral AIPSTZ2 base address */ +#define AIPSTZ2_BASE (0x4017C000u) +/** Peripheral AIPSTZ2 base pointer */ +#define AIPSTZ2 ((AIPSTZ_Type *)AIPSTZ2_BASE) +/** Peripheral AIPSTZ3 base address */ +#define AIPSTZ3_BASE (0x4027C000u) +/** Peripheral AIPSTZ3 base pointer */ +#define AIPSTZ3 ((AIPSTZ_Type *)AIPSTZ3_BASE) +/** Peripheral AIPSTZ4 base address */ +#define AIPSTZ4_BASE (0x4037C000u) +/** Peripheral AIPSTZ4 base pointer */ +#define AIPSTZ4 ((AIPSTZ_Type *)AIPSTZ4_BASE) +/** Array initializer of AIPSTZ peripheral base addresses */ +#define AIPSTZ_BASE_ADDRS { 0u, AIPSTZ1_BASE, AIPSTZ2_BASE, AIPSTZ3_BASE, AIPSTZ4_BASE } +/** Array initializer of AIPSTZ peripheral base pointers */ +#define AIPSTZ_BASE_PTRS { (AIPSTZ_Type *)0u, AIPSTZ1, AIPSTZ2, AIPSTZ3, AIPSTZ4 } + +/*! + * @} + */ /* end of group AIPSTZ_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- AOI Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup AOI_Peripheral_Access_Layer AOI Peripheral Access Layer + * @{ + */ + +/** AOI - Register Layout Typedef */ +typedef struct { + struct { /* offset: 0x0, array step: 0x4 */ + __IO uint16_t BFCRT01; /**< Boolean Function Term 0 and 1 Configuration Register for EVENTn, array offset: 0x0, array step: 0x4 */ + __IO uint16_t BFCRT23; /**< Boolean Function Term 2 and 3 Configuration Register for EVENTn, array offset: 0x2, array step: 0x4 */ + } BFCRT[4]; +} AOI_Type; + +/* ---------------------------------------------------------------------------- + -- AOI Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup AOI_Register_Masks AOI Register Masks + * @{ + */ + +/*! @name BFCRT01 - Boolean Function Term 0 and 1 Configuration Register for EVENTn */ +/*! @{ */ +#define AOI_BFCRT01_PT1_DC_MASK (0x3U) +#define AOI_BFCRT01_PT1_DC_SHIFT (0U) +/*! PT1_DC - Product term 1, D input configuration + * 0b00..Force the D input in this product term to a logical zero + * 0b01..Pass the D input in this product term + * 0b10..Complement the D input in this product term + * 0b11..Force the D input in this product term to a logical one + */ +#define AOI_BFCRT01_PT1_DC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT01_PT1_DC_SHIFT)) & AOI_BFCRT01_PT1_DC_MASK) +#define AOI_BFCRT01_PT1_CC_MASK (0xCU) +#define AOI_BFCRT01_PT1_CC_SHIFT (2U) +/*! PT1_CC - Product term 1, C input configuration + * 0b00..Force the C input in this product term to a logical zero + * 0b01..Pass the C input in this product term + * 0b10..Complement the C input in this product term + * 0b11..Force the C input in this product term to a logical one + */ +#define AOI_BFCRT01_PT1_CC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT01_PT1_CC_SHIFT)) & AOI_BFCRT01_PT1_CC_MASK) +#define AOI_BFCRT01_PT1_BC_MASK (0x30U) +#define AOI_BFCRT01_PT1_BC_SHIFT (4U) +/*! PT1_BC - Product term 1, B input configuration + * 0b00..Force the B input in this product term to a logical zero + * 0b01..Pass the B input in this product term + * 0b10..Complement the B input in this product term + * 0b11..Force the B input in this product term to a logical one + */ +#define AOI_BFCRT01_PT1_BC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT01_PT1_BC_SHIFT)) & AOI_BFCRT01_PT1_BC_MASK) +#define AOI_BFCRT01_PT1_AC_MASK (0xC0U) +#define AOI_BFCRT01_PT1_AC_SHIFT (6U) +/*! PT1_AC - Product term 1, A input configuration + * 0b00..Force the A input in this product term to a logical zero + * 0b01..Pass the A input in this product term + * 0b10..Complement the A input in this product term + * 0b11..Force the A input in this product term to a logical one + */ +#define AOI_BFCRT01_PT1_AC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT01_PT1_AC_SHIFT)) & AOI_BFCRT01_PT1_AC_MASK) +#define AOI_BFCRT01_PT0_DC_MASK (0x300U) +#define AOI_BFCRT01_PT0_DC_SHIFT (8U) +/*! PT0_DC - Product term 0, D input configuration + * 0b00..Force the D input in this product term to a logical zero + * 0b01..Pass the D input in this product term + * 0b10..Complement the D input in this product term + * 0b11..Force the D input in this product term to a logical one + */ +#define AOI_BFCRT01_PT0_DC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT01_PT0_DC_SHIFT)) & AOI_BFCRT01_PT0_DC_MASK) +#define AOI_BFCRT01_PT0_CC_MASK (0xC00U) +#define AOI_BFCRT01_PT0_CC_SHIFT (10U) +/*! PT0_CC - Product term 0, C input configuration + * 0b00..Force the C input in this product term to a logical zero + * 0b01..Pass the C input in this product term + * 0b10..Complement the C input in this product term + * 0b11..Force the C input in this product term to a logical one + */ +#define AOI_BFCRT01_PT0_CC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT01_PT0_CC_SHIFT)) & AOI_BFCRT01_PT0_CC_MASK) +#define AOI_BFCRT01_PT0_BC_MASK (0x3000U) +#define AOI_BFCRT01_PT0_BC_SHIFT (12U) +/*! PT0_BC - Product term 0, B input configuration + * 0b00..Force the B input in this product term to a logical zero + * 0b01..Pass the B input in this product term + * 0b10..Complement the B input in this product term + * 0b11..Force the B input in this product term to a logical one + */ +#define AOI_BFCRT01_PT0_BC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT01_PT0_BC_SHIFT)) & AOI_BFCRT01_PT0_BC_MASK) +#define AOI_BFCRT01_PT0_AC_MASK (0xC000U) +#define AOI_BFCRT01_PT0_AC_SHIFT (14U) +/*! PT0_AC - Product term 0, A input configuration + * 0b00..Force the A input in this product term to a logical zero + * 0b01..Pass the A input in this product term + * 0b10..Complement the A input in this product term + * 0b11..Force the A input in this product term to a logical one + */ +#define AOI_BFCRT01_PT0_AC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT01_PT0_AC_SHIFT)) & AOI_BFCRT01_PT0_AC_MASK) +/*! @} */ + +/* The count of AOI_BFCRT01 */ +#define AOI_BFCRT01_COUNT (4U) + +/*! @name BFCRT23 - Boolean Function Term 2 and 3 Configuration Register for EVENTn */ +/*! @{ */ +#define AOI_BFCRT23_PT3_DC_MASK (0x3U) +#define AOI_BFCRT23_PT3_DC_SHIFT (0U) +/*! PT3_DC - Product term 3, D input configuration + * 0b00..Force the D input in this product term to a logical zero + * 0b01..Pass the D input in this product term + * 0b10..Complement the D input in this product term + * 0b11..Force the D input in this product term to a logical one + */ +#define AOI_BFCRT23_PT3_DC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT23_PT3_DC_SHIFT)) & AOI_BFCRT23_PT3_DC_MASK) +#define AOI_BFCRT23_PT3_CC_MASK (0xCU) +#define AOI_BFCRT23_PT3_CC_SHIFT (2U) +/*! PT3_CC - Product term 3, C input configuration + * 0b00..Force the C input in this product term to a logical zero + * 0b01..Pass the C input in this product term + * 0b10..Complement the C input in this product term + * 0b11..Force the C input in this product term to a logical one + */ +#define AOI_BFCRT23_PT3_CC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT23_PT3_CC_SHIFT)) & AOI_BFCRT23_PT3_CC_MASK) +#define AOI_BFCRT23_PT3_BC_MASK (0x30U) +#define AOI_BFCRT23_PT3_BC_SHIFT (4U) +/*! PT3_BC - Product term 3, B input configuration + * 0b00..Force the B input in this product term to a logical zero + * 0b01..Pass the B input in this product term + * 0b10..Complement the B input in this product term + * 0b11..Force the B input in this product term to a logical one + */ +#define AOI_BFCRT23_PT3_BC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT23_PT3_BC_SHIFT)) & AOI_BFCRT23_PT3_BC_MASK) +#define AOI_BFCRT23_PT3_AC_MASK (0xC0U) +#define AOI_BFCRT23_PT3_AC_SHIFT (6U) +/*! PT3_AC - Product term 3, A input configuration + * 0b00..Force the A input in this product term to a logical zero + * 0b01..Pass the A input in this product term + * 0b10..Complement the A input in this product term + * 0b11..Force the A input in this product term to a logical one + */ +#define AOI_BFCRT23_PT3_AC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT23_PT3_AC_SHIFT)) & AOI_BFCRT23_PT3_AC_MASK) +#define AOI_BFCRT23_PT2_DC_MASK (0x300U) +#define AOI_BFCRT23_PT2_DC_SHIFT (8U) +/*! PT2_DC - Product term 2, D input configuration + * 0b00..Force the D input in this product term to a logical zero + * 0b01..Pass the D input in this product term + * 0b10..Complement the D input in this product term + * 0b11..Force the D input in this product term to a logical one + */ +#define AOI_BFCRT23_PT2_DC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT23_PT2_DC_SHIFT)) & AOI_BFCRT23_PT2_DC_MASK) +#define AOI_BFCRT23_PT2_CC_MASK (0xC00U) +#define AOI_BFCRT23_PT2_CC_SHIFT (10U) +/*! PT2_CC - Product term 2, C input configuration + * 0b00..Force the C input in this product term to a logical zero + * 0b01..Pass the C input in this product term + * 0b10..Complement the C input in this product term + * 0b11..Force the C input in this product term to a logical one + */ +#define AOI_BFCRT23_PT2_CC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT23_PT2_CC_SHIFT)) & AOI_BFCRT23_PT2_CC_MASK) +#define AOI_BFCRT23_PT2_BC_MASK (0x3000U) +#define AOI_BFCRT23_PT2_BC_SHIFT (12U) +/*! PT2_BC - Product term 2, B input configuration + * 0b00..Force the B input in this product term to a logical zero + * 0b01..Pass the B input in this product term + * 0b10..Complement the B input in this product term + * 0b11..Force the B input in this product term to a logical one + */ +#define AOI_BFCRT23_PT2_BC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT23_PT2_BC_SHIFT)) & AOI_BFCRT23_PT2_BC_MASK) +#define AOI_BFCRT23_PT2_AC_MASK (0xC000U) +#define AOI_BFCRT23_PT2_AC_SHIFT (14U) +/*! PT2_AC - Product term 2, A input configuration + * 0b00..Force the A input in this product term to a logical zero + * 0b01..Pass the A input in this product term + * 0b10..Complement the A input in this product term + * 0b11..Force the A input in this product term to a logical one + */ +#define AOI_BFCRT23_PT2_AC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT23_PT2_AC_SHIFT)) & AOI_BFCRT23_PT2_AC_MASK) +/*! @} */ + +/* The count of AOI_BFCRT23 */ +#define AOI_BFCRT23_COUNT (4U) + + +/*! + * @} + */ /* end of group AOI_Register_Masks */ + + +/* AOI - Peripheral instance base addresses */ +/** Peripheral AOI1 base address */ +#define AOI1_BASE (0x403B4000u) +/** Peripheral AOI1 base pointer */ +#define AOI1 ((AOI_Type *)AOI1_BASE) +/** Peripheral AOI2 base address */ +#define AOI2_BASE (0x403B8000u) +/** Peripheral AOI2 base pointer */ +#define AOI2 ((AOI_Type *)AOI2_BASE) +/** Array initializer of AOI peripheral base addresses */ +#define AOI_BASE_ADDRS { 0u, AOI1_BASE, AOI2_BASE } +/** Array initializer of AOI peripheral base pointers */ +#define AOI_BASE_PTRS { (AOI_Type *)0u, AOI1, AOI2 } + +/*! + * @} + */ /* end of group AOI_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- BEE Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup BEE_Peripheral_Access_Layer BEE Peripheral Access Layer + * @{ + */ + +/** BEE - Register Layout Typedef */ +typedef struct { + __IO uint32_t CTRL; /**< BEE Control Register, offset: 0x0 */ + __IO uint32_t ADDR_OFFSET0; /**< , offset: 0x4 */ + __IO uint32_t ADDR_OFFSET1; /**< , offset: 0x8 */ + __IO uint32_t AES_KEY0_W0; /**< , offset: 0xC */ + __IO uint32_t AES_KEY0_W1; /**< , offset: 0x10 */ + __IO uint32_t AES_KEY0_W2; /**< , offset: 0x14 */ + __IO uint32_t AES_KEY0_W3; /**< , offset: 0x18 */ + __IO uint32_t STATUS; /**< , offset: 0x1C */ + __O uint32_t CTR_NONCE0_W0; /**< , offset: 0x20 */ + __O uint32_t CTR_NONCE0_W1; /**< , offset: 0x24 */ + __O uint32_t CTR_NONCE0_W2; /**< , offset: 0x28 */ + __O uint32_t CTR_NONCE0_W3; /**< , offset: 0x2C */ + __O uint32_t CTR_NONCE1_W0; /**< , offset: 0x30 */ + __O uint32_t CTR_NONCE1_W1; /**< , offset: 0x34 */ + __O uint32_t CTR_NONCE1_W2; /**< , offset: 0x38 */ + __O uint32_t CTR_NONCE1_W3; /**< , offset: 0x3C */ + __IO uint32_t REGION1_TOP; /**< , offset: 0x40 */ + __IO uint32_t REGION1_BOT; /**< , offset: 0x44 */ +} BEE_Type; + +/* ---------------------------------------------------------------------------- + -- BEE Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup BEE_Register_Masks BEE Register Masks + * @{ + */ + +/*! @name CTRL - BEE Control Register */ +/*! @{ */ +#define BEE_CTRL_BEE_ENABLE_MASK (0x1U) +#define BEE_CTRL_BEE_ENABLE_SHIFT (0U) +/*! BEE_ENABLE + * 0b0..Disable BEE + * 0b1..Enable BEE + */ +#define BEE_CTRL_BEE_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_BEE_ENABLE_SHIFT)) & BEE_CTRL_BEE_ENABLE_MASK) +#define BEE_CTRL_CTRL_CLK_EN_MASK (0x2U) +#define BEE_CTRL_CTRL_CLK_EN_SHIFT (1U) +#define BEE_CTRL_CTRL_CLK_EN(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_CTRL_CLK_EN_SHIFT)) & BEE_CTRL_CTRL_CLK_EN_MASK) +#define BEE_CTRL_CTRL_SFTRST_N_MASK (0x4U) +#define BEE_CTRL_CTRL_SFTRST_N_SHIFT (2U) +#define BEE_CTRL_CTRL_SFTRST_N(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_CTRL_SFTRST_N_SHIFT)) & BEE_CTRL_CTRL_SFTRST_N_MASK) +#define BEE_CTRL_KEY_VALID_MASK (0x10U) +#define BEE_CTRL_KEY_VALID_SHIFT (4U) +#define BEE_CTRL_KEY_VALID(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_KEY_VALID_SHIFT)) & BEE_CTRL_KEY_VALID_MASK) +#define BEE_CTRL_KEY_REGION_SEL_MASK (0x20U) +#define BEE_CTRL_KEY_REGION_SEL_SHIFT (5U) +/*! KEY_REGION_SEL + * 0b0..Load AES key for region0 + * 0b1..Load AES key for region1 + */ +#define BEE_CTRL_KEY_REGION_SEL(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_KEY_REGION_SEL_SHIFT)) & BEE_CTRL_KEY_REGION_SEL_MASK) +#define BEE_CTRL_AC_PROT_EN_MASK (0x40U) +#define BEE_CTRL_AC_PROT_EN_SHIFT (6U) +#define BEE_CTRL_AC_PROT_EN(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_AC_PROT_EN_SHIFT)) & BEE_CTRL_AC_PROT_EN_MASK) +#define BEE_CTRL_LITTLE_ENDIAN_MASK (0x80U) +#define BEE_CTRL_LITTLE_ENDIAN_SHIFT (7U) +/*! LITTLE_ENDIAN + * 0b0..The input and output data of the AES core is swapped as below: {B15,B14,B13,B12,B11,B10,B9,B8, B7,B6,B5,B4,B3,B2,B1,B0} swap to {B0,B1,B2,B3,B4,B5,B6,B7, B8,B9,B10,B11,B12,B13,B14,B15}, where B0~B15 refers to Byte0 to Byte15. + * 0b1..The input and output data of AES core is not swapped. + */ +#define BEE_CTRL_LITTLE_ENDIAN(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_LITTLE_ENDIAN_SHIFT)) & BEE_CTRL_LITTLE_ENDIAN_MASK) +#define BEE_CTRL_SECURITY_LEVEL_R0_MASK (0x300U) +#define BEE_CTRL_SECURITY_LEVEL_R0_SHIFT (8U) +#define BEE_CTRL_SECURITY_LEVEL_R0(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_SECURITY_LEVEL_R0_SHIFT)) & BEE_CTRL_SECURITY_LEVEL_R0_MASK) +#define BEE_CTRL_CTRL_AES_MODE_R0_MASK (0x400U) +#define BEE_CTRL_CTRL_AES_MODE_R0_SHIFT (10U) +/*! CTRL_AES_MODE_R0 + * 0b0..ECB + * 0b1..CTR + */ +#define BEE_CTRL_CTRL_AES_MODE_R0(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_CTRL_AES_MODE_R0_SHIFT)) & BEE_CTRL_CTRL_AES_MODE_R0_MASK) +#define BEE_CTRL_SECURITY_LEVEL_R1_MASK (0x3000U) +#define BEE_CTRL_SECURITY_LEVEL_R1_SHIFT (12U) +#define BEE_CTRL_SECURITY_LEVEL_R1(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_SECURITY_LEVEL_R1_SHIFT)) & BEE_CTRL_SECURITY_LEVEL_R1_MASK) +#define BEE_CTRL_CTRL_AES_MODE_R1_MASK (0x4000U) +#define BEE_CTRL_CTRL_AES_MODE_R1_SHIFT (14U) +/*! CTRL_AES_MODE_R1 + * 0b0..ECB + * 0b1..CTR + */ +#define BEE_CTRL_CTRL_AES_MODE_R1(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_CTRL_AES_MODE_R1_SHIFT)) & BEE_CTRL_CTRL_AES_MODE_R1_MASK) +#define BEE_CTRL_BEE_ENABLE_LOCK_MASK (0x10000U) +#define BEE_CTRL_BEE_ENABLE_LOCK_SHIFT (16U) +#define BEE_CTRL_BEE_ENABLE_LOCK(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_BEE_ENABLE_LOCK_SHIFT)) & BEE_CTRL_BEE_ENABLE_LOCK_MASK) +#define BEE_CTRL_CTRL_CLK_EN_LOCK_MASK (0x20000U) +#define BEE_CTRL_CTRL_CLK_EN_LOCK_SHIFT (17U) +#define BEE_CTRL_CTRL_CLK_EN_LOCK(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_CTRL_CLK_EN_LOCK_SHIFT)) & BEE_CTRL_CTRL_CLK_EN_LOCK_MASK) +#define BEE_CTRL_CTRL_SFTRST_N_LOCK_MASK (0x40000U) +#define BEE_CTRL_CTRL_SFTRST_N_LOCK_SHIFT (18U) +#define BEE_CTRL_CTRL_SFTRST_N_LOCK(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_CTRL_SFTRST_N_LOCK_SHIFT)) & BEE_CTRL_CTRL_SFTRST_N_LOCK_MASK) +#define BEE_CTRL_REGION1_ADDR_LOCK_MASK (0x80000U) +#define BEE_CTRL_REGION1_ADDR_LOCK_SHIFT (19U) +#define BEE_CTRL_REGION1_ADDR_LOCK(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_REGION1_ADDR_LOCK_SHIFT)) & BEE_CTRL_REGION1_ADDR_LOCK_MASK) +#define BEE_CTRL_KEY_VALID_LOCK_MASK (0x100000U) +#define BEE_CTRL_KEY_VALID_LOCK_SHIFT (20U) +#define BEE_CTRL_KEY_VALID_LOCK(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_KEY_VALID_LOCK_SHIFT)) & BEE_CTRL_KEY_VALID_LOCK_MASK) +#define BEE_CTRL_KEY_REGION_SEL_LOCK_MASK (0x200000U) +#define BEE_CTRL_KEY_REGION_SEL_LOCK_SHIFT (21U) +#define BEE_CTRL_KEY_REGION_SEL_LOCK(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_KEY_REGION_SEL_LOCK_SHIFT)) & BEE_CTRL_KEY_REGION_SEL_LOCK_MASK) +#define BEE_CTRL_AC_PROT_EN_LOCK_MASK (0x400000U) +#define BEE_CTRL_AC_PROT_EN_LOCK_SHIFT (22U) +#define BEE_CTRL_AC_PROT_EN_LOCK(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_AC_PROT_EN_LOCK_SHIFT)) & BEE_CTRL_AC_PROT_EN_LOCK_MASK) +#define BEE_CTRL_LITTLE_ENDIAN_LOCK_MASK (0x800000U) +#define BEE_CTRL_LITTLE_ENDIAN_LOCK_SHIFT (23U) +#define BEE_CTRL_LITTLE_ENDIAN_LOCK(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_LITTLE_ENDIAN_LOCK_SHIFT)) & BEE_CTRL_LITTLE_ENDIAN_LOCK_MASK) +#define BEE_CTRL_SECURITY_LEVEL_R0_LOCK_MASK (0x3000000U) +#define BEE_CTRL_SECURITY_LEVEL_R0_LOCK_SHIFT (24U) +#define BEE_CTRL_SECURITY_LEVEL_R0_LOCK(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_SECURITY_LEVEL_R0_LOCK_SHIFT)) & BEE_CTRL_SECURITY_LEVEL_R0_LOCK_MASK) +#define BEE_CTRL_CTRL_AES_MODE_R0_LOCK_MASK (0x4000000U) +#define BEE_CTRL_CTRL_AES_MODE_R0_LOCK_SHIFT (26U) +#define BEE_CTRL_CTRL_AES_MODE_R0_LOCK(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_CTRL_AES_MODE_R0_LOCK_SHIFT)) & BEE_CTRL_CTRL_AES_MODE_R0_LOCK_MASK) +#define BEE_CTRL_REGION0_KEY_LOCK_MASK (0x8000000U) +#define BEE_CTRL_REGION0_KEY_LOCK_SHIFT (27U) +#define BEE_CTRL_REGION0_KEY_LOCK(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_REGION0_KEY_LOCK_SHIFT)) & BEE_CTRL_REGION0_KEY_LOCK_MASK) +#define BEE_CTRL_SECURITY_LEVEL_R1_LOCK_MASK (0x30000000U) +#define BEE_CTRL_SECURITY_LEVEL_R1_LOCK_SHIFT (28U) +#define BEE_CTRL_SECURITY_LEVEL_R1_LOCK(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_SECURITY_LEVEL_R1_LOCK_SHIFT)) & BEE_CTRL_SECURITY_LEVEL_R1_LOCK_MASK) +#define BEE_CTRL_CTRL_AES_MODE_R1_LOCK_MASK (0x40000000U) +#define BEE_CTRL_CTRL_AES_MODE_R1_LOCK_SHIFT (30U) +#define BEE_CTRL_CTRL_AES_MODE_R1_LOCK(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_CTRL_AES_MODE_R1_LOCK_SHIFT)) & BEE_CTRL_CTRL_AES_MODE_R1_LOCK_MASK) +#define BEE_CTRL_REGION1_KEY_LOCK_MASK (0x80000000U) +#define BEE_CTRL_REGION1_KEY_LOCK_SHIFT (31U) +#define BEE_CTRL_REGION1_KEY_LOCK(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_REGION1_KEY_LOCK_SHIFT)) & BEE_CTRL_REGION1_KEY_LOCK_MASK) +/*! @} */ + +/*! @name ADDR_OFFSET0 - */ +/*! @{ */ +#define BEE_ADDR_OFFSET0_ADDR_OFFSET0_MASK (0xFFFFU) +#define BEE_ADDR_OFFSET0_ADDR_OFFSET0_SHIFT (0U) +#define BEE_ADDR_OFFSET0_ADDR_OFFSET0(x) (((uint32_t)(((uint32_t)(x)) << BEE_ADDR_OFFSET0_ADDR_OFFSET0_SHIFT)) & BEE_ADDR_OFFSET0_ADDR_OFFSET0_MASK) +#define BEE_ADDR_OFFSET0_ADDR_OFFSET0_LOCK_MASK (0xFFFF0000U) +#define BEE_ADDR_OFFSET0_ADDR_OFFSET0_LOCK_SHIFT (16U) +#define BEE_ADDR_OFFSET0_ADDR_OFFSET0_LOCK(x) (((uint32_t)(((uint32_t)(x)) << BEE_ADDR_OFFSET0_ADDR_OFFSET0_LOCK_SHIFT)) & BEE_ADDR_OFFSET0_ADDR_OFFSET0_LOCK_MASK) +/*! @} */ + +/*! @name ADDR_OFFSET1 - */ +/*! @{ */ +#define BEE_ADDR_OFFSET1_ADDR_OFFSET1_MASK (0xFFFFU) +#define BEE_ADDR_OFFSET1_ADDR_OFFSET1_SHIFT (0U) +#define BEE_ADDR_OFFSET1_ADDR_OFFSET1(x) (((uint32_t)(((uint32_t)(x)) << BEE_ADDR_OFFSET1_ADDR_OFFSET1_SHIFT)) & BEE_ADDR_OFFSET1_ADDR_OFFSET1_MASK) +#define BEE_ADDR_OFFSET1_ADDR_OFFSET1_LOCK_MASK (0xFFFF0000U) +#define BEE_ADDR_OFFSET1_ADDR_OFFSET1_LOCK_SHIFT (16U) +#define BEE_ADDR_OFFSET1_ADDR_OFFSET1_LOCK(x) (((uint32_t)(((uint32_t)(x)) << BEE_ADDR_OFFSET1_ADDR_OFFSET1_LOCK_SHIFT)) & BEE_ADDR_OFFSET1_ADDR_OFFSET1_LOCK_MASK) +/*! @} */ + +/*! @name AES_KEY0_W0 - */ +/*! @{ */ +#define BEE_AES_KEY0_W0_KEY0_MASK (0xFFFFFFFFU) +#define BEE_AES_KEY0_W0_KEY0_SHIFT (0U) +#define BEE_AES_KEY0_W0_KEY0(x) (((uint32_t)(((uint32_t)(x)) << BEE_AES_KEY0_W0_KEY0_SHIFT)) & BEE_AES_KEY0_W0_KEY0_MASK) +/*! @} */ + +/*! @name AES_KEY0_W1 - */ +/*! @{ */ +#define BEE_AES_KEY0_W1_KEY1_MASK (0xFFFFFFFFU) +#define BEE_AES_KEY0_W1_KEY1_SHIFT (0U) +#define BEE_AES_KEY0_W1_KEY1(x) (((uint32_t)(((uint32_t)(x)) << BEE_AES_KEY0_W1_KEY1_SHIFT)) & BEE_AES_KEY0_W1_KEY1_MASK) +/*! @} */ + +/*! @name AES_KEY0_W2 - */ +/*! @{ */ +#define BEE_AES_KEY0_W2_KEY2_MASK (0xFFFFFFFFU) +#define BEE_AES_KEY0_W2_KEY2_SHIFT (0U) +#define BEE_AES_KEY0_W2_KEY2(x) (((uint32_t)(((uint32_t)(x)) << BEE_AES_KEY0_W2_KEY2_SHIFT)) & BEE_AES_KEY0_W2_KEY2_MASK) +/*! @} */ + +/*! @name AES_KEY0_W3 - */ +/*! @{ */ +#define BEE_AES_KEY0_W3_KEY3_MASK (0xFFFFFFFFU) +#define BEE_AES_KEY0_W3_KEY3_SHIFT (0U) +#define BEE_AES_KEY0_W3_KEY3(x) (((uint32_t)(((uint32_t)(x)) << BEE_AES_KEY0_W3_KEY3_SHIFT)) & BEE_AES_KEY0_W3_KEY3_MASK) +/*! @} */ + +/*! @name STATUS - */ +/*! @{ */ +#define BEE_STATUS_IRQ_VEC_MASK (0xFFU) +#define BEE_STATUS_IRQ_VEC_SHIFT (0U) +#define BEE_STATUS_IRQ_VEC(x) (((uint32_t)(((uint32_t)(x)) << BEE_STATUS_IRQ_VEC_SHIFT)) & BEE_STATUS_IRQ_VEC_MASK) +#define BEE_STATUS_BEE_IDLE_MASK (0x100U) +#define BEE_STATUS_BEE_IDLE_SHIFT (8U) +#define BEE_STATUS_BEE_IDLE(x) (((uint32_t)(((uint32_t)(x)) << BEE_STATUS_BEE_IDLE_SHIFT)) & BEE_STATUS_BEE_IDLE_MASK) +/*! @} */ + +/*! @name CTR_NONCE0_W0 - */ +/*! @{ */ +#define BEE_CTR_NONCE0_W0_NONCE00_MASK (0xFFFFFFFFU) +#define BEE_CTR_NONCE0_W0_NONCE00_SHIFT (0U) +#define BEE_CTR_NONCE0_W0_NONCE00(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTR_NONCE0_W0_NONCE00_SHIFT)) & BEE_CTR_NONCE0_W0_NONCE00_MASK) +/*! @} */ + +/*! @name CTR_NONCE0_W1 - */ +/*! @{ */ +#define BEE_CTR_NONCE0_W1_NONCE01_MASK (0xFFFFFFFFU) +#define BEE_CTR_NONCE0_W1_NONCE01_SHIFT (0U) +#define BEE_CTR_NONCE0_W1_NONCE01(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTR_NONCE0_W1_NONCE01_SHIFT)) & BEE_CTR_NONCE0_W1_NONCE01_MASK) +/*! @} */ + +/*! @name CTR_NONCE0_W2 - */ +/*! @{ */ +#define BEE_CTR_NONCE0_W2_NONCE02_MASK (0xFFFFFFFFU) +#define BEE_CTR_NONCE0_W2_NONCE02_SHIFT (0U) +#define BEE_CTR_NONCE0_W2_NONCE02(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTR_NONCE0_W2_NONCE02_SHIFT)) & BEE_CTR_NONCE0_W2_NONCE02_MASK) +/*! @} */ + +/*! @name CTR_NONCE0_W3 - */ +/*! @{ */ +#define BEE_CTR_NONCE0_W3_NONCE03_MASK (0xFFFFFFFFU) +#define BEE_CTR_NONCE0_W3_NONCE03_SHIFT (0U) +#define BEE_CTR_NONCE0_W3_NONCE03(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTR_NONCE0_W3_NONCE03_SHIFT)) & BEE_CTR_NONCE0_W3_NONCE03_MASK) +/*! @} */ + +/*! @name CTR_NONCE1_W0 - */ +/*! @{ */ +#define BEE_CTR_NONCE1_W0_NONCE10_MASK (0xFFFFFFFFU) +#define BEE_CTR_NONCE1_W0_NONCE10_SHIFT (0U) +#define BEE_CTR_NONCE1_W0_NONCE10(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTR_NONCE1_W0_NONCE10_SHIFT)) & BEE_CTR_NONCE1_W0_NONCE10_MASK) +/*! @} */ + +/*! @name CTR_NONCE1_W1 - */ +/*! @{ */ +#define BEE_CTR_NONCE1_W1_NONCE11_MASK (0xFFFFFFFFU) +#define BEE_CTR_NONCE1_W1_NONCE11_SHIFT (0U) +#define BEE_CTR_NONCE1_W1_NONCE11(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTR_NONCE1_W1_NONCE11_SHIFT)) & BEE_CTR_NONCE1_W1_NONCE11_MASK) +/*! @} */ + +/*! @name CTR_NONCE1_W2 - */ +/*! @{ */ +#define BEE_CTR_NONCE1_W2_NONCE12_MASK (0xFFFFFFFFU) +#define BEE_CTR_NONCE1_W2_NONCE12_SHIFT (0U) +#define BEE_CTR_NONCE1_W2_NONCE12(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTR_NONCE1_W2_NONCE12_SHIFT)) & BEE_CTR_NONCE1_W2_NONCE12_MASK) +/*! @} */ + +/*! @name CTR_NONCE1_W3 - */ +/*! @{ */ +#define BEE_CTR_NONCE1_W3_NONCE13_MASK (0xFFFFFFFFU) +#define BEE_CTR_NONCE1_W3_NONCE13_SHIFT (0U) +#define BEE_CTR_NONCE1_W3_NONCE13(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTR_NONCE1_W3_NONCE13_SHIFT)) & BEE_CTR_NONCE1_W3_NONCE13_MASK) +/*! @} */ + +/*! @name REGION1_TOP - */ +/*! @{ */ +#define BEE_REGION1_TOP_REGION1_TOP_MASK (0xFFFFFFFFU) +#define BEE_REGION1_TOP_REGION1_TOP_SHIFT (0U) +#define BEE_REGION1_TOP_REGION1_TOP(x) (((uint32_t)(((uint32_t)(x)) << BEE_REGION1_TOP_REGION1_TOP_SHIFT)) & BEE_REGION1_TOP_REGION1_TOP_MASK) +/*! @} */ + +/*! @name REGION1_BOT - */ +/*! @{ */ +#define BEE_REGION1_BOT_REGION1_BOT_MASK (0xFFFFFFFFU) +#define BEE_REGION1_BOT_REGION1_BOT_SHIFT (0U) +#define BEE_REGION1_BOT_REGION1_BOT(x) (((uint32_t)(((uint32_t)(x)) << BEE_REGION1_BOT_REGION1_BOT_SHIFT)) & BEE_REGION1_BOT_REGION1_BOT_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group BEE_Register_Masks */ + + +/* BEE - Peripheral instance base addresses */ +/** Peripheral BEE base address */ +#define BEE_BASE (0x403EC000u) +/** Peripheral BEE base pointer */ +#define BEE ((BEE_Type *)BEE_BASE) +/** Array initializer of BEE peripheral base addresses */ +#define BEE_BASE_ADDRS { BEE_BASE } +/** Array initializer of BEE peripheral base pointers */ +#define BEE_BASE_PTRS { BEE } + +/*! + * @} + */ /* end of group BEE_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- CAN Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup CAN_Peripheral_Access_Layer CAN Peripheral Access Layer + * @{ + */ + +/** CAN - Register Layout Typedef */ +typedef struct { + __IO uint32_t MCR; /**< Module Configuration Register, offset: 0x0 */ + __IO uint32_t CTRL1; /**< Control 1 Register, offset: 0x4 */ + __IO uint32_t TIMER; /**< Free Running Timer Register, offset: 0x8 */ + uint8_t RESERVED_0[4]; + __IO uint32_t RXMGMASK; /**< Rx Mailboxes Global Mask Register, offset: 0x10 */ + __IO uint32_t RX14MASK; /**< Rx Buffer 14 Mask Register, offset: 0x14 */ + __IO uint32_t RX15MASK; /**< Rx Buffer 15 Mask Register, offset: 0x18 */ + __IO uint32_t ECR; /**< Error Counter Register, offset: 0x1C */ + __IO uint32_t ESR1; /**< Error and Status 1 Register, offset: 0x20 */ + __IO uint32_t IMASK2; /**< Interrupt Masks 2 Register, offset: 0x24 */ + __IO uint32_t IMASK1; /**< Interrupt Masks 1 Register, offset: 0x28 */ + __IO uint32_t IFLAG2; /**< Interrupt Flags 2 Register, offset: 0x2C */ + __IO uint32_t IFLAG1; /**< Interrupt Flags 1 Register, offset: 0x30 */ + __IO uint32_t CTRL2; /**< Control 2 Register, offset: 0x34 */ + __I uint32_t ESR2; /**< Error and Status 2 Register, offset: 0x38 */ + uint8_t RESERVED_1[8]; + __I uint32_t CRCR; /**< CRC Register, offset: 0x44 */ + __IO uint32_t RXFGMASK; /**< Rx FIFO Global Mask Register, offset: 0x48 */ + __I uint32_t RXFIR; /**< Rx FIFO Information Register, offset: 0x4C */ + uint8_t RESERVED_2[8]; + __I uint32_t DBG1; /**< Debug 1 register, offset: 0x58 */ + __I uint32_t DBG2; /**< Debug 2 register, offset: 0x5C */ + uint8_t RESERVED_3[32]; + struct { /* offset: 0x80, array step: 0x10 */ + __IO uint32_t CS; /**< Message Buffer 0 CS Register..Message Buffer 63 CS Register, array offset: 0x80, array step: 0x10 */ + __IO uint32_t ID; /**< Message Buffer 0 ID Register..Message Buffer 63 ID Register, array offset: 0x84, array step: 0x10 */ + __IO uint32_t WORD0; /**< Message Buffer 0 WORD0 Register..Message Buffer 63 WORD0 Register, array offset: 0x88, array step: 0x10 */ + __IO uint32_t WORD1; /**< Message Buffer 0 WORD1 Register..Message Buffer 63 WORD1 Register, array offset: 0x8C, array step: 0x10 */ + } MB[64]; + uint8_t RESERVED_4[1024]; + __IO uint32_t RXIMR[64]; /**< Rx Individual Mask Registers, array offset: 0x880, array step: 0x4 */ + uint8_t RESERVED_5[96]; + __IO uint32_t GFWR; /**< Glitch Filter Width Registers, offset: 0x9E0 */ +} CAN_Type; + +/* ---------------------------------------------------------------------------- + -- CAN Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup CAN_Register_Masks CAN Register Masks + * @{ + */ + +/*! @name MCR - Module Configuration Register */ +/*! @{ */ +#define CAN_MCR_MAXMB_MASK (0x7FU) +#define CAN_MCR_MAXMB_SHIFT (0U) +#define CAN_MCR_MAXMB(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_MAXMB_SHIFT)) & CAN_MCR_MAXMB_MASK) +#define CAN_MCR_IDAM_MASK (0x300U) +#define CAN_MCR_IDAM_SHIFT (8U) +/*! IDAM + * 0b00..Format A One full ID (standard or extended) per ID filter Table element. + * 0b01..Format B Two full standard IDs or two partial 14-bit extended IDs per ID filter Table element. + * 0b10..Format C Four partial 8-bit IDs (standard or extended) per ID filter Table element. + * 0b11..Format D All frames rejected. + */ +#define CAN_MCR_IDAM(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_IDAM_SHIFT)) & CAN_MCR_IDAM_MASK) +#define CAN_MCR_AEN_MASK (0x1000U) +#define CAN_MCR_AEN_SHIFT (12U) +/*! AEN + * 0b1..Abort enabled + * 0b0..Abort disabled + */ +#define CAN_MCR_AEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_AEN_SHIFT)) & CAN_MCR_AEN_MASK) +#define CAN_MCR_LPRIOEN_MASK (0x2000U) +#define CAN_MCR_LPRIOEN_SHIFT (13U) +/*! LPRIOEN + * 0b1..Local Priority enabled + * 0b0..Local Priority disabled + */ +#define CAN_MCR_LPRIOEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_LPRIOEN_SHIFT)) & CAN_MCR_LPRIOEN_MASK) +#define CAN_MCR_IRMQ_MASK (0x10000U) +#define CAN_MCR_IRMQ_SHIFT (16U) +/*! IRMQ + * 0b1..Individual Rx masking and queue feature are enabled. + * 0b0..Individual Rx masking and queue feature are disabled.For backward compatibility, the reading of C/S word locks the MB even if it is EMPTY. + */ +#define CAN_MCR_IRMQ(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_IRMQ_SHIFT)) & CAN_MCR_IRMQ_MASK) +#define CAN_MCR_SRXDIS_MASK (0x20000U) +#define CAN_MCR_SRXDIS_SHIFT (17U) +/*! SRXDIS + * 0b1..Self reception disabled + * 0b0..Self reception enabled + */ +#define CAN_MCR_SRXDIS(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_SRXDIS_SHIFT)) & CAN_MCR_SRXDIS_MASK) +#define CAN_MCR_WAKSRC_MASK (0x80000U) +#define CAN_MCR_WAKSRC_SHIFT (19U) +/*! WAKSRC + * 0b1..FLEXCAN uses the filtered FLEXCAN_RX input to detect recessive to dominant edges on the CAN bus + * 0b0..FLEXCAN uses the unfiltered FLEXCAN_RX input to detect recessive to dominant edges on the CAN bus. + */ +#define CAN_MCR_WAKSRC(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_WAKSRC_SHIFT)) & CAN_MCR_WAKSRC_MASK) +#define CAN_MCR_LPMACK_MASK (0x100000U) +#define CAN_MCR_LPMACK_SHIFT (20U) +/*! LPMACK + * 0b1..FLEXCAN is either in Disable Mode, or Stop mode + * 0b0..FLEXCAN not in any of the low power modes + */ +#define CAN_MCR_LPMACK(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_LPMACK_SHIFT)) & CAN_MCR_LPMACK_MASK) +#define CAN_MCR_WRNEN_MASK (0x200000U) +#define CAN_MCR_WRNEN_SHIFT (21U) +/*! WRNEN + * 0b1..TWRN_INT and RWRN_INT bits are set when the respective error counter transition from <96 to >= 96. + * 0b0..TWRN_INT and RWRN_INT bits are zero, independent of the values in the error counters. + */ +#define CAN_MCR_WRNEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_WRNEN_SHIFT)) & CAN_MCR_WRNEN_MASK) +#define CAN_MCR_SLFWAK_MASK (0x400000U) +#define CAN_MCR_SLFWAK_SHIFT (22U) +/*! SLFWAK + * 0b1..FLEXCAN Self Wake Up feature is enabled + * 0b0..FLEXCAN Self Wake Up feature is disabled + */ +#define CAN_MCR_SLFWAK(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_SLFWAK_SHIFT)) & CAN_MCR_SLFWAK_MASK) +#define CAN_MCR_SUPV_MASK (0x800000U) +#define CAN_MCR_SUPV_SHIFT (23U) +/*! SUPV + * 0b1..FlexCAN is in Supervisor Mode. Affected registers allow only Supervisor access. Unrestricted access behaves as though the access was done to an unimplemented register location + * 0b0..FlexCAN is in User Mode. Affected registers allow both Supervisor and Unrestricted accesses + */ +#define CAN_MCR_SUPV(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_SUPV_SHIFT)) & CAN_MCR_SUPV_MASK) +#define CAN_MCR_FRZACK_MASK (0x1000000U) +#define CAN_MCR_FRZACK_SHIFT (24U) +/*! FRZACK + * 0b1..FLEXCAN in Freeze Mode, prescaler stopped + * 0b0..FLEXCAN not in Freeze Mode, prescaler running + */ +#define CAN_MCR_FRZACK(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_FRZACK_SHIFT)) & CAN_MCR_FRZACK_MASK) +#define CAN_MCR_SOFTRST_MASK (0x2000000U) +#define CAN_MCR_SOFTRST_SHIFT (25U) +/*! SOFTRST + * 0b1..Reset the registers + * 0b0..No reset request + */ +#define CAN_MCR_SOFTRST(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_SOFTRST_SHIFT)) & CAN_MCR_SOFTRST_MASK) +#define CAN_MCR_WAKMSK_MASK (0x4000000U) +#define CAN_MCR_WAKMSK_SHIFT (26U) +/*! WAKMSK + * 0b1..Wake Up Interrupt is enabled + * 0b0..Wake Up Interrupt is disabled + */ +#define CAN_MCR_WAKMSK(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_WAKMSK_SHIFT)) & CAN_MCR_WAKMSK_MASK) +#define CAN_MCR_NOTRDY_MASK (0x8000000U) +#define CAN_MCR_NOTRDY_SHIFT (27U) +/*! NOTRDY + * 0b1..FLEXCAN module is either in Disable Mode, Stop Mode or Freeze Mode + * 0b0..FLEXCAN module is either in Normal Mode, Listen-Only Mode or Loop-Back Mode + */ +#define CAN_MCR_NOTRDY(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_NOTRDY_SHIFT)) & CAN_MCR_NOTRDY_MASK) +#define CAN_MCR_HALT_MASK (0x10000000U) +#define CAN_MCR_HALT_SHIFT (28U) +/*! HALT + * 0b1..Enters Freeze Mode if the FRZ bit is asserted. + * 0b0..No Freeze Mode request. + */ +#define CAN_MCR_HALT(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_HALT_SHIFT)) & CAN_MCR_HALT_MASK) +#define CAN_MCR_RFEN_MASK (0x20000000U) +#define CAN_MCR_RFEN_SHIFT (29U) +/*! RFEN + * 0b1..FIFO enabled + * 0b0..FIFO not enabled + */ +#define CAN_MCR_RFEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_RFEN_SHIFT)) & CAN_MCR_RFEN_MASK) +#define CAN_MCR_FRZ_MASK (0x40000000U) +#define CAN_MCR_FRZ_SHIFT (30U) +/*! FRZ + * 0b1..Enabled to enter Freeze Mode + * 0b0..Not enabled to enter Freeze Mode + */ +#define CAN_MCR_FRZ(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_FRZ_SHIFT)) & CAN_MCR_FRZ_MASK) +#define CAN_MCR_MDIS_MASK (0x80000000U) +#define CAN_MCR_MDIS_SHIFT (31U) +/*! MDIS + * 0b1..Disable the FLEXCAN module + * 0b0..Enable the FLEXCAN module + */ +#define CAN_MCR_MDIS(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_MDIS_SHIFT)) & CAN_MCR_MDIS_MASK) +/*! @} */ + +/*! @name CTRL1 - Control 1 Register */ +/*! @{ */ +#define CAN_CTRL1_PROPSEG_MASK (0x7U) +#define CAN_CTRL1_PROPSEG_SHIFT (0U) +#define CAN_CTRL1_PROPSEG(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_PROPSEG_SHIFT)) & CAN_CTRL1_PROPSEG_MASK) +#define CAN_CTRL1_LOM_MASK (0x8U) +#define CAN_CTRL1_LOM_SHIFT (3U) +/*! LOM + * 0b1..FLEXCAN module operates in Listen Only Mode + * 0b0..Listen Only Mode is deactivated + */ +#define CAN_CTRL1_LOM(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_LOM_SHIFT)) & CAN_CTRL1_LOM_MASK) +#define CAN_CTRL1_LBUF_MASK (0x10U) +#define CAN_CTRL1_LBUF_SHIFT (4U) +/*! LBUF + * 0b1..Lowest number buffer is transmitted first + * 0b0..Buffer with highest priority is transmitted first + */ +#define CAN_CTRL1_LBUF(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_LBUF_SHIFT)) & CAN_CTRL1_LBUF_MASK) +#define CAN_CTRL1_TSYN_MASK (0x20U) +#define CAN_CTRL1_TSYN_SHIFT (5U) +/*! TSYN + * 0b1..Timer Sync feature enabled + * 0b0..Timer Sync feature disabled + */ +#define CAN_CTRL1_TSYN(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_TSYN_SHIFT)) & CAN_CTRL1_TSYN_MASK) +#define CAN_CTRL1_BOFFREC_MASK (0x40U) +#define CAN_CTRL1_BOFFREC_SHIFT (6U) +/*! BOFFREC + * 0b1..Automatic recovering from Bus Off state disabled + * 0b0..Automatic recovering from Bus Off state enabled, according to CAN Spec 2.0 part B + */ +#define CAN_CTRL1_BOFFREC(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_BOFFREC_SHIFT)) & CAN_CTRL1_BOFFREC_MASK) +#define CAN_CTRL1_SMP_MASK (0x80U) +#define CAN_CTRL1_SMP_SHIFT (7U) +/*! SMP + * 0b1..Three samples are used to determine the value of the received bit: the regular one (sample point) and 2 preceding samples, a majority rule is used + * 0b0..Just one sample is used to determine the bit value + */ +#define CAN_CTRL1_SMP(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_SMP_SHIFT)) & CAN_CTRL1_SMP_MASK) +#define CAN_CTRL1_RWRNMSK_MASK (0x400U) +#define CAN_CTRL1_RWRNMSK_SHIFT (10U) +/*! RWRNMSK + * 0b1..Rx Warning Interrupt enabled + * 0b0..Rx Warning Interrupt disabled + */ +#define CAN_CTRL1_RWRNMSK(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_RWRNMSK_SHIFT)) & CAN_CTRL1_RWRNMSK_MASK) +#define CAN_CTRL1_TWRNMSK_MASK (0x800U) +#define CAN_CTRL1_TWRNMSK_SHIFT (11U) +/*! TWRNMSK + * 0b1..Tx Warning Interrupt enabled + * 0b0..Tx Warning Interrupt disabled + */ +#define CAN_CTRL1_TWRNMSK(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_TWRNMSK_SHIFT)) & CAN_CTRL1_TWRNMSK_MASK) +#define CAN_CTRL1_LPB_MASK (0x1000U) +#define CAN_CTRL1_LPB_SHIFT (12U) +/*! LPB + * 0b1..Loop Back enabled + * 0b0..Loop Back disabled + */ +#define CAN_CTRL1_LPB(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_LPB_SHIFT)) & CAN_CTRL1_LPB_MASK) +#define CAN_CTRL1_ERRMSK_MASK (0x4000U) +#define CAN_CTRL1_ERRMSK_SHIFT (14U) +/*! ERRMSK + * 0b1..Error interrupt enabled + * 0b0..Error interrupt disabled + */ +#define CAN_CTRL1_ERRMSK(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_ERRMSK_SHIFT)) & CAN_CTRL1_ERRMSK_MASK) +#define CAN_CTRL1_BOFFMSK_MASK (0x8000U) +#define CAN_CTRL1_BOFFMSK_SHIFT (15U) +/*! BOFFMSK + * 0b1..Bus Off interrupt enabled + * 0b0..Bus Off interrupt disabled + */ +#define CAN_CTRL1_BOFFMSK(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_BOFFMSK_SHIFT)) & CAN_CTRL1_BOFFMSK_MASK) +#define CAN_CTRL1_PSEG2_MASK (0x70000U) +#define CAN_CTRL1_PSEG2_SHIFT (16U) +#define CAN_CTRL1_PSEG2(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_PSEG2_SHIFT)) & CAN_CTRL1_PSEG2_MASK) +#define CAN_CTRL1_PSEG1_MASK (0x380000U) +#define CAN_CTRL1_PSEG1_SHIFT (19U) +#define CAN_CTRL1_PSEG1(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_PSEG1_SHIFT)) & CAN_CTRL1_PSEG1_MASK) +#define CAN_CTRL1_RJW_MASK (0xC00000U) +#define CAN_CTRL1_RJW_SHIFT (22U) +#define CAN_CTRL1_RJW(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_RJW_SHIFT)) & CAN_CTRL1_RJW_MASK) +#define CAN_CTRL1_PRESDIV_MASK (0xFF000000U) +#define CAN_CTRL1_PRESDIV_SHIFT (24U) +#define CAN_CTRL1_PRESDIV(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_PRESDIV_SHIFT)) & CAN_CTRL1_PRESDIV_MASK) +/*! @} */ + +/*! @name TIMER - Free Running Timer Register */ +/*! @{ */ +#define CAN_TIMER_TIMER_MASK (0xFFFFU) +#define CAN_TIMER_TIMER_SHIFT (0U) +#define CAN_TIMER_TIMER(x) (((uint32_t)(((uint32_t)(x)) << CAN_TIMER_TIMER_SHIFT)) & CAN_TIMER_TIMER_MASK) +/*! @} */ + +/*! @name RXMGMASK - Rx Mailboxes Global Mask Register */ +/*! @{ */ +#define CAN_RXMGMASK_MG_MASK (0xFFFFFFFFU) +#define CAN_RXMGMASK_MG_SHIFT (0U) +/*! MG + * 0b00000000000000000000000000000001..The corresponding bit in the filter is checked against the one received + * 0b00000000000000000000000000000000..the corresponding bit in the filter is "don't care" + */ +#define CAN_RXMGMASK_MG(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXMGMASK_MG_SHIFT)) & CAN_RXMGMASK_MG_MASK) +/*! @} */ + +/*! @name RX14MASK - Rx Buffer 14 Mask Register */ +/*! @{ */ +#define CAN_RX14MASK_RX14M_MASK (0xFFFFFFFFU) +#define CAN_RX14MASK_RX14M_SHIFT (0U) +/*! RX14M + * 0b00000000000000000000000000000001..The corresponding bit in the filter is checked + * 0b00000000000000000000000000000000..the corresponding bit in the filter is "don't care" + */ +#define CAN_RX14MASK_RX14M(x) (((uint32_t)(((uint32_t)(x)) << CAN_RX14MASK_RX14M_SHIFT)) & CAN_RX14MASK_RX14M_MASK) +/*! @} */ + +/*! @name RX15MASK - Rx Buffer 15 Mask Register */ +/*! @{ */ +#define CAN_RX15MASK_RX15M_MASK (0xFFFFFFFFU) +#define CAN_RX15MASK_RX15M_SHIFT (0U) +/*! RX15M + * 0b00000000000000000000000000000001..The corresponding bit in the filter is checked + * 0b00000000000000000000000000000000..the corresponding bit in the filter is "don't care" + */ +#define CAN_RX15MASK_RX15M(x) (((uint32_t)(((uint32_t)(x)) << CAN_RX15MASK_RX15M_SHIFT)) & CAN_RX15MASK_RX15M_MASK) +/*! @} */ + +/*! @name ECR - Error Counter Register */ +/*! @{ */ +#define CAN_ECR_TX_ERR_COUNTER_MASK (0xFFU) +#define CAN_ECR_TX_ERR_COUNTER_SHIFT (0U) +#define CAN_ECR_TX_ERR_COUNTER(x) (((uint32_t)(((uint32_t)(x)) << CAN_ECR_TX_ERR_COUNTER_SHIFT)) & CAN_ECR_TX_ERR_COUNTER_MASK) +#define CAN_ECR_RX_ERR_COUNTER_MASK (0xFF00U) +#define CAN_ECR_RX_ERR_COUNTER_SHIFT (8U) +#define CAN_ECR_RX_ERR_COUNTER(x) (((uint32_t)(((uint32_t)(x)) << CAN_ECR_RX_ERR_COUNTER_SHIFT)) & CAN_ECR_RX_ERR_COUNTER_MASK) +/*! @} */ + +/*! @name ESR1 - Error and Status 1 Register */ +/*! @{ */ +#define CAN_ESR1_WAKINT_MASK (0x1U) +#define CAN_ESR1_WAKINT_SHIFT (0U) +/*! WAKINT + * 0b1..Indicates a recessive to dominant transition received on the CAN bus when the FLEXCAN module is in Stop Mode + * 0b0..No such occurrence + */ +#define CAN_ESR1_WAKINT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_WAKINT_SHIFT)) & CAN_ESR1_WAKINT_MASK) +#define CAN_ESR1_ERRINT_MASK (0x2U) +#define CAN_ESR1_ERRINT_SHIFT (1U) +/*! ERRINT + * 0b1..Indicates setting of any Error Bit in the Error and Status Register + * 0b0..No such occurrence + */ +#define CAN_ESR1_ERRINT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_ERRINT_SHIFT)) & CAN_ESR1_ERRINT_MASK) +#define CAN_ESR1_BOFFINT_MASK (0x4U) +#define CAN_ESR1_BOFFINT_SHIFT (2U) +/*! BOFFINT + * 0b1..FLEXCAN module entered 'Bus Off' state + * 0b0..No such occurrence + */ +#define CAN_ESR1_BOFFINT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_BOFFINT_SHIFT)) & CAN_ESR1_BOFFINT_MASK) +#define CAN_ESR1_RX_MASK (0x8U) +#define CAN_ESR1_RX_SHIFT (3U) +/*! RX + * 0b1..FLEXCAN is transmitting a message + * 0b0..FLEXCAN is receiving a message + */ +#define CAN_ESR1_RX(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_RX_SHIFT)) & CAN_ESR1_RX_MASK) +#define CAN_ESR1_FLTCONF_MASK (0x30U) +#define CAN_ESR1_FLTCONF_SHIFT (4U) +/*! FLTCONF + * 0b00..Error Active + * 0b01..Error Passive + * 0b1x..Bus off + */ +#define CAN_ESR1_FLTCONF(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_FLTCONF_SHIFT)) & CAN_ESR1_FLTCONF_MASK) +#define CAN_ESR1_TX_MASK (0x40U) +#define CAN_ESR1_TX_SHIFT (6U) +/*! TX + * 0b1..FLEXCAN is transmitting a message + * 0b0..FLEXCAN is receiving a message + */ +#define CAN_ESR1_TX(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_TX_SHIFT)) & CAN_ESR1_TX_MASK) +#define CAN_ESR1_IDLE_MASK (0x80U) +#define CAN_ESR1_IDLE_SHIFT (7U) +/*! IDLE + * 0b1..CAN bus is now IDLE + * 0b0..No such occurrence + */ +#define CAN_ESR1_IDLE(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_IDLE_SHIFT)) & CAN_ESR1_IDLE_MASK) +#define CAN_ESR1_RXWRN_MASK (0x100U) +#define CAN_ESR1_RXWRN_SHIFT (8U) +/*! RXWRN + * 0b1..Rx_Err_Counter >= 96 + * 0b0..No such occurrence + */ +#define CAN_ESR1_RXWRN(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_RXWRN_SHIFT)) & CAN_ESR1_RXWRN_MASK) +#define CAN_ESR1_TXWRN_MASK (0x200U) +#define CAN_ESR1_TXWRN_SHIFT (9U) +/*! TXWRN + * 0b1..TX_Err_Counter >= 96 + * 0b0..No such occurrence + */ +#define CAN_ESR1_TXWRN(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_TXWRN_SHIFT)) & CAN_ESR1_TXWRN_MASK) +#define CAN_ESR1_STFERR_MASK (0x400U) +#define CAN_ESR1_STFERR_SHIFT (10U) +/*! STFERR + * 0b1..A Stuffing Error occurred since last read of this register. + * 0b0..No such occurrence. + */ +#define CAN_ESR1_STFERR(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_STFERR_SHIFT)) & CAN_ESR1_STFERR_MASK) +#define CAN_ESR1_FRMERR_MASK (0x800U) +#define CAN_ESR1_FRMERR_SHIFT (11U) +/*! FRMERR + * 0b1..A Form Error occurred since last read of this register + * 0b0..No such occurrence + */ +#define CAN_ESR1_FRMERR(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_FRMERR_SHIFT)) & CAN_ESR1_FRMERR_MASK) +#define CAN_ESR1_CRCERR_MASK (0x1000U) +#define CAN_ESR1_CRCERR_SHIFT (12U) +/*! CRCERR + * 0b1..A CRC error occurred since last read of this register. + * 0b0..No such occurrence + */ +#define CAN_ESR1_CRCERR(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_CRCERR_SHIFT)) & CAN_ESR1_CRCERR_MASK) +#define CAN_ESR1_ACKERR_MASK (0x2000U) +#define CAN_ESR1_ACKERR_SHIFT (13U) +/*! ACKERR + * 0b1..An ACK error occurred since last read of this register + * 0b0..No such occurrence + */ +#define CAN_ESR1_ACKERR(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_ACKERR_SHIFT)) & CAN_ESR1_ACKERR_MASK) +#define CAN_ESR1_BIT0ERR_MASK (0x4000U) +#define CAN_ESR1_BIT0ERR_SHIFT (14U) +/*! BIT0ERR + * 0b1..At least one bit sent as dominant is received as recessive + * 0b0..No such occurrence + */ +#define CAN_ESR1_BIT0ERR(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_BIT0ERR_SHIFT)) & CAN_ESR1_BIT0ERR_MASK) +#define CAN_ESR1_BIT1ERR_MASK (0x8000U) +#define CAN_ESR1_BIT1ERR_SHIFT (15U) +/*! BIT1ERR + * 0b1..At least one bit sent as recessive is received as dominant + * 0b0..No such occurrence + */ +#define CAN_ESR1_BIT1ERR(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_BIT1ERR_SHIFT)) & CAN_ESR1_BIT1ERR_MASK) +#define CAN_ESR1_RWRNINT_MASK (0x10000U) +#define CAN_ESR1_RWRNINT_SHIFT (16U) +/*! RWRNINT + * 0b1..The Rx error counter transition from < 96 to >= 96 + * 0b0..No such occurrence + */ +#define CAN_ESR1_RWRNINT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_RWRNINT_SHIFT)) & CAN_ESR1_RWRNINT_MASK) +#define CAN_ESR1_TWRNINT_MASK (0x20000U) +#define CAN_ESR1_TWRNINT_SHIFT (17U) +/*! TWRNINT + * 0b1..The Tx error counter transition from < 96 to >= 96 + * 0b0..No such occurrence + */ +#define CAN_ESR1_TWRNINT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_TWRNINT_SHIFT)) & CAN_ESR1_TWRNINT_MASK) +#define CAN_ESR1_SYNCH_MASK (0x40000U) +#define CAN_ESR1_SYNCH_SHIFT (18U) +/*! SYNCH + * 0b1..FlexCAN is synchronized to the CAN bus + * 0b0..FlexCAN is not synchronized to the CAN bus + */ +#define CAN_ESR1_SYNCH(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_SYNCH_SHIFT)) & CAN_ESR1_SYNCH_MASK) +/*! @} */ + +/*! @name IMASK2 - Interrupt Masks 2 Register */ +/*! @{ */ +#define CAN_IMASK2_BUFHM_MASK (0xFFFFFFFFU) +#define CAN_IMASK2_BUFHM_SHIFT (0U) +/*! BUFHM + * 0b00000000000000000000000000000001..The corresponding buffer Interrupt is enabled + * 0b00000000000000000000000000000000..The corresponding buffer Interrupt is disabled + */ +#define CAN_IMASK2_BUFHM(x) (((uint32_t)(((uint32_t)(x)) << CAN_IMASK2_BUFHM_SHIFT)) & CAN_IMASK2_BUFHM_MASK) +/*! @} */ + +/*! @name IMASK1 - Interrupt Masks 1 Register */ +/*! @{ */ +#define CAN_IMASK1_BUFLM_MASK (0xFFFFFFFFU) +#define CAN_IMASK1_BUFLM_SHIFT (0U) +/*! BUFLM + * 0b00000000000000000000000000000001..The corresponding buffer Interrupt is enabled + * 0b00000000000000000000000000000000..The corresponding buffer Interrupt is disabled + */ +#define CAN_IMASK1_BUFLM(x) (((uint32_t)(((uint32_t)(x)) << CAN_IMASK1_BUFLM_SHIFT)) & CAN_IMASK1_BUFLM_MASK) +/*! @} */ + +/*! @name IFLAG2 - Interrupt Flags 2 Register */ +/*! @{ */ +#define CAN_IFLAG2_BUFHI_MASK (0xFFFFFFFFU) +#define CAN_IFLAG2_BUFHI_SHIFT (0U) +/*! BUFHI + * 0b00000000000000000000000000000001..The corresponding buffer has successfully completed transmission or reception + * 0b00000000000000000000000000000000..No such occurrence + */ +#define CAN_IFLAG2_BUFHI(x) (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG2_BUFHI_SHIFT)) & CAN_IFLAG2_BUFHI_MASK) +/*! @} */ + +/*! @name IFLAG1 - Interrupt Flags 1 Register */ +/*! @{ */ +#define CAN_IFLAG1_BUF4TO0I_MASK (0x1FU) +#define CAN_IFLAG1_BUF4TO0I_SHIFT (0U) +/*! BUF4TO0I + * 0b00001..Corresponding MB completed transmission/reception + * 0b00000..No such occurrence + */ +#define CAN_IFLAG1_BUF4TO0I(x) (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF4TO0I_SHIFT)) & CAN_IFLAG1_BUF4TO0I_MASK) +#define CAN_IFLAG1_BUF5I_MASK (0x20U) +#define CAN_IFLAG1_BUF5I_SHIFT (5U) +/*! BUF5I + * 0b1..MB5 completed transmission/reception or frames available in the FIFO + * 0b0..No such occurrence + */ +#define CAN_IFLAG1_BUF5I(x) (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF5I_SHIFT)) & CAN_IFLAG1_BUF5I_MASK) +#define CAN_IFLAG1_BUF6I_MASK (0x40U) +#define CAN_IFLAG1_BUF6I_SHIFT (6U) +/*! BUF6I + * 0b1..MB6 completed transmission/reception or FIFO almost full + * 0b0..No such occurrence + */ +#define CAN_IFLAG1_BUF6I(x) (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF6I_SHIFT)) & CAN_IFLAG1_BUF6I_MASK) +#define CAN_IFLAG1_BUF7I_MASK (0x80U) +#define CAN_IFLAG1_BUF7I_SHIFT (7U) +/*! BUF7I + * 0b1..MB7 completed transmission/reception or FIFO overflow + * 0b0..No such occurrence + */ +#define CAN_IFLAG1_BUF7I(x) (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF7I_SHIFT)) & CAN_IFLAG1_BUF7I_MASK) +#define CAN_IFLAG1_BUF31TO8I_MASK (0xFFFFFF00U) +#define CAN_IFLAG1_BUF31TO8I_SHIFT (8U) +/*! BUF31TO8I + * 0b000000000000000000000001..The corresponding MB has successfully completed transmission or reception + * 0b000000000000000000000000..No such occurrence + */ +#define CAN_IFLAG1_BUF31TO8I(x) (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF31TO8I_SHIFT)) & CAN_IFLAG1_BUF31TO8I_MASK) +/*! @} */ + +/*! @name CTRL2 - Control 2 Register */ +/*! @{ */ +#define CAN_CTRL2_EACEN_MASK (0x10000U) +#define CAN_CTRL2_EACEN_SHIFT (16U) +/*! EACEN + * 0b1..Enables the comparison of both Rx Mailbox filter's IDE and RTR bit with their corresponding bits within the incoming frame. Mask bits do apply. + * 0b0..Rx Mailbox filter's IDE bit is always compared and RTR is never compared despite mask bits. + */ +#define CAN_CTRL2_EACEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_EACEN_SHIFT)) & CAN_CTRL2_EACEN_MASK) +#define CAN_CTRL2_RRS_MASK (0x20000U) +#define CAN_CTRL2_RRS_SHIFT (17U) +/*! RRS + * 0b1..Remote Request Frame is stored + * 0b0..Remote Response Frame is generated + */ +#define CAN_CTRL2_RRS(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_RRS_SHIFT)) & CAN_CTRL2_RRS_MASK) +#define CAN_CTRL2_MRP_MASK (0x40000U) +#define CAN_CTRL2_MRP_SHIFT (18U) +/*! MRP + * 0b1..Matching starts from Mailboxes and continues on Rx FIFO + * 0b0..Matching starts from Rx FIFO and continues on Mailboxes + */ +#define CAN_CTRL2_MRP(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_MRP_SHIFT)) & CAN_CTRL2_MRP_MASK) +#define CAN_CTRL2_TASD_MASK (0xF80000U) +#define CAN_CTRL2_TASD_SHIFT (19U) +#define CAN_CTRL2_TASD(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_TASD_SHIFT)) & CAN_CTRL2_TASD_MASK) +#define CAN_CTRL2_RFFN_MASK (0xF000000U) +#define CAN_CTRL2_RFFN_SHIFT (24U) +#define CAN_CTRL2_RFFN(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_RFFN_SHIFT)) & CAN_CTRL2_RFFN_MASK) +#define CAN_CTRL2_WRMFRZ_MASK (0x10000000U) +#define CAN_CTRL2_WRMFRZ_SHIFT (28U) +/*! WRMFRZ + * 0b1..Enable unrestricted write access to FlexCAN memory + * 0b0..Keep the write access restricted in some regions of FlexCAN memory + */ +#define CAN_CTRL2_WRMFRZ(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_WRMFRZ_SHIFT)) & CAN_CTRL2_WRMFRZ_MASK) +/*! @} */ + +/*! @name ESR2 - Error and Status 2 Register */ +/*! @{ */ +#define CAN_ESR2_IMB_MASK (0x2000U) +#define CAN_ESR2_IMB_SHIFT (13U) +/*! IMB + * 0b1..If ESR2[VPS] is asserted, there is at least one inactive Mailbox. LPTM content is the number of the first one. + * 0b0..If ESR2[VPS] is asserted, the ESR2[LPTM] is not an inactive Mailbox. + */ +#define CAN_ESR2_IMB(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR2_IMB_SHIFT)) & CAN_ESR2_IMB_MASK) +#define CAN_ESR2_VPS_MASK (0x4000U) +#define CAN_ESR2_VPS_SHIFT (14U) +/*! VPS + * 0b1..Contents of IMB and LPTM are valid + * 0b0..Contents of IMB and LPTM are invalid + */ +#define CAN_ESR2_VPS(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR2_VPS_SHIFT)) & CAN_ESR2_VPS_MASK) +#define CAN_ESR2_LPTM_MASK (0x7F0000U) +#define CAN_ESR2_LPTM_SHIFT (16U) +#define CAN_ESR2_LPTM(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR2_LPTM_SHIFT)) & CAN_ESR2_LPTM_MASK) +/*! @} */ + +/*! @name CRCR - CRC Register */ +/*! @{ */ +#define CAN_CRCR_TXCRC_MASK (0x7FFFU) +#define CAN_CRCR_TXCRC_SHIFT (0U) +#define CAN_CRCR_TXCRC(x) (((uint32_t)(((uint32_t)(x)) << CAN_CRCR_TXCRC_SHIFT)) & CAN_CRCR_TXCRC_MASK) +#define CAN_CRCR_MBCRC_MASK (0x7F0000U) +#define CAN_CRCR_MBCRC_SHIFT (16U) +#define CAN_CRCR_MBCRC(x) (((uint32_t)(((uint32_t)(x)) << CAN_CRCR_MBCRC_SHIFT)) & CAN_CRCR_MBCRC_MASK) +/*! @} */ + +/*! @name RXFGMASK - Rx FIFO Global Mask Register */ +/*! @{ */ +#define CAN_RXFGMASK_FGM_MASK (0xFFFFFFFFU) +#define CAN_RXFGMASK_FGM_SHIFT (0U) +/*! FGM + * 0b00000000000000000000000000000001..The corresponding bit in the filter is checked + * 0b00000000000000000000000000000000..The corresponding bit in the filter is "don't care" + */ +#define CAN_RXFGMASK_FGM(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXFGMASK_FGM_SHIFT)) & CAN_RXFGMASK_FGM_MASK) +/*! @} */ + +/*! @name RXFIR - Rx FIFO Information Register */ +/*! @{ */ +#define CAN_RXFIR_IDHIT_MASK (0x1FFU) +#define CAN_RXFIR_IDHIT_SHIFT (0U) +#define CAN_RXFIR_IDHIT(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXFIR_IDHIT_SHIFT)) & CAN_RXFIR_IDHIT_MASK) +/*! @} */ + +/*! @name DBG1 - Debug 1 register */ +/*! @{ */ +#define CAN_DBG1_CFSM_MASK (0x3FU) +#define CAN_DBG1_CFSM_SHIFT (0U) +#define CAN_DBG1_CFSM(x) (((uint32_t)(((uint32_t)(x)) << CAN_DBG1_CFSM_SHIFT)) & CAN_DBG1_CFSM_MASK) +#define CAN_DBG1_CBN_MASK (0x1F000000U) +#define CAN_DBG1_CBN_SHIFT (24U) +#define CAN_DBG1_CBN(x) (((uint32_t)(((uint32_t)(x)) << CAN_DBG1_CBN_SHIFT)) & CAN_DBG1_CBN_MASK) +/*! @} */ + +/*! @name DBG2 - Debug 2 register */ +/*! @{ */ +#define CAN_DBG2_RMP_MASK (0x7FU) +#define CAN_DBG2_RMP_SHIFT (0U) +#define CAN_DBG2_RMP(x) (((uint32_t)(((uint32_t)(x)) << CAN_DBG2_RMP_SHIFT)) & CAN_DBG2_RMP_MASK) +#define CAN_DBG2_MPP_MASK (0x80U) +#define CAN_DBG2_MPP_SHIFT (7U) +/*! MPP - Matching Process in Progress + * 0b0..No matching process ongoing. + * 0b1..Matching process is in progress. + */ +#define CAN_DBG2_MPP(x) (((uint32_t)(((uint32_t)(x)) << CAN_DBG2_MPP_SHIFT)) & CAN_DBG2_MPP_MASK) +#define CAN_DBG2_TAP_MASK (0x7F00U) +#define CAN_DBG2_TAP_SHIFT (8U) +#define CAN_DBG2_TAP(x) (((uint32_t)(((uint32_t)(x)) << CAN_DBG2_TAP_SHIFT)) & CAN_DBG2_TAP_MASK) +#define CAN_DBG2_APP_MASK (0x8000U) +#define CAN_DBG2_APP_SHIFT (15U) +/*! APP - Arbitration Process in Progress + * 0b0..No matching process ongoing. + * 0b1..Matching process is in progress. + */ +#define CAN_DBG2_APP(x) (((uint32_t)(((uint32_t)(x)) << CAN_DBG2_APP_SHIFT)) & CAN_DBG2_APP_MASK) +/*! @} */ + +/*! @name CS - Message Buffer 0 CS Register..Message Buffer 63 CS Register */ +/*! @{ */ +#define CAN_CS_TIME_STAMP_MASK (0xFFFFU) +#define CAN_CS_TIME_STAMP_SHIFT (0U) +#define CAN_CS_TIME_STAMP(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_TIME_STAMP_SHIFT)) & CAN_CS_TIME_STAMP_MASK) +#define CAN_CS_DLC_MASK (0xF0000U) +#define CAN_CS_DLC_SHIFT (16U) +#define CAN_CS_DLC(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_DLC_SHIFT)) & CAN_CS_DLC_MASK) +#define CAN_CS_RTR_MASK (0x100000U) +#define CAN_CS_RTR_SHIFT (20U) +#define CAN_CS_RTR(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_RTR_SHIFT)) & CAN_CS_RTR_MASK) +#define CAN_CS_IDE_MASK (0x200000U) +#define CAN_CS_IDE_SHIFT (21U) +#define CAN_CS_IDE(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_IDE_SHIFT)) & CAN_CS_IDE_MASK) +#define CAN_CS_SRR_MASK (0x400000U) +#define CAN_CS_SRR_SHIFT (22U) +#define CAN_CS_SRR(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_SRR_SHIFT)) & CAN_CS_SRR_MASK) +#define CAN_CS_CODE_MASK (0xF000000U) +#define CAN_CS_CODE_SHIFT (24U) +#define CAN_CS_CODE(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_CODE_SHIFT)) & CAN_CS_CODE_MASK) +/*! @} */ + +/* The count of CAN_CS */ +#define CAN_CS_COUNT (64U) + +/*! @name ID - Message Buffer 0 ID Register..Message Buffer 63 ID Register */ +/*! @{ */ +#define CAN_ID_EXT_MASK (0x3FFFFU) +#define CAN_ID_EXT_SHIFT (0U) +#define CAN_ID_EXT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ID_EXT_SHIFT)) & CAN_ID_EXT_MASK) +#define CAN_ID_STD_MASK (0x1FFC0000U) +#define CAN_ID_STD_SHIFT (18U) +#define CAN_ID_STD(x) (((uint32_t)(((uint32_t)(x)) << CAN_ID_STD_SHIFT)) & CAN_ID_STD_MASK) +#define CAN_ID_PRIO_MASK (0xE0000000U) +#define CAN_ID_PRIO_SHIFT (29U) +#define CAN_ID_PRIO(x) (((uint32_t)(((uint32_t)(x)) << CAN_ID_PRIO_SHIFT)) & CAN_ID_PRIO_MASK) +/*! @} */ + +/* The count of CAN_ID */ +#define CAN_ID_COUNT (64U) + +/*! @name WORD0 - Message Buffer 0 WORD0 Register..Message Buffer 63 WORD0 Register */ +/*! @{ */ +#define CAN_WORD0_DATA_BYTE_3_MASK (0xFFU) +#define CAN_WORD0_DATA_BYTE_3_SHIFT (0U) +#define CAN_WORD0_DATA_BYTE_3(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD0_DATA_BYTE_3_SHIFT)) & CAN_WORD0_DATA_BYTE_3_MASK) +#define CAN_WORD0_DATA_BYTE_2_MASK (0xFF00U) +#define CAN_WORD0_DATA_BYTE_2_SHIFT (8U) +#define CAN_WORD0_DATA_BYTE_2(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD0_DATA_BYTE_2_SHIFT)) & CAN_WORD0_DATA_BYTE_2_MASK) +#define CAN_WORD0_DATA_BYTE_1_MASK (0xFF0000U) +#define CAN_WORD0_DATA_BYTE_1_SHIFT (16U) +#define CAN_WORD0_DATA_BYTE_1(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD0_DATA_BYTE_1_SHIFT)) & CAN_WORD0_DATA_BYTE_1_MASK) +#define CAN_WORD0_DATA_BYTE_0_MASK (0xFF000000U) +#define CAN_WORD0_DATA_BYTE_0_SHIFT (24U) +#define CAN_WORD0_DATA_BYTE_0(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD0_DATA_BYTE_0_SHIFT)) & CAN_WORD0_DATA_BYTE_0_MASK) +/*! @} */ + +/* The count of CAN_WORD0 */ +#define CAN_WORD0_COUNT (64U) + +/*! @name WORD1 - Message Buffer 0 WORD1 Register..Message Buffer 63 WORD1 Register */ +/*! @{ */ +#define CAN_WORD1_DATA_BYTE_7_MASK (0xFFU) +#define CAN_WORD1_DATA_BYTE_7_SHIFT (0U) +#define CAN_WORD1_DATA_BYTE_7(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD1_DATA_BYTE_7_SHIFT)) & CAN_WORD1_DATA_BYTE_7_MASK) +#define CAN_WORD1_DATA_BYTE_6_MASK (0xFF00U) +#define CAN_WORD1_DATA_BYTE_6_SHIFT (8U) +#define CAN_WORD1_DATA_BYTE_6(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD1_DATA_BYTE_6_SHIFT)) & CAN_WORD1_DATA_BYTE_6_MASK) +#define CAN_WORD1_DATA_BYTE_5_MASK (0xFF0000U) +#define CAN_WORD1_DATA_BYTE_5_SHIFT (16U) +#define CAN_WORD1_DATA_BYTE_5(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD1_DATA_BYTE_5_SHIFT)) & CAN_WORD1_DATA_BYTE_5_MASK) +#define CAN_WORD1_DATA_BYTE_4_MASK (0xFF000000U) +#define CAN_WORD1_DATA_BYTE_4_SHIFT (24U) +#define CAN_WORD1_DATA_BYTE_4(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD1_DATA_BYTE_4_SHIFT)) & CAN_WORD1_DATA_BYTE_4_MASK) +/*! @} */ + +/* The count of CAN_WORD1 */ +#define CAN_WORD1_COUNT (64U) + +/*! @name RXIMR - Rx Individual Mask Registers */ +/*! @{ */ +#define CAN_RXIMR_MI_MASK (0xFFFFFFFFU) +#define CAN_RXIMR_MI_SHIFT (0U) +/*! MI + * 0b00000000000000000000000000000001..The corresponding bit in the filter is checked + * 0b00000000000000000000000000000000..the corresponding bit in the filter is "don't care" + */ +#define CAN_RXIMR_MI(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXIMR_MI_SHIFT)) & CAN_RXIMR_MI_MASK) +/*! @} */ + +/* The count of CAN_RXIMR */ +#define CAN_RXIMR_COUNT (64U) + +/*! @name GFWR - Glitch Filter Width Registers */ +/*! @{ */ +#define CAN_GFWR_GFWR_MASK (0xFFU) +#define CAN_GFWR_GFWR_SHIFT (0U) +#define CAN_GFWR_GFWR(x) (((uint32_t)(((uint32_t)(x)) << CAN_GFWR_GFWR_SHIFT)) & CAN_GFWR_GFWR_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group CAN_Register_Masks */ + + +/* CAN - Peripheral instance base addresses */ +/** Peripheral CAN1 base address */ +#define CAN1_BASE (0x401D0000u) +/** Peripheral CAN1 base pointer */ +#define CAN1 ((CAN_Type *)CAN1_BASE) +/** Peripheral CAN2 base address */ +#define CAN2_BASE (0x401D4000u) +/** Peripheral CAN2 base pointer */ +#define CAN2 ((CAN_Type *)CAN2_BASE) +/** Array initializer of CAN peripheral base addresses */ +#define CAN_BASE_ADDRS { 0u, CAN1_BASE, CAN2_BASE } +/** Array initializer of CAN peripheral base pointers */ +#define CAN_BASE_PTRS { (CAN_Type *)0u, CAN1, CAN2 } +/** Interrupt vectors for the CAN peripheral type */ +#define CAN_Rx_Warning_IRQS { NotAvail_IRQn, CAN1_IRQn, CAN2_IRQn } +#define CAN_Tx_Warning_IRQS { NotAvail_IRQn, CAN1_IRQn, CAN2_IRQn } +#define CAN_Wake_Up_IRQS { NotAvail_IRQn, CAN1_IRQn, CAN2_IRQn } +#define CAN_Error_IRQS { NotAvail_IRQn, CAN1_IRQn, CAN2_IRQn } +#define CAN_Bus_Off_IRQS { NotAvail_IRQn, CAN1_IRQn, CAN2_IRQn } +#define CAN_ORed_Message_buffer_IRQS { NotAvail_IRQn, CAN1_IRQn, CAN2_IRQn } +/* Backward compatibility */ +#define CAN_ECR_TXERRCNT_MASK CAN_ECR_TX_ERR_COUNTER_MASK +#define CAN_ECR_TXERRCNT_SHIFT CAN_ECR_TX_ERR_COUNTER_SHIFT +#define CAN_ECR_TXERRCNT(x) CAN_ECR_TX_ERR_COUNTER(x) +#define CAN_ECR_RXERRCNT_MASK CAN_ECR_RX_ERR_COUNTER_MASK +#define CAN_ECR_RXERRCNT_SHIFT CAN_ECR_RX_ERR_COUNTER_SHIFT +#define CAN_ECR_RXERRCNT(x) CAN_ECR_RX_ERR_COUNTER(x) + + +/*! + * @} + */ /* end of group CAN_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- CCM Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup CCM_Peripheral_Access_Layer CCM Peripheral Access Layer + * @{ + */ + +/** CCM - Register Layout Typedef */ +typedef struct { + __IO uint32_t CCR; /**< CCM Control Register, offset: 0x0 */ + uint8_t RESERVED_0[4]; + __I uint32_t CSR; /**< CCM Status Register, offset: 0x8 */ + __IO uint32_t CCSR; /**< CCM Clock Switcher Register, offset: 0xC */ + __IO uint32_t CACRR; /**< CCM Arm Clock Root Register, offset: 0x10 */ + __IO uint32_t CBCDR; /**< CCM Bus Clock Divider Register, offset: 0x14 */ + __IO uint32_t CBCMR; /**< CCM Bus Clock Multiplexer Register, offset: 0x18 */ + __IO uint32_t CSCMR1; /**< CCM Serial Clock Multiplexer Register 1, offset: 0x1C */ + __IO uint32_t CSCMR2; /**< CCM Serial Clock Multiplexer Register 2, offset: 0x20 */ + __IO uint32_t CSCDR1; /**< CCM Serial Clock Divider Register 1, offset: 0x24 */ + __IO uint32_t CS1CDR; /**< CCM Clock Divider Register, offset: 0x28 */ + __IO uint32_t CS2CDR; /**< CCM Clock Divider Register, offset: 0x2C */ + __IO uint32_t CDCDR; /**< CCM D1 Clock Divider Register, offset: 0x30 */ + uint8_t RESERVED_1[4]; + __IO uint32_t CSCDR2; /**< CCM Serial Clock Divider Register 2, offset: 0x38 */ + __IO uint32_t CSCDR3; /**< CCM Serial Clock Divider Register 3, offset: 0x3C */ + uint8_t RESERVED_2[8]; + __I uint32_t CDHIPR; /**< CCM Divider Handshake In-Process Register, offset: 0x48 */ + uint8_t RESERVED_3[8]; + __IO uint32_t CLPCR; /**< CCM Low Power Control Register, offset: 0x54 */ + __IO uint32_t CISR; /**< CCM Interrupt Status Register, offset: 0x58 */ + __IO uint32_t CIMR; /**< CCM Interrupt Mask Register, offset: 0x5C */ + __IO uint32_t CCOSR; /**< CCM Clock Output Source Register, offset: 0x60 */ + __IO uint32_t CGPR; /**< CCM General Purpose Register, offset: 0x64 */ + __IO uint32_t CCGR0; /**< CCM Clock Gating Register 0, offset: 0x68 */ + __IO uint32_t CCGR1; /**< CCM Clock Gating Register 1, offset: 0x6C */ + __IO uint32_t CCGR2; /**< CCM Clock Gating Register 2, offset: 0x70 */ + __IO uint32_t CCGR3; /**< CCM Clock Gating Register 3, offset: 0x74 */ + __IO uint32_t CCGR4; /**< CCM Clock Gating Register 4, offset: 0x78 */ + __IO uint32_t CCGR5; /**< CCM Clock Gating Register 5, offset: 0x7C */ + __IO uint32_t CCGR6; /**< CCM Clock Gating Register 6, offset: 0x80 */ + uint8_t RESERVED_4[4]; + __IO uint32_t CMEOR; /**< CCM Module Enable Overide Register, offset: 0x88 */ +} CCM_Type; + +/* ---------------------------------------------------------------------------- + -- CCM Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup CCM_Register_Masks CCM Register Masks + * @{ + */ + +/*! @name CCR - CCM Control Register */ +/*! @{ */ +#define CCM_CCR_OSCNT_MASK (0xFFU) +#define CCM_CCR_OSCNT_SHIFT (0U) +/*! OSCNT + * 0b00000000..count 1 ckil + * 0b11111111..count 256 ckil's + */ +#define CCM_CCR_OSCNT(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCR_OSCNT_SHIFT)) & CCM_CCR_OSCNT_MASK) +#define CCM_CCR_COSC_EN_MASK (0x1000U) +#define CCM_CCR_COSC_EN_SHIFT (12U) +/*! COSC_EN + * 0b0..disable on chip oscillator + * 0b1..enable on chip oscillator + */ +#define CCM_CCR_COSC_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCR_COSC_EN_SHIFT)) & CCM_CCR_COSC_EN_MASK) +#define CCM_CCR_REG_BYPASS_COUNT_MASK (0x7E00000U) +#define CCM_CCR_REG_BYPASS_COUNT_SHIFT (21U) +/*! REG_BYPASS_COUNT + * 0b000000..no delay + * 0b000001..1 CKIL clock period delay + * 0b111111..63 CKIL clock periods delay + */ +#define CCM_CCR_REG_BYPASS_COUNT(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCR_REG_BYPASS_COUNT_SHIFT)) & CCM_CCR_REG_BYPASS_COUNT_MASK) +#define CCM_CCR_RBC_EN_MASK (0x8000000U) +#define CCM_CCR_RBC_EN_SHIFT (27U) +/*! RBC_EN + * 0b1..REG_BYPASS_COUNTER enabled. + * 0b0..REG_BYPASS_COUNTER disabled + */ +#define CCM_CCR_RBC_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCR_RBC_EN_SHIFT)) & CCM_CCR_RBC_EN_MASK) +/*! @} */ + +/*! @name CSR - CCM Status Register */ +/*! @{ */ +#define CCM_CSR_REF_EN_B_MASK (0x1U) +#define CCM_CSR_REF_EN_B_SHIFT (0U) +/*! REF_EN_B + * 0b0..value of CCM_REF_EN_B is '0' + * 0b1..value of CCM_REF_EN_B is '1' + */ +#define CCM_CSR_REF_EN_B(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSR_REF_EN_B_SHIFT)) & CCM_CSR_REF_EN_B_MASK) +#define CCM_CSR_CAMP2_READY_MASK (0x8U) +#define CCM_CSR_CAMP2_READY_SHIFT (3U) +/*! CAMP2_READY + * 0b0..CAMP2 is not ready. + * 0b1..CAMP2 is ready. + */ +#define CCM_CSR_CAMP2_READY(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSR_CAMP2_READY_SHIFT)) & CCM_CSR_CAMP2_READY_MASK) +#define CCM_CSR_COSC_READY_MASK (0x20U) +#define CCM_CSR_COSC_READY_SHIFT (5U) +/*! COSC_READY + * 0b0..on board oscillator is not ready. + * 0b1..on board oscillator is ready. + */ +#define CCM_CSR_COSC_READY(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSR_COSC_READY_SHIFT)) & CCM_CSR_COSC_READY_MASK) +/*! @} */ + +/*! @name CCSR - CCM Clock Switcher Register */ +/*! @{ */ +#define CCM_CCSR_PLL3_SW_CLK_SEL_MASK (0x1U) +#define CCM_CCSR_PLL3_SW_CLK_SEL_SHIFT (0U) +/*! PLL3_SW_CLK_SEL + * 0b0..pll3_main_clk + * 0b1..pll3 bypass clock + */ +#define CCM_CCSR_PLL3_SW_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCSR_PLL3_SW_CLK_SEL_SHIFT)) & CCM_CCSR_PLL3_SW_CLK_SEL_MASK) +/*! @} */ + +/*! @name CACRR - CCM Arm Clock Root Register */ +/*! @{ */ +#define CCM_CACRR_ARM_PODF_MASK (0x7U) +#define CCM_CACRR_ARM_PODF_SHIFT (0U) +/*! ARM_PODF + * 0b000..divide by 1 + * 0b001..divide by 2 + * 0b010..divide by 3 + * 0b011..divide by 4 + * 0b100..divide by 5 + * 0b101..divide by 6 + * 0b110..divide by 7 + * 0b111..divide by 8 + */ +#define CCM_CACRR_ARM_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CACRR_ARM_PODF_SHIFT)) & CCM_CACRR_ARM_PODF_MASK) +/*! @} */ + +/*! @name CBCDR - CCM Bus Clock Divider Register */ +/*! @{ */ +#define CCM_CBCDR_SEMC_CLK_SEL_MASK (0x40U) +#define CCM_CBCDR_SEMC_CLK_SEL_SHIFT (6U) +/*! SEMC_CLK_SEL + * 0b0..Periph_clk output will be used as SEMC clock root + * 0b1..SEMC alternative clock will be used as SEMC clock root + */ +#define CCM_CBCDR_SEMC_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CBCDR_SEMC_CLK_SEL_SHIFT)) & CCM_CBCDR_SEMC_CLK_SEL_MASK) +#define CCM_CBCDR_SEMC_ALT_CLK_SEL_MASK (0x80U) +#define CCM_CBCDR_SEMC_ALT_CLK_SEL_SHIFT (7U) +/*! SEMC_ALT_CLK_SEL + * 0b0..PLL2 PFD2 will be selected as alternative clock for SEMC root clock + * 0b1..PLL3 PFD1 will be selected as alternative clock for SEMC root clock + */ +#define CCM_CBCDR_SEMC_ALT_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CBCDR_SEMC_ALT_CLK_SEL_SHIFT)) & CCM_CBCDR_SEMC_ALT_CLK_SEL_MASK) +#define CCM_CBCDR_IPG_PODF_MASK (0x300U) +#define CCM_CBCDR_IPG_PODF_SHIFT (8U) +/*! IPG_PODF + * 0b00..divide by 1 + * 0b01..divide by 2 + * 0b10..divide by 3 + * 0b11..divide by 4 + */ +#define CCM_CBCDR_IPG_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CBCDR_IPG_PODF_SHIFT)) & CCM_CBCDR_IPG_PODF_MASK) +#define CCM_CBCDR_AHB_PODF_MASK (0x1C00U) +#define CCM_CBCDR_AHB_PODF_SHIFT (10U) +/*! AHB_PODF + * 0b000..divide by 1 + * 0b001..divide by 2 + * 0b010..divide by 3 + * 0b011..divide by 4 + * 0b100..divide by 5 + * 0b101..divide by 6 + * 0b110..divide by 7 + * 0b111..divide by 8 + */ +#define CCM_CBCDR_AHB_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CBCDR_AHB_PODF_SHIFT)) & CCM_CBCDR_AHB_PODF_MASK) +#define CCM_CBCDR_SEMC_PODF_MASK (0x70000U) +#define CCM_CBCDR_SEMC_PODF_SHIFT (16U) +/*! SEMC_PODF + * 0b000..divide by 1 + * 0b001..divide by 2 + * 0b010..divide by 3 + * 0b011..divide by 4 + * 0b100..divide by 5 + * 0b101..divide by 6 + * 0b110..divide by 7 + * 0b111..divide by 8 + */ +#define CCM_CBCDR_SEMC_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CBCDR_SEMC_PODF_SHIFT)) & CCM_CBCDR_SEMC_PODF_MASK) +#define CCM_CBCDR_PERIPH_CLK_SEL_MASK (0x2000000U) +#define CCM_CBCDR_PERIPH_CLK_SEL_SHIFT (25U) +/*! PERIPH_CLK_SEL + * 0b0..derive clock from pre_periph_clk_sel + * 0b1..derive clock from periph_clk2_clk_divided + */ +#define CCM_CBCDR_PERIPH_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CBCDR_PERIPH_CLK_SEL_SHIFT)) & CCM_CBCDR_PERIPH_CLK_SEL_MASK) +#define CCM_CBCDR_PERIPH_CLK2_PODF_MASK (0x38000000U) +#define CCM_CBCDR_PERIPH_CLK2_PODF_SHIFT (27U) +/*! PERIPH_CLK2_PODF + * 0b000..divide by 1 + * 0b001..divide by 2 + * 0b010..divide by 3 + * 0b011..divide by 4 + * 0b100..divide by 5 + * 0b101..divide by 6 + * 0b110..divide by 7 + * 0b111..divide by 8 + */ +#define CCM_CBCDR_PERIPH_CLK2_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CBCDR_PERIPH_CLK2_PODF_SHIFT)) & CCM_CBCDR_PERIPH_CLK2_PODF_MASK) +/*! @} */ + +/*! @name CBCMR - CCM Bus Clock Multiplexer Register */ +/*! @{ */ +#define CCM_CBCMR_LPSPI_CLK_SEL_MASK (0x30U) +#define CCM_CBCMR_LPSPI_CLK_SEL_SHIFT (4U) +/*! LPSPI_CLK_SEL + * 0b00..derive clock from PLL3 PFD1 clk + * 0b01..derive clock from PLL3 PFD0 + * 0b10..derive clock from PLL2 + * 0b11..derive clock from PLL2 PFD2 + */ +#define CCM_CBCMR_LPSPI_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CBCMR_LPSPI_CLK_SEL_SHIFT)) & CCM_CBCMR_LPSPI_CLK_SEL_MASK) +#define CCM_CBCMR_PERIPH_CLK2_SEL_MASK (0x3000U) +#define CCM_CBCMR_PERIPH_CLK2_SEL_SHIFT (12U) +/*! PERIPH_CLK2_SEL + * 0b00..derive clock from pll3_sw_clk + * 0b01..derive clock from osc_clk (pll1_ref_clk) + * 0b10..derive clock from pll2_bypass_clk + * 0b11..reserved + */ +#define CCM_CBCMR_PERIPH_CLK2_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CBCMR_PERIPH_CLK2_SEL_SHIFT)) & CCM_CBCMR_PERIPH_CLK2_SEL_MASK) +#define CCM_CBCMR_TRACE_CLK_SEL_MASK (0xC000U) +#define CCM_CBCMR_TRACE_CLK_SEL_SHIFT (14U) +/*! TRACE_CLK_SEL + * 0b00..derive clock from PLL2 + * 0b01..derive clock from PLL2 PFD2 + * 0b10..derive clock from PLL2 PFD0 + * 0b11..derive clock from PLL2 PFD1 + */ +#define CCM_CBCMR_TRACE_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CBCMR_TRACE_CLK_SEL_SHIFT)) & CCM_CBCMR_TRACE_CLK_SEL_MASK) +#define CCM_CBCMR_PRE_PERIPH_CLK_SEL_MASK (0xC0000U) +#define CCM_CBCMR_PRE_PERIPH_CLK_SEL_SHIFT (18U) +/*! PRE_PERIPH_CLK_SEL + * 0b00..derive clock from PLL2 + * 0b01..derive clock from PLL2 PFD2 + * 0b10..derive clock from PLL2 PFD0 + * 0b11..derive clock from divided PLL1 + */ +#define CCM_CBCMR_PRE_PERIPH_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CBCMR_PRE_PERIPH_CLK_SEL_SHIFT)) & CCM_CBCMR_PRE_PERIPH_CLK_SEL_MASK) +#define CCM_CBCMR_LCDIF_PODF_MASK (0x3800000U) +#define CCM_CBCMR_LCDIF_PODF_SHIFT (23U) +/*! LCDIF_PODF + * 0b000..divide by 1 + * 0b001..divide by 2 + * 0b010..divide by 3 + * 0b011..divide by 4 + * 0b100..divide by 5 + * 0b101..divide by 6 + * 0b110..divide by 7 + * 0b111..divide by 8 + */ +#define CCM_CBCMR_LCDIF_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CBCMR_LCDIF_PODF_SHIFT)) & CCM_CBCMR_LCDIF_PODF_MASK) +#define CCM_CBCMR_LPSPI_PODF_MASK (0x1C000000U) +#define CCM_CBCMR_LPSPI_PODF_SHIFT (26U) +/*! LPSPI_PODF + * 0b000..divide by 1 + * 0b001..divide by 2 + * 0b010..divide by 3 + * 0b011..divide by 4 + * 0b100..divide by 5 + * 0b101..divide by 6 + * 0b110..divide by 7 + * 0b111..divide by 8 + */ +#define CCM_CBCMR_LPSPI_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CBCMR_LPSPI_PODF_SHIFT)) & CCM_CBCMR_LPSPI_PODF_MASK) +/*! @} */ + +/*! @name CSCMR1 - CCM Serial Clock Multiplexer Register 1 */ +/*! @{ */ +#define CCM_CSCMR1_PERCLK_PODF_MASK (0x3FU) +#define CCM_CSCMR1_PERCLK_PODF_SHIFT (0U) +/*! PERCLK_PODF + * 0b000000..divide by 1 + * 0b000001..divide by 2 + * 0b000010..divide by 3 + * 0b000011..divide by 4 + * 0b000100..divide by 5 + * 0b000101..divide by 6 + * 0b000110..divide by 7 + * 0b111111..divide by 64 + */ +#define CCM_CSCMR1_PERCLK_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCMR1_PERCLK_PODF_SHIFT)) & CCM_CSCMR1_PERCLK_PODF_MASK) +#define CCM_CSCMR1_PERCLK_CLK_SEL_MASK (0x40U) +#define CCM_CSCMR1_PERCLK_CLK_SEL_SHIFT (6U) +/*! PERCLK_CLK_SEL + * 0b0..derive clock from ipg clk root + * 0b1..derive clock from osc_clk + */ +#define CCM_CSCMR1_PERCLK_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCMR1_PERCLK_CLK_SEL_SHIFT)) & CCM_CSCMR1_PERCLK_CLK_SEL_MASK) +#define CCM_CSCMR1_SAI1_CLK_SEL_MASK (0xC00U) +#define CCM_CSCMR1_SAI1_CLK_SEL_SHIFT (10U) +/*! SAI1_CLK_SEL + * 0b00..derive clock from PLL3 PFD2 + * 0b01..derive clock from PLL5 + * 0b10..derive clock from PLL4 + * 0b11..Reserved + */ +#define CCM_CSCMR1_SAI1_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCMR1_SAI1_CLK_SEL_SHIFT)) & CCM_CSCMR1_SAI1_CLK_SEL_MASK) +#define CCM_CSCMR1_SAI2_CLK_SEL_MASK (0x3000U) +#define CCM_CSCMR1_SAI2_CLK_SEL_SHIFT (12U) +/*! SAI2_CLK_SEL + * 0b00..derive clock from PLL3 PFD2 + * 0b01..derive clock from PLL5 + * 0b10..derive clock from PLL4 + * 0b11..Reserved + */ +#define CCM_CSCMR1_SAI2_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCMR1_SAI2_CLK_SEL_SHIFT)) & CCM_CSCMR1_SAI2_CLK_SEL_MASK) +#define CCM_CSCMR1_SAI3_CLK_SEL_MASK (0xC000U) +#define CCM_CSCMR1_SAI3_CLK_SEL_SHIFT (14U) +/*! SAI3_CLK_SEL + * 0b00..derive clock from PLL3 PFD2 + * 0b01..derive clock from PLL5 + * 0b10..derive clock from PLL4 + * 0b11..Reserved + */ +#define CCM_CSCMR1_SAI3_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCMR1_SAI3_CLK_SEL_SHIFT)) & CCM_CSCMR1_SAI3_CLK_SEL_MASK) +#define CCM_CSCMR1_USDHC1_CLK_SEL_MASK (0x10000U) +#define CCM_CSCMR1_USDHC1_CLK_SEL_SHIFT (16U) +/*! USDHC1_CLK_SEL + * 0b0..derive clock from PLL2 PFD2 + * 0b1..derive clock from PLL2 PFD0 + */ +#define CCM_CSCMR1_USDHC1_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCMR1_USDHC1_CLK_SEL_SHIFT)) & CCM_CSCMR1_USDHC1_CLK_SEL_MASK) +#define CCM_CSCMR1_USDHC2_CLK_SEL_MASK (0x20000U) +#define CCM_CSCMR1_USDHC2_CLK_SEL_SHIFT (17U) +/*! USDHC2_CLK_SEL + * 0b0..derive clock from PLL2 PFD2 + * 0b1..derive clock from PLL2 PFD0 + */ +#define CCM_CSCMR1_USDHC2_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCMR1_USDHC2_CLK_SEL_SHIFT)) & CCM_CSCMR1_USDHC2_CLK_SEL_MASK) +#define CCM_CSCMR1_FLEXSPI_PODF_MASK (0x3800000U) +#define CCM_CSCMR1_FLEXSPI_PODF_SHIFT (23U) +/*! FLEXSPI_PODF + * 0b000..divide by 1 + * 0b001..divide by 2 + * 0b010..divide by 3 + * 0b011..divide by 4 + * 0b100..divide by 5 + * 0b101..divide by 6 + * 0b110..divide by 7 + * 0b111..divide by 8 + */ +#define CCM_CSCMR1_FLEXSPI_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCMR1_FLEXSPI_PODF_SHIFT)) & CCM_CSCMR1_FLEXSPI_PODF_MASK) +#define CCM_CSCMR1_FLEXSPI_CLK_SEL_MASK (0x60000000U) +#define CCM_CSCMR1_FLEXSPI_CLK_SEL_SHIFT (29U) +/*! FLEXSPI_CLK_SEL + * 0b00..derive clock from semc_clk_root_pre + * 0b01..derive clock from pll3_sw_clk + * 0b10..derive clock from PLL2 PFD2 + * 0b11..derive clock from PLL3 PFD0 + */ +#define CCM_CSCMR1_FLEXSPI_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCMR1_FLEXSPI_CLK_SEL_SHIFT)) & CCM_CSCMR1_FLEXSPI_CLK_SEL_MASK) +/*! @} */ + +/*! @name CSCMR2 - CCM Serial Clock Multiplexer Register 2 */ +/*! @{ */ +#define CCM_CSCMR2_CAN_CLK_PODF_MASK (0xFCU) +#define CCM_CSCMR2_CAN_CLK_PODF_SHIFT (2U) +/*! CAN_CLK_PODF + * 0b000000..divide by 1 + * 0b000111..divide by 8 + * 0b111111..divide by 2^6 + */ +#define CCM_CSCMR2_CAN_CLK_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCMR2_CAN_CLK_PODF_SHIFT)) & CCM_CSCMR2_CAN_CLK_PODF_MASK) +#define CCM_CSCMR2_CAN_CLK_SEL_MASK (0x300U) +#define CCM_CSCMR2_CAN_CLK_SEL_SHIFT (8U) +/*! CAN_CLK_SEL + * 0b00..derive clock from pll3_sw_clk divided clock (60M) + * 0b01..derive clock from osc_clk (24M) + * 0b10..derive clock from pll3_sw_clk divided clock (80M) + * 0b11..Disable FlexCAN clock + */ +#define CCM_CSCMR2_CAN_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCMR2_CAN_CLK_SEL_SHIFT)) & CCM_CSCMR2_CAN_CLK_SEL_MASK) +#define CCM_CSCMR2_FLEXIO2_CLK_SEL_MASK (0x180000U) +#define CCM_CSCMR2_FLEXIO2_CLK_SEL_SHIFT (19U) +/*! FLEXIO2_CLK_SEL + * 0b00..derive clock from PLL4 divided clock + * 0b01..derive clock from PLL3 PFD2 clock + * 0b10..derive clock from PLL5 clock + * 0b11..derive clock from pll3_sw_clk + */ +#define CCM_CSCMR2_FLEXIO2_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCMR2_FLEXIO2_CLK_SEL_SHIFT)) & CCM_CSCMR2_FLEXIO2_CLK_SEL_MASK) +/*! @} */ + +/*! @name CSCDR1 - CCM Serial Clock Divider Register 1 */ +/*! @{ */ +#define CCM_CSCDR1_UART_CLK_PODF_MASK (0x3FU) +#define CCM_CSCDR1_UART_CLK_PODF_SHIFT (0U) +/*! UART_CLK_PODF + * 0b000000..divide by 1 + * 0b111111..divide by 2^6 + */ +#define CCM_CSCDR1_UART_CLK_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCDR1_UART_CLK_PODF_SHIFT)) & CCM_CSCDR1_UART_CLK_PODF_MASK) +#define CCM_CSCDR1_UART_CLK_SEL_MASK (0x40U) +#define CCM_CSCDR1_UART_CLK_SEL_SHIFT (6U) +/*! UART_CLK_SEL + * 0b0..derive clock from pll3_80m + * 0b1..derive clock from osc_clk + */ +#define CCM_CSCDR1_UART_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCDR1_UART_CLK_SEL_SHIFT)) & CCM_CSCDR1_UART_CLK_SEL_MASK) +#define CCM_CSCDR1_USDHC1_PODF_MASK (0x3800U) +#define CCM_CSCDR1_USDHC1_PODF_SHIFT (11U) +/*! USDHC1_PODF + * 0b000..divide by 1 + * 0b001..divide by 2 + * 0b010..divide by 3 + * 0b011..divide by 4 + * 0b100..divide by 5 + * 0b101..divide by 6 + * 0b110..divide by 7 + * 0b111..divide by 8 + */ +#define CCM_CSCDR1_USDHC1_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCDR1_USDHC1_PODF_SHIFT)) & CCM_CSCDR1_USDHC1_PODF_MASK) +#define CCM_CSCDR1_USDHC2_PODF_MASK (0x70000U) +#define CCM_CSCDR1_USDHC2_PODF_SHIFT (16U) +/*! USDHC2_PODF + * 0b000..divide by 1 + * 0b001..divide by 2 + * 0b010..divide by 3 + * 0b011..divide by 4 + * 0b100..divide by 5 + * 0b101..divide by 6 + * 0b110..divide by 7 + * 0b111..divide by 8 + */ +#define CCM_CSCDR1_USDHC2_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCDR1_USDHC2_PODF_SHIFT)) & CCM_CSCDR1_USDHC2_PODF_MASK) +#define CCM_CSCDR1_TRACE_PODF_MASK (0x6000000U) +#define CCM_CSCDR1_TRACE_PODF_SHIFT (25U) +/*! TRACE_PODF + * 0b00..divide by 1 + * 0b01..divide by 2 + * 0b10..divide by 3 + * 0b11..divide by 4 + */ +#define CCM_CSCDR1_TRACE_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCDR1_TRACE_PODF_SHIFT)) & CCM_CSCDR1_TRACE_PODF_MASK) +/*! @} */ + +/*! @name CS1CDR - CCM Clock Divider Register */ +/*! @{ */ +#define CCM_CS1CDR_SAI1_CLK_PODF_MASK (0x3FU) +#define CCM_CS1CDR_SAI1_CLK_PODF_SHIFT (0U) +/*! SAI1_CLK_PODF + * 0b000000..divide by 1 + * 0b111111..divide by 2^6 + */ +#define CCM_CS1CDR_SAI1_CLK_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CS1CDR_SAI1_CLK_PODF_SHIFT)) & CCM_CS1CDR_SAI1_CLK_PODF_MASK) +#define CCM_CS1CDR_SAI1_CLK_PRED_MASK (0x1C0U) +#define CCM_CS1CDR_SAI1_CLK_PRED_SHIFT (6U) +/*! SAI1_CLK_PRED + * 0b000..divide by 1 + * 0b001..divide by 2 + * 0b010..divide by 3 + * 0b011..divide by 4 + * 0b100..divide by 5 + * 0b101..divide by 6 + * 0b110..divide by 7 + * 0b111..divide by 8 + */ +#define CCM_CS1CDR_SAI1_CLK_PRED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CS1CDR_SAI1_CLK_PRED_SHIFT)) & CCM_CS1CDR_SAI1_CLK_PRED_MASK) +#define CCM_CS1CDR_FLEXIO2_CLK_PRED_MASK (0xE00U) +#define CCM_CS1CDR_FLEXIO2_CLK_PRED_SHIFT (9U) +/*! FLEXIO2_CLK_PRED + * 0b000..divide by 1 + * 0b001..divide by 2 + * 0b010..divide by 3 + * 0b011..divide by 4 + * 0b100..divide by 5 + * 0b101..divide by 6 + * 0b110..divide by 7 + * 0b111..divide by 8 + */ +#define CCM_CS1CDR_FLEXIO2_CLK_PRED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CS1CDR_FLEXIO2_CLK_PRED_SHIFT)) & CCM_CS1CDR_FLEXIO2_CLK_PRED_MASK) +#define CCM_CS1CDR_SAI3_CLK_PODF_MASK (0x3F0000U) +#define CCM_CS1CDR_SAI3_CLK_PODF_SHIFT (16U) +/*! SAI3_CLK_PODF + * 0b000000..divide by 1 + * 0b111111..divide by 2^6 + */ +#define CCM_CS1CDR_SAI3_CLK_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CS1CDR_SAI3_CLK_PODF_SHIFT)) & CCM_CS1CDR_SAI3_CLK_PODF_MASK) +#define CCM_CS1CDR_SAI3_CLK_PRED_MASK (0x1C00000U) +#define CCM_CS1CDR_SAI3_CLK_PRED_SHIFT (22U) +/*! SAI3_CLK_PRED + * 0b000..divide by 1 + * 0b001..divide by 2 + * 0b010..divide by 3 + * 0b011..divide by 4 + * 0b100..divide by 5 + * 0b101..divide by 6 + * 0b110..divide by 7 + * 0b111..divide by 8 + */ +#define CCM_CS1CDR_SAI3_CLK_PRED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CS1CDR_SAI3_CLK_PRED_SHIFT)) & CCM_CS1CDR_SAI3_CLK_PRED_MASK) +#define CCM_CS1CDR_FLEXIO2_CLK_PODF_MASK (0xE000000U) +#define CCM_CS1CDR_FLEXIO2_CLK_PODF_SHIFT (25U) +/*! FLEXIO2_CLK_PODF + * 0b000..divide by 1 + * 0b001..divide by 2 + * 0b010..divide by 3 + * 0b011..divide by 4 + * 0b100..divide by 5 + * 0b101..divide by 6 + * 0b110..divide by 7 + * 0b111..divide by 8 + */ +#define CCM_CS1CDR_FLEXIO2_CLK_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CS1CDR_FLEXIO2_CLK_PODF_SHIFT)) & CCM_CS1CDR_FLEXIO2_CLK_PODF_MASK) +/*! @} */ + +/*! @name CS2CDR - CCM Clock Divider Register */ +/*! @{ */ +#define CCM_CS2CDR_SAI2_CLK_PODF_MASK (0x3FU) +#define CCM_CS2CDR_SAI2_CLK_PODF_SHIFT (0U) +/*! SAI2_CLK_PODF + * 0b000000..divide by 1 + * 0b111111..divide by 2^6 + */ +#define CCM_CS2CDR_SAI2_CLK_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CS2CDR_SAI2_CLK_PODF_SHIFT)) & CCM_CS2CDR_SAI2_CLK_PODF_MASK) +#define CCM_CS2CDR_SAI2_CLK_PRED_MASK (0x1C0U) +#define CCM_CS2CDR_SAI2_CLK_PRED_SHIFT (6U) +/*! SAI2_CLK_PRED + * 0b000..divide by 1 + * 0b001..divide by 2 + * 0b010..divide by 3 + * 0b011..divide by 4 + * 0b100..divide by 5 + * 0b101..divide by 6 + * 0b110..divide by 7 + * 0b111..divide by 8 + */ +#define CCM_CS2CDR_SAI2_CLK_PRED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CS2CDR_SAI2_CLK_PRED_SHIFT)) & CCM_CS2CDR_SAI2_CLK_PRED_MASK) +/*! @} */ + +/*! @name CDCDR - CCM D1 Clock Divider Register */ +/*! @{ */ +#define CCM_CDCDR_FLEXIO1_CLK_SEL_MASK (0x180U) +#define CCM_CDCDR_FLEXIO1_CLK_SEL_SHIFT (7U) +/*! FLEXIO1_CLK_SEL + * 0b00..derive clock from PLL4 + * 0b01..derive clock from PLL3 PFD2 + * 0b10..derive clock from PLL5 + * 0b11..derive clock from pll3_sw_clk + */ +#define CCM_CDCDR_FLEXIO1_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CDCDR_FLEXIO1_CLK_SEL_SHIFT)) & CCM_CDCDR_FLEXIO1_CLK_SEL_MASK) +#define CCM_CDCDR_FLEXIO1_CLK_PODF_MASK (0xE00U) +#define CCM_CDCDR_FLEXIO1_CLK_PODF_SHIFT (9U) +/*! FLEXIO1_CLK_PODF + * 0b000..divide by 1 + * 0b111..divide by 8 + */ +#define CCM_CDCDR_FLEXIO1_CLK_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CDCDR_FLEXIO1_CLK_PODF_SHIFT)) & CCM_CDCDR_FLEXIO1_CLK_PODF_MASK) +#define CCM_CDCDR_FLEXIO1_CLK_PRED_MASK (0x7000U) +#define CCM_CDCDR_FLEXIO1_CLK_PRED_SHIFT (12U) +/*! FLEXIO1_CLK_PRED + * 0b000..divide by 1 (do not use with high input frequencies) + * 0b001..divide by 2 + * 0b010..divide by 3 + * 0b111..divide by 8 + */ +#define CCM_CDCDR_FLEXIO1_CLK_PRED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CDCDR_FLEXIO1_CLK_PRED_SHIFT)) & CCM_CDCDR_FLEXIO1_CLK_PRED_MASK) +#define CCM_CDCDR_SPDIF0_CLK_SEL_MASK (0x300000U) +#define CCM_CDCDR_SPDIF0_CLK_SEL_SHIFT (20U) +/*! SPDIF0_CLK_SEL + * 0b00..derive clock from PLL4 + * 0b01..derive clock from PLL3 PFD2 + * 0b10..derive clock from PLL5 + * 0b11..derive clock from pll3_sw_clk + */ +#define CCM_CDCDR_SPDIF0_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CDCDR_SPDIF0_CLK_SEL_SHIFT)) & CCM_CDCDR_SPDIF0_CLK_SEL_MASK) +#define CCM_CDCDR_SPDIF0_CLK_PODF_MASK (0x1C00000U) +#define CCM_CDCDR_SPDIF0_CLK_PODF_SHIFT (22U) +/*! SPDIF0_CLK_PODF + * 0b000..divide by 1 + * 0b111..divide by 8 + */ +#define CCM_CDCDR_SPDIF0_CLK_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CDCDR_SPDIF0_CLK_PODF_SHIFT)) & CCM_CDCDR_SPDIF0_CLK_PODF_MASK) +#define CCM_CDCDR_SPDIF0_CLK_PRED_MASK (0xE000000U) +#define CCM_CDCDR_SPDIF0_CLK_PRED_SHIFT (25U) +/*! SPDIF0_CLK_PRED + * 0b000..divide by 1 (do not use with high input frequencies) + * 0b001..divide by 2 + * 0b010..divide by 3 + * 0b111..divide by 8 + */ +#define CCM_CDCDR_SPDIF0_CLK_PRED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CDCDR_SPDIF0_CLK_PRED_SHIFT)) & CCM_CDCDR_SPDIF0_CLK_PRED_MASK) +/*! @} */ + +/*! @name CSCDR2 - CCM Serial Clock Divider Register 2 */ +/*! @{ */ +#define CCM_CSCDR2_LCDIF_PRED_MASK (0x7000U) +#define CCM_CSCDR2_LCDIF_PRED_SHIFT (12U) +/*! LCDIF_PRED + * 0b000..divide by 1 + * 0b001..divide by 2 + * 0b010..divide by 3 + * 0b011..divide by 4 + * 0b100..divide by 5 + * 0b101..divide by 6 + * 0b110..divide by 7 + * 0b111..divide by 8 + */ +#define CCM_CSCDR2_LCDIF_PRED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCDR2_LCDIF_PRED_SHIFT)) & CCM_CSCDR2_LCDIF_PRED_MASK) +#define CCM_CSCDR2_LCDIF_PRE_CLK_SEL_MASK (0x38000U) +#define CCM_CSCDR2_LCDIF_PRE_CLK_SEL_SHIFT (15U) +/*! LCDIF_PRE_CLK_SEL + * 0b000..derive clock from PLL2 + * 0b001..derive clock from PLL3 PFD3 + * 0b010..derive clock from PLL5 + * 0b011..derive clock from PLL2 PFD0 + * 0b100..derive clock from PLL2 PFD1 + * 0b101..derive clock from PLL3 PFD1 + */ +#define CCM_CSCDR2_LCDIF_PRE_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCDR2_LCDIF_PRE_CLK_SEL_SHIFT)) & CCM_CSCDR2_LCDIF_PRE_CLK_SEL_MASK) +#define CCM_CSCDR2_LPI2C_CLK_SEL_MASK (0x40000U) +#define CCM_CSCDR2_LPI2C_CLK_SEL_SHIFT (18U) +/*! LPI2C_CLK_SEL + * 0b0..derive clock from pll3_60m + * 0b1..derive clock from osc_clk + */ +#define CCM_CSCDR2_LPI2C_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCDR2_LPI2C_CLK_SEL_SHIFT)) & CCM_CSCDR2_LPI2C_CLK_SEL_MASK) +#define CCM_CSCDR2_LPI2C_CLK_PODF_MASK (0x1F80000U) +#define CCM_CSCDR2_LPI2C_CLK_PODF_SHIFT (19U) +/*! LPI2C_CLK_PODF + * 0b000000..divide by 1 + * 0b111111..divide by 2^6 + */ +#define CCM_CSCDR2_LPI2C_CLK_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCDR2_LPI2C_CLK_PODF_SHIFT)) & CCM_CSCDR2_LPI2C_CLK_PODF_MASK) +/*! @} */ + +/*! @name CSCDR3 - CCM Serial Clock Divider Register 3 */ +/*! @{ */ +#define CCM_CSCDR3_CSI_CLK_SEL_MASK (0x600U) +#define CCM_CSCDR3_CSI_CLK_SEL_SHIFT (9U) +/*! CSI_CLK_SEL + * 0b00..derive clock from osc_clk (24M) + * 0b01..derive clock from PLL2 PFD2 + * 0b10..derive clock from pll3_120M + * 0b11..derive clock from PLL3 PFD1 + */ +#define CCM_CSCDR3_CSI_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCDR3_CSI_CLK_SEL_SHIFT)) & CCM_CSCDR3_CSI_CLK_SEL_MASK) +#define CCM_CSCDR3_CSI_PODF_MASK (0x3800U) +#define CCM_CSCDR3_CSI_PODF_SHIFT (11U) +/*! CSI_PODF + * 0b000..divide by 1 + * 0b001..divide by 2 + * 0b010..divide by 3 + * 0b011..divide by 4 + * 0b100..divide by 5 + * 0b101..divide by 6 + * 0b110..divide by 7 + * 0b111..divide by 8 + */ +#define CCM_CSCDR3_CSI_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCDR3_CSI_PODF_SHIFT)) & CCM_CSCDR3_CSI_PODF_MASK) +/*! @} */ + +/*! @name CDHIPR - CCM Divider Handshake In-Process Register */ +/*! @{ */ +#define CCM_CDHIPR_SEMC_PODF_BUSY_MASK (0x1U) +#define CCM_CDHIPR_SEMC_PODF_BUSY_SHIFT (0U) +/*! SEMC_PODF_BUSY + * 0b0..divider is not busy and its value represents the actual division. + * 0b1..divider is busy with handshake process with module. The value read in the divider represents the previous value of the division factor, and after the handshake the written value of the semc_podf will be applied. + */ +#define CCM_CDHIPR_SEMC_PODF_BUSY(x) (((uint32_t)(((uint32_t)(x)) << CCM_CDHIPR_SEMC_PODF_BUSY_SHIFT)) & CCM_CDHIPR_SEMC_PODF_BUSY_MASK) +#define CCM_CDHIPR_AHB_PODF_BUSY_MASK (0x2U) +#define CCM_CDHIPR_AHB_PODF_BUSY_SHIFT (1U) +/*! AHB_PODF_BUSY + * 0b0..divider is not busy and its value represents the actual division. + * 0b1..divider is busy with handshake process with module. The value read in the divider represents the previous value of the division factor, and after the handshake the written value of the ahb_podf will be applied. + */ +#define CCM_CDHIPR_AHB_PODF_BUSY(x) (((uint32_t)(((uint32_t)(x)) << CCM_CDHIPR_AHB_PODF_BUSY_SHIFT)) & CCM_CDHIPR_AHB_PODF_BUSY_MASK) +#define CCM_CDHIPR_PERIPH2_CLK_SEL_BUSY_MASK (0x8U) +#define CCM_CDHIPR_PERIPH2_CLK_SEL_BUSY_SHIFT (3U) +/*! PERIPH2_CLK_SEL_BUSY + * 0b0..mux is not busy and its value represents the actual division. + * 0b1..mux is busy with handshake process with module. The value read in the periph2_clk_sel represents the previous value of select, and after the handshake periph2_clk_sel value will be applied. + */ +#define CCM_CDHIPR_PERIPH2_CLK_SEL_BUSY(x) (((uint32_t)(((uint32_t)(x)) << CCM_CDHIPR_PERIPH2_CLK_SEL_BUSY_SHIFT)) & CCM_CDHIPR_PERIPH2_CLK_SEL_BUSY_MASK) +#define CCM_CDHIPR_PERIPH_CLK_SEL_BUSY_MASK (0x20U) +#define CCM_CDHIPR_PERIPH_CLK_SEL_BUSY_SHIFT (5U) +/*! PERIPH_CLK_SEL_BUSY + * 0b0..mux is not busy and its value represents the actual division. + * 0b1..mux is busy with handshake process with module. The value read in the periph_clk_sel represents the previous value of select, and after the handshake periph_clk_sel value will be applied. + */ +#define CCM_CDHIPR_PERIPH_CLK_SEL_BUSY(x) (((uint32_t)(((uint32_t)(x)) << CCM_CDHIPR_PERIPH_CLK_SEL_BUSY_SHIFT)) & CCM_CDHIPR_PERIPH_CLK_SEL_BUSY_MASK) +#define CCM_CDHIPR_ARM_PODF_BUSY_MASK (0x10000U) +#define CCM_CDHIPR_ARM_PODF_BUSY_SHIFT (16U) +/*! ARM_PODF_BUSY + * 0b0..divider is not busy and its value represents the actual division. + * 0b1..divider is busy with handshake process with module. The value read in the divider represents the previous value of the division factor, and after the handshake the written value of the arm_podf will be applied. + */ +#define CCM_CDHIPR_ARM_PODF_BUSY(x) (((uint32_t)(((uint32_t)(x)) << CCM_CDHIPR_ARM_PODF_BUSY_SHIFT)) & CCM_CDHIPR_ARM_PODF_BUSY_MASK) +/*! @} */ + +/*! @name CLPCR - CCM Low Power Control Register */ +/*! @{ */ +#define CCM_CLPCR_LPM_MASK (0x3U) +#define CCM_CLPCR_LPM_SHIFT (0U) +/*! LPM + * 0b00..Remain in run mode + * 0b01..Transfer to wait mode + * 0b10..Transfer to stop mode + * 0b11..Reserved + */ +#define CCM_CLPCR_LPM(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLPCR_LPM_SHIFT)) & CCM_CLPCR_LPM_MASK) +#define CCM_CLPCR_ARM_CLK_DIS_ON_LPM_MASK (0x20U) +#define CCM_CLPCR_ARM_CLK_DIS_ON_LPM_SHIFT (5U) +/*! ARM_CLK_DIS_ON_LPM + * 0b0..ARM clock enabled on wait mode. + * 0b1..ARM clock disabled on wait mode. . + */ +#define CCM_CLPCR_ARM_CLK_DIS_ON_LPM(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLPCR_ARM_CLK_DIS_ON_LPM_SHIFT)) & CCM_CLPCR_ARM_CLK_DIS_ON_LPM_MASK) +#define CCM_CLPCR_SBYOS_MASK (0x40U) +#define CCM_CLPCR_SBYOS_SHIFT (6U) +/*! SBYOS + * 0b0..On-chip oscillator will not be powered down, after next entrance to STOP mode. (CCM_REF_EN_B will remain asserted - '0' and cosc_pwrdown will remain de asserted - '0') + * 0b1..On-chip oscillator will be powered down, after next entrance to STOP mode. (CCM_REF_EN_B will be deasserted - '1' and cosc_pwrdown will be asserted - '1'). When returning from STOP mode, external oscillator will be enabled again, on-chip oscillator will return to oscillator mode, and after oscnt count, CCM will continue with the exit from the STOP mode process. + */ +#define CCM_CLPCR_SBYOS(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLPCR_SBYOS_SHIFT)) & CCM_CLPCR_SBYOS_MASK) +#define CCM_CLPCR_DIS_REF_OSC_MASK (0x80U) +#define CCM_CLPCR_DIS_REF_OSC_SHIFT (7U) +/*! DIS_REF_OSC + * 0b0..external high frequency oscillator will be enabled, i.e. CCM_REF_EN_B = '0'. + * 0b1..external high frequency oscillator will be disabled, i.e. CCM_REF_EN_B = '1' + */ +#define CCM_CLPCR_DIS_REF_OSC(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLPCR_DIS_REF_OSC_SHIFT)) & CCM_CLPCR_DIS_REF_OSC_MASK) +#define CCM_CLPCR_VSTBY_MASK (0x100U) +#define CCM_CLPCR_VSTBY_SHIFT (8U) +/*! VSTBY + * 0b0..Voltage will not be changed to standby voltage after next entrance to STOP mode. ( PMIC_STBY_REQ will remain negated - '0') + * 0b1..Voltage will be requested to change to standby voltage after next entrance to stop mode. ( PMIC_STBY_REQ will be asserted - '1'). + */ +#define CCM_CLPCR_VSTBY(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLPCR_VSTBY_SHIFT)) & CCM_CLPCR_VSTBY_MASK) +#define CCM_CLPCR_STBY_COUNT_MASK (0x600U) +#define CCM_CLPCR_STBY_COUNT_SHIFT (9U) +/*! STBY_COUNT + * 0b00..CCM will wait (1*pmic_delay_scaler)+1 ckil clock cycles + * 0b01..CCM will wait (3*pmic_delay_scaler)+1 ckil clock cycles + * 0b10..CCM will wait (7*pmic_delay_scaler)+1 ckil clock cycles + * 0b11..CCM will wait (15*pmic_delay_scaler)+1 ckil clock cycles + */ +#define CCM_CLPCR_STBY_COUNT(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLPCR_STBY_COUNT_SHIFT)) & CCM_CLPCR_STBY_COUNT_MASK) +#define CCM_CLPCR_COSC_PWRDOWN_MASK (0x800U) +#define CCM_CLPCR_COSC_PWRDOWN_SHIFT (11U) +/*! COSC_PWRDOWN + * 0b0..On chip oscillator will not be powered down, i.e. cosc_pwrdown = '0'. + * 0b1..On chip oscillator will be powered down, i.e. cosc_pwrdown = '1'. + */ +#define CCM_CLPCR_COSC_PWRDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLPCR_COSC_PWRDOWN_SHIFT)) & CCM_CLPCR_COSC_PWRDOWN_MASK) +#define CCM_CLPCR_BYPASS_LPM_HS1_MASK (0x80000U) +#define CCM_CLPCR_BYPASS_LPM_HS1_SHIFT (19U) +#define CCM_CLPCR_BYPASS_LPM_HS1(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLPCR_BYPASS_LPM_HS1_SHIFT)) & CCM_CLPCR_BYPASS_LPM_HS1_MASK) +#define CCM_CLPCR_BYPASS_LPM_HS0_MASK (0x200000U) +#define CCM_CLPCR_BYPASS_LPM_HS0_SHIFT (21U) +#define CCM_CLPCR_BYPASS_LPM_HS0(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLPCR_BYPASS_LPM_HS0_SHIFT)) & CCM_CLPCR_BYPASS_LPM_HS0_MASK) +#define CCM_CLPCR_MASK_CORE0_WFI_MASK (0x400000U) +#define CCM_CLPCR_MASK_CORE0_WFI_SHIFT (22U) +/*! MASK_CORE0_WFI + * 0b0..WFI of core0 is not masked + * 0b1..WFI of core0 is masked + */ +#define CCM_CLPCR_MASK_CORE0_WFI(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLPCR_MASK_CORE0_WFI_SHIFT)) & CCM_CLPCR_MASK_CORE0_WFI_MASK) +#define CCM_CLPCR_MASK_SCU_IDLE_MASK (0x4000000U) +#define CCM_CLPCR_MASK_SCU_IDLE_SHIFT (26U) +/*! MASK_SCU_IDLE + * 0b1..SCU IDLE is masked + * 0b0..SCU IDLE is not masked + */ +#define CCM_CLPCR_MASK_SCU_IDLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLPCR_MASK_SCU_IDLE_SHIFT)) & CCM_CLPCR_MASK_SCU_IDLE_MASK) +#define CCM_CLPCR_MASK_L2CC_IDLE_MASK (0x8000000U) +#define CCM_CLPCR_MASK_L2CC_IDLE_SHIFT (27U) +/*! MASK_L2CC_IDLE + * 0b1..L2CC IDLE is masked + * 0b0..L2CC IDLE is not masked + */ +#define CCM_CLPCR_MASK_L2CC_IDLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLPCR_MASK_L2CC_IDLE_SHIFT)) & CCM_CLPCR_MASK_L2CC_IDLE_MASK) +/*! @} */ + +/*! @name CISR - CCM Interrupt Status Register */ +/*! @{ */ +#define CCM_CISR_LRF_PLL_MASK (0x1U) +#define CCM_CISR_LRF_PLL_SHIFT (0U) +/*! LRF_PLL + * 0b0..interrupt is not generated due to lock ready of all enabled and not bypaseed PLLs + * 0b1..interrupt generated due to lock ready of all enabled and not bypaseed PLLs + */ +#define CCM_CISR_LRF_PLL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CISR_LRF_PLL_SHIFT)) & CCM_CISR_LRF_PLL_MASK) +#define CCM_CISR_COSC_READY_MASK (0x40U) +#define CCM_CISR_COSC_READY_SHIFT (6U) +/*! COSC_READY + * 0b0..interrupt is not generated due to on board oscillator ready + * 0b1..interrupt generated due to on board oscillator ready + */ +#define CCM_CISR_COSC_READY(x) (((uint32_t)(((uint32_t)(x)) << CCM_CISR_COSC_READY_SHIFT)) & CCM_CISR_COSC_READY_MASK) +#define CCM_CISR_SEMC_PODF_LOADED_MASK (0x20000U) +#define CCM_CISR_SEMC_PODF_LOADED_SHIFT (17U) +/*! SEMC_PODF_LOADED + * 0b0..interrupt is not generated due to frequency change of semc_podf + * 0b1..interrupt generated due to frequency change of semc_podf + */ +#define CCM_CISR_SEMC_PODF_LOADED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CISR_SEMC_PODF_LOADED_SHIFT)) & CCM_CISR_SEMC_PODF_LOADED_MASK) +#define CCM_CISR_PERIPH2_CLK_SEL_LOADED_MASK (0x80000U) +#define CCM_CISR_PERIPH2_CLK_SEL_LOADED_SHIFT (19U) +/*! PERIPH2_CLK_SEL_LOADED + * 0b0..interrupt is not generated due to frequency change of periph2_clk_sel + * 0b1..interrupt generated due to frequency change of periph2_clk_sel + */ +#define CCM_CISR_PERIPH2_CLK_SEL_LOADED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CISR_PERIPH2_CLK_SEL_LOADED_SHIFT)) & CCM_CISR_PERIPH2_CLK_SEL_LOADED_MASK) +#define CCM_CISR_AHB_PODF_LOADED_MASK (0x100000U) +#define CCM_CISR_AHB_PODF_LOADED_SHIFT (20U) +/*! AHB_PODF_LOADED + * 0b0..interrupt is not generated due to frequency change of ahb_podf + * 0b1..interrupt generated due to frequency change of ahb_podf + */ +#define CCM_CISR_AHB_PODF_LOADED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CISR_AHB_PODF_LOADED_SHIFT)) & CCM_CISR_AHB_PODF_LOADED_MASK) +#define CCM_CISR_PERIPH_CLK_SEL_LOADED_MASK (0x400000U) +#define CCM_CISR_PERIPH_CLK_SEL_LOADED_SHIFT (22U) +/*! PERIPH_CLK_SEL_LOADED + * 0b0..interrupt is not generated due to update of periph_clk_sel. + * 0b1..interrupt generated due to update of periph_clk_sel. + */ +#define CCM_CISR_PERIPH_CLK_SEL_LOADED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CISR_PERIPH_CLK_SEL_LOADED_SHIFT)) & CCM_CISR_PERIPH_CLK_SEL_LOADED_MASK) +#define CCM_CISR_ARM_PODF_LOADED_MASK (0x4000000U) +#define CCM_CISR_ARM_PODF_LOADED_SHIFT (26U) +/*! ARM_PODF_LOADED + * 0b0..interrupt is not generated due to frequency change of arm_podf + * 0b1..interrupt generated due to frequency change of arm_podf + */ +#define CCM_CISR_ARM_PODF_LOADED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CISR_ARM_PODF_LOADED_SHIFT)) & CCM_CISR_ARM_PODF_LOADED_MASK) +/*! @} */ + +/*! @name CIMR - CCM Interrupt Mask Register */ +/*! @{ */ +#define CCM_CIMR_MASK_LRF_PLL_MASK (0x1U) +#define CCM_CIMR_MASK_LRF_PLL_SHIFT (0U) +/*! MASK_LRF_PLL + * 0b0..don't mask interrupt due to lrf of PLLs - interrupt will be created + * 0b1..mask interrupt due to lrf of PLLs + */ +#define CCM_CIMR_MASK_LRF_PLL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CIMR_MASK_LRF_PLL_SHIFT)) & CCM_CIMR_MASK_LRF_PLL_MASK) +#define CCM_CIMR_MASK_COSC_READY_MASK (0x40U) +#define CCM_CIMR_MASK_COSC_READY_SHIFT (6U) +/*! MASK_COSC_READY + * 0b0..don't mask interrupt due to on board oscillator ready - interrupt will be created + * 0b1..mask interrupt due to on board oscillator ready + */ +#define CCM_CIMR_MASK_COSC_READY(x) (((uint32_t)(((uint32_t)(x)) << CCM_CIMR_MASK_COSC_READY_SHIFT)) & CCM_CIMR_MASK_COSC_READY_MASK) +#define CCM_CIMR_MASK_SEMC_PODF_LOADED_MASK (0x20000U) +#define CCM_CIMR_MASK_SEMC_PODF_LOADED_SHIFT (17U) +/*! MASK_SEMC_PODF_LOADED + * 0b0..don't mask interrupt due to frequency change of semc_podf - interrupt will be created + * 0b1..mask interrupt due to frequency change of semc_podf + */ +#define CCM_CIMR_MASK_SEMC_PODF_LOADED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CIMR_MASK_SEMC_PODF_LOADED_SHIFT)) & CCM_CIMR_MASK_SEMC_PODF_LOADED_MASK) +#define CCM_CIMR_MASK_PERIPH2_CLK_SEL_LOADED_MASK (0x80000U) +#define CCM_CIMR_MASK_PERIPH2_CLK_SEL_LOADED_SHIFT (19U) +/*! MASK_PERIPH2_CLK_SEL_LOADED + * 0b0..don't mask interrupt due to update of periph2_clk_sel - interrupt will be created + * 0b1..mask interrupt due to update of periph2_clk_sel + */ +#define CCM_CIMR_MASK_PERIPH2_CLK_SEL_LOADED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CIMR_MASK_PERIPH2_CLK_SEL_LOADED_SHIFT)) & CCM_CIMR_MASK_PERIPH2_CLK_SEL_LOADED_MASK) +#define CCM_CIMR_MASK_AHB_PODF_LOADED_MASK (0x100000U) +#define CCM_CIMR_MASK_AHB_PODF_LOADED_SHIFT (20U) +/*! MASK_AHB_PODF_LOADED + * 0b0..don't mask interrupt due to frequency change of ahb_podf - interrupt will be created + * 0b1..mask interrupt due to frequency change of ahb_podf + */ +#define CCM_CIMR_MASK_AHB_PODF_LOADED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CIMR_MASK_AHB_PODF_LOADED_SHIFT)) & CCM_CIMR_MASK_AHB_PODF_LOADED_MASK) +#define CCM_CIMR_MASK_PERIPH_CLK_SEL_LOADED_MASK (0x400000U) +#define CCM_CIMR_MASK_PERIPH_CLK_SEL_LOADED_SHIFT (22U) +/*! MASK_PERIPH_CLK_SEL_LOADED + * 0b0..don't mask interrupt due to update of periph_clk_sel - interrupt will be created + * 0b1..mask interrupt due to update of periph_clk_sel + */ +#define CCM_CIMR_MASK_PERIPH_CLK_SEL_LOADED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CIMR_MASK_PERIPH_CLK_SEL_LOADED_SHIFT)) & CCM_CIMR_MASK_PERIPH_CLK_SEL_LOADED_MASK) +#define CCM_CIMR_ARM_PODF_LOADED_MASK (0x4000000U) +#define CCM_CIMR_ARM_PODF_LOADED_SHIFT (26U) +/*! ARM_PODF_LOADED + * 0b0..don't mask interrupt due to frequency change of arm_podf - interrupt will be created + * 0b1..mask interrupt due to frequency change of arm_podf + */ +#define CCM_CIMR_ARM_PODF_LOADED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CIMR_ARM_PODF_LOADED_SHIFT)) & CCM_CIMR_ARM_PODF_LOADED_MASK) +/*! @} */ + +/*! @name CCOSR - CCM Clock Output Source Register */ +/*! @{ */ +#define CCM_CCOSR_CLKO1_SEL_MASK (0xFU) +#define CCM_CCOSR_CLKO1_SEL_SHIFT (0U) +/*! CLKO1_SEL + * 0b0000..USB1 PLL clock (divided by 2) + * 0b0001..SYS PLL clock (divided by 2) + * 0b0011..VIDEO PLL clock (divided by 2) + * 0b0101..semc_clk_root + * 0b0110..Reserved + * 0b1010..lcdif_pix_clk_root + * 0b1011..ahb_clk_root + * 0b1100..ipg_clk_root + * 0b1101..perclk_root + * 0b1110..ckil_sync_clk_root + * 0b1111..pll4_main_clk + */ +#define CCM_CCOSR_CLKO1_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCOSR_CLKO1_SEL_SHIFT)) & CCM_CCOSR_CLKO1_SEL_MASK) +#define CCM_CCOSR_CLKO1_DIV_MASK (0x70U) +#define CCM_CCOSR_CLKO1_DIV_SHIFT (4U) +/*! CLKO1_DIV + * 0b000..divide by 1 + * 0b001..divide by 2 + * 0b010..divide by 3 + * 0b011..divide by 4 + * 0b100..divide by 5 + * 0b101..divide by 6 + * 0b110..divide by 7 + * 0b111..divide by 8 + */ +#define CCM_CCOSR_CLKO1_DIV(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCOSR_CLKO1_DIV_SHIFT)) & CCM_CCOSR_CLKO1_DIV_MASK) +#define CCM_CCOSR_CLKO1_EN_MASK (0x80U) +#define CCM_CCOSR_CLKO1_EN_SHIFT (7U) +/*! CLKO1_EN + * 0b0..CCM_CLKO1 disabled. + * 0b1..CCM_CLKO1 enabled. + */ +#define CCM_CCOSR_CLKO1_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCOSR_CLKO1_EN_SHIFT)) & CCM_CCOSR_CLKO1_EN_MASK) +#define CCM_CCOSR_CLK_OUT_SEL_MASK (0x100U) +#define CCM_CCOSR_CLK_OUT_SEL_SHIFT (8U) +/*! CLK_OUT_SEL + * 0b0..CCM_CLKO1 output drives CCM_CLKO1 clock + * 0b1..CCM_CLKO1 output drives CCM_CLKO2 clock + */ +#define CCM_CCOSR_CLK_OUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCOSR_CLK_OUT_SEL_SHIFT)) & CCM_CCOSR_CLK_OUT_SEL_MASK) +#define CCM_CCOSR_CLKO2_SEL_MASK (0x1F0000U) +#define CCM_CCOSR_CLKO2_SEL_SHIFT (16U) +/*! CLKO2_SEL + * 0b00011..usdhc1_clk_root + * 0b00101..wrck_clk_root + * 0b00110..lpi2c_clk_root + * 0b01011..csi_clk_root + * 0b01110..osc_clk + * 0b10001..usdhc2_clk_root + * 0b10010..sai1_clk_root + * 0b10011..sai2_clk_root + * 0b10100..sai3_clk_root + * 0b10111..can_clk_root + * 0b11011..flexspi_clk_root + * 0b11100..uart_clk_root + * 0b11101..spdif0_clk_root + * 0b11111..Reserved + */ +#define CCM_CCOSR_CLKO2_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCOSR_CLKO2_SEL_SHIFT)) & CCM_CCOSR_CLKO2_SEL_MASK) +#define CCM_CCOSR_CLKO2_DIV_MASK (0xE00000U) +#define CCM_CCOSR_CLKO2_DIV_SHIFT (21U) +/*! CLKO2_DIV + * 0b000..divide by 1 + * 0b001..divide by 2 + * 0b010..divide by 3 + * 0b011..divide by 4 + * 0b100..divide by 5 + * 0b101..divide by 6 + * 0b110..divide by 7 + * 0b111..divide by 8 + */ +#define CCM_CCOSR_CLKO2_DIV(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCOSR_CLKO2_DIV_SHIFT)) & CCM_CCOSR_CLKO2_DIV_MASK) +#define CCM_CCOSR_CLKO2_EN_MASK (0x1000000U) +#define CCM_CCOSR_CLKO2_EN_SHIFT (24U) +/*! CLKO2_EN + * 0b0..CCM_CLKO2 disabled. + * 0b1..CCM_CLKO2 enabled. + */ +#define CCM_CCOSR_CLKO2_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCOSR_CLKO2_EN_SHIFT)) & CCM_CCOSR_CLKO2_EN_MASK) +/*! @} */ + +/*! @name CGPR - CCM General Purpose Register */ +/*! @{ */ +#define CCM_CGPR_PMIC_DELAY_SCALER_MASK (0x1U) +#define CCM_CGPR_PMIC_DELAY_SCALER_SHIFT (0U) +/*! PMIC_DELAY_SCALER + * 0b0..clock is not divided + * 0b1..clock is divided /8 + */ +#define CCM_CGPR_PMIC_DELAY_SCALER(x) (((uint32_t)(((uint32_t)(x)) << CCM_CGPR_PMIC_DELAY_SCALER_SHIFT)) & CCM_CGPR_PMIC_DELAY_SCALER_MASK) +#define CCM_CGPR_EFUSE_PROG_SUPPLY_GATE_MASK (0x10U) +#define CCM_CGPR_EFUSE_PROG_SUPPLY_GATE_SHIFT (4U) +/*! EFUSE_PROG_SUPPLY_GATE + * 0b0..fuse programing supply voltage is gated off to the efuse module + * 0b1..allow fuse programing. + */ +#define CCM_CGPR_EFUSE_PROG_SUPPLY_GATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_CGPR_EFUSE_PROG_SUPPLY_GATE_SHIFT)) & CCM_CGPR_EFUSE_PROG_SUPPLY_GATE_MASK) +#define CCM_CGPR_SYS_MEM_DS_CTRL_MASK (0xC000U) +#define CCM_CGPR_SYS_MEM_DS_CTRL_SHIFT (14U) +/*! SYS_MEM_DS_CTRL + * 0b00..Disable memory DS mode always + * 0b01..Enable memory (outside ARM platform) DS mode when system STOP and PLL are disabled + * 0b1x..enable memory (outside ARM platform) DS mode when system is in STOP mode + */ +#define CCM_CGPR_SYS_MEM_DS_CTRL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CGPR_SYS_MEM_DS_CTRL_SHIFT)) & CCM_CGPR_SYS_MEM_DS_CTRL_MASK) +#define CCM_CGPR_FPL_MASK (0x10000U) +#define CCM_CGPR_FPL_SHIFT (16U) +/*! FPL - Fast PLL enable. + * 0b0..Engage PLL enable default way. + * 0b1..Engage PLL enable 3 CKIL clocks earlier at exiting low power mode (STOP). Should be used only if 24MHz OSC was active in low power mode. + */ +#define CCM_CGPR_FPL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CGPR_FPL_SHIFT)) & CCM_CGPR_FPL_MASK) +#define CCM_CGPR_INT_MEM_CLK_LPM_MASK (0x20000U) +#define CCM_CGPR_INT_MEM_CLK_LPM_SHIFT (17U) +/*! INT_MEM_CLK_LPM + * 0b0..Disable the clock to the ARM platform memories when entering Low Power Mode + * 0b1..Keep the clocks to the ARM platform memories enabled only if an interrupt is pending when entering Low Power Modes (WAIT and STOP without power gating) + */ +#define CCM_CGPR_INT_MEM_CLK_LPM(x) (((uint32_t)(((uint32_t)(x)) << CCM_CGPR_INT_MEM_CLK_LPM_SHIFT)) & CCM_CGPR_INT_MEM_CLK_LPM_MASK) +/*! @} */ + +/*! @name CCGR0 - CCM Clock Gating Register 0 */ +/*! @{ */ +#define CCM_CCGR0_CG0_MASK (0x3U) +#define CCM_CCGR0_CG0_SHIFT (0U) +#define CCM_CCGR0_CG0(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG0_SHIFT)) & CCM_CCGR0_CG0_MASK) +#define CCM_CCGR0_CG1_MASK (0xCU) +#define CCM_CCGR0_CG1_SHIFT (2U) +#define CCM_CCGR0_CG1(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG1_SHIFT)) & CCM_CCGR0_CG1_MASK) +#define CCM_CCGR0_CG2_MASK (0x30U) +#define CCM_CCGR0_CG2_SHIFT (4U) +#define CCM_CCGR0_CG2(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG2_SHIFT)) & CCM_CCGR0_CG2_MASK) +#define CCM_CCGR0_CG3_MASK (0xC0U) +#define CCM_CCGR0_CG3_SHIFT (6U) +#define CCM_CCGR0_CG3(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG3_SHIFT)) & CCM_CCGR0_CG3_MASK) +#define CCM_CCGR0_CG4_MASK (0x300U) +#define CCM_CCGR0_CG4_SHIFT (8U) +#define CCM_CCGR0_CG4(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG4_SHIFT)) & CCM_CCGR0_CG4_MASK) +#define CCM_CCGR0_CG5_MASK (0xC00U) +#define CCM_CCGR0_CG5_SHIFT (10U) +#define CCM_CCGR0_CG5(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG5_SHIFT)) & CCM_CCGR0_CG5_MASK) +#define CCM_CCGR0_CG6_MASK (0x3000U) +#define CCM_CCGR0_CG6_SHIFT (12U) +#define CCM_CCGR0_CG6(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG6_SHIFT)) & CCM_CCGR0_CG6_MASK) +#define CCM_CCGR0_CG7_MASK (0xC000U) +#define CCM_CCGR0_CG7_SHIFT (14U) +#define CCM_CCGR0_CG7(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG7_SHIFT)) & CCM_CCGR0_CG7_MASK) +#define CCM_CCGR0_CG8_MASK (0x30000U) +#define CCM_CCGR0_CG8_SHIFT (16U) +#define CCM_CCGR0_CG8(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG8_SHIFT)) & CCM_CCGR0_CG8_MASK) +#define CCM_CCGR0_CG9_MASK (0xC0000U) +#define CCM_CCGR0_CG9_SHIFT (18U) +#define CCM_CCGR0_CG9(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG9_SHIFT)) & CCM_CCGR0_CG9_MASK) +#define CCM_CCGR0_CG10_MASK (0x300000U) +#define CCM_CCGR0_CG10_SHIFT (20U) +#define CCM_CCGR0_CG10(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG10_SHIFT)) & CCM_CCGR0_CG10_MASK) +#define CCM_CCGR0_CG11_MASK (0xC00000U) +#define CCM_CCGR0_CG11_SHIFT (22U) +#define CCM_CCGR0_CG11(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG11_SHIFT)) & CCM_CCGR0_CG11_MASK) +#define CCM_CCGR0_CG12_MASK (0x3000000U) +#define CCM_CCGR0_CG12_SHIFT (24U) +#define CCM_CCGR0_CG12(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG12_SHIFT)) & CCM_CCGR0_CG12_MASK) +#define CCM_CCGR0_CG13_MASK (0xC000000U) +#define CCM_CCGR0_CG13_SHIFT (26U) +#define CCM_CCGR0_CG13(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG13_SHIFT)) & CCM_CCGR0_CG13_MASK) +#define CCM_CCGR0_CG14_MASK (0x30000000U) +#define CCM_CCGR0_CG14_SHIFT (28U) +#define CCM_CCGR0_CG14(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG14_SHIFT)) & CCM_CCGR0_CG14_MASK) +#define CCM_CCGR0_CG15_MASK (0xC0000000U) +#define CCM_CCGR0_CG15_SHIFT (30U) +#define CCM_CCGR0_CG15(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG15_SHIFT)) & CCM_CCGR0_CG15_MASK) +/*! @} */ + +/*! @name CCGR1 - CCM Clock Gating Register 1 */ +/*! @{ */ +#define CCM_CCGR1_CG0_MASK (0x3U) +#define CCM_CCGR1_CG0_SHIFT (0U) +#define CCM_CCGR1_CG0(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG0_SHIFT)) & CCM_CCGR1_CG0_MASK) +#define CCM_CCGR1_CG1_MASK (0xCU) +#define CCM_CCGR1_CG1_SHIFT (2U) +#define CCM_CCGR1_CG1(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG1_SHIFT)) & CCM_CCGR1_CG1_MASK) +#define CCM_CCGR1_CG2_MASK (0x30U) +#define CCM_CCGR1_CG2_SHIFT (4U) +#define CCM_CCGR1_CG2(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG2_SHIFT)) & CCM_CCGR1_CG2_MASK) +#define CCM_CCGR1_CG3_MASK (0xC0U) +#define CCM_CCGR1_CG3_SHIFT (6U) +#define CCM_CCGR1_CG3(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG3_SHIFT)) & CCM_CCGR1_CG3_MASK) +#define CCM_CCGR1_CG4_MASK (0x300U) +#define CCM_CCGR1_CG4_SHIFT (8U) +#define CCM_CCGR1_CG4(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG4_SHIFT)) & CCM_CCGR1_CG4_MASK) +#define CCM_CCGR1_CG5_MASK (0xC00U) +#define CCM_CCGR1_CG5_SHIFT (10U) +#define CCM_CCGR1_CG5(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG5_SHIFT)) & CCM_CCGR1_CG5_MASK) +#define CCM_CCGR1_CG6_MASK (0x3000U) +#define CCM_CCGR1_CG6_SHIFT (12U) +#define CCM_CCGR1_CG6(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG6_SHIFT)) & CCM_CCGR1_CG6_MASK) +#define CCM_CCGR1_CG7_MASK (0xC000U) +#define CCM_CCGR1_CG7_SHIFT (14U) +#define CCM_CCGR1_CG7(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG7_SHIFT)) & CCM_CCGR1_CG7_MASK) +#define CCM_CCGR1_CG8_MASK (0x30000U) +#define CCM_CCGR1_CG8_SHIFT (16U) +#define CCM_CCGR1_CG8(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG8_SHIFT)) & CCM_CCGR1_CG8_MASK) +#define CCM_CCGR1_CG9_MASK (0xC0000U) +#define CCM_CCGR1_CG9_SHIFT (18U) +#define CCM_CCGR1_CG9(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG9_SHIFT)) & CCM_CCGR1_CG9_MASK) +#define CCM_CCGR1_CG10_MASK (0x300000U) +#define CCM_CCGR1_CG10_SHIFT (20U) +#define CCM_CCGR1_CG10(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG10_SHIFT)) & CCM_CCGR1_CG10_MASK) +#define CCM_CCGR1_CG11_MASK (0xC00000U) +#define CCM_CCGR1_CG11_SHIFT (22U) +#define CCM_CCGR1_CG11(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG11_SHIFT)) & CCM_CCGR1_CG11_MASK) +#define CCM_CCGR1_CG12_MASK (0x3000000U) +#define CCM_CCGR1_CG12_SHIFT (24U) +#define CCM_CCGR1_CG12(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG12_SHIFT)) & CCM_CCGR1_CG12_MASK) +#define CCM_CCGR1_CG13_MASK (0xC000000U) +#define CCM_CCGR1_CG13_SHIFT (26U) +#define CCM_CCGR1_CG13(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG13_SHIFT)) & CCM_CCGR1_CG13_MASK) +#define CCM_CCGR1_CG14_MASK (0x30000000U) +#define CCM_CCGR1_CG14_SHIFT (28U) +#define CCM_CCGR1_CG14(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG14_SHIFT)) & CCM_CCGR1_CG14_MASK) +#define CCM_CCGR1_CG15_MASK (0xC0000000U) +#define CCM_CCGR1_CG15_SHIFT (30U) +#define CCM_CCGR1_CG15(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG15_SHIFT)) & CCM_CCGR1_CG15_MASK) +/*! @} */ + +/*! @name CCGR2 - CCM Clock Gating Register 2 */ +/*! @{ */ +#define CCM_CCGR2_CG0_MASK (0x3U) +#define CCM_CCGR2_CG0_SHIFT (0U) +#define CCM_CCGR2_CG0(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG0_SHIFT)) & CCM_CCGR2_CG0_MASK) +#define CCM_CCGR2_CG1_MASK (0xCU) +#define CCM_CCGR2_CG1_SHIFT (2U) +#define CCM_CCGR2_CG1(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG1_SHIFT)) & CCM_CCGR2_CG1_MASK) +#define CCM_CCGR2_CG2_MASK (0x30U) +#define CCM_CCGR2_CG2_SHIFT (4U) +#define CCM_CCGR2_CG2(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG2_SHIFT)) & CCM_CCGR2_CG2_MASK) +#define CCM_CCGR2_CG3_MASK (0xC0U) +#define CCM_CCGR2_CG3_SHIFT (6U) +#define CCM_CCGR2_CG3(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG3_SHIFT)) & CCM_CCGR2_CG3_MASK) +#define CCM_CCGR2_CG4_MASK (0x300U) +#define CCM_CCGR2_CG4_SHIFT (8U) +#define CCM_CCGR2_CG4(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG4_SHIFT)) & CCM_CCGR2_CG4_MASK) +#define CCM_CCGR2_CG5_MASK (0xC00U) +#define CCM_CCGR2_CG5_SHIFT (10U) +#define CCM_CCGR2_CG5(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG5_SHIFT)) & CCM_CCGR2_CG5_MASK) +#define CCM_CCGR2_CG6_MASK (0x3000U) +#define CCM_CCGR2_CG6_SHIFT (12U) +#define CCM_CCGR2_CG6(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG6_SHIFT)) & CCM_CCGR2_CG6_MASK) +#define CCM_CCGR2_CG7_MASK (0xC000U) +#define CCM_CCGR2_CG7_SHIFT (14U) +#define CCM_CCGR2_CG7(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG7_SHIFT)) & CCM_CCGR2_CG7_MASK) +#define CCM_CCGR2_CG8_MASK (0x30000U) +#define CCM_CCGR2_CG8_SHIFT (16U) +#define CCM_CCGR2_CG8(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG8_SHIFT)) & CCM_CCGR2_CG8_MASK) +#define CCM_CCGR2_CG9_MASK (0xC0000U) +#define CCM_CCGR2_CG9_SHIFT (18U) +#define CCM_CCGR2_CG9(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG9_SHIFT)) & CCM_CCGR2_CG9_MASK) +#define CCM_CCGR2_CG10_MASK (0x300000U) +#define CCM_CCGR2_CG10_SHIFT (20U) +#define CCM_CCGR2_CG10(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG10_SHIFT)) & CCM_CCGR2_CG10_MASK) +#define CCM_CCGR2_CG11_MASK (0xC00000U) +#define CCM_CCGR2_CG11_SHIFT (22U) +#define CCM_CCGR2_CG11(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG11_SHIFT)) & CCM_CCGR2_CG11_MASK) +#define CCM_CCGR2_CG12_MASK (0x3000000U) +#define CCM_CCGR2_CG12_SHIFT (24U) +#define CCM_CCGR2_CG12(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG12_SHIFT)) & CCM_CCGR2_CG12_MASK) +#define CCM_CCGR2_CG13_MASK (0xC000000U) +#define CCM_CCGR2_CG13_SHIFT (26U) +#define CCM_CCGR2_CG13(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG13_SHIFT)) & CCM_CCGR2_CG13_MASK) +#define CCM_CCGR2_CG14_MASK (0x30000000U) +#define CCM_CCGR2_CG14_SHIFT (28U) +#define CCM_CCGR2_CG14(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG14_SHIFT)) & CCM_CCGR2_CG14_MASK) +#define CCM_CCGR2_CG15_MASK (0xC0000000U) +#define CCM_CCGR2_CG15_SHIFT (30U) +#define CCM_CCGR2_CG15(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG15_SHIFT)) & CCM_CCGR2_CG15_MASK) +/*! @} */ + +/*! @name CCGR3 - CCM Clock Gating Register 3 */ +/*! @{ */ +#define CCM_CCGR3_CG0_MASK (0x3U) +#define CCM_CCGR3_CG0_SHIFT (0U) +#define CCM_CCGR3_CG0(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG0_SHIFT)) & CCM_CCGR3_CG0_MASK) +#define CCM_CCGR3_CG1_MASK (0xCU) +#define CCM_CCGR3_CG1_SHIFT (2U) +#define CCM_CCGR3_CG1(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG1_SHIFT)) & CCM_CCGR3_CG1_MASK) +#define CCM_CCGR3_CG2_MASK (0x30U) +#define CCM_CCGR3_CG2_SHIFT (4U) +#define CCM_CCGR3_CG2(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG2_SHIFT)) & CCM_CCGR3_CG2_MASK) +#define CCM_CCGR3_CG3_MASK (0xC0U) +#define CCM_CCGR3_CG3_SHIFT (6U) +#define CCM_CCGR3_CG3(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG3_SHIFT)) & CCM_CCGR3_CG3_MASK) +#define CCM_CCGR3_CG4_MASK (0x300U) +#define CCM_CCGR3_CG4_SHIFT (8U) +#define CCM_CCGR3_CG4(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG4_SHIFT)) & CCM_CCGR3_CG4_MASK) +#define CCM_CCGR3_CG5_MASK (0xC00U) +#define CCM_CCGR3_CG5_SHIFT (10U) +#define CCM_CCGR3_CG5(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG5_SHIFT)) & CCM_CCGR3_CG5_MASK) +#define CCM_CCGR3_CG6_MASK (0x3000U) +#define CCM_CCGR3_CG6_SHIFT (12U) +#define CCM_CCGR3_CG6(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG6_SHIFT)) & CCM_CCGR3_CG6_MASK) +#define CCM_CCGR3_CG7_MASK (0xC000U) +#define CCM_CCGR3_CG7_SHIFT (14U) +#define CCM_CCGR3_CG7(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG7_SHIFT)) & CCM_CCGR3_CG7_MASK) +#define CCM_CCGR3_CG8_MASK (0x30000U) +#define CCM_CCGR3_CG8_SHIFT (16U) +#define CCM_CCGR3_CG8(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG8_SHIFT)) & CCM_CCGR3_CG8_MASK) +#define CCM_CCGR3_CG9_MASK (0xC0000U) +#define CCM_CCGR3_CG9_SHIFT (18U) +#define CCM_CCGR3_CG9(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG9_SHIFT)) & CCM_CCGR3_CG9_MASK) +#define CCM_CCGR3_CG10_MASK (0x300000U) +#define CCM_CCGR3_CG10_SHIFT (20U) +#define CCM_CCGR3_CG10(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG10_SHIFT)) & CCM_CCGR3_CG10_MASK) +#define CCM_CCGR3_CG11_MASK (0xC00000U) +#define CCM_CCGR3_CG11_SHIFT (22U) +#define CCM_CCGR3_CG11(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG11_SHIFT)) & CCM_CCGR3_CG11_MASK) +#define CCM_CCGR3_CG12_MASK (0x3000000U) +#define CCM_CCGR3_CG12_SHIFT (24U) +#define CCM_CCGR3_CG12(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG12_SHIFT)) & CCM_CCGR3_CG12_MASK) +#define CCM_CCGR3_CG13_MASK (0xC000000U) +#define CCM_CCGR3_CG13_SHIFT (26U) +#define CCM_CCGR3_CG13(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG13_SHIFT)) & CCM_CCGR3_CG13_MASK) +#define CCM_CCGR3_CG14_MASK (0x30000000U) +#define CCM_CCGR3_CG14_SHIFT (28U) +#define CCM_CCGR3_CG14(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG14_SHIFT)) & CCM_CCGR3_CG14_MASK) +#define CCM_CCGR3_CG15_MASK (0xC0000000U) +#define CCM_CCGR3_CG15_SHIFT (30U) +#define CCM_CCGR3_CG15(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG15_SHIFT)) & CCM_CCGR3_CG15_MASK) +/*! @} */ + +/*! @name CCGR4 - CCM Clock Gating Register 4 */ +/*! @{ */ +#define CCM_CCGR4_CG0_MASK (0x3U) +#define CCM_CCGR4_CG0_SHIFT (0U) +#define CCM_CCGR4_CG0(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG0_SHIFT)) & CCM_CCGR4_CG0_MASK) +#define CCM_CCGR4_CG1_MASK (0xCU) +#define CCM_CCGR4_CG1_SHIFT (2U) +#define CCM_CCGR4_CG1(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG1_SHIFT)) & CCM_CCGR4_CG1_MASK) +#define CCM_CCGR4_CG2_MASK (0x30U) +#define CCM_CCGR4_CG2_SHIFT (4U) +#define CCM_CCGR4_CG2(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG2_SHIFT)) & CCM_CCGR4_CG2_MASK) +#define CCM_CCGR4_CG3_MASK (0xC0U) +#define CCM_CCGR4_CG3_SHIFT (6U) +#define CCM_CCGR4_CG3(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG3_SHIFT)) & CCM_CCGR4_CG3_MASK) +#define CCM_CCGR4_CG4_MASK (0x300U) +#define CCM_CCGR4_CG4_SHIFT (8U) +#define CCM_CCGR4_CG4(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG4_SHIFT)) & CCM_CCGR4_CG4_MASK) +#define CCM_CCGR4_CG5_MASK (0xC00U) +#define CCM_CCGR4_CG5_SHIFT (10U) +#define CCM_CCGR4_CG5(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG5_SHIFT)) & CCM_CCGR4_CG5_MASK) +#define CCM_CCGR4_CG6_MASK (0x3000U) +#define CCM_CCGR4_CG6_SHIFT (12U) +#define CCM_CCGR4_CG6(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG6_SHIFT)) & CCM_CCGR4_CG6_MASK) +#define CCM_CCGR4_CG7_MASK (0xC000U) +#define CCM_CCGR4_CG7_SHIFT (14U) +#define CCM_CCGR4_CG7(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG7_SHIFT)) & CCM_CCGR4_CG7_MASK) +#define CCM_CCGR4_CG8_MASK (0x30000U) +#define CCM_CCGR4_CG8_SHIFT (16U) +#define CCM_CCGR4_CG8(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG8_SHIFT)) & CCM_CCGR4_CG8_MASK) +#define CCM_CCGR4_CG9_MASK (0xC0000U) +#define CCM_CCGR4_CG9_SHIFT (18U) +#define CCM_CCGR4_CG9(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG9_SHIFT)) & CCM_CCGR4_CG9_MASK) +#define CCM_CCGR4_CG10_MASK (0x300000U) +#define CCM_CCGR4_CG10_SHIFT (20U) +#define CCM_CCGR4_CG10(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG10_SHIFT)) & CCM_CCGR4_CG10_MASK) +#define CCM_CCGR4_CG11_MASK (0xC00000U) +#define CCM_CCGR4_CG11_SHIFT (22U) +#define CCM_CCGR4_CG11(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG11_SHIFT)) & CCM_CCGR4_CG11_MASK) +#define CCM_CCGR4_CG12_MASK (0x3000000U) +#define CCM_CCGR4_CG12_SHIFT (24U) +#define CCM_CCGR4_CG12(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG12_SHIFT)) & CCM_CCGR4_CG12_MASK) +#define CCM_CCGR4_CG13_MASK (0xC000000U) +#define CCM_CCGR4_CG13_SHIFT (26U) +#define CCM_CCGR4_CG13(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG13_SHIFT)) & CCM_CCGR4_CG13_MASK) +#define CCM_CCGR4_CG14_MASK (0x30000000U) +#define CCM_CCGR4_CG14_SHIFT (28U) +#define CCM_CCGR4_CG14(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG14_SHIFT)) & CCM_CCGR4_CG14_MASK) +#define CCM_CCGR4_CG15_MASK (0xC0000000U) +#define CCM_CCGR4_CG15_SHIFT (30U) +#define CCM_CCGR4_CG15(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG15_SHIFT)) & CCM_CCGR4_CG15_MASK) +/*! @} */ + +/*! @name CCGR5 - CCM Clock Gating Register 5 */ +/*! @{ */ +#define CCM_CCGR5_CG0_MASK (0x3U) +#define CCM_CCGR5_CG0_SHIFT (0U) +#define CCM_CCGR5_CG0(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG0_SHIFT)) & CCM_CCGR5_CG0_MASK) +#define CCM_CCGR5_CG1_MASK (0xCU) +#define CCM_CCGR5_CG1_SHIFT (2U) +#define CCM_CCGR5_CG1(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG1_SHIFT)) & CCM_CCGR5_CG1_MASK) +#define CCM_CCGR5_CG2_MASK (0x30U) +#define CCM_CCGR5_CG2_SHIFT (4U) +#define CCM_CCGR5_CG2(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG2_SHIFT)) & CCM_CCGR5_CG2_MASK) +#define CCM_CCGR5_CG3_MASK (0xC0U) +#define CCM_CCGR5_CG3_SHIFT (6U) +#define CCM_CCGR5_CG3(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG3_SHIFT)) & CCM_CCGR5_CG3_MASK) +#define CCM_CCGR5_CG4_MASK (0x300U) +#define CCM_CCGR5_CG4_SHIFT (8U) +#define CCM_CCGR5_CG4(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG4_SHIFT)) & CCM_CCGR5_CG4_MASK) +#define CCM_CCGR5_CG5_MASK (0xC00U) +#define CCM_CCGR5_CG5_SHIFT (10U) +#define CCM_CCGR5_CG5(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG5_SHIFT)) & CCM_CCGR5_CG5_MASK) +#define CCM_CCGR5_CG6_MASK (0x3000U) +#define CCM_CCGR5_CG6_SHIFT (12U) +#define CCM_CCGR5_CG6(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG6_SHIFT)) & CCM_CCGR5_CG6_MASK) +#define CCM_CCGR5_CG7_MASK (0xC000U) +#define CCM_CCGR5_CG7_SHIFT (14U) +#define CCM_CCGR5_CG7(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG7_SHIFT)) & CCM_CCGR5_CG7_MASK) +#define CCM_CCGR5_CG8_MASK (0x30000U) +#define CCM_CCGR5_CG8_SHIFT (16U) +#define CCM_CCGR5_CG8(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG8_SHIFT)) & CCM_CCGR5_CG8_MASK) +#define CCM_CCGR5_CG9_MASK (0xC0000U) +#define CCM_CCGR5_CG9_SHIFT (18U) +#define CCM_CCGR5_CG9(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG9_SHIFT)) & CCM_CCGR5_CG9_MASK) +#define CCM_CCGR5_CG10_MASK (0x300000U) +#define CCM_CCGR5_CG10_SHIFT (20U) +#define CCM_CCGR5_CG10(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG10_SHIFT)) & CCM_CCGR5_CG10_MASK) +#define CCM_CCGR5_CG11_MASK (0xC00000U) +#define CCM_CCGR5_CG11_SHIFT (22U) +#define CCM_CCGR5_CG11(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG11_SHIFT)) & CCM_CCGR5_CG11_MASK) +#define CCM_CCGR5_CG12_MASK (0x3000000U) +#define CCM_CCGR5_CG12_SHIFT (24U) +#define CCM_CCGR5_CG12(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG12_SHIFT)) & CCM_CCGR5_CG12_MASK) +#define CCM_CCGR5_CG13_MASK (0xC000000U) +#define CCM_CCGR5_CG13_SHIFT (26U) +#define CCM_CCGR5_CG13(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG13_SHIFT)) & CCM_CCGR5_CG13_MASK) +#define CCM_CCGR5_CG14_MASK (0x30000000U) +#define CCM_CCGR5_CG14_SHIFT (28U) +#define CCM_CCGR5_CG14(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG14_SHIFT)) & CCM_CCGR5_CG14_MASK) +#define CCM_CCGR5_CG15_MASK (0xC0000000U) +#define CCM_CCGR5_CG15_SHIFT (30U) +#define CCM_CCGR5_CG15(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG15_SHIFT)) & CCM_CCGR5_CG15_MASK) +/*! @} */ + +/*! @name CCGR6 - CCM Clock Gating Register 6 */ +/*! @{ */ +#define CCM_CCGR6_CG0_MASK (0x3U) +#define CCM_CCGR6_CG0_SHIFT (0U) +#define CCM_CCGR6_CG0(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG0_SHIFT)) & CCM_CCGR6_CG0_MASK) +#define CCM_CCGR6_CG1_MASK (0xCU) +#define CCM_CCGR6_CG1_SHIFT (2U) +#define CCM_CCGR6_CG1(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG1_SHIFT)) & CCM_CCGR6_CG1_MASK) +#define CCM_CCGR6_CG2_MASK (0x30U) +#define CCM_CCGR6_CG2_SHIFT (4U) +#define CCM_CCGR6_CG2(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG2_SHIFT)) & CCM_CCGR6_CG2_MASK) +#define CCM_CCGR6_CG3_MASK (0xC0U) +#define CCM_CCGR6_CG3_SHIFT (6U) +#define CCM_CCGR6_CG3(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG3_SHIFT)) & CCM_CCGR6_CG3_MASK) +#define CCM_CCGR6_CG4_MASK (0x300U) +#define CCM_CCGR6_CG4_SHIFT (8U) +#define CCM_CCGR6_CG4(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG4_SHIFT)) & CCM_CCGR6_CG4_MASK) +#define CCM_CCGR6_CG5_MASK (0xC00U) +#define CCM_CCGR6_CG5_SHIFT (10U) +#define CCM_CCGR6_CG5(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG5_SHIFT)) & CCM_CCGR6_CG5_MASK) +#define CCM_CCGR6_CG6_MASK (0x3000U) +#define CCM_CCGR6_CG6_SHIFT (12U) +#define CCM_CCGR6_CG6(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG6_SHIFT)) & CCM_CCGR6_CG6_MASK) +#define CCM_CCGR6_CG7_MASK (0xC000U) +#define CCM_CCGR6_CG7_SHIFT (14U) +#define CCM_CCGR6_CG7(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG7_SHIFT)) & CCM_CCGR6_CG7_MASK) +#define CCM_CCGR6_CG8_MASK (0x30000U) +#define CCM_CCGR6_CG8_SHIFT (16U) +#define CCM_CCGR6_CG8(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG8_SHIFT)) & CCM_CCGR6_CG8_MASK) +#define CCM_CCGR6_CG9_MASK (0xC0000U) +#define CCM_CCGR6_CG9_SHIFT (18U) +#define CCM_CCGR6_CG9(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG9_SHIFT)) & CCM_CCGR6_CG9_MASK) +#define CCM_CCGR6_CG10_MASK (0x300000U) +#define CCM_CCGR6_CG10_SHIFT (20U) +#define CCM_CCGR6_CG10(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG10_SHIFT)) & CCM_CCGR6_CG10_MASK) +#define CCM_CCGR6_CG11_MASK (0xC00000U) +#define CCM_CCGR6_CG11_SHIFT (22U) +#define CCM_CCGR6_CG11(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG11_SHIFT)) & CCM_CCGR6_CG11_MASK) +#define CCM_CCGR6_CG12_MASK (0x3000000U) +#define CCM_CCGR6_CG12_SHIFT (24U) +#define CCM_CCGR6_CG12(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG12_SHIFT)) & CCM_CCGR6_CG12_MASK) +#define CCM_CCGR6_CG13_MASK (0xC000000U) +#define CCM_CCGR6_CG13_SHIFT (26U) +#define CCM_CCGR6_CG13(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG13_SHIFT)) & CCM_CCGR6_CG13_MASK) +#define CCM_CCGR6_CG14_MASK (0x30000000U) +#define CCM_CCGR6_CG14_SHIFT (28U) +#define CCM_CCGR6_CG14(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG14_SHIFT)) & CCM_CCGR6_CG14_MASK) +#define CCM_CCGR6_CG15_MASK (0xC0000000U) +#define CCM_CCGR6_CG15_SHIFT (30U) +#define CCM_CCGR6_CG15(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG15_SHIFT)) & CCM_CCGR6_CG15_MASK) +/*! @} */ + +/*! @name CMEOR - CCM Module Enable Overide Register */ +/*! @{ */ +#define CCM_CMEOR_MOD_EN_OV_GPT_MASK (0x20U) +#define CCM_CMEOR_MOD_EN_OV_GPT_SHIFT (5U) +/*! MOD_EN_OV_GPT + * 0b0..don't override module enable signal + * 0b1..override module enable signal + */ +#define CCM_CMEOR_MOD_EN_OV_GPT(x) (((uint32_t)(((uint32_t)(x)) << CCM_CMEOR_MOD_EN_OV_GPT_SHIFT)) & CCM_CMEOR_MOD_EN_OV_GPT_MASK) +#define CCM_CMEOR_MOD_EN_OV_PIT_MASK (0x40U) +#define CCM_CMEOR_MOD_EN_OV_PIT_SHIFT (6U) +/*! MOD_EN_OV_PIT + * 0b0..don't override module enable signal + * 0b1..override module enable signal + */ +#define CCM_CMEOR_MOD_EN_OV_PIT(x) (((uint32_t)(((uint32_t)(x)) << CCM_CMEOR_MOD_EN_OV_PIT_SHIFT)) & CCM_CMEOR_MOD_EN_OV_PIT_MASK) +#define CCM_CMEOR_MOD_EN_USDHC_MASK (0x80U) +#define CCM_CMEOR_MOD_EN_USDHC_SHIFT (7U) +/*! MOD_EN_USDHC + * 0b0..don't override module enable signal + * 0b1..override module enable signal + */ +#define CCM_CMEOR_MOD_EN_USDHC(x) (((uint32_t)(((uint32_t)(x)) << CCM_CMEOR_MOD_EN_USDHC_SHIFT)) & CCM_CMEOR_MOD_EN_USDHC_MASK) +#define CCM_CMEOR_MOD_EN_OV_TRNG_MASK (0x200U) +#define CCM_CMEOR_MOD_EN_OV_TRNG_SHIFT (9U) +/*! MOD_EN_OV_TRNG + * 0b0..don't override module enable signal + * 0b1..override module enable signal + */ +#define CCM_CMEOR_MOD_EN_OV_TRNG(x) (((uint32_t)(((uint32_t)(x)) << CCM_CMEOR_MOD_EN_OV_TRNG_SHIFT)) & CCM_CMEOR_MOD_EN_OV_TRNG_MASK) +#define CCM_CMEOR_MOD_EN_OV_CAN2_CPI_MASK (0x10000000U) +#define CCM_CMEOR_MOD_EN_OV_CAN2_CPI_SHIFT (28U) +/*! MOD_EN_OV_CAN2_CPI + * 0b0..don't override module enable signal + * 0b1..override module enable signal + */ +#define CCM_CMEOR_MOD_EN_OV_CAN2_CPI(x) (((uint32_t)(((uint32_t)(x)) << CCM_CMEOR_MOD_EN_OV_CAN2_CPI_SHIFT)) & CCM_CMEOR_MOD_EN_OV_CAN2_CPI_MASK) +#define CCM_CMEOR_MOD_EN_OV_CAN1_CPI_MASK (0x40000000U) +#define CCM_CMEOR_MOD_EN_OV_CAN1_CPI_SHIFT (30U) +/*! MOD_EN_OV_CAN1_CPI + * 0b0..don't overide module enable signal + * 0b1..overide module enable signal + */ +#define CCM_CMEOR_MOD_EN_OV_CAN1_CPI(x) (((uint32_t)(((uint32_t)(x)) << CCM_CMEOR_MOD_EN_OV_CAN1_CPI_SHIFT)) & CCM_CMEOR_MOD_EN_OV_CAN1_CPI_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group CCM_Register_Masks */ + + +/* CCM - Peripheral instance base addresses */ +/** Peripheral CCM base address */ +#define CCM_BASE (0x400FC000u) +/** Peripheral CCM base pointer */ +#define CCM ((CCM_Type *)CCM_BASE) +/** Array initializer of CCM peripheral base addresses */ +#define CCM_BASE_ADDRS { CCM_BASE } +/** Array initializer of CCM peripheral base pointers */ +#define CCM_BASE_PTRS { CCM } +/** Interrupt vectors for the CCM peripheral type */ +#define CCM_IRQS { CCM_1_IRQn, CCM_2_IRQn } + +/*! + * @} + */ /* end of group CCM_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- CCM_ANALOG Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup CCM_ANALOG_Peripheral_Access_Layer CCM_ANALOG Peripheral Access Layer + * @{ + */ + +/** CCM_ANALOG - Register Layout Typedef */ +typedef struct { + __IO uint32_t PLL_ARM; /**< Analog ARM PLL control Register, offset: 0x0 */ + __IO uint32_t PLL_ARM_SET; /**< Analog ARM PLL control Register, offset: 0x4 */ + __IO uint32_t PLL_ARM_CLR; /**< Analog ARM PLL control Register, offset: 0x8 */ + __IO uint32_t PLL_ARM_TOG; /**< Analog ARM PLL control Register, offset: 0xC */ + __IO uint32_t PLL_USB1; /**< Analog USB1 480MHz PLL Control Register, offset: 0x10 */ + __IO uint32_t PLL_USB1_SET; /**< Analog USB1 480MHz PLL Control Register, offset: 0x14 */ + __IO uint32_t PLL_USB1_CLR; /**< Analog USB1 480MHz PLL Control Register, offset: 0x18 */ + __IO uint32_t PLL_USB1_TOG; /**< Analog USB1 480MHz PLL Control Register, offset: 0x1C */ + __IO uint32_t PLL_USB2; /**< Analog USB2 480MHz PLL Control Register, offset: 0x20 */ + __IO uint32_t PLL_USB2_SET; /**< Analog USB2 480MHz PLL Control Register, offset: 0x24 */ + __IO uint32_t PLL_USB2_CLR; /**< Analog USB2 480MHz PLL Control Register, offset: 0x28 */ + __IO uint32_t PLL_USB2_TOG; /**< Analog USB2 480MHz PLL Control Register, offset: 0x2C */ + __IO uint32_t PLL_SYS; /**< Analog System PLL Control Register, offset: 0x30 */ + __IO uint32_t PLL_SYS_SET; /**< Analog System PLL Control Register, offset: 0x34 */ + __IO uint32_t PLL_SYS_CLR; /**< Analog System PLL Control Register, offset: 0x38 */ + __IO uint32_t PLL_SYS_TOG; /**< Analog System PLL Control Register, offset: 0x3C */ + __IO uint32_t PLL_SYS_SS; /**< 528MHz System PLL Spread Spectrum Register, offset: 0x40 */ + uint8_t RESERVED_0[12]; + __IO uint32_t PLL_SYS_NUM; /**< Numerator of 528MHz System PLL Fractional Loop Divider Register, offset: 0x50 */ + uint8_t RESERVED_1[12]; + __IO uint32_t PLL_SYS_DENOM; /**< Denominator of 528MHz System PLL Fractional Loop Divider Register, offset: 0x60 */ + uint8_t RESERVED_2[12]; + __IO uint32_t PLL_AUDIO; /**< Analog Audio PLL control Register, offset: 0x70 */ + __IO uint32_t PLL_AUDIO_SET; /**< Analog Audio PLL control Register, offset: 0x74 */ + __IO uint32_t PLL_AUDIO_CLR; /**< Analog Audio PLL control Register, offset: 0x78 */ + __IO uint32_t PLL_AUDIO_TOG; /**< Analog Audio PLL control Register, offset: 0x7C */ + __IO uint32_t PLL_AUDIO_NUM; /**< Numerator of Audio PLL Fractional Loop Divider Register, offset: 0x80 */ + uint8_t RESERVED_3[12]; + __IO uint32_t PLL_AUDIO_DENOM; /**< Denominator of Audio PLL Fractional Loop Divider Register, offset: 0x90 */ + uint8_t RESERVED_4[12]; + __IO uint32_t PLL_VIDEO; /**< Analog Video PLL control Register, offset: 0xA0 */ + __IO uint32_t PLL_VIDEO_SET; /**< Analog Video PLL control Register, offset: 0xA4 */ + __IO uint32_t PLL_VIDEO_CLR; /**< Analog Video PLL control Register, offset: 0xA8 */ + __IO uint32_t PLL_VIDEO_TOG; /**< Analog Video PLL control Register, offset: 0xAC */ + __IO uint32_t PLL_VIDEO_NUM; /**< Numerator of Video PLL Fractional Loop Divider Register, offset: 0xB0 */ + uint8_t RESERVED_5[12]; + __IO uint32_t PLL_VIDEO_DENOM; /**< Denominator of Video PLL Fractional Loop Divider Register, offset: 0xC0 */ + uint8_t RESERVED_6[28]; + __IO uint32_t PLL_ENET; /**< Analog ENET PLL Control Register, offset: 0xE0 */ + __IO uint32_t PLL_ENET_SET; /**< Analog ENET PLL Control Register, offset: 0xE4 */ + __IO uint32_t PLL_ENET_CLR; /**< Analog ENET PLL Control Register, offset: 0xE8 */ + __IO uint32_t PLL_ENET_TOG; /**< Analog ENET PLL Control Register, offset: 0xEC */ + __IO uint32_t PFD_480; /**< 480MHz Clock (PLL3) Phase Fractional Divider Control Register, offset: 0xF0 */ + __IO uint32_t PFD_480_SET; /**< 480MHz Clock (PLL3) Phase Fractional Divider Control Register, offset: 0xF4 */ + __IO uint32_t PFD_480_CLR; /**< 480MHz Clock (PLL3) Phase Fractional Divider Control Register, offset: 0xF8 */ + __IO uint32_t PFD_480_TOG; /**< 480MHz Clock (PLL3) Phase Fractional Divider Control Register, offset: 0xFC */ + __IO uint32_t PFD_528; /**< 528MHz Clock (PLL2) Phase Fractional Divider Control Register, offset: 0x100 */ + __IO uint32_t PFD_528_SET; /**< 528MHz Clock (PLL2) Phase Fractional Divider Control Register, offset: 0x104 */ + __IO uint32_t PFD_528_CLR; /**< 528MHz Clock (PLL2) Phase Fractional Divider Control Register, offset: 0x108 */ + __IO uint32_t PFD_528_TOG; /**< 528MHz Clock (PLL2) Phase Fractional Divider Control Register, offset: 0x10C */ + uint8_t RESERVED_7[64]; + __IO uint32_t MISC0; /**< Miscellaneous Register 0, offset: 0x150 */ + __IO uint32_t MISC0_SET; /**< Miscellaneous Register 0, offset: 0x154 */ + __IO uint32_t MISC0_CLR; /**< Miscellaneous Register 0, offset: 0x158 */ + __IO uint32_t MISC0_TOG; /**< Miscellaneous Register 0, offset: 0x15C */ + __IO uint32_t MISC1; /**< Miscellaneous Register 1, offset: 0x160 */ + __IO uint32_t MISC1_SET; /**< Miscellaneous Register 1, offset: 0x164 */ + __IO uint32_t MISC1_CLR; /**< Miscellaneous Register 1, offset: 0x168 */ + __IO uint32_t MISC1_TOG; /**< Miscellaneous Register 1, offset: 0x16C */ + __IO uint32_t MISC2; /**< Miscellaneous Register 2, offset: 0x170 */ + __IO uint32_t MISC2_SET; /**< Miscellaneous Register 2, offset: 0x174 */ + __IO uint32_t MISC2_CLR; /**< Miscellaneous Register 2, offset: 0x178 */ + __IO uint32_t MISC2_TOG; /**< Miscellaneous Register 2, offset: 0x17C */ +} CCM_ANALOG_Type; + +/* ---------------------------------------------------------------------------- + -- CCM_ANALOG Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup CCM_ANALOG_Register_Masks CCM_ANALOG Register Masks + * @{ + */ + +/*! @name PLL_ARM - Analog ARM PLL control Register */ +/*! @{ */ +#define CCM_ANALOG_PLL_ARM_DIV_SELECT_MASK (0x7FU) +#define CCM_ANALOG_PLL_ARM_DIV_SELECT_SHIFT (0U) +#define CCM_ANALOG_PLL_ARM_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_ARM_DIV_SELECT_MASK) +#define CCM_ANALOG_PLL_ARM_POWERDOWN_MASK (0x1000U) +#define CCM_ANALOG_PLL_ARM_POWERDOWN_SHIFT (12U) +#define CCM_ANALOG_PLL_ARM_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_ARM_POWERDOWN_MASK) +#define CCM_ANALOG_PLL_ARM_ENABLE_MASK (0x2000U) +#define CCM_ANALOG_PLL_ARM_ENABLE_SHIFT (13U) +#define CCM_ANALOG_PLL_ARM_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_ENABLE_SHIFT)) & CCM_ANALOG_PLL_ARM_ENABLE_MASK) +#define CCM_ANALOG_PLL_ARM_BYPASS_CLK_SRC_MASK (0xC000U) +#define CCM_ANALOG_PLL_ARM_BYPASS_CLK_SRC_SHIFT (14U) +/*! BYPASS_CLK_SRC + * 0b00..Select the 24MHz oscillator as source. + * 0b01..Select the CLK1_N / CLK1_P as source. + * 0b10..Reserved1 + * 0b11..Reserved2 + */ +#define CCM_ANALOG_PLL_ARM_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_ARM_BYPASS_CLK_SRC_MASK) +#define CCM_ANALOG_PLL_ARM_BYPASS_MASK (0x10000U) +#define CCM_ANALOG_PLL_ARM_BYPASS_SHIFT (16U) +#define CCM_ANALOG_PLL_ARM_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_BYPASS_SHIFT)) & CCM_ANALOG_PLL_ARM_BYPASS_MASK) +#define CCM_ANALOG_PLL_ARM_PLL_SEL_MASK (0x80000U) +#define CCM_ANALOG_PLL_ARM_PLL_SEL_SHIFT (19U) +#define CCM_ANALOG_PLL_ARM_PLL_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_PLL_SEL_SHIFT)) & CCM_ANALOG_PLL_ARM_PLL_SEL_MASK) +#define CCM_ANALOG_PLL_ARM_LOCK_MASK (0x80000000U) +#define CCM_ANALOG_PLL_ARM_LOCK_SHIFT (31U) +#define CCM_ANALOG_PLL_ARM_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_LOCK_SHIFT)) & CCM_ANALOG_PLL_ARM_LOCK_MASK) +/*! @} */ + +/*! @name PLL_ARM_SET - Analog ARM PLL control Register */ +/*! @{ */ +#define CCM_ANALOG_PLL_ARM_SET_DIV_SELECT_MASK (0x7FU) +#define CCM_ANALOG_PLL_ARM_SET_DIV_SELECT_SHIFT (0U) +#define CCM_ANALOG_PLL_ARM_SET_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_SET_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_ARM_SET_DIV_SELECT_MASK) +#define CCM_ANALOG_PLL_ARM_SET_POWERDOWN_MASK (0x1000U) +#define CCM_ANALOG_PLL_ARM_SET_POWERDOWN_SHIFT (12U) +#define CCM_ANALOG_PLL_ARM_SET_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_SET_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_ARM_SET_POWERDOWN_MASK) +#define CCM_ANALOG_PLL_ARM_SET_ENABLE_MASK (0x2000U) +#define CCM_ANALOG_PLL_ARM_SET_ENABLE_SHIFT (13U) +#define CCM_ANALOG_PLL_ARM_SET_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_SET_ENABLE_SHIFT)) & CCM_ANALOG_PLL_ARM_SET_ENABLE_MASK) +#define CCM_ANALOG_PLL_ARM_SET_BYPASS_CLK_SRC_MASK (0xC000U) +#define CCM_ANALOG_PLL_ARM_SET_BYPASS_CLK_SRC_SHIFT (14U) +/*! BYPASS_CLK_SRC + * 0b00..Select the 24MHz oscillator as source. + * 0b01..Select the CLK1_N / CLK1_P as source. + * 0b10..Reserved1 + * 0b11..Reserved2 + */ +#define CCM_ANALOG_PLL_ARM_SET_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_SET_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_ARM_SET_BYPASS_CLK_SRC_MASK) +#define CCM_ANALOG_PLL_ARM_SET_BYPASS_MASK (0x10000U) +#define CCM_ANALOG_PLL_ARM_SET_BYPASS_SHIFT (16U) +#define CCM_ANALOG_PLL_ARM_SET_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_SET_BYPASS_SHIFT)) & CCM_ANALOG_PLL_ARM_SET_BYPASS_MASK) +#define CCM_ANALOG_PLL_ARM_SET_PLL_SEL_MASK (0x80000U) +#define CCM_ANALOG_PLL_ARM_SET_PLL_SEL_SHIFT (19U) +#define CCM_ANALOG_PLL_ARM_SET_PLL_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_SET_PLL_SEL_SHIFT)) & CCM_ANALOG_PLL_ARM_SET_PLL_SEL_MASK) +#define CCM_ANALOG_PLL_ARM_SET_LOCK_MASK (0x80000000U) +#define CCM_ANALOG_PLL_ARM_SET_LOCK_SHIFT (31U) +#define CCM_ANALOG_PLL_ARM_SET_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_SET_LOCK_SHIFT)) & CCM_ANALOG_PLL_ARM_SET_LOCK_MASK) +/*! @} */ + +/*! @name PLL_ARM_CLR - Analog ARM PLL control Register */ +/*! @{ */ +#define CCM_ANALOG_PLL_ARM_CLR_DIV_SELECT_MASK (0x7FU) +#define CCM_ANALOG_PLL_ARM_CLR_DIV_SELECT_SHIFT (0U) +#define CCM_ANALOG_PLL_ARM_CLR_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_CLR_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_ARM_CLR_DIV_SELECT_MASK) +#define CCM_ANALOG_PLL_ARM_CLR_POWERDOWN_MASK (0x1000U) +#define CCM_ANALOG_PLL_ARM_CLR_POWERDOWN_SHIFT (12U) +#define CCM_ANALOG_PLL_ARM_CLR_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_CLR_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_ARM_CLR_POWERDOWN_MASK) +#define CCM_ANALOG_PLL_ARM_CLR_ENABLE_MASK (0x2000U) +#define CCM_ANALOG_PLL_ARM_CLR_ENABLE_SHIFT (13U) +#define CCM_ANALOG_PLL_ARM_CLR_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_CLR_ENABLE_SHIFT)) & CCM_ANALOG_PLL_ARM_CLR_ENABLE_MASK) +#define CCM_ANALOG_PLL_ARM_CLR_BYPASS_CLK_SRC_MASK (0xC000U) +#define CCM_ANALOG_PLL_ARM_CLR_BYPASS_CLK_SRC_SHIFT (14U) +/*! BYPASS_CLK_SRC + * 0b00..Select the 24MHz oscillator as source. + * 0b01..Select the CLK1_N / CLK1_P as source. + * 0b10..Reserved1 + * 0b11..Reserved2 + */ +#define CCM_ANALOG_PLL_ARM_CLR_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_CLR_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_ARM_CLR_BYPASS_CLK_SRC_MASK) +#define CCM_ANALOG_PLL_ARM_CLR_BYPASS_MASK (0x10000U) +#define CCM_ANALOG_PLL_ARM_CLR_BYPASS_SHIFT (16U) +#define CCM_ANALOG_PLL_ARM_CLR_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_CLR_BYPASS_SHIFT)) & CCM_ANALOG_PLL_ARM_CLR_BYPASS_MASK) +#define CCM_ANALOG_PLL_ARM_CLR_PLL_SEL_MASK (0x80000U) +#define CCM_ANALOG_PLL_ARM_CLR_PLL_SEL_SHIFT (19U) +#define CCM_ANALOG_PLL_ARM_CLR_PLL_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_CLR_PLL_SEL_SHIFT)) & CCM_ANALOG_PLL_ARM_CLR_PLL_SEL_MASK) +#define CCM_ANALOG_PLL_ARM_CLR_LOCK_MASK (0x80000000U) +#define CCM_ANALOG_PLL_ARM_CLR_LOCK_SHIFT (31U) +#define CCM_ANALOG_PLL_ARM_CLR_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_CLR_LOCK_SHIFT)) & CCM_ANALOG_PLL_ARM_CLR_LOCK_MASK) +/*! @} */ + +/*! @name PLL_ARM_TOG - Analog ARM PLL control Register */ +/*! @{ */ +#define CCM_ANALOG_PLL_ARM_TOG_DIV_SELECT_MASK (0x7FU) +#define CCM_ANALOG_PLL_ARM_TOG_DIV_SELECT_SHIFT (0U) +#define CCM_ANALOG_PLL_ARM_TOG_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_TOG_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_ARM_TOG_DIV_SELECT_MASK) +#define CCM_ANALOG_PLL_ARM_TOG_POWERDOWN_MASK (0x1000U) +#define CCM_ANALOG_PLL_ARM_TOG_POWERDOWN_SHIFT (12U) +#define CCM_ANALOG_PLL_ARM_TOG_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_TOG_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_ARM_TOG_POWERDOWN_MASK) +#define CCM_ANALOG_PLL_ARM_TOG_ENABLE_MASK (0x2000U) +#define CCM_ANALOG_PLL_ARM_TOG_ENABLE_SHIFT (13U) +#define CCM_ANALOG_PLL_ARM_TOG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_TOG_ENABLE_SHIFT)) & CCM_ANALOG_PLL_ARM_TOG_ENABLE_MASK) +#define CCM_ANALOG_PLL_ARM_TOG_BYPASS_CLK_SRC_MASK (0xC000U) +#define CCM_ANALOG_PLL_ARM_TOG_BYPASS_CLK_SRC_SHIFT (14U) +/*! BYPASS_CLK_SRC + * 0b00..Select the 24MHz oscillator as source. + * 0b01..Select the CLK1_N / CLK1_P as source. + * 0b10..Reserved1 + * 0b11..Reserved2 + */ +#define CCM_ANALOG_PLL_ARM_TOG_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_TOG_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_ARM_TOG_BYPASS_CLK_SRC_MASK) +#define CCM_ANALOG_PLL_ARM_TOG_BYPASS_MASK (0x10000U) +#define CCM_ANALOG_PLL_ARM_TOG_BYPASS_SHIFT (16U) +#define CCM_ANALOG_PLL_ARM_TOG_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_TOG_BYPASS_SHIFT)) & CCM_ANALOG_PLL_ARM_TOG_BYPASS_MASK) +#define CCM_ANALOG_PLL_ARM_TOG_PLL_SEL_MASK (0x80000U) +#define CCM_ANALOG_PLL_ARM_TOG_PLL_SEL_SHIFT (19U) +#define CCM_ANALOG_PLL_ARM_TOG_PLL_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_TOG_PLL_SEL_SHIFT)) & CCM_ANALOG_PLL_ARM_TOG_PLL_SEL_MASK) +#define CCM_ANALOG_PLL_ARM_TOG_LOCK_MASK (0x80000000U) +#define CCM_ANALOG_PLL_ARM_TOG_LOCK_SHIFT (31U) +#define CCM_ANALOG_PLL_ARM_TOG_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_TOG_LOCK_SHIFT)) & CCM_ANALOG_PLL_ARM_TOG_LOCK_MASK) +/*! @} */ + +/*! @name PLL_USB1 - Analog USB1 480MHz PLL Control Register */ +/*! @{ */ +#define CCM_ANALOG_PLL_USB1_DIV_SELECT_MASK (0x2U) +#define CCM_ANALOG_PLL_USB1_DIV_SELECT_SHIFT (1U) +#define CCM_ANALOG_PLL_USB1_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_USB1_DIV_SELECT_MASK) +#define CCM_ANALOG_PLL_USB1_EN_USB_CLKS_MASK (0x40U) +#define CCM_ANALOG_PLL_USB1_EN_USB_CLKS_SHIFT (6U) +/*! EN_USB_CLKS + * 0b0..PLL outputs for USBPHYn off. + * 0b1..PLL outputs for USBPHYn on. + */ +#define CCM_ANALOG_PLL_USB1_EN_USB_CLKS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_EN_USB_CLKS_SHIFT)) & CCM_ANALOG_PLL_USB1_EN_USB_CLKS_MASK) +#define CCM_ANALOG_PLL_USB1_POWER_MASK (0x1000U) +#define CCM_ANALOG_PLL_USB1_POWER_SHIFT (12U) +#define CCM_ANALOG_PLL_USB1_POWER(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_POWER_SHIFT)) & CCM_ANALOG_PLL_USB1_POWER_MASK) +#define CCM_ANALOG_PLL_USB1_ENABLE_MASK (0x2000U) +#define CCM_ANALOG_PLL_USB1_ENABLE_SHIFT (13U) +#define CCM_ANALOG_PLL_USB1_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_ENABLE_SHIFT)) & CCM_ANALOG_PLL_USB1_ENABLE_MASK) +#define CCM_ANALOG_PLL_USB1_BYPASS_CLK_SRC_MASK (0xC000U) +#define CCM_ANALOG_PLL_USB1_BYPASS_CLK_SRC_SHIFT (14U) +/*! BYPASS_CLK_SRC + * 0b00..Select the 24MHz oscillator as source. + * 0b01..Select the CLK1_N / CLK1_P as source. + */ +#define CCM_ANALOG_PLL_USB1_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_USB1_BYPASS_CLK_SRC_MASK) +#define CCM_ANALOG_PLL_USB1_BYPASS_MASK (0x10000U) +#define CCM_ANALOG_PLL_USB1_BYPASS_SHIFT (16U) +#define CCM_ANALOG_PLL_USB1_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_BYPASS_SHIFT)) & CCM_ANALOG_PLL_USB1_BYPASS_MASK) +#define CCM_ANALOG_PLL_USB1_LOCK_MASK (0x80000000U) +#define CCM_ANALOG_PLL_USB1_LOCK_SHIFT (31U) +#define CCM_ANALOG_PLL_USB1_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_LOCK_SHIFT)) & CCM_ANALOG_PLL_USB1_LOCK_MASK) +/*! @} */ + +/*! @name PLL_USB1_SET - Analog USB1 480MHz PLL Control Register */ +/*! @{ */ +#define CCM_ANALOG_PLL_USB1_SET_DIV_SELECT_MASK (0x2U) +#define CCM_ANALOG_PLL_USB1_SET_DIV_SELECT_SHIFT (1U) +#define CCM_ANALOG_PLL_USB1_SET_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_SET_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_USB1_SET_DIV_SELECT_MASK) +#define CCM_ANALOG_PLL_USB1_SET_EN_USB_CLKS_MASK (0x40U) +#define CCM_ANALOG_PLL_USB1_SET_EN_USB_CLKS_SHIFT (6U) +/*! EN_USB_CLKS + * 0b0..PLL outputs for USBPHYn off. + * 0b1..PLL outputs for USBPHYn on. + */ +#define CCM_ANALOG_PLL_USB1_SET_EN_USB_CLKS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_SET_EN_USB_CLKS_SHIFT)) & CCM_ANALOG_PLL_USB1_SET_EN_USB_CLKS_MASK) +#define CCM_ANALOG_PLL_USB1_SET_POWER_MASK (0x1000U) +#define CCM_ANALOG_PLL_USB1_SET_POWER_SHIFT (12U) +#define CCM_ANALOG_PLL_USB1_SET_POWER(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_SET_POWER_SHIFT)) & CCM_ANALOG_PLL_USB1_SET_POWER_MASK) +#define CCM_ANALOG_PLL_USB1_SET_ENABLE_MASK (0x2000U) +#define CCM_ANALOG_PLL_USB1_SET_ENABLE_SHIFT (13U) +#define CCM_ANALOG_PLL_USB1_SET_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_SET_ENABLE_SHIFT)) & CCM_ANALOG_PLL_USB1_SET_ENABLE_MASK) +#define CCM_ANALOG_PLL_USB1_SET_BYPASS_CLK_SRC_MASK (0xC000U) +#define CCM_ANALOG_PLL_USB1_SET_BYPASS_CLK_SRC_SHIFT (14U) +/*! BYPASS_CLK_SRC + * 0b00..Select the 24MHz oscillator as source. + * 0b01..Select the CLK1_N / CLK1_P as source. + */ +#define CCM_ANALOG_PLL_USB1_SET_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_SET_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_USB1_SET_BYPASS_CLK_SRC_MASK) +#define CCM_ANALOG_PLL_USB1_SET_BYPASS_MASK (0x10000U) +#define CCM_ANALOG_PLL_USB1_SET_BYPASS_SHIFT (16U) +#define CCM_ANALOG_PLL_USB1_SET_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_SET_BYPASS_SHIFT)) & CCM_ANALOG_PLL_USB1_SET_BYPASS_MASK) +#define CCM_ANALOG_PLL_USB1_SET_LOCK_MASK (0x80000000U) +#define CCM_ANALOG_PLL_USB1_SET_LOCK_SHIFT (31U) +#define CCM_ANALOG_PLL_USB1_SET_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_SET_LOCK_SHIFT)) & CCM_ANALOG_PLL_USB1_SET_LOCK_MASK) +/*! @} */ + +/*! @name PLL_USB1_CLR - Analog USB1 480MHz PLL Control Register */ +/*! @{ */ +#define CCM_ANALOG_PLL_USB1_CLR_DIV_SELECT_MASK (0x2U) +#define CCM_ANALOG_PLL_USB1_CLR_DIV_SELECT_SHIFT (1U) +#define CCM_ANALOG_PLL_USB1_CLR_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_CLR_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_USB1_CLR_DIV_SELECT_MASK) +#define CCM_ANALOG_PLL_USB1_CLR_EN_USB_CLKS_MASK (0x40U) +#define CCM_ANALOG_PLL_USB1_CLR_EN_USB_CLKS_SHIFT (6U) +/*! EN_USB_CLKS + * 0b0..PLL outputs for USBPHYn off. + * 0b1..PLL outputs for USBPHYn on. + */ +#define CCM_ANALOG_PLL_USB1_CLR_EN_USB_CLKS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_CLR_EN_USB_CLKS_SHIFT)) & CCM_ANALOG_PLL_USB1_CLR_EN_USB_CLKS_MASK) +#define CCM_ANALOG_PLL_USB1_CLR_POWER_MASK (0x1000U) +#define CCM_ANALOG_PLL_USB1_CLR_POWER_SHIFT (12U) +#define CCM_ANALOG_PLL_USB1_CLR_POWER(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_CLR_POWER_SHIFT)) & CCM_ANALOG_PLL_USB1_CLR_POWER_MASK) +#define CCM_ANALOG_PLL_USB1_CLR_ENABLE_MASK (0x2000U) +#define CCM_ANALOG_PLL_USB1_CLR_ENABLE_SHIFT (13U) +#define CCM_ANALOG_PLL_USB1_CLR_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_CLR_ENABLE_SHIFT)) & CCM_ANALOG_PLL_USB1_CLR_ENABLE_MASK) +#define CCM_ANALOG_PLL_USB1_CLR_BYPASS_CLK_SRC_MASK (0xC000U) +#define CCM_ANALOG_PLL_USB1_CLR_BYPASS_CLK_SRC_SHIFT (14U) +/*! BYPASS_CLK_SRC + * 0b00..Select the 24MHz oscillator as source. + * 0b01..Select the CLK1_N / CLK1_P as source. + */ +#define CCM_ANALOG_PLL_USB1_CLR_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_CLR_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_USB1_CLR_BYPASS_CLK_SRC_MASK) +#define CCM_ANALOG_PLL_USB1_CLR_BYPASS_MASK (0x10000U) +#define CCM_ANALOG_PLL_USB1_CLR_BYPASS_SHIFT (16U) +#define CCM_ANALOG_PLL_USB1_CLR_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_CLR_BYPASS_SHIFT)) & CCM_ANALOG_PLL_USB1_CLR_BYPASS_MASK) +#define CCM_ANALOG_PLL_USB1_CLR_LOCK_MASK (0x80000000U) +#define CCM_ANALOG_PLL_USB1_CLR_LOCK_SHIFT (31U) +#define CCM_ANALOG_PLL_USB1_CLR_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_CLR_LOCK_SHIFT)) & CCM_ANALOG_PLL_USB1_CLR_LOCK_MASK) +/*! @} */ + +/*! @name PLL_USB1_TOG - Analog USB1 480MHz PLL Control Register */ +/*! @{ */ +#define CCM_ANALOG_PLL_USB1_TOG_DIV_SELECT_MASK (0x2U) +#define CCM_ANALOG_PLL_USB1_TOG_DIV_SELECT_SHIFT (1U) +#define CCM_ANALOG_PLL_USB1_TOG_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_TOG_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_USB1_TOG_DIV_SELECT_MASK) +#define CCM_ANALOG_PLL_USB1_TOG_EN_USB_CLKS_MASK (0x40U) +#define CCM_ANALOG_PLL_USB1_TOG_EN_USB_CLKS_SHIFT (6U) +/*! EN_USB_CLKS + * 0b0..PLL outputs for USBPHYn off. + * 0b1..PLL outputs for USBPHYn on. + */ +#define CCM_ANALOG_PLL_USB1_TOG_EN_USB_CLKS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_TOG_EN_USB_CLKS_SHIFT)) & CCM_ANALOG_PLL_USB1_TOG_EN_USB_CLKS_MASK) +#define CCM_ANALOG_PLL_USB1_TOG_POWER_MASK (0x1000U) +#define CCM_ANALOG_PLL_USB1_TOG_POWER_SHIFT (12U) +#define CCM_ANALOG_PLL_USB1_TOG_POWER(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_TOG_POWER_SHIFT)) & CCM_ANALOG_PLL_USB1_TOG_POWER_MASK) +#define CCM_ANALOG_PLL_USB1_TOG_ENABLE_MASK (0x2000U) +#define CCM_ANALOG_PLL_USB1_TOG_ENABLE_SHIFT (13U) +#define CCM_ANALOG_PLL_USB1_TOG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_TOG_ENABLE_SHIFT)) & CCM_ANALOG_PLL_USB1_TOG_ENABLE_MASK) +#define CCM_ANALOG_PLL_USB1_TOG_BYPASS_CLK_SRC_MASK (0xC000U) +#define CCM_ANALOG_PLL_USB1_TOG_BYPASS_CLK_SRC_SHIFT (14U) +/*! BYPASS_CLK_SRC + * 0b00..Select the 24MHz oscillator as source. + * 0b01..Select the CLK1_N / CLK1_P as source. + */ +#define CCM_ANALOG_PLL_USB1_TOG_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_TOG_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_USB1_TOG_BYPASS_CLK_SRC_MASK) +#define CCM_ANALOG_PLL_USB1_TOG_BYPASS_MASK (0x10000U) +#define CCM_ANALOG_PLL_USB1_TOG_BYPASS_SHIFT (16U) +#define CCM_ANALOG_PLL_USB1_TOG_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_TOG_BYPASS_SHIFT)) & CCM_ANALOG_PLL_USB1_TOG_BYPASS_MASK) +#define CCM_ANALOG_PLL_USB1_TOG_LOCK_MASK (0x80000000U) +#define CCM_ANALOG_PLL_USB1_TOG_LOCK_SHIFT (31U) +#define CCM_ANALOG_PLL_USB1_TOG_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_TOG_LOCK_SHIFT)) & CCM_ANALOG_PLL_USB1_TOG_LOCK_MASK) +/*! @} */ + +/*! @name PLL_USB2 - Analog USB2 480MHz PLL Control Register */ +/*! @{ */ +#define CCM_ANALOG_PLL_USB2_DIV_SELECT_MASK (0x2U) +#define CCM_ANALOG_PLL_USB2_DIV_SELECT_SHIFT (1U) +#define CCM_ANALOG_PLL_USB2_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_USB2_DIV_SELECT_MASK) +#define CCM_ANALOG_PLL_USB2_EN_USB_CLKS_MASK (0x40U) +#define CCM_ANALOG_PLL_USB2_EN_USB_CLKS_SHIFT (6U) +#define CCM_ANALOG_PLL_USB2_EN_USB_CLKS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_EN_USB_CLKS_SHIFT)) & CCM_ANALOG_PLL_USB2_EN_USB_CLKS_MASK) +#define CCM_ANALOG_PLL_USB2_POWER_MASK (0x1000U) +#define CCM_ANALOG_PLL_USB2_POWER_SHIFT (12U) +#define CCM_ANALOG_PLL_USB2_POWER(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_POWER_SHIFT)) & CCM_ANALOG_PLL_USB2_POWER_MASK) +#define CCM_ANALOG_PLL_USB2_ENABLE_MASK (0x2000U) +#define CCM_ANALOG_PLL_USB2_ENABLE_SHIFT (13U) +#define CCM_ANALOG_PLL_USB2_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_ENABLE_SHIFT)) & CCM_ANALOG_PLL_USB2_ENABLE_MASK) +#define CCM_ANALOG_PLL_USB2_BYPASS_CLK_SRC_MASK (0xC000U) +#define CCM_ANALOG_PLL_USB2_BYPASS_CLK_SRC_SHIFT (14U) +/*! BYPASS_CLK_SRC + * 0b00..Select the 24MHz oscillator as source. + * 0b01..Select the CLK1_N / CLK1_P as source. + * 0b10..Reserved1 + * 0b11..Reserved2 + */ +#define CCM_ANALOG_PLL_USB2_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_USB2_BYPASS_CLK_SRC_MASK) +#define CCM_ANALOG_PLL_USB2_BYPASS_MASK (0x10000U) +#define CCM_ANALOG_PLL_USB2_BYPASS_SHIFT (16U) +#define CCM_ANALOG_PLL_USB2_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_BYPASS_SHIFT)) & CCM_ANALOG_PLL_USB2_BYPASS_MASK) +#define CCM_ANALOG_PLL_USB2_LOCK_MASK (0x80000000U) +#define CCM_ANALOG_PLL_USB2_LOCK_SHIFT (31U) +#define CCM_ANALOG_PLL_USB2_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_LOCK_SHIFT)) & CCM_ANALOG_PLL_USB2_LOCK_MASK) +/*! @} */ + +/*! @name PLL_USB2_SET - Analog USB2 480MHz PLL Control Register */ +/*! @{ */ +#define CCM_ANALOG_PLL_USB2_SET_DIV_SELECT_MASK (0x2U) +#define CCM_ANALOG_PLL_USB2_SET_DIV_SELECT_SHIFT (1U) +#define CCM_ANALOG_PLL_USB2_SET_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_SET_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_USB2_SET_DIV_SELECT_MASK) +#define CCM_ANALOG_PLL_USB2_SET_EN_USB_CLKS_MASK (0x40U) +#define CCM_ANALOG_PLL_USB2_SET_EN_USB_CLKS_SHIFT (6U) +#define CCM_ANALOG_PLL_USB2_SET_EN_USB_CLKS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_SET_EN_USB_CLKS_SHIFT)) & CCM_ANALOG_PLL_USB2_SET_EN_USB_CLKS_MASK) +#define CCM_ANALOG_PLL_USB2_SET_POWER_MASK (0x1000U) +#define CCM_ANALOG_PLL_USB2_SET_POWER_SHIFT (12U) +#define CCM_ANALOG_PLL_USB2_SET_POWER(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_SET_POWER_SHIFT)) & CCM_ANALOG_PLL_USB2_SET_POWER_MASK) +#define CCM_ANALOG_PLL_USB2_SET_ENABLE_MASK (0x2000U) +#define CCM_ANALOG_PLL_USB2_SET_ENABLE_SHIFT (13U) +#define CCM_ANALOG_PLL_USB2_SET_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_SET_ENABLE_SHIFT)) & CCM_ANALOG_PLL_USB2_SET_ENABLE_MASK) +#define CCM_ANALOG_PLL_USB2_SET_BYPASS_CLK_SRC_MASK (0xC000U) +#define CCM_ANALOG_PLL_USB2_SET_BYPASS_CLK_SRC_SHIFT (14U) +/*! BYPASS_CLK_SRC + * 0b00..Select the 24MHz oscillator as source. + * 0b01..Select the CLK1_N / CLK1_P as source. + * 0b10..Reserved1 + * 0b11..Reserved2 + */ +#define CCM_ANALOG_PLL_USB2_SET_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_SET_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_USB2_SET_BYPASS_CLK_SRC_MASK) +#define CCM_ANALOG_PLL_USB2_SET_BYPASS_MASK (0x10000U) +#define CCM_ANALOG_PLL_USB2_SET_BYPASS_SHIFT (16U) +#define CCM_ANALOG_PLL_USB2_SET_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_SET_BYPASS_SHIFT)) & CCM_ANALOG_PLL_USB2_SET_BYPASS_MASK) +#define CCM_ANALOG_PLL_USB2_SET_LOCK_MASK (0x80000000U) +#define CCM_ANALOG_PLL_USB2_SET_LOCK_SHIFT (31U) +#define CCM_ANALOG_PLL_USB2_SET_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_SET_LOCK_SHIFT)) & CCM_ANALOG_PLL_USB2_SET_LOCK_MASK) +/*! @} */ + +/*! @name PLL_USB2_CLR - Analog USB2 480MHz PLL Control Register */ +/*! @{ */ +#define CCM_ANALOG_PLL_USB2_CLR_DIV_SELECT_MASK (0x2U) +#define CCM_ANALOG_PLL_USB2_CLR_DIV_SELECT_SHIFT (1U) +#define CCM_ANALOG_PLL_USB2_CLR_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_CLR_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_USB2_CLR_DIV_SELECT_MASK) +#define CCM_ANALOG_PLL_USB2_CLR_EN_USB_CLKS_MASK (0x40U) +#define CCM_ANALOG_PLL_USB2_CLR_EN_USB_CLKS_SHIFT (6U) +#define CCM_ANALOG_PLL_USB2_CLR_EN_USB_CLKS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_CLR_EN_USB_CLKS_SHIFT)) & CCM_ANALOG_PLL_USB2_CLR_EN_USB_CLKS_MASK) +#define CCM_ANALOG_PLL_USB2_CLR_POWER_MASK (0x1000U) +#define CCM_ANALOG_PLL_USB2_CLR_POWER_SHIFT (12U) +#define CCM_ANALOG_PLL_USB2_CLR_POWER(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_CLR_POWER_SHIFT)) & CCM_ANALOG_PLL_USB2_CLR_POWER_MASK) +#define CCM_ANALOG_PLL_USB2_CLR_ENABLE_MASK (0x2000U) +#define CCM_ANALOG_PLL_USB2_CLR_ENABLE_SHIFT (13U) +#define CCM_ANALOG_PLL_USB2_CLR_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_CLR_ENABLE_SHIFT)) & CCM_ANALOG_PLL_USB2_CLR_ENABLE_MASK) +#define CCM_ANALOG_PLL_USB2_CLR_BYPASS_CLK_SRC_MASK (0xC000U) +#define CCM_ANALOG_PLL_USB2_CLR_BYPASS_CLK_SRC_SHIFT (14U) +/*! BYPASS_CLK_SRC + * 0b00..Select the 24MHz oscillator as source. + * 0b01..Select the CLK1_N / CLK1_P as source. + * 0b10..Reserved1 + * 0b11..Reserved2 + */ +#define CCM_ANALOG_PLL_USB2_CLR_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_CLR_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_USB2_CLR_BYPASS_CLK_SRC_MASK) +#define CCM_ANALOG_PLL_USB2_CLR_BYPASS_MASK (0x10000U) +#define CCM_ANALOG_PLL_USB2_CLR_BYPASS_SHIFT (16U) +#define CCM_ANALOG_PLL_USB2_CLR_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_CLR_BYPASS_SHIFT)) & CCM_ANALOG_PLL_USB2_CLR_BYPASS_MASK) +#define CCM_ANALOG_PLL_USB2_CLR_LOCK_MASK (0x80000000U) +#define CCM_ANALOG_PLL_USB2_CLR_LOCK_SHIFT (31U) +#define CCM_ANALOG_PLL_USB2_CLR_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_CLR_LOCK_SHIFT)) & CCM_ANALOG_PLL_USB2_CLR_LOCK_MASK) +/*! @} */ + +/*! @name PLL_USB2_TOG - Analog USB2 480MHz PLL Control Register */ +/*! @{ */ +#define CCM_ANALOG_PLL_USB2_TOG_DIV_SELECT_MASK (0x2U) +#define CCM_ANALOG_PLL_USB2_TOG_DIV_SELECT_SHIFT (1U) +#define CCM_ANALOG_PLL_USB2_TOG_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_TOG_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_USB2_TOG_DIV_SELECT_MASK) +#define CCM_ANALOG_PLL_USB2_TOG_EN_USB_CLKS_MASK (0x40U) +#define CCM_ANALOG_PLL_USB2_TOG_EN_USB_CLKS_SHIFT (6U) +#define CCM_ANALOG_PLL_USB2_TOG_EN_USB_CLKS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_TOG_EN_USB_CLKS_SHIFT)) & CCM_ANALOG_PLL_USB2_TOG_EN_USB_CLKS_MASK) +#define CCM_ANALOG_PLL_USB2_TOG_POWER_MASK (0x1000U) +#define CCM_ANALOG_PLL_USB2_TOG_POWER_SHIFT (12U) +#define CCM_ANALOG_PLL_USB2_TOG_POWER(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_TOG_POWER_SHIFT)) & CCM_ANALOG_PLL_USB2_TOG_POWER_MASK) +#define CCM_ANALOG_PLL_USB2_TOG_ENABLE_MASK (0x2000U) +#define CCM_ANALOG_PLL_USB2_TOG_ENABLE_SHIFT (13U) +#define CCM_ANALOG_PLL_USB2_TOG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_TOG_ENABLE_SHIFT)) & CCM_ANALOG_PLL_USB2_TOG_ENABLE_MASK) +#define CCM_ANALOG_PLL_USB2_TOG_BYPASS_CLK_SRC_MASK (0xC000U) +#define CCM_ANALOG_PLL_USB2_TOG_BYPASS_CLK_SRC_SHIFT (14U) +/*! BYPASS_CLK_SRC + * 0b00..Select the 24MHz oscillator as source. + * 0b01..Select the CLK1_N / CLK1_P as source. + * 0b10..Reserved1 + * 0b11..Reserved2 + */ +#define CCM_ANALOG_PLL_USB2_TOG_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_TOG_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_USB2_TOG_BYPASS_CLK_SRC_MASK) +#define CCM_ANALOG_PLL_USB2_TOG_BYPASS_MASK (0x10000U) +#define CCM_ANALOG_PLL_USB2_TOG_BYPASS_SHIFT (16U) +#define CCM_ANALOG_PLL_USB2_TOG_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_TOG_BYPASS_SHIFT)) & CCM_ANALOG_PLL_USB2_TOG_BYPASS_MASK) +#define CCM_ANALOG_PLL_USB2_TOG_LOCK_MASK (0x80000000U) +#define CCM_ANALOG_PLL_USB2_TOG_LOCK_SHIFT (31U) +#define CCM_ANALOG_PLL_USB2_TOG_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_TOG_LOCK_SHIFT)) & CCM_ANALOG_PLL_USB2_TOG_LOCK_MASK) +/*! @} */ + +/*! @name PLL_SYS - Analog System PLL Control Register */ +/*! @{ */ +#define CCM_ANALOG_PLL_SYS_DIV_SELECT_MASK (0x1U) +#define CCM_ANALOG_PLL_SYS_DIV_SELECT_SHIFT (0U) +#define CCM_ANALOG_PLL_SYS_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_SYS_DIV_SELECT_MASK) +#define CCM_ANALOG_PLL_SYS_POWERDOWN_MASK (0x1000U) +#define CCM_ANALOG_PLL_SYS_POWERDOWN_SHIFT (12U) +#define CCM_ANALOG_PLL_SYS_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_SYS_POWERDOWN_MASK) +#define CCM_ANALOG_PLL_SYS_ENABLE_MASK (0x2000U) +#define CCM_ANALOG_PLL_SYS_ENABLE_SHIFT (13U) +#define CCM_ANALOG_PLL_SYS_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_ENABLE_SHIFT)) & CCM_ANALOG_PLL_SYS_ENABLE_MASK) +#define CCM_ANALOG_PLL_SYS_BYPASS_CLK_SRC_MASK (0xC000U) +#define CCM_ANALOG_PLL_SYS_BYPASS_CLK_SRC_SHIFT (14U) +/*! BYPASS_CLK_SRC + * 0b00..Select the 24MHz oscillator as source. + * 0b01..Select the CLK1_N / CLK1_P as source. + */ +#define CCM_ANALOG_PLL_SYS_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_SYS_BYPASS_CLK_SRC_MASK) +#define CCM_ANALOG_PLL_SYS_BYPASS_MASK (0x10000U) +#define CCM_ANALOG_PLL_SYS_BYPASS_SHIFT (16U) +#define CCM_ANALOG_PLL_SYS_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_BYPASS_SHIFT)) & CCM_ANALOG_PLL_SYS_BYPASS_MASK) +#define CCM_ANALOG_PLL_SYS_PFD_OFFSET_EN_MASK (0x40000U) +#define CCM_ANALOG_PLL_SYS_PFD_OFFSET_EN_SHIFT (18U) +#define CCM_ANALOG_PLL_SYS_PFD_OFFSET_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_PFD_OFFSET_EN_SHIFT)) & CCM_ANALOG_PLL_SYS_PFD_OFFSET_EN_MASK) +#define CCM_ANALOG_PLL_SYS_LOCK_MASK (0x80000000U) +#define CCM_ANALOG_PLL_SYS_LOCK_SHIFT (31U) +#define CCM_ANALOG_PLL_SYS_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_LOCK_SHIFT)) & CCM_ANALOG_PLL_SYS_LOCK_MASK) +/*! @} */ + +/*! @name PLL_SYS_SET - Analog System PLL Control Register */ +/*! @{ */ +#define CCM_ANALOG_PLL_SYS_SET_DIV_SELECT_MASK (0x1U) +#define CCM_ANALOG_PLL_SYS_SET_DIV_SELECT_SHIFT (0U) +#define CCM_ANALOG_PLL_SYS_SET_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_SET_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_SYS_SET_DIV_SELECT_MASK) +#define CCM_ANALOG_PLL_SYS_SET_POWERDOWN_MASK (0x1000U) +#define CCM_ANALOG_PLL_SYS_SET_POWERDOWN_SHIFT (12U) +#define CCM_ANALOG_PLL_SYS_SET_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_SET_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_SYS_SET_POWERDOWN_MASK) +#define CCM_ANALOG_PLL_SYS_SET_ENABLE_MASK (0x2000U) +#define CCM_ANALOG_PLL_SYS_SET_ENABLE_SHIFT (13U) +#define CCM_ANALOG_PLL_SYS_SET_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_SET_ENABLE_SHIFT)) & CCM_ANALOG_PLL_SYS_SET_ENABLE_MASK) +#define CCM_ANALOG_PLL_SYS_SET_BYPASS_CLK_SRC_MASK (0xC000U) +#define CCM_ANALOG_PLL_SYS_SET_BYPASS_CLK_SRC_SHIFT (14U) +/*! BYPASS_CLK_SRC + * 0b00..Select the 24MHz oscillator as source. + * 0b01..Select the CLK1_N / CLK1_P as source. + */ +#define CCM_ANALOG_PLL_SYS_SET_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_SET_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_SYS_SET_BYPASS_CLK_SRC_MASK) +#define CCM_ANALOG_PLL_SYS_SET_BYPASS_MASK (0x10000U) +#define CCM_ANALOG_PLL_SYS_SET_BYPASS_SHIFT (16U) +#define CCM_ANALOG_PLL_SYS_SET_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_SET_BYPASS_SHIFT)) & CCM_ANALOG_PLL_SYS_SET_BYPASS_MASK) +#define CCM_ANALOG_PLL_SYS_SET_PFD_OFFSET_EN_MASK (0x40000U) +#define CCM_ANALOG_PLL_SYS_SET_PFD_OFFSET_EN_SHIFT (18U) +#define CCM_ANALOG_PLL_SYS_SET_PFD_OFFSET_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_SET_PFD_OFFSET_EN_SHIFT)) & CCM_ANALOG_PLL_SYS_SET_PFD_OFFSET_EN_MASK) +#define CCM_ANALOG_PLL_SYS_SET_LOCK_MASK (0x80000000U) +#define CCM_ANALOG_PLL_SYS_SET_LOCK_SHIFT (31U) +#define CCM_ANALOG_PLL_SYS_SET_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_SET_LOCK_SHIFT)) & CCM_ANALOG_PLL_SYS_SET_LOCK_MASK) +/*! @} */ + +/*! @name PLL_SYS_CLR - Analog System PLL Control Register */ +/*! @{ */ +#define CCM_ANALOG_PLL_SYS_CLR_DIV_SELECT_MASK (0x1U) +#define CCM_ANALOG_PLL_SYS_CLR_DIV_SELECT_SHIFT (0U) +#define CCM_ANALOG_PLL_SYS_CLR_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_CLR_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_SYS_CLR_DIV_SELECT_MASK) +#define CCM_ANALOG_PLL_SYS_CLR_POWERDOWN_MASK (0x1000U) +#define CCM_ANALOG_PLL_SYS_CLR_POWERDOWN_SHIFT (12U) +#define CCM_ANALOG_PLL_SYS_CLR_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_CLR_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_SYS_CLR_POWERDOWN_MASK) +#define CCM_ANALOG_PLL_SYS_CLR_ENABLE_MASK (0x2000U) +#define CCM_ANALOG_PLL_SYS_CLR_ENABLE_SHIFT (13U) +#define CCM_ANALOG_PLL_SYS_CLR_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_CLR_ENABLE_SHIFT)) & CCM_ANALOG_PLL_SYS_CLR_ENABLE_MASK) +#define CCM_ANALOG_PLL_SYS_CLR_BYPASS_CLK_SRC_MASK (0xC000U) +#define CCM_ANALOG_PLL_SYS_CLR_BYPASS_CLK_SRC_SHIFT (14U) +/*! BYPASS_CLK_SRC + * 0b00..Select the 24MHz oscillator as source. + * 0b01..Select the CLK1_N / CLK1_P as source. + */ +#define CCM_ANALOG_PLL_SYS_CLR_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_CLR_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_SYS_CLR_BYPASS_CLK_SRC_MASK) +#define CCM_ANALOG_PLL_SYS_CLR_BYPASS_MASK (0x10000U) +#define CCM_ANALOG_PLL_SYS_CLR_BYPASS_SHIFT (16U) +#define CCM_ANALOG_PLL_SYS_CLR_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_CLR_BYPASS_SHIFT)) & CCM_ANALOG_PLL_SYS_CLR_BYPASS_MASK) +#define CCM_ANALOG_PLL_SYS_CLR_PFD_OFFSET_EN_MASK (0x40000U) +#define CCM_ANALOG_PLL_SYS_CLR_PFD_OFFSET_EN_SHIFT (18U) +#define CCM_ANALOG_PLL_SYS_CLR_PFD_OFFSET_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_CLR_PFD_OFFSET_EN_SHIFT)) & CCM_ANALOG_PLL_SYS_CLR_PFD_OFFSET_EN_MASK) +#define CCM_ANALOG_PLL_SYS_CLR_LOCK_MASK (0x80000000U) +#define CCM_ANALOG_PLL_SYS_CLR_LOCK_SHIFT (31U) +#define CCM_ANALOG_PLL_SYS_CLR_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_CLR_LOCK_SHIFT)) & CCM_ANALOG_PLL_SYS_CLR_LOCK_MASK) +/*! @} */ + +/*! @name PLL_SYS_TOG - Analog System PLL Control Register */ +/*! @{ */ +#define CCM_ANALOG_PLL_SYS_TOG_DIV_SELECT_MASK (0x1U) +#define CCM_ANALOG_PLL_SYS_TOG_DIV_SELECT_SHIFT (0U) +#define CCM_ANALOG_PLL_SYS_TOG_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_TOG_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_SYS_TOG_DIV_SELECT_MASK) +#define CCM_ANALOG_PLL_SYS_TOG_POWERDOWN_MASK (0x1000U) +#define CCM_ANALOG_PLL_SYS_TOG_POWERDOWN_SHIFT (12U) +#define CCM_ANALOG_PLL_SYS_TOG_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_TOG_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_SYS_TOG_POWERDOWN_MASK) +#define CCM_ANALOG_PLL_SYS_TOG_ENABLE_MASK (0x2000U) +#define CCM_ANALOG_PLL_SYS_TOG_ENABLE_SHIFT (13U) +#define CCM_ANALOG_PLL_SYS_TOG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_TOG_ENABLE_SHIFT)) & CCM_ANALOG_PLL_SYS_TOG_ENABLE_MASK) +#define CCM_ANALOG_PLL_SYS_TOG_BYPASS_CLK_SRC_MASK (0xC000U) +#define CCM_ANALOG_PLL_SYS_TOG_BYPASS_CLK_SRC_SHIFT (14U) +/*! BYPASS_CLK_SRC + * 0b00..Select the 24MHz oscillator as source. + * 0b01..Select the CLK1_N / CLK1_P as source. + */ +#define CCM_ANALOG_PLL_SYS_TOG_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_TOG_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_SYS_TOG_BYPASS_CLK_SRC_MASK) +#define CCM_ANALOG_PLL_SYS_TOG_BYPASS_MASK (0x10000U) +#define CCM_ANALOG_PLL_SYS_TOG_BYPASS_SHIFT (16U) +#define CCM_ANALOG_PLL_SYS_TOG_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_TOG_BYPASS_SHIFT)) & CCM_ANALOG_PLL_SYS_TOG_BYPASS_MASK) +#define CCM_ANALOG_PLL_SYS_TOG_PFD_OFFSET_EN_MASK (0x40000U) +#define CCM_ANALOG_PLL_SYS_TOG_PFD_OFFSET_EN_SHIFT (18U) +#define CCM_ANALOG_PLL_SYS_TOG_PFD_OFFSET_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_TOG_PFD_OFFSET_EN_SHIFT)) & CCM_ANALOG_PLL_SYS_TOG_PFD_OFFSET_EN_MASK) +#define CCM_ANALOG_PLL_SYS_TOG_LOCK_MASK (0x80000000U) +#define CCM_ANALOG_PLL_SYS_TOG_LOCK_SHIFT (31U) +#define CCM_ANALOG_PLL_SYS_TOG_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_TOG_LOCK_SHIFT)) & CCM_ANALOG_PLL_SYS_TOG_LOCK_MASK) +/*! @} */ + +/*! @name PLL_SYS_SS - 528MHz System PLL Spread Spectrum Register */ +/*! @{ */ +#define CCM_ANALOG_PLL_SYS_SS_STEP_MASK (0x7FFFU) +#define CCM_ANALOG_PLL_SYS_SS_STEP_SHIFT (0U) +#define CCM_ANALOG_PLL_SYS_SS_STEP(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_SS_STEP_SHIFT)) & CCM_ANALOG_PLL_SYS_SS_STEP_MASK) +#define CCM_ANALOG_PLL_SYS_SS_ENABLE_MASK (0x8000U) +#define CCM_ANALOG_PLL_SYS_SS_ENABLE_SHIFT (15U) +/*! ENABLE - Enable bit + * 0b0..Spread spectrum modulation disabled + * 0b1..Soread spectrum modulation enabled + */ +#define CCM_ANALOG_PLL_SYS_SS_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_SS_ENABLE_SHIFT)) & CCM_ANALOG_PLL_SYS_SS_ENABLE_MASK) +#define CCM_ANALOG_PLL_SYS_SS_STOP_MASK (0xFFFF0000U) +#define CCM_ANALOG_PLL_SYS_SS_STOP_SHIFT (16U) +#define CCM_ANALOG_PLL_SYS_SS_STOP(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_SS_STOP_SHIFT)) & CCM_ANALOG_PLL_SYS_SS_STOP_MASK) +/*! @} */ + +/*! @name PLL_SYS_NUM - Numerator of 528MHz System PLL Fractional Loop Divider Register */ +/*! @{ */ +#define CCM_ANALOG_PLL_SYS_NUM_A_MASK (0x3FFFFFFFU) +#define CCM_ANALOG_PLL_SYS_NUM_A_SHIFT (0U) +#define CCM_ANALOG_PLL_SYS_NUM_A(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_NUM_A_SHIFT)) & CCM_ANALOG_PLL_SYS_NUM_A_MASK) +/*! @} */ + +/*! @name PLL_SYS_DENOM - Denominator of 528MHz System PLL Fractional Loop Divider Register */ +/*! @{ */ +#define CCM_ANALOG_PLL_SYS_DENOM_B_MASK (0x3FFFFFFFU) +#define CCM_ANALOG_PLL_SYS_DENOM_B_SHIFT (0U) +#define CCM_ANALOG_PLL_SYS_DENOM_B(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_DENOM_B_SHIFT)) & CCM_ANALOG_PLL_SYS_DENOM_B_MASK) +/*! @} */ + +/*! @name PLL_AUDIO - Analog Audio PLL control Register */ +/*! @{ */ +#define CCM_ANALOG_PLL_AUDIO_DIV_SELECT_MASK (0x7FU) +#define CCM_ANALOG_PLL_AUDIO_DIV_SELECT_SHIFT (0U) +#define CCM_ANALOG_PLL_AUDIO_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_AUDIO_DIV_SELECT_MASK) +#define CCM_ANALOG_PLL_AUDIO_POWERDOWN_MASK (0x1000U) +#define CCM_ANALOG_PLL_AUDIO_POWERDOWN_SHIFT (12U) +#define CCM_ANALOG_PLL_AUDIO_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_AUDIO_POWERDOWN_MASK) +#define CCM_ANALOG_PLL_AUDIO_ENABLE_MASK (0x2000U) +#define CCM_ANALOG_PLL_AUDIO_ENABLE_SHIFT (13U) +#define CCM_ANALOG_PLL_AUDIO_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_ENABLE_SHIFT)) & CCM_ANALOG_PLL_AUDIO_ENABLE_MASK) +#define CCM_ANALOG_PLL_AUDIO_BYPASS_CLK_SRC_MASK (0xC000U) +#define CCM_ANALOG_PLL_AUDIO_BYPASS_CLK_SRC_SHIFT (14U) +/*! BYPASS_CLK_SRC + * 0b00..Select the 24MHz oscillator as source. + * 0b01..Select the CLK1_N / CLK1_P as source. + * 0b10..Reserved1 + * 0b11..Reserved2 + */ +#define CCM_ANALOG_PLL_AUDIO_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_AUDIO_BYPASS_CLK_SRC_MASK) +#define CCM_ANALOG_PLL_AUDIO_BYPASS_MASK (0x10000U) +#define CCM_ANALOG_PLL_AUDIO_BYPASS_SHIFT (16U) +#define CCM_ANALOG_PLL_AUDIO_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_BYPASS_SHIFT)) & CCM_ANALOG_PLL_AUDIO_BYPASS_MASK) +#define CCM_ANALOG_PLL_AUDIO_PFD_OFFSET_EN_MASK (0x40000U) +#define CCM_ANALOG_PLL_AUDIO_PFD_OFFSET_EN_SHIFT (18U) +#define CCM_ANALOG_PLL_AUDIO_PFD_OFFSET_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_PFD_OFFSET_EN_SHIFT)) & CCM_ANALOG_PLL_AUDIO_PFD_OFFSET_EN_MASK) +#define CCM_ANALOG_PLL_AUDIO_POST_DIV_SELECT_MASK (0x180000U) +#define CCM_ANALOG_PLL_AUDIO_POST_DIV_SELECT_SHIFT (19U) +/*! POST_DIV_SELECT + * 0b00..Divide by 4. + * 0b01..Divide by 2. + * 0b10..Divide by 1. + * 0b11..Reserved + */ +#define CCM_ANALOG_PLL_AUDIO_POST_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_POST_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_AUDIO_POST_DIV_SELECT_MASK) +#define CCM_ANALOG_PLL_AUDIO_LOCK_MASK (0x80000000U) +#define CCM_ANALOG_PLL_AUDIO_LOCK_SHIFT (31U) +#define CCM_ANALOG_PLL_AUDIO_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_LOCK_SHIFT)) & CCM_ANALOG_PLL_AUDIO_LOCK_MASK) +/*! @} */ + +/*! @name PLL_AUDIO_SET - Analog Audio PLL control Register */ +/*! @{ */ +#define CCM_ANALOG_PLL_AUDIO_SET_DIV_SELECT_MASK (0x7FU) +#define CCM_ANALOG_PLL_AUDIO_SET_DIV_SELECT_SHIFT (0U) +#define CCM_ANALOG_PLL_AUDIO_SET_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_SET_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_AUDIO_SET_DIV_SELECT_MASK) +#define CCM_ANALOG_PLL_AUDIO_SET_POWERDOWN_MASK (0x1000U) +#define CCM_ANALOG_PLL_AUDIO_SET_POWERDOWN_SHIFT (12U) +#define CCM_ANALOG_PLL_AUDIO_SET_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_SET_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_AUDIO_SET_POWERDOWN_MASK) +#define CCM_ANALOG_PLL_AUDIO_SET_ENABLE_MASK (0x2000U) +#define CCM_ANALOG_PLL_AUDIO_SET_ENABLE_SHIFT (13U) +#define CCM_ANALOG_PLL_AUDIO_SET_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_SET_ENABLE_SHIFT)) & CCM_ANALOG_PLL_AUDIO_SET_ENABLE_MASK) +#define CCM_ANALOG_PLL_AUDIO_SET_BYPASS_CLK_SRC_MASK (0xC000U) +#define CCM_ANALOG_PLL_AUDIO_SET_BYPASS_CLK_SRC_SHIFT (14U) +/*! BYPASS_CLK_SRC + * 0b00..Select the 24MHz oscillator as source. + * 0b01..Select the CLK1_N / CLK1_P as source. + * 0b10..Reserved1 + * 0b11..Reserved2 + */ +#define CCM_ANALOG_PLL_AUDIO_SET_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_SET_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_AUDIO_SET_BYPASS_CLK_SRC_MASK) +#define CCM_ANALOG_PLL_AUDIO_SET_BYPASS_MASK (0x10000U) +#define CCM_ANALOG_PLL_AUDIO_SET_BYPASS_SHIFT (16U) +#define CCM_ANALOG_PLL_AUDIO_SET_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_SET_BYPASS_SHIFT)) & CCM_ANALOG_PLL_AUDIO_SET_BYPASS_MASK) +#define CCM_ANALOG_PLL_AUDIO_SET_PFD_OFFSET_EN_MASK (0x40000U) +#define CCM_ANALOG_PLL_AUDIO_SET_PFD_OFFSET_EN_SHIFT (18U) +#define CCM_ANALOG_PLL_AUDIO_SET_PFD_OFFSET_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_SET_PFD_OFFSET_EN_SHIFT)) & CCM_ANALOG_PLL_AUDIO_SET_PFD_OFFSET_EN_MASK) +#define CCM_ANALOG_PLL_AUDIO_SET_POST_DIV_SELECT_MASK (0x180000U) +#define CCM_ANALOG_PLL_AUDIO_SET_POST_DIV_SELECT_SHIFT (19U) +/*! POST_DIV_SELECT + * 0b00..Divide by 4. + * 0b01..Divide by 2. + * 0b10..Divide by 1. + * 0b11..Reserved + */ +#define CCM_ANALOG_PLL_AUDIO_SET_POST_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_SET_POST_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_AUDIO_SET_POST_DIV_SELECT_MASK) +#define CCM_ANALOG_PLL_AUDIO_SET_LOCK_MASK (0x80000000U) +#define CCM_ANALOG_PLL_AUDIO_SET_LOCK_SHIFT (31U) +#define CCM_ANALOG_PLL_AUDIO_SET_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_SET_LOCK_SHIFT)) & CCM_ANALOG_PLL_AUDIO_SET_LOCK_MASK) +/*! @} */ + +/*! @name PLL_AUDIO_CLR - Analog Audio PLL control Register */ +/*! @{ */ +#define CCM_ANALOG_PLL_AUDIO_CLR_DIV_SELECT_MASK (0x7FU) +#define CCM_ANALOG_PLL_AUDIO_CLR_DIV_SELECT_SHIFT (0U) +#define CCM_ANALOG_PLL_AUDIO_CLR_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_CLR_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_AUDIO_CLR_DIV_SELECT_MASK) +#define CCM_ANALOG_PLL_AUDIO_CLR_POWERDOWN_MASK (0x1000U) +#define CCM_ANALOG_PLL_AUDIO_CLR_POWERDOWN_SHIFT (12U) +#define CCM_ANALOG_PLL_AUDIO_CLR_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_CLR_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_AUDIO_CLR_POWERDOWN_MASK) +#define CCM_ANALOG_PLL_AUDIO_CLR_ENABLE_MASK (0x2000U) +#define CCM_ANALOG_PLL_AUDIO_CLR_ENABLE_SHIFT (13U) +#define CCM_ANALOG_PLL_AUDIO_CLR_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_CLR_ENABLE_SHIFT)) & CCM_ANALOG_PLL_AUDIO_CLR_ENABLE_MASK) +#define CCM_ANALOG_PLL_AUDIO_CLR_BYPASS_CLK_SRC_MASK (0xC000U) +#define CCM_ANALOG_PLL_AUDIO_CLR_BYPASS_CLK_SRC_SHIFT (14U) +/*! BYPASS_CLK_SRC + * 0b00..Select the 24MHz oscillator as source. + * 0b01..Select the CLK1_N / CLK1_P as source. + * 0b10..Reserved1 + * 0b11..Reserved2 + */ +#define CCM_ANALOG_PLL_AUDIO_CLR_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_CLR_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_AUDIO_CLR_BYPASS_CLK_SRC_MASK) +#define CCM_ANALOG_PLL_AUDIO_CLR_BYPASS_MASK (0x10000U) +#define CCM_ANALOG_PLL_AUDIO_CLR_BYPASS_SHIFT (16U) +#define CCM_ANALOG_PLL_AUDIO_CLR_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_CLR_BYPASS_SHIFT)) & CCM_ANALOG_PLL_AUDIO_CLR_BYPASS_MASK) +#define CCM_ANALOG_PLL_AUDIO_CLR_PFD_OFFSET_EN_MASK (0x40000U) +#define CCM_ANALOG_PLL_AUDIO_CLR_PFD_OFFSET_EN_SHIFT (18U) +#define CCM_ANALOG_PLL_AUDIO_CLR_PFD_OFFSET_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_CLR_PFD_OFFSET_EN_SHIFT)) & CCM_ANALOG_PLL_AUDIO_CLR_PFD_OFFSET_EN_MASK) +#define CCM_ANALOG_PLL_AUDIO_CLR_POST_DIV_SELECT_MASK (0x180000U) +#define CCM_ANALOG_PLL_AUDIO_CLR_POST_DIV_SELECT_SHIFT (19U) +/*! POST_DIV_SELECT + * 0b00..Divide by 4. + * 0b01..Divide by 2. + * 0b10..Divide by 1. + * 0b11..Reserved + */ +#define CCM_ANALOG_PLL_AUDIO_CLR_POST_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_CLR_POST_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_AUDIO_CLR_POST_DIV_SELECT_MASK) +#define CCM_ANALOG_PLL_AUDIO_CLR_LOCK_MASK (0x80000000U) +#define CCM_ANALOG_PLL_AUDIO_CLR_LOCK_SHIFT (31U) +#define CCM_ANALOG_PLL_AUDIO_CLR_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_CLR_LOCK_SHIFT)) & CCM_ANALOG_PLL_AUDIO_CLR_LOCK_MASK) +/*! @} */ + +/*! @name PLL_AUDIO_TOG - Analog Audio PLL control Register */ +/*! @{ */ +#define CCM_ANALOG_PLL_AUDIO_TOG_DIV_SELECT_MASK (0x7FU) +#define CCM_ANALOG_PLL_AUDIO_TOG_DIV_SELECT_SHIFT (0U) +#define CCM_ANALOG_PLL_AUDIO_TOG_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_TOG_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_AUDIO_TOG_DIV_SELECT_MASK) +#define CCM_ANALOG_PLL_AUDIO_TOG_POWERDOWN_MASK (0x1000U) +#define CCM_ANALOG_PLL_AUDIO_TOG_POWERDOWN_SHIFT (12U) +#define CCM_ANALOG_PLL_AUDIO_TOG_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_TOG_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_AUDIO_TOG_POWERDOWN_MASK) +#define CCM_ANALOG_PLL_AUDIO_TOG_ENABLE_MASK (0x2000U) +#define CCM_ANALOG_PLL_AUDIO_TOG_ENABLE_SHIFT (13U) +#define CCM_ANALOG_PLL_AUDIO_TOG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_TOG_ENABLE_SHIFT)) & CCM_ANALOG_PLL_AUDIO_TOG_ENABLE_MASK) +#define CCM_ANALOG_PLL_AUDIO_TOG_BYPASS_CLK_SRC_MASK (0xC000U) +#define CCM_ANALOG_PLL_AUDIO_TOG_BYPASS_CLK_SRC_SHIFT (14U) +/*! BYPASS_CLK_SRC + * 0b00..Select the 24MHz oscillator as source. + * 0b01..Select the CLK1_N / CLK1_P as source. + * 0b10..Reserved1 + * 0b11..Reserved2 + */ +#define CCM_ANALOG_PLL_AUDIO_TOG_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_TOG_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_AUDIO_TOG_BYPASS_CLK_SRC_MASK) +#define CCM_ANALOG_PLL_AUDIO_TOG_BYPASS_MASK (0x10000U) +#define CCM_ANALOG_PLL_AUDIO_TOG_BYPASS_SHIFT (16U) +#define CCM_ANALOG_PLL_AUDIO_TOG_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_TOG_BYPASS_SHIFT)) & CCM_ANALOG_PLL_AUDIO_TOG_BYPASS_MASK) +#define CCM_ANALOG_PLL_AUDIO_TOG_PFD_OFFSET_EN_MASK (0x40000U) +#define CCM_ANALOG_PLL_AUDIO_TOG_PFD_OFFSET_EN_SHIFT (18U) +#define CCM_ANALOG_PLL_AUDIO_TOG_PFD_OFFSET_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_TOG_PFD_OFFSET_EN_SHIFT)) & CCM_ANALOG_PLL_AUDIO_TOG_PFD_OFFSET_EN_MASK) +#define CCM_ANALOG_PLL_AUDIO_TOG_POST_DIV_SELECT_MASK (0x180000U) +#define CCM_ANALOG_PLL_AUDIO_TOG_POST_DIV_SELECT_SHIFT (19U) +/*! POST_DIV_SELECT + * 0b00..Divide by 4. + * 0b01..Divide by 2. + * 0b10..Divide by 1. + * 0b11..Reserved + */ +#define CCM_ANALOG_PLL_AUDIO_TOG_POST_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_TOG_POST_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_AUDIO_TOG_POST_DIV_SELECT_MASK) +#define CCM_ANALOG_PLL_AUDIO_TOG_LOCK_MASK (0x80000000U) +#define CCM_ANALOG_PLL_AUDIO_TOG_LOCK_SHIFT (31U) +#define CCM_ANALOG_PLL_AUDIO_TOG_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_TOG_LOCK_SHIFT)) & CCM_ANALOG_PLL_AUDIO_TOG_LOCK_MASK) +/*! @} */ + +/*! @name PLL_AUDIO_NUM - Numerator of Audio PLL Fractional Loop Divider Register */ +/*! @{ */ +#define CCM_ANALOG_PLL_AUDIO_NUM_A_MASK (0x3FFFFFFFU) +#define CCM_ANALOG_PLL_AUDIO_NUM_A_SHIFT (0U) +#define CCM_ANALOG_PLL_AUDIO_NUM_A(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_NUM_A_SHIFT)) & CCM_ANALOG_PLL_AUDIO_NUM_A_MASK) +/*! @} */ + +/*! @name PLL_AUDIO_DENOM - Denominator of Audio PLL Fractional Loop Divider Register */ +/*! @{ */ +#define CCM_ANALOG_PLL_AUDIO_DENOM_B_MASK (0x3FFFFFFFU) +#define CCM_ANALOG_PLL_AUDIO_DENOM_B_SHIFT (0U) +#define CCM_ANALOG_PLL_AUDIO_DENOM_B(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_DENOM_B_SHIFT)) & CCM_ANALOG_PLL_AUDIO_DENOM_B_MASK) +/*! @} */ + +/*! @name PLL_VIDEO - Analog Video PLL control Register */ +/*! @{ */ +#define CCM_ANALOG_PLL_VIDEO_DIV_SELECT_MASK (0x7FU) +#define CCM_ANALOG_PLL_VIDEO_DIV_SELECT_SHIFT (0U) +#define CCM_ANALOG_PLL_VIDEO_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_VIDEO_DIV_SELECT_MASK) +#define CCM_ANALOG_PLL_VIDEO_POWERDOWN_MASK (0x1000U) +#define CCM_ANALOG_PLL_VIDEO_POWERDOWN_SHIFT (12U) +#define CCM_ANALOG_PLL_VIDEO_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_VIDEO_POWERDOWN_MASK) +#define CCM_ANALOG_PLL_VIDEO_ENABLE_MASK (0x2000U) +#define CCM_ANALOG_PLL_VIDEO_ENABLE_SHIFT (13U) +#define CCM_ANALOG_PLL_VIDEO_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_ENABLE_SHIFT)) & CCM_ANALOG_PLL_VIDEO_ENABLE_MASK) +#define CCM_ANALOG_PLL_VIDEO_BYPASS_CLK_SRC_MASK (0xC000U) +#define CCM_ANALOG_PLL_VIDEO_BYPASS_CLK_SRC_SHIFT (14U) +/*! BYPASS_CLK_SRC + * 0b00..Select the 24MHz oscillator as source. + * 0b01..Select the CLK1_N / CLK1_P as source. + * 0b10..Reserved1 + * 0b11..Reserved2 + */ +#define CCM_ANALOG_PLL_VIDEO_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_VIDEO_BYPASS_CLK_SRC_MASK) +#define CCM_ANALOG_PLL_VIDEO_BYPASS_MASK (0x10000U) +#define CCM_ANALOG_PLL_VIDEO_BYPASS_SHIFT (16U) +#define CCM_ANALOG_PLL_VIDEO_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_BYPASS_SHIFT)) & CCM_ANALOG_PLL_VIDEO_BYPASS_MASK) +#define CCM_ANALOG_PLL_VIDEO_PFD_OFFSET_EN_MASK (0x40000U) +#define CCM_ANALOG_PLL_VIDEO_PFD_OFFSET_EN_SHIFT (18U) +#define CCM_ANALOG_PLL_VIDEO_PFD_OFFSET_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_PFD_OFFSET_EN_SHIFT)) & CCM_ANALOG_PLL_VIDEO_PFD_OFFSET_EN_MASK) +#define CCM_ANALOG_PLL_VIDEO_POST_DIV_SELECT_MASK (0x180000U) +#define CCM_ANALOG_PLL_VIDEO_POST_DIV_SELECT_SHIFT (19U) +/*! POST_DIV_SELECT + * 0b00..Divide by 4. + * 0b01..Divide by 2. + * 0b10..Divide by 1. + * 0b11..Reserved + */ +#define CCM_ANALOG_PLL_VIDEO_POST_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_POST_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_VIDEO_POST_DIV_SELECT_MASK) +#define CCM_ANALOG_PLL_VIDEO_LOCK_MASK (0x80000000U) +#define CCM_ANALOG_PLL_VIDEO_LOCK_SHIFT (31U) +#define CCM_ANALOG_PLL_VIDEO_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_LOCK_SHIFT)) & CCM_ANALOG_PLL_VIDEO_LOCK_MASK) +/*! @} */ + +/*! @name PLL_VIDEO_SET - Analog Video PLL control Register */ +/*! @{ */ +#define CCM_ANALOG_PLL_VIDEO_SET_DIV_SELECT_MASK (0x7FU) +#define CCM_ANALOG_PLL_VIDEO_SET_DIV_SELECT_SHIFT (0U) +#define CCM_ANALOG_PLL_VIDEO_SET_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_SET_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_VIDEO_SET_DIV_SELECT_MASK) +#define CCM_ANALOG_PLL_VIDEO_SET_POWERDOWN_MASK (0x1000U) +#define CCM_ANALOG_PLL_VIDEO_SET_POWERDOWN_SHIFT (12U) +#define CCM_ANALOG_PLL_VIDEO_SET_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_SET_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_VIDEO_SET_POWERDOWN_MASK) +#define CCM_ANALOG_PLL_VIDEO_SET_ENABLE_MASK (0x2000U) +#define CCM_ANALOG_PLL_VIDEO_SET_ENABLE_SHIFT (13U) +#define CCM_ANALOG_PLL_VIDEO_SET_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_SET_ENABLE_SHIFT)) & CCM_ANALOG_PLL_VIDEO_SET_ENABLE_MASK) +#define CCM_ANALOG_PLL_VIDEO_SET_BYPASS_CLK_SRC_MASK (0xC000U) +#define CCM_ANALOG_PLL_VIDEO_SET_BYPASS_CLK_SRC_SHIFT (14U) +/*! BYPASS_CLK_SRC + * 0b00..Select the 24MHz oscillator as source. + * 0b01..Select the CLK1_N / CLK1_P as source. + * 0b10..Reserved1 + * 0b11..Reserved2 + */ +#define CCM_ANALOG_PLL_VIDEO_SET_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_SET_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_VIDEO_SET_BYPASS_CLK_SRC_MASK) +#define CCM_ANALOG_PLL_VIDEO_SET_BYPASS_MASK (0x10000U) +#define CCM_ANALOG_PLL_VIDEO_SET_BYPASS_SHIFT (16U) +#define CCM_ANALOG_PLL_VIDEO_SET_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_SET_BYPASS_SHIFT)) & CCM_ANALOG_PLL_VIDEO_SET_BYPASS_MASK) +#define CCM_ANALOG_PLL_VIDEO_SET_PFD_OFFSET_EN_MASK (0x40000U) +#define CCM_ANALOG_PLL_VIDEO_SET_PFD_OFFSET_EN_SHIFT (18U) +#define CCM_ANALOG_PLL_VIDEO_SET_PFD_OFFSET_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_SET_PFD_OFFSET_EN_SHIFT)) & CCM_ANALOG_PLL_VIDEO_SET_PFD_OFFSET_EN_MASK) +#define CCM_ANALOG_PLL_VIDEO_SET_POST_DIV_SELECT_MASK (0x180000U) +#define CCM_ANALOG_PLL_VIDEO_SET_POST_DIV_SELECT_SHIFT (19U) +/*! POST_DIV_SELECT + * 0b00..Divide by 4. + * 0b01..Divide by 2. + * 0b10..Divide by 1. + * 0b11..Reserved + */ +#define CCM_ANALOG_PLL_VIDEO_SET_POST_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_SET_POST_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_VIDEO_SET_POST_DIV_SELECT_MASK) +#define CCM_ANALOG_PLL_VIDEO_SET_LOCK_MASK (0x80000000U) +#define CCM_ANALOG_PLL_VIDEO_SET_LOCK_SHIFT (31U) +#define CCM_ANALOG_PLL_VIDEO_SET_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_SET_LOCK_SHIFT)) & CCM_ANALOG_PLL_VIDEO_SET_LOCK_MASK) +/*! @} */ + +/*! @name PLL_VIDEO_CLR - Analog Video PLL control Register */ +/*! @{ */ +#define CCM_ANALOG_PLL_VIDEO_CLR_DIV_SELECT_MASK (0x7FU) +#define CCM_ANALOG_PLL_VIDEO_CLR_DIV_SELECT_SHIFT (0U) +#define CCM_ANALOG_PLL_VIDEO_CLR_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_CLR_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_VIDEO_CLR_DIV_SELECT_MASK) +#define CCM_ANALOG_PLL_VIDEO_CLR_POWERDOWN_MASK (0x1000U) +#define CCM_ANALOG_PLL_VIDEO_CLR_POWERDOWN_SHIFT (12U) +#define CCM_ANALOG_PLL_VIDEO_CLR_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_CLR_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_VIDEO_CLR_POWERDOWN_MASK) +#define CCM_ANALOG_PLL_VIDEO_CLR_ENABLE_MASK (0x2000U) +#define CCM_ANALOG_PLL_VIDEO_CLR_ENABLE_SHIFT (13U) +#define CCM_ANALOG_PLL_VIDEO_CLR_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_CLR_ENABLE_SHIFT)) & CCM_ANALOG_PLL_VIDEO_CLR_ENABLE_MASK) +#define CCM_ANALOG_PLL_VIDEO_CLR_BYPASS_CLK_SRC_MASK (0xC000U) +#define CCM_ANALOG_PLL_VIDEO_CLR_BYPASS_CLK_SRC_SHIFT (14U) +/*! BYPASS_CLK_SRC + * 0b00..Select the 24MHz oscillator as source. + * 0b01..Select the CLK1_N / CLK1_P as source. + * 0b10..Reserved1 + * 0b11..Reserved2 + */ +#define CCM_ANALOG_PLL_VIDEO_CLR_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_CLR_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_VIDEO_CLR_BYPASS_CLK_SRC_MASK) +#define CCM_ANALOG_PLL_VIDEO_CLR_BYPASS_MASK (0x10000U) +#define CCM_ANALOG_PLL_VIDEO_CLR_BYPASS_SHIFT (16U) +#define CCM_ANALOG_PLL_VIDEO_CLR_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_CLR_BYPASS_SHIFT)) & CCM_ANALOG_PLL_VIDEO_CLR_BYPASS_MASK) +#define CCM_ANALOG_PLL_VIDEO_CLR_PFD_OFFSET_EN_MASK (0x40000U) +#define CCM_ANALOG_PLL_VIDEO_CLR_PFD_OFFSET_EN_SHIFT (18U) +#define CCM_ANALOG_PLL_VIDEO_CLR_PFD_OFFSET_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_CLR_PFD_OFFSET_EN_SHIFT)) & CCM_ANALOG_PLL_VIDEO_CLR_PFD_OFFSET_EN_MASK) +#define CCM_ANALOG_PLL_VIDEO_CLR_POST_DIV_SELECT_MASK (0x180000U) +#define CCM_ANALOG_PLL_VIDEO_CLR_POST_DIV_SELECT_SHIFT (19U) +/*! POST_DIV_SELECT + * 0b00..Divide by 4. + * 0b01..Divide by 2. + * 0b10..Divide by 1. + * 0b11..Reserved + */ +#define CCM_ANALOG_PLL_VIDEO_CLR_POST_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_CLR_POST_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_VIDEO_CLR_POST_DIV_SELECT_MASK) +#define CCM_ANALOG_PLL_VIDEO_CLR_LOCK_MASK (0x80000000U) +#define CCM_ANALOG_PLL_VIDEO_CLR_LOCK_SHIFT (31U) +#define CCM_ANALOG_PLL_VIDEO_CLR_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_CLR_LOCK_SHIFT)) & CCM_ANALOG_PLL_VIDEO_CLR_LOCK_MASK) +/*! @} */ + +/*! @name PLL_VIDEO_TOG - Analog Video PLL control Register */ +/*! @{ */ +#define CCM_ANALOG_PLL_VIDEO_TOG_DIV_SELECT_MASK (0x7FU) +#define CCM_ANALOG_PLL_VIDEO_TOG_DIV_SELECT_SHIFT (0U) +#define CCM_ANALOG_PLL_VIDEO_TOG_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_TOG_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_VIDEO_TOG_DIV_SELECT_MASK) +#define CCM_ANALOG_PLL_VIDEO_TOG_POWERDOWN_MASK (0x1000U) +#define CCM_ANALOG_PLL_VIDEO_TOG_POWERDOWN_SHIFT (12U) +#define CCM_ANALOG_PLL_VIDEO_TOG_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_TOG_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_VIDEO_TOG_POWERDOWN_MASK) +#define CCM_ANALOG_PLL_VIDEO_TOG_ENABLE_MASK (0x2000U) +#define CCM_ANALOG_PLL_VIDEO_TOG_ENABLE_SHIFT (13U) +#define CCM_ANALOG_PLL_VIDEO_TOG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_TOG_ENABLE_SHIFT)) & CCM_ANALOG_PLL_VIDEO_TOG_ENABLE_MASK) +#define CCM_ANALOG_PLL_VIDEO_TOG_BYPASS_CLK_SRC_MASK (0xC000U) +#define CCM_ANALOG_PLL_VIDEO_TOG_BYPASS_CLK_SRC_SHIFT (14U) +/*! BYPASS_CLK_SRC + * 0b00..Select the 24MHz oscillator as source. + * 0b01..Select the CLK1_N / CLK1_P as source. + * 0b10..Reserved1 + * 0b11..Reserved2 + */ +#define CCM_ANALOG_PLL_VIDEO_TOG_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_TOG_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_VIDEO_TOG_BYPASS_CLK_SRC_MASK) +#define CCM_ANALOG_PLL_VIDEO_TOG_BYPASS_MASK (0x10000U) +#define CCM_ANALOG_PLL_VIDEO_TOG_BYPASS_SHIFT (16U) +#define CCM_ANALOG_PLL_VIDEO_TOG_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_TOG_BYPASS_SHIFT)) & CCM_ANALOG_PLL_VIDEO_TOG_BYPASS_MASK) +#define CCM_ANALOG_PLL_VIDEO_TOG_PFD_OFFSET_EN_MASK (0x40000U) +#define CCM_ANALOG_PLL_VIDEO_TOG_PFD_OFFSET_EN_SHIFT (18U) +#define CCM_ANALOG_PLL_VIDEO_TOG_PFD_OFFSET_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_TOG_PFD_OFFSET_EN_SHIFT)) & CCM_ANALOG_PLL_VIDEO_TOG_PFD_OFFSET_EN_MASK) +#define CCM_ANALOG_PLL_VIDEO_TOG_POST_DIV_SELECT_MASK (0x180000U) +#define CCM_ANALOG_PLL_VIDEO_TOG_POST_DIV_SELECT_SHIFT (19U) +/*! POST_DIV_SELECT + * 0b00..Divide by 4. + * 0b01..Divide by 2. + * 0b10..Divide by 1. + * 0b11..Reserved + */ +#define CCM_ANALOG_PLL_VIDEO_TOG_POST_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_TOG_POST_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_VIDEO_TOG_POST_DIV_SELECT_MASK) +#define CCM_ANALOG_PLL_VIDEO_TOG_LOCK_MASK (0x80000000U) +#define CCM_ANALOG_PLL_VIDEO_TOG_LOCK_SHIFT (31U) +#define CCM_ANALOG_PLL_VIDEO_TOG_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_TOG_LOCK_SHIFT)) & CCM_ANALOG_PLL_VIDEO_TOG_LOCK_MASK) +/*! @} */ + +/*! @name PLL_VIDEO_NUM - Numerator of Video PLL Fractional Loop Divider Register */ +/*! @{ */ +#define CCM_ANALOG_PLL_VIDEO_NUM_A_MASK (0x3FFFFFFFU) +#define CCM_ANALOG_PLL_VIDEO_NUM_A_SHIFT (0U) +#define CCM_ANALOG_PLL_VIDEO_NUM_A(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_NUM_A_SHIFT)) & CCM_ANALOG_PLL_VIDEO_NUM_A_MASK) +/*! @} */ + +/*! @name PLL_VIDEO_DENOM - Denominator of Video PLL Fractional Loop Divider Register */ +/*! @{ */ +#define CCM_ANALOG_PLL_VIDEO_DENOM_B_MASK (0x3FFFFFFFU) +#define CCM_ANALOG_PLL_VIDEO_DENOM_B_SHIFT (0U) +#define CCM_ANALOG_PLL_VIDEO_DENOM_B(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_DENOM_B_SHIFT)) & CCM_ANALOG_PLL_VIDEO_DENOM_B_MASK) +/*! @} */ + +/*! @name PLL_ENET - Analog ENET PLL Control Register */ +/*! @{ */ +#define CCM_ANALOG_PLL_ENET_DIV_SELECT_MASK (0x3U) +#define CCM_ANALOG_PLL_ENET_DIV_SELECT_SHIFT (0U) +#define CCM_ANALOG_PLL_ENET_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_ENET_DIV_SELECT_MASK) +#define CCM_ANALOG_PLL_ENET_POWERDOWN_MASK (0x1000U) +#define CCM_ANALOG_PLL_ENET_POWERDOWN_SHIFT (12U) +#define CCM_ANALOG_PLL_ENET_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_ENET_POWERDOWN_MASK) +#define CCM_ANALOG_PLL_ENET_ENABLE_MASK (0x2000U) +#define CCM_ANALOG_PLL_ENET_ENABLE_SHIFT (13U) +#define CCM_ANALOG_PLL_ENET_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_ENABLE_SHIFT)) & CCM_ANALOG_PLL_ENET_ENABLE_MASK) +#define CCM_ANALOG_PLL_ENET_BYPASS_CLK_SRC_MASK (0xC000U) +#define CCM_ANALOG_PLL_ENET_BYPASS_CLK_SRC_SHIFT (14U) +/*! BYPASS_CLK_SRC + * 0b00..Select the 24MHz oscillator as source. + * 0b01..Select the CLK1_N / CLK1_P as source. + * 0b10..Reserved1 + * 0b11..Reserved2 + */ +#define CCM_ANALOG_PLL_ENET_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_ENET_BYPASS_CLK_SRC_MASK) +#define CCM_ANALOG_PLL_ENET_BYPASS_MASK (0x10000U) +#define CCM_ANALOG_PLL_ENET_BYPASS_SHIFT (16U) +#define CCM_ANALOG_PLL_ENET_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_BYPASS_SHIFT)) & CCM_ANALOG_PLL_ENET_BYPASS_MASK) +#define CCM_ANALOG_PLL_ENET_PFD_OFFSET_EN_MASK (0x40000U) +#define CCM_ANALOG_PLL_ENET_PFD_OFFSET_EN_SHIFT (18U) +#define CCM_ANALOG_PLL_ENET_PFD_OFFSET_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_PFD_OFFSET_EN_SHIFT)) & CCM_ANALOG_PLL_ENET_PFD_OFFSET_EN_MASK) +#define CCM_ANALOG_PLL_ENET_ENET_25M_REF_EN_MASK (0x200000U) +#define CCM_ANALOG_PLL_ENET_ENET_25M_REF_EN_SHIFT (21U) +#define CCM_ANALOG_PLL_ENET_ENET_25M_REF_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_ENET_25M_REF_EN_SHIFT)) & CCM_ANALOG_PLL_ENET_ENET_25M_REF_EN_MASK) +#define CCM_ANALOG_PLL_ENET_LOCK_MASK (0x80000000U) +#define CCM_ANALOG_PLL_ENET_LOCK_SHIFT (31U) +#define CCM_ANALOG_PLL_ENET_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_LOCK_SHIFT)) & CCM_ANALOG_PLL_ENET_LOCK_MASK) +/*! @} */ + +/*! @name PLL_ENET_SET - Analog ENET PLL Control Register */ +/*! @{ */ +#define CCM_ANALOG_PLL_ENET_SET_DIV_SELECT_MASK (0x3U) +#define CCM_ANALOG_PLL_ENET_SET_DIV_SELECT_SHIFT (0U) +#define CCM_ANALOG_PLL_ENET_SET_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_SET_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_ENET_SET_DIV_SELECT_MASK) +#define CCM_ANALOG_PLL_ENET_SET_POWERDOWN_MASK (0x1000U) +#define CCM_ANALOG_PLL_ENET_SET_POWERDOWN_SHIFT (12U) +#define CCM_ANALOG_PLL_ENET_SET_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_SET_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_ENET_SET_POWERDOWN_MASK) +#define CCM_ANALOG_PLL_ENET_SET_ENABLE_MASK (0x2000U) +#define CCM_ANALOG_PLL_ENET_SET_ENABLE_SHIFT (13U) +#define CCM_ANALOG_PLL_ENET_SET_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_SET_ENABLE_SHIFT)) & CCM_ANALOG_PLL_ENET_SET_ENABLE_MASK) +#define CCM_ANALOG_PLL_ENET_SET_BYPASS_CLK_SRC_MASK (0xC000U) +#define CCM_ANALOG_PLL_ENET_SET_BYPASS_CLK_SRC_SHIFT (14U) +/*! BYPASS_CLK_SRC + * 0b00..Select the 24MHz oscillator as source. + * 0b01..Select the CLK1_N / CLK1_P as source. + * 0b10..Reserved1 + * 0b11..Reserved2 + */ +#define CCM_ANALOG_PLL_ENET_SET_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_SET_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_ENET_SET_BYPASS_CLK_SRC_MASK) +#define CCM_ANALOG_PLL_ENET_SET_BYPASS_MASK (0x10000U) +#define CCM_ANALOG_PLL_ENET_SET_BYPASS_SHIFT (16U) +#define CCM_ANALOG_PLL_ENET_SET_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_SET_BYPASS_SHIFT)) & CCM_ANALOG_PLL_ENET_SET_BYPASS_MASK) +#define CCM_ANALOG_PLL_ENET_SET_PFD_OFFSET_EN_MASK (0x40000U) +#define CCM_ANALOG_PLL_ENET_SET_PFD_OFFSET_EN_SHIFT (18U) +#define CCM_ANALOG_PLL_ENET_SET_PFD_OFFSET_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_SET_PFD_OFFSET_EN_SHIFT)) & CCM_ANALOG_PLL_ENET_SET_PFD_OFFSET_EN_MASK) +#define CCM_ANALOG_PLL_ENET_SET_ENET_25M_REF_EN_MASK (0x200000U) +#define CCM_ANALOG_PLL_ENET_SET_ENET_25M_REF_EN_SHIFT (21U) +#define CCM_ANALOG_PLL_ENET_SET_ENET_25M_REF_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_SET_ENET_25M_REF_EN_SHIFT)) & CCM_ANALOG_PLL_ENET_SET_ENET_25M_REF_EN_MASK) +#define CCM_ANALOG_PLL_ENET_SET_LOCK_MASK (0x80000000U) +#define CCM_ANALOG_PLL_ENET_SET_LOCK_SHIFT (31U) +#define CCM_ANALOG_PLL_ENET_SET_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_SET_LOCK_SHIFT)) & CCM_ANALOG_PLL_ENET_SET_LOCK_MASK) +/*! @} */ + +/*! @name PLL_ENET_CLR - Analog ENET PLL Control Register */ +/*! @{ */ +#define CCM_ANALOG_PLL_ENET_CLR_DIV_SELECT_MASK (0x3U) +#define CCM_ANALOG_PLL_ENET_CLR_DIV_SELECT_SHIFT (0U) +#define CCM_ANALOG_PLL_ENET_CLR_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_CLR_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_ENET_CLR_DIV_SELECT_MASK) +#define CCM_ANALOG_PLL_ENET_CLR_POWERDOWN_MASK (0x1000U) +#define CCM_ANALOG_PLL_ENET_CLR_POWERDOWN_SHIFT (12U) +#define CCM_ANALOG_PLL_ENET_CLR_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_CLR_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_ENET_CLR_POWERDOWN_MASK) +#define CCM_ANALOG_PLL_ENET_CLR_ENABLE_MASK (0x2000U) +#define CCM_ANALOG_PLL_ENET_CLR_ENABLE_SHIFT (13U) +#define CCM_ANALOG_PLL_ENET_CLR_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_CLR_ENABLE_SHIFT)) & CCM_ANALOG_PLL_ENET_CLR_ENABLE_MASK) +#define CCM_ANALOG_PLL_ENET_CLR_BYPASS_CLK_SRC_MASK (0xC000U) +#define CCM_ANALOG_PLL_ENET_CLR_BYPASS_CLK_SRC_SHIFT (14U) +/*! BYPASS_CLK_SRC + * 0b00..Select the 24MHz oscillator as source. + * 0b01..Select the CLK1_N / CLK1_P as source. + * 0b10..Reserved1 + * 0b11..Reserved2 + */ +#define CCM_ANALOG_PLL_ENET_CLR_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_CLR_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_ENET_CLR_BYPASS_CLK_SRC_MASK) +#define CCM_ANALOG_PLL_ENET_CLR_BYPASS_MASK (0x10000U) +#define CCM_ANALOG_PLL_ENET_CLR_BYPASS_SHIFT (16U) +#define CCM_ANALOG_PLL_ENET_CLR_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_CLR_BYPASS_SHIFT)) & CCM_ANALOG_PLL_ENET_CLR_BYPASS_MASK) +#define CCM_ANALOG_PLL_ENET_CLR_PFD_OFFSET_EN_MASK (0x40000U) +#define CCM_ANALOG_PLL_ENET_CLR_PFD_OFFSET_EN_SHIFT (18U) +#define CCM_ANALOG_PLL_ENET_CLR_PFD_OFFSET_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_CLR_PFD_OFFSET_EN_SHIFT)) & CCM_ANALOG_PLL_ENET_CLR_PFD_OFFSET_EN_MASK) +#define CCM_ANALOG_PLL_ENET_CLR_ENET_25M_REF_EN_MASK (0x200000U) +#define CCM_ANALOG_PLL_ENET_CLR_ENET_25M_REF_EN_SHIFT (21U) +#define CCM_ANALOG_PLL_ENET_CLR_ENET_25M_REF_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_CLR_ENET_25M_REF_EN_SHIFT)) & CCM_ANALOG_PLL_ENET_CLR_ENET_25M_REF_EN_MASK) +#define CCM_ANALOG_PLL_ENET_CLR_LOCK_MASK (0x80000000U) +#define CCM_ANALOG_PLL_ENET_CLR_LOCK_SHIFT (31U) +#define CCM_ANALOG_PLL_ENET_CLR_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_CLR_LOCK_SHIFT)) & CCM_ANALOG_PLL_ENET_CLR_LOCK_MASK) +/*! @} */ + +/*! @name PLL_ENET_TOG - Analog ENET PLL Control Register */ +/*! @{ */ +#define CCM_ANALOG_PLL_ENET_TOG_DIV_SELECT_MASK (0x3U) +#define CCM_ANALOG_PLL_ENET_TOG_DIV_SELECT_SHIFT (0U) +#define CCM_ANALOG_PLL_ENET_TOG_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_TOG_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_ENET_TOG_DIV_SELECT_MASK) +#define CCM_ANALOG_PLL_ENET_TOG_POWERDOWN_MASK (0x1000U) +#define CCM_ANALOG_PLL_ENET_TOG_POWERDOWN_SHIFT (12U) +#define CCM_ANALOG_PLL_ENET_TOG_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_TOG_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_ENET_TOG_POWERDOWN_MASK) +#define CCM_ANALOG_PLL_ENET_TOG_ENABLE_MASK (0x2000U) +#define CCM_ANALOG_PLL_ENET_TOG_ENABLE_SHIFT (13U) +#define CCM_ANALOG_PLL_ENET_TOG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_TOG_ENABLE_SHIFT)) & CCM_ANALOG_PLL_ENET_TOG_ENABLE_MASK) +#define CCM_ANALOG_PLL_ENET_TOG_BYPASS_CLK_SRC_MASK (0xC000U) +#define CCM_ANALOG_PLL_ENET_TOG_BYPASS_CLK_SRC_SHIFT (14U) +/*! BYPASS_CLK_SRC + * 0b00..Select the 24MHz oscillator as source. + * 0b01..Select the CLK1_N / CLK1_P as source. + * 0b10..Reserved1 + * 0b11..Reserved2 + */ +#define CCM_ANALOG_PLL_ENET_TOG_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_TOG_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_ENET_TOG_BYPASS_CLK_SRC_MASK) +#define CCM_ANALOG_PLL_ENET_TOG_BYPASS_MASK (0x10000U) +#define CCM_ANALOG_PLL_ENET_TOG_BYPASS_SHIFT (16U) +#define CCM_ANALOG_PLL_ENET_TOG_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_TOG_BYPASS_SHIFT)) & CCM_ANALOG_PLL_ENET_TOG_BYPASS_MASK) +#define CCM_ANALOG_PLL_ENET_TOG_PFD_OFFSET_EN_MASK (0x40000U) +#define CCM_ANALOG_PLL_ENET_TOG_PFD_OFFSET_EN_SHIFT (18U) +#define CCM_ANALOG_PLL_ENET_TOG_PFD_OFFSET_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_TOG_PFD_OFFSET_EN_SHIFT)) & CCM_ANALOG_PLL_ENET_TOG_PFD_OFFSET_EN_MASK) +#define CCM_ANALOG_PLL_ENET_TOG_ENET_25M_REF_EN_MASK (0x200000U) +#define CCM_ANALOG_PLL_ENET_TOG_ENET_25M_REF_EN_SHIFT (21U) +#define CCM_ANALOG_PLL_ENET_TOG_ENET_25M_REF_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_TOG_ENET_25M_REF_EN_SHIFT)) & CCM_ANALOG_PLL_ENET_TOG_ENET_25M_REF_EN_MASK) +#define CCM_ANALOG_PLL_ENET_TOG_LOCK_MASK (0x80000000U) +#define CCM_ANALOG_PLL_ENET_TOG_LOCK_SHIFT (31U) +#define CCM_ANALOG_PLL_ENET_TOG_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_TOG_LOCK_SHIFT)) & CCM_ANALOG_PLL_ENET_TOG_LOCK_MASK) +/*! @} */ + +/*! @name PFD_480 - 480MHz Clock (PLL3) Phase Fractional Divider Control Register */ +/*! @{ */ +#define CCM_ANALOG_PFD_480_PFD0_FRAC_MASK (0x3FU) +#define CCM_ANALOG_PFD_480_PFD0_FRAC_SHIFT (0U) +#define CCM_ANALOG_PFD_480_PFD0_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_PFD0_FRAC_SHIFT)) & CCM_ANALOG_PFD_480_PFD0_FRAC_MASK) +#define CCM_ANALOG_PFD_480_PFD0_STABLE_MASK (0x40U) +#define CCM_ANALOG_PFD_480_PFD0_STABLE_SHIFT (6U) +#define CCM_ANALOG_PFD_480_PFD0_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_PFD0_STABLE_SHIFT)) & CCM_ANALOG_PFD_480_PFD0_STABLE_MASK) +#define CCM_ANALOG_PFD_480_PFD0_CLKGATE_MASK (0x80U) +#define CCM_ANALOG_PFD_480_PFD0_CLKGATE_SHIFT (7U) +#define CCM_ANALOG_PFD_480_PFD0_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_PFD0_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_480_PFD0_CLKGATE_MASK) +#define CCM_ANALOG_PFD_480_PFD1_FRAC_MASK (0x3F00U) +#define CCM_ANALOG_PFD_480_PFD1_FRAC_SHIFT (8U) +#define CCM_ANALOG_PFD_480_PFD1_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_PFD1_FRAC_SHIFT)) & CCM_ANALOG_PFD_480_PFD1_FRAC_MASK) +#define CCM_ANALOG_PFD_480_PFD1_STABLE_MASK (0x4000U) +#define CCM_ANALOG_PFD_480_PFD1_STABLE_SHIFT (14U) +#define CCM_ANALOG_PFD_480_PFD1_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_PFD1_STABLE_SHIFT)) & CCM_ANALOG_PFD_480_PFD1_STABLE_MASK) +#define CCM_ANALOG_PFD_480_PFD1_CLKGATE_MASK (0x8000U) +#define CCM_ANALOG_PFD_480_PFD1_CLKGATE_SHIFT (15U) +#define CCM_ANALOG_PFD_480_PFD1_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_PFD1_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_480_PFD1_CLKGATE_MASK) +#define CCM_ANALOG_PFD_480_PFD2_FRAC_MASK (0x3F0000U) +#define CCM_ANALOG_PFD_480_PFD2_FRAC_SHIFT (16U) +#define CCM_ANALOG_PFD_480_PFD2_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_PFD2_FRAC_SHIFT)) & CCM_ANALOG_PFD_480_PFD2_FRAC_MASK) +#define CCM_ANALOG_PFD_480_PFD2_STABLE_MASK (0x400000U) +#define CCM_ANALOG_PFD_480_PFD2_STABLE_SHIFT (22U) +#define CCM_ANALOG_PFD_480_PFD2_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_PFD2_STABLE_SHIFT)) & CCM_ANALOG_PFD_480_PFD2_STABLE_MASK) +#define CCM_ANALOG_PFD_480_PFD2_CLKGATE_MASK (0x800000U) +#define CCM_ANALOG_PFD_480_PFD2_CLKGATE_SHIFT (23U) +#define CCM_ANALOG_PFD_480_PFD2_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_PFD2_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_480_PFD2_CLKGATE_MASK) +#define CCM_ANALOG_PFD_480_PFD3_FRAC_MASK (0x3F000000U) +#define CCM_ANALOG_PFD_480_PFD3_FRAC_SHIFT (24U) +#define CCM_ANALOG_PFD_480_PFD3_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_PFD3_FRAC_SHIFT)) & CCM_ANALOG_PFD_480_PFD3_FRAC_MASK) +#define CCM_ANALOG_PFD_480_PFD3_STABLE_MASK (0x40000000U) +#define CCM_ANALOG_PFD_480_PFD3_STABLE_SHIFT (30U) +#define CCM_ANALOG_PFD_480_PFD3_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_PFD3_STABLE_SHIFT)) & CCM_ANALOG_PFD_480_PFD3_STABLE_MASK) +#define CCM_ANALOG_PFD_480_PFD3_CLKGATE_MASK (0x80000000U) +#define CCM_ANALOG_PFD_480_PFD3_CLKGATE_SHIFT (31U) +#define CCM_ANALOG_PFD_480_PFD3_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_PFD3_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_480_PFD3_CLKGATE_MASK) +/*! @} */ + +/*! @name PFD_480_SET - 480MHz Clock (PLL3) Phase Fractional Divider Control Register */ +/*! @{ */ +#define CCM_ANALOG_PFD_480_SET_PFD0_FRAC_MASK (0x3FU) +#define CCM_ANALOG_PFD_480_SET_PFD0_FRAC_SHIFT (0U) +#define CCM_ANALOG_PFD_480_SET_PFD0_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_SET_PFD0_FRAC_SHIFT)) & CCM_ANALOG_PFD_480_SET_PFD0_FRAC_MASK) +#define CCM_ANALOG_PFD_480_SET_PFD0_STABLE_MASK (0x40U) +#define CCM_ANALOG_PFD_480_SET_PFD0_STABLE_SHIFT (6U) +#define CCM_ANALOG_PFD_480_SET_PFD0_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_SET_PFD0_STABLE_SHIFT)) & CCM_ANALOG_PFD_480_SET_PFD0_STABLE_MASK) +#define CCM_ANALOG_PFD_480_SET_PFD0_CLKGATE_MASK (0x80U) +#define CCM_ANALOG_PFD_480_SET_PFD0_CLKGATE_SHIFT (7U) +#define CCM_ANALOG_PFD_480_SET_PFD0_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_SET_PFD0_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_480_SET_PFD0_CLKGATE_MASK) +#define CCM_ANALOG_PFD_480_SET_PFD1_FRAC_MASK (0x3F00U) +#define CCM_ANALOG_PFD_480_SET_PFD1_FRAC_SHIFT (8U) +#define CCM_ANALOG_PFD_480_SET_PFD1_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_SET_PFD1_FRAC_SHIFT)) & CCM_ANALOG_PFD_480_SET_PFD1_FRAC_MASK) +#define CCM_ANALOG_PFD_480_SET_PFD1_STABLE_MASK (0x4000U) +#define CCM_ANALOG_PFD_480_SET_PFD1_STABLE_SHIFT (14U) +#define CCM_ANALOG_PFD_480_SET_PFD1_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_SET_PFD1_STABLE_SHIFT)) & CCM_ANALOG_PFD_480_SET_PFD1_STABLE_MASK) +#define CCM_ANALOG_PFD_480_SET_PFD1_CLKGATE_MASK (0x8000U) +#define CCM_ANALOG_PFD_480_SET_PFD1_CLKGATE_SHIFT (15U) +#define CCM_ANALOG_PFD_480_SET_PFD1_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_SET_PFD1_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_480_SET_PFD1_CLKGATE_MASK) +#define CCM_ANALOG_PFD_480_SET_PFD2_FRAC_MASK (0x3F0000U) +#define CCM_ANALOG_PFD_480_SET_PFD2_FRAC_SHIFT (16U) +#define CCM_ANALOG_PFD_480_SET_PFD2_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_SET_PFD2_FRAC_SHIFT)) & CCM_ANALOG_PFD_480_SET_PFD2_FRAC_MASK) +#define CCM_ANALOG_PFD_480_SET_PFD2_STABLE_MASK (0x400000U) +#define CCM_ANALOG_PFD_480_SET_PFD2_STABLE_SHIFT (22U) +#define CCM_ANALOG_PFD_480_SET_PFD2_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_SET_PFD2_STABLE_SHIFT)) & CCM_ANALOG_PFD_480_SET_PFD2_STABLE_MASK) +#define CCM_ANALOG_PFD_480_SET_PFD2_CLKGATE_MASK (0x800000U) +#define CCM_ANALOG_PFD_480_SET_PFD2_CLKGATE_SHIFT (23U) +#define CCM_ANALOG_PFD_480_SET_PFD2_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_SET_PFD2_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_480_SET_PFD2_CLKGATE_MASK) +#define CCM_ANALOG_PFD_480_SET_PFD3_FRAC_MASK (0x3F000000U) +#define CCM_ANALOG_PFD_480_SET_PFD3_FRAC_SHIFT (24U) +#define CCM_ANALOG_PFD_480_SET_PFD3_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_SET_PFD3_FRAC_SHIFT)) & CCM_ANALOG_PFD_480_SET_PFD3_FRAC_MASK) +#define CCM_ANALOG_PFD_480_SET_PFD3_STABLE_MASK (0x40000000U) +#define CCM_ANALOG_PFD_480_SET_PFD3_STABLE_SHIFT (30U) +#define CCM_ANALOG_PFD_480_SET_PFD3_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_SET_PFD3_STABLE_SHIFT)) & CCM_ANALOG_PFD_480_SET_PFD3_STABLE_MASK) +#define CCM_ANALOG_PFD_480_SET_PFD3_CLKGATE_MASK (0x80000000U) +#define CCM_ANALOG_PFD_480_SET_PFD3_CLKGATE_SHIFT (31U) +#define CCM_ANALOG_PFD_480_SET_PFD3_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_SET_PFD3_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_480_SET_PFD3_CLKGATE_MASK) +/*! @} */ + +/*! @name PFD_480_CLR - 480MHz Clock (PLL3) Phase Fractional Divider Control Register */ +/*! @{ */ +#define CCM_ANALOG_PFD_480_CLR_PFD0_FRAC_MASK (0x3FU) +#define CCM_ANALOG_PFD_480_CLR_PFD0_FRAC_SHIFT (0U) +#define CCM_ANALOG_PFD_480_CLR_PFD0_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_CLR_PFD0_FRAC_SHIFT)) & CCM_ANALOG_PFD_480_CLR_PFD0_FRAC_MASK) +#define CCM_ANALOG_PFD_480_CLR_PFD0_STABLE_MASK (0x40U) +#define CCM_ANALOG_PFD_480_CLR_PFD0_STABLE_SHIFT (6U) +#define CCM_ANALOG_PFD_480_CLR_PFD0_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_CLR_PFD0_STABLE_SHIFT)) & CCM_ANALOG_PFD_480_CLR_PFD0_STABLE_MASK) +#define CCM_ANALOG_PFD_480_CLR_PFD0_CLKGATE_MASK (0x80U) +#define CCM_ANALOG_PFD_480_CLR_PFD0_CLKGATE_SHIFT (7U) +#define CCM_ANALOG_PFD_480_CLR_PFD0_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_CLR_PFD0_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_480_CLR_PFD0_CLKGATE_MASK) +#define CCM_ANALOG_PFD_480_CLR_PFD1_FRAC_MASK (0x3F00U) +#define CCM_ANALOG_PFD_480_CLR_PFD1_FRAC_SHIFT (8U) +#define CCM_ANALOG_PFD_480_CLR_PFD1_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_CLR_PFD1_FRAC_SHIFT)) & CCM_ANALOG_PFD_480_CLR_PFD1_FRAC_MASK) +#define CCM_ANALOG_PFD_480_CLR_PFD1_STABLE_MASK (0x4000U) +#define CCM_ANALOG_PFD_480_CLR_PFD1_STABLE_SHIFT (14U) +#define CCM_ANALOG_PFD_480_CLR_PFD1_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_CLR_PFD1_STABLE_SHIFT)) & CCM_ANALOG_PFD_480_CLR_PFD1_STABLE_MASK) +#define CCM_ANALOG_PFD_480_CLR_PFD1_CLKGATE_MASK (0x8000U) +#define CCM_ANALOG_PFD_480_CLR_PFD1_CLKGATE_SHIFT (15U) +#define CCM_ANALOG_PFD_480_CLR_PFD1_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_CLR_PFD1_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_480_CLR_PFD1_CLKGATE_MASK) +#define CCM_ANALOG_PFD_480_CLR_PFD2_FRAC_MASK (0x3F0000U) +#define CCM_ANALOG_PFD_480_CLR_PFD2_FRAC_SHIFT (16U) +#define CCM_ANALOG_PFD_480_CLR_PFD2_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_CLR_PFD2_FRAC_SHIFT)) & CCM_ANALOG_PFD_480_CLR_PFD2_FRAC_MASK) +#define CCM_ANALOG_PFD_480_CLR_PFD2_STABLE_MASK (0x400000U) +#define CCM_ANALOG_PFD_480_CLR_PFD2_STABLE_SHIFT (22U) +#define CCM_ANALOG_PFD_480_CLR_PFD2_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_CLR_PFD2_STABLE_SHIFT)) & CCM_ANALOG_PFD_480_CLR_PFD2_STABLE_MASK) +#define CCM_ANALOG_PFD_480_CLR_PFD2_CLKGATE_MASK (0x800000U) +#define CCM_ANALOG_PFD_480_CLR_PFD2_CLKGATE_SHIFT (23U) +#define CCM_ANALOG_PFD_480_CLR_PFD2_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_CLR_PFD2_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_480_CLR_PFD2_CLKGATE_MASK) +#define CCM_ANALOG_PFD_480_CLR_PFD3_FRAC_MASK (0x3F000000U) +#define CCM_ANALOG_PFD_480_CLR_PFD3_FRAC_SHIFT (24U) +#define CCM_ANALOG_PFD_480_CLR_PFD3_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_CLR_PFD3_FRAC_SHIFT)) & CCM_ANALOG_PFD_480_CLR_PFD3_FRAC_MASK) +#define CCM_ANALOG_PFD_480_CLR_PFD3_STABLE_MASK (0x40000000U) +#define CCM_ANALOG_PFD_480_CLR_PFD3_STABLE_SHIFT (30U) +#define CCM_ANALOG_PFD_480_CLR_PFD3_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_CLR_PFD3_STABLE_SHIFT)) & CCM_ANALOG_PFD_480_CLR_PFD3_STABLE_MASK) +#define CCM_ANALOG_PFD_480_CLR_PFD3_CLKGATE_MASK (0x80000000U) +#define CCM_ANALOG_PFD_480_CLR_PFD3_CLKGATE_SHIFT (31U) +#define CCM_ANALOG_PFD_480_CLR_PFD3_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_CLR_PFD3_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_480_CLR_PFD3_CLKGATE_MASK) +/*! @} */ + +/*! @name PFD_480_TOG - 480MHz Clock (PLL3) Phase Fractional Divider Control Register */ +/*! @{ */ +#define CCM_ANALOG_PFD_480_TOG_PFD0_FRAC_MASK (0x3FU) +#define CCM_ANALOG_PFD_480_TOG_PFD0_FRAC_SHIFT (0U) +#define CCM_ANALOG_PFD_480_TOG_PFD0_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_TOG_PFD0_FRAC_SHIFT)) & CCM_ANALOG_PFD_480_TOG_PFD0_FRAC_MASK) +#define CCM_ANALOG_PFD_480_TOG_PFD0_STABLE_MASK (0x40U) +#define CCM_ANALOG_PFD_480_TOG_PFD0_STABLE_SHIFT (6U) +#define CCM_ANALOG_PFD_480_TOG_PFD0_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_TOG_PFD0_STABLE_SHIFT)) & CCM_ANALOG_PFD_480_TOG_PFD0_STABLE_MASK) +#define CCM_ANALOG_PFD_480_TOG_PFD0_CLKGATE_MASK (0x80U) +#define CCM_ANALOG_PFD_480_TOG_PFD0_CLKGATE_SHIFT (7U) +#define CCM_ANALOG_PFD_480_TOG_PFD0_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_TOG_PFD0_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_480_TOG_PFD0_CLKGATE_MASK) +#define CCM_ANALOG_PFD_480_TOG_PFD1_FRAC_MASK (0x3F00U) +#define CCM_ANALOG_PFD_480_TOG_PFD1_FRAC_SHIFT (8U) +#define CCM_ANALOG_PFD_480_TOG_PFD1_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_TOG_PFD1_FRAC_SHIFT)) & CCM_ANALOG_PFD_480_TOG_PFD1_FRAC_MASK) +#define CCM_ANALOG_PFD_480_TOG_PFD1_STABLE_MASK (0x4000U) +#define CCM_ANALOG_PFD_480_TOG_PFD1_STABLE_SHIFT (14U) +#define CCM_ANALOG_PFD_480_TOG_PFD1_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_TOG_PFD1_STABLE_SHIFT)) & CCM_ANALOG_PFD_480_TOG_PFD1_STABLE_MASK) +#define CCM_ANALOG_PFD_480_TOG_PFD1_CLKGATE_MASK (0x8000U) +#define CCM_ANALOG_PFD_480_TOG_PFD1_CLKGATE_SHIFT (15U) +#define CCM_ANALOG_PFD_480_TOG_PFD1_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_TOG_PFD1_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_480_TOG_PFD1_CLKGATE_MASK) +#define CCM_ANALOG_PFD_480_TOG_PFD2_FRAC_MASK (0x3F0000U) +#define CCM_ANALOG_PFD_480_TOG_PFD2_FRAC_SHIFT (16U) +#define CCM_ANALOG_PFD_480_TOG_PFD2_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_TOG_PFD2_FRAC_SHIFT)) & CCM_ANALOG_PFD_480_TOG_PFD2_FRAC_MASK) +#define CCM_ANALOG_PFD_480_TOG_PFD2_STABLE_MASK (0x400000U) +#define CCM_ANALOG_PFD_480_TOG_PFD2_STABLE_SHIFT (22U) +#define CCM_ANALOG_PFD_480_TOG_PFD2_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_TOG_PFD2_STABLE_SHIFT)) & CCM_ANALOG_PFD_480_TOG_PFD2_STABLE_MASK) +#define CCM_ANALOG_PFD_480_TOG_PFD2_CLKGATE_MASK (0x800000U) +#define CCM_ANALOG_PFD_480_TOG_PFD2_CLKGATE_SHIFT (23U) +#define CCM_ANALOG_PFD_480_TOG_PFD2_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_TOG_PFD2_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_480_TOG_PFD2_CLKGATE_MASK) +#define CCM_ANALOG_PFD_480_TOG_PFD3_FRAC_MASK (0x3F000000U) +#define CCM_ANALOG_PFD_480_TOG_PFD3_FRAC_SHIFT (24U) +#define CCM_ANALOG_PFD_480_TOG_PFD3_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_TOG_PFD3_FRAC_SHIFT)) & CCM_ANALOG_PFD_480_TOG_PFD3_FRAC_MASK) +#define CCM_ANALOG_PFD_480_TOG_PFD3_STABLE_MASK (0x40000000U) +#define CCM_ANALOG_PFD_480_TOG_PFD3_STABLE_SHIFT (30U) +#define CCM_ANALOG_PFD_480_TOG_PFD3_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_TOG_PFD3_STABLE_SHIFT)) & CCM_ANALOG_PFD_480_TOG_PFD3_STABLE_MASK) +#define CCM_ANALOG_PFD_480_TOG_PFD3_CLKGATE_MASK (0x80000000U) +#define CCM_ANALOG_PFD_480_TOG_PFD3_CLKGATE_SHIFT (31U) +#define CCM_ANALOG_PFD_480_TOG_PFD3_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_TOG_PFD3_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_480_TOG_PFD3_CLKGATE_MASK) +/*! @} */ + +/*! @name PFD_528 - 528MHz Clock (PLL2) Phase Fractional Divider Control Register */ +/*! @{ */ +#define CCM_ANALOG_PFD_528_PFD0_FRAC_MASK (0x3FU) +#define CCM_ANALOG_PFD_528_PFD0_FRAC_SHIFT (0U) +#define CCM_ANALOG_PFD_528_PFD0_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_PFD0_FRAC_SHIFT)) & CCM_ANALOG_PFD_528_PFD0_FRAC_MASK) +#define CCM_ANALOG_PFD_528_PFD0_STABLE_MASK (0x40U) +#define CCM_ANALOG_PFD_528_PFD0_STABLE_SHIFT (6U) +#define CCM_ANALOG_PFD_528_PFD0_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_PFD0_STABLE_SHIFT)) & CCM_ANALOG_PFD_528_PFD0_STABLE_MASK) +#define CCM_ANALOG_PFD_528_PFD0_CLKGATE_MASK (0x80U) +#define CCM_ANALOG_PFD_528_PFD0_CLKGATE_SHIFT (7U) +#define CCM_ANALOG_PFD_528_PFD0_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_PFD0_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_528_PFD0_CLKGATE_MASK) +#define CCM_ANALOG_PFD_528_PFD1_FRAC_MASK (0x3F00U) +#define CCM_ANALOG_PFD_528_PFD1_FRAC_SHIFT (8U) +#define CCM_ANALOG_PFD_528_PFD1_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_PFD1_FRAC_SHIFT)) & CCM_ANALOG_PFD_528_PFD1_FRAC_MASK) +#define CCM_ANALOG_PFD_528_PFD1_STABLE_MASK (0x4000U) +#define CCM_ANALOG_PFD_528_PFD1_STABLE_SHIFT (14U) +#define CCM_ANALOG_PFD_528_PFD1_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_PFD1_STABLE_SHIFT)) & CCM_ANALOG_PFD_528_PFD1_STABLE_MASK) +#define CCM_ANALOG_PFD_528_PFD1_CLKGATE_MASK (0x8000U) +#define CCM_ANALOG_PFD_528_PFD1_CLKGATE_SHIFT (15U) +#define CCM_ANALOG_PFD_528_PFD1_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_PFD1_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_528_PFD1_CLKGATE_MASK) +#define CCM_ANALOG_PFD_528_PFD2_FRAC_MASK (0x3F0000U) +#define CCM_ANALOG_PFD_528_PFD2_FRAC_SHIFT (16U) +#define CCM_ANALOG_PFD_528_PFD2_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_PFD2_FRAC_SHIFT)) & CCM_ANALOG_PFD_528_PFD2_FRAC_MASK) +#define CCM_ANALOG_PFD_528_PFD2_STABLE_MASK (0x400000U) +#define CCM_ANALOG_PFD_528_PFD2_STABLE_SHIFT (22U) +#define CCM_ANALOG_PFD_528_PFD2_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_PFD2_STABLE_SHIFT)) & CCM_ANALOG_PFD_528_PFD2_STABLE_MASK) +#define CCM_ANALOG_PFD_528_PFD2_CLKGATE_MASK (0x800000U) +#define CCM_ANALOG_PFD_528_PFD2_CLKGATE_SHIFT (23U) +#define CCM_ANALOG_PFD_528_PFD2_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_PFD2_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_528_PFD2_CLKGATE_MASK) +#define CCM_ANALOG_PFD_528_PFD3_FRAC_MASK (0x3F000000U) +#define CCM_ANALOG_PFD_528_PFD3_FRAC_SHIFT (24U) +#define CCM_ANALOG_PFD_528_PFD3_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_PFD3_FRAC_SHIFT)) & CCM_ANALOG_PFD_528_PFD3_FRAC_MASK) +#define CCM_ANALOG_PFD_528_PFD3_STABLE_MASK (0x40000000U) +#define CCM_ANALOG_PFD_528_PFD3_STABLE_SHIFT (30U) +#define CCM_ANALOG_PFD_528_PFD3_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_PFD3_STABLE_SHIFT)) & CCM_ANALOG_PFD_528_PFD3_STABLE_MASK) +#define CCM_ANALOG_PFD_528_PFD3_CLKGATE_MASK (0x80000000U) +#define CCM_ANALOG_PFD_528_PFD3_CLKGATE_SHIFT (31U) +#define CCM_ANALOG_PFD_528_PFD3_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_PFD3_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_528_PFD3_CLKGATE_MASK) +/*! @} */ + +/*! @name PFD_528_SET - 528MHz Clock (PLL2) Phase Fractional Divider Control Register */ +/*! @{ */ +#define CCM_ANALOG_PFD_528_SET_PFD0_FRAC_MASK (0x3FU) +#define CCM_ANALOG_PFD_528_SET_PFD0_FRAC_SHIFT (0U) +#define CCM_ANALOG_PFD_528_SET_PFD0_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_SET_PFD0_FRAC_SHIFT)) & CCM_ANALOG_PFD_528_SET_PFD0_FRAC_MASK) +#define CCM_ANALOG_PFD_528_SET_PFD0_STABLE_MASK (0x40U) +#define CCM_ANALOG_PFD_528_SET_PFD0_STABLE_SHIFT (6U) +#define CCM_ANALOG_PFD_528_SET_PFD0_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_SET_PFD0_STABLE_SHIFT)) & CCM_ANALOG_PFD_528_SET_PFD0_STABLE_MASK) +#define CCM_ANALOG_PFD_528_SET_PFD0_CLKGATE_MASK (0x80U) +#define CCM_ANALOG_PFD_528_SET_PFD0_CLKGATE_SHIFT (7U) +#define CCM_ANALOG_PFD_528_SET_PFD0_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_SET_PFD0_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_528_SET_PFD0_CLKGATE_MASK) +#define CCM_ANALOG_PFD_528_SET_PFD1_FRAC_MASK (0x3F00U) +#define CCM_ANALOG_PFD_528_SET_PFD1_FRAC_SHIFT (8U) +#define CCM_ANALOG_PFD_528_SET_PFD1_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_SET_PFD1_FRAC_SHIFT)) & CCM_ANALOG_PFD_528_SET_PFD1_FRAC_MASK) +#define CCM_ANALOG_PFD_528_SET_PFD1_STABLE_MASK (0x4000U) +#define CCM_ANALOG_PFD_528_SET_PFD1_STABLE_SHIFT (14U) +#define CCM_ANALOG_PFD_528_SET_PFD1_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_SET_PFD1_STABLE_SHIFT)) & CCM_ANALOG_PFD_528_SET_PFD1_STABLE_MASK) +#define CCM_ANALOG_PFD_528_SET_PFD1_CLKGATE_MASK (0x8000U) +#define CCM_ANALOG_PFD_528_SET_PFD1_CLKGATE_SHIFT (15U) +#define CCM_ANALOG_PFD_528_SET_PFD1_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_SET_PFD1_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_528_SET_PFD1_CLKGATE_MASK) +#define CCM_ANALOG_PFD_528_SET_PFD2_FRAC_MASK (0x3F0000U) +#define CCM_ANALOG_PFD_528_SET_PFD2_FRAC_SHIFT (16U) +#define CCM_ANALOG_PFD_528_SET_PFD2_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_SET_PFD2_FRAC_SHIFT)) & CCM_ANALOG_PFD_528_SET_PFD2_FRAC_MASK) +#define CCM_ANALOG_PFD_528_SET_PFD2_STABLE_MASK (0x400000U) +#define CCM_ANALOG_PFD_528_SET_PFD2_STABLE_SHIFT (22U) +#define CCM_ANALOG_PFD_528_SET_PFD2_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_SET_PFD2_STABLE_SHIFT)) & CCM_ANALOG_PFD_528_SET_PFD2_STABLE_MASK) +#define CCM_ANALOG_PFD_528_SET_PFD2_CLKGATE_MASK (0x800000U) +#define CCM_ANALOG_PFD_528_SET_PFD2_CLKGATE_SHIFT (23U) +#define CCM_ANALOG_PFD_528_SET_PFD2_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_SET_PFD2_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_528_SET_PFD2_CLKGATE_MASK) +#define CCM_ANALOG_PFD_528_SET_PFD3_FRAC_MASK (0x3F000000U) +#define CCM_ANALOG_PFD_528_SET_PFD3_FRAC_SHIFT (24U) +#define CCM_ANALOG_PFD_528_SET_PFD3_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_SET_PFD3_FRAC_SHIFT)) & CCM_ANALOG_PFD_528_SET_PFD3_FRAC_MASK) +#define CCM_ANALOG_PFD_528_SET_PFD3_STABLE_MASK (0x40000000U) +#define CCM_ANALOG_PFD_528_SET_PFD3_STABLE_SHIFT (30U) +#define CCM_ANALOG_PFD_528_SET_PFD3_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_SET_PFD3_STABLE_SHIFT)) & CCM_ANALOG_PFD_528_SET_PFD3_STABLE_MASK) +#define CCM_ANALOG_PFD_528_SET_PFD3_CLKGATE_MASK (0x80000000U) +#define CCM_ANALOG_PFD_528_SET_PFD3_CLKGATE_SHIFT (31U) +#define CCM_ANALOG_PFD_528_SET_PFD3_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_SET_PFD3_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_528_SET_PFD3_CLKGATE_MASK) +/*! @} */ + +/*! @name PFD_528_CLR - 528MHz Clock (PLL2) Phase Fractional Divider Control Register */ +/*! @{ */ +#define CCM_ANALOG_PFD_528_CLR_PFD0_FRAC_MASK (0x3FU) +#define CCM_ANALOG_PFD_528_CLR_PFD0_FRAC_SHIFT (0U) +#define CCM_ANALOG_PFD_528_CLR_PFD0_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_CLR_PFD0_FRAC_SHIFT)) & CCM_ANALOG_PFD_528_CLR_PFD0_FRAC_MASK) +#define CCM_ANALOG_PFD_528_CLR_PFD0_STABLE_MASK (0x40U) +#define CCM_ANALOG_PFD_528_CLR_PFD0_STABLE_SHIFT (6U) +#define CCM_ANALOG_PFD_528_CLR_PFD0_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_CLR_PFD0_STABLE_SHIFT)) & CCM_ANALOG_PFD_528_CLR_PFD0_STABLE_MASK) +#define CCM_ANALOG_PFD_528_CLR_PFD0_CLKGATE_MASK (0x80U) +#define CCM_ANALOG_PFD_528_CLR_PFD0_CLKGATE_SHIFT (7U) +#define CCM_ANALOG_PFD_528_CLR_PFD0_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_CLR_PFD0_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_528_CLR_PFD0_CLKGATE_MASK) +#define CCM_ANALOG_PFD_528_CLR_PFD1_FRAC_MASK (0x3F00U) +#define CCM_ANALOG_PFD_528_CLR_PFD1_FRAC_SHIFT (8U) +#define CCM_ANALOG_PFD_528_CLR_PFD1_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_CLR_PFD1_FRAC_SHIFT)) & CCM_ANALOG_PFD_528_CLR_PFD1_FRAC_MASK) +#define CCM_ANALOG_PFD_528_CLR_PFD1_STABLE_MASK (0x4000U) +#define CCM_ANALOG_PFD_528_CLR_PFD1_STABLE_SHIFT (14U) +#define CCM_ANALOG_PFD_528_CLR_PFD1_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_CLR_PFD1_STABLE_SHIFT)) & CCM_ANALOG_PFD_528_CLR_PFD1_STABLE_MASK) +#define CCM_ANALOG_PFD_528_CLR_PFD1_CLKGATE_MASK (0x8000U) +#define CCM_ANALOG_PFD_528_CLR_PFD1_CLKGATE_SHIFT (15U) +#define CCM_ANALOG_PFD_528_CLR_PFD1_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_CLR_PFD1_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_528_CLR_PFD1_CLKGATE_MASK) +#define CCM_ANALOG_PFD_528_CLR_PFD2_FRAC_MASK (0x3F0000U) +#define CCM_ANALOG_PFD_528_CLR_PFD2_FRAC_SHIFT (16U) +#define CCM_ANALOG_PFD_528_CLR_PFD2_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_CLR_PFD2_FRAC_SHIFT)) & CCM_ANALOG_PFD_528_CLR_PFD2_FRAC_MASK) +#define CCM_ANALOG_PFD_528_CLR_PFD2_STABLE_MASK (0x400000U) +#define CCM_ANALOG_PFD_528_CLR_PFD2_STABLE_SHIFT (22U) +#define CCM_ANALOG_PFD_528_CLR_PFD2_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_CLR_PFD2_STABLE_SHIFT)) & CCM_ANALOG_PFD_528_CLR_PFD2_STABLE_MASK) +#define CCM_ANALOG_PFD_528_CLR_PFD2_CLKGATE_MASK (0x800000U) +#define CCM_ANALOG_PFD_528_CLR_PFD2_CLKGATE_SHIFT (23U) +#define CCM_ANALOG_PFD_528_CLR_PFD2_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_CLR_PFD2_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_528_CLR_PFD2_CLKGATE_MASK) +#define CCM_ANALOG_PFD_528_CLR_PFD3_FRAC_MASK (0x3F000000U) +#define CCM_ANALOG_PFD_528_CLR_PFD3_FRAC_SHIFT (24U) +#define CCM_ANALOG_PFD_528_CLR_PFD3_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_CLR_PFD3_FRAC_SHIFT)) & CCM_ANALOG_PFD_528_CLR_PFD3_FRAC_MASK) +#define CCM_ANALOG_PFD_528_CLR_PFD3_STABLE_MASK (0x40000000U) +#define CCM_ANALOG_PFD_528_CLR_PFD3_STABLE_SHIFT (30U) +#define CCM_ANALOG_PFD_528_CLR_PFD3_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_CLR_PFD3_STABLE_SHIFT)) & CCM_ANALOG_PFD_528_CLR_PFD3_STABLE_MASK) +#define CCM_ANALOG_PFD_528_CLR_PFD3_CLKGATE_MASK (0x80000000U) +#define CCM_ANALOG_PFD_528_CLR_PFD3_CLKGATE_SHIFT (31U) +#define CCM_ANALOG_PFD_528_CLR_PFD3_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_CLR_PFD3_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_528_CLR_PFD3_CLKGATE_MASK) +/*! @} */ + +/*! @name PFD_528_TOG - 528MHz Clock (PLL2) Phase Fractional Divider Control Register */ +/*! @{ */ +#define CCM_ANALOG_PFD_528_TOG_PFD0_FRAC_MASK (0x3FU) +#define CCM_ANALOG_PFD_528_TOG_PFD0_FRAC_SHIFT (0U) +#define CCM_ANALOG_PFD_528_TOG_PFD0_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_TOG_PFD0_FRAC_SHIFT)) & CCM_ANALOG_PFD_528_TOG_PFD0_FRAC_MASK) +#define CCM_ANALOG_PFD_528_TOG_PFD0_STABLE_MASK (0x40U) +#define CCM_ANALOG_PFD_528_TOG_PFD0_STABLE_SHIFT (6U) +#define CCM_ANALOG_PFD_528_TOG_PFD0_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_TOG_PFD0_STABLE_SHIFT)) & CCM_ANALOG_PFD_528_TOG_PFD0_STABLE_MASK) +#define CCM_ANALOG_PFD_528_TOG_PFD0_CLKGATE_MASK (0x80U) +#define CCM_ANALOG_PFD_528_TOG_PFD0_CLKGATE_SHIFT (7U) +#define CCM_ANALOG_PFD_528_TOG_PFD0_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_TOG_PFD0_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_528_TOG_PFD0_CLKGATE_MASK) +#define CCM_ANALOG_PFD_528_TOG_PFD1_FRAC_MASK (0x3F00U) +#define CCM_ANALOG_PFD_528_TOG_PFD1_FRAC_SHIFT (8U) +#define CCM_ANALOG_PFD_528_TOG_PFD1_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_TOG_PFD1_FRAC_SHIFT)) & CCM_ANALOG_PFD_528_TOG_PFD1_FRAC_MASK) +#define CCM_ANALOG_PFD_528_TOG_PFD1_STABLE_MASK (0x4000U) +#define CCM_ANALOG_PFD_528_TOG_PFD1_STABLE_SHIFT (14U) +#define CCM_ANALOG_PFD_528_TOG_PFD1_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_TOG_PFD1_STABLE_SHIFT)) & CCM_ANALOG_PFD_528_TOG_PFD1_STABLE_MASK) +#define CCM_ANALOG_PFD_528_TOG_PFD1_CLKGATE_MASK (0x8000U) +#define CCM_ANALOG_PFD_528_TOG_PFD1_CLKGATE_SHIFT (15U) +#define CCM_ANALOG_PFD_528_TOG_PFD1_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_TOG_PFD1_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_528_TOG_PFD1_CLKGATE_MASK) +#define CCM_ANALOG_PFD_528_TOG_PFD2_FRAC_MASK (0x3F0000U) +#define CCM_ANALOG_PFD_528_TOG_PFD2_FRAC_SHIFT (16U) +#define CCM_ANALOG_PFD_528_TOG_PFD2_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_TOG_PFD2_FRAC_SHIFT)) & CCM_ANALOG_PFD_528_TOG_PFD2_FRAC_MASK) +#define CCM_ANALOG_PFD_528_TOG_PFD2_STABLE_MASK (0x400000U) +#define CCM_ANALOG_PFD_528_TOG_PFD2_STABLE_SHIFT (22U) +#define CCM_ANALOG_PFD_528_TOG_PFD2_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_TOG_PFD2_STABLE_SHIFT)) & CCM_ANALOG_PFD_528_TOG_PFD2_STABLE_MASK) +#define CCM_ANALOG_PFD_528_TOG_PFD2_CLKGATE_MASK (0x800000U) +#define CCM_ANALOG_PFD_528_TOG_PFD2_CLKGATE_SHIFT (23U) +#define CCM_ANALOG_PFD_528_TOG_PFD2_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_TOG_PFD2_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_528_TOG_PFD2_CLKGATE_MASK) +#define CCM_ANALOG_PFD_528_TOG_PFD3_FRAC_MASK (0x3F000000U) +#define CCM_ANALOG_PFD_528_TOG_PFD3_FRAC_SHIFT (24U) +#define CCM_ANALOG_PFD_528_TOG_PFD3_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_TOG_PFD3_FRAC_SHIFT)) & CCM_ANALOG_PFD_528_TOG_PFD3_FRAC_MASK) +#define CCM_ANALOG_PFD_528_TOG_PFD3_STABLE_MASK (0x40000000U) +#define CCM_ANALOG_PFD_528_TOG_PFD3_STABLE_SHIFT (30U) +#define CCM_ANALOG_PFD_528_TOG_PFD3_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_TOG_PFD3_STABLE_SHIFT)) & CCM_ANALOG_PFD_528_TOG_PFD3_STABLE_MASK) +#define CCM_ANALOG_PFD_528_TOG_PFD3_CLKGATE_MASK (0x80000000U) +#define CCM_ANALOG_PFD_528_TOG_PFD3_CLKGATE_SHIFT (31U) +#define CCM_ANALOG_PFD_528_TOG_PFD3_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_TOG_PFD3_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_528_TOG_PFD3_CLKGATE_MASK) +/*! @} */ + +/*! @name MISC0 - Miscellaneous Register 0 */ +/*! @{ */ +#define CCM_ANALOG_MISC0_REFTOP_PWD_MASK (0x1U) +#define CCM_ANALOG_MISC0_REFTOP_PWD_SHIFT (0U) +#define CCM_ANALOG_MISC0_REFTOP_PWD(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_REFTOP_PWD_SHIFT)) & CCM_ANALOG_MISC0_REFTOP_PWD_MASK) +#define CCM_ANALOG_MISC0_REFTOP_SELFBIASOFF_MASK (0x8U) +#define CCM_ANALOG_MISC0_REFTOP_SELFBIASOFF_SHIFT (3U) +/*! REFTOP_SELFBIASOFF + * 0b0..Uses coarse bias currents for startup + * 0b1..Uses bandgap-based bias currents for best performance. + */ +#define CCM_ANALOG_MISC0_REFTOP_SELFBIASOFF(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_REFTOP_SELFBIASOFF_SHIFT)) & CCM_ANALOG_MISC0_REFTOP_SELFBIASOFF_MASK) +#define CCM_ANALOG_MISC0_REFTOP_VBGADJ_MASK (0x70U) +#define CCM_ANALOG_MISC0_REFTOP_VBGADJ_SHIFT (4U) +/*! REFTOP_VBGADJ + * 0b000..Nominal VBG + * 0b001..VBG+0.78% + * 0b010..VBG+1.56% + * 0b011..VBG+2.34% + * 0b100..VBG-0.78% + * 0b101..VBG-1.56% + * 0b110..VBG-2.34% + * 0b111..VBG-3.12% + */ +#define CCM_ANALOG_MISC0_REFTOP_VBGADJ(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_REFTOP_VBGADJ_SHIFT)) & CCM_ANALOG_MISC0_REFTOP_VBGADJ_MASK) +#define CCM_ANALOG_MISC0_REFTOP_VBGUP_MASK (0x80U) +#define CCM_ANALOG_MISC0_REFTOP_VBGUP_SHIFT (7U) +#define CCM_ANALOG_MISC0_REFTOP_VBGUP(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_REFTOP_VBGUP_SHIFT)) & CCM_ANALOG_MISC0_REFTOP_VBGUP_MASK) +#define CCM_ANALOG_MISC0_STOP_MODE_CONFIG_MASK (0xC00U) +#define CCM_ANALOG_MISC0_STOP_MODE_CONFIG_SHIFT (10U) +/*! STOP_MODE_CONFIG + * 0b00..All analog except rtc powered down on stop mode assertion. XtalOsc=on, RCOsc=off; + * 0b01..Certain analog functions such as certain regulators left up. XtalOsc=on, RCOsc=off; + * 0b10..XtalOsc=off, RCOsc=on, Old BG=on, New BG=off. + * 0b11..XtalOsc=off, RCOsc=on, Old BG=off, New BG=on. + */ +#define CCM_ANALOG_MISC0_STOP_MODE_CONFIG(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_STOP_MODE_CONFIG_SHIFT)) & CCM_ANALOG_MISC0_STOP_MODE_CONFIG_MASK) +#define CCM_ANALOG_MISC0_DISCON_HIGH_SNVS_MASK (0x1000U) +#define CCM_ANALOG_MISC0_DISCON_HIGH_SNVS_SHIFT (12U) +/*! DISCON_HIGH_SNVS + * 0b0..Turn on the switch + * 0b1..Turn off the switch + */ +#define CCM_ANALOG_MISC0_DISCON_HIGH_SNVS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_DISCON_HIGH_SNVS_SHIFT)) & CCM_ANALOG_MISC0_DISCON_HIGH_SNVS_MASK) +#define CCM_ANALOG_MISC0_OSC_I_MASK (0x6000U) +#define CCM_ANALOG_MISC0_OSC_I_SHIFT (13U) +/*! OSC_I + * 0b00..Nominal + * 0b01..Decrease current by 12.5% + * 0b10..Decrease current by 25.0% + * 0b11..Decrease current by 37.5% + */ +#define CCM_ANALOG_MISC0_OSC_I(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_OSC_I_SHIFT)) & CCM_ANALOG_MISC0_OSC_I_MASK) +#define CCM_ANALOG_MISC0_OSC_XTALOK_MASK (0x8000U) +#define CCM_ANALOG_MISC0_OSC_XTALOK_SHIFT (15U) +#define CCM_ANALOG_MISC0_OSC_XTALOK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_OSC_XTALOK_SHIFT)) & CCM_ANALOG_MISC0_OSC_XTALOK_MASK) +#define CCM_ANALOG_MISC0_OSC_XTALOK_EN_MASK (0x10000U) +#define CCM_ANALOG_MISC0_OSC_XTALOK_EN_SHIFT (16U) +#define CCM_ANALOG_MISC0_OSC_XTALOK_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_OSC_XTALOK_EN_SHIFT)) & CCM_ANALOG_MISC0_OSC_XTALOK_EN_MASK) +#define CCM_ANALOG_MISC0_CLKGATE_CTRL_MASK (0x2000000U) +#define CCM_ANALOG_MISC0_CLKGATE_CTRL_SHIFT (25U) +/*! CLKGATE_CTRL + * 0b0..Allow the logic to automatically gate the clock when the XTAL is powered down. + * 0b1..Prevent the logic from ever gating off the clock. + */ +#define CCM_ANALOG_MISC0_CLKGATE_CTRL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_CLKGATE_CTRL_SHIFT)) & CCM_ANALOG_MISC0_CLKGATE_CTRL_MASK) +#define CCM_ANALOG_MISC0_CLKGATE_DELAY_MASK (0x1C000000U) +#define CCM_ANALOG_MISC0_CLKGATE_DELAY_SHIFT (26U) +/*! CLKGATE_DELAY + * 0b000..0.5ms + * 0b001..1.0ms + * 0b010..2.0ms + * 0b011..3.0ms + * 0b100..4.0ms + * 0b101..5.0ms + * 0b110..6.0ms + * 0b111..7.0ms + */ +#define CCM_ANALOG_MISC0_CLKGATE_DELAY(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_CLKGATE_DELAY_SHIFT)) & CCM_ANALOG_MISC0_CLKGATE_DELAY_MASK) +#define CCM_ANALOG_MISC0_RTC_XTAL_SOURCE_MASK (0x20000000U) +#define CCM_ANALOG_MISC0_RTC_XTAL_SOURCE_SHIFT (29U) +/*! RTC_XTAL_SOURCE + * 0b0..Internal ring oscillator + * 0b1..RTC_XTAL + */ +#define CCM_ANALOG_MISC0_RTC_XTAL_SOURCE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_RTC_XTAL_SOURCE_SHIFT)) & CCM_ANALOG_MISC0_RTC_XTAL_SOURCE_MASK) +#define CCM_ANALOG_MISC0_XTAL_24M_PWD_MASK (0x40000000U) +#define CCM_ANALOG_MISC0_XTAL_24M_PWD_SHIFT (30U) +#define CCM_ANALOG_MISC0_XTAL_24M_PWD(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_XTAL_24M_PWD_SHIFT)) & CCM_ANALOG_MISC0_XTAL_24M_PWD_MASK) +/*! @} */ + +/*! @name MISC0_SET - Miscellaneous Register 0 */ +/*! @{ */ +#define CCM_ANALOG_MISC0_SET_REFTOP_PWD_MASK (0x1U) +#define CCM_ANALOG_MISC0_SET_REFTOP_PWD_SHIFT (0U) +#define CCM_ANALOG_MISC0_SET_REFTOP_PWD(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_SET_REFTOP_PWD_SHIFT)) & CCM_ANALOG_MISC0_SET_REFTOP_PWD_MASK) +#define CCM_ANALOG_MISC0_SET_REFTOP_SELFBIASOFF_MASK (0x8U) +#define CCM_ANALOG_MISC0_SET_REFTOP_SELFBIASOFF_SHIFT (3U) +/*! REFTOP_SELFBIASOFF + * 0b0..Uses coarse bias currents for startup + * 0b1..Uses bandgap-based bias currents for best performance. + */ +#define CCM_ANALOG_MISC0_SET_REFTOP_SELFBIASOFF(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_SET_REFTOP_SELFBIASOFF_SHIFT)) & CCM_ANALOG_MISC0_SET_REFTOP_SELFBIASOFF_MASK) +#define CCM_ANALOG_MISC0_SET_REFTOP_VBGADJ_MASK (0x70U) +#define CCM_ANALOG_MISC0_SET_REFTOP_VBGADJ_SHIFT (4U) +/*! REFTOP_VBGADJ + * 0b000..Nominal VBG + * 0b001..VBG+0.78% + * 0b010..VBG+1.56% + * 0b011..VBG+2.34% + * 0b100..VBG-0.78% + * 0b101..VBG-1.56% + * 0b110..VBG-2.34% + * 0b111..VBG-3.12% + */ +#define CCM_ANALOG_MISC0_SET_REFTOP_VBGADJ(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_SET_REFTOP_VBGADJ_SHIFT)) & CCM_ANALOG_MISC0_SET_REFTOP_VBGADJ_MASK) +#define CCM_ANALOG_MISC0_SET_REFTOP_VBGUP_MASK (0x80U) +#define CCM_ANALOG_MISC0_SET_REFTOP_VBGUP_SHIFT (7U) +#define CCM_ANALOG_MISC0_SET_REFTOP_VBGUP(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_SET_REFTOP_VBGUP_SHIFT)) & CCM_ANALOG_MISC0_SET_REFTOP_VBGUP_MASK) +#define CCM_ANALOG_MISC0_SET_STOP_MODE_CONFIG_MASK (0xC00U) +#define CCM_ANALOG_MISC0_SET_STOP_MODE_CONFIG_SHIFT (10U) +/*! STOP_MODE_CONFIG + * 0b00..All analog except rtc powered down on stop mode assertion. XtalOsc=on, RCOsc=off; + * 0b01..Certain analog functions such as certain regulators left up. XtalOsc=on, RCOsc=off; + * 0b10..XtalOsc=off, RCOsc=on, Old BG=on, New BG=off. + * 0b11..XtalOsc=off, RCOsc=on, Old BG=off, New BG=on. + */ +#define CCM_ANALOG_MISC0_SET_STOP_MODE_CONFIG(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_SET_STOP_MODE_CONFIG_SHIFT)) & CCM_ANALOG_MISC0_SET_STOP_MODE_CONFIG_MASK) +#define CCM_ANALOG_MISC0_SET_DISCON_HIGH_SNVS_MASK (0x1000U) +#define CCM_ANALOG_MISC0_SET_DISCON_HIGH_SNVS_SHIFT (12U) +/*! DISCON_HIGH_SNVS + * 0b0..Turn on the switch + * 0b1..Turn off the switch + */ +#define CCM_ANALOG_MISC0_SET_DISCON_HIGH_SNVS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_SET_DISCON_HIGH_SNVS_SHIFT)) & CCM_ANALOG_MISC0_SET_DISCON_HIGH_SNVS_MASK) +#define CCM_ANALOG_MISC0_SET_OSC_I_MASK (0x6000U) +#define CCM_ANALOG_MISC0_SET_OSC_I_SHIFT (13U) +/*! OSC_I + * 0b00..Nominal + * 0b01..Decrease current by 12.5% + * 0b10..Decrease current by 25.0% + * 0b11..Decrease current by 37.5% + */ +#define CCM_ANALOG_MISC0_SET_OSC_I(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_SET_OSC_I_SHIFT)) & CCM_ANALOG_MISC0_SET_OSC_I_MASK) +#define CCM_ANALOG_MISC0_SET_OSC_XTALOK_MASK (0x8000U) +#define CCM_ANALOG_MISC0_SET_OSC_XTALOK_SHIFT (15U) +#define CCM_ANALOG_MISC0_SET_OSC_XTALOK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_SET_OSC_XTALOK_SHIFT)) & CCM_ANALOG_MISC0_SET_OSC_XTALOK_MASK) +#define CCM_ANALOG_MISC0_SET_OSC_XTALOK_EN_MASK (0x10000U) +#define CCM_ANALOG_MISC0_SET_OSC_XTALOK_EN_SHIFT (16U) +#define CCM_ANALOG_MISC0_SET_OSC_XTALOK_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_SET_OSC_XTALOK_EN_SHIFT)) & CCM_ANALOG_MISC0_SET_OSC_XTALOK_EN_MASK) +#define CCM_ANALOG_MISC0_SET_CLKGATE_CTRL_MASK (0x2000000U) +#define CCM_ANALOG_MISC0_SET_CLKGATE_CTRL_SHIFT (25U) +/*! CLKGATE_CTRL + * 0b0..Allow the logic to automatically gate the clock when the XTAL is powered down. + * 0b1..Prevent the logic from ever gating off the clock. + */ +#define CCM_ANALOG_MISC0_SET_CLKGATE_CTRL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_SET_CLKGATE_CTRL_SHIFT)) & CCM_ANALOG_MISC0_SET_CLKGATE_CTRL_MASK) +#define CCM_ANALOG_MISC0_SET_CLKGATE_DELAY_MASK (0x1C000000U) +#define CCM_ANALOG_MISC0_SET_CLKGATE_DELAY_SHIFT (26U) +/*! CLKGATE_DELAY + * 0b000..0.5ms + * 0b001..1.0ms + * 0b010..2.0ms + * 0b011..3.0ms + * 0b100..4.0ms + * 0b101..5.0ms + * 0b110..6.0ms + * 0b111..7.0ms + */ +#define CCM_ANALOG_MISC0_SET_CLKGATE_DELAY(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_SET_CLKGATE_DELAY_SHIFT)) & CCM_ANALOG_MISC0_SET_CLKGATE_DELAY_MASK) +#define CCM_ANALOG_MISC0_SET_RTC_XTAL_SOURCE_MASK (0x20000000U) +#define CCM_ANALOG_MISC0_SET_RTC_XTAL_SOURCE_SHIFT (29U) +/*! RTC_XTAL_SOURCE + * 0b0..Internal ring oscillator + * 0b1..RTC_XTAL + */ +#define CCM_ANALOG_MISC0_SET_RTC_XTAL_SOURCE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_SET_RTC_XTAL_SOURCE_SHIFT)) & CCM_ANALOG_MISC0_SET_RTC_XTAL_SOURCE_MASK) +#define CCM_ANALOG_MISC0_SET_XTAL_24M_PWD_MASK (0x40000000U) +#define CCM_ANALOG_MISC0_SET_XTAL_24M_PWD_SHIFT (30U) +#define CCM_ANALOG_MISC0_SET_XTAL_24M_PWD(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_SET_XTAL_24M_PWD_SHIFT)) & CCM_ANALOG_MISC0_SET_XTAL_24M_PWD_MASK) +/*! @} */ + +/*! @name MISC0_CLR - Miscellaneous Register 0 */ +/*! @{ */ +#define CCM_ANALOG_MISC0_CLR_REFTOP_PWD_MASK (0x1U) +#define CCM_ANALOG_MISC0_CLR_REFTOP_PWD_SHIFT (0U) +#define CCM_ANALOG_MISC0_CLR_REFTOP_PWD(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_CLR_REFTOP_PWD_SHIFT)) & CCM_ANALOG_MISC0_CLR_REFTOP_PWD_MASK) +#define CCM_ANALOG_MISC0_CLR_REFTOP_SELFBIASOFF_MASK (0x8U) +#define CCM_ANALOG_MISC0_CLR_REFTOP_SELFBIASOFF_SHIFT (3U) +/*! REFTOP_SELFBIASOFF + * 0b0..Uses coarse bias currents for startup + * 0b1..Uses bandgap-based bias currents for best performance. + */ +#define CCM_ANALOG_MISC0_CLR_REFTOP_SELFBIASOFF(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_CLR_REFTOP_SELFBIASOFF_SHIFT)) & CCM_ANALOG_MISC0_CLR_REFTOP_SELFBIASOFF_MASK) +#define CCM_ANALOG_MISC0_CLR_REFTOP_VBGADJ_MASK (0x70U) +#define CCM_ANALOG_MISC0_CLR_REFTOP_VBGADJ_SHIFT (4U) +/*! REFTOP_VBGADJ + * 0b000..Nominal VBG + * 0b001..VBG+0.78% + * 0b010..VBG+1.56% + * 0b011..VBG+2.34% + * 0b100..VBG-0.78% + * 0b101..VBG-1.56% + * 0b110..VBG-2.34% + * 0b111..VBG-3.12% + */ +#define CCM_ANALOG_MISC0_CLR_REFTOP_VBGADJ(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_CLR_REFTOP_VBGADJ_SHIFT)) & CCM_ANALOG_MISC0_CLR_REFTOP_VBGADJ_MASK) +#define CCM_ANALOG_MISC0_CLR_REFTOP_VBGUP_MASK (0x80U) +#define CCM_ANALOG_MISC0_CLR_REFTOP_VBGUP_SHIFT (7U) +#define CCM_ANALOG_MISC0_CLR_REFTOP_VBGUP(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_CLR_REFTOP_VBGUP_SHIFT)) & CCM_ANALOG_MISC0_CLR_REFTOP_VBGUP_MASK) +#define CCM_ANALOG_MISC0_CLR_STOP_MODE_CONFIG_MASK (0xC00U) +#define CCM_ANALOG_MISC0_CLR_STOP_MODE_CONFIG_SHIFT (10U) +/*! STOP_MODE_CONFIG + * 0b00..All analog except rtc powered down on stop mode assertion. XtalOsc=on, RCOsc=off; + * 0b01..Certain analog functions such as certain regulators left up. XtalOsc=on, RCOsc=off; + * 0b10..XtalOsc=off, RCOsc=on, Old BG=on, New BG=off. + * 0b11..XtalOsc=off, RCOsc=on, Old BG=off, New BG=on. + */ +#define CCM_ANALOG_MISC0_CLR_STOP_MODE_CONFIG(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_CLR_STOP_MODE_CONFIG_SHIFT)) & CCM_ANALOG_MISC0_CLR_STOP_MODE_CONFIG_MASK) +#define CCM_ANALOG_MISC0_CLR_DISCON_HIGH_SNVS_MASK (0x1000U) +#define CCM_ANALOG_MISC0_CLR_DISCON_HIGH_SNVS_SHIFT (12U) +/*! DISCON_HIGH_SNVS + * 0b0..Turn on the switch + * 0b1..Turn off the switch + */ +#define CCM_ANALOG_MISC0_CLR_DISCON_HIGH_SNVS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_CLR_DISCON_HIGH_SNVS_SHIFT)) & CCM_ANALOG_MISC0_CLR_DISCON_HIGH_SNVS_MASK) +#define CCM_ANALOG_MISC0_CLR_OSC_I_MASK (0x6000U) +#define CCM_ANALOG_MISC0_CLR_OSC_I_SHIFT (13U) +/*! OSC_I + * 0b00..Nominal + * 0b01..Decrease current by 12.5% + * 0b10..Decrease current by 25.0% + * 0b11..Decrease current by 37.5% + */ +#define CCM_ANALOG_MISC0_CLR_OSC_I(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_CLR_OSC_I_SHIFT)) & CCM_ANALOG_MISC0_CLR_OSC_I_MASK) +#define CCM_ANALOG_MISC0_CLR_OSC_XTALOK_MASK (0x8000U) +#define CCM_ANALOG_MISC0_CLR_OSC_XTALOK_SHIFT (15U) +#define CCM_ANALOG_MISC0_CLR_OSC_XTALOK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_CLR_OSC_XTALOK_SHIFT)) & CCM_ANALOG_MISC0_CLR_OSC_XTALOK_MASK) +#define CCM_ANALOG_MISC0_CLR_OSC_XTALOK_EN_MASK (0x10000U) +#define CCM_ANALOG_MISC0_CLR_OSC_XTALOK_EN_SHIFT (16U) +#define CCM_ANALOG_MISC0_CLR_OSC_XTALOK_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_CLR_OSC_XTALOK_EN_SHIFT)) & CCM_ANALOG_MISC0_CLR_OSC_XTALOK_EN_MASK) +#define CCM_ANALOG_MISC0_CLR_CLKGATE_CTRL_MASK (0x2000000U) +#define CCM_ANALOG_MISC0_CLR_CLKGATE_CTRL_SHIFT (25U) +/*! CLKGATE_CTRL + * 0b0..Allow the logic to automatically gate the clock when the XTAL is powered down. + * 0b1..Prevent the logic from ever gating off the clock. + */ +#define CCM_ANALOG_MISC0_CLR_CLKGATE_CTRL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_CLR_CLKGATE_CTRL_SHIFT)) & CCM_ANALOG_MISC0_CLR_CLKGATE_CTRL_MASK) +#define CCM_ANALOG_MISC0_CLR_CLKGATE_DELAY_MASK (0x1C000000U) +#define CCM_ANALOG_MISC0_CLR_CLKGATE_DELAY_SHIFT (26U) +/*! CLKGATE_DELAY + * 0b000..0.5ms + * 0b001..1.0ms + * 0b010..2.0ms + * 0b011..3.0ms + * 0b100..4.0ms + * 0b101..5.0ms + * 0b110..6.0ms + * 0b111..7.0ms + */ +#define CCM_ANALOG_MISC0_CLR_CLKGATE_DELAY(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_CLR_CLKGATE_DELAY_SHIFT)) & CCM_ANALOG_MISC0_CLR_CLKGATE_DELAY_MASK) +#define CCM_ANALOG_MISC0_CLR_RTC_XTAL_SOURCE_MASK (0x20000000U) +#define CCM_ANALOG_MISC0_CLR_RTC_XTAL_SOURCE_SHIFT (29U) +/*! RTC_XTAL_SOURCE + * 0b0..Internal ring oscillator + * 0b1..RTC_XTAL + */ +#define CCM_ANALOG_MISC0_CLR_RTC_XTAL_SOURCE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_CLR_RTC_XTAL_SOURCE_SHIFT)) & CCM_ANALOG_MISC0_CLR_RTC_XTAL_SOURCE_MASK) +#define CCM_ANALOG_MISC0_CLR_XTAL_24M_PWD_MASK (0x40000000U) +#define CCM_ANALOG_MISC0_CLR_XTAL_24M_PWD_SHIFT (30U) +#define CCM_ANALOG_MISC0_CLR_XTAL_24M_PWD(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_CLR_XTAL_24M_PWD_SHIFT)) & CCM_ANALOG_MISC0_CLR_XTAL_24M_PWD_MASK) +/*! @} */ + +/*! @name MISC0_TOG - Miscellaneous Register 0 */ +/*! @{ */ +#define CCM_ANALOG_MISC0_TOG_REFTOP_PWD_MASK (0x1U) +#define CCM_ANALOG_MISC0_TOG_REFTOP_PWD_SHIFT (0U) +#define CCM_ANALOG_MISC0_TOG_REFTOP_PWD(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_TOG_REFTOP_PWD_SHIFT)) & CCM_ANALOG_MISC0_TOG_REFTOP_PWD_MASK) +#define CCM_ANALOG_MISC0_TOG_REFTOP_SELFBIASOFF_MASK (0x8U) +#define CCM_ANALOG_MISC0_TOG_REFTOP_SELFBIASOFF_SHIFT (3U) +/*! REFTOP_SELFBIASOFF + * 0b0..Uses coarse bias currents for startup + * 0b1..Uses bandgap-based bias currents for best performance. + */ +#define CCM_ANALOG_MISC0_TOG_REFTOP_SELFBIASOFF(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_TOG_REFTOP_SELFBIASOFF_SHIFT)) & CCM_ANALOG_MISC0_TOG_REFTOP_SELFBIASOFF_MASK) +#define CCM_ANALOG_MISC0_TOG_REFTOP_VBGADJ_MASK (0x70U) +#define CCM_ANALOG_MISC0_TOG_REFTOP_VBGADJ_SHIFT (4U) +/*! REFTOP_VBGADJ + * 0b000..Nominal VBG + * 0b001..VBG+0.78% + * 0b010..VBG+1.56% + * 0b011..VBG+2.34% + * 0b100..VBG-0.78% + * 0b101..VBG-1.56% + * 0b110..VBG-2.34% + * 0b111..VBG-3.12% + */ +#define CCM_ANALOG_MISC0_TOG_REFTOP_VBGADJ(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_TOG_REFTOP_VBGADJ_SHIFT)) & CCM_ANALOG_MISC0_TOG_REFTOP_VBGADJ_MASK) +#define CCM_ANALOG_MISC0_TOG_REFTOP_VBGUP_MASK (0x80U) +#define CCM_ANALOG_MISC0_TOG_REFTOP_VBGUP_SHIFT (7U) +#define CCM_ANALOG_MISC0_TOG_REFTOP_VBGUP(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_TOG_REFTOP_VBGUP_SHIFT)) & CCM_ANALOG_MISC0_TOG_REFTOP_VBGUP_MASK) +#define CCM_ANALOG_MISC0_TOG_STOP_MODE_CONFIG_MASK (0xC00U) +#define CCM_ANALOG_MISC0_TOG_STOP_MODE_CONFIG_SHIFT (10U) +/*! STOP_MODE_CONFIG + * 0b00..All analog except rtc powered down on stop mode assertion. XtalOsc=on, RCOsc=off; + * 0b01..Certain analog functions such as certain regulators left up. XtalOsc=on, RCOsc=off; + * 0b10..XtalOsc=off, RCOsc=on, Old BG=on, New BG=off. + * 0b11..XtalOsc=off, RCOsc=on, Old BG=off, New BG=on. + */ +#define CCM_ANALOG_MISC0_TOG_STOP_MODE_CONFIG(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_TOG_STOP_MODE_CONFIG_SHIFT)) & CCM_ANALOG_MISC0_TOG_STOP_MODE_CONFIG_MASK) +#define CCM_ANALOG_MISC0_TOG_DISCON_HIGH_SNVS_MASK (0x1000U) +#define CCM_ANALOG_MISC0_TOG_DISCON_HIGH_SNVS_SHIFT (12U) +/*! DISCON_HIGH_SNVS + * 0b0..Turn on the switch + * 0b1..Turn off the switch + */ +#define CCM_ANALOG_MISC0_TOG_DISCON_HIGH_SNVS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_TOG_DISCON_HIGH_SNVS_SHIFT)) & CCM_ANALOG_MISC0_TOG_DISCON_HIGH_SNVS_MASK) +#define CCM_ANALOG_MISC0_TOG_OSC_I_MASK (0x6000U) +#define CCM_ANALOG_MISC0_TOG_OSC_I_SHIFT (13U) +/*! OSC_I + * 0b00..Nominal + * 0b01..Decrease current by 12.5% + * 0b10..Decrease current by 25.0% + * 0b11..Decrease current by 37.5% + */ +#define CCM_ANALOG_MISC0_TOG_OSC_I(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_TOG_OSC_I_SHIFT)) & CCM_ANALOG_MISC0_TOG_OSC_I_MASK) +#define CCM_ANALOG_MISC0_TOG_OSC_XTALOK_MASK (0x8000U) +#define CCM_ANALOG_MISC0_TOG_OSC_XTALOK_SHIFT (15U) +#define CCM_ANALOG_MISC0_TOG_OSC_XTALOK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_TOG_OSC_XTALOK_SHIFT)) & CCM_ANALOG_MISC0_TOG_OSC_XTALOK_MASK) +#define CCM_ANALOG_MISC0_TOG_OSC_XTALOK_EN_MASK (0x10000U) +#define CCM_ANALOG_MISC0_TOG_OSC_XTALOK_EN_SHIFT (16U) +#define CCM_ANALOG_MISC0_TOG_OSC_XTALOK_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_TOG_OSC_XTALOK_EN_SHIFT)) & CCM_ANALOG_MISC0_TOG_OSC_XTALOK_EN_MASK) +#define CCM_ANALOG_MISC0_TOG_CLKGATE_CTRL_MASK (0x2000000U) +#define CCM_ANALOG_MISC0_TOG_CLKGATE_CTRL_SHIFT (25U) +/*! CLKGATE_CTRL + * 0b0..Allow the logic to automatically gate the clock when the XTAL is powered down. + * 0b1..Prevent the logic from ever gating off the clock. + */ +#define CCM_ANALOG_MISC0_TOG_CLKGATE_CTRL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_TOG_CLKGATE_CTRL_SHIFT)) & CCM_ANALOG_MISC0_TOG_CLKGATE_CTRL_MASK) +#define CCM_ANALOG_MISC0_TOG_CLKGATE_DELAY_MASK (0x1C000000U) +#define CCM_ANALOG_MISC0_TOG_CLKGATE_DELAY_SHIFT (26U) +/*! CLKGATE_DELAY + * 0b000..0.5ms + * 0b001..1.0ms + * 0b010..2.0ms + * 0b011..3.0ms + * 0b100..4.0ms + * 0b101..5.0ms + * 0b110..6.0ms + * 0b111..7.0ms + */ +#define CCM_ANALOG_MISC0_TOG_CLKGATE_DELAY(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_TOG_CLKGATE_DELAY_SHIFT)) & CCM_ANALOG_MISC0_TOG_CLKGATE_DELAY_MASK) +#define CCM_ANALOG_MISC0_TOG_RTC_XTAL_SOURCE_MASK (0x20000000U) +#define CCM_ANALOG_MISC0_TOG_RTC_XTAL_SOURCE_SHIFT (29U) +/*! RTC_XTAL_SOURCE + * 0b0..Internal ring oscillator + * 0b1..RTC_XTAL + */ +#define CCM_ANALOG_MISC0_TOG_RTC_XTAL_SOURCE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_TOG_RTC_XTAL_SOURCE_SHIFT)) & CCM_ANALOG_MISC0_TOG_RTC_XTAL_SOURCE_MASK) +#define CCM_ANALOG_MISC0_TOG_XTAL_24M_PWD_MASK (0x40000000U) +#define CCM_ANALOG_MISC0_TOG_XTAL_24M_PWD_SHIFT (30U) +#define CCM_ANALOG_MISC0_TOG_XTAL_24M_PWD(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_TOG_XTAL_24M_PWD_SHIFT)) & CCM_ANALOG_MISC0_TOG_XTAL_24M_PWD_MASK) +/*! @} */ + +/*! @name MISC1 - Miscellaneous Register 1 */ +/*! @{ */ +#define CCM_ANALOG_MISC1_LVDS1_CLK_SEL_MASK (0x1FU) +#define CCM_ANALOG_MISC1_LVDS1_CLK_SEL_SHIFT (0U) +/*! LVDS1_CLK_SEL + * 0b00000..Arm PLL + * 0b00001..System PLL + * 0b00010..ref_pfd4_clk == pll2_pfd0_clk + * 0b00011..ref_pfd5_clk == pll2_pfd1_clk + * 0b00100..ref_pfd6_clk == pll2_pfd2_clk + * 0b00101..ref_pfd7_clk == pll2_pfd3_clk + * 0b00110..Audio PLL + * 0b00111..Video PLL + * 0b01001..ethernet ref clock (ENET_PLL) + * 0b01100..USB1 PLL clock + * 0b01101..USB2 PLL clock + * 0b01110..ref_pfd0_clk == pll3_pfd0_clk + * 0b01111..ref_pfd1_clk == pll3_pfd1_clk + * 0b10000..ref_pfd2_clk == pll3_pfd2_clk + * 0b10001..ref_pfd3_clk == pll3_pfd3_clk + * 0b10010..xtal (24M) + */ +#define CCM_ANALOG_MISC1_LVDS1_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_LVDS1_CLK_SEL_SHIFT)) & CCM_ANALOG_MISC1_LVDS1_CLK_SEL_MASK) +#define CCM_ANALOG_MISC1_LVDSCLK1_OBEN_MASK (0x400U) +#define CCM_ANALOG_MISC1_LVDSCLK1_OBEN_SHIFT (10U) +#define CCM_ANALOG_MISC1_LVDSCLK1_OBEN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_LVDSCLK1_OBEN_SHIFT)) & CCM_ANALOG_MISC1_LVDSCLK1_OBEN_MASK) +#define CCM_ANALOG_MISC1_LVDSCLK1_IBEN_MASK (0x1000U) +#define CCM_ANALOG_MISC1_LVDSCLK1_IBEN_SHIFT (12U) +#define CCM_ANALOG_MISC1_LVDSCLK1_IBEN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_LVDSCLK1_IBEN_SHIFT)) & CCM_ANALOG_MISC1_LVDSCLK1_IBEN_MASK) +#define CCM_ANALOG_MISC1_PFD_480_AUTOGATE_EN_MASK (0x10000U) +#define CCM_ANALOG_MISC1_PFD_480_AUTOGATE_EN_SHIFT (16U) +#define CCM_ANALOG_MISC1_PFD_480_AUTOGATE_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_PFD_480_AUTOGATE_EN_SHIFT)) & CCM_ANALOG_MISC1_PFD_480_AUTOGATE_EN_MASK) +#define CCM_ANALOG_MISC1_PFD_528_AUTOGATE_EN_MASK (0x20000U) +#define CCM_ANALOG_MISC1_PFD_528_AUTOGATE_EN_SHIFT (17U) +#define CCM_ANALOG_MISC1_PFD_528_AUTOGATE_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_PFD_528_AUTOGATE_EN_SHIFT)) & CCM_ANALOG_MISC1_PFD_528_AUTOGATE_EN_MASK) +#define CCM_ANALOG_MISC1_IRQ_TEMPPANIC_MASK (0x8000000U) +#define CCM_ANALOG_MISC1_IRQ_TEMPPANIC_SHIFT (27U) +#define CCM_ANALOG_MISC1_IRQ_TEMPPANIC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_IRQ_TEMPPANIC_SHIFT)) & CCM_ANALOG_MISC1_IRQ_TEMPPANIC_MASK) +#define CCM_ANALOG_MISC1_IRQ_TEMPLOW_MASK (0x10000000U) +#define CCM_ANALOG_MISC1_IRQ_TEMPLOW_SHIFT (28U) +#define CCM_ANALOG_MISC1_IRQ_TEMPLOW(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_IRQ_TEMPLOW_SHIFT)) & CCM_ANALOG_MISC1_IRQ_TEMPLOW_MASK) +#define CCM_ANALOG_MISC1_IRQ_TEMPHIGH_MASK (0x20000000U) +#define CCM_ANALOG_MISC1_IRQ_TEMPHIGH_SHIFT (29U) +#define CCM_ANALOG_MISC1_IRQ_TEMPHIGH(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_IRQ_TEMPHIGH_SHIFT)) & CCM_ANALOG_MISC1_IRQ_TEMPHIGH_MASK) +#define CCM_ANALOG_MISC1_IRQ_ANA_BO_MASK (0x40000000U) +#define CCM_ANALOG_MISC1_IRQ_ANA_BO_SHIFT (30U) +#define CCM_ANALOG_MISC1_IRQ_ANA_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_IRQ_ANA_BO_SHIFT)) & CCM_ANALOG_MISC1_IRQ_ANA_BO_MASK) +#define CCM_ANALOG_MISC1_IRQ_DIG_BO_MASK (0x80000000U) +#define CCM_ANALOG_MISC1_IRQ_DIG_BO_SHIFT (31U) +#define CCM_ANALOG_MISC1_IRQ_DIG_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_IRQ_DIG_BO_SHIFT)) & CCM_ANALOG_MISC1_IRQ_DIG_BO_MASK) +/*! @} */ + +/*! @name MISC1_SET - Miscellaneous Register 1 */ +/*! @{ */ +#define CCM_ANALOG_MISC1_SET_LVDS1_CLK_SEL_MASK (0x1FU) +#define CCM_ANALOG_MISC1_SET_LVDS1_CLK_SEL_SHIFT (0U) +/*! LVDS1_CLK_SEL + * 0b00000..Arm PLL + * 0b00001..System PLL + * 0b00010..ref_pfd4_clk == pll2_pfd0_clk + * 0b00011..ref_pfd5_clk == pll2_pfd1_clk + * 0b00100..ref_pfd6_clk == pll2_pfd2_clk + * 0b00101..ref_pfd7_clk == pll2_pfd3_clk + * 0b00110..Audio PLL + * 0b00111..Video PLL + * 0b01001..ethernet ref clock (ENET_PLL) + * 0b01100..USB1 PLL clock + * 0b01101..USB2 PLL clock + * 0b01110..ref_pfd0_clk == pll3_pfd0_clk + * 0b01111..ref_pfd1_clk == pll3_pfd1_clk + * 0b10000..ref_pfd2_clk == pll3_pfd2_clk + * 0b10001..ref_pfd3_clk == pll3_pfd3_clk + * 0b10010..xtal (24M) + */ +#define CCM_ANALOG_MISC1_SET_LVDS1_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_SET_LVDS1_CLK_SEL_SHIFT)) & CCM_ANALOG_MISC1_SET_LVDS1_CLK_SEL_MASK) +#define CCM_ANALOG_MISC1_SET_LVDSCLK1_OBEN_MASK (0x400U) +#define CCM_ANALOG_MISC1_SET_LVDSCLK1_OBEN_SHIFT (10U) +#define CCM_ANALOG_MISC1_SET_LVDSCLK1_OBEN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_SET_LVDSCLK1_OBEN_SHIFT)) & CCM_ANALOG_MISC1_SET_LVDSCLK1_OBEN_MASK) +#define CCM_ANALOG_MISC1_SET_LVDSCLK1_IBEN_MASK (0x1000U) +#define CCM_ANALOG_MISC1_SET_LVDSCLK1_IBEN_SHIFT (12U) +#define CCM_ANALOG_MISC1_SET_LVDSCLK1_IBEN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_SET_LVDSCLK1_IBEN_SHIFT)) & CCM_ANALOG_MISC1_SET_LVDSCLK1_IBEN_MASK) +#define CCM_ANALOG_MISC1_SET_PFD_480_AUTOGATE_EN_MASK (0x10000U) +#define CCM_ANALOG_MISC1_SET_PFD_480_AUTOGATE_EN_SHIFT (16U) +#define CCM_ANALOG_MISC1_SET_PFD_480_AUTOGATE_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_SET_PFD_480_AUTOGATE_EN_SHIFT)) & CCM_ANALOG_MISC1_SET_PFD_480_AUTOGATE_EN_MASK) +#define CCM_ANALOG_MISC1_SET_PFD_528_AUTOGATE_EN_MASK (0x20000U) +#define CCM_ANALOG_MISC1_SET_PFD_528_AUTOGATE_EN_SHIFT (17U) +#define CCM_ANALOG_MISC1_SET_PFD_528_AUTOGATE_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_SET_PFD_528_AUTOGATE_EN_SHIFT)) & CCM_ANALOG_MISC1_SET_PFD_528_AUTOGATE_EN_MASK) +#define CCM_ANALOG_MISC1_SET_IRQ_TEMPPANIC_MASK (0x8000000U) +#define CCM_ANALOG_MISC1_SET_IRQ_TEMPPANIC_SHIFT (27U) +#define CCM_ANALOG_MISC1_SET_IRQ_TEMPPANIC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_SET_IRQ_TEMPPANIC_SHIFT)) & CCM_ANALOG_MISC1_SET_IRQ_TEMPPANIC_MASK) +#define CCM_ANALOG_MISC1_SET_IRQ_TEMPLOW_MASK (0x10000000U) +#define CCM_ANALOG_MISC1_SET_IRQ_TEMPLOW_SHIFT (28U) +#define CCM_ANALOG_MISC1_SET_IRQ_TEMPLOW(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_SET_IRQ_TEMPLOW_SHIFT)) & CCM_ANALOG_MISC1_SET_IRQ_TEMPLOW_MASK) +#define CCM_ANALOG_MISC1_SET_IRQ_TEMPHIGH_MASK (0x20000000U) +#define CCM_ANALOG_MISC1_SET_IRQ_TEMPHIGH_SHIFT (29U) +#define CCM_ANALOG_MISC1_SET_IRQ_TEMPHIGH(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_SET_IRQ_TEMPHIGH_SHIFT)) & CCM_ANALOG_MISC1_SET_IRQ_TEMPHIGH_MASK) +#define CCM_ANALOG_MISC1_SET_IRQ_ANA_BO_MASK (0x40000000U) +#define CCM_ANALOG_MISC1_SET_IRQ_ANA_BO_SHIFT (30U) +#define CCM_ANALOG_MISC1_SET_IRQ_ANA_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_SET_IRQ_ANA_BO_SHIFT)) & CCM_ANALOG_MISC1_SET_IRQ_ANA_BO_MASK) +#define CCM_ANALOG_MISC1_SET_IRQ_DIG_BO_MASK (0x80000000U) +#define CCM_ANALOG_MISC1_SET_IRQ_DIG_BO_SHIFT (31U) +#define CCM_ANALOG_MISC1_SET_IRQ_DIG_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_SET_IRQ_DIG_BO_SHIFT)) & CCM_ANALOG_MISC1_SET_IRQ_DIG_BO_MASK) +/*! @} */ + +/*! @name MISC1_CLR - Miscellaneous Register 1 */ +/*! @{ */ +#define CCM_ANALOG_MISC1_CLR_LVDS1_CLK_SEL_MASK (0x1FU) +#define CCM_ANALOG_MISC1_CLR_LVDS1_CLK_SEL_SHIFT (0U) +/*! LVDS1_CLK_SEL + * 0b00000..Arm PLL + * 0b00001..System PLL + * 0b00010..ref_pfd4_clk == pll2_pfd0_clk + * 0b00011..ref_pfd5_clk == pll2_pfd1_clk + * 0b00100..ref_pfd6_clk == pll2_pfd2_clk + * 0b00101..ref_pfd7_clk == pll2_pfd3_clk + * 0b00110..Audio PLL + * 0b00111..Video PLL + * 0b01001..ethernet ref clock (ENET_PLL) + * 0b01100..USB1 PLL clock + * 0b01101..USB2 PLL clock + * 0b01110..ref_pfd0_clk == pll3_pfd0_clk + * 0b01111..ref_pfd1_clk == pll3_pfd1_clk + * 0b10000..ref_pfd2_clk == pll3_pfd2_clk + * 0b10001..ref_pfd3_clk == pll3_pfd3_clk + * 0b10010..xtal (24M) + */ +#define CCM_ANALOG_MISC1_CLR_LVDS1_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_CLR_LVDS1_CLK_SEL_SHIFT)) & CCM_ANALOG_MISC1_CLR_LVDS1_CLK_SEL_MASK) +#define CCM_ANALOG_MISC1_CLR_LVDSCLK1_OBEN_MASK (0x400U) +#define CCM_ANALOG_MISC1_CLR_LVDSCLK1_OBEN_SHIFT (10U) +#define CCM_ANALOG_MISC1_CLR_LVDSCLK1_OBEN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_CLR_LVDSCLK1_OBEN_SHIFT)) & CCM_ANALOG_MISC1_CLR_LVDSCLK1_OBEN_MASK) +#define CCM_ANALOG_MISC1_CLR_LVDSCLK1_IBEN_MASK (0x1000U) +#define CCM_ANALOG_MISC1_CLR_LVDSCLK1_IBEN_SHIFT (12U) +#define CCM_ANALOG_MISC1_CLR_LVDSCLK1_IBEN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_CLR_LVDSCLK1_IBEN_SHIFT)) & CCM_ANALOG_MISC1_CLR_LVDSCLK1_IBEN_MASK) +#define CCM_ANALOG_MISC1_CLR_PFD_480_AUTOGATE_EN_MASK (0x10000U) +#define CCM_ANALOG_MISC1_CLR_PFD_480_AUTOGATE_EN_SHIFT (16U) +#define CCM_ANALOG_MISC1_CLR_PFD_480_AUTOGATE_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_CLR_PFD_480_AUTOGATE_EN_SHIFT)) & CCM_ANALOG_MISC1_CLR_PFD_480_AUTOGATE_EN_MASK) +#define CCM_ANALOG_MISC1_CLR_PFD_528_AUTOGATE_EN_MASK (0x20000U) +#define CCM_ANALOG_MISC1_CLR_PFD_528_AUTOGATE_EN_SHIFT (17U) +#define CCM_ANALOG_MISC1_CLR_PFD_528_AUTOGATE_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_CLR_PFD_528_AUTOGATE_EN_SHIFT)) & CCM_ANALOG_MISC1_CLR_PFD_528_AUTOGATE_EN_MASK) +#define CCM_ANALOG_MISC1_CLR_IRQ_TEMPPANIC_MASK (0x8000000U) +#define CCM_ANALOG_MISC1_CLR_IRQ_TEMPPANIC_SHIFT (27U) +#define CCM_ANALOG_MISC1_CLR_IRQ_TEMPPANIC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_CLR_IRQ_TEMPPANIC_SHIFT)) & CCM_ANALOG_MISC1_CLR_IRQ_TEMPPANIC_MASK) +#define CCM_ANALOG_MISC1_CLR_IRQ_TEMPLOW_MASK (0x10000000U) +#define CCM_ANALOG_MISC1_CLR_IRQ_TEMPLOW_SHIFT (28U) +#define CCM_ANALOG_MISC1_CLR_IRQ_TEMPLOW(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_CLR_IRQ_TEMPLOW_SHIFT)) & CCM_ANALOG_MISC1_CLR_IRQ_TEMPLOW_MASK) +#define CCM_ANALOG_MISC1_CLR_IRQ_TEMPHIGH_MASK (0x20000000U) +#define CCM_ANALOG_MISC1_CLR_IRQ_TEMPHIGH_SHIFT (29U) +#define CCM_ANALOG_MISC1_CLR_IRQ_TEMPHIGH(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_CLR_IRQ_TEMPHIGH_SHIFT)) & CCM_ANALOG_MISC1_CLR_IRQ_TEMPHIGH_MASK) +#define CCM_ANALOG_MISC1_CLR_IRQ_ANA_BO_MASK (0x40000000U) +#define CCM_ANALOG_MISC1_CLR_IRQ_ANA_BO_SHIFT (30U) +#define CCM_ANALOG_MISC1_CLR_IRQ_ANA_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_CLR_IRQ_ANA_BO_SHIFT)) & CCM_ANALOG_MISC1_CLR_IRQ_ANA_BO_MASK) +#define CCM_ANALOG_MISC1_CLR_IRQ_DIG_BO_MASK (0x80000000U) +#define CCM_ANALOG_MISC1_CLR_IRQ_DIG_BO_SHIFT (31U) +#define CCM_ANALOG_MISC1_CLR_IRQ_DIG_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_CLR_IRQ_DIG_BO_SHIFT)) & CCM_ANALOG_MISC1_CLR_IRQ_DIG_BO_MASK) +/*! @} */ + +/*! @name MISC1_TOG - Miscellaneous Register 1 */ +/*! @{ */ +#define CCM_ANALOG_MISC1_TOG_LVDS1_CLK_SEL_MASK (0x1FU) +#define CCM_ANALOG_MISC1_TOG_LVDS1_CLK_SEL_SHIFT (0U) +/*! LVDS1_CLK_SEL + * 0b00000..Arm PLL + * 0b00001..System PLL + * 0b00010..ref_pfd4_clk == pll2_pfd0_clk + * 0b00011..ref_pfd5_clk == pll2_pfd1_clk + * 0b00100..ref_pfd6_clk == pll2_pfd2_clk + * 0b00101..ref_pfd7_clk == pll2_pfd3_clk + * 0b00110..Audio PLL + * 0b00111..Video PLL + * 0b01001..ethernet ref clock (ENET_PLL) + * 0b01100..USB1 PLL clock + * 0b01101..USB2 PLL clock + * 0b01110..ref_pfd0_clk == pll3_pfd0_clk + * 0b01111..ref_pfd1_clk == pll3_pfd1_clk + * 0b10000..ref_pfd2_clk == pll3_pfd2_clk + * 0b10001..ref_pfd3_clk == pll3_pfd3_clk + * 0b10010..xtal (24M) + */ +#define CCM_ANALOG_MISC1_TOG_LVDS1_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_TOG_LVDS1_CLK_SEL_SHIFT)) & CCM_ANALOG_MISC1_TOG_LVDS1_CLK_SEL_MASK) +#define CCM_ANALOG_MISC1_TOG_LVDSCLK1_OBEN_MASK (0x400U) +#define CCM_ANALOG_MISC1_TOG_LVDSCLK1_OBEN_SHIFT (10U) +#define CCM_ANALOG_MISC1_TOG_LVDSCLK1_OBEN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_TOG_LVDSCLK1_OBEN_SHIFT)) & CCM_ANALOG_MISC1_TOG_LVDSCLK1_OBEN_MASK) +#define CCM_ANALOG_MISC1_TOG_LVDSCLK1_IBEN_MASK (0x1000U) +#define CCM_ANALOG_MISC1_TOG_LVDSCLK1_IBEN_SHIFT (12U) +#define CCM_ANALOG_MISC1_TOG_LVDSCLK1_IBEN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_TOG_LVDSCLK1_IBEN_SHIFT)) & CCM_ANALOG_MISC1_TOG_LVDSCLK1_IBEN_MASK) +#define CCM_ANALOG_MISC1_TOG_PFD_480_AUTOGATE_EN_MASK (0x10000U) +#define CCM_ANALOG_MISC1_TOG_PFD_480_AUTOGATE_EN_SHIFT (16U) +#define CCM_ANALOG_MISC1_TOG_PFD_480_AUTOGATE_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_TOG_PFD_480_AUTOGATE_EN_SHIFT)) & CCM_ANALOG_MISC1_TOG_PFD_480_AUTOGATE_EN_MASK) +#define CCM_ANALOG_MISC1_TOG_PFD_528_AUTOGATE_EN_MASK (0x20000U) +#define CCM_ANALOG_MISC1_TOG_PFD_528_AUTOGATE_EN_SHIFT (17U) +#define CCM_ANALOG_MISC1_TOG_PFD_528_AUTOGATE_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_TOG_PFD_528_AUTOGATE_EN_SHIFT)) & CCM_ANALOG_MISC1_TOG_PFD_528_AUTOGATE_EN_MASK) +#define CCM_ANALOG_MISC1_TOG_IRQ_TEMPPANIC_MASK (0x8000000U) +#define CCM_ANALOG_MISC1_TOG_IRQ_TEMPPANIC_SHIFT (27U) +#define CCM_ANALOG_MISC1_TOG_IRQ_TEMPPANIC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_TOG_IRQ_TEMPPANIC_SHIFT)) & CCM_ANALOG_MISC1_TOG_IRQ_TEMPPANIC_MASK) +#define CCM_ANALOG_MISC1_TOG_IRQ_TEMPLOW_MASK (0x10000000U) +#define CCM_ANALOG_MISC1_TOG_IRQ_TEMPLOW_SHIFT (28U) +#define CCM_ANALOG_MISC1_TOG_IRQ_TEMPLOW(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_TOG_IRQ_TEMPLOW_SHIFT)) & CCM_ANALOG_MISC1_TOG_IRQ_TEMPLOW_MASK) +#define CCM_ANALOG_MISC1_TOG_IRQ_TEMPHIGH_MASK (0x20000000U) +#define CCM_ANALOG_MISC1_TOG_IRQ_TEMPHIGH_SHIFT (29U) +#define CCM_ANALOG_MISC1_TOG_IRQ_TEMPHIGH(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_TOG_IRQ_TEMPHIGH_SHIFT)) & CCM_ANALOG_MISC1_TOG_IRQ_TEMPHIGH_MASK) +#define CCM_ANALOG_MISC1_TOG_IRQ_ANA_BO_MASK (0x40000000U) +#define CCM_ANALOG_MISC1_TOG_IRQ_ANA_BO_SHIFT (30U) +#define CCM_ANALOG_MISC1_TOG_IRQ_ANA_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_TOG_IRQ_ANA_BO_SHIFT)) & CCM_ANALOG_MISC1_TOG_IRQ_ANA_BO_MASK) +#define CCM_ANALOG_MISC1_TOG_IRQ_DIG_BO_MASK (0x80000000U) +#define CCM_ANALOG_MISC1_TOG_IRQ_DIG_BO_SHIFT (31U) +#define CCM_ANALOG_MISC1_TOG_IRQ_DIG_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_TOG_IRQ_DIG_BO_SHIFT)) & CCM_ANALOG_MISC1_TOG_IRQ_DIG_BO_MASK) +/*! @} */ + +/*! @name MISC2 - Miscellaneous Register 2 */ +/*! @{ */ +#define CCM_ANALOG_MISC2_REG0_BO_OFFSET_MASK (0x7U) +#define CCM_ANALOG_MISC2_REG0_BO_OFFSET_SHIFT (0U) +/*! REG0_BO_OFFSET + * 0b100..Brownout offset = 0.100V + * 0b111..Brownout offset = 0.175V + */ +#define CCM_ANALOG_MISC2_REG0_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_REG0_BO_OFFSET_SHIFT)) & CCM_ANALOG_MISC2_REG0_BO_OFFSET_MASK) +#define CCM_ANALOG_MISC2_REG0_BO_STATUS_MASK (0x8U) +#define CCM_ANALOG_MISC2_REG0_BO_STATUS_SHIFT (3U) +/*! REG0_BO_STATUS + * 0b1..Brownout, supply is below target minus brownout offset. + */ +#define CCM_ANALOG_MISC2_REG0_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_REG0_BO_STATUS_SHIFT)) & CCM_ANALOG_MISC2_REG0_BO_STATUS_MASK) +#define CCM_ANALOG_MISC2_REG0_ENABLE_BO_MASK (0x20U) +#define CCM_ANALOG_MISC2_REG0_ENABLE_BO_SHIFT (5U) +#define CCM_ANALOG_MISC2_REG0_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_REG0_ENABLE_BO_SHIFT)) & CCM_ANALOG_MISC2_REG0_ENABLE_BO_MASK) +#define CCM_ANALOG_MISC2_REG0_OK_MASK (0x40U) +#define CCM_ANALOG_MISC2_REG0_OK_SHIFT (6U) +#define CCM_ANALOG_MISC2_REG0_OK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_REG0_OK_SHIFT)) & CCM_ANALOG_MISC2_REG0_OK_MASK) +#define CCM_ANALOG_MISC2_PLL3_disable_MASK (0x80U) +#define CCM_ANALOG_MISC2_PLL3_disable_SHIFT (7U) +/*! PLL3_disable + * 0b0..PLL3 is being used by peripherals and is enabled when SoC is not in any low power mode + * 0b1..PLL3 can be disabled when the SoC is not in any low power mode + */ +#define CCM_ANALOG_MISC2_PLL3_disable(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_PLL3_disable_SHIFT)) & CCM_ANALOG_MISC2_PLL3_disable_MASK) +#define CCM_ANALOG_MISC2_REG1_BO_OFFSET_MASK (0x700U) +#define CCM_ANALOG_MISC2_REG1_BO_OFFSET_SHIFT (8U) +/*! REG1_BO_OFFSET + * 0b100..Brownout offset = 0.100V + * 0b111..Brownout offset = 0.175V + */ +#define CCM_ANALOG_MISC2_REG1_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_REG1_BO_OFFSET_SHIFT)) & CCM_ANALOG_MISC2_REG1_BO_OFFSET_MASK) +#define CCM_ANALOG_MISC2_REG1_BO_STATUS_MASK (0x800U) +#define CCM_ANALOG_MISC2_REG1_BO_STATUS_SHIFT (11U) +/*! REG1_BO_STATUS + * 0b1..Brownout, supply is below target minus brownout offset. + */ +#define CCM_ANALOG_MISC2_REG1_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_REG1_BO_STATUS_SHIFT)) & CCM_ANALOG_MISC2_REG1_BO_STATUS_MASK) +#define CCM_ANALOG_MISC2_REG1_ENABLE_BO_MASK (0x2000U) +#define CCM_ANALOG_MISC2_REG1_ENABLE_BO_SHIFT (13U) +#define CCM_ANALOG_MISC2_REG1_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_REG1_ENABLE_BO_SHIFT)) & CCM_ANALOG_MISC2_REG1_ENABLE_BO_MASK) +#define CCM_ANALOG_MISC2_REG1_OK_MASK (0x4000U) +#define CCM_ANALOG_MISC2_REG1_OK_SHIFT (14U) +#define CCM_ANALOG_MISC2_REG1_OK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_REG1_OK_SHIFT)) & CCM_ANALOG_MISC2_REG1_OK_MASK) +#define CCM_ANALOG_MISC2_AUDIO_DIV_LSB_MASK (0x8000U) +#define CCM_ANALOG_MISC2_AUDIO_DIV_LSB_SHIFT (15U) +/*! AUDIO_DIV_LSB + * 0b0..divide by 1 (Default) + * 0b1..divide by 2 + */ +#define CCM_ANALOG_MISC2_AUDIO_DIV_LSB(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_AUDIO_DIV_LSB_SHIFT)) & CCM_ANALOG_MISC2_AUDIO_DIV_LSB_MASK) +#define CCM_ANALOG_MISC2_REG2_BO_OFFSET_MASK (0x70000U) +#define CCM_ANALOG_MISC2_REG2_BO_OFFSET_SHIFT (16U) +/*! REG2_BO_OFFSET + * 0b100..Brownout offset = 0.100V + * 0b111..Brownout offset = 0.175V + */ +#define CCM_ANALOG_MISC2_REG2_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_REG2_BO_OFFSET_SHIFT)) & CCM_ANALOG_MISC2_REG2_BO_OFFSET_MASK) +#define CCM_ANALOG_MISC2_REG2_BO_STATUS_MASK (0x80000U) +#define CCM_ANALOG_MISC2_REG2_BO_STATUS_SHIFT (19U) +#define CCM_ANALOG_MISC2_REG2_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_REG2_BO_STATUS_SHIFT)) & CCM_ANALOG_MISC2_REG2_BO_STATUS_MASK) +#define CCM_ANALOG_MISC2_REG2_ENABLE_BO_MASK (0x200000U) +#define CCM_ANALOG_MISC2_REG2_ENABLE_BO_SHIFT (21U) +#define CCM_ANALOG_MISC2_REG2_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_REG2_ENABLE_BO_SHIFT)) & CCM_ANALOG_MISC2_REG2_ENABLE_BO_MASK) +#define CCM_ANALOG_MISC2_REG2_OK_MASK (0x400000U) +#define CCM_ANALOG_MISC2_REG2_OK_SHIFT (22U) +#define CCM_ANALOG_MISC2_REG2_OK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_REG2_OK_SHIFT)) & CCM_ANALOG_MISC2_REG2_OK_MASK) +#define CCM_ANALOG_MISC2_AUDIO_DIV_MSB_MASK (0x800000U) +#define CCM_ANALOG_MISC2_AUDIO_DIV_MSB_SHIFT (23U) +/*! AUDIO_DIV_MSB + * 0b0..divide by 1 (Default) + * 0b1..divide by 2 + */ +#define CCM_ANALOG_MISC2_AUDIO_DIV_MSB(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_AUDIO_DIV_MSB_SHIFT)) & CCM_ANALOG_MISC2_AUDIO_DIV_MSB_MASK) +#define CCM_ANALOG_MISC2_REG0_STEP_TIME_MASK (0x3000000U) +#define CCM_ANALOG_MISC2_REG0_STEP_TIME_SHIFT (24U) +/*! REG0_STEP_TIME + * 0b00..64 + * 0b01..128 + * 0b10..256 + * 0b11..512 + */ +#define CCM_ANALOG_MISC2_REG0_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_REG0_STEP_TIME_SHIFT)) & CCM_ANALOG_MISC2_REG0_STEP_TIME_MASK) +#define CCM_ANALOG_MISC2_REG1_STEP_TIME_MASK (0xC000000U) +#define CCM_ANALOG_MISC2_REG1_STEP_TIME_SHIFT (26U) +/*! REG1_STEP_TIME + * 0b00..64 + * 0b01..128 + * 0b10..256 + * 0b11..512 + */ +#define CCM_ANALOG_MISC2_REG1_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_REG1_STEP_TIME_SHIFT)) & CCM_ANALOG_MISC2_REG1_STEP_TIME_MASK) +#define CCM_ANALOG_MISC2_REG2_STEP_TIME_MASK (0x30000000U) +#define CCM_ANALOG_MISC2_REG2_STEP_TIME_SHIFT (28U) +/*! REG2_STEP_TIME + * 0b00..64 + * 0b01..128 + * 0b10..256 + * 0b11..512 + */ +#define CCM_ANALOG_MISC2_REG2_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_REG2_STEP_TIME_SHIFT)) & CCM_ANALOG_MISC2_REG2_STEP_TIME_MASK) +#define CCM_ANALOG_MISC2_VIDEO_DIV_MASK (0xC0000000U) +#define CCM_ANALOG_MISC2_VIDEO_DIV_SHIFT (30U) +/*! VIDEO_DIV + * 0b00..divide by 1 (Default) + * 0b01..divide by 2 + * 0b10..divide by 1 + * 0b11..divide by 4 + */ +#define CCM_ANALOG_MISC2_VIDEO_DIV(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_VIDEO_DIV_SHIFT)) & CCM_ANALOG_MISC2_VIDEO_DIV_MASK) +/*! @} */ + +/*! @name MISC2_SET - Miscellaneous Register 2 */ +/*! @{ */ +#define CCM_ANALOG_MISC2_SET_REG0_BO_OFFSET_MASK (0x7U) +#define CCM_ANALOG_MISC2_SET_REG0_BO_OFFSET_SHIFT (0U) +/*! REG0_BO_OFFSET + * 0b100..Brownout offset = 0.100V + * 0b111..Brownout offset = 0.175V + */ +#define CCM_ANALOG_MISC2_SET_REG0_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_REG0_BO_OFFSET_SHIFT)) & CCM_ANALOG_MISC2_SET_REG0_BO_OFFSET_MASK) +#define CCM_ANALOG_MISC2_SET_REG0_BO_STATUS_MASK (0x8U) +#define CCM_ANALOG_MISC2_SET_REG0_BO_STATUS_SHIFT (3U) +/*! REG0_BO_STATUS + * 0b1..Brownout, supply is below target minus brownout offset. + */ +#define CCM_ANALOG_MISC2_SET_REG0_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_REG0_BO_STATUS_SHIFT)) & CCM_ANALOG_MISC2_SET_REG0_BO_STATUS_MASK) +#define CCM_ANALOG_MISC2_SET_REG0_ENABLE_BO_MASK (0x20U) +#define CCM_ANALOG_MISC2_SET_REG0_ENABLE_BO_SHIFT (5U) +#define CCM_ANALOG_MISC2_SET_REG0_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_REG0_ENABLE_BO_SHIFT)) & CCM_ANALOG_MISC2_SET_REG0_ENABLE_BO_MASK) +#define CCM_ANALOG_MISC2_SET_REG0_OK_MASK (0x40U) +#define CCM_ANALOG_MISC2_SET_REG0_OK_SHIFT (6U) +#define CCM_ANALOG_MISC2_SET_REG0_OK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_REG0_OK_SHIFT)) & CCM_ANALOG_MISC2_SET_REG0_OK_MASK) +#define CCM_ANALOG_MISC2_SET_PLL3_disable_MASK (0x80U) +#define CCM_ANALOG_MISC2_SET_PLL3_disable_SHIFT (7U) +/*! PLL3_disable + * 0b0..PLL3 is being used by peripherals and is enabled when SoC is not in any low power mode + * 0b1..PLL3 can be disabled when the SoC is not in any low power mode + */ +#define CCM_ANALOG_MISC2_SET_PLL3_disable(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_PLL3_disable_SHIFT)) & CCM_ANALOG_MISC2_SET_PLL3_disable_MASK) +#define CCM_ANALOG_MISC2_SET_REG1_BO_OFFSET_MASK (0x700U) +#define CCM_ANALOG_MISC2_SET_REG1_BO_OFFSET_SHIFT (8U) +/*! REG1_BO_OFFSET + * 0b100..Brownout offset = 0.100V + * 0b111..Brownout offset = 0.175V + */ +#define CCM_ANALOG_MISC2_SET_REG1_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_REG1_BO_OFFSET_SHIFT)) & CCM_ANALOG_MISC2_SET_REG1_BO_OFFSET_MASK) +#define CCM_ANALOG_MISC2_SET_REG1_BO_STATUS_MASK (0x800U) +#define CCM_ANALOG_MISC2_SET_REG1_BO_STATUS_SHIFT (11U) +/*! REG1_BO_STATUS + * 0b1..Brownout, supply is below target minus brownout offset. + */ +#define CCM_ANALOG_MISC2_SET_REG1_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_REG1_BO_STATUS_SHIFT)) & CCM_ANALOG_MISC2_SET_REG1_BO_STATUS_MASK) +#define CCM_ANALOG_MISC2_SET_REG1_ENABLE_BO_MASK (0x2000U) +#define CCM_ANALOG_MISC2_SET_REG1_ENABLE_BO_SHIFT (13U) +#define CCM_ANALOG_MISC2_SET_REG1_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_REG1_ENABLE_BO_SHIFT)) & CCM_ANALOG_MISC2_SET_REG1_ENABLE_BO_MASK) +#define CCM_ANALOG_MISC2_SET_REG1_OK_MASK (0x4000U) +#define CCM_ANALOG_MISC2_SET_REG1_OK_SHIFT (14U) +#define CCM_ANALOG_MISC2_SET_REG1_OK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_REG1_OK_SHIFT)) & CCM_ANALOG_MISC2_SET_REG1_OK_MASK) +#define CCM_ANALOG_MISC2_SET_AUDIO_DIV_LSB_MASK (0x8000U) +#define CCM_ANALOG_MISC2_SET_AUDIO_DIV_LSB_SHIFT (15U) +/*! AUDIO_DIV_LSB + * 0b0..divide by 1 (Default) + * 0b1..divide by 2 + */ +#define CCM_ANALOG_MISC2_SET_AUDIO_DIV_LSB(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_AUDIO_DIV_LSB_SHIFT)) & CCM_ANALOG_MISC2_SET_AUDIO_DIV_LSB_MASK) +#define CCM_ANALOG_MISC2_SET_REG2_BO_OFFSET_MASK (0x70000U) +#define CCM_ANALOG_MISC2_SET_REG2_BO_OFFSET_SHIFT (16U) +/*! REG2_BO_OFFSET + * 0b100..Brownout offset = 0.100V + * 0b111..Brownout offset = 0.175V + */ +#define CCM_ANALOG_MISC2_SET_REG2_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_REG2_BO_OFFSET_SHIFT)) & CCM_ANALOG_MISC2_SET_REG2_BO_OFFSET_MASK) +#define CCM_ANALOG_MISC2_SET_REG2_BO_STATUS_MASK (0x80000U) +#define CCM_ANALOG_MISC2_SET_REG2_BO_STATUS_SHIFT (19U) +#define CCM_ANALOG_MISC2_SET_REG2_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_REG2_BO_STATUS_SHIFT)) & CCM_ANALOG_MISC2_SET_REG2_BO_STATUS_MASK) +#define CCM_ANALOG_MISC2_SET_REG2_ENABLE_BO_MASK (0x200000U) +#define CCM_ANALOG_MISC2_SET_REG2_ENABLE_BO_SHIFT (21U) +#define CCM_ANALOG_MISC2_SET_REG2_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_REG2_ENABLE_BO_SHIFT)) & CCM_ANALOG_MISC2_SET_REG2_ENABLE_BO_MASK) +#define CCM_ANALOG_MISC2_SET_REG2_OK_MASK (0x400000U) +#define CCM_ANALOG_MISC2_SET_REG2_OK_SHIFT (22U) +#define CCM_ANALOG_MISC2_SET_REG2_OK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_REG2_OK_SHIFT)) & CCM_ANALOG_MISC2_SET_REG2_OK_MASK) +#define CCM_ANALOG_MISC2_SET_AUDIO_DIV_MSB_MASK (0x800000U) +#define CCM_ANALOG_MISC2_SET_AUDIO_DIV_MSB_SHIFT (23U) +/*! AUDIO_DIV_MSB + * 0b0..divide by 1 (Default) + * 0b1..divide by 2 + */ +#define CCM_ANALOG_MISC2_SET_AUDIO_DIV_MSB(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_AUDIO_DIV_MSB_SHIFT)) & CCM_ANALOG_MISC2_SET_AUDIO_DIV_MSB_MASK) +#define CCM_ANALOG_MISC2_SET_REG0_STEP_TIME_MASK (0x3000000U) +#define CCM_ANALOG_MISC2_SET_REG0_STEP_TIME_SHIFT (24U) +/*! REG0_STEP_TIME + * 0b00..64 + * 0b01..128 + * 0b10..256 + * 0b11..512 + */ +#define CCM_ANALOG_MISC2_SET_REG0_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_REG0_STEP_TIME_SHIFT)) & CCM_ANALOG_MISC2_SET_REG0_STEP_TIME_MASK) +#define CCM_ANALOG_MISC2_SET_REG1_STEP_TIME_MASK (0xC000000U) +#define CCM_ANALOG_MISC2_SET_REG1_STEP_TIME_SHIFT (26U) +/*! REG1_STEP_TIME + * 0b00..64 + * 0b01..128 + * 0b10..256 + * 0b11..512 + */ +#define CCM_ANALOG_MISC2_SET_REG1_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_REG1_STEP_TIME_SHIFT)) & CCM_ANALOG_MISC2_SET_REG1_STEP_TIME_MASK) +#define CCM_ANALOG_MISC2_SET_REG2_STEP_TIME_MASK (0x30000000U) +#define CCM_ANALOG_MISC2_SET_REG2_STEP_TIME_SHIFT (28U) +/*! REG2_STEP_TIME + * 0b00..64 + * 0b01..128 + * 0b10..256 + * 0b11..512 + */ +#define CCM_ANALOG_MISC2_SET_REG2_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_REG2_STEP_TIME_SHIFT)) & CCM_ANALOG_MISC2_SET_REG2_STEP_TIME_MASK) +#define CCM_ANALOG_MISC2_SET_VIDEO_DIV_MASK (0xC0000000U) +#define CCM_ANALOG_MISC2_SET_VIDEO_DIV_SHIFT (30U) +/*! VIDEO_DIV + * 0b00..divide by 1 (Default) + * 0b01..divide by 2 + * 0b10..divide by 1 + * 0b11..divide by 4 + */ +#define CCM_ANALOG_MISC2_SET_VIDEO_DIV(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_VIDEO_DIV_SHIFT)) & CCM_ANALOG_MISC2_SET_VIDEO_DIV_MASK) +/*! @} */ + +/*! @name MISC2_CLR - Miscellaneous Register 2 */ +/*! @{ */ +#define CCM_ANALOG_MISC2_CLR_REG0_BO_OFFSET_MASK (0x7U) +#define CCM_ANALOG_MISC2_CLR_REG0_BO_OFFSET_SHIFT (0U) +/*! REG0_BO_OFFSET + * 0b100..Brownout offset = 0.100V + * 0b111..Brownout offset = 0.175V + */ +#define CCM_ANALOG_MISC2_CLR_REG0_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_REG0_BO_OFFSET_SHIFT)) & CCM_ANALOG_MISC2_CLR_REG0_BO_OFFSET_MASK) +#define CCM_ANALOG_MISC2_CLR_REG0_BO_STATUS_MASK (0x8U) +#define CCM_ANALOG_MISC2_CLR_REG0_BO_STATUS_SHIFT (3U) +/*! REG0_BO_STATUS + * 0b1..Brownout, supply is below target minus brownout offset. + */ +#define CCM_ANALOG_MISC2_CLR_REG0_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_REG0_BO_STATUS_SHIFT)) & CCM_ANALOG_MISC2_CLR_REG0_BO_STATUS_MASK) +#define CCM_ANALOG_MISC2_CLR_REG0_ENABLE_BO_MASK (0x20U) +#define CCM_ANALOG_MISC2_CLR_REG0_ENABLE_BO_SHIFT (5U) +#define CCM_ANALOG_MISC2_CLR_REG0_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_REG0_ENABLE_BO_SHIFT)) & CCM_ANALOG_MISC2_CLR_REG0_ENABLE_BO_MASK) +#define CCM_ANALOG_MISC2_CLR_REG0_OK_MASK (0x40U) +#define CCM_ANALOG_MISC2_CLR_REG0_OK_SHIFT (6U) +#define CCM_ANALOG_MISC2_CLR_REG0_OK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_REG0_OK_SHIFT)) & CCM_ANALOG_MISC2_CLR_REG0_OK_MASK) +#define CCM_ANALOG_MISC2_CLR_PLL3_disable_MASK (0x80U) +#define CCM_ANALOG_MISC2_CLR_PLL3_disable_SHIFT (7U) +/*! PLL3_disable + * 0b0..PLL3 is being used by peripherals and is enabled when SoC is not in any low power mode + * 0b1..PLL3 can be disabled when the SoC is not in any low power mode + */ +#define CCM_ANALOG_MISC2_CLR_PLL3_disable(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_PLL3_disable_SHIFT)) & CCM_ANALOG_MISC2_CLR_PLL3_disable_MASK) +#define CCM_ANALOG_MISC2_CLR_REG1_BO_OFFSET_MASK (0x700U) +#define CCM_ANALOG_MISC2_CLR_REG1_BO_OFFSET_SHIFT (8U) +/*! REG1_BO_OFFSET + * 0b100..Brownout offset = 0.100V + * 0b111..Brownout offset = 0.175V + */ +#define CCM_ANALOG_MISC2_CLR_REG1_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_REG1_BO_OFFSET_SHIFT)) & CCM_ANALOG_MISC2_CLR_REG1_BO_OFFSET_MASK) +#define CCM_ANALOG_MISC2_CLR_REG1_BO_STATUS_MASK (0x800U) +#define CCM_ANALOG_MISC2_CLR_REG1_BO_STATUS_SHIFT (11U) +/*! REG1_BO_STATUS + * 0b1..Brownout, supply is below target minus brownout offset. + */ +#define CCM_ANALOG_MISC2_CLR_REG1_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_REG1_BO_STATUS_SHIFT)) & CCM_ANALOG_MISC2_CLR_REG1_BO_STATUS_MASK) +#define CCM_ANALOG_MISC2_CLR_REG1_ENABLE_BO_MASK (0x2000U) +#define CCM_ANALOG_MISC2_CLR_REG1_ENABLE_BO_SHIFT (13U) +#define CCM_ANALOG_MISC2_CLR_REG1_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_REG1_ENABLE_BO_SHIFT)) & CCM_ANALOG_MISC2_CLR_REG1_ENABLE_BO_MASK) +#define CCM_ANALOG_MISC2_CLR_REG1_OK_MASK (0x4000U) +#define CCM_ANALOG_MISC2_CLR_REG1_OK_SHIFT (14U) +#define CCM_ANALOG_MISC2_CLR_REG1_OK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_REG1_OK_SHIFT)) & CCM_ANALOG_MISC2_CLR_REG1_OK_MASK) +#define CCM_ANALOG_MISC2_CLR_AUDIO_DIV_LSB_MASK (0x8000U) +#define CCM_ANALOG_MISC2_CLR_AUDIO_DIV_LSB_SHIFT (15U) +/*! AUDIO_DIV_LSB + * 0b0..divide by 1 (Default) + * 0b1..divide by 2 + */ +#define CCM_ANALOG_MISC2_CLR_AUDIO_DIV_LSB(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_AUDIO_DIV_LSB_SHIFT)) & CCM_ANALOG_MISC2_CLR_AUDIO_DIV_LSB_MASK) +#define CCM_ANALOG_MISC2_CLR_REG2_BO_OFFSET_MASK (0x70000U) +#define CCM_ANALOG_MISC2_CLR_REG2_BO_OFFSET_SHIFT (16U) +/*! REG2_BO_OFFSET + * 0b100..Brownout offset = 0.100V + * 0b111..Brownout offset = 0.175V + */ +#define CCM_ANALOG_MISC2_CLR_REG2_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_REG2_BO_OFFSET_SHIFT)) & CCM_ANALOG_MISC2_CLR_REG2_BO_OFFSET_MASK) +#define CCM_ANALOG_MISC2_CLR_REG2_BO_STATUS_MASK (0x80000U) +#define CCM_ANALOG_MISC2_CLR_REG2_BO_STATUS_SHIFT (19U) +#define CCM_ANALOG_MISC2_CLR_REG2_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_REG2_BO_STATUS_SHIFT)) & CCM_ANALOG_MISC2_CLR_REG2_BO_STATUS_MASK) +#define CCM_ANALOG_MISC2_CLR_REG2_ENABLE_BO_MASK (0x200000U) +#define CCM_ANALOG_MISC2_CLR_REG2_ENABLE_BO_SHIFT (21U) +#define CCM_ANALOG_MISC2_CLR_REG2_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_REG2_ENABLE_BO_SHIFT)) & CCM_ANALOG_MISC2_CLR_REG2_ENABLE_BO_MASK) +#define CCM_ANALOG_MISC2_CLR_REG2_OK_MASK (0x400000U) +#define CCM_ANALOG_MISC2_CLR_REG2_OK_SHIFT (22U) +#define CCM_ANALOG_MISC2_CLR_REG2_OK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_REG2_OK_SHIFT)) & CCM_ANALOG_MISC2_CLR_REG2_OK_MASK) +#define CCM_ANALOG_MISC2_CLR_AUDIO_DIV_MSB_MASK (0x800000U) +#define CCM_ANALOG_MISC2_CLR_AUDIO_DIV_MSB_SHIFT (23U) +/*! AUDIO_DIV_MSB + * 0b0..divide by 1 (Default) + * 0b1..divide by 2 + */ +#define CCM_ANALOG_MISC2_CLR_AUDIO_DIV_MSB(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_AUDIO_DIV_MSB_SHIFT)) & CCM_ANALOG_MISC2_CLR_AUDIO_DIV_MSB_MASK) +#define CCM_ANALOG_MISC2_CLR_REG0_STEP_TIME_MASK (0x3000000U) +#define CCM_ANALOG_MISC2_CLR_REG0_STEP_TIME_SHIFT (24U) +/*! REG0_STEP_TIME + * 0b00..64 + * 0b01..128 + * 0b10..256 + * 0b11..512 + */ +#define CCM_ANALOG_MISC2_CLR_REG0_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_REG0_STEP_TIME_SHIFT)) & CCM_ANALOG_MISC2_CLR_REG0_STEP_TIME_MASK) +#define CCM_ANALOG_MISC2_CLR_REG1_STEP_TIME_MASK (0xC000000U) +#define CCM_ANALOG_MISC2_CLR_REG1_STEP_TIME_SHIFT (26U) +/*! REG1_STEP_TIME + * 0b00..64 + * 0b01..128 + * 0b10..256 + * 0b11..512 + */ +#define CCM_ANALOG_MISC2_CLR_REG1_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_REG1_STEP_TIME_SHIFT)) & CCM_ANALOG_MISC2_CLR_REG1_STEP_TIME_MASK) +#define CCM_ANALOG_MISC2_CLR_REG2_STEP_TIME_MASK (0x30000000U) +#define CCM_ANALOG_MISC2_CLR_REG2_STEP_TIME_SHIFT (28U) +/*! REG2_STEP_TIME + * 0b00..64 + * 0b01..128 + * 0b10..256 + * 0b11..512 + */ +#define CCM_ANALOG_MISC2_CLR_REG2_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_REG2_STEP_TIME_SHIFT)) & CCM_ANALOG_MISC2_CLR_REG2_STEP_TIME_MASK) +#define CCM_ANALOG_MISC2_CLR_VIDEO_DIV_MASK (0xC0000000U) +#define CCM_ANALOG_MISC2_CLR_VIDEO_DIV_SHIFT (30U) +/*! VIDEO_DIV + * 0b00..divide by 1 (Default) + * 0b01..divide by 2 + * 0b10..divide by 1 + * 0b11..divide by 4 + */ +#define CCM_ANALOG_MISC2_CLR_VIDEO_DIV(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_VIDEO_DIV_SHIFT)) & CCM_ANALOG_MISC2_CLR_VIDEO_DIV_MASK) +/*! @} */ + +/*! @name MISC2_TOG - Miscellaneous Register 2 */ +/*! @{ */ +#define CCM_ANALOG_MISC2_TOG_REG0_BO_OFFSET_MASK (0x7U) +#define CCM_ANALOG_MISC2_TOG_REG0_BO_OFFSET_SHIFT (0U) +/*! REG0_BO_OFFSET + * 0b100..Brownout offset = 0.100V + * 0b111..Brownout offset = 0.175V + */ +#define CCM_ANALOG_MISC2_TOG_REG0_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_REG0_BO_OFFSET_SHIFT)) & CCM_ANALOG_MISC2_TOG_REG0_BO_OFFSET_MASK) +#define CCM_ANALOG_MISC2_TOG_REG0_BO_STATUS_MASK (0x8U) +#define CCM_ANALOG_MISC2_TOG_REG0_BO_STATUS_SHIFT (3U) +/*! REG0_BO_STATUS + * 0b1..Brownout, supply is below target minus brownout offset. + */ +#define CCM_ANALOG_MISC2_TOG_REG0_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_REG0_BO_STATUS_SHIFT)) & CCM_ANALOG_MISC2_TOG_REG0_BO_STATUS_MASK) +#define CCM_ANALOG_MISC2_TOG_REG0_ENABLE_BO_MASK (0x20U) +#define CCM_ANALOG_MISC2_TOG_REG0_ENABLE_BO_SHIFT (5U) +#define CCM_ANALOG_MISC2_TOG_REG0_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_REG0_ENABLE_BO_SHIFT)) & CCM_ANALOG_MISC2_TOG_REG0_ENABLE_BO_MASK) +#define CCM_ANALOG_MISC2_TOG_REG0_OK_MASK (0x40U) +#define CCM_ANALOG_MISC2_TOG_REG0_OK_SHIFT (6U) +#define CCM_ANALOG_MISC2_TOG_REG0_OK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_REG0_OK_SHIFT)) & CCM_ANALOG_MISC2_TOG_REG0_OK_MASK) +#define CCM_ANALOG_MISC2_TOG_PLL3_disable_MASK (0x80U) +#define CCM_ANALOG_MISC2_TOG_PLL3_disable_SHIFT (7U) +/*! PLL3_disable + * 0b0..PLL3 is being used by peripherals and is enabled when SoC is not in any low power mode + * 0b1..PLL3 can be disabled when the SoC is not in any low power mode + */ +#define CCM_ANALOG_MISC2_TOG_PLL3_disable(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_PLL3_disable_SHIFT)) & CCM_ANALOG_MISC2_TOG_PLL3_disable_MASK) +#define CCM_ANALOG_MISC2_TOG_REG1_BO_OFFSET_MASK (0x700U) +#define CCM_ANALOG_MISC2_TOG_REG1_BO_OFFSET_SHIFT (8U) +/*! REG1_BO_OFFSET + * 0b100..Brownout offset = 0.100V + * 0b111..Brownout offset = 0.175V + */ +#define CCM_ANALOG_MISC2_TOG_REG1_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_REG1_BO_OFFSET_SHIFT)) & CCM_ANALOG_MISC2_TOG_REG1_BO_OFFSET_MASK) +#define CCM_ANALOG_MISC2_TOG_REG1_BO_STATUS_MASK (0x800U) +#define CCM_ANALOG_MISC2_TOG_REG1_BO_STATUS_SHIFT (11U) +/*! REG1_BO_STATUS + * 0b1..Brownout, supply is below target minus brownout offset. + */ +#define CCM_ANALOG_MISC2_TOG_REG1_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_REG1_BO_STATUS_SHIFT)) & CCM_ANALOG_MISC2_TOG_REG1_BO_STATUS_MASK) +#define CCM_ANALOG_MISC2_TOG_REG1_ENABLE_BO_MASK (0x2000U) +#define CCM_ANALOG_MISC2_TOG_REG1_ENABLE_BO_SHIFT (13U) +#define CCM_ANALOG_MISC2_TOG_REG1_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_REG1_ENABLE_BO_SHIFT)) & CCM_ANALOG_MISC2_TOG_REG1_ENABLE_BO_MASK) +#define CCM_ANALOG_MISC2_TOG_REG1_OK_MASK (0x4000U) +#define CCM_ANALOG_MISC2_TOG_REG1_OK_SHIFT (14U) +#define CCM_ANALOG_MISC2_TOG_REG1_OK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_REG1_OK_SHIFT)) & CCM_ANALOG_MISC2_TOG_REG1_OK_MASK) +#define CCM_ANALOG_MISC2_TOG_AUDIO_DIV_LSB_MASK (0x8000U) +#define CCM_ANALOG_MISC2_TOG_AUDIO_DIV_LSB_SHIFT (15U) +/*! AUDIO_DIV_LSB + * 0b0..divide by 1 (Default) + * 0b1..divide by 2 + */ +#define CCM_ANALOG_MISC2_TOG_AUDIO_DIV_LSB(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_AUDIO_DIV_LSB_SHIFT)) & CCM_ANALOG_MISC2_TOG_AUDIO_DIV_LSB_MASK) +#define CCM_ANALOG_MISC2_TOG_REG2_BO_OFFSET_MASK (0x70000U) +#define CCM_ANALOG_MISC2_TOG_REG2_BO_OFFSET_SHIFT (16U) +/*! REG2_BO_OFFSET + * 0b100..Brownout offset = 0.100V + * 0b111..Brownout offset = 0.175V + */ +#define CCM_ANALOG_MISC2_TOG_REG2_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_REG2_BO_OFFSET_SHIFT)) & CCM_ANALOG_MISC2_TOG_REG2_BO_OFFSET_MASK) +#define CCM_ANALOG_MISC2_TOG_REG2_BO_STATUS_MASK (0x80000U) +#define CCM_ANALOG_MISC2_TOG_REG2_BO_STATUS_SHIFT (19U) +#define CCM_ANALOG_MISC2_TOG_REG2_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_REG2_BO_STATUS_SHIFT)) & CCM_ANALOG_MISC2_TOG_REG2_BO_STATUS_MASK) +#define CCM_ANALOG_MISC2_TOG_REG2_ENABLE_BO_MASK (0x200000U) +#define CCM_ANALOG_MISC2_TOG_REG2_ENABLE_BO_SHIFT (21U) +#define CCM_ANALOG_MISC2_TOG_REG2_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_REG2_ENABLE_BO_SHIFT)) & CCM_ANALOG_MISC2_TOG_REG2_ENABLE_BO_MASK) +#define CCM_ANALOG_MISC2_TOG_REG2_OK_MASK (0x400000U) +#define CCM_ANALOG_MISC2_TOG_REG2_OK_SHIFT (22U) +#define CCM_ANALOG_MISC2_TOG_REG2_OK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_REG2_OK_SHIFT)) & CCM_ANALOG_MISC2_TOG_REG2_OK_MASK) +#define CCM_ANALOG_MISC2_TOG_AUDIO_DIV_MSB_MASK (0x800000U) +#define CCM_ANALOG_MISC2_TOG_AUDIO_DIV_MSB_SHIFT (23U) +/*! AUDIO_DIV_MSB + * 0b0..divide by 1 (Default) + * 0b1..divide by 2 + */ +#define CCM_ANALOG_MISC2_TOG_AUDIO_DIV_MSB(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_AUDIO_DIV_MSB_SHIFT)) & CCM_ANALOG_MISC2_TOG_AUDIO_DIV_MSB_MASK) +#define CCM_ANALOG_MISC2_TOG_REG0_STEP_TIME_MASK (0x3000000U) +#define CCM_ANALOG_MISC2_TOG_REG0_STEP_TIME_SHIFT (24U) +/*! REG0_STEP_TIME + * 0b00..64 + * 0b01..128 + * 0b10..256 + * 0b11..512 + */ +#define CCM_ANALOG_MISC2_TOG_REG0_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_REG0_STEP_TIME_SHIFT)) & CCM_ANALOG_MISC2_TOG_REG0_STEP_TIME_MASK) +#define CCM_ANALOG_MISC2_TOG_REG1_STEP_TIME_MASK (0xC000000U) +#define CCM_ANALOG_MISC2_TOG_REG1_STEP_TIME_SHIFT (26U) +/*! REG1_STEP_TIME + * 0b00..64 + * 0b01..128 + * 0b10..256 + * 0b11..512 + */ +#define CCM_ANALOG_MISC2_TOG_REG1_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_REG1_STEP_TIME_SHIFT)) & CCM_ANALOG_MISC2_TOG_REG1_STEP_TIME_MASK) +#define CCM_ANALOG_MISC2_TOG_REG2_STEP_TIME_MASK (0x30000000U) +#define CCM_ANALOG_MISC2_TOG_REG2_STEP_TIME_SHIFT (28U) +/*! REG2_STEP_TIME + * 0b00..64 + * 0b01..128 + * 0b10..256 + * 0b11..512 + */ +#define CCM_ANALOG_MISC2_TOG_REG2_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_REG2_STEP_TIME_SHIFT)) & CCM_ANALOG_MISC2_TOG_REG2_STEP_TIME_MASK) +#define CCM_ANALOG_MISC2_TOG_VIDEO_DIV_MASK (0xC0000000U) +#define CCM_ANALOG_MISC2_TOG_VIDEO_DIV_SHIFT (30U) +/*! VIDEO_DIV + * 0b00..divide by 1 (Default) + * 0b01..divide by 2 + * 0b10..divide by 1 + * 0b11..divide by 4 + */ +#define CCM_ANALOG_MISC2_TOG_VIDEO_DIV(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_VIDEO_DIV_SHIFT)) & CCM_ANALOG_MISC2_TOG_VIDEO_DIV_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group CCM_ANALOG_Register_Masks */ + + +/* CCM_ANALOG - Peripheral instance base addresses */ +/** Peripheral CCM_ANALOG base address */ +#define CCM_ANALOG_BASE (0x400D8000u) +/** Peripheral CCM_ANALOG base pointer */ +#define CCM_ANALOG ((CCM_ANALOG_Type *)CCM_ANALOG_BASE) +/** Array initializer of CCM_ANALOG peripheral base addresses */ +#define CCM_ANALOG_BASE_ADDRS { CCM_ANALOG_BASE } +/** Array initializer of CCM_ANALOG peripheral base pointers */ +#define CCM_ANALOG_BASE_PTRS { CCM_ANALOG } + +/*! + * @} + */ /* end of group CCM_ANALOG_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- CMP Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup CMP_Peripheral_Access_Layer CMP Peripheral Access Layer + * @{ + */ + +/** CMP - Register Layout Typedef */ +typedef struct { + __IO uint8_t CR0; /**< CMP Control Register 0, offset: 0x0 */ + __IO uint8_t CR1; /**< CMP Control Register 1, offset: 0x1 */ + __IO uint8_t FPR; /**< CMP Filter Period Register, offset: 0x2 */ + __IO uint8_t SCR; /**< CMP Status and Control Register, offset: 0x3 */ + __IO uint8_t DACCR; /**< DAC Control Register, offset: 0x4 */ + __IO uint8_t MUXCR; /**< MUX Control Register, offset: 0x5 */ +} CMP_Type; + +/* ---------------------------------------------------------------------------- + -- CMP Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup CMP_Register_Masks CMP Register Masks + * @{ + */ + +/*! @name CR0 - CMP Control Register 0 */ +/*! @{ */ +#define CMP_CR0_HYSTCTR_MASK (0x3U) +#define CMP_CR0_HYSTCTR_SHIFT (0U) +/*! HYSTCTR - Comparator hard block hysteresis control + * 0b00..Level 0 + * 0b01..Level 1 + * 0b10..Level 2 + * 0b11..Level 3 + */ +#define CMP_CR0_HYSTCTR(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR0_HYSTCTR_SHIFT)) & CMP_CR0_HYSTCTR_MASK) +#define CMP_CR0_FILTER_CNT_MASK (0x70U) +#define CMP_CR0_FILTER_CNT_SHIFT (4U) +/*! FILTER_CNT - Filter Sample Count + * 0b000..Filter is disabled. If SE = 1, then COUT is a logic 0. This is not a legal state, and is not recommended. If SE = 0, COUT = COUTA. + * 0b001..One sample must agree. The comparator output is simply sampled. + * 0b010..2 consecutive samples must agree. + * 0b011..3 consecutive samples must agree. + * 0b100..4 consecutive samples must agree. + * 0b101..5 consecutive samples must agree. + * 0b110..6 consecutive samples must agree. + * 0b111..7 consecutive samples must agree. + */ +#define CMP_CR0_FILTER_CNT(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR0_FILTER_CNT_SHIFT)) & CMP_CR0_FILTER_CNT_MASK) +/*! @} */ + +/*! @name CR1 - CMP Control Register 1 */ +/*! @{ */ +#define CMP_CR1_EN_MASK (0x1U) +#define CMP_CR1_EN_SHIFT (0U) +/*! EN - Comparator Module Enable + * 0b0..Analog Comparator is disabled. + * 0b1..Analog Comparator is enabled. + */ +#define CMP_CR1_EN(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_EN_SHIFT)) & CMP_CR1_EN_MASK) +#define CMP_CR1_OPE_MASK (0x2U) +#define CMP_CR1_OPE_SHIFT (1U) +/*! OPE - Comparator Output Pin Enable + * 0b0..CMPO is not available on the associated CMPO output pin. If the comparator does not own the pin, this field has no effect. + * 0b1..CMPO is available on the associated CMPO output pin. The comparator output (CMPO) is driven out on the associated CMPO output pin if the comparator owns the pin. If the comparator does not own the field, this bit has no effect. + */ +#define CMP_CR1_OPE(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_OPE_SHIFT)) & CMP_CR1_OPE_MASK) +#define CMP_CR1_COS_MASK (0x4U) +#define CMP_CR1_COS_SHIFT (2U) +/*! COS - Comparator Output Select + * 0b0..Set the filtered comparator output (CMPO) to equal COUT. + * 0b1..Set the unfiltered comparator output (CMPO) to equal COUTA. + */ +#define CMP_CR1_COS(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_COS_SHIFT)) & CMP_CR1_COS_MASK) +#define CMP_CR1_INV_MASK (0x8U) +#define CMP_CR1_INV_SHIFT (3U) +/*! INV - Comparator INVERT + * 0b0..Does not invert the comparator output. + * 0b1..Inverts the comparator output. + */ +#define CMP_CR1_INV(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_INV_SHIFT)) & CMP_CR1_INV_MASK) +#define CMP_CR1_PMODE_MASK (0x10U) +#define CMP_CR1_PMODE_SHIFT (4U) +/*! PMODE - Power Mode Select + * 0b0..Low-Speed (LS) Comparison mode selected. In this mode, CMP has slower output propagation delay and lower current consumption. + * 0b1..High-Speed (HS) Comparison mode selected. In this mode, CMP has faster output propagation delay and higher current consumption. + */ +#define CMP_CR1_PMODE(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_PMODE_SHIFT)) & CMP_CR1_PMODE_MASK) +#define CMP_CR1_WE_MASK (0x40U) +#define CMP_CR1_WE_SHIFT (6U) +/*! WE - Windowing Enable + * 0b0..Windowing mode is not selected. + * 0b1..Windowing mode is selected. + */ +#define CMP_CR1_WE(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_WE_SHIFT)) & CMP_CR1_WE_MASK) +#define CMP_CR1_SE_MASK (0x80U) +#define CMP_CR1_SE_SHIFT (7U) +/*! SE - Sample Enable + * 0b0..Sampling mode is not selected. + * 0b1..Sampling mode is selected. + */ +#define CMP_CR1_SE(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_SE_SHIFT)) & CMP_CR1_SE_MASK) +/*! @} */ + +/*! @name FPR - CMP Filter Period Register */ +/*! @{ */ +#define CMP_FPR_FILT_PER_MASK (0xFFU) +#define CMP_FPR_FILT_PER_SHIFT (0U) +#define CMP_FPR_FILT_PER(x) (((uint8_t)(((uint8_t)(x)) << CMP_FPR_FILT_PER_SHIFT)) & CMP_FPR_FILT_PER_MASK) +/*! @} */ + +/*! @name SCR - CMP Status and Control Register */ +/*! @{ */ +#define CMP_SCR_COUT_MASK (0x1U) +#define CMP_SCR_COUT_SHIFT (0U) +#define CMP_SCR_COUT(x) (((uint8_t)(((uint8_t)(x)) << CMP_SCR_COUT_SHIFT)) & CMP_SCR_COUT_MASK) +#define CMP_SCR_CFF_MASK (0x2U) +#define CMP_SCR_CFF_SHIFT (1U) +/*! CFF - Analog Comparator Flag Falling + * 0b0..Falling-edge on COUT has not been detected. + * 0b1..Falling-edge on COUT has occurred. + */ +#define CMP_SCR_CFF(x) (((uint8_t)(((uint8_t)(x)) << CMP_SCR_CFF_SHIFT)) & CMP_SCR_CFF_MASK) +#define CMP_SCR_CFR_MASK (0x4U) +#define CMP_SCR_CFR_SHIFT (2U) +/*! CFR - Analog Comparator Flag Rising + * 0b0..Rising-edge on COUT has not been detected. + * 0b1..Rising-edge on COUT has occurred. + */ +#define CMP_SCR_CFR(x) (((uint8_t)(((uint8_t)(x)) << CMP_SCR_CFR_SHIFT)) & CMP_SCR_CFR_MASK) +#define CMP_SCR_IEF_MASK (0x8U) +#define CMP_SCR_IEF_SHIFT (3U) +/*! IEF - Comparator Interrupt Enable Falling + * 0b0..Interrupt is disabled. + * 0b1..Interrupt is enabled. + */ +#define CMP_SCR_IEF(x) (((uint8_t)(((uint8_t)(x)) << CMP_SCR_IEF_SHIFT)) & CMP_SCR_IEF_MASK) +#define CMP_SCR_IER_MASK (0x10U) +#define CMP_SCR_IER_SHIFT (4U) +/*! IER - Comparator Interrupt Enable Rising + * 0b0..Interrupt is disabled. + * 0b1..Interrupt is enabled. + */ +#define CMP_SCR_IER(x) (((uint8_t)(((uint8_t)(x)) << CMP_SCR_IER_SHIFT)) & CMP_SCR_IER_MASK) +#define CMP_SCR_DMAEN_MASK (0x40U) +#define CMP_SCR_DMAEN_SHIFT (6U) +/*! DMAEN - DMA Enable Control + * 0b0..DMA is disabled. + * 0b1..DMA is enabled. + */ +#define CMP_SCR_DMAEN(x) (((uint8_t)(((uint8_t)(x)) << CMP_SCR_DMAEN_SHIFT)) & CMP_SCR_DMAEN_MASK) +/*! @} */ + +/*! @name DACCR - DAC Control Register */ +/*! @{ */ +#define CMP_DACCR_VOSEL_MASK (0x3FU) +#define CMP_DACCR_VOSEL_SHIFT (0U) +#define CMP_DACCR_VOSEL(x) (((uint8_t)(((uint8_t)(x)) << CMP_DACCR_VOSEL_SHIFT)) & CMP_DACCR_VOSEL_MASK) +#define CMP_DACCR_VRSEL_MASK (0x40U) +#define CMP_DACCR_VRSEL_SHIFT (6U) +/*! VRSEL - Supply Voltage Reference Source Select + * 0b0..Vin1 is selected as resistor ladder network supply reference. + * 0b1..Vin2 is selected as resistor ladder network supply reference. + */ +#define CMP_DACCR_VRSEL(x) (((uint8_t)(((uint8_t)(x)) << CMP_DACCR_VRSEL_SHIFT)) & CMP_DACCR_VRSEL_MASK) +#define CMP_DACCR_DACEN_MASK (0x80U) +#define CMP_DACCR_DACEN_SHIFT (7U) +/*! DACEN - DAC Enable + * 0b0..DAC is disabled. + * 0b1..DAC is enabled. + */ +#define CMP_DACCR_DACEN(x) (((uint8_t)(((uint8_t)(x)) << CMP_DACCR_DACEN_SHIFT)) & CMP_DACCR_DACEN_MASK) +/*! @} */ + +/*! @name MUXCR - MUX Control Register */ +/*! @{ */ +#define CMP_MUXCR_MSEL_MASK (0x7U) +#define CMP_MUXCR_MSEL_SHIFT (0U) +/*! MSEL - Minus Input Mux Control + * 0b000..IN0 + * 0b001..IN1 + * 0b010..IN2 + * 0b011..IN3 + * 0b100..IN4 + * 0b101..IN5 + * 0b110..IN6 + * 0b111..IN7 + */ +#define CMP_MUXCR_MSEL(x) (((uint8_t)(((uint8_t)(x)) << CMP_MUXCR_MSEL_SHIFT)) & CMP_MUXCR_MSEL_MASK) +#define CMP_MUXCR_PSEL_MASK (0x38U) +#define CMP_MUXCR_PSEL_SHIFT (3U) +/*! PSEL - Plus Input Mux Control + * 0b000..IN0 + * 0b001..IN1 + * 0b010..IN2 + * 0b011..IN3 + * 0b100..IN4 + * 0b101..IN5 + * 0b110..IN6 + * 0b111..IN7 + */ +#define CMP_MUXCR_PSEL(x) (((uint8_t)(((uint8_t)(x)) << CMP_MUXCR_PSEL_SHIFT)) & CMP_MUXCR_PSEL_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group CMP_Register_Masks */ + + +/* CMP - Peripheral instance base addresses */ +/** Peripheral CMP1 base address */ +#define CMP1_BASE (0x40094000u) +/** Peripheral CMP1 base pointer */ +#define CMP1 ((CMP_Type *)CMP1_BASE) +/** Peripheral CMP2 base address */ +#define CMP2_BASE (0x40094008u) +/** Peripheral CMP2 base pointer */ +#define CMP2 ((CMP_Type *)CMP2_BASE) +/** Peripheral CMP3 base address */ +#define CMP3_BASE (0x40094010u) +/** Peripheral CMP3 base pointer */ +#define CMP3 ((CMP_Type *)CMP3_BASE) +/** Peripheral CMP4 base address */ +#define CMP4_BASE (0x40094018u) +/** Peripheral CMP4 base pointer */ +#define CMP4 ((CMP_Type *)CMP4_BASE) +/** Array initializer of CMP peripheral base addresses */ +#define CMP_BASE_ADDRS { 0u, CMP1_BASE, CMP2_BASE, CMP3_BASE, CMP4_BASE } +/** Array initializer of CMP peripheral base pointers */ +#define CMP_BASE_PTRS { (CMP_Type *)0u, CMP1, CMP2, CMP3, CMP4 } +/** Interrupt vectors for the CMP peripheral type */ +#define CMP_IRQS { NotAvail_IRQn, ACMP1_IRQn, ACMP2_IRQn, ACMP3_IRQn, ACMP4_IRQn } + +/*! + * @} + */ /* end of group CMP_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- CSI Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup CSI_Peripheral_Access_Layer CSI Peripheral Access Layer + * @{ + */ + +/** CSI - Register Layout Typedef */ +typedef struct { + __IO uint32_t CSICR1; /**< CSI Control Register 1, offset: 0x0 */ + __IO uint32_t CSICR2; /**< CSI Control Register 2, offset: 0x4 */ + __IO uint32_t CSICR3; /**< CSI Control Register 3, offset: 0x8 */ + __I uint32_t CSISTATFIFO; /**< CSI Statistic FIFO Register, offset: 0xC */ + __I uint32_t CSIRFIFO; /**< CSI RX FIFO Register, offset: 0x10 */ + __IO uint32_t CSIRXCNT; /**< CSI RX Count Register, offset: 0x14 */ + __IO uint32_t CSISR; /**< CSI Status Register, offset: 0x18 */ + uint8_t RESERVED_0[4]; + __IO uint32_t CSIDMASA_STATFIFO; /**< CSI DMA Start Address Register - for STATFIFO, offset: 0x20 */ + __IO uint32_t CSIDMATS_STATFIFO; /**< CSI DMA Transfer Size Register - for STATFIFO, offset: 0x24 */ + __IO uint32_t CSIDMASA_FB1; /**< CSI DMA Start Address Register - for Frame Buffer1, offset: 0x28 */ + __IO uint32_t CSIDMASA_FB2; /**< CSI DMA Transfer Size Register - for Frame Buffer2, offset: 0x2C */ + __IO uint32_t CSIFBUF_PARA; /**< CSI Frame Buffer Parameter Register, offset: 0x30 */ + __IO uint32_t CSIIMAG_PARA; /**< CSI Image Parameter Register, offset: 0x34 */ + uint8_t RESERVED_1[16]; + __IO uint32_t CSICR18; /**< CSI Control Register 18, offset: 0x48 */ + __IO uint32_t CSICR19; /**< CSI Control Register 19, offset: 0x4C */ +} CSI_Type; + +/* ---------------------------------------------------------------------------- + -- CSI Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup CSI_Register_Masks CSI Register Masks + * @{ + */ + +/*! @name CSICR1 - CSI Control Register 1 */ +/*! @{ */ +#define CSI_CSICR1_PIXEL_BIT_MASK (0x1U) +#define CSI_CSICR1_PIXEL_BIT_SHIFT (0U) +/*! PIXEL_BIT + * 0b0..8-bit data for each pixel + * 0b1..10-bit data for each pixel + */ +#define CSI_CSICR1_PIXEL_BIT(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_PIXEL_BIT_SHIFT)) & CSI_CSICR1_PIXEL_BIT_MASK) +#define CSI_CSICR1_REDGE_MASK (0x2U) +#define CSI_CSICR1_REDGE_SHIFT (1U) +/*! REDGE + * 0b0..Pixel data is latched at the falling edge of CSI_PIXCLK + * 0b1..Pixel data is latched at the rising edge of CSI_PIXCLK + */ +#define CSI_CSICR1_REDGE(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_REDGE_SHIFT)) & CSI_CSICR1_REDGE_MASK) +#define CSI_CSICR1_INV_PCLK_MASK (0x4U) +#define CSI_CSICR1_INV_PCLK_SHIFT (2U) +/*! INV_PCLK + * 0b0..CSI_PIXCLK is directly applied to internal circuitry + * 0b1..CSI_PIXCLK is inverted before applied to internal circuitry + */ +#define CSI_CSICR1_INV_PCLK(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_INV_PCLK_SHIFT)) & CSI_CSICR1_INV_PCLK_MASK) +#define CSI_CSICR1_INV_DATA_MASK (0x8U) +#define CSI_CSICR1_INV_DATA_SHIFT (3U) +/*! INV_DATA + * 0b0..CSI_D[7:0] data lines are directly applied to internal circuitry + * 0b1..CSI_D[7:0] data lines are inverted before applied to internal circuitry + */ +#define CSI_CSICR1_INV_DATA(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_INV_DATA_SHIFT)) & CSI_CSICR1_INV_DATA_MASK) +#define CSI_CSICR1_GCLK_MODE_MASK (0x10U) +#define CSI_CSICR1_GCLK_MODE_SHIFT (4U) +/*! GCLK_MODE + * 0b0..Non-gated clock mode. All incoming pixel clocks are valid. HSYNC is ignored. + * 0b1..Gated clock mode. Pixel clock signal is valid only when HSYNC is active. + */ +#define CSI_CSICR1_GCLK_MODE(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_GCLK_MODE_SHIFT)) & CSI_CSICR1_GCLK_MODE_MASK) +#define CSI_CSICR1_CLR_RXFIFO_MASK (0x20U) +#define CSI_CSICR1_CLR_RXFIFO_SHIFT (5U) +#define CSI_CSICR1_CLR_RXFIFO(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_CLR_RXFIFO_SHIFT)) & CSI_CSICR1_CLR_RXFIFO_MASK) +#define CSI_CSICR1_CLR_STATFIFO_MASK (0x40U) +#define CSI_CSICR1_CLR_STATFIFO_SHIFT (6U) +#define CSI_CSICR1_CLR_STATFIFO(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_CLR_STATFIFO_SHIFT)) & CSI_CSICR1_CLR_STATFIFO_MASK) +#define CSI_CSICR1_PACK_DIR_MASK (0x80U) +#define CSI_CSICR1_PACK_DIR_SHIFT (7U) +/*! PACK_DIR + * 0b0..Pack from LSB first. For image data, 0x11, 0x22, 0x33, 0x44, it will appear as 0x44332211 in RX FIFO. For stat data, 0xAAAA, 0xBBBB, it will appear as 0xBBBBAAAA in STAT FIFO. + * 0b1..Pack from MSB first. For image data, 0x11, 0x22, 0x33, 0x44, it will appear as 0x11223344 in RX FIFO. For stat data, 0xAAAA, 0xBBBB, it will appear as 0xAAAABBBB in STAT FIFO. + */ +#define CSI_CSICR1_PACK_DIR(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_PACK_DIR_SHIFT)) & CSI_CSICR1_PACK_DIR_MASK) +#define CSI_CSICR1_FCC_MASK (0x100U) +#define CSI_CSICR1_FCC_SHIFT (8U) +/*! FCC + * 0b0..Asynchronous FIFO clear is selected. + * 0b1..Synchronous FIFO clear is selected. + */ +#define CSI_CSICR1_FCC(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_FCC_SHIFT)) & CSI_CSICR1_FCC_MASK) +#define CSI_CSICR1_CCIR_EN_MASK (0x400U) +#define CSI_CSICR1_CCIR_EN_SHIFT (10U) +/*! CCIR_EN + * 0b0..Traditional interface is selected. Timing interface logic is used to latch data. + * 0b1..CCIR656 interface is selected. + */ +#define CSI_CSICR1_CCIR_EN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_CCIR_EN_SHIFT)) & CSI_CSICR1_CCIR_EN_MASK) +#define CSI_CSICR1_HSYNC_POL_MASK (0x800U) +#define CSI_CSICR1_HSYNC_POL_SHIFT (11U) +/*! HSYNC_POL + * 0b0..HSYNC is active low + * 0b1..HSYNC is active high + */ +#define CSI_CSICR1_HSYNC_POL(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_HSYNC_POL_SHIFT)) & CSI_CSICR1_HSYNC_POL_MASK) +#define CSI_CSICR1_SOF_INTEN_MASK (0x10000U) +#define CSI_CSICR1_SOF_INTEN_SHIFT (16U) +/*! SOF_INTEN + * 0b0..SOF interrupt disable + * 0b1..SOF interrupt enable + */ +#define CSI_CSICR1_SOF_INTEN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_SOF_INTEN_SHIFT)) & CSI_CSICR1_SOF_INTEN_MASK) +#define CSI_CSICR1_SOF_POL_MASK (0x20000U) +#define CSI_CSICR1_SOF_POL_SHIFT (17U) +/*! SOF_POL + * 0b0..SOF interrupt is generated on SOF falling edge + * 0b1..SOF interrupt is generated on SOF rising edge + */ +#define CSI_CSICR1_SOF_POL(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_SOF_POL_SHIFT)) & CSI_CSICR1_SOF_POL_MASK) +#define CSI_CSICR1_RXFF_INTEN_MASK (0x40000U) +#define CSI_CSICR1_RXFF_INTEN_SHIFT (18U) +/*! RXFF_INTEN + * 0b0..RxFIFO full interrupt disable + * 0b1..RxFIFO full interrupt enable + */ +#define CSI_CSICR1_RXFF_INTEN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_RXFF_INTEN_SHIFT)) & CSI_CSICR1_RXFF_INTEN_MASK) +#define CSI_CSICR1_FB1_DMA_DONE_INTEN_MASK (0x80000U) +#define CSI_CSICR1_FB1_DMA_DONE_INTEN_SHIFT (19U) +/*! FB1_DMA_DONE_INTEN + * 0b0..Frame Buffer1 DMA Transfer Done interrupt disable + * 0b1..Frame Buffer1 DMA Transfer Done interrupt enable + */ +#define CSI_CSICR1_FB1_DMA_DONE_INTEN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_FB1_DMA_DONE_INTEN_SHIFT)) & CSI_CSICR1_FB1_DMA_DONE_INTEN_MASK) +#define CSI_CSICR1_FB2_DMA_DONE_INTEN_MASK (0x100000U) +#define CSI_CSICR1_FB2_DMA_DONE_INTEN_SHIFT (20U) +/*! FB2_DMA_DONE_INTEN + * 0b0..Frame Buffer2 DMA Transfer Done interrupt disable + * 0b1..Frame Buffer2 DMA Transfer Done interrupt enable + */ +#define CSI_CSICR1_FB2_DMA_DONE_INTEN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_FB2_DMA_DONE_INTEN_SHIFT)) & CSI_CSICR1_FB2_DMA_DONE_INTEN_MASK) +#define CSI_CSICR1_STATFF_INTEN_MASK (0x200000U) +#define CSI_CSICR1_STATFF_INTEN_SHIFT (21U) +/*! STATFF_INTEN + * 0b0..STATFIFO full interrupt disable + * 0b1..STATFIFO full interrupt enable + */ +#define CSI_CSICR1_STATFF_INTEN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_STATFF_INTEN_SHIFT)) & CSI_CSICR1_STATFF_INTEN_MASK) +#define CSI_CSICR1_SFF_DMA_DONE_INTEN_MASK (0x400000U) +#define CSI_CSICR1_SFF_DMA_DONE_INTEN_SHIFT (22U) +/*! SFF_DMA_DONE_INTEN + * 0b0..STATFIFO DMA Transfer Done interrupt disable + * 0b1..STATFIFO DMA Transfer Done interrupt enable + */ +#define CSI_CSICR1_SFF_DMA_DONE_INTEN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_SFF_DMA_DONE_INTEN_SHIFT)) & CSI_CSICR1_SFF_DMA_DONE_INTEN_MASK) +#define CSI_CSICR1_RF_OR_INTEN_MASK (0x1000000U) +#define CSI_CSICR1_RF_OR_INTEN_SHIFT (24U) +/*! RF_OR_INTEN + * 0b0..RxFIFO overrun interrupt is disabled + * 0b1..RxFIFO overrun interrupt is enabled + */ +#define CSI_CSICR1_RF_OR_INTEN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_RF_OR_INTEN_SHIFT)) & CSI_CSICR1_RF_OR_INTEN_MASK) +#define CSI_CSICR1_SF_OR_INTEN_MASK (0x2000000U) +#define CSI_CSICR1_SF_OR_INTEN_SHIFT (25U) +/*! SF_OR_INTEN + * 0b0..STATFIFO overrun interrupt is disabled + * 0b1..STATFIFO overrun interrupt is enabled + */ +#define CSI_CSICR1_SF_OR_INTEN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_SF_OR_INTEN_SHIFT)) & CSI_CSICR1_SF_OR_INTEN_MASK) +#define CSI_CSICR1_COF_INT_EN_MASK (0x4000000U) +#define CSI_CSICR1_COF_INT_EN_SHIFT (26U) +/*! COF_INT_EN + * 0b0..COF interrupt is disabled + * 0b1..COF interrupt is enabled + */ +#define CSI_CSICR1_COF_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_COF_INT_EN_SHIFT)) & CSI_CSICR1_COF_INT_EN_MASK) +#define CSI_CSICR1_CCIR_MODE_MASK (0x8000000U) +#define CSI_CSICR1_CCIR_MODE_SHIFT (27U) +/*! CCIR_MODE + * 0b0..Progressive mode is selected + * 0b1..Interlace mode is selected + */ +#define CSI_CSICR1_CCIR_MODE(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_CCIR_MODE_SHIFT)) & CSI_CSICR1_CCIR_MODE_MASK) +#define CSI_CSICR1_PrP_IF_EN_MASK (0x10000000U) +#define CSI_CSICR1_PrP_IF_EN_SHIFT (28U) +/*! PrP_IF_EN + * 0b0..CSI to PrP bus is disabled + * 0b1..CSI to PrP bus is enabled + */ +#define CSI_CSICR1_PrP_IF_EN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_PrP_IF_EN_SHIFT)) & CSI_CSICR1_PrP_IF_EN_MASK) +#define CSI_CSICR1_EOF_INT_EN_MASK (0x20000000U) +#define CSI_CSICR1_EOF_INT_EN_SHIFT (29U) +/*! EOF_INT_EN + * 0b0..EOF interrupt is disabled. + * 0b1..EOF interrupt is generated when RX count value is reached. + */ +#define CSI_CSICR1_EOF_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_EOF_INT_EN_SHIFT)) & CSI_CSICR1_EOF_INT_EN_MASK) +#define CSI_CSICR1_EXT_VSYNC_MASK (0x40000000U) +#define CSI_CSICR1_EXT_VSYNC_SHIFT (30U) +/*! EXT_VSYNC + * 0b0..Internal VSYNC mode + * 0b1..External VSYNC mode + */ +#define CSI_CSICR1_EXT_VSYNC(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_EXT_VSYNC_SHIFT)) & CSI_CSICR1_EXT_VSYNC_MASK) +#define CSI_CSICR1_SWAP16_EN_MASK (0x80000000U) +#define CSI_CSICR1_SWAP16_EN_SHIFT (31U) +/*! SWAP16_EN + * 0b0..Disable swapping + * 0b1..Enable swapping + */ +#define CSI_CSICR1_SWAP16_EN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_SWAP16_EN_SHIFT)) & CSI_CSICR1_SWAP16_EN_MASK) +/*! @} */ + +/*! @name CSICR2 - CSI Control Register 2 */ +/*! @{ */ +#define CSI_CSICR2_HSC_MASK (0xFFU) +#define CSI_CSICR2_HSC_SHIFT (0U) +#define CSI_CSICR2_HSC(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR2_HSC_SHIFT)) & CSI_CSICR2_HSC_MASK) +#define CSI_CSICR2_VSC_MASK (0xFF00U) +#define CSI_CSICR2_VSC_SHIFT (8U) +#define CSI_CSICR2_VSC(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR2_VSC_SHIFT)) & CSI_CSICR2_VSC_MASK) +#define CSI_CSICR2_LVRM_MASK (0x70000U) +#define CSI_CSICR2_LVRM_SHIFT (16U) +/*! LVRM + * 0b000..512 x 384 + * 0b001..448 x 336 + * 0b010..384 x 288 + * 0b011..384 x 256 + * 0b100..320 x 240 + * 0b101..288 x 216 + * 0b110..400 x 300 + */ +#define CSI_CSICR2_LVRM(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR2_LVRM_SHIFT)) & CSI_CSICR2_LVRM_MASK) +#define CSI_CSICR2_BTS_MASK (0x180000U) +#define CSI_CSICR2_BTS_SHIFT (19U) +/*! BTS + * 0b00..GR + * 0b01..RG + * 0b10..BG + * 0b11..GB + */ +#define CSI_CSICR2_BTS(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR2_BTS_SHIFT)) & CSI_CSICR2_BTS_MASK) +#define CSI_CSICR2_SCE_MASK (0x800000U) +#define CSI_CSICR2_SCE_SHIFT (23U) +/*! SCE + * 0b0..Skip count disable + * 0b1..Skip count enable + */ +#define CSI_CSICR2_SCE(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR2_SCE_SHIFT)) & CSI_CSICR2_SCE_MASK) +#define CSI_CSICR2_AFS_MASK (0x3000000U) +#define CSI_CSICR2_AFS_SHIFT (24U) +/*! AFS + * 0b00..Abs Diff on consecutive green pixels + * 0b01..Abs Diff on every third green pixels + * 0b1x..Abs Diff on every four green pixels + */ +#define CSI_CSICR2_AFS(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR2_AFS_SHIFT)) & CSI_CSICR2_AFS_MASK) +#define CSI_CSICR2_DRM_MASK (0x4000000U) +#define CSI_CSICR2_DRM_SHIFT (26U) +/*! DRM + * 0b0..Stats grid of 8 x 6 + * 0b1..Stats grid of 8 x 12 + */ +#define CSI_CSICR2_DRM(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR2_DRM_SHIFT)) & CSI_CSICR2_DRM_MASK) +#define CSI_CSICR2_DMA_BURST_TYPE_SFF_MASK (0x30000000U) +#define CSI_CSICR2_DMA_BURST_TYPE_SFF_SHIFT (28U) +/*! DMA_BURST_TYPE_SFF + * 0bx0..INCR8 + * 0b01..INCR4 + * 0b11..INCR16 + */ +#define CSI_CSICR2_DMA_BURST_TYPE_SFF(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR2_DMA_BURST_TYPE_SFF_SHIFT)) & CSI_CSICR2_DMA_BURST_TYPE_SFF_MASK) +#define CSI_CSICR2_DMA_BURST_TYPE_RFF_MASK (0xC0000000U) +#define CSI_CSICR2_DMA_BURST_TYPE_RFF_SHIFT (30U) +/*! DMA_BURST_TYPE_RFF + * 0bx0..INCR8 + * 0b01..INCR4 + * 0b11..INCR16 + */ +#define CSI_CSICR2_DMA_BURST_TYPE_RFF(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR2_DMA_BURST_TYPE_RFF_SHIFT)) & CSI_CSICR2_DMA_BURST_TYPE_RFF_MASK) +/*! @} */ + +/*! @name CSICR3 - CSI Control Register 3 */ +/*! @{ */ +#define CSI_CSICR3_ECC_AUTO_EN_MASK (0x1U) +#define CSI_CSICR3_ECC_AUTO_EN_SHIFT (0U) +/*! ECC_AUTO_EN + * 0b0..Auto Error correction is disabled. + * 0b1..Auto Error correction is enabled. + */ +#define CSI_CSICR3_ECC_AUTO_EN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR3_ECC_AUTO_EN_SHIFT)) & CSI_CSICR3_ECC_AUTO_EN_MASK) +#define CSI_CSICR3_ECC_INT_EN_MASK (0x2U) +#define CSI_CSICR3_ECC_INT_EN_SHIFT (1U) +/*! ECC_INT_EN + * 0b0..No interrupt is generated when error is detected. Only the status bit ECC_INT is set. + * 0b1..Interrupt is generated when error is detected. + */ +#define CSI_CSICR3_ECC_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR3_ECC_INT_EN_SHIFT)) & CSI_CSICR3_ECC_INT_EN_MASK) +#define CSI_CSICR3_ZERO_PACK_EN_MASK (0x4U) +#define CSI_CSICR3_ZERO_PACK_EN_SHIFT (2U) +/*! ZERO_PACK_EN + * 0b0..Zero packing disabled + * 0b1..Zero packing enabled + */ +#define CSI_CSICR3_ZERO_PACK_EN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR3_ZERO_PACK_EN_SHIFT)) & CSI_CSICR3_ZERO_PACK_EN_MASK) +#define CSI_CSICR3_TWO_8BIT_SENSOR_MASK (0x8U) +#define CSI_CSICR3_TWO_8BIT_SENSOR_SHIFT (3U) +/*! TWO_8BIT_SENSOR + * 0b0..Only one sensor is connected. + * 0b1..Two 8-bit sensors are connected or one 16-bit sensor is connected. + */ +#define CSI_CSICR3_TWO_8BIT_SENSOR(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR3_TWO_8BIT_SENSOR_SHIFT)) & CSI_CSICR3_TWO_8BIT_SENSOR_MASK) +#define CSI_CSICR3_RxFF_LEVEL_MASK (0x70U) +#define CSI_CSICR3_RxFF_LEVEL_SHIFT (4U) +/*! RxFF_LEVEL + * 0b000..4 Double words + * 0b001..8 Double words + * 0b010..16 Double words + * 0b011..24 Double words + * 0b100..32 Double words + * 0b101..48 Double words + * 0b110..64 Double words + * 0b111..96 Double words + */ +#define CSI_CSICR3_RxFF_LEVEL(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR3_RxFF_LEVEL_SHIFT)) & CSI_CSICR3_RxFF_LEVEL_MASK) +#define CSI_CSICR3_HRESP_ERR_EN_MASK (0x80U) +#define CSI_CSICR3_HRESP_ERR_EN_SHIFT (7U) +/*! HRESP_ERR_EN + * 0b0..Disable hresponse error interrupt + * 0b1..Enable hresponse error interrupt + */ +#define CSI_CSICR3_HRESP_ERR_EN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR3_HRESP_ERR_EN_SHIFT)) & CSI_CSICR3_HRESP_ERR_EN_MASK) +#define CSI_CSICR3_STATFF_LEVEL_MASK (0x700U) +#define CSI_CSICR3_STATFF_LEVEL_SHIFT (8U) +/*! STATFF_LEVEL + * 0b000..4 Double words + * 0b001..8 Double words + * 0b010..12 Double words + * 0b011..16 Double words + * 0b100..24 Double words + * 0b101..32 Double words + * 0b110..48 Double words + * 0b111..64 Double words + */ +#define CSI_CSICR3_STATFF_LEVEL(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR3_STATFF_LEVEL_SHIFT)) & CSI_CSICR3_STATFF_LEVEL_MASK) +#define CSI_CSICR3_DMA_REQ_EN_SFF_MASK (0x800U) +#define CSI_CSICR3_DMA_REQ_EN_SFF_SHIFT (11U) +/*! DMA_REQ_EN_SFF + * 0b0..Disable the dma request + * 0b1..Enable the dma request + */ +#define CSI_CSICR3_DMA_REQ_EN_SFF(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR3_DMA_REQ_EN_SFF_SHIFT)) & CSI_CSICR3_DMA_REQ_EN_SFF_MASK) +#define CSI_CSICR3_DMA_REQ_EN_RFF_MASK (0x1000U) +#define CSI_CSICR3_DMA_REQ_EN_RFF_SHIFT (12U) +/*! DMA_REQ_EN_RFF + * 0b0..Disable the dma request + * 0b1..Enable the dma request + */ +#define CSI_CSICR3_DMA_REQ_EN_RFF(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR3_DMA_REQ_EN_RFF_SHIFT)) & CSI_CSICR3_DMA_REQ_EN_RFF_MASK) +#define CSI_CSICR3_DMA_REFLASH_SFF_MASK (0x2000U) +#define CSI_CSICR3_DMA_REFLASH_SFF_SHIFT (13U) +/*! DMA_REFLASH_SFF + * 0b0..No reflashing + * 0b1..Reflash the embedded DMA controller + */ +#define CSI_CSICR3_DMA_REFLASH_SFF(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR3_DMA_REFLASH_SFF_SHIFT)) & CSI_CSICR3_DMA_REFLASH_SFF_MASK) +#define CSI_CSICR3_DMA_REFLASH_RFF_MASK (0x4000U) +#define CSI_CSICR3_DMA_REFLASH_RFF_SHIFT (14U) +/*! DMA_REFLASH_RFF + * 0b0..No reflashing + * 0b1..Reflash the embedded DMA controller + */ +#define CSI_CSICR3_DMA_REFLASH_RFF(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR3_DMA_REFLASH_RFF_SHIFT)) & CSI_CSICR3_DMA_REFLASH_RFF_MASK) +#define CSI_CSICR3_FRMCNT_RST_MASK (0x8000U) +#define CSI_CSICR3_FRMCNT_RST_SHIFT (15U) +/*! FRMCNT_RST + * 0b0..Do not reset + * 0b1..Reset frame counter immediately + */ +#define CSI_CSICR3_FRMCNT_RST(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR3_FRMCNT_RST_SHIFT)) & CSI_CSICR3_FRMCNT_RST_MASK) +#define CSI_CSICR3_FRMCNT_MASK (0xFFFF0000U) +#define CSI_CSICR3_FRMCNT_SHIFT (16U) +#define CSI_CSICR3_FRMCNT(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR3_FRMCNT_SHIFT)) & CSI_CSICR3_FRMCNT_MASK) +/*! @} */ + +/*! @name CSISTATFIFO - CSI Statistic FIFO Register */ +/*! @{ */ +#define CSI_CSISTATFIFO_STAT_MASK (0xFFFFFFFFU) +#define CSI_CSISTATFIFO_STAT_SHIFT (0U) +#define CSI_CSISTATFIFO_STAT(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSISTATFIFO_STAT_SHIFT)) & CSI_CSISTATFIFO_STAT_MASK) +/*! @} */ + +/*! @name CSIRFIFO - CSI RX FIFO Register */ +/*! @{ */ +#define CSI_CSIRFIFO_IMAGE_MASK (0xFFFFFFFFU) +#define CSI_CSIRFIFO_IMAGE_SHIFT (0U) +#define CSI_CSIRFIFO_IMAGE(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSIRFIFO_IMAGE_SHIFT)) & CSI_CSIRFIFO_IMAGE_MASK) +/*! @} */ + +/*! @name CSIRXCNT - CSI RX Count Register */ +/*! @{ */ +#define CSI_CSIRXCNT_RXCNT_MASK (0x3FFFFFU) +#define CSI_CSIRXCNT_RXCNT_SHIFT (0U) +#define CSI_CSIRXCNT_RXCNT(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSIRXCNT_RXCNT_SHIFT)) & CSI_CSIRXCNT_RXCNT_MASK) +/*! @} */ + +/*! @name CSISR - CSI Status Register */ +/*! @{ */ +#define CSI_CSISR_DRDY_MASK (0x1U) +#define CSI_CSISR_DRDY_SHIFT (0U) +/*! DRDY + * 0b0..No data (word) is ready + * 0b1..At least 1 datum (word) is ready in RXFIFO. + */ +#define CSI_CSISR_DRDY(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSISR_DRDY_SHIFT)) & CSI_CSISR_DRDY_MASK) +#define CSI_CSISR_ECC_INT_MASK (0x2U) +#define CSI_CSISR_ECC_INT_SHIFT (1U) +/*! ECC_INT + * 0b0..No error detected + * 0b1..Error is detected in CCIR coding + */ +#define CSI_CSISR_ECC_INT(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSISR_ECC_INT_SHIFT)) & CSI_CSISR_ECC_INT_MASK) +#define CSI_CSISR_HRESP_ERR_INT_MASK (0x80U) +#define CSI_CSISR_HRESP_ERR_INT_SHIFT (7U) +/*! HRESP_ERR_INT + * 0b0..No hresponse error. + * 0b1..Hresponse error is detected. + */ +#define CSI_CSISR_HRESP_ERR_INT(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSISR_HRESP_ERR_INT_SHIFT)) & CSI_CSISR_HRESP_ERR_INT_MASK) +#define CSI_CSISR_COF_INT_MASK (0x2000U) +#define CSI_CSISR_COF_INT_SHIFT (13U) +/*! COF_INT + * 0b0..Video field has no change. + * 0b1..Change of video field is detected. + */ +#define CSI_CSISR_COF_INT(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSISR_COF_INT_SHIFT)) & CSI_CSISR_COF_INT_MASK) +#define CSI_CSISR_F1_INT_MASK (0x4000U) +#define CSI_CSISR_F1_INT_SHIFT (14U) +/*! F1_INT + * 0b0..Field 1 of video is not detected. + * 0b1..Field 1 of video is about to start. + */ +#define CSI_CSISR_F1_INT(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSISR_F1_INT_SHIFT)) & CSI_CSISR_F1_INT_MASK) +#define CSI_CSISR_F2_INT_MASK (0x8000U) +#define CSI_CSISR_F2_INT_SHIFT (15U) +/*! F2_INT + * 0b0..Field 2 of video is not detected + * 0b1..Field 2 of video is about to start + */ +#define CSI_CSISR_F2_INT(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSISR_F2_INT_SHIFT)) & CSI_CSISR_F2_INT_MASK) +#define CSI_CSISR_SOF_INT_MASK (0x10000U) +#define CSI_CSISR_SOF_INT_SHIFT (16U) +/*! SOF_INT + * 0b0..SOF is not detected. + * 0b1..SOF is detected. + */ +#define CSI_CSISR_SOF_INT(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSISR_SOF_INT_SHIFT)) & CSI_CSISR_SOF_INT_MASK) +#define CSI_CSISR_EOF_INT_MASK (0x20000U) +#define CSI_CSISR_EOF_INT_SHIFT (17U) +/*! EOF_INT + * 0b0..EOF is not detected. + * 0b1..EOF is detected. + */ +#define CSI_CSISR_EOF_INT(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSISR_EOF_INT_SHIFT)) & CSI_CSISR_EOF_INT_MASK) +#define CSI_CSISR_RxFF_INT_MASK (0x40000U) +#define CSI_CSISR_RxFF_INT_SHIFT (18U) +/*! RxFF_INT + * 0b0..RxFIFO is not full. + * 0b1..RxFIFO is full. + */ +#define CSI_CSISR_RxFF_INT(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSISR_RxFF_INT_SHIFT)) & CSI_CSISR_RxFF_INT_MASK) +#define CSI_CSISR_DMA_TSF_DONE_FB1_MASK (0x80000U) +#define CSI_CSISR_DMA_TSF_DONE_FB1_SHIFT (19U) +/*! DMA_TSF_DONE_FB1 + * 0b0..DMA transfer is not completed. + * 0b1..DMA transfer is completed. + */ +#define CSI_CSISR_DMA_TSF_DONE_FB1(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSISR_DMA_TSF_DONE_FB1_SHIFT)) & CSI_CSISR_DMA_TSF_DONE_FB1_MASK) +#define CSI_CSISR_DMA_TSF_DONE_FB2_MASK (0x100000U) +#define CSI_CSISR_DMA_TSF_DONE_FB2_SHIFT (20U) +/*! DMA_TSF_DONE_FB2 + * 0b0..DMA transfer is not completed. + * 0b1..DMA transfer is completed. + */ +#define CSI_CSISR_DMA_TSF_DONE_FB2(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSISR_DMA_TSF_DONE_FB2_SHIFT)) & CSI_CSISR_DMA_TSF_DONE_FB2_MASK) +#define CSI_CSISR_STATFF_INT_MASK (0x200000U) +#define CSI_CSISR_STATFF_INT_SHIFT (21U) +/*! STATFF_INT + * 0b0..STATFIFO is not full. + * 0b1..STATFIFO is full. + */ +#define CSI_CSISR_STATFF_INT(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSISR_STATFF_INT_SHIFT)) & CSI_CSISR_STATFF_INT_MASK) +#define CSI_CSISR_DMA_TSF_DONE_SFF_MASK (0x400000U) +#define CSI_CSISR_DMA_TSF_DONE_SFF_SHIFT (22U) +/*! DMA_TSF_DONE_SFF + * 0b0..DMA transfer is not completed. + * 0b1..DMA transfer is completed. + */ +#define CSI_CSISR_DMA_TSF_DONE_SFF(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSISR_DMA_TSF_DONE_SFF_SHIFT)) & CSI_CSISR_DMA_TSF_DONE_SFF_MASK) +#define CSI_CSISR_RF_OR_INT_MASK (0x1000000U) +#define CSI_CSISR_RF_OR_INT_SHIFT (24U) +/*! RF_OR_INT + * 0b0..RXFIFO has not overflowed. + * 0b1..RXFIFO has overflowed. + */ +#define CSI_CSISR_RF_OR_INT(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSISR_RF_OR_INT_SHIFT)) & CSI_CSISR_RF_OR_INT_MASK) +#define CSI_CSISR_SF_OR_INT_MASK (0x2000000U) +#define CSI_CSISR_SF_OR_INT_SHIFT (25U) +/*! SF_OR_INT + * 0b0..STATFIFO has not overflowed. + * 0b1..STATFIFO has overflowed. + */ +#define CSI_CSISR_SF_OR_INT(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSISR_SF_OR_INT_SHIFT)) & CSI_CSISR_SF_OR_INT_MASK) +#define CSI_CSISR_DMA_FIELD1_DONE_MASK (0x4000000U) +#define CSI_CSISR_DMA_FIELD1_DONE_SHIFT (26U) +#define CSI_CSISR_DMA_FIELD1_DONE(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSISR_DMA_FIELD1_DONE_SHIFT)) & CSI_CSISR_DMA_FIELD1_DONE_MASK) +#define CSI_CSISR_DMA_FIELD0_DONE_MASK (0x8000000U) +#define CSI_CSISR_DMA_FIELD0_DONE_SHIFT (27U) +#define CSI_CSISR_DMA_FIELD0_DONE(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSISR_DMA_FIELD0_DONE_SHIFT)) & CSI_CSISR_DMA_FIELD0_DONE_MASK) +#define CSI_CSISR_BASEADDR_CHHANGE_ERROR_MASK (0x10000000U) +#define CSI_CSISR_BASEADDR_CHHANGE_ERROR_SHIFT (28U) +#define CSI_CSISR_BASEADDR_CHHANGE_ERROR(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSISR_BASEADDR_CHHANGE_ERROR_SHIFT)) & CSI_CSISR_BASEADDR_CHHANGE_ERROR_MASK) +/*! @} */ + +/*! @name CSIDMASA_STATFIFO - CSI DMA Start Address Register - for STATFIFO */ +/*! @{ */ +#define CSI_CSIDMASA_STATFIFO_DMA_START_ADDR_SFF_MASK (0xFFFFFFFCU) +#define CSI_CSIDMASA_STATFIFO_DMA_START_ADDR_SFF_SHIFT (2U) +#define CSI_CSIDMASA_STATFIFO_DMA_START_ADDR_SFF(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSIDMASA_STATFIFO_DMA_START_ADDR_SFF_SHIFT)) & CSI_CSIDMASA_STATFIFO_DMA_START_ADDR_SFF_MASK) +/*! @} */ + +/*! @name CSIDMATS_STATFIFO - CSI DMA Transfer Size Register - for STATFIFO */ +/*! @{ */ +#define CSI_CSIDMATS_STATFIFO_DMA_TSF_SIZE_SFF_MASK (0xFFFFFFFFU) +#define CSI_CSIDMATS_STATFIFO_DMA_TSF_SIZE_SFF_SHIFT (0U) +#define CSI_CSIDMATS_STATFIFO_DMA_TSF_SIZE_SFF(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSIDMATS_STATFIFO_DMA_TSF_SIZE_SFF_SHIFT)) & CSI_CSIDMATS_STATFIFO_DMA_TSF_SIZE_SFF_MASK) +/*! @} */ + +/*! @name CSIDMASA_FB1 - CSI DMA Start Address Register - for Frame Buffer1 */ +/*! @{ */ +#define CSI_CSIDMASA_FB1_DMA_START_ADDR_FB1_MASK (0xFFFFFFFCU) +#define CSI_CSIDMASA_FB1_DMA_START_ADDR_FB1_SHIFT (2U) +#define CSI_CSIDMASA_FB1_DMA_START_ADDR_FB1(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSIDMASA_FB1_DMA_START_ADDR_FB1_SHIFT)) & CSI_CSIDMASA_FB1_DMA_START_ADDR_FB1_MASK) +/*! @} */ + +/*! @name CSIDMASA_FB2 - CSI DMA Transfer Size Register - for Frame Buffer2 */ +/*! @{ */ +#define CSI_CSIDMASA_FB2_DMA_START_ADDR_FB2_MASK (0xFFFFFFFCU) +#define CSI_CSIDMASA_FB2_DMA_START_ADDR_FB2_SHIFT (2U) +#define CSI_CSIDMASA_FB2_DMA_START_ADDR_FB2(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSIDMASA_FB2_DMA_START_ADDR_FB2_SHIFT)) & CSI_CSIDMASA_FB2_DMA_START_ADDR_FB2_MASK) +/*! @} */ + +/*! @name CSIFBUF_PARA - CSI Frame Buffer Parameter Register */ +/*! @{ */ +#define CSI_CSIFBUF_PARA_FBUF_STRIDE_MASK (0xFFFFU) +#define CSI_CSIFBUF_PARA_FBUF_STRIDE_SHIFT (0U) +#define CSI_CSIFBUF_PARA_FBUF_STRIDE(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSIFBUF_PARA_FBUF_STRIDE_SHIFT)) & CSI_CSIFBUF_PARA_FBUF_STRIDE_MASK) +#define CSI_CSIFBUF_PARA_DEINTERLACE_STRIDE_MASK (0xFFFF0000U) +#define CSI_CSIFBUF_PARA_DEINTERLACE_STRIDE_SHIFT (16U) +#define CSI_CSIFBUF_PARA_DEINTERLACE_STRIDE(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSIFBUF_PARA_DEINTERLACE_STRIDE_SHIFT)) & CSI_CSIFBUF_PARA_DEINTERLACE_STRIDE_MASK) +/*! @} */ + +/*! @name CSIIMAG_PARA - CSI Image Parameter Register */ +/*! @{ */ +#define CSI_CSIIMAG_PARA_IMAGE_HEIGHT_MASK (0xFFFFU) +#define CSI_CSIIMAG_PARA_IMAGE_HEIGHT_SHIFT (0U) +#define CSI_CSIIMAG_PARA_IMAGE_HEIGHT(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSIIMAG_PARA_IMAGE_HEIGHT_SHIFT)) & CSI_CSIIMAG_PARA_IMAGE_HEIGHT_MASK) +#define CSI_CSIIMAG_PARA_IMAGE_WIDTH_MASK (0xFFFF0000U) +#define CSI_CSIIMAG_PARA_IMAGE_WIDTH_SHIFT (16U) +#define CSI_CSIIMAG_PARA_IMAGE_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSIIMAG_PARA_IMAGE_WIDTH_SHIFT)) & CSI_CSIIMAG_PARA_IMAGE_WIDTH_MASK) +/*! @} */ + +/*! @name CSICR18 - CSI Control Register 18 */ +/*! @{ */ +#define CSI_CSICR18_DEINTERLACE_EN_MASK (0x4U) +#define CSI_CSICR18_DEINTERLACE_EN_SHIFT (2U) +/*! DEINTERLACE_EN + * 0b0..Deinterlace disabled + * 0b1..Deinterlace enabled + */ +#define CSI_CSICR18_DEINTERLACE_EN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR18_DEINTERLACE_EN_SHIFT)) & CSI_CSICR18_DEINTERLACE_EN_MASK) +#define CSI_CSICR18_PARALLEL24_EN_MASK (0x8U) +#define CSI_CSICR18_PARALLEL24_EN_SHIFT (3U) +#define CSI_CSICR18_PARALLEL24_EN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR18_PARALLEL24_EN_SHIFT)) & CSI_CSICR18_PARALLEL24_EN_MASK) +#define CSI_CSICR18_BASEADDR_SWITCH_EN_MASK (0x10U) +#define CSI_CSICR18_BASEADDR_SWITCH_EN_SHIFT (4U) +#define CSI_CSICR18_BASEADDR_SWITCH_EN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR18_BASEADDR_SWITCH_EN_SHIFT)) & CSI_CSICR18_BASEADDR_SWITCH_EN_MASK) +#define CSI_CSICR18_BASEADDR_SWITCH_SEL_MASK (0x20U) +#define CSI_CSICR18_BASEADDR_SWITCH_SEL_SHIFT (5U) +/*! BASEADDR_SWITCH_SEL + * 0b0..Switching base address at the edge of the vsync + * 0b1..Switching base address at the edge of the first data of each frame + */ +#define CSI_CSICR18_BASEADDR_SWITCH_SEL(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR18_BASEADDR_SWITCH_SEL_SHIFT)) & CSI_CSICR18_BASEADDR_SWITCH_SEL_MASK) +#define CSI_CSICR18_FIELD0_DONE_IE_MASK (0x40U) +#define CSI_CSICR18_FIELD0_DONE_IE_SHIFT (6U) +/*! FIELD0_DONE_IE + * 0b0..Interrupt disabled + * 0b1..Interrupt enabled + */ +#define CSI_CSICR18_FIELD0_DONE_IE(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR18_FIELD0_DONE_IE_SHIFT)) & CSI_CSICR18_FIELD0_DONE_IE_MASK) +#define CSI_CSICR18_DMA_FIELD1_DONE_IE_MASK (0x80U) +#define CSI_CSICR18_DMA_FIELD1_DONE_IE_SHIFT (7U) +/*! DMA_FIELD1_DONE_IE + * 0b0..Interrupt disabled + * 0b1..Interrupt enabled + */ +#define CSI_CSICR18_DMA_FIELD1_DONE_IE(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR18_DMA_FIELD1_DONE_IE_SHIFT)) & CSI_CSICR18_DMA_FIELD1_DONE_IE_MASK) +#define CSI_CSICR18_LAST_DMA_REQ_SEL_MASK (0x100U) +#define CSI_CSICR18_LAST_DMA_REQ_SEL_SHIFT (8U) +/*! LAST_DMA_REQ_SEL + * 0b0..fifo_full_level + * 0b1..hburst_length + */ +#define CSI_CSICR18_LAST_DMA_REQ_SEL(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR18_LAST_DMA_REQ_SEL_SHIFT)) & CSI_CSICR18_LAST_DMA_REQ_SEL_MASK) +#define CSI_CSICR18_BASEADDR_CHANGE_ERROR_IE_MASK (0x200U) +#define CSI_CSICR18_BASEADDR_CHANGE_ERROR_IE_SHIFT (9U) +#define CSI_CSICR18_BASEADDR_CHANGE_ERROR_IE(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR18_BASEADDR_CHANGE_ERROR_IE_SHIFT)) & CSI_CSICR18_BASEADDR_CHANGE_ERROR_IE_MASK) +#define CSI_CSICR18_RGB888A_FORMAT_SEL_MASK (0x400U) +#define CSI_CSICR18_RGB888A_FORMAT_SEL_SHIFT (10U) +/*! RGB888A_FORMAT_SEL + * 0b0..{8'h0, data[23:0]} + * 0b1..{data[23:0], 8'h0} + */ +#define CSI_CSICR18_RGB888A_FORMAT_SEL(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR18_RGB888A_FORMAT_SEL_SHIFT)) & CSI_CSICR18_RGB888A_FORMAT_SEL_MASK) +#define CSI_CSICR18_AHB_HPROT_MASK (0xF000U) +#define CSI_CSICR18_AHB_HPROT_SHIFT (12U) +#define CSI_CSICR18_AHB_HPROT(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR18_AHB_HPROT_SHIFT)) & CSI_CSICR18_AHB_HPROT_MASK) +#define CSI_CSICR18_MASK_OPTION_MASK (0xC0000U) +#define CSI_CSICR18_MASK_OPTION_SHIFT (18U) +/*! MASK_OPTION + * 0b00..Writing to memory from first completely frame, when using this option, the CSI_ENABLE should be 1. + * 0b01..Writing to memory when CSI_ENABLE is 1. + * 0b10..Writing to memory from second completely frame, when using this option, the CSI_ENABLE should be 1. + * 0b11..Writing to memory when data comes in, not matter the CSI_ENABLE is 1 or 0. + */ +#define CSI_CSICR18_MASK_OPTION(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR18_MASK_OPTION_SHIFT)) & CSI_CSICR18_MASK_OPTION_MASK) +#define CSI_CSICR18_CSI_ENABLE_MASK (0x80000000U) +#define CSI_CSICR18_CSI_ENABLE_SHIFT (31U) +#define CSI_CSICR18_CSI_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR18_CSI_ENABLE_SHIFT)) & CSI_CSICR18_CSI_ENABLE_MASK) +/*! @} */ + +/*! @name CSICR19 - CSI Control Register 19 */ +/*! @{ */ +#define CSI_CSICR19_DMA_RFIFO_HIGHEST_FIFO_LEVEL_MASK (0xFFU) +#define CSI_CSICR19_DMA_RFIFO_HIGHEST_FIFO_LEVEL_SHIFT (0U) +#define CSI_CSICR19_DMA_RFIFO_HIGHEST_FIFO_LEVEL(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR19_DMA_RFIFO_HIGHEST_FIFO_LEVEL_SHIFT)) & CSI_CSICR19_DMA_RFIFO_HIGHEST_FIFO_LEVEL_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group CSI_Register_Masks */ + + +/* CSI - Peripheral instance base addresses */ +/** Peripheral CSI base address */ +#define CSI_BASE (0x402BC000u) +/** Peripheral CSI base pointer */ +#define CSI ((CSI_Type *)CSI_BASE) +/** Array initializer of CSI peripheral base addresses */ +#define CSI_BASE_ADDRS { CSI_BASE } +/** Array initializer of CSI peripheral base pointers */ +#define CSI_BASE_PTRS { CSI } +/** Interrupt vectors for the CSI peripheral type */ +#define CSI_IRQS { CSI_IRQn } + +/*! + * @} + */ /* end of group CSI_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- CSU Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup CSU_Peripheral_Access_Layer CSU Peripheral Access Layer + * @{ + */ + +/** CSU - Register Layout Typedef */ +typedef struct { + __IO uint32_t CSL[32]; /**< Config security level register, array offset: 0x0, array step: 0x4 */ + uint8_t RESERVED_0[384]; + __IO uint32_t HP0; /**< HP0 register, offset: 0x200 */ + uint8_t RESERVED_1[20]; + __IO uint32_t SA; /**< Secure access register, offset: 0x218 */ + uint8_t RESERVED_2[316]; + __IO uint32_t HPCONTROL0; /**< HPCONTROL0 register, offset: 0x358 */ +} CSU_Type; + +/* ---------------------------------------------------------------------------- + -- CSU Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup CSU_Register_Masks CSU Register Masks + * @{ + */ + +/*! @name CSL - Config security level register */ +/*! @{ */ +#define CSU_CSL_SUR_S2_MASK (0x1U) +#define CSU_CSL_SUR_S2_SHIFT (0U) +/*! SUR_S2 + * 0b0..The secure user read access is disabled for the second slave. + * 0b1..The secure user read access is enabled for the second slave. + */ +#define CSU_CSL_SUR_S2(x) (((uint32_t)(((uint32_t)(x)) << CSU_CSL_SUR_S2_SHIFT)) & CSU_CSL_SUR_S2_MASK) +#define CSU_CSL_SSR_S2_MASK (0x2U) +#define CSU_CSL_SSR_S2_SHIFT (1U) +/*! SSR_S2 + * 0b0..The secure supervisor read access is disabled for the second slave. + * 0b1..The secure supervisor read access is enabled for the second slave. + */ +#define CSU_CSL_SSR_S2(x) (((uint32_t)(((uint32_t)(x)) << CSU_CSL_SSR_S2_SHIFT)) & CSU_CSL_SSR_S2_MASK) +#define CSU_CSL_NUR_S2_MASK (0x4U) +#define CSU_CSL_NUR_S2_SHIFT (2U) +/*! NUR_S2 + * 0b0..The non-secure user read access is disabled for the second slave. + * 0b1..The non-secure user read access is enabled for the second slave. + */ +#define CSU_CSL_NUR_S2(x) (((uint32_t)(((uint32_t)(x)) << CSU_CSL_NUR_S2_SHIFT)) & CSU_CSL_NUR_S2_MASK) +#define CSU_CSL_NSR_S2_MASK (0x8U) +#define CSU_CSL_NSR_S2_SHIFT (3U) +/*! NSR_S2 + * 0b0..The non-secure supervisor read access is disabled for the second slave. + * 0b1..The non-secure supervisor read access is enabled for the second slave. + */ +#define CSU_CSL_NSR_S2(x) (((uint32_t)(((uint32_t)(x)) << CSU_CSL_NSR_S2_SHIFT)) & CSU_CSL_NSR_S2_MASK) +#define CSU_CSL_SUW_S2_MASK (0x10U) +#define CSU_CSL_SUW_S2_SHIFT (4U) +/*! SUW_S2 + * 0b0..The secure user write access is disabled for the second slave. + * 0b1..The secure user write access is enabled for the second slave. + */ +#define CSU_CSL_SUW_S2(x) (((uint32_t)(((uint32_t)(x)) << CSU_CSL_SUW_S2_SHIFT)) & CSU_CSL_SUW_S2_MASK) +#define CSU_CSL_SSW_S2_MASK (0x20U) +#define CSU_CSL_SSW_S2_SHIFT (5U) +/*! SSW_S2 + * 0b0..The secure supervisor write access is disabled for the second slave. + * 0b1..The secure supervisor write access is enabled for the second slave. + */ +#define CSU_CSL_SSW_S2(x) (((uint32_t)(((uint32_t)(x)) << CSU_CSL_SSW_S2_SHIFT)) & CSU_CSL_SSW_S2_MASK) +#define CSU_CSL_NUW_S2_MASK (0x40U) +#define CSU_CSL_NUW_S2_SHIFT (6U) +/*! NUW_S2 + * 0b0..The non-secure user write access is disabled for the second slave. + * 0b1..The non-secure user write access is enabled for the second slave. + */ +#define CSU_CSL_NUW_S2(x) (((uint32_t)(((uint32_t)(x)) << CSU_CSL_NUW_S2_SHIFT)) & CSU_CSL_NUW_S2_MASK) +#define CSU_CSL_NSW_S2_MASK (0x80U) +#define CSU_CSL_NSW_S2_SHIFT (7U) +/*! NSW_S2 + * 0b0..The non-secure supervisor write access is disabled for the second slave. + * 0b1..The non-secure supervisor write access is enabled for the second slave. + */ +#define CSU_CSL_NSW_S2(x) (((uint32_t)(((uint32_t)(x)) << CSU_CSL_NSW_S2_SHIFT)) & CSU_CSL_NSW_S2_MASK) +#define CSU_CSL_LOCK_S2_MASK (0x100U) +#define CSU_CSL_LOCK_S2_SHIFT (8U) +/*! LOCK_S2 + * 0b0..Not locked. Bits 7-0 can be written by the software. + * 0b1..Bits 7-0 are locked and cannot be written by the software + */ +#define CSU_CSL_LOCK_S2(x) (((uint32_t)(((uint32_t)(x)) << CSU_CSL_LOCK_S2_SHIFT)) & CSU_CSL_LOCK_S2_MASK) +#define CSU_CSL_SUR_S1_MASK (0x10000U) +#define CSU_CSL_SUR_S1_SHIFT (16U) +/*! SUR_S1 + * 0b0..The secure user read access is disabled for the first slave. + * 0b1..The secure user read access is enabled for the first slave. + */ +#define CSU_CSL_SUR_S1(x) (((uint32_t)(((uint32_t)(x)) << CSU_CSL_SUR_S1_SHIFT)) & CSU_CSL_SUR_S1_MASK) +#define CSU_CSL_SSR_S1_MASK (0x20000U) +#define CSU_CSL_SSR_S1_SHIFT (17U) +/*! SSR_S1 + * 0b0..The secure supervisor read access is disabled for the first slave. + * 0b1..The secure supervisor read access is enabled for the first slave. + */ +#define CSU_CSL_SSR_S1(x) (((uint32_t)(((uint32_t)(x)) << CSU_CSL_SSR_S1_SHIFT)) & CSU_CSL_SSR_S1_MASK) +#define CSU_CSL_NUR_S1_MASK (0x40000U) +#define CSU_CSL_NUR_S1_SHIFT (18U) +/*! NUR_S1 + * 0b0..The non-secure user read access is disabled for the first slave. + * 0b1..The non-secure user read access is enabled for the first slave. + */ +#define CSU_CSL_NUR_S1(x) (((uint32_t)(((uint32_t)(x)) << CSU_CSL_NUR_S1_SHIFT)) & CSU_CSL_NUR_S1_MASK) +#define CSU_CSL_NSR_S1_MASK (0x80000U) +#define CSU_CSL_NSR_S1_SHIFT (19U) +/*! NSR_S1 + * 0b0..The non-secure supervisor read access is disabled for the first slave. + * 0b1..The non-secure supervisor read access is enabled for the first slave. + */ +#define CSU_CSL_NSR_S1(x) (((uint32_t)(((uint32_t)(x)) << CSU_CSL_NSR_S1_SHIFT)) & CSU_CSL_NSR_S1_MASK) +#define CSU_CSL_SUW_S1_MASK (0x100000U) +#define CSU_CSL_SUW_S1_SHIFT (20U) +/*! SUW_S1 + * 0b0..The secure user write access is disabled for the first slave. + * 0b1..The secure user write access is enabled for the first slave. + */ +#define CSU_CSL_SUW_S1(x) (((uint32_t)(((uint32_t)(x)) << CSU_CSL_SUW_S1_SHIFT)) & CSU_CSL_SUW_S1_MASK) +#define CSU_CSL_SSW_S1_MASK (0x200000U) +#define CSU_CSL_SSW_S1_SHIFT (21U) +/*! SSW_S1 + * 0b0..The secure supervisor write access is disabled for the first slave. + * 0b1..The secure supervisor write access is enabled for the first slave. + */ +#define CSU_CSL_SSW_S1(x) (((uint32_t)(((uint32_t)(x)) << CSU_CSL_SSW_S1_SHIFT)) & CSU_CSL_SSW_S1_MASK) +#define CSU_CSL_NUW_S1_MASK (0x400000U) +#define CSU_CSL_NUW_S1_SHIFT (22U) +/*! NUW_S1 + * 0b0..The non-secure user write access is disabled for the first slave. + * 0b1..The non-secure user write access is enabled for the first slave. + */ +#define CSU_CSL_NUW_S1(x) (((uint32_t)(((uint32_t)(x)) << CSU_CSL_NUW_S1_SHIFT)) & CSU_CSL_NUW_S1_MASK) +#define CSU_CSL_NSW_S1_MASK (0x800000U) +#define CSU_CSL_NSW_S1_SHIFT (23U) +/*! NSW_S1 + * 0b0..The non-secure supervisor write access is disabled for the first slave. + * 0b1..The non-secure supervisor write access is enabled for the first slave + */ +#define CSU_CSL_NSW_S1(x) (((uint32_t)(((uint32_t)(x)) << CSU_CSL_NSW_S1_SHIFT)) & CSU_CSL_NSW_S1_MASK) +#define CSU_CSL_LOCK_S1_MASK (0x1000000U) +#define CSU_CSL_LOCK_S1_SHIFT (24U) +/*! LOCK_S1 + * 0b0..Not locked. The bits 16-23 can be written by the software. + * 0b1..The bits 16-23 are locked and can't be written by the software. + */ +#define CSU_CSL_LOCK_S1(x) (((uint32_t)(((uint32_t)(x)) << CSU_CSL_LOCK_S1_SHIFT)) & CSU_CSL_LOCK_S1_MASK) +/*! @} */ + +/* The count of CSU_CSL */ +#define CSU_CSL_COUNT (32U) + +/*! @name HP0 - HP0 register */ +/*! @{ */ +#define CSU_HP0_HP_DMA_MASK (0x4U) +#define CSU_HP0_HP_DMA_SHIFT (2U) +/*! HP_DMA + * 0b0..The hprot1 input signal value is routed to the csu_hprot1 output for the corresponding master. + * 0b1..The HP register bit is routed to the csu_hprot1 output for the corresponding master. + */ +#define CSU_HP0_HP_DMA(x) (((uint32_t)(((uint32_t)(x)) << CSU_HP0_HP_DMA_SHIFT)) & CSU_HP0_HP_DMA_MASK) +#define CSU_HP0_L_DMA_MASK (0x8U) +#define CSU_HP0_L_DMA_SHIFT (3U) +/*! L_DMA + * 0b0..No lock-the adjacent (next lower) bit can be written by the software. + * 0b1..Lock-the adjacent (next lower) bit can't be written by the software. + */ +#define CSU_HP0_L_DMA(x) (((uint32_t)(((uint32_t)(x)) << CSU_HP0_L_DMA_SHIFT)) & CSU_HP0_L_DMA_MASK) +#define CSU_HP0_HP_LCDIF_MASK (0x10U) +#define CSU_HP0_HP_LCDIF_SHIFT (4U) +/*! HP_LCDIF + * 0b0..The hprot1 input signal value is routed to the csu_hprot1 output for the corresponding master. + * 0b1..The HP register bit is routed to the csu_hprot1 output for the corresponding master. + */ +#define CSU_HP0_HP_LCDIF(x) (((uint32_t)(((uint32_t)(x)) << CSU_HP0_HP_LCDIF_SHIFT)) & CSU_HP0_HP_LCDIF_MASK) +#define CSU_HP0_L_LCDIF_MASK (0x20U) +#define CSU_HP0_L_LCDIF_SHIFT (5U) +/*! L_LCDIF + * 0b0..No lock-the adjacent (next lower) bit can be written by the software. + * 0b1..Lock-the adjacent (next lower) bit can't be written by the software. + */ +#define CSU_HP0_L_LCDIF(x) (((uint32_t)(((uint32_t)(x)) << CSU_HP0_L_LCDIF_SHIFT)) & CSU_HP0_L_LCDIF_MASK) +#define CSU_HP0_HP_CSI_MASK (0x40U) +#define CSU_HP0_HP_CSI_SHIFT (6U) +/*! HP_CSI + * 0b0..The hprot1 input signal value is routed to the csu_hprot1 output for the corresponding master. + * 0b1..The HP register bit is routed to the csu_hprot1 output for the corresponding master. + */ +#define CSU_HP0_HP_CSI(x) (((uint32_t)(((uint32_t)(x)) << CSU_HP0_HP_CSI_SHIFT)) & CSU_HP0_HP_CSI_MASK) +#define CSU_HP0_L_CSI_MASK (0x80U) +#define CSU_HP0_L_CSI_SHIFT (7U) +/*! L_CSI + * 0b0..No lock-the adjacent (next lower) bit can be written by the software. + * 0b1..Lock-the adjacent (next lower) bit can't be written by the software. + */ +#define CSU_HP0_L_CSI(x) (((uint32_t)(((uint32_t)(x)) << CSU_HP0_L_CSI_SHIFT)) & CSU_HP0_L_CSI_MASK) +#define CSU_HP0_HP_PXP_MASK (0x100U) +#define CSU_HP0_HP_PXP_SHIFT (8U) +/*! HP_PXP + * 0b0..The hprot1 input signal value is routed to the csu_hprot1 output for the corresponding master. + * 0b1..The HP register bit is routed to the csu_hprot1 output for the corresponding master. + */ +#define CSU_HP0_HP_PXP(x) (((uint32_t)(((uint32_t)(x)) << CSU_HP0_HP_PXP_SHIFT)) & CSU_HP0_HP_PXP_MASK) +#define CSU_HP0_L_PXP_MASK (0x200U) +#define CSU_HP0_L_PXP_SHIFT (9U) +/*! L_PXP + * 0b0..No lock-the adjacent (next lower) bit can be written by the software. + * 0b1..Lock-the adjacent (next lower) bit can't be written by the software. + */ +#define CSU_HP0_L_PXP(x) (((uint32_t)(((uint32_t)(x)) << CSU_HP0_L_PXP_SHIFT)) & CSU_HP0_L_PXP_MASK) +#define CSU_HP0_HP_DCP_MASK (0x400U) +#define CSU_HP0_HP_DCP_SHIFT (10U) +/*! HP_DCP + * 0b0..The hprot1 input signal value is routed to the csu_hprot1 output for the corresponding master. + * 0b1..The HP register bit is routed to the csu_hprot1 output for the corresponding master. + */ +#define CSU_HP0_HP_DCP(x) (((uint32_t)(((uint32_t)(x)) << CSU_HP0_HP_DCP_SHIFT)) & CSU_HP0_HP_DCP_MASK) +#define CSU_HP0_L_DCP_MASK (0x800U) +#define CSU_HP0_L_DCP_SHIFT (11U) +/*! L_DCP + * 0b0..No lock-the adjacent (next lower) bit can be written by the software. + * 0b1..Lock-the adjacent (next lower) bit cannot be written by the software. + */ +#define CSU_HP0_L_DCP(x) (((uint32_t)(((uint32_t)(x)) << CSU_HP0_L_DCP_SHIFT)) & CSU_HP0_L_DCP_MASK) +#define CSU_HP0_HP_ENET_MASK (0x4000U) +#define CSU_HP0_HP_ENET_SHIFT (14U) +/*! HP_ENET + * 0b0..The hprot1 input signal value is routed to the csu_hprot1 output for the corresponding master. + * 0b1..The HP register bit is routed to the csu_hprot1 output for the corresponding master. + */ +#define CSU_HP0_HP_ENET(x) (((uint32_t)(((uint32_t)(x)) << CSU_HP0_HP_ENET_SHIFT)) & CSU_HP0_HP_ENET_MASK) +#define CSU_HP0_L_ENET_MASK (0x8000U) +#define CSU_HP0_L_ENET_SHIFT (15U) +/*! L_ENET + * 0b0..No lock-the adjacent (next lower) bit can be written by the software. + * 0b1..Lock-the adjacent (next lower) bit can't be written by the software. + */ +#define CSU_HP0_L_ENET(x) (((uint32_t)(((uint32_t)(x)) << CSU_HP0_L_ENET_SHIFT)) & CSU_HP0_L_ENET_MASK) +#define CSU_HP0_HP_USDHC1_MASK (0x10000U) +#define CSU_HP0_HP_USDHC1_SHIFT (16U) +/*! HP_USDHC1 + * 0b0..The hprot1 input signal value is routed to the csu_hprot1 output for the corresponding master. + * 0b1..The HP register bit is routed to the csu_hprot1 output for the corresponding master. + */ +#define CSU_HP0_HP_USDHC1(x) (((uint32_t)(((uint32_t)(x)) << CSU_HP0_HP_USDHC1_SHIFT)) & CSU_HP0_HP_USDHC1_MASK) +#define CSU_HP0_L_USDHC1_MASK (0x20000U) +#define CSU_HP0_L_USDHC1_SHIFT (17U) +/*! L_USDHC1 + * 0b0..No lock-the adjacent (next lower) bit can be written by the software. + * 0b1..Lock-the adjacent (next lower) bit can't be written by the software. + */ +#define CSU_HP0_L_USDHC1(x) (((uint32_t)(((uint32_t)(x)) << CSU_HP0_L_USDHC1_SHIFT)) & CSU_HP0_L_USDHC1_MASK) +#define CSU_HP0_HP_USDHC2_MASK (0x40000U) +#define CSU_HP0_HP_USDHC2_SHIFT (18U) +/*! HP_USDHC2 + * 0b0..The hprot1 input signal value is routed to the csu_hprot1 output for the corresponding master. + * 0b1..The HP register bit is routed to the csu_hprot1 output for the corresponding master. + */ +#define CSU_HP0_HP_USDHC2(x) (((uint32_t)(((uint32_t)(x)) << CSU_HP0_HP_USDHC2_SHIFT)) & CSU_HP0_HP_USDHC2_MASK) +#define CSU_HP0_L_USDHC2_MASK (0x80000U) +#define CSU_HP0_L_USDHC2_SHIFT (19U) +/*! L_USDHC2 + * 0b0..No lock-the adjacent (next lower) bit can be written by the software. + * 0b1..Lock-the adjacent (next lower) bit can't be written by the software. + */ +#define CSU_HP0_L_USDHC2(x) (((uint32_t)(((uint32_t)(x)) << CSU_HP0_L_USDHC2_SHIFT)) & CSU_HP0_L_USDHC2_MASK) +#define CSU_HP0_HP_TPSMP_MASK (0x100000U) +#define CSU_HP0_HP_TPSMP_SHIFT (20U) +/*! HP_TPSMP + * 0b0..The hprot1 input signal value is routed to the csu_hprot1 output for the corresponding master. + * 0b1..The HP register bit is routed to the csu_hprot1 output for the corresponding master. + */ +#define CSU_HP0_HP_TPSMP(x) (((uint32_t)(((uint32_t)(x)) << CSU_HP0_HP_TPSMP_SHIFT)) & CSU_HP0_HP_TPSMP_MASK) +#define CSU_HP0_L_TPSMP_MASK (0x200000U) +#define CSU_HP0_L_TPSMP_SHIFT (21U) +/*! L_TPSMP + * 0b0..No lock-the adjacent (next lower) bit can be written by the software. + * 0b1..Lock-the adjacent (next lower) bit can't be written by the software. + */ +#define CSU_HP0_L_TPSMP(x) (((uint32_t)(((uint32_t)(x)) << CSU_HP0_L_TPSMP_SHIFT)) & CSU_HP0_L_TPSMP_MASK) +#define CSU_HP0_HP_USB_MASK (0x400000U) +#define CSU_HP0_HP_USB_SHIFT (22U) +/*! HP_USB + * 0b0..The hprot1 input signal value is routed to the csu_hprot1 output for the corresponding master. + * 0b1..The HP register bit is routed to the csu_hprot1 output for the corresponding master. + */ +#define CSU_HP0_HP_USB(x) (((uint32_t)(((uint32_t)(x)) << CSU_HP0_HP_USB_SHIFT)) & CSU_HP0_HP_USB_MASK) +#define CSU_HP0_L_USB_MASK (0x800000U) +#define CSU_HP0_L_USB_SHIFT (23U) +/*! L_USB + * 0b0..No lock-the adjacent (next lower) bit can be written by the software. + * 0b1..Lock-the adjacent (next lower) bit can't be written by the software. + */ +#define CSU_HP0_L_USB(x) (((uint32_t)(((uint32_t)(x)) << CSU_HP0_L_USB_SHIFT)) & CSU_HP0_L_USB_MASK) +/*! @} */ + +/*! @name SA - Secure access register */ +/*! @{ */ +#define CSU_SA_NSA_DMA_MASK (0x4U) +#define CSU_SA_NSA_DMA_SHIFT (2U) +/*! NSA_DMA - Non-secure access policy indicator bit + * 0b0..Secure access for the corresponding type-1 master + * 0b1..Non-secure access for the corresponding type-1 master + */ +#define CSU_SA_NSA_DMA(x) (((uint32_t)(((uint32_t)(x)) << CSU_SA_NSA_DMA_SHIFT)) & CSU_SA_NSA_DMA_MASK) +#define CSU_SA_L_DMA_MASK (0x8U) +#define CSU_SA_L_DMA_SHIFT (3U) +/*! L_DMA + * 0b0..No lock-the adjacent (next lower) bit can be written by the software. + * 0b1..Lock-the adjacent (next lower) bit can't be written by the software. + */ +#define CSU_SA_L_DMA(x) (((uint32_t)(((uint32_t)(x)) << CSU_SA_L_DMA_SHIFT)) & CSU_SA_L_DMA_MASK) +#define CSU_SA_NSA_LCDIF_MASK (0x10U) +#define CSU_SA_NSA_LCDIF_SHIFT (4U) +/*! NSA_LCDIF - Non-secure access policy indicator bit + * 0b0..Secure access for the corresponding type-1 master + * 0b1..Non-secure access for the corresponding type-1 master + */ +#define CSU_SA_NSA_LCDIF(x) (((uint32_t)(((uint32_t)(x)) << CSU_SA_NSA_LCDIF_SHIFT)) & CSU_SA_NSA_LCDIF_MASK) +#define CSU_SA_L_LCDIF_MASK (0x20U) +#define CSU_SA_L_LCDIF_SHIFT (5U) +/*! L_LCDIF + * 0b0..No lock-the adjacent (next lower) bit can be written by the software. + * 0b1..Lock-the adjacent (next lower) bit can't be written by the software. + */ +#define CSU_SA_L_LCDIF(x) (((uint32_t)(((uint32_t)(x)) << CSU_SA_L_LCDIF_SHIFT)) & CSU_SA_L_LCDIF_MASK) +#define CSU_SA_NSA_CSI_MASK (0x40U) +#define CSU_SA_NSA_CSI_SHIFT (6U) +/*! NSA_CSI - Non-secure access policy indicator bit + * 0b0..Secure access for the corresponding type-1 master + * 0b1..Non-secure access for the corresponding type-1 master + */ +#define CSU_SA_NSA_CSI(x) (((uint32_t)(((uint32_t)(x)) << CSU_SA_NSA_CSI_SHIFT)) & CSU_SA_NSA_CSI_MASK) +#define CSU_SA_L_CSI_MASK (0x80U) +#define CSU_SA_L_CSI_SHIFT (7U) +/*! L_CSI + * 0b0..No lock-the adjacent (next lower) bit can be written by the software. + * 0b1..Lock-the adjacent (next lower) bit can't be written by the software. + */ +#define CSU_SA_L_CSI(x) (((uint32_t)(((uint32_t)(x)) << CSU_SA_L_CSI_SHIFT)) & CSU_SA_L_CSI_MASK) +#define CSU_SA_NSA_PXP_MASK (0x100U) +#define CSU_SA_NSA_PXP_SHIFT (8U) +/*! NSA_PXP - Non-Secure Access Policy indicator bit + * 0b0..Secure access for the corresponding type-1 master + * 0b1..Non-secure access for the corresponding type-1 master + */ +#define CSU_SA_NSA_PXP(x) (((uint32_t)(((uint32_t)(x)) << CSU_SA_NSA_PXP_SHIFT)) & CSU_SA_NSA_PXP_MASK) +#define CSU_SA_L_PXP_MASK (0x200U) +#define CSU_SA_L_PXP_SHIFT (9U) +/*! L_PXP + * 0b0..No lock-the adjacent (next lower) bit can be written by the software. + * 0b1..Lock-the adjacent (next lower) bit can't be written by the software. + */ +#define CSU_SA_L_PXP(x) (((uint32_t)(((uint32_t)(x)) << CSU_SA_L_PXP_SHIFT)) & CSU_SA_L_PXP_MASK) +#define CSU_SA_NSA_DCP_MASK (0x400U) +#define CSU_SA_NSA_DCP_SHIFT (10U) +/*! NSA_DCP - Non-secure access policy indicator bit + * 0b0..Secure access for the corresponding type-1 master + * 0b1..Non-secure access for the corresponding type-1 master + */ +#define CSU_SA_NSA_DCP(x) (((uint32_t)(((uint32_t)(x)) << CSU_SA_NSA_DCP_SHIFT)) & CSU_SA_NSA_DCP_MASK) +#define CSU_SA_L_DCP_MASK (0x800U) +#define CSU_SA_L_DCP_SHIFT (11U) +/*! L_DCP + * 0b0..No lock-the adjacent (next lower) bit can be written by the software. + * 0b1..Lock-the adjacent (next lower) bit can't be written by the software. + */ +#define CSU_SA_L_DCP(x) (((uint32_t)(((uint32_t)(x)) << CSU_SA_L_DCP_SHIFT)) & CSU_SA_L_DCP_MASK) +#define CSU_SA_NSA_ENET_MASK (0x4000U) +#define CSU_SA_NSA_ENET_SHIFT (14U) +/*! NSA_ENET - Non-secure access policy indicator bit + * 0b0..Secure access for the corresponding type-1 master + * 0b1..Non-secure access for the corresponding type-1 master + */ +#define CSU_SA_NSA_ENET(x) (((uint32_t)(((uint32_t)(x)) << CSU_SA_NSA_ENET_SHIFT)) & CSU_SA_NSA_ENET_MASK) +#define CSU_SA_L_ENET_MASK (0x8000U) +#define CSU_SA_L_ENET_SHIFT (15U) +/*! L_ENET + * 0b0..No lock-the adjacent (next lower) bit can be written by the software. + * 0b1..Lock-the adjacent (next lower) bit can't be written by the software. + */ +#define CSU_SA_L_ENET(x) (((uint32_t)(((uint32_t)(x)) << CSU_SA_L_ENET_SHIFT)) & CSU_SA_L_ENET_MASK) +#define CSU_SA_NSA_USDHC1_MASK (0x10000U) +#define CSU_SA_NSA_USDHC1_SHIFT (16U) +/*! NSA_USDHC1 - Non-secure access policy indicator bit + * 0b0..Secure access for the corresponding type-1 master + * 0b1..Non-secure access for the corresponding type-1 master + */ +#define CSU_SA_NSA_USDHC1(x) (((uint32_t)(((uint32_t)(x)) << CSU_SA_NSA_USDHC1_SHIFT)) & CSU_SA_NSA_USDHC1_MASK) +#define CSU_SA_L_USDHC1_MASK (0x20000U) +#define CSU_SA_L_USDHC1_SHIFT (17U) +/*! L_USDHC1 + * 0b0..No lock-the adjacent (next lower) bit can be written by the software. + * 0b1..Lock-the adjacent (next lower) bit can't be written by the software. + */ +#define CSU_SA_L_USDHC1(x) (((uint32_t)(((uint32_t)(x)) << CSU_SA_L_USDHC1_SHIFT)) & CSU_SA_L_USDHC1_MASK) +#define CSU_SA_NSA_USDHC2_MASK (0x40000U) +#define CSU_SA_NSA_USDHC2_SHIFT (18U) +/*! NSA_USDHC2 - Non-secure access policy indicator bit + * 0b0..Secure access for the corresponding type-1 master + * 0b1..Non-secure access for the corresponding type-1 master + */ +#define CSU_SA_NSA_USDHC2(x) (((uint32_t)(((uint32_t)(x)) << CSU_SA_NSA_USDHC2_SHIFT)) & CSU_SA_NSA_USDHC2_MASK) +#define CSU_SA_L_USDHC2_MASK (0x80000U) +#define CSU_SA_L_USDHC2_SHIFT (19U) +/*! L_USDHC2 + * 0b0..No lock-the adjacent (next lower) bit can be written by the software. + * 0b1..Lock-the adjacent (next lower) bit can't be written by the software. + */ +#define CSU_SA_L_USDHC2(x) (((uint32_t)(((uint32_t)(x)) << CSU_SA_L_USDHC2_SHIFT)) & CSU_SA_L_USDHC2_MASK) +#define CSU_SA_NSA_TPSMP_MASK (0x100000U) +#define CSU_SA_NSA_TPSMP_SHIFT (20U) +/*! NSA_TPSMP - Non-secure access policy indicator bit + * 0b0..Secure access for the corresponding type-1 master + * 0b1..Non-secure access for the corresponding type-1 master + */ +#define CSU_SA_NSA_TPSMP(x) (((uint32_t)(((uint32_t)(x)) << CSU_SA_NSA_TPSMP_SHIFT)) & CSU_SA_NSA_TPSMP_MASK) +#define CSU_SA_L_TPSMP_MASK (0x200000U) +#define CSU_SA_L_TPSMP_SHIFT (21U) +/*! L_TPSMP + * 0b0..No lock-the adjacent (next lower) bit can be written by the software. + * 0b1..Lock-the adjacent (next lower) bit can't be written by the software. + */ +#define CSU_SA_L_TPSMP(x) (((uint32_t)(((uint32_t)(x)) << CSU_SA_L_TPSMP_SHIFT)) & CSU_SA_L_TPSMP_MASK) +#define CSU_SA_NSA_USB_MASK (0x400000U) +#define CSU_SA_NSA_USB_SHIFT (22U) +/*! NSA_USB - Non-secure access policy indicator bit + * 0b0..Secure access for the corresponding type-1 master + * 0b1..Non-secure access for the corresponding type-1 master + */ +#define CSU_SA_NSA_USB(x) (((uint32_t)(((uint32_t)(x)) << CSU_SA_NSA_USB_SHIFT)) & CSU_SA_NSA_USB_MASK) +#define CSU_SA_L_USB_MASK (0x800000U) +#define CSU_SA_L_USB_SHIFT (23U) +/*! L_USB + * 0b0..No lock-the adjacent (next lower) bit can be written by the software. + * 0b1..Lock-the adjacent (next lower) bit can't be written by the software. + */ +#define CSU_SA_L_USB(x) (((uint32_t)(((uint32_t)(x)) << CSU_SA_L_USB_SHIFT)) & CSU_SA_L_USB_MASK) +/*! @} */ + +/*! @name HPCONTROL0 - HPCONTROL0 register */ +/*! @{ */ +#define CSU_HPCONTROL0_HPC_DMA_MASK (0x4U) +#define CSU_HPCONTROL0_HPC_DMA_SHIFT (2U) +/*! HPC_DMA + * 0b0..User mode for the corresponding master + * 0b1..Supervisor mode for the corresponding master + */ +#define CSU_HPCONTROL0_HPC_DMA(x) (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_HPC_DMA_SHIFT)) & CSU_HPCONTROL0_HPC_DMA_MASK) +#define CSU_HPCONTROL0_L_DMA_MASK (0x8U) +#define CSU_HPCONTROL0_L_DMA_SHIFT (3U) +/*! L_DMA + * 0b0..No lock-the adjacent (next lower) bit can be written by the software. + * 0b1..Lock-the adjacent (next lower) bit can't be written by the software. + */ +#define CSU_HPCONTROL0_L_DMA(x) (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_L_DMA_SHIFT)) & CSU_HPCONTROL0_L_DMA_MASK) +#define CSU_HPCONTROL0_HPC_LCDIF_MASK (0x10U) +#define CSU_HPCONTROL0_HPC_LCDIF_SHIFT (4U) +/*! HPC_LCDIF + * 0b0..User mode for the corresponding master + * 0b1..Supervisor mode for the corresponding master + */ +#define CSU_HPCONTROL0_HPC_LCDIF(x) (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_HPC_LCDIF_SHIFT)) & CSU_HPCONTROL0_HPC_LCDIF_MASK) +#define CSU_HPCONTROL0_L_LCDIF_MASK (0x20U) +#define CSU_HPCONTROL0_L_LCDIF_SHIFT (5U) +/*! L_LCDIF + * 0b0..No lock-the adjacent (next lower) bit can be written by the software. + * 0b1..Lock-the adjacent (next lower) bit can't be written by the software. + */ +#define CSU_HPCONTROL0_L_LCDIF(x) (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_L_LCDIF_SHIFT)) & CSU_HPCONTROL0_L_LCDIF_MASK) +#define CSU_HPCONTROL0_HPC_CSI_MASK (0x40U) +#define CSU_HPCONTROL0_HPC_CSI_SHIFT (6U) +/*! HPC_CSI + * 0b0..User mode for the corresponding master + * 0b1..Supervisor mode for the corresponding master + */ +#define CSU_HPCONTROL0_HPC_CSI(x) (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_HPC_CSI_SHIFT)) & CSU_HPCONTROL0_HPC_CSI_MASK) +#define CSU_HPCONTROL0_L_CSI_MASK (0x80U) +#define CSU_HPCONTROL0_L_CSI_SHIFT (7U) +/*! L_CSI + * 0b0..No lock-the adjacent (next lower) bit can be written by the software. + * 0b1..Lock-the adjacent (next lower) bit can't be written by the software. + */ +#define CSU_HPCONTROL0_L_CSI(x) (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_L_CSI_SHIFT)) & CSU_HPCONTROL0_L_CSI_MASK) +#define CSU_HPCONTROL0_HPC_PXP_MASK (0x100U) +#define CSU_HPCONTROL0_HPC_PXP_SHIFT (8U) +/*! HPC_PXP + * 0b0..User mode for the corresponding master + * 0b1..Supervisor mode for the corresponding master + */ +#define CSU_HPCONTROL0_HPC_PXP(x) (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_HPC_PXP_SHIFT)) & CSU_HPCONTROL0_HPC_PXP_MASK) +#define CSU_HPCONTROL0_L_PXP_MASK (0x200U) +#define CSU_HPCONTROL0_L_PXP_SHIFT (9U) +/*! L_PXP + * 0b0..No lock-the adjacent (next lower) bit can be written by the software. + * 0b1..Lock-the adjacent (next lower) bit can't be written by the software. + */ +#define CSU_HPCONTROL0_L_PXP(x) (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_L_PXP_SHIFT)) & CSU_HPCONTROL0_L_PXP_MASK) +#define CSU_HPCONTROL0_HPC_DCP_MASK (0x400U) +#define CSU_HPCONTROL0_HPC_DCP_SHIFT (10U) +/*! HPC_DCP + * 0b0..User mode for the corresponding master + * 0b1..Supervisor mode for the corresponding master + */ +#define CSU_HPCONTROL0_HPC_DCP(x) (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_HPC_DCP_SHIFT)) & CSU_HPCONTROL0_HPC_DCP_MASK) +#define CSU_HPCONTROL0_L_DCP_MASK (0x800U) +#define CSU_HPCONTROL0_L_DCP_SHIFT (11U) +/*! L_DCP + * 0b0..No lock-the adjacent (next lower) bit can be written by the software. + * 0b1..Lock-the adjacent (next lower) bit can't be written by the software. + */ +#define CSU_HPCONTROL0_L_DCP(x) (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_L_DCP_SHIFT)) & CSU_HPCONTROL0_L_DCP_MASK) +#define CSU_HPCONTROL0_HPC_ENET_MASK (0x4000U) +#define CSU_HPCONTROL0_HPC_ENET_SHIFT (14U) +/*! HPC_ENET + * 0b0..User mode for the corresponding master + * 0b1..Supervisor mode for the corresponding master + */ +#define CSU_HPCONTROL0_HPC_ENET(x) (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_HPC_ENET_SHIFT)) & CSU_HPCONTROL0_HPC_ENET_MASK) +#define CSU_HPCONTROL0_L_ENET_MASK (0x8000U) +#define CSU_HPCONTROL0_L_ENET_SHIFT (15U) +/*! L_ENET + * 0b0..No lock-the adjacent (next lower) bit can be written by the software. + * 0b1..Lock-the adjacent (next lower) bit can't be written by the software. + */ +#define CSU_HPCONTROL0_L_ENET(x) (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_L_ENET_SHIFT)) & CSU_HPCONTROL0_L_ENET_MASK) +#define CSU_HPCONTROL0_HPC_USDHC1_MASK (0x10000U) +#define CSU_HPCONTROL0_HPC_USDHC1_SHIFT (16U) +/*! HPC_USDHC1 + * 0b0..User mode for the corresponding master + * 0b1..Supervisor mode for the corresponding master + */ +#define CSU_HPCONTROL0_HPC_USDHC1(x) (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_HPC_USDHC1_SHIFT)) & CSU_HPCONTROL0_HPC_USDHC1_MASK) +#define CSU_HPCONTROL0_L_USDHC1_MASK (0x20000U) +#define CSU_HPCONTROL0_L_USDHC1_SHIFT (17U) +/*! L_USDHC1 + * 0b0..No lock-the adjacent (next lower) bit can be written by the software. + * 0b1..Lock-the adjacent (next lower) bit can't be written by the software. + */ +#define CSU_HPCONTROL0_L_USDHC1(x) (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_L_USDHC1_SHIFT)) & CSU_HPCONTROL0_L_USDHC1_MASK) +#define CSU_HPCONTROL0_HPC_USDHC2_MASK (0x40000U) +#define CSU_HPCONTROL0_HPC_USDHC2_SHIFT (18U) +/*! HPC_USDHC2 + * 0b0..User mode for the corresponding master + * 0b1..Supervisor mode for the corresponding master + */ +#define CSU_HPCONTROL0_HPC_USDHC2(x) (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_HPC_USDHC2_SHIFT)) & CSU_HPCONTROL0_HPC_USDHC2_MASK) +#define CSU_HPCONTROL0_L_USDHC2_MASK (0x80000U) +#define CSU_HPCONTROL0_L_USDHC2_SHIFT (19U) +/*! L_USDHC2 + * 0b0..No lock-the adjacent (next lower) bit can be written by the software. + * 0b1..Lock-the adjacent (next lower) bit can't be written by the software. + */ +#define CSU_HPCONTROL0_L_USDHC2(x) (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_L_USDHC2_SHIFT)) & CSU_HPCONTROL0_L_USDHC2_MASK) +#define CSU_HPCONTROL0_HPC_TPSMP_MASK (0x100000U) +#define CSU_HPCONTROL0_HPC_TPSMP_SHIFT (20U) +/*! HPC_TPSMP + * 0b0..User mode for the corresponding master + * 0b1..Supervisor mode for the corresponding master + */ +#define CSU_HPCONTROL0_HPC_TPSMP(x) (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_HPC_TPSMP_SHIFT)) & CSU_HPCONTROL0_HPC_TPSMP_MASK) +#define CSU_HPCONTROL0_L_TPSMP_MASK (0x200000U) +#define CSU_HPCONTROL0_L_TPSMP_SHIFT (21U) +/*! L_TPSMP + * 0b0..No lock-the adjacent (next lower) bit can be written by the software. + * 0b1..Lock-the adjacent (next lower) bit can't be written by the software. + */ +#define CSU_HPCONTROL0_L_TPSMP(x) (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_L_TPSMP_SHIFT)) & CSU_HPCONTROL0_L_TPSMP_MASK) +#define CSU_HPCONTROL0_HPC_USB_MASK (0x400000U) +#define CSU_HPCONTROL0_HPC_USB_SHIFT (22U) +/*! HPC_USB + * 0b0..User mode for the corresponding master + * 0b1..Supervisor mode for the corresponding master + */ +#define CSU_HPCONTROL0_HPC_USB(x) (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_HPC_USB_SHIFT)) & CSU_HPCONTROL0_HPC_USB_MASK) +#define CSU_HPCONTROL0_L_USB_MASK (0x800000U) +#define CSU_HPCONTROL0_L_USB_SHIFT (23U) +/*! L_USB + * 0b0..No lock-the adjacent (next lower) bit can be written by the software. + * 0b1..Lock-the adjacent (next lower) bit can't be written by the software. + */ +#define CSU_HPCONTROL0_L_USB(x) (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_L_USB_SHIFT)) & CSU_HPCONTROL0_L_USB_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group CSU_Register_Masks */ + + +/* CSU - Peripheral instance base addresses */ +/** Peripheral CSU base address */ +#define CSU_BASE (0x400DC000u) +/** Peripheral CSU base pointer */ +#define CSU ((CSU_Type *)CSU_BASE) +/** Array initializer of CSU peripheral base addresses */ +#define CSU_BASE_ADDRS { CSU_BASE } +/** Array initializer of CSU peripheral base pointers */ +#define CSU_BASE_PTRS { CSU } + +/*! + * @} + */ /* end of group CSU_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- DCDC Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup DCDC_Peripheral_Access_Layer DCDC Peripheral Access Layer + * @{ + */ + +/** DCDC - Register Layout Typedef */ +typedef struct { + __IO uint32_t REG0; /**< DCDC Register 0, offset: 0x0 */ + __IO uint32_t REG1; /**< DCDC Register 1, offset: 0x4 */ + __IO uint32_t REG2; /**< DCDC Register 2, offset: 0x8 */ + __IO uint32_t REG3; /**< DCDC Register 3, offset: 0xC */ +} DCDC_Type; + +/* ---------------------------------------------------------------------------- + -- DCDC Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup DCDC_Register_Masks DCDC Register Masks + * @{ + */ + +/*! @name REG0 - DCDC Register 0 */ +/*! @{ */ +#define DCDC_REG0_PWD_ZCD_MASK (0x1U) +#define DCDC_REG0_PWD_ZCD_SHIFT (0U) +#define DCDC_REG0_PWD_ZCD(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_PWD_ZCD_SHIFT)) & DCDC_REG0_PWD_ZCD_MASK) +#define DCDC_REG0_DISABLE_AUTO_CLK_SWITCH_MASK (0x2U) +#define DCDC_REG0_DISABLE_AUTO_CLK_SWITCH_SHIFT (1U) +#define DCDC_REG0_DISABLE_AUTO_CLK_SWITCH(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_DISABLE_AUTO_CLK_SWITCH_SHIFT)) & DCDC_REG0_DISABLE_AUTO_CLK_SWITCH_MASK) +#define DCDC_REG0_SEL_CLK_MASK (0x4U) +#define DCDC_REG0_SEL_CLK_SHIFT (2U) +#define DCDC_REG0_SEL_CLK(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_SEL_CLK_SHIFT)) & DCDC_REG0_SEL_CLK_MASK) +#define DCDC_REG0_PWD_OSC_INT_MASK (0x8U) +#define DCDC_REG0_PWD_OSC_INT_SHIFT (3U) +#define DCDC_REG0_PWD_OSC_INT(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_PWD_OSC_INT_SHIFT)) & DCDC_REG0_PWD_OSC_INT_MASK) +#define DCDC_REG0_PWD_CUR_SNS_CMP_MASK (0x10U) +#define DCDC_REG0_PWD_CUR_SNS_CMP_SHIFT (4U) +#define DCDC_REG0_PWD_CUR_SNS_CMP(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_PWD_CUR_SNS_CMP_SHIFT)) & DCDC_REG0_PWD_CUR_SNS_CMP_MASK) +#define DCDC_REG0_CUR_SNS_THRSH_MASK (0xE0U) +#define DCDC_REG0_CUR_SNS_THRSH_SHIFT (5U) +#define DCDC_REG0_CUR_SNS_THRSH(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_CUR_SNS_THRSH_SHIFT)) & DCDC_REG0_CUR_SNS_THRSH_MASK) +#define DCDC_REG0_PWD_OVERCUR_DET_MASK (0x100U) +#define DCDC_REG0_PWD_OVERCUR_DET_SHIFT (8U) +#define DCDC_REG0_PWD_OVERCUR_DET(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_PWD_OVERCUR_DET_SHIFT)) & DCDC_REG0_PWD_OVERCUR_DET_MASK) +#define DCDC_REG0_OVERCUR_TRIG_ADJ_MASK (0x600U) +#define DCDC_REG0_OVERCUR_TRIG_ADJ_SHIFT (9U) +#define DCDC_REG0_OVERCUR_TRIG_ADJ(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_OVERCUR_TRIG_ADJ_SHIFT)) & DCDC_REG0_OVERCUR_TRIG_ADJ_MASK) +#define DCDC_REG0_PWD_CMP_BATT_DET_MASK (0x800U) +#define DCDC_REG0_PWD_CMP_BATT_DET_SHIFT (11U) +#define DCDC_REG0_PWD_CMP_BATT_DET(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_PWD_CMP_BATT_DET_SHIFT)) & DCDC_REG0_PWD_CMP_BATT_DET_MASK) +#define DCDC_REG0_ADJ_POSLIMIT_BUCK_MASK (0xF000U) +#define DCDC_REG0_ADJ_POSLIMIT_BUCK_SHIFT (12U) +#define DCDC_REG0_ADJ_POSLIMIT_BUCK(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_ADJ_POSLIMIT_BUCK_SHIFT)) & DCDC_REG0_ADJ_POSLIMIT_BUCK_MASK) +#define DCDC_REG0_EN_LP_OVERLOAD_SNS_MASK (0x10000U) +#define DCDC_REG0_EN_LP_OVERLOAD_SNS_SHIFT (16U) +#define DCDC_REG0_EN_LP_OVERLOAD_SNS(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_EN_LP_OVERLOAD_SNS_SHIFT)) & DCDC_REG0_EN_LP_OVERLOAD_SNS_MASK) +#define DCDC_REG0_PWD_HIGH_VOLT_DET_MASK (0x20000U) +#define DCDC_REG0_PWD_HIGH_VOLT_DET_SHIFT (17U) +#define DCDC_REG0_PWD_HIGH_VOLT_DET(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_PWD_HIGH_VOLT_DET_SHIFT)) & DCDC_REG0_PWD_HIGH_VOLT_DET_MASK) +#define DCDC_REG0_LP_OVERLOAD_THRSH_MASK (0xC0000U) +#define DCDC_REG0_LP_OVERLOAD_THRSH_SHIFT (18U) +#define DCDC_REG0_LP_OVERLOAD_THRSH(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_LP_OVERLOAD_THRSH_SHIFT)) & DCDC_REG0_LP_OVERLOAD_THRSH_MASK) +#define DCDC_REG0_LP_OVERLOAD_FREQ_SEL_MASK (0x100000U) +#define DCDC_REG0_LP_OVERLOAD_FREQ_SEL_SHIFT (20U) +#define DCDC_REG0_LP_OVERLOAD_FREQ_SEL(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_LP_OVERLOAD_FREQ_SEL_SHIFT)) & DCDC_REG0_LP_OVERLOAD_FREQ_SEL_MASK) +#define DCDC_REG0_LP_HIGH_HYS_MASK (0x200000U) +#define DCDC_REG0_LP_HIGH_HYS_SHIFT (21U) +#define DCDC_REG0_LP_HIGH_HYS(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_LP_HIGH_HYS_SHIFT)) & DCDC_REG0_LP_HIGH_HYS_MASK) +#define DCDC_REG0_PWD_CMP_OFFSET_MASK (0x4000000U) +#define DCDC_REG0_PWD_CMP_OFFSET_SHIFT (26U) +#define DCDC_REG0_PWD_CMP_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_PWD_CMP_OFFSET_SHIFT)) & DCDC_REG0_PWD_CMP_OFFSET_MASK) +#define DCDC_REG0_XTALOK_DISABLE_MASK (0x8000000U) +#define DCDC_REG0_XTALOK_DISABLE_SHIFT (27U) +#define DCDC_REG0_XTALOK_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_XTALOK_DISABLE_SHIFT)) & DCDC_REG0_XTALOK_DISABLE_MASK) +#define DCDC_REG0_CURRENT_ALERT_RESET_MASK (0x10000000U) +#define DCDC_REG0_CURRENT_ALERT_RESET_SHIFT (28U) +#define DCDC_REG0_CURRENT_ALERT_RESET(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_CURRENT_ALERT_RESET_SHIFT)) & DCDC_REG0_CURRENT_ALERT_RESET_MASK) +#define DCDC_REG0_XTAL_24M_OK_MASK (0x20000000U) +#define DCDC_REG0_XTAL_24M_OK_SHIFT (29U) +#define DCDC_REG0_XTAL_24M_OK(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_XTAL_24M_OK_SHIFT)) & DCDC_REG0_XTAL_24M_OK_MASK) +#define DCDC_REG0_STS_DC_OK_MASK (0x80000000U) +#define DCDC_REG0_STS_DC_OK_SHIFT (31U) +#define DCDC_REG0_STS_DC_OK(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_STS_DC_OK_SHIFT)) & DCDC_REG0_STS_DC_OK_MASK) +/*! @} */ + +/*! @name REG1 - DCDC Register 1 */ +/*! @{ */ +#define DCDC_REG1_REG_FBK_SEL_MASK (0x180U) +#define DCDC_REG1_REG_FBK_SEL_SHIFT (7U) +#define DCDC_REG1_REG_FBK_SEL(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG1_REG_FBK_SEL_SHIFT)) & DCDC_REG1_REG_FBK_SEL_MASK) +#define DCDC_REG1_REG_RLOAD_SW_MASK (0x200U) +#define DCDC_REG1_REG_RLOAD_SW_SHIFT (9U) +#define DCDC_REG1_REG_RLOAD_SW(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG1_REG_RLOAD_SW_SHIFT)) & DCDC_REG1_REG_RLOAD_SW_MASK) +#define DCDC_REG1_LP_CMP_ISRC_SEL_MASK (0x3000U) +#define DCDC_REG1_LP_CMP_ISRC_SEL_SHIFT (12U) +#define DCDC_REG1_LP_CMP_ISRC_SEL(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG1_LP_CMP_ISRC_SEL_SHIFT)) & DCDC_REG1_LP_CMP_ISRC_SEL_MASK) +#define DCDC_REG1_LOOPCTRL_HST_THRESH_MASK (0x200000U) +#define DCDC_REG1_LOOPCTRL_HST_THRESH_SHIFT (21U) +#define DCDC_REG1_LOOPCTRL_HST_THRESH(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG1_LOOPCTRL_HST_THRESH_SHIFT)) & DCDC_REG1_LOOPCTRL_HST_THRESH_MASK) +#define DCDC_REG1_LOOPCTRL_EN_HYST_MASK (0x800000U) +#define DCDC_REG1_LOOPCTRL_EN_HYST_SHIFT (23U) +#define DCDC_REG1_LOOPCTRL_EN_HYST(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG1_LOOPCTRL_EN_HYST_SHIFT)) & DCDC_REG1_LOOPCTRL_EN_HYST_MASK) +#define DCDC_REG1_VBG_TRIM_MASK (0x1F000000U) +#define DCDC_REG1_VBG_TRIM_SHIFT (24U) +#define DCDC_REG1_VBG_TRIM(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG1_VBG_TRIM_SHIFT)) & DCDC_REG1_VBG_TRIM_MASK) +/*! @} */ + +/*! @name REG2 - DCDC Register 2 */ +/*! @{ */ +#define DCDC_REG2_LOOPCTRL_DC_C_MASK (0x3U) +#define DCDC_REG2_LOOPCTRL_DC_C_SHIFT (0U) +#define DCDC_REG2_LOOPCTRL_DC_C(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG2_LOOPCTRL_DC_C_SHIFT)) & DCDC_REG2_LOOPCTRL_DC_C_MASK) +#define DCDC_REG2_LOOPCTRL_DC_R_MASK (0x3CU) +#define DCDC_REG2_LOOPCTRL_DC_R_SHIFT (2U) +#define DCDC_REG2_LOOPCTRL_DC_R(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG2_LOOPCTRL_DC_R_SHIFT)) & DCDC_REG2_LOOPCTRL_DC_R_MASK) +#define DCDC_REG2_LOOPCTRL_DC_FF_MASK (0x1C0U) +#define DCDC_REG2_LOOPCTRL_DC_FF_SHIFT (6U) +#define DCDC_REG2_LOOPCTRL_DC_FF(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG2_LOOPCTRL_DC_FF_SHIFT)) & DCDC_REG2_LOOPCTRL_DC_FF_MASK) +#define DCDC_REG2_LOOPCTRL_EN_RCSCALE_MASK (0xE00U) +#define DCDC_REG2_LOOPCTRL_EN_RCSCALE_SHIFT (9U) +#define DCDC_REG2_LOOPCTRL_EN_RCSCALE(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG2_LOOPCTRL_EN_RCSCALE_SHIFT)) & DCDC_REG2_LOOPCTRL_EN_RCSCALE_MASK) +#define DCDC_REG2_LOOPCTRL_RCSCALE_THRSH_MASK (0x1000U) +#define DCDC_REG2_LOOPCTRL_RCSCALE_THRSH_SHIFT (12U) +#define DCDC_REG2_LOOPCTRL_RCSCALE_THRSH(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG2_LOOPCTRL_RCSCALE_THRSH_SHIFT)) & DCDC_REG2_LOOPCTRL_RCSCALE_THRSH_MASK) +#define DCDC_REG2_LOOPCTRL_HYST_SIGN_MASK (0x2000U) +#define DCDC_REG2_LOOPCTRL_HYST_SIGN_SHIFT (13U) +#define DCDC_REG2_LOOPCTRL_HYST_SIGN(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG2_LOOPCTRL_HYST_SIGN_SHIFT)) & DCDC_REG2_LOOPCTRL_HYST_SIGN_MASK) +#define DCDC_REG2_DISABLE_PULSE_SKIP_MASK (0x8000000U) +#define DCDC_REG2_DISABLE_PULSE_SKIP_SHIFT (27U) +#define DCDC_REG2_DISABLE_PULSE_SKIP(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG2_DISABLE_PULSE_SKIP_SHIFT)) & DCDC_REG2_DISABLE_PULSE_SKIP_MASK) +#define DCDC_REG2_DCM_SET_CTRL_MASK (0x10000000U) +#define DCDC_REG2_DCM_SET_CTRL_SHIFT (28U) +#define DCDC_REG2_DCM_SET_CTRL(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG2_DCM_SET_CTRL_SHIFT)) & DCDC_REG2_DCM_SET_CTRL_MASK) +/*! @} */ + +/*! @name REG3 - DCDC Register 3 */ +/*! @{ */ +#define DCDC_REG3_TRG_MASK (0x1FU) +#define DCDC_REG3_TRG_SHIFT (0U) +#define DCDC_REG3_TRG(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG3_TRG_SHIFT)) & DCDC_REG3_TRG_MASK) +#define DCDC_REG3_TARGET_LP_MASK (0x700U) +#define DCDC_REG3_TARGET_LP_SHIFT (8U) +#define DCDC_REG3_TARGET_LP(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG3_TARGET_LP_SHIFT)) & DCDC_REG3_TARGET_LP_MASK) +#define DCDC_REG3_MINPWR_DC_HALFCLK_MASK (0x1000000U) +#define DCDC_REG3_MINPWR_DC_HALFCLK_SHIFT (24U) +#define DCDC_REG3_MINPWR_DC_HALFCLK(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG3_MINPWR_DC_HALFCLK_SHIFT)) & DCDC_REG3_MINPWR_DC_HALFCLK_MASK) +#define DCDC_REG3_MISC_DELAY_TIMING_MASK (0x8000000U) +#define DCDC_REG3_MISC_DELAY_TIMING_SHIFT (27U) +#define DCDC_REG3_MISC_DELAY_TIMING(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG3_MISC_DELAY_TIMING_SHIFT)) & DCDC_REG3_MISC_DELAY_TIMING_MASK) +#define DCDC_REG3_MISC_DISABLEFET_LOGIC_MASK (0x10000000U) +#define DCDC_REG3_MISC_DISABLEFET_LOGIC_SHIFT (28U) +#define DCDC_REG3_MISC_DISABLEFET_LOGIC(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG3_MISC_DISABLEFET_LOGIC_SHIFT)) & DCDC_REG3_MISC_DISABLEFET_LOGIC_MASK) +#define DCDC_REG3_DISABLE_STEP_MASK (0x40000000U) +#define DCDC_REG3_DISABLE_STEP_SHIFT (30U) +#define DCDC_REG3_DISABLE_STEP(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG3_DISABLE_STEP_SHIFT)) & DCDC_REG3_DISABLE_STEP_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group DCDC_Register_Masks */ + + +/* DCDC - Peripheral instance base addresses */ +/** Peripheral DCDC base address */ +#define DCDC_BASE (0x40080000u) +/** Peripheral DCDC base pointer */ +#define DCDC ((DCDC_Type *)DCDC_BASE) +/** Array initializer of DCDC peripheral base addresses */ +#define DCDC_BASE_ADDRS { DCDC_BASE } +/** Array initializer of DCDC peripheral base pointers */ +#define DCDC_BASE_PTRS { DCDC } +/** Interrupt vectors for the DCDC peripheral type */ +#define DCDC_IRQS { DCDC_IRQn } + +/*! + * @} + */ /* end of group DCDC_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- DCP Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup DCP_Peripheral_Access_Layer DCP Peripheral Access Layer + * @{ + */ + +/** DCP - Register Layout Typedef */ +typedef struct { + __IO uint32_t CTRL; /**< DCP control register 0, offset: 0x0 */ + uint8_t RESERVED_0[12]; + __IO uint32_t STAT; /**< DCP status register, offset: 0x10 */ + uint8_t RESERVED_1[12]; + __IO uint32_t CHANNELCTRL; /**< DCP channel control register, offset: 0x20 */ + uint8_t RESERVED_2[12]; + __IO uint32_t CAPABILITY0; /**< DCP capability 0 register, offset: 0x30 */ + uint8_t RESERVED_3[12]; + __I uint32_t CAPABILITY1; /**< DCP capability 1 register, offset: 0x40 */ + uint8_t RESERVED_4[12]; + __IO uint32_t CONTEXT; /**< DCP context buffer pointer, offset: 0x50 */ + uint8_t RESERVED_5[12]; + __IO uint32_t KEY; /**< DCP key index, offset: 0x60 */ + uint8_t RESERVED_6[12]; + __IO uint32_t KEYDATA; /**< DCP key data, offset: 0x70 */ + uint8_t RESERVED_7[12]; + __I uint32_t PACKET0; /**< DCP work packet 0 status register, offset: 0x80 */ + uint8_t RESERVED_8[12]; + __I uint32_t PACKET1; /**< DCP work packet 1 status register, offset: 0x90 */ + uint8_t RESERVED_9[12]; + __I uint32_t PACKET2; /**< DCP work packet 2 status register, offset: 0xA0 */ + uint8_t RESERVED_10[12]; + __I uint32_t PACKET3; /**< DCP work packet 3 status register, offset: 0xB0 */ + uint8_t RESERVED_11[12]; + __I uint32_t PACKET4; /**< DCP work packet 4 status register, offset: 0xC0 */ + uint8_t RESERVED_12[12]; + __I uint32_t PACKET5; /**< DCP work packet 5 status register, offset: 0xD0 */ + uint8_t RESERVED_13[12]; + __I uint32_t PACKET6; /**< DCP work packet 6 status register, offset: 0xE0 */ + uint8_t RESERVED_14[28]; + __IO uint32_t CH0CMDPTR; /**< DCP channel 0 command pointer address register, offset: 0x100 */ + uint8_t RESERVED_15[12]; + __IO uint32_t CH0SEMA; /**< DCP channel 0 semaphore register, offset: 0x110 */ + uint8_t RESERVED_16[12]; + __IO uint32_t CH0STAT; /**< DCP channel 0 status register, offset: 0x120 */ + uint8_t RESERVED_17[12]; + __IO uint32_t CH0OPTS; /**< DCP channel 0 options register, offset: 0x130 */ + uint8_t RESERVED_18[12]; + __IO uint32_t CH1CMDPTR; /**< DCP channel 1 command pointer address register, offset: 0x140 */ + uint8_t RESERVED_19[12]; + __IO uint32_t CH1SEMA; /**< DCP channel 1 semaphore register, offset: 0x150 */ + uint8_t RESERVED_20[12]; + __IO uint32_t CH1STAT; /**< DCP channel 1 status register, offset: 0x160 */ + uint8_t RESERVED_21[12]; + __IO uint32_t CH1OPTS; /**< DCP channel 1 options register, offset: 0x170 */ + uint8_t RESERVED_22[12]; + __IO uint32_t CH2CMDPTR; /**< DCP channel 2 command pointer address register, offset: 0x180 */ + uint8_t RESERVED_23[12]; + __IO uint32_t CH2SEMA; /**< DCP channel 2 semaphore register, offset: 0x190 */ + uint8_t RESERVED_24[12]; + __IO uint32_t CH2STAT; /**< DCP channel 2 status register, offset: 0x1A0 */ + uint8_t RESERVED_25[12]; + __IO uint32_t CH2OPTS; /**< DCP channel 2 options register, offset: 0x1B0 */ + uint8_t RESERVED_26[12]; + __IO uint32_t CH3CMDPTR; /**< DCP channel 3 command pointer address register, offset: 0x1C0 */ + uint8_t RESERVED_27[12]; + __IO uint32_t CH3SEMA; /**< DCP channel 3 semaphore register, offset: 0x1D0 */ + uint8_t RESERVED_28[12]; + __IO uint32_t CH3STAT; /**< DCP channel 3 status register, offset: 0x1E0 */ + uint8_t RESERVED_29[12]; + __IO uint32_t CH3OPTS; /**< DCP channel 3 options register, offset: 0x1F0 */ + uint8_t RESERVED_30[524]; + __IO uint32_t DBGSELECT; /**< DCP debug select register, offset: 0x400 */ + uint8_t RESERVED_31[12]; + __I uint32_t DBGDATA; /**< DCP debug data register, offset: 0x410 */ + uint8_t RESERVED_32[12]; + __IO uint32_t PAGETABLE; /**< DCP page table register, offset: 0x420 */ + uint8_t RESERVED_33[12]; + __I uint32_t VERSION; /**< DCP version register, offset: 0x430 */ +} DCP_Type; + +/* ---------------------------------------------------------------------------- + -- DCP Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup DCP_Register_Masks DCP Register Masks + * @{ + */ + +/*! @name CTRL - DCP control register 0 */ +/*! @{ */ +#define DCP_CTRL_CHANNEL_INTERRUPT_ENABLE_MASK (0xFFU) +#define DCP_CTRL_CHANNEL_INTERRUPT_ENABLE_SHIFT (0U) +/*! CHANNEL_INTERRUPT_ENABLE + * 0b00000001..CH0 + * 0b00000010..CH1 + * 0b00000100..CH2 + * 0b00001000..CH3 + */ +#define DCP_CTRL_CHANNEL_INTERRUPT_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_CHANNEL_INTERRUPT_ENABLE_SHIFT)) & DCP_CTRL_CHANNEL_INTERRUPT_ENABLE_MASK) +#define DCP_CTRL_RSVD_CSC_INTERRUPT_ENABLE_MASK (0x100U) +#define DCP_CTRL_RSVD_CSC_INTERRUPT_ENABLE_SHIFT (8U) +#define DCP_CTRL_RSVD_CSC_INTERRUPT_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_RSVD_CSC_INTERRUPT_ENABLE_SHIFT)) & DCP_CTRL_RSVD_CSC_INTERRUPT_ENABLE_MASK) +#define DCP_CTRL_ENABLE_CONTEXT_SWITCHING_MASK (0x200000U) +#define DCP_CTRL_ENABLE_CONTEXT_SWITCHING_SHIFT (21U) +#define DCP_CTRL_ENABLE_CONTEXT_SWITCHING(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_ENABLE_CONTEXT_SWITCHING_SHIFT)) & DCP_CTRL_ENABLE_CONTEXT_SWITCHING_MASK) +#define DCP_CTRL_ENABLE_CONTEXT_CACHING_MASK (0x400000U) +#define DCP_CTRL_ENABLE_CONTEXT_CACHING_SHIFT (22U) +#define DCP_CTRL_ENABLE_CONTEXT_CACHING(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_ENABLE_CONTEXT_CACHING_SHIFT)) & DCP_CTRL_ENABLE_CONTEXT_CACHING_MASK) +#define DCP_CTRL_GATHER_RESIDUAL_WRITES_MASK (0x800000U) +#define DCP_CTRL_GATHER_RESIDUAL_WRITES_SHIFT (23U) +#define DCP_CTRL_GATHER_RESIDUAL_WRITES(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_GATHER_RESIDUAL_WRITES_SHIFT)) & DCP_CTRL_GATHER_RESIDUAL_WRITES_MASK) +#define DCP_CTRL_PRESENT_SHA_MASK (0x10000000U) +#define DCP_CTRL_PRESENT_SHA_SHIFT (28U) +/*! PRESENT_SHA + * 0b1..Present + * 0b0..Absent + */ +#define DCP_CTRL_PRESENT_SHA(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_PRESENT_SHA_SHIFT)) & DCP_CTRL_PRESENT_SHA_MASK) +#define DCP_CTRL_PRESENT_CRYPTO_MASK (0x20000000U) +#define DCP_CTRL_PRESENT_CRYPTO_SHIFT (29U) +/*! PRESENT_CRYPTO + * 0b1..Present + * 0b0..Absent + */ +#define DCP_CTRL_PRESENT_CRYPTO(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_PRESENT_CRYPTO_SHIFT)) & DCP_CTRL_PRESENT_CRYPTO_MASK) +#define DCP_CTRL_CLKGATE_MASK (0x40000000U) +#define DCP_CTRL_CLKGATE_SHIFT (30U) +#define DCP_CTRL_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_CLKGATE_SHIFT)) & DCP_CTRL_CLKGATE_MASK) +#define DCP_CTRL_SFTRST_MASK (0x80000000U) +#define DCP_CTRL_SFTRST_SHIFT (31U) +#define DCP_CTRL_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_SFTRST_SHIFT)) & DCP_CTRL_SFTRST_MASK) +/*! @} */ + +/*! @name STAT - DCP status register */ +/*! @{ */ +#define DCP_STAT_IRQ_MASK (0xFU) +#define DCP_STAT_IRQ_SHIFT (0U) +#define DCP_STAT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << DCP_STAT_IRQ_SHIFT)) & DCP_STAT_IRQ_MASK) +#define DCP_STAT_RSVD_IRQ_MASK (0x100U) +#define DCP_STAT_RSVD_IRQ_SHIFT (8U) +#define DCP_STAT_RSVD_IRQ(x) (((uint32_t)(((uint32_t)(x)) << DCP_STAT_RSVD_IRQ_SHIFT)) & DCP_STAT_RSVD_IRQ_MASK) +#define DCP_STAT_READY_CHANNELS_MASK (0xFF0000U) +#define DCP_STAT_READY_CHANNELS_SHIFT (16U) +/*! READY_CHANNELS + * 0b00000001..CH0 + * 0b00000010..CH1 + * 0b00000100..CH2 + * 0b00001000..CH3 + */ +#define DCP_STAT_READY_CHANNELS(x) (((uint32_t)(((uint32_t)(x)) << DCP_STAT_READY_CHANNELS_SHIFT)) & DCP_STAT_READY_CHANNELS_MASK) +#define DCP_STAT_CUR_CHANNEL_MASK (0xF000000U) +#define DCP_STAT_CUR_CHANNEL_SHIFT (24U) +/*! CUR_CHANNEL + * 0b0000..None + * 0b0001..CH0 + * 0b0010..CH1 + * 0b0011..CH2 + * 0b0100..CH3 + */ +#define DCP_STAT_CUR_CHANNEL(x) (((uint32_t)(((uint32_t)(x)) << DCP_STAT_CUR_CHANNEL_SHIFT)) & DCP_STAT_CUR_CHANNEL_MASK) +#define DCP_STAT_OTP_KEY_READY_MASK (0x10000000U) +#define DCP_STAT_OTP_KEY_READY_SHIFT (28U) +#define DCP_STAT_OTP_KEY_READY(x) (((uint32_t)(((uint32_t)(x)) << DCP_STAT_OTP_KEY_READY_SHIFT)) & DCP_STAT_OTP_KEY_READY_MASK) +/*! @} */ + +/*! @name CHANNELCTRL - DCP channel control register */ +/*! @{ */ +#define DCP_CHANNELCTRL_ENABLE_CHANNEL_MASK (0xFFU) +#define DCP_CHANNELCTRL_ENABLE_CHANNEL_SHIFT (0U) +/*! ENABLE_CHANNEL + * 0b00000001..CH0 + * 0b00000010..CH1 + * 0b00000100..CH2 + * 0b00001000..CH3 + */ +#define DCP_CHANNELCTRL_ENABLE_CHANNEL(x) (((uint32_t)(((uint32_t)(x)) << DCP_CHANNELCTRL_ENABLE_CHANNEL_SHIFT)) & DCP_CHANNELCTRL_ENABLE_CHANNEL_MASK) +#define DCP_CHANNELCTRL_HIGH_PRIORITY_CHANNEL_MASK (0xFF00U) +#define DCP_CHANNELCTRL_HIGH_PRIORITY_CHANNEL_SHIFT (8U) +/*! HIGH_PRIORITY_CHANNEL + * 0b00000001..CH0 + * 0b00000010..CH1 + * 0b00000100..CH2 + * 0b00001000..CH3 + */ +#define DCP_CHANNELCTRL_HIGH_PRIORITY_CHANNEL(x) (((uint32_t)(((uint32_t)(x)) << DCP_CHANNELCTRL_HIGH_PRIORITY_CHANNEL_SHIFT)) & DCP_CHANNELCTRL_HIGH_PRIORITY_CHANNEL_MASK) +#define DCP_CHANNELCTRL_CH0_IRQ_MERGED_MASK (0x10000U) +#define DCP_CHANNELCTRL_CH0_IRQ_MERGED_SHIFT (16U) +#define DCP_CHANNELCTRL_CH0_IRQ_MERGED(x) (((uint32_t)(((uint32_t)(x)) << DCP_CHANNELCTRL_CH0_IRQ_MERGED_SHIFT)) & DCP_CHANNELCTRL_CH0_IRQ_MERGED_MASK) +#define DCP_CHANNELCTRL_RSVD_MASK (0xFFFE0000U) +#define DCP_CHANNELCTRL_RSVD_SHIFT (17U) +#define DCP_CHANNELCTRL_RSVD(x) (((uint32_t)(((uint32_t)(x)) << DCP_CHANNELCTRL_RSVD_SHIFT)) & DCP_CHANNELCTRL_RSVD_MASK) +/*! @} */ + +/*! @name CAPABILITY0 - DCP capability 0 register */ +/*! @{ */ +#define DCP_CAPABILITY0_NUM_KEYS_MASK (0xFFU) +#define DCP_CAPABILITY0_NUM_KEYS_SHIFT (0U) +#define DCP_CAPABILITY0_NUM_KEYS(x) (((uint32_t)(((uint32_t)(x)) << DCP_CAPABILITY0_NUM_KEYS_SHIFT)) & DCP_CAPABILITY0_NUM_KEYS_MASK) +#define DCP_CAPABILITY0_NUM_CHANNELS_MASK (0xF00U) +#define DCP_CAPABILITY0_NUM_CHANNELS_SHIFT (8U) +#define DCP_CAPABILITY0_NUM_CHANNELS(x) (((uint32_t)(((uint32_t)(x)) << DCP_CAPABILITY0_NUM_CHANNELS_SHIFT)) & DCP_CAPABILITY0_NUM_CHANNELS_MASK) +#define DCP_CAPABILITY0_RSVD_MASK (0x1FFFF000U) +#define DCP_CAPABILITY0_RSVD_SHIFT (12U) +#define DCP_CAPABILITY0_RSVD(x) (((uint32_t)(((uint32_t)(x)) << DCP_CAPABILITY0_RSVD_SHIFT)) & DCP_CAPABILITY0_RSVD_MASK) +#define DCP_CAPABILITY0_DISABLE_UNIQUE_KEY_MASK (0x20000000U) +#define DCP_CAPABILITY0_DISABLE_UNIQUE_KEY_SHIFT (29U) +#define DCP_CAPABILITY0_DISABLE_UNIQUE_KEY(x) (((uint32_t)(((uint32_t)(x)) << DCP_CAPABILITY0_DISABLE_UNIQUE_KEY_SHIFT)) & DCP_CAPABILITY0_DISABLE_UNIQUE_KEY_MASK) +#define DCP_CAPABILITY0_DISABLE_DECRYPT_MASK (0x80000000U) +#define DCP_CAPABILITY0_DISABLE_DECRYPT_SHIFT (31U) +#define DCP_CAPABILITY0_DISABLE_DECRYPT(x) (((uint32_t)(((uint32_t)(x)) << DCP_CAPABILITY0_DISABLE_DECRYPT_SHIFT)) & DCP_CAPABILITY0_DISABLE_DECRYPT_MASK) +/*! @} */ + +/*! @name CAPABILITY1 - DCP capability 1 register */ +/*! @{ */ +#define DCP_CAPABILITY1_CIPHER_ALGORITHMS_MASK (0xFFFFU) +#define DCP_CAPABILITY1_CIPHER_ALGORITHMS_SHIFT (0U) +/*! CIPHER_ALGORITHMS + * 0b0000000000000001..AES128 + */ +#define DCP_CAPABILITY1_CIPHER_ALGORITHMS(x) (((uint32_t)(((uint32_t)(x)) << DCP_CAPABILITY1_CIPHER_ALGORITHMS_SHIFT)) & DCP_CAPABILITY1_CIPHER_ALGORITHMS_MASK) +#define DCP_CAPABILITY1_HASH_ALGORITHMS_MASK (0xFFFF0000U) +#define DCP_CAPABILITY1_HASH_ALGORITHMS_SHIFT (16U) +/*! HASH_ALGORITHMS + * 0b0000000000000001..SHA1 + * 0b0000000000000010..CRC32 + * 0b0000000000000100..SHA256 + */ +#define DCP_CAPABILITY1_HASH_ALGORITHMS(x) (((uint32_t)(((uint32_t)(x)) << DCP_CAPABILITY1_HASH_ALGORITHMS_SHIFT)) & DCP_CAPABILITY1_HASH_ALGORITHMS_MASK) +/*! @} */ + +/*! @name CONTEXT - DCP context buffer pointer */ +/*! @{ */ +#define DCP_CONTEXT_ADDR_MASK (0xFFFFFFFFU) +#define DCP_CONTEXT_ADDR_SHIFT (0U) +#define DCP_CONTEXT_ADDR(x) (((uint32_t)(((uint32_t)(x)) << DCP_CONTEXT_ADDR_SHIFT)) & DCP_CONTEXT_ADDR_MASK) +/*! @} */ + +/*! @name KEY - DCP key index */ +/*! @{ */ +#define DCP_KEY_SUBWORD_MASK (0x3U) +#define DCP_KEY_SUBWORD_SHIFT (0U) +#define DCP_KEY_SUBWORD(x) (((uint32_t)(((uint32_t)(x)) << DCP_KEY_SUBWORD_SHIFT)) & DCP_KEY_SUBWORD_MASK) +#define DCP_KEY_RSVD_SUBWORD_MASK (0xCU) +#define DCP_KEY_RSVD_SUBWORD_SHIFT (2U) +#define DCP_KEY_RSVD_SUBWORD(x) (((uint32_t)(((uint32_t)(x)) << DCP_KEY_RSVD_SUBWORD_SHIFT)) & DCP_KEY_RSVD_SUBWORD_MASK) +#define DCP_KEY_INDEX_MASK (0x30U) +#define DCP_KEY_INDEX_SHIFT (4U) +#define DCP_KEY_INDEX(x) (((uint32_t)(((uint32_t)(x)) << DCP_KEY_INDEX_SHIFT)) & DCP_KEY_INDEX_MASK) +#define DCP_KEY_RSVD_INDEX_MASK (0xC0U) +#define DCP_KEY_RSVD_INDEX_SHIFT (6U) +#define DCP_KEY_RSVD_INDEX(x) (((uint32_t)(((uint32_t)(x)) << DCP_KEY_RSVD_INDEX_SHIFT)) & DCP_KEY_RSVD_INDEX_MASK) +#define DCP_KEY_RSVD_MASK (0xFFFFFF00U) +#define DCP_KEY_RSVD_SHIFT (8U) +#define DCP_KEY_RSVD(x) (((uint32_t)(((uint32_t)(x)) << DCP_KEY_RSVD_SHIFT)) & DCP_KEY_RSVD_MASK) +/*! @} */ + +/*! @name KEYDATA - DCP key data */ +/*! @{ */ +#define DCP_KEYDATA_DATA_MASK (0xFFFFFFFFU) +#define DCP_KEYDATA_DATA_SHIFT (0U) +#define DCP_KEYDATA_DATA(x) (((uint32_t)(((uint32_t)(x)) << DCP_KEYDATA_DATA_SHIFT)) & DCP_KEYDATA_DATA_MASK) +/*! @} */ + +/*! @name PACKET0 - DCP work packet 0 status register */ +/*! @{ */ +#define DCP_PACKET0_ADDR_MASK (0xFFFFFFFFU) +#define DCP_PACKET0_ADDR_SHIFT (0U) +#define DCP_PACKET0_ADDR(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET0_ADDR_SHIFT)) & DCP_PACKET0_ADDR_MASK) +/*! @} */ + +/*! @name PACKET1 - DCP work packet 1 status register */ +/*! @{ */ +#define DCP_PACKET1_INTERRUPT_MASK (0x1U) +#define DCP_PACKET1_INTERRUPT_SHIFT (0U) +#define DCP_PACKET1_INTERRUPT(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_INTERRUPT_SHIFT)) & DCP_PACKET1_INTERRUPT_MASK) +#define DCP_PACKET1_DECR_SEMAPHORE_MASK (0x2U) +#define DCP_PACKET1_DECR_SEMAPHORE_SHIFT (1U) +#define DCP_PACKET1_DECR_SEMAPHORE(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_DECR_SEMAPHORE_SHIFT)) & DCP_PACKET1_DECR_SEMAPHORE_MASK) +#define DCP_PACKET1_CHAIN_MASK (0x4U) +#define DCP_PACKET1_CHAIN_SHIFT (2U) +#define DCP_PACKET1_CHAIN(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_CHAIN_SHIFT)) & DCP_PACKET1_CHAIN_MASK) +#define DCP_PACKET1_CHAIN_CONTIGUOUS_MASK (0x8U) +#define DCP_PACKET1_CHAIN_CONTIGUOUS_SHIFT (3U) +#define DCP_PACKET1_CHAIN_CONTIGUOUS(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_CHAIN_CONTIGUOUS_SHIFT)) & DCP_PACKET1_CHAIN_CONTIGUOUS_MASK) +#define DCP_PACKET1_ENABLE_MEMCOPY_MASK (0x10U) +#define DCP_PACKET1_ENABLE_MEMCOPY_SHIFT (4U) +#define DCP_PACKET1_ENABLE_MEMCOPY(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_ENABLE_MEMCOPY_SHIFT)) & DCP_PACKET1_ENABLE_MEMCOPY_MASK) +#define DCP_PACKET1_ENABLE_CIPHER_MASK (0x20U) +#define DCP_PACKET1_ENABLE_CIPHER_SHIFT (5U) +#define DCP_PACKET1_ENABLE_CIPHER(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_ENABLE_CIPHER_SHIFT)) & DCP_PACKET1_ENABLE_CIPHER_MASK) +#define DCP_PACKET1_ENABLE_HASH_MASK (0x40U) +#define DCP_PACKET1_ENABLE_HASH_SHIFT (6U) +#define DCP_PACKET1_ENABLE_HASH(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_ENABLE_HASH_SHIFT)) & DCP_PACKET1_ENABLE_HASH_MASK) +#define DCP_PACKET1_ENABLE_BLIT_MASK (0x80U) +#define DCP_PACKET1_ENABLE_BLIT_SHIFT (7U) +#define DCP_PACKET1_ENABLE_BLIT(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_ENABLE_BLIT_SHIFT)) & DCP_PACKET1_ENABLE_BLIT_MASK) +#define DCP_PACKET1_CIPHER_ENCRYPT_MASK (0x100U) +#define DCP_PACKET1_CIPHER_ENCRYPT_SHIFT (8U) +/*! CIPHER_ENCRYPT + * 0b1..ENCRYPT + * 0b0..DECRYPT + */ +#define DCP_PACKET1_CIPHER_ENCRYPT(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_CIPHER_ENCRYPT_SHIFT)) & DCP_PACKET1_CIPHER_ENCRYPT_MASK) +#define DCP_PACKET1_CIPHER_INIT_MASK (0x200U) +#define DCP_PACKET1_CIPHER_INIT_SHIFT (9U) +#define DCP_PACKET1_CIPHER_INIT(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_CIPHER_INIT_SHIFT)) & DCP_PACKET1_CIPHER_INIT_MASK) +#define DCP_PACKET1_OTP_KEY_MASK (0x400U) +#define DCP_PACKET1_OTP_KEY_SHIFT (10U) +#define DCP_PACKET1_OTP_KEY(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_OTP_KEY_SHIFT)) & DCP_PACKET1_OTP_KEY_MASK) +#define DCP_PACKET1_PAYLOAD_KEY_MASK (0x800U) +#define DCP_PACKET1_PAYLOAD_KEY_SHIFT (11U) +#define DCP_PACKET1_PAYLOAD_KEY(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_PAYLOAD_KEY_SHIFT)) & DCP_PACKET1_PAYLOAD_KEY_MASK) +#define DCP_PACKET1_HASH_INIT_MASK (0x1000U) +#define DCP_PACKET1_HASH_INIT_SHIFT (12U) +#define DCP_PACKET1_HASH_INIT(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_HASH_INIT_SHIFT)) & DCP_PACKET1_HASH_INIT_MASK) +#define DCP_PACKET1_HASH_TERM_MASK (0x2000U) +#define DCP_PACKET1_HASH_TERM_SHIFT (13U) +#define DCP_PACKET1_HASH_TERM(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_HASH_TERM_SHIFT)) & DCP_PACKET1_HASH_TERM_MASK) +#define DCP_PACKET1_CHECK_HASH_MASK (0x4000U) +#define DCP_PACKET1_CHECK_HASH_SHIFT (14U) +#define DCP_PACKET1_CHECK_HASH(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_CHECK_HASH_SHIFT)) & DCP_PACKET1_CHECK_HASH_MASK) +#define DCP_PACKET1_HASH_OUTPUT_MASK (0x8000U) +#define DCP_PACKET1_HASH_OUTPUT_SHIFT (15U) +/*! HASH_OUTPUT + * 0b0..INPUT + * 0b1..OUTPUT + */ +#define DCP_PACKET1_HASH_OUTPUT(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_HASH_OUTPUT_SHIFT)) & DCP_PACKET1_HASH_OUTPUT_MASK) +#define DCP_PACKET1_CONSTANT_FILL_MASK (0x10000U) +#define DCP_PACKET1_CONSTANT_FILL_SHIFT (16U) +#define DCP_PACKET1_CONSTANT_FILL(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_CONSTANT_FILL_SHIFT)) & DCP_PACKET1_CONSTANT_FILL_MASK) +#define DCP_PACKET1_TEST_SEMA_IRQ_MASK (0x20000U) +#define DCP_PACKET1_TEST_SEMA_IRQ_SHIFT (17U) +#define DCP_PACKET1_TEST_SEMA_IRQ(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_TEST_SEMA_IRQ_SHIFT)) & DCP_PACKET1_TEST_SEMA_IRQ_MASK) +#define DCP_PACKET1_KEY_BYTESWAP_MASK (0x40000U) +#define DCP_PACKET1_KEY_BYTESWAP_SHIFT (18U) +#define DCP_PACKET1_KEY_BYTESWAP(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_KEY_BYTESWAP_SHIFT)) & DCP_PACKET1_KEY_BYTESWAP_MASK) +#define DCP_PACKET1_KEY_WORDSWAP_MASK (0x80000U) +#define DCP_PACKET1_KEY_WORDSWAP_SHIFT (19U) +#define DCP_PACKET1_KEY_WORDSWAP(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_KEY_WORDSWAP_SHIFT)) & DCP_PACKET1_KEY_WORDSWAP_MASK) +#define DCP_PACKET1_INPUT_BYTESWAP_MASK (0x100000U) +#define DCP_PACKET1_INPUT_BYTESWAP_SHIFT (20U) +#define DCP_PACKET1_INPUT_BYTESWAP(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_INPUT_BYTESWAP_SHIFT)) & DCP_PACKET1_INPUT_BYTESWAP_MASK) +#define DCP_PACKET1_INPUT_WORDSWAP_MASK (0x200000U) +#define DCP_PACKET1_INPUT_WORDSWAP_SHIFT (21U) +#define DCP_PACKET1_INPUT_WORDSWAP(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_INPUT_WORDSWAP_SHIFT)) & DCP_PACKET1_INPUT_WORDSWAP_MASK) +#define DCP_PACKET1_OUTPUT_BYTESWAP_MASK (0x400000U) +#define DCP_PACKET1_OUTPUT_BYTESWAP_SHIFT (22U) +#define DCP_PACKET1_OUTPUT_BYTESWAP(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_OUTPUT_BYTESWAP_SHIFT)) & DCP_PACKET1_OUTPUT_BYTESWAP_MASK) +#define DCP_PACKET1_OUTPUT_WORDSWAP_MASK (0x800000U) +#define DCP_PACKET1_OUTPUT_WORDSWAP_SHIFT (23U) +#define DCP_PACKET1_OUTPUT_WORDSWAP(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_OUTPUT_WORDSWAP_SHIFT)) & DCP_PACKET1_OUTPUT_WORDSWAP_MASK) +#define DCP_PACKET1_TAG_MASK (0xFF000000U) +#define DCP_PACKET1_TAG_SHIFT (24U) +#define DCP_PACKET1_TAG(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_TAG_SHIFT)) & DCP_PACKET1_TAG_MASK) +/*! @} */ + +/*! @name PACKET2 - DCP work packet 2 status register */ +/*! @{ */ +#define DCP_PACKET2_CIPHER_SELECT_MASK (0xFU) +#define DCP_PACKET2_CIPHER_SELECT_SHIFT (0U) +/*! CIPHER_SELECT + * 0b0000..AES128 + */ +#define DCP_PACKET2_CIPHER_SELECT(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET2_CIPHER_SELECT_SHIFT)) & DCP_PACKET2_CIPHER_SELECT_MASK) +#define DCP_PACKET2_CIPHER_MODE_MASK (0xF0U) +#define DCP_PACKET2_CIPHER_MODE_SHIFT (4U) +/*! CIPHER_MODE + * 0b0000..ECB + * 0b0001..CBC + */ +#define DCP_PACKET2_CIPHER_MODE(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET2_CIPHER_MODE_SHIFT)) & DCP_PACKET2_CIPHER_MODE_MASK) +#define DCP_PACKET2_KEY_SELECT_MASK (0xFF00U) +#define DCP_PACKET2_KEY_SELECT_SHIFT (8U) +/*! KEY_SELECT + * 0b00000000..KEY0 + * 0b00000001..KEY1 + * 0b00000010..KEY2 + * 0b00000011..KEY3 + * 0b11111110..UNIQUE_KEY + * 0b11111111..OTP_KEY + */ +#define DCP_PACKET2_KEY_SELECT(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET2_KEY_SELECT_SHIFT)) & DCP_PACKET2_KEY_SELECT_MASK) +#define DCP_PACKET2_HASH_SELECT_MASK (0xF0000U) +#define DCP_PACKET2_HASH_SELECT_SHIFT (16U) +/*! HASH_SELECT + * 0b0000..SHA1 + * 0b0001..CRC32 + * 0b0010..SHA256 + */ +#define DCP_PACKET2_HASH_SELECT(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET2_HASH_SELECT_SHIFT)) & DCP_PACKET2_HASH_SELECT_MASK) +#define DCP_PACKET2_RSVD_MASK (0xF00000U) +#define DCP_PACKET2_RSVD_SHIFT (20U) +#define DCP_PACKET2_RSVD(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET2_RSVD_SHIFT)) & DCP_PACKET2_RSVD_MASK) +#define DCP_PACKET2_CIPHER_CFG_MASK (0xFF000000U) +#define DCP_PACKET2_CIPHER_CFG_SHIFT (24U) +#define DCP_PACKET2_CIPHER_CFG(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET2_CIPHER_CFG_SHIFT)) & DCP_PACKET2_CIPHER_CFG_MASK) +/*! @} */ + +/*! @name PACKET3 - DCP work packet 3 status register */ +/*! @{ */ +#define DCP_PACKET3_ADDR_MASK (0xFFFFFFFFU) +#define DCP_PACKET3_ADDR_SHIFT (0U) +#define DCP_PACKET3_ADDR(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET3_ADDR_SHIFT)) & DCP_PACKET3_ADDR_MASK) +/*! @} */ + +/*! @name PACKET4 - DCP work packet 4 status register */ +/*! @{ */ +#define DCP_PACKET4_ADDR_MASK (0xFFFFFFFFU) +#define DCP_PACKET4_ADDR_SHIFT (0U) +#define DCP_PACKET4_ADDR(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET4_ADDR_SHIFT)) & DCP_PACKET4_ADDR_MASK) +/*! @} */ + +/*! @name PACKET5 - DCP work packet 5 status register */ +/*! @{ */ +#define DCP_PACKET5_COUNT_MASK (0xFFFFFFFFU) +#define DCP_PACKET5_COUNT_SHIFT (0U) +#define DCP_PACKET5_COUNT(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET5_COUNT_SHIFT)) & DCP_PACKET5_COUNT_MASK) +/*! @} */ + +/*! @name PACKET6 - DCP work packet 6 status register */ +/*! @{ */ +#define DCP_PACKET6_ADDR_MASK (0xFFFFFFFFU) +#define DCP_PACKET6_ADDR_SHIFT (0U) +#define DCP_PACKET6_ADDR(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET6_ADDR_SHIFT)) & DCP_PACKET6_ADDR_MASK) +/*! @} */ + +/*! @name CH0CMDPTR - DCP channel 0 command pointer address register */ +/*! @{ */ +#define DCP_CH0CMDPTR_ADDR_MASK (0xFFFFFFFFU) +#define DCP_CH0CMDPTR_ADDR_SHIFT (0U) +#define DCP_CH0CMDPTR_ADDR(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0CMDPTR_ADDR_SHIFT)) & DCP_CH0CMDPTR_ADDR_MASK) +/*! @} */ + +/*! @name CH0SEMA - DCP channel 0 semaphore register */ +/*! @{ */ +#define DCP_CH0SEMA_INCREMENT_MASK (0xFFU) +#define DCP_CH0SEMA_INCREMENT_SHIFT (0U) +#define DCP_CH0SEMA_INCREMENT(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0SEMA_INCREMENT_SHIFT)) & DCP_CH0SEMA_INCREMENT_MASK) +#define DCP_CH0SEMA_VALUE_MASK (0xFF0000U) +#define DCP_CH0SEMA_VALUE_SHIFT (16U) +#define DCP_CH0SEMA_VALUE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0SEMA_VALUE_SHIFT)) & DCP_CH0SEMA_VALUE_MASK) +/*! @} */ + +/*! @name CH0STAT - DCP channel 0 status register */ +/*! @{ */ +#define DCP_CH0STAT_RSVD_COMPLETE_MASK (0x1U) +#define DCP_CH0STAT_RSVD_COMPLETE_SHIFT (0U) +#define DCP_CH0STAT_RSVD_COMPLETE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_RSVD_COMPLETE_SHIFT)) & DCP_CH0STAT_RSVD_COMPLETE_MASK) +#define DCP_CH0STAT_HASH_MISMATCH_MASK (0x2U) +#define DCP_CH0STAT_HASH_MISMATCH_SHIFT (1U) +#define DCP_CH0STAT_HASH_MISMATCH(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_HASH_MISMATCH_SHIFT)) & DCP_CH0STAT_HASH_MISMATCH_MASK) +#define DCP_CH0STAT_ERROR_SETUP_MASK (0x4U) +#define DCP_CH0STAT_ERROR_SETUP_SHIFT (2U) +#define DCP_CH0STAT_ERROR_SETUP(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_ERROR_SETUP_SHIFT)) & DCP_CH0STAT_ERROR_SETUP_MASK) +#define DCP_CH0STAT_ERROR_PACKET_MASK (0x8U) +#define DCP_CH0STAT_ERROR_PACKET_SHIFT (3U) +#define DCP_CH0STAT_ERROR_PACKET(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_ERROR_PACKET_SHIFT)) & DCP_CH0STAT_ERROR_PACKET_MASK) +#define DCP_CH0STAT_ERROR_SRC_MASK (0x10U) +#define DCP_CH0STAT_ERROR_SRC_SHIFT (4U) +#define DCP_CH0STAT_ERROR_SRC(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_ERROR_SRC_SHIFT)) & DCP_CH0STAT_ERROR_SRC_MASK) +#define DCP_CH0STAT_ERROR_DST_MASK (0x20U) +#define DCP_CH0STAT_ERROR_DST_SHIFT (5U) +#define DCP_CH0STAT_ERROR_DST(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_ERROR_DST_SHIFT)) & DCP_CH0STAT_ERROR_DST_MASK) +#define DCP_CH0STAT_ERROR_PAGEFAULT_MASK (0x40U) +#define DCP_CH0STAT_ERROR_PAGEFAULT_SHIFT (6U) +#define DCP_CH0STAT_ERROR_PAGEFAULT(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_ERROR_PAGEFAULT_SHIFT)) & DCP_CH0STAT_ERROR_PAGEFAULT_MASK) +#define DCP_CH0STAT_ERROR_CODE_MASK (0xFF0000U) +#define DCP_CH0STAT_ERROR_CODE_SHIFT (16U) +/*! ERROR_CODE + * 0b00000001..Error signalled because the next pointer is 0x00000000 + * 0b00000010..Error signalled because the semaphore is non-zero and neither chain bit is set + * 0b00000011..Error signalled because an error is reported reading/writing the context buffer + * 0b00000100..Error signalled because an error is reported reading/writing the payload + * 0b00000101..Error signalled because the control packet specifies an invalid mode select (for instance, blit + hash) + */ +#define DCP_CH0STAT_ERROR_CODE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_ERROR_CODE_SHIFT)) & DCP_CH0STAT_ERROR_CODE_MASK) +#define DCP_CH0STAT_TAG_MASK (0xFF000000U) +#define DCP_CH0STAT_TAG_SHIFT (24U) +#define DCP_CH0STAT_TAG(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_TAG_SHIFT)) & DCP_CH0STAT_TAG_MASK) +/*! @} */ + +/*! @name CH0OPTS - DCP channel 0 options register */ +/*! @{ */ +#define DCP_CH0OPTS_RECOVERY_TIMER_MASK (0xFFFFU) +#define DCP_CH0OPTS_RECOVERY_TIMER_SHIFT (0U) +#define DCP_CH0OPTS_RECOVERY_TIMER(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0OPTS_RECOVERY_TIMER_SHIFT)) & DCP_CH0OPTS_RECOVERY_TIMER_MASK) +#define DCP_CH0OPTS_RSVD_MASK (0xFFFF0000U) +#define DCP_CH0OPTS_RSVD_SHIFT (16U) +#define DCP_CH0OPTS_RSVD(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0OPTS_RSVD_SHIFT)) & DCP_CH0OPTS_RSVD_MASK) +/*! @} */ + +/*! @name CH1CMDPTR - DCP channel 1 command pointer address register */ +/*! @{ */ +#define DCP_CH1CMDPTR_ADDR_MASK (0xFFFFFFFFU) +#define DCP_CH1CMDPTR_ADDR_SHIFT (0U) +#define DCP_CH1CMDPTR_ADDR(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1CMDPTR_ADDR_SHIFT)) & DCP_CH1CMDPTR_ADDR_MASK) +/*! @} */ + +/*! @name CH1SEMA - DCP channel 1 semaphore register */ +/*! @{ */ +#define DCP_CH1SEMA_INCREMENT_MASK (0xFFU) +#define DCP_CH1SEMA_INCREMENT_SHIFT (0U) +#define DCP_CH1SEMA_INCREMENT(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1SEMA_INCREMENT_SHIFT)) & DCP_CH1SEMA_INCREMENT_MASK) +#define DCP_CH1SEMA_VALUE_MASK (0xFF0000U) +#define DCP_CH1SEMA_VALUE_SHIFT (16U) +#define DCP_CH1SEMA_VALUE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1SEMA_VALUE_SHIFT)) & DCP_CH1SEMA_VALUE_MASK) +/*! @} */ + +/*! @name CH1STAT - DCP channel 1 status register */ +/*! @{ */ +#define DCP_CH1STAT_RSVD_COMPLETE_MASK (0x1U) +#define DCP_CH1STAT_RSVD_COMPLETE_SHIFT (0U) +#define DCP_CH1STAT_RSVD_COMPLETE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_RSVD_COMPLETE_SHIFT)) & DCP_CH1STAT_RSVD_COMPLETE_MASK) +#define DCP_CH1STAT_HASH_MISMATCH_MASK (0x2U) +#define DCP_CH1STAT_HASH_MISMATCH_SHIFT (1U) +#define DCP_CH1STAT_HASH_MISMATCH(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_HASH_MISMATCH_SHIFT)) & DCP_CH1STAT_HASH_MISMATCH_MASK) +#define DCP_CH1STAT_ERROR_SETUP_MASK (0x4U) +#define DCP_CH1STAT_ERROR_SETUP_SHIFT (2U) +#define DCP_CH1STAT_ERROR_SETUP(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_ERROR_SETUP_SHIFT)) & DCP_CH1STAT_ERROR_SETUP_MASK) +#define DCP_CH1STAT_ERROR_PACKET_MASK (0x8U) +#define DCP_CH1STAT_ERROR_PACKET_SHIFT (3U) +#define DCP_CH1STAT_ERROR_PACKET(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_ERROR_PACKET_SHIFT)) & DCP_CH1STAT_ERROR_PACKET_MASK) +#define DCP_CH1STAT_ERROR_SRC_MASK (0x10U) +#define DCP_CH1STAT_ERROR_SRC_SHIFT (4U) +#define DCP_CH1STAT_ERROR_SRC(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_ERROR_SRC_SHIFT)) & DCP_CH1STAT_ERROR_SRC_MASK) +#define DCP_CH1STAT_ERROR_DST_MASK (0x20U) +#define DCP_CH1STAT_ERROR_DST_SHIFT (5U) +#define DCP_CH1STAT_ERROR_DST(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_ERROR_DST_SHIFT)) & DCP_CH1STAT_ERROR_DST_MASK) +#define DCP_CH1STAT_ERROR_PAGEFAULT_MASK (0x40U) +#define DCP_CH1STAT_ERROR_PAGEFAULT_SHIFT (6U) +#define DCP_CH1STAT_ERROR_PAGEFAULT(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_ERROR_PAGEFAULT_SHIFT)) & DCP_CH1STAT_ERROR_PAGEFAULT_MASK) +#define DCP_CH1STAT_ERROR_CODE_MASK (0xFF0000U) +#define DCP_CH1STAT_ERROR_CODE_SHIFT (16U) +/*! ERROR_CODE + * 0b00000001..Error is signalled because the next pointer is 0x00000000. + * 0b00000010..Error is signalled because the semaphore is of a non-zero value and neither of the chain bits is set. + * 0b00000011..Error is signalled because an error was reported when reading/writing the context buffer. + * 0b00000100..Error is signalled because an error was reported when reading/writing the payload. + * 0b00000101..Error is signalled because the control packet specifies an invalid mode select (for example, blit + hash). + */ +#define DCP_CH1STAT_ERROR_CODE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_ERROR_CODE_SHIFT)) & DCP_CH1STAT_ERROR_CODE_MASK) +#define DCP_CH1STAT_TAG_MASK (0xFF000000U) +#define DCP_CH1STAT_TAG_SHIFT (24U) +#define DCP_CH1STAT_TAG(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_TAG_SHIFT)) & DCP_CH1STAT_TAG_MASK) +/*! @} */ + +/*! @name CH1OPTS - DCP channel 1 options register */ +/*! @{ */ +#define DCP_CH1OPTS_RECOVERY_TIMER_MASK (0xFFFFU) +#define DCP_CH1OPTS_RECOVERY_TIMER_SHIFT (0U) +#define DCP_CH1OPTS_RECOVERY_TIMER(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1OPTS_RECOVERY_TIMER_SHIFT)) & DCP_CH1OPTS_RECOVERY_TIMER_MASK) +#define DCP_CH1OPTS_RSVD_MASK (0xFFFF0000U) +#define DCP_CH1OPTS_RSVD_SHIFT (16U) +#define DCP_CH1OPTS_RSVD(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1OPTS_RSVD_SHIFT)) & DCP_CH1OPTS_RSVD_MASK) +/*! @} */ + +/*! @name CH2CMDPTR - DCP channel 2 command pointer address register */ +/*! @{ */ +#define DCP_CH2CMDPTR_ADDR_MASK (0xFFFFFFFFU) +#define DCP_CH2CMDPTR_ADDR_SHIFT (0U) +#define DCP_CH2CMDPTR_ADDR(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2CMDPTR_ADDR_SHIFT)) & DCP_CH2CMDPTR_ADDR_MASK) +/*! @} */ + +/*! @name CH2SEMA - DCP channel 2 semaphore register */ +/*! @{ */ +#define DCP_CH2SEMA_INCREMENT_MASK (0xFFU) +#define DCP_CH2SEMA_INCREMENT_SHIFT (0U) +#define DCP_CH2SEMA_INCREMENT(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2SEMA_INCREMENT_SHIFT)) & DCP_CH2SEMA_INCREMENT_MASK) +#define DCP_CH2SEMA_VALUE_MASK (0xFF0000U) +#define DCP_CH2SEMA_VALUE_SHIFT (16U) +#define DCP_CH2SEMA_VALUE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2SEMA_VALUE_SHIFT)) & DCP_CH2SEMA_VALUE_MASK) +/*! @} */ + +/*! @name CH2STAT - DCP channel 2 status register */ +/*! @{ */ +#define DCP_CH2STAT_RSVD_COMPLETE_MASK (0x1U) +#define DCP_CH2STAT_RSVD_COMPLETE_SHIFT (0U) +#define DCP_CH2STAT_RSVD_COMPLETE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_RSVD_COMPLETE_SHIFT)) & DCP_CH2STAT_RSVD_COMPLETE_MASK) +#define DCP_CH2STAT_HASH_MISMATCH_MASK (0x2U) +#define DCP_CH2STAT_HASH_MISMATCH_SHIFT (1U) +#define DCP_CH2STAT_HASH_MISMATCH(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_HASH_MISMATCH_SHIFT)) & DCP_CH2STAT_HASH_MISMATCH_MASK) +#define DCP_CH2STAT_ERROR_SETUP_MASK (0x4U) +#define DCP_CH2STAT_ERROR_SETUP_SHIFT (2U) +#define DCP_CH2STAT_ERROR_SETUP(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_ERROR_SETUP_SHIFT)) & DCP_CH2STAT_ERROR_SETUP_MASK) +#define DCP_CH2STAT_ERROR_PACKET_MASK (0x8U) +#define DCP_CH2STAT_ERROR_PACKET_SHIFT (3U) +#define DCP_CH2STAT_ERROR_PACKET(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_ERROR_PACKET_SHIFT)) & DCP_CH2STAT_ERROR_PACKET_MASK) +#define DCP_CH2STAT_ERROR_SRC_MASK (0x10U) +#define DCP_CH2STAT_ERROR_SRC_SHIFT (4U) +#define DCP_CH2STAT_ERROR_SRC(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_ERROR_SRC_SHIFT)) & DCP_CH2STAT_ERROR_SRC_MASK) +#define DCP_CH2STAT_ERROR_DST_MASK (0x20U) +#define DCP_CH2STAT_ERROR_DST_SHIFT (5U) +#define DCP_CH2STAT_ERROR_DST(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_ERROR_DST_SHIFT)) & DCP_CH2STAT_ERROR_DST_MASK) +#define DCP_CH2STAT_ERROR_PAGEFAULT_MASK (0x40U) +#define DCP_CH2STAT_ERROR_PAGEFAULT_SHIFT (6U) +#define DCP_CH2STAT_ERROR_PAGEFAULT(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_ERROR_PAGEFAULT_SHIFT)) & DCP_CH2STAT_ERROR_PAGEFAULT_MASK) +#define DCP_CH2STAT_ERROR_CODE_MASK (0xFF0000U) +#define DCP_CH2STAT_ERROR_CODE_SHIFT (16U) +/*! ERROR_CODE + * 0b00000001..Error is signalled because the next pointer is 0x00000000. + * 0b00000010..Error is signalled because the semaphore is of a non-zero value and neither of the chain bits is set. + * 0b00000011..Error is signalled because an error was reported while reading/writing the context buffer. + * 0b00000100..Error is signalled because an error was reported while reading/writing the payload. + * 0b00000101..Error is signalled because the control packet specifies an invalid mode select (for instance, blit + hash). + */ +#define DCP_CH2STAT_ERROR_CODE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_ERROR_CODE_SHIFT)) & DCP_CH2STAT_ERROR_CODE_MASK) +#define DCP_CH2STAT_TAG_MASK (0xFF000000U) +#define DCP_CH2STAT_TAG_SHIFT (24U) +#define DCP_CH2STAT_TAG(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_TAG_SHIFT)) & DCP_CH2STAT_TAG_MASK) +/*! @} */ + +/*! @name CH2OPTS - DCP channel 2 options register */ +/*! @{ */ +#define DCP_CH2OPTS_RECOVERY_TIMER_MASK (0xFFFFU) +#define DCP_CH2OPTS_RECOVERY_TIMER_SHIFT (0U) +#define DCP_CH2OPTS_RECOVERY_TIMER(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2OPTS_RECOVERY_TIMER_SHIFT)) & DCP_CH2OPTS_RECOVERY_TIMER_MASK) +#define DCP_CH2OPTS_RSVD_MASK (0xFFFF0000U) +#define DCP_CH2OPTS_RSVD_SHIFT (16U) +#define DCP_CH2OPTS_RSVD(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2OPTS_RSVD_SHIFT)) & DCP_CH2OPTS_RSVD_MASK) +/*! @} */ + +/*! @name CH3CMDPTR - DCP channel 3 command pointer address register */ +/*! @{ */ +#define DCP_CH3CMDPTR_ADDR_MASK (0xFFFFFFFFU) +#define DCP_CH3CMDPTR_ADDR_SHIFT (0U) +#define DCP_CH3CMDPTR_ADDR(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3CMDPTR_ADDR_SHIFT)) & DCP_CH3CMDPTR_ADDR_MASK) +/*! @} */ + +/*! @name CH3SEMA - DCP channel 3 semaphore register */ +/*! @{ */ +#define DCP_CH3SEMA_INCREMENT_MASK (0xFFU) +#define DCP_CH3SEMA_INCREMENT_SHIFT (0U) +#define DCP_CH3SEMA_INCREMENT(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3SEMA_INCREMENT_SHIFT)) & DCP_CH3SEMA_INCREMENT_MASK) +#define DCP_CH3SEMA_VALUE_MASK (0xFF0000U) +#define DCP_CH3SEMA_VALUE_SHIFT (16U) +#define DCP_CH3SEMA_VALUE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3SEMA_VALUE_SHIFT)) & DCP_CH3SEMA_VALUE_MASK) +/*! @} */ + +/*! @name CH3STAT - DCP channel 3 status register */ +/*! @{ */ +#define DCP_CH3STAT_RSVD_COMPLETE_MASK (0x1U) +#define DCP_CH3STAT_RSVD_COMPLETE_SHIFT (0U) +#define DCP_CH3STAT_RSVD_COMPLETE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3STAT_RSVD_COMPLETE_SHIFT)) & DCP_CH3STAT_RSVD_COMPLETE_MASK) +#define DCP_CH3STAT_HASH_MISMATCH_MASK (0x2U) +#define DCP_CH3STAT_HASH_MISMATCH_SHIFT (1U) +#define DCP_CH3STAT_HASH_MISMATCH(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3STAT_HASH_MISMATCH_SHIFT)) & DCP_CH3STAT_HASH_MISMATCH_MASK) +#define DCP_CH3STAT_ERROR_SETUP_MASK (0x4U) +#define DCP_CH3STAT_ERROR_SETUP_SHIFT (2U) +#define DCP_CH3STAT_ERROR_SETUP(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3STAT_ERROR_SETUP_SHIFT)) & DCP_CH3STAT_ERROR_SETUP_MASK) +#define DCP_CH3STAT_ERROR_PACKET_MASK (0x8U) +#define DCP_CH3STAT_ERROR_PACKET_SHIFT (3U) +#define DCP_CH3STAT_ERROR_PACKET(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3STAT_ERROR_PACKET_SHIFT)) & DCP_CH3STAT_ERROR_PACKET_MASK) +#define DCP_CH3STAT_ERROR_SRC_MASK (0x10U) +#define DCP_CH3STAT_ERROR_SRC_SHIFT (4U) +#define DCP_CH3STAT_ERROR_SRC(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3STAT_ERROR_SRC_SHIFT)) & DCP_CH3STAT_ERROR_SRC_MASK) +#define DCP_CH3STAT_ERROR_DST_MASK (0x20U) +#define DCP_CH3STAT_ERROR_DST_SHIFT (5U) +#define DCP_CH3STAT_ERROR_DST(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3STAT_ERROR_DST_SHIFT)) & DCP_CH3STAT_ERROR_DST_MASK) +#define DCP_CH3STAT_ERROR_PAGEFAULT_MASK (0x40U) +#define DCP_CH3STAT_ERROR_PAGEFAULT_SHIFT (6U) +#define DCP_CH3STAT_ERROR_PAGEFAULT(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3STAT_ERROR_PAGEFAULT_SHIFT)) & DCP_CH3STAT_ERROR_PAGEFAULT_MASK) +#define DCP_CH3STAT_ERROR_CODE_MASK (0xFF0000U) +#define DCP_CH3STAT_ERROR_CODE_SHIFT (16U) +/*! ERROR_CODE + * 0b00000001..Error is signalled because the next pointer is 0x00000000. + * 0b00000010..Error is signalled because the semaphore is of a non-zero value and neither of the chain bits is set. + * 0b00000011..Error is signalled because an error was reported while reading/writing the context buffer. + * 0b00000100..Error is signalled because an error was reported while reading/writing the payload. + * 0b00000101..Error is signalled because the control packet specifies an invalid mode select (for example, blit + hash). + */ +#define DCP_CH3STAT_ERROR_CODE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3STAT_ERROR_CODE_SHIFT)) & DCP_CH3STAT_ERROR_CODE_MASK) +#define DCP_CH3STAT_TAG_MASK (0xFF000000U) +#define DCP_CH3STAT_TAG_SHIFT (24U) +#define DCP_CH3STAT_TAG(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3STAT_TAG_SHIFT)) & DCP_CH3STAT_TAG_MASK) +/*! @} */ + +/*! @name CH3OPTS - DCP channel 3 options register */ +/*! @{ */ +#define DCP_CH3OPTS_RECOVERY_TIMER_MASK (0xFFFFU) +#define DCP_CH3OPTS_RECOVERY_TIMER_SHIFT (0U) +#define DCP_CH3OPTS_RECOVERY_TIMER(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3OPTS_RECOVERY_TIMER_SHIFT)) & DCP_CH3OPTS_RECOVERY_TIMER_MASK) +#define DCP_CH3OPTS_RSVD_MASK (0xFFFF0000U) +#define DCP_CH3OPTS_RSVD_SHIFT (16U) +#define DCP_CH3OPTS_RSVD(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3OPTS_RSVD_SHIFT)) & DCP_CH3OPTS_RSVD_MASK) +/*! @} */ + +/*! @name DBGSELECT - DCP debug select register */ +/*! @{ */ +#define DCP_DBGSELECT_INDEX_MASK (0xFFU) +#define DCP_DBGSELECT_INDEX_SHIFT (0U) +/*! INDEX + * 0b00000001..CONTROL + * 0b00010000..OTPKEY0 + * 0b00010001..OTPKEY1 + * 0b00010010..OTPKEY2 + * 0b00010011..OTPKEY3 + */ +#define DCP_DBGSELECT_INDEX(x) (((uint32_t)(((uint32_t)(x)) << DCP_DBGSELECT_INDEX_SHIFT)) & DCP_DBGSELECT_INDEX_MASK) +#define DCP_DBGSELECT_RSVD_MASK (0xFFFFFF00U) +#define DCP_DBGSELECT_RSVD_SHIFT (8U) +#define DCP_DBGSELECT_RSVD(x) (((uint32_t)(((uint32_t)(x)) << DCP_DBGSELECT_RSVD_SHIFT)) & DCP_DBGSELECT_RSVD_MASK) +/*! @} */ + +/*! @name DBGDATA - DCP debug data register */ +/*! @{ */ +#define DCP_DBGDATA_DATA_MASK (0xFFFFFFFFU) +#define DCP_DBGDATA_DATA_SHIFT (0U) +#define DCP_DBGDATA_DATA(x) (((uint32_t)(((uint32_t)(x)) << DCP_DBGDATA_DATA_SHIFT)) & DCP_DBGDATA_DATA_MASK) +/*! @} */ + +/*! @name PAGETABLE - DCP page table register */ +/*! @{ */ +#define DCP_PAGETABLE_ENABLE_MASK (0x1U) +#define DCP_PAGETABLE_ENABLE_SHIFT (0U) +#define DCP_PAGETABLE_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << DCP_PAGETABLE_ENABLE_SHIFT)) & DCP_PAGETABLE_ENABLE_MASK) +#define DCP_PAGETABLE_FLUSH_MASK (0x2U) +#define DCP_PAGETABLE_FLUSH_SHIFT (1U) +#define DCP_PAGETABLE_FLUSH(x) (((uint32_t)(((uint32_t)(x)) << DCP_PAGETABLE_FLUSH_SHIFT)) & DCP_PAGETABLE_FLUSH_MASK) +#define DCP_PAGETABLE_BASE_MASK (0xFFFFFFFCU) +#define DCP_PAGETABLE_BASE_SHIFT (2U) +#define DCP_PAGETABLE_BASE(x) (((uint32_t)(((uint32_t)(x)) << DCP_PAGETABLE_BASE_SHIFT)) & DCP_PAGETABLE_BASE_MASK) +/*! @} */ + +/*! @name VERSION - DCP version register */ +/*! @{ */ +#define DCP_VERSION_STEP_MASK (0xFFFFU) +#define DCP_VERSION_STEP_SHIFT (0U) +#define DCP_VERSION_STEP(x) (((uint32_t)(((uint32_t)(x)) << DCP_VERSION_STEP_SHIFT)) & DCP_VERSION_STEP_MASK) +#define DCP_VERSION_MINOR_MASK (0xFF0000U) +#define DCP_VERSION_MINOR_SHIFT (16U) +#define DCP_VERSION_MINOR(x) (((uint32_t)(((uint32_t)(x)) << DCP_VERSION_MINOR_SHIFT)) & DCP_VERSION_MINOR_MASK) +#define DCP_VERSION_MAJOR_MASK (0xFF000000U) +#define DCP_VERSION_MAJOR_SHIFT (24U) +#define DCP_VERSION_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << DCP_VERSION_MAJOR_SHIFT)) & DCP_VERSION_MAJOR_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group DCP_Register_Masks */ + + +/* DCP - Peripheral instance base addresses */ +/** Peripheral DCP base address */ +#define DCP_BASE (0x402FC000u) +/** Peripheral DCP base pointer */ +#define DCP ((DCP_Type *)DCP_BASE) +/** Array initializer of DCP peripheral base addresses */ +#define DCP_BASE_ADDRS { DCP_BASE } +/** Array initializer of DCP peripheral base pointers */ +#define DCP_BASE_PTRS { DCP } +/** Interrupt vectors for the DCP peripheral type */ +#define DCP_IRQS { DCP_IRQn } +#define DCP_VMI_IRQS { DCP_VMI_IRQn } + +/*! + * @} + */ /* end of group DCP_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- DMA Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup DMA_Peripheral_Access_Layer DMA Peripheral Access Layer + * @{ + */ + +/** DMA - Register Layout Typedef */ +typedef struct { + __IO uint32_t CR; /**< Control Register, offset: 0x0 */ + __I uint32_t ES; /**< Error Status Register, offset: 0x4 */ + uint8_t RESERVED_0[4]; + __IO uint32_t ERQ; /**< Enable Request Register, offset: 0xC */ + uint8_t RESERVED_1[4]; + __IO uint32_t EEI; /**< Enable Error Interrupt Register, offset: 0x14 */ + __O uint8_t CEEI; /**< Clear Enable Error Interrupt Register, offset: 0x18 */ + __O uint8_t SEEI; /**< Set Enable Error Interrupt Register, offset: 0x19 */ + __O uint8_t CERQ; /**< Clear Enable Request Register, offset: 0x1A */ + __O uint8_t SERQ; /**< Set Enable Request Register, offset: 0x1B */ + __O uint8_t CDNE; /**< Clear DONE Status Bit Register, offset: 0x1C */ + __O uint8_t SSRT; /**< Set START Bit Register, offset: 0x1D */ + __O uint8_t CERR; /**< Clear Error Register, offset: 0x1E */ + __O uint8_t CINT; /**< Clear Interrupt Request Register, offset: 0x1F */ + uint8_t RESERVED_2[4]; + __IO uint32_t INT; /**< Interrupt Request Register, offset: 0x24 */ + uint8_t RESERVED_3[4]; + __IO uint32_t ERR; /**< Error Register, offset: 0x2C */ + uint8_t RESERVED_4[4]; + __I uint32_t HRS; /**< Hardware Request Status Register, offset: 0x34 */ + uint8_t RESERVED_5[12]; + __IO uint32_t EARS; /**< Enable Asynchronous Request in Stop Register, offset: 0x44 */ + uint8_t RESERVED_6[184]; + __IO uint8_t DCHPRI3; /**< Channel n Priority Register, offset: 0x100 */ + __IO uint8_t DCHPRI2; /**< Channel n Priority Register, offset: 0x101 */ + __IO uint8_t DCHPRI1; /**< Channel n Priority Register, offset: 0x102 */ + __IO uint8_t DCHPRI0; /**< Channel n Priority Register, offset: 0x103 */ + __IO uint8_t DCHPRI7; /**< Channel n Priority Register, offset: 0x104 */ + __IO uint8_t DCHPRI6; /**< Channel n Priority Register, offset: 0x105 */ + __IO uint8_t DCHPRI5; /**< Channel n Priority Register, offset: 0x106 */ + __IO uint8_t DCHPRI4; /**< Channel n Priority Register, offset: 0x107 */ + __IO uint8_t DCHPRI11; /**< Channel n Priority Register, offset: 0x108 */ + __IO uint8_t DCHPRI10; /**< Channel n Priority Register, offset: 0x109 */ + __IO uint8_t DCHPRI9; /**< Channel n Priority Register, offset: 0x10A */ + __IO uint8_t DCHPRI8; /**< Channel n Priority Register, offset: 0x10B */ + __IO uint8_t DCHPRI15; /**< Channel n Priority Register, offset: 0x10C */ + __IO uint8_t DCHPRI14; /**< Channel n Priority Register, offset: 0x10D */ + __IO uint8_t DCHPRI13; /**< Channel n Priority Register, offset: 0x10E */ + __IO uint8_t DCHPRI12; /**< Channel n Priority Register, offset: 0x10F */ + __IO uint8_t DCHPRI19; /**< Channel n Priority Register, offset: 0x110 */ + __IO uint8_t DCHPRI18; /**< Channel n Priority Register, offset: 0x111 */ + __IO uint8_t DCHPRI17; /**< Channel n Priority Register, offset: 0x112 */ + __IO uint8_t DCHPRI16; /**< Channel n Priority Register, offset: 0x113 */ + __IO uint8_t DCHPRI23; /**< Channel n Priority Register, offset: 0x114 */ + __IO uint8_t DCHPRI22; /**< Channel n Priority Register, offset: 0x115 */ + __IO uint8_t DCHPRI21; /**< Channel n Priority Register, offset: 0x116 */ + __IO uint8_t DCHPRI20; /**< Channel n Priority Register, offset: 0x117 */ + __IO uint8_t DCHPRI27; /**< Channel n Priority Register, offset: 0x118 */ + __IO uint8_t DCHPRI26; /**< Channel n Priority Register, offset: 0x119 */ + __IO uint8_t DCHPRI25; /**< Channel n Priority Register, offset: 0x11A */ + __IO uint8_t DCHPRI24; /**< Channel n Priority Register, offset: 0x11B */ + __IO uint8_t DCHPRI31; /**< Channel n Priority Register, offset: 0x11C */ + __IO uint8_t DCHPRI30; /**< Channel n Priority Register, offset: 0x11D */ + __IO uint8_t DCHPRI29; /**< Channel n Priority Register, offset: 0x11E */ + __IO uint8_t DCHPRI28; /**< Channel n Priority Register, offset: 0x11F */ + uint8_t RESERVED_7[3808]; + struct { /* offset: 0x1000, array step: 0x20 */ + __IO uint32_t SADDR; /**< TCD Source Address, array offset: 0x1000, array step: 0x20 */ + __IO uint16_t SOFF; /**< TCD Signed Source Address Offset, array offset: 0x1004, array step: 0x20 */ + __IO uint16_t ATTR; /**< TCD Transfer Attributes, array offset: 0x1006, array step: 0x20 */ + union { /* offset: 0x1008, array step: 0x20 */ + __IO uint32_t NBYTES_MLNO; /**< TCD Minor Byte Count (Minor Loop Mapping Disabled), array offset: 0x1008, array step: 0x20 */ + __IO uint32_t NBYTES_MLOFFNO; /**< TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled), array offset: 0x1008, array step: 0x20 */ + __IO uint32_t NBYTES_MLOFFYES; /**< TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled), array offset: 0x1008, array step: 0x20 */ + }; + __IO uint32_t SLAST; /**< TCD Last Source Address Adjustment, array offset: 0x100C, array step: 0x20 */ + __IO uint32_t DADDR; /**< TCD Destination Address, array offset: 0x1010, array step: 0x20 */ + __IO uint16_t DOFF; /**< TCD Signed Destination Address Offset, array offset: 0x1014, array step: 0x20 */ + union { /* offset: 0x1016, array step: 0x20 */ + __IO uint16_t CITER_ELINKNO; /**< TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled), array offset: 0x1016, array step: 0x20 */ + __IO uint16_t CITER_ELINKYES; /**< TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled), array offset: 0x1016, array step: 0x20 */ + }; + __IO uint32_t DLAST_SGA; /**< TCD Last Destination Address Adjustment/Scatter Gather Address, array offset: 0x1018, array step: 0x20 */ + __IO uint16_t CSR; /**< TCD Control and Status, array offset: 0x101C, array step: 0x20 */ + union { /* offset: 0x101E, array step: 0x20 */ + __IO uint16_t BITER_ELINKNO; /**< TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled), array offset: 0x101E, array step: 0x20 */ + __IO uint16_t BITER_ELINKYES; /**< TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled), array offset: 0x101E, array step: 0x20 */ + }; + } TCD[32]; +} DMA_Type; + +/* ---------------------------------------------------------------------------- + -- DMA Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup DMA_Register_Masks DMA Register Masks + * @{ + */ + +/*! @name CR - Control Register */ +/*! @{ */ +#define DMA_CR_EDBG_MASK (0x2U) +#define DMA_CR_EDBG_SHIFT (1U) +/*! EDBG - Enable Debug + * 0b0..When in debug mode, the DMA continues to operate. + * 0b1..When in debug mode, the DMA stalls the start of a new channel. Executing channels are allowed to complete. Channel execution resumes when the system exits debug mode or the EDBG bit is cleared. + */ +#define DMA_CR_EDBG(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_EDBG_SHIFT)) & DMA_CR_EDBG_MASK) +#define DMA_CR_ERCA_MASK (0x4U) +#define DMA_CR_ERCA_SHIFT (2U) +/*! ERCA - Enable Round Robin Channel Arbitration + * 0b0..Fixed priority arbitration is used for channel selection within each group. + * 0b1..Round robin arbitration is used for channel selection within each group. + */ +#define DMA_CR_ERCA(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_ERCA_SHIFT)) & DMA_CR_ERCA_MASK) +#define DMA_CR_ERGA_MASK (0x8U) +#define DMA_CR_ERGA_SHIFT (3U) +/*! ERGA - Enable Round Robin Group Arbitration + * 0b0..Fixed priority arbitration is used for selection among the groups. + * 0b1..Round robin arbitration is used for selection among the groups. + */ +#define DMA_CR_ERGA(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_ERGA_SHIFT)) & DMA_CR_ERGA_MASK) +#define DMA_CR_HOE_MASK (0x10U) +#define DMA_CR_HOE_SHIFT (4U) +/*! HOE - Halt On Error + * 0b0..Normal operation + * 0b1..Any error causes the HALT bit to set. Subsequently, all service requests are ignored until the HALT bit is cleared. + */ +#define DMA_CR_HOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_HOE_SHIFT)) & DMA_CR_HOE_MASK) +#define DMA_CR_HALT_MASK (0x20U) +#define DMA_CR_HALT_SHIFT (5U) +/*! HALT - Halt DMA Operations + * 0b0..Normal operation + * 0b1..Stall the start of any new channels. Executing channels are allowed to complete. Channel execution resumes when this bit is cleared. + */ +#define DMA_CR_HALT(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_HALT_SHIFT)) & DMA_CR_HALT_MASK) +#define DMA_CR_CLM_MASK (0x40U) +#define DMA_CR_CLM_SHIFT (6U) +/*! CLM - Continuous Link Mode + * 0b0..A minor loop channel link made to itself goes through channel arbitration before being activated again. + * 0b1..A minor loop channel link made to itself does not go through channel arbitration before being activated again. Upon minor loop completion, the channel activates again if that channel has a minor loop channel link enabled and the link channel is itself. This effectively applies the minor loop offsets and restarts the next minor loop. + */ +#define DMA_CR_CLM(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_CLM_SHIFT)) & DMA_CR_CLM_MASK) +#define DMA_CR_EMLM_MASK (0x80U) +#define DMA_CR_EMLM_SHIFT (7U) +/*! EMLM - Enable Minor Loop Mapping + * 0b0..Disabled. TCDn.word2 is defined as a 32-bit NBYTES field. + * 0b1..Enabled. TCDn.word2 is redefined to include individual enable fields, an offset field, and the NBYTES field. The individual enable fields allow the minor loop offset to be applied to the source address, the destination address, or both. The NBYTES field is reduced when either offset is enabled. + */ +#define DMA_CR_EMLM(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_EMLM_SHIFT)) & DMA_CR_EMLM_MASK) +#define DMA_CR_GRP0PRI_MASK (0x100U) +#define DMA_CR_GRP0PRI_SHIFT (8U) +#define DMA_CR_GRP0PRI(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_GRP0PRI_SHIFT)) & DMA_CR_GRP0PRI_MASK) +#define DMA_CR_GRP1PRI_MASK (0x400U) +#define DMA_CR_GRP1PRI_SHIFT (10U) +#define DMA_CR_GRP1PRI(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_GRP1PRI_SHIFT)) & DMA_CR_GRP1PRI_MASK) +#define DMA_CR_ECX_MASK (0x10000U) +#define DMA_CR_ECX_SHIFT (16U) +/*! ECX - Error Cancel Transfer + * 0b0..Normal operation + * 0b1..Cancel the remaining data transfer in the same fashion as the CX bit. Stop the executing channel and force the minor loop to finish. The cancel takes effect after the last write of the current read/write sequence. The ECX bit clears itself after the cancel is honored. In addition to cancelling the transfer, ECX treats the cancel as an error condition, thus updating the Error Status register (DMAx_ES) and generating an optional error interrupt. + */ +#define DMA_CR_ECX(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_ECX_SHIFT)) & DMA_CR_ECX_MASK) +#define DMA_CR_CX_MASK (0x20000U) +#define DMA_CR_CX_SHIFT (17U) +/*! CX - Cancel Transfer + * 0b0..Normal operation + * 0b1..Cancel the remaining data transfer. Stop the executing channel and force the minor loop to finish. The cancel takes effect after the last write of the current read/write sequence. The CX bit clears itself after the cancel has been honored. This cancel retires the channel normally as if the minor loop was completed. + */ +#define DMA_CR_CX(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_CX_SHIFT)) & DMA_CR_CX_MASK) +#define DMA_CR_ACTIVE_MASK (0x80000000U) +#define DMA_CR_ACTIVE_SHIFT (31U) +/*! ACTIVE - DMA Active Status + * 0b0..eDMA is idle. + * 0b1..eDMA is executing a channel. + */ +#define DMA_CR_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_ACTIVE_SHIFT)) & DMA_CR_ACTIVE_MASK) +/*! @} */ + +/*! @name ES - Error Status Register */ +/*! @{ */ +#define DMA_ES_DBE_MASK (0x1U) +#define DMA_ES_DBE_SHIFT (0U) +/*! DBE - Destination Bus Error + * 0b0..No destination bus error + * 0b1..The last recorded error was a bus error on a destination write + */ +#define DMA_ES_DBE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_DBE_SHIFT)) & DMA_ES_DBE_MASK) +#define DMA_ES_SBE_MASK (0x2U) +#define DMA_ES_SBE_SHIFT (1U) +/*! SBE - Source Bus Error + * 0b0..No source bus error + * 0b1..The last recorded error was a bus error on a source read + */ +#define DMA_ES_SBE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_SBE_SHIFT)) & DMA_ES_SBE_MASK) +#define DMA_ES_SGE_MASK (0x4U) +#define DMA_ES_SGE_SHIFT (2U) +/*! SGE - Scatter/Gather Configuration Error + * 0b0..No scatter/gather configuration error + * 0b1..The last recorded error was a configuration error detected in the TCDn_DLASTSGA field. This field is checked at the beginning of a scatter/gather operation after major loop completion if TCDn_CSR[ESG] is enabled. TCDn_DLASTSGA is not on a 32 byte boundary. + */ +#define DMA_ES_SGE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_SGE_SHIFT)) & DMA_ES_SGE_MASK) +#define DMA_ES_NCE_MASK (0x8U) +#define DMA_ES_NCE_SHIFT (3U) +/*! NCE - NBYTES/CITER Configuration Error + * 0b0..No NBYTES/CITER configuration error + * 0b1..The last recorded error was a configuration error detected in the TCDn_NBYTES or TCDn_CITER fields. TCDn_NBYTES is not a multiple of TCDn_ATTR[SSIZE] and TCDn_ATTR[DSIZE], or TCDn_CITER[CITER] is equal to zero, or TCDn_CITER[ELINK] is not equal to TCDn_BITER[ELINK] + */ +#define DMA_ES_NCE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_NCE_SHIFT)) & DMA_ES_NCE_MASK) +#define DMA_ES_DOE_MASK (0x10U) +#define DMA_ES_DOE_SHIFT (4U) +/*! DOE - Destination Offset Error + * 0b0..No destination offset configuration error + * 0b1..The last recorded error was a configuration error detected in the TCDn_DOFF field. TCDn_DOFF is inconsistent with TCDn_ATTR[DSIZE]. + */ +#define DMA_ES_DOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_DOE_SHIFT)) & DMA_ES_DOE_MASK) +#define DMA_ES_DAE_MASK (0x20U) +#define DMA_ES_DAE_SHIFT (5U) +/*! DAE - Destination Address Error + * 0b0..No destination address configuration error + * 0b1..The last recorded error was a configuration error detected in the TCDn_DADDR field. TCDn_DADDR is inconsistent with TCDn_ATTR[DSIZE]. + */ +#define DMA_ES_DAE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_DAE_SHIFT)) & DMA_ES_DAE_MASK) +#define DMA_ES_SOE_MASK (0x40U) +#define DMA_ES_SOE_SHIFT (6U) +/*! SOE - Source Offset Error + * 0b0..No source offset configuration error + * 0b1..The last recorded error was a configuration error detected in the TCDn_SOFF field. TCDn_SOFF is inconsistent with TCDn_ATTR[SSIZE]. + */ +#define DMA_ES_SOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_SOE_SHIFT)) & DMA_ES_SOE_MASK) +#define DMA_ES_SAE_MASK (0x80U) +#define DMA_ES_SAE_SHIFT (7U) +/*! SAE - Source Address Error + * 0b0..No source address configuration error. + * 0b1..The last recorded error was a configuration error detected in the TCDn_SADDR field. TCDn_SADDR is inconsistent with TCDn_ATTR[SSIZE]. + */ +#define DMA_ES_SAE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_SAE_SHIFT)) & DMA_ES_SAE_MASK) +#define DMA_ES_ERRCHN_MASK (0x1F00U) +#define DMA_ES_ERRCHN_SHIFT (8U) +#define DMA_ES_ERRCHN(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_ERRCHN_SHIFT)) & DMA_ES_ERRCHN_MASK) +#define DMA_ES_CPE_MASK (0x4000U) +#define DMA_ES_CPE_SHIFT (14U) +/*! CPE - Channel Priority Error + * 0b0..No channel priority error + * 0b1..The last recorded error was a configuration error in the channel priorities within a group. Channel priorities within a group are not unique. + */ +#define DMA_ES_CPE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_CPE_SHIFT)) & DMA_ES_CPE_MASK) +#define DMA_ES_GPE_MASK (0x8000U) +#define DMA_ES_GPE_SHIFT (15U) +/*! GPE - Group Priority Error + * 0b0..No group priority error + * 0b1..The last recorded error was a configuration error among the group priorities. All group priorities are not unique. + */ +#define DMA_ES_GPE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_GPE_SHIFT)) & DMA_ES_GPE_MASK) +#define DMA_ES_ECX_MASK (0x10000U) +#define DMA_ES_ECX_SHIFT (16U) +/*! ECX - Transfer Canceled + * 0b0..No canceled transfers + * 0b1..The last recorded entry was a canceled transfer by the error cancel transfer input + */ +#define DMA_ES_ECX(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_ECX_SHIFT)) & DMA_ES_ECX_MASK) +#define DMA_ES_VLD_MASK (0x80000000U) +#define DMA_ES_VLD_SHIFT (31U) +/*! VLD - VLD + * 0b0..No ERR bits are set. + * 0b1..At least one ERR bit is set indicating a valid error exists that has not been cleared. + */ +#define DMA_ES_VLD(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_VLD_SHIFT)) & DMA_ES_VLD_MASK) +/*! @} */ + +/*! @name ERQ - Enable Request Register */ +/*! @{ */ +#define DMA_ERQ_ERQ0_MASK (0x1U) +#define DMA_ERQ_ERQ0_SHIFT (0U) +/*! ERQ0 - Enable DMA Request 0 + * 0b0..The DMA request signal for the corresponding channel is disabled + * 0b1..The DMA request signal for the corresponding channel is enabled + */ +#define DMA_ERQ_ERQ0(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ0_SHIFT)) & DMA_ERQ_ERQ0_MASK) +#define DMA_ERQ_ERQ1_MASK (0x2U) +#define DMA_ERQ_ERQ1_SHIFT (1U) +/*! ERQ1 - Enable DMA Request 1 + * 0b0..The DMA request signal for the corresponding channel is disabled + * 0b1..The DMA request signal for the corresponding channel is enabled + */ +#define DMA_ERQ_ERQ1(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ1_SHIFT)) & DMA_ERQ_ERQ1_MASK) +#define DMA_ERQ_ERQ2_MASK (0x4U) +#define DMA_ERQ_ERQ2_SHIFT (2U) +/*! ERQ2 - Enable DMA Request 2 + * 0b0..The DMA request signal for the corresponding channel is disabled + * 0b1..The DMA request signal for the corresponding channel is enabled + */ +#define DMA_ERQ_ERQ2(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ2_SHIFT)) & DMA_ERQ_ERQ2_MASK) +#define DMA_ERQ_ERQ3_MASK (0x8U) +#define DMA_ERQ_ERQ3_SHIFT (3U) +/*! ERQ3 - Enable DMA Request 3 + * 0b0..The DMA request signal for the corresponding channel is disabled + * 0b1..The DMA request signal for the corresponding channel is enabled + */ +#define DMA_ERQ_ERQ3(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ3_SHIFT)) & DMA_ERQ_ERQ3_MASK) +#define DMA_ERQ_ERQ4_MASK (0x10U) +#define DMA_ERQ_ERQ4_SHIFT (4U) +/*! ERQ4 - Enable DMA Request 4 + * 0b0..The DMA request signal for the corresponding channel is disabled + * 0b1..The DMA request signal for the corresponding channel is enabled + */ +#define DMA_ERQ_ERQ4(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ4_SHIFT)) & DMA_ERQ_ERQ4_MASK) +#define DMA_ERQ_ERQ5_MASK (0x20U) +#define DMA_ERQ_ERQ5_SHIFT (5U) +/*! ERQ5 - Enable DMA Request 5 + * 0b0..The DMA request signal for the corresponding channel is disabled + * 0b1..The DMA request signal for the corresponding channel is enabled + */ +#define DMA_ERQ_ERQ5(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ5_SHIFT)) & DMA_ERQ_ERQ5_MASK) +#define DMA_ERQ_ERQ6_MASK (0x40U) +#define DMA_ERQ_ERQ6_SHIFT (6U) +/*! ERQ6 - Enable DMA Request 6 + * 0b0..The DMA request signal for the corresponding channel is disabled + * 0b1..The DMA request signal for the corresponding channel is enabled + */ +#define DMA_ERQ_ERQ6(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ6_SHIFT)) & DMA_ERQ_ERQ6_MASK) +#define DMA_ERQ_ERQ7_MASK (0x80U) +#define DMA_ERQ_ERQ7_SHIFT (7U) +/*! ERQ7 - Enable DMA Request 7 + * 0b0..The DMA request signal for the corresponding channel is disabled + * 0b1..The DMA request signal for the corresponding channel is enabled + */ +#define DMA_ERQ_ERQ7(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ7_SHIFT)) & DMA_ERQ_ERQ7_MASK) +#define DMA_ERQ_ERQ8_MASK (0x100U) +#define DMA_ERQ_ERQ8_SHIFT (8U) +/*! ERQ8 - Enable DMA Request 8 + * 0b0..The DMA request signal for the corresponding channel is disabled + * 0b1..The DMA request signal for the corresponding channel is enabled + */ +#define DMA_ERQ_ERQ8(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ8_SHIFT)) & DMA_ERQ_ERQ8_MASK) +#define DMA_ERQ_ERQ9_MASK (0x200U) +#define DMA_ERQ_ERQ9_SHIFT (9U) +/*! ERQ9 - Enable DMA Request 9 + * 0b0..The DMA request signal for the corresponding channel is disabled + * 0b1..The DMA request signal for the corresponding channel is enabled + */ +#define DMA_ERQ_ERQ9(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ9_SHIFT)) & DMA_ERQ_ERQ9_MASK) +#define DMA_ERQ_ERQ10_MASK (0x400U) +#define DMA_ERQ_ERQ10_SHIFT (10U) +/*! ERQ10 - Enable DMA Request 10 + * 0b0..The DMA request signal for the corresponding channel is disabled + * 0b1..The DMA request signal for the corresponding channel is enabled + */ +#define DMA_ERQ_ERQ10(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ10_SHIFT)) & DMA_ERQ_ERQ10_MASK) +#define DMA_ERQ_ERQ11_MASK (0x800U) +#define DMA_ERQ_ERQ11_SHIFT (11U) +/*! ERQ11 - Enable DMA Request 11 + * 0b0..The DMA request signal for the corresponding channel is disabled + * 0b1..The DMA request signal for the corresponding channel is enabled + */ +#define DMA_ERQ_ERQ11(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ11_SHIFT)) & DMA_ERQ_ERQ11_MASK) +#define DMA_ERQ_ERQ12_MASK (0x1000U) +#define DMA_ERQ_ERQ12_SHIFT (12U) +/*! ERQ12 - Enable DMA Request 12 + * 0b0..The DMA request signal for the corresponding channel is disabled + * 0b1..The DMA request signal for the corresponding channel is enabled + */ +#define DMA_ERQ_ERQ12(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ12_SHIFT)) & DMA_ERQ_ERQ12_MASK) +#define DMA_ERQ_ERQ13_MASK (0x2000U) +#define DMA_ERQ_ERQ13_SHIFT (13U) +/*! ERQ13 - Enable DMA Request 13 + * 0b0..The DMA request signal for the corresponding channel is disabled + * 0b1..The DMA request signal for the corresponding channel is enabled + */ +#define DMA_ERQ_ERQ13(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ13_SHIFT)) & DMA_ERQ_ERQ13_MASK) +#define DMA_ERQ_ERQ14_MASK (0x4000U) +#define DMA_ERQ_ERQ14_SHIFT (14U) +/*! ERQ14 - Enable DMA Request 14 + * 0b0..The DMA request signal for the corresponding channel is disabled + * 0b1..The DMA request signal for the corresponding channel is enabled + */ +#define DMA_ERQ_ERQ14(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ14_SHIFT)) & DMA_ERQ_ERQ14_MASK) +#define DMA_ERQ_ERQ15_MASK (0x8000U) +#define DMA_ERQ_ERQ15_SHIFT (15U) +/*! ERQ15 - Enable DMA Request 15 + * 0b0..The DMA request signal for the corresponding channel is disabled + * 0b1..The DMA request signal for the corresponding channel is enabled + */ +#define DMA_ERQ_ERQ15(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ15_SHIFT)) & DMA_ERQ_ERQ15_MASK) +#define DMA_ERQ_ERQ16_MASK (0x10000U) +#define DMA_ERQ_ERQ16_SHIFT (16U) +/*! ERQ16 - Enable DMA Request 16 + * 0b0..The DMA request signal for the corresponding channel is disabled + * 0b1..The DMA request signal for the corresponding channel is enabled + */ +#define DMA_ERQ_ERQ16(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ16_SHIFT)) & DMA_ERQ_ERQ16_MASK) +#define DMA_ERQ_ERQ17_MASK (0x20000U) +#define DMA_ERQ_ERQ17_SHIFT (17U) +/*! ERQ17 - Enable DMA Request 17 + * 0b0..The DMA request signal for the corresponding channel is disabled + * 0b1..The DMA request signal for the corresponding channel is enabled + */ +#define DMA_ERQ_ERQ17(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ17_SHIFT)) & DMA_ERQ_ERQ17_MASK) +#define DMA_ERQ_ERQ18_MASK (0x40000U) +#define DMA_ERQ_ERQ18_SHIFT (18U) +/*! ERQ18 - Enable DMA Request 18 + * 0b0..The DMA request signal for the corresponding channel is disabled + * 0b1..The DMA request signal for the corresponding channel is enabled + */ +#define DMA_ERQ_ERQ18(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ18_SHIFT)) & DMA_ERQ_ERQ18_MASK) +#define DMA_ERQ_ERQ19_MASK (0x80000U) +#define DMA_ERQ_ERQ19_SHIFT (19U) +/*! ERQ19 - Enable DMA Request 19 + * 0b0..The DMA request signal for the corresponding channel is disabled + * 0b1..The DMA request signal for the corresponding channel is enabled + */ +#define DMA_ERQ_ERQ19(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ19_SHIFT)) & DMA_ERQ_ERQ19_MASK) +#define DMA_ERQ_ERQ20_MASK (0x100000U) +#define DMA_ERQ_ERQ20_SHIFT (20U) +/*! ERQ20 - Enable DMA Request 20 + * 0b0..The DMA request signal for the corresponding channel is disabled + * 0b1..The DMA request signal for the corresponding channel is enabled + */ +#define DMA_ERQ_ERQ20(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ20_SHIFT)) & DMA_ERQ_ERQ20_MASK) +#define DMA_ERQ_ERQ21_MASK (0x200000U) +#define DMA_ERQ_ERQ21_SHIFT (21U) +/*! ERQ21 - Enable DMA Request 21 + * 0b0..The DMA request signal for the corresponding channel is disabled + * 0b1..The DMA request signal for the corresponding channel is enabled + */ +#define DMA_ERQ_ERQ21(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ21_SHIFT)) & DMA_ERQ_ERQ21_MASK) +#define DMA_ERQ_ERQ22_MASK (0x400000U) +#define DMA_ERQ_ERQ22_SHIFT (22U) +/*! ERQ22 - Enable DMA Request 22 + * 0b0..The DMA request signal for the corresponding channel is disabled + * 0b1..The DMA request signal for the corresponding channel is enabled + */ +#define DMA_ERQ_ERQ22(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ22_SHIFT)) & DMA_ERQ_ERQ22_MASK) +#define DMA_ERQ_ERQ23_MASK (0x800000U) +#define DMA_ERQ_ERQ23_SHIFT (23U) +/*! ERQ23 - Enable DMA Request 23 + * 0b0..The DMA request signal for the corresponding channel is disabled + * 0b1..The DMA request signal for the corresponding channel is enabled + */ +#define DMA_ERQ_ERQ23(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ23_SHIFT)) & DMA_ERQ_ERQ23_MASK) +#define DMA_ERQ_ERQ24_MASK (0x1000000U) +#define DMA_ERQ_ERQ24_SHIFT (24U) +/*! ERQ24 - Enable DMA Request 24 + * 0b0..The DMA request signal for the corresponding channel is disabled + * 0b1..The DMA request signal for the corresponding channel is enabled + */ +#define DMA_ERQ_ERQ24(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ24_SHIFT)) & DMA_ERQ_ERQ24_MASK) +#define DMA_ERQ_ERQ25_MASK (0x2000000U) +#define DMA_ERQ_ERQ25_SHIFT (25U) +/*! ERQ25 - Enable DMA Request 25 + * 0b0..The DMA request signal for the corresponding channel is disabled + * 0b1..The DMA request signal for the corresponding channel is enabled + */ +#define DMA_ERQ_ERQ25(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ25_SHIFT)) & DMA_ERQ_ERQ25_MASK) +#define DMA_ERQ_ERQ26_MASK (0x4000000U) +#define DMA_ERQ_ERQ26_SHIFT (26U) +/*! ERQ26 - Enable DMA Request 26 + * 0b0..The DMA request signal for the corresponding channel is disabled + * 0b1..The DMA request signal for the corresponding channel is enabled + */ +#define DMA_ERQ_ERQ26(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ26_SHIFT)) & DMA_ERQ_ERQ26_MASK) +#define DMA_ERQ_ERQ27_MASK (0x8000000U) +#define DMA_ERQ_ERQ27_SHIFT (27U) +/*! ERQ27 - Enable DMA Request 27 + * 0b0..The DMA request signal for the corresponding channel is disabled + * 0b1..The DMA request signal for the corresponding channel is enabled + */ +#define DMA_ERQ_ERQ27(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ27_SHIFT)) & DMA_ERQ_ERQ27_MASK) +#define DMA_ERQ_ERQ28_MASK (0x10000000U) +#define DMA_ERQ_ERQ28_SHIFT (28U) +/*! ERQ28 - Enable DMA Request 28 + * 0b0..The DMA request signal for the corresponding channel is disabled + * 0b1..The DMA request signal for the corresponding channel is enabled + */ +#define DMA_ERQ_ERQ28(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ28_SHIFT)) & DMA_ERQ_ERQ28_MASK) +#define DMA_ERQ_ERQ29_MASK (0x20000000U) +#define DMA_ERQ_ERQ29_SHIFT (29U) +/*! ERQ29 - Enable DMA Request 29 + * 0b0..The DMA request signal for the corresponding channel is disabled + * 0b1..The DMA request signal for the corresponding channel is enabled + */ +#define DMA_ERQ_ERQ29(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ29_SHIFT)) & DMA_ERQ_ERQ29_MASK) +#define DMA_ERQ_ERQ30_MASK (0x40000000U) +#define DMA_ERQ_ERQ30_SHIFT (30U) +/*! ERQ30 - Enable DMA Request 30 + * 0b0..The DMA request signal for the corresponding channel is disabled + * 0b1..The DMA request signal for the corresponding channel is enabled + */ +#define DMA_ERQ_ERQ30(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ30_SHIFT)) & DMA_ERQ_ERQ30_MASK) +#define DMA_ERQ_ERQ31_MASK (0x80000000U) +#define DMA_ERQ_ERQ31_SHIFT (31U) +/*! ERQ31 - Enable DMA Request 31 + * 0b0..The DMA request signal for the corresponding channel is disabled + * 0b1..The DMA request signal for the corresponding channel is enabled + */ +#define DMA_ERQ_ERQ31(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ31_SHIFT)) & DMA_ERQ_ERQ31_MASK) +/*! @} */ + +/*! @name EEI - Enable Error Interrupt Register */ +/*! @{ */ +#define DMA_EEI_EEI0_MASK (0x1U) +#define DMA_EEI_EEI0_SHIFT (0U) +/*! EEI0 - Enable Error Interrupt 0 + * 0b0..The error signal for corresponding channel does not generate an error interrupt + * 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request + */ +#define DMA_EEI_EEI0(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI0_SHIFT)) & DMA_EEI_EEI0_MASK) +#define DMA_EEI_EEI1_MASK (0x2U) +#define DMA_EEI_EEI1_SHIFT (1U) +/*! EEI1 - Enable Error Interrupt 1 + * 0b0..The error signal for corresponding channel does not generate an error interrupt + * 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request + */ +#define DMA_EEI_EEI1(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI1_SHIFT)) & DMA_EEI_EEI1_MASK) +#define DMA_EEI_EEI2_MASK (0x4U) +#define DMA_EEI_EEI2_SHIFT (2U) +/*! EEI2 - Enable Error Interrupt 2 + * 0b0..The error signal for corresponding channel does not generate an error interrupt + * 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request + */ +#define DMA_EEI_EEI2(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI2_SHIFT)) & DMA_EEI_EEI2_MASK) +#define DMA_EEI_EEI3_MASK (0x8U) +#define DMA_EEI_EEI3_SHIFT (3U) +/*! EEI3 - Enable Error Interrupt 3 + * 0b0..The error signal for corresponding channel does not generate an error interrupt + * 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request + */ +#define DMA_EEI_EEI3(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI3_SHIFT)) & DMA_EEI_EEI3_MASK) +#define DMA_EEI_EEI4_MASK (0x10U) +#define DMA_EEI_EEI4_SHIFT (4U) +/*! EEI4 - Enable Error Interrupt 4 + * 0b0..The error signal for corresponding channel does not generate an error interrupt + * 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request + */ +#define DMA_EEI_EEI4(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI4_SHIFT)) & DMA_EEI_EEI4_MASK) +#define DMA_EEI_EEI5_MASK (0x20U) +#define DMA_EEI_EEI5_SHIFT (5U) +/*! EEI5 - Enable Error Interrupt 5 + * 0b0..The error signal for corresponding channel does not generate an error interrupt + * 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request + */ +#define DMA_EEI_EEI5(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI5_SHIFT)) & DMA_EEI_EEI5_MASK) +#define DMA_EEI_EEI6_MASK (0x40U) +#define DMA_EEI_EEI6_SHIFT (6U) +/*! EEI6 - Enable Error Interrupt 6 + * 0b0..The error signal for corresponding channel does not generate an error interrupt + * 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request + */ +#define DMA_EEI_EEI6(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI6_SHIFT)) & DMA_EEI_EEI6_MASK) +#define DMA_EEI_EEI7_MASK (0x80U) +#define DMA_EEI_EEI7_SHIFT (7U) +/*! EEI7 - Enable Error Interrupt 7 + * 0b0..The error signal for corresponding channel does not generate an error interrupt + * 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request + */ +#define DMA_EEI_EEI7(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI7_SHIFT)) & DMA_EEI_EEI7_MASK) +#define DMA_EEI_EEI8_MASK (0x100U) +#define DMA_EEI_EEI8_SHIFT (8U) +/*! EEI8 - Enable Error Interrupt 8 + * 0b0..The error signal for corresponding channel does not generate an error interrupt + * 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request + */ +#define DMA_EEI_EEI8(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI8_SHIFT)) & DMA_EEI_EEI8_MASK) +#define DMA_EEI_EEI9_MASK (0x200U) +#define DMA_EEI_EEI9_SHIFT (9U) +/*! EEI9 - Enable Error Interrupt 9 + * 0b0..The error signal for corresponding channel does not generate an error interrupt + * 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request + */ +#define DMA_EEI_EEI9(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI9_SHIFT)) & DMA_EEI_EEI9_MASK) +#define DMA_EEI_EEI10_MASK (0x400U) +#define DMA_EEI_EEI10_SHIFT (10U) +/*! EEI10 - Enable Error Interrupt 10 + * 0b0..The error signal for corresponding channel does not generate an error interrupt + * 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request + */ +#define DMA_EEI_EEI10(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI10_SHIFT)) & DMA_EEI_EEI10_MASK) +#define DMA_EEI_EEI11_MASK (0x800U) +#define DMA_EEI_EEI11_SHIFT (11U) +/*! EEI11 - Enable Error Interrupt 11 + * 0b0..The error signal for corresponding channel does not generate an error interrupt + * 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request + */ +#define DMA_EEI_EEI11(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI11_SHIFT)) & DMA_EEI_EEI11_MASK) +#define DMA_EEI_EEI12_MASK (0x1000U) +#define DMA_EEI_EEI12_SHIFT (12U) +/*! EEI12 - Enable Error Interrupt 12 + * 0b0..The error signal for corresponding channel does not generate an error interrupt + * 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request + */ +#define DMA_EEI_EEI12(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI12_SHIFT)) & DMA_EEI_EEI12_MASK) +#define DMA_EEI_EEI13_MASK (0x2000U) +#define DMA_EEI_EEI13_SHIFT (13U) +/*! EEI13 - Enable Error Interrupt 13 + * 0b0..The error signal for corresponding channel does not generate an error interrupt + * 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request + */ +#define DMA_EEI_EEI13(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI13_SHIFT)) & DMA_EEI_EEI13_MASK) +#define DMA_EEI_EEI14_MASK (0x4000U) +#define DMA_EEI_EEI14_SHIFT (14U) +/*! EEI14 - Enable Error Interrupt 14 + * 0b0..The error signal for corresponding channel does not generate an error interrupt + * 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request + */ +#define DMA_EEI_EEI14(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI14_SHIFT)) & DMA_EEI_EEI14_MASK) +#define DMA_EEI_EEI15_MASK (0x8000U) +#define DMA_EEI_EEI15_SHIFT (15U) +/*! EEI15 - Enable Error Interrupt 15 + * 0b0..The error signal for corresponding channel does not generate an error interrupt + * 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request + */ +#define DMA_EEI_EEI15(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI15_SHIFT)) & DMA_EEI_EEI15_MASK) +#define DMA_EEI_EEI16_MASK (0x10000U) +#define DMA_EEI_EEI16_SHIFT (16U) +/*! EEI16 - Enable Error Interrupt 16 + * 0b0..The error signal for corresponding channel does not generate an error interrupt + * 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request + */ +#define DMA_EEI_EEI16(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI16_SHIFT)) & DMA_EEI_EEI16_MASK) +#define DMA_EEI_EEI17_MASK (0x20000U) +#define DMA_EEI_EEI17_SHIFT (17U) +/*! EEI17 - Enable Error Interrupt 17 + * 0b0..The error signal for corresponding channel does not generate an error interrupt + * 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request + */ +#define DMA_EEI_EEI17(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI17_SHIFT)) & DMA_EEI_EEI17_MASK) +#define DMA_EEI_EEI18_MASK (0x40000U) +#define DMA_EEI_EEI18_SHIFT (18U) +/*! EEI18 - Enable Error Interrupt 18 + * 0b0..The error signal for corresponding channel does not generate an error interrupt + * 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request + */ +#define DMA_EEI_EEI18(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI18_SHIFT)) & DMA_EEI_EEI18_MASK) +#define DMA_EEI_EEI19_MASK (0x80000U) +#define DMA_EEI_EEI19_SHIFT (19U) +/*! EEI19 - Enable Error Interrupt 19 + * 0b0..The error signal for corresponding channel does not generate an error interrupt + * 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request + */ +#define DMA_EEI_EEI19(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI19_SHIFT)) & DMA_EEI_EEI19_MASK) +#define DMA_EEI_EEI20_MASK (0x100000U) +#define DMA_EEI_EEI20_SHIFT (20U) +/*! EEI20 - Enable Error Interrupt 20 + * 0b0..The error signal for corresponding channel does not generate an error interrupt + * 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request + */ +#define DMA_EEI_EEI20(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI20_SHIFT)) & DMA_EEI_EEI20_MASK) +#define DMA_EEI_EEI21_MASK (0x200000U) +#define DMA_EEI_EEI21_SHIFT (21U) +/*! EEI21 - Enable Error Interrupt 21 + * 0b0..The error signal for corresponding channel does not generate an error interrupt + * 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request + */ +#define DMA_EEI_EEI21(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI21_SHIFT)) & DMA_EEI_EEI21_MASK) +#define DMA_EEI_EEI22_MASK (0x400000U) +#define DMA_EEI_EEI22_SHIFT (22U) +/*! EEI22 - Enable Error Interrupt 22 + * 0b0..The error signal for corresponding channel does not generate an error interrupt + * 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request + */ +#define DMA_EEI_EEI22(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI22_SHIFT)) & DMA_EEI_EEI22_MASK) +#define DMA_EEI_EEI23_MASK (0x800000U) +#define DMA_EEI_EEI23_SHIFT (23U) +/*! EEI23 - Enable Error Interrupt 23 + * 0b0..The error signal for corresponding channel does not generate an error interrupt + * 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request + */ +#define DMA_EEI_EEI23(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI23_SHIFT)) & DMA_EEI_EEI23_MASK) +#define DMA_EEI_EEI24_MASK (0x1000000U) +#define DMA_EEI_EEI24_SHIFT (24U) +/*! EEI24 - Enable Error Interrupt 24 + * 0b0..The error signal for corresponding channel does not generate an error interrupt + * 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request + */ +#define DMA_EEI_EEI24(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI24_SHIFT)) & DMA_EEI_EEI24_MASK) +#define DMA_EEI_EEI25_MASK (0x2000000U) +#define DMA_EEI_EEI25_SHIFT (25U) +/*! EEI25 - Enable Error Interrupt 25 + * 0b0..The error signal for corresponding channel does not generate an error interrupt + * 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request + */ +#define DMA_EEI_EEI25(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI25_SHIFT)) & DMA_EEI_EEI25_MASK) +#define DMA_EEI_EEI26_MASK (0x4000000U) +#define DMA_EEI_EEI26_SHIFT (26U) +/*! EEI26 - Enable Error Interrupt 26 + * 0b0..The error signal for corresponding channel does not generate an error interrupt + * 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request + */ +#define DMA_EEI_EEI26(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI26_SHIFT)) & DMA_EEI_EEI26_MASK) +#define DMA_EEI_EEI27_MASK (0x8000000U) +#define DMA_EEI_EEI27_SHIFT (27U) +/*! EEI27 - Enable Error Interrupt 27 + * 0b0..The error signal for corresponding channel does not generate an error interrupt + * 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request + */ +#define DMA_EEI_EEI27(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI27_SHIFT)) & DMA_EEI_EEI27_MASK) +#define DMA_EEI_EEI28_MASK (0x10000000U) +#define DMA_EEI_EEI28_SHIFT (28U) +/*! EEI28 - Enable Error Interrupt 28 + * 0b0..The error signal for corresponding channel does not generate an error interrupt + * 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request + */ +#define DMA_EEI_EEI28(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI28_SHIFT)) & DMA_EEI_EEI28_MASK) +#define DMA_EEI_EEI29_MASK (0x20000000U) +#define DMA_EEI_EEI29_SHIFT (29U) +/*! EEI29 - Enable Error Interrupt 29 + * 0b0..The error signal for corresponding channel does not generate an error interrupt + * 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request + */ +#define DMA_EEI_EEI29(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI29_SHIFT)) & DMA_EEI_EEI29_MASK) +#define DMA_EEI_EEI30_MASK (0x40000000U) +#define DMA_EEI_EEI30_SHIFT (30U) +/*! EEI30 - Enable Error Interrupt 30 + * 0b0..The error signal for corresponding channel does not generate an error interrupt + * 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request + */ +#define DMA_EEI_EEI30(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI30_SHIFT)) & DMA_EEI_EEI30_MASK) +#define DMA_EEI_EEI31_MASK (0x80000000U) +#define DMA_EEI_EEI31_SHIFT (31U) +/*! EEI31 - Enable Error Interrupt 31 + * 0b0..The error signal for corresponding channel does not generate an error interrupt + * 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request + */ +#define DMA_EEI_EEI31(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI31_SHIFT)) & DMA_EEI_EEI31_MASK) +/*! @} */ + +/*! @name CEEI - Clear Enable Error Interrupt Register */ +/*! @{ */ +#define DMA_CEEI_CEEI_MASK (0x1FU) +#define DMA_CEEI_CEEI_SHIFT (0U) +#define DMA_CEEI_CEEI(x) (((uint8_t)(((uint8_t)(x)) << DMA_CEEI_CEEI_SHIFT)) & DMA_CEEI_CEEI_MASK) +#define DMA_CEEI_CAEE_MASK (0x40U) +#define DMA_CEEI_CAEE_SHIFT (6U) +/*! CAEE - Clear All Enable Error Interrupts + * 0b0..Clear only the EEI bit specified in the CEEI field + * 0b1..Clear all bits in EEI + */ +#define DMA_CEEI_CAEE(x) (((uint8_t)(((uint8_t)(x)) << DMA_CEEI_CAEE_SHIFT)) & DMA_CEEI_CAEE_MASK) +#define DMA_CEEI_NOP_MASK (0x80U) +#define DMA_CEEI_NOP_SHIFT (7U) +/*! NOP - No Op enable + * 0b0..Normal operation + * 0b1..No operation, ignore the other bits in this register + */ +#define DMA_CEEI_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_CEEI_NOP_SHIFT)) & DMA_CEEI_NOP_MASK) +/*! @} */ + +/*! @name SEEI - Set Enable Error Interrupt Register */ +/*! @{ */ +#define DMA_SEEI_SEEI_MASK (0x1FU) +#define DMA_SEEI_SEEI_SHIFT (0U) +#define DMA_SEEI_SEEI(x) (((uint8_t)(((uint8_t)(x)) << DMA_SEEI_SEEI_SHIFT)) & DMA_SEEI_SEEI_MASK) +#define DMA_SEEI_SAEE_MASK (0x40U) +#define DMA_SEEI_SAEE_SHIFT (6U) +/*! SAEE - Sets All Enable Error Interrupts + * 0b0..Set only the EEI bit specified in the SEEI field. + * 0b1..Sets all bits in EEI + */ +#define DMA_SEEI_SAEE(x) (((uint8_t)(((uint8_t)(x)) << DMA_SEEI_SAEE_SHIFT)) & DMA_SEEI_SAEE_MASK) +#define DMA_SEEI_NOP_MASK (0x80U) +#define DMA_SEEI_NOP_SHIFT (7U) +/*! NOP - No Op enable + * 0b0..Normal operation + * 0b1..No operation, ignore the other bits in this register + */ +#define DMA_SEEI_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_SEEI_NOP_SHIFT)) & DMA_SEEI_NOP_MASK) +/*! @} */ + +/*! @name CERQ - Clear Enable Request Register */ +/*! @{ */ +#define DMA_CERQ_CERQ_MASK (0x1FU) +#define DMA_CERQ_CERQ_SHIFT (0U) +#define DMA_CERQ_CERQ(x) (((uint8_t)(((uint8_t)(x)) << DMA_CERQ_CERQ_SHIFT)) & DMA_CERQ_CERQ_MASK) +#define DMA_CERQ_CAER_MASK (0x40U) +#define DMA_CERQ_CAER_SHIFT (6U) +/*! CAER - Clear All Enable Requests + * 0b0..Clear only the ERQ bit specified in the CERQ field + * 0b1..Clear all bits in ERQ + */ +#define DMA_CERQ_CAER(x) (((uint8_t)(((uint8_t)(x)) << DMA_CERQ_CAER_SHIFT)) & DMA_CERQ_CAER_MASK) +#define DMA_CERQ_NOP_MASK (0x80U) +#define DMA_CERQ_NOP_SHIFT (7U) +/*! NOP - No Op enable + * 0b0..Normal operation + * 0b1..No operation, ignore the other bits in this register + */ +#define DMA_CERQ_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_CERQ_NOP_SHIFT)) & DMA_CERQ_NOP_MASK) +/*! @} */ + +/*! @name SERQ - Set Enable Request Register */ +/*! @{ */ +#define DMA_SERQ_SERQ_MASK (0x1FU) +#define DMA_SERQ_SERQ_SHIFT (0U) +#define DMA_SERQ_SERQ(x) (((uint8_t)(((uint8_t)(x)) << DMA_SERQ_SERQ_SHIFT)) & DMA_SERQ_SERQ_MASK) +#define DMA_SERQ_SAER_MASK (0x40U) +#define DMA_SERQ_SAER_SHIFT (6U) +/*! SAER - Set All Enable Requests + * 0b0..Set only the ERQ bit specified in the SERQ field + * 0b1..Set all bits in ERQ + */ +#define DMA_SERQ_SAER(x) (((uint8_t)(((uint8_t)(x)) << DMA_SERQ_SAER_SHIFT)) & DMA_SERQ_SAER_MASK) +#define DMA_SERQ_NOP_MASK (0x80U) +#define DMA_SERQ_NOP_SHIFT (7U) +/*! NOP - No Op enable + * 0b0..Normal operation + * 0b1..No operation, ignore the other bits in this register + */ +#define DMA_SERQ_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_SERQ_NOP_SHIFT)) & DMA_SERQ_NOP_MASK) +/*! @} */ + +/*! @name CDNE - Clear DONE Status Bit Register */ +/*! @{ */ +#define DMA_CDNE_CDNE_MASK (0x1FU) +#define DMA_CDNE_CDNE_SHIFT (0U) +#define DMA_CDNE_CDNE(x) (((uint8_t)(((uint8_t)(x)) << DMA_CDNE_CDNE_SHIFT)) & DMA_CDNE_CDNE_MASK) +#define DMA_CDNE_CADN_MASK (0x40U) +#define DMA_CDNE_CADN_SHIFT (6U) +/*! CADN - Clears All DONE Bits + * 0b0..Clears only the TCDn_CSR[DONE] bit specified in the CDNE field + * 0b1..Clears all bits in TCDn_CSR[DONE] + */ +#define DMA_CDNE_CADN(x) (((uint8_t)(((uint8_t)(x)) << DMA_CDNE_CADN_SHIFT)) & DMA_CDNE_CADN_MASK) +#define DMA_CDNE_NOP_MASK (0x80U) +#define DMA_CDNE_NOP_SHIFT (7U) +/*! NOP - No Op enable + * 0b0..Normal operation + * 0b1..No operation, ignore the other bits in this register + */ +#define DMA_CDNE_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_CDNE_NOP_SHIFT)) & DMA_CDNE_NOP_MASK) +/*! @} */ + +/*! @name SSRT - Set START Bit Register */ +/*! @{ */ +#define DMA_SSRT_SSRT_MASK (0x1FU) +#define DMA_SSRT_SSRT_SHIFT (0U) +#define DMA_SSRT_SSRT(x) (((uint8_t)(((uint8_t)(x)) << DMA_SSRT_SSRT_SHIFT)) & DMA_SSRT_SSRT_MASK) +#define DMA_SSRT_SAST_MASK (0x40U) +#define DMA_SSRT_SAST_SHIFT (6U) +/*! SAST - Set All START Bits (activates all channels) + * 0b0..Set only the TCDn_CSR[START] bit specified in the SSRT field + * 0b1..Set all bits in TCDn_CSR[START] + */ +#define DMA_SSRT_SAST(x) (((uint8_t)(((uint8_t)(x)) << DMA_SSRT_SAST_SHIFT)) & DMA_SSRT_SAST_MASK) +#define DMA_SSRT_NOP_MASK (0x80U) +#define DMA_SSRT_NOP_SHIFT (7U) +/*! NOP - No Op enable + * 0b0..Normal operation + * 0b1..No operation, ignore the other bits in this register + */ +#define DMA_SSRT_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_SSRT_NOP_SHIFT)) & DMA_SSRT_NOP_MASK) +/*! @} */ + +/*! @name CERR - Clear Error Register */ +/*! @{ */ +#define DMA_CERR_CERR_MASK (0x1FU) +#define DMA_CERR_CERR_SHIFT (0U) +#define DMA_CERR_CERR(x) (((uint8_t)(((uint8_t)(x)) << DMA_CERR_CERR_SHIFT)) & DMA_CERR_CERR_MASK) +#define DMA_CERR_CAEI_MASK (0x40U) +#define DMA_CERR_CAEI_SHIFT (6U) +/*! CAEI - Clear All Error Indicators + * 0b0..Clear only the ERR bit specified in the CERR field + * 0b1..Clear all bits in ERR + */ +#define DMA_CERR_CAEI(x) (((uint8_t)(((uint8_t)(x)) << DMA_CERR_CAEI_SHIFT)) & DMA_CERR_CAEI_MASK) +#define DMA_CERR_NOP_MASK (0x80U) +#define DMA_CERR_NOP_SHIFT (7U) +/*! NOP - No Op enable + * 0b0..Normal operation + * 0b1..No operation, ignore the other bits in this register + */ +#define DMA_CERR_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_CERR_NOP_SHIFT)) & DMA_CERR_NOP_MASK) +/*! @} */ + +/*! @name CINT - Clear Interrupt Request Register */ +/*! @{ */ +#define DMA_CINT_CINT_MASK (0x1FU) +#define DMA_CINT_CINT_SHIFT (0U) +#define DMA_CINT_CINT(x) (((uint8_t)(((uint8_t)(x)) << DMA_CINT_CINT_SHIFT)) & DMA_CINT_CINT_MASK) +#define DMA_CINT_CAIR_MASK (0x40U) +#define DMA_CINT_CAIR_SHIFT (6U) +/*! CAIR - Clear All Interrupt Requests + * 0b0..Clear only the INT bit specified in the CINT field + * 0b1..Clear all bits in INT + */ +#define DMA_CINT_CAIR(x) (((uint8_t)(((uint8_t)(x)) << DMA_CINT_CAIR_SHIFT)) & DMA_CINT_CAIR_MASK) +#define DMA_CINT_NOP_MASK (0x80U) +#define DMA_CINT_NOP_SHIFT (7U) +/*! NOP - No Op enable + * 0b0..Normal operation + * 0b1..No operation, ignore the other bits in this register + */ +#define DMA_CINT_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_CINT_NOP_SHIFT)) & DMA_CINT_NOP_MASK) +/*! @} */ + +/*! @name INT - Interrupt Request Register */ +/*! @{ */ +#define DMA_INT_INT0_MASK (0x1U) +#define DMA_INT_INT0_SHIFT (0U) +/*! INT0 - Interrupt Request 0 + * 0b0..The interrupt request for corresponding channel is cleared + * 0b1..The interrupt request for corresponding channel is active + */ +#define DMA_INT_INT0(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT0_SHIFT)) & DMA_INT_INT0_MASK) +#define DMA_INT_INT1_MASK (0x2U) +#define DMA_INT_INT1_SHIFT (1U) +/*! INT1 - Interrupt Request 1 + * 0b0..The interrupt request for corresponding channel is cleared + * 0b1..The interrupt request for corresponding channel is active + */ +#define DMA_INT_INT1(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT1_SHIFT)) & DMA_INT_INT1_MASK) +#define DMA_INT_INT2_MASK (0x4U) +#define DMA_INT_INT2_SHIFT (2U) +/*! INT2 - Interrupt Request 2 + * 0b0..The interrupt request for corresponding channel is cleared + * 0b1..The interrupt request for corresponding channel is active + */ +#define DMA_INT_INT2(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT2_SHIFT)) & DMA_INT_INT2_MASK) +#define DMA_INT_INT3_MASK (0x8U) +#define DMA_INT_INT3_SHIFT (3U) +/*! INT3 - Interrupt Request 3 + * 0b0..The interrupt request for corresponding channel is cleared + * 0b1..The interrupt request for corresponding channel is active + */ +#define DMA_INT_INT3(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT3_SHIFT)) & DMA_INT_INT3_MASK) +#define DMA_INT_INT4_MASK (0x10U) +#define DMA_INT_INT4_SHIFT (4U) +/*! INT4 - Interrupt Request 4 + * 0b0..The interrupt request for corresponding channel is cleared + * 0b1..The interrupt request for corresponding channel is active + */ +#define DMA_INT_INT4(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT4_SHIFT)) & DMA_INT_INT4_MASK) +#define DMA_INT_INT5_MASK (0x20U) +#define DMA_INT_INT5_SHIFT (5U) +/*! INT5 - Interrupt Request 5 + * 0b0..The interrupt request for corresponding channel is cleared + * 0b1..The interrupt request for corresponding channel is active + */ +#define DMA_INT_INT5(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT5_SHIFT)) & DMA_INT_INT5_MASK) +#define DMA_INT_INT6_MASK (0x40U) +#define DMA_INT_INT6_SHIFT (6U) +/*! INT6 - Interrupt Request 6 + * 0b0..The interrupt request for corresponding channel is cleared + * 0b1..The interrupt request for corresponding channel is active + */ +#define DMA_INT_INT6(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT6_SHIFT)) & DMA_INT_INT6_MASK) +#define DMA_INT_INT7_MASK (0x80U) +#define DMA_INT_INT7_SHIFT (7U) +/*! INT7 - Interrupt Request 7 + * 0b0..The interrupt request for corresponding channel is cleared + * 0b1..The interrupt request for corresponding channel is active + */ +#define DMA_INT_INT7(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT7_SHIFT)) & DMA_INT_INT7_MASK) +#define DMA_INT_INT8_MASK (0x100U) +#define DMA_INT_INT8_SHIFT (8U) +/*! INT8 - Interrupt Request 8 + * 0b0..The interrupt request for corresponding channel is cleared + * 0b1..The interrupt request for corresponding channel is active + */ +#define DMA_INT_INT8(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT8_SHIFT)) & DMA_INT_INT8_MASK) +#define DMA_INT_INT9_MASK (0x200U) +#define DMA_INT_INT9_SHIFT (9U) +/*! INT9 - Interrupt Request 9 + * 0b0..The interrupt request for corresponding channel is cleared + * 0b1..The interrupt request for corresponding channel is active + */ +#define DMA_INT_INT9(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT9_SHIFT)) & DMA_INT_INT9_MASK) +#define DMA_INT_INT10_MASK (0x400U) +#define DMA_INT_INT10_SHIFT (10U) +/*! INT10 - Interrupt Request 10 + * 0b0..The interrupt request for corresponding channel is cleared + * 0b1..The interrupt request for corresponding channel is active + */ +#define DMA_INT_INT10(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT10_SHIFT)) & DMA_INT_INT10_MASK) +#define DMA_INT_INT11_MASK (0x800U) +#define DMA_INT_INT11_SHIFT (11U) +/*! INT11 - Interrupt Request 11 + * 0b0..The interrupt request for corresponding channel is cleared + * 0b1..The interrupt request for corresponding channel is active + */ +#define DMA_INT_INT11(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT11_SHIFT)) & DMA_INT_INT11_MASK) +#define DMA_INT_INT12_MASK (0x1000U) +#define DMA_INT_INT12_SHIFT (12U) +/*! INT12 - Interrupt Request 12 + * 0b0..The interrupt request for corresponding channel is cleared + * 0b1..The interrupt request for corresponding channel is active + */ +#define DMA_INT_INT12(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT12_SHIFT)) & DMA_INT_INT12_MASK) +#define DMA_INT_INT13_MASK (0x2000U) +#define DMA_INT_INT13_SHIFT (13U) +/*! INT13 - Interrupt Request 13 + * 0b0..The interrupt request for corresponding channel is cleared + * 0b1..The interrupt request for corresponding channel is active + */ +#define DMA_INT_INT13(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT13_SHIFT)) & DMA_INT_INT13_MASK) +#define DMA_INT_INT14_MASK (0x4000U) +#define DMA_INT_INT14_SHIFT (14U) +/*! INT14 - Interrupt Request 14 + * 0b0..The interrupt request for corresponding channel is cleared + * 0b1..The interrupt request for corresponding channel is active + */ +#define DMA_INT_INT14(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT14_SHIFT)) & DMA_INT_INT14_MASK) +#define DMA_INT_INT15_MASK (0x8000U) +#define DMA_INT_INT15_SHIFT (15U) +/*! INT15 - Interrupt Request 15 + * 0b0..The interrupt request for corresponding channel is cleared + * 0b1..The interrupt request for corresponding channel is active + */ +#define DMA_INT_INT15(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT15_SHIFT)) & DMA_INT_INT15_MASK) +#define DMA_INT_INT16_MASK (0x10000U) +#define DMA_INT_INT16_SHIFT (16U) +/*! INT16 - Interrupt Request 16 + * 0b0..The interrupt request for corresponding channel is cleared + * 0b1..The interrupt request for corresponding channel is active + */ +#define DMA_INT_INT16(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT16_SHIFT)) & DMA_INT_INT16_MASK) +#define DMA_INT_INT17_MASK (0x20000U) +#define DMA_INT_INT17_SHIFT (17U) +/*! INT17 - Interrupt Request 17 + * 0b0..The interrupt request for corresponding channel is cleared + * 0b1..The interrupt request for corresponding channel is active + */ +#define DMA_INT_INT17(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT17_SHIFT)) & DMA_INT_INT17_MASK) +#define DMA_INT_INT18_MASK (0x40000U) +#define DMA_INT_INT18_SHIFT (18U) +/*! INT18 - Interrupt Request 18 + * 0b0..The interrupt request for corresponding channel is cleared + * 0b1..The interrupt request for corresponding channel is active + */ +#define DMA_INT_INT18(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT18_SHIFT)) & DMA_INT_INT18_MASK) +#define DMA_INT_INT19_MASK (0x80000U) +#define DMA_INT_INT19_SHIFT (19U) +/*! INT19 - Interrupt Request 19 + * 0b0..The interrupt request for corresponding channel is cleared + * 0b1..The interrupt request for corresponding channel is active + */ +#define DMA_INT_INT19(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT19_SHIFT)) & DMA_INT_INT19_MASK) +#define DMA_INT_INT20_MASK (0x100000U) +#define DMA_INT_INT20_SHIFT (20U) +/*! INT20 - Interrupt Request 20 + * 0b0..The interrupt request for corresponding channel is cleared + * 0b1..The interrupt request for corresponding channel is active + */ +#define DMA_INT_INT20(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT20_SHIFT)) & DMA_INT_INT20_MASK) +#define DMA_INT_INT21_MASK (0x200000U) +#define DMA_INT_INT21_SHIFT (21U) +/*! INT21 - Interrupt Request 21 + * 0b0..The interrupt request for corresponding channel is cleared + * 0b1..The interrupt request for corresponding channel is active + */ +#define DMA_INT_INT21(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT21_SHIFT)) & DMA_INT_INT21_MASK) +#define DMA_INT_INT22_MASK (0x400000U) +#define DMA_INT_INT22_SHIFT (22U) +/*! INT22 - Interrupt Request 22 + * 0b0..The interrupt request for corresponding channel is cleared + * 0b1..The interrupt request for corresponding channel is active + */ +#define DMA_INT_INT22(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT22_SHIFT)) & DMA_INT_INT22_MASK) +#define DMA_INT_INT23_MASK (0x800000U) +#define DMA_INT_INT23_SHIFT (23U) +/*! INT23 - Interrupt Request 23 + * 0b0..The interrupt request for corresponding channel is cleared + * 0b1..The interrupt request for corresponding channel is active + */ +#define DMA_INT_INT23(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT23_SHIFT)) & DMA_INT_INT23_MASK) +#define DMA_INT_INT24_MASK (0x1000000U) +#define DMA_INT_INT24_SHIFT (24U) +/*! INT24 - Interrupt Request 24 + * 0b0..The interrupt request for corresponding channel is cleared + * 0b1..The interrupt request for corresponding channel is active + */ +#define DMA_INT_INT24(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT24_SHIFT)) & DMA_INT_INT24_MASK) +#define DMA_INT_INT25_MASK (0x2000000U) +#define DMA_INT_INT25_SHIFT (25U) +/*! INT25 - Interrupt Request 25 + * 0b0..The interrupt request for corresponding channel is cleared + * 0b1..The interrupt request for corresponding channel is active + */ +#define DMA_INT_INT25(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT25_SHIFT)) & DMA_INT_INT25_MASK) +#define DMA_INT_INT26_MASK (0x4000000U) +#define DMA_INT_INT26_SHIFT (26U) +/*! INT26 - Interrupt Request 26 + * 0b0..The interrupt request for corresponding channel is cleared + * 0b1..The interrupt request for corresponding channel is active + */ +#define DMA_INT_INT26(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT26_SHIFT)) & DMA_INT_INT26_MASK) +#define DMA_INT_INT27_MASK (0x8000000U) +#define DMA_INT_INT27_SHIFT (27U) +/*! INT27 - Interrupt Request 27 + * 0b0..The interrupt request for corresponding channel is cleared + * 0b1..The interrupt request for corresponding channel is active + */ +#define DMA_INT_INT27(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT27_SHIFT)) & DMA_INT_INT27_MASK) +#define DMA_INT_INT28_MASK (0x10000000U) +#define DMA_INT_INT28_SHIFT (28U) +/*! INT28 - Interrupt Request 28 + * 0b0..The interrupt request for corresponding channel is cleared + * 0b1..The interrupt request for corresponding channel is active + */ +#define DMA_INT_INT28(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT28_SHIFT)) & DMA_INT_INT28_MASK) +#define DMA_INT_INT29_MASK (0x20000000U) +#define DMA_INT_INT29_SHIFT (29U) +/*! INT29 - Interrupt Request 29 + * 0b0..The interrupt request for corresponding channel is cleared + * 0b1..The interrupt request for corresponding channel is active + */ +#define DMA_INT_INT29(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT29_SHIFT)) & DMA_INT_INT29_MASK) +#define DMA_INT_INT30_MASK (0x40000000U) +#define DMA_INT_INT30_SHIFT (30U) +/*! INT30 - Interrupt Request 30 + * 0b0..The interrupt request for corresponding channel is cleared + * 0b1..The interrupt request for corresponding channel is active + */ +#define DMA_INT_INT30(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT30_SHIFT)) & DMA_INT_INT30_MASK) +#define DMA_INT_INT31_MASK (0x80000000U) +#define DMA_INT_INT31_SHIFT (31U) +/*! INT31 - Interrupt Request 31 + * 0b0..The interrupt request for corresponding channel is cleared + * 0b1..The interrupt request for corresponding channel is active + */ +#define DMA_INT_INT31(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT31_SHIFT)) & DMA_INT_INT31_MASK) +/*! @} */ + +/*! @name ERR - Error Register */ +/*! @{ */ +#define DMA_ERR_ERR0_MASK (0x1U) +#define DMA_ERR_ERR0_SHIFT (0U) +/*! ERR0 - Error In Channel 0 + * 0b0..An error in this channel has not occurred + * 0b1..An error in this channel has occurred + */ +#define DMA_ERR_ERR0(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR0_SHIFT)) & DMA_ERR_ERR0_MASK) +#define DMA_ERR_ERR1_MASK (0x2U) +#define DMA_ERR_ERR1_SHIFT (1U) +/*! ERR1 - Error In Channel 1 + * 0b0..An error in this channel has not occurred + * 0b1..An error in this channel has occurred + */ +#define DMA_ERR_ERR1(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR1_SHIFT)) & DMA_ERR_ERR1_MASK) +#define DMA_ERR_ERR2_MASK (0x4U) +#define DMA_ERR_ERR2_SHIFT (2U) +/*! ERR2 - Error In Channel 2 + * 0b0..An error in this channel has not occurred + * 0b1..An error in this channel has occurred + */ +#define DMA_ERR_ERR2(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR2_SHIFT)) & DMA_ERR_ERR2_MASK) +#define DMA_ERR_ERR3_MASK (0x8U) +#define DMA_ERR_ERR3_SHIFT (3U) +/*! ERR3 - Error In Channel 3 + * 0b0..An error in this channel has not occurred + * 0b1..An error in this channel has occurred + */ +#define DMA_ERR_ERR3(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR3_SHIFT)) & DMA_ERR_ERR3_MASK) +#define DMA_ERR_ERR4_MASK (0x10U) +#define DMA_ERR_ERR4_SHIFT (4U) +/*! ERR4 - Error In Channel 4 + * 0b0..An error in this channel has not occurred + * 0b1..An error in this channel has occurred + */ +#define DMA_ERR_ERR4(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR4_SHIFT)) & DMA_ERR_ERR4_MASK) +#define DMA_ERR_ERR5_MASK (0x20U) +#define DMA_ERR_ERR5_SHIFT (5U) +/*! ERR5 - Error In Channel 5 + * 0b0..An error in this channel has not occurred + * 0b1..An error in this channel has occurred + */ +#define DMA_ERR_ERR5(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR5_SHIFT)) & DMA_ERR_ERR5_MASK) +#define DMA_ERR_ERR6_MASK (0x40U) +#define DMA_ERR_ERR6_SHIFT (6U) +/*! ERR6 - Error In Channel 6 + * 0b0..An error in this channel has not occurred + * 0b1..An error in this channel has occurred + */ +#define DMA_ERR_ERR6(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR6_SHIFT)) & DMA_ERR_ERR6_MASK) +#define DMA_ERR_ERR7_MASK (0x80U) +#define DMA_ERR_ERR7_SHIFT (7U) +/*! ERR7 - Error In Channel 7 + * 0b0..An error in this channel has not occurred + * 0b1..An error in this channel has occurred + */ +#define DMA_ERR_ERR7(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR7_SHIFT)) & DMA_ERR_ERR7_MASK) +#define DMA_ERR_ERR8_MASK (0x100U) +#define DMA_ERR_ERR8_SHIFT (8U) +/*! ERR8 - Error In Channel 8 + * 0b0..An error in this channel has not occurred + * 0b1..An error in this channel has occurred + */ +#define DMA_ERR_ERR8(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR8_SHIFT)) & DMA_ERR_ERR8_MASK) +#define DMA_ERR_ERR9_MASK (0x200U) +#define DMA_ERR_ERR9_SHIFT (9U) +/*! ERR9 - Error In Channel 9 + * 0b0..An error in this channel has not occurred + * 0b1..An error in this channel has occurred + */ +#define DMA_ERR_ERR9(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR9_SHIFT)) & DMA_ERR_ERR9_MASK) +#define DMA_ERR_ERR10_MASK (0x400U) +#define DMA_ERR_ERR10_SHIFT (10U) +/*! ERR10 - Error In Channel 10 + * 0b0..An error in this channel has not occurred + * 0b1..An error in this channel has occurred + */ +#define DMA_ERR_ERR10(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR10_SHIFT)) & DMA_ERR_ERR10_MASK) +#define DMA_ERR_ERR11_MASK (0x800U) +#define DMA_ERR_ERR11_SHIFT (11U) +/*! ERR11 - Error In Channel 11 + * 0b0..An error in this channel has not occurred + * 0b1..An error in this channel has occurred + */ +#define DMA_ERR_ERR11(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR11_SHIFT)) & DMA_ERR_ERR11_MASK) +#define DMA_ERR_ERR12_MASK (0x1000U) +#define DMA_ERR_ERR12_SHIFT (12U) +/*! ERR12 - Error In Channel 12 + * 0b0..An error in this channel has not occurred + * 0b1..An error in this channel has occurred + */ +#define DMA_ERR_ERR12(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR12_SHIFT)) & DMA_ERR_ERR12_MASK) +#define DMA_ERR_ERR13_MASK (0x2000U) +#define DMA_ERR_ERR13_SHIFT (13U) +/*! ERR13 - Error In Channel 13 + * 0b0..An error in this channel has not occurred + * 0b1..An error in this channel has occurred + */ +#define DMA_ERR_ERR13(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR13_SHIFT)) & DMA_ERR_ERR13_MASK) +#define DMA_ERR_ERR14_MASK (0x4000U) +#define DMA_ERR_ERR14_SHIFT (14U) +/*! ERR14 - Error In Channel 14 + * 0b0..An error in this channel has not occurred + * 0b1..An error in this channel has occurred + */ +#define DMA_ERR_ERR14(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR14_SHIFT)) & DMA_ERR_ERR14_MASK) +#define DMA_ERR_ERR15_MASK (0x8000U) +#define DMA_ERR_ERR15_SHIFT (15U) +/*! ERR15 - Error In Channel 15 + * 0b0..An error in this channel has not occurred + * 0b1..An error in this channel has occurred + */ +#define DMA_ERR_ERR15(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR15_SHIFT)) & DMA_ERR_ERR15_MASK) +#define DMA_ERR_ERR16_MASK (0x10000U) +#define DMA_ERR_ERR16_SHIFT (16U) +/*! ERR16 - Error In Channel 16 + * 0b0..An error in this channel has not occurred + * 0b1..An error in this channel has occurred + */ +#define DMA_ERR_ERR16(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR16_SHIFT)) & DMA_ERR_ERR16_MASK) +#define DMA_ERR_ERR17_MASK (0x20000U) +#define DMA_ERR_ERR17_SHIFT (17U) +/*! ERR17 - Error In Channel 17 + * 0b0..An error in this channel has not occurred + * 0b1..An error in this channel has occurred + */ +#define DMA_ERR_ERR17(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR17_SHIFT)) & DMA_ERR_ERR17_MASK) +#define DMA_ERR_ERR18_MASK (0x40000U) +#define DMA_ERR_ERR18_SHIFT (18U) +/*! ERR18 - Error In Channel 18 + * 0b0..An error in this channel has not occurred + * 0b1..An error in this channel has occurred + */ +#define DMA_ERR_ERR18(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR18_SHIFT)) & DMA_ERR_ERR18_MASK) +#define DMA_ERR_ERR19_MASK (0x80000U) +#define DMA_ERR_ERR19_SHIFT (19U) +/*! ERR19 - Error In Channel 19 + * 0b0..An error in this channel has not occurred + * 0b1..An error in this channel has occurred + */ +#define DMA_ERR_ERR19(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR19_SHIFT)) & DMA_ERR_ERR19_MASK) +#define DMA_ERR_ERR20_MASK (0x100000U) +#define DMA_ERR_ERR20_SHIFT (20U) +/*! ERR20 - Error In Channel 20 + * 0b0..An error in this channel has not occurred + * 0b1..An error in this channel has occurred + */ +#define DMA_ERR_ERR20(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR20_SHIFT)) & DMA_ERR_ERR20_MASK) +#define DMA_ERR_ERR21_MASK (0x200000U) +#define DMA_ERR_ERR21_SHIFT (21U) +/*! ERR21 - Error In Channel 21 + * 0b0..An error in this channel has not occurred + * 0b1..An error in this channel has occurred + */ +#define DMA_ERR_ERR21(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR21_SHIFT)) & DMA_ERR_ERR21_MASK) +#define DMA_ERR_ERR22_MASK (0x400000U) +#define DMA_ERR_ERR22_SHIFT (22U) +/*! ERR22 - Error In Channel 22 + * 0b0..An error in this channel has not occurred + * 0b1..An error in this channel has occurred + */ +#define DMA_ERR_ERR22(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR22_SHIFT)) & DMA_ERR_ERR22_MASK) +#define DMA_ERR_ERR23_MASK (0x800000U) +#define DMA_ERR_ERR23_SHIFT (23U) +/*! ERR23 - Error In Channel 23 + * 0b0..An error in this channel has not occurred + * 0b1..An error in this channel has occurred + */ +#define DMA_ERR_ERR23(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR23_SHIFT)) & DMA_ERR_ERR23_MASK) +#define DMA_ERR_ERR24_MASK (0x1000000U) +#define DMA_ERR_ERR24_SHIFT (24U) +/*! ERR24 - Error In Channel 24 + * 0b0..An error in this channel has not occurred + * 0b1..An error in this channel has occurred + */ +#define DMA_ERR_ERR24(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR24_SHIFT)) & DMA_ERR_ERR24_MASK) +#define DMA_ERR_ERR25_MASK (0x2000000U) +#define DMA_ERR_ERR25_SHIFT (25U) +/*! ERR25 - Error In Channel 25 + * 0b0..An error in this channel has not occurred + * 0b1..An error in this channel has occurred + */ +#define DMA_ERR_ERR25(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR25_SHIFT)) & DMA_ERR_ERR25_MASK) +#define DMA_ERR_ERR26_MASK (0x4000000U) +#define DMA_ERR_ERR26_SHIFT (26U) +/*! ERR26 - Error In Channel 26 + * 0b0..An error in this channel has not occurred + * 0b1..An error in this channel has occurred + */ +#define DMA_ERR_ERR26(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR26_SHIFT)) & DMA_ERR_ERR26_MASK) +#define DMA_ERR_ERR27_MASK (0x8000000U) +#define DMA_ERR_ERR27_SHIFT (27U) +/*! ERR27 - Error In Channel 27 + * 0b0..An error in this channel has not occurred + * 0b1..An error in this channel has occurred + */ +#define DMA_ERR_ERR27(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR27_SHIFT)) & DMA_ERR_ERR27_MASK) +#define DMA_ERR_ERR28_MASK (0x10000000U) +#define DMA_ERR_ERR28_SHIFT (28U) +/*! ERR28 - Error In Channel 28 + * 0b0..An error in this channel has not occurred + * 0b1..An error in this channel has occurred + */ +#define DMA_ERR_ERR28(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR28_SHIFT)) & DMA_ERR_ERR28_MASK) +#define DMA_ERR_ERR29_MASK (0x20000000U) +#define DMA_ERR_ERR29_SHIFT (29U) +/*! ERR29 - Error In Channel 29 + * 0b0..An error in this channel has not occurred + * 0b1..An error in this channel has occurred + */ +#define DMA_ERR_ERR29(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR29_SHIFT)) & DMA_ERR_ERR29_MASK) +#define DMA_ERR_ERR30_MASK (0x40000000U) +#define DMA_ERR_ERR30_SHIFT (30U) +/*! ERR30 - Error In Channel 30 + * 0b0..An error in this channel has not occurred + * 0b1..An error in this channel has occurred + */ +#define DMA_ERR_ERR30(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR30_SHIFT)) & DMA_ERR_ERR30_MASK) +#define DMA_ERR_ERR31_MASK (0x80000000U) +#define DMA_ERR_ERR31_SHIFT (31U) +/*! ERR31 - Error In Channel 31 + * 0b0..An error in this channel has not occurred + * 0b1..An error in this channel has occurred + */ +#define DMA_ERR_ERR31(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR31_SHIFT)) & DMA_ERR_ERR31_MASK) +/*! @} */ + +/*! @name HRS - Hardware Request Status Register */ +/*! @{ */ +#define DMA_HRS_HRS0_MASK (0x1U) +#define DMA_HRS_HRS0_SHIFT (0U) +/*! HRS0 - Hardware Request Status Channel 0 + * 0b0..A hardware service request for channel 0 is not present + * 0b1..A hardware service request for channel 0 is present + */ +#define DMA_HRS_HRS0(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS0_SHIFT)) & DMA_HRS_HRS0_MASK) +#define DMA_HRS_HRS1_MASK (0x2U) +#define DMA_HRS_HRS1_SHIFT (1U) +/*! HRS1 - Hardware Request Status Channel 1 + * 0b0..A hardware service request for channel 1 is not present + * 0b1..A hardware service request for channel 1 is present + */ +#define DMA_HRS_HRS1(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS1_SHIFT)) & DMA_HRS_HRS1_MASK) +#define DMA_HRS_HRS2_MASK (0x4U) +#define DMA_HRS_HRS2_SHIFT (2U) +/*! HRS2 - Hardware Request Status Channel 2 + * 0b0..A hardware service request for channel 2 is not present + * 0b1..A hardware service request for channel 2 is present + */ +#define DMA_HRS_HRS2(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS2_SHIFT)) & DMA_HRS_HRS2_MASK) +#define DMA_HRS_HRS3_MASK (0x8U) +#define DMA_HRS_HRS3_SHIFT (3U) +/*! HRS3 - Hardware Request Status Channel 3 + * 0b0..A hardware service request for channel 3 is not present + * 0b1..A hardware service request for channel 3 is present + */ +#define DMA_HRS_HRS3(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS3_SHIFT)) & DMA_HRS_HRS3_MASK) +#define DMA_HRS_HRS4_MASK (0x10U) +#define DMA_HRS_HRS4_SHIFT (4U) +/*! HRS4 - Hardware Request Status Channel 4 + * 0b0..A hardware service request for channel 4 is not present + * 0b1..A hardware service request for channel 4 is present + */ +#define DMA_HRS_HRS4(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS4_SHIFT)) & DMA_HRS_HRS4_MASK) +#define DMA_HRS_HRS5_MASK (0x20U) +#define DMA_HRS_HRS5_SHIFT (5U) +/*! HRS5 - Hardware Request Status Channel 5 + * 0b0..A hardware service request for channel 5 is not present + * 0b1..A hardware service request for channel 5 is present + */ +#define DMA_HRS_HRS5(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS5_SHIFT)) & DMA_HRS_HRS5_MASK) +#define DMA_HRS_HRS6_MASK (0x40U) +#define DMA_HRS_HRS6_SHIFT (6U) +/*! HRS6 - Hardware Request Status Channel 6 + * 0b0..A hardware service request for channel 6 is not present + * 0b1..A hardware service request for channel 6 is present + */ +#define DMA_HRS_HRS6(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS6_SHIFT)) & DMA_HRS_HRS6_MASK) +#define DMA_HRS_HRS7_MASK (0x80U) +#define DMA_HRS_HRS7_SHIFT (7U) +/*! HRS7 - Hardware Request Status Channel 7 + * 0b0..A hardware service request for channel 7 is not present + * 0b1..A hardware service request for channel 7 is present + */ +#define DMA_HRS_HRS7(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS7_SHIFT)) & DMA_HRS_HRS7_MASK) +#define DMA_HRS_HRS8_MASK (0x100U) +#define DMA_HRS_HRS8_SHIFT (8U) +/*! HRS8 - Hardware Request Status Channel 8 + * 0b0..A hardware service request for channel 8 is not present + * 0b1..A hardware service request for channel 8 is present + */ +#define DMA_HRS_HRS8(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS8_SHIFT)) & DMA_HRS_HRS8_MASK) +#define DMA_HRS_HRS9_MASK (0x200U) +#define DMA_HRS_HRS9_SHIFT (9U) +/*! HRS9 - Hardware Request Status Channel 9 + * 0b0..A hardware service request for channel 9 is not present + * 0b1..A hardware service request for channel 9 is present + */ +#define DMA_HRS_HRS9(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS9_SHIFT)) & DMA_HRS_HRS9_MASK) +#define DMA_HRS_HRS10_MASK (0x400U) +#define DMA_HRS_HRS10_SHIFT (10U) +/*! HRS10 - Hardware Request Status Channel 10 + * 0b0..A hardware service request for channel 10 is not present + * 0b1..A hardware service request for channel 10 is present + */ +#define DMA_HRS_HRS10(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS10_SHIFT)) & DMA_HRS_HRS10_MASK) +#define DMA_HRS_HRS11_MASK (0x800U) +#define DMA_HRS_HRS11_SHIFT (11U) +/*! HRS11 - Hardware Request Status Channel 11 + * 0b0..A hardware service request for channel 11 is not present + * 0b1..A hardware service request for channel 11 is present + */ +#define DMA_HRS_HRS11(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS11_SHIFT)) & DMA_HRS_HRS11_MASK) +#define DMA_HRS_HRS12_MASK (0x1000U) +#define DMA_HRS_HRS12_SHIFT (12U) +/*! HRS12 - Hardware Request Status Channel 12 + * 0b0..A hardware service request for channel 12 is not present + * 0b1..A hardware service request for channel 12 is present + */ +#define DMA_HRS_HRS12(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS12_SHIFT)) & DMA_HRS_HRS12_MASK) +#define DMA_HRS_HRS13_MASK (0x2000U) +#define DMA_HRS_HRS13_SHIFT (13U) +/*! HRS13 - Hardware Request Status Channel 13 + * 0b0..A hardware service request for channel 13 is not present + * 0b1..A hardware service request for channel 13 is present + */ +#define DMA_HRS_HRS13(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS13_SHIFT)) & DMA_HRS_HRS13_MASK) +#define DMA_HRS_HRS14_MASK (0x4000U) +#define DMA_HRS_HRS14_SHIFT (14U) +/*! HRS14 - Hardware Request Status Channel 14 + * 0b0..A hardware service request for channel 14 is not present + * 0b1..A hardware service request for channel 14 is present + */ +#define DMA_HRS_HRS14(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS14_SHIFT)) & DMA_HRS_HRS14_MASK) +#define DMA_HRS_HRS15_MASK (0x8000U) +#define DMA_HRS_HRS15_SHIFT (15U) +/*! HRS15 - Hardware Request Status Channel 15 + * 0b0..A hardware service request for channel 15 is not present + * 0b1..A hardware service request for channel 15 is present + */ +#define DMA_HRS_HRS15(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS15_SHIFT)) & DMA_HRS_HRS15_MASK) +#define DMA_HRS_HRS16_MASK (0x10000U) +#define DMA_HRS_HRS16_SHIFT (16U) +/*! HRS16 - Hardware Request Status Channel 16 + * 0b0..A hardware service request for channel 16 is not present + * 0b1..A hardware service request for channel 16 is present + */ +#define DMA_HRS_HRS16(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS16_SHIFT)) & DMA_HRS_HRS16_MASK) +#define DMA_HRS_HRS17_MASK (0x20000U) +#define DMA_HRS_HRS17_SHIFT (17U) +/*! HRS17 - Hardware Request Status Channel 17 + * 0b0..A hardware service request for channel 17 is not present + * 0b1..A hardware service request for channel 17 is present + */ +#define DMA_HRS_HRS17(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS17_SHIFT)) & DMA_HRS_HRS17_MASK) +#define DMA_HRS_HRS18_MASK (0x40000U) +#define DMA_HRS_HRS18_SHIFT (18U) +/*! HRS18 - Hardware Request Status Channel 18 + * 0b0..A hardware service request for channel 18 is not present + * 0b1..A hardware service request for channel 18 is present + */ +#define DMA_HRS_HRS18(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS18_SHIFT)) & DMA_HRS_HRS18_MASK) +#define DMA_HRS_HRS19_MASK (0x80000U) +#define DMA_HRS_HRS19_SHIFT (19U) +/*! HRS19 - Hardware Request Status Channel 19 + * 0b0..A hardware service request for channel 19 is not present + * 0b1..A hardware service request for channel 19 is present + */ +#define DMA_HRS_HRS19(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS19_SHIFT)) & DMA_HRS_HRS19_MASK) +#define DMA_HRS_HRS20_MASK (0x100000U) +#define DMA_HRS_HRS20_SHIFT (20U) +/*! HRS20 - Hardware Request Status Channel 20 + * 0b0..A hardware service request for channel 20 is not present + * 0b1..A hardware service request for channel 20 is present + */ +#define DMA_HRS_HRS20(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS20_SHIFT)) & DMA_HRS_HRS20_MASK) +#define DMA_HRS_HRS21_MASK (0x200000U) +#define DMA_HRS_HRS21_SHIFT (21U) +/*! HRS21 - Hardware Request Status Channel 21 + * 0b0..A hardware service request for channel 21 is not present + * 0b1..A hardware service request for channel 21 is present + */ +#define DMA_HRS_HRS21(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS21_SHIFT)) & DMA_HRS_HRS21_MASK) +#define DMA_HRS_HRS22_MASK (0x400000U) +#define DMA_HRS_HRS22_SHIFT (22U) +/*! HRS22 - Hardware Request Status Channel 22 + * 0b0..A hardware service request for channel 22 is not present + * 0b1..A hardware service request for channel 22 is present + */ +#define DMA_HRS_HRS22(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS22_SHIFT)) & DMA_HRS_HRS22_MASK) +#define DMA_HRS_HRS23_MASK (0x800000U) +#define DMA_HRS_HRS23_SHIFT (23U) +/*! HRS23 - Hardware Request Status Channel 23 + * 0b0..A hardware service request for channel 23 is not present + * 0b1..A hardware service request for channel 23 is present + */ +#define DMA_HRS_HRS23(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS23_SHIFT)) & DMA_HRS_HRS23_MASK) +#define DMA_HRS_HRS24_MASK (0x1000000U) +#define DMA_HRS_HRS24_SHIFT (24U) +/*! HRS24 - Hardware Request Status Channel 24 + * 0b0..A hardware service request for channel 24 is not present + * 0b1..A hardware service request for channel 24 is present + */ +#define DMA_HRS_HRS24(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS24_SHIFT)) & DMA_HRS_HRS24_MASK) +#define DMA_HRS_HRS25_MASK (0x2000000U) +#define DMA_HRS_HRS25_SHIFT (25U) +/*! HRS25 - Hardware Request Status Channel 25 + * 0b0..A hardware service request for channel 25 is not present + * 0b1..A hardware service request for channel 25 is present + */ +#define DMA_HRS_HRS25(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS25_SHIFT)) & DMA_HRS_HRS25_MASK) +#define DMA_HRS_HRS26_MASK (0x4000000U) +#define DMA_HRS_HRS26_SHIFT (26U) +/*! HRS26 - Hardware Request Status Channel 26 + * 0b0..A hardware service request for channel 26 is not present + * 0b1..A hardware service request for channel 26 is present + */ +#define DMA_HRS_HRS26(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS26_SHIFT)) & DMA_HRS_HRS26_MASK) +#define DMA_HRS_HRS27_MASK (0x8000000U) +#define DMA_HRS_HRS27_SHIFT (27U) +/*! HRS27 - Hardware Request Status Channel 27 + * 0b0..A hardware service request for channel 27 is not present + * 0b1..A hardware service request for channel 27 is present + */ +#define DMA_HRS_HRS27(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS27_SHIFT)) & DMA_HRS_HRS27_MASK) +#define DMA_HRS_HRS28_MASK (0x10000000U) +#define DMA_HRS_HRS28_SHIFT (28U) +/*! HRS28 - Hardware Request Status Channel 28 + * 0b0..A hardware service request for channel 28 is not present + * 0b1..A hardware service request for channel 28 is present + */ +#define DMA_HRS_HRS28(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS28_SHIFT)) & DMA_HRS_HRS28_MASK) +#define DMA_HRS_HRS29_MASK (0x20000000U) +#define DMA_HRS_HRS29_SHIFT (29U) +/*! HRS29 - Hardware Request Status Channel 29 + * 0b0..A hardware service request for channel 29 is not preset + * 0b1..A hardware service request for channel 29 is present + */ +#define DMA_HRS_HRS29(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS29_SHIFT)) & DMA_HRS_HRS29_MASK) +#define DMA_HRS_HRS30_MASK (0x40000000U) +#define DMA_HRS_HRS30_SHIFT (30U) +/*! HRS30 - Hardware Request Status Channel 30 + * 0b0..A hardware service request for channel 30 is not present + * 0b1..A hardware service request for channel 30 is present + */ +#define DMA_HRS_HRS30(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS30_SHIFT)) & DMA_HRS_HRS30_MASK) +#define DMA_HRS_HRS31_MASK (0x80000000U) +#define DMA_HRS_HRS31_SHIFT (31U) +/*! HRS31 - Hardware Request Status Channel 31 + * 0b0..A hardware service request for channel 31 is not present + * 0b1..A hardware service request for channel 31 is present + */ +#define DMA_HRS_HRS31(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS31_SHIFT)) & DMA_HRS_HRS31_MASK) +/*! @} */ + +/*! @name EARS - Enable Asynchronous Request in Stop Register */ +/*! @{ */ +#define DMA_EARS_EDREQ_0_MASK (0x1U) +#define DMA_EARS_EDREQ_0_SHIFT (0U) +/*! EDREQ_0 - Enable asynchronous DMA request in stop mode for channel 0. + * 0b0..Disable asynchronous DMA request for channel 0. + * 0b1..Enable asynchronous DMA request for channel 0. + */ +#define DMA_EARS_EDREQ_0(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_0_SHIFT)) & DMA_EARS_EDREQ_0_MASK) +#define DMA_EARS_EDREQ_1_MASK (0x2U) +#define DMA_EARS_EDREQ_1_SHIFT (1U) +/*! EDREQ_1 - Enable asynchronous DMA request in stop mode for channel 1. + * 0b0..Disable asynchronous DMA request for channel 1 + * 0b1..Enable asynchronous DMA request for channel 1. + */ +#define DMA_EARS_EDREQ_1(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_1_SHIFT)) & DMA_EARS_EDREQ_1_MASK) +#define DMA_EARS_EDREQ_2_MASK (0x4U) +#define DMA_EARS_EDREQ_2_SHIFT (2U) +/*! EDREQ_2 - Enable asynchronous DMA request in stop mode for channel 2. + * 0b0..Disable asynchronous DMA request for channel 2. + * 0b1..Enable asynchronous DMA request for channel 2. + */ +#define DMA_EARS_EDREQ_2(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_2_SHIFT)) & DMA_EARS_EDREQ_2_MASK) +#define DMA_EARS_EDREQ_3_MASK (0x8U) +#define DMA_EARS_EDREQ_3_SHIFT (3U) +/*! EDREQ_3 - Enable asynchronous DMA request in stop mode for channel 3. + * 0b0..Disable asynchronous DMA request for channel 3. + * 0b1..Enable asynchronous DMA request for channel 3. + */ +#define DMA_EARS_EDREQ_3(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_3_SHIFT)) & DMA_EARS_EDREQ_3_MASK) +#define DMA_EARS_EDREQ_4_MASK (0x10U) +#define DMA_EARS_EDREQ_4_SHIFT (4U) +/*! EDREQ_4 - Enable asynchronous DMA request in stop mode for channel 4 + * 0b0..Disable asynchronous DMA request for channel 4. + * 0b1..Enable asynchronous DMA request for channel 4. + */ +#define DMA_EARS_EDREQ_4(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_4_SHIFT)) & DMA_EARS_EDREQ_4_MASK) +#define DMA_EARS_EDREQ_5_MASK (0x20U) +#define DMA_EARS_EDREQ_5_SHIFT (5U) +/*! EDREQ_5 - Enable asynchronous DMA request in stop mode for channel 5 + * 0b0..Disable asynchronous DMA request for channel 5. + * 0b1..Enable asynchronous DMA request for channel 5. + */ +#define DMA_EARS_EDREQ_5(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_5_SHIFT)) & DMA_EARS_EDREQ_5_MASK) +#define DMA_EARS_EDREQ_6_MASK (0x40U) +#define DMA_EARS_EDREQ_6_SHIFT (6U) +/*! EDREQ_6 - Enable asynchronous DMA request in stop mode for channel 6 + * 0b0..Disable asynchronous DMA request for channel 6. + * 0b1..Enable asynchronous DMA request for channel 6. + */ +#define DMA_EARS_EDREQ_6(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_6_SHIFT)) & DMA_EARS_EDREQ_6_MASK) +#define DMA_EARS_EDREQ_7_MASK (0x80U) +#define DMA_EARS_EDREQ_7_SHIFT (7U) +/*! EDREQ_7 - Enable asynchronous DMA request in stop mode for channel 7 + * 0b0..Disable asynchronous DMA request for channel 7. + * 0b1..Enable asynchronous DMA request for channel 7. + */ +#define DMA_EARS_EDREQ_7(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_7_SHIFT)) & DMA_EARS_EDREQ_7_MASK) +#define DMA_EARS_EDREQ_8_MASK (0x100U) +#define DMA_EARS_EDREQ_8_SHIFT (8U) +/*! EDREQ_8 - Enable asynchronous DMA request in stop mode for channel 8 + * 0b0..Disable asynchronous DMA request for channel 8. + * 0b1..Enable asynchronous DMA request for channel 8. + */ +#define DMA_EARS_EDREQ_8(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_8_SHIFT)) & DMA_EARS_EDREQ_8_MASK) +#define DMA_EARS_EDREQ_9_MASK (0x200U) +#define DMA_EARS_EDREQ_9_SHIFT (9U) +/*! EDREQ_9 - Enable asynchronous DMA request in stop mode for channel 9 + * 0b0..Disable asynchronous DMA request for channel 9. + * 0b1..Enable asynchronous DMA request for channel 9. + */ +#define DMA_EARS_EDREQ_9(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_9_SHIFT)) & DMA_EARS_EDREQ_9_MASK) +#define DMA_EARS_EDREQ_10_MASK (0x400U) +#define DMA_EARS_EDREQ_10_SHIFT (10U) +/*! EDREQ_10 - Enable asynchronous DMA request in stop mode for channel 10 + * 0b0..Disable asynchronous DMA request for channel 10. + * 0b1..Enable asynchronous DMA request for channel 10. + */ +#define DMA_EARS_EDREQ_10(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_10_SHIFT)) & DMA_EARS_EDREQ_10_MASK) +#define DMA_EARS_EDREQ_11_MASK (0x800U) +#define DMA_EARS_EDREQ_11_SHIFT (11U) +/*! EDREQ_11 - Enable asynchronous DMA request in stop mode for channel 11 + * 0b0..Disable asynchronous DMA request for channel 11. + * 0b1..Enable asynchronous DMA request for channel 11. + */ +#define DMA_EARS_EDREQ_11(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_11_SHIFT)) & DMA_EARS_EDREQ_11_MASK) +#define DMA_EARS_EDREQ_12_MASK (0x1000U) +#define DMA_EARS_EDREQ_12_SHIFT (12U) +/*! EDREQ_12 - Enable asynchronous DMA request in stop mode for channel 12 + * 0b0..Disable asynchronous DMA request for channel 12. + * 0b1..Enable asynchronous DMA request for channel 12. + */ +#define DMA_EARS_EDREQ_12(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_12_SHIFT)) & DMA_EARS_EDREQ_12_MASK) +#define DMA_EARS_EDREQ_13_MASK (0x2000U) +#define DMA_EARS_EDREQ_13_SHIFT (13U) +/*! EDREQ_13 - Enable asynchronous DMA request in stop mode for channel 13 + * 0b0..Disable asynchronous DMA request for channel 13. + * 0b1..Enable asynchronous DMA request for channel 13. + */ +#define DMA_EARS_EDREQ_13(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_13_SHIFT)) & DMA_EARS_EDREQ_13_MASK) +#define DMA_EARS_EDREQ_14_MASK (0x4000U) +#define DMA_EARS_EDREQ_14_SHIFT (14U) +/*! EDREQ_14 - Enable asynchronous DMA request in stop mode for channel 14 + * 0b0..Disable asynchronous DMA request for channel 14. + * 0b1..Enable asynchronous DMA request for channel 14. + */ +#define DMA_EARS_EDREQ_14(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_14_SHIFT)) & DMA_EARS_EDREQ_14_MASK) +#define DMA_EARS_EDREQ_15_MASK (0x8000U) +#define DMA_EARS_EDREQ_15_SHIFT (15U) +/*! EDREQ_15 - Enable asynchronous DMA request in stop mode for channel 15 + * 0b0..Disable asynchronous DMA request for channel 15. + * 0b1..Enable asynchronous DMA request for channel 15. + */ +#define DMA_EARS_EDREQ_15(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_15_SHIFT)) & DMA_EARS_EDREQ_15_MASK) +#define DMA_EARS_EDREQ_16_MASK (0x10000U) +#define DMA_EARS_EDREQ_16_SHIFT (16U) +/*! EDREQ_16 - Enable asynchronous DMA request in stop mode for channel 16 + * 0b0..Disable asynchronous DMA request for channel 16 + * 0b1..Enable asynchronous DMA request for channel 16 + */ +#define DMA_EARS_EDREQ_16(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_16_SHIFT)) & DMA_EARS_EDREQ_16_MASK) +#define DMA_EARS_EDREQ_17_MASK (0x20000U) +#define DMA_EARS_EDREQ_17_SHIFT (17U) +/*! EDREQ_17 - Enable asynchronous DMA request in stop mode for channel 17 + * 0b0..Disable asynchronous DMA request for channel 17 + * 0b1..Enable asynchronous DMA request for channel 17 + */ +#define DMA_EARS_EDREQ_17(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_17_SHIFT)) & DMA_EARS_EDREQ_17_MASK) +#define DMA_EARS_EDREQ_18_MASK (0x40000U) +#define DMA_EARS_EDREQ_18_SHIFT (18U) +/*! EDREQ_18 - Enable asynchronous DMA request in stop mode for channel 18 + * 0b0..Disable asynchronous DMA request for channel 18 + * 0b1..Enable asynchronous DMA request for channel 18 + */ +#define DMA_EARS_EDREQ_18(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_18_SHIFT)) & DMA_EARS_EDREQ_18_MASK) +#define DMA_EARS_EDREQ_19_MASK (0x80000U) +#define DMA_EARS_EDREQ_19_SHIFT (19U) +/*! EDREQ_19 - Enable asynchronous DMA request in stop mode for channel 19 + * 0b0..Disable asynchronous DMA request for channel 19 + * 0b1..Enable asynchronous DMA request for channel 19 + */ +#define DMA_EARS_EDREQ_19(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_19_SHIFT)) & DMA_EARS_EDREQ_19_MASK) +#define DMA_EARS_EDREQ_20_MASK (0x100000U) +#define DMA_EARS_EDREQ_20_SHIFT (20U) +/*! EDREQ_20 - Enable asynchronous DMA request in stop mode for channel 20 + * 0b0..Disable asynchronous DMA request for channel 20 + * 0b1..Enable asynchronous DMA request for channel 20 + */ +#define DMA_EARS_EDREQ_20(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_20_SHIFT)) & DMA_EARS_EDREQ_20_MASK) +#define DMA_EARS_EDREQ_21_MASK (0x200000U) +#define DMA_EARS_EDREQ_21_SHIFT (21U) +/*! EDREQ_21 - Enable asynchronous DMA request in stop mode for channel 21 + * 0b0..Disable asynchronous DMA request for channel 21 + * 0b1..Enable asynchronous DMA request for channel 21 + */ +#define DMA_EARS_EDREQ_21(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_21_SHIFT)) & DMA_EARS_EDREQ_21_MASK) +#define DMA_EARS_EDREQ_22_MASK (0x400000U) +#define DMA_EARS_EDREQ_22_SHIFT (22U) +/*! EDREQ_22 - Enable asynchronous DMA request in stop mode for channel 22 + * 0b0..Disable asynchronous DMA request for channel 22 + * 0b1..Enable asynchronous DMA request for channel 22 + */ +#define DMA_EARS_EDREQ_22(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_22_SHIFT)) & DMA_EARS_EDREQ_22_MASK) +#define DMA_EARS_EDREQ_23_MASK (0x800000U) +#define DMA_EARS_EDREQ_23_SHIFT (23U) +/*! EDREQ_23 - Enable asynchronous DMA request in stop mode for channel 23 + * 0b0..Disable asynchronous DMA request for channel 23 + * 0b1..Enable asynchronous DMA request for channel 23 + */ +#define DMA_EARS_EDREQ_23(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_23_SHIFT)) & DMA_EARS_EDREQ_23_MASK) +#define DMA_EARS_EDREQ_24_MASK (0x1000000U) +#define DMA_EARS_EDREQ_24_SHIFT (24U) +/*! EDREQ_24 - Enable asynchronous DMA request in stop mode for channel 24 + * 0b0..Disable asynchronous DMA request for channel 24 + * 0b1..Enable asynchronous DMA request for channel 24 + */ +#define DMA_EARS_EDREQ_24(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_24_SHIFT)) & DMA_EARS_EDREQ_24_MASK) +#define DMA_EARS_EDREQ_25_MASK (0x2000000U) +#define DMA_EARS_EDREQ_25_SHIFT (25U) +/*! EDREQ_25 - Enable asynchronous DMA request in stop mode for channel 25 + * 0b0..Disable asynchronous DMA request for channel 25 + * 0b1..Enable asynchronous DMA request for channel 25 + */ +#define DMA_EARS_EDREQ_25(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_25_SHIFT)) & DMA_EARS_EDREQ_25_MASK) +#define DMA_EARS_EDREQ_26_MASK (0x4000000U) +#define DMA_EARS_EDREQ_26_SHIFT (26U) +/*! EDREQ_26 - Enable asynchronous DMA request in stop mode for channel 26 + * 0b0..Disable asynchronous DMA request for channel 26 + * 0b1..Enable asynchronous DMA request for channel 26 + */ +#define DMA_EARS_EDREQ_26(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_26_SHIFT)) & DMA_EARS_EDREQ_26_MASK) +#define DMA_EARS_EDREQ_27_MASK (0x8000000U) +#define DMA_EARS_EDREQ_27_SHIFT (27U) +/*! EDREQ_27 - Enable asynchronous DMA request in stop mode for channel 27 + * 0b0..Disable asynchronous DMA request for channel 27 + * 0b1..Enable asynchronous DMA request for channel 27 + */ +#define DMA_EARS_EDREQ_27(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_27_SHIFT)) & DMA_EARS_EDREQ_27_MASK) +#define DMA_EARS_EDREQ_28_MASK (0x10000000U) +#define DMA_EARS_EDREQ_28_SHIFT (28U) +/*! EDREQ_28 - Enable asynchronous DMA request in stop mode for channel 28 + * 0b0..Disable asynchronous DMA request for channel 28 + * 0b1..Enable asynchronous DMA request for channel 28 + */ +#define DMA_EARS_EDREQ_28(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_28_SHIFT)) & DMA_EARS_EDREQ_28_MASK) +#define DMA_EARS_EDREQ_29_MASK (0x20000000U) +#define DMA_EARS_EDREQ_29_SHIFT (29U) +/*! EDREQ_29 - Enable asynchronous DMA request in stop mode for channel 29 + * 0b0..Disable asynchronous DMA request for channel 29 + * 0b1..Enable asynchronous DMA request for channel 29 + */ +#define DMA_EARS_EDREQ_29(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_29_SHIFT)) & DMA_EARS_EDREQ_29_MASK) +#define DMA_EARS_EDREQ_30_MASK (0x40000000U) +#define DMA_EARS_EDREQ_30_SHIFT (30U) +/*! EDREQ_30 - Enable asynchronous DMA request in stop mode for channel 30 + * 0b0..Disable asynchronous DMA request for channel 30 + * 0b1..Enable asynchronous DMA request for channel 30 + */ +#define DMA_EARS_EDREQ_30(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_30_SHIFT)) & DMA_EARS_EDREQ_30_MASK) +#define DMA_EARS_EDREQ_31_MASK (0x80000000U) +#define DMA_EARS_EDREQ_31_SHIFT (31U) +/*! EDREQ_31 - Enable asynchronous DMA request in stop mode for channel 31 + * 0b0..Disable asynchronous DMA request for channel 31 + * 0b1..Enable asynchronous DMA request for channel 31 + */ +#define DMA_EARS_EDREQ_31(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_31_SHIFT)) & DMA_EARS_EDREQ_31_MASK) +/*! @} */ + +/*! @name DCHPRI3 - Channel n Priority Register */ +/*! @{ */ +#define DMA_DCHPRI3_CHPRI_MASK (0xFU) +#define DMA_DCHPRI3_CHPRI_SHIFT (0U) +#define DMA_DCHPRI3_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI3_CHPRI_SHIFT)) & DMA_DCHPRI3_CHPRI_MASK) +#define DMA_DCHPRI3_GRPPRI_MASK (0x30U) +#define DMA_DCHPRI3_GRPPRI_SHIFT (4U) +#define DMA_DCHPRI3_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI3_GRPPRI_SHIFT)) & DMA_DCHPRI3_GRPPRI_MASK) +#define DMA_DCHPRI3_DPA_MASK (0x40U) +#define DMA_DCHPRI3_DPA_SHIFT (6U) +/*! DPA - Disable Preempt Ability. This field resets to 0. + * 0b0..Channel n can suspend a lower priority channel. + * 0b1..Channel n cannot suspend any channel, regardless of channel priority. + */ +#define DMA_DCHPRI3_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI3_DPA_SHIFT)) & DMA_DCHPRI3_DPA_MASK) +#define DMA_DCHPRI3_ECP_MASK (0x80U) +#define DMA_DCHPRI3_ECP_SHIFT (7U) +/*! ECP - Enable Channel Preemption. This field resets to 0. + * 0b0..Channel n cannot be suspended by a higher priority channel's service request. + * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel. + */ +#define DMA_DCHPRI3_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI3_ECP_SHIFT)) & DMA_DCHPRI3_ECP_MASK) +/*! @} */ + +/*! @name DCHPRI2 - Channel n Priority Register */ +/*! @{ */ +#define DMA_DCHPRI2_CHPRI_MASK (0xFU) +#define DMA_DCHPRI2_CHPRI_SHIFT (0U) +#define DMA_DCHPRI2_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI2_CHPRI_SHIFT)) & DMA_DCHPRI2_CHPRI_MASK) +#define DMA_DCHPRI2_GRPPRI_MASK (0x30U) +#define DMA_DCHPRI2_GRPPRI_SHIFT (4U) +#define DMA_DCHPRI2_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI2_GRPPRI_SHIFT)) & DMA_DCHPRI2_GRPPRI_MASK) +#define DMA_DCHPRI2_DPA_MASK (0x40U) +#define DMA_DCHPRI2_DPA_SHIFT (6U) +/*! DPA - Disable Preempt Ability. This field resets to 0. + * 0b0..Channel n can suspend a lower priority channel. + * 0b1..Channel n cannot suspend any channel, regardless of channel priority. + */ +#define DMA_DCHPRI2_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI2_DPA_SHIFT)) & DMA_DCHPRI2_DPA_MASK) +#define DMA_DCHPRI2_ECP_MASK (0x80U) +#define DMA_DCHPRI2_ECP_SHIFT (7U) +/*! ECP - Enable Channel Preemption. This field resets to 0. + * 0b0..Channel n cannot be suspended by a higher priority channel's service request. + * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel. + */ +#define DMA_DCHPRI2_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI2_ECP_SHIFT)) & DMA_DCHPRI2_ECP_MASK) +/*! @} */ + +/*! @name DCHPRI1 - Channel n Priority Register */ +/*! @{ */ +#define DMA_DCHPRI1_CHPRI_MASK (0xFU) +#define DMA_DCHPRI1_CHPRI_SHIFT (0U) +#define DMA_DCHPRI1_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI1_CHPRI_SHIFT)) & DMA_DCHPRI1_CHPRI_MASK) +#define DMA_DCHPRI1_GRPPRI_MASK (0x30U) +#define DMA_DCHPRI1_GRPPRI_SHIFT (4U) +#define DMA_DCHPRI1_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI1_GRPPRI_SHIFT)) & DMA_DCHPRI1_GRPPRI_MASK) +#define DMA_DCHPRI1_DPA_MASK (0x40U) +#define DMA_DCHPRI1_DPA_SHIFT (6U) +/*! DPA - Disable Preempt Ability. This field resets to 0. + * 0b0..Channel n can suspend a lower priority channel. + * 0b1..Channel n cannot suspend any channel, regardless of channel priority. + */ +#define DMA_DCHPRI1_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI1_DPA_SHIFT)) & DMA_DCHPRI1_DPA_MASK) +#define DMA_DCHPRI1_ECP_MASK (0x80U) +#define DMA_DCHPRI1_ECP_SHIFT (7U) +/*! ECP - Enable Channel Preemption. This field resets to 0. + * 0b0..Channel n cannot be suspended by a higher priority channel's service request. + * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel. + */ +#define DMA_DCHPRI1_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI1_ECP_SHIFT)) & DMA_DCHPRI1_ECP_MASK) +/*! @} */ + +/*! @name DCHPRI0 - Channel n Priority Register */ +/*! @{ */ +#define DMA_DCHPRI0_CHPRI_MASK (0xFU) +#define DMA_DCHPRI0_CHPRI_SHIFT (0U) +#define DMA_DCHPRI0_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI0_CHPRI_SHIFT)) & DMA_DCHPRI0_CHPRI_MASK) +#define DMA_DCHPRI0_GRPPRI_MASK (0x30U) +#define DMA_DCHPRI0_GRPPRI_SHIFT (4U) +#define DMA_DCHPRI0_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI0_GRPPRI_SHIFT)) & DMA_DCHPRI0_GRPPRI_MASK) +#define DMA_DCHPRI0_DPA_MASK (0x40U) +#define DMA_DCHPRI0_DPA_SHIFT (6U) +/*! DPA - Disable Preempt Ability. This field resets to 0. + * 0b0..Channel n can suspend a lower priority channel. + * 0b1..Channel n cannot suspend any channel, regardless of channel priority. + */ +#define DMA_DCHPRI0_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI0_DPA_SHIFT)) & DMA_DCHPRI0_DPA_MASK) +#define DMA_DCHPRI0_ECP_MASK (0x80U) +#define DMA_DCHPRI0_ECP_SHIFT (7U) +/*! ECP - Enable Channel Preemption. This field resets to 0. + * 0b0..Channel n cannot be suspended by a higher priority channel's service request. + * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel. + */ +#define DMA_DCHPRI0_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI0_ECP_SHIFT)) & DMA_DCHPRI0_ECP_MASK) +/*! @} */ + +/*! @name DCHPRI7 - Channel n Priority Register */ +/*! @{ */ +#define DMA_DCHPRI7_CHPRI_MASK (0xFU) +#define DMA_DCHPRI7_CHPRI_SHIFT (0U) +#define DMA_DCHPRI7_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI7_CHPRI_SHIFT)) & DMA_DCHPRI7_CHPRI_MASK) +#define DMA_DCHPRI7_GRPPRI_MASK (0x30U) +#define DMA_DCHPRI7_GRPPRI_SHIFT (4U) +#define DMA_DCHPRI7_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI7_GRPPRI_SHIFT)) & DMA_DCHPRI7_GRPPRI_MASK) +#define DMA_DCHPRI7_DPA_MASK (0x40U) +#define DMA_DCHPRI7_DPA_SHIFT (6U) +/*! DPA - Disable Preempt Ability. This field resets to 0. + * 0b0..Channel n can suspend a lower priority channel. + * 0b1..Channel n cannot suspend any channel, regardless of channel priority. + */ +#define DMA_DCHPRI7_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI7_DPA_SHIFT)) & DMA_DCHPRI7_DPA_MASK) +#define DMA_DCHPRI7_ECP_MASK (0x80U) +#define DMA_DCHPRI7_ECP_SHIFT (7U) +/*! ECP - Enable Channel Preemption. This field resets to 0. + * 0b0..Channel n cannot be suspended by a higher priority channel's service request. + * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel. + */ +#define DMA_DCHPRI7_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI7_ECP_SHIFT)) & DMA_DCHPRI7_ECP_MASK) +/*! @} */ + +/*! @name DCHPRI6 - Channel n Priority Register */ +/*! @{ */ +#define DMA_DCHPRI6_CHPRI_MASK (0xFU) +#define DMA_DCHPRI6_CHPRI_SHIFT (0U) +#define DMA_DCHPRI6_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI6_CHPRI_SHIFT)) & DMA_DCHPRI6_CHPRI_MASK) +#define DMA_DCHPRI6_GRPPRI_MASK (0x30U) +#define DMA_DCHPRI6_GRPPRI_SHIFT (4U) +#define DMA_DCHPRI6_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI6_GRPPRI_SHIFT)) & DMA_DCHPRI6_GRPPRI_MASK) +#define DMA_DCHPRI6_DPA_MASK (0x40U) +#define DMA_DCHPRI6_DPA_SHIFT (6U) +/*! DPA - Disable Preempt Ability. This field resets to 0. + * 0b0..Channel n can suspend a lower priority channel. + * 0b1..Channel n cannot suspend any channel, regardless of channel priority. + */ +#define DMA_DCHPRI6_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI6_DPA_SHIFT)) & DMA_DCHPRI6_DPA_MASK) +#define DMA_DCHPRI6_ECP_MASK (0x80U) +#define DMA_DCHPRI6_ECP_SHIFT (7U) +/*! ECP - Enable Channel Preemption. This field resets to 0. + * 0b0..Channel n cannot be suspended by a higher priority channel's service request. + * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel. + */ +#define DMA_DCHPRI6_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI6_ECP_SHIFT)) & DMA_DCHPRI6_ECP_MASK) +/*! @} */ + +/*! @name DCHPRI5 - Channel n Priority Register */ +/*! @{ */ +#define DMA_DCHPRI5_CHPRI_MASK (0xFU) +#define DMA_DCHPRI5_CHPRI_SHIFT (0U) +#define DMA_DCHPRI5_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI5_CHPRI_SHIFT)) & DMA_DCHPRI5_CHPRI_MASK) +#define DMA_DCHPRI5_GRPPRI_MASK (0x30U) +#define DMA_DCHPRI5_GRPPRI_SHIFT (4U) +#define DMA_DCHPRI5_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI5_GRPPRI_SHIFT)) & DMA_DCHPRI5_GRPPRI_MASK) +#define DMA_DCHPRI5_DPA_MASK (0x40U) +#define DMA_DCHPRI5_DPA_SHIFT (6U) +/*! DPA - Disable Preempt Ability. This field resets to 0. + * 0b0..Channel n can suspend a lower priority channel. + * 0b1..Channel n cannot suspend any channel, regardless of channel priority. + */ +#define DMA_DCHPRI5_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI5_DPA_SHIFT)) & DMA_DCHPRI5_DPA_MASK) +#define DMA_DCHPRI5_ECP_MASK (0x80U) +#define DMA_DCHPRI5_ECP_SHIFT (7U) +/*! ECP - Enable Channel Preemption. This field resets to 0. + * 0b0..Channel n cannot be suspended by a higher priority channel's service request. + * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel. + */ +#define DMA_DCHPRI5_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI5_ECP_SHIFT)) & DMA_DCHPRI5_ECP_MASK) +/*! @} */ + +/*! @name DCHPRI4 - Channel n Priority Register */ +/*! @{ */ +#define DMA_DCHPRI4_CHPRI_MASK (0xFU) +#define DMA_DCHPRI4_CHPRI_SHIFT (0U) +#define DMA_DCHPRI4_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI4_CHPRI_SHIFT)) & DMA_DCHPRI4_CHPRI_MASK) +#define DMA_DCHPRI4_GRPPRI_MASK (0x30U) +#define DMA_DCHPRI4_GRPPRI_SHIFT (4U) +#define DMA_DCHPRI4_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI4_GRPPRI_SHIFT)) & DMA_DCHPRI4_GRPPRI_MASK) +#define DMA_DCHPRI4_DPA_MASK (0x40U) +#define DMA_DCHPRI4_DPA_SHIFT (6U) +/*! DPA - Disable Preempt Ability. This field resets to 0. + * 0b0..Channel n can suspend a lower priority channel. + * 0b1..Channel n cannot suspend any channel, regardless of channel priority. + */ +#define DMA_DCHPRI4_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI4_DPA_SHIFT)) & DMA_DCHPRI4_DPA_MASK) +#define DMA_DCHPRI4_ECP_MASK (0x80U) +#define DMA_DCHPRI4_ECP_SHIFT (7U) +/*! ECP - Enable Channel Preemption. This field resets to 0. + * 0b0..Channel n cannot be suspended by a higher priority channel's service request. + * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel. + */ +#define DMA_DCHPRI4_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI4_ECP_SHIFT)) & DMA_DCHPRI4_ECP_MASK) +/*! @} */ + +/*! @name DCHPRI11 - Channel n Priority Register */ +/*! @{ */ +#define DMA_DCHPRI11_CHPRI_MASK (0xFU) +#define DMA_DCHPRI11_CHPRI_SHIFT (0U) +#define DMA_DCHPRI11_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI11_CHPRI_SHIFT)) & DMA_DCHPRI11_CHPRI_MASK) +#define DMA_DCHPRI11_GRPPRI_MASK (0x30U) +#define DMA_DCHPRI11_GRPPRI_SHIFT (4U) +#define DMA_DCHPRI11_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI11_GRPPRI_SHIFT)) & DMA_DCHPRI11_GRPPRI_MASK) +#define DMA_DCHPRI11_DPA_MASK (0x40U) +#define DMA_DCHPRI11_DPA_SHIFT (6U) +/*! DPA - Disable Preempt Ability. This field resets to 0. + * 0b0..Channel n can suspend a lower priority channel. + * 0b1..Channel n cannot suspend any channel, regardless of channel priority. + */ +#define DMA_DCHPRI11_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI11_DPA_SHIFT)) & DMA_DCHPRI11_DPA_MASK) +#define DMA_DCHPRI11_ECP_MASK (0x80U) +#define DMA_DCHPRI11_ECP_SHIFT (7U) +/*! ECP - Enable Channel Preemption. This field resets to 0. + * 0b0..Channel n cannot be suspended by a higher priority channel's service request. + * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel. + */ +#define DMA_DCHPRI11_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI11_ECP_SHIFT)) & DMA_DCHPRI11_ECP_MASK) +/*! @} */ + +/*! @name DCHPRI10 - Channel n Priority Register */ +/*! @{ */ +#define DMA_DCHPRI10_CHPRI_MASK (0xFU) +#define DMA_DCHPRI10_CHPRI_SHIFT (0U) +#define DMA_DCHPRI10_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI10_CHPRI_SHIFT)) & DMA_DCHPRI10_CHPRI_MASK) +#define DMA_DCHPRI10_GRPPRI_MASK (0x30U) +#define DMA_DCHPRI10_GRPPRI_SHIFT (4U) +#define DMA_DCHPRI10_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI10_GRPPRI_SHIFT)) & DMA_DCHPRI10_GRPPRI_MASK) +#define DMA_DCHPRI10_DPA_MASK (0x40U) +#define DMA_DCHPRI10_DPA_SHIFT (6U) +/*! DPA - Disable Preempt Ability. This field resets to 0. + * 0b0..Channel n can suspend a lower priority channel. + * 0b1..Channel n cannot suspend any channel, regardless of channel priority. + */ +#define DMA_DCHPRI10_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI10_DPA_SHIFT)) & DMA_DCHPRI10_DPA_MASK) +#define DMA_DCHPRI10_ECP_MASK (0x80U) +#define DMA_DCHPRI10_ECP_SHIFT (7U) +/*! ECP - Enable Channel Preemption. This field resets to 0. + * 0b0..Channel n cannot be suspended by a higher priority channel's service request. + * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel. + */ +#define DMA_DCHPRI10_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI10_ECP_SHIFT)) & DMA_DCHPRI10_ECP_MASK) +/*! @} */ + +/*! @name DCHPRI9 - Channel n Priority Register */ +/*! @{ */ +#define DMA_DCHPRI9_CHPRI_MASK (0xFU) +#define DMA_DCHPRI9_CHPRI_SHIFT (0U) +#define DMA_DCHPRI9_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI9_CHPRI_SHIFT)) & DMA_DCHPRI9_CHPRI_MASK) +#define DMA_DCHPRI9_GRPPRI_MASK (0x30U) +#define DMA_DCHPRI9_GRPPRI_SHIFT (4U) +#define DMA_DCHPRI9_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI9_GRPPRI_SHIFT)) & DMA_DCHPRI9_GRPPRI_MASK) +#define DMA_DCHPRI9_DPA_MASK (0x40U) +#define DMA_DCHPRI9_DPA_SHIFT (6U) +/*! DPA - Disable Preempt Ability. This field resets to 0. + * 0b0..Channel n can suspend a lower priority channel. + * 0b1..Channel n cannot suspend any channel, regardless of channel priority. + */ +#define DMA_DCHPRI9_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI9_DPA_SHIFT)) & DMA_DCHPRI9_DPA_MASK) +#define DMA_DCHPRI9_ECP_MASK (0x80U) +#define DMA_DCHPRI9_ECP_SHIFT (7U) +/*! ECP - Enable Channel Preemption. This field resets to 0. + * 0b0..Channel n cannot be suspended by a higher priority channel's service request. + * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel. + */ +#define DMA_DCHPRI9_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI9_ECP_SHIFT)) & DMA_DCHPRI9_ECP_MASK) +/*! @} */ + +/*! @name DCHPRI8 - Channel n Priority Register */ +/*! @{ */ +#define DMA_DCHPRI8_CHPRI_MASK (0xFU) +#define DMA_DCHPRI8_CHPRI_SHIFT (0U) +#define DMA_DCHPRI8_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI8_CHPRI_SHIFT)) & DMA_DCHPRI8_CHPRI_MASK) +#define DMA_DCHPRI8_GRPPRI_MASK (0x30U) +#define DMA_DCHPRI8_GRPPRI_SHIFT (4U) +#define DMA_DCHPRI8_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI8_GRPPRI_SHIFT)) & DMA_DCHPRI8_GRPPRI_MASK) +#define DMA_DCHPRI8_DPA_MASK (0x40U) +#define DMA_DCHPRI8_DPA_SHIFT (6U) +/*! DPA - Disable Preempt Ability. This field resets to 0. + * 0b0..Channel n can suspend a lower priority channel. + * 0b1..Channel n cannot suspend any channel, regardless of channel priority. + */ +#define DMA_DCHPRI8_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI8_DPA_SHIFT)) & DMA_DCHPRI8_DPA_MASK) +#define DMA_DCHPRI8_ECP_MASK (0x80U) +#define DMA_DCHPRI8_ECP_SHIFT (7U) +/*! ECP - Enable Channel Preemption. This field resets to 0. + * 0b0..Channel n cannot be suspended by a higher priority channel's service request. + * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel. + */ +#define DMA_DCHPRI8_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI8_ECP_SHIFT)) & DMA_DCHPRI8_ECP_MASK) +/*! @} */ + +/*! @name DCHPRI15 - Channel n Priority Register */ +/*! @{ */ +#define DMA_DCHPRI15_CHPRI_MASK (0xFU) +#define DMA_DCHPRI15_CHPRI_SHIFT (0U) +#define DMA_DCHPRI15_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI15_CHPRI_SHIFT)) & DMA_DCHPRI15_CHPRI_MASK) +#define DMA_DCHPRI15_GRPPRI_MASK (0x30U) +#define DMA_DCHPRI15_GRPPRI_SHIFT (4U) +#define DMA_DCHPRI15_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI15_GRPPRI_SHIFT)) & DMA_DCHPRI15_GRPPRI_MASK) +#define DMA_DCHPRI15_DPA_MASK (0x40U) +#define DMA_DCHPRI15_DPA_SHIFT (6U) +/*! DPA - Disable Preempt Ability. This field resets to 0. + * 0b0..Channel n can suspend a lower priority channel. + * 0b1..Channel n cannot suspend any channel, regardless of channel priority. + */ +#define DMA_DCHPRI15_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI15_DPA_SHIFT)) & DMA_DCHPRI15_DPA_MASK) +#define DMA_DCHPRI15_ECP_MASK (0x80U) +#define DMA_DCHPRI15_ECP_SHIFT (7U) +/*! ECP - Enable Channel Preemption. This field resets to 0. + * 0b0..Channel n cannot be suspended by a higher priority channel's service request. + * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel. + */ +#define DMA_DCHPRI15_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI15_ECP_SHIFT)) & DMA_DCHPRI15_ECP_MASK) +/*! @} */ + +/*! @name DCHPRI14 - Channel n Priority Register */ +/*! @{ */ +#define DMA_DCHPRI14_CHPRI_MASK (0xFU) +#define DMA_DCHPRI14_CHPRI_SHIFT (0U) +#define DMA_DCHPRI14_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI14_CHPRI_SHIFT)) & DMA_DCHPRI14_CHPRI_MASK) +#define DMA_DCHPRI14_GRPPRI_MASK (0x30U) +#define DMA_DCHPRI14_GRPPRI_SHIFT (4U) +#define DMA_DCHPRI14_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI14_GRPPRI_SHIFT)) & DMA_DCHPRI14_GRPPRI_MASK) +#define DMA_DCHPRI14_DPA_MASK (0x40U) +#define DMA_DCHPRI14_DPA_SHIFT (6U) +/*! DPA - Disable Preempt Ability. This field resets to 0. + * 0b0..Channel n can suspend a lower priority channel. + * 0b1..Channel n cannot suspend any channel, regardless of channel priority. + */ +#define DMA_DCHPRI14_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI14_DPA_SHIFT)) & DMA_DCHPRI14_DPA_MASK) +#define DMA_DCHPRI14_ECP_MASK (0x80U) +#define DMA_DCHPRI14_ECP_SHIFT (7U) +/*! ECP - Enable Channel Preemption. This field resets to 0. + * 0b0..Channel n cannot be suspended by a higher priority channel's service request. + * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel. + */ +#define DMA_DCHPRI14_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI14_ECP_SHIFT)) & DMA_DCHPRI14_ECP_MASK) +/*! @} */ + +/*! @name DCHPRI13 - Channel n Priority Register */ +/*! @{ */ +#define DMA_DCHPRI13_CHPRI_MASK (0xFU) +#define DMA_DCHPRI13_CHPRI_SHIFT (0U) +#define DMA_DCHPRI13_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI13_CHPRI_SHIFT)) & DMA_DCHPRI13_CHPRI_MASK) +#define DMA_DCHPRI13_GRPPRI_MASK (0x30U) +#define DMA_DCHPRI13_GRPPRI_SHIFT (4U) +#define DMA_DCHPRI13_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI13_GRPPRI_SHIFT)) & DMA_DCHPRI13_GRPPRI_MASK) +#define DMA_DCHPRI13_DPA_MASK (0x40U) +#define DMA_DCHPRI13_DPA_SHIFT (6U) +/*! DPA - Disable Preempt Ability. This field resets to 0. + * 0b0..Channel n can suspend a lower priority channel. + * 0b1..Channel n cannot suspend any channel, regardless of channel priority. + */ +#define DMA_DCHPRI13_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI13_DPA_SHIFT)) & DMA_DCHPRI13_DPA_MASK) +#define DMA_DCHPRI13_ECP_MASK (0x80U) +#define DMA_DCHPRI13_ECP_SHIFT (7U) +/*! ECP - Enable Channel Preemption. This field resets to 0. + * 0b0..Channel n cannot be suspended by a higher priority channel's service request. + * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel. + */ +#define DMA_DCHPRI13_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI13_ECP_SHIFT)) & DMA_DCHPRI13_ECP_MASK) +/*! @} */ + +/*! @name DCHPRI12 - Channel n Priority Register */ +/*! @{ */ +#define DMA_DCHPRI12_CHPRI_MASK (0xFU) +#define DMA_DCHPRI12_CHPRI_SHIFT (0U) +#define DMA_DCHPRI12_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI12_CHPRI_SHIFT)) & DMA_DCHPRI12_CHPRI_MASK) +#define DMA_DCHPRI12_GRPPRI_MASK (0x30U) +#define DMA_DCHPRI12_GRPPRI_SHIFT (4U) +#define DMA_DCHPRI12_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI12_GRPPRI_SHIFT)) & DMA_DCHPRI12_GRPPRI_MASK) +#define DMA_DCHPRI12_DPA_MASK (0x40U) +#define DMA_DCHPRI12_DPA_SHIFT (6U) +/*! DPA - Disable Preempt Ability. This field resets to 0. + * 0b0..Channel n can suspend a lower priority channel. + * 0b1..Channel n cannot suspend any channel, regardless of channel priority. + */ +#define DMA_DCHPRI12_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI12_DPA_SHIFT)) & DMA_DCHPRI12_DPA_MASK) +#define DMA_DCHPRI12_ECP_MASK (0x80U) +#define DMA_DCHPRI12_ECP_SHIFT (7U) +/*! ECP - Enable Channel Preemption. This field resets to 0. + * 0b0..Channel n cannot be suspended by a higher priority channel's service request. + * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel. + */ +#define DMA_DCHPRI12_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI12_ECP_SHIFT)) & DMA_DCHPRI12_ECP_MASK) +/*! @} */ + +/*! @name DCHPRI19 - Channel n Priority Register */ +/*! @{ */ +#define DMA_DCHPRI19_CHPRI_MASK (0xFU) +#define DMA_DCHPRI19_CHPRI_SHIFT (0U) +#define DMA_DCHPRI19_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI19_CHPRI_SHIFT)) & DMA_DCHPRI19_CHPRI_MASK) +#define DMA_DCHPRI19_GRPPRI_MASK (0x30U) +#define DMA_DCHPRI19_GRPPRI_SHIFT (4U) +#define DMA_DCHPRI19_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI19_GRPPRI_SHIFT)) & DMA_DCHPRI19_GRPPRI_MASK) +#define DMA_DCHPRI19_DPA_MASK (0x40U) +#define DMA_DCHPRI19_DPA_SHIFT (6U) +/*! DPA - Disable Preempt Ability. This field resets to 0. + * 0b0..Channel n can suspend a lower priority channel. + * 0b1..Channel n cannot suspend any channel, regardless of channel priority. + */ +#define DMA_DCHPRI19_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI19_DPA_SHIFT)) & DMA_DCHPRI19_DPA_MASK) +#define DMA_DCHPRI19_ECP_MASK (0x80U) +#define DMA_DCHPRI19_ECP_SHIFT (7U) +/*! ECP - Enable Channel Preemption. This field resets to 0. + * 0b0..Channel n cannot be suspended by a higher priority channel's service request. + * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel. + */ +#define DMA_DCHPRI19_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI19_ECP_SHIFT)) & DMA_DCHPRI19_ECP_MASK) +/*! @} */ + +/*! @name DCHPRI18 - Channel n Priority Register */ +/*! @{ */ +#define DMA_DCHPRI18_CHPRI_MASK (0xFU) +#define DMA_DCHPRI18_CHPRI_SHIFT (0U) +#define DMA_DCHPRI18_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI18_CHPRI_SHIFT)) & DMA_DCHPRI18_CHPRI_MASK) +#define DMA_DCHPRI18_GRPPRI_MASK (0x30U) +#define DMA_DCHPRI18_GRPPRI_SHIFT (4U) +#define DMA_DCHPRI18_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI18_GRPPRI_SHIFT)) & DMA_DCHPRI18_GRPPRI_MASK) +#define DMA_DCHPRI18_DPA_MASK (0x40U) +#define DMA_DCHPRI18_DPA_SHIFT (6U) +/*! DPA - Disable Preempt Ability. This field resets to 0. + * 0b0..Channel n can suspend a lower priority channel. + * 0b1..Channel n cannot suspend any channel, regardless of channel priority. + */ +#define DMA_DCHPRI18_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI18_DPA_SHIFT)) & DMA_DCHPRI18_DPA_MASK) +#define DMA_DCHPRI18_ECP_MASK (0x80U) +#define DMA_DCHPRI18_ECP_SHIFT (7U) +/*! ECP - Enable Channel Preemption. This field resets to 0. + * 0b0..Channel n cannot be suspended by a higher priority channel's service request. + * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel. + */ +#define DMA_DCHPRI18_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI18_ECP_SHIFT)) & DMA_DCHPRI18_ECP_MASK) +/*! @} */ + +/*! @name DCHPRI17 - Channel n Priority Register */ +/*! @{ */ +#define DMA_DCHPRI17_CHPRI_MASK (0xFU) +#define DMA_DCHPRI17_CHPRI_SHIFT (0U) +#define DMA_DCHPRI17_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI17_CHPRI_SHIFT)) & DMA_DCHPRI17_CHPRI_MASK) +#define DMA_DCHPRI17_GRPPRI_MASK (0x30U) +#define DMA_DCHPRI17_GRPPRI_SHIFT (4U) +#define DMA_DCHPRI17_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI17_GRPPRI_SHIFT)) & DMA_DCHPRI17_GRPPRI_MASK) +#define DMA_DCHPRI17_DPA_MASK (0x40U) +#define DMA_DCHPRI17_DPA_SHIFT (6U) +/*! DPA - Disable Preempt Ability. This field resets to 0. + * 0b0..Channel n can suspend a lower priority channel. + * 0b1..Channel n cannot suspend any channel, regardless of channel priority. + */ +#define DMA_DCHPRI17_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI17_DPA_SHIFT)) & DMA_DCHPRI17_DPA_MASK) +#define DMA_DCHPRI17_ECP_MASK (0x80U) +#define DMA_DCHPRI17_ECP_SHIFT (7U) +/*! ECP - Enable Channel Preemption. This field resets to 0. + * 0b0..Channel n cannot be suspended by a higher priority channel's service request. + * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel. + */ +#define DMA_DCHPRI17_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI17_ECP_SHIFT)) & DMA_DCHPRI17_ECP_MASK) +/*! @} */ + +/*! @name DCHPRI16 - Channel n Priority Register */ +/*! @{ */ +#define DMA_DCHPRI16_CHPRI_MASK (0xFU) +#define DMA_DCHPRI16_CHPRI_SHIFT (0U) +#define DMA_DCHPRI16_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI16_CHPRI_SHIFT)) & DMA_DCHPRI16_CHPRI_MASK) +#define DMA_DCHPRI16_GRPPRI_MASK (0x30U) +#define DMA_DCHPRI16_GRPPRI_SHIFT (4U) +#define DMA_DCHPRI16_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI16_GRPPRI_SHIFT)) & DMA_DCHPRI16_GRPPRI_MASK) +#define DMA_DCHPRI16_DPA_MASK (0x40U) +#define DMA_DCHPRI16_DPA_SHIFT (6U) +/*! DPA - Disable Preempt Ability. This field resets to 0. + * 0b0..Channel n can suspend a lower priority channel. + * 0b1..Channel n cannot suspend any channel, regardless of channel priority. + */ +#define DMA_DCHPRI16_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI16_DPA_SHIFT)) & DMA_DCHPRI16_DPA_MASK) +#define DMA_DCHPRI16_ECP_MASK (0x80U) +#define DMA_DCHPRI16_ECP_SHIFT (7U) +/*! ECP - Enable Channel Preemption. This field resets to 0. + * 0b0..Channel n cannot be suspended by a higher priority channel's service request. + * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel. + */ +#define DMA_DCHPRI16_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI16_ECP_SHIFT)) & DMA_DCHPRI16_ECP_MASK) +/*! @} */ + +/*! @name DCHPRI23 - Channel n Priority Register */ +/*! @{ */ +#define DMA_DCHPRI23_CHPRI_MASK (0xFU) +#define DMA_DCHPRI23_CHPRI_SHIFT (0U) +#define DMA_DCHPRI23_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI23_CHPRI_SHIFT)) & DMA_DCHPRI23_CHPRI_MASK) +#define DMA_DCHPRI23_GRPPRI_MASK (0x30U) +#define DMA_DCHPRI23_GRPPRI_SHIFT (4U) +#define DMA_DCHPRI23_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI23_GRPPRI_SHIFT)) & DMA_DCHPRI23_GRPPRI_MASK) +#define DMA_DCHPRI23_DPA_MASK (0x40U) +#define DMA_DCHPRI23_DPA_SHIFT (6U) +/*! DPA - Disable Preempt Ability. This field resets to 0. + * 0b0..Channel n can suspend a lower priority channel. + * 0b1..Channel n cannot suspend any channel, regardless of channel priority. + */ +#define DMA_DCHPRI23_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI23_DPA_SHIFT)) & DMA_DCHPRI23_DPA_MASK) +#define DMA_DCHPRI23_ECP_MASK (0x80U) +#define DMA_DCHPRI23_ECP_SHIFT (7U) +/*! ECP - Enable Channel Preemption. This field resets to 0. + * 0b0..Channel n cannot be suspended by a higher priority channel's service request. + * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel. + */ +#define DMA_DCHPRI23_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI23_ECP_SHIFT)) & DMA_DCHPRI23_ECP_MASK) +/*! @} */ + +/*! @name DCHPRI22 - Channel n Priority Register */ +/*! @{ */ +#define DMA_DCHPRI22_CHPRI_MASK (0xFU) +#define DMA_DCHPRI22_CHPRI_SHIFT (0U) +#define DMA_DCHPRI22_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI22_CHPRI_SHIFT)) & DMA_DCHPRI22_CHPRI_MASK) +#define DMA_DCHPRI22_GRPPRI_MASK (0x30U) +#define DMA_DCHPRI22_GRPPRI_SHIFT (4U) +#define DMA_DCHPRI22_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI22_GRPPRI_SHIFT)) & DMA_DCHPRI22_GRPPRI_MASK) +#define DMA_DCHPRI22_DPA_MASK (0x40U) +#define DMA_DCHPRI22_DPA_SHIFT (6U) +/*! DPA - Disable Preempt Ability. This field resets to 0. + * 0b0..Channel n can suspend a lower priority channel. + * 0b1..Channel n cannot suspend any channel, regardless of channel priority. + */ +#define DMA_DCHPRI22_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI22_DPA_SHIFT)) & DMA_DCHPRI22_DPA_MASK) +#define DMA_DCHPRI22_ECP_MASK (0x80U) +#define DMA_DCHPRI22_ECP_SHIFT (7U) +/*! ECP - Enable Channel Preemption. This field resets to 0. + * 0b0..Channel n cannot be suspended by a higher priority channel's service request. + * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel. + */ +#define DMA_DCHPRI22_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI22_ECP_SHIFT)) & DMA_DCHPRI22_ECP_MASK) +/*! @} */ + +/*! @name DCHPRI21 - Channel n Priority Register */ +/*! @{ */ +#define DMA_DCHPRI21_CHPRI_MASK (0xFU) +#define DMA_DCHPRI21_CHPRI_SHIFT (0U) +#define DMA_DCHPRI21_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI21_CHPRI_SHIFT)) & DMA_DCHPRI21_CHPRI_MASK) +#define DMA_DCHPRI21_GRPPRI_MASK (0x30U) +#define DMA_DCHPRI21_GRPPRI_SHIFT (4U) +#define DMA_DCHPRI21_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI21_GRPPRI_SHIFT)) & DMA_DCHPRI21_GRPPRI_MASK) +#define DMA_DCHPRI21_DPA_MASK (0x40U) +#define DMA_DCHPRI21_DPA_SHIFT (6U) +/*! DPA - Disable Preempt Ability. This field resets to 0. + * 0b0..Channel n can suspend a lower priority channel. + * 0b1..Channel n cannot suspend any channel, regardless of channel priority. + */ +#define DMA_DCHPRI21_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI21_DPA_SHIFT)) & DMA_DCHPRI21_DPA_MASK) +#define DMA_DCHPRI21_ECP_MASK (0x80U) +#define DMA_DCHPRI21_ECP_SHIFT (7U) +/*! ECP - Enable Channel Preemption. This field resets to 0. + * 0b0..Channel n cannot be suspended by a higher priority channel's service request. + * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel. + */ +#define DMA_DCHPRI21_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI21_ECP_SHIFT)) & DMA_DCHPRI21_ECP_MASK) +/*! @} */ + +/*! @name DCHPRI20 - Channel n Priority Register */ +/*! @{ */ +#define DMA_DCHPRI20_CHPRI_MASK (0xFU) +#define DMA_DCHPRI20_CHPRI_SHIFT (0U) +#define DMA_DCHPRI20_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI20_CHPRI_SHIFT)) & DMA_DCHPRI20_CHPRI_MASK) +#define DMA_DCHPRI20_GRPPRI_MASK (0x30U) +#define DMA_DCHPRI20_GRPPRI_SHIFT (4U) +#define DMA_DCHPRI20_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI20_GRPPRI_SHIFT)) & DMA_DCHPRI20_GRPPRI_MASK) +#define DMA_DCHPRI20_DPA_MASK (0x40U) +#define DMA_DCHPRI20_DPA_SHIFT (6U) +/*! DPA - Disable Preempt Ability. This field resets to 0. + * 0b0..Channel n can suspend a lower priority channel. + * 0b1..Channel n cannot suspend any channel, regardless of channel priority. + */ +#define DMA_DCHPRI20_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI20_DPA_SHIFT)) & DMA_DCHPRI20_DPA_MASK) +#define DMA_DCHPRI20_ECP_MASK (0x80U) +#define DMA_DCHPRI20_ECP_SHIFT (7U) +/*! ECP - Enable Channel Preemption. This field resets to 0. + * 0b0..Channel n cannot be suspended by a higher priority channel's service request. + * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel. + */ +#define DMA_DCHPRI20_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI20_ECP_SHIFT)) & DMA_DCHPRI20_ECP_MASK) +/*! @} */ + +/*! @name DCHPRI27 - Channel n Priority Register */ +/*! @{ */ +#define DMA_DCHPRI27_CHPRI_MASK (0xFU) +#define DMA_DCHPRI27_CHPRI_SHIFT (0U) +#define DMA_DCHPRI27_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI27_CHPRI_SHIFT)) & DMA_DCHPRI27_CHPRI_MASK) +#define DMA_DCHPRI27_GRPPRI_MASK (0x30U) +#define DMA_DCHPRI27_GRPPRI_SHIFT (4U) +#define DMA_DCHPRI27_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI27_GRPPRI_SHIFT)) & DMA_DCHPRI27_GRPPRI_MASK) +#define DMA_DCHPRI27_DPA_MASK (0x40U) +#define DMA_DCHPRI27_DPA_SHIFT (6U) +/*! DPA - Disable Preempt Ability. This field resets to 0. + * 0b0..Channel n can suspend a lower priority channel. + * 0b1..Channel n cannot suspend any channel, regardless of channel priority. + */ +#define DMA_DCHPRI27_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI27_DPA_SHIFT)) & DMA_DCHPRI27_DPA_MASK) +#define DMA_DCHPRI27_ECP_MASK (0x80U) +#define DMA_DCHPRI27_ECP_SHIFT (7U) +/*! ECP - Enable Channel Preemption. This field resets to 0. + * 0b0..Channel n cannot be suspended by a higher priority channel's service request. + * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel. + */ +#define DMA_DCHPRI27_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI27_ECP_SHIFT)) & DMA_DCHPRI27_ECP_MASK) +/*! @} */ + +/*! @name DCHPRI26 - Channel n Priority Register */ +/*! @{ */ +#define DMA_DCHPRI26_CHPRI_MASK (0xFU) +#define DMA_DCHPRI26_CHPRI_SHIFT (0U) +#define DMA_DCHPRI26_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI26_CHPRI_SHIFT)) & DMA_DCHPRI26_CHPRI_MASK) +#define DMA_DCHPRI26_GRPPRI_MASK (0x30U) +#define DMA_DCHPRI26_GRPPRI_SHIFT (4U) +#define DMA_DCHPRI26_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI26_GRPPRI_SHIFT)) & DMA_DCHPRI26_GRPPRI_MASK) +#define DMA_DCHPRI26_DPA_MASK (0x40U) +#define DMA_DCHPRI26_DPA_SHIFT (6U) +/*! DPA - Disable Preempt Ability. This field resets to 0. + * 0b0..Channel n can suspend a lower priority channel. + * 0b1..Channel n cannot suspend any channel, regardless of channel priority. + */ +#define DMA_DCHPRI26_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI26_DPA_SHIFT)) & DMA_DCHPRI26_DPA_MASK) +#define DMA_DCHPRI26_ECP_MASK (0x80U) +#define DMA_DCHPRI26_ECP_SHIFT (7U) +/*! ECP - Enable Channel Preemption. This field resets to 0. + * 0b0..Channel n cannot be suspended by a higher priority channel's service request. + * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel. + */ +#define DMA_DCHPRI26_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI26_ECP_SHIFT)) & DMA_DCHPRI26_ECP_MASK) +/*! @} */ + +/*! @name DCHPRI25 - Channel n Priority Register */ +/*! @{ */ +#define DMA_DCHPRI25_CHPRI_MASK (0xFU) +#define DMA_DCHPRI25_CHPRI_SHIFT (0U) +#define DMA_DCHPRI25_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI25_CHPRI_SHIFT)) & DMA_DCHPRI25_CHPRI_MASK) +#define DMA_DCHPRI25_GRPPRI_MASK (0x30U) +#define DMA_DCHPRI25_GRPPRI_SHIFT (4U) +#define DMA_DCHPRI25_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI25_GRPPRI_SHIFT)) & DMA_DCHPRI25_GRPPRI_MASK) +#define DMA_DCHPRI25_DPA_MASK (0x40U) +#define DMA_DCHPRI25_DPA_SHIFT (6U) +/*! DPA - Disable Preempt Ability. This field resets to 0. + * 0b0..Channel n can suspend a lower priority channel. + * 0b1..Channel n cannot suspend any channel, regardless of channel priority. + */ +#define DMA_DCHPRI25_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI25_DPA_SHIFT)) & DMA_DCHPRI25_DPA_MASK) +#define DMA_DCHPRI25_ECP_MASK (0x80U) +#define DMA_DCHPRI25_ECP_SHIFT (7U) +/*! ECP - Enable Channel Preemption. This field resets to 0. + * 0b0..Channel n cannot be suspended by a higher priority channel's service request. + * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel. + */ +#define DMA_DCHPRI25_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI25_ECP_SHIFT)) & DMA_DCHPRI25_ECP_MASK) +/*! @} */ + +/*! @name DCHPRI24 - Channel n Priority Register */ +/*! @{ */ +#define DMA_DCHPRI24_CHPRI_MASK (0xFU) +#define DMA_DCHPRI24_CHPRI_SHIFT (0U) +#define DMA_DCHPRI24_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI24_CHPRI_SHIFT)) & DMA_DCHPRI24_CHPRI_MASK) +#define DMA_DCHPRI24_GRPPRI_MASK (0x30U) +#define DMA_DCHPRI24_GRPPRI_SHIFT (4U) +#define DMA_DCHPRI24_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI24_GRPPRI_SHIFT)) & DMA_DCHPRI24_GRPPRI_MASK) +#define DMA_DCHPRI24_DPA_MASK (0x40U) +#define DMA_DCHPRI24_DPA_SHIFT (6U) +/*! DPA - Disable Preempt Ability. This field resets to 0. + * 0b0..Channel n can suspend a lower priority channel. + * 0b1..Channel n cannot suspend any channel, regardless of channel priority. + */ +#define DMA_DCHPRI24_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI24_DPA_SHIFT)) & DMA_DCHPRI24_DPA_MASK) +#define DMA_DCHPRI24_ECP_MASK (0x80U) +#define DMA_DCHPRI24_ECP_SHIFT (7U) +/*! ECP - Enable Channel Preemption. This field resets to 0. + * 0b0..Channel n cannot be suspended by a higher priority channel's service request. + * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel. + */ +#define DMA_DCHPRI24_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI24_ECP_SHIFT)) & DMA_DCHPRI24_ECP_MASK) +/*! @} */ + +/*! @name DCHPRI31 - Channel n Priority Register */ +/*! @{ */ +#define DMA_DCHPRI31_CHPRI_MASK (0xFU) +#define DMA_DCHPRI31_CHPRI_SHIFT (0U) +#define DMA_DCHPRI31_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI31_CHPRI_SHIFT)) & DMA_DCHPRI31_CHPRI_MASK) +#define DMA_DCHPRI31_GRPPRI_MASK (0x30U) +#define DMA_DCHPRI31_GRPPRI_SHIFT (4U) +#define DMA_DCHPRI31_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI31_GRPPRI_SHIFT)) & DMA_DCHPRI31_GRPPRI_MASK) +#define DMA_DCHPRI31_DPA_MASK (0x40U) +#define DMA_DCHPRI31_DPA_SHIFT (6U) +/*! DPA - Disable Preempt Ability. This field resets to 0. + * 0b0..Channel n can suspend a lower priority channel. + * 0b1..Channel n cannot suspend any channel, regardless of channel priority. + */ +#define DMA_DCHPRI31_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI31_DPA_SHIFT)) & DMA_DCHPRI31_DPA_MASK) +#define DMA_DCHPRI31_ECP_MASK (0x80U) +#define DMA_DCHPRI31_ECP_SHIFT (7U) +/*! ECP - Enable Channel Preemption. This field resets to 0. + * 0b0..Channel n cannot be suspended by a higher priority channel's service request. + * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel. + */ +#define DMA_DCHPRI31_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI31_ECP_SHIFT)) & DMA_DCHPRI31_ECP_MASK) +/*! @} */ + +/*! @name DCHPRI30 - Channel n Priority Register */ +/*! @{ */ +#define DMA_DCHPRI30_CHPRI_MASK (0xFU) +#define DMA_DCHPRI30_CHPRI_SHIFT (0U) +#define DMA_DCHPRI30_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI30_CHPRI_SHIFT)) & DMA_DCHPRI30_CHPRI_MASK) +#define DMA_DCHPRI30_GRPPRI_MASK (0x30U) +#define DMA_DCHPRI30_GRPPRI_SHIFT (4U) +#define DMA_DCHPRI30_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI30_GRPPRI_SHIFT)) & DMA_DCHPRI30_GRPPRI_MASK) +#define DMA_DCHPRI30_DPA_MASK (0x40U) +#define DMA_DCHPRI30_DPA_SHIFT (6U) +/*! DPA - Disable Preempt Ability. This field resets to 0. + * 0b0..Channel n can suspend a lower priority channel. + * 0b1..Channel n cannot suspend any channel, regardless of channel priority. + */ +#define DMA_DCHPRI30_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI30_DPA_SHIFT)) & DMA_DCHPRI30_DPA_MASK) +#define DMA_DCHPRI30_ECP_MASK (0x80U) +#define DMA_DCHPRI30_ECP_SHIFT (7U) +/*! ECP - Enable Channel Preemption. This field resets to 0. + * 0b0..Channel n cannot be suspended by a higher priority channel's service request. + * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel. + */ +#define DMA_DCHPRI30_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI30_ECP_SHIFT)) & DMA_DCHPRI30_ECP_MASK) +/*! @} */ + +/*! @name DCHPRI29 - Channel n Priority Register */ +/*! @{ */ +#define DMA_DCHPRI29_CHPRI_MASK (0xFU) +#define DMA_DCHPRI29_CHPRI_SHIFT (0U) +#define DMA_DCHPRI29_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI29_CHPRI_SHIFT)) & DMA_DCHPRI29_CHPRI_MASK) +#define DMA_DCHPRI29_GRPPRI_MASK (0x30U) +#define DMA_DCHPRI29_GRPPRI_SHIFT (4U) +#define DMA_DCHPRI29_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI29_GRPPRI_SHIFT)) & DMA_DCHPRI29_GRPPRI_MASK) +#define DMA_DCHPRI29_DPA_MASK (0x40U) +#define DMA_DCHPRI29_DPA_SHIFT (6U) +/*! DPA - Disable Preempt Ability. This field resets to 0. + * 0b0..Channel n can suspend a lower priority channel. + * 0b1..Channel n cannot suspend any channel, regardless of channel priority. + */ +#define DMA_DCHPRI29_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI29_DPA_SHIFT)) & DMA_DCHPRI29_DPA_MASK) +#define DMA_DCHPRI29_ECP_MASK (0x80U) +#define DMA_DCHPRI29_ECP_SHIFT (7U) +/*! ECP - Enable Channel Preemption. This field resets to 0. + * 0b0..Channel n cannot be suspended by a higher priority channel's service request. + * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel. + */ +#define DMA_DCHPRI29_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI29_ECP_SHIFT)) & DMA_DCHPRI29_ECP_MASK) +/*! @} */ + +/*! @name DCHPRI28 - Channel n Priority Register */ +/*! @{ */ +#define DMA_DCHPRI28_CHPRI_MASK (0xFU) +#define DMA_DCHPRI28_CHPRI_SHIFT (0U) +#define DMA_DCHPRI28_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI28_CHPRI_SHIFT)) & DMA_DCHPRI28_CHPRI_MASK) +#define DMA_DCHPRI28_GRPPRI_MASK (0x30U) +#define DMA_DCHPRI28_GRPPRI_SHIFT (4U) +#define DMA_DCHPRI28_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI28_GRPPRI_SHIFT)) & DMA_DCHPRI28_GRPPRI_MASK) +#define DMA_DCHPRI28_DPA_MASK (0x40U) +#define DMA_DCHPRI28_DPA_SHIFT (6U) +/*! DPA - Disable Preempt Ability. This field resets to 0. + * 0b0..Channel n can suspend a lower priority channel. + * 0b1..Channel n cannot suspend any channel, regardless of channel priority. + */ +#define DMA_DCHPRI28_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI28_DPA_SHIFT)) & DMA_DCHPRI28_DPA_MASK) +#define DMA_DCHPRI28_ECP_MASK (0x80U) +#define DMA_DCHPRI28_ECP_SHIFT (7U) +/*! ECP - Enable Channel Preemption. This field resets to 0. + * 0b0..Channel n cannot be suspended by a higher priority channel's service request. + * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel. + */ +#define DMA_DCHPRI28_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI28_ECP_SHIFT)) & DMA_DCHPRI28_ECP_MASK) +/*! @} */ + +/*! @name SADDR - TCD Source Address */ +/*! @{ */ +#define DMA_SADDR_SADDR_MASK (0xFFFFFFFFU) +#define DMA_SADDR_SADDR_SHIFT (0U) +#define DMA_SADDR_SADDR(x) (((uint32_t)(((uint32_t)(x)) << DMA_SADDR_SADDR_SHIFT)) & DMA_SADDR_SADDR_MASK) +/*! @} */ + +/* The count of DMA_SADDR */ +#define DMA_SADDR_COUNT (32U) + +/*! @name SOFF - TCD Signed Source Address Offset */ +/*! @{ */ +#define DMA_SOFF_SOFF_MASK (0xFFFFU) +#define DMA_SOFF_SOFF_SHIFT (0U) +#define DMA_SOFF_SOFF(x) (((uint16_t)(((uint16_t)(x)) << DMA_SOFF_SOFF_SHIFT)) & DMA_SOFF_SOFF_MASK) +/*! @} */ + +/* The count of DMA_SOFF */ +#define DMA_SOFF_COUNT (32U) + +/*! @name ATTR - TCD Transfer Attributes */ +/*! @{ */ +#define DMA_ATTR_DSIZE_MASK (0x7U) +#define DMA_ATTR_DSIZE_SHIFT (0U) +#define DMA_ATTR_DSIZE(x) (((uint16_t)(((uint16_t)(x)) << DMA_ATTR_DSIZE_SHIFT)) & DMA_ATTR_DSIZE_MASK) +#define DMA_ATTR_DMOD_MASK (0xF8U) +#define DMA_ATTR_DMOD_SHIFT (3U) +#define DMA_ATTR_DMOD(x) (((uint16_t)(((uint16_t)(x)) << DMA_ATTR_DMOD_SHIFT)) & DMA_ATTR_DMOD_MASK) +#define DMA_ATTR_SSIZE_MASK (0x700U) +#define DMA_ATTR_SSIZE_SHIFT (8U) +/*! SSIZE - Source data transfer size + * 0b000..8-bit + * 0b001..16-bit + * 0b010..32-bit + * 0b011..64-bit + * 0b100..Reserved + * 0b101..32-byte burst (4 beats of 64 bits) + * 0b110..Reserved + * 0b111..Reserved + */ +#define DMA_ATTR_SSIZE(x) (((uint16_t)(((uint16_t)(x)) << DMA_ATTR_SSIZE_SHIFT)) & DMA_ATTR_SSIZE_MASK) +#define DMA_ATTR_SMOD_MASK (0xF800U) +#define DMA_ATTR_SMOD_SHIFT (11U) +/*! SMOD - Source Address Modulo + * 0b00000..Source address modulo feature is disabled + * 0b00001-0b11111..This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + */ +#define DMA_ATTR_SMOD(x) (((uint16_t)(((uint16_t)(x)) << DMA_ATTR_SMOD_SHIFT)) & DMA_ATTR_SMOD_MASK) +/*! @} */ + +/* The count of DMA_ATTR */ +#define DMA_ATTR_COUNT (32U) + +/*! @name NBYTES_MLNO - TCD Minor Byte Count (Minor Loop Mapping Disabled) */ +/*! @{ */ +#define DMA_NBYTES_MLNO_NBYTES_MASK (0xFFFFFFFFU) +#define DMA_NBYTES_MLNO_NBYTES_SHIFT (0U) +#define DMA_NBYTES_MLNO_NBYTES(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLNO_NBYTES_SHIFT)) & DMA_NBYTES_MLNO_NBYTES_MASK) +/*! @} */ + +/* The count of DMA_NBYTES_MLNO */ +#define DMA_NBYTES_MLNO_COUNT (32U) + +/*! @name NBYTES_MLOFFNO - TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled) */ +/*! @{ */ +#define DMA_NBYTES_MLOFFNO_NBYTES_MASK (0x3FFFFFFFU) +#define DMA_NBYTES_MLOFFNO_NBYTES_SHIFT (0U) +#define DMA_NBYTES_MLOFFNO_NBYTES(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFNO_NBYTES_SHIFT)) & DMA_NBYTES_MLOFFNO_NBYTES_MASK) +#define DMA_NBYTES_MLOFFNO_DMLOE_MASK (0x40000000U) +#define DMA_NBYTES_MLOFFNO_DMLOE_SHIFT (30U) +/*! DMLOE - Destination Minor Loop Offset enable + * 0b0..The minor loop offset is not applied to the DADDR + * 0b1..The minor loop offset is applied to the DADDR + */ +#define DMA_NBYTES_MLOFFNO_DMLOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFNO_DMLOE_SHIFT)) & DMA_NBYTES_MLOFFNO_DMLOE_MASK) +#define DMA_NBYTES_MLOFFNO_SMLOE_MASK (0x80000000U) +#define DMA_NBYTES_MLOFFNO_SMLOE_SHIFT (31U) +/*! SMLOE - Source Minor Loop Offset Enable + * 0b0..The minor loop offset is not applied to the SADDR + * 0b1..The minor loop offset is applied to the SADDR + */ +#define DMA_NBYTES_MLOFFNO_SMLOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFNO_SMLOE_SHIFT)) & DMA_NBYTES_MLOFFNO_SMLOE_MASK) +/*! @} */ + +/* The count of DMA_NBYTES_MLOFFNO */ +#define DMA_NBYTES_MLOFFNO_COUNT (32U) + +/*! @name NBYTES_MLOFFYES - TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled) */ +/*! @{ */ +#define DMA_NBYTES_MLOFFYES_NBYTES_MASK (0x3FFU) +#define DMA_NBYTES_MLOFFYES_NBYTES_SHIFT (0U) +#define DMA_NBYTES_MLOFFYES_NBYTES(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFYES_NBYTES_SHIFT)) & DMA_NBYTES_MLOFFYES_NBYTES_MASK) +#define DMA_NBYTES_MLOFFYES_MLOFF_MASK (0x3FFFFC00U) +#define DMA_NBYTES_MLOFFYES_MLOFF_SHIFT (10U) +#define DMA_NBYTES_MLOFFYES_MLOFF(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFYES_MLOFF_SHIFT)) & DMA_NBYTES_MLOFFYES_MLOFF_MASK) +#define DMA_NBYTES_MLOFFYES_DMLOE_MASK (0x40000000U) +#define DMA_NBYTES_MLOFFYES_DMLOE_SHIFT (30U) +/*! DMLOE - Destination Minor Loop Offset enable + * 0b0..The minor loop offset is not applied to the DADDR + * 0b1..The minor loop offset is applied to the DADDR + */ +#define DMA_NBYTES_MLOFFYES_DMLOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFYES_DMLOE_SHIFT)) & DMA_NBYTES_MLOFFYES_DMLOE_MASK) +#define DMA_NBYTES_MLOFFYES_SMLOE_MASK (0x80000000U) +#define DMA_NBYTES_MLOFFYES_SMLOE_SHIFT (31U) +/*! SMLOE - Source Minor Loop Offset Enable + * 0b0..The minor loop offset is not applied to the SADDR + * 0b1..The minor loop offset is applied to the SADDR + */ +#define DMA_NBYTES_MLOFFYES_SMLOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFYES_SMLOE_SHIFT)) & DMA_NBYTES_MLOFFYES_SMLOE_MASK) +/*! @} */ + +/* The count of DMA_NBYTES_MLOFFYES */ +#define DMA_NBYTES_MLOFFYES_COUNT (32U) + +/*! @name SLAST - TCD Last Source Address Adjustment */ +/*! @{ */ +#define DMA_SLAST_SLAST_MASK (0xFFFFFFFFU) +#define DMA_SLAST_SLAST_SHIFT (0U) +#define DMA_SLAST_SLAST(x) (((uint32_t)(((uint32_t)(x)) << DMA_SLAST_SLAST_SHIFT)) & DMA_SLAST_SLAST_MASK) +/*! @} */ + +/* The count of DMA_SLAST */ +#define DMA_SLAST_COUNT (32U) + +/*! @name DADDR - TCD Destination Address */ +/*! @{ */ +#define DMA_DADDR_DADDR_MASK (0xFFFFFFFFU) +#define DMA_DADDR_DADDR_SHIFT (0U) +#define DMA_DADDR_DADDR(x) (((uint32_t)(((uint32_t)(x)) << DMA_DADDR_DADDR_SHIFT)) & DMA_DADDR_DADDR_MASK) +/*! @} */ + +/* The count of DMA_DADDR */ +#define DMA_DADDR_COUNT (32U) + +/*! @name DOFF - TCD Signed Destination Address Offset */ +/*! @{ */ +#define DMA_DOFF_DOFF_MASK (0xFFFFU) +#define DMA_DOFF_DOFF_SHIFT (0U) +#define DMA_DOFF_DOFF(x) (((uint16_t)(((uint16_t)(x)) << DMA_DOFF_DOFF_SHIFT)) & DMA_DOFF_DOFF_MASK) +/*! @} */ + +/* The count of DMA_DOFF */ +#define DMA_DOFF_COUNT (32U) + +/*! @name CITER_ELINKNO - TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled) */ +/*! @{ */ +#define DMA_CITER_ELINKNO_CITER_MASK (0x7FFFU) +#define DMA_CITER_ELINKNO_CITER_SHIFT (0U) +#define DMA_CITER_ELINKNO_CITER(x) (((uint16_t)(((uint16_t)(x)) << DMA_CITER_ELINKNO_CITER_SHIFT)) & DMA_CITER_ELINKNO_CITER_MASK) +#define DMA_CITER_ELINKNO_ELINK_MASK (0x8000U) +#define DMA_CITER_ELINKNO_ELINK_SHIFT (15U) +/*! ELINK - Enable channel-to-channel linking on minor-loop complete + * 0b0..The channel-to-channel linking is disabled + * 0b1..The channel-to-channel linking is enabled + */ +#define DMA_CITER_ELINKNO_ELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_CITER_ELINKNO_ELINK_SHIFT)) & DMA_CITER_ELINKNO_ELINK_MASK) +/*! @} */ + +/* The count of DMA_CITER_ELINKNO */ +#define DMA_CITER_ELINKNO_COUNT (32U) + +/*! @name CITER_ELINKYES - TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled) */ +/*! @{ */ +#define DMA_CITER_ELINKYES_CITER_MASK (0x1FFU) +#define DMA_CITER_ELINKYES_CITER_SHIFT (0U) +#define DMA_CITER_ELINKYES_CITER(x) (((uint16_t)(((uint16_t)(x)) << DMA_CITER_ELINKYES_CITER_SHIFT)) & DMA_CITER_ELINKYES_CITER_MASK) +#define DMA_CITER_ELINKYES_LINKCH_MASK (0x3E00U) +#define DMA_CITER_ELINKYES_LINKCH_SHIFT (9U) +#define DMA_CITER_ELINKYES_LINKCH(x) (((uint16_t)(((uint16_t)(x)) << DMA_CITER_ELINKYES_LINKCH_SHIFT)) & DMA_CITER_ELINKYES_LINKCH_MASK) +#define DMA_CITER_ELINKYES_ELINK_MASK (0x8000U) +#define DMA_CITER_ELINKYES_ELINK_SHIFT (15U) +/*! ELINK - Enable channel-to-channel linking on minor-loop complete + * 0b0..The channel-to-channel linking is disabled + * 0b1..The channel-to-channel linking is enabled + */ +#define DMA_CITER_ELINKYES_ELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_CITER_ELINKYES_ELINK_SHIFT)) & DMA_CITER_ELINKYES_ELINK_MASK) +/*! @} */ + +/* The count of DMA_CITER_ELINKYES */ +#define DMA_CITER_ELINKYES_COUNT (32U) + +/*! @name DLAST_SGA - TCD Last Destination Address Adjustment/Scatter Gather Address */ +/*! @{ */ +#define DMA_DLAST_SGA_DLASTSGA_MASK (0xFFFFFFFFU) +#define DMA_DLAST_SGA_DLASTSGA_SHIFT (0U) +#define DMA_DLAST_SGA_DLASTSGA(x) (((uint32_t)(((uint32_t)(x)) << DMA_DLAST_SGA_DLASTSGA_SHIFT)) & DMA_DLAST_SGA_DLASTSGA_MASK) +/*! @} */ + +/* The count of DMA_DLAST_SGA */ +#define DMA_DLAST_SGA_COUNT (32U) + +/*! @name CSR - TCD Control and Status */ +/*! @{ */ +#define DMA_CSR_START_MASK (0x1U) +#define DMA_CSR_START_SHIFT (0U) +/*! START - Channel Start + * 0b0..The channel is not explicitly started. + * 0b1..The channel is explicitly started via a software initiated service request. + */ +#define DMA_CSR_START(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_START_SHIFT)) & DMA_CSR_START_MASK) +#define DMA_CSR_INTMAJOR_MASK (0x2U) +#define DMA_CSR_INTMAJOR_SHIFT (1U) +/*! INTMAJOR - Enable an interrupt when major iteration count completes. + * 0b0..The end-of-major loop interrupt is disabled. + * 0b1..The end-of-major loop interrupt is enabled. + */ +#define DMA_CSR_INTMAJOR(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_INTMAJOR_SHIFT)) & DMA_CSR_INTMAJOR_MASK) +#define DMA_CSR_INTHALF_MASK (0x4U) +#define DMA_CSR_INTHALF_SHIFT (2U) +/*! INTHALF - Enable an interrupt when major counter is half complete. + * 0b0..The half-point interrupt is disabled. + * 0b1..The half-point interrupt is enabled. + */ +#define DMA_CSR_INTHALF(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_INTHALF_SHIFT)) & DMA_CSR_INTHALF_MASK) +#define DMA_CSR_DREQ_MASK (0x8U) +#define DMA_CSR_DREQ_SHIFT (3U) +/*! DREQ - Disable Request + * 0b0..The channel's ERQ bit is not affected. + * 0b1..The channel's ERQ bit is cleared when the major loop is complete. + */ +#define DMA_CSR_DREQ(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_DREQ_SHIFT)) & DMA_CSR_DREQ_MASK) +#define DMA_CSR_ESG_MASK (0x10U) +#define DMA_CSR_ESG_SHIFT (4U) +/*! ESG - Enable Scatter/Gather Processing + * 0b0..The current channel's TCD is normal format. + * 0b1..The current channel's TCD specifies a scatter gather format. The DLASTSGA field provides a memory pointer to the next TCD to be loaded into this channel after the major loop completes its execution. + */ +#define DMA_CSR_ESG(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_ESG_SHIFT)) & DMA_CSR_ESG_MASK) +#define DMA_CSR_MAJORELINK_MASK (0x20U) +#define DMA_CSR_MAJORELINK_SHIFT (5U) +/*! MAJORELINK - Enable channel-to-channel linking on major loop complete + * 0b0..The channel-to-channel linking is disabled. + * 0b1..The channel-to-channel linking is enabled. + */ +#define DMA_CSR_MAJORELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_MAJORELINK_SHIFT)) & DMA_CSR_MAJORELINK_MASK) +#define DMA_CSR_ACTIVE_MASK (0x40U) +#define DMA_CSR_ACTIVE_SHIFT (6U) +#define DMA_CSR_ACTIVE(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_ACTIVE_SHIFT)) & DMA_CSR_ACTIVE_MASK) +#define DMA_CSR_DONE_MASK (0x80U) +#define DMA_CSR_DONE_SHIFT (7U) +#define DMA_CSR_DONE(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_DONE_SHIFT)) & DMA_CSR_DONE_MASK) +#define DMA_CSR_MAJORLINKCH_MASK (0x1F00U) +#define DMA_CSR_MAJORLINKCH_SHIFT (8U) +#define DMA_CSR_MAJORLINKCH(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_MAJORLINKCH_SHIFT)) & DMA_CSR_MAJORLINKCH_MASK) +#define DMA_CSR_BWC_MASK (0xC000U) +#define DMA_CSR_BWC_SHIFT (14U) +/*! BWC - Bandwidth Control + * 0b00..No eDMA engine stalls. + * 0b01..Reserved + * 0b10..eDMA engine stalls for 4 cycles after each R/W. + * 0b11..eDMA engine stalls for 8 cycles after each R/W. + */ +#define DMA_CSR_BWC(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_BWC_SHIFT)) & DMA_CSR_BWC_MASK) +/*! @} */ + +/* The count of DMA_CSR */ +#define DMA_CSR_COUNT (32U) + +/*! @name BITER_ELINKNO - TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled) */ +/*! @{ */ +#define DMA_BITER_ELINKNO_BITER_MASK (0x7FFFU) +#define DMA_BITER_ELINKNO_BITER_SHIFT (0U) +#define DMA_BITER_ELINKNO_BITER(x) (((uint16_t)(((uint16_t)(x)) << DMA_BITER_ELINKNO_BITER_SHIFT)) & DMA_BITER_ELINKNO_BITER_MASK) +#define DMA_BITER_ELINKNO_ELINK_MASK (0x8000U) +#define DMA_BITER_ELINKNO_ELINK_SHIFT (15U) +/*! ELINK - Enables channel-to-channel linking on minor loop complete + * 0b0..The channel-to-channel linking is disabled + * 0b1..The channel-to-channel linking is enabled + */ +#define DMA_BITER_ELINKNO_ELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_BITER_ELINKNO_ELINK_SHIFT)) & DMA_BITER_ELINKNO_ELINK_MASK) +/*! @} */ + +/* The count of DMA_BITER_ELINKNO */ +#define DMA_BITER_ELINKNO_COUNT (32U) + +/*! @name BITER_ELINKYES - TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled) */ +/*! @{ */ +#define DMA_BITER_ELINKYES_BITER_MASK (0x1FFU) +#define DMA_BITER_ELINKYES_BITER_SHIFT (0U) +#define DMA_BITER_ELINKYES_BITER(x) (((uint16_t)(((uint16_t)(x)) << DMA_BITER_ELINKYES_BITER_SHIFT)) & DMA_BITER_ELINKYES_BITER_MASK) +#define DMA_BITER_ELINKYES_LINKCH_MASK (0x3E00U) +#define DMA_BITER_ELINKYES_LINKCH_SHIFT (9U) +#define DMA_BITER_ELINKYES_LINKCH(x) (((uint16_t)(((uint16_t)(x)) << DMA_BITER_ELINKYES_LINKCH_SHIFT)) & DMA_BITER_ELINKYES_LINKCH_MASK) +#define DMA_BITER_ELINKYES_ELINK_MASK (0x8000U) +#define DMA_BITER_ELINKYES_ELINK_SHIFT (15U) +/*! ELINK - Enables channel-to-channel linking on minor loop complete + * 0b0..The channel-to-channel linking is disabled + * 0b1..The channel-to-channel linking is enabled + */ +#define DMA_BITER_ELINKYES_ELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_BITER_ELINKYES_ELINK_SHIFT)) & DMA_BITER_ELINKYES_ELINK_MASK) +/*! @} */ + +/* The count of DMA_BITER_ELINKYES */ +#define DMA_BITER_ELINKYES_COUNT (32U) + + +/*! + * @} + */ /* end of group DMA_Register_Masks */ + + +/* DMA - Peripheral instance base addresses */ +/** Peripheral DMA0 base address */ +#define DMA0_BASE (0x400E8000u) +/** Peripheral DMA0 base pointer */ +#define DMA0 ((DMA_Type *)DMA0_BASE) +/** Array initializer of DMA peripheral base addresses */ +#define DMA_BASE_ADDRS { DMA0_BASE } +/** Array initializer of DMA peripheral base pointers */ +#define DMA_BASE_PTRS { DMA0 } +/** Interrupt vectors for the DMA peripheral type */ +#define DMA_CHN_IRQS { { DMA0_DMA16_IRQn, DMA1_DMA17_IRQn, DMA2_DMA18_IRQn, DMA3_DMA19_IRQn, DMA4_DMA20_IRQn, DMA5_DMA21_IRQn, DMA6_DMA22_IRQn, DMA7_DMA23_IRQn, DMA8_DMA24_IRQn, DMA9_DMA25_IRQn, DMA10_DMA26_IRQn, DMA11_DMA27_IRQn, DMA12_DMA28_IRQn, DMA13_DMA29_IRQn, DMA14_DMA30_IRQn, DMA15_DMA31_IRQn, DMA0_DMA16_IRQn, DMA1_DMA17_IRQn, DMA2_DMA18_IRQn, DMA3_DMA19_IRQn, DMA4_DMA20_IRQn, DMA5_DMA21_IRQn, DMA6_DMA22_IRQn, DMA7_DMA23_IRQn, DMA8_DMA24_IRQn, DMA9_DMA25_IRQn, DMA10_DMA26_IRQn, DMA11_DMA27_IRQn, DMA12_DMA28_IRQn, DMA13_DMA29_IRQn, DMA14_DMA30_IRQn, DMA15_DMA31_IRQn } } +#define DMA_ERROR_IRQS { DMA_ERROR_IRQn } + +/*! + * @} + */ /* end of group DMA_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- DMAMUX Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup DMAMUX_Peripheral_Access_Layer DMAMUX Peripheral Access Layer + * @{ + */ + +/** DMAMUX - Register Layout Typedef */ +typedef struct { + __IO uint32_t CHCFG[32]; /**< Channel 0 Configuration Register..Channel 31 Configuration Register, array offset: 0x0, array step: 0x4 */ +} DMAMUX_Type; + +/* ---------------------------------------------------------------------------- + -- DMAMUX Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup DMAMUX_Register_Masks DMAMUX Register Masks + * @{ + */ + +/*! @name CHCFG - Channel 0 Configuration Register..Channel 31 Configuration Register */ +/*! @{ */ +#define DMAMUX_CHCFG_SOURCE_MASK (0x7FU) +#define DMAMUX_CHCFG_SOURCE_SHIFT (0U) +#define DMAMUX_CHCFG_SOURCE(x) (((uint32_t)(((uint32_t)(x)) << DMAMUX_CHCFG_SOURCE_SHIFT)) & DMAMUX_CHCFG_SOURCE_MASK) +#define DMAMUX_CHCFG_A_ON_MASK (0x20000000U) +#define DMAMUX_CHCFG_A_ON_SHIFT (29U) +/*! A_ON - DMA Channel Always Enable + * 0b0..DMA Channel Always ON function is disabled + * 0b1..DMA Channel Always ON function is enabled + */ +#define DMAMUX_CHCFG_A_ON(x) (((uint32_t)(((uint32_t)(x)) << DMAMUX_CHCFG_A_ON_SHIFT)) & DMAMUX_CHCFG_A_ON_MASK) +#define DMAMUX_CHCFG_TRIG_MASK (0x40000000U) +#define DMAMUX_CHCFG_TRIG_SHIFT (30U) +/*! TRIG - DMA Channel Trigger Enable + * 0b0..Triggering is disabled. If triggering is disabled and ENBL is set, the DMA Channel will simply route the specified source to the DMA channel. (Normal mode) + * 0b1..Triggering is enabled. If triggering is enabled and ENBL is set, the DMA_CH_MUX is in Periodic Trigger mode. + */ +#define DMAMUX_CHCFG_TRIG(x) (((uint32_t)(((uint32_t)(x)) << DMAMUX_CHCFG_TRIG_SHIFT)) & DMAMUX_CHCFG_TRIG_MASK) +#define DMAMUX_CHCFG_ENBL_MASK (0x80000000U) +#define DMAMUX_CHCFG_ENBL_SHIFT (31U) +/*! ENBL - DMA Mux Channel Enable + * 0b0..DMA Mux channel is disabled + * 0b1..DMA Mux channel is enabled + */ +#define DMAMUX_CHCFG_ENBL(x) (((uint32_t)(((uint32_t)(x)) << DMAMUX_CHCFG_ENBL_SHIFT)) & DMAMUX_CHCFG_ENBL_MASK) +/*! @} */ + +/* The count of DMAMUX_CHCFG */ +#define DMAMUX_CHCFG_COUNT (32U) + + +/*! + * @} + */ /* end of group DMAMUX_Register_Masks */ + + +/* DMAMUX - Peripheral instance base addresses */ +/** Peripheral DMAMUX base address */ +#define DMAMUX_BASE (0x400EC000u) +/** Peripheral DMAMUX base pointer */ +#define DMAMUX ((DMAMUX_Type *)DMAMUX_BASE) +/** Array initializer of DMAMUX peripheral base addresses */ +#define DMAMUX_BASE_ADDRS { DMAMUX_BASE } +/** Array initializer of DMAMUX peripheral base pointers */ +#define DMAMUX_BASE_PTRS { DMAMUX } + +/*! + * @} + */ /* end of group DMAMUX_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- ENC Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup ENC_Peripheral_Access_Layer ENC Peripheral Access Layer + * @{ + */ + +/** ENC - Register Layout Typedef */ +typedef struct { + __IO uint16_t CTRL; /**< Control Register, offset: 0x0 */ + __IO uint16_t FILT; /**< Input Filter Register, offset: 0x2 */ + __IO uint16_t WTR; /**< Watchdog Timeout Register, offset: 0x4 */ + __IO uint16_t POSD; /**< Position Difference Counter Register, offset: 0x6 */ + __I uint16_t POSDH; /**< Position Difference Hold Register, offset: 0x8 */ + __IO uint16_t REV; /**< Revolution Counter Register, offset: 0xA */ + __I uint16_t REVH; /**< Revolution Hold Register, offset: 0xC */ + __IO uint16_t UPOS; /**< Upper Position Counter Register, offset: 0xE */ + __IO uint16_t LPOS; /**< Lower Position Counter Register, offset: 0x10 */ + __I uint16_t UPOSH; /**< Upper Position Hold Register, offset: 0x12 */ + __I uint16_t LPOSH; /**< Lower Position Hold Register, offset: 0x14 */ + __IO uint16_t UINIT; /**< Upper Initialization Register, offset: 0x16 */ + __IO uint16_t LINIT; /**< Lower Initialization Register, offset: 0x18 */ + __I uint16_t IMR; /**< Input Monitor Register, offset: 0x1A */ + __IO uint16_t TST; /**< Test Register, offset: 0x1C */ + __IO uint16_t CTRL2; /**< Control 2 Register, offset: 0x1E */ + __IO uint16_t UMOD; /**< Upper Modulus Register, offset: 0x20 */ + __IO uint16_t LMOD; /**< Lower Modulus Register, offset: 0x22 */ + __IO uint16_t UCOMP; /**< Upper Position Compare Register, offset: 0x24 */ + __IO uint16_t LCOMP; /**< Lower Position Compare Register, offset: 0x26 */ +} ENC_Type; + +/* ---------------------------------------------------------------------------- + -- ENC Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup ENC_Register_Masks ENC Register Masks + * @{ + */ + +/*! @name CTRL - Control Register */ +/*! @{ */ +#define ENC_CTRL_CMPIE_MASK (0x1U) +#define ENC_CTRL_CMPIE_SHIFT (0U) +/*! CMPIE - Compare Interrupt Enable + * 0b0..Compare interrupt is disabled + * 0b1..Compare interrupt is enabled + */ +#define ENC_CTRL_CMPIE(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_CMPIE_SHIFT)) & ENC_CTRL_CMPIE_MASK) +#define ENC_CTRL_CMPIRQ_MASK (0x2U) +#define ENC_CTRL_CMPIRQ_SHIFT (1U) +/*! CMPIRQ - Compare Interrupt Request + * 0b0..No match has occurred + * 0b1..COMP match has occurred + */ +#define ENC_CTRL_CMPIRQ(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_CMPIRQ_SHIFT)) & ENC_CTRL_CMPIRQ_MASK) +#define ENC_CTRL_WDE_MASK (0x4U) +#define ENC_CTRL_WDE_SHIFT (2U) +/*! WDE - Watchdog Enable + * 0b0..Watchdog timer is disabled + * 0b1..Watchdog timer is enabled + */ +#define ENC_CTRL_WDE(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_WDE_SHIFT)) & ENC_CTRL_WDE_MASK) +#define ENC_CTRL_DIE_MASK (0x8U) +#define ENC_CTRL_DIE_SHIFT (3U) +/*! DIE - Watchdog Timeout Interrupt Enable + * 0b0..Watchdog timer interrupt is disabled + * 0b1..Watchdog timer interrupt is enabled + */ +#define ENC_CTRL_DIE(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_DIE_SHIFT)) & ENC_CTRL_DIE_MASK) +#define ENC_CTRL_DIRQ_MASK (0x10U) +#define ENC_CTRL_DIRQ_SHIFT (4U) +/*! DIRQ - Watchdog Timeout Interrupt Request + * 0b0..No interrupt has occurred + * 0b1..Watchdog timeout interrupt has occurred + */ +#define ENC_CTRL_DIRQ(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_DIRQ_SHIFT)) & ENC_CTRL_DIRQ_MASK) +#define ENC_CTRL_XNE_MASK (0x20U) +#define ENC_CTRL_XNE_SHIFT (5U) +/*! XNE - Use Negative Edge of INDEX Pulse + * 0b0..Use positive transition edge of INDEX pulse + * 0b1..Use negative transition edge of INDEX pulse + */ +#define ENC_CTRL_XNE(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_XNE_SHIFT)) & ENC_CTRL_XNE_MASK) +#define ENC_CTRL_XIP_MASK (0x40U) +#define ENC_CTRL_XIP_SHIFT (6U) +/*! XIP - INDEX Triggered Initialization of Position Counters UPOS and LPOS + * 0b0..No action + * 0b1..INDEX pulse initializes the position counter + */ +#define ENC_CTRL_XIP(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_XIP_SHIFT)) & ENC_CTRL_XIP_MASK) +#define ENC_CTRL_XIE_MASK (0x80U) +#define ENC_CTRL_XIE_SHIFT (7U) +/*! XIE - INDEX Pulse Interrupt Enable + * 0b0..INDEX pulse interrupt is disabled + * 0b1..INDEX pulse interrupt is enabled + */ +#define ENC_CTRL_XIE(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_XIE_SHIFT)) & ENC_CTRL_XIE_MASK) +#define ENC_CTRL_XIRQ_MASK (0x100U) +#define ENC_CTRL_XIRQ_SHIFT (8U) +/*! XIRQ - INDEX Pulse Interrupt Request + * 0b0..No interrupt has occurred + * 0b1..INDEX pulse interrupt has occurred + */ +#define ENC_CTRL_XIRQ(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_XIRQ_SHIFT)) & ENC_CTRL_XIRQ_MASK) +#define ENC_CTRL_PH1_MASK (0x200U) +#define ENC_CTRL_PH1_SHIFT (9U) +/*! PH1 - Enable Signal Phase Count Mode + * 0b0..Use standard quadrature decoder where PHASEA and PHASEB represent a two phase quadrature signal. + * 0b1..Bypass the quadrature decoder. A positive transition of the PHASEA input generates a count signal. The PHASEB input and the REV bit control the counter direction. If CTRL[REV] = 0, PHASEB = 0, then count up If CTRL[REV] = 0, PHASEB = 1, then count down If CTRL[REV] = 1, PHASEB = 0, then count down If CTRL[REV] = 1, PHASEB = 1, then count up + */ +#define ENC_CTRL_PH1(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_PH1_SHIFT)) & ENC_CTRL_PH1_MASK) +#define ENC_CTRL_REV_MASK (0x400U) +#define ENC_CTRL_REV_SHIFT (10U) +/*! REV - Enable Reverse Direction Counting + * 0b0..Count normally + * 0b1..Count in the reverse direction + */ +#define ENC_CTRL_REV(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_REV_SHIFT)) & ENC_CTRL_REV_MASK) +#define ENC_CTRL_SWIP_MASK (0x800U) +#define ENC_CTRL_SWIP_SHIFT (11U) +/*! SWIP - Software Triggered Initialization of Position Counters UPOS and LPOS + * 0b0..No action + * 0b1..Initialize position counter + */ +#define ENC_CTRL_SWIP(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_SWIP_SHIFT)) & ENC_CTRL_SWIP_MASK) +#define ENC_CTRL_HNE_MASK (0x1000U) +#define ENC_CTRL_HNE_SHIFT (12U) +/*! HNE - Use Negative Edge of HOME Input + * 0b0..Use positive going edge-to-trigger initialization of position counters UPOS and LPOS + * 0b1..Use negative going edge-to-trigger initialization of position counters UPOS and LPOS + */ +#define ENC_CTRL_HNE(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_HNE_SHIFT)) & ENC_CTRL_HNE_MASK) +#define ENC_CTRL_HIP_MASK (0x2000U) +#define ENC_CTRL_HIP_SHIFT (13U) +/*! HIP - Enable HOME to Initialize Position Counters UPOS and LPOS + * 0b0..No action + * 0b1..HOME signal initializes the position counter + */ +#define ENC_CTRL_HIP(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_HIP_SHIFT)) & ENC_CTRL_HIP_MASK) +#define ENC_CTRL_HIE_MASK (0x4000U) +#define ENC_CTRL_HIE_SHIFT (14U) +/*! HIE - HOME Interrupt Enable + * 0b0..Disable HOME interrupts + * 0b1..Enable HOME interrupts + */ +#define ENC_CTRL_HIE(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_HIE_SHIFT)) & ENC_CTRL_HIE_MASK) +#define ENC_CTRL_HIRQ_MASK (0x8000U) +#define ENC_CTRL_HIRQ_SHIFT (15U) +/*! HIRQ - HOME Signal Transition Interrupt Request + * 0b0..No interrupt + * 0b1..HOME signal transition interrupt request + */ +#define ENC_CTRL_HIRQ(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_HIRQ_SHIFT)) & ENC_CTRL_HIRQ_MASK) +/*! @} */ + +/*! @name FILT - Input Filter Register */ +/*! @{ */ +#define ENC_FILT_FILT_PER_MASK (0xFFU) +#define ENC_FILT_FILT_PER_SHIFT (0U) +#define ENC_FILT_FILT_PER(x) (((uint16_t)(((uint16_t)(x)) << ENC_FILT_FILT_PER_SHIFT)) & ENC_FILT_FILT_PER_MASK) +#define ENC_FILT_FILT_CNT_MASK (0x700U) +#define ENC_FILT_FILT_CNT_SHIFT (8U) +#define ENC_FILT_FILT_CNT(x) (((uint16_t)(((uint16_t)(x)) << ENC_FILT_FILT_CNT_SHIFT)) & ENC_FILT_FILT_CNT_MASK) +/*! @} */ + +/*! @name WTR - Watchdog Timeout Register */ +/*! @{ */ +#define ENC_WTR_WDOG_MASK (0xFFFFU) +#define ENC_WTR_WDOG_SHIFT (0U) +#define ENC_WTR_WDOG(x) (((uint16_t)(((uint16_t)(x)) << ENC_WTR_WDOG_SHIFT)) & ENC_WTR_WDOG_MASK) +/*! @} */ + +/*! @name POSD - Position Difference Counter Register */ +/*! @{ */ +#define ENC_POSD_POSD_MASK (0xFFFFU) +#define ENC_POSD_POSD_SHIFT (0U) +#define ENC_POSD_POSD(x) (((uint16_t)(((uint16_t)(x)) << ENC_POSD_POSD_SHIFT)) & ENC_POSD_POSD_MASK) +/*! @} */ + +/*! @name POSDH - Position Difference Hold Register */ +/*! @{ */ +#define ENC_POSDH_POSDH_MASK (0xFFFFU) +#define ENC_POSDH_POSDH_SHIFT (0U) +#define ENC_POSDH_POSDH(x) (((uint16_t)(((uint16_t)(x)) << ENC_POSDH_POSDH_SHIFT)) & ENC_POSDH_POSDH_MASK) +/*! @} */ + +/*! @name REV - Revolution Counter Register */ +/*! @{ */ +#define ENC_REV_REV_MASK (0xFFFFU) +#define ENC_REV_REV_SHIFT (0U) +#define ENC_REV_REV(x) (((uint16_t)(((uint16_t)(x)) << ENC_REV_REV_SHIFT)) & ENC_REV_REV_MASK) +/*! @} */ + +/*! @name REVH - Revolution Hold Register */ +/*! @{ */ +#define ENC_REVH_REVH_MASK (0xFFFFU) +#define ENC_REVH_REVH_SHIFT (0U) +#define ENC_REVH_REVH(x) (((uint16_t)(((uint16_t)(x)) << ENC_REVH_REVH_SHIFT)) & ENC_REVH_REVH_MASK) +/*! @} */ + +/*! @name UPOS - Upper Position Counter Register */ +/*! @{ */ +#define ENC_UPOS_POS_MASK (0xFFFFU) +#define ENC_UPOS_POS_SHIFT (0U) +#define ENC_UPOS_POS(x) (((uint16_t)(((uint16_t)(x)) << ENC_UPOS_POS_SHIFT)) & ENC_UPOS_POS_MASK) +/*! @} */ + +/*! @name LPOS - Lower Position Counter Register */ +/*! @{ */ +#define ENC_LPOS_POS_MASK (0xFFFFU) +#define ENC_LPOS_POS_SHIFT (0U) +#define ENC_LPOS_POS(x) (((uint16_t)(((uint16_t)(x)) << ENC_LPOS_POS_SHIFT)) & ENC_LPOS_POS_MASK) +/*! @} */ + +/*! @name UPOSH - Upper Position Hold Register */ +/*! @{ */ +#define ENC_UPOSH_POSH_MASK (0xFFFFU) +#define ENC_UPOSH_POSH_SHIFT (0U) +#define ENC_UPOSH_POSH(x) (((uint16_t)(((uint16_t)(x)) << ENC_UPOSH_POSH_SHIFT)) & ENC_UPOSH_POSH_MASK) +/*! @} */ + +/*! @name LPOSH - Lower Position Hold Register */ +/*! @{ */ +#define ENC_LPOSH_POSH_MASK (0xFFFFU) +#define ENC_LPOSH_POSH_SHIFT (0U) +#define ENC_LPOSH_POSH(x) (((uint16_t)(((uint16_t)(x)) << ENC_LPOSH_POSH_SHIFT)) & ENC_LPOSH_POSH_MASK) +/*! @} */ + +/*! @name UINIT - Upper Initialization Register */ +/*! @{ */ +#define ENC_UINIT_INIT_MASK (0xFFFFU) +#define ENC_UINIT_INIT_SHIFT (0U) +#define ENC_UINIT_INIT(x) (((uint16_t)(((uint16_t)(x)) << ENC_UINIT_INIT_SHIFT)) & ENC_UINIT_INIT_MASK) +/*! @} */ + +/*! @name LINIT - Lower Initialization Register */ +/*! @{ */ +#define ENC_LINIT_INIT_MASK (0xFFFFU) +#define ENC_LINIT_INIT_SHIFT (0U) +#define ENC_LINIT_INIT(x) (((uint16_t)(((uint16_t)(x)) << ENC_LINIT_INIT_SHIFT)) & ENC_LINIT_INIT_MASK) +/*! @} */ + +/*! @name IMR - Input Monitor Register */ +/*! @{ */ +#define ENC_IMR_HOME_MASK (0x1U) +#define ENC_IMR_HOME_SHIFT (0U) +#define ENC_IMR_HOME(x) (((uint16_t)(((uint16_t)(x)) << ENC_IMR_HOME_SHIFT)) & ENC_IMR_HOME_MASK) +#define ENC_IMR_INDEX_MASK (0x2U) +#define ENC_IMR_INDEX_SHIFT (1U) +#define ENC_IMR_INDEX(x) (((uint16_t)(((uint16_t)(x)) << ENC_IMR_INDEX_SHIFT)) & ENC_IMR_INDEX_MASK) +#define ENC_IMR_PHB_MASK (0x4U) +#define ENC_IMR_PHB_SHIFT (2U) +#define ENC_IMR_PHB(x) (((uint16_t)(((uint16_t)(x)) << ENC_IMR_PHB_SHIFT)) & ENC_IMR_PHB_MASK) +#define ENC_IMR_PHA_MASK (0x8U) +#define ENC_IMR_PHA_SHIFT (3U) +#define ENC_IMR_PHA(x) (((uint16_t)(((uint16_t)(x)) << ENC_IMR_PHA_SHIFT)) & ENC_IMR_PHA_MASK) +#define ENC_IMR_FHOM_MASK (0x10U) +#define ENC_IMR_FHOM_SHIFT (4U) +#define ENC_IMR_FHOM(x) (((uint16_t)(((uint16_t)(x)) << ENC_IMR_FHOM_SHIFT)) & ENC_IMR_FHOM_MASK) +#define ENC_IMR_FIND_MASK (0x20U) +#define ENC_IMR_FIND_SHIFT (5U) +#define ENC_IMR_FIND(x) (((uint16_t)(((uint16_t)(x)) << ENC_IMR_FIND_SHIFT)) & ENC_IMR_FIND_MASK) +#define ENC_IMR_FPHB_MASK (0x40U) +#define ENC_IMR_FPHB_SHIFT (6U) +#define ENC_IMR_FPHB(x) (((uint16_t)(((uint16_t)(x)) << ENC_IMR_FPHB_SHIFT)) & ENC_IMR_FPHB_MASK) +#define ENC_IMR_FPHA_MASK (0x80U) +#define ENC_IMR_FPHA_SHIFT (7U) +#define ENC_IMR_FPHA(x) (((uint16_t)(((uint16_t)(x)) << ENC_IMR_FPHA_SHIFT)) & ENC_IMR_FPHA_MASK) +/*! @} */ + +/*! @name TST - Test Register */ +/*! @{ */ +#define ENC_TST_TEST_COUNT_MASK (0xFFU) +#define ENC_TST_TEST_COUNT_SHIFT (0U) +#define ENC_TST_TEST_COUNT(x) (((uint16_t)(((uint16_t)(x)) << ENC_TST_TEST_COUNT_SHIFT)) & ENC_TST_TEST_COUNT_MASK) +#define ENC_TST_TEST_PERIOD_MASK (0x1F00U) +#define ENC_TST_TEST_PERIOD_SHIFT (8U) +#define ENC_TST_TEST_PERIOD(x) (((uint16_t)(((uint16_t)(x)) << ENC_TST_TEST_PERIOD_SHIFT)) & ENC_TST_TEST_PERIOD_MASK) +#define ENC_TST_QDN_MASK (0x2000U) +#define ENC_TST_QDN_SHIFT (13U) +/*! QDN - Quadrature Decoder Negative Signal + * 0b0..Leaves quadrature decoder signal in a positive direction + * 0b1..Generates a negative quadrature decoder signal + */ +#define ENC_TST_QDN(x) (((uint16_t)(((uint16_t)(x)) << ENC_TST_QDN_SHIFT)) & ENC_TST_QDN_MASK) +#define ENC_TST_TCE_MASK (0x4000U) +#define ENC_TST_TCE_SHIFT (14U) +/*! TCE - Test Counter Enable + * 0b0..Test count is not enabled + * 0b1..Test count is enabled + */ +#define ENC_TST_TCE(x) (((uint16_t)(((uint16_t)(x)) << ENC_TST_TCE_SHIFT)) & ENC_TST_TCE_MASK) +#define ENC_TST_TEN_MASK (0x8000U) +#define ENC_TST_TEN_SHIFT (15U) +/*! TEN - Test Mode Enable + * 0b0..Test module is not enabled + * 0b1..Test module is enabled + */ +#define ENC_TST_TEN(x) (((uint16_t)(((uint16_t)(x)) << ENC_TST_TEN_SHIFT)) & ENC_TST_TEN_MASK) +/*! @} */ + +/*! @name CTRL2 - Control 2 Register */ +/*! @{ */ +#define ENC_CTRL2_UPDHLD_MASK (0x1U) +#define ENC_CTRL2_UPDHLD_SHIFT (0U) +/*! UPDHLD - Update Hold Registers + * 0b0..Disable updates of hold registers on rising edge of TRIGGER + * 0b1..Enable updates of hold registers on rising edge of TRIGGER + */ +#define ENC_CTRL2_UPDHLD(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_UPDHLD_SHIFT)) & ENC_CTRL2_UPDHLD_MASK) +#define ENC_CTRL2_UPDPOS_MASK (0x2U) +#define ENC_CTRL2_UPDPOS_SHIFT (1U) +/*! UPDPOS - Update Position Registers + * 0b0..No action for POSD, REV, UPOS and LPOS on rising edge of TRIGGER + * 0b1..Clear POSD, REV, UPOS and LPOS on rising edge of TRIGGER + */ +#define ENC_CTRL2_UPDPOS(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_UPDPOS_SHIFT)) & ENC_CTRL2_UPDPOS_MASK) +#define ENC_CTRL2_MOD_MASK (0x4U) +#define ENC_CTRL2_MOD_SHIFT (2U) +/*! MOD - Enable Modulo Counting + * 0b0..Disable modulo counting + * 0b1..Enable modulo counting + */ +#define ENC_CTRL2_MOD(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_MOD_SHIFT)) & ENC_CTRL2_MOD_MASK) +#define ENC_CTRL2_DIR_MASK (0x8U) +#define ENC_CTRL2_DIR_SHIFT (3U) +/*! DIR - Count Direction Flag + * 0b0..Last count was in the down direction + * 0b1..Last count was in the up direction + */ +#define ENC_CTRL2_DIR(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_DIR_SHIFT)) & ENC_CTRL2_DIR_MASK) +#define ENC_CTRL2_RUIE_MASK (0x10U) +#define ENC_CTRL2_RUIE_SHIFT (4U) +/*! RUIE - Roll-under Interrupt Enable + * 0b0..Roll-under interrupt is disabled + * 0b1..Roll-under interrupt is enabled + */ +#define ENC_CTRL2_RUIE(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_RUIE_SHIFT)) & ENC_CTRL2_RUIE_MASK) +#define ENC_CTRL2_RUIRQ_MASK (0x20U) +#define ENC_CTRL2_RUIRQ_SHIFT (5U) +/*! RUIRQ - Roll-under Interrupt Request + * 0b0..No roll-under has occurred + * 0b1..Roll-under has occurred + */ +#define ENC_CTRL2_RUIRQ(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_RUIRQ_SHIFT)) & ENC_CTRL2_RUIRQ_MASK) +#define ENC_CTRL2_ROIE_MASK (0x40U) +#define ENC_CTRL2_ROIE_SHIFT (6U) +/*! ROIE - Roll-over Interrupt Enable + * 0b0..Roll-over interrupt is disabled + * 0b1..Roll-over interrupt is enabled + */ +#define ENC_CTRL2_ROIE(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_ROIE_SHIFT)) & ENC_CTRL2_ROIE_MASK) +#define ENC_CTRL2_ROIRQ_MASK (0x80U) +#define ENC_CTRL2_ROIRQ_SHIFT (7U) +/*! ROIRQ - Roll-over Interrupt Request + * 0b0..No roll-over has occurred + * 0b1..Roll-over has occurred + */ +#define ENC_CTRL2_ROIRQ(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_ROIRQ_SHIFT)) & ENC_CTRL2_ROIRQ_MASK) +#define ENC_CTRL2_REVMOD_MASK (0x100U) +#define ENC_CTRL2_REVMOD_SHIFT (8U) +/*! REVMOD - Revolution Counter Modulus Enable + * 0b0..Use INDEX pulse to increment/decrement revolution counter (REV). + * 0b1..Use modulus counting roll-over/under to increment/decrement revolution counter (REV). + */ +#define ENC_CTRL2_REVMOD(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_REVMOD_SHIFT)) & ENC_CTRL2_REVMOD_MASK) +#define ENC_CTRL2_OUTCTL_MASK (0x200U) +#define ENC_CTRL2_OUTCTL_SHIFT (9U) +/*! OUTCTL - Output Control + * 0b0..POSMATCH pulses when a match occurs between the position counters (POS) and the compare value (COMP). + * 0b1..POSMATCH pulses when the UPOS, LPOS, REV, or POSD registers are read. + */ +#define ENC_CTRL2_OUTCTL(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_OUTCTL_SHIFT)) & ENC_CTRL2_OUTCTL_MASK) +#define ENC_CTRL2_SABIE_MASK (0x400U) +#define ENC_CTRL2_SABIE_SHIFT (10U) +/*! SABIE - Simultaneous PHASEA and PHASEB Change Interrupt Enable + * 0b0..Simultaneous PHASEA and PHASEB change interrupt disabled. + * 0b1..Simultaneous PHASEA and PHASEB change interrupt enabled. + */ +#define ENC_CTRL2_SABIE(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_SABIE_SHIFT)) & ENC_CTRL2_SABIE_MASK) +#define ENC_CTRL2_SABIRQ_MASK (0x800U) +#define ENC_CTRL2_SABIRQ_SHIFT (11U) +/*! SABIRQ - Simultaneous PHASEA and PHASEB Change Interrupt Request + * 0b0..No simultaneous change of PHASEA and PHASEB has occurred. + * 0b1..A simultaneous change of PHASEA and PHASEB has occurred. + */ +#define ENC_CTRL2_SABIRQ(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_SABIRQ_SHIFT)) & ENC_CTRL2_SABIRQ_MASK) +/*! @} */ + +/*! @name UMOD - Upper Modulus Register */ +/*! @{ */ +#define ENC_UMOD_MOD_MASK (0xFFFFU) +#define ENC_UMOD_MOD_SHIFT (0U) +#define ENC_UMOD_MOD(x) (((uint16_t)(((uint16_t)(x)) << ENC_UMOD_MOD_SHIFT)) & ENC_UMOD_MOD_MASK) +/*! @} */ + +/*! @name LMOD - Lower Modulus Register */ +/*! @{ */ +#define ENC_LMOD_MOD_MASK (0xFFFFU) +#define ENC_LMOD_MOD_SHIFT (0U) +#define ENC_LMOD_MOD(x) (((uint16_t)(((uint16_t)(x)) << ENC_LMOD_MOD_SHIFT)) & ENC_LMOD_MOD_MASK) +/*! @} */ + +/*! @name UCOMP - Upper Position Compare Register */ +/*! @{ */ +#define ENC_UCOMP_COMP_MASK (0xFFFFU) +#define ENC_UCOMP_COMP_SHIFT (0U) +#define ENC_UCOMP_COMP(x) (((uint16_t)(((uint16_t)(x)) << ENC_UCOMP_COMP_SHIFT)) & ENC_UCOMP_COMP_MASK) +/*! @} */ + +/*! @name LCOMP - Lower Position Compare Register */ +/*! @{ */ +#define ENC_LCOMP_COMP_MASK (0xFFFFU) +#define ENC_LCOMP_COMP_SHIFT (0U) +#define ENC_LCOMP_COMP(x) (((uint16_t)(((uint16_t)(x)) << ENC_LCOMP_COMP_SHIFT)) & ENC_LCOMP_COMP_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group ENC_Register_Masks */ + + +/* ENC - Peripheral instance base addresses */ +/** Peripheral ENC1 base address */ +#define ENC1_BASE (0x403C8000u) +/** Peripheral ENC1 base pointer */ +#define ENC1 ((ENC_Type *)ENC1_BASE) +/** Peripheral ENC2 base address */ +#define ENC2_BASE (0x403CC000u) +/** Peripheral ENC2 base pointer */ +#define ENC2 ((ENC_Type *)ENC2_BASE) +/** Peripheral ENC3 base address */ +#define ENC3_BASE (0x403D0000u) +/** Peripheral ENC3 base pointer */ +#define ENC3 ((ENC_Type *)ENC3_BASE) +/** Peripheral ENC4 base address */ +#define ENC4_BASE (0x403D4000u) +/** Peripheral ENC4 base pointer */ +#define ENC4 ((ENC_Type *)ENC4_BASE) +/** Array initializer of ENC peripheral base addresses */ +#define ENC_BASE_ADDRS { 0u, ENC1_BASE, ENC2_BASE, ENC3_BASE, ENC4_BASE } +/** Array initializer of ENC peripheral base pointers */ +#define ENC_BASE_PTRS { (ENC_Type *)0u, ENC1, ENC2, ENC3, ENC4 } +/** Interrupt vectors for the ENC peripheral type */ +#define ENC_COMPARE_IRQS { NotAvail_IRQn, ENC1_IRQn, ENC2_IRQn, ENC3_IRQn, ENC4_IRQn } +#define ENC_HOME_IRQS { NotAvail_IRQn, ENC1_IRQn, ENC2_IRQn, ENC3_IRQn, ENC4_IRQn } +#define ENC_WDOG_IRQS { NotAvail_IRQn, ENC1_IRQn, ENC2_IRQn, ENC3_IRQn, ENC4_IRQn } +#define ENC_INDEX_IRQS { NotAvail_IRQn, ENC1_IRQn, ENC2_IRQn, ENC3_IRQn, ENC4_IRQn } +#define ENC_INPUT_SWITCH_IRQS { NotAvail_IRQn, ENC1_IRQn, ENC2_IRQn, ENC3_IRQn, ENC4_IRQn } + +/*! + * @} + */ /* end of group ENC_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- ENET Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup ENET_Peripheral_Access_Layer ENET Peripheral Access Layer + * @{ + */ + +/** ENET - Register Layout Typedef */ +typedef struct { + uint8_t RESERVED_0[4]; + __IO uint32_t EIR; /**< Interrupt Event Register, offset: 0x4 */ + __IO uint32_t EIMR; /**< Interrupt Mask Register, offset: 0x8 */ + uint8_t RESERVED_1[4]; + __IO uint32_t RDAR; /**< Receive Descriptor Active Register, offset: 0x10 */ + __IO uint32_t TDAR; /**< Transmit Descriptor Active Register, offset: 0x14 */ + uint8_t RESERVED_2[12]; + __IO uint32_t ECR; /**< Ethernet Control Register, offset: 0x24 */ + uint8_t RESERVED_3[24]; + __IO uint32_t MMFR; /**< MII Management Frame Register, offset: 0x40 */ + __IO uint32_t MSCR; /**< MII Speed Control Register, offset: 0x44 */ + uint8_t RESERVED_4[28]; + __IO uint32_t MIBC; /**< MIB Control Register, offset: 0x64 */ + uint8_t RESERVED_5[28]; + __IO uint32_t RCR; /**< Receive Control Register, offset: 0x84 */ + uint8_t RESERVED_6[60]; + __IO uint32_t TCR; /**< Transmit Control Register, offset: 0xC4 */ + uint8_t RESERVED_7[28]; + __IO uint32_t PALR; /**< Physical Address Lower Register, offset: 0xE4 */ + __IO uint32_t PAUR; /**< Physical Address Upper Register, offset: 0xE8 */ + __IO uint32_t OPD; /**< Opcode/Pause Duration Register, offset: 0xEC */ + __IO uint32_t TXIC; /**< Transmit Interrupt Coalescing Register, offset: 0xF0 */ + uint8_t RESERVED_8[12]; + __IO uint32_t RXIC; /**< Receive Interrupt Coalescing Register, offset: 0x100 */ + uint8_t RESERVED_9[20]; + __IO uint32_t IAUR; /**< Descriptor Individual Upper Address Register, offset: 0x118 */ + __IO uint32_t IALR; /**< Descriptor Individual Lower Address Register, offset: 0x11C */ + __IO uint32_t GAUR; /**< Descriptor Group Upper Address Register, offset: 0x120 */ + __IO uint32_t GALR; /**< Descriptor Group Lower Address Register, offset: 0x124 */ + uint8_t RESERVED_10[28]; + __IO uint32_t TFWR; /**< Transmit FIFO Watermark Register, offset: 0x144 */ + uint8_t RESERVED_11[56]; + __IO uint32_t RDSR; /**< Receive Descriptor Ring Start Register, offset: 0x180 */ + __IO uint32_t TDSR; /**< Transmit Buffer Descriptor Ring Start Register, offset: 0x184 */ + __IO uint32_t MRBR; /**< Maximum Receive Buffer Size Register, offset: 0x188 */ + uint8_t RESERVED_12[4]; + __IO uint32_t RSFL; /**< Receive FIFO Section Full Threshold, offset: 0x190 */ + __IO uint32_t RSEM; /**< Receive FIFO Section Empty Threshold, offset: 0x194 */ + __IO uint32_t RAEM; /**< Receive FIFO Almost Empty Threshold, offset: 0x198 */ + __IO uint32_t RAFL; /**< Receive FIFO Almost Full Threshold, offset: 0x19C */ + __IO uint32_t TSEM; /**< Transmit FIFO Section Empty Threshold, offset: 0x1A0 */ + __IO uint32_t TAEM; /**< Transmit FIFO Almost Empty Threshold, offset: 0x1A4 */ + __IO uint32_t TAFL; /**< Transmit FIFO Almost Full Threshold, offset: 0x1A8 */ + __IO uint32_t TIPG; /**< Transmit Inter-Packet Gap, offset: 0x1AC */ + __IO uint32_t FTRL; /**< Frame Truncation Length, offset: 0x1B0 */ + uint8_t RESERVED_13[12]; + __IO uint32_t TACC; /**< Transmit Accelerator Function Configuration, offset: 0x1C0 */ + __IO uint32_t RACC; /**< Receive Accelerator Function Configuration, offset: 0x1C4 */ + uint8_t RESERVED_14[56]; + uint32_t RMON_T_DROP; /**< Reserved Statistic Register, offset: 0x200 */ + __I uint32_t RMON_T_PACKETS; /**< Tx Packet Count Statistic Register, offset: 0x204 */ + __I uint32_t RMON_T_BC_PKT; /**< Tx Broadcast Packets Statistic Register, offset: 0x208 */ + __I uint32_t RMON_T_MC_PKT; /**< Tx Multicast Packets Statistic Register, offset: 0x20C */ + __I uint32_t RMON_T_CRC_ALIGN; /**< Tx Packets with CRC/Align Error Statistic Register, offset: 0x210 */ + __I uint32_t RMON_T_UNDERSIZE; /**< Tx Packets Less Than Bytes and Good CRC Statistic Register, offset: 0x214 */ + __I uint32_t RMON_T_OVERSIZE; /**< Tx Packets GT MAX_FL bytes and Good CRC Statistic Register, offset: 0x218 */ + __I uint32_t RMON_T_FRAG; /**< Tx Packets Less Than 64 Bytes and Bad CRC Statistic Register, offset: 0x21C */ + __I uint32_t RMON_T_JAB; /**< Tx Packets Greater Than MAX_FL bytes and Bad CRC Statistic Register, offset: 0x220 */ + __I uint32_t RMON_T_COL; /**< Tx Collision Count Statistic Register, offset: 0x224 */ + __I uint32_t RMON_T_P64; /**< Tx 64-Byte Packets Statistic Register, offset: 0x228 */ + __I uint32_t RMON_T_P65TO127; /**< Tx 65- to 127-byte Packets Statistic Register, offset: 0x22C */ + __I uint32_t RMON_T_P128TO255; /**< Tx 128- to 255-byte Packets Statistic Register, offset: 0x230 */ + __I uint32_t RMON_T_P256TO511; /**< Tx 256- to 511-byte Packets Statistic Register, offset: 0x234 */ + __I uint32_t RMON_T_P512TO1023; /**< Tx 512- to 1023-byte Packets Statistic Register, offset: 0x238 */ + __I uint32_t RMON_T_P1024TO2047; /**< Tx 1024- to 2047-byte Packets Statistic Register, offset: 0x23C */ + __I uint32_t RMON_T_P_GTE2048; /**< Tx Packets Greater Than 2048 Bytes Statistic Register, offset: 0x240 */ + __I uint32_t RMON_T_OCTETS; /**< Tx Octets Statistic Register, offset: 0x244 */ + uint32_t IEEE_T_DROP; /**< Reserved Statistic Register, offset: 0x248 */ + __I uint32_t IEEE_T_FRAME_OK; /**< Frames Transmitted OK Statistic Register, offset: 0x24C */ + __I uint32_t IEEE_T_1COL; /**< Frames Transmitted with Single Collision Statistic Register, offset: 0x250 */ + __I uint32_t IEEE_T_MCOL; /**< Frames Transmitted with Multiple Collisions Statistic Register, offset: 0x254 */ + __I uint32_t IEEE_T_DEF; /**< Frames Transmitted after Deferral Delay Statistic Register, offset: 0x258 */ + __I uint32_t IEEE_T_LCOL; /**< Frames Transmitted with Late Collision Statistic Register, offset: 0x25C */ + __I uint32_t IEEE_T_EXCOL; /**< Frames Transmitted with Excessive Collisions Statistic Register, offset: 0x260 */ + __I uint32_t IEEE_T_MACERR; /**< Frames Transmitted with Tx FIFO Underrun Statistic Register, offset: 0x264 */ + __I uint32_t IEEE_T_CSERR; /**< Frames Transmitted with Carrier Sense Error Statistic Register, offset: 0x268 */ + __I uint32_t IEEE_T_SQE; /**< Reserved Statistic Register, offset: 0x26C */ + __I uint32_t IEEE_T_FDXFC; /**< Flow Control Pause Frames Transmitted Statistic Register, offset: 0x270 */ + __I uint32_t IEEE_T_OCTETS_OK; /**< Octet Count for Frames Transmitted w/o Error Statistic Register, offset: 0x274 */ + uint8_t RESERVED_15[12]; + __I uint32_t RMON_R_PACKETS; /**< Rx Packet Count Statistic Register, offset: 0x284 */ + __I uint32_t RMON_R_BC_PKT; /**< Rx Broadcast Packets Statistic Register, offset: 0x288 */ + __I uint32_t RMON_R_MC_PKT; /**< Rx Multicast Packets Statistic Register, offset: 0x28C */ + __I uint32_t RMON_R_CRC_ALIGN; /**< Rx Packets with CRC/Align Error Statistic Register, offset: 0x290 */ + __I uint32_t RMON_R_UNDERSIZE; /**< Rx Packets with Less Than 64 Bytes and Good CRC Statistic Register, offset: 0x294 */ + __I uint32_t RMON_R_OVERSIZE; /**< Rx Packets Greater Than MAX_FL and Good CRC Statistic Register, offset: 0x298 */ + __I uint32_t RMON_R_FRAG; /**< Rx Packets Less Than 64 Bytes and Bad CRC Statistic Register, offset: 0x29C */ + __I uint32_t RMON_R_JAB; /**< Rx Packets Greater Than MAX_FL Bytes and Bad CRC Statistic Register, offset: 0x2A0 */ + uint32_t RMON_R_RESVD_0; /**< Reserved Statistic Register, offset: 0x2A4 */ + __I uint32_t RMON_R_P64; /**< Rx 64-Byte Packets Statistic Register, offset: 0x2A8 */ + __I uint32_t RMON_R_P65TO127; /**< Rx 65- to 127-Byte Packets Statistic Register, offset: 0x2AC */ + __I uint32_t RMON_R_P128TO255; /**< Rx 128- to 255-Byte Packets Statistic Register, offset: 0x2B0 */ + __I uint32_t RMON_R_P256TO511; /**< Rx 256- to 511-Byte Packets Statistic Register, offset: 0x2B4 */ + __I uint32_t RMON_R_P512TO1023; /**< Rx 512- to 1023-Byte Packets Statistic Register, offset: 0x2B8 */ + __I uint32_t RMON_R_P1024TO2047; /**< Rx 1024- to 2047-Byte Packets Statistic Register, offset: 0x2BC */ + __I uint32_t RMON_R_P_GTE2048; /**< Rx Packets Greater than 2048 Bytes Statistic Register, offset: 0x2C0 */ + __I uint32_t RMON_R_OCTETS; /**< Rx Octets Statistic Register, offset: 0x2C4 */ + __I uint32_t IEEE_R_DROP; /**< Frames not Counted Correctly Statistic Register, offset: 0x2C8 */ + __I uint32_t IEEE_R_FRAME_OK; /**< Frames Received OK Statistic Register, offset: 0x2CC */ + __I uint32_t IEEE_R_CRC; /**< Frames Received with CRC Error Statistic Register, offset: 0x2D0 */ + __I uint32_t IEEE_R_ALIGN; /**< Frames Received with Alignment Error Statistic Register, offset: 0x2D4 */ + __I uint32_t IEEE_R_MACERR; /**< Receive FIFO Overflow Count Statistic Register, offset: 0x2D8 */ + __I uint32_t IEEE_R_FDXFC; /**< Flow Control Pause Frames Received Statistic Register, offset: 0x2DC */ + __I uint32_t IEEE_R_OCTETS_OK; /**< Octet Count for Frames Received without Error Statistic Register, offset: 0x2E0 */ + uint8_t RESERVED_16[284]; + __IO uint32_t ATCR; /**< Adjustable Timer Control Register, offset: 0x400 */ + __IO uint32_t ATVR; /**< Timer Value Register, offset: 0x404 */ + __IO uint32_t ATOFF; /**< Timer Offset Register, offset: 0x408 */ + __IO uint32_t ATPER; /**< Timer Period Register, offset: 0x40C */ + __IO uint32_t ATCOR; /**< Timer Correction Register, offset: 0x410 */ + __IO uint32_t ATINC; /**< Time-Stamping Clock Period Register, offset: 0x414 */ + __I uint32_t ATSTMP; /**< Timestamp of Last Transmitted Frame, offset: 0x418 */ + uint8_t RESERVED_17[488]; + __IO uint32_t TGSR; /**< Timer Global Status Register, offset: 0x604 */ + struct { /* offset: 0x608, array step: 0x8 */ + __IO uint32_t TCSR; /**< Timer Control Status Register, array offset: 0x608, array step: 0x8 */ + __IO uint32_t TCCR; /**< Timer Compare Capture Register, array offset: 0x60C, array step: 0x8 */ + } CHANNEL[4]; +} ENET_Type; + +/* ---------------------------------------------------------------------------- + -- ENET Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup ENET_Register_Masks ENET Register Masks + * @{ + */ + +/*! @name EIR - Interrupt Event Register */ +/*! @{ */ +#define ENET_EIR_TS_TIMER_MASK (0x8000U) +#define ENET_EIR_TS_TIMER_SHIFT (15U) +#define ENET_EIR_TS_TIMER(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_TS_TIMER_SHIFT)) & ENET_EIR_TS_TIMER_MASK) +#define ENET_EIR_TS_AVAIL_MASK (0x10000U) +#define ENET_EIR_TS_AVAIL_SHIFT (16U) +#define ENET_EIR_TS_AVAIL(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_TS_AVAIL_SHIFT)) & ENET_EIR_TS_AVAIL_MASK) +#define ENET_EIR_WAKEUP_MASK (0x20000U) +#define ENET_EIR_WAKEUP_SHIFT (17U) +#define ENET_EIR_WAKEUP(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_WAKEUP_SHIFT)) & ENET_EIR_WAKEUP_MASK) +#define ENET_EIR_PLR_MASK (0x40000U) +#define ENET_EIR_PLR_SHIFT (18U) +#define ENET_EIR_PLR(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_PLR_SHIFT)) & ENET_EIR_PLR_MASK) +#define ENET_EIR_UN_MASK (0x80000U) +#define ENET_EIR_UN_SHIFT (19U) +#define ENET_EIR_UN(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_UN_SHIFT)) & ENET_EIR_UN_MASK) +#define ENET_EIR_RL_MASK (0x100000U) +#define ENET_EIR_RL_SHIFT (20U) +#define ENET_EIR_RL(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_RL_SHIFT)) & ENET_EIR_RL_MASK) +#define ENET_EIR_LC_MASK (0x200000U) +#define ENET_EIR_LC_SHIFT (21U) +#define ENET_EIR_LC(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_LC_SHIFT)) & ENET_EIR_LC_MASK) +#define ENET_EIR_EBERR_MASK (0x400000U) +#define ENET_EIR_EBERR_SHIFT (22U) +#define ENET_EIR_EBERR(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_EBERR_SHIFT)) & ENET_EIR_EBERR_MASK) +#define ENET_EIR_MII_MASK (0x800000U) +#define ENET_EIR_MII_SHIFT (23U) +#define ENET_EIR_MII(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_MII_SHIFT)) & ENET_EIR_MII_MASK) +#define ENET_EIR_RXB_MASK (0x1000000U) +#define ENET_EIR_RXB_SHIFT (24U) +#define ENET_EIR_RXB(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_RXB_SHIFT)) & ENET_EIR_RXB_MASK) +#define ENET_EIR_RXF_MASK (0x2000000U) +#define ENET_EIR_RXF_SHIFT (25U) +#define ENET_EIR_RXF(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_RXF_SHIFT)) & ENET_EIR_RXF_MASK) +#define ENET_EIR_TXB_MASK (0x4000000U) +#define ENET_EIR_TXB_SHIFT (26U) +#define ENET_EIR_TXB(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_TXB_SHIFT)) & ENET_EIR_TXB_MASK) +#define ENET_EIR_TXF_MASK (0x8000000U) +#define ENET_EIR_TXF_SHIFT (27U) +#define ENET_EIR_TXF(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_TXF_SHIFT)) & ENET_EIR_TXF_MASK) +#define ENET_EIR_GRA_MASK (0x10000000U) +#define ENET_EIR_GRA_SHIFT (28U) +#define ENET_EIR_GRA(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_GRA_SHIFT)) & ENET_EIR_GRA_MASK) +#define ENET_EIR_BABT_MASK (0x20000000U) +#define ENET_EIR_BABT_SHIFT (29U) +#define ENET_EIR_BABT(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_BABT_SHIFT)) & ENET_EIR_BABT_MASK) +#define ENET_EIR_BABR_MASK (0x40000000U) +#define ENET_EIR_BABR_SHIFT (30U) +#define ENET_EIR_BABR(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_BABR_SHIFT)) & ENET_EIR_BABR_MASK) +/*! @} */ + +/*! @name EIMR - Interrupt Mask Register */ +/*! @{ */ +#define ENET_EIMR_TS_TIMER_MASK (0x8000U) +#define ENET_EIMR_TS_TIMER_SHIFT (15U) +#define ENET_EIMR_TS_TIMER(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_TS_TIMER_SHIFT)) & ENET_EIMR_TS_TIMER_MASK) +#define ENET_EIMR_TS_AVAIL_MASK (0x10000U) +#define ENET_EIMR_TS_AVAIL_SHIFT (16U) +#define ENET_EIMR_TS_AVAIL(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_TS_AVAIL_SHIFT)) & ENET_EIMR_TS_AVAIL_MASK) +#define ENET_EIMR_WAKEUP_MASK (0x20000U) +#define ENET_EIMR_WAKEUP_SHIFT (17U) +#define ENET_EIMR_WAKEUP(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_WAKEUP_SHIFT)) & ENET_EIMR_WAKEUP_MASK) +#define ENET_EIMR_PLR_MASK (0x40000U) +#define ENET_EIMR_PLR_SHIFT (18U) +#define ENET_EIMR_PLR(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_PLR_SHIFT)) & ENET_EIMR_PLR_MASK) +#define ENET_EIMR_UN_MASK (0x80000U) +#define ENET_EIMR_UN_SHIFT (19U) +#define ENET_EIMR_UN(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_UN_SHIFT)) & ENET_EIMR_UN_MASK) +#define ENET_EIMR_RL_MASK (0x100000U) +#define ENET_EIMR_RL_SHIFT (20U) +#define ENET_EIMR_RL(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_RL_SHIFT)) & ENET_EIMR_RL_MASK) +#define ENET_EIMR_LC_MASK (0x200000U) +#define ENET_EIMR_LC_SHIFT (21U) +#define ENET_EIMR_LC(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_LC_SHIFT)) & ENET_EIMR_LC_MASK) +#define ENET_EIMR_EBERR_MASK (0x400000U) +#define ENET_EIMR_EBERR_SHIFT (22U) +#define ENET_EIMR_EBERR(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_EBERR_SHIFT)) & ENET_EIMR_EBERR_MASK) +#define ENET_EIMR_MII_MASK (0x800000U) +#define ENET_EIMR_MII_SHIFT (23U) +#define ENET_EIMR_MII(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_MII_SHIFT)) & ENET_EIMR_MII_MASK) +#define ENET_EIMR_RXB_MASK (0x1000000U) +#define ENET_EIMR_RXB_SHIFT (24U) +#define ENET_EIMR_RXB(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_RXB_SHIFT)) & ENET_EIMR_RXB_MASK) +#define ENET_EIMR_RXF_MASK (0x2000000U) +#define ENET_EIMR_RXF_SHIFT (25U) +#define ENET_EIMR_RXF(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_RXF_SHIFT)) & ENET_EIMR_RXF_MASK) +#define ENET_EIMR_TXB_MASK (0x4000000U) +#define ENET_EIMR_TXB_SHIFT (26U) +/*! TXB - TXB Interrupt Mask + * 0b0..The corresponding interrupt source is masked. + * 0b1..The corresponding interrupt source is not masked. + */ +#define ENET_EIMR_TXB(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_TXB_SHIFT)) & ENET_EIMR_TXB_MASK) +#define ENET_EIMR_TXF_MASK (0x8000000U) +#define ENET_EIMR_TXF_SHIFT (27U) +/*! TXF - TXF Interrupt Mask + * 0b0..The corresponding interrupt source is masked. + * 0b1..The corresponding interrupt source is not masked. + */ +#define ENET_EIMR_TXF(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_TXF_SHIFT)) & ENET_EIMR_TXF_MASK) +#define ENET_EIMR_GRA_MASK (0x10000000U) +#define ENET_EIMR_GRA_SHIFT (28U) +/*! GRA - GRA Interrupt Mask + * 0b0..The corresponding interrupt source is masked. + * 0b1..The corresponding interrupt source is not masked. + */ +#define ENET_EIMR_GRA(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_GRA_SHIFT)) & ENET_EIMR_GRA_MASK) +#define ENET_EIMR_BABT_MASK (0x20000000U) +#define ENET_EIMR_BABT_SHIFT (29U) +/*! BABT - BABT Interrupt Mask + * 0b0..The corresponding interrupt source is masked. + * 0b1..The corresponding interrupt source is not masked. + */ +#define ENET_EIMR_BABT(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_BABT_SHIFT)) & ENET_EIMR_BABT_MASK) +#define ENET_EIMR_BABR_MASK (0x40000000U) +#define ENET_EIMR_BABR_SHIFT (30U) +/*! BABR - BABR Interrupt Mask + * 0b0..The corresponding interrupt source is masked. + * 0b1..The corresponding interrupt source is not masked. + */ +#define ENET_EIMR_BABR(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_BABR_SHIFT)) & ENET_EIMR_BABR_MASK) +/*! @} */ + +/*! @name RDAR - Receive Descriptor Active Register */ +/*! @{ */ +#define ENET_RDAR_RDAR_MASK (0x1000000U) +#define ENET_RDAR_RDAR_SHIFT (24U) +#define ENET_RDAR_RDAR(x) (((uint32_t)(((uint32_t)(x)) << ENET_RDAR_RDAR_SHIFT)) & ENET_RDAR_RDAR_MASK) +/*! @} */ + +/*! @name TDAR - Transmit Descriptor Active Register */ +/*! @{ */ +#define ENET_TDAR_TDAR_MASK (0x1000000U) +#define ENET_TDAR_TDAR_SHIFT (24U) +#define ENET_TDAR_TDAR(x) (((uint32_t)(((uint32_t)(x)) << ENET_TDAR_TDAR_SHIFT)) & ENET_TDAR_TDAR_MASK) +/*! @} */ + +/*! @name ECR - Ethernet Control Register */ +/*! @{ */ +#define ENET_ECR_RESET_MASK (0x1U) +#define ENET_ECR_RESET_SHIFT (0U) +#define ENET_ECR_RESET(x) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_RESET_SHIFT)) & ENET_ECR_RESET_MASK) +#define ENET_ECR_ETHEREN_MASK (0x2U) +#define ENET_ECR_ETHEREN_SHIFT (1U) +/*! ETHEREN - Ethernet Enable + * 0b0..Reception immediately stops and transmission stops after a bad CRC is appended to any currently transmitted frame. + * 0b1..MAC is enabled, and reception and transmission are possible. + */ +#define ENET_ECR_ETHEREN(x) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_ETHEREN_SHIFT)) & ENET_ECR_ETHEREN_MASK) +#define ENET_ECR_MAGICEN_MASK (0x4U) +#define ENET_ECR_MAGICEN_SHIFT (2U) +/*! MAGICEN - Magic Packet Detection Enable + * 0b0..Magic detection logic disabled. + * 0b1..The MAC core detects magic packets and asserts EIR[WAKEUP] when a frame is detected. + */ +#define ENET_ECR_MAGICEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_MAGICEN_SHIFT)) & ENET_ECR_MAGICEN_MASK) +#define ENET_ECR_SLEEP_MASK (0x8U) +#define ENET_ECR_SLEEP_SHIFT (3U) +/*! SLEEP - Sleep Mode Enable + * 0b0..Normal operating mode. + * 0b1..Sleep mode. + */ +#define ENET_ECR_SLEEP(x) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_SLEEP_SHIFT)) & ENET_ECR_SLEEP_MASK) +#define ENET_ECR_EN1588_MASK (0x10U) +#define ENET_ECR_EN1588_SHIFT (4U) +/*! EN1588 - EN1588 Enable + * 0b0..Legacy FEC buffer descriptors and functions enabled. + * 0b1..Enhanced frame time-stamping functions enabled. + */ +#define ENET_ECR_EN1588(x) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_EN1588_SHIFT)) & ENET_ECR_EN1588_MASK) +#define ENET_ECR_DBGEN_MASK (0x40U) +#define ENET_ECR_DBGEN_SHIFT (6U) +/*! DBGEN - Debug Enable + * 0b0..MAC continues operation in debug mode. + * 0b1..MAC enters hardware freeze mode when the processor is in debug mode. + */ +#define ENET_ECR_DBGEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_DBGEN_SHIFT)) & ENET_ECR_DBGEN_MASK) +#define ENET_ECR_DBSWP_MASK (0x100U) +#define ENET_ECR_DBSWP_SHIFT (8U) +/*! DBSWP - Descriptor Byte Swapping Enable + * 0b0..The buffer descriptor bytes are not swapped to support big-endian devices. + * 0b1..The buffer descriptor bytes are swapped to support little-endian devices. + */ +#define ENET_ECR_DBSWP(x) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_DBSWP_SHIFT)) & ENET_ECR_DBSWP_MASK) +/*! @} */ + +/*! @name MMFR - MII Management Frame Register */ +/*! @{ */ +#define ENET_MMFR_DATA_MASK (0xFFFFU) +#define ENET_MMFR_DATA_SHIFT (0U) +#define ENET_MMFR_DATA(x) (((uint32_t)(((uint32_t)(x)) << ENET_MMFR_DATA_SHIFT)) & ENET_MMFR_DATA_MASK) +#define ENET_MMFR_TA_MASK (0x30000U) +#define ENET_MMFR_TA_SHIFT (16U) +#define ENET_MMFR_TA(x) (((uint32_t)(((uint32_t)(x)) << ENET_MMFR_TA_SHIFT)) & ENET_MMFR_TA_MASK) +#define ENET_MMFR_RA_MASK (0x7C0000U) +#define ENET_MMFR_RA_SHIFT (18U) +#define ENET_MMFR_RA(x) (((uint32_t)(((uint32_t)(x)) << ENET_MMFR_RA_SHIFT)) & ENET_MMFR_RA_MASK) +#define ENET_MMFR_PA_MASK (0xF800000U) +#define ENET_MMFR_PA_SHIFT (23U) +#define ENET_MMFR_PA(x) (((uint32_t)(((uint32_t)(x)) << ENET_MMFR_PA_SHIFT)) & ENET_MMFR_PA_MASK) +#define ENET_MMFR_OP_MASK (0x30000000U) +#define ENET_MMFR_OP_SHIFT (28U) +#define ENET_MMFR_OP(x) (((uint32_t)(((uint32_t)(x)) << ENET_MMFR_OP_SHIFT)) & ENET_MMFR_OP_MASK) +#define ENET_MMFR_ST_MASK (0xC0000000U) +#define ENET_MMFR_ST_SHIFT (30U) +#define ENET_MMFR_ST(x) (((uint32_t)(((uint32_t)(x)) << ENET_MMFR_ST_SHIFT)) & ENET_MMFR_ST_MASK) +/*! @} */ + +/*! @name MSCR - MII Speed Control Register */ +/*! @{ */ +#define ENET_MSCR_MII_SPEED_MASK (0x7EU) +#define ENET_MSCR_MII_SPEED_SHIFT (1U) +#define ENET_MSCR_MII_SPEED(x) (((uint32_t)(((uint32_t)(x)) << ENET_MSCR_MII_SPEED_SHIFT)) & ENET_MSCR_MII_SPEED_MASK) +#define ENET_MSCR_DIS_PRE_MASK (0x80U) +#define ENET_MSCR_DIS_PRE_SHIFT (7U) +/*! DIS_PRE - Disable Preamble + * 0b0..Preamble enabled. + * 0b1..Preamble (32 ones) is not prepended to the MII management frame. + */ +#define ENET_MSCR_DIS_PRE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MSCR_DIS_PRE_SHIFT)) & ENET_MSCR_DIS_PRE_MASK) +#define ENET_MSCR_HOLDTIME_MASK (0x700U) +#define ENET_MSCR_HOLDTIME_SHIFT (8U) +/*! HOLDTIME - Hold time On MDIO Output + * 0b000..1 internal module clock cycle + * 0b001..2 internal module clock cycles + * 0b010..3 internal module clock cycles + * 0b111..8 internal module clock cycles + */ +#define ENET_MSCR_HOLDTIME(x) (((uint32_t)(((uint32_t)(x)) << ENET_MSCR_HOLDTIME_SHIFT)) & ENET_MSCR_HOLDTIME_MASK) +/*! @} */ + +/*! @name MIBC - MIB Control Register */ +/*! @{ */ +#define ENET_MIBC_MIB_CLEAR_MASK (0x20000000U) +#define ENET_MIBC_MIB_CLEAR_SHIFT (29U) +/*! MIB_CLEAR - MIB Clear + * 0b0..See note above. + * 0b1..All statistics counters are reset to 0. + */ +#define ENET_MIBC_MIB_CLEAR(x) (((uint32_t)(((uint32_t)(x)) << ENET_MIBC_MIB_CLEAR_SHIFT)) & ENET_MIBC_MIB_CLEAR_MASK) +#define ENET_MIBC_MIB_IDLE_MASK (0x40000000U) +#define ENET_MIBC_MIB_IDLE_SHIFT (30U) +/*! MIB_IDLE - MIB Idle + * 0b0..The MIB block is updating MIB counters. + * 0b1..The MIB block is not currently updating any MIB counters. + */ +#define ENET_MIBC_MIB_IDLE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MIBC_MIB_IDLE_SHIFT)) & ENET_MIBC_MIB_IDLE_MASK) +#define ENET_MIBC_MIB_DIS_MASK (0x80000000U) +#define ENET_MIBC_MIB_DIS_SHIFT (31U) +/*! MIB_DIS - Disable MIB Logic + * 0b0..MIB logic is enabled. + * 0b1..MIB logic is disabled. The MIB logic halts and does not update any MIB counters. + */ +#define ENET_MIBC_MIB_DIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MIBC_MIB_DIS_SHIFT)) & ENET_MIBC_MIB_DIS_MASK) +/*! @} */ + +/*! @name RCR - Receive Control Register */ +/*! @{ */ +#define ENET_RCR_LOOP_MASK (0x1U) +#define ENET_RCR_LOOP_SHIFT (0U) +/*! LOOP - Internal Loopback + * 0b0..Loopback disabled. + * 0b1..Transmitted frames are looped back internal to the device and transmit MII output signals are not asserted. DRT must be cleared. + */ +#define ENET_RCR_LOOP(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_LOOP_SHIFT)) & ENET_RCR_LOOP_MASK) +#define ENET_RCR_DRT_MASK (0x2U) +#define ENET_RCR_DRT_SHIFT (1U) +/*! DRT - Disable Receive On Transmit + * 0b0..Receive path operates independently of transmit (i.e., full-duplex mode). Can also be used to monitor transmit activity in half-duplex mode. + * 0b1..Disable reception of frames while transmitting. (Normally used for half-duplex mode.) + */ +#define ENET_RCR_DRT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_DRT_SHIFT)) & ENET_RCR_DRT_MASK) +#define ENET_RCR_MII_MODE_MASK (0x4U) +#define ENET_RCR_MII_MODE_SHIFT (2U) +/*! MII_MODE - Media Independent Interface Mode + * 0b0..Reserved. + * 0b1..MII or RMII mode, as indicated by the RMII_MODE field. + */ +#define ENET_RCR_MII_MODE(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_MII_MODE_SHIFT)) & ENET_RCR_MII_MODE_MASK) +#define ENET_RCR_PROM_MASK (0x8U) +#define ENET_RCR_PROM_SHIFT (3U) +/*! PROM - Promiscuous Mode + * 0b0..Disabled. + * 0b1..Enabled. + */ +#define ENET_RCR_PROM(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_PROM_SHIFT)) & ENET_RCR_PROM_MASK) +#define ENET_RCR_BC_REJ_MASK (0x10U) +#define ENET_RCR_BC_REJ_SHIFT (4U) +#define ENET_RCR_BC_REJ(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_BC_REJ_SHIFT)) & ENET_RCR_BC_REJ_MASK) +#define ENET_RCR_FCE_MASK (0x20U) +#define ENET_RCR_FCE_SHIFT (5U) +#define ENET_RCR_FCE(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_FCE_SHIFT)) & ENET_RCR_FCE_MASK) +#define ENET_RCR_RMII_MODE_MASK (0x100U) +#define ENET_RCR_RMII_MODE_SHIFT (8U) +/*! RMII_MODE - RMII Mode Enable + * 0b0..MAC configured for MII mode. + * 0b1..MAC configured for RMII operation. + */ +#define ENET_RCR_RMII_MODE(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_RMII_MODE_SHIFT)) & ENET_RCR_RMII_MODE_MASK) +#define ENET_RCR_RMII_10T_MASK (0x200U) +#define ENET_RCR_RMII_10T_SHIFT (9U) +/*! RMII_10T + * 0b0..100-Mbit/s operation. + * 0b1..10-Mbit/s operation. + */ +#define ENET_RCR_RMII_10T(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_RMII_10T_SHIFT)) & ENET_RCR_RMII_10T_MASK) +#define ENET_RCR_PADEN_MASK (0x1000U) +#define ENET_RCR_PADEN_SHIFT (12U) +/*! PADEN - Enable Frame Padding Remove On Receive + * 0b0..No padding is removed on receive by the MAC. + * 0b1..Padding is removed from received frames. + */ +#define ENET_RCR_PADEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_PADEN_SHIFT)) & ENET_RCR_PADEN_MASK) +#define ENET_RCR_PAUFWD_MASK (0x2000U) +#define ENET_RCR_PAUFWD_SHIFT (13U) +/*! PAUFWD - Terminate/Forward Pause Frames + * 0b0..Pause frames are terminated and discarded in the MAC. + * 0b1..Pause frames are forwarded to the user application. + */ +#define ENET_RCR_PAUFWD(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_PAUFWD_SHIFT)) & ENET_RCR_PAUFWD_MASK) +#define ENET_RCR_CRCFWD_MASK (0x4000U) +#define ENET_RCR_CRCFWD_SHIFT (14U) +/*! CRCFWD - Terminate/Forward Received CRC + * 0b0..The CRC field of received frames is transmitted to the user application. + * 0b1..The CRC field is stripped from the frame. + */ +#define ENET_RCR_CRCFWD(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_CRCFWD_SHIFT)) & ENET_RCR_CRCFWD_MASK) +#define ENET_RCR_CFEN_MASK (0x8000U) +#define ENET_RCR_CFEN_SHIFT (15U) +/*! CFEN - MAC Control Frame Enable + * 0b0..MAC control frames with any opcode other than 0x0001 (pause frame) are accepted and forwarded to the client interface. + * 0b1..MAC control frames with any opcode other than 0x0001 (pause frame) are silently discarded. + */ +#define ENET_RCR_CFEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_CFEN_SHIFT)) & ENET_RCR_CFEN_MASK) +#define ENET_RCR_MAX_FL_MASK (0x3FFF0000U) +#define ENET_RCR_MAX_FL_SHIFT (16U) +#define ENET_RCR_MAX_FL(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_MAX_FL_SHIFT)) & ENET_RCR_MAX_FL_MASK) +#define ENET_RCR_NLC_MASK (0x40000000U) +#define ENET_RCR_NLC_SHIFT (30U) +/*! NLC - Payload Length Check Disable + * 0b0..The payload length check is disabled. + * 0b1..The core checks the frame's payload length with the frame length/type field. Errors are indicated in the EIR[PLR] field. + */ +#define ENET_RCR_NLC(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_NLC_SHIFT)) & ENET_RCR_NLC_MASK) +#define ENET_RCR_GRS_MASK (0x80000000U) +#define ENET_RCR_GRS_SHIFT (31U) +#define ENET_RCR_GRS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_GRS_SHIFT)) & ENET_RCR_GRS_MASK) +/*! @} */ + +/*! @name TCR - Transmit Control Register */ +/*! @{ */ +#define ENET_TCR_GTS_MASK (0x1U) +#define ENET_TCR_GTS_SHIFT (0U) +#define ENET_TCR_GTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCR_GTS_SHIFT)) & ENET_TCR_GTS_MASK) +#define ENET_TCR_FDEN_MASK (0x4U) +#define ENET_TCR_FDEN_SHIFT (2U) +#define ENET_TCR_FDEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCR_FDEN_SHIFT)) & ENET_TCR_FDEN_MASK) +#define ENET_TCR_TFC_PAUSE_MASK (0x8U) +#define ENET_TCR_TFC_PAUSE_SHIFT (3U) +/*! TFC_PAUSE - Transmit Frame Control Pause + * 0b0..No PAUSE frame transmitted. + * 0b1..The MAC stops transmission of data frames after the current transmission is complete. + */ +#define ENET_TCR_TFC_PAUSE(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCR_TFC_PAUSE_SHIFT)) & ENET_TCR_TFC_PAUSE_MASK) +#define ENET_TCR_RFC_PAUSE_MASK (0x10U) +#define ENET_TCR_RFC_PAUSE_SHIFT (4U) +#define ENET_TCR_RFC_PAUSE(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCR_RFC_PAUSE_SHIFT)) & ENET_TCR_RFC_PAUSE_MASK) +#define ENET_TCR_ADDSEL_MASK (0xE0U) +#define ENET_TCR_ADDSEL_SHIFT (5U) +/*! ADDSEL - Source MAC Address Select On Transmit + * 0b000..Node MAC address programmed on PADDR1/2 registers. + * 0b100..Reserved. + * 0b101..Reserved. + * 0b110..Reserved. + */ +#define ENET_TCR_ADDSEL(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCR_ADDSEL_SHIFT)) & ENET_TCR_ADDSEL_MASK) +#define ENET_TCR_ADDINS_MASK (0x100U) +#define ENET_TCR_ADDINS_SHIFT (8U) +/*! ADDINS - Set MAC Address On Transmit + * 0b0..The source MAC address is not modified by the MAC. + * 0b1..The MAC overwrites the source MAC address with the programmed MAC address according to ADDSEL. + */ +#define ENET_TCR_ADDINS(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCR_ADDINS_SHIFT)) & ENET_TCR_ADDINS_MASK) +#define ENET_TCR_CRCFWD_MASK (0x200U) +#define ENET_TCR_CRCFWD_SHIFT (9U) +/*! CRCFWD - Forward Frame From Application With CRC + * 0b0..TxBD[TC] controls whether the frame has a CRC from the application. + * 0b1..The transmitter does not append any CRC to transmitted frames, as it is expecting a frame with CRC from the application. + */ +#define ENET_TCR_CRCFWD(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCR_CRCFWD_SHIFT)) & ENET_TCR_CRCFWD_MASK) +/*! @} */ + +/*! @name PALR - Physical Address Lower Register */ +/*! @{ */ +#define ENET_PALR_PADDR1_MASK (0xFFFFFFFFU) +#define ENET_PALR_PADDR1_SHIFT (0U) +#define ENET_PALR_PADDR1(x) (((uint32_t)(((uint32_t)(x)) << ENET_PALR_PADDR1_SHIFT)) & ENET_PALR_PADDR1_MASK) +/*! @} */ + +/*! @name PAUR - Physical Address Upper Register */ +/*! @{ */ +#define ENET_PAUR_TYPE_MASK (0xFFFFU) +#define ENET_PAUR_TYPE_SHIFT (0U) +#define ENET_PAUR_TYPE(x) (((uint32_t)(((uint32_t)(x)) << ENET_PAUR_TYPE_SHIFT)) & ENET_PAUR_TYPE_MASK) +#define ENET_PAUR_PADDR2_MASK (0xFFFF0000U) +#define ENET_PAUR_PADDR2_SHIFT (16U) +#define ENET_PAUR_PADDR2(x) (((uint32_t)(((uint32_t)(x)) << ENET_PAUR_PADDR2_SHIFT)) & ENET_PAUR_PADDR2_MASK) +/*! @} */ + +/*! @name OPD - Opcode/Pause Duration Register */ +/*! @{ */ +#define ENET_OPD_PAUSE_DUR_MASK (0xFFFFU) +#define ENET_OPD_PAUSE_DUR_SHIFT (0U) +#define ENET_OPD_PAUSE_DUR(x) (((uint32_t)(((uint32_t)(x)) << ENET_OPD_PAUSE_DUR_SHIFT)) & ENET_OPD_PAUSE_DUR_MASK) +#define ENET_OPD_OPCODE_MASK (0xFFFF0000U) +#define ENET_OPD_OPCODE_SHIFT (16U) +#define ENET_OPD_OPCODE(x) (((uint32_t)(((uint32_t)(x)) << ENET_OPD_OPCODE_SHIFT)) & ENET_OPD_OPCODE_MASK) +/*! @} */ + +/*! @name TXIC - Transmit Interrupt Coalescing Register */ +/*! @{ */ +#define ENET_TXIC_ICTT_MASK (0xFFFFU) +#define ENET_TXIC_ICTT_SHIFT (0U) +#define ENET_TXIC_ICTT(x) (((uint32_t)(((uint32_t)(x)) << ENET_TXIC_ICTT_SHIFT)) & ENET_TXIC_ICTT_MASK) +#define ENET_TXIC_ICFT_MASK (0xFF00000U) +#define ENET_TXIC_ICFT_SHIFT (20U) +#define ENET_TXIC_ICFT(x) (((uint32_t)(((uint32_t)(x)) << ENET_TXIC_ICFT_SHIFT)) & ENET_TXIC_ICFT_MASK) +#define ENET_TXIC_ICCS_MASK (0x40000000U) +#define ENET_TXIC_ICCS_SHIFT (30U) +/*! ICCS - Interrupt Coalescing Timer Clock Source Select + * 0b0..Use MII/GMII TX clocks. + * 0b1..Use ENET system clock. + */ +#define ENET_TXIC_ICCS(x) (((uint32_t)(((uint32_t)(x)) << ENET_TXIC_ICCS_SHIFT)) & ENET_TXIC_ICCS_MASK) +#define ENET_TXIC_ICEN_MASK (0x80000000U) +#define ENET_TXIC_ICEN_SHIFT (31U) +/*! ICEN - Interrupt Coalescing Enable + * 0b0..Disable Interrupt coalescing. + * 0b1..Enable Interrupt coalescing. + */ +#define ENET_TXIC_ICEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_TXIC_ICEN_SHIFT)) & ENET_TXIC_ICEN_MASK) +/*! @} */ + +/*! @name RXIC - Receive Interrupt Coalescing Register */ +/*! @{ */ +#define ENET_RXIC_ICTT_MASK (0xFFFFU) +#define ENET_RXIC_ICTT_SHIFT (0U) +#define ENET_RXIC_ICTT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RXIC_ICTT_SHIFT)) & ENET_RXIC_ICTT_MASK) +#define ENET_RXIC_ICFT_MASK (0xFF00000U) +#define ENET_RXIC_ICFT_SHIFT (20U) +#define ENET_RXIC_ICFT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RXIC_ICFT_SHIFT)) & ENET_RXIC_ICFT_MASK) +#define ENET_RXIC_ICCS_MASK (0x40000000U) +#define ENET_RXIC_ICCS_SHIFT (30U) +/*! ICCS - Interrupt Coalescing Timer Clock Source Select + * 0b0..Use MII/GMII TX clocks. + * 0b1..Use ENET system clock. + */ +#define ENET_RXIC_ICCS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RXIC_ICCS_SHIFT)) & ENET_RXIC_ICCS_MASK) +#define ENET_RXIC_ICEN_MASK (0x80000000U) +#define ENET_RXIC_ICEN_SHIFT (31U) +/*! ICEN - Interrupt Coalescing Enable + * 0b0..Disable Interrupt coalescing. + * 0b1..Enable Interrupt coalescing. + */ +#define ENET_RXIC_ICEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_RXIC_ICEN_SHIFT)) & ENET_RXIC_ICEN_MASK) +/*! @} */ + +/*! @name IAUR - Descriptor Individual Upper Address Register */ +/*! @{ */ +#define ENET_IAUR_IADDR1_MASK (0xFFFFFFFFU) +#define ENET_IAUR_IADDR1_SHIFT (0U) +#define ENET_IAUR_IADDR1(x) (((uint32_t)(((uint32_t)(x)) << ENET_IAUR_IADDR1_SHIFT)) & ENET_IAUR_IADDR1_MASK) +/*! @} */ + +/*! @name IALR - Descriptor Individual Lower Address Register */ +/*! @{ */ +#define ENET_IALR_IADDR2_MASK (0xFFFFFFFFU) +#define ENET_IALR_IADDR2_SHIFT (0U) +#define ENET_IALR_IADDR2(x) (((uint32_t)(((uint32_t)(x)) << ENET_IALR_IADDR2_SHIFT)) & ENET_IALR_IADDR2_MASK) +/*! @} */ + +/*! @name GAUR - Descriptor Group Upper Address Register */ +/*! @{ */ +#define ENET_GAUR_GADDR1_MASK (0xFFFFFFFFU) +#define ENET_GAUR_GADDR1_SHIFT (0U) +#define ENET_GAUR_GADDR1(x) (((uint32_t)(((uint32_t)(x)) << ENET_GAUR_GADDR1_SHIFT)) & ENET_GAUR_GADDR1_MASK) +/*! @} */ + +/*! @name GALR - Descriptor Group Lower Address Register */ +/*! @{ */ +#define ENET_GALR_GADDR2_MASK (0xFFFFFFFFU) +#define ENET_GALR_GADDR2_SHIFT (0U) +#define ENET_GALR_GADDR2(x) (((uint32_t)(((uint32_t)(x)) << ENET_GALR_GADDR2_SHIFT)) & ENET_GALR_GADDR2_MASK) +/*! @} */ + +/*! @name TFWR - Transmit FIFO Watermark Register */ +/*! @{ */ +#define ENET_TFWR_TFWR_MASK (0x3FU) +#define ENET_TFWR_TFWR_SHIFT (0U) +/*! TFWR - Transmit FIFO Write + * 0b000000..64 bytes written. + * 0b000001..64 bytes written. + * 0b000010..128 bytes written. + * 0b000011..192 bytes written. + * 0b011111..1984 bytes written. + */ +#define ENET_TFWR_TFWR(x) (((uint32_t)(((uint32_t)(x)) << ENET_TFWR_TFWR_SHIFT)) & ENET_TFWR_TFWR_MASK) +#define ENET_TFWR_STRFWD_MASK (0x100U) +#define ENET_TFWR_STRFWD_SHIFT (8U) +/*! STRFWD - Store And Forward Enable + * 0b0..Reset. The transmission start threshold is programmed in TFWR[TFWR]. + * 0b1..Enabled. + */ +#define ENET_TFWR_STRFWD(x) (((uint32_t)(((uint32_t)(x)) << ENET_TFWR_STRFWD_SHIFT)) & ENET_TFWR_STRFWD_MASK) +/*! @} */ + +/*! @name RDSR - Receive Descriptor Ring Start Register */ +/*! @{ */ +#define ENET_RDSR_R_DES_START_MASK (0xFFFFFFF8U) +#define ENET_RDSR_R_DES_START_SHIFT (3U) +#define ENET_RDSR_R_DES_START(x) (((uint32_t)(((uint32_t)(x)) << ENET_RDSR_R_DES_START_SHIFT)) & ENET_RDSR_R_DES_START_MASK) +/*! @} */ + +/*! @name TDSR - Transmit Buffer Descriptor Ring Start Register */ +/*! @{ */ +#define ENET_TDSR_X_DES_START_MASK (0xFFFFFFF8U) +#define ENET_TDSR_X_DES_START_SHIFT (3U) +#define ENET_TDSR_X_DES_START(x) (((uint32_t)(((uint32_t)(x)) << ENET_TDSR_X_DES_START_SHIFT)) & ENET_TDSR_X_DES_START_MASK) +/*! @} */ + +/*! @name MRBR - Maximum Receive Buffer Size Register */ +/*! @{ */ +#define ENET_MRBR_R_BUF_SIZE_MASK (0x3FF0U) +#define ENET_MRBR_R_BUF_SIZE_SHIFT (4U) +#define ENET_MRBR_R_BUF_SIZE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MRBR_R_BUF_SIZE_SHIFT)) & ENET_MRBR_R_BUF_SIZE_MASK) +/*! @} */ + +/*! @name RSFL - Receive FIFO Section Full Threshold */ +/*! @{ */ +#define ENET_RSFL_RX_SECTION_FULL_MASK (0xFFU) +#define ENET_RSFL_RX_SECTION_FULL_SHIFT (0U) +#define ENET_RSFL_RX_SECTION_FULL(x) (((uint32_t)(((uint32_t)(x)) << ENET_RSFL_RX_SECTION_FULL_SHIFT)) & ENET_RSFL_RX_SECTION_FULL_MASK) +/*! @} */ + +/*! @name RSEM - Receive FIFO Section Empty Threshold */ +/*! @{ */ +#define ENET_RSEM_RX_SECTION_EMPTY_MASK (0xFFU) +#define ENET_RSEM_RX_SECTION_EMPTY_SHIFT (0U) +#define ENET_RSEM_RX_SECTION_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << ENET_RSEM_RX_SECTION_EMPTY_SHIFT)) & ENET_RSEM_RX_SECTION_EMPTY_MASK) +#define ENET_RSEM_STAT_SECTION_EMPTY_MASK (0x1F0000U) +#define ENET_RSEM_STAT_SECTION_EMPTY_SHIFT (16U) +#define ENET_RSEM_STAT_SECTION_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << ENET_RSEM_STAT_SECTION_EMPTY_SHIFT)) & ENET_RSEM_STAT_SECTION_EMPTY_MASK) +/*! @} */ + +/*! @name RAEM - Receive FIFO Almost Empty Threshold */ +/*! @{ */ +#define ENET_RAEM_RX_ALMOST_EMPTY_MASK (0xFFU) +#define ENET_RAEM_RX_ALMOST_EMPTY_SHIFT (0U) +#define ENET_RAEM_RX_ALMOST_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << ENET_RAEM_RX_ALMOST_EMPTY_SHIFT)) & ENET_RAEM_RX_ALMOST_EMPTY_MASK) +/*! @} */ + +/*! @name RAFL - Receive FIFO Almost Full Threshold */ +/*! @{ */ +#define ENET_RAFL_RX_ALMOST_FULL_MASK (0xFFU) +#define ENET_RAFL_RX_ALMOST_FULL_SHIFT (0U) +#define ENET_RAFL_RX_ALMOST_FULL(x) (((uint32_t)(((uint32_t)(x)) << ENET_RAFL_RX_ALMOST_FULL_SHIFT)) & ENET_RAFL_RX_ALMOST_FULL_MASK) +/*! @} */ + +/*! @name TSEM - Transmit FIFO Section Empty Threshold */ +/*! @{ */ +#define ENET_TSEM_TX_SECTION_EMPTY_MASK (0xFFU) +#define ENET_TSEM_TX_SECTION_EMPTY_SHIFT (0U) +#define ENET_TSEM_TX_SECTION_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << ENET_TSEM_TX_SECTION_EMPTY_SHIFT)) & ENET_TSEM_TX_SECTION_EMPTY_MASK) +/*! @} */ + +/*! @name TAEM - Transmit FIFO Almost Empty Threshold */ +/*! @{ */ +#define ENET_TAEM_TX_ALMOST_EMPTY_MASK (0xFFU) +#define ENET_TAEM_TX_ALMOST_EMPTY_SHIFT (0U) +#define ENET_TAEM_TX_ALMOST_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << ENET_TAEM_TX_ALMOST_EMPTY_SHIFT)) & ENET_TAEM_TX_ALMOST_EMPTY_MASK) +/*! @} */ + +/*! @name TAFL - Transmit FIFO Almost Full Threshold */ +/*! @{ */ +#define ENET_TAFL_TX_ALMOST_FULL_MASK (0xFFU) +#define ENET_TAFL_TX_ALMOST_FULL_SHIFT (0U) +#define ENET_TAFL_TX_ALMOST_FULL(x) (((uint32_t)(((uint32_t)(x)) << ENET_TAFL_TX_ALMOST_FULL_SHIFT)) & ENET_TAFL_TX_ALMOST_FULL_MASK) +/*! @} */ + +/*! @name TIPG - Transmit Inter-Packet Gap */ +/*! @{ */ +#define ENET_TIPG_IPG_MASK (0x1FU) +#define ENET_TIPG_IPG_SHIFT (0U) +#define ENET_TIPG_IPG(x) (((uint32_t)(((uint32_t)(x)) << ENET_TIPG_IPG_SHIFT)) & ENET_TIPG_IPG_MASK) +/*! @} */ + +/*! @name FTRL - Frame Truncation Length */ +/*! @{ */ +#define ENET_FTRL_TRUNC_FL_MASK (0x3FFFU) +#define ENET_FTRL_TRUNC_FL_SHIFT (0U) +#define ENET_FTRL_TRUNC_FL(x) (((uint32_t)(((uint32_t)(x)) << ENET_FTRL_TRUNC_FL_SHIFT)) & ENET_FTRL_TRUNC_FL_MASK) +/*! @} */ + +/*! @name TACC - Transmit Accelerator Function Configuration */ +/*! @{ */ +#define ENET_TACC_SHIFT16_MASK (0x1U) +#define ENET_TACC_SHIFT16_SHIFT (0U) +/*! SHIFT16 - TX FIFO Shift-16 + * 0b0..Disabled. + * 0b1..Indicates to the transmit data FIFO that the written frames contain two additional octets before the frame data. This means the actual frame begins at bit 16 of the first word written into the FIFO. This function allows putting the frame payload on a 32-bit boundary in memory, as the 14-byte Ethernet header is extended to a 16-byte header. + */ +#define ENET_TACC_SHIFT16(x) (((uint32_t)(((uint32_t)(x)) << ENET_TACC_SHIFT16_SHIFT)) & ENET_TACC_SHIFT16_MASK) +#define ENET_TACC_IPCHK_MASK (0x8U) +#define ENET_TACC_IPCHK_SHIFT (3U) +/*! IPCHK + * 0b0..Checksum is not inserted. + * 0b1..If an IP frame is transmitted, the checksum is inserted automatically. The IP header checksum field must be cleared. If a non-IP frame is transmitted the frame is not modified. + */ +#define ENET_TACC_IPCHK(x) (((uint32_t)(((uint32_t)(x)) << ENET_TACC_IPCHK_SHIFT)) & ENET_TACC_IPCHK_MASK) +#define ENET_TACC_PROCHK_MASK (0x10U) +#define ENET_TACC_PROCHK_SHIFT (4U) +/*! PROCHK + * 0b0..Checksum not inserted. + * 0b1..If an IP frame with a known protocol is transmitted, the checksum is inserted automatically into the frame. The checksum field must be cleared. The other frames are not modified. + */ +#define ENET_TACC_PROCHK(x) (((uint32_t)(((uint32_t)(x)) << ENET_TACC_PROCHK_SHIFT)) & ENET_TACC_PROCHK_MASK) +/*! @} */ + +/*! @name RACC - Receive Accelerator Function Configuration */ +/*! @{ */ +#define ENET_RACC_PADREM_MASK (0x1U) +#define ENET_RACC_PADREM_SHIFT (0U) +/*! PADREM - Enable Padding Removal For Short IP Frames + * 0b0..Padding not removed. + * 0b1..Any bytes following the IP payload section of the frame are removed from the frame. + */ +#define ENET_RACC_PADREM(x) (((uint32_t)(((uint32_t)(x)) << ENET_RACC_PADREM_SHIFT)) & ENET_RACC_PADREM_MASK) +#define ENET_RACC_IPDIS_MASK (0x2U) +#define ENET_RACC_IPDIS_SHIFT (1U) +/*! IPDIS - Enable Discard Of Frames With Wrong IPv4 Header Checksum + * 0b0..Frames with wrong IPv4 header checksum are not discarded. + * 0b1..If an IPv4 frame is received with a mismatching header checksum, the frame is discarded. IPv6 has no header checksum and is not affected by this setting. Discarding is only available when the RX FIFO operates in store and forward mode (RSFL cleared). + */ +#define ENET_RACC_IPDIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RACC_IPDIS_SHIFT)) & ENET_RACC_IPDIS_MASK) +#define ENET_RACC_PRODIS_MASK (0x4U) +#define ENET_RACC_PRODIS_SHIFT (2U) +/*! PRODIS - Enable Discard Of Frames With Wrong Protocol Checksum + * 0b0..Frames with wrong checksum are not discarded. + * 0b1..If a TCP/IP, UDP/IP, or ICMP/IP frame is received that has a wrong TCP, UDP, or ICMP checksum, the frame is discarded. Discarding is only available when the RX FIFO operates in store and forward mode (RSFL cleared). + */ +#define ENET_RACC_PRODIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RACC_PRODIS_SHIFT)) & ENET_RACC_PRODIS_MASK) +#define ENET_RACC_LINEDIS_MASK (0x40U) +#define ENET_RACC_LINEDIS_SHIFT (6U) +/*! LINEDIS - Enable Discard Of Frames With MAC Layer Errors + * 0b0..Frames with errors are not discarded. + * 0b1..Any frame received with a CRC, length, or PHY error is automatically discarded and not forwarded to the user application interface. + */ +#define ENET_RACC_LINEDIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RACC_LINEDIS_SHIFT)) & ENET_RACC_LINEDIS_MASK) +#define ENET_RACC_SHIFT16_MASK (0x80U) +#define ENET_RACC_SHIFT16_SHIFT (7U) +/*! SHIFT16 - RX FIFO Shift-16 + * 0b0..Disabled. + * 0b1..Instructs the MAC to write two additional bytes in front of each frame received into the RX FIFO. + */ +#define ENET_RACC_SHIFT16(x) (((uint32_t)(((uint32_t)(x)) << ENET_RACC_SHIFT16_SHIFT)) & ENET_RACC_SHIFT16_MASK) +/*! @} */ + +/*! @name RMON_T_PACKETS - Tx Packet Count Statistic Register */ +/*! @{ */ +#define ENET_RMON_T_PACKETS_TXPKTS_MASK (0xFFFFU) +#define ENET_RMON_T_PACKETS_TXPKTS_SHIFT (0U) +#define ENET_RMON_T_PACKETS_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_PACKETS_TXPKTS_SHIFT)) & ENET_RMON_T_PACKETS_TXPKTS_MASK) +/*! @} */ + +/*! @name RMON_T_BC_PKT - Tx Broadcast Packets Statistic Register */ +/*! @{ */ +#define ENET_RMON_T_BC_PKT_TXPKTS_MASK (0xFFFFU) +#define ENET_RMON_T_BC_PKT_TXPKTS_SHIFT (0U) +#define ENET_RMON_T_BC_PKT_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_BC_PKT_TXPKTS_SHIFT)) & ENET_RMON_T_BC_PKT_TXPKTS_MASK) +/*! @} */ + +/*! @name RMON_T_MC_PKT - Tx Multicast Packets Statistic Register */ +/*! @{ */ +#define ENET_RMON_T_MC_PKT_TXPKTS_MASK (0xFFFFU) +#define ENET_RMON_T_MC_PKT_TXPKTS_SHIFT (0U) +#define ENET_RMON_T_MC_PKT_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_MC_PKT_TXPKTS_SHIFT)) & ENET_RMON_T_MC_PKT_TXPKTS_MASK) +/*! @} */ + +/*! @name RMON_T_CRC_ALIGN - Tx Packets with CRC/Align Error Statistic Register */ +/*! @{ */ +#define ENET_RMON_T_CRC_ALIGN_TXPKTS_MASK (0xFFFFU) +#define ENET_RMON_T_CRC_ALIGN_TXPKTS_SHIFT (0U) +#define ENET_RMON_T_CRC_ALIGN_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_CRC_ALIGN_TXPKTS_SHIFT)) & ENET_RMON_T_CRC_ALIGN_TXPKTS_MASK) +/*! @} */ + +/*! @name RMON_T_UNDERSIZE - Tx Packets Less Than Bytes and Good CRC Statistic Register */ +/*! @{ */ +#define ENET_RMON_T_UNDERSIZE_TXPKTS_MASK (0xFFFFU) +#define ENET_RMON_T_UNDERSIZE_TXPKTS_SHIFT (0U) +#define ENET_RMON_T_UNDERSIZE_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_UNDERSIZE_TXPKTS_SHIFT)) & ENET_RMON_T_UNDERSIZE_TXPKTS_MASK) +/*! @} */ + +/*! @name RMON_T_OVERSIZE - Tx Packets GT MAX_FL bytes and Good CRC Statistic Register */ +/*! @{ */ +#define ENET_RMON_T_OVERSIZE_TXPKTS_MASK (0xFFFFU) +#define ENET_RMON_T_OVERSIZE_TXPKTS_SHIFT (0U) +#define ENET_RMON_T_OVERSIZE_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_OVERSIZE_TXPKTS_SHIFT)) & ENET_RMON_T_OVERSIZE_TXPKTS_MASK) +/*! @} */ + +/*! @name RMON_T_FRAG - Tx Packets Less Than 64 Bytes and Bad CRC Statistic Register */ +/*! @{ */ +#define ENET_RMON_T_FRAG_TXPKTS_MASK (0xFFFFU) +#define ENET_RMON_T_FRAG_TXPKTS_SHIFT (0U) +#define ENET_RMON_T_FRAG_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_FRAG_TXPKTS_SHIFT)) & ENET_RMON_T_FRAG_TXPKTS_MASK) +/*! @} */ + +/*! @name RMON_T_JAB - Tx Packets Greater Than MAX_FL bytes and Bad CRC Statistic Register */ +/*! @{ */ +#define ENET_RMON_T_JAB_TXPKTS_MASK (0xFFFFU) +#define ENET_RMON_T_JAB_TXPKTS_SHIFT (0U) +#define ENET_RMON_T_JAB_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_JAB_TXPKTS_SHIFT)) & ENET_RMON_T_JAB_TXPKTS_MASK) +/*! @} */ + +/*! @name RMON_T_COL - Tx Collision Count Statistic Register */ +/*! @{ */ +#define ENET_RMON_T_COL_TXPKTS_MASK (0xFFFFU) +#define ENET_RMON_T_COL_TXPKTS_SHIFT (0U) +#define ENET_RMON_T_COL_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_COL_TXPKTS_SHIFT)) & ENET_RMON_T_COL_TXPKTS_MASK) +/*! @} */ + +/*! @name RMON_T_P64 - Tx 64-Byte Packets Statistic Register */ +/*! @{ */ +#define ENET_RMON_T_P64_TXPKTS_MASK (0xFFFFU) +#define ENET_RMON_T_P64_TXPKTS_SHIFT (0U) +#define ENET_RMON_T_P64_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P64_TXPKTS_SHIFT)) & ENET_RMON_T_P64_TXPKTS_MASK) +/*! @} */ + +/*! @name RMON_T_P65TO127 - Tx 65- to 127-byte Packets Statistic Register */ +/*! @{ */ +#define ENET_RMON_T_P65TO127_TXPKTS_MASK (0xFFFFU) +#define ENET_RMON_T_P65TO127_TXPKTS_SHIFT (0U) +#define ENET_RMON_T_P65TO127_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P65TO127_TXPKTS_SHIFT)) & ENET_RMON_T_P65TO127_TXPKTS_MASK) +/*! @} */ + +/*! @name RMON_T_P128TO255 - Tx 128- to 255-byte Packets Statistic Register */ +/*! @{ */ +#define ENET_RMON_T_P128TO255_TXPKTS_MASK (0xFFFFU) +#define ENET_RMON_T_P128TO255_TXPKTS_SHIFT (0U) +#define ENET_RMON_T_P128TO255_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P128TO255_TXPKTS_SHIFT)) & ENET_RMON_T_P128TO255_TXPKTS_MASK) +/*! @} */ + +/*! @name RMON_T_P256TO511 - Tx 256- to 511-byte Packets Statistic Register */ +/*! @{ */ +#define ENET_RMON_T_P256TO511_TXPKTS_MASK (0xFFFFU) +#define ENET_RMON_T_P256TO511_TXPKTS_SHIFT (0U) +#define ENET_RMON_T_P256TO511_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P256TO511_TXPKTS_SHIFT)) & ENET_RMON_T_P256TO511_TXPKTS_MASK) +/*! @} */ + +/*! @name RMON_T_P512TO1023 - Tx 512- to 1023-byte Packets Statistic Register */ +/*! @{ */ +#define ENET_RMON_T_P512TO1023_TXPKTS_MASK (0xFFFFU) +#define ENET_RMON_T_P512TO1023_TXPKTS_SHIFT (0U) +#define ENET_RMON_T_P512TO1023_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P512TO1023_TXPKTS_SHIFT)) & ENET_RMON_T_P512TO1023_TXPKTS_MASK) +/*! @} */ + +/*! @name RMON_T_P1024TO2047 - Tx 1024- to 2047-byte Packets Statistic Register */ +/*! @{ */ +#define ENET_RMON_T_P1024TO2047_TXPKTS_MASK (0xFFFFU) +#define ENET_RMON_T_P1024TO2047_TXPKTS_SHIFT (0U) +#define ENET_RMON_T_P1024TO2047_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P1024TO2047_TXPKTS_SHIFT)) & ENET_RMON_T_P1024TO2047_TXPKTS_MASK) +/*! @} */ + +/*! @name RMON_T_P_GTE2048 - Tx Packets Greater Than 2048 Bytes Statistic Register */ +/*! @{ */ +#define ENET_RMON_T_P_GTE2048_TXPKTS_MASK (0xFFFFU) +#define ENET_RMON_T_P_GTE2048_TXPKTS_SHIFT (0U) +#define ENET_RMON_T_P_GTE2048_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P_GTE2048_TXPKTS_SHIFT)) & ENET_RMON_T_P_GTE2048_TXPKTS_MASK) +/*! @} */ + +/*! @name RMON_T_OCTETS - Tx Octets Statistic Register */ +/*! @{ */ +#define ENET_RMON_T_OCTETS_TXOCTS_MASK (0xFFFFFFFFU) +#define ENET_RMON_T_OCTETS_TXOCTS_SHIFT (0U) +#define ENET_RMON_T_OCTETS_TXOCTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_OCTETS_TXOCTS_SHIFT)) & ENET_RMON_T_OCTETS_TXOCTS_MASK) +/*! @} */ + +/*! @name IEEE_T_FRAME_OK - Frames Transmitted OK Statistic Register */ +/*! @{ */ +#define ENET_IEEE_T_FRAME_OK_COUNT_MASK (0xFFFFU) +#define ENET_IEEE_T_FRAME_OK_COUNT_SHIFT (0U) +#define ENET_IEEE_T_FRAME_OK_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_FRAME_OK_COUNT_SHIFT)) & ENET_IEEE_T_FRAME_OK_COUNT_MASK) +/*! @} */ + +/*! @name IEEE_T_1COL - Frames Transmitted with Single Collision Statistic Register */ +/*! @{ */ +#define ENET_IEEE_T_1COL_COUNT_MASK (0xFFFFU) +#define ENET_IEEE_T_1COL_COUNT_SHIFT (0U) +#define ENET_IEEE_T_1COL_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_1COL_COUNT_SHIFT)) & ENET_IEEE_T_1COL_COUNT_MASK) +/*! @} */ + +/*! @name IEEE_T_MCOL - Frames Transmitted with Multiple Collisions Statistic Register */ +/*! @{ */ +#define ENET_IEEE_T_MCOL_COUNT_MASK (0xFFFFU) +#define ENET_IEEE_T_MCOL_COUNT_SHIFT (0U) +#define ENET_IEEE_T_MCOL_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_MCOL_COUNT_SHIFT)) & ENET_IEEE_T_MCOL_COUNT_MASK) +/*! @} */ + +/*! @name IEEE_T_DEF - Frames Transmitted after Deferral Delay Statistic Register */ +/*! @{ */ +#define ENET_IEEE_T_DEF_COUNT_MASK (0xFFFFU) +#define ENET_IEEE_T_DEF_COUNT_SHIFT (0U) +#define ENET_IEEE_T_DEF_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_DEF_COUNT_SHIFT)) & ENET_IEEE_T_DEF_COUNT_MASK) +/*! @} */ + +/*! @name IEEE_T_LCOL - Frames Transmitted with Late Collision Statistic Register */ +/*! @{ */ +#define ENET_IEEE_T_LCOL_COUNT_MASK (0xFFFFU) +#define ENET_IEEE_T_LCOL_COUNT_SHIFT (0U) +#define ENET_IEEE_T_LCOL_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_LCOL_COUNT_SHIFT)) & ENET_IEEE_T_LCOL_COUNT_MASK) +/*! @} */ + +/*! @name IEEE_T_EXCOL - Frames Transmitted with Excessive Collisions Statistic Register */ +/*! @{ */ +#define ENET_IEEE_T_EXCOL_COUNT_MASK (0xFFFFU) +#define ENET_IEEE_T_EXCOL_COUNT_SHIFT (0U) +#define ENET_IEEE_T_EXCOL_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_EXCOL_COUNT_SHIFT)) & ENET_IEEE_T_EXCOL_COUNT_MASK) +/*! @} */ + +/*! @name IEEE_T_MACERR - Frames Transmitted with Tx FIFO Underrun Statistic Register */ +/*! @{ */ +#define ENET_IEEE_T_MACERR_COUNT_MASK (0xFFFFU) +#define ENET_IEEE_T_MACERR_COUNT_SHIFT (0U) +#define ENET_IEEE_T_MACERR_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_MACERR_COUNT_SHIFT)) & ENET_IEEE_T_MACERR_COUNT_MASK) +/*! @} */ + +/*! @name IEEE_T_CSERR - Frames Transmitted with Carrier Sense Error Statistic Register */ +/*! @{ */ +#define ENET_IEEE_T_CSERR_COUNT_MASK (0xFFFFU) +#define ENET_IEEE_T_CSERR_COUNT_SHIFT (0U) +#define ENET_IEEE_T_CSERR_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_CSERR_COUNT_SHIFT)) & ENET_IEEE_T_CSERR_COUNT_MASK) +/*! @} */ + +/*! @name IEEE_T_SQE - Reserved Statistic Register */ +/*! @{ */ +#define ENET_IEEE_T_SQE_COUNT_MASK (0xFFFFU) +#define ENET_IEEE_T_SQE_COUNT_SHIFT (0U) +#define ENET_IEEE_T_SQE_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_SQE_COUNT_SHIFT)) & ENET_IEEE_T_SQE_COUNT_MASK) +/*! @} */ + +/*! @name IEEE_T_FDXFC - Flow Control Pause Frames Transmitted Statistic Register */ +/*! @{ */ +#define ENET_IEEE_T_FDXFC_COUNT_MASK (0xFFFFU) +#define ENET_IEEE_T_FDXFC_COUNT_SHIFT (0U) +#define ENET_IEEE_T_FDXFC_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_FDXFC_COUNT_SHIFT)) & ENET_IEEE_T_FDXFC_COUNT_MASK) +/*! @} */ + +/*! @name IEEE_T_OCTETS_OK - Octet Count for Frames Transmitted w/o Error Statistic Register */ +/*! @{ */ +#define ENET_IEEE_T_OCTETS_OK_COUNT_MASK (0xFFFFFFFFU) +#define ENET_IEEE_T_OCTETS_OK_COUNT_SHIFT (0U) +#define ENET_IEEE_T_OCTETS_OK_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_OCTETS_OK_COUNT_SHIFT)) & ENET_IEEE_T_OCTETS_OK_COUNT_MASK) +/*! @} */ + +/*! @name RMON_R_PACKETS - Rx Packet Count Statistic Register */ +/*! @{ */ +#define ENET_RMON_R_PACKETS_COUNT_MASK (0xFFFFU) +#define ENET_RMON_R_PACKETS_COUNT_SHIFT (0U) +#define ENET_RMON_R_PACKETS_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_PACKETS_COUNT_SHIFT)) & ENET_RMON_R_PACKETS_COUNT_MASK) +/*! @} */ + +/*! @name RMON_R_BC_PKT - Rx Broadcast Packets Statistic Register */ +/*! @{ */ +#define ENET_RMON_R_BC_PKT_COUNT_MASK (0xFFFFU) +#define ENET_RMON_R_BC_PKT_COUNT_SHIFT (0U) +#define ENET_RMON_R_BC_PKT_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_BC_PKT_COUNT_SHIFT)) & ENET_RMON_R_BC_PKT_COUNT_MASK) +/*! @} */ + +/*! @name RMON_R_MC_PKT - Rx Multicast Packets Statistic Register */ +/*! @{ */ +#define ENET_RMON_R_MC_PKT_COUNT_MASK (0xFFFFU) +#define ENET_RMON_R_MC_PKT_COUNT_SHIFT (0U) +#define ENET_RMON_R_MC_PKT_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_MC_PKT_COUNT_SHIFT)) & ENET_RMON_R_MC_PKT_COUNT_MASK) +/*! @} */ + +/*! @name RMON_R_CRC_ALIGN - Rx Packets with CRC/Align Error Statistic Register */ +/*! @{ */ +#define ENET_RMON_R_CRC_ALIGN_COUNT_MASK (0xFFFFU) +#define ENET_RMON_R_CRC_ALIGN_COUNT_SHIFT (0U) +#define ENET_RMON_R_CRC_ALIGN_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_CRC_ALIGN_COUNT_SHIFT)) & ENET_RMON_R_CRC_ALIGN_COUNT_MASK) +/*! @} */ + +/*! @name RMON_R_UNDERSIZE - Rx Packets with Less Than 64 Bytes and Good CRC Statistic Register */ +/*! @{ */ +#define ENET_RMON_R_UNDERSIZE_COUNT_MASK (0xFFFFU) +#define ENET_RMON_R_UNDERSIZE_COUNT_SHIFT (0U) +#define ENET_RMON_R_UNDERSIZE_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_UNDERSIZE_COUNT_SHIFT)) & ENET_RMON_R_UNDERSIZE_COUNT_MASK) +/*! @} */ + +/*! @name RMON_R_OVERSIZE - Rx Packets Greater Than MAX_FL and Good CRC Statistic Register */ +/*! @{ */ +#define ENET_RMON_R_OVERSIZE_COUNT_MASK (0xFFFFU) +#define ENET_RMON_R_OVERSIZE_COUNT_SHIFT (0U) +#define ENET_RMON_R_OVERSIZE_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_OVERSIZE_COUNT_SHIFT)) & ENET_RMON_R_OVERSIZE_COUNT_MASK) +/*! @} */ + +/*! @name RMON_R_FRAG - Rx Packets Less Than 64 Bytes and Bad CRC Statistic Register */ +/*! @{ */ +#define ENET_RMON_R_FRAG_COUNT_MASK (0xFFFFU) +#define ENET_RMON_R_FRAG_COUNT_SHIFT (0U) +#define ENET_RMON_R_FRAG_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_FRAG_COUNT_SHIFT)) & ENET_RMON_R_FRAG_COUNT_MASK) +/*! @} */ + +/*! @name RMON_R_JAB - Rx Packets Greater Than MAX_FL Bytes and Bad CRC Statistic Register */ +/*! @{ */ +#define ENET_RMON_R_JAB_COUNT_MASK (0xFFFFU) +#define ENET_RMON_R_JAB_COUNT_SHIFT (0U) +#define ENET_RMON_R_JAB_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_JAB_COUNT_SHIFT)) & ENET_RMON_R_JAB_COUNT_MASK) +/*! @} */ + +/*! @name RMON_R_P64 - Rx 64-Byte Packets Statistic Register */ +/*! @{ */ +#define ENET_RMON_R_P64_COUNT_MASK (0xFFFFU) +#define ENET_RMON_R_P64_COUNT_SHIFT (0U) +#define ENET_RMON_R_P64_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P64_COUNT_SHIFT)) & ENET_RMON_R_P64_COUNT_MASK) +/*! @} */ + +/*! @name RMON_R_P65TO127 - Rx 65- to 127-Byte Packets Statistic Register */ +/*! @{ */ +#define ENET_RMON_R_P65TO127_COUNT_MASK (0xFFFFU) +#define ENET_RMON_R_P65TO127_COUNT_SHIFT (0U) +#define ENET_RMON_R_P65TO127_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P65TO127_COUNT_SHIFT)) & ENET_RMON_R_P65TO127_COUNT_MASK) +/*! @} */ + +/*! @name RMON_R_P128TO255 - Rx 128- to 255-Byte Packets Statistic Register */ +/*! @{ */ +#define ENET_RMON_R_P128TO255_COUNT_MASK (0xFFFFU) +#define ENET_RMON_R_P128TO255_COUNT_SHIFT (0U) +#define ENET_RMON_R_P128TO255_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P128TO255_COUNT_SHIFT)) & ENET_RMON_R_P128TO255_COUNT_MASK) +/*! @} */ + +/*! @name RMON_R_P256TO511 - Rx 256- to 511-Byte Packets Statistic Register */ +/*! @{ */ +#define ENET_RMON_R_P256TO511_COUNT_MASK (0xFFFFU) +#define ENET_RMON_R_P256TO511_COUNT_SHIFT (0U) +#define ENET_RMON_R_P256TO511_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P256TO511_COUNT_SHIFT)) & ENET_RMON_R_P256TO511_COUNT_MASK) +/*! @} */ + +/*! @name RMON_R_P512TO1023 - Rx 512- to 1023-Byte Packets Statistic Register */ +/*! @{ */ +#define ENET_RMON_R_P512TO1023_COUNT_MASK (0xFFFFU) +#define ENET_RMON_R_P512TO1023_COUNT_SHIFT (0U) +#define ENET_RMON_R_P512TO1023_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P512TO1023_COUNT_SHIFT)) & ENET_RMON_R_P512TO1023_COUNT_MASK) +/*! @} */ + +/*! @name RMON_R_P1024TO2047 - Rx 1024- to 2047-Byte Packets Statistic Register */ +/*! @{ */ +#define ENET_RMON_R_P1024TO2047_COUNT_MASK (0xFFFFU) +#define ENET_RMON_R_P1024TO2047_COUNT_SHIFT (0U) +#define ENET_RMON_R_P1024TO2047_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P1024TO2047_COUNT_SHIFT)) & ENET_RMON_R_P1024TO2047_COUNT_MASK) +/*! @} */ + +/*! @name RMON_R_P_GTE2048 - Rx Packets Greater than 2048 Bytes Statistic Register */ +/*! @{ */ +#define ENET_RMON_R_P_GTE2048_COUNT_MASK (0xFFFFU) +#define ENET_RMON_R_P_GTE2048_COUNT_SHIFT (0U) +#define ENET_RMON_R_P_GTE2048_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P_GTE2048_COUNT_SHIFT)) & ENET_RMON_R_P_GTE2048_COUNT_MASK) +/*! @} */ + +/*! @name RMON_R_OCTETS - Rx Octets Statistic Register */ +/*! @{ */ +#define ENET_RMON_R_OCTETS_COUNT_MASK (0xFFFFFFFFU) +#define ENET_RMON_R_OCTETS_COUNT_SHIFT (0U) +#define ENET_RMON_R_OCTETS_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_OCTETS_COUNT_SHIFT)) & ENET_RMON_R_OCTETS_COUNT_MASK) +/*! @} */ + +/*! @name IEEE_R_DROP - Frames not Counted Correctly Statistic Register */ +/*! @{ */ +#define ENET_IEEE_R_DROP_COUNT_MASK (0xFFFFU) +#define ENET_IEEE_R_DROP_COUNT_SHIFT (0U) +#define ENET_IEEE_R_DROP_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_DROP_COUNT_SHIFT)) & ENET_IEEE_R_DROP_COUNT_MASK) +/*! @} */ + +/*! @name IEEE_R_FRAME_OK - Frames Received OK Statistic Register */ +/*! @{ */ +#define ENET_IEEE_R_FRAME_OK_COUNT_MASK (0xFFFFU) +#define ENET_IEEE_R_FRAME_OK_COUNT_SHIFT (0U) +#define ENET_IEEE_R_FRAME_OK_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_FRAME_OK_COUNT_SHIFT)) & ENET_IEEE_R_FRAME_OK_COUNT_MASK) +/*! @} */ + +/*! @name IEEE_R_CRC - Frames Received with CRC Error Statistic Register */ +/*! @{ */ +#define ENET_IEEE_R_CRC_COUNT_MASK (0xFFFFU) +#define ENET_IEEE_R_CRC_COUNT_SHIFT (0U) +#define ENET_IEEE_R_CRC_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_CRC_COUNT_SHIFT)) & ENET_IEEE_R_CRC_COUNT_MASK) +/*! @} */ + +/*! @name IEEE_R_ALIGN - Frames Received with Alignment Error Statistic Register */ +/*! @{ */ +#define ENET_IEEE_R_ALIGN_COUNT_MASK (0xFFFFU) +#define ENET_IEEE_R_ALIGN_COUNT_SHIFT (0U) +#define ENET_IEEE_R_ALIGN_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_ALIGN_COUNT_SHIFT)) & ENET_IEEE_R_ALIGN_COUNT_MASK) +/*! @} */ + +/*! @name IEEE_R_MACERR - Receive FIFO Overflow Count Statistic Register */ +/*! @{ */ +#define ENET_IEEE_R_MACERR_COUNT_MASK (0xFFFFU) +#define ENET_IEEE_R_MACERR_COUNT_SHIFT (0U) +#define ENET_IEEE_R_MACERR_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_MACERR_COUNT_SHIFT)) & ENET_IEEE_R_MACERR_COUNT_MASK) +/*! @} */ + +/*! @name IEEE_R_FDXFC - Flow Control Pause Frames Received Statistic Register */ +/*! @{ */ +#define ENET_IEEE_R_FDXFC_COUNT_MASK (0xFFFFU) +#define ENET_IEEE_R_FDXFC_COUNT_SHIFT (0U) +#define ENET_IEEE_R_FDXFC_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_FDXFC_COUNT_SHIFT)) & ENET_IEEE_R_FDXFC_COUNT_MASK) +/*! @} */ + +/*! @name IEEE_R_OCTETS_OK - Octet Count for Frames Received without Error Statistic Register */ +/*! @{ */ +#define ENET_IEEE_R_OCTETS_OK_COUNT_MASK (0xFFFFFFFFU) +#define ENET_IEEE_R_OCTETS_OK_COUNT_SHIFT (0U) +#define ENET_IEEE_R_OCTETS_OK_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_OCTETS_OK_COUNT_SHIFT)) & ENET_IEEE_R_OCTETS_OK_COUNT_MASK) +/*! @} */ + +/*! @name ATCR - Adjustable Timer Control Register */ +/*! @{ */ +#define ENET_ATCR_EN_MASK (0x1U) +#define ENET_ATCR_EN_SHIFT (0U) +/*! EN - Enable Timer + * 0b0..The timer stops at the current value. + * 0b1..The timer starts incrementing. + */ +#define ENET_ATCR_EN(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_EN_SHIFT)) & ENET_ATCR_EN_MASK) +#define ENET_ATCR_OFFEN_MASK (0x4U) +#define ENET_ATCR_OFFEN_SHIFT (2U) +/*! OFFEN - Enable One-Shot Offset Event + * 0b0..Disable. + * 0b1..The timer can be reset to zero when the given offset time is reached (offset event). The field is cleared when the offset event is reached, so no further event occurs until the field is set again. The timer offset value must be set before setting this field. + */ +#define ENET_ATCR_OFFEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_OFFEN_SHIFT)) & ENET_ATCR_OFFEN_MASK) +#define ENET_ATCR_OFFRST_MASK (0x8U) +#define ENET_ATCR_OFFRST_SHIFT (3U) +/*! OFFRST - Reset Timer On Offset Event + * 0b0..The timer is not affected and no action occurs, besides clearing OFFEN, when the offset is reached. + * 0b1..If OFFEN is set, the timer resets to zero when the offset setting is reached. The offset event does not cause a timer interrupt. + */ +#define ENET_ATCR_OFFRST(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_OFFRST_SHIFT)) & ENET_ATCR_OFFRST_MASK) +#define ENET_ATCR_PEREN_MASK (0x10U) +#define ENET_ATCR_PEREN_SHIFT (4U) +/*! PEREN - Enable Periodical Event + * 0b0..Disable. + * 0b1..A period event interrupt can be generated (EIR[TS_TIMER]) and the event signal output is asserted when the timer wraps around according to the periodic setting ATPER. The timer period value must be set before setting this bit. Not all devices contain the event signal output. See the chip configuration details. + */ +#define ENET_ATCR_PEREN(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_PEREN_SHIFT)) & ENET_ATCR_PEREN_MASK) +#define ENET_ATCR_PINPER_MASK (0x80U) +#define ENET_ATCR_PINPER_SHIFT (7U) +/*! PINPER + * 0b0..Disable. + * 0b1..Enable. + */ +#define ENET_ATCR_PINPER(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_PINPER_SHIFT)) & ENET_ATCR_PINPER_MASK) +#define ENET_ATCR_RESTART_MASK (0x200U) +#define ENET_ATCR_RESTART_SHIFT (9U) +#define ENET_ATCR_RESTART(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_RESTART_SHIFT)) & ENET_ATCR_RESTART_MASK) +#define ENET_ATCR_CAPTURE_MASK (0x800U) +#define ENET_ATCR_CAPTURE_SHIFT (11U) +/*! CAPTURE - Capture Timer Value + * 0b0..No effect. + * 0b1..The current time is captured and can be read from the ATVR register. + */ +#define ENET_ATCR_CAPTURE(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_CAPTURE_SHIFT)) & ENET_ATCR_CAPTURE_MASK) +#define ENET_ATCR_SLAVE_MASK (0x2000U) +#define ENET_ATCR_SLAVE_SHIFT (13U) +/*! SLAVE - Enable Timer Slave Mode + * 0b0..The timer is active and all configuration fields in this register are relevant. + * 0b1..The internal timer is disabled and the externally provided timer value is used. All other fields, except CAPTURE, in this register have no effect. CAPTURE can still be used to capture the current timer value. + */ +#define ENET_ATCR_SLAVE(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_SLAVE_SHIFT)) & ENET_ATCR_SLAVE_MASK) +/*! @} */ + +/*! @name ATVR - Timer Value Register */ +/*! @{ */ +#define ENET_ATVR_ATIME_MASK (0xFFFFFFFFU) +#define ENET_ATVR_ATIME_SHIFT (0U) +#define ENET_ATVR_ATIME(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATVR_ATIME_SHIFT)) & ENET_ATVR_ATIME_MASK) +/*! @} */ + +/*! @name ATOFF - Timer Offset Register */ +/*! @{ */ +#define ENET_ATOFF_OFFSET_MASK (0xFFFFFFFFU) +#define ENET_ATOFF_OFFSET_SHIFT (0U) +#define ENET_ATOFF_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATOFF_OFFSET_SHIFT)) & ENET_ATOFF_OFFSET_MASK) +/*! @} */ + +/*! @name ATPER - Timer Period Register */ +/*! @{ */ +#define ENET_ATPER_PERIOD_MASK (0xFFFFFFFFU) +#define ENET_ATPER_PERIOD_SHIFT (0U) +#define ENET_ATPER_PERIOD(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATPER_PERIOD_SHIFT)) & ENET_ATPER_PERIOD_MASK) +/*! @} */ + +/*! @name ATCOR - Timer Correction Register */ +/*! @{ */ +#define ENET_ATCOR_COR_MASK (0x7FFFFFFFU) +#define ENET_ATCOR_COR_SHIFT (0U) +#define ENET_ATCOR_COR(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATCOR_COR_SHIFT)) & ENET_ATCOR_COR_MASK) +/*! @} */ + +/*! @name ATINC - Time-Stamping Clock Period Register */ +/*! @{ */ +#define ENET_ATINC_INC_MASK (0x7FU) +#define ENET_ATINC_INC_SHIFT (0U) +#define ENET_ATINC_INC(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATINC_INC_SHIFT)) & ENET_ATINC_INC_MASK) +#define ENET_ATINC_INC_CORR_MASK (0x7F00U) +#define ENET_ATINC_INC_CORR_SHIFT (8U) +#define ENET_ATINC_INC_CORR(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATINC_INC_CORR_SHIFT)) & ENET_ATINC_INC_CORR_MASK) +/*! @} */ + +/*! @name ATSTMP - Timestamp of Last Transmitted Frame */ +/*! @{ */ +#define ENET_ATSTMP_TIMESTAMP_MASK (0xFFFFFFFFU) +#define ENET_ATSTMP_TIMESTAMP_SHIFT (0U) +#define ENET_ATSTMP_TIMESTAMP(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATSTMP_TIMESTAMP_SHIFT)) & ENET_ATSTMP_TIMESTAMP_MASK) +/*! @} */ + +/*! @name TGSR - Timer Global Status Register */ +/*! @{ */ +#define ENET_TGSR_TF0_MASK (0x1U) +#define ENET_TGSR_TF0_SHIFT (0U) +/*! TF0 - Copy Of Timer Flag For Channel 0 + * 0b0..Timer Flag for Channel 0 is clear + * 0b1..Timer Flag for Channel 0 is set + */ +#define ENET_TGSR_TF0(x) (((uint32_t)(((uint32_t)(x)) << ENET_TGSR_TF0_SHIFT)) & ENET_TGSR_TF0_MASK) +#define ENET_TGSR_TF1_MASK (0x2U) +#define ENET_TGSR_TF1_SHIFT (1U) +/*! TF1 - Copy Of Timer Flag For Channel 1 + * 0b0..Timer Flag for Channel 1 is clear + * 0b1..Timer Flag for Channel 1 is set + */ +#define ENET_TGSR_TF1(x) (((uint32_t)(((uint32_t)(x)) << ENET_TGSR_TF1_SHIFT)) & ENET_TGSR_TF1_MASK) +#define ENET_TGSR_TF2_MASK (0x4U) +#define ENET_TGSR_TF2_SHIFT (2U) +/*! TF2 - Copy Of Timer Flag For Channel 2 + * 0b0..Timer Flag for Channel 2 is clear + * 0b1..Timer Flag for Channel 2 is set + */ +#define ENET_TGSR_TF2(x) (((uint32_t)(((uint32_t)(x)) << ENET_TGSR_TF2_SHIFT)) & ENET_TGSR_TF2_MASK) +#define ENET_TGSR_TF3_MASK (0x8U) +#define ENET_TGSR_TF3_SHIFT (3U) +/*! TF3 - Copy Of Timer Flag For Channel 3 + * 0b0..Timer Flag for Channel 3 is clear + * 0b1..Timer Flag for Channel 3 is set + */ +#define ENET_TGSR_TF3(x) (((uint32_t)(((uint32_t)(x)) << ENET_TGSR_TF3_SHIFT)) & ENET_TGSR_TF3_MASK) +/*! @} */ + +/*! @name TCSR - Timer Control Status Register */ +/*! @{ */ +#define ENET_TCSR_TDRE_MASK (0x1U) +#define ENET_TCSR_TDRE_SHIFT (0U) +/*! TDRE - Timer DMA Request Enable + * 0b0..DMA request is disabled + * 0b1..DMA request is enabled + */ +#define ENET_TCSR_TDRE(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCSR_TDRE_SHIFT)) & ENET_TCSR_TDRE_MASK) +#define ENET_TCSR_TMODE_MASK (0x3CU) +#define ENET_TCSR_TMODE_SHIFT (2U) +/*! TMODE - Timer Mode + * 0b0000..Timer Channel is disabled. + * 0b0001..Timer Channel is configured for Input Capture on rising edge. + * 0b0010..Timer Channel is configured for Input Capture on falling edge. + * 0b0011..Timer Channel is configured for Input Capture on both edges. + * 0b0100..Timer Channel is configured for Output Compare - software only. + * 0b0101..Timer Channel is configured for Output Compare - toggle output on compare. + * 0b0110..Timer Channel is configured for Output Compare - clear output on compare. + * 0b0111..Timer Channel is configured for Output Compare - set output on compare. + * 0b1000..Reserved + * 0b1010..Timer Channel is configured for Output Compare - clear output on compare, set output on overflow. + * 0b10x1..Timer Channel is configured for Output Compare - set output on compare, clear output on overflow. + * 0b110x..Reserved + * 0b1110..Timer Channel is configured for Output Compare - pulse output low on compare for 1 to 32 1588-clock cycles as specified by TPWC. + * 0b1111..Timer Channel is configured for Output Compare - pulse output high on compare for 1 to 32 1588-clock cycles as specified by TPWC. + */ +#define ENET_TCSR_TMODE(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCSR_TMODE_SHIFT)) & ENET_TCSR_TMODE_MASK) +#define ENET_TCSR_TIE_MASK (0x40U) +#define ENET_TCSR_TIE_SHIFT (6U) +/*! TIE - Timer Interrupt Enable + * 0b0..Interrupt is disabled + * 0b1..Interrupt is enabled + */ +#define ENET_TCSR_TIE(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCSR_TIE_SHIFT)) & ENET_TCSR_TIE_MASK) +#define ENET_TCSR_TF_MASK (0x80U) +#define ENET_TCSR_TF_SHIFT (7U) +/*! TF - Timer Flag + * 0b0..Input Capture or Output Compare has not occurred. + * 0b1..Input Capture or Output Compare has occurred. + */ +#define ENET_TCSR_TF(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCSR_TF_SHIFT)) & ENET_TCSR_TF_MASK) +#define ENET_TCSR_TPWC_MASK (0xF800U) +#define ENET_TCSR_TPWC_SHIFT (11U) +/*! TPWC - Timer PulseWidth Control + * 0b00000..Pulse width is one 1588-clock cycle. + * 0b00001..Pulse width is two 1588-clock cycles. + * 0b00010..Pulse width is three 1588-clock cycles. + * 0b00011..Pulse width is four 1588-clock cycles. + * 0b11111..Pulse width is 32 1588-clock cycles. + */ +#define ENET_TCSR_TPWC(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCSR_TPWC_SHIFT)) & ENET_TCSR_TPWC_MASK) +/*! @} */ + +/* The count of ENET_TCSR */ +#define ENET_TCSR_COUNT (4U) + +/*! @name TCCR - Timer Compare Capture Register */ +/*! @{ */ +#define ENET_TCCR_TCC_MASK (0xFFFFFFFFU) +#define ENET_TCCR_TCC_SHIFT (0U) +#define ENET_TCCR_TCC(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCCR_TCC_SHIFT)) & ENET_TCCR_TCC_MASK) +/*! @} */ + +/* The count of ENET_TCCR */ +#define ENET_TCCR_COUNT (4U) + + +/*! + * @} + */ /* end of group ENET_Register_Masks */ + + +/* ENET - Peripheral instance base addresses */ +/** Peripheral ENET base address */ +#define ENET_BASE (0x402D8000u) +/** Peripheral ENET base pointer */ +#define ENET ((ENET_Type *)ENET_BASE) +/** Array initializer of ENET peripheral base addresses */ +#define ENET_BASE_ADDRS { ENET_BASE } +/** Array initializer of ENET peripheral base pointers */ +#define ENET_BASE_PTRS { ENET } +/** Interrupt vectors for the ENET peripheral type */ +#define ENET_Transmit_IRQS { ENET_IRQn } +#define ENET_Receive_IRQS { ENET_IRQn } +#define ENET_Error_IRQS { ENET_IRQn } +#define ENET_1588_Timer_IRQS { ENET_1588_Timer_IRQn } +/* ENET Buffer Descriptor and Buffer Address Alignment. */ +#define ENET_BUFF_ALIGNMENT (64U) + + +/*! + * @} + */ /* end of group ENET_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- EWM Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup EWM_Peripheral_Access_Layer EWM Peripheral Access Layer + * @{ + */ + +/** EWM - Register Layout Typedef */ +typedef struct { + __IO uint8_t CTRL; /**< Control Register, offset: 0x0 */ + __O uint8_t SERV; /**< Service Register, offset: 0x1 */ + __IO uint8_t CMPL; /**< Compare Low Register, offset: 0x2 */ + __IO uint8_t CMPH; /**< Compare High Register, offset: 0x3 */ + __IO uint8_t CLKCTRL; /**< Clock Control Register, offset: 0x4 */ + __IO uint8_t CLKPRESCALER; /**< Clock Prescaler Register, offset: 0x5 */ +} EWM_Type; + +/* ---------------------------------------------------------------------------- + -- EWM Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup EWM_Register_Masks EWM Register Masks + * @{ + */ + +/*! @name CTRL - Control Register */ +/*! @{ */ +#define EWM_CTRL_EWMEN_MASK (0x1U) +#define EWM_CTRL_EWMEN_SHIFT (0U) +#define EWM_CTRL_EWMEN(x) (((uint8_t)(((uint8_t)(x)) << EWM_CTRL_EWMEN_SHIFT)) & EWM_CTRL_EWMEN_MASK) +#define EWM_CTRL_ASSIN_MASK (0x2U) +#define EWM_CTRL_ASSIN_SHIFT (1U) +#define EWM_CTRL_ASSIN(x) (((uint8_t)(((uint8_t)(x)) << EWM_CTRL_ASSIN_SHIFT)) & EWM_CTRL_ASSIN_MASK) +#define EWM_CTRL_INEN_MASK (0x4U) +#define EWM_CTRL_INEN_SHIFT (2U) +#define EWM_CTRL_INEN(x) (((uint8_t)(((uint8_t)(x)) << EWM_CTRL_INEN_SHIFT)) & EWM_CTRL_INEN_MASK) +#define EWM_CTRL_INTEN_MASK (0x8U) +#define EWM_CTRL_INTEN_SHIFT (3U) +#define EWM_CTRL_INTEN(x) (((uint8_t)(((uint8_t)(x)) << EWM_CTRL_INTEN_SHIFT)) & EWM_CTRL_INTEN_MASK) +/*! @} */ + +/*! @name SERV - Service Register */ +/*! @{ */ +#define EWM_SERV_SERVICE_MASK (0xFFU) +#define EWM_SERV_SERVICE_SHIFT (0U) +#define EWM_SERV_SERVICE(x) (((uint8_t)(((uint8_t)(x)) << EWM_SERV_SERVICE_SHIFT)) & EWM_SERV_SERVICE_MASK) +/*! @} */ + +/*! @name CMPL - Compare Low Register */ +/*! @{ */ +#define EWM_CMPL_COMPAREL_MASK (0xFFU) +#define EWM_CMPL_COMPAREL_SHIFT (0U) +#define EWM_CMPL_COMPAREL(x) (((uint8_t)(((uint8_t)(x)) << EWM_CMPL_COMPAREL_SHIFT)) & EWM_CMPL_COMPAREL_MASK) +/*! @} */ + +/*! @name CMPH - Compare High Register */ +/*! @{ */ +#define EWM_CMPH_COMPAREH_MASK (0xFFU) +#define EWM_CMPH_COMPAREH_SHIFT (0U) +#define EWM_CMPH_COMPAREH(x) (((uint8_t)(((uint8_t)(x)) << EWM_CMPH_COMPAREH_SHIFT)) & EWM_CMPH_COMPAREH_MASK) +/*! @} */ + +/*! @name CLKCTRL - Clock Control Register */ +/*! @{ */ +#define EWM_CLKCTRL_CLKSEL_MASK (0x3U) +#define EWM_CLKCTRL_CLKSEL_SHIFT (0U) +#define EWM_CLKCTRL_CLKSEL(x) (((uint8_t)(((uint8_t)(x)) << EWM_CLKCTRL_CLKSEL_SHIFT)) & EWM_CLKCTRL_CLKSEL_MASK) +/*! @} */ + +/*! @name CLKPRESCALER - Clock Prescaler Register */ +/*! @{ */ +#define EWM_CLKPRESCALER_CLK_DIV_MASK (0xFFU) +#define EWM_CLKPRESCALER_CLK_DIV_SHIFT (0U) +#define EWM_CLKPRESCALER_CLK_DIV(x) (((uint8_t)(((uint8_t)(x)) << EWM_CLKPRESCALER_CLK_DIV_SHIFT)) & EWM_CLKPRESCALER_CLK_DIV_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group EWM_Register_Masks */ + + +/* EWM - Peripheral instance base addresses */ +/** Peripheral EWM base address */ +#define EWM_BASE (0x400B4000u) +/** Peripheral EWM base pointer */ +#define EWM ((EWM_Type *)EWM_BASE) +/** Array initializer of EWM peripheral base addresses */ +#define EWM_BASE_ADDRS { EWM_BASE } +/** Array initializer of EWM peripheral base pointers */ +#define EWM_BASE_PTRS { EWM } +/** Interrupt vectors for the EWM peripheral type */ +#define EWM_IRQS { EWM_IRQn } + +/*! + * @} + */ /* end of group EWM_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- FLEXIO Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup FLEXIO_Peripheral_Access_Layer FLEXIO Peripheral Access Layer + * @{ + */ + +/** FLEXIO - Register Layout Typedef */ +typedef struct { + __I uint32_t VERID; /**< Version ID Register, offset: 0x0 */ + __I uint32_t PARAM; /**< Parameter Register, offset: 0x4 */ + __IO uint32_t CTRL; /**< FlexIO Control Register, offset: 0x8 */ + __I uint32_t PIN; /**< Pin State Register, offset: 0xC */ + __IO uint32_t SHIFTSTAT; /**< Shifter Status Register, offset: 0x10 */ + __IO uint32_t SHIFTERR; /**< Shifter Error Register, offset: 0x14 */ + __IO uint32_t TIMSTAT; /**< Timer Status Register, offset: 0x18 */ + uint8_t RESERVED_0[4]; + __IO uint32_t SHIFTSIEN; /**< Shifter Status Interrupt Enable, offset: 0x20 */ + __IO uint32_t SHIFTEIEN; /**< Shifter Error Interrupt Enable, offset: 0x24 */ + __IO uint32_t TIMIEN; /**< Timer Interrupt Enable Register, offset: 0x28 */ + uint8_t RESERVED_1[4]; + __IO uint32_t SHIFTSDEN; /**< Shifter Status DMA Enable, offset: 0x30 */ + uint8_t RESERVED_2[12]; + __IO uint32_t SHIFTSTATE; /**< Shifter State Register, offset: 0x40 */ + uint8_t RESERVED_3[60]; + __IO uint32_t SHIFTCTL[4]; /**< Shifter Control N Register, array offset: 0x80, array step: 0x4 */ + uint8_t RESERVED_4[112]; + __IO uint32_t SHIFTCFG[4]; /**< Shifter Configuration N Register, array offset: 0x100, array step: 0x4 */ + uint8_t RESERVED_5[240]; + __IO uint32_t SHIFTBUF[4]; /**< Shifter Buffer N Register, array offset: 0x200, array step: 0x4 */ + uint8_t RESERVED_6[112]; + __IO uint32_t SHIFTBUFBIS[4]; /**< Shifter Buffer N Bit Swapped Register, array offset: 0x280, array step: 0x4 */ + uint8_t RESERVED_7[112]; + __IO uint32_t SHIFTBUFBYS[4]; /**< Shifter Buffer N Byte Swapped Register, array offset: 0x300, array step: 0x4 */ + uint8_t RESERVED_8[112]; + __IO uint32_t SHIFTBUFBBS[4]; /**< Shifter Buffer N Bit Byte Swapped Register, array offset: 0x380, array step: 0x4 */ + uint8_t RESERVED_9[112]; + __IO uint32_t TIMCTL[4]; /**< Timer Control N Register, array offset: 0x400, array step: 0x4 */ + uint8_t RESERVED_10[112]; + __IO uint32_t TIMCFG[4]; /**< Timer Configuration N Register, array offset: 0x480, array step: 0x4 */ + uint8_t RESERVED_11[112]; + __IO uint32_t TIMCMP[4]; /**< Timer Compare N Register, array offset: 0x500, array step: 0x4 */ + uint8_t RESERVED_12[368]; + __IO uint32_t SHIFTBUFNBS[4]; /**< Shifter Buffer N Nibble Byte Swapped Register, array offset: 0x680, array step: 0x4 */ + uint8_t RESERVED_13[112]; + __IO uint32_t SHIFTBUFHWS[4]; /**< Shifter Buffer N Half Word Swapped Register, array offset: 0x700, array step: 0x4 */ + uint8_t RESERVED_14[112]; + __IO uint32_t SHIFTBUFNIS[4]; /**< Shifter Buffer N Nibble Swapped Register, array offset: 0x780, array step: 0x4 */ +} FLEXIO_Type; + +/* ---------------------------------------------------------------------------- + -- FLEXIO Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup FLEXIO_Register_Masks FLEXIO Register Masks + * @{ + */ + +/*! @name VERID - Version ID Register */ +/*! @{ */ +#define FLEXIO_VERID_FEATURE_MASK (0xFFFFU) +#define FLEXIO_VERID_FEATURE_SHIFT (0U) +/*! FEATURE - Feature Specification Number + * 0b0000000000000000..Standard features implemented. + * 0b0000000000000001..Supports state, logic and parallel modes. + */ +#define FLEXIO_VERID_FEATURE(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_VERID_FEATURE_SHIFT)) & FLEXIO_VERID_FEATURE_MASK) +#define FLEXIO_VERID_MINOR_MASK (0xFF0000U) +#define FLEXIO_VERID_MINOR_SHIFT (16U) +#define FLEXIO_VERID_MINOR(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_VERID_MINOR_SHIFT)) & FLEXIO_VERID_MINOR_MASK) +#define FLEXIO_VERID_MAJOR_MASK (0xFF000000U) +#define FLEXIO_VERID_MAJOR_SHIFT (24U) +#define FLEXIO_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_VERID_MAJOR_SHIFT)) & FLEXIO_VERID_MAJOR_MASK) +/*! @} */ + +/*! @name PARAM - Parameter Register */ +/*! @{ */ +#define FLEXIO_PARAM_SHIFTER_MASK (0xFFU) +#define FLEXIO_PARAM_SHIFTER_SHIFT (0U) +#define FLEXIO_PARAM_SHIFTER(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_PARAM_SHIFTER_SHIFT)) & FLEXIO_PARAM_SHIFTER_MASK) +#define FLEXIO_PARAM_TIMER_MASK (0xFF00U) +#define FLEXIO_PARAM_TIMER_SHIFT (8U) +#define FLEXIO_PARAM_TIMER(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_PARAM_TIMER_SHIFT)) & FLEXIO_PARAM_TIMER_MASK) +#define FLEXIO_PARAM_PIN_MASK (0xFF0000U) +#define FLEXIO_PARAM_PIN_SHIFT (16U) +#define FLEXIO_PARAM_PIN(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_PARAM_PIN_SHIFT)) & FLEXIO_PARAM_PIN_MASK) +#define FLEXIO_PARAM_TRIGGER_MASK (0xFF000000U) +#define FLEXIO_PARAM_TRIGGER_SHIFT (24U) +#define FLEXIO_PARAM_TRIGGER(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_PARAM_TRIGGER_SHIFT)) & FLEXIO_PARAM_TRIGGER_MASK) +/*! @} */ + +/*! @name CTRL - FlexIO Control Register */ +/*! @{ */ +#define FLEXIO_CTRL_FLEXEN_MASK (0x1U) +#define FLEXIO_CTRL_FLEXEN_SHIFT (0U) +/*! FLEXEN - FlexIO Enable + * 0b0..FlexIO module is disabled. + * 0b1..FlexIO module is enabled. + */ +#define FLEXIO_CTRL_FLEXEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_CTRL_FLEXEN_SHIFT)) & FLEXIO_CTRL_FLEXEN_MASK) +#define FLEXIO_CTRL_SWRST_MASK (0x2U) +#define FLEXIO_CTRL_SWRST_SHIFT (1U) +/*! SWRST - Software Reset + * 0b0..Software reset is disabled + * 0b1..Software reset is enabled, all FlexIO registers except the Control Register are reset. + */ +#define FLEXIO_CTRL_SWRST(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_CTRL_SWRST_SHIFT)) & FLEXIO_CTRL_SWRST_MASK) +#define FLEXIO_CTRL_FASTACC_MASK (0x4U) +#define FLEXIO_CTRL_FASTACC_SHIFT (2U) +/*! FASTACC - Fast Access + * 0b0..Configures for normal register accesses to FlexIO + * 0b1..Configures for fast register accesses to FlexIO + */ +#define FLEXIO_CTRL_FASTACC(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_CTRL_FASTACC_SHIFT)) & FLEXIO_CTRL_FASTACC_MASK) +#define FLEXIO_CTRL_DBGE_MASK (0x40000000U) +#define FLEXIO_CTRL_DBGE_SHIFT (30U) +/*! DBGE - Debug Enable + * 0b0..FlexIO is disabled in debug modes. + * 0b1..FlexIO is enabled in debug modes + */ +#define FLEXIO_CTRL_DBGE(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_CTRL_DBGE_SHIFT)) & FLEXIO_CTRL_DBGE_MASK) +#define FLEXIO_CTRL_DOZEN_MASK (0x80000000U) +#define FLEXIO_CTRL_DOZEN_SHIFT (31U) +/*! DOZEN - Doze Enable + * 0b0..FlexIO enabled in Doze modes. + * 0b1..FlexIO disabled in Doze modes. + */ +#define FLEXIO_CTRL_DOZEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_CTRL_DOZEN_SHIFT)) & FLEXIO_CTRL_DOZEN_MASK) +/*! @} */ + +/*! @name PIN - Pin State Register */ +/*! @{ */ +#define FLEXIO_PIN_PDI_MASK (0xFFFFFFFFU) +#define FLEXIO_PIN_PDI_SHIFT (0U) +#define FLEXIO_PIN_PDI(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_PIN_PDI_SHIFT)) & FLEXIO_PIN_PDI_MASK) +/*! @} */ + +/*! @name SHIFTSTAT - Shifter Status Register */ +/*! @{ */ +#define FLEXIO_SHIFTSTAT_SSF_MASK (0xFU) +#define FLEXIO_SHIFTSTAT_SSF_SHIFT (0U) +#define FLEXIO_SHIFTSTAT_SSF(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTSTAT_SSF_SHIFT)) & FLEXIO_SHIFTSTAT_SSF_MASK) +/*! @} */ + +/*! @name SHIFTERR - Shifter Error Register */ +/*! @{ */ +#define FLEXIO_SHIFTERR_SEF_MASK (0xFU) +#define FLEXIO_SHIFTERR_SEF_SHIFT (0U) +#define FLEXIO_SHIFTERR_SEF(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTERR_SEF_SHIFT)) & FLEXIO_SHIFTERR_SEF_MASK) +/*! @} */ + +/*! @name TIMSTAT - Timer Status Register */ +/*! @{ */ +#define FLEXIO_TIMSTAT_TSF_MASK (0xFU) +#define FLEXIO_TIMSTAT_TSF_SHIFT (0U) +#define FLEXIO_TIMSTAT_TSF(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMSTAT_TSF_SHIFT)) & FLEXIO_TIMSTAT_TSF_MASK) +/*! @} */ + +/*! @name SHIFTSIEN - Shifter Status Interrupt Enable */ +/*! @{ */ +#define FLEXIO_SHIFTSIEN_SSIE_MASK (0xFU) +#define FLEXIO_SHIFTSIEN_SSIE_SHIFT (0U) +#define FLEXIO_SHIFTSIEN_SSIE(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTSIEN_SSIE_SHIFT)) & FLEXIO_SHIFTSIEN_SSIE_MASK) +/*! @} */ + +/*! @name SHIFTEIEN - Shifter Error Interrupt Enable */ +/*! @{ */ +#define FLEXIO_SHIFTEIEN_SEIE_MASK (0xFU) +#define FLEXIO_SHIFTEIEN_SEIE_SHIFT (0U) +#define FLEXIO_SHIFTEIEN_SEIE(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTEIEN_SEIE_SHIFT)) & FLEXIO_SHIFTEIEN_SEIE_MASK) +/*! @} */ + +/*! @name TIMIEN - Timer Interrupt Enable Register */ +/*! @{ */ +#define FLEXIO_TIMIEN_TEIE_MASK (0xFU) +#define FLEXIO_TIMIEN_TEIE_SHIFT (0U) +#define FLEXIO_TIMIEN_TEIE(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMIEN_TEIE_SHIFT)) & FLEXIO_TIMIEN_TEIE_MASK) +/*! @} */ + +/*! @name SHIFTSDEN - Shifter Status DMA Enable */ +/*! @{ */ +#define FLEXIO_SHIFTSDEN_SSDE_MASK (0xFU) +#define FLEXIO_SHIFTSDEN_SSDE_SHIFT (0U) +#define FLEXIO_SHIFTSDEN_SSDE(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTSDEN_SSDE_SHIFT)) & FLEXIO_SHIFTSDEN_SSDE_MASK) +/*! @} */ + +/*! @name SHIFTSTATE - Shifter State Register */ +/*! @{ */ +#define FLEXIO_SHIFTSTATE_STATE_MASK (0x7U) +#define FLEXIO_SHIFTSTATE_STATE_SHIFT (0U) +#define FLEXIO_SHIFTSTATE_STATE(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTSTATE_STATE_SHIFT)) & FLEXIO_SHIFTSTATE_STATE_MASK) +/*! @} */ + +/*! @name SHIFTCTL - Shifter Control N Register */ +/*! @{ */ +#define FLEXIO_SHIFTCTL_SMOD_MASK (0x7U) +#define FLEXIO_SHIFTCTL_SMOD_SHIFT (0U) +/*! SMOD - Shifter Mode + * 0b000..Disabled. + * 0b001..Receive mode. Captures the current Shifter content into the SHIFTBUF on expiration of the Timer. + * 0b010..Transmit mode. Load SHIFTBUF contents into the Shifter on expiration of the Timer. + * 0b011..Reserved. + * 0b100..Match Store mode. Shifter data is compared to SHIFTBUF content on expiration of the Timer. + * 0b101..Match Continuous mode. Shifter data is continuously compared to SHIFTBUF contents. + * 0b110..State mode. SHIFTBUF contents are used for storing programmable state attributes. + * 0b111..Logic mode. SHIFTBUF contents are used for implementing programmable logic look up table. + */ +#define FLEXIO_SHIFTCTL_SMOD(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCTL_SMOD_SHIFT)) & FLEXIO_SHIFTCTL_SMOD_MASK) +#define FLEXIO_SHIFTCTL_PINPOL_MASK (0x80U) +#define FLEXIO_SHIFTCTL_PINPOL_SHIFT (7U) +/*! PINPOL - Shifter Pin Polarity + * 0b0..Pin is active high + * 0b1..Pin is active low + */ +#define FLEXIO_SHIFTCTL_PINPOL(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCTL_PINPOL_SHIFT)) & FLEXIO_SHIFTCTL_PINPOL_MASK) +#define FLEXIO_SHIFTCTL_PINSEL_MASK (0x1F00U) +#define FLEXIO_SHIFTCTL_PINSEL_SHIFT (8U) +#define FLEXIO_SHIFTCTL_PINSEL(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCTL_PINSEL_SHIFT)) & FLEXIO_SHIFTCTL_PINSEL_MASK) +#define FLEXIO_SHIFTCTL_PINCFG_MASK (0x30000U) +#define FLEXIO_SHIFTCTL_PINCFG_SHIFT (16U) +/*! PINCFG - Shifter Pin Configuration + * 0b00..Shifter pin output disabled + * 0b01..Shifter pin open drain or bidirectional output enable + * 0b10..Shifter pin bidirectional output data + * 0b11..Shifter pin output + */ +#define FLEXIO_SHIFTCTL_PINCFG(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCTL_PINCFG_SHIFT)) & FLEXIO_SHIFTCTL_PINCFG_MASK) +#define FLEXIO_SHIFTCTL_TIMPOL_MASK (0x800000U) +#define FLEXIO_SHIFTCTL_TIMPOL_SHIFT (23U) +/*! TIMPOL - Timer Polarity + * 0b0..Shift on posedge of Shift clock + * 0b1..Shift on negedge of Shift clock + */ +#define FLEXIO_SHIFTCTL_TIMPOL(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCTL_TIMPOL_SHIFT)) & FLEXIO_SHIFTCTL_TIMPOL_MASK) +#define FLEXIO_SHIFTCTL_TIMSEL_MASK (0x3000000U) +#define FLEXIO_SHIFTCTL_TIMSEL_SHIFT (24U) +#define FLEXIO_SHIFTCTL_TIMSEL(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCTL_TIMSEL_SHIFT)) & FLEXIO_SHIFTCTL_TIMSEL_MASK) +/*! @} */ + +/* The count of FLEXIO_SHIFTCTL */ +#define FLEXIO_SHIFTCTL_COUNT (4U) + +/*! @name SHIFTCFG - Shifter Configuration N Register */ +/*! @{ */ +#define FLEXIO_SHIFTCFG_SSTART_MASK (0x3U) +#define FLEXIO_SHIFTCFG_SSTART_SHIFT (0U) +/*! SSTART - Shifter Start bit + * 0b00..Start bit disabled for transmitter/receiver/match store, transmitter loads data on enable + * 0b01..Start bit disabled for transmitter/receiver/match store, transmitter loads data on first shift + * 0b10..Transmitter outputs start bit value 0 before loading data on first shift, receiver/match store sets error flag if start bit is not 0 + * 0b11..Transmitter outputs start bit value 1 before loading data on first shift, receiver/match store sets error flag if start bit is not 1 + */ +#define FLEXIO_SHIFTCFG_SSTART(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCFG_SSTART_SHIFT)) & FLEXIO_SHIFTCFG_SSTART_MASK) +#define FLEXIO_SHIFTCFG_SSTOP_MASK (0x30U) +#define FLEXIO_SHIFTCFG_SSTOP_SHIFT (4U) +/*! SSTOP - Shifter Stop bit + * 0b00..Stop bit disabled for transmitter/receiver/match store + * 0b01..Reserved for transmitter/receiver/match store + * 0b10..Transmitter outputs stop bit value 0 on store, receiver/match store sets error flag if stop bit is not 0 + * 0b11..Transmitter outputs stop bit value 1 on store, receiver/match store sets error flag if stop bit is not 1 + */ +#define FLEXIO_SHIFTCFG_SSTOP(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCFG_SSTOP_SHIFT)) & FLEXIO_SHIFTCFG_SSTOP_MASK) +#define FLEXIO_SHIFTCFG_INSRC_MASK (0x100U) +#define FLEXIO_SHIFTCFG_INSRC_SHIFT (8U) +/*! INSRC - Input Source + * 0b0..Pin + * 0b1..Shifter N+1 Output + */ +#define FLEXIO_SHIFTCFG_INSRC(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCFG_INSRC_SHIFT)) & FLEXIO_SHIFTCFG_INSRC_MASK) +#define FLEXIO_SHIFTCFG_PWIDTH_MASK (0x1F0000U) +#define FLEXIO_SHIFTCFG_PWIDTH_SHIFT (16U) +#define FLEXIO_SHIFTCFG_PWIDTH(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCFG_PWIDTH_SHIFT)) & FLEXIO_SHIFTCFG_PWIDTH_MASK) +/*! @} */ + +/* The count of FLEXIO_SHIFTCFG */ +#define FLEXIO_SHIFTCFG_COUNT (4U) + +/*! @name SHIFTBUF - Shifter Buffer N Register */ +/*! @{ */ +#define FLEXIO_SHIFTBUF_SHIFTBUF_MASK (0xFFFFFFFFU) +#define FLEXIO_SHIFTBUF_SHIFTBUF_SHIFT (0U) +#define FLEXIO_SHIFTBUF_SHIFTBUF(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUF_SHIFTBUF_SHIFT)) & FLEXIO_SHIFTBUF_SHIFTBUF_MASK) +/*! @} */ + +/* The count of FLEXIO_SHIFTBUF */ +#define FLEXIO_SHIFTBUF_COUNT (4U) + +/*! @name SHIFTBUFBIS - Shifter Buffer N Bit Swapped Register */ +/*! @{ */ +#define FLEXIO_SHIFTBUFBIS_SHIFTBUFBIS_MASK (0xFFFFFFFFU) +#define FLEXIO_SHIFTBUFBIS_SHIFTBUFBIS_SHIFT (0U) +#define FLEXIO_SHIFTBUFBIS_SHIFTBUFBIS(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUFBIS_SHIFTBUFBIS_SHIFT)) & FLEXIO_SHIFTBUFBIS_SHIFTBUFBIS_MASK) +/*! @} */ + +/* The count of FLEXIO_SHIFTBUFBIS */ +#define FLEXIO_SHIFTBUFBIS_COUNT (4U) + +/*! @name SHIFTBUFBYS - Shifter Buffer N Byte Swapped Register */ +/*! @{ */ +#define FLEXIO_SHIFTBUFBYS_SHIFTBUFBYS_MASK (0xFFFFFFFFU) +#define FLEXIO_SHIFTBUFBYS_SHIFTBUFBYS_SHIFT (0U) +#define FLEXIO_SHIFTBUFBYS_SHIFTBUFBYS(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUFBYS_SHIFTBUFBYS_SHIFT)) & FLEXIO_SHIFTBUFBYS_SHIFTBUFBYS_MASK) +/*! @} */ + +/* The count of FLEXIO_SHIFTBUFBYS */ +#define FLEXIO_SHIFTBUFBYS_COUNT (4U) + +/*! @name SHIFTBUFBBS - Shifter Buffer N Bit Byte Swapped Register */ +/*! @{ */ +#define FLEXIO_SHIFTBUFBBS_SHIFTBUFBBS_MASK (0xFFFFFFFFU) +#define FLEXIO_SHIFTBUFBBS_SHIFTBUFBBS_SHIFT (0U) +#define FLEXIO_SHIFTBUFBBS_SHIFTBUFBBS(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUFBBS_SHIFTBUFBBS_SHIFT)) & FLEXIO_SHIFTBUFBBS_SHIFTBUFBBS_MASK) +/*! @} */ + +/* The count of FLEXIO_SHIFTBUFBBS */ +#define FLEXIO_SHIFTBUFBBS_COUNT (4U) + +/*! @name TIMCTL - Timer Control N Register */ +/*! @{ */ +#define FLEXIO_TIMCTL_TIMOD_MASK (0x3U) +#define FLEXIO_TIMCTL_TIMOD_SHIFT (0U) +/*! TIMOD - Timer Mode + * 0b00..Timer Disabled. + * 0b01..Dual 8-bit counters baud mode. + * 0b10..Dual 8-bit counters PWM high mode. + * 0b11..Single 16-bit counter mode. + */ +#define FLEXIO_TIMCTL_TIMOD(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_TIMOD_SHIFT)) & FLEXIO_TIMCTL_TIMOD_MASK) +#define FLEXIO_TIMCTL_PINPOL_MASK (0x80U) +#define FLEXIO_TIMCTL_PINPOL_SHIFT (7U) +/*! PINPOL - Timer Pin Polarity + * 0b0..Pin is active high + * 0b1..Pin is active low + */ +#define FLEXIO_TIMCTL_PINPOL(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_PINPOL_SHIFT)) & FLEXIO_TIMCTL_PINPOL_MASK) +#define FLEXIO_TIMCTL_PINSEL_MASK (0x1F00U) +#define FLEXIO_TIMCTL_PINSEL_SHIFT (8U) +#define FLEXIO_TIMCTL_PINSEL(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_PINSEL_SHIFT)) & FLEXIO_TIMCTL_PINSEL_MASK) +#define FLEXIO_TIMCTL_PINCFG_MASK (0x30000U) +#define FLEXIO_TIMCTL_PINCFG_SHIFT (16U) +/*! PINCFG - Timer Pin Configuration + * 0b00..Timer pin output disabled + * 0b01..Timer pin open drain or bidirectional output enable + * 0b10..Timer pin bidirectional output data + * 0b11..Timer pin output + */ +#define FLEXIO_TIMCTL_PINCFG(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_PINCFG_SHIFT)) & FLEXIO_TIMCTL_PINCFG_MASK) +#define FLEXIO_TIMCTL_TRGSRC_MASK (0x400000U) +#define FLEXIO_TIMCTL_TRGSRC_SHIFT (22U) +/*! TRGSRC - Trigger Source + * 0b0..External trigger selected + * 0b1..Internal trigger selected + */ +#define FLEXIO_TIMCTL_TRGSRC(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_TRGSRC_SHIFT)) & FLEXIO_TIMCTL_TRGSRC_MASK) +#define FLEXIO_TIMCTL_TRGPOL_MASK (0x800000U) +#define FLEXIO_TIMCTL_TRGPOL_SHIFT (23U) +/*! TRGPOL - Trigger Polarity + * 0b0..Trigger active high + * 0b1..Trigger active low + */ +#define FLEXIO_TIMCTL_TRGPOL(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_TRGPOL_SHIFT)) & FLEXIO_TIMCTL_TRGPOL_MASK) +#define FLEXIO_TIMCTL_TRGSEL_MASK (0x3F000000U) +#define FLEXIO_TIMCTL_TRGSEL_SHIFT (24U) +#define FLEXIO_TIMCTL_TRGSEL(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_TRGSEL_SHIFT)) & FLEXIO_TIMCTL_TRGSEL_MASK) +/*! @} */ + +/* The count of FLEXIO_TIMCTL */ +#define FLEXIO_TIMCTL_COUNT (4U) + +/*! @name TIMCFG - Timer Configuration N Register */ +/*! @{ */ +#define FLEXIO_TIMCFG_TSTART_MASK (0x2U) +#define FLEXIO_TIMCFG_TSTART_SHIFT (1U) +/*! TSTART - Timer Start Bit + * 0b0..Start bit disabled + * 0b1..Start bit enabled + */ +#define FLEXIO_TIMCFG_TSTART(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TSTART_SHIFT)) & FLEXIO_TIMCFG_TSTART_MASK) +#define FLEXIO_TIMCFG_TSTOP_MASK (0x30U) +#define FLEXIO_TIMCFG_TSTOP_SHIFT (4U) +/*! TSTOP - Timer Stop Bit + * 0b00..Stop bit disabled + * 0b01..Stop bit is enabled on timer compare + * 0b10..Stop bit is enabled on timer disable + * 0b11..Stop bit is enabled on timer compare and timer disable + */ +#define FLEXIO_TIMCFG_TSTOP(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TSTOP_SHIFT)) & FLEXIO_TIMCFG_TSTOP_MASK) +#define FLEXIO_TIMCFG_TIMENA_MASK (0x700U) +#define FLEXIO_TIMCFG_TIMENA_SHIFT (8U) +/*! TIMENA - Timer Enable + * 0b000..Timer always enabled + * 0b001..Timer enabled on Timer N-1 enable + * 0b010..Timer enabled on Trigger high + * 0b011..Timer enabled on Trigger high and Pin high + * 0b100..Timer enabled on Pin rising edge + * 0b101..Timer enabled on Pin rising edge and Trigger high + * 0b110..Timer enabled on Trigger rising edge + * 0b111..Timer enabled on Trigger rising or falling edge + */ +#define FLEXIO_TIMCFG_TIMENA(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TIMENA_SHIFT)) & FLEXIO_TIMCFG_TIMENA_MASK) +#define FLEXIO_TIMCFG_TIMDIS_MASK (0x7000U) +#define FLEXIO_TIMCFG_TIMDIS_SHIFT (12U) +/*! TIMDIS - Timer Disable + * 0b000..Timer never disabled + * 0b001..Timer disabled on Timer N-1 disable + * 0b010..Timer disabled on Timer compare (upper 8-bits match and decrement) + * 0b011..Timer disabled on Timer compare (upper 8-bits match and decrement) and Trigger Low + * 0b100..Timer disabled on Pin rising or falling edge + * 0b101..Timer disabled on Pin rising or falling edge provided Trigger is high + * 0b110..Timer disabled on Trigger falling edge + * 0b111..Reserved + */ +#define FLEXIO_TIMCFG_TIMDIS(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TIMDIS_SHIFT)) & FLEXIO_TIMCFG_TIMDIS_MASK) +#define FLEXIO_TIMCFG_TIMRST_MASK (0x70000U) +#define FLEXIO_TIMCFG_TIMRST_SHIFT (16U) +/*! TIMRST - Timer Reset + * 0b000..Timer never reset + * 0b001..Reserved + * 0b010..Timer reset on Timer Pin equal to Timer Output + * 0b011..Timer reset on Timer Trigger equal to Timer Output + * 0b100..Timer reset on Timer Pin rising edge + * 0b101..Reserved + * 0b110..Timer reset on Trigger rising edge + * 0b111..Timer reset on Trigger rising or falling edge + */ +#define FLEXIO_TIMCFG_TIMRST(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TIMRST_SHIFT)) & FLEXIO_TIMCFG_TIMRST_MASK) +#define FLEXIO_TIMCFG_TIMDEC_MASK (0x300000U) +#define FLEXIO_TIMCFG_TIMDEC_SHIFT (20U) +/*! TIMDEC - Timer Decrement + * 0b00..Decrement counter on FlexIO clock, Shift clock equals Timer output. + * 0b01..Decrement counter on Trigger input (both edges), Shift clock equals Timer output. + * 0b10..Decrement counter on Pin input (both edges), Shift clock equals Pin input. + * 0b11..Decrement counter on Trigger input (both edges), Shift clock equals Trigger input. + */ +#define FLEXIO_TIMCFG_TIMDEC(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TIMDEC_SHIFT)) & FLEXIO_TIMCFG_TIMDEC_MASK) +#define FLEXIO_TIMCFG_TIMOUT_MASK (0x3000000U) +#define FLEXIO_TIMCFG_TIMOUT_SHIFT (24U) +/*! TIMOUT - Timer Output + * 0b00..Timer output is logic one when enabled and is not affected by timer reset + * 0b01..Timer output is logic zero when enabled and is not affected by timer reset + * 0b10..Timer output is logic one when enabled and on timer reset + * 0b11..Timer output is logic zero when enabled and on timer reset + */ +#define FLEXIO_TIMCFG_TIMOUT(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TIMOUT_SHIFT)) & FLEXIO_TIMCFG_TIMOUT_MASK) +/*! @} */ + +/* The count of FLEXIO_TIMCFG */ +#define FLEXIO_TIMCFG_COUNT (4U) + +/*! @name TIMCMP - Timer Compare N Register */ +/*! @{ */ +#define FLEXIO_TIMCMP_CMP_MASK (0xFFFFU) +#define FLEXIO_TIMCMP_CMP_SHIFT (0U) +#define FLEXIO_TIMCMP_CMP(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCMP_CMP_SHIFT)) & FLEXIO_TIMCMP_CMP_MASK) +/*! @} */ + +/* The count of FLEXIO_TIMCMP */ +#define FLEXIO_TIMCMP_COUNT (4U) + +/*! @name SHIFTBUFNBS - Shifter Buffer N Nibble Byte Swapped Register */ +/*! @{ */ +#define FLEXIO_SHIFTBUFNBS_SHIFTBUFNBS_MASK (0xFFFFFFFFU) +#define FLEXIO_SHIFTBUFNBS_SHIFTBUFNBS_SHIFT (0U) +#define FLEXIO_SHIFTBUFNBS_SHIFTBUFNBS(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUFNBS_SHIFTBUFNBS_SHIFT)) & FLEXIO_SHIFTBUFNBS_SHIFTBUFNBS_MASK) +/*! @} */ + +/* The count of FLEXIO_SHIFTBUFNBS */ +#define FLEXIO_SHIFTBUFNBS_COUNT (4U) + +/*! @name SHIFTBUFHWS - Shifter Buffer N Half Word Swapped Register */ +/*! @{ */ +#define FLEXIO_SHIFTBUFHWS_SHIFTBUFHWS_MASK (0xFFFFFFFFU) +#define FLEXIO_SHIFTBUFHWS_SHIFTBUFHWS_SHIFT (0U) +#define FLEXIO_SHIFTBUFHWS_SHIFTBUFHWS(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUFHWS_SHIFTBUFHWS_SHIFT)) & FLEXIO_SHIFTBUFHWS_SHIFTBUFHWS_MASK) +/*! @} */ + +/* The count of FLEXIO_SHIFTBUFHWS */ +#define FLEXIO_SHIFTBUFHWS_COUNT (4U) + +/*! @name SHIFTBUFNIS - Shifter Buffer N Nibble Swapped Register */ +/*! @{ */ +#define FLEXIO_SHIFTBUFNIS_SHIFTBUFNIS_MASK (0xFFFFFFFFU) +#define FLEXIO_SHIFTBUFNIS_SHIFTBUFNIS_SHIFT (0U) +#define FLEXIO_SHIFTBUFNIS_SHIFTBUFNIS(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUFNIS_SHIFTBUFNIS_SHIFT)) & FLEXIO_SHIFTBUFNIS_SHIFTBUFNIS_MASK) +/*! @} */ + +/* The count of FLEXIO_SHIFTBUFNIS */ +#define FLEXIO_SHIFTBUFNIS_COUNT (4U) + + +/*! + * @} + */ /* end of group FLEXIO_Register_Masks */ + + +/* FLEXIO - Peripheral instance base addresses */ +/** Peripheral FLEXIO1 base address */ +#define FLEXIO1_BASE (0x401AC000u) +/** Peripheral FLEXIO1 base pointer */ +#define FLEXIO1 ((FLEXIO_Type *)FLEXIO1_BASE) +/** Peripheral FLEXIO2 base address */ +#define FLEXIO2_BASE (0x401B0000u) +/** Peripheral FLEXIO2 base pointer */ +#define FLEXIO2 ((FLEXIO_Type *)FLEXIO2_BASE) +/** Array initializer of FLEXIO peripheral base addresses */ +#define FLEXIO_BASE_ADDRS { 0u, FLEXIO1_BASE, FLEXIO2_BASE } +/** Array initializer of FLEXIO peripheral base pointers */ +#define FLEXIO_BASE_PTRS { (FLEXIO_Type *)0u, FLEXIO1, FLEXIO2 } +/** Interrupt vectors for the FLEXIO peripheral type */ +#define FLEXIO_IRQS { NotAvail_IRQn, FLEXIO1_IRQn, FLEXIO2_IRQn } + +/*! + * @} + */ /* end of group FLEXIO_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- FLEXRAM Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup FLEXRAM_Peripheral_Access_Layer FLEXRAM Peripheral Access Layer + * @{ + */ + +/** FLEXRAM - Register Layout Typedef */ +typedef struct { + __IO uint32_t TCM_CTRL; /**< TCM CRTL Register, offset: 0x0 */ + uint8_t RESERVED_0[12]; + __IO uint32_t INT_STATUS; /**< Interrupt Status Register, offset: 0x10 */ + __IO uint32_t INT_STAT_EN; /**< Interrupt Status Enable Register, offset: 0x14 */ + __IO uint32_t INT_SIG_EN; /**< Interrupt Enable Register, offset: 0x18 */ +} FLEXRAM_Type; + +/* ---------------------------------------------------------------------------- + -- FLEXRAM Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup FLEXRAM_Register_Masks FLEXRAM Register Masks + * @{ + */ + +/*! @name TCM_CTRL - TCM CRTL Register */ +/*! @{ */ +#define FLEXRAM_TCM_CTRL_TCM_WWAIT_EN_MASK (0x1U) +#define FLEXRAM_TCM_CTRL_TCM_WWAIT_EN_SHIFT (0U) +/*! TCM_WWAIT_EN - TCM Write Wait Mode Enable + * 0b0..TCM write fast mode: Write RAM accesses are expected to be finished in 1-cycle. + * 0b1..TCM write wait mode: Write RAM accesses are expected to be finished in 2-cycles. + */ +#define FLEXRAM_TCM_CTRL_TCM_WWAIT_EN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_TCM_CTRL_TCM_WWAIT_EN_SHIFT)) & FLEXRAM_TCM_CTRL_TCM_WWAIT_EN_MASK) +#define FLEXRAM_TCM_CTRL_TCM_RWAIT_EN_MASK (0x2U) +#define FLEXRAM_TCM_CTRL_TCM_RWAIT_EN_SHIFT (1U) +/*! TCM_RWAIT_EN - TCM Read Wait Mode Enable + * 0b0..TCM read fast mode: Read RAM accesses are expected to be finished in 1-cycle. + * 0b1..TCM read wait mode: Read RAM accesses are expected to be finished in 2-cycles. + */ +#define FLEXRAM_TCM_CTRL_TCM_RWAIT_EN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_TCM_CTRL_TCM_RWAIT_EN_SHIFT)) & FLEXRAM_TCM_CTRL_TCM_RWAIT_EN_MASK) +#define FLEXRAM_TCM_CTRL_FORCE_CLK_ON_MASK (0x4U) +#define FLEXRAM_TCM_CTRL_FORCE_CLK_ON_SHIFT (2U) +#define FLEXRAM_TCM_CTRL_FORCE_CLK_ON(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_TCM_CTRL_FORCE_CLK_ON_SHIFT)) & FLEXRAM_TCM_CTRL_FORCE_CLK_ON_MASK) +/*! @} */ + +/*! @name INT_STATUS - Interrupt Status Register */ +/*! @{ */ +#define FLEXRAM_INT_STATUS_ITCM_ERR_STATUS_MASK (0x8U) +#define FLEXRAM_INT_STATUS_ITCM_ERR_STATUS_SHIFT (3U) +/*! ITCM_ERR_STATUS - ITCM Access Error Status + * 0b0..ITCM access error does not happen + * 0b1..ITCM access error happens. + */ +#define FLEXRAM_INT_STATUS_ITCM_ERR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_STATUS_ITCM_ERR_STATUS_SHIFT)) & FLEXRAM_INT_STATUS_ITCM_ERR_STATUS_MASK) +#define FLEXRAM_INT_STATUS_DTCM_ERR_STATUS_MASK (0x10U) +#define FLEXRAM_INT_STATUS_DTCM_ERR_STATUS_SHIFT (4U) +/*! DTCM_ERR_STATUS - DTCM Access Error Status + * 0b0..DTCM access error does not happen + * 0b1..DTCM access error happens. + */ +#define FLEXRAM_INT_STATUS_DTCM_ERR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_STATUS_DTCM_ERR_STATUS_SHIFT)) & FLEXRAM_INT_STATUS_DTCM_ERR_STATUS_MASK) +#define FLEXRAM_INT_STATUS_OCRAM_ERR_STATUS_MASK (0x20U) +#define FLEXRAM_INT_STATUS_OCRAM_ERR_STATUS_SHIFT (5U) +/*! OCRAM_ERR_STATUS - OCRAM Access Error Status + * 0b0..OCRAM access error does not happen + * 0b1..OCRAM access error happens. + */ +#define FLEXRAM_INT_STATUS_OCRAM_ERR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_STATUS_OCRAM_ERR_STATUS_SHIFT)) & FLEXRAM_INT_STATUS_OCRAM_ERR_STATUS_MASK) +/*! @} */ + +/*! @name INT_STAT_EN - Interrupt Status Enable Register */ +/*! @{ */ +#define FLEXRAM_INT_STAT_EN_ITCM_ERR_STAT_EN_MASK (0x8U) +#define FLEXRAM_INT_STAT_EN_ITCM_ERR_STAT_EN_SHIFT (3U) +/*! ITCM_ERR_STAT_EN - ITCM Access Error Status Enable + * 0b0..Masked + * 0b1..Enabled + */ +#define FLEXRAM_INT_STAT_EN_ITCM_ERR_STAT_EN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_STAT_EN_ITCM_ERR_STAT_EN_SHIFT)) & FLEXRAM_INT_STAT_EN_ITCM_ERR_STAT_EN_MASK) +#define FLEXRAM_INT_STAT_EN_DTCM_ERR_STAT_EN_MASK (0x10U) +#define FLEXRAM_INT_STAT_EN_DTCM_ERR_STAT_EN_SHIFT (4U) +/*! DTCM_ERR_STAT_EN - DTCM Access Error Status Enable + * 0b0..Masked + * 0b1..Enabled + */ +#define FLEXRAM_INT_STAT_EN_DTCM_ERR_STAT_EN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_STAT_EN_DTCM_ERR_STAT_EN_SHIFT)) & FLEXRAM_INT_STAT_EN_DTCM_ERR_STAT_EN_MASK) +#define FLEXRAM_INT_STAT_EN_OCRAM_ERR_STAT_EN_MASK (0x20U) +#define FLEXRAM_INT_STAT_EN_OCRAM_ERR_STAT_EN_SHIFT (5U) +/*! OCRAM_ERR_STAT_EN - OCRAM Access Error Status Enable + * 0b0..Masked + * 0b1..Enabled + */ +#define FLEXRAM_INT_STAT_EN_OCRAM_ERR_STAT_EN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_STAT_EN_OCRAM_ERR_STAT_EN_SHIFT)) & FLEXRAM_INT_STAT_EN_OCRAM_ERR_STAT_EN_MASK) +/*! @} */ + +/*! @name INT_SIG_EN - Interrupt Enable Register */ +/*! @{ */ +#define FLEXRAM_INT_SIG_EN_ITCM_ERR_SIG_EN_MASK (0x8U) +#define FLEXRAM_INT_SIG_EN_ITCM_ERR_SIG_EN_SHIFT (3U) +/*! ITCM_ERR_SIG_EN - ITCM Access Error Interrupt Enable + * 0b0..Masked + * 0b1..Enabled + */ +#define FLEXRAM_INT_SIG_EN_ITCM_ERR_SIG_EN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_SIG_EN_ITCM_ERR_SIG_EN_SHIFT)) & FLEXRAM_INT_SIG_EN_ITCM_ERR_SIG_EN_MASK) +#define FLEXRAM_INT_SIG_EN_DTCM_ERR_SIG_EN_MASK (0x10U) +#define FLEXRAM_INT_SIG_EN_DTCM_ERR_SIG_EN_SHIFT (4U) +/*! DTCM_ERR_SIG_EN - DTCM Access Error Interrupt Enable + * 0b0..Masked + * 0b1..Enabled + */ +#define FLEXRAM_INT_SIG_EN_DTCM_ERR_SIG_EN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_SIG_EN_DTCM_ERR_SIG_EN_SHIFT)) & FLEXRAM_INT_SIG_EN_DTCM_ERR_SIG_EN_MASK) +#define FLEXRAM_INT_SIG_EN_OCRAM_ERR_SIG_EN_MASK (0x20U) +#define FLEXRAM_INT_SIG_EN_OCRAM_ERR_SIG_EN_SHIFT (5U) +/*! OCRAM_ERR_SIG_EN - OCRAM Access Error Interrupt Enable + * 0b0..Masked + * 0b1..Enabled + */ +#define FLEXRAM_INT_SIG_EN_OCRAM_ERR_SIG_EN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_SIG_EN_OCRAM_ERR_SIG_EN_SHIFT)) & FLEXRAM_INT_SIG_EN_OCRAM_ERR_SIG_EN_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group FLEXRAM_Register_Masks */ + + +/* FLEXRAM - Peripheral instance base addresses */ +/** Peripheral FLEXRAM base address */ +#define FLEXRAM_BASE (0x400B0000u) +/** Peripheral FLEXRAM base pointer */ +#define FLEXRAM ((FLEXRAM_Type *)FLEXRAM_BASE) +/** Array initializer of FLEXRAM peripheral base addresses */ +#define FLEXRAM_BASE_ADDRS { FLEXRAM_BASE } +/** Array initializer of FLEXRAM peripheral base pointers */ +#define FLEXRAM_BASE_PTRS { FLEXRAM } +/** Interrupt vectors for the FLEXRAM peripheral type */ +#define FLEXRAM_IRQS { FLEXRAM_IRQn } + +/*! + * @} + */ /* end of group FLEXRAM_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- FLEXSPI Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup FLEXSPI_Peripheral_Access_Layer FLEXSPI Peripheral Access Layer + * @{ + */ + +/** FLEXSPI - Register Layout Typedef */ +typedef struct { + __IO uint32_t MCR0; /**< Module Control Register 0, offset: 0x0 */ + __IO uint32_t MCR1; /**< Module Control Register 1, offset: 0x4 */ + __IO uint32_t MCR2; /**< Module Control Register 2, offset: 0x8 */ + __IO uint32_t AHBCR; /**< AHB Bus Control Register, offset: 0xC */ + __IO uint32_t INTEN; /**< Interrupt Enable Register, offset: 0x10 */ + __IO uint32_t INTR; /**< Interrupt Register, offset: 0x14 */ + __IO uint32_t LUTKEY; /**< LUT Key Register, offset: 0x18 */ + __IO uint32_t LUTCR; /**< LUT Control Register, offset: 0x1C */ + __IO uint32_t AHBRXBUFCR0[4]; /**< AHB RX Buffer 0 Control Register 0..AHB RX Buffer 3 Control Register 0, array offset: 0x20, array step: 0x4 */ + uint8_t RESERVED_0[48]; + __IO uint32_t FLSHCR0[4]; /**< Flash A1 Control Register 0..Flash B2 Control Register 0, array offset: 0x60, array step: 0x4 */ + __IO uint32_t FLSHCR1[4]; /**< Flash A1 Control Register 1..Flash B2 Control Register 1, array offset: 0x70, array step: 0x4 */ + __IO uint32_t FLSHCR2[4]; /**< Flash A1 Control Register 2..Flash B2 Control Register 2, array offset: 0x80, array step: 0x4 */ + uint8_t RESERVED_1[4]; + __IO uint32_t FLSHCR4; /**< Flash Control Register 4, offset: 0x94 */ + uint8_t RESERVED_2[8]; + __IO uint32_t IPCR0; /**< IP Control Register 0, offset: 0xA0 */ + __IO uint32_t IPCR1; /**< IP Control Register 1, offset: 0xA4 */ + uint8_t RESERVED_3[8]; + __IO uint32_t IPCMD; /**< IP Command Register, offset: 0xB0 */ + uint8_t RESERVED_4[4]; + __IO uint32_t IPRXFCR; /**< IP RX FIFO Control Register, offset: 0xB8 */ + __IO uint32_t IPTXFCR; /**< IP TX FIFO Control Register, offset: 0xBC */ + __IO uint32_t DLLCR[2]; /**< DLL Control Register 0, array offset: 0xC0, array step: 0x4 */ + uint8_t RESERVED_5[24]; + __I uint32_t STS0; /**< Status Register 0, offset: 0xE0 */ + __I uint32_t STS1; /**< Status Register 1, offset: 0xE4 */ + __I uint32_t STS2; /**< Status Register 2, offset: 0xE8 */ + __I uint32_t AHBSPNDSTS; /**< AHB Suspend Status Register, offset: 0xEC */ + __I uint32_t IPRXFSTS; /**< IP RX FIFO Status Register, offset: 0xF0 */ + __I uint32_t IPTXFSTS; /**< IP TX FIFO Status Register, offset: 0xF4 */ + uint8_t RESERVED_6[8]; + __I uint32_t RFDR[32]; /**< IP RX FIFO Data Register 0..IP RX FIFO Data Register 31, array offset: 0x100, array step: 0x4 */ + __O uint32_t TFDR[32]; /**< IP TX FIFO Data Register 0..IP TX FIFO Data Register 31, array offset: 0x180, array step: 0x4 */ + __IO uint32_t LUT[64]; /**< LUT 0..LUT 63, array offset: 0x200, array step: 0x4 */ +} FLEXSPI_Type; + +/* ---------------------------------------------------------------------------- + -- FLEXSPI Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup FLEXSPI_Register_Masks FLEXSPI Register Masks + * @{ + */ + +/*! @name MCR0 - Module Control Register 0 */ +/*! @{ */ +#define FLEXSPI_MCR0_SWRESET_MASK (0x1U) +#define FLEXSPI_MCR0_SWRESET_SHIFT (0U) +#define FLEXSPI_MCR0_SWRESET(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_SWRESET_SHIFT)) & FLEXSPI_MCR0_SWRESET_MASK) +#define FLEXSPI_MCR0_MDIS_MASK (0x2U) +#define FLEXSPI_MCR0_MDIS_SHIFT (1U) +#define FLEXSPI_MCR0_MDIS(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_MDIS_SHIFT)) & FLEXSPI_MCR0_MDIS_MASK) +#define FLEXSPI_MCR0_RXCLKSRC_MASK (0x30U) +#define FLEXSPI_MCR0_RXCLKSRC_SHIFT (4U) +/*! RXCLKSRC - Sample Clock source selection for Flash Reading + * 0b00..Dummy Read strobe generated by FlexSPI Controller and loopback internally. + * 0b01..Dummy Read strobe generated by FlexSPI Controller and loopback from DQS pad. + * 0b10..Reserved + * 0b11..Flash provided Read strobe and input from DQS pad + */ +#define FLEXSPI_MCR0_RXCLKSRC(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_RXCLKSRC_SHIFT)) & FLEXSPI_MCR0_RXCLKSRC_MASK) +#define FLEXSPI_MCR0_ARDFEN_MASK (0x40U) +#define FLEXSPI_MCR0_ARDFEN_SHIFT (6U) +/*! ARDFEN - Enable AHB bus Read Access to IP RX FIFO. + * 0b0..IP RX FIFO should be read by IP Bus. AHB Bus read access to IP RX FIFO memory space will get bus error response. + * 0b1..IP RX FIFO should be read by AHB Bus. IP Bus read access to IP RX FIFO memory space will always return data zero but no bus error response. + */ +#define FLEXSPI_MCR0_ARDFEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_ARDFEN_SHIFT)) & FLEXSPI_MCR0_ARDFEN_MASK) +#define FLEXSPI_MCR0_ATDFEN_MASK (0x80U) +#define FLEXSPI_MCR0_ATDFEN_SHIFT (7U) +/*! ATDFEN - Enable AHB bus Write Access to IP TX FIFO. + * 0b0..IP TX FIFO should be written by IP Bus. AHB Bus write access to IP TX FIFO memory space will get bus error response. + * 0b1..IP TX FIFO should be written by AHB Bus. IP Bus write access to IP TX FIFO memory space will be ignored but no bus error response. + */ +#define FLEXSPI_MCR0_ATDFEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_ATDFEN_SHIFT)) & FLEXSPI_MCR0_ATDFEN_MASK) +#define FLEXSPI_MCR0_HSEN_MASK (0x800U) +#define FLEXSPI_MCR0_HSEN_SHIFT (11U) +/*! HSEN - Half Speed Serial Flash access Enable. + * 0b0..Disable divide by 2 of serial flash clock for half speed commands. + * 0b1..Enable divide by 2 of serial flash clock for half speed commands. + */ +#define FLEXSPI_MCR0_HSEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_HSEN_SHIFT)) & FLEXSPI_MCR0_HSEN_MASK) +#define FLEXSPI_MCR0_DOZEEN_MASK (0x1000U) +#define FLEXSPI_MCR0_DOZEEN_SHIFT (12U) +/*! DOZEEN - Doze mode enable bit + * 0b0..Doze mode support disabled. AHB clock and serial clock will not be gated off when there is doze mode request from system. + * 0b1..Doze mode support enabled. AHB clock and serial clock will be gated off when there is doze mode request from system. + */ +#define FLEXSPI_MCR0_DOZEEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_DOZEEN_SHIFT)) & FLEXSPI_MCR0_DOZEEN_MASK) +#define FLEXSPI_MCR0_COMBINATIONEN_MASK (0x2000U) +#define FLEXSPI_MCR0_COMBINATIONEN_SHIFT (13U) +/*! COMBINATIONEN - This bit is to support Flash Octal mode access by combining Port A and B Data pins (SIOA[3:0] and SIOB[3:0]). + * 0b0..Disable. + * 0b1..Enable. + */ +#define FLEXSPI_MCR0_COMBINATIONEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_COMBINATIONEN_SHIFT)) & FLEXSPI_MCR0_COMBINATIONEN_MASK) +#define FLEXSPI_MCR0_SCKFREERUNEN_MASK (0x4000U) +#define FLEXSPI_MCR0_SCKFREERUNEN_SHIFT (14U) +/*! SCKFREERUNEN - This bit is used to force SCK output free-running. For FPGA applications, external device may use SCK clock as reference clock to its internal PLL. If SCK free-running is enabled, data sampling with loopback clock from SCK pad is not supported (MCR0[RXCLKSRC]=2). + * 0b0..Disable. + * 0b1..Enable. + */ +#define FLEXSPI_MCR0_SCKFREERUNEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_SCKFREERUNEN_SHIFT)) & FLEXSPI_MCR0_SCKFREERUNEN_MASK) +#define FLEXSPI_MCR0_IPGRANTWAIT_MASK (0xFF0000U) +#define FLEXSPI_MCR0_IPGRANTWAIT_SHIFT (16U) +#define FLEXSPI_MCR0_IPGRANTWAIT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_IPGRANTWAIT_SHIFT)) & FLEXSPI_MCR0_IPGRANTWAIT_MASK) +#define FLEXSPI_MCR0_AHBGRANTWAIT_MASK (0xFF000000U) +#define FLEXSPI_MCR0_AHBGRANTWAIT_SHIFT (24U) +#define FLEXSPI_MCR0_AHBGRANTWAIT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_AHBGRANTWAIT_SHIFT)) & FLEXSPI_MCR0_AHBGRANTWAIT_MASK) +/*! @} */ + +/*! @name MCR1 - Module Control Register 1 */ +/*! @{ */ +#define FLEXSPI_MCR1_AHBBUSWAIT_MASK (0xFFFFU) +#define FLEXSPI_MCR1_AHBBUSWAIT_SHIFT (0U) +#define FLEXSPI_MCR1_AHBBUSWAIT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR1_AHBBUSWAIT_SHIFT)) & FLEXSPI_MCR1_AHBBUSWAIT_MASK) +#define FLEXSPI_MCR1_SEQWAIT_MASK (0xFFFF0000U) +#define FLEXSPI_MCR1_SEQWAIT_SHIFT (16U) +#define FLEXSPI_MCR1_SEQWAIT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR1_SEQWAIT_SHIFT)) & FLEXSPI_MCR1_SEQWAIT_MASK) +/*! @} */ + +/*! @name MCR2 - Module Control Register 2 */ +/*! @{ */ +#define FLEXSPI_MCR2_CLRAHBBUFOPT_MASK (0x800U) +#define FLEXSPI_MCR2_CLRAHBBUFOPT_SHIFT (11U) +/*! CLRAHBBUFOPT - This bit determines whether AHB RX Buffer and AHB TX Buffer will be cleaned automaticaly when FlexSPI returns STOP mode ACK. Software should set this bit if AHB RX Buffer or AHB TX Buffer will be powered off in STOP mode. Otherwise AHB read access after exiting STOP mode may hit AHB RX Buffer or AHB TX Buffer but their data entries are invalid. + * 0b0..AHB RX/TX Buffer will not be cleaned automatically when FlexSPI return Stop mode ACK. + * 0b1..AHB RX/TX Buffer will be cleaned automatically when FlexSPI return Stop mode ACK. + */ +#define FLEXSPI_MCR2_CLRAHBBUFOPT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR2_CLRAHBBUFOPT_SHIFT)) & FLEXSPI_MCR2_CLRAHBBUFOPT_MASK) +#define FLEXSPI_MCR2_CLRLEARNPHASE_MASK (0x4000U) +#define FLEXSPI_MCR2_CLRLEARNPHASE_SHIFT (14U) +#define FLEXSPI_MCR2_CLRLEARNPHASE(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR2_CLRLEARNPHASE_SHIFT)) & FLEXSPI_MCR2_CLRLEARNPHASE_MASK) +#define FLEXSPI_MCR2_SAMEDEVICEEN_MASK (0x8000U) +#define FLEXSPI_MCR2_SAMEDEVICEEN_SHIFT (15U) +/*! SAMEDEVICEEN - All external devices are same devices (both in types and size) for A1/A2/B1/B2. + * 0b0..In Individual mode, FLSHA1CRx/FLSHA2CRx/FLSHB1CRx/FLSHB2CRx register setting will be applied to Flash A1/A2/B1/B2 seperately. In Parallel mode, FLSHA1CRx register setting will be applied to Flash A1 and B1, FLSHA2CRx register setting will be applied to Flash A2 and B2. FLSHB1CRx/FLSHB2CRx register settings will be ignored. + * 0b1..FLSHA1CR0/FLSHA1CR1/FLSHA1CR2 register settings will be applied to Flash A1/A2/B1/B2. FLSHA2CRx/FLSHB1CRx/FLSHB2CRx will be ignored. + */ +#define FLEXSPI_MCR2_SAMEDEVICEEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR2_SAMEDEVICEEN_SHIFT)) & FLEXSPI_MCR2_SAMEDEVICEEN_MASK) +#define FLEXSPI_MCR2_SCKBDIFFOPT_MASK (0x80000U) +#define FLEXSPI_MCR2_SCKBDIFFOPT_SHIFT (19U) +/*! SCKBDIFFOPT - SCKB pad can be used as SCKA differential clock output (inverted clock to SCKA). In this case, port B flash access is not available. After change the value of this feild, MCR0[SWRESET] should be set. + * 0b1..SCKB pad is used as port A SCK inverted clock output (Differential clock to SCKA). Port B flash access is not available. + * 0b0..SCKB pad is used as port B SCK clock output. Port B flash access is available. + */ +#define FLEXSPI_MCR2_SCKBDIFFOPT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR2_SCKBDIFFOPT_SHIFT)) & FLEXSPI_MCR2_SCKBDIFFOPT_MASK) +#define FLEXSPI_MCR2_RESUMEWAIT_MASK (0xFF000000U) +#define FLEXSPI_MCR2_RESUMEWAIT_SHIFT (24U) +#define FLEXSPI_MCR2_RESUMEWAIT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR2_RESUMEWAIT_SHIFT)) & FLEXSPI_MCR2_RESUMEWAIT_MASK) +/*! @} */ + +/*! @name AHBCR - AHB Bus Control Register */ +/*! @{ */ +#define FLEXSPI_AHBCR_APAREN_MASK (0x1U) +#define FLEXSPI_AHBCR_APAREN_SHIFT (0U) +/*! APAREN - Parallel mode enabled for AHB triggered Command (both read and write) . + * 0b0..Flash will be accessed in Individual mode. + * 0b1..Flash will be accessed in Parallel mode. + */ +#define FLEXSPI_AHBCR_APAREN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBCR_APAREN_SHIFT)) & FLEXSPI_AHBCR_APAREN_MASK) +#define FLEXSPI_AHBCR_CACHABLEEN_MASK (0x8U) +#define FLEXSPI_AHBCR_CACHABLEEN_SHIFT (3U) +/*! CACHABLEEN - Enable AHB bus cachable read access support. + * 0b0..Disabled. When there is AHB bus cachable read access, FlexSPI will not check whether it hit AHB TX Buffer. + * 0b1..Enabled. When there is AHB bus cachable read access, FlexSPI will check whether it hit AHB TX Buffer first. + */ +#define FLEXSPI_AHBCR_CACHABLEEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBCR_CACHABLEEN_SHIFT)) & FLEXSPI_AHBCR_CACHABLEEN_MASK) +#define FLEXSPI_AHBCR_BUFFERABLEEN_MASK (0x10U) +#define FLEXSPI_AHBCR_BUFFERABLEEN_SHIFT (4U) +/*! BUFFERABLEEN - Enable AHB bus bufferable write access support. This field affects the last beat of AHB write access, refer for more details about AHB bufferable write. + * 0b0..Disabled. For all AHB write access (no matter bufferable or non-bufferable ), FlexSPI will return AHB Bus ready after all data is transmitted to External device and AHB command finished. + * 0b1..Enabled. For AHB bufferable write access, FlexSPI will return AHB Bus ready when the AHB command is granted by arbitrator and will not wait for AHB command finished. + */ +#define FLEXSPI_AHBCR_BUFFERABLEEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBCR_BUFFERABLEEN_SHIFT)) & FLEXSPI_AHBCR_BUFFERABLEEN_MASK) +#define FLEXSPI_AHBCR_PREFETCHEN_MASK (0x20U) +#define FLEXSPI_AHBCR_PREFETCHEN_SHIFT (5U) +#define FLEXSPI_AHBCR_PREFETCHEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBCR_PREFETCHEN_SHIFT)) & FLEXSPI_AHBCR_PREFETCHEN_MASK) +#define FLEXSPI_AHBCR_READADDROPT_MASK (0x40U) +#define FLEXSPI_AHBCR_READADDROPT_SHIFT (6U) +/*! READADDROPT - AHB Read Address option bit. This option bit is intend to remove AHB burst start address alignment limitation. + * 0b0..There is AHB read burst start address alignment limitation when flash is accessed in parallel mode or flash is wordaddressable. + * 0b1..There is no AHB read burst start address alignment limitation. FlexSPI will fetch more datas than AHB burst required to meet the alignment requirement. + */ +#define FLEXSPI_AHBCR_READADDROPT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBCR_READADDROPT_SHIFT)) & FLEXSPI_AHBCR_READADDROPT_MASK) +/*! @} */ + +/*! @name INTEN - Interrupt Enable Register */ +/*! @{ */ +#define FLEXSPI_INTEN_IPCMDDONEEN_MASK (0x1U) +#define FLEXSPI_INTEN_IPCMDDONEEN_SHIFT (0U) +#define FLEXSPI_INTEN_IPCMDDONEEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_IPCMDDONEEN_SHIFT)) & FLEXSPI_INTEN_IPCMDDONEEN_MASK) +#define FLEXSPI_INTEN_IPCMDGEEN_MASK (0x2U) +#define FLEXSPI_INTEN_IPCMDGEEN_SHIFT (1U) +#define FLEXSPI_INTEN_IPCMDGEEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_IPCMDGEEN_SHIFT)) & FLEXSPI_INTEN_IPCMDGEEN_MASK) +#define FLEXSPI_INTEN_AHBCMDGEEN_MASK (0x4U) +#define FLEXSPI_INTEN_AHBCMDGEEN_SHIFT (2U) +#define FLEXSPI_INTEN_AHBCMDGEEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_AHBCMDGEEN_SHIFT)) & FLEXSPI_INTEN_AHBCMDGEEN_MASK) +#define FLEXSPI_INTEN_IPCMDERREN_MASK (0x8U) +#define FLEXSPI_INTEN_IPCMDERREN_SHIFT (3U) +#define FLEXSPI_INTEN_IPCMDERREN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_IPCMDERREN_SHIFT)) & FLEXSPI_INTEN_IPCMDERREN_MASK) +#define FLEXSPI_INTEN_AHBCMDERREN_MASK (0x10U) +#define FLEXSPI_INTEN_AHBCMDERREN_SHIFT (4U) +#define FLEXSPI_INTEN_AHBCMDERREN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_AHBCMDERREN_SHIFT)) & FLEXSPI_INTEN_AHBCMDERREN_MASK) +#define FLEXSPI_INTEN_IPRXWAEN_MASK (0x20U) +#define FLEXSPI_INTEN_IPRXWAEN_SHIFT (5U) +#define FLEXSPI_INTEN_IPRXWAEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_IPRXWAEN_SHIFT)) & FLEXSPI_INTEN_IPRXWAEN_MASK) +#define FLEXSPI_INTEN_IPTXWEEN_MASK (0x40U) +#define FLEXSPI_INTEN_IPTXWEEN_SHIFT (6U) +#define FLEXSPI_INTEN_IPTXWEEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_IPTXWEEN_SHIFT)) & FLEXSPI_INTEN_IPTXWEEN_MASK) +#define FLEXSPI_INTEN_SCKSTOPBYRDEN_MASK (0x100U) +#define FLEXSPI_INTEN_SCKSTOPBYRDEN_SHIFT (8U) +#define FLEXSPI_INTEN_SCKSTOPBYRDEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_SCKSTOPBYRDEN_SHIFT)) & FLEXSPI_INTEN_SCKSTOPBYRDEN_MASK) +#define FLEXSPI_INTEN_SCKSTOPBYWREN_MASK (0x200U) +#define FLEXSPI_INTEN_SCKSTOPBYWREN_SHIFT (9U) +#define FLEXSPI_INTEN_SCKSTOPBYWREN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_SCKSTOPBYWREN_SHIFT)) & FLEXSPI_INTEN_SCKSTOPBYWREN_MASK) +#define FLEXSPI_INTEN_AHBBUSTIMEOUTEN_MASK (0x400U) +#define FLEXSPI_INTEN_AHBBUSTIMEOUTEN_SHIFT (10U) +#define FLEXSPI_INTEN_AHBBUSTIMEOUTEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_AHBBUSTIMEOUTEN_SHIFT)) & FLEXSPI_INTEN_AHBBUSTIMEOUTEN_MASK) +#define FLEXSPI_INTEN_SEQTIMEOUTEN_MASK (0x800U) +#define FLEXSPI_INTEN_SEQTIMEOUTEN_SHIFT (11U) +#define FLEXSPI_INTEN_SEQTIMEOUTEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_SEQTIMEOUTEN_SHIFT)) & FLEXSPI_INTEN_SEQTIMEOUTEN_MASK) +/*! @} */ + +/*! @name INTR - Interrupt Register */ +/*! @{ */ +#define FLEXSPI_INTR_IPCMDDONE_MASK (0x1U) +#define FLEXSPI_INTR_IPCMDDONE_SHIFT (0U) +#define FLEXSPI_INTR_IPCMDDONE(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_IPCMDDONE_SHIFT)) & FLEXSPI_INTR_IPCMDDONE_MASK) +#define FLEXSPI_INTR_IPCMDGE_MASK (0x2U) +#define FLEXSPI_INTR_IPCMDGE_SHIFT (1U) +#define FLEXSPI_INTR_IPCMDGE(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_IPCMDGE_SHIFT)) & FLEXSPI_INTR_IPCMDGE_MASK) +#define FLEXSPI_INTR_AHBCMDGE_MASK (0x4U) +#define FLEXSPI_INTR_AHBCMDGE_SHIFT (2U) +#define FLEXSPI_INTR_AHBCMDGE(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_AHBCMDGE_SHIFT)) & FLEXSPI_INTR_AHBCMDGE_MASK) +#define FLEXSPI_INTR_IPCMDERR_MASK (0x8U) +#define FLEXSPI_INTR_IPCMDERR_SHIFT (3U) +#define FLEXSPI_INTR_IPCMDERR(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_IPCMDERR_SHIFT)) & FLEXSPI_INTR_IPCMDERR_MASK) +#define FLEXSPI_INTR_AHBCMDERR_MASK (0x10U) +#define FLEXSPI_INTR_AHBCMDERR_SHIFT (4U) +#define FLEXSPI_INTR_AHBCMDERR(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_AHBCMDERR_SHIFT)) & FLEXSPI_INTR_AHBCMDERR_MASK) +#define FLEXSPI_INTR_IPRXWA_MASK (0x20U) +#define FLEXSPI_INTR_IPRXWA_SHIFT (5U) +#define FLEXSPI_INTR_IPRXWA(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_IPRXWA_SHIFT)) & FLEXSPI_INTR_IPRXWA_MASK) +#define FLEXSPI_INTR_IPTXWE_MASK (0x40U) +#define FLEXSPI_INTR_IPTXWE_SHIFT (6U) +#define FLEXSPI_INTR_IPTXWE(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_IPTXWE_SHIFT)) & FLEXSPI_INTR_IPTXWE_MASK) +#define FLEXSPI_INTR_SCKSTOPBYRD_MASK (0x100U) +#define FLEXSPI_INTR_SCKSTOPBYRD_SHIFT (8U) +#define FLEXSPI_INTR_SCKSTOPBYRD(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_SCKSTOPBYRD_SHIFT)) & FLEXSPI_INTR_SCKSTOPBYRD_MASK) +#define FLEXSPI_INTR_SCKSTOPBYWR_MASK (0x200U) +#define FLEXSPI_INTR_SCKSTOPBYWR_SHIFT (9U) +#define FLEXSPI_INTR_SCKSTOPBYWR(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_SCKSTOPBYWR_SHIFT)) & FLEXSPI_INTR_SCKSTOPBYWR_MASK) +#define FLEXSPI_INTR_AHBBUSTIMEOUT_MASK (0x400U) +#define FLEXSPI_INTR_AHBBUSTIMEOUT_SHIFT (10U) +#define FLEXSPI_INTR_AHBBUSTIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_AHBBUSTIMEOUT_SHIFT)) & FLEXSPI_INTR_AHBBUSTIMEOUT_MASK) +#define FLEXSPI_INTR_SEQTIMEOUT_MASK (0x800U) +#define FLEXSPI_INTR_SEQTIMEOUT_SHIFT (11U) +#define FLEXSPI_INTR_SEQTIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_SEQTIMEOUT_SHIFT)) & FLEXSPI_INTR_SEQTIMEOUT_MASK) +/*! @} */ + +/*! @name LUTKEY - LUT Key Register */ +/*! @{ */ +#define FLEXSPI_LUTKEY_KEY_MASK (0xFFFFFFFFU) +#define FLEXSPI_LUTKEY_KEY_SHIFT (0U) +#define FLEXSPI_LUTKEY_KEY(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUTKEY_KEY_SHIFT)) & FLEXSPI_LUTKEY_KEY_MASK) +/*! @} */ + +/*! @name LUTCR - LUT Control Register */ +/*! @{ */ +#define FLEXSPI_LUTCR_LOCK_MASK (0x1U) +#define FLEXSPI_LUTCR_LOCK_SHIFT (0U) +#define FLEXSPI_LUTCR_LOCK(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUTCR_LOCK_SHIFT)) & FLEXSPI_LUTCR_LOCK_MASK) +#define FLEXSPI_LUTCR_UNLOCK_MASK (0x2U) +#define FLEXSPI_LUTCR_UNLOCK_SHIFT (1U) +#define FLEXSPI_LUTCR_UNLOCK(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUTCR_UNLOCK_SHIFT)) & FLEXSPI_LUTCR_UNLOCK_MASK) +/*! @} */ + +/*! @name AHBRXBUFCR0 - AHB RX Buffer 0 Control Register 0..AHB RX Buffer 3 Control Register 0 */ +/*! @{ */ +#define FLEXSPI_AHBRXBUFCR0_BUFSZ_MASK (0xFFU) +#define FLEXSPI_AHBRXBUFCR0_BUFSZ_SHIFT (0U) +#define FLEXSPI_AHBRXBUFCR0_BUFSZ(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBRXBUFCR0_BUFSZ_SHIFT)) & FLEXSPI_AHBRXBUFCR0_BUFSZ_MASK) +#define FLEXSPI_AHBRXBUFCR0_MSTRID_MASK (0xF0000U) +#define FLEXSPI_AHBRXBUFCR0_MSTRID_SHIFT (16U) +#define FLEXSPI_AHBRXBUFCR0_MSTRID(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBRXBUFCR0_MSTRID_SHIFT)) & FLEXSPI_AHBRXBUFCR0_MSTRID_MASK) +#define FLEXSPI_AHBRXBUFCR0_PRIORITY_MASK (0x3000000U) +#define FLEXSPI_AHBRXBUFCR0_PRIORITY_SHIFT (24U) +#define FLEXSPI_AHBRXBUFCR0_PRIORITY(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBRXBUFCR0_PRIORITY_SHIFT)) & FLEXSPI_AHBRXBUFCR0_PRIORITY_MASK) +#define FLEXSPI_AHBRXBUFCR0_PREFETCHEN_MASK (0x80000000U) +#define FLEXSPI_AHBRXBUFCR0_PREFETCHEN_SHIFT (31U) +#define FLEXSPI_AHBRXBUFCR0_PREFETCHEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBRXBUFCR0_PREFETCHEN_SHIFT)) & FLEXSPI_AHBRXBUFCR0_PREFETCHEN_MASK) +/*! @} */ + +/* The count of FLEXSPI_AHBRXBUFCR0 */ +#define FLEXSPI_AHBRXBUFCR0_COUNT (4U) + +/*! @name FLSHCR0 - Flash A1 Control Register 0..Flash B2 Control Register 0 */ +/*! @{ */ +#define FLEXSPI_FLSHCR0_FLSHSZ_MASK (0x7FFFFFU) +#define FLEXSPI_FLSHCR0_FLSHSZ_SHIFT (0U) +#define FLEXSPI_FLSHCR0_FLSHSZ(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR0_FLSHSZ_SHIFT)) & FLEXSPI_FLSHCR0_FLSHSZ_MASK) +/*! @} */ + +/* The count of FLEXSPI_FLSHCR0 */ +#define FLEXSPI_FLSHCR0_COUNT (4U) + +/*! @name FLSHCR1 - Flash A1 Control Register 1..Flash B2 Control Register 1 */ +/*! @{ */ +#define FLEXSPI_FLSHCR1_TCSS_MASK (0x1FU) +#define FLEXSPI_FLSHCR1_TCSS_SHIFT (0U) +#define FLEXSPI_FLSHCR1_TCSS(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR1_TCSS_SHIFT)) & FLEXSPI_FLSHCR1_TCSS_MASK) +#define FLEXSPI_FLSHCR1_TCSH_MASK (0x3E0U) +#define FLEXSPI_FLSHCR1_TCSH_SHIFT (5U) +#define FLEXSPI_FLSHCR1_TCSH(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR1_TCSH_SHIFT)) & FLEXSPI_FLSHCR1_TCSH_MASK) +#define FLEXSPI_FLSHCR1_WA_MASK (0x400U) +#define FLEXSPI_FLSHCR1_WA_SHIFT (10U) +#define FLEXSPI_FLSHCR1_WA(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR1_WA_SHIFT)) & FLEXSPI_FLSHCR1_WA_MASK) +#define FLEXSPI_FLSHCR1_CAS_MASK (0x7800U) +#define FLEXSPI_FLSHCR1_CAS_SHIFT (11U) +#define FLEXSPI_FLSHCR1_CAS(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR1_CAS_SHIFT)) & FLEXSPI_FLSHCR1_CAS_MASK) +#define FLEXSPI_FLSHCR1_CSINTERVALUNIT_MASK (0x8000U) +#define FLEXSPI_FLSHCR1_CSINTERVALUNIT_SHIFT (15U) +/*! CSINTERVALUNIT - CS interval unit + * 0b0..The CS interval unit is 1 serial clock cycle + * 0b1..The CS interval unit is 256 serial clock cycle + */ +#define FLEXSPI_FLSHCR1_CSINTERVALUNIT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR1_CSINTERVALUNIT_SHIFT)) & FLEXSPI_FLSHCR1_CSINTERVALUNIT_MASK) +#define FLEXSPI_FLSHCR1_CSINTERVAL_MASK (0xFFFF0000U) +#define FLEXSPI_FLSHCR1_CSINTERVAL_SHIFT (16U) +#define FLEXSPI_FLSHCR1_CSINTERVAL(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR1_CSINTERVAL_SHIFT)) & FLEXSPI_FLSHCR1_CSINTERVAL_MASK) +/*! @} */ + +/* The count of FLEXSPI_FLSHCR1 */ +#define FLEXSPI_FLSHCR1_COUNT (4U) + +/*! @name FLSHCR2 - Flash A1 Control Register 2..Flash B2 Control Register 2 */ +/*! @{ */ +#define FLEXSPI_FLSHCR2_ARDSEQID_MASK (0xFU) +#define FLEXSPI_FLSHCR2_ARDSEQID_SHIFT (0U) +#define FLEXSPI_FLSHCR2_ARDSEQID(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR2_ARDSEQID_SHIFT)) & FLEXSPI_FLSHCR2_ARDSEQID_MASK) +#define FLEXSPI_FLSHCR2_ARDSEQNUM_MASK (0xE0U) +#define FLEXSPI_FLSHCR2_ARDSEQNUM_SHIFT (5U) +#define FLEXSPI_FLSHCR2_ARDSEQNUM(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR2_ARDSEQNUM_SHIFT)) & FLEXSPI_FLSHCR2_ARDSEQNUM_MASK) +#define FLEXSPI_FLSHCR2_AWRSEQID_MASK (0xF00U) +#define FLEXSPI_FLSHCR2_AWRSEQID_SHIFT (8U) +#define FLEXSPI_FLSHCR2_AWRSEQID(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR2_AWRSEQID_SHIFT)) & FLEXSPI_FLSHCR2_AWRSEQID_MASK) +#define FLEXSPI_FLSHCR2_AWRSEQNUM_MASK (0xE000U) +#define FLEXSPI_FLSHCR2_AWRSEQNUM_SHIFT (13U) +#define FLEXSPI_FLSHCR2_AWRSEQNUM(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR2_AWRSEQNUM_SHIFT)) & FLEXSPI_FLSHCR2_AWRSEQNUM_MASK) +#define FLEXSPI_FLSHCR2_AWRWAIT_MASK (0xFFF0000U) +#define FLEXSPI_FLSHCR2_AWRWAIT_SHIFT (16U) +#define FLEXSPI_FLSHCR2_AWRWAIT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR2_AWRWAIT_SHIFT)) & FLEXSPI_FLSHCR2_AWRWAIT_MASK) +#define FLEXSPI_FLSHCR2_AWRWAITUNIT_MASK (0x70000000U) +#define FLEXSPI_FLSHCR2_AWRWAITUNIT_SHIFT (28U) +/*! AWRWAITUNIT - AWRWAIT unit + * 0b000..The AWRWAIT unit is 2 ahb clock cycle + * 0b001..The AWRWAIT unit is 8 ahb clock cycle + * 0b010..The AWRWAIT unit is 32 ahb clock cycle + * 0b011..The AWRWAIT unit is 128 ahb clock cycle + * 0b100..The AWRWAIT unit is 512 ahb clock cycle + * 0b101..The AWRWAIT unit is 2048 ahb clock cycle + * 0b110..The AWRWAIT unit is 8192 ahb clock cycle + * 0b111..The AWRWAIT unit is 32768 ahb clock cycle + */ +#define FLEXSPI_FLSHCR2_AWRWAITUNIT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR2_AWRWAITUNIT_SHIFT)) & FLEXSPI_FLSHCR2_AWRWAITUNIT_MASK) +#define FLEXSPI_FLSHCR2_CLRINSTRPTR_MASK (0x80000000U) +#define FLEXSPI_FLSHCR2_CLRINSTRPTR_SHIFT (31U) +#define FLEXSPI_FLSHCR2_CLRINSTRPTR(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR2_CLRINSTRPTR_SHIFT)) & FLEXSPI_FLSHCR2_CLRINSTRPTR_MASK) +/*! @} */ + +/* The count of FLEXSPI_FLSHCR2 */ +#define FLEXSPI_FLSHCR2_COUNT (4U) + +/*! @name FLSHCR4 - Flash Control Register 4 */ +/*! @{ */ +#define FLEXSPI_FLSHCR4_WMOPT1_MASK (0x1U) +#define FLEXSPI_FLSHCR4_WMOPT1_SHIFT (0U) +/*! WMOPT1 - Write mask option bit 1. This option bit could be used to remove AHB write burst start address alignment limitation. + * 0b0..DQS pin will be used as Write Mask when writing to external device. There is no limitation on AHB write burst start address alignment when flash is accessed in individual mode. + * 0b1..DQS pin will not be used as Write Mask when writing to external device. There is limitation on AHB write burst start address alignment when flash is accessed in individual mode. + */ +#define FLEXSPI_FLSHCR4_WMOPT1(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR4_WMOPT1_SHIFT)) & FLEXSPI_FLSHCR4_WMOPT1_MASK) +#define FLEXSPI_FLSHCR4_WMENA_MASK (0x4U) +#define FLEXSPI_FLSHCR4_WMENA_SHIFT (2U) +/*! WMENA - Write mask enable bit for flash device on port A. When write mask function is needed for memory device on port A, this bit must be set. + * 0b0..Write mask is disabled, DQS(RWDS) pin will be un-driven when writing to external device. + * 0b1..Write mask is enabled, DQS(RWDS) pin will be driven by FlexSPI as write mask output when writing to external device. + */ +#define FLEXSPI_FLSHCR4_WMENA(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR4_WMENA_SHIFT)) & FLEXSPI_FLSHCR4_WMENA_MASK) +#define FLEXSPI_FLSHCR4_WMENB_MASK (0x8U) +#define FLEXSPI_FLSHCR4_WMENB_SHIFT (3U) +/*! WMENB - Write mask enable bit for flash device on port B. When write mask function is needed for memory device on port B, this bit must be set. + * 0b0..Write mask is disabled, DQS(RWDS) pin will be un-driven when writing to external device. + * 0b1..Write mask is enabled, DQS(RWDS) pin will be driven by FlexSPI as write mask output when writing to external device. + */ +#define FLEXSPI_FLSHCR4_WMENB(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR4_WMENB_SHIFT)) & FLEXSPI_FLSHCR4_WMENB_MASK) +/*! @} */ + +/*! @name IPCR0 - IP Control Register 0 */ +/*! @{ */ +#define FLEXSPI_IPCR0_SFAR_MASK (0xFFFFFFFFU) +#define FLEXSPI_IPCR0_SFAR_SHIFT (0U) +#define FLEXSPI_IPCR0_SFAR(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPCR0_SFAR_SHIFT)) & FLEXSPI_IPCR0_SFAR_MASK) +/*! @} */ + +/*! @name IPCR1 - IP Control Register 1 */ +/*! @{ */ +#define FLEXSPI_IPCR1_IDATSZ_MASK (0xFFFFU) +#define FLEXSPI_IPCR1_IDATSZ_SHIFT (0U) +#define FLEXSPI_IPCR1_IDATSZ(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPCR1_IDATSZ_SHIFT)) & FLEXSPI_IPCR1_IDATSZ_MASK) +#define FLEXSPI_IPCR1_ISEQID_MASK (0xF0000U) +#define FLEXSPI_IPCR1_ISEQID_SHIFT (16U) +#define FLEXSPI_IPCR1_ISEQID(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPCR1_ISEQID_SHIFT)) & FLEXSPI_IPCR1_ISEQID_MASK) +#define FLEXSPI_IPCR1_ISEQNUM_MASK (0x7000000U) +#define FLEXSPI_IPCR1_ISEQNUM_SHIFT (24U) +#define FLEXSPI_IPCR1_ISEQNUM(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPCR1_ISEQNUM_SHIFT)) & FLEXSPI_IPCR1_ISEQNUM_MASK) +#define FLEXSPI_IPCR1_IPAREN_MASK (0x80000000U) +#define FLEXSPI_IPCR1_IPAREN_SHIFT (31U) +/*! IPAREN - Parallel mode Enabled for IP command. + * 0b0..Flash will be accessed in Individual mode. + * 0b1..Flash will be accessed in Parallel mode. + */ +#define FLEXSPI_IPCR1_IPAREN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPCR1_IPAREN_SHIFT)) & FLEXSPI_IPCR1_IPAREN_MASK) +/*! @} */ + +/*! @name IPCMD - IP Command Register */ +/*! @{ */ +#define FLEXSPI_IPCMD_TRG_MASK (0x1U) +#define FLEXSPI_IPCMD_TRG_SHIFT (0U) +#define FLEXSPI_IPCMD_TRG(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPCMD_TRG_SHIFT)) & FLEXSPI_IPCMD_TRG_MASK) +/*! @} */ + +/*! @name IPRXFCR - IP RX FIFO Control Register */ +/*! @{ */ +#define FLEXSPI_IPRXFCR_CLRIPRXF_MASK (0x1U) +#define FLEXSPI_IPRXFCR_CLRIPRXF_SHIFT (0U) +#define FLEXSPI_IPRXFCR_CLRIPRXF(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPRXFCR_CLRIPRXF_SHIFT)) & FLEXSPI_IPRXFCR_CLRIPRXF_MASK) +#define FLEXSPI_IPRXFCR_RXDMAEN_MASK (0x2U) +#define FLEXSPI_IPRXFCR_RXDMAEN_SHIFT (1U) +/*! RXDMAEN - IP RX FIFO reading by DMA enabled. + * 0b0..IP RX FIFO would be read by processor. + * 0b1..IP RX FIFO would be read by DMA. + */ +#define FLEXSPI_IPRXFCR_RXDMAEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPRXFCR_RXDMAEN_SHIFT)) & FLEXSPI_IPRXFCR_RXDMAEN_MASK) +#define FLEXSPI_IPRXFCR_RXWMRK_MASK (0x3CU) +#define FLEXSPI_IPRXFCR_RXWMRK_SHIFT (2U) +#define FLEXSPI_IPRXFCR_RXWMRK(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPRXFCR_RXWMRK_SHIFT)) & FLEXSPI_IPRXFCR_RXWMRK_MASK) +/*! @} */ + +/*! @name IPTXFCR - IP TX FIFO Control Register */ +/*! @{ */ +#define FLEXSPI_IPTXFCR_CLRIPTXF_MASK (0x1U) +#define FLEXSPI_IPTXFCR_CLRIPTXF_SHIFT (0U) +#define FLEXSPI_IPTXFCR_CLRIPTXF(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPTXFCR_CLRIPTXF_SHIFT)) & FLEXSPI_IPTXFCR_CLRIPTXF_MASK) +#define FLEXSPI_IPTXFCR_TXDMAEN_MASK (0x2U) +#define FLEXSPI_IPTXFCR_TXDMAEN_SHIFT (1U) +/*! TXDMAEN - IP TX FIFO filling by DMA enabled. + * 0b0..IP TX FIFO would be filled by processor. + * 0b1..IP TX FIFO would be filled by DMA. + */ +#define FLEXSPI_IPTXFCR_TXDMAEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPTXFCR_TXDMAEN_SHIFT)) & FLEXSPI_IPTXFCR_TXDMAEN_MASK) +#define FLEXSPI_IPTXFCR_TXWMRK_MASK (0x3CU) +#define FLEXSPI_IPTXFCR_TXWMRK_SHIFT (2U) +#define FLEXSPI_IPTXFCR_TXWMRK(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPTXFCR_TXWMRK_SHIFT)) & FLEXSPI_IPTXFCR_TXWMRK_MASK) +/*! @} */ + +/*! @name DLLCR - DLL Control Register 0 */ +/*! @{ */ +#define FLEXSPI_DLLCR_DLLEN_MASK (0x1U) +#define FLEXSPI_DLLCR_DLLEN_SHIFT (0U) +#define FLEXSPI_DLLCR_DLLEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_DLLCR_DLLEN_SHIFT)) & FLEXSPI_DLLCR_DLLEN_MASK) +#define FLEXSPI_DLLCR_DLLRESET_MASK (0x2U) +#define FLEXSPI_DLLCR_DLLRESET_SHIFT (1U) +#define FLEXSPI_DLLCR_DLLRESET(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_DLLCR_DLLRESET_SHIFT)) & FLEXSPI_DLLCR_DLLRESET_MASK) +#define FLEXSPI_DLLCR_SLVDLYTARGET_MASK (0x78U) +#define FLEXSPI_DLLCR_SLVDLYTARGET_SHIFT (3U) +#define FLEXSPI_DLLCR_SLVDLYTARGET(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_DLLCR_SLVDLYTARGET_SHIFT)) & FLEXSPI_DLLCR_SLVDLYTARGET_MASK) +#define FLEXSPI_DLLCR_OVRDEN_MASK (0x100U) +#define FLEXSPI_DLLCR_OVRDEN_SHIFT (8U) +#define FLEXSPI_DLLCR_OVRDEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_DLLCR_OVRDEN_SHIFT)) & FLEXSPI_DLLCR_OVRDEN_MASK) +#define FLEXSPI_DLLCR_OVRDVAL_MASK (0x7E00U) +#define FLEXSPI_DLLCR_OVRDVAL_SHIFT (9U) +#define FLEXSPI_DLLCR_OVRDVAL(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_DLLCR_OVRDVAL_SHIFT)) & FLEXSPI_DLLCR_OVRDVAL_MASK) +/*! @} */ + +/* The count of FLEXSPI_DLLCR */ +#define FLEXSPI_DLLCR_COUNT (2U) + +/*! @name STS0 - Status Register 0 */ +/*! @{ */ +#define FLEXSPI_STS0_SEQIDLE_MASK (0x1U) +#define FLEXSPI_STS0_SEQIDLE_SHIFT (0U) +#define FLEXSPI_STS0_SEQIDLE(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS0_SEQIDLE_SHIFT)) & FLEXSPI_STS0_SEQIDLE_MASK) +#define FLEXSPI_STS0_ARBIDLE_MASK (0x2U) +#define FLEXSPI_STS0_ARBIDLE_SHIFT (1U) +#define FLEXSPI_STS0_ARBIDLE(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS0_ARBIDLE_SHIFT)) & FLEXSPI_STS0_ARBIDLE_MASK) +#define FLEXSPI_STS0_ARBCMDSRC_MASK (0xCU) +#define FLEXSPI_STS0_ARBCMDSRC_SHIFT (2U) +/*! ARBCMDSRC - This status field indicates the trigger source of current command sequence granted by arbitrator. This field value is meaningless when ARB_CTL is not busy (STS0[ARBIDLE]=0x1). + * 0b00..Triggered by AHB read command (triggered by AHB read). + * 0b01..Triggered by AHB write command (triggered by AHB Write). + * 0b10..Triggered by IP command (triggered by setting register bit IPCMD.TRG). + * 0b11..Triggered by suspended command (resumed). + */ +#define FLEXSPI_STS0_ARBCMDSRC(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS0_ARBCMDSRC_SHIFT)) & FLEXSPI_STS0_ARBCMDSRC_MASK) +/*! @} */ + +/*! @name STS1 - Status Register 1 */ +/*! @{ */ +#define FLEXSPI_STS1_AHBCMDERRID_MASK (0xFU) +#define FLEXSPI_STS1_AHBCMDERRID_SHIFT (0U) +#define FLEXSPI_STS1_AHBCMDERRID(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS1_AHBCMDERRID_SHIFT)) & FLEXSPI_STS1_AHBCMDERRID_MASK) +#define FLEXSPI_STS1_AHBCMDERRCODE_MASK (0xF00U) +#define FLEXSPI_STS1_AHBCMDERRCODE_SHIFT (8U) +/*! AHBCMDERRCODE - Indicates the Error Code when AHB command Error detected. This field will be cleared when INTR[AHBCMDERR] is write-1-clear(w1c). + * 0b0000..No error. + * 0b0010..AHB Write command with JMP_ON_CS instruction used in the sequence. + * 0b0011..There is unknown instruction opcode in the sequence. + * 0b0100..Instruction DUMMY_SDR/DUMMY_RWDS_SDR used in DDR sequence. + * 0b0101..Instruction DUMMY_DDR/DUMMY_RWDS_DDR used in SDR sequence. + * 0b1110..Sequence execution timeout. + */ +#define FLEXSPI_STS1_AHBCMDERRCODE(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS1_AHBCMDERRCODE_SHIFT)) & FLEXSPI_STS1_AHBCMDERRCODE_MASK) +#define FLEXSPI_STS1_IPCMDERRID_MASK (0xF0000U) +#define FLEXSPI_STS1_IPCMDERRID_SHIFT (16U) +#define FLEXSPI_STS1_IPCMDERRID(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS1_IPCMDERRID_SHIFT)) & FLEXSPI_STS1_IPCMDERRID_MASK) +#define FLEXSPI_STS1_IPCMDERRCODE_MASK (0xF000000U) +#define FLEXSPI_STS1_IPCMDERRCODE_SHIFT (24U) +/*! IPCMDERRCODE - Indicates the Error Code when IP command Error detected. This field will be cleared when INTR[IPCMDERR] is write-1-clear(w1c). + * 0b0000..No error. + * 0b0010..IP command with JMP_ON_CS instruction used in the sequence. + * 0b0011..There is unknown instruction opcode in the sequence. + * 0b0100..Instruction DUMMY_SDR/DUMMY_RWDS_SDR used in DDR sequence. + * 0b0101..Instruction DUMMY_DDR/DUMMY_RWDS_DDR used in SDR sequence. + * 0b0110..Flash access start address exceed the whole flash address range (A1/A2/B1/B2). + * 0b1110..Sequence execution timeout. + * 0b1111..Flash boundary crossed. + */ +#define FLEXSPI_STS1_IPCMDERRCODE(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS1_IPCMDERRCODE_SHIFT)) & FLEXSPI_STS1_IPCMDERRCODE_MASK) +/*! @} */ + +/*! @name STS2 - Status Register 2 */ +/*! @{ */ +#define FLEXSPI_STS2_ASLVLOCK_MASK (0x1U) +#define FLEXSPI_STS2_ASLVLOCK_SHIFT (0U) +#define FLEXSPI_STS2_ASLVLOCK(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS2_ASLVLOCK_SHIFT)) & FLEXSPI_STS2_ASLVLOCK_MASK) +#define FLEXSPI_STS2_AREFLOCK_MASK (0x2U) +#define FLEXSPI_STS2_AREFLOCK_SHIFT (1U) +#define FLEXSPI_STS2_AREFLOCK(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS2_AREFLOCK_SHIFT)) & FLEXSPI_STS2_AREFLOCK_MASK) +#define FLEXSPI_STS2_ASLVSEL_MASK (0xFCU) +#define FLEXSPI_STS2_ASLVSEL_SHIFT (2U) +#define FLEXSPI_STS2_ASLVSEL(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS2_ASLVSEL_SHIFT)) & FLEXSPI_STS2_ASLVSEL_MASK) +#define FLEXSPI_STS2_AREFSEL_MASK (0x3F00U) +#define FLEXSPI_STS2_AREFSEL_SHIFT (8U) +#define FLEXSPI_STS2_AREFSEL(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS2_AREFSEL_SHIFT)) & FLEXSPI_STS2_AREFSEL_MASK) +#define FLEXSPI_STS2_BSLVLOCK_MASK (0x10000U) +#define FLEXSPI_STS2_BSLVLOCK_SHIFT (16U) +#define FLEXSPI_STS2_BSLVLOCK(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS2_BSLVLOCK_SHIFT)) & FLEXSPI_STS2_BSLVLOCK_MASK) +#define FLEXSPI_STS2_BREFLOCK_MASK (0x20000U) +#define FLEXSPI_STS2_BREFLOCK_SHIFT (17U) +#define FLEXSPI_STS2_BREFLOCK(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS2_BREFLOCK_SHIFT)) & FLEXSPI_STS2_BREFLOCK_MASK) +#define FLEXSPI_STS2_BSLVSEL_MASK (0xFC0000U) +#define FLEXSPI_STS2_BSLVSEL_SHIFT (18U) +#define FLEXSPI_STS2_BSLVSEL(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS2_BSLVSEL_SHIFT)) & FLEXSPI_STS2_BSLVSEL_MASK) +#define FLEXSPI_STS2_BREFSEL_MASK (0x3F000000U) +#define FLEXSPI_STS2_BREFSEL_SHIFT (24U) +#define FLEXSPI_STS2_BREFSEL(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS2_BREFSEL_SHIFT)) & FLEXSPI_STS2_BREFSEL_MASK) +/*! @} */ + +/*! @name AHBSPNDSTS - AHB Suspend Status Register */ +/*! @{ */ +#define FLEXSPI_AHBSPNDSTS_ACTIVE_MASK (0x1U) +#define FLEXSPI_AHBSPNDSTS_ACTIVE_SHIFT (0U) +#define FLEXSPI_AHBSPNDSTS_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBSPNDSTS_ACTIVE_SHIFT)) & FLEXSPI_AHBSPNDSTS_ACTIVE_MASK) +#define FLEXSPI_AHBSPNDSTS_BUFID_MASK (0xEU) +#define FLEXSPI_AHBSPNDSTS_BUFID_SHIFT (1U) +#define FLEXSPI_AHBSPNDSTS_BUFID(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBSPNDSTS_BUFID_SHIFT)) & FLEXSPI_AHBSPNDSTS_BUFID_MASK) +#define FLEXSPI_AHBSPNDSTS_DATLFT_MASK (0xFFFF0000U) +#define FLEXSPI_AHBSPNDSTS_DATLFT_SHIFT (16U) +#define FLEXSPI_AHBSPNDSTS_DATLFT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBSPNDSTS_DATLFT_SHIFT)) & FLEXSPI_AHBSPNDSTS_DATLFT_MASK) +/*! @} */ + +/*! @name IPRXFSTS - IP RX FIFO Status Register */ +/*! @{ */ +#define FLEXSPI_IPRXFSTS_FILL_MASK (0xFFU) +#define FLEXSPI_IPRXFSTS_FILL_SHIFT (0U) +#define FLEXSPI_IPRXFSTS_FILL(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPRXFSTS_FILL_SHIFT)) & FLEXSPI_IPRXFSTS_FILL_MASK) +#define FLEXSPI_IPRXFSTS_RDCNTR_MASK (0xFFFF0000U) +#define FLEXSPI_IPRXFSTS_RDCNTR_SHIFT (16U) +#define FLEXSPI_IPRXFSTS_RDCNTR(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPRXFSTS_RDCNTR_SHIFT)) & FLEXSPI_IPRXFSTS_RDCNTR_MASK) +/*! @} */ + +/*! @name IPTXFSTS - IP TX FIFO Status Register */ +/*! @{ */ +#define FLEXSPI_IPTXFSTS_FILL_MASK (0xFFU) +#define FLEXSPI_IPTXFSTS_FILL_SHIFT (0U) +#define FLEXSPI_IPTXFSTS_FILL(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPTXFSTS_FILL_SHIFT)) & FLEXSPI_IPTXFSTS_FILL_MASK) +#define FLEXSPI_IPTXFSTS_WRCNTR_MASK (0xFFFF0000U) +#define FLEXSPI_IPTXFSTS_WRCNTR_SHIFT (16U) +#define FLEXSPI_IPTXFSTS_WRCNTR(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPTXFSTS_WRCNTR_SHIFT)) & FLEXSPI_IPTXFSTS_WRCNTR_MASK) +/*! @} */ + +/*! @name RFDR - IP RX FIFO Data Register 0..IP RX FIFO Data Register 31 */ +/*! @{ */ +#define FLEXSPI_RFDR_RXDATA_MASK (0xFFFFFFFFU) +#define FLEXSPI_RFDR_RXDATA_SHIFT (0U) +#define FLEXSPI_RFDR_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_RFDR_RXDATA_SHIFT)) & FLEXSPI_RFDR_RXDATA_MASK) +/*! @} */ + +/* The count of FLEXSPI_RFDR */ +#define FLEXSPI_RFDR_COUNT (32U) + +/*! @name TFDR - IP TX FIFO Data Register 0..IP TX FIFO Data Register 31 */ +/*! @{ */ +#define FLEXSPI_TFDR_TXDATA_MASK (0xFFFFFFFFU) +#define FLEXSPI_TFDR_TXDATA_SHIFT (0U) +#define FLEXSPI_TFDR_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_TFDR_TXDATA_SHIFT)) & FLEXSPI_TFDR_TXDATA_MASK) +/*! @} */ + +/* The count of FLEXSPI_TFDR */ +#define FLEXSPI_TFDR_COUNT (32U) + +/*! @name LUT - LUT 0..LUT 63 */ +/*! @{ */ +#define FLEXSPI_LUT_OPERAND0_MASK (0xFFU) +#define FLEXSPI_LUT_OPERAND0_SHIFT (0U) +#define FLEXSPI_LUT_OPERAND0(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUT_OPERAND0_SHIFT)) & FLEXSPI_LUT_OPERAND0_MASK) +#define FLEXSPI_LUT_NUM_PADS0_MASK (0x300U) +#define FLEXSPI_LUT_NUM_PADS0_SHIFT (8U) +#define FLEXSPI_LUT_NUM_PADS0(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUT_NUM_PADS0_SHIFT)) & FLEXSPI_LUT_NUM_PADS0_MASK) +#define FLEXSPI_LUT_OPCODE0_MASK (0xFC00U) +#define FLEXSPI_LUT_OPCODE0_SHIFT (10U) +#define FLEXSPI_LUT_OPCODE0(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUT_OPCODE0_SHIFT)) & FLEXSPI_LUT_OPCODE0_MASK) +#define FLEXSPI_LUT_OPERAND1_MASK (0xFF0000U) +#define FLEXSPI_LUT_OPERAND1_SHIFT (16U) +#define FLEXSPI_LUT_OPERAND1(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUT_OPERAND1_SHIFT)) & FLEXSPI_LUT_OPERAND1_MASK) +#define FLEXSPI_LUT_NUM_PADS1_MASK (0x3000000U) +#define FLEXSPI_LUT_NUM_PADS1_SHIFT (24U) +#define FLEXSPI_LUT_NUM_PADS1(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUT_NUM_PADS1_SHIFT)) & FLEXSPI_LUT_NUM_PADS1_MASK) +#define FLEXSPI_LUT_OPCODE1_MASK (0xFC000000U) +#define FLEXSPI_LUT_OPCODE1_SHIFT (26U) +#define FLEXSPI_LUT_OPCODE1(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUT_OPCODE1_SHIFT)) & FLEXSPI_LUT_OPCODE1_MASK) +/*! @} */ + +/* The count of FLEXSPI_LUT */ +#define FLEXSPI_LUT_COUNT (64U) + + +/*! + * @} + */ /* end of group FLEXSPI_Register_Masks */ + + +/* FLEXSPI - Peripheral instance base addresses */ +/** Peripheral FLEXSPI base address */ +#define FLEXSPI_BASE (0x402A8000u) +/** Peripheral FLEXSPI base pointer */ +#define FLEXSPI ((FLEXSPI_Type *)FLEXSPI_BASE) +/** Array initializer of FLEXSPI peripheral base addresses */ +#define FLEXSPI_BASE_ADDRS { FLEXSPI_BASE } +/** Array initializer of FLEXSPI peripheral base pointers */ +#define FLEXSPI_BASE_PTRS { FLEXSPI } +/** Interrupt vectors for the FLEXSPI peripheral type */ +#define FLEXSPI_IRQS { FLEXSPI_IRQn } +/* FlexSPI AMBA address. */ +#define FlexSPI_AMBA_BASE (0x60000000U) +/* FlexSPI ASFM address. */ +#define FlexSPI_ASFM_BASE (0x00000000U) +/* Base Address of AHB address space mapped to IP RX FIFO. */ +#define FlexSPI_ARDF_BASE (0x7FC00000U) +/* Base Address of AHB address space mapped to IP TX FIFO. */ +#define FlexSPI_ATDF_BASE (0x7F800000U) + + +/*! + * @} + */ /* end of group FLEXSPI_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- GPC Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup GPC_Peripheral_Access_Layer GPC Peripheral Access Layer + * @{ + */ + +/** GPC - Register Layout Typedef */ +typedef struct { + __IO uint32_t CNTR; /**< GPC Interface control register, offset: 0x0 */ + uint8_t RESERVED_0[4]; + __IO uint32_t IMR[4]; /**< IRQ masking register 1..IRQ masking register 4, array offset: 0x8, array step: 0x4 */ + __I uint32_t ISR[4]; /**< IRQ status resister 1..IRQ status resister 4, array offset: 0x18, array step: 0x4 */ + uint8_t RESERVED_1[12]; + __IO uint32_t IMR5; /**< IRQ masking register 5, offset: 0x34 */ + __I uint32_t ISR5; /**< IRQ status resister 5, offset: 0x38 */ +} GPC_Type; + +/* ---------------------------------------------------------------------------- + -- GPC Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup GPC_Register_Masks GPC Register Masks + * @{ + */ + +/*! @name CNTR - GPC Interface control register */ +/*! @{ */ +#define GPC_CNTR_MEGA_PDN_REQ_MASK (0x4U) +#define GPC_CNTR_MEGA_PDN_REQ_SHIFT (2U) +/*! MEGA_PDN_REQ + * 0b0..No Request + * 0b1..Request power down sequence + */ +#define GPC_CNTR_MEGA_PDN_REQ(x) (((uint32_t)(((uint32_t)(x)) << GPC_CNTR_MEGA_PDN_REQ_SHIFT)) & GPC_CNTR_MEGA_PDN_REQ_MASK) +#define GPC_CNTR_MEGA_PUP_REQ_MASK (0x8U) +#define GPC_CNTR_MEGA_PUP_REQ_SHIFT (3U) +/*! MEGA_PUP_REQ + * 0b0..No Request + * 0b1..Request power up sequence + */ +#define GPC_CNTR_MEGA_PUP_REQ(x) (((uint32_t)(((uint32_t)(x)) << GPC_CNTR_MEGA_PUP_REQ_SHIFT)) & GPC_CNTR_MEGA_PUP_REQ_MASK) +#define GPC_CNTR_PDRAM0_PGE_MASK (0x400000U) +#define GPC_CNTR_PDRAM0_PGE_SHIFT (22U) +/*! PDRAM0_PGE + * 0b1..FlexRAM PDRAM0 domain (bank1-7) will be power down once when CPU core is power down. + * 0b0..FlexRAM PDRAM0 domain (bank1-7) will keep power on even if CPU core is power down. + */ +#define GPC_CNTR_PDRAM0_PGE(x) (((uint32_t)(((uint32_t)(x)) << GPC_CNTR_PDRAM0_PGE_SHIFT)) & GPC_CNTR_PDRAM0_PGE_MASK) +/*! @} */ + +/*! @name IMR - IRQ masking register 1..IRQ masking register 4 */ +/*! @{ */ +#define GPC_IMR_IMR1_MASK (0xFFFFFFFFU) +#define GPC_IMR_IMR1_SHIFT (0U) +#define GPC_IMR_IMR1(x) (((uint32_t)(((uint32_t)(x)) << GPC_IMR_IMR1_SHIFT)) & GPC_IMR_IMR1_MASK) +#define GPC_IMR_IMR2_MASK (0xFFFFFFFFU) +#define GPC_IMR_IMR2_SHIFT (0U) +#define GPC_IMR_IMR2(x) (((uint32_t)(((uint32_t)(x)) << GPC_IMR_IMR2_SHIFT)) & GPC_IMR_IMR2_MASK) +#define GPC_IMR_IMR3_MASK (0xFFFFFFFFU) +#define GPC_IMR_IMR3_SHIFT (0U) +#define GPC_IMR_IMR3(x) (((uint32_t)(((uint32_t)(x)) << GPC_IMR_IMR3_SHIFT)) & GPC_IMR_IMR3_MASK) +#define GPC_IMR_IMR4_MASK (0xFFFFFFFFU) +#define GPC_IMR_IMR4_SHIFT (0U) +#define GPC_IMR_IMR4(x) (((uint32_t)(((uint32_t)(x)) << GPC_IMR_IMR4_SHIFT)) & GPC_IMR_IMR4_MASK) +/*! @} */ + +/* The count of GPC_IMR */ +#define GPC_IMR_COUNT (4U) + +/*! @name ISR - IRQ status resister 1..IRQ status resister 4 */ +/*! @{ */ +#define GPC_ISR_ISR1_MASK (0xFFFFFFFFU) +#define GPC_ISR_ISR1_SHIFT (0U) +#define GPC_ISR_ISR1(x) (((uint32_t)(((uint32_t)(x)) << GPC_ISR_ISR1_SHIFT)) & GPC_ISR_ISR1_MASK) +#define GPC_ISR_ISR2_MASK (0xFFFFFFFFU) +#define GPC_ISR_ISR2_SHIFT (0U) +#define GPC_ISR_ISR2(x) (((uint32_t)(((uint32_t)(x)) << GPC_ISR_ISR2_SHIFT)) & GPC_ISR_ISR2_MASK) +#define GPC_ISR_ISR3_MASK (0xFFFFFFFFU) +#define GPC_ISR_ISR3_SHIFT (0U) +#define GPC_ISR_ISR3(x) (((uint32_t)(((uint32_t)(x)) << GPC_ISR_ISR3_SHIFT)) & GPC_ISR_ISR3_MASK) +#define GPC_ISR_ISR4_MASK (0xFFFFFFFFU) +#define GPC_ISR_ISR4_SHIFT (0U) +#define GPC_ISR_ISR4(x) (((uint32_t)(((uint32_t)(x)) << GPC_ISR_ISR4_SHIFT)) & GPC_ISR_ISR4_MASK) +/*! @} */ + +/* The count of GPC_ISR */ +#define GPC_ISR_COUNT (4U) + +/*! @name IMR5 - IRQ masking register 5 */ +/*! @{ */ +#define GPC_IMR5_IMR5_MASK (0xFFFFFFFFU) +#define GPC_IMR5_IMR5_SHIFT (0U) +#define GPC_IMR5_IMR5(x) (((uint32_t)(((uint32_t)(x)) << GPC_IMR5_IMR5_SHIFT)) & GPC_IMR5_IMR5_MASK) +/*! @} */ + +/*! @name ISR5 - IRQ status resister 5 */ +/*! @{ */ +#define GPC_ISR5_ISR4_MASK (0xFFFFFFFFU) +#define GPC_ISR5_ISR4_SHIFT (0U) +#define GPC_ISR5_ISR4(x) (((uint32_t)(((uint32_t)(x)) << GPC_ISR5_ISR4_SHIFT)) & GPC_ISR5_ISR4_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group GPC_Register_Masks */ + + +/* GPC - Peripheral instance base addresses */ +/** Peripheral GPC base address */ +#define GPC_BASE (0x400F4000u) +/** Peripheral GPC base pointer */ +#define GPC ((GPC_Type *)GPC_BASE) +/** Array initializer of GPC peripheral base addresses */ +#define GPC_BASE_ADDRS { GPC_BASE } +/** Array initializer of GPC peripheral base pointers */ +#define GPC_BASE_PTRS { GPC } +/** Interrupt vectors for the GPC peripheral type */ +#define GPC_IRQS { GPC_IRQn } + +/*! + * @} + */ /* end of group GPC_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- GPIO Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup GPIO_Peripheral_Access_Layer GPIO Peripheral Access Layer + * @{ + */ + +/** GPIO - Register Layout Typedef */ +typedef struct { + __IO uint32_t DR; /**< GPIO data register, offset: 0x0 */ + __IO uint32_t GDIR; /**< GPIO direction register, offset: 0x4 */ + __I uint32_t PSR; /**< GPIO pad status register, offset: 0x8 */ + __IO uint32_t ICR1; /**< GPIO interrupt configuration register1, offset: 0xC */ + __IO uint32_t ICR2; /**< GPIO interrupt configuration register2, offset: 0x10 */ + __IO uint32_t IMR; /**< GPIO interrupt mask register, offset: 0x14 */ + __IO uint32_t ISR; /**< GPIO interrupt status register, offset: 0x18 */ + __IO uint32_t EDGE_SEL; /**< GPIO edge select register, offset: 0x1C */ + uint8_t RESERVED_0[100]; + __O uint32_t DR_SET; /**< GPIO data register SET, offset: 0x84 */ + __O uint32_t DR_CLEAR; /**< GPIO data register CLEAR, offset: 0x88 */ + __O uint32_t DR_TOGGLE; /**< GPIO data register TOGGLE, offset: 0x8C */ +} GPIO_Type; + +/* ---------------------------------------------------------------------------- + -- GPIO Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup GPIO_Register_Masks GPIO Register Masks + * @{ + */ + +/*! @name DR - GPIO data register */ +/*! @{ */ +#define GPIO_DR_DR_MASK (0xFFFFFFFFU) +#define GPIO_DR_DR_SHIFT (0U) +#define GPIO_DR_DR(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DR_DR_SHIFT)) & GPIO_DR_DR_MASK) +/*! @} */ + +/*! @name GDIR - GPIO direction register */ +/*! @{ */ +#define GPIO_GDIR_GDIR_MASK (0xFFFFFFFFU) +#define GPIO_GDIR_GDIR_SHIFT (0U) +#define GPIO_GDIR_GDIR(x) (((uint32_t)(((uint32_t)(x)) << GPIO_GDIR_GDIR_SHIFT)) & GPIO_GDIR_GDIR_MASK) +/*! @} */ + +/*! @name PSR - GPIO pad status register */ +/*! @{ */ +#define GPIO_PSR_PSR_MASK (0xFFFFFFFFU) +#define GPIO_PSR_PSR_SHIFT (0U) +#define GPIO_PSR_PSR(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PSR_PSR_SHIFT)) & GPIO_PSR_PSR_MASK) +/*! @} */ + +/*! @name ICR1 - GPIO interrupt configuration register1 */ +/*! @{ */ +#define GPIO_ICR1_ICR0_MASK (0x3U) +#define GPIO_ICR1_ICR0_SHIFT (0U) +/*! ICR0 - ICR0 + * 0b00..Interrupt n is low-level sensitive. + * 0b01..Interrupt n is high-level sensitive. + * 0b10..Interrupt n is rising-edge sensitive. + * 0b11..Interrupt n is falling-edge sensitive. + */ +#define GPIO_ICR1_ICR0(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR0_SHIFT)) & GPIO_ICR1_ICR0_MASK) +#define GPIO_ICR1_ICR1_MASK (0xCU) +#define GPIO_ICR1_ICR1_SHIFT (2U) +/*! ICR1 - ICR1 + * 0b00..Interrupt n is low-level sensitive. + * 0b01..Interrupt n is high-level sensitive. + * 0b10..Interrupt n is rising-edge sensitive. + * 0b11..Interrupt n is falling-edge sensitive. + */ +#define GPIO_ICR1_ICR1(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR1_SHIFT)) & GPIO_ICR1_ICR1_MASK) +#define GPIO_ICR1_ICR2_MASK (0x30U) +#define GPIO_ICR1_ICR2_SHIFT (4U) +/*! ICR2 - ICR2 + * 0b00..Interrupt n is low-level sensitive. + * 0b01..Interrupt n is high-level sensitive. + * 0b10..Interrupt n is rising-edge sensitive. + * 0b11..Interrupt n is falling-edge sensitive. + */ +#define GPIO_ICR1_ICR2(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR2_SHIFT)) & GPIO_ICR1_ICR2_MASK) +#define GPIO_ICR1_ICR3_MASK (0xC0U) +#define GPIO_ICR1_ICR3_SHIFT (6U) +/*! ICR3 - ICR3 + * 0b00..Interrupt n is low-level sensitive. + * 0b01..Interrupt n is high-level sensitive. + * 0b10..Interrupt n is rising-edge sensitive. + * 0b11..Interrupt n is falling-edge sensitive. + */ +#define GPIO_ICR1_ICR3(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR3_SHIFT)) & GPIO_ICR1_ICR3_MASK) +#define GPIO_ICR1_ICR4_MASK (0x300U) +#define GPIO_ICR1_ICR4_SHIFT (8U) +/*! ICR4 - ICR4 + * 0b00..Interrupt n is low-level sensitive. + * 0b01..Interrupt n is high-level sensitive. + * 0b10..Interrupt n is rising-edge sensitive. + * 0b11..Interrupt n is falling-edge sensitive. + */ +#define GPIO_ICR1_ICR4(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR4_SHIFT)) & GPIO_ICR1_ICR4_MASK) +#define GPIO_ICR1_ICR5_MASK (0xC00U) +#define GPIO_ICR1_ICR5_SHIFT (10U) +/*! ICR5 - ICR5 + * 0b00..Interrupt n is low-level sensitive. + * 0b01..Interrupt n is high-level sensitive. + * 0b10..Interrupt n is rising-edge sensitive. + * 0b11..Interrupt n is falling-edge sensitive. + */ +#define GPIO_ICR1_ICR5(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR5_SHIFT)) & GPIO_ICR1_ICR5_MASK) +#define GPIO_ICR1_ICR6_MASK (0x3000U) +#define GPIO_ICR1_ICR6_SHIFT (12U) +/*! ICR6 - ICR6 + * 0b00..Interrupt n is low-level sensitive. + * 0b01..Interrupt n is high-level sensitive. + * 0b10..Interrupt n is rising-edge sensitive. + * 0b11..Interrupt n is falling-edge sensitive. + */ +#define GPIO_ICR1_ICR6(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR6_SHIFT)) & GPIO_ICR1_ICR6_MASK) +#define GPIO_ICR1_ICR7_MASK (0xC000U) +#define GPIO_ICR1_ICR7_SHIFT (14U) +/*! ICR7 - ICR7 + * 0b00..Interrupt n is low-level sensitive. + * 0b01..Interrupt n is high-level sensitive. + * 0b10..Interrupt n is rising-edge sensitive. + * 0b11..Interrupt n is falling-edge sensitive. + */ +#define GPIO_ICR1_ICR7(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR7_SHIFT)) & GPIO_ICR1_ICR7_MASK) +#define GPIO_ICR1_ICR8_MASK (0x30000U) +#define GPIO_ICR1_ICR8_SHIFT (16U) +/*! ICR8 - ICR8 + * 0b00..Interrupt n is low-level sensitive. + * 0b01..Interrupt n is high-level sensitive. + * 0b10..Interrupt n is rising-edge sensitive. + * 0b11..Interrupt n is falling-edge sensitive. + */ +#define GPIO_ICR1_ICR8(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR8_SHIFT)) & GPIO_ICR1_ICR8_MASK) +#define GPIO_ICR1_ICR9_MASK (0xC0000U) +#define GPIO_ICR1_ICR9_SHIFT (18U) +/*! ICR9 - ICR9 + * 0b00..Interrupt n is low-level sensitive. + * 0b01..Interrupt n is high-level sensitive. + * 0b10..Interrupt n is rising-edge sensitive. + * 0b11..Interrupt n is falling-edge sensitive. + */ +#define GPIO_ICR1_ICR9(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR9_SHIFT)) & GPIO_ICR1_ICR9_MASK) +#define GPIO_ICR1_ICR10_MASK (0x300000U) +#define GPIO_ICR1_ICR10_SHIFT (20U) +/*! ICR10 - ICR10 + * 0b00..Interrupt n is low-level sensitive. + * 0b01..Interrupt n is high-level sensitive. + * 0b10..Interrupt n is rising-edge sensitive. + * 0b11..Interrupt n is falling-edge sensitive. + */ +#define GPIO_ICR1_ICR10(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR10_SHIFT)) & GPIO_ICR1_ICR10_MASK) +#define GPIO_ICR1_ICR11_MASK (0xC00000U) +#define GPIO_ICR1_ICR11_SHIFT (22U) +/*! ICR11 - ICR11 + * 0b00..Interrupt n is low-level sensitive. + * 0b01..Interrupt n is high-level sensitive. + * 0b10..Interrupt n is rising-edge sensitive. + * 0b11..Interrupt n is falling-edge sensitive. + */ +#define GPIO_ICR1_ICR11(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR11_SHIFT)) & GPIO_ICR1_ICR11_MASK) +#define GPIO_ICR1_ICR12_MASK (0x3000000U) +#define GPIO_ICR1_ICR12_SHIFT (24U) +/*! ICR12 - ICR12 + * 0b00..Interrupt n is low-level sensitive. + * 0b01..Interrupt n is high-level sensitive. + * 0b10..Interrupt n is rising-edge sensitive. + * 0b11..Interrupt n is falling-edge sensitive. + */ +#define GPIO_ICR1_ICR12(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR12_SHIFT)) & GPIO_ICR1_ICR12_MASK) +#define GPIO_ICR1_ICR13_MASK (0xC000000U) +#define GPIO_ICR1_ICR13_SHIFT (26U) +/*! ICR13 - ICR13 + * 0b00..Interrupt n is low-level sensitive. + * 0b01..Interrupt n is high-level sensitive. + * 0b10..Interrupt n is rising-edge sensitive. + * 0b11..Interrupt n is falling-edge sensitive. + */ +#define GPIO_ICR1_ICR13(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR13_SHIFT)) & GPIO_ICR1_ICR13_MASK) +#define GPIO_ICR1_ICR14_MASK (0x30000000U) +#define GPIO_ICR1_ICR14_SHIFT (28U) +/*! ICR14 - ICR14 + * 0b00..Interrupt n is low-level sensitive. + * 0b01..Interrupt n is high-level sensitive. + * 0b10..Interrupt n is rising-edge sensitive. + * 0b11..Interrupt n is falling-edge sensitive. + */ +#define GPIO_ICR1_ICR14(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR14_SHIFT)) & GPIO_ICR1_ICR14_MASK) +#define GPIO_ICR1_ICR15_MASK (0xC0000000U) +#define GPIO_ICR1_ICR15_SHIFT (30U) +/*! ICR15 - ICR15 + * 0b00..Interrupt n is low-level sensitive. + * 0b01..Interrupt n is high-level sensitive. + * 0b10..Interrupt n is rising-edge sensitive. + * 0b11..Interrupt n is falling-edge sensitive. + */ +#define GPIO_ICR1_ICR15(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR15_SHIFT)) & GPIO_ICR1_ICR15_MASK) +/*! @} */ + +/*! @name ICR2 - GPIO interrupt configuration register2 */ +/*! @{ */ +#define GPIO_ICR2_ICR16_MASK (0x3U) +#define GPIO_ICR2_ICR16_SHIFT (0U) +/*! ICR16 - ICR16 + * 0b00..Interrupt n is low-level sensitive. + * 0b01..Interrupt n is high-level sensitive. + * 0b10..Interrupt n is rising-edge sensitive. + * 0b11..Interrupt n is falling-edge sensitive. + */ +#define GPIO_ICR2_ICR16(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR16_SHIFT)) & GPIO_ICR2_ICR16_MASK) +#define GPIO_ICR2_ICR17_MASK (0xCU) +#define GPIO_ICR2_ICR17_SHIFT (2U) +/*! ICR17 - ICR17 + * 0b00..Interrupt n is low-level sensitive. + * 0b01..Interrupt n is high-level sensitive. + * 0b10..Interrupt n is rising-edge sensitive. + * 0b11..Interrupt n is falling-edge sensitive. + */ +#define GPIO_ICR2_ICR17(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR17_SHIFT)) & GPIO_ICR2_ICR17_MASK) +#define GPIO_ICR2_ICR18_MASK (0x30U) +#define GPIO_ICR2_ICR18_SHIFT (4U) +/*! ICR18 - ICR18 + * 0b00..Interrupt n is low-level sensitive. + * 0b01..Interrupt n is high-level sensitive. + * 0b10..Interrupt n is rising-edge sensitive. + * 0b11..Interrupt n is falling-edge sensitive. + */ +#define GPIO_ICR2_ICR18(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR18_SHIFT)) & GPIO_ICR2_ICR18_MASK) +#define GPIO_ICR2_ICR19_MASK (0xC0U) +#define GPIO_ICR2_ICR19_SHIFT (6U) +/*! ICR19 - ICR19 + * 0b00..Interrupt n is low-level sensitive. + * 0b01..Interrupt n is high-level sensitive. + * 0b10..Interrupt n is rising-edge sensitive. + * 0b11..Interrupt n is falling-edge sensitive. + */ +#define GPIO_ICR2_ICR19(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR19_SHIFT)) & GPIO_ICR2_ICR19_MASK) +#define GPIO_ICR2_ICR20_MASK (0x300U) +#define GPIO_ICR2_ICR20_SHIFT (8U) +/*! ICR20 - ICR20 + * 0b00..Interrupt n is low-level sensitive. + * 0b01..Interrupt n is high-level sensitive. + * 0b10..Interrupt n is rising-edge sensitive. + * 0b11..Interrupt n is falling-edge sensitive. + */ +#define GPIO_ICR2_ICR20(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR20_SHIFT)) & GPIO_ICR2_ICR20_MASK) +#define GPIO_ICR2_ICR21_MASK (0xC00U) +#define GPIO_ICR2_ICR21_SHIFT (10U) +/*! ICR21 - ICR21 + * 0b00..Interrupt n is low-level sensitive. + * 0b01..Interrupt n is high-level sensitive. + * 0b10..Interrupt n is rising-edge sensitive. + * 0b11..Interrupt n is falling-edge sensitive. + */ +#define GPIO_ICR2_ICR21(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR21_SHIFT)) & GPIO_ICR2_ICR21_MASK) +#define GPIO_ICR2_ICR22_MASK (0x3000U) +#define GPIO_ICR2_ICR22_SHIFT (12U) +/*! ICR22 - ICR22 + * 0b00..Interrupt n is low-level sensitive. + * 0b01..Interrupt n is high-level sensitive. + * 0b10..Interrupt n is rising-edge sensitive. + * 0b11..Interrupt n is falling-edge sensitive. + */ +#define GPIO_ICR2_ICR22(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR22_SHIFT)) & GPIO_ICR2_ICR22_MASK) +#define GPIO_ICR2_ICR23_MASK (0xC000U) +#define GPIO_ICR2_ICR23_SHIFT (14U) +/*! ICR23 - ICR23 + * 0b00..Interrupt n is low-level sensitive. + * 0b01..Interrupt n is high-level sensitive. + * 0b10..Interrupt n is rising-edge sensitive. + * 0b11..Interrupt n is falling-edge sensitive. + */ +#define GPIO_ICR2_ICR23(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR23_SHIFT)) & GPIO_ICR2_ICR23_MASK) +#define GPIO_ICR2_ICR24_MASK (0x30000U) +#define GPIO_ICR2_ICR24_SHIFT (16U) +/*! ICR24 - ICR24 + * 0b00..Interrupt n is low-level sensitive. + * 0b01..Interrupt n is high-level sensitive. + * 0b10..Interrupt n is rising-edge sensitive. + * 0b11..Interrupt n is falling-edge sensitive. + */ +#define GPIO_ICR2_ICR24(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR24_SHIFT)) & GPIO_ICR2_ICR24_MASK) +#define GPIO_ICR2_ICR25_MASK (0xC0000U) +#define GPIO_ICR2_ICR25_SHIFT (18U) +/*! ICR25 - ICR25 + * 0b00..Interrupt n is low-level sensitive. + * 0b01..Interrupt n is high-level sensitive. + * 0b10..Interrupt n is rising-edge sensitive. + * 0b11..Interrupt n is falling-edge sensitive. + */ +#define GPIO_ICR2_ICR25(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR25_SHIFT)) & GPIO_ICR2_ICR25_MASK) +#define GPIO_ICR2_ICR26_MASK (0x300000U) +#define GPIO_ICR2_ICR26_SHIFT (20U) +/*! ICR26 - ICR26 + * 0b00..Interrupt n is low-level sensitive. + * 0b01..Interrupt n is high-level sensitive. + * 0b10..Interrupt n is rising-edge sensitive. + * 0b11..Interrupt n is falling-edge sensitive. + */ +#define GPIO_ICR2_ICR26(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR26_SHIFT)) & GPIO_ICR2_ICR26_MASK) +#define GPIO_ICR2_ICR27_MASK (0xC00000U) +#define GPIO_ICR2_ICR27_SHIFT (22U) +/*! ICR27 - ICR27 + * 0b00..Interrupt n is low-level sensitive. + * 0b01..Interrupt n is high-level sensitive. + * 0b10..Interrupt n is rising-edge sensitive. + * 0b11..Interrupt n is falling-edge sensitive. + */ +#define GPIO_ICR2_ICR27(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR27_SHIFT)) & GPIO_ICR2_ICR27_MASK) +#define GPIO_ICR2_ICR28_MASK (0x3000000U) +#define GPIO_ICR2_ICR28_SHIFT (24U) +/*! ICR28 - ICR28 + * 0b00..Interrupt n is low-level sensitive. + * 0b01..Interrupt n is high-level sensitive. + * 0b10..Interrupt n is rising-edge sensitive. + * 0b11..Interrupt n is falling-edge sensitive. + */ +#define GPIO_ICR2_ICR28(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR28_SHIFT)) & GPIO_ICR2_ICR28_MASK) +#define GPIO_ICR2_ICR29_MASK (0xC000000U) +#define GPIO_ICR2_ICR29_SHIFT (26U) +/*! ICR29 - ICR29 + * 0b00..Interrupt n is low-level sensitive. + * 0b01..Interrupt n is high-level sensitive. + * 0b10..Interrupt n is rising-edge sensitive. + * 0b11..Interrupt n is falling-edge sensitive. + */ +#define GPIO_ICR2_ICR29(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR29_SHIFT)) & GPIO_ICR2_ICR29_MASK) +#define GPIO_ICR2_ICR30_MASK (0x30000000U) +#define GPIO_ICR2_ICR30_SHIFT (28U) +/*! ICR30 - ICR30 + * 0b00..Interrupt n is low-level sensitive. + * 0b01..Interrupt n is high-level sensitive. + * 0b10..Interrupt n is rising-edge sensitive. + * 0b11..Interrupt n is falling-edge sensitive. + */ +#define GPIO_ICR2_ICR30(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR30_SHIFT)) & GPIO_ICR2_ICR30_MASK) +#define GPIO_ICR2_ICR31_MASK (0xC0000000U) +#define GPIO_ICR2_ICR31_SHIFT (30U) +/*! ICR31 - ICR31 + * 0b00..Interrupt n is low-level sensitive. + * 0b01..Interrupt n is high-level sensitive. + * 0b10..Interrupt n is rising-edge sensitive. + * 0b11..Interrupt n is falling-edge sensitive. + */ +#define GPIO_ICR2_ICR31(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR31_SHIFT)) & GPIO_ICR2_ICR31_MASK) +/*! @} */ + +/*! @name IMR - GPIO interrupt mask register */ +/*! @{ */ +#define GPIO_IMR_IMR_MASK (0xFFFFFFFFU) +#define GPIO_IMR_IMR_SHIFT (0U) +#define GPIO_IMR_IMR(x) (((uint32_t)(((uint32_t)(x)) << GPIO_IMR_IMR_SHIFT)) & GPIO_IMR_IMR_MASK) +/*! @} */ + +/*! @name ISR - GPIO interrupt status register */ +/*! @{ */ +#define GPIO_ISR_ISR_MASK (0xFFFFFFFFU) +#define GPIO_ISR_ISR_SHIFT (0U) +#define GPIO_ISR_ISR(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ISR_ISR_SHIFT)) & GPIO_ISR_ISR_MASK) +/*! @} */ + +/*! @name EDGE_SEL - GPIO edge select register */ +/*! @{ */ +#define GPIO_EDGE_SEL_GPIO_EDGE_SEL_MASK (0xFFFFFFFFU) +#define GPIO_EDGE_SEL_GPIO_EDGE_SEL_SHIFT (0U) +#define GPIO_EDGE_SEL_GPIO_EDGE_SEL(x) (((uint32_t)(((uint32_t)(x)) << GPIO_EDGE_SEL_GPIO_EDGE_SEL_SHIFT)) & GPIO_EDGE_SEL_GPIO_EDGE_SEL_MASK) +/*! @} */ + +/*! @name DR_SET - GPIO data register SET */ +/*! @{ */ +#define GPIO_DR_SET_DR_SET_MASK (0xFFFFFFFFU) +#define GPIO_DR_SET_DR_SET_SHIFT (0U) +#define GPIO_DR_SET_DR_SET(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DR_SET_DR_SET_SHIFT)) & GPIO_DR_SET_DR_SET_MASK) +/*! @} */ + +/*! @name DR_CLEAR - GPIO data register CLEAR */ +/*! @{ */ +#define GPIO_DR_CLEAR_DR_CLEAR_MASK (0xFFFFFFFFU) +#define GPIO_DR_CLEAR_DR_CLEAR_SHIFT (0U) +#define GPIO_DR_CLEAR_DR_CLEAR(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DR_CLEAR_DR_CLEAR_SHIFT)) & GPIO_DR_CLEAR_DR_CLEAR_MASK) +/*! @} */ + +/*! @name DR_TOGGLE - GPIO data register TOGGLE */ +/*! @{ */ +#define GPIO_DR_TOGGLE_DR_TOGGLE_MASK (0xFFFFFFFFU) +#define GPIO_DR_TOGGLE_DR_TOGGLE_SHIFT (0U) +#define GPIO_DR_TOGGLE_DR_TOGGLE(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DR_TOGGLE_DR_TOGGLE_SHIFT)) & GPIO_DR_TOGGLE_DR_TOGGLE_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group GPIO_Register_Masks */ + + +/* GPIO - Peripheral instance base addresses */ +/** Peripheral GPIO1 base address */ +#define GPIO1_BASE (0x401B8000u) +/** Peripheral GPIO1 base pointer */ +#define GPIO1 ((GPIO_Type *)GPIO1_BASE) +/** Peripheral GPIO2 base address */ +#define GPIO2_BASE (0x401BC000u) +/** Peripheral GPIO2 base pointer */ +#define GPIO2 ((GPIO_Type *)GPIO2_BASE) +/** Peripheral GPIO3 base address */ +#define GPIO3_BASE (0x401C0000u) +/** Peripheral GPIO3 base pointer */ +#define GPIO3 ((GPIO_Type *)GPIO3_BASE) +/** Peripheral GPIO4 base address */ +#define GPIO4_BASE (0x401C4000u) +/** Peripheral GPIO4 base pointer */ +#define GPIO4 ((GPIO_Type *)GPIO4_BASE) +/** Peripheral GPIO5 base address */ +#define GPIO5_BASE (0x400C0000u) +/** Peripheral GPIO5 base pointer */ +#define GPIO5 ((GPIO_Type *)GPIO5_BASE) +/** Array initializer of GPIO peripheral base addresses */ +#define GPIO_BASE_ADDRS { 0u, GPIO1_BASE, GPIO2_BASE, GPIO3_BASE, GPIO4_BASE, GPIO5_BASE } +/** Array initializer of GPIO peripheral base pointers */ +#define GPIO_BASE_PTRS { (GPIO_Type *)0u, GPIO1, GPIO2, GPIO3, GPIO4, GPIO5 } +/** Interrupt vectors for the GPIO peripheral type */ +#define GPIO_IRQS { NotAvail_IRQn, GPIO1_INT0_IRQn, GPIO1_INT1_IRQn, GPIO1_INT2_IRQn, GPIO1_INT3_IRQn, GPIO1_INT4_IRQn, GPIO1_INT5_IRQn, GPIO1_INT6_IRQn, GPIO1_INT7_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn } +#define GPIO_COMBINED_LOW_IRQS { NotAvail_IRQn, GPIO1_Combined_0_15_IRQn, GPIO2_Combined_0_15_IRQn, GPIO3_Combined_0_15_IRQn, GPIO4_Combined_0_15_IRQn, GPIO5_Combined_0_15_IRQn } +#define GPIO_COMBINED_HIGH_IRQS { NotAvail_IRQn, GPIO1_Combined_16_31_IRQn, GPIO2_Combined_16_31_IRQn, GPIO3_Combined_16_31_IRQn, GPIO4_Combined_16_31_IRQn, GPIO5_Combined_16_31_IRQn } + +/*! + * @} + */ /* end of group GPIO_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- GPT Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup GPT_Peripheral_Access_Layer GPT Peripheral Access Layer + * @{ + */ + +/** GPT - Register Layout Typedef */ +typedef struct { + __IO uint32_t CR; /**< GPT Control Register, offset: 0x0 */ + __IO uint32_t PR; /**< GPT Prescaler Register, offset: 0x4 */ + __IO uint32_t SR; /**< GPT Status Register, offset: 0x8 */ + __IO uint32_t IR; /**< GPT Interrupt Register, offset: 0xC */ + __IO uint32_t OCR[3]; /**< GPT Output Compare Register 1..GPT Output Compare Register 3, array offset: 0x10, array step: 0x4 */ + __I uint32_t ICR[2]; /**< GPT Input Capture Register 1..GPT Input Capture Register 2, array offset: 0x1C, array step: 0x4 */ + __I uint32_t CNT; /**< GPT Counter Register, offset: 0x24 */ +} GPT_Type; + +/* ---------------------------------------------------------------------------- + -- GPT Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup GPT_Register_Masks GPT Register Masks + * @{ + */ + +/*! @name CR - GPT Control Register */ +/*! @{ */ +#define GPT_CR_EN_MASK (0x1U) +#define GPT_CR_EN_SHIFT (0U) +/*! EN + * 0b0..GPT is disabled. + * 0b1..GPT is enabled. + */ +#define GPT_CR_EN(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_EN_SHIFT)) & GPT_CR_EN_MASK) +#define GPT_CR_ENMOD_MASK (0x2U) +#define GPT_CR_ENMOD_SHIFT (1U) +/*! ENMOD + * 0b0..GPT counter will retain its value when it is disabled. + * 0b1..GPT counter value is reset to 0 when it is disabled. + */ +#define GPT_CR_ENMOD(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_ENMOD_SHIFT)) & GPT_CR_ENMOD_MASK) +#define GPT_CR_DBGEN_MASK (0x4U) +#define GPT_CR_DBGEN_SHIFT (2U) +/*! DBGEN + * 0b0..GPT is disabled in debug mode. + * 0b1..GPT is enabled in debug mode. + */ +#define GPT_CR_DBGEN(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_DBGEN_SHIFT)) & GPT_CR_DBGEN_MASK) +#define GPT_CR_WAITEN_MASK (0x8U) +#define GPT_CR_WAITEN_SHIFT (3U) +/*! WAITEN + * 0b0..GPT is disabled in wait mode. + * 0b1..GPT is enabled in wait mode. + */ +#define GPT_CR_WAITEN(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_WAITEN_SHIFT)) & GPT_CR_WAITEN_MASK) +#define GPT_CR_DOZEEN_MASK (0x10U) +#define GPT_CR_DOZEEN_SHIFT (4U) +/*! DOZEEN + * 0b0..GPT is disabled in doze mode. + * 0b1..GPT is enabled in doze mode. + */ +#define GPT_CR_DOZEEN(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_DOZEEN_SHIFT)) & GPT_CR_DOZEEN_MASK) +#define GPT_CR_STOPEN_MASK (0x20U) +#define GPT_CR_STOPEN_SHIFT (5U) +/*! STOPEN + * 0b0..GPT is disabled in Stop mode. + * 0b1..GPT is enabled in Stop mode. + */ +#define GPT_CR_STOPEN(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_STOPEN_SHIFT)) & GPT_CR_STOPEN_MASK) +#define GPT_CR_CLKSRC_MASK (0x1C0U) +#define GPT_CR_CLKSRC_SHIFT (6U) +/*! CLKSRC + * 0b000..No clock + * 0b001..Peripheral Clock (ipg_clk) + * 0b010..High Frequency Reference Clock (ipg_clk_highfreq) + * 0b011..External Clock + * 0b100..Low Frequency Reference Clock (ipg_clk_32k) + * 0b101..Crystal oscillator as Reference Clock (ipg_clk_24M) + */ +#define GPT_CR_CLKSRC(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_CLKSRC_SHIFT)) & GPT_CR_CLKSRC_MASK) +#define GPT_CR_FRR_MASK (0x200U) +#define GPT_CR_FRR_SHIFT (9U) +/*! FRR + * 0b0..Restart mode + * 0b1..Free-Run mode + */ +#define GPT_CR_FRR(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_FRR_SHIFT)) & GPT_CR_FRR_MASK) +#define GPT_CR_EN_24M_MASK (0x400U) +#define GPT_CR_EN_24M_SHIFT (10U) +/*! EN_24M + * 0b0..24M clock disabled + * 0b1..24M clock enabled + */ +#define GPT_CR_EN_24M(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_EN_24M_SHIFT)) & GPT_CR_EN_24M_MASK) +#define GPT_CR_SWR_MASK (0x8000U) +#define GPT_CR_SWR_SHIFT (15U) +/*! SWR + * 0b0..GPT is not in reset state + * 0b1..GPT is in reset state + */ +#define GPT_CR_SWR(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_SWR_SHIFT)) & GPT_CR_SWR_MASK) +#define GPT_CR_IM1_MASK (0x30000U) +#define GPT_CR_IM1_SHIFT (16U) +#define GPT_CR_IM1(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_IM1_SHIFT)) & GPT_CR_IM1_MASK) +#define GPT_CR_IM2_MASK (0xC0000U) +#define GPT_CR_IM2_SHIFT (18U) +/*! IM2 + * 0b00..capture disabled + * 0b01..capture on rising edge only + * 0b10..capture on falling edge only + * 0b11..capture on both edges + */ +#define GPT_CR_IM2(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_IM2_SHIFT)) & GPT_CR_IM2_MASK) +#define GPT_CR_OM1_MASK (0x700000U) +#define GPT_CR_OM1_SHIFT (20U) +#define GPT_CR_OM1(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_OM1_SHIFT)) & GPT_CR_OM1_MASK) +#define GPT_CR_OM2_MASK (0x3800000U) +#define GPT_CR_OM2_SHIFT (23U) +#define GPT_CR_OM2(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_OM2_SHIFT)) & GPT_CR_OM2_MASK) +#define GPT_CR_OM3_MASK (0x1C000000U) +#define GPT_CR_OM3_SHIFT (26U) +/*! OM3 + * 0b000..Output disconnected. No response on pin. + * 0b001..Toggle output pin + * 0b010..Clear output pin + * 0b011..Set output pin + * 0b1xx..Generate an active low pulse (that is one input clock wide) on the output pin. + */ +#define GPT_CR_OM3(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_OM3_SHIFT)) & GPT_CR_OM3_MASK) +#define GPT_CR_FO1_MASK (0x20000000U) +#define GPT_CR_FO1_SHIFT (29U) +#define GPT_CR_FO1(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_FO1_SHIFT)) & GPT_CR_FO1_MASK) +#define GPT_CR_FO2_MASK (0x40000000U) +#define GPT_CR_FO2_SHIFT (30U) +#define GPT_CR_FO2(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_FO2_SHIFT)) & GPT_CR_FO2_MASK) +#define GPT_CR_FO3_MASK (0x80000000U) +#define GPT_CR_FO3_SHIFT (31U) +/*! FO3 + * 0b0..Writing a 0 has no effect. + * 0b1..Causes the programmed pin action on the timer Output Compare n pin; the OFn flag is not set. + */ +#define GPT_CR_FO3(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_FO3_SHIFT)) & GPT_CR_FO3_MASK) +/*! @} */ + +/*! @name PR - GPT Prescaler Register */ +/*! @{ */ +#define GPT_PR_PRESCALER_MASK (0xFFFU) +#define GPT_PR_PRESCALER_SHIFT (0U) +/*! PRESCALER + * 0b000000000000..Divide by 1 + * 0b000000000001..Divide by 2 + * 0b111111111111..Divide by 4096 + */ +#define GPT_PR_PRESCALER(x) (((uint32_t)(((uint32_t)(x)) << GPT_PR_PRESCALER_SHIFT)) & GPT_PR_PRESCALER_MASK) +#define GPT_PR_PRESCALER24M_MASK (0xF000U) +#define GPT_PR_PRESCALER24M_SHIFT (12U) +/*! PRESCALER24M + * 0b0000..Divide by 1 + * 0b0001..Divide by 2 + * 0b1111..Divide by 16 + */ +#define GPT_PR_PRESCALER24M(x) (((uint32_t)(((uint32_t)(x)) << GPT_PR_PRESCALER24M_SHIFT)) & GPT_PR_PRESCALER24M_MASK) +/*! @} */ + +/*! @name SR - GPT Status Register */ +/*! @{ */ +#define GPT_SR_OF1_MASK (0x1U) +#define GPT_SR_OF1_SHIFT (0U) +#define GPT_SR_OF1(x) (((uint32_t)(((uint32_t)(x)) << GPT_SR_OF1_SHIFT)) & GPT_SR_OF1_MASK) +#define GPT_SR_OF2_MASK (0x2U) +#define GPT_SR_OF2_SHIFT (1U) +#define GPT_SR_OF2(x) (((uint32_t)(((uint32_t)(x)) << GPT_SR_OF2_SHIFT)) & GPT_SR_OF2_MASK) +#define GPT_SR_OF3_MASK (0x4U) +#define GPT_SR_OF3_SHIFT (2U) +/*! OF3 + * 0b0..Compare event has not occurred. + * 0b1..Compare event has occurred. + */ +#define GPT_SR_OF3(x) (((uint32_t)(((uint32_t)(x)) << GPT_SR_OF3_SHIFT)) & GPT_SR_OF3_MASK) +#define GPT_SR_IF1_MASK (0x8U) +#define GPT_SR_IF1_SHIFT (3U) +#define GPT_SR_IF1(x) (((uint32_t)(((uint32_t)(x)) << GPT_SR_IF1_SHIFT)) & GPT_SR_IF1_MASK) +#define GPT_SR_IF2_MASK (0x10U) +#define GPT_SR_IF2_SHIFT (4U) +/*! IF2 + * 0b0..Capture event has not occurred. + * 0b1..Capture event has occurred. + */ +#define GPT_SR_IF2(x) (((uint32_t)(((uint32_t)(x)) << GPT_SR_IF2_SHIFT)) & GPT_SR_IF2_MASK) +#define GPT_SR_ROV_MASK (0x20U) +#define GPT_SR_ROV_SHIFT (5U) +/*! ROV + * 0b0..Rollover has not occurred. + * 0b1..Rollover has occurred. + */ +#define GPT_SR_ROV(x) (((uint32_t)(((uint32_t)(x)) << GPT_SR_ROV_SHIFT)) & GPT_SR_ROV_MASK) +/*! @} */ + +/*! @name IR - GPT Interrupt Register */ +/*! @{ */ +#define GPT_IR_OF1IE_MASK (0x1U) +#define GPT_IR_OF1IE_SHIFT (0U) +#define GPT_IR_OF1IE(x) (((uint32_t)(((uint32_t)(x)) << GPT_IR_OF1IE_SHIFT)) & GPT_IR_OF1IE_MASK) +#define GPT_IR_OF2IE_MASK (0x2U) +#define GPT_IR_OF2IE_SHIFT (1U) +#define GPT_IR_OF2IE(x) (((uint32_t)(((uint32_t)(x)) << GPT_IR_OF2IE_SHIFT)) & GPT_IR_OF2IE_MASK) +#define GPT_IR_OF3IE_MASK (0x4U) +#define GPT_IR_OF3IE_SHIFT (2U) +/*! OF3IE + * 0b0..Output Compare Channel n interrupt is disabled. + * 0b1..Output Compare Channel n interrupt is enabled. + */ +#define GPT_IR_OF3IE(x) (((uint32_t)(((uint32_t)(x)) << GPT_IR_OF3IE_SHIFT)) & GPT_IR_OF3IE_MASK) +#define GPT_IR_IF1IE_MASK (0x8U) +#define GPT_IR_IF1IE_SHIFT (3U) +#define GPT_IR_IF1IE(x) (((uint32_t)(((uint32_t)(x)) << GPT_IR_IF1IE_SHIFT)) & GPT_IR_IF1IE_MASK) +#define GPT_IR_IF2IE_MASK (0x10U) +#define GPT_IR_IF2IE_SHIFT (4U) +/*! IF2IE + * 0b0..IF2IE Input Capture n Interrupt Enable is disabled. + * 0b1..IF2IE Input Capture n Interrupt Enable is enabled. + */ +#define GPT_IR_IF2IE(x) (((uint32_t)(((uint32_t)(x)) << GPT_IR_IF2IE_SHIFT)) & GPT_IR_IF2IE_MASK) +#define GPT_IR_ROVIE_MASK (0x20U) +#define GPT_IR_ROVIE_SHIFT (5U) +/*! ROVIE + * 0b0..Rollover interrupt is disabled. + * 0b1..Rollover interrupt enabled. + */ +#define GPT_IR_ROVIE(x) (((uint32_t)(((uint32_t)(x)) << GPT_IR_ROVIE_SHIFT)) & GPT_IR_ROVIE_MASK) +/*! @} */ + +/*! @name OCR - GPT Output Compare Register 1..GPT Output Compare Register 3 */ +/*! @{ */ +#define GPT_OCR_COMP_MASK (0xFFFFFFFFU) +#define GPT_OCR_COMP_SHIFT (0U) +#define GPT_OCR_COMP(x) (((uint32_t)(((uint32_t)(x)) << GPT_OCR_COMP_SHIFT)) & GPT_OCR_COMP_MASK) +/*! @} */ + +/* The count of GPT_OCR */ +#define GPT_OCR_COUNT (3U) + +/*! @name ICR - GPT Input Capture Register 1..GPT Input Capture Register 2 */ +/*! @{ */ +#define GPT_ICR_CAPT_MASK (0xFFFFFFFFU) +#define GPT_ICR_CAPT_SHIFT (0U) +#define GPT_ICR_CAPT(x) (((uint32_t)(((uint32_t)(x)) << GPT_ICR_CAPT_SHIFT)) & GPT_ICR_CAPT_MASK) +/*! @} */ + +/* The count of GPT_ICR */ +#define GPT_ICR_COUNT (2U) + +/*! @name CNT - GPT Counter Register */ +/*! @{ */ +#define GPT_CNT_COUNT_MASK (0xFFFFFFFFU) +#define GPT_CNT_COUNT_SHIFT (0U) +#define GPT_CNT_COUNT(x) (((uint32_t)(((uint32_t)(x)) << GPT_CNT_COUNT_SHIFT)) & GPT_CNT_COUNT_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group GPT_Register_Masks */ + + +/* GPT - Peripheral instance base addresses */ +/** Peripheral GPT1 base address */ +#define GPT1_BASE (0x401EC000u) +/** Peripheral GPT1 base pointer */ +#define GPT1 ((GPT_Type *)GPT1_BASE) +/** Peripheral GPT2 base address */ +#define GPT2_BASE (0x401F0000u) +/** Peripheral GPT2 base pointer */ +#define GPT2 ((GPT_Type *)GPT2_BASE) +/** Array initializer of GPT peripheral base addresses */ +#define GPT_BASE_ADDRS { 0u, GPT1_BASE, GPT2_BASE } +/** Array initializer of GPT peripheral base pointers */ +#define GPT_BASE_PTRS { (GPT_Type *)0u, GPT1, GPT2 } +/** Interrupt vectors for the GPT peripheral type */ +#define GPT_IRQS { NotAvail_IRQn, GPT1_IRQn, GPT2_IRQn } + +/*! + * @} + */ /* end of group GPT_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- I2S Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup I2S_Peripheral_Access_Layer I2S Peripheral Access Layer + * @{ + */ + +/** I2S - Register Layout Typedef */ +typedef struct { + __I uint32_t VERID; /**< Version ID Register, offset: 0x0 */ + __I uint32_t PARAM; /**< Parameter Register, offset: 0x4 */ + __IO uint32_t TCSR; /**< SAI Transmit Control Register, offset: 0x8 */ + __IO uint32_t TCR1; /**< SAI Transmit Configuration 1 Register, offset: 0xC */ + __IO uint32_t TCR2; /**< SAI Transmit Configuration 2 Register, offset: 0x10 */ + __IO uint32_t TCR3; /**< SAI Transmit Configuration 3 Register, offset: 0x14 */ + __IO uint32_t TCR4; /**< SAI Transmit Configuration 4 Register, offset: 0x18 */ + __IO uint32_t TCR5; /**< SAI Transmit Configuration 5 Register, offset: 0x1C */ + __O uint32_t TDR[4]; /**< SAI Transmit Data Register, array offset: 0x20, array step: 0x4 */ + uint8_t RESERVED_0[16]; + __I uint32_t TFR[4]; /**< SAI Transmit FIFO Register, array offset: 0x40, array step: 0x4 */ + uint8_t RESERVED_1[16]; + __IO uint32_t TMR; /**< SAI Transmit Mask Register, offset: 0x60 */ + uint8_t RESERVED_2[36]; + __IO uint32_t RCSR; /**< SAI Receive Control Register, offset: 0x88 */ + __IO uint32_t RCR1; /**< SAI Receive Configuration 1 Register, offset: 0x8C */ + __IO uint32_t RCR2; /**< SAI Receive Configuration 2 Register, offset: 0x90 */ + __IO uint32_t RCR3; /**< SAI Receive Configuration 3 Register, offset: 0x94 */ + __IO uint32_t RCR4; /**< SAI Receive Configuration 4 Register, offset: 0x98 */ + __IO uint32_t RCR5; /**< SAI Receive Configuration 5 Register, offset: 0x9C */ + __I uint32_t RDR[4]; /**< SAI Receive Data Register, array offset: 0xA0, array step: 0x4 */ + uint8_t RESERVED_3[16]; + __I uint32_t RFR[4]; /**< SAI Receive FIFO Register, array offset: 0xC0, array step: 0x4 */ + uint8_t RESERVED_4[16]; + __IO uint32_t RMR; /**< SAI Receive Mask Register, offset: 0xE0 */ +} I2S_Type; + +/* ---------------------------------------------------------------------------- + -- I2S Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup I2S_Register_Masks I2S Register Masks + * @{ + */ + +/*! @name VERID - Version ID Register */ +/*! @{ */ +#define I2S_VERID_FEATURE_MASK (0xFFFFU) +#define I2S_VERID_FEATURE_SHIFT (0U) +/*! FEATURE - Feature Specification Number + * 0b0000000000000000..Standard feature set. + */ +#define I2S_VERID_FEATURE(x) (((uint32_t)(((uint32_t)(x)) << I2S_VERID_FEATURE_SHIFT)) & I2S_VERID_FEATURE_MASK) +#define I2S_VERID_MINOR_MASK (0xFF0000U) +#define I2S_VERID_MINOR_SHIFT (16U) +#define I2S_VERID_MINOR(x) (((uint32_t)(((uint32_t)(x)) << I2S_VERID_MINOR_SHIFT)) & I2S_VERID_MINOR_MASK) +#define I2S_VERID_MAJOR_MASK (0xFF000000U) +#define I2S_VERID_MAJOR_SHIFT (24U) +#define I2S_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << I2S_VERID_MAJOR_SHIFT)) & I2S_VERID_MAJOR_MASK) +/*! @} */ + +/*! @name PARAM - Parameter Register */ +/*! @{ */ +#define I2S_PARAM_DATALINE_MASK (0xFU) +#define I2S_PARAM_DATALINE_SHIFT (0U) +#define I2S_PARAM_DATALINE(x) (((uint32_t)(((uint32_t)(x)) << I2S_PARAM_DATALINE_SHIFT)) & I2S_PARAM_DATALINE_MASK) +#define I2S_PARAM_FIFO_MASK (0xF00U) +#define I2S_PARAM_FIFO_SHIFT (8U) +#define I2S_PARAM_FIFO(x) (((uint32_t)(((uint32_t)(x)) << I2S_PARAM_FIFO_SHIFT)) & I2S_PARAM_FIFO_MASK) +#define I2S_PARAM_FRAME_MASK (0xF0000U) +#define I2S_PARAM_FRAME_SHIFT (16U) +#define I2S_PARAM_FRAME(x) (((uint32_t)(((uint32_t)(x)) << I2S_PARAM_FRAME_SHIFT)) & I2S_PARAM_FRAME_MASK) +/*! @} */ + +/*! @name TCSR - SAI Transmit Control Register */ +/*! @{ */ +#define I2S_TCSR_FRDE_MASK (0x1U) +#define I2S_TCSR_FRDE_SHIFT (0U) +/*! FRDE - FIFO Request DMA Enable + * 0b0..Disables the DMA request. + * 0b1..Enables the DMA request. + */ +#define I2S_TCSR_FRDE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FRDE_SHIFT)) & I2S_TCSR_FRDE_MASK) +#define I2S_TCSR_FWDE_MASK (0x2U) +#define I2S_TCSR_FWDE_SHIFT (1U) +/*! FWDE - FIFO Warning DMA Enable + * 0b0..Disables the DMA request. + * 0b1..Enables the DMA request. + */ +#define I2S_TCSR_FWDE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FWDE_SHIFT)) & I2S_TCSR_FWDE_MASK) +#define I2S_TCSR_FRIE_MASK (0x100U) +#define I2S_TCSR_FRIE_SHIFT (8U) +/*! FRIE - FIFO Request Interrupt Enable + * 0b0..Disables the interrupt. + * 0b1..Enables the interrupt. + */ +#define I2S_TCSR_FRIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FRIE_SHIFT)) & I2S_TCSR_FRIE_MASK) +#define I2S_TCSR_FWIE_MASK (0x200U) +#define I2S_TCSR_FWIE_SHIFT (9U) +/*! FWIE - FIFO Warning Interrupt Enable + * 0b0..Disables the interrupt. + * 0b1..Enables the interrupt. + */ +#define I2S_TCSR_FWIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FWIE_SHIFT)) & I2S_TCSR_FWIE_MASK) +#define I2S_TCSR_FEIE_MASK (0x400U) +#define I2S_TCSR_FEIE_SHIFT (10U) +/*! FEIE - FIFO Error Interrupt Enable + * 0b0..Disables the interrupt. + * 0b1..Enables the interrupt. + */ +#define I2S_TCSR_FEIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FEIE_SHIFT)) & I2S_TCSR_FEIE_MASK) +#define I2S_TCSR_SEIE_MASK (0x800U) +#define I2S_TCSR_SEIE_SHIFT (11U) +/*! SEIE - Sync Error Interrupt Enable + * 0b0..Disables interrupt. + * 0b1..Enables interrupt. + */ +#define I2S_TCSR_SEIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_SEIE_SHIFT)) & I2S_TCSR_SEIE_MASK) +#define I2S_TCSR_WSIE_MASK (0x1000U) +#define I2S_TCSR_WSIE_SHIFT (12U) +/*! WSIE - Word Start Interrupt Enable + * 0b0..Disables interrupt. + * 0b1..Enables interrupt. + */ +#define I2S_TCSR_WSIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_WSIE_SHIFT)) & I2S_TCSR_WSIE_MASK) +#define I2S_TCSR_FRF_MASK (0x10000U) +#define I2S_TCSR_FRF_SHIFT (16U) +/*! FRF - FIFO Request Flag + * 0b0..Transmit FIFO watermark has not been reached. + * 0b1..Transmit FIFO watermark has been reached. + */ +#define I2S_TCSR_FRF(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FRF_SHIFT)) & I2S_TCSR_FRF_MASK) +#define I2S_TCSR_FWF_MASK (0x20000U) +#define I2S_TCSR_FWF_SHIFT (17U) +/*! FWF - FIFO Warning Flag + * 0b0..No enabled transmit FIFO is empty. + * 0b1..Enabled transmit FIFO is empty. + */ +#define I2S_TCSR_FWF(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FWF_SHIFT)) & I2S_TCSR_FWF_MASK) +#define I2S_TCSR_FEF_MASK (0x40000U) +#define I2S_TCSR_FEF_SHIFT (18U) +/*! FEF - FIFO Error Flag + * 0b0..Transmit underrun not detected. + * 0b1..Transmit underrun detected. + */ +#define I2S_TCSR_FEF(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FEF_SHIFT)) & I2S_TCSR_FEF_MASK) +#define I2S_TCSR_SEF_MASK (0x80000U) +#define I2S_TCSR_SEF_SHIFT (19U) +/*! SEF - Sync Error Flag + * 0b0..Sync error not detected. + * 0b1..Frame sync error detected. + */ +#define I2S_TCSR_SEF(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_SEF_SHIFT)) & I2S_TCSR_SEF_MASK) +#define I2S_TCSR_WSF_MASK (0x100000U) +#define I2S_TCSR_WSF_SHIFT (20U) +/*! WSF - Word Start Flag + * 0b0..Start of word not detected. + * 0b1..Start of word detected. + */ +#define I2S_TCSR_WSF(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_WSF_SHIFT)) & I2S_TCSR_WSF_MASK) +#define I2S_TCSR_SR_MASK (0x1000000U) +#define I2S_TCSR_SR_SHIFT (24U) +/*! SR - Software Reset + * 0b0..No effect. + * 0b1..Software reset. + */ +#define I2S_TCSR_SR(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_SR_SHIFT)) & I2S_TCSR_SR_MASK) +#define I2S_TCSR_FR_MASK (0x2000000U) +#define I2S_TCSR_FR_SHIFT (25U) +/*! FR - FIFO Reset + * 0b0..No effect. + * 0b1..FIFO reset. + */ +#define I2S_TCSR_FR(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FR_SHIFT)) & I2S_TCSR_FR_MASK) +#define I2S_TCSR_BCE_MASK (0x10000000U) +#define I2S_TCSR_BCE_SHIFT (28U) +/*! BCE - Bit Clock Enable + * 0b0..Transmit bit clock is disabled. + * 0b1..Transmit bit clock is enabled. + */ +#define I2S_TCSR_BCE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_BCE_SHIFT)) & I2S_TCSR_BCE_MASK) +#define I2S_TCSR_DBGE_MASK (0x20000000U) +#define I2S_TCSR_DBGE_SHIFT (29U) +/*! DBGE - Debug Enable + * 0b0..Transmitter is disabled in Debug mode, after completing the current frame. + * 0b1..Transmitter is enabled in Debug mode. + */ +#define I2S_TCSR_DBGE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_DBGE_SHIFT)) & I2S_TCSR_DBGE_MASK) +#define I2S_TCSR_STOPE_MASK (0x40000000U) +#define I2S_TCSR_STOPE_SHIFT (30U) +/*! STOPE - Stop Enable + * 0b0..Transmitter disabled in Stop mode. + * 0b1..Transmitter enabled in Stop mode. + */ +#define I2S_TCSR_STOPE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_STOPE_SHIFT)) & I2S_TCSR_STOPE_MASK) +#define I2S_TCSR_TE_MASK (0x80000000U) +#define I2S_TCSR_TE_SHIFT (31U) +/*! TE - Transmitter Enable + * 0b0..Transmitter is disabled. + * 0b1..Transmitter is enabled, or transmitter has been disabled and has not yet reached end of frame. + */ +#define I2S_TCSR_TE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_TE_SHIFT)) & I2S_TCSR_TE_MASK) +/*! @} */ + +/*! @name TCR1 - SAI Transmit Configuration 1 Register */ +/*! @{ */ +#define I2S_TCR1_TFW_MASK (0x1FU) +#define I2S_TCR1_TFW_SHIFT (0U) +#define I2S_TCR1_TFW(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR1_TFW_SHIFT)) & I2S_TCR1_TFW_MASK) +/*! @} */ + +/*! @name TCR2 - SAI Transmit Configuration 2 Register */ +/*! @{ */ +#define I2S_TCR2_DIV_MASK (0xFFU) +#define I2S_TCR2_DIV_SHIFT (0U) +#define I2S_TCR2_DIV(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_DIV_SHIFT)) & I2S_TCR2_DIV_MASK) +#define I2S_TCR2_BCD_MASK (0x1000000U) +#define I2S_TCR2_BCD_SHIFT (24U) +/*! BCD - Bit Clock Direction + * 0b0..Bit clock is generated externally in Slave mode. + * 0b1..Bit clock is generated internally in Master mode. + */ +#define I2S_TCR2_BCD(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_BCD_SHIFT)) & I2S_TCR2_BCD_MASK) +#define I2S_TCR2_BCP_MASK (0x2000000U) +#define I2S_TCR2_BCP_SHIFT (25U) +/*! BCP - Bit Clock Polarity + * 0b0..Bit clock is active high with drive outputs on rising edge and sample inputs on falling edge. + * 0b1..Bit clock is active low with drive outputs on falling edge and sample inputs on rising edge. + */ +#define I2S_TCR2_BCP(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_BCP_SHIFT)) & I2S_TCR2_BCP_MASK) +#define I2S_TCR2_MSEL_MASK (0xC000000U) +#define I2S_TCR2_MSEL_SHIFT (26U) +/*! MSEL - MCLK Select + * 0b00..Bus Clock selected. + * 0b01..Master Clock (MCLK) 1 option selected. + * 0b10..Master Clock (MCLK) 2 option selected. + * 0b11..Master Clock (MCLK) 3 option selected. + */ +#define I2S_TCR2_MSEL(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_MSEL_SHIFT)) & I2S_TCR2_MSEL_MASK) +#define I2S_TCR2_BCI_MASK (0x10000000U) +#define I2S_TCR2_BCI_SHIFT (28U) +/*! BCI - Bit Clock Input + * 0b0..No effect. + * 0b1..Internal logic is clocked as if bit clock was externally generated. + */ +#define I2S_TCR2_BCI(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_BCI_SHIFT)) & I2S_TCR2_BCI_MASK) +#define I2S_TCR2_BCS_MASK (0x20000000U) +#define I2S_TCR2_BCS_SHIFT (29U) +/*! BCS - Bit Clock Swap + * 0b0..Use the normal bit clock source. + * 0b1..Swap the bit clock source. + */ +#define I2S_TCR2_BCS(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_BCS_SHIFT)) & I2S_TCR2_BCS_MASK) +#define I2S_TCR2_SYNC_MASK (0xC0000000U) +#define I2S_TCR2_SYNC_SHIFT (30U) +/*! SYNC - Synchronous Mode + * 0b00..Asynchronous mode. + * 0b01..Synchronous with receiver. + * 0b10..Reserved. + * 0b11..Reserved. + */ +#define I2S_TCR2_SYNC(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_SYNC_SHIFT)) & I2S_TCR2_SYNC_MASK) +/*! @} */ + +/*! @name TCR3 - SAI Transmit Configuration 3 Register */ +/*! @{ */ +#define I2S_TCR3_WDFL_MASK (0x1FU) +#define I2S_TCR3_WDFL_SHIFT (0U) +#define I2S_TCR3_WDFL(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR3_WDFL_SHIFT)) & I2S_TCR3_WDFL_MASK) +#define I2S_TCR3_TCE_MASK (0xF0000U) +#define I2S_TCR3_TCE_SHIFT (16U) +#define I2S_TCR3_TCE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR3_TCE_SHIFT)) & I2S_TCR3_TCE_MASK) +#define I2S_TCR3_CFR_MASK (0xF000000U) +#define I2S_TCR3_CFR_SHIFT (24U) +#define I2S_TCR3_CFR(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR3_CFR_SHIFT)) & I2S_TCR3_CFR_MASK) +/*! @} */ + +/*! @name TCR4 - SAI Transmit Configuration 4 Register */ +/*! @{ */ +#define I2S_TCR4_FSD_MASK (0x1U) +#define I2S_TCR4_FSD_SHIFT (0U) +/*! FSD - Frame Sync Direction + * 0b0..Frame sync is generated externally in Slave mode. + * 0b1..Frame sync is generated internally in Master mode. + */ +#define I2S_TCR4_FSD(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FSD_SHIFT)) & I2S_TCR4_FSD_MASK) +#define I2S_TCR4_FSP_MASK (0x2U) +#define I2S_TCR4_FSP_SHIFT (1U) +/*! FSP - Frame Sync Polarity + * 0b0..Frame sync is active high. + * 0b1..Frame sync is active low. + */ +#define I2S_TCR4_FSP(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FSP_SHIFT)) & I2S_TCR4_FSP_MASK) +#define I2S_TCR4_ONDEM_MASK (0x4U) +#define I2S_TCR4_ONDEM_SHIFT (2U) +/*! ONDEM - On Demand Mode + * 0b0..Internal frame sync is generated continuously. + * 0b1..Internal frame sync is generated when the FIFO warning flag is clear. + */ +#define I2S_TCR4_ONDEM(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_ONDEM_SHIFT)) & I2S_TCR4_ONDEM_MASK) +#define I2S_TCR4_FSE_MASK (0x8U) +#define I2S_TCR4_FSE_SHIFT (3U) +/*! FSE - Frame Sync Early + * 0b0..Frame sync asserts with the first bit of the frame. + * 0b1..Frame sync asserts one bit before the first bit of the frame. + */ +#define I2S_TCR4_FSE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FSE_SHIFT)) & I2S_TCR4_FSE_MASK) +#define I2S_TCR4_MF_MASK (0x10U) +#define I2S_TCR4_MF_SHIFT (4U) +/*! MF - MSB First + * 0b0..LSB is transmitted first. + * 0b1..MSB is transmitted first. + */ +#define I2S_TCR4_MF(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_MF_SHIFT)) & I2S_TCR4_MF_MASK) +#define I2S_TCR4_CHMOD_MASK (0x20U) +#define I2S_TCR4_CHMOD_SHIFT (5U) +/*! CHMOD - Channel Mode + * 0b0..TDM mode, transmit data pins are tri-stated when slots are masked or channels are disabled. + * 0b1..Output mode, transmit data pins are never tri-stated and will output zero when slots are masked or channels are disabled. + */ +#define I2S_TCR4_CHMOD(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_CHMOD_SHIFT)) & I2S_TCR4_CHMOD_MASK) +#define I2S_TCR4_SYWD_MASK (0x1F00U) +#define I2S_TCR4_SYWD_SHIFT (8U) +#define I2S_TCR4_SYWD(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_SYWD_SHIFT)) & I2S_TCR4_SYWD_MASK) +#define I2S_TCR4_FRSZ_MASK (0x1F0000U) +#define I2S_TCR4_FRSZ_SHIFT (16U) +#define I2S_TCR4_FRSZ(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FRSZ_SHIFT)) & I2S_TCR4_FRSZ_MASK) +#define I2S_TCR4_FPACK_MASK (0x3000000U) +#define I2S_TCR4_FPACK_SHIFT (24U) +/*! FPACK - FIFO Packing Mode + * 0b00..FIFO packing is disabled + * 0b01..Reserved + * 0b10..8-bit FIFO packing is enabled + * 0b11..16-bit FIFO packing is enabled + */ +#define I2S_TCR4_FPACK(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FPACK_SHIFT)) & I2S_TCR4_FPACK_MASK) +#define I2S_TCR4_FCOMB_MASK (0xC000000U) +#define I2S_TCR4_FCOMB_SHIFT (26U) +/*! FCOMB - FIFO Combine Mode + * 0b00..FIFO combine mode disabled. + * 0b01..FIFO combine mode enabled on FIFO reads (from transmit shift registers). + * 0b10..FIFO combine mode enabled on FIFO writes (by software). + * 0b11..FIFO combine mode enabled on FIFO reads (from transmit shift registers) and writes (by software). + */ +#define I2S_TCR4_FCOMB(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FCOMB_SHIFT)) & I2S_TCR4_FCOMB_MASK) +#define I2S_TCR4_FCONT_MASK (0x10000000U) +#define I2S_TCR4_FCONT_SHIFT (28U) +/*! FCONT - FIFO Continue on Error + * 0b0..On FIFO error, the SAI will continue from the start of the next frame after the FIFO error flag has been cleared. + * 0b1..On FIFO error, the SAI will continue from the same word that caused the FIFO error to set after the FIFO warning flag has been cleared. + */ +#define I2S_TCR4_FCONT(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FCONT_SHIFT)) & I2S_TCR4_FCONT_MASK) +/*! @} */ + +/*! @name TCR5 - SAI Transmit Configuration 5 Register */ +/*! @{ */ +#define I2S_TCR5_FBT_MASK (0x1F00U) +#define I2S_TCR5_FBT_SHIFT (8U) +#define I2S_TCR5_FBT(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR5_FBT_SHIFT)) & I2S_TCR5_FBT_MASK) +#define I2S_TCR5_W0W_MASK (0x1F0000U) +#define I2S_TCR5_W0W_SHIFT (16U) +#define I2S_TCR5_W0W(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR5_W0W_SHIFT)) & I2S_TCR5_W0W_MASK) +#define I2S_TCR5_WNW_MASK (0x1F000000U) +#define I2S_TCR5_WNW_SHIFT (24U) +#define I2S_TCR5_WNW(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR5_WNW_SHIFT)) & I2S_TCR5_WNW_MASK) +/*! @} */ + +/*! @name TDR - SAI Transmit Data Register */ +/*! @{ */ +#define I2S_TDR_TDR_MASK (0xFFFFFFFFU) +#define I2S_TDR_TDR_SHIFT (0U) +#define I2S_TDR_TDR(x) (((uint32_t)(((uint32_t)(x)) << I2S_TDR_TDR_SHIFT)) & I2S_TDR_TDR_MASK) +/*! @} */ + +/* The count of I2S_TDR */ +#define I2S_TDR_COUNT (4U) + +/*! @name TFR - SAI Transmit FIFO Register */ +/*! @{ */ +#define I2S_TFR_RFP_MASK (0x3FU) +#define I2S_TFR_RFP_SHIFT (0U) +#define I2S_TFR_RFP(x) (((uint32_t)(((uint32_t)(x)) << I2S_TFR_RFP_SHIFT)) & I2S_TFR_RFP_MASK) +#define I2S_TFR_WFP_MASK (0x3F0000U) +#define I2S_TFR_WFP_SHIFT (16U) +#define I2S_TFR_WFP(x) (((uint32_t)(((uint32_t)(x)) << I2S_TFR_WFP_SHIFT)) & I2S_TFR_WFP_MASK) +#define I2S_TFR_WCP_MASK (0x80000000U) +#define I2S_TFR_WCP_SHIFT (31U) +/*! WCP - Write Channel Pointer + * 0b0..No effect. + * 0b1..FIFO combine is enabled for FIFO writes and this FIFO will be written on the next FIFO write. + */ +#define I2S_TFR_WCP(x) (((uint32_t)(((uint32_t)(x)) << I2S_TFR_WCP_SHIFT)) & I2S_TFR_WCP_MASK) +/*! @} */ + +/* The count of I2S_TFR */ +#define I2S_TFR_COUNT (4U) + +/*! @name TMR - SAI Transmit Mask Register */ +/*! @{ */ +#define I2S_TMR_TWM_MASK (0xFFFFFFFFU) +#define I2S_TMR_TWM_SHIFT (0U) +/*! TWM - Transmit Word Mask + * 0b00000000000000000000000000000000..Word N is enabled. + * 0b00000000000000000000000000000001..Word N is masked. The transmit data pins are tri-stated or drive zero when masked. + */ +#define I2S_TMR_TWM(x) (((uint32_t)(((uint32_t)(x)) << I2S_TMR_TWM_SHIFT)) & I2S_TMR_TWM_MASK) +/*! @} */ + +/*! @name RCSR - SAI Receive Control Register */ +/*! @{ */ +#define I2S_RCSR_FRDE_MASK (0x1U) +#define I2S_RCSR_FRDE_SHIFT (0U) +/*! FRDE - FIFO Request DMA Enable + * 0b0..Disables the DMA request. + * 0b1..Enables the DMA request. + */ +#define I2S_RCSR_FRDE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FRDE_SHIFT)) & I2S_RCSR_FRDE_MASK) +#define I2S_RCSR_FWDE_MASK (0x2U) +#define I2S_RCSR_FWDE_SHIFT (1U) +/*! FWDE - FIFO Warning DMA Enable + * 0b0..Disables the DMA request. + * 0b1..Enables the DMA request. + */ +#define I2S_RCSR_FWDE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FWDE_SHIFT)) & I2S_RCSR_FWDE_MASK) +#define I2S_RCSR_FRIE_MASK (0x100U) +#define I2S_RCSR_FRIE_SHIFT (8U) +/*! FRIE - FIFO Request Interrupt Enable + * 0b0..Disables the interrupt. + * 0b1..Enables the interrupt. + */ +#define I2S_RCSR_FRIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FRIE_SHIFT)) & I2S_RCSR_FRIE_MASK) +#define I2S_RCSR_FWIE_MASK (0x200U) +#define I2S_RCSR_FWIE_SHIFT (9U) +/*! FWIE - FIFO Warning Interrupt Enable + * 0b0..Disables the interrupt. + * 0b1..Enables the interrupt. + */ +#define I2S_RCSR_FWIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FWIE_SHIFT)) & I2S_RCSR_FWIE_MASK) +#define I2S_RCSR_FEIE_MASK (0x400U) +#define I2S_RCSR_FEIE_SHIFT (10U) +/*! FEIE - FIFO Error Interrupt Enable + * 0b0..Disables the interrupt. + * 0b1..Enables the interrupt. + */ +#define I2S_RCSR_FEIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FEIE_SHIFT)) & I2S_RCSR_FEIE_MASK) +#define I2S_RCSR_SEIE_MASK (0x800U) +#define I2S_RCSR_SEIE_SHIFT (11U) +/*! SEIE - Sync Error Interrupt Enable + * 0b0..Disables interrupt. + * 0b1..Enables interrupt. + */ +#define I2S_RCSR_SEIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_SEIE_SHIFT)) & I2S_RCSR_SEIE_MASK) +#define I2S_RCSR_WSIE_MASK (0x1000U) +#define I2S_RCSR_WSIE_SHIFT (12U) +/*! WSIE - Word Start Interrupt Enable + * 0b0..Disables interrupt. + * 0b1..Enables interrupt. + */ +#define I2S_RCSR_WSIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_WSIE_SHIFT)) & I2S_RCSR_WSIE_MASK) +#define I2S_RCSR_FRF_MASK (0x10000U) +#define I2S_RCSR_FRF_SHIFT (16U) +/*! FRF - FIFO Request Flag + * 0b0..Receive FIFO watermark not reached. + * 0b1..Receive FIFO watermark has been reached. + */ +#define I2S_RCSR_FRF(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FRF_SHIFT)) & I2S_RCSR_FRF_MASK) +#define I2S_RCSR_FWF_MASK (0x20000U) +#define I2S_RCSR_FWF_SHIFT (17U) +/*! FWF - FIFO Warning Flag + * 0b0..No enabled receive FIFO is full. + * 0b1..Enabled receive FIFO is full. + */ +#define I2S_RCSR_FWF(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FWF_SHIFT)) & I2S_RCSR_FWF_MASK) +#define I2S_RCSR_FEF_MASK (0x40000U) +#define I2S_RCSR_FEF_SHIFT (18U) +/*! FEF - FIFO Error Flag + * 0b0..Receive overflow not detected. + * 0b1..Receive overflow detected. + */ +#define I2S_RCSR_FEF(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FEF_SHIFT)) & I2S_RCSR_FEF_MASK) +#define I2S_RCSR_SEF_MASK (0x80000U) +#define I2S_RCSR_SEF_SHIFT (19U) +/*! SEF - Sync Error Flag + * 0b0..Sync error not detected. + * 0b1..Frame sync error detected. + */ +#define I2S_RCSR_SEF(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_SEF_SHIFT)) & I2S_RCSR_SEF_MASK) +#define I2S_RCSR_WSF_MASK (0x100000U) +#define I2S_RCSR_WSF_SHIFT (20U) +/*! WSF - Word Start Flag + * 0b0..Start of word not detected. + * 0b1..Start of word detected. + */ +#define I2S_RCSR_WSF(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_WSF_SHIFT)) & I2S_RCSR_WSF_MASK) +#define I2S_RCSR_SR_MASK (0x1000000U) +#define I2S_RCSR_SR_SHIFT (24U) +/*! SR - Software Reset + * 0b0..No effect. + * 0b1..Software reset. + */ +#define I2S_RCSR_SR(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_SR_SHIFT)) & I2S_RCSR_SR_MASK) +#define I2S_RCSR_FR_MASK (0x2000000U) +#define I2S_RCSR_FR_SHIFT (25U) +/*! FR - FIFO Reset + * 0b0..No effect. + * 0b1..FIFO reset. + */ +#define I2S_RCSR_FR(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FR_SHIFT)) & I2S_RCSR_FR_MASK) +#define I2S_RCSR_BCE_MASK (0x10000000U) +#define I2S_RCSR_BCE_SHIFT (28U) +/*! BCE - Bit Clock Enable + * 0b0..Receive bit clock is disabled. + * 0b1..Receive bit clock is enabled. + */ +#define I2S_RCSR_BCE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_BCE_SHIFT)) & I2S_RCSR_BCE_MASK) +#define I2S_RCSR_DBGE_MASK (0x20000000U) +#define I2S_RCSR_DBGE_SHIFT (29U) +/*! DBGE - Debug Enable + * 0b0..Receiver is disabled in Debug mode, after completing the current frame. + * 0b1..Receiver is enabled in Debug mode. + */ +#define I2S_RCSR_DBGE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_DBGE_SHIFT)) & I2S_RCSR_DBGE_MASK) +#define I2S_RCSR_STOPE_MASK (0x40000000U) +#define I2S_RCSR_STOPE_SHIFT (30U) +/*! STOPE - Stop Enable + * 0b0..Receiver disabled in Stop mode. + * 0b1..Receiver enabled in Stop mode. + */ +#define I2S_RCSR_STOPE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_STOPE_SHIFT)) & I2S_RCSR_STOPE_MASK) +#define I2S_RCSR_RE_MASK (0x80000000U) +#define I2S_RCSR_RE_SHIFT (31U) +/*! RE - Receiver Enable + * 0b0..Receiver is disabled. + * 0b1..Receiver is enabled, or receiver has been disabled and has not yet reached end of frame. + */ +#define I2S_RCSR_RE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_RE_SHIFT)) & I2S_RCSR_RE_MASK) +/*! @} */ + +/*! @name RCR1 - SAI Receive Configuration 1 Register */ +/*! @{ */ +#define I2S_RCR1_RFW_MASK (0x1FU) +#define I2S_RCR1_RFW_SHIFT (0U) +#define I2S_RCR1_RFW(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR1_RFW_SHIFT)) & I2S_RCR1_RFW_MASK) +/*! @} */ + +/*! @name RCR2 - SAI Receive Configuration 2 Register */ +/*! @{ */ +#define I2S_RCR2_DIV_MASK (0xFFU) +#define I2S_RCR2_DIV_SHIFT (0U) +#define I2S_RCR2_DIV(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_DIV_SHIFT)) & I2S_RCR2_DIV_MASK) +#define I2S_RCR2_BCD_MASK (0x1000000U) +#define I2S_RCR2_BCD_SHIFT (24U) +/*! BCD - Bit Clock Direction + * 0b0..Bit clock is generated externally in Slave mode. + * 0b1..Bit clock is generated internally in Master mode. + */ +#define I2S_RCR2_BCD(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_BCD_SHIFT)) & I2S_RCR2_BCD_MASK) +#define I2S_RCR2_BCP_MASK (0x2000000U) +#define I2S_RCR2_BCP_SHIFT (25U) +/*! BCP - Bit Clock Polarity + * 0b0..Bit Clock is active high with drive outputs on rising edge and sample inputs on falling edge. + * 0b1..Bit Clock is active low with drive outputs on falling edge and sample inputs on rising edge. + */ +#define I2S_RCR2_BCP(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_BCP_SHIFT)) & I2S_RCR2_BCP_MASK) +#define I2S_RCR2_MSEL_MASK (0xC000000U) +#define I2S_RCR2_MSEL_SHIFT (26U) +/*! MSEL - MCLK Select + * 0b00..Bus Clock selected. + * 0b01..Master Clock (MCLK) 1 option selected. + * 0b10..Master Clock (MCLK) 2 option selected. + * 0b11..Master Clock (MCLK) 3 option selected. + */ +#define I2S_RCR2_MSEL(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_MSEL_SHIFT)) & I2S_RCR2_MSEL_MASK) +#define I2S_RCR2_BCI_MASK (0x10000000U) +#define I2S_RCR2_BCI_SHIFT (28U) +/*! BCI - Bit Clock Input + * 0b0..No effect. + * 0b1..Internal logic is clocked as if bit clock was externally generated. + */ +#define I2S_RCR2_BCI(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_BCI_SHIFT)) & I2S_RCR2_BCI_MASK) +#define I2S_RCR2_BCS_MASK (0x20000000U) +#define I2S_RCR2_BCS_SHIFT (29U) +/*! BCS - Bit Clock Swap + * 0b0..Use the normal bit clock source. + * 0b1..Swap the bit clock source. + */ +#define I2S_RCR2_BCS(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_BCS_SHIFT)) & I2S_RCR2_BCS_MASK) +#define I2S_RCR2_SYNC_MASK (0xC0000000U) +#define I2S_RCR2_SYNC_SHIFT (30U) +/*! SYNC - Synchronous Mode + * 0b00..Asynchronous mode. + * 0b01..Synchronous with transmitter. + * 0b10..Reserved. + * 0b11..Reserved. + */ +#define I2S_RCR2_SYNC(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_SYNC_SHIFT)) & I2S_RCR2_SYNC_MASK) +/*! @} */ + +/*! @name RCR3 - SAI Receive Configuration 3 Register */ +/*! @{ */ +#define I2S_RCR3_WDFL_MASK (0x1FU) +#define I2S_RCR3_WDFL_SHIFT (0U) +#define I2S_RCR3_WDFL(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR3_WDFL_SHIFT)) & I2S_RCR3_WDFL_MASK) +#define I2S_RCR3_RCE_MASK (0xF0000U) +#define I2S_RCR3_RCE_SHIFT (16U) +#define I2S_RCR3_RCE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR3_RCE_SHIFT)) & I2S_RCR3_RCE_MASK) +#define I2S_RCR3_CFR_MASK (0xF000000U) +#define I2S_RCR3_CFR_SHIFT (24U) +#define I2S_RCR3_CFR(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR3_CFR_SHIFT)) & I2S_RCR3_CFR_MASK) +/*! @} */ + +/*! @name RCR4 - SAI Receive Configuration 4 Register */ +/*! @{ */ +#define I2S_RCR4_FSD_MASK (0x1U) +#define I2S_RCR4_FSD_SHIFT (0U) +/*! FSD - Frame Sync Direction + * 0b0..Frame Sync is generated externally in Slave mode. + * 0b1..Frame Sync is generated internally in Master mode. + */ +#define I2S_RCR4_FSD(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FSD_SHIFT)) & I2S_RCR4_FSD_MASK) +#define I2S_RCR4_FSP_MASK (0x2U) +#define I2S_RCR4_FSP_SHIFT (1U) +/*! FSP - Frame Sync Polarity + * 0b0..Frame sync is active high. + * 0b1..Frame sync is active low. + */ +#define I2S_RCR4_FSP(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FSP_SHIFT)) & I2S_RCR4_FSP_MASK) +#define I2S_RCR4_ONDEM_MASK (0x4U) +#define I2S_RCR4_ONDEM_SHIFT (2U) +/*! ONDEM - On Demand Mode + * 0b0..Internal frame sync is generated continuously. + * 0b1..Internal frame sync is generated when the FIFO warning flag is clear. + */ +#define I2S_RCR4_ONDEM(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_ONDEM_SHIFT)) & I2S_RCR4_ONDEM_MASK) +#define I2S_RCR4_FSE_MASK (0x8U) +#define I2S_RCR4_FSE_SHIFT (3U) +/*! FSE - Frame Sync Early + * 0b0..Frame sync asserts with the first bit of the frame. + * 0b1..Frame sync asserts one bit before the first bit of the frame. + */ +#define I2S_RCR4_FSE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FSE_SHIFT)) & I2S_RCR4_FSE_MASK) +#define I2S_RCR4_MF_MASK (0x10U) +#define I2S_RCR4_MF_SHIFT (4U) +/*! MF - MSB First + * 0b0..LSB is received first. + * 0b1..MSB is received first. + */ +#define I2S_RCR4_MF(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_MF_SHIFT)) & I2S_RCR4_MF_MASK) +#define I2S_RCR4_SYWD_MASK (0x1F00U) +#define I2S_RCR4_SYWD_SHIFT (8U) +#define I2S_RCR4_SYWD(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_SYWD_SHIFT)) & I2S_RCR4_SYWD_MASK) +#define I2S_RCR4_FRSZ_MASK (0x1F0000U) +#define I2S_RCR4_FRSZ_SHIFT (16U) +#define I2S_RCR4_FRSZ(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FRSZ_SHIFT)) & I2S_RCR4_FRSZ_MASK) +#define I2S_RCR4_FPACK_MASK (0x3000000U) +#define I2S_RCR4_FPACK_SHIFT (24U) +/*! FPACK - FIFO Packing Mode + * 0b00..FIFO packing is disabled + * 0b01..Reserved. + * 0b10..8-bit FIFO packing is enabled + * 0b11..16-bit FIFO packing is enabled + */ +#define I2S_RCR4_FPACK(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FPACK_SHIFT)) & I2S_RCR4_FPACK_MASK) +#define I2S_RCR4_FCOMB_MASK (0xC000000U) +#define I2S_RCR4_FCOMB_SHIFT (26U) +/*! FCOMB - FIFO Combine Mode + * 0b00..FIFO combine mode disabled. + * 0b01..FIFO combine mode enabled on FIFO writes (from receive shift registers). + * 0b10..FIFO combine mode enabled on FIFO reads (by software). + * 0b11..FIFO combine mode enabled on FIFO writes (from receive shift registers) and reads (by software). + */ +#define I2S_RCR4_FCOMB(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FCOMB_SHIFT)) & I2S_RCR4_FCOMB_MASK) +#define I2S_RCR4_FCONT_MASK (0x10000000U) +#define I2S_RCR4_FCONT_SHIFT (28U) +/*! FCONT - FIFO Continue on Error + * 0b0..On FIFO error, the SAI will continue from the start of the next frame after the FIFO error flag has been cleared. + * 0b1..On FIFO error, the SAI will continue from the same word that caused the FIFO error to set after the FIFO warning flag has been cleared. + */ +#define I2S_RCR4_FCONT(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FCONT_SHIFT)) & I2S_RCR4_FCONT_MASK) +/*! @} */ + +/*! @name RCR5 - SAI Receive Configuration 5 Register */ +/*! @{ */ +#define I2S_RCR5_FBT_MASK (0x1F00U) +#define I2S_RCR5_FBT_SHIFT (8U) +#define I2S_RCR5_FBT(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR5_FBT_SHIFT)) & I2S_RCR5_FBT_MASK) +#define I2S_RCR5_W0W_MASK (0x1F0000U) +#define I2S_RCR5_W0W_SHIFT (16U) +#define I2S_RCR5_W0W(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR5_W0W_SHIFT)) & I2S_RCR5_W0W_MASK) +#define I2S_RCR5_WNW_MASK (0x1F000000U) +#define I2S_RCR5_WNW_SHIFT (24U) +#define I2S_RCR5_WNW(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR5_WNW_SHIFT)) & I2S_RCR5_WNW_MASK) +/*! @} */ + +/*! @name RDR - SAI Receive Data Register */ +/*! @{ */ +#define I2S_RDR_RDR_MASK (0xFFFFFFFFU) +#define I2S_RDR_RDR_SHIFT (0U) +#define I2S_RDR_RDR(x) (((uint32_t)(((uint32_t)(x)) << I2S_RDR_RDR_SHIFT)) & I2S_RDR_RDR_MASK) +/*! @} */ + +/* The count of I2S_RDR */ +#define I2S_RDR_COUNT (4U) + +/*! @name RFR - SAI Receive FIFO Register */ +/*! @{ */ +#define I2S_RFR_RFP_MASK (0x3FU) +#define I2S_RFR_RFP_SHIFT (0U) +#define I2S_RFR_RFP(x) (((uint32_t)(((uint32_t)(x)) << I2S_RFR_RFP_SHIFT)) & I2S_RFR_RFP_MASK) +#define I2S_RFR_RCP_MASK (0x8000U) +#define I2S_RFR_RCP_SHIFT (15U) +/*! RCP - Receive Channel Pointer + * 0b0..No effect. + * 0b1..FIFO combine is enabled for FIFO reads and this FIFO will be read on the next FIFO read. + */ +#define I2S_RFR_RCP(x) (((uint32_t)(((uint32_t)(x)) << I2S_RFR_RCP_SHIFT)) & I2S_RFR_RCP_MASK) +#define I2S_RFR_WFP_MASK (0x3F0000U) +#define I2S_RFR_WFP_SHIFT (16U) +#define I2S_RFR_WFP(x) (((uint32_t)(((uint32_t)(x)) << I2S_RFR_WFP_SHIFT)) & I2S_RFR_WFP_MASK) +/*! @} */ + +/* The count of I2S_RFR */ +#define I2S_RFR_COUNT (4U) + +/*! @name RMR - SAI Receive Mask Register */ +/*! @{ */ +#define I2S_RMR_RWM_MASK (0xFFFFFFFFU) +#define I2S_RMR_RWM_SHIFT (0U) +/*! RWM - Receive Word Mask + * 0b00000000000000000000000000000000..Word N is enabled. + * 0b00000000000000000000000000000001..Word N is masked. + */ +#define I2S_RMR_RWM(x) (((uint32_t)(((uint32_t)(x)) << I2S_RMR_RWM_SHIFT)) & I2S_RMR_RWM_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group I2S_Register_Masks */ + + +/* I2S - Peripheral instance base addresses */ +/** Peripheral SAI1 base address */ +#define SAI1_BASE (0x40384000u) +/** Peripheral SAI1 base pointer */ +#define SAI1 ((I2S_Type *)SAI1_BASE) +/** Peripheral SAI2 base address */ +#define SAI2_BASE (0x40388000u) +/** Peripheral SAI2 base pointer */ +#define SAI2 ((I2S_Type *)SAI2_BASE) +/** Peripheral SAI3 base address */ +#define SAI3_BASE (0x4038C000u) +/** Peripheral SAI3 base pointer */ +#define SAI3 ((I2S_Type *)SAI3_BASE) +/** Array initializer of I2S peripheral base addresses */ +#define I2S_BASE_ADDRS { 0u, SAI1_BASE, SAI2_BASE, SAI3_BASE } +/** Array initializer of I2S peripheral base pointers */ +#define I2S_BASE_PTRS { (I2S_Type *)0u, SAI1, SAI2, SAI3 } +/** Interrupt vectors for the I2S peripheral type */ +#define I2S_RX_IRQS { NotAvail_IRQn, SAI1_IRQn, SAI2_IRQn, SAI3_RX_IRQn } +#define I2S_TX_IRQS { NotAvail_IRQn, SAI1_IRQn, SAI2_IRQn, SAI3_TX_IRQn } + +/*! + * @} + */ /* end of group I2S_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- IOMUXC Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup IOMUXC_Peripheral_Access_Layer IOMUXC Peripheral Access Layer + * @{ + */ + +/** IOMUXC - Register Layout Typedef */ +typedef struct { + uint8_t RESERVED_0[20]; + __IO uint32_t SW_MUX_CTL_PAD[124]; /**< SW_MUX_CTL_PAD_GPIO_EMC_00 SW MUX Control Register..SW_MUX_CTL_PAD_GPIO_SD_B1_11 SW MUX Control Register, array offset: 0x14, array step: 0x4 */ + __IO uint32_t SW_PAD_CTL_PAD[124]; /**< SW_PAD_CTL_PAD_GPIO_EMC_00 SW PAD Control Register..SW_PAD_CTL_PAD_GPIO_SD_B1_11 SW PAD Control Register, array offset: 0x204, array step: 0x4 */ + __IO uint32_t SELECT_INPUT[154]; /**< ANATOP_USB_OTG1_ID_SELECT_INPUT DAISY Register..XBAR1_IN23_SELECT_INPUT DAISY Register, array offset: 0x3F4, array step: 0x4 */ +} IOMUXC_Type; + +/* ---------------------------------------------------------------------------- + -- IOMUXC Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup IOMUXC_Register_Masks IOMUXC Register Masks + * @{ + */ + +/*! @name SW_MUX_CTL_PAD - SW_MUX_CTL_PAD_GPIO_EMC_00 SW MUX Control Register..SW_MUX_CTL_PAD_GPIO_SD_B1_11 SW MUX Control Register */ +/*! @{ */ +#define IOMUXC_SW_MUX_CTL_PAD_MUX_MODE_MASK (0x7U) +#define IOMUXC_SW_MUX_CTL_PAD_MUX_MODE_SHIFT (0U) +/*! MUX_MODE - MUX Mode Select Field. + * 0b000..Select mux mode: ALT0 mux port: LPI2C4_SCL of instance: lpi2c4 + * 0b001..Select mux mode: ALT1 mux port: CCM_PMIC_READY of instance: ccm + * 0b010..Select mux mode: ALT2 mux port: LPUART1_TX of instance: lpuart1 + * 0b011..Select mux mode: ALT3 mux port: WDOG2_WDOG_B of instance: wdog2 + * 0b100..Select mux mode: ALT4 mux port: FLEXPWM1_PWMX02 of instance: flexpwm1 + * 0b101..Select mux mode: ALT5 mux port: GPIO1_IO12 of instance: gpio1 + * 0b110..Select mux mode: ALT6 mux port: ENET_1588_EVENT1_OUT of instance: enet + * 0b111..Select mux mode: ALT7 mux port: NMI_GLUE_NMI of instance: nmi_glue + */ +#define IOMUXC_SW_MUX_CTL_PAD_MUX_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_MUX_CTL_PAD_MUX_MODE_SHIFT)) & IOMUXC_SW_MUX_CTL_PAD_MUX_MODE_MASK) +#define IOMUXC_SW_MUX_CTL_PAD_SION_MASK (0x10U) +#define IOMUXC_SW_MUX_CTL_PAD_SION_SHIFT (4U) +/*! SION - Software Input On Field. + * 0b1..Force input path of pad GPIO_SD_B1_11 + * 0b0..Input Path is determined by functionality + */ +#define IOMUXC_SW_MUX_CTL_PAD_SION(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_MUX_CTL_PAD_SION_SHIFT)) & IOMUXC_SW_MUX_CTL_PAD_SION_MASK) +/*! @} */ + +/* The count of IOMUXC_SW_MUX_CTL_PAD */ +#define IOMUXC_SW_MUX_CTL_PAD_COUNT (124U) + +/*! @name SW_PAD_CTL_PAD - SW_PAD_CTL_PAD_GPIO_EMC_00 SW PAD Control Register..SW_PAD_CTL_PAD_GPIO_SD_B1_11 SW PAD Control Register */ +/*! @{ */ +#define IOMUXC_SW_PAD_CTL_PAD_SRE_MASK (0x1U) +#define IOMUXC_SW_PAD_CTL_PAD_SRE_SHIFT (0U) +/*! SRE - Slew Rate Field + * 0b0..Slow Slew Rate + * 0b1..Fast Slew Rate + */ +#define IOMUXC_SW_PAD_CTL_PAD_SRE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_PAD_CTL_PAD_SRE_SHIFT)) & IOMUXC_SW_PAD_CTL_PAD_SRE_MASK) +#define IOMUXC_SW_PAD_CTL_PAD_DSE_MASK (0x38U) +#define IOMUXC_SW_PAD_CTL_PAD_DSE_SHIFT (3U) +/*! DSE - Drive Strength Field + * 0b000..output driver disabled; + * 0b001..R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) + * 0b010..R0/2 + * 0b011..R0/3 + * 0b100..R0/4 + * 0b101..R0/5 + * 0b110..R0/6 + * 0b111..R0/7 + */ +#define IOMUXC_SW_PAD_CTL_PAD_DSE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_PAD_CTL_PAD_DSE_SHIFT)) & IOMUXC_SW_PAD_CTL_PAD_DSE_MASK) +#define IOMUXC_SW_PAD_CTL_PAD_SPEED_MASK (0xC0U) +#define IOMUXC_SW_PAD_CTL_PAD_SPEED_SHIFT (6U) +/*! SPEED - Speed Field + * 0b00..low(50MHz) + * 0b01..medium(100MHz) + * 0b10..medium(100MHz) + * 0b11..max(200MHz) + */ +#define IOMUXC_SW_PAD_CTL_PAD_SPEED(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_PAD_CTL_PAD_SPEED_SHIFT)) & IOMUXC_SW_PAD_CTL_PAD_SPEED_MASK) +#define IOMUXC_SW_PAD_CTL_PAD_ODE_MASK (0x800U) +#define IOMUXC_SW_PAD_CTL_PAD_ODE_SHIFT (11U) +/*! ODE - Open Drain Enable Field + * 0b0..Open Drain Disabled + * 0b1..Open Drain Enabled + */ +#define IOMUXC_SW_PAD_CTL_PAD_ODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_PAD_CTL_PAD_ODE_SHIFT)) & IOMUXC_SW_PAD_CTL_PAD_ODE_MASK) +#define IOMUXC_SW_PAD_CTL_PAD_PKE_MASK (0x1000U) +#define IOMUXC_SW_PAD_CTL_PAD_PKE_SHIFT (12U) +/*! PKE - Pull / Keep Enable Field + * 0b0..Pull/Keeper Disabled + * 0b1..Pull/Keeper Enabled + */ +#define IOMUXC_SW_PAD_CTL_PAD_PKE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_PAD_CTL_PAD_PKE_SHIFT)) & IOMUXC_SW_PAD_CTL_PAD_PKE_MASK) +#define IOMUXC_SW_PAD_CTL_PAD_PUE_MASK (0x2000U) +#define IOMUXC_SW_PAD_CTL_PAD_PUE_SHIFT (13U) +/*! PUE - Pull / Keep Select Field + * 0b0..Keeper + * 0b1..Pull + */ +#define IOMUXC_SW_PAD_CTL_PAD_PUE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_PAD_CTL_PAD_PUE_SHIFT)) & IOMUXC_SW_PAD_CTL_PAD_PUE_MASK) +#define IOMUXC_SW_PAD_CTL_PAD_PUS_MASK (0xC000U) +#define IOMUXC_SW_PAD_CTL_PAD_PUS_SHIFT (14U) +/*! PUS - Pull Up / Down Config. Field + * 0b00..100K Ohm Pull Down + * 0b01..47K Ohm Pull Up + * 0b10..100K Ohm Pull Up + * 0b11..22K Ohm Pull Up + */ +#define IOMUXC_SW_PAD_CTL_PAD_PUS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_PAD_CTL_PAD_PUS_SHIFT)) & IOMUXC_SW_PAD_CTL_PAD_PUS_MASK) +#define IOMUXC_SW_PAD_CTL_PAD_HYS_MASK (0x10000U) +#define IOMUXC_SW_PAD_CTL_PAD_HYS_SHIFT (16U) +/*! HYS - Hyst. Enable Field + * 0b0..Hysteresis Disabled + * 0b1..Hysteresis Enabled + */ +#define IOMUXC_SW_PAD_CTL_PAD_HYS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_PAD_CTL_PAD_HYS_SHIFT)) & IOMUXC_SW_PAD_CTL_PAD_HYS_MASK) +/*! @} */ + +/* The count of IOMUXC_SW_PAD_CTL_PAD */ +#define IOMUXC_SW_PAD_CTL_PAD_COUNT (124U) + +/*! @name SELECT_INPUT - ANATOP_USB_OTG1_ID_SELECT_INPUT DAISY Register..XBAR1_IN23_SELECT_INPUT DAISY Register */ +/*! @{ */ +#define IOMUXC_SELECT_INPUT_DAISY_MASK (0x7U) /* Merged from fields with different position or width, of widths (1, 2, 3), largest definition used */ +#define IOMUXC_SELECT_INPUT_DAISY_SHIFT (0U) +/*! DAISY - Selecting Pads Involved in Daisy Chain. + * 0b000..Selecting Pad: GPIO_SD_B1_03 for Mode: ALT6 + * 0b001..Selecting Pad: GPIO_AD_B0_12 for Mode: ALT1 + * 0b010..Selecting Pad: GPIO_AD_B1_01 for Mode: ALT4 + * 0b011..Selecting Pad: GPIO_AD_B1_08 for Mode: ALT3 + * 0b100..Selecting Pad: GPIO_EMC_32 for Mode: ALT3 + */ +#define IOMUXC_SELECT_INPUT_DAISY(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SELECT_INPUT_DAISY_SHIFT)) & IOMUXC_SELECT_INPUT_DAISY_MASK) /* Merged from fields with different position or width, of widths (1, 2, 3), largest definition used */ +/*! @} */ + +/* The count of IOMUXC_SELECT_INPUT */ +#define IOMUXC_SELECT_INPUT_COUNT (154U) + + +/*! + * @} + */ /* end of group IOMUXC_Register_Masks */ + + +/* IOMUXC - Peripheral instance base addresses */ +/** Peripheral IOMUXC base address */ +#define IOMUXC_BASE (0x401F8000u) +/** Peripheral IOMUXC base pointer */ +#define IOMUXC ((IOMUXC_Type *)IOMUXC_BASE) +/** Array initializer of IOMUXC peripheral base addresses */ +#define IOMUXC_BASE_ADDRS { IOMUXC_BASE } +/** Array initializer of IOMUXC peripheral base pointers */ +#define IOMUXC_BASE_PTRS { IOMUXC } + +/*! + * @} + */ /* end of group IOMUXC_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- IOMUXC_GPR Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup IOMUXC_GPR_Peripheral_Access_Layer IOMUXC_GPR Peripheral Access Layer + * @{ + */ + +/** IOMUXC_GPR - Register Layout Typedef */ +typedef struct { + uint32_t GPR0; /**< GPR0 General Purpose Register, offset: 0x0 */ + __IO uint32_t GPR1; /**< GPR1 General Purpose Register, offset: 0x4 */ + __IO uint32_t GPR2; /**< GPR2 General Purpose Register, offset: 0x8 */ + __IO uint32_t GPR3; /**< GPR3 General Purpose Register, offset: 0xC */ + __IO uint32_t GPR4; /**< GPR4 General Purpose Register, offset: 0x10 */ + __IO uint32_t GPR5; /**< GPR5 General Purpose Register, offset: 0x14 */ + __IO uint32_t GPR6; /**< GPR6 General Purpose Register, offset: 0x18 */ + __IO uint32_t GPR7; /**< GPR7 General Purpose Register, offset: 0x1C */ + __IO uint32_t GPR8; /**< GPR8 General Purpose Register, offset: 0x20 */ + uint32_t GPR9; /**< GPR9 General Purpose Register, offset: 0x24 */ + __IO uint32_t GPR10; /**< GPR10 General Purpose Register, offset: 0x28 */ + __IO uint32_t GPR11; /**< GPR11 General Purpose Register, offset: 0x2C */ + __IO uint32_t GPR12; /**< GPR12 General Purpose Register, offset: 0x30 */ + __IO uint32_t GPR13; /**< GPR13 General Purpose Register, offset: 0x34 */ + __IO uint32_t GPR14; /**< GPR14 General Purpose Register, offset: 0x38 */ + uint32_t GPR15; /**< GPR15 General Purpose Register, offset: 0x3C */ + __IO uint32_t GPR16; /**< GPR16 General Purpose Register, offset: 0x40 */ + __IO uint32_t GPR17; /**< GPR17 General Purpose Register, offset: 0x44 */ + __IO uint32_t GPR18; /**< GPR18 General Purpose Register, offset: 0x48 */ + __IO uint32_t GPR19; /**< GPR19 General Purpose Register, offset: 0x4C */ + __IO uint32_t GPR20; /**< GPR20 General Purpose Register, offset: 0x50 */ + __IO uint32_t GPR21; /**< GPR21 General Purpose Register, offset: 0x54 */ + __IO uint32_t GPR22; /**< GPR22 General Purpose Register, offset: 0x58 */ + __IO uint32_t GPR23; /**< GPR23 General Purpose Register, offset: 0x5C */ + __IO uint32_t GPR24; /**< GPR24 General Purpose Register, offset: 0x60 */ + __IO uint32_t GPR25; /**< GPR25 General Purpose Register, offset: 0x64 */ +} IOMUXC_GPR_Type; + +/* ---------------------------------------------------------------------------- + -- IOMUXC_GPR Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup IOMUXC_GPR_Register_Masks IOMUXC_GPR Register Masks + * @{ + */ + +/*! @name GPR1 - GPR1 General Purpose Register */ +/*! @{ */ +#define IOMUXC_GPR_GPR1_SAI1_MCLK1_SEL_MASK (0x7U) +#define IOMUXC_GPR_GPR1_SAI1_MCLK1_SEL_SHIFT (0U) +/*! SAI1_MCLK1_SEL + * 0b000..ccm.ssi1_clk_root + * 0b001..ccm.ssi2_clk_root + * 0b010..ccm.ssi3_clk_root + * 0b011..iomux.sai1_ipg_clk_sai_mclk + * 0b100..iomux.sai2_ipg_clk_sai_mclk + * 0b101..iomux.sai3_ipg_clk_sai_mclk + * 0b110..Reserved + * 0b111..Reserved + */ +#define IOMUXC_GPR_GPR1_SAI1_MCLK1_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_SAI1_MCLK1_SEL_SHIFT)) & IOMUXC_GPR_GPR1_SAI1_MCLK1_SEL_MASK) +#define IOMUXC_GPR_GPR1_SAI1_MCLK2_SEL_MASK (0x38U) +#define IOMUXC_GPR_GPR1_SAI1_MCLK2_SEL_SHIFT (3U) +/*! SAI1_MCLK2_SEL + * 0b000..ccm.ssi1_clk_root + * 0b001..ccm.ssi2_clk_root + * 0b010..ccm.ssi3_clk_root + * 0b011..iomux.sai1_ipg_clk_sai_mclk + * 0b100..iomux.sai2_ipg_clk_sai_mclk + * 0b101..iomux.sai3_ipg_clk_sai_mclk + * 0b110..Reserved + * 0b111..Reserved + */ +#define IOMUXC_GPR_GPR1_SAI1_MCLK2_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_SAI1_MCLK2_SEL_SHIFT)) & IOMUXC_GPR_GPR1_SAI1_MCLK2_SEL_MASK) +#define IOMUXC_GPR_GPR1_SAI1_MCLK3_SEL_MASK (0xC0U) +#define IOMUXC_GPR_GPR1_SAI1_MCLK3_SEL_SHIFT (6U) +/*! SAI1_MCLK3_SEL + * 0b00..ccm.spdif0_clk_root + * 0b01..iomux.spdif_tx_clk2 + * 0b10..spdif.spdif_srclk + * 0b11..spdif.spdif_outclock + */ +#define IOMUXC_GPR_GPR1_SAI1_MCLK3_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_SAI1_MCLK3_SEL_SHIFT)) & IOMUXC_GPR_GPR1_SAI1_MCLK3_SEL_MASK) +#define IOMUXC_GPR_GPR1_SAI2_MCLK3_SEL_MASK (0x300U) +#define IOMUXC_GPR_GPR1_SAI2_MCLK3_SEL_SHIFT (8U) +/*! SAI2_MCLK3_SEL + * 0b00..ccm.spdif0_clk_root + * 0b01..iomux.spdif_tx_clk2 + * 0b10..spdif.spdif_srclk + * 0b11..spdif.spdif_outclock + */ +#define IOMUXC_GPR_GPR1_SAI2_MCLK3_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_SAI2_MCLK3_SEL_SHIFT)) & IOMUXC_GPR_GPR1_SAI2_MCLK3_SEL_MASK) +#define IOMUXC_GPR_GPR1_SAI3_MCLK3_SEL_MASK (0xC00U) +#define IOMUXC_GPR_GPR1_SAI3_MCLK3_SEL_SHIFT (10U) +/*! SAI3_MCLK3_SEL + * 0b00..ccm.spdif0_clk_root + * 0b01..iomux.spdif_tx_clk2 + * 0b10..spdif.spdif_srclk + * 0b11..spdif.spdif_outclock + */ +#define IOMUXC_GPR_GPR1_SAI3_MCLK3_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_SAI3_MCLK3_SEL_SHIFT)) & IOMUXC_GPR_GPR1_SAI3_MCLK3_SEL_MASK) +#define IOMUXC_GPR_GPR1_GINT_MASK (0x1000U) +#define IOMUXC_GPR_GPR1_GINT_SHIFT (12U) +/*! GINT + * 0b0..Global interrupt request is not asserted. + * 0b1..Global interrupt request is asserted. + */ +#define IOMUXC_GPR_GPR1_GINT(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_GINT_SHIFT)) & IOMUXC_GPR_GPR1_GINT_MASK) +#define IOMUXC_GPR_GPR1_ENET1_CLK_SEL_MASK (0x2000U) +#define IOMUXC_GPR_GPR1_ENET1_CLK_SEL_SHIFT (13U) +/*! ENET1_CLK_SEL + * 0b0..ENET1 TX reference clock driven by ref_enetpll0. This clock is also output to pins via the IOMUX. ENET_REF_CLK1 function. + * 0b1..Gets ENET1 TX reference clock from the ENET1_TX_CLK pin. In this use case, an external OSC provides the clock for both the external PHY and the internal controller. + */ +#define IOMUXC_GPR_GPR1_ENET1_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_ENET1_CLK_SEL_SHIFT)) & IOMUXC_GPR_GPR1_ENET1_CLK_SEL_MASK) +#define IOMUXC_GPR_GPR1_USB_EXP_MODE_MASK (0x8000U) +#define IOMUXC_GPR_GPR1_USB_EXP_MODE_SHIFT (15U) +/*! USB_EXP_MODE + * 0b0..Exposure mode is disabled. + * 0b1..Exposure mode is enabled. + */ +#define IOMUXC_GPR_GPR1_USB_EXP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_USB_EXP_MODE_SHIFT)) & IOMUXC_GPR_GPR1_USB_EXP_MODE_MASK) +#define IOMUXC_GPR_GPR1_ENET1_TX_CLK_DIR_MASK (0x20000U) +#define IOMUXC_GPR_GPR1_ENET1_TX_CLK_DIR_SHIFT (17U) +/*! ENET1_TX_CLK_DIR + * 0b0..ENET1_TX_CLK output driver is disabled and ENET_REF_CLK1 is a clock input. + * 0b1..ENET1_TX_CLK output driver is enabled and ENET_REF_CLK1 is an output driven by ref_enetpll0. + */ +#define IOMUXC_GPR_GPR1_ENET1_TX_CLK_DIR(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_ENET1_TX_CLK_DIR_SHIFT)) & IOMUXC_GPR_GPR1_ENET1_TX_CLK_DIR_MASK) +#define IOMUXC_GPR_GPR1_SAI1_MCLK_DIR_MASK (0x80000U) +#define IOMUXC_GPR_GPR1_SAI1_MCLK_DIR_SHIFT (19U) +/*! SAI1_MCLK_DIR + * 0b0..sai1.MCLK is input signal + * 0b1..sai1.MCLK is output signal + */ +#define IOMUXC_GPR_GPR1_SAI1_MCLK_DIR(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_SAI1_MCLK_DIR_SHIFT)) & IOMUXC_GPR_GPR1_SAI1_MCLK_DIR_MASK) +#define IOMUXC_GPR_GPR1_SAI2_MCLK_DIR_MASK (0x100000U) +#define IOMUXC_GPR_GPR1_SAI2_MCLK_DIR_SHIFT (20U) +/*! SAI2_MCLK_DIR + * 0b0..sai2.MCLK is input signal + * 0b1..sai2.MCLK is output signal + */ +#define IOMUXC_GPR_GPR1_SAI2_MCLK_DIR(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_SAI2_MCLK_DIR_SHIFT)) & IOMUXC_GPR_GPR1_SAI2_MCLK_DIR_MASK) +#define IOMUXC_GPR_GPR1_SAI3_MCLK_DIR_MASK (0x200000U) +#define IOMUXC_GPR_GPR1_SAI3_MCLK_DIR_SHIFT (21U) +/*! SAI3_MCLK_DIR + * 0b0..sai3.MCLK is input signal + * 0b1..sai3.MCLK is output signal + */ +#define IOMUXC_GPR_GPR1_SAI3_MCLK_DIR(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_SAI3_MCLK_DIR_SHIFT)) & IOMUXC_GPR_GPR1_SAI3_MCLK_DIR_MASK) +#define IOMUXC_GPR_GPR1_EXC_MON_MASK (0x400000U) +#define IOMUXC_GPR_GPR1_EXC_MON_SHIFT (22U) +/*! EXC_MON + * 0b0..OKAY response + * 0b1..SLVError response + */ +#define IOMUXC_GPR_GPR1_EXC_MON(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_EXC_MON_SHIFT)) & IOMUXC_GPR_GPR1_EXC_MON_MASK) +#define IOMUXC_GPR_GPR1_ENET_IPG_CLK_S_EN_MASK (0x800000U) +#define IOMUXC_GPR_GPR1_ENET_IPG_CLK_S_EN_SHIFT (23U) +/*! ENET_IPG_CLK_S_EN + * 0b0..ipg_clk_s is gated when there is no IPS access + * 0b1..ipg_clk_s is always on + */ +#define IOMUXC_GPR_GPR1_ENET_IPG_CLK_S_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_ENET_IPG_CLK_S_EN_SHIFT)) & IOMUXC_GPR_GPR1_ENET_IPG_CLK_S_EN_MASK) +#define IOMUXC_GPR_GPR1_CM7_FORCE_HCLK_EN_MASK (0x80000000U) +#define IOMUXC_GPR_GPR1_CM7_FORCE_HCLK_EN_SHIFT (31U) +/*! CM7_FORCE_HCLK_EN + * 0b0..AHB clock is not running (gated) + * 0b1..AHB clock is running (enabled) + */ +#define IOMUXC_GPR_GPR1_CM7_FORCE_HCLK_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_CM7_FORCE_HCLK_EN_SHIFT)) & IOMUXC_GPR_GPR1_CM7_FORCE_HCLK_EN_MASK) +/*! @} */ + +/*! @name GPR2 - GPR2 General Purpose Register */ +/*! @{ */ +#define IOMUXC_GPR_GPR2_L2_MEM_EN_POWERSAVING_MASK (0x1000U) +#define IOMUXC_GPR_GPR2_L2_MEM_EN_POWERSAVING_SHIFT (12U) +/*! L2_MEM_EN_POWERSAVING + * 0b0..none memory power saving features enabled, SHUTDOWN/DEEPSLEEP/LIGHTSLEEP will have no effect + * 0b1..memory power saving features enabled, set SHUTDOWN/DEEPSLEEP/LIGHTSLEEP(priority high to low) to enable power saving levels + */ +#define IOMUXC_GPR_GPR2_L2_MEM_EN_POWERSAVING(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR2_L2_MEM_EN_POWERSAVING_SHIFT)) & IOMUXC_GPR_GPR2_L2_MEM_EN_POWERSAVING_MASK) +#define IOMUXC_GPR_GPR2_L2_MEM_DEEPSLEEP_MASK (0x4000U) +#define IOMUXC_GPR_GPR2_L2_MEM_DEEPSLEEP_SHIFT (14U) +/*! L2_MEM_DEEPSLEEP + * 0b0..no force sleep control supported, memory deep sleep mode only entered when whole system in stop mode + * 0b1..force memory into deep sleep mode + */ +#define IOMUXC_GPR_GPR2_L2_MEM_DEEPSLEEP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR2_L2_MEM_DEEPSLEEP_SHIFT)) & IOMUXC_GPR_GPR2_L2_MEM_DEEPSLEEP_MASK) +#define IOMUXC_GPR_GPR2_MQS_CLK_DIV_MASK (0xFF0000U) +#define IOMUXC_GPR_GPR2_MQS_CLK_DIV_SHIFT (16U) +/*! MQS_CLK_DIV + * 0b00000000..mclk frequency = hmclk frequency + * 0b00000001..mclk frequency = 1/2 * hmclk frequency + * 0b00000010..mclk frequency = 1/3 * hmclk frequency + * 0b11111111..mclk frequency = 1/256 * hmclk frequency + */ +#define IOMUXC_GPR_GPR2_MQS_CLK_DIV(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR2_MQS_CLK_DIV_SHIFT)) & IOMUXC_GPR_GPR2_MQS_CLK_DIV_MASK) +#define IOMUXC_GPR_GPR2_MQS_SW_RST_MASK (0x1000000U) +#define IOMUXC_GPR_GPR2_MQS_SW_RST_SHIFT (24U) +/*! MQS_SW_RST + * 0b0..Exit software reset for MQS + * 0b1..Enable software reset for MQS + */ +#define IOMUXC_GPR_GPR2_MQS_SW_RST(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR2_MQS_SW_RST_SHIFT)) & IOMUXC_GPR_GPR2_MQS_SW_RST_MASK) +#define IOMUXC_GPR_GPR2_MQS_EN_MASK (0x2000000U) +#define IOMUXC_GPR_GPR2_MQS_EN_SHIFT (25U) +/*! MQS_EN + * 0b0..Disable MQS + * 0b1..Enable MQS + */ +#define IOMUXC_GPR_GPR2_MQS_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR2_MQS_EN_SHIFT)) & IOMUXC_GPR_GPR2_MQS_EN_MASK) +#define IOMUXC_GPR_GPR2_MQS_OVERSAMPLE_MASK (0x4000000U) +#define IOMUXC_GPR_GPR2_MQS_OVERSAMPLE_SHIFT (26U) +/*! MQS_OVERSAMPLE + * 0b0..32 + * 0b1..64 + */ +#define IOMUXC_GPR_GPR2_MQS_OVERSAMPLE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR2_MQS_OVERSAMPLE_SHIFT)) & IOMUXC_GPR_GPR2_MQS_OVERSAMPLE_MASK) +#define IOMUXC_GPR_GPR2_QTIMER1_TMR_CNTS_FREEZE_MASK (0x10000000U) +#define IOMUXC_GPR_GPR2_QTIMER1_TMR_CNTS_FREEZE_SHIFT (28U) +/*! QTIMER1_TMR_CNTS_FREEZE + * 0b0..timer counter work normally + * 0b1..reset counter and ouput flags + */ +#define IOMUXC_GPR_GPR2_QTIMER1_TMR_CNTS_FREEZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR2_QTIMER1_TMR_CNTS_FREEZE_SHIFT)) & IOMUXC_GPR_GPR2_QTIMER1_TMR_CNTS_FREEZE_MASK) +#define IOMUXC_GPR_GPR2_QTIMER2_TMR_CNTS_FREEZE_MASK (0x20000000U) +#define IOMUXC_GPR_GPR2_QTIMER2_TMR_CNTS_FREEZE_SHIFT (29U) +/*! QTIMER2_TMR_CNTS_FREEZE + * 0b0..timer counter work normally + * 0b1..reset counter and ouput flags + */ +#define IOMUXC_GPR_GPR2_QTIMER2_TMR_CNTS_FREEZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR2_QTIMER2_TMR_CNTS_FREEZE_SHIFT)) & IOMUXC_GPR_GPR2_QTIMER2_TMR_CNTS_FREEZE_MASK) +#define IOMUXC_GPR_GPR2_QTIMER3_TMR_CNTS_FREEZE_MASK (0x40000000U) +#define IOMUXC_GPR_GPR2_QTIMER3_TMR_CNTS_FREEZE_SHIFT (30U) +/*! QTIMER3_TMR_CNTS_FREEZE + * 0b0..timer counter work normally + * 0b1..reset counter and ouput flags + */ +#define IOMUXC_GPR_GPR2_QTIMER3_TMR_CNTS_FREEZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR2_QTIMER3_TMR_CNTS_FREEZE_SHIFT)) & IOMUXC_GPR_GPR2_QTIMER3_TMR_CNTS_FREEZE_MASK) +#define IOMUXC_GPR_GPR2_QTIMER4_TMR_CNTS_FREEZE_MASK (0x80000000U) +#define IOMUXC_GPR_GPR2_QTIMER4_TMR_CNTS_FREEZE_SHIFT (31U) +/*! QTIMER4_TMR_CNTS_FREEZE + * 0b0..timer counter work normally + * 0b1..reset counter and ouput flags + */ +#define IOMUXC_GPR_GPR2_QTIMER4_TMR_CNTS_FREEZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR2_QTIMER4_TMR_CNTS_FREEZE_SHIFT)) & IOMUXC_GPR_GPR2_QTIMER4_TMR_CNTS_FREEZE_MASK) +/*! @} */ + +/*! @name GPR3 - GPR3 General Purpose Register */ +/*! @{ */ +#define IOMUXC_GPR_GPR3_OCRAM_CTL_MASK (0xFU) +#define IOMUXC_GPR_GPR3_OCRAM_CTL_SHIFT (0U) +#define IOMUXC_GPR_GPR3_OCRAM_CTL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR3_OCRAM_CTL_SHIFT)) & IOMUXC_GPR_GPR3_OCRAM_CTL_MASK) +#define IOMUXC_GPR_GPR3_DCP_KEY_SEL_MASK (0x10U) +#define IOMUXC_GPR_GPR3_DCP_KEY_SEL_SHIFT (4U) +/*! DCP_KEY_SEL + * 0b0..Select [127:0] from snvs/ocotp key as dcp key + * 0b1..Select [255:128] from snvs/ocotp key as dcp key + */ +#define IOMUXC_GPR_GPR3_DCP_KEY_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR3_DCP_KEY_SEL_SHIFT)) & IOMUXC_GPR_GPR3_DCP_KEY_SEL_MASK) +#define IOMUXC_GPR_GPR3_OCRAM_STATUS_MASK (0xF0000U) +#define IOMUXC_GPR_GPR3_OCRAM_STATUS_SHIFT (16U) +/*! OCRAM_STATUS + * 0b0000..read data pipeline configuration valid + * 0b0001..read data pipeline control bit changed + */ +#define IOMUXC_GPR_GPR3_OCRAM_STATUS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR3_OCRAM_STATUS_SHIFT)) & IOMUXC_GPR_GPR3_OCRAM_STATUS_MASK) +/*! @} */ + +/*! @name GPR4 - GPR4 General Purpose Register */ +/*! @{ */ +#define IOMUXC_GPR_GPR4_EDMA_STOP_REQ_MASK (0x1U) +#define IOMUXC_GPR_GPR4_EDMA_STOP_REQ_SHIFT (0U) +/*! EDMA_STOP_REQ + * 0b0..stop request off + * 0b1..stop request on + */ +#define IOMUXC_GPR_GPR4_EDMA_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_EDMA_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR4_EDMA_STOP_REQ_MASK) +#define IOMUXC_GPR_GPR4_CAN1_STOP_REQ_MASK (0x2U) +#define IOMUXC_GPR_GPR4_CAN1_STOP_REQ_SHIFT (1U) +/*! CAN1_STOP_REQ + * 0b0..stop request off + * 0b1..stop request on + */ +#define IOMUXC_GPR_GPR4_CAN1_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_CAN1_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR4_CAN1_STOP_REQ_MASK) +#define IOMUXC_GPR_GPR4_CAN2_STOP_REQ_MASK (0x4U) +#define IOMUXC_GPR_GPR4_CAN2_STOP_REQ_SHIFT (2U) +/*! CAN2_STOP_REQ + * 0b0..stop request off + * 0b1..stop request on + */ +#define IOMUXC_GPR_GPR4_CAN2_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_CAN2_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR4_CAN2_STOP_REQ_MASK) +#define IOMUXC_GPR_GPR4_TRNG_STOP_REQ_MASK (0x8U) +#define IOMUXC_GPR_GPR4_TRNG_STOP_REQ_SHIFT (3U) +/*! TRNG_STOP_REQ + * 0b0..stop request off + * 0b1..stop request on + */ +#define IOMUXC_GPR_GPR4_TRNG_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_TRNG_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR4_TRNG_STOP_REQ_MASK) +#define IOMUXC_GPR_GPR4_ENET_STOP_REQ_MASK (0x10U) +#define IOMUXC_GPR_GPR4_ENET_STOP_REQ_SHIFT (4U) +/*! ENET_STOP_REQ + * 0b0..stop request off + * 0b1..stop request on + */ +#define IOMUXC_GPR_GPR4_ENET_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_ENET_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR4_ENET_STOP_REQ_MASK) +#define IOMUXC_GPR_GPR4_SAI1_STOP_REQ_MASK (0x20U) +#define IOMUXC_GPR_GPR4_SAI1_STOP_REQ_SHIFT (5U) +/*! SAI1_STOP_REQ + * 0b0..stop request off + * 0b1..stop request on + */ +#define IOMUXC_GPR_GPR4_SAI1_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_SAI1_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR4_SAI1_STOP_REQ_MASK) +#define IOMUXC_GPR_GPR4_SAI2_STOP_REQ_MASK (0x40U) +#define IOMUXC_GPR_GPR4_SAI2_STOP_REQ_SHIFT (6U) +/*! SAI2_STOP_REQ + * 0b0..stop request off + * 0b1..stop request on + */ +#define IOMUXC_GPR_GPR4_SAI2_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_SAI2_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR4_SAI2_STOP_REQ_MASK) +#define IOMUXC_GPR_GPR4_SAI3_STOP_REQ_MASK (0x80U) +#define IOMUXC_GPR_GPR4_SAI3_STOP_REQ_SHIFT (7U) +/*! SAI3_STOP_REQ + * 0b0..stop request off + * 0b1..stop request on + */ +#define IOMUXC_GPR_GPR4_SAI3_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_SAI3_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR4_SAI3_STOP_REQ_MASK) +#define IOMUXC_GPR_GPR4_SEMC_STOP_REQ_MASK (0x200U) +#define IOMUXC_GPR_GPR4_SEMC_STOP_REQ_SHIFT (9U) +/*! SEMC_STOP_REQ + * 0b0..stop request off + * 0b1..stop request on + */ +#define IOMUXC_GPR_GPR4_SEMC_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_SEMC_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR4_SEMC_STOP_REQ_MASK) +#define IOMUXC_GPR_GPR4_PIT_STOP_REQ_MASK (0x400U) +#define IOMUXC_GPR_GPR4_PIT_STOP_REQ_SHIFT (10U) +/*! PIT_STOP_REQ + * 0b0..stop request off + * 0b1..stop request on + */ +#define IOMUXC_GPR_GPR4_PIT_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_PIT_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR4_PIT_STOP_REQ_MASK) +#define IOMUXC_GPR_GPR4_FLEXSPI_STOP_REQ_MASK (0x800U) +#define IOMUXC_GPR_GPR4_FLEXSPI_STOP_REQ_SHIFT (11U) +/*! FLEXSPI_STOP_REQ + * 0b0..stop request off + * 0b1..stop request on + */ +#define IOMUXC_GPR_GPR4_FLEXSPI_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_FLEXSPI_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR4_FLEXSPI_STOP_REQ_MASK) +#define IOMUXC_GPR_GPR4_FLEXIO1_STOP_REQ_MASK (0x1000U) +#define IOMUXC_GPR_GPR4_FLEXIO1_STOP_REQ_SHIFT (12U) +/*! FLEXIO1_STOP_REQ + * 0b0..stop request off + * 0b1..stop request on + */ +#define IOMUXC_GPR_GPR4_FLEXIO1_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_FLEXIO1_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR4_FLEXIO1_STOP_REQ_MASK) +#define IOMUXC_GPR_GPR4_FLEXIO2_STOP_REQ_MASK (0x2000U) +#define IOMUXC_GPR_GPR4_FLEXIO2_STOP_REQ_SHIFT (13U) +/*! FLEXIO2_STOP_REQ + * 0b0..stop request off + * 0b1..stop request on + */ +#define IOMUXC_GPR_GPR4_FLEXIO2_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_FLEXIO2_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR4_FLEXIO2_STOP_REQ_MASK) +#define IOMUXC_GPR_GPR4_EDMA_STOP_ACK_MASK (0x10000U) +#define IOMUXC_GPR_GPR4_EDMA_STOP_ACK_SHIFT (16U) +/*! EDMA_STOP_ACK + * 0b0..EDMA stop acknowledge is not asserted + * 0b1..EDMA stop acknowledge is asserted (EDMA is in STOP mode). + */ +#define IOMUXC_GPR_GPR4_EDMA_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_EDMA_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR4_EDMA_STOP_ACK_MASK) +#define IOMUXC_GPR_GPR4_CAN1_STOP_ACK_MASK (0x20000U) +#define IOMUXC_GPR_GPR4_CAN1_STOP_ACK_SHIFT (17U) +/*! CAN1_STOP_ACK + * 0b0..CAN1 stop acknowledge is not asserted + * 0b1..CAN1 stop acknowledge is asserted + */ +#define IOMUXC_GPR_GPR4_CAN1_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_CAN1_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR4_CAN1_STOP_ACK_MASK) +#define IOMUXC_GPR_GPR4_CAN2_STOP_ACK_MASK (0x40000U) +#define IOMUXC_GPR_GPR4_CAN2_STOP_ACK_SHIFT (18U) +/*! CAN2_STOP_ACK + * 0b0..CAN2 stop acknowledge is not asserted + * 0b1..CAN2 stop acknowledge is asserted + */ +#define IOMUXC_GPR_GPR4_CAN2_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_CAN2_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR4_CAN2_STOP_ACK_MASK) +#define IOMUXC_GPR_GPR4_TRNG_STOP_ACK_MASK (0x80000U) +#define IOMUXC_GPR_GPR4_TRNG_STOP_ACK_SHIFT (19U) +/*! TRNG_STOP_ACK + * 0b0..TRNG stop acknowledge is not asserted + * 0b1..TRNG stop acknowledge is asserted + */ +#define IOMUXC_GPR_GPR4_TRNG_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_TRNG_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR4_TRNG_STOP_ACK_MASK) +#define IOMUXC_GPR_GPR4_ENET_STOP_ACK_MASK (0x100000U) +#define IOMUXC_GPR_GPR4_ENET_STOP_ACK_SHIFT (20U) +/*! ENET_STOP_ACK + * 0b0..ENET stop acknowledge is not asserted + * 0b1..ENET stop acknowledge is asserted + */ +#define IOMUXC_GPR_GPR4_ENET_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_ENET_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR4_ENET_STOP_ACK_MASK) +#define IOMUXC_GPR_GPR4_SAI1_STOP_ACK_MASK (0x200000U) +#define IOMUXC_GPR_GPR4_SAI1_STOP_ACK_SHIFT (21U) +/*! SAI1_STOP_ACK + * 0b0..SAI1 stop acknowledge is not asserted + * 0b1..SAI1 stop acknowledge is asserted + */ +#define IOMUXC_GPR_GPR4_SAI1_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_SAI1_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR4_SAI1_STOP_ACK_MASK) +#define IOMUXC_GPR_GPR4_SAI2_STOP_ACK_MASK (0x400000U) +#define IOMUXC_GPR_GPR4_SAI2_STOP_ACK_SHIFT (22U) +/*! SAI2_STOP_ACK + * 0b0..SAI2 stop acknowledge is not asserted + * 0b1..SAI2 stop acknowledge is asserted + */ +#define IOMUXC_GPR_GPR4_SAI2_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_SAI2_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR4_SAI2_STOP_ACK_MASK) +#define IOMUXC_GPR_GPR4_SAI3_STOP_ACK_MASK (0x800000U) +#define IOMUXC_GPR_GPR4_SAI3_STOP_ACK_SHIFT (23U) +/*! SAI3_STOP_ACK + * 0b0..SAI3 stop acknowledge is not asserted + * 0b1..SAI3 stop acknowledge is asserted + */ +#define IOMUXC_GPR_GPR4_SAI3_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_SAI3_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR4_SAI3_STOP_ACK_MASK) +#define IOMUXC_GPR_GPR4_SEMC_STOP_ACK_MASK (0x2000000U) +#define IOMUXC_GPR_GPR4_SEMC_STOP_ACK_SHIFT (25U) +/*! SEMC_STOP_ACK + * 0b0..SEMC stop acknowledge is not asserted + * 0b1..SEMC stop acknowledge is asserted + */ +#define IOMUXC_GPR_GPR4_SEMC_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_SEMC_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR4_SEMC_STOP_ACK_MASK) +#define IOMUXC_GPR_GPR4_PIT_STOP_ACK_MASK (0x4000000U) +#define IOMUXC_GPR_GPR4_PIT_STOP_ACK_SHIFT (26U) +/*! PIT_STOP_ACK + * 0b0..PIT stop acknowledge is not asserted + * 0b1..PIT stop acknowledge is asserted + */ +#define IOMUXC_GPR_GPR4_PIT_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_PIT_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR4_PIT_STOP_ACK_MASK) +#define IOMUXC_GPR_GPR4_FLEXSPI_STOP_ACK_MASK (0x8000000U) +#define IOMUXC_GPR_GPR4_FLEXSPI_STOP_ACK_SHIFT (27U) +/*! FLEXSPI_STOP_ACK + * 0b0..FLEXSPI stop acknowledge is not asserted + * 0b1..FLEXSPI stop acknowledge is asserted + */ +#define IOMUXC_GPR_GPR4_FLEXSPI_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_FLEXSPI_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR4_FLEXSPI_STOP_ACK_MASK) +#define IOMUXC_GPR_GPR4_FLEXIO1_STOP_ACK_MASK (0x10000000U) +#define IOMUXC_GPR_GPR4_FLEXIO1_STOP_ACK_SHIFT (28U) +/*! FLEXIO1_STOP_ACK + * 0b0..FLEXIO1 stop acknowledge is not asserted + * 0b1..FLEXIO1 stop acknowledge is asserted + */ +#define IOMUXC_GPR_GPR4_FLEXIO1_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_FLEXIO1_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR4_FLEXIO1_STOP_ACK_MASK) +#define IOMUXC_GPR_GPR4_FLEXIO2_STOP_ACK_MASK (0x20000000U) +#define IOMUXC_GPR_GPR4_FLEXIO2_STOP_ACK_SHIFT (29U) +/*! FLEXIO2_STOP_ACK + * 0b0..FLEXIO2 stop acknowledge is not asserted + * 0b1..FLEXIO2 stop acknowledge is asserted (FLEXIO2 is in STOP mode) + */ +#define IOMUXC_GPR_GPR4_FLEXIO2_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_FLEXIO2_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR4_FLEXIO2_STOP_ACK_MASK) +/*! @} */ + +/*! @name GPR5 - GPR5 General Purpose Register */ +/*! @{ */ +#define IOMUXC_GPR_GPR5_WDOG1_MASK_MASK (0x40U) +#define IOMUXC_GPR_GPR5_WDOG1_MASK_SHIFT (6U) +/*! WDOG1_MASK + * 0b0..WDOG1 Timeout behaves normally + * 0b1..WDOG1 Timeout is masked + */ +#define IOMUXC_GPR_GPR5_WDOG1_MASK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR5_WDOG1_MASK_SHIFT)) & IOMUXC_GPR_GPR5_WDOG1_MASK_MASK) +#define IOMUXC_GPR_GPR5_WDOG2_MASK_MASK (0x80U) +#define IOMUXC_GPR_GPR5_WDOG2_MASK_SHIFT (7U) +/*! WDOG2_MASK + * 0b0..WDOG2 Timeout behaves normally + * 0b1..WDOG2 Timeout is masked + */ +#define IOMUXC_GPR_GPR5_WDOG2_MASK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR5_WDOG2_MASK_SHIFT)) & IOMUXC_GPR_GPR5_WDOG2_MASK_MASK) +#define IOMUXC_GPR_GPR5_GPT2_CAPIN1_SEL_MASK (0x800000U) +#define IOMUXC_GPR_GPR5_GPT2_CAPIN1_SEL_SHIFT (23U) +/*! GPT2_CAPIN1_SEL + * 0b0..source from pad + * 0b1..source from enet1.ipp_do_mac0_timer[3] + */ +#define IOMUXC_GPR_GPR5_GPT2_CAPIN1_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR5_GPT2_CAPIN1_SEL_SHIFT)) & IOMUXC_GPR_GPR5_GPT2_CAPIN1_SEL_MASK) +#define IOMUXC_GPR_GPR5_ENET_EVENT3IN_SEL_MASK (0x2000000U) +#define IOMUXC_GPR_GPR5_ENET_EVENT3IN_SEL_SHIFT (25U) +/*! ENET_EVENT3IN_SEL + * 0b0..event3 source input from pad + * 0b1..event3 source input from gpt2.ipp_do_cmpout1 + */ +#define IOMUXC_GPR_GPR5_ENET_EVENT3IN_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR5_ENET_EVENT3IN_SEL_SHIFT)) & IOMUXC_GPR_GPR5_ENET_EVENT3IN_SEL_MASK) +#define IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT1_MASK (0x10000000U) +#define IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT1_SHIFT (28U) +/*! VREF_1M_CLK_GPT1 + * 0b0..GPT1 ipg_clk_highfreq driven by IPG_PERCLK + * 0b1..GPT1 ipg_clk_highfreq driven by anatop 1 MHz clock + */ +#define IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT1(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT1_SHIFT)) & IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT1_MASK) +#define IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT2_MASK (0x20000000U) +#define IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT2_SHIFT (29U) +/*! VREF_1M_CLK_GPT2 + * 0b0..GPT2 ipg_clk_highfreq driven by IPG_PERCLK + * 0b1..GPT2 ipg_clk_highfreq driven by anatop 1 MHz clock + */ +#define IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT2(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT2_SHIFT)) & IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT2_MASK) +/*! @} */ + +/*! @name GPR6 - GPR6 General Purpose Register */ +/*! @{ */ +#define IOMUXC_GPR_GPR6_QTIMER1_TRM0_INPUT_SEL_MASK (0x1U) +#define IOMUXC_GPR_GPR6_QTIMER1_TRM0_INPUT_SEL_SHIFT (0U) +/*! QTIMER1_TRM0_INPUT_SEL + * 0b0..input from IOMUX + * 0b1..input from XBAR + */ +#define IOMUXC_GPR_GPR6_QTIMER1_TRM0_INPUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_QTIMER1_TRM0_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR6_QTIMER1_TRM0_INPUT_SEL_MASK) +#define IOMUXC_GPR_GPR6_QTIMER1_TRM1_INPUT_SEL_MASK (0x2U) +#define IOMUXC_GPR_GPR6_QTIMER1_TRM1_INPUT_SEL_SHIFT (1U) +/*! QTIMER1_TRM1_INPUT_SEL + * 0b0..input from IOMUX + * 0b1..input from XBAR + */ +#define IOMUXC_GPR_GPR6_QTIMER1_TRM1_INPUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_QTIMER1_TRM1_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR6_QTIMER1_TRM1_INPUT_SEL_MASK) +#define IOMUXC_GPR_GPR6_QTIMER1_TRM2_INPUT_SEL_MASK (0x4U) +#define IOMUXC_GPR_GPR6_QTIMER1_TRM2_INPUT_SEL_SHIFT (2U) +/*! QTIMER1_TRM2_INPUT_SEL + * 0b0..input from IOMUX + * 0b1..input from XBAR + */ +#define IOMUXC_GPR_GPR6_QTIMER1_TRM2_INPUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_QTIMER1_TRM2_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR6_QTIMER1_TRM2_INPUT_SEL_MASK) +#define IOMUXC_GPR_GPR6_QTIMER1_TRM3_INPUT_SEL_MASK (0x8U) +#define IOMUXC_GPR_GPR6_QTIMER1_TRM3_INPUT_SEL_SHIFT (3U) +/*! QTIMER1_TRM3_INPUT_SEL + * 0b0..input from IOMUX + * 0b1..input from XBAR + */ +#define IOMUXC_GPR_GPR6_QTIMER1_TRM3_INPUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_QTIMER1_TRM3_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR6_QTIMER1_TRM3_INPUT_SEL_MASK) +#define IOMUXC_GPR_GPR6_QTIMER2_TRM0_INPUT_SEL_MASK (0x10U) +#define IOMUXC_GPR_GPR6_QTIMER2_TRM0_INPUT_SEL_SHIFT (4U) +/*! QTIMER2_TRM0_INPUT_SEL + * 0b0..input from IOMUX + * 0b1..input from XBAR + */ +#define IOMUXC_GPR_GPR6_QTIMER2_TRM0_INPUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_QTIMER2_TRM0_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR6_QTIMER2_TRM0_INPUT_SEL_MASK) +#define IOMUXC_GPR_GPR6_QTIMER2_TRM1_INPUT_SEL_MASK (0x20U) +#define IOMUXC_GPR_GPR6_QTIMER2_TRM1_INPUT_SEL_SHIFT (5U) +/*! QTIMER2_TRM1_INPUT_SEL + * 0b0..input from IOMUX + * 0b1..input from XBAR + */ +#define IOMUXC_GPR_GPR6_QTIMER2_TRM1_INPUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_QTIMER2_TRM1_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR6_QTIMER2_TRM1_INPUT_SEL_MASK) +#define IOMUXC_GPR_GPR6_QTIMER2_TRM2_INPUT_SEL_MASK (0x40U) +#define IOMUXC_GPR_GPR6_QTIMER2_TRM2_INPUT_SEL_SHIFT (6U) +/*! QTIMER2_TRM2_INPUT_SEL + * 0b0..input from IOMUX + * 0b1..input from XBAR + */ +#define IOMUXC_GPR_GPR6_QTIMER2_TRM2_INPUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_QTIMER2_TRM2_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR6_QTIMER2_TRM2_INPUT_SEL_MASK) +#define IOMUXC_GPR_GPR6_QTIMER2_TRM3_INPUT_SEL_MASK (0x80U) +#define IOMUXC_GPR_GPR6_QTIMER2_TRM3_INPUT_SEL_SHIFT (7U) +/*! QTIMER2_TRM3_INPUT_SEL + * 0b0..input from IOMUX + * 0b1..input from XBAR + */ +#define IOMUXC_GPR_GPR6_QTIMER2_TRM3_INPUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_QTIMER2_TRM3_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR6_QTIMER2_TRM3_INPUT_SEL_MASK) +#define IOMUXC_GPR_GPR6_QTIMER3_TRM0_INPUT_SEL_MASK (0x100U) +#define IOMUXC_GPR_GPR6_QTIMER3_TRM0_INPUT_SEL_SHIFT (8U) +/*! QTIMER3_TRM0_INPUT_SEL + * 0b0..input from IOMUX + * 0b1..input from XBAR + */ +#define IOMUXC_GPR_GPR6_QTIMER3_TRM0_INPUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_QTIMER3_TRM0_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR6_QTIMER3_TRM0_INPUT_SEL_MASK) +#define IOMUXC_GPR_GPR6_QTIMER3_TRM1_INPUT_SEL_MASK (0x200U) +#define IOMUXC_GPR_GPR6_QTIMER3_TRM1_INPUT_SEL_SHIFT (9U) +/*! QTIMER3_TRM1_INPUT_SEL + * 0b0..input from IOMUX + * 0b1..input from XBAR + */ +#define IOMUXC_GPR_GPR6_QTIMER3_TRM1_INPUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_QTIMER3_TRM1_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR6_QTIMER3_TRM1_INPUT_SEL_MASK) +#define IOMUXC_GPR_GPR6_QTIMER3_TRM2_INPUT_SEL_MASK (0x400U) +#define IOMUXC_GPR_GPR6_QTIMER3_TRM2_INPUT_SEL_SHIFT (10U) +/*! QTIMER3_TRM2_INPUT_SEL + * 0b0..input from IOMUX + * 0b1..input from XBAR + */ +#define IOMUXC_GPR_GPR6_QTIMER3_TRM2_INPUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_QTIMER3_TRM2_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR6_QTIMER3_TRM2_INPUT_SEL_MASK) +#define IOMUXC_GPR_GPR6_QTIMER3_TRM3_INPUT_SEL_MASK (0x800U) +#define IOMUXC_GPR_GPR6_QTIMER3_TRM3_INPUT_SEL_SHIFT (11U) +/*! QTIMER3_TRM3_INPUT_SEL + * 0b0..input from IOMUX + * 0b1..input from XBAR + */ +#define IOMUXC_GPR_GPR6_QTIMER3_TRM3_INPUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_QTIMER3_TRM3_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR6_QTIMER3_TRM3_INPUT_SEL_MASK) +#define IOMUXC_GPR_GPR6_QTIMER4_TRM0_INPUT_SEL_MASK (0x1000U) +#define IOMUXC_GPR_GPR6_QTIMER4_TRM0_INPUT_SEL_SHIFT (12U) +/*! QTIMER4_TRM0_INPUT_SEL + * 0b0..input from IOMUX + * 0b1..input from XBAR + */ +#define IOMUXC_GPR_GPR6_QTIMER4_TRM0_INPUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_QTIMER4_TRM0_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR6_QTIMER4_TRM0_INPUT_SEL_MASK) +#define IOMUXC_GPR_GPR6_QTIMER4_TRM1_INPUT_SEL_MASK (0x2000U) +#define IOMUXC_GPR_GPR6_QTIMER4_TRM1_INPUT_SEL_SHIFT (13U) +/*! QTIMER4_TRM1_INPUT_SEL + * 0b0..input from IOMUX + * 0b1..input from XBAR + */ +#define IOMUXC_GPR_GPR6_QTIMER4_TRM1_INPUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_QTIMER4_TRM1_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR6_QTIMER4_TRM1_INPUT_SEL_MASK) +#define IOMUXC_GPR_GPR6_QTIMER4_TRM2_INPUT_SEL_MASK (0x4000U) +#define IOMUXC_GPR_GPR6_QTIMER4_TRM2_INPUT_SEL_SHIFT (14U) +/*! QTIMER4_TRM2_INPUT_SEL + * 0b0..input from IOMUX + * 0b1..input from XBAR + */ +#define IOMUXC_GPR_GPR6_QTIMER4_TRM2_INPUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_QTIMER4_TRM2_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR6_QTIMER4_TRM2_INPUT_SEL_MASK) +#define IOMUXC_GPR_GPR6_QTIMER4_TRM3_INPUT_SEL_MASK (0x8000U) +#define IOMUXC_GPR_GPR6_QTIMER4_TRM3_INPUT_SEL_SHIFT (15U) +/*! QTIMER4_TRM3_INPUT_SEL + * 0b0..input from IOMUX + * 0b1..input from XBAR + */ +#define IOMUXC_GPR_GPR6_QTIMER4_TRM3_INPUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_QTIMER4_TRM3_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR6_QTIMER4_TRM3_INPUT_SEL_MASK) +#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_4_MASK (0x10000U) +#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_4_SHIFT (16U) +/*! IOMUXC_XBAR_DIR_SEL_4 + * 0b0..XBAR_INOUT as input + * 0b1..XBAR_INOUT as output + */ +#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_4_SHIFT)) & IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_4_MASK) +#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_5_MASK (0x20000U) +#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_5_SHIFT (17U) +/*! IOMUXC_XBAR_DIR_SEL_5 + * 0b0..XBAR_INOUT as input + * 0b1..XBAR_INOUT as output + */ +#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_5(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_5_SHIFT)) & IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_5_MASK) +#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_6_MASK (0x40000U) +#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_6_SHIFT (18U) +/*! IOMUXC_XBAR_DIR_SEL_6 + * 0b0..XBAR_INOUT as input + * 0b1..XBAR_INOUT as output + */ +#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_6(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_6_SHIFT)) & IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_6_MASK) +#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_7_MASK (0x80000U) +#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_7_SHIFT (19U) +/*! IOMUXC_XBAR_DIR_SEL_7 + * 0b0..XBAR_INOUT as input + * 0b1..XBAR_INOUT as output + */ +#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_7(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_7_SHIFT)) & IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_7_MASK) +#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_8_MASK (0x100000U) +#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_8_SHIFT (20U) +/*! IOMUXC_XBAR_DIR_SEL_8 + * 0b0..XBAR_INOUT as input + * 0b1..XBAR_INOUT as output + */ +#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_8(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_8_SHIFT)) & IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_8_MASK) +#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_9_MASK (0x200000U) +#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_9_SHIFT (21U) +/*! IOMUXC_XBAR_DIR_SEL_9 + * 0b0..XBAR_INOUT as input + * 0b1..XBAR_INOUT as output + */ +#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_9(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_9_SHIFT)) & IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_9_MASK) +#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_10_MASK (0x400000U) +#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_10_SHIFT (22U) +/*! IOMUXC_XBAR_DIR_SEL_10 + * 0b0..XBAR_INOUT as input + * 0b1..XBAR_INOUT as output + */ +#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_10(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_10_SHIFT)) & IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_10_MASK) +#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_11_MASK (0x800000U) +#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_11_SHIFT (23U) +/*! IOMUXC_XBAR_DIR_SEL_11 + * 0b0..XBAR_INOUT as input + * 0b1..XBAR_INOUT as output + */ +#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_11(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_11_SHIFT)) & IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_11_MASK) +#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_12_MASK (0x1000000U) +#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_12_SHIFT (24U) +/*! IOMUXC_XBAR_DIR_SEL_12 + * 0b0..XBAR_INOUT as input + * 0b1..XBAR_INOUT as output + */ +#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_12(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_12_SHIFT)) & IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_12_MASK) +#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_13_MASK (0x2000000U) +#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_13_SHIFT (25U) +/*! IOMUXC_XBAR_DIR_SEL_13 + * 0b0..XBAR_INOUT as input + * 0b1..XBAR_INOUT as output + */ +#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_13(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_13_SHIFT)) & IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_13_MASK) +#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_14_MASK (0x4000000U) +#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_14_SHIFT (26U) +/*! IOMUXC_XBAR_DIR_SEL_14 + * 0b0..XBAR_INOUT as input + * 0b1..XBAR_INOUT as output + */ +#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_14(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_14_SHIFT)) & IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_14_MASK) +#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_15_MASK (0x8000000U) +#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_15_SHIFT (27U) +/*! IOMUXC_XBAR_DIR_SEL_15 + * 0b0..XBAR_INOUT as input + * 0b1..XBAR_INOUT as output + */ +#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_15(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_15_SHIFT)) & IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_15_MASK) +#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_16_MASK (0x10000000U) +#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_16_SHIFT (28U) +/*! IOMUXC_XBAR_DIR_SEL_16 + * 0b0..XBAR_INOUT as input + * 0b1..XBAR_INOUT as output + */ +#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_16(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_16_SHIFT)) & IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_16_MASK) +#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_17_MASK (0x20000000U) +#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_17_SHIFT (29U) +/*! IOMUXC_XBAR_DIR_SEL_17 + * 0b0..XBAR_INOUT as input + * 0b1..XBAR_INOUT as output + */ +#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_17(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_17_SHIFT)) & IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_17_MASK) +#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_18_MASK (0x40000000U) +#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_18_SHIFT (30U) +/*! IOMUXC_XBAR_DIR_SEL_18 + * 0b0..XBAR_INOUT as input + * 0b1..XBAR_INOUT as output + */ +#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_18_SHIFT)) & IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_18_MASK) +#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_19_MASK (0x80000000U) +#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_19_SHIFT (31U) +/*! IOMUXC_XBAR_DIR_SEL_19 + * 0b0..XBAR_INOUT as input + * 0b1..XBAR_INOUT as output + */ +#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_19(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_19_SHIFT)) & IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_19_MASK) +/*! @} */ + +/*! @name GPR7 - GPR7 General Purpose Register */ +/*! @{ */ +#define IOMUXC_GPR_GPR7_LPI2C1_STOP_REQ_MASK (0x1U) +#define IOMUXC_GPR_GPR7_LPI2C1_STOP_REQ_SHIFT (0U) +/*! LPI2C1_STOP_REQ + * 0b0..stop request off + * 0b1..stop request on + */ +#define IOMUXC_GPR_GPR7_LPI2C1_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPI2C1_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR7_LPI2C1_STOP_REQ_MASK) +#define IOMUXC_GPR_GPR7_LPI2C2_STOP_REQ_MASK (0x2U) +#define IOMUXC_GPR_GPR7_LPI2C2_STOP_REQ_SHIFT (1U) +/*! LPI2C2_STOP_REQ + * 0b0..stop request off + * 0b1..stop request on + */ +#define IOMUXC_GPR_GPR7_LPI2C2_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPI2C2_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR7_LPI2C2_STOP_REQ_MASK) +#define IOMUXC_GPR_GPR7_LPI2C3_STOP_REQ_MASK (0x4U) +#define IOMUXC_GPR_GPR7_LPI2C3_STOP_REQ_SHIFT (2U) +/*! LPI2C3_STOP_REQ + * 0b0..stop request off + * 0b1..stop request on + */ +#define IOMUXC_GPR_GPR7_LPI2C3_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPI2C3_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR7_LPI2C3_STOP_REQ_MASK) +#define IOMUXC_GPR_GPR7_LPI2C4_STOP_REQ_MASK (0x8U) +#define IOMUXC_GPR_GPR7_LPI2C4_STOP_REQ_SHIFT (3U) +/*! LPI2C4_STOP_REQ + * 0b0..stop request off + * 0b1..stop request on + */ +#define IOMUXC_GPR_GPR7_LPI2C4_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPI2C4_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR7_LPI2C4_STOP_REQ_MASK) +#define IOMUXC_GPR_GPR7_LPSPI1_STOP_REQ_MASK (0x10U) +#define IOMUXC_GPR_GPR7_LPSPI1_STOP_REQ_SHIFT (4U) +/*! LPSPI1_STOP_REQ + * 0b0..stop request off + * 0b1..stop request on + */ +#define IOMUXC_GPR_GPR7_LPSPI1_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPSPI1_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR7_LPSPI1_STOP_REQ_MASK) +#define IOMUXC_GPR_GPR7_LPSPI2_STOP_REQ_MASK (0x20U) +#define IOMUXC_GPR_GPR7_LPSPI2_STOP_REQ_SHIFT (5U) +/*! LPSPI2_STOP_REQ + * 0b0..stop request off + * 0b1..stop request on + */ +#define IOMUXC_GPR_GPR7_LPSPI2_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPSPI2_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR7_LPSPI2_STOP_REQ_MASK) +#define IOMUXC_GPR_GPR7_LPSPI3_STOP_REQ_MASK (0x40U) +#define IOMUXC_GPR_GPR7_LPSPI3_STOP_REQ_SHIFT (6U) +/*! LPSPI3_STOP_REQ + * 0b0..stop request off + * 0b1..stop request on + */ +#define IOMUXC_GPR_GPR7_LPSPI3_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPSPI3_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR7_LPSPI3_STOP_REQ_MASK) +#define IOMUXC_GPR_GPR7_LPSPI4_STOP_REQ_MASK (0x80U) +#define IOMUXC_GPR_GPR7_LPSPI4_STOP_REQ_SHIFT (7U) +/*! LPSPI4_STOP_REQ + * 0b0..stop request off + * 0b1..stop request on + */ +#define IOMUXC_GPR_GPR7_LPSPI4_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPSPI4_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR7_LPSPI4_STOP_REQ_MASK) +#define IOMUXC_GPR_GPR7_LPUART1_STOP_REQ_MASK (0x100U) +#define IOMUXC_GPR_GPR7_LPUART1_STOP_REQ_SHIFT (8U) +/*! LPUART1_STOP_REQ + * 0b0..stop request off + * 0b1..stop request on + */ +#define IOMUXC_GPR_GPR7_LPUART1_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPUART1_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR7_LPUART1_STOP_REQ_MASK) +#define IOMUXC_GPR_GPR7_LPUART2_STOP_REQ_MASK (0x200U) +#define IOMUXC_GPR_GPR7_LPUART2_STOP_REQ_SHIFT (9U) +/*! LPUART2_STOP_REQ + * 0b0..stop request off + * 0b1..stop request on + */ +#define IOMUXC_GPR_GPR7_LPUART2_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPUART2_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR7_LPUART2_STOP_REQ_MASK) +#define IOMUXC_GPR_GPR7_LPUART3_STOP_REQ_MASK (0x400U) +#define IOMUXC_GPR_GPR7_LPUART3_STOP_REQ_SHIFT (10U) +/*! LPUART3_STOP_REQ + * 0b0..stop request off + * 0b1..stop request on + */ +#define IOMUXC_GPR_GPR7_LPUART3_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPUART3_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR7_LPUART3_STOP_REQ_MASK) +#define IOMUXC_GPR_GPR7_LPUART4_STOP_REQ_MASK (0x800U) +#define IOMUXC_GPR_GPR7_LPUART4_STOP_REQ_SHIFT (11U) +/*! LPUART4_STOP_REQ + * 0b0..stop request off + * 0b1..stop request on + */ +#define IOMUXC_GPR_GPR7_LPUART4_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPUART4_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR7_LPUART4_STOP_REQ_MASK) +#define IOMUXC_GPR_GPR7_LPUART5_STOP_REQ_MASK (0x1000U) +#define IOMUXC_GPR_GPR7_LPUART5_STOP_REQ_SHIFT (12U) +/*! LPUART5_STOP_REQ + * 0b0..stop request off + * 0b1..stop request on + */ +#define IOMUXC_GPR_GPR7_LPUART5_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPUART5_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR7_LPUART5_STOP_REQ_MASK) +#define IOMUXC_GPR_GPR7_LPUART6_STOP_REQ_MASK (0x2000U) +#define IOMUXC_GPR_GPR7_LPUART6_STOP_REQ_SHIFT (13U) +/*! LPUART6_STOP_REQ + * 0b0..stop request off + * 0b1..stop request on + */ +#define IOMUXC_GPR_GPR7_LPUART6_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPUART6_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR7_LPUART6_STOP_REQ_MASK) +#define IOMUXC_GPR_GPR7_LPUART7_STOP_REQ_MASK (0x4000U) +#define IOMUXC_GPR_GPR7_LPUART7_STOP_REQ_SHIFT (14U) +/*! LPUART7_STOP_REQ + * 0b0..stop request off + * 0b1..stop request on + */ +#define IOMUXC_GPR_GPR7_LPUART7_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPUART7_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR7_LPUART7_STOP_REQ_MASK) +#define IOMUXC_GPR_GPR7_LPUART8_STOP_REQ_MASK (0x8000U) +#define IOMUXC_GPR_GPR7_LPUART8_STOP_REQ_SHIFT (15U) +/*! LPUART8_STOP_REQ + * 0b0..stop request off + * 0b1..stop request on + */ +#define IOMUXC_GPR_GPR7_LPUART8_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPUART8_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR7_LPUART8_STOP_REQ_MASK) +#define IOMUXC_GPR_GPR7_LPI2C1_STOP_ACK_MASK (0x10000U) +#define IOMUXC_GPR_GPR7_LPI2C1_STOP_ACK_SHIFT (16U) +/*! LPI2C1_STOP_ACK + * 0b0..stop acknowledge is not asserted + * 0b1..stop acknowledge is asserted (the module is in Stop mode) + */ +#define IOMUXC_GPR_GPR7_LPI2C1_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPI2C1_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR7_LPI2C1_STOP_ACK_MASK) +#define IOMUXC_GPR_GPR7_LPI2C2_STOP_ACK_MASK (0x20000U) +#define IOMUXC_GPR_GPR7_LPI2C2_STOP_ACK_SHIFT (17U) +/*! LPI2C2_STOP_ACK + * 0b0..stop acknowledge is not asserted + * 0b1..stop acknowledge is asserted + */ +#define IOMUXC_GPR_GPR7_LPI2C2_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPI2C2_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR7_LPI2C2_STOP_ACK_MASK) +#define IOMUXC_GPR_GPR7_LPI2C3_STOP_ACK_MASK (0x40000U) +#define IOMUXC_GPR_GPR7_LPI2C3_STOP_ACK_SHIFT (18U) +/*! LPI2C3_STOP_ACK + * 0b0..stop acknowledge is not asserted + * 0b1..stop acknowledge is asserted + */ +#define IOMUXC_GPR_GPR7_LPI2C3_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPI2C3_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR7_LPI2C3_STOP_ACK_MASK) +#define IOMUXC_GPR_GPR7_LPI2C4_STOP_ACK_MASK (0x80000U) +#define IOMUXC_GPR_GPR7_LPI2C4_STOP_ACK_SHIFT (19U) +/*! LPI2C4_STOP_ACK + * 0b0..stop acknowledge is not asserted + * 0b1..stop acknowledge is asserted + */ +#define IOMUXC_GPR_GPR7_LPI2C4_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPI2C4_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR7_LPI2C4_STOP_ACK_MASK) +#define IOMUXC_GPR_GPR7_LPSPI1_STOP_ACK_MASK (0x100000U) +#define IOMUXC_GPR_GPR7_LPSPI1_STOP_ACK_SHIFT (20U) +/*! LPSPI1_STOP_ACK + * 0b0..stop acknowledge is not asserted + * 0b1..stop acknowledge is asserted + */ +#define IOMUXC_GPR_GPR7_LPSPI1_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPSPI1_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR7_LPSPI1_STOP_ACK_MASK) +#define IOMUXC_GPR_GPR7_LPSPI2_STOP_ACK_MASK (0x200000U) +#define IOMUXC_GPR_GPR7_LPSPI2_STOP_ACK_SHIFT (21U) +/*! LPSPI2_STOP_ACK + * 0b0..stop acknowledge is not asserted + * 0b1..stop acknowledge is asserted + */ +#define IOMUXC_GPR_GPR7_LPSPI2_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPSPI2_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR7_LPSPI2_STOP_ACK_MASK) +#define IOMUXC_GPR_GPR7_LPSPI3_STOP_ACK_MASK (0x400000U) +#define IOMUXC_GPR_GPR7_LPSPI3_STOP_ACK_SHIFT (22U) +/*! LPSPI3_STOP_ACK + * 0b0..stop acknowledge is not asserted + * 0b1..stop acknowledge is asserted + */ +#define IOMUXC_GPR_GPR7_LPSPI3_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPSPI3_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR7_LPSPI3_STOP_ACK_MASK) +#define IOMUXC_GPR_GPR7_LPSPI4_STOP_ACK_MASK (0x800000U) +#define IOMUXC_GPR_GPR7_LPSPI4_STOP_ACK_SHIFT (23U) +/*! LPSPI4_STOP_ACK + * 0b0..stop acknowledge is not asserted + * 0b1..stop acknowledge is asserted + */ +#define IOMUXC_GPR_GPR7_LPSPI4_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPSPI4_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR7_LPSPI4_STOP_ACK_MASK) +#define IOMUXC_GPR_GPR7_LPUART1_STOP_ACK_MASK (0x1000000U) +#define IOMUXC_GPR_GPR7_LPUART1_STOP_ACK_SHIFT (24U) +/*! LPUART1_STOP_ACK + * 0b0..stop acknowledge is not asserted + * 0b1..stop acknowledge is asserted + */ +#define IOMUXC_GPR_GPR7_LPUART1_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPUART1_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR7_LPUART1_STOP_ACK_MASK) +#define IOMUXC_GPR_GPR7_LPUART2_STOP_ACK_MASK (0x2000000U) +#define IOMUXC_GPR_GPR7_LPUART2_STOP_ACK_SHIFT (25U) +/*! LPUART2_STOP_ACK + * 0b0..stop acknowledge is not asserted + * 0b1..stop acknowledge is asserted + */ +#define IOMUXC_GPR_GPR7_LPUART2_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPUART2_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR7_LPUART2_STOP_ACK_MASK) +#define IOMUXC_GPR_GPR7_LPUART3_STOP_ACK_MASK (0x4000000U) +#define IOMUXC_GPR_GPR7_LPUART3_STOP_ACK_SHIFT (26U) +/*! LPUART3_STOP_ACK + * 0b0..stop acknowledge is not asserted + * 0b1..stop acknowledge is asserted + */ +#define IOMUXC_GPR_GPR7_LPUART3_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPUART3_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR7_LPUART3_STOP_ACK_MASK) +#define IOMUXC_GPR_GPR7_LPUART4_STOP_ACK_MASK (0x8000000U) +#define IOMUXC_GPR_GPR7_LPUART4_STOP_ACK_SHIFT (27U) +/*! LPUART4_STOP_ACK + * 0b0..stop acknowledge is not asserted + * 0b1..stop acknowledge is asserted + */ +#define IOMUXC_GPR_GPR7_LPUART4_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPUART4_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR7_LPUART4_STOP_ACK_MASK) +#define IOMUXC_GPR_GPR7_LPUART5_STOP_ACK_MASK (0x10000000U) +#define IOMUXC_GPR_GPR7_LPUART5_STOP_ACK_SHIFT (28U) +/*! LPUART5_STOP_ACK + * 0b0..stop acknowledge is not asserted + * 0b1..stop acknowledge is asserted + */ +#define IOMUXC_GPR_GPR7_LPUART5_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPUART5_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR7_LPUART5_STOP_ACK_MASK) +#define IOMUXC_GPR_GPR7_LPUART6_STOP_ACK_MASK (0x20000000U) +#define IOMUXC_GPR_GPR7_LPUART6_STOP_ACK_SHIFT (29U) +/*! LPUART6_STOP_ACK + * 0b0..stop acknowledge is not asserted + * 0b1..stop acknowledge is asserted + */ +#define IOMUXC_GPR_GPR7_LPUART6_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPUART6_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR7_LPUART6_STOP_ACK_MASK) +#define IOMUXC_GPR_GPR7_LPUART7_STOP_ACK_MASK (0x40000000U) +#define IOMUXC_GPR_GPR7_LPUART7_STOP_ACK_SHIFT (30U) +/*! LPUART7_STOP_ACK + * 0b0..stop acknowledge is not asserted + * 0b1..stop acknowledge is asserted + */ +#define IOMUXC_GPR_GPR7_LPUART7_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPUART7_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR7_LPUART7_STOP_ACK_MASK) +#define IOMUXC_GPR_GPR7_LPUART8_STOP_ACK_MASK (0x80000000U) +#define IOMUXC_GPR_GPR7_LPUART8_STOP_ACK_SHIFT (31U) +/*! LPUART8_STOP_ACK + * 0b0..stop acknowledge is not asserted + * 0b1..stop acknowledge is asserted (the module is in Stop mode) + */ +#define IOMUXC_GPR_GPR7_LPUART8_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPUART8_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR7_LPUART8_STOP_ACK_MASK) +/*! @} */ + +/*! @name GPR8 - GPR8 General Purpose Register */ +/*! @{ */ +#define IOMUXC_GPR_GPR8_LPI2C1_IPG_STOP_MODE_MASK (0x1U) +#define IOMUXC_GPR_GPR8_LPI2C1_IPG_STOP_MODE_SHIFT (0U) +/*! LPI2C1_IPG_STOP_MODE + * 0b0..the module is functional in Stop mode + * 0b1..the module is NOT functional in Stop mode, when this bit is equal to 1 and ipg_stop is asserted + */ +#define IOMUXC_GPR_GPR8_LPI2C1_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPI2C1_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR8_LPI2C1_IPG_STOP_MODE_MASK) +#define IOMUXC_GPR_GPR8_LPI2C1_IPG_DOZE_MASK (0x2U) +#define IOMUXC_GPR_GPR8_LPI2C1_IPG_DOZE_SHIFT (1U) +/*! LPI2C1_IPG_DOZE + * 0b0..not in doze mode + * 0b1..in doze mode + */ +#define IOMUXC_GPR_GPR8_LPI2C1_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPI2C1_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR8_LPI2C1_IPG_DOZE_MASK) +#define IOMUXC_GPR_GPR8_LPI2C2_IPG_STOP_MODE_MASK (0x4U) +#define IOMUXC_GPR_GPR8_LPI2C2_IPG_STOP_MODE_SHIFT (2U) +/*! LPI2C2_IPG_STOP_MODE + * 0b0..the module is functional in Stop mode + * 0b1..the module is NOT functional in Stop mode, when this bit is equal to 1 and ipg_stop is asserted + */ +#define IOMUXC_GPR_GPR8_LPI2C2_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPI2C2_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR8_LPI2C2_IPG_STOP_MODE_MASK) +#define IOMUXC_GPR_GPR8_LPI2C2_IPG_DOZE_MASK (0x8U) +#define IOMUXC_GPR_GPR8_LPI2C2_IPG_DOZE_SHIFT (3U) +/*! LPI2C2_IPG_DOZE + * 0b0..not in doze mode + * 0b1..in doze mode + */ +#define IOMUXC_GPR_GPR8_LPI2C2_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPI2C2_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR8_LPI2C2_IPG_DOZE_MASK) +#define IOMUXC_GPR_GPR8_LPI2C3_IPG_STOP_MODE_MASK (0x10U) +#define IOMUXC_GPR_GPR8_LPI2C3_IPG_STOP_MODE_SHIFT (4U) +/*! LPI2C3_IPG_STOP_MODE + * 0b0..the module is functional in Stop mode + * 0b1..the module is NOT functional in Stop mode, when this bit is equal to 1 and ipg_stop is asserted + */ +#define IOMUXC_GPR_GPR8_LPI2C3_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPI2C3_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR8_LPI2C3_IPG_STOP_MODE_MASK) +#define IOMUXC_GPR_GPR8_LPI2C3_IPG_DOZE_MASK (0x20U) +#define IOMUXC_GPR_GPR8_LPI2C3_IPG_DOZE_SHIFT (5U) +/*! LPI2C3_IPG_DOZE + * 0b0..not in doze mode + * 0b1..in doze mode + */ +#define IOMUXC_GPR_GPR8_LPI2C3_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPI2C3_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR8_LPI2C3_IPG_DOZE_MASK) +#define IOMUXC_GPR_GPR8_LPI2C4_IPG_STOP_MODE_MASK (0x40U) +#define IOMUXC_GPR_GPR8_LPI2C4_IPG_STOP_MODE_SHIFT (6U) +/*! LPI2C4_IPG_STOP_MODE + * 0b0..the module is functional in Stop mode + * 0b1..the module is NOT functional in Stop mode, when this bit is equal to 1 and ipg_stop is asserted + */ +#define IOMUXC_GPR_GPR8_LPI2C4_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPI2C4_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR8_LPI2C4_IPG_STOP_MODE_MASK) +#define IOMUXC_GPR_GPR8_LPI2C4_IPG_DOZE_MASK (0x80U) +#define IOMUXC_GPR_GPR8_LPI2C4_IPG_DOZE_SHIFT (7U) +/*! LPI2C4_IPG_DOZE + * 0b0..not in doze mode + * 0b1..in doze mode + */ +#define IOMUXC_GPR_GPR8_LPI2C4_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPI2C4_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR8_LPI2C4_IPG_DOZE_MASK) +#define IOMUXC_GPR_GPR8_LPSPI1_IPG_STOP_MODE_MASK (0x100U) +#define IOMUXC_GPR_GPR8_LPSPI1_IPG_STOP_MODE_SHIFT (8U) +/*! LPSPI1_IPG_STOP_MODE + * 0b0..the module is functional in Stop mode + * 0b1..the module is NOT functional in Stop mode, when this bit is equal to 1 and ipg_stop is asserted + */ +#define IOMUXC_GPR_GPR8_LPSPI1_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPSPI1_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR8_LPSPI1_IPG_STOP_MODE_MASK) +#define IOMUXC_GPR_GPR8_LPSPI1_IPG_DOZE_MASK (0x200U) +#define IOMUXC_GPR_GPR8_LPSPI1_IPG_DOZE_SHIFT (9U) +/*! LPSPI1_IPG_DOZE + * 0b0..not in doze mode + * 0b1..in doze mode + */ +#define IOMUXC_GPR_GPR8_LPSPI1_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPSPI1_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR8_LPSPI1_IPG_DOZE_MASK) +#define IOMUXC_GPR_GPR8_LPSPI2_IPG_STOP_MODE_MASK (0x400U) +#define IOMUXC_GPR_GPR8_LPSPI2_IPG_STOP_MODE_SHIFT (10U) +/*! LPSPI2_IPG_STOP_MODE + * 0b0..the module is functional in Stop mode + * 0b1..the module is NOT functional in Stop mode, when this bit is equal to 1 and ipg_stop is asserted + */ +#define IOMUXC_GPR_GPR8_LPSPI2_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPSPI2_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR8_LPSPI2_IPG_STOP_MODE_MASK) +#define IOMUXC_GPR_GPR8_LPSPI2_IPG_DOZE_MASK (0x800U) +#define IOMUXC_GPR_GPR8_LPSPI2_IPG_DOZE_SHIFT (11U) +/*! LPSPI2_IPG_DOZE + * 0b0..not in doze mode + * 0b1..in doze mode + */ +#define IOMUXC_GPR_GPR8_LPSPI2_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPSPI2_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR8_LPSPI2_IPG_DOZE_MASK) +#define IOMUXC_GPR_GPR8_LPSPI3_IPG_STOP_MODE_MASK (0x1000U) +#define IOMUXC_GPR_GPR8_LPSPI3_IPG_STOP_MODE_SHIFT (12U) +/*! LPSPI3_IPG_STOP_MODE + * 0b0..the module is functional in Stop mode + * 0b1..the module is NOT functional in Stop mode, when this bit is equal to 1 and ipg_stop is asserted + */ +#define IOMUXC_GPR_GPR8_LPSPI3_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPSPI3_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR8_LPSPI3_IPG_STOP_MODE_MASK) +#define IOMUXC_GPR_GPR8_LPSPI3_IPG_DOZE_MASK (0x2000U) +#define IOMUXC_GPR_GPR8_LPSPI3_IPG_DOZE_SHIFT (13U) +/*! LPSPI3_IPG_DOZE + * 0b0..not in doze mode + * 0b1..in doze mode + */ +#define IOMUXC_GPR_GPR8_LPSPI3_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPSPI3_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR8_LPSPI3_IPG_DOZE_MASK) +#define IOMUXC_GPR_GPR8_LPSPI4_IPG_STOP_MODE_MASK (0x4000U) +#define IOMUXC_GPR_GPR8_LPSPI4_IPG_STOP_MODE_SHIFT (14U) +/*! LPSPI4_IPG_STOP_MODE + * 0b0..the module is functional in Stop mode + * 0b1..the module is NOT functional in Stop mode, when this bit is equal to 1 and ipg_stop is asserted + */ +#define IOMUXC_GPR_GPR8_LPSPI4_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPSPI4_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR8_LPSPI4_IPG_STOP_MODE_MASK) +#define IOMUXC_GPR_GPR8_LPSPI4_IPG_DOZE_MASK (0x8000U) +#define IOMUXC_GPR_GPR8_LPSPI4_IPG_DOZE_SHIFT (15U) +/*! LPSPI4_IPG_DOZE + * 0b0..not in doze mode + * 0b1..in doze mode + */ +#define IOMUXC_GPR_GPR8_LPSPI4_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPSPI4_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR8_LPSPI4_IPG_DOZE_MASK) +#define IOMUXC_GPR_GPR8_LPUART1_IPG_STOP_MODE_MASK (0x10000U) +#define IOMUXC_GPR_GPR8_LPUART1_IPG_STOP_MODE_SHIFT (16U) +/*! LPUART1_IPG_STOP_MODE + * 0b0..the module is functional in Stop mode + * 0b1..the module is NOT functional in Stop mode, when this bit is equal to 1 and ipg_stop is asserted + */ +#define IOMUXC_GPR_GPR8_LPUART1_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPUART1_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR8_LPUART1_IPG_STOP_MODE_MASK) +#define IOMUXC_GPR_GPR8_LPUART1_IPG_DOZE_MASK (0x20000U) +#define IOMUXC_GPR_GPR8_LPUART1_IPG_DOZE_SHIFT (17U) +/*! LPUART1_IPG_DOZE + * 0b0..not in doze mode + * 0b1..in doze mode + */ +#define IOMUXC_GPR_GPR8_LPUART1_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPUART1_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR8_LPUART1_IPG_DOZE_MASK) +#define IOMUXC_GPR_GPR8_LPUART2_IPG_STOP_MODE_MASK (0x40000U) +#define IOMUXC_GPR_GPR8_LPUART2_IPG_STOP_MODE_SHIFT (18U) +/*! LPUART2_IPG_STOP_MODE + * 0b0..the module is functional in Stop mode + * 0b1..the module is NOT functional in Stop mode, when this bit is equal to 1 and ipg_stop is asserted + */ +#define IOMUXC_GPR_GPR8_LPUART2_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPUART2_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR8_LPUART2_IPG_STOP_MODE_MASK) +#define IOMUXC_GPR_GPR8_LPUART2_IPG_DOZE_MASK (0x80000U) +#define IOMUXC_GPR_GPR8_LPUART2_IPG_DOZE_SHIFT (19U) +/*! LPUART2_IPG_DOZE + * 0b0..not in doze mode + * 0b1..in doze mode + */ +#define IOMUXC_GPR_GPR8_LPUART2_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPUART2_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR8_LPUART2_IPG_DOZE_MASK) +#define IOMUXC_GPR_GPR8_LPUART3_IPG_STOP_MODE_MASK (0x100000U) +#define IOMUXC_GPR_GPR8_LPUART3_IPG_STOP_MODE_SHIFT (20U) +/*! LPUART3_IPG_STOP_MODE + * 0b0..the module is functional in Stop mode + * 0b1..the module is NOT functional in Stop mode, when this bit is equal to 1 and ipg_stop is asserted + */ +#define IOMUXC_GPR_GPR8_LPUART3_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPUART3_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR8_LPUART3_IPG_STOP_MODE_MASK) +#define IOMUXC_GPR_GPR8_LPUART3_IPG_DOZE_MASK (0x200000U) +#define IOMUXC_GPR_GPR8_LPUART3_IPG_DOZE_SHIFT (21U) +/*! LPUART3_IPG_DOZE + * 0b0..not in doze mode + * 0b1..in doze mode + */ +#define IOMUXC_GPR_GPR8_LPUART3_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPUART3_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR8_LPUART3_IPG_DOZE_MASK) +#define IOMUXC_GPR_GPR8_LPUART4_IPG_STOP_MODE_MASK (0x400000U) +#define IOMUXC_GPR_GPR8_LPUART4_IPG_STOP_MODE_SHIFT (22U) +/*! LPUART4_IPG_STOP_MODE + * 0b0..the module is functional in Stop mode + * 0b1..the module is NOT functional in Stop mode, when this bit is equal to 1 and ipg_stop is asserted + */ +#define IOMUXC_GPR_GPR8_LPUART4_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPUART4_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR8_LPUART4_IPG_STOP_MODE_MASK) +#define IOMUXC_GPR_GPR8_LPUART4_IPG_DOZE_MASK (0x800000U) +#define IOMUXC_GPR_GPR8_LPUART4_IPG_DOZE_SHIFT (23U) +/*! LPUART4_IPG_DOZE + * 0b0..not in doze mode + * 0b1..in doze mode + */ +#define IOMUXC_GPR_GPR8_LPUART4_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPUART4_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR8_LPUART4_IPG_DOZE_MASK) +#define IOMUXC_GPR_GPR8_LPUART5_IPG_STOP_MODE_MASK (0x1000000U) +#define IOMUXC_GPR_GPR8_LPUART5_IPG_STOP_MODE_SHIFT (24U) +/*! LPUART5_IPG_STOP_MODE + * 0b0..the module is functional in Stop mode + * 0b1..the module is NOT functional in Stop mode, when this bit is equal to 1 and ipg_stop is asserted + */ +#define IOMUXC_GPR_GPR8_LPUART5_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPUART5_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR8_LPUART5_IPG_STOP_MODE_MASK) +#define IOMUXC_GPR_GPR8_LPUART5_IPG_DOZE_MASK (0x2000000U) +#define IOMUXC_GPR_GPR8_LPUART5_IPG_DOZE_SHIFT (25U) +/*! LPUART5_IPG_DOZE + * 0b0..not in doze mode + * 0b1..in doze mode + */ +#define IOMUXC_GPR_GPR8_LPUART5_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPUART5_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR8_LPUART5_IPG_DOZE_MASK) +#define IOMUXC_GPR_GPR8_LPUART6_IPG_STOP_MODE_MASK (0x4000000U) +#define IOMUXC_GPR_GPR8_LPUART6_IPG_STOP_MODE_SHIFT (26U) +/*! LPUART6_IPG_STOP_MODE + * 0b0..the module is functional in Stop mode + * 0b1..the module is NOT functional in Stop mode, when this bit is equal to 1 and ipg_stop is asserted + */ +#define IOMUXC_GPR_GPR8_LPUART6_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPUART6_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR8_LPUART6_IPG_STOP_MODE_MASK) +#define IOMUXC_GPR_GPR8_LPUART6_IPG_DOZE_MASK (0x8000000U) +#define IOMUXC_GPR_GPR8_LPUART6_IPG_DOZE_SHIFT (27U) +/*! LPUART6_IPG_DOZE + * 0b0..not in doze mode + * 0b1..in doze mode + */ +#define IOMUXC_GPR_GPR8_LPUART6_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPUART6_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR8_LPUART6_IPG_DOZE_MASK) +#define IOMUXC_GPR_GPR8_LPUART7_IPG_STOP_MODE_MASK (0x10000000U) +#define IOMUXC_GPR_GPR8_LPUART7_IPG_STOP_MODE_SHIFT (28U) +/*! LPUART7_IPG_STOP_MODE + * 0b0..the module is functional in Stop mode + * 0b1..the module is NOT functional in Stop mode, when this bit is equal to 1 and ipg_stop is asserted + */ +#define IOMUXC_GPR_GPR8_LPUART7_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPUART7_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR8_LPUART7_IPG_STOP_MODE_MASK) +#define IOMUXC_GPR_GPR8_LPUART7_IPG_DOZE_MASK (0x20000000U) +#define IOMUXC_GPR_GPR8_LPUART7_IPG_DOZE_SHIFT (29U) +/*! LPUART7_IPG_DOZE + * 0b0..not in doze mode + * 0b1..in doze mode + */ +#define IOMUXC_GPR_GPR8_LPUART7_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPUART7_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR8_LPUART7_IPG_DOZE_MASK) +#define IOMUXC_GPR_GPR8_LPUART8_IPG_STOP_MODE_MASK (0x40000000U) +#define IOMUXC_GPR_GPR8_LPUART8_IPG_STOP_MODE_SHIFT (30U) +/*! LPUART8_IPG_STOP_MODE + * 0b0..the module is functional in Stop mode + * 0b1..the module is NOT functional in Stop mode, when this bit is equal to 1 and ipg_stop is asserted + */ +#define IOMUXC_GPR_GPR8_LPUART8_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPUART8_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR8_LPUART8_IPG_STOP_MODE_MASK) +#define IOMUXC_GPR_GPR8_LPUART8_IPG_DOZE_MASK (0x80000000U) +#define IOMUXC_GPR_GPR8_LPUART8_IPG_DOZE_SHIFT (31U) +/*! LPUART8_IPG_DOZE + * 0b0..not in doze mode + * 0b1..in doze mode + */ +#define IOMUXC_GPR_GPR8_LPUART8_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPUART8_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR8_LPUART8_IPG_DOZE_MASK) +/*! @} */ + +/*! @name GPR10 - GPR10 General Purpose Register */ +/*! @{ */ +#define IOMUXC_GPR_GPR10_NIDEN_MASK (0x1U) +#define IOMUXC_GPR_GPR10_NIDEN_SHIFT (0U) +/*! NIDEN + * 0b0..Debug turned off. + * 0b1..Debug enabled (default). + */ +#define IOMUXC_GPR_GPR10_NIDEN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR10_NIDEN_SHIFT)) & IOMUXC_GPR_GPR10_NIDEN_MASK) +#define IOMUXC_GPR_GPR10_DBG_EN_MASK (0x2U) +#define IOMUXC_GPR_GPR10_DBG_EN_SHIFT (1U) +/*! DBG_EN + * 0b0..Debug turned off. + * 0b1..Debug enabled (default). + */ +#define IOMUXC_GPR_GPR10_DBG_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR10_DBG_EN_SHIFT)) & IOMUXC_GPR_GPR10_DBG_EN_MASK) +#define IOMUXC_GPR_GPR10_SEC_ERR_RESP_MASK (0x4U) +#define IOMUXC_GPR_GPR10_SEC_ERR_RESP_SHIFT (2U) +/*! SEC_ERR_RESP + * 0b0..OKEY response + * 0b1..SLVError (default) + */ +#define IOMUXC_GPR_GPR10_SEC_ERR_RESP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR10_SEC_ERR_RESP_SHIFT)) & IOMUXC_GPR_GPR10_SEC_ERR_RESP_MASK) +#define IOMUXC_GPR_GPR10_DCPKEY_OCOTP_OR_KEYMUX_MASK (0x10U) +#define IOMUXC_GPR_GPR10_DCPKEY_OCOTP_OR_KEYMUX_SHIFT (4U) +/*! DCPKEY_OCOTP_OR_KEYMUX + * 0b0..Select key from Key MUX (SNVS/OTPMK). + * 0b1..Select key from OCOTP (SW_GP2). + */ +#define IOMUXC_GPR_GPR10_DCPKEY_OCOTP_OR_KEYMUX(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR10_DCPKEY_OCOTP_OR_KEYMUX_SHIFT)) & IOMUXC_GPR_GPR10_DCPKEY_OCOTP_OR_KEYMUX_MASK) +#define IOMUXC_GPR_GPR10_OCRAM_TZ_EN_MASK (0x100U) +#define IOMUXC_GPR_GPR10_OCRAM_TZ_EN_SHIFT (8U) +/*! OCRAM_TZ_EN + * 0b0..The TrustZone feature is disabled. Entire OCRAM space is available for all access types (secure/non-secure/user/supervisor). + * 0b1..The TrustZone feature is enabled. Access to address in the range specified by [ENDADDR:STARTADDR] follows the execution mode access policy described in CSU chapter. + */ +#define IOMUXC_GPR_GPR10_OCRAM_TZ_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR10_OCRAM_TZ_EN_SHIFT)) & IOMUXC_GPR_GPR10_OCRAM_TZ_EN_MASK) +#define IOMUXC_GPR_GPR10_OCRAM_TZ_ADDR_MASK (0xFE00U) +#define IOMUXC_GPR_GPR10_OCRAM_TZ_ADDR_SHIFT (9U) +#define IOMUXC_GPR_GPR10_OCRAM_TZ_ADDR(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR10_OCRAM_TZ_ADDR_SHIFT)) & IOMUXC_GPR_GPR10_OCRAM_TZ_ADDR_MASK) +#define IOMUXC_GPR_GPR10_LOCK_NIDEN_MASK (0x10000U) +#define IOMUXC_GPR_GPR10_LOCK_NIDEN_SHIFT (16U) +/*! LOCK_NIDEN + * 0b0..Field is not locked + * 0b1..Field is locked (read access only) + */ +#define IOMUXC_GPR_GPR10_LOCK_NIDEN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR10_LOCK_NIDEN_SHIFT)) & IOMUXC_GPR_GPR10_LOCK_NIDEN_MASK) +#define IOMUXC_GPR_GPR10_LOCK_DBG_EN_MASK (0x20000U) +#define IOMUXC_GPR_GPR10_LOCK_DBG_EN_SHIFT (17U) +/*! LOCK_DBG_EN + * 0b0..Field is not locked + * 0b1..Field is locked (read access only) + */ +#define IOMUXC_GPR_GPR10_LOCK_DBG_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR10_LOCK_DBG_EN_SHIFT)) & IOMUXC_GPR_GPR10_LOCK_DBG_EN_MASK) +#define IOMUXC_GPR_GPR10_LOCK_SEC_ERR_RESP_MASK (0x40000U) +#define IOMUXC_GPR_GPR10_LOCK_SEC_ERR_RESP_SHIFT (18U) +/*! LOCK_SEC_ERR_RESP + * 0b0..Field is not locked + * 0b1..Field is locked (read access only) + */ +#define IOMUXC_GPR_GPR10_LOCK_SEC_ERR_RESP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR10_LOCK_SEC_ERR_RESP_SHIFT)) & IOMUXC_GPR_GPR10_LOCK_SEC_ERR_RESP_MASK) +#define IOMUXC_GPR_GPR10_LOCK_DCPKEY_OCOTP_OR_KEYMUX_MASK (0x100000U) +#define IOMUXC_GPR_GPR10_LOCK_DCPKEY_OCOTP_OR_KEYMUX_SHIFT (20U) +/*! LOCK_DCPKEY_OCOTP_OR_KEYMUX + * 0b0..Field is not locked + * 0b1..Field is locked (read access only) + */ +#define IOMUXC_GPR_GPR10_LOCK_DCPKEY_OCOTP_OR_KEYMUX(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR10_LOCK_DCPKEY_OCOTP_OR_KEYMUX_SHIFT)) & IOMUXC_GPR_GPR10_LOCK_DCPKEY_OCOTP_OR_KEYMUX_MASK) +#define IOMUXC_GPR_GPR10_LOCK_OCRAM_TZ_EN_MASK (0x1000000U) +#define IOMUXC_GPR_GPR10_LOCK_OCRAM_TZ_EN_SHIFT (24U) +/*! LOCK_OCRAM_TZ_EN + * 0b0..Field is not locked + * 0b1..Field is locked (read access only) + */ +#define IOMUXC_GPR_GPR10_LOCK_OCRAM_TZ_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR10_LOCK_OCRAM_TZ_EN_SHIFT)) & IOMUXC_GPR_GPR10_LOCK_OCRAM_TZ_EN_MASK) +#define IOMUXC_GPR_GPR10_LOCK_OCRAM_TZ_ADDR_MASK (0xFE000000U) +#define IOMUXC_GPR_GPR10_LOCK_OCRAM_TZ_ADDR_SHIFT (25U) +/*! LOCK_OCRAM_TZ_ADDR + * 0b0000000..Field is not locked + * 0b0000001..Field is locked (read access only) + */ +#define IOMUXC_GPR_GPR10_LOCK_OCRAM_TZ_ADDR(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR10_LOCK_OCRAM_TZ_ADDR_SHIFT)) & IOMUXC_GPR_GPR10_LOCK_OCRAM_TZ_ADDR_MASK) +/*! @} */ + +/*! @name GPR11 - GPR11 General Purpose Register */ +/*! @{ */ +#define IOMUXC_GPR_GPR11_M7_APC_AC_R0_CTRL_MASK (0x3U) +#define IOMUXC_GPR_GPR11_M7_APC_AC_R0_CTRL_SHIFT (0U) +/*! M7_APC_AC_R0_CTRL + * 0b00..No access protection + * 0b01..M7 debug protection enabled + * 0b10..FlexSPI access protection + * 0b11..Both M7 debug and FlexSPI access are protected + */ +#define IOMUXC_GPR_GPR11_M7_APC_AC_R0_CTRL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR11_M7_APC_AC_R0_CTRL_SHIFT)) & IOMUXC_GPR_GPR11_M7_APC_AC_R0_CTRL_MASK) +#define IOMUXC_GPR_GPR11_M7_APC_AC_R1_CTRL_MASK (0xCU) +#define IOMUXC_GPR_GPR11_M7_APC_AC_R1_CTRL_SHIFT (2U) +/*! M7_APC_AC_R1_CTRL + * 0b00..No access protection + * 0b01..M7 debug protection enabled + * 0b10..FlexSPI access protection + * 0b11..Both M7 debug and FlexSPI access are protected + */ +#define IOMUXC_GPR_GPR11_M7_APC_AC_R1_CTRL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR11_M7_APC_AC_R1_CTRL_SHIFT)) & IOMUXC_GPR_GPR11_M7_APC_AC_R1_CTRL_MASK) +#define IOMUXC_GPR_GPR11_M7_APC_AC_R2_CTRL_MASK (0x30U) +#define IOMUXC_GPR_GPR11_M7_APC_AC_R2_CTRL_SHIFT (4U) +/*! M7_APC_AC_R2_CTRL + * 0b00..No access protection + * 0b01..M7 debug protection enabled + * 0b10..FlexSPI access protection + * 0b11..Both M7 debug and FlexSPI access are protected + */ +#define IOMUXC_GPR_GPR11_M7_APC_AC_R2_CTRL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR11_M7_APC_AC_R2_CTRL_SHIFT)) & IOMUXC_GPR_GPR11_M7_APC_AC_R2_CTRL_MASK) +#define IOMUXC_GPR_GPR11_M7_APC_AC_R3_CTRL_MASK (0xC0U) +#define IOMUXC_GPR_GPR11_M7_APC_AC_R3_CTRL_SHIFT (6U) +/*! M7_APC_AC_R3_CTRL + * 0b00..No access protection + * 0b01..M7 debug protection enabled + * 0b10..FlexSPI access protection + * 0b11..Both M7 debug and FlexSPI access are protected + */ +#define IOMUXC_GPR_GPR11_M7_APC_AC_R3_CTRL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR11_M7_APC_AC_R3_CTRL_SHIFT)) & IOMUXC_GPR_GPR11_M7_APC_AC_R3_CTRL_MASK) +#define IOMUXC_GPR_GPR11_BEE_DE_RX_EN_MASK (0xF00U) +#define IOMUXC_GPR_GPR11_BEE_DE_RX_EN_SHIFT (8U) +#define IOMUXC_GPR_GPR11_BEE_DE_RX_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR11_BEE_DE_RX_EN_SHIFT)) & IOMUXC_GPR_GPR11_BEE_DE_RX_EN_MASK) +#define IOMUXC_GPR_GPR11_LOCK_M7_APC_AC_R0_CTRL_MASK (0x30000U) +#define IOMUXC_GPR_GPR11_LOCK_M7_APC_AC_R0_CTRL_SHIFT (16U) +#define IOMUXC_GPR_GPR11_LOCK_M7_APC_AC_R0_CTRL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR11_LOCK_M7_APC_AC_R0_CTRL_SHIFT)) & IOMUXC_GPR_GPR11_LOCK_M7_APC_AC_R0_CTRL_MASK) +#define IOMUXC_GPR_GPR11_LOCK_M7_APC_AC_R1_CTRL_MASK (0xC0000U) +#define IOMUXC_GPR_GPR11_LOCK_M7_APC_AC_R1_CTRL_SHIFT (18U) +#define IOMUXC_GPR_GPR11_LOCK_M7_APC_AC_R1_CTRL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR11_LOCK_M7_APC_AC_R1_CTRL_SHIFT)) & IOMUXC_GPR_GPR11_LOCK_M7_APC_AC_R1_CTRL_MASK) +#define IOMUXC_GPR_GPR11_LOCK_M7_APC_AC_R2_CTRL_MASK (0x300000U) +#define IOMUXC_GPR_GPR11_LOCK_M7_APC_AC_R2_CTRL_SHIFT (20U) +#define IOMUXC_GPR_GPR11_LOCK_M7_APC_AC_R2_CTRL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR11_LOCK_M7_APC_AC_R2_CTRL_SHIFT)) & IOMUXC_GPR_GPR11_LOCK_M7_APC_AC_R2_CTRL_MASK) +#define IOMUXC_GPR_GPR11_LOCK_M7_APC_AC_R3_CTRL_MASK (0xC00000U) +#define IOMUXC_GPR_GPR11_LOCK_M7_APC_AC_R3_CTRL_SHIFT (22U) +#define IOMUXC_GPR_GPR11_LOCK_M7_APC_AC_R3_CTRL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR11_LOCK_M7_APC_AC_R3_CTRL_SHIFT)) & IOMUXC_GPR_GPR11_LOCK_M7_APC_AC_R3_CTRL_MASK) +#define IOMUXC_GPR_GPR11_LOCK_BEE_DE_RX_EN_MASK (0xF000000U) +#define IOMUXC_GPR_GPR11_LOCK_BEE_DE_RX_EN_SHIFT (24U) +#define IOMUXC_GPR_GPR11_LOCK_BEE_DE_RX_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR11_LOCK_BEE_DE_RX_EN_SHIFT)) & IOMUXC_GPR_GPR11_LOCK_BEE_DE_RX_EN_MASK) +/*! @} */ + +/*! @name GPR12 - GPR12 General Purpose Register */ +/*! @{ */ +#define IOMUXC_GPR_GPR12_FLEXIO1_IPG_STOP_MODE_MASK (0x1U) +#define IOMUXC_GPR_GPR12_FLEXIO1_IPG_STOP_MODE_SHIFT (0U) +/*! FLEXIO1_IPG_STOP_MODE + * 0b0..FlexIO1 is functional in Stop mode. + * 0b1..When this bit is equal to 1'b1 and ipg_stop is asserted, FlexIO1 is not functional in Stop mode. + */ +#define IOMUXC_GPR_GPR12_FLEXIO1_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR12_FLEXIO1_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR12_FLEXIO1_IPG_STOP_MODE_MASK) +#define IOMUXC_GPR_GPR12_FLEXIO1_IPG_DOZE_MASK (0x2U) +#define IOMUXC_GPR_GPR12_FLEXIO1_IPG_DOZE_SHIFT (1U) +/*! FLEXIO1_IPG_DOZE + * 0b0..FLEXIO1 is not in doze mode + * 0b1..FLEXIO1 is in doze mode + */ +#define IOMUXC_GPR_GPR12_FLEXIO1_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR12_FLEXIO1_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR12_FLEXIO1_IPG_DOZE_MASK) +#define IOMUXC_GPR_GPR12_FLEXIO2_IPG_STOP_MODE_MASK (0x4U) +#define IOMUXC_GPR_GPR12_FLEXIO2_IPG_STOP_MODE_SHIFT (2U) +/*! FLEXIO2_IPG_STOP_MODE + * 0b0..FlexIO2 is functional in Stop mode. + * 0b1..When this bit is equal to 1'b1 and ipg_stop is asserted, FlexIO2 is not functional in Stop mode. + */ +#define IOMUXC_GPR_GPR12_FLEXIO2_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR12_FLEXIO2_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR12_FLEXIO2_IPG_STOP_MODE_MASK) +#define IOMUXC_GPR_GPR12_FLEXIO2_IPG_DOZE_MASK (0x8U) +#define IOMUXC_GPR_GPR12_FLEXIO2_IPG_DOZE_SHIFT (3U) +/*! FLEXIO2_IPG_DOZE + * 0b0..FLEXIO2 is not in doze mode + * 0b1..FLEXIO2 is in doze mode + */ +#define IOMUXC_GPR_GPR12_FLEXIO2_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR12_FLEXIO2_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR12_FLEXIO2_IPG_DOZE_MASK) +#define IOMUXC_GPR_GPR12_ACMP_IPG_STOP_MODE_MASK (0x10U) +#define IOMUXC_GPR_GPR12_ACMP_IPG_STOP_MODE_SHIFT (4U) +/*! ACMP_IPG_STOP_MODE + * 0b0..ACMP is functional in Stop mode. + * 0b1..When this bit is equal to 1'b1 and ipg_stop is asserted, ACMP is not functional in Stop mode. + */ +#define IOMUXC_GPR_GPR12_ACMP_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR12_ACMP_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR12_ACMP_IPG_STOP_MODE_MASK) +/*! @} */ + +/*! @name GPR13 - GPR13 General Purpose Register */ +/*! @{ */ +#define IOMUXC_GPR_GPR13_ARCACHE_USDHC_MASK (0x1U) +#define IOMUXC_GPR_GPR13_ARCACHE_USDHC_SHIFT (0U) +/*! ARCACHE_USDHC + * 0b0..Cacheable attribute is off for read transactions. + * 0b1..Cacheable attribute is on for read transactions. + */ +#define IOMUXC_GPR_GPR13_ARCACHE_USDHC(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR13_ARCACHE_USDHC_SHIFT)) & IOMUXC_GPR_GPR13_ARCACHE_USDHC_MASK) +#define IOMUXC_GPR_GPR13_AWCACHE_USDHC_MASK (0x2U) +#define IOMUXC_GPR_GPR13_AWCACHE_USDHC_SHIFT (1U) +/*! AWCACHE_USDHC + * 0b0..Cacheable attribute is off for write transactions. + * 0b1..Cacheable attribute is on for write transactions. + */ +#define IOMUXC_GPR_GPR13_AWCACHE_USDHC(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR13_AWCACHE_USDHC_SHIFT)) & IOMUXC_GPR_GPR13_AWCACHE_USDHC_MASK) +#define IOMUXC_GPR_GPR13_CACHE_ENET_MASK (0x80U) +#define IOMUXC_GPR_GPR13_CACHE_ENET_SHIFT (7U) +/*! CACHE_ENET + * 0b0..Cacheable attribute is off for read/write transactions. + * 0b1..Cacheable attribute is on for read/write transactions. + */ +#define IOMUXC_GPR_GPR13_CACHE_ENET(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR13_CACHE_ENET_SHIFT)) & IOMUXC_GPR_GPR13_CACHE_ENET_MASK) +#define IOMUXC_GPR_GPR13_CACHE_USB_MASK (0x2000U) +#define IOMUXC_GPR_GPR13_CACHE_USB_SHIFT (13U) +/*! CACHE_USB + * 0b0..Cacheable attribute is off for read/write transactions. + * 0b1..Cacheable attribute is on for read/write transactions. + */ +#define IOMUXC_GPR_GPR13_CACHE_USB(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR13_CACHE_USB_SHIFT)) & IOMUXC_GPR_GPR13_CACHE_USB_MASK) +/*! @} */ + +/*! @name GPR14 - GPR14 General Purpose Register */ +/*! @{ */ +#define IOMUXC_GPR_GPR14_ACMP1_CMP_IGEN_TRIM_DN_MASK (0x1U) +#define IOMUXC_GPR_GPR14_ACMP1_CMP_IGEN_TRIM_DN_SHIFT (0U) +/*! ACMP1_CMP_IGEN_TRIM_DN + * 0b0..no reduce + * 0b1..reduces + */ +#define IOMUXC_GPR_GPR14_ACMP1_CMP_IGEN_TRIM_DN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR14_ACMP1_CMP_IGEN_TRIM_DN_SHIFT)) & IOMUXC_GPR_GPR14_ACMP1_CMP_IGEN_TRIM_DN_MASK) +#define IOMUXC_GPR_GPR14_ACMP2_CMP_IGEN_TRIM_DN_MASK (0x2U) +#define IOMUXC_GPR_GPR14_ACMP2_CMP_IGEN_TRIM_DN_SHIFT (1U) +/*! ACMP2_CMP_IGEN_TRIM_DN + * 0b0..no reduce + * 0b1..reduces + */ +#define IOMUXC_GPR_GPR14_ACMP2_CMP_IGEN_TRIM_DN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR14_ACMP2_CMP_IGEN_TRIM_DN_SHIFT)) & IOMUXC_GPR_GPR14_ACMP2_CMP_IGEN_TRIM_DN_MASK) +#define IOMUXC_GPR_GPR14_ACMP3_CMP_IGEN_TRIM_DN_MASK (0x4U) +#define IOMUXC_GPR_GPR14_ACMP3_CMP_IGEN_TRIM_DN_SHIFT (2U) +/*! ACMP3_CMP_IGEN_TRIM_DN + * 0b0..no reduce + * 0b1..reduces + */ +#define IOMUXC_GPR_GPR14_ACMP3_CMP_IGEN_TRIM_DN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR14_ACMP3_CMP_IGEN_TRIM_DN_SHIFT)) & IOMUXC_GPR_GPR14_ACMP3_CMP_IGEN_TRIM_DN_MASK) +#define IOMUXC_GPR_GPR14_ACMP4_CMP_IGEN_TRIM_DN_MASK (0x8U) +#define IOMUXC_GPR_GPR14_ACMP4_CMP_IGEN_TRIM_DN_SHIFT (3U) +/*! ACMP4_CMP_IGEN_TRIM_DN + * 0b0..no reduce + * 0b1..reduces + */ +#define IOMUXC_GPR_GPR14_ACMP4_CMP_IGEN_TRIM_DN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR14_ACMP4_CMP_IGEN_TRIM_DN_SHIFT)) & IOMUXC_GPR_GPR14_ACMP4_CMP_IGEN_TRIM_DN_MASK) +#define IOMUXC_GPR_GPR14_ACMP1_CMP_IGEN_TRIM_UP_MASK (0x10U) +#define IOMUXC_GPR_GPR14_ACMP1_CMP_IGEN_TRIM_UP_SHIFT (4U) +/*! ACMP1_CMP_IGEN_TRIM_UP + * 0b0..no increase + * 0b1..increases + */ +#define IOMUXC_GPR_GPR14_ACMP1_CMP_IGEN_TRIM_UP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR14_ACMP1_CMP_IGEN_TRIM_UP_SHIFT)) & IOMUXC_GPR_GPR14_ACMP1_CMP_IGEN_TRIM_UP_MASK) +#define IOMUXC_GPR_GPR14_ACMP2_CMP_IGEN_TRIM_UP_MASK (0x20U) +#define IOMUXC_GPR_GPR14_ACMP2_CMP_IGEN_TRIM_UP_SHIFT (5U) +/*! ACMP2_CMP_IGEN_TRIM_UP + * 0b0..no increase + * 0b1..increases + */ +#define IOMUXC_GPR_GPR14_ACMP2_CMP_IGEN_TRIM_UP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR14_ACMP2_CMP_IGEN_TRIM_UP_SHIFT)) & IOMUXC_GPR_GPR14_ACMP2_CMP_IGEN_TRIM_UP_MASK) +#define IOMUXC_GPR_GPR14_ACMP3_CMP_IGEN_TRIM_UP_MASK (0x40U) +#define IOMUXC_GPR_GPR14_ACMP3_CMP_IGEN_TRIM_UP_SHIFT (6U) +/*! ACMP3_CMP_IGEN_TRIM_UP + * 0b0..no increase + * 0b1..increases + */ +#define IOMUXC_GPR_GPR14_ACMP3_CMP_IGEN_TRIM_UP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR14_ACMP3_CMP_IGEN_TRIM_UP_SHIFT)) & IOMUXC_GPR_GPR14_ACMP3_CMP_IGEN_TRIM_UP_MASK) +#define IOMUXC_GPR_GPR14_ACMP4_CMP_IGEN_TRIM_UP_MASK (0x80U) +#define IOMUXC_GPR_GPR14_ACMP4_CMP_IGEN_TRIM_UP_SHIFT (7U) +/*! ACMP4_CMP_IGEN_TRIM_UP + * 0b0..no increase + * 0b1..increases + */ +#define IOMUXC_GPR_GPR14_ACMP4_CMP_IGEN_TRIM_UP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR14_ACMP4_CMP_IGEN_TRIM_UP_SHIFT)) & IOMUXC_GPR_GPR14_ACMP4_CMP_IGEN_TRIM_UP_MASK) +#define IOMUXC_GPR_GPR14_ACMP1_SAMPLE_SYNC_EN_MASK (0x100U) +#define IOMUXC_GPR_GPR14_ACMP1_SAMPLE_SYNC_EN_SHIFT (8U) +/*! ACMP1_SAMPLE_SYNC_EN + * 0b0..select XBAR output + * 0b1..select synced sample_lv + */ +#define IOMUXC_GPR_GPR14_ACMP1_SAMPLE_SYNC_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR14_ACMP1_SAMPLE_SYNC_EN_SHIFT)) & IOMUXC_GPR_GPR14_ACMP1_SAMPLE_SYNC_EN_MASK) +#define IOMUXC_GPR_GPR14_ACMP2_SAMPLE_SYNC_EN_MASK (0x200U) +#define IOMUXC_GPR_GPR14_ACMP2_SAMPLE_SYNC_EN_SHIFT (9U) +/*! ACMP2_SAMPLE_SYNC_EN + * 0b0..select XBAR output + * 0b1..select synced sample_lv + */ +#define IOMUXC_GPR_GPR14_ACMP2_SAMPLE_SYNC_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR14_ACMP2_SAMPLE_SYNC_EN_SHIFT)) & IOMUXC_GPR_GPR14_ACMP2_SAMPLE_SYNC_EN_MASK) +#define IOMUXC_GPR_GPR14_ACMP3_SAMPLE_SYNC_EN_MASK (0x400U) +#define IOMUXC_GPR_GPR14_ACMP3_SAMPLE_SYNC_EN_SHIFT (10U) +/*! ACMP3_SAMPLE_SYNC_EN + * 0b0..select XBAR output + * 0b1..select synced sample_lv + */ +#define IOMUXC_GPR_GPR14_ACMP3_SAMPLE_SYNC_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR14_ACMP3_SAMPLE_SYNC_EN_SHIFT)) & IOMUXC_GPR_GPR14_ACMP3_SAMPLE_SYNC_EN_MASK) +#define IOMUXC_GPR_GPR14_ACMP4_SAMPLE_SYNC_EN_MASK (0x800U) +#define IOMUXC_GPR_GPR14_ACMP4_SAMPLE_SYNC_EN_SHIFT (11U) +/*! ACMP4_SAMPLE_SYNC_EN + * 0b0..select XBAR output + * 0b1..select synced sample_lv + */ +#define IOMUXC_GPR_GPR14_ACMP4_SAMPLE_SYNC_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR14_ACMP4_SAMPLE_SYNC_EN_SHIFT)) & IOMUXC_GPR_GPR14_ACMP4_SAMPLE_SYNC_EN_MASK) +#define IOMUXC_GPR_GPR14_CM7_CFGITCMSZ_MASK (0xF0000U) +#define IOMUXC_GPR_GPR14_CM7_CFGITCMSZ_SHIFT (16U) +/*! CM7_CFGITCMSZ + * 0b0000..0 KB (No ITCM) + * 0b0011..4 KB + * 0b0100..8 KB + * 0b0101..16 KB + * 0b0110..32 KB + * 0b0111..64 KB + * 0b1000..128 KB + * 0b1001..256 KB + * 0b1010..512 KB + */ +#define IOMUXC_GPR_GPR14_CM7_CFGITCMSZ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR14_CM7_CFGITCMSZ_SHIFT)) & IOMUXC_GPR_GPR14_CM7_CFGITCMSZ_MASK) +#define IOMUXC_GPR_GPR14_CM7_CFGDTCMSZ_MASK (0xF00000U) +#define IOMUXC_GPR_GPR14_CM7_CFGDTCMSZ_SHIFT (20U) +/*! CM7_CFGDTCMSZ + * 0b0000..0 KB (No DTCM) + * 0b0011..4 KB + * 0b0100..8 KB + * 0b0101..16 KB + * 0b0110..32 KB + * 0b0111..64 KB + * 0b1000..128 KB + * 0b1001..256 KB + * 0b1010..512 KB + */ +#define IOMUXC_GPR_GPR14_CM7_CFGDTCMSZ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR14_CM7_CFGDTCMSZ_SHIFT)) & IOMUXC_GPR_GPR14_CM7_CFGDTCMSZ_MASK) +/*! @} */ + +/*! @name GPR16 - GPR16 General Purpose Register */ +/*! @{ */ +#define IOMUXC_GPR_GPR16_INIT_ITCM_EN_MASK (0x1U) +#define IOMUXC_GPR_GPR16_INIT_ITCM_EN_SHIFT (0U) +/*! INIT_ITCM_EN + * 0b0..ITCM is disabled + * 0b1..ITCM is enabled + */ +#define IOMUXC_GPR_GPR16_INIT_ITCM_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR16_INIT_ITCM_EN_SHIFT)) & IOMUXC_GPR_GPR16_INIT_ITCM_EN_MASK) +#define IOMUXC_GPR_GPR16_INIT_DTCM_EN_MASK (0x2U) +#define IOMUXC_GPR_GPR16_INIT_DTCM_EN_SHIFT (1U) +/*! INIT_DTCM_EN + * 0b0..DTCM is disabled + * 0b1..DTCM is enabled + */ +#define IOMUXC_GPR_GPR16_INIT_DTCM_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR16_INIT_DTCM_EN_SHIFT)) & IOMUXC_GPR_GPR16_INIT_DTCM_EN_MASK) +#define IOMUXC_GPR_GPR16_FLEXRAM_BANK_CFG_SEL_MASK (0x4U) +#define IOMUXC_GPR_GPR16_FLEXRAM_BANK_CFG_SEL_SHIFT (2U) +/*! FLEXRAM_BANK_CFG_SEL + * 0b0..use fuse value to config + * 0b1..use FLEXRAM_BANK_CFG to config + */ +#define IOMUXC_GPR_GPR16_FLEXRAM_BANK_CFG_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR16_FLEXRAM_BANK_CFG_SEL_SHIFT)) & IOMUXC_GPR_GPR16_FLEXRAM_BANK_CFG_SEL_MASK) +/*! @} */ + +/*! @name GPR17 - GPR17 General Purpose Register */ +/*! @{ */ +#define IOMUXC_GPR_GPR17_FLEXRAM_BANK_CFG_MASK (0xFFFFFFFFU) +#define IOMUXC_GPR_GPR17_FLEXRAM_BANK_CFG_SHIFT (0U) +#define IOMUXC_GPR_GPR17_FLEXRAM_BANK_CFG(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR17_FLEXRAM_BANK_CFG_SHIFT)) & IOMUXC_GPR_GPR17_FLEXRAM_BANK_CFG_MASK) +/*! @} */ + +/*! @name GPR18 - GPR18 General Purpose Register */ +/*! @{ */ +#define IOMUXC_GPR_GPR18_LOCK_M7_APC_AC_R0_BOT_MASK (0x1U) +#define IOMUXC_GPR_GPR18_LOCK_M7_APC_AC_R0_BOT_SHIFT (0U) +/*! LOCK_M7_APC_AC_R0_BOT + * 0b0..Register field [31:1] is not locked + * 0b1..Register field [31:1] is locked (read access only) + */ +#define IOMUXC_GPR_GPR18_LOCK_M7_APC_AC_R0_BOT(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR18_LOCK_M7_APC_AC_R0_BOT_SHIFT)) & IOMUXC_GPR_GPR18_LOCK_M7_APC_AC_R0_BOT_MASK) +#define IOMUXC_GPR_GPR18_M7_APC_AC_R0_BOT_MASK (0xFFFFFFF8U) +#define IOMUXC_GPR_GPR18_M7_APC_AC_R0_BOT_SHIFT (3U) +#define IOMUXC_GPR_GPR18_M7_APC_AC_R0_BOT(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR18_M7_APC_AC_R0_BOT_SHIFT)) & IOMUXC_GPR_GPR18_M7_APC_AC_R0_BOT_MASK) +/*! @} */ + +/*! @name GPR19 - GPR19 General Purpose Register */ +/*! @{ */ +#define IOMUXC_GPR_GPR19_LOCK_M7_APC_AC_R0_TOP_MASK (0x1U) +#define IOMUXC_GPR_GPR19_LOCK_M7_APC_AC_R0_TOP_SHIFT (0U) +/*! LOCK_M7_APC_AC_R0_TOP + * 0b0..Register field [31:1] is not locked + * 0b1..Register field [31:1] is locked (read access only) + */ +#define IOMUXC_GPR_GPR19_LOCK_M7_APC_AC_R0_TOP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR19_LOCK_M7_APC_AC_R0_TOP_SHIFT)) & IOMUXC_GPR_GPR19_LOCK_M7_APC_AC_R0_TOP_MASK) +#define IOMUXC_GPR_GPR19_M7_APC_AC_R0_TOP_MASK (0xFFFFFFF8U) +#define IOMUXC_GPR_GPR19_M7_APC_AC_R0_TOP_SHIFT (3U) +#define IOMUXC_GPR_GPR19_M7_APC_AC_R0_TOP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR19_M7_APC_AC_R0_TOP_SHIFT)) & IOMUXC_GPR_GPR19_M7_APC_AC_R0_TOP_MASK) +/*! @} */ + +/*! @name GPR20 - GPR20 General Purpose Register */ +/*! @{ */ +#define IOMUXC_GPR_GPR20_LOCK_M7_APC_AC_R1_BOT_MASK (0x1U) +#define IOMUXC_GPR_GPR20_LOCK_M7_APC_AC_R1_BOT_SHIFT (0U) +/*! LOCK_M7_APC_AC_R1_BOT + * 0b0..Register field [31:1] is not locked + * 0b1..Register field [31:1] is locked (read access only) + */ +#define IOMUXC_GPR_GPR20_LOCK_M7_APC_AC_R1_BOT(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR20_LOCK_M7_APC_AC_R1_BOT_SHIFT)) & IOMUXC_GPR_GPR20_LOCK_M7_APC_AC_R1_BOT_MASK) +#define IOMUXC_GPR_GPR20_M7_APC_AC_R1_BOT_MASK (0xFFFFFFF8U) +#define IOMUXC_GPR_GPR20_M7_APC_AC_R1_BOT_SHIFT (3U) +#define IOMUXC_GPR_GPR20_M7_APC_AC_R1_BOT(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR20_M7_APC_AC_R1_BOT_SHIFT)) & IOMUXC_GPR_GPR20_M7_APC_AC_R1_BOT_MASK) +/*! @} */ + +/*! @name GPR21 - GPR21 General Purpose Register */ +/*! @{ */ +#define IOMUXC_GPR_GPR21_LOCK_M7_APC_AC_R1_TOP_MASK (0x1U) +#define IOMUXC_GPR_GPR21_LOCK_M7_APC_AC_R1_TOP_SHIFT (0U) +/*! LOCK_M7_APC_AC_R1_TOP + * 0b0..Register field [31:1] is not locked + * 0b1..Register field [31:1] is locked (read access only) + */ +#define IOMUXC_GPR_GPR21_LOCK_M7_APC_AC_R1_TOP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR21_LOCK_M7_APC_AC_R1_TOP_SHIFT)) & IOMUXC_GPR_GPR21_LOCK_M7_APC_AC_R1_TOP_MASK) +#define IOMUXC_GPR_GPR21_M7_APC_AC_R1_TOP_MASK (0xFFFFFFF8U) +#define IOMUXC_GPR_GPR21_M7_APC_AC_R1_TOP_SHIFT (3U) +#define IOMUXC_GPR_GPR21_M7_APC_AC_R1_TOP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR21_M7_APC_AC_R1_TOP_SHIFT)) & IOMUXC_GPR_GPR21_M7_APC_AC_R1_TOP_MASK) +/*! @} */ + +/*! @name GPR22 - GPR22 General Purpose Register */ +/*! @{ */ +#define IOMUXC_GPR_GPR22_LOCK_M7_APC_AC_R2_BOT_MASK (0x1U) +#define IOMUXC_GPR_GPR22_LOCK_M7_APC_AC_R2_BOT_SHIFT (0U) +/*! LOCK_M7_APC_AC_R2_BOT + * 0b0..Register field [31:1] is not locked + * 0b1..Register field [31:1] is locked (read access only) + */ +#define IOMUXC_GPR_GPR22_LOCK_M7_APC_AC_R2_BOT(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR22_LOCK_M7_APC_AC_R2_BOT_SHIFT)) & IOMUXC_GPR_GPR22_LOCK_M7_APC_AC_R2_BOT_MASK) +#define IOMUXC_GPR_GPR22_M7_APC_AC_R2_BOT_MASK (0xFFFFFFF8U) +#define IOMUXC_GPR_GPR22_M7_APC_AC_R2_BOT_SHIFT (3U) +#define IOMUXC_GPR_GPR22_M7_APC_AC_R2_BOT(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR22_M7_APC_AC_R2_BOT_SHIFT)) & IOMUXC_GPR_GPR22_M7_APC_AC_R2_BOT_MASK) +/*! @} */ + +/*! @name GPR23 - GPR23 General Purpose Register */ +/*! @{ */ +#define IOMUXC_GPR_GPR23_LOCK_M7_APC_AC_R2_TOP_MASK (0x1U) +#define IOMUXC_GPR_GPR23_LOCK_M7_APC_AC_R2_TOP_SHIFT (0U) +/*! LOCK_M7_APC_AC_R2_TOP + * 0b0..Register field [31:1] is not locked + * 0b1..Register field [31:1] is locked (read access only) + */ +#define IOMUXC_GPR_GPR23_LOCK_M7_APC_AC_R2_TOP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR23_LOCK_M7_APC_AC_R2_TOP_SHIFT)) & IOMUXC_GPR_GPR23_LOCK_M7_APC_AC_R2_TOP_MASK) +#define IOMUXC_GPR_GPR23_M7_APC_AC_R2_TOP_MASK (0xFFFFFFF8U) +#define IOMUXC_GPR_GPR23_M7_APC_AC_R2_TOP_SHIFT (3U) +#define IOMUXC_GPR_GPR23_M7_APC_AC_R2_TOP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR23_M7_APC_AC_R2_TOP_SHIFT)) & IOMUXC_GPR_GPR23_M7_APC_AC_R2_TOP_MASK) +/*! @} */ + +/*! @name GPR24 - GPR24 General Purpose Register */ +/*! @{ */ +#define IOMUXC_GPR_GPR24_LOCK_M7_APC_AC_R3_BOT_MASK (0x1U) +#define IOMUXC_GPR_GPR24_LOCK_M7_APC_AC_R3_BOT_SHIFT (0U) +/*! LOCK_M7_APC_AC_R3_BOT + * 0b0..Register field [31:1] is not locked + * 0b1..Register field [31:1] is locked (read access only) + */ +#define IOMUXC_GPR_GPR24_LOCK_M7_APC_AC_R3_BOT(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR24_LOCK_M7_APC_AC_R3_BOT_SHIFT)) & IOMUXC_GPR_GPR24_LOCK_M7_APC_AC_R3_BOT_MASK) +#define IOMUXC_GPR_GPR24_M7_APC_AC_R3_BOT_MASK (0xFFFFFFF8U) +#define IOMUXC_GPR_GPR24_M7_APC_AC_R3_BOT_SHIFT (3U) +#define IOMUXC_GPR_GPR24_M7_APC_AC_R3_BOT(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR24_M7_APC_AC_R3_BOT_SHIFT)) & IOMUXC_GPR_GPR24_M7_APC_AC_R3_BOT_MASK) +/*! @} */ + +/*! @name GPR25 - GPR25 General Purpose Register */ +/*! @{ */ +#define IOMUXC_GPR_GPR25_LOCK_M7_APC_AC_R3_TOP_MASK (0x1U) +#define IOMUXC_GPR_GPR25_LOCK_M7_APC_AC_R3_TOP_SHIFT (0U) +/*! LOCK_M7_APC_AC_R3_TOP + * 0b0..Register field [31:1] is not locked + * 0b1..Register field [31:1] is locked (read access only) + */ +#define IOMUXC_GPR_GPR25_LOCK_M7_APC_AC_R3_TOP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR25_LOCK_M7_APC_AC_R3_TOP_SHIFT)) & IOMUXC_GPR_GPR25_LOCK_M7_APC_AC_R3_TOP_MASK) +#define IOMUXC_GPR_GPR25_M7_APC_AC_R3_TOP_MASK (0xFFFFFFF8U) +#define IOMUXC_GPR_GPR25_M7_APC_AC_R3_TOP_SHIFT (3U) +#define IOMUXC_GPR_GPR25_M7_APC_AC_R3_TOP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR25_M7_APC_AC_R3_TOP_SHIFT)) & IOMUXC_GPR_GPR25_M7_APC_AC_R3_TOP_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group IOMUXC_GPR_Register_Masks */ + + +/* IOMUXC_GPR - Peripheral instance base addresses */ +/** Peripheral IOMUXC_GPR base address */ +#define IOMUXC_GPR_BASE (0x400AC000u) +/** Peripheral IOMUXC_GPR base pointer */ +#define IOMUXC_GPR ((IOMUXC_GPR_Type *)IOMUXC_GPR_BASE) +/** Array initializer of IOMUXC_GPR peripheral base addresses */ +#define IOMUXC_GPR_BASE_ADDRS { IOMUXC_GPR_BASE } +/** Array initializer of IOMUXC_GPR peripheral base pointers */ +#define IOMUXC_GPR_BASE_PTRS { IOMUXC_GPR } + +/*! + * @} + */ /* end of group IOMUXC_GPR_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- IOMUXC_SNVS Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup IOMUXC_SNVS_Peripheral_Access_Layer IOMUXC_SNVS Peripheral Access Layer + * @{ + */ + +/** IOMUXC_SNVS - Register Layout Typedef */ +typedef struct { + __IO uint32_t SW_MUX_CTL_PAD_WAKEUP; /**< SW_MUX_CTL_PAD_WAKEUP SW MUX Control Register, offset: 0x0 */ + __IO uint32_t SW_MUX_CTL_PAD_PMIC_ON_REQ; /**< SW_MUX_CTL_PAD_PMIC_ON_REQ SW MUX Control Register, offset: 0x4 */ + __IO uint32_t SW_MUX_CTL_PAD_PMIC_STBY_REQ; /**< SW_MUX_CTL_PAD_PMIC_STBY_REQ SW MUX Control Register, offset: 0x8 */ + __IO uint32_t SW_PAD_CTL_PAD_TEST_MODE; /**< SW_PAD_CTL_PAD_TEST_MODE SW PAD Control Register, offset: 0xC */ + __IO uint32_t SW_PAD_CTL_PAD_POR_B; /**< SW_PAD_CTL_PAD_POR_B SW PAD Control Register, offset: 0x10 */ + __IO uint32_t SW_PAD_CTL_PAD_ONOFF; /**< SW_PAD_CTL_PAD_ONOFF SW PAD Control Register, offset: 0x14 */ + __IO uint32_t SW_PAD_CTL_PAD_WAKEUP; /**< SW_PAD_CTL_PAD_WAKEUP SW PAD Control Register, offset: 0x18 */ + __IO uint32_t SW_PAD_CTL_PAD_PMIC_ON_REQ; /**< SW_PAD_CTL_PAD_PMIC_ON_REQ SW PAD Control Register, offset: 0x1C */ + __IO uint32_t SW_PAD_CTL_PAD_PMIC_STBY_REQ; /**< SW_PAD_CTL_PAD_PMIC_STBY_REQ SW PAD Control Register, offset: 0x20 */ +} IOMUXC_SNVS_Type; + +/* ---------------------------------------------------------------------------- + -- IOMUXC_SNVS Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup IOMUXC_SNVS_Register_Masks IOMUXC_SNVS Register Masks + * @{ + */ + +/*! @name SW_MUX_CTL_PAD_WAKEUP - SW_MUX_CTL_PAD_WAKEUP SW MUX Control Register */ +/*! @{ */ +#define IOMUXC_SNVS_SW_MUX_CTL_PAD_WAKEUP_MUX_MODE_MASK (0x7U) +#define IOMUXC_SNVS_SW_MUX_CTL_PAD_WAKEUP_MUX_MODE_SHIFT (0U) +/*! MUX_MODE - MUX Mode Select Field. + * 0b101..Select mux mode: ALT5 mux port: GPIO5_IO00 of instance: gpio5 + * 0b111..Select mux mode: ALT7 mux port: NMI_GLUE_NMI of instance: nmi_glue + */ +#define IOMUXC_SNVS_SW_MUX_CTL_PAD_WAKEUP_MUX_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_MUX_CTL_PAD_WAKEUP_MUX_MODE_SHIFT)) & IOMUXC_SNVS_SW_MUX_CTL_PAD_WAKEUP_MUX_MODE_MASK) +#define IOMUXC_SNVS_SW_MUX_CTL_PAD_WAKEUP_SION_MASK (0x10U) +#define IOMUXC_SNVS_SW_MUX_CTL_PAD_WAKEUP_SION_SHIFT (4U) +/*! SION - Software Input On Field. + * 0b1..Force input path of pad WAKEUP + * 0b0..Input Path is determined by functionality + */ +#define IOMUXC_SNVS_SW_MUX_CTL_PAD_WAKEUP_SION(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_MUX_CTL_PAD_WAKEUP_SION_SHIFT)) & IOMUXC_SNVS_SW_MUX_CTL_PAD_WAKEUP_SION_MASK) +/*! @} */ + +/*! @name SW_MUX_CTL_PAD_PMIC_ON_REQ - SW_MUX_CTL_PAD_PMIC_ON_REQ SW MUX Control Register */ +/*! @{ */ +#define IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_ON_REQ_MUX_MODE_MASK (0x7U) +#define IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_ON_REQ_MUX_MODE_SHIFT (0U) +/*! MUX_MODE - MUX Mode Select Field. + * 0b000..Select mux mode: ALT0 mux port: SNVS_LP_PMIC_ON_REQ of instance: snvs_lp + * 0b101..Select mux mode: ALT5 mux port: GPIO5_IO01 of instance: gpio5 + */ +#define IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_ON_REQ_MUX_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_ON_REQ_MUX_MODE_SHIFT)) & IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_ON_REQ_MUX_MODE_MASK) +#define IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_ON_REQ_SION_MASK (0x10U) +#define IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_ON_REQ_SION_SHIFT (4U) +/*! SION - Software Input On Field. + * 0b1..Force input path of pad PMIC_ON_REQ + * 0b0..Input Path is determined by functionality + */ +#define IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_ON_REQ_SION(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_ON_REQ_SION_SHIFT)) & IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_ON_REQ_SION_MASK) +/*! @} */ + +/*! @name SW_MUX_CTL_PAD_PMIC_STBY_REQ - SW_MUX_CTL_PAD_PMIC_STBY_REQ SW MUX Control Register */ +/*! @{ */ +#define IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_STBY_REQ_MUX_MODE_MASK (0x7U) +#define IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_STBY_REQ_MUX_MODE_SHIFT (0U) +/*! MUX_MODE - MUX Mode Select Field. + * 0b000..Select mux mode: ALT0 mux port: CCM_PMIC_VSTBY_REQ of instance: ccm + * 0b101..Select mux mode: ALT5 mux port: GPIO5_IO02 of instance: gpio5 + */ +#define IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_STBY_REQ_MUX_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_STBY_REQ_MUX_MODE_SHIFT)) & IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_STBY_REQ_MUX_MODE_MASK) +#define IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_STBY_REQ_SION_MASK (0x10U) +#define IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_STBY_REQ_SION_SHIFT (4U) +/*! SION - Software Input On Field. + * 0b1..Force input path of pad PMIC_STBY_REQ + * 0b0..Input Path is determined by functionality + */ +#define IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_STBY_REQ_SION(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_STBY_REQ_SION_SHIFT)) & IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_STBY_REQ_SION_MASK) +/*! @} */ + +/*! @name SW_PAD_CTL_PAD_TEST_MODE - SW_PAD_CTL_PAD_TEST_MODE SW PAD Control Register */ +/*! @{ */ +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_SRE_MASK (0x1U) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_SRE_SHIFT (0U) +/*! SRE - Slew Rate Field + * 0b0..Slow Slew Rate + * 0b1..Fast Slew Rate + */ +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_SRE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_SRE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_SRE_MASK) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_DSE_MASK (0x38U) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_DSE_SHIFT (3U) +/*! DSE - Drive Strength Field + * 0b000..output driver disabled; + * 0b001..R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + * 0b010..R0/2 + * 0b011..R0/3 + * 0b100..R0/4 + * 0b101..R0/5 + * 0b110..R0/6 + * 0b111..R0/7 + */ +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_DSE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_DSE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_DSE_MASK) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_SPEED_MASK (0xC0U) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_SPEED_SHIFT (6U) +/*! SPEED - Speed Field + * 0b10..medium(100MHz) + */ +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_SPEED(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_SPEED_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_SPEED_MASK) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_ODE_MASK (0x800U) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_ODE_SHIFT (11U) +/*! ODE - Open Drain Enable Field + * 0b0..Open Drain Disabled + * 0b1..Open Drain Enabled + */ +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_ODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_ODE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_ODE_MASK) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_PKE_MASK (0x1000U) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_PKE_SHIFT (12U) +/*! PKE - Pull / Keep Enable Field + * 0b0..Pull/Keeper Disabled + * 0b1..Pull/Keeper Enabled + */ +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_PKE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_PKE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_PKE_MASK) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_PUE_MASK (0x2000U) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_PUE_SHIFT (13U) +/*! PUE - Pull / Keep Select Field + * 0b0..Keeper + * 0b1..Pull + */ +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_PUE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_PUE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_PUE_MASK) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_PUS_MASK (0xC000U) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_PUS_SHIFT (14U) +/*! PUS - Pull Up / Down Config. Field + * 0b00..100K Ohm Pull Down + * 0b01..47K Ohm Pull Up + * 0b10..100K Ohm Pull Up + * 0b11..22K Ohm Pull Up + */ +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_PUS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_PUS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_PUS_MASK) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_HYS_MASK (0x10000U) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_HYS_SHIFT (16U) +/*! HYS - Hyst. Enable Field + * 0b0..Hysteresis Disabled + * 0b1..Hysteresis Enabled + */ +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_HYS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_HYS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_HYS_MASK) +/*! @} */ + +/*! @name SW_PAD_CTL_PAD_POR_B - SW_PAD_CTL_PAD_POR_B SW PAD Control Register */ +/*! @{ */ +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_SRE_MASK (0x1U) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_SRE_SHIFT (0U) +/*! SRE - Slew Rate Field + * 0b0..Slow Slew Rate + * 0b1..Fast Slew Rate + */ +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_SRE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_SRE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_SRE_MASK) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_DSE_MASK (0x38U) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_DSE_SHIFT (3U) +/*! DSE - Drive Strength Field + * 0b000..output driver disabled; + * 0b001..R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + * 0b010..R0/2 + * 0b011..R0/3 + * 0b100..R0/4 + * 0b101..R0/5 + * 0b110..R0/6 + * 0b111..R0/7 + */ +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_DSE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_DSE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_DSE_MASK) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_SPEED_MASK (0xC0U) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_SPEED_SHIFT (6U) +/*! SPEED - Speed Field + * 0b10..medium(100MHz) + */ +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_SPEED(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_SPEED_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_SPEED_MASK) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_ODE_MASK (0x800U) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_ODE_SHIFT (11U) +/*! ODE - Open Drain Enable Field + * 0b0..Open Drain Disabled + * 0b1..Open Drain Enabled + */ +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_ODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_ODE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_ODE_MASK) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_PKE_MASK (0x1000U) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_PKE_SHIFT (12U) +/*! PKE - Pull / Keep Enable Field + * 0b0..Pull/Keeper Disabled + * 0b1..Pull/Keeper Enabled + */ +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_PKE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_PKE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_PKE_MASK) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_PUE_MASK (0x2000U) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_PUE_SHIFT (13U) +/*! PUE - Pull / Keep Select Field + * 0b0..Keeper + * 0b1..Pull + */ +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_PUE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_PUE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_PUE_MASK) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_PUS_MASK (0xC000U) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_PUS_SHIFT (14U) +/*! PUS - Pull Up / Down Config. Field + * 0b00..100K Ohm Pull Down + * 0b01..47K Ohm Pull Up + * 0b10..100K Ohm Pull Up + * 0b11..22K Ohm Pull Up + */ +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_PUS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_PUS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_PUS_MASK) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_HYS_MASK (0x10000U) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_HYS_SHIFT (16U) +/*! HYS - Hyst. Enable Field + * 0b0..Hysteresis Disabled + * 0b1..Hysteresis Enabled + */ +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_HYS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_HYS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_HYS_MASK) +/*! @} */ + +/*! @name SW_PAD_CTL_PAD_ONOFF - SW_PAD_CTL_PAD_ONOFF SW PAD Control Register */ +/*! @{ */ +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_SRE_MASK (0x1U) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_SRE_SHIFT (0U) +/*! SRE - Slew Rate Field + * 0b0..Slow Slew Rate + * 0b1..Fast Slew Rate + */ +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_SRE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_SRE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_SRE_MASK) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_DSE_MASK (0x38U) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_DSE_SHIFT (3U) +/*! DSE - Drive Strength Field + * 0b000..output driver disabled; + * 0b001..R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + * 0b010..R0/2 + * 0b011..R0/3 + * 0b100..R0/4 + * 0b101..R0/5 + * 0b110..R0/6 + * 0b111..R0/7 + */ +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_DSE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_DSE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_DSE_MASK) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_SPEED_MASK (0xC0U) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_SPEED_SHIFT (6U) +/*! SPEED - Speed Field + * 0b10..medium(100MHz) + */ +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_SPEED(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_SPEED_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_SPEED_MASK) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_ODE_MASK (0x800U) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_ODE_SHIFT (11U) +/*! ODE - Open Drain Enable Field + * 0b0..Open Drain Disabled + * 0b1..Open Drain Enabled + */ +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_ODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_ODE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_ODE_MASK) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_PKE_MASK (0x1000U) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_PKE_SHIFT (12U) +/*! PKE - Pull / Keep Enable Field + * 0b0..Pull/Keeper Disabled + * 0b1..Pull/Keeper Enabled + */ +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_PKE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_PKE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_PKE_MASK) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_PUE_MASK (0x2000U) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_PUE_SHIFT (13U) +/*! PUE - Pull / Keep Select Field + * 0b0..Keeper + * 0b1..Pull + */ +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_PUE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_PUE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_PUE_MASK) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_PUS_MASK (0xC000U) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_PUS_SHIFT (14U) +/*! PUS - Pull Up / Down Config. Field + * 0b00..100K Ohm Pull Down + * 0b01..47K Ohm Pull Up + * 0b10..100K Ohm Pull Up + * 0b11..22K Ohm Pull Up + */ +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_PUS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_PUS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_PUS_MASK) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_HYS_MASK (0x10000U) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_HYS_SHIFT (16U) +/*! HYS - Hyst. Enable Field + * 0b0..Hysteresis Disabled + * 0b1..Hysteresis Enabled + */ +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_HYS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_HYS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_HYS_MASK) +/*! @} */ + +/*! @name SW_PAD_CTL_PAD_WAKEUP - SW_PAD_CTL_PAD_WAKEUP SW PAD Control Register */ +/*! @{ */ +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_SRE_MASK (0x1U) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_SRE_SHIFT (0U) +/*! SRE - Slew Rate Field + * 0b0..Slow Slew Rate + * 0b1..Fast Slew Rate + */ +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_SRE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_SRE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_SRE_MASK) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_DSE_MASK (0x38U) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_DSE_SHIFT (3U) +/*! DSE - Drive Strength Field + * 0b000..output driver disabled; + * 0b001..R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + * 0b010..R0/2 + * 0b011..R0/3 + * 0b100..R0/4 + * 0b101..R0/5 + * 0b110..R0/6 + * 0b111..R0/7 + */ +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_DSE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_DSE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_DSE_MASK) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_SPEED_MASK (0xC0U) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_SPEED_SHIFT (6U) +/*! SPEED - Speed Field + * 0b10..medium(100MHz) + */ +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_SPEED(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_SPEED_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_SPEED_MASK) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_ODE_MASK (0x800U) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_ODE_SHIFT (11U) +/*! ODE - Open Drain Enable Field + * 0b0..Open Drain Disabled + * 0b1..Open Drain Enabled + */ +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_ODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_ODE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_ODE_MASK) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_PKE_MASK (0x1000U) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_PKE_SHIFT (12U) +/*! PKE - Pull / Keep Enable Field + * 0b0..Pull/Keeper Disabled + * 0b1..Pull/Keeper Enabled + */ +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_PKE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_PKE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_PKE_MASK) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_PUE_MASK (0x2000U) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_PUE_SHIFT (13U) +/*! PUE - Pull / Keep Select Field + * 0b0..Keeper + * 0b1..Pull + */ +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_PUE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_PUE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_PUE_MASK) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_PUS_MASK (0xC000U) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_PUS_SHIFT (14U) +/*! PUS - Pull Up / Down Config. Field + * 0b00..100K Ohm Pull Down + * 0b01..47K Ohm Pull Up + * 0b10..100K Ohm Pull Up + * 0b11..22K Ohm Pull Up + */ +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_PUS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_PUS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_PUS_MASK) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_HYS_MASK (0x10000U) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_HYS_SHIFT (16U) +/*! HYS - Hyst. Enable Field + * 0b0..Hysteresis Disabled + * 0b1..Hysteresis Enabled + */ +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_HYS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_HYS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_HYS_MASK) +/*! @} */ + +/*! @name SW_PAD_CTL_PAD_PMIC_ON_REQ - SW_PAD_CTL_PAD_PMIC_ON_REQ SW PAD Control Register */ +/*! @{ */ +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_SRE_MASK (0x1U) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_SRE_SHIFT (0U) +/*! SRE - Slew Rate Field + * 0b0..Slow Slew Rate + * 0b1..Fast Slew Rate + */ +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_SRE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_SRE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_SRE_MASK) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_DSE_MASK (0x38U) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_DSE_SHIFT (3U) +/*! DSE - Drive Strength Field + * 0b000..output driver disabled; + * 0b001..R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + * 0b010..R0/2 + * 0b011..R0/3 + * 0b100..R0/4 + * 0b101..R0/5 + * 0b110..R0/6 + * 0b111..R0/7 + */ +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_DSE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_DSE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_DSE_MASK) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_SPEED_MASK (0xC0U) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_SPEED_SHIFT (6U) +/*! SPEED - Speed Field + * 0b10..medium(100MHz) + */ +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_SPEED(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_SPEED_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_SPEED_MASK) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_ODE_MASK (0x800U) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_ODE_SHIFT (11U) +/*! ODE - Open Drain Enable Field + * 0b0..Open Drain Disabled + * 0b1..Open Drain Enabled + */ +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_ODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_ODE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_ODE_MASK) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_PKE_MASK (0x1000U) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_PKE_SHIFT (12U) +/*! PKE - Pull / Keep Enable Field + * 0b0..Pull/Keeper Disabled + * 0b1..Pull/Keeper Enabled + */ +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_PKE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_PKE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_PKE_MASK) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_PUE_MASK (0x2000U) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_PUE_SHIFT (13U) +/*! PUE - Pull / Keep Select Field + * 0b0..Keeper + * 0b1..Pull + */ +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_PUE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_PUE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_PUE_MASK) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_PUS_MASK (0xC000U) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_PUS_SHIFT (14U) +/*! PUS - Pull Up / Down Config. Field + * 0b00..100K Ohm Pull Down + * 0b01..47K Ohm Pull Up + * 0b10..100K Ohm Pull Up + * 0b11..22K Ohm Pull Up + */ +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_PUS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_PUS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_PUS_MASK) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_HYS_MASK (0x10000U) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_HYS_SHIFT (16U) +/*! HYS - Hyst. Enable Field + * 0b0..Hysteresis Disabled + * 0b1..Hysteresis Enabled + */ +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_HYS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_HYS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_HYS_MASK) +/*! @} */ + +/*! @name SW_PAD_CTL_PAD_PMIC_STBY_REQ - SW_PAD_CTL_PAD_PMIC_STBY_REQ SW PAD Control Register */ +/*! @{ */ +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_SRE_MASK (0x1U) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_SRE_SHIFT (0U) +/*! SRE - Slew Rate Field + * 0b0..Slow Slew Rate + * 0b1..Fast Slew Rate + */ +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_SRE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_SRE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_SRE_MASK) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_DSE_MASK (0x38U) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_DSE_SHIFT (3U) +/*! DSE - Drive Strength Field + * 0b000..output driver disabled; + * 0b001..R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + * 0b010..R0/2 + * 0b011..R0/3 + * 0b100..R0/4 + * 0b101..R0/5 + * 0b110..R0/6 + * 0b111..R0/7 + */ +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_DSE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_DSE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_DSE_MASK) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_SPEED_MASK (0xC0U) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_SPEED_SHIFT (6U) +/*! SPEED - Speed Field + * 0b10..medium(100MHz) + */ +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_SPEED(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_SPEED_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_SPEED_MASK) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_ODE_MASK (0x800U) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_ODE_SHIFT (11U) +/*! ODE - Open Drain Enable Field + * 0b0..Open Drain Disabled + * 0b1..Open Drain Enabled + */ +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_ODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_ODE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_ODE_MASK) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_PKE_MASK (0x1000U) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_PKE_SHIFT (12U) +/*! PKE - Pull / Keep Enable Field + * 0b0..Pull/Keeper Disabled + * 0b1..Pull/Keeper Enabled + */ +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_PKE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_PKE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_PKE_MASK) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_PUE_MASK (0x2000U) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_PUE_SHIFT (13U) +/*! PUE - Pull / Keep Select Field + * 0b0..Keeper + * 0b1..Pull + */ +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_PUE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_PUE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_PUE_MASK) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_PUS_MASK (0xC000U) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_PUS_SHIFT (14U) +/*! PUS - Pull Up / Down Config. Field + * 0b00..100K Ohm Pull Down + * 0b01..47K Ohm Pull Up + * 0b10..100K Ohm Pull Up + * 0b11..22K Ohm Pull Up + */ +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_PUS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_PUS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_PUS_MASK) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_HYS_MASK (0x10000U) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_HYS_SHIFT (16U) +/*! HYS - Hyst. Enable Field + * 0b0..Hysteresis Disabled + * 0b1..Hysteresis Enabled + */ +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_HYS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_HYS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_HYS_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group IOMUXC_SNVS_Register_Masks */ + + +/* IOMUXC_SNVS - Peripheral instance base addresses */ +/** Peripheral IOMUXC_SNVS base address */ +#define IOMUXC_SNVS_BASE (0x400A8000u) +/** Peripheral IOMUXC_SNVS base pointer */ +#define IOMUXC_SNVS ((IOMUXC_SNVS_Type *)IOMUXC_SNVS_BASE) +/** Array initializer of IOMUXC_SNVS peripheral base addresses */ +#define IOMUXC_SNVS_BASE_ADDRS { IOMUXC_SNVS_BASE } +/** Array initializer of IOMUXC_SNVS peripheral base pointers */ +#define IOMUXC_SNVS_BASE_PTRS { IOMUXC_SNVS } + +/*! + * @} + */ /* end of group IOMUXC_SNVS_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- IOMUXC_SNVS_GPR Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup IOMUXC_SNVS_GPR_Peripheral_Access_Layer IOMUXC_SNVS_GPR Peripheral Access Layer + * @{ + */ + +/** IOMUXC_SNVS_GPR - Register Layout Typedef */ +typedef struct { + uint32_t GPR0; /**< GPR0 General Purpose Register, offset: 0x0 */ + uint32_t GPR1; /**< GPR1 General Purpose Register, offset: 0x4 */ + uint32_t GPR2; /**< GPR2 General Purpose Register, offset: 0x8 */ + __IO uint32_t GPR3; /**< GPR3 General Purpose Register, offset: 0xC */ +} IOMUXC_SNVS_GPR_Type; + +/* ---------------------------------------------------------------------------- + -- IOMUXC_SNVS_GPR Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup IOMUXC_SNVS_GPR_Register_Masks IOMUXC_SNVS_GPR Register Masks + * @{ + */ + +/*! @name GPR3 - GPR3 General Purpose Register */ +/*! @{ */ +#define IOMUXC_SNVS_GPR_GPR3_LPSR_MODE_ENABLE_MASK (0x1U) +#define IOMUXC_SNVS_GPR_GPR3_LPSR_MODE_ENABLE_SHIFT (0U) +#define IOMUXC_SNVS_GPR_GPR3_LPSR_MODE_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR3_LPSR_MODE_ENABLE_SHIFT)) & IOMUXC_SNVS_GPR_GPR3_LPSR_MODE_ENABLE_MASK) +#define IOMUXC_SNVS_GPR_GPR3_DCDC_STATUS_CAPT_CLR_MASK (0x2U) +#define IOMUXC_SNVS_GPR_GPR3_DCDC_STATUS_CAPT_CLR_SHIFT (1U) +#define IOMUXC_SNVS_GPR_GPR3_DCDC_STATUS_CAPT_CLR(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR3_DCDC_STATUS_CAPT_CLR_SHIFT)) & IOMUXC_SNVS_GPR_GPR3_DCDC_STATUS_CAPT_CLR_MASK) +#define IOMUXC_SNVS_GPR_GPR3_POR_PULL_TYPE_MASK (0xCU) +#define IOMUXC_SNVS_GPR_GPR3_POR_PULL_TYPE_SHIFT (2U) +#define IOMUXC_SNVS_GPR_GPR3_POR_PULL_TYPE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR3_POR_PULL_TYPE_SHIFT)) & IOMUXC_SNVS_GPR_GPR3_POR_PULL_TYPE_MASK) +#define IOMUXC_SNVS_GPR_GPR3_DCDC_IN_LOW_VOL_MASK (0x10000U) +#define IOMUXC_SNVS_GPR_GPR3_DCDC_IN_LOW_VOL_SHIFT (16U) +#define IOMUXC_SNVS_GPR_GPR3_DCDC_IN_LOW_VOL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR3_DCDC_IN_LOW_VOL_SHIFT)) & IOMUXC_SNVS_GPR_GPR3_DCDC_IN_LOW_VOL_MASK) +#define IOMUXC_SNVS_GPR_GPR3_DCDC_OVER_CUR_MASK (0x20000U) +#define IOMUXC_SNVS_GPR_GPR3_DCDC_OVER_CUR_SHIFT (17U) +#define IOMUXC_SNVS_GPR_GPR3_DCDC_OVER_CUR(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR3_DCDC_OVER_CUR_SHIFT)) & IOMUXC_SNVS_GPR_GPR3_DCDC_OVER_CUR_MASK) +#define IOMUXC_SNVS_GPR_GPR3_DCDC_OVER_VOL_MASK (0x40000U) +#define IOMUXC_SNVS_GPR_GPR3_DCDC_OVER_VOL_SHIFT (18U) +#define IOMUXC_SNVS_GPR_GPR3_DCDC_OVER_VOL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR3_DCDC_OVER_VOL_SHIFT)) & IOMUXC_SNVS_GPR_GPR3_DCDC_OVER_VOL_MASK) +#define IOMUXC_SNVS_GPR_GPR3_DCDC_STS_DC_OK_MASK (0x80000U) +#define IOMUXC_SNVS_GPR_GPR3_DCDC_STS_DC_OK_SHIFT (19U) +#define IOMUXC_SNVS_GPR_GPR3_DCDC_STS_DC_OK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR3_DCDC_STS_DC_OK_SHIFT)) & IOMUXC_SNVS_GPR_GPR3_DCDC_STS_DC_OK_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group IOMUXC_SNVS_GPR_Register_Masks */ + + +/* IOMUXC_SNVS_GPR - Peripheral instance base addresses */ +/** Peripheral IOMUXC_SNVS_GPR base address */ +#define IOMUXC_SNVS_GPR_BASE (0x400A4000u) +/** Peripheral IOMUXC_SNVS_GPR base pointer */ +#define IOMUXC_SNVS_GPR ((IOMUXC_SNVS_GPR_Type *)IOMUXC_SNVS_GPR_BASE) +/** Array initializer of IOMUXC_SNVS_GPR peripheral base addresses */ +#define IOMUXC_SNVS_GPR_BASE_ADDRS { IOMUXC_SNVS_GPR_BASE } +/** Array initializer of IOMUXC_SNVS_GPR peripheral base pointers */ +#define IOMUXC_SNVS_GPR_BASE_PTRS { IOMUXC_SNVS_GPR } + +/*! + * @} + */ /* end of group IOMUXC_SNVS_GPR_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- KPP Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup KPP_Peripheral_Access_Layer KPP Peripheral Access Layer + * @{ + */ + +/** KPP - Register Layout Typedef */ +typedef struct { + __IO uint16_t KPCR; /**< Keypad Control Register, offset: 0x0 */ + __IO uint16_t KPSR; /**< Keypad Status Register, offset: 0x2 */ + __IO uint16_t KDDR; /**< Keypad Data Direction Register, offset: 0x4 */ + __IO uint16_t KPDR; /**< Keypad Data Register, offset: 0x6 */ +} KPP_Type; + +/* ---------------------------------------------------------------------------- + -- KPP Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup KPP_Register_Masks KPP Register Masks + * @{ + */ + +/*! @name KPCR - Keypad Control Register */ +/*! @{ */ +#define KPP_KPCR_KRE_MASK (0xFFU) +#define KPP_KPCR_KRE_SHIFT (0U) +/*! KRE + * 0b00000000..Row is not included in the keypad key press detect. + * 0b00000001..Row is included in the keypad key press detect. + */ +#define KPP_KPCR_KRE(x) (((uint16_t)(((uint16_t)(x)) << KPP_KPCR_KRE_SHIFT)) & KPP_KPCR_KRE_MASK) +#define KPP_KPCR_KCO_MASK (0xFF00U) +#define KPP_KPCR_KCO_SHIFT (8U) +/*! KCO + * 0b00000000..Column strobe output is totem pole drive. + * 0b00000001..Column strobe output is open drain. + */ +#define KPP_KPCR_KCO(x) (((uint16_t)(((uint16_t)(x)) << KPP_KPCR_KCO_SHIFT)) & KPP_KPCR_KCO_MASK) +/*! @} */ + +/*! @name KPSR - Keypad Status Register */ +/*! @{ */ +#define KPP_KPSR_KPKD_MASK (0x1U) +#define KPP_KPSR_KPKD_SHIFT (0U) +/*! KPKD + * 0b0..No key presses detected + * 0b1..A key has been depressed + */ +#define KPP_KPSR_KPKD(x) (((uint16_t)(((uint16_t)(x)) << KPP_KPSR_KPKD_SHIFT)) & KPP_KPSR_KPKD_MASK) +#define KPP_KPSR_KPKR_MASK (0x2U) +#define KPP_KPSR_KPKR_SHIFT (1U) +/*! KPKR + * 0b0..No key release detected + * 0b1..All keys have been released + */ +#define KPP_KPSR_KPKR(x) (((uint16_t)(((uint16_t)(x)) << KPP_KPSR_KPKR_SHIFT)) & KPP_KPSR_KPKR_MASK) +#define KPP_KPSR_KDSC_MASK (0x4U) +#define KPP_KPSR_KDSC_SHIFT (2U) +/*! KDSC + * 0b0..No effect + * 0b1..Set bits that clear the keypad depress synchronizer chain + */ +#define KPP_KPSR_KDSC(x) (((uint16_t)(((uint16_t)(x)) << KPP_KPSR_KDSC_SHIFT)) & KPP_KPSR_KDSC_MASK) +#define KPP_KPSR_KRSS_MASK (0x8U) +#define KPP_KPSR_KRSS_SHIFT (3U) +/*! KRSS + * 0b0..No effect + * 0b1..Set bits which sets keypad release synchronizer chain + */ +#define KPP_KPSR_KRSS(x) (((uint16_t)(((uint16_t)(x)) << KPP_KPSR_KRSS_SHIFT)) & KPP_KPSR_KRSS_MASK) +#define KPP_KPSR_KDIE_MASK (0x100U) +#define KPP_KPSR_KDIE_SHIFT (8U) +/*! KDIE + * 0b0..No interrupt request is generated when KPKD is set. + * 0b1..An interrupt request is generated when KPKD is set. + */ +#define KPP_KPSR_KDIE(x) (((uint16_t)(((uint16_t)(x)) << KPP_KPSR_KDIE_SHIFT)) & KPP_KPSR_KDIE_MASK) +#define KPP_KPSR_KRIE_MASK (0x200U) +#define KPP_KPSR_KRIE_SHIFT (9U) +/*! KRIE + * 0b0..No interrupt request is generated when KPKR is set. + * 0b1..An interrupt request is generated when KPKR is set. + */ +#define KPP_KPSR_KRIE(x) (((uint16_t)(((uint16_t)(x)) << KPP_KPSR_KRIE_SHIFT)) & KPP_KPSR_KRIE_MASK) +/*! @} */ + +/*! @name KDDR - Keypad Data Direction Register */ +/*! @{ */ +#define KPP_KDDR_KRDD_MASK (0xFFU) +#define KPP_KDDR_KRDD_SHIFT (0U) +/*! KRDD + * 0b00000000..ROWn pin configured as an input. + * 0b00000001..ROWn pin configured as an output. + */ +#define KPP_KDDR_KRDD(x) (((uint16_t)(((uint16_t)(x)) << KPP_KDDR_KRDD_SHIFT)) & KPP_KDDR_KRDD_MASK) +#define KPP_KDDR_KCDD_MASK (0xFF00U) +#define KPP_KDDR_KCDD_SHIFT (8U) +/*! KCDD + * 0b00000000..COLn pin is configured as an input. + * 0b00000001..COLn pin is configured as an output. + */ +#define KPP_KDDR_KCDD(x) (((uint16_t)(((uint16_t)(x)) << KPP_KDDR_KCDD_SHIFT)) & KPP_KDDR_KCDD_MASK) +/*! @} */ + +/*! @name KPDR - Keypad Data Register */ +/*! @{ */ +#define KPP_KPDR_KRD_MASK (0xFFU) +#define KPP_KPDR_KRD_SHIFT (0U) +#define KPP_KPDR_KRD(x) (((uint16_t)(((uint16_t)(x)) << KPP_KPDR_KRD_SHIFT)) & KPP_KPDR_KRD_MASK) +#define KPP_KPDR_KCD_MASK (0xFF00U) +#define KPP_KPDR_KCD_SHIFT (8U) +#define KPP_KPDR_KCD(x) (((uint16_t)(((uint16_t)(x)) << KPP_KPDR_KCD_SHIFT)) & KPP_KPDR_KCD_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group KPP_Register_Masks */ + + +/* KPP - Peripheral instance base addresses */ +/** Peripheral KPP base address */ +#define KPP_BASE (0x401FC000u) +/** Peripheral KPP base pointer */ +#define KPP ((KPP_Type *)KPP_BASE) +/** Array initializer of KPP peripheral base addresses */ +#define KPP_BASE_ADDRS { KPP_BASE } +/** Array initializer of KPP peripheral base pointers */ +#define KPP_BASE_PTRS { KPP } +/** Interrupt vectors for the KPP peripheral type */ +#define KPP_IRQS { KPP_IRQn } + +/*! + * @} + */ /* end of group KPP_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- LCDIF Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup LCDIF_Peripheral_Access_Layer LCDIF Peripheral Access Layer + * @{ + */ + +/** LCDIF - Register Layout Typedef */ +typedef struct { + __IO uint32_t CTRL; /**< LCDIF General Control Register, offset: 0x0 */ + __IO uint32_t CTRL_SET; /**< LCDIF General Control Register, offset: 0x4 */ + __IO uint32_t CTRL_CLR; /**< LCDIF General Control Register, offset: 0x8 */ + __IO uint32_t CTRL_TOG; /**< LCDIF General Control Register, offset: 0xC */ + __IO uint32_t CTRL1; /**< LCDIF General Control1 Register, offset: 0x10 */ + __IO uint32_t CTRL1_SET; /**< LCDIF General Control1 Register, offset: 0x14 */ + __IO uint32_t CTRL1_CLR; /**< LCDIF General Control1 Register, offset: 0x18 */ + __IO uint32_t CTRL1_TOG; /**< LCDIF General Control1 Register, offset: 0x1C */ + __IO uint32_t CTRL2; /**< LCDIF General Control2 Register, offset: 0x20 */ + __IO uint32_t CTRL2_SET; /**< LCDIF General Control2 Register, offset: 0x24 */ + __IO uint32_t CTRL2_CLR; /**< LCDIF General Control2 Register, offset: 0x28 */ + __IO uint32_t CTRL2_TOG; /**< LCDIF General Control2 Register, offset: 0x2C */ + __IO uint32_t TRANSFER_COUNT; /**< LCDIF Horizontal and Vertical Valid Data Count Register, offset: 0x30 */ + uint8_t RESERVED_0[12]; + __IO uint32_t CUR_BUF; /**< LCD Interface Current Buffer Address Register, offset: 0x40 */ + uint8_t RESERVED_1[12]; + __IO uint32_t NEXT_BUF; /**< LCD Interface Next Buffer Address Register, offset: 0x50 */ + uint8_t RESERVED_2[28]; + __IO uint32_t VDCTRL0; /**< LCDIF VSYNC Mode and Dotclk Mode Control Register0, offset: 0x70 */ + __IO uint32_t VDCTRL0_SET; /**< LCDIF VSYNC Mode and Dotclk Mode Control Register0, offset: 0x74 */ + __IO uint32_t VDCTRL0_CLR; /**< LCDIF VSYNC Mode and Dotclk Mode Control Register0, offset: 0x78 */ + __IO uint32_t VDCTRL0_TOG; /**< LCDIF VSYNC Mode and Dotclk Mode Control Register0, offset: 0x7C */ + __IO uint32_t VDCTRL1; /**< LCDIF VSYNC Mode and Dotclk Mode Control Register1, offset: 0x80 */ + uint8_t RESERVED_3[12]; + __IO uint32_t VDCTRL2; /**< LCDIF VSYNC Mode and Dotclk Mode Control Register2, offset: 0x90 */ + uint8_t RESERVED_4[12]; + __IO uint32_t VDCTRL3; /**< LCDIF VSYNC Mode and Dotclk Mode Control Register3, offset: 0xA0 */ + uint8_t RESERVED_5[12]; + __IO uint32_t VDCTRL4; /**< LCDIF VSYNC Mode and Dotclk Mode Control Register4, offset: 0xB0 */ + uint8_t RESERVED_6[220]; + __IO uint32_t BM_ERROR_STAT; /**< Bus Master Error Status Register, offset: 0x190 */ + uint8_t RESERVED_7[12]; + __IO uint32_t CRC_STAT; /**< CRC Status Register, offset: 0x1A0 */ + uint8_t RESERVED_8[12]; + __I uint32_t STAT; /**< LCD Interface Status Register, offset: 0x1B0 */ + uint8_t RESERVED_9[76]; + __IO uint32_t THRES; /**< LCDIF Threshold Register, offset: 0x200 */ + uint8_t RESERVED_10[380]; + __IO uint32_t PIGEONCTRL0; /**< LCDIF Pigeon Mode Control0 Register, offset: 0x380 */ + __IO uint32_t PIGEONCTRL0_SET; /**< LCDIF Pigeon Mode Control0 Register, offset: 0x384 */ + __IO uint32_t PIGEONCTRL0_CLR; /**< LCDIF Pigeon Mode Control0 Register, offset: 0x388 */ + __IO uint32_t PIGEONCTRL0_TOG; /**< LCDIF Pigeon Mode Control0 Register, offset: 0x38C */ + __IO uint32_t PIGEONCTRL1; /**< LCDIF Pigeon Mode Control1 Register, offset: 0x390 */ + __IO uint32_t PIGEONCTRL1_SET; /**< LCDIF Pigeon Mode Control1 Register, offset: 0x394 */ + __IO uint32_t PIGEONCTRL1_CLR; /**< LCDIF Pigeon Mode Control1 Register, offset: 0x398 */ + __IO uint32_t PIGEONCTRL1_TOG; /**< LCDIF Pigeon Mode Control1 Register, offset: 0x39C */ + __IO uint32_t PIGEONCTRL2; /**< LCDIF Pigeon Mode Control2 Register, offset: 0x3A0 */ + __IO uint32_t PIGEONCTRL2_SET; /**< LCDIF Pigeon Mode Control2 Register, offset: 0x3A4 */ + __IO uint32_t PIGEONCTRL2_CLR; /**< LCDIF Pigeon Mode Control2 Register, offset: 0x3A8 */ + __IO uint32_t PIGEONCTRL2_TOG; /**< LCDIF Pigeon Mode Control2 Register, offset: 0x3AC */ + uint8_t RESERVED_11[1104]; + struct { /* offset: 0x800, array step: 0x40 */ + __IO uint32_t PIGEON_0; /**< Panel Interface Signal Generator Register, array offset: 0x800, array step: 0x40 */ + uint8_t RESERVED_0[12]; + __IO uint32_t PIGEON_1; /**< Panel Interface Signal Generator Register, array offset: 0x810, array step: 0x40 */ + uint8_t RESERVED_1[12]; + __IO uint32_t PIGEON_2; /**< Panel Interface Signal Generator Register, array offset: 0x820, array step: 0x40 */ + uint8_t RESERVED_2[28]; + } PIGEON[12]; + __IO uint32_t LUT_CTRL; /**< Lookup Table Data Register., offset: 0xB00 */ + uint8_t RESERVED_12[12]; + __IO uint32_t LUT0_ADDR; /**< Lookup Table Control Register., offset: 0xB10 */ + uint8_t RESERVED_13[12]; + __IO uint32_t LUT0_DATA; /**< Lookup Table Data Register., offset: 0xB20 */ + uint8_t RESERVED_14[12]; + __IO uint32_t LUT1_ADDR; /**< Lookup Table Control Register., offset: 0xB30 */ + uint8_t RESERVED_15[12]; + __IO uint32_t LUT1_DATA; /**< Lookup Table Data Register., offset: 0xB40 */ +} LCDIF_Type; + +/* ---------------------------------------------------------------------------- + -- LCDIF Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup LCDIF_Register_Masks LCDIF Register Masks + * @{ + */ + +/*! @name CTRL - LCDIF General Control Register */ +/*! @{ */ +#define LCDIF_CTRL_RUN_MASK (0x1U) +#define LCDIF_CTRL_RUN_SHIFT (0U) +#define LCDIF_CTRL_RUN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_RUN_SHIFT)) & LCDIF_CTRL_RUN_MASK) +#define LCDIF_CTRL_DATA_FORMAT_24_BIT_MASK (0x2U) +#define LCDIF_CTRL_DATA_FORMAT_24_BIT_SHIFT (1U) +/*! DATA_FORMAT_24_BIT + * 0b0..Data input to the block is in 24 bpp format, such that all RGB 888 data is contained in 24 bits. + * 0b1..Data input to the block is actually RGB 18 bpp, but there is 1 color per byte, hence the upper 2 bits in each byte do not contain any useful data, and should be dropped. + */ +#define LCDIF_CTRL_DATA_FORMAT_24_BIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_DATA_FORMAT_24_BIT_SHIFT)) & LCDIF_CTRL_DATA_FORMAT_24_BIT_MASK) +#define LCDIF_CTRL_DATA_FORMAT_18_BIT_MASK (0x4U) +#define LCDIF_CTRL_DATA_FORMAT_18_BIT_SHIFT (2U) +/*! DATA_FORMAT_18_BIT + * 0b0..Data input to the block is in 18 bpp format, such that lower 18 bits contain RGB 666 and upper 14 bits do not contain any useful data. + * 0b1..Data input to the block is in 18 bpp format, such that upper 18 bits contain RGB 666 and lower 14 bits do not contain any useful data. + */ +#define LCDIF_CTRL_DATA_FORMAT_18_BIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_DATA_FORMAT_18_BIT_SHIFT)) & LCDIF_CTRL_DATA_FORMAT_18_BIT_MASK) +#define LCDIF_CTRL_DATA_FORMAT_16_BIT_MASK (0x8U) +#define LCDIF_CTRL_DATA_FORMAT_16_BIT_SHIFT (3U) +#define LCDIF_CTRL_DATA_FORMAT_16_BIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_DATA_FORMAT_16_BIT_SHIFT)) & LCDIF_CTRL_DATA_FORMAT_16_BIT_MASK) +#define LCDIF_CTRL_RSRVD0_MASK (0x10U) +#define LCDIF_CTRL_RSRVD0_SHIFT (4U) +#define LCDIF_CTRL_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_RSRVD0_SHIFT)) & LCDIF_CTRL_RSRVD0_MASK) +#define LCDIF_CTRL_MASTER_MASK (0x20U) +#define LCDIF_CTRL_MASTER_SHIFT (5U) +#define LCDIF_CTRL_MASTER(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_MASTER_SHIFT)) & LCDIF_CTRL_MASTER_MASK) +#define LCDIF_CTRL_ENABLE_PXP_HANDSHAKE_MASK (0x40U) +#define LCDIF_CTRL_ENABLE_PXP_HANDSHAKE_SHIFT (6U) +#define LCDIF_CTRL_ENABLE_PXP_HANDSHAKE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_ENABLE_PXP_HANDSHAKE_SHIFT)) & LCDIF_CTRL_ENABLE_PXP_HANDSHAKE_MASK) +#define LCDIF_CTRL_WORD_LENGTH_MASK (0x300U) +#define LCDIF_CTRL_WORD_LENGTH_SHIFT (8U) +/*! WORD_LENGTH + * 0b00..Input data is 16 bits per pixel. + * 0b01..Input data is 8 bits wide. + * 0b10..Input data is 18 bits per pixel. + * 0b11..Input data is 24 bits per pixel. + */ +#define LCDIF_CTRL_WORD_LENGTH(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_WORD_LENGTH_SHIFT)) & LCDIF_CTRL_WORD_LENGTH_MASK) +#define LCDIF_CTRL_LCD_DATABUS_WIDTH_MASK (0xC00U) +#define LCDIF_CTRL_LCD_DATABUS_WIDTH_SHIFT (10U) +/*! LCD_DATABUS_WIDTH + * 0b00..16-bit data bus mode. + * 0b01..8-bit data bus mode. + * 0b10..18-bit data bus mode. + * 0b11..24-bit data bus mode. + */ +#define LCDIF_CTRL_LCD_DATABUS_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_LCD_DATABUS_WIDTH_SHIFT)) & LCDIF_CTRL_LCD_DATABUS_WIDTH_MASK) +#define LCDIF_CTRL_CSC_DATA_SWIZZLE_MASK (0x3000U) +#define LCDIF_CTRL_CSC_DATA_SWIZZLE_SHIFT (12U) +/*! CSC_DATA_SWIZZLE + * 0b00..No byte swapping.(Little endian) + * 0b00..Little Endian byte ordering (same as NO_SWAP). + * 0b01..Big Endian swap (swap bytes 0,3 and 1,2). + * 0b01..Swizzle all bytes, swap bytes 0,3 and 1,2 (aka Big Endian). + * 0b10..Swap half-words. + * 0b11..Swap bytes within each half-word. + */ +#define LCDIF_CTRL_CSC_DATA_SWIZZLE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CSC_DATA_SWIZZLE_SHIFT)) & LCDIF_CTRL_CSC_DATA_SWIZZLE_MASK) +#define LCDIF_CTRL_INPUT_DATA_SWIZZLE_MASK (0xC000U) +#define LCDIF_CTRL_INPUT_DATA_SWIZZLE_SHIFT (14U) +/*! INPUT_DATA_SWIZZLE + * 0b00..No byte swapping.(Little endian) + * 0b00..Little Endian byte ordering (same as NO_SWAP). + * 0b01..Big Endian swap (swap bytes 0,3 and 1,2). + * 0b01..Swizzle all bytes, swap bytes 0,3 and 1,2 (aka Big Endian). + * 0b10..Swap half-words. + * 0b11..Swap bytes within each half-word. + */ +#define LCDIF_CTRL_INPUT_DATA_SWIZZLE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_INPUT_DATA_SWIZZLE_SHIFT)) & LCDIF_CTRL_INPUT_DATA_SWIZZLE_MASK) +#define LCDIF_CTRL_DOTCLK_MODE_MASK (0x20000U) +#define LCDIF_CTRL_DOTCLK_MODE_SHIFT (17U) +#define LCDIF_CTRL_DOTCLK_MODE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_DOTCLK_MODE_SHIFT)) & LCDIF_CTRL_DOTCLK_MODE_MASK) +#define LCDIF_CTRL_BYPASS_COUNT_MASK (0x80000U) +#define LCDIF_CTRL_BYPASS_COUNT_SHIFT (19U) +#define LCDIF_CTRL_BYPASS_COUNT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_BYPASS_COUNT_SHIFT)) & LCDIF_CTRL_BYPASS_COUNT_MASK) +#define LCDIF_CTRL_SHIFT_NUM_BITS_MASK (0x3E00000U) +#define LCDIF_CTRL_SHIFT_NUM_BITS_SHIFT (21U) +#define LCDIF_CTRL_SHIFT_NUM_BITS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SHIFT_NUM_BITS_SHIFT)) & LCDIF_CTRL_SHIFT_NUM_BITS_MASK) +#define LCDIF_CTRL_DATA_SHIFT_DIR_MASK (0x4000000U) +#define LCDIF_CTRL_DATA_SHIFT_DIR_SHIFT (26U) +/*! DATA_SHIFT_DIR + * 0b0..Data to be transmitted is shifted LEFT by SHIFT_NUM_BITS bits. + * 0b1..Data to be transmitted is shifted RIGHT by SHIFT_NUM_BITS bits. + */ +#define LCDIF_CTRL_DATA_SHIFT_DIR(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_DATA_SHIFT_DIR_SHIFT)) & LCDIF_CTRL_DATA_SHIFT_DIR_MASK) +#define LCDIF_CTRL_CLKGATE_MASK (0x40000000U) +#define LCDIF_CTRL_CLKGATE_SHIFT (30U) +#define LCDIF_CTRL_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLKGATE_SHIFT)) & LCDIF_CTRL_CLKGATE_MASK) +#define LCDIF_CTRL_SFTRST_MASK (0x80000000U) +#define LCDIF_CTRL_SFTRST_SHIFT (31U) +#define LCDIF_CTRL_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SFTRST_SHIFT)) & LCDIF_CTRL_SFTRST_MASK) +/*! @} */ + +/*! @name CTRL_SET - LCDIF General Control Register */ +/*! @{ */ +#define LCDIF_CTRL_SET_RUN_MASK (0x1U) +#define LCDIF_CTRL_SET_RUN_SHIFT (0U) +#define LCDIF_CTRL_SET_RUN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_RUN_SHIFT)) & LCDIF_CTRL_SET_RUN_MASK) +#define LCDIF_CTRL_SET_DATA_FORMAT_24_BIT_MASK (0x2U) +#define LCDIF_CTRL_SET_DATA_FORMAT_24_BIT_SHIFT (1U) +/*! DATA_FORMAT_24_BIT + * 0b0..Data input to the block is in 24 bpp format, such that all RGB 888 data is contained in 24 bits. + * 0b1..Data input to the block is actually RGB 18 bpp, but there is 1 color per byte, hence the upper 2 bits in each byte do not contain any useful data, and should be dropped. + */ +#define LCDIF_CTRL_SET_DATA_FORMAT_24_BIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_DATA_FORMAT_24_BIT_SHIFT)) & LCDIF_CTRL_SET_DATA_FORMAT_24_BIT_MASK) +#define LCDIF_CTRL_SET_DATA_FORMAT_18_BIT_MASK (0x4U) +#define LCDIF_CTRL_SET_DATA_FORMAT_18_BIT_SHIFT (2U) +/*! DATA_FORMAT_18_BIT + * 0b0..Data input to the block is in 18 bpp format, such that lower 18 bits contain RGB 666 and upper 14 bits do not contain any useful data. + * 0b1..Data input to the block is in 18 bpp format, such that upper 18 bits contain RGB 666 and lower 14 bits do not contain any useful data. + */ +#define LCDIF_CTRL_SET_DATA_FORMAT_18_BIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_DATA_FORMAT_18_BIT_SHIFT)) & LCDIF_CTRL_SET_DATA_FORMAT_18_BIT_MASK) +#define LCDIF_CTRL_SET_DATA_FORMAT_16_BIT_MASK (0x8U) +#define LCDIF_CTRL_SET_DATA_FORMAT_16_BIT_SHIFT (3U) +#define LCDIF_CTRL_SET_DATA_FORMAT_16_BIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_DATA_FORMAT_16_BIT_SHIFT)) & LCDIF_CTRL_SET_DATA_FORMAT_16_BIT_MASK) +#define LCDIF_CTRL_SET_RSRVD0_MASK (0x10U) +#define LCDIF_CTRL_SET_RSRVD0_SHIFT (4U) +#define LCDIF_CTRL_SET_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_RSRVD0_SHIFT)) & LCDIF_CTRL_SET_RSRVD0_MASK) +#define LCDIF_CTRL_SET_MASTER_MASK (0x20U) +#define LCDIF_CTRL_SET_MASTER_SHIFT (5U) +#define LCDIF_CTRL_SET_MASTER(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_MASTER_SHIFT)) & LCDIF_CTRL_SET_MASTER_MASK) +#define LCDIF_CTRL_SET_ENABLE_PXP_HANDSHAKE_MASK (0x40U) +#define LCDIF_CTRL_SET_ENABLE_PXP_HANDSHAKE_SHIFT (6U) +#define LCDIF_CTRL_SET_ENABLE_PXP_HANDSHAKE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_ENABLE_PXP_HANDSHAKE_SHIFT)) & LCDIF_CTRL_SET_ENABLE_PXP_HANDSHAKE_MASK) +#define LCDIF_CTRL_SET_WORD_LENGTH_MASK (0x300U) +#define LCDIF_CTRL_SET_WORD_LENGTH_SHIFT (8U) +/*! WORD_LENGTH + * 0b00..Input data is 16 bits per pixel. + * 0b01..Input data is 8 bits wide. + * 0b10..Input data is 18 bits per pixel. + * 0b11..Input data is 24 bits per pixel. + */ +#define LCDIF_CTRL_SET_WORD_LENGTH(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_WORD_LENGTH_SHIFT)) & LCDIF_CTRL_SET_WORD_LENGTH_MASK) +#define LCDIF_CTRL_SET_LCD_DATABUS_WIDTH_MASK (0xC00U) +#define LCDIF_CTRL_SET_LCD_DATABUS_WIDTH_SHIFT (10U) +/*! LCD_DATABUS_WIDTH + * 0b00..16-bit data bus mode. + * 0b01..8-bit data bus mode. + * 0b10..18-bit data bus mode. + * 0b11..24-bit data bus mode. + */ +#define LCDIF_CTRL_SET_LCD_DATABUS_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_LCD_DATABUS_WIDTH_SHIFT)) & LCDIF_CTRL_SET_LCD_DATABUS_WIDTH_MASK) +#define LCDIF_CTRL_SET_CSC_DATA_SWIZZLE_MASK (0x3000U) +#define LCDIF_CTRL_SET_CSC_DATA_SWIZZLE_SHIFT (12U) +/*! CSC_DATA_SWIZZLE + * 0b00..No byte swapping.(Little endian) + * 0b00..Little Endian byte ordering (same as NO_SWAP). + * 0b01..Big Endian swap (swap bytes 0,3 and 1,2). + * 0b01..Swizzle all bytes, swap bytes 0,3 and 1,2 (aka Big Endian). + * 0b10..Swap half-words. + * 0b11..Swap bytes within each half-word. + */ +#define LCDIF_CTRL_SET_CSC_DATA_SWIZZLE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_CSC_DATA_SWIZZLE_SHIFT)) & LCDIF_CTRL_SET_CSC_DATA_SWIZZLE_MASK) +#define LCDIF_CTRL_SET_INPUT_DATA_SWIZZLE_MASK (0xC000U) +#define LCDIF_CTRL_SET_INPUT_DATA_SWIZZLE_SHIFT (14U) +/*! INPUT_DATA_SWIZZLE + * 0b00..No byte swapping.(Little endian) + * 0b00..Little Endian byte ordering (same as NO_SWAP). + * 0b01..Big Endian swap (swap bytes 0,3 and 1,2). + * 0b01..Swizzle all bytes, swap bytes 0,3 and 1,2 (aka Big Endian). + * 0b10..Swap half-words. + * 0b11..Swap bytes within each half-word. + */ +#define LCDIF_CTRL_SET_INPUT_DATA_SWIZZLE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_INPUT_DATA_SWIZZLE_SHIFT)) & LCDIF_CTRL_SET_INPUT_DATA_SWIZZLE_MASK) +#define LCDIF_CTRL_SET_DOTCLK_MODE_MASK (0x20000U) +#define LCDIF_CTRL_SET_DOTCLK_MODE_SHIFT (17U) +#define LCDIF_CTRL_SET_DOTCLK_MODE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_DOTCLK_MODE_SHIFT)) & LCDIF_CTRL_SET_DOTCLK_MODE_MASK) +#define LCDIF_CTRL_SET_BYPASS_COUNT_MASK (0x80000U) +#define LCDIF_CTRL_SET_BYPASS_COUNT_SHIFT (19U) +#define LCDIF_CTRL_SET_BYPASS_COUNT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_BYPASS_COUNT_SHIFT)) & LCDIF_CTRL_SET_BYPASS_COUNT_MASK) +#define LCDIF_CTRL_SET_SHIFT_NUM_BITS_MASK (0x3E00000U) +#define LCDIF_CTRL_SET_SHIFT_NUM_BITS_SHIFT (21U) +#define LCDIF_CTRL_SET_SHIFT_NUM_BITS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_SHIFT_NUM_BITS_SHIFT)) & LCDIF_CTRL_SET_SHIFT_NUM_BITS_MASK) +#define LCDIF_CTRL_SET_DATA_SHIFT_DIR_MASK (0x4000000U) +#define LCDIF_CTRL_SET_DATA_SHIFT_DIR_SHIFT (26U) +/*! DATA_SHIFT_DIR + * 0b0..Data to be transmitted is shifted LEFT by SHIFT_NUM_BITS bits. + * 0b1..Data to be transmitted is shifted RIGHT by SHIFT_NUM_BITS bits. + */ +#define LCDIF_CTRL_SET_DATA_SHIFT_DIR(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_DATA_SHIFT_DIR_SHIFT)) & LCDIF_CTRL_SET_DATA_SHIFT_DIR_MASK) +#define LCDIF_CTRL_SET_CLKGATE_MASK (0x40000000U) +#define LCDIF_CTRL_SET_CLKGATE_SHIFT (30U) +#define LCDIF_CTRL_SET_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_CLKGATE_SHIFT)) & LCDIF_CTRL_SET_CLKGATE_MASK) +#define LCDIF_CTRL_SET_SFTRST_MASK (0x80000000U) +#define LCDIF_CTRL_SET_SFTRST_SHIFT (31U) +#define LCDIF_CTRL_SET_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_SFTRST_SHIFT)) & LCDIF_CTRL_SET_SFTRST_MASK) +/*! @} */ + +/*! @name CTRL_CLR - LCDIF General Control Register */ +/*! @{ */ +#define LCDIF_CTRL_CLR_RUN_MASK (0x1U) +#define LCDIF_CTRL_CLR_RUN_SHIFT (0U) +#define LCDIF_CTRL_CLR_RUN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_RUN_SHIFT)) & LCDIF_CTRL_CLR_RUN_MASK) +#define LCDIF_CTRL_CLR_DATA_FORMAT_24_BIT_MASK (0x2U) +#define LCDIF_CTRL_CLR_DATA_FORMAT_24_BIT_SHIFT (1U) +/*! DATA_FORMAT_24_BIT + * 0b0..Data input to the block is in 24 bpp format, such that all RGB 888 data is contained in 24 bits. + * 0b1..Data input to the block is actually RGB 18 bpp, but there is 1 color per byte, hence the upper 2 bits in each byte do not contain any useful data, and should be dropped. + */ +#define LCDIF_CTRL_CLR_DATA_FORMAT_24_BIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_DATA_FORMAT_24_BIT_SHIFT)) & LCDIF_CTRL_CLR_DATA_FORMAT_24_BIT_MASK) +#define LCDIF_CTRL_CLR_DATA_FORMAT_18_BIT_MASK (0x4U) +#define LCDIF_CTRL_CLR_DATA_FORMAT_18_BIT_SHIFT (2U) +/*! DATA_FORMAT_18_BIT + * 0b0..Data input to the block is in 18 bpp format, such that lower 18 bits contain RGB 666 and upper 14 bits do not contain any useful data. + * 0b1..Data input to the block is in 18 bpp format, such that upper 18 bits contain RGB 666 and lower 14 bits do not contain any useful data. + */ +#define LCDIF_CTRL_CLR_DATA_FORMAT_18_BIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_DATA_FORMAT_18_BIT_SHIFT)) & LCDIF_CTRL_CLR_DATA_FORMAT_18_BIT_MASK) +#define LCDIF_CTRL_CLR_DATA_FORMAT_16_BIT_MASK (0x8U) +#define LCDIF_CTRL_CLR_DATA_FORMAT_16_BIT_SHIFT (3U) +#define LCDIF_CTRL_CLR_DATA_FORMAT_16_BIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_DATA_FORMAT_16_BIT_SHIFT)) & LCDIF_CTRL_CLR_DATA_FORMAT_16_BIT_MASK) +#define LCDIF_CTRL_CLR_RSRVD0_MASK (0x10U) +#define LCDIF_CTRL_CLR_RSRVD0_SHIFT (4U) +#define LCDIF_CTRL_CLR_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_RSRVD0_SHIFT)) & LCDIF_CTRL_CLR_RSRVD0_MASK) +#define LCDIF_CTRL_CLR_MASTER_MASK (0x20U) +#define LCDIF_CTRL_CLR_MASTER_SHIFT (5U) +#define LCDIF_CTRL_CLR_MASTER(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_MASTER_SHIFT)) & LCDIF_CTRL_CLR_MASTER_MASK) +#define LCDIF_CTRL_CLR_ENABLE_PXP_HANDSHAKE_MASK (0x40U) +#define LCDIF_CTRL_CLR_ENABLE_PXP_HANDSHAKE_SHIFT (6U) +#define LCDIF_CTRL_CLR_ENABLE_PXP_HANDSHAKE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_ENABLE_PXP_HANDSHAKE_SHIFT)) & LCDIF_CTRL_CLR_ENABLE_PXP_HANDSHAKE_MASK) +#define LCDIF_CTRL_CLR_WORD_LENGTH_MASK (0x300U) +#define LCDIF_CTRL_CLR_WORD_LENGTH_SHIFT (8U) +/*! WORD_LENGTH + * 0b00..Input data is 16 bits per pixel. + * 0b01..Input data is 8 bits wide. + * 0b10..Input data is 18 bits per pixel. + * 0b11..Input data is 24 bits per pixel. + */ +#define LCDIF_CTRL_CLR_WORD_LENGTH(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_WORD_LENGTH_SHIFT)) & LCDIF_CTRL_CLR_WORD_LENGTH_MASK) +#define LCDIF_CTRL_CLR_LCD_DATABUS_WIDTH_MASK (0xC00U) +#define LCDIF_CTRL_CLR_LCD_DATABUS_WIDTH_SHIFT (10U) +/*! LCD_DATABUS_WIDTH + * 0b00..16-bit data bus mode. + * 0b01..8-bit data bus mode. + * 0b10..18-bit data bus mode. + * 0b11..24-bit data bus mode. + */ +#define LCDIF_CTRL_CLR_LCD_DATABUS_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_LCD_DATABUS_WIDTH_SHIFT)) & LCDIF_CTRL_CLR_LCD_DATABUS_WIDTH_MASK) +#define LCDIF_CTRL_CLR_CSC_DATA_SWIZZLE_MASK (0x3000U) +#define LCDIF_CTRL_CLR_CSC_DATA_SWIZZLE_SHIFT (12U) +/*! CSC_DATA_SWIZZLE + * 0b00..No byte swapping.(Little endian) + * 0b00..Little Endian byte ordering (same as NO_SWAP). + * 0b01..Big Endian swap (swap bytes 0,3 and 1,2). + * 0b01..Swizzle all bytes, swap bytes 0,3 and 1,2 (aka Big Endian). + * 0b10..Swap half-words. + * 0b11..Swap bytes within each half-word. + */ +#define LCDIF_CTRL_CLR_CSC_DATA_SWIZZLE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_CSC_DATA_SWIZZLE_SHIFT)) & LCDIF_CTRL_CLR_CSC_DATA_SWIZZLE_MASK) +#define LCDIF_CTRL_CLR_INPUT_DATA_SWIZZLE_MASK (0xC000U) +#define LCDIF_CTRL_CLR_INPUT_DATA_SWIZZLE_SHIFT (14U) +/*! INPUT_DATA_SWIZZLE + * 0b00..No byte swapping.(Little endian) + * 0b00..Little Endian byte ordering (same as NO_SWAP). + * 0b01..Big Endian swap (swap bytes 0,3 and 1,2). + * 0b01..Swizzle all bytes, swap bytes 0,3 and 1,2 (aka Big Endian). + * 0b10..Swap half-words. + * 0b11..Swap bytes within each half-word. + */ +#define LCDIF_CTRL_CLR_INPUT_DATA_SWIZZLE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_INPUT_DATA_SWIZZLE_SHIFT)) & LCDIF_CTRL_CLR_INPUT_DATA_SWIZZLE_MASK) +#define LCDIF_CTRL_CLR_DOTCLK_MODE_MASK (0x20000U) +#define LCDIF_CTRL_CLR_DOTCLK_MODE_SHIFT (17U) +#define LCDIF_CTRL_CLR_DOTCLK_MODE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_DOTCLK_MODE_SHIFT)) & LCDIF_CTRL_CLR_DOTCLK_MODE_MASK) +#define LCDIF_CTRL_CLR_BYPASS_COUNT_MASK (0x80000U) +#define LCDIF_CTRL_CLR_BYPASS_COUNT_SHIFT (19U) +#define LCDIF_CTRL_CLR_BYPASS_COUNT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_BYPASS_COUNT_SHIFT)) & LCDIF_CTRL_CLR_BYPASS_COUNT_MASK) +#define LCDIF_CTRL_CLR_SHIFT_NUM_BITS_MASK (0x3E00000U) +#define LCDIF_CTRL_CLR_SHIFT_NUM_BITS_SHIFT (21U) +#define LCDIF_CTRL_CLR_SHIFT_NUM_BITS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_SHIFT_NUM_BITS_SHIFT)) & LCDIF_CTRL_CLR_SHIFT_NUM_BITS_MASK) +#define LCDIF_CTRL_CLR_DATA_SHIFT_DIR_MASK (0x4000000U) +#define LCDIF_CTRL_CLR_DATA_SHIFT_DIR_SHIFT (26U) +/*! DATA_SHIFT_DIR + * 0b0..Data to be transmitted is shifted LEFT by SHIFT_NUM_BITS bits. + * 0b1..Data to be transmitted is shifted RIGHT by SHIFT_NUM_BITS bits. + */ +#define LCDIF_CTRL_CLR_DATA_SHIFT_DIR(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_DATA_SHIFT_DIR_SHIFT)) & LCDIF_CTRL_CLR_DATA_SHIFT_DIR_MASK) +#define LCDIF_CTRL_CLR_CLKGATE_MASK (0x40000000U) +#define LCDIF_CTRL_CLR_CLKGATE_SHIFT (30U) +#define LCDIF_CTRL_CLR_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_CLKGATE_SHIFT)) & LCDIF_CTRL_CLR_CLKGATE_MASK) +#define LCDIF_CTRL_CLR_SFTRST_MASK (0x80000000U) +#define LCDIF_CTRL_CLR_SFTRST_SHIFT (31U) +#define LCDIF_CTRL_CLR_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_SFTRST_SHIFT)) & LCDIF_CTRL_CLR_SFTRST_MASK) +/*! @} */ + +/*! @name CTRL_TOG - LCDIF General Control Register */ +/*! @{ */ +#define LCDIF_CTRL_TOG_RUN_MASK (0x1U) +#define LCDIF_CTRL_TOG_RUN_SHIFT (0U) +#define LCDIF_CTRL_TOG_RUN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_RUN_SHIFT)) & LCDIF_CTRL_TOG_RUN_MASK) +#define LCDIF_CTRL_TOG_DATA_FORMAT_24_BIT_MASK (0x2U) +#define LCDIF_CTRL_TOG_DATA_FORMAT_24_BIT_SHIFT (1U) +/*! DATA_FORMAT_24_BIT + * 0b0..Data input to the block is in 24 bpp format, such that all RGB 888 data is contained in 24 bits. + * 0b1..Data input to the block is actually RGB 18 bpp, but there is 1 color per byte, hence the upper 2 bits in each byte do not contain any useful data, and should be dropped. + */ +#define LCDIF_CTRL_TOG_DATA_FORMAT_24_BIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_DATA_FORMAT_24_BIT_SHIFT)) & LCDIF_CTRL_TOG_DATA_FORMAT_24_BIT_MASK) +#define LCDIF_CTRL_TOG_DATA_FORMAT_18_BIT_MASK (0x4U) +#define LCDIF_CTRL_TOG_DATA_FORMAT_18_BIT_SHIFT (2U) +/*! DATA_FORMAT_18_BIT + * 0b0..Data input to the block is in 18 bpp format, such that lower 18 bits contain RGB 666 and upper 14 bits do not contain any useful data. + * 0b1..Data input to the block is in 18 bpp format, such that upper 18 bits contain RGB 666 and lower 14 bits do not contain any useful data. + */ +#define LCDIF_CTRL_TOG_DATA_FORMAT_18_BIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_DATA_FORMAT_18_BIT_SHIFT)) & LCDIF_CTRL_TOG_DATA_FORMAT_18_BIT_MASK) +#define LCDIF_CTRL_TOG_DATA_FORMAT_16_BIT_MASK (0x8U) +#define LCDIF_CTRL_TOG_DATA_FORMAT_16_BIT_SHIFT (3U) +#define LCDIF_CTRL_TOG_DATA_FORMAT_16_BIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_DATA_FORMAT_16_BIT_SHIFT)) & LCDIF_CTRL_TOG_DATA_FORMAT_16_BIT_MASK) +#define LCDIF_CTRL_TOG_RSRVD0_MASK (0x10U) +#define LCDIF_CTRL_TOG_RSRVD0_SHIFT (4U) +#define LCDIF_CTRL_TOG_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_RSRVD0_SHIFT)) & LCDIF_CTRL_TOG_RSRVD0_MASK) +#define LCDIF_CTRL_TOG_MASTER_MASK (0x20U) +#define LCDIF_CTRL_TOG_MASTER_SHIFT (5U) +#define LCDIF_CTRL_TOG_MASTER(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_MASTER_SHIFT)) & LCDIF_CTRL_TOG_MASTER_MASK) +#define LCDIF_CTRL_TOG_ENABLE_PXP_HANDSHAKE_MASK (0x40U) +#define LCDIF_CTRL_TOG_ENABLE_PXP_HANDSHAKE_SHIFT (6U) +#define LCDIF_CTRL_TOG_ENABLE_PXP_HANDSHAKE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_ENABLE_PXP_HANDSHAKE_SHIFT)) & LCDIF_CTRL_TOG_ENABLE_PXP_HANDSHAKE_MASK) +#define LCDIF_CTRL_TOG_WORD_LENGTH_MASK (0x300U) +#define LCDIF_CTRL_TOG_WORD_LENGTH_SHIFT (8U) +/*! WORD_LENGTH + * 0b00..Input data is 16 bits per pixel. + * 0b01..Input data is 8 bits wide. + * 0b10..Input data is 18 bits per pixel. + * 0b11..Input data is 24 bits per pixel. + */ +#define LCDIF_CTRL_TOG_WORD_LENGTH(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_WORD_LENGTH_SHIFT)) & LCDIF_CTRL_TOG_WORD_LENGTH_MASK) +#define LCDIF_CTRL_TOG_LCD_DATABUS_WIDTH_MASK (0xC00U) +#define LCDIF_CTRL_TOG_LCD_DATABUS_WIDTH_SHIFT (10U) +/*! LCD_DATABUS_WIDTH + * 0b00..16-bit data bus mode. + * 0b01..8-bit data bus mode. + * 0b10..18-bit data bus mode. + * 0b11..24-bit data bus mode. + */ +#define LCDIF_CTRL_TOG_LCD_DATABUS_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_LCD_DATABUS_WIDTH_SHIFT)) & LCDIF_CTRL_TOG_LCD_DATABUS_WIDTH_MASK) +#define LCDIF_CTRL_TOG_CSC_DATA_SWIZZLE_MASK (0x3000U) +#define LCDIF_CTRL_TOG_CSC_DATA_SWIZZLE_SHIFT (12U) +/*! CSC_DATA_SWIZZLE + * 0b00..No byte swapping.(Little endian) + * 0b00..Little Endian byte ordering (same as NO_SWAP). + * 0b01..Big Endian swap (swap bytes 0,3 and 1,2). + * 0b01..Swizzle all bytes, swap bytes 0,3 and 1,2 (aka Big Endian). + * 0b10..Swap half-words. + * 0b11..Swap bytes within each half-word. + */ +#define LCDIF_CTRL_TOG_CSC_DATA_SWIZZLE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_CSC_DATA_SWIZZLE_SHIFT)) & LCDIF_CTRL_TOG_CSC_DATA_SWIZZLE_MASK) +#define LCDIF_CTRL_TOG_INPUT_DATA_SWIZZLE_MASK (0xC000U) +#define LCDIF_CTRL_TOG_INPUT_DATA_SWIZZLE_SHIFT (14U) +/*! INPUT_DATA_SWIZZLE + * 0b00..No byte swapping.(Little endian) + * 0b00..Little Endian byte ordering (same as NO_SWAP). + * 0b01..Big Endian swap (swap bytes 0,3 and 1,2). + * 0b01..Swizzle all bytes, swap bytes 0,3 and 1,2 (aka Big Endian). + * 0b10..Swap half-words. + * 0b11..Swap bytes within each half-word. + */ +#define LCDIF_CTRL_TOG_INPUT_DATA_SWIZZLE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_INPUT_DATA_SWIZZLE_SHIFT)) & LCDIF_CTRL_TOG_INPUT_DATA_SWIZZLE_MASK) +#define LCDIF_CTRL_TOG_DOTCLK_MODE_MASK (0x20000U) +#define LCDIF_CTRL_TOG_DOTCLK_MODE_SHIFT (17U) +#define LCDIF_CTRL_TOG_DOTCLK_MODE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_DOTCLK_MODE_SHIFT)) & LCDIF_CTRL_TOG_DOTCLK_MODE_MASK) +#define LCDIF_CTRL_TOG_BYPASS_COUNT_MASK (0x80000U) +#define LCDIF_CTRL_TOG_BYPASS_COUNT_SHIFT (19U) +#define LCDIF_CTRL_TOG_BYPASS_COUNT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_BYPASS_COUNT_SHIFT)) & LCDIF_CTRL_TOG_BYPASS_COUNT_MASK) +#define LCDIF_CTRL_TOG_SHIFT_NUM_BITS_MASK (0x3E00000U) +#define LCDIF_CTRL_TOG_SHIFT_NUM_BITS_SHIFT (21U) +#define LCDIF_CTRL_TOG_SHIFT_NUM_BITS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_SHIFT_NUM_BITS_SHIFT)) & LCDIF_CTRL_TOG_SHIFT_NUM_BITS_MASK) +#define LCDIF_CTRL_TOG_DATA_SHIFT_DIR_MASK (0x4000000U) +#define LCDIF_CTRL_TOG_DATA_SHIFT_DIR_SHIFT (26U) +/*! DATA_SHIFT_DIR + * 0b0..Data to be transmitted is shifted LEFT by SHIFT_NUM_BITS bits. + * 0b1..Data to be transmitted is shifted RIGHT by SHIFT_NUM_BITS bits. + */ +#define LCDIF_CTRL_TOG_DATA_SHIFT_DIR(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_DATA_SHIFT_DIR_SHIFT)) & LCDIF_CTRL_TOG_DATA_SHIFT_DIR_MASK) +#define LCDIF_CTRL_TOG_CLKGATE_MASK (0x40000000U) +#define LCDIF_CTRL_TOG_CLKGATE_SHIFT (30U) +#define LCDIF_CTRL_TOG_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_CLKGATE_SHIFT)) & LCDIF_CTRL_TOG_CLKGATE_MASK) +#define LCDIF_CTRL_TOG_SFTRST_MASK (0x80000000U) +#define LCDIF_CTRL_TOG_SFTRST_SHIFT (31U) +#define LCDIF_CTRL_TOG_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_SFTRST_SHIFT)) & LCDIF_CTRL_TOG_SFTRST_MASK) +/*! @} */ + +/*! @name CTRL1 - LCDIF General Control1 Register */ +/*! @{ */ +#define LCDIF_CTRL1_RSRVD0_MASK (0xF8U) +#define LCDIF_CTRL1_RSRVD0_SHIFT (3U) +#define LCDIF_CTRL1_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_RSRVD0_SHIFT)) & LCDIF_CTRL1_RSRVD0_MASK) +#define LCDIF_CTRL1_VSYNC_EDGE_IRQ_MASK (0x100U) +#define LCDIF_CTRL1_VSYNC_EDGE_IRQ_SHIFT (8U) +/*! VSYNC_EDGE_IRQ + * 0b0..No Interrupt Request Pending. + * 0b1..Interrupt Request Pending. + */ +#define LCDIF_CTRL1_VSYNC_EDGE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_VSYNC_EDGE_IRQ_SHIFT)) & LCDIF_CTRL1_VSYNC_EDGE_IRQ_MASK) +#define LCDIF_CTRL1_CUR_FRAME_DONE_IRQ_MASK (0x200U) +#define LCDIF_CTRL1_CUR_FRAME_DONE_IRQ_SHIFT (9U) +/*! CUR_FRAME_DONE_IRQ + * 0b0..No Interrupt Request Pending. + * 0b1..Interrupt Request Pending. + */ +#define LCDIF_CTRL1_CUR_FRAME_DONE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CUR_FRAME_DONE_IRQ_SHIFT)) & LCDIF_CTRL1_CUR_FRAME_DONE_IRQ_MASK) +#define LCDIF_CTRL1_UNDERFLOW_IRQ_MASK (0x400U) +#define LCDIF_CTRL1_UNDERFLOW_IRQ_SHIFT (10U) +/*! UNDERFLOW_IRQ + * 0b0..No Interrupt Request Pending. + * 0b1..Interrupt Request Pending. + */ +#define LCDIF_CTRL1_UNDERFLOW_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_UNDERFLOW_IRQ_SHIFT)) & LCDIF_CTRL1_UNDERFLOW_IRQ_MASK) +#define LCDIF_CTRL1_OVERFLOW_IRQ_MASK (0x800U) +#define LCDIF_CTRL1_OVERFLOW_IRQ_SHIFT (11U) +/*! OVERFLOW_IRQ + * 0b0..No Interrupt Request Pending. + * 0b1..Interrupt Request Pending. + */ +#define LCDIF_CTRL1_OVERFLOW_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_OVERFLOW_IRQ_SHIFT)) & LCDIF_CTRL1_OVERFLOW_IRQ_MASK) +#define LCDIF_CTRL1_VSYNC_EDGE_IRQ_EN_MASK (0x1000U) +#define LCDIF_CTRL1_VSYNC_EDGE_IRQ_EN_SHIFT (12U) +#define LCDIF_CTRL1_VSYNC_EDGE_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_VSYNC_EDGE_IRQ_EN_SHIFT)) & LCDIF_CTRL1_VSYNC_EDGE_IRQ_EN_MASK) +#define LCDIF_CTRL1_CUR_FRAME_DONE_IRQ_EN_MASK (0x2000U) +#define LCDIF_CTRL1_CUR_FRAME_DONE_IRQ_EN_SHIFT (13U) +#define LCDIF_CTRL1_CUR_FRAME_DONE_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CUR_FRAME_DONE_IRQ_EN_SHIFT)) & LCDIF_CTRL1_CUR_FRAME_DONE_IRQ_EN_MASK) +#define LCDIF_CTRL1_UNDERFLOW_IRQ_EN_MASK (0x4000U) +#define LCDIF_CTRL1_UNDERFLOW_IRQ_EN_SHIFT (14U) +#define LCDIF_CTRL1_UNDERFLOW_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_UNDERFLOW_IRQ_EN_SHIFT)) & LCDIF_CTRL1_UNDERFLOW_IRQ_EN_MASK) +#define LCDIF_CTRL1_OVERFLOW_IRQ_EN_MASK (0x8000U) +#define LCDIF_CTRL1_OVERFLOW_IRQ_EN_SHIFT (15U) +#define LCDIF_CTRL1_OVERFLOW_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_OVERFLOW_IRQ_EN_SHIFT)) & LCDIF_CTRL1_OVERFLOW_IRQ_EN_MASK) +#define LCDIF_CTRL1_BYTE_PACKING_FORMAT_MASK (0xF0000U) +#define LCDIF_CTRL1_BYTE_PACKING_FORMAT_SHIFT (16U) +#define LCDIF_CTRL1_BYTE_PACKING_FORMAT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_BYTE_PACKING_FORMAT_SHIFT)) & LCDIF_CTRL1_BYTE_PACKING_FORMAT_MASK) +#define LCDIF_CTRL1_IRQ_ON_ALTERNATE_FIELDS_MASK (0x100000U) +#define LCDIF_CTRL1_IRQ_ON_ALTERNATE_FIELDS_SHIFT (20U) +#define LCDIF_CTRL1_IRQ_ON_ALTERNATE_FIELDS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_IRQ_ON_ALTERNATE_FIELDS_SHIFT)) & LCDIF_CTRL1_IRQ_ON_ALTERNATE_FIELDS_MASK) +#define LCDIF_CTRL1_FIFO_CLEAR_MASK (0x200000U) +#define LCDIF_CTRL1_FIFO_CLEAR_SHIFT (21U) +#define LCDIF_CTRL1_FIFO_CLEAR(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_FIFO_CLEAR_SHIFT)) & LCDIF_CTRL1_FIFO_CLEAR_MASK) +#define LCDIF_CTRL1_START_INTERLACE_FROM_SECOND_FIELD_MASK (0x400000U) +#define LCDIF_CTRL1_START_INTERLACE_FROM_SECOND_FIELD_SHIFT (22U) +#define LCDIF_CTRL1_START_INTERLACE_FROM_SECOND_FIELD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_START_INTERLACE_FROM_SECOND_FIELD_SHIFT)) & LCDIF_CTRL1_START_INTERLACE_FROM_SECOND_FIELD_MASK) +#define LCDIF_CTRL1_INTERLACE_FIELDS_MASK (0x800000U) +#define LCDIF_CTRL1_INTERLACE_FIELDS_SHIFT (23U) +#define LCDIF_CTRL1_INTERLACE_FIELDS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_INTERLACE_FIELDS_SHIFT)) & LCDIF_CTRL1_INTERLACE_FIELDS_MASK) +#define LCDIF_CTRL1_RECOVER_ON_UNDERFLOW_MASK (0x1000000U) +#define LCDIF_CTRL1_RECOVER_ON_UNDERFLOW_SHIFT (24U) +#define LCDIF_CTRL1_RECOVER_ON_UNDERFLOW(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_RECOVER_ON_UNDERFLOW_SHIFT)) & LCDIF_CTRL1_RECOVER_ON_UNDERFLOW_MASK) +#define LCDIF_CTRL1_BM_ERROR_IRQ_MASK (0x2000000U) +#define LCDIF_CTRL1_BM_ERROR_IRQ_SHIFT (25U) +/*! BM_ERROR_IRQ + * 0b0..No Interrupt Request Pending. + * 0b1..Interrupt Request Pending. + */ +#define LCDIF_CTRL1_BM_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_BM_ERROR_IRQ_SHIFT)) & LCDIF_CTRL1_BM_ERROR_IRQ_MASK) +#define LCDIF_CTRL1_BM_ERROR_IRQ_EN_MASK (0x4000000U) +#define LCDIF_CTRL1_BM_ERROR_IRQ_EN_SHIFT (26U) +#define LCDIF_CTRL1_BM_ERROR_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_BM_ERROR_IRQ_EN_SHIFT)) & LCDIF_CTRL1_BM_ERROR_IRQ_EN_MASK) +#define LCDIF_CTRL1_CS_OUT_SELECT_MASK (0x40000000U) +#define LCDIF_CTRL1_CS_OUT_SELECT_SHIFT (30U) +#define LCDIF_CTRL1_CS_OUT_SELECT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CS_OUT_SELECT_SHIFT)) & LCDIF_CTRL1_CS_OUT_SELECT_MASK) +#define LCDIF_CTRL1_IMAGE_DATA_SELECT_MASK (0x80000000U) +#define LCDIF_CTRL1_IMAGE_DATA_SELECT_SHIFT (31U) +#define LCDIF_CTRL1_IMAGE_DATA_SELECT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_IMAGE_DATA_SELECT_SHIFT)) & LCDIF_CTRL1_IMAGE_DATA_SELECT_MASK) +/*! @} */ + +/*! @name CTRL1_SET - LCDIF General Control1 Register */ +/*! @{ */ +#define LCDIF_CTRL1_SET_RSRVD0_MASK (0xF8U) +#define LCDIF_CTRL1_SET_RSRVD0_SHIFT (3U) +#define LCDIF_CTRL1_SET_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_RSRVD0_SHIFT)) & LCDIF_CTRL1_SET_RSRVD0_MASK) +#define LCDIF_CTRL1_SET_VSYNC_EDGE_IRQ_MASK (0x100U) +#define LCDIF_CTRL1_SET_VSYNC_EDGE_IRQ_SHIFT (8U) +/*! VSYNC_EDGE_IRQ + * 0b0..No Interrupt Request Pending. + * 0b1..Interrupt Request Pending. + */ +#define LCDIF_CTRL1_SET_VSYNC_EDGE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_VSYNC_EDGE_IRQ_SHIFT)) & LCDIF_CTRL1_SET_VSYNC_EDGE_IRQ_MASK) +#define LCDIF_CTRL1_SET_CUR_FRAME_DONE_IRQ_MASK (0x200U) +#define LCDIF_CTRL1_SET_CUR_FRAME_DONE_IRQ_SHIFT (9U) +/*! CUR_FRAME_DONE_IRQ + * 0b0..No Interrupt Request Pending. + * 0b1..Interrupt Request Pending. + */ +#define LCDIF_CTRL1_SET_CUR_FRAME_DONE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_CUR_FRAME_DONE_IRQ_SHIFT)) & LCDIF_CTRL1_SET_CUR_FRAME_DONE_IRQ_MASK) +#define LCDIF_CTRL1_SET_UNDERFLOW_IRQ_MASK (0x400U) +#define LCDIF_CTRL1_SET_UNDERFLOW_IRQ_SHIFT (10U) +/*! UNDERFLOW_IRQ + * 0b0..No Interrupt Request Pending. + * 0b1..Interrupt Request Pending. + */ +#define LCDIF_CTRL1_SET_UNDERFLOW_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_UNDERFLOW_IRQ_SHIFT)) & LCDIF_CTRL1_SET_UNDERFLOW_IRQ_MASK) +#define LCDIF_CTRL1_SET_OVERFLOW_IRQ_MASK (0x800U) +#define LCDIF_CTRL1_SET_OVERFLOW_IRQ_SHIFT (11U) +/*! OVERFLOW_IRQ + * 0b0..No Interrupt Request Pending. + * 0b1..Interrupt Request Pending. + */ +#define LCDIF_CTRL1_SET_OVERFLOW_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_OVERFLOW_IRQ_SHIFT)) & LCDIF_CTRL1_SET_OVERFLOW_IRQ_MASK) +#define LCDIF_CTRL1_SET_VSYNC_EDGE_IRQ_EN_MASK (0x1000U) +#define LCDIF_CTRL1_SET_VSYNC_EDGE_IRQ_EN_SHIFT (12U) +#define LCDIF_CTRL1_SET_VSYNC_EDGE_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_VSYNC_EDGE_IRQ_EN_SHIFT)) & LCDIF_CTRL1_SET_VSYNC_EDGE_IRQ_EN_MASK) +#define LCDIF_CTRL1_SET_CUR_FRAME_DONE_IRQ_EN_MASK (0x2000U) +#define LCDIF_CTRL1_SET_CUR_FRAME_DONE_IRQ_EN_SHIFT (13U) +#define LCDIF_CTRL1_SET_CUR_FRAME_DONE_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_CUR_FRAME_DONE_IRQ_EN_SHIFT)) & LCDIF_CTRL1_SET_CUR_FRAME_DONE_IRQ_EN_MASK) +#define LCDIF_CTRL1_SET_UNDERFLOW_IRQ_EN_MASK (0x4000U) +#define LCDIF_CTRL1_SET_UNDERFLOW_IRQ_EN_SHIFT (14U) +#define LCDIF_CTRL1_SET_UNDERFLOW_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_UNDERFLOW_IRQ_EN_SHIFT)) & LCDIF_CTRL1_SET_UNDERFLOW_IRQ_EN_MASK) +#define LCDIF_CTRL1_SET_OVERFLOW_IRQ_EN_MASK (0x8000U) +#define LCDIF_CTRL1_SET_OVERFLOW_IRQ_EN_SHIFT (15U) +#define LCDIF_CTRL1_SET_OVERFLOW_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_OVERFLOW_IRQ_EN_SHIFT)) & LCDIF_CTRL1_SET_OVERFLOW_IRQ_EN_MASK) +#define LCDIF_CTRL1_SET_BYTE_PACKING_FORMAT_MASK (0xF0000U) +#define LCDIF_CTRL1_SET_BYTE_PACKING_FORMAT_SHIFT (16U) +#define LCDIF_CTRL1_SET_BYTE_PACKING_FORMAT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_BYTE_PACKING_FORMAT_SHIFT)) & LCDIF_CTRL1_SET_BYTE_PACKING_FORMAT_MASK) +#define LCDIF_CTRL1_SET_IRQ_ON_ALTERNATE_FIELDS_MASK (0x100000U) +#define LCDIF_CTRL1_SET_IRQ_ON_ALTERNATE_FIELDS_SHIFT (20U) +#define LCDIF_CTRL1_SET_IRQ_ON_ALTERNATE_FIELDS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_IRQ_ON_ALTERNATE_FIELDS_SHIFT)) & LCDIF_CTRL1_SET_IRQ_ON_ALTERNATE_FIELDS_MASK) +#define LCDIF_CTRL1_SET_FIFO_CLEAR_MASK (0x200000U) +#define LCDIF_CTRL1_SET_FIFO_CLEAR_SHIFT (21U) +#define LCDIF_CTRL1_SET_FIFO_CLEAR(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_FIFO_CLEAR_SHIFT)) & LCDIF_CTRL1_SET_FIFO_CLEAR_MASK) +#define LCDIF_CTRL1_SET_START_INTERLACE_FROM_SECOND_FIELD_MASK (0x400000U) +#define LCDIF_CTRL1_SET_START_INTERLACE_FROM_SECOND_FIELD_SHIFT (22U) +#define LCDIF_CTRL1_SET_START_INTERLACE_FROM_SECOND_FIELD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_START_INTERLACE_FROM_SECOND_FIELD_SHIFT)) & LCDIF_CTRL1_SET_START_INTERLACE_FROM_SECOND_FIELD_MASK) +#define LCDIF_CTRL1_SET_INTERLACE_FIELDS_MASK (0x800000U) +#define LCDIF_CTRL1_SET_INTERLACE_FIELDS_SHIFT (23U) +#define LCDIF_CTRL1_SET_INTERLACE_FIELDS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_INTERLACE_FIELDS_SHIFT)) & LCDIF_CTRL1_SET_INTERLACE_FIELDS_MASK) +#define LCDIF_CTRL1_SET_RECOVER_ON_UNDERFLOW_MASK (0x1000000U) +#define LCDIF_CTRL1_SET_RECOVER_ON_UNDERFLOW_SHIFT (24U) +#define LCDIF_CTRL1_SET_RECOVER_ON_UNDERFLOW(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_RECOVER_ON_UNDERFLOW_SHIFT)) & LCDIF_CTRL1_SET_RECOVER_ON_UNDERFLOW_MASK) +#define LCDIF_CTRL1_SET_BM_ERROR_IRQ_MASK (0x2000000U) +#define LCDIF_CTRL1_SET_BM_ERROR_IRQ_SHIFT (25U) +/*! BM_ERROR_IRQ + * 0b0..No Interrupt Request Pending. + * 0b1..Interrupt Request Pending. + */ +#define LCDIF_CTRL1_SET_BM_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_BM_ERROR_IRQ_SHIFT)) & LCDIF_CTRL1_SET_BM_ERROR_IRQ_MASK) +#define LCDIF_CTRL1_SET_BM_ERROR_IRQ_EN_MASK (0x4000000U) +#define LCDIF_CTRL1_SET_BM_ERROR_IRQ_EN_SHIFT (26U) +#define LCDIF_CTRL1_SET_BM_ERROR_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_BM_ERROR_IRQ_EN_SHIFT)) & LCDIF_CTRL1_SET_BM_ERROR_IRQ_EN_MASK) +#define LCDIF_CTRL1_SET_CS_OUT_SELECT_MASK (0x40000000U) +#define LCDIF_CTRL1_SET_CS_OUT_SELECT_SHIFT (30U) +#define LCDIF_CTRL1_SET_CS_OUT_SELECT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_CS_OUT_SELECT_SHIFT)) & LCDIF_CTRL1_SET_CS_OUT_SELECT_MASK) +#define LCDIF_CTRL1_SET_IMAGE_DATA_SELECT_MASK (0x80000000U) +#define LCDIF_CTRL1_SET_IMAGE_DATA_SELECT_SHIFT (31U) +#define LCDIF_CTRL1_SET_IMAGE_DATA_SELECT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_IMAGE_DATA_SELECT_SHIFT)) & LCDIF_CTRL1_SET_IMAGE_DATA_SELECT_MASK) +/*! @} */ + +/*! @name CTRL1_CLR - LCDIF General Control1 Register */ +/*! @{ */ +#define LCDIF_CTRL1_CLR_RSRVD0_MASK (0xF8U) +#define LCDIF_CTRL1_CLR_RSRVD0_SHIFT (3U) +#define LCDIF_CTRL1_CLR_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_RSRVD0_SHIFT)) & LCDIF_CTRL1_CLR_RSRVD0_MASK) +#define LCDIF_CTRL1_CLR_VSYNC_EDGE_IRQ_MASK (0x100U) +#define LCDIF_CTRL1_CLR_VSYNC_EDGE_IRQ_SHIFT (8U) +/*! VSYNC_EDGE_IRQ + * 0b0..No Interrupt Request Pending. + * 0b1..Interrupt Request Pending. + */ +#define LCDIF_CTRL1_CLR_VSYNC_EDGE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_VSYNC_EDGE_IRQ_SHIFT)) & LCDIF_CTRL1_CLR_VSYNC_EDGE_IRQ_MASK) +#define LCDIF_CTRL1_CLR_CUR_FRAME_DONE_IRQ_MASK (0x200U) +#define LCDIF_CTRL1_CLR_CUR_FRAME_DONE_IRQ_SHIFT (9U) +/*! CUR_FRAME_DONE_IRQ + * 0b0..No Interrupt Request Pending. + * 0b1..Interrupt Request Pending. + */ +#define LCDIF_CTRL1_CLR_CUR_FRAME_DONE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_CUR_FRAME_DONE_IRQ_SHIFT)) & LCDIF_CTRL1_CLR_CUR_FRAME_DONE_IRQ_MASK) +#define LCDIF_CTRL1_CLR_UNDERFLOW_IRQ_MASK (0x400U) +#define LCDIF_CTRL1_CLR_UNDERFLOW_IRQ_SHIFT (10U) +/*! UNDERFLOW_IRQ + * 0b0..No Interrupt Request Pending. + * 0b1..Interrupt Request Pending. + */ +#define LCDIF_CTRL1_CLR_UNDERFLOW_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_UNDERFLOW_IRQ_SHIFT)) & LCDIF_CTRL1_CLR_UNDERFLOW_IRQ_MASK) +#define LCDIF_CTRL1_CLR_OVERFLOW_IRQ_MASK (0x800U) +#define LCDIF_CTRL1_CLR_OVERFLOW_IRQ_SHIFT (11U) +/*! OVERFLOW_IRQ + * 0b0..No Interrupt Request Pending. + * 0b1..Interrupt Request Pending. + */ +#define LCDIF_CTRL1_CLR_OVERFLOW_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_OVERFLOW_IRQ_SHIFT)) & LCDIF_CTRL1_CLR_OVERFLOW_IRQ_MASK) +#define LCDIF_CTRL1_CLR_VSYNC_EDGE_IRQ_EN_MASK (0x1000U) +#define LCDIF_CTRL1_CLR_VSYNC_EDGE_IRQ_EN_SHIFT (12U) +#define LCDIF_CTRL1_CLR_VSYNC_EDGE_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_VSYNC_EDGE_IRQ_EN_SHIFT)) & LCDIF_CTRL1_CLR_VSYNC_EDGE_IRQ_EN_MASK) +#define LCDIF_CTRL1_CLR_CUR_FRAME_DONE_IRQ_EN_MASK (0x2000U) +#define LCDIF_CTRL1_CLR_CUR_FRAME_DONE_IRQ_EN_SHIFT (13U) +#define LCDIF_CTRL1_CLR_CUR_FRAME_DONE_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_CUR_FRAME_DONE_IRQ_EN_SHIFT)) & LCDIF_CTRL1_CLR_CUR_FRAME_DONE_IRQ_EN_MASK) +#define LCDIF_CTRL1_CLR_UNDERFLOW_IRQ_EN_MASK (0x4000U) +#define LCDIF_CTRL1_CLR_UNDERFLOW_IRQ_EN_SHIFT (14U) +#define LCDIF_CTRL1_CLR_UNDERFLOW_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_UNDERFLOW_IRQ_EN_SHIFT)) & LCDIF_CTRL1_CLR_UNDERFLOW_IRQ_EN_MASK) +#define LCDIF_CTRL1_CLR_OVERFLOW_IRQ_EN_MASK (0x8000U) +#define LCDIF_CTRL1_CLR_OVERFLOW_IRQ_EN_SHIFT (15U) +#define LCDIF_CTRL1_CLR_OVERFLOW_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_OVERFLOW_IRQ_EN_SHIFT)) & LCDIF_CTRL1_CLR_OVERFLOW_IRQ_EN_MASK) +#define LCDIF_CTRL1_CLR_BYTE_PACKING_FORMAT_MASK (0xF0000U) +#define LCDIF_CTRL1_CLR_BYTE_PACKING_FORMAT_SHIFT (16U) +#define LCDIF_CTRL1_CLR_BYTE_PACKING_FORMAT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_BYTE_PACKING_FORMAT_SHIFT)) & LCDIF_CTRL1_CLR_BYTE_PACKING_FORMAT_MASK) +#define LCDIF_CTRL1_CLR_IRQ_ON_ALTERNATE_FIELDS_MASK (0x100000U) +#define LCDIF_CTRL1_CLR_IRQ_ON_ALTERNATE_FIELDS_SHIFT (20U) +#define LCDIF_CTRL1_CLR_IRQ_ON_ALTERNATE_FIELDS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_IRQ_ON_ALTERNATE_FIELDS_SHIFT)) & LCDIF_CTRL1_CLR_IRQ_ON_ALTERNATE_FIELDS_MASK) +#define LCDIF_CTRL1_CLR_FIFO_CLEAR_MASK (0x200000U) +#define LCDIF_CTRL1_CLR_FIFO_CLEAR_SHIFT (21U) +#define LCDIF_CTRL1_CLR_FIFO_CLEAR(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_FIFO_CLEAR_SHIFT)) & LCDIF_CTRL1_CLR_FIFO_CLEAR_MASK) +#define LCDIF_CTRL1_CLR_START_INTERLACE_FROM_SECOND_FIELD_MASK (0x400000U) +#define LCDIF_CTRL1_CLR_START_INTERLACE_FROM_SECOND_FIELD_SHIFT (22U) +#define LCDIF_CTRL1_CLR_START_INTERLACE_FROM_SECOND_FIELD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_START_INTERLACE_FROM_SECOND_FIELD_SHIFT)) & LCDIF_CTRL1_CLR_START_INTERLACE_FROM_SECOND_FIELD_MASK) +#define LCDIF_CTRL1_CLR_INTERLACE_FIELDS_MASK (0x800000U) +#define LCDIF_CTRL1_CLR_INTERLACE_FIELDS_SHIFT (23U) +#define LCDIF_CTRL1_CLR_INTERLACE_FIELDS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_INTERLACE_FIELDS_SHIFT)) & LCDIF_CTRL1_CLR_INTERLACE_FIELDS_MASK) +#define LCDIF_CTRL1_CLR_RECOVER_ON_UNDERFLOW_MASK (0x1000000U) +#define LCDIF_CTRL1_CLR_RECOVER_ON_UNDERFLOW_SHIFT (24U) +#define LCDIF_CTRL1_CLR_RECOVER_ON_UNDERFLOW(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_RECOVER_ON_UNDERFLOW_SHIFT)) & LCDIF_CTRL1_CLR_RECOVER_ON_UNDERFLOW_MASK) +#define LCDIF_CTRL1_CLR_BM_ERROR_IRQ_MASK (0x2000000U) +#define LCDIF_CTRL1_CLR_BM_ERROR_IRQ_SHIFT (25U) +/*! BM_ERROR_IRQ + * 0b0..No Interrupt Request Pending. + * 0b1..Interrupt Request Pending. + */ +#define LCDIF_CTRL1_CLR_BM_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_BM_ERROR_IRQ_SHIFT)) & LCDIF_CTRL1_CLR_BM_ERROR_IRQ_MASK) +#define LCDIF_CTRL1_CLR_BM_ERROR_IRQ_EN_MASK (0x4000000U) +#define LCDIF_CTRL1_CLR_BM_ERROR_IRQ_EN_SHIFT (26U) +#define LCDIF_CTRL1_CLR_BM_ERROR_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_BM_ERROR_IRQ_EN_SHIFT)) & LCDIF_CTRL1_CLR_BM_ERROR_IRQ_EN_MASK) +#define LCDIF_CTRL1_CLR_CS_OUT_SELECT_MASK (0x40000000U) +#define LCDIF_CTRL1_CLR_CS_OUT_SELECT_SHIFT (30U) +#define LCDIF_CTRL1_CLR_CS_OUT_SELECT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_CS_OUT_SELECT_SHIFT)) & LCDIF_CTRL1_CLR_CS_OUT_SELECT_MASK) +#define LCDIF_CTRL1_CLR_IMAGE_DATA_SELECT_MASK (0x80000000U) +#define LCDIF_CTRL1_CLR_IMAGE_DATA_SELECT_SHIFT (31U) +#define LCDIF_CTRL1_CLR_IMAGE_DATA_SELECT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_IMAGE_DATA_SELECT_SHIFT)) & LCDIF_CTRL1_CLR_IMAGE_DATA_SELECT_MASK) +/*! @} */ + +/*! @name CTRL1_TOG - LCDIF General Control1 Register */ +/*! @{ */ +#define LCDIF_CTRL1_TOG_RSRVD0_MASK (0xF8U) +#define LCDIF_CTRL1_TOG_RSRVD0_SHIFT (3U) +#define LCDIF_CTRL1_TOG_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_RSRVD0_SHIFT)) & LCDIF_CTRL1_TOG_RSRVD0_MASK) +#define LCDIF_CTRL1_TOG_VSYNC_EDGE_IRQ_MASK (0x100U) +#define LCDIF_CTRL1_TOG_VSYNC_EDGE_IRQ_SHIFT (8U) +/*! VSYNC_EDGE_IRQ + * 0b0..No Interrupt Request Pending. + * 0b1..Interrupt Request Pending. + */ +#define LCDIF_CTRL1_TOG_VSYNC_EDGE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_VSYNC_EDGE_IRQ_SHIFT)) & LCDIF_CTRL1_TOG_VSYNC_EDGE_IRQ_MASK) +#define LCDIF_CTRL1_TOG_CUR_FRAME_DONE_IRQ_MASK (0x200U) +#define LCDIF_CTRL1_TOG_CUR_FRAME_DONE_IRQ_SHIFT (9U) +/*! CUR_FRAME_DONE_IRQ + * 0b0..No Interrupt Request Pending. + * 0b1..Interrupt Request Pending. + */ +#define LCDIF_CTRL1_TOG_CUR_FRAME_DONE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_CUR_FRAME_DONE_IRQ_SHIFT)) & LCDIF_CTRL1_TOG_CUR_FRAME_DONE_IRQ_MASK) +#define LCDIF_CTRL1_TOG_UNDERFLOW_IRQ_MASK (0x400U) +#define LCDIF_CTRL1_TOG_UNDERFLOW_IRQ_SHIFT (10U) +/*! UNDERFLOW_IRQ + * 0b0..No Interrupt Request Pending. + * 0b1..Interrupt Request Pending. + */ +#define LCDIF_CTRL1_TOG_UNDERFLOW_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_UNDERFLOW_IRQ_SHIFT)) & LCDIF_CTRL1_TOG_UNDERFLOW_IRQ_MASK) +#define LCDIF_CTRL1_TOG_OVERFLOW_IRQ_MASK (0x800U) +#define LCDIF_CTRL1_TOG_OVERFLOW_IRQ_SHIFT (11U) +/*! OVERFLOW_IRQ + * 0b0..No Interrupt Request Pending. + * 0b1..Interrupt Request Pending. + */ +#define LCDIF_CTRL1_TOG_OVERFLOW_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_OVERFLOW_IRQ_SHIFT)) & LCDIF_CTRL1_TOG_OVERFLOW_IRQ_MASK) +#define LCDIF_CTRL1_TOG_VSYNC_EDGE_IRQ_EN_MASK (0x1000U) +#define LCDIF_CTRL1_TOG_VSYNC_EDGE_IRQ_EN_SHIFT (12U) +#define LCDIF_CTRL1_TOG_VSYNC_EDGE_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_VSYNC_EDGE_IRQ_EN_SHIFT)) & LCDIF_CTRL1_TOG_VSYNC_EDGE_IRQ_EN_MASK) +#define LCDIF_CTRL1_TOG_CUR_FRAME_DONE_IRQ_EN_MASK (0x2000U) +#define LCDIF_CTRL1_TOG_CUR_FRAME_DONE_IRQ_EN_SHIFT (13U) +#define LCDIF_CTRL1_TOG_CUR_FRAME_DONE_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_CUR_FRAME_DONE_IRQ_EN_SHIFT)) & LCDIF_CTRL1_TOG_CUR_FRAME_DONE_IRQ_EN_MASK) +#define LCDIF_CTRL1_TOG_UNDERFLOW_IRQ_EN_MASK (0x4000U) +#define LCDIF_CTRL1_TOG_UNDERFLOW_IRQ_EN_SHIFT (14U) +#define LCDIF_CTRL1_TOG_UNDERFLOW_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_UNDERFLOW_IRQ_EN_SHIFT)) & LCDIF_CTRL1_TOG_UNDERFLOW_IRQ_EN_MASK) +#define LCDIF_CTRL1_TOG_OVERFLOW_IRQ_EN_MASK (0x8000U) +#define LCDIF_CTRL1_TOG_OVERFLOW_IRQ_EN_SHIFT (15U) +#define LCDIF_CTRL1_TOG_OVERFLOW_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_OVERFLOW_IRQ_EN_SHIFT)) & LCDIF_CTRL1_TOG_OVERFLOW_IRQ_EN_MASK) +#define LCDIF_CTRL1_TOG_BYTE_PACKING_FORMAT_MASK (0xF0000U) +#define LCDIF_CTRL1_TOG_BYTE_PACKING_FORMAT_SHIFT (16U) +#define LCDIF_CTRL1_TOG_BYTE_PACKING_FORMAT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_BYTE_PACKING_FORMAT_SHIFT)) & LCDIF_CTRL1_TOG_BYTE_PACKING_FORMAT_MASK) +#define LCDIF_CTRL1_TOG_IRQ_ON_ALTERNATE_FIELDS_MASK (0x100000U) +#define LCDIF_CTRL1_TOG_IRQ_ON_ALTERNATE_FIELDS_SHIFT (20U) +#define LCDIF_CTRL1_TOG_IRQ_ON_ALTERNATE_FIELDS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_IRQ_ON_ALTERNATE_FIELDS_SHIFT)) & LCDIF_CTRL1_TOG_IRQ_ON_ALTERNATE_FIELDS_MASK) +#define LCDIF_CTRL1_TOG_FIFO_CLEAR_MASK (0x200000U) +#define LCDIF_CTRL1_TOG_FIFO_CLEAR_SHIFT (21U) +#define LCDIF_CTRL1_TOG_FIFO_CLEAR(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_FIFO_CLEAR_SHIFT)) & LCDIF_CTRL1_TOG_FIFO_CLEAR_MASK) +#define LCDIF_CTRL1_TOG_START_INTERLACE_FROM_SECOND_FIELD_MASK (0x400000U) +#define LCDIF_CTRL1_TOG_START_INTERLACE_FROM_SECOND_FIELD_SHIFT (22U) +#define LCDIF_CTRL1_TOG_START_INTERLACE_FROM_SECOND_FIELD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_START_INTERLACE_FROM_SECOND_FIELD_SHIFT)) & LCDIF_CTRL1_TOG_START_INTERLACE_FROM_SECOND_FIELD_MASK) +#define LCDIF_CTRL1_TOG_INTERLACE_FIELDS_MASK (0x800000U) +#define LCDIF_CTRL1_TOG_INTERLACE_FIELDS_SHIFT (23U) +#define LCDIF_CTRL1_TOG_INTERLACE_FIELDS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_INTERLACE_FIELDS_SHIFT)) & LCDIF_CTRL1_TOG_INTERLACE_FIELDS_MASK) +#define LCDIF_CTRL1_TOG_RECOVER_ON_UNDERFLOW_MASK (0x1000000U) +#define LCDIF_CTRL1_TOG_RECOVER_ON_UNDERFLOW_SHIFT (24U) +#define LCDIF_CTRL1_TOG_RECOVER_ON_UNDERFLOW(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_RECOVER_ON_UNDERFLOW_SHIFT)) & LCDIF_CTRL1_TOG_RECOVER_ON_UNDERFLOW_MASK) +#define LCDIF_CTRL1_TOG_BM_ERROR_IRQ_MASK (0x2000000U) +#define LCDIF_CTRL1_TOG_BM_ERROR_IRQ_SHIFT (25U) +/*! BM_ERROR_IRQ + * 0b0..No Interrupt Request Pending. + * 0b1..Interrupt Request Pending. + */ +#define LCDIF_CTRL1_TOG_BM_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_BM_ERROR_IRQ_SHIFT)) & LCDIF_CTRL1_TOG_BM_ERROR_IRQ_MASK) +#define LCDIF_CTRL1_TOG_BM_ERROR_IRQ_EN_MASK (0x4000000U) +#define LCDIF_CTRL1_TOG_BM_ERROR_IRQ_EN_SHIFT (26U) +#define LCDIF_CTRL1_TOG_BM_ERROR_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_BM_ERROR_IRQ_EN_SHIFT)) & LCDIF_CTRL1_TOG_BM_ERROR_IRQ_EN_MASK) +#define LCDIF_CTRL1_TOG_CS_OUT_SELECT_MASK (0x40000000U) +#define LCDIF_CTRL1_TOG_CS_OUT_SELECT_SHIFT (30U) +#define LCDIF_CTRL1_TOG_CS_OUT_SELECT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_CS_OUT_SELECT_SHIFT)) & LCDIF_CTRL1_TOG_CS_OUT_SELECT_MASK) +#define LCDIF_CTRL1_TOG_IMAGE_DATA_SELECT_MASK (0x80000000U) +#define LCDIF_CTRL1_TOG_IMAGE_DATA_SELECT_SHIFT (31U) +#define LCDIF_CTRL1_TOG_IMAGE_DATA_SELECT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_IMAGE_DATA_SELECT_SHIFT)) & LCDIF_CTRL1_TOG_IMAGE_DATA_SELECT_MASK) +/*! @} */ + +/*! @name CTRL2 - LCDIF General Control2 Register */ +/*! @{ */ +#define LCDIF_CTRL2_RSRVD0_MASK (0xFFFU) +#define LCDIF_CTRL2_RSRVD0_SHIFT (0U) +#define LCDIF_CTRL2_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_RSRVD0_SHIFT)) & LCDIF_CTRL2_RSRVD0_MASK) +#define LCDIF_CTRL2_EVEN_LINE_PATTERN_MASK (0x7000U) +#define LCDIF_CTRL2_EVEN_LINE_PATTERN_SHIFT (12U) +/*! EVEN_LINE_PATTERN + * 0b000..RGB + * 0b001..RBG + * 0b010..GBR + * 0b011..GRB + * 0b100..BRG + * 0b101..BGR + */ +#define LCDIF_CTRL2_EVEN_LINE_PATTERN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_EVEN_LINE_PATTERN_SHIFT)) & LCDIF_CTRL2_EVEN_LINE_PATTERN_MASK) +#define LCDIF_CTRL2_RSRVD3_MASK (0x8000U) +#define LCDIF_CTRL2_RSRVD3_SHIFT (15U) +#define LCDIF_CTRL2_RSRVD3(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_RSRVD3_SHIFT)) & LCDIF_CTRL2_RSRVD3_MASK) +#define LCDIF_CTRL2_ODD_LINE_PATTERN_MASK (0x70000U) +#define LCDIF_CTRL2_ODD_LINE_PATTERN_SHIFT (16U) +/*! ODD_LINE_PATTERN + * 0b000..RGB + * 0b001..RBG + * 0b010..GBR + * 0b011..GRB + * 0b100..BRG + * 0b101..BGR + */ +#define LCDIF_CTRL2_ODD_LINE_PATTERN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_ODD_LINE_PATTERN_SHIFT)) & LCDIF_CTRL2_ODD_LINE_PATTERN_MASK) +#define LCDIF_CTRL2_RSRVD4_MASK (0x80000U) +#define LCDIF_CTRL2_RSRVD4_SHIFT (19U) +#define LCDIF_CTRL2_RSRVD4(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_RSRVD4_SHIFT)) & LCDIF_CTRL2_RSRVD4_MASK) +#define LCDIF_CTRL2_BURST_LEN_8_MASK (0x100000U) +#define LCDIF_CTRL2_BURST_LEN_8_SHIFT (20U) +#define LCDIF_CTRL2_BURST_LEN_8(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_BURST_LEN_8_SHIFT)) & LCDIF_CTRL2_BURST_LEN_8_MASK) +#define LCDIF_CTRL2_OUTSTANDING_REQS_MASK (0xE00000U) +#define LCDIF_CTRL2_OUTSTANDING_REQS_SHIFT (21U) +/*! OUTSTANDING_REQS + * 0b000..REQ_1 + * 0b001..REQ_2 + * 0b010..REQ_4 + * 0b011..REQ_8 + * 0b100..REQ_16 + */ +#define LCDIF_CTRL2_OUTSTANDING_REQS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_OUTSTANDING_REQS_SHIFT)) & LCDIF_CTRL2_OUTSTANDING_REQS_MASK) +#define LCDIF_CTRL2_RSRVD5_MASK (0xFF000000U) +#define LCDIF_CTRL2_RSRVD5_SHIFT (24U) +#define LCDIF_CTRL2_RSRVD5(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_RSRVD5_SHIFT)) & LCDIF_CTRL2_RSRVD5_MASK) +/*! @} */ + +/*! @name CTRL2_SET - LCDIF General Control2 Register */ +/*! @{ */ +#define LCDIF_CTRL2_SET_RSRVD0_MASK (0xFFFU) +#define LCDIF_CTRL2_SET_RSRVD0_SHIFT (0U) +#define LCDIF_CTRL2_SET_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_SET_RSRVD0_SHIFT)) & LCDIF_CTRL2_SET_RSRVD0_MASK) +#define LCDIF_CTRL2_SET_EVEN_LINE_PATTERN_MASK (0x7000U) +#define LCDIF_CTRL2_SET_EVEN_LINE_PATTERN_SHIFT (12U) +/*! EVEN_LINE_PATTERN + * 0b000..RGB + * 0b001..RBG + * 0b010..GBR + * 0b011..GRB + * 0b100..BRG + * 0b101..BGR + */ +#define LCDIF_CTRL2_SET_EVEN_LINE_PATTERN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_SET_EVEN_LINE_PATTERN_SHIFT)) & LCDIF_CTRL2_SET_EVEN_LINE_PATTERN_MASK) +#define LCDIF_CTRL2_SET_RSRVD3_MASK (0x8000U) +#define LCDIF_CTRL2_SET_RSRVD3_SHIFT (15U) +#define LCDIF_CTRL2_SET_RSRVD3(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_SET_RSRVD3_SHIFT)) & LCDIF_CTRL2_SET_RSRVD3_MASK) +#define LCDIF_CTRL2_SET_ODD_LINE_PATTERN_MASK (0x70000U) +#define LCDIF_CTRL2_SET_ODD_LINE_PATTERN_SHIFT (16U) +/*! ODD_LINE_PATTERN + * 0b000..RGB + * 0b001..RBG + * 0b010..GBR + * 0b011..GRB + * 0b100..BRG + * 0b101..BGR + */ +#define LCDIF_CTRL2_SET_ODD_LINE_PATTERN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_SET_ODD_LINE_PATTERN_SHIFT)) & LCDIF_CTRL2_SET_ODD_LINE_PATTERN_MASK) +#define LCDIF_CTRL2_SET_RSRVD4_MASK (0x80000U) +#define LCDIF_CTRL2_SET_RSRVD4_SHIFT (19U) +#define LCDIF_CTRL2_SET_RSRVD4(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_SET_RSRVD4_SHIFT)) & LCDIF_CTRL2_SET_RSRVD4_MASK) +#define LCDIF_CTRL2_SET_BURST_LEN_8_MASK (0x100000U) +#define LCDIF_CTRL2_SET_BURST_LEN_8_SHIFT (20U) +#define LCDIF_CTRL2_SET_BURST_LEN_8(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_SET_BURST_LEN_8_SHIFT)) & LCDIF_CTRL2_SET_BURST_LEN_8_MASK) +#define LCDIF_CTRL2_SET_OUTSTANDING_REQS_MASK (0xE00000U) +#define LCDIF_CTRL2_SET_OUTSTANDING_REQS_SHIFT (21U) +/*! OUTSTANDING_REQS + * 0b000..REQ_1 + * 0b001..REQ_2 + * 0b010..REQ_4 + * 0b011..REQ_8 + * 0b100..REQ_16 + */ +#define LCDIF_CTRL2_SET_OUTSTANDING_REQS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_SET_OUTSTANDING_REQS_SHIFT)) & LCDIF_CTRL2_SET_OUTSTANDING_REQS_MASK) +#define LCDIF_CTRL2_SET_RSRVD5_MASK (0xFF000000U) +#define LCDIF_CTRL2_SET_RSRVD5_SHIFT (24U) +#define LCDIF_CTRL2_SET_RSRVD5(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_SET_RSRVD5_SHIFT)) & LCDIF_CTRL2_SET_RSRVD5_MASK) +/*! @} */ + +/*! @name CTRL2_CLR - LCDIF General Control2 Register */ +/*! @{ */ +#define LCDIF_CTRL2_CLR_RSRVD0_MASK (0xFFFU) +#define LCDIF_CTRL2_CLR_RSRVD0_SHIFT (0U) +#define LCDIF_CTRL2_CLR_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_CLR_RSRVD0_SHIFT)) & LCDIF_CTRL2_CLR_RSRVD0_MASK) +#define LCDIF_CTRL2_CLR_EVEN_LINE_PATTERN_MASK (0x7000U) +#define LCDIF_CTRL2_CLR_EVEN_LINE_PATTERN_SHIFT (12U) +/*! EVEN_LINE_PATTERN + * 0b000..RGB + * 0b001..RBG + * 0b010..GBR + * 0b011..GRB + * 0b100..BRG + * 0b101..BGR + */ +#define LCDIF_CTRL2_CLR_EVEN_LINE_PATTERN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_CLR_EVEN_LINE_PATTERN_SHIFT)) & LCDIF_CTRL2_CLR_EVEN_LINE_PATTERN_MASK) +#define LCDIF_CTRL2_CLR_RSRVD3_MASK (0x8000U) +#define LCDIF_CTRL2_CLR_RSRVD3_SHIFT (15U) +#define LCDIF_CTRL2_CLR_RSRVD3(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_CLR_RSRVD3_SHIFT)) & LCDIF_CTRL2_CLR_RSRVD3_MASK) +#define LCDIF_CTRL2_CLR_ODD_LINE_PATTERN_MASK (0x70000U) +#define LCDIF_CTRL2_CLR_ODD_LINE_PATTERN_SHIFT (16U) +/*! ODD_LINE_PATTERN + * 0b000..RGB + * 0b001..RBG + * 0b010..GBR + * 0b011..GRB + * 0b100..BRG + * 0b101..BGR + */ +#define LCDIF_CTRL2_CLR_ODD_LINE_PATTERN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_CLR_ODD_LINE_PATTERN_SHIFT)) & LCDIF_CTRL2_CLR_ODD_LINE_PATTERN_MASK) +#define LCDIF_CTRL2_CLR_RSRVD4_MASK (0x80000U) +#define LCDIF_CTRL2_CLR_RSRVD4_SHIFT (19U) +#define LCDIF_CTRL2_CLR_RSRVD4(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_CLR_RSRVD4_SHIFT)) & LCDIF_CTRL2_CLR_RSRVD4_MASK) +#define LCDIF_CTRL2_CLR_BURST_LEN_8_MASK (0x100000U) +#define LCDIF_CTRL2_CLR_BURST_LEN_8_SHIFT (20U) +#define LCDIF_CTRL2_CLR_BURST_LEN_8(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_CLR_BURST_LEN_8_SHIFT)) & LCDIF_CTRL2_CLR_BURST_LEN_8_MASK) +#define LCDIF_CTRL2_CLR_OUTSTANDING_REQS_MASK (0xE00000U) +#define LCDIF_CTRL2_CLR_OUTSTANDING_REQS_SHIFT (21U) +/*! OUTSTANDING_REQS + * 0b000..REQ_1 + * 0b001..REQ_2 + * 0b010..REQ_4 + * 0b011..REQ_8 + * 0b100..REQ_16 + */ +#define LCDIF_CTRL2_CLR_OUTSTANDING_REQS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_CLR_OUTSTANDING_REQS_SHIFT)) & LCDIF_CTRL2_CLR_OUTSTANDING_REQS_MASK) +#define LCDIF_CTRL2_CLR_RSRVD5_MASK (0xFF000000U) +#define LCDIF_CTRL2_CLR_RSRVD5_SHIFT (24U) +#define LCDIF_CTRL2_CLR_RSRVD5(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_CLR_RSRVD5_SHIFT)) & LCDIF_CTRL2_CLR_RSRVD5_MASK) +/*! @} */ + +/*! @name CTRL2_TOG - LCDIF General Control2 Register */ +/*! @{ */ +#define LCDIF_CTRL2_TOG_RSRVD0_MASK (0xFFFU) +#define LCDIF_CTRL2_TOG_RSRVD0_SHIFT (0U) +#define LCDIF_CTRL2_TOG_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_TOG_RSRVD0_SHIFT)) & LCDIF_CTRL2_TOG_RSRVD0_MASK) +#define LCDIF_CTRL2_TOG_EVEN_LINE_PATTERN_MASK (0x7000U) +#define LCDIF_CTRL2_TOG_EVEN_LINE_PATTERN_SHIFT (12U) +/*! EVEN_LINE_PATTERN + * 0b000..RGB + * 0b001..RBG + * 0b010..GBR + * 0b011..GRB + * 0b100..BRG + * 0b101..BGR + */ +#define LCDIF_CTRL2_TOG_EVEN_LINE_PATTERN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_TOG_EVEN_LINE_PATTERN_SHIFT)) & LCDIF_CTRL2_TOG_EVEN_LINE_PATTERN_MASK) +#define LCDIF_CTRL2_TOG_RSRVD3_MASK (0x8000U) +#define LCDIF_CTRL2_TOG_RSRVD3_SHIFT (15U) +#define LCDIF_CTRL2_TOG_RSRVD3(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_TOG_RSRVD3_SHIFT)) & LCDIF_CTRL2_TOG_RSRVD3_MASK) +#define LCDIF_CTRL2_TOG_ODD_LINE_PATTERN_MASK (0x70000U) +#define LCDIF_CTRL2_TOG_ODD_LINE_PATTERN_SHIFT (16U) +/*! ODD_LINE_PATTERN + * 0b000..RGB + * 0b001..RBG + * 0b010..GBR + * 0b011..GRB + * 0b100..BRG + * 0b101..BGR + */ +#define LCDIF_CTRL2_TOG_ODD_LINE_PATTERN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_TOG_ODD_LINE_PATTERN_SHIFT)) & LCDIF_CTRL2_TOG_ODD_LINE_PATTERN_MASK) +#define LCDIF_CTRL2_TOG_RSRVD4_MASK (0x80000U) +#define LCDIF_CTRL2_TOG_RSRVD4_SHIFT (19U) +#define LCDIF_CTRL2_TOG_RSRVD4(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_TOG_RSRVD4_SHIFT)) & LCDIF_CTRL2_TOG_RSRVD4_MASK) +#define LCDIF_CTRL2_TOG_BURST_LEN_8_MASK (0x100000U) +#define LCDIF_CTRL2_TOG_BURST_LEN_8_SHIFT (20U) +#define LCDIF_CTRL2_TOG_BURST_LEN_8(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_TOG_BURST_LEN_8_SHIFT)) & LCDIF_CTRL2_TOG_BURST_LEN_8_MASK) +#define LCDIF_CTRL2_TOG_OUTSTANDING_REQS_MASK (0xE00000U) +#define LCDIF_CTRL2_TOG_OUTSTANDING_REQS_SHIFT (21U) +/*! OUTSTANDING_REQS + * 0b000..REQ_1 + * 0b001..REQ_2 + * 0b010..REQ_4 + * 0b011..REQ_8 + * 0b100..REQ_16 + */ +#define LCDIF_CTRL2_TOG_OUTSTANDING_REQS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_TOG_OUTSTANDING_REQS_SHIFT)) & LCDIF_CTRL2_TOG_OUTSTANDING_REQS_MASK) +#define LCDIF_CTRL2_TOG_RSRVD5_MASK (0xFF000000U) +#define LCDIF_CTRL2_TOG_RSRVD5_SHIFT (24U) +#define LCDIF_CTRL2_TOG_RSRVD5(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_TOG_RSRVD5_SHIFT)) & LCDIF_CTRL2_TOG_RSRVD5_MASK) +/*! @} */ + +/*! @name TRANSFER_COUNT - LCDIF Horizontal and Vertical Valid Data Count Register */ +/*! @{ */ +#define LCDIF_TRANSFER_COUNT_H_COUNT_MASK (0xFFFFU) +#define LCDIF_TRANSFER_COUNT_H_COUNT_SHIFT (0U) +#define LCDIF_TRANSFER_COUNT_H_COUNT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_TRANSFER_COUNT_H_COUNT_SHIFT)) & LCDIF_TRANSFER_COUNT_H_COUNT_MASK) +#define LCDIF_TRANSFER_COUNT_V_COUNT_MASK (0xFFFF0000U) +#define LCDIF_TRANSFER_COUNT_V_COUNT_SHIFT (16U) +#define LCDIF_TRANSFER_COUNT_V_COUNT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_TRANSFER_COUNT_V_COUNT_SHIFT)) & LCDIF_TRANSFER_COUNT_V_COUNT_MASK) +/*! @} */ + +/*! @name CUR_BUF - LCD Interface Current Buffer Address Register */ +/*! @{ */ +#define LCDIF_CUR_BUF_ADDR_MASK (0xFFFFFFFFU) +#define LCDIF_CUR_BUF_ADDR_SHIFT (0U) +#define LCDIF_CUR_BUF_ADDR(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CUR_BUF_ADDR_SHIFT)) & LCDIF_CUR_BUF_ADDR_MASK) +/*! @} */ + +/*! @name NEXT_BUF - LCD Interface Next Buffer Address Register */ +/*! @{ */ +#define LCDIF_NEXT_BUF_ADDR_MASK (0xFFFFFFFFU) +#define LCDIF_NEXT_BUF_ADDR_SHIFT (0U) +#define LCDIF_NEXT_BUF_ADDR(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_NEXT_BUF_ADDR_SHIFT)) & LCDIF_NEXT_BUF_ADDR_MASK) +/*! @} */ + +/*! @name VDCTRL0 - LCDIF VSYNC Mode and Dotclk Mode Control Register0 */ +/*! @{ */ +#define LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_MASK (0x3FFFFU) +#define LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_SHIFT (0U) +#define LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_SHIFT)) & LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_MASK) +#define LCDIF_VDCTRL0_HALF_LINE_MODE_MASK (0x40000U) +#define LCDIF_VDCTRL0_HALF_LINE_MODE_SHIFT (18U) +#define LCDIF_VDCTRL0_HALF_LINE_MODE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_HALF_LINE_MODE_SHIFT)) & LCDIF_VDCTRL0_HALF_LINE_MODE_MASK) +#define LCDIF_VDCTRL0_HALF_LINE_MASK (0x80000U) +#define LCDIF_VDCTRL0_HALF_LINE_SHIFT (19U) +#define LCDIF_VDCTRL0_HALF_LINE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_HALF_LINE_SHIFT)) & LCDIF_VDCTRL0_HALF_LINE_MASK) +#define LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_UNIT_MASK (0x100000U) +#define LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_UNIT_SHIFT (20U) +#define LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_UNIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_UNIT_SHIFT)) & LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_UNIT_MASK) +#define LCDIF_VDCTRL0_VSYNC_PERIOD_UNIT_MASK (0x200000U) +#define LCDIF_VDCTRL0_VSYNC_PERIOD_UNIT_SHIFT (21U) +#define LCDIF_VDCTRL0_VSYNC_PERIOD_UNIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_VSYNC_PERIOD_UNIT_SHIFT)) & LCDIF_VDCTRL0_VSYNC_PERIOD_UNIT_MASK) +#define LCDIF_VDCTRL0_RSRVD1_MASK (0xC00000U) +#define LCDIF_VDCTRL0_RSRVD1_SHIFT (22U) +#define LCDIF_VDCTRL0_RSRVD1(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_RSRVD1_SHIFT)) & LCDIF_VDCTRL0_RSRVD1_MASK) +#define LCDIF_VDCTRL0_ENABLE_POL_MASK (0x1000000U) +#define LCDIF_VDCTRL0_ENABLE_POL_SHIFT (24U) +#define LCDIF_VDCTRL0_ENABLE_POL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_ENABLE_POL_SHIFT)) & LCDIF_VDCTRL0_ENABLE_POL_MASK) +#define LCDIF_VDCTRL0_DOTCLK_POL_MASK (0x2000000U) +#define LCDIF_VDCTRL0_DOTCLK_POL_SHIFT (25U) +#define LCDIF_VDCTRL0_DOTCLK_POL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_DOTCLK_POL_SHIFT)) & LCDIF_VDCTRL0_DOTCLK_POL_MASK) +#define LCDIF_VDCTRL0_HSYNC_POL_MASK (0x4000000U) +#define LCDIF_VDCTRL0_HSYNC_POL_SHIFT (26U) +#define LCDIF_VDCTRL0_HSYNC_POL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_HSYNC_POL_SHIFT)) & LCDIF_VDCTRL0_HSYNC_POL_MASK) +#define LCDIF_VDCTRL0_VSYNC_POL_MASK (0x8000000U) +#define LCDIF_VDCTRL0_VSYNC_POL_SHIFT (27U) +#define LCDIF_VDCTRL0_VSYNC_POL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_VSYNC_POL_SHIFT)) & LCDIF_VDCTRL0_VSYNC_POL_MASK) +#define LCDIF_VDCTRL0_ENABLE_PRESENT_MASK (0x10000000U) +#define LCDIF_VDCTRL0_ENABLE_PRESENT_SHIFT (28U) +#define LCDIF_VDCTRL0_ENABLE_PRESENT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_ENABLE_PRESENT_SHIFT)) & LCDIF_VDCTRL0_ENABLE_PRESENT_MASK) +#define LCDIF_VDCTRL0_RSRVD2_MASK (0xE0000000U) +#define LCDIF_VDCTRL0_RSRVD2_SHIFT (29U) +#define LCDIF_VDCTRL0_RSRVD2(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_RSRVD2_SHIFT)) & LCDIF_VDCTRL0_RSRVD2_MASK) +/*! @} */ + +/*! @name VDCTRL0_SET - LCDIF VSYNC Mode and Dotclk Mode Control Register0 */ +/*! @{ */ +#define LCDIF_VDCTRL0_SET_VSYNC_PULSE_WIDTH_MASK (0x3FFFFU) +#define LCDIF_VDCTRL0_SET_VSYNC_PULSE_WIDTH_SHIFT (0U) +#define LCDIF_VDCTRL0_SET_VSYNC_PULSE_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_SET_VSYNC_PULSE_WIDTH_SHIFT)) & LCDIF_VDCTRL0_SET_VSYNC_PULSE_WIDTH_MASK) +#define LCDIF_VDCTRL0_SET_HALF_LINE_MODE_MASK (0x40000U) +#define LCDIF_VDCTRL0_SET_HALF_LINE_MODE_SHIFT (18U) +#define LCDIF_VDCTRL0_SET_HALF_LINE_MODE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_SET_HALF_LINE_MODE_SHIFT)) & LCDIF_VDCTRL0_SET_HALF_LINE_MODE_MASK) +#define LCDIF_VDCTRL0_SET_HALF_LINE_MASK (0x80000U) +#define LCDIF_VDCTRL0_SET_HALF_LINE_SHIFT (19U) +#define LCDIF_VDCTRL0_SET_HALF_LINE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_SET_HALF_LINE_SHIFT)) & LCDIF_VDCTRL0_SET_HALF_LINE_MASK) +#define LCDIF_VDCTRL0_SET_VSYNC_PULSE_WIDTH_UNIT_MASK (0x100000U) +#define LCDIF_VDCTRL0_SET_VSYNC_PULSE_WIDTH_UNIT_SHIFT (20U) +#define LCDIF_VDCTRL0_SET_VSYNC_PULSE_WIDTH_UNIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_SET_VSYNC_PULSE_WIDTH_UNIT_SHIFT)) & LCDIF_VDCTRL0_SET_VSYNC_PULSE_WIDTH_UNIT_MASK) +#define LCDIF_VDCTRL0_SET_VSYNC_PERIOD_UNIT_MASK (0x200000U) +#define LCDIF_VDCTRL0_SET_VSYNC_PERIOD_UNIT_SHIFT (21U) +#define LCDIF_VDCTRL0_SET_VSYNC_PERIOD_UNIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_SET_VSYNC_PERIOD_UNIT_SHIFT)) & LCDIF_VDCTRL0_SET_VSYNC_PERIOD_UNIT_MASK) +#define LCDIF_VDCTRL0_SET_RSRVD1_MASK (0xC00000U) +#define LCDIF_VDCTRL0_SET_RSRVD1_SHIFT (22U) +#define LCDIF_VDCTRL0_SET_RSRVD1(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_SET_RSRVD1_SHIFT)) & LCDIF_VDCTRL0_SET_RSRVD1_MASK) +#define LCDIF_VDCTRL0_SET_ENABLE_POL_MASK (0x1000000U) +#define LCDIF_VDCTRL0_SET_ENABLE_POL_SHIFT (24U) +#define LCDIF_VDCTRL0_SET_ENABLE_POL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_SET_ENABLE_POL_SHIFT)) & LCDIF_VDCTRL0_SET_ENABLE_POL_MASK) +#define LCDIF_VDCTRL0_SET_DOTCLK_POL_MASK (0x2000000U) +#define LCDIF_VDCTRL0_SET_DOTCLK_POL_SHIFT (25U) +#define LCDIF_VDCTRL0_SET_DOTCLK_POL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_SET_DOTCLK_POL_SHIFT)) & LCDIF_VDCTRL0_SET_DOTCLK_POL_MASK) +#define LCDIF_VDCTRL0_SET_HSYNC_POL_MASK (0x4000000U) +#define LCDIF_VDCTRL0_SET_HSYNC_POL_SHIFT (26U) +#define LCDIF_VDCTRL0_SET_HSYNC_POL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_SET_HSYNC_POL_SHIFT)) & LCDIF_VDCTRL0_SET_HSYNC_POL_MASK) +#define LCDIF_VDCTRL0_SET_VSYNC_POL_MASK (0x8000000U) +#define LCDIF_VDCTRL0_SET_VSYNC_POL_SHIFT (27U) +#define LCDIF_VDCTRL0_SET_VSYNC_POL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_SET_VSYNC_POL_SHIFT)) & LCDIF_VDCTRL0_SET_VSYNC_POL_MASK) +#define LCDIF_VDCTRL0_SET_ENABLE_PRESENT_MASK (0x10000000U) +#define LCDIF_VDCTRL0_SET_ENABLE_PRESENT_SHIFT (28U) +#define LCDIF_VDCTRL0_SET_ENABLE_PRESENT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_SET_ENABLE_PRESENT_SHIFT)) & LCDIF_VDCTRL0_SET_ENABLE_PRESENT_MASK) +#define LCDIF_VDCTRL0_SET_RSRVD2_MASK (0xE0000000U) +#define LCDIF_VDCTRL0_SET_RSRVD2_SHIFT (29U) +#define LCDIF_VDCTRL0_SET_RSRVD2(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_SET_RSRVD2_SHIFT)) & LCDIF_VDCTRL0_SET_RSRVD2_MASK) +/*! @} */ + +/*! @name VDCTRL0_CLR - LCDIF VSYNC Mode and Dotclk Mode Control Register0 */ +/*! @{ */ +#define LCDIF_VDCTRL0_CLR_VSYNC_PULSE_WIDTH_MASK (0x3FFFFU) +#define LCDIF_VDCTRL0_CLR_VSYNC_PULSE_WIDTH_SHIFT (0U) +#define LCDIF_VDCTRL0_CLR_VSYNC_PULSE_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_CLR_VSYNC_PULSE_WIDTH_SHIFT)) & LCDIF_VDCTRL0_CLR_VSYNC_PULSE_WIDTH_MASK) +#define LCDIF_VDCTRL0_CLR_HALF_LINE_MODE_MASK (0x40000U) +#define LCDIF_VDCTRL0_CLR_HALF_LINE_MODE_SHIFT (18U) +#define LCDIF_VDCTRL0_CLR_HALF_LINE_MODE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_CLR_HALF_LINE_MODE_SHIFT)) & LCDIF_VDCTRL0_CLR_HALF_LINE_MODE_MASK) +#define LCDIF_VDCTRL0_CLR_HALF_LINE_MASK (0x80000U) +#define LCDIF_VDCTRL0_CLR_HALF_LINE_SHIFT (19U) +#define LCDIF_VDCTRL0_CLR_HALF_LINE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_CLR_HALF_LINE_SHIFT)) & LCDIF_VDCTRL0_CLR_HALF_LINE_MASK) +#define LCDIF_VDCTRL0_CLR_VSYNC_PULSE_WIDTH_UNIT_MASK (0x100000U) +#define LCDIF_VDCTRL0_CLR_VSYNC_PULSE_WIDTH_UNIT_SHIFT (20U) +#define LCDIF_VDCTRL0_CLR_VSYNC_PULSE_WIDTH_UNIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_CLR_VSYNC_PULSE_WIDTH_UNIT_SHIFT)) & LCDIF_VDCTRL0_CLR_VSYNC_PULSE_WIDTH_UNIT_MASK) +#define LCDIF_VDCTRL0_CLR_VSYNC_PERIOD_UNIT_MASK (0x200000U) +#define LCDIF_VDCTRL0_CLR_VSYNC_PERIOD_UNIT_SHIFT (21U) +#define LCDIF_VDCTRL0_CLR_VSYNC_PERIOD_UNIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_CLR_VSYNC_PERIOD_UNIT_SHIFT)) & LCDIF_VDCTRL0_CLR_VSYNC_PERIOD_UNIT_MASK) +#define LCDIF_VDCTRL0_CLR_RSRVD1_MASK (0xC00000U) +#define LCDIF_VDCTRL0_CLR_RSRVD1_SHIFT (22U) +#define LCDIF_VDCTRL0_CLR_RSRVD1(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_CLR_RSRVD1_SHIFT)) & LCDIF_VDCTRL0_CLR_RSRVD1_MASK) +#define LCDIF_VDCTRL0_CLR_ENABLE_POL_MASK (0x1000000U) +#define LCDIF_VDCTRL0_CLR_ENABLE_POL_SHIFT (24U) +#define LCDIF_VDCTRL0_CLR_ENABLE_POL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_CLR_ENABLE_POL_SHIFT)) & LCDIF_VDCTRL0_CLR_ENABLE_POL_MASK) +#define LCDIF_VDCTRL0_CLR_DOTCLK_POL_MASK (0x2000000U) +#define LCDIF_VDCTRL0_CLR_DOTCLK_POL_SHIFT (25U) +#define LCDIF_VDCTRL0_CLR_DOTCLK_POL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_CLR_DOTCLK_POL_SHIFT)) & LCDIF_VDCTRL0_CLR_DOTCLK_POL_MASK) +#define LCDIF_VDCTRL0_CLR_HSYNC_POL_MASK (0x4000000U) +#define LCDIF_VDCTRL0_CLR_HSYNC_POL_SHIFT (26U) +#define LCDIF_VDCTRL0_CLR_HSYNC_POL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_CLR_HSYNC_POL_SHIFT)) & LCDIF_VDCTRL0_CLR_HSYNC_POL_MASK) +#define LCDIF_VDCTRL0_CLR_VSYNC_POL_MASK (0x8000000U) +#define LCDIF_VDCTRL0_CLR_VSYNC_POL_SHIFT (27U) +#define LCDIF_VDCTRL0_CLR_VSYNC_POL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_CLR_VSYNC_POL_SHIFT)) & LCDIF_VDCTRL0_CLR_VSYNC_POL_MASK) +#define LCDIF_VDCTRL0_CLR_ENABLE_PRESENT_MASK (0x10000000U) +#define LCDIF_VDCTRL0_CLR_ENABLE_PRESENT_SHIFT (28U) +#define LCDIF_VDCTRL0_CLR_ENABLE_PRESENT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_CLR_ENABLE_PRESENT_SHIFT)) & LCDIF_VDCTRL0_CLR_ENABLE_PRESENT_MASK) +#define LCDIF_VDCTRL0_CLR_RSRVD2_MASK (0xE0000000U) +#define LCDIF_VDCTRL0_CLR_RSRVD2_SHIFT (29U) +#define LCDIF_VDCTRL0_CLR_RSRVD2(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_CLR_RSRVD2_SHIFT)) & LCDIF_VDCTRL0_CLR_RSRVD2_MASK) +/*! @} */ + +/*! @name VDCTRL0_TOG - LCDIF VSYNC Mode and Dotclk Mode Control Register0 */ +/*! @{ */ +#define LCDIF_VDCTRL0_TOG_VSYNC_PULSE_WIDTH_MASK (0x3FFFFU) +#define LCDIF_VDCTRL0_TOG_VSYNC_PULSE_WIDTH_SHIFT (0U) +#define LCDIF_VDCTRL0_TOG_VSYNC_PULSE_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_TOG_VSYNC_PULSE_WIDTH_SHIFT)) & LCDIF_VDCTRL0_TOG_VSYNC_PULSE_WIDTH_MASK) +#define LCDIF_VDCTRL0_TOG_HALF_LINE_MODE_MASK (0x40000U) +#define LCDIF_VDCTRL0_TOG_HALF_LINE_MODE_SHIFT (18U) +#define LCDIF_VDCTRL0_TOG_HALF_LINE_MODE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_TOG_HALF_LINE_MODE_SHIFT)) & LCDIF_VDCTRL0_TOG_HALF_LINE_MODE_MASK) +#define LCDIF_VDCTRL0_TOG_HALF_LINE_MASK (0x80000U) +#define LCDIF_VDCTRL0_TOG_HALF_LINE_SHIFT (19U) +#define LCDIF_VDCTRL0_TOG_HALF_LINE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_TOG_HALF_LINE_SHIFT)) & LCDIF_VDCTRL0_TOG_HALF_LINE_MASK) +#define LCDIF_VDCTRL0_TOG_VSYNC_PULSE_WIDTH_UNIT_MASK (0x100000U) +#define LCDIF_VDCTRL0_TOG_VSYNC_PULSE_WIDTH_UNIT_SHIFT (20U) +#define LCDIF_VDCTRL0_TOG_VSYNC_PULSE_WIDTH_UNIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_TOG_VSYNC_PULSE_WIDTH_UNIT_SHIFT)) & LCDIF_VDCTRL0_TOG_VSYNC_PULSE_WIDTH_UNIT_MASK) +#define LCDIF_VDCTRL0_TOG_VSYNC_PERIOD_UNIT_MASK (0x200000U) +#define LCDIF_VDCTRL0_TOG_VSYNC_PERIOD_UNIT_SHIFT (21U) +#define LCDIF_VDCTRL0_TOG_VSYNC_PERIOD_UNIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_TOG_VSYNC_PERIOD_UNIT_SHIFT)) & LCDIF_VDCTRL0_TOG_VSYNC_PERIOD_UNIT_MASK) +#define LCDIF_VDCTRL0_TOG_RSRVD1_MASK (0xC00000U) +#define LCDIF_VDCTRL0_TOG_RSRVD1_SHIFT (22U) +#define LCDIF_VDCTRL0_TOG_RSRVD1(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_TOG_RSRVD1_SHIFT)) & LCDIF_VDCTRL0_TOG_RSRVD1_MASK) +#define LCDIF_VDCTRL0_TOG_ENABLE_POL_MASK (0x1000000U) +#define LCDIF_VDCTRL0_TOG_ENABLE_POL_SHIFT (24U) +#define LCDIF_VDCTRL0_TOG_ENABLE_POL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_TOG_ENABLE_POL_SHIFT)) & LCDIF_VDCTRL0_TOG_ENABLE_POL_MASK) +#define LCDIF_VDCTRL0_TOG_DOTCLK_POL_MASK (0x2000000U) +#define LCDIF_VDCTRL0_TOG_DOTCLK_POL_SHIFT (25U) +#define LCDIF_VDCTRL0_TOG_DOTCLK_POL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_TOG_DOTCLK_POL_SHIFT)) & LCDIF_VDCTRL0_TOG_DOTCLK_POL_MASK) +#define LCDIF_VDCTRL0_TOG_HSYNC_POL_MASK (0x4000000U) +#define LCDIF_VDCTRL0_TOG_HSYNC_POL_SHIFT (26U) +#define LCDIF_VDCTRL0_TOG_HSYNC_POL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_TOG_HSYNC_POL_SHIFT)) & LCDIF_VDCTRL0_TOG_HSYNC_POL_MASK) +#define LCDIF_VDCTRL0_TOG_VSYNC_POL_MASK (0x8000000U) +#define LCDIF_VDCTRL0_TOG_VSYNC_POL_SHIFT (27U) +#define LCDIF_VDCTRL0_TOG_VSYNC_POL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_TOG_VSYNC_POL_SHIFT)) & LCDIF_VDCTRL0_TOG_VSYNC_POL_MASK) +#define LCDIF_VDCTRL0_TOG_ENABLE_PRESENT_MASK (0x10000000U) +#define LCDIF_VDCTRL0_TOG_ENABLE_PRESENT_SHIFT (28U) +#define LCDIF_VDCTRL0_TOG_ENABLE_PRESENT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_TOG_ENABLE_PRESENT_SHIFT)) & LCDIF_VDCTRL0_TOG_ENABLE_PRESENT_MASK) +#define LCDIF_VDCTRL0_TOG_RSRVD2_MASK (0xE0000000U) +#define LCDIF_VDCTRL0_TOG_RSRVD2_SHIFT (29U) +#define LCDIF_VDCTRL0_TOG_RSRVD2(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_TOG_RSRVD2_SHIFT)) & LCDIF_VDCTRL0_TOG_RSRVD2_MASK) +/*! @} */ + +/*! @name VDCTRL1 - LCDIF VSYNC Mode and Dotclk Mode Control Register1 */ +/*! @{ */ +#define LCDIF_VDCTRL1_VSYNC_PERIOD_MASK (0xFFFFFFFFU) +#define LCDIF_VDCTRL1_VSYNC_PERIOD_SHIFT (0U) +#define LCDIF_VDCTRL1_VSYNC_PERIOD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL1_VSYNC_PERIOD_SHIFT)) & LCDIF_VDCTRL1_VSYNC_PERIOD_MASK) +/*! @} */ + +/*! @name VDCTRL2 - LCDIF VSYNC Mode and Dotclk Mode Control Register2 */ +/*! @{ */ +#define LCDIF_VDCTRL2_HSYNC_PERIOD_MASK (0x3FFFFU) +#define LCDIF_VDCTRL2_HSYNC_PERIOD_SHIFT (0U) +#define LCDIF_VDCTRL2_HSYNC_PERIOD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL2_HSYNC_PERIOD_SHIFT)) & LCDIF_VDCTRL2_HSYNC_PERIOD_MASK) +#define LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH_MASK (0xFFFC0000U) +#define LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH_SHIFT (18U) +#define LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH_SHIFT)) & LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH_MASK) +/*! @} */ + +/*! @name VDCTRL3 - LCDIF VSYNC Mode and Dotclk Mode Control Register3 */ +/*! @{ */ +#define LCDIF_VDCTRL3_VERTICAL_WAIT_CNT_MASK (0xFFFFU) +#define LCDIF_VDCTRL3_VERTICAL_WAIT_CNT_SHIFT (0U) +#define LCDIF_VDCTRL3_VERTICAL_WAIT_CNT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL3_VERTICAL_WAIT_CNT_SHIFT)) & LCDIF_VDCTRL3_VERTICAL_WAIT_CNT_MASK) +#define LCDIF_VDCTRL3_HORIZONTAL_WAIT_CNT_MASK (0xFFF0000U) +#define LCDIF_VDCTRL3_HORIZONTAL_WAIT_CNT_SHIFT (16U) +#define LCDIF_VDCTRL3_HORIZONTAL_WAIT_CNT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL3_HORIZONTAL_WAIT_CNT_SHIFT)) & LCDIF_VDCTRL3_HORIZONTAL_WAIT_CNT_MASK) +#define LCDIF_VDCTRL3_VSYNC_ONLY_MASK (0x10000000U) +#define LCDIF_VDCTRL3_VSYNC_ONLY_SHIFT (28U) +#define LCDIF_VDCTRL3_VSYNC_ONLY(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL3_VSYNC_ONLY_SHIFT)) & LCDIF_VDCTRL3_VSYNC_ONLY_MASK) +#define LCDIF_VDCTRL3_MUX_SYNC_SIGNALS_MASK (0x20000000U) +#define LCDIF_VDCTRL3_MUX_SYNC_SIGNALS_SHIFT (29U) +#define LCDIF_VDCTRL3_MUX_SYNC_SIGNALS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL3_MUX_SYNC_SIGNALS_SHIFT)) & LCDIF_VDCTRL3_MUX_SYNC_SIGNALS_MASK) +#define LCDIF_VDCTRL3_RSRVD0_MASK (0xC0000000U) +#define LCDIF_VDCTRL3_RSRVD0_SHIFT (30U) +#define LCDIF_VDCTRL3_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL3_RSRVD0_SHIFT)) & LCDIF_VDCTRL3_RSRVD0_MASK) +/*! @} */ + +/*! @name VDCTRL4 - LCDIF VSYNC Mode and Dotclk Mode Control Register4 */ +/*! @{ */ +#define LCDIF_VDCTRL4_DOTCLK_H_VALID_DATA_CNT_MASK (0x3FFFFU) +#define LCDIF_VDCTRL4_DOTCLK_H_VALID_DATA_CNT_SHIFT (0U) +#define LCDIF_VDCTRL4_DOTCLK_H_VALID_DATA_CNT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL4_DOTCLK_H_VALID_DATA_CNT_SHIFT)) & LCDIF_VDCTRL4_DOTCLK_H_VALID_DATA_CNT_MASK) +#define LCDIF_VDCTRL4_SYNC_SIGNALS_ON_MASK (0x40000U) +#define LCDIF_VDCTRL4_SYNC_SIGNALS_ON_SHIFT (18U) +#define LCDIF_VDCTRL4_SYNC_SIGNALS_ON(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL4_SYNC_SIGNALS_ON_SHIFT)) & LCDIF_VDCTRL4_SYNC_SIGNALS_ON_MASK) +#define LCDIF_VDCTRL4_RSRVD0_MASK (0x1FF80000U) +#define LCDIF_VDCTRL4_RSRVD0_SHIFT (19U) +#define LCDIF_VDCTRL4_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL4_RSRVD0_SHIFT)) & LCDIF_VDCTRL4_RSRVD0_MASK) +#define LCDIF_VDCTRL4_DOTCLK_DLY_SEL_MASK (0xE0000000U) +#define LCDIF_VDCTRL4_DOTCLK_DLY_SEL_SHIFT (29U) +#define LCDIF_VDCTRL4_DOTCLK_DLY_SEL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL4_DOTCLK_DLY_SEL_SHIFT)) & LCDIF_VDCTRL4_DOTCLK_DLY_SEL_MASK) +/*! @} */ + +/*! @name BM_ERROR_STAT - Bus Master Error Status Register */ +/*! @{ */ +#define LCDIF_BM_ERROR_STAT_ADDR_MASK (0xFFFFFFFFU) +#define LCDIF_BM_ERROR_STAT_ADDR_SHIFT (0U) +#define LCDIF_BM_ERROR_STAT_ADDR(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_BM_ERROR_STAT_ADDR_SHIFT)) & LCDIF_BM_ERROR_STAT_ADDR_MASK) +/*! @} */ + +/*! @name CRC_STAT - CRC Status Register */ +/*! @{ */ +#define LCDIF_CRC_STAT_CRC_VALUE_MASK (0xFFFFFFFFU) +#define LCDIF_CRC_STAT_CRC_VALUE_SHIFT (0U) +#define LCDIF_CRC_STAT_CRC_VALUE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CRC_STAT_CRC_VALUE_SHIFT)) & LCDIF_CRC_STAT_CRC_VALUE_MASK) +/*! @} */ + +/*! @name STAT - LCD Interface Status Register */ +/*! @{ */ +#define LCDIF_STAT_LFIFO_COUNT_MASK (0x1FFU) +#define LCDIF_STAT_LFIFO_COUNT_SHIFT (0U) +#define LCDIF_STAT_LFIFO_COUNT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_STAT_LFIFO_COUNT_SHIFT)) & LCDIF_STAT_LFIFO_COUNT_MASK) +#define LCDIF_STAT_RSRVD0_MASK (0x1FFFE00U) +#define LCDIF_STAT_RSRVD0_SHIFT (9U) +#define LCDIF_STAT_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_STAT_RSRVD0_SHIFT)) & LCDIF_STAT_RSRVD0_MASK) +#define LCDIF_STAT_TXFIFO_EMPTY_MASK (0x4000000U) +#define LCDIF_STAT_TXFIFO_EMPTY_SHIFT (26U) +#define LCDIF_STAT_TXFIFO_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_STAT_TXFIFO_EMPTY_SHIFT)) & LCDIF_STAT_TXFIFO_EMPTY_MASK) +#define LCDIF_STAT_TXFIFO_FULL_MASK (0x8000000U) +#define LCDIF_STAT_TXFIFO_FULL_SHIFT (27U) +#define LCDIF_STAT_TXFIFO_FULL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_STAT_TXFIFO_FULL_SHIFT)) & LCDIF_STAT_TXFIFO_FULL_MASK) +#define LCDIF_STAT_LFIFO_EMPTY_MASK (0x10000000U) +#define LCDIF_STAT_LFIFO_EMPTY_SHIFT (28U) +#define LCDIF_STAT_LFIFO_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_STAT_LFIFO_EMPTY_SHIFT)) & LCDIF_STAT_LFIFO_EMPTY_MASK) +#define LCDIF_STAT_LFIFO_FULL_MASK (0x20000000U) +#define LCDIF_STAT_LFIFO_FULL_SHIFT (29U) +#define LCDIF_STAT_LFIFO_FULL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_STAT_LFIFO_FULL_SHIFT)) & LCDIF_STAT_LFIFO_FULL_MASK) +#define LCDIF_STAT_DMA_REQ_MASK (0x40000000U) +#define LCDIF_STAT_DMA_REQ_SHIFT (30U) +#define LCDIF_STAT_DMA_REQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_STAT_DMA_REQ_SHIFT)) & LCDIF_STAT_DMA_REQ_MASK) +#define LCDIF_STAT_PRESENT_MASK (0x80000000U) +#define LCDIF_STAT_PRESENT_SHIFT (31U) +#define LCDIF_STAT_PRESENT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_STAT_PRESENT_SHIFT)) & LCDIF_STAT_PRESENT_MASK) +/*! @} */ + +/*! @name THRES - LCDIF Threshold Register */ +/*! @{ */ +#define LCDIF_THRES_PANIC_MASK (0x1FFU) +#define LCDIF_THRES_PANIC_SHIFT (0U) +#define LCDIF_THRES_PANIC(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_THRES_PANIC_SHIFT)) & LCDIF_THRES_PANIC_MASK) +#define LCDIF_THRES_RSRVD1_MASK (0xFE00U) +#define LCDIF_THRES_RSRVD1_SHIFT (9U) +#define LCDIF_THRES_RSRVD1(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_THRES_RSRVD1_SHIFT)) & LCDIF_THRES_RSRVD1_MASK) +#define LCDIF_THRES_FASTCLOCK_MASK (0x1FF0000U) +#define LCDIF_THRES_FASTCLOCK_SHIFT (16U) +#define LCDIF_THRES_FASTCLOCK(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_THRES_FASTCLOCK_SHIFT)) & LCDIF_THRES_FASTCLOCK_MASK) +#define LCDIF_THRES_RSRVD2_MASK (0xFE000000U) +#define LCDIF_THRES_RSRVD2_SHIFT (25U) +#define LCDIF_THRES_RSRVD2(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_THRES_RSRVD2_SHIFT)) & LCDIF_THRES_RSRVD2_MASK) +/*! @} */ + +/*! @name PIGEONCTRL0 - LCDIF Pigeon Mode Control0 Register */ +/*! @{ */ +#define LCDIF_PIGEONCTRL0_FD_PERIOD_MASK (0xFFFU) +#define LCDIF_PIGEONCTRL0_FD_PERIOD_SHIFT (0U) +#define LCDIF_PIGEONCTRL0_FD_PERIOD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL0_FD_PERIOD_SHIFT)) & LCDIF_PIGEONCTRL0_FD_PERIOD_MASK) +#define LCDIF_PIGEONCTRL0_LD_PERIOD_MASK (0xFFF0000U) +#define LCDIF_PIGEONCTRL0_LD_PERIOD_SHIFT (16U) +#define LCDIF_PIGEONCTRL0_LD_PERIOD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL0_LD_PERIOD_SHIFT)) & LCDIF_PIGEONCTRL0_LD_PERIOD_MASK) +/*! @} */ + +/*! @name PIGEONCTRL0_SET - LCDIF Pigeon Mode Control0 Register */ +/*! @{ */ +#define LCDIF_PIGEONCTRL0_SET_FD_PERIOD_MASK (0xFFFU) +#define LCDIF_PIGEONCTRL0_SET_FD_PERIOD_SHIFT (0U) +#define LCDIF_PIGEONCTRL0_SET_FD_PERIOD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL0_SET_FD_PERIOD_SHIFT)) & LCDIF_PIGEONCTRL0_SET_FD_PERIOD_MASK) +#define LCDIF_PIGEONCTRL0_SET_LD_PERIOD_MASK (0xFFF0000U) +#define LCDIF_PIGEONCTRL0_SET_LD_PERIOD_SHIFT (16U) +#define LCDIF_PIGEONCTRL0_SET_LD_PERIOD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL0_SET_LD_PERIOD_SHIFT)) & LCDIF_PIGEONCTRL0_SET_LD_PERIOD_MASK) +/*! @} */ + +/*! @name PIGEONCTRL0_CLR - LCDIF Pigeon Mode Control0 Register */ +/*! @{ */ +#define LCDIF_PIGEONCTRL0_CLR_FD_PERIOD_MASK (0xFFFU) +#define LCDIF_PIGEONCTRL0_CLR_FD_PERIOD_SHIFT (0U) +#define LCDIF_PIGEONCTRL0_CLR_FD_PERIOD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL0_CLR_FD_PERIOD_SHIFT)) & LCDIF_PIGEONCTRL0_CLR_FD_PERIOD_MASK) +#define LCDIF_PIGEONCTRL0_CLR_LD_PERIOD_MASK (0xFFF0000U) +#define LCDIF_PIGEONCTRL0_CLR_LD_PERIOD_SHIFT (16U) +#define LCDIF_PIGEONCTRL0_CLR_LD_PERIOD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL0_CLR_LD_PERIOD_SHIFT)) & LCDIF_PIGEONCTRL0_CLR_LD_PERIOD_MASK) +/*! @} */ + +/*! @name PIGEONCTRL0_TOG - LCDIF Pigeon Mode Control0 Register */ +/*! @{ */ +#define LCDIF_PIGEONCTRL0_TOG_FD_PERIOD_MASK (0xFFFU) +#define LCDIF_PIGEONCTRL0_TOG_FD_PERIOD_SHIFT (0U) +#define LCDIF_PIGEONCTRL0_TOG_FD_PERIOD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL0_TOG_FD_PERIOD_SHIFT)) & LCDIF_PIGEONCTRL0_TOG_FD_PERIOD_MASK) +#define LCDIF_PIGEONCTRL0_TOG_LD_PERIOD_MASK (0xFFF0000U) +#define LCDIF_PIGEONCTRL0_TOG_LD_PERIOD_SHIFT (16U) +#define LCDIF_PIGEONCTRL0_TOG_LD_PERIOD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL0_TOG_LD_PERIOD_SHIFT)) & LCDIF_PIGEONCTRL0_TOG_LD_PERIOD_MASK) +/*! @} */ + +/*! @name PIGEONCTRL1 - LCDIF Pigeon Mode Control1 Register */ +/*! @{ */ +#define LCDIF_PIGEONCTRL1_FRAME_CNT_PERIOD_MASK (0xFFFU) +#define LCDIF_PIGEONCTRL1_FRAME_CNT_PERIOD_SHIFT (0U) +#define LCDIF_PIGEONCTRL1_FRAME_CNT_PERIOD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL1_FRAME_CNT_PERIOD_SHIFT)) & LCDIF_PIGEONCTRL1_FRAME_CNT_PERIOD_MASK) +#define LCDIF_PIGEONCTRL1_FRAME_CNT_CYCLES_MASK (0xFFF0000U) +#define LCDIF_PIGEONCTRL1_FRAME_CNT_CYCLES_SHIFT (16U) +#define LCDIF_PIGEONCTRL1_FRAME_CNT_CYCLES(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL1_FRAME_CNT_CYCLES_SHIFT)) & LCDIF_PIGEONCTRL1_FRAME_CNT_CYCLES_MASK) +/*! @} */ + +/*! @name PIGEONCTRL1_SET - LCDIF Pigeon Mode Control1 Register */ +/*! @{ */ +#define LCDIF_PIGEONCTRL1_SET_FRAME_CNT_PERIOD_MASK (0xFFFU) +#define LCDIF_PIGEONCTRL1_SET_FRAME_CNT_PERIOD_SHIFT (0U) +#define LCDIF_PIGEONCTRL1_SET_FRAME_CNT_PERIOD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL1_SET_FRAME_CNT_PERIOD_SHIFT)) & LCDIF_PIGEONCTRL1_SET_FRAME_CNT_PERIOD_MASK) +#define LCDIF_PIGEONCTRL1_SET_FRAME_CNT_CYCLES_MASK (0xFFF0000U) +#define LCDIF_PIGEONCTRL1_SET_FRAME_CNT_CYCLES_SHIFT (16U) +#define LCDIF_PIGEONCTRL1_SET_FRAME_CNT_CYCLES(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL1_SET_FRAME_CNT_CYCLES_SHIFT)) & LCDIF_PIGEONCTRL1_SET_FRAME_CNT_CYCLES_MASK) +/*! @} */ + +/*! @name PIGEONCTRL1_CLR - LCDIF Pigeon Mode Control1 Register */ +/*! @{ */ +#define LCDIF_PIGEONCTRL1_CLR_FRAME_CNT_PERIOD_MASK (0xFFFU) +#define LCDIF_PIGEONCTRL1_CLR_FRAME_CNT_PERIOD_SHIFT (0U) +#define LCDIF_PIGEONCTRL1_CLR_FRAME_CNT_PERIOD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL1_CLR_FRAME_CNT_PERIOD_SHIFT)) & LCDIF_PIGEONCTRL1_CLR_FRAME_CNT_PERIOD_MASK) +#define LCDIF_PIGEONCTRL1_CLR_FRAME_CNT_CYCLES_MASK (0xFFF0000U) +#define LCDIF_PIGEONCTRL1_CLR_FRAME_CNT_CYCLES_SHIFT (16U) +#define LCDIF_PIGEONCTRL1_CLR_FRAME_CNT_CYCLES(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL1_CLR_FRAME_CNT_CYCLES_SHIFT)) & LCDIF_PIGEONCTRL1_CLR_FRAME_CNT_CYCLES_MASK) +/*! @} */ + +/*! @name PIGEONCTRL1_TOG - LCDIF Pigeon Mode Control1 Register */ +/*! @{ */ +#define LCDIF_PIGEONCTRL1_TOG_FRAME_CNT_PERIOD_MASK (0xFFFU) +#define LCDIF_PIGEONCTRL1_TOG_FRAME_CNT_PERIOD_SHIFT (0U) +#define LCDIF_PIGEONCTRL1_TOG_FRAME_CNT_PERIOD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL1_TOG_FRAME_CNT_PERIOD_SHIFT)) & LCDIF_PIGEONCTRL1_TOG_FRAME_CNT_PERIOD_MASK) +#define LCDIF_PIGEONCTRL1_TOG_FRAME_CNT_CYCLES_MASK (0xFFF0000U) +#define LCDIF_PIGEONCTRL1_TOG_FRAME_CNT_CYCLES_SHIFT (16U) +#define LCDIF_PIGEONCTRL1_TOG_FRAME_CNT_CYCLES(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL1_TOG_FRAME_CNT_CYCLES_SHIFT)) & LCDIF_PIGEONCTRL1_TOG_FRAME_CNT_CYCLES_MASK) +/*! @} */ + +/*! @name PIGEONCTRL2 - LCDIF Pigeon Mode Control2 Register */ +/*! @{ */ +#define LCDIF_PIGEONCTRL2_PIGEON_DATA_EN_MASK (0x1U) +#define LCDIF_PIGEONCTRL2_PIGEON_DATA_EN_SHIFT (0U) +#define LCDIF_PIGEONCTRL2_PIGEON_DATA_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL2_PIGEON_DATA_EN_SHIFT)) & LCDIF_PIGEONCTRL2_PIGEON_DATA_EN_MASK) +#define LCDIF_PIGEONCTRL2_PIGEON_CLK_GATE_MASK (0x2U) +#define LCDIF_PIGEONCTRL2_PIGEON_CLK_GATE_SHIFT (1U) +#define LCDIF_PIGEONCTRL2_PIGEON_CLK_GATE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL2_PIGEON_CLK_GATE_SHIFT)) & LCDIF_PIGEONCTRL2_PIGEON_CLK_GATE_MASK) +/*! @} */ + +/*! @name PIGEONCTRL2_SET - LCDIF Pigeon Mode Control2 Register */ +/*! @{ */ +#define LCDIF_PIGEONCTRL2_SET_PIGEON_DATA_EN_MASK (0x1U) +#define LCDIF_PIGEONCTRL2_SET_PIGEON_DATA_EN_SHIFT (0U) +#define LCDIF_PIGEONCTRL2_SET_PIGEON_DATA_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL2_SET_PIGEON_DATA_EN_SHIFT)) & LCDIF_PIGEONCTRL2_SET_PIGEON_DATA_EN_MASK) +#define LCDIF_PIGEONCTRL2_SET_PIGEON_CLK_GATE_MASK (0x2U) +#define LCDIF_PIGEONCTRL2_SET_PIGEON_CLK_GATE_SHIFT (1U) +#define LCDIF_PIGEONCTRL2_SET_PIGEON_CLK_GATE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL2_SET_PIGEON_CLK_GATE_SHIFT)) & LCDIF_PIGEONCTRL2_SET_PIGEON_CLK_GATE_MASK) +/*! @} */ + +/*! @name PIGEONCTRL2_CLR - LCDIF Pigeon Mode Control2 Register */ +/*! @{ */ +#define LCDIF_PIGEONCTRL2_CLR_PIGEON_DATA_EN_MASK (0x1U) +#define LCDIF_PIGEONCTRL2_CLR_PIGEON_DATA_EN_SHIFT (0U) +#define LCDIF_PIGEONCTRL2_CLR_PIGEON_DATA_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL2_CLR_PIGEON_DATA_EN_SHIFT)) & LCDIF_PIGEONCTRL2_CLR_PIGEON_DATA_EN_MASK) +#define LCDIF_PIGEONCTRL2_CLR_PIGEON_CLK_GATE_MASK (0x2U) +#define LCDIF_PIGEONCTRL2_CLR_PIGEON_CLK_GATE_SHIFT (1U) +#define LCDIF_PIGEONCTRL2_CLR_PIGEON_CLK_GATE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL2_CLR_PIGEON_CLK_GATE_SHIFT)) & LCDIF_PIGEONCTRL2_CLR_PIGEON_CLK_GATE_MASK) +/*! @} */ + +/*! @name PIGEONCTRL2_TOG - LCDIF Pigeon Mode Control2 Register */ +/*! @{ */ +#define LCDIF_PIGEONCTRL2_TOG_PIGEON_DATA_EN_MASK (0x1U) +#define LCDIF_PIGEONCTRL2_TOG_PIGEON_DATA_EN_SHIFT (0U) +#define LCDIF_PIGEONCTRL2_TOG_PIGEON_DATA_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL2_TOG_PIGEON_DATA_EN_SHIFT)) & LCDIF_PIGEONCTRL2_TOG_PIGEON_DATA_EN_MASK) +#define LCDIF_PIGEONCTRL2_TOG_PIGEON_CLK_GATE_MASK (0x2U) +#define LCDIF_PIGEONCTRL2_TOG_PIGEON_CLK_GATE_SHIFT (1U) +#define LCDIF_PIGEONCTRL2_TOG_PIGEON_CLK_GATE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL2_TOG_PIGEON_CLK_GATE_SHIFT)) & LCDIF_PIGEONCTRL2_TOG_PIGEON_CLK_GATE_MASK) +/*! @} */ + +/*! @name PIGEON_0 - Panel Interface Signal Generator Register */ +/*! @{ */ +#define LCDIF_PIGEON_0_EN_MASK (0x1U) +#define LCDIF_PIGEON_0_EN_SHIFT (0U) +#define LCDIF_PIGEON_0_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEON_0_EN_SHIFT)) & LCDIF_PIGEON_0_EN_MASK) +#define LCDIF_PIGEON_0_POL_MASK (0x2U) +#define LCDIF_PIGEON_0_POL_SHIFT (1U) +/*! POL + * 0b0..Normal Signal (Active high) + * 0b1..Inverted signal (Active low) + */ +#define LCDIF_PIGEON_0_POL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEON_0_POL_SHIFT)) & LCDIF_PIGEON_0_POL_MASK) +#define LCDIF_PIGEON_0_INC_SEL_MASK (0xCU) +#define LCDIF_PIGEON_0_INC_SEL_SHIFT (2U) +/*! INC_SEL + * 0b00..pclk + * 0b01..Line start pulse + * 0b10..Frame start pulse + * 0b11..Use another signal as tick event + */ +#define LCDIF_PIGEON_0_INC_SEL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEON_0_INC_SEL_SHIFT)) & LCDIF_PIGEON_0_INC_SEL_MASK) +#define LCDIF_PIGEON_0_OFFSET_MASK (0xF0U) +#define LCDIF_PIGEON_0_OFFSET_SHIFT (4U) +#define LCDIF_PIGEON_0_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEON_0_OFFSET_SHIFT)) & LCDIF_PIGEON_0_OFFSET_MASK) +#define LCDIF_PIGEON_0_MASK_CNT_SEL_MASK (0xF00U) +#define LCDIF_PIGEON_0_MASK_CNT_SEL_SHIFT (8U) +/*! MASK_CNT_SEL + * 0b0000..pclk counter within one hscan state + * 0b0001..pclk cycle within one hscan state + * 0b0010..line counter within one vscan state + * 0b0011..line cycle within one vscan state + * 0b0100..frame counter + * 0b0101..frame cycle + * 0b0110..horizontal counter (pclk counter within one line ) + * 0b0111..vertical counter (line counter within one frame) + */ +#define LCDIF_PIGEON_0_MASK_CNT_SEL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEON_0_MASK_CNT_SEL_SHIFT)) & LCDIF_PIGEON_0_MASK_CNT_SEL_MASK) +#define LCDIF_PIGEON_0_MASK_CNT_MASK (0xFFF000U) +#define LCDIF_PIGEON_0_MASK_CNT_SHIFT (12U) +#define LCDIF_PIGEON_0_MASK_CNT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEON_0_MASK_CNT_SHIFT)) & LCDIF_PIGEON_0_MASK_CNT_MASK) +#define LCDIF_PIGEON_0_STATE_MASK_MASK (0xFF000000U) +#define LCDIF_PIGEON_0_STATE_MASK_SHIFT (24U) +/*! STATE_MASK + * 0b00000001..FRAME SYNC + * 0b00000010..FRAME BEGIN + * 0b00000100..FRAME DATA + * 0b00001000..FRAME END + * 0b00010000..LINE SYNC + * 0b00100000..LINE BEGIN + * 0b01000000..LINE DATA + * 0b10000000..LINE END + */ +#define LCDIF_PIGEON_0_STATE_MASK(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEON_0_STATE_MASK_SHIFT)) & LCDIF_PIGEON_0_STATE_MASK_MASK) +/*! @} */ + +/* The count of LCDIF_PIGEON_0 */ +#define LCDIF_PIGEON_0_COUNT (12U) + +/*! @name PIGEON_1 - Panel Interface Signal Generator Register */ +/*! @{ */ +#define LCDIF_PIGEON_1_SET_CNT_MASK (0xFFFFU) +#define LCDIF_PIGEON_1_SET_CNT_SHIFT (0U) +/*! SET_CNT + * 0b0000000000000000..Start as active + */ +#define LCDIF_PIGEON_1_SET_CNT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEON_1_SET_CNT_SHIFT)) & LCDIF_PIGEON_1_SET_CNT_MASK) +#define LCDIF_PIGEON_1_CLR_CNT_MASK (0xFFFF0000U) +#define LCDIF_PIGEON_1_CLR_CNT_SHIFT (16U) +/*! CLR_CNT + * 0b0000000000000000..Keep active until mask off + */ +#define LCDIF_PIGEON_1_CLR_CNT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEON_1_CLR_CNT_SHIFT)) & LCDIF_PIGEON_1_CLR_CNT_MASK) +/*! @} */ + +/* The count of LCDIF_PIGEON_1 */ +#define LCDIF_PIGEON_1_COUNT (12U) + +/*! @name PIGEON_2 - Panel Interface Signal Generator Register */ +/*! @{ */ +#define LCDIF_PIGEON_2_SIG_LOGIC_MASK (0xFU) +#define LCDIF_PIGEON_2_SIG_LOGIC_SHIFT (0U) +/*! SIG_LOGIC + * 0b0000..No logic operation + * 0b0001..sigout = sig_another AND this_sig + * 0b0010..sigout = sig_another OR this_sig + * 0b0011..mask = sig_another AND other_masks + */ +#define LCDIF_PIGEON_2_SIG_LOGIC(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEON_2_SIG_LOGIC_SHIFT)) & LCDIF_PIGEON_2_SIG_LOGIC_MASK) +#define LCDIF_PIGEON_2_SIG_ANOTHER_MASK (0x1F0U) +#define LCDIF_PIGEON_2_SIG_ANOTHER_SHIFT (4U) +/*! SIG_ANOTHER + * 0b00000..Keep active until mask off + */ +#define LCDIF_PIGEON_2_SIG_ANOTHER(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEON_2_SIG_ANOTHER_SHIFT)) & LCDIF_PIGEON_2_SIG_ANOTHER_MASK) +#define LCDIF_PIGEON_2_RSVD_MASK (0xFFFFFE00U) +#define LCDIF_PIGEON_2_RSVD_SHIFT (9U) +#define LCDIF_PIGEON_2_RSVD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEON_2_RSVD_SHIFT)) & LCDIF_PIGEON_2_RSVD_MASK) +/*! @} */ + +/* The count of LCDIF_PIGEON_2 */ +#define LCDIF_PIGEON_2_COUNT (12U) + +/*! @name LUT_CTRL - Lookup Table Data Register. */ +/*! @{ */ +#define LCDIF_LUT_CTRL_LUT_BYPASS_MASK (0x1U) +#define LCDIF_LUT_CTRL_LUT_BYPASS_SHIFT (0U) +#define LCDIF_LUT_CTRL_LUT_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_LUT_CTRL_LUT_BYPASS_SHIFT)) & LCDIF_LUT_CTRL_LUT_BYPASS_MASK) +/*! @} */ + +/*! @name LUT0_ADDR - Lookup Table Control Register. */ +/*! @{ */ +#define LCDIF_LUT0_ADDR_ADDR_MASK (0xFFU) +#define LCDIF_LUT0_ADDR_ADDR_SHIFT (0U) +#define LCDIF_LUT0_ADDR_ADDR(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_LUT0_ADDR_ADDR_SHIFT)) & LCDIF_LUT0_ADDR_ADDR_MASK) +/*! @} */ + +/*! @name LUT0_DATA - Lookup Table Data Register. */ +/*! @{ */ +#define LCDIF_LUT0_DATA_DATA_MASK (0xFFFFFFFFU) +#define LCDIF_LUT0_DATA_DATA_SHIFT (0U) +#define LCDIF_LUT0_DATA_DATA(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_LUT0_DATA_DATA_SHIFT)) & LCDIF_LUT0_DATA_DATA_MASK) +/*! @} */ + +/*! @name LUT1_ADDR - Lookup Table Control Register. */ +/*! @{ */ +#define LCDIF_LUT1_ADDR_ADDR_MASK (0xFFU) +#define LCDIF_LUT1_ADDR_ADDR_SHIFT (0U) +#define LCDIF_LUT1_ADDR_ADDR(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_LUT1_ADDR_ADDR_SHIFT)) & LCDIF_LUT1_ADDR_ADDR_MASK) +/*! @} */ + +/*! @name LUT1_DATA - Lookup Table Data Register. */ +/*! @{ */ +#define LCDIF_LUT1_DATA_DATA_MASK (0xFFFFFFFFU) +#define LCDIF_LUT1_DATA_DATA_SHIFT (0U) +#define LCDIF_LUT1_DATA_DATA(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_LUT1_DATA_DATA_SHIFT)) & LCDIF_LUT1_DATA_DATA_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group LCDIF_Register_Masks */ + + +/* LCDIF - Peripheral instance base addresses */ +/** Peripheral LCDIF base address */ +#define LCDIF_BASE (0x402B8000u) +/** Peripheral LCDIF base pointer */ +#define LCDIF ((LCDIF_Type *)LCDIF_BASE) +/** Array initializer of LCDIF peripheral base addresses */ +#define LCDIF_BASE_ADDRS { LCDIF_BASE } +/** Array initializer of LCDIF peripheral base pointers */ +#define LCDIF_BASE_PTRS { LCDIF } +/** Interrupt vectors for the LCDIF peripheral type */ +#define LCDIF_IRQ0_IRQS { LCDIF_IRQn } + +/*! + * @} + */ /* end of group LCDIF_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- LPI2C Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup LPI2C_Peripheral_Access_Layer LPI2C Peripheral Access Layer + * @{ + */ + +/** LPI2C - Register Layout Typedef */ +typedef struct { + __I uint32_t VERID; /**< Version ID Register, offset: 0x0 */ + __I uint32_t PARAM; /**< Parameter Register, offset: 0x4 */ + uint8_t RESERVED_0[8]; + __IO uint32_t MCR; /**< Master Control Register, offset: 0x10 */ + __IO uint32_t MSR; /**< Master Status Register, offset: 0x14 */ + __IO uint32_t MIER; /**< Master Interrupt Enable Register, offset: 0x18 */ + __IO uint32_t MDER; /**< Master DMA Enable Register, offset: 0x1C */ + __IO uint32_t MCFGR0; /**< Master Configuration Register 0, offset: 0x20 */ + __IO uint32_t MCFGR1; /**< Master Configuration Register 1, offset: 0x24 */ + __IO uint32_t MCFGR2; /**< Master Configuration Register 2, offset: 0x28 */ + __IO uint32_t MCFGR3; /**< Master Configuration Register 3, offset: 0x2C */ + uint8_t RESERVED_1[16]; + __IO uint32_t MDMR; /**< Master Data Match Register, offset: 0x40 */ + uint8_t RESERVED_2[4]; + __IO uint32_t MCCR0; /**< Master Clock Configuration Register 0, offset: 0x48 */ + uint8_t RESERVED_3[4]; + __IO uint32_t MCCR1; /**< Master Clock Configuration Register 1, offset: 0x50 */ + uint8_t RESERVED_4[4]; + __IO uint32_t MFCR; /**< Master FIFO Control Register, offset: 0x58 */ + __I uint32_t MFSR; /**< Master FIFO Status Register, offset: 0x5C */ + __O uint32_t MTDR; /**< Master Transmit Data Register, offset: 0x60 */ + uint8_t RESERVED_5[12]; + __I uint32_t MRDR; /**< Master Receive Data Register, offset: 0x70 */ + uint8_t RESERVED_6[156]; + __IO uint32_t SCR; /**< Slave Control Register, offset: 0x110 */ + __IO uint32_t SSR; /**< Slave Status Register, offset: 0x114 */ + __IO uint32_t SIER; /**< Slave Interrupt Enable Register, offset: 0x118 */ + __IO uint32_t SDER; /**< Slave DMA Enable Register, offset: 0x11C */ + uint8_t RESERVED_7[4]; + __IO uint32_t SCFGR1; /**< Slave Configuration Register 1, offset: 0x124 */ + __IO uint32_t SCFGR2; /**< Slave Configuration Register 2, offset: 0x128 */ + uint8_t RESERVED_8[20]; + __IO uint32_t SAMR; /**< Slave Address Match Register, offset: 0x140 */ + uint8_t RESERVED_9[12]; + __I uint32_t SASR; /**< Slave Address Status Register, offset: 0x150 */ + __IO uint32_t STAR; /**< Slave Transmit ACK Register, offset: 0x154 */ + uint8_t RESERVED_10[8]; + __O uint32_t STDR; /**< Slave Transmit Data Register, offset: 0x160 */ + uint8_t RESERVED_11[12]; + __I uint32_t SRDR; /**< Slave Receive Data Register, offset: 0x170 */ +} LPI2C_Type; + +/* ---------------------------------------------------------------------------- + -- LPI2C Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup LPI2C_Register_Masks LPI2C Register Masks + * @{ + */ + +/*! @name VERID - Version ID Register */ +/*! @{ */ +#define LPI2C_VERID_FEATURE_MASK (0xFFFFU) +#define LPI2C_VERID_FEATURE_SHIFT (0U) +/*! FEATURE - Feature Specification Number + * 0b0000000000000010..Master only, with standard feature set + * 0b0000000000000011..Master and slave, with standard feature set + */ +#define LPI2C_VERID_FEATURE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_VERID_FEATURE_SHIFT)) & LPI2C_VERID_FEATURE_MASK) +#define LPI2C_VERID_MINOR_MASK (0xFF0000U) +#define LPI2C_VERID_MINOR_SHIFT (16U) +#define LPI2C_VERID_MINOR(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_VERID_MINOR_SHIFT)) & LPI2C_VERID_MINOR_MASK) +#define LPI2C_VERID_MAJOR_MASK (0xFF000000U) +#define LPI2C_VERID_MAJOR_SHIFT (24U) +#define LPI2C_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_VERID_MAJOR_SHIFT)) & LPI2C_VERID_MAJOR_MASK) +/*! @} */ + +/*! @name PARAM - Parameter Register */ +/*! @{ */ +#define LPI2C_PARAM_MTXFIFO_MASK (0xFU) +#define LPI2C_PARAM_MTXFIFO_SHIFT (0U) +#define LPI2C_PARAM_MTXFIFO(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_PARAM_MTXFIFO_SHIFT)) & LPI2C_PARAM_MTXFIFO_MASK) +#define LPI2C_PARAM_MRXFIFO_MASK (0xF00U) +#define LPI2C_PARAM_MRXFIFO_SHIFT (8U) +#define LPI2C_PARAM_MRXFIFO(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_PARAM_MRXFIFO_SHIFT)) & LPI2C_PARAM_MRXFIFO_MASK) +/*! @} */ + +/*! @name MCR - Master Control Register */ +/*! @{ */ +#define LPI2C_MCR_MEN_MASK (0x1U) +#define LPI2C_MCR_MEN_SHIFT (0U) +/*! MEN - Master Enable + * 0b0..Master logic is disabled + * 0b1..Master logic is enabled + */ +#define LPI2C_MCR_MEN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCR_MEN_SHIFT)) & LPI2C_MCR_MEN_MASK) +#define LPI2C_MCR_RST_MASK (0x2U) +#define LPI2C_MCR_RST_SHIFT (1U) +/*! RST - Software Reset + * 0b0..Master logic is not reset + * 0b1..Master logic is reset + */ +#define LPI2C_MCR_RST(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCR_RST_SHIFT)) & LPI2C_MCR_RST_MASK) +#define LPI2C_MCR_DOZEN_MASK (0x4U) +#define LPI2C_MCR_DOZEN_SHIFT (2U) +/*! DOZEN - Doze mode enable + * 0b0..Master is enabled in Doze mode + * 0b1..Master is disabled in Doze mode + */ +#define LPI2C_MCR_DOZEN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCR_DOZEN_SHIFT)) & LPI2C_MCR_DOZEN_MASK) +#define LPI2C_MCR_DBGEN_MASK (0x8U) +#define LPI2C_MCR_DBGEN_SHIFT (3U) +/*! DBGEN - Debug Enable + * 0b0..Master is disabled in debug mode + * 0b1..Master is enabled in debug mode + */ +#define LPI2C_MCR_DBGEN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCR_DBGEN_SHIFT)) & LPI2C_MCR_DBGEN_MASK) +#define LPI2C_MCR_RTF_MASK (0x100U) +#define LPI2C_MCR_RTF_SHIFT (8U) +/*! RTF - Reset Transmit FIFO + * 0b0..No effect + * 0b1..Transmit FIFO is reset + */ +#define LPI2C_MCR_RTF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCR_RTF_SHIFT)) & LPI2C_MCR_RTF_MASK) +#define LPI2C_MCR_RRF_MASK (0x200U) +#define LPI2C_MCR_RRF_SHIFT (9U) +/*! RRF - Reset Receive FIFO + * 0b0..No effect + * 0b1..Receive FIFO is reset + */ +#define LPI2C_MCR_RRF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCR_RRF_SHIFT)) & LPI2C_MCR_RRF_MASK) +/*! @} */ + +/*! @name MSR - Master Status Register */ +/*! @{ */ +#define LPI2C_MSR_TDF_MASK (0x1U) +#define LPI2C_MSR_TDF_SHIFT (0U) +/*! TDF - Transmit Data Flag + * 0b0..Transmit data is not requested + * 0b1..Transmit data is requested + */ +#define LPI2C_MSR_TDF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_TDF_SHIFT)) & LPI2C_MSR_TDF_MASK) +#define LPI2C_MSR_RDF_MASK (0x2U) +#define LPI2C_MSR_RDF_SHIFT (1U) +/*! RDF - Receive Data Flag + * 0b0..Receive Data is not ready + * 0b1..Receive data is ready + */ +#define LPI2C_MSR_RDF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_RDF_SHIFT)) & LPI2C_MSR_RDF_MASK) +#define LPI2C_MSR_EPF_MASK (0x100U) +#define LPI2C_MSR_EPF_SHIFT (8U) +/*! EPF - End Packet Flag + * 0b0..Master has not generated a STOP or Repeated START condition + * 0b1..Master has generated a STOP or Repeated START condition + */ +#define LPI2C_MSR_EPF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_EPF_SHIFT)) & LPI2C_MSR_EPF_MASK) +#define LPI2C_MSR_SDF_MASK (0x200U) +#define LPI2C_MSR_SDF_SHIFT (9U) +/*! SDF - STOP Detect Flag + * 0b0..Master has not generated a STOP condition + * 0b1..Master has generated a STOP condition + */ +#define LPI2C_MSR_SDF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_SDF_SHIFT)) & LPI2C_MSR_SDF_MASK) +#define LPI2C_MSR_NDF_MASK (0x400U) +#define LPI2C_MSR_NDF_SHIFT (10U) +/*! NDF - NACK Detect Flag + * 0b0..Unexpected NACK was not detected + * 0b1..Unexpected NACK was detected + */ +#define LPI2C_MSR_NDF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_NDF_SHIFT)) & LPI2C_MSR_NDF_MASK) +#define LPI2C_MSR_ALF_MASK (0x800U) +#define LPI2C_MSR_ALF_SHIFT (11U) +/*! ALF - Arbitration Lost Flag + * 0b0..Master has not lost arbitration + * 0b1..Master has lost arbitration + */ +#define LPI2C_MSR_ALF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_ALF_SHIFT)) & LPI2C_MSR_ALF_MASK) +#define LPI2C_MSR_FEF_MASK (0x1000U) +#define LPI2C_MSR_FEF_SHIFT (12U) +/*! FEF - FIFO Error Flag + * 0b0..No error + * 0b1..Master sending or receiving data without a START condition + */ +#define LPI2C_MSR_FEF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_FEF_SHIFT)) & LPI2C_MSR_FEF_MASK) +#define LPI2C_MSR_PLTF_MASK (0x2000U) +#define LPI2C_MSR_PLTF_SHIFT (13U) +/*! PLTF - Pin Low Timeout Flag + * 0b0..Pin low timeout has not occurred or is disabled + * 0b1..Pin low timeout has occurred + */ +#define LPI2C_MSR_PLTF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_PLTF_SHIFT)) & LPI2C_MSR_PLTF_MASK) +#define LPI2C_MSR_DMF_MASK (0x4000U) +#define LPI2C_MSR_DMF_SHIFT (14U) +/*! DMF - Data Match Flag + * 0b0..Have not received matching data + * 0b1..Have received matching data + */ +#define LPI2C_MSR_DMF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_DMF_SHIFT)) & LPI2C_MSR_DMF_MASK) +#define LPI2C_MSR_MBF_MASK (0x1000000U) +#define LPI2C_MSR_MBF_SHIFT (24U) +/*! MBF - Master Busy Flag + * 0b0..I2C Master is idle + * 0b1..I2C Master is busy + */ +#define LPI2C_MSR_MBF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_MBF_SHIFT)) & LPI2C_MSR_MBF_MASK) +#define LPI2C_MSR_BBF_MASK (0x2000000U) +#define LPI2C_MSR_BBF_SHIFT (25U) +/*! BBF - Bus Busy Flag + * 0b0..I2C Bus is idle + * 0b1..I2C Bus is busy + */ +#define LPI2C_MSR_BBF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_BBF_SHIFT)) & LPI2C_MSR_BBF_MASK) +/*! @} */ + +/*! @name MIER - Master Interrupt Enable Register */ +/*! @{ */ +#define LPI2C_MIER_TDIE_MASK (0x1U) +#define LPI2C_MIER_TDIE_SHIFT (0U) +/*! TDIE - Transmit Data Interrupt Enable + * 0b0..Disabled + * 0b1..Enabled + */ +#define LPI2C_MIER_TDIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_TDIE_SHIFT)) & LPI2C_MIER_TDIE_MASK) +#define LPI2C_MIER_RDIE_MASK (0x2U) +#define LPI2C_MIER_RDIE_SHIFT (1U) +/*! RDIE - Receive Data Interrupt Enable + * 0b0..Disabled + * 0b1..Enabled + */ +#define LPI2C_MIER_RDIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_RDIE_SHIFT)) & LPI2C_MIER_RDIE_MASK) +#define LPI2C_MIER_EPIE_MASK (0x100U) +#define LPI2C_MIER_EPIE_SHIFT (8U) +/*! EPIE - End Packet Interrupt Enable + * 0b0..Disabled + * 0b1..Enabled + */ +#define LPI2C_MIER_EPIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_EPIE_SHIFT)) & LPI2C_MIER_EPIE_MASK) +#define LPI2C_MIER_SDIE_MASK (0x200U) +#define LPI2C_MIER_SDIE_SHIFT (9U) +/*! SDIE - STOP Detect Interrupt Enable + * 0b0..Disabled + * 0b1..Enabled + */ +#define LPI2C_MIER_SDIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_SDIE_SHIFT)) & LPI2C_MIER_SDIE_MASK) +#define LPI2C_MIER_NDIE_MASK (0x400U) +#define LPI2C_MIER_NDIE_SHIFT (10U) +/*! NDIE - NACK Detect Interrupt Enable + * 0b0..Disabled + * 0b1..Enabled + */ +#define LPI2C_MIER_NDIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_NDIE_SHIFT)) & LPI2C_MIER_NDIE_MASK) +#define LPI2C_MIER_ALIE_MASK (0x800U) +#define LPI2C_MIER_ALIE_SHIFT (11U) +/*! ALIE - Arbitration Lost Interrupt Enable + * 0b0..Disabled + * 0b1..Enabled + */ +#define LPI2C_MIER_ALIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_ALIE_SHIFT)) & LPI2C_MIER_ALIE_MASK) +#define LPI2C_MIER_FEIE_MASK (0x1000U) +#define LPI2C_MIER_FEIE_SHIFT (12U) +/*! FEIE - FIFO Error Interrupt Enable + * 0b0..Enabled + * 0b1..Disabled + */ +#define LPI2C_MIER_FEIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_FEIE_SHIFT)) & LPI2C_MIER_FEIE_MASK) +#define LPI2C_MIER_PLTIE_MASK (0x2000U) +#define LPI2C_MIER_PLTIE_SHIFT (13U) +/*! PLTIE - Pin Low Timeout Interrupt Enable + * 0b0..Disabled + * 0b1..Enabled + */ +#define LPI2C_MIER_PLTIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_PLTIE_SHIFT)) & LPI2C_MIER_PLTIE_MASK) +#define LPI2C_MIER_DMIE_MASK (0x4000U) +#define LPI2C_MIER_DMIE_SHIFT (14U) +/*! DMIE - Data Match Interrupt Enable + * 0b0..Disabled + * 0b1..Enabled + */ +#define LPI2C_MIER_DMIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_DMIE_SHIFT)) & LPI2C_MIER_DMIE_MASK) +/*! @} */ + +/*! @name MDER - Master DMA Enable Register */ +/*! @{ */ +#define LPI2C_MDER_TDDE_MASK (0x1U) +#define LPI2C_MDER_TDDE_SHIFT (0U) +/*! TDDE - Transmit Data DMA Enable + * 0b0..DMA request is disabled + * 0b1..DMA request is enabled + */ +#define LPI2C_MDER_TDDE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MDER_TDDE_SHIFT)) & LPI2C_MDER_TDDE_MASK) +#define LPI2C_MDER_RDDE_MASK (0x2U) +#define LPI2C_MDER_RDDE_SHIFT (1U) +/*! RDDE - Receive Data DMA Enable + * 0b0..DMA request is disabled + * 0b1..DMA request is enabled + */ +#define LPI2C_MDER_RDDE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MDER_RDDE_SHIFT)) & LPI2C_MDER_RDDE_MASK) +/*! @} */ + +/*! @name MCFGR0 - Master Configuration Register 0 */ +/*! @{ */ +#define LPI2C_MCFGR0_HREN_MASK (0x1U) +#define LPI2C_MCFGR0_HREN_SHIFT (0U) +/*! HREN - Host Request Enable + * 0b0..Host request input is disabled + * 0b1..Host request input is enabled + */ +#define LPI2C_MCFGR0_HREN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR0_HREN_SHIFT)) & LPI2C_MCFGR0_HREN_MASK) +#define LPI2C_MCFGR0_HRPOL_MASK (0x2U) +#define LPI2C_MCFGR0_HRPOL_SHIFT (1U) +/*! HRPOL - Host Request Polarity + * 0b0..Active low + * 0b1..Active high + */ +#define LPI2C_MCFGR0_HRPOL(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR0_HRPOL_SHIFT)) & LPI2C_MCFGR0_HRPOL_MASK) +#define LPI2C_MCFGR0_HRSEL_MASK (0x4U) +#define LPI2C_MCFGR0_HRSEL_SHIFT (2U) +/*! HRSEL - Host Request Select + * 0b0..Host request input is pin HREQ + * 0b1..Host request input is input trigger + */ +#define LPI2C_MCFGR0_HRSEL(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR0_HRSEL_SHIFT)) & LPI2C_MCFGR0_HRSEL_MASK) +#define LPI2C_MCFGR0_CIRFIFO_MASK (0x100U) +#define LPI2C_MCFGR0_CIRFIFO_SHIFT (8U) +/*! CIRFIFO - Circular FIFO Enable + * 0b0..Circular FIFO is disabled + * 0b1..Circular FIFO is enabled + */ +#define LPI2C_MCFGR0_CIRFIFO(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR0_CIRFIFO_SHIFT)) & LPI2C_MCFGR0_CIRFIFO_MASK) +#define LPI2C_MCFGR0_RDMO_MASK (0x200U) +#define LPI2C_MCFGR0_RDMO_SHIFT (9U) +/*! RDMO - Receive Data Match Only + * 0b0..Received data is stored in the receive FIFO + * 0b1..Received data is discarded unless the the Data Match Flag (MSR[DMF]) is set + */ +#define LPI2C_MCFGR0_RDMO(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR0_RDMO_SHIFT)) & LPI2C_MCFGR0_RDMO_MASK) +/*! @} */ + +/*! @name MCFGR1 - Master Configuration Register 1 */ +/*! @{ */ +#define LPI2C_MCFGR1_PRESCALE_MASK (0x7U) +#define LPI2C_MCFGR1_PRESCALE_SHIFT (0U) +/*! PRESCALE - Prescaler + * 0b000..Divide by 1 + * 0b001..Divide by 2 + * 0b010..Divide by 4 + * 0b011..Divide by 8 + * 0b100..Divide by 16 + * 0b101..Divide by 32 + * 0b110..Divide by 64 + * 0b111..Divide by 128 + */ +#define LPI2C_MCFGR1_PRESCALE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR1_PRESCALE_SHIFT)) & LPI2C_MCFGR1_PRESCALE_MASK) +#define LPI2C_MCFGR1_AUTOSTOP_MASK (0x100U) +#define LPI2C_MCFGR1_AUTOSTOP_SHIFT (8U) +/*! AUTOSTOP - Automatic STOP Generation + * 0b0..No effect + * 0b1..STOP condition is automatically generated whenever the transmit FIFO is empty and the LPI2C master is busy + */ +#define LPI2C_MCFGR1_AUTOSTOP(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR1_AUTOSTOP_SHIFT)) & LPI2C_MCFGR1_AUTOSTOP_MASK) +#define LPI2C_MCFGR1_IGNACK_MASK (0x200U) +#define LPI2C_MCFGR1_IGNACK_SHIFT (9U) +/*! IGNACK - IGNACK + * 0b0..LPI2C Master will receive ACK and NACK normally + * 0b1..LPI2C Master will treat a received NACK as if it (NACK) was an ACK + */ +#define LPI2C_MCFGR1_IGNACK(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR1_IGNACK_SHIFT)) & LPI2C_MCFGR1_IGNACK_MASK) +#define LPI2C_MCFGR1_TIMECFG_MASK (0x400U) +#define LPI2C_MCFGR1_TIMECFG_SHIFT (10U) +/*! TIMECFG - Timeout Configuration + * 0b0..Pin Low Timeout Flag will set if SCL is low for longer than the configured timeout + * 0b1..Pin Low Timeout Flag will set if either SCL or SDA is low for longer than the configured timeout + */ +#define LPI2C_MCFGR1_TIMECFG(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR1_TIMECFG_SHIFT)) & LPI2C_MCFGR1_TIMECFG_MASK) +#define LPI2C_MCFGR1_MATCFG_MASK (0x70000U) +#define LPI2C_MCFGR1_MATCFG_SHIFT (16U) +/*! MATCFG - Match Configuration + * 0b000..Match is disabled + * 0b001..Reserved + * 0b010..Match is enabled (1st data word equals MATCH0 OR MATCH1) + * 0b011..Match is enabled (any data word equals MATCH0 OR MATCH1) + * 0b100..Match is enabled (1st data word equals MATCH0 AND 2nd data word equals MATCH1) + * 0b101..Match is enabled (any data word equals MATCH0 AND next data word equals MATCH1) + * 0b110..Match is enabled (1st data word AND MATCH1 equals MATCH0 AND MATCH1) + * 0b111..Match is enabled (any data word AND MATCH1 equals MATCH0 AND MATCH1) + */ +#define LPI2C_MCFGR1_MATCFG(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR1_MATCFG_SHIFT)) & LPI2C_MCFGR1_MATCFG_MASK) +#define LPI2C_MCFGR1_PINCFG_MASK (0x7000000U) +#define LPI2C_MCFGR1_PINCFG_SHIFT (24U) +/*! PINCFG - Pin Configuration + * 0b000..2-pin open drain mode + * 0b001..2-pin output only mode (ultra-fast mode) + * 0b010..2-pin push-pull mode + * 0b011..4-pin push-pull mode + * 0b100..2-pin open drain mode with separate LPI2C slave + * 0b101..2-pin output only mode (ultra-fast mode) with separate LPI2C slave + * 0b110..2-pin push-pull mode with separate LPI2C slave + * 0b111..4-pin push-pull mode (inverted outputs) + */ +#define LPI2C_MCFGR1_PINCFG(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR1_PINCFG_SHIFT)) & LPI2C_MCFGR1_PINCFG_MASK) +/*! @} */ + +/*! @name MCFGR2 - Master Configuration Register 2 */ +/*! @{ */ +#define LPI2C_MCFGR2_BUSIDLE_MASK (0xFFFU) +#define LPI2C_MCFGR2_BUSIDLE_SHIFT (0U) +#define LPI2C_MCFGR2_BUSIDLE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR2_BUSIDLE_SHIFT)) & LPI2C_MCFGR2_BUSIDLE_MASK) +#define LPI2C_MCFGR2_FILTSCL_MASK (0xF0000U) +#define LPI2C_MCFGR2_FILTSCL_SHIFT (16U) +#define LPI2C_MCFGR2_FILTSCL(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR2_FILTSCL_SHIFT)) & LPI2C_MCFGR2_FILTSCL_MASK) +#define LPI2C_MCFGR2_FILTSDA_MASK (0xF000000U) +#define LPI2C_MCFGR2_FILTSDA_SHIFT (24U) +#define LPI2C_MCFGR2_FILTSDA(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR2_FILTSDA_SHIFT)) & LPI2C_MCFGR2_FILTSDA_MASK) +/*! @} */ + +/*! @name MCFGR3 - Master Configuration Register 3 */ +/*! @{ */ +#define LPI2C_MCFGR3_PINLOW_MASK (0xFFF00U) +#define LPI2C_MCFGR3_PINLOW_SHIFT (8U) +#define LPI2C_MCFGR3_PINLOW(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR3_PINLOW_SHIFT)) & LPI2C_MCFGR3_PINLOW_MASK) +/*! @} */ + +/*! @name MDMR - Master Data Match Register */ +/*! @{ */ +#define LPI2C_MDMR_MATCH0_MASK (0xFFU) +#define LPI2C_MDMR_MATCH0_SHIFT (0U) +#define LPI2C_MDMR_MATCH0(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MDMR_MATCH0_SHIFT)) & LPI2C_MDMR_MATCH0_MASK) +#define LPI2C_MDMR_MATCH1_MASK (0xFF0000U) +#define LPI2C_MDMR_MATCH1_SHIFT (16U) +#define LPI2C_MDMR_MATCH1(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MDMR_MATCH1_SHIFT)) & LPI2C_MDMR_MATCH1_MASK) +/*! @} */ + +/*! @name MCCR0 - Master Clock Configuration Register 0 */ +/*! @{ */ +#define LPI2C_MCCR0_CLKLO_MASK (0x3FU) +#define LPI2C_MCCR0_CLKLO_SHIFT (0U) +#define LPI2C_MCCR0_CLKLO(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR0_CLKLO_SHIFT)) & LPI2C_MCCR0_CLKLO_MASK) +#define LPI2C_MCCR0_CLKHI_MASK (0x3F00U) +#define LPI2C_MCCR0_CLKHI_SHIFT (8U) +#define LPI2C_MCCR0_CLKHI(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR0_CLKHI_SHIFT)) & LPI2C_MCCR0_CLKHI_MASK) +#define LPI2C_MCCR0_SETHOLD_MASK (0x3F0000U) +#define LPI2C_MCCR0_SETHOLD_SHIFT (16U) +#define LPI2C_MCCR0_SETHOLD(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR0_SETHOLD_SHIFT)) & LPI2C_MCCR0_SETHOLD_MASK) +#define LPI2C_MCCR0_DATAVD_MASK (0x3F000000U) +#define LPI2C_MCCR0_DATAVD_SHIFT (24U) +#define LPI2C_MCCR0_DATAVD(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR0_DATAVD_SHIFT)) & LPI2C_MCCR0_DATAVD_MASK) +/*! @} */ + +/*! @name MCCR1 - Master Clock Configuration Register 1 */ +/*! @{ */ +#define LPI2C_MCCR1_CLKLO_MASK (0x3FU) +#define LPI2C_MCCR1_CLKLO_SHIFT (0U) +#define LPI2C_MCCR1_CLKLO(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR1_CLKLO_SHIFT)) & LPI2C_MCCR1_CLKLO_MASK) +#define LPI2C_MCCR1_CLKHI_MASK (0x3F00U) +#define LPI2C_MCCR1_CLKHI_SHIFT (8U) +#define LPI2C_MCCR1_CLKHI(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR1_CLKHI_SHIFT)) & LPI2C_MCCR1_CLKHI_MASK) +#define LPI2C_MCCR1_SETHOLD_MASK (0x3F0000U) +#define LPI2C_MCCR1_SETHOLD_SHIFT (16U) +#define LPI2C_MCCR1_SETHOLD(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR1_SETHOLD_SHIFT)) & LPI2C_MCCR1_SETHOLD_MASK) +#define LPI2C_MCCR1_DATAVD_MASK (0x3F000000U) +#define LPI2C_MCCR1_DATAVD_SHIFT (24U) +#define LPI2C_MCCR1_DATAVD(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR1_DATAVD_SHIFT)) & LPI2C_MCCR1_DATAVD_MASK) +/*! @} */ + +/*! @name MFCR - Master FIFO Control Register */ +/*! @{ */ +#define LPI2C_MFCR_TXWATER_MASK (0x3U) +#define LPI2C_MFCR_TXWATER_SHIFT (0U) +#define LPI2C_MFCR_TXWATER(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MFCR_TXWATER_SHIFT)) & LPI2C_MFCR_TXWATER_MASK) +#define LPI2C_MFCR_RXWATER_MASK (0x30000U) +#define LPI2C_MFCR_RXWATER_SHIFT (16U) +#define LPI2C_MFCR_RXWATER(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MFCR_RXWATER_SHIFT)) & LPI2C_MFCR_RXWATER_MASK) +/*! @} */ + +/*! @name MFSR - Master FIFO Status Register */ +/*! @{ */ +#define LPI2C_MFSR_TXCOUNT_MASK (0x7U) +#define LPI2C_MFSR_TXCOUNT_SHIFT (0U) +#define LPI2C_MFSR_TXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MFSR_TXCOUNT_SHIFT)) & LPI2C_MFSR_TXCOUNT_MASK) +#define LPI2C_MFSR_RXCOUNT_MASK (0x70000U) +#define LPI2C_MFSR_RXCOUNT_SHIFT (16U) +#define LPI2C_MFSR_RXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MFSR_RXCOUNT_SHIFT)) & LPI2C_MFSR_RXCOUNT_MASK) +/*! @} */ + +/*! @name MTDR - Master Transmit Data Register */ +/*! @{ */ +#define LPI2C_MTDR_DATA_MASK (0xFFU) +#define LPI2C_MTDR_DATA_SHIFT (0U) +#define LPI2C_MTDR_DATA(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MTDR_DATA_SHIFT)) & LPI2C_MTDR_DATA_MASK) +#define LPI2C_MTDR_CMD_MASK (0x700U) +#define LPI2C_MTDR_CMD_SHIFT (8U) +/*! CMD - Command Data + * 0b000..Transmit DATA[7:0] + * 0b001..Receive (DATA[7:0] + 1) bytes + * 0b010..Generate STOP condition + * 0b011..Receive and discard (DATA[7:0] + 1) bytes + * 0b100..Generate (repeated) START and transmit address in DATA[7:0] + * 0b101..Generate (repeated) START and transmit address in DATA[7:0]. This transfer expects a NACK to be returned. + * 0b110..Generate (repeated) START and transmit address in DATA[7:0] using high speed mode + * 0b111..Generate (repeated) START and transmit address in DATA[7:0] using high speed mode. This transfer expects a NACK to be returned. + */ +#define LPI2C_MTDR_CMD(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MTDR_CMD_SHIFT)) & LPI2C_MTDR_CMD_MASK) +/*! @} */ + +/*! @name MRDR - Master Receive Data Register */ +/*! @{ */ +#define LPI2C_MRDR_DATA_MASK (0xFFU) +#define LPI2C_MRDR_DATA_SHIFT (0U) +#define LPI2C_MRDR_DATA(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MRDR_DATA_SHIFT)) & LPI2C_MRDR_DATA_MASK) +#define LPI2C_MRDR_RXEMPTY_MASK (0x4000U) +#define LPI2C_MRDR_RXEMPTY_SHIFT (14U) +/*! RXEMPTY - RX Empty + * 0b0..Receive FIFO is not empty + * 0b1..Receive FIFO is empty + */ +#define LPI2C_MRDR_RXEMPTY(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MRDR_RXEMPTY_SHIFT)) & LPI2C_MRDR_RXEMPTY_MASK) +/*! @} */ + +/*! @name SCR - Slave Control Register */ +/*! @{ */ +#define LPI2C_SCR_SEN_MASK (0x1U) +#define LPI2C_SCR_SEN_SHIFT (0U) +/*! SEN - Slave Enable + * 0b0..I2C Slave mode is disabled + * 0b1..I2C Slave mode is enabled + */ +#define LPI2C_SCR_SEN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCR_SEN_SHIFT)) & LPI2C_SCR_SEN_MASK) +#define LPI2C_SCR_RST_MASK (0x2U) +#define LPI2C_SCR_RST_SHIFT (1U) +/*! RST - Software Reset + * 0b0..Slave mode logic is not reset + * 0b1..Slave mode logic is reset + */ +#define LPI2C_SCR_RST(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCR_RST_SHIFT)) & LPI2C_SCR_RST_MASK) +#define LPI2C_SCR_FILTEN_MASK (0x10U) +#define LPI2C_SCR_FILTEN_SHIFT (4U) +/*! FILTEN - Filter Enable + * 0b0..Disable digital filter and output delay counter for slave mode + * 0b1..Enable digital filter and output delay counter for slave mode + */ +#define LPI2C_SCR_FILTEN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCR_FILTEN_SHIFT)) & LPI2C_SCR_FILTEN_MASK) +#define LPI2C_SCR_FILTDZ_MASK (0x20U) +#define LPI2C_SCR_FILTDZ_SHIFT (5U) +/*! FILTDZ - Filter Doze Enable + * 0b0..Filter remains enabled in Doze mode + * 0b1..Filter is disabled in Doze mode + */ +#define LPI2C_SCR_FILTDZ(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCR_FILTDZ_SHIFT)) & LPI2C_SCR_FILTDZ_MASK) +#define LPI2C_SCR_RTF_MASK (0x100U) +#define LPI2C_SCR_RTF_SHIFT (8U) +/*! RTF - Reset Transmit FIFO + * 0b0..No effect + * 0b1..Transmit Data Register is now empty + */ +#define LPI2C_SCR_RTF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCR_RTF_SHIFT)) & LPI2C_SCR_RTF_MASK) +#define LPI2C_SCR_RRF_MASK (0x200U) +#define LPI2C_SCR_RRF_SHIFT (9U) +/*! RRF - Reset Receive FIFO + * 0b0..No effect + * 0b1..Receive Data Register is now empty + */ +#define LPI2C_SCR_RRF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCR_RRF_SHIFT)) & LPI2C_SCR_RRF_MASK) +/*! @} */ + +/*! @name SSR - Slave Status Register */ +/*! @{ */ +#define LPI2C_SSR_TDF_MASK (0x1U) +#define LPI2C_SSR_TDF_SHIFT (0U) +/*! TDF - Transmit Data Flag + * 0b0..Transmit data not requested + * 0b1..Transmit data is requested + */ +#define LPI2C_SSR_TDF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_TDF_SHIFT)) & LPI2C_SSR_TDF_MASK) +#define LPI2C_SSR_RDF_MASK (0x2U) +#define LPI2C_SSR_RDF_SHIFT (1U) +/*! RDF - Receive Data Flag + * 0b0..Receive data is not ready + * 0b1..Receive data is ready + */ +#define LPI2C_SSR_RDF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_RDF_SHIFT)) & LPI2C_SSR_RDF_MASK) +#define LPI2C_SSR_AVF_MASK (0x4U) +#define LPI2C_SSR_AVF_SHIFT (2U) +/*! AVF - Address Valid Flag + * 0b0..Address Status Register is not valid + * 0b1..Address Status Register is valid + */ +#define LPI2C_SSR_AVF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_AVF_SHIFT)) & LPI2C_SSR_AVF_MASK) +#define LPI2C_SSR_TAF_MASK (0x8U) +#define LPI2C_SSR_TAF_SHIFT (3U) +/*! TAF - Transmit ACK Flag + * 0b0..Transmit ACK/NACK is not required + * 0b1..Transmit ACK/NACK is required + */ +#define LPI2C_SSR_TAF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_TAF_SHIFT)) & LPI2C_SSR_TAF_MASK) +#define LPI2C_SSR_RSF_MASK (0x100U) +#define LPI2C_SSR_RSF_SHIFT (8U) +/*! RSF - Repeated Start Flag + * 0b0..Slave has not detected a Repeated START condition + * 0b1..Slave has detected a Repeated START condition + */ +#define LPI2C_SSR_RSF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_RSF_SHIFT)) & LPI2C_SSR_RSF_MASK) +#define LPI2C_SSR_SDF_MASK (0x200U) +#define LPI2C_SSR_SDF_SHIFT (9U) +/*! SDF - STOP Detect Flag + * 0b0..Slave has not detected a STOP condition + * 0b1..Slave has detected a STOP condition + */ +#define LPI2C_SSR_SDF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_SDF_SHIFT)) & LPI2C_SSR_SDF_MASK) +#define LPI2C_SSR_BEF_MASK (0x400U) +#define LPI2C_SSR_BEF_SHIFT (10U) +/*! BEF - Bit Error Flag + * 0b0..Slave has not detected a bit error + * 0b1..Slave has detected a bit error + */ +#define LPI2C_SSR_BEF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_BEF_SHIFT)) & LPI2C_SSR_BEF_MASK) +#define LPI2C_SSR_FEF_MASK (0x800U) +#define LPI2C_SSR_FEF_SHIFT (11U) +/*! FEF - FIFO Error Flag + * 0b0..FIFO underflow or overflow was not detected + * 0b1..FIFO underflow or overflow was detected + */ +#define LPI2C_SSR_FEF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_FEF_SHIFT)) & LPI2C_SSR_FEF_MASK) +#define LPI2C_SSR_AM0F_MASK (0x1000U) +#define LPI2C_SSR_AM0F_SHIFT (12U) +/*! AM0F - Address Match 0 Flag + * 0b0..Have not received an ADDR0 matching address + * 0b1..Have received an ADDR0 matching address + */ +#define LPI2C_SSR_AM0F(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_AM0F_SHIFT)) & LPI2C_SSR_AM0F_MASK) +#define LPI2C_SSR_AM1F_MASK (0x2000U) +#define LPI2C_SSR_AM1F_SHIFT (13U) +/*! AM1F - Address Match 1 Flag + * 0b0..Have not received an ADDR1 or ADDR0/ADDR1 range matching address + * 0b1..Have received an ADDR1 or ADDR0/ADDR1 range matching address + */ +#define LPI2C_SSR_AM1F(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_AM1F_SHIFT)) & LPI2C_SSR_AM1F_MASK) +#define LPI2C_SSR_GCF_MASK (0x4000U) +#define LPI2C_SSR_GCF_SHIFT (14U) +/*! GCF - General Call Flag + * 0b0..Slave has not detected the General Call Address or the General Call Address is disabled + * 0b1..Slave has detected the General Call Address + */ +#define LPI2C_SSR_GCF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_GCF_SHIFT)) & LPI2C_SSR_GCF_MASK) +#define LPI2C_SSR_SARF_MASK (0x8000U) +#define LPI2C_SSR_SARF_SHIFT (15U) +/*! SARF - SMBus Alert Response Flag + * 0b0..SMBus Alert Response is disabled or not detected + * 0b1..SMBus Alert Response is enabled and detected + */ +#define LPI2C_SSR_SARF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_SARF_SHIFT)) & LPI2C_SSR_SARF_MASK) +#define LPI2C_SSR_SBF_MASK (0x1000000U) +#define LPI2C_SSR_SBF_SHIFT (24U) +/*! SBF - Slave Busy Flag + * 0b0..I2C Slave is idle + * 0b1..I2C Slave is busy + */ +#define LPI2C_SSR_SBF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_SBF_SHIFT)) & LPI2C_SSR_SBF_MASK) +#define LPI2C_SSR_BBF_MASK (0x2000000U) +#define LPI2C_SSR_BBF_SHIFT (25U) +/*! BBF - Bus Busy Flag + * 0b0..I2C Bus is idle + * 0b1..I2C Bus is busy + */ +#define LPI2C_SSR_BBF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_BBF_SHIFT)) & LPI2C_SSR_BBF_MASK) +/*! @} */ + +/*! @name SIER - Slave Interrupt Enable Register */ +/*! @{ */ +#define LPI2C_SIER_TDIE_MASK (0x1U) +#define LPI2C_SIER_TDIE_SHIFT (0U) +/*! TDIE - Transmit Data Interrupt Enable + * 0b0..Disabled + * 0b1..Enabled + */ +#define LPI2C_SIER_TDIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_TDIE_SHIFT)) & LPI2C_SIER_TDIE_MASK) +#define LPI2C_SIER_RDIE_MASK (0x2U) +#define LPI2C_SIER_RDIE_SHIFT (1U) +/*! RDIE - Receive Data Interrupt Enable + * 0b0..Disabled + * 0b1..Enabled + */ +#define LPI2C_SIER_RDIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_RDIE_SHIFT)) & LPI2C_SIER_RDIE_MASK) +#define LPI2C_SIER_AVIE_MASK (0x4U) +#define LPI2C_SIER_AVIE_SHIFT (2U) +/*! AVIE - Address Valid Interrupt Enable + * 0b0..Disabled + * 0b1..Enabled + */ +#define LPI2C_SIER_AVIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_AVIE_SHIFT)) & LPI2C_SIER_AVIE_MASK) +#define LPI2C_SIER_TAIE_MASK (0x8U) +#define LPI2C_SIER_TAIE_SHIFT (3U) +/*! TAIE - Transmit ACK Interrupt Enable + * 0b0..Disabled + * 0b1..Enabled + */ +#define LPI2C_SIER_TAIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_TAIE_SHIFT)) & LPI2C_SIER_TAIE_MASK) +#define LPI2C_SIER_RSIE_MASK (0x100U) +#define LPI2C_SIER_RSIE_SHIFT (8U) +/*! RSIE - Repeated Start Interrupt Enable + * 0b0..Disabled + * 0b1..Enabled + */ +#define LPI2C_SIER_RSIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_RSIE_SHIFT)) & LPI2C_SIER_RSIE_MASK) +#define LPI2C_SIER_SDIE_MASK (0x200U) +#define LPI2C_SIER_SDIE_SHIFT (9U) +/*! SDIE - STOP Detect Interrupt Enable + * 0b0..Disabled + * 0b1..Enabled + */ +#define LPI2C_SIER_SDIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_SDIE_SHIFT)) & LPI2C_SIER_SDIE_MASK) +#define LPI2C_SIER_BEIE_MASK (0x400U) +#define LPI2C_SIER_BEIE_SHIFT (10U) +/*! BEIE - Bit Error Interrupt Enable + * 0b0..Disabled + * 0b1..Enabled + */ +#define LPI2C_SIER_BEIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_BEIE_SHIFT)) & LPI2C_SIER_BEIE_MASK) +#define LPI2C_SIER_FEIE_MASK (0x800U) +#define LPI2C_SIER_FEIE_SHIFT (11U) +/*! FEIE - FIFO Error Interrupt Enable + * 0b0..Disabled + * 0b1..Enabled + */ +#define LPI2C_SIER_FEIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_FEIE_SHIFT)) & LPI2C_SIER_FEIE_MASK) +#define LPI2C_SIER_AM0IE_MASK (0x1000U) +#define LPI2C_SIER_AM0IE_SHIFT (12U) +/*! AM0IE - Address Match 0 Interrupt Enable + * 0b0..Enabled + * 0b1..Disabled + */ +#define LPI2C_SIER_AM0IE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_AM0IE_SHIFT)) & LPI2C_SIER_AM0IE_MASK) +#define LPI2C_SIER_AM1F_MASK (0x2000U) +#define LPI2C_SIER_AM1F_SHIFT (13U) +/*! AM1F - Address Match 1 Interrupt Enable + * 0b0..Disabled + * 0b1..Enabled + */ +#define LPI2C_SIER_AM1F(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_AM1F_SHIFT)) & LPI2C_SIER_AM1F_MASK) +#define LPI2C_SIER_GCIE_MASK (0x4000U) +#define LPI2C_SIER_GCIE_SHIFT (14U) +/*! GCIE - General Call Interrupt Enable + * 0b0..Disabled + * 0b1..Enabled + */ +#define LPI2C_SIER_GCIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_GCIE_SHIFT)) & LPI2C_SIER_GCIE_MASK) +#define LPI2C_SIER_SARIE_MASK (0x8000U) +#define LPI2C_SIER_SARIE_SHIFT (15U) +/*! SARIE - SMBus Alert Response Interrupt Enable + * 0b0..Disabled + * 0b1..Enabled + */ +#define LPI2C_SIER_SARIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_SARIE_SHIFT)) & LPI2C_SIER_SARIE_MASK) +/*! @} */ + +/*! @name SDER - Slave DMA Enable Register */ +/*! @{ */ +#define LPI2C_SDER_TDDE_MASK (0x1U) +#define LPI2C_SDER_TDDE_SHIFT (0U) +/*! TDDE - Transmit Data DMA Enable + * 0b0..DMA request is disabled + * 0b1..DMA request is enabled + */ +#define LPI2C_SDER_TDDE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SDER_TDDE_SHIFT)) & LPI2C_SDER_TDDE_MASK) +#define LPI2C_SDER_RDDE_MASK (0x2U) +#define LPI2C_SDER_RDDE_SHIFT (1U) +/*! RDDE - Receive Data DMA Enable + * 0b0..DMA request is disabled + * 0b1..DMA request is enabled + */ +#define LPI2C_SDER_RDDE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SDER_RDDE_SHIFT)) & LPI2C_SDER_RDDE_MASK) +#define LPI2C_SDER_AVDE_MASK (0x4U) +#define LPI2C_SDER_AVDE_SHIFT (2U) +/*! AVDE - Address Valid DMA Enable + * 0b0..DMA request is disabled + * 0b1..DMA request is enabled + */ +#define LPI2C_SDER_AVDE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SDER_AVDE_SHIFT)) & LPI2C_SDER_AVDE_MASK) +/*! @} */ + +/*! @name SCFGR1 - Slave Configuration Register 1 */ +/*! @{ */ +#define LPI2C_SCFGR1_ADRSTALL_MASK (0x1U) +#define LPI2C_SCFGR1_ADRSTALL_SHIFT (0U) +/*! ADRSTALL - Address SCL Stall + * 0b0..Clock stretching is disabled + * 0b1..Clock stretching is enabled + */ +#define LPI2C_SCFGR1_ADRSTALL(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_ADRSTALL_SHIFT)) & LPI2C_SCFGR1_ADRSTALL_MASK) +#define LPI2C_SCFGR1_RXSTALL_MASK (0x2U) +#define LPI2C_SCFGR1_RXSTALL_SHIFT (1U) +/*! RXSTALL - RX SCL Stall + * 0b0..Clock stretching is disabled + * 0b1..Clock stretching is enabled + */ +#define LPI2C_SCFGR1_RXSTALL(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_RXSTALL_SHIFT)) & LPI2C_SCFGR1_RXSTALL_MASK) +#define LPI2C_SCFGR1_TXDSTALL_MASK (0x4U) +#define LPI2C_SCFGR1_TXDSTALL_SHIFT (2U) +/*! TXDSTALL - TX Data SCL Stall + * 0b0..Clock stretching is disabled + * 0b1..Clock stretching is enabled + */ +#define LPI2C_SCFGR1_TXDSTALL(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_TXDSTALL_SHIFT)) & LPI2C_SCFGR1_TXDSTALL_MASK) +#define LPI2C_SCFGR1_ACKSTALL_MASK (0x8U) +#define LPI2C_SCFGR1_ACKSTALL_SHIFT (3U) +/*! ACKSTALL - ACK SCL Stall + * 0b0..Clock stretching is disabled + * 0b1..Clock stretching is enabled + */ +#define LPI2C_SCFGR1_ACKSTALL(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_ACKSTALL_SHIFT)) & LPI2C_SCFGR1_ACKSTALL_MASK) +#define LPI2C_SCFGR1_GCEN_MASK (0x100U) +#define LPI2C_SCFGR1_GCEN_SHIFT (8U) +/*! GCEN - General Call Enable + * 0b0..General Call address is disabled + * 0b1..General Call address is enabled + */ +#define LPI2C_SCFGR1_GCEN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_GCEN_SHIFT)) & LPI2C_SCFGR1_GCEN_MASK) +#define LPI2C_SCFGR1_SAEN_MASK (0x200U) +#define LPI2C_SCFGR1_SAEN_SHIFT (9U) +/*! SAEN - SMBus Alert Enable + * 0b0..Disables match on SMBus Alert + * 0b1..Enables match on SMBus Alert + */ +#define LPI2C_SCFGR1_SAEN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_SAEN_SHIFT)) & LPI2C_SCFGR1_SAEN_MASK) +#define LPI2C_SCFGR1_TXCFG_MASK (0x400U) +#define LPI2C_SCFGR1_TXCFG_SHIFT (10U) +/*! TXCFG - Transmit Flag Configuration + * 0b0..Transmit Data Flag will only assert during a slave-transmit transfer when the Transmit Data register is empty + * 0b1..Transmit Data Flag will assert whenever the Transmit Data register is empty + */ +#define LPI2C_SCFGR1_TXCFG(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_TXCFG_SHIFT)) & LPI2C_SCFGR1_TXCFG_MASK) +#define LPI2C_SCFGR1_RXCFG_MASK (0x800U) +#define LPI2C_SCFGR1_RXCFG_SHIFT (11U) +/*! RXCFG - Receive Data Configuration + * 0b0..Reading the Receive Data register will return received data and clear the Receive Data flag (MSR[RDF]). + * 0b1..Reading the Receive Data register when the Address Valid flag (SSR[AVF])is set, will return the Address Status register and clear the Address Valid flag. Reading the Receive Data register when the Address Valid flag is clear, will return received data and clear the Receive Data flag (MSR[RDF]). + */ +#define LPI2C_SCFGR1_RXCFG(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_RXCFG_SHIFT)) & LPI2C_SCFGR1_RXCFG_MASK) +#define LPI2C_SCFGR1_IGNACK_MASK (0x1000U) +#define LPI2C_SCFGR1_IGNACK_SHIFT (12U) +/*! IGNACK - Ignore NACK + * 0b0..Slave will end transfer when NACK is detected + * 0b1..Slave will not end transfer when NACK detected + */ +#define LPI2C_SCFGR1_IGNACK(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_IGNACK_SHIFT)) & LPI2C_SCFGR1_IGNACK_MASK) +#define LPI2C_SCFGR1_HSMEN_MASK (0x2000U) +#define LPI2C_SCFGR1_HSMEN_SHIFT (13U) +/*! HSMEN - High Speed Mode Enable + * 0b0..Disables detection of HS-mode master code + * 0b1..Enables detection of HS-mode master code + */ +#define LPI2C_SCFGR1_HSMEN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_HSMEN_SHIFT)) & LPI2C_SCFGR1_HSMEN_MASK) +#define LPI2C_SCFGR1_ADDRCFG_MASK (0x70000U) +#define LPI2C_SCFGR1_ADDRCFG_SHIFT (16U) +/*! ADDRCFG - Address Configuration + * 0b000..Address match 0 (7-bit) + * 0b001..Address match 0 (10-bit) + * 0b010..Address match 0 (7-bit) or Address match 1 (7-bit) + * 0b011..Address match 0 (10-bit) or Address match 1 (10-bit) + * 0b100..Address match 0 (7-bit) or Address match 1 (10-bit) + * 0b101..Address match 0 (10-bit) or Address match 1 (7-bit) + * 0b110..From Address match 0 (7-bit) to Address match 1 (7-bit) + * 0b111..From Address match 0 (10-bit) to Address match 1 (10-bit) + */ +#define LPI2C_SCFGR1_ADDRCFG(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_ADDRCFG_SHIFT)) & LPI2C_SCFGR1_ADDRCFG_MASK) +/*! @} */ + +/*! @name SCFGR2 - Slave Configuration Register 2 */ +/*! @{ */ +#define LPI2C_SCFGR2_CLKHOLD_MASK (0xFU) +#define LPI2C_SCFGR2_CLKHOLD_SHIFT (0U) +#define LPI2C_SCFGR2_CLKHOLD(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR2_CLKHOLD_SHIFT)) & LPI2C_SCFGR2_CLKHOLD_MASK) +#define LPI2C_SCFGR2_DATAVD_MASK (0x3F00U) +#define LPI2C_SCFGR2_DATAVD_SHIFT (8U) +#define LPI2C_SCFGR2_DATAVD(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR2_DATAVD_SHIFT)) & LPI2C_SCFGR2_DATAVD_MASK) +#define LPI2C_SCFGR2_FILTSCL_MASK (0xF0000U) +#define LPI2C_SCFGR2_FILTSCL_SHIFT (16U) +#define LPI2C_SCFGR2_FILTSCL(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR2_FILTSCL_SHIFT)) & LPI2C_SCFGR2_FILTSCL_MASK) +#define LPI2C_SCFGR2_FILTSDA_MASK (0xF000000U) +#define LPI2C_SCFGR2_FILTSDA_SHIFT (24U) +#define LPI2C_SCFGR2_FILTSDA(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR2_FILTSDA_SHIFT)) & LPI2C_SCFGR2_FILTSDA_MASK) +/*! @} */ + +/*! @name SAMR - Slave Address Match Register */ +/*! @{ */ +#define LPI2C_SAMR_ADDR0_MASK (0x7FEU) +#define LPI2C_SAMR_ADDR0_SHIFT (1U) +#define LPI2C_SAMR_ADDR0(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SAMR_ADDR0_SHIFT)) & LPI2C_SAMR_ADDR0_MASK) +#define LPI2C_SAMR_ADDR1_MASK (0x7FE0000U) +#define LPI2C_SAMR_ADDR1_SHIFT (17U) +#define LPI2C_SAMR_ADDR1(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SAMR_ADDR1_SHIFT)) & LPI2C_SAMR_ADDR1_MASK) +/*! @} */ + +/*! @name SASR - Slave Address Status Register */ +/*! @{ */ +#define LPI2C_SASR_RADDR_MASK (0x7FFU) +#define LPI2C_SASR_RADDR_SHIFT (0U) +#define LPI2C_SASR_RADDR(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SASR_RADDR_SHIFT)) & LPI2C_SASR_RADDR_MASK) +#define LPI2C_SASR_ANV_MASK (0x4000U) +#define LPI2C_SASR_ANV_SHIFT (14U) +/*! ANV - Address Not Valid + * 0b0..Received Address (RADDR) is valid + * 0b1..Received Address (RADDR) is not valid + */ +#define LPI2C_SASR_ANV(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SASR_ANV_SHIFT)) & LPI2C_SASR_ANV_MASK) +/*! @} */ + +/*! @name STAR - Slave Transmit ACK Register */ +/*! @{ */ +#define LPI2C_STAR_TXNACK_MASK (0x1U) +#define LPI2C_STAR_TXNACK_SHIFT (0U) +/*! TXNACK - Transmit NACK + * 0b0..Write a Transmit ACK for each received word + * 0b1..Write a Transmit NACK for each received word + */ +#define LPI2C_STAR_TXNACK(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_STAR_TXNACK_SHIFT)) & LPI2C_STAR_TXNACK_MASK) +/*! @} */ + +/*! @name STDR - Slave Transmit Data Register */ +/*! @{ */ +#define LPI2C_STDR_DATA_MASK (0xFFU) +#define LPI2C_STDR_DATA_SHIFT (0U) +#define LPI2C_STDR_DATA(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_STDR_DATA_SHIFT)) & LPI2C_STDR_DATA_MASK) +/*! @} */ + +/*! @name SRDR - Slave Receive Data Register */ +/*! @{ */ +#define LPI2C_SRDR_DATA_MASK (0xFFU) +#define LPI2C_SRDR_DATA_SHIFT (0U) +#define LPI2C_SRDR_DATA(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SRDR_DATA_SHIFT)) & LPI2C_SRDR_DATA_MASK) +#define LPI2C_SRDR_RXEMPTY_MASK (0x4000U) +#define LPI2C_SRDR_RXEMPTY_SHIFT (14U) +/*! RXEMPTY - RX Empty + * 0b0..The Receive Data Register is not empty + * 0b1..The Receive Data Register is empty + */ +#define LPI2C_SRDR_RXEMPTY(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SRDR_RXEMPTY_SHIFT)) & LPI2C_SRDR_RXEMPTY_MASK) +#define LPI2C_SRDR_SOF_MASK (0x8000U) +#define LPI2C_SRDR_SOF_SHIFT (15U) +/*! SOF - Start Of Frame + * 0b0..Indicates this is not the first data word since a (repeated) START or STOP condition + * 0b1..Indicates this is the first data word since a (repeated) START or STOP condition + */ +#define LPI2C_SRDR_SOF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SRDR_SOF_SHIFT)) & LPI2C_SRDR_SOF_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group LPI2C_Register_Masks */ + + +/* LPI2C - Peripheral instance base addresses */ +/** Peripheral LPI2C1 base address */ +#define LPI2C1_BASE (0x403F0000u) +/** Peripheral LPI2C1 base pointer */ +#define LPI2C1 ((LPI2C_Type *)LPI2C1_BASE) +/** Peripheral LPI2C2 base address */ +#define LPI2C2_BASE (0x403F4000u) +/** Peripheral LPI2C2 base pointer */ +#define LPI2C2 ((LPI2C_Type *)LPI2C2_BASE) +/** Peripheral LPI2C3 base address */ +#define LPI2C3_BASE (0x403F8000u) +/** Peripheral LPI2C3 base pointer */ +#define LPI2C3 ((LPI2C_Type *)LPI2C3_BASE) +/** Peripheral LPI2C4 base address */ +#define LPI2C4_BASE (0x403FC000u) +/** Peripheral LPI2C4 base pointer */ +#define LPI2C4 ((LPI2C_Type *)LPI2C4_BASE) +/** Array initializer of LPI2C peripheral base addresses */ +#define LPI2C_BASE_ADDRS { 0u, LPI2C1_BASE, LPI2C2_BASE, LPI2C3_BASE, LPI2C4_BASE } +/** Array initializer of LPI2C peripheral base pointers */ +#define LPI2C_BASE_PTRS { (LPI2C_Type *)0u, LPI2C1, LPI2C2, LPI2C3, LPI2C4 } +/** Interrupt vectors for the LPI2C peripheral type */ +#define LPI2C_IRQS { NotAvail_IRQn, LPI2C1_IRQn, LPI2C2_IRQn, LPI2C3_IRQn, LPI2C4_IRQn } + +/*! + * @} + */ /* end of group LPI2C_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- LPSPI Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup LPSPI_Peripheral_Access_Layer LPSPI Peripheral Access Layer + * @{ + */ + +/** LPSPI - Register Layout Typedef */ +typedef struct { + __I uint32_t VERID; /**< Version ID Register, offset: 0x0 */ + __I uint32_t PARAM; /**< Parameter Register, offset: 0x4 */ + uint8_t RESERVED_0[8]; + __IO uint32_t CR; /**< Control Register, offset: 0x10 */ + __IO uint32_t SR; /**< Status Register, offset: 0x14 */ + __IO uint32_t IER; /**< Interrupt Enable Register, offset: 0x18 */ + __IO uint32_t DER; /**< DMA Enable Register, offset: 0x1C */ + __IO uint32_t CFGR0; /**< Configuration Register 0, offset: 0x20 */ + __IO uint32_t CFGR1; /**< Configuration Register 1, offset: 0x24 */ + uint8_t RESERVED_1[8]; + __IO uint32_t DMR0; /**< Data Match Register 0, offset: 0x30 */ + __IO uint32_t DMR1; /**< Data Match Register 1, offset: 0x34 */ + uint8_t RESERVED_2[8]; + __IO uint32_t CCR; /**< Clock Configuration Register, offset: 0x40 */ + uint8_t RESERVED_3[20]; + __IO uint32_t FCR; /**< FIFO Control Register, offset: 0x58 */ + __I uint32_t FSR; /**< FIFO Status Register, offset: 0x5C */ + __IO uint32_t TCR; /**< Transmit Command Register, offset: 0x60 */ + __O uint32_t TDR; /**< Transmit Data Register, offset: 0x64 */ + uint8_t RESERVED_4[8]; + __I uint32_t RSR; /**< Receive Status Register, offset: 0x70 */ + __I uint32_t RDR; /**< Receive Data Register, offset: 0x74 */ +} LPSPI_Type; + +/* ---------------------------------------------------------------------------- + -- LPSPI Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup LPSPI_Register_Masks LPSPI Register Masks + * @{ + */ + +/*! @name VERID - Version ID Register */ +/*! @{ */ +#define LPSPI_VERID_FEATURE_MASK (0xFFFFU) +#define LPSPI_VERID_FEATURE_SHIFT (0U) +/*! FEATURE - Module Identification Number + * 0b0000000000000100..Standard feature set supporting a 32-bit shift register. + */ +#define LPSPI_VERID_FEATURE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_VERID_FEATURE_SHIFT)) & LPSPI_VERID_FEATURE_MASK) +#define LPSPI_VERID_MINOR_MASK (0xFF0000U) +#define LPSPI_VERID_MINOR_SHIFT (16U) +#define LPSPI_VERID_MINOR(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_VERID_MINOR_SHIFT)) & LPSPI_VERID_MINOR_MASK) +#define LPSPI_VERID_MAJOR_MASK (0xFF000000U) +#define LPSPI_VERID_MAJOR_SHIFT (24U) +#define LPSPI_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_VERID_MAJOR_SHIFT)) & LPSPI_VERID_MAJOR_MASK) +/*! @} */ + +/*! @name PARAM - Parameter Register */ +/*! @{ */ +#define LPSPI_PARAM_TXFIFO_MASK (0xFFU) +#define LPSPI_PARAM_TXFIFO_SHIFT (0U) +#define LPSPI_PARAM_TXFIFO(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_PARAM_TXFIFO_SHIFT)) & LPSPI_PARAM_TXFIFO_MASK) +#define LPSPI_PARAM_RXFIFO_MASK (0xFF00U) +#define LPSPI_PARAM_RXFIFO_SHIFT (8U) +#define LPSPI_PARAM_RXFIFO(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_PARAM_RXFIFO_SHIFT)) & LPSPI_PARAM_RXFIFO_MASK) +#define LPSPI_PARAM_PCSNUM_MASK (0xFF0000U) +#define LPSPI_PARAM_PCSNUM_SHIFT (16U) +#define LPSPI_PARAM_PCSNUM(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_PARAM_PCSNUM_SHIFT)) & LPSPI_PARAM_PCSNUM_MASK) +/*! @} */ + +/*! @name CR - Control Register */ +/*! @{ */ +#define LPSPI_CR_MEN_MASK (0x1U) +#define LPSPI_CR_MEN_SHIFT (0U) +/*! MEN - Module Enable + * 0b0..Module is disabled + * 0b1..Module is enabled + */ +#define LPSPI_CR_MEN(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CR_MEN_SHIFT)) & LPSPI_CR_MEN_MASK) +#define LPSPI_CR_RST_MASK (0x2U) +#define LPSPI_CR_RST_SHIFT (1U) +/*! RST - Software Reset + * 0b0..Module is not reset + * 0b1..Module is reset + */ +#define LPSPI_CR_RST(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CR_RST_SHIFT)) & LPSPI_CR_RST_MASK) +#define LPSPI_CR_DOZEN_MASK (0x4U) +#define LPSPI_CR_DOZEN_SHIFT (2U) +/*! DOZEN - Doze mode enable + * 0b0..Module is enabled in Doze mode + * 0b1..Module is disabled in Doze mode + */ +#define LPSPI_CR_DOZEN(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CR_DOZEN_SHIFT)) & LPSPI_CR_DOZEN_MASK) +#define LPSPI_CR_DBGEN_MASK (0x8U) +#define LPSPI_CR_DBGEN_SHIFT (3U) +/*! DBGEN - Debug Enable + * 0b0..Module is disabled in debug mode + * 0b1..Module is enabled in debug mode + */ +#define LPSPI_CR_DBGEN(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CR_DBGEN_SHIFT)) & LPSPI_CR_DBGEN_MASK) +#define LPSPI_CR_RTF_MASK (0x100U) +#define LPSPI_CR_RTF_SHIFT (8U) +/*! RTF - Reset Transmit FIFO + * 0b0..No effect + * 0b1..Transmit FIFO is reset + */ +#define LPSPI_CR_RTF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CR_RTF_SHIFT)) & LPSPI_CR_RTF_MASK) +#define LPSPI_CR_RRF_MASK (0x200U) +#define LPSPI_CR_RRF_SHIFT (9U) +/*! RRF - Reset Receive FIFO + * 0b0..No effect + * 0b1..Receive FIFO is reset + */ +#define LPSPI_CR_RRF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CR_RRF_SHIFT)) & LPSPI_CR_RRF_MASK) +/*! @} */ + +/*! @name SR - Status Register */ +/*! @{ */ +#define LPSPI_SR_TDF_MASK (0x1U) +#define LPSPI_SR_TDF_SHIFT (0U) +/*! TDF - Transmit Data Flag + * 0b0..Transmit data not requested + * 0b1..Transmit data is requested + */ +#define LPSPI_SR_TDF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_TDF_SHIFT)) & LPSPI_SR_TDF_MASK) +#define LPSPI_SR_RDF_MASK (0x2U) +#define LPSPI_SR_RDF_SHIFT (1U) +/*! RDF - Receive Data Flag + * 0b0..Receive Data is not ready + * 0b1..Receive data is ready + */ +#define LPSPI_SR_RDF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_RDF_SHIFT)) & LPSPI_SR_RDF_MASK) +#define LPSPI_SR_WCF_MASK (0x100U) +#define LPSPI_SR_WCF_SHIFT (8U) +/*! WCF - Word Complete Flag + * 0b0..Transfer of a received word has not yet completed + * 0b1..Transfer of a received word has completed + */ +#define LPSPI_SR_WCF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_WCF_SHIFT)) & LPSPI_SR_WCF_MASK) +#define LPSPI_SR_FCF_MASK (0x200U) +#define LPSPI_SR_FCF_SHIFT (9U) +/*! FCF - Frame Complete Flag + * 0b0..Frame transfer has not completed + * 0b1..Frame transfer has completed + */ +#define LPSPI_SR_FCF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_FCF_SHIFT)) & LPSPI_SR_FCF_MASK) +#define LPSPI_SR_TCF_MASK (0x400U) +#define LPSPI_SR_TCF_SHIFT (10U) +/*! TCF - Transfer Complete Flag + * 0b0..All transfers have not completed + * 0b1..All transfers have completed + */ +#define LPSPI_SR_TCF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_TCF_SHIFT)) & LPSPI_SR_TCF_MASK) +#define LPSPI_SR_TEF_MASK (0x800U) +#define LPSPI_SR_TEF_SHIFT (11U) +/*! TEF - Transmit Error Flag + * 0b0..Transmit FIFO underrun has not occurred + * 0b1..Transmit FIFO underrun has occurred + */ +#define LPSPI_SR_TEF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_TEF_SHIFT)) & LPSPI_SR_TEF_MASK) +#define LPSPI_SR_REF_MASK (0x1000U) +#define LPSPI_SR_REF_SHIFT (12U) +/*! REF - Receive Error Flag + * 0b0..Receive FIFO has not overflowed + * 0b1..Receive FIFO has overflowed + */ +#define LPSPI_SR_REF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_REF_SHIFT)) & LPSPI_SR_REF_MASK) +#define LPSPI_SR_DMF_MASK (0x2000U) +#define LPSPI_SR_DMF_SHIFT (13U) +/*! DMF - Data Match Flag + * 0b0..Have not received matching data + * 0b1..Have received matching data + */ +#define LPSPI_SR_DMF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_DMF_SHIFT)) & LPSPI_SR_DMF_MASK) +#define LPSPI_SR_MBF_MASK (0x1000000U) +#define LPSPI_SR_MBF_SHIFT (24U) +/*! MBF - Module Busy Flag + * 0b0..LPSPI is idle + * 0b1..LPSPI is busy + */ +#define LPSPI_SR_MBF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_MBF_SHIFT)) & LPSPI_SR_MBF_MASK) +/*! @} */ + +/*! @name IER - Interrupt Enable Register */ +/*! @{ */ +#define LPSPI_IER_TDIE_MASK (0x1U) +#define LPSPI_IER_TDIE_SHIFT (0U) +/*! TDIE - Transmit Data Interrupt Enable + * 0b0..Disabled + * 0b1..Enabled + */ +#define LPSPI_IER_TDIE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_IER_TDIE_SHIFT)) & LPSPI_IER_TDIE_MASK) +#define LPSPI_IER_RDIE_MASK (0x2U) +#define LPSPI_IER_RDIE_SHIFT (1U) +/*! RDIE - Receive Data Interrupt Enable + * 0b0..Disabled + * 0b1..Enabled + */ +#define LPSPI_IER_RDIE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_IER_RDIE_SHIFT)) & LPSPI_IER_RDIE_MASK) +#define LPSPI_IER_WCIE_MASK (0x100U) +#define LPSPI_IER_WCIE_SHIFT (8U) +/*! WCIE - Word Complete Interrupt Enable + * 0b0..Disabled + * 0b1..Enabled + */ +#define LPSPI_IER_WCIE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_IER_WCIE_SHIFT)) & LPSPI_IER_WCIE_MASK) +#define LPSPI_IER_FCIE_MASK (0x200U) +#define LPSPI_IER_FCIE_SHIFT (9U) +/*! FCIE - Frame Complete Interrupt Enable + * 0b0..Disabled + * 0b1..Enabled + */ +#define LPSPI_IER_FCIE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_IER_FCIE_SHIFT)) & LPSPI_IER_FCIE_MASK) +#define LPSPI_IER_TCIE_MASK (0x400U) +#define LPSPI_IER_TCIE_SHIFT (10U) +/*! TCIE - Transfer Complete Interrupt Enable + * 0b0..Disabled + * 0b1..Enabled + */ +#define LPSPI_IER_TCIE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_IER_TCIE_SHIFT)) & LPSPI_IER_TCIE_MASK) +#define LPSPI_IER_TEIE_MASK (0x800U) +#define LPSPI_IER_TEIE_SHIFT (11U) +/*! TEIE - Transmit Error Interrupt Enable + * 0b0..Disabled + * 0b1..Enabled + */ +#define LPSPI_IER_TEIE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_IER_TEIE_SHIFT)) & LPSPI_IER_TEIE_MASK) +#define LPSPI_IER_REIE_MASK (0x1000U) +#define LPSPI_IER_REIE_SHIFT (12U) +/*! REIE - Receive Error Interrupt Enable + * 0b0..Disabled + * 0b1..Enabled + */ +#define LPSPI_IER_REIE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_IER_REIE_SHIFT)) & LPSPI_IER_REIE_MASK) +#define LPSPI_IER_DMIE_MASK (0x2000U) +#define LPSPI_IER_DMIE_SHIFT (13U) +/*! DMIE - Data Match Interrupt Enable + * 0b0..Disabled + * 0b1..Enabled + */ +#define LPSPI_IER_DMIE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_IER_DMIE_SHIFT)) & LPSPI_IER_DMIE_MASK) +/*! @} */ + +/*! @name DER - DMA Enable Register */ +/*! @{ */ +#define LPSPI_DER_TDDE_MASK (0x1U) +#define LPSPI_DER_TDDE_SHIFT (0U) +/*! TDDE - Transmit Data DMA Enable + * 0b0..DMA request is disabled + * 0b1..DMA request is enabled + */ +#define LPSPI_DER_TDDE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_DER_TDDE_SHIFT)) & LPSPI_DER_TDDE_MASK) +#define LPSPI_DER_RDDE_MASK (0x2U) +#define LPSPI_DER_RDDE_SHIFT (1U) +/*! RDDE - Receive Data DMA Enable + * 0b0..DMA request is disabled + * 0b1..DMA request is enabled + */ +#define LPSPI_DER_RDDE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_DER_RDDE_SHIFT)) & LPSPI_DER_RDDE_MASK) +/*! @} */ + +/*! @name CFGR0 - Configuration Register 0 */ +/*! @{ */ +#define LPSPI_CFGR0_HREN_MASK (0x1U) +#define LPSPI_CFGR0_HREN_SHIFT (0U) +/*! HREN - Host Request Enable + * 0b0..Host request is disabled + * 0b1..Host request is enabled + */ +#define LPSPI_CFGR0_HREN(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR0_HREN_SHIFT)) & LPSPI_CFGR0_HREN_MASK) +#define LPSPI_CFGR0_HRPOL_MASK (0x2U) +#define LPSPI_CFGR0_HRPOL_SHIFT (1U) +/*! HRPOL - Host Request Polarity + * 0b0..Active low + * 0b1..Active high + */ +#define LPSPI_CFGR0_HRPOL(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR0_HRPOL_SHIFT)) & LPSPI_CFGR0_HRPOL_MASK) +#define LPSPI_CFGR0_HRSEL_MASK (0x4U) +#define LPSPI_CFGR0_HRSEL_SHIFT (2U) +/*! HRSEL - Host Request Select + * 0b0..Host request input is the LPSPI_HREQ pin + * 0b1..Host request input is the input trigger + */ +#define LPSPI_CFGR0_HRSEL(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR0_HRSEL_SHIFT)) & LPSPI_CFGR0_HRSEL_MASK) +#define LPSPI_CFGR0_CIRFIFO_MASK (0x100U) +#define LPSPI_CFGR0_CIRFIFO_SHIFT (8U) +/*! CIRFIFO - Circular FIFO Enable + * 0b0..Circular FIFO is disabled + * 0b1..Circular FIFO is enabled + */ +#define LPSPI_CFGR0_CIRFIFO(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR0_CIRFIFO_SHIFT)) & LPSPI_CFGR0_CIRFIFO_MASK) +#define LPSPI_CFGR0_RDMO_MASK (0x200U) +#define LPSPI_CFGR0_RDMO_SHIFT (9U) +/*! RDMO - Receive Data Match Only + * 0b0..Received data is stored in the receive FIFO as in normal operations + * 0b1..Received data is discarded unless the Data Match Flag (DMF) is set + */ +#define LPSPI_CFGR0_RDMO(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR0_RDMO_SHIFT)) & LPSPI_CFGR0_RDMO_MASK) +/*! @} */ + +/*! @name CFGR1 - Configuration Register 1 */ +/*! @{ */ +#define LPSPI_CFGR1_MASTER_MASK (0x1U) +#define LPSPI_CFGR1_MASTER_SHIFT (0U) +/*! MASTER - Master Mode + * 0b0..Slave mode + * 0b1..Master mode + */ +#define LPSPI_CFGR1_MASTER(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_MASTER_SHIFT)) & LPSPI_CFGR1_MASTER_MASK) +#define LPSPI_CFGR1_SAMPLE_MASK (0x2U) +#define LPSPI_CFGR1_SAMPLE_SHIFT (1U) +/*! SAMPLE - Sample Point + * 0b0..Input data is sampled on SCK edge + * 0b1..Input data is sampled on delayed SCK edge + */ +#define LPSPI_CFGR1_SAMPLE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_SAMPLE_SHIFT)) & LPSPI_CFGR1_SAMPLE_MASK) +#define LPSPI_CFGR1_AUTOPCS_MASK (0x4U) +#define LPSPI_CFGR1_AUTOPCS_SHIFT (2U) +/*! AUTOPCS - Automatic PCS + * 0b0..Automatic PCS generation is disabled + * 0b1..Automatic PCS generation is enabled + */ +#define LPSPI_CFGR1_AUTOPCS(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_AUTOPCS_SHIFT)) & LPSPI_CFGR1_AUTOPCS_MASK) +#define LPSPI_CFGR1_NOSTALL_MASK (0x8U) +#define LPSPI_CFGR1_NOSTALL_SHIFT (3U) +/*! NOSTALL - No Stall + * 0b0..Transfers will stall when the transmit FIFO is empty or the receive FIFO is full + * 0b1..Transfers will not stall, allowing transmit FIFO underruns or receive FIFO overruns to occur + */ +#define LPSPI_CFGR1_NOSTALL(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_NOSTALL_SHIFT)) & LPSPI_CFGR1_NOSTALL_MASK) +#define LPSPI_CFGR1_PCSPOL_MASK (0xF00U) +#define LPSPI_CFGR1_PCSPOL_SHIFT (8U) +/*! PCSPOL - Peripheral Chip Select Polarity + * 0b0000..The Peripheral Chip Select pin PCSx is active low + * 0b0001..The Peripheral Chip Select pin PCSx is active high + */ +#define LPSPI_CFGR1_PCSPOL(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_PCSPOL_SHIFT)) & LPSPI_CFGR1_PCSPOL_MASK) +#define LPSPI_CFGR1_MATCFG_MASK (0x70000U) +#define LPSPI_CFGR1_MATCFG_SHIFT (16U) +/*! MATCFG - Match Configuration + * 0b000..Match is disabled + * 0b001..Reserved + * 0b010..010b - Match is enabled, if 1st data word equals MATCH0 OR MATCH1, i.e., (1st data word = MATCH0 + MATCH1) + * 0b011..011b - Match is enabled, if any data word equals MATCH0 OR MATCH1, i.e., (any data word = MATCH0 + MATCH1) + * 0b100..100b - Match is enabled, if 1st data word equals MATCH0 AND 2nd data word equals MATCH1, i.e., [(1st data word = MATCH0) * (2nd data word = MATCH1)] + * 0b101..101b - Match is enabled, if any data word equals MATCH0 AND the next data word equals MATCH1, i.e., [(any data word = MATCH0) * (next data word = MATCH1)] + * 0b110..110b - Match is enabled, if (1st data word AND MATCH1) equals (MATCH0 AND MATCH1), i.e., [(1st data word * MATCH1) = (MATCH0 * MATCH1)] + * 0b111..111b - Match is enabled, if (any data word AND MATCH1) equals (MATCH0 AND MATCH1), i.e., [(any data word * MATCH1) = (MATCH0 * MATCH1)] + */ +#define LPSPI_CFGR1_MATCFG(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_MATCFG_SHIFT)) & LPSPI_CFGR1_MATCFG_MASK) +#define LPSPI_CFGR1_PINCFG_MASK (0x3000000U) +#define LPSPI_CFGR1_PINCFG_SHIFT (24U) +/*! PINCFG - Pin Configuration + * 0b00..SIN is used for input data and SOUT is used for output data + * 0b01..SIN is used for both input and output data + * 0b10..SOUT is used for both input and output data + * 0b11..SOUT is used for input data and SIN is used for output data + */ +#define LPSPI_CFGR1_PINCFG(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_PINCFG_SHIFT)) & LPSPI_CFGR1_PINCFG_MASK) +#define LPSPI_CFGR1_OUTCFG_MASK (0x4000000U) +#define LPSPI_CFGR1_OUTCFG_SHIFT (26U) +/*! OUTCFG - Output Config + * 0b0..Output data retains last value when chip select is negated + * 0b1..Output data is tristated when chip select is negated + */ +#define LPSPI_CFGR1_OUTCFG(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_OUTCFG_SHIFT)) & LPSPI_CFGR1_OUTCFG_MASK) +#define LPSPI_CFGR1_PCSCFG_MASK (0x8000000U) +#define LPSPI_CFGR1_PCSCFG_SHIFT (27U) +/*! PCSCFG - Peripheral Chip Select Configuration + * 0b0..PCS[3:2] are enabled + * 0b1..PCS[3:2] are disabled + */ +#define LPSPI_CFGR1_PCSCFG(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_PCSCFG_SHIFT)) & LPSPI_CFGR1_PCSCFG_MASK) +/*! @} */ + +/*! @name DMR0 - Data Match Register 0 */ +/*! @{ */ +#define LPSPI_DMR0_MATCH0_MASK (0xFFFFFFFFU) +#define LPSPI_DMR0_MATCH0_SHIFT (0U) +#define LPSPI_DMR0_MATCH0(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_DMR0_MATCH0_SHIFT)) & LPSPI_DMR0_MATCH0_MASK) +/*! @} */ + +/*! @name DMR1 - Data Match Register 1 */ +/*! @{ */ +#define LPSPI_DMR1_MATCH1_MASK (0xFFFFFFFFU) +#define LPSPI_DMR1_MATCH1_SHIFT (0U) +#define LPSPI_DMR1_MATCH1(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_DMR1_MATCH1_SHIFT)) & LPSPI_DMR1_MATCH1_MASK) +/*! @} */ + +/*! @name CCR - Clock Configuration Register */ +/*! @{ */ +#define LPSPI_CCR_SCKDIV_MASK (0xFFU) +#define LPSPI_CCR_SCKDIV_SHIFT (0U) +#define LPSPI_CCR_SCKDIV(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CCR_SCKDIV_SHIFT)) & LPSPI_CCR_SCKDIV_MASK) +#define LPSPI_CCR_DBT_MASK (0xFF00U) +#define LPSPI_CCR_DBT_SHIFT (8U) +#define LPSPI_CCR_DBT(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CCR_DBT_SHIFT)) & LPSPI_CCR_DBT_MASK) +#define LPSPI_CCR_PCSSCK_MASK (0xFF0000U) +#define LPSPI_CCR_PCSSCK_SHIFT (16U) +#define LPSPI_CCR_PCSSCK(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CCR_PCSSCK_SHIFT)) & LPSPI_CCR_PCSSCK_MASK) +#define LPSPI_CCR_SCKPCS_MASK (0xFF000000U) +#define LPSPI_CCR_SCKPCS_SHIFT (24U) +#define LPSPI_CCR_SCKPCS(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CCR_SCKPCS_SHIFT)) & LPSPI_CCR_SCKPCS_MASK) +/*! @} */ + +/*! @name FCR - FIFO Control Register */ +/*! @{ */ +#define LPSPI_FCR_TXWATER_MASK (0xFU) +#define LPSPI_FCR_TXWATER_SHIFT (0U) +#define LPSPI_FCR_TXWATER(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_FCR_TXWATER_SHIFT)) & LPSPI_FCR_TXWATER_MASK) +#define LPSPI_FCR_RXWATER_MASK (0xF0000U) +#define LPSPI_FCR_RXWATER_SHIFT (16U) +#define LPSPI_FCR_RXWATER(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_FCR_RXWATER_SHIFT)) & LPSPI_FCR_RXWATER_MASK) +/*! @} */ + +/*! @name FSR - FIFO Status Register */ +/*! @{ */ +#define LPSPI_FSR_TXCOUNT_MASK (0x1FU) +#define LPSPI_FSR_TXCOUNT_SHIFT (0U) +#define LPSPI_FSR_TXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_FSR_TXCOUNT_SHIFT)) & LPSPI_FSR_TXCOUNT_MASK) +#define LPSPI_FSR_RXCOUNT_MASK (0x1F0000U) +#define LPSPI_FSR_RXCOUNT_SHIFT (16U) +#define LPSPI_FSR_RXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_FSR_RXCOUNT_SHIFT)) & LPSPI_FSR_RXCOUNT_MASK) +/*! @} */ + +/*! @name TCR - Transmit Command Register */ +/*! @{ */ +#define LPSPI_TCR_FRAMESZ_MASK (0xFFFU) +#define LPSPI_TCR_FRAMESZ_SHIFT (0U) +#define LPSPI_TCR_FRAMESZ(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_FRAMESZ_SHIFT)) & LPSPI_TCR_FRAMESZ_MASK) +#define LPSPI_TCR_WIDTH_MASK (0x30000U) +#define LPSPI_TCR_WIDTH_SHIFT (16U) +/*! WIDTH - Transfer Width + * 0b00..1 bit transfer + * 0b01..2 bit transfer + * 0b10..4 bit transfer + * 0b11..Reserved + */ +#define LPSPI_TCR_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_WIDTH_SHIFT)) & LPSPI_TCR_WIDTH_MASK) +#define LPSPI_TCR_TXMSK_MASK (0x40000U) +#define LPSPI_TCR_TXMSK_SHIFT (18U) +/*! TXMSK - Transmit Data Mask + * 0b0..Normal transfer + * 0b1..Mask transmit data + */ +#define LPSPI_TCR_TXMSK(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_TXMSK_SHIFT)) & LPSPI_TCR_TXMSK_MASK) +#define LPSPI_TCR_RXMSK_MASK (0x80000U) +#define LPSPI_TCR_RXMSK_SHIFT (19U) +/*! RXMSK - Receive Data Mask + * 0b0..Normal transfer + * 0b1..Receive data is masked + */ +#define LPSPI_TCR_RXMSK(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_RXMSK_SHIFT)) & LPSPI_TCR_RXMSK_MASK) +#define LPSPI_TCR_CONTC_MASK (0x100000U) +#define LPSPI_TCR_CONTC_SHIFT (20U) +/*! CONTC - Continuing Command + * 0b0..Command word for start of new transfer + * 0b1..Command word for continuing transfer + */ +#define LPSPI_TCR_CONTC(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_CONTC_SHIFT)) & LPSPI_TCR_CONTC_MASK) +#define LPSPI_TCR_CONT_MASK (0x200000U) +#define LPSPI_TCR_CONT_SHIFT (21U) +/*! CONT - Continuous Transfer + * 0b0..Continuous transfer is disabled + * 0b1..Continuous transfer is enabled + */ +#define LPSPI_TCR_CONT(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_CONT_SHIFT)) & LPSPI_TCR_CONT_MASK) +#define LPSPI_TCR_BYSW_MASK (0x400000U) +#define LPSPI_TCR_BYSW_SHIFT (22U) +/*! BYSW - Byte Swap + * 0b0..Byte swap is disabled + * 0b1..Byte swap is enabled + */ +#define LPSPI_TCR_BYSW(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_BYSW_SHIFT)) & LPSPI_TCR_BYSW_MASK) +#define LPSPI_TCR_LSBF_MASK (0x800000U) +#define LPSPI_TCR_LSBF_SHIFT (23U) +/*! LSBF - LSB First + * 0b0..Data is transferred MSB first + * 0b1..Data is transferred LSB first + */ +#define LPSPI_TCR_LSBF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_LSBF_SHIFT)) & LPSPI_TCR_LSBF_MASK) +#define LPSPI_TCR_PCS_MASK (0x3000000U) +#define LPSPI_TCR_PCS_SHIFT (24U) +/*! PCS - Peripheral Chip Select + * 0b00..Transfer using LPSPI_PCS[0] + * 0b01..Transfer using LPSPI_PCS[1] + * 0b10..Transfer using LPSPI_PCS[2] + * 0b11..Transfer using LPSPI_PCS[3] + */ +#define LPSPI_TCR_PCS(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_PCS_SHIFT)) & LPSPI_TCR_PCS_MASK) +#define LPSPI_TCR_PRESCALE_MASK (0x38000000U) +#define LPSPI_TCR_PRESCALE_SHIFT (27U) +/*! PRESCALE - Prescaler Value + * 0b000..Divide by 1 + * 0b001..Divide by 2 + * 0b010..Divide by 4 + * 0b011..Divide by 8 + * 0b100..Divide by 16 + * 0b101..Divide by 32 + * 0b110..Divide by 64 + * 0b111..Divide by 128 + */ +#define LPSPI_TCR_PRESCALE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_PRESCALE_SHIFT)) & LPSPI_TCR_PRESCALE_MASK) +#define LPSPI_TCR_CPHA_MASK (0x40000000U) +#define LPSPI_TCR_CPHA_SHIFT (30U) +/*! CPHA - Clock Phase + * 0b0..Data is captured on the leading edge of SCK and changed on the following edge of SCK + * 0b1..Data is changed on the leading edge of SCK and captured on the following edge of SCK + */ +#define LPSPI_TCR_CPHA(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_CPHA_SHIFT)) & LPSPI_TCR_CPHA_MASK) +#define LPSPI_TCR_CPOL_MASK (0x80000000U) +#define LPSPI_TCR_CPOL_SHIFT (31U) +/*! CPOL - Clock Polarity + * 0b0..The inactive state value of SCK is low + * 0b1..The inactive state value of SCK is high + */ +#define LPSPI_TCR_CPOL(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_CPOL_SHIFT)) & LPSPI_TCR_CPOL_MASK) +/*! @} */ + +/*! @name TDR - Transmit Data Register */ +/*! @{ */ +#define LPSPI_TDR_DATA_MASK (0xFFFFFFFFU) +#define LPSPI_TDR_DATA_SHIFT (0U) +#define LPSPI_TDR_DATA(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TDR_DATA_SHIFT)) & LPSPI_TDR_DATA_MASK) +/*! @} */ + +/*! @name RSR - Receive Status Register */ +/*! @{ */ +#define LPSPI_RSR_SOF_MASK (0x1U) +#define LPSPI_RSR_SOF_SHIFT (0U) +/*! SOF - Start Of Frame + * 0b0..Subsequent data word received after LPSPI_PCS assertion + * 0b1..First data word received after LPSPI_PCS assertion + */ +#define LPSPI_RSR_SOF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_RSR_SOF_SHIFT)) & LPSPI_RSR_SOF_MASK) +#define LPSPI_RSR_RXEMPTY_MASK (0x2U) +#define LPSPI_RSR_RXEMPTY_SHIFT (1U) +/*! RXEMPTY - RX FIFO Empty + * 0b0..RX FIFO is not empty + * 0b1..RX FIFO is empty + */ +#define LPSPI_RSR_RXEMPTY(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_RSR_RXEMPTY_SHIFT)) & LPSPI_RSR_RXEMPTY_MASK) +/*! @} */ + +/*! @name RDR - Receive Data Register */ +/*! @{ */ +#define LPSPI_RDR_DATA_MASK (0xFFFFFFFFU) +#define LPSPI_RDR_DATA_SHIFT (0U) +#define LPSPI_RDR_DATA(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_RDR_DATA_SHIFT)) & LPSPI_RDR_DATA_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group LPSPI_Register_Masks */ + + +/* LPSPI - Peripheral instance base addresses */ +/** Peripheral LPSPI1 base address */ +#define LPSPI1_BASE (0x40394000u) +/** Peripheral LPSPI1 base pointer */ +#define LPSPI1 ((LPSPI_Type *)LPSPI1_BASE) +/** Peripheral LPSPI2 base address */ +#define LPSPI2_BASE (0x40398000u) +/** Peripheral LPSPI2 base pointer */ +#define LPSPI2 ((LPSPI_Type *)LPSPI2_BASE) +/** Peripheral LPSPI3 base address */ +#define LPSPI3_BASE (0x4039C000u) +/** Peripheral LPSPI3 base pointer */ +#define LPSPI3 ((LPSPI_Type *)LPSPI3_BASE) +/** Peripheral LPSPI4 base address */ +#define LPSPI4_BASE (0x403A0000u) +/** Peripheral LPSPI4 base pointer */ +#define LPSPI4 ((LPSPI_Type *)LPSPI4_BASE) +/** Array initializer of LPSPI peripheral base addresses */ +#define LPSPI_BASE_ADDRS { 0u, LPSPI1_BASE, LPSPI2_BASE, LPSPI3_BASE, LPSPI4_BASE } +/** Array initializer of LPSPI peripheral base pointers */ +#define LPSPI_BASE_PTRS { (LPSPI_Type *)0u, LPSPI1, LPSPI2, LPSPI3, LPSPI4 } +/** Interrupt vectors for the LPSPI peripheral type */ +#define LPSPI_IRQS { NotAvail_IRQn, LPSPI1_IRQn, LPSPI2_IRQn, LPSPI3_IRQn, LPSPI4_IRQn } + +/*! + * @} + */ /* end of group LPSPI_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- LPUART Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup LPUART_Peripheral_Access_Layer LPUART Peripheral Access Layer + * @{ + */ + +/** LPUART - Register Layout Typedef */ +typedef struct { + __I uint32_t VERID; /**< Version ID Register, offset: 0x0 */ + __I uint32_t PARAM; /**< Parameter Register, offset: 0x4 */ + __IO uint32_t GLOBAL; /**< LPUART Global Register, offset: 0x8 */ + __IO uint32_t PINCFG; /**< LPUART Pin Configuration Register, offset: 0xC */ + __IO uint32_t BAUD; /**< LPUART Baud Rate Register, offset: 0x10 */ + __IO uint32_t STAT; /**< LPUART Status Register, offset: 0x14 */ + __IO uint32_t CTRL; /**< LPUART Control Register, offset: 0x18 */ + __IO uint32_t DATA; /**< LPUART Data Register, offset: 0x1C */ + __IO uint32_t MATCH; /**< LPUART Match Address Register, offset: 0x20 */ + __IO uint32_t MODIR; /**< LPUART Modem IrDA Register, offset: 0x24 */ + __IO uint32_t FIFO; /**< LPUART FIFO Register, offset: 0x28 */ + __IO uint32_t WATER; /**< LPUART Watermark Register, offset: 0x2C */ +} LPUART_Type; + +/* ---------------------------------------------------------------------------- + -- LPUART Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup LPUART_Register_Masks LPUART Register Masks + * @{ + */ + +/*! @name VERID - Version ID Register */ +/*! @{ */ +#define LPUART_VERID_FEATURE_MASK (0xFFFFU) +#define LPUART_VERID_FEATURE_SHIFT (0U) +/*! FEATURE - Feature Identification Number + * 0b0000000000000001..Standard feature set. + * 0b0000000000000011..Standard feature set with MODEM/IrDA support. + */ +#define LPUART_VERID_FEATURE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_VERID_FEATURE_SHIFT)) & LPUART_VERID_FEATURE_MASK) +#define LPUART_VERID_MINOR_MASK (0xFF0000U) +#define LPUART_VERID_MINOR_SHIFT (16U) +#define LPUART_VERID_MINOR(x) (((uint32_t)(((uint32_t)(x)) << LPUART_VERID_MINOR_SHIFT)) & LPUART_VERID_MINOR_MASK) +#define LPUART_VERID_MAJOR_MASK (0xFF000000U) +#define LPUART_VERID_MAJOR_SHIFT (24U) +#define LPUART_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << LPUART_VERID_MAJOR_SHIFT)) & LPUART_VERID_MAJOR_MASK) +/*! @} */ + +/*! @name PARAM - Parameter Register */ +/*! @{ */ +#define LPUART_PARAM_TXFIFO_MASK (0xFFU) +#define LPUART_PARAM_TXFIFO_SHIFT (0U) +#define LPUART_PARAM_TXFIFO(x) (((uint32_t)(((uint32_t)(x)) << LPUART_PARAM_TXFIFO_SHIFT)) & LPUART_PARAM_TXFIFO_MASK) +#define LPUART_PARAM_RXFIFO_MASK (0xFF00U) +#define LPUART_PARAM_RXFIFO_SHIFT (8U) +#define LPUART_PARAM_RXFIFO(x) (((uint32_t)(((uint32_t)(x)) << LPUART_PARAM_RXFIFO_SHIFT)) & LPUART_PARAM_RXFIFO_MASK) +/*! @} */ + +/*! @name GLOBAL - LPUART Global Register */ +/*! @{ */ +#define LPUART_GLOBAL_RST_MASK (0x2U) +#define LPUART_GLOBAL_RST_SHIFT (1U) +/*! RST - Software Reset + * 0b0..Module is not reset. + * 0b1..Module is reset. + */ +#define LPUART_GLOBAL_RST(x) (((uint32_t)(((uint32_t)(x)) << LPUART_GLOBAL_RST_SHIFT)) & LPUART_GLOBAL_RST_MASK) +/*! @} */ + +/*! @name PINCFG - LPUART Pin Configuration Register */ +/*! @{ */ +#define LPUART_PINCFG_TRGSEL_MASK (0x3U) +#define LPUART_PINCFG_TRGSEL_SHIFT (0U) +/*! TRGSEL - Trigger Select + * 0b00..Input trigger is disabled. + * 0b01..Input trigger is used instead of RXD pin input. + * 0b10..Input trigger is used instead of CTS_B pin input. + * 0b11..Input trigger is used to modulate the TXD pin output. The TXD pin output (after TXINV configuration) is ANDed with the input trigger. + */ +#define LPUART_PINCFG_TRGSEL(x) (((uint32_t)(((uint32_t)(x)) << LPUART_PINCFG_TRGSEL_SHIFT)) & LPUART_PINCFG_TRGSEL_MASK) +/*! @} */ + +/*! @name BAUD - LPUART Baud Rate Register */ +/*! @{ */ +#define LPUART_BAUD_SBR_MASK (0x1FFFU) +#define LPUART_BAUD_SBR_SHIFT (0U) +#define LPUART_BAUD_SBR(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_SBR_SHIFT)) & LPUART_BAUD_SBR_MASK) +#define LPUART_BAUD_SBNS_MASK (0x2000U) +#define LPUART_BAUD_SBNS_SHIFT (13U) +/*! SBNS - Stop Bit Number Select + * 0b0..One stop bit. + * 0b1..Two stop bits. + */ +#define LPUART_BAUD_SBNS(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_SBNS_SHIFT)) & LPUART_BAUD_SBNS_MASK) +#define LPUART_BAUD_RXEDGIE_MASK (0x4000U) +#define LPUART_BAUD_RXEDGIE_SHIFT (14U) +/*! RXEDGIE - RX Input Active Edge Interrupt Enable + * 0b0..Hardware interrupts from STAT[RXEDGIF] are disabled. + * 0b1..Hardware interrupt is requested when STAT[RXEDGIF] flag is 1. + */ +#define LPUART_BAUD_RXEDGIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_RXEDGIE_SHIFT)) & LPUART_BAUD_RXEDGIE_MASK) +#define LPUART_BAUD_LBKDIE_MASK (0x8000U) +#define LPUART_BAUD_LBKDIE_SHIFT (15U) +/*! LBKDIE - LIN Break Detect Interrupt Enable + * 0b0..Hardware interrupts from STAT[LBKDIF] flag are disabled (use polling). + * 0b1..Hardware interrupt requested when STAT[LBKDIF] flag is 1. + */ +#define LPUART_BAUD_LBKDIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_LBKDIE_SHIFT)) & LPUART_BAUD_LBKDIE_MASK) +#define LPUART_BAUD_RESYNCDIS_MASK (0x10000U) +#define LPUART_BAUD_RESYNCDIS_SHIFT (16U) +/*! RESYNCDIS - Resynchronization Disable + * 0b0..Resynchronization during received data word is supported + * 0b1..Resynchronization during received data word is disabled + */ +#define LPUART_BAUD_RESYNCDIS(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_RESYNCDIS_SHIFT)) & LPUART_BAUD_RESYNCDIS_MASK) +#define LPUART_BAUD_BOTHEDGE_MASK (0x20000U) +#define LPUART_BAUD_BOTHEDGE_SHIFT (17U) +/*! BOTHEDGE - Both Edge Sampling + * 0b0..Receiver samples input data using the rising edge of the baud rate clock. + * 0b1..Receiver samples input data using the rising and falling edge of the baud rate clock. + */ +#define LPUART_BAUD_BOTHEDGE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_BOTHEDGE_SHIFT)) & LPUART_BAUD_BOTHEDGE_MASK) +#define LPUART_BAUD_MATCFG_MASK (0xC0000U) +#define LPUART_BAUD_MATCFG_SHIFT (18U) +/*! MATCFG - Match Configuration + * 0b00..Address Match Wakeup + * 0b01..Idle Match Wakeup + * 0b10..Match On and Match Off + * 0b11..Enables RWU on Data Match and Match On/Off for transmitter CTS input + */ +#define LPUART_BAUD_MATCFG(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_MATCFG_SHIFT)) & LPUART_BAUD_MATCFG_MASK) +#define LPUART_BAUD_RIDMAE_MASK (0x100000U) +#define LPUART_BAUD_RIDMAE_SHIFT (20U) +/*! RIDMAE - Receiver Idle DMA Enable + * 0b0..DMA request disabled. + * 0b1..DMA request enabled. + */ +#define LPUART_BAUD_RIDMAE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_RIDMAE_SHIFT)) & LPUART_BAUD_RIDMAE_MASK) +#define LPUART_BAUD_RDMAE_MASK (0x200000U) +#define LPUART_BAUD_RDMAE_SHIFT (21U) +/*! RDMAE - Receiver Full DMA Enable + * 0b0..DMA request disabled. + * 0b1..DMA request enabled. + */ +#define LPUART_BAUD_RDMAE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_RDMAE_SHIFT)) & LPUART_BAUD_RDMAE_MASK) +#define LPUART_BAUD_TDMAE_MASK (0x800000U) +#define LPUART_BAUD_TDMAE_SHIFT (23U) +/*! TDMAE - Transmitter DMA Enable + * 0b0..DMA request disabled. + * 0b1..DMA request enabled. + */ +#define LPUART_BAUD_TDMAE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_TDMAE_SHIFT)) & LPUART_BAUD_TDMAE_MASK) +#define LPUART_BAUD_OSR_MASK (0x1F000000U) +#define LPUART_BAUD_OSR_SHIFT (24U) +/*! OSR - Oversampling Ratio + * 0b00000..Writing 0 to this field will result in an oversampling ratio of 16 + * 0b00001..Reserved + * 0b00010..Reserved + * 0b00011..Oversampling ratio of 4, requires BOTHEDGE to be set. + * 0b00100..Oversampling ratio of 5, requires BOTHEDGE to be set. + * 0b00101..Oversampling ratio of 6, requires BOTHEDGE to be set. + * 0b00110..Oversampling ratio of 7, requires BOTHEDGE to be set. + * 0b00111..Oversampling ratio of 8. + * 0b01000..Oversampling ratio of 9. + * 0b01001..Oversampling ratio of 10. + * 0b01010..Oversampling ratio of 11. + * 0b01011..Oversampling ratio of 12. + * 0b01100..Oversampling ratio of 13. + * 0b01101..Oversampling ratio of 14. + * 0b01110..Oversampling ratio of 15. + * 0b01111..Oversampling ratio of 16. + * 0b10000..Oversampling ratio of 17. + * 0b10001..Oversampling ratio of 18. + * 0b10010..Oversampling ratio of 19. + * 0b10011..Oversampling ratio of 20. + * 0b10100..Oversampling ratio of 21. + * 0b10101..Oversampling ratio of 22. + * 0b10110..Oversampling ratio of 23. + * 0b10111..Oversampling ratio of 24. + * 0b11000..Oversampling ratio of 25. + * 0b11001..Oversampling ratio of 26. + * 0b11010..Oversampling ratio of 27. + * 0b11011..Oversampling ratio of 28. + * 0b11100..Oversampling ratio of 29. + * 0b11101..Oversampling ratio of 30. + * 0b11110..Oversampling ratio of 31. + * 0b11111..Oversampling ratio of 32. + */ +#define LPUART_BAUD_OSR(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_OSR_SHIFT)) & LPUART_BAUD_OSR_MASK) +#define LPUART_BAUD_M10_MASK (0x20000000U) +#define LPUART_BAUD_M10_SHIFT (29U) +/*! M10 - 10-bit Mode select + * 0b0..Receiver and transmitter use 7-bit to 9-bit data characters. + * 0b1..Receiver and transmitter use 10-bit data characters. + */ +#define LPUART_BAUD_M10(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_M10_SHIFT)) & LPUART_BAUD_M10_MASK) +#define LPUART_BAUD_MAEN2_MASK (0x40000000U) +#define LPUART_BAUD_MAEN2_SHIFT (30U) +/*! MAEN2 - Match Address Mode Enable 2 + * 0b0..Normal operation. + * 0b1..Enables automatic address matching or data matching mode for MATCH[MA2]. + */ +#define LPUART_BAUD_MAEN2(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_MAEN2_SHIFT)) & LPUART_BAUD_MAEN2_MASK) +#define LPUART_BAUD_MAEN1_MASK (0x80000000U) +#define LPUART_BAUD_MAEN1_SHIFT (31U) +/*! MAEN1 - Match Address Mode Enable 1 + * 0b0..Normal operation. + * 0b1..Enables automatic address matching or data matching mode for MATCH[MA1]. + */ +#define LPUART_BAUD_MAEN1(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_MAEN1_SHIFT)) & LPUART_BAUD_MAEN1_MASK) +/*! @} */ + +/*! @name STAT - LPUART Status Register */ +/*! @{ */ +#define LPUART_STAT_MA2F_MASK (0x4000U) +#define LPUART_STAT_MA2F_SHIFT (14U) +/*! MA2F - Match 2 Flag + * 0b0..Received data is not equal to MA2 + * 0b1..Received data is equal to MA2 + */ +#define LPUART_STAT_MA2F(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_MA2F_SHIFT)) & LPUART_STAT_MA2F_MASK) +#define LPUART_STAT_MA1F_MASK (0x8000U) +#define LPUART_STAT_MA1F_SHIFT (15U) +/*! MA1F - Match 1 Flag + * 0b0..Received data is not equal to MA1 + * 0b1..Received data is equal to MA1 + */ +#define LPUART_STAT_MA1F(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_MA1F_SHIFT)) & LPUART_STAT_MA1F_MASK) +#define LPUART_STAT_PF_MASK (0x10000U) +#define LPUART_STAT_PF_SHIFT (16U) +/*! PF - Parity Error Flag + * 0b0..No parity error. + * 0b1..Parity error. + */ +#define LPUART_STAT_PF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_PF_SHIFT)) & LPUART_STAT_PF_MASK) +#define LPUART_STAT_FE_MASK (0x20000U) +#define LPUART_STAT_FE_SHIFT (17U) +/*! FE - Framing Error Flag + * 0b0..No framing error detected. This does not guarantee the framing is correct. + * 0b1..Framing error. + */ +#define LPUART_STAT_FE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_FE_SHIFT)) & LPUART_STAT_FE_MASK) +#define LPUART_STAT_NF_MASK (0x40000U) +#define LPUART_STAT_NF_SHIFT (18U) +/*! NF - Noise Flag + * 0b0..No noise detected. + * 0b1..Noise detected in the received character in the DATA register. + */ +#define LPUART_STAT_NF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_NF_SHIFT)) & LPUART_STAT_NF_MASK) +#define LPUART_STAT_OR_MASK (0x80000U) +#define LPUART_STAT_OR_SHIFT (19U) +/*! OR - Receiver Overrun Flag + * 0b0..No overrun. + * 0b1..Receive overrun (new LPUART data lost). + */ +#define LPUART_STAT_OR(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_OR_SHIFT)) & LPUART_STAT_OR_MASK) +#define LPUART_STAT_IDLE_MASK (0x100000U) +#define LPUART_STAT_IDLE_SHIFT (20U) +/*! IDLE - Idle Line Flag + * 0b0..No idle line detected. + * 0b1..Idle line was detected. + */ +#define LPUART_STAT_IDLE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_IDLE_SHIFT)) & LPUART_STAT_IDLE_MASK) +#define LPUART_STAT_RDRF_MASK (0x200000U) +#define LPUART_STAT_RDRF_SHIFT (21U) +/*! RDRF - Receive Data Register Full Flag + * 0b0..Receive data buffer empty. + * 0b1..Receive data buffer full. + */ +#define LPUART_STAT_RDRF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_RDRF_SHIFT)) & LPUART_STAT_RDRF_MASK) +#define LPUART_STAT_TC_MASK (0x400000U) +#define LPUART_STAT_TC_SHIFT (22U) +/*! TC - Transmission Complete Flag + * 0b0..Transmitter active (sending data, a preamble, or a break). + * 0b1..Transmitter idle (transmission activity complete). + */ +#define LPUART_STAT_TC(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_TC_SHIFT)) & LPUART_STAT_TC_MASK) +#define LPUART_STAT_TDRE_MASK (0x800000U) +#define LPUART_STAT_TDRE_SHIFT (23U) +/*! TDRE - Transmit Data Register Empty Flag + * 0b0..Transmit data buffer full. + * 0b1..Transmit data buffer empty. + */ +#define LPUART_STAT_TDRE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_TDRE_SHIFT)) & LPUART_STAT_TDRE_MASK) +#define LPUART_STAT_RAF_MASK (0x1000000U) +#define LPUART_STAT_RAF_SHIFT (24U) +/*! RAF - Receiver Active Flag + * 0b0..LPUART receiver idle waiting for a start bit. + * 0b1..LPUART receiver active (RXD input not idle). + */ +#define LPUART_STAT_RAF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_RAF_SHIFT)) & LPUART_STAT_RAF_MASK) +#define LPUART_STAT_LBKDE_MASK (0x2000000U) +#define LPUART_STAT_LBKDE_SHIFT (25U) +/*! LBKDE - LIN Break Detection Enable + * 0b0..LIN break detect is disabled, normal break character can be detected. + * 0b1..LIN break detect is enabled. LIN break character is detected at length of 11 bit times (if M = 0) or 12 (if M = 1) or 13 (M10 = 1). + */ +#define LPUART_STAT_LBKDE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_LBKDE_SHIFT)) & LPUART_STAT_LBKDE_MASK) +#define LPUART_STAT_BRK13_MASK (0x4000000U) +#define LPUART_STAT_BRK13_SHIFT (26U) +/*! BRK13 - Break Character Generation Length + * 0b0..Break character is transmitted with length of 9 to 13 bit times. + * 0b1..Break character is transmitted with length of 12 to 15 bit times. + */ +#define LPUART_STAT_BRK13(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_BRK13_SHIFT)) & LPUART_STAT_BRK13_MASK) +#define LPUART_STAT_RWUID_MASK (0x8000000U) +#define LPUART_STAT_RWUID_SHIFT (27U) +/*! RWUID - Receive Wake Up Idle Detect + * 0b0..During receive standby state (RWU = 1), the IDLE bit does not get set upon detection of an idle character. During address match wakeup, the IDLE bit does not set when an address does not match. + * 0b1..During receive standby state (RWU = 1), the IDLE bit gets set upon detection of an idle character. During address match wakeup, the IDLE bit does set when an address does not match. + */ +#define LPUART_STAT_RWUID(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_RWUID_SHIFT)) & LPUART_STAT_RWUID_MASK) +#define LPUART_STAT_RXINV_MASK (0x10000000U) +#define LPUART_STAT_RXINV_SHIFT (28U) +/*! RXINV - Receive Data Inversion + * 0b0..Receive data not inverted. + * 0b1..Receive data inverted. + */ +#define LPUART_STAT_RXINV(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_RXINV_SHIFT)) & LPUART_STAT_RXINV_MASK) +#define LPUART_STAT_MSBF_MASK (0x20000000U) +#define LPUART_STAT_MSBF_SHIFT (29U) +/*! MSBF - MSB First + * 0b0..LSB (bit0) is the first bit that is transmitted following the start bit. Further, the first bit received after the start bit is identified as bit0. + * 0b1..MSB (bit9, bit8, bit7 or bit6) is the first bit that is transmitted following the start bit depending on the setting of CTRL[M], CTRL[PE] and BAUD[M10]. Further, the first bit received after the start bit is identified as bit9, bit8, bit7 or bit6 depending on the setting of CTRL[M] and CTRL[PE]. + */ +#define LPUART_STAT_MSBF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_MSBF_SHIFT)) & LPUART_STAT_MSBF_MASK) +#define LPUART_STAT_RXEDGIF_MASK (0x40000000U) +#define LPUART_STAT_RXEDGIF_SHIFT (30U) +/*! RXEDGIF - RXD Pin Active Edge Interrupt Flag + * 0b0..No active edge on the receive pin has occurred. + * 0b1..An active edge on the receive pin has occurred. + */ +#define LPUART_STAT_RXEDGIF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_RXEDGIF_SHIFT)) & LPUART_STAT_RXEDGIF_MASK) +#define LPUART_STAT_LBKDIF_MASK (0x80000000U) +#define LPUART_STAT_LBKDIF_SHIFT (31U) +/*! LBKDIF - LIN Break Detect Interrupt Flag + * 0b0..No LIN break character has been detected. + * 0b1..LIN break character has been detected. + */ +#define LPUART_STAT_LBKDIF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_LBKDIF_SHIFT)) & LPUART_STAT_LBKDIF_MASK) +/*! @} */ + +/*! @name CTRL - LPUART Control Register */ +/*! @{ */ +#define LPUART_CTRL_PT_MASK (0x1U) +#define LPUART_CTRL_PT_SHIFT (0U) +/*! PT - Parity Type + * 0b0..Even parity. + * 0b1..Odd parity. + */ +#define LPUART_CTRL_PT(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_PT_SHIFT)) & LPUART_CTRL_PT_MASK) +#define LPUART_CTRL_PE_MASK (0x2U) +#define LPUART_CTRL_PE_SHIFT (1U) +/*! PE - Parity Enable + * 0b0..No hardware parity generation or checking. + * 0b1..Parity enabled. + */ +#define LPUART_CTRL_PE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_PE_SHIFT)) & LPUART_CTRL_PE_MASK) +#define LPUART_CTRL_ILT_MASK (0x4U) +#define LPUART_CTRL_ILT_SHIFT (2U) +/*! ILT - Idle Line Type Select + * 0b0..Idle character bit count starts after start bit. + * 0b1..Idle character bit count starts after stop bit. + */ +#define LPUART_CTRL_ILT(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_ILT_SHIFT)) & LPUART_CTRL_ILT_MASK) +#define LPUART_CTRL_WAKE_MASK (0x8U) +#define LPUART_CTRL_WAKE_SHIFT (3U) +/*! WAKE - Receiver Wakeup Method Select + * 0b0..Configures RWU for idle-line wakeup. + * 0b1..Configures RWU with address-mark wakeup. + */ +#define LPUART_CTRL_WAKE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_WAKE_SHIFT)) & LPUART_CTRL_WAKE_MASK) +#define LPUART_CTRL_M_MASK (0x10U) +#define LPUART_CTRL_M_SHIFT (4U) +/*! M - 9-Bit or 8-Bit Mode Select + * 0b0..Receiver and transmitter use 8-bit data characters. + * 0b1..Receiver and transmitter use 9-bit data characters. + */ +#define LPUART_CTRL_M(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_M_SHIFT)) & LPUART_CTRL_M_MASK) +#define LPUART_CTRL_RSRC_MASK (0x20U) +#define LPUART_CTRL_RSRC_SHIFT (5U) +/*! RSRC - Receiver Source Select + * 0b0..Provided LOOPS is set, RSRC is cleared, selects internal loop back mode and the LPUART does not use the RXD pin. + * 0b1..Single-wire LPUART mode where the TXD pin is connected to the transmitter output and receiver input. + */ +#define LPUART_CTRL_RSRC(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_RSRC_SHIFT)) & LPUART_CTRL_RSRC_MASK) +#define LPUART_CTRL_DOZEEN_MASK (0x40U) +#define LPUART_CTRL_DOZEEN_SHIFT (6U) +/*! DOZEEN - Doze Enable + * 0b0..LPUART is enabled in Doze mode. + * 0b1..LPUART is disabled in Doze mode. + */ +#define LPUART_CTRL_DOZEEN(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_DOZEEN_SHIFT)) & LPUART_CTRL_DOZEEN_MASK) +#define LPUART_CTRL_LOOPS_MASK (0x80U) +#define LPUART_CTRL_LOOPS_SHIFT (7U) +/*! LOOPS - Loop Mode Select + * 0b0..Normal operation - RXD and TXD use separate pins. + * 0b1..Loop mode or single-wire mode where transmitter outputs are internally connected to receiver input (see RSRC bit). + */ +#define LPUART_CTRL_LOOPS(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_LOOPS_SHIFT)) & LPUART_CTRL_LOOPS_MASK) +#define LPUART_CTRL_IDLECFG_MASK (0x700U) +#define LPUART_CTRL_IDLECFG_SHIFT (8U) +/*! IDLECFG - Idle Configuration + * 0b000..1 idle character + * 0b001..2 idle characters + * 0b010..4 idle characters + * 0b011..8 idle characters + * 0b100..16 idle characters + * 0b101..32 idle characters + * 0b110..64 idle characters + * 0b111..128 idle characters + */ +#define LPUART_CTRL_IDLECFG(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_IDLECFG_SHIFT)) & LPUART_CTRL_IDLECFG_MASK) +#define LPUART_CTRL_M7_MASK (0x800U) +#define LPUART_CTRL_M7_SHIFT (11U) +/*! M7 - 7-Bit Mode Select + * 0b0..Receiver and transmitter use 8-bit to 10-bit data characters. + * 0b1..Receiver and transmitter use 7-bit data characters. + */ +#define LPUART_CTRL_M7(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_M7_SHIFT)) & LPUART_CTRL_M7_MASK) +#define LPUART_CTRL_MA2IE_MASK (0x4000U) +#define LPUART_CTRL_MA2IE_SHIFT (14U) +/*! MA2IE - Match 2 Interrupt Enable + * 0b0..MA2F interrupt disabled + * 0b1..MA2F interrupt enabled + */ +#define LPUART_CTRL_MA2IE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_MA2IE_SHIFT)) & LPUART_CTRL_MA2IE_MASK) +#define LPUART_CTRL_MA1IE_MASK (0x8000U) +#define LPUART_CTRL_MA1IE_SHIFT (15U) +/*! MA1IE - Match 1 Interrupt Enable + * 0b0..MA1F interrupt disabled + * 0b1..MA1F interrupt enabled + */ +#define LPUART_CTRL_MA1IE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_MA1IE_SHIFT)) & LPUART_CTRL_MA1IE_MASK) +#define LPUART_CTRL_SBK_MASK (0x10000U) +#define LPUART_CTRL_SBK_SHIFT (16U) +/*! SBK - Send Break + * 0b0..Normal transmitter operation. + * 0b1..Queue break character(s) to be sent. + */ +#define LPUART_CTRL_SBK(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_SBK_SHIFT)) & LPUART_CTRL_SBK_MASK) +#define LPUART_CTRL_RWU_MASK (0x20000U) +#define LPUART_CTRL_RWU_SHIFT (17U) +/*! RWU - Receiver Wakeup Control + * 0b0..Normal receiver operation. + * 0b1..LPUART receiver in standby waiting for wakeup condition. + */ +#define LPUART_CTRL_RWU(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_RWU_SHIFT)) & LPUART_CTRL_RWU_MASK) +#define LPUART_CTRL_RE_MASK (0x40000U) +#define LPUART_CTRL_RE_SHIFT (18U) +/*! RE - Receiver Enable + * 0b0..Receiver disabled. + * 0b1..Receiver enabled. + */ +#define LPUART_CTRL_RE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_RE_SHIFT)) & LPUART_CTRL_RE_MASK) +#define LPUART_CTRL_TE_MASK (0x80000U) +#define LPUART_CTRL_TE_SHIFT (19U) +/*! TE - Transmitter Enable + * 0b0..Transmitter disabled. + * 0b1..Transmitter enabled. + */ +#define LPUART_CTRL_TE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_TE_SHIFT)) & LPUART_CTRL_TE_MASK) +#define LPUART_CTRL_ILIE_MASK (0x100000U) +#define LPUART_CTRL_ILIE_SHIFT (20U) +/*! ILIE - Idle Line Interrupt Enable + * 0b0..Hardware interrupts from IDLE disabled; use polling. + * 0b1..Hardware interrupt requested when IDLE flag is 1. + */ +#define LPUART_CTRL_ILIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_ILIE_SHIFT)) & LPUART_CTRL_ILIE_MASK) +#define LPUART_CTRL_RIE_MASK (0x200000U) +#define LPUART_CTRL_RIE_SHIFT (21U) +/*! RIE - Receiver Interrupt Enable + * 0b0..Hardware interrupts from RDRF disabled; use polling. + * 0b1..Hardware interrupt requested when RDRF flag is 1. + */ +#define LPUART_CTRL_RIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_RIE_SHIFT)) & LPUART_CTRL_RIE_MASK) +#define LPUART_CTRL_TCIE_MASK (0x400000U) +#define LPUART_CTRL_TCIE_SHIFT (22U) +/*! TCIE - Transmission Complete Interrupt Enable for + * 0b0..Hardware interrupts from TC disabled; use polling. + * 0b1..Hardware interrupt requested when TC flag is 1. + */ +#define LPUART_CTRL_TCIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_TCIE_SHIFT)) & LPUART_CTRL_TCIE_MASK) +#define LPUART_CTRL_TIE_MASK (0x800000U) +#define LPUART_CTRL_TIE_SHIFT (23U) +/*! TIE - Transmit Interrupt Enable + * 0b0..Hardware interrupts from TDRE disabled; use polling. + * 0b1..Hardware interrupt requested when TDRE flag is 1. + */ +#define LPUART_CTRL_TIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_TIE_SHIFT)) & LPUART_CTRL_TIE_MASK) +#define LPUART_CTRL_PEIE_MASK (0x1000000U) +#define LPUART_CTRL_PEIE_SHIFT (24U) +/*! PEIE - Parity Error Interrupt Enable + * 0b0..PF interrupts disabled; use polling). + * 0b1..Hardware interrupt requested when PF is set. + */ +#define LPUART_CTRL_PEIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_PEIE_SHIFT)) & LPUART_CTRL_PEIE_MASK) +#define LPUART_CTRL_FEIE_MASK (0x2000000U) +#define LPUART_CTRL_FEIE_SHIFT (25U) +/*! FEIE - Framing Error Interrupt Enable + * 0b0..FE interrupts disabled; use polling. + * 0b1..Hardware interrupt requested when FE is set. + */ +#define LPUART_CTRL_FEIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_FEIE_SHIFT)) & LPUART_CTRL_FEIE_MASK) +#define LPUART_CTRL_NEIE_MASK (0x4000000U) +#define LPUART_CTRL_NEIE_SHIFT (26U) +/*! NEIE - Noise Error Interrupt Enable + * 0b0..NF interrupts disabled; use polling. + * 0b1..Hardware interrupt requested when NF is set. + */ +#define LPUART_CTRL_NEIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_NEIE_SHIFT)) & LPUART_CTRL_NEIE_MASK) +#define LPUART_CTRL_ORIE_MASK (0x8000000U) +#define LPUART_CTRL_ORIE_SHIFT (27U) +/*! ORIE - Overrun Interrupt Enable + * 0b0..OR interrupts disabled; use polling. + * 0b1..Hardware interrupt requested when OR is set. + */ +#define LPUART_CTRL_ORIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_ORIE_SHIFT)) & LPUART_CTRL_ORIE_MASK) +#define LPUART_CTRL_TXINV_MASK (0x10000000U) +#define LPUART_CTRL_TXINV_SHIFT (28U) +/*! TXINV - Transmit Data Inversion + * 0b0..Transmit data not inverted. + * 0b1..Transmit data inverted. + */ +#define LPUART_CTRL_TXINV(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_TXINV_SHIFT)) & LPUART_CTRL_TXINV_MASK) +#define LPUART_CTRL_TXDIR_MASK (0x20000000U) +#define LPUART_CTRL_TXDIR_SHIFT (29U) +/*! TXDIR - TXD Pin Direction in Single-Wire Mode + * 0b0..TXD pin is an input in single-wire mode. + * 0b1..TXD pin is an output in single-wire mode. + */ +#define LPUART_CTRL_TXDIR(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_TXDIR_SHIFT)) & LPUART_CTRL_TXDIR_MASK) +#define LPUART_CTRL_R9T8_MASK (0x40000000U) +#define LPUART_CTRL_R9T8_SHIFT (30U) +#define LPUART_CTRL_R9T8(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_R9T8_SHIFT)) & LPUART_CTRL_R9T8_MASK) +#define LPUART_CTRL_R8T9_MASK (0x80000000U) +#define LPUART_CTRL_R8T9_SHIFT (31U) +#define LPUART_CTRL_R8T9(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_R8T9_SHIFT)) & LPUART_CTRL_R8T9_MASK) +/*! @} */ + +/*! @name DATA - LPUART Data Register */ +/*! @{ */ +#define LPUART_DATA_R0T0_MASK (0x1U) +#define LPUART_DATA_R0T0_SHIFT (0U) +#define LPUART_DATA_R0T0(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R0T0_SHIFT)) & LPUART_DATA_R0T0_MASK) +#define LPUART_DATA_R1T1_MASK (0x2U) +#define LPUART_DATA_R1T1_SHIFT (1U) +#define LPUART_DATA_R1T1(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R1T1_SHIFT)) & LPUART_DATA_R1T1_MASK) +#define LPUART_DATA_R2T2_MASK (0x4U) +#define LPUART_DATA_R2T2_SHIFT (2U) +#define LPUART_DATA_R2T2(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R2T2_SHIFT)) & LPUART_DATA_R2T2_MASK) +#define LPUART_DATA_R3T3_MASK (0x8U) +#define LPUART_DATA_R3T3_SHIFT (3U) +#define LPUART_DATA_R3T3(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R3T3_SHIFT)) & LPUART_DATA_R3T3_MASK) +#define LPUART_DATA_R4T4_MASK (0x10U) +#define LPUART_DATA_R4T4_SHIFT (4U) +#define LPUART_DATA_R4T4(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R4T4_SHIFT)) & LPUART_DATA_R4T4_MASK) +#define LPUART_DATA_R5T5_MASK (0x20U) +#define LPUART_DATA_R5T5_SHIFT (5U) +#define LPUART_DATA_R5T5(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R5T5_SHIFT)) & LPUART_DATA_R5T5_MASK) +#define LPUART_DATA_R6T6_MASK (0x40U) +#define LPUART_DATA_R6T6_SHIFT (6U) +#define LPUART_DATA_R6T6(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R6T6_SHIFT)) & LPUART_DATA_R6T6_MASK) +#define LPUART_DATA_R7T7_MASK (0x80U) +#define LPUART_DATA_R7T7_SHIFT (7U) +#define LPUART_DATA_R7T7(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R7T7_SHIFT)) & LPUART_DATA_R7T7_MASK) +#define LPUART_DATA_R8T8_MASK (0x100U) +#define LPUART_DATA_R8T8_SHIFT (8U) +#define LPUART_DATA_R8T8(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R8T8_SHIFT)) & LPUART_DATA_R8T8_MASK) +#define LPUART_DATA_R9T9_MASK (0x200U) +#define LPUART_DATA_R9T9_SHIFT (9U) +#define LPUART_DATA_R9T9(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R9T9_SHIFT)) & LPUART_DATA_R9T9_MASK) +#define LPUART_DATA_IDLINE_MASK (0x800U) +#define LPUART_DATA_IDLINE_SHIFT (11U) +/*! IDLINE - Idle Line + * 0b0..Receiver was not idle before receiving this character. + * 0b1..Receiver was idle before receiving this character. + */ +#define LPUART_DATA_IDLINE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_IDLINE_SHIFT)) & LPUART_DATA_IDLINE_MASK) +#define LPUART_DATA_RXEMPT_MASK (0x1000U) +#define LPUART_DATA_RXEMPT_SHIFT (12U) +/*! RXEMPT - Receive Buffer Empty + * 0b0..Receive buffer contains valid data. + * 0b1..Receive buffer is empty, data returned on read is not valid. + */ +#define LPUART_DATA_RXEMPT(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_RXEMPT_SHIFT)) & LPUART_DATA_RXEMPT_MASK) +#define LPUART_DATA_FRETSC_MASK (0x2000U) +#define LPUART_DATA_FRETSC_SHIFT (13U) +/*! FRETSC - Frame Error / Transmit Special Character + * 0b0..The dataword was received without a frame error on read, or transmit a normal character on write. + * 0b1..The dataword was received with a frame error, or transmit an idle or break character on transmit. + */ +#define LPUART_DATA_FRETSC(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_FRETSC_SHIFT)) & LPUART_DATA_FRETSC_MASK) +#define LPUART_DATA_PARITYE_MASK (0x4000U) +#define LPUART_DATA_PARITYE_SHIFT (14U) +/*! PARITYE - PARITYE + * 0b0..The dataword was received without a parity error. + * 0b1..The dataword was received with a parity error. + */ +#define LPUART_DATA_PARITYE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_PARITYE_SHIFT)) & LPUART_DATA_PARITYE_MASK) +#define LPUART_DATA_NOISY_MASK (0x8000U) +#define LPUART_DATA_NOISY_SHIFT (15U) +/*! NOISY - NOISY + * 0b0..The dataword was received without noise. + * 0b1..The data was received with noise. + */ +#define LPUART_DATA_NOISY(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_NOISY_SHIFT)) & LPUART_DATA_NOISY_MASK) +/*! @} */ + +/*! @name MATCH - LPUART Match Address Register */ +/*! @{ */ +#define LPUART_MATCH_MA1_MASK (0x3FFU) +#define LPUART_MATCH_MA1_SHIFT (0U) +#define LPUART_MATCH_MA1(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MATCH_MA1_SHIFT)) & LPUART_MATCH_MA1_MASK) +#define LPUART_MATCH_MA2_MASK (0x3FF0000U) +#define LPUART_MATCH_MA2_SHIFT (16U) +#define LPUART_MATCH_MA2(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MATCH_MA2_SHIFT)) & LPUART_MATCH_MA2_MASK) +/*! @} */ + +/*! @name MODIR - LPUART Modem IrDA Register */ +/*! @{ */ +#define LPUART_MODIR_TXCTSE_MASK (0x1U) +#define LPUART_MODIR_TXCTSE_SHIFT (0U) +/*! TXCTSE - Transmitter clear-to-send enable + * 0b0..CTS has no effect on the transmitter. + * 0b1..Enables clear-to-send operation. The transmitter checks the state of CTS each time it is ready to send a character. If CTS is asserted, the character is sent. If CTS is deasserted, the signal TXD remains in the mark state and transmission is delayed until CTS is asserted. Changes in CTS as a character is being sent do not affect its transmission. + */ +#define LPUART_MODIR_TXCTSE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TXCTSE_SHIFT)) & LPUART_MODIR_TXCTSE_MASK) +#define LPUART_MODIR_TXRTSE_MASK (0x2U) +#define LPUART_MODIR_TXRTSE_SHIFT (1U) +/*! TXRTSE - Transmitter request-to-send enable + * 0b0..The transmitter has no effect on RTS. + * 0b1..When a character is placed into an empty transmitter data buffer , RTS asserts one bit time before the start bit is transmitted. RTS deasserts one bit time after all characters in the transmitter data buffer and shift register are completely sent, including the last stop bit. + */ +#define LPUART_MODIR_TXRTSE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TXRTSE_SHIFT)) & LPUART_MODIR_TXRTSE_MASK) +#define LPUART_MODIR_TXRTSPOL_MASK (0x4U) +#define LPUART_MODIR_TXRTSPOL_SHIFT (2U) +/*! TXRTSPOL - Transmitter request-to-send polarity + * 0b0..Transmitter RTS is active low. + * 0b1..Transmitter RTS is active high. + */ +#define LPUART_MODIR_TXRTSPOL(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TXRTSPOL_SHIFT)) & LPUART_MODIR_TXRTSPOL_MASK) +#define LPUART_MODIR_RXRTSE_MASK (0x8U) +#define LPUART_MODIR_RXRTSE_SHIFT (3U) +/*! RXRTSE - Receiver request-to-send enable + * 0b0..The receiver has no effect on RTS. + * 0b1..RTS is deasserted if the receiver data register is full or a start bit has been detected that would cause the receiver data register to become full. RTS is asserted if the receiver data register is not full and has not detected a start bit that would cause the receiver data register to become full. + */ +#define LPUART_MODIR_RXRTSE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_RXRTSE_SHIFT)) & LPUART_MODIR_RXRTSE_MASK) +#define LPUART_MODIR_TXCTSC_MASK (0x10U) +#define LPUART_MODIR_TXCTSC_SHIFT (4U) +/*! TXCTSC - Transmit CTS Configuration + * 0b0..CTS input is sampled at the start of each character. + * 0b1..CTS input is sampled when the transmitter is idle. + */ +#define LPUART_MODIR_TXCTSC(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TXCTSC_SHIFT)) & LPUART_MODIR_TXCTSC_MASK) +#define LPUART_MODIR_TXCTSSRC_MASK (0x20U) +#define LPUART_MODIR_TXCTSSRC_SHIFT (5U) +/*! TXCTSSRC - Transmit CTS Source + * 0b0..CTS input is the CTS_B pin. + * 0b1..CTS input is the inverted Receiver Match result. + */ +#define LPUART_MODIR_TXCTSSRC(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TXCTSSRC_SHIFT)) & LPUART_MODIR_TXCTSSRC_MASK) +#define LPUART_MODIR_RTSWATER_MASK (0x300U) +#define LPUART_MODIR_RTSWATER_SHIFT (8U) +#define LPUART_MODIR_RTSWATER(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_RTSWATER_SHIFT)) & LPUART_MODIR_RTSWATER_MASK) +#define LPUART_MODIR_TNP_MASK (0x30000U) +#define LPUART_MODIR_TNP_SHIFT (16U) +/*! TNP - Transmitter narrow pulse + * 0b00..1/OSR. + * 0b01..2/OSR. + * 0b10..3/OSR. + * 0b11..4/OSR. + */ +#define LPUART_MODIR_TNP(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TNP_SHIFT)) & LPUART_MODIR_TNP_MASK) +#define LPUART_MODIR_IREN_MASK (0x40000U) +#define LPUART_MODIR_IREN_SHIFT (18U) +/*! IREN - Infrared enable + * 0b0..IR disabled. + * 0b1..IR enabled. + */ +#define LPUART_MODIR_IREN(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_IREN_SHIFT)) & LPUART_MODIR_IREN_MASK) +/*! @} */ + +/*! @name FIFO - LPUART FIFO Register */ +/*! @{ */ +#define LPUART_FIFO_RXFIFOSIZE_MASK (0x7U) +#define LPUART_FIFO_RXFIFOSIZE_SHIFT (0U) +/*! RXFIFOSIZE - Receive FIFO Buffer Depth + * 0b000..Receive FIFO/Buffer depth = 1 dataword. + * 0b001..Receive FIFO/Buffer depth = 4 datawords. + * 0b010..Receive FIFO/Buffer depth = 8 datawords. + * 0b011..Receive FIFO/Buffer depth = 16 datawords. + * 0b100..Receive FIFO/Buffer depth = 32 datawords. + * 0b101..Receive FIFO/Buffer depth = 64 datawords. + * 0b110..Receive FIFO/Buffer depth = 128 datawords. + * 0b111..Receive FIFO/Buffer depth = 256 datawords. + */ +#define LPUART_FIFO_RXFIFOSIZE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_RXFIFOSIZE_SHIFT)) & LPUART_FIFO_RXFIFOSIZE_MASK) +#define LPUART_FIFO_RXFE_MASK (0x8U) +#define LPUART_FIFO_RXFE_SHIFT (3U) +/*! RXFE - Receive FIFO Enable + * 0b0..Receive FIFO is not enabled. Buffer is depth 1. + * 0b1..Receive FIFO is enabled. Buffer is depth indicted by RXFIFOSIZE. + */ +#define LPUART_FIFO_RXFE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_RXFE_SHIFT)) & LPUART_FIFO_RXFE_MASK) +#define LPUART_FIFO_TXFIFOSIZE_MASK (0x70U) +#define LPUART_FIFO_TXFIFOSIZE_SHIFT (4U) +/*! TXFIFOSIZE - Transmit FIFO Buffer Depth + * 0b000..Transmit FIFO/Buffer depth = 1 dataword. + * 0b001..Transmit FIFO/Buffer depth = 4 datawords. + * 0b010..Transmit FIFO/Buffer depth = 8 datawords. + * 0b011..Transmit FIFO/Buffer depth = 16 datawords. + * 0b100..Transmit FIFO/Buffer depth = 32 datawords. + * 0b101..Transmit FIFO/Buffer depth = 64 datawords. + * 0b110..Transmit FIFO/Buffer depth = 128 datawords. + * 0b111..Transmit FIFO/Buffer depth = 256 datawords + */ +#define LPUART_FIFO_TXFIFOSIZE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_TXFIFOSIZE_SHIFT)) & LPUART_FIFO_TXFIFOSIZE_MASK) +#define LPUART_FIFO_TXFE_MASK (0x80U) +#define LPUART_FIFO_TXFE_SHIFT (7U) +/*! TXFE - Transmit FIFO Enable + * 0b0..Transmit FIFO is not enabled. Buffer is depth 1. + * 0b1..Transmit FIFO is enabled. Buffer is depth indicated by TXFIFOSIZE. + */ +#define LPUART_FIFO_TXFE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_TXFE_SHIFT)) & LPUART_FIFO_TXFE_MASK) +#define LPUART_FIFO_RXUFE_MASK (0x100U) +#define LPUART_FIFO_RXUFE_SHIFT (8U) +/*! RXUFE - Receive FIFO Underflow Interrupt Enable + * 0b0..RXUF flag does not generate an interrupt to the host. + * 0b1..RXUF flag generates an interrupt to the host. + */ +#define LPUART_FIFO_RXUFE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_RXUFE_SHIFT)) & LPUART_FIFO_RXUFE_MASK) +#define LPUART_FIFO_TXOFE_MASK (0x200U) +#define LPUART_FIFO_TXOFE_SHIFT (9U) +/*! TXOFE - Transmit FIFO Overflow Interrupt Enable + * 0b0..TXOF flag does not generate an interrupt to the host. + * 0b1..TXOF flag generates an interrupt to the host. + */ +#define LPUART_FIFO_TXOFE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_TXOFE_SHIFT)) & LPUART_FIFO_TXOFE_MASK) +#define LPUART_FIFO_RXIDEN_MASK (0x1C00U) +#define LPUART_FIFO_RXIDEN_SHIFT (10U) +/*! RXIDEN - Receiver Idle Empty Enable + * 0b000..Disable RDRF assertion due to partially filled FIFO when receiver is idle. + * 0b001..Enable RDRF assertion due to partially filled FIFO when receiver is idle for 1 character. + * 0b010..Enable RDRF assertion due to partially filled FIFO when receiver is idle for 2 characters. + * 0b011..Enable RDRF assertion due to partially filled FIFO when receiver is idle for 4 characters. + * 0b100..Enable RDRF assertion due to partially filled FIFO when receiver is idle for 8 characters. + * 0b101..Enable RDRF assertion due to partially filled FIFO when receiver is idle for 16 characters. + * 0b110..Enable RDRF assertion due to partially filled FIFO when receiver is idle for 32 characters. + * 0b111..Enable RDRF assertion due to partially filled FIFO when receiver is idle for 64 characters. + */ +#define LPUART_FIFO_RXIDEN(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_RXIDEN_SHIFT)) & LPUART_FIFO_RXIDEN_MASK) +#define LPUART_FIFO_RXFLUSH_MASK (0x4000U) +#define LPUART_FIFO_RXFLUSH_SHIFT (14U) +/*! RXFLUSH - Receive FIFO/Buffer Flush + * 0b0..No flush operation occurs. + * 0b1..All data in the receive FIFO/buffer is cleared out. + */ +#define LPUART_FIFO_RXFLUSH(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_RXFLUSH_SHIFT)) & LPUART_FIFO_RXFLUSH_MASK) +#define LPUART_FIFO_TXFLUSH_MASK (0x8000U) +#define LPUART_FIFO_TXFLUSH_SHIFT (15U) +/*! TXFLUSH - Transmit FIFO/Buffer Flush + * 0b0..No flush operation occurs. + * 0b1..All data in the transmit FIFO/Buffer is cleared out. + */ +#define LPUART_FIFO_TXFLUSH(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_TXFLUSH_SHIFT)) & LPUART_FIFO_TXFLUSH_MASK) +#define LPUART_FIFO_RXUF_MASK (0x10000U) +#define LPUART_FIFO_RXUF_SHIFT (16U) +/*! RXUF - Receiver Buffer Underflow Flag + * 0b0..No receive buffer underflow has occurred since the last time the flag was cleared. + * 0b1..At least one receive buffer underflow has occurred since the last time the flag was cleared. + */ +#define LPUART_FIFO_RXUF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_RXUF_SHIFT)) & LPUART_FIFO_RXUF_MASK) +#define LPUART_FIFO_TXOF_MASK (0x20000U) +#define LPUART_FIFO_TXOF_SHIFT (17U) +/*! TXOF - Transmitter Buffer Overflow Flag + * 0b0..No transmit buffer overflow has occurred since the last time the flag was cleared. + * 0b1..At least one transmit buffer overflow has occurred since the last time the flag was cleared. + */ +#define LPUART_FIFO_TXOF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_TXOF_SHIFT)) & LPUART_FIFO_TXOF_MASK) +#define LPUART_FIFO_RXEMPT_MASK (0x400000U) +#define LPUART_FIFO_RXEMPT_SHIFT (22U) +/*! RXEMPT - Receive Buffer/FIFO Empty + * 0b0..Receive buffer is not empty. + * 0b1..Receive buffer is empty. + */ +#define LPUART_FIFO_RXEMPT(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_RXEMPT_SHIFT)) & LPUART_FIFO_RXEMPT_MASK) +#define LPUART_FIFO_TXEMPT_MASK (0x800000U) +#define LPUART_FIFO_TXEMPT_SHIFT (23U) +/*! TXEMPT - Transmit Buffer/FIFO Empty + * 0b0..Transmit buffer is not empty. + * 0b1..Transmit buffer is empty. + */ +#define LPUART_FIFO_TXEMPT(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_TXEMPT_SHIFT)) & LPUART_FIFO_TXEMPT_MASK) +/*! @} */ + +/*! @name WATER - LPUART Watermark Register */ +/*! @{ */ +#define LPUART_WATER_TXWATER_MASK (0x3U) +#define LPUART_WATER_TXWATER_SHIFT (0U) +#define LPUART_WATER_TXWATER(x) (((uint32_t)(((uint32_t)(x)) << LPUART_WATER_TXWATER_SHIFT)) & LPUART_WATER_TXWATER_MASK) +#define LPUART_WATER_TXCOUNT_MASK (0x700U) +#define LPUART_WATER_TXCOUNT_SHIFT (8U) +#define LPUART_WATER_TXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << LPUART_WATER_TXCOUNT_SHIFT)) & LPUART_WATER_TXCOUNT_MASK) +#define LPUART_WATER_RXWATER_MASK (0x30000U) +#define LPUART_WATER_RXWATER_SHIFT (16U) +#define LPUART_WATER_RXWATER(x) (((uint32_t)(((uint32_t)(x)) << LPUART_WATER_RXWATER_SHIFT)) & LPUART_WATER_RXWATER_MASK) +#define LPUART_WATER_RXCOUNT_MASK (0x7000000U) +#define LPUART_WATER_RXCOUNT_SHIFT (24U) +#define LPUART_WATER_RXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << LPUART_WATER_RXCOUNT_SHIFT)) & LPUART_WATER_RXCOUNT_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group LPUART_Register_Masks */ + + +/* LPUART - Peripheral instance base addresses */ +/** Peripheral LPUART1 base address */ +#define LPUART1_BASE (0x40184000u) +/** Peripheral LPUART1 base pointer */ +#define LPUART1 ((LPUART_Type *)LPUART1_BASE) +/** Peripheral LPUART2 base address */ +#define LPUART2_BASE (0x40188000u) +/** Peripheral LPUART2 base pointer */ +#define LPUART2 ((LPUART_Type *)LPUART2_BASE) +/** Peripheral LPUART3 base address */ +#define LPUART3_BASE (0x4018C000u) +/** Peripheral LPUART3 base pointer */ +#define LPUART3 ((LPUART_Type *)LPUART3_BASE) +/** Peripheral LPUART4 base address */ +#define LPUART4_BASE (0x40190000u) +/** Peripheral LPUART4 base pointer */ +#define LPUART4 ((LPUART_Type *)LPUART4_BASE) +/** Peripheral LPUART5 base address */ +#define LPUART5_BASE (0x40194000u) +/** Peripheral LPUART5 base pointer */ +#define LPUART5 ((LPUART_Type *)LPUART5_BASE) +/** Peripheral LPUART6 base address */ +#define LPUART6_BASE (0x40198000u) +/** Peripheral LPUART6 base pointer */ +#define LPUART6 ((LPUART_Type *)LPUART6_BASE) +/** Peripheral LPUART7 base address */ +#define LPUART7_BASE (0x4019C000u) +/** Peripheral LPUART7 base pointer */ +#define LPUART7 ((LPUART_Type *)LPUART7_BASE) +/** Peripheral LPUART8 base address */ +#define LPUART8_BASE (0x401A0000u) +/** Peripheral LPUART8 base pointer */ +#define LPUART8 ((LPUART_Type *)LPUART8_BASE) +/** Array initializer of LPUART peripheral base addresses */ +#define LPUART_BASE_ADDRS { 0u, LPUART1_BASE, LPUART2_BASE, LPUART3_BASE, LPUART4_BASE, LPUART5_BASE, LPUART6_BASE, LPUART7_BASE, LPUART8_BASE } +/** Array initializer of LPUART peripheral base pointers */ +#define LPUART_BASE_PTRS { (LPUART_Type *)0u, LPUART1, LPUART2, LPUART3, LPUART4, LPUART5, LPUART6, LPUART7, LPUART8 } +/** Interrupt vectors for the LPUART peripheral type */ +#define LPUART_RX_TX_IRQS { NotAvail_IRQn, LPUART1_IRQn, LPUART2_IRQn, LPUART3_IRQn, LPUART4_IRQn, LPUART5_IRQn, LPUART6_IRQn, LPUART7_IRQn, LPUART8_IRQn } + +/*! + * @} + */ /* end of group LPUART_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- OCOTP Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup OCOTP_Peripheral_Access_Layer OCOTP Peripheral Access Layer + * @{ + */ + +/** OCOTP - Register Layout Typedef */ +typedef struct { + __IO uint32_t CTRL; /**< OTP Controller Control Register, offset: 0x0 */ + __IO uint32_t CTRL_SET; /**< OTP Controller Control Register, offset: 0x4 */ + __IO uint32_t CTRL_CLR; /**< OTP Controller Control Register, offset: 0x8 */ + __IO uint32_t CTRL_TOG; /**< OTP Controller Control Register, offset: 0xC */ + __IO uint32_t TIMING; /**< OTP Controller Timing Register, offset: 0x10 */ + uint8_t RESERVED_0[12]; + __IO uint32_t DATA; /**< OTP Controller Write Data Register, offset: 0x20 */ + uint8_t RESERVED_1[12]; + __IO uint32_t READ_CTRL; /**< OTP Controller Write Data Register, offset: 0x30 */ + uint8_t RESERVED_2[12]; + __IO uint32_t READ_FUSE_DATA; /**< OTP Controller Read Data Register, offset: 0x40 */ + uint8_t RESERVED_3[12]; + __IO uint32_t SW_STICKY; /**< Sticky bit Register, offset: 0x50 */ + uint8_t RESERVED_4[12]; + __IO uint32_t SCS; /**< Software Controllable Signals Register, offset: 0x60 */ + __IO uint32_t SCS_SET; /**< Software Controllable Signals Register, offset: 0x64 */ + __IO uint32_t SCS_CLR; /**< Software Controllable Signals Register, offset: 0x68 */ + __IO uint32_t SCS_TOG; /**< Software Controllable Signals Register, offset: 0x6C */ + uint8_t RESERVED_5[32]; + __I uint32_t VERSION; /**< OTP Controller Version Register, offset: 0x90 */ + uint8_t RESERVED_6[108]; + __IO uint32_t TIMING2; /**< OTP Controller Timing Register 2, offset: 0x100 */ + uint8_t RESERVED_7[764]; + __IO uint32_t LOCK; /**< Value of OTP Bank0 Word0 (Lock controls), offset: 0x400 */ + uint8_t RESERVED_8[12]; + __IO uint32_t CFG0; /**< Value of OTP Bank0 Word1 (Configuration and Manufacturing Info.), offset: 0x410 */ + uint8_t RESERVED_9[12]; + __IO uint32_t CFG1; /**< Value of OTP Bank0 Word2 (Configuration and Manufacturing Info.), offset: 0x420 */ + uint8_t RESERVED_10[12]; + __IO uint32_t CFG2; /**< Value of OTP Bank0 Word3 (Configuration and Manufacturing Info.), offset: 0x430 */ + uint8_t RESERVED_11[12]; + __IO uint32_t CFG3; /**< Value of OTP Bank0 Word4 (Configuration and Manufacturing Info.), offset: 0x440 */ + uint8_t RESERVED_12[12]; + __IO uint32_t CFG4; /**< Value of OTP Bank0 Word5 (Configuration and Manufacturing Info.), offset: 0x450 */ + uint8_t RESERVED_13[12]; + __IO uint32_t CFG5; /**< Value of OTP Bank0 Word6 (Configuration and Manufacturing Info.), offset: 0x460 */ + uint8_t RESERVED_14[12]; + __IO uint32_t CFG6; /**< Value of OTP Bank0 Word7 (Configuration and Manufacturing Info.), offset: 0x470 */ + uint8_t RESERVED_15[12]; + __IO uint32_t MEM0; /**< Value of OTP Bank1 Word0 (Memory Related Info.), offset: 0x480 */ + uint8_t RESERVED_16[12]; + __IO uint32_t MEM1; /**< Value of OTP Bank1 Word1 (Memory Related Info.), offset: 0x490 */ + uint8_t RESERVED_17[12]; + __IO uint32_t MEM2; /**< Value of OTP Bank1 Word2 (Memory Related Info.), offset: 0x4A0 */ + uint8_t RESERVED_18[12]; + __IO uint32_t MEM3; /**< Value of OTP Bank1 Word3 (Memory Related Info.), offset: 0x4B0 */ + uint8_t RESERVED_19[12]; + __IO uint32_t MEM4; /**< Value of OTP Bank1 Word4 (Memory Related Info.), offset: 0x4C0 */ + uint8_t RESERVED_20[12]; + __IO uint32_t ANA0; /**< Value of OTP Bank1 Word5 (Analog Info.), offset: 0x4D0 */ + uint8_t RESERVED_21[12]; + __IO uint32_t ANA1; /**< Value of OTP Bank1 Word6 (Analog Info.), offset: 0x4E0 */ + uint8_t RESERVED_22[12]; + __IO uint32_t ANA2; /**< Value of OTP Bank1 Word7 (Analog Info.), offset: 0x4F0 */ + uint8_t RESERVED_23[140]; + __IO uint32_t SRK0; /**< Shadow Register for OTP Bank3 Word0 (SRK Hash), offset: 0x580 */ + uint8_t RESERVED_24[12]; + __IO uint32_t SRK1; /**< Shadow Register for OTP Bank3 Word1 (SRK Hash), offset: 0x590 */ + uint8_t RESERVED_25[12]; + __IO uint32_t SRK2; /**< Shadow Register for OTP Bank3 Word2 (SRK Hash), offset: 0x5A0 */ + uint8_t RESERVED_26[12]; + __IO uint32_t SRK3; /**< Shadow Register for OTP Bank3 Word3 (SRK Hash), offset: 0x5B0 */ + uint8_t RESERVED_27[12]; + __IO uint32_t SRK4; /**< Shadow Register for OTP Bank3 Word4 (SRK Hash), offset: 0x5C0 */ + uint8_t RESERVED_28[12]; + __IO uint32_t SRK5; /**< Shadow Register for OTP Bank3 Word5 (SRK Hash), offset: 0x5D0 */ + uint8_t RESERVED_29[12]; + __IO uint32_t SRK6; /**< Shadow Register for OTP Bank3 Word6 (SRK Hash), offset: 0x5E0 */ + uint8_t RESERVED_30[12]; + __IO uint32_t SRK7; /**< Shadow Register for OTP Bank3 Word7 (SRK Hash), offset: 0x5F0 */ + uint8_t RESERVED_31[12]; + __IO uint32_t SJC_RESP0; /**< Value of OTP Bank4 Word0 (Secure JTAG Response Field), offset: 0x600 */ + uint8_t RESERVED_32[12]; + __IO uint32_t SJC_RESP1; /**< Value of OTP Bank4 Word1 (Secure JTAG Response Field), offset: 0x610 */ + uint8_t RESERVED_33[12]; + __IO uint32_t MAC0; /**< Value of OTP Bank4 Word2 (MAC Address), offset: 0x620 */ + uint8_t RESERVED_34[12]; + __IO uint32_t MAC1; /**< Value of OTP Bank4 Word3 (MAC Address), offset: 0x630 */ + uint8_t RESERVED_35[12]; + __IO uint32_t GP3; /**< Value of OTP Bank4 Word4 (MAC Address), offset: 0x640 */ + uint8_t RESERVED_36[28]; + __IO uint32_t GP1; /**< Value of OTP Bank4 Word6 (General Purpose Customer Defined Info), offset: 0x660 */ + uint8_t RESERVED_37[12]; + __IO uint32_t GP2; /**< Value of OTP Bank4 Word7 (General Purpose Customer Defined Info), offset: 0x670 */ + uint8_t RESERVED_38[12]; + __IO uint32_t SW_GP1; /**< Value of OTP Bank5 Word0 (SW GP1), offset: 0x680 */ + uint8_t RESERVED_39[12]; + __IO uint32_t SW_GP20; /**< Value of OTP Bank5 Word1 (SW GP2), offset: 0x690 */ + uint8_t RESERVED_40[12]; + __IO uint32_t SW_GP21; /**< Value of OTP Bank5 Word2 (SW GP2), offset: 0x6A0 */ + uint8_t RESERVED_41[12]; + __IO uint32_t SW_GP22; /**< Value of OTP Bank5 Word3 (SW GP2), offset: 0x6B0 */ + uint8_t RESERVED_42[12]; + __IO uint32_t SW_GP23; /**< Value of OTP Bank5 Word4 (SW GP2), offset: 0x6C0 */ + uint8_t RESERVED_43[12]; + __IO uint32_t MISC_CONF0; /**< Value of OTP Bank5 Word5 (Misc Conf), offset: 0x6D0 */ + uint8_t RESERVED_44[12]; + __IO uint32_t MISC_CONF1; /**< Value of OTP Bank5 Word6 (Misc Conf), offset: 0x6E0 */ + uint8_t RESERVED_45[12]; + __IO uint32_t SRK_REVOKE; /**< Value of OTP Bank5 Word7 (SRK Revoke), offset: 0x6F0 */ +} OCOTP_Type; + +/* ---------------------------------------------------------------------------- + -- OCOTP Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup OCOTP_Register_Masks OCOTP Register Masks + * @{ + */ + +/*! @name CTRL - OTP Controller Control Register */ +/*! @{ */ +#define OCOTP_CTRL_ADDR_MASK (0x3FU) +#define OCOTP_CTRL_ADDR_SHIFT (0U) +#define OCOTP_CTRL_ADDR(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_ADDR_SHIFT)) & OCOTP_CTRL_ADDR_MASK) +#define OCOTP_CTRL_BUSY_MASK (0x100U) +#define OCOTP_CTRL_BUSY_SHIFT (8U) +#define OCOTP_CTRL_BUSY(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_BUSY_SHIFT)) & OCOTP_CTRL_BUSY_MASK) +#define OCOTP_CTRL_ERROR_MASK (0x200U) +#define OCOTP_CTRL_ERROR_SHIFT (9U) +#define OCOTP_CTRL_ERROR(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_ERROR_SHIFT)) & OCOTP_CTRL_ERROR_MASK) +#define OCOTP_CTRL_RELOAD_SHADOWS_MASK (0x400U) +#define OCOTP_CTRL_RELOAD_SHADOWS_SHIFT (10U) +#define OCOTP_CTRL_RELOAD_SHADOWS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_RELOAD_SHADOWS_SHIFT)) & OCOTP_CTRL_RELOAD_SHADOWS_MASK) +#define OCOTP_CTRL_WR_UNLOCK_MASK (0xFFFF0000U) +#define OCOTP_CTRL_WR_UNLOCK_SHIFT (16U) +#define OCOTP_CTRL_WR_UNLOCK(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_WR_UNLOCK_SHIFT)) & OCOTP_CTRL_WR_UNLOCK_MASK) +/*! @} */ + +/*! @name CTRL_SET - OTP Controller Control Register */ +/*! @{ */ +#define OCOTP_CTRL_SET_ADDR_MASK (0x3FU) +#define OCOTP_CTRL_SET_ADDR_SHIFT (0U) +#define OCOTP_CTRL_SET_ADDR(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_SET_ADDR_SHIFT)) & OCOTP_CTRL_SET_ADDR_MASK) +#define OCOTP_CTRL_SET_BUSY_MASK (0x100U) +#define OCOTP_CTRL_SET_BUSY_SHIFT (8U) +#define OCOTP_CTRL_SET_BUSY(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_SET_BUSY_SHIFT)) & OCOTP_CTRL_SET_BUSY_MASK) +#define OCOTP_CTRL_SET_ERROR_MASK (0x200U) +#define OCOTP_CTRL_SET_ERROR_SHIFT (9U) +#define OCOTP_CTRL_SET_ERROR(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_SET_ERROR_SHIFT)) & OCOTP_CTRL_SET_ERROR_MASK) +#define OCOTP_CTRL_SET_RELOAD_SHADOWS_MASK (0x400U) +#define OCOTP_CTRL_SET_RELOAD_SHADOWS_SHIFT (10U) +#define OCOTP_CTRL_SET_RELOAD_SHADOWS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_SET_RELOAD_SHADOWS_SHIFT)) & OCOTP_CTRL_SET_RELOAD_SHADOWS_MASK) +#define OCOTP_CTRL_SET_WR_UNLOCK_MASK (0xFFFF0000U) +#define OCOTP_CTRL_SET_WR_UNLOCK_SHIFT (16U) +#define OCOTP_CTRL_SET_WR_UNLOCK(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_SET_WR_UNLOCK_SHIFT)) & OCOTP_CTRL_SET_WR_UNLOCK_MASK) +/*! @} */ + +/*! @name CTRL_CLR - OTP Controller Control Register */ +/*! @{ */ +#define OCOTP_CTRL_CLR_ADDR_MASK (0x3FU) +#define OCOTP_CTRL_CLR_ADDR_SHIFT (0U) +#define OCOTP_CTRL_CLR_ADDR(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_CLR_ADDR_SHIFT)) & OCOTP_CTRL_CLR_ADDR_MASK) +#define OCOTP_CTRL_CLR_BUSY_MASK (0x100U) +#define OCOTP_CTRL_CLR_BUSY_SHIFT (8U) +#define OCOTP_CTRL_CLR_BUSY(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_CLR_BUSY_SHIFT)) & OCOTP_CTRL_CLR_BUSY_MASK) +#define OCOTP_CTRL_CLR_ERROR_MASK (0x200U) +#define OCOTP_CTRL_CLR_ERROR_SHIFT (9U) +#define OCOTP_CTRL_CLR_ERROR(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_CLR_ERROR_SHIFT)) & OCOTP_CTRL_CLR_ERROR_MASK) +#define OCOTP_CTRL_CLR_RELOAD_SHADOWS_MASK (0x400U) +#define OCOTP_CTRL_CLR_RELOAD_SHADOWS_SHIFT (10U) +#define OCOTP_CTRL_CLR_RELOAD_SHADOWS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_CLR_RELOAD_SHADOWS_SHIFT)) & OCOTP_CTRL_CLR_RELOAD_SHADOWS_MASK) +#define OCOTP_CTRL_CLR_WR_UNLOCK_MASK (0xFFFF0000U) +#define OCOTP_CTRL_CLR_WR_UNLOCK_SHIFT (16U) +#define OCOTP_CTRL_CLR_WR_UNLOCK(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_CLR_WR_UNLOCK_SHIFT)) & OCOTP_CTRL_CLR_WR_UNLOCK_MASK) +/*! @} */ + +/*! @name CTRL_TOG - OTP Controller Control Register */ +/*! @{ */ +#define OCOTP_CTRL_TOG_ADDR_MASK (0x3FU) +#define OCOTP_CTRL_TOG_ADDR_SHIFT (0U) +#define OCOTP_CTRL_TOG_ADDR(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_TOG_ADDR_SHIFT)) & OCOTP_CTRL_TOG_ADDR_MASK) +#define OCOTP_CTRL_TOG_BUSY_MASK (0x100U) +#define OCOTP_CTRL_TOG_BUSY_SHIFT (8U) +#define OCOTP_CTRL_TOG_BUSY(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_TOG_BUSY_SHIFT)) & OCOTP_CTRL_TOG_BUSY_MASK) +#define OCOTP_CTRL_TOG_ERROR_MASK (0x200U) +#define OCOTP_CTRL_TOG_ERROR_SHIFT (9U) +#define OCOTP_CTRL_TOG_ERROR(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_TOG_ERROR_SHIFT)) & OCOTP_CTRL_TOG_ERROR_MASK) +#define OCOTP_CTRL_TOG_RELOAD_SHADOWS_MASK (0x400U) +#define OCOTP_CTRL_TOG_RELOAD_SHADOWS_SHIFT (10U) +#define OCOTP_CTRL_TOG_RELOAD_SHADOWS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_TOG_RELOAD_SHADOWS_SHIFT)) & OCOTP_CTRL_TOG_RELOAD_SHADOWS_MASK) +#define OCOTP_CTRL_TOG_WR_UNLOCK_MASK (0xFFFF0000U) +#define OCOTP_CTRL_TOG_WR_UNLOCK_SHIFT (16U) +#define OCOTP_CTRL_TOG_WR_UNLOCK(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_TOG_WR_UNLOCK_SHIFT)) & OCOTP_CTRL_TOG_WR_UNLOCK_MASK) +/*! @} */ + +/*! @name TIMING - OTP Controller Timing Register */ +/*! @{ */ +#define OCOTP_TIMING_STROBE_PROG_MASK (0xFFFU) +#define OCOTP_TIMING_STROBE_PROG_SHIFT (0U) +#define OCOTP_TIMING_STROBE_PROG(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_TIMING_STROBE_PROG_SHIFT)) & OCOTP_TIMING_STROBE_PROG_MASK) +#define OCOTP_TIMING_RELAX_MASK (0xF000U) +#define OCOTP_TIMING_RELAX_SHIFT (12U) +#define OCOTP_TIMING_RELAX(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_TIMING_RELAX_SHIFT)) & OCOTP_TIMING_RELAX_MASK) +#define OCOTP_TIMING_STROBE_READ_MASK (0x3F0000U) +#define OCOTP_TIMING_STROBE_READ_SHIFT (16U) +#define OCOTP_TIMING_STROBE_READ(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_TIMING_STROBE_READ_SHIFT)) & OCOTP_TIMING_STROBE_READ_MASK) +#define OCOTP_TIMING_WAIT_MASK (0xFC00000U) +#define OCOTP_TIMING_WAIT_SHIFT (22U) +#define OCOTP_TIMING_WAIT(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_TIMING_WAIT_SHIFT)) & OCOTP_TIMING_WAIT_MASK) +/*! @} */ + +/*! @name DATA - OTP Controller Write Data Register */ +/*! @{ */ +#define OCOTP_DATA_DATA_MASK (0xFFFFFFFFU) +#define OCOTP_DATA_DATA_SHIFT (0U) +#define OCOTP_DATA_DATA(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_DATA_DATA_SHIFT)) & OCOTP_DATA_DATA_MASK) +/*! @} */ + +/*! @name READ_CTRL - OTP Controller Write Data Register */ +/*! @{ */ +#define OCOTP_READ_CTRL_READ_FUSE_MASK (0x1U) +#define OCOTP_READ_CTRL_READ_FUSE_SHIFT (0U) +#define OCOTP_READ_CTRL_READ_FUSE(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_READ_CTRL_READ_FUSE_SHIFT)) & OCOTP_READ_CTRL_READ_FUSE_MASK) +/*! @} */ + +/*! @name READ_FUSE_DATA - OTP Controller Read Data Register */ +/*! @{ */ +#define OCOTP_READ_FUSE_DATA_DATA_MASK (0xFFFFFFFFU) +#define OCOTP_READ_FUSE_DATA_DATA_SHIFT (0U) +#define OCOTP_READ_FUSE_DATA_DATA(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_READ_FUSE_DATA_DATA_SHIFT)) & OCOTP_READ_FUSE_DATA_DATA_MASK) +/*! @} */ + +/*! @name SW_STICKY - Sticky bit Register */ +/*! @{ */ +#define OCOTP_SW_STICKY_BLOCK_DTCP_KEY_MASK (0x1U) +#define OCOTP_SW_STICKY_BLOCK_DTCP_KEY_SHIFT (0U) +#define OCOTP_SW_STICKY_BLOCK_DTCP_KEY(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SW_STICKY_BLOCK_DTCP_KEY_SHIFT)) & OCOTP_SW_STICKY_BLOCK_DTCP_KEY_MASK) +#define OCOTP_SW_STICKY_SRK_REVOKE_LOCK_MASK (0x2U) +#define OCOTP_SW_STICKY_SRK_REVOKE_LOCK_SHIFT (1U) +#define OCOTP_SW_STICKY_SRK_REVOKE_LOCK(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SW_STICKY_SRK_REVOKE_LOCK_SHIFT)) & OCOTP_SW_STICKY_SRK_REVOKE_LOCK_MASK) +#define OCOTP_SW_STICKY_FIELD_RETURN_LOCK_MASK (0x4U) +#define OCOTP_SW_STICKY_FIELD_RETURN_LOCK_SHIFT (2U) +#define OCOTP_SW_STICKY_FIELD_RETURN_LOCK(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SW_STICKY_FIELD_RETURN_LOCK_SHIFT)) & OCOTP_SW_STICKY_FIELD_RETURN_LOCK_MASK) +#define OCOTP_SW_STICKY_BLOCK_ROM_PART_MASK (0x8U) +#define OCOTP_SW_STICKY_BLOCK_ROM_PART_SHIFT (3U) +#define OCOTP_SW_STICKY_BLOCK_ROM_PART(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SW_STICKY_BLOCK_ROM_PART_SHIFT)) & OCOTP_SW_STICKY_BLOCK_ROM_PART_MASK) +#define OCOTP_SW_STICKY_JTAG_BLOCK_RELEASE_MASK (0x10U) +#define OCOTP_SW_STICKY_JTAG_BLOCK_RELEASE_SHIFT (4U) +#define OCOTP_SW_STICKY_JTAG_BLOCK_RELEASE(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SW_STICKY_JTAG_BLOCK_RELEASE_SHIFT)) & OCOTP_SW_STICKY_JTAG_BLOCK_RELEASE_MASK) +/*! @} */ + +/*! @name SCS - Software Controllable Signals Register */ +/*! @{ */ +#define OCOTP_SCS_HAB_JDE_MASK (0x1U) +#define OCOTP_SCS_HAB_JDE_SHIFT (0U) +#define OCOTP_SCS_HAB_JDE(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SCS_HAB_JDE_SHIFT)) & OCOTP_SCS_HAB_JDE_MASK) +#define OCOTP_SCS_SPARE_MASK (0x7FFFFFFEU) +#define OCOTP_SCS_SPARE_SHIFT (1U) +#define OCOTP_SCS_SPARE(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SCS_SPARE_SHIFT)) & OCOTP_SCS_SPARE_MASK) +#define OCOTP_SCS_LOCK_MASK (0x80000000U) +#define OCOTP_SCS_LOCK_SHIFT (31U) +#define OCOTP_SCS_LOCK(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SCS_LOCK_SHIFT)) & OCOTP_SCS_LOCK_MASK) +/*! @} */ + +/*! @name SCS_SET - Software Controllable Signals Register */ +/*! @{ */ +#define OCOTP_SCS_SET_HAB_JDE_MASK (0x1U) +#define OCOTP_SCS_SET_HAB_JDE_SHIFT (0U) +#define OCOTP_SCS_SET_HAB_JDE(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SCS_SET_HAB_JDE_SHIFT)) & OCOTP_SCS_SET_HAB_JDE_MASK) +#define OCOTP_SCS_SET_SPARE_MASK (0x7FFFFFFEU) +#define OCOTP_SCS_SET_SPARE_SHIFT (1U) +#define OCOTP_SCS_SET_SPARE(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SCS_SET_SPARE_SHIFT)) & OCOTP_SCS_SET_SPARE_MASK) +#define OCOTP_SCS_SET_LOCK_MASK (0x80000000U) +#define OCOTP_SCS_SET_LOCK_SHIFT (31U) +#define OCOTP_SCS_SET_LOCK(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SCS_SET_LOCK_SHIFT)) & OCOTP_SCS_SET_LOCK_MASK) +/*! @} */ + +/*! @name SCS_CLR - Software Controllable Signals Register */ +/*! @{ */ +#define OCOTP_SCS_CLR_HAB_JDE_MASK (0x1U) +#define OCOTP_SCS_CLR_HAB_JDE_SHIFT (0U) +#define OCOTP_SCS_CLR_HAB_JDE(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SCS_CLR_HAB_JDE_SHIFT)) & OCOTP_SCS_CLR_HAB_JDE_MASK) +#define OCOTP_SCS_CLR_SPARE_MASK (0x7FFFFFFEU) +#define OCOTP_SCS_CLR_SPARE_SHIFT (1U) +#define OCOTP_SCS_CLR_SPARE(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SCS_CLR_SPARE_SHIFT)) & OCOTP_SCS_CLR_SPARE_MASK) +#define OCOTP_SCS_CLR_LOCK_MASK (0x80000000U) +#define OCOTP_SCS_CLR_LOCK_SHIFT (31U) +#define OCOTP_SCS_CLR_LOCK(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SCS_CLR_LOCK_SHIFT)) & OCOTP_SCS_CLR_LOCK_MASK) +/*! @} */ + +/*! @name SCS_TOG - Software Controllable Signals Register */ +/*! @{ */ +#define OCOTP_SCS_TOG_HAB_JDE_MASK (0x1U) +#define OCOTP_SCS_TOG_HAB_JDE_SHIFT (0U) +#define OCOTP_SCS_TOG_HAB_JDE(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SCS_TOG_HAB_JDE_SHIFT)) & OCOTP_SCS_TOG_HAB_JDE_MASK) +#define OCOTP_SCS_TOG_SPARE_MASK (0x7FFFFFFEU) +#define OCOTP_SCS_TOG_SPARE_SHIFT (1U) +#define OCOTP_SCS_TOG_SPARE(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SCS_TOG_SPARE_SHIFT)) & OCOTP_SCS_TOG_SPARE_MASK) +#define OCOTP_SCS_TOG_LOCK_MASK (0x80000000U) +#define OCOTP_SCS_TOG_LOCK_SHIFT (31U) +#define OCOTP_SCS_TOG_LOCK(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SCS_TOG_LOCK_SHIFT)) & OCOTP_SCS_TOG_LOCK_MASK) +/*! @} */ + +/*! @name VERSION - OTP Controller Version Register */ +/*! @{ */ +#define OCOTP_VERSION_STEP_MASK (0xFFFFU) +#define OCOTP_VERSION_STEP_SHIFT (0U) +#define OCOTP_VERSION_STEP(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_VERSION_STEP_SHIFT)) & OCOTP_VERSION_STEP_MASK) +#define OCOTP_VERSION_MINOR_MASK (0xFF0000U) +#define OCOTP_VERSION_MINOR_SHIFT (16U) +#define OCOTP_VERSION_MINOR(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_VERSION_MINOR_SHIFT)) & OCOTP_VERSION_MINOR_MASK) +#define OCOTP_VERSION_MAJOR_MASK (0xFF000000U) +#define OCOTP_VERSION_MAJOR_SHIFT (24U) +#define OCOTP_VERSION_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_VERSION_MAJOR_SHIFT)) & OCOTP_VERSION_MAJOR_MASK) +/*! @} */ + +/*! @name TIMING2 - OTP Controller Timing Register 2 */ +/*! @{ */ +#define OCOTP_TIMING2_RELAX_PROG_MASK (0xFFFU) +#define OCOTP_TIMING2_RELAX_PROG_SHIFT (0U) +#define OCOTP_TIMING2_RELAX_PROG(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_TIMING2_RELAX_PROG_SHIFT)) & OCOTP_TIMING2_RELAX_PROG_MASK) +#define OCOTP_TIMING2_RELAX_READ_MASK (0x3F0000U) +#define OCOTP_TIMING2_RELAX_READ_SHIFT (16U) +#define OCOTP_TIMING2_RELAX_READ(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_TIMING2_RELAX_READ_SHIFT)) & OCOTP_TIMING2_RELAX_READ_MASK) +#define OCOTP_TIMING2_RELAX1_MASK (0x1FC00000U) +#define OCOTP_TIMING2_RELAX1_SHIFT (22U) +#define OCOTP_TIMING2_RELAX1(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_TIMING2_RELAX1_SHIFT)) & OCOTP_TIMING2_RELAX1_MASK) +/*! @} */ + +/*! @name LOCK - Value of OTP Bank0 Word0 (Lock controls) */ +/*! @{ */ +#define OCOTP_LOCK_TESTER_MASK (0x3U) +#define OCOTP_LOCK_TESTER_SHIFT (0U) +#define OCOTP_LOCK_TESTER(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_LOCK_TESTER_SHIFT)) & OCOTP_LOCK_TESTER_MASK) +#define OCOTP_LOCK_BOOT_CFG_MASK (0xCU) +#define OCOTP_LOCK_BOOT_CFG_SHIFT (2U) +#define OCOTP_LOCK_BOOT_CFG(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_LOCK_BOOT_CFG_SHIFT)) & OCOTP_LOCK_BOOT_CFG_MASK) +#define OCOTP_LOCK_MEM_TRIM_MASK (0x30U) +#define OCOTP_LOCK_MEM_TRIM_SHIFT (4U) +#define OCOTP_LOCK_MEM_TRIM(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_LOCK_MEM_TRIM_SHIFT)) & OCOTP_LOCK_MEM_TRIM_MASK) +#define OCOTP_LOCK_SJC_RESP_MASK (0x40U) +#define OCOTP_LOCK_SJC_RESP_SHIFT (6U) +#define OCOTP_LOCK_SJC_RESP(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_LOCK_SJC_RESP_SHIFT)) & OCOTP_LOCK_SJC_RESP_MASK) +#define OCOTP_LOCK_MAC_ADDR_MASK (0x300U) +#define OCOTP_LOCK_MAC_ADDR_SHIFT (8U) +#define OCOTP_LOCK_MAC_ADDR(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_LOCK_MAC_ADDR_SHIFT)) & OCOTP_LOCK_MAC_ADDR_MASK) +#define OCOTP_LOCK_GP1_MASK (0xC00U) +#define OCOTP_LOCK_GP1_SHIFT (10U) +#define OCOTP_LOCK_GP1(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_LOCK_GP1_SHIFT)) & OCOTP_LOCK_GP1_MASK) +#define OCOTP_LOCK_GP2_MASK (0x3000U) +#define OCOTP_LOCK_GP2_SHIFT (12U) +#define OCOTP_LOCK_GP2(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_LOCK_GP2_SHIFT)) & OCOTP_LOCK_GP2_MASK) +#define OCOTP_LOCK_OTPMK_MSB_MASK (0x8000U) +#define OCOTP_LOCK_OTPMK_MSB_SHIFT (15U) +#define OCOTP_LOCK_OTPMK_MSB(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_LOCK_OTPMK_MSB_SHIFT)) & OCOTP_LOCK_OTPMK_MSB_MASK) +#define OCOTP_LOCK_SW_GP1_MASK (0x10000U) +#define OCOTP_LOCK_SW_GP1_SHIFT (16U) +#define OCOTP_LOCK_SW_GP1(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_LOCK_SW_GP1_SHIFT)) & OCOTP_LOCK_SW_GP1_MASK) +#define OCOTP_LOCK_OTPMK_LSB_MASK (0x20000U) +#define OCOTP_LOCK_OTPMK_LSB_SHIFT (17U) +#define OCOTP_LOCK_OTPMK_LSB(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_LOCK_OTPMK_LSB_SHIFT)) & OCOTP_LOCK_OTPMK_LSB_MASK) +#define OCOTP_LOCK_ANALOG_MASK (0xC0000U) +#define OCOTP_LOCK_ANALOG_SHIFT (18U) +#define OCOTP_LOCK_ANALOG(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_LOCK_ANALOG_SHIFT)) & OCOTP_LOCK_ANALOG_MASK) +#define OCOTP_LOCK_OTPMK_CRC_MASK (0x100000U) +#define OCOTP_LOCK_OTPMK_CRC_SHIFT (20U) +#define OCOTP_LOCK_OTPMK_CRC(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_LOCK_OTPMK_CRC_SHIFT)) & OCOTP_LOCK_OTPMK_CRC_MASK) +#define OCOTP_LOCK_SW_GP2_LOCK_MASK (0x200000U) +#define OCOTP_LOCK_SW_GP2_LOCK_SHIFT (21U) +#define OCOTP_LOCK_SW_GP2_LOCK(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_LOCK_SW_GP2_LOCK_SHIFT)) & OCOTP_LOCK_SW_GP2_LOCK_MASK) +#define OCOTP_LOCK_MISC_CONF_MASK (0x400000U) +#define OCOTP_LOCK_MISC_CONF_SHIFT (22U) +#define OCOTP_LOCK_MISC_CONF(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_LOCK_MISC_CONF_SHIFT)) & OCOTP_LOCK_MISC_CONF_MASK) +#define OCOTP_LOCK_SW_GP2_RLOCK_MASK (0x800000U) +#define OCOTP_LOCK_SW_GP2_RLOCK_SHIFT (23U) +#define OCOTP_LOCK_SW_GP2_RLOCK(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_LOCK_SW_GP2_RLOCK_SHIFT)) & OCOTP_LOCK_SW_GP2_RLOCK_MASK) +#define OCOTP_LOCK_GP3_MASK (0xC000000U) +#define OCOTP_LOCK_GP3_SHIFT (26U) +#define OCOTP_LOCK_GP3(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_LOCK_GP3_SHIFT)) & OCOTP_LOCK_GP3_MASK) +#define OCOTP_LOCK_FIELD_RETURN_MASK (0xF0000000U) +#define OCOTP_LOCK_FIELD_RETURN_SHIFT (28U) +#define OCOTP_LOCK_FIELD_RETURN(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_LOCK_FIELD_RETURN_SHIFT)) & OCOTP_LOCK_FIELD_RETURN_MASK) +/*! @} */ + +/*! @name CFG0 - Value of OTP Bank0 Word1 (Configuration and Manufacturing Info.) */ +/*! @{ */ +#define OCOTP_CFG0_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_CFG0_BITS_SHIFT (0U) +#define OCOTP_CFG0_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CFG0_BITS_SHIFT)) & OCOTP_CFG0_BITS_MASK) +/*! @} */ + +/*! @name CFG1 - Value of OTP Bank0 Word2 (Configuration and Manufacturing Info.) */ +/*! @{ */ +#define OCOTP_CFG1_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_CFG1_BITS_SHIFT (0U) +#define OCOTP_CFG1_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CFG1_BITS_SHIFT)) & OCOTP_CFG1_BITS_MASK) +/*! @} */ + +/*! @name CFG2 - Value of OTP Bank0 Word3 (Configuration and Manufacturing Info.) */ +/*! @{ */ +#define OCOTP_CFG2_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_CFG2_BITS_SHIFT (0U) +#define OCOTP_CFG2_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CFG2_BITS_SHIFT)) & OCOTP_CFG2_BITS_MASK) +/*! @} */ + +/*! @name CFG3 - Value of OTP Bank0 Word4 (Configuration and Manufacturing Info.) */ +/*! @{ */ +#define OCOTP_CFG3_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_CFG3_BITS_SHIFT (0U) +#define OCOTP_CFG3_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CFG3_BITS_SHIFT)) & OCOTP_CFG3_BITS_MASK) +/*! @} */ + +/*! @name CFG4 - Value of OTP Bank0 Word5 (Configuration and Manufacturing Info.) */ +/*! @{ */ +#define OCOTP_CFG4_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_CFG4_BITS_SHIFT (0U) +#define OCOTP_CFG4_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CFG4_BITS_SHIFT)) & OCOTP_CFG4_BITS_MASK) +/*! @} */ + +/*! @name CFG5 - Value of OTP Bank0 Word6 (Configuration and Manufacturing Info.) */ +/*! @{ */ +#define OCOTP_CFG5_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_CFG5_BITS_SHIFT (0U) +#define OCOTP_CFG5_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CFG5_BITS_SHIFT)) & OCOTP_CFG5_BITS_MASK) +/*! @} */ + +/*! @name CFG6 - Value of OTP Bank0 Word7 (Configuration and Manufacturing Info.) */ +/*! @{ */ +#define OCOTP_CFG6_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_CFG6_BITS_SHIFT (0U) +#define OCOTP_CFG6_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CFG6_BITS_SHIFT)) & OCOTP_CFG6_BITS_MASK) +/*! @} */ + +/*! @name MEM0 - Value of OTP Bank1 Word0 (Memory Related Info.) */ +/*! @{ */ +#define OCOTP_MEM0_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_MEM0_BITS_SHIFT (0U) +#define OCOTP_MEM0_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_MEM0_BITS_SHIFT)) & OCOTP_MEM0_BITS_MASK) +/*! @} */ + +/*! @name MEM1 - Value of OTP Bank1 Word1 (Memory Related Info.) */ +/*! @{ */ +#define OCOTP_MEM1_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_MEM1_BITS_SHIFT (0U) +#define OCOTP_MEM1_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_MEM1_BITS_SHIFT)) & OCOTP_MEM1_BITS_MASK) +/*! @} */ + +/*! @name MEM2 - Value of OTP Bank1 Word2 (Memory Related Info.) */ +/*! @{ */ +#define OCOTP_MEM2_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_MEM2_BITS_SHIFT (0U) +#define OCOTP_MEM2_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_MEM2_BITS_SHIFT)) & OCOTP_MEM2_BITS_MASK) +/*! @} */ + +/*! @name MEM3 - Value of OTP Bank1 Word3 (Memory Related Info.) */ +/*! @{ */ +#define OCOTP_MEM3_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_MEM3_BITS_SHIFT (0U) +#define OCOTP_MEM3_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_MEM3_BITS_SHIFT)) & OCOTP_MEM3_BITS_MASK) +/*! @} */ + +/*! @name MEM4 - Value of OTP Bank1 Word4 (Memory Related Info.) */ +/*! @{ */ +#define OCOTP_MEM4_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_MEM4_BITS_SHIFT (0U) +#define OCOTP_MEM4_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_MEM4_BITS_SHIFT)) & OCOTP_MEM4_BITS_MASK) +/*! @} */ + +/*! @name ANA0 - Value of OTP Bank1 Word5 (Analog Info.) */ +/*! @{ */ +#define OCOTP_ANA0_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_ANA0_BITS_SHIFT (0U) +#define OCOTP_ANA0_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_ANA0_BITS_SHIFT)) & OCOTP_ANA0_BITS_MASK) +/*! @} */ + +/*! @name ANA1 - Value of OTP Bank1 Word6 (Analog Info.) */ +/*! @{ */ +#define OCOTP_ANA1_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_ANA1_BITS_SHIFT (0U) +#define OCOTP_ANA1_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_ANA1_BITS_SHIFT)) & OCOTP_ANA1_BITS_MASK) +/*! @} */ + +/*! @name ANA2 - Value of OTP Bank1 Word7 (Analog Info.) */ +/*! @{ */ +#define OCOTP_ANA2_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_ANA2_BITS_SHIFT (0U) +#define OCOTP_ANA2_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_ANA2_BITS_SHIFT)) & OCOTP_ANA2_BITS_MASK) +/*! @} */ + +/*! @name SRK0 - Shadow Register for OTP Bank3 Word0 (SRK Hash) */ +/*! @{ */ +#define OCOTP_SRK0_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_SRK0_BITS_SHIFT (0U) +#define OCOTP_SRK0_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SRK0_BITS_SHIFT)) & OCOTP_SRK0_BITS_MASK) +/*! @} */ + +/*! @name SRK1 - Shadow Register for OTP Bank3 Word1 (SRK Hash) */ +/*! @{ */ +#define OCOTP_SRK1_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_SRK1_BITS_SHIFT (0U) +#define OCOTP_SRK1_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SRK1_BITS_SHIFT)) & OCOTP_SRK1_BITS_MASK) +/*! @} */ + +/*! @name SRK2 - Shadow Register for OTP Bank3 Word2 (SRK Hash) */ +/*! @{ */ +#define OCOTP_SRK2_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_SRK2_BITS_SHIFT (0U) +#define OCOTP_SRK2_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SRK2_BITS_SHIFT)) & OCOTP_SRK2_BITS_MASK) +/*! @} */ + +/*! @name SRK3 - Shadow Register for OTP Bank3 Word3 (SRK Hash) */ +/*! @{ */ +#define OCOTP_SRK3_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_SRK3_BITS_SHIFT (0U) +#define OCOTP_SRK3_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SRK3_BITS_SHIFT)) & OCOTP_SRK3_BITS_MASK) +/*! @} */ + +/*! @name SRK4 - Shadow Register for OTP Bank3 Word4 (SRK Hash) */ +/*! @{ */ +#define OCOTP_SRK4_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_SRK4_BITS_SHIFT (0U) +#define OCOTP_SRK4_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SRK4_BITS_SHIFT)) & OCOTP_SRK4_BITS_MASK) +/*! @} */ + +/*! @name SRK5 - Shadow Register for OTP Bank3 Word5 (SRK Hash) */ +/*! @{ */ +#define OCOTP_SRK5_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_SRK5_BITS_SHIFT (0U) +#define OCOTP_SRK5_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SRK5_BITS_SHIFT)) & OCOTP_SRK5_BITS_MASK) +/*! @} */ + +/*! @name SRK6 - Shadow Register for OTP Bank3 Word6 (SRK Hash) */ +/*! @{ */ +#define OCOTP_SRK6_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_SRK6_BITS_SHIFT (0U) +#define OCOTP_SRK6_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SRK6_BITS_SHIFT)) & OCOTP_SRK6_BITS_MASK) +/*! @} */ + +/*! @name SRK7 - Shadow Register for OTP Bank3 Word7 (SRK Hash) */ +/*! @{ */ +#define OCOTP_SRK7_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_SRK7_BITS_SHIFT (0U) +#define OCOTP_SRK7_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SRK7_BITS_SHIFT)) & OCOTP_SRK7_BITS_MASK) +/*! @} */ + +/*! @name SJC_RESP0 - Value of OTP Bank4 Word0 (Secure JTAG Response Field) */ +/*! @{ */ +#define OCOTP_SJC_RESP0_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_SJC_RESP0_BITS_SHIFT (0U) +#define OCOTP_SJC_RESP0_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SJC_RESP0_BITS_SHIFT)) & OCOTP_SJC_RESP0_BITS_MASK) +/*! @} */ + +/*! @name SJC_RESP1 - Value of OTP Bank4 Word1 (Secure JTAG Response Field) */ +/*! @{ */ +#define OCOTP_SJC_RESP1_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_SJC_RESP1_BITS_SHIFT (0U) +#define OCOTP_SJC_RESP1_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SJC_RESP1_BITS_SHIFT)) & OCOTP_SJC_RESP1_BITS_MASK) +/*! @} */ + +/*! @name MAC0 - Value of OTP Bank4 Word2 (MAC Address) */ +/*! @{ */ +#define OCOTP_MAC0_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_MAC0_BITS_SHIFT (0U) +#define OCOTP_MAC0_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_MAC0_BITS_SHIFT)) & OCOTP_MAC0_BITS_MASK) +/*! @} */ + +/*! @name MAC1 - Value of OTP Bank4 Word3 (MAC Address) */ +/*! @{ */ +#define OCOTP_MAC1_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_MAC1_BITS_SHIFT (0U) +#define OCOTP_MAC1_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_MAC1_BITS_SHIFT)) & OCOTP_MAC1_BITS_MASK) +/*! @} */ + +/*! @name GP3 - Value of OTP Bank4 Word4 (MAC Address) */ +/*! @{ */ +#define OCOTP_GP3_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_GP3_BITS_SHIFT (0U) +#define OCOTP_GP3_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_GP3_BITS_SHIFT)) & OCOTP_GP3_BITS_MASK) +/*! @} */ + +/*! @name GP1 - Value of OTP Bank4 Word6 (General Purpose Customer Defined Info) */ +/*! @{ */ +#define OCOTP_GP1_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_GP1_BITS_SHIFT (0U) +#define OCOTP_GP1_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_GP1_BITS_SHIFT)) & OCOTP_GP1_BITS_MASK) +/*! @} */ + +/*! @name GP2 - Value of OTP Bank4 Word7 (General Purpose Customer Defined Info) */ +/*! @{ */ +#define OCOTP_GP2_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_GP2_BITS_SHIFT (0U) +#define OCOTP_GP2_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_GP2_BITS_SHIFT)) & OCOTP_GP2_BITS_MASK) +/*! @} */ + +/*! @name SW_GP1 - Value of OTP Bank5 Word0 (SW GP1) */ +/*! @{ */ +#define OCOTP_SW_GP1_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_SW_GP1_BITS_SHIFT (0U) +#define OCOTP_SW_GP1_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SW_GP1_BITS_SHIFT)) & OCOTP_SW_GP1_BITS_MASK) +/*! @} */ + +/*! @name SW_GP20 - Value of OTP Bank5 Word1 (SW GP2) */ +/*! @{ */ +#define OCOTP_SW_GP20_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_SW_GP20_BITS_SHIFT (0U) +#define OCOTP_SW_GP20_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SW_GP20_BITS_SHIFT)) & OCOTP_SW_GP20_BITS_MASK) +/*! @} */ + +/*! @name SW_GP21 - Value of OTP Bank5 Word2 (SW GP2) */ +/*! @{ */ +#define OCOTP_SW_GP21_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_SW_GP21_BITS_SHIFT (0U) +#define OCOTP_SW_GP21_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SW_GP21_BITS_SHIFT)) & OCOTP_SW_GP21_BITS_MASK) +/*! @} */ + +/*! @name SW_GP22 - Value of OTP Bank5 Word3 (SW GP2) */ +/*! @{ */ +#define OCOTP_SW_GP22_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_SW_GP22_BITS_SHIFT (0U) +#define OCOTP_SW_GP22_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SW_GP22_BITS_SHIFT)) & OCOTP_SW_GP22_BITS_MASK) +/*! @} */ + +/*! @name SW_GP23 - Value of OTP Bank5 Word4 (SW GP2) */ +/*! @{ */ +#define OCOTP_SW_GP23_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_SW_GP23_BITS_SHIFT (0U) +#define OCOTP_SW_GP23_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SW_GP23_BITS_SHIFT)) & OCOTP_SW_GP23_BITS_MASK) +/*! @} */ + +/*! @name MISC_CONF0 - Value of OTP Bank5 Word5 (Misc Conf) */ +/*! @{ */ +#define OCOTP_MISC_CONF0_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_MISC_CONF0_BITS_SHIFT (0U) +#define OCOTP_MISC_CONF0_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_MISC_CONF0_BITS_SHIFT)) & OCOTP_MISC_CONF0_BITS_MASK) +/*! @} */ + +/*! @name MISC_CONF1 - Value of OTP Bank5 Word6 (Misc Conf) */ +/*! @{ */ +#define OCOTP_MISC_CONF1_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_MISC_CONF1_BITS_SHIFT (0U) +#define OCOTP_MISC_CONF1_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_MISC_CONF1_BITS_SHIFT)) & OCOTP_MISC_CONF1_BITS_MASK) +/*! @} */ + +/*! @name SRK_REVOKE - Value of OTP Bank5 Word7 (SRK Revoke) */ +/*! @{ */ +#define OCOTP_SRK_REVOKE_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_SRK_REVOKE_BITS_SHIFT (0U) +#define OCOTP_SRK_REVOKE_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SRK_REVOKE_BITS_SHIFT)) & OCOTP_SRK_REVOKE_BITS_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group OCOTP_Register_Masks */ + + +/* OCOTP - Peripheral instance base addresses */ +/** Peripheral OCOTP base address */ +#define OCOTP_BASE (0x401F4000u) +/** Peripheral OCOTP base pointer */ +#define OCOTP ((OCOTP_Type *)OCOTP_BASE) +/** Array initializer of OCOTP peripheral base addresses */ +#define OCOTP_BASE_ADDRS { OCOTP_BASE } +/** Array initializer of OCOTP peripheral base pointers */ +#define OCOTP_BASE_PTRS { OCOTP } + +/*! + * @} + */ /* end of group OCOTP_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- PGC Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup PGC_Peripheral_Access_Layer PGC Peripheral Access Layer + * @{ + */ + +/** PGC - Register Layout Typedef */ +typedef struct { + uint8_t RESERVED_0[544]; + __IO uint32_t MEGA_CTRL; /**< PGC Mega Control Register, offset: 0x220 */ + __IO uint32_t MEGA_PUPSCR; /**< PGC Mega Power Up Sequence Control Register, offset: 0x224 */ + __IO uint32_t MEGA_PDNSCR; /**< PGC Mega Pull Down Sequence Control Register, offset: 0x228 */ + __IO uint32_t MEGA_SR; /**< PGC Mega Power Gating Controller Status Register, offset: 0x22C */ + uint8_t RESERVED_1[112]; + __IO uint32_t CPU_CTRL; /**< PGC CPU Control Register, offset: 0x2A0 */ + __IO uint32_t CPU_PUPSCR; /**< PGC CPU Power Up Sequence Control Register, offset: 0x2A4 */ + __IO uint32_t CPU_PDNSCR; /**< PGC CPU Pull Down Sequence Control Register, offset: 0x2A8 */ + __IO uint32_t CPU_SR; /**< PGC CPU Power Gating Controller Status Register, offset: 0x2AC */ +} PGC_Type; + +/* ---------------------------------------------------------------------------- + -- PGC Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup PGC_Register_Masks PGC Register Masks + * @{ + */ + +/*! @name MEGA_CTRL - PGC Mega Control Register */ +/*! @{ */ +#define PGC_MEGA_CTRL_PCR_MASK (0x1U) +#define PGC_MEGA_CTRL_PCR_SHIFT (0U) +/*! PCR + * 0b0..Do not switch off power even if pdn_req is asserted. + * 0b1..Switch off power when pdn_req is asserted. + */ +#define PGC_MEGA_CTRL_PCR(x) (((uint32_t)(((uint32_t)(x)) << PGC_MEGA_CTRL_PCR_SHIFT)) & PGC_MEGA_CTRL_PCR_MASK) +/*! @} */ + +/*! @name MEGA_PUPSCR - PGC Mega Power Up Sequence Control Register */ +/*! @{ */ +#define PGC_MEGA_PUPSCR_SW_MASK (0x3FU) +#define PGC_MEGA_PUPSCR_SW_SHIFT (0U) +#define PGC_MEGA_PUPSCR_SW(x) (((uint32_t)(((uint32_t)(x)) << PGC_MEGA_PUPSCR_SW_SHIFT)) & PGC_MEGA_PUPSCR_SW_MASK) +#define PGC_MEGA_PUPSCR_SW2ISO_MASK (0x3F00U) +#define PGC_MEGA_PUPSCR_SW2ISO_SHIFT (8U) +#define PGC_MEGA_PUPSCR_SW2ISO(x) (((uint32_t)(((uint32_t)(x)) << PGC_MEGA_PUPSCR_SW2ISO_SHIFT)) & PGC_MEGA_PUPSCR_SW2ISO_MASK) +/*! @} */ + +/*! @name MEGA_PDNSCR - PGC Mega Pull Down Sequence Control Register */ +/*! @{ */ +#define PGC_MEGA_PDNSCR_ISO_MASK (0x3FU) +#define PGC_MEGA_PDNSCR_ISO_SHIFT (0U) +#define PGC_MEGA_PDNSCR_ISO(x) (((uint32_t)(((uint32_t)(x)) << PGC_MEGA_PDNSCR_ISO_SHIFT)) & PGC_MEGA_PDNSCR_ISO_MASK) +#define PGC_MEGA_PDNSCR_ISO2SW_MASK (0x3F00U) +#define PGC_MEGA_PDNSCR_ISO2SW_SHIFT (8U) +#define PGC_MEGA_PDNSCR_ISO2SW(x) (((uint32_t)(((uint32_t)(x)) << PGC_MEGA_PDNSCR_ISO2SW_SHIFT)) & PGC_MEGA_PDNSCR_ISO2SW_MASK) +/*! @} */ + +/*! @name MEGA_SR - PGC Mega Power Gating Controller Status Register */ +/*! @{ */ +#define PGC_MEGA_SR_PSR_MASK (0x1U) +#define PGC_MEGA_SR_PSR_SHIFT (0U) +/*! PSR + * 0b0..The target subsystem was not powered down for the previous power-down request. + * 0b1..The target subsystem was powered down for the previous power-down request. + */ +#define PGC_MEGA_SR_PSR(x) (((uint32_t)(((uint32_t)(x)) << PGC_MEGA_SR_PSR_SHIFT)) & PGC_MEGA_SR_PSR_MASK) +/*! @} */ + +/*! @name CPU_CTRL - PGC CPU Control Register */ +/*! @{ */ +#define PGC_CPU_CTRL_PCR_MASK (0x1U) +#define PGC_CPU_CTRL_PCR_SHIFT (0U) +/*! PCR + * 0b0..Do not switch off power even if pdn_req is asserted. + * 0b1..Switch off power when pdn_req is asserted. + */ +#define PGC_CPU_CTRL_PCR(x) (((uint32_t)(((uint32_t)(x)) << PGC_CPU_CTRL_PCR_SHIFT)) & PGC_CPU_CTRL_PCR_MASK) +/*! @} */ + +/*! @name CPU_PUPSCR - PGC CPU Power Up Sequence Control Register */ +/*! @{ */ +#define PGC_CPU_PUPSCR_SW_MASK (0x3FU) +#define PGC_CPU_PUPSCR_SW_SHIFT (0U) +#define PGC_CPU_PUPSCR_SW(x) (((uint32_t)(((uint32_t)(x)) << PGC_CPU_PUPSCR_SW_SHIFT)) & PGC_CPU_PUPSCR_SW_MASK) +#define PGC_CPU_PUPSCR_SW2ISO_MASK (0x3F00U) +#define PGC_CPU_PUPSCR_SW2ISO_SHIFT (8U) +#define PGC_CPU_PUPSCR_SW2ISO(x) (((uint32_t)(((uint32_t)(x)) << PGC_CPU_PUPSCR_SW2ISO_SHIFT)) & PGC_CPU_PUPSCR_SW2ISO_MASK) +/*! @} */ + +/*! @name CPU_PDNSCR - PGC CPU Pull Down Sequence Control Register */ +/*! @{ */ +#define PGC_CPU_PDNSCR_ISO_MASK (0x3FU) +#define PGC_CPU_PDNSCR_ISO_SHIFT (0U) +#define PGC_CPU_PDNSCR_ISO(x) (((uint32_t)(((uint32_t)(x)) << PGC_CPU_PDNSCR_ISO_SHIFT)) & PGC_CPU_PDNSCR_ISO_MASK) +#define PGC_CPU_PDNSCR_ISO2SW_MASK (0x3F00U) +#define PGC_CPU_PDNSCR_ISO2SW_SHIFT (8U) +#define PGC_CPU_PDNSCR_ISO2SW(x) (((uint32_t)(((uint32_t)(x)) << PGC_CPU_PDNSCR_ISO2SW_SHIFT)) & PGC_CPU_PDNSCR_ISO2SW_MASK) +/*! @} */ + +/*! @name CPU_SR - PGC CPU Power Gating Controller Status Register */ +/*! @{ */ +#define PGC_CPU_SR_PSR_MASK (0x1U) +#define PGC_CPU_SR_PSR_SHIFT (0U) +/*! PSR + * 0b0..The target subsystem was not powered down for the previous power-down request. + * 0b1..The target subsystem was powered down for the previous power-down request. + */ +#define PGC_CPU_SR_PSR(x) (((uint32_t)(((uint32_t)(x)) << PGC_CPU_SR_PSR_SHIFT)) & PGC_CPU_SR_PSR_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group PGC_Register_Masks */ + + +/* PGC - Peripheral instance base addresses */ +/** Peripheral PGC base address */ +#define PGC_BASE (0x400F4000u) +/** Peripheral PGC base pointer */ +#define PGC ((PGC_Type *)PGC_BASE) +/** Array initializer of PGC peripheral base addresses */ +#define PGC_BASE_ADDRS { PGC_BASE } +/** Array initializer of PGC peripheral base pointers */ +#define PGC_BASE_PTRS { PGC } + +/*! + * @} + */ /* end of group PGC_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- PIT Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup PIT_Peripheral_Access_Layer PIT Peripheral Access Layer + * @{ + */ + +/** PIT - Register Layout Typedef */ +typedef struct { + __IO uint32_t MCR; /**< PIT Module Control Register, offset: 0x0 */ + uint8_t RESERVED_0[220]; + __I uint32_t LTMR64H; /**< PIT Upper Lifetime Timer Register, offset: 0xE0 */ + __I uint32_t LTMR64L; /**< PIT Lower Lifetime Timer Register, offset: 0xE4 */ + uint8_t RESERVED_1[24]; + struct { /* offset: 0x100, array step: 0x10 */ + __IO uint32_t LDVAL; /**< Timer Load Value Register, array offset: 0x100, array step: 0x10 */ + __I uint32_t CVAL; /**< Current Timer Value Register, array offset: 0x104, array step: 0x10 */ + __IO uint32_t TCTRL; /**< Timer Control Register, array offset: 0x108, array step: 0x10 */ + __IO uint32_t TFLG; /**< Timer Flag Register, array offset: 0x10C, array step: 0x10 */ + } CHANNEL[4]; +} PIT_Type; + +/* ---------------------------------------------------------------------------- + -- PIT Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup PIT_Register_Masks PIT Register Masks + * @{ + */ + +/*! @name MCR - PIT Module Control Register */ +/*! @{ */ +#define PIT_MCR_FRZ_MASK (0x1U) +#define PIT_MCR_FRZ_SHIFT (0U) +/*! FRZ - Freeze + * 0b0..Timers continue to run in Debug mode. + * 0b1..Timers are stopped in Debug mode. + */ +#define PIT_MCR_FRZ(x) (((uint32_t)(((uint32_t)(x)) << PIT_MCR_FRZ_SHIFT)) & PIT_MCR_FRZ_MASK) +#define PIT_MCR_MDIS_MASK (0x2U) +#define PIT_MCR_MDIS_SHIFT (1U) +/*! MDIS - Module Disable - (PIT section) + * 0b0..Clock for standard PIT timers is enabled. + * 0b1..Clock for standard PIT timers is disabled. + */ +#define PIT_MCR_MDIS(x) (((uint32_t)(((uint32_t)(x)) << PIT_MCR_MDIS_SHIFT)) & PIT_MCR_MDIS_MASK) +/*! @} */ + +/*! @name LTMR64H - PIT Upper Lifetime Timer Register */ +/*! @{ */ +#define PIT_LTMR64H_LTH_MASK (0xFFFFFFFFU) +#define PIT_LTMR64H_LTH_SHIFT (0U) +#define PIT_LTMR64H_LTH(x) (((uint32_t)(((uint32_t)(x)) << PIT_LTMR64H_LTH_SHIFT)) & PIT_LTMR64H_LTH_MASK) +/*! @} */ + +/*! @name LTMR64L - PIT Lower Lifetime Timer Register */ +/*! @{ */ +#define PIT_LTMR64L_LTL_MASK (0xFFFFFFFFU) +#define PIT_LTMR64L_LTL_SHIFT (0U) +#define PIT_LTMR64L_LTL(x) (((uint32_t)(((uint32_t)(x)) << PIT_LTMR64L_LTL_SHIFT)) & PIT_LTMR64L_LTL_MASK) +/*! @} */ + +/*! @name LDVAL - Timer Load Value Register */ +/*! @{ */ +#define PIT_LDVAL_TSV_MASK (0xFFFFFFFFU) +#define PIT_LDVAL_TSV_SHIFT (0U) +#define PIT_LDVAL_TSV(x) (((uint32_t)(((uint32_t)(x)) << PIT_LDVAL_TSV_SHIFT)) & PIT_LDVAL_TSV_MASK) +/*! @} */ + +/* The count of PIT_LDVAL */ +#define PIT_LDVAL_COUNT (4U) + +/*! @name CVAL - Current Timer Value Register */ +/*! @{ */ +#define PIT_CVAL_TVL_MASK (0xFFFFFFFFU) +#define PIT_CVAL_TVL_SHIFT (0U) +#define PIT_CVAL_TVL(x) (((uint32_t)(((uint32_t)(x)) << PIT_CVAL_TVL_SHIFT)) & PIT_CVAL_TVL_MASK) +/*! @} */ + +/* The count of PIT_CVAL */ +#define PIT_CVAL_COUNT (4U) + +/*! @name TCTRL - Timer Control Register */ +/*! @{ */ +#define PIT_TCTRL_TEN_MASK (0x1U) +#define PIT_TCTRL_TEN_SHIFT (0U) +/*! TEN - Timer Enable + * 0b0..Timer n is disabled. + * 0b1..Timer n is enabled. + */ +#define PIT_TCTRL_TEN(x) (((uint32_t)(((uint32_t)(x)) << PIT_TCTRL_TEN_SHIFT)) & PIT_TCTRL_TEN_MASK) +#define PIT_TCTRL_TIE_MASK (0x2U) +#define PIT_TCTRL_TIE_SHIFT (1U) +/*! TIE - Timer Interrupt Enable + * 0b0..Interrupt requests from Timer n are disabled. + * 0b1..Interrupt will be requested whenever TIF is set. + */ +#define PIT_TCTRL_TIE(x) (((uint32_t)(((uint32_t)(x)) << PIT_TCTRL_TIE_SHIFT)) & PIT_TCTRL_TIE_MASK) +#define PIT_TCTRL_CHN_MASK (0x4U) +#define PIT_TCTRL_CHN_SHIFT (2U) +/*! CHN - Chain Mode + * 0b0..Timer is not chained. + * 0b1..Timer is chained to previous timer. For example, for Channel 2, if this field is set, Timer 2 is chained to Timer 1. + */ +#define PIT_TCTRL_CHN(x) (((uint32_t)(((uint32_t)(x)) << PIT_TCTRL_CHN_SHIFT)) & PIT_TCTRL_CHN_MASK) +/*! @} */ + +/* The count of PIT_TCTRL */ +#define PIT_TCTRL_COUNT (4U) + +/*! @name TFLG - Timer Flag Register */ +/*! @{ */ +#define PIT_TFLG_TIF_MASK (0x1U) +#define PIT_TFLG_TIF_SHIFT (0U) +/*! TIF - Timer Interrupt Flag + * 0b0..Timeout has not yet occurred. + * 0b1..Timeout has occurred. + */ +#define PIT_TFLG_TIF(x) (((uint32_t)(((uint32_t)(x)) << PIT_TFLG_TIF_SHIFT)) & PIT_TFLG_TIF_MASK) +/*! @} */ + +/* The count of PIT_TFLG */ +#define PIT_TFLG_COUNT (4U) + + +/*! + * @} + */ /* end of group PIT_Register_Masks */ + + +/* PIT - Peripheral instance base addresses */ +/** Peripheral PIT base address */ +#define PIT_BASE (0x40084000u) +/** Peripheral PIT base pointer */ +#define PIT ((PIT_Type *)PIT_BASE) +/** Array initializer of PIT peripheral base addresses */ +#define PIT_BASE_ADDRS { PIT_BASE } +/** Array initializer of PIT peripheral base pointers */ +#define PIT_BASE_PTRS { PIT } +/** Interrupt vectors for the PIT peripheral type */ +#define PIT_IRQS { { PIT_IRQn, PIT_IRQn, PIT_IRQn, PIT_IRQn } } + +/*! + * @} + */ /* end of group PIT_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- PMU Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup PMU_Peripheral_Access_Layer PMU Peripheral Access Layer + * @{ + */ + +/** PMU - Register Layout Typedef */ +typedef struct { + uint8_t RESERVED_0[272]; + __IO uint32_t REG_1P1; /**< Regulator 1P1 Register, offset: 0x110 */ + __IO uint32_t REG_1P1_SET; /**< Regulator 1P1 Register, offset: 0x114 */ + __IO uint32_t REG_1P1_CLR; /**< Regulator 1P1 Register, offset: 0x118 */ + __IO uint32_t REG_1P1_TOG; /**< Regulator 1P1 Register, offset: 0x11C */ + __IO uint32_t REG_3P0; /**< Regulator 3P0 Register, offset: 0x120 */ + __IO uint32_t REG_3P0_SET; /**< Regulator 3P0 Register, offset: 0x124 */ + __IO uint32_t REG_3P0_CLR; /**< Regulator 3P0 Register, offset: 0x128 */ + __IO uint32_t REG_3P0_TOG; /**< Regulator 3P0 Register, offset: 0x12C */ + __IO uint32_t REG_2P5; /**< Regulator 2P5 Register, offset: 0x130 */ + __IO uint32_t REG_2P5_SET; /**< Regulator 2P5 Register, offset: 0x134 */ + __IO uint32_t REG_2P5_CLR; /**< Regulator 2P5 Register, offset: 0x138 */ + __IO uint32_t REG_2P5_TOG; /**< Regulator 2P5 Register, offset: 0x13C */ + __IO uint32_t REG_CORE; /**< Digital Regulator Core Register, offset: 0x140 */ + __IO uint32_t REG_CORE_SET; /**< Digital Regulator Core Register, offset: 0x144 */ + __IO uint32_t REG_CORE_CLR; /**< Digital Regulator Core Register, offset: 0x148 */ + __IO uint32_t REG_CORE_TOG; /**< Digital Regulator Core Register, offset: 0x14C */ + __IO uint32_t MISC0; /**< Miscellaneous Register 0, offset: 0x150 */ + __IO uint32_t MISC0_SET; /**< Miscellaneous Register 0, offset: 0x154 */ + __IO uint32_t MISC0_CLR; /**< Miscellaneous Register 0, offset: 0x158 */ + __IO uint32_t MISC0_TOG; /**< Miscellaneous Register 0, offset: 0x15C */ + __IO uint32_t MISC1; /**< Miscellaneous Register 1, offset: 0x160 */ + __IO uint32_t MISC1_SET; /**< Miscellaneous Register 1, offset: 0x164 */ + __IO uint32_t MISC1_CLR; /**< Miscellaneous Register 1, offset: 0x168 */ + __IO uint32_t MISC1_TOG; /**< Miscellaneous Register 1, offset: 0x16C */ + __IO uint32_t MISC2; /**< Miscellaneous Control Register, offset: 0x170 */ + __IO uint32_t MISC2_SET; /**< Miscellaneous Control Register, offset: 0x174 */ + __IO uint32_t MISC2_CLR; /**< Miscellaneous Control Register, offset: 0x178 */ + __IO uint32_t MISC2_TOG; /**< Miscellaneous Control Register, offset: 0x17C */ +} PMU_Type; + +/* ---------------------------------------------------------------------------- + -- PMU Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup PMU_Register_Masks PMU Register Masks + * @{ + */ + +/*! @name REG_1P1 - Regulator 1P1 Register */ +/*! @{ */ +#define PMU_REG_1P1_ENABLE_LINREG_MASK (0x1U) +#define PMU_REG_1P1_ENABLE_LINREG_SHIFT (0U) +#define PMU_REG_1P1_ENABLE_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_ENABLE_LINREG_SHIFT)) & PMU_REG_1P1_ENABLE_LINREG_MASK) +#define PMU_REG_1P1_ENABLE_BO_MASK (0x2U) +#define PMU_REG_1P1_ENABLE_BO_SHIFT (1U) +#define PMU_REG_1P1_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_ENABLE_BO_SHIFT)) & PMU_REG_1P1_ENABLE_BO_MASK) +#define PMU_REG_1P1_ENABLE_ILIMIT_MASK (0x4U) +#define PMU_REG_1P1_ENABLE_ILIMIT_SHIFT (2U) +#define PMU_REG_1P1_ENABLE_ILIMIT(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_ENABLE_ILIMIT_SHIFT)) & PMU_REG_1P1_ENABLE_ILIMIT_MASK) +#define PMU_REG_1P1_ENABLE_PULLDOWN_MASK (0x8U) +#define PMU_REG_1P1_ENABLE_PULLDOWN_SHIFT (3U) +#define PMU_REG_1P1_ENABLE_PULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_ENABLE_PULLDOWN_SHIFT)) & PMU_REG_1P1_ENABLE_PULLDOWN_MASK) +#define PMU_REG_1P1_BO_OFFSET_MASK (0x70U) +#define PMU_REG_1P1_BO_OFFSET_SHIFT (4U) +#define PMU_REG_1P1_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_BO_OFFSET_SHIFT)) & PMU_REG_1P1_BO_OFFSET_MASK) +#define PMU_REG_1P1_OUTPUT_TRG_MASK (0x1F00U) +#define PMU_REG_1P1_OUTPUT_TRG_SHIFT (8U) +/*! OUTPUT_TRG + * 0b00100..0.8V + * 0b10000..1.1V + * 0b000x1..1.375V + */ +#define PMU_REG_1P1_OUTPUT_TRG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_OUTPUT_TRG_SHIFT)) & PMU_REG_1P1_OUTPUT_TRG_MASK) +#define PMU_REG_1P1_BO_VDD1P1_MASK (0x10000U) +#define PMU_REG_1P1_BO_VDD1P1_SHIFT (16U) +#define PMU_REG_1P1_BO_VDD1P1(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_BO_VDD1P1_SHIFT)) & PMU_REG_1P1_BO_VDD1P1_MASK) +#define PMU_REG_1P1_OK_VDD1P1_MASK (0x20000U) +#define PMU_REG_1P1_OK_VDD1P1_SHIFT (17U) +#define PMU_REG_1P1_OK_VDD1P1(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_OK_VDD1P1_SHIFT)) & PMU_REG_1P1_OK_VDD1P1_MASK) +#define PMU_REG_1P1_ENABLE_WEAK_LINREG_MASK (0x40000U) +#define PMU_REG_1P1_ENABLE_WEAK_LINREG_SHIFT (18U) +#define PMU_REG_1P1_ENABLE_WEAK_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_ENABLE_WEAK_LINREG_SHIFT)) & PMU_REG_1P1_ENABLE_WEAK_LINREG_MASK) +#define PMU_REG_1P1_SELREF_WEAK_LINREG_MASK (0x80000U) +#define PMU_REG_1P1_SELREF_WEAK_LINREG_SHIFT (19U) +/*! SELREF_WEAK_LINREG + * 0b0..Weak-linreg output tracks low-power-bandgap voltage + * 0b1..Weak-linreg output tracks VDD_SOC_IN voltage + */ +#define PMU_REG_1P1_SELREF_WEAK_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_SELREF_WEAK_LINREG_SHIFT)) & PMU_REG_1P1_SELREF_WEAK_LINREG_MASK) +/*! @} */ + +/*! @name REG_1P1_SET - Regulator 1P1 Register */ +/*! @{ */ +#define PMU_REG_1P1_SET_ENABLE_LINREG_MASK (0x1U) +#define PMU_REG_1P1_SET_ENABLE_LINREG_SHIFT (0U) +#define PMU_REG_1P1_SET_ENABLE_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_SET_ENABLE_LINREG_SHIFT)) & PMU_REG_1P1_SET_ENABLE_LINREG_MASK) +#define PMU_REG_1P1_SET_ENABLE_BO_MASK (0x2U) +#define PMU_REG_1P1_SET_ENABLE_BO_SHIFT (1U) +#define PMU_REG_1P1_SET_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_SET_ENABLE_BO_SHIFT)) & PMU_REG_1P1_SET_ENABLE_BO_MASK) +#define PMU_REG_1P1_SET_ENABLE_ILIMIT_MASK (0x4U) +#define PMU_REG_1P1_SET_ENABLE_ILIMIT_SHIFT (2U) +#define PMU_REG_1P1_SET_ENABLE_ILIMIT(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_SET_ENABLE_ILIMIT_SHIFT)) & PMU_REG_1P1_SET_ENABLE_ILIMIT_MASK) +#define PMU_REG_1P1_SET_ENABLE_PULLDOWN_MASK (0x8U) +#define PMU_REG_1P1_SET_ENABLE_PULLDOWN_SHIFT (3U) +#define PMU_REG_1P1_SET_ENABLE_PULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_SET_ENABLE_PULLDOWN_SHIFT)) & PMU_REG_1P1_SET_ENABLE_PULLDOWN_MASK) +#define PMU_REG_1P1_SET_BO_OFFSET_MASK (0x70U) +#define PMU_REG_1P1_SET_BO_OFFSET_SHIFT (4U) +#define PMU_REG_1P1_SET_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_SET_BO_OFFSET_SHIFT)) & PMU_REG_1P1_SET_BO_OFFSET_MASK) +#define PMU_REG_1P1_SET_OUTPUT_TRG_MASK (0x1F00U) +#define PMU_REG_1P1_SET_OUTPUT_TRG_SHIFT (8U) +/*! OUTPUT_TRG + * 0b00100..0.8V + * 0b10000..1.1V + * 0b000x1..1.375V + */ +#define PMU_REG_1P1_SET_OUTPUT_TRG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_SET_OUTPUT_TRG_SHIFT)) & PMU_REG_1P1_SET_OUTPUT_TRG_MASK) +#define PMU_REG_1P1_SET_BO_VDD1P1_MASK (0x10000U) +#define PMU_REG_1P1_SET_BO_VDD1P1_SHIFT (16U) +#define PMU_REG_1P1_SET_BO_VDD1P1(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_SET_BO_VDD1P1_SHIFT)) & PMU_REG_1P1_SET_BO_VDD1P1_MASK) +#define PMU_REG_1P1_SET_OK_VDD1P1_MASK (0x20000U) +#define PMU_REG_1P1_SET_OK_VDD1P1_SHIFT (17U) +#define PMU_REG_1P1_SET_OK_VDD1P1(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_SET_OK_VDD1P1_SHIFT)) & PMU_REG_1P1_SET_OK_VDD1P1_MASK) +#define PMU_REG_1P1_SET_ENABLE_WEAK_LINREG_MASK (0x40000U) +#define PMU_REG_1P1_SET_ENABLE_WEAK_LINREG_SHIFT (18U) +#define PMU_REG_1P1_SET_ENABLE_WEAK_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_SET_ENABLE_WEAK_LINREG_SHIFT)) & PMU_REG_1P1_SET_ENABLE_WEAK_LINREG_MASK) +#define PMU_REG_1P1_SET_SELREF_WEAK_LINREG_MASK (0x80000U) +#define PMU_REG_1P1_SET_SELREF_WEAK_LINREG_SHIFT (19U) +/*! SELREF_WEAK_LINREG + * 0b0..Weak-linreg output tracks low-power-bandgap voltage + * 0b1..Weak-linreg output tracks VDD_SOC_IN voltage + */ +#define PMU_REG_1P1_SET_SELREF_WEAK_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_SET_SELREF_WEAK_LINREG_SHIFT)) & PMU_REG_1P1_SET_SELREF_WEAK_LINREG_MASK) +/*! @} */ + +/*! @name REG_1P1_CLR - Regulator 1P1 Register */ +/*! @{ */ +#define PMU_REG_1P1_CLR_ENABLE_LINREG_MASK (0x1U) +#define PMU_REG_1P1_CLR_ENABLE_LINREG_SHIFT (0U) +#define PMU_REG_1P1_CLR_ENABLE_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_CLR_ENABLE_LINREG_SHIFT)) & PMU_REG_1P1_CLR_ENABLE_LINREG_MASK) +#define PMU_REG_1P1_CLR_ENABLE_BO_MASK (0x2U) +#define PMU_REG_1P1_CLR_ENABLE_BO_SHIFT (1U) +#define PMU_REG_1P1_CLR_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_CLR_ENABLE_BO_SHIFT)) & PMU_REG_1P1_CLR_ENABLE_BO_MASK) +#define PMU_REG_1P1_CLR_ENABLE_ILIMIT_MASK (0x4U) +#define PMU_REG_1P1_CLR_ENABLE_ILIMIT_SHIFT (2U) +#define PMU_REG_1P1_CLR_ENABLE_ILIMIT(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_CLR_ENABLE_ILIMIT_SHIFT)) & PMU_REG_1P1_CLR_ENABLE_ILIMIT_MASK) +#define PMU_REG_1P1_CLR_ENABLE_PULLDOWN_MASK (0x8U) +#define PMU_REG_1P1_CLR_ENABLE_PULLDOWN_SHIFT (3U) +#define PMU_REG_1P1_CLR_ENABLE_PULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_CLR_ENABLE_PULLDOWN_SHIFT)) & PMU_REG_1P1_CLR_ENABLE_PULLDOWN_MASK) +#define PMU_REG_1P1_CLR_BO_OFFSET_MASK (0x70U) +#define PMU_REG_1P1_CLR_BO_OFFSET_SHIFT (4U) +#define PMU_REG_1P1_CLR_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_CLR_BO_OFFSET_SHIFT)) & PMU_REG_1P1_CLR_BO_OFFSET_MASK) +#define PMU_REG_1P1_CLR_OUTPUT_TRG_MASK (0x1F00U) +#define PMU_REG_1P1_CLR_OUTPUT_TRG_SHIFT (8U) +/*! OUTPUT_TRG + * 0b00100..0.8V + * 0b10000..1.1V + * 0b000x1..1.375V + */ +#define PMU_REG_1P1_CLR_OUTPUT_TRG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_CLR_OUTPUT_TRG_SHIFT)) & PMU_REG_1P1_CLR_OUTPUT_TRG_MASK) +#define PMU_REG_1P1_CLR_BO_VDD1P1_MASK (0x10000U) +#define PMU_REG_1P1_CLR_BO_VDD1P1_SHIFT (16U) +#define PMU_REG_1P1_CLR_BO_VDD1P1(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_CLR_BO_VDD1P1_SHIFT)) & PMU_REG_1P1_CLR_BO_VDD1P1_MASK) +#define PMU_REG_1P1_CLR_OK_VDD1P1_MASK (0x20000U) +#define PMU_REG_1P1_CLR_OK_VDD1P1_SHIFT (17U) +#define PMU_REG_1P1_CLR_OK_VDD1P1(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_CLR_OK_VDD1P1_SHIFT)) & PMU_REG_1P1_CLR_OK_VDD1P1_MASK) +#define PMU_REG_1P1_CLR_ENABLE_WEAK_LINREG_MASK (0x40000U) +#define PMU_REG_1P1_CLR_ENABLE_WEAK_LINREG_SHIFT (18U) +#define PMU_REG_1P1_CLR_ENABLE_WEAK_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_CLR_ENABLE_WEAK_LINREG_SHIFT)) & PMU_REG_1P1_CLR_ENABLE_WEAK_LINREG_MASK) +#define PMU_REG_1P1_CLR_SELREF_WEAK_LINREG_MASK (0x80000U) +#define PMU_REG_1P1_CLR_SELREF_WEAK_LINREG_SHIFT (19U) +/*! SELREF_WEAK_LINREG + * 0b0..Weak-linreg output tracks low-power-bandgap voltage + * 0b1..Weak-linreg output tracks VDD_SOC_IN voltage + */ +#define PMU_REG_1P1_CLR_SELREF_WEAK_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_CLR_SELREF_WEAK_LINREG_SHIFT)) & PMU_REG_1P1_CLR_SELREF_WEAK_LINREG_MASK) +/*! @} */ + +/*! @name REG_1P1_TOG - Regulator 1P1 Register */ +/*! @{ */ +#define PMU_REG_1P1_TOG_ENABLE_LINREG_MASK (0x1U) +#define PMU_REG_1P1_TOG_ENABLE_LINREG_SHIFT (0U) +#define PMU_REG_1P1_TOG_ENABLE_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_TOG_ENABLE_LINREG_SHIFT)) & PMU_REG_1P1_TOG_ENABLE_LINREG_MASK) +#define PMU_REG_1P1_TOG_ENABLE_BO_MASK (0x2U) +#define PMU_REG_1P1_TOG_ENABLE_BO_SHIFT (1U) +#define PMU_REG_1P1_TOG_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_TOG_ENABLE_BO_SHIFT)) & PMU_REG_1P1_TOG_ENABLE_BO_MASK) +#define PMU_REG_1P1_TOG_ENABLE_ILIMIT_MASK (0x4U) +#define PMU_REG_1P1_TOG_ENABLE_ILIMIT_SHIFT (2U) +#define PMU_REG_1P1_TOG_ENABLE_ILIMIT(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_TOG_ENABLE_ILIMIT_SHIFT)) & PMU_REG_1P1_TOG_ENABLE_ILIMIT_MASK) +#define PMU_REG_1P1_TOG_ENABLE_PULLDOWN_MASK (0x8U) +#define PMU_REG_1P1_TOG_ENABLE_PULLDOWN_SHIFT (3U) +#define PMU_REG_1P1_TOG_ENABLE_PULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_TOG_ENABLE_PULLDOWN_SHIFT)) & PMU_REG_1P1_TOG_ENABLE_PULLDOWN_MASK) +#define PMU_REG_1P1_TOG_BO_OFFSET_MASK (0x70U) +#define PMU_REG_1P1_TOG_BO_OFFSET_SHIFT (4U) +#define PMU_REG_1P1_TOG_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_TOG_BO_OFFSET_SHIFT)) & PMU_REG_1P1_TOG_BO_OFFSET_MASK) +#define PMU_REG_1P1_TOG_OUTPUT_TRG_MASK (0x1F00U) +#define PMU_REG_1P1_TOG_OUTPUT_TRG_SHIFT (8U) +/*! OUTPUT_TRG + * 0b00100..0.8V + * 0b10000..1.1V + * 0b000x1..1.375V + */ +#define PMU_REG_1P1_TOG_OUTPUT_TRG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_TOG_OUTPUT_TRG_SHIFT)) & PMU_REG_1P1_TOG_OUTPUT_TRG_MASK) +#define PMU_REG_1P1_TOG_BO_VDD1P1_MASK (0x10000U) +#define PMU_REG_1P1_TOG_BO_VDD1P1_SHIFT (16U) +#define PMU_REG_1P1_TOG_BO_VDD1P1(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_TOG_BO_VDD1P1_SHIFT)) & PMU_REG_1P1_TOG_BO_VDD1P1_MASK) +#define PMU_REG_1P1_TOG_OK_VDD1P1_MASK (0x20000U) +#define PMU_REG_1P1_TOG_OK_VDD1P1_SHIFT (17U) +#define PMU_REG_1P1_TOG_OK_VDD1P1(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_TOG_OK_VDD1P1_SHIFT)) & PMU_REG_1P1_TOG_OK_VDD1P1_MASK) +#define PMU_REG_1P1_TOG_ENABLE_WEAK_LINREG_MASK (0x40000U) +#define PMU_REG_1P1_TOG_ENABLE_WEAK_LINREG_SHIFT (18U) +#define PMU_REG_1P1_TOG_ENABLE_WEAK_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_TOG_ENABLE_WEAK_LINREG_SHIFT)) & PMU_REG_1P1_TOG_ENABLE_WEAK_LINREG_MASK) +#define PMU_REG_1P1_TOG_SELREF_WEAK_LINREG_MASK (0x80000U) +#define PMU_REG_1P1_TOG_SELREF_WEAK_LINREG_SHIFT (19U) +/*! SELREF_WEAK_LINREG + * 0b0..Weak-linreg output tracks low-power-bandgap voltage + * 0b1..Weak-linreg output tracks VDD_SOC_IN voltage + */ +#define PMU_REG_1P1_TOG_SELREF_WEAK_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_TOG_SELREF_WEAK_LINREG_SHIFT)) & PMU_REG_1P1_TOG_SELREF_WEAK_LINREG_MASK) +/*! @} */ + +/*! @name REG_3P0 - Regulator 3P0 Register */ +/*! @{ */ +#define PMU_REG_3P0_ENABLE_LINREG_MASK (0x1U) +#define PMU_REG_3P0_ENABLE_LINREG_SHIFT (0U) +#define PMU_REG_3P0_ENABLE_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_ENABLE_LINREG_SHIFT)) & PMU_REG_3P0_ENABLE_LINREG_MASK) +#define PMU_REG_3P0_ENABLE_BO_MASK (0x2U) +#define PMU_REG_3P0_ENABLE_BO_SHIFT (1U) +#define PMU_REG_3P0_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_ENABLE_BO_SHIFT)) & PMU_REG_3P0_ENABLE_BO_MASK) +#define PMU_REG_3P0_ENABLE_ILIMIT_MASK (0x4U) +#define PMU_REG_3P0_ENABLE_ILIMIT_SHIFT (2U) +#define PMU_REG_3P0_ENABLE_ILIMIT(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_ENABLE_ILIMIT_SHIFT)) & PMU_REG_3P0_ENABLE_ILIMIT_MASK) +#define PMU_REG_3P0_BO_OFFSET_MASK (0x70U) +#define PMU_REG_3P0_BO_OFFSET_SHIFT (4U) +#define PMU_REG_3P0_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_BO_OFFSET_SHIFT)) & PMU_REG_3P0_BO_OFFSET_MASK) +#define PMU_REG_3P0_VBUS_SEL_MASK (0x80U) +#define PMU_REG_3P0_VBUS_SEL_SHIFT (7U) +/*! VBUS_SEL + * 0b1..Utilize VBUS OTG1 power + * 0b0..Utilize VBUS OTG2 power + */ +#define PMU_REG_3P0_VBUS_SEL(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_VBUS_SEL_SHIFT)) & PMU_REG_3P0_VBUS_SEL_MASK) +#define PMU_REG_3P0_OUTPUT_TRG_MASK (0x1F00U) +#define PMU_REG_3P0_OUTPUT_TRG_SHIFT (8U) +/*! OUTPUT_TRG + * 0b00000..2.625V + * 0b01111..3.000V + * 0b11111..3.400V + */ +#define PMU_REG_3P0_OUTPUT_TRG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_OUTPUT_TRG_SHIFT)) & PMU_REG_3P0_OUTPUT_TRG_MASK) +#define PMU_REG_3P0_BO_VDD3P0_MASK (0x10000U) +#define PMU_REG_3P0_BO_VDD3P0_SHIFT (16U) +#define PMU_REG_3P0_BO_VDD3P0(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_BO_VDD3P0_SHIFT)) & PMU_REG_3P0_BO_VDD3P0_MASK) +#define PMU_REG_3P0_OK_VDD3P0_MASK (0x20000U) +#define PMU_REG_3P0_OK_VDD3P0_SHIFT (17U) +#define PMU_REG_3P0_OK_VDD3P0(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_OK_VDD3P0_SHIFT)) & PMU_REG_3P0_OK_VDD3P0_MASK) +/*! @} */ + +/*! @name REG_3P0_SET - Regulator 3P0 Register */ +/*! @{ */ +#define PMU_REG_3P0_SET_ENABLE_LINREG_MASK (0x1U) +#define PMU_REG_3P0_SET_ENABLE_LINREG_SHIFT (0U) +#define PMU_REG_3P0_SET_ENABLE_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_SET_ENABLE_LINREG_SHIFT)) & PMU_REG_3P0_SET_ENABLE_LINREG_MASK) +#define PMU_REG_3P0_SET_ENABLE_BO_MASK (0x2U) +#define PMU_REG_3P0_SET_ENABLE_BO_SHIFT (1U) +#define PMU_REG_3P0_SET_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_SET_ENABLE_BO_SHIFT)) & PMU_REG_3P0_SET_ENABLE_BO_MASK) +#define PMU_REG_3P0_SET_ENABLE_ILIMIT_MASK (0x4U) +#define PMU_REG_3P0_SET_ENABLE_ILIMIT_SHIFT (2U) +#define PMU_REG_3P0_SET_ENABLE_ILIMIT(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_SET_ENABLE_ILIMIT_SHIFT)) & PMU_REG_3P0_SET_ENABLE_ILIMIT_MASK) +#define PMU_REG_3P0_SET_BO_OFFSET_MASK (0x70U) +#define PMU_REG_3P0_SET_BO_OFFSET_SHIFT (4U) +#define PMU_REG_3P0_SET_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_SET_BO_OFFSET_SHIFT)) & PMU_REG_3P0_SET_BO_OFFSET_MASK) +#define PMU_REG_3P0_SET_VBUS_SEL_MASK (0x80U) +#define PMU_REG_3P0_SET_VBUS_SEL_SHIFT (7U) +/*! VBUS_SEL + * 0b1..Utilize VBUS OTG1 power + * 0b0..Utilize VBUS OTG2 power + */ +#define PMU_REG_3P0_SET_VBUS_SEL(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_SET_VBUS_SEL_SHIFT)) & PMU_REG_3P0_SET_VBUS_SEL_MASK) +#define PMU_REG_3P0_SET_OUTPUT_TRG_MASK (0x1F00U) +#define PMU_REG_3P0_SET_OUTPUT_TRG_SHIFT (8U) +/*! OUTPUT_TRG + * 0b00000..2.625V + * 0b01111..3.000V + * 0b11111..3.400V + */ +#define PMU_REG_3P0_SET_OUTPUT_TRG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_SET_OUTPUT_TRG_SHIFT)) & PMU_REG_3P0_SET_OUTPUT_TRG_MASK) +#define PMU_REG_3P0_SET_BO_VDD3P0_MASK (0x10000U) +#define PMU_REG_3P0_SET_BO_VDD3P0_SHIFT (16U) +#define PMU_REG_3P0_SET_BO_VDD3P0(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_SET_BO_VDD3P0_SHIFT)) & PMU_REG_3P0_SET_BO_VDD3P0_MASK) +#define PMU_REG_3P0_SET_OK_VDD3P0_MASK (0x20000U) +#define PMU_REG_3P0_SET_OK_VDD3P0_SHIFT (17U) +#define PMU_REG_3P0_SET_OK_VDD3P0(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_SET_OK_VDD3P0_SHIFT)) & PMU_REG_3P0_SET_OK_VDD3P0_MASK) +/*! @} */ + +/*! @name REG_3P0_CLR - Regulator 3P0 Register */ +/*! @{ */ +#define PMU_REG_3P0_CLR_ENABLE_LINREG_MASK (0x1U) +#define PMU_REG_3P0_CLR_ENABLE_LINREG_SHIFT (0U) +#define PMU_REG_3P0_CLR_ENABLE_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_CLR_ENABLE_LINREG_SHIFT)) & PMU_REG_3P0_CLR_ENABLE_LINREG_MASK) +#define PMU_REG_3P0_CLR_ENABLE_BO_MASK (0x2U) +#define PMU_REG_3P0_CLR_ENABLE_BO_SHIFT (1U) +#define PMU_REG_3P0_CLR_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_CLR_ENABLE_BO_SHIFT)) & PMU_REG_3P0_CLR_ENABLE_BO_MASK) +#define PMU_REG_3P0_CLR_ENABLE_ILIMIT_MASK (0x4U) +#define PMU_REG_3P0_CLR_ENABLE_ILIMIT_SHIFT (2U) +#define PMU_REG_3P0_CLR_ENABLE_ILIMIT(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_CLR_ENABLE_ILIMIT_SHIFT)) & PMU_REG_3P0_CLR_ENABLE_ILIMIT_MASK) +#define PMU_REG_3P0_CLR_BO_OFFSET_MASK (0x70U) +#define PMU_REG_3P0_CLR_BO_OFFSET_SHIFT (4U) +#define PMU_REG_3P0_CLR_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_CLR_BO_OFFSET_SHIFT)) & PMU_REG_3P0_CLR_BO_OFFSET_MASK) +#define PMU_REG_3P0_CLR_VBUS_SEL_MASK (0x80U) +#define PMU_REG_3P0_CLR_VBUS_SEL_SHIFT (7U) +/*! VBUS_SEL + * 0b1..Utilize VBUS OTG1 power + * 0b0..Utilize VBUS OTG2 power + */ +#define PMU_REG_3P0_CLR_VBUS_SEL(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_CLR_VBUS_SEL_SHIFT)) & PMU_REG_3P0_CLR_VBUS_SEL_MASK) +#define PMU_REG_3P0_CLR_OUTPUT_TRG_MASK (0x1F00U) +#define PMU_REG_3P0_CLR_OUTPUT_TRG_SHIFT (8U) +/*! OUTPUT_TRG + * 0b00000..2.625V + * 0b01111..3.000V + * 0b11111..3.400V + */ +#define PMU_REG_3P0_CLR_OUTPUT_TRG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_CLR_OUTPUT_TRG_SHIFT)) & PMU_REG_3P0_CLR_OUTPUT_TRG_MASK) +#define PMU_REG_3P0_CLR_BO_VDD3P0_MASK (0x10000U) +#define PMU_REG_3P0_CLR_BO_VDD3P0_SHIFT (16U) +#define PMU_REG_3P0_CLR_BO_VDD3P0(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_CLR_BO_VDD3P0_SHIFT)) & PMU_REG_3P0_CLR_BO_VDD3P0_MASK) +#define PMU_REG_3P0_CLR_OK_VDD3P0_MASK (0x20000U) +#define PMU_REG_3P0_CLR_OK_VDD3P0_SHIFT (17U) +#define PMU_REG_3P0_CLR_OK_VDD3P0(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_CLR_OK_VDD3P0_SHIFT)) & PMU_REG_3P0_CLR_OK_VDD3P0_MASK) +/*! @} */ + +/*! @name REG_3P0_TOG - Regulator 3P0 Register */ +/*! @{ */ +#define PMU_REG_3P0_TOG_ENABLE_LINREG_MASK (0x1U) +#define PMU_REG_3P0_TOG_ENABLE_LINREG_SHIFT (0U) +#define PMU_REG_3P0_TOG_ENABLE_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_TOG_ENABLE_LINREG_SHIFT)) & PMU_REG_3P0_TOG_ENABLE_LINREG_MASK) +#define PMU_REG_3P0_TOG_ENABLE_BO_MASK (0x2U) +#define PMU_REG_3P0_TOG_ENABLE_BO_SHIFT (1U) +#define PMU_REG_3P0_TOG_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_TOG_ENABLE_BO_SHIFT)) & PMU_REG_3P0_TOG_ENABLE_BO_MASK) +#define PMU_REG_3P0_TOG_ENABLE_ILIMIT_MASK (0x4U) +#define PMU_REG_3P0_TOG_ENABLE_ILIMIT_SHIFT (2U) +#define PMU_REG_3P0_TOG_ENABLE_ILIMIT(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_TOG_ENABLE_ILIMIT_SHIFT)) & PMU_REG_3P0_TOG_ENABLE_ILIMIT_MASK) +#define PMU_REG_3P0_TOG_BO_OFFSET_MASK (0x70U) +#define PMU_REG_3P0_TOG_BO_OFFSET_SHIFT (4U) +#define PMU_REG_3P0_TOG_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_TOG_BO_OFFSET_SHIFT)) & PMU_REG_3P0_TOG_BO_OFFSET_MASK) +#define PMU_REG_3P0_TOG_VBUS_SEL_MASK (0x80U) +#define PMU_REG_3P0_TOG_VBUS_SEL_SHIFT (7U) +/*! VBUS_SEL + * 0b1..Utilize VBUS OTG1 power + * 0b0..Utilize VBUS OTG2 power + */ +#define PMU_REG_3P0_TOG_VBUS_SEL(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_TOG_VBUS_SEL_SHIFT)) & PMU_REG_3P0_TOG_VBUS_SEL_MASK) +#define PMU_REG_3P0_TOG_OUTPUT_TRG_MASK (0x1F00U) +#define PMU_REG_3P0_TOG_OUTPUT_TRG_SHIFT (8U) +/*! OUTPUT_TRG + * 0b00000..2.625V + * 0b01111..3.000V + * 0b11111..3.400V + */ +#define PMU_REG_3P0_TOG_OUTPUT_TRG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_TOG_OUTPUT_TRG_SHIFT)) & PMU_REG_3P0_TOG_OUTPUT_TRG_MASK) +#define PMU_REG_3P0_TOG_BO_VDD3P0_MASK (0x10000U) +#define PMU_REG_3P0_TOG_BO_VDD3P0_SHIFT (16U) +#define PMU_REG_3P0_TOG_BO_VDD3P0(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_TOG_BO_VDD3P0_SHIFT)) & PMU_REG_3P0_TOG_BO_VDD3P0_MASK) +#define PMU_REG_3P0_TOG_OK_VDD3P0_MASK (0x20000U) +#define PMU_REG_3P0_TOG_OK_VDD3P0_SHIFT (17U) +#define PMU_REG_3P0_TOG_OK_VDD3P0(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_TOG_OK_VDD3P0_SHIFT)) & PMU_REG_3P0_TOG_OK_VDD3P0_MASK) +/*! @} */ + +/*! @name REG_2P5 - Regulator 2P5 Register */ +/*! @{ */ +#define PMU_REG_2P5_ENABLE_LINREG_MASK (0x1U) +#define PMU_REG_2P5_ENABLE_LINREG_SHIFT (0U) +#define PMU_REG_2P5_ENABLE_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_ENABLE_LINREG_SHIFT)) & PMU_REG_2P5_ENABLE_LINREG_MASK) +#define PMU_REG_2P5_ENABLE_BO_MASK (0x2U) +#define PMU_REG_2P5_ENABLE_BO_SHIFT (1U) +#define PMU_REG_2P5_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_ENABLE_BO_SHIFT)) & PMU_REG_2P5_ENABLE_BO_MASK) +#define PMU_REG_2P5_ENABLE_ILIMIT_MASK (0x4U) +#define PMU_REG_2P5_ENABLE_ILIMIT_SHIFT (2U) +#define PMU_REG_2P5_ENABLE_ILIMIT(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_ENABLE_ILIMIT_SHIFT)) & PMU_REG_2P5_ENABLE_ILIMIT_MASK) +#define PMU_REG_2P5_ENABLE_PULLDOWN_MASK (0x8U) +#define PMU_REG_2P5_ENABLE_PULLDOWN_SHIFT (3U) +#define PMU_REG_2P5_ENABLE_PULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_ENABLE_PULLDOWN_SHIFT)) & PMU_REG_2P5_ENABLE_PULLDOWN_MASK) +#define PMU_REG_2P5_BO_OFFSET_MASK (0x70U) +#define PMU_REG_2P5_BO_OFFSET_SHIFT (4U) +#define PMU_REG_2P5_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_BO_OFFSET_SHIFT)) & PMU_REG_2P5_BO_OFFSET_MASK) +#define PMU_REG_2P5_OUTPUT_TRG_MASK (0x1F00U) +#define PMU_REG_2P5_OUTPUT_TRG_SHIFT (8U) +/*! OUTPUT_TRG + * 0b00000..2.10V + * 0b10000..2.50V + * 0b11111..2.875V + */ +#define PMU_REG_2P5_OUTPUT_TRG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_OUTPUT_TRG_SHIFT)) & PMU_REG_2P5_OUTPUT_TRG_MASK) +#define PMU_REG_2P5_BO_VDD2P5_MASK (0x10000U) +#define PMU_REG_2P5_BO_VDD2P5_SHIFT (16U) +#define PMU_REG_2P5_BO_VDD2P5(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_BO_VDD2P5_SHIFT)) & PMU_REG_2P5_BO_VDD2P5_MASK) +#define PMU_REG_2P5_OK_VDD2P5_MASK (0x20000U) +#define PMU_REG_2P5_OK_VDD2P5_SHIFT (17U) +#define PMU_REG_2P5_OK_VDD2P5(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_OK_VDD2P5_SHIFT)) & PMU_REG_2P5_OK_VDD2P5_MASK) +#define PMU_REG_2P5_ENABLE_WEAK_LINREG_MASK (0x40000U) +#define PMU_REG_2P5_ENABLE_WEAK_LINREG_SHIFT (18U) +#define PMU_REG_2P5_ENABLE_WEAK_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_ENABLE_WEAK_LINREG_SHIFT)) & PMU_REG_2P5_ENABLE_WEAK_LINREG_MASK) +/*! @} */ + +/*! @name REG_2P5_SET - Regulator 2P5 Register */ +/*! @{ */ +#define PMU_REG_2P5_SET_ENABLE_LINREG_MASK (0x1U) +#define PMU_REG_2P5_SET_ENABLE_LINREG_SHIFT (0U) +#define PMU_REG_2P5_SET_ENABLE_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_SET_ENABLE_LINREG_SHIFT)) & PMU_REG_2P5_SET_ENABLE_LINREG_MASK) +#define PMU_REG_2P5_SET_ENABLE_BO_MASK (0x2U) +#define PMU_REG_2P5_SET_ENABLE_BO_SHIFT (1U) +#define PMU_REG_2P5_SET_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_SET_ENABLE_BO_SHIFT)) & PMU_REG_2P5_SET_ENABLE_BO_MASK) +#define PMU_REG_2P5_SET_ENABLE_ILIMIT_MASK (0x4U) +#define PMU_REG_2P5_SET_ENABLE_ILIMIT_SHIFT (2U) +#define PMU_REG_2P5_SET_ENABLE_ILIMIT(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_SET_ENABLE_ILIMIT_SHIFT)) & PMU_REG_2P5_SET_ENABLE_ILIMIT_MASK) +#define PMU_REG_2P5_SET_ENABLE_PULLDOWN_MASK (0x8U) +#define PMU_REG_2P5_SET_ENABLE_PULLDOWN_SHIFT (3U) +#define PMU_REG_2P5_SET_ENABLE_PULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_SET_ENABLE_PULLDOWN_SHIFT)) & PMU_REG_2P5_SET_ENABLE_PULLDOWN_MASK) +#define PMU_REG_2P5_SET_BO_OFFSET_MASK (0x70U) +#define PMU_REG_2P5_SET_BO_OFFSET_SHIFT (4U) +#define PMU_REG_2P5_SET_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_SET_BO_OFFSET_SHIFT)) & PMU_REG_2P5_SET_BO_OFFSET_MASK) +#define PMU_REG_2P5_SET_OUTPUT_TRG_MASK (0x1F00U) +#define PMU_REG_2P5_SET_OUTPUT_TRG_SHIFT (8U) +/*! OUTPUT_TRG + * 0b00000..2.10V + * 0b10000..2.50V + * 0b11111..2.875V + */ +#define PMU_REG_2P5_SET_OUTPUT_TRG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_SET_OUTPUT_TRG_SHIFT)) & PMU_REG_2P5_SET_OUTPUT_TRG_MASK) +#define PMU_REG_2P5_SET_BO_VDD2P5_MASK (0x10000U) +#define PMU_REG_2P5_SET_BO_VDD2P5_SHIFT (16U) +#define PMU_REG_2P5_SET_BO_VDD2P5(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_SET_BO_VDD2P5_SHIFT)) & PMU_REG_2P5_SET_BO_VDD2P5_MASK) +#define PMU_REG_2P5_SET_OK_VDD2P5_MASK (0x20000U) +#define PMU_REG_2P5_SET_OK_VDD2P5_SHIFT (17U) +#define PMU_REG_2P5_SET_OK_VDD2P5(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_SET_OK_VDD2P5_SHIFT)) & PMU_REG_2P5_SET_OK_VDD2P5_MASK) +#define PMU_REG_2P5_SET_ENABLE_WEAK_LINREG_MASK (0x40000U) +#define PMU_REG_2P5_SET_ENABLE_WEAK_LINREG_SHIFT (18U) +#define PMU_REG_2P5_SET_ENABLE_WEAK_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_SET_ENABLE_WEAK_LINREG_SHIFT)) & PMU_REG_2P5_SET_ENABLE_WEAK_LINREG_MASK) +/*! @} */ + +/*! @name REG_2P5_CLR - Regulator 2P5 Register */ +/*! @{ */ +#define PMU_REG_2P5_CLR_ENABLE_LINREG_MASK (0x1U) +#define PMU_REG_2P5_CLR_ENABLE_LINREG_SHIFT (0U) +#define PMU_REG_2P5_CLR_ENABLE_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_CLR_ENABLE_LINREG_SHIFT)) & PMU_REG_2P5_CLR_ENABLE_LINREG_MASK) +#define PMU_REG_2P5_CLR_ENABLE_BO_MASK (0x2U) +#define PMU_REG_2P5_CLR_ENABLE_BO_SHIFT (1U) +#define PMU_REG_2P5_CLR_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_CLR_ENABLE_BO_SHIFT)) & PMU_REG_2P5_CLR_ENABLE_BO_MASK) +#define PMU_REG_2P5_CLR_ENABLE_ILIMIT_MASK (0x4U) +#define PMU_REG_2P5_CLR_ENABLE_ILIMIT_SHIFT (2U) +#define PMU_REG_2P5_CLR_ENABLE_ILIMIT(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_CLR_ENABLE_ILIMIT_SHIFT)) & PMU_REG_2P5_CLR_ENABLE_ILIMIT_MASK) +#define PMU_REG_2P5_CLR_ENABLE_PULLDOWN_MASK (0x8U) +#define PMU_REG_2P5_CLR_ENABLE_PULLDOWN_SHIFT (3U) +#define PMU_REG_2P5_CLR_ENABLE_PULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_CLR_ENABLE_PULLDOWN_SHIFT)) & PMU_REG_2P5_CLR_ENABLE_PULLDOWN_MASK) +#define PMU_REG_2P5_CLR_BO_OFFSET_MASK (0x70U) +#define PMU_REG_2P5_CLR_BO_OFFSET_SHIFT (4U) +#define PMU_REG_2P5_CLR_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_CLR_BO_OFFSET_SHIFT)) & PMU_REG_2P5_CLR_BO_OFFSET_MASK) +#define PMU_REG_2P5_CLR_OUTPUT_TRG_MASK (0x1F00U) +#define PMU_REG_2P5_CLR_OUTPUT_TRG_SHIFT (8U) +/*! OUTPUT_TRG + * 0b00000..2.10V + * 0b10000..2.50V + * 0b11111..2.875V + */ +#define PMU_REG_2P5_CLR_OUTPUT_TRG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_CLR_OUTPUT_TRG_SHIFT)) & PMU_REG_2P5_CLR_OUTPUT_TRG_MASK) +#define PMU_REG_2P5_CLR_BO_VDD2P5_MASK (0x10000U) +#define PMU_REG_2P5_CLR_BO_VDD2P5_SHIFT (16U) +#define PMU_REG_2P5_CLR_BO_VDD2P5(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_CLR_BO_VDD2P5_SHIFT)) & PMU_REG_2P5_CLR_BO_VDD2P5_MASK) +#define PMU_REG_2P5_CLR_OK_VDD2P5_MASK (0x20000U) +#define PMU_REG_2P5_CLR_OK_VDD2P5_SHIFT (17U) +#define PMU_REG_2P5_CLR_OK_VDD2P5(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_CLR_OK_VDD2P5_SHIFT)) & PMU_REG_2P5_CLR_OK_VDD2P5_MASK) +#define PMU_REG_2P5_CLR_ENABLE_WEAK_LINREG_MASK (0x40000U) +#define PMU_REG_2P5_CLR_ENABLE_WEAK_LINREG_SHIFT (18U) +#define PMU_REG_2P5_CLR_ENABLE_WEAK_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_CLR_ENABLE_WEAK_LINREG_SHIFT)) & PMU_REG_2P5_CLR_ENABLE_WEAK_LINREG_MASK) +/*! @} */ + +/*! @name REG_2P5_TOG - Regulator 2P5 Register */ +/*! @{ */ +#define PMU_REG_2P5_TOG_ENABLE_LINREG_MASK (0x1U) +#define PMU_REG_2P5_TOG_ENABLE_LINREG_SHIFT (0U) +#define PMU_REG_2P5_TOG_ENABLE_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_TOG_ENABLE_LINREG_SHIFT)) & PMU_REG_2P5_TOG_ENABLE_LINREG_MASK) +#define PMU_REG_2P5_TOG_ENABLE_BO_MASK (0x2U) +#define PMU_REG_2P5_TOG_ENABLE_BO_SHIFT (1U) +#define PMU_REG_2P5_TOG_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_TOG_ENABLE_BO_SHIFT)) & PMU_REG_2P5_TOG_ENABLE_BO_MASK) +#define PMU_REG_2P5_TOG_ENABLE_ILIMIT_MASK (0x4U) +#define PMU_REG_2P5_TOG_ENABLE_ILIMIT_SHIFT (2U) +#define PMU_REG_2P5_TOG_ENABLE_ILIMIT(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_TOG_ENABLE_ILIMIT_SHIFT)) & PMU_REG_2P5_TOG_ENABLE_ILIMIT_MASK) +#define PMU_REG_2P5_TOG_ENABLE_PULLDOWN_MASK (0x8U) +#define PMU_REG_2P5_TOG_ENABLE_PULLDOWN_SHIFT (3U) +#define PMU_REG_2P5_TOG_ENABLE_PULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_TOG_ENABLE_PULLDOWN_SHIFT)) & PMU_REG_2P5_TOG_ENABLE_PULLDOWN_MASK) +#define PMU_REG_2P5_TOG_BO_OFFSET_MASK (0x70U) +#define PMU_REG_2P5_TOG_BO_OFFSET_SHIFT (4U) +#define PMU_REG_2P5_TOG_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_TOG_BO_OFFSET_SHIFT)) & PMU_REG_2P5_TOG_BO_OFFSET_MASK) +#define PMU_REG_2P5_TOG_OUTPUT_TRG_MASK (0x1F00U) +#define PMU_REG_2P5_TOG_OUTPUT_TRG_SHIFT (8U) +/*! OUTPUT_TRG + * 0b00000..2.10V + * 0b10000..2.50V + * 0b11111..2.875V + */ +#define PMU_REG_2P5_TOG_OUTPUT_TRG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_TOG_OUTPUT_TRG_SHIFT)) & PMU_REG_2P5_TOG_OUTPUT_TRG_MASK) +#define PMU_REG_2P5_TOG_BO_VDD2P5_MASK (0x10000U) +#define PMU_REG_2P5_TOG_BO_VDD2P5_SHIFT (16U) +#define PMU_REG_2P5_TOG_BO_VDD2P5(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_TOG_BO_VDD2P5_SHIFT)) & PMU_REG_2P5_TOG_BO_VDD2P5_MASK) +#define PMU_REG_2P5_TOG_OK_VDD2P5_MASK (0x20000U) +#define PMU_REG_2P5_TOG_OK_VDD2P5_SHIFT (17U) +#define PMU_REG_2P5_TOG_OK_VDD2P5(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_TOG_OK_VDD2P5_SHIFT)) & PMU_REG_2P5_TOG_OK_VDD2P5_MASK) +#define PMU_REG_2P5_TOG_ENABLE_WEAK_LINREG_MASK (0x40000U) +#define PMU_REG_2P5_TOG_ENABLE_WEAK_LINREG_SHIFT (18U) +#define PMU_REG_2P5_TOG_ENABLE_WEAK_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_TOG_ENABLE_WEAK_LINREG_SHIFT)) & PMU_REG_2P5_TOG_ENABLE_WEAK_LINREG_MASK) +/*! @} */ + +/*! @name REG_CORE - Digital Regulator Core Register */ +/*! @{ */ +#define PMU_REG_CORE_REG0_TARG_MASK (0x1FU) +#define PMU_REG_CORE_REG0_TARG_SHIFT (0U) +/*! REG0_TARG + * 0b00000..Power gated off + * 0b00001..Target core voltage = 0.725V + * 0b00010..Target core voltage = 0.750V + * 0b00011..Target core voltage = 0.775V + * 0b10000..Target core voltage = 1.100V + * 0b11110..Target core voltage = 1.450V + * 0b11111..Power FET switched full on. No regulation. + */ +#define PMU_REG_CORE_REG0_TARG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_REG0_TARG_SHIFT)) & PMU_REG_CORE_REG0_TARG_MASK) +#define PMU_REG_CORE_REG0_ADJ_MASK (0x1E0U) +#define PMU_REG_CORE_REG0_ADJ_SHIFT (5U) +/*! REG0_ADJ - This bit field defines the adjustment bits to calibrate the target value of Reg0. The adjustment is applied on top on any adjustment applied to the global reference in the misc0 register. + * 0b0000..No adjustment + * 0b0001..+ 0.25% + * 0b0010..+ 0.50% + * 0b0011..+ 0.75% + * 0b0100..+ 1.00% + * 0b0101..+ 1.25% + * 0b0110..+ 1.50% + * 0b0111..+ 1.75% + * 0b1000..- 0.25% + * 0b1001..- 0.50% + * 0b1010..- 0.75% + * 0b1011..- 1.00% + * 0b1100..- 1.25% + * 0b1101..- 1.50% + * 0b1110..- 1.75% + * 0b1111..- 2.00% + */ +#define PMU_REG_CORE_REG0_ADJ(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_REG0_ADJ_SHIFT)) & PMU_REG_CORE_REG0_ADJ_MASK) +#define PMU_REG_CORE_REG1_TARG_MASK (0x3E00U) +#define PMU_REG_CORE_REG1_TARG_SHIFT (9U) +/*! REG1_TARG - This bit field defines the target voltage for the vpu/gpu power domain. Single bit increments reflect 25mV core voltage steps. Not all steps will make sense to use either because of input supply limitations or load operation. + * 0b00000..Power gated off + * 0b00001..Target core voltage = 0.725V + * 0b00010..Target core voltage = 0.750V + * 0b00011..Target core voltage = 0.775V + * 0b10000..Target core voltage = 1.100V + * 0b11110..Target core voltage = 1.450V + * 0b11111..Power FET switched full on. No regulation. + */ +#define PMU_REG_CORE_REG1_TARG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_REG1_TARG_SHIFT)) & PMU_REG_CORE_REG1_TARG_MASK) +#define PMU_REG_CORE_REG1_ADJ_MASK (0x3C000U) +#define PMU_REG_CORE_REG1_ADJ_SHIFT (14U) +/*! REG1_ADJ - This bit field defines the adjustment bits to calibrate the target value of Reg1. The adjustment is applied on top on any adjustment applied to the global reference in the misc0 register. + * 0b0000..No adjustment + * 0b0001..+ 0.25% + * 0b0010..+ 0.50% + * 0b0011..+ 0.75% + * 0b0100..+ 1.00% + * 0b0101..+ 1.25% + * 0b0110..+ 1.50% + * 0b0111..+ 1.75% + * 0b1000..- 0.25% + * 0b1001..- 0.50% + * 0b1010..- 0.75% + * 0b1011..- 1.00% + * 0b1100..- 1.25% + * 0b1101..- 1.50% + * 0b1110..- 1.75% + * 0b1111..- 2.00% + */ +#define PMU_REG_CORE_REG1_ADJ(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_REG1_ADJ_SHIFT)) & PMU_REG_CORE_REG1_ADJ_MASK) +#define PMU_REG_CORE_REG2_TARG_MASK (0x7C0000U) +#define PMU_REG_CORE_REG2_TARG_SHIFT (18U) +/*! REG2_TARG + * 0b00000..Power gated off + * 0b00001..Target core voltage = 0.725V + * 0b00010..Target core voltage = 0.750V + * 0b00011..Target core voltage = 0.775V + * 0b10000..Target core voltage = 1.100V + * 0b11110..Target core voltage = 1.450V + * 0b11111..Power FET switched full on. No regulation. + */ +#define PMU_REG_CORE_REG2_TARG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_REG2_TARG_SHIFT)) & PMU_REG_CORE_REG2_TARG_MASK) +#define PMU_REG_CORE_REG2_ADJ_MASK (0x7800000U) +#define PMU_REG_CORE_REG2_ADJ_SHIFT (23U) +/*! REG2_ADJ - This bit field defines the adjustment bits to calibrate the target value of Reg2. The adjustment is applied on top on any adjustment applied to the global reference in the misc0 register. + * 0b0000..No adjustment + * 0b0001..+ 0.25% + * 0b0010..+ 0.50% + * 0b0011..+ 0.75% + * 0b0100..+ 1.00% + * 0b0101..+ 1.25% + * 0b0110..+ 1.50% + * 0b0111..+ 1.75% + * 0b1000..- 0.25% + * 0b1001..- 0.50% + * 0b1010..- 0.75% + * 0b1011..- 1.00% + * 0b1100..- 1.25% + * 0b1101..- 1.50% + * 0b1110..- 1.75% + * 0b1111..- 2.00% + */ +#define PMU_REG_CORE_REG2_ADJ(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_REG2_ADJ_SHIFT)) & PMU_REG_CORE_REG2_ADJ_MASK) +#define PMU_REG_CORE_RAMP_RATE_MASK (0x18000000U) +#define PMU_REG_CORE_RAMP_RATE_SHIFT (27U) +/*! RAMP_RATE + * 0b00..Fast + * 0b01..Medium Fast + * 0b10..Medium Slow + * 0b11..Slow + */ +#define PMU_REG_CORE_RAMP_RATE(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_RAMP_RATE_SHIFT)) & PMU_REG_CORE_RAMP_RATE_MASK) +#define PMU_REG_CORE_FET_ODRIVE_MASK (0x20000000U) +#define PMU_REG_CORE_FET_ODRIVE_SHIFT (29U) +#define PMU_REG_CORE_FET_ODRIVE(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_FET_ODRIVE_SHIFT)) & PMU_REG_CORE_FET_ODRIVE_MASK) +/*! @} */ + +/*! @name REG_CORE_SET - Digital Regulator Core Register */ +/*! @{ */ +#define PMU_REG_CORE_SET_REG0_TARG_MASK (0x1FU) +#define PMU_REG_CORE_SET_REG0_TARG_SHIFT (0U) +/*! REG0_TARG + * 0b00000..Power gated off + * 0b00001..Target core voltage = 0.725V + * 0b00010..Target core voltage = 0.750V + * 0b00011..Target core voltage = 0.775V + * 0b10000..Target core voltage = 1.100V + * 0b11110..Target core voltage = 1.450V + * 0b11111..Power FET switched full on. No regulation. + */ +#define PMU_REG_CORE_SET_REG0_TARG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_SET_REG0_TARG_SHIFT)) & PMU_REG_CORE_SET_REG0_TARG_MASK) +#define PMU_REG_CORE_SET_REG0_ADJ_MASK (0x1E0U) +#define PMU_REG_CORE_SET_REG0_ADJ_SHIFT (5U) +/*! REG0_ADJ - This bit field defines the adjustment bits to calibrate the target value of Reg0. The adjustment is applied on top on any adjustment applied to the global reference in the misc0 register. + * 0b0000..No adjustment + * 0b0001..+ 0.25% + * 0b0010..+ 0.50% + * 0b0011..+ 0.75% + * 0b0100..+ 1.00% + * 0b0101..+ 1.25% + * 0b0110..+ 1.50% + * 0b0111..+ 1.75% + * 0b1000..- 0.25% + * 0b1001..- 0.50% + * 0b1010..- 0.75% + * 0b1011..- 1.00% + * 0b1100..- 1.25% + * 0b1101..- 1.50% + * 0b1110..- 1.75% + * 0b1111..- 2.00% + */ +#define PMU_REG_CORE_SET_REG0_ADJ(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_SET_REG0_ADJ_SHIFT)) & PMU_REG_CORE_SET_REG0_ADJ_MASK) +#define PMU_REG_CORE_SET_REG1_TARG_MASK (0x3E00U) +#define PMU_REG_CORE_SET_REG1_TARG_SHIFT (9U) +/*! REG1_TARG - This bit field defines the target voltage for the vpu/gpu power domain. Single bit increments reflect 25mV core voltage steps. Not all steps will make sense to use either because of input supply limitations or load operation. + * 0b00000..Power gated off + * 0b00001..Target core voltage = 0.725V + * 0b00010..Target core voltage = 0.750V + * 0b00011..Target core voltage = 0.775V + * 0b10000..Target core voltage = 1.100V + * 0b11110..Target core voltage = 1.450V + * 0b11111..Power FET switched full on. No regulation. + */ +#define PMU_REG_CORE_SET_REG1_TARG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_SET_REG1_TARG_SHIFT)) & PMU_REG_CORE_SET_REG1_TARG_MASK) +#define PMU_REG_CORE_SET_REG1_ADJ_MASK (0x3C000U) +#define PMU_REG_CORE_SET_REG1_ADJ_SHIFT (14U) +/*! REG1_ADJ - This bit field defines the adjustment bits to calibrate the target value of Reg1. The adjustment is applied on top on any adjustment applied to the global reference in the misc0 register. + * 0b0000..No adjustment + * 0b0001..+ 0.25% + * 0b0010..+ 0.50% + * 0b0011..+ 0.75% + * 0b0100..+ 1.00% + * 0b0101..+ 1.25% + * 0b0110..+ 1.50% + * 0b0111..+ 1.75% + * 0b1000..- 0.25% + * 0b1001..- 0.50% + * 0b1010..- 0.75% + * 0b1011..- 1.00% + * 0b1100..- 1.25% + * 0b1101..- 1.50% + * 0b1110..- 1.75% + * 0b1111..- 2.00% + */ +#define PMU_REG_CORE_SET_REG1_ADJ(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_SET_REG1_ADJ_SHIFT)) & PMU_REG_CORE_SET_REG1_ADJ_MASK) +#define PMU_REG_CORE_SET_REG2_TARG_MASK (0x7C0000U) +#define PMU_REG_CORE_SET_REG2_TARG_SHIFT (18U) +/*! REG2_TARG + * 0b00000..Power gated off + * 0b00001..Target core voltage = 0.725V + * 0b00010..Target core voltage = 0.750V + * 0b00011..Target core voltage = 0.775V + * 0b10000..Target core voltage = 1.100V + * 0b11110..Target core voltage = 1.450V + * 0b11111..Power FET switched full on. No regulation. + */ +#define PMU_REG_CORE_SET_REG2_TARG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_SET_REG2_TARG_SHIFT)) & PMU_REG_CORE_SET_REG2_TARG_MASK) +#define PMU_REG_CORE_SET_REG2_ADJ_MASK (0x7800000U) +#define PMU_REG_CORE_SET_REG2_ADJ_SHIFT (23U) +/*! REG2_ADJ - This bit field defines the adjustment bits to calibrate the target value of Reg2. The adjustment is applied on top on any adjustment applied to the global reference in the misc0 register. + * 0b0000..No adjustment + * 0b0001..+ 0.25% + * 0b0010..+ 0.50% + * 0b0011..+ 0.75% + * 0b0100..+ 1.00% + * 0b0101..+ 1.25% + * 0b0110..+ 1.50% + * 0b0111..+ 1.75% + * 0b1000..- 0.25% + * 0b1001..- 0.50% + * 0b1010..- 0.75% + * 0b1011..- 1.00% + * 0b1100..- 1.25% + * 0b1101..- 1.50% + * 0b1110..- 1.75% + * 0b1111..- 2.00% + */ +#define PMU_REG_CORE_SET_REG2_ADJ(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_SET_REG2_ADJ_SHIFT)) & PMU_REG_CORE_SET_REG2_ADJ_MASK) +#define PMU_REG_CORE_SET_RAMP_RATE_MASK (0x18000000U) +#define PMU_REG_CORE_SET_RAMP_RATE_SHIFT (27U) +/*! RAMP_RATE + * 0b00..Fast + * 0b01..Medium Fast + * 0b10..Medium Slow + * 0b11..Slow + */ +#define PMU_REG_CORE_SET_RAMP_RATE(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_SET_RAMP_RATE_SHIFT)) & PMU_REG_CORE_SET_RAMP_RATE_MASK) +#define PMU_REG_CORE_SET_FET_ODRIVE_MASK (0x20000000U) +#define PMU_REG_CORE_SET_FET_ODRIVE_SHIFT (29U) +#define PMU_REG_CORE_SET_FET_ODRIVE(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_SET_FET_ODRIVE_SHIFT)) & PMU_REG_CORE_SET_FET_ODRIVE_MASK) +/*! @} */ + +/*! @name REG_CORE_CLR - Digital Regulator Core Register */ +/*! @{ */ +#define PMU_REG_CORE_CLR_REG0_TARG_MASK (0x1FU) +#define PMU_REG_CORE_CLR_REG0_TARG_SHIFT (0U) +/*! REG0_TARG + * 0b00000..Power gated off + * 0b00001..Target core voltage = 0.725V + * 0b00010..Target core voltage = 0.750V + * 0b00011..Target core voltage = 0.775V + * 0b10000..Target core voltage = 1.100V + * 0b11110..Target core voltage = 1.450V + * 0b11111..Power FET switched full on. No regulation. + */ +#define PMU_REG_CORE_CLR_REG0_TARG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_CLR_REG0_TARG_SHIFT)) & PMU_REG_CORE_CLR_REG0_TARG_MASK) +#define PMU_REG_CORE_CLR_REG0_ADJ_MASK (0x1E0U) +#define PMU_REG_CORE_CLR_REG0_ADJ_SHIFT (5U) +/*! REG0_ADJ - This bit field defines the adjustment bits to calibrate the target value of Reg0. The adjustment is applied on top on any adjustment applied to the global reference in the misc0 register. + * 0b0000..No adjustment + * 0b0001..+ 0.25% + * 0b0010..+ 0.50% + * 0b0011..+ 0.75% + * 0b0100..+ 1.00% + * 0b0101..+ 1.25% + * 0b0110..+ 1.50% + * 0b0111..+ 1.75% + * 0b1000..- 0.25% + * 0b1001..- 0.50% + * 0b1010..- 0.75% + * 0b1011..- 1.00% + * 0b1100..- 1.25% + * 0b1101..- 1.50% + * 0b1110..- 1.75% + * 0b1111..- 2.00% + */ +#define PMU_REG_CORE_CLR_REG0_ADJ(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_CLR_REG0_ADJ_SHIFT)) & PMU_REG_CORE_CLR_REG0_ADJ_MASK) +#define PMU_REG_CORE_CLR_REG1_TARG_MASK (0x3E00U) +#define PMU_REG_CORE_CLR_REG1_TARG_SHIFT (9U) +/*! REG1_TARG - This bit field defines the target voltage for the vpu/gpu power domain. Single bit increments reflect 25mV core voltage steps. Not all steps will make sense to use either because of input supply limitations or load operation. + * 0b00000..Power gated off + * 0b00001..Target core voltage = 0.725V + * 0b00010..Target core voltage = 0.750V + * 0b00011..Target core voltage = 0.775V + * 0b10000..Target core voltage = 1.100V + * 0b11110..Target core voltage = 1.450V + * 0b11111..Power FET switched full on. No regulation. + */ +#define PMU_REG_CORE_CLR_REG1_TARG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_CLR_REG1_TARG_SHIFT)) & PMU_REG_CORE_CLR_REG1_TARG_MASK) +#define PMU_REG_CORE_CLR_REG1_ADJ_MASK (0x3C000U) +#define PMU_REG_CORE_CLR_REG1_ADJ_SHIFT (14U) +/*! REG1_ADJ - This bit field defines the adjustment bits to calibrate the target value of Reg1. The adjustment is applied on top on any adjustment applied to the global reference in the misc0 register. + * 0b0000..No adjustment + * 0b0001..+ 0.25% + * 0b0010..+ 0.50% + * 0b0011..+ 0.75% + * 0b0100..+ 1.00% + * 0b0101..+ 1.25% + * 0b0110..+ 1.50% + * 0b0111..+ 1.75% + * 0b1000..- 0.25% + * 0b1001..- 0.50% + * 0b1010..- 0.75% + * 0b1011..- 1.00% + * 0b1100..- 1.25% + * 0b1101..- 1.50% + * 0b1110..- 1.75% + * 0b1111..- 2.00% + */ +#define PMU_REG_CORE_CLR_REG1_ADJ(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_CLR_REG1_ADJ_SHIFT)) & PMU_REG_CORE_CLR_REG1_ADJ_MASK) +#define PMU_REG_CORE_CLR_REG2_TARG_MASK (0x7C0000U) +#define PMU_REG_CORE_CLR_REG2_TARG_SHIFT (18U) +/*! REG2_TARG + * 0b00000..Power gated off + * 0b00001..Target core voltage = 0.725V + * 0b00010..Target core voltage = 0.750V + * 0b00011..Target core voltage = 0.775V + * 0b10000..Target core voltage = 1.100V + * 0b11110..Target core voltage = 1.450V + * 0b11111..Power FET switched full on. No regulation. + */ +#define PMU_REG_CORE_CLR_REG2_TARG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_CLR_REG2_TARG_SHIFT)) & PMU_REG_CORE_CLR_REG2_TARG_MASK) +#define PMU_REG_CORE_CLR_REG2_ADJ_MASK (0x7800000U) +#define PMU_REG_CORE_CLR_REG2_ADJ_SHIFT (23U) +/*! REG2_ADJ - This bit field defines the adjustment bits to calibrate the target value of Reg2. The adjustment is applied on top on any adjustment applied to the global reference in the misc0 register. + * 0b0000..No adjustment + * 0b0001..+ 0.25% + * 0b0010..+ 0.50% + * 0b0011..+ 0.75% + * 0b0100..+ 1.00% + * 0b0101..+ 1.25% + * 0b0110..+ 1.50% + * 0b0111..+ 1.75% + * 0b1000..- 0.25% + * 0b1001..- 0.50% + * 0b1010..- 0.75% + * 0b1011..- 1.00% + * 0b1100..- 1.25% + * 0b1101..- 1.50% + * 0b1110..- 1.75% + * 0b1111..- 2.00% + */ +#define PMU_REG_CORE_CLR_REG2_ADJ(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_CLR_REG2_ADJ_SHIFT)) & PMU_REG_CORE_CLR_REG2_ADJ_MASK) +#define PMU_REG_CORE_CLR_RAMP_RATE_MASK (0x18000000U) +#define PMU_REG_CORE_CLR_RAMP_RATE_SHIFT (27U) +/*! RAMP_RATE + * 0b00..Fast + * 0b01..Medium Fast + * 0b10..Medium Slow + * 0b11..Slow + */ +#define PMU_REG_CORE_CLR_RAMP_RATE(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_CLR_RAMP_RATE_SHIFT)) & PMU_REG_CORE_CLR_RAMP_RATE_MASK) +#define PMU_REG_CORE_CLR_FET_ODRIVE_MASK (0x20000000U) +#define PMU_REG_CORE_CLR_FET_ODRIVE_SHIFT (29U) +#define PMU_REG_CORE_CLR_FET_ODRIVE(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_CLR_FET_ODRIVE_SHIFT)) & PMU_REG_CORE_CLR_FET_ODRIVE_MASK) +/*! @} */ + +/*! @name REG_CORE_TOG - Digital Regulator Core Register */ +/*! @{ */ +#define PMU_REG_CORE_TOG_REG0_TARG_MASK (0x1FU) +#define PMU_REG_CORE_TOG_REG0_TARG_SHIFT (0U) +/*! REG0_TARG + * 0b00000..Power gated off + * 0b00001..Target core voltage = 0.725V + * 0b00010..Target core voltage = 0.750V + * 0b00011..Target core voltage = 0.775V + * 0b10000..Target core voltage = 1.100V + * 0b11110..Target core voltage = 1.450V + * 0b11111..Power FET switched full on. No regulation. + */ +#define PMU_REG_CORE_TOG_REG0_TARG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_TOG_REG0_TARG_SHIFT)) & PMU_REG_CORE_TOG_REG0_TARG_MASK) +#define PMU_REG_CORE_TOG_REG0_ADJ_MASK (0x1E0U) +#define PMU_REG_CORE_TOG_REG0_ADJ_SHIFT (5U) +/*! REG0_ADJ - This bit field defines the adjustment bits to calibrate the target value of Reg0. The adjustment is applied on top on any adjustment applied to the global reference in the misc0 register. + * 0b0000..No adjustment + * 0b0001..+ 0.25% + * 0b0010..+ 0.50% + * 0b0011..+ 0.75% + * 0b0100..+ 1.00% + * 0b0101..+ 1.25% + * 0b0110..+ 1.50% + * 0b0111..+ 1.75% + * 0b1000..- 0.25% + * 0b1001..- 0.50% + * 0b1010..- 0.75% + * 0b1011..- 1.00% + * 0b1100..- 1.25% + * 0b1101..- 1.50% + * 0b1110..- 1.75% + * 0b1111..- 2.00% + */ +#define PMU_REG_CORE_TOG_REG0_ADJ(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_TOG_REG0_ADJ_SHIFT)) & PMU_REG_CORE_TOG_REG0_ADJ_MASK) +#define PMU_REG_CORE_TOG_REG1_TARG_MASK (0x3E00U) +#define PMU_REG_CORE_TOG_REG1_TARG_SHIFT (9U) +/*! REG1_TARG - This bit field defines the target voltage for the vpu/gpu power domain. Single bit increments reflect 25mV core voltage steps. Not all steps will make sense to use either because of input supply limitations or load operation. + * 0b00000..Power gated off + * 0b00001..Target core voltage = 0.725V + * 0b00010..Target core voltage = 0.750V + * 0b00011..Target core voltage = 0.775V + * 0b10000..Target core voltage = 1.100V + * 0b11110..Target core voltage = 1.450V + * 0b11111..Power FET switched full on. No regulation. + */ +#define PMU_REG_CORE_TOG_REG1_TARG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_TOG_REG1_TARG_SHIFT)) & PMU_REG_CORE_TOG_REG1_TARG_MASK) +#define PMU_REG_CORE_TOG_REG1_ADJ_MASK (0x3C000U) +#define PMU_REG_CORE_TOG_REG1_ADJ_SHIFT (14U) +/*! REG1_ADJ - This bit field defines the adjustment bits to calibrate the target value of Reg1. The adjustment is applied on top on any adjustment applied to the global reference in the misc0 register. + * 0b0000..No adjustment + * 0b0001..+ 0.25% + * 0b0010..+ 0.50% + * 0b0011..+ 0.75% + * 0b0100..+ 1.00% + * 0b0101..+ 1.25% + * 0b0110..+ 1.50% + * 0b0111..+ 1.75% + * 0b1000..- 0.25% + * 0b1001..- 0.50% + * 0b1010..- 0.75% + * 0b1011..- 1.00% + * 0b1100..- 1.25% + * 0b1101..- 1.50% + * 0b1110..- 1.75% + * 0b1111..- 2.00% + */ +#define PMU_REG_CORE_TOG_REG1_ADJ(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_TOG_REG1_ADJ_SHIFT)) & PMU_REG_CORE_TOG_REG1_ADJ_MASK) +#define PMU_REG_CORE_TOG_REG2_TARG_MASK (0x7C0000U) +#define PMU_REG_CORE_TOG_REG2_TARG_SHIFT (18U) +/*! REG2_TARG + * 0b00000..Power gated off + * 0b00001..Target core voltage = 0.725V + * 0b00010..Target core voltage = 0.750V + * 0b00011..Target core voltage = 0.775V + * 0b10000..Target core voltage = 1.100V + * 0b11110..Target core voltage = 1.450V + * 0b11111..Power FET switched full on. No regulation. + */ +#define PMU_REG_CORE_TOG_REG2_TARG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_TOG_REG2_TARG_SHIFT)) & PMU_REG_CORE_TOG_REG2_TARG_MASK) +#define PMU_REG_CORE_TOG_REG2_ADJ_MASK (0x7800000U) +#define PMU_REG_CORE_TOG_REG2_ADJ_SHIFT (23U) +/*! REG2_ADJ - This bit field defines the adjustment bits to calibrate the target value of Reg2. The adjustment is applied on top on any adjustment applied to the global reference in the misc0 register. + * 0b0000..No adjustment + * 0b0001..+ 0.25% + * 0b0010..+ 0.50% + * 0b0011..+ 0.75% + * 0b0100..+ 1.00% + * 0b0101..+ 1.25% + * 0b0110..+ 1.50% + * 0b0111..+ 1.75% + * 0b1000..- 0.25% + * 0b1001..- 0.50% + * 0b1010..- 0.75% + * 0b1011..- 1.00% + * 0b1100..- 1.25% + * 0b1101..- 1.50% + * 0b1110..- 1.75% + * 0b1111..- 2.00% + */ +#define PMU_REG_CORE_TOG_REG2_ADJ(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_TOG_REG2_ADJ_SHIFT)) & PMU_REG_CORE_TOG_REG2_ADJ_MASK) +#define PMU_REG_CORE_TOG_RAMP_RATE_MASK (0x18000000U) +#define PMU_REG_CORE_TOG_RAMP_RATE_SHIFT (27U) +/*! RAMP_RATE + * 0b00..Fast + * 0b01..Medium Fast + * 0b10..Medium Slow + * 0b11..Slow + */ +#define PMU_REG_CORE_TOG_RAMP_RATE(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_TOG_RAMP_RATE_SHIFT)) & PMU_REG_CORE_TOG_RAMP_RATE_MASK) +#define PMU_REG_CORE_TOG_FET_ODRIVE_MASK (0x20000000U) +#define PMU_REG_CORE_TOG_FET_ODRIVE_SHIFT (29U) +#define PMU_REG_CORE_TOG_FET_ODRIVE(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_TOG_FET_ODRIVE_SHIFT)) & PMU_REG_CORE_TOG_FET_ODRIVE_MASK) +/*! @} */ + +/*! @name MISC0 - Miscellaneous Register 0 */ +/*! @{ */ +#define PMU_MISC0_REFTOP_PWD_MASK (0x1U) +#define PMU_MISC0_REFTOP_PWD_SHIFT (0U) +#define PMU_MISC0_REFTOP_PWD(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_REFTOP_PWD_SHIFT)) & PMU_MISC0_REFTOP_PWD_MASK) +#define PMU_MISC0_REFTOP_SELFBIASOFF_MASK (0x8U) +#define PMU_MISC0_REFTOP_SELFBIASOFF_SHIFT (3U) +/*! REFTOP_SELFBIASOFF + * 0b0..Uses coarse bias currents for startup + * 0b1..Uses bandgap-based bias currents for best performance. + */ +#define PMU_MISC0_REFTOP_SELFBIASOFF(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_REFTOP_SELFBIASOFF_SHIFT)) & PMU_MISC0_REFTOP_SELFBIASOFF_MASK) +#define PMU_MISC0_REFTOP_VBGADJ_MASK (0x70U) +#define PMU_MISC0_REFTOP_VBGADJ_SHIFT (4U) +/*! REFTOP_VBGADJ + * 0b000..Nominal VBG + * 0b001..VBG+0.78% + * 0b010..VBG+1.56% + * 0b011..VBG+2.34% + * 0b100..VBG-0.78% + * 0b101..VBG-1.56% + * 0b110..VBG-2.34% + * 0b111..VBG-3.12% + */ +#define PMU_MISC0_REFTOP_VBGADJ(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_REFTOP_VBGADJ_SHIFT)) & PMU_MISC0_REFTOP_VBGADJ_MASK) +#define PMU_MISC0_REFTOP_VBGUP_MASK (0x80U) +#define PMU_MISC0_REFTOP_VBGUP_SHIFT (7U) +#define PMU_MISC0_REFTOP_VBGUP(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_REFTOP_VBGUP_SHIFT)) & PMU_MISC0_REFTOP_VBGUP_MASK) +#define PMU_MISC0_STOP_MODE_CONFIG_MASK (0xC00U) +#define PMU_MISC0_STOP_MODE_CONFIG_SHIFT (10U) +/*! STOP_MODE_CONFIG + * 0b00..SUSPEND (DSM) + * 0b01..Analog regulators are ON. + * 0b10..STOP (lower power) + * 0b11..STOP (very lower power) + */ +#define PMU_MISC0_STOP_MODE_CONFIG(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_STOP_MODE_CONFIG_SHIFT)) & PMU_MISC0_STOP_MODE_CONFIG_MASK) +#define PMU_MISC0_DISCON_HIGH_SNVS_MASK (0x1000U) +#define PMU_MISC0_DISCON_HIGH_SNVS_SHIFT (12U) +/*! DISCON_HIGH_SNVS + * 0b0..Turn on the switch + * 0b1..Turn off the switch + */ +#define PMU_MISC0_DISCON_HIGH_SNVS(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_DISCON_HIGH_SNVS_SHIFT)) & PMU_MISC0_DISCON_HIGH_SNVS_MASK) +#define PMU_MISC0_OSC_I_MASK (0x6000U) +#define PMU_MISC0_OSC_I_SHIFT (13U) +/*! OSC_I + * 0b00..Nominal + * 0b01..Decrease current by 12.5% + * 0b10..Decrease current by 25.0% + * 0b11..Decrease current by 37.5% + */ +#define PMU_MISC0_OSC_I(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_OSC_I_SHIFT)) & PMU_MISC0_OSC_I_MASK) +#define PMU_MISC0_OSC_XTALOK_MASK (0x8000U) +#define PMU_MISC0_OSC_XTALOK_SHIFT (15U) +#define PMU_MISC0_OSC_XTALOK(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_OSC_XTALOK_SHIFT)) & PMU_MISC0_OSC_XTALOK_MASK) +#define PMU_MISC0_OSC_XTALOK_EN_MASK (0x10000U) +#define PMU_MISC0_OSC_XTALOK_EN_SHIFT (16U) +#define PMU_MISC0_OSC_XTALOK_EN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_OSC_XTALOK_EN_SHIFT)) & PMU_MISC0_OSC_XTALOK_EN_MASK) +#define PMU_MISC0_CLKGATE_CTRL_MASK (0x2000000U) +#define PMU_MISC0_CLKGATE_CTRL_SHIFT (25U) +/*! CLKGATE_CTRL + * 0b0..Allow the logic to automatically gate the clock when the XTAL is powered down. + * 0b1..Prevent the logic from ever gating off the clock. + */ +#define PMU_MISC0_CLKGATE_CTRL(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_CLKGATE_CTRL_SHIFT)) & PMU_MISC0_CLKGATE_CTRL_MASK) +#define PMU_MISC0_CLKGATE_DELAY_MASK (0x1C000000U) +#define PMU_MISC0_CLKGATE_DELAY_SHIFT (26U) +/*! CLKGATE_DELAY + * 0b000..0.5ms + * 0b001..1.0ms + * 0b010..2.0ms + * 0b011..3.0ms + * 0b100..4.0ms + * 0b101..5.0ms + * 0b110..6.0ms + * 0b111..7.0ms + */ +#define PMU_MISC0_CLKGATE_DELAY(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_CLKGATE_DELAY_SHIFT)) & PMU_MISC0_CLKGATE_DELAY_MASK) +#define PMU_MISC0_RTC_XTAL_SOURCE_MASK (0x20000000U) +#define PMU_MISC0_RTC_XTAL_SOURCE_SHIFT (29U) +/*! RTC_XTAL_SOURCE + * 0b0..Internal ring oscillator + * 0b1..RTC_XTAL + */ +#define PMU_MISC0_RTC_XTAL_SOURCE(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_RTC_XTAL_SOURCE_SHIFT)) & PMU_MISC0_RTC_XTAL_SOURCE_MASK) +#define PMU_MISC0_XTAL_24M_PWD_MASK (0x40000000U) +#define PMU_MISC0_XTAL_24M_PWD_SHIFT (30U) +#define PMU_MISC0_XTAL_24M_PWD(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_XTAL_24M_PWD_SHIFT)) & PMU_MISC0_XTAL_24M_PWD_MASK) +#define PMU_MISC0_VID_PLL_PREDIV_MASK (0x80000000U) +#define PMU_MISC0_VID_PLL_PREDIV_SHIFT (31U) +/*! VID_PLL_PREDIV + * 0b0..Divide by 1 + * 0b1..Divide by 2 + */ +#define PMU_MISC0_VID_PLL_PREDIV(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_VID_PLL_PREDIV_SHIFT)) & PMU_MISC0_VID_PLL_PREDIV_MASK) +/*! @} */ + +/*! @name MISC0_SET - Miscellaneous Register 0 */ +/*! @{ */ +#define PMU_MISC0_SET_REFTOP_PWD_MASK (0x1U) +#define PMU_MISC0_SET_REFTOP_PWD_SHIFT (0U) +#define PMU_MISC0_SET_REFTOP_PWD(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_SET_REFTOP_PWD_SHIFT)) & PMU_MISC0_SET_REFTOP_PWD_MASK) +#define PMU_MISC0_SET_REFTOP_SELFBIASOFF_MASK (0x8U) +#define PMU_MISC0_SET_REFTOP_SELFBIASOFF_SHIFT (3U) +/*! REFTOP_SELFBIASOFF + * 0b0..Uses coarse bias currents for startup + * 0b1..Uses bandgap-based bias currents for best performance. + */ +#define PMU_MISC0_SET_REFTOP_SELFBIASOFF(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_SET_REFTOP_SELFBIASOFF_SHIFT)) & PMU_MISC0_SET_REFTOP_SELFBIASOFF_MASK) +#define PMU_MISC0_SET_REFTOP_VBGADJ_MASK (0x70U) +#define PMU_MISC0_SET_REFTOP_VBGADJ_SHIFT (4U) +/*! REFTOP_VBGADJ + * 0b000..Nominal VBG + * 0b001..VBG+0.78% + * 0b010..VBG+1.56% + * 0b011..VBG+2.34% + * 0b100..VBG-0.78% + * 0b101..VBG-1.56% + * 0b110..VBG-2.34% + * 0b111..VBG-3.12% + */ +#define PMU_MISC0_SET_REFTOP_VBGADJ(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_SET_REFTOP_VBGADJ_SHIFT)) & PMU_MISC0_SET_REFTOP_VBGADJ_MASK) +#define PMU_MISC0_SET_REFTOP_VBGUP_MASK (0x80U) +#define PMU_MISC0_SET_REFTOP_VBGUP_SHIFT (7U) +#define PMU_MISC0_SET_REFTOP_VBGUP(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_SET_REFTOP_VBGUP_SHIFT)) & PMU_MISC0_SET_REFTOP_VBGUP_MASK) +#define PMU_MISC0_SET_STOP_MODE_CONFIG_MASK (0xC00U) +#define PMU_MISC0_SET_STOP_MODE_CONFIG_SHIFT (10U) +/*! STOP_MODE_CONFIG + * 0b00..SUSPEND (DSM) + * 0b01..Analog regulators are ON. + * 0b10..STOP (lower power) + * 0b11..STOP (very lower power) + */ +#define PMU_MISC0_SET_STOP_MODE_CONFIG(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_SET_STOP_MODE_CONFIG_SHIFT)) & PMU_MISC0_SET_STOP_MODE_CONFIG_MASK) +#define PMU_MISC0_SET_DISCON_HIGH_SNVS_MASK (0x1000U) +#define PMU_MISC0_SET_DISCON_HIGH_SNVS_SHIFT (12U) +/*! DISCON_HIGH_SNVS + * 0b0..Turn on the switch + * 0b1..Turn off the switch + */ +#define PMU_MISC0_SET_DISCON_HIGH_SNVS(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_SET_DISCON_HIGH_SNVS_SHIFT)) & PMU_MISC0_SET_DISCON_HIGH_SNVS_MASK) +#define PMU_MISC0_SET_OSC_I_MASK (0x6000U) +#define PMU_MISC0_SET_OSC_I_SHIFT (13U) +/*! OSC_I + * 0b00..Nominal + * 0b01..Decrease current by 12.5% + * 0b10..Decrease current by 25.0% + * 0b11..Decrease current by 37.5% + */ +#define PMU_MISC0_SET_OSC_I(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_SET_OSC_I_SHIFT)) & PMU_MISC0_SET_OSC_I_MASK) +#define PMU_MISC0_SET_OSC_XTALOK_MASK (0x8000U) +#define PMU_MISC0_SET_OSC_XTALOK_SHIFT (15U) +#define PMU_MISC0_SET_OSC_XTALOK(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_SET_OSC_XTALOK_SHIFT)) & PMU_MISC0_SET_OSC_XTALOK_MASK) +#define PMU_MISC0_SET_OSC_XTALOK_EN_MASK (0x10000U) +#define PMU_MISC0_SET_OSC_XTALOK_EN_SHIFT (16U) +#define PMU_MISC0_SET_OSC_XTALOK_EN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_SET_OSC_XTALOK_EN_SHIFT)) & PMU_MISC0_SET_OSC_XTALOK_EN_MASK) +#define PMU_MISC0_SET_CLKGATE_CTRL_MASK (0x2000000U) +#define PMU_MISC0_SET_CLKGATE_CTRL_SHIFT (25U) +/*! CLKGATE_CTRL + * 0b0..Allow the logic to automatically gate the clock when the XTAL is powered down. + * 0b1..Prevent the logic from ever gating off the clock. + */ +#define PMU_MISC0_SET_CLKGATE_CTRL(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_SET_CLKGATE_CTRL_SHIFT)) & PMU_MISC0_SET_CLKGATE_CTRL_MASK) +#define PMU_MISC0_SET_CLKGATE_DELAY_MASK (0x1C000000U) +#define PMU_MISC0_SET_CLKGATE_DELAY_SHIFT (26U) +/*! CLKGATE_DELAY + * 0b000..0.5ms + * 0b001..1.0ms + * 0b010..2.0ms + * 0b011..3.0ms + * 0b100..4.0ms + * 0b101..5.0ms + * 0b110..6.0ms + * 0b111..7.0ms + */ +#define PMU_MISC0_SET_CLKGATE_DELAY(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_SET_CLKGATE_DELAY_SHIFT)) & PMU_MISC0_SET_CLKGATE_DELAY_MASK) +#define PMU_MISC0_SET_RTC_XTAL_SOURCE_MASK (0x20000000U) +#define PMU_MISC0_SET_RTC_XTAL_SOURCE_SHIFT (29U) +/*! RTC_XTAL_SOURCE + * 0b0..Internal ring oscillator + * 0b1..RTC_XTAL + */ +#define PMU_MISC0_SET_RTC_XTAL_SOURCE(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_SET_RTC_XTAL_SOURCE_SHIFT)) & PMU_MISC0_SET_RTC_XTAL_SOURCE_MASK) +#define PMU_MISC0_SET_XTAL_24M_PWD_MASK (0x40000000U) +#define PMU_MISC0_SET_XTAL_24M_PWD_SHIFT (30U) +#define PMU_MISC0_SET_XTAL_24M_PWD(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_SET_XTAL_24M_PWD_SHIFT)) & PMU_MISC0_SET_XTAL_24M_PWD_MASK) +#define PMU_MISC0_SET_VID_PLL_PREDIV_MASK (0x80000000U) +#define PMU_MISC0_SET_VID_PLL_PREDIV_SHIFT (31U) +/*! VID_PLL_PREDIV + * 0b0..Divide by 1 + * 0b1..Divide by 2 + */ +#define PMU_MISC0_SET_VID_PLL_PREDIV(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_SET_VID_PLL_PREDIV_SHIFT)) & PMU_MISC0_SET_VID_PLL_PREDIV_MASK) +/*! @} */ + +/*! @name MISC0_CLR - Miscellaneous Register 0 */ +/*! @{ */ +#define PMU_MISC0_CLR_REFTOP_PWD_MASK (0x1U) +#define PMU_MISC0_CLR_REFTOP_PWD_SHIFT (0U) +#define PMU_MISC0_CLR_REFTOP_PWD(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_CLR_REFTOP_PWD_SHIFT)) & PMU_MISC0_CLR_REFTOP_PWD_MASK) +#define PMU_MISC0_CLR_REFTOP_SELFBIASOFF_MASK (0x8U) +#define PMU_MISC0_CLR_REFTOP_SELFBIASOFF_SHIFT (3U) +/*! REFTOP_SELFBIASOFF + * 0b0..Uses coarse bias currents for startup + * 0b1..Uses bandgap-based bias currents for best performance. + */ +#define PMU_MISC0_CLR_REFTOP_SELFBIASOFF(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_CLR_REFTOP_SELFBIASOFF_SHIFT)) & PMU_MISC0_CLR_REFTOP_SELFBIASOFF_MASK) +#define PMU_MISC0_CLR_REFTOP_VBGADJ_MASK (0x70U) +#define PMU_MISC0_CLR_REFTOP_VBGADJ_SHIFT (4U) +/*! REFTOP_VBGADJ + * 0b000..Nominal VBG + * 0b001..VBG+0.78% + * 0b010..VBG+1.56% + * 0b011..VBG+2.34% + * 0b100..VBG-0.78% + * 0b101..VBG-1.56% + * 0b110..VBG-2.34% + * 0b111..VBG-3.12% + */ +#define PMU_MISC0_CLR_REFTOP_VBGADJ(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_CLR_REFTOP_VBGADJ_SHIFT)) & PMU_MISC0_CLR_REFTOP_VBGADJ_MASK) +#define PMU_MISC0_CLR_REFTOP_VBGUP_MASK (0x80U) +#define PMU_MISC0_CLR_REFTOP_VBGUP_SHIFT (7U) +#define PMU_MISC0_CLR_REFTOP_VBGUP(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_CLR_REFTOP_VBGUP_SHIFT)) & PMU_MISC0_CLR_REFTOP_VBGUP_MASK) +#define PMU_MISC0_CLR_STOP_MODE_CONFIG_MASK (0xC00U) +#define PMU_MISC0_CLR_STOP_MODE_CONFIG_SHIFT (10U) +/*! STOP_MODE_CONFIG + * 0b00..SUSPEND (DSM) + * 0b01..Analog regulators are ON. + * 0b10..STOP (lower power) + * 0b11..STOP (very lower power) + */ +#define PMU_MISC0_CLR_STOP_MODE_CONFIG(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_CLR_STOP_MODE_CONFIG_SHIFT)) & PMU_MISC0_CLR_STOP_MODE_CONFIG_MASK) +#define PMU_MISC0_CLR_DISCON_HIGH_SNVS_MASK (0x1000U) +#define PMU_MISC0_CLR_DISCON_HIGH_SNVS_SHIFT (12U) +/*! DISCON_HIGH_SNVS + * 0b0..Turn on the switch + * 0b1..Turn off the switch + */ +#define PMU_MISC0_CLR_DISCON_HIGH_SNVS(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_CLR_DISCON_HIGH_SNVS_SHIFT)) & PMU_MISC0_CLR_DISCON_HIGH_SNVS_MASK) +#define PMU_MISC0_CLR_OSC_I_MASK (0x6000U) +#define PMU_MISC0_CLR_OSC_I_SHIFT (13U) +/*! OSC_I + * 0b00..Nominal + * 0b01..Decrease current by 12.5% + * 0b10..Decrease current by 25.0% + * 0b11..Decrease current by 37.5% + */ +#define PMU_MISC0_CLR_OSC_I(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_CLR_OSC_I_SHIFT)) & PMU_MISC0_CLR_OSC_I_MASK) +#define PMU_MISC0_CLR_OSC_XTALOK_MASK (0x8000U) +#define PMU_MISC0_CLR_OSC_XTALOK_SHIFT (15U) +#define PMU_MISC0_CLR_OSC_XTALOK(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_CLR_OSC_XTALOK_SHIFT)) & PMU_MISC0_CLR_OSC_XTALOK_MASK) +#define PMU_MISC0_CLR_OSC_XTALOK_EN_MASK (0x10000U) +#define PMU_MISC0_CLR_OSC_XTALOK_EN_SHIFT (16U) +#define PMU_MISC0_CLR_OSC_XTALOK_EN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_CLR_OSC_XTALOK_EN_SHIFT)) & PMU_MISC0_CLR_OSC_XTALOK_EN_MASK) +#define PMU_MISC0_CLR_CLKGATE_CTRL_MASK (0x2000000U) +#define PMU_MISC0_CLR_CLKGATE_CTRL_SHIFT (25U) +/*! CLKGATE_CTRL + * 0b0..Allow the logic to automatically gate the clock when the XTAL is powered down. + * 0b1..Prevent the logic from ever gating off the clock. + */ +#define PMU_MISC0_CLR_CLKGATE_CTRL(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_CLR_CLKGATE_CTRL_SHIFT)) & PMU_MISC0_CLR_CLKGATE_CTRL_MASK) +#define PMU_MISC0_CLR_CLKGATE_DELAY_MASK (0x1C000000U) +#define PMU_MISC0_CLR_CLKGATE_DELAY_SHIFT (26U) +/*! CLKGATE_DELAY + * 0b000..0.5ms + * 0b001..1.0ms + * 0b010..2.0ms + * 0b011..3.0ms + * 0b100..4.0ms + * 0b101..5.0ms + * 0b110..6.0ms + * 0b111..7.0ms + */ +#define PMU_MISC0_CLR_CLKGATE_DELAY(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_CLR_CLKGATE_DELAY_SHIFT)) & PMU_MISC0_CLR_CLKGATE_DELAY_MASK) +#define PMU_MISC0_CLR_RTC_XTAL_SOURCE_MASK (0x20000000U) +#define PMU_MISC0_CLR_RTC_XTAL_SOURCE_SHIFT (29U) +/*! RTC_XTAL_SOURCE + * 0b0..Internal ring oscillator + * 0b1..RTC_XTAL + */ +#define PMU_MISC0_CLR_RTC_XTAL_SOURCE(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_CLR_RTC_XTAL_SOURCE_SHIFT)) & PMU_MISC0_CLR_RTC_XTAL_SOURCE_MASK) +#define PMU_MISC0_CLR_XTAL_24M_PWD_MASK (0x40000000U) +#define PMU_MISC0_CLR_XTAL_24M_PWD_SHIFT (30U) +#define PMU_MISC0_CLR_XTAL_24M_PWD(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_CLR_XTAL_24M_PWD_SHIFT)) & PMU_MISC0_CLR_XTAL_24M_PWD_MASK) +#define PMU_MISC0_CLR_VID_PLL_PREDIV_MASK (0x80000000U) +#define PMU_MISC0_CLR_VID_PLL_PREDIV_SHIFT (31U) +/*! VID_PLL_PREDIV + * 0b0..Divide by 1 + * 0b1..Divide by 2 + */ +#define PMU_MISC0_CLR_VID_PLL_PREDIV(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_CLR_VID_PLL_PREDIV_SHIFT)) & PMU_MISC0_CLR_VID_PLL_PREDIV_MASK) +/*! @} */ + +/*! @name MISC0_TOG - Miscellaneous Register 0 */ +/*! @{ */ +#define PMU_MISC0_TOG_REFTOP_PWD_MASK (0x1U) +#define PMU_MISC0_TOG_REFTOP_PWD_SHIFT (0U) +#define PMU_MISC0_TOG_REFTOP_PWD(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_TOG_REFTOP_PWD_SHIFT)) & PMU_MISC0_TOG_REFTOP_PWD_MASK) +#define PMU_MISC0_TOG_REFTOP_SELFBIASOFF_MASK (0x8U) +#define PMU_MISC0_TOG_REFTOP_SELFBIASOFF_SHIFT (3U) +/*! REFTOP_SELFBIASOFF + * 0b0..Uses coarse bias currents for startup + * 0b1..Uses bandgap-based bias currents for best performance. + */ +#define PMU_MISC0_TOG_REFTOP_SELFBIASOFF(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_TOG_REFTOP_SELFBIASOFF_SHIFT)) & PMU_MISC0_TOG_REFTOP_SELFBIASOFF_MASK) +#define PMU_MISC0_TOG_REFTOP_VBGADJ_MASK (0x70U) +#define PMU_MISC0_TOG_REFTOP_VBGADJ_SHIFT (4U) +/*! REFTOP_VBGADJ + * 0b000..Nominal VBG + * 0b001..VBG+0.78% + * 0b010..VBG+1.56% + * 0b011..VBG+2.34% + * 0b100..VBG-0.78% + * 0b101..VBG-1.56% + * 0b110..VBG-2.34% + * 0b111..VBG-3.12% + */ +#define PMU_MISC0_TOG_REFTOP_VBGADJ(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_TOG_REFTOP_VBGADJ_SHIFT)) & PMU_MISC0_TOG_REFTOP_VBGADJ_MASK) +#define PMU_MISC0_TOG_REFTOP_VBGUP_MASK (0x80U) +#define PMU_MISC0_TOG_REFTOP_VBGUP_SHIFT (7U) +#define PMU_MISC0_TOG_REFTOP_VBGUP(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_TOG_REFTOP_VBGUP_SHIFT)) & PMU_MISC0_TOG_REFTOP_VBGUP_MASK) +#define PMU_MISC0_TOG_STOP_MODE_CONFIG_MASK (0xC00U) +#define PMU_MISC0_TOG_STOP_MODE_CONFIG_SHIFT (10U) +/*! STOP_MODE_CONFIG + * 0b00..SUSPEND (DSM) + * 0b01..Analog regulators are ON. + * 0b10..STOP (lower power) + * 0b11..STOP (very lower power) + */ +#define PMU_MISC0_TOG_STOP_MODE_CONFIG(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_TOG_STOP_MODE_CONFIG_SHIFT)) & PMU_MISC0_TOG_STOP_MODE_CONFIG_MASK) +#define PMU_MISC0_TOG_DISCON_HIGH_SNVS_MASK (0x1000U) +#define PMU_MISC0_TOG_DISCON_HIGH_SNVS_SHIFT (12U) +/*! DISCON_HIGH_SNVS + * 0b0..Turn on the switch + * 0b1..Turn off the switch + */ +#define PMU_MISC0_TOG_DISCON_HIGH_SNVS(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_TOG_DISCON_HIGH_SNVS_SHIFT)) & PMU_MISC0_TOG_DISCON_HIGH_SNVS_MASK) +#define PMU_MISC0_TOG_OSC_I_MASK (0x6000U) +#define PMU_MISC0_TOG_OSC_I_SHIFT (13U) +/*! OSC_I + * 0b00..Nominal + * 0b01..Decrease current by 12.5% + * 0b10..Decrease current by 25.0% + * 0b11..Decrease current by 37.5% + */ +#define PMU_MISC0_TOG_OSC_I(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_TOG_OSC_I_SHIFT)) & PMU_MISC0_TOG_OSC_I_MASK) +#define PMU_MISC0_TOG_OSC_XTALOK_MASK (0x8000U) +#define PMU_MISC0_TOG_OSC_XTALOK_SHIFT (15U) +#define PMU_MISC0_TOG_OSC_XTALOK(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_TOG_OSC_XTALOK_SHIFT)) & PMU_MISC0_TOG_OSC_XTALOK_MASK) +#define PMU_MISC0_TOG_OSC_XTALOK_EN_MASK (0x10000U) +#define PMU_MISC0_TOG_OSC_XTALOK_EN_SHIFT (16U) +#define PMU_MISC0_TOG_OSC_XTALOK_EN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_TOG_OSC_XTALOK_EN_SHIFT)) & PMU_MISC0_TOG_OSC_XTALOK_EN_MASK) +#define PMU_MISC0_TOG_CLKGATE_CTRL_MASK (0x2000000U) +#define PMU_MISC0_TOG_CLKGATE_CTRL_SHIFT (25U) +/*! CLKGATE_CTRL + * 0b0..Allow the logic to automatically gate the clock when the XTAL is powered down. + * 0b1..Prevent the logic from ever gating off the clock. + */ +#define PMU_MISC0_TOG_CLKGATE_CTRL(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_TOG_CLKGATE_CTRL_SHIFT)) & PMU_MISC0_TOG_CLKGATE_CTRL_MASK) +#define PMU_MISC0_TOG_CLKGATE_DELAY_MASK (0x1C000000U) +#define PMU_MISC0_TOG_CLKGATE_DELAY_SHIFT (26U) +/*! CLKGATE_DELAY + * 0b000..0.5ms + * 0b001..1.0ms + * 0b010..2.0ms + * 0b011..3.0ms + * 0b100..4.0ms + * 0b101..5.0ms + * 0b110..6.0ms + * 0b111..7.0ms + */ +#define PMU_MISC0_TOG_CLKGATE_DELAY(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_TOG_CLKGATE_DELAY_SHIFT)) & PMU_MISC0_TOG_CLKGATE_DELAY_MASK) +#define PMU_MISC0_TOG_RTC_XTAL_SOURCE_MASK (0x20000000U) +#define PMU_MISC0_TOG_RTC_XTAL_SOURCE_SHIFT (29U) +/*! RTC_XTAL_SOURCE + * 0b0..Internal ring oscillator + * 0b1..RTC_XTAL + */ +#define PMU_MISC0_TOG_RTC_XTAL_SOURCE(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_TOG_RTC_XTAL_SOURCE_SHIFT)) & PMU_MISC0_TOG_RTC_XTAL_SOURCE_MASK) +#define PMU_MISC0_TOG_XTAL_24M_PWD_MASK (0x40000000U) +#define PMU_MISC0_TOG_XTAL_24M_PWD_SHIFT (30U) +#define PMU_MISC0_TOG_XTAL_24M_PWD(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_TOG_XTAL_24M_PWD_SHIFT)) & PMU_MISC0_TOG_XTAL_24M_PWD_MASK) +#define PMU_MISC0_TOG_VID_PLL_PREDIV_MASK (0x80000000U) +#define PMU_MISC0_TOG_VID_PLL_PREDIV_SHIFT (31U) +/*! VID_PLL_PREDIV + * 0b0..Divide by 1 + * 0b1..Divide by 2 + */ +#define PMU_MISC0_TOG_VID_PLL_PREDIV(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_TOG_VID_PLL_PREDIV_SHIFT)) & PMU_MISC0_TOG_VID_PLL_PREDIV_MASK) +/*! @} */ + +/*! @name MISC1 - Miscellaneous Register 1 */ +/*! @{ */ +#define PMU_MISC1_LVDS1_CLK_SEL_MASK (0x1FU) +#define PMU_MISC1_LVDS1_CLK_SEL_SHIFT (0U) +/*! LVDS1_CLK_SEL + * 0b00000..Arm PLL + * 0b00001..System PLL + * 0b00010..ref_pfd4_clk == pll2_pfd0_clk + * 0b00011..ref_pfd5_clk == pll2_pfd1_clk + * 0b00100..ref_pfd6_clk == pll2_pfd2_clk + * 0b00101..ref_pfd7_clk == pll2_pfd3_clk + * 0b00110..Audio PLL + * 0b00111..Video PLL + * 0b01001..ethernet ref clock (ENET_PLL) + * 0b01100..USB1 PLL clock + * 0b01101..USB2 PLL clock + * 0b01110..ref_pfd0_clk == pll3_pfd0_clk + * 0b01111..ref_pfd1_clk == pll3_pfd1_clk + * 0b10000..ref_pfd2_clk == pll3_pfd2_clk + * 0b10001..ref_pfd3_clk == pll3_pfd3_clk + * 0b10010..xtal (24M) + */ +#define PMU_MISC1_LVDS1_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_LVDS1_CLK_SEL_SHIFT)) & PMU_MISC1_LVDS1_CLK_SEL_MASK) +#define PMU_MISC1_LVDS2_CLK_SEL_MASK (0x3E0U) +#define PMU_MISC1_LVDS2_CLK_SEL_SHIFT (5U) +/*! LVDS2_CLK_SEL + * 0b00000..Arm PLL + * 0b00001..System PLL + * 0b00010..ref_pfd4_clk == pll2_pfd0_clk + * 0b00011..ref_pfd5_clk == pll2_pfd1_clk + * 0b00100..ref_pfd6_clk == pll2_pfd2_clk + * 0b00101..ref_pfd7_clk == pll2_pfd3_clk + * 0b00110..Audio PLL + * 0b00111..Video PLL + * 0b01000..MLB PLL + * 0b01001..ethernet ref clock (ENET_PLL) + * 0b01010..PCIe ref clock (125M) + * 0b01011..SATA ref clock (100M) + * 0b01100..USB1 PLL clock + * 0b01101..USB2 PLL clock + * 0b01110..ref_pfd0_clk == pll3_pfd0_clk + * 0b01111..ref_pfd1_clk == pll3_pfd1_clk + * 0b10000..ref_pfd2_clk == pll3_pfd2_clk + * 0b10001..ref_pfd3_clk == pll3_pfd3_clk + * 0b10010..xtal (24M) + * 0b10011..LVDS1 (loopback) + * 0b10100..LVDS2 (not useful) + */ +#define PMU_MISC1_LVDS2_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_LVDS2_CLK_SEL_SHIFT)) & PMU_MISC1_LVDS2_CLK_SEL_MASK) +#define PMU_MISC1_LVDSCLK1_OBEN_MASK (0x400U) +#define PMU_MISC1_LVDSCLK1_OBEN_SHIFT (10U) +#define PMU_MISC1_LVDSCLK1_OBEN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_LVDSCLK1_OBEN_SHIFT)) & PMU_MISC1_LVDSCLK1_OBEN_MASK) +#define PMU_MISC1_LVDSCLK2_OBEN_MASK (0x800U) +#define PMU_MISC1_LVDSCLK2_OBEN_SHIFT (11U) +#define PMU_MISC1_LVDSCLK2_OBEN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_LVDSCLK2_OBEN_SHIFT)) & PMU_MISC1_LVDSCLK2_OBEN_MASK) +#define PMU_MISC1_LVDSCLK1_IBEN_MASK (0x1000U) +#define PMU_MISC1_LVDSCLK1_IBEN_SHIFT (12U) +#define PMU_MISC1_LVDSCLK1_IBEN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_LVDSCLK1_IBEN_SHIFT)) & PMU_MISC1_LVDSCLK1_IBEN_MASK) +#define PMU_MISC1_LVDSCLK2_IBEN_MASK (0x2000U) +#define PMU_MISC1_LVDSCLK2_IBEN_SHIFT (13U) +#define PMU_MISC1_LVDSCLK2_IBEN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_LVDSCLK2_IBEN_SHIFT)) & PMU_MISC1_LVDSCLK2_IBEN_MASK) +#define PMU_MISC1_PFD_480_AUTOGATE_EN_MASK (0x10000U) +#define PMU_MISC1_PFD_480_AUTOGATE_EN_SHIFT (16U) +#define PMU_MISC1_PFD_480_AUTOGATE_EN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_PFD_480_AUTOGATE_EN_SHIFT)) & PMU_MISC1_PFD_480_AUTOGATE_EN_MASK) +#define PMU_MISC1_PFD_528_AUTOGATE_EN_MASK (0x20000U) +#define PMU_MISC1_PFD_528_AUTOGATE_EN_SHIFT (17U) +#define PMU_MISC1_PFD_528_AUTOGATE_EN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_PFD_528_AUTOGATE_EN_SHIFT)) & PMU_MISC1_PFD_528_AUTOGATE_EN_MASK) +#define PMU_MISC1_IRQ_TEMPPANIC_MASK (0x8000000U) +#define PMU_MISC1_IRQ_TEMPPANIC_SHIFT (27U) +#define PMU_MISC1_IRQ_TEMPPANIC(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_IRQ_TEMPPANIC_SHIFT)) & PMU_MISC1_IRQ_TEMPPANIC_MASK) +#define PMU_MISC1_IRQ_TEMPLOW_MASK (0x10000000U) +#define PMU_MISC1_IRQ_TEMPLOW_SHIFT (28U) +#define PMU_MISC1_IRQ_TEMPLOW(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_IRQ_TEMPLOW_SHIFT)) & PMU_MISC1_IRQ_TEMPLOW_MASK) +#define PMU_MISC1_IRQ_TEMPHIGH_MASK (0x20000000U) +#define PMU_MISC1_IRQ_TEMPHIGH_SHIFT (29U) +#define PMU_MISC1_IRQ_TEMPHIGH(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_IRQ_TEMPHIGH_SHIFT)) & PMU_MISC1_IRQ_TEMPHIGH_MASK) +#define PMU_MISC1_IRQ_ANA_BO_MASK (0x40000000U) +#define PMU_MISC1_IRQ_ANA_BO_SHIFT (30U) +#define PMU_MISC1_IRQ_ANA_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_IRQ_ANA_BO_SHIFT)) & PMU_MISC1_IRQ_ANA_BO_MASK) +#define PMU_MISC1_IRQ_DIG_BO_MASK (0x80000000U) +#define PMU_MISC1_IRQ_DIG_BO_SHIFT (31U) +#define PMU_MISC1_IRQ_DIG_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_IRQ_DIG_BO_SHIFT)) & PMU_MISC1_IRQ_DIG_BO_MASK) +/*! @} */ + +/*! @name MISC1_SET - Miscellaneous Register 1 */ +/*! @{ */ +#define PMU_MISC1_SET_LVDS1_CLK_SEL_MASK (0x1FU) +#define PMU_MISC1_SET_LVDS1_CLK_SEL_SHIFT (0U) +/*! LVDS1_CLK_SEL + * 0b00000..Arm PLL + * 0b00001..System PLL + * 0b00010..ref_pfd4_clk == pll2_pfd0_clk + * 0b00011..ref_pfd5_clk == pll2_pfd1_clk + * 0b00100..ref_pfd6_clk == pll2_pfd2_clk + * 0b00101..ref_pfd7_clk == pll2_pfd3_clk + * 0b00110..Audio PLL + * 0b00111..Video PLL + * 0b01001..ethernet ref clock (ENET_PLL) + * 0b01100..USB1 PLL clock + * 0b01101..USB2 PLL clock + * 0b01110..ref_pfd0_clk == pll3_pfd0_clk + * 0b01111..ref_pfd1_clk == pll3_pfd1_clk + * 0b10000..ref_pfd2_clk == pll3_pfd2_clk + * 0b10001..ref_pfd3_clk == pll3_pfd3_clk + * 0b10010..xtal (24M) + */ +#define PMU_MISC1_SET_LVDS1_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_SET_LVDS1_CLK_SEL_SHIFT)) & PMU_MISC1_SET_LVDS1_CLK_SEL_MASK) +#define PMU_MISC1_SET_LVDS2_CLK_SEL_MASK (0x3E0U) +#define PMU_MISC1_SET_LVDS2_CLK_SEL_SHIFT (5U) +/*! LVDS2_CLK_SEL + * 0b00000..Arm PLL + * 0b00001..System PLL + * 0b00010..ref_pfd4_clk == pll2_pfd0_clk + * 0b00011..ref_pfd5_clk == pll2_pfd1_clk + * 0b00100..ref_pfd6_clk == pll2_pfd2_clk + * 0b00101..ref_pfd7_clk == pll2_pfd3_clk + * 0b00110..Audio PLL + * 0b00111..Video PLL + * 0b01000..MLB PLL + * 0b01001..ethernet ref clock (ENET_PLL) + * 0b01010..PCIe ref clock (125M) + * 0b01011..SATA ref clock (100M) + * 0b01100..USB1 PLL clock + * 0b01101..USB2 PLL clock + * 0b01110..ref_pfd0_clk == pll3_pfd0_clk + * 0b01111..ref_pfd1_clk == pll3_pfd1_clk + * 0b10000..ref_pfd2_clk == pll3_pfd2_clk + * 0b10001..ref_pfd3_clk == pll3_pfd3_clk + * 0b10010..xtal (24M) + * 0b10011..LVDS1 (loopback) + * 0b10100..LVDS2 (not useful) + */ +#define PMU_MISC1_SET_LVDS2_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_SET_LVDS2_CLK_SEL_SHIFT)) & PMU_MISC1_SET_LVDS2_CLK_SEL_MASK) +#define PMU_MISC1_SET_LVDSCLK1_OBEN_MASK (0x400U) +#define PMU_MISC1_SET_LVDSCLK1_OBEN_SHIFT (10U) +#define PMU_MISC1_SET_LVDSCLK1_OBEN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_SET_LVDSCLK1_OBEN_SHIFT)) & PMU_MISC1_SET_LVDSCLK1_OBEN_MASK) +#define PMU_MISC1_SET_LVDSCLK2_OBEN_MASK (0x800U) +#define PMU_MISC1_SET_LVDSCLK2_OBEN_SHIFT (11U) +#define PMU_MISC1_SET_LVDSCLK2_OBEN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_SET_LVDSCLK2_OBEN_SHIFT)) & PMU_MISC1_SET_LVDSCLK2_OBEN_MASK) +#define PMU_MISC1_SET_LVDSCLK1_IBEN_MASK (0x1000U) +#define PMU_MISC1_SET_LVDSCLK1_IBEN_SHIFT (12U) +#define PMU_MISC1_SET_LVDSCLK1_IBEN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_SET_LVDSCLK1_IBEN_SHIFT)) & PMU_MISC1_SET_LVDSCLK1_IBEN_MASK) +#define PMU_MISC1_SET_LVDSCLK2_IBEN_MASK (0x2000U) +#define PMU_MISC1_SET_LVDSCLK2_IBEN_SHIFT (13U) +#define PMU_MISC1_SET_LVDSCLK2_IBEN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_SET_LVDSCLK2_IBEN_SHIFT)) & PMU_MISC1_SET_LVDSCLK2_IBEN_MASK) +#define PMU_MISC1_SET_PFD_480_AUTOGATE_EN_MASK (0x10000U) +#define PMU_MISC1_SET_PFD_480_AUTOGATE_EN_SHIFT (16U) +#define PMU_MISC1_SET_PFD_480_AUTOGATE_EN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_SET_PFD_480_AUTOGATE_EN_SHIFT)) & PMU_MISC1_SET_PFD_480_AUTOGATE_EN_MASK) +#define PMU_MISC1_SET_PFD_528_AUTOGATE_EN_MASK (0x20000U) +#define PMU_MISC1_SET_PFD_528_AUTOGATE_EN_SHIFT (17U) +#define PMU_MISC1_SET_PFD_528_AUTOGATE_EN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_SET_PFD_528_AUTOGATE_EN_SHIFT)) & PMU_MISC1_SET_PFD_528_AUTOGATE_EN_MASK) +#define PMU_MISC1_SET_IRQ_TEMPPANIC_MASK (0x8000000U) +#define PMU_MISC1_SET_IRQ_TEMPPANIC_SHIFT (27U) +#define PMU_MISC1_SET_IRQ_TEMPPANIC(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_SET_IRQ_TEMPPANIC_SHIFT)) & PMU_MISC1_SET_IRQ_TEMPPANIC_MASK) +#define PMU_MISC1_SET_IRQ_TEMPLOW_MASK (0x10000000U) +#define PMU_MISC1_SET_IRQ_TEMPLOW_SHIFT (28U) +#define PMU_MISC1_SET_IRQ_TEMPLOW(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_SET_IRQ_TEMPLOW_SHIFT)) & PMU_MISC1_SET_IRQ_TEMPLOW_MASK) +#define PMU_MISC1_SET_IRQ_TEMPHIGH_MASK (0x20000000U) +#define PMU_MISC1_SET_IRQ_TEMPHIGH_SHIFT (29U) +#define PMU_MISC1_SET_IRQ_TEMPHIGH(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_SET_IRQ_TEMPHIGH_SHIFT)) & PMU_MISC1_SET_IRQ_TEMPHIGH_MASK) +#define PMU_MISC1_SET_IRQ_ANA_BO_MASK (0x40000000U) +#define PMU_MISC1_SET_IRQ_ANA_BO_SHIFT (30U) +#define PMU_MISC1_SET_IRQ_ANA_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_SET_IRQ_ANA_BO_SHIFT)) & PMU_MISC1_SET_IRQ_ANA_BO_MASK) +#define PMU_MISC1_SET_IRQ_DIG_BO_MASK (0x80000000U) +#define PMU_MISC1_SET_IRQ_DIG_BO_SHIFT (31U) +#define PMU_MISC1_SET_IRQ_DIG_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_SET_IRQ_DIG_BO_SHIFT)) & PMU_MISC1_SET_IRQ_DIG_BO_MASK) +/*! @} */ + +/*! @name MISC1_CLR - Miscellaneous Register 1 */ +/*! @{ */ +#define PMU_MISC1_CLR_LVDS1_CLK_SEL_MASK (0x1FU) +#define PMU_MISC1_CLR_LVDS1_CLK_SEL_SHIFT (0U) +/*! LVDS1_CLK_SEL + * 0b00000..Arm PLL + * 0b00001..System PLL + * 0b00010..ref_pfd4_clk == pll2_pfd0_clk + * 0b00011..ref_pfd5_clk == pll2_pfd1_clk + * 0b00100..ref_pfd6_clk == pll2_pfd2_clk + * 0b00101..ref_pfd7_clk == pll2_pfd3_clk + * 0b00110..Audio PLL + * 0b00111..Video PLL + * 0b01001..ethernet ref clock (ENET_PLL) + * 0b01100..USB1 PLL clock + * 0b01101..USB2 PLL clock + * 0b01110..ref_pfd0_clk == pll3_pfd0_clk + * 0b01111..ref_pfd1_clk == pll3_pfd1_clk + * 0b10000..ref_pfd2_clk == pll3_pfd2_clk + * 0b10001..ref_pfd3_clk == pll3_pfd3_clk + * 0b10010..xtal (24M) + */ +#define PMU_MISC1_CLR_LVDS1_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_CLR_LVDS1_CLK_SEL_SHIFT)) & PMU_MISC1_CLR_LVDS1_CLK_SEL_MASK) +#define PMU_MISC1_CLR_LVDS2_CLK_SEL_MASK (0x3E0U) +#define PMU_MISC1_CLR_LVDS2_CLK_SEL_SHIFT (5U) +/*! LVDS2_CLK_SEL + * 0b00000..Arm PLL + * 0b00001..System PLL + * 0b00010..ref_pfd4_clk == pll2_pfd0_clk + * 0b00011..ref_pfd5_clk == pll2_pfd1_clk + * 0b00100..ref_pfd6_clk == pll2_pfd2_clk + * 0b00101..ref_pfd7_clk == pll2_pfd3_clk + * 0b00110..Audio PLL + * 0b00111..Video PLL + * 0b01000..MLB PLL + * 0b01001..ethernet ref clock (ENET_PLL) + * 0b01010..PCIe ref clock (125M) + * 0b01011..SATA ref clock (100M) + * 0b01100..USB1 PLL clock + * 0b01101..USB2 PLL clock + * 0b01110..ref_pfd0_clk == pll3_pfd0_clk + * 0b01111..ref_pfd1_clk == pll3_pfd1_clk + * 0b10000..ref_pfd2_clk == pll3_pfd2_clk + * 0b10001..ref_pfd3_clk == pll3_pfd3_clk + * 0b10010..xtal (24M) + * 0b10011..LVDS1 (loopback) + * 0b10100..LVDS2 (not useful) + */ +#define PMU_MISC1_CLR_LVDS2_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_CLR_LVDS2_CLK_SEL_SHIFT)) & PMU_MISC1_CLR_LVDS2_CLK_SEL_MASK) +#define PMU_MISC1_CLR_LVDSCLK1_OBEN_MASK (0x400U) +#define PMU_MISC1_CLR_LVDSCLK1_OBEN_SHIFT (10U) +#define PMU_MISC1_CLR_LVDSCLK1_OBEN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_CLR_LVDSCLK1_OBEN_SHIFT)) & PMU_MISC1_CLR_LVDSCLK1_OBEN_MASK) +#define PMU_MISC1_CLR_LVDSCLK2_OBEN_MASK (0x800U) +#define PMU_MISC1_CLR_LVDSCLK2_OBEN_SHIFT (11U) +#define PMU_MISC1_CLR_LVDSCLK2_OBEN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_CLR_LVDSCLK2_OBEN_SHIFT)) & PMU_MISC1_CLR_LVDSCLK2_OBEN_MASK) +#define PMU_MISC1_CLR_LVDSCLK1_IBEN_MASK (0x1000U) +#define PMU_MISC1_CLR_LVDSCLK1_IBEN_SHIFT (12U) +#define PMU_MISC1_CLR_LVDSCLK1_IBEN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_CLR_LVDSCLK1_IBEN_SHIFT)) & PMU_MISC1_CLR_LVDSCLK1_IBEN_MASK) +#define PMU_MISC1_CLR_LVDSCLK2_IBEN_MASK (0x2000U) +#define PMU_MISC1_CLR_LVDSCLK2_IBEN_SHIFT (13U) +#define PMU_MISC1_CLR_LVDSCLK2_IBEN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_CLR_LVDSCLK2_IBEN_SHIFT)) & PMU_MISC1_CLR_LVDSCLK2_IBEN_MASK) +#define PMU_MISC1_CLR_PFD_480_AUTOGATE_EN_MASK (0x10000U) +#define PMU_MISC1_CLR_PFD_480_AUTOGATE_EN_SHIFT (16U) +#define PMU_MISC1_CLR_PFD_480_AUTOGATE_EN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_CLR_PFD_480_AUTOGATE_EN_SHIFT)) & PMU_MISC1_CLR_PFD_480_AUTOGATE_EN_MASK) +#define PMU_MISC1_CLR_PFD_528_AUTOGATE_EN_MASK (0x20000U) +#define PMU_MISC1_CLR_PFD_528_AUTOGATE_EN_SHIFT (17U) +#define PMU_MISC1_CLR_PFD_528_AUTOGATE_EN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_CLR_PFD_528_AUTOGATE_EN_SHIFT)) & PMU_MISC1_CLR_PFD_528_AUTOGATE_EN_MASK) +#define PMU_MISC1_CLR_IRQ_TEMPPANIC_MASK (0x8000000U) +#define PMU_MISC1_CLR_IRQ_TEMPPANIC_SHIFT (27U) +#define PMU_MISC1_CLR_IRQ_TEMPPANIC(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_CLR_IRQ_TEMPPANIC_SHIFT)) & PMU_MISC1_CLR_IRQ_TEMPPANIC_MASK) +#define PMU_MISC1_CLR_IRQ_TEMPLOW_MASK (0x10000000U) +#define PMU_MISC1_CLR_IRQ_TEMPLOW_SHIFT (28U) +#define PMU_MISC1_CLR_IRQ_TEMPLOW(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_CLR_IRQ_TEMPLOW_SHIFT)) & PMU_MISC1_CLR_IRQ_TEMPLOW_MASK) +#define PMU_MISC1_CLR_IRQ_TEMPHIGH_MASK (0x20000000U) +#define PMU_MISC1_CLR_IRQ_TEMPHIGH_SHIFT (29U) +#define PMU_MISC1_CLR_IRQ_TEMPHIGH(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_CLR_IRQ_TEMPHIGH_SHIFT)) & PMU_MISC1_CLR_IRQ_TEMPHIGH_MASK) +#define PMU_MISC1_CLR_IRQ_ANA_BO_MASK (0x40000000U) +#define PMU_MISC1_CLR_IRQ_ANA_BO_SHIFT (30U) +#define PMU_MISC1_CLR_IRQ_ANA_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_CLR_IRQ_ANA_BO_SHIFT)) & PMU_MISC1_CLR_IRQ_ANA_BO_MASK) +#define PMU_MISC1_CLR_IRQ_DIG_BO_MASK (0x80000000U) +#define PMU_MISC1_CLR_IRQ_DIG_BO_SHIFT (31U) +#define PMU_MISC1_CLR_IRQ_DIG_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_CLR_IRQ_DIG_BO_SHIFT)) & PMU_MISC1_CLR_IRQ_DIG_BO_MASK) +/*! @} */ + +/*! @name MISC1_TOG - Miscellaneous Register 1 */ +/*! @{ */ +#define PMU_MISC1_TOG_LVDS1_CLK_SEL_MASK (0x1FU) +#define PMU_MISC1_TOG_LVDS1_CLK_SEL_SHIFT (0U) +/*! LVDS1_CLK_SEL + * 0b00000..Arm PLL + * 0b00001..System PLL + * 0b00010..ref_pfd4_clk == pll2_pfd0_clk + * 0b00011..ref_pfd5_clk == pll2_pfd1_clk + * 0b00100..ref_pfd6_clk == pll2_pfd2_clk + * 0b00101..ref_pfd7_clk == pll2_pfd3_clk + * 0b00110..Audio PLL + * 0b00111..Video PLL + * 0b01001..ethernet ref clock (ENET_PLL) + * 0b01100..USB1 PLL clock + * 0b01101..USB2 PLL clock + * 0b01110..ref_pfd0_clk == pll3_pfd0_clk + * 0b01111..ref_pfd1_clk == pll3_pfd1_clk + * 0b10000..ref_pfd2_clk == pll3_pfd2_clk + * 0b10001..ref_pfd3_clk == pll3_pfd3_clk + * 0b10010..xtal (24M) + */ +#define PMU_MISC1_TOG_LVDS1_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_TOG_LVDS1_CLK_SEL_SHIFT)) & PMU_MISC1_TOG_LVDS1_CLK_SEL_MASK) +#define PMU_MISC1_TOG_LVDS2_CLK_SEL_MASK (0x3E0U) +#define PMU_MISC1_TOG_LVDS2_CLK_SEL_SHIFT (5U) +/*! LVDS2_CLK_SEL + * 0b00000..Arm PLL + * 0b00001..System PLL + * 0b00010..ref_pfd4_clk == pll2_pfd0_clk + * 0b00011..ref_pfd5_clk == pll2_pfd1_clk + * 0b00100..ref_pfd6_clk == pll2_pfd2_clk + * 0b00101..ref_pfd7_clk == pll2_pfd3_clk + * 0b00110..Audio PLL + * 0b00111..Video PLL + * 0b01000..MLB PLL + * 0b01001..ethernet ref clock (ENET_PLL) + * 0b01010..PCIe ref clock (125M) + * 0b01011..SATA ref clock (100M) + * 0b01100..USB1 PLL clock + * 0b01101..USB2 PLL clock + * 0b01110..ref_pfd0_clk == pll3_pfd0_clk + * 0b01111..ref_pfd1_clk == pll3_pfd1_clk + * 0b10000..ref_pfd2_clk == pll3_pfd2_clk + * 0b10001..ref_pfd3_clk == pll3_pfd3_clk + * 0b10010..xtal (24M) + * 0b10011..LVDS1 (loopback) + * 0b10100..LVDS2 (not useful) + */ +#define PMU_MISC1_TOG_LVDS2_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_TOG_LVDS2_CLK_SEL_SHIFT)) & PMU_MISC1_TOG_LVDS2_CLK_SEL_MASK) +#define PMU_MISC1_TOG_LVDSCLK1_OBEN_MASK (0x400U) +#define PMU_MISC1_TOG_LVDSCLK1_OBEN_SHIFT (10U) +#define PMU_MISC1_TOG_LVDSCLK1_OBEN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_TOG_LVDSCLK1_OBEN_SHIFT)) & PMU_MISC1_TOG_LVDSCLK1_OBEN_MASK) +#define PMU_MISC1_TOG_LVDSCLK2_OBEN_MASK (0x800U) +#define PMU_MISC1_TOG_LVDSCLK2_OBEN_SHIFT (11U) +#define PMU_MISC1_TOG_LVDSCLK2_OBEN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_TOG_LVDSCLK2_OBEN_SHIFT)) & PMU_MISC1_TOG_LVDSCLK2_OBEN_MASK) +#define PMU_MISC1_TOG_LVDSCLK1_IBEN_MASK (0x1000U) +#define PMU_MISC1_TOG_LVDSCLK1_IBEN_SHIFT (12U) +#define PMU_MISC1_TOG_LVDSCLK1_IBEN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_TOG_LVDSCLK1_IBEN_SHIFT)) & PMU_MISC1_TOG_LVDSCLK1_IBEN_MASK) +#define PMU_MISC1_TOG_LVDSCLK2_IBEN_MASK (0x2000U) +#define PMU_MISC1_TOG_LVDSCLK2_IBEN_SHIFT (13U) +#define PMU_MISC1_TOG_LVDSCLK2_IBEN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_TOG_LVDSCLK2_IBEN_SHIFT)) & PMU_MISC1_TOG_LVDSCLK2_IBEN_MASK) +#define PMU_MISC1_TOG_PFD_480_AUTOGATE_EN_MASK (0x10000U) +#define PMU_MISC1_TOG_PFD_480_AUTOGATE_EN_SHIFT (16U) +#define PMU_MISC1_TOG_PFD_480_AUTOGATE_EN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_TOG_PFD_480_AUTOGATE_EN_SHIFT)) & PMU_MISC1_TOG_PFD_480_AUTOGATE_EN_MASK) +#define PMU_MISC1_TOG_PFD_528_AUTOGATE_EN_MASK (0x20000U) +#define PMU_MISC1_TOG_PFD_528_AUTOGATE_EN_SHIFT (17U) +#define PMU_MISC1_TOG_PFD_528_AUTOGATE_EN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_TOG_PFD_528_AUTOGATE_EN_SHIFT)) & PMU_MISC1_TOG_PFD_528_AUTOGATE_EN_MASK) +#define PMU_MISC1_TOG_IRQ_TEMPPANIC_MASK (0x8000000U) +#define PMU_MISC1_TOG_IRQ_TEMPPANIC_SHIFT (27U) +#define PMU_MISC1_TOG_IRQ_TEMPPANIC(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_TOG_IRQ_TEMPPANIC_SHIFT)) & PMU_MISC1_TOG_IRQ_TEMPPANIC_MASK) +#define PMU_MISC1_TOG_IRQ_TEMPLOW_MASK (0x10000000U) +#define PMU_MISC1_TOG_IRQ_TEMPLOW_SHIFT (28U) +#define PMU_MISC1_TOG_IRQ_TEMPLOW(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_TOG_IRQ_TEMPLOW_SHIFT)) & PMU_MISC1_TOG_IRQ_TEMPLOW_MASK) +#define PMU_MISC1_TOG_IRQ_TEMPHIGH_MASK (0x20000000U) +#define PMU_MISC1_TOG_IRQ_TEMPHIGH_SHIFT (29U) +#define PMU_MISC1_TOG_IRQ_TEMPHIGH(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_TOG_IRQ_TEMPHIGH_SHIFT)) & PMU_MISC1_TOG_IRQ_TEMPHIGH_MASK) +#define PMU_MISC1_TOG_IRQ_ANA_BO_MASK (0x40000000U) +#define PMU_MISC1_TOG_IRQ_ANA_BO_SHIFT (30U) +#define PMU_MISC1_TOG_IRQ_ANA_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_TOG_IRQ_ANA_BO_SHIFT)) & PMU_MISC1_TOG_IRQ_ANA_BO_MASK) +#define PMU_MISC1_TOG_IRQ_DIG_BO_MASK (0x80000000U) +#define PMU_MISC1_TOG_IRQ_DIG_BO_SHIFT (31U) +#define PMU_MISC1_TOG_IRQ_DIG_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_TOG_IRQ_DIG_BO_SHIFT)) & PMU_MISC1_TOG_IRQ_DIG_BO_MASK) +/*! @} */ + +/*! @name MISC2 - Miscellaneous Control Register */ +/*! @{ */ +#define PMU_MISC2_REG0_BO_OFFSET_MASK (0x7U) +#define PMU_MISC2_REG0_BO_OFFSET_SHIFT (0U) +/*! REG0_BO_OFFSET + * 0b100..Brownout offset = 0.100V + * 0b111..Brownout offset = 0.175V + */ +#define PMU_MISC2_REG0_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_REG0_BO_OFFSET_SHIFT)) & PMU_MISC2_REG0_BO_OFFSET_MASK) +#define PMU_MISC2_REG0_BO_STATUS_MASK (0x8U) +#define PMU_MISC2_REG0_BO_STATUS_SHIFT (3U) +/*! REG0_BO_STATUS + * 0b1..Brownout, supply is below target minus brownout offset. + */ +#define PMU_MISC2_REG0_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_REG0_BO_STATUS_SHIFT)) & PMU_MISC2_REG0_BO_STATUS_MASK) +#define PMU_MISC2_REG0_ENABLE_BO_MASK (0x20U) +#define PMU_MISC2_REG0_ENABLE_BO_SHIFT (5U) +#define PMU_MISC2_REG0_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_REG0_ENABLE_BO_SHIFT)) & PMU_MISC2_REG0_ENABLE_BO_MASK) +#define PMU_MISC2_PLL3_disable_MASK (0x80U) +#define PMU_MISC2_PLL3_disable_SHIFT (7U) +#define PMU_MISC2_PLL3_disable(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_PLL3_disable_SHIFT)) & PMU_MISC2_PLL3_disable_MASK) +#define PMU_MISC2_REG1_BO_OFFSET_MASK (0x700U) +#define PMU_MISC2_REG1_BO_OFFSET_SHIFT (8U) +/*! REG1_BO_OFFSET + * 0b100..Brownout offset = 0.100V + * 0b111..Brownout offset = 0.175V + */ +#define PMU_MISC2_REG1_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_REG1_BO_OFFSET_SHIFT)) & PMU_MISC2_REG1_BO_OFFSET_MASK) +#define PMU_MISC2_REG1_BO_STATUS_MASK (0x800U) +#define PMU_MISC2_REG1_BO_STATUS_SHIFT (11U) +/*! REG1_BO_STATUS + * 0b1..Brownout, supply is below target minus brownout offset. + */ +#define PMU_MISC2_REG1_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_REG1_BO_STATUS_SHIFT)) & PMU_MISC2_REG1_BO_STATUS_MASK) +#define PMU_MISC2_REG1_ENABLE_BO_MASK (0x2000U) +#define PMU_MISC2_REG1_ENABLE_BO_SHIFT (13U) +#define PMU_MISC2_REG1_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_REG1_ENABLE_BO_SHIFT)) & PMU_MISC2_REG1_ENABLE_BO_MASK) +#define PMU_MISC2_AUDIO_DIV_LSB_MASK (0x8000U) +#define PMU_MISC2_AUDIO_DIV_LSB_SHIFT (15U) +/*! AUDIO_DIV_LSB + * 0b0..divide by 1 (Default) + * 0b1..divide by 2 + */ +#define PMU_MISC2_AUDIO_DIV_LSB(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_AUDIO_DIV_LSB_SHIFT)) & PMU_MISC2_AUDIO_DIV_LSB_MASK) +#define PMU_MISC2_REG2_BO_OFFSET_MASK (0x70000U) +#define PMU_MISC2_REG2_BO_OFFSET_SHIFT (16U) +/*! REG2_BO_OFFSET + * 0b100..Brownout offset = 0.100V + * 0b111..Brownout offset = 0.175V + */ +#define PMU_MISC2_REG2_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_REG2_BO_OFFSET_SHIFT)) & PMU_MISC2_REG2_BO_OFFSET_MASK) +#define PMU_MISC2_REG2_BO_STATUS_MASK (0x80000U) +#define PMU_MISC2_REG2_BO_STATUS_SHIFT (19U) +#define PMU_MISC2_REG2_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_REG2_BO_STATUS_SHIFT)) & PMU_MISC2_REG2_BO_STATUS_MASK) +#define PMU_MISC2_REG2_ENABLE_BO_MASK (0x200000U) +#define PMU_MISC2_REG2_ENABLE_BO_SHIFT (21U) +#define PMU_MISC2_REG2_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_REG2_ENABLE_BO_SHIFT)) & PMU_MISC2_REG2_ENABLE_BO_MASK) +#define PMU_MISC2_REG2_OK_MASK (0x400000U) +#define PMU_MISC2_REG2_OK_SHIFT (22U) +#define PMU_MISC2_REG2_OK(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_REG2_OK_SHIFT)) & PMU_MISC2_REG2_OK_MASK) +#define PMU_MISC2_AUDIO_DIV_MSB_MASK (0x800000U) +#define PMU_MISC2_AUDIO_DIV_MSB_SHIFT (23U) +/*! AUDIO_DIV_MSB + * 0b0..divide by 1 (Default) + * 0b1..divide by 2 + */ +#define PMU_MISC2_AUDIO_DIV_MSB(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_AUDIO_DIV_MSB_SHIFT)) & PMU_MISC2_AUDIO_DIV_MSB_MASK) +#define PMU_MISC2_REG0_STEP_TIME_MASK (0x3000000U) +#define PMU_MISC2_REG0_STEP_TIME_SHIFT (24U) +/*! REG0_STEP_TIME + * 0b00..64 + * 0b01..128 + * 0b10..256 + * 0b11..512 + */ +#define PMU_MISC2_REG0_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_REG0_STEP_TIME_SHIFT)) & PMU_MISC2_REG0_STEP_TIME_MASK) +#define PMU_MISC2_REG1_STEP_TIME_MASK (0xC000000U) +#define PMU_MISC2_REG1_STEP_TIME_SHIFT (26U) +/*! REG1_STEP_TIME + * 0b00..64 + * 0b01..128 + * 0b10..256 + * 0b11..512 + */ +#define PMU_MISC2_REG1_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_REG1_STEP_TIME_SHIFT)) & PMU_MISC2_REG1_STEP_TIME_MASK) +#define PMU_MISC2_REG2_STEP_TIME_MASK (0x30000000U) +#define PMU_MISC2_REG2_STEP_TIME_SHIFT (28U) +/*! REG2_STEP_TIME + * 0b00..64 + * 0b01..128 + * 0b10..256 + * 0b11..512 + */ +#define PMU_MISC2_REG2_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_REG2_STEP_TIME_SHIFT)) & PMU_MISC2_REG2_STEP_TIME_MASK) +#define PMU_MISC2_VIDEO_DIV_MASK (0xC0000000U) +#define PMU_MISC2_VIDEO_DIV_SHIFT (30U) +/*! VIDEO_DIV + * 0b00..divide by 1 (Default) + * 0b01..divide by 2 + * 0b10..divide by 1 + * 0b11..divide by 4 + */ +#define PMU_MISC2_VIDEO_DIV(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_VIDEO_DIV_SHIFT)) & PMU_MISC2_VIDEO_DIV_MASK) +/*! @} */ + +/*! @name MISC2_SET - Miscellaneous Control Register */ +/*! @{ */ +#define PMU_MISC2_SET_REG0_BO_OFFSET_MASK (0x7U) +#define PMU_MISC2_SET_REG0_BO_OFFSET_SHIFT (0U) +/*! REG0_BO_OFFSET + * 0b100..Brownout offset = 0.100V + * 0b111..Brownout offset = 0.175V + */ +#define PMU_MISC2_SET_REG0_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_SET_REG0_BO_OFFSET_SHIFT)) & PMU_MISC2_SET_REG0_BO_OFFSET_MASK) +#define PMU_MISC2_SET_REG0_BO_STATUS_MASK (0x8U) +#define PMU_MISC2_SET_REG0_BO_STATUS_SHIFT (3U) +/*! REG0_BO_STATUS + * 0b1..Brownout, supply is below target minus brownout offset. + */ +#define PMU_MISC2_SET_REG0_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_SET_REG0_BO_STATUS_SHIFT)) & PMU_MISC2_SET_REG0_BO_STATUS_MASK) +#define PMU_MISC2_SET_REG0_ENABLE_BO_MASK (0x20U) +#define PMU_MISC2_SET_REG0_ENABLE_BO_SHIFT (5U) +#define PMU_MISC2_SET_REG0_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_SET_REG0_ENABLE_BO_SHIFT)) & PMU_MISC2_SET_REG0_ENABLE_BO_MASK) +#define PMU_MISC2_SET_PLL3_disable_MASK (0x80U) +#define PMU_MISC2_SET_PLL3_disable_SHIFT (7U) +#define PMU_MISC2_SET_PLL3_disable(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_SET_PLL3_disable_SHIFT)) & PMU_MISC2_SET_PLL3_disable_MASK) +#define PMU_MISC2_SET_REG1_BO_OFFSET_MASK (0x700U) +#define PMU_MISC2_SET_REG1_BO_OFFSET_SHIFT (8U) +/*! REG1_BO_OFFSET + * 0b100..Brownout offset = 0.100V + * 0b111..Brownout offset = 0.175V + */ +#define PMU_MISC2_SET_REG1_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_SET_REG1_BO_OFFSET_SHIFT)) & PMU_MISC2_SET_REG1_BO_OFFSET_MASK) +#define PMU_MISC2_SET_REG1_BO_STATUS_MASK (0x800U) +#define PMU_MISC2_SET_REG1_BO_STATUS_SHIFT (11U) +/*! REG1_BO_STATUS + * 0b1..Brownout, supply is below target minus brownout offset. + */ +#define PMU_MISC2_SET_REG1_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_SET_REG1_BO_STATUS_SHIFT)) & PMU_MISC2_SET_REG1_BO_STATUS_MASK) +#define PMU_MISC2_SET_REG1_ENABLE_BO_MASK (0x2000U) +#define PMU_MISC2_SET_REG1_ENABLE_BO_SHIFT (13U) +#define PMU_MISC2_SET_REG1_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_SET_REG1_ENABLE_BO_SHIFT)) & PMU_MISC2_SET_REG1_ENABLE_BO_MASK) +#define PMU_MISC2_SET_AUDIO_DIV_LSB_MASK (0x8000U) +#define PMU_MISC2_SET_AUDIO_DIV_LSB_SHIFT (15U) +/*! AUDIO_DIV_LSB + * 0b0..divide by 1 (Default) + * 0b1..divide by 2 + */ +#define PMU_MISC2_SET_AUDIO_DIV_LSB(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_SET_AUDIO_DIV_LSB_SHIFT)) & PMU_MISC2_SET_AUDIO_DIV_LSB_MASK) +#define PMU_MISC2_SET_REG2_BO_OFFSET_MASK (0x70000U) +#define PMU_MISC2_SET_REG2_BO_OFFSET_SHIFT (16U) +/*! REG2_BO_OFFSET + * 0b100..Brownout offset = 0.100V + * 0b111..Brownout offset = 0.175V + */ +#define PMU_MISC2_SET_REG2_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_SET_REG2_BO_OFFSET_SHIFT)) & PMU_MISC2_SET_REG2_BO_OFFSET_MASK) +#define PMU_MISC2_SET_REG2_BO_STATUS_MASK (0x80000U) +#define PMU_MISC2_SET_REG2_BO_STATUS_SHIFT (19U) +#define PMU_MISC2_SET_REG2_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_SET_REG2_BO_STATUS_SHIFT)) & PMU_MISC2_SET_REG2_BO_STATUS_MASK) +#define PMU_MISC2_SET_REG2_ENABLE_BO_MASK (0x200000U) +#define PMU_MISC2_SET_REG2_ENABLE_BO_SHIFT (21U) +#define PMU_MISC2_SET_REG2_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_SET_REG2_ENABLE_BO_SHIFT)) & PMU_MISC2_SET_REG2_ENABLE_BO_MASK) +#define PMU_MISC2_SET_REG2_OK_MASK (0x400000U) +#define PMU_MISC2_SET_REG2_OK_SHIFT (22U) +#define PMU_MISC2_SET_REG2_OK(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_SET_REG2_OK_SHIFT)) & PMU_MISC2_SET_REG2_OK_MASK) +#define PMU_MISC2_SET_AUDIO_DIV_MSB_MASK (0x800000U) +#define PMU_MISC2_SET_AUDIO_DIV_MSB_SHIFT (23U) +/*! AUDIO_DIV_MSB + * 0b0..divide by 1 (Default) + * 0b1..divide by 2 + */ +#define PMU_MISC2_SET_AUDIO_DIV_MSB(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_SET_AUDIO_DIV_MSB_SHIFT)) & PMU_MISC2_SET_AUDIO_DIV_MSB_MASK) +#define PMU_MISC2_SET_REG0_STEP_TIME_MASK (0x3000000U) +#define PMU_MISC2_SET_REG0_STEP_TIME_SHIFT (24U) +/*! REG0_STEP_TIME + * 0b00..64 + * 0b01..128 + * 0b10..256 + * 0b11..512 + */ +#define PMU_MISC2_SET_REG0_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_SET_REG0_STEP_TIME_SHIFT)) & PMU_MISC2_SET_REG0_STEP_TIME_MASK) +#define PMU_MISC2_SET_REG1_STEP_TIME_MASK (0xC000000U) +#define PMU_MISC2_SET_REG1_STEP_TIME_SHIFT (26U) +/*! REG1_STEP_TIME + * 0b00..64 + * 0b01..128 + * 0b10..256 + * 0b11..512 + */ +#define PMU_MISC2_SET_REG1_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_SET_REG1_STEP_TIME_SHIFT)) & PMU_MISC2_SET_REG1_STEP_TIME_MASK) +#define PMU_MISC2_SET_REG2_STEP_TIME_MASK (0x30000000U) +#define PMU_MISC2_SET_REG2_STEP_TIME_SHIFT (28U) +/*! REG2_STEP_TIME + * 0b00..64 + * 0b01..128 + * 0b10..256 + * 0b11..512 + */ +#define PMU_MISC2_SET_REG2_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_SET_REG2_STEP_TIME_SHIFT)) & PMU_MISC2_SET_REG2_STEP_TIME_MASK) +#define PMU_MISC2_SET_VIDEO_DIV_MASK (0xC0000000U) +#define PMU_MISC2_SET_VIDEO_DIV_SHIFT (30U) +/*! VIDEO_DIV + * 0b00..divide by 1 (Default) + * 0b01..divide by 2 + * 0b10..divide by 1 + * 0b11..divide by 4 + */ +#define PMU_MISC2_SET_VIDEO_DIV(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_SET_VIDEO_DIV_SHIFT)) & PMU_MISC2_SET_VIDEO_DIV_MASK) +/*! @} */ + +/*! @name MISC2_CLR - Miscellaneous Control Register */ +/*! @{ */ +#define PMU_MISC2_CLR_REG0_BO_OFFSET_MASK (0x7U) +#define PMU_MISC2_CLR_REG0_BO_OFFSET_SHIFT (0U) +/*! REG0_BO_OFFSET + * 0b100..Brownout offset = 0.100V + * 0b111..Brownout offset = 0.175V + */ +#define PMU_MISC2_CLR_REG0_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_CLR_REG0_BO_OFFSET_SHIFT)) & PMU_MISC2_CLR_REG0_BO_OFFSET_MASK) +#define PMU_MISC2_CLR_REG0_BO_STATUS_MASK (0x8U) +#define PMU_MISC2_CLR_REG0_BO_STATUS_SHIFT (3U) +/*! REG0_BO_STATUS + * 0b1..Brownout, supply is below target minus brownout offset. + */ +#define PMU_MISC2_CLR_REG0_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_CLR_REG0_BO_STATUS_SHIFT)) & PMU_MISC2_CLR_REG0_BO_STATUS_MASK) +#define PMU_MISC2_CLR_REG0_ENABLE_BO_MASK (0x20U) +#define PMU_MISC2_CLR_REG0_ENABLE_BO_SHIFT (5U) +#define PMU_MISC2_CLR_REG0_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_CLR_REG0_ENABLE_BO_SHIFT)) & PMU_MISC2_CLR_REG0_ENABLE_BO_MASK) +#define PMU_MISC2_CLR_PLL3_disable_MASK (0x80U) +#define PMU_MISC2_CLR_PLL3_disable_SHIFT (7U) +#define PMU_MISC2_CLR_PLL3_disable(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_CLR_PLL3_disable_SHIFT)) & PMU_MISC2_CLR_PLL3_disable_MASK) +#define PMU_MISC2_CLR_REG1_BO_OFFSET_MASK (0x700U) +#define PMU_MISC2_CLR_REG1_BO_OFFSET_SHIFT (8U) +/*! REG1_BO_OFFSET + * 0b100..Brownout offset = 0.100V + * 0b111..Brownout offset = 0.175V + */ +#define PMU_MISC2_CLR_REG1_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_CLR_REG1_BO_OFFSET_SHIFT)) & PMU_MISC2_CLR_REG1_BO_OFFSET_MASK) +#define PMU_MISC2_CLR_REG1_BO_STATUS_MASK (0x800U) +#define PMU_MISC2_CLR_REG1_BO_STATUS_SHIFT (11U) +/*! REG1_BO_STATUS + * 0b1..Brownout, supply is below target minus brownout offset. + */ +#define PMU_MISC2_CLR_REG1_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_CLR_REG1_BO_STATUS_SHIFT)) & PMU_MISC2_CLR_REG1_BO_STATUS_MASK) +#define PMU_MISC2_CLR_REG1_ENABLE_BO_MASK (0x2000U) +#define PMU_MISC2_CLR_REG1_ENABLE_BO_SHIFT (13U) +#define PMU_MISC2_CLR_REG1_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_CLR_REG1_ENABLE_BO_SHIFT)) & PMU_MISC2_CLR_REG1_ENABLE_BO_MASK) +#define PMU_MISC2_CLR_AUDIO_DIV_LSB_MASK (0x8000U) +#define PMU_MISC2_CLR_AUDIO_DIV_LSB_SHIFT (15U) +/*! AUDIO_DIV_LSB + * 0b0..divide by 1 (Default) + * 0b1..divide by 2 + */ +#define PMU_MISC2_CLR_AUDIO_DIV_LSB(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_CLR_AUDIO_DIV_LSB_SHIFT)) & PMU_MISC2_CLR_AUDIO_DIV_LSB_MASK) +#define PMU_MISC2_CLR_REG2_BO_OFFSET_MASK (0x70000U) +#define PMU_MISC2_CLR_REG2_BO_OFFSET_SHIFT (16U) +/*! REG2_BO_OFFSET + * 0b100..Brownout offset = 0.100V + * 0b111..Brownout offset = 0.175V + */ +#define PMU_MISC2_CLR_REG2_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_CLR_REG2_BO_OFFSET_SHIFT)) & PMU_MISC2_CLR_REG2_BO_OFFSET_MASK) +#define PMU_MISC2_CLR_REG2_BO_STATUS_MASK (0x80000U) +#define PMU_MISC2_CLR_REG2_BO_STATUS_SHIFT (19U) +#define PMU_MISC2_CLR_REG2_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_CLR_REG2_BO_STATUS_SHIFT)) & PMU_MISC2_CLR_REG2_BO_STATUS_MASK) +#define PMU_MISC2_CLR_REG2_ENABLE_BO_MASK (0x200000U) +#define PMU_MISC2_CLR_REG2_ENABLE_BO_SHIFT (21U) +#define PMU_MISC2_CLR_REG2_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_CLR_REG2_ENABLE_BO_SHIFT)) & PMU_MISC2_CLR_REG2_ENABLE_BO_MASK) +#define PMU_MISC2_CLR_REG2_OK_MASK (0x400000U) +#define PMU_MISC2_CLR_REG2_OK_SHIFT (22U) +#define PMU_MISC2_CLR_REG2_OK(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_CLR_REG2_OK_SHIFT)) & PMU_MISC2_CLR_REG2_OK_MASK) +#define PMU_MISC2_CLR_AUDIO_DIV_MSB_MASK (0x800000U) +#define PMU_MISC2_CLR_AUDIO_DIV_MSB_SHIFT (23U) +/*! AUDIO_DIV_MSB + * 0b0..divide by 1 (Default) + * 0b1..divide by 2 + */ +#define PMU_MISC2_CLR_AUDIO_DIV_MSB(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_CLR_AUDIO_DIV_MSB_SHIFT)) & PMU_MISC2_CLR_AUDIO_DIV_MSB_MASK) +#define PMU_MISC2_CLR_REG0_STEP_TIME_MASK (0x3000000U) +#define PMU_MISC2_CLR_REG0_STEP_TIME_SHIFT (24U) +/*! REG0_STEP_TIME + * 0b00..64 + * 0b01..128 + * 0b10..256 + * 0b11..512 + */ +#define PMU_MISC2_CLR_REG0_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_CLR_REG0_STEP_TIME_SHIFT)) & PMU_MISC2_CLR_REG0_STEP_TIME_MASK) +#define PMU_MISC2_CLR_REG1_STEP_TIME_MASK (0xC000000U) +#define PMU_MISC2_CLR_REG1_STEP_TIME_SHIFT (26U) +/*! REG1_STEP_TIME + * 0b00..64 + * 0b01..128 + * 0b10..256 + * 0b11..512 + */ +#define PMU_MISC2_CLR_REG1_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_CLR_REG1_STEP_TIME_SHIFT)) & PMU_MISC2_CLR_REG1_STEP_TIME_MASK) +#define PMU_MISC2_CLR_REG2_STEP_TIME_MASK (0x30000000U) +#define PMU_MISC2_CLR_REG2_STEP_TIME_SHIFT (28U) +/*! REG2_STEP_TIME + * 0b00..64 + * 0b01..128 + * 0b10..256 + * 0b11..512 + */ +#define PMU_MISC2_CLR_REG2_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_CLR_REG2_STEP_TIME_SHIFT)) & PMU_MISC2_CLR_REG2_STEP_TIME_MASK) +#define PMU_MISC2_CLR_VIDEO_DIV_MASK (0xC0000000U) +#define PMU_MISC2_CLR_VIDEO_DIV_SHIFT (30U) +/*! VIDEO_DIV + * 0b00..divide by 1 (Default) + * 0b01..divide by 2 + * 0b10..divide by 1 + * 0b11..divide by 4 + */ +#define PMU_MISC2_CLR_VIDEO_DIV(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_CLR_VIDEO_DIV_SHIFT)) & PMU_MISC2_CLR_VIDEO_DIV_MASK) +/*! @} */ + +/*! @name MISC2_TOG - Miscellaneous Control Register */ +/*! @{ */ +#define PMU_MISC2_TOG_REG0_BO_OFFSET_MASK (0x7U) +#define PMU_MISC2_TOG_REG0_BO_OFFSET_SHIFT (0U) +/*! REG0_BO_OFFSET + * 0b100..Brownout offset = 0.100V + * 0b111..Brownout offset = 0.175V + */ +#define PMU_MISC2_TOG_REG0_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_TOG_REG0_BO_OFFSET_SHIFT)) & PMU_MISC2_TOG_REG0_BO_OFFSET_MASK) +#define PMU_MISC2_TOG_REG0_BO_STATUS_MASK (0x8U) +#define PMU_MISC2_TOG_REG0_BO_STATUS_SHIFT (3U) +/*! REG0_BO_STATUS + * 0b1..Brownout, supply is below target minus brownout offset. + */ +#define PMU_MISC2_TOG_REG0_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_TOG_REG0_BO_STATUS_SHIFT)) & PMU_MISC2_TOG_REG0_BO_STATUS_MASK) +#define PMU_MISC2_TOG_REG0_ENABLE_BO_MASK (0x20U) +#define PMU_MISC2_TOG_REG0_ENABLE_BO_SHIFT (5U) +#define PMU_MISC2_TOG_REG0_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_TOG_REG0_ENABLE_BO_SHIFT)) & PMU_MISC2_TOG_REG0_ENABLE_BO_MASK) +#define PMU_MISC2_TOG_PLL3_disable_MASK (0x80U) +#define PMU_MISC2_TOG_PLL3_disable_SHIFT (7U) +#define PMU_MISC2_TOG_PLL3_disable(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_TOG_PLL3_disable_SHIFT)) & PMU_MISC2_TOG_PLL3_disable_MASK) +#define PMU_MISC2_TOG_REG1_BO_OFFSET_MASK (0x700U) +#define PMU_MISC2_TOG_REG1_BO_OFFSET_SHIFT (8U) +/*! REG1_BO_OFFSET + * 0b100..Brownout offset = 0.100V + * 0b111..Brownout offset = 0.175V + */ +#define PMU_MISC2_TOG_REG1_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_TOG_REG1_BO_OFFSET_SHIFT)) & PMU_MISC2_TOG_REG1_BO_OFFSET_MASK) +#define PMU_MISC2_TOG_REG1_BO_STATUS_MASK (0x800U) +#define PMU_MISC2_TOG_REG1_BO_STATUS_SHIFT (11U) +/*! REG1_BO_STATUS + * 0b1..Brownout, supply is below target minus brownout offset. + */ +#define PMU_MISC2_TOG_REG1_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_TOG_REG1_BO_STATUS_SHIFT)) & PMU_MISC2_TOG_REG1_BO_STATUS_MASK) +#define PMU_MISC2_TOG_REG1_ENABLE_BO_MASK (0x2000U) +#define PMU_MISC2_TOG_REG1_ENABLE_BO_SHIFT (13U) +#define PMU_MISC2_TOG_REG1_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_TOG_REG1_ENABLE_BO_SHIFT)) & PMU_MISC2_TOG_REG1_ENABLE_BO_MASK) +#define PMU_MISC2_TOG_AUDIO_DIV_LSB_MASK (0x8000U) +#define PMU_MISC2_TOG_AUDIO_DIV_LSB_SHIFT (15U) +/*! AUDIO_DIV_LSB + * 0b0..divide by 1 (Default) + * 0b1..divide by 2 + */ +#define PMU_MISC2_TOG_AUDIO_DIV_LSB(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_TOG_AUDIO_DIV_LSB_SHIFT)) & PMU_MISC2_TOG_AUDIO_DIV_LSB_MASK) +#define PMU_MISC2_TOG_REG2_BO_OFFSET_MASK (0x70000U) +#define PMU_MISC2_TOG_REG2_BO_OFFSET_SHIFT (16U) +/*! REG2_BO_OFFSET + * 0b100..Brownout offset = 0.100V + * 0b111..Brownout offset = 0.175V + */ +#define PMU_MISC2_TOG_REG2_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_TOG_REG2_BO_OFFSET_SHIFT)) & PMU_MISC2_TOG_REG2_BO_OFFSET_MASK) +#define PMU_MISC2_TOG_REG2_BO_STATUS_MASK (0x80000U) +#define PMU_MISC2_TOG_REG2_BO_STATUS_SHIFT (19U) +#define PMU_MISC2_TOG_REG2_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_TOG_REG2_BO_STATUS_SHIFT)) & PMU_MISC2_TOG_REG2_BO_STATUS_MASK) +#define PMU_MISC2_TOG_REG2_ENABLE_BO_MASK (0x200000U) +#define PMU_MISC2_TOG_REG2_ENABLE_BO_SHIFT (21U) +#define PMU_MISC2_TOG_REG2_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_TOG_REG2_ENABLE_BO_SHIFT)) & PMU_MISC2_TOG_REG2_ENABLE_BO_MASK) +#define PMU_MISC2_TOG_REG2_OK_MASK (0x400000U) +#define PMU_MISC2_TOG_REG2_OK_SHIFT (22U) +#define PMU_MISC2_TOG_REG2_OK(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_TOG_REG2_OK_SHIFT)) & PMU_MISC2_TOG_REG2_OK_MASK) +#define PMU_MISC2_TOG_AUDIO_DIV_MSB_MASK (0x800000U) +#define PMU_MISC2_TOG_AUDIO_DIV_MSB_SHIFT (23U) +/*! AUDIO_DIV_MSB + * 0b0..divide by 1 (Default) + * 0b1..divide by 2 + */ +#define PMU_MISC2_TOG_AUDIO_DIV_MSB(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_TOG_AUDIO_DIV_MSB_SHIFT)) & PMU_MISC2_TOG_AUDIO_DIV_MSB_MASK) +#define PMU_MISC2_TOG_REG0_STEP_TIME_MASK (0x3000000U) +#define PMU_MISC2_TOG_REG0_STEP_TIME_SHIFT (24U) +/*! REG0_STEP_TIME + * 0b00..64 + * 0b01..128 + * 0b10..256 + * 0b11..512 + */ +#define PMU_MISC2_TOG_REG0_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_TOG_REG0_STEP_TIME_SHIFT)) & PMU_MISC2_TOG_REG0_STEP_TIME_MASK) +#define PMU_MISC2_TOG_REG1_STEP_TIME_MASK (0xC000000U) +#define PMU_MISC2_TOG_REG1_STEP_TIME_SHIFT (26U) +/*! REG1_STEP_TIME + * 0b00..64 + * 0b01..128 + * 0b10..256 + * 0b11..512 + */ +#define PMU_MISC2_TOG_REG1_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_TOG_REG1_STEP_TIME_SHIFT)) & PMU_MISC2_TOG_REG1_STEP_TIME_MASK) +#define PMU_MISC2_TOG_REG2_STEP_TIME_MASK (0x30000000U) +#define PMU_MISC2_TOG_REG2_STEP_TIME_SHIFT (28U) +/*! REG2_STEP_TIME + * 0b00..64 + * 0b01..128 + * 0b10..256 + * 0b11..512 + */ +#define PMU_MISC2_TOG_REG2_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_TOG_REG2_STEP_TIME_SHIFT)) & PMU_MISC2_TOG_REG2_STEP_TIME_MASK) +#define PMU_MISC2_TOG_VIDEO_DIV_MASK (0xC0000000U) +#define PMU_MISC2_TOG_VIDEO_DIV_SHIFT (30U) +/*! VIDEO_DIV + * 0b00..divide by 1 (Default) + * 0b01..divide by 2 + * 0b10..divide by 1 + * 0b11..divide by 4 + */ +#define PMU_MISC2_TOG_VIDEO_DIV(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_TOG_VIDEO_DIV_SHIFT)) & PMU_MISC2_TOG_VIDEO_DIV_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group PMU_Register_Masks */ + + +/* PMU - Peripheral instance base addresses */ +/** Peripheral PMU base address */ +#define PMU_BASE (0x400D8000u) +/** Peripheral PMU base pointer */ +#define PMU ((PMU_Type *)PMU_BASE) +/** Array initializer of PMU peripheral base addresses */ +#define PMU_BASE_ADDRS { PMU_BASE } +/** Array initializer of PMU peripheral base pointers */ +#define PMU_BASE_PTRS { PMU } + +/*! + * @} + */ /* end of group PMU_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- PWM Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup PWM_Peripheral_Access_Layer PWM Peripheral Access Layer + * @{ + */ + +/** PWM - Register Layout Typedef */ +typedef struct { + struct { /* offset: 0x0, array step: 0x60 */ + __I uint16_t CNT; /**< Counter Register, array offset: 0x0, array step: 0x60 */ + __IO uint16_t INIT; /**< Initial Count Register, array offset: 0x2, array step: 0x60 */ + __IO uint16_t CTRL2; /**< Control 2 Register, array offset: 0x4, array step: 0x60 */ + __IO uint16_t CTRL; /**< Control Register, array offset: 0x6, array step: 0x60 */ + uint8_t RESERVED_0[2]; + __IO uint16_t VAL0; /**< Value Register 0, array offset: 0xA, array step: 0x60 */ + __IO uint16_t FRACVAL1; /**< Fractional Value Register 1, array offset: 0xC, array step: 0x60 */ + __IO uint16_t VAL1; /**< Value Register 1, array offset: 0xE, array step: 0x60 */ + __IO uint16_t FRACVAL2; /**< Fractional Value Register 2, array offset: 0x10, array step: 0x60 */ + __IO uint16_t VAL2; /**< Value Register 2, array offset: 0x12, array step: 0x60 */ + __IO uint16_t FRACVAL3; /**< Fractional Value Register 3, array offset: 0x14, array step: 0x60 */ + __IO uint16_t VAL3; /**< Value Register 3, array offset: 0x16, array step: 0x60 */ + __IO uint16_t FRACVAL4; /**< Fractional Value Register 4, array offset: 0x18, array step: 0x60 */ + __IO uint16_t VAL4; /**< Value Register 4, array offset: 0x1A, array step: 0x60 */ + __IO uint16_t FRACVAL5; /**< Fractional Value Register 5, array offset: 0x1C, array step: 0x60 */ + __IO uint16_t VAL5; /**< Value Register 5, array offset: 0x1E, array step: 0x60 */ + __IO uint16_t FRCTRL; /**< Fractional Control Register, array offset: 0x20, array step: 0x60 */ + __IO uint16_t OCTRL; /**< Output Control Register, array offset: 0x22, array step: 0x60 */ + __IO uint16_t STS; /**< Status Register, array offset: 0x24, array step: 0x60 */ + __IO uint16_t INTEN; /**< Interrupt Enable Register, array offset: 0x26, array step: 0x60 */ + __IO uint16_t DMAEN; /**< DMA Enable Register, array offset: 0x28, array step: 0x60 */ + __IO uint16_t TCTRL; /**< Output Trigger Control Register, array offset: 0x2A, array step: 0x60 */ + __IO uint16_t DISMAP[2]; /**< Fault Disable Mapping Register 0..Fault Disable Mapping Register 1, array offset: 0x2C, array step: index*0x60, index2*0x2 */ + __IO uint16_t DTCNT0; /**< Deadtime Count Register 0, array offset: 0x30, array step: 0x60 */ + __IO uint16_t DTCNT1; /**< Deadtime Count Register 1, array offset: 0x32, array step: 0x60 */ + __IO uint16_t CAPTCTRLA; /**< Capture Control A Register, array offset: 0x34, array step: 0x60 */ + __IO uint16_t CAPTCOMPA; /**< Capture Compare A Register, array offset: 0x36, array step: 0x60 */ + __IO uint16_t CAPTCTRLB; /**< Capture Control B Register, array offset: 0x38, array step: 0x60 */ + __IO uint16_t CAPTCOMPB; /**< Capture Compare B Register, array offset: 0x3A, array step: 0x60 */ + __IO uint16_t CAPTCTRLX; /**< Capture Control X Register, array offset: 0x3C, array step: 0x60 */ + __IO uint16_t CAPTCOMPX; /**< Capture Compare X Register, array offset: 0x3E, array step: 0x60 */ + __I uint16_t CVAL0; /**< Capture Value 0 Register, array offset: 0x40, array step: 0x60 */ + __I uint16_t CVAL0CYC; /**< Capture Value 0 Cycle Register, array offset: 0x42, array step: 0x60 */ + __I uint16_t CVAL1; /**< Capture Value 1 Register, array offset: 0x44, array step: 0x60 */ + __I uint16_t CVAL1CYC; /**< Capture Value 1 Cycle Register, array offset: 0x46, array step: 0x60 */ + __I uint16_t CVAL2; /**< Capture Value 2 Register, array offset: 0x48, array step: 0x60 */ + __I uint16_t CVAL2CYC; /**< Capture Value 2 Cycle Register, array offset: 0x4A, array step: 0x60 */ + __I uint16_t CVAL3; /**< Capture Value 3 Register, array offset: 0x4C, array step: 0x60 */ + __I uint16_t CVAL3CYC; /**< Capture Value 3 Cycle Register, array offset: 0x4E, array step: 0x60 */ + __I uint16_t CVAL4; /**< Capture Value 4 Register, array offset: 0x50, array step: 0x60 */ + __I uint16_t CVAL4CYC; /**< Capture Value 4 Cycle Register, array offset: 0x52, array step: 0x60 */ + __I uint16_t CVAL5; /**< Capture Value 5 Register, array offset: 0x54, array step: 0x60 */ + __I uint16_t CVAL5CYC; /**< Capture Value 5 Cycle Register, array offset: 0x56, array step: 0x60 */ + uint8_t RESERVED_1[8]; + } SM[4]; + __IO uint16_t OUTEN; /**< Output Enable Register, offset: 0x180 */ + __IO uint16_t MASK; /**< Mask Register, offset: 0x182 */ + __IO uint16_t SWCOUT; /**< Software Controlled Output Register, offset: 0x184 */ + __IO uint16_t DTSRCSEL; /**< PWM Source Select Register, offset: 0x186 */ + __IO uint16_t MCTRL; /**< Master Control Register, offset: 0x188 */ + __IO uint16_t MCTRL2; /**< Master Control 2 Register, offset: 0x18A */ + __IO uint16_t FCTRL; /**< Fault Control Register, offset: 0x18C */ + __IO uint16_t FSTS; /**< Fault Status Register, offset: 0x18E */ + __IO uint16_t FFILT; /**< Fault Filter Register, offset: 0x190 */ + __IO uint16_t FTST; /**< Fault Test Register, offset: 0x192 */ + __IO uint16_t FCTRL2; /**< Fault Control 2 Register, offset: 0x194 */ +} PWM_Type; + +/* ---------------------------------------------------------------------------- + -- PWM Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup PWM_Register_Masks PWM Register Masks + * @{ + */ + +/*! @name CNT - Counter Register */ +/*! @{ */ +#define PWM_CNT_CNT_MASK (0xFFFFU) +#define PWM_CNT_CNT_SHIFT (0U) +#define PWM_CNT_CNT(x) (((uint16_t)(((uint16_t)(x)) << PWM_CNT_CNT_SHIFT)) & PWM_CNT_CNT_MASK) +/*! @} */ + +/* The count of PWM_CNT */ +#define PWM_CNT_COUNT (4U) + +/*! @name INIT - Initial Count Register */ +/*! @{ */ +#define PWM_INIT_INIT_MASK (0xFFFFU) +#define PWM_INIT_INIT_SHIFT (0U) +#define PWM_INIT_INIT(x) (((uint16_t)(((uint16_t)(x)) << PWM_INIT_INIT_SHIFT)) & PWM_INIT_INIT_MASK) +/*! @} */ + +/* The count of PWM_INIT */ +#define PWM_INIT_COUNT (4U) + +/*! @name CTRL2 - Control 2 Register */ +/*! @{ */ +#define PWM_CTRL2_CLK_SEL_MASK (0x3U) +#define PWM_CTRL2_CLK_SEL_SHIFT (0U) +/*! CLK_SEL - Clock Source Select + * 0b00..The IPBus clock is used as the clock for the local prescaler and counter. + * 0b01..EXT_CLK is used as the clock for the local prescaler and counter. + * 0b10..Submodule 0's clock (AUX_CLK) is used as the source clock for the local prescaler and counter. This setting should not be used in submodule 0 as it will force the clock to logic 0. + * 0b11..reserved + */ +#define PWM_CTRL2_CLK_SEL(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_CLK_SEL_SHIFT)) & PWM_CTRL2_CLK_SEL_MASK) +#define PWM_CTRL2_RELOAD_SEL_MASK (0x4U) +#define PWM_CTRL2_RELOAD_SEL_SHIFT (2U) +/*! RELOAD_SEL - Reload Source Select + * 0b0..The local RELOAD signal is used to reload registers. + * 0b1..The master RELOAD signal (from submodule 0) is used to reload registers. This setting should not be used in submodule 0 as it will force the RELOAD signal to logic 0. + */ +#define PWM_CTRL2_RELOAD_SEL(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_RELOAD_SEL_SHIFT)) & PWM_CTRL2_RELOAD_SEL_MASK) +#define PWM_CTRL2_FORCE_SEL_MASK (0x38U) +#define PWM_CTRL2_FORCE_SEL_SHIFT (3U) +/*! FORCE_SEL - This read/write bit determines the source of the FORCE OUTPUT signal for this submodule. + * 0b000..The local force signal, CTRL2[FORCE], from this submodule is used to force updates. + * 0b001..The master force signal from submodule 0 is used to force updates. This setting should not be used in submodule 0 as it will hold the FORCE OUTPUT signal to logic 0. + * 0b010..The local reload signal from this submodule is used to force updates without regard to the state of LDOK. + * 0b011..The master reload signal from submodule0 is used to force updates if LDOK is set. This setting should not be used in submodule0 as it will hold the FORCE OUTPUT signal to logic 0. + * 0b100..The local sync signal from this submodule is used to force updates. + * 0b101..The master sync signal from submodule0 is used to force updates. This setting should not be used in submodule0 as it will hold the FORCE OUTPUT signal to logic 0. + * 0b110..The external force signal, EXT_FORCE, from outside the PWM module causes updates. + * 0b111..The external sync signal, EXT_SYNC, from outside the PWM module causes updates. + */ +#define PWM_CTRL2_FORCE_SEL(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_FORCE_SEL_SHIFT)) & PWM_CTRL2_FORCE_SEL_MASK) +#define PWM_CTRL2_FORCE_MASK (0x40U) +#define PWM_CTRL2_FORCE_SHIFT (6U) +#define PWM_CTRL2_FORCE(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_FORCE_SHIFT)) & PWM_CTRL2_FORCE_MASK) +#define PWM_CTRL2_FRCEN_MASK (0x80U) +#define PWM_CTRL2_FRCEN_SHIFT (7U) +/*! FRCEN - FRCEN + * 0b0..Initialization from a FORCE_OUT is disabled. + * 0b1..Initialization from a FORCE_OUT is enabled. + */ +#define PWM_CTRL2_FRCEN(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_FRCEN_SHIFT)) & PWM_CTRL2_FRCEN_MASK) +#define PWM_CTRL2_INIT_SEL_MASK (0x300U) +#define PWM_CTRL2_INIT_SEL_SHIFT (8U) +/*! INIT_SEL - Initialization Control Select + * 0b00..Local sync (PWM_X) causes initialization. + * 0b01..Master reload from submodule 0 causes initialization. This setting should not be used in submodule 0 as it will force the INIT signal to logic 0. The submodule counter will only reinitialize when a master reload occurs. + * 0b10..Master sync from submodule 0 causes initialization. This setting should not be used in submodule 0 as it will force the INIT signal to logic 0. + * 0b11..EXT_SYNC causes initialization. + */ +#define PWM_CTRL2_INIT_SEL(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_INIT_SEL_SHIFT)) & PWM_CTRL2_INIT_SEL_MASK) +#define PWM_CTRL2_PWMX_INIT_MASK (0x400U) +#define PWM_CTRL2_PWMX_INIT_SHIFT (10U) +#define PWM_CTRL2_PWMX_INIT(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_PWMX_INIT_SHIFT)) & PWM_CTRL2_PWMX_INIT_MASK) +#define PWM_CTRL2_PWM45_INIT_MASK (0x800U) +#define PWM_CTRL2_PWM45_INIT_SHIFT (11U) +#define PWM_CTRL2_PWM45_INIT(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_PWM45_INIT_SHIFT)) & PWM_CTRL2_PWM45_INIT_MASK) +#define PWM_CTRL2_PWM23_INIT_MASK (0x1000U) +#define PWM_CTRL2_PWM23_INIT_SHIFT (12U) +#define PWM_CTRL2_PWM23_INIT(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_PWM23_INIT_SHIFT)) & PWM_CTRL2_PWM23_INIT_MASK) +#define PWM_CTRL2_INDEP_MASK (0x2000U) +#define PWM_CTRL2_INDEP_SHIFT (13U) +/*! INDEP - Independent or Complementary Pair Operation + * 0b0..PWM_A and PWM_B form a complementary PWM pair. + * 0b1..PWM_A and PWM_B outputs are independent PWMs. + */ +#define PWM_CTRL2_INDEP(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_INDEP_SHIFT)) & PWM_CTRL2_INDEP_MASK) +#define PWM_CTRL2_WAITEN_MASK (0x4000U) +#define PWM_CTRL2_WAITEN_SHIFT (14U) +#define PWM_CTRL2_WAITEN(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_WAITEN_SHIFT)) & PWM_CTRL2_WAITEN_MASK) +#define PWM_CTRL2_DBGEN_MASK (0x8000U) +#define PWM_CTRL2_DBGEN_SHIFT (15U) +#define PWM_CTRL2_DBGEN(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_DBGEN_SHIFT)) & PWM_CTRL2_DBGEN_MASK) +/*! @} */ + +/* The count of PWM_CTRL2 */ +#define PWM_CTRL2_COUNT (4U) + +/*! @name CTRL - Control Register */ +/*! @{ */ +#define PWM_CTRL_DBLEN_MASK (0x1U) +#define PWM_CTRL_DBLEN_SHIFT (0U) +/*! DBLEN - Double Switching Enable + * 0b0..Double switching disabled. + * 0b1..Double switching enabled. + */ +#define PWM_CTRL_DBLEN(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL_DBLEN_SHIFT)) & PWM_CTRL_DBLEN_MASK) +#define PWM_CTRL_DBLX_MASK (0x2U) +#define PWM_CTRL_DBLX_SHIFT (1U) +/*! DBLX - PWMX Double Switching Enable + * 0b0..PWMX double pulse disabled. + * 0b1..PWMX double pulse enabled. + */ +#define PWM_CTRL_DBLX(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL_DBLX_SHIFT)) & PWM_CTRL_DBLX_MASK) +#define PWM_CTRL_LDMOD_MASK (0x4U) +#define PWM_CTRL_LDMOD_SHIFT (2U) +/*! LDMOD - Load Mode Select + * 0b0..Buffered registers of this submodule are loaded and take effect at the next PWM reload if MCTRL[LDOK] is set. + * 0b1..Buffered registers of this submodule are loaded and take effect immediately upon MCTRL[LDOK] being set. In this case it is not necessary to set CTRL[FULL] or CTRL[HALF]. + */ +#define PWM_CTRL_LDMOD(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL_LDMOD_SHIFT)) & PWM_CTRL_LDMOD_MASK) +#define PWM_CTRL_SPLIT_MASK (0x8U) +#define PWM_CTRL_SPLIT_SHIFT (3U) +/*! SPLIT - Split the DBLPWM signal to PWMA and PWMB + * 0b0..DBLPWM is not split. PWMA and PWMB each have double pulses. + * 0b1..DBLPWM is split to PWMA and PWMB. + */ +#define PWM_CTRL_SPLIT(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL_SPLIT_SHIFT)) & PWM_CTRL_SPLIT_MASK) +#define PWM_CTRL_PRSC_MASK (0x70U) +#define PWM_CTRL_PRSC_SHIFT (4U) +/*! PRSC - Prescaler + * 0b000..PWM clock frequency = fclk + * 0b001..PWM clock frequency = fclk/2 + * 0b010..PWM clock frequency = fclk/4 + * 0b011..PWM clock frequency = fclk/8 + * 0b100..PWM clock frequency = fclk/16 + * 0b101..PWM clock frequency = fclk/32 + * 0b110..PWM clock frequency = fclk/64 + * 0b111..PWM clock frequency = fclk/128 + */ +#define PWM_CTRL_PRSC(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL_PRSC_SHIFT)) & PWM_CTRL_PRSC_MASK) +#define PWM_CTRL_COMPMODE_MASK (0x80U) +#define PWM_CTRL_COMPMODE_SHIFT (7U) +/*! COMPMODE - Compare Mode + * 0b0..The VAL* registers and the PWM counter are compared using an "equal to" method. This means that PWM edges are only produced when the counter is equal to one of the VAL* register values. This implies that a PWMA output that is high at the end of a period will maintain this state until a match with VAL3 clears the output in the following period. + * 0b1..The VAL* registers and the PWM counter are compared using an "equal to or greater than" method. This means that PWM edges are produced when the counter is equal to or greater than one of the VAL* register values. This implies that a PWMA output that is high at the end of a period could go low at the start of the next period if the starting counter value is greater than (but not necessarily equal to) the new VAL3 value. + */ +#define PWM_CTRL_COMPMODE(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL_COMPMODE_SHIFT)) & PWM_CTRL_COMPMODE_MASK) +#define PWM_CTRL_DT_MASK (0x300U) +#define PWM_CTRL_DT_SHIFT (8U) +#define PWM_CTRL_DT(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL_DT_SHIFT)) & PWM_CTRL_DT_MASK) +#define PWM_CTRL_FULL_MASK (0x400U) +#define PWM_CTRL_FULL_SHIFT (10U) +/*! FULL - Full Cycle Reload + * 0b0..Full-cycle reloads disabled. + * 0b1..Full-cycle reloads enabled. + */ +#define PWM_CTRL_FULL(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL_FULL_SHIFT)) & PWM_CTRL_FULL_MASK) +#define PWM_CTRL_HALF_MASK (0x800U) +#define PWM_CTRL_HALF_SHIFT (11U) +/*! HALF - Half Cycle Reload + * 0b0..Half-cycle reloads disabled. + * 0b1..Half-cycle reloads enabled. + */ +#define PWM_CTRL_HALF(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL_HALF_SHIFT)) & PWM_CTRL_HALF_MASK) +#define PWM_CTRL_LDFQ_MASK (0xF000U) +#define PWM_CTRL_LDFQ_SHIFT (12U) +/*! LDFQ - Load Frequency + * 0b0000..Every PWM opportunity + * 0b0001..Every 2 PWM opportunities + * 0b0010..Every 3 PWM opportunities + * 0b0011..Every 4 PWM opportunities + * 0b0100..Every 5 PWM opportunities + * 0b0101..Every 6 PWM opportunities + * 0b0110..Every 7 PWM opportunities + * 0b0111..Every 8 PWM opportunities + * 0b1000..Every 9 PWM opportunities + * 0b1001..Every 10 PWM opportunities + * 0b1010..Every 11 PWM opportunities + * 0b1011..Every 12 PWM opportunities + * 0b1100..Every 13 PWM opportunities + * 0b1101..Every 14 PWM opportunities + * 0b1110..Every 15 PWM opportunities + * 0b1111..Every 16 PWM opportunities + */ +#define PWM_CTRL_LDFQ(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL_LDFQ_SHIFT)) & PWM_CTRL_LDFQ_MASK) +/*! @} */ + +/* The count of PWM_CTRL */ +#define PWM_CTRL_COUNT (4U) + +/*! @name VAL0 - Value Register 0 */ +/*! @{ */ +#define PWM_VAL0_VAL0_MASK (0xFFFFU) +#define PWM_VAL0_VAL0_SHIFT (0U) +#define PWM_VAL0_VAL0(x) (((uint16_t)(((uint16_t)(x)) << PWM_VAL0_VAL0_SHIFT)) & PWM_VAL0_VAL0_MASK) +/*! @} */ + +/* The count of PWM_VAL0 */ +#define PWM_VAL0_COUNT (4U) + +/*! @name FRACVAL1 - Fractional Value Register 1 */ +/*! @{ */ +#define PWM_FRACVAL1_FRACVAL1_MASK (0xF800U) +#define PWM_FRACVAL1_FRACVAL1_SHIFT (11U) +#define PWM_FRACVAL1_FRACVAL1(x) (((uint16_t)(((uint16_t)(x)) << PWM_FRACVAL1_FRACVAL1_SHIFT)) & PWM_FRACVAL1_FRACVAL1_MASK) +/*! @} */ + +/* The count of PWM_FRACVAL1 */ +#define PWM_FRACVAL1_COUNT (4U) + +/*! @name VAL1 - Value Register 1 */ +/*! @{ */ +#define PWM_VAL1_VAL1_MASK (0xFFFFU) +#define PWM_VAL1_VAL1_SHIFT (0U) +#define PWM_VAL1_VAL1(x) (((uint16_t)(((uint16_t)(x)) << PWM_VAL1_VAL1_SHIFT)) & PWM_VAL1_VAL1_MASK) +/*! @} */ + +/* The count of PWM_VAL1 */ +#define PWM_VAL1_COUNT (4U) + +/*! @name FRACVAL2 - Fractional Value Register 2 */ +/*! @{ */ +#define PWM_FRACVAL2_FRACVAL2_MASK (0xF800U) +#define PWM_FRACVAL2_FRACVAL2_SHIFT (11U) +#define PWM_FRACVAL2_FRACVAL2(x) (((uint16_t)(((uint16_t)(x)) << PWM_FRACVAL2_FRACVAL2_SHIFT)) & PWM_FRACVAL2_FRACVAL2_MASK) +/*! @} */ + +/* The count of PWM_FRACVAL2 */ +#define PWM_FRACVAL2_COUNT (4U) + +/*! @name VAL2 - Value Register 2 */ +/*! @{ */ +#define PWM_VAL2_VAL2_MASK (0xFFFFU) +#define PWM_VAL2_VAL2_SHIFT (0U) +#define PWM_VAL2_VAL2(x) (((uint16_t)(((uint16_t)(x)) << PWM_VAL2_VAL2_SHIFT)) & PWM_VAL2_VAL2_MASK) +/*! @} */ + +/* The count of PWM_VAL2 */ +#define PWM_VAL2_COUNT (4U) + +/*! @name FRACVAL3 - Fractional Value Register 3 */ +/*! @{ */ +#define PWM_FRACVAL3_FRACVAL3_MASK (0xF800U) +#define PWM_FRACVAL3_FRACVAL3_SHIFT (11U) +#define PWM_FRACVAL3_FRACVAL3(x) (((uint16_t)(((uint16_t)(x)) << PWM_FRACVAL3_FRACVAL3_SHIFT)) & PWM_FRACVAL3_FRACVAL3_MASK) +/*! @} */ + +/* The count of PWM_FRACVAL3 */ +#define PWM_FRACVAL3_COUNT (4U) + +/*! @name VAL3 - Value Register 3 */ +/*! @{ */ +#define PWM_VAL3_VAL3_MASK (0xFFFFU) +#define PWM_VAL3_VAL3_SHIFT (0U) +#define PWM_VAL3_VAL3(x) (((uint16_t)(((uint16_t)(x)) << PWM_VAL3_VAL3_SHIFT)) & PWM_VAL3_VAL3_MASK) +/*! @} */ + +/* The count of PWM_VAL3 */ +#define PWM_VAL3_COUNT (4U) + +/*! @name FRACVAL4 - Fractional Value Register 4 */ +/*! @{ */ +#define PWM_FRACVAL4_FRACVAL4_MASK (0xF800U) +#define PWM_FRACVAL4_FRACVAL4_SHIFT (11U) +#define PWM_FRACVAL4_FRACVAL4(x) (((uint16_t)(((uint16_t)(x)) << PWM_FRACVAL4_FRACVAL4_SHIFT)) & PWM_FRACVAL4_FRACVAL4_MASK) +/*! @} */ + +/* The count of PWM_FRACVAL4 */ +#define PWM_FRACVAL4_COUNT (4U) + +/*! @name VAL4 - Value Register 4 */ +/*! @{ */ +#define PWM_VAL4_VAL4_MASK (0xFFFFU) +#define PWM_VAL4_VAL4_SHIFT (0U) +#define PWM_VAL4_VAL4(x) (((uint16_t)(((uint16_t)(x)) << PWM_VAL4_VAL4_SHIFT)) & PWM_VAL4_VAL4_MASK) +/*! @} */ + +/* The count of PWM_VAL4 */ +#define PWM_VAL4_COUNT (4U) + +/*! @name FRACVAL5 - Fractional Value Register 5 */ +/*! @{ */ +#define PWM_FRACVAL5_FRACVAL5_MASK (0xF800U) +#define PWM_FRACVAL5_FRACVAL5_SHIFT (11U) +#define PWM_FRACVAL5_FRACVAL5(x) (((uint16_t)(((uint16_t)(x)) << PWM_FRACVAL5_FRACVAL5_SHIFT)) & PWM_FRACVAL5_FRACVAL5_MASK) +/*! @} */ + +/* The count of PWM_FRACVAL5 */ +#define PWM_FRACVAL5_COUNT (4U) + +/*! @name VAL5 - Value Register 5 */ +/*! @{ */ +#define PWM_VAL5_VAL5_MASK (0xFFFFU) +#define PWM_VAL5_VAL5_SHIFT (0U) +#define PWM_VAL5_VAL5(x) (((uint16_t)(((uint16_t)(x)) << PWM_VAL5_VAL5_SHIFT)) & PWM_VAL5_VAL5_MASK) +/*! @} */ + +/* The count of PWM_VAL5 */ +#define PWM_VAL5_COUNT (4U) + +/*! @name FRCTRL - Fractional Control Register */ +/*! @{ */ +#define PWM_FRCTRL_FRAC1_EN_MASK (0x2U) +#define PWM_FRCTRL_FRAC1_EN_SHIFT (1U) +/*! FRAC1_EN - Fractional Cycle PWM Period Enable + * 0b0..Disable fractional cycle length for the PWM period. + * 0b1..Enable fractional cycle length for the PWM period. + */ +#define PWM_FRCTRL_FRAC1_EN(x) (((uint16_t)(((uint16_t)(x)) << PWM_FRCTRL_FRAC1_EN_SHIFT)) & PWM_FRCTRL_FRAC1_EN_MASK) +#define PWM_FRCTRL_FRAC23_EN_MASK (0x4U) +#define PWM_FRCTRL_FRAC23_EN_SHIFT (2U) +/*! FRAC23_EN - Fractional Cycle Placement Enable for PWM_A + * 0b0..Disable fractional cycle placement for PWM_A. + * 0b1..Enable fractional cycle placement for PWM_A. + */ +#define PWM_FRCTRL_FRAC23_EN(x) (((uint16_t)(((uint16_t)(x)) << PWM_FRCTRL_FRAC23_EN_SHIFT)) & PWM_FRCTRL_FRAC23_EN_MASK) +#define PWM_FRCTRL_FRAC45_EN_MASK (0x10U) +#define PWM_FRCTRL_FRAC45_EN_SHIFT (4U) +/*! FRAC45_EN - Fractional Cycle Placement Enable for PWM_B + * 0b0..Disable fractional cycle placement for PWM_B. + * 0b1..Enable fractional cycle placement for PWM_B. + */ +#define PWM_FRCTRL_FRAC45_EN(x) (((uint16_t)(((uint16_t)(x)) << PWM_FRCTRL_FRAC45_EN_SHIFT)) & PWM_FRCTRL_FRAC45_EN_MASK) +#define PWM_FRCTRL_FRAC_PU_MASK (0x100U) +#define PWM_FRCTRL_FRAC_PU_SHIFT (8U) +/*! FRAC_PU - Fractional Delay Circuit Power Up + * 0b0..Turn off fractional delay logic. + * 0b1..Power up fractional delay logic. + */ +#define PWM_FRCTRL_FRAC_PU(x) (((uint16_t)(((uint16_t)(x)) << PWM_FRCTRL_FRAC_PU_SHIFT)) & PWM_FRCTRL_FRAC_PU_MASK) +#define PWM_FRCTRL_TEST_MASK (0x8000U) +#define PWM_FRCTRL_TEST_SHIFT (15U) +#define PWM_FRCTRL_TEST(x) (((uint16_t)(((uint16_t)(x)) << PWM_FRCTRL_TEST_SHIFT)) & PWM_FRCTRL_TEST_MASK) +/*! @} */ + +/* The count of PWM_FRCTRL */ +#define PWM_FRCTRL_COUNT (4U) + +/*! @name OCTRL - Output Control Register */ +/*! @{ */ +#define PWM_OCTRL_PWMXFS_MASK (0x3U) +#define PWM_OCTRL_PWMXFS_SHIFT (0U) +/*! PWMXFS - PWM_X Fault State + * 0b00..Output is forced to logic 0 state prior to consideration of output polarity control. + * 0b01..Output is forced to logic 1 state prior to consideration of output polarity control. + * 0b10..Output is tristated. + * 0b11..Output is tristated. + */ +#define PWM_OCTRL_PWMXFS(x) (((uint16_t)(((uint16_t)(x)) << PWM_OCTRL_PWMXFS_SHIFT)) & PWM_OCTRL_PWMXFS_MASK) +#define PWM_OCTRL_PWMBFS_MASK (0xCU) +#define PWM_OCTRL_PWMBFS_SHIFT (2U) +/*! PWMBFS - PWM_B Fault State + * 0b00..Output is forced to logic 0 state prior to consideration of output polarity control. + * 0b01..Output is forced to logic 1 state prior to consideration of output polarity control. + * 0b10..Output is tristated. + * 0b11..Output is tristated. + */ +#define PWM_OCTRL_PWMBFS(x) (((uint16_t)(((uint16_t)(x)) << PWM_OCTRL_PWMBFS_SHIFT)) & PWM_OCTRL_PWMBFS_MASK) +#define PWM_OCTRL_PWMAFS_MASK (0x30U) +#define PWM_OCTRL_PWMAFS_SHIFT (4U) +/*! PWMAFS - PWM_A Fault State + * 0b00..Output is forced to logic 0 state prior to consideration of output polarity control. + * 0b01..Output is forced to logic 1 state prior to consideration of output polarity control. + * 0b10..Output is tristated. + * 0b11..Output is tristated. + */ +#define PWM_OCTRL_PWMAFS(x) (((uint16_t)(((uint16_t)(x)) << PWM_OCTRL_PWMAFS_SHIFT)) & PWM_OCTRL_PWMAFS_MASK) +#define PWM_OCTRL_POLX_MASK (0x100U) +#define PWM_OCTRL_POLX_SHIFT (8U) +/*! POLX - PWM_X Output Polarity + * 0b0..PWM_X output not inverted. A high level on the PWM_X pin represents the "on" or "active" state. + * 0b1..PWM_X output inverted. A low level on the PWM_X pin represents the "on" or "active" state. + */ +#define PWM_OCTRL_POLX(x) (((uint16_t)(((uint16_t)(x)) << PWM_OCTRL_POLX_SHIFT)) & PWM_OCTRL_POLX_MASK) +#define PWM_OCTRL_POLB_MASK (0x200U) +#define PWM_OCTRL_POLB_SHIFT (9U) +/*! POLB - PWM_B Output Polarity + * 0b0..PWM_B output not inverted. A high level on the PWM_B pin represents the "on" or "active" state. + * 0b1..PWM_B output inverted. A low level on the PWM_B pin represents the "on" or "active" state. + */ +#define PWM_OCTRL_POLB(x) (((uint16_t)(((uint16_t)(x)) << PWM_OCTRL_POLB_SHIFT)) & PWM_OCTRL_POLB_MASK) +#define PWM_OCTRL_POLA_MASK (0x400U) +#define PWM_OCTRL_POLA_SHIFT (10U) +/*! POLA - PWM_A Output Polarity + * 0b0..PWM_A output not inverted. A high level on the PWM_A pin represents the "on" or "active" state. + * 0b1..PWM_A output inverted. A low level on the PWM_A pin represents the "on" or "active" state. + */ +#define PWM_OCTRL_POLA(x) (((uint16_t)(((uint16_t)(x)) << PWM_OCTRL_POLA_SHIFT)) & PWM_OCTRL_POLA_MASK) +#define PWM_OCTRL_PWMX_IN_MASK (0x2000U) +#define PWM_OCTRL_PWMX_IN_SHIFT (13U) +#define PWM_OCTRL_PWMX_IN(x) (((uint16_t)(((uint16_t)(x)) << PWM_OCTRL_PWMX_IN_SHIFT)) & PWM_OCTRL_PWMX_IN_MASK) +#define PWM_OCTRL_PWMB_IN_MASK (0x4000U) +#define PWM_OCTRL_PWMB_IN_SHIFT (14U) +#define PWM_OCTRL_PWMB_IN(x) (((uint16_t)(((uint16_t)(x)) << PWM_OCTRL_PWMB_IN_SHIFT)) & PWM_OCTRL_PWMB_IN_MASK) +#define PWM_OCTRL_PWMA_IN_MASK (0x8000U) +#define PWM_OCTRL_PWMA_IN_SHIFT (15U) +#define PWM_OCTRL_PWMA_IN(x) (((uint16_t)(((uint16_t)(x)) << PWM_OCTRL_PWMA_IN_SHIFT)) & PWM_OCTRL_PWMA_IN_MASK) +/*! @} */ + +/* The count of PWM_OCTRL */ +#define PWM_OCTRL_COUNT (4U) + +/*! @name STS - Status Register */ +/*! @{ */ +#define PWM_STS_CMPF_MASK (0x3FU) +#define PWM_STS_CMPF_SHIFT (0U) +/*! CMPF - Compare Flags + * 0b000000..No compare event has occurred for a particular VALx value. + * 0b000001..A compare event has occurred for a particular VALx value. + */ +#define PWM_STS_CMPF(x) (((uint16_t)(((uint16_t)(x)) << PWM_STS_CMPF_SHIFT)) & PWM_STS_CMPF_MASK) +#define PWM_STS_CFX0_MASK (0x40U) +#define PWM_STS_CFX0_SHIFT (6U) +#define PWM_STS_CFX0(x) (((uint16_t)(((uint16_t)(x)) << PWM_STS_CFX0_SHIFT)) & PWM_STS_CFX0_MASK) +#define PWM_STS_CFX1_MASK (0x80U) +#define PWM_STS_CFX1_SHIFT (7U) +#define PWM_STS_CFX1(x) (((uint16_t)(((uint16_t)(x)) << PWM_STS_CFX1_SHIFT)) & PWM_STS_CFX1_MASK) +#define PWM_STS_CFB0_MASK (0x100U) +#define PWM_STS_CFB0_SHIFT (8U) +#define PWM_STS_CFB0(x) (((uint16_t)(((uint16_t)(x)) << PWM_STS_CFB0_SHIFT)) & PWM_STS_CFB0_MASK) +#define PWM_STS_CFB1_MASK (0x200U) +#define PWM_STS_CFB1_SHIFT (9U) +#define PWM_STS_CFB1(x) (((uint16_t)(((uint16_t)(x)) << PWM_STS_CFB1_SHIFT)) & PWM_STS_CFB1_MASK) +#define PWM_STS_CFA0_MASK (0x400U) +#define PWM_STS_CFA0_SHIFT (10U) +#define PWM_STS_CFA0(x) (((uint16_t)(((uint16_t)(x)) << PWM_STS_CFA0_SHIFT)) & PWM_STS_CFA0_MASK) +#define PWM_STS_CFA1_MASK (0x800U) +#define PWM_STS_CFA1_SHIFT (11U) +#define PWM_STS_CFA1(x) (((uint16_t)(((uint16_t)(x)) << PWM_STS_CFA1_SHIFT)) & PWM_STS_CFA1_MASK) +#define PWM_STS_RF_MASK (0x1000U) +#define PWM_STS_RF_SHIFT (12U) +/*! RF - Reload Flag + * 0b0..No new reload cycle since last STS[RF] clearing + * 0b1..New reload cycle since last STS[RF] clearing + */ +#define PWM_STS_RF(x) (((uint16_t)(((uint16_t)(x)) << PWM_STS_RF_SHIFT)) & PWM_STS_RF_MASK) +#define PWM_STS_REF_MASK (0x2000U) +#define PWM_STS_REF_SHIFT (13U) +/*! REF - Reload Error Flag + * 0b0..No reload error occurred. + * 0b1..Reload signal occurred with non-coherent data and MCTRL[LDOK] = 0. + */ +#define PWM_STS_REF(x) (((uint16_t)(((uint16_t)(x)) << PWM_STS_REF_SHIFT)) & PWM_STS_REF_MASK) +#define PWM_STS_RUF_MASK (0x4000U) +#define PWM_STS_RUF_SHIFT (14U) +/*! RUF - Registers Updated Flag + * 0b0..No register update has occurred since last reload. + * 0b1..At least one of the double buffered registers has been updated since the last reload. + */ +#define PWM_STS_RUF(x) (((uint16_t)(((uint16_t)(x)) << PWM_STS_RUF_SHIFT)) & PWM_STS_RUF_MASK) +/*! @} */ + +/* The count of PWM_STS */ +#define PWM_STS_COUNT (4U) + +/*! @name INTEN - Interrupt Enable Register */ +/*! @{ */ +#define PWM_INTEN_CMPIE_MASK (0x3FU) +#define PWM_INTEN_CMPIE_SHIFT (0U) +/*! CMPIE - Compare Interrupt Enables + * 0b000000..The corresponding STS[CMPF] bit will not cause an interrupt request. + * 0b000001..The corresponding STS[CMPF] bit will cause an interrupt request. + */ +#define PWM_INTEN_CMPIE(x) (((uint16_t)(((uint16_t)(x)) << PWM_INTEN_CMPIE_SHIFT)) & PWM_INTEN_CMPIE_MASK) +#define PWM_INTEN_CX0IE_MASK (0x40U) +#define PWM_INTEN_CX0IE_SHIFT (6U) +/*! CX0IE - Capture X 0 Interrupt Enable + * 0b0..Interrupt request disabled for STS[CFX0]. + * 0b1..Interrupt request enabled for STS[CFX0]. + */ +#define PWM_INTEN_CX0IE(x) (((uint16_t)(((uint16_t)(x)) << PWM_INTEN_CX0IE_SHIFT)) & PWM_INTEN_CX0IE_MASK) +#define PWM_INTEN_CX1IE_MASK (0x80U) +#define PWM_INTEN_CX1IE_SHIFT (7U) +/*! CX1IE - Capture X 1 Interrupt Enable + * 0b0..Interrupt request disabled for STS[CFX1]. + * 0b1..Interrupt request enabled for STS[CFX1]. + */ +#define PWM_INTEN_CX1IE(x) (((uint16_t)(((uint16_t)(x)) << PWM_INTEN_CX1IE_SHIFT)) & PWM_INTEN_CX1IE_MASK) +#define PWM_INTEN_CB0IE_MASK (0x100U) +#define PWM_INTEN_CB0IE_SHIFT (8U) +/*! CB0IE - Capture B 0 Interrupt Enable + * 0b0..Interrupt request disabled for STS[CFB0]. + * 0b1..Interrupt request enabled for STS[CFB0]. + */ +#define PWM_INTEN_CB0IE(x) (((uint16_t)(((uint16_t)(x)) << PWM_INTEN_CB0IE_SHIFT)) & PWM_INTEN_CB0IE_MASK) +#define PWM_INTEN_CB1IE_MASK (0x200U) +#define PWM_INTEN_CB1IE_SHIFT (9U) +/*! CB1IE - Capture B 1 Interrupt Enable + * 0b0..Interrupt request disabled for STS[CFB1]. + * 0b1..Interrupt request enabled for STS[CFB1]. + */ +#define PWM_INTEN_CB1IE(x) (((uint16_t)(((uint16_t)(x)) << PWM_INTEN_CB1IE_SHIFT)) & PWM_INTEN_CB1IE_MASK) +#define PWM_INTEN_CA0IE_MASK (0x400U) +#define PWM_INTEN_CA0IE_SHIFT (10U) +/*! CA0IE - Capture A 0 Interrupt Enable + * 0b0..Interrupt request disabled for STS[CFA0]. + * 0b1..Interrupt request enabled for STS[CFA0]. + */ +#define PWM_INTEN_CA0IE(x) (((uint16_t)(((uint16_t)(x)) << PWM_INTEN_CA0IE_SHIFT)) & PWM_INTEN_CA0IE_MASK) +#define PWM_INTEN_CA1IE_MASK (0x800U) +#define PWM_INTEN_CA1IE_SHIFT (11U) +/*! CA1IE - Capture A 1 Interrupt Enable + * 0b0..Interrupt request disabled for STS[CFA1]. + * 0b1..Interrupt request enabled for STS[CFA1]. + */ +#define PWM_INTEN_CA1IE(x) (((uint16_t)(((uint16_t)(x)) << PWM_INTEN_CA1IE_SHIFT)) & PWM_INTEN_CA1IE_MASK) +#define PWM_INTEN_RIE_MASK (0x1000U) +#define PWM_INTEN_RIE_SHIFT (12U) +/*! RIE - Reload Interrupt Enable + * 0b0..STS[RF] CPU interrupt requests disabled + * 0b1..STS[RF] CPU interrupt requests enabled + */ +#define PWM_INTEN_RIE(x) (((uint16_t)(((uint16_t)(x)) << PWM_INTEN_RIE_SHIFT)) & PWM_INTEN_RIE_MASK) +#define PWM_INTEN_REIE_MASK (0x2000U) +#define PWM_INTEN_REIE_SHIFT (13U) +/*! REIE - Reload Error Interrupt Enable + * 0b0..STS[REF] CPU interrupt requests disabled + * 0b1..STS[REF] CPU interrupt requests enabled + */ +#define PWM_INTEN_REIE(x) (((uint16_t)(((uint16_t)(x)) << PWM_INTEN_REIE_SHIFT)) & PWM_INTEN_REIE_MASK) +/*! @} */ + +/* The count of PWM_INTEN */ +#define PWM_INTEN_COUNT (4U) + +/*! @name DMAEN - DMA Enable Register */ +/*! @{ */ +#define PWM_DMAEN_CX0DE_MASK (0x1U) +#define PWM_DMAEN_CX0DE_SHIFT (0U) +#define PWM_DMAEN_CX0DE(x) (((uint16_t)(((uint16_t)(x)) << PWM_DMAEN_CX0DE_SHIFT)) & PWM_DMAEN_CX0DE_MASK) +#define PWM_DMAEN_CX1DE_MASK (0x2U) +#define PWM_DMAEN_CX1DE_SHIFT (1U) +#define PWM_DMAEN_CX1DE(x) (((uint16_t)(((uint16_t)(x)) << PWM_DMAEN_CX1DE_SHIFT)) & PWM_DMAEN_CX1DE_MASK) +#define PWM_DMAEN_CB0DE_MASK (0x4U) +#define PWM_DMAEN_CB0DE_SHIFT (2U) +#define PWM_DMAEN_CB0DE(x) (((uint16_t)(((uint16_t)(x)) << PWM_DMAEN_CB0DE_SHIFT)) & PWM_DMAEN_CB0DE_MASK) +#define PWM_DMAEN_CB1DE_MASK (0x8U) +#define PWM_DMAEN_CB1DE_SHIFT (3U) +#define PWM_DMAEN_CB1DE(x) (((uint16_t)(((uint16_t)(x)) << PWM_DMAEN_CB1DE_SHIFT)) & PWM_DMAEN_CB1DE_MASK) +#define PWM_DMAEN_CA0DE_MASK (0x10U) +#define PWM_DMAEN_CA0DE_SHIFT (4U) +#define PWM_DMAEN_CA0DE(x) (((uint16_t)(((uint16_t)(x)) << PWM_DMAEN_CA0DE_SHIFT)) & PWM_DMAEN_CA0DE_MASK) +#define PWM_DMAEN_CA1DE_MASK (0x20U) +#define PWM_DMAEN_CA1DE_SHIFT (5U) +#define PWM_DMAEN_CA1DE(x) (((uint16_t)(((uint16_t)(x)) << PWM_DMAEN_CA1DE_SHIFT)) & PWM_DMAEN_CA1DE_MASK) +#define PWM_DMAEN_CAPTDE_MASK (0xC0U) +#define PWM_DMAEN_CAPTDE_SHIFT (6U) +/*! CAPTDE - Capture DMA Enable Source Select + * 0b00..Read DMA requests disabled. + * 0b01..Exceeding a FIFO watermark sets the DMA read request. This requires at least one of DMAEN[CA1DE], DMAEN[CA0DE], DMAEN[CB1DE], DMAEN[CB0DE], DMAEN[CX1DE], or DMAEN[CX0DE] to also be set in order to determine to which watermark(s) the DMA request is sensitive. + * 0b10..A local sync (VAL1 matches counter) sets the read DMA request. + * 0b11..A local reload (STS[RF] being set) sets the read DMA request. + */ +#define PWM_DMAEN_CAPTDE(x) (((uint16_t)(((uint16_t)(x)) << PWM_DMAEN_CAPTDE_SHIFT)) & PWM_DMAEN_CAPTDE_MASK) +#define PWM_DMAEN_FAND_MASK (0x100U) +#define PWM_DMAEN_FAND_SHIFT (8U) +/*! FAND - FIFO Watermark AND Control + * 0b0..Selected FIFO watermarks are OR'ed together. + * 0b1..Selected FIFO watermarks are AND'ed together. + */ +#define PWM_DMAEN_FAND(x) (((uint16_t)(((uint16_t)(x)) << PWM_DMAEN_FAND_SHIFT)) & PWM_DMAEN_FAND_MASK) +#define PWM_DMAEN_VALDE_MASK (0x200U) +#define PWM_DMAEN_VALDE_SHIFT (9U) +/*! VALDE - Value Registers DMA Enable + * 0b0..DMA write requests disabled + * 0b1..DMA write requests for the VALx and FRACVALx registers enabled + */ +#define PWM_DMAEN_VALDE(x) (((uint16_t)(((uint16_t)(x)) << PWM_DMAEN_VALDE_SHIFT)) & PWM_DMAEN_VALDE_MASK) +/*! @} */ + +/* The count of PWM_DMAEN */ +#define PWM_DMAEN_COUNT (4U) + +/*! @name TCTRL - Output Trigger Control Register */ +/*! @{ */ +#define PWM_TCTRL_OUT_TRIG_EN_MASK (0x3FU) +#define PWM_TCTRL_OUT_TRIG_EN_SHIFT (0U) +/*! OUT_TRIG_EN - Output Trigger Enables + * 0b000000..PWM_OUT_TRIGx will not set when the counter value matches the VALx value. + * 0b000001..PWM_OUT_TRIGx will set when the counter value matches the VALx value. + */ +#define PWM_TCTRL_OUT_TRIG_EN(x) (((uint16_t)(((uint16_t)(x)) << PWM_TCTRL_OUT_TRIG_EN_SHIFT)) & PWM_TCTRL_OUT_TRIG_EN_MASK) +#define PWM_TCTRL_TRGFRQ_MASK (0x1000U) +#define PWM_TCTRL_TRGFRQ_SHIFT (12U) +/*! TRGFRQ - Trigger frequency + * 0b0..Trigger outputs are generated during every PWM period even if the PWM is not reloaded every period due to CTRL[LDFQ] being non-zero. + * 0b1..Trigger outputs are generated only during the final PWM period prior to a reload opportunity when the PWM is not reloaded every period due to CTRL[LDFQ] being non-zero. + */ +#define PWM_TCTRL_TRGFRQ(x) (((uint16_t)(((uint16_t)(x)) << PWM_TCTRL_TRGFRQ_SHIFT)) & PWM_TCTRL_TRGFRQ_MASK) +#define PWM_TCTRL_PWBOT1_MASK (0x4000U) +#define PWM_TCTRL_PWBOT1_SHIFT (14U) +/*! PWBOT1 - Output Trigger 1 Source Select + * 0b0..Route the PWM_OUT_TRIG1 signal to PWM_OUT_TRIG1 port. + * 0b1..Route the PWMB output to the PWM_OUT_TRIG1 port. + */ +#define PWM_TCTRL_PWBOT1(x) (((uint16_t)(((uint16_t)(x)) << PWM_TCTRL_PWBOT1_SHIFT)) & PWM_TCTRL_PWBOT1_MASK) +#define PWM_TCTRL_PWAOT0_MASK (0x8000U) +#define PWM_TCTRL_PWAOT0_SHIFT (15U) +/*! PWAOT0 - Output Trigger 0 Source Select + * 0b0..Route the PWM_OUT_TRIG0 signal to PWM_OUT_TRIG0 port. + * 0b1..Route the PWMA output to the PWM_OUT_TRIG0 port. + */ +#define PWM_TCTRL_PWAOT0(x) (((uint16_t)(((uint16_t)(x)) << PWM_TCTRL_PWAOT0_SHIFT)) & PWM_TCTRL_PWAOT0_MASK) +/*! @} */ + +/* The count of PWM_TCTRL */ +#define PWM_TCTRL_COUNT (4U) + +/*! @name DISMAP - Fault Disable Mapping Register 0..Fault Disable Mapping Register 1 */ +/*! @{ */ +#define PWM_DISMAP_DIS0A_MASK (0xFU) +#define PWM_DISMAP_DIS0A_SHIFT (0U) +#define PWM_DISMAP_DIS0A(x) (((uint16_t)(((uint16_t)(x)) << PWM_DISMAP_DIS0A_SHIFT)) & PWM_DISMAP_DIS0A_MASK) +#define PWM_DISMAP_DIS1A_MASK (0xFU) +#define PWM_DISMAP_DIS1A_SHIFT (0U) +#define PWM_DISMAP_DIS1A(x) (((uint16_t)(((uint16_t)(x)) << PWM_DISMAP_DIS1A_SHIFT)) & PWM_DISMAP_DIS1A_MASK) +#define PWM_DISMAP_DIS0B_MASK (0xF0U) +#define PWM_DISMAP_DIS0B_SHIFT (4U) +#define PWM_DISMAP_DIS0B(x) (((uint16_t)(((uint16_t)(x)) << PWM_DISMAP_DIS0B_SHIFT)) & PWM_DISMAP_DIS0B_MASK) +#define PWM_DISMAP_DIS1B_MASK (0xF0U) +#define PWM_DISMAP_DIS1B_SHIFT (4U) +#define PWM_DISMAP_DIS1B(x) (((uint16_t)(((uint16_t)(x)) << PWM_DISMAP_DIS1B_SHIFT)) & PWM_DISMAP_DIS1B_MASK) +#define PWM_DISMAP_DIS0X_MASK (0xF00U) +#define PWM_DISMAP_DIS0X_SHIFT (8U) +#define PWM_DISMAP_DIS0X(x) (((uint16_t)(((uint16_t)(x)) << PWM_DISMAP_DIS0X_SHIFT)) & PWM_DISMAP_DIS0X_MASK) +#define PWM_DISMAP_DIS1X_MASK (0xF00U) +#define PWM_DISMAP_DIS1X_SHIFT (8U) +#define PWM_DISMAP_DIS1X(x) (((uint16_t)(((uint16_t)(x)) << PWM_DISMAP_DIS1X_SHIFT)) & PWM_DISMAP_DIS1X_MASK) +/*! @} */ + +/* The count of PWM_DISMAP */ +#define PWM_DISMAP_COUNT (4U) + +/* The count of PWM_DISMAP */ +#define PWM_DISMAP_COUNT2 (2U) + +/*! @name DTCNT0 - Deadtime Count Register 0 */ +/*! @{ */ +#define PWM_DTCNT0_DTCNT0_MASK (0xFFFFU) +#define PWM_DTCNT0_DTCNT0_SHIFT (0U) +#define PWM_DTCNT0_DTCNT0(x) (((uint16_t)(((uint16_t)(x)) << PWM_DTCNT0_DTCNT0_SHIFT)) & PWM_DTCNT0_DTCNT0_MASK) +/*! @} */ + +/* The count of PWM_DTCNT0 */ +#define PWM_DTCNT0_COUNT (4U) + +/*! @name DTCNT1 - Deadtime Count Register 1 */ +/*! @{ */ +#define PWM_DTCNT1_DTCNT1_MASK (0xFFFFU) +#define PWM_DTCNT1_DTCNT1_SHIFT (0U) +#define PWM_DTCNT1_DTCNT1(x) (((uint16_t)(((uint16_t)(x)) << PWM_DTCNT1_DTCNT1_SHIFT)) & PWM_DTCNT1_DTCNT1_MASK) +/*! @} */ + +/* The count of PWM_DTCNT1 */ +#define PWM_DTCNT1_COUNT (4U) + +/*! @name CAPTCTRLA - Capture Control A Register */ +/*! @{ */ +#define PWM_CAPTCTRLA_ARMA_MASK (0x1U) +#define PWM_CAPTCTRLA_ARMA_SHIFT (0U) +/*! ARMA - Arm A + * 0b0..Input capture operation is disabled. + * 0b1..Input capture operation as specified by CAPTCTRLA[EDGAx] is enabled. + */ +#define PWM_CAPTCTRLA_ARMA(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLA_ARMA_SHIFT)) & PWM_CAPTCTRLA_ARMA_MASK) +#define PWM_CAPTCTRLA_ONESHOTA_MASK (0x2U) +#define PWM_CAPTCTRLA_ONESHOTA_SHIFT (1U) +/*! ONESHOTA - One Shot Mode A + * 0b0..Free running mode is selected. If both capture circuits are enabled, then capture circuit 0 is armed first after CAPTCTRLA[ARMA] is set. Once a capture occurs, capture circuit 0 is disarmed and capture circuit 1 is armed. After capture circuit 1 performs a capture, it is disarmed and capture circuit 0 is re-armed. The process continues indefinitely.If only one of the capture circuits is enabled, then captures continue indefinitely on the enabled capture circuit. + * 0b1..One shot mode is selected. If both capture circuits are enabled, then capture circuit 0 is armed first after CAPTCTRLA[ARMA] is set. Once a capture occurs, capture circuit 0 is disarmed and capture circuit 1 is armed. After capture circuit 1 performs a capture, it is disarmed and CAPTCTRLA[ARMA] is cleared. No further captures will be performed until CAPTCTRLA[ARMA] is set again.If only one of the capture circuits is enabled, then a single capture will occur on the enabled capture circuit and CAPTCTRLA[ARMA] is then cleared. + */ +#define PWM_CAPTCTRLA_ONESHOTA(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLA_ONESHOTA_SHIFT)) & PWM_CAPTCTRLA_ONESHOTA_MASK) +#define PWM_CAPTCTRLA_EDGA0_MASK (0xCU) +#define PWM_CAPTCTRLA_EDGA0_SHIFT (2U) +/*! EDGA0 - Edge A 0 + * 0b00..Disabled + * 0b01..Capture falling edges + * 0b10..Capture rising edges + * 0b11..Capture any edge + */ +#define PWM_CAPTCTRLA_EDGA0(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLA_EDGA0_SHIFT)) & PWM_CAPTCTRLA_EDGA0_MASK) +#define PWM_CAPTCTRLA_EDGA1_MASK (0x30U) +#define PWM_CAPTCTRLA_EDGA1_SHIFT (4U) +/*! EDGA1 - Edge A 1 + * 0b00..Disabled + * 0b01..Capture falling edges + * 0b10..Capture rising edges + * 0b11..Capture any edge + */ +#define PWM_CAPTCTRLA_EDGA1(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLA_EDGA1_SHIFT)) & PWM_CAPTCTRLA_EDGA1_MASK) +#define PWM_CAPTCTRLA_INP_SELA_MASK (0x40U) +#define PWM_CAPTCTRLA_INP_SELA_SHIFT (6U) +/*! INP_SELA - Input Select A + * 0b0..Raw PWM_A input signal selected as source. + * 0b1..Output of edge counter/compare selected as source. Note that when this bitfield is set to 1, the internal edge counter is enabled and the rising and/or falling edges specified by the CAPTCTRLA[EDGA0] and CAPTCTRLA[EDGA1] fields are ignored. The software must still place a value other than 00 in either or both of the CAPTCTLRA[EDGA0] and/or CAPTCTRLA[EDGA1] fields in order to enable one or both of the capture registers. + */ +#define PWM_CAPTCTRLA_INP_SELA(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLA_INP_SELA_SHIFT)) & PWM_CAPTCTRLA_INP_SELA_MASK) +#define PWM_CAPTCTRLA_EDGCNTA_EN_MASK (0x80U) +#define PWM_CAPTCTRLA_EDGCNTA_EN_SHIFT (7U) +/*! EDGCNTA_EN - Edge Counter A Enable + * 0b0..Edge counter disabled and held in reset + * 0b1..Edge counter enabled + */ +#define PWM_CAPTCTRLA_EDGCNTA_EN(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLA_EDGCNTA_EN_SHIFT)) & PWM_CAPTCTRLA_EDGCNTA_EN_MASK) +#define PWM_CAPTCTRLA_CFAWM_MASK (0x300U) +#define PWM_CAPTCTRLA_CFAWM_SHIFT (8U) +#define PWM_CAPTCTRLA_CFAWM(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLA_CFAWM_SHIFT)) & PWM_CAPTCTRLA_CFAWM_MASK) +#define PWM_CAPTCTRLA_CA0CNT_MASK (0x1C00U) +#define PWM_CAPTCTRLA_CA0CNT_SHIFT (10U) +#define PWM_CAPTCTRLA_CA0CNT(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLA_CA0CNT_SHIFT)) & PWM_CAPTCTRLA_CA0CNT_MASK) +#define PWM_CAPTCTRLA_CA1CNT_MASK (0xE000U) +#define PWM_CAPTCTRLA_CA1CNT_SHIFT (13U) +#define PWM_CAPTCTRLA_CA1CNT(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLA_CA1CNT_SHIFT)) & PWM_CAPTCTRLA_CA1CNT_MASK) +/*! @} */ + +/* The count of PWM_CAPTCTRLA */ +#define PWM_CAPTCTRLA_COUNT (4U) + +/*! @name CAPTCOMPA - Capture Compare A Register */ +/*! @{ */ +#define PWM_CAPTCOMPA_EDGCMPA_MASK (0xFFU) +#define PWM_CAPTCOMPA_EDGCMPA_SHIFT (0U) +#define PWM_CAPTCOMPA_EDGCMPA(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCOMPA_EDGCMPA_SHIFT)) & PWM_CAPTCOMPA_EDGCMPA_MASK) +#define PWM_CAPTCOMPA_EDGCNTA_MASK (0xFF00U) +#define PWM_CAPTCOMPA_EDGCNTA_SHIFT (8U) +#define PWM_CAPTCOMPA_EDGCNTA(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCOMPA_EDGCNTA_SHIFT)) & PWM_CAPTCOMPA_EDGCNTA_MASK) +/*! @} */ + +/* The count of PWM_CAPTCOMPA */ +#define PWM_CAPTCOMPA_COUNT (4U) + +/*! @name CAPTCTRLB - Capture Control B Register */ +/*! @{ */ +#define PWM_CAPTCTRLB_ARMB_MASK (0x1U) +#define PWM_CAPTCTRLB_ARMB_SHIFT (0U) +/*! ARMB - Arm B + * 0b0..Input capture operation is disabled. + * 0b1..Input capture operation as specified by CAPTCTRLB[EDGBx] is enabled. + */ +#define PWM_CAPTCTRLB_ARMB(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLB_ARMB_SHIFT)) & PWM_CAPTCTRLB_ARMB_MASK) +#define PWM_CAPTCTRLB_ONESHOTB_MASK (0x2U) +#define PWM_CAPTCTRLB_ONESHOTB_SHIFT (1U) +/*! ONESHOTB - One Shot Mode B + * 0b0..Free running mode is selected. If both capture circuits are enabled, then capture circuit 0 is armed first after CAPTCTRLB[ARMB] is set. Once a capture occurs, capture circuit 0 is disarmed and capture circuit 1 is armed. After capture circuit 1 performs a capture, it is disarmed and capture circuit 0 is re-armed. The process continues indefinitely.If only one of the capture circuits is enabled, then captures continue indefinitely on the enabled capture circuit. + * 0b1..One shot mode is selected. If both capture circuits are enabled, then capture circuit 0 is armed first after CAPTCTRLB[ARMB] is set. Once a capture occurs, capture circuit 0 is disarmed and capture circuit 1 is armed. After capture circuit 1 performs a capture, it is disarmed and CAPTCTRLB[ARMB] is cleared. No further captures will be performed until CAPTCTRLB[ARMB] is set again.If only one of the capture circuits is enabled, then a single capture will occur on the enabled capture circuit and CAPTCTRLB[ARMB] is then cleared. + */ +#define PWM_CAPTCTRLB_ONESHOTB(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLB_ONESHOTB_SHIFT)) & PWM_CAPTCTRLB_ONESHOTB_MASK) +#define PWM_CAPTCTRLB_EDGB0_MASK (0xCU) +#define PWM_CAPTCTRLB_EDGB0_SHIFT (2U) +/*! EDGB0 - Edge B 0 + * 0b00..Disabled + * 0b01..Capture falling edges + * 0b10..Capture rising edges + * 0b11..Capture any edge + */ +#define PWM_CAPTCTRLB_EDGB0(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLB_EDGB0_SHIFT)) & PWM_CAPTCTRLB_EDGB0_MASK) +#define PWM_CAPTCTRLB_EDGB1_MASK (0x30U) +#define PWM_CAPTCTRLB_EDGB1_SHIFT (4U) +/*! EDGB1 - Edge B 1 + * 0b00..Disabled + * 0b01..Capture falling edges + * 0b10..Capture rising edges + * 0b11..Capture any edge + */ +#define PWM_CAPTCTRLB_EDGB1(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLB_EDGB1_SHIFT)) & PWM_CAPTCTRLB_EDGB1_MASK) +#define PWM_CAPTCTRLB_INP_SELB_MASK (0x40U) +#define PWM_CAPTCTRLB_INP_SELB_SHIFT (6U) +/*! INP_SELB - Input Select B + * 0b0..Raw PWM_B input signal selected as source. + * 0b1..Output of edge counter/compare selected as source. Note that when this bitfield is set to 1, the internal edge counter is enabled and the rising and/or falling edges specified by the CAPTCTRLB[EDGB0] and CAPTCTRLB[EDGB1] fields are ignored. The software must still place a value other than 00 in either or both of the CAPTCTLRB[EDGB0] and/or CAPTCTRLB[EDGB1] fields in order to enable one or both of the capture registers. + */ +#define PWM_CAPTCTRLB_INP_SELB(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLB_INP_SELB_SHIFT)) & PWM_CAPTCTRLB_INP_SELB_MASK) +#define PWM_CAPTCTRLB_EDGCNTB_EN_MASK (0x80U) +#define PWM_CAPTCTRLB_EDGCNTB_EN_SHIFT (7U) +/*! EDGCNTB_EN - Edge Counter B Enable + * 0b0..Edge counter disabled and held in reset + * 0b1..Edge counter enabled + */ +#define PWM_CAPTCTRLB_EDGCNTB_EN(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLB_EDGCNTB_EN_SHIFT)) & PWM_CAPTCTRLB_EDGCNTB_EN_MASK) +#define PWM_CAPTCTRLB_CFBWM_MASK (0x300U) +#define PWM_CAPTCTRLB_CFBWM_SHIFT (8U) +#define PWM_CAPTCTRLB_CFBWM(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLB_CFBWM_SHIFT)) & PWM_CAPTCTRLB_CFBWM_MASK) +#define PWM_CAPTCTRLB_CB0CNT_MASK (0x1C00U) +#define PWM_CAPTCTRLB_CB0CNT_SHIFT (10U) +#define PWM_CAPTCTRLB_CB0CNT(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLB_CB0CNT_SHIFT)) & PWM_CAPTCTRLB_CB0CNT_MASK) +#define PWM_CAPTCTRLB_CB1CNT_MASK (0xE000U) +#define PWM_CAPTCTRLB_CB1CNT_SHIFT (13U) +#define PWM_CAPTCTRLB_CB1CNT(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLB_CB1CNT_SHIFT)) & PWM_CAPTCTRLB_CB1CNT_MASK) +/*! @} */ + +/* The count of PWM_CAPTCTRLB */ +#define PWM_CAPTCTRLB_COUNT (4U) + +/*! @name CAPTCOMPB - Capture Compare B Register */ +/*! @{ */ +#define PWM_CAPTCOMPB_EDGCMPB_MASK (0xFFU) +#define PWM_CAPTCOMPB_EDGCMPB_SHIFT (0U) +#define PWM_CAPTCOMPB_EDGCMPB(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCOMPB_EDGCMPB_SHIFT)) & PWM_CAPTCOMPB_EDGCMPB_MASK) +#define PWM_CAPTCOMPB_EDGCNTB_MASK (0xFF00U) +#define PWM_CAPTCOMPB_EDGCNTB_SHIFT (8U) +#define PWM_CAPTCOMPB_EDGCNTB(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCOMPB_EDGCNTB_SHIFT)) & PWM_CAPTCOMPB_EDGCNTB_MASK) +/*! @} */ + +/* The count of PWM_CAPTCOMPB */ +#define PWM_CAPTCOMPB_COUNT (4U) + +/*! @name CAPTCTRLX - Capture Control X Register */ +/*! @{ */ +#define PWM_CAPTCTRLX_ARMX_MASK (0x1U) +#define PWM_CAPTCTRLX_ARMX_SHIFT (0U) +/*! ARMX - Arm X + * 0b0..Input capture operation is disabled. + * 0b1..Input capture operation as specified by CAPTCTRLX[EDGXx] is enabled. + */ +#define PWM_CAPTCTRLX_ARMX(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLX_ARMX_SHIFT)) & PWM_CAPTCTRLX_ARMX_MASK) +#define PWM_CAPTCTRLX_ONESHOTX_MASK (0x2U) +#define PWM_CAPTCTRLX_ONESHOTX_SHIFT (1U) +/*! ONESHOTX - One Shot Mode Aux + * 0b0..Free running mode is selected. If both capture circuits are enabled, then capture circuit 0 is armed first after the ARMX bit is set. Once a capture occurs, capture circuit 0 is disarmed and capture circuit 1 is armed. After capture circuit 1 performs a capture, it is disarmed and capture circuit 0 is re-armed. The process continues indefinitely.If only one of the capture circuits is enabled, then captures continue indefinitely on the enabled capture circuit. + * 0b1..One shot mode is selected. If both capture circuits are enabled, then capture circuit 0 is armed first after the ARMX bit is set. Once a capture occurs, capture circuit 0 is disarmed and capture circuit 1 is armed. After capture circuit 1 performs a capture, it is disarmed and the ARMX bit is cleared. No further captures will be performed until the ARMX bit is set again.If only one of the capture circuits is enabled, then a single capture will occur on the enabled capture circuit and the ARMX bit is then cleared. + */ +#define PWM_CAPTCTRLX_ONESHOTX(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLX_ONESHOTX_SHIFT)) & PWM_CAPTCTRLX_ONESHOTX_MASK) +#define PWM_CAPTCTRLX_EDGX0_MASK (0xCU) +#define PWM_CAPTCTRLX_EDGX0_SHIFT (2U) +/*! EDGX0 - Edge X 0 + * 0b00..Disabled + * 0b01..Capture falling edges + * 0b10..Capture rising edges + * 0b11..Capture any edge + */ +#define PWM_CAPTCTRLX_EDGX0(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLX_EDGX0_SHIFT)) & PWM_CAPTCTRLX_EDGX0_MASK) +#define PWM_CAPTCTRLX_EDGX1_MASK (0x30U) +#define PWM_CAPTCTRLX_EDGX1_SHIFT (4U) +/*! EDGX1 - Edge X 1 + * 0b00..Disabled + * 0b01..Capture falling edges + * 0b10..Capture rising edges + * 0b11..Capture any edge + */ +#define PWM_CAPTCTRLX_EDGX1(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLX_EDGX1_SHIFT)) & PWM_CAPTCTRLX_EDGX1_MASK) +#define PWM_CAPTCTRLX_INP_SELX_MASK (0x40U) +#define PWM_CAPTCTRLX_INP_SELX_SHIFT (6U) +/*! INP_SELX - Input Select X + * 0b0..Raw PWM_X input signal selected as source. + * 0b1..Output of edge counter/compare selected as source. Note that when this bitfield is set to 1, the internal edge counter is enabled and the rising and/or falling edges specified by the CAPTCTRLX[EDGX0] and CAPTCTRLX[EDGX1] fields are ignored. The software must still place a value other than 00 in either or both of the CAPTCTLRX[EDGX0] and/or CAPTCTRLX[EDGX1] fields in order to enable one or both of the capture registers. + */ +#define PWM_CAPTCTRLX_INP_SELX(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLX_INP_SELX_SHIFT)) & PWM_CAPTCTRLX_INP_SELX_MASK) +#define PWM_CAPTCTRLX_EDGCNTX_EN_MASK (0x80U) +#define PWM_CAPTCTRLX_EDGCNTX_EN_SHIFT (7U) +/*! EDGCNTX_EN - Edge Counter X Enable + * 0b0..Edge counter disabled and held in reset + * 0b1..Edge counter enabled + */ +#define PWM_CAPTCTRLX_EDGCNTX_EN(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLX_EDGCNTX_EN_SHIFT)) & PWM_CAPTCTRLX_EDGCNTX_EN_MASK) +#define PWM_CAPTCTRLX_CFXWM_MASK (0x300U) +#define PWM_CAPTCTRLX_CFXWM_SHIFT (8U) +#define PWM_CAPTCTRLX_CFXWM(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLX_CFXWM_SHIFT)) & PWM_CAPTCTRLX_CFXWM_MASK) +#define PWM_CAPTCTRLX_CX0CNT_MASK (0x1C00U) +#define PWM_CAPTCTRLX_CX0CNT_SHIFT (10U) +#define PWM_CAPTCTRLX_CX0CNT(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLX_CX0CNT_SHIFT)) & PWM_CAPTCTRLX_CX0CNT_MASK) +#define PWM_CAPTCTRLX_CX1CNT_MASK (0xE000U) +#define PWM_CAPTCTRLX_CX1CNT_SHIFT (13U) +#define PWM_CAPTCTRLX_CX1CNT(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLX_CX1CNT_SHIFT)) & PWM_CAPTCTRLX_CX1CNT_MASK) +/*! @} */ + +/* The count of PWM_CAPTCTRLX */ +#define PWM_CAPTCTRLX_COUNT (4U) + +/*! @name CAPTCOMPX - Capture Compare X Register */ +/*! @{ */ +#define PWM_CAPTCOMPX_EDGCMPX_MASK (0xFFU) +#define PWM_CAPTCOMPX_EDGCMPX_SHIFT (0U) +#define PWM_CAPTCOMPX_EDGCMPX(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCOMPX_EDGCMPX_SHIFT)) & PWM_CAPTCOMPX_EDGCMPX_MASK) +#define PWM_CAPTCOMPX_EDGCNTX_MASK (0xFF00U) +#define PWM_CAPTCOMPX_EDGCNTX_SHIFT (8U) +#define PWM_CAPTCOMPX_EDGCNTX(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCOMPX_EDGCNTX_SHIFT)) & PWM_CAPTCOMPX_EDGCNTX_MASK) +/*! @} */ + +/* The count of PWM_CAPTCOMPX */ +#define PWM_CAPTCOMPX_COUNT (4U) + +/*! @name CVAL0 - Capture Value 0 Register */ +/*! @{ */ +#define PWM_CVAL0_CAPTVAL0_MASK (0xFFFFU) +#define PWM_CVAL0_CAPTVAL0_SHIFT (0U) +#define PWM_CVAL0_CAPTVAL0(x) (((uint16_t)(((uint16_t)(x)) << PWM_CVAL0_CAPTVAL0_SHIFT)) & PWM_CVAL0_CAPTVAL0_MASK) +/*! @} */ + +/* The count of PWM_CVAL0 */ +#define PWM_CVAL0_COUNT (4U) + +/*! @name CVAL0CYC - Capture Value 0 Cycle Register */ +/*! @{ */ +#define PWM_CVAL0CYC_CVAL0CYC_MASK (0xFU) +#define PWM_CVAL0CYC_CVAL0CYC_SHIFT (0U) +#define PWM_CVAL0CYC_CVAL0CYC(x) (((uint16_t)(((uint16_t)(x)) << PWM_CVAL0CYC_CVAL0CYC_SHIFT)) & PWM_CVAL0CYC_CVAL0CYC_MASK) +/*! @} */ + +/* The count of PWM_CVAL0CYC */ +#define PWM_CVAL0CYC_COUNT (4U) + +/*! @name CVAL1 - Capture Value 1 Register */ +/*! @{ */ +#define PWM_CVAL1_CAPTVAL1_MASK (0xFFFFU) +#define PWM_CVAL1_CAPTVAL1_SHIFT (0U) +#define PWM_CVAL1_CAPTVAL1(x) (((uint16_t)(((uint16_t)(x)) << PWM_CVAL1_CAPTVAL1_SHIFT)) & PWM_CVAL1_CAPTVAL1_MASK) +/*! @} */ + +/* The count of PWM_CVAL1 */ +#define PWM_CVAL1_COUNT (4U) + +/*! @name CVAL1CYC - Capture Value 1 Cycle Register */ +/*! @{ */ +#define PWM_CVAL1CYC_CVAL1CYC_MASK (0xFU) +#define PWM_CVAL1CYC_CVAL1CYC_SHIFT (0U) +#define PWM_CVAL1CYC_CVAL1CYC(x) (((uint16_t)(((uint16_t)(x)) << PWM_CVAL1CYC_CVAL1CYC_SHIFT)) & PWM_CVAL1CYC_CVAL1CYC_MASK) +/*! @} */ + +/* The count of PWM_CVAL1CYC */ +#define PWM_CVAL1CYC_COUNT (4U) + +/*! @name CVAL2 - Capture Value 2 Register */ +/*! @{ */ +#define PWM_CVAL2_CAPTVAL2_MASK (0xFFFFU) +#define PWM_CVAL2_CAPTVAL2_SHIFT (0U) +#define PWM_CVAL2_CAPTVAL2(x) (((uint16_t)(((uint16_t)(x)) << PWM_CVAL2_CAPTVAL2_SHIFT)) & PWM_CVAL2_CAPTVAL2_MASK) +/*! @} */ + +/* The count of PWM_CVAL2 */ +#define PWM_CVAL2_COUNT (4U) + +/*! @name CVAL2CYC - Capture Value 2 Cycle Register */ +/*! @{ */ +#define PWM_CVAL2CYC_CVAL2CYC_MASK (0xFU) +#define PWM_CVAL2CYC_CVAL2CYC_SHIFT (0U) +#define PWM_CVAL2CYC_CVAL2CYC(x) (((uint16_t)(((uint16_t)(x)) << PWM_CVAL2CYC_CVAL2CYC_SHIFT)) & PWM_CVAL2CYC_CVAL2CYC_MASK) +/*! @} */ + +/* The count of PWM_CVAL2CYC */ +#define PWM_CVAL2CYC_COUNT (4U) + +/*! @name CVAL3 - Capture Value 3 Register */ +/*! @{ */ +#define PWM_CVAL3_CAPTVAL3_MASK (0xFFFFU) +#define PWM_CVAL3_CAPTVAL3_SHIFT (0U) +#define PWM_CVAL3_CAPTVAL3(x) (((uint16_t)(((uint16_t)(x)) << PWM_CVAL3_CAPTVAL3_SHIFT)) & PWM_CVAL3_CAPTVAL3_MASK) +/*! @} */ + +/* The count of PWM_CVAL3 */ +#define PWM_CVAL3_COUNT (4U) + +/*! @name CVAL3CYC - Capture Value 3 Cycle Register */ +/*! @{ */ +#define PWM_CVAL3CYC_CVAL3CYC_MASK (0xFU) +#define PWM_CVAL3CYC_CVAL3CYC_SHIFT (0U) +#define PWM_CVAL3CYC_CVAL3CYC(x) (((uint16_t)(((uint16_t)(x)) << PWM_CVAL3CYC_CVAL3CYC_SHIFT)) & PWM_CVAL3CYC_CVAL3CYC_MASK) +/*! @} */ + +/* The count of PWM_CVAL3CYC */ +#define PWM_CVAL3CYC_COUNT (4U) + +/*! @name CVAL4 - Capture Value 4 Register */ +/*! @{ */ +#define PWM_CVAL4_CAPTVAL4_MASK (0xFFFFU) +#define PWM_CVAL4_CAPTVAL4_SHIFT (0U) +#define PWM_CVAL4_CAPTVAL4(x) (((uint16_t)(((uint16_t)(x)) << PWM_CVAL4_CAPTVAL4_SHIFT)) & PWM_CVAL4_CAPTVAL4_MASK) +/*! @} */ + +/* The count of PWM_CVAL4 */ +#define PWM_CVAL4_COUNT (4U) + +/*! @name CVAL4CYC - Capture Value 4 Cycle Register */ +/*! @{ */ +#define PWM_CVAL4CYC_CVAL4CYC_MASK (0xFU) +#define PWM_CVAL4CYC_CVAL4CYC_SHIFT (0U) +#define PWM_CVAL4CYC_CVAL4CYC(x) (((uint16_t)(((uint16_t)(x)) << PWM_CVAL4CYC_CVAL4CYC_SHIFT)) & PWM_CVAL4CYC_CVAL4CYC_MASK) +/*! @} */ + +/* The count of PWM_CVAL4CYC */ +#define PWM_CVAL4CYC_COUNT (4U) + +/*! @name CVAL5 - Capture Value 5 Register */ +/*! @{ */ +#define PWM_CVAL5_CAPTVAL5_MASK (0xFFFFU) +#define PWM_CVAL5_CAPTVAL5_SHIFT (0U) +#define PWM_CVAL5_CAPTVAL5(x) (((uint16_t)(((uint16_t)(x)) << PWM_CVAL5_CAPTVAL5_SHIFT)) & PWM_CVAL5_CAPTVAL5_MASK) +/*! @} */ + +/* The count of PWM_CVAL5 */ +#define PWM_CVAL5_COUNT (4U) + +/*! @name CVAL5CYC - Capture Value 5 Cycle Register */ +/*! @{ */ +#define PWM_CVAL5CYC_CVAL5CYC_MASK (0xFU) +#define PWM_CVAL5CYC_CVAL5CYC_SHIFT (0U) +#define PWM_CVAL5CYC_CVAL5CYC(x) (((uint16_t)(((uint16_t)(x)) << PWM_CVAL5CYC_CVAL5CYC_SHIFT)) & PWM_CVAL5CYC_CVAL5CYC_MASK) +/*! @} */ + +/* The count of PWM_CVAL5CYC */ +#define PWM_CVAL5CYC_COUNT (4U) + +/*! @name OUTEN - Output Enable Register */ +/*! @{ */ +#define PWM_OUTEN_PWMX_EN_MASK (0xFU) +#define PWM_OUTEN_PWMX_EN_SHIFT (0U) +/*! PWMX_EN - PWM_X Output Enables + * 0b0000..PWM_X output disabled. + * 0b0001..PWM_X output enabled. + */ +#define PWM_OUTEN_PWMX_EN(x) (((uint16_t)(((uint16_t)(x)) << PWM_OUTEN_PWMX_EN_SHIFT)) & PWM_OUTEN_PWMX_EN_MASK) +#define PWM_OUTEN_PWMB_EN_MASK (0xF0U) +#define PWM_OUTEN_PWMB_EN_SHIFT (4U) +/*! PWMB_EN - PWM_B Output Enables + * 0b0000..PWM_B output disabled. + * 0b0001..PWM_B output enabled. + */ +#define PWM_OUTEN_PWMB_EN(x) (((uint16_t)(((uint16_t)(x)) << PWM_OUTEN_PWMB_EN_SHIFT)) & PWM_OUTEN_PWMB_EN_MASK) +#define PWM_OUTEN_PWMA_EN_MASK (0xF00U) +#define PWM_OUTEN_PWMA_EN_SHIFT (8U) +/*! PWMA_EN - PWM_A Output Enables + * 0b0000..PWM_A output disabled. + * 0b0001..PWM_A output enabled. + */ +#define PWM_OUTEN_PWMA_EN(x) (((uint16_t)(((uint16_t)(x)) << PWM_OUTEN_PWMA_EN_SHIFT)) & PWM_OUTEN_PWMA_EN_MASK) +/*! @} */ + +/*! @name MASK - Mask Register */ +/*! @{ */ +#define PWM_MASK_MASKX_MASK (0xFU) +#define PWM_MASK_MASKX_SHIFT (0U) +/*! MASKX - PWM_X Masks + * 0b0000..PWM_X output normal. + * 0b0001..PWM_X output masked. + */ +#define PWM_MASK_MASKX(x) (((uint16_t)(((uint16_t)(x)) << PWM_MASK_MASKX_SHIFT)) & PWM_MASK_MASKX_MASK) +#define PWM_MASK_MASKB_MASK (0xF0U) +#define PWM_MASK_MASKB_SHIFT (4U) +/*! MASKB - PWM_B Masks + * 0b0000..PWM_B output normal. + * 0b0001..PWM_B output masked. + */ +#define PWM_MASK_MASKB(x) (((uint16_t)(((uint16_t)(x)) << PWM_MASK_MASKB_SHIFT)) & PWM_MASK_MASKB_MASK) +#define PWM_MASK_MASKA_MASK (0xF00U) +#define PWM_MASK_MASKA_SHIFT (8U) +/*! MASKA - PWM_A Masks + * 0b0000..PWM_A output normal. + * 0b0001..PWM_A output masked. + */ +#define PWM_MASK_MASKA(x) (((uint16_t)(((uint16_t)(x)) << PWM_MASK_MASKA_SHIFT)) & PWM_MASK_MASKA_MASK) +#define PWM_MASK_UPDATE_MASK_MASK (0xF000U) +#define PWM_MASK_UPDATE_MASK_SHIFT (12U) +/*! UPDATE_MASK - Update Mask Bits Immediately + * 0b0000..Normal operation. MASK* bits within the corresponding submodule are not updated until a FORCE_OUT event occurs within the submodule. + * 0b0001..Immediate operation. MASK* bits within the corresponding submodule are updated on the following clock edge after setting this bit. + */ +#define PWM_MASK_UPDATE_MASK(x) (((uint16_t)(((uint16_t)(x)) << PWM_MASK_UPDATE_MASK_SHIFT)) & PWM_MASK_UPDATE_MASK_MASK) +/*! @} */ + +/*! @name SWCOUT - Software Controlled Output Register */ +/*! @{ */ +#define PWM_SWCOUT_SM0OUT45_MASK (0x1U) +#define PWM_SWCOUT_SM0OUT45_SHIFT (0U) +/*! SM0OUT45 - Submodule 0 Software Controlled Output 45 + * 0b0..A logic 0 is supplied to the deadtime generator of submodule 0 instead of PWM45. + * 0b1..A logic 1 is supplied to the deadtime generator of submodule 0 instead of PWM45. + */ +#define PWM_SWCOUT_SM0OUT45(x) (((uint16_t)(((uint16_t)(x)) << PWM_SWCOUT_SM0OUT45_SHIFT)) & PWM_SWCOUT_SM0OUT45_MASK) +#define PWM_SWCOUT_SM0OUT23_MASK (0x2U) +#define PWM_SWCOUT_SM0OUT23_SHIFT (1U) +/*! SM0OUT23 - Submodule 0 Software Controlled Output 23 + * 0b0..A logic 0 is supplied to the deadtime generator of submodule 0 instead of PWM23. + * 0b1..A logic 1 is supplied to the deadtime generator of submodule 0 instead of PWM23. + */ +#define PWM_SWCOUT_SM0OUT23(x) (((uint16_t)(((uint16_t)(x)) << PWM_SWCOUT_SM0OUT23_SHIFT)) & PWM_SWCOUT_SM0OUT23_MASK) +#define PWM_SWCOUT_SM1OUT45_MASK (0x4U) +#define PWM_SWCOUT_SM1OUT45_SHIFT (2U) +/*! SM1OUT45 - Submodule 1 Software Controlled Output 45 + * 0b0..A logic 0 is supplied to the deadtime generator of submodule 1 instead of PWM45. + * 0b1..A logic 1 is supplied to the deadtime generator of submodule 1 instead of PWM45. + */ +#define PWM_SWCOUT_SM1OUT45(x) (((uint16_t)(((uint16_t)(x)) << PWM_SWCOUT_SM1OUT45_SHIFT)) & PWM_SWCOUT_SM1OUT45_MASK) +#define PWM_SWCOUT_SM1OUT23_MASK (0x8U) +#define PWM_SWCOUT_SM1OUT23_SHIFT (3U) +/*! SM1OUT23 - Submodule 1 Software Controlled Output 23 + * 0b0..A logic 0 is supplied to the deadtime generator of submodule 1 instead of PWM23. + * 0b1..A logic 1 is supplied to the deadtime generator of submodule 1 instead of PWM23. + */ +#define PWM_SWCOUT_SM1OUT23(x) (((uint16_t)(((uint16_t)(x)) << PWM_SWCOUT_SM1OUT23_SHIFT)) & PWM_SWCOUT_SM1OUT23_MASK) +#define PWM_SWCOUT_SM2OUT45_MASK (0x10U) +#define PWM_SWCOUT_SM2OUT45_SHIFT (4U) +/*! SM2OUT45 - Submodule 2 Software Controlled Output 45 + * 0b0..A logic 0 is supplied to the deadtime generator of submodule 2 instead of PWM45. + * 0b1..A logic 1 is supplied to the deadtime generator of submodule 2 instead of PWM45. + */ +#define PWM_SWCOUT_SM2OUT45(x) (((uint16_t)(((uint16_t)(x)) << PWM_SWCOUT_SM2OUT45_SHIFT)) & PWM_SWCOUT_SM2OUT45_MASK) +#define PWM_SWCOUT_SM2OUT23_MASK (0x20U) +#define PWM_SWCOUT_SM2OUT23_SHIFT (5U) +/*! SM2OUT23 - Submodule 2 Software Controlled Output 23 + * 0b0..A logic 0 is supplied to the deadtime generator of submodule 2 instead of PWM23. + * 0b1..A logic 1 is supplied to the deadtime generator of submodule 2 instead of PWM23. + */ +#define PWM_SWCOUT_SM2OUT23(x) (((uint16_t)(((uint16_t)(x)) << PWM_SWCOUT_SM2OUT23_SHIFT)) & PWM_SWCOUT_SM2OUT23_MASK) +#define PWM_SWCOUT_SM3OUT45_MASK (0x40U) +#define PWM_SWCOUT_SM3OUT45_SHIFT (6U) +/*! SM3OUT45 - Submodule 3 Software Controlled Output 45 + * 0b0..A logic 0 is supplied to the deadtime generator of submodule 3 instead of PWM45. + * 0b1..A logic 1 is supplied to the deadtime generator of submodule 3 instead of PWM45. + */ +#define PWM_SWCOUT_SM3OUT45(x) (((uint16_t)(((uint16_t)(x)) << PWM_SWCOUT_SM3OUT45_SHIFT)) & PWM_SWCOUT_SM3OUT45_MASK) +#define PWM_SWCOUT_SM3OUT23_MASK (0x80U) +#define PWM_SWCOUT_SM3OUT23_SHIFT (7U) +/*! SM3OUT23 - Submodule 3 Software Controlled Output 23 + * 0b0..A logic 0 is supplied to the deadtime generator of submodule 3 instead of PWM23. + * 0b1..A logic 1 is supplied to the deadtime generator of submodule 3 instead of PWM23. + */ +#define PWM_SWCOUT_SM3OUT23(x) (((uint16_t)(((uint16_t)(x)) << PWM_SWCOUT_SM3OUT23_SHIFT)) & PWM_SWCOUT_SM3OUT23_MASK) +/*! @} */ + +/*! @name DTSRCSEL - PWM Source Select Register */ +/*! @{ */ +#define PWM_DTSRCSEL_SM0SEL45_MASK (0x3U) +#define PWM_DTSRCSEL_SM0SEL45_SHIFT (0U) +/*! SM0SEL45 - Submodule 0 PWM45 Control Select + * 0b00..Generated SM0PWM45 signal is used by the deadtime logic. + * 0b01..Inverted generated SM0PWM45 signal is used by the deadtime logic. + * 0b10..SWCOUT[SM0OUT45] is used by the deadtime logic. + * 0b11..PWM0_EXTB signal is used by the deadtime logic. + */ +#define PWM_DTSRCSEL_SM0SEL45(x) (((uint16_t)(((uint16_t)(x)) << PWM_DTSRCSEL_SM0SEL45_SHIFT)) & PWM_DTSRCSEL_SM0SEL45_MASK) +#define PWM_DTSRCSEL_SM0SEL23_MASK (0xCU) +#define PWM_DTSRCSEL_SM0SEL23_SHIFT (2U) +/*! SM0SEL23 - Submodule 0 PWM23 Control Select + * 0b00..Generated SM0PWM23 signal is used by the deadtime logic. + * 0b01..Inverted generated SM0PWM23 signal is used by the deadtime logic. + * 0b10..SWCOUT[SM0OUT23] is used by the deadtime logic. + * 0b11..PWM0_EXTA signal is used by the deadtime logic. + */ +#define PWM_DTSRCSEL_SM0SEL23(x) (((uint16_t)(((uint16_t)(x)) << PWM_DTSRCSEL_SM0SEL23_SHIFT)) & PWM_DTSRCSEL_SM0SEL23_MASK) +#define PWM_DTSRCSEL_SM1SEL45_MASK (0x30U) +#define PWM_DTSRCSEL_SM1SEL45_SHIFT (4U) +/*! SM1SEL45 - Submodule 1 PWM45 Control Select + * 0b00..Generated SM1PWM45 signal is used by the deadtime logic. + * 0b01..Inverted generated SM1PWM45 signal is used by the deadtime logic. + * 0b10..SWCOUT[SM1OUT45] is used by the deadtime logic. + * 0b11..PWM1_EXTB signal is used by the deadtime logic. + */ +#define PWM_DTSRCSEL_SM1SEL45(x) (((uint16_t)(((uint16_t)(x)) << PWM_DTSRCSEL_SM1SEL45_SHIFT)) & PWM_DTSRCSEL_SM1SEL45_MASK) +#define PWM_DTSRCSEL_SM1SEL23_MASK (0xC0U) +#define PWM_DTSRCSEL_SM1SEL23_SHIFT (6U) +/*! SM1SEL23 - Submodule 1 PWM23 Control Select + * 0b00..Generated SM1PWM23 signal is used by the deadtime logic. + * 0b01..Inverted generated SM1PWM23 signal is used by the deadtime logic. + * 0b10..SWCOUT[SM1OUT23] is used by the deadtime logic. + * 0b11..PWM1_EXTA signal is used by the deadtime logic. + */ +#define PWM_DTSRCSEL_SM1SEL23(x) (((uint16_t)(((uint16_t)(x)) << PWM_DTSRCSEL_SM1SEL23_SHIFT)) & PWM_DTSRCSEL_SM1SEL23_MASK) +#define PWM_DTSRCSEL_SM2SEL45_MASK (0x300U) +#define PWM_DTSRCSEL_SM2SEL45_SHIFT (8U) +/*! SM2SEL45 - Submodule 2 PWM45 Control Select + * 0b00..Generated SM2PWM45 signal is used by the deadtime logic. + * 0b01..Inverted generated SM2PWM45 signal is used by the deadtime logic. + * 0b10..SWCOUT[SM2OUT45] is used by the deadtime logic. + * 0b11..PWM2_EXTB signal is used by the deadtime logic. + */ +#define PWM_DTSRCSEL_SM2SEL45(x) (((uint16_t)(((uint16_t)(x)) << PWM_DTSRCSEL_SM2SEL45_SHIFT)) & PWM_DTSRCSEL_SM2SEL45_MASK) +#define PWM_DTSRCSEL_SM2SEL23_MASK (0xC00U) +#define PWM_DTSRCSEL_SM2SEL23_SHIFT (10U) +/*! SM2SEL23 - Submodule 2 PWM23 Control Select + * 0b00..Generated SM2PWM23 signal is used by the deadtime logic. + * 0b01..Inverted generated SM2PWM23 signal is used by the deadtime logic. + * 0b10..SWCOUT[SM2OUT23] is used by the deadtime logic. + * 0b11..PWM2_EXTA signal is used by the deadtime logic. + */ +#define PWM_DTSRCSEL_SM2SEL23(x) (((uint16_t)(((uint16_t)(x)) << PWM_DTSRCSEL_SM2SEL23_SHIFT)) & PWM_DTSRCSEL_SM2SEL23_MASK) +#define PWM_DTSRCSEL_SM3SEL45_MASK (0x3000U) +#define PWM_DTSRCSEL_SM3SEL45_SHIFT (12U) +/*! SM3SEL45 - Submodule 3 PWM45 Control Select + * 0b00..Generated SM3PWM45 signal is used by the deadtime logic. + * 0b01..Inverted generated SM3PWM45 signal is used by the deadtime logic. + * 0b10..SWCOUT[SM3OUT45] is used by the deadtime logic. + * 0b11..PWM3_EXTB signal is used by the deadtime logic. + */ +#define PWM_DTSRCSEL_SM3SEL45(x) (((uint16_t)(((uint16_t)(x)) << PWM_DTSRCSEL_SM3SEL45_SHIFT)) & PWM_DTSRCSEL_SM3SEL45_MASK) +#define PWM_DTSRCSEL_SM3SEL23_MASK (0xC000U) +#define PWM_DTSRCSEL_SM3SEL23_SHIFT (14U) +/*! SM3SEL23 - Submodule 3 PWM23 Control Select + * 0b00..Generated SM3PWM23 signal is used by the deadtime logic. + * 0b01..Inverted generated SM3PWM23 signal is used by the deadtime logic. + * 0b10..SWCOUT[SM3OUT23] is used by the deadtime logic. + * 0b11..PWM3_EXTA signal is used by the deadtime logic. + */ +#define PWM_DTSRCSEL_SM3SEL23(x) (((uint16_t)(((uint16_t)(x)) << PWM_DTSRCSEL_SM3SEL23_SHIFT)) & PWM_DTSRCSEL_SM3SEL23_MASK) +/*! @} */ + +/*! @name MCTRL - Master Control Register */ +/*! @{ */ +#define PWM_MCTRL_LDOK_MASK (0xFU) +#define PWM_MCTRL_LDOK_SHIFT (0U) +/*! LDOK - Load Okay + * 0b0000..Do not load new values. + * 0b0001..Load prescaler, modulus, and PWM values of the corresponding submodule. + */ +#define PWM_MCTRL_LDOK(x) (((uint16_t)(((uint16_t)(x)) << PWM_MCTRL_LDOK_SHIFT)) & PWM_MCTRL_LDOK_MASK) +#define PWM_MCTRL_CLDOK_MASK (0xF0U) +#define PWM_MCTRL_CLDOK_SHIFT (4U) +#define PWM_MCTRL_CLDOK(x) (((uint16_t)(((uint16_t)(x)) << PWM_MCTRL_CLDOK_SHIFT)) & PWM_MCTRL_CLDOK_MASK) +#define PWM_MCTRL_RUN_MASK (0xF00U) +#define PWM_MCTRL_RUN_SHIFT (8U) +/*! RUN - Run + * 0b0000..PWM generator is disabled in the corresponding submodule. + * 0b0001..PWM generator is enabled in the corresponding submodule. + */ +#define PWM_MCTRL_RUN(x) (((uint16_t)(((uint16_t)(x)) << PWM_MCTRL_RUN_SHIFT)) & PWM_MCTRL_RUN_MASK) +#define PWM_MCTRL_IPOL_MASK (0xF000U) +#define PWM_MCTRL_IPOL_SHIFT (12U) +/*! IPOL - Current Polarity + * 0b0000..PWM23 is used to generate complementary PWM pair in the corresponding submodule. + * 0b0001..PWM45 is used to generate complementary PWM pair in the corresponding submodule. + */ +#define PWM_MCTRL_IPOL(x) (((uint16_t)(((uint16_t)(x)) << PWM_MCTRL_IPOL_SHIFT)) & PWM_MCTRL_IPOL_MASK) +/*! @} */ + +/*! @name MCTRL2 - Master Control 2 Register */ +/*! @{ */ +#define PWM_MCTRL2_MONPLL_MASK (0x3U) +#define PWM_MCTRL2_MONPLL_SHIFT (0U) +/*! MONPLL - Monitor PLL State + * 0b00..Not locked. Do not monitor PLL operation. Resetting of the fractional delay block in case of PLL losing lock will be controlled by software. + * 0b01..Not locked. Monitor PLL operation to automatically disable the fractional delay block when the PLL encounters problems. + * 0b10..Locked. Do not monitor PLL operation. Resetting of the fractional delay block in case of PLL losing lock will be controlled by software. These bits are write protected until the next reset. + * 0b11..Locked. Monitor PLL operation to automatically disable the fractional delay block when the PLL encounters problems. These bits are write protected until the next reset. + */ +#define PWM_MCTRL2_MONPLL(x) (((uint16_t)(((uint16_t)(x)) << PWM_MCTRL2_MONPLL_SHIFT)) & PWM_MCTRL2_MONPLL_MASK) +/*! @} */ + +/*! @name FCTRL - Fault Control Register */ +/*! @{ */ +#define PWM_FCTRL_FIE_MASK (0xFU) +#define PWM_FCTRL_FIE_SHIFT (0U) +/*! FIE - Fault Interrupt Enables + * 0b0000..FAULTx CPU interrupt requests disabled. + * 0b0001..FAULTx CPU interrupt requests enabled. + */ +#define PWM_FCTRL_FIE(x) (((uint16_t)(((uint16_t)(x)) << PWM_FCTRL_FIE_SHIFT)) & PWM_FCTRL_FIE_MASK) +#define PWM_FCTRL_FSAFE_MASK (0xF0U) +#define PWM_FCTRL_FSAFE_SHIFT (4U) +/*! FSAFE - Fault Safety Mode + * 0b0000..Normal mode. PWM outputs disabled by this fault are not enabled until FSTS[FFLAGx] is clear at the start of a half cycle or full cycle depending on the state of FSTS[FFULL] without regard to the state of FSTS[FFPINx]. The PWM outputs disabled by this fault input will not be re-enabled until the actual FAULTx input signal de-asserts since the fault input will combinationally disable the PWM outputs (as programmed in DISMAPn). + * 0b0001..Safe mode. PWM outputs disabled by this fault are not enabled until FSTS[FFLAGx] is clear and FSTS[FFPINx] is clear at the start of a half cycle or full cycle depending on the state of FSTS[FFULL]. + */ +#define PWM_FCTRL_FSAFE(x) (((uint16_t)(((uint16_t)(x)) << PWM_FCTRL_FSAFE_SHIFT)) & PWM_FCTRL_FSAFE_MASK) +#define PWM_FCTRL_FAUTO_MASK (0xF00U) +#define PWM_FCTRL_FAUTO_SHIFT (8U) +/*! FAUTO - Automatic Fault Clearing + * 0b0000..Manual fault clearing. PWM outputs disabled by this fault are not enabled until FSTS[FFLAGx] is clear at the start of a half cycle or full cycle depending the state of FSTS[FFULL]. This is further controlled by FCTRL[FSAFE]. + * 0b0001..Automatic fault clearing. PWM outputs disabled by this fault are enabled when FSTS[FFPINx] is clear at the start of a half cycle or full cycle depending on the state of FSTS[FFULL] without regard to the state of FSTS[FFLAGx]. + */ +#define PWM_FCTRL_FAUTO(x) (((uint16_t)(((uint16_t)(x)) << PWM_FCTRL_FAUTO_SHIFT)) & PWM_FCTRL_FAUTO_MASK) +#define PWM_FCTRL_FLVL_MASK (0xF000U) +#define PWM_FCTRL_FLVL_SHIFT (12U) +/*! FLVL - Fault Level + * 0b0000..A logic 0 on the fault input indicates a fault condition. + * 0b0001..A logic 1 on the fault input indicates a fault condition. + */ +#define PWM_FCTRL_FLVL(x) (((uint16_t)(((uint16_t)(x)) << PWM_FCTRL_FLVL_SHIFT)) & PWM_FCTRL_FLVL_MASK) +/*! @} */ + +/*! @name FSTS - Fault Status Register */ +/*! @{ */ +#define PWM_FSTS_FFLAG_MASK (0xFU) +#define PWM_FSTS_FFLAG_SHIFT (0U) +/*! FFLAG - Fault Flags + * 0b0000..No fault on the FAULTx pin. + * 0b0001..Fault on the FAULTx pin. + */ +#define PWM_FSTS_FFLAG(x) (((uint16_t)(((uint16_t)(x)) << PWM_FSTS_FFLAG_SHIFT)) & PWM_FSTS_FFLAG_MASK) +#define PWM_FSTS_FFULL_MASK (0xF0U) +#define PWM_FSTS_FFULL_SHIFT (4U) +/*! FFULL - Full Cycle + * 0b0000..PWM outputs are not re-enabled at the start of a full cycle + * 0b0001..PWM outputs are re-enabled at the start of a full cycle + */ +#define PWM_FSTS_FFULL(x) (((uint16_t)(((uint16_t)(x)) << PWM_FSTS_FFULL_SHIFT)) & PWM_FSTS_FFULL_MASK) +#define PWM_FSTS_FFPIN_MASK (0xF00U) +#define PWM_FSTS_FFPIN_SHIFT (8U) +#define PWM_FSTS_FFPIN(x) (((uint16_t)(((uint16_t)(x)) << PWM_FSTS_FFPIN_SHIFT)) & PWM_FSTS_FFPIN_MASK) +#define PWM_FSTS_FHALF_MASK (0xF000U) +#define PWM_FSTS_FHALF_SHIFT (12U) +/*! FHALF - Half Cycle Fault Recovery + * 0b0000..PWM outputs are not re-enabled at the start of a half cycle. + * 0b0001..PWM outputs are re-enabled at the start of a half cycle (as defined by VAL0). + */ +#define PWM_FSTS_FHALF(x) (((uint16_t)(((uint16_t)(x)) << PWM_FSTS_FHALF_SHIFT)) & PWM_FSTS_FHALF_MASK) +/*! @} */ + +/*! @name FFILT - Fault Filter Register */ +/*! @{ */ +#define PWM_FFILT_FILT_PER_MASK (0xFFU) +#define PWM_FFILT_FILT_PER_SHIFT (0U) +#define PWM_FFILT_FILT_PER(x) (((uint16_t)(((uint16_t)(x)) << PWM_FFILT_FILT_PER_SHIFT)) & PWM_FFILT_FILT_PER_MASK) +#define PWM_FFILT_FILT_CNT_MASK (0x700U) +#define PWM_FFILT_FILT_CNT_SHIFT (8U) +#define PWM_FFILT_FILT_CNT(x) (((uint16_t)(((uint16_t)(x)) << PWM_FFILT_FILT_CNT_SHIFT)) & PWM_FFILT_FILT_CNT_MASK) +#define PWM_FFILT_GSTR_MASK (0x8000U) +#define PWM_FFILT_GSTR_SHIFT (15U) +/*! GSTR - Fault Glitch Stretch Enable + * 0b0..Fault input glitch stretching is disabled. + * 0b1..Input fault signals will be stretched to at least 2 IPBus clock cycles. + */ +#define PWM_FFILT_GSTR(x) (((uint16_t)(((uint16_t)(x)) << PWM_FFILT_GSTR_SHIFT)) & PWM_FFILT_GSTR_MASK) +/*! @} */ + +/*! @name FTST - Fault Test Register */ +/*! @{ */ +#define PWM_FTST_FTEST_MASK (0x1U) +#define PWM_FTST_FTEST_SHIFT (0U) +/*! FTEST - Fault Test + * 0b0..No fault + * 0b1..Cause a simulated fault + */ +#define PWM_FTST_FTEST(x) (((uint16_t)(((uint16_t)(x)) << PWM_FTST_FTEST_SHIFT)) & PWM_FTST_FTEST_MASK) +/*! @} */ + +/*! @name FCTRL2 - Fault Control 2 Register */ +/*! @{ */ +#define PWM_FCTRL2_NOCOMB_MASK (0xFU) +#define PWM_FCTRL2_NOCOMB_SHIFT (0U) +/*! NOCOMB - No Combinational Path From Fault Input To PWM Output + * 0b0000..There is a combinational link from the fault inputs to the PWM outputs. The fault inputs are combined with the filtered and latched fault signals to disable the PWM outputs. + * 0b0001..The direct combinational path from the fault inputs to the PWM outputs is disabled and the filtered and latched fault signals are used to disable the PWM outputs. + */ +#define PWM_FCTRL2_NOCOMB(x) (((uint16_t)(((uint16_t)(x)) << PWM_FCTRL2_NOCOMB_SHIFT)) & PWM_FCTRL2_NOCOMB_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group PWM_Register_Masks */ + + +/* PWM - Peripheral instance base addresses */ +/** Peripheral PWM1 base address */ +#define PWM1_BASE (0x403DC000u) +/** Peripheral PWM1 base pointer */ +#define PWM1 ((PWM_Type *)PWM1_BASE) +/** Peripheral PWM2 base address */ +#define PWM2_BASE (0x403E0000u) +/** Peripheral PWM2 base pointer */ +#define PWM2 ((PWM_Type *)PWM2_BASE) +/** Peripheral PWM3 base address */ +#define PWM3_BASE (0x403E4000u) +/** Peripheral PWM3 base pointer */ +#define PWM3 ((PWM_Type *)PWM3_BASE) +/** Peripheral PWM4 base address */ +#define PWM4_BASE (0x403E8000u) +/** Peripheral PWM4 base pointer */ +#define PWM4 ((PWM_Type *)PWM4_BASE) +/** Array initializer of PWM peripheral base addresses */ +#define PWM_BASE_ADDRS { 0u, PWM1_BASE, PWM2_BASE, PWM3_BASE, PWM4_BASE } +/** Array initializer of PWM peripheral base pointers */ +#define PWM_BASE_PTRS { (PWM_Type *)0u, PWM1, PWM2, PWM3, PWM4 } +/** Interrupt vectors for the PWM peripheral type */ +#define PWM_CMP_IRQS { { NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn }, { PWM1_0_IRQn, PWM1_1_IRQn, PWM1_2_IRQn, PWM1_3_IRQn }, { PWM2_0_IRQn, PWM2_1_IRQn, PWM2_2_IRQn, PWM2_3_IRQn }, { PWM3_0_IRQn, PWM3_1_IRQn, PWM3_2_IRQn, PWM3_3_IRQn }, { PWM4_0_IRQn, PWM4_1_IRQn, PWM4_2_IRQn, PWM4_3_IRQn } } +#define PWM_RELOAD_IRQS { { NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn }, { PWM1_0_IRQn, PWM1_1_IRQn, PWM1_2_IRQn, PWM1_3_IRQn }, { PWM2_0_IRQn, PWM2_1_IRQn, PWM2_2_IRQn, PWM2_3_IRQn }, { PWM3_0_IRQn, PWM3_1_IRQn, PWM3_2_IRQn, PWM3_3_IRQn }, { PWM4_0_IRQn, PWM4_1_IRQn, PWM4_2_IRQn, PWM4_3_IRQn } } +#define PWM_CAPTURE_IRQS { { NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn }, { PWM1_0_IRQn, PWM1_1_IRQn, PWM1_2_IRQn, PWM1_3_IRQn }, { PWM2_0_IRQn, PWM2_1_IRQn, PWM2_2_IRQn, PWM2_3_IRQn }, { PWM3_0_IRQn, PWM3_1_IRQn, PWM3_2_IRQn, PWM3_3_IRQn }, { PWM4_0_IRQn, PWM4_1_IRQn, PWM4_2_IRQn, PWM4_3_IRQn } } +#define PWM_FAULT_IRQS { NotAvail_IRQn, PWM1_FAULT_IRQn, PWM2_FAULT_IRQn, PWM3_FAULT_IRQn, PWM4_FAULT_IRQn } +#define PWM_RELOAD_ERROR_IRQS { NotAvail_IRQn, PWM1_FAULT_IRQn, PWM2_FAULT_IRQn, PWM3_FAULT_IRQn, PWM4_FAULT_IRQn } + +/*! + * @} + */ /* end of group PWM_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- PXP Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup PXP_Peripheral_Access_Layer PXP Peripheral Access Layer + * @{ + */ + +/** PXP - Register Layout Typedef */ +typedef struct { + __IO uint32_t CTRL; /**< Control Register 0, offset: 0x0 */ + __IO uint32_t CTRL_SET; /**< Control Register 0, offset: 0x4 */ + __IO uint32_t CTRL_CLR; /**< Control Register 0, offset: 0x8 */ + __IO uint32_t CTRL_TOG; /**< Control Register 0, offset: 0xC */ + __IO uint32_t STAT; /**< Status Register, offset: 0x10 */ + __IO uint32_t STAT_SET; /**< Status Register, offset: 0x14 */ + __IO uint32_t STAT_CLR; /**< Status Register, offset: 0x18 */ + __IO uint32_t STAT_TOG; /**< Status Register, offset: 0x1C */ + __IO uint32_t OUT_CTRL; /**< Output Buffer Control Register, offset: 0x20 */ + __IO uint32_t OUT_CTRL_SET; /**< Output Buffer Control Register, offset: 0x24 */ + __IO uint32_t OUT_CTRL_CLR; /**< Output Buffer Control Register, offset: 0x28 */ + __IO uint32_t OUT_CTRL_TOG; /**< Output Buffer Control Register, offset: 0x2C */ + __IO uint32_t OUT_BUF; /**< Output Frame Buffer Pointer, offset: 0x30 */ + uint8_t RESERVED_0[12]; + __IO uint32_t OUT_BUF2; /**< Output Frame Buffer Pointer #2, offset: 0x40 */ + uint8_t RESERVED_1[12]; + __IO uint32_t OUT_PITCH; /**< Output Buffer Pitch, offset: 0x50 */ + uint8_t RESERVED_2[12]; + __IO uint32_t OUT_LRC; /**< Output Surface Lower Right Coordinate, offset: 0x60 */ + uint8_t RESERVED_3[12]; + __IO uint32_t OUT_PS_ULC; /**< Processed Surface Upper Left Coordinate, offset: 0x70 */ + uint8_t RESERVED_4[12]; + __IO uint32_t OUT_PS_LRC; /**< Processed Surface Lower Right Coordinate, offset: 0x80 */ + uint8_t RESERVED_5[12]; + __IO uint32_t OUT_AS_ULC; /**< Alpha Surface Upper Left Coordinate, offset: 0x90 */ + uint8_t RESERVED_6[12]; + __IO uint32_t OUT_AS_LRC; /**< Alpha Surface Lower Right Coordinate, offset: 0xA0 */ + uint8_t RESERVED_7[12]; + __IO uint32_t PS_CTRL; /**< Processed Surface (PS) Control Register, offset: 0xB0 */ + __IO uint32_t PS_CTRL_SET; /**< Processed Surface (PS) Control Register, offset: 0xB4 */ + __IO uint32_t PS_CTRL_CLR; /**< Processed Surface (PS) Control Register, offset: 0xB8 */ + __IO uint32_t PS_CTRL_TOG; /**< Processed Surface (PS) Control Register, offset: 0xBC */ + __IO uint32_t PS_BUF; /**< PS Input Buffer Address, offset: 0xC0 */ + uint8_t RESERVED_8[12]; + __IO uint32_t PS_UBUF; /**< PS U/Cb or 2 Plane UV Input Buffer Address, offset: 0xD0 */ + uint8_t RESERVED_9[12]; + __IO uint32_t PS_VBUF; /**< PS V/Cr Input Buffer Address, offset: 0xE0 */ + uint8_t RESERVED_10[12]; + __IO uint32_t PS_PITCH; /**< Processed Surface Pitch, offset: 0xF0 */ + uint8_t RESERVED_11[12]; + __IO uint32_t PS_BACKGROUND; /**< PS Background Color, offset: 0x100 */ + uint8_t RESERVED_12[12]; + __IO uint32_t PS_SCALE; /**< PS Scale Factor Register, offset: 0x110 */ + uint8_t RESERVED_13[12]; + __IO uint32_t PS_OFFSET; /**< PS Scale Offset Register, offset: 0x120 */ + uint8_t RESERVED_14[12]; + __IO uint32_t PS_CLRKEYLOW; /**< PS Color Key Low, offset: 0x130 */ + uint8_t RESERVED_15[12]; + __IO uint32_t PS_CLRKEYHIGH; /**< PS Color Key High, offset: 0x140 */ + uint8_t RESERVED_16[12]; + __IO uint32_t AS_CTRL; /**< Alpha Surface Control, offset: 0x150 */ + uint8_t RESERVED_17[12]; + __IO uint32_t AS_BUF; /**< Alpha Surface Buffer Pointer, offset: 0x160 */ + uint8_t RESERVED_18[12]; + __IO uint32_t AS_PITCH; /**< Alpha Surface Pitch, offset: 0x170 */ + uint8_t RESERVED_19[12]; + __IO uint32_t AS_CLRKEYLOW; /**< Overlay Color Key Low, offset: 0x180 */ + uint8_t RESERVED_20[12]; + __IO uint32_t AS_CLRKEYHIGH; /**< Overlay Color Key High, offset: 0x190 */ + uint8_t RESERVED_21[12]; + __IO uint32_t CSC1_COEF0; /**< Color Space Conversion Coefficient Register 0, offset: 0x1A0 */ + uint8_t RESERVED_22[12]; + __IO uint32_t CSC1_COEF1; /**< Color Space Conversion Coefficient Register 1, offset: 0x1B0 */ + uint8_t RESERVED_23[12]; + __IO uint32_t CSC1_COEF2; /**< Color Space Conversion Coefficient Register 2, offset: 0x1C0 */ + uint8_t RESERVED_24[348]; + __IO uint32_t POWER; /**< PXP Power Control Register, offset: 0x320 */ + uint8_t RESERVED_25[220]; + __IO uint32_t NEXT; /**< Next Frame Pointer, offset: 0x400 */ + uint8_t RESERVED_26[60]; + __IO uint32_t PORTER_DUFF_CTRL; /**< PXP Alpha Engine A Control Register., offset: 0x440 */ +} PXP_Type; + +/* ---------------------------------------------------------------------------- + -- PXP Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup PXP_Register_Masks PXP Register Masks + * @{ + */ + +/*! @name CTRL - Control Register 0 */ +/*! @{ */ +#define PXP_CTRL_ENABLE_MASK (0x1U) +#define PXP_CTRL_ENABLE_SHIFT (0U) +#define PXP_CTRL_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_ENABLE_SHIFT)) & PXP_CTRL_ENABLE_MASK) +#define PXP_CTRL_IRQ_ENABLE_MASK (0x2U) +#define PXP_CTRL_IRQ_ENABLE_SHIFT (1U) +#define PXP_CTRL_IRQ_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_IRQ_ENABLE_SHIFT)) & PXP_CTRL_IRQ_ENABLE_MASK) +#define PXP_CTRL_NEXT_IRQ_ENABLE_MASK (0x4U) +#define PXP_CTRL_NEXT_IRQ_ENABLE_SHIFT (2U) +#define PXP_CTRL_NEXT_IRQ_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_NEXT_IRQ_ENABLE_SHIFT)) & PXP_CTRL_NEXT_IRQ_ENABLE_MASK) +#define PXP_CTRL_ENABLE_LCD_HANDSHAKE_MASK (0x10U) +#define PXP_CTRL_ENABLE_LCD_HANDSHAKE_SHIFT (4U) +#define PXP_CTRL_ENABLE_LCD_HANDSHAKE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_ENABLE_LCD_HANDSHAKE_SHIFT)) & PXP_CTRL_ENABLE_LCD_HANDSHAKE_MASK) +#define PXP_CTRL_RSVD0_MASK (0xE0U) +#define PXP_CTRL_RSVD0_SHIFT (5U) +#define PXP_CTRL_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_RSVD0_SHIFT)) & PXP_CTRL_RSVD0_MASK) +#define PXP_CTRL_ROTATE_MASK (0x300U) +#define PXP_CTRL_ROTATE_SHIFT (8U) +/*! ROTATE + * 0b00..ROT_0 + * 0b01..ROT_90 + * 0b10..ROT_180 + * 0b11..ROT_270 + */ +#define PXP_CTRL_ROTATE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_ROTATE_SHIFT)) & PXP_CTRL_ROTATE_MASK) +#define PXP_CTRL_HFLIP_MASK (0x400U) +#define PXP_CTRL_HFLIP_SHIFT (10U) +#define PXP_CTRL_HFLIP(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_HFLIP_SHIFT)) & PXP_CTRL_HFLIP_MASK) +#define PXP_CTRL_VFLIP_MASK (0x800U) +#define PXP_CTRL_VFLIP_SHIFT (11U) +#define PXP_CTRL_VFLIP(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_VFLIP_SHIFT)) & PXP_CTRL_VFLIP_MASK) +#define PXP_CTRL_RSVD1_MASK (0x3FF000U) +#define PXP_CTRL_RSVD1_SHIFT (12U) +#define PXP_CTRL_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_RSVD1_SHIFT)) & PXP_CTRL_RSVD1_MASK) +#define PXP_CTRL_ROT_POS_MASK (0x400000U) +#define PXP_CTRL_ROT_POS_SHIFT (22U) +#define PXP_CTRL_ROT_POS(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_ROT_POS_SHIFT)) & PXP_CTRL_ROT_POS_MASK) +#define PXP_CTRL_BLOCK_SIZE_MASK (0x800000U) +#define PXP_CTRL_BLOCK_SIZE_SHIFT (23U) +/*! BLOCK_SIZE + * 0b0..Process 8x8 pixel blocks. + * 0b1..Process 16x16 pixel blocks. + */ +#define PXP_CTRL_BLOCK_SIZE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_BLOCK_SIZE_SHIFT)) & PXP_CTRL_BLOCK_SIZE_MASK) +#define PXP_CTRL_RSVD3_MASK (0xF000000U) +#define PXP_CTRL_RSVD3_SHIFT (24U) +#define PXP_CTRL_RSVD3(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_RSVD3_SHIFT)) & PXP_CTRL_RSVD3_MASK) +#define PXP_CTRL_EN_REPEAT_MASK (0x10000000U) +#define PXP_CTRL_EN_REPEAT_SHIFT (28U) +#define PXP_CTRL_EN_REPEAT(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_EN_REPEAT_SHIFT)) & PXP_CTRL_EN_REPEAT_MASK) +#define PXP_CTRL_RSVD4_MASK (0x20000000U) +#define PXP_CTRL_RSVD4_SHIFT (29U) +#define PXP_CTRL_RSVD4(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_RSVD4_SHIFT)) & PXP_CTRL_RSVD4_MASK) +#define PXP_CTRL_CLKGATE_MASK (0x40000000U) +#define PXP_CTRL_CLKGATE_SHIFT (30U) +#define PXP_CTRL_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_CLKGATE_SHIFT)) & PXP_CTRL_CLKGATE_MASK) +#define PXP_CTRL_SFTRST_MASK (0x80000000U) +#define PXP_CTRL_SFTRST_SHIFT (31U) +#define PXP_CTRL_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_SFTRST_SHIFT)) & PXP_CTRL_SFTRST_MASK) +/*! @} */ + +/*! @name CTRL_SET - Control Register 0 */ +/*! @{ */ +#define PXP_CTRL_SET_ENABLE_MASK (0x1U) +#define PXP_CTRL_SET_ENABLE_SHIFT (0U) +#define PXP_CTRL_SET_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_SET_ENABLE_SHIFT)) & PXP_CTRL_SET_ENABLE_MASK) +#define PXP_CTRL_SET_IRQ_ENABLE_MASK (0x2U) +#define PXP_CTRL_SET_IRQ_ENABLE_SHIFT (1U) +#define PXP_CTRL_SET_IRQ_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_SET_IRQ_ENABLE_SHIFT)) & PXP_CTRL_SET_IRQ_ENABLE_MASK) +#define PXP_CTRL_SET_NEXT_IRQ_ENABLE_MASK (0x4U) +#define PXP_CTRL_SET_NEXT_IRQ_ENABLE_SHIFT (2U) +#define PXP_CTRL_SET_NEXT_IRQ_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_SET_NEXT_IRQ_ENABLE_SHIFT)) & PXP_CTRL_SET_NEXT_IRQ_ENABLE_MASK) +#define PXP_CTRL_SET_ENABLE_LCD_HANDSHAKE_MASK (0x10U) +#define PXP_CTRL_SET_ENABLE_LCD_HANDSHAKE_SHIFT (4U) +#define PXP_CTRL_SET_ENABLE_LCD_HANDSHAKE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_SET_ENABLE_LCD_HANDSHAKE_SHIFT)) & PXP_CTRL_SET_ENABLE_LCD_HANDSHAKE_MASK) +#define PXP_CTRL_SET_RSVD0_MASK (0xE0U) +#define PXP_CTRL_SET_RSVD0_SHIFT (5U) +#define PXP_CTRL_SET_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_SET_RSVD0_SHIFT)) & PXP_CTRL_SET_RSVD0_MASK) +#define PXP_CTRL_SET_ROTATE_MASK (0x300U) +#define PXP_CTRL_SET_ROTATE_SHIFT (8U) +/*! ROTATE + * 0b00..ROT_0 + * 0b01..ROT_90 + * 0b10..ROT_180 + * 0b11..ROT_270 + */ +#define PXP_CTRL_SET_ROTATE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_SET_ROTATE_SHIFT)) & PXP_CTRL_SET_ROTATE_MASK) +#define PXP_CTRL_SET_HFLIP_MASK (0x400U) +#define PXP_CTRL_SET_HFLIP_SHIFT (10U) +#define PXP_CTRL_SET_HFLIP(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_SET_HFLIP_SHIFT)) & PXP_CTRL_SET_HFLIP_MASK) +#define PXP_CTRL_SET_VFLIP_MASK (0x800U) +#define PXP_CTRL_SET_VFLIP_SHIFT (11U) +#define PXP_CTRL_SET_VFLIP(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_SET_VFLIP_SHIFT)) & PXP_CTRL_SET_VFLIP_MASK) +#define PXP_CTRL_SET_RSVD1_MASK (0x3FF000U) +#define PXP_CTRL_SET_RSVD1_SHIFT (12U) +#define PXP_CTRL_SET_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_SET_RSVD1_SHIFT)) & PXP_CTRL_SET_RSVD1_MASK) +#define PXP_CTRL_SET_ROT_POS_MASK (0x400000U) +#define PXP_CTRL_SET_ROT_POS_SHIFT (22U) +#define PXP_CTRL_SET_ROT_POS(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_SET_ROT_POS_SHIFT)) & PXP_CTRL_SET_ROT_POS_MASK) +#define PXP_CTRL_SET_BLOCK_SIZE_MASK (0x800000U) +#define PXP_CTRL_SET_BLOCK_SIZE_SHIFT (23U) +/*! BLOCK_SIZE + * 0b0..Process 8x8 pixel blocks. + * 0b1..Process 16x16 pixel blocks. + */ +#define PXP_CTRL_SET_BLOCK_SIZE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_SET_BLOCK_SIZE_SHIFT)) & PXP_CTRL_SET_BLOCK_SIZE_MASK) +#define PXP_CTRL_SET_RSVD3_MASK (0xF000000U) +#define PXP_CTRL_SET_RSVD3_SHIFT (24U) +#define PXP_CTRL_SET_RSVD3(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_SET_RSVD3_SHIFT)) & PXP_CTRL_SET_RSVD3_MASK) +#define PXP_CTRL_SET_EN_REPEAT_MASK (0x10000000U) +#define PXP_CTRL_SET_EN_REPEAT_SHIFT (28U) +#define PXP_CTRL_SET_EN_REPEAT(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_SET_EN_REPEAT_SHIFT)) & PXP_CTRL_SET_EN_REPEAT_MASK) +#define PXP_CTRL_SET_RSVD4_MASK (0x20000000U) +#define PXP_CTRL_SET_RSVD4_SHIFT (29U) +#define PXP_CTRL_SET_RSVD4(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_SET_RSVD4_SHIFT)) & PXP_CTRL_SET_RSVD4_MASK) +#define PXP_CTRL_SET_CLKGATE_MASK (0x40000000U) +#define PXP_CTRL_SET_CLKGATE_SHIFT (30U) +#define PXP_CTRL_SET_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_SET_CLKGATE_SHIFT)) & PXP_CTRL_SET_CLKGATE_MASK) +#define PXP_CTRL_SET_SFTRST_MASK (0x80000000U) +#define PXP_CTRL_SET_SFTRST_SHIFT (31U) +#define PXP_CTRL_SET_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_SET_SFTRST_SHIFT)) & PXP_CTRL_SET_SFTRST_MASK) +/*! @} */ + +/*! @name CTRL_CLR - Control Register 0 */ +/*! @{ */ +#define PXP_CTRL_CLR_ENABLE_MASK (0x1U) +#define PXP_CTRL_CLR_ENABLE_SHIFT (0U) +#define PXP_CTRL_CLR_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_CLR_ENABLE_SHIFT)) & PXP_CTRL_CLR_ENABLE_MASK) +#define PXP_CTRL_CLR_IRQ_ENABLE_MASK (0x2U) +#define PXP_CTRL_CLR_IRQ_ENABLE_SHIFT (1U) +#define PXP_CTRL_CLR_IRQ_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_CLR_IRQ_ENABLE_SHIFT)) & PXP_CTRL_CLR_IRQ_ENABLE_MASK) +#define PXP_CTRL_CLR_NEXT_IRQ_ENABLE_MASK (0x4U) +#define PXP_CTRL_CLR_NEXT_IRQ_ENABLE_SHIFT (2U) +#define PXP_CTRL_CLR_NEXT_IRQ_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_CLR_NEXT_IRQ_ENABLE_SHIFT)) & PXP_CTRL_CLR_NEXT_IRQ_ENABLE_MASK) +#define PXP_CTRL_CLR_ENABLE_LCD_HANDSHAKE_MASK (0x10U) +#define PXP_CTRL_CLR_ENABLE_LCD_HANDSHAKE_SHIFT (4U) +#define PXP_CTRL_CLR_ENABLE_LCD_HANDSHAKE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_CLR_ENABLE_LCD_HANDSHAKE_SHIFT)) & PXP_CTRL_CLR_ENABLE_LCD_HANDSHAKE_MASK) +#define PXP_CTRL_CLR_RSVD0_MASK (0xE0U) +#define PXP_CTRL_CLR_RSVD0_SHIFT (5U) +#define PXP_CTRL_CLR_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_CLR_RSVD0_SHIFT)) & PXP_CTRL_CLR_RSVD0_MASK) +#define PXP_CTRL_CLR_ROTATE_MASK (0x300U) +#define PXP_CTRL_CLR_ROTATE_SHIFT (8U) +/*! ROTATE + * 0b00..ROT_0 + * 0b01..ROT_90 + * 0b10..ROT_180 + * 0b11..ROT_270 + */ +#define PXP_CTRL_CLR_ROTATE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_CLR_ROTATE_SHIFT)) & PXP_CTRL_CLR_ROTATE_MASK) +#define PXP_CTRL_CLR_HFLIP_MASK (0x400U) +#define PXP_CTRL_CLR_HFLIP_SHIFT (10U) +#define PXP_CTRL_CLR_HFLIP(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_CLR_HFLIP_SHIFT)) & PXP_CTRL_CLR_HFLIP_MASK) +#define PXP_CTRL_CLR_VFLIP_MASK (0x800U) +#define PXP_CTRL_CLR_VFLIP_SHIFT (11U) +#define PXP_CTRL_CLR_VFLIP(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_CLR_VFLIP_SHIFT)) & PXP_CTRL_CLR_VFLIP_MASK) +#define PXP_CTRL_CLR_RSVD1_MASK (0x3FF000U) +#define PXP_CTRL_CLR_RSVD1_SHIFT (12U) +#define PXP_CTRL_CLR_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_CLR_RSVD1_SHIFT)) & PXP_CTRL_CLR_RSVD1_MASK) +#define PXP_CTRL_CLR_ROT_POS_MASK (0x400000U) +#define PXP_CTRL_CLR_ROT_POS_SHIFT (22U) +#define PXP_CTRL_CLR_ROT_POS(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_CLR_ROT_POS_SHIFT)) & PXP_CTRL_CLR_ROT_POS_MASK) +#define PXP_CTRL_CLR_BLOCK_SIZE_MASK (0x800000U) +#define PXP_CTRL_CLR_BLOCK_SIZE_SHIFT (23U) +/*! BLOCK_SIZE + * 0b0..Process 8x8 pixel blocks. + * 0b1..Process 16x16 pixel blocks. + */ +#define PXP_CTRL_CLR_BLOCK_SIZE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_CLR_BLOCK_SIZE_SHIFT)) & PXP_CTRL_CLR_BLOCK_SIZE_MASK) +#define PXP_CTRL_CLR_RSVD3_MASK (0xF000000U) +#define PXP_CTRL_CLR_RSVD3_SHIFT (24U) +#define PXP_CTRL_CLR_RSVD3(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_CLR_RSVD3_SHIFT)) & PXP_CTRL_CLR_RSVD3_MASK) +#define PXP_CTRL_CLR_EN_REPEAT_MASK (0x10000000U) +#define PXP_CTRL_CLR_EN_REPEAT_SHIFT (28U) +#define PXP_CTRL_CLR_EN_REPEAT(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_CLR_EN_REPEAT_SHIFT)) & PXP_CTRL_CLR_EN_REPEAT_MASK) +#define PXP_CTRL_CLR_RSVD4_MASK (0x20000000U) +#define PXP_CTRL_CLR_RSVD4_SHIFT (29U) +#define PXP_CTRL_CLR_RSVD4(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_CLR_RSVD4_SHIFT)) & PXP_CTRL_CLR_RSVD4_MASK) +#define PXP_CTRL_CLR_CLKGATE_MASK (0x40000000U) +#define PXP_CTRL_CLR_CLKGATE_SHIFT (30U) +#define PXP_CTRL_CLR_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_CLR_CLKGATE_SHIFT)) & PXP_CTRL_CLR_CLKGATE_MASK) +#define PXP_CTRL_CLR_SFTRST_MASK (0x80000000U) +#define PXP_CTRL_CLR_SFTRST_SHIFT (31U) +#define PXP_CTRL_CLR_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_CLR_SFTRST_SHIFT)) & PXP_CTRL_CLR_SFTRST_MASK) +/*! @} */ + +/*! @name CTRL_TOG - Control Register 0 */ +/*! @{ */ +#define PXP_CTRL_TOG_ENABLE_MASK (0x1U) +#define PXP_CTRL_TOG_ENABLE_SHIFT (0U) +#define PXP_CTRL_TOG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_TOG_ENABLE_SHIFT)) & PXP_CTRL_TOG_ENABLE_MASK) +#define PXP_CTRL_TOG_IRQ_ENABLE_MASK (0x2U) +#define PXP_CTRL_TOG_IRQ_ENABLE_SHIFT (1U) +#define PXP_CTRL_TOG_IRQ_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_TOG_IRQ_ENABLE_SHIFT)) & PXP_CTRL_TOG_IRQ_ENABLE_MASK) +#define PXP_CTRL_TOG_NEXT_IRQ_ENABLE_MASK (0x4U) +#define PXP_CTRL_TOG_NEXT_IRQ_ENABLE_SHIFT (2U) +#define PXP_CTRL_TOG_NEXT_IRQ_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_TOG_NEXT_IRQ_ENABLE_SHIFT)) & PXP_CTRL_TOG_NEXT_IRQ_ENABLE_MASK) +#define PXP_CTRL_TOG_ENABLE_LCD_HANDSHAKE_MASK (0x10U) +#define PXP_CTRL_TOG_ENABLE_LCD_HANDSHAKE_SHIFT (4U) +#define PXP_CTRL_TOG_ENABLE_LCD_HANDSHAKE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_TOG_ENABLE_LCD_HANDSHAKE_SHIFT)) & PXP_CTRL_TOG_ENABLE_LCD_HANDSHAKE_MASK) +#define PXP_CTRL_TOG_RSVD0_MASK (0xE0U) +#define PXP_CTRL_TOG_RSVD0_SHIFT (5U) +#define PXP_CTRL_TOG_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_TOG_RSVD0_SHIFT)) & PXP_CTRL_TOG_RSVD0_MASK) +#define PXP_CTRL_TOG_ROTATE_MASK (0x300U) +#define PXP_CTRL_TOG_ROTATE_SHIFT (8U) +/*! ROTATE + * 0b00..ROT_0 + * 0b01..ROT_90 + * 0b10..ROT_180 + * 0b11..ROT_270 + */ +#define PXP_CTRL_TOG_ROTATE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_TOG_ROTATE_SHIFT)) & PXP_CTRL_TOG_ROTATE_MASK) +#define PXP_CTRL_TOG_HFLIP_MASK (0x400U) +#define PXP_CTRL_TOG_HFLIP_SHIFT (10U) +#define PXP_CTRL_TOG_HFLIP(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_TOG_HFLIP_SHIFT)) & PXP_CTRL_TOG_HFLIP_MASK) +#define PXP_CTRL_TOG_VFLIP_MASK (0x800U) +#define PXP_CTRL_TOG_VFLIP_SHIFT (11U) +#define PXP_CTRL_TOG_VFLIP(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_TOG_VFLIP_SHIFT)) & PXP_CTRL_TOG_VFLIP_MASK) +#define PXP_CTRL_TOG_RSVD1_MASK (0x3FF000U) +#define PXP_CTRL_TOG_RSVD1_SHIFT (12U) +#define PXP_CTRL_TOG_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_TOG_RSVD1_SHIFT)) & PXP_CTRL_TOG_RSVD1_MASK) +#define PXP_CTRL_TOG_ROT_POS_MASK (0x400000U) +#define PXP_CTRL_TOG_ROT_POS_SHIFT (22U) +#define PXP_CTRL_TOG_ROT_POS(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_TOG_ROT_POS_SHIFT)) & PXP_CTRL_TOG_ROT_POS_MASK) +#define PXP_CTRL_TOG_BLOCK_SIZE_MASK (0x800000U) +#define PXP_CTRL_TOG_BLOCK_SIZE_SHIFT (23U) +/*! BLOCK_SIZE + * 0b0..Process 8x8 pixel blocks. + * 0b1..Process 16x16 pixel blocks. + */ +#define PXP_CTRL_TOG_BLOCK_SIZE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_TOG_BLOCK_SIZE_SHIFT)) & PXP_CTRL_TOG_BLOCK_SIZE_MASK) +#define PXP_CTRL_TOG_RSVD3_MASK (0xF000000U) +#define PXP_CTRL_TOG_RSVD3_SHIFT (24U) +#define PXP_CTRL_TOG_RSVD3(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_TOG_RSVD3_SHIFT)) & PXP_CTRL_TOG_RSVD3_MASK) +#define PXP_CTRL_TOG_EN_REPEAT_MASK (0x10000000U) +#define PXP_CTRL_TOG_EN_REPEAT_SHIFT (28U) +#define PXP_CTRL_TOG_EN_REPEAT(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_TOG_EN_REPEAT_SHIFT)) & PXP_CTRL_TOG_EN_REPEAT_MASK) +#define PXP_CTRL_TOG_RSVD4_MASK (0x20000000U) +#define PXP_CTRL_TOG_RSVD4_SHIFT (29U) +#define PXP_CTRL_TOG_RSVD4(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_TOG_RSVD4_SHIFT)) & PXP_CTRL_TOG_RSVD4_MASK) +#define PXP_CTRL_TOG_CLKGATE_MASK (0x40000000U) +#define PXP_CTRL_TOG_CLKGATE_SHIFT (30U) +#define PXP_CTRL_TOG_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_TOG_CLKGATE_SHIFT)) & PXP_CTRL_TOG_CLKGATE_MASK) +#define PXP_CTRL_TOG_SFTRST_MASK (0x80000000U) +#define PXP_CTRL_TOG_SFTRST_SHIFT (31U) +#define PXP_CTRL_TOG_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_TOG_SFTRST_SHIFT)) & PXP_CTRL_TOG_SFTRST_MASK) +/*! @} */ + +/*! @name STAT - Status Register */ +/*! @{ */ +#define PXP_STAT_IRQ_MASK (0x1U) +#define PXP_STAT_IRQ_SHIFT (0U) +#define PXP_STAT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_IRQ_SHIFT)) & PXP_STAT_IRQ_MASK) +#define PXP_STAT_AXI_WRITE_ERROR_MASK (0x2U) +#define PXP_STAT_AXI_WRITE_ERROR_SHIFT (1U) +#define PXP_STAT_AXI_WRITE_ERROR(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_AXI_WRITE_ERROR_SHIFT)) & PXP_STAT_AXI_WRITE_ERROR_MASK) +#define PXP_STAT_AXI_READ_ERROR_MASK (0x4U) +#define PXP_STAT_AXI_READ_ERROR_SHIFT (2U) +#define PXP_STAT_AXI_READ_ERROR(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_AXI_READ_ERROR_SHIFT)) & PXP_STAT_AXI_READ_ERROR_MASK) +#define PXP_STAT_NEXT_IRQ_MASK (0x8U) +#define PXP_STAT_NEXT_IRQ_SHIFT (3U) +#define PXP_STAT_NEXT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_NEXT_IRQ_SHIFT)) & PXP_STAT_NEXT_IRQ_MASK) +#define PXP_STAT_AXI_ERROR_ID_MASK (0xF0U) +#define PXP_STAT_AXI_ERROR_ID_SHIFT (4U) +#define PXP_STAT_AXI_ERROR_ID(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_AXI_ERROR_ID_SHIFT)) & PXP_STAT_AXI_ERROR_ID_MASK) +#define PXP_STAT_LUT_DMA_LOAD_DONE_IRQ_MASK (0x100U) +#define PXP_STAT_LUT_DMA_LOAD_DONE_IRQ_SHIFT (8U) +#define PXP_STAT_LUT_DMA_LOAD_DONE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_LUT_DMA_LOAD_DONE_IRQ_SHIFT)) & PXP_STAT_LUT_DMA_LOAD_DONE_IRQ_MASK) +#define PXP_STAT_RSVD2_MASK (0xFE00U) +#define PXP_STAT_RSVD2_SHIFT (9U) +#define PXP_STAT_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_RSVD2_SHIFT)) & PXP_STAT_RSVD2_MASK) +#define PXP_STAT_BLOCKY_MASK (0xFF0000U) +#define PXP_STAT_BLOCKY_SHIFT (16U) +#define PXP_STAT_BLOCKY(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_BLOCKY_SHIFT)) & PXP_STAT_BLOCKY_MASK) +#define PXP_STAT_BLOCKX_MASK (0xFF000000U) +#define PXP_STAT_BLOCKX_SHIFT (24U) +#define PXP_STAT_BLOCKX(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_BLOCKX_SHIFT)) & PXP_STAT_BLOCKX_MASK) +/*! @} */ + +/*! @name STAT_SET - Status Register */ +/*! @{ */ +#define PXP_STAT_SET_IRQ_MASK (0x1U) +#define PXP_STAT_SET_IRQ_SHIFT (0U) +#define PXP_STAT_SET_IRQ(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_SET_IRQ_SHIFT)) & PXP_STAT_SET_IRQ_MASK) +#define PXP_STAT_SET_AXI_WRITE_ERROR_MASK (0x2U) +#define PXP_STAT_SET_AXI_WRITE_ERROR_SHIFT (1U) +#define PXP_STAT_SET_AXI_WRITE_ERROR(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_SET_AXI_WRITE_ERROR_SHIFT)) & PXP_STAT_SET_AXI_WRITE_ERROR_MASK) +#define PXP_STAT_SET_AXI_READ_ERROR_MASK (0x4U) +#define PXP_STAT_SET_AXI_READ_ERROR_SHIFT (2U) +#define PXP_STAT_SET_AXI_READ_ERROR(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_SET_AXI_READ_ERROR_SHIFT)) & PXP_STAT_SET_AXI_READ_ERROR_MASK) +#define PXP_STAT_SET_NEXT_IRQ_MASK (0x8U) +#define PXP_STAT_SET_NEXT_IRQ_SHIFT (3U) +#define PXP_STAT_SET_NEXT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_SET_NEXT_IRQ_SHIFT)) & PXP_STAT_SET_NEXT_IRQ_MASK) +#define PXP_STAT_SET_AXI_ERROR_ID_MASK (0xF0U) +#define PXP_STAT_SET_AXI_ERROR_ID_SHIFT (4U) +#define PXP_STAT_SET_AXI_ERROR_ID(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_SET_AXI_ERROR_ID_SHIFT)) & PXP_STAT_SET_AXI_ERROR_ID_MASK) +#define PXP_STAT_SET_LUT_DMA_LOAD_DONE_IRQ_MASK (0x100U) +#define PXP_STAT_SET_LUT_DMA_LOAD_DONE_IRQ_SHIFT (8U) +#define PXP_STAT_SET_LUT_DMA_LOAD_DONE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_SET_LUT_DMA_LOAD_DONE_IRQ_SHIFT)) & PXP_STAT_SET_LUT_DMA_LOAD_DONE_IRQ_MASK) +#define PXP_STAT_SET_RSVD2_MASK (0xFE00U) +#define PXP_STAT_SET_RSVD2_SHIFT (9U) +#define PXP_STAT_SET_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_SET_RSVD2_SHIFT)) & PXP_STAT_SET_RSVD2_MASK) +#define PXP_STAT_SET_BLOCKY_MASK (0xFF0000U) +#define PXP_STAT_SET_BLOCKY_SHIFT (16U) +#define PXP_STAT_SET_BLOCKY(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_SET_BLOCKY_SHIFT)) & PXP_STAT_SET_BLOCKY_MASK) +#define PXP_STAT_SET_BLOCKX_MASK (0xFF000000U) +#define PXP_STAT_SET_BLOCKX_SHIFT (24U) +#define PXP_STAT_SET_BLOCKX(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_SET_BLOCKX_SHIFT)) & PXP_STAT_SET_BLOCKX_MASK) +/*! @} */ + +/*! @name STAT_CLR - Status Register */ +/*! @{ */ +#define PXP_STAT_CLR_IRQ_MASK (0x1U) +#define PXP_STAT_CLR_IRQ_SHIFT (0U) +#define PXP_STAT_CLR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_CLR_IRQ_SHIFT)) & PXP_STAT_CLR_IRQ_MASK) +#define PXP_STAT_CLR_AXI_WRITE_ERROR_MASK (0x2U) +#define PXP_STAT_CLR_AXI_WRITE_ERROR_SHIFT (1U) +#define PXP_STAT_CLR_AXI_WRITE_ERROR(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_CLR_AXI_WRITE_ERROR_SHIFT)) & PXP_STAT_CLR_AXI_WRITE_ERROR_MASK) +#define PXP_STAT_CLR_AXI_READ_ERROR_MASK (0x4U) +#define PXP_STAT_CLR_AXI_READ_ERROR_SHIFT (2U) +#define PXP_STAT_CLR_AXI_READ_ERROR(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_CLR_AXI_READ_ERROR_SHIFT)) & PXP_STAT_CLR_AXI_READ_ERROR_MASK) +#define PXP_STAT_CLR_NEXT_IRQ_MASK (0x8U) +#define PXP_STAT_CLR_NEXT_IRQ_SHIFT (3U) +#define PXP_STAT_CLR_NEXT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_CLR_NEXT_IRQ_SHIFT)) & PXP_STAT_CLR_NEXT_IRQ_MASK) +#define PXP_STAT_CLR_AXI_ERROR_ID_MASK (0xF0U) +#define PXP_STAT_CLR_AXI_ERROR_ID_SHIFT (4U) +#define PXP_STAT_CLR_AXI_ERROR_ID(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_CLR_AXI_ERROR_ID_SHIFT)) & PXP_STAT_CLR_AXI_ERROR_ID_MASK) +#define PXP_STAT_CLR_LUT_DMA_LOAD_DONE_IRQ_MASK (0x100U) +#define PXP_STAT_CLR_LUT_DMA_LOAD_DONE_IRQ_SHIFT (8U) +#define PXP_STAT_CLR_LUT_DMA_LOAD_DONE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_CLR_LUT_DMA_LOAD_DONE_IRQ_SHIFT)) & PXP_STAT_CLR_LUT_DMA_LOAD_DONE_IRQ_MASK) +#define PXP_STAT_CLR_RSVD2_MASK (0xFE00U) +#define PXP_STAT_CLR_RSVD2_SHIFT (9U) +#define PXP_STAT_CLR_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_CLR_RSVD2_SHIFT)) & PXP_STAT_CLR_RSVD2_MASK) +#define PXP_STAT_CLR_BLOCKY_MASK (0xFF0000U) +#define PXP_STAT_CLR_BLOCKY_SHIFT (16U) +#define PXP_STAT_CLR_BLOCKY(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_CLR_BLOCKY_SHIFT)) & PXP_STAT_CLR_BLOCKY_MASK) +#define PXP_STAT_CLR_BLOCKX_MASK (0xFF000000U) +#define PXP_STAT_CLR_BLOCKX_SHIFT (24U) +#define PXP_STAT_CLR_BLOCKX(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_CLR_BLOCKX_SHIFT)) & PXP_STAT_CLR_BLOCKX_MASK) +/*! @} */ + +/*! @name STAT_TOG - Status Register */ +/*! @{ */ +#define PXP_STAT_TOG_IRQ_MASK (0x1U) +#define PXP_STAT_TOG_IRQ_SHIFT (0U) +#define PXP_STAT_TOG_IRQ(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_TOG_IRQ_SHIFT)) & PXP_STAT_TOG_IRQ_MASK) +#define PXP_STAT_TOG_AXI_WRITE_ERROR_MASK (0x2U) +#define PXP_STAT_TOG_AXI_WRITE_ERROR_SHIFT (1U) +#define PXP_STAT_TOG_AXI_WRITE_ERROR(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_TOG_AXI_WRITE_ERROR_SHIFT)) & PXP_STAT_TOG_AXI_WRITE_ERROR_MASK) +#define PXP_STAT_TOG_AXI_READ_ERROR_MASK (0x4U) +#define PXP_STAT_TOG_AXI_READ_ERROR_SHIFT (2U) +#define PXP_STAT_TOG_AXI_READ_ERROR(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_TOG_AXI_READ_ERROR_SHIFT)) & PXP_STAT_TOG_AXI_READ_ERROR_MASK) +#define PXP_STAT_TOG_NEXT_IRQ_MASK (0x8U) +#define PXP_STAT_TOG_NEXT_IRQ_SHIFT (3U) +#define PXP_STAT_TOG_NEXT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_TOG_NEXT_IRQ_SHIFT)) & PXP_STAT_TOG_NEXT_IRQ_MASK) +#define PXP_STAT_TOG_AXI_ERROR_ID_MASK (0xF0U) +#define PXP_STAT_TOG_AXI_ERROR_ID_SHIFT (4U) +#define PXP_STAT_TOG_AXI_ERROR_ID(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_TOG_AXI_ERROR_ID_SHIFT)) & PXP_STAT_TOG_AXI_ERROR_ID_MASK) +#define PXP_STAT_TOG_LUT_DMA_LOAD_DONE_IRQ_MASK (0x100U) +#define PXP_STAT_TOG_LUT_DMA_LOAD_DONE_IRQ_SHIFT (8U) +#define PXP_STAT_TOG_LUT_DMA_LOAD_DONE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_TOG_LUT_DMA_LOAD_DONE_IRQ_SHIFT)) & PXP_STAT_TOG_LUT_DMA_LOAD_DONE_IRQ_MASK) +#define PXP_STAT_TOG_RSVD2_MASK (0xFE00U) +#define PXP_STAT_TOG_RSVD2_SHIFT (9U) +#define PXP_STAT_TOG_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_TOG_RSVD2_SHIFT)) & PXP_STAT_TOG_RSVD2_MASK) +#define PXP_STAT_TOG_BLOCKY_MASK (0xFF0000U) +#define PXP_STAT_TOG_BLOCKY_SHIFT (16U) +#define PXP_STAT_TOG_BLOCKY(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_TOG_BLOCKY_SHIFT)) & PXP_STAT_TOG_BLOCKY_MASK) +#define PXP_STAT_TOG_BLOCKX_MASK (0xFF000000U) +#define PXP_STAT_TOG_BLOCKX_SHIFT (24U) +#define PXP_STAT_TOG_BLOCKX(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_TOG_BLOCKX_SHIFT)) & PXP_STAT_TOG_BLOCKX_MASK) +/*! @} */ + +/*! @name OUT_CTRL - Output Buffer Control Register */ +/*! @{ */ +#define PXP_OUT_CTRL_FORMAT_MASK (0x1FU) +#define PXP_OUT_CTRL_FORMAT_SHIFT (0U) +/*! FORMAT + * 0b00000..32-bit pixels + * 0b00100..32-bit pixels (unpacked 24-bit pixel in 32 bit DWORD.) + * 0b00101..24-bit pixels (packed 24-bit format) + * 0b01000..16-bit pixels + * 0b01001..16-bit pixels + * 0b01100..16-bit pixels + * 0b01101..16-bit pixels + * 0b01110..16-bit pixels + * 0b10000..32-bit pixels (1-plane XYUV unpacked) + * 0b10010..16-bit pixels (1-plane U0,Y0,V0,Y1 interleaved bytes) + * 0b10011..16-bit pixels (1-plane V0,Y0,U0,Y1 interleaved bytes) + * 0b10100..8-bit monochrome pixels (1-plane Y luma output) + * 0b10101..4-bit monochrome pixels (1-plane Y luma, 4 bit truncation) + * 0b11000..16-bit pixels (2-plane UV interleaved bytes) + * 0b11001..16-bit pixels (2-plane UV) + * 0b11010..16-bit pixels (2-plane VU interleaved bytes) + * 0b11011..16-bit pixels (2-plane VU) + */ +#define PXP_OUT_CTRL_FORMAT(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_FORMAT_SHIFT)) & PXP_OUT_CTRL_FORMAT_MASK) +#define PXP_OUT_CTRL_RSVD0_MASK (0xE0U) +#define PXP_OUT_CTRL_RSVD0_SHIFT (5U) +#define PXP_OUT_CTRL_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_RSVD0_SHIFT)) & PXP_OUT_CTRL_RSVD0_MASK) +#define PXP_OUT_CTRL_INTERLACED_OUTPUT_MASK (0x300U) +#define PXP_OUT_CTRL_INTERLACED_OUTPUT_SHIFT (8U) +/*! INTERLACED_OUTPUT + * 0b00..All data written in progressive format to the OUTBUF Pointer. + * 0b01..Interlaced output: only data for field 0 is written to the OUTBUF Pointer. + * 0b10..Interlaced output: only data for field 1 is written to the OUTBUF2 Pointer. + * 0b11..Interlaced output: data for field 0 is written to OUTBUF and data for field 1 is written to OUTBUF2. + */ +#define PXP_OUT_CTRL_INTERLACED_OUTPUT(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_INTERLACED_OUTPUT_SHIFT)) & PXP_OUT_CTRL_INTERLACED_OUTPUT_MASK) +#define PXP_OUT_CTRL_RSVD1_MASK (0x7FFC00U) +#define PXP_OUT_CTRL_RSVD1_SHIFT (10U) +#define PXP_OUT_CTRL_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_RSVD1_SHIFT)) & PXP_OUT_CTRL_RSVD1_MASK) +#define PXP_OUT_CTRL_ALPHA_OUTPUT_MASK (0x800000U) +#define PXP_OUT_CTRL_ALPHA_OUTPUT_SHIFT (23U) +#define PXP_OUT_CTRL_ALPHA_OUTPUT(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_ALPHA_OUTPUT_SHIFT)) & PXP_OUT_CTRL_ALPHA_OUTPUT_MASK) +#define PXP_OUT_CTRL_ALPHA_MASK (0xFF000000U) +#define PXP_OUT_CTRL_ALPHA_SHIFT (24U) +#define PXP_OUT_CTRL_ALPHA(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_ALPHA_SHIFT)) & PXP_OUT_CTRL_ALPHA_MASK) +/*! @} */ + +/*! @name OUT_CTRL_SET - Output Buffer Control Register */ +/*! @{ */ +#define PXP_OUT_CTRL_SET_FORMAT_MASK (0x1FU) +#define PXP_OUT_CTRL_SET_FORMAT_SHIFT (0U) +/*! FORMAT + * 0b00000..32-bit pixels + * 0b00100..32-bit pixels (unpacked 24-bit pixel in 32 bit DWORD.) + * 0b00101..24-bit pixels (packed 24-bit format) + * 0b01000..16-bit pixels + * 0b01001..16-bit pixels + * 0b01100..16-bit pixels + * 0b01101..16-bit pixels + * 0b01110..16-bit pixels + * 0b10000..32-bit pixels (1-plane XYUV unpacked) + * 0b10010..16-bit pixels (1-plane U0,Y0,V0,Y1 interleaved bytes) + * 0b10011..16-bit pixels (1-plane V0,Y0,U0,Y1 interleaved bytes) + * 0b10100..8-bit monochrome pixels (1-plane Y luma output) + * 0b10101..4-bit monochrome pixels (1-plane Y luma, 4 bit truncation) + * 0b11000..16-bit pixels (2-plane UV interleaved bytes) + * 0b11001..16-bit pixels (2-plane UV) + * 0b11010..16-bit pixels (2-plane VU interleaved bytes) + * 0b11011..16-bit pixels (2-plane VU) + */ +#define PXP_OUT_CTRL_SET_FORMAT(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_SET_FORMAT_SHIFT)) & PXP_OUT_CTRL_SET_FORMAT_MASK) +#define PXP_OUT_CTRL_SET_RSVD0_MASK (0xE0U) +#define PXP_OUT_CTRL_SET_RSVD0_SHIFT (5U) +#define PXP_OUT_CTRL_SET_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_SET_RSVD0_SHIFT)) & PXP_OUT_CTRL_SET_RSVD0_MASK) +#define PXP_OUT_CTRL_SET_INTERLACED_OUTPUT_MASK (0x300U) +#define PXP_OUT_CTRL_SET_INTERLACED_OUTPUT_SHIFT (8U) +/*! INTERLACED_OUTPUT + * 0b00..All data written in progressive format to the OUTBUF Pointer. + * 0b01..Interlaced output: only data for field 0 is written to the OUTBUF Pointer. + * 0b10..Interlaced output: only data for field 1 is written to the OUTBUF2 Pointer. + * 0b11..Interlaced output: data for field 0 is written to OUTBUF and data for field 1 is written to OUTBUF2. + */ +#define PXP_OUT_CTRL_SET_INTERLACED_OUTPUT(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_SET_INTERLACED_OUTPUT_SHIFT)) & PXP_OUT_CTRL_SET_INTERLACED_OUTPUT_MASK) +#define PXP_OUT_CTRL_SET_RSVD1_MASK (0x7FFC00U) +#define PXP_OUT_CTRL_SET_RSVD1_SHIFT (10U) +#define PXP_OUT_CTRL_SET_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_SET_RSVD1_SHIFT)) & PXP_OUT_CTRL_SET_RSVD1_MASK) +#define PXP_OUT_CTRL_SET_ALPHA_OUTPUT_MASK (0x800000U) +#define PXP_OUT_CTRL_SET_ALPHA_OUTPUT_SHIFT (23U) +#define PXP_OUT_CTRL_SET_ALPHA_OUTPUT(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_SET_ALPHA_OUTPUT_SHIFT)) & PXP_OUT_CTRL_SET_ALPHA_OUTPUT_MASK) +#define PXP_OUT_CTRL_SET_ALPHA_MASK (0xFF000000U) +#define PXP_OUT_CTRL_SET_ALPHA_SHIFT (24U) +#define PXP_OUT_CTRL_SET_ALPHA(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_SET_ALPHA_SHIFT)) & PXP_OUT_CTRL_SET_ALPHA_MASK) +/*! @} */ + +/*! @name OUT_CTRL_CLR - Output Buffer Control Register */ +/*! @{ */ +#define PXP_OUT_CTRL_CLR_FORMAT_MASK (0x1FU) +#define PXP_OUT_CTRL_CLR_FORMAT_SHIFT (0U) +/*! FORMAT + * 0b00000..32-bit pixels + * 0b00100..32-bit pixels (unpacked 24-bit pixel in 32 bit DWORD.) + * 0b00101..24-bit pixels (packed 24-bit format) + * 0b01000..16-bit pixels + * 0b01001..16-bit pixels + * 0b01100..16-bit pixels + * 0b01101..16-bit pixels + * 0b01110..16-bit pixels + * 0b10000..32-bit pixels (1-plane XYUV unpacked) + * 0b10010..16-bit pixels (1-plane U0,Y0,V0,Y1 interleaved bytes) + * 0b10011..16-bit pixels (1-plane V0,Y0,U0,Y1 interleaved bytes) + * 0b10100..8-bit monochrome pixels (1-plane Y luma output) + * 0b10101..4-bit monochrome pixels (1-plane Y luma, 4 bit truncation) + * 0b11000..16-bit pixels (2-plane UV interleaved bytes) + * 0b11001..16-bit pixels (2-plane UV) + * 0b11010..16-bit pixels (2-plane VU interleaved bytes) + * 0b11011..16-bit pixels (2-plane VU) + */ +#define PXP_OUT_CTRL_CLR_FORMAT(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_CLR_FORMAT_SHIFT)) & PXP_OUT_CTRL_CLR_FORMAT_MASK) +#define PXP_OUT_CTRL_CLR_RSVD0_MASK (0xE0U) +#define PXP_OUT_CTRL_CLR_RSVD0_SHIFT (5U) +#define PXP_OUT_CTRL_CLR_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_CLR_RSVD0_SHIFT)) & PXP_OUT_CTRL_CLR_RSVD0_MASK) +#define PXP_OUT_CTRL_CLR_INTERLACED_OUTPUT_MASK (0x300U) +#define PXP_OUT_CTRL_CLR_INTERLACED_OUTPUT_SHIFT (8U) +/*! INTERLACED_OUTPUT + * 0b00..All data written in progressive format to the OUTBUF Pointer. + * 0b01..Interlaced output: only data for field 0 is written to the OUTBUF Pointer. + * 0b10..Interlaced output: only data for field 1 is written to the OUTBUF2 Pointer. + * 0b11..Interlaced output: data for field 0 is written to OUTBUF and data for field 1 is written to OUTBUF2. + */ +#define PXP_OUT_CTRL_CLR_INTERLACED_OUTPUT(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_CLR_INTERLACED_OUTPUT_SHIFT)) & PXP_OUT_CTRL_CLR_INTERLACED_OUTPUT_MASK) +#define PXP_OUT_CTRL_CLR_RSVD1_MASK (0x7FFC00U) +#define PXP_OUT_CTRL_CLR_RSVD1_SHIFT (10U) +#define PXP_OUT_CTRL_CLR_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_CLR_RSVD1_SHIFT)) & PXP_OUT_CTRL_CLR_RSVD1_MASK) +#define PXP_OUT_CTRL_CLR_ALPHA_OUTPUT_MASK (0x800000U) +#define PXP_OUT_CTRL_CLR_ALPHA_OUTPUT_SHIFT (23U) +#define PXP_OUT_CTRL_CLR_ALPHA_OUTPUT(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_CLR_ALPHA_OUTPUT_SHIFT)) & PXP_OUT_CTRL_CLR_ALPHA_OUTPUT_MASK) +#define PXP_OUT_CTRL_CLR_ALPHA_MASK (0xFF000000U) +#define PXP_OUT_CTRL_CLR_ALPHA_SHIFT (24U) +#define PXP_OUT_CTRL_CLR_ALPHA(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_CLR_ALPHA_SHIFT)) & PXP_OUT_CTRL_CLR_ALPHA_MASK) +/*! @} */ + +/*! @name OUT_CTRL_TOG - Output Buffer Control Register */ +/*! @{ */ +#define PXP_OUT_CTRL_TOG_FORMAT_MASK (0x1FU) +#define PXP_OUT_CTRL_TOG_FORMAT_SHIFT (0U) +/*! FORMAT + * 0b00000..32-bit pixels + * 0b00100..32-bit pixels (unpacked 24-bit pixel in 32 bit DWORD.) + * 0b00101..24-bit pixels (packed 24-bit format) + * 0b01000..16-bit pixels + * 0b01001..16-bit pixels + * 0b01100..16-bit pixels + * 0b01101..16-bit pixels + * 0b01110..16-bit pixels + * 0b10000..32-bit pixels (1-plane XYUV unpacked) + * 0b10010..16-bit pixels (1-plane U0,Y0,V0,Y1 interleaved bytes) + * 0b10011..16-bit pixels (1-plane V0,Y0,U0,Y1 interleaved bytes) + * 0b10100..8-bit monochrome pixels (1-plane Y luma output) + * 0b10101..4-bit monochrome pixels (1-plane Y luma, 4 bit truncation) + * 0b11000..16-bit pixels (2-plane UV interleaved bytes) + * 0b11001..16-bit pixels (2-plane UV) + * 0b11010..16-bit pixels (2-plane VU interleaved bytes) + * 0b11011..16-bit pixels (2-plane VU) + */ +#define PXP_OUT_CTRL_TOG_FORMAT(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_TOG_FORMAT_SHIFT)) & PXP_OUT_CTRL_TOG_FORMAT_MASK) +#define PXP_OUT_CTRL_TOG_RSVD0_MASK (0xE0U) +#define PXP_OUT_CTRL_TOG_RSVD0_SHIFT (5U) +#define PXP_OUT_CTRL_TOG_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_TOG_RSVD0_SHIFT)) & PXP_OUT_CTRL_TOG_RSVD0_MASK) +#define PXP_OUT_CTRL_TOG_INTERLACED_OUTPUT_MASK (0x300U) +#define PXP_OUT_CTRL_TOG_INTERLACED_OUTPUT_SHIFT (8U) +/*! INTERLACED_OUTPUT + * 0b00..All data written in progressive format to the OUTBUF Pointer. + * 0b01..Interlaced output: only data for field 0 is written to the OUTBUF Pointer. + * 0b10..Interlaced output: only data for field 1 is written to the OUTBUF2 Pointer. + * 0b11..Interlaced output: data for field 0 is written to OUTBUF and data for field 1 is written to OUTBUF2. + */ +#define PXP_OUT_CTRL_TOG_INTERLACED_OUTPUT(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_TOG_INTERLACED_OUTPUT_SHIFT)) & PXP_OUT_CTRL_TOG_INTERLACED_OUTPUT_MASK) +#define PXP_OUT_CTRL_TOG_RSVD1_MASK (0x7FFC00U) +#define PXP_OUT_CTRL_TOG_RSVD1_SHIFT (10U) +#define PXP_OUT_CTRL_TOG_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_TOG_RSVD1_SHIFT)) & PXP_OUT_CTRL_TOG_RSVD1_MASK) +#define PXP_OUT_CTRL_TOG_ALPHA_OUTPUT_MASK (0x800000U) +#define PXP_OUT_CTRL_TOG_ALPHA_OUTPUT_SHIFT (23U) +#define PXP_OUT_CTRL_TOG_ALPHA_OUTPUT(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_TOG_ALPHA_OUTPUT_SHIFT)) & PXP_OUT_CTRL_TOG_ALPHA_OUTPUT_MASK) +#define PXP_OUT_CTRL_TOG_ALPHA_MASK (0xFF000000U) +#define PXP_OUT_CTRL_TOG_ALPHA_SHIFT (24U) +#define PXP_OUT_CTRL_TOG_ALPHA(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_TOG_ALPHA_SHIFT)) & PXP_OUT_CTRL_TOG_ALPHA_MASK) +/*! @} */ + +/*! @name OUT_BUF - Output Frame Buffer Pointer */ +/*! @{ */ +#define PXP_OUT_BUF_ADDR_MASK (0xFFFFFFFFU) +#define PXP_OUT_BUF_ADDR_SHIFT (0U) +#define PXP_OUT_BUF_ADDR(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_BUF_ADDR_SHIFT)) & PXP_OUT_BUF_ADDR_MASK) +/*! @} */ + +/*! @name OUT_BUF2 - Output Frame Buffer Pointer #2 */ +/*! @{ */ +#define PXP_OUT_BUF2_ADDR_MASK (0xFFFFFFFFU) +#define PXP_OUT_BUF2_ADDR_SHIFT (0U) +#define PXP_OUT_BUF2_ADDR(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_BUF2_ADDR_SHIFT)) & PXP_OUT_BUF2_ADDR_MASK) +/*! @} */ + +/*! @name OUT_PITCH - Output Buffer Pitch */ +/*! @{ */ +#define PXP_OUT_PITCH_PITCH_MASK (0xFFFFU) +#define PXP_OUT_PITCH_PITCH_SHIFT (0U) +#define PXP_OUT_PITCH_PITCH(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_PITCH_PITCH_SHIFT)) & PXP_OUT_PITCH_PITCH_MASK) +#define PXP_OUT_PITCH_RSVD_MASK (0xFFFF0000U) +#define PXP_OUT_PITCH_RSVD_SHIFT (16U) +#define PXP_OUT_PITCH_RSVD(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_PITCH_RSVD_SHIFT)) & PXP_OUT_PITCH_RSVD_MASK) +/*! @} */ + +/*! @name OUT_LRC - Output Surface Lower Right Coordinate */ +/*! @{ */ +#define PXP_OUT_LRC_Y_MASK (0x3FFFU) +#define PXP_OUT_LRC_Y_SHIFT (0U) +#define PXP_OUT_LRC_Y(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_LRC_Y_SHIFT)) & PXP_OUT_LRC_Y_MASK) +#define PXP_OUT_LRC_RSVD0_MASK (0xC000U) +#define PXP_OUT_LRC_RSVD0_SHIFT (14U) +#define PXP_OUT_LRC_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_LRC_RSVD0_SHIFT)) & PXP_OUT_LRC_RSVD0_MASK) +#define PXP_OUT_LRC_X_MASK (0x3FFF0000U) +#define PXP_OUT_LRC_X_SHIFT (16U) +#define PXP_OUT_LRC_X(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_LRC_X_SHIFT)) & PXP_OUT_LRC_X_MASK) +#define PXP_OUT_LRC_RSVD1_MASK (0xC0000000U) +#define PXP_OUT_LRC_RSVD1_SHIFT (30U) +#define PXP_OUT_LRC_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_LRC_RSVD1_SHIFT)) & PXP_OUT_LRC_RSVD1_MASK) +/*! @} */ + +/*! @name OUT_PS_ULC - Processed Surface Upper Left Coordinate */ +/*! @{ */ +#define PXP_OUT_PS_ULC_Y_MASK (0x3FFFU) +#define PXP_OUT_PS_ULC_Y_SHIFT (0U) +#define PXP_OUT_PS_ULC_Y(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_PS_ULC_Y_SHIFT)) & PXP_OUT_PS_ULC_Y_MASK) +#define PXP_OUT_PS_ULC_RSVD0_MASK (0xC000U) +#define PXP_OUT_PS_ULC_RSVD0_SHIFT (14U) +#define PXP_OUT_PS_ULC_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_PS_ULC_RSVD0_SHIFT)) & PXP_OUT_PS_ULC_RSVD0_MASK) +#define PXP_OUT_PS_ULC_X_MASK (0x3FFF0000U) +#define PXP_OUT_PS_ULC_X_SHIFT (16U) +#define PXP_OUT_PS_ULC_X(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_PS_ULC_X_SHIFT)) & PXP_OUT_PS_ULC_X_MASK) +#define PXP_OUT_PS_ULC_RSVD1_MASK (0xC0000000U) +#define PXP_OUT_PS_ULC_RSVD1_SHIFT (30U) +#define PXP_OUT_PS_ULC_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_PS_ULC_RSVD1_SHIFT)) & PXP_OUT_PS_ULC_RSVD1_MASK) +/*! @} */ + +/*! @name OUT_PS_LRC - Processed Surface Lower Right Coordinate */ +/*! @{ */ +#define PXP_OUT_PS_LRC_Y_MASK (0x3FFFU) +#define PXP_OUT_PS_LRC_Y_SHIFT (0U) +#define PXP_OUT_PS_LRC_Y(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_PS_LRC_Y_SHIFT)) & PXP_OUT_PS_LRC_Y_MASK) +#define PXP_OUT_PS_LRC_RSVD0_MASK (0xC000U) +#define PXP_OUT_PS_LRC_RSVD0_SHIFT (14U) +#define PXP_OUT_PS_LRC_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_PS_LRC_RSVD0_SHIFT)) & PXP_OUT_PS_LRC_RSVD0_MASK) +#define PXP_OUT_PS_LRC_X_MASK (0x3FFF0000U) +#define PXP_OUT_PS_LRC_X_SHIFT (16U) +#define PXP_OUT_PS_LRC_X(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_PS_LRC_X_SHIFT)) & PXP_OUT_PS_LRC_X_MASK) +#define PXP_OUT_PS_LRC_RSVD1_MASK (0xC0000000U) +#define PXP_OUT_PS_LRC_RSVD1_SHIFT (30U) +#define PXP_OUT_PS_LRC_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_PS_LRC_RSVD1_SHIFT)) & PXP_OUT_PS_LRC_RSVD1_MASK) +/*! @} */ + +/*! @name OUT_AS_ULC - Alpha Surface Upper Left Coordinate */ +/*! @{ */ +#define PXP_OUT_AS_ULC_Y_MASK (0x3FFFU) +#define PXP_OUT_AS_ULC_Y_SHIFT (0U) +#define PXP_OUT_AS_ULC_Y(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_AS_ULC_Y_SHIFT)) & PXP_OUT_AS_ULC_Y_MASK) +#define PXP_OUT_AS_ULC_RSVD0_MASK (0xC000U) +#define PXP_OUT_AS_ULC_RSVD0_SHIFT (14U) +#define PXP_OUT_AS_ULC_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_AS_ULC_RSVD0_SHIFT)) & PXP_OUT_AS_ULC_RSVD0_MASK) +#define PXP_OUT_AS_ULC_X_MASK (0x3FFF0000U) +#define PXP_OUT_AS_ULC_X_SHIFT (16U) +#define PXP_OUT_AS_ULC_X(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_AS_ULC_X_SHIFT)) & PXP_OUT_AS_ULC_X_MASK) +#define PXP_OUT_AS_ULC_RSVD1_MASK (0xC0000000U) +#define PXP_OUT_AS_ULC_RSVD1_SHIFT (30U) +#define PXP_OUT_AS_ULC_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_AS_ULC_RSVD1_SHIFT)) & PXP_OUT_AS_ULC_RSVD1_MASK) +/*! @} */ + +/*! @name OUT_AS_LRC - Alpha Surface Lower Right Coordinate */ +/*! @{ */ +#define PXP_OUT_AS_LRC_Y_MASK (0x3FFFU) +#define PXP_OUT_AS_LRC_Y_SHIFT (0U) +#define PXP_OUT_AS_LRC_Y(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_AS_LRC_Y_SHIFT)) & PXP_OUT_AS_LRC_Y_MASK) +#define PXP_OUT_AS_LRC_RSVD0_MASK (0xC000U) +#define PXP_OUT_AS_LRC_RSVD0_SHIFT (14U) +#define PXP_OUT_AS_LRC_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_AS_LRC_RSVD0_SHIFT)) & PXP_OUT_AS_LRC_RSVD0_MASK) +#define PXP_OUT_AS_LRC_X_MASK (0x3FFF0000U) +#define PXP_OUT_AS_LRC_X_SHIFT (16U) +#define PXP_OUT_AS_LRC_X(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_AS_LRC_X_SHIFT)) & PXP_OUT_AS_LRC_X_MASK) +#define PXP_OUT_AS_LRC_RSVD1_MASK (0xC0000000U) +#define PXP_OUT_AS_LRC_RSVD1_SHIFT (30U) +#define PXP_OUT_AS_LRC_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_AS_LRC_RSVD1_SHIFT)) & PXP_OUT_AS_LRC_RSVD1_MASK) +/*! @} */ + +/*! @name PS_CTRL - Processed Surface (PS) Control Register */ +/*! @{ */ +#define PXP_PS_CTRL_FORMAT_MASK (0x1FU) +#define PXP_PS_CTRL_FORMAT_SHIFT (0U) +/*! FORMAT + * 0b00100..32-bit pixels (unpacked 24-bit format) + * 0b01100..16-bit pixels + * 0b01101..16-bit pixels + * 0b01110..16-bit pixels + * 0b10000..32-bit pixels (1-plane XYUV unpacked) + * 0b10010..16-bit pixels (1-plane U0,Y0,V0,Y1 interleaved bytes) + * 0b10011..16-bit pixels (1-plane V0,Y0,U0,Y1 interleaved bytes) + * 0b10100..8-bit monochrome pixels (1-plane Y luma output) + * 0b10101..4-bit monochrome pixels (1-plane Y luma, 4 bit truncation) + * 0b11000..16-bit pixels (2-plane UV interleaved bytes) + * 0b11001..16-bit pixels (2-plane UV) + * 0b11010..16-bit pixels (2-plane VU interleaved bytes) + * 0b11011..16-bit pixels (2-plane VU) + * 0b11110..16-bit pixels (3-plane format) + * 0b11111..16-bit pixels (3-plane format) + */ +#define PXP_PS_CTRL_FORMAT(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_FORMAT_SHIFT)) & PXP_PS_CTRL_FORMAT_MASK) +#define PXP_PS_CTRL_WB_SWAP_MASK (0x20U) +#define PXP_PS_CTRL_WB_SWAP_SHIFT (5U) +#define PXP_PS_CTRL_WB_SWAP(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_WB_SWAP_SHIFT)) & PXP_PS_CTRL_WB_SWAP_MASK) +#define PXP_PS_CTRL_RSVD0_MASK (0xC0U) +#define PXP_PS_CTRL_RSVD0_SHIFT (6U) +#define PXP_PS_CTRL_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_RSVD0_SHIFT)) & PXP_PS_CTRL_RSVD0_MASK) +#define PXP_PS_CTRL_DECY_MASK (0x300U) +#define PXP_PS_CTRL_DECY_SHIFT (8U) +/*! DECY + * 0b00..Disable pre-decimation filter. + * 0b01..Decimate PS by 2. + * 0b10..Decimate PS by 4. + * 0b11..Decimate PS by 8. + */ +#define PXP_PS_CTRL_DECY(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_DECY_SHIFT)) & PXP_PS_CTRL_DECY_MASK) +#define PXP_PS_CTRL_DECX_MASK (0xC00U) +#define PXP_PS_CTRL_DECX_SHIFT (10U) +/*! DECX + * 0b00..Disable pre-decimation filter. + * 0b01..Decimate PS by 2. + * 0b10..Decimate PS by 4. + * 0b11..Decimate PS by 8. + */ +#define PXP_PS_CTRL_DECX(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_DECX_SHIFT)) & PXP_PS_CTRL_DECX_MASK) +#define PXP_PS_CTRL_RSVD1_MASK (0xFFFFF000U) +#define PXP_PS_CTRL_RSVD1_SHIFT (12U) +#define PXP_PS_CTRL_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_RSVD1_SHIFT)) & PXP_PS_CTRL_RSVD1_MASK) +/*! @} */ + +/*! @name PS_CTRL_SET - Processed Surface (PS) Control Register */ +/*! @{ */ +#define PXP_PS_CTRL_SET_FORMAT_MASK (0x1FU) +#define PXP_PS_CTRL_SET_FORMAT_SHIFT (0U) +/*! FORMAT + * 0b00100..32-bit pixels (unpacked 24-bit format) + * 0b01100..16-bit pixels + * 0b01101..16-bit pixels + * 0b01110..16-bit pixels + * 0b10000..32-bit pixels (1-plane XYUV unpacked) + * 0b10010..16-bit pixels (1-plane U0,Y0,V0,Y1 interleaved bytes) + * 0b10011..16-bit pixels (1-plane V0,Y0,U0,Y1 interleaved bytes) + * 0b10100..8-bit monochrome pixels (1-plane Y luma output) + * 0b10101..4-bit monochrome pixels (1-plane Y luma, 4 bit truncation) + * 0b11000..16-bit pixels (2-plane UV interleaved bytes) + * 0b11001..16-bit pixels (2-plane UV) + * 0b11010..16-bit pixels (2-plane VU interleaved bytes) + * 0b11011..16-bit pixels (2-plane VU) + * 0b11110..16-bit pixels (3-plane format) + * 0b11111..16-bit pixels (3-plane format) + */ +#define PXP_PS_CTRL_SET_FORMAT(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_SET_FORMAT_SHIFT)) & PXP_PS_CTRL_SET_FORMAT_MASK) +#define PXP_PS_CTRL_SET_WB_SWAP_MASK (0x20U) +#define PXP_PS_CTRL_SET_WB_SWAP_SHIFT (5U) +#define PXP_PS_CTRL_SET_WB_SWAP(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_SET_WB_SWAP_SHIFT)) & PXP_PS_CTRL_SET_WB_SWAP_MASK) +#define PXP_PS_CTRL_SET_RSVD0_MASK (0xC0U) +#define PXP_PS_CTRL_SET_RSVD0_SHIFT (6U) +#define PXP_PS_CTRL_SET_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_SET_RSVD0_SHIFT)) & PXP_PS_CTRL_SET_RSVD0_MASK) +#define PXP_PS_CTRL_SET_DECY_MASK (0x300U) +#define PXP_PS_CTRL_SET_DECY_SHIFT (8U) +/*! DECY + * 0b00..Disable pre-decimation filter. + * 0b01..Decimate PS by 2. + * 0b10..Decimate PS by 4. + * 0b11..Decimate PS by 8. + */ +#define PXP_PS_CTRL_SET_DECY(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_SET_DECY_SHIFT)) & PXP_PS_CTRL_SET_DECY_MASK) +#define PXP_PS_CTRL_SET_DECX_MASK (0xC00U) +#define PXP_PS_CTRL_SET_DECX_SHIFT (10U) +/*! DECX + * 0b00..Disable pre-decimation filter. + * 0b01..Decimate PS by 2. + * 0b10..Decimate PS by 4. + * 0b11..Decimate PS by 8. + */ +#define PXP_PS_CTRL_SET_DECX(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_SET_DECX_SHIFT)) & PXP_PS_CTRL_SET_DECX_MASK) +#define PXP_PS_CTRL_SET_RSVD1_MASK (0xFFFFF000U) +#define PXP_PS_CTRL_SET_RSVD1_SHIFT (12U) +#define PXP_PS_CTRL_SET_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_SET_RSVD1_SHIFT)) & PXP_PS_CTRL_SET_RSVD1_MASK) +/*! @} */ + +/*! @name PS_CTRL_CLR - Processed Surface (PS) Control Register */ +/*! @{ */ +#define PXP_PS_CTRL_CLR_FORMAT_MASK (0x1FU) +#define PXP_PS_CTRL_CLR_FORMAT_SHIFT (0U) +/*! FORMAT + * 0b00100..32-bit pixels (unpacked 24-bit format) + * 0b01100..16-bit pixels + * 0b01101..16-bit pixels + * 0b01110..16-bit pixels + * 0b10000..32-bit pixels (1-plane XYUV unpacked) + * 0b10010..16-bit pixels (1-plane U0,Y0,V0,Y1 interleaved bytes) + * 0b10011..16-bit pixels (1-plane V0,Y0,U0,Y1 interleaved bytes) + * 0b10100..8-bit monochrome pixels (1-plane Y luma output) + * 0b10101..4-bit monochrome pixels (1-plane Y luma, 4 bit truncation) + * 0b11000..16-bit pixels (2-plane UV interleaved bytes) + * 0b11001..16-bit pixels (2-plane UV) + * 0b11010..16-bit pixels (2-plane VU interleaved bytes) + * 0b11011..16-bit pixels (2-plane VU) + * 0b11110..16-bit pixels (3-plane format) + * 0b11111..16-bit pixels (3-plane format) + */ +#define PXP_PS_CTRL_CLR_FORMAT(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_CLR_FORMAT_SHIFT)) & PXP_PS_CTRL_CLR_FORMAT_MASK) +#define PXP_PS_CTRL_CLR_WB_SWAP_MASK (0x20U) +#define PXP_PS_CTRL_CLR_WB_SWAP_SHIFT (5U) +#define PXP_PS_CTRL_CLR_WB_SWAP(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_CLR_WB_SWAP_SHIFT)) & PXP_PS_CTRL_CLR_WB_SWAP_MASK) +#define PXP_PS_CTRL_CLR_RSVD0_MASK (0xC0U) +#define PXP_PS_CTRL_CLR_RSVD0_SHIFT (6U) +#define PXP_PS_CTRL_CLR_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_CLR_RSVD0_SHIFT)) & PXP_PS_CTRL_CLR_RSVD0_MASK) +#define PXP_PS_CTRL_CLR_DECY_MASK (0x300U) +#define PXP_PS_CTRL_CLR_DECY_SHIFT (8U) +/*! DECY + * 0b00..Disable pre-decimation filter. + * 0b01..Decimate PS by 2. + * 0b10..Decimate PS by 4. + * 0b11..Decimate PS by 8. + */ +#define PXP_PS_CTRL_CLR_DECY(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_CLR_DECY_SHIFT)) & PXP_PS_CTRL_CLR_DECY_MASK) +#define PXP_PS_CTRL_CLR_DECX_MASK (0xC00U) +#define PXP_PS_CTRL_CLR_DECX_SHIFT (10U) +/*! DECX + * 0b00..Disable pre-decimation filter. + * 0b01..Decimate PS by 2. + * 0b10..Decimate PS by 4. + * 0b11..Decimate PS by 8. + */ +#define PXP_PS_CTRL_CLR_DECX(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_CLR_DECX_SHIFT)) & PXP_PS_CTRL_CLR_DECX_MASK) +#define PXP_PS_CTRL_CLR_RSVD1_MASK (0xFFFFF000U) +#define PXP_PS_CTRL_CLR_RSVD1_SHIFT (12U) +#define PXP_PS_CTRL_CLR_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_CLR_RSVD1_SHIFT)) & PXP_PS_CTRL_CLR_RSVD1_MASK) +/*! @} */ + +/*! @name PS_CTRL_TOG - Processed Surface (PS) Control Register */ +/*! @{ */ +#define PXP_PS_CTRL_TOG_FORMAT_MASK (0x1FU) +#define PXP_PS_CTRL_TOG_FORMAT_SHIFT (0U) +/*! FORMAT + * 0b00100..32-bit pixels (unpacked 24-bit format) + * 0b01100..16-bit pixels + * 0b01101..16-bit pixels + * 0b01110..16-bit pixels + * 0b10000..32-bit pixels (1-plane XYUV unpacked) + * 0b10010..16-bit pixels (1-plane U0,Y0,V0,Y1 interleaved bytes) + * 0b10011..16-bit pixels (1-plane V0,Y0,U0,Y1 interleaved bytes) + * 0b10100..8-bit monochrome pixels (1-plane Y luma output) + * 0b10101..4-bit monochrome pixels (1-plane Y luma, 4 bit truncation) + * 0b11000..16-bit pixels (2-plane UV interleaved bytes) + * 0b11001..16-bit pixels (2-plane UV) + * 0b11010..16-bit pixels (2-plane VU interleaved bytes) + * 0b11011..16-bit pixels (2-plane VU) + * 0b11110..16-bit pixels (3-plane format) + * 0b11111..16-bit pixels (3-plane format) + */ +#define PXP_PS_CTRL_TOG_FORMAT(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_TOG_FORMAT_SHIFT)) & PXP_PS_CTRL_TOG_FORMAT_MASK) +#define PXP_PS_CTRL_TOG_WB_SWAP_MASK (0x20U) +#define PXP_PS_CTRL_TOG_WB_SWAP_SHIFT (5U) +#define PXP_PS_CTRL_TOG_WB_SWAP(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_TOG_WB_SWAP_SHIFT)) & PXP_PS_CTRL_TOG_WB_SWAP_MASK) +#define PXP_PS_CTRL_TOG_RSVD0_MASK (0xC0U) +#define PXP_PS_CTRL_TOG_RSVD0_SHIFT (6U) +#define PXP_PS_CTRL_TOG_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_TOG_RSVD0_SHIFT)) & PXP_PS_CTRL_TOG_RSVD0_MASK) +#define PXP_PS_CTRL_TOG_DECY_MASK (0x300U) +#define PXP_PS_CTRL_TOG_DECY_SHIFT (8U) +/*! DECY + * 0b00..Disable pre-decimation filter. + * 0b01..Decimate PS by 2. + * 0b10..Decimate PS by 4. + * 0b11..Decimate PS by 8. + */ +#define PXP_PS_CTRL_TOG_DECY(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_TOG_DECY_SHIFT)) & PXP_PS_CTRL_TOG_DECY_MASK) +#define PXP_PS_CTRL_TOG_DECX_MASK (0xC00U) +#define PXP_PS_CTRL_TOG_DECX_SHIFT (10U) +/*! DECX + * 0b00..Disable pre-decimation filter. + * 0b01..Decimate PS by 2. + * 0b10..Decimate PS by 4. + * 0b11..Decimate PS by 8. + */ +#define PXP_PS_CTRL_TOG_DECX(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_TOG_DECX_SHIFT)) & PXP_PS_CTRL_TOG_DECX_MASK) +#define PXP_PS_CTRL_TOG_RSVD1_MASK (0xFFFFF000U) +#define PXP_PS_CTRL_TOG_RSVD1_SHIFT (12U) +#define PXP_PS_CTRL_TOG_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_TOG_RSVD1_SHIFT)) & PXP_PS_CTRL_TOG_RSVD1_MASK) +/*! @} */ + +/*! @name PS_BUF - PS Input Buffer Address */ +/*! @{ */ +#define PXP_PS_BUF_ADDR_MASK (0xFFFFFFFFU) +#define PXP_PS_BUF_ADDR_SHIFT (0U) +#define PXP_PS_BUF_ADDR(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_BUF_ADDR_SHIFT)) & PXP_PS_BUF_ADDR_MASK) +/*! @} */ + +/*! @name PS_UBUF - PS U/Cb or 2 Plane UV Input Buffer Address */ +/*! @{ */ +#define PXP_PS_UBUF_ADDR_MASK (0xFFFFFFFFU) +#define PXP_PS_UBUF_ADDR_SHIFT (0U) +#define PXP_PS_UBUF_ADDR(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_UBUF_ADDR_SHIFT)) & PXP_PS_UBUF_ADDR_MASK) +/*! @} */ + +/*! @name PS_VBUF - PS V/Cr Input Buffer Address */ +/*! @{ */ +#define PXP_PS_VBUF_ADDR_MASK (0xFFFFFFFFU) +#define PXP_PS_VBUF_ADDR_SHIFT (0U) +#define PXP_PS_VBUF_ADDR(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_VBUF_ADDR_SHIFT)) & PXP_PS_VBUF_ADDR_MASK) +/*! @} */ + +/*! @name PS_PITCH - Processed Surface Pitch */ +/*! @{ */ +#define PXP_PS_PITCH_PITCH_MASK (0xFFFFU) +#define PXP_PS_PITCH_PITCH_SHIFT (0U) +#define PXP_PS_PITCH_PITCH(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_PITCH_PITCH_SHIFT)) & PXP_PS_PITCH_PITCH_MASK) +#define PXP_PS_PITCH_RSVD_MASK (0xFFFF0000U) +#define PXP_PS_PITCH_RSVD_SHIFT (16U) +#define PXP_PS_PITCH_RSVD(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_PITCH_RSVD_SHIFT)) & PXP_PS_PITCH_RSVD_MASK) +/*! @} */ + +/*! @name PS_BACKGROUND - PS Background Color */ +/*! @{ */ +#define PXP_PS_BACKGROUND_COLOR_MASK (0xFFFFFFU) +#define PXP_PS_BACKGROUND_COLOR_SHIFT (0U) +#define PXP_PS_BACKGROUND_COLOR(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_BACKGROUND_COLOR_SHIFT)) & PXP_PS_BACKGROUND_COLOR_MASK) +#define PXP_PS_BACKGROUND_RSVD_MASK (0xFF000000U) +#define PXP_PS_BACKGROUND_RSVD_SHIFT (24U) +#define PXP_PS_BACKGROUND_RSVD(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_BACKGROUND_RSVD_SHIFT)) & PXP_PS_BACKGROUND_RSVD_MASK) +/*! @} */ + +/*! @name PS_SCALE - PS Scale Factor Register */ +/*! @{ */ +#define PXP_PS_SCALE_XSCALE_MASK (0x7FFFU) +#define PXP_PS_SCALE_XSCALE_SHIFT (0U) +#define PXP_PS_SCALE_XSCALE(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_SCALE_XSCALE_SHIFT)) & PXP_PS_SCALE_XSCALE_MASK) +#define PXP_PS_SCALE_RSVD1_MASK (0x8000U) +#define PXP_PS_SCALE_RSVD1_SHIFT (15U) +#define PXP_PS_SCALE_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_SCALE_RSVD1_SHIFT)) & PXP_PS_SCALE_RSVD1_MASK) +#define PXP_PS_SCALE_YSCALE_MASK (0x7FFF0000U) +#define PXP_PS_SCALE_YSCALE_SHIFT (16U) +#define PXP_PS_SCALE_YSCALE(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_SCALE_YSCALE_SHIFT)) & PXP_PS_SCALE_YSCALE_MASK) +#define PXP_PS_SCALE_RSVD2_MASK (0x80000000U) +#define PXP_PS_SCALE_RSVD2_SHIFT (31U) +#define PXP_PS_SCALE_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_SCALE_RSVD2_SHIFT)) & PXP_PS_SCALE_RSVD2_MASK) +/*! @} */ + +/*! @name PS_OFFSET - PS Scale Offset Register */ +/*! @{ */ +#define PXP_PS_OFFSET_XOFFSET_MASK (0xFFFU) +#define PXP_PS_OFFSET_XOFFSET_SHIFT (0U) +#define PXP_PS_OFFSET_XOFFSET(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_OFFSET_XOFFSET_SHIFT)) & PXP_PS_OFFSET_XOFFSET_MASK) +#define PXP_PS_OFFSET_RSVD1_MASK (0xF000U) +#define PXP_PS_OFFSET_RSVD1_SHIFT (12U) +#define PXP_PS_OFFSET_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_OFFSET_RSVD1_SHIFT)) & PXP_PS_OFFSET_RSVD1_MASK) +#define PXP_PS_OFFSET_YOFFSET_MASK (0xFFF0000U) +#define PXP_PS_OFFSET_YOFFSET_SHIFT (16U) +#define PXP_PS_OFFSET_YOFFSET(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_OFFSET_YOFFSET_SHIFT)) & PXP_PS_OFFSET_YOFFSET_MASK) +#define PXP_PS_OFFSET_RSVD2_MASK (0xF0000000U) +#define PXP_PS_OFFSET_RSVD2_SHIFT (28U) +#define PXP_PS_OFFSET_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_OFFSET_RSVD2_SHIFT)) & PXP_PS_OFFSET_RSVD2_MASK) +/*! @} */ + +/*! @name PS_CLRKEYLOW - PS Color Key Low */ +/*! @{ */ +#define PXP_PS_CLRKEYLOW_PIXEL_MASK (0xFFFFFFU) +#define PXP_PS_CLRKEYLOW_PIXEL_SHIFT (0U) +#define PXP_PS_CLRKEYLOW_PIXEL(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CLRKEYLOW_PIXEL_SHIFT)) & PXP_PS_CLRKEYLOW_PIXEL_MASK) +#define PXP_PS_CLRKEYLOW_RSVD1_MASK (0xFF000000U) +#define PXP_PS_CLRKEYLOW_RSVD1_SHIFT (24U) +#define PXP_PS_CLRKEYLOW_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CLRKEYLOW_RSVD1_SHIFT)) & PXP_PS_CLRKEYLOW_RSVD1_MASK) +/*! @} */ + +/*! @name PS_CLRKEYHIGH - PS Color Key High */ +/*! @{ */ +#define PXP_PS_CLRKEYHIGH_PIXEL_MASK (0xFFFFFFU) +#define PXP_PS_CLRKEYHIGH_PIXEL_SHIFT (0U) +#define PXP_PS_CLRKEYHIGH_PIXEL(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CLRKEYHIGH_PIXEL_SHIFT)) & PXP_PS_CLRKEYHIGH_PIXEL_MASK) +#define PXP_PS_CLRKEYHIGH_RSVD1_MASK (0xFF000000U) +#define PXP_PS_CLRKEYHIGH_RSVD1_SHIFT (24U) +#define PXP_PS_CLRKEYHIGH_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CLRKEYHIGH_RSVD1_SHIFT)) & PXP_PS_CLRKEYHIGH_RSVD1_MASK) +/*! @} */ + +/*! @name AS_CTRL - Alpha Surface Control */ +/*! @{ */ +#define PXP_AS_CTRL_RSVD0_MASK (0x1U) +#define PXP_AS_CTRL_RSVD0_SHIFT (0U) +#define PXP_AS_CTRL_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << PXP_AS_CTRL_RSVD0_SHIFT)) & PXP_AS_CTRL_RSVD0_MASK) +#define PXP_AS_CTRL_ALPHA_CTRL_MASK (0x6U) +#define PXP_AS_CTRL_ALPHA_CTRL_SHIFT (1U) +/*! ALPHA_CTRL + * 0b00..Indicates that the AS pixel alpha value will be used to blend the AS with PS. The ALPHA field is ignored. + * 0b01..Indicates that the value in the ALPHA field should be used instead of the alpha values present in the input pixels. + * 0b10..Indicates that the value in the ALPHA field should be used to scale all pixel alpha values. Each pixel alpha is multiplied by the value in the ALPHA field. + * 0b11..Enable ROPs. The ROP field indicates an operation to be performed on the alpha surface and PS pixels. + */ +#define PXP_AS_CTRL_ALPHA_CTRL(x) (((uint32_t)(((uint32_t)(x)) << PXP_AS_CTRL_ALPHA_CTRL_SHIFT)) & PXP_AS_CTRL_ALPHA_CTRL_MASK) +#define PXP_AS_CTRL_ENABLE_COLORKEY_MASK (0x8U) +#define PXP_AS_CTRL_ENABLE_COLORKEY_SHIFT (3U) +#define PXP_AS_CTRL_ENABLE_COLORKEY(x) (((uint32_t)(((uint32_t)(x)) << PXP_AS_CTRL_ENABLE_COLORKEY_SHIFT)) & PXP_AS_CTRL_ENABLE_COLORKEY_MASK) +#define PXP_AS_CTRL_FORMAT_MASK (0xF0U) +#define PXP_AS_CTRL_FORMAT_SHIFT (4U) +/*! FORMAT + * 0b0000..32-bit pixels with alpha + * 0b0100..32-bit pixels without alpha (unpacked 24-bit format) + * 0b1000..16-bit pixels with alpha + * 0b1001..16-bit pixels with alpha + * 0b1100..16-bit pixels without alpha + * 0b1101..16-bit pixels without alpha + * 0b1110..16-bit pixels without alpha + */ +#define PXP_AS_CTRL_FORMAT(x) (((uint32_t)(((uint32_t)(x)) << PXP_AS_CTRL_FORMAT_SHIFT)) & PXP_AS_CTRL_FORMAT_MASK) +#define PXP_AS_CTRL_ALPHA_MASK (0xFF00U) +#define PXP_AS_CTRL_ALPHA_SHIFT (8U) +#define PXP_AS_CTRL_ALPHA(x) (((uint32_t)(((uint32_t)(x)) << PXP_AS_CTRL_ALPHA_SHIFT)) & PXP_AS_CTRL_ALPHA_MASK) +#define PXP_AS_CTRL_ROP_MASK (0xF0000U) +#define PXP_AS_CTRL_ROP_SHIFT (16U) +/*! ROP + * 0b0000..AS AND PS + * 0b0001..nAS AND PS + * 0b0010..AS AND nPS + * 0b0011..AS OR PS + * 0b0100..nAS OR PS + * 0b0101..AS OR nPS + * 0b0110..nAS + * 0b0111..nPS + * 0b1000..AS NAND PS + * 0b1001..AS NOR PS + * 0b1010..AS XOR PS + * 0b1011..AS XNOR PS + */ +#define PXP_AS_CTRL_ROP(x) (((uint32_t)(((uint32_t)(x)) << PXP_AS_CTRL_ROP_SHIFT)) & PXP_AS_CTRL_ROP_MASK) +#define PXP_AS_CTRL_ALPHA_INVERT_MASK (0x100000U) +#define PXP_AS_CTRL_ALPHA_INVERT_SHIFT (20U) +#define PXP_AS_CTRL_ALPHA_INVERT(x) (((uint32_t)(((uint32_t)(x)) << PXP_AS_CTRL_ALPHA_INVERT_SHIFT)) & PXP_AS_CTRL_ALPHA_INVERT_MASK) +#define PXP_AS_CTRL_RSVD1_MASK (0xFFE00000U) +#define PXP_AS_CTRL_RSVD1_SHIFT (21U) +#define PXP_AS_CTRL_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << PXP_AS_CTRL_RSVD1_SHIFT)) & PXP_AS_CTRL_RSVD1_MASK) +/*! @} */ + +/*! @name AS_BUF - Alpha Surface Buffer Pointer */ +/*! @{ */ +#define PXP_AS_BUF_ADDR_MASK (0xFFFFFFFFU) +#define PXP_AS_BUF_ADDR_SHIFT (0U) +#define PXP_AS_BUF_ADDR(x) (((uint32_t)(((uint32_t)(x)) << PXP_AS_BUF_ADDR_SHIFT)) & PXP_AS_BUF_ADDR_MASK) +/*! @} */ + +/*! @name AS_PITCH - Alpha Surface Pitch */ +/*! @{ */ +#define PXP_AS_PITCH_PITCH_MASK (0xFFFFU) +#define PXP_AS_PITCH_PITCH_SHIFT (0U) +#define PXP_AS_PITCH_PITCH(x) (((uint32_t)(((uint32_t)(x)) << PXP_AS_PITCH_PITCH_SHIFT)) & PXP_AS_PITCH_PITCH_MASK) +#define PXP_AS_PITCH_RSVD_MASK (0xFFFF0000U) +#define PXP_AS_PITCH_RSVD_SHIFT (16U) +#define PXP_AS_PITCH_RSVD(x) (((uint32_t)(((uint32_t)(x)) << PXP_AS_PITCH_RSVD_SHIFT)) & PXP_AS_PITCH_RSVD_MASK) +/*! @} */ + +/*! @name AS_CLRKEYLOW - Overlay Color Key Low */ +/*! @{ */ +#define PXP_AS_CLRKEYLOW_PIXEL_MASK (0xFFFFFFU) +#define PXP_AS_CLRKEYLOW_PIXEL_SHIFT (0U) +#define PXP_AS_CLRKEYLOW_PIXEL(x) (((uint32_t)(((uint32_t)(x)) << PXP_AS_CLRKEYLOW_PIXEL_SHIFT)) & PXP_AS_CLRKEYLOW_PIXEL_MASK) +#define PXP_AS_CLRKEYLOW_RSVD1_MASK (0xFF000000U) +#define PXP_AS_CLRKEYLOW_RSVD1_SHIFT (24U) +#define PXP_AS_CLRKEYLOW_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << PXP_AS_CLRKEYLOW_RSVD1_SHIFT)) & PXP_AS_CLRKEYLOW_RSVD1_MASK) +/*! @} */ + +/*! @name AS_CLRKEYHIGH - Overlay Color Key High */ +/*! @{ */ +#define PXP_AS_CLRKEYHIGH_PIXEL_MASK (0xFFFFFFU) +#define PXP_AS_CLRKEYHIGH_PIXEL_SHIFT (0U) +#define PXP_AS_CLRKEYHIGH_PIXEL(x) (((uint32_t)(((uint32_t)(x)) << PXP_AS_CLRKEYHIGH_PIXEL_SHIFT)) & PXP_AS_CLRKEYHIGH_PIXEL_MASK) +#define PXP_AS_CLRKEYHIGH_RSVD1_MASK (0xFF000000U) +#define PXP_AS_CLRKEYHIGH_RSVD1_SHIFT (24U) +#define PXP_AS_CLRKEYHIGH_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << PXP_AS_CLRKEYHIGH_RSVD1_SHIFT)) & PXP_AS_CLRKEYHIGH_RSVD1_MASK) +/*! @} */ + +/*! @name CSC1_COEF0 - Color Space Conversion Coefficient Register 0 */ +/*! @{ */ +#define PXP_CSC1_COEF0_Y_OFFSET_MASK (0x1FFU) +#define PXP_CSC1_COEF0_Y_OFFSET_SHIFT (0U) +#define PXP_CSC1_COEF0_Y_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PXP_CSC1_COEF0_Y_OFFSET_SHIFT)) & PXP_CSC1_COEF0_Y_OFFSET_MASK) +#define PXP_CSC1_COEF0_UV_OFFSET_MASK (0x3FE00U) +#define PXP_CSC1_COEF0_UV_OFFSET_SHIFT (9U) +#define PXP_CSC1_COEF0_UV_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PXP_CSC1_COEF0_UV_OFFSET_SHIFT)) & PXP_CSC1_COEF0_UV_OFFSET_MASK) +#define PXP_CSC1_COEF0_C0_MASK (0x1FFC0000U) +#define PXP_CSC1_COEF0_C0_SHIFT (18U) +#define PXP_CSC1_COEF0_C0(x) (((uint32_t)(((uint32_t)(x)) << PXP_CSC1_COEF0_C0_SHIFT)) & PXP_CSC1_COEF0_C0_MASK) +#define PXP_CSC1_COEF0_RSVD1_MASK (0x20000000U) +#define PXP_CSC1_COEF0_RSVD1_SHIFT (29U) +#define PXP_CSC1_COEF0_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << PXP_CSC1_COEF0_RSVD1_SHIFT)) & PXP_CSC1_COEF0_RSVD1_MASK) +#define PXP_CSC1_COEF0_BYPASS_MASK (0x40000000U) +#define PXP_CSC1_COEF0_BYPASS_SHIFT (30U) +#define PXP_CSC1_COEF0_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << PXP_CSC1_COEF0_BYPASS_SHIFT)) & PXP_CSC1_COEF0_BYPASS_MASK) +#define PXP_CSC1_COEF0_YCBCR_MODE_MASK (0x80000000U) +#define PXP_CSC1_COEF0_YCBCR_MODE_SHIFT (31U) +#define PXP_CSC1_COEF0_YCBCR_MODE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CSC1_COEF0_YCBCR_MODE_SHIFT)) & PXP_CSC1_COEF0_YCBCR_MODE_MASK) +/*! @} */ + +/*! @name CSC1_COEF1 - Color Space Conversion Coefficient Register 1 */ +/*! @{ */ +#define PXP_CSC1_COEF1_C4_MASK (0x7FFU) +#define PXP_CSC1_COEF1_C4_SHIFT (0U) +#define PXP_CSC1_COEF1_C4(x) (((uint32_t)(((uint32_t)(x)) << PXP_CSC1_COEF1_C4_SHIFT)) & PXP_CSC1_COEF1_C4_MASK) +#define PXP_CSC1_COEF1_RSVD0_MASK (0xF800U) +#define PXP_CSC1_COEF1_RSVD0_SHIFT (11U) +#define PXP_CSC1_COEF1_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << PXP_CSC1_COEF1_RSVD0_SHIFT)) & PXP_CSC1_COEF1_RSVD0_MASK) +#define PXP_CSC1_COEF1_C1_MASK (0x7FF0000U) +#define PXP_CSC1_COEF1_C1_SHIFT (16U) +#define PXP_CSC1_COEF1_C1(x) (((uint32_t)(((uint32_t)(x)) << PXP_CSC1_COEF1_C1_SHIFT)) & PXP_CSC1_COEF1_C1_MASK) +#define PXP_CSC1_COEF1_RSVD1_MASK (0xF8000000U) +#define PXP_CSC1_COEF1_RSVD1_SHIFT (27U) +#define PXP_CSC1_COEF1_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << PXP_CSC1_COEF1_RSVD1_SHIFT)) & PXP_CSC1_COEF1_RSVD1_MASK) +/*! @} */ + +/*! @name CSC1_COEF2 - Color Space Conversion Coefficient Register 2 */ +/*! @{ */ +#define PXP_CSC1_COEF2_C3_MASK (0x7FFU) +#define PXP_CSC1_COEF2_C3_SHIFT (0U) +#define PXP_CSC1_COEF2_C3(x) (((uint32_t)(((uint32_t)(x)) << PXP_CSC1_COEF2_C3_SHIFT)) & PXP_CSC1_COEF2_C3_MASK) +#define PXP_CSC1_COEF2_RSVD0_MASK (0xF800U) +#define PXP_CSC1_COEF2_RSVD0_SHIFT (11U) +#define PXP_CSC1_COEF2_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << PXP_CSC1_COEF2_RSVD0_SHIFT)) & PXP_CSC1_COEF2_RSVD0_MASK) +#define PXP_CSC1_COEF2_C2_MASK (0x7FF0000U) +#define PXP_CSC1_COEF2_C2_SHIFT (16U) +#define PXP_CSC1_COEF2_C2(x) (((uint32_t)(((uint32_t)(x)) << PXP_CSC1_COEF2_C2_SHIFT)) & PXP_CSC1_COEF2_C2_MASK) +#define PXP_CSC1_COEF2_RSVD1_MASK (0xF8000000U) +#define PXP_CSC1_COEF2_RSVD1_SHIFT (27U) +#define PXP_CSC1_COEF2_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << PXP_CSC1_COEF2_RSVD1_SHIFT)) & PXP_CSC1_COEF2_RSVD1_MASK) +/*! @} */ + +/*! @name POWER - PXP Power Control Register */ +/*! @{ */ +#define PXP_POWER_ROT_MEM_LP_STATE_MASK (0xE00U) +#define PXP_POWER_ROT_MEM_LP_STATE_SHIFT (9U) +/*! ROT_MEM_LP_STATE + * 0b000..Memory is not in low power state. + * 0b001..Light Sleep Mode. Low leakage mode, maintain memory contents. + * 0b010..Deep Sleep Mode. Low leakage mode, maintain memory contents. + * 0b100..Shut Down Mode. Shut Down periphery and core, no memory retention. + */ +#define PXP_POWER_ROT_MEM_LP_STATE(x) (((uint32_t)(((uint32_t)(x)) << PXP_POWER_ROT_MEM_LP_STATE_SHIFT)) & PXP_POWER_ROT_MEM_LP_STATE_MASK) +#define PXP_POWER_CTRL_MASK (0xFFFFF000U) +#define PXP_POWER_CTRL_SHIFT (12U) +#define PXP_POWER_CTRL(x) (((uint32_t)(((uint32_t)(x)) << PXP_POWER_CTRL_SHIFT)) & PXP_POWER_CTRL_MASK) +/*! @} */ + +/*! @name NEXT - Next Frame Pointer */ +/*! @{ */ +#define PXP_NEXT_ENABLED_MASK (0x1U) +#define PXP_NEXT_ENABLED_SHIFT (0U) +#define PXP_NEXT_ENABLED(x) (((uint32_t)(((uint32_t)(x)) << PXP_NEXT_ENABLED_SHIFT)) & PXP_NEXT_ENABLED_MASK) +#define PXP_NEXT_RSVD_MASK (0x2U) +#define PXP_NEXT_RSVD_SHIFT (1U) +#define PXP_NEXT_RSVD(x) (((uint32_t)(((uint32_t)(x)) << PXP_NEXT_RSVD_SHIFT)) & PXP_NEXT_RSVD_MASK) +#define PXP_NEXT_POINTER_MASK (0xFFFFFFFCU) +#define PXP_NEXT_POINTER_SHIFT (2U) +#define PXP_NEXT_POINTER(x) (((uint32_t)(((uint32_t)(x)) << PXP_NEXT_POINTER_SHIFT)) & PXP_NEXT_POINTER_MASK) +/*! @} */ + +/*! @name PORTER_DUFF_CTRL - PXP Alpha Engine A Control Register. */ +/*! @{ */ +#define PXP_PORTER_DUFF_CTRL_POTER_DUFF_ENABLE_MASK (0x1U) +#define PXP_PORTER_DUFF_CTRL_POTER_DUFF_ENABLE_SHIFT (0U) +#define PXP_PORTER_DUFF_CTRL_POTER_DUFF_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << PXP_PORTER_DUFF_CTRL_POTER_DUFF_ENABLE_SHIFT)) & PXP_PORTER_DUFF_CTRL_POTER_DUFF_ENABLE_MASK) +#define PXP_PORTER_DUFF_CTRL_S0_S1_FACTOR_MODE_MASK (0x6U) +#define PXP_PORTER_DUFF_CTRL_S0_S1_FACTOR_MODE_SHIFT (1U) +#define PXP_PORTER_DUFF_CTRL_S0_S1_FACTOR_MODE(x) (((uint32_t)(((uint32_t)(x)) << PXP_PORTER_DUFF_CTRL_S0_S1_FACTOR_MODE_SHIFT)) & PXP_PORTER_DUFF_CTRL_S0_S1_FACTOR_MODE_MASK) +#define PXP_PORTER_DUFF_CTRL_S0_GLOBAL_ALPHA_MODE_MASK (0x18U) +#define PXP_PORTER_DUFF_CTRL_S0_GLOBAL_ALPHA_MODE_SHIFT (3U) +#define PXP_PORTER_DUFF_CTRL_S0_GLOBAL_ALPHA_MODE(x) (((uint32_t)(((uint32_t)(x)) << PXP_PORTER_DUFF_CTRL_S0_GLOBAL_ALPHA_MODE_SHIFT)) & PXP_PORTER_DUFF_CTRL_S0_GLOBAL_ALPHA_MODE_MASK) +#define PXP_PORTER_DUFF_CTRL_S0_ALPHA_MODE_MASK (0x20U) +#define PXP_PORTER_DUFF_CTRL_S0_ALPHA_MODE_SHIFT (5U) +#define PXP_PORTER_DUFF_CTRL_S0_ALPHA_MODE(x) (((uint32_t)(((uint32_t)(x)) << PXP_PORTER_DUFF_CTRL_S0_ALPHA_MODE_SHIFT)) & PXP_PORTER_DUFF_CTRL_S0_ALPHA_MODE_MASK) +#define PXP_PORTER_DUFF_CTRL_S0_COLOR_MODE_MASK (0x40U) +#define PXP_PORTER_DUFF_CTRL_S0_COLOR_MODE_SHIFT (6U) +#define PXP_PORTER_DUFF_CTRL_S0_COLOR_MODE(x) (((uint32_t)(((uint32_t)(x)) << PXP_PORTER_DUFF_CTRL_S0_COLOR_MODE_SHIFT)) & PXP_PORTER_DUFF_CTRL_S0_COLOR_MODE_MASK) +#define PXP_PORTER_DUFF_CTRL_S1_S0_FACTOR_MODE_MASK (0x300U) +#define PXP_PORTER_DUFF_CTRL_S1_S0_FACTOR_MODE_SHIFT (8U) +#define PXP_PORTER_DUFF_CTRL_S1_S0_FACTOR_MODE(x) (((uint32_t)(((uint32_t)(x)) << PXP_PORTER_DUFF_CTRL_S1_S0_FACTOR_MODE_SHIFT)) & PXP_PORTER_DUFF_CTRL_S1_S0_FACTOR_MODE_MASK) +#define PXP_PORTER_DUFF_CTRL_S1_GLOBAL_ALPHA_MODE_MASK (0xC00U) +#define PXP_PORTER_DUFF_CTRL_S1_GLOBAL_ALPHA_MODE_SHIFT (10U) +#define PXP_PORTER_DUFF_CTRL_S1_GLOBAL_ALPHA_MODE(x) (((uint32_t)(((uint32_t)(x)) << PXP_PORTER_DUFF_CTRL_S1_GLOBAL_ALPHA_MODE_SHIFT)) & PXP_PORTER_DUFF_CTRL_S1_GLOBAL_ALPHA_MODE_MASK) +#define PXP_PORTER_DUFF_CTRL_S1_ALPHA_MODE_MASK (0x1000U) +#define PXP_PORTER_DUFF_CTRL_S1_ALPHA_MODE_SHIFT (12U) +#define PXP_PORTER_DUFF_CTRL_S1_ALPHA_MODE(x) (((uint32_t)(((uint32_t)(x)) << PXP_PORTER_DUFF_CTRL_S1_ALPHA_MODE_SHIFT)) & PXP_PORTER_DUFF_CTRL_S1_ALPHA_MODE_MASK) +#define PXP_PORTER_DUFF_CTRL_S1_COLOR_MODE_MASK (0x2000U) +#define PXP_PORTER_DUFF_CTRL_S1_COLOR_MODE_SHIFT (13U) +#define PXP_PORTER_DUFF_CTRL_S1_COLOR_MODE(x) (((uint32_t)(((uint32_t)(x)) << PXP_PORTER_DUFF_CTRL_S1_COLOR_MODE_SHIFT)) & PXP_PORTER_DUFF_CTRL_S1_COLOR_MODE_MASK) +#define PXP_PORTER_DUFF_CTRL_S0_GLOBAL_ALPHA_MASK (0xFF0000U) +#define PXP_PORTER_DUFF_CTRL_S0_GLOBAL_ALPHA_SHIFT (16U) +#define PXP_PORTER_DUFF_CTRL_S0_GLOBAL_ALPHA(x) (((uint32_t)(((uint32_t)(x)) << PXP_PORTER_DUFF_CTRL_S0_GLOBAL_ALPHA_SHIFT)) & PXP_PORTER_DUFF_CTRL_S0_GLOBAL_ALPHA_MASK) +#define PXP_PORTER_DUFF_CTRL_S1_GLOBAL_ALPHA_MASK (0xFF000000U) +#define PXP_PORTER_DUFF_CTRL_S1_GLOBAL_ALPHA_SHIFT (24U) +#define PXP_PORTER_DUFF_CTRL_S1_GLOBAL_ALPHA(x) (((uint32_t)(((uint32_t)(x)) << PXP_PORTER_DUFF_CTRL_S1_GLOBAL_ALPHA_SHIFT)) & PXP_PORTER_DUFF_CTRL_S1_GLOBAL_ALPHA_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group PXP_Register_Masks */ + + +/* PXP - Peripheral instance base addresses */ +/** Peripheral PXP base address */ +#define PXP_BASE (0x402B4000u) +/** Peripheral PXP base pointer */ +#define PXP ((PXP_Type *)PXP_BASE) +/** Array initializer of PXP peripheral base addresses */ +#define PXP_BASE_ADDRS { PXP_BASE } +/** Array initializer of PXP peripheral base pointers */ +#define PXP_BASE_PTRS { PXP } +/** Interrupt vectors for the PXP peripheral type */ +#define PXP_IRQ0_IRQS { PXP_IRQn } + +/*! + * @} + */ /* end of group PXP_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- ROMC Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup ROMC_Peripheral_Access_Layer ROMC Peripheral Access Layer + * @{ + */ + +/** ROMC - Register Layout Typedef */ +typedef struct { + uint8_t RESERVED_0[212]; + __IO uint32_t ROMPATCHD[8]; /**< ROMC Data Registers, array offset: 0xD4, array step: 0x4 */ + __IO uint32_t ROMPATCHCNTL; /**< ROMC Control Register, offset: 0xF4 */ + uint32_t ROMPATCHENH; /**< ROMC Enable Register High, offset: 0xF8 */ + __IO uint32_t ROMPATCHENL; /**< ROMC Enable Register Low, offset: 0xFC */ + __IO uint32_t ROMPATCHA[16]; /**< ROMC Address Registers, array offset: 0x100, array step: 0x4 */ + uint8_t RESERVED_1[200]; + __IO uint32_t ROMPATCHSR; /**< ROMC Status Register, offset: 0x208 */ +} ROMC_Type; + +/* ---------------------------------------------------------------------------- + -- ROMC Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup ROMC_Register_Masks ROMC Register Masks + * @{ + */ + +/*! @name ROMPATCHD - ROMC Data Registers */ +/*! @{ */ +#define ROMC_ROMPATCHD_DATAX_MASK (0xFFFFFFFFU) +#define ROMC_ROMPATCHD_DATAX_SHIFT (0U) +#define ROMC_ROMPATCHD_DATAX(x) (((uint32_t)(((uint32_t)(x)) << ROMC_ROMPATCHD_DATAX_SHIFT)) & ROMC_ROMPATCHD_DATAX_MASK) +/*! @} */ + +/* The count of ROMC_ROMPATCHD */ +#define ROMC_ROMPATCHD_COUNT (8U) + +/*! @name ROMPATCHCNTL - ROMC Control Register */ +/*! @{ */ +#define ROMC_ROMPATCHCNTL_DATAFIX_MASK (0xFFU) +#define ROMC_ROMPATCHCNTL_DATAFIX_SHIFT (0U) +/*! DATAFIX + * 0b00000000..Address comparator triggers a opcode patch + * 0b00000001..Address comparator triggers a data fix + */ +#define ROMC_ROMPATCHCNTL_DATAFIX(x) (((uint32_t)(((uint32_t)(x)) << ROMC_ROMPATCHCNTL_DATAFIX_SHIFT)) & ROMC_ROMPATCHCNTL_DATAFIX_MASK) +#define ROMC_ROMPATCHCNTL_DIS_MASK (0x20000000U) +#define ROMC_ROMPATCHCNTL_DIS_SHIFT (29U) +/*! DIS + * 0b0..Does not affect any ROMC functions (default) + * 0b1..Disable all ROMC functions: data fixing, and opcode patching + */ +#define ROMC_ROMPATCHCNTL_DIS(x) (((uint32_t)(((uint32_t)(x)) << ROMC_ROMPATCHCNTL_DIS_SHIFT)) & ROMC_ROMPATCHCNTL_DIS_MASK) +/*! @} */ + +/*! @name ROMPATCHENL - ROMC Enable Register Low */ +/*! @{ */ +#define ROMC_ROMPATCHENL_ENABLE_MASK (0xFFFFU) +#define ROMC_ROMPATCHENL_ENABLE_SHIFT (0U) +/*! ENABLE + * 0b0000000000000000..Address comparator disabled + * 0b0000000000000001..Address comparator enabled, ROMC will trigger a opcode patch or data fix event upon matching of the associated address + */ +#define ROMC_ROMPATCHENL_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ROMC_ROMPATCHENL_ENABLE_SHIFT)) & ROMC_ROMPATCHENL_ENABLE_MASK) +/*! @} */ + +/*! @name ROMPATCHA - ROMC Address Registers */ +/*! @{ */ +#define ROMC_ROMPATCHA_THUMBX_MASK (0x1U) +#define ROMC_ROMPATCHA_THUMBX_SHIFT (0U) +/*! THUMBX + * 0b0..Arm patch + * 0b1..THUMB patch (ignore if data fix) + */ +#define ROMC_ROMPATCHA_THUMBX(x) (((uint32_t)(((uint32_t)(x)) << ROMC_ROMPATCHA_THUMBX_SHIFT)) & ROMC_ROMPATCHA_THUMBX_MASK) +#define ROMC_ROMPATCHA_ADDRX_MASK (0x7FFFFEU) +#define ROMC_ROMPATCHA_ADDRX_SHIFT (1U) +#define ROMC_ROMPATCHA_ADDRX(x) (((uint32_t)(((uint32_t)(x)) << ROMC_ROMPATCHA_ADDRX_SHIFT)) & ROMC_ROMPATCHA_ADDRX_MASK) +/*! @} */ + +/* The count of ROMC_ROMPATCHA */ +#define ROMC_ROMPATCHA_COUNT (16U) + +/*! @name ROMPATCHSR - ROMC Status Register */ +/*! @{ */ +#define ROMC_ROMPATCHSR_SOURCE_MASK (0x3FU) +#define ROMC_ROMPATCHSR_SOURCE_SHIFT (0U) +/*! SOURCE + * 0b000000..Address Comparator 0 matched + * 0b000001..Address Comparator 1 matched + * 0b001111..Address Comparator 15 matched + */ +#define ROMC_ROMPATCHSR_SOURCE(x) (((uint32_t)(((uint32_t)(x)) << ROMC_ROMPATCHSR_SOURCE_SHIFT)) & ROMC_ROMPATCHSR_SOURCE_MASK) +#define ROMC_ROMPATCHSR_SW_MASK (0x20000U) +#define ROMC_ROMPATCHSR_SW_SHIFT (17U) +/*! SW + * 0b0..no event or comparator collisions + * 0b1..a collision has occurred + */ +#define ROMC_ROMPATCHSR_SW(x) (((uint32_t)(((uint32_t)(x)) << ROMC_ROMPATCHSR_SW_SHIFT)) & ROMC_ROMPATCHSR_SW_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group ROMC_Register_Masks */ + + +/* ROMC - Peripheral instance base addresses */ +/** Peripheral ROMC base address */ +#define ROMC_BASE (0x40180000u) +/** Peripheral ROMC base pointer */ +#define ROMC ((ROMC_Type *)ROMC_BASE) +/** Array initializer of ROMC peripheral base addresses */ +#define ROMC_BASE_ADDRS { ROMC_BASE } +/** Array initializer of ROMC peripheral base pointers */ +#define ROMC_BASE_PTRS { ROMC } + +/*! + * @} + */ /* end of group ROMC_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- RTWDOG Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup RTWDOG_Peripheral_Access_Layer RTWDOG Peripheral Access Layer + * @{ + */ + +/** RTWDOG - Register Layout Typedef */ +typedef struct { + __IO uint32_t CS; /**< Watchdog Control and Status Register, offset: 0x0 */ + __IO uint32_t CNT; /**< Watchdog Counter Register, offset: 0x4 */ + __IO uint32_t TOVAL; /**< Watchdog Timeout Value Register, offset: 0x8 */ + __IO uint32_t WIN; /**< Watchdog Window Register, offset: 0xC */ +} RTWDOG_Type; + +/* ---------------------------------------------------------------------------- + -- RTWDOG Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup RTWDOG_Register_Masks RTWDOG Register Masks + * @{ + */ + +/*! @name CS - Watchdog Control and Status Register */ +/*! @{ */ +#define RTWDOG_CS_STOP_MASK (0x1U) +#define RTWDOG_CS_STOP_SHIFT (0U) +/*! STOP - Stop Enable + * 0b0..Watchdog disabled in chip stop mode. + * 0b1..Watchdog enabled in chip stop mode. + */ +#define RTWDOG_CS_STOP(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_CS_STOP_SHIFT)) & RTWDOG_CS_STOP_MASK) +#define RTWDOG_CS_WAIT_MASK (0x2U) +#define RTWDOG_CS_WAIT_SHIFT (1U) +/*! WAIT - Wait Enable + * 0b0..Watchdog disabled in chip wait mode. + * 0b1..Watchdog enabled in chip wait mode. + */ +#define RTWDOG_CS_WAIT(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_CS_WAIT_SHIFT)) & RTWDOG_CS_WAIT_MASK) +#define RTWDOG_CS_DBG_MASK (0x4U) +#define RTWDOG_CS_DBG_SHIFT (2U) +/*! DBG - Debug Enable + * 0b0..Watchdog disabled in chip debug mode. + * 0b1..Watchdog enabled in chip debug mode. + */ +#define RTWDOG_CS_DBG(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_CS_DBG_SHIFT)) & RTWDOG_CS_DBG_MASK) +#define RTWDOG_CS_TST_MASK (0x18U) +#define RTWDOG_CS_TST_SHIFT (3U) +/*! TST - Watchdog Test + * 0b00..Watchdog test mode disabled. + * 0b01..Watchdog user mode enabled. (Watchdog test mode disabled.) After testing the watchdog, software should use this setting to indicate that the watchdog is functioning normally in user mode. + * 0b10..Watchdog test mode enabled, only the low byte is used. CNT[CNTLOW] is compared with TOVAL[TOVALLOW]. + * 0b11..Watchdog test mode enabled, only the high byte is used. CNT[CNTHIGH] is compared with TOVAL[TOVALHIGH]. + */ +#define RTWDOG_CS_TST(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_CS_TST_SHIFT)) & RTWDOG_CS_TST_MASK) +#define RTWDOG_CS_UPDATE_MASK (0x20U) +#define RTWDOG_CS_UPDATE_SHIFT (5U) +/*! UPDATE - Allow updates + * 0b0..Updates not allowed. After the initial configuration, the watchdog cannot be later modified without forcing a reset. + * 0b1..Updates allowed. Software can modify the watchdog configuration registers within 128 bus clocks after performing the unlock write sequence. + */ +#define RTWDOG_CS_UPDATE(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_CS_UPDATE_SHIFT)) & RTWDOG_CS_UPDATE_MASK) +#define RTWDOG_CS_INT_MASK (0x40U) +#define RTWDOG_CS_INT_SHIFT (6U) +/*! INT - Watchdog Interrupt + * 0b0..Watchdog interrupts are disabled. Watchdog resets are not delayed. + * 0b1..Watchdog interrupts are enabled. Watchdog resets are delayed by 128 bus clocks from the interrupt vector fetch. + */ +#define RTWDOG_CS_INT(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_CS_INT_SHIFT)) & RTWDOG_CS_INT_MASK) +#define RTWDOG_CS_EN_MASK (0x80U) +#define RTWDOG_CS_EN_SHIFT (7U) +/*! EN - Watchdog Enable + * 0b0..Watchdog disabled. + * 0b1..Watchdog enabled. + */ +#define RTWDOG_CS_EN(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_CS_EN_SHIFT)) & RTWDOG_CS_EN_MASK) +#define RTWDOG_CS_CLK_MASK (0x300U) +#define RTWDOG_CS_CLK_SHIFT (8U) +/*! CLK - Watchdog Clock + * 0b00..Bus clock + * 0b01..LPO clock + * 0b10..INTCLK (internal clock) + * 0b11..ERCLK (external reference clock) + */ +#define RTWDOG_CS_CLK(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_CS_CLK_SHIFT)) & RTWDOG_CS_CLK_MASK) +#define RTWDOG_CS_RCS_MASK (0x400U) +#define RTWDOG_CS_RCS_SHIFT (10U) +/*! RCS - Reconfiguration Success + * 0b0..Reconfiguring WDOG. + * 0b1..Reconfiguration is successful. + */ +#define RTWDOG_CS_RCS(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_CS_RCS_SHIFT)) & RTWDOG_CS_RCS_MASK) +#define RTWDOG_CS_ULK_MASK (0x800U) +#define RTWDOG_CS_ULK_SHIFT (11U) +/*! ULK - Unlock status + * 0b0..WDOG is locked. + * 0b1..WDOG is unlocked. + */ +#define RTWDOG_CS_ULK(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_CS_ULK_SHIFT)) & RTWDOG_CS_ULK_MASK) +#define RTWDOG_CS_PRES_MASK (0x1000U) +#define RTWDOG_CS_PRES_SHIFT (12U) +/*! PRES - Watchdog prescaler + * 0b0..256 prescaler disabled. + * 0b1..256 prescaler enabled. + */ +#define RTWDOG_CS_PRES(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_CS_PRES_SHIFT)) & RTWDOG_CS_PRES_MASK) +#define RTWDOG_CS_CMD32EN_MASK (0x2000U) +#define RTWDOG_CS_CMD32EN_SHIFT (13U) +/*! CMD32EN - Enables or disables WDOG support for 32-bit (otherwise 16-bit or 8-bit) refresh/unlock command write words + * 0b0..Disables support for 32-bit refresh/unlock command write words. Only 16-bit or 8-bit is supported. + * 0b1..Enables support for 32-bit refresh/unlock command write words. 16-bit or 8-bit is NOT supported. + */ +#define RTWDOG_CS_CMD32EN(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_CS_CMD32EN_SHIFT)) & RTWDOG_CS_CMD32EN_MASK) +#define RTWDOG_CS_FLG_MASK (0x4000U) +#define RTWDOG_CS_FLG_SHIFT (14U) +/*! FLG - Watchdog Interrupt Flag + * 0b0..No interrupt occurred. + * 0b1..An interrupt occurred. + */ +#define RTWDOG_CS_FLG(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_CS_FLG_SHIFT)) & RTWDOG_CS_FLG_MASK) +#define RTWDOG_CS_WIN_MASK (0x8000U) +#define RTWDOG_CS_WIN_SHIFT (15U) +/*! WIN - Watchdog Window + * 0b0..Window mode disabled. + * 0b1..Window mode enabled. + */ +#define RTWDOG_CS_WIN(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_CS_WIN_SHIFT)) & RTWDOG_CS_WIN_MASK) +/*! @} */ + +/*! @name CNT - Watchdog Counter Register */ +/*! @{ */ +#define RTWDOG_CNT_CNTLOW_MASK (0xFFU) +#define RTWDOG_CNT_CNTLOW_SHIFT (0U) +#define RTWDOG_CNT_CNTLOW(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_CNT_CNTLOW_SHIFT)) & RTWDOG_CNT_CNTLOW_MASK) +#define RTWDOG_CNT_CNTHIGH_MASK (0xFF00U) +#define RTWDOG_CNT_CNTHIGH_SHIFT (8U) +#define RTWDOG_CNT_CNTHIGH(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_CNT_CNTHIGH_SHIFT)) & RTWDOG_CNT_CNTHIGH_MASK) +/*! @} */ + +/*! @name TOVAL - Watchdog Timeout Value Register */ +/*! @{ */ +#define RTWDOG_TOVAL_TOVALLOW_MASK (0xFFU) +#define RTWDOG_TOVAL_TOVALLOW_SHIFT (0U) +#define RTWDOG_TOVAL_TOVALLOW(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_TOVAL_TOVALLOW_SHIFT)) & RTWDOG_TOVAL_TOVALLOW_MASK) +#define RTWDOG_TOVAL_TOVALHIGH_MASK (0xFF00U) +#define RTWDOG_TOVAL_TOVALHIGH_SHIFT (8U) +#define RTWDOG_TOVAL_TOVALHIGH(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_TOVAL_TOVALHIGH_SHIFT)) & RTWDOG_TOVAL_TOVALHIGH_MASK) +/*! @} */ + +/*! @name WIN - Watchdog Window Register */ +/*! @{ */ +#define RTWDOG_WIN_WINLOW_MASK (0xFFU) +#define RTWDOG_WIN_WINLOW_SHIFT (0U) +#define RTWDOG_WIN_WINLOW(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_WIN_WINLOW_SHIFT)) & RTWDOG_WIN_WINLOW_MASK) +#define RTWDOG_WIN_WINHIGH_MASK (0xFF00U) +#define RTWDOG_WIN_WINHIGH_SHIFT (8U) +#define RTWDOG_WIN_WINHIGH(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_WIN_WINHIGH_SHIFT)) & RTWDOG_WIN_WINHIGH_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group RTWDOG_Register_Masks */ + + +/* RTWDOG - Peripheral instance base addresses */ +/** Peripheral RTWDOG base address */ +#define RTWDOG_BASE (0x400BC000u) +/** Peripheral RTWDOG base pointer */ +#define RTWDOG ((RTWDOG_Type *)RTWDOG_BASE) +/** Array initializer of RTWDOG peripheral base addresses */ +#define RTWDOG_BASE_ADDRS { RTWDOG_BASE } +/** Array initializer of RTWDOG peripheral base pointers */ +#define RTWDOG_BASE_PTRS { RTWDOG } +/** Interrupt vectors for the RTWDOG peripheral type */ +#define RTWDOG_IRQS { RTWDOG_IRQn } +/* Extra definition */ +#define RTWDOG_UPDATE_KEY (0xD928C520U) +#define RTWDOG_REFRESH_KEY (0xB480A602U) + + +/*! + * @} + */ /* end of group RTWDOG_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- SEMC Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup SEMC_Peripheral_Access_Layer SEMC Peripheral Access Layer + * @{ + */ + +/** SEMC - Register Layout Typedef */ +typedef struct { + __IO uint32_t MCR; /**< Module Control Register, offset: 0x0 */ + __IO uint32_t IOCR; /**< IO Mux Control Register, offset: 0x4 */ + __IO uint32_t BMCR0; /**< Master Bus (AXI) Control Register 0, offset: 0x8 */ + __IO uint32_t BMCR1; /**< Master Bus (AXI) Control Register 1, offset: 0xC */ + __IO uint32_t BR[9]; /**< Base Register 0 (For SDRAM CS0 device)..Base Register 8 (For NAND device), array offset: 0x10, array step: 0x4 */ + uint8_t RESERVED_0[4]; + __IO uint32_t INTEN; /**< Interrupt Enable Register, offset: 0x38 */ + __IO uint32_t INTR; /**< Interrupt Enable Register, offset: 0x3C */ + __IO uint32_t SDRAMCR0; /**< SDRAM control register 0, offset: 0x40 */ + __IO uint32_t SDRAMCR1; /**< SDRAM control register 1, offset: 0x44 */ + __IO uint32_t SDRAMCR2; /**< SDRAM control register 2, offset: 0x48 */ + __IO uint32_t SDRAMCR3; /**< SDRAM control register 3, offset: 0x4C */ + __IO uint32_t NANDCR0; /**< NAND control register 0, offset: 0x50 */ + __IO uint32_t NANDCR1; /**< NAND control register 1, offset: 0x54 */ + __IO uint32_t NANDCR2; /**< NAND control register 2, offset: 0x58 */ + __IO uint32_t NANDCR3; /**< NAND control register 3, offset: 0x5C */ + __IO uint32_t NORCR0; /**< NOR control register 0, offset: 0x60 */ + __IO uint32_t NORCR1; /**< NOR control register 1, offset: 0x64 */ + __IO uint32_t NORCR2; /**< NOR control register 2, offset: 0x68 */ + uint32_t NORCR3; /**< NOR control register 3, offset: 0x6C */ + __IO uint32_t SRAMCR0; /**< SRAM control register 0, offset: 0x70 */ + __IO uint32_t SRAMCR1; /**< SRAM control register 1, offset: 0x74 */ + __IO uint32_t SRAMCR2; /**< SRAM control register 2, offset: 0x78 */ + uint32_t SRAMCR3; /**< SRAM control register 3, offset: 0x7C */ + __IO uint32_t DBICR0; /**< DBI-B control register 0, offset: 0x80 */ + __IO uint32_t DBICR1; /**< DBI-B control register 1, offset: 0x84 */ + uint8_t RESERVED_1[8]; + __IO uint32_t IPCR0; /**< IP Command control register 0, offset: 0x90 */ + __IO uint32_t IPCR1; /**< IP Command control register 1, offset: 0x94 */ + __IO uint32_t IPCR2; /**< IP Command control register 2, offset: 0x98 */ + __IO uint32_t IPCMD; /**< IP Command register, offset: 0x9C */ + __IO uint32_t IPTXDAT; /**< TX DATA register (for IP Command), offset: 0xA0 */ + uint8_t RESERVED_2[12]; + __I uint32_t IPRXDAT; /**< RX DATA register (for IP Command), offset: 0xB0 */ + uint8_t RESERVED_3[12]; + __I uint32_t STS0; /**< Status register 0, offset: 0xC0 */ + uint32_t STS1; /**< Status register 1, offset: 0xC4 */ + __I uint32_t STS2; /**< Status register 2, offset: 0xC8 */ + uint32_t STS3; /**< Status register 3, offset: 0xCC */ + uint32_t STS4; /**< Status register 4, offset: 0xD0 */ + uint32_t STS5; /**< Status register 5, offset: 0xD4 */ + uint32_t STS6; /**< Status register 6, offset: 0xD8 */ + uint32_t STS7; /**< Status register 7, offset: 0xDC */ + uint32_t STS8; /**< Status register 8, offset: 0xE0 */ + uint32_t STS9; /**< Status register 9, offset: 0xE4 */ + uint32_t STS10; /**< Status register 10, offset: 0xE8 */ + uint32_t STS11; /**< Status register 11, offset: 0xEC */ + __I uint32_t STS12; /**< Status register 12, offset: 0xF0 */ + uint32_t STS13; /**< Status register 13, offset: 0xF4 */ + uint32_t STS14; /**< Status register 14, offset: 0xF8 */ + uint32_t STS15; /**< Status register 15, offset: 0xFC */ +} SEMC_Type; + +/* ---------------------------------------------------------------------------- + -- SEMC Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup SEMC_Register_Masks SEMC Register Masks + * @{ + */ + +/*! @name MCR - Module Control Register */ +/*! @{ */ +#define SEMC_MCR_SWRST_MASK (0x1U) +#define SEMC_MCR_SWRST_SHIFT (0U) +#define SEMC_MCR_SWRST(x) (((uint32_t)(((uint32_t)(x)) << SEMC_MCR_SWRST_SHIFT)) & SEMC_MCR_SWRST_MASK) +#define SEMC_MCR_MDIS_MASK (0x2U) +#define SEMC_MCR_MDIS_SHIFT (1U) +/*! MDIS - Module Disable + * 0b0..Module enabled + * 0b1..Module disabled. + */ +#define SEMC_MCR_MDIS(x) (((uint32_t)(((uint32_t)(x)) << SEMC_MCR_MDIS_SHIFT)) & SEMC_MCR_MDIS_MASK) +#define SEMC_MCR_DQSMD_MASK (0x4U) +#define SEMC_MCR_DQSMD_SHIFT (2U) +/*! DQSMD - DQS (read strobe) mode + * 0b0..Dummy read strobe loopbacked internally + * 0b1..Dummy read strobe loopbacked from DQS pad + */ +#define SEMC_MCR_DQSMD(x) (((uint32_t)(((uint32_t)(x)) << SEMC_MCR_DQSMD_SHIFT)) & SEMC_MCR_DQSMD_MASK) +#define SEMC_MCR_WPOL0_MASK (0x40U) +#define SEMC_MCR_WPOL0_SHIFT (6U) +/*! WPOL0 - WAIT/RDY# polarity for NOR/PSRAM + * 0b0..Low active + * 0b1..High active + */ +#define SEMC_MCR_WPOL0(x) (((uint32_t)(((uint32_t)(x)) << SEMC_MCR_WPOL0_SHIFT)) & SEMC_MCR_WPOL0_MASK) +#define SEMC_MCR_WPOL1_MASK (0x80U) +#define SEMC_MCR_WPOL1_SHIFT (7U) +/*! WPOL1 - WAIT/RDY# polarity for NAND + * 0b0..Low active + * 0b1..High active + */ +#define SEMC_MCR_WPOL1(x) (((uint32_t)(((uint32_t)(x)) << SEMC_MCR_WPOL1_SHIFT)) & SEMC_MCR_WPOL1_MASK) +#define SEMC_MCR_CTO_MASK (0xFF0000U) +#define SEMC_MCR_CTO_SHIFT (16U) +#define SEMC_MCR_CTO(x) (((uint32_t)(((uint32_t)(x)) << SEMC_MCR_CTO_SHIFT)) & SEMC_MCR_CTO_MASK) +#define SEMC_MCR_BTO_MASK (0x1F000000U) +#define SEMC_MCR_BTO_SHIFT (24U) +/*! BTO - Bus timeout cycles + * 0b00000..255*1 + * 0b00001-0b11110..255*2 - 255*2^30 + * 0b11111..255*2^31 + */ +#define SEMC_MCR_BTO(x) (((uint32_t)(((uint32_t)(x)) << SEMC_MCR_BTO_SHIFT)) & SEMC_MCR_BTO_MASK) +/*! @} */ + +/*! @name IOCR - IO Mux Control Register */ +/*! @{ */ +#define SEMC_IOCR_MUX_A8_MASK (0x7U) +#define SEMC_IOCR_MUX_A8_SHIFT (0U) +/*! MUX_A8 - SEMC_A8 output selection + * 0b000..SDRAM Address bit (A8) + * 0b001..NAND CE# + * 0b010..NOR CE# + * 0b011..PSRAM CE# + * 0b100..DBI CSX + * 0b101..SDRAM Address bit (A8) + * 0b110..SDRAM Address bit (A8) + * 0b111..SDRAM Address bit (A8) + */ +#define SEMC_IOCR_MUX_A8(x) (((uint32_t)(((uint32_t)(x)) << SEMC_IOCR_MUX_A8_SHIFT)) & SEMC_IOCR_MUX_A8_MASK) +#define SEMC_IOCR_MUX_CSX0_MASK (0x38U) +#define SEMC_IOCR_MUX_CSX0_SHIFT (3U) +/*! MUX_CSX0 - SEMC_CSX0 output selection + * 0b000..NOR/PSRAM Address bit 24 (A24) + * 0b001..SDRAM CS1 + * 0b010..SDRAM CS2 + * 0b011..SDRAM CS3 + * 0b100..NAND CE# + * 0b101..NOR CE# + * 0b110..PSRAM CE# + * 0b111..DBI CSX + */ +#define SEMC_IOCR_MUX_CSX0(x) (((uint32_t)(((uint32_t)(x)) << SEMC_IOCR_MUX_CSX0_SHIFT)) & SEMC_IOCR_MUX_CSX0_MASK) +#define SEMC_IOCR_MUX_CSX1_MASK (0x1C0U) +#define SEMC_IOCR_MUX_CSX1_SHIFT (6U) +/*! MUX_CSX1 - SEMC_CSX1 output selection + * 0b000..NOR/PSRAM Address bit 25 (A25) + * 0b001..SDRAM CS1 + * 0b010..SDRAM CS2 + * 0b011..SDRAM CS3 + * 0b100..NAND CE# + * 0b101..NOR CE# + * 0b110..PSRAM CE# + * 0b111..DBI CSX + */ +#define SEMC_IOCR_MUX_CSX1(x) (((uint32_t)(((uint32_t)(x)) << SEMC_IOCR_MUX_CSX1_SHIFT)) & SEMC_IOCR_MUX_CSX1_MASK) +#define SEMC_IOCR_MUX_CSX2_MASK (0xE00U) +#define SEMC_IOCR_MUX_CSX2_SHIFT (9U) +/*! MUX_CSX2 - SEMC_CSX2 output selection + * 0b000..NOR/PSRAM Address bit 26 (A26) + * 0b001..SDRAM CS1 + * 0b010..SDRAM CS2 + * 0b011..SDRAM CS3 + * 0b100..NAND CE# + * 0b101..NOR CE# + * 0b110..PSRAM CE# + * 0b111..DBI CSX + */ +#define SEMC_IOCR_MUX_CSX2(x) (((uint32_t)(((uint32_t)(x)) << SEMC_IOCR_MUX_CSX2_SHIFT)) & SEMC_IOCR_MUX_CSX2_MASK) +#define SEMC_IOCR_MUX_CSX3_MASK (0x7000U) +#define SEMC_IOCR_MUX_CSX3_SHIFT (12U) +/*! MUX_CSX3 - SEMC_CSX3 output selection + * 0b000..NOR/PSRAM Address bit 27 (A27) + * 0b001..SDRAM CS1 + * 0b010..SDRAM CS2 + * 0b011..SDRAM CS3 + * 0b100..NAND CE# + * 0b101..NOR CE# + * 0b110..PSRAM CE# + * 0b111..DBI CSX + */ +#define SEMC_IOCR_MUX_CSX3(x) (((uint32_t)(((uint32_t)(x)) << SEMC_IOCR_MUX_CSX3_SHIFT)) & SEMC_IOCR_MUX_CSX3_MASK) +#define SEMC_IOCR_MUX_RDY_MASK (0x38000U) +#define SEMC_IOCR_MUX_RDY_SHIFT (15U) +/*! MUX_RDY - SEMC_RDY function selection + * 0b000..NAND Ready/Wait# input + * 0b001..SDRAM CS1 + * 0b010..SDRAM CS2 + * 0b011..SDRAM CS3 + * 0b100..NOR CE# + * 0b101..PSRAM CE# + * 0b110..DBI CSX + * 0b111..NOR/PSRAM Address bit 27 + */ +#define SEMC_IOCR_MUX_RDY(x) (((uint32_t)(((uint32_t)(x)) << SEMC_IOCR_MUX_RDY_SHIFT)) & SEMC_IOCR_MUX_RDY_MASK) +/*! @} */ + +/*! @name BMCR0 - Master Bus (AXI) Control Register 0 */ +/*! @{ */ +#define SEMC_BMCR0_WQOS_MASK (0xFU) +#define SEMC_BMCR0_WQOS_SHIFT (0U) +#define SEMC_BMCR0_WQOS(x) (((uint32_t)(((uint32_t)(x)) << SEMC_BMCR0_WQOS_SHIFT)) & SEMC_BMCR0_WQOS_MASK) +#define SEMC_BMCR0_WAGE_MASK (0xF0U) +#define SEMC_BMCR0_WAGE_SHIFT (4U) +#define SEMC_BMCR0_WAGE(x) (((uint32_t)(((uint32_t)(x)) << SEMC_BMCR0_WAGE_SHIFT)) & SEMC_BMCR0_WAGE_MASK) +#define SEMC_BMCR0_WSH_MASK (0xFF00U) +#define SEMC_BMCR0_WSH_SHIFT (8U) +#define SEMC_BMCR0_WSH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_BMCR0_WSH_SHIFT)) & SEMC_BMCR0_WSH_MASK) +#define SEMC_BMCR0_WRWS_MASK (0xFF0000U) +#define SEMC_BMCR0_WRWS_SHIFT (16U) +#define SEMC_BMCR0_WRWS(x) (((uint32_t)(((uint32_t)(x)) << SEMC_BMCR0_WRWS_SHIFT)) & SEMC_BMCR0_WRWS_MASK) +/*! @} */ + +/*! @name BMCR1 - Master Bus (AXI) Control Register 1 */ +/*! @{ */ +#define SEMC_BMCR1_WQOS_MASK (0xFU) +#define SEMC_BMCR1_WQOS_SHIFT (0U) +#define SEMC_BMCR1_WQOS(x) (((uint32_t)(((uint32_t)(x)) << SEMC_BMCR1_WQOS_SHIFT)) & SEMC_BMCR1_WQOS_MASK) +#define SEMC_BMCR1_WAGE_MASK (0xF0U) +#define SEMC_BMCR1_WAGE_SHIFT (4U) +#define SEMC_BMCR1_WAGE(x) (((uint32_t)(((uint32_t)(x)) << SEMC_BMCR1_WAGE_SHIFT)) & SEMC_BMCR1_WAGE_MASK) +#define SEMC_BMCR1_WPH_MASK (0xFF00U) +#define SEMC_BMCR1_WPH_SHIFT (8U) +#define SEMC_BMCR1_WPH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_BMCR1_WPH_SHIFT)) & SEMC_BMCR1_WPH_MASK) +#define SEMC_BMCR1_WRWS_MASK (0xFF0000U) +#define SEMC_BMCR1_WRWS_SHIFT (16U) +#define SEMC_BMCR1_WRWS(x) (((uint32_t)(((uint32_t)(x)) << SEMC_BMCR1_WRWS_SHIFT)) & SEMC_BMCR1_WRWS_MASK) +#define SEMC_BMCR1_WBR_MASK (0xFF000000U) +#define SEMC_BMCR1_WBR_SHIFT (24U) +#define SEMC_BMCR1_WBR(x) (((uint32_t)(((uint32_t)(x)) << SEMC_BMCR1_WBR_SHIFT)) & SEMC_BMCR1_WBR_MASK) +/*! @} */ + +/*! @name BR - Base Register 0 (For SDRAM CS0 device)..Base Register 8 (For NAND device) */ +/*! @{ */ +#define SEMC_BR_VLD_MASK (0x1U) +#define SEMC_BR_VLD_SHIFT (0U) +#define SEMC_BR_VLD(x) (((uint32_t)(((uint32_t)(x)) << SEMC_BR_VLD_SHIFT)) & SEMC_BR_VLD_MASK) +#define SEMC_BR_MS_MASK (0x3EU) +#define SEMC_BR_MS_SHIFT (1U) +/*! MS - Memory size + * 0b00000..4KB + * 0b00001..8KB + * 0b00010..16KB + * 0b00011..32KB + * 0b00100..64KB + * 0b00101..128KB + * 0b00110..256KB + * 0b00111..512KB + * 0b01000..1MB + * 0b01001..2MB + * 0b01010..4MB + * 0b01011..8MB + * 0b01100..16MB + * 0b01101..32MB + * 0b01110..64MB + * 0b01111..128MB + * 0b10000..256MB + * 0b10001..512MB + * 0b10010..1GB + * 0b10011..2GB + * 0b10100..4GB + * 0b10101..4GB + * 0b10110..4GB + * 0b10111..4GB + * 0b11000..4GB + * 0b11001..4GB + * 0b11010..4GB + * 0b11011..4GB + * 0b11100..4GB + * 0b11101..4GB + * 0b11110..4GB + * 0b11111..4GB + */ +#define SEMC_BR_MS(x) (((uint32_t)(((uint32_t)(x)) << SEMC_BR_MS_SHIFT)) & SEMC_BR_MS_MASK) +#define SEMC_BR_BA_MASK (0xFFFFF000U) +#define SEMC_BR_BA_SHIFT (12U) +#define SEMC_BR_BA(x) (((uint32_t)(((uint32_t)(x)) << SEMC_BR_BA_SHIFT)) & SEMC_BR_BA_MASK) +/*! @} */ + +/* The count of SEMC_BR */ +#define SEMC_BR_COUNT (9U) + +/*! @name INTEN - Interrupt Enable Register */ +/*! @{ */ +#define SEMC_INTEN_IPCMDDONEEN_MASK (0x1U) +#define SEMC_INTEN_IPCMDDONEEN_SHIFT (0U) +#define SEMC_INTEN_IPCMDDONEEN(x) (((uint32_t)(((uint32_t)(x)) << SEMC_INTEN_IPCMDDONEEN_SHIFT)) & SEMC_INTEN_IPCMDDONEEN_MASK) +#define SEMC_INTEN_IPCMDERREN_MASK (0x2U) +#define SEMC_INTEN_IPCMDERREN_SHIFT (1U) +#define SEMC_INTEN_IPCMDERREN(x) (((uint32_t)(((uint32_t)(x)) << SEMC_INTEN_IPCMDERREN_SHIFT)) & SEMC_INTEN_IPCMDERREN_MASK) +#define SEMC_INTEN_AXICMDERREN_MASK (0x4U) +#define SEMC_INTEN_AXICMDERREN_SHIFT (2U) +#define SEMC_INTEN_AXICMDERREN(x) (((uint32_t)(((uint32_t)(x)) << SEMC_INTEN_AXICMDERREN_SHIFT)) & SEMC_INTEN_AXICMDERREN_MASK) +#define SEMC_INTEN_AXIBUSERREN_MASK (0x8U) +#define SEMC_INTEN_AXIBUSERREN_SHIFT (3U) +#define SEMC_INTEN_AXIBUSERREN(x) (((uint32_t)(((uint32_t)(x)) << SEMC_INTEN_AXIBUSERREN_SHIFT)) & SEMC_INTEN_AXIBUSERREN_MASK) +#define SEMC_INTEN_NDPAGEENDEN_MASK (0x10U) +#define SEMC_INTEN_NDPAGEENDEN_SHIFT (4U) +/*! NDPAGEENDEN - This bit enable/disable the NDPAGEEND interrupt generation. + * 0b0..Disable + * 0b1..Enable + */ +#define SEMC_INTEN_NDPAGEENDEN(x) (((uint32_t)(((uint32_t)(x)) << SEMC_INTEN_NDPAGEENDEN_SHIFT)) & SEMC_INTEN_NDPAGEENDEN_MASK) +#define SEMC_INTEN_NDNOPENDEN_MASK (0x20U) +#define SEMC_INTEN_NDNOPENDEN_SHIFT (5U) +/*! NDNOPENDEN - This bit enable/disable the NDNOPEND interrupt generation. + * 0b0..Disable + * 0b1..Enable + */ +#define SEMC_INTEN_NDNOPENDEN(x) (((uint32_t)(((uint32_t)(x)) << SEMC_INTEN_NDNOPENDEN_SHIFT)) & SEMC_INTEN_NDNOPENDEN_MASK) +/*! @} */ + +/*! @name INTR - Interrupt Enable Register */ +/*! @{ */ +#define SEMC_INTR_IPCMDDONE_MASK (0x1U) +#define SEMC_INTR_IPCMDDONE_SHIFT (0U) +#define SEMC_INTR_IPCMDDONE(x) (((uint32_t)(((uint32_t)(x)) << SEMC_INTR_IPCMDDONE_SHIFT)) & SEMC_INTR_IPCMDDONE_MASK) +#define SEMC_INTR_IPCMDERR_MASK (0x2U) +#define SEMC_INTR_IPCMDERR_SHIFT (1U) +#define SEMC_INTR_IPCMDERR(x) (((uint32_t)(((uint32_t)(x)) << SEMC_INTR_IPCMDERR_SHIFT)) & SEMC_INTR_IPCMDERR_MASK) +#define SEMC_INTR_AXICMDERR_MASK (0x4U) +#define SEMC_INTR_AXICMDERR_SHIFT (2U) +#define SEMC_INTR_AXICMDERR(x) (((uint32_t)(((uint32_t)(x)) << SEMC_INTR_AXICMDERR_SHIFT)) & SEMC_INTR_AXICMDERR_MASK) +#define SEMC_INTR_AXIBUSERR_MASK (0x8U) +#define SEMC_INTR_AXIBUSERR_SHIFT (3U) +#define SEMC_INTR_AXIBUSERR(x) (((uint32_t)(((uint32_t)(x)) << SEMC_INTR_AXIBUSERR_SHIFT)) & SEMC_INTR_AXIBUSERR_MASK) +#define SEMC_INTR_NDPAGEEND_MASK (0x10U) +#define SEMC_INTR_NDPAGEEND_SHIFT (4U) +#define SEMC_INTR_NDPAGEEND(x) (((uint32_t)(((uint32_t)(x)) << SEMC_INTR_NDPAGEEND_SHIFT)) & SEMC_INTR_NDPAGEEND_MASK) +#define SEMC_INTR_NDNOPEND_MASK (0x20U) +#define SEMC_INTR_NDNOPEND_SHIFT (5U) +#define SEMC_INTR_NDNOPEND(x) (((uint32_t)(((uint32_t)(x)) << SEMC_INTR_NDNOPEND_SHIFT)) & SEMC_INTR_NDNOPEND_MASK) +/*! @} */ + +/*! @name SDRAMCR0 - SDRAM control register 0 */ +/*! @{ */ +#define SEMC_SDRAMCR0_PS_MASK (0x1U) +#define SEMC_SDRAMCR0_PS_SHIFT (0U) +/*! PS - Port Size + * 0b0..8bit + * 0b1..16bit + */ +#define SEMC_SDRAMCR0_PS(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR0_PS_SHIFT)) & SEMC_SDRAMCR0_PS_MASK) +#define SEMC_SDRAMCR0_BL_MASK (0x70U) +#define SEMC_SDRAMCR0_BL_SHIFT (4U) +/*! BL - Burst Length + * 0b000..1 + * 0b001..2 + * 0b010..4 + * 0b011..8 + * 0b100..8 + * 0b101..8 + * 0b110..8 + * 0b111..8 + */ +#define SEMC_SDRAMCR0_BL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR0_BL_SHIFT)) & SEMC_SDRAMCR0_BL_MASK) +#define SEMC_SDRAMCR0_COL_MASK (0x300U) +#define SEMC_SDRAMCR0_COL_SHIFT (8U) +/*! COL - Column address bit number + * 0b00..12 bit + * 0b01..11 bit + * 0b10..10 bit + * 0b11..9 bit + */ +#define SEMC_SDRAMCR0_COL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR0_COL_SHIFT)) & SEMC_SDRAMCR0_COL_MASK) +#define SEMC_SDRAMCR0_CL_MASK (0xC00U) +#define SEMC_SDRAMCR0_CL_SHIFT (10U) +/*! CL - CAS Latency + * 0b00..1 + * 0b01..1 + * 0b10..2 + * 0b11..3 + */ +#define SEMC_SDRAMCR0_CL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR0_CL_SHIFT)) & SEMC_SDRAMCR0_CL_MASK) +/*! @} */ + +/*! @name SDRAMCR1 - SDRAM control register 1 */ +/*! @{ */ +#define SEMC_SDRAMCR1_PRE2ACT_MASK (0xFU) +#define SEMC_SDRAMCR1_PRE2ACT_SHIFT (0U) +#define SEMC_SDRAMCR1_PRE2ACT(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR1_PRE2ACT_SHIFT)) & SEMC_SDRAMCR1_PRE2ACT_MASK) +#define SEMC_SDRAMCR1_ACT2RW_MASK (0xF0U) +#define SEMC_SDRAMCR1_ACT2RW_SHIFT (4U) +#define SEMC_SDRAMCR1_ACT2RW(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR1_ACT2RW_SHIFT)) & SEMC_SDRAMCR1_ACT2RW_MASK) +#define SEMC_SDRAMCR1_RFRC_MASK (0x1F00U) +#define SEMC_SDRAMCR1_RFRC_SHIFT (8U) +#define SEMC_SDRAMCR1_RFRC(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR1_RFRC_SHIFT)) & SEMC_SDRAMCR1_RFRC_MASK) +#define SEMC_SDRAMCR1_WRC_MASK (0xE000U) +#define SEMC_SDRAMCR1_WRC_SHIFT (13U) +#define SEMC_SDRAMCR1_WRC(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR1_WRC_SHIFT)) & SEMC_SDRAMCR1_WRC_MASK) +#define SEMC_SDRAMCR1_CKEOFF_MASK (0xF0000U) +#define SEMC_SDRAMCR1_CKEOFF_SHIFT (16U) +#define SEMC_SDRAMCR1_CKEOFF(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR1_CKEOFF_SHIFT)) & SEMC_SDRAMCR1_CKEOFF_MASK) +#define SEMC_SDRAMCR1_ACT2PRE_MASK (0xF00000U) +#define SEMC_SDRAMCR1_ACT2PRE_SHIFT (20U) +#define SEMC_SDRAMCR1_ACT2PRE(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR1_ACT2PRE_SHIFT)) & SEMC_SDRAMCR1_ACT2PRE_MASK) +/*! @} */ + +/*! @name SDRAMCR2 - SDRAM control register 2 */ +/*! @{ */ +#define SEMC_SDRAMCR2_SRRC_MASK (0xFFU) +#define SEMC_SDRAMCR2_SRRC_SHIFT (0U) +#define SEMC_SDRAMCR2_SRRC(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR2_SRRC_SHIFT)) & SEMC_SDRAMCR2_SRRC_MASK) +#define SEMC_SDRAMCR2_REF2REF_MASK (0xFF00U) +#define SEMC_SDRAMCR2_REF2REF_SHIFT (8U) +#define SEMC_SDRAMCR2_REF2REF(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR2_REF2REF_SHIFT)) & SEMC_SDRAMCR2_REF2REF_MASK) +#define SEMC_SDRAMCR2_ACT2ACT_MASK (0xFF0000U) +#define SEMC_SDRAMCR2_ACT2ACT_SHIFT (16U) +#define SEMC_SDRAMCR2_ACT2ACT(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR2_ACT2ACT_SHIFT)) & SEMC_SDRAMCR2_ACT2ACT_MASK) +#define SEMC_SDRAMCR2_ITO_MASK (0xFF000000U) +#define SEMC_SDRAMCR2_ITO_SHIFT (24U) +/*! ITO - SDRAM Idle timeout + * 0b00000000..IDLE timeout period is 256*Prescale period. + * 0b00000001-0b11111111..IDLE timeout period is ITO*Prescale period. + */ +#define SEMC_SDRAMCR2_ITO(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR2_ITO_SHIFT)) & SEMC_SDRAMCR2_ITO_MASK) +/*! @} */ + +/*! @name SDRAMCR3 - SDRAM control register 3 */ +/*! @{ */ +#define SEMC_SDRAMCR3_REN_MASK (0x1U) +#define SEMC_SDRAMCR3_REN_SHIFT (0U) +#define SEMC_SDRAMCR3_REN(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR3_REN_SHIFT)) & SEMC_SDRAMCR3_REN_MASK) +#define SEMC_SDRAMCR3_REBL_MASK (0xEU) +#define SEMC_SDRAMCR3_REBL_SHIFT (1U) +/*! REBL - Refresh burst length + * 0b000..1 + * 0b001..2 + * 0b010..3 + * 0b011..4 + * 0b100..5 + * 0b101..6 + * 0b110..7 + * 0b111..8 + */ +#define SEMC_SDRAMCR3_REBL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR3_REBL_SHIFT)) & SEMC_SDRAMCR3_REBL_MASK) +#define SEMC_SDRAMCR3_PRESCALE_MASK (0xFF00U) +#define SEMC_SDRAMCR3_PRESCALE_SHIFT (8U) +/*! PRESCALE - Prescaler timer period + * 0b00000000..256*16 cycle + * 0b00000001-0b11111111..PRESCALE*16 cycle + */ +#define SEMC_SDRAMCR3_PRESCALE(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR3_PRESCALE_SHIFT)) & SEMC_SDRAMCR3_PRESCALE_MASK) +#define SEMC_SDRAMCR3_RT_MASK (0xFF0000U) +#define SEMC_SDRAMCR3_RT_SHIFT (16U) +/*! RT - Refresh timer period + * 0b00000000..256*Prescaler period + * 0b00000001-0b11111111..RT*Prescaler period + */ +#define SEMC_SDRAMCR3_RT(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR3_RT_SHIFT)) & SEMC_SDRAMCR3_RT_MASK) +#define SEMC_SDRAMCR3_UT_MASK (0xFF000000U) +#define SEMC_SDRAMCR3_UT_SHIFT (24U) +/*! UT - Refresh urgent threshold + * 0b00000000..256*Prescaler period + * 0b00000001-0b11111111..UT*Prescaler period + */ +#define SEMC_SDRAMCR3_UT(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR3_UT_SHIFT)) & SEMC_SDRAMCR3_UT_MASK) +/*! @} */ + +/*! @name NANDCR0 - NAND control register 0 */ +/*! @{ */ +#define SEMC_NANDCR0_PS_MASK (0x1U) +#define SEMC_NANDCR0_PS_SHIFT (0U) +/*! PS - Port Size + * 0b0..8bit + * 0b1..16bit + */ +#define SEMC_NANDCR0_PS(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR0_PS_SHIFT)) & SEMC_NANDCR0_PS_MASK) +#define SEMC_NANDCR0_BL_MASK (0x70U) +#define SEMC_NANDCR0_BL_SHIFT (4U) +/*! BL - Burst Length + * 0b000..1 + * 0b001..2 + * 0b010..4 + * 0b011..8 + * 0b100..16 + * 0b101..32 + * 0b110..64 + * 0b111..64 + */ +#define SEMC_NANDCR0_BL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR0_BL_SHIFT)) & SEMC_NANDCR0_BL_MASK) +#define SEMC_NANDCR0_EDO_MASK (0x80U) +#define SEMC_NANDCR0_EDO_SHIFT (7U) +/*! EDO - EDO mode enabled + * 0b0..EDO mode disabled + * 0b1..EDO mode enabled + */ +#define SEMC_NANDCR0_EDO(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR0_EDO_SHIFT)) & SEMC_NANDCR0_EDO_MASK) +#define SEMC_NANDCR0_COL_MASK (0x700U) +#define SEMC_NANDCR0_COL_SHIFT (8U) +/*! COL - Column address bit number + * 0b000..16 + * 0b001..15 + * 0b010..14 + * 0b011..13 + * 0b100..12 + * 0b101..11 + * 0b110..10 + * 0b111..9 + */ +#define SEMC_NANDCR0_COL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR0_COL_SHIFT)) & SEMC_NANDCR0_COL_MASK) +/*! @} */ + +/*! @name NANDCR1 - NAND control register 1 */ +/*! @{ */ +#define SEMC_NANDCR1_CES_MASK (0xFU) +#define SEMC_NANDCR1_CES_SHIFT (0U) +#define SEMC_NANDCR1_CES(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR1_CES_SHIFT)) & SEMC_NANDCR1_CES_MASK) +#define SEMC_NANDCR1_CEH_MASK (0xF0U) +#define SEMC_NANDCR1_CEH_SHIFT (4U) +#define SEMC_NANDCR1_CEH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR1_CEH_SHIFT)) & SEMC_NANDCR1_CEH_MASK) +#define SEMC_NANDCR1_WEL_MASK (0xF00U) +#define SEMC_NANDCR1_WEL_SHIFT (8U) +#define SEMC_NANDCR1_WEL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR1_WEL_SHIFT)) & SEMC_NANDCR1_WEL_MASK) +#define SEMC_NANDCR1_WEH_MASK (0xF000U) +#define SEMC_NANDCR1_WEH_SHIFT (12U) +#define SEMC_NANDCR1_WEH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR1_WEH_SHIFT)) & SEMC_NANDCR1_WEH_MASK) +#define SEMC_NANDCR1_REL_MASK (0xF0000U) +#define SEMC_NANDCR1_REL_SHIFT (16U) +#define SEMC_NANDCR1_REL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR1_REL_SHIFT)) & SEMC_NANDCR1_REL_MASK) +#define SEMC_NANDCR1_REH_MASK (0xF00000U) +#define SEMC_NANDCR1_REH_SHIFT (20U) +#define SEMC_NANDCR1_REH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR1_REH_SHIFT)) & SEMC_NANDCR1_REH_MASK) +#define SEMC_NANDCR1_TA_MASK (0xF000000U) +#define SEMC_NANDCR1_TA_SHIFT (24U) +#define SEMC_NANDCR1_TA(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR1_TA_SHIFT)) & SEMC_NANDCR1_TA_MASK) +#define SEMC_NANDCR1_CEITV_MASK (0xF0000000U) +#define SEMC_NANDCR1_CEITV_SHIFT (28U) +#define SEMC_NANDCR1_CEITV(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR1_CEITV_SHIFT)) & SEMC_NANDCR1_CEITV_MASK) +/*! @} */ + +/*! @name NANDCR2 - NAND control register 2 */ +/*! @{ */ +#define SEMC_NANDCR2_TWHR_MASK (0x3FU) +#define SEMC_NANDCR2_TWHR_SHIFT (0U) +#define SEMC_NANDCR2_TWHR(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR2_TWHR_SHIFT)) & SEMC_NANDCR2_TWHR_MASK) +#define SEMC_NANDCR2_TRHW_MASK (0xFC0U) +#define SEMC_NANDCR2_TRHW_SHIFT (6U) +#define SEMC_NANDCR2_TRHW(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR2_TRHW_SHIFT)) & SEMC_NANDCR2_TRHW_MASK) +#define SEMC_NANDCR2_TADL_MASK (0x3F000U) +#define SEMC_NANDCR2_TADL_SHIFT (12U) +#define SEMC_NANDCR2_TADL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR2_TADL_SHIFT)) & SEMC_NANDCR2_TADL_MASK) +#define SEMC_NANDCR2_TRR_MASK (0xFC0000U) +#define SEMC_NANDCR2_TRR_SHIFT (18U) +#define SEMC_NANDCR2_TRR(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR2_TRR_SHIFT)) & SEMC_NANDCR2_TRR_MASK) +#define SEMC_NANDCR2_TWB_MASK (0x3F000000U) +#define SEMC_NANDCR2_TWB_SHIFT (24U) +#define SEMC_NANDCR2_TWB(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR2_TWB_SHIFT)) & SEMC_NANDCR2_TWB_MASK) +/*! @} */ + +/*! @name NANDCR3 - NAND control register 3 */ +/*! @{ */ +#define SEMC_NANDCR3_NDOPT1_MASK (0x1U) +#define SEMC_NANDCR3_NDOPT1_SHIFT (0U) +#define SEMC_NANDCR3_NDOPT1(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR3_NDOPT1_SHIFT)) & SEMC_NANDCR3_NDOPT1_MASK) +#define SEMC_NANDCR3_NDOPT2_MASK (0x2U) +#define SEMC_NANDCR3_NDOPT2_SHIFT (1U) +#define SEMC_NANDCR3_NDOPT2(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR3_NDOPT2_SHIFT)) & SEMC_NANDCR3_NDOPT2_MASK) +#define SEMC_NANDCR3_NDOPT3_MASK (0x4U) +#define SEMC_NANDCR3_NDOPT3_SHIFT (2U) +#define SEMC_NANDCR3_NDOPT3(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR3_NDOPT3_SHIFT)) & SEMC_NANDCR3_NDOPT3_MASK) +/*! @} */ + +/*! @name NORCR0 - NOR control register 0 */ +/*! @{ */ +#define SEMC_NORCR0_PS_MASK (0x1U) +#define SEMC_NORCR0_PS_SHIFT (0U) +/*! PS - Port Size + * 0b0..8bit + * 0b1..16bit + */ +#define SEMC_NORCR0_PS(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR0_PS_SHIFT)) & SEMC_NORCR0_PS_MASK) +#define SEMC_NORCR0_BL_MASK (0x70U) +#define SEMC_NORCR0_BL_SHIFT (4U) +/*! BL - Burst Length + * 0b000..1 + * 0b001..2 + * 0b010..4 + * 0b011..8 + * 0b100..16 + * 0b101..32 + * 0b110..64 + * 0b111..64 + */ +#define SEMC_NORCR0_BL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR0_BL_SHIFT)) & SEMC_NORCR0_BL_MASK) +#define SEMC_NORCR0_AM_MASK (0x300U) +#define SEMC_NORCR0_AM_SHIFT (8U) +/*! AM - Address Mode + * 0b00..Address/Data MUX mode + * 0b01..Advanced Address/Data MUX mode + * 0b10..Address/Data non-MUX mode + * 0b11..Address/Data non-MUX mode + */ +#define SEMC_NORCR0_AM(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR0_AM_SHIFT)) & SEMC_NORCR0_AM_MASK) +#define SEMC_NORCR0_ADVP_MASK (0x400U) +#define SEMC_NORCR0_ADVP_SHIFT (10U) +/*! ADVP - ADV# polarity + * 0b0..ADV# is Low Active. In ASYNC mode, device sample address with ADV# rise edge; In SYNC mode, device sample address when ADV# is LOW. + * 0b1..ADV# is High Active. In ASYNC mode, device sample address with ADV# fall edge; In SYNC mode, device sample address when ADV# is HIGH. + */ +#define SEMC_NORCR0_ADVP(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR0_ADVP_SHIFT)) & SEMC_NORCR0_ADVP_MASK) +#define SEMC_NORCR0_COL_MASK (0xF000U) +#define SEMC_NORCR0_COL_SHIFT (12U) +/*! COL - Column Address bit width + * 0b0000..12 Bits + * 0b0001..11 Bits + * 0b0010..10 Bits + * 0b0011..9 Bits + * 0b0100..8 Bits + * 0b0101..7 Bits + * 0b0110..6 Bits + * 0b0111..5 Bits + * 0b1000..4 Bits + * 0b1001..3 Bits + * 0b1010..2 Bits + * 0b1011..12 Bits + * 0b1100..12 Bits + * 0b1101..12 Bits + * 0b1110..12 Bits + * 0b1111..12 Bits + */ +#define SEMC_NORCR0_COL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR0_COL_SHIFT)) & SEMC_NORCR0_COL_MASK) +/*! @} */ + +/*! @name NORCR1 - NOR control register 1 */ +/*! @{ */ +#define SEMC_NORCR1_CES_MASK (0xFU) +#define SEMC_NORCR1_CES_SHIFT (0U) +#define SEMC_NORCR1_CES(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR1_CES_SHIFT)) & SEMC_NORCR1_CES_MASK) +#define SEMC_NORCR1_CEH_MASK (0xF0U) +#define SEMC_NORCR1_CEH_SHIFT (4U) +#define SEMC_NORCR1_CEH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR1_CEH_SHIFT)) & SEMC_NORCR1_CEH_MASK) +#define SEMC_NORCR1_AS_MASK (0xF00U) +#define SEMC_NORCR1_AS_SHIFT (8U) +#define SEMC_NORCR1_AS(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR1_AS_SHIFT)) & SEMC_NORCR1_AS_MASK) +#define SEMC_NORCR1_AH_MASK (0xF000U) +#define SEMC_NORCR1_AH_SHIFT (12U) +#define SEMC_NORCR1_AH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR1_AH_SHIFT)) & SEMC_NORCR1_AH_MASK) +#define SEMC_NORCR1_WEL_MASK (0xF0000U) +#define SEMC_NORCR1_WEL_SHIFT (16U) +#define SEMC_NORCR1_WEL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR1_WEL_SHIFT)) & SEMC_NORCR1_WEL_MASK) +#define SEMC_NORCR1_WEH_MASK (0xF00000U) +#define SEMC_NORCR1_WEH_SHIFT (20U) +#define SEMC_NORCR1_WEH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR1_WEH_SHIFT)) & SEMC_NORCR1_WEH_MASK) +#define SEMC_NORCR1_REL_MASK (0xF000000U) +#define SEMC_NORCR1_REL_SHIFT (24U) +#define SEMC_NORCR1_REL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR1_REL_SHIFT)) & SEMC_NORCR1_REL_MASK) +#define SEMC_NORCR1_REH_MASK (0xF0000000U) +#define SEMC_NORCR1_REH_SHIFT (28U) +#define SEMC_NORCR1_REH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR1_REH_SHIFT)) & SEMC_NORCR1_REH_MASK) +/*! @} */ + +/*! @name NORCR2 - NOR control register 2 */ +/*! @{ */ +#define SEMC_NORCR2_WDS_MASK (0xFU) +#define SEMC_NORCR2_WDS_SHIFT (0U) +#define SEMC_NORCR2_WDS(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR2_WDS_SHIFT)) & SEMC_NORCR2_WDS_MASK) +#define SEMC_NORCR2_WDH_MASK (0xF0U) +#define SEMC_NORCR2_WDH_SHIFT (4U) +#define SEMC_NORCR2_WDH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR2_WDH_SHIFT)) & SEMC_NORCR2_WDH_MASK) +#define SEMC_NORCR2_TA_MASK (0xF00U) +#define SEMC_NORCR2_TA_SHIFT (8U) +#define SEMC_NORCR2_TA(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR2_TA_SHIFT)) & SEMC_NORCR2_TA_MASK) +#define SEMC_NORCR2_AWDH_MASK (0xF000U) +#define SEMC_NORCR2_AWDH_SHIFT (12U) +#define SEMC_NORCR2_AWDH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR2_AWDH_SHIFT)) & SEMC_NORCR2_AWDH_MASK) +#define SEMC_NORCR2_LC_MASK (0xF0000U) +#define SEMC_NORCR2_LC_SHIFT (16U) +#define SEMC_NORCR2_LC(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR2_LC_SHIFT)) & SEMC_NORCR2_LC_MASK) +#define SEMC_NORCR2_RD_MASK (0xF00000U) +#define SEMC_NORCR2_RD_SHIFT (20U) +#define SEMC_NORCR2_RD(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR2_RD_SHIFT)) & SEMC_NORCR2_RD_MASK) +#define SEMC_NORCR2_CEITV_MASK (0xF000000U) +#define SEMC_NORCR2_CEITV_SHIFT (24U) +#define SEMC_NORCR2_CEITV(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR2_CEITV_SHIFT)) & SEMC_NORCR2_CEITV_MASK) +/*! @} */ + +/*! @name SRAMCR0 - SRAM control register 0 */ +/*! @{ */ +#define SEMC_SRAMCR0_PS_MASK (0x1U) +#define SEMC_SRAMCR0_PS_SHIFT (0U) +/*! PS - Port Size + * 0b0..8bit + * 0b1..16bit + */ +#define SEMC_SRAMCR0_PS(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR0_PS_SHIFT)) & SEMC_SRAMCR0_PS_MASK) +#define SEMC_SRAMCR0_BL_MASK (0x70U) +#define SEMC_SRAMCR0_BL_SHIFT (4U) +/*! BL - Burst Length + * 0b000..1 + * 0b001..2 + * 0b010..4 + * 0b011..8 + * 0b100..16 + * 0b101..32 + * 0b110..64 + * 0b111..64 + */ +#define SEMC_SRAMCR0_BL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR0_BL_SHIFT)) & SEMC_SRAMCR0_BL_MASK) +#define SEMC_SRAMCR0_AM_MASK (0x300U) +#define SEMC_SRAMCR0_AM_SHIFT (8U) +/*! AM - Address Mode + * 0b00..Address/Data MUX mode + * 0b01..Advanced Address/Data MUX mode + * 0b10..Address/Data non-MUX mode + * 0b11..Address/Data non-MUX mode + */ +#define SEMC_SRAMCR0_AM(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR0_AM_SHIFT)) & SEMC_SRAMCR0_AM_MASK) +#define SEMC_SRAMCR0_ADVP_MASK (0x400U) +#define SEMC_SRAMCR0_ADVP_SHIFT (10U) +/*! ADVP - ADV# polarity + * 0b0..ADV# is Low Active. In ASYNC mode, device sample address with ADV# rise edge; In SYNC mode, device sample address when ADV# is LOW. + * 0b1..ADV# is High Active. In ASYNC mode, device sample address with ADV# fall edge; In SYNC mode, device sample address when ADV# is HIGH. + */ +#define SEMC_SRAMCR0_ADVP(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR0_ADVP_SHIFT)) & SEMC_SRAMCR0_ADVP_MASK) +#define SEMC_SRAMCR0_COL_MASK (0xF000U) +#define SEMC_SRAMCR0_COL_SHIFT (12U) +/*! COL - Column Address bit width + * 0b0000..12 Bits + * 0b0001..11 Bits + * 0b0010..10 Bits + * 0b0011..9 Bits + * 0b0100..8 Bits + * 0b0101..7 Bits + * 0b0110..6 Bits + * 0b0111..5 Bits + * 0b1000..4 Bits + * 0b1001..3 Bits + * 0b1010..2 Bits + * 0b1011..12 Bits + * 0b1100..12 Bits + * 0b1101..12 Bits + * 0b1110..12 Bits + * 0b1111..12 Bits + */ +#define SEMC_SRAMCR0_COL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR0_COL_SHIFT)) & SEMC_SRAMCR0_COL_MASK) +/*! @} */ + +/*! @name SRAMCR1 - SRAM control register 1 */ +/*! @{ */ +#define SEMC_SRAMCR1_CES_MASK (0xFU) +#define SEMC_SRAMCR1_CES_SHIFT (0U) +#define SEMC_SRAMCR1_CES(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR1_CES_SHIFT)) & SEMC_SRAMCR1_CES_MASK) +#define SEMC_SRAMCR1_CEH_MASK (0xF0U) +#define SEMC_SRAMCR1_CEH_SHIFT (4U) +#define SEMC_SRAMCR1_CEH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR1_CEH_SHIFT)) & SEMC_SRAMCR1_CEH_MASK) +#define SEMC_SRAMCR1_AS_MASK (0xF00U) +#define SEMC_SRAMCR1_AS_SHIFT (8U) +#define SEMC_SRAMCR1_AS(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR1_AS_SHIFT)) & SEMC_SRAMCR1_AS_MASK) +#define SEMC_SRAMCR1_AH_MASK (0xF000U) +#define SEMC_SRAMCR1_AH_SHIFT (12U) +#define SEMC_SRAMCR1_AH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR1_AH_SHIFT)) & SEMC_SRAMCR1_AH_MASK) +#define SEMC_SRAMCR1_WEL_MASK (0xF0000U) +#define SEMC_SRAMCR1_WEL_SHIFT (16U) +#define SEMC_SRAMCR1_WEL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR1_WEL_SHIFT)) & SEMC_SRAMCR1_WEL_MASK) +#define SEMC_SRAMCR1_WEH_MASK (0xF00000U) +#define SEMC_SRAMCR1_WEH_SHIFT (20U) +#define SEMC_SRAMCR1_WEH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR1_WEH_SHIFT)) & SEMC_SRAMCR1_WEH_MASK) +#define SEMC_SRAMCR1_REL_MASK (0xF000000U) +#define SEMC_SRAMCR1_REL_SHIFT (24U) +#define SEMC_SRAMCR1_REL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR1_REL_SHIFT)) & SEMC_SRAMCR1_REL_MASK) +#define SEMC_SRAMCR1_REH_MASK (0xF0000000U) +#define SEMC_SRAMCR1_REH_SHIFT (28U) +#define SEMC_SRAMCR1_REH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR1_REH_SHIFT)) & SEMC_SRAMCR1_REH_MASK) +/*! @} */ + +/*! @name SRAMCR2 - SRAM control register 2 */ +/*! @{ */ +#define SEMC_SRAMCR2_WDS_MASK (0xFU) +#define SEMC_SRAMCR2_WDS_SHIFT (0U) +#define SEMC_SRAMCR2_WDS(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR2_WDS_SHIFT)) & SEMC_SRAMCR2_WDS_MASK) +#define SEMC_SRAMCR2_WDH_MASK (0xF0U) +#define SEMC_SRAMCR2_WDH_SHIFT (4U) +#define SEMC_SRAMCR2_WDH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR2_WDH_SHIFT)) & SEMC_SRAMCR2_WDH_MASK) +#define SEMC_SRAMCR2_TA_MASK (0xF00U) +#define SEMC_SRAMCR2_TA_SHIFT (8U) +#define SEMC_SRAMCR2_TA(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR2_TA_SHIFT)) & SEMC_SRAMCR2_TA_MASK) +#define SEMC_SRAMCR2_AWDH_MASK (0xF000U) +#define SEMC_SRAMCR2_AWDH_SHIFT (12U) +#define SEMC_SRAMCR2_AWDH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR2_AWDH_SHIFT)) & SEMC_SRAMCR2_AWDH_MASK) +#define SEMC_SRAMCR2_LC_MASK (0xF0000U) +#define SEMC_SRAMCR2_LC_SHIFT (16U) +#define SEMC_SRAMCR2_LC(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR2_LC_SHIFT)) & SEMC_SRAMCR2_LC_MASK) +#define SEMC_SRAMCR2_RD_MASK (0xF00000U) +#define SEMC_SRAMCR2_RD_SHIFT (20U) +#define SEMC_SRAMCR2_RD(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR2_RD_SHIFT)) & SEMC_SRAMCR2_RD_MASK) +#define SEMC_SRAMCR2_CEITV_MASK (0xF000000U) +#define SEMC_SRAMCR2_CEITV_SHIFT (24U) +#define SEMC_SRAMCR2_CEITV(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR2_CEITV_SHIFT)) & SEMC_SRAMCR2_CEITV_MASK) +/*! @} */ + +/*! @name DBICR0 - DBI-B control register 0 */ +/*! @{ */ +#define SEMC_DBICR0_PS_MASK (0x1U) +#define SEMC_DBICR0_PS_SHIFT (0U) +/*! PS - Port Size + * 0b0..8bit + * 0b1..16bit + */ +#define SEMC_DBICR0_PS(x) (((uint32_t)(((uint32_t)(x)) << SEMC_DBICR0_PS_SHIFT)) & SEMC_DBICR0_PS_MASK) +#define SEMC_DBICR0_BL_MASK (0x70U) +#define SEMC_DBICR0_BL_SHIFT (4U) +/*! BL - Burst Length + * 0b000..1 + * 0b001..2 + * 0b010..4 + * 0b011..8 + * 0b100..16 + * 0b101..32 + * 0b110..64 + * 0b111..64 + */ +#define SEMC_DBICR0_BL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_DBICR0_BL_SHIFT)) & SEMC_DBICR0_BL_MASK) +#define SEMC_DBICR0_COL_MASK (0xF000U) +#define SEMC_DBICR0_COL_SHIFT (12U) +/*! COL - Column Address bit width + * 0b0000..12 Bits + * 0b0001..11 Bits + * 0b0010..10 Bits + * 0b0011..9 Bits + * 0b0100..8 Bits + * 0b0101..7 Bits + * 0b0110..6 Bits + * 0b0111..5 Bits + * 0b1000..4 Bits + * 0b1001..3 Bits + * 0b1010..2 Bits + * 0b1011..12 Bits + * 0b1100..12 Bits + * 0b1101..12 Bits + * 0b1110..12 Bits + * 0b1111..12 Bits + */ +#define SEMC_DBICR0_COL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_DBICR0_COL_SHIFT)) & SEMC_DBICR0_COL_MASK) +/*! @} */ + +/*! @name DBICR1 - DBI-B control register 1 */ +/*! @{ */ +#define SEMC_DBICR1_CES_MASK (0xFU) +#define SEMC_DBICR1_CES_SHIFT (0U) +#define SEMC_DBICR1_CES(x) (((uint32_t)(((uint32_t)(x)) << SEMC_DBICR1_CES_SHIFT)) & SEMC_DBICR1_CES_MASK) +#define SEMC_DBICR1_CEH_MASK (0xF0U) +#define SEMC_DBICR1_CEH_SHIFT (4U) +#define SEMC_DBICR1_CEH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_DBICR1_CEH_SHIFT)) & SEMC_DBICR1_CEH_MASK) +#define SEMC_DBICR1_WEL_MASK (0xF00U) +#define SEMC_DBICR1_WEL_SHIFT (8U) +#define SEMC_DBICR1_WEL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_DBICR1_WEL_SHIFT)) & SEMC_DBICR1_WEL_MASK) +#define SEMC_DBICR1_WEH_MASK (0xF000U) +#define SEMC_DBICR1_WEH_SHIFT (12U) +#define SEMC_DBICR1_WEH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_DBICR1_WEH_SHIFT)) & SEMC_DBICR1_WEH_MASK) +#define SEMC_DBICR1_REL_MASK (0xF0000U) +#define SEMC_DBICR1_REL_SHIFT (16U) +#define SEMC_DBICR1_REL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_DBICR1_REL_SHIFT)) & SEMC_DBICR1_REL_MASK) +#define SEMC_DBICR1_REH_MASK (0xF00000U) +#define SEMC_DBICR1_REH_SHIFT (20U) +#define SEMC_DBICR1_REH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_DBICR1_REH_SHIFT)) & SEMC_DBICR1_REH_MASK) +#define SEMC_DBICR1_CEITV_MASK (0xF000000U) +#define SEMC_DBICR1_CEITV_SHIFT (24U) +#define SEMC_DBICR1_CEITV(x) (((uint32_t)(((uint32_t)(x)) << SEMC_DBICR1_CEITV_SHIFT)) & SEMC_DBICR1_CEITV_MASK) +#define SEMC_DBICR1_REL2_MASK (0x30000000U) +#define SEMC_DBICR1_REL2_SHIFT (28U) +#define SEMC_DBICR1_REL2(x) (((uint32_t)(((uint32_t)(x)) << SEMC_DBICR1_REL2_SHIFT)) & SEMC_DBICR1_REL2_MASK) +#define SEMC_DBICR1_REH2_MASK (0xC0000000U) +#define SEMC_DBICR1_REH2_SHIFT (30U) +#define SEMC_DBICR1_REH2(x) (((uint32_t)(((uint32_t)(x)) << SEMC_DBICR1_REH2_SHIFT)) & SEMC_DBICR1_REH2_MASK) +/*! @} */ + +/*! @name IPCR0 - IP Command control register 0 */ +/*! @{ */ +#define SEMC_IPCR0_SA_MASK (0xFFFFFFFFU) +#define SEMC_IPCR0_SA_SHIFT (0U) +#define SEMC_IPCR0_SA(x) (((uint32_t)(((uint32_t)(x)) << SEMC_IPCR0_SA_SHIFT)) & SEMC_IPCR0_SA_MASK) +/*! @} */ + +/*! @name IPCR1 - IP Command control register 1 */ +/*! @{ */ +#define SEMC_IPCR1_DATSZ_MASK (0x7U) +#define SEMC_IPCR1_DATSZ_SHIFT (0U) +/*! DATSZ - Data Size in Byte + * 0b000..4 + * 0b001..1 + * 0b010..2 + * 0b011..3 + * 0b100..4 + * 0b101..4 + * 0b110..4 + * 0b111..4 + */ +#define SEMC_IPCR1_DATSZ(x) (((uint32_t)(((uint32_t)(x)) << SEMC_IPCR1_DATSZ_SHIFT)) & SEMC_IPCR1_DATSZ_MASK) +/*! @} */ + +/*! @name IPCR2 - IP Command control register 2 */ +/*! @{ */ +#define SEMC_IPCR2_BM0_MASK (0x1U) +#define SEMC_IPCR2_BM0_SHIFT (0U) +/*! BM0 - Byte Mask for Byte 0 (IPTXD bit 7:0) + * 0b0..Byte Unmasked + * 0b1..Byte Masked + */ +#define SEMC_IPCR2_BM0(x) (((uint32_t)(((uint32_t)(x)) << SEMC_IPCR2_BM0_SHIFT)) & SEMC_IPCR2_BM0_MASK) +#define SEMC_IPCR2_BM1_MASK (0x2U) +#define SEMC_IPCR2_BM1_SHIFT (1U) +/*! BM1 - Byte Mask for Byte 1 (IPTXD bit 15:8) + * 0b0..Byte Unmasked + * 0b1..Byte Masked + */ +#define SEMC_IPCR2_BM1(x) (((uint32_t)(((uint32_t)(x)) << SEMC_IPCR2_BM1_SHIFT)) & SEMC_IPCR2_BM1_MASK) +#define SEMC_IPCR2_BM2_MASK (0x4U) +#define SEMC_IPCR2_BM2_SHIFT (2U) +/*! BM2 - Byte Mask for Byte 2 (IPTXD bit 23:16) + * 0b0..Byte Unmasked + * 0b1..Byte Masked + */ +#define SEMC_IPCR2_BM2(x) (((uint32_t)(((uint32_t)(x)) << SEMC_IPCR2_BM2_SHIFT)) & SEMC_IPCR2_BM2_MASK) +#define SEMC_IPCR2_BM3_MASK (0x8U) +#define SEMC_IPCR2_BM3_SHIFT (3U) +/*! BM3 - Byte Mask for Byte 3 (IPTXD bit 31:24) + * 0b0..Byte Unmasked + * 0b1..Byte Masked + */ +#define SEMC_IPCR2_BM3(x) (((uint32_t)(((uint32_t)(x)) << SEMC_IPCR2_BM3_SHIFT)) & SEMC_IPCR2_BM3_MASK) +/*! @} */ + +/*! @name IPCMD - IP Command register */ +/*! @{ */ +#define SEMC_IPCMD_CMD_MASK (0xFFFFU) +#define SEMC_IPCMD_CMD_SHIFT (0U) +#define SEMC_IPCMD_CMD(x) (((uint32_t)(((uint32_t)(x)) << SEMC_IPCMD_CMD_SHIFT)) & SEMC_IPCMD_CMD_MASK) +#define SEMC_IPCMD_KEY_MASK (0xFFFF0000U) +#define SEMC_IPCMD_KEY_SHIFT (16U) +#define SEMC_IPCMD_KEY(x) (((uint32_t)(((uint32_t)(x)) << SEMC_IPCMD_KEY_SHIFT)) & SEMC_IPCMD_KEY_MASK) +/*! @} */ + +/*! @name IPTXDAT - TX DATA register (for IP Command) */ +/*! @{ */ +#define SEMC_IPTXDAT_DAT_MASK (0xFFFFFFFFU) +#define SEMC_IPTXDAT_DAT_SHIFT (0U) +#define SEMC_IPTXDAT_DAT(x) (((uint32_t)(((uint32_t)(x)) << SEMC_IPTXDAT_DAT_SHIFT)) & SEMC_IPTXDAT_DAT_MASK) +/*! @} */ + +/*! @name IPRXDAT - RX DATA register (for IP Command) */ +/*! @{ */ +#define SEMC_IPRXDAT_DAT_MASK (0xFFFFFFFFU) +#define SEMC_IPRXDAT_DAT_SHIFT (0U) +#define SEMC_IPRXDAT_DAT(x) (((uint32_t)(((uint32_t)(x)) << SEMC_IPRXDAT_DAT_SHIFT)) & SEMC_IPRXDAT_DAT_MASK) +/*! @} */ + +/*! @name STS0 - Status register 0 */ +/*! @{ */ +#define SEMC_STS0_IDLE_MASK (0x1U) +#define SEMC_STS0_IDLE_SHIFT (0U) +#define SEMC_STS0_IDLE(x) (((uint32_t)(((uint32_t)(x)) << SEMC_STS0_IDLE_SHIFT)) & SEMC_STS0_IDLE_MASK) +#define SEMC_STS0_NARDY_MASK (0x2U) +#define SEMC_STS0_NARDY_SHIFT (1U) +/*! NARDY - Indicating NAND device Ready/WAIT# pin level. + * 0b0..NAND device is not ready + * 0b1..NAND device is ready + */ +#define SEMC_STS0_NARDY(x) (((uint32_t)(((uint32_t)(x)) << SEMC_STS0_NARDY_SHIFT)) & SEMC_STS0_NARDY_MASK) +/*! @} */ + +/*! @name STS2 - Status register 2 */ +/*! @{ */ +#define SEMC_STS2_NDWRPEND_MASK (0x8U) +#define SEMC_STS2_NDWRPEND_SHIFT (3U) +/*! NDWRPEND - This field indicating whether there is pending AXI command (write) to NAND device. + * 0b0..No pending + * 0b1..Pending + */ +#define SEMC_STS2_NDWRPEND(x) (((uint32_t)(((uint32_t)(x)) << SEMC_STS2_NDWRPEND_SHIFT)) & SEMC_STS2_NDWRPEND_MASK) +/*! @} */ + +/*! @name STS12 - Status register 12 */ +/*! @{ */ +#define SEMC_STS12_NDADDR_MASK (0xFFFFFFFFU) +#define SEMC_STS12_NDADDR_SHIFT (0U) +#define SEMC_STS12_NDADDR(x) (((uint32_t)(((uint32_t)(x)) << SEMC_STS12_NDADDR_SHIFT)) & SEMC_STS12_NDADDR_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group SEMC_Register_Masks */ + + +/* SEMC - Peripheral instance base addresses */ +/** Peripheral SEMC base address */ +#define SEMC_BASE (0x402F0000u) +/** Peripheral SEMC base pointer */ +#define SEMC ((SEMC_Type *)SEMC_BASE) +/** Array initializer of SEMC peripheral base addresses */ +#define SEMC_BASE_ADDRS { SEMC_BASE } +/** Array initializer of SEMC peripheral base pointers */ +#define SEMC_BASE_PTRS { SEMC } +/** Interrupt vectors for the SEMC peripheral type */ +#define SEMC_IRQS { SEMC_IRQn } + +/*! + * @} + */ /* end of group SEMC_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- SNVS Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup SNVS_Peripheral_Access_Layer SNVS Peripheral Access Layer + * @{ + */ + +/** SNVS - Register Layout Typedef */ +typedef struct { + __IO uint32_t HPLR; /**< SNVS_HP Lock Register, offset: 0x0 */ + __IO uint32_t HPCOMR; /**< SNVS_HP Command Register, offset: 0x4 */ + __IO uint32_t HPCR; /**< SNVS_HP Control Register, offset: 0x8 */ + __IO uint32_t HPSICR; /**< SNVS_HP Security Interrupt Control Register, offset: 0xC */ + __IO uint32_t HPSVCR; /**< SNVS_HP Security Violation Control Register, offset: 0x10 */ + __IO uint32_t HPSR; /**< SNVS_HP Status Register, offset: 0x14 */ + __IO uint32_t HPSVSR; /**< SNVS_HP Security Violation Status Register, offset: 0x18 */ + __IO uint32_t HPHACIVR; /**< SNVS_HP High Assurance Counter IV Register, offset: 0x1C */ + __I uint32_t HPHACR; /**< SNVS_HP High Assurance Counter Register, offset: 0x20 */ + __IO uint32_t HPRTCMR; /**< SNVS_HP Real Time Counter MSB Register, offset: 0x24 */ + __IO uint32_t HPRTCLR; /**< SNVS_HP Real Time Counter LSB Register, offset: 0x28 */ + __IO uint32_t HPTAMR; /**< SNVS_HP Time Alarm MSB Register, offset: 0x2C */ + __IO uint32_t HPTALR; /**< SNVS_HP Time Alarm LSB Register, offset: 0x30 */ + __IO uint32_t LPLR; /**< SNVS_LP Lock Register, offset: 0x34 */ + __IO uint32_t LPCR; /**< SNVS_LP Control Register, offset: 0x38 */ + __IO uint32_t LPMKCR; /**< SNVS_LP Master Key Control Register, offset: 0x3C */ + __IO uint32_t LPSVCR; /**< SNVS_LP Security Violation Control Register, offset: 0x40 */ + uint8_t RESERVED_0[4]; + __IO uint32_t LPTDCR; /**< SNVS_LP Tamper Detectors Configuration Register, offset: 0x48 */ + __IO uint32_t LPSR; /**< SNVS_LP Status Register, offset: 0x4C */ + __IO uint32_t LPSRTCMR; /**< SNVS_LP Secure Real Time Counter MSB Register, offset: 0x50 */ + __IO uint32_t LPSRTCLR; /**< SNVS_LP Secure Real Time Counter LSB Register, offset: 0x54 */ + __IO uint32_t LPTAR; /**< SNVS_LP Time Alarm Register, offset: 0x58 */ + __I uint32_t LPSMCMR; /**< SNVS_LP Secure Monotonic Counter MSB Register, offset: 0x5C */ + __I uint32_t LPSMCLR; /**< SNVS_LP Secure Monotonic Counter LSB Register, offset: 0x60 */ + __IO uint32_t LPPGDR; /**< SNVS_LP Power Glitch Detector Register, offset: 0x64 */ + __IO uint32_t LPGPR0_LEGACY_ALIAS; /**< SNVS_LP General Purpose Register 0 (legacy alias), offset: 0x68 */ + __IO uint32_t LPZMKR[8]; /**< SNVS_LP Zeroizable Master Key Register, array offset: 0x6C, array step: 0x4 */ + uint8_t RESERVED_1[4]; + __IO uint32_t LPGPR_ALIAS[4]; /**< SNVS_LP General Purpose Registers 0 .. 3, array offset: 0x90, array step: 0x4 */ + uint8_t RESERVED_2[96]; + __IO uint32_t LPGPR[8]; /**< SNVS_LP General Purpose Registers 0 .. 7, array offset: 0x100, array step: 0x4 */ + uint8_t RESERVED_3[2776]; + __I uint32_t HPVIDR1; /**< SNVS_HP Version ID Register 1, offset: 0xBF8 */ + __I uint32_t HPVIDR2; /**< SNVS_HP Version ID Register 2, offset: 0xBFC */ +} SNVS_Type; + +/* ---------------------------------------------------------------------------- + -- SNVS Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup SNVS_Register_Masks SNVS Register Masks + * @{ + */ + +/*! @name HPLR - SNVS_HP Lock Register */ +/*! @{ */ +#define SNVS_HPLR_ZMK_WSL_MASK (0x1U) +#define SNVS_HPLR_ZMK_WSL_SHIFT (0U) +/*! ZMK_WSL + * 0b0..Write access is allowed + * 0b1..Write access is not allowed + */ +#define SNVS_HPLR_ZMK_WSL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_ZMK_WSL_SHIFT)) & SNVS_HPLR_ZMK_WSL_MASK) +#define SNVS_HPLR_ZMK_RSL_MASK (0x2U) +#define SNVS_HPLR_ZMK_RSL_SHIFT (1U) +/*! ZMK_RSL + * 0b0..Read access is allowed (only in software Programming mode) + * 0b1..Read access is not allowed + */ +#define SNVS_HPLR_ZMK_RSL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_ZMK_RSL_SHIFT)) & SNVS_HPLR_ZMK_RSL_MASK) +#define SNVS_HPLR_SRTC_SL_MASK (0x4U) +#define SNVS_HPLR_SRTC_SL_SHIFT (2U) +/*! SRTC_SL + * 0b0..Write access is allowed + * 0b1..Write access is not allowed + */ +#define SNVS_HPLR_SRTC_SL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_SRTC_SL_SHIFT)) & SNVS_HPLR_SRTC_SL_MASK) +#define SNVS_HPLR_LPCALB_SL_MASK (0x8U) +#define SNVS_HPLR_LPCALB_SL_SHIFT (3U) +/*! LPCALB_SL + * 0b0..Write access is allowed + * 0b1..Write access is not allowed + */ +#define SNVS_HPLR_LPCALB_SL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_LPCALB_SL_SHIFT)) & SNVS_HPLR_LPCALB_SL_MASK) +#define SNVS_HPLR_MC_SL_MASK (0x10U) +#define SNVS_HPLR_MC_SL_SHIFT (4U) +/*! MC_SL + * 0b0..Write access (increment) is allowed + * 0b1..Write access (increment) is not allowed + */ +#define SNVS_HPLR_MC_SL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_MC_SL_SHIFT)) & SNVS_HPLR_MC_SL_MASK) +#define SNVS_HPLR_GPR_SL_MASK (0x20U) +#define SNVS_HPLR_GPR_SL_SHIFT (5U) +/*! GPR_SL + * 0b0..Write access is allowed + * 0b1..Write access is not allowed + */ +#define SNVS_HPLR_GPR_SL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_GPR_SL_SHIFT)) & SNVS_HPLR_GPR_SL_MASK) +#define SNVS_HPLR_LPSVCR_SL_MASK (0x40U) +#define SNVS_HPLR_LPSVCR_SL_SHIFT (6U) +/*! LPSVCR_SL + * 0b0..Write access is allowed + * 0b1..Write access is not allowed + */ +#define SNVS_HPLR_LPSVCR_SL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_LPSVCR_SL_SHIFT)) & SNVS_HPLR_LPSVCR_SL_MASK) +#define SNVS_HPLR_LPTDCR_SL_MASK (0x100U) +#define SNVS_HPLR_LPTDCR_SL_SHIFT (8U) +/*! LPTDCR_SL + * 0b0..Write access is allowed + * 0b1..Write access is not allowed + */ +#define SNVS_HPLR_LPTDCR_SL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_LPTDCR_SL_SHIFT)) & SNVS_HPLR_LPTDCR_SL_MASK) +#define SNVS_HPLR_MKS_SL_MASK (0x200U) +#define SNVS_HPLR_MKS_SL_SHIFT (9U) +/*! MKS_SL + * 0b0..Write access is allowed + * 0b1..Write access is not allowed + */ +#define SNVS_HPLR_MKS_SL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_MKS_SL_SHIFT)) & SNVS_HPLR_MKS_SL_MASK) +#define SNVS_HPLR_HPSVCR_L_MASK (0x10000U) +#define SNVS_HPLR_HPSVCR_L_SHIFT (16U) +/*! HPSVCR_L + * 0b0..Write access is allowed + * 0b1..Write access is not allowed + */ +#define SNVS_HPLR_HPSVCR_L(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_HPSVCR_L_SHIFT)) & SNVS_HPLR_HPSVCR_L_MASK) +#define SNVS_HPLR_HPSICR_L_MASK (0x20000U) +#define SNVS_HPLR_HPSICR_L_SHIFT (17U) +/*! HPSICR_L + * 0b0..Write access is allowed + * 0b1..Write access is not allowed + */ +#define SNVS_HPLR_HPSICR_L(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_HPSICR_L_SHIFT)) & SNVS_HPLR_HPSICR_L_MASK) +#define SNVS_HPLR_HAC_L_MASK (0x40000U) +#define SNVS_HPLR_HAC_L_SHIFT (18U) +/*! HAC_L + * 0b0..Write access is allowed + * 0b1..Write access is not allowed + */ +#define SNVS_HPLR_HAC_L(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_HAC_L_SHIFT)) & SNVS_HPLR_HAC_L_MASK) +/*! @} */ + +/*! @name HPCOMR - SNVS_HP Command Register */ +/*! @{ */ +#define SNVS_HPCOMR_SSM_ST_MASK (0x1U) +#define SNVS_HPCOMR_SSM_ST_SHIFT (0U) +#define SNVS_HPCOMR_SSM_ST(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_SSM_ST_SHIFT)) & SNVS_HPCOMR_SSM_ST_MASK) +#define SNVS_HPCOMR_SSM_ST_DIS_MASK (0x2U) +#define SNVS_HPCOMR_SSM_ST_DIS_SHIFT (1U) +/*! SSM_ST_DIS + * 0b0..Secure to Trusted State transition is enabled + * 0b1..Secure to Trusted State transition is disabled + */ +#define SNVS_HPCOMR_SSM_ST_DIS(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_SSM_ST_DIS_SHIFT)) & SNVS_HPCOMR_SSM_ST_DIS_MASK) +#define SNVS_HPCOMR_SSM_SFNS_DIS_MASK (0x4U) +#define SNVS_HPCOMR_SSM_SFNS_DIS_SHIFT (2U) +/*! SSM_SFNS_DIS + * 0b0..Soft Fail to Non-Secure State transition is enabled + * 0b1..Soft Fail to Non-Secure State transition is disabled + */ +#define SNVS_HPCOMR_SSM_SFNS_DIS(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_SSM_SFNS_DIS_SHIFT)) & SNVS_HPCOMR_SSM_SFNS_DIS_MASK) +#define SNVS_HPCOMR_LP_SWR_MASK (0x10U) +#define SNVS_HPCOMR_LP_SWR_SHIFT (4U) +/*! LP_SWR + * 0b0..No Action + * 0b1..Reset LP section + */ +#define SNVS_HPCOMR_LP_SWR(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_LP_SWR_SHIFT)) & SNVS_HPCOMR_LP_SWR_MASK) +#define SNVS_HPCOMR_LP_SWR_DIS_MASK (0x20U) +#define SNVS_HPCOMR_LP_SWR_DIS_SHIFT (5U) +/*! LP_SWR_DIS + * 0b0..LP software reset is enabled + * 0b1..LP software reset is disabled + */ +#define SNVS_HPCOMR_LP_SWR_DIS(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_LP_SWR_DIS_SHIFT)) & SNVS_HPCOMR_LP_SWR_DIS_MASK) +#define SNVS_HPCOMR_SW_SV_MASK (0x100U) +#define SNVS_HPCOMR_SW_SV_SHIFT (8U) +#define SNVS_HPCOMR_SW_SV(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_SW_SV_SHIFT)) & SNVS_HPCOMR_SW_SV_MASK) +#define SNVS_HPCOMR_SW_FSV_MASK (0x200U) +#define SNVS_HPCOMR_SW_FSV_SHIFT (9U) +#define SNVS_HPCOMR_SW_FSV(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_SW_FSV_SHIFT)) & SNVS_HPCOMR_SW_FSV_MASK) +#define SNVS_HPCOMR_SW_LPSV_MASK (0x400U) +#define SNVS_HPCOMR_SW_LPSV_SHIFT (10U) +#define SNVS_HPCOMR_SW_LPSV(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_SW_LPSV_SHIFT)) & SNVS_HPCOMR_SW_LPSV_MASK) +#define SNVS_HPCOMR_PROG_ZMK_MASK (0x1000U) +#define SNVS_HPCOMR_PROG_ZMK_SHIFT (12U) +/*! PROG_ZMK + * 0b0..No Action + * 0b1..Activate hardware key programming mechanism + */ +#define SNVS_HPCOMR_PROG_ZMK(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_PROG_ZMK_SHIFT)) & SNVS_HPCOMR_PROG_ZMK_MASK) +#define SNVS_HPCOMR_MKS_EN_MASK (0x2000U) +#define SNVS_HPCOMR_MKS_EN_SHIFT (13U) +/*! MKS_EN + * 0b0..OTP master key is selected as an SNVS master key + * 0b1..SNVS master key is selected according to the setting of the MASTER_KEY_SEL field of LPMKCR + */ +#define SNVS_HPCOMR_MKS_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_MKS_EN_SHIFT)) & SNVS_HPCOMR_MKS_EN_MASK) +#define SNVS_HPCOMR_HAC_EN_MASK (0x10000U) +#define SNVS_HPCOMR_HAC_EN_SHIFT (16U) +/*! HAC_EN + * 0b0..High Assurance Counter is disabled + * 0b1..High Assurance Counter is enabled + */ +#define SNVS_HPCOMR_HAC_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_HAC_EN_SHIFT)) & SNVS_HPCOMR_HAC_EN_MASK) +#define SNVS_HPCOMR_HAC_LOAD_MASK (0x20000U) +#define SNVS_HPCOMR_HAC_LOAD_SHIFT (17U) +/*! HAC_LOAD + * 0b0..No Action + * 0b1..Load the HAC + */ +#define SNVS_HPCOMR_HAC_LOAD(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_HAC_LOAD_SHIFT)) & SNVS_HPCOMR_HAC_LOAD_MASK) +#define SNVS_HPCOMR_HAC_CLEAR_MASK (0x40000U) +#define SNVS_HPCOMR_HAC_CLEAR_SHIFT (18U) +/*! HAC_CLEAR + * 0b0..No Action + * 0b1..Clear the HAC + */ +#define SNVS_HPCOMR_HAC_CLEAR(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_HAC_CLEAR_SHIFT)) & SNVS_HPCOMR_HAC_CLEAR_MASK) +#define SNVS_HPCOMR_HAC_STOP_MASK (0x80000U) +#define SNVS_HPCOMR_HAC_STOP_SHIFT (19U) +#define SNVS_HPCOMR_HAC_STOP(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_HAC_STOP_SHIFT)) & SNVS_HPCOMR_HAC_STOP_MASK) +#define SNVS_HPCOMR_NPSWA_EN_MASK (0x80000000U) +#define SNVS_HPCOMR_NPSWA_EN_SHIFT (31U) +#define SNVS_HPCOMR_NPSWA_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_NPSWA_EN_SHIFT)) & SNVS_HPCOMR_NPSWA_EN_MASK) +/*! @} */ + +/*! @name HPCR - SNVS_HP Control Register */ +/*! @{ */ +#define SNVS_HPCR_RTC_EN_MASK (0x1U) +#define SNVS_HPCR_RTC_EN_SHIFT (0U) +/*! RTC_EN + * 0b0..RTC is disabled + * 0b1..RTC is enabled + */ +#define SNVS_HPCR_RTC_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCR_RTC_EN_SHIFT)) & SNVS_HPCR_RTC_EN_MASK) +#define SNVS_HPCR_HPTA_EN_MASK (0x2U) +#define SNVS_HPCR_HPTA_EN_SHIFT (1U) +/*! HPTA_EN + * 0b0..HP Time Alarm Interrupt is disabled + * 0b1..HP Time Alarm Interrupt is enabled + */ +#define SNVS_HPCR_HPTA_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCR_HPTA_EN_SHIFT)) & SNVS_HPCR_HPTA_EN_MASK) +#define SNVS_HPCR_DIS_PI_MASK (0x4U) +#define SNVS_HPCR_DIS_PI_SHIFT (2U) +/*! DIS_PI + * 0b0..Periodic interrupt will trigger a functional interrupt + * 0b1..Disable periodic interrupt in the function interrupt + */ +#define SNVS_HPCR_DIS_PI(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCR_DIS_PI_SHIFT)) & SNVS_HPCR_DIS_PI_MASK) +#define SNVS_HPCR_PI_EN_MASK (0x8U) +#define SNVS_HPCR_PI_EN_SHIFT (3U) +/*! PI_EN + * 0b0..HP Periodic Interrupt is disabled + * 0b1..HP Periodic Interrupt is enabled + */ +#define SNVS_HPCR_PI_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCR_PI_EN_SHIFT)) & SNVS_HPCR_PI_EN_MASK) +#define SNVS_HPCR_PI_FREQ_MASK (0xF0U) +#define SNVS_HPCR_PI_FREQ_SHIFT (4U) +/*! PI_FREQ + * 0b0000..- bit 0 of the HPRTCLR is selected as a source of the periodic interrupt + * 0b0001..- bit 1 of the HPRTCLR is selected as a source of the periodic interrupt + * 0b0010..- bit 2 of the HPRTCLR is selected as a source of the periodic interrupt + * 0b0011..- bit 3 of the HPRTCLR is selected as a source of the periodic interrupt + * 0b0100..- bit 4 of the HPRTCLR is selected as a source of the periodic interrupt + * 0b0101..- bit 5 of the HPRTCLR is selected as a source of the periodic interrupt + * 0b0110..- bit 6 of the HPRTCLR is selected as a source of the periodic interrupt + * 0b0111..- bit 7 of the HPRTCLR is selected as a source of the periodic interrupt + * 0b1000..- bit 8 of the HPRTCLR is selected as a source of the periodic interrupt + * 0b1001..- bit 9 of the HPRTCLR is selected as a source of the periodic interrupt + * 0b1010..- bit 10 of the HPRTCLR is selected as a source of the periodic interrupt + * 0b1011..- bit 11 of the HPRTCLR is selected as a source of the periodic interrupt + * 0b1100..- bit 12 of the HPRTCLR is selected as a source of the periodic interrupt + * 0b1101..- bit 13 of the HPRTCLR is selected as a source of the periodic interrupt + * 0b1110..- bit 14 of the HPRTCLR is selected as a source of the periodic interrupt + * 0b1111..- bit 15 of the HPRTCLR is selected as a source of the periodic interrupt + */ +#define SNVS_HPCR_PI_FREQ(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCR_PI_FREQ_SHIFT)) & SNVS_HPCR_PI_FREQ_MASK) +#define SNVS_HPCR_HPCALB_EN_MASK (0x100U) +#define SNVS_HPCR_HPCALB_EN_SHIFT (8U) +/*! HPCALB_EN + * 0b0..HP Timer calibration disabled + * 0b1..HP Timer calibration enabled + */ +#define SNVS_HPCR_HPCALB_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCR_HPCALB_EN_SHIFT)) & SNVS_HPCR_HPCALB_EN_MASK) +#define SNVS_HPCR_HPCALB_VAL_MASK (0x7C00U) +#define SNVS_HPCR_HPCALB_VAL_SHIFT (10U) +/*! HPCALB_VAL + * 0b00000..+0 counts per each 32768 ticks of the counter + * 0b00001..+1 counts per each 32768 ticks of the counter + * 0b00010..+2 counts per each 32768 ticks of the counter + * 0b01111..+15 counts per each 32768 ticks of the counter + * 0b10000..-16 counts per each 32768 ticks of the counter + * 0b10001..-15 counts per each 32768 ticks of the counter + * 0b11110..-2 counts per each 32768 ticks of the counter + * 0b11111..-1 counts per each 32768 ticks of the counter + */ +#define SNVS_HPCR_HPCALB_VAL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCR_HPCALB_VAL_SHIFT)) & SNVS_HPCR_HPCALB_VAL_MASK) +#define SNVS_HPCR_HP_TS_MASK (0x10000U) +#define SNVS_HPCR_HP_TS_SHIFT (16U) +/*! HP_TS + * 0b0..No Action + * 0b1..Synchronize the HP Time Counter to the LP Time Counter + */ +#define SNVS_HPCR_HP_TS(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCR_HP_TS_SHIFT)) & SNVS_HPCR_HP_TS_MASK) +#define SNVS_HPCR_BTN_CONFIG_MASK (0x7000000U) +#define SNVS_HPCR_BTN_CONFIG_SHIFT (24U) +#define SNVS_HPCR_BTN_CONFIG(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCR_BTN_CONFIG_SHIFT)) & SNVS_HPCR_BTN_CONFIG_MASK) +#define SNVS_HPCR_BTN_MASK_MASK (0x8000000U) +#define SNVS_HPCR_BTN_MASK_SHIFT (27U) +#define SNVS_HPCR_BTN_MASK(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCR_BTN_MASK_SHIFT)) & SNVS_HPCR_BTN_MASK_MASK) +/*! @} */ + +/*! @name HPSICR - SNVS_HP Security Interrupt Control Register */ +/*! @{ */ +#define SNVS_HPSICR_SV0_EN_MASK (0x1U) +#define SNVS_HPSICR_SV0_EN_SHIFT (0U) +/*! SV0_EN + * 0b0..Security Violation 0 Interrupt is Disabled + * 0b1..Security Violation 0 Interrupt is Enabled + */ +#define SNVS_HPSICR_SV0_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSICR_SV0_EN_SHIFT)) & SNVS_HPSICR_SV0_EN_MASK) +#define SNVS_HPSICR_SV1_EN_MASK (0x2U) +#define SNVS_HPSICR_SV1_EN_SHIFT (1U) +/*! SV1_EN + * 0b0..Security Violation 1 Interrupt is Disabled + * 0b1..Security Violation 1 Interrupt is Enabled + */ +#define SNVS_HPSICR_SV1_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSICR_SV1_EN_SHIFT)) & SNVS_HPSICR_SV1_EN_MASK) +#define SNVS_HPSICR_SV2_EN_MASK (0x4U) +#define SNVS_HPSICR_SV2_EN_SHIFT (2U) +/*! SV2_EN + * 0b0..Security Violation 2 Interrupt is Disabled + * 0b1..Security Violation 2 Interrupt is Enabled + */ +#define SNVS_HPSICR_SV2_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSICR_SV2_EN_SHIFT)) & SNVS_HPSICR_SV2_EN_MASK) +#define SNVS_HPSICR_SV3_EN_MASK (0x8U) +#define SNVS_HPSICR_SV3_EN_SHIFT (3U) +/*! SV3_EN + * 0b0..Security Violation 3 Interrupt is Disabled + * 0b1..Security Violation 3 Interrupt is Enabled + */ +#define SNVS_HPSICR_SV3_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSICR_SV3_EN_SHIFT)) & SNVS_HPSICR_SV3_EN_MASK) +#define SNVS_HPSICR_SV4_EN_MASK (0x10U) +#define SNVS_HPSICR_SV4_EN_SHIFT (4U) +/*! SV4_EN + * 0b0..Security Violation 4 Interrupt is Disabled + * 0b1..Security Violation 4 Interrupt is Enabled + */ +#define SNVS_HPSICR_SV4_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSICR_SV4_EN_SHIFT)) & SNVS_HPSICR_SV4_EN_MASK) +#define SNVS_HPSICR_SV5_EN_MASK (0x20U) +#define SNVS_HPSICR_SV5_EN_SHIFT (5U) +/*! SV5_EN + * 0b0..Security Violation 5 Interrupt is Disabled + * 0b1..Security Violation 5 Interrupt is Enabled + */ +#define SNVS_HPSICR_SV5_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSICR_SV5_EN_SHIFT)) & SNVS_HPSICR_SV5_EN_MASK) +#define SNVS_HPSICR_LPSVI_EN_MASK (0x80000000U) +#define SNVS_HPSICR_LPSVI_EN_SHIFT (31U) +/*! LPSVI_EN + * 0b0..LP Security Violation Interrupt is Disabled + * 0b1..LP Security Violation Interrupt is Enabled + */ +#define SNVS_HPSICR_LPSVI_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSICR_LPSVI_EN_SHIFT)) & SNVS_HPSICR_LPSVI_EN_MASK) +/*! @} */ + +/*! @name HPSVCR - SNVS_HP Security Violation Control Register */ +/*! @{ */ +#define SNVS_HPSVCR_SV0_CFG_MASK (0x1U) +#define SNVS_HPSVCR_SV0_CFG_SHIFT (0U) +/*! SV0_CFG + * 0b0..Security Violation 0 is a non-fatal violation + * 0b1..Security Violation 0 is a fatal violation + */ +#define SNVS_HPSVCR_SV0_CFG(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVCR_SV0_CFG_SHIFT)) & SNVS_HPSVCR_SV0_CFG_MASK) +#define SNVS_HPSVCR_SV1_CFG_MASK (0x2U) +#define SNVS_HPSVCR_SV1_CFG_SHIFT (1U) +/*! SV1_CFG + * 0b0..Security Violation 1 is a non-fatal violation + * 0b1..Security Violation 1 is a fatal violation + */ +#define SNVS_HPSVCR_SV1_CFG(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVCR_SV1_CFG_SHIFT)) & SNVS_HPSVCR_SV1_CFG_MASK) +#define SNVS_HPSVCR_SV2_CFG_MASK (0x4U) +#define SNVS_HPSVCR_SV2_CFG_SHIFT (2U) +/*! SV2_CFG + * 0b0..Security Violation 2 is a non-fatal violation + * 0b1..Security Violation 2 is a fatal violation + */ +#define SNVS_HPSVCR_SV2_CFG(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVCR_SV2_CFG_SHIFT)) & SNVS_HPSVCR_SV2_CFG_MASK) +#define SNVS_HPSVCR_SV3_CFG_MASK (0x8U) +#define SNVS_HPSVCR_SV3_CFG_SHIFT (3U) +/*! SV3_CFG + * 0b0..Security Violation 3 is a non-fatal violation + * 0b1..Security Violation 3 is a fatal violation + */ +#define SNVS_HPSVCR_SV3_CFG(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVCR_SV3_CFG_SHIFT)) & SNVS_HPSVCR_SV3_CFG_MASK) +#define SNVS_HPSVCR_SV4_CFG_MASK (0x10U) +#define SNVS_HPSVCR_SV4_CFG_SHIFT (4U) +/*! SV4_CFG + * 0b0..Security Violation 4 is a non-fatal violation + * 0b1..Security Violation 4 is a fatal violation + */ +#define SNVS_HPSVCR_SV4_CFG(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVCR_SV4_CFG_SHIFT)) & SNVS_HPSVCR_SV4_CFG_MASK) +#define SNVS_HPSVCR_SV5_CFG_MASK (0x60U) +#define SNVS_HPSVCR_SV5_CFG_SHIFT (5U) +/*! SV5_CFG + * 0b00..Security Violation 5 is disabled + * 0b01..Security Violation 5 is a non-fatal violation + * 0b1x..Security Violation 5 is a fatal violation + */ +#define SNVS_HPSVCR_SV5_CFG(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVCR_SV5_CFG_SHIFT)) & SNVS_HPSVCR_SV5_CFG_MASK) +#define SNVS_HPSVCR_LPSV_CFG_MASK (0xC0000000U) +#define SNVS_HPSVCR_LPSV_CFG_SHIFT (30U) +/*! LPSV_CFG + * 0b00..LP security violation is disabled + * 0b01..LP security violation is a non-fatal violation + * 0b1x..LP security violation is a fatal violation + */ +#define SNVS_HPSVCR_LPSV_CFG(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVCR_LPSV_CFG_SHIFT)) & SNVS_HPSVCR_LPSV_CFG_MASK) +/*! @} */ + +/*! @name HPSR - SNVS_HP Status Register */ +/*! @{ */ +#define SNVS_HPSR_HPTA_MASK (0x1U) +#define SNVS_HPSR_HPTA_SHIFT (0U) +/*! HPTA + * 0b0..No time alarm interrupt occurred. + * 0b1..A time alarm interrupt occurred. + */ +#define SNVS_HPSR_HPTA(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSR_HPTA_SHIFT)) & SNVS_HPSR_HPTA_MASK) +#define SNVS_HPSR_PI_MASK (0x2U) +#define SNVS_HPSR_PI_SHIFT (1U) +/*! PI + * 0b0..No periodic interrupt occurred. + * 0b1..A periodic interrupt occurred. + */ +#define SNVS_HPSR_PI(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSR_PI_SHIFT)) & SNVS_HPSR_PI_MASK) +#define SNVS_HPSR_LPDIS_MASK (0x10U) +#define SNVS_HPSR_LPDIS_SHIFT (4U) +#define SNVS_HPSR_LPDIS(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSR_LPDIS_SHIFT)) & SNVS_HPSR_LPDIS_MASK) +#define SNVS_HPSR_BTN_MASK (0x40U) +#define SNVS_HPSR_BTN_SHIFT (6U) +#define SNVS_HPSR_BTN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSR_BTN_SHIFT)) & SNVS_HPSR_BTN_MASK) +#define SNVS_HPSR_BI_MASK (0x80U) +#define SNVS_HPSR_BI_SHIFT (7U) +#define SNVS_HPSR_BI(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSR_BI_SHIFT)) & SNVS_HPSR_BI_MASK) +#define SNVS_HPSR_SSM_STATE_MASK (0xF00U) +#define SNVS_HPSR_SSM_STATE_SHIFT (8U) +/*! SSM_STATE + * 0b0000..Init + * 0b0001..Hard Fail + * 0b0011..Soft Fail + * 0b1000..Init Intermediate (transition state between Init and Check - SSM stays in this state only one clock cycle) + * 0b1001..Check + * 0b1011..Non-Secure + * 0b1101..Trusted + * 0b1111..Secure + */ +#define SNVS_HPSR_SSM_STATE(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSR_SSM_STATE_SHIFT)) & SNVS_HPSR_SSM_STATE_MASK) +#define SNVS_HPSR_SECURITY_CONFIG_MASK (0xF000U) +#define SNVS_HPSR_SECURITY_CONFIG_SHIFT (12U) +/*! SECURITY_CONFIG + * 0b0000, 0b1000..FAB configuration + * 0b0001, 0b0010, 0b0011..OPEN configuration + * 0b1010, 0b1001, 0b1011..CLOSED configuration + * 0bx1xx..FIELD RETURN configuration + */ +#define SNVS_HPSR_SECURITY_CONFIG(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSR_SECURITY_CONFIG_SHIFT)) & SNVS_HPSR_SECURITY_CONFIG_MASK) +#define SNVS_HPSR_OTPMK_SYNDROME_MASK (0x1FF0000U) +#define SNVS_HPSR_OTPMK_SYNDROME_SHIFT (16U) +#define SNVS_HPSR_OTPMK_SYNDROME(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSR_OTPMK_SYNDROME_SHIFT)) & SNVS_HPSR_OTPMK_SYNDROME_MASK) +#define SNVS_HPSR_OTPMK_ZERO_MASK (0x8000000U) +#define SNVS_HPSR_OTPMK_ZERO_SHIFT (27U) +/*! OTPMK_ZERO + * 0b0..The OTPMK is not zero. + * 0b1..The OTPMK is zero. + */ +#define SNVS_HPSR_OTPMK_ZERO(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSR_OTPMK_ZERO_SHIFT)) & SNVS_HPSR_OTPMK_ZERO_MASK) +#define SNVS_HPSR_ZMK_ZERO_MASK (0x80000000U) +#define SNVS_HPSR_ZMK_ZERO_SHIFT (31U) +/*! ZMK_ZERO + * 0b0..The ZMK is not zero. + * 0b1..The ZMK is zero. + */ +#define SNVS_HPSR_ZMK_ZERO(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSR_ZMK_ZERO_SHIFT)) & SNVS_HPSR_ZMK_ZERO_MASK) +/*! @} */ + +/*! @name HPSVSR - SNVS_HP Security Violation Status Register */ +/*! @{ */ +#define SNVS_HPSVSR_SV0_MASK (0x1U) +#define SNVS_HPSVSR_SV0_SHIFT (0U) +/*! SV0 + * 0b0..No Security Violation 0 security violation was detected. + * 0b1..Security Violation 0 security violation was detected. + */ +#define SNVS_HPSVSR_SV0(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVSR_SV0_SHIFT)) & SNVS_HPSVSR_SV0_MASK) +#define SNVS_HPSVSR_SV1_MASK (0x2U) +#define SNVS_HPSVSR_SV1_SHIFT (1U) +/*! SV1 + * 0b0..No Security Violation 1 security violation was detected. + * 0b1..Security Violation 1 security violation was detected. + */ +#define SNVS_HPSVSR_SV1(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVSR_SV1_SHIFT)) & SNVS_HPSVSR_SV1_MASK) +#define SNVS_HPSVSR_SV2_MASK (0x4U) +#define SNVS_HPSVSR_SV2_SHIFT (2U) +/*! SV2 + * 0b0..No Security Violation 2 security violation was detected. + * 0b1..Security Violation 2 security violation was detected. + */ +#define SNVS_HPSVSR_SV2(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVSR_SV2_SHIFT)) & SNVS_HPSVSR_SV2_MASK) +#define SNVS_HPSVSR_SV3_MASK (0x8U) +#define SNVS_HPSVSR_SV3_SHIFT (3U) +/*! SV3 + * 0b0..No Security Violation 3 security violation was detected. + * 0b1..Security Violation 3 security violation was detected. + */ +#define SNVS_HPSVSR_SV3(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVSR_SV3_SHIFT)) & SNVS_HPSVSR_SV3_MASK) +#define SNVS_HPSVSR_SV4_MASK (0x10U) +#define SNVS_HPSVSR_SV4_SHIFT (4U) +/*! SV4 + * 0b0..No Security Violation 4 security violation was detected. + * 0b1..Security Violation 4 security violation was detected. + */ +#define SNVS_HPSVSR_SV4(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVSR_SV4_SHIFT)) & SNVS_HPSVSR_SV4_MASK) +#define SNVS_HPSVSR_SV5_MASK (0x20U) +#define SNVS_HPSVSR_SV5_SHIFT (5U) +/*! SV5 + * 0b0..No Security Violation 5 security violation was detected. + * 0b1..Security Violation 5 security violation was detected. + */ +#define SNVS_HPSVSR_SV5(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVSR_SV5_SHIFT)) & SNVS_HPSVSR_SV5_MASK) +#define SNVS_HPSVSR_SW_SV_MASK (0x2000U) +#define SNVS_HPSVSR_SW_SV_SHIFT (13U) +#define SNVS_HPSVSR_SW_SV(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVSR_SW_SV_SHIFT)) & SNVS_HPSVSR_SW_SV_MASK) +#define SNVS_HPSVSR_SW_FSV_MASK (0x4000U) +#define SNVS_HPSVSR_SW_FSV_SHIFT (14U) +#define SNVS_HPSVSR_SW_FSV(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVSR_SW_FSV_SHIFT)) & SNVS_HPSVSR_SW_FSV_MASK) +#define SNVS_HPSVSR_SW_LPSV_MASK (0x8000U) +#define SNVS_HPSVSR_SW_LPSV_SHIFT (15U) +#define SNVS_HPSVSR_SW_LPSV(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVSR_SW_LPSV_SHIFT)) & SNVS_HPSVSR_SW_LPSV_MASK) +#define SNVS_HPSVSR_ZMK_SYNDROME_MASK (0x1FF0000U) +#define SNVS_HPSVSR_ZMK_SYNDROME_SHIFT (16U) +#define SNVS_HPSVSR_ZMK_SYNDROME(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVSR_ZMK_SYNDROME_SHIFT)) & SNVS_HPSVSR_ZMK_SYNDROME_MASK) +#define SNVS_HPSVSR_ZMK_ECC_FAIL_MASK (0x8000000U) +#define SNVS_HPSVSR_ZMK_ECC_FAIL_SHIFT (27U) +/*! ZMK_ECC_FAIL + * 0b0..ZMK ECC Failure was not detected. + * 0b1..ZMK ECC Failure was detected. + */ +#define SNVS_HPSVSR_ZMK_ECC_FAIL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVSR_ZMK_ECC_FAIL_SHIFT)) & SNVS_HPSVSR_ZMK_ECC_FAIL_MASK) +#define SNVS_HPSVSR_LP_SEC_VIO_MASK (0x80000000U) +#define SNVS_HPSVSR_LP_SEC_VIO_SHIFT (31U) +#define SNVS_HPSVSR_LP_SEC_VIO(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVSR_LP_SEC_VIO_SHIFT)) & SNVS_HPSVSR_LP_SEC_VIO_MASK) +/*! @} */ + +/*! @name HPHACIVR - SNVS_HP High Assurance Counter IV Register */ +/*! @{ */ +#define SNVS_HPHACIVR_HAC_COUNTER_IV_MASK (0xFFFFFFFFU) +#define SNVS_HPHACIVR_HAC_COUNTER_IV_SHIFT (0U) +#define SNVS_HPHACIVR_HAC_COUNTER_IV(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPHACIVR_HAC_COUNTER_IV_SHIFT)) & SNVS_HPHACIVR_HAC_COUNTER_IV_MASK) +/*! @} */ + +/*! @name HPHACR - SNVS_HP High Assurance Counter Register */ +/*! @{ */ +#define SNVS_HPHACR_HAC_COUNTER_MASK (0xFFFFFFFFU) +#define SNVS_HPHACR_HAC_COUNTER_SHIFT (0U) +#define SNVS_HPHACR_HAC_COUNTER(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPHACR_HAC_COUNTER_SHIFT)) & SNVS_HPHACR_HAC_COUNTER_MASK) +/*! @} */ + +/*! @name HPRTCMR - SNVS_HP Real Time Counter MSB Register */ +/*! @{ */ +#define SNVS_HPRTCMR_RTC_MASK (0x7FFFU) +#define SNVS_HPRTCMR_RTC_SHIFT (0U) +#define SNVS_HPRTCMR_RTC(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPRTCMR_RTC_SHIFT)) & SNVS_HPRTCMR_RTC_MASK) +/*! @} */ + +/*! @name HPRTCLR - SNVS_HP Real Time Counter LSB Register */ +/*! @{ */ +#define SNVS_HPRTCLR_RTC_MASK (0xFFFFFFFFU) +#define SNVS_HPRTCLR_RTC_SHIFT (0U) +#define SNVS_HPRTCLR_RTC(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPRTCLR_RTC_SHIFT)) & SNVS_HPRTCLR_RTC_MASK) +/*! @} */ + +/*! @name HPTAMR - SNVS_HP Time Alarm MSB Register */ +/*! @{ */ +#define SNVS_HPTAMR_HPTA_MS_MASK (0x7FFFU) +#define SNVS_HPTAMR_HPTA_MS_SHIFT (0U) +#define SNVS_HPTAMR_HPTA_MS(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPTAMR_HPTA_MS_SHIFT)) & SNVS_HPTAMR_HPTA_MS_MASK) +/*! @} */ + +/*! @name HPTALR - SNVS_HP Time Alarm LSB Register */ +/*! @{ */ +#define SNVS_HPTALR_HPTA_LS_MASK (0xFFFFFFFFU) +#define SNVS_HPTALR_HPTA_LS_SHIFT (0U) +#define SNVS_HPTALR_HPTA_LS(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPTALR_HPTA_LS_SHIFT)) & SNVS_HPTALR_HPTA_LS_MASK) +/*! @} */ + +/*! @name LPLR - SNVS_LP Lock Register */ +/*! @{ */ +#define SNVS_LPLR_ZMK_WHL_MASK (0x1U) +#define SNVS_LPLR_ZMK_WHL_SHIFT (0U) +/*! ZMK_WHL + * 0b0..Write access is allowed. + * 0b1..Write access is not allowed. + */ +#define SNVS_LPLR_ZMK_WHL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPLR_ZMK_WHL_SHIFT)) & SNVS_LPLR_ZMK_WHL_MASK) +#define SNVS_LPLR_ZMK_RHL_MASK (0x2U) +#define SNVS_LPLR_ZMK_RHL_SHIFT (1U) +/*! ZMK_RHL + * 0b0..Read access is allowed (only in software programming mode). + * 0b1..Read access is not allowed. + */ +#define SNVS_LPLR_ZMK_RHL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPLR_ZMK_RHL_SHIFT)) & SNVS_LPLR_ZMK_RHL_MASK) +#define SNVS_LPLR_SRTC_HL_MASK (0x4U) +#define SNVS_LPLR_SRTC_HL_SHIFT (2U) +/*! SRTC_HL + * 0b0..Write access is allowed. + * 0b1..Write access is not allowed. + */ +#define SNVS_LPLR_SRTC_HL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPLR_SRTC_HL_SHIFT)) & SNVS_LPLR_SRTC_HL_MASK) +#define SNVS_LPLR_LPCALB_HL_MASK (0x8U) +#define SNVS_LPLR_LPCALB_HL_SHIFT (3U) +/*! LPCALB_HL + * 0b0..Write access is allowed. + * 0b1..Write access is not allowed. + */ +#define SNVS_LPLR_LPCALB_HL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPLR_LPCALB_HL_SHIFT)) & SNVS_LPLR_LPCALB_HL_MASK) +#define SNVS_LPLR_MC_HL_MASK (0x10U) +#define SNVS_LPLR_MC_HL_SHIFT (4U) +/*! MC_HL + * 0b0..Write access (increment) is allowed. + * 0b1..Write access (increment) is not allowed. + */ +#define SNVS_LPLR_MC_HL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPLR_MC_HL_SHIFT)) & SNVS_LPLR_MC_HL_MASK) +#define SNVS_LPLR_GPR_HL_MASK (0x20U) +#define SNVS_LPLR_GPR_HL_SHIFT (5U) +/*! GPR_HL + * 0b0..Write access is allowed. + * 0b1..Write access is not allowed. + */ +#define SNVS_LPLR_GPR_HL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPLR_GPR_HL_SHIFT)) & SNVS_LPLR_GPR_HL_MASK) +#define SNVS_LPLR_LPSVCR_HL_MASK (0x40U) +#define SNVS_LPLR_LPSVCR_HL_SHIFT (6U) +/*! LPSVCR_HL + * 0b0..Write access is allowed. + * 0b1..Write access is not allowed. + */ +#define SNVS_LPLR_LPSVCR_HL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPLR_LPSVCR_HL_SHIFT)) & SNVS_LPLR_LPSVCR_HL_MASK) +#define SNVS_LPLR_LPTDCR_HL_MASK (0x100U) +#define SNVS_LPLR_LPTDCR_HL_SHIFT (8U) +/*! LPTDCR_HL + * 0b0..Write access is allowed. + * 0b1..Write access is not allowed. + */ +#define SNVS_LPLR_LPTDCR_HL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPLR_LPTDCR_HL_SHIFT)) & SNVS_LPLR_LPTDCR_HL_MASK) +#define SNVS_LPLR_MKS_HL_MASK (0x200U) +#define SNVS_LPLR_MKS_HL_SHIFT (9U) +/*! MKS_HL + * 0b0..Write access is allowed. + * 0b1..Write access is not allowed. + */ +#define SNVS_LPLR_MKS_HL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPLR_MKS_HL_SHIFT)) & SNVS_LPLR_MKS_HL_MASK) +/*! @} */ + +/*! @name LPCR - SNVS_LP Control Register */ +/*! @{ */ +#define SNVS_LPCR_SRTC_ENV_MASK (0x1U) +#define SNVS_LPCR_SRTC_ENV_SHIFT (0U) +/*! SRTC_ENV + * 0b0..SRTC is disabled or invalid. + * 0b1..SRTC is enabled and valid. + */ +#define SNVS_LPCR_SRTC_ENV(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_SRTC_ENV_SHIFT)) & SNVS_LPCR_SRTC_ENV_MASK) +#define SNVS_LPCR_LPTA_EN_MASK (0x2U) +#define SNVS_LPCR_LPTA_EN_SHIFT (1U) +/*! LPTA_EN + * 0b0..LP time alarm interrupt is disabled. + * 0b1..LP time alarm interrupt is enabled. + */ +#define SNVS_LPCR_LPTA_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_LPTA_EN_SHIFT)) & SNVS_LPCR_LPTA_EN_MASK) +#define SNVS_LPCR_MC_ENV_MASK (0x4U) +#define SNVS_LPCR_MC_ENV_SHIFT (2U) +/*! MC_ENV + * 0b0..MC is disabled or invalid. + * 0b1..MC is enabled and valid. + */ +#define SNVS_LPCR_MC_ENV(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_MC_ENV_SHIFT)) & SNVS_LPCR_MC_ENV_MASK) +#define SNVS_LPCR_LPWUI_EN_MASK (0x8U) +#define SNVS_LPCR_LPWUI_EN_SHIFT (3U) +#define SNVS_LPCR_LPWUI_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_LPWUI_EN_SHIFT)) & SNVS_LPCR_LPWUI_EN_MASK) +#define SNVS_LPCR_SRTC_INV_EN_MASK (0x10U) +#define SNVS_LPCR_SRTC_INV_EN_SHIFT (4U) +/*! SRTC_INV_EN + * 0b0..SRTC stays valid in the case of security violation. + * 0b1..SRTC is invalidated in the case of security violation. + */ +#define SNVS_LPCR_SRTC_INV_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_SRTC_INV_EN_SHIFT)) & SNVS_LPCR_SRTC_INV_EN_MASK) +#define SNVS_LPCR_DP_EN_MASK (0x20U) +#define SNVS_LPCR_DP_EN_SHIFT (5U) +/*! DP_EN + * 0b0..Smart PMIC enabled. + * 0b1..Dumb PMIC enabled. + */ +#define SNVS_LPCR_DP_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_DP_EN_SHIFT)) & SNVS_LPCR_DP_EN_MASK) +#define SNVS_LPCR_TOP_MASK (0x40U) +#define SNVS_LPCR_TOP_SHIFT (6U) +/*! TOP + * 0b0..Leave system power on. + * 0b1..Turn off system power. + */ +#define SNVS_LPCR_TOP(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_TOP_SHIFT)) & SNVS_LPCR_TOP_MASK) +#define SNVS_LPCR_PWR_GLITCH_EN_MASK (0x80U) +#define SNVS_LPCR_PWR_GLITCH_EN_SHIFT (7U) +#define SNVS_LPCR_PWR_GLITCH_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_PWR_GLITCH_EN_SHIFT)) & SNVS_LPCR_PWR_GLITCH_EN_MASK) +#define SNVS_LPCR_LPCALB_EN_MASK (0x100U) +#define SNVS_LPCR_LPCALB_EN_SHIFT (8U) +/*! LPCALB_EN + * 0b0..SRTC Time calibration is disabled. + * 0b1..SRTC Time calibration is enabled. + */ +#define SNVS_LPCR_LPCALB_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_LPCALB_EN_SHIFT)) & SNVS_LPCR_LPCALB_EN_MASK) +#define SNVS_LPCR_LPCALB_VAL_MASK (0x7C00U) +#define SNVS_LPCR_LPCALB_VAL_SHIFT (10U) +/*! LPCALB_VAL + * 0b00000..+0 counts per each 32768 ticks of the counter clock + * 0b00001..+1 counts per each 32768 ticks of the counter clock + * 0b00010..+2 counts per each 32768 ticks of the counter clock + * 0b01111..+15 counts per each 32768 ticks of the counter clock + * 0b10000..-16 counts per each 32768 ticks of the counter clock + * 0b10001..-15 counts per each 32768 ticks of the counter clock + * 0b11110..-2 counts per each 32768 ticks of the counter clock + * 0b11111..-1 counts per each 32768 ticks of the counter clock + */ +#define SNVS_LPCR_LPCALB_VAL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_LPCALB_VAL_SHIFT)) & SNVS_LPCR_LPCALB_VAL_MASK) +#define SNVS_LPCR_BTN_PRESS_TIME_MASK (0x30000U) +#define SNVS_LPCR_BTN_PRESS_TIME_SHIFT (16U) +#define SNVS_LPCR_BTN_PRESS_TIME(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_BTN_PRESS_TIME_SHIFT)) & SNVS_LPCR_BTN_PRESS_TIME_MASK) +#define SNVS_LPCR_DEBOUNCE_MASK (0xC0000U) +#define SNVS_LPCR_DEBOUNCE_SHIFT (18U) +#define SNVS_LPCR_DEBOUNCE(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_DEBOUNCE_SHIFT)) & SNVS_LPCR_DEBOUNCE_MASK) +#define SNVS_LPCR_ON_TIME_MASK (0x300000U) +#define SNVS_LPCR_ON_TIME_SHIFT (20U) +#define SNVS_LPCR_ON_TIME(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_ON_TIME_SHIFT)) & SNVS_LPCR_ON_TIME_MASK) +#define SNVS_LPCR_PK_EN_MASK (0x400000U) +#define SNVS_LPCR_PK_EN_SHIFT (22U) +#define SNVS_LPCR_PK_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_PK_EN_SHIFT)) & SNVS_LPCR_PK_EN_MASK) +#define SNVS_LPCR_PK_OVERRIDE_MASK (0x800000U) +#define SNVS_LPCR_PK_OVERRIDE_SHIFT (23U) +#define SNVS_LPCR_PK_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_PK_OVERRIDE_SHIFT)) & SNVS_LPCR_PK_OVERRIDE_MASK) +#define SNVS_LPCR_GPR_Z_DIS_MASK (0x1000000U) +#define SNVS_LPCR_GPR_Z_DIS_SHIFT (24U) +#define SNVS_LPCR_GPR_Z_DIS(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_GPR_Z_DIS_SHIFT)) & SNVS_LPCR_GPR_Z_DIS_MASK) +/*! @} */ + +/*! @name LPMKCR - SNVS_LP Master Key Control Register */ +/*! @{ */ +#define SNVS_LPMKCR_MASTER_KEY_SEL_MASK (0x3U) +#define SNVS_LPMKCR_MASTER_KEY_SEL_SHIFT (0U) +/*! MASTER_KEY_SEL + * 0b0x..Select one time programmable master key. + * 0b10..Select zeroizable master key when MKS_EN bit is set . + * 0b11..Select combined master key when MKS_EN bit is set . + */ +#define SNVS_LPMKCR_MASTER_KEY_SEL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPMKCR_MASTER_KEY_SEL_SHIFT)) & SNVS_LPMKCR_MASTER_KEY_SEL_MASK) +#define SNVS_LPMKCR_ZMK_HWP_MASK (0x4U) +#define SNVS_LPMKCR_ZMK_HWP_SHIFT (2U) +/*! ZMK_HWP + * 0b0..ZMK is in the software programming mode. + * 0b1..ZMK is in the hardware programming mode. + */ +#define SNVS_LPMKCR_ZMK_HWP(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPMKCR_ZMK_HWP_SHIFT)) & SNVS_LPMKCR_ZMK_HWP_MASK) +#define SNVS_LPMKCR_ZMK_VAL_MASK (0x8U) +#define SNVS_LPMKCR_ZMK_VAL_SHIFT (3U) +/*! ZMK_VAL + * 0b0..ZMK is not valid. + * 0b1..ZMK is valid. + */ +#define SNVS_LPMKCR_ZMK_VAL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPMKCR_ZMK_VAL_SHIFT)) & SNVS_LPMKCR_ZMK_VAL_MASK) +#define SNVS_LPMKCR_ZMK_ECC_EN_MASK (0x10U) +#define SNVS_LPMKCR_ZMK_ECC_EN_SHIFT (4U) +/*! ZMK_ECC_EN + * 0b0..ZMK ECC check is disabled. + * 0b1..ZMK ECC check is enabled. + */ +#define SNVS_LPMKCR_ZMK_ECC_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPMKCR_ZMK_ECC_EN_SHIFT)) & SNVS_LPMKCR_ZMK_ECC_EN_MASK) +#define SNVS_LPMKCR_ZMK_ECC_VALUE_MASK (0xFF80U) +#define SNVS_LPMKCR_ZMK_ECC_VALUE_SHIFT (7U) +#define SNVS_LPMKCR_ZMK_ECC_VALUE(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPMKCR_ZMK_ECC_VALUE_SHIFT)) & SNVS_LPMKCR_ZMK_ECC_VALUE_MASK) +/*! @} */ + +/*! @name LPSVCR - SNVS_LP Security Violation Control Register */ +/*! @{ */ +#define SNVS_LPSVCR_SV0_EN_MASK (0x1U) +#define SNVS_LPSVCR_SV0_EN_SHIFT (0U) +/*! SV0_EN + * 0b0..Security Violation 0 is disabled in the LP domain. + * 0b1..Security Violation 0 is enabled in the LP domain. + */ +#define SNVS_LPSVCR_SV0_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSVCR_SV0_EN_SHIFT)) & SNVS_LPSVCR_SV0_EN_MASK) +#define SNVS_LPSVCR_SV1_EN_MASK (0x2U) +#define SNVS_LPSVCR_SV1_EN_SHIFT (1U) +/*! SV1_EN + * 0b0..Security Violation 1 is disabled in the LP domain. + * 0b1..Security Violation 1 is enabled in the LP domain. + */ +#define SNVS_LPSVCR_SV1_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSVCR_SV1_EN_SHIFT)) & SNVS_LPSVCR_SV1_EN_MASK) +#define SNVS_LPSVCR_SV2_EN_MASK (0x4U) +#define SNVS_LPSVCR_SV2_EN_SHIFT (2U) +/*! SV2_EN + * 0b0..Security Violation 2 is disabled in the LP domain. + * 0b1..Security Violation 2 is enabled in the LP domain. + */ +#define SNVS_LPSVCR_SV2_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSVCR_SV2_EN_SHIFT)) & SNVS_LPSVCR_SV2_EN_MASK) +#define SNVS_LPSVCR_SV3_EN_MASK (0x8U) +#define SNVS_LPSVCR_SV3_EN_SHIFT (3U) +/*! SV3_EN + * 0b0..Security Violation 3 is disabled in the LP domain. + * 0b1..Security Violation 3 is enabled in the LP domain. + */ +#define SNVS_LPSVCR_SV3_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSVCR_SV3_EN_SHIFT)) & SNVS_LPSVCR_SV3_EN_MASK) +#define SNVS_LPSVCR_SV4_EN_MASK (0x10U) +#define SNVS_LPSVCR_SV4_EN_SHIFT (4U) +/*! SV4_EN + * 0b0..Security Violation 4 is disabled in the LP domain. + * 0b1..Security Violation 4 is enabled in the LP domain. + */ +#define SNVS_LPSVCR_SV4_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSVCR_SV4_EN_SHIFT)) & SNVS_LPSVCR_SV4_EN_MASK) +#define SNVS_LPSVCR_SV5_EN_MASK (0x20U) +#define SNVS_LPSVCR_SV5_EN_SHIFT (5U) +/*! SV5_EN + * 0b0..Security Violation 5 is disabled in the LP domain. + * 0b1..Security Violation 5 is enabled in the LP domain. + */ +#define SNVS_LPSVCR_SV5_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSVCR_SV5_EN_SHIFT)) & SNVS_LPSVCR_SV5_EN_MASK) +/*! @} */ + +/*! @name LPTDCR - SNVS_LP Tamper Detectors Configuration Register */ +/*! @{ */ +#define SNVS_LPTDCR_SRTCR_EN_MASK (0x2U) +#define SNVS_LPTDCR_SRTCR_EN_SHIFT (1U) +/*! SRTCR_EN + * 0b0..SRTC rollover is disabled. + * 0b1..SRTC rollover is enabled. + */ +#define SNVS_LPTDCR_SRTCR_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDCR_SRTCR_EN_SHIFT)) & SNVS_LPTDCR_SRTCR_EN_MASK) +#define SNVS_LPTDCR_MCR_EN_MASK (0x4U) +#define SNVS_LPTDCR_MCR_EN_SHIFT (2U) +/*! MCR_EN + * 0b0..MC rollover is disabled. + * 0b1..MC rollover is enabled. + */ +#define SNVS_LPTDCR_MCR_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDCR_MCR_EN_SHIFT)) & SNVS_LPTDCR_MCR_EN_MASK) +#define SNVS_LPTDCR_ET1_EN_MASK (0x200U) +#define SNVS_LPTDCR_ET1_EN_SHIFT (9U) +/*! ET1_EN + * 0b0..External tamper 1 is disabled. + * 0b1..External tamper 1 is enabled. + */ +#define SNVS_LPTDCR_ET1_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDCR_ET1_EN_SHIFT)) & SNVS_LPTDCR_ET1_EN_MASK) +#define SNVS_LPTDCR_ET1P_MASK (0x800U) +#define SNVS_LPTDCR_ET1P_SHIFT (11U) +/*! ET1P + * 0b0..External tamper 1 is active low. + * 0b1..External tamper 1 is active high. + */ +#define SNVS_LPTDCR_ET1P(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDCR_ET1P_SHIFT)) & SNVS_LPTDCR_ET1P_MASK) +#define SNVS_LPTDCR_PFD_OBSERV_MASK (0x4000U) +#define SNVS_LPTDCR_PFD_OBSERV_SHIFT (14U) +#define SNVS_LPTDCR_PFD_OBSERV(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDCR_PFD_OBSERV_SHIFT)) & SNVS_LPTDCR_PFD_OBSERV_MASK) +#define SNVS_LPTDCR_POR_OBSERV_MASK (0x8000U) +#define SNVS_LPTDCR_POR_OBSERV_SHIFT (15U) +#define SNVS_LPTDCR_POR_OBSERV(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDCR_POR_OBSERV_SHIFT)) & SNVS_LPTDCR_POR_OBSERV_MASK) +#define SNVS_LPTDCR_OSCB_MASK (0x10000000U) +#define SNVS_LPTDCR_OSCB_SHIFT (28U) +/*! OSCB + * 0b0..Normal SRTC clock oscillator not bypassed. + * 0b1..Normal SRTC clock oscillator bypassed. Alternate clock can drive the SRTC clock source. + */ +#define SNVS_LPTDCR_OSCB(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDCR_OSCB_SHIFT)) & SNVS_LPTDCR_OSCB_MASK) +/*! @} */ + +/*! @name LPSR - SNVS_LP Status Register */ +/*! @{ */ +#define SNVS_LPSR_LPTA_MASK (0x1U) +#define SNVS_LPSR_LPTA_SHIFT (0U) +/*! LPTA + * 0b0..No time alarm interrupt occurred. + * 0b1..A time alarm interrupt occurred. + */ +#define SNVS_LPSR_LPTA(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_LPTA_SHIFT)) & SNVS_LPSR_LPTA_MASK) +#define SNVS_LPSR_SRTCR_MASK (0x2U) +#define SNVS_LPSR_SRTCR_SHIFT (1U) +/*! SRTCR + * 0b0..SRTC has not reached its maximum value. + * 0b1..SRTC has reached its maximum value. + */ +#define SNVS_LPSR_SRTCR(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_SRTCR_SHIFT)) & SNVS_LPSR_SRTCR_MASK) +#define SNVS_LPSR_MCR_MASK (0x4U) +#define SNVS_LPSR_MCR_SHIFT (2U) +/*! MCR + * 0b0..MC has not reached its maximum value. + * 0b1..MC has reached its maximum value. + */ +#define SNVS_LPSR_MCR(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_MCR_SHIFT)) & SNVS_LPSR_MCR_MASK) +#define SNVS_LPSR_PGD_MASK (0x8U) +#define SNVS_LPSR_PGD_SHIFT (3U) +#define SNVS_LPSR_PGD(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_PGD_SHIFT)) & SNVS_LPSR_PGD_MASK) +#define SNVS_LPSR_ET1D_MASK (0x200U) +#define SNVS_LPSR_ET1D_SHIFT (9U) +/*! ET1D + * 0b0..External tampering 1 not detected. + * 0b1..External tampering 1 detected. + */ +#define SNVS_LPSR_ET1D(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_ET1D_SHIFT)) & SNVS_LPSR_ET1D_MASK) +#define SNVS_LPSR_ESVD_MASK (0x10000U) +#define SNVS_LPSR_ESVD_SHIFT (16U) +/*! ESVD + * 0b0..No external security violation. + * 0b1..External security violation is detected. + */ +#define SNVS_LPSR_ESVD(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_ESVD_SHIFT)) & SNVS_LPSR_ESVD_MASK) +#define SNVS_LPSR_EO_MASK (0x20000U) +#define SNVS_LPSR_EO_SHIFT (17U) +/*! EO + * 0b0..Emergency off was not detected. + * 0b1..Emergency off was detected. + */ +#define SNVS_LPSR_EO(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_EO_SHIFT)) & SNVS_LPSR_EO_MASK) +#define SNVS_LPSR_SPO_MASK (0x40000U) +#define SNVS_LPSR_SPO_SHIFT (18U) +/*! SPO + * 0b0..Set Power Off was not detected. + * 0b1..Set Power Off was detected. + */ +#define SNVS_LPSR_SPO(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_SPO_SHIFT)) & SNVS_LPSR_SPO_MASK) +#define SNVS_LPSR_SED_MASK (0x100000U) +#define SNVS_LPSR_SED_SHIFT (20U) +/*! SED + * 0b0..Scan exit was not detected. + * 0b1..Scan exit was detected. + */ +#define SNVS_LPSR_SED(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_SED_SHIFT)) & SNVS_LPSR_SED_MASK) +#define SNVS_LPSR_LPNS_MASK (0x40000000U) +#define SNVS_LPSR_LPNS_SHIFT (30U) +/*! LPNS + * 0b0..LP section was not programmed in the non-secure state. + * 0b1..LP section was programmed in the non-secure state. + */ +#define SNVS_LPSR_LPNS(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_LPNS_SHIFT)) & SNVS_LPSR_LPNS_MASK) +#define SNVS_LPSR_LPS_MASK (0x80000000U) +#define SNVS_LPSR_LPS_SHIFT (31U) +/*! LPS + * 0b0..LP section was not programmed in secure or trusted state. + * 0b1..LP section was programmed in secure or trusted state. + */ +#define SNVS_LPSR_LPS(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_LPS_SHIFT)) & SNVS_LPSR_LPS_MASK) +/*! @} */ + +/*! @name LPSRTCMR - SNVS_LP Secure Real Time Counter MSB Register */ +/*! @{ */ +#define SNVS_LPSRTCMR_SRTC_MASK (0x7FFFU) +#define SNVS_LPSRTCMR_SRTC_SHIFT (0U) +#define SNVS_LPSRTCMR_SRTC(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSRTCMR_SRTC_SHIFT)) & SNVS_LPSRTCMR_SRTC_MASK) +/*! @} */ + +/*! @name LPSRTCLR - SNVS_LP Secure Real Time Counter LSB Register */ +/*! @{ */ +#define SNVS_LPSRTCLR_SRTC_MASK (0xFFFFFFFFU) +#define SNVS_LPSRTCLR_SRTC_SHIFT (0U) +#define SNVS_LPSRTCLR_SRTC(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSRTCLR_SRTC_SHIFT)) & SNVS_LPSRTCLR_SRTC_MASK) +/*! @} */ + +/*! @name LPTAR - SNVS_LP Time Alarm Register */ +/*! @{ */ +#define SNVS_LPTAR_LPTA_MASK (0xFFFFFFFFU) +#define SNVS_LPTAR_LPTA_SHIFT (0U) +#define SNVS_LPTAR_LPTA(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPTAR_LPTA_SHIFT)) & SNVS_LPTAR_LPTA_MASK) +/*! @} */ + +/*! @name LPSMCMR - SNVS_LP Secure Monotonic Counter MSB Register */ +/*! @{ */ +#define SNVS_LPSMCMR_MON_COUNTER_MASK (0xFFFFU) +#define SNVS_LPSMCMR_MON_COUNTER_SHIFT (0U) +#define SNVS_LPSMCMR_MON_COUNTER(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSMCMR_MON_COUNTER_SHIFT)) & SNVS_LPSMCMR_MON_COUNTER_MASK) +#define SNVS_LPSMCMR_MC_ERA_BITS_MASK (0xFFFF0000U) +#define SNVS_LPSMCMR_MC_ERA_BITS_SHIFT (16U) +#define SNVS_LPSMCMR_MC_ERA_BITS(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSMCMR_MC_ERA_BITS_SHIFT)) & SNVS_LPSMCMR_MC_ERA_BITS_MASK) +/*! @} */ + +/*! @name LPSMCLR - SNVS_LP Secure Monotonic Counter LSB Register */ +/*! @{ */ +#define SNVS_LPSMCLR_MON_COUNTER_MASK (0xFFFFFFFFU) +#define SNVS_LPSMCLR_MON_COUNTER_SHIFT (0U) +#define SNVS_LPSMCLR_MON_COUNTER(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSMCLR_MON_COUNTER_SHIFT)) & SNVS_LPSMCLR_MON_COUNTER_MASK) +/*! @} */ + +/*! @name LPPGDR - SNVS_LP Power Glitch Detector Register */ +/*! @{ */ +#define SNVS_LPPGDR_PGD_MASK (0xFFFFFFFFU) +#define SNVS_LPPGDR_PGD_SHIFT (0U) +#define SNVS_LPPGDR_PGD(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPPGDR_PGD_SHIFT)) & SNVS_LPPGDR_PGD_MASK) +/*! @} */ + +/*! @name LPGPR0_LEGACY_ALIAS - SNVS_LP General Purpose Register 0 (legacy alias) */ +/*! @{ */ +#define SNVS_LPGPR0_LEGACY_ALIAS_GPR_MASK (0xFFFFFFFFU) +#define SNVS_LPGPR0_LEGACY_ALIAS_GPR_SHIFT (0U) +#define SNVS_LPGPR0_LEGACY_ALIAS_GPR(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPGPR0_LEGACY_ALIAS_GPR_SHIFT)) & SNVS_LPGPR0_LEGACY_ALIAS_GPR_MASK) +/*! @} */ + +/*! @name LPZMKR - SNVS_LP Zeroizable Master Key Register */ +/*! @{ */ +#define SNVS_LPZMKR_ZMK_MASK (0xFFFFFFFFU) +#define SNVS_LPZMKR_ZMK_SHIFT (0U) +#define SNVS_LPZMKR_ZMK(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPZMKR_ZMK_SHIFT)) & SNVS_LPZMKR_ZMK_MASK) +/*! @} */ + +/* The count of SNVS_LPZMKR */ +#define SNVS_LPZMKR_COUNT (8U) + +/*! @name LPGPR_ALIAS - SNVS_LP General Purpose Registers 0 .. 3 */ +/*! @{ */ +#define SNVS_LPGPR_ALIAS_GPR_MASK (0xFFFFFFFFU) +#define SNVS_LPGPR_ALIAS_GPR_SHIFT (0U) +#define SNVS_LPGPR_ALIAS_GPR(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPGPR_ALIAS_GPR_SHIFT)) & SNVS_LPGPR_ALIAS_GPR_MASK) +/*! @} */ + +/* The count of SNVS_LPGPR_ALIAS */ +#define SNVS_LPGPR_ALIAS_COUNT (4U) + +/*! @name LPGPR - SNVS_LP General Purpose Registers 0 .. 7 */ +/*! @{ */ +#define SNVS_LPGPR_GPR_MASK (0xFFFFFFFFU) +#define SNVS_LPGPR_GPR_SHIFT (0U) +#define SNVS_LPGPR_GPR(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPGPR_GPR_SHIFT)) & SNVS_LPGPR_GPR_MASK) +/*! @} */ + +/* The count of SNVS_LPGPR */ +#define SNVS_LPGPR_COUNT (8U) + +/*! @name HPVIDR1 - SNVS_HP Version ID Register 1 */ +/*! @{ */ +#define SNVS_HPVIDR1_MINOR_REV_MASK (0xFFU) +#define SNVS_HPVIDR1_MINOR_REV_SHIFT (0U) +#define SNVS_HPVIDR1_MINOR_REV(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPVIDR1_MINOR_REV_SHIFT)) & SNVS_HPVIDR1_MINOR_REV_MASK) +#define SNVS_HPVIDR1_MAJOR_REV_MASK (0xFF00U) +#define SNVS_HPVIDR1_MAJOR_REV_SHIFT (8U) +#define SNVS_HPVIDR1_MAJOR_REV(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPVIDR1_MAJOR_REV_SHIFT)) & SNVS_HPVIDR1_MAJOR_REV_MASK) +#define SNVS_HPVIDR1_IP_ID_MASK (0xFFFF0000U) +#define SNVS_HPVIDR1_IP_ID_SHIFT (16U) +#define SNVS_HPVIDR1_IP_ID(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPVIDR1_IP_ID_SHIFT)) & SNVS_HPVIDR1_IP_ID_MASK) +/*! @} */ + +/*! @name HPVIDR2 - SNVS_HP Version ID Register 2 */ +/*! @{ */ +#define SNVS_HPVIDR2_CONFIG_OPT_MASK (0xFFU) +#define SNVS_HPVIDR2_CONFIG_OPT_SHIFT (0U) +#define SNVS_HPVIDR2_CONFIG_OPT(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPVIDR2_CONFIG_OPT_SHIFT)) & SNVS_HPVIDR2_CONFIG_OPT_MASK) +#define SNVS_HPVIDR2_ECO_REV_MASK (0xFF00U) +#define SNVS_HPVIDR2_ECO_REV_SHIFT (8U) +#define SNVS_HPVIDR2_ECO_REV(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPVIDR2_ECO_REV_SHIFT)) & SNVS_HPVIDR2_ECO_REV_MASK) +#define SNVS_HPVIDR2_INTG_OPT_MASK (0xFF0000U) +#define SNVS_HPVIDR2_INTG_OPT_SHIFT (16U) +#define SNVS_HPVIDR2_INTG_OPT(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPVIDR2_INTG_OPT_SHIFT)) & SNVS_HPVIDR2_INTG_OPT_MASK) +#define SNVS_HPVIDR2_IP_ERA_MASK (0xFF000000U) +#define SNVS_HPVIDR2_IP_ERA_SHIFT (24U) +#define SNVS_HPVIDR2_IP_ERA(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPVIDR2_IP_ERA_SHIFT)) & SNVS_HPVIDR2_IP_ERA_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group SNVS_Register_Masks */ + + +/* SNVS - Peripheral instance base addresses */ +/** Peripheral SNVS base address */ +#define SNVS_BASE (0x400D4000u) +/** Peripheral SNVS base pointer */ +#define SNVS ((SNVS_Type *)SNVS_BASE) +/** Array initializer of SNVS peripheral base addresses */ +#define SNVS_BASE_ADDRS { SNVS_BASE } +/** Array initializer of SNVS peripheral base pointers */ +#define SNVS_BASE_PTRS { SNVS } +/** Interrupt vectors for the SNVS peripheral type */ +#define SNVS_IRQS { SNVS_LP_WRAPPER_IRQn } +#define SNVS_CONSOLIDATED_IRQS { SNVS_HP_WRAPPER_IRQn } +#define SNVS_SECURITY_IRQS { SNVS_HP_WRAPPER_TZ_IRQn } + +/*! + * @} + */ /* end of group SNVS_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- SPDIF Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup SPDIF_Peripheral_Access_Layer SPDIF Peripheral Access Layer + * @{ + */ + +/** SPDIF - Register Layout Typedef */ +typedef struct { + __IO uint32_t SCR; /**< SPDIF Configuration Register, offset: 0x0 */ + __IO uint32_t SRCD; /**< CDText Control Register, offset: 0x4 */ + __IO uint32_t SRPC; /**< PhaseConfig Register, offset: 0x8 */ + __IO uint32_t SIE; /**< InterruptEn Register, offset: 0xC */ + union { /* offset: 0x10 */ + __O uint32_t SIC; /**< InterruptClear Register, offset: 0x10 */ + __I uint32_t SIS; /**< InterruptStat Register, offset: 0x10 */ + }; + __I uint32_t SRL; /**< SPDIFRxLeft Register, offset: 0x14 */ + __I uint32_t SRR; /**< SPDIFRxRight Register, offset: 0x18 */ + __I uint32_t SRCSH; /**< SPDIFRxCChannel_h Register, offset: 0x1C */ + __I uint32_t SRCSL; /**< SPDIFRxCChannel_l Register, offset: 0x20 */ + __I uint32_t SRU; /**< UchannelRx Register, offset: 0x24 */ + __I uint32_t SRQ; /**< QchannelRx Register, offset: 0x28 */ + __O uint32_t STL; /**< SPDIFTxLeft Register, offset: 0x2C */ + __O uint32_t STR; /**< SPDIFTxRight Register, offset: 0x30 */ + __IO uint32_t STCSCH; /**< SPDIFTxCChannelCons_h Register, offset: 0x34 */ + __IO uint32_t STCSCL; /**< SPDIFTxCChannelCons_l Register, offset: 0x38 */ + uint8_t RESERVED_0[8]; + __I uint32_t SRFM; /**< FreqMeas Register, offset: 0x44 */ + uint8_t RESERVED_1[8]; + __IO uint32_t STC; /**< SPDIFTxClk Register, offset: 0x50 */ +} SPDIF_Type; + +/* ---------------------------------------------------------------------------- + -- SPDIF Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup SPDIF_Register_Masks SPDIF Register Masks + * @{ + */ + +/*! @name SCR - SPDIF Configuration Register */ +/*! @{ */ +#define SPDIF_SCR_USRC_SEL_MASK (0x3U) +#define SPDIF_SCR_USRC_SEL_SHIFT (0U) +/*! USrc_Sel + * 0b00..No embedded U channel + * 0b01..U channel from SPDIF receive block (CD mode) + * 0b10..Reserved + * 0b11..U channel from on chip transmitter + */ +#define SPDIF_SCR_USRC_SEL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_USRC_SEL_SHIFT)) & SPDIF_SCR_USRC_SEL_MASK) +#define SPDIF_SCR_TXSEL_MASK (0x1CU) +#define SPDIF_SCR_TXSEL_SHIFT (2U) +/*! TxSel + * 0b000..Off and output 0 + * 0b001..Feed-through SPDIFIN + * 0b101..Tx Normal operation + */ +#define SPDIF_SCR_TXSEL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_TXSEL_SHIFT)) & SPDIF_SCR_TXSEL_MASK) +#define SPDIF_SCR_VALCTRL_MASK (0x20U) +#define SPDIF_SCR_VALCTRL_SHIFT (5U) +/*! ValCtrl + * 0b0..Outgoing Validity always set + * 0b1..Outgoing Validity always clear + */ +#define SPDIF_SCR_VALCTRL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_VALCTRL_SHIFT)) & SPDIF_SCR_VALCTRL_MASK) +#define SPDIF_SCR_DMA_TX_EN_MASK (0x100U) +#define SPDIF_SCR_DMA_TX_EN_SHIFT (8U) +#define SPDIF_SCR_DMA_TX_EN(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_DMA_TX_EN_SHIFT)) & SPDIF_SCR_DMA_TX_EN_MASK) +#define SPDIF_SCR_DMA_RX_EN_MASK (0x200U) +#define SPDIF_SCR_DMA_RX_EN_SHIFT (9U) +#define SPDIF_SCR_DMA_RX_EN(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_DMA_RX_EN_SHIFT)) & SPDIF_SCR_DMA_RX_EN_MASK) +#define SPDIF_SCR_TXFIFO_CTRL_MASK (0xC00U) +#define SPDIF_SCR_TXFIFO_CTRL_SHIFT (10U) +/*! TxFIFO_Ctrl + * 0b00..Send out digital zero on SPDIF Tx + * 0b01..Tx Normal operation + * 0b10..Reset to 1 sample remaining + * 0b11..Reserved + */ +#define SPDIF_SCR_TXFIFO_CTRL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_TXFIFO_CTRL_SHIFT)) & SPDIF_SCR_TXFIFO_CTRL_MASK) +#define SPDIF_SCR_SOFT_RESET_MASK (0x1000U) +#define SPDIF_SCR_SOFT_RESET_SHIFT (12U) +#define SPDIF_SCR_SOFT_RESET(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_SOFT_RESET_SHIFT)) & SPDIF_SCR_SOFT_RESET_MASK) +#define SPDIF_SCR_LOW_POWER_MASK (0x2000U) +#define SPDIF_SCR_LOW_POWER_SHIFT (13U) +#define SPDIF_SCR_LOW_POWER(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_LOW_POWER_SHIFT)) & SPDIF_SCR_LOW_POWER_MASK) +#define SPDIF_SCR_TXFIFOEMPTY_SEL_MASK (0x18000U) +#define SPDIF_SCR_TXFIFOEMPTY_SEL_SHIFT (15U) +/*! TxFIFOEmpty_Sel + * 0b00..Empty interrupt if 0 sample in Tx left and right FIFOs + * 0b01..Empty interrupt if at most 4 sample in Tx left and right FIFOs + * 0b10..Empty interrupt if at most 8 sample in Tx left and right FIFOs + * 0b11..Empty interrupt if at most 12 sample in Tx left and right FIFOs + */ +#define SPDIF_SCR_TXFIFOEMPTY_SEL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_TXFIFOEMPTY_SEL_SHIFT)) & SPDIF_SCR_TXFIFOEMPTY_SEL_MASK) +#define SPDIF_SCR_TXAUTOSYNC_MASK (0x20000U) +#define SPDIF_SCR_TXAUTOSYNC_SHIFT (17U) +/*! TxAutoSync + * 0b0..Tx FIFO auto sync off + * 0b1..Tx FIFO auto sync on + */ +#define SPDIF_SCR_TXAUTOSYNC(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_TXAUTOSYNC_SHIFT)) & SPDIF_SCR_TXAUTOSYNC_MASK) +#define SPDIF_SCR_RXAUTOSYNC_MASK (0x40000U) +#define SPDIF_SCR_RXAUTOSYNC_SHIFT (18U) +/*! RxAutoSync + * 0b0..Rx FIFO auto sync off + * 0b1..RxFIFO auto sync on + */ +#define SPDIF_SCR_RXAUTOSYNC(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_RXAUTOSYNC_SHIFT)) & SPDIF_SCR_RXAUTOSYNC_MASK) +#define SPDIF_SCR_RXFIFOFULL_SEL_MASK (0x180000U) +#define SPDIF_SCR_RXFIFOFULL_SEL_SHIFT (19U) +/*! RxFIFOFull_Sel + * 0b00..Full interrupt if at least 1 sample in Rx left and right FIFOs + * 0b01..Full interrupt if at least 4 sample in Rx left and right FIFOs + * 0b10..Full interrupt if at least 8 sample in Rx left and right FIFOs + * 0b11..Full interrupt if at least 16 sample in Rx left and right FIFO + */ +#define SPDIF_SCR_RXFIFOFULL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_RXFIFOFULL_SEL_SHIFT)) & SPDIF_SCR_RXFIFOFULL_SEL_MASK) +#define SPDIF_SCR_RXFIFO_RST_MASK (0x200000U) +#define SPDIF_SCR_RXFIFO_RST_SHIFT (21U) +/*! RxFIFO_Rst + * 0b0..Normal operation + * 0b1..Reset register to 1 sample remaining + */ +#define SPDIF_SCR_RXFIFO_RST(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_RXFIFO_RST_SHIFT)) & SPDIF_SCR_RXFIFO_RST_MASK) +#define SPDIF_SCR_RXFIFO_OFF_ON_MASK (0x400000U) +#define SPDIF_SCR_RXFIFO_OFF_ON_SHIFT (22U) +/*! RxFIFO_Off_On + * 0b0..SPDIF Rx FIFO is on + * 0b1..SPDIF Rx FIFO is off. Does not accept data from interface + */ +#define SPDIF_SCR_RXFIFO_OFF_ON(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_RXFIFO_OFF_ON_SHIFT)) & SPDIF_SCR_RXFIFO_OFF_ON_MASK) +#define SPDIF_SCR_RXFIFO_CTRL_MASK (0x800000U) +#define SPDIF_SCR_RXFIFO_CTRL_SHIFT (23U) +/*! RxFIFO_Ctrl + * 0b0..Normal operation + * 0b1..Always read zero from Rx data register + */ +#define SPDIF_SCR_RXFIFO_CTRL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_RXFIFO_CTRL_SHIFT)) & SPDIF_SCR_RXFIFO_CTRL_MASK) +/*! @} */ + +/*! @name SRCD - CDText Control Register */ +/*! @{ */ +#define SPDIF_SRCD_USYNCMODE_MASK (0x2U) +#define SPDIF_SRCD_USYNCMODE_SHIFT (1U) +/*! USyncMode + * 0b0..Non-CD data + * 0b1..CD user channel subcode + */ +#define SPDIF_SRCD_USYNCMODE(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SRCD_USYNCMODE_SHIFT)) & SPDIF_SRCD_USYNCMODE_MASK) +/*! @} */ + +/*! @name SRPC - PhaseConfig Register */ +/*! @{ */ +#define SPDIF_SRPC_GAINSEL_MASK (0x38U) +#define SPDIF_SRPC_GAINSEL_SHIFT (3U) +/*! GainSel + * 0b000..24*(2**10) + * 0b001..16*(2**10) + * 0b010..12*(2**10) + * 0b011..8*(2**10) + * 0b100..6*(2**10) + * 0b101..4*(2**10) + * 0b110..3*(2**10) + */ +#define SPDIF_SRPC_GAINSEL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SRPC_GAINSEL_SHIFT)) & SPDIF_SRPC_GAINSEL_MASK) +#define SPDIF_SRPC_LOCK_MASK (0x40U) +#define SPDIF_SRPC_LOCK_SHIFT (6U) +#define SPDIF_SRPC_LOCK(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SRPC_LOCK_SHIFT)) & SPDIF_SRPC_LOCK_MASK) +#define SPDIF_SRPC_CLKSRC_SEL_MASK (0x780U) +#define SPDIF_SRPC_CLKSRC_SEL_SHIFT (7U) +/*! ClkSrc_Sel + * 0b0000..if (DPLL Locked) SPDIF_RxClk else REF_CLK_32K (XTALOSC) + * 0b0001..if (DPLL Locked) SPDIF_RxClk else tx_clk (SPDIF0_CLK_ROOT) + * 0b0011..if (DPLL Locked) SPDIF_RxClk else SPDIF_EXT_CLK + * 0b0101..REF_CLK_32K (XTALOSC) + * 0b0110..tx_clk (SPDIF0_CLK_ROOT) + * 0b1000..SPDIF_EXT_CLK + */ +#define SPDIF_SRPC_CLKSRC_SEL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SRPC_CLKSRC_SEL_SHIFT)) & SPDIF_SRPC_CLKSRC_SEL_MASK) +/*! @} */ + +/*! @name SIE - InterruptEn Register */ +/*! @{ */ +#define SPDIF_SIE_RXFIFOFUL_MASK (0x1U) +#define SPDIF_SIE_RXFIFOFUL_SHIFT (0U) +#define SPDIF_SIE_RXFIFOFUL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_RXFIFOFUL_SHIFT)) & SPDIF_SIE_RXFIFOFUL_MASK) +#define SPDIF_SIE_TXEM_MASK (0x2U) +#define SPDIF_SIE_TXEM_SHIFT (1U) +#define SPDIF_SIE_TXEM(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_TXEM_SHIFT)) & SPDIF_SIE_TXEM_MASK) +#define SPDIF_SIE_LOCKLOSS_MASK (0x4U) +#define SPDIF_SIE_LOCKLOSS_SHIFT (2U) +#define SPDIF_SIE_LOCKLOSS(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_LOCKLOSS_SHIFT)) & SPDIF_SIE_LOCKLOSS_MASK) +#define SPDIF_SIE_RXFIFORESYN_MASK (0x8U) +#define SPDIF_SIE_RXFIFORESYN_SHIFT (3U) +#define SPDIF_SIE_RXFIFORESYN(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_RXFIFORESYN_SHIFT)) & SPDIF_SIE_RXFIFORESYN_MASK) +#define SPDIF_SIE_RXFIFOUNOV_MASK (0x10U) +#define SPDIF_SIE_RXFIFOUNOV_SHIFT (4U) +#define SPDIF_SIE_RXFIFOUNOV(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_RXFIFOUNOV_SHIFT)) & SPDIF_SIE_RXFIFOUNOV_MASK) +#define SPDIF_SIE_UQERR_MASK (0x20U) +#define SPDIF_SIE_UQERR_SHIFT (5U) +#define SPDIF_SIE_UQERR(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_UQERR_SHIFT)) & SPDIF_SIE_UQERR_MASK) +#define SPDIF_SIE_UQSYNC_MASK (0x40U) +#define SPDIF_SIE_UQSYNC_SHIFT (6U) +#define SPDIF_SIE_UQSYNC(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_UQSYNC_SHIFT)) & SPDIF_SIE_UQSYNC_MASK) +#define SPDIF_SIE_QRXOV_MASK (0x80U) +#define SPDIF_SIE_QRXOV_SHIFT (7U) +#define SPDIF_SIE_QRXOV(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_QRXOV_SHIFT)) & SPDIF_SIE_QRXOV_MASK) +#define SPDIF_SIE_QRXFUL_MASK (0x100U) +#define SPDIF_SIE_QRXFUL_SHIFT (8U) +#define SPDIF_SIE_QRXFUL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_QRXFUL_SHIFT)) & SPDIF_SIE_QRXFUL_MASK) +#define SPDIF_SIE_URXOV_MASK (0x200U) +#define SPDIF_SIE_URXOV_SHIFT (9U) +#define SPDIF_SIE_URXOV(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_URXOV_SHIFT)) & SPDIF_SIE_URXOV_MASK) +#define SPDIF_SIE_URXFUL_MASK (0x400U) +#define SPDIF_SIE_URXFUL_SHIFT (10U) +#define SPDIF_SIE_URXFUL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_URXFUL_SHIFT)) & SPDIF_SIE_URXFUL_MASK) +#define SPDIF_SIE_BITERR_MASK (0x4000U) +#define SPDIF_SIE_BITERR_SHIFT (14U) +#define SPDIF_SIE_BITERR(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_BITERR_SHIFT)) & SPDIF_SIE_BITERR_MASK) +#define SPDIF_SIE_SYMERR_MASK (0x8000U) +#define SPDIF_SIE_SYMERR_SHIFT (15U) +#define SPDIF_SIE_SYMERR(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_SYMERR_SHIFT)) & SPDIF_SIE_SYMERR_MASK) +#define SPDIF_SIE_VALNOGOOD_MASK (0x10000U) +#define SPDIF_SIE_VALNOGOOD_SHIFT (16U) +#define SPDIF_SIE_VALNOGOOD(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_VALNOGOOD_SHIFT)) & SPDIF_SIE_VALNOGOOD_MASK) +#define SPDIF_SIE_CNEW_MASK (0x20000U) +#define SPDIF_SIE_CNEW_SHIFT (17U) +#define SPDIF_SIE_CNEW(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_CNEW_SHIFT)) & SPDIF_SIE_CNEW_MASK) +#define SPDIF_SIE_TXRESYN_MASK (0x40000U) +#define SPDIF_SIE_TXRESYN_SHIFT (18U) +#define SPDIF_SIE_TXRESYN(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_TXRESYN_SHIFT)) & SPDIF_SIE_TXRESYN_MASK) +#define SPDIF_SIE_TXUNOV_MASK (0x80000U) +#define SPDIF_SIE_TXUNOV_SHIFT (19U) +#define SPDIF_SIE_TXUNOV(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_TXUNOV_SHIFT)) & SPDIF_SIE_TXUNOV_MASK) +#define SPDIF_SIE_LOCK_MASK (0x100000U) +#define SPDIF_SIE_LOCK_SHIFT (20U) +#define SPDIF_SIE_LOCK(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_LOCK_SHIFT)) & SPDIF_SIE_LOCK_MASK) +/*! @} */ + +/*! @name SIC - InterruptClear Register */ +/*! @{ */ +#define SPDIF_SIC_LOCKLOSS_MASK (0x4U) +#define SPDIF_SIC_LOCKLOSS_SHIFT (2U) +#define SPDIF_SIC_LOCKLOSS(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_LOCKLOSS_SHIFT)) & SPDIF_SIC_LOCKLOSS_MASK) +#define SPDIF_SIC_RXFIFORESYN_MASK (0x8U) +#define SPDIF_SIC_RXFIFORESYN_SHIFT (3U) +#define SPDIF_SIC_RXFIFORESYN(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_RXFIFORESYN_SHIFT)) & SPDIF_SIC_RXFIFORESYN_MASK) +#define SPDIF_SIC_RXFIFOUNOV_MASK (0x10U) +#define SPDIF_SIC_RXFIFOUNOV_SHIFT (4U) +#define SPDIF_SIC_RXFIFOUNOV(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_RXFIFOUNOV_SHIFT)) & SPDIF_SIC_RXFIFOUNOV_MASK) +#define SPDIF_SIC_UQERR_MASK (0x20U) +#define SPDIF_SIC_UQERR_SHIFT (5U) +#define SPDIF_SIC_UQERR(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_UQERR_SHIFT)) & SPDIF_SIC_UQERR_MASK) +#define SPDIF_SIC_UQSYNC_MASK (0x40U) +#define SPDIF_SIC_UQSYNC_SHIFT (6U) +#define SPDIF_SIC_UQSYNC(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_UQSYNC_SHIFT)) & SPDIF_SIC_UQSYNC_MASK) +#define SPDIF_SIC_QRXOV_MASK (0x80U) +#define SPDIF_SIC_QRXOV_SHIFT (7U) +#define SPDIF_SIC_QRXOV(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_QRXOV_SHIFT)) & SPDIF_SIC_QRXOV_MASK) +#define SPDIF_SIC_URXOV_MASK (0x200U) +#define SPDIF_SIC_URXOV_SHIFT (9U) +#define SPDIF_SIC_URXOV(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_URXOV_SHIFT)) & SPDIF_SIC_URXOV_MASK) +#define SPDIF_SIC_BITERR_MASK (0x4000U) +#define SPDIF_SIC_BITERR_SHIFT (14U) +#define SPDIF_SIC_BITERR(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_BITERR_SHIFT)) & SPDIF_SIC_BITERR_MASK) +#define SPDIF_SIC_SYMERR_MASK (0x8000U) +#define SPDIF_SIC_SYMERR_SHIFT (15U) +#define SPDIF_SIC_SYMERR(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_SYMERR_SHIFT)) & SPDIF_SIC_SYMERR_MASK) +#define SPDIF_SIC_VALNOGOOD_MASK (0x10000U) +#define SPDIF_SIC_VALNOGOOD_SHIFT (16U) +#define SPDIF_SIC_VALNOGOOD(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_VALNOGOOD_SHIFT)) & SPDIF_SIC_VALNOGOOD_MASK) +#define SPDIF_SIC_CNEW_MASK (0x20000U) +#define SPDIF_SIC_CNEW_SHIFT (17U) +#define SPDIF_SIC_CNEW(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_CNEW_SHIFT)) & SPDIF_SIC_CNEW_MASK) +#define SPDIF_SIC_TXRESYN_MASK (0x40000U) +#define SPDIF_SIC_TXRESYN_SHIFT (18U) +#define SPDIF_SIC_TXRESYN(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_TXRESYN_SHIFT)) & SPDIF_SIC_TXRESYN_MASK) +#define SPDIF_SIC_TXUNOV_MASK (0x80000U) +#define SPDIF_SIC_TXUNOV_SHIFT (19U) +#define SPDIF_SIC_TXUNOV(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_TXUNOV_SHIFT)) & SPDIF_SIC_TXUNOV_MASK) +#define SPDIF_SIC_LOCK_MASK (0x100000U) +#define SPDIF_SIC_LOCK_SHIFT (20U) +#define SPDIF_SIC_LOCK(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_LOCK_SHIFT)) & SPDIF_SIC_LOCK_MASK) +/*! @} */ + +/*! @name SIS - InterruptStat Register */ +/*! @{ */ +#define SPDIF_SIS_RXFIFOFUL_MASK (0x1U) +#define SPDIF_SIS_RXFIFOFUL_SHIFT (0U) +#define SPDIF_SIS_RXFIFOFUL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_RXFIFOFUL_SHIFT)) & SPDIF_SIS_RXFIFOFUL_MASK) +#define SPDIF_SIS_TXEM_MASK (0x2U) +#define SPDIF_SIS_TXEM_SHIFT (1U) +#define SPDIF_SIS_TXEM(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_TXEM_SHIFT)) & SPDIF_SIS_TXEM_MASK) +#define SPDIF_SIS_LOCKLOSS_MASK (0x4U) +#define SPDIF_SIS_LOCKLOSS_SHIFT (2U) +#define SPDIF_SIS_LOCKLOSS(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_LOCKLOSS_SHIFT)) & SPDIF_SIS_LOCKLOSS_MASK) +#define SPDIF_SIS_RXFIFORESYN_MASK (0x8U) +#define SPDIF_SIS_RXFIFORESYN_SHIFT (3U) +#define SPDIF_SIS_RXFIFORESYN(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_RXFIFORESYN_SHIFT)) & SPDIF_SIS_RXFIFORESYN_MASK) +#define SPDIF_SIS_RXFIFOUNOV_MASK (0x10U) +#define SPDIF_SIS_RXFIFOUNOV_SHIFT (4U) +#define SPDIF_SIS_RXFIFOUNOV(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_RXFIFOUNOV_SHIFT)) & SPDIF_SIS_RXFIFOUNOV_MASK) +#define SPDIF_SIS_UQERR_MASK (0x20U) +#define SPDIF_SIS_UQERR_SHIFT (5U) +#define SPDIF_SIS_UQERR(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_UQERR_SHIFT)) & SPDIF_SIS_UQERR_MASK) +#define SPDIF_SIS_UQSYNC_MASK (0x40U) +#define SPDIF_SIS_UQSYNC_SHIFT (6U) +#define SPDIF_SIS_UQSYNC(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_UQSYNC_SHIFT)) & SPDIF_SIS_UQSYNC_MASK) +#define SPDIF_SIS_QRXOV_MASK (0x80U) +#define SPDIF_SIS_QRXOV_SHIFT (7U) +#define SPDIF_SIS_QRXOV(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_QRXOV_SHIFT)) & SPDIF_SIS_QRXOV_MASK) +#define SPDIF_SIS_QRXFUL_MASK (0x100U) +#define SPDIF_SIS_QRXFUL_SHIFT (8U) +#define SPDIF_SIS_QRXFUL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_QRXFUL_SHIFT)) & SPDIF_SIS_QRXFUL_MASK) +#define SPDIF_SIS_URXOV_MASK (0x200U) +#define SPDIF_SIS_URXOV_SHIFT (9U) +#define SPDIF_SIS_URXOV(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_URXOV_SHIFT)) & SPDIF_SIS_URXOV_MASK) +#define SPDIF_SIS_URXFUL_MASK (0x400U) +#define SPDIF_SIS_URXFUL_SHIFT (10U) +#define SPDIF_SIS_URXFUL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_URXFUL_SHIFT)) & SPDIF_SIS_URXFUL_MASK) +#define SPDIF_SIS_BITERR_MASK (0x4000U) +#define SPDIF_SIS_BITERR_SHIFT (14U) +#define SPDIF_SIS_BITERR(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_BITERR_SHIFT)) & SPDIF_SIS_BITERR_MASK) +#define SPDIF_SIS_SYMERR_MASK (0x8000U) +#define SPDIF_SIS_SYMERR_SHIFT (15U) +#define SPDIF_SIS_SYMERR(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_SYMERR_SHIFT)) & SPDIF_SIS_SYMERR_MASK) +#define SPDIF_SIS_VALNOGOOD_MASK (0x10000U) +#define SPDIF_SIS_VALNOGOOD_SHIFT (16U) +#define SPDIF_SIS_VALNOGOOD(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_VALNOGOOD_SHIFT)) & SPDIF_SIS_VALNOGOOD_MASK) +#define SPDIF_SIS_CNEW_MASK (0x20000U) +#define SPDIF_SIS_CNEW_SHIFT (17U) +#define SPDIF_SIS_CNEW(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_CNEW_SHIFT)) & SPDIF_SIS_CNEW_MASK) +#define SPDIF_SIS_TXRESYN_MASK (0x40000U) +#define SPDIF_SIS_TXRESYN_SHIFT (18U) +#define SPDIF_SIS_TXRESYN(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_TXRESYN_SHIFT)) & SPDIF_SIS_TXRESYN_MASK) +#define SPDIF_SIS_TXUNOV_MASK (0x80000U) +#define SPDIF_SIS_TXUNOV_SHIFT (19U) +#define SPDIF_SIS_TXUNOV(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_TXUNOV_SHIFT)) & SPDIF_SIS_TXUNOV_MASK) +#define SPDIF_SIS_LOCK_MASK (0x100000U) +#define SPDIF_SIS_LOCK_SHIFT (20U) +#define SPDIF_SIS_LOCK(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_LOCK_SHIFT)) & SPDIF_SIS_LOCK_MASK) +/*! @} */ + +/*! @name SRL - SPDIFRxLeft Register */ +/*! @{ */ +#define SPDIF_SRL_RXDATALEFT_MASK (0xFFFFFFU) +#define SPDIF_SRL_RXDATALEFT_SHIFT (0U) +#define SPDIF_SRL_RXDATALEFT(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SRL_RXDATALEFT_SHIFT)) & SPDIF_SRL_RXDATALEFT_MASK) +/*! @} */ + +/*! @name SRR - SPDIFRxRight Register */ +/*! @{ */ +#define SPDIF_SRR_RXDATARIGHT_MASK (0xFFFFFFU) +#define SPDIF_SRR_RXDATARIGHT_SHIFT (0U) +#define SPDIF_SRR_RXDATARIGHT(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SRR_RXDATARIGHT_SHIFT)) & SPDIF_SRR_RXDATARIGHT_MASK) +/*! @} */ + +/*! @name SRCSH - SPDIFRxCChannel_h Register */ +/*! @{ */ +#define SPDIF_SRCSH_RXCCHANNEL_H_MASK (0xFFFFFFU) +#define SPDIF_SRCSH_RXCCHANNEL_H_SHIFT (0U) +#define SPDIF_SRCSH_RXCCHANNEL_H(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SRCSH_RXCCHANNEL_H_SHIFT)) & SPDIF_SRCSH_RXCCHANNEL_H_MASK) +/*! @} */ + +/*! @name SRCSL - SPDIFRxCChannel_l Register */ +/*! @{ */ +#define SPDIF_SRCSL_RXCCHANNEL_L_MASK (0xFFFFFFU) +#define SPDIF_SRCSL_RXCCHANNEL_L_SHIFT (0U) +#define SPDIF_SRCSL_RXCCHANNEL_L(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SRCSL_RXCCHANNEL_L_SHIFT)) & SPDIF_SRCSL_RXCCHANNEL_L_MASK) +/*! @} */ + +/*! @name SRU - UchannelRx Register */ +/*! @{ */ +#define SPDIF_SRU_RXUCHANNEL_MASK (0xFFFFFFU) +#define SPDIF_SRU_RXUCHANNEL_SHIFT (0U) +#define SPDIF_SRU_RXUCHANNEL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SRU_RXUCHANNEL_SHIFT)) & SPDIF_SRU_RXUCHANNEL_MASK) +/*! @} */ + +/*! @name SRQ - QchannelRx Register */ +/*! @{ */ +#define SPDIF_SRQ_RXQCHANNEL_MASK (0xFFFFFFU) +#define SPDIF_SRQ_RXQCHANNEL_SHIFT (0U) +#define SPDIF_SRQ_RXQCHANNEL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SRQ_RXQCHANNEL_SHIFT)) & SPDIF_SRQ_RXQCHANNEL_MASK) +/*! @} */ + +/*! @name STL - SPDIFTxLeft Register */ +/*! @{ */ +#define SPDIF_STL_TXDATALEFT_MASK (0xFFFFFFU) +#define SPDIF_STL_TXDATALEFT_SHIFT (0U) +#define SPDIF_STL_TXDATALEFT(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_STL_TXDATALEFT_SHIFT)) & SPDIF_STL_TXDATALEFT_MASK) +/*! @} */ + +/*! @name STR - SPDIFTxRight Register */ +/*! @{ */ +#define SPDIF_STR_TXDATARIGHT_MASK (0xFFFFFFU) +#define SPDIF_STR_TXDATARIGHT_SHIFT (0U) +#define SPDIF_STR_TXDATARIGHT(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_STR_TXDATARIGHT_SHIFT)) & SPDIF_STR_TXDATARIGHT_MASK) +/*! @} */ + +/*! @name STCSCH - SPDIFTxCChannelCons_h Register */ +/*! @{ */ +#define SPDIF_STCSCH_TXCCHANNELCONS_H_MASK (0xFFFFFFU) +#define SPDIF_STCSCH_TXCCHANNELCONS_H_SHIFT (0U) +#define SPDIF_STCSCH_TXCCHANNELCONS_H(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_STCSCH_TXCCHANNELCONS_H_SHIFT)) & SPDIF_STCSCH_TXCCHANNELCONS_H_MASK) +/*! @} */ + +/*! @name STCSCL - SPDIFTxCChannelCons_l Register */ +/*! @{ */ +#define SPDIF_STCSCL_TXCCHANNELCONS_L_MASK (0xFFFFFFU) +#define SPDIF_STCSCL_TXCCHANNELCONS_L_SHIFT (0U) +#define SPDIF_STCSCL_TXCCHANNELCONS_L(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_STCSCL_TXCCHANNELCONS_L_SHIFT)) & SPDIF_STCSCL_TXCCHANNELCONS_L_MASK) +/*! @} */ + +/*! @name SRFM - FreqMeas Register */ +/*! @{ */ +#define SPDIF_SRFM_FREQMEAS_MASK (0xFFFFFFU) +#define SPDIF_SRFM_FREQMEAS_SHIFT (0U) +#define SPDIF_SRFM_FREQMEAS(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SRFM_FREQMEAS_SHIFT)) & SPDIF_SRFM_FREQMEAS_MASK) +/*! @} */ + +/*! @name STC - SPDIFTxClk Register */ +/*! @{ */ +#define SPDIF_STC_TXCLK_DF_MASK (0x7FU) +#define SPDIF_STC_TXCLK_DF_SHIFT (0U) +/*! TxClk_DF + * 0b0000000..divider factor is 1 + * 0b0000001..divider factor is 2 + * 0b1111111..divider factor is 128 + */ +#define SPDIF_STC_TXCLK_DF(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_STC_TXCLK_DF_SHIFT)) & SPDIF_STC_TXCLK_DF_MASK) +#define SPDIF_STC_TX_ALL_CLK_EN_MASK (0x80U) +#define SPDIF_STC_TX_ALL_CLK_EN_SHIFT (7U) +/*! tx_all_clk_en + * 0b0..disable transfer clock. + * 0b1..enable transfer clock. + */ +#define SPDIF_STC_TX_ALL_CLK_EN(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_STC_TX_ALL_CLK_EN_SHIFT)) & SPDIF_STC_TX_ALL_CLK_EN_MASK) +#define SPDIF_STC_TXCLK_SOURCE_MASK (0x700U) +#define SPDIF_STC_TXCLK_SOURCE_SHIFT (8U) +/*! TxClk_Source + * 0b000..REF_CLK_32K input (XTALOSC 32 kHz clock) + * 0b001..tx_clk input (from SPDIF0_CLK_ROOT. See CCM.) + * 0b011..SPDIF_EXT_CLK, from pads + * 0b101..ipg_clk input (frequency divided) + */ +#define SPDIF_STC_TXCLK_SOURCE(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_STC_TXCLK_SOURCE_SHIFT)) & SPDIF_STC_TXCLK_SOURCE_MASK) +#define SPDIF_STC_SYSCLK_DF_MASK (0xFF800U) +#define SPDIF_STC_SYSCLK_DF_SHIFT (11U) +/*! SYSCLK_DF + * 0b000000000..no clock signal + * 0b000000001..divider factor is 2 + * 0b111111111..divider factor is 512 + */ +#define SPDIF_STC_SYSCLK_DF(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_STC_SYSCLK_DF_SHIFT)) & SPDIF_STC_SYSCLK_DF_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group SPDIF_Register_Masks */ + + +/* SPDIF - Peripheral instance base addresses */ +/** Peripheral SPDIF base address */ +#define SPDIF_BASE (0x40380000u) +/** Peripheral SPDIF base pointer */ +#define SPDIF ((SPDIF_Type *)SPDIF_BASE) +/** Array initializer of SPDIF peripheral base addresses */ +#define SPDIF_BASE_ADDRS { SPDIF_BASE } +/** Array initializer of SPDIF peripheral base pointers */ +#define SPDIF_BASE_PTRS { SPDIF } +/** Interrupt vectors for the SPDIF peripheral type */ +#define SPDIF_IRQS { SPDIF_IRQn } + +/*! + * @} + */ /* end of group SPDIF_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- SRC Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup SRC_Peripheral_Access_Layer SRC Peripheral Access Layer + * @{ + */ + +/** SRC - Register Layout Typedef */ +typedef struct { + __IO uint32_t SCR; /**< SRC Control Register, offset: 0x0 */ + __I uint32_t SBMR1; /**< SRC Boot Mode Register 1, offset: 0x4 */ + __IO uint32_t SRSR; /**< SRC Reset Status Register, offset: 0x8 */ + uint8_t RESERVED_0[16]; + __I uint32_t SBMR2; /**< SRC Boot Mode Register 2, offset: 0x1C */ + __IO uint32_t GPR[10]; /**< SRC General Purpose Register 1..SRC General Purpose Register 10, array offset: 0x20, array step: 0x4 */ +} SRC_Type; + +/* ---------------------------------------------------------------------------- + -- SRC Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup SRC_Register_Masks SRC Register Masks + * @{ + */ + +/*! @name SCR - SRC Control Register */ +/*! @{ */ +#define SRC_SCR_MASK_WDOG_RST_MASK (0x780U) +#define SRC_SCR_MASK_WDOG_RST_SHIFT (7U) +/*! mask_wdog_rst + * 0b0101..wdog_rst_b is masked + * 0b1010..wdog_rst_b is not masked (default) + */ +#define SRC_SCR_MASK_WDOG_RST(x) (((uint32_t)(((uint32_t)(x)) << SRC_SCR_MASK_WDOG_RST_SHIFT)) & SRC_SCR_MASK_WDOG_RST_MASK) +#define SRC_SCR_CORE0_RST_MASK (0x2000U) +#define SRC_SCR_CORE0_RST_SHIFT (13U) +/*! core0_rst + * 0b0..do not assert core0 reset + * 0b1..assert core0 reset + */ +#define SRC_SCR_CORE0_RST(x) (((uint32_t)(((uint32_t)(x)) << SRC_SCR_CORE0_RST_SHIFT)) & SRC_SCR_CORE0_RST_MASK) +#define SRC_SCR_CORE0_DBG_RST_MASK (0x20000U) +#define SRC_SCR_CORE0_DBG_RST_SHIFT (17U) +/*! core0_dbg_rst + * 0b0..do not assert core0 debug reset + * 0b1..assert core0 debug reset + */ +#define SRC_SCR_CORE0_DBG_RST(x) (((uint32_t)(((uint32_t)(x)) << SRC_SCR_CORE0_DBG_RST_SHIFT)) & SRC_SCR_CORE0_DBG_RST_MASK) +#define SRC_SCR_DBG_RST_MSK_PG_MASK (0x2000000U) +#define SRC_SCR_DBG_RST_MSK_PG_SHIFT (25U) +/*! dbg_rst_msk_pg + * 0b0..do not mask core debug resets (debug resets will be asserted after power gating event) + * 0b1..mask core debug resets (debug resets won't be asserted after power gating event) + */ +#define SRC_SCR_DBG_RST_MSK_PG(x) (((uint32_t)(((uint32_t)(x)) << SRC_SCR_DBG_RST_MSK_PG_SHIFT)) & SRC_SCR_DBG_RST_MSK_PG_MASK) +#define SRC_SCR_MASK_WDOG3_RST_MASK (0xF0000000U) +#define SRC_SCR_MASK_WDOG3_RST_SHIFT (28U) +/*! mask_wdog3_rst + * 0b0101..wdog3_rst_b is masked + * 0b1010..wdog3_rst_b is not masked + */ +#define SRC_SCR_MASK_WDOG3_RST(x) (((uint32_t)(((uint32_t)(x)) << SRC_SCR_MASK_WDOG3_RST_SHIFT)) & SRC_SCR_MASK_WDOG3_RST_MASK) +/*! @} */ + +/*! @name SBMR1 - SRC Boot Mode Register 1 */ +/*! @{ */ +#define SRC_SBMR1_BOOT_CFG1_MASK (0xFFU) +#define SRC_SBMR1_BOOT_CFG1_SHIFT (0U) +#define SRC_SBMR1_BOOT_CFG1(x) (((uint32_t)(((uint32_t)(x)) << SRC_SBMR1_BOOT_CFG1_SHIFT)) & SRC_SBMR1_BOOT_CFG1_MASK) +#define SRC_SBMR1_BOOT_CFG2_MASK (0xFF00U) +#define SRC_SBMR1_BOOT_CFG2_SHIFT (8U) +#define SRC_SBMR1_BOOT_CFG2(x) (((uint32_t)(((uint32_t)(x)) << SRC_SBMR1_BOOT_CFG2_SHIFT)) & SRC_SBMR1_BOOT_CFG2_MASK) +#define SRC_SBMR1_BOOT_CFG3_MASK (0xFF0000U) +#define SRC_SBMR1_BOOT_CFG3_SHIFT (16U) +#define SRC_SBMR1_BOOT_CFG3(x) (((uint32_t)(((uint32_t)(x)) << SRC_SBMR1_BOOT_CFG3_SHIFT)) & SRC_SBMR1_BOOT_CFG3_MASK) +#define SRC_SBMR1_BOOT_CFG4_MASK (0xFF000000U) +#define SRC_SBMR1_BOOT_CFG4_SHIFT (24U) +#define SRC_SBMR1_BOOT_CFG4(x) (((uint32_t)(((uint32_t)(x)) << SRC_SBMR1_BOOT_CFG4_SHIFT)) & SRC_SBMR1_BOOT_CFG4_MASK) +/*! @} */ + +/*! @name SRSR - SRC Reset Status Register */ +/*! @{ */ +#define SRC_SRSR_IPP_RESET_B_MASK (0x1U) +#define SRC_SRSR_IPP_RESET_B_SHIFT (0U) +/*! ipp_reset_b + * 0b0..Reset is not a result of ipp_reset_b pin. + * 0b1..Reset is a result of ipp_reset_b pin. + */ +#define SRC_SRSR_IPP_RESET_B(x) (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_IPP_RESET_B_SHIFT)) & SRC_SRSR_IPP_RESET_B_MASK) +#define SRC_SRSR_LOCKUP_SYSRESETREQ_MASK (0x2U) +#define SRC_SRSR_LOCKUP_SYSRESETREQ_SHIFT (1U) +/*! lockup_sysresetreq + * 0b0..Reset is not a result of the mentioned case. + * 0b1..Reset is a result of the mentioned case. + */ +#define SRC_SRSR_LOCKUP_SYSRESETREQ(x) (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_LOCKUP_SYSRESETREQ_SHIFT)) & SRC_SRSR_LOCKUP_SYSRESETREQ_MASK) +#define SRC_SRSR_CSU_RESET_B_MASK (0x4U) +#define SRC_SRSR_CSU_RESET_B_SHIFT (2U) +/*! csu_reset_b + * 0b0..Reset is not a result of the csu_reset_b event. + * 0b1..Reset is a result of the csu_reset_b event. + */ +#define SRC_SRSR_CSU_RESET_B(x) (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_CSU_RESET_B_SHIFT)) & SRC_SRSR_CSU_RESET_B_MASK) +#define SRC_SRSR_IPP_USER_RESET_B_MASK (0x8U) +#define SRC_SRSR_IPP_USER_RESET_B_SHIFT (3U) +/*! ipp_user_reset_b + * 0b0..Reset is not a result of the ipp_user_reset_b qualified as COLD reset event. + * 0b1..Reset is a result of the ipp_user_reset_b qualified as COLD reset event. + */ +#define SRC_SRSR_IPP_USER_RESET_B(x) (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_IPP_USER_RESET_B_SHIFT)) & SRC_SRSR_IPP_USER_RESET_B_MASK) +#define SRC_SRSR_WDOG_RST_B_MASK (0x10U) +#define SRC_SRSR_WDOG_RST_B_SHIFT (4U) +/*! wdog_rst_b + * 0b0..Reset is not a result of the watchdog time-out event. + * 0b1..Reset is a result of the watchdog time-out event. + */ +#define SRC_SRSR_WDOG_RST_B(x) (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_WDOG_RST_B_SHIFT)) & SRC_SRSR_WDOG_RST_B_MASK) +#define SRC_SRSR_JTAG_RST_B_MASK (0x20U) +#define SRC_SRSR_JTAG_RST_B_SHIFT (5U) +/*! jtag_rst_b + * 0b0..Reset is not a result of HIGH-Z reset from JTAG. + * 0b1..Reset is a result of HIGH-Z reset from JTAG. + */ +#define SRC_SRSR_JTAG_RST_B(x) (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_JTAG_RST_B_SHIFT)) & SRC_SRSR_JTAG_RST_B_MASK) +#define SRC_SRSR_JTAG_SW_RST_MASK (0x40U) +#define SRC_SRSR_JTAG_SW_RST_SHIFT (6U) +/*! jtag_sw_rst + * 0b0..Reset is not a result of software reset from JTAG. + * 0b1..Reset is a result of software reset from JTAG. + */ +#define SRC_SRSR_JTAG_SW_RST(x) (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_JTAG_SW_RST_SHIFT)) & SRC_SRSR_JTAG_SW_RST_MASK) +#define SRC_SRSR_WDOG3_RST_B_MASK (0x80U) +#define SRC_SRSR_WDOG3_RST_B_SHIFT (7U) +/*! wdog3_rst_b + * 0b0..Reset is not a result of the watchdog3 time-out event. + * 0b1..Reset is a result of the watchdog3 time-out event. + */ +#define SRC_SRSR_WDOG3_RST_B(x) (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_WDOG3_RST_B_SHIFT)) & SRC_SRSR_WDOG3_RST_B_MASK) +#define SRC_SRSR_TEMPSENSE_RST_B_MASK (0x100U) +#define SRC_SRSR_TEMPSENSE_RST_B_SHIFT (8U) +/*! tempsense_rst_b + * 0b0..Reset is not a result of software reset from Temperature Sensor. + * 0b1..Reset is a result of software reset from Temperature Sensor. + */ +#define SRC_SRSR_TEMPSENSE_RST_B(x) (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_TEMPSENSE_RST_B_SHIFT)) & SRC_SRSR_TEMPSENSE_RST_B_MASK) +/*! @} */ + +/*! @name SBMR2 - SRC Boot Mode Register 2 */ +/*! @{ */ +#define SRC_SBMR2_SEC_CONFIG_MASK (0x3U) +#define SRC_SBMR2_SEC_CONFIG_SHIFT (0U) +#define SRC_SBMR2_SEC_CONFIG(x) (((uint32_t)(((uint32_t)(x)) << SRC_SBMR2_SEC_CONFIG_SHIFT)) & SRC_SBMR2_SEC_CONFIG_MASK) +#define SRC_SBMR2_DIR_BT_DIS_MASK (0x8U) +#define SRC_SBMR2_DIR_BT_DIS_SHIFT (3U) +#define SRC_SBMR2_DIR_BT_DIS(x) (((uint32_t)(((uint32_t)(x)) << SRC_SBMR2_DIR_BT_DIS_SHIFT)) & SRC_SBMR2_DIR_BT_DIS_MASK) +#define SRC_SBMR2_BT_FUSE_SEL_MASK (0x10U) +#define SRC_SBMR2_BT_FUSE_SEL_SHIFT (4U) +#define SRC_SBMR2_BT_FUSE_SEL(x) (((uint32_t)(((uint32_t)(x)) << SRC_SBMR2_BT_FUSE_SEL_SHIFT)) & SRC_SBMR2_BT_FUSE_SEL_MASK) +#define SRC_SBMR2_BMOD_MASK (0x3000000U) +#define SRC_SBMR2_BMOD_SHIFT (24U) +#define SRC_SBMR2_BMOD(x) (((uint32_t)(((uint32_t)(x)) << SRC_SBMR2_BMOD_SHIFT)) & SRC_SBMR2_BMOD_MASK) +/*! @} */ + +/*! @name GPR - SRC General Purpose Register 1..SRC General Purpose Register 10 */ +/*! @{ */ +#define SRC_GPR_PERSISTENT_ARG0_MASK (0xFFFFFFFFU) +#define SRC_GPR_PERSISTENT_ARG0_SHIFT (0U) +#define SRC_GPR_PERSISTENT_ARG0(x) (((uint32_t)(((uint32_t)(x)) << SRC_GPR_PERSISTENT_ARG0_SHIFT)) & SRC_GPR_PERSISTENT_ARG0_MASK) +#define SRC_GPR_PERSISTENT_ENTRY0_MASK (0xFFFFFFFFU) +#define SRC_GPR_PERSISTENT_ENTRY0_SHIFT (0U) +#define SRC_GPR_PERSISTENT_ENTRY0(x) (((uint32_t)(((uint32_t)(x)) << SRC_GPR_PERSISTENT_ENTRY0_SHIFT)) & SRC_GPR_PERSISTENT_ENTRY0_MASK) +/*! @} */ + +/* The count of SRC_GPR */ +#define SRC_GPR_COUNT (10U) + + +/*! + * @} + */ /* end of group SRC_Register_Masks */ + + +/* SRC - Peripheral instance base addresses */ +/** Peripheral SRC base address */ +#define SRC_BASE (0x400F8000u) +/** Peripheral SRC base pointer */ +#define SRC ((SRC_Type *)SRC_BASE) +/** Array initializer of SRC peripheral base addresses */ +#define SRC_BASE_ADDRS { SRC_BASE } +/** Array initializer of SRC peripheral base pointers */ +#define SRC_BASE_PTRS { SRC } +/** Interrupt vectors for the SRC peripheral type */ +#define SRC_IRQS { SRC_IRQn } +/* Backward compatibility */ +#define SRC_SCR_MWDR_MASK SRC_SCR_MASK_WDOG_RST_MASK +#define SRC_SCR_MWDR_SHIFT SRC_SCR_MASK_WDOG_RST_SHIFT +#define SRC_SCR_MWDR(x) SRC_SCR_MASK_WDOG_RST(x) +#define SRC_SRSR_WDOG_MASK SRC_SRSR_WDOG_RST_B_MASK +#define SRC_SRSR_WDOG_SHIFT SRC_SRSR_WDOG_RST_B_SHIFT +#define SRC_SRSR_WDOG(x) SRC_SRSR_WDOG_RST_B(x) +#define SRC_SRSR_JTAG_MASK SRC_SRSR_JTAG_RST_B_MASK +#define SRC_SRSR_JTAG_SHIFT SRC_SRSR_JTAG_RST_B_SHIFT +#define SRC_SRSR_JTAG(x) SRC_SRSR_JTAG_RST_B(x) +#define SRC_SRSR_SJC_MASK SRC_SRSR_JTAG_SW_RST_MASK +#define SRC_SRSR_SJC_SHIFT SRC_SRSR_JTAG_SW_RST_SHIFT +#define SRC_SRSR_SJC(x) SRC_SRSR_JTAG_SW_RST(x) +#define SRC_SRSR_TSR_MASK SRC_SRSR_TEMPSENSE_RST_B_MASK +#define SRC_SRSR_TSR_SHIFT SRC_SRSR_TEMPSENSE_RST_B_SHIFT +#define SRC_SRSR_TSR(x) SRC_SRSR_TEMPSENSE_RST_B(x) +/* Extra definition */ +#define SRC_SRSR_W1C_BITS_MASK ( SRC_SRSR_WDOG3_RST_B_MASK \ + | SRC_SRSR_JTAG_SW_RST_MASK \ + | SRC_SRSR_JTAG_RST_B_MASK \ + | SRC_SRSR_WDOG_RST_B_MASK \ + | SRC_SRSR_IPP_USER_RESET_B_MASK \ + | SRC_SRSR_CSU_RESET_B_MASK \ + | SRC_SRSR_LOCKUP_SYSRESETREQ_MASK \ + | SRC_SRSR_IPP_RESET_B_MASK) + + +/*! + * @} + */ /* end of group SRC_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- TEMPMON Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup TEMPMON_Peripheral_Access_Layer TEMPMON Peripheral Access Layer + * @{ + */ + +/** TEMPMON - Register Layout Typedef */ +typedef struct { + uint8_t RESERVED_0[384]; + __IO uint32_t TEMPSENSE0; /**< Tempsensor Control Register 0, offset: 0x180 */ + __IO uint32_t TEMPSENSE0_SET; /**< Tempsensor Control Register 0, offset: 0x184 */ + __IO uint32_t TEMPSENSE0_CLR; /**< Tempsensor Control Register 0, offset: 0x188 */ + __IO uint32_t TEMPSENSE0_TOG; /**< Tempsensor Control Register 0, offset: 0x18C */ + __IO uint32_t TEMPSENSE1; /**< Tempsensor Control Register 1, offset: 0x190 */ + __IO uint32_t TEMPSENSE1_SET; /**< Tempsensor Control Register 1, offset: 0x194 */ + __IO uint32_t TEMPSENSE1_CLR; /**< Tempsensor Control Register 1, offset: 0x198 */ + __IO uint32_t TEMPSENSE1_TOG; /**< Tempsensor Control Register 1, offset: 0x19C */ + uint8_t RESERVED_1[240]; + __IO uint32_t TEMPSENSE2; /**< Tempsensor Control Register 2, offset: 0x290 */ + __IO uint32_t TEMPSENSE2_SET; /**< Tempsensor Control Register 2, offset: 0x294 */ + __IO uint32_t TEMPSENSE2_CLR; /**< Tempsensor Control Register 2, offset: 0x298 */ + __IO uint32_t TEMPSENSE2_TOG; /**< Tempsensor Control Register 2, offset: 0x29C */ +} TEMPMON_Type; + +/* ---------------------------------------------------------------------------- + -- TEMPMON Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup TEMPMON_Register_Masks TEMPMON Register Masks + * @{ + */ + +/*! @name TEMPSENSE0 - Tempsensor Control Register 0 */ +/*! @{ */ +#define TEMPMON_TEMPSENSE0_POWER_DOWN_MASK (0x1U) +#define TEMPMON_TEMPSENSE0_POWER_DOWN_SHIFT (0U) +/*! POWER_DOWN + * 0b0..Enable power to the temperature sensor. + * 0b1..Power down the temperature sensor. + */ +#define TEMPMON_TEMPSENSE0_POWER_DOWN(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_POWER_DOWN_SHIFT)) & TEMPMON_TEMPSENSE0_POWER_DOWN_MASK) +#define TEMPMON_TEMPSENSE0_MEASURE_TEMP_MASK (0x2U) +#define TEMPMON_TEMPSENSE0_MEASURE_TEMP_SHIFT (1U) +/*! MEASURE_TEMP + * 0b0..Do not start the measurement process. + * 0b1..Start the measurement process. + */ +#define TEMPMON_TEMPSENSE0_MEASURE_TEMP(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_MEASURE_TEMP_SHIFT)) & TEMPMON_TEMPSENSE0_MEASURE_TEMP_MASK) +#define TEMPMON_TEMPSENSE0_FINISHED_MASK (0x4U) +#define TEMPMON_TEMPSENSE0_FINISHED_SHIFT (2U) +/*! FINISHED + * 0b0..Last measurement is not ready yet. + * 0b1..Last measurement is valid. + */ +#define TEMPMON_TEMPSENSE0_FINISHED(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_FINISHED_SHIFT)) & TEMPMON_TEMPSENSE0_FINISHED_MASK) +#define TEMPMON_TEMPSENSE0_TEMP_CNT_MASK (0xFFF00U) +#define TEMPMON_TEMPSENSE0_TEMP_CNT_SHIFT (8U) +#define TEMPMON_TEMPSENSE0_TEMP_CNT(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_TEMP_CNT_SHIFT)) & TEMPMON_TEMPSENSE0_TEMP_CNT_MASK) +#define TEMPMON_TEMPSENSE0_ALARM_VALUE_MASK (0xFFF00000U) +#define TEMPMON_TEMPSENSE0_ALARM_VALUE_SHIFT (20U) +#define TEMPMON_TEMPSENSE0_ALARM_VALUE(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_ALARM_VALUE_SHIFT)) & TEMPMON_TEMPSENSE0_ALARM_VALUE_MASK) +/*! @} */ + +/*! @name TEMPSENSE0_SET - Tempsensor Control Register 0 */ +/*! @{ */ +#define TEMPMON_TEMPSENSE0_SET_POWER_DOWN_MASK (0x1U) +#define TEMPMON_TEMPSENSE0_SET_POWER_DOWN_SHIFT (0U) +/*! POWER_DOWN + * 0b0..Enable power to the temperature sensor. + * 0b1..Power down the temperature sensor. + */ +#define TEMPMON_TEMPSENSE0_SET_POWER_DOWN(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_SET_POWER_DOWN_SHIFT)) & TEMPMON_TEMPSENSE0_SET_POWER_DOWN_MASK) +#define TEMPMON_TEMPSENSE0_SET_MEASURE_TEMP_MASK (0x2U) +#define TEMPMON_TEMPSENSE0_SET_MEASURE_TEMP_SHIFT (1U) +/*! MEASURE_TEMP + * 0b0..Do not start the measurement process. + * 0b1..Start the measurement process. + */ +#define TEMPMON_TEMPSENSE0_SET_MEASURE_TEMP(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_SET_MEASURE_TEMP_SHIFT)) & TEMPMON_TEMPSENSE0_SET_MEASURE_TEMP_MASK) +#define TEMPMON_TEMPSENSE0_SET_FINISHED_MASK (0x4U) +#define TEMPMON_TEMPSENSE0_SET_FINISHED_SHIFT (2U) +/*! FINISHED + * 0b0..Last measurement is not ready yet. + * 0b1..Last measurement is valid. + */ +#define TEMPMON_TEMPSENSE0_SET_FINISHED(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_SET_FINISHED_SHIFT)) & TEMPMON_TEMPSENSE0_SET_FINISHED_MASK) +#define TEMPMON_TEMPSENSE0_SET_TEMP_CNT_MASK (0xFFF00U) +#define TEMPMON_TEMPSENSE0_SET_TEMP_CNT_SHIFT (8U) +#define TEMPMON_TEMPSENSE0_SET_TEMP_CNT(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_SET_TEMP_CNT_SHIFT)) & TEMPMON_TEMPSENSE0_SET_TEMP_CNT_MASK) +#define TEMPMON_TEMPSENSE0_SET_ALARM_VALUE_MASK (0xFFF00000U) +#define TEMPMON_TEMPSENSE0_SET_ALARM_VALUE_SHIFT (20U) +#define TEMPMON_TEMPSENSE0_SET_ALARM_VALUE(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_SET_ALARM_VALUE_SHIFT)) & TEMPMON_TEMPSENSE0_SET_ALARM_VALUE_MASK) +/*! @} */ + +/*! @name TEMPSENSE0_CLR - Tempsensor Control Register 0 */ +/*! @{ */ +#define TEMPMON_TEMPSENSE0_CLR_POWER_DOWN_MASK (0x1U) +#define TEMPMON_TEMPSENSE0_CLR_POWER_DOWN_SHIFT (0U) +/*! POWER_DOWN + * 0b0..Enable power to the temperature sensor. + * 0b1..Power down the temperature sensor. + */ +#define TEMPMON_TEMPSENSE0_CLR_POWER_DOWN(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_CLR_POWER_DOWN_SHIFT)) & TEMPMON_TEMPSENSE0_CLR_POWER_DOWN_MASK) +#define TEMPMON_TEMPSENSE0_CLR_MEASURE_TEMP_MASK (0x2U) +#define TEMPMON_TEMPSENSE0_CLR_MEASURE_TEMP_SHIFT (1U) +/*! MEASURE_TEMP + * 0b0..Do not start the measurement process. + * 0b1..Start the measurement process. + */ +#define TEMPMON_TEMPSENSE0_CLR_MEASURE_TEMP(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_CLR_MEASURE_TEMP_SHIFT)) & TEMPMON_TEMPSENSE0_CLR_MEASURE_TEMP_MASK) +#define TEMPMON_TEMPSENSE0_CLR_FINISHED_MASK (0x4U) +#define TEMPMON_TEMPSENSE0_CLR_FINISHED_SHIFT (2U) +/*! FINISHED + * 0b0..Last measurement is not ready yet. + * 0b1..Last measurement is valid. + */ +#define TEMPMON_TEMPSENSE0_CLR_FINISHED(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_CLR_FINISHED_SHIFT)) & TEMPMON_TEMPSENSE0_CLR_FINISHED_MASK) +#define TEMPMON_TEMPSENSE0_CLR_TEMP_CNT_MASK (0xFFF00U) +#define TEMPMON_TEMPSENSE0_CLR_TEMP_CNT_SHIFT (8U) +#define TEMPMON_TEMPSENSE0_CLR_TEMP_CNT(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_CLR_TEMP_CNT_SHIFT)) & TEMPMON_TEMPSENSE0_CLR_TEMP_CNT_MASK) +#define TEMPMON_TEMPSENSE0_CLR_ALARM_VALUE_MASK (0xFFF00000U) +#define TEMPMON_TEMPSENSE0_CLR_ALARM_VALUE_SHIFT (20U) +#define TEMPMON_TEMPSENSE0_CLR_ALARM_VALUE(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_CLR_ALARM_VALUE_SHIFT)) & TEMPMON_TEMPSENSE0_CLR_ALARM_VALUE_MASK) +/*! @} */ + +/*! @name TEMPSENSE0_TOG - Tempsensor Control Register 0 */ +/*! @{ */ +#define TEMPMON_TEMPSENSE0_TOG_POWER_DOWN_MASK (0x1U) +#define TEMPMON_TEMPSENSE0_TOG_POWER_DOWN_SHIFT (0U) +/*! POWER_DOWN + * 0b0..Enable power to the temperature sensor. + * 0b1..Power down the temperature sensor. + */ +#define TEMPMON_TEMPSENSE0_TOG_POWER_DOWN(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_TOG_POWER_DOWN_SHIFT)) & TEMPMON_TEMPSENSE0_TOG_POWER_DOWN_MASK) +#define TEMPMON_TEMPSENSE0_TOG_MEASURE_TEMP_MASK (0x2U) +#define TEMPMON_TEMPSENSE0_TOG_MEASURE_TEMP_SHIFT (1U) +/*! MEASURE_TEMP + * 0b0..Do not start the measurement process. + * 0b1..Start the measurement process. + */ +#define TEMPMON_TEMPSENSE0_TOG_MEASURE_TEMP(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_TOG_MEASURE_TEMP_SHIFT)) & TEMPMON_TEMPSENSE0_TOG_MEASURE_TEMP_MASK) +#define TEMPMON_TEMPSENSE0_TOG_FINISHED_MASK (0x4U) +#define TEMPMON_TEMPSENSE0_TOG_FINISHED_SHIFT (2U) +/*! FINISHED + * 0b0..Last measurement is not ready yet. + * 0b1..Last measurement is valid. + */ +#define TEMPMON_TEMPSENSE0_TOG_FINISHED(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_TOG_FINISHED_SHIFT)) & TEMPMON_TEMPSENSE0_TOG_FINISHED_MASK) +#define TEMPMON_TEMPSENSE0_TOG_TEMP_CNT_MASK (0xFFF00U) +#define TEMPMON_TEMPSENSE0_TOG_TEMP_CNT_SHIFT (8U) +#define TEMPMON_TEMPSENSE0_TOG_TEMP_CNT(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_TOG_TEMP_CNT_SHIFT)) & TEMPMON_TEMPSENSE0_TOG_TEMP_CNT_MASK) +#define TEMPMON_TEMPSENSE0_TOG_ALARM_VALUE_MASK (0xFFF00000U) +#define TEMPMON_TEMPSENSE0_TOG_ALARM_VALUE_SHIFT (20U) +#define TEMPMON_TEMPSENSE0_TOG_ALARM_VALUE(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_TOG_ALARM_VALUE_SHIFT)) & TEMPMON_TEMPSENSE0_TOG_ALARM_VALUE_MASK) +/*! @} */ + +/*! @name TEMPSENSE1 - Tempsensor Control Register 1 */ +/*! @{ */ +#define TEMPMON_TEMPSENSE1_MEASURE_FREQ_MASK (0xFFFFU) +#define TEMPMON_TEMPSENSE1_MEASURE_FREQ_SHIFT (0U) +#define TEMPMON_TEMPSENSE1_MEASURE_FREQ(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE1_MEASURE_FREQ_SHIFT)) & TEMPMON_TEMPSENSE1_MEASURE_FREQ_MASK) +/*! @} */ + +/*! @name TEMPSENSE1_SET - Tempsensor Control Register 1 */ +/*! @{ */ +#define TEMPMON_TEMPSENSE1_SET_MEASURE_FREQ_MASK (0xFFFFU) +#define TEMPMON_TEMPSENSE1_SET_MEASURE_FREQ_SHIFT (0U) +#define TEMPMON_TEMPSENSE1_SET_MEASURE_FREQ(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE1_SET_MEASURE_FREQ_SHIFT)) & TEMPMON_TEMPSENSE1_SET_MEASURE_FREQ_MASK) +/*! @} */ + +/*! @name TEMPSENSE1_CLR - Tempsensor Control Register 1 */ +/*! @{ */ +#define TEMPMON_TEMPSENSE1_CLR_MEASURE_FREQ_MASK (0xFFFFU) +#define TEMPMON_TEMPSENSE1_CLR_MEASURE_FREQ_SHIFT (0U) +#define TEMPMON_TEMPSENSE1_CLR_MEASURE_FREQ(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE1_CLR_MEASURE_FREQ_SHIFT)) & TEMPMON_TEMPSENSE1_CLR_MEASURE_FREQ_MASK) +/*! @} */ + +/*! @name TEMPSENSE1_TOG - Tempsensor Control Register 1 */ +/*! @{ */ +#define TEMPMON_TEMPSENSE1_TOG_MEASURE_FREQ_MASK (0xFFFFU) +#define TEMPMON_TEMPSENSE1_TOG_MEASURE_FREQ_SHIFT (0U) +#define TEMPMON_TEMPSENSE1_TOG_MEASURE_FREQ(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE1_TOG_MEASURE_FREQ_SHIFT)) & TEMPMON_TEMPSENSE1_TOG_MEASURE_FREQ_MASK) +/*! @} */ + +/*! @name TEMPSENSE2 - Tempsensor Control Register 2 */ +/*! @{ */ +#define TEMPMON_TEMPSENSE2_LOW_ALARM_VALUE_MASK (0xFFFU) +#define TEMPMON_TEMPSENSE2_LOW_ALARM_VALUE_SHIFT (0U) +#define TEMPMON_TEMPSENSE2_LOW_ALARM_VALUE(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE2_LOW_ALARM_VALUE_SHIFT)) & TEMPMON_TEMPSENSE2_LOW_ALARM_VALUE_MASK) +#define TEMPMON_TEMPSENSE2_PANIC_ALARM_VALUE_MASK (0xFFF0000U) +#define TEMPMON_TEMPSENSE2_PANIC_ALARM_VALUE_SHIFT (16U) +#define TEMPMON_TEMPSENSE2_PANIC_ALARM_VALUE(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE2_PANIC_ALARM_VALUE_SHIFT)) & TEMPMON_TEMPSENSE2_PANIC_ALARM_VALUE_MASK) +/*! @} */ + +/*! @name TEMPSENSE2_SET - Tempsensor Control Register 2 */ +/*! @{ */ +#define TEMPMON_TEMPSENSE2_SET_LOW_ALARM_VALUE_MASK (0xFFFU) +#define TEMPMON_TEMPSENSE2_SET_LOW_ALARM_VALUE_SHIFT (0U) +#define TEMPMON_TEMPSENSE2_SET_LOW_ALARM_VALUE(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE2_SET_LOW_ALARM_VALUE_SHIFT)) & TEMPMON_TEMPSENSE2_SET_LOW_ALARM_VALUE_MASK) +#define TEMPMON_TEMPSENSE2_SET_PANIC_ALARM_VALUE_MASK (0xFFF0000U) +#define TEMPMON_TEMPSENSE2_SET_PANIC_ALARM_VALUE_SHIFT (16U) +#define TEMPMON_TEMPSENSE2_SET_PANIC_ALARM_VALUE(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE2_SET_PANIC_ALARM_VALUE_SHIFT)) & TEMPMON_TEMPSENSE2_SET_PANIC_ALARM_VALUE_MASK) +/*! @} */ + +/*! @name TEMPSENSE2_CLR - Tempsensor Control Register 2 */ +/*! @{ */ +#define TEMPMON_TEMPSENSE2_CLR_LOW_ALARM_VALUE_MASK (0xFFFU) +#define TEMPMON_TEMPSENSE2_CLR_LOW_ALARM_VALUE_SHIFT (0U) +#define TEMPMON_TEMPSENSE2_CLR_LOW_ALARM_VALUE(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE2_CLR_LOW_ALARM_VALUE_SHIFT)) & TEMPMON_TEMPSENSE2_CLR_LOW_ALARM_VALUE_MASK) +#define TEMPMON_TEMPSENSE2_CLR_PANIC_ALARM_VALUE_MASK (0xFFF0000U) +#define TEMPMON_TEMPSENSE2_CLR_PANIC_ALARM_VALUE_SHIFT (16U) +#define TEMPMON_TEMPSENSE2_CLR_PANIC_ALARM_VALUE(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE2_CLR_PANIC_ALARM_VALUE_SHIFT)) & TEMPMON_TEMPSENSE2_CLR_PANIC_ALARM_VALUE_MASK) +/*! @} */ + +/*! @name TEMPSENSE2_TOG - Tempsensor Control Register 2 */ +/*! @{ */ +#define TEMPMON_TEMPSENSE2_TOG_LOW_ALARM_VALUE_MASK (0xFFFU) +#define TEMPMON_TEMPSENSE2_TOG_LOW_ALARM_VALUE_SHIFT (0U) +#define TEMPMON_TEMPSENSE2_TOG_LOW_ALARM_VALUE(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE2_TOG_LOW_ALARM_VALUE_SHIFT)) & TEMPMON_TEMPSENSE2_TOG_LOW_ALARM_VALUE_MASK) +#define TEMPMON_TEMPSENSE2_TOG_PANIC_ALARM_VALUE_MASK (0xFFF0000U) +#define TEMPMON_TEMPSENSE2_TOG_PANIC_ALARM_VALUE_SHIFT (16U) +#define TEMPMON_TEMPSENSE2_TOG_PANIC_ALARM_VALUE(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE2_TOG_PANIC_ALARM_VALUE_SHIFT)) & TEMPMON_TEMPSENSE2_TOG_PANIC_ALARM_VALUE_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group TEMPMON_Register_Masks */ + + +/* TEMPMON - Peripheral instance base addresses */ +/** Peripheral TEMPMON base address */ +#define TEMPMON_BASE (0x400D8000u) +/** Peripheral TEMPMON base pointer */ +#define TEMPMON ((TEMPMON_Type *)TEMPMON_BASE) +/** Array initializer of TEMPMON peripheral base addresses */ +#define TEMPMON_BASE_ADDRS { TEMPMON_BASE } +/** Array initializer of TEMPMON peripheral base pointers */ +#define TEMPMON_BASE_PTRS { TEMPMON } + +/*! + * @} + */ /* end of group TEMPMON_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- TMR Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup TMR_Peripheral_Access_Layer TMR Peripheral Access Layer + * @{ + */ + +/** TMR - Register Layout Typedef */ +typedef struct { + struct { /* offset: 0x0, array step: 0x20 */ + __IO uint16_t COMP1; /**< Timer Channel Compare Register 1, array offset: 0x0, array step: 0x20 */ + __IO uint16_t COMP2; /**< Timer Channel Compare Register 2, array offset: 0x2, array step: 0x20 */ + __IO uint16_t CAPT; /**< Timer Channel Capture Register, array offset: 0x4, array step: 0x20 */ + __IO uint16_t LOAD; /**< Timer Channel Load Register, array offset: 0x6, array step: 0x20 */ + __IO uint16_t HOLD; /**< Timer Channel Hold Register, array offset: 0x8, array step: 0x20 */ + __IO uint16_t CNTR; /**< Timer Channel Counter Register, array offset: 0xA, array step: 0x20 */ + __IO uint16_t CTRL; /**< Timer Channel Control Register, array offset: 0xC, array step: 0x20 */ + __IO uint16_t SCTRL; /**< Timer Channel Status and Control Register, array offset: 0xE, array step: 0x20 */ + __IO uint16_t CMPLD1; /**< Timer Channel Comparator Load Register 1, array offset: 0x10, array step: 0x20 */ + __IO uint16_t CMPLD2; /**< Timer Channel Comparator Load Register 2, array offset: 0x12, array step: 0x20 */ + __IO uint16_t CSCTRL; /**< Timer Channel Comparator Status and Control Register, array offset: 0x14, array step: 0x20 */ + __IO uint16_t FILT; /**< Timer Channel Input Filter Register, array offset: 0x16, array step: 0x20 */ + __IO uint16_t DMA; /**< Timer Channel DMA Enable Register, array offset: 0x18, array step: 0x20 */ + uint8_t RESERVED_0[4]; + __IO uint16_t ENBL; /**< Timer Channel Enable Register, array offset: 0x1E, array step: 0x20, this item is not available for all array instances */ + } CHANNEL[4]; +} TMR_Type; + +/* ---------------------------------------------------------------------------- + -- TMR Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup TMR_Register_Masks TMR Register Masks + * @{ + */ + +/*! @name COMP1 - Timer Channel Compare Register 1 */ +/*! @{ */ +#define TMR_COMP1_COMPARISON_1_MASK (0xFFFFU) +#define TMR_COMP1_COMPARISON_1_SHIFT (0U) +#define TMR_COMP1_COMPARISON_1(x) (((uint16_t)(((uint16_t)(x)) << TMR_COMP1_COMPARISON_1_SHIFT)) & TMR_COMP1_COMPARISON_1_MASK) +/*! @} */ + +/* The count of TMR_COMP1 */ +#define TMR_COMP1_COUNT (4U) + +/*! @name COMP2 - Timer Channel Compare Register 2 */ +/*! @{ */ +#define TMR_COMP2_COMPARISON_2_MASK (0xFFFFU) +#define TMR_COMP2_COMPARISON_2_SHIFT (0U) +#define TMR_COMP2_COMPARISON_2(x) (((uint16_t)(((uint16_t)(x)) << TMR_COMP2_COMPARISON_2_SHIFT)) & TMR_COMP2_COMPARISON_2_MASK) +/*! @} */ + +/* The count of TMR_COMP2 */ +#define TMR_COMP2_COUNT (4U) + +/*! @name CAPT - Timer Channel Capture Register */ +/*! @{ */ +#define TMR_CAPT_CAPTURE_MASK (0xFFFFU) +#define TMR_CAPT_CAPTURE_SHIFT (0U) +#define TMR_CAPT_CAPTURE(x) (((uint16_t)(((uint16_t)(x)) << TMR_CAPT_CAPTURE_SHIFT)) & TMR_CAPT_CAPTURE_MASK) +/*! @} */ + +/* The count of TMR_CAPT */ +#define TMR_CAPT_COUNT (4U) + +/*! @name LOAD - Timer Channel Load Register */ +/*! @{ */ +#define TMR_LOAD_LOAD_MASK (0xFFFFU) +#define TMR_LOAD_LOAD_SHIFT (0U) +#define TMR_LOAD_LOAD(x) (((uint16_t)(((uint16_t)(x)) << TMR_LOAD_LOAD_SHIFT)) & TMR_LOAD_LOAD_MASK) +/*! @} */ + +/* The count of TMR_LOAD */ +#define TMR_LOAD_COUNT (4U) + +/*! @name HOLD - Timer Channel Hold Register */ +/*! @{ */ +#define TMR_HOLD_HOLD_MASK (0xFFFFU) +#define TMR_HOLD_HOLD_SHIFT (0U) +#define TMR_HOLD_HOLD(x) (((uint16_t)(((uint16_t)(x)) << TMR_HOLD_HOLD_SHIFT)) & TMR_HOLD_HOLD_MASK) +/*! @} */ + +/* The count of TMR_HOLD */ +#define TMR_HOLD_COUNT (4U) + +/*! @name CNTR - Timer Channel Counter Register */ +/*! @{ */ +#define TMR_CNTR_COUNTER_MASK (0xFFFFU) +#define TMR_CNTR_COUNTER_SHIFT (0U) +#define TMR_CNTR_COUNTER(x) (((uint16_t)(((uint16_t)(x)) << TMR_CNTR_COUNTER_SHIFT)) & TMR_CNTR_COUNTER_MASK) +/*! @} */ + +/* The count of TMR_CNTR */ +#define TMR_CNTR_COUNT (4U) + +/*! @name CTRL - Timer Channel Control Register */ +/*! @{ */ +#define TMR_CTRL_OUTMODE_MASK (0x7U) +#define TMR_CTRL_OUTMODE_SHIFT (0U) +/*! OUTMODE - Output Mode + * 0b000..Asserted while counter is active + * 0b001..Clear OFLAG output on successful compare + * 0b010..Set OFLAG output on successful compare + * 0b011..Toggle OFLAG output on successful compare + * 0b100..Toggle OFLAG output using alternating compare registers + * 0b101..Set on compare, cleared on secondary source input edge + * 0b110..Set on compare, cleared on counter rollover + * 0b111..Enable gated clock output while counter is active + */ +#define TMR_CTRL_OUTMODE(x) (((uint16_t)(((uint16_t)(x)) << TMR_CTRL_OUTMODE_SHIFT)) & TMR_CTRL_OUTMODE_MASK) +#define TMR_CTRL_COINIT_MASK (0x8U) +#define TMR_CTRL_COINIT_SHIFT (3U) +/*! COINIT - Co-Channel Initialization + * 0b0..Co-channel counter/timers cannot force a re-initialization of this counter/timer + * 0b1..Co-channel counter/timers may force a re-initialization of this counter/timer + */ +#define TMR_CTRL_COINIT(x) (((uint16_t)(((uint16_t)(x)) << TMR_CTRL_COINIT_SHIFT)) & TMR_CTRL_COINIT_MASK) +#define TMR_CTRL_DIR_MASK (0x10U) +#define TMR_CTRL_DIR_SHIFT (4U) +/*! DIR - Count Direction + * 0b0..Count up. + * 0b1..Count down. + */ +#define TMR_CTRL_DIR(x) (((uint16_t)(((uint16_t)(x)) << TMR_CTRL_DIR_SHIFT)) & TMR_CTRL_DIR_MASK) +#define TMR_CTRL_LENGTH_MASK (0x20U) +#define TMR_CTRL_LENGTH_SHIFT (5U) +/*! LENGTH - Count Length + * 0b0..Count until roll over at $FFFF and continue from $0000. + * 0b1..Count until compare, then re-initialize. If counting up, a successful compare occurs when the counter reaches a COMP1 value. If counting down, a successful compare occurs when the counter reaches a COMP2 value. When output mode $4 is used, alternating values of COMP1 and COMP2 are used to generate successful comparisons. For example, the counter counts until a COMP1 value is reached, re-initializes, counts until COMP2 value is reached, re-initializes, counts until COMP1 value is reached, and so on. + */ +#define TMR_CTRL_LENGTH(x) (((uint16_t)(((uint16_t)(x)) << TMR_CTRL_LENGTH_SHIFT)) & TMR_CTRL_LENGTH_MASK) +#define TMR_CTRL_ONCE_MASK (0x40U) +#define TMR_CTRL_ONCE_SHIFT (6U) +/*! ONCE - Count Once + * 0b0..Count repeatedly. + * 0b1..Count until compare and then stop. If counting up, a successful compare occurs when the counter reaches a COMP1 value. If counting down, a successful compare occurs when the counter reaches a COMP2 value. When output mode $4 is used, the counter re-initializes after reaching the COMP1 value, continues to count to the COMP2 value, and then stops. + */ +#define TMR_CTRL_ONCE(x) (((uint16_t)(((uint16_t)(x)) << TMR_CTRL_ONCE_SHIFT)) & TMR_CTRL_ONCE_MASK) +#define TMR_CTRL_SCS_MASK (0x180U) +#define TMR_CTRL_SCS_SHIFT (7U) +/*! SCS - Secondary Count Source + * 0b00..Counter 0 input pin + * 0b01..Counter 1 input pin + * 0b10..Counter 2 input pin + * 0b11..Counter 3 input pin + */ +#define TMR_CTRL_SCS(x) (((uint16_t)(((uint16_t)(x)) << TMR_CTRL_SCS_SHIFT)) & TMR_CTRL_SCS_MASK) +#define TMR_CTRL_PCS_MASK (0x1E00U) +#define TMR_CTRL_PCS_SHIFT (9U) +/*! PCS - Primary Count Source + * 0b0000..Counter 0 input pin + * 0b0001..Counter 1 input pin + * 0b0010..Counter 2 input pin + * 0b0011..Counter 3 input pin + * 0b0100..Counter 0 output + * 0b0101..Counter 1 output + * 0b0110..Counter 2 output + * 0b0111..Counter 3 output + * 0b1000..IP bus clock divide by 1 prescaler + * 0b1001..IP bus clock divide by 2 prescaler + * 0b1010..IP bus clock divide by 4 prescaler + * 0b1011..IP bus clock divide by 8 prescaler + * 0b1100..IP bus clock divide by 16 prescaler + * 0b1101..IP bus clock divide by 32 prescaler + * 0b1110..IP bus clock divide by 64 prescaler + * 0b1111..IP bus clock divide by 128 prescaler + */ +#define TMR_CTRL_PCS(x) (((uint16_t)(((uint16_t)(x)) << TMR_CTRL_PCS_SHIFT)) & TMR_CTRL_PCS_MASK) +#define TMR_CTRL_CM_MASK (0xE000U) +#define TMR_CTRL_CM_SHIFT (13U) +/*! CM - Count Mode + * 0b000..No operation + * 0b001..Count rising edges of primary sourceRising edges are counted only when SCTRL[IPS] = 0. Falling edges are counted when SCTRL[IPS] = 1. If the primary count source is IP bus clock divide by 1, only rising edges are counted regardless of the value of SCTRL[IPS]. + * 0b010..Count rising and falling edges of primary sourceIP bus clock divide by 1 cannot be used as a primary count source in edge count mode. + * 0b011..Count rising edges of primary source while secondary input high active + * 0b100..Quadrature count mode, uses primary and secondary sources + * 0b101..Count rising edges of primary source; secondary source specifies directionRising edges are counted only when SCTRL[IPS] = 0. Falling edges are counted when SCTRL[IPS] = 1. + * 0b110..Edge of secondary source triggers primary count until compare + * 0b111..Cascaded counter mode (up/down)The primary count source must be set to one of the counter outputs. + */ +#define TMR_CTRL_CM(x) (((uint16_t)(((uint16_t)(x)) << TMR_CTRL_CM_SHIFT)) & TMR_CTRL_CM_MASK) +/*! @} */ + +/* The count of TMR_CTRL */ +#define TMR_CTRL_COUNT (4U) + +/*! @name SCTRL - Timer Channel Status and Control Register */ +/*! @{ */ +#define TMR_SCTRL_OEN_MASK (0x1U) +#define TMR_SCTRL_OEN_SHIFT (0U) +/*! OEN - Output Enable + * 0b0..The external pin is configured as an input. + * 0b1..The OFLAG output signal is driven on the external pin. Other timer groups using this external pin as their input see the driven value. The polarity of the signal is determined by OPS. + */ +#define TMR_SCTRL_OEN(x) (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_OEN_SHIFT)) & TMR_SCTRL_OEN_MASK) +#define TMR_SCTRL_OPS_MASK (0x2U) +#define TMR_SCTRL_OPS_SHIFT (1U) +/*! OPS - Output Polarity Select + * 0b0..True polarity. + * 0b1..Inverted polarity. + */ +#define TMR_SCTRL_OPS(x) (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_OPS_SHIFT)) & TMR_SCTRL_OPS_MASK) +#define TMR_SCTRL_FORCE_MASK (0x4U) +#define TMR_SCTRL_FORCE_SHIFT (2U) +#define TMR_SCTRL_FORCE(x) (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_FORCE_SHIFT)) & TMR_SCTRL_FORCE_MASK) +#define TMR_SCTRL_VAL_MASK (0x8U) +#define TMR_SCTRL_VAL_SHIFT (3U) +#define TMR_SCTRL_VAL(x) (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_VAL_SHIFT)) & TMR_SCTRL_VAL_MASK) +#define TMR_SCTRL_EEOF_MASK (0x10U) +#define TMR_SCTRL_EEOF_SHIFT (4U) +#define TMR_SCTRL_EEOF(x) (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_EEOF_SHIFT)) & TMR_SCTRL_EEOF_MASK) +#define TMR_SCTRL_MSTR_MASK (0x20U) +#define TMR_SCTRL_MSTR_SHIFT (5U) +#define TMR_SCTRL_MSTR(x) (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_MSTR_SHIFT)) & TMR_SCTRL_MSTR_MASK) +#define TMR_SCTRL_CAPTURE_MODE_MASK (0xC0U) +#define TMR_SCTRL_CAPTURE_MODE_SHIFT (6U) +/*! CAPTURE_MODE - Input Capture Mode + * 0b00..Capture function is disabled + * 0b01..Load capture register on rising edge (when IPS=0) or falling edge (when IPS=1) of input + * 0b10..Load capture register on falling edge (when IPS=0) or rising edge (when IPS=1) of input + * 0b11..Load capture register on both edges of input + */ +#define TMR_SCTRL_CAPTURE_MODE(x) (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_CAPTURE_MODE_SHIFT)) & TMR_SCTRL_CAPTURE_MODE_MASK) +#define TMR_SCTRL_INPUT_MASK (0x100U) +#define TMR_SCTRL_INPUT_SHIFT (8U) +#define TMR_SCTRL_INPUT(x) (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_INPUT_SHIFT)) & TMR_SCTRL_INPUT_MASK) +#define TMR_SCTRL_IPS_MASK (0x200U) +#define TMR_SCTRL_IPS_SHIFT (9U) +#define TMR_SCTRL_IPS(x) (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_IPS_SHIFT)) & TMR_SCTRL_IPS_MASK) +#define TMR_SCTRL_IEFIE_MASK (0x400U) +#define TMR_SCTRL_IEFIE_SHIFT (10U) +#define TMR_SCTRL_IEFIE(x) (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_IEFIE_SHIFT)) & TMR_SCTRL_IEFIE_MASK) +#define TMR_SCTRL_IEF_MASK (0x800U) +#define TMR_SCTRL_IEF_SHIFT (11U) +#define TMR_SCTRL_IEF(x) (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_IEF_SHIFT)) & TMR_SCTRL_IEF_MASK) +#define TMR_SCTRL_TOFIE_MASK (0x1000U) +#define TMR_SCTRL_TOFIE_SHIFT (12U) +#define TMR_SCTRL_TOFIE(x) (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_TOFIE_SHIFT)) & TMR_SCTRL_TOFIE_MASK) +#define TMR_SCTRL_TOF_MASK (0x2000U) +#define TMR_SCTRL_TOF_SHIFT (13U) +#define TMR_SCTRL_TOF(x) (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_TOF_SHIFT)) & TMR_SCTRL_TOF_MASK) +#define TMR_SCTRL_TCFIE_MASK (0x4000U) +#define TMR_SCTRL_TCFIE_SHIFT (14U) +#define TMR_SCTRL_TCFIE(x) (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_TCFIE_SHIFT)) & TMR_SCTRL_TCFIE_MASK) +#define TMR_SCTRL_TCF_MASK (0x8000U) +#define TMR_SCTRL_TCF_SHIFT (15U) +#define TMR_SCTRL_TCF(x) (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_TCF_SHIFT)) & TMR_SCTRL_TCF_MASK) +/*! @} */ + +/* The count of TMR_SCTRL */ +#define TMR_SCTRL_COUNT (4U) + +/*! @name CMPLD1 - Timer Channel Comparator Load Register 1 */ +/*! @{ */ +#define TMR_CMPLD1_COMPARATOR_LOAD_1_MASK (0xFFFFU) +#define TMR_CMPLD1_COMPARATOR_LOAD_1_SHIFT (0U) +#define TMR_CMPLD1_COMPARATOR_LOAD_1(x) (((uint16_t)(((uint16_t)(x)) << TMR_CMPLD1_COMPARATOR_LOAD_1_SHIFT)) & TMR_CMPLD1_COMPARATOR_LOAD_1_MASK) +/*! @} */ + +/* The count of TMR_CMPLD1 */ +#define TMR_CMPLD1_COUNT (4U) + +/*! @name CMPLD2 - Timer Channel Comparator Load Register 2 */ +/*! @{ */ +#define TMR_CMPLD2_COMPARATOR_LOAD_2_MASK (0xFFFFU) +#define TMR_CMPLD2_COMPARATOR_LOAD_2_SHIFT (0U) +#define TMR_CMPLD2_COMPARATOR_LOAD_2(x) (((uint16_t)(((uint16_t)(x)) << TMR_CMPLD2_COMPARATOR_LOAD_2_SHIFT)) & TMR_CMPLD2_COMPARATOR_LOAD_2_MASK) +/*! @} */ + +/* The count of TMR_CMPLD2 */ +#define TMR_CMPLD2_COUNT (4U) + +/*! @name CSCTRL - Timer Channel Comparator Status and Control Register */ +/*! @{ */ +#define TMR_CSCTRL_CL1_MASK (0x3U) +#define TMR_CSCTRL_CL1_SHIFT (0U) +/*! CL1 - Compare Load Control 1 + * 0b00..Never preload + * 0b01..Load upon successful compare with the value in COMP1 + * 0b10..Load upon successful compare with the value in COMP2 + * 0b11..Reserved + */ +#define TMR_CSCTRL_CL1(x) (((uint16_t)(((uint16_t)(x)) << TMR_CSCTRL_CL1_SHIFT)) & TMR_CSCTRL_CL1_MASK) +#define TMR_CSCTRL_CL2_MASK (0xCU) +#define TMR_CSCTRL_CL2_SHIFT (2U) +/*! CL2 - Compare Load Control 2 + * 0b00..Never preload + * 0b01..Load upon successful compare with the value in COMP1 + * 0b10..Load upon successful compare with the value in COMP2 + * 0b11..Reserved + */ +#define TMR_CSCTRL_CL2(x) (((uint16_t)(((uint16_t)(x)) << TMR_CSCTRL_CL2_SHIFT)) & TMR_CSCTRL_CL2_MASK) +#define TMR_CSCTRL_TCF1_MASK (0x10U) +#define TMR_CSCTRL_TCF1_SHIFT (4U) +#define TMR_CSCTRL_TCF1(x) (((uint16_t)(((uint16_t)(x)) << TMR_CSCTRL_TCF1_SHIFT)) & TMR_CSCTRL_TCF1_MASK) +#define TMR_CSCTRL_TCF2_MASK (0x20U) +#define TMR_CSCTRL_TCF2_SHIFT (5U) +#define TMR_CSCTRL_TCF2(x) (((uint16_t)(((uint16_t)(x)) << TMR_CSCTRL_TCF2_SHIFT)) & TMR_CSCTRL_TCF2_MASK) +#define TMR_CSCTRL_TCF1EN_MASK (0x40U) +#define TMR_CSCTRL_TCF1EN_SHIFT (6U) +#define TMR_CSCTRL_TCF1EN(x) (((uint16_t)(((uint16_t)(x)) << TMR_CSCTRL_TCF1EN_SHIFT)) & TMR_CSCTRL_TCF1EN_MASK) +#define TMR_CSCTRL_TCF2EN_MASK (0x80U) +#define TMR_CSCTRL_TCF2EN_SHIFT (7U) +#define TMR_CSCTRL_TCF2EN(x) (((uint16_t)(((uint16_t)(x)) << TMR_CSCTRL_TCF2EN_SHIFT)) & TMR_CSCTRL_TCF2EN_MASK) +#define TMR_CSCTRL_UP_MASK (0x200U) +#define TMR_CSCTRL_UP_SHIFT (9U) +/*! UP - Counting Direction Indicator + * 0b0..The last count was in the DOWN direction. + * 0b1..The last count was in the UP direction. + */ +#define TMR_CSCTRL_UP(x) (((uint16_t)(((uint16_t)(x)) << TMR_CSCTRL_UP_SHIFT)) & TMR_CSCTRL_UP_MASK) +#define TMR_CSCTRL_TCI_MASK (0x400U) +#define TMR_CSCTRL_TCI_SHIFT (10U) +/*! TCI - Triggered Count Initialization Control + * 0b0..Stop counter upon receiving a second trigger event while still counting from the first trigger event. + * 0b1..Reload the counter upon receiving a second trigger event while still counting from the first trigger event. + */ +#define TMR_CSCTRL_TCI(x) (((uint16_t)(((uint16_t)(x)) << TMR_CSCTRL_TCI_SHIFT)) & TMR_CSCTRL_TCI_MASK) +#define TMR_CSCTRL_ROC_MASK (0x800U) +#define TMR_CSCTRL_ROC_SHIFT (11U) +/*! ROC - Reload on Capture + * 0b0..Do not reload the counter on a capture event. + * 0b1..Reload the counter on a capture event. + */ +#define TMR_CSCTRL_ROC(x) (((uint16_t)(((uint16_t)(x)) << TMR_CSCTRL_ROC_SHIFT)) & TMR_CSCTRL_ROC_MASK) +#define TMR_CSCTRL_ALT_LOAD_MASK (0x1000U) +#define TMR_CSCTRL_ALT_LOAD_SHIFT (12U) +/*! ALT_LOAD - Alternative Load Enable + * 0b0..Counter can be re-initialized only with the LOAD register. + * 0b1..Counter can be re-initialized with the LOAD or CMPLD2 registers depending on count direction. + */ +#define TMR_CSCTRL_ALT_LOAD(x) (((uint16_t)(((uint16_t)(x)) << TMR_CSCTRL_ALT_LOAD_SHIFT)) & TMR_CSCTRL_ALT_LOAD_MASK) +#define TMR_CSCTRL_FAULT_MASK (0x2000U) +#define TMR_CSCTRL_FAULT_SHIFT (13U) +/*! FAULT - Fault Enable + * 0b0..Fault function disabled. + * 0b1..Fault function enabled. + */ +#define TMR_CSCTRL_FAULT(x) (((uint16_t)(((uint16_t)(x)) << TMR_CSCTRL_FAULT_SHIFT)) & TMR_CSCTRL_FAULT_MASK) +#define TMR_CSCTRL_DBG_EN_MASK (0xC000U) +#define TMR_CSCTRL_DBG_EN_SHIFT (14U) +/*! DBG_EN - Debug Actions Enable + * 0b00..Continue with normal operation during debug mode. (default) + * 0b01..Halt TMR counter during debug mode. + * 0b10..Force TMR output to logic 0 (prior to consideration of SCTRL[OPS]). + * 0b11..Both halt counter and force output to 0 during debug mode. + */ +#define TMR_CSCTRL_DBG_EN(x) (((uint16_t)(((uint16_t)(x)) << TMR_CSCTRL_DBG_EN_SHIFT)) & TMR_CSCTRL_DBG_EN_MASK) +/*! @} */ + +/* The count of TMR_CSCTRL */ +#define TMR_CSCTRL_COUNT (4U) + +/*! @name FILT - Timer Channel Input Filter Register */ +/*! @{ */ +#define TMR_FILT_FILT_PER_MASK (0xFFU) +#define TMR_FILT_FILT_PER_SHIFT (0U) +#define TMR_FILT_FILT_PER(x) (((uint16_t)(((uint16_t)(x)) << TMR_FILT_FILT_PER_SHIFT)) & TMR_FILT_FILT_PER_MASK) +#define TMR_FILT_FILT_CNT_MASK (0x700U) +#define TMR_FILT_FILT_CNT_SHIFT (8U) +#define TMR_FILT_FILT_CNT(x) (((uint16_t)(((uint16_t)(x)) << TMR_FILT_FILT_CNT_SHIFT)) & TMR_FILT_FILT_CNT_MASK) +/*! @} */ + +/* The count of TMR_FILT */ +#define TMR_FILT_COUNT (4U) + +/*! @name DMA - Timer Channel DMA Enable Register */ +/*! @{ */ +#define TMR_DMA_IEFDE_MASK (0x1U) +#define TMR_DMA_IEFDE_SHIFT (0U) +#define TMR_DMA_IEFDE(x) (((uint16_t)(((uint16_t)(x)) << TMR_DMA_IEFDE_SHIFT)) & TMR_DMA_IEFDE_MASK) +#define TMR_DMA_CMPLD1DE_MASK (0x2U) +#define TMR_DMA_CMPLD1DE_SHIFT (1U) +#define TMR_DMA_CMPLD1DE(x) (((uint16_t)(((uint16_t)(x)) << TMR_DMA_CMPLD1DE_SHIFT)) & TMR_DMA_CMPLD1DE_MASK) +#define TMR_DMA_CMPLD2DE_MASK (0x4U) +#define TMR_DMA_CMPLD2DE_SHIFT (2U) +#define TMR_DMA_CMPLD2DE(x) (((uint16_t)(((uint16_t)(x)) << TMR_DMA_CMPLD2DE_SHIFT)) & TMR_DMA_CMPLD2DE_MASK) +/*! @} */ + +/* The count of TMR_DMA */ +#define TMR_DMA_COUNT (4U) + +/*! @name ENBL - Timer Channel Enable Register */ +/*! @{ */ +#define TMR_ENBL_ENBL_MASK (0xFU) +#define TMR_ENBL_ENBL_SHIFT (0U) +/*! ENBL - Timer Channel Enable + * 0b0000..Timer channel is disabled. + * 0b0001..Timer channel is enabled. (default) + */ +#define TMR_ENBL_ENBL(x) (((uint16_t)(((uint16_t)(x)) << TMR_ENBL_ENBL_SHIFT)) & TMR_ENBL_ENBL_MASK) +/*! @} */ + +/* The count of TMR_ENBL */ +#define TMR_ENBL_COUNT (4U) + + +/*! + * @} + */ /* end of group TMR_Register_Masks */ + + +/* TMR - Peripheral instance base addresses */ +/** Peripheral TMR1 base address */ +#define TMR1_BASE (0x401DC000u) +/** Peripheral TMR1 base pointer */ +#define TMR1 ((TMR_Type *)TMR1_BASE) +/** Peripheral TMR2 base address */ +#define TMR2_BASE (0x401E0000u) +/** Peripheral TMR2 base pointer */ +#define TMR2 ((TMR_Type *)TMR2_BASE) +/** Peripheral TMR3 base address */ +#define TMR3_BASE (0x401E4000u) +/** Peripheral TMR3 base pointer */ +#define TMR3 ((TMR_Type *)TMR3_BASE) +/** Peripheral TMR4 base address */ +#define TMR4_BASE (0x401E8000u) +/** Peripheral TMR4 base pointer */ +#define TMR4 ((TMR_Type *)TMR4_BASE) +/** Array initializer of TMR peripheral base addresses */ +#define TMR_BASE_ADDRS { 0u, TMR1_BASE, TMR2_BASE, TMR3_BASE, TMR4_BASE } +/** Array initializer of TMR peripheral base pointers */ +#define TMR_BASE_PTRS { (TMR_Type *)0u, TMR1, TMR2, TMR3, TMR4 } +/** Interrupt vectors for the TMR peripheral type */ +#define TMR_IRQS { NotAvail_IRQn, TMR1_IRQn, TMR2_IRQn, TMR3_IRQn, TMR4_IRQn } + +/*! + * @} + */ /* end of group TMR_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- TRNG Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup TRNG_Peripheral_Access_Layer TRNG Peripheral Access Layer + * @{ + */ + +/** TRNG - Register Layout Typedef */ +typedef struct { + __IO uint32_t MCTL; /**< Miscellaneous Control Register, offset: 0x0 */ + __IO uint32_t SCMISC; /**< Statistical Check Miscellaneous Register, offset: 0x4 */ + __IO uint32_t PKRRNG; /**< Poker Range Register, offset: 0x8 */ + union { /* offset: 0xC */ + __IO uint32_t PKRMAX; /**< Poker Maximum Limit Register, offset: 0xC */ + __I uint32_t PKRSQ; /**< Poker Square Calculation Result Register, offset: 0xC */ + }; + __IO uint32_t SDCTL; /**< Seed Control Register, offset: 0x10 */ + union { /* offset: 0x14 */ + __IO uint32_t SBLIM; /**< Sparse Bit Limit Register, offset: 0x14 */ + __I uint32_t TOTSAM; /**< Total Samples Register, offset: 0x14 */ + }; + __IO uint32_t FRQMIN; /**< Frequency Count Minimum Limit Register, offset: 0x18 */ + union { /* offset: 0x1C */ + __I uint32_t FRQCNT; /**< Frequency Count Register, offset: 0x1C */ + __IO uint32_t FRQMAX; /**< Frequency Count Maximum Limit Register, offset: 0x1C */ + }; + union { /* offset: 0x20 */ + __I uint32_t SCMC; /**< Statistical Check Monobit Count Register, offset: 0x20 */ + __IO uint32_t SCML; /**< Statistical Check Monobit Limit Register, offset: 0x20 */ + }; + union { /* offset: 0x24 */ + __I uint32_t SCR1C; /**< Statistical Check Run Length 1 Count Register, offset: 0x24 */ + __IO uint32_t SCR1L; /**< Statistical Check Run Length 1 Limit Register, offset: 0x24 */ + }; + union { /* offset: 0x28 */ + __I uint32_t SCR2C; /**< Statistical Check Run Length 2 Count Register, offset: 0x28 */ + __IO uint32_t SCR2L; /**< Statistical Check Run Length 2 Limit Register, offset: 0x28 */ + }; + union { /* offset: 0x2C */ + __I uint32_t SCR3C; /**< Statistical Check Run Length 3 Count Register, offset: 0x2C */ + __IO uint32_t SCR3L; /**< Statistical Check Run Length 3 Limit Register, offset: 0x2C */ + }; + union { /* offset: 0x30 */ + __I uint32_t SCR4C; /**< Statistical Check Run Length 4 Count Register, offset: 0x30 */ + __IO uint32_t SCR4L; /**< Statistical Check Run Length 4 Limit Register, offset: 0x30 */ + }; + union { /* offset: 0x34 */ + __I uint32_t SCR5C; /**< Statistical Check Run Length 5 Count Register, offset: 0x34 */ + __IO uint32_t SCR5L; /**< Statistical Check Run Length 5 Limit Register, offset: 0x34 */ + }; + union { /* offset: 0x38 */ + __I uint32_t SCR6PC; /**< Statistical Check Run Length 6+ Count Register, offset: 0x38 */ + __IO uint32_t SCR6PL; /**< Statistical Check Run Length 6+ Limit Register, offset: 0x38 */ + }; + __I uint32_t STATUS; /**< Status Register, offset: 0x3C */ + __I uint32_t ENT[16]; /**< Entropy Read Register, array offset: 0x40, array step: 0x4 */ + __I uint32_t PKRCNT10; /**< Statistical Check Poker Count 1 and 0 Register, offset: 0x80 */ + __I uint32_t PKRCNT32; /**< Statistical Check Poker Count 3 and 2 Register, offset: 0x84 */ + __I uint32_t PKRCNT54; /**< Statistical Check Poker Count 5 and 4 Register, offset: 0x88 */ + __I uint32_t PKRCNT76; /**< Statistical Check Poker Count 7 and 6 Register, offset: 0x8C */ + __I uint32_t PKRCNT98; /**< Statistical Check Poker Count 9 and 8 Register, offset: 0x90 */ + __I uint32_t PKRCNTBA; /**< Statistical Check Poker Count B and A Register, offset: 0x94 */ + __I uint32_t PKRCNTDC; /**< Statistical Check Poker Count D and C Register, offset: 0x98 */ + __I uint32_t PKRCNTFE; /**< Statistical Check Poker Count F and E Register, offset: 0x9C */ + __IO uint32_t SEC_CFG; /**< Security Configuration Register, offset: 0xA0 */ + __IO uint32_t INT_CTRL; /**< Interrupt Control Register, offset: 0xA4 */ + __IO uint32_t INT_MASK; /**< Mask Register, offset: 0xA8 */ + __I uint32_t INT_STATUS; /**< Interrupt Status Register, offset: 0xAC */ + uint8_t RESERVED_0[64]; + __I uint32_t VID1; /**< Version ID Register (MS), offset: 0xF0 */ + __I uint32_t VID2; /**< Version ID Register (LS), offset: 0xF4 */ +} TRNG_Type; + +/* ---------------------------------------------------------------------------- + -- TRNG Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup TRNG_Register_Masks TRNG Register Masks + * @{ + */ + +/*! @name MCTL - Miscellaneous Control Register */ +/*! @{ */ +#define TRNG_MCTL_SAMP_MODE_MASK (0x3U) +#define TRNG_MCTL_SAMP_MODE_SHIFT (0U) +/*! SAMP_MODE + * 0b00..use Von Neumann data into both Entropy shifter and Statistical Checker + * 0b01..use raw data into both Entropy shifter and Statistical Checker + * 0b10..use Von Neumann data into Entropy shifter. Use raw data into Statistical Checker + * 0b11..undefined/reserved. + */ +#define TRNG_MCTL_SAMP_MODE(x) (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_SAMP_MODE_SHIFT)) & TRNG_MCTL_SAMP_MODE_MASK) +#define TRNG_MCTL_OSC_DIV_MASK (0xCU) +#define TRNG_MCTL_OSC_DIV_SHIFT (2U) +/*! OSC_DIV + * 0b00..use ring oscillator with no divide + * 0b01..use ring oscillator divided-by-2 + * 0b10..use ring oscillator divided-by-4 + * 0b11..use ring oscillator divided-by-8 + */ +#define TRNG_MCTL_OSC_DIV(x) (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_OSC_DIV_SHIFT)) & TRNG_MCTL_OSC_DIV_MASK) +#define TRNG_MCTL_UNUSED4_MASK (0x10U) +#define TRNG_MCTL_UNUSED4_SHIFT (4U) +#define TRNG_MCTL_UNUSED4(x) (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_UNUSED4_SHIFT)) & TRNG_MCTL_UNUSED4_MASK) +#define TRNG_MCTL_UNUSED5_MASK (0x20U) +#define TRNG_MCTL_UNUSED5_SHIFT (5U) +#define TRNG_MCTL_UNUSED5(x) (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_UNUSED5_SHIFT)) & TRNG_MCTL_UNUSED5_MASK) +#define TRNG_MCTL_RST_DEF_MASK (0x40U) +#define TRNG_MCTL_RST_DEF_SHIFT (6U) +#define TRNG_MCTL_RST_DEF(x) (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_RST_DEF_SHIFT)) & TRNG_MCTL_RST_DEF_MASK) +#define TRNG_MCTL_FOR_SCLK_MASK (0x80U) +#define TRNG_MCTL_FOR_SCLK_SHIFT (7U) +#define TRNG_MCTL_FOR_SCLK(x) (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_FOR_SCLK_SHIFT)) & TRNG_MCTL_FOR_SCLK_MASK) +#define TRNG_MCTL_FCT_FAIL_MASK (0x100U) +#define TRNG_MCTL_FCT_FAIL_SHIFT (8U) +#define TRNG_MCTL_FCT_FAIL(x) (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_FCT_FAIL_SHIFT)) & TRNG_MCTL_FCT_FAIL_MASK) +#define TRNG_MCTL_FCT_VAL_MASK (0x200U) +#define TRNG_MCTL_FCT_VAL_SHIFT (9U) +#define TRNG_MCTL_FCT_VAL(x) (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_FCT_VAL_SHIFT)) & TRNG_MCTL_FCT_VAL_MASK) +#define TRNG_MCTL_ENT_VAL_MASK (0x400U) +#define TRNG_MCTL_ENT_VAL_SHIFT (10U) +#define TRNG_MCTL_ENT_VAL(x) (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_ENT_VAL_SHIFT)) & TRNG_MCTL_ENT_VAL_MASK) +#define TRNG_MCTL_TST_OUT_MASK (0x800U) +#define TRNG_MCTL_TST_OUT_SHIFT (11U) +#define TRNG_MCTL_TST_OUT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_TST_OUT_SHIFT)) & TRNG_MCTL_TST_OUT_MASK) +#define TRNG_MCTL_ERR_MASK (0x1000U) +#define TRNG_MCTL_ERR_SHIFT (12U) +#define TRNG_MCTL_ERR(x) (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_ERR_SHIFT)) & TRNG_MCTL_ERR_MASK) +#define TRNG_MCTL_TSTOP_OK_MASK (0x2000U) +#define TRNG_MCTL_TSTOP_OK_SHIFT (13U) +#define TRNG_MCTL_TSTOP_OK(x) (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_TSTOP_OK_SHIFT)) & TRNG_MCTL_TSTOP_OK_MASK) +#define TRNG_MCTL_LRUN_CONT_MASK (0x4000U) +#define TRNG_MCTL_LRUN_CONT_SHIFT (14U) +#define TRNG_MCTL_LRUN_CONT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_LRUN_CONT_SHIFT)) & TRNG_MCTL_LRUN_CONT_MASK) +#define TRNG_MCTL_PRGM_MASK (0x10000U) +#define TRNG_MCTL_PRGM_SHIFT (16U) +#define TRNG_MCTL_PRGM(x) (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_PRGM_SHIFT)) & TRNG_MCTL_PRGM_MASK) +/*! @} */ + +/*! @name SCMISC - Statistical Check Miscellaneous Register */ +/*! @{ */ +#define TRNG_SCMISC_LRUN_MAX_MASK (0xFFU) +#define TRNG_SCMISC_LRUN_MAX_SHIFT (0U) +#define TRNG_SCMISC_LRUN_MAX(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCMISC_LRUN_MAX_SHIFT)) & TRNG_SCMISC_LRUN_MAX_MASK) +#define TRNG_SCMISC_RTY_CT_MASK (0xF0000U) +#define TRNG_SCMISC_RTY_CT_SHIFT (16U) +#define TRNG_SCMISC_RTY_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCMISC_RTY_CT_SHIFT)) & TRNG_SCMISC_RTY_CT_MASK) +/*! @} */ + +/*! @name PKRRNG - Poker Range Register */ +/*! @{ */ +#define TRNG_PKRRNG_PKR_RNG_MASK (0xFFFFU) +#define TRNG_PKRRNG_PKR_RNG_SHIFT (0U) +#define TRNG_PKRRNG_PKR_RNG(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRRNG_PKR_RNG_SHIFT)) & TRNG_PKRRNG_PKR_RNG_MASK) +/*! @} */ + +/*! @name PKRMAX - Poker Maximum Limit Register */ +/*! @{ */ +#define TRNG_PKRMAX_PKR_MAX_MASK (0xFFFFFFU) +#define TRNG_PKRMAX_PKR_MAX_SHIFT (0U) +#define TRNG_PKRMAX_PKR_MAX(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRMAX_PKR_MAX_SHIFT)) & TRNG_PKRMAX_PKR_MAX_MASK) +/*! @} */ + +/*! @name PKRSQ - Poker Square Calculation Result Register */ +/*! @{ */ +#define TRNG_PKRSQ_PKR_SQ_MASK (0xFFFFFFU) +#define TRNG_PKRSQ_PKR_SQ_SHIFT (0U) +#define TRNG_PKRSQ_PKR_SQ(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRSQ_PKR_SQ_SHIFT)) & TRNG_PKRSQ_PKR_SQ_MASK) +/*! @} */ + +/*! @name SDCTL - Seed Control Register */ +/*! @{ */ +#define TRNG_SDCTL_SAMP_SIZE_MASK (0xFFFFU) +#define TRNG_SDCTL_SAMP_SIZE_SHIFT (0U) +#define TRNG_SDCTL_SAMP_SIZE(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SDCTL_SAMP_SIZE_SHIFT)) & TRNG_SDCTL_SAMP_SIZE_MASK) +#define TRNG_SDCTL_ENT_DLY_MASK (0xFFFF0000U) +#define TRNG_SDCTL_ENT_DLY_SHIFT (16U) +#define TRNG_SDCTL_ENT_DLY(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SDCTL_ENT_DLY_SHIFT)) & TRNG_SDCTL_ENT_DLY_MASK) +/*! @} */ + +/*! @name SBLIM - Sparse Bit Limit Register */ +/*! @{ */ +#define TRNG_SBLIM_SB_LIM_MASK (0x3FFU) +#define TRNG_SBLIM_SB_LIM_SHIFT (0U) +#define TRNG_SBLIM_SB_LIM(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SBLIM_SB_LIM_SHIFT)) & TRNG_SBLIM_SB_LIM_MASK) +/*! @} */ + +/*! @name TOTSAM - Total Samples Register */ +/*! @{ */ +#define TRNG_TOTSAM_TOT_SAM_MASK (0xFFFFFU) +#define TRNG_TOTSAM_TOT_SAM_SHIFT (0U) +#define TRNG_TOTSAM_TOT_SAM(x) (((uint32_t)(((uint32_t)(x)) << TRNG_TOTSAM_TOT_SAM_SHIFT)) & TRNG_TOTSAM_TOT_SAM_MASK) +/*! @} */ + +/*! @name FRQMIN - Frequency Count Minimum Limit Register */ +/*! @{ */ +#define TRNG_FRQMIN_FRQ_MIN_MASK (0x3FFFFFU) +#define TRNG_FRQMIN_FRQ_MIN_SHIFT (0U) +#define TRNG_FRQMIN_FRQ_MIN(x) (((uint32_t)(((uint32_t)(x)) << TRNG_FRQMIN_FRQ_MIN_SHIFT)) & TRNG_FRQMIN_FRQ_MIN_MASK) +/*! @} */ + +/*! @name FRQCNT - Frequency Count Register */ +/*! @{ */ +#define TRNG_FRQCNT_FRQ_CT_MASK (0x3FFFFFU) +#define TRNG_FRQCNT_FRQ_CT_SHIFT (0U) +#define TRNG_FRQCNT_FRQ_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_FRQCNT_FRQ_CT_SHIFT)) & TRNG_FRQCNT_FRQ_CT_MASK) +/*! @} */ + +/*! @name FRQMAX - Frequency Count Maximum Limit Register */ +/*! @{ */ +#define TRNG_FRQMAX_FRQ_MAX_MASK (0x3FFFFFU) +#define TRNG_FRQMAX_FRQ_MAX_SHIFT (0U) +#define TRNG_FRQMAX_FRQ_MAX(x) (((uint32_t)(((uint32_t)(x)) << TRNG_FRQMAX_FRQ_MAX_SHIFT)) & TRNG_FRQMAX_FRQ_MAX_MASK) +/*! @} */ + +/*! @name SCMC - Statistical Check Monobit Count Register */ +/*! @{ */ +#define TRNG_SCMC_MONO_CT_MASK (0xFFFFU) +#define TRNG_SCMC_MONO_CT_SHIFT (0U) +#define TRNG_SCMC_MONO_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCMC_MONO_CT_SHIFT)) & TRNG_SCMC_MONO_CT_MASK) +/*! @} */ + +/*! @name SCML - Statistical Check Monobit Limit Register */ +/*! @{ */ +#define TRNG_SCML_MONO_MAX_MASK (0xFFFFU) +#define TRNG_SCML_MONO_MAX_SHIFT (0U) +#define TRNG_SCML_MONO_MAX(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCML_MONO_MAX_SHIFT)) & TRNG_SCML_MONO_MAX_MASK) +#define TRNG_SCML_MONO_RNG_MASK (0xFFFF0000U) +#define TRNG_SCML_MONO_RNG_SHIFT (16U) +#define TRNG_SCML_MONO_RNG(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCML_MONO_RNG_SHIFT)) & TRNG_SCML_MONO_RNG_MASK) +/*! @} */ + +/*! @name SCR1C - Statistical Check Run Length 1 Count Register */ +/*! @{ */ +#define TRNG_SCR1C_R1_0_CT_MASK (0x7FFFU) +#define TRNG_SCR1C_R1_0_CT_SHIFT (0U) +#define TRNG_SCR1C_R1_0_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR1C_R1_0_CT_SHIFT)) & TRNG_SCR1C_R1_0_CT_MASK) +#define TRNG_SCR1C_R1_1_CT_MASK (0x7FFF0000U) +#define TRNG_SCR1C_R1_1_CT_SHIFT (16U) +#define TRNG_SCR1C_R1_1_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR1C_R1_1_CT_SHIFT)) & TRNG_SCR1C_R1_1_CT_MASK) +/*! @} */ + +/*! @name SCR1L - Statistical Check Run Length 1 Limit Register */ +/*! @{ */ +#define TRNG_SCR1L_RUN1_MAX_MASK (0x7FFFU) +#define TRNG_SCR1L_RUN1_MAX_SHIFT (0U) +#define TRNG_SCR1L_RUN1_MAX(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR1L_RUN1_MAX_SHIFT)) & TRNG_SCR1L_RUN1_MAX_MASK) +#define TRNG_SCR1L_RUN1_RNG_MASK (0x7FFF0000U) +#define TRNG_SCR1L_RUN1_RNG_SHIFT (16U) +#define TRNG_SCR1L_RUN1_RNG(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR1L_RUN1_RNG_SHIFT)) & TRNG_SCR1L_RUN1_RNG_MASK) +/*! @} */ + +/*! @name SCR2C - Statistical Check Run Length 2 Count Register */ +/*! @{ */ +#define TRNG_SCR2C_R2_0_CT_MASK (0x3FFFU) +#define TRNG_SCR2C_R2_0_CT_SHIFT (0U) +#define TRNG_SCR2C_R2_0_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR2C_R2_0_CT_SHIFT)) & TRNG_SCR2C_R2_0_CT_MASK) +#define TRNG_SCR2C_R2_1_CT_MASK (0x3FFF0000U) +#define TRNG_SCR2C_R2_1_CT_SHIFT (16U) +#define TRNG_SCR2C_R2_1_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR2C_R2_1_CT_SHIFT)) & TRNG_SCR2C_R2_1_CT_MASK) +/*! @} */ + +/*! @name SCR2L - Statistical Check Run Length 2 Limit Register */ +/*! @{ */ +#define TRNG_SCR2L_RUN2_MAX_MASK (0x3FFFU) +#define TRNG_SCR2L_RUN2_MAX_SHIFT (0U) +#define TRNG_SCR2L_RUN2_MAX(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR2L_RUN2_MAX_SHIFT)) & TRNG_SCR2L_RUN2_MAX_MASK) +#define TRNG_SCR2L_RUN2_RNG_MASK (0x3FFF0000U) +#define TRNG_SCR2L_RUN2_RNG_SHIFT (16U) +#define TRNG_SCR2L_RUN2_RNG(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR2L_RUN2_RNG_SHIFT)) & TRNG_SCR2L_RUN2_RNG_MASK) +/*! @} */ + +/*! @name SCR3C - Statistical Check Run Length 3 Count Register */ +/*! @{ */ +#define TRNG_SCR3C_R3_0_CT_MASK (0x1FFFU) +#define TRNG_SCR3C_R3_0_CT_SHIFT (0U) +#define TRNG_SCR3C_R3_0_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR3C_R3_0_CT_SHIFT)) & TRNG_SCR3C_R3_0_CT_MASK) +#define TRNG_SCR3C_R3_1_CT_MASK (0x1FFF0000U) +#define TRNG_SCR3C_R3_1_CT_SHIFT (16U) +#define TRNG_SCR3C_R3_1_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR3C_R3_1_CT_SHIFT)) & TRNG_SCR3C_R3_1_CT_MASK) +/*! @} */ + +/*! @name SCR3L - Statistical Check Run Length 3 Limit Register */ +/*! @{ */ +#define TRNG_SCR3L_RUN3_MAX_MASK (0x1FFFU) +#define TRNG_SCR3L_RUN3_MAX_SHIFT (0U) +#define TRNG_SCR3L_RUN3_MAX(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR3L_RUN3_MAX_SHIFT)) & TRNG_SCR3L_RUN3_MAX_MASK) +#define TRNG_SCR3L_RUN3_RNG_MASK (0x1FFF0000U) +#define TRNG_SCR3L_RUN3_RNG_SHIFT (16U) +#define TRNG_SCR3L_RUN3_RNG(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR3L_RUN3_RNG_SHIFT)) & TRNG_SCR3L_RUN3_RNG_MASK) +/*! @} */ + +/*! @name SCR4C - Statistical Check Run Length 4 Count Register */ +/*! @{ */ +#define TRNG_SCR4C_R4_0_CT_MASK (0xFFFU) +#define TRNG_SCR4C_R4_0_CT_SHIFT (0U) +#define TRNG_SCR4C_R4_0_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR4C_R4_0_CT_SHIFT)) & TRNG_SCR4C_R4_0_CT_MASK) +#define TRNG_SCR4C_R4_1_CT_MASK (0xFFF0000U) +#define TRNG_SCR4C_R4_1_CT_SHIFT (16U) +#define TRNG_SCR4C_R4_1_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR4C_R4_1_CT_SHIFT)) & TRNG_SCR4C_R4_1_CT_MASK) +/*! @} */ + +/*! @name SCR4L - Statistical Check Run Length 4 Limit Register */ +/*! @{ */ +#define TRNG_SCR4L_RUN4_MAX_MASK (0xFFFU) +#define TRNG_SCR4L_RUN4_MAX_SHIFT (0U) +#define TRNG_SCR4L_RUN4_MAX(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR4L_RUN4_MAX_SHIFT)) & TRNG_SCR4L_RUN4_MAX_MASK) +#define TRNG_SCR4L_RUN4_RNG_MASK (0xFFF0000U) +#define TRNG_SCR4L_RUN4_RNG_SHIFT (16U) +#define TRNG_SCR4L_RUN4_RNG(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR4L_RUN4_RNG_SHIFT)) & TRNG_SCR4L_RUN4_RNG_MASK) +/*! @} */ + +/*! @name SCR5C - Statistical Check Run Length 5 Count Register */ +/*! @{ */ +#define TRNG_SCR5C_R5_0_CT_MASK (0x7FFU) +#define TRNG_SCR5C_R5_0_CT_SHIFT (0U) +#define TRNG_SCR5C_R5_0_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR5C_R5_0_CT_SHIFT)) & TRNG_SCR5C_R5_0_CT_MASK) +#define TRNG_SCR5C_R5_1_CT_MASK (0x7FF0000U) +#define TRNG_SCR5C_R5_1_CT_SHIFT (16U) +#define TRNG_SCR5C_R5_1_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR5C_R5_1_CT_SHIFT)) & TRNG_SCR5C_R5_1_CT_MASK) +/*! @} */ + +/*! @name SCR5L - Statistical Check Run Length 5 Limit Register */ +/*! @{ */ +#define TRNG_SCR5L_RUN5_MAX_MASK (0x7FFU) +#define TRNG_SCR5L_RUN5_MAX_SHIFT (0U) +#define TRNG_SCR5L_RUN5_MAX(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR5L_RUN5_MAX_SHIFT)) & TRNG_SCR5L_RUN5_MAX_MASK) +#define TRNG_SCR5L_RUN5_RNG_MASK (0x7FF0000U) +#define TRNG_SCR5L_RUN5_RNG_SHIFT (16U) +#define TRNG_SCR5L_RUN5_RNG(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR5L_RUN5_RNG_SHIFT)) & TRNG_SCR5L_RUN5_RNG_MASK) +/*! @} */ + +/*! @name SCR6PC - Statistical Check Run Length 6+ Count Register */ +/*! @{ */ +#define TRNG_SCR6PC_R6P_0_CT_MASK (0x7FFU) +#define TRNG_SCR6PC_R6P_0_CT_SHIFT (0U) +#define TRNG_SCR6PC_R6P_0_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR6PC_R6P_0_CT_SHIFT)) & TRNG_SCR6PC_R6P_0_CT_MASK) +#define TRNG_SCR6PC_R6P_1_CT_MASK (0x7FF0000U) +#define TRNG_SCR6PC_R6P_1_CT_SHIFT (16U) +#define TRNG_SCR6PC_R6P_1_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR6PC_R6P_1_CT_SHIFT)) & TRNG_SCR6PC_R6P_1_CT_MASK) +/*! @} */ + +/*! @name SCR6PL - Statistical Check Run Length 6+ Limit Register */ +/*! @{ */ +#define TRNG_SCR6PL_RUN6P_MAX_MASK (0x7FFU) +#define TRNG_SCR6PL_RUN6P_MAX_SHIFT (0U) +#define TRNG_SCR6PL_RUN6P_MAX(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR6PL_RUN6P_MAX_SHIFT)) & TRNG_SCR6PL_RUN6P_MAX_MASK) +#define TRNG_SCR6PL_RUN6P_RNG_MASK (0x7FF0000U) +#define TRNG_SCR6PL_RUN6P_RNG_SHIFT (16U) +#define TRNG_SCR6PL_RUN6P_RNG(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR6PL_RUN6P_RNG_SHIFT)) & TRNG_SCR6PL_RUN6P_RNG_MASK) +/*! @} */ + +/*! @name STATUS - Status Register */ +/*! @{ */ +#define TRNG_STATUS_TF1BR0_MASK (0x1U) +#define TRNG_STATUS_TF1BR0_SHIFT (0U) +#define TRNG_STATUS_TF1BR0(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TF1BR0_SHIFT)) & TRNG_STATUS_TF1BR0_MASK) +#define TRNG_STATUS_TF1BR1_MASK (0x2U) +#define TRNG_STATUS_TF1BR1_SHIFT (1U) +#define TRNG_STATUS_TF1BR1(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TF1BR1_SHIFT)) & TRNG_STATUS_TF1BR1_MASK) +#define TRNG_STATUS_TF2BR0_MASK (0x4U) +#define TRNG_STATUS_TF2BR0_SHIFT (2U) +#define TRNG_STATUS_TF2BR0(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TF2BR0_SHIFT)) & TRNG_STATUS_TF2BR0_MASK) +#define TRNG_STATUS_TF2BR1_MASK (0x8U) +#define TRNG_STATUS_TF2BR1_SHIFT (3U) +#define TRNG_STATUS_TF2BR1(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TF2BR1_SHIFT)) & TRNG_STATUS_TF2BR1_MASK) +#define TRNG_STATUS_TF3BR0_MASK (0x10U) +#define TRNG_STATUS_TF3BR0_SHIFT (4U) +#define TRNG_STATUS_TF3BR0(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TF3BR0_SHIFT)) & TRNG_STATUS_TF3BR0_MASK) +#define TRNG_STATUS_TF3BR1_MASK (0x20U) +#define TRNG_STATUS_TF3BR1_SHIFT (5U) +#define TRNG_STATUS_TF3BR1(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TF3BR1_SHIFT)) & TRNG_STATUS_TF3BR1_MASK) +#define TRNG_STATUS_TF4BR0_MASK (0x40U) +#define TRNG_STATUS_TF4BR0_SHIFT (6U) +#define TRNG_STATUS_TF4BR0(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TF4BR0_SHIFT)) & TRNG_STATUS_TF4BR0_MASK) +#define TRNG_STATUS_TF4BR1_MASK (0x80U) +#define TRNG_STATUS_TF4BR1_SHIFT (7U) +#define TRNG_STATUS_TF4BR1(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TF4BR1_SHIFT)) & TRNG_STATUS_TF4BR1_MASK) +#define TRNG_STATUS_TF5BR0_MASK (0x100U) +#define TRNG_STATUS_TF5BR0_SHIFT (8U) +#define TRNG_STATUS_TF5BR0(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TF5BR0_SHIFT)) & TRNG_STATUS_TF5BR0_MASK) +#define TRNG_STATUS_TF5BR1_MASK (0x200U) +#define TRNG_STATUS_TF5BR1_SHIFT (9U) +#define TRNG_STATUS_TF5BR1(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TF5BR1_SHIFT)) & TRNG_STATUS_TF5BR1_MASK) +#define TRNG_STATUS_TF6PBR0_MASK (0x400U) +#define TRNG_STATUS_TF6PBR0_SHIFT (10U) +#define TRNG_STATUS_TF6PBR0(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TF6PBR0_SHIFT)) & TRNG_STATUS_TF6PBR0_MASK) +#define TRNG_STATUS_TF6PBR1_MASK (0x800U) +#define TRNG_STATUS_TF6PBR1_SHIFT (11U) +#define TRNG_STATUS_TF6PBR1(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TF6PBR1_SHIFT)) & TRNG_STATUS_TF6PBR1_MASK) +#define TRNG_STATUS_TFSB_MASK (0x1000U) +#define TRNG_STATUS_TFSB_SHIFT (12U) +#define TRNG_STATUS_TFSB(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TFSB_SHIFT)) & TRNG_STATUS_TFSB_MASK) +#define TRNG_STATUS_TFLR_MASK (0x2000U) +#define TRNG_STATUS_TFLR_SHIFT (13U) +#define TRNG_STATUS_TFLR(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TFLR_SHIFT)) & TRNG_STATUS_TFLR_MASK) +#define TRNG_STATUS_TFP_MASK (0x4000U) +#define TRNG_STATUS_TFP_SHIFT (14U) +#define TRNG_STATUS_TFP(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TFP_SHIFT)) & TRNG_STATUS_TFP_MASK) +#define TRNG_STATUS_TFMB_MASK (0x8000U) +#define TRNG_STATUS_TFMB_SHIFT (15U) +#define TRNG_STATUS_TFMB(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TFMB_SHIFT)) & TRNG_STATUS_TFMB_MASK) +#define TRNG_STATUS_RETRY_CT_MASK (0xF0000U) +#define TRNG_STATUS_RETRY_CT_SHIFT (16U) +#define TRNG_STATUS_RETRY_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_RETRY_CT_SHIFT)) & TRNG_STATUS_RETRY_CT_MASK) +/*! @} */ + +/*! @name ENT - Entropy Read Register */ +/*! @{ */ +#define TRNG_ENT_ENT_MASK (0xFFFFFFFFU) +#define TRNG_ENT_ENT_SHIFT (0U) +#define TRNG_ENT_ENT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_ENT_ENT_SHIFT)) & TRNG_ENT_ENT_MASK) +/*! @} */ + +/* The count of TRNG_ENT */ +#define TRNG_ENT_COUNT (16U) + +/*! @name PKRCNT10 - Statistical Check Poker Count 1 and 0 Register */ +/*! @{ */ +#define TRNG_PKRCNT10_PKR_0_CT_MASK (0xFFFFU) +#define TRNG_PKRCNT10_PKR_0_CT_SHIFT (0U) +#define TRNG_PKRCNT10_PKR_0_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNT10_PKR_0_CT_SHIFT)) & TRNG_PKRCNT10_PKR_0_CT_MASK) +#define TRNG_PKRCNT10_PKR_1_CT_MASK (0xFFFF0000U) +#define TRNG_PKRCNT10_PKR_1_CT_SHIFT (16U) +#define TRNG_PKRCNT10_PKR_1_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNT10_PKR_1_CT_SHIFT)) & TRNG_PKRCNT10_PKR_1_CT_MASK) +/*! @} */ + +/*! @name PKRCNT32 - Statistical Check Poker Count 3 and 2 Register */ +/*! @{ */ +#define TRNG_PKRCNT32_PKR_2_CT_MASK (0xFFFFU) +#define TRNG_PKRCNT32_PKR_2_CT_SHIFT (0U) +#define TRNG_PKRCNT32_PKR_2_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNT32_PKR_2_CT_SHIFT)) & TRNG_PKRCNT32_PKR_2_CT_MASK) +#define TRNG_PKRCNT32_PKR_3_CT_MASK (0xFFFF0000U) +#define TRNG_PKRCNT32_PKR_3_CT_SHIFT (16U) +#define TRNG_PKRCNT32_PKR_3_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNT32_PKR_3_CT_SHIFT)) & TRNG_PKRCNT32_PKR_3_CT_MASK) +/*! @} */ + +/*! @name PKRCNT54 - Statistical Check Poker Count 5 and 4 Register */ +/*! @{ */ +#define TRNG_PKRCNT54_PKR_4_CT_MASK (0xFFFFU) +#define TRNG_PKRCNT54_PKR_4_CT_SHIFT (0U) +#define TRNG_PKRCNT54_PKR_4_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNT54_PKR_4_CT_SHIFT)) & TRNG_PKRCNT54_PKR_4_CT_MASK) +#define TRNG_PKRCNT54_PKR_5_CT_MASK (0xFFFF0000U) +#define TRNG_PKRCNT54_PKR_5_CT_SHIFT (16U) +#define TRNG_PKRCNT54_PKR_5_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNT54_PKR_5_CT_SHIFT)) & TRNG_PKRCNT54_PKR_5_CT_MASK) +/*! @} */ + +/*! @name PKRCNT76 - Statistical Check Poker Count 7 and 6 Register */ +/*! @{ */ +#define TRNG_PKRCNT76_PKR_6_CT_MASK (0xFFFFU) +#define TRNG_PKRCNT76_PKR_6_CT_SHIFT (0U) +#define TRNG_PKRCNT76_PKR_6_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNT76_PKR_6_CT_SHIFT)) & TRNG_PKRCNT76_PKR_6_CT_MASK) +#define TRNG_PKRCNT76_PKR_7_CT_MASK (0xFFFF0000U) +#define TRNG_PKRCNT76_PKR_7_CT_SHIFT (16U) +#define TRNG_PKRCNT76_PKR_7_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNT76_PKR_7_CT_SHIFT)) & TRNG_PKRCNT76_PKR_7_CT_MASK) +/*! @} */ + +/*! @name PKRCNT98 - Statistical Check Poker Count 9 and 8 Register */ +/*! @{ */ +#define TRNG_PKRCNT98_PKR_8_CT_MASK (0xFFFFU) +#define TRNG_PKRCNT98_PKR_8_CT_SHIFT (0U) +#define TRNG_PKRCNT98_PKR_8_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNT98_PKR_8_CT_SHIFT)) & TRNG_PKRCNT98_PKR_8_CT_MASK) +#define TRNG_PKRCNT98_PKR_9_CT_MASK (0xFFFF0000U) +#define TRNG_PKRCNT98_PKR_9_CT_SHIFT (16U) +#define TRNG_PKRCNT98_PKR_9_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNT98_PKR_9_CT_SHIFT)) & TRNG_PKRCNT98_PKR_9_CT_MASK) +/*! @} */ + +/*! @name PKRCNTBA - Statistical Check Poker Count B and A Register */ +/*! @{ */ +#define TRNG_PKRCNTBA_PKR_A_CT_MASK (0xFFFFU) +#define TRNG_PKRCNTBA_PKR_A_CT_SHIFT (0U) +#define TRNG_PKRCNTBA_PKR_A_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNTBA_PKR_A_CT_SHIFT)) & TRNG_PKRCNTBA_PKR_A_CT_MASK) +#define TRNG_PKRCNTBA_PKR_B_CT_MASK (0xFFFF0000U) +#define TRNG_PKRCNTBA_PKR_B_CT_SHIFT (16U) +#define TRNG_PKRCNTBA_PKR_B_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNTBA_PKR_B_CT_SHIFT)) & TRNG_PKRCNTBA_PKR_B_CT_MASK) +/*! @} */ + +/*! @name PKRCNTDC - Statistical Check Poker Count D and C Register */ +/*! @{ */ +#define TRNG_PKRCNTDC_PKR_C_CT_MASK (0xFFFFU) +#define TRNG_PKRCNTDC_PKR_C_CT_SHIFT (0U) +#define TRNG_PKRCNTDC_PKR_C_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNTDC_PKR_C_CT_SHIFT)) & TRNG_PKRCNTDC_PKR_C_CT_MASK) +#define TRNG_PKRCNTDC_PKR_D_CT_MASK (0xFFFF0000U) +#define TRNG_PKRCNTDC_PKR_D_CT_SHIFT (16U) +#define TRNG_PKRCNTDC_PKR_D_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNTDC_PKR_D_CT_SHIFT)) & TRNG_PKRCNTDC_PKR_D_CT_MASK) +/*! @} */ + +/*! @name PKRCNTFE - Statistical Check Poker Count F and E Register */ +/*! @{ */ +#define TRNG_PKRCNTFE_PKR_E_CT_MASK (0xFFFFU) +#define TRNG_PKRCNTFE_PKR_E_CT_SHIFT (0U) +#define TRNG_PKRCNTFE_PKR_E_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNTFE_PKR_E_CT_SHIFT)) & TRNG_PKRCNTFE_PKR_E_CT_MASK) +#define TRNG_PKRCNTFE_PKR_F_CT_MASK (0xFFFF0000U) +#define TRNG_PKRCNTFE_PKR_F_CT_SHIFT (16U) +#define TRNG_PKRCNTFE_PKR_F_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNTFE_PKR_F_CT_SHIFT)) & TRNG_PKRCNTFE_PKR_F_CT_MASK) +/*! @} */ + +/*! @name SEC_CFG - Security Configuration Register */ +/*! @{ */ +#define TRNG_SEC_CFG_UNUSED0_MASK (0x1U) +#define TRNG_SEC_CFG_UNUSED0_SHIFT (0U) +#define TRNG_SEC_CFG_UNUSED0(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SEC_CFG_UNUSED0_SHIFT)) & TRNG_SEC_CFG_UNUSED0_MASK) +#define TRNG_SEC_CFG_NO_PRGM_MASK (0x2U) +#define TRNG_SEC_CFG_NO_PRGM_SHIFT (1U) +/*! NO_PRGM + * 0b0..Programability of registers controlled only by the Miscellaneous Control Register's access mode bit. + * 0b1..Overides Miscellaneous Control Register access mode and prevents TRNG register programming. + */ +#define TRNG_SEC_CFG_NO_PRGM(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SEC_CFG_NO_PRGM_SHIFT)) & TRNG_SEC_CFG_NO_PRGM_MASK) +#define TRNG_SEC_CFG_UNUSED2_MASK (0x4U) +#define TRNG_SEC_CFG_UNUSED2_SHIFT (2U) +#define TRNG_SEC_CFG_UNUSED2(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SEC_CFG_UNUSED2_SHIFT)) & TRNG_SEC_CFG_UNUSED2_MASK) +/*! @} */ + +/*! @name INT_CTRL - Interrupt Control Register */ +/*! @{ */ +#define TRNG_INT_CTRL_HW_ERR_MASK (0x1U) +#define TRNG_INT_CTRL_HW_ERR_SHIFT (0U) +/*! HW_ERR + * 0b0..Corresponding bit of INT_STATUS register cleared. + * 0b1..Corresponding bit of INT_STATUS register active. + */ +#define TRNG_INT_CTRL_HW_ERR(x) (((uint32_t)(((uint32_t)(x)) << TRNG_INT_CTRL_HW_ERR_SHIFT)) & TRNG_INT_CTRL_HW_ERR_MASK) +#define TRNG_INT_CTRL_ENT_VAL_MASK (0x2U) +#define TRNG_INT_CTRL_ENT_VAL_SHIFT (1U) +/*! ENT_VAL + * 0b0..Same behavior as bit 0 of this register. + * 0b1..Same behavior as bit 0 of this register. + */ +#define TRNG_INT_CTRL_ENT_VAL(x) (((uint32_t)(((uint32_t)(x)) << TRNG_INT_CTRL_ENT_VAL_SHIFT)) & TRNG_INT_CTRL_ENT_VAL_MASK) +#define TRNG_INT_CTRL_FRQ_CT_FAIL_MASK (0x4U) +#define TRNG_INT_CTRL_FRQ_CT_FAIL_SHIFT (2U) +/*! FRQ_CT_FAIL + * 0b0..Same behavior as bit 0 of this register. + * 0b1..Same behavior as bit 0 of this register. + */ +#define TRNG_INT_CTRL_FRQ_CT_FAIL(x) (((uint32_t)(((uint32_t)(x)) << TRNG_INT_CTRL_FRQ_CT_FAIL_SHIFT)) & TRNG_INT_CTRL_FRQ_CT_FAIL_MASK) +#define TRNG_INT_CTRL_UNUSED_MASK (0xFFFFFFF8U) +#define TRNG_INT_CTRL_UNUSED_SHIFT (3U) +#define TRNG_INT_CTRL_UNUSED(x) (((uint32_t)(((uint32_t)(x)) << TRNG_INT_CTRL_UNUSED_SHIFT)) & TRNG_INT_CTRL_UNUSED_MASK) +/*! @} */ + +/*! @name INT_MASK - Mask Register */ +/*! @{ */ +#define TRNG_INT_MASK_HW_ERR_MASK (0x1U) +#define TRNG_INT_MASK_HW_ERR_SHIFT (0U) +/*! HW_ERR + * 0b0..Corresponding interrupt of INT_STATUS is masked. + * 0b1..Corresponding bit of INT_STATUS is active. + */ +#define TRNG_INT_MASK_HW_ERR(x) (((uint32_t)(((uint32_t)(x)) << TRNG_INT_MASK_HW_ERR_SHIFT)) & TRNG_INT_MASK_HW_ERR_MASK) +#define TRNG_INT_MASK_ENT_VAL_MASK (0x2U) +#define TRNG_INT_MASK_ENT_VAL_SHIFT (1U) +/*! ENT_VAL + * 0b0..Same behavior as bit 0 of this register. + * 0b1..Same behavior as bit 0 of this register. + */ +#define TRNG_INT_MASK_ENT_VAL(x) (((uint32_t)(((uint32_t)(x)) << TRNG_INT_MASK_ENT_VAL_SHIFT)) & TRNG_INT_MASK_ENT_VAL_MASK) +#define TRNG_INT_MASK_FRQ_CT_FAIL_MASK (0x4U) +#define TRNG_INT_MASK_FRQ_CT_FAIL_SHIFT (2U) +/*! FRQ_CT_FAIL + * 0b0..Same behavior as bit 0 of this register. + * 0b1..Same behavior as bit 0 of this register. + */ +#define TRNG_INT_MASK_FRQ_CT_FAIL(x) (((uint32_t)(((uint32_t)(x)) << TRNG_INT_MASK_FRQ_CT_FAIL_SHIFT)) & TRNG_INT_MASK_FRQ_CT_FAIL_MASK) +/*! @} */ + +/*! @name INT_STATUS - Interrupt Status Register */ +/*! @{ */ +#define TRNG_INT_STATUS_HW_ERR_MASK (0x1U) +#define TRNG_INT_STATUS_HW_ERR_SHIFT (0U) +/*! HW_ERR + * 0b0..no error + * 0b1..error detected. + */ +#define TRNG_INT_STATUS_HW_ERR(x) (((uint32_t)(((uint32_t)(x)) << TRNG_INT_STATUS_HW_ERR_SHIFT)) & TRNG_INT_STATUS_HW_ERR_MASK) +#define TRNG_INT_STATUS_ENT_VAL_MASK (0x2U) +#define TRNG_INT_STATUS_ENT_VAL_SHIFT (1U) +/*! ENT_VAL + * 0b0..Busy generation entropy. Any value read is invalid. + * 0b1..TRNG can be stopped and entropy is valid if read. + */ +#define TRNG_INT_STATUS_ENT_VAL(x) (((uint32_t)(((uint32_t)(x)) << TRNG_INT_STATUS_ENT_VAL_SHIFT)) & TRNG_INT_STATUS_ENT_VAL_MASK) +#define TRNG_INT_STATUS_FRQ_CT_FAIL_MASK (0x4U) +#define TRNG_INT_STATUS_FRQ_CT_FAIL_SHIFT (2U) +/*! FRQ_CT_FAIL + * 0b0..No hardware nor self test frequency errors. + * 0b1..The frequency counter has detected a failure. + */ +#define TRNG_INT_STATUS_FRQ_CT_FAIL(x) (((uint32_t)(((uint32_t)(x)) << TRNG_INT_STATUS_FRQ_CT_FAIL_SHIFT)) & TRNG_INT_STATUS_FRQ_CT_FAIL_MASK) +/*! @} */ + +/*! @name VID1 - Version ID Register (MS) */ +/*! @{ */ +#define TRNG_VID1_MIN_REV_MASK (0xFFU) +#define TRNG_VID1_MIN_REV_SHIFT (0U) +/*! MIN_REV + * 0b00000000..Minor revision number for TRNG. + */ +#define TRNG_VID1_MIN_REV(x) (((uint32_t)(((uint32_t)(x)) << TRNG_VID1_MIN_REV_SHIFT)) & TRNG_VID1_MIN_REV_MASK) +#define TRNG_VID1_MAJ_REV_MASK (0xFF00U) +#define TRNG_VID1_MAJ_REV_SHIFT (8U) +/*! MAJ_REV + * 0b00000001..Major revision number for TRNG. + */ +#define TRNG_VID1_MAJ_REV(x) (((uint32_t)(((uint32_t)(x)) << TRNG_VID1_MAJ_REV_SHIFT)) & TRNG_VID1_MAJ_REV_MASK) +#define TRNG_VID1_IP_ID_MASK (0xFFFF0000U) +#define TRNG_VID1_IP_ID_SHIFT (16U) +/*! IP_ID + * 0b0000000000110000..ID for TRNG. + */ +#define TRNG_VID1_IP_ID(x) (((uint32_t)(((uint32_t)(x)) << TRNG_VID1_IP_ID_SHIFT)) & TRNG_VID1_IP_ID_MASK) +/*! @} */ + +/*! @name VID2 - Version ID Register (LS) */ +/*! @{ */ +#define TRNG_VID2_CONFIG_OPT_MASK (0xFFU) +#define TRNG_VID2_CONFIG_OPT_SHIFT (0U) +/*! CONFIG_OPT + * 0b00000000..TRNG_CONFIG_OPT for TRNG. + */ +#define TRNG_VID2_CONFIG_OPT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_VID2_CONFIG_OPT_SHIFT)) & TRNG_VID2_CONFIG_OPT_MASK) +#define TRNG_VID2_ECO_REV_MASK (0xFF00U) +#define TRNG_VID2_ECO_REV_SHIFT (8U) +/*! ECO_REV + * 0b00000000..TRNG_ECO_REV for TRNG. + */ +#define TRNG_VID2_ECO_REV(x) (((uint32_t)(((uint32_t)(x)) << TRNG_VID2_ECO_REV_SHIFT)) & TRNG_VID2_ECO_REV_MASK) +#define TRNG_VID2_INTG_OPT_MASK (0xFF0000U) +#define TRNG_VID2_INTG_OPT_SHIFT (16U) +/*! INTG_OPT + * 0b00000000..INTG_OPT for TRNG. + */ +#define TRNG_VID2_INTG_OPT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_VID2_INTG_OPT_SHIFT)) & TRNG_VID2_INTG_OPT_MASK) +#define TRNG_VID2_ERA_MASK (0xFF000000U) +#define TRNG_VID2_ERA_SHIFT (24U) +/*! ERA + * 0b00000000..COMPILE_OPT for TRNG. + */ +#define TRNG_VID2_ERA(x) (((uint32_t)(((uint32_t)(x)) << TRNG_VID2_ERA_SHIFT)) & TRNG_VID2_ERA_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group TRNG_Register_Masks */ + + +/* TRNG - Peripheral instance base addresses */ +/** Peripheral TRNG base address */ +#define TRNG_BASE (0x400CC000u) +/** Peripheral TRNG base pointer */ +#define TRNG ((TRNG_Type *)TRNG_BASE) +/** Array initializer of TRNG peripheral base addresses */ +#define TRNG_BASE_ADDRS { TRNG_BASE } +/** Array initializer of TRNG peripheral base pointers */ +#define TRNG_BASE_PTRS { TRNG } +/** Interrupt vectors for the TRNG peripheral type */ +#define TRNG_IRQS { TRNG_IRQn } + +/*! + * @} + */ /* end of group TRNG_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- TSC Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup TSC_Peripheral_Access_Layer TSC Peripheral Access Layer + * @{ + */ + +/** TSC - Register Layout Typedef */ +typedef struct { + __IO uint32_t BASIC_SETTING; /**< , offset: 0x0 */ + uint8_t RESERVED_0[12]; + __IO uint32_t PRE_CHARGE_TIME; /**< , offset: 0x10 */ + uint8_t RESERVED_1[12]; + __IO uint32_t FLOW_CONTROL; /**< Flow Control, offset: 0x20 */ + uint8_t RESERVED_2[12]; + __I uint32_t MEASEURE_VALUE; /**< Measure Value, offset: 0x30 */ + uint8_t RESERVED_3[12]; + __IO uint32_t INT_EN; /**< Interrupt Enable, offset: 0x40 */ + uint8_t RESERVED_4[12]; + __IO uint32_t INT_SIG_EN; /**< Interrupt Signal Enable, offset: 0x50 */ + uint8_t RESERVED_5[12]; + __IO uint32_t INT_STATUS; /**< Intterrupt Status, offset: 0x60 */ + uint8_t RESERVED_6[12]; + __IO uint32_t DEBUG_MODE; /**< , offset: 0x70 */ + uint8_t RESERVED_7[12]; + __IO uint32_t DEBUG_MODE2; /**< , offset: 0x80 */ +} TSC_Type; + +/* ---------------------------------------------------------------------------- + -- TSC Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup TSC_Register_Masks TSC Register Masks + * @{ + */ + +/*! @name BASIC_SETTING - */ +/*! @{ */ +#define TSC_BASIC_SETTING_AUTO_MEASURE_MASK (0x1U) +#define TSC_BASIC_SETTING_AUTO_MEASURE_SHIFT (0U) +/*! AUTO_MEASURE - Auto Measure + * 0b0..Disable Auto Measure + * 0b1..Auto Measure + */ +#define TSC_BASIC_SETTING_AUTO_MEASURE(x) (((uint32_t)(((uint32_t)(x)) << TSC_BASIC_SETTING_AUTO_MEASURE_SHIFT)) & TSC_BASIC_SETTING_AUTO_MEASURE_MASK) +#define TSC_BASIC_SETTING_4_5_WIRE_MASK (0x10U) +#define TSC_BASIC_SETTING_4_5_WIRE_SHIFT (4U) +/*! 4_5_WIRE - 4/5 Wire detection + * 0b0..4-Wire Detection Mode + * 0b1..5-Wire Detection Mode + */ +#define TSC_BASIC_SETTING_4_5_WIRE(x) (((uint32_t)(((uint32_t)(x)) << TSC_BASIC_SETTING_4_5_WIRE_SHIFT)) & TSC_BASIC_SETTING_4_5_WIRE_MASK) +#define TSC_BASIC_SETTING_MEASURE_DELAY_TIME_MASK (0xFFFFFF00U) +#define TSC_BASIC_SETTING_MEASURE_DELAY_TIME_SHIFT (8U) +#define TSC_BASIC_SETTING_MEASURE_DELAY_TIME(x) (((uint32_t)(((uint32_t)(x)) << TSC_BASIC_SETTING_MEASURE_DELAY_TIME_SHIFT)) & TSC_BASIC_SETTING_MEASURE_DELAY_TIME_MASK) +/*! @} */ + +/*! @name PRE_CHARGE_TIME - */ +/*! @{ */ +#define TSC_PRE_CHARGE_TIME_PRE_CHARGE_TIME_MASK (0xFFFFFFFFU) +#define TSC_PRE_CHARGE_TIME_PRE_CHARGE_TIME_SHIFT (0U) +#define TSC_PRE_CHARGE_TIME_PRE_CHARGE_TIME(x) (((uint32_t)(((uint32_t)(x)) << TSC_PRE_CHARGE_TIME_PRE_CHARGE_TIME_SHIFT)) & TSC_PRE_CHARGE_TIME_PRE_CHARGE_TIME_MASK) +/*! @} */ + +/*! @name FLOW_CONTROL - Flow Control */ +/*! @{ */ +#define TSC_FLOW_CONTROL_SW_RST_MASK (0x1U) +#define TSC_FLOW_CONTROL_SW_RST_SHIFT (0U) +#define TSC_FLOW_CONTROL_SW_RST(x) (((uint32_t)(((uint32_t)(x)) << TSC_FLOW_CONTROL_SW_RST_SHIFT)) & TSC_FLOW_CONTROL_SW_RST_MASK) +#define TSC_FLOW_CONTROL_START_MEASURE_MASK (0x10U) +#define TSC_FLOW_CONTROL_START_MEASURE_SHIFT (4U) +/*! START_MEASURE - Start Measure + * 0b0..Do not start measure for now + * 0b1..Start measure the X/Y coordinate value + */ +#define TSC_FLOW_CONTROL_START_MEASURE(x) (((uint32_t)(((uint32_t)(x)) << TSC_FLOW_CONTROL_START_MEASURE_SHIFT)) & TSC_FLOW_CONTROL_START_MEASURE_MASK) +#define TSC_FLOW_CONTROL_DROP_MEASURE_MASK (0x100U) +#define TSC_FLOW_CONTROL_DROP_MEASURE_SHIFT (8U) +/*! DROP_MEASURE - Drop Measure + * 0b0..Do not drop measure for now + * 0b1..Drop the measure and controller return to idle status + */ +#define TSC_FLOW_CONTROL_DROP_MEASURE(x) (((uint32_t)(((uint32_t)(x)) << TSC_FLOW_CONTROL_DROP_MEASURE_SHIFT)) & TSC_FLOW_CONTROL_DROP_MEASURE_MASK) +#define TSC_FLOW_CONTROL_START_SENSE_MASK (0x1000U) +#define TSC_FLOW_CONTROL_START_SENSE_SHIFT (12U) +/*! START_SENSE - Start Sense + * 0b0..Stay at idle status + * 0b1..Start sense detection and (if auto_measure set to 1) measure after detect a touch + */ +#define TSC_FLOW_CONTROL_START_SENSE(x) (((uint32_t)(((uint32_t)(x)) << TSC_FLOW_CONTROL_START_SENSE_SHIFT)) & TSC_FLOW_CONTROL_START_SENSE_MASK) +#define TSC_FLOW_CONTROL_DISABLE_MASK (0x10000U) +#define TSC_FLOW_CONTROL_DISABLE_SHIFT (16U) +/*! DISABLE + * 0b0..Leave HW state machine control + * 0b1..SW set to idle status + */ +#define TSC_FLOW_CONTROL_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << TSC_FLOW_CONTROL_DISABLE_SHIFT)) & TSC_FLOW_CONTROL_DISABLE_MASK) +/*! @} */ + +/*! @name MEASEURE_VALUE - Measure Value */ +/*! @{ */ +#define TSC_MEASEURE_VALUE_Y_VALUE_MASK (0xFFFU) +#define TSC_MEASEURE_VALUE_Y_VALUE_SHIFT (0U) +#define TSC_MEASEURE_VALUE_Y_VALUE(x) (((uint32_t)(((uint32_t)(x)) << TSC_MEASEURE_VALUE_Y_VALUE_SHIFT)) & TSC_MEASEURE_VALUE_Y_VALUE_MASK) +#define TSC_MEASEURE_VALUE_X_VALUE_MASK (0xFFF0000U) +#define TSC_MEASEURE_VALUE_X_VALUE_SHIFT (16U) +#define TSC_MEASEURE_VALUE_X_VALUE(x) (((uint32_t)(((uint32_t)(x)) << TSC_MEASEURE_VALUE_X_VALUE_SHIFT)) & TSC_MEASEURE_VALUE_X_VALUE_MASK) +/*! @} */ + +/*! @name INT_EN - Interrupt Enable */ +/*! @{ */ +#define TSC_INT_EN_MEASURE_INT_EN_MASK (0x1U) +#define TSC_INT_EN_MEASURE_INT_EN_SHIFT (0U) +/*! MEASURE_INT_EN - Measure Interrupt Enable + * 0b0..Disable measure interrupt + * 0b1..Enable measure interrupt + */ +#define TSC_INT_EN_MEASURE_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << TSC_INT_EN_MEASURE_INT_EN_SHIFT)) & TSC_INT_EN_MEASURE_INT_EN_MASK) +#define TSC_INT_EN_DETECT_INT_EN_MASK (0x10U) +#define TSC_INT_EN_DETECT_INT_EN_SHIFT (4U) +/*! DETECT_INT_EN - Detect Interrupt Enable + * 0b0..Disable detect interrupt + * 0b1..Enable detect interrupt + */ +#define TSC_INT_EN_DETECT_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << TSC_INT_EN_DETECT_INT_EN_SHIFT)) & TSC_INT_EN_DETECT_INT_EN_MASK) +#define TSC_INT_EN_IDLE_SW_INT_EN_MASK (0x1000U) +#define TSC_INT_EN_IDLE_SW_INT_EN_SHIFT (12U) +/*! IDLE_SW_INT_EN - Idle Software Interrupt Enable + * 0b0..Disable idle software interrupt + * 0b1..Enable idle software interrupt + */ +#define TSC_INT_EN_IDLE_SW_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << TSC_INT_EN_IDLE_SW_INT_EN_SHIFT)) & TSC_INT_EN_IDLE_SW_INT_EN_MASK) +/*! @} */ + +/*! @name INT_SIG_EN - Interrupt Signal Enable */ +/*! @{ */ +#define TSC_INT_SIG_EN_MEASURE_SIG_EN_MASK (0x1U) +#define TSC_INT_SIG_EN_MEASURE_SIG_EN_SHIFT (0U) +#define TSC_INT_SIG_EN_MEASURE_SIG_EN(x) (((uint32_t)(((uint32_t)(x)) << TSC_INT_SIG_EN_MEASURE_SIG_EN_SHIFT)) & TSC_INT_SIG_EN_MEASURE_SIG_EN_MASK) +#define TSC_INT_SIG_EN_DETECT_SIG_EN_MASK (0x10U) +#define TSC_INT_SIG_EN_DETECT_SIG_EN_SHIFT (4U) +/*! DETECT_SIG_EN - Detect Signal Enable + * 0b0..Disable detect signal + * 0b1..Enable detect signal + */ +#define TSC_INT_SIG_EN_DETECT_SIG_EN(x) (((uint32_t)(((uint32_t)(x)) << TSC_INT_SIG_EN_DETECT_SIG_EN_SHIFT)) & TSC_INT_SIG_EN_DETECT_SIG_EN_MASK) +#define TSC_INT_SIG_EN_VALID_SIG_EN_MASK (0x100U) +#define TSC_INT_SIG_EN_VALID_SIG_EN_SHIFT (8U) +/*! VALID_SIG_EN - Valid Signal Enable + * 0b0..Disable valid signal + * 0b1..Enable valid signal + */ +#define TSC_INT_SIG_EN_VALID_SIG_EN(x) (((uint32_t)(((uint32_t)(x)) << TSC_INT_SIG_EN_VALID_SIG_EN_SHIFT)) & TSC_INT_SIG_EN_VALID_SIG_EN_MASK) +#define TSC_INT_SIG_EN_IDLE_SW_SIG_EN_MASK (0x1000U) +#define TSC_INT_SIG_EN_IDLE_SW_SIG_EN_SHIFT (12U) +/*! IDLE_SW_SIG_EN - Idle Software Signal Enable + * 0b0..Disable idle software signal + * 0b1..Enable idle software signal + */ +#define TSC_INT_SIG_EN_IDLE_SW_SIG_EN(x) (((uint32_t)(((uint32_t)(x)) << TSC_INT_SIG_EN_IDLE_SW_SIG_EN_SHIFT)) & TSC_INT_SIG_EN_IDLE_SW_SIG_EN_MASK) +/*! @} */ + +/*! @name INT_STATUS - Intterrupt Status */ +/*! @{ */ +#define TSC_INT_STATUS_MEASURE_MASK (0x1U) +#define TSC_INT_STATUS_MEASURE_SHIFT (0U) +/*! MEASURE - Measure Signal + * 0b0..Does not exist a measure signal + * 0b1..Exist a measure signal + */ +#define TSC_INT_STATUS_MEASURE(x) (((uint32_t)(((uint32_t)(x)) << TSC_INT_STATUS_MEASURE_SHIFT)) & TSC_INT_STATUS_MEASURE_MASK) +#define TSC_INT_STATUS_DETECT_MASK (0x10U) +#define TSC_INT_STATUS_DETECT_SHIFT (4U) +/*! DETECT - Detect Signal + * 0b0..Does not exist a detect signal + * 0b1..Exist detect signal + */ +#define TSC_INT_STATUS_DETECT(x) (((uint32_t)(((uint32_t)(x)) << TSC_INT_STATUS_DETECT_SHIFT)) & TSC_INT_STATUS_DETECT_MASK) +#define TSC_INT_STATUS_VALID_MASK (0x100U) +#define TSC_INT_STATUS_VALID_SHIFT (8U) +/*! VALID - Valid Signal + * 0b0..There is no touch detected after measurement, indicates that the measured value is not valid + * 0b1..There is touch detection after measurement, indicates that the measure is valid + */ +#define TSC_INT_STATUS_VALID(x) (((uint32_t)(((uint32_t)(x)) << TSC_INT_STATUS_VALID_SHIFT)) & TSC_INT_STATUS_VALID_MASK) +#define TSC_INT_STATUS_IDLE_SW_MASK (0x1000U) +#define TSC_INT_STATUS_IDLE_SW_SHIFT (12U) +/*! IDLE_SW - Idle Software + * 0b0..Haven't return to idle status + * 0b1..Already return to idle status + */ +#define TSC_INT_STATUS_IDLE_SW(x) (((uint32_t)(((uint32_t)(x)) << TSC_INT_STATUS_IDLE_SW_SHIFT)) & TSC_INT_STATUS_IDLE_SW_MASK) +/*! @} */ + +/*! @name DEBUG_MODE - */ +/*! @{ */ +#define TSC_DEBUG_MODE_ADC_CONV_VALUE_MASK (0xFFFU) +#define TSC_DEBUG_MODE_ADC_CONV_VALUE_SHIFT (0U) +#define TSC_DEBUG_MODE_ADC_CONV_VALUE(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE_ADC_CONV_VALUE_SHIFT)) & TSC_DEBUG_MODE_ADC_CONV_VALUE_MASK) +#define TSC_DEBUG_MODE_ADC_COCO_MASK (0x1000U) +#define TSC_DEBUG_MODE_ADC_COCO_SHIFT (12U) +#define TSC_DEBUG_MODE_ADC_COCO(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE_ADC_COCO_SHIFT)) & TSC_DEBUG_MODE_ADC_COCO_MASK) +#define TSC_DEBUG_MODE_EXT_HWTS_MASK (0x1F0000U) +#define TSC_DEBUG_MODE_EXT_HWTS_SHIFT (16U) +#define TSC_DEBUG_MODE_EXT_HWTS(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE_EXT_HWTS_SHIFT)) & TSC_DEBUG_MODE_EXT_HWTS_MASK) +#define TSC_DEBUG_MODE_TRIGGER_MASK (0x1000000U) +#define TSC_DEBUG_MODE_TRIGGER_SHIFT (24U) +/*! TRIGGER - Trigger + * 0b0..No hardware trigger signal + * 0b1..Hardware trigger signal, the signal must last at least 1 ips clock period + */ +#define TSC_DEBUG_MODE_TRIGGER(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE_TRIGGER_SHIFT)) & TSC_DEBUG_MODE_TRIGGER_MASK) +#define TSC_DEBUG_MODE_ADC_COCO_CLEAR_MASK (0x2000000U) +#define TSC_DEBUG_MODE_ADC_COCO_CLEAR_SHIFT (25U) +/*! ADC_COCO_CLEAR - ADC Coco Clear + * 0b0..No ADC COCO clear + * 0b1..Set ADC COCO clear + */ +#define TSC_DEBUG_MODE_ADC_COCO_CLEAR(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE_ADC_COCO_CLEAR_SHIFT)) & TSC_DEBUG_MODE_ADC_COCO_CLEAR_MASK) +#define TSC_DEBUG_MODE_ADC_COCO_CLEAR_DISABLE_MASK (0x4000000U) +#define TSC_DEBUG_MODE_ADC_COCO_CLEAR_DISABLE_SHIFT (26U) +/*! ADC_COCO_CLEAR_DISABLE - ADC COCO Clear Disable + * 0b0..Allow TSC hardware generates ADC COCO clear + * 0b1..Prevent TSC from generate ADC COCO clear signal + */ +#define TSC_DEBUG_MODE_ADC_COCO_CLEAR_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE_ADC_COCO_CLEAR_DISABLE_SHIFT)) & TSC_DEBUG_MODE_ADC_COCO_CLEAR_DISABLE_MASK) +#define TSC_DEBUG_MODE_DEBUG_EN_MASK (0x10000000U) +#define TSC_DEBUG_MODE_DEBUG_EN_SHIFT (28U) +/*! DEBUG_EN - Debug Enable + * 0b0..Enable debug mode + * 0b1..Disable debug mode + */ +#define TSC_DEBUG_MODE_DEBUG_EN(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE_DEBUG_EN_SHIFT)) & TSC_DEBUG_MODE_DEBUG_EN_MASK) +/*! @} */ + +/*! @name DEBUG_MODE2 - */ +/*! @{ */ +#define TSC_DEBUG_MODE2_XPUL_PULL_DOWN_MASK (0x1U) +#define TSC_DEBUG_MODE2_XPUL_PULL_DOWN_SHIFT (0U) +/*! XPUL_PULL_DOWN - XPUL Wire Pull Down Switch + * 0b0..Close the switch + * 0b1..Open up the switch + */ +#define TSC_DEBUG_MODE2_XPUL_PULL_DOWN(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE2_XPUL_PULL_DOWN_SHIFT)) & TSC_DEBUG_MODE2_XPUL_PULL_DOWN_MASK) +#define TSC_DEBUG_MODE2_XPUL_PULL_UP_MASK (0x2U) +#define TSC_DEBUG_MODE2_XPUL_PULL_UP_SHIFT (1U) +/*! XPUL_PULL_UP - XPUL Wire Pull Up Switch + * 0b0..Close the switch + * 0b1..Open up the switch + */ +#define TSC_DEBUG_MODE2_XPUL_PULL_UP(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE2_XPUL_PULL_UP_SHIFT)) & TSC_DEBUG_MODE2_XPUL_PULL_UP_MASK) +#define TSC_DEBUG_MODE2_XPUL_200K_PULL_UP_MASK (0x4U) +#define TSC_DEBUG_MODE2_XPUL_200K_PULL_UP_SHIFT (2U) +/*! XPUL_200K_PULL_UP - XPUL Wire 200K Pull Up Switch + * 0b0..Close the switch + * 0b1..Open up the switch + */ +#define TSC_DEBUG_MODE2_XPUL_200K_PULL_UP(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE2_XPUL_200K_PULL_UP_SHIFT)) & TSC_DEBUG_MODE2_XPUL_200K_PULL_UP_MASK) +#define TSC_DEBUG_MODE2_XNUR_PULL_DOWN_MASK (0x8U) +#define TSC_DEBUG_MODE2_XNUR_PULL_DOWN_SHIFT (3U) +/*! XNUR_PULL_DOWN - XNUR Wire Pull Down Switch + * 0b0..Close the switch + * 0b1..Open up the switch + */ +#define TSC_DEBUG_MODE2_XNUR_PULL_DOWN(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE2_XNUR_PULL_DOWN_SHIFT)) & TSC_DEBUG_MODE2_XNUR_PULL_DOWN_MASK) +#define TSC_DEBUG_MODE2_XNUR_PULL_UP_MASK (0x10U) +#define TSC_DEBUG_MODE2_XNUR_PULL_UP_SHIFT (4U) +/*! XNUR_PULL_UP - XNUR Wire Pull Up Switch + * 0b0..Close the switch + * 0b1..Open up the switch + */ +#define TSC_DEBUG_MODE2_XNUR_PULL_UP(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE2_XNUR_PULL_UP_SHIFT)) & TSC_DEBUG_MODE2_XNUR_PULL_UP_MASK) +#define TSC_DEBUG_MODE2_XNUR_200K_PULL_UP_MASK (0x20U) +#define TSC_DEBUG_MODE2_XNUR_200K_PULL_UP_SHIFT (5U) +/*! XNUR_200K_PULL_UP - XNUR Wire 200K Pull Up Switch + * 0b0..Close the switch + * 0b1..Open up the switch + */ +#define TSC_DEBUG_MODE2_XNUR_200K_PULL_UP(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE2_XNUR_200K_PULL_UP_SHIFT)) & TSC_DEBUG_MODE2_XNUR_200K_PULL_UP_MASK) +#define TSC_DEBUG_MODE2_YPLL_PULL_DOWN_MASK (0x40U) +#define TSC_DEBUG_MODE2_YPLL_PULL_DOWN_SHIFT (6U) +/*! YPLL_PULL_DOWN - YPLL Wire Pull Down Switch + * 0b0..Close the switch + * 0b1..Open up the switch + */ +#define TSC_DEBUG_MODE2_YPLL_PULL_DOWN(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE2_YPLL_PULL_DOWN_SHIFT)) & TSC_DEBUG_MODE2_YPLL_PULL_DOWN_MASK) +#define TSC_DEBUG_MODE2_YPLL_PULL_UP_MASK (0x80U) +#define TSC_DEBUG_MODE2_YPLL_PULL_UP_SHIFT (7U) +/*! YPLL_PULL_UP - YPLL Wire Pull Up Switch + * 0b0..Close the switch + * 0b1..Open the switch + */ +#define TSC_DEBUG_MODE2_YPLL_PULL_UP(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE2_YPLL_PULL_UP_SHIFT)) & TSC_DEBUG_MODE2_YPLL_PULL_UP_MASK) +#define TSC_DEBUG_MODE2_YPLL_200K_PULL_UP_MASK (0x100U) +#define TSC_DEBUG_MODE2_YPLL_200K_PULL_UP_SHIFT (8U) +/*! YPLL_200K_PULL_UP - YPLL Wire 200K Pull Up Switch + * 0b0..Close the switch + * 0b1..Open up the switch + */ +#define TSC_DEBUG_MODE2_YPLL_200K_PULL_UP(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE2_YPLL_200K_PULL_UP_SHIFT)) & TSC_DEBUG_MODE2_YPLL_200K_PULL_UP_MASK) +#define TSC_DEBUG_MODE2_YNLR_PULL_DOWN_MASK (0x200U) +#define TSC_DEBUG_MODE2_YNLR_PULL_DOWN_SHIFT (9U) +/*! YNLR_PULL_DOWN - YNLR Wire Pull Down Switch + * 0b0..Close the switch + * 0b1..Open up the switch + */ +#define TSC_DEBUG_MODE2_YNLR_PULL_DOWN(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE2_YNLR_PULL_DOWN_SHIFT)) & TSC_DEBUG_MODE2_YNLR_PULL_DOWN_MASK) +#define TSC_DEBUG_MODE2_YNLR_PULL_UP_MASK (0x400U) +#define TSC_DEBUG_MODE2_YNLR_PULL_UP_SHIFT (10U) +/*! YNLR_PULL_UP - YNLR Wire Pull Up Switch + * 0b0..Close the switch + * 0b1..Open up the switch + */ +#define TSC_DEBUG_MODE2_YNLR_PULL_UP(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE2_YNLR_PULL_UP_SHIFT)) & TSC_DEBUG_MODE2_YNLR_PULL_UP_MASK) +#define TSC_DEBUG_MODE2_YNLR_200K_PULL_UP_MASK (0x800U) +#define TSC_DEBUG_MODE2_YNLR_200K_PULL_UP_SHIFT (11U) +/*! YNLR_200K_PULL_UP - YNLR Wire 200K Pull Up Switch + * 0b0..Close the switch + * 0b1..Open up the switch + */ +#define TSC_DEBUG_MODE2_YNLR_200K_PULL_UP(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE2_YNLR_200K_PULL_UP_SHIFT)) & TSC_DEBUG_MODE2_YNLR_200K_PULL_UP_MASK) +#define TSC_DEBUG_MODE2_WIPER_PULL_DOWN_MASK (0x1000U) +#define TSC_DEBUG_MODE2_WIPER_PULL_DOWN_SHIFT (12U) +/*! WIPER_PULL_DOWN - Wiper Wire Pull Down Switch + * 0b0..Close the switch + * 0b1..Open up the switch + */ +#define TSC_DEBUG_MODE2_WIPER_PULL_DOWN(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE2_WIPER_PULL_DOWN_SHIFT)) & TSC_DEBUG_MODE2_WIPER_PULL_DOWN_MASK) +#define TSC_DEBUG_MODE2_WIPER_PULL_UP_MASK (0x2000U) +#define TSC_DEBUG_MODE2_WIPER_PULL_UP_SHIFT (13U) +/*! WIPER_PULL_UP - Wiper Wire Pull Up Switch + * 0b0..Close the switch + * 0b1..Open up the switch + */ +#define TSC_DEBUG_MODE2_WIPER_PULL_UP(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE2_WIPER_PULL_UP_SHIFT)) & TSC_DEBUG_MODE2_WIPER_PULL_UP_MASK) +#define TSC_DEBUG_MODE2_WIPER_200K_PULL_UP_MASK (0x4000U) +#define TSC_DEBUG_MODE2_WIPER_200K_PULL_UP_SHIFT (14U) +/*! WIPER_200K_PULL_UP - Wiper Wire 200K Pull Up Switch + * 0b0..Close the switch + * 0b1..Open up the switch + */ +#define TSC_DEBUG_MODE2_WIPER_200K_PULL_UP(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE2_WIPER_200K_PULL_UP_SHIFT)) & TSC_DEBUG_MODE2_WIPER_200K_PULL_UP_MASK) +#define TSC_DEBUG_MODE2_DETECT_FOUR_WIRE_MASK (0x10000U) +#define TSC_DEBUG_MODE2_DETECT_FOUR_WIRE_SHIFT (16U) +/*! DETECT_FOUR_WIRE - Detect Four Wire + * 0b0..No detect signal + * 0b1..Yes, there is a detect on the touch screen. + */ +#define TSC_DEBUG_MODE2_DETECT_FOUR_WIRE(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE2_DETECT_FOUR_WIRE_SHIFT)) & TSC_DEBUG_MODE2_DETECT_FOUR_WIRE_MASK) +#define TSC_DEBUG_MODE2_DETECT_FIVE_WIRE_MASK (0x20000U) +#define TSC_DEBUG_MODE2_DETECT_FIVE_WIRE_SHIFT (17U) +/*! DETECT_FIVE_WIRE - Detect Five Wire + * 0b0..No detect signal + * 0b1..Yes, there is a detect on the touch screen. + */ +#define TSC_DEBUG_MODE2_DETECT_FIVE_WIRE(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE2_DETECT_FIVE_WIRE_SHIFT)) & TSC_DEBUG_MODE2_DETECT_FIVE_WIRE_MASK) +#define TSC_DEBUG_MODE2_STATE_MACHINE_MASK (0x700000U) +#define TSC_DEBUG_MODE2_STATE_MACHINE_SHIFT (20U) +/*! STATE_MACHINE - State Machine + * 0b000..Idle + * 0b001..Pre-charge + * 0b010..Detect + * 0b011..X-measure + * 0b100..Y-measure + * 0b101..Pre-charge + * 0b110..Detect + */ +#define TSC_DEBUG_MODE2_STATE_MACHINE(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE2_STATE_MACHINE_SHIFT)) & TSC_DEBUG_MODE2_STATE_MACHINE_MASK) +#define TSC_DEBUG_MODE2_INTERMEDIATE_MASK (0x800000U) +#define TSC_DEBUG_MODE2_INTERMEDIATE_SHIFT (23U) +/*! INTERMEDIATE - Intermediate State + * 0b0..Not in intermedia + * 0b1..Intermedia + */ +#define TSC_DEBUG_MODE2_INTERMEDIATE(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE2_INTERMEDIATE_SHIFT)) & TSC_DEBUG_MODE2_INTERMEDIATE_MASK) +#define TSC_DEBUG_MODE2_DETECT_ENABLE_FOUR_WIRE_MASK (0x1000000U) +#define TSC_DEBUG_MODE2_DETECT_ENABLE_FOUR_WIRE_SHIFT (24U) +/*! DETECT_ENABLE_FOUR_WIRE - Detect Enable Four Wire + * 0b0..Do not read four wire detect value, read default value from analogue + * 0b1..Read four wire detect status from analogue + */ +#define TSC_DEBUG_MODE2_DETECT_ENABLE_FOUR_WIRE(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE2_DETECT_ENABLE_FOUR_WIRE_SHIFT)) & TSC_DEBUG_MODE2_DETECT_ENABLE_FOUR_WIRE_MASK) +#define TSC_DEBUG_MODE2_DETECT_ENABLE_FIVE_WIRE_MASK (0x10000000U) +#define TSC_DEBUG_MODE2_DETECT_ENABLE_FIVE_WIRE_SHIFT (28U) +/*! DETECT_ENABLE_FIVE_WIRE - Detect Enable Five Wire + * 0b0..Do not read five wire detect value, read default value from analogue + * 0b1..Read five wire detect status from analogue + */ +#define TSC_DEBUG_MODE2_DETECT_ENABLE_FIVE_WIRE(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE2_DETECT_ENABLE_FIVE_WIRE_SHIFT)) & TSC_DEBUG_MODE2_DETECT_ENABLE_FIVE_WIRE_MASK) +#define TSC_DEBUG_MODE2_DE_GLITCH_MASK (0x60000000U) +#define TSC_DEBUG_MODE2_DE_GLITCH_SHIFT (29U) +/*! DE_GLITCH + * 0b00..Normal function: 0x1fff ipg clock cycles; Low power mode: 0x9 low power clock cycles + * 0b01..Normal function: 0xfff ipg clock cycles; Low power mode: :0x7 low power clock cycles + * 0b10..Normal function: 0x7ff ipg clock cycles; Low power mode:0x5 low power clock cycles + * 0b11..Normal function: 0x3 ipg clock cycles; Low power mode:0x3 low power clock cycles + */ +#define TSC_DEBUG_MODE2_DE_GLITCH(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE2_DE_GLITCH_SHIFT)) & TSC_DEBUG_MODE2_DE_GLITCH_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group TSC_Register_Masks */ + + +/* TSC - Peripheral instance base addresses */ +/** Peripheral TSC base address */ +#define TSC_BASE (0x400E0000u) +/** Peripheral TSC base pointer */ +#define TSC ((TSC_Type *)TSC_BASE) +/** Array initializer of TSC peripheral base addresses */ +#define TSC_BASE_ADDRS { TSC_BASE } +/** Array initializer of TSC peripheral base pointers */ +#define TSC_BASE_PTRS { TSC } +/** Interrupt vectors for the TSC peripheral type */ +#define TSC_IRQS { TSC_DIG_IRQn } +/* Backward compatibility */ +#define TSC_BASIC_SETTING__4_5_WIRE_MASK TSC_BASIC_SETTING_4_5_WIRE_MASK +#define TSC_BASIC_SETTING__4_5_WIRE_SHIFT TSC_BASIC_SETTING_4_5_WIRE_SHIFT +#define TSC_BASIC_SETTING__4_5_WIRE(x) TSC_BASIC_SETTING_4_5_WIRE(x) + + +/*! + * @} + */ /* end of group TSC_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- USB Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup USB_Peripheral_Access_Layer USB Peripheral Access Layer + * @{ + */ + +/** USB - Register Layout Typedef */ +typedef struct { + __I uint32_t ID; /**< Identification register, offset: 0x0 */ + __I uint32_t HWGENERAL; /**< Hardware General, offset: 0x4 */ + __I uint32_t HWHOST; /**< Host Hardware Parameters, offset: 0x8 */ + __I uint32_t HWDEVICE; /**< Device Hardware Parameters, offset: 0xC */ + __I uint32_t HWTXBUF; /**< TX Buffer Hardware Parameters, offset: 0x10 */ + __I uint32_t HWRXBUF; /**< RX Buffer Hardware Parameters, offset: 0x14 */ + uint8_t RESERVED_0[104]; + __IO uint32_t GPTIMER0LD; /**< General Purpose Timer #0 Load, offset: 0x80 */ + __IO uint32_t GPTIMER0CTRL; /**< General Purpose Timer #0 Controller, offset: 0x84 */ + __IO uint32_t GPTIMER1LD; /**< General Purpose Timer #1 Load, offset: 0x88 */ + __IO uint32_t GPTIMER1CTRL; /**< General Purpose Timer #1 Controller, offset: 0x8C */ + __IO uint32_t SBUSCFG; /**< System Bus Config, offset: 0x90 */ + uint8_t RESERVED_1[108]; + __I uint8_t CAPLENGTH; /**< Capability Registers Length, offset: 0x100 */ + uint8_t RESERVED_2[1]; + __I uint16_t HCIVERSION; /**< Host Controller Interface Version, offset: 0x102 */ + __I uint32_t HCSPARAMS; /**< Host Controller Structural Parameters, offset: 0x104 */ + __I uint32_t HCCPARAMS; /**< Host Controller Capability Parameters, offset: 0x108 */ + uint8_t RESERVED_3[20]; + __I uint16_t DCIVERSION; /**< Device Controller Interface Version, offset: 0x120 */ + uint8_t RESERVED_4[2]; + __I uint32_t DCCPARAMS; /**< Device Controller Capability Parameters, offset: 0x124 */ + uint8_t RESERVED_5[24]; + __IO uint32_t USBCMD; /**< USB Command Register, offset: 0x140 */ + __IO uint32_t USBSTS; /**< USB Status Register, offset: 0x144 */ + __IO uint32_t USBINTR; /**< Interrupt Enable Register, offset: 0x148 */ + __IO uint32_t FRINDEX; /**< USB Frame Index, offset: 0x14C */ + uint8_t RESERVED_6[4]; + union { /* offset: 0x154 */ + __IO uint32_t DEVICEADDR; /**< Device Address, offset: 0x154 */ + __IO uint32_t PERIODICLISTBASE; /**< Frame List Base Address, offset: 0x154 */ + }; + union { /* offset: 0x158 */ + __IO uint32_t ASYNCLISTADDR; /**< Next Asynch. Address, offset: 0x158 */ + __IO uint32_t ENDPTLISTADDR; /**< Endpoint List Address, offset: 0x158 */ + }; + uint8_t RESERVED_7[4]; + __IO uint32_t BURSTSIZE; /**< Programmable Burst Size, offset: 0x160 */ + __IO uint32_t TXFILLTUNING; /**< TX FIFO Fill Tuning, offset: 0x164 */ + uint8_t RESERVED_8[16]; + __IO uint32_t ENDPTNAK; /**< Endpoint NAK, offset: 0x178 */ + __IO uint32_t ENDPTNAKEN; /**< Endpoint NAK Enable, offset: 0x17C */ + __I uint32_t CONFIGFLAG; /**< Configure Flag Register, offset: 0x180 */ + __IO uint32_t PORTSC1; /**< Port Status & Control, offset: 0x184 */ + uint8_t RESERVED_9[28]; + __IO uint32_t OTGSC; /**< On-The-Go Status & control, offset: 0x1A4 */ + __IO uint32_t USBMODE; /**< USB Device Mode, offset: 0x1A8 */ + __IO uint32_t ENDPTSETUPSTAT; /**< Endpoint Setup Status, offset: 0x1AC */ + __IO uint32_t ENDPTPRIME; /**< Endpoint Prime, offset: 0x1B0 */ + __IO uint32_t ENDPTFLUSH; /**< Endpoint Flush, offset: 0x1B4 */ + __I uint32_t ENDPTSTAT; /**< Endpoint Status, offset: 0x1B8 */ + __IO uint32_t ENDPTCOMPLETE; /**< Endpoint Complete, offset: 0x1BC */ + __IO uint32_t ENDPTCTRL0; /**< Endpoint Control0, offset: 0x1C0 */ + __IO uint32_t ENDPTCTRL[7]; /**< Endpoint Control 1..Endpoint Control 7, array offset: 0x1C4, array step: 0x4 */ +} USB_Type; + +/* ---------------------------------------------------------------------------- + -- USB Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup USB_Register_Masks USB Register Masks + * @{ + */ + +/*! @name ID - Identification register */ +/*! @{ */ +#define USB_ID_ID_MASK (0x3FU) +#define USB_ID_ID_SHIFT (0U) +#define USB_ID_ID(x) (((uint32_t)(((uint32_t)(x)) << USB_ID_ID_SHIFT)) & USB_ID_ID_MASK) +#define USB_ID_NID_MASK (0x3F00U) +#define USB_ID_NID_SHIFT (8U) +#define USB_ID_NID(x) (((uint32_t)(((uint32_t)(x)) << USB_ID_NID_SHIFT)) & USB_ID_NID_MASK) +#define USB_ID_REVISION_MASK (0xFF0000U) +#define USB_ID_REVISION_SHIFT (16U) +#define USB_ID_REVISION(x) (((uint32_t)(((uint32_t)(x)) << USB_ID_REVISION_SHIFT)) & USB_ID_REVISION_MASK) +/*! @} */ + +/*! @name HWGENERAL - Hardware General */ +/*! @{ */ +#define USB_HWGENERAL_PHYW_MASK (0x30U) +#define USB_HWGENERAL_PHYW_SHIFT (4U) +/*! PHYW + * 0b00..8 bit wide data bus Software non-programmable + * 0b01..16 bit wide data bus Software non-programmable + * 0b10..Reset to 8 bit wide data bus Software programmable + * 0b11..Reset to 16 bit wide data bus Software programmable + */ +#define USB_HWGENERAL_PHYW(x) (((uint32_t)(((uint32_t)(x)) << USB_HWGENERAL_PHYW_SHIFT)) & USB_HWGENERAL_PHYW_MASK) +#define USB_HWGENERAL_PHYM_MASK (0x1C0U) +#define USB_HWGENERAL_PHYM_SHIFT (6U) +/*! PHYM + * 0b000..UTMI/UMTI+ + * 0b001..ULPI DDR + * 0b010..ULPI + * 0b011..Serial Only + * 0b100..Software programmable - reset to UTMI/UTMI+ + * 0b101..Software programmable - reset to ULPI DDR + * 0b110..Software programmable - reset to ULPI + * 0b111..Software programmable - reset to Serial + */ +#define USB_HWGENERAL_PHYM(x) (((uint32_t)(((uint32_t)(x)) << USB_HWGENERAL_PHYM_SHIFT)) & USB_HWGENERAL_PHYM_MASK) +#define USB_HWGENERAL_SM_MASK (0x600U) +#define USB_HWGENERAL_SM_SHIFT (9U) +/*! SM + * 0b00..No Serial Engine, always use parallel signalling. + * 0b01..Serial Engine present, always use serial signalling for FS/LS. + * 0b10..Software programmable - Reset to use parallel signalling for FS/LS + * 0b11..Software programmable - Reset to use serial signalling for FS/LS + */ +#define USB_HWGENERAL_SM(x) (((uint32_t)(((uint32_t)(x)) << USB_HWGENERAL_SM_SHIFT)) & USB_HWGENERAL_SM_MASK) +/*! @} */ + +/*! @name HWHOST - Host Hardware Parameters */ +/*! @{ */ +#define USB_HWHOST_HC_MASK (0x1U) +#define USB_HWHOST_HC_SHIFT (0U) +/*! HC + * 0b1..Supported + * 0b0..Not supported + */ +#define USB_HWHOST_HC(x) (((uint32_t)(((uint32_t)(x)) << USB_HWHOST_HC_SHIFT)) & USB_HWHOST_HC_MASK) +#define USB_HWHOST_NPORT_MASK (0xEU) +#define USB_HWHOST_NPORT_SHIFT (1U) +#define USB_HWHOST_NPORT(x) (((uint32_t)(((uint32_t)(x)) << USB_HWHOST_NPORT_SHIFT)) & USB_HWHOST_NPORT_MASK) +/*! @} */ + +/*! @name HWDEVICE - Device Hardware Parameters */ +/*! @{ */ +#define USB_HWDEVICE_DC_MASK (0x1U) +#define USB_HWDEVICE_DC_SHIFT (0U) +/*! DC + * 0b1..Supported + * 0b0..Not supported + */ +#define USB_HWDEVICE_DC(x) (((uint32_t)(((uint32_t)(x)) << USB_HWDEVICE_DC_SHIFT)) & USB_HWDEVICE_DC_MASK) +#define USB_HWDEVICE_DEVEP_MASK (0x3EU) +#define USB_HWDEVICE_DEVEP_SHIFT (1U) +#define USB_HWDEVICE_DEVEP(x) (((uint32_t)(((uint32_t)(x)) << USB_HWDEVICE_DEVEP_SHIFT)) & USB_HWDEVICE_DEVEP_MASK) +/*! @} */ + +/*! @name HWTXBUF - TX Buffer Hardware Parameters */ +/*! @{ */ +#define USB_HWTXBUF_TXBURST_MASK (0xFFU) +#define USB_HWTXBUF_TXBURST_SHIFT (0U) +#define USB_HWTXBUF_TXBURST(x) (((uint32_t)(((uint32_t)(x)) << USB_HWTXBUF_TXBURST_SHIFT)) & USB_HWTXBUF_TXBURST_MASK) +#define USB_HWTXBUF_TXCHANADD_MASK (0xFF0000U) +#define USB_HWTXBUF_TXCHANADD_SHIFT (16U) +#define USB_HWTXBUF_TXCHANADD(x) (((uint32_t)(((uint32_t)(x)) << USB_HWTXBUF_TXCHANADD_SHIFT)) & USB_HWTXBUF_TXCHANADD_MASK) +/*! @} */ + +/*! @name HWRXBUF - RX Buffer Hardware Parameters */ +/*! @{ */ +#define USB_HWRXBUF_RXBURST_MASK (0xFFU) +#define USB_HWRXBUF_RXBURST_SHIFT (0U) +#define USB_HWRXBUF_RXBURST(x) (((uint32_t)(((uint32_t)(x)) << USB_HWRXBUF_RXBURST_SHIFT)) & USB_HWRXBUF_RXBURST_MASK) +#define USB_HWRXBUF_RXADD_MASK (0xFF00U) +#define USB_HWRXBUF_RXADD_SHIFT (8U) +#define USB_HWRXBUF_RXADD(x) (((uint32_t)(((uint32_t)(x)) << USB_HWRXBUF_RXADD_SHIFT)) & USB_HWRXBUF_RXADD_MASK) +/*! @} */ + +/*! @name GPTIMER0LD - General Purpose Timer #0 Load */ +/*! @{ */ +#define USB_GPTIMER0LD_GPTLD_MASK (0xFFFFFFU) +#define USB_GPTIMER0LD_GPTLD_SHIFT (0U) +#define USB_GPTIMER0LD_GPTLD(x) (((uint32_t)(((uint32_t)(x)) << USB_GPTIMER0LD_GPTLD_SHIFT)) & USB_GPTIMER0LD_GPTLD_MASK) +/*! @} */ + +/*! @name GPTIMER0CTRL - General Purpose Timer #0 Controller */ +/*! @{ */ +#define USB_GPTIMER0CTRL_GPTCNT_MASK (0xFFFFFFU) +#define USB_GPTIMER0CTRL_GPTCNT_SHIFT (0U) +#define USB_GPTIMER0CTRL_GPTCNT(x) (((uint32_t)(((uint32_t)(x)) << USB_GPTIMER0CTRL_GPTCNT_SHIFT)) & USB_GPTIMER0CTRL_GPTCNT_MASK) +#define USB_GPTIMER0CTRL_GPTMODE_MASK (0x1000000U) +#define USB_GPTIMER0CTRL_GPTMODE_SHIFT (24U) +/*! GPTMODE + * 0b0..One Shot Mode + * 0b1..Repeat Mode + */ +#define USB_GPTIMER0CTRL_GPTMODE(x) (((uint32_t)(((uint32_t)(x)) << USB_GPTIMER0CTRL_GPTMODE_SHIFT)) & USB_GPTIMER0CTRL_GPTMODE_MASK) +#define USB_GPTIMER0CTRL_GPTRST_MASK (0x40000000U) +#define USB_GPTIMER0CTRL_GPTRST_SHIFT (30U) +/*! GPTRST + * 0b0..No action + * 0b1..Load counter value from GPTLD bits in n_GPTIMER0LD + */ +#define USB_GPTIMER0CTRL_GPTRST(x) (((uint32_t)(((uint32_t)(x)) << USB_GPTIMER0CTRL_GPTRST_SHIFT)) & USB_GPTIMER0CTRL_GPTRST_MASK) +#define USB_GPTIMER0CTRL_GPTRUN_MASK (0x80000000U) +#define USB_GPTIMER0CTRL_GPTRUN_SHIFT (31U) +/*! GPTRUN + * 0b0..Stop counting + * 0b1..Run + */ +#define USB_GPTIMER0CTRL_GPTRUN(x) (((uint32_t)(((uint32_t)(x)) << USB_GPTIMER0CTRL_GPTRUN_SHIFT)) & USB_GPTIMER0CTRL_GPTRUN_MASK) +/*! @} */ + +/*! @name GPTIMER1LD - General Purpose Timer #1 Load */ +/*! @{ */ +#define USB_GPTIMER1LD_GPTLD_MASK (0xFFFFFFU) +#define USB_GPTIMER1LD_GPTLD_SHIFT (0U) +#define USB_GPTIMER1LD_GPTLD(x) (((uint32_t)(((uint32_t)(x)) << USB_GPTIMER1LD_GPTLD_SHIFT)) & USB_GPTIMER1LD_GPTLD_MASK) +/*! @} */ + +/*! @name GPTIMER1CTRL - General Purpose Timer #1 Controller */ +/*! @{ */ +#define USB_GPTIMER1CTRL_GPTCNT_MASK (0xFFFFFFU) +#define USB_GPTIMER1CTRL_GPTCNT_SHIFT (0U) +#define USB_GPTIMER1CTRL_GPTCNT(x) (((uint32_t)(((uint32_t)(x)) << USB_GPTIMER1CTRL_GPTCNT_SHIFT)) & USB_GPTIMER1CTRL_GPTCNT_MASK) +#define USB_GPTIMER1CTRL_GPTMODE_MASK (0x1000000U) +#define USB_GPTIMER1CTRL_GPTMODE_SHIFT (24U) +/*! GPTMODE + * 0b0..One Shot Mode + * 0b1..Repeat Mode + */ +#define USB_GPTIMER1CTRL_GPTMODE(x) (((uint32_t)(((uint32_t)(x)) << USB_GPTIMER1CTRL_GPTMODE_SHIFT)) & USB_GPTIMER1CTRL_GPTMODE_MASK) +#define USB_GPTIMER1CTRL_GPTRST_MASK (0x40000000U) +#define USB_GPTIMER1CTRL_GPTRST_SHIFT (30U) +/*! GPTRST + * 0b0..No action + * 0b1..Load counter value from GPTLD bits in USB_n_GPTIMER0LD + */ +#define USB_GPTIMER1CTRL_GPTRST(x) (((uint32_t)(((uint32_t)(x)) << USB_GPTIMER1CTRL_GPTRST_SHIFT)) & USB_GPTIMER1CTRL_GPTRST_MASK) +#define USB_GPTIMER1CTRL_GPTRUN_MASK (0x80000000U) +#define USB_GPTIMER1CTRL_GPTRUN_SHIFT (31U) +/*! GPTRUN + * 0b0..Stop counting + * 0b1..Run + */ +#define USB_GPTIMER1CTRL_GPTRUN(x) (((uint32_t)(((uint32_t)(x)) << USB_GPTIMER1CTRL_GPTRUN_SHIFT)) & USB_GPTIMER1CTRL_GPTRUN_MASK) +/*! @} */ + +/*! @name SBUSCFG - System Bus Config */ +/*! @{ */ +#define USB_SBUSCFG_AHBBRST_MASK (0x7U) +#define USB_SBUSCFG_AHBBRST_SHIFT (0U) +/*! AHBBRST + * 0b000..Incremental burst of unspecified length only + * 0b001..INCR4 burst, then single transfer + * 0b010..INCR8 burst, INCR4 burst, then single transfer + * 0b011..INCR16 burst, INCR8 burst, INCR4 burst, then single transfer + * 0b100..Reserved, don't use + * 0b101..INCR4 burst, then incremental burst of unspecified length + * 0b110..INCR8 burst, INCR4 burst, then incremental burst of unspecified length + * 0b111..INCR16 burst, INCR8 burst, INCR4 burst, then incremental burst of unspecified length + */ +#define USB_SBUSCFG_AHBBRST(x) (((uint32_t)(((uint32_t)(x)) << USB_SBUSCFG_AHBBRST_SHIFT)) & USB_SBUSCFG_AHBBRST_MASK) +/*! @} */ + +/*! @name CAPLENGTH - Capability Registers Length */ +/*! @{ */ +#define USB_CAPLENGTH_CAPLENGTH_MASK (0xFFU) +#define USB_CAPLENGTH_CAPLENGTH_SHIFT (0U) +#define USB_CAPLENGTH_CAPLENGTH(x) (((uint8_t)(((uint8_t)(x)) << USB_CAPLENGTH_CAPLENGTH_SHIFT)) & USB_CAPLENGTH_CAPLENGTH_MASK) +/*! @} */ + +/*! @name HCIVERSION - Host Controller Interface Version */ +/*! @{ */ +#define USB_HCIVERSION_HCIVERSION_MASK (0xFFFFU) +#define USB_HCIVERSION_HCIVERSION_SHIFT (0U) +#define USB_HCIVERSION_HCIVERSION(x) (((uint16_t)(((uint16_t)(x)) << USB_HCIVERSION_HCIVERSION_SHIFT)) & USB_HCIVERSION_HCIVERSION_MASK) +/*! @} */ + +/*! @name HCSPARAMS - Host Controller Structural Parameters */ +/*! @{ */ +#define USB_HCSPARAMS_N_PORTS_MASK (0xFU) +#define USB_HCSPARAMS_N_PORTS_SHIFT (0U) +#define USB_HCSPARAMS_N_PORTS(x) (((uint32_t)(((uint32_t)(x)) << USB_HCSPARAMS_N_PORTS_SHIFT)) & USB_HCSPARAMS_N_PORTS_MASK) +#define USB_HCSPARAMS_PPC_MASK (0x10U) +#define USB_HCSPARAMS_PPC_SHIFT (4U) +#define USB_HCSPARAMS_PPC(x) (((uint32_t)(((uint32_t)(x)) << USB_HCSPARAMS_PPC_SHIFT)) & USB_HCSPARAMS_PPC_MASK) +#define USB_HCSPARAMS_N_PCC_MASK (0xF00U) +#define USB_HCSPARAMS_N_PCC_SHIFT (8U) +#define USB_HCSPARAMS_N_PCC(x) (((uint32_t)(((uint32_t)(x)) << USB_HCSPARAMS_N_PCC_SHIFT)) & USB_HCSPARAMS_N_PCC_MASK) +#define USB_HCSPARAMS_N_CC_MASK (0xF000U) +#define USB_HCSPARAMS_N_CC_SHIFT (12U) +/*! N_CC + * 0b0000..There is no internal Companion Controller and port-ownership hand-off is not supported. + * 0b0001..There are internal companion controller(s) and port-ownership hand-offs is supported. + */ +#define USB_HCSPARAMS_N_CC(x) (((uint32_t)(((uint32_t)(x)) << USB_HCSPARAMS_N_CC_SHIFT)) & USB_HCSPARAMS_N_CC_MASK) +#define USB_HCSPARAMS_PI_MASK (0x10000U) +#define USB_HCSPARAMS_PI_SHIFT (16U) +#define USB_HCSPARAMS_PI(x) (((uint32_t)(((uint32_t)(x)) << USB_HCSPARAMS_PI_SHIFT)) & USB_HCSPARAMS_PI_MASK) +#define USB_HCSPARAMS_N_PTT_MASK (0xF00000U) +#define USB_HCSPARAMS_N_PTT_SHIFT (20U) +#define USB_HCSPARAMS_N_PTT(x) (((uint32_t)(((uint32_t)(x)) << USB_HCSPARAMS_N_PTT_SHIFT)) & USB_HCSPARAMS_N_PTT_MASK) +#define USB_HCSPARAMS_N_TT_MASK (0xF000000U) +#define USB_HCSPARAMS_N_TT_SHIFT (24U) +#define USB_HCSPARAMS_N_TT(x) (((uint32_t)(((uint32_t)(x)) << USB_HCSPARAMS_N_TT_SHIFT)) & USB_HCSPARAMS_N_TT_MASK) +/*! @} */ + +/*! @name HCCPARAMS - Host Controller Capability Parameters */ +/*! @{ */ +#define USB_HCCPARAMS_ADC_MASK (0x1U) +#define USB_HCCPARAMS_ADC_SHIFT (0U) +#define USB_HCCPARAMS_ADC(x) (((uint32_t)(((uint32_t)(x)) << USB_HCCPARAMS_ADC_SHIFT)) & USB_HCCPARAMS_ADC_MASK) +#define USB_HCCPARAMS_PFL_MASK (0x2U) +#define USB_HCCPARAMS_PFL_SHIFT (1U) +#define USB_HCCPARAMS_PFL(x) (((uint32_t)(((uint32_t)(x)) << USB_HCCPARAMS_PFL_SHIFT)) & USB_HCCPARAMS_PFL_MASK) +#define USB_HCCPARAMS_ASP_MASK (0x4U) +#define USB_HCCPARAMS_ASP_SHIFT (2U) +#define USB_HCCPARAMS_ASP(x) (((uint32_t)(((uint32_t)(x)) << USB_HCCPARAMS_ASP_SHIFT)) & USB_HCCPARAMS_ASP_MASK) +#define USB_HCCPARAMS_IST_MASK (0xF0U) +#define USB_HCCPARAMS_IST_SHIFT (4U) +#define USB_HCCPARAMS_IST(x) (((uint32_t)(((uint32_t)(x)) << USB_HCCPARAMS_IST_SHIFT)) & USB_HCCPARAMS_IST_MASK) +#define USB_HCCPARAMS_EECP_MASK (0xFF00U) +#define USB_HCCPARAMS_EECP_SHIFT (8U) +#define USB_HCCPARAMS_EECP(x) (((uint32_t)(((uint32_t)(x)) << USB_HCCPARAMS_EECP_SHIFT)) & USB_HCCPARAMS_EECP_MASK) +/*! @} */ + +/*! @name DCIVERSION - Device Controller Interface Version */ +/*! @{ */ +#define USB_DCIVERSION_DCIVERSION_MASK (0xFFFFU) +#define USB_DCIVERSION_DCIVERSION_SHIFT (0U) +#define USB_DCIVERSION_DCIVERSION(x) (((uint16_t)(((uint16_t)(x)) << USB_DCIVERSION_DCIVERSION_SHIFT)) & USB_DCIVERSION_DCIVERSION_MASK) +/*! @} */ + +/*! @name DCCPARAMS - Device Controller Capability Parameters */ +/*! @{ */ +#define USB_DCCPARAMS_DEN_MASK (0x1FU) +#define USB_DCCPARAMS_DEN_SHIFT (0U) +#define USB_DCCPARAMS_DEN(x) (((uint32_t)(((uint32_t)(x)) << USB_DCCPARAMS_DEN_SHIFT)) & USB_DCCPARAMS_DEN_MASK) +#define USB_DCCPARAMS_DC_MASK (0x80U) +#define USB_DCCPARAMS_DC_SHIFT (7U) +#define USB_DCCPARAMS_DC(x) (((uint32_t)(((uint32_t)(x)) << USB_DCCPARAMS_DC_SHIFT)) & USB_DCCPARAMS_DC_MASK) +#define USB_DCCPARAMS_HC_MASK (0x100U) +#define USB_DCCPARAMS_HC_SHIFT (8U) +#define USB_DCCPARAMS_HC(x) (((uint32_t)(((uint32_t)(x)) << USB_DCCPARAMS_HC_SHIFT)) & USB_DCCPARAMS_HC_MASK) +/*! @} */ + +/*! @name USBCMD - USB Command Register */ +/*! @{ */ +#define USB_USBCMD_RS_MASK (0x1U) +#define USB_USBCMD_RS_SHIFT (0U) +#define USB_USBCMD_RS(x) (((uint32_t)(((uint32_t)(x)) << USB_USBCMD_RS_SHIFT)) & USB_USBCMD_RS_MASK) +#define USB_USBCMD_RST_MASK (0x2U) +#define USB_USBCMD_RST_SHIFT (1U) +#define USB_USBCMD_RST(x) (((uint32_t)(((uint32_t)(x)) << USB_USBCMD_RST_SHIFT)) & USB_USBCMD_RST_MASK) +#define USB_USBCMD_FS_1_MASK (0xCU) +#define USB_USBCMD_FS_1_SHIFT (2U) +#define USB_USBCMD_FS_1(x) (((uint32_t)(((uint32_t)(x)) << USB_USBCMD_FS_1_SHIFT)) & USB_USBCMD_FS_1_MASK) +#define USB_USBCMD_PSE_MASK (0x10U) +#define USB_USBCMD_PSE_SHIFT (4U) +/*! PSE + * 0b0..Do not process the Periodic Schedule + * 0b1..Use the PERIODICLISTBASE register to access the Periodic Schedule. + */ +#define USB_USBCMD_PSE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBCMD_PSE_SHIFT)) & USB_USBCMD_PSE_MASK) +#define USB_USBCMD_ASE_MASK (0x20U) +#define USB_USBCMD_ASE_SHIFT (5U) +/*! ASE + * 0b0..Do not process the Asynchronous Schedule. + * 0b1..Use the ASYNCLISTADDR register to access the Asynchronous Schedule. + */ +#define USB_USBCMD_ASE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBCMD_ASE_SHIFT)) & USB_USBCMD_ASE_MASK) +#define USB_USBCMD_IAA_MASK (0x40U) +#define USB_USBCMD_IAA_SHIFT (6U) +#define USB_USBCMD_IAA(x) (((uint32_t)(((uint32_t)(x)) << USB_USBCMD_IAA_SHIFT)) & USB_USBCMD_IAA_MASK) +#define USB_USBCMD_ASP_MASK (0x300U) +#define USB_USBCMD_ASP_SHIFT (8U) +#define USB_USBCMD_ASP(x) (((uint32_t)(((uint32_t)(x)) << USB_USBCMD_ASP_SHIFT)) & USB_USBCMD_ASP_MASK) +#define USB_USBCMD_ASPE_MASK (0x800U) +#define USB_USBCMD_ASPE_SHIFT (11U) +#define USB_USBCMD_ASPE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBCMD_ASPE_SHIFT)) & USB_USBCMD_ASPE_MASK) +#define USB_USBCMD_ATDTW_MASK (0x1000U) +#define USB_USBCMD_ATDTW_SHIFT (12U) +#define USB_USBCMD_ATDTW(x) (((uint32_t)(((uint32_t)(x)) << USB_USBCMD_ATDTW_SHIFT)) & USB_USBCMD_ATDTW_MASK) +#define USB_USBCMD_SUTW_MASK (0x2000U) +#define USB_USBCMD_SUTW_SHIFT (13U) +#define USB_USBCMD_SUTW(x) (((uint32_t)(((uint32_t)(x)) << USB_USBCMD_SUTW_SHIFT)) & USB_USBCMD_SUTW_MASK) +#define USB_USBCMD_FS_2_MASK (0x8000U) +#define USB_USBCMD_FS_2_SHIFT (15U) +/*! FS_2 + * 0b0..1024 elements (4096 bytes) Default value + * 0b1..512 elements (2048 bytes) + */ +#define USB_USBCMD_FS_2(x) (((uint32_t)(((uint32_t)(x)) << USB_USBCMD_FS_2_SHIFT)) & USB_USBCMD_FS_2_MASK) +#define USB_USBCMD_ITC_MASK (0xFF0000U) +#define USB_USBCMD_ITC_SHIFT (16U) +/*! ITC + * 0b00000000..Immediate (no threshold) + * 0b00000001..1 micro-frame + * 0b00000010..2 micro-frames + * 0b00000100..4 micro-frames + * 0b00001000..8 micro-frames + * 0b00010000..16 micro-frames + * 0b00100000..32 micro-frames + * 0b01000000..64 micro-frames + */ +#define USB_USBCMD_ITC(x) (((uint32_t)(((uint32_t)(x)) << USB_USBCMD_ITC_SHIFT)) & USB_USBCMD_ITC_MASK) +/*! @} */ + +/*! @name USBSTS - USB Status Register */ +/*! @{ */ +#define USB_USBSTS_UI_MASK (0x1U) +#define USB_USBSTS_UI_SHIFT (0U) +#define USB_USBSTS_UI(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_UI_SHIFT)) & USB_USBSTS_UI_MASK) +#define USB_USBSTS_UEI_MASK (0x2U) +#define USB_USBSTS_UEI_SHIFT (1U) +#define USB_USBSTS_UEI(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_UEI_SHIFT)) & USB_USBSTS_UEI_MASK) +#define USB_USBSTS_PCI_MASK (0x4U) +#define USB_USBSTS_PCI_SHIFT (2U) +#define USB_USBSTS_PCI(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_PCI_SHIFT)) & USB_USBSTS_PCI_MASK) +#define USB_USBSTS_FRI_MASK (0x8U) +#define USB_USBSTS_FRI_SHIFT (3U) +#define USB_USBSTS_FRI(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_FRI_SHIFT)) & USB_USBSTS_FRI_MASK) +#define USB_USBSTS_SEI_MASK (0x10U) +#define USB_USBSTS_SEI_SHIFT (4U) +#define USB_USBSTS_SEI(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_SEI_SHIFT)) & USB_USBSTS_SEI_MASK) +#define USB_USBSTS_AAI_MASK (0x20U) +#define USB_USBSTS_AAI_SHIFT (5U) +#define USB_USBSTS_AAI(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_AAI_SHIFT)) & USB_USBSTS_AAI_MASK) +#define USB_USBSTS_URI_MASK (0x40U) +#define USB_USBSTS_URI_SHIFT (6U) +#define USB_USBSTS_URI(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_URI_SHIFT)) & USB_USBSTS_URI_MASK) +#define USB_USBSTS_SRI_MASK (0x80U) +#define USB_USBSTS_SRI_SHIFT (7U) +#define USB_USBSTS_SRI(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_SRI_SHIFT)) & USB_USBSTS_SRI_MASK) +#define USB_USBSTS_SLI_MASK (0x100U) +#define USB_USBSTS_SLI_SHIFT (8U) +#define USB_USBSTS_SLI(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_SLI_SHIFT)) & USB_USBSTS_SLI_MASK) +#define USB_USBSTS_ULPII_MASK (0x400U) +#define USB_USBSTS_ULPII_SHIFT (10U) +#define USB_USBSTS_ULPII(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_ULPII_SHIFT)) & USB_USBSTS_ULPII_MASK) +#define USB_USBSTS_HCH_MASK (0x1000U) +#define USB_USBSTS_HCH_SHIFT (12U) +#define USB_USBSTS_HCH(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_HCH_SHIFT)) & USB_USBSTS_HCH_MASK) +#define USB_USBSTS_RCL_MASK (0x2000U) +#define USB_USBSTS_RCL_SHIFT (13U) +#define USB_USBSTS_RCL(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_RCL_SHIFT)) & USB_USBSTS_RCL_MASK) +#define USB_USBSTS_PS_MASK (0x4000U) +#define USB_USBSTS_PS_SHIFT (14U) +#define USB_USBSTS_PS(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_PS_SHIFT)) & USB_USBSTS_PS_MASK) +#define USB_USBSTS_AS_MASK (0x8000U) +#define USB_USBSTS_AS_SHIFT (15U) +#define USB_USBSTS_AS(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_AS_SHIFT)) & USB_USBSTS_AS_MASK) +#define USB_USBSTS_NAKI_MASK (0x10000U) +#define USB_USBSTS_NAKI_SHIFT (16U) +#define USB_USBSTS_NAKI(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_NAKI_SHIFT)) & USB_USBSTS_NAKI_MASK) +#define USB_USBSTS_TI0_MASK (0x1000000U) +#define USB_USBSTS_TI0_SHIFT (24U) +#define USB_USBSTS_TI0(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_TI0_SHIFT)) & USB_USBSTS_TI0_MASK) +#define USB_USBSTS_TI1_MASK (0x2000000U) +#define USB_USBSTS_TI1_SHIFT (25U) +#define USB_USBSTS_TI1(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_TI1_SHIFT)) & USB_USBSTS_TI1_MASK) +/*! @} */ + +/*! @name USBINTR - Interrupt Enable Register */ +/*! @{ */ +#define USB_USBINTR_UE_MASK (0x1U) +#define USB_USBINTR_UE_SHIFT (0U) +#define USB_USBINTR_UE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_UE_SHIFT)) & USB_USBINTR_UE_MASK) +#define USB_USBINTR_UEE_MASK (0x2U) +#define USB_USBINTR_UEE_SHIFT (1U) +#define USB_USBINTR_UEE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_UEE_SHIFT)) & USB_USBINTR_UEE_MASK) +#define USB_USBINTR_PCE_MASK (0x4U) +#define USB_USBINTR_PCE_SHIFT (2U) +#define USB_USBINTR_PCE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_PCE_SHIFT)) & USB_USBINTR_PCE_MASK) +#define USB_USBINTR_FRE_MASK (0x8U) +#define USB_USBINTR_FRE_SHIFT (3U) +#define USB_USBINTR_FRE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_FRE_SHIFT)) & USB_USBINTR_FRE_MASK) +#define USB_USBINTR_SEE_MASK (0x10U) +#define USB_USBINTR_SEE_SHIFT (4U) +#define USB_USBINTR_SEE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_SEE_SHIFT)) & USB_USBINTR_SEE_MASK) +#define USB_USBINTR_AAE_MASK (0x20U) +#define USB_USBINTR_AAE_SHIFT (5U) +#define USB_USBINTR_AAE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_AAE_SHIFT)) & USB_USBINTR_AAE_MASK) +#define USB_USBINTR_URE_MASK (0x40U) +#define USB_USBINTR_URE_SHIFT (6U) +#define USB_USBINTR_URE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_URE_SHIFT)) & USB_USBINTR_URE_MASK) +#define USB_USBINTR_SRE_MASK (0x80U) +#define USB_USBINTR_SRE_SHIFT (7U) +#define USB_USBINTR_SRE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_SRE_SHIFT)) & USB_USBINTR_SRE_MASK) +#define USB_USBINTR_SLE_MASK (0x100U) +#define USB_USBINTR_SLE_SHIFT (8U) +#define USB_USBINTR_SLE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_SLE_SHIFT)) & USB_USBINTR_SLE_MASK) +#define USB_USBINTR_ULPIE_MASK (0x400U) +#define USB_USBINTR_ULPIE_SHIFT (10U) +#define USB_USBINTR_ULPIE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_ULPIE_SHIFT)) & USB_USBINTR_ULPIE_MASK) +#define USB_USBINTR_NAKE_MASK (0x10000U) +#define USB_USBINTR_NAKE_SHIFT (16U) +#define USB_USBINTR_NAKE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_NAKE_SHIFT)) & USB_USBINTR_NAKE_MASK) +#define USB_USBINTR_UAIE_MASK (0x40000U) +#define USB_USBINTR_UAIE_SHIFT (18U) +#define USB_USBINTR_UAIE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_UAIE_SHIFT)) & USB_USBINTR_UAIE_MASK) +#define USB_USBINTR_UPIE_MASK (0x80000U) +#define USB_USBINTR_UPIE_SHIFT (19U) +#define USB_USBINTR_UPIE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_UPIE_SHIFT)) & USB_USBINTR_UPIE_MASK) +#define USB_USBINTR_TIE0_MASK (0x1000000U) +#define USB_USBINTR_TIE0_SHIFT (24U) +#define USB_USBINTR_TIE0(x) (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_TIE0_SHIFT)) & USB_USBINTR_TIE0_MASK) +#define USB_USBINTR_TIE1_MASK (0x2000000U) +#define USB_USBINTR_TIE1_SHIFT (25U) +#define USB_USBINTR_TIE1(x) (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_TIE1_SHIFT)) & USB_USBINTR_TIE1_MASK) +/*! @} */ + +/*! @name FRINDEX - USB Frame Index */ +/*! @{ */ +#define USB_FRINDEX_FRINDEX_MASK (0x3FFFU) +#define USB_FRINDEX_FRINDEX_SHIFT (0U) +/*! FRINDEX + * 0b00000000000000..(1024) 12 + * 0b00000000000001..(512) 11 + * 0b00000000000010..(256) 10 + * 0b00000000000011..(128) 9 + * 0b00000000000100..(64) 8 + * 0b00000000000101..(32) 7 + * 0b00000000000110..(16) 6 + * 0b00000000000111..(8) 5 + */ +#define USB_FRINDEX_FRINDEX(x) (((uint32_t)(((uint32_t)(x)) << USB_FRINDEX_FRINDEX_SHIFT)) & USB_FRINDEX_FRINDEX_MASK) +/*! @} */ + +/*! @name DEVICEADDR - Device Address */ +/*! @{ */ +#define USB_DEVICEADDR_USBADRA_MASK (0x1000000U) +#define USB_DEVICEADDR_USBADRA_SHIFT (24U) +#define USB_DEVICEADDR_USBADRA(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVICEADDR_USBADRA_SHIFT)) & USB_DEVICEADDR_USBADRA_MASK) +#define USB_DEVICEADDR_USBADR_MASK (0xFE000000U) +#define USB_DEVICEADDR_USBADR_SHIFT (25U) +#define USB_DEVICEADDR_USBADR(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVICEADDR_USBADR_SHIFT)) & USB_DEVICEADDR_USBADR_MASK) +/*! @} */ + +/*! @name PERIODICLISTBASE - Frame List Base Address */ +/*! @{ */ +#define USB_PERIODICLISTBASE_BASEADR_MASK (0xFFFFF000U) +#define USB_PERIODICLISTBASE_BASEADR_SHIFT (12U) +#define USB_PERIODICLISTBASE_BASEADR(x) (((uint32_t)(((uint32_t)(x)) << USB_PERIODICLISTBASE_BASEADR_SHIFT)) & USB_PERIODICLISTBASE_BASEADR_MASK) +/*! @} */ + +/*! @name ASYNCLISTADDR - Next Asynch. Address */ +/*! @{ */ +#define USB_ASYNCLISTADDR_ASYBASE_MASK (0xFFFFFFE0U) +#define USB_ASYNCLISTADDR_ASYBASE_SHIFT (5U) +#define USB_ASYNCLISTADDR_ASYBASE(x) (((uint32_t)(((uint32_t)(x)) << USB_ASYNCLISTADDR_ASYBASE_SHIFT)) & USB_ASYNCLISTADDR_ASYBASE_MASK) +/*! @} */ + +/*! @name ENDPTLISTADDR - Endpoint List Address */ +/*! @{ */ +#define USB_ENDPTLISTADDR_EPBASE_MASK (0xFFFFF800U) +#define USB_ENDPTLISTADDR_EPBASE_SHIFT (11U) +#define USB_ENDPTLISTADDR_EPBASE(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTLISTADDR_EPBASE_SHIFT)) & USB_ENDPTLISTADDR_EPBASE_MASK) +/*! @} */ + +/*! @name BURSTSIZE - Programmable Burst Size */ +/*! @{ */ +#define USB_BURSTSIZE_RXPBURST_MASK (0xFFU) +#define USB_BURSTSIZE_RXPBURST_SHIFT (0U) +#define USB_BURSTSIZE_RXPBURST(x) (((uint32_t)(((uint32_t)(x)) << USB_BURSTSIZE_RXPBURST_SHIFT)) & USB_BURSTSIZE_RXPBURST_MASK) +#define USB_BURSTSIZE_TXPBURST_MASK (0x1FF00U) +#define USB_BURSTSIZE_TXPBURST_SHIFT (8U) +#define USB_BURSTSIZE_TXPBURST(x) (((uint32_t)(((uint32_t)(x)) << USB_BURSTSIZE_TXPBURST_SHIFT)) & USB_BURSTSIZE_TXPBURST_MASK) +/*! @} */ + +/*! @name TXFILLTUNING - TX FIFO Fill Tuning */ +/*! @{ */ +#define USB_TXFILLTUNING_TXSCHOH_MASK (0xFFU) +#define USB_TXFILLTUNING_TXSCHOH_SHIFT (0U) +#define USB_TXFILLTUNING_TXSCHOH(x) (((uint32_t)(((uint32_t)(x)) << USB_TXFILLTUNING_TXSCHOH_SHIFT)) & USB_TXFILLTUNING_TXSCHOH_MASK) +#define USB_TXFILLTUNING_TXSCHHEALTH_MASK (0x1F00U) +#define USB_TXFILLTUNING_TXSCHHEALTH_SHIFT (8U) +#define USB_TXFILLTUNING_TXSCHHEALTH(x) (((uint32_t)(((uint32_t)(x)) << USB_TXFILLTUNING_TXSCHHEALTH_SHIFT)) & USB_TXFILLTUNING_TXSCHHEALTH_MASK) +#define USB_TXFILLTUNING_TXFIFOTHRES_MASK (0x3F0000U) +#define USB_TXFILLTUNING_TXFIFOTHRES_SHIFT (16U) +#define USB_TXFILLTUNING_TXFIFOTHRES(x) (((uint32_t)(((uint32_t)(x)) << USB_TXFILLTUNING_TXFIFOTHRES_SHIFT)) & USB_TXFILLTUNING_TXFIFOTHRES_MASK) +/*! @} */ + +/*! @name ENDPTNAK - Endpoint NAK */ +/*! @{ */ +#define USB_ENDPTNAK_EPRN_MASK (0xFFU) +#define USB_ENDPTNAK_EPRN_SHIFT (0U) +#define USB_ENDPTNAK_EPRN(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTNAK_EPRN_SHIFT)) & USB_ENDPTNAK_EPRN_MASK) +#define USB_ENDPTNAK_EPTN_MASK (0xFF0000U) +#define USB_ENDPTNAK_EPTN_SHIFT (16U) +#define USB_ENDPTNAK_EPTN(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTNAK_EPTN_SHIFT)) & USB_ENDPTNAK_EPTN_MASK) +/*! @} */ + +/*! @name ENDPTNAKEN - Endpoint NAK Enable */ +/*! @{ */ +#define USB_ENDPTNAKEN_EPRNE_MASK (0xFFU) +#define USB_ENDPTNAKEN_EPRNE_SHIFT (0U) +#define USB_ENDPTNAKEN_EPRNE(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTNAKEN_EPRNE_SHIFT)) & USB_ENDPTNAKEN_EPRNE_MASK) +#define USB_ENDPTNAKEN_EPTNE_MASK (0xFF0000U) +#define USB_ENDPTNAKEN_EPTNE_SHIFT (16U) +#define USB_ENDPTNAKEN_EPTNE(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTNAKEN_EPTNE_SHIFT)) & USB_ENDPTNAKEN_EPTNE_MASK) +/*! @} */ + +/*! @name CONFIGFLAG - Configure Flag Register */ +/*! @{ */ +#define USB_CONFIGFLAG_CF_MASK (0x1U) +#define USB_CONFIGFLAG_CF_SHIFT (0U) +/*! CF + * 0b0..Port routing control logic default-routes each port to an implementation dependent classic host controller. + * 0b1..Port routing control logic default-routes all ports to this host controller. + */ +#define USB_CONFIGFLAG_CF(x) (((uint32_t)(((uint32_t)(x)) << USB_CONFIGFLAG_CF_SHIFT)) & USB_CONFIGFLAG_CF_MASK) +/*! @} */ + +/*! @name PORTSC1 - Port Status & Control */ +/*! @{ */ +#define USB_PORTSC1_CCS_MASK (0x1U) +#define USB_PORTSC1_CCS_SHIFT (0U) +#define USB_PORTSC1_CCS(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_CCS_SHIFT)) & USB_PORTSC1_CCS_MASK) +#define USB_PORTSC1_CSC_MASK (0x2U) +#define USB_PORTSC1_CSC_SHIFT (1U) +#define USB_PORTSC1_CSC(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_CSC_SHIFT)) & USB_PORTSC1_CSC_MASK) +#define USB_PORTSC1_PE_MASK (0x4U) +#define USB_PORTSC1_PE_SHIFT (2U) +#define USB_PORTSC1_PE(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PE_SHIFT)) & USB_PORTSC1_PE_MASK) +#define USB_PORTSC1_PEC_MASK (0x8U) +#define USB_PORTSC1_PEC_SHIFT (3U) +#define USB_PORTSC1_PEC(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PEC_SHIFT)) & USB_PORTSC1_PEC_MASK) +#define USB_PORTSC1_OCA_MASK (0x10U) +#define USB_PORTSC1_OCA_SHIFT (4U) +/*! OCA + * 0b1..This port currently has an over-current condition + * 0b0..This port does not have an over-current condition. + */ +#define USB_PORTSC1_OCA(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_OCA_SHIFT)) & USB_PORTSC1_OCA_MASK) +#define USB_PORTSC1_OCC_MASK (0x20U) +#define USB_PORTSC1_OCC_SHIFT (5U) +#define USB_PORTSC1_OCC(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_OCC_SHIFT)) & USB_PORTSC1_OCC_MASK) +#define USB_PORTSC1_FPR_MASK (0x40U) +#define USB_PORTSC1_FPR_SHIFT (6U) +#define USB_PORTSC1_FPR(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_FPR_SHIFT)) & USB_PORTSC1_FPR_MASK) +#define USB_PORTSC1_SUSP_MASK (0x80U) +#define USB_PORTSC1_SUSP_SHIFT (7U) +#define USB_PORTSC1_SUSP(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_SUSP_SHIFT)) & USB_PORTSC1_SUSP_MASK) +#define USB_PORTSC1_PR_MASK (0x100U) +#define USB_PORTSC1_PR_SHIFT (8U) +#define USB_PORTSC1_PR(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PR_SHIFT)) & USB_PORTSC1_PR_MASK) +#define USB_PORTSC1_HSP_MASK (0x200U) +#define USB_PORTSC1_HSP_SHIFT (9U) +#define USB_PORTSC1_HSP(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_HSP_SHIFT)) & USB_PORTSC1_HSP_MASK) +#define USB_PORTSC1_LS_MASK (0xC00U) +#define USB_PORTSC1_LS_SHIFT (10U) +/*! LS + * 0b00..SE0 + * 0b10..J-state + * 0b01..K-state + * 0b11..Undefined + */ +#define USB_PORTSC1_LS(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_LS_SHIFT)) & USB_PORTSC1_LS_MASK) +#define USB_PORTSC1_PP_MASK (0x1000U) +#define USB_PORTSC1_PP_SHIFT (12U) +#define USB_PORTSC1_PP(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PP_SHIFT)) & USB_PORTSC1_PP_MASK) +#define USB_PORTSC1_PO_MASK (0x2000U) +#define USB_PORTSC1_PO_SHIFT (13U) +#define USB_PORTSC1_PO(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PO_SHIFT)) & USB_PORTSC1_PO_MASK) +#define USB_PORTSC1_PIC_MASK (0xC000U) +#define USB_PORTSC1_PIC_SHIFT (14U) +/*! PIC + * 0b00..Port indicators are off + * 0b01..Amber + * 0b10..Green + * 0b11..Undefined + */ +#define USB_PORTSC1_PIC(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PIC_SHIFT)) & USB_PORTSC1_PIC_MASK) +#define USB_PORTSC1_PTC_MASK (0xF0000U) +#define USB_PORTSC1_PTC_SHIFT (16U) +/*! PTC + * 0b0000..TEST_MODE_DISABLE + * 0b0001..J_STATE + * 0b0010..K_STATE + * 0b0011..SE0 (host) / NAK (device) + * 0b0100..Packet + * 0b0101..FORCE_ENABLE_HS + * 0b0110..FORCE_ENABLE_FS + * 0b0111..FORCE_ENABLE_LS + */ +#define USB_PORTSC1_PTC(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PTC_SHIFT)) & USB_PORTSC1_PTC_MASK) +#define USB_PORTSC1_WKCN_MASK (0x100000U) +#define USB_PORTSC1_WKCN_SHIFT (20U) +#define USB_PORTSC1_WKCN(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_WKCN_SHIFT)) & USB_PORTSC1_WKCN_MASK) +#define USB_PORTSC1_WKDC_MASK (0x200000U) +#define USB_PORTSC1_WKDC_SHIFT (21U) +#define USB_PORTSC1_WKDC(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_WKDC_SHIFT)) & USB_PORTSC1_WKDC_MASK) +#define USB_PORTSC1_WKOC_MASK (0x400000U) +#define USB_PORTSC1_WKOC_SHIFT (22U) +#define USB_PORTSC1_WKOC(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_WKOC_SHIFT)) & USB_PORTSC1_WKOC_MASK) +#define USB_PORTSC1_PHCD_MASK (0x800000U) +#define USB_PORTSC1_PHCD_SHIFT (23U) +/*! PHCD + * 0b1..Disable PHY clock + * 0b0..Enable PHY clock + */ +#define USB_PORTSC1_PHCD(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PHCD_SHIFT)) & USB_PORTSC1_PHCD_MASK) +#define USB_PORTSC1_PFSC_MASK (0x1000000U) +#define USB_PORTSC1_PFSC_SHIFT (24U) +/*! PFSC + * 0b1..Forced to full speed + * 0b0..Normal operation + */ +#define USB_PORTSC1_PFSC(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PFSC_SHIFT)) & USB_PORTSC1_PFSC_MASK) +#define USB_PORTSC1_PTS_2_MASK (0x2000000U) +#define USB_PORTSC1_PTS_2_SHIFT (25U) +#define USB_PORTSC1_PTS_2(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PTS_2_SHIFT)) & USB_PORTSC1_PTS_2_MASK) +#define USB_PORTSC1_PSPD_MASK (0xC000000U) +#define USB_PORTSC1_PSPD_SHIFT (26U) +/*! PSPD + * 0b00..Full Speed + * 0b01..Low Speed + * 0b10..High Speed + * 0b11..Undefined + */ +#define USB_PORTSC1_PSPD(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PSPD_SHIFT)) & USB_PORTSC1_PSPD_MASK) +#define USB_PORTSC1_PTW_MASK (0x10000000U) +#define USB_PORTSC1_PTW_SHIFT (28U) +/*! PTW + * 0b0..Select the 8-bit UTMI interface [60MHz] + * 0b1..Select the 16-bit UTMI interface [30MHz] + */ +#define USB_PORTSC1_PTW(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PTW_SHIFT)) & USB_PORTSC1_PTW_MASK) +#define USB_PORTSC1_STS_MASK (0x20000000U) +#define USB_PORTSC1_STS_SHIFT (29U) +#define USB_PORTSC1_STS(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_STS_SHIFT)) & USB_PORTSC1_STS_MASK) +#define USB_PORTSC1_PTS_1_MASK (0xC0000000U) +#define USB_PORTSC1_PTS_1_SHIFT (30U) +#define USB_PORTSC1_PTS_1(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PTS_1_SHIFT)) & USB_PORTSC1_PTS_1_MASK) +/*! @} */ + +/*! @name OTGSC - On-The-Go Status & control */ +/*! @{ */ +#define USB_OTGSC_VD_MASK (0x1U) +#define USB_OTGSC_VD_SHIFT (0U) +#define USB_OTGSC_VD(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_VD_SHIFT)) & USB_OTGSC_VD_MASK) +#define USB_OTGSC_VC_MASK (0x2U) +#define USB_OTGSC_VC_SHIFT (1U) +#define USB_OTGSC_VC(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_VC_SHIFT)) & USB_OTGSC_VC_MASK) +#define USB_OTGSC_OT_MASK (0x8U) +#define USB_OTGSC_OT_SHIFT (3U) +#define USB_OTGSC_OT(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_OT_SHIFT)) & USB_OTGSC_OT_MASK) +#define USB_OTGSC_DP_MASK (0x10U) +#define USB_OTGSC_DP_SHIFT (4U) +#define USB_OTGSC_DP(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_DP_SHIFT)) & USB_OTGSC_DP_MASK) +#define USB_OTGSC_IDPU_MASK (0x20U) +#define USB_OTGSC_IDPU_SHIFT (5U) +#define USB_OTGSC_IDPU(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_IDPU_SHIFT)) & USB_OTGSC_IDPU_MASK) +#define USB_OTGSC_ID_MASK (0x100U) +#define USB_OTGSC_ID_SHIFT (8U) +#define USB_OTGSC_ID(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_ID_SHIFT)) & USB_OTGSC_ID_MASK) +#define USB_OTGSC_AVV_MASK (0x200U) +#define USB_OTGSC_AVV_SHIFT (9U) +#define USB_OTGSC_AVV(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_AVV_SHIFT)) & USB_OTGSC_AVV_MASK) +#define USB_OTGSC_ASV_MASK (0x400U) +#define USB_OTGSC_ASV_SHIFT (10U) +#define USB_OTGSC_ASV(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_ASV_SHIFT)) & USB_OTGSC_ASV_MASK) +#define USB_OTGSC_BSV_MASK (0x800U) +#define USB_OTGSC_BSV_SHIFT (11U) +#define USB_OTGSC_BSV(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_BSV_SHIFT)) & USB_OTGSC_BSV_MASK) +#define USB_OTGSC_BSE_MASK (0x1000U) +#define USB_OTGSC_BSE_SHIFT (12U) +#define USB_OTGSC_BSE(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_BSE_SHIFT)) & USB_OTGSC_BSE_MASK) +#define USB_OTGSC_TOG_1MS_MASK (0x2000U) +#define USB_OTGSC_TOG_1MS_SHIFT (13U) +#define USB_OTGSC_TOG_1MS(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_TOG_1MS_SHIFT)) & USB_OTGSC_TOG_1MS_MASK) +#define USB_OTGSC_DPS_MASK (0x4000U) +#define USB_OTGSC_DPS_SHIFT (14U) +#define USB_OTGSC_DPS(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_DPS_SHIFT)) & USB_OTGSC_DPS_MASK) +#define USB_OTGSC_IDIS_MASK (0x10000U) +#define USB_OTGSC_IDIS_SHIFT (16U) +#define USB_OTGSC_IDIS(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_IDIS_SHIFT)) & USB_OTGSC_IDIS_MASK) +#define USB_OTGSC_AVVIS_MASK (0x20000U) +#define USB_OTGSC_AVVIS_SHIFT (17U) +#define USB_OTGSC_AVVIS(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_AVVIS_SHIFT)) & USB_OTGSC_AVVIS_MASK) +#define USB_OTGSC_ASVIS_MASK (0x40000U) +#define USB_OTGSC_ASVIS_SHIFT (18U) +#define USB_OTGSC_ASVIS(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_ASVIS_SHIFT)) & USB_OTGSC_ASVIS_MASK) +#define USB_OTGSC_BSVIS_MASK (0x80000U) +#define USB_OTGSC_BSVIS_SHIFT (19U) +#define USB_OTGSC_BSVIS(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_BSVIS_SHIFT)) & USB_OTGSC_BSVIS_MASK) +#define USB_OTGSC_BSEIS_MASK (0x100000U) +#define USB_OTGSC_BSEIS_SHIFT (20U) +#define USB_OTGSC_BSEIS(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_BSEIS_SHIFT)) & USB_OTGSC_BSEIS_MASK) +#define USB_OTGSC_STATUS_1MS_MASK (0x200000U) +#define USB_OTGSC_STATUS_1MS_SHIFT (21U) +#define USB_OTGSC_STATUS_1MS(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_STATUS_1MS_SHIFT)) & USB_OTGSC_STATUS_1MS_MASK) +#define USB_OTGSC_DPIS_MASK (0x400000U) +#define USB_OTGSC_DPIS_SHIFT (22U) +#define USB_OTGSC_DPIS(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_DPIS_SHIFT)) & USB_OTGSC_DPIS_MASK) +#define USB_OTGSC_IDIE_MASK (0x1000000U) +#define USB_OTGSC_IDIE_SHIFT (24U) +#define USB_OTGSC_IDIE(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_IDIE_SHIFT)) & USB_OTGSC_IDIE_MASK) +#define USB_OTGSC_AVVIE_MASK (0x2000000U) +#define USB_OTGSC_AVVIE_SHIFT (25U) +#define USB_OTGSC_AVVIE(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_AVVIE_SHIFT)) & USB_OTGSC_AVVIE_MASK) +#define USB_OTGSC_ASVIE_MASK (0x4000000U) +#define USB_OTGSC_ASVIE_SHIFT (26U) +#define USB_OTGSC_ASVIE(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_ASVIE_SHIFT)) & USB_OTGSC_ASVIE_MASK) +#define USB_OTGSC_BSVIE_MASK (0x8000000U) +#define USB_OTGSC_BSVIE_SHIFT (27U) +#define USB_OTGSC_BSVIE(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_BSVIE_SHIFT)) & USB_OTGSC_BSVIE_MASK) +#define USB_OTGSC_BSEIE_MASK (0x10000000U) +#define USB_OTGSC_BSEIE_SHIFT (28U) +#define USB_OTGSC_BSEIE(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_BSEIE_SHIFT)) & USB_OTGSC_BSEIE_MASK) +#define USB_OTGSC_EN_1MS_MASK (0x20000000U) +#define USB_OTGSC_EN_1MS_SHIFT (29U) +#define USB_OTGSC_EN_1MS(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_EN_1MS_SHIFT)) & USB_OTGSC_EN_1MS_MASK) +#define USB_OTGSC_DPIE_MASK (0x40000000U) +#define USB_OTGSC_DPIE_SHIFT (30U) +#define USB_OTGSC_DPIE(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_DPIE_SHIFT)) & USB_OTGSC_DPIE_MASK) +/*! @} */ + +/*! @name USBMODE - USB Device Mode */ +/*! @{ */ +#define USB_USBMODE_CM_MASK (0x3U) +#define USB_USBMODE_CM_SHIFT (0U) +/*! CM + * 0b00..Idle [Default for combination host/device] + * 0b01..Reserved + * 0b10..Device Controller [Default for device only controller] + * 0b11..Host Controller [Default for host only controller] + */ +#define USB_USBMODE_CM(x) (((uint32_t)(((uint32_t)(x)) << USB_USBMODE_CM_SHIFT)) & USB_USBMODE_CM_MASK) +#define USB_USBMODE_ES_MASK (0x4U) +#define USB_USBMODE_ES_SHIFT (2U) +/*! ES + * 0b0..Little Endian [Default] + * 0b1..Big Endian + */ +#define USB_USBMODE_ES(x) (((uint32_t)(((uint32_t)(x)) << USB_USBMODE_ES_SHIFT)) & USB_USBMODE_ES_MASK) +#define USB_USBMODE_SLOM_MASK (0x8U) +#define USB_USBMODE_SLOM_SHIFT (3U) +/*! SLOM + * 0b0..Setup Lockouts On (default); + * 0b1..Setup Lockouts Off (DCD requires use of Setup Data Buffer Tripwire in USBCMDUSB Command Register . + */ +#define USB_USBMODE_SLOM(x) (((uint32_t)(((uint32_t)(x)) << USB_USBMODE_SLOM_SHIFT)) & USB_USBMODE_SLOM_MASK) +#define USB_USBMODE_SDIS_MASK (0x10U) +#define USB_USBMODE_SDIS_SHIFT (4U) +#define USB_USBMODE_SDIS(x) (((uint32_t)(((uint32_t)(x)) << USB_USBMODE_SDIS_SHIFT)) & USB_USBMODE_SDIS_MASK) +/*! @} */ + +/*! @name ENDPTSETUPSTAT - Endpoint Setup Status */ +/*! @{ */ +#define USB_ENDPTSETUPSTAT_ENDPTSETUPSTAT_MASK (0xFFFFU) +#define USB_ENDPTSETUPSTAT_ENDPTSETUPSTAT_SHIFT (0U) +#define USB_ENDPTSETUPSTAT_ENDPTSETUPSTAT(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTSETUPSTAT_ENDPTSETUPSTAT_SHIFT)) & USB_ENDPTSETUPSTAT_ENDPTSETUPSTAT_MASK) +/*! @} */ + +/*! @name ENDPTPRIME - Endpoint Prime */ +/*! @{ */ +#define USB_ENDPTPRIME_PERB_MASK (0xFFU) +#define USB_ENDPTPRIME_PERB_SHIFT (0U) +#define USB_ENDPTPRIME_PERB(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTPRIME_PERB_SHIFT)) & USB_ENDPTPRIME_PERB_MASK) +#define USB_ENDPTPRIME_PETB_MASK (0xFF0000U) +#define USB_ENDPTPRIME_PETB_SHIFT (16U) +#define USB_ENDPTPRIME_PETB(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTPRIME_PETB_SHIFT)) & USB_ENDPTPRIME_PETB_MASK) +/*! @} */ + +/*! @name ENDPTFLUSH - Endpoint Flush */ +/*! @{ */ +#define USB_ENDPTFLUSH_FERB_MASK (0xFFU) +#define USB_ENDPTFLUSH_FERB_SHIFT (0U) +#define USB_ENDPTFLUSH_FERB(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTFLUSH_FERB_SHIFT)) & USB_ENDPTFLUSH_FERB_MASK) +#define USB_ENDPTFLUSH_FETB_MASK (0xFF0000U) +#define USB_ENDPTFLUSH_FETB_SHIFT (16U) +#define USB_ENDPTFLUSH_FETB(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTFLUSH_FETB_SHIFT)) & USB_ENDPTFLUSH_FETB_MASK) +/*! @} */ + +/*! @name ENDPTSTAT - Endpoint Status */ +/*! @{ */ +#define USB_ENDPTSTAT_ERBR_MASK (0xFFU) +#define USB_ENDPTSTAT_ERBR_SHIFT (0U) +#define USB_ENDPTSTAT_ERBR(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTSTAT_ERBR_SHIFT)) & USB_ENDPTSTAT_ERBR_MASK) +#define USB_ENDPTSTAT_ETBR_MASK (0xFF0000U) +#define USB_ENDPTSTAT_ETBR_SHIFT (16U) +#define USB_ENDPTSTAT_ETBR(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTSTAT_ETBR_SHIFT)) & USB_ENDPTSTAT_ETBR_MASK) +/*! @} */ + +/*! @name ENDPTCOMPLETE - Endpoint Complete */ +/*! @{ */ +#define USB_ENDPTCOMPLETE_ERCE_MASK (0xFFU) +#define USB_ENDPTCOMPLETE_ERCE_SHIFT (0U) +#define USB_ENDPTCOMPLETE_ERCE(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCOMPLETE_ERCE_SHIFT)) & USB_ENDPTCOMPLETE_ERCE_MASK) +#define USB_ENDPTCOMPLETE_ETCE_MASK (0xFF0000U) +#define USB_ENDPTCOMPLETE_ETCE_SHIFT (16U) +#define USB_ENDPTCOMPLETE_ETCE(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCOMPLETE_ETCE_SHIFT)) & USB_ENDPTCOMPLETE_ETCE_MASK) +/*! @} */ + +/*! @name ENDPTCTRL0 - Endpoint Control0 */ +/*! @{ */ +#define USB_ENDPTCTRL0_RXS_MASK (0x1U) +#define USB_ENDPTCTRL0_RXS_SHIFT (0U) +#define USB_ENDPTCTRL0_RXS(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL0_RXS_SHIFT)) & USB_ENDPTCTRL0_RXS_MASK) +#define USB_ENDPTCTRL0_RXT_MASK (0xCU) +#define USB_ENDPTCTRL0_RXT_SHIFT (2U) +#define USB_ENDPTCTRL0_RXT(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL0_RXT_SHIFT)) & USB_ENDPTCTRL0_RXT_MASK) +#define USB_ENDPTCTRL0_RXE_MASK (0x80U) +#define USB_ENDPTCTRL0_RXE_SHIFT (7U) +#define USB_ENDPTCTRL0_RXE(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL0_RXE_SHIFT)) & USB_ENDPTCTRL0_RXE_MASK) +#define USB_ENDPTCTRL0_TXS_MASK (0x10000U) +#define USB_ENDPTCTRL0_TXS_SHIFT (16U) +#define USB_ENDPTCTRL0_TXS(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL0_TXS_SHIFT)) & USB_ENDPTCTRL0_TXS_MASK) +#define USB_ENDPTCTRL0_TXT_MASK (0xC0000U) +#define USB_ENDPTCTRL0_TXT_SHIFT (18U) +#define USB_ENDPTCTRL0_TXT(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL0_TXT_SHIFT)) & USB_ENDPTCTRL0_TXT_MASK) +#define USB_ENDPTCTRL0_TXE_MASK (0x800000U) +#define USB_ENDPTCTRL0_TXE_SHIFT (23U) +#define USB_ENDPTCTRL0_TXE(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL0_TXE_SHIFT)) & USB_ENDPTCTRL0_TXE_MASK) +/*! @} */ + +/*! @name ENDPTCTRL - Endpoint Control 1..Endpoint Control 7 */ +/*! @{ */ +#define USB_ENDPTCTRL_RXS_MASK (0x1U) +#define USB_ENDPTCTRL_RXS_SHIFT (0U) +#define USB_ENDPTCTRL_RXS(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL_RXS_SHIFT)) & USB_ENDPTCTRL_RXS_MASK) +#define USB_ENDPTCTRL_RXD_MASK (0x2U) +#define USB_ENDPTCTRL_RXD_SHIFT (1U) +#define USB_ENDPTCTRL_RXD(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL_RXD_SHIFT)) & USB_ENDPTCTRL_RXD_MASK) +#define USB_ENDPTCTRL_RXT_MASK (0xCU) +#define USB_ENDPTCTRL_RXT_SHIFT (2U) +#define USB_ENDPTCTRL_RXT(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL_RXT_SHIFT)) & USB_ENDPTCTRL_RXT_MASK) +#define USB_ENDPTCTRL_RXI_MASK (0x20U) +#define USB_ENDPTCTRL_RXI_SHIFT (5U) +#define USB_ENDPTCTRL_RXI(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL_RXI_SHIFT)) & USB_ENDPTCTRL_RXI_MASK) +#define USB_ENDPTCTRL_RXR_MASK (0x40U) +#define USB_ENDPTCTRL_RXR_SHIFT (6U) +#define USB_ENDPTCTRL_RXR(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL_RXR_SHIFT)) & USB_ENDPTCTRL_RXR_MASK) +#define USB_ENDPTCTRL_RXE_MASK (0x80U) +#define USB_ENDPTCTRL_RXE_SHIFT (7U) +#define USB_ENDPTCTRL_RXE(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL_RXE_SHIFT)) & USB_ENDPTCTRL_RXE_MASK) +#define USB_ENDPTCTRL_TXS_MASK (0x10000U) +#define USB_ENDPTCTRL_TXS_SHIFT (16U) +#define USB_ENDPTCTRL_TXS(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL_TXS_SHIFT)) & USB_ENDPTCTRL_TXS_MASK) +#define USB_ENDPTCTRL_TXD_MASK (0x20000U) +#define USB_ENDPTCTRL_TXD_SHIFT (17U) +#define USB_ENDPTCTRL_TXD(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL_TXD_SHIFT)) & USB_ENDPTCTRL_TXD_MASK) +#define USB_ENDPTCTRL_TXT_MASK (0xC0000U) +#define USB_ENDPTCTRL_TXT_SHIFT (18U) +#define USB_ENDPTCTRL_TXT(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL_TXT_SHIFT)) & USB_ENDPTCTRL_TXT_MASK) +#define USB_ENDPTCTRL_TXI_MASK (0x200000U) +#define USB_ENDPTCTRL_TXI_SHIFT (21U) +#define USB_ENDPTCTRL_TXI(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL_TXI_SHIFT)) & USB_ENDPTCTRL_TXI_MASK) +#define USB_ENDPTCTRL_TXR_MASK (0x400000U) +#define USB_ENDPTCTRL_TXR_SHIFT (22U) +#define USB_ENDPTCTRL_TXR(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL_TXR_SHIFT)) & USB_ENDPTCTRL_TXR_MASK) +#define USB_ENDPTCTRL_TXE_MASK (0x800000U) +#define USB_ENDPTCTRL_TXE_SHIFT (23U) +#define USB_ENDPTCTRL_TXE(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL_TXE_SHIFT)) & USB_ENDPTCTRL_TXE_MASK) +/*! @} */ + +/* The count of USB_ENDPTCTRL */ +#define USB_ENDPTCTRL_COUNT (7U) + + +/*! + * @} + */ /* end of group USB_Register_Masks */ + + +/* USB - Peripheral instance base addresses */ +/** Peripheral USB1 base address */ +#define USB1_BASE (0x402E0000u) +/** Peripheral USB1 base pointer */ +#define USB1 ((USB_Type *)USB1_BASE) +/** Peripheral USB2 base address */ +#define USB2_BASE (0x402E0200u) +/** Peripheral USB2 base pointer */ +#define USB2 ((USB_Type *)USB2_BASE) +/** Array initializer of USB peripheral base addresses */ +#define USB_BASE_ADDRS { 0u, USB1_BASE, USB2_BASE } +/** Array initializer of USB peripheral base pointers */ +#define USB_BASE_PTRS { (USB_Type *)0u, USB1, USB2 } +/** Interrupt vectors for the USB peripheral type */ +#define USB_IRQS { NotAvail_IRQn, USB_OTG1_IRQn, USB_OTG2_IRQn } +/* Backward compatibility */ +#define GPTIMER0CTL GPTIMER0CTRL +#define GPTIMER1CTL GPTIMER1CTRL +#define USB_SBUSCFG SBUSCFG +#define EPLISTADDR ENDPTLISTADDR +#define EPSETUPSR ENDPTSETUPSTAT +#define EPPRIME ENDPTPRIME +#define EPFLUSH ENDPTFLUSH +#define EPSR ENDPTSTAT +#define EPCOMPLETE ENDPTCOMPLETE +#define EPCR ENDPTCTRL +#define EPCR0 ENDPTCTRL0 +#define USBHS_ID_ID_MASK USB_ID_ID_MASK +#define USBHS_ID_ID_SHIFT USB_ID_ID_SHIFT +#define USBHS_ID_ID(x) USB_ID_ID(x) +#define USBHS_ID_NID_MASK USB_ID_NID_MASK +#define USBHS_ID_NID_SHIFT USB_ID_NID_SHIFT +#define USBHS_ID_NID(x) USB_ID_NID(x) +#define USBHS_ID_REVISION_MASK USB_ID_REVISION_MASK +#define USBHS_ID_REVISION_SHIFT USB_ID_REVISION_SHIFT +#define USBHS_ID_REVISION(x) USB_ID_REVISION(x) +#define USBHS_HWGENERAL_PHYW_MASK USB_HWGENERAL_PHYW_MASK +#define USBHS_HWGENERAL_PHYW_SHIFT USB_HWGENERAL_PHYW_SHIFT +#define USBHS_HWGENERAL_PHYW(x) USB_HWGENERAL_PHYW(x) +#define USBHS_HWGENERAL_PHYM_MASK USB_HWGENERAL_PHYM_MASK +#define USBHS_HWGENERAL_PHYM_SHIFT USB_HWGENERAL_PHYM_SHIFT +#define USBHS_HWGENERAL_PHYM(x) USB_HWGENERAL_PHYM(x) +#define USBHS_HWGENERAL_SM_MASK USB_HWGENERAL_SM_MASK +#define USBHS_HWGENERAL_SM_SHIFT USB_HWGENERAL_SM_SHIFT +#define USBHS_HWGENERAL_SM(x) USB_HWGENERAL_SM(x) +#define USBHS_HWHOST_HC_MASK USB_HWHOST_HC_MASK +#define USBHS_HWHOST_HC_SHIFT USB_HWHOST_HC_SHIFT +#define USBHS_HWHOST_HC(x) USB_HWHOST_HC(x) +#define USBHS_HWHOST_NPORT_MASK USB_HWHOST_NPORT_MASK +#define USBHS_HWHOST_NPORT_SHIFT USB_HWHOST_NPORT_SHIFT +#define USBHS_HWHOST_NPORT(x) USB_HWHOST_NPORT(x) +#define USBHS_HWDEVICE_DC_MASK USB_HWDEVICE_DC_MASK +#define USBHS_HWDEVICE_DC_SHIFT USB_HWDEVICE_DC_SHIFT +#define USBHS_HWDEVICE_DC(x) USB_HWDEVICE_DC(x) +#define USBHS_HWDEVICE_DEVEP_MASK USB_HWDEVICE_DEVEP_MASK +#define USBHS_HWDEVICE_DEVEP_SHIFT USB_HWDEVICE_DEVEP_SHIFT +#define USBHS_HWDEVICE_DEVEP(x) USB_HWDEVICE_DEVEP(x) +#define USBHS_HWTXBUF_TXBURST_MASK USB_HWTXBUF_TXBURST_MASK +#define USBHS_HWTXBUF_TXBURST_SHIFT USB_HWTXBUF_TXBURST_SHIFT +#define USBHS_HWTXBUF_TXBURST(x) USB_HWTXBUF_TXBURST(x) +#define USBHS_HWTXBUF_TXCHANADD_MASK USB_HWTXBUF_TXCHANADD_MASK +#define USBHS_HWTXBUF_TXCHANADD_SHIFT USB_HWTXBUF_TXCHANADD_SHIFT +#define USBHS_HWTXBUF_TXCHANADD(x) USB_HWTXBUF_TXCHANADD(x) +#define USBHS_HWRXBUF_RXBURST_MASK USB_HWRXBUF_RXBURST_MASK +#define USBHS_HWRXBUF_RXBURST_SHIFT USB_HWRXBUF_RXBURST_SHIFT +#define USBHS_HWRXBUF_RXBURST(x) USB_HWRXBUF_RXBURST(x) +#define USBHS_HWRXBUF_RXADD_MASK USB_HWRXBUF_RXADD_MASK +#define USBHS_HWRXBUF_RXADD_SHIFT USB_HWRXBUF_RXADD_SHIFT +#define USBHS_HWRXBUF_RXADD(x) USB_HWRXBUF_RXADD(x) +#define USBHS_GPTIMER0LD_GPTLD_MASK USB_GPTIMER0LD_GPTLD_MASK +#define USBHS_GPTIMER0LD_GPTLD_SHIFT USB_GPTIMER0LD_GPTLD_SHIFT +#define USBHS_GPTIMER0LD_GPTLD(x) USB_GPTIMER0LD_GPTLD(x) +#define USBHS_GPTIMER0CTL_GPTCNT_MASK USB_GPTIMER0CTRL_GPTCNT_MASK +#define USBHS_GPTIMER0CTL_GPTCNT_SHIFT USB_GPTIMER0CTRL_GPTCNT_SHIFT +#define USBHS_GPTIMER0CTL_GPTCNT(x) USB_GPTIMER0CTRL_GPTCNT(x) +#define USBHS_GPTIMER0CTL_MODE_MASK USB_GPTIMER0CTRL_GPTMODE_MASK +#define USBHS_GPTIMER0CTL_MODE_SHIFT USB_GPTIMER0CTRL_GPTMODE_SHIFT +#define USBHS_GPTIMER0CTL_MODE(x) USB_GPTIMER0CTRL_GPTMODE(x) +#define USBHS_GPTIMER0CTL_RST_MASK USB_GPTIMER0CTRL_GPTRST_MASK +#define USBHS_GPTIMER0CTL_RST_SHIFT USB_GPTIMER0CTRL_GPTRST_SHIFT +#define USBHS_GPTIMER0CTL_RST(x) USB_GPTIMER0CTRL_GPTRST(x) +#define USBHS_GPTIMER0CTL_RUN_MASK USB_GPTIMER0CTRL_GPTRUN_MASK +#define USBHS_GPTIMER0CTL_RUN_SHIFT USB_GPTIMER0CTRL_GPTRUN_SHIFT +#define USBHS_GPTIMER0CTL_RUN(x) USB_GPTIMER0CTRL_GPTRUN(x) +#define USBHS_GPTIMER1LD_GPTLD_MASK USB_GPTIMER1LD_GPTLD_MASK +#define USBHS_GPTIMER1LD_GPTLD_SHIFT USB_GPTIMER1LD_GPTLD_SHIFT +#define USBHS_GPTIMER1LD_GPTLD(x) USB_GPTIMER1LD_GPTLD(x) +#define USBHS_GPTIMER1CTL_GPTCNT_MASK USB_GPTIMER1CTRL_GPTCNT_MASK +#define USBHS_GPTIMER1CTL_GPTCNT_SHIFT USB_GPTIMER1CTRL_GPTCNT_SHIFT +#define USBHS_GPTIMER1CTL_GPTCNT(x) USB_GPTIMER1CTRL_GPTCNT(x) +#define USBHS_GPTIMER1CTL_MODE_MASK USB_GPTIMER1CTRL_GPTMODE_MASK +#define USBHS_GPTIMER1CTL_MODE_SHIFT USB_GPTIMER1CTRL_GPTMODE_SHIFT +#define USBHS_GPTIMER1CTL_MODE(x) USB_GPTIMER1CTRL_GPTMODE(x) +#define USBHS_GPTIMER1CTL_RST_MASK USB_GPTIMER1CTRL_GPTRST_MASK +#define USBHS_GPTIMER1CTL_RST_SHIFT USB_GPTIMER1CTRL_GPTRST_SHIFT +#define USBHS_GPTIMER1CTL_RST(x) USB_GPTIMER1CTRL_GPTRST(x) +#define USBHS_GPTIMER1CTL_RUN_MASK USB_GPTIMER1CTRL_GPTRUN_MASK +#define USBHS_GPTIMER1CTL_RUN_SHIFT USB_GPTIMER1CTRL_GPTRUN_SHIFT +#define USBHS_GPTIMER1CTL_RUN(x) USB_GPTIMER1CTRL_GPTRUN(x) +#define USBHS_USB_SBUSCFG_BURSTMODE_MASK USB_SBUSCFG_AHBBRST_MASK +#define USBHS_USB_SBUSCFG_BURSTMODE_SHIFT USB_SBUSCFG_AHBBRST_SHIFT +#define USBHS_USB_SBUSCFG_BURSTMODE(x) USB_SBUSCFG_AHBBRST(x) +#define USBHS_HCIVERSION_CAPLENGTH(x) USB_HCIVERSION_CAPLENGTH(x) +#define USBHS_HCIVERSION_HCIVERSION_MASK USB_HCIVERSION_HCIVERSION_MASK +#define USBHS_HCIVERSION_HCIVERSION_SHIFT USB_HCIVERSION_HCIVERSION_SHIFT +#define USBHS_HCIVERSION_HCIVERSION(x) USB_HCIVERSION_HCIVERSION(x) +#define USBHS_HCSPARAMS_N_PORTS_MASK USB_HCSPARAMS_N_PORTS_MASK +#define USBHS_HCSPARAMS_N_PORTS_SHIFT USB_HCSPARAMS_N_PORTS_SHIFT +#define USBHS_HCSPARAMS_N_PORTS(x) USB_HCSPARAMS_N_PORTS(x) +#define USBHS_HCSPARAMS_PPC_MASK USB_HCSPARAMS_PPC_MASK +#define USBHS_HCSPARAMS_PPC_SHIFT USB_HCSPARAMS_PPC_SHIFT +#define USBHS_HCSPARAMS_PPC(x) USB_HCSPARAMS_PPC(x) +#define USBHS_HCSPARAMS_N_PCC_MASK USB_HCSPARAMS_N_PCC_MASK +#define USBHS_HCSPARAMS_N_PCC_SHIFT USB_HCSPARAMS_N_PCC_SHIFT +#define USBHS_HCSPARAMS_N_PCC(x) USB_HCSPARAMS_N_PCC(x) +#define USBHS_HCSPARAMS_N_CC_MASK USB_HCSPARAMS_N_CC_MASK +#define USBHS_HCSPARAMS_N_CC_SHIFT USB_HCSPARAMS_N_CC_SHIFT +#define USBHS_HCSPARAMS_N_CC(x) USB_HCSPARAMS_N_CC(x) +#define USBHS_HCSPARAMS_PI_MASK USB_HCSPARAMS_PI_MASK +#define USBHS_HCSPARAMS_PI_SHIFT USB_HCSPARAMS_PI_SHIFT +#define USBHS_HCSPARAMS_PI(x) USB_HCSPARAMS_PI(x) +#define USBHS_HCSPARAMS_N_PTT_MASK USB_HCSPARAMS_N_PTT_MASK +#define USBHS_HCSPARAMS_N_PTT_SHIFT USB_HCSPARAMS_N_PTT_SHIFT +#define USBHS_HCSPARAMS_N_PTT(x) USB_HCSPARAMS_N_PTT(x) +#define USBHS_HCSPARAMS_N_TT_MASK USB_HCSPARAMS_N_TT_MASK +#define USBHS_HCSPARAMS_N_TT_SHIFT USB_HCSPARAMS_N_TT_SHIFT +#define USBHS_HCSPARAMS_N_TT(x) USB_HCSPARAMS_N_TT(x) +#define USBHS_HCCPARAMS_ADC_MASK USB_HCCPARAMS_ADC_MASK +#define USBHS_HCCPARAMS_ADC_SHIFT USB_HCCPARAMS_ADC_SHIFT +#define USBHS_HCCPARAMS_ADC(x) USB_HCCPARAMS_ADC(x) +#define USBHS_HCCPARAMS_PFL_MASK USB_HCCPARAMS_PFL_MASK +#define USBHS_HCCPARAMS_PFL_SHIFT USB_HCCPARAMS_PFL_SHIFT +#define USBHS_HCCPARAMS_PFL(x) USB_HCCPARAMS_PFL(x) +#define USBHS_HCCPARAMS_ASP_MASK USB_HCCPARAMS_ASP_MASK +#define USBHS_HCCPARAMS_ASP_SHIFT USB_HCCPARAMS_ASP_SHIFT +#define USBHS_HCCPARAMS_ASP(x) USB_HCCPARAMS_ASP(x) +#define USBHS_HCCPARAMS_IST_MASK USB_HCCPARAMS_IST_MASK +#define USBHS_HCCPARAMS_IST_SHIFT USB_HCCPARAMS_IST_SHIFT +#define USBHS_HCCPARAMS_IST(x) USB_HCCPARAMS_IST(x) +#define USBHS_HCCPARAMS_EECP_MASK USB_HCCPARAMS_EECP_MASK +#define USBHS_HCCPARAMS_EECP_SHIFT USB_HCCPARAMS_EECP_SHIFT +#define USBHS_HCCPARAMS_EECP(x) USB_HCCPARAMS_EECP(x) +#define USBHS_DCIVERSION_DCIVERSION_MASK USB_DCIVERSION_DCIVERSION_MASK +#define USBHS_DCIVERSION_DCIVERSION_SHIFT USB_DCIVERSION_DCIVERSION_SHIFT +#define USBHS_DCIVERSION_DCIVERSION(x) USB_DCIVERSION_DCIVERSION(x) +#define USBHS_DCCPARAMS_DEN_MASK USB_DCCPARAMS_DEN_MASK +#define USBHS_DCCPARAMS_DEN_SHIFT USB_DCCPARAMS_DEN_SHIFT +#define USBHS_DCCPARAMS_DEN(x) USB_DCCPARAMS_DEN(x) +#define USBHS_DCCPARAMS_DC_MASK USB_DCCPARAMS_DC_MASK +#define USBHS_DCCPARAMS_DC_SHIFT USB_DCCPARAMS_DC_SHIFT +#define USBHS_DCCPARAMS_DC(x) USB_DCCPARAMS_DC(x) +#define USBHS_DCCPARAMS_HC_MASK USB_DCCPARAMS_HC_MASK +#define USBHS_DCCPARAMS_HC_SHIFT USB_DCCPARAMS_HC_SHIFT +#define USBHS_DCCPARAMS_HC(x) USB_DCCPARAMS_HC(x) +#define USBHS_USBCMD_RS_MASK USB_USBCMD_RS_MASK +#define USBHS_USBCMD_RS_SHIFT USB_USBCMD_RS_SHIFT +#define USBHS_USBCMD_RS(x) USB_USBCMD_RS(x) +#define USBHS_USBCMD_RST_MASK USB_USBCMD_RST_MASK +#define USBHS_USBCMD_RST_SHIFT USB_USBCMD_RST_SHIFT +#define USBHS_USBCMD_RST(x) USB_USBCMD_RST(x) +#define USBHS_USBCMD_FS_MASK USB_USBCMD_FS_1_MASK +#define USBHS_USBCMD_FS_SHIFT USB_USBCMD_FS_1_SHIFT +#define USBHS_USBCMD_FS(x) USB_USBCMD_FS_1(x) +#define USBHS_USBCMD_PSE_MASK USB_USBCMD_PSE_MASK +#define USBHS_USBCMD_PSE_SHIFT USB_USBCMD_PSE_SHIFT +#define USBHS_USBCMD_PSE(x) USB_USBCMD_PSE(x) +#define USBHS_USBCMD_ASE_MASK USB_USBCMD_ASE_MASK +#define USBHS_USBCMD_ASE_SHIFT USB_USBCMD_ASE_SHIFT +#define USBHS_USBCMD_ASE(x) USB_USBCMD_ASE(x) +#define USBHS_USBCMD_IAA_MASK USB_USBCMD_IAA_MASK +#define USBHS_USBCMD_IAA_SHIFT USB_USBCMD_IAA_SHIFT +#define USBHS_USBCMD_IAA(x) USB_USBCMD_IAA(x) +#define USBHS_USBCMD_ASP_MASK USB_USBCMD_ASP_MASK +#define USBHS_USBCMD_ASP_SHIFT USB_USBCMD_ASP_SHIFT +#define USBHS_USBCMD_ASP(x) USB_USBCMD_ASP(x) +#define USBHS_USBCMD_ASPE_MASK USB_USBCMD_ASPE_MASK +#define USBHS_USBCMD_ASPE_SHIFT USB_USBCMD_ASPE_SHIFT +#define USBHS_USBCMD_ASPE(x) USB_USBCMD_ASPE(x) +#define USBHS_USBCMD_ATDTW_MASK USB_USBCMD_ATDTW_MASK +#define USBHS_USBCMD_ATDTW_SHIFT USB_USBCMD_ATDTW_SHIFT +#define USBHS_USBCMD_ATDTW(x) USB_USBCMD_ATDTW(x) +#define USBHS_USBCMD_SUTW_MASK USB_USBCMD_SUTW_MASK +#define USBHS_USBCMD_SUTW_SHIFT USB_USBCMD_SUTW_SHIFT +#define USBHS_USBCMD_SUTW(x) USB_USBCMD_SUTW(x) +#define USBHS_USBCMD_FS2_MASK USB_USBCMD_FS_2_MASK +#define USBHS_USBCMD_FS2_SHIFT USB_USBCMD_FS_2_SHIFT +#define USBHS_USBCMD_FS2(x) USB_USBCMD_FS_2(x) +#define USBHS_USBCMD_ITC_MASK USB_USBCMD_ITC_MASK +#define USBHS_USBCMD_ITC_SHIFT USB_USBCMD_ITC_SHIFT +#define USBHS_USBCMD_ITC(x) USB_USBCMD_ITC(x) +#define USBHS_USBSTS_UI_MASK USB_USBSTS_UI_MASK +#define USBHS_USBSTS_UI_SHIFT USB_USBSTS_UI_SHIFT +#define USBHS_USBSTS_UI(x) USB_USBSTS_UI(x) +#define USBHS_USBSTS_UEI_MASK USB_USBSTS_UEI_MASK +#define USBHS_USBSTS_UEI_SHIFT USB_USBSTS_UEI_SHIFT +#define USBHS_USBSTS_UEI(x) USB_USBSTS_UEI(x) +#define USBHS_USBSTS_PCI_MASK USB_USBSTS_PCI_MASK +#define USBHS_USBSTS_PCI_SHIFT USB_USBSTS_PCI_SHIFT +#define USBHS_USBSTS_PCI(x) USB_USBSTS_PCI(x) +#define USBHS_USBSTS_FRI_MASK USB_USBSTS_FRI_MASK +#define USBHS_USBSTS_FRI_SHIFT USB_USBSTS_FRI_SHIFT +#define USBHS_USBSTS_FRI(x) USB_USBSTS_FRI(x) +#define USBHS_USBSTS_SEI_MASK USB_USBSTS_SEI_MASK +#define USBHS_USBSTS_SEI_SHIFT USB_USBSTS_SEI_SHIFT +#define USBHS_USBSTS_SEI(x) USB_USBSTS_SEI(x) +#define USBHS_USBSTS_AAI_MASK USB_USBSTS_AAI_MASK +#define USBHS_USBSTS_AAI_SHIFT USB_USBSTS_AAI_SHIFT +#define USBHS_USBSTS_AAI(x) USB_USBSTS_AAI(x) +#define USBHS_USBSTS_URI_MASK USB_USBSTS_URI_MASK +#define USBHS_USBSTS_URI_SHIFT USB_USBSTS_URI_SHIFT +#define USBHS_USBSTS_URI(x) USB_USBSTS_URI(x) +#define USBHS_USBSTS_SRI_MASK USB_USBSTS_SRI_MASK +#define USBHS_USBSTS_SRI_SHIFT USB_USBSTS_SRI_SHIFT +#define USBHS_USBSTS_SRI(x) USB_USBSTS_SRI(x) +#define USBHS_USBSTS_SLI_MASK USB_USBSTS_SLI_MASK +#define USBHS_USBSTS_SLI_SHIFT USB_USBSTS_SLI_SHIFT +#define USBHS_USBSTS_SLI(x) USB_USBSTS_SLI(x) +#define USBHS_USBSTS_ULPII_MASK USB_USBSTS_ULPII_MASK +#define USBHS_USBSTS_ULPII_SHIFT USB_USBSTS_ULPII_SHIFT +#define USBHS_USBSTS_ULPII(x) USB_USBSTS_ULPII(x) +#define USBHS_USBSTS_HCH_MASK USB_USBSTS_HCH_MASK +#define USBHS_USBSTS_HCH_SHIFT USB_USBSTS_HCH_SHIFT +#define USBHS_USBSTS_HCH(x) USB_USBSTS_HCH(x) +#define USBHS_USBSTS_RCL_MASK USB_USBSTS_RCL_MASK +#define USBHS_USBSTS_RCL_SHIFT USB_USBSTS_RCL_SHIFT +#define USBHS_USBSTS_RCL(x) USB_USBSTS_RCL(x) +#define USBHS_USBSTS_PS_MASK USB_USBSTS_PS_MASK +#define USBHS_USBSTS_PS_SHIFT USB_USBSTS_PS_SHIFT +#define USBHS_USBSTS_PS(x) USB_USBSTS_PS(x) +#define USBHS_USBSTS_AS_MASK USB_USBSTS_AS_MASK +#define USBHS_USBSTS_AS_SHIFT USB_USBSTS_AS_SHIFT +#define USBHS_USBSTS_AS(x) USB_USBSTS_AS(x) +#define USBHS_USBSTS_NAKI_MASK USB_USBSTS_NAKI_MASK +#define USBHS_USBSTS_NAKI_SHIFT USB_USBSTS_NAKI_SHIFT +#define USBHS_USBSTS_NAKI(x) USB_USBSTS_NAKI(x) +#define USBHS_USBSTS_TI0_MASK USB_USBSTS_TI0_MASK +#define USBHS_USBSTS_TI0_SHIFT USB_USBSTS_TI0_SHIFT +#define USBHS_USBSTS_TI0(x) USB_USBSTS_TI0(x) +#define USBHS_USBSTS_TI1_MASK USB_USBSTS_TI1_MASK +#define USBHS_USBSTS_TI1_SHIFT USB_USBSTS_TI1_SHIFT +#define USBHS_USBSTS_TI1(x) USB_USBSTS_TI1(x) +#define USBHS_USBINTR_UE_MASK USB_USBINTR_UE_MASK +#define USBHS_USBINTR_UE_SHIFT USB_USBINTR_UE_SHIFT +#define USBHS_USBINTR_UE(x) USB_USBINTR_UE(x) +#define USBHS_USBINTR_UEE_MASK USB_USBINTR_UEE_MASK +#define USBHS_USBINTR_UEE_SHIFT USB_USBINTR_UEE_SHIFT +#define USBHS_USBINTR_UEE(x) USB_USBINTR_UEE(x) +#define USBHS_USBINTR_PCE_MASK USB_USBINTR_PCE_MASK +#define USBHS_USBINTR_PCE_SHIFT USB_USBINTR_PCE_SHIFT +#define USBHS_USBINTR_PCE(x) USB_USBINTR_PCE(x) +#define USBHS_USBINTR_FRE_MASK USB_USBINTR_FRE_MASK +#define USBHS_USBINTR_FRE_SHIFT USB_USBINTR_FRE_SHIFT +#define USBHS_USBINTR_FRE(x) USB_USBINTR_FRE(x) +#define USBHS_USBINTR_SEE_MASK USB_USBINTR_SEE_MASK +#define USBHS_USBINTR_SEE_SHIFT USB_USBINTR_SEE_SHIFT +#define USBHS_USBINTR_SEE(x) USB_USBINTR_SEE(x) +#define USBHS_USBINTR_AAE_MASK USB_USBINTR_AAE_MASK +#define USBHS_USBINTR_AAE_SHIFT USB_USBINTR_AAE_SHIFT +#define USBHS_USBINTR_AAE(x) USB_USBINTR_AAE(x) +#define USBHS_USBINTR_URE_MASK USB_USBINTR_URE_MASK +#define USBHS_USBINTR_URE_SHIFT USB_USBINTR_URE_SHIFT +#define USBHS_USBINTR_URE(x) USB_USBINTR_URE(x) +#define USBHS_USBINTR_SRE_MASK USB_USBINTR_SRE_MASK +#define USBHS_USBINTR_SRE_SHIFT USB_USBINTR_SRE_SHIFT +#define USBHS_USBINTR_SRE(x) USB_USBINTR_SRE(x) +#define USBHS_USBINTR_SLE_MASK USB_USBINTR_SLE_MASK +#define USBHS_USBINTR_SLE_SHIFT USB_USBINTR_SLE_SHIFT +#define USBHS_USBINTR_SLE(x) USB_USBINTR_SLE(x) +#define USBHS_USBINTR_ULPIE_MASK USB_USBINTR_ULPIE_MASK +#define USBHS_USBINTR_ULPIE_SHIFT USB_USBINTR_ULPIE_SHIFT +#define USBHS_USBINTR_ULPIE(x) USB_USBINTR_ULPIE(x) +#define USBHS_USBINTR_NAKE_MASK USB_USBINTR_NAKE_MASK +#define USBHS_USBINTR_NAKE_SHIFT USB_USBINTR_NAKE_SHIFT +#define USBHS_USBINTR_NAKE(x) USB_USBINTR_NAKE(x) +#define USBHS_USBINTR_UAIE_MASK USB_USBINTR_UAIE_MASK +#define USBHS_USBINTR_UAIE_SHIFT USB_USBINTR_UAIE_SHIFT +#define USBHS_USBINTR_UAIE(x) USB_USBINTR_UAIE(x) +#define USBHS_USBINTR_UPIE_MASK USB_USBINTR_UPIE_MASK +#define USBHS_USBINTR_UPIE_SHIFT USB_USBINTR_UPIE_SHIFT +#define USBHS_USBINTR_UPIE(x) USB_USBINTR_UPIE(x) +#define USBHS_USBINTR_TIE0_MASK USB_USBINTR_TIE0_MASK +#define USBHS_USBINTR_TIE0_SHIFT USB_USBINTR_TIE0_SHIFT +#define USBHS_USBINTR_TIE0(x) USB_USBINTR_TIE0(x) +#define USBHS_USBINTR_TIE1_MASK USB_USBINTR_TIE1_MASK +#define USBHS_USBINTR_TIE1_SHIFT USB_USBINTR_TIE1_SHIFT +#define USBHS_USBINTR_TIE1(x) USB_USBINTR_TIE1(x) +#define USBHS_FRINDEX_FRINDEX_MASK USB_FRINDEX_FRINDEX_MASK +#define USBHS_FRINDEX_FRINDEX_SHIFT USB_FRINDEX_FRINDEX_SHIFT +#define USBHS_FRINDEX_FRINDEX(x) USB_FRINDEX_FRINDEX(x) +#define USBHS_DEVICEADDR_USBADRA_MASK USB_DEVICEADDR_USBADRA_MASK +#define USBHS_DEVICEADDR_USBADRA_SHIFT USB_DEVICEADDR_USBADRA_SHIFT +#define USBHS_DEVICEADDR_USBADRA(x) USB_DEVICEADDR_USBADRA(x) +#define USBHS_DEVICEADDR_USBADR_MASK USB_DEVICEADDR_USBADR_MASK +#define USBHS_DEVICEADDR_USBADR_SHIFT USB_DEVICEADDR_USBADR_SHIFT +#define USBHS_DEVICEADDR_USBADR(x) USB_DEVICEADDR_USBADR(x) +#define USBHS_PERIODICLISTBASE_PERBASE_MASK USB_PERIODICLISTBASE_BASEADR_MASK +#define USBHS_PERIODICLISTBASE_PERBASE_SHIFT USB_PERIODICLISTBASE_BASEADR_SHIFT +#define USBHS_PERIODICLISTBASE_PERBASE(x) USB_PERIODICLISTBASE_BASEADR(x) +#define USBHS_ASYNCLISTADDR_ASYBASE_MASK USB_ASYNCLISTADDR_ASYBASE_MASK +#define USBHS_ASYNCLISTADDR_ASYBASE_SHIFT USB_ASYNCLISTADDR_ASYBASE_SHIFT +#define USBHS_ASYNCLISTADDR_ASYBASE(x) USB_ASYNCLISTADDR_ASYBASE(x) +#define USBHS_EPLISTADDR_EPBASE_MASK USB_ENDPTLISTADDR_EPBASE_MASK +#define USBHS_EPLISTADDR_EPBASE_SHIFT USB_ENDPTLISTADDR_EPBASE_SHIFT +#define USBHS_EPLISTADDR_EPBASE(x) USB_ENDPTLISTADDR_EPBASE(x) +#define USBHS_BURSTSIZE_RXPBURST_MASK USB_BURSTSIZE_RXPBURST_MASK +#define USBHS_BURSTSIZE_RXPBURST_SHIFT USB_BURSTSIZE_RXPBURST_SHIFT +#define USBHS_BURSTSIZE_RXPBURST(x) USB_BURSTSIZE_RXPBURST(x) +#define USBHS_BURSTSIZE_TXPBURST_MASK USB_BURSTSIZE_TXPBURST_MASK +#define USBHS_BURSTSIZE_TXPBURST_SHIFT USB_BURSTSIZE_TXPBURST_SHIFT +#define USBHS_BURSTSIZE_TXPBURST(x) USB_BURSTSIZE_TXPBURST(x) +#define USBHS_TXFILLTUNING_TXSCHOH_MASK USB_TXFILLTUNING_TXSCHOH_MASK +#define USBHS_TXFILLTUNING_TXSCHOH_SHIFT USB_TXFILLTUNING_TXSCHOH_SHIFT +#define USBHS_TXFILLTUNING_TXSCHOH(x) USB_TXFILLTUNING_TXSCHOH(x) +#define USBHS_TXFILLTUNING_TXSCHHEALTH_MASK USB_TXFILLTUNING_TXSCHHEALTH_MASK +#define USBHS_TXFILLTUNING_TXSCHHEALTH_SHIFT USB_TXFILLTUNING_TXSCHHEALTH_SHIFT +#define USBHS_TXFILLTUNING_TXSCHHEALTH(x) USB_TXFILLTUNING_TXSCHHEALTH(x) +#define USBHS_TXFILLTUNING_TXFIFOTHRES_MASK USB_TXFILLTUNING_TXFIFOTHRES_MASK +#define USBHS_TXFILLTUNING_TXFIFOTHRES_SHIFT USB_TXFILLTUNING_TXFIFOTHRES_SHIFT +#define USBHS_TXFILLTUNING_TXFIFOTHRES(x) USB_TXFILLTUNING_TXFIFOTHRES(x) +#define USBHS_ENDPTNAK_EPRN_MASK USB_ENDPTNAK_EPRN_MASK +#define USBHS_ENDPTNAK_EPRN_SHIFT USB_ENDPTNAK_EPRN_SHIFT +#define USBHS_ENDPTNAK_EPRN(x) USB_ENDPTNAK_EPRN(x) +#define USBHS_ENDPTNAK_EPTN_MASK USB_ENDPTNAK_EPTN_MASK +#define USBHS_ENDPTNAK_EPTN_SHIFT USB_ENDPTNAK_EPTN_SHIFT +#define USBHS_ENDPTNAK_EPTN(x) USB_ENDPTNAK_EPTN(x) +#define USBHS_ENDPTNAKEN_EPRNE_MASK USB_ENDPTNAKEN_EPRNE_MASK +#define USBHS_ENDPTNAKEN_EPRNE_SHIFT USB_ENDPTNAKEN_EPRNE_SHIFT +#define USBHS_ENDPTNAKEN_EPRNE(x) USB_ENDPTNAKEN_EPRNE(x) +#define USBHS_ENDPTNAKEN_EPTNE_MASK USB_ENDPTNAKEN_EPTNE_MASK +#define USBHS_ENDPTNAKEN_EPTNE_SHIFT USB_ENDPTNAKEN_EPTNE_SHIFT +#define USBHS_ENDPTNAKEN_EPTNE(x) USB_ENDPTNAKEN_EPTNE(x) +#define USBHS_CONFIGFLAG_CF_MASK USB_CONFIGFLAG_CF_MASK +#define USBHS_CONFIGFLAG_CF_SHIFT USB_CONFIGFLAG_CF_SHIFT +#define USBHS_CONFIGFLAG_CF(x) USB_CONFIGFLAG_CF(x) +#define USBHS_PORTSC1_CCS_MASK USB_PORTSC1_CCS_MASK +#define USBHS_PORTSC1_CCS_SHIFT USB_PORTSC1_CCS_SHIFT +#define USBHS_PORTSC1_CCS(x) USB_PORTSC1_CCS(x) +#define USBHS_PORTSC1_CSC_MASK USB_PORTSC1_CSC_MASK +#define USBHS_PORTSC1_CSC_SHIFT USB_PORTSC1_CSC_SHIFT +#define USBHS_PORTSC1_CSC(x) USB_PORTSC1_CSC(x) +#define USBHS_PORTSC1_PE_MASK USB_PORTSC1_PE_MASK +#define USBHS_PORTSC1_PE_SHIFT USB_PORTSC1_PE_SHIFT +#define USBHS_PORTSC1_PE(x) USB_PORTSC1_PE(x) +#define USBHS_PORTSC1_PEC_MASK USB_PORTSC1_PEC_MASK +#define USBHS_PORTSC1_PEC_SHIFT USB_PORTSC1_PEC_SHIFT +#define USBHS_PORTSC1_PEC(x) USB_PORTSC1_PEC(x) +#define USBHS_PORTSC1_OCA_MASK USB_PORTSC1_OCA_MASK +#define USBHS_PORTSC1_OCA_SHIFT USB_PORTSC1_OCA_SHIFT +#define USBHS_PORTSC1_OCA(x) USB_PORTSC1_OCA(x) +#define USBHS_PORTSC1_OCC_MASK USB_PORTSC1_OCC_MASK +#define USBHS_PORTSC1_OCC_SHIFT USB_PORTSC1_OCC_SHIFT +#define USBHS_PORTSC1_OCC(x) USB_PORTSC1_OCC(x) +#define USBHS_PORTSC1_FPR_MASK USB_PORTSC1_FPR_MASK +#define USBHS_PORTSC1_FPR_SHIFT USB_PORTSC1_FPR_SHIFT +#define USBHS_PORTSC1_FPR(x) USB_PORTSC1_FPR(x) +#define USBHS_PORTSC1_SUSP_MASK USB_PORTSC1_SUSP_MASK +#define USBHS_PORTSC1_SUSP_SHIFT USB_PORTSC1_SUSP_SHIFT +#define USBHS_PORTSC1_SUSP(x) USB_PORTSC1_SUSP(x) +#define USBHS_PORTSC1_PR_MASK USB_PORTSC1_PR_MASK +#define USBHS_PORTSC1_PR_SHIFT USB_PORTSC1_PR_SHIFT +#define USBHS_PORTSC1_PR(x) USB_PORTSC1_PR(x) +#define USBHS_PORTSC1_HSP_MASK USB_PORTSC1_HSP_MASK +#define USBHS_PORTSC1_HSP_SHIFT USB_PORTSC1_HSP_SHIFT +#define USBHS_PORTSC1_HSP(x) USB_PORTSC1_HSP(x) +#define USBHS_PORTSC1_LS_MASK USB_PORTSC1_LS_MASK +#define USBHS_PORTSC1_LS_SHIFT USB_PORTSC1_LS_SHIFT +#define USBHS_PORTSC1_LS(x) USB_PORTSC1_LS(x) +#define USBHS_PORTSC1_PP_MASK USB_PORTSC1_PP_MASK +#define USBHS_PORTSC1_PP_SHIFT USB_PORTSC1_PP_SHIFT +#define USBHS_PORTSC1_PP(x) USB_PORTSC1_PP(x) +#define USBHS_PORTSC1_PO_MASK USB_PORTSC1_PO_MASK +#define USBHS_PORTSC1_PO_SHIFT USB_PORTSC1_PO_SHIFT +#define USBHS_PORTSC1_PO(x) USB_PORTSC1_PO(x) +#define USBHS_PORTSC1_PIC_MASK USB_PORTSC1_PIC_MASK +#define USBHS_PORTSC1_PIC_SHIFT USB_PORTSC1_PIC_SHIFT +#define USBHS_PORTSC1_PIC(x) USB_PORTSC1_PIC(x) +#define USBHS_PORTSC1_PTC_MASK USB_PORTSC1_PTC_MASK +#define USBHS_PORTSC1_PTC_SHIFT USB_PORTSC1_PTC_SHIFT +#define USBHS_PORTSC1_PTC(x) USB_PORTSC1_PTC(x) +#define USBHS_PORTSC1_WKCN_MASK USB_PORTSC1_WKCN_MASK +#define USBHS_PORTSC1_WKCN_SHIFT USB_PORTSC1_WKCN_SHIFT +#define USBHS_PORTSC1_WKCN(x) USB_PORTSC1_WKCN(x) +#define USBHS_PORTSC1_WKDS_MASK USB_PORTSC1_WKDC_MASK +#define USBHS_PORTSC1_WKDS_SHIFT USB_PORTSC1_WKDC_SHIFT +#define USBHS_PORTSC1_WKDS(x) USB_PORTSC1_WKDC(x) +#define USBHS_PORTSC1_WKOC_MASK USB_PORTSC1_WKOC_MASK +#define USBHS_PORTSC1_WKOC_SHIFT USB_PORTSC1_WKOC_SHIFT +#define USBHS_PORTSC1_WKOC(x) USB_PORTSC1_WKOC(x) +#define USBHS_PORTSC1_PHCD_MASK USB_PORTSC1_PHCD_MASK +#define USBHS_PORTSC1_PHCD_SHIFT USB_PORTSC1_PHCD_SHIFT +#define USBHS_PORTSC1_PHCD(x) USB_PORTSC1_PHCD(x) +#define USBHS_PORTSC1_PFSC_MASK USB_PORTSC1_PFSC_MASK +#define USBHS_PORTSC1_PFSC_SHIFT USB_PORTSC1_PFSC_SHIFT +#define USBHS_PORTSC1_PFSC(x) USB_PORTSC1_PFSC(x) +#define USBHS_PORTSC1_PTS2_MASK USB_PORTSC1_PTS_2_MASK +#define USBHS_PORTSC1_PTS2_SHIFT USB_PORTSC1_PTS_2_SHIFT +#define USBHS_PORTSC1_PTS2(x) USB_PORTSC1_PTS_2(x) +#define USBHS_PORTSC1_PSPD_MASK USB_PORTSC1_PSPD_MASK +#define USBHS_PORTSC1_PSPD_SHIFT USB_PORTSC1_PSPD_SHIFT +#define USBHS_PORTSC1_PSPD(x) USB_PORTSC1_PSPD(x) +#define USBHS_PORTSC1_PTW_MASK USB_PORTSC1_PTW_MASK +#define USBHS_PORTSC1_PTW_SHIFT USB_PORTSC1_PTW_SHIFT +#define USBHS_PORTSC1_PTW(x) USB_PORTSC1_PTW(x) +#define USBHS_PORTSC1_STS_MASK USB_PORTSC1_STS_MASK +#define USBHS_PORTSC1_STS_SHIFT USB_PORTSC1_STS_SHIFT +#define USBHS_PORTSC1_STS(x) USB_PORTSC1_STS(x) +#define USBHS_PORTSC1_PTS_MASK USB_PORTSC1_PTS_1_MASK +#define USBHS_PORTSC1_PTS_SHIFT USB_PORTSC1_PTS_1_SHIFT +#define USBHS_PORTSC1_PTS(x) USB_PORTSC1_PTS_1(x) +#define USBHS_OTGSC_VD_MASK USB_OTGSC_VD_MASK +#define USBHS_OTGSC_VD_SHIFT USB_OTGSC_VD_SHIFT +#define USBHS_OTGSC_VD(x) USB_OTGSC_VD(x) +#define USBHS_OTGSC_VC_MASK USB_OTGSC_VC_MASK +#define USBHS_OTGSC_VC_SHIFT USB_OTGSC_VC_SHIFT +#define USBHS_OTGSC_VC(x) USB_OTGSC_VC(x) +#define USBHS_OTGSC_OT_MASK USB_OTGSC_OT_MASK +#define USBHS_OTGSC_OT_SHIFT USB_OTGSC_OT_SHIFT +#define USBHS_OTGSC_OT(x) USB_OTGSC_OT(x) +#define USBHS_OTGSC_DP_MASK USB_OTGSC_DP_MASK +#define USBHS_OTGSC_DP_SHIFT USB_OTGSC_DP_SHIFT +#define USBHS_OTGSC_DP(x) USB_OTGSC_DP(x) +#define USBHS_OTGSC_IDPU_MASK USB_OTGSC_IDPU_MASK +#define USBHS_OTGSC_IDPU_SHIFT USB_OTGSC_IDPU_SHIFT +#define USBHS_OTGSC_IDPU(x) USB_OTGSC_IDPU(x) +#define USBHS_OTGSC_ID_MASK USB_OTGSC_ID_MASK +#define USBHS_OTGSC_ID_SHIFT USB_OTGSC_ID_SHIFT +#define USBHS_OTGSC_ID(x) USB_OTGSC_ID(x) +#define USBHS_OTGSC_AVV_MASK USB_OTGSC_AVV_MASK +#define USBHS_OTGSC_AVV_SHIFT USB_OTGSC_AVV_SHIFT +#define USBHS_OTGSC_AVV(x) USB_OTGSC_AVV(x) +#define USBHS_OTGSC_ASV_MASK USB_OTGSC_ASV_MASK +#define USBHS_OTGSC_ASV_SHIFT USB_OTGSC_ASV_SHIFT +#define USBHS_OTGSC_ASV(x) USB_OTGSC_ASV(x) +#define USBHS_OTGSC_BSV_MASK USB_OTGSC_BSV_MASK +#define USBHS_OTGSC_BSV_SHIFT USB_OTGSC_BSV_SHIFT +#define USBHS_OTGSC_BSV(x) USB_OTGSC_BSV(x) +#define USBHS_OTGSC_BSE_MASK USB_OTGSC_BSE_MASK +#define USBHS_OTGSC_BSE_SHIFT USB_OTGSC_BSE_SHIFT +#define USBHS_OTGSC_BSE(x) USB_OTGSC_BSE(x) +#define USBHS_OTGSC_MST_MASK USB_OTGSC_TOG_1MS_MASK +#define USBHS_OTGSC_MST_SHIFT USB_OTGSC_TOG_1MS_SHIFT +#define USBHS_OTGSC_MST(x) USB_OTGSC_TOG_1MS(x) +#define USBHS_OTGSC_DPS_MASK USB_OTGSC_DPS_MASK +#define USBHS_OTGSC_DPS_SHIFT USB_OTGSC_DPS_SHIFT +#define USBHS_OTGSC_DPS(x) USB_OTGSC_DPS(x) +#define USBHS_OTGSC_IDIS_MASK USB_OTGSC_IDIS_MASK +#define USBHS_OTGSC_IDIS_SHIFT USB_OTGSC_IDIS_SHIFT +#define USBHS_OTGSC_IDIS(x) USB_OTGSC_IDIS(x) +#define USBHS_OTGSC_AVVIS_MASK USB_OTGSC_AVVIS_MASK +#define USBHS_OTGSC_AVVIS_SHIFT USB_OTGSC_AVVIS_SHIFT +#define USBHS_OTGSC_AVVIS(x) USB_OTGSC_AVVIS(x) +#define USBHS_OTGSC_ASVIS_MASK USB_OTGSC_ASVIS_MASK +#define USBHS_OTGSC_ASVIS_SHIFT USB_OTGSC_ASVIS_SHIFT +#define USBHS_OTGSC_ASVIS(x) USB_OTGSC_ASVIS(x) +#define USBHS_OTGSC_BSVIS_MASK USB_OTGSC_BSVIS_MASK +#define USBHS_OTGSC_BSVIS_SHIFT USB_OTGSC_BSVIS_SHIFT +#define USBHS_OTGSC_BSVIS(x) USB_OTGSC_BSVIS(x) +#define USBHS_OTGSC_BSEIS_MASK USB_OTGSC_BSEIS_MASK +#define USBHS_OTGSC_BSEIS_SHIFT USB_OTGSC_BSEIS_SHIFT +#define USBHS_OTGSC_BSEIS(x) USB_OTGSC_BSEIS(x) +#define USBHS_OTGSC_MSS_MASK USB_OTGSC_STATUS_1MS_MASK +#define USBHS_OTGSC_MSS_SHIFT USB_OTGSC_STATUS_1MS_SHIFT +#define USBHS_OTGSC_MSS(x) USB_OTGSC_STATUS_1MS(x) +#define USBHS_OTGSC_DPIS_MASK USB_OTGSC_DPIS_MASK +#define USBHS_OTGSC_DPIS_SHIFT USB_OTGSC_DPIS_SHIFT +#define USBHS_OTGSC_DPIS(x) USB_OTGSC_DPIS(x) +#define USBHS_OTGSC_IDIE_MASK USB_OTGSC_IDIE_MASK +#define USBHS_OTGSC_IDIE_SHIFT USB_OTGSC_IDIE_SHIFT +#define USBHS_OTGSC_IDIE(x) USB_OTGSC_IDIE(x) +#define USBHS_OTGSC_AVVIE_MASK USB_OTGSC_AVVIE_MASK +#define USBHS_OTGSC_AVVIE_SHIFT USB_OTGSC_AVVIE_SHIFT +#define USBHS_OTGSC_AVVIE(x) USB_OTGSC_AVVIE(x) +#define USBHS_OTGSC_ASVIE_MASK USB_OTGSC_ASVIE_MASK +#define USBHS_OTGSC_ASVIE_SHIFT USB_OTGSC_ASVIE_SHIFT +#define USBHS_OTGSC_ASVIE(x) USB_OTGSC_ASVIE(x) +#define USBHS_OTGSC_BSVIE_MASK USB_OTGSC_BSVIE_MASK +#define USBHS_OTGSC_BSVIE_SHIFT USB_OTGSC_BSVIE_SHIFT +#define USBHS_OTGSC_BSVIE(x) USB_OTGSC_BSVIE(x) +#define USBHS_OTGSC_BSEIE_MASK USB_OTGSC_BSEIE_MASK +#define USBHS_OTGSC_BSEIE_SHIFT USB_OTGSC_BSEIE_SHIFT +#define USBHS_OTGSC_BSEIE(x) USB_OTGSC_BSEIE(x) +#define USBHS_OTGSC_MSE_MASK USB_OTGSC_EN_1MS_MASK +#define USBHS_OTGSC_MSE_SHIFT USB_OTGSC_EN_1MS_SHIFT +#define USBHS_OTGSC_MSE(x) USB_OTGSC_EN_1MS(x) +#define USBHS_OTGSC_DPIE_MASK USB_OTGSC_DPIE_MASK +#define USBHS_OTGSC_DPIE_SHIFT USB_OTGSC_DPIE_SHIFT +#define USBHS_OTGSC_DPIE(x) USB_OTGSC_DPIE(x) +#define USBHS_USBMODE_CM_MASK USB_USBMODE_CM_MASK +#define USBHS_USBMODE_CM_SHIFT USB_USBMODE_CM_SHIFT +#define USBHS_USBMODE_CM(x) USB_USBMODE_CM(x) +#define USBHS_USBMODE_ES_MASK USB_USBMODE_ES_MASK +#define USBHS_USBMODE_ES_SHIFT USB_USBMODE_ES_SHIFT +#define USBHS_USBMODE_ES(x) USB_USBMODE_ES(x) +#define USBHS_USBMODE_SLOM_MASK USB_USBMODE_SLOM_MASK +#define USBHS_USBMODE_SLOM_SHIFT USB_USBMODE_SLOM_SHIFT +#define USBHS_USBMODE_SLOM(x) USB_USBMODE_SLOM(x) +#define USBHS_USBMODE_SDIS_MASK USB_USBMODE_SDIS_MASK +#define USBHS_USBMODE_SDIS_SHIFT USB_USBMODE_SDIS_SHIFT +#define USBHS_USBMODE_SDIS(x) USB_USBMODE_SDIS(x) +#define USBHS_EPSETUPSR_EPSETUPSTAT_MASK USB_ENDPTSETUPSTAT_ENDPTSETUPSTAT_MASK +#define USBHS_EPSETUPSR_EPSETUPSTAT_SHIFT USB_ENDPTSETUPSTAT_ENDPTSETUPSTAT_SHIFT +#define USBHS_EPSETUPSR_EPSETUPSTAT(x) USB_ENDPTSETUPSTAT_ENDPTSETUPSTAT(x) +#define USBHS_EPPRIME_PERB_MASK USB_ENDPTPRIME_PERB_MASK +#define USBHS_EPPRIME_PERB_SHIFT USB_ENDPTPRIME_PERB_SHIFT +#define USBHS_EPPRIME_PERB(x) USB_ENDPTPRIME_PERB(x) +#define USBHS_EPPRIME_PETB_MASK USB_ENDPTPRIME_PETB_MASK +#define USBHS_EPPRIME_PETB_SHIFT USB_ENDPTPRIME_PETB_SHIFT +#define USBHS_EPPRIME_PETB(x) USB_ENDPTPRIME_PETB(x) +#define USBHS_EPFLUSH_FERB_MASK USB_ENDPTFLUSH_FERB_MASK +#define USBHS_EPFLUSH_FERB_SHIFT USB_ENDPTFLUSH_FERB_SHIFT +#define USBHS_EPFLUSH_FERB(x) USB_ENDPTFLUSH_FERB(x) +#define USBHS_EPFLUSH_FETB_MASK USB_ENDPTFLUSH_FETB_MASK +#define USBHS_EPFLUSH_FETB_SHIFT USB_ENDPTFLUSH_FETB_SHIFT +#define USBHS_EPFLUSH_FETB(x) USB_ENDPTFLUSH_FETB(x) +#define USBHS_EPSR_ERBR_MASK USB_ENDPTSTAT_ERBR_MASK +#define USBHS_EPSR_ERBR_SHIFT USB_ENDPTSTAT_ERBR_SHIFT +#define USBHS_EPSR_ERBR(x) USB_ENDPTSTAT_ERBR(x) +#define USBHS_EPSR_ETBR_MASK USB_ENDPTSTAT_ETBR_MASK +#define USBHS_EPSR_ETBR_SHIFT USB_ENDPTSTAT_ETBR_SHIFT +#define USBHS_EPSR_ETBR(x) USB_ENDPTSTAT_ETBR(x) +#define USBHS_EPCOMPLETE_ERCE_MASK USB_ENDPTCOMPLETE_ERCE_MASK +#define USBHS_EPCOMPLETE_ERCE_SHIFT USB_ENDPTCOMPLETE_ERCE_SHIFT +#define USBHS_EPCOMPLETE_ERCE(x) USB_ENDPTCOMPLETE_ERCE(x) +#define USBHS_EPCOMPLETE_ETCE_MASK USB_ENDPTCOMPLETE_ETCE_MASK +#define USBHS_EPCOMPLETE_ETCE_SHIFT USB_ENDPTCOMPLETE_ETCE_SHIFT +#define USBHS_EPCOMPLETE_ETCE(x) USB_ENDPTCOMPLETE_ETCE(x) +#define USBHS_EPCR0_RXS_MASK USB_ENDPTCTRL0_RXS_MASK +#define USBHS_EPCR0_RXS_SHIFT USB_ENDPTCTRL0_RXS_SHIFT +#define USBHS_EPCR0_RXS(x) USB_ENDPTCTRL0_RXS(x) +#define USBHS_EPCR0_RXT_MASK USB_ENDPTCTRL0_RXT_MASK +#define USBHS_EPCR0_RXT_SHIFT USB_ENDPTCTRL0_RXT_SHIFT +#define USBHS_EPCR0_RXT(x) USB_ENDPTCTRL0_RXT(x) +#define USBHS_EPCR0_RXE_MASK USB_ENDPTCTRL0_RXE_MASK +#define USBHS_EPCR0_RXE_SHIFT USB_ENDPTCTRL0_RXE_SHIFT +#define USBHS_EPCR0_RXE(x) USB_ENDPTCTRL0_RXE(x) +#define USBHS_EPCR0_TXS_MASK USB_ENDPTCTRL0_TXS_MASK +#define USBHS_EPCR0_TXS_SHIFT USB_ENDPTCTRL0_TXS_SHIFT +#define USBHS_EPCR0_TXS(x) USB_ENDPTCTRL0_TXS(x) +#define USBHS_EPCR0_TXT_MASK USB_ENDPTCTRL0_TXT_MASK +#define USBHS_EPCR0_TXT_SHIFT USB_ENDPTCTRL0_TXT_SHIFT +#define USBHS_EPCR0_TXT(x) USB_ENDPTCTRL0_TXT(x) +#define USBHS_EPCR0_TXE_MASK USB_ENDPTCTRL0_TXE_MASK +#define USBHS_EPCR0_TXE_SHIFT USB_ENDPTCTRL0_TXE_SHIFT +#define USBHS_EPCR0_TXE(x) USB_ENDPTCTRL0_TXE(x) +#define USBHS_EPCR_RXS_MASK USB_ENDPTCTRL_RXS_MASK +#define USBHS_EPCR_RXS_SHIFT USB_ENDPTCTRL_RXS_SHIFT +#define USBHS_EPCR_RXS(x) USB_ENDPTCTRL_RXS(x) +#define USBHS_EPCR_RXD_MASK USB_ENDPTCTRL_RXD_MASK +#define USBHS_EPCR_RXD_SHIFT USB_ENDPTCTRL_RXD_SHIFT +#define USBHS_EPCR_RXD(x) USB_ENDPTCTRL_RXD(x) +#define USBHS_EPCR_RXT_MASK USB_ENDPTCTRL_RXT_MASK +#define USBHS_EPCR_RXT_SHIFT USB_ENDPTCTRL_RXT_SHIFT +#define USBHS_EPCR_RXT(x) USB_ENDPTCTRL_RXT(x) +#define USBHS_EPCR_RXI_MASK USB_ENDPTCTRL_RXI_MASK +#define USBHS_EPCR_RXI_SHIFT USB_ENDPTCTRL_RXI_SHIFT +#define USBHS_EPCR_RXI(x) USB_ENDPTCTRL_RXI(x) +#define USBHS_EPCR_RXR_MASK USB_ENDPTCTRL_RXR_MASK +#define USBHS_EPCR_RXR_SHIFT USB_ENDPTCTRL_RXR_SHIFT +#define USBHS_EPCR_RXR(x) USB_ENDPTCTRL_RXR(x) +#define USBHS_EPCR_RXE_MASK USB_ENDPTCTRL_RXE_MASK +#define USBHS_EPCR_RXE_SHIFT USB_ENDPTCTRL_RXE_SHIFT +#define USBHS_EPCR_RXE(x) USB_ENDPTCTRL_RXE(x) +#define USBHS_EPCR_TXS_MASK USB_ENDPTCTRL_TXS_MASK +#define USBHS_EPCR_TXS_SHIFT USB_ENDPTCTRL_TXS_SHIFT +#define USBHS_EPCR_TXS(x) USB_ENDPTCTRL_TXS(x) +#define USBHS_EPCR_TXD_MASK USB_ENDPTCTRL_TXD_MASK +#define USBHS_EPCR_TXD_SHIFT USB_ENDPTCTRL_TXD_SHIFT +#define USBHS_EPCR_TXD(x) USB_ENDPTCTRL_TXD(x) +#define USBHS_EPCR_TXT_MASK USB_ENDPTCTRL_TXT_MASK +#define USBHS_EPCR_TXT_SHIFT USB_ENDPTCTRL_TXT_SHIFT +#define USBHS_EPCR_TXT(x) USB_ENDPTCTRL_TXT(x) +#define USBHS_EPCR_TXI_MASK USB_ENDPTCTRL_TXI_MASK +#define USBHS_EPCR_TXI_SHIFT USB_ENDPTCTRL_TXI_SHIFT +#define USBHS_EPCR_TXI(x) USB_ENDPTCTRL_TXI(x) +#define USBHS_EPCR_TXR_MASK USB_ENDPTCTRL_TXR_MASK +#define USBHS_EPCR_TXR_SHIFT USB_ENDPTCTRL_TXR_SHIFT +#define USBHS_EPCR_TXR(x) USB_ENDPTCTRL_TXR(x) +#define USBHS_EPCR_TXE_MASK USB_ENDPTCTRL_TXE_MASK +#define USBHS_EPCR_TXE_SHIFT USB_ENDPTCTRL_TXE_SHIFT +#define USBHS_EPCR_TXE(x) USB_ENDPTCTRL_TXE(x) +#define USBHS_EPCR_COUNT USB_ENDPTCTRL_COUNT +#define USBHS_Type USB_Type +#define USBHS_BASE_ADDRS { USB1_BASE, USB2_BASE } +#define USBHS_IRQS { USB_OTG1_IRQn, USB_OTG2_IRQn } +#define USBHS_IRQHandler USB_OTG1_IRQHandler + + +/*! + * @} + */ /* end of group USB_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- USBNC Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup USBNC_Peripheral_Access_Layer USBNC Peripheral Access Layer + * @{ + */ + +/** USBNC - Register Layout Typedef */ +typedef struct { + uint8_t RESERVED_0[2048]; + __IO uint32_t USB_OTGn_CTRL; /**< USB OTG1 Control Register..USB OTG2 Control Register, offset: 0x800 */ + uint8_t RESERVED_1[20]; + __IO uint32_t USB_OTGn_PHY_CTRL_0; /**< OTG1 UTMI PHY Control 0 Register..OTG2 UTMI PHY Control 0 Register, offset: 0x818 */ +} USBNC_Type; + +/* ---------------------------------------------------------------------------- + -- USBNC Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup USBNC_Register_Masks USBNC Register Masks + * @{ + */ + +/*! @name USB_OTGn_CTRL - USB OTG1 Control Register..USB OTG2 Control Register */ +/*! @{ */ +#define USBNC_USB_OTGn_CTRL_OVER_CUR_DIS_MASK (0x80U) +#define USBNC_USB_OTGn_CTRL_OVER_CUR_DIS_SHIFT (7U) +/*! OVER_CUR_DIS + * 0b1..Disables overcurrent detection + * 0b0..Enables overcurrent detection + */ +#define USBNC_USB_OTGn_CTRL_OVER_CUR_DIS(x) (((uint32_t)(((uint32_t)(x)) << USBNC_USB_OTGn_CTRL_OVER_CUR_DIS_SHIFT)) & USBNC_USB_OTGn_CTRL_OVER_CUR_DIS_MASK) +#define USBNC_USB_OTGn_CTRL_OVER_CUR_POL_MASK (0x100U) +#define USBNC_USB_OTGn_CTRL_OVER_CUR_POL_SHIFT (8U) +/*! OVER_CUR_POL + * 0b1..Low active (low on this signal represents an overcurrent condition) + * 0b0..High active (high on this signal represents an overcurrent condition) + */ +#define USBNC_USB_OTGn_CTRL_OVER_CUR_POL(x) (((uint32_t)(((uint32_t)(x)) << USBNC_USB_OTGn_CTRL_OVER_CUR_POL_SHIFT)) & USBNC_USB_OTGn_CTRL_OVER_CUR_POL_MASK) +#define USBNC_USB_OTGn_CTRL_PWR_POL_MASK (0x200U) +#define USBNC_USB_OTGn_CTRL_PWR_POL_SHIFT (9U) +/*! PWR_POL + * 0b1..PMIC Power Pin is High active. + * 0b0..PMIC Power Pin is Low active. + */ +#define USBNC_USB_OTGn_CTRL_PWR_POL(x) (((uint32_t)(((uint32_t)(x)) << USBNC_USB_OTGn_CTRL_PWR_POL_SHIFT)) & USBNC_USB_OTGn_CTRL_PWR_POL_MASK) +#define USBNC_USB_OTGn_CTRL_WIE_MASK (0x400U) +#define USBNC_USB_OTGn_CTRL_WIE_SHIFT (10U) +/*! WIE + * 0b1..Interrupt Enabled + * 0b0..Interrupt Disabled + */ +#define USBNC_USB_OTGn_CTRL_WIE(x) (((uint32_t)(((uint32_t)(x)) << USBNC_USB_OTGn_CTRL_WIE_SHIFT)) & USBNC_USB_OTGn_CTRL_WIE_MASK) +#define USBNC_USB_OTGn_CTRL_WKUP_SW_EN_MASK (0x4000U) +#define USBNC_USB_OTGn_CTRL_WKUP_SW_EN_SHIFT (14U) +/*! WKUP_SW_EN + * 0b1..Enable + * 0b0..Disable + */ +#define USBNC_USB_OTGn_CTRL_WKUP_SW_EN(x) (((uint32_t)(((uint32_t)(x)) << USBNC_USB_OTGn_CTRL_WKUP_SW_EN_SHIFT)) & USBNC_USB_OTGn_CTRL_WKUP_SW_EN_MASK) +#define USBNC_USB_OTGn_CTRL_WKUP_SW_MASK (0x8000U) +#define USBNC_USB_OTGn_CTRL_WKUP_SW_SHIFT (15U) +/*! WKUP_SW + * 0b1..Force wake-up + * 0b0..Inactive + */ +#define USBNC_USB_OTGn_CTRL_WKUP_SW(x) (((uint32_t)(((uint32_t)(x)) << USBNC_USB_OTGn_CTRL_WKUP_SW_SHIFT)) & USBNC_USB_OTGn_CTRL_WKUP_SW_MASK) +#define USBNC_USB_OTGn_CTRL_WKUP_ID_EN_MASK (0x10000U) +#define USBNC_USB_OTGn_CTRL_WKUP_ID_EN_SHIFT (16U) +/*! WKUP_ID_EN + * 0b1..Enable + * 0b0..Disable + */ +#define USBNC_USB_OTGn_CTRL_WKUP_ID_EN(x) (((uint32_t)(((uint32_t)(x)) << USBNC_USB_OTGn_CTRL_WKUP_ID_EN_SHIFT)) & USBNC_USB_OTGn_CTRL_WKUP_ID_EN_MASK) +#define USBNC_USB_OTGn_CTRL_WKUP_VBUS_EN_MASK (0x20000U) +#define USBNC_USB_OTGn_CTRL_WKUP_VBUS_EN_SHIFT (17U) +/*! WKUP_VBUS_EN + * 0b1..Enable + * 0b0..Disable + */ +#define USBNC_USB_OTGn_CTRL_WKUP_VBUS_EN(x) (((uint32_t)(((uint32_t)(x)) << USBNC_USB_OTGn_CTRL_WKUP_VBUS_EN_SHIFT)) & USBNC_USB_OTGn_CTRL_WKUP_VBUS_EN_MASK) +#define USBNC_USB_OTGn_CTRL_WKUP_DPDM_EN_MASK (0x20000000U) +#define USBNC_USB_OTGn_CTRL_WKUP_DPDM_EN_SHIFT (29U) +/*! WKUP_DPDM_EN + * 0b1..(Default) DPDM changes wake-up to be enabled, it is for device only. + * 0b0..DPDM changes wake-up to be disabled only when VBUS is 0. + */ +#define USBNC_USB_OTGn_CTRL_WKUP_DPDM_EN(x) (((uint32_t)(((uint32_t)(x)) << USBNC_USB_OTGn_CTRL_WKUP_DPDM_EN_SHIFT)) & USBNC_USB_OTGn_CTRL_WKUP_DPDM_EN_MASK) +#define USBNC_USB_OTGn_CTRL_WIR_MASK (0x80000000U) +#define USBNC_USB_OTGn_CTRL_WIR_SHIFT (31U) +/*! WIR + * 0b1..Wake-up Interrupt Request received + * 0b0..No wake-up interrupt request received + */ +#define USBNC_USB_OTGn_CTRL_WIR(x) (((uint32_t)(((uint32_t)(x)) << USBNC_USB_OTGn_CTRL_WIR_SHIFT)) & USBNC_USB_OTGn_CTRL_WIR_MASK) +/*! @} */ + +/*! @name USB_OTGn_PHY_CTRL_0 - OTG1 UTMI PHY Control 0 Register..OTG2 UTMI PHY Control 0 Register */ +/*! @{ */ +#define USBNC_USB_OTGn_PHY_CTRL_0_UTMI_CLK_VLD_MASK (0x80000000U) +#define USBNC_USB_OTGn_PHY_CTRL_0_UTMI_CLK_VLD_SHIFT (31U) +/*! UTMI_CLK_VLD + * 0b1..Valid + * 0b0..Invalid + */ +#define USBNC_USB_OTGn_PHY_CTRL_0_UTMI_CLK_VLD(x) (((uint32_t)(((uint32_t)(x)) << USBNC_USB_OTGn_PHY_CTRL_0_UTMI_CLK_VLD_SHIFT)) & USBNC_USB_OTGn_PHY_CTRL_0_UTMI_CLK_VLD_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group USBNC_Register_Masks */ + + +/* USBNC - Peripheral instance base addresses */ +/** Peripheral USBNC1 base address */ +#define USBNC1_BASE (0x402E0000u) +/** Peripheral USBNC1 base pointer */ +#define USBNC1 ((USBNC_Type *)USBNC1_BASE) +/** Peripheral USBNC2 base address */ +#define USBNC2_BASE (0x402E0004u) +/** Peripheral USBNC2 base pointer */ +#define USBNC2 ((USBNC_Type *)USBNC2_BASE) +/** Array initializer of USBNC peripheral base addresses */ +#define USBNC_BASE_ADDRS { 0u, USBNC1_BASE, USBNC2_BASE } +/** Array initializer of USBNC peripheral base pointers */ +#define USBNC_BASE_PTRS { (USBNC_Type *)0u, USBNC1, USBNC2 } + +/*! + * @} + */ /* end of group USBNC_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- USBPHY Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup USBPHY_Peripheral_Access_Layer USBPHY Peripheral Access Layer + * @{ + */ + +/** USBPHY - Register Layout Typedef */ +typedef struct { + __IO uint32_t PWD; /**< USB PHY Power-Down Register, offset: 0x0 */ + __IO uint32_t PWD_SET; /**< USB PHY Power-Down Register, offset: 0x4 */ + __IO uint32_t PWD_CLR; /**< USB PHY Power-Down Register, offset: 0x8 */ + __IO uint32_t PWD_TOG; /**< USB PHY Power-Down Register, offset: 0xC */ + __IO uint32_t TX; /**< USB PHY Transmitter Control Register, offset: 0x10 */ + __IO uint32_t TX_SET; /**< USB PHY Transmitter Control Register, offset: 0x14 */ + __IO uint32_t TX_CLR; /**< USB PHY Transmitter Control Register, offset: 0x18 */ + __IO uint32_t TX_TOG; /**< USB PHY Transmitter Control Register, offset: 0x1C */ + __IO uint32_t RX; /**< USB PHY Receiver Control Register, offset: 0x20 */ + __IO uint32_t RX_SET; /**< USB PHY Receiver Control Register, offset: 0x24 */ + __IO uint32_t RX_CLR; /**< USB PHY Receiver Control Register, offset: 0x28 */ + __IO uint32_t RX_TOG; /**< USB PHY Receiver Control Register, offset: 0x2C */ + __IO uint32_t CTRL; /**< USB PHY General Control Register, offset: 0x30 */ + __IO uint32_t CTRL_SET; /**< USB PHY General Control Register, offset: 0x34 */ + __IO uint32_t CTRL_CLR; /**< USB PHY General Control Register, offset: 0x38 */ + __IO uint32_t CTRL_TOG; /**< USB PHY General Control Register, offset: 0x3C */ + __IO uint32_t STATUS; /**< USB PHY Status Register, offset: 0x40 */ + uint8_t RESERVED_0[12]; + __IO uint32_t DEBUGr; /**< USB PHY Debug Register, offset: 0x50 */ + __IO uint32_t DEBUG_SET; /**< USB PHY Debug Register, offset: 0x54 */ + __IO uint32_t DEBUG_CLR; /**< USB PHY Debug Register, offset: 0x58 */ + __IO uint32_t DEBUG_TOG; /**< USB PHY Debug Register, offset: 0x5C */ + __I uint32_t DEBUG0_STATUS; /**< UTMI Debug Status Register 0, offset: 0x60 */ + uint8_t RESERVED_1[12]; + __IO uint32_t DEBUG1; /**< UTMI Debug Status Register 1, offset: 0x70 */ + __IO uint32_t DEBUG1_SET; /**< UTMI Debug Status Register 1, offset: 0x74 */ + __IO uint32_t DEBUG1_CLR; /**< UTMI Debug Status Register 1, offset: 0x78 */ + __IO uint32_t DEBUG1_TOG; /**< UTMI Debug Status Register 1, offset: 0x7C */ + __I uint32_t VERSION; /**< UTMI RTL Version, offset: 0x80 */ +} USBPHY_Type; + +/* ---------------------------------------------------------------------------- + -- USBPHY Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup USBPHY_Register_Masks USBPHY Register Masks + * @{ + */ + +/*! @name PWD - USB PHY Power-Down Register */ +/*! @{ */ +#define USBPHY_PWD_RSVD0_MASK (0x3FFU) +#define USBPHY_PWD_RSVD0_SHIFT (0U) +#define USBPHY_PWD_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_RSVD0_SHIFT)) & USBPHY_PWD_RSVD0_MASK) +#define USBPHY_PWD_TXPWDFS_MASK (0x400U) +#define USBPHY_PWD_TXPWDFS_SHIFT (10U) +#define USBPHY_PWD_TXPWDFS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TXPWDFS_SHIFT)) & USBPHY_PWD_TXPWDFS_MASK) +#define USBPHY_PWD_TXPWDIBIAS_MASK (0x800U) +#define USBPHY_PWD_TXPWDIBIAS_SHIFT (11U) +#define USBPHY_PWD_TXPWDIBIAS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TXPWDIBIAS_SHIFT)) & USBPHY_PWD_TXPWDIBIAS_MASK) +#define USBPHY_PWD_TXPWDV2I_MASK (0x1000U) +#define USBPHY_PWD_TXPWDV2I_SHIFT (12U) +#define USBPHY_PWD_TXPWDV2I(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TXPWDV2I_SHIFT)) & USBPHY_PWD_TXPWDV2I_MASK) +#define USBPHY_PWD_RSVD1_MASK (0x1E000U) +#define USBPHY_PWD_RSVD1_SHIFT (13U) +#define USBPHY_PWD_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_RSVD1_SHIFT)) & USBPHY_PWD_RSVD1_MASK) +#define USBPHY_PWD_RXPWDENV_MASK (0x20000U) +#define USBPHY_PWD_RXPWDENV_SHIFT (17U) +#define USBPHY_PWD_RXPWDENV(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_RXPWDENV_SHIFT)) & USBPHY_PWD_RXPWDENV_MASK) +#define USBPHY_PWD_RXPWD1PT1_MASK (0x40000U) +#define USBPHY_PWD_RXPWD1PT1_SHIFT (18U) +#define USBPHY_PWD_RXPWD1PT1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_RXPWD1PT1_SHIFT)) & USBPHY_PWD_RXPWD1PT1_MASK) +#define USBPHY_PWD_RXPWDDIFF_MASK (0x80000U) +#define USBPHY_PWD_RXPWDDIFF_SHIFT (19U) +#define USBPHY_PWD_RXPWDDIFF(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_RXPWDDIFF_SHIFT)) & USBPHY_PWD_RXPWDDIFF_MASK) +#define USBPHY_PWD_RXPWDRX_MASK (0x100000U) +#define USBPHY_PWD_RXPWDRX_SHIFT (20U) +#define USBPHY_PWD_RXPWDRX(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_RXPWDRX_SHIFT)) & USBPHY_PWD_RXPWDRX_MASK) +#define USBPHY_PWD_RSVD2_MASK (0xFFE00000U) +#define USBPHY_PWD_RSVD2_SHIFT (21U) +#define USBPHY_PWD_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_RSVD2_SHIFT)) & USBPHY_PWD_RSVD2_MASK) +/*! @} */ + +/*! @name PWD_SET - USB PHY Power-Down Register */ +/*! @{ */ +#define USBPHY_PWD_SET_RSVD0_MASK (0x3FFU) +#define USBPHY_PWD_SET_RSVD0_SHIFT (0U) +#define USBPHY_PWD_SET_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_RSVD0_SHIFT)) & USBPHY_PWD_SET_RSVD0_MASK) +#define USBPHY_PWD_SET_TXPWDFS_MASK (0x400U) +#define USBPHY_PWD_SET_TXPWDFS_SHIFT (10U) +#define USBPHY_PWD_SET_TXPWDFS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_TXPWDFS_SHIFT)) & USBPHY_PWD_SET_TXPWDFS_MASK) +#define USBPHY_PWD_SET_TXPWDIBIAS_MASK (0x800U) +#define USBPHY_PWD_SET_TXPWDIBIAS_SHIFT (11U) +#define USBPHY_PWD_SET_TXPWDIBIAS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_TXPWDIBIAS_SHIFT)) & USBPHY_PWD_SET_TXPWDIBIAS_MASK) +#define USBPHY_PWD_SET_TXPWDV2I_MASK (0x1000U) +#define USBPHY_PWD_SET_TXPWDV2I_SHIFT (12U) +#define USBPHY_PWD_SET_TXPWDV2I(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_TXPWDV2I_SHIFT)) & USBPHY_PWD_SET_TXPWDV2I_MASK) +#define USBPHY_PWD_SET_RSVD1_MASK (0x1E000U) +#define USBPHY_PWD_SET_RSVD1_SHIFT (13U) +#define USBPHY_PWD_SET_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_RSVD1_SHIFT)) & USBPHY_PWD_SET_RSVD1_MASK) +#define USBPHY_PWD_SET_RXPWDENV_MASK (0x20000U) +#define USBPHY_PWD_SET_RXPWDENV_SHIFT (17U) +#define USBPHY_PWD_SET_RXPWDENV(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_RXPWDENV_SHIFT)) & USBPHY_PWD_SET_RXPWDENV_MASK) +#define USBPHY_PWD_SET_RXPWD1PT1_MASK (0x40000U) +#define USBPHY_PWD_SET_RXPWD1PT1_SHIFT (18U) +#define USBPHY_PWD_SET_RXPWD1PT1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_RXPWD1PT1_SHIFT)) & USBPHY_PWD_SET_RXPWD1PT1_MASK) +#define USBPHY_PWD_SET_RXPWDDIFF_MASK (0x80000U) +#define USBPHY_PWD_SET_RXPWDDIFF_SHIFT (19U) +#define USBPHY_PWD_SET_RXPWDDIFF(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_RXPWDDIFF_SHIFT)) & USBPHY_PWD_SET_RXPWDDIFF_MASK) +#define USBPHY_PWD_SET_RXPWDRX_MASK (0x100000U) +#define USBPHY_PWD_SET_RXPWDRX_SHIFT (20U) +#define USBPHY_PWD_SET_RXPWDRX(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_RXPWDRX_SHIFT)) & USBPHY_PWD_SET_RXPWDRX_MASK) +#define USBPHY_PWD_SET_RSVD2_MASK (0xFFE00000U) +#define USBPHY_PWD_SET_RSVD2_SHIFT (21U) +#define USBPHY_PWD_SET_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_RSVD2_SHIFT)) & USBPHY_PWD_SET_RSVD2_MASK) +/*! @} */ + +/*! @name PWD_CLR - USB PHY Power-Down Register */ +/*! @{ */ +#define USBPHY_PWD_CLR_RSVD0_MASK (0x3FFU) +#define USBPHY_PWD_CLR_RSVD0_SHIFT (0U) +#define USBPHY_PWD_CLR_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_RSVD0_SHIFT)) & USBPHY_PWD_CLR_RSVD0_MASK) +#define USBPHY_PWD_CLR_TXPWDFS_MASK (0x400U) +#define USBPHY_PWD_CLR_TXPWDFS_SHIFT (10U) +#define USBPHY_PWD_CLR_TXPWDFS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_TXPWDFS_SHIFT)) & USBPHY_PWD_CLR_TXPWDFS_MASK) +#define USBPHY_PWD_CLR_TXPWDIBIAS_MASK (0x800U) +#define USBPHY_PWD_CLR_TXPWDIBIAS_SHIFT (11U) +#define USBPHY_PWD_CLR_TXPWDIBIAS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_TXPWDIBIAS_SHIFT)) & USBPHY_PWD_CLR_TXPWDIBIAS_MASK) +#define USBPHY_PWD_CLR_TXPWDV2I_MASK (0x1000U) +#define USBPHY_PWD_CLR_TXPWDV2I_SHIFT (12U) +#define USBPHY_PWD_CLR_TXPWDV2I(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_TXPWDV2I_SHIFT)) & USBPHY_PWD_CLR_TXPWDV2I_MASK) +#define USBPHY_PWD_CLR_RSVD1_MASK (0x1E000U) +#define USBPHY_PWD_CLR_RSVD1_SHIFT (13U) +#define USBPHY_PWD_CLR_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_RSVD1_SHIFT)) & USBPHY_PWD_CLR_RSVD1_MASK) +#define USBPHY_PWD_CLR_RXPWDENV_MASK (0x20000U) +#define USBPHY_PWD_CLR_RXPWDENV_SHIFT (17U) +#define USBPHY_PWD_CLR_RXPWDENV(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_RXPWDENV_SHIFT)) & USBPHY_PWD_CLR_RXPWDENV_MASK) +#define USBPHY_PWD_CLR_RXPWD1PT1_MASK (0x40000U) +#define USBPHY_PWD_CLR_RXPWD1PT1_SHIFT (18U) +#define USBPHY_PWD_CLR_RXPWD1PT1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_RXPWD1PT1_SHIFT)) & USBPHY_PWD_CLR_RXPWD1PT1_MASK) +#define USBPHY_PWD_CLR_RXPWDDIFF_MASK (0x80000U) +#define USBPHY_PWD_CLR_RXPWDDIFF_SHIFT (19U) +#define USBPHY_PWD_CLR_RXPWDDIFF(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_RXPWDDIFF_SHIFT)) & USBPHY_PWD_CLR_RXPWDDIFF_MASK) +#define USBPHY_PWD_CLR_RXPWDRX_MASK (0x100000U) +#define USBPHY_PWD_CLR_RXPWDRX_SHIFT (20U) +#define USBPHY_PWD_CLR_RXPWDRX(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_RXPWDRX_SHIFT)) & USBPHY_PWD_CLR_RXPWDRX_MASK) +#define USBPHY_PWD_CLR_RSVD2_MASK (0xFFE00000U) +#define USBPHY_PWD_CLR_RSVD2_SHIFT (21U) +#define USBPHY_PWD_CLR_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_RSVD2_SHIFT)) & USBPHY_PWD_CLR_RSVD2_MASK) +/*! @} */ + +/*! @name PWD_TOG - USB PHY Power-Down Register */ +/*! @{ */ +#define USBPHY_PWD_TOG_RSVD0_MASK (0x3FFU) +#define USBPHY_PWD_TOG_RSVD0_SHIFT (0U) +#define USBPHY_PWD_TOG_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_RSVD0_SHIFT)) & USBPHY_PWD_TOG_RSVD0_MASK) +#define USBPHY_PWD_TOG_TXPWDFS_MASK (0x400U) +#define USBPHY_PWD_TOG_TXPWDFS_SHIFT (10U) +#define USBPHY_PWD_TOG_TXPWDFS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_TXPWDFS_SHIFT)) & USBPHY_PWD_TOG_TXPWDFS_MASK) +#define USBPHY_PWD_TOG_TXPWDIBIAS_MASK (0x800U) +#define USBPHY_PWD_TOG_TXPWDIBIAS_SHIFT (11U) +#define USBPHY_PWD_TOG_TXPWDIBIAS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_TXPWDIBIAS_SHIFT)) & USBPHY_PWD_TOG_TXPWDIBIAS_MASK) +#define USBPHY_PWD_TOG_TXPWDV2I_MASK (0x1000U) +#define USBPHY_PWD_TOG_TXPWDV2I_SHIFT (12U) +#define USBPHY_PWD_TOG_TXPWDV2I(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_TXPWDV2I_SHIFT)) & USBPHY_PWD_TOG_TXPWDV2I_MASK) +#define USBPHY_PWD_TOG_RSVD1_MASK (0x1E000U) +#define USBPHY_PWD_TOG_RSVD1_SHIFT (13U) +#define USBPHY_PWD_TOG_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_RSVD1_SHIFT)) & USBPHY_PWD_TOG_RSVD1_MASK) +#define USBPHY_PWD_TOG_RXPWDENV_MASK (0x20000U) +#define USBPHY_PWD_TOG_RXPWDENV_SHIFT (17U) +#define USBPHY_PWD_TOG_RXPWDENV(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_RXPWDENV_SHIFT)) & USBPHY_PWD_TOG_RXPWDENV_MASK) +#define USBPHY_PWD_TOG_RXPWD1PT1_MASK (0x40000U) +#define USBPHY_PWD_TOG_RXPWD1PT1_SHIFT (18U) +#define USBPHY_PWD_TOG_RXPWD1PT1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_RXPWD1PT1_SHIFT)) & USBPHY_PWD_TOG_RXPWD1PT1_MASK) +#define USBPHY_PWD_TOG_RXPWDDIFF_MASK (0x80000U) +#define USBPHY_PWD_TOG_RXPWDDIFF_SHIFT (19U) +#define USBPHY_PWD_TOG_RXPWDDIFF(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_RXPWDDIFF_SHIFT)) & USBPHY_PWD_TOG_RXPWDDIFF_MASK) +#define USBPHY_PWD_TOG_RXPWDRX_MASK (0x100000U) +#define USBPHY_PWD_TOG_RXPWDRX_SHIFT (20U) +#define USBPHY_PWD_TOG_RXPWDRX(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_RXPWDRX_SHIFT)) & USBPHY_PWD_TOG_RXPWDRX_MASK) +#define USBPHY_PWD_TOG_RSVD2_MASK (0xFFE00000U) +#define USBPHY_PWD_TOG_RSVD2_SHIFT (21U) +#define USBPHY_PWD_TOG_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_RSVD2_SHIFT)) & USBPHY_PWD_TOG_RSVD2_MASK) +/*! @} */ + +/*! @name TX - USB PHY Transmitter Control Register */ +/*! @{ */ +#define USBPHY_TX_D_CAL_MASK (0xFU) +#define USBPHY_TX_D_CAL_SHIFT (0U) +#define USBPHY_TX_D_CAL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_D_CAL_SHIFT)) & USBPHY_TX_D_CAL_MASK) +#define USBPHY_TX_RSVD0_MASK (0xF0U) +#define USBPHY_TX_RSVD0_SHIFT (4U) +#define USBPHY_TX_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_RSVD0_SHIFT)) & USBPHY_TX_RSVD0_MASK) +#define USBPHY_TX_TXCAL45DN_MASK (0xF00U) +#define USBPHY_TX_TXCAL45DN_SHIFT (8U) +#define USBPHY_TX_TXCAL45DN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TXCAL45DN_SHIFT)) & USBPHY_TX_TXCAL45DN_MASK) +#define USBPHY_TX_RSVD1_MASK (0xF000U) +#define USBPHY_TX_RSVD1_SHIFT (12U) +#define USBPHY_TX_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_RSVD1_SHIFT)) & USBPHY_TX_RSVD1_MASK) +#define USBPHY_TX_TXCAL45DP_MASK (0xF0000U) +#define USBPHY_TX_TXCAL45DP_SHIFT (16U) +#define USBPHY_TX_TXCAL45DP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TXCAL45DP_SHIFT)) & USBPHY_TX_TXCAL45DP_MASK) +#define USBPHY_TX_RSVD2_MASK (0x3F00000U) +#define USBPHY_TX_RSVD2_SHIFT (20U) +#define USBPHY_TX_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_RSVD2_SHIFT)) & USBPHY_TX_RSVD2_MASK) +#define USBPHY_TX_USBPHY_TX_EDGECTRL_MASK (0x1C000000U) +#define USBPHY_TX_USBPHY_TX_EDGECTRL_SHIFT (26U) +#define USBPHY_TX_USBPHY_TX_EDGECTRL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_USBPHY_TX_EDGECTRL_SHIFT)) & USBPHY_TX_USBPHY_TX_EDGECTRL_MASK) +#define USBPHY_TX_RSVD5_MASK (0xE0000000U) +#define USBPHY_TX_RSVD5_SHIFT (29U) +#define USBPHY_TX_RSVD5(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_RSVD5_SHIFT)) & USBPHY_TX_RSVD5_MASK) +/*! @} */ + +/*! @name TX_SET - USB PHY Transmitter Control Register */ +/*! @{ */ +#define USBPHY_TX_SET_D_CAL_MASK (0xFU) +#define USBPHY_TX_SET_D_CAL_SHIFT (0U) +#define USBPHY_TX_SET_D_CAL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_SET_D_CAL_SHIFT)) & USBPHY_TX_SET_D_CAL_MASK) +#define USBPHY_TX_SET_RSVD0_MASK (0xF0U) +#define USBPHY_TX_SET_RSVD0_SHIFT (4U) +#define USBPHY_TX_SET_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_SET_RSVD0_SHIFT)) & USBPHY_TX_SET_RSVD0_MASK) +#define USBPHY_TX_SET_TXCAL45DN_MASK (0xF00U) +#define USBPHY_TX_SET_TXCAL45DN_SHIFT (8U) +#define USBPHY_TX_SET_TXCAL45DN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_SET_TXCAL45DN_SHIFT)) & USBPHY_TX_SET_TXCAL45DN_MASK) +#define USBPHY_TX_SET_RSVD1_MASK (0xF000U) +#define USBPHY_TX_SET_RSVD1_SHIFT (12U) +#define USBPHY_TX_SET_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_SET_RSVD1_SHIFT)) & USBPHY_TX_SET_RSVD1_MASK) +#define USBPHY_TX_SET_TXCAL45DP_MASK (0xF0000U) +#define USBPHY_TX_SET_TXCAL45DP_SHIFT (16U) +#define USBPHY_TX_SET_TXCAL45DP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_SET_TXCAL45DP_SHIFT)) & USBPHY_TX_SET_TXCAL45DP_MASK) +#define USBPHY_TX_SET_RSVD2_MASK (0x3F00000U) +#define USBPHY_TX_SET_RSVD2_SHIFT (20U) +#define USBPHY_TX_SET_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_SET_RSVD2_SHIFT)) & USBPHY_TX_SET_RSVD2_MASK) +#define USBPHY_TX_SET_USBPHY_TX_EDGECTRL_MASK (0x1C000000U) +#define USBPHY_TX_SET_USBPHY_TX_EDGECTRL_SHIFT (26U) +#define USBPHY_TX_SET_USBPHY_TX_EDGECTRL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_SET_USBPHY_TX_EDGECTRL_SHIFT)) & USBPHY_TX_SET_USBPHY_TX_EDGECTRL_MASK) +#define USBPHY_TX_SET_RSVD5_MASK (0xE0000000U) +#define USBPHY_TX_SET_RSVD5_SHIFT (29U) +#define USBPHY_TX_SET_RSVD5(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_SET_RSVD5_SHIFT)) & USBPHY_TX_SET_RSVD5_MASK) +/*! @} */ + +/*! @name TX_CLR - USB PHY Transmitter Control Register */ +/*! @{ */ +#define USBPHY_TX_CLR_D_CAL_MASK (0xFU) +#define USBPHY_TX_CLR_D_CAL_SHIFT (0U) +#define USBPHY_TX_CLR_D_CAL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_CLR_D_CAL_SHIFT)) & USBPHY_TX_CLR_D_CAL_MASK) +#define USBPHY_TX_CLR_RSVD0_MASK (0xF0U) +#define USBPHY_TX_CLR_RSVD0_SHIFT (4U) +#define USBPHY_TX_CLR_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_CLR_RSVD0_SHIFT)) & USBPHY_TX_CLR_RSVD0_MASK) +#define USBPHY_TX_CLR_TXCAL45DN_MASK (0xF00U) +#define USBPHY_TX_CLR_TXCAL45DN_SHIFT (8U) +#define USBPHY_TX_CLR_TXCAL45DN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_CLR_TXCAL45DN_SHIFT)) & USBPHY_TX_CLR_TXCAL45DN_MASK) +#define USBPHY_TX_CLR_RSVD1_MASK (0xF000U) +#define USBPHY_TX_CLR_RSVD1_SHIFT (12U) +#define USBPHY_TX_CLR_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_CLR_RSVD1_SHIFT)) & USBPHY_TX_CLR_RSVD1_MASK) +#define USBPHY_TX_CLR_TXCAL45DP_MASK (0xF0000U) +#define USBPHY_TX_CLR_TXCAL45DP_SHIFT (16U) +#define USBPHY_TX_CLR_TXCAL45DP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_CLR_TXCAL45DP_SHIFT)) & USBPHY_TX_CLR_TXCAL45DP_MASK) +#define USBPHY_TX_CLR_RSVD2_MASK (0x3F00000U) +#define USBPHY_TX_CLR_RSVD2_SHIFT (20U) +#define USBPHY_TX_CLR_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_CLR_RSVD2_SHIFT)) & USBPHY_TX_CLR_RSVD2_MASK) +#define USBPHY_TX_CLR_USBPHY_TX_EDGECTRL_MASK (0x1C000000U) +#define USBPHY_TX_CLR_USBPHY_TX_EDGECTRL_SHIFT (26U) +#define USBPHY_TX_CLR_USBPHY_TX_EDGECTRL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_CLR_USBPHY_TX_EDGECTRL_SHIFT)) & USBPHY_TX_CLR_USBPHY_TX_EDGECTRL_MASK) +#define USBPHY_TX_CLR_RSVD5_MASK (0xE0000000U) +#define USBPHY_TX_CLR_RSVD5_SHIFT (29U) +#define USBPHY_TX_CLR_RSVD5(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_CLR_RSVD5_SHIFT)) & USBPHY_TX_CLR_RSVD5_MASK) +/*! @} */ + +/*! @name TX_TOG - USB PHY Transmitter Control Register */ +/*! @{ */ +#define USBPHY_TX_TOG_D_CAL_MASK (0xFU) +#define USBPHY_TX_TOG_D_CAL_SHIFT (0U) +#define USBPHY_TX_TOG_D_CAL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TOG_D_CAL_SHIFT)) & USBPHY_TX_TOG_D_CAL_MASK) +#define USBPHY_TX_TOG_RSVD0_MASK (0xF0U) +#define USBPHY_TX_TOG_RSVD0_SHIFT (4U) +#define USBPHY_TX_TOG_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TOG_RSVD0_SHIFT)) & USBPHY_TX_TOG_RSVD0_MASK) +#define USBPHY_TX_TOG_TXCAL45DN_MASK (0xF00U) +#define USBPHY_TX_TOG_TXCAL45DN_SHIFT (8U) +#define USBPHY_TX_TOG_TXCAL45DN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TOG_TXCAL45DN_SHIFT)) & USBPHY_TX_TOG_TXCAL45DN_MASK) +#define USBPHY_TX_TOG_RSVD1_MASK (0xF000U) +#define USBPHY_TX_TOG_RSVD1_SHIFT (12U) +#define USBPHY_TX_TOG_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TOG_RSVD1_SHIFT)) & USBPHY_TX_TOG_RSVD1_MASK) +#define USBPHY_TX_TOG_TXCAL45DP_MASK (0xF0000U) +#define USBPHY_TX_TOG_TXCAL45DP_SHIFT (16U) +#define USBPHY_TX_TOG_TXCAL45DP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TOG_TXCAL45DP_SHIFT)) & USBPHY_TX_TOG_TXCAL45DP_MASK) +#define USBPHY_TX_TOG_RSVD2_MASK (0x3F00000U) +#define USBPHY_TX_TOG_RSVD2_SHIFT (20U) +#define USBPHY_TX_TOG_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TOG_RSVD2_SHIFT)) & USBPHY_TX_TOG_RSVD2_MASK) +#define USBPHY_TX_TOG_USBPHY_TX_EDGECTRL_MASK (0x1C000000U) +#define USBPHY_TX_TOG_USBPHY_TX_EDGECTRL_SHIFT (26U) +#define USBPHY_TX_TOG_USBPHY_TX_EDGECTRL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TOG_USBPHY_TX_EDGECTRL_SHIFT)) & USBPHY_TX_TOG_USBPHY_TX_EDGECTRL_MASK) +#define USBPHY_TX_TOG_RSVD5_MASK (0xE0000000U) +#define USBPHY_TX_TOG_RSVD5_SHIFT (29U) +#define USBPHY_TX_TOG_RSVD5(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TOG_RSVD5_SHIFT)) & USBPHY_TX_TOG_RSVD5_MASK) +/*! @} */ + +/*! @name RX - USB PHY Receiver Control Register */ +/*! @{ */ +#define USBPHY_RX_ENVADJ_MASK (0x7U) +#define USBPHY_RX_ENVADJ_SHIFT (0U) +#define USBPHY_RX_ENVADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_ENVADJ_SHIFT)) & USBPHY_RX_ENVADJ_MASK) +#define USBPHY_RX_RSVD0_MASK (0x8U) +#define USBPHY_RX_RSVD0_SHIFT (3U) +#define USBPHY_RX_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_RSVD0_SHIFT)) & USBPHY_RX_RSVD0_MASK) +#define USBPHY_RX_DISCONADJ_MASK (0x70U) +#define USBPHY_RX_DISCONADJ_SHIFT (4U) +#define USBPHY_RX_DISCONADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_DISCONADJ_SHIFT)) & USBPHY_RX_DISCONADJ_MASK) +#define USBPHY_RX_RSVD1_MASK (0x3FFF80U) +#define USBPHY_RX_RSVD1_SHIFT (7U) +#define USBPHY_RX_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_RSVD1_SHIFT)) & USBPHY_RX_RSVD1_MASK) +#define USBPHY_RX_RXDBYPASS_MASK (0x400000U) +#define USBPHY_RX_RXDBYPASS_SHIFT (22U) +#define USBPHY_RX_RXDBYPASS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_RXDBYPASS_SHIFT)) & USBPHY_RX_RXDBYPASS_MASK) +#define USBPHY_RX_RSVD2_MASK (0xFF800000U) +#define USBPHY_RX_RSVD2_SHIFT (23U) +#define USBPHY_RX_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_RSVD2_SHIFT)) & USBPHY_RX_RSVD2_MASK) +/*! @} */ + +/*! @name RX_SET - USB PHY Receiver Control Register */ +/*! @{ */ +#define USBPHY_RX_SET_ENVADJ_MASK (0x7U) +#define USBPHY_RX_SET_ENVADJ_SHIFT (0U) +#define USBPHY_RX_SET_ENVADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_SET_ENVADJ_SHIFT)) & USBPHY_RX_SET_ENVADJ_MASK) +#define USBPHY_RX_SET_RSVD0_MASK (0x8U) +#define USBPHY_RX_SET_RSVD0_SHIFT (3U) +#define USBPHY_RX_SET_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_SET_RSVD0_SHIFT)) & USBPHY_RX_SET_RSVD0_MASK) +#define USBPHY_RX_SET_DISCONADJ_MASK (0x70U) +#define USBPHY_RX_SET_DISCONADJ_SHIFT (4U) +#define USBPHY_RX_SET_DISCONADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_SET_DISCONADJ_SHIFT)) & USBPHY_RX_SET_DISCONADJ_MASK) +#define USBPHY_RX_SET_RSVD1_MASK (0x3FFF80U) +#define USBPHY_RX_SET_RSVD1_SHIFT (7U) +#define USBPHY_RX_SET_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_SET_RSVD1_SHIFT)) & USBPHY_RX_SET_RSVD1_MASK) +#define USBPHY_RX_SET_RXDBYPASS_MASK (0x400000U) +#define USBPHY_RX_SET_RXDBYPASS_SHIFT (22U) +#define USBPHY_RX_SET_RXDBYPASS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_SET_RXDBYPASS_SHIFT)) & USBPHY_RX_SET_RXDBYPASS_MASK) +#define USBPHY_RX_SET_RSVD2_MASK (0xFF800000U) +#define USBPHY_RX_SET_RSVD2_SHIFT (23U) +#define USBPHY_RX_SET_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_SET_RSVD2_SHIFT)) & USBPHY_RX_SET_RSVD2_MASK) +/*! @} */ + +/*! @name RX_CLR - USB PHY Receiver Control Register */ +/*! @{ */ +#define USBPHY_RX_CLR_ENVADJ_MASK (0x7U) +#define USBPHY_RX_CLR_ENVADJ_SHIFT (0U) +#define USBPHY_RX_CLR_ENVADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_CLR_ENVADJ_SHIFT)) & USBPHY_RX_CLR_ENVADJ_MASK) +#define USBPHY_RX_CLR_RSVD0_MASK (0x8U) +#define USBPHY_RX_CLR_RSVD0_SHIFT (3U) +#define USBPHY_RX_CLR_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_CLR_RSVD0_SHIFT)) & USBPHY_RX_CLR_RSVD0_MASK) +#define USBPHY_RX_CLR_DISCONADJ_MASK (0x70U) +#define USBPHY_RX_CLR_DISCONADJ_SHIFT (4U) +#define USBPHY_RX_CLR_DISCONADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_CLR_DISCONADJ_SHIFT)) & USBPHY_RX_CLR_DISCONADJ_MASK) +#define USBPHY_RX_CLR_RSVD1_MASK (0x3FFF80U) +#define USBPHY_RX_CLR_RSVD1_SHIFT (7U) +#define USBPHY_RX_CLR_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_CLR_RSVD1_SHIFT)) & USBPHY_RX_CLR_RSVD1_MASK) +#define USBPHY_RX_CLR_RXDBYPASS_MASK (0x400000U) +#define USBPHY_RX_CLR_RXDBYPASS_SHIFT (22U) +#define USBPHY_RX_CLR_RXDBYPASS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_CLR_RXDBYPASS_SHIFT)) & USBPHY_RX_CLR_RXDBYPASS_MASK) +#define USBPHY_RX_CLR_RSVD2_MASK (0xFF800000U) +#define USBPHY_RX_CLR_RSVD2_SHIFT (23U) +#define USBPHY_RX_CLR_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_CLR_RSVD2_SHIFT)) & USBPHY_RX_CLR_RSVD2_MASK) +/*! @} */ + +/*! @name RX_TOG - USB PHY Receiver Control Register */ +/*! @{ */ +#define USBPHY_RX_TOG_ENVADJ_MASK (0x7U) +#define USBPHY_RX_TOG_ENVADJ_SHIFT (0U) +#define USBPHY_RX_TOG_ENVADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_TOG_ENVADJ_SHIFT)) & USBPHY_RX_TOG_ENVADJ_MASK) +#define USBPHY_RX_TOG_RSVD0_MASK (0x8U) +#define USBPHY_RX_TOG_RSVD0_SHIFT (3U) +#define USBPHY_RX_TOG_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_TOG_RSVD0_SHIFT)) & USBPHY_RX_TOG_RSVD0_MASK) +#define USBPHY_RX_TOG_DISCONADJ_MASK (0x70U) +#define USBPHY_RX_TOG_DISCONADJ_SHIFT (4U) +#define USBPHY_RX_TOG_DISCONADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_TOG_DISCONADJ_SHIFT)) & USBPHY_RX_TOG_DISCONADJ_MASK) +#define USBPHY_RX_TOG_RSVD1_MASK (0x3FFF80U) +#define USBPHY_RX_TOG_RSVD1_SHIFT (7U) +#define USBPHY_RX_TOG_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_TOG_RSVD1_SHIFT)) & USBPHY_RX_TOG_RSVD1_MASK) +#define USBPHY_RX_TOG_RXDBYPASS_MASK (0x400000U) +#define USBPHY_RX_TOG_RXDBYPASS_SHIFT (22U) +#define USBPHY_RX_TOG_RXDBYPASS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_TOG_RXDBYPASS_SHIFT)) & USBPHY_RX_TOG_RXDBYPASS_MASK) +#define USBPHY_RX_TOG_RSVD2_MASK (0xFF800000U) +#define USBPHY_RX_TOG_RSVD2_SHIFT (23U) +#define USBPHY_RX_TOG_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_TOG_RSVD2_SHIFT)) & USBPHY_RX_TOG_RSVD2_MASK) +/*! @} */ + +/*! @name CTRL - USB PHY General Control Register */ +/*! @{ */ +#define USBPHY_CTRL_ENOTG_ID_CHG_IRQ_MASK (0x1U) +#define USBPHY_CTRL_ENOTG_ID_CHG_IRQ_SHIFT (0U) +#define USBPHY_CTRL_ENOTG_ID_CHG_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENOTG_ID_CHG_IRQ_SHIFT)) & USBPHY_CTRL_ENOTG_ID_CHG_IRQ_MASK) +#define USBPHY_CTRL_ENHOSTDISCONDETECT_MASK (0x2U) +#define USBPHY_CTRL_ENHOSTDISCONDETECT_SHIFT (1U) +#define USBPHY_CTRL_ENHOSTDISCONDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENHOSTDISCONDETECT_SHIFT)) & USBPHY_CTRL_ENHOSTDISCONDETECT_MASK) +#define USBPHY_CTRL_ENIRQHOSTDISCON_MASK (0x4U) +#define USBPHY_CTRL_ENIRQHOSTDISCON_SHIFT (2U) +#define USBPHY_CTRL_ENIRQHOSTDISCON(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENIRQHOSTDISCON_SHIFT)) & USBPHY_CTRL_ENIRQHOSTDISCON_MASK) +#define USBPHY_CTRL_HOSTDISCONDETECT_IRQ_MASK (0x8U) +#define USBPHY_CTRL_HOSTDISCONDETECT_IRQ_SHIFT (3U) +#define USBPHY_CTRL_HOSTDISCONDETECT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_HOSTDISCONDETECT_IRQ_SHIFT)) & USBPHY_CTRL_HOSTDISCONDETECT_IRQ_MASK) +#define USBPHY_CTRL_ENDEVPLUGINDETECT_MASK (0x10U) +#define USBPHY_CTRL_ENDEVPLUGINDETECT_SHIFT (4U) +#define USBPHY_CTRL_ENDEVPLUGINDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENDEVPLUGINDETECT_SHIFT)) & USBPHY_CTRL_ENDEVPLUGINDETECT_MASK) +#define USBPHY_CTRL_DEVPLUGIN_POLARITY_MASK (0x20U) +#define USBPHY_CTRL_DEVPLUGIN_POLARITY_SHIFT (5U) +#define USBPHY_CTRL_DEVPLUGIN_POLARITY(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_DEVPLUGIN_POLARITY_SHIFT)) & USBPHY_CTRL_DEVPLUGIN_POLARITY_MASK) +#define USBPHY_CTRL_OTG_ID_CHG_IRQ_MASK (0x40U) +#define USBPHY_CTRL_OTG_ID_CHG_IRQ_SHIFT (6U) +#define USBPHY_CTRL_OTG_ID_CHG_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_OTG_ID_CHG_IRQ_SHIFT)) & USBPHY_CTRL_OTG_ID_CHG_IRQ_MASK) +#define USBPHY_CTRL_ENOTGIDDETECT_MASK (0x80U) +#define USBPHY_CTRL_ENOTGIDDETECT_SHIFT (7U) +#define USBPHY_CTRL_ENOTGIDDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENOTGIDDETECT_SHIFT)) & USBPHY_CTRL_ENOTGIDDETECT_MASK) +#define USBPHY_CTRL_RESUMEIRQSTICKY_MASK (0x100U) +#define USBPHY_CTRL_RESUMEIRQSTICKY_SHIFT (8U) +#define USBPHY_CTRL_RESUMEIRQSTICKY(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_RESUMEIRQSTICKY_SHIFT)) & USBPHY_CTRL_RESUMEIRQSTICKY_MASK) +#define USBPHY_CTRL_ENIRQRESUMEDETECT_MASK (0x200U) +#define USBPHY_CTRL_ENIRQRESUMEDETECT_SHIFT (9U) +#define USBPHY_CTRL_ENIRQRESUMEDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENIRQRESUMEDETECT_SHIFT)) & USBPHY_CTRL_ENIRQRESUMEDETECT_MASK) +#define USBPHY_CTRL_RESUME_IRQ_MASK (0x400U) +#define USBPHY_CTRL_RESUME_IRQ_SHIFT (10U) +#define USBPHY_CTRL_RESUME_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_RESUME_IRQ_SHIFT)) & USBPHY_CTRL_RESUME_IRQ_MASK) +#define USBPHY_CTRL_ENIRQDEVPLUGIN_MASK (0x800U) +#define USBPHY_CTRL_ENIRQDEVPLUGIN_SHIFT (11U) +#define USBPHY_CTRL_ENIRQDEVPLUGIN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENIRQDEVPLUGIN_SHIFT)) & USBPHY_CTRL_ENIRQDEVPLUGIN_MASK) +#define USBPHY_CTRL_DEVPLUGIN_IRQ_MASK (0x1000U) +#define USBPHY_CTRL_DEVPLUGIN_IRQ_SHIFT (12U) +#define USBPHY_CTRL_DEVPLUGIN_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_DEVPLUGIN_IRQ_SHIFT)) & USBPHY_CTRL_DEVPLUGIN_IRQ_MASK) +#define USBPHY_CTRL_DATA_ON_LRADC_MASK (0x2000U) +#define USBPHY_CTRL_DATA_ON_LRADC_SHIFT (13U) +#define USBPHY_CTRL_DATA_ON_LRADC(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_DATA_ON_LRADC_SHIFT)) & USBPHY_CTRL_DATA_ON_LRADC_MASK) +#define USBPHY_CTRL_ENUTMILEVEL2_MASK (0x4000U) +#define USBPHY_CTRL_ENUTMILEVEL2_SHIFT (14U) +#define USBPHY_CTRL_ENUTMILEVEL2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENUTMILEVEL2_SHIFT)) & USBPHY_CTRL_ENUTMILEVEL2_MASK) +#define USBPHY_CTRL_ENUTMILEVEL3_MASK (0x8000U) +#define USBPHY_CTRL_ENUTMILEVEL3_SHIFT (15U) +#define USBPHY_CTRL_ENUTMILEVEL3(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENUTMILEVEL3_SHIFT)) & USBPHY_CTRL_ENUTMILEVEL3_MASK) +#define USBPHY_CTRL_ENIRQWAKEUP_MASK (0x10000U) +#define USBPHY_CTRL_ENIRQWAKEUP_SHIFT (16U) +#define USBPHY_CTRL_ENIRQWAKEUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENIRQWAKEUP_SHIFT)) & USBPHY_CTRL_ENIRQWAKEUP_MASK) +#define USBPHY_CTRL_WAKEUP_IRQ_MASK (0x20000U) +#define USBPHY_CTRL_WAKEUP_IRQ_SHIFT (17U) +#define USBPHY_CTRL_WAKEUP_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_WAKEUP_IRQ_SHIFT)) & USBPHY_CTRL_WAKEUP_IRQ_MASK) +#define USBPHY_CTRL_ENAUTO_PWRON_PLL_MASK (0x40000U) +#define USBPHY_CTRL_ENAUTO_PWRON_PLL_SHIFT (18U) +#define USBPHY_CTRL_ENAUTO_PWRON_PLL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENAUTO_PWRON_PLL_SHIFT)) & USBPHY_CTRL_ENAUTO_PWRON_PLL_MASK) +#define USBPHY_CTRL_ENAUTOCLR_CLKGATE_MASK (0x80000U) +#define USBPHY_CTRL_ENAUTOCLR_CLKGATE_SHIFT (19U) +#define USBPHY_CTRL_ENAUTOCLR_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENAUTOCLR_CLKGATE_SHIFT)) & USBPHY_CTRL_ENAUTOCLR_CLKGATE_MASK) +#define USBPHY_CTRL_ENAUTOCLR_PHY_PWD_MASK (0x100000U) +#define USBPHY_CTRL_ENAUTOCLR_PHY_PWD_SHIFT (20U) +#define USBPHY_CTRL_ENAUTOCLR_PHY_PWD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENAUTOCLR_PHY_PWD_SHIFT)) & USBPHY_CTRL_ENAUTOCLR_PHY_PWD_MASK) +#define USBPHY_CTRL_ENDPDMCHG_WKUP_MASK (0x200000U) +#define USBPHY_CTRL_ENDPDMCHG_WKUP_SHIFT (21U) +#define USBPHY_CTRL_ENDPDMCHG_WKUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENDPDMCHG_WKUP_SHIFT)) & USBPHY_CTRL_ENDPDMCHG_WKUP_MASK) +#define USBPHY_CTRL_ENIDCHG_WKUP_MASK (0x400000U) +#define USBPHY_CTRL_ENIDCHG_WKUP_SHIFT (22U) +#define USBPHY_CTRL_ENIDCHG_WKUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENIDCHG_WKUP_SHIFT)) & USBPHY_CTRL_ENIDCHG_WKUP_MASK) +#define USBPHY_CTRL_ENVBUSCHG_WKUP_MASK (0x800000U) +#define USBPHY_CTRL_ENVBUSCHG_WKUP_SHIFT (23U) +#define USBPHY_CTRL_ENVBUSCHG_WKUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENVBUSCHG_WKUP_SHIFT)) & USBPHY_CTRL_ENVBUSCHG_WKUP_MASK) +#define USBPHY_CTRL_FSDLL_RST_EN_MASK (0x1000000U) +#define USBPHY_CTRL_FSDLL_RST_EN_SHIFT (24U) +#define USBPHY_CTRL_FSDLL_RST_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_FSDLL_RST_EN_SHIFT)) & USBPHY_CTRL_FSDLL_RST_EN_MASK) +#define USBPHY_CTRL_RSVD1_MASK (0x6000000U) +#define USBPHY_CTRL_RSVD1_SHIFT (25U) +#define USBPHY_CTRL_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_RSVD1_SHIFT)) & USBPHY_CTRL_RSVD1_MASK) +#define USBPHY_CTRL_OTG_ID_VALUE_MASK (0x8000000U) +#define USBPHY_CTRL_OTG_ID_VALUE_SHIFT (27U) +#define USBPHY_CTRL_OTG_ID_VALUE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_OTG_ID_VALUE_SHIFT)) & USBPHY_CTRL_OTG_ID_VALUE_MASK) +#define USBPHY_CTRL_HOST_FORCE_LS_SE0_MASK (0x10000000U) +#define USBPHY_CTRL_HOST_FORCE_LS_SE0_SHIFT (28U) +#define USBPHY_CTRL_HOST_FORCE_LS_SE0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_HOST_FORCE_LS_SE0_SHIFT)) & USBPHY_CTRL_HOST_FORCE_LS_SE0_MASK) +#define USBPHY_CTRL_UTMI_SUSPENDM_MASK (0x20000000U) +#define USBPHY_CTRL_UTMI_SUSPENDM_SHIFT (29U) +#define USBPHY_CTRL_UTMI_SUSPENDM(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_UTMI_SUSPENDM_SHIFT)) & USBPHY_CTRL_UTMI_SUSPENDM_MASK) +#define USBPHY_CTRL_CLKGATE_MASK (0x40000000U) +#define USBPHY_CTRL_CLKGATE_SHIFT (30U) +#define USBPHY_CTRL_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLKGATE_SHIFT)) & USBPHY_CTRL_CLKGATE_MASK) +#define USBPHY_CTRL_SFTRST_MASK (0x80000000U) +#define USBPHY_CTRL_SFTRST_SHIFT (31U) +#define USBPHY_CTRL_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SFTRST_SHIFT)) & USBPHY_CTRL_SFTRST_MASK) +/*! @} */ + +/*! @name CTRL_SET - USB PHY General Control Register */ +/*! @{ */ +#define USBPHY_CTRL_SET_ENOTG_ID_CHG_IRQ_MASK (0x1U) +#define USBPHY_CTRL_SET_ENOTG_ID_CHG_IRQ_SHIFT (0U) +#define USBPHY_CTRL_SET_ENOTG_ID_CHG_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENOTG_ID_CHG_IRQ_SHIFT)) & USBPHY_CTRL_SET_ENOTG_ID_CHG_IRQ_MASK) +#define USBPHY_CTRL_SET_ENHOSTDISCONDETECT_MASK (0x2U) +#define USBPHY_CTRL_SET_ENHOSTDISCONDETECT_SHIFT (1U) +#define USBPHY_CTRL_SET_ENHOSTDISCONDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENHOSTDISCONDETECT_SHIFT)) & USBPHY_CTRL_SET_ENHOSTDISCONDETECT_MASK) +#define USBPHY_CTRL_SET_ENIRQHOSTDISCON_MASK (0x4U) +#define USBPHY_CTRL_SET_ENIRQHOSTDISCON_SHIFT (2U) +#define USBPHY_CTRL_SET_ENIRQHOSTDISCON(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENIRQHOSTDISCON_SHIFT)) & USBPHY_CTRL_SET_ENIRQHOSTDISCON_MASK) +#define USBPHY_CTRL_SET_HOSTDISCONDETECT_IRQ_MASK (0x8U) +#define USBPHY_CTRL_SET_HOSTDISCONDETECT_IRQ_SHIFT (3U) +#define USBPHY_CTRL_SET_HOSTDISCONDETECT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_HOSTDISCONDETECT_IRQ_SHIFT)) & USBPHY_CTRL_SET_HOSTDISCONDETECT_IRQ_MASK) +#define USBPHY_CTRL_SET_ENDEVPLUGINDETECT_MASK (0x10U) +#define USBPHY_CTRL_SET_ENDEVPLUGINDETECT_SHIFT (4U) +#define USBPHY_CTRL_SET_ENDEVPLUGINDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENDEVPLUGINDETECT_SHIFT)) & USBPHY_CTRL_SET_ENDEVPLUGINDETECT_MASK) +#define USBPHY_CTRL_SET_DEVPLUGIN_POLARITY_MASK (0x20U) +#define USBPHY_CTRL_SET_DEVPLUGIN_POLARITY_SHIFT (5U) +#define USBPHY_CTRL_SET_DEVPLUGIN_POLARITY(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_DEVPLUGIN_POLARITY_SHIFT)) & USBPHY_CTRL_SET_DEVPLUGIN_POLARITY_MASK) +#define USBPHY_CTRL_SET_OTG_ID_CHG_IRQ_MASK (0x40U) +#define USBPHY_CTRL_SET_OTG_ID_CHG_IRQ_SHIFT (6U) +#define USBPHY_CTRL_SET_OTG_ID_CHG_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_OTG_ID_CHG_IRQ_SHIFT)) & USBPHY_CTRL_SET_OTG_ID_CHG_IRQ_MASK) +#define USBPHY_CTRL_SET_ENOTGIDDETECT_MASK (0x80U) +#define USBPHY_CTRL_SET_ENOTGIDDETECT_SHIFT (7U) +#define USBPHY_CTRL_SET_ENOTGIDDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENOTGIDDETECT_SHIFT)) & USBPHY_CTRL_SET_ENOTGIDDETECT_MASK) +#define USBPHY_CTRL_SET_RESUMEIRQSTICKY_MASK (0x100U) +#define USBPHY_CTRL_SET_RESUMEIRQSTICKY_SHIFT (8U) +#define USBPHY_CTRL_SET_RESUMEIRQSTICKY(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_RESUMEIRQSTICKY_SHIFT)) & USBPHY_CTRL_SET_RESUMEIRQSTICKY_MASK) +#define USBPHY_CTRL_SET_ENIRQRESUMEDETECT_MASK (0x200U) +#define USBPHY_CTRL_SET_ENIRQRESUMEDETECT_SHIFT (9U) +#define USBPHY_CTRL_SET_ENIRQRESUMEDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENIRQRESUMEDETECT_SHIFT)) & USBPHY_CTRL_SET_ENIRQRESUMEDETECT_MASK) +#define USBPHY_CTRL_SET_RESUME_IRQ_MASK (0x400U) +#define USBPHY_CTRL_SET_RESUME_IRQ_SHIFT (10U) +#define USBPHY_CTRL_SET_RESUME_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_RESUME_IRQ_SHIFT)) & USBPHY_CTRL_SET_RESUME_IRQ_MASK) +#define USBPHY_CTRL_SET_ENIRQDEVPLUGIN_MASK (0x800U) +#define USBPHY_CTRL_SET_ENIRQDEVPLUGIN_SHIFT (11U) +#define USBPHY_CTRL_SET_ENIRQDEVPLUGIN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENIRQDEVPLUGIN_SHIFT)) & USBPHY_CTRL_SET_ENIRQDEVPLUGIN_MASK) +#define USBPHY_CTRL_SET_DEVPLUGIN_IRQ_MASK (0x1000U) +#define USBPHY_CTRL_SET_DEVPLUGIN_IRQ_SHIFT (12U) +#define USBPHY_CTRL_SET_DEVPLUGIN_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_DEVPLUGIN_IRQ_SHIFT)) & USBPHY_CTRL_SET_DEVPLUGIN_IRQ_MASK) +#define USBPHY_CTRL_SET_DATA_ON_LRADC_MASK (0x2000U) +#define USBPHY_CTRL_SET_DATA_ON_LRADC_SHIFT (13U) +#define USBPHY_CTRL_SET_DATA_ON_LRADC(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_DATA_ON_LRADC_SHIFT)) & USBPHY_CTRL_SET_DATA_ON_LRADC_MASK) +#define USBPHY_CTRL_SET_ENUTMILEVEL2_MASK (0x4000U) +#define USBPHY_CTRL_SET_ENUTMILEVEL2_SHIFT (14U) +#define USBPHY_CTRL_SET_ENUTMILEVEL2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENUTMILEVEL2_SHIFT)) & USBPHY_CTRL_SET_ENUTMILEVEL2_MASK) +#define USBPHY_CTRL_SET_ENUTMILEVEL3_MASK (0x8000U) +#define USBPHY_CTRL_SET_ENUTMILEVEL3_SHIFT (15U) +#define USBPHY_CTRL_SET_ENUTMILEVEL3(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENUTMILEVEL3_SHIFT)) & USBPHY_CTRL_SET_ENUTMILEVEL3_MASK) +#define USBPHY_CTRL_SET_ENIRQWAKEUP_MASK (0x10000U) +#define USBPHY_CTRL_SET_ENIRQWAKEUP_SHIFT (16U) +#define USBPHY_CTRL_SET_ENIRQWAKEUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENIRQWAKEUP_SHIFT)) & USBPHY_CTRL_SET_ENIRQWAKEUP_MASK) +#define USBPHY_CTRL_SET_WAKEUP_IRQ_MASK (0x20000U) +#define USBPHY_CTRL_SET_WAKEUP_IRQ_SHIFT (17U) +#define USBPHY_CTRL_SET_WAKEUP_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_WAKEUP_IRQ_SHIFT)) & USBPHY_CTRL_SET_WAKEUP_IRQ_MASK) +#define USBPHY_CTRL_SET_ENAUTO_PWRON_PLL_MASK (0x40000U) +#define USBPHY_CTRL_SET_ENAUTO_PWRON_PLL_SHIFT (18U) +#define USBPHY_CTRL_SET_ENAUTO_PWRON_PLL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENAUTO_PWRON_PLL_SHIFT)) & USBPHY_CTRL_SET_ENAUTO_PWRON_PLL_MASK) +#define USBPHY_CTRL_SET_ENAUTOCLR_CLKGATE_MASK (0x80000U) +#define USBPHY_CTRL_SET_ENAUTOCLR_CLKGATE_SHIFT (19U) +#define USBPHY_CTRL_SET_ENAUTOCLR_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENAUTOCLR_CLKGATE_SHIFT)) & USBPHY_CTRL_SET_ENAUTOCLR_CLKGATE_MASK) +#define USBPHY_CTRL_SET_ENAUTOCLR_PHY_PWD_MASK (0x100000U) +#define USBPHY_CTRL_SET_ENAUTOCLR_PHY_PWD_SHIFT (20U) +#define USBPHY_CTRL_SET_ENAUTOCLR_PHY_PWD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENAUTOCLR_PHY_PWD_SHIFT)) & USBPHY_CTRL_SET_ENAUTOCLR_PHY_PWD_MASK) +#define USBPHY_CTRL_SET_ENDPDMCHG_WKUP_MASK (0x200000U) +#define USBPHY_CTRL_SET_ENDPDMCHG_WKUP_SHIFT (21U) +#define USBPHY_CTRL_SET_ENDPDMCHG_WKUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENDPDMCHG_WKUP_SHIFT)) & USBPHY_CTRL_SET_ENDPDMCHG_WKUP_MASK) +#define USBPHY_CTRL_SET_ENIDCHG_WKUP_MASK (0x400000U) +#define USBPHY_CTRL_SET_ENIDCHG_WKUP_SHIFT (22U) +#define USBPHY_CTRL_SET_ENIDCHG_WKUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENIDCHG_WKUP_SHIFT)) & USBPHY_CTRL_SET_ENIDCHG_WKUP_MASK) +#define USBPHY_CTRL_SET_ENVBUSCHG_WKUP_MASK (0x800000U) +#define USBPHY_CTRL_SET_ENVBUSCHG_WKUP_SHIFT (23U) +#define USBPHY_CTRL_SET_ENVBUSCHG_WKUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENVBUSCHG_WKUP_SHIFT)) & USBPHY_CTRL_SET_ENVBUSCHG_WKUP_MASK) +#define USBPHY_CTRL_SET_FSDLL_RST_EN_MASK (0x1000000U) +#define USBPHY_CTRL_SET_FSDLL_RST_EN_SHIFT (24U) +#define USBPHY_CTRL_SET_FSDLL_RST_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_FSDLL_RST_EN_SHIFT)) & USBPHY_CTRL_SET_FSDLL_RST_EN_MASK) +#define USBPHY_CTRL_SET_RSVD1_MASK (0x6000000U) +#define USBPHY_CTRL_SET_RSVD1_SHIFT (25U) +#define USBPHY_CTRL_SET_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_RSVD1_SHIFT)) & USBPHY_CTRL_SET_RSVD1_MASK) +#define USBPHY_CTRL_SET_OTG_ID_VALUE_MASK (0x8000000U) +#define USBPHY_CTRL_SET_OTG_ID_VALUE_SHIFT (27U) +#define USBPHY_CTRL_SET_OTG_ID_VALUE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_OTG_ID_VALUE_SHIFT)) & USBPHY_CTRL_SET_OTG_ID_VALUE_MASK) +#define USBPHY_CTRL_SET_HOST_FORCE_LS_SE0_MASK (0x10000000U) +#define USBPHY_CTRL_SET_HOST_FORCE_LS_SE0_SHIFT (28U) +#define USBPHY_CTRL_SET_HOST_FORCE_LS_SE0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_HOST_FORCE_LS_SE0_SHIFT)) & USBPHY_CTRL_SET_HOST_FORCE_LS_SE0_MASK) +#define USBPHY_CTRL_SET_UTMI_SUSPENDM_MASK (0x20000000U) +#define USBPHY_CTRL_SET_UTMI_SUSPENDM_SHIFT (29U) +#define USBPHY_CTRL_SET_UTMI_SUSPENDM(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_UTMI_SUSPENDM_SHIFT)) & USBPHY_CTRL_SET_UTMI_SUSPENDM_MASK) +#define USBPHY_CTRL_SET_CLKGATE_MASK (0x40000000U) +#define USBPHY_CTRL_SET_CLKGATE_SHIFT (30U) +#define USBPHY_CTRL_SET_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_CLKGATE_SHIFT)) & USBPHY_CTRL_SET_CLKGATE_MASK) +#define USBPHY_CTRL_SET_SFTRST_MASK (0x80000000U) +#define USBPHY_CTRL_SET_SFTRST_SHIFT (31U) +#define USBPHY_CTRL_SET_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_SFTRST_SHIFT)) & USBPHY_CTRL_SET_SFTRST_MASK) +/*! @} */ + +/*! @name CTRL_CLR - USB PHY General Control Register */ +/*! @{ */ +#define USBPHY_CTRL_CLR_ENOTG_ID_CHG_IRQ_MASK (0x1U) +#define USBPHY_CTRL_CLR_ENOTG_ID_CHG_IRQ_SHIFT (0U) +#define USBPHY_CTRL_CLR_ENOTG_ID_CHG_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENOTG_ID_CHG_IRQ_SHIFT)) & USBPHY_CTRL_CLR_ENOTG_ID_CHG_IRQ_MASK) +#define USBPHY_CTRL_CLR_ENHOSTDISCONDETECT_MASK (0x2U) +#define USBPHY_CTRL_CLR_ENHOSTDISCONDETECT_SHIFT (1U) +#define USBPHY_CTRL_CLR_ENHOSTDISCONDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENHOSTDISCONDETECT_SHIFT)) & USBPHY_CTRL_CLR_ENHOSTDISCONDETECT_MASK) +#define USBPHY_CTRL_CLR_ENIRQHOSTDISCON_MASK (0x4U) +#define USBPHY_CTRL_CLR_ENIRQHOSTDISCON_SHIFT (2U) +#define USBPHY_CTRL_CLR_ENIRQHOSTDISCON(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENIRQHOSTDISCON_SHIFT)) & USBPHY_CTRL_CLR_ENIRQHOSTDISCON_MASK) +#define USBPHY_CTRL_CLR_HOSTDISCONDETECT_IRQ_MASK (0x8U) +#define USBPHY_CTRL_CLR_HOSTDISCONDETECT_IRQ_SHIFT (3U) +#define USBPHY_CTRL_CLR_HOSTDISCONDETECT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_HOSTDISCONDETECT_IRQ_SHIFT)) & USBPHY_CTRL_CLR_HOSTDISCONDETECT_IRQ_MASK) +#define USBPHY_CTRL_CLR_ENDEVPLUGINDETECT_MASK (0x10U) +#define USBPHY_CTRL_CLR_ENDEVPLUGINDETECT_SHIFT (4U) +#define USBPHY_CTRL_CLR_ENDEVPLUGINDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENDEVPLUGINDETECT_SHIFT)) & USBPHY_CTRL_CLR_ENDEVPLUGINDETECT_MASK) +#define USBPHY_CTRL_CLR_DEVPLUGIN_POLARITY_MASK (0x20U) +#define USBPHY_CTRL_CLR_DEVPLUGIN_POLARITY_SHIFT (5U) +#define USBPHY_CTRL_CLR_DEVPLUGIN_POLARITY(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_DEVPLUGIN_POLARITY_SHIFT)) & USBPHY_CTRL_CLR_DEVPLUGIN_POLARITY_MASK) +#define USBPHY_CTRL_CLR_OTG_ID_CHG_IRQ_MASK (0x40U) +#define USBPHY_CTRL_CLR_OTG_ID_CHG_IRQ_SHIFT (6U) +#define USBPHY_CTRL_CLR_OTG_ID_CHG_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_OTG_ID_CHG_IRQ_SHIFT)) & USBPHY_CTRL_CLR_OTG_ID_CHG_IRQ_MASK) +#define USBPHY_CTRL_CLR_ENOTGIDDETECT_MASK (0x80U) +#define USBPHY_CTRL_CLR_ENOTGIDDETECT_SHIFT (7U) +#define USBPHY_CTRL_CLR_ENOTGIDDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENOTGIDDETECT_SHIFT)) & USBPHY_CTRL_CLR_ENOTGIDDETECT_MASK) +#define USBPHY_CTRL_CLR_RESUMEIRQSTICKY_MASK (0x100U) +#define USBPHY_CTRL_CLR_RESUMEIRQSTICKY_SHIFT (8U) +#define USBPHY_CTRL_CLR_RESUMEIRQSTICKY(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_RESUMEIRQSTICKY_SHIFT)) & USBPHY_CTRL_CLR_RESUMEIRQSTICKY_MASK) +#define USBPHY_CTRL_CLR_ENIRQRESUMEDETECT_MASK (0x200U) +#define USBPHY_CTRL_CLR_ENIRQRESUMEDETECT_SHIFT (9U) +#define USBPHY_CTRL_CLR_ENIRQRESUMEDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENIRQRESUMEDETECT_SHIFT)) & USBPHY_CTRL_CLR_ENIRQRESUMEDETECT_MASK) +#define USBPHY_CTRL_CLR_RESUME_IRQ_MASK (0x400U) +#define USBPHY_CTRL_CLR_RESUME_IRQ_SHIFT (10U) +#define USBPHY_CTRL_CLR_RESUME_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_RESUME_IRQ_SHIFT)) & USBPHY_CTRL_CLR_RESUME_IRQ_MASK) +#define USBPHY_CTRL_CLR_ENIRQDEVPLUGIN_MASK (0x800U) +#define USBPHY_CTRL_CLR_ENIRQDEVPLUGIN_SHIFT (11U) +#define USBPHY_CTRL_CLR_ENIRQDEVPLUGIN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENIRQDEVPLUGIN_SHIFT)) & USBPHY_CTRL_CLR_ENIRQDEVPLUGIN_MASK) +#define USBPHY_CTRL_CLR_DEVPLUGIN_IRQ_MASK (0x1000U) +#define USBPHY_CTRL_CLR_DEVPLUGIN_IRQ_SHIFT (12U) +#define USBPHY_CTRL_CLR_DEVPLUGIN_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_DEVPLUGIN_IRQ_SHIFT)) & USBPHY_CTRL_CLR_DEVPLUGIN_IRQ_MASK) +#define USBPHY_CTRL_CLR_DATA_ON_LRADC_MASK (0x2000U) +#define USBPHY_CTRL_CLR_DATA_ON_LRADC_SHIFT (13U) +#define USBPHY_CTRL_CLR_DATA_ON_LRADC(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_DATA_ON_LRADC_SHIFT)) & USBPHY_CTRL_CLR_DATA_ON_LRADC_MASK) +#define USBPHY_CTRL_CLR_ENUTMILEVEL2_MASK (0x4000U) +#define USBPHY_CTRL_CLR_ENUTMILEVEL2_SHIFT (14U) +#define USBPHY_CTRL_CLR_ENUTMILEVEL2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENUTMILEVEL2_SHIFT)) & USBPHY_CTRL_CLR_ENUTMILEVEL2_MASK) +#define USBPHY_CTRL_CLR_ENUTMILEVEL3_MASK (0x8000U) +#define USBPHY_CTRL_CLR_ENUTMILEVEL3_SHIFT (15U) +#define USBPHY_CTRL_CLR_ENUTMILEVEL3(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENUTMILEVEL3_SHIFT)) & USBPHY_CTRL_CLR_ENUTMILEVEL3_MASK) +#define USBPHY_CTRL_CLR_ENIRQWAKEUP_MASK (0x10000U) +#define USBPHY_CTRL_CLR_ENIRQWAKEUP_SHIFT (16U) +#define USBPHY_CTRL_CLR_ENIRQWAKEUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENIRQWAKEUP_SHIFT)) & USBPHY_CTRL_CLR_ENIRQWAKEUP_MASK) +#define USBPHY_CTRL_CLR_WAKEUP_IRQ_MASK (0x20000U) +#define USBPHY_CTRL_CLR_WAKEUP_IRQ_SHIFT (17U) +#define USBPHY_CTRL_CLR_WAKEUP_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_WAKEUP_IRQ_SHIFT)) & USBPHY_CTRL_CLR_WAKEUP_IRQ_MASK) +#define USBPHY_CTRL_CLR_ENAUTO_PWRON_PLL_MASK (0x40000U) +#define USBPHY_CTRL_CLR_ENAUTO_PWRON_PLL_SHIFT (18U) +#define USBPHY_CTRL_CLR_ENAUTO_PWRON_PLL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENAUTO_PWRON_PLL_SHIFT)) & USBPHY_CTRL_CLR_ENAUTO_PWRON_PLL_MASK) +#define USBPHY_CTRL_CLR_ENAUTOCLR_CLKGATE_MASK (0x80000U) +#define USBPHY_CTRL_CLR_ENAUTOCLR_CLKGATE_SHIFT (19U) +#define USBPHY_CTRL_CLR_ENAUTOCLR_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENAUTOCLR_CLKGATE_SHIFT)) & USBPHY_CTRL_CLR_ENAUTOCLR_CLKGATE_MASK) +#define USBPHY_CTRL_CLR_ENAUTOCLR_PHY_PWD_MASK (0x100000U) +#define USBPHY_CTRL_CLR_ENAUTOCLR_PHY_PWD_SHIFT (20U) +#define USBPHY_CTRL_CLR_ENAUTOCLR_PHY_PWD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENAUTOCLR_PHY_PWD_SHIFT)) & USBPHY_CTRL_CLR_ENAUTOCLR_PHY_PWD_MASK) +#define USBPHY_CTRL_CLR_ENDPDMCHG_WKUP_MASK (0x200000U) +#define USBPHY_CTRL_CLR_ENDPDMCHG_WKUP_SHIFT (21U) +#define USBPHY_CTRL_CLR_ENDPDMCHG_WKUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENDPDMCHG_WKUP_SHIFT)) & USBPHY_CTRL_CLR_ENDPDMCHG_WKUP_MASK) +#define USBPHY_CTRL_CLR_ENIDCHG_WKUP_MASK (0x400000U) +#define USBPHY_CTRL_CLR_ENIDCHG_WKUP_SHIFT (22U) +#define USBPHY_CTRL_CLR_ENIDCHG_WKUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENIDCHG_WKUP_SHIFT)) & USBPHY_CTRL_CLR_ENIDCHG_WKUP_MASK) +#define USBPHY_CTRL_CLR_ENVBUSCHG_WKUP_MASK (0x800000U) +#define USBPHY_CTRL_CLR_ENVBUSCHG_WKUP_SHIFT (23U) +#define USBPHY_CTRL_CLR_ENVBUSCHG_WKUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENVBUSCHG_WKUP_SHIFT)) & USBPHY_CTRL_CLR_ENVBUSCHG_WKUP_MASK) +#define USBPHY_CTRL_CLR_FSDLL_RST_EN_MASK (0x1000000U) +#define USBPHY_CTRL_CLR_FSDLL_RST_EN_SHIFT (24U) +#define USBPHY_CTRL_CLR_FSDLL_RST_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_FSDLL_RST_EN_SHIFT)) & USBPHY_CTRL_CLR_FSDLL_RST_EN_MASK) +#define USBPHY_CTRL_CLR_RSVD1_MASK (0x6000000U) +#define USBPHY_CTRL_CLR_RSVD1_SHIFT (25U) +#define USBPHY_CTRL_CLR_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_RSVD1_SHIFT)) & USBPHY_CTRL_CLR_RSVD1_MASK) +#define USBPHY_CTRL_CLR_OTG_ID_VALUE_MASK (0x8000000U) +#define USBPHY_CTRL_CLR_OTG_ID_VALUE_SHIFT (27U) +#define USBPHY_CTRL_CLR_OTG_ID_VALUE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_OTG_ID_VALUE_SHIFT)) & USBPHY_CTRL_CLR_OTG_ID_VALUE_MASK) +#define USBPHY_CTRL_CLR_HOST_FORCE_LS_SE0_MASK (0x10000000U) +#define USBPHY_CTRL_CLR_HOST_FORCE_LS_SE0_SHIFT (28U) +#define USBPHY_CTRL_CLR_HOST_FORCE_LS_SE0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_HOST_FORCE_LS_SE0_SHIFT)) & USBPHY_CTRL_CLR_HOST_FORCE_LS_SE0_MASK) +#define USBPHY_CTRL_CLR_UTMI_SUSPENDM_MASK (0x20000000U) +#define USBPHY_CTRL_CLR_UTMI_SUSPENDM_SHIFT (29U) +#define USBPHY_CTRL_CLR_UTMI_SUSPENDM(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_UTMI_SUSPENDM_SHIFT)) & USBPHY_CTRL_CLR_UTMI_SUSPENDM_MASK) +#define USBPHY_CTRL_CLR_CLKGATE_MASK (0x40000000U) +#define USBPHY_CTRL_CLR_CLKGATE_SHIFT (30U) +#define USBPHY_CTRL_CLR_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_CLKGATE_SHIFT)) & USBPHY_CTRL_CLR_CLKGATE_MASK) +#define USBPHY_CTRL_CLR_SFTRST_MASK (0x80000000U) +#define USBPHY_CTRL_CLR_SFTRST_SHIFT (31U) +#define USBPHY_CTRL_CLR_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_SFTRST_SHIFT)) & USBPHY_CTRL_CLR_SFTRST_MASK) +/*! @} */ + +/*! @name CTRL_TOG - USB PHY General Control Register */ +/*! @{ */ +#define USBPHY_CTRL_TOG_ENOTG_ID_CHG_IRQ_MASK (0x1U) +#define USBPHY_CTRL_TOG_ENOTG_ID_CHG_IRQ_SHIFT (0U) +#define USBPHY_CTRL_TOG_ENOTG_ID_CHG_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENOTG_ID_CHG_IRQ_SHIFT)) & USBPHY_CTRL_TOG_ENOTG_ID_CHG_IRQ_MASK) +#define USBPHY_CTRL_TOG_ENHOSTDISCONDETECT_MASK (0x2U) +#define USBPHY_CTRL_TOG_ENHOSTDISCONDETECT_SHIFT (1U) +#define USBPHY_CTRL_TOG_ENHOSTDISCONDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENHOSTDISCONDETECT_SHIFT)) & USBPHY_CTRL_TOG_ENHOSTDISCONDETECT_MASK) +#define USBPHY_CTRL_TOG_ENIRQHOSTDISCON_MASK (0x4U) +#define USBPHY_CTRL_TOG_ENIRQHOSTDISCON_SHIFT (2U) +#define USBPHY_CTRL_TOG_ENIRQHOSTDISCON(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENIRQHOSTDISCON_SHIFT)) & USBPHY_CTRL_TOG_ENIRQHOSTDISCON_MASK) +#define USBPHY_CTRL_TOG_HOSTDISCONDETECT_IRQ_MASK (0x8U) +#define USBPHY_CTRL_TOG_HOSTDISCONDETECT_IRQ_SHIFT (3U) +#define USBPHY_CTRL_TOG_HOSTDISCONDETECT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_HOSTDISCONDETECT_IRQ_SHIFT)) & USBPHY_CTRL_TOG_HOSTDISCONDETECT_IRQ_MASK) +#define USBPHY_CTRL_TOG_ENDEVPLUGINDETECT_MASK (0x10U) +#define USBPHY_CTRL_TOG_ENDEVPLUGINDETECT_SHIFT (4U) +#define USBPHY_CTRL_TOG_ENDEVPLUGINDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENDEVPLUGINDETECT_SHIFT)) & USBPHY_CTRL_TOG_ENDEVPLUGINDETECT_MASK) +#define USBPHY_CTRL_TOG_DEVPLUGIN_POLARITY_MASK (0x20U) +#define USBPHY_CTRL_TOG_DEVPLUGIN_POLARITY_SHIFT (5U) +#define USBPHY_CTRL_TOG_DEVPLUGIN_POLARITY(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_DEVPLUGIN_POLARITY_SHIFT)) & USBPHY_CTRL_TOG_DEVPLUGIN_POLARITY_MASK) +#define USBPHY_CTRL_TOG_OTG_ID_CHG_IRQ_MASK (0x40U) +#define USBPHY_CTRL_TOG_OTG_ID_CHG_IRQ_SHIFT (6U) +#define USBPHY_CTRL_TOG_OTG_ID_CHG_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_OTG_ID_CHG_IRQ_SHIFT)) & USBPHY_CTRL_TOG_OTG_ID_CHG_IRQ_MASK) +#define USBPHY_CTRL_TOG_ENOTGIDDETECT_MASK (0x80U) +#define USBPHY_CTRL_TOG_ENOTGIDDETECT_SHIFT (7U) +#define USBPHY_CTRL_TOG_ENOTGIDDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENOTGIDDETECT_SHIFT)) & USBPHY_CTRL_TOG_ENOTGIDDETECT_MASK) +#define USBPHY_CTRL_TOG_RESUMEIRQSTICKY_MASK (0x100U) +#define USBPHY_CTRL_TOG_RESUMEIRQSTICKY_SHIFT (8U) +#define USBPHY_CTRL_TOG_RESUMEIRQSTICKY(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_RESUMEIRQSTICKY_SHIFT)) & USBPHY_CTRL_TOG_RESUMEIRQSTICKY_MASK) +#define USBPHY_CTRL_TOG_ENIRQRESUMEDETECT_MASK (0x200U) +#define USBPHY_CTRL_TOG_ENIRQRESUMEDETECT_SHIFT (9U) +#define USBPHY_CTRL_TOG_ENIRQRESUMEDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENIRQRESUMEDETECT_SHIFT)) & USBPHY_CTRL_TOG_ENIRQRESUMEDETECT_MASK) +#define USBPHY_CTRL_TOG_RESUME_IRQ_MASK (0x400U) +#define USBPHY_CTRL_TOG_RESUME_IRQ_SHIFT (10U) +#define USBPHY_CTRL_TOG_RESUME_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_RESUME_IRQ_SHIFT)) & USBPHY_CTRL_TOG_RESUME_IRQ_MASK) +#define USBPHY_CTRL_TOG_ENIRQDEVPLUGIN_MASK (0x800U) +#define USBPHY_CTRL_TOG_ENIRQDEVPLUGIN_SHIFT (11U) +#define USBPHY_CTRL_TOG_ENIRQDEVPLUGIN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENIRQDEVPLUGIN_SHIFT)) & USBPHY_CTRL_TOG_ENIRQDEVPLUGIN_MASK) +#define USBPHY_CTRL_TOG_DEVPLUGIN_IRQ_MASK (0x1000U) +#define USBPHY_CTRL_TOG_DEVPLUGIN_IRQ_SHIFT (12U) +#define USBPHY_CTRL_TOG_DEVPLUGIN_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_DEVPLUGIN_IRQ_SHIFT)) & USBPHY_CTRL_TOG_DEVPLUGIN_IRQ_MASK) +#define USBPHY_CTRL_TOG_DATA_ON_LRADC_MASK (0x2000U) +#define USBPHY_CTRL_TOG_DATA_ON_LRADC_SHIFT (13U) +#define USBPHY_CTRL_TOG_DATA_ON_LRADC(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_DATA_ON_LRADC_SHIFT)) & USBPHY_CTRL_TOG_DATA_ON_LRADC_MASK) +#define USBPHY_CTRL_TOG_ENUTMILEVEL2_MASK (0x4000U) +#define USBPHY_CTRL_TOG_ENUTMILEVEL2_SHIFT (14U) +#define USBPHY_CTRL_TOG_ENUTMILEVEL2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENUTMILEVEL2_SHIFT)) & USBPHY_CTRL_TOG_ENUTMILEVEL2_MASK) +#define USBPHY_CTRL_TOG_ENUTMILEVEL3_MASK (0x8000U) +#define USBPHY_CTRL_TOG_ENUTMILEVEL3_SHIFT (15U) +#define USBPHY_CTRL_TOG_ENUTMILEVEL3(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENUTMILEVEL3_SHIFT)) & USBPHY_CTRL_TOG_ENUTMILEVEL3_MASK) +#define USBPHY_CTRL_TOG_ENIRQWAKEUP_MASK (0x10000U) +#define USBPHY_CTRL_TOG_ENIRQWAKEUP_SHIFT (16U) +#define USBPHY_CTRL_TOG_ENIRQWAKEUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENIRQWAKEUP_SHIFT)) & USBPHY_CTRL_TOG_ENIRQWAKEUP_MASK) +#define USBPHY_CTRL_TOG_WAKEUP_IRQ_MASK (0x20000U) +#define USBPHY_CTRL_TOG_WAKEUP_IRQ_SHIFT (17U) +#define USBPHY_CTRL_TOG_WAKEUP_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_WAKEUP_IRQ_SHIFT)) & USBPHY_CTRL_TOG_WAKEUP_IRQ_MASK) +#define USBPHY_CTRL_TOG_ENAUTO_PWRON_PLL_MASK (0x40000U) +#define USBPHY_CTRL_TOG_ENAUTO_PWRON_PLL_SHIFT (18U) +#define USBPHY_CTRL_TOG_ENAUTO_PWRON_PLL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENAUTO_PWRON_PLL_SHIFT)) & USBPHY_CTRL_TOG_ENAUTO_PWRON_PLL_MASK) +#define USBPHY_CTRL_TOG_ENAUTOCLR_CLKGATE_MASK (0x80000U) +#define USBPHY_CTRL_TOG_ENAUTOCLR_CLKGATE_SHIFT (19U) +#define USBPHY_CTRL_TOG_ENAUTOCLR_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENAUTOCLR_CLKGATE_SHIFT)) & USBPHY_CTRL_TOG_ENAUTOCLR_CLKGATE_MASK) +#define USBPHY_CTRL_TOG_ENAUTOCLR_PHY_PWD_MASK (0x100000U) +#define USBPHY_CTRL_TOG_ENAUTOCLR_PHY_PWD_SHIFT (20U) +#define USBPHY_CTRL_TOG_ENAUTOCLR_PHY_PWD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENAUTOCLR_PHY_PWD_SHIFT)) & USBPHY_CTRL_TOG_ENAUTOCLR_PHY_PWD_MASK) +#define USBPHY_CTRL_TOG_ENDPDMCHG_WKUP_MASK (0x200000U) +#define USBPHY_CTRL_TOG_ENDPDMCHG_WKUP_SHIFT (21U) +#define USBPHY_CTRL_TOG_ENDPDMCHG_WKUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENDPDMCHG_WKUP_SHIFT)) & USBPHY_CTRL_TOG_ENDPDMCHG_WKUP_MASK) +#define USBPHY_CTRL_TOG_ENIDCHG_WKUP_MASK (0x400000U) +#define USBPHY_CTRL_TOG_ENIDCHG_WKUP_SHIFT (22U) +#define USBPHY_CTRL_TOG_ENIDCHG_WKUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENIDCHG_WKUP_SHIFT)) & USBPHY_CTRL_TOG_ENIDCHG_WKUP_MASK) +#define USBPHY_CTRL_TOG_ENVBUSCHG_WKUP_MASK (0x800000U) +#define USBPHY_CTRL_TOG_ENVBUSCHG_WKUP_SHIFT (23U) +#define USBPHY_CTRL_TOG_ENVBUSCHG_WKUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENVBUSCHG_WKUP_SHIFT)) & USBPHY_CTRL_TOG_ENVBUSCHG_WKUP_MASK) +#define USBPHY_CTRL_TOG_FSDLL_RST_EN_MASK (0x1000000U) +#define USBPHY_CTRL_TOG_FSDLL_RST_EN_SHIFT (24U) +#define USBPHY_CTRL_TOG_FSDLL_RST_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_FSDLL_RST_EN_SHIFT)) & USBPHY_CTRL_TOG_FSDLL_RST_EN_MASK) +#define USBPHY_CTRL_TOG_RSVD1_MASK (0x6000000U) +#define USBPHY_CTRL_TOG_RSVD1_SHIFT (25U) +#define USBPHY_CTRL_TOG_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_RSVD1_SHIFT)) & USBPHY_CTRL_TOG_RSVD1_MASK) +#define USBPHY_CTRL_TOG_OTG_ID_VALUE_MASK (0x8000000U) +#define USBPHY_CTRL_TOG_OTG_ID_VALUE_SHIFT (27U) +#define USBPHY_CTRL_TOG_OTG_ID_VALUE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_OTG_ID_VALUE_SHIFT)) & USBPHY_CTRL_TOG_OTG_ID_VALUE_MASK) +#define USBPHY_CTRL_TOG_HOST_FORCE_LS_SE0_MASK (0x10000000U) +#define USBPHY_CTRL_TOG_HOST_FORCE_LS_SE0_SHIFT (28U) +#define USBPHY_CTRL_TOG_HOST_FORCE_LS_SE0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_HOST_FORCE_LS_SE0_SHIFT)) & USBPHY_CTRL_TOG_HOST_FORCE_LS_SE0_MASK) +#define USBPHY_CTRL_TOG_UTMI_SUSPENDM_MASK (0x20000000U) +#define USBPHY_CTRL_TOG_UTMI_SUSPENDM_SHIFT (29U) +#define USBPHY_CTRL_TOG_UTMI_SUSPENDM(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_UTMI_SUSPENDM_SHIFT)) & USBPHY_CTRL_TOG_UTMI_SUSPENDM_MASK) +#define USBPHY_CTRL_TOG_CLKGATE_MASK (0x40000000U) +#define USBPHY_CTRL_TOG_CLKGATE_SHIFT (30U) +#define USBPHY_CTRL_TOG_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_CLKGATE_SHIFT)) & USBPHY_CTRL_TOG_CLKGATE_MASK) +#define USBPHY_CTRL_TOG_SFTRST_MASK (0x80000000U) +#define USBPHY_CTRL_TOG_SFTRST_SHIFT (31U) +#define USBPHY_CTRL_TOG_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_SFTRST_SHIFT)) & USBPHY_CTRL_TOG_SFTRST_MASK) +/*! @} */ + +/*! @name STATUS - USB PHY Status Register */ +/*! @{ */ +#define USBPHY_STATUS_RSVD0_MASK (0x7U) +#define USBPHY_STATUS_RSVD0_SHIFT (0U) +#define USBPHY_STATUS_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_STATUS_RSVD0_SHIFT)) & USBPHY_STATUS_RSVD0_MASK) +#define USBPHY_STATUS_HOSTDISCONDETECT_STATUS_MASK (0x8U) +#define USBPHY_STATUS_HOSTDISCONDETECT_STATUS_SHIFT (3U) +#define USBPHY_STATUS_HOSTDISCONDETECT_STATUS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_STATUS_HOSTDISCONDETECT_STATUS_SHIFT)) & USBPHY_STATUS_HOSTDISCONDETECT_STATUS_MASK) +#define USBPHY_STATUS_RSVD1_MASK (0x30U) +#define USBPHY_STATUS_RSVD1_SHIFT (4U) +#define USBPHY_STATUS_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_STATUS_RSVD1_SHIFT)) & USBPHY_STATUS_RSVD1_MASK) +#define USBPHY_STATUS_DEVPLUGIN_STATUS_MASK (0x40U) +#define USBPHY_STATUS_DEVPLUGIN_STATUS_SHIFT (6U) +#define USBPHY_STATUS_DEVPLUGIN_STATUS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_STATUS_DEVPLUGIN_STATUS_SHIFT)) & USBPHY_STATUS_DEVPLUGIN_STATUS_MASK) +#define USBPHY_STATUS_RSVD2_MASK (0x80U) +#define USBPHY_STATUS_RSVD2_SHIFT (7U) +#define USBPHY_STATUS_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_STATUS_RSVD2_SHIFT)) & USBPHY_STATUS_RSVD2_MASK) +#define USBPHY_STATUS_OTGID_STATUS_MASK (0x100U) +#define USBPHY_STATUS_OTGID_STATUS_SHIFT (8U) +#define USBPHY_STATUS_OTGID_STATUS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_STATUS_OTGID_STATUS_SHIFT)) & USBPHY_STATUS_OTGID_STATUS_MASK) +#define USBPHY_STATUS_RSVD3_MASK (0x200U) +#define USBPHY_STATUS_RSVD3_SHIFT (9U) +#define USBPHY_STATUS_RSVD3(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_STATUS_RSVD3_SHIFT)) & USBPHY_STATUS_RSVD3_MASK) +#define USBPHY_STATUS_RESUME_STATUS_MASK (0x400U) +#define USBPHY_STATUS_RESUME_STATUS_SHIFT (10U) +#define USBPHY_STATUS_RESUME_STATUS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_STATUS_RESUME_STATUS_SHIFT)) & USBPHY_STATUS_RESUME_STATUS_MASK) +#define USBPHY_STATUS_RSVD4_MASK (0xFFFFF800U) +#define USBPHY_STATUS_RSVD4_SHIFT (11U) +#define USBPHY_STATUS_RSVD4(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_STATUS_RSVD4_SHIFT)) & USBPHY_STATUS_RSVD4_MASK) +/*! @} */ + +/*! @name DEBUG - USB PHY Debug Register */ +/*! @{ */ +#define USBPHY_DEBUG_OTGIDPIOLOCK_MASK (0x1U) +#define USBPHY_DEBUG_OTGIDPIOLOCK_SHIFT (0U) +#define USBPHY_DEBUG_OTGIDPIOLOCK(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_OTGIDPIOLOCK_SHIFT)) & USBPHY_DEBUG_OTGIDPIOLOCK_MASK) +#define USBPHY_DEBUG_DEBUG_INTERFACE_HOLD_MASK (0x2U) +#define USBPHY_DEBUG_DEBUG_INTERFACE_HOLD_SHIFT (1U) +#define USBPHY_DEBUG_DEBUG_INTERFACE_HOLD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_DEBUG_INTERFACE_HOLD_SHIFT)) & USBPHY_DEBUG_DEBUG_INTERFACE_HOLD_MASK) +#define USBPHY_DEBUG_HSTPULLDOWN_MASK (0xCU) +#define USBPHY_DEBUG_HSTPULLDOWN_SHIFT (2U) +#define USBPHY_DEBUG_HSTPULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_HSTPULLDOWN_SHIFT)) & USBPHY_DEBUG_HSTPULLDOWN_MASK) +#define USBPHY_DEBUG_ENHSTPULLDOWN_MASK (0x30U) +#define USBPHY_DEBUG_ENHSTPULLDOWN_SHIFT (4U) +#define USBPHY_DEBUG_ENHSTPULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_ENHSTPULLDOWN_SHIFT)) & USBPHY_DEBUG_ENHSTPULLDOWN_MASK) +#define USBPHY_DEBUG_RSVD0_MASK (0xC0U) +#define USBPHY_DEBUG_RSVD0_SHIFT (6U) +#define USBPHY_DEBUG_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_RSVD0_SHIFT)) & USBPHY_DEBUG_RSVD0_MASK) +#define USBPHY_DEBUG_TX2RXCOUNT_MASK (0xF00U) +#define USBPHY_DEBUG_TX2RXCOUNT_SHIFT (8U) +#define USBPHY_DEBUG_TX2RXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TX2RXCOUNT_SHIFT)) & USBPHY_DEBUG_TX2RXCOUNT_MASK) +#define USBPHY_DEBUG_ENTX2RXCOUNT_MASK (0x1000U) +#define USBPHY_DEBUG_ENTX2RXCOUNT_SHIFT (12U) +#define USBPHY_DEBUG_ENTX2RXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_ENTX2RXCOUNT_SHIFT)) & USBPHY_DEBUG_ENTX2RXCOUNT_MASK) +#define USBPHY_DEBUG_RSVD1_MASK (0xE000U) +#define USBPHY_DEBUG_RSVD1_SHIFT (13U) +#define USBPHY_DEBUG_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_RSVD1_SHIFT)) & USBPHY_DEBUG_RSVD1_MASK) +#define USBPHY_DEBUG_SQUELCHRESETCOUNT_MASK (0x1F0000U) +#define USBPHY_DEBUG_SQUELCHRESETCOUNT_SHIFT (16U) +#define USBPHY_DEBUG_SQUELCHRESETCOUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SQUELCHRESETCOUNT_SHIFT)) & USBPHY_DEBUG_SQUELCHRESETCOUNT_MASK) +#define USBPHY_DEBUG_RSVD2_MASK (0xE00000U) +#define USBPHY_DEBUG_RSVD2_SHIFT (21U) +#define USBPHY_DEBUG_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_RSVD2_SHIFT)) & USBPHY_DEBUG_RSVD2_MASK) +#define USBPHY_DEBUG_ENSQUELCHRESET_MASK (0x1000000U) +#define USBPHY_DEBUG_ENSQUELCHRESET_SHIFT (24U) +#define USBPHY_DEBUG_ENSQUELCHRESET(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_ENSQUELCHRESET_SHIFT)) & USBPHY_DEBUG_ENSQUELCHRESET_MASK) +#define USBPHY_DEBUG_SQUELCHRESETLENGTH_MASK (0x1E000000U) +#define USBPHY_DEBUG_SQUELCHRESETLENGTH_SHIFT (25U) +#define USBPHY_DEBUG_SQUELCHRESETLENGTH(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SQUELCHRESETLENGTH_SHIFT)) & USBPHY_DEBUG_SQUELCHRESETLENGTH_MASK) +#define USBPHY_DEBUG_HOST_RESUME_DEBUG_MASK (0x20000000U) +#define USBPHY_DEBUG_HOST_RESUME_DEBUG_SHIFT (29U) +#define USBPHY_DEBUG_HOST_RESUME_DEBUG(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_HOST_RESUME_DEBUG_SHIFT)) & USBPHY_DEBUG_HOST_RESUME_DEBUG_MASK) +#define USBPHY_DEBUG_CLKGATE_MASK (0x40000000U) +#define USBPHY_DEBUG_CLKGATE_SHIFT (30U) +#define USBPHY_DEBUG_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLKGATE_SHIFT)) & USBPHY_DEBUG_CLKGATE_MASK) +#define USBPHY_DEBUG_RSVD3_MASK (0x80000000U) +#define USBPHY_DEBUG_RSVD3_SHIFT (31U) +#define USBPHY_DEBUG_RSVD3(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_RSVD3_SHIFT)) & USBPHY_DEBUG_RSVD3_MASK) +/*! @} */ + +/*! @name DEBUG_SET - USB PHY Debug Register */ +/*! @{ */ +#define USBPHY_DEBUG_SET_OTGIDPIOLOCK_MASK (0x1U) +#define USBPHY_DEBUG_SET_OTGIDPIOLOCK_SHIFT (0U) +#define USBPHY_DEBUG_SET_OTGIDPIOLOCK(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_OTGIDPIOLOCK_SHIFT)) & USBPHY_DEBUG_SET_OTGIDPIOLOCK_MASK) +#define USBPHY_DEBUG_SET_DEBUG_INTERFACE_HOLD_MASK (0x2U) +#define USBPHY_DEBUG_SET_DEBUG_INTERFACE_HOLD_SHIFT (1U) +#define USBPHY_DEBUG_SET_DEBUG_INTERFACE_HOLD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_DEBUG_INTERFACE_HOLD_SHIFT)) & USBPHY_DEBUG_SET_DEBUG_INTERFACE_HOLD_MASK) +#define USBPHY_DEBUG_SET_HSTPULLDOWN_MASK (0xCU) +#define USBPHY_DEBUG_SET_HSTPULLDOWN_SHIFT (2U) +#define USBPHY_DEBUG_SET_HSTPULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_HSTPULLDOWN_SHIFT)) & USBPHY_DEBUG_SET_HSTPULLDOWN_MASK) +#define USBPHY_DEBUG_SET_ENHSTPULLDOWN_MASK (0x30U) +#define USBPHY_DEBUG_SET_ENHSTPULLDOWN_SHIFT (4U) +#define USBPHY_DEBUG_SET_ENHSTPULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_ENHSTPULLDOWN_SHIFT)) & USBPHY_DEBUG_SET_ENHSTPULLDOWN_MASK) +#define USBPHY_DEBUG_SET_RSVD0_MASK (0xC0U) +#define USBPHY_DEBUG_SET_RSVD0_SHIFT (6U) +#define USBPHY_DEBUG_SET_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_RSVD0_SHIFT)) & USBPHY_DEBUG_SET_RSVD0_MASK) +#define USBPHY_DEBUG_SET_TX2RXCOUNT_MASK (0xF00U) +#define USBPHY_DEBUG_SET_TX2RXCOUNT_SHIFT (8U) +#define USBPHY_DEBUG_SET_TX2RXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_TX2RXCOUNT_SHIFT)) & USBPHY_DEBUG_SET_TX2RXCOUNT_MASK) +#define USBPHY_DEBUG_SET_ENTX2RXCOUNT_MASK (0x1000U) +#define USBPHY_DEBUG_SET_ENTX2RXCOUNT_SHIFT (12U) +#define USBPHY_DEBUG_SET_ENTX2RXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_ENTX2RXCOUNT_SHIFT)) & USBPHY_DEBUG_SET_ENTX2RXCOUNT_MASK) +#define USBPHY_DEBUG_SET_RSVD1_MASK (0xE000U) +#define USBPHY_DEBUG_SET_RSVD1_SHIFT (13U) +#define USBPHY_DEBUG_SET_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_RSVD1_SHIFT)) & USBPHY_DEBUG_SET_RSVD1_MASK) +#define USBPHY_DEBUG_SET_SQUELCHRESETCOUNT_MASK (0x1F0000U) +#define USBPHY_DEBUG_SET_SQUELCHRESETCOUNT_SHIFT (16U) +#define USBPHY_DEBUG_SET_SQUELCHRESETCOUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_SQUELCHRESETCOUNT_SHIFT)) & USBPHY_DEBUG_SET_SQUELCHRESETCOUNT_MASK) +#define USBPHY_DEBUG_SET_RSVD2_MASK (0xE00000U) +#define USBPHY_DEBUG_SET_RSVD2_SHIFT (21U) +#define USBPHY_DEBUG_SET_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_RSVD2_SHIFT)) & USBPHY_DEBUG_SET_RSVD2_MASK) +#define USBPHY_DEBUG_SET_ENSQUELCHRESET_MASK (0x1000000U) +#define USBPHY_DEBUG_SET_ENSQUELCHRESET_SHIFT (24U) +#define USBPHY_DEBUG_SET_ENSQUELCHRESET(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_ENSQUELCHRESET_SHIFT)) & USBPHY_DEBUG_SET_ENSQUELCHRESET_MASK) +#define USBPHY_DEBUG_SET_SQUELCHRESETLENGTH_MASK (0x1E000000U) +#define USBPHY_DEBUG_SET_SQUELCHRESETLENGTH_SHIFT (25U) +#define USBPHY_DEBUG_SET_SQUELCHRESETLENGTH(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_SQUELCHRESETLENGTH_SHIFT)) & USBPHY_DEBUG_SET_SQUELCHRESETLENGTH_MASK) +#define USBPHY_DEBUG_SET_HOST_RESUME_DEBUG_MASK (0x20000000U) +#define USBPHY_DEBUG_SET_HOST_RESUME_DEBUG_SHIFT (29U) +#define USBPHY_DEBUG_SET_HOST_RESUME_DEBUG(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_HOST_RESUME_DEBUG_SHIFT)) & USBPHY_DEBUG_SET_HOST_RESUME_DEBUG_MASK) +#define USBPHY_DEBUG_SET_CLKGATE_MASK (0x40000000U) +#define USBPHY_DEBUG_SET_CLKGATE_SHIFT (30U) +#define USBPHY_DEBUG_SET_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_CLKGATE_SHIFT)) & USBPHY_DEBUG_SET_CLKGATE_MASK) +#define USBPHY_DEBUG_SET_RSVD3_MASK (0x80000000U) +#define USBPHY_DEBUG_SET_RSVD3_SHIFT (31U) +#define USBPHY_DEBUG_SET_RSVD3(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_RSVD3_SHIFT)) & USBPHY_DEBUG_SET_RSVD3_MASK) +/*! @} */ + +/*! @name DEBUG_CLR - USB PHY Debug Register */ +/*! @{ */ +#define USBPHY_DEBUG_CLR_OTGIDPIOLOCK_MASK (0x1U) +#define USBPHY_DEBUG_CLR_OTGIDPIOLOCK_SHIFT (0U) +#define USBPHY_DEBUG_CLR_OTGIDPIOLOCK(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_OTGIDPIOLOCK_SHIFT)) & USBPHY_DEBUG_CLR_OTGIDPIOLOCK_MASK) +#define USBPHY_DEBUG_CLR_DEBUG_INTERFACE_HOLD_MASK (0x2U) +#define USBPHY_DEBUG_CLR_DEBUG_INTERFACE_HOLD_SHIFT (1U) +#define USBPHY_DEBUG_CLR_DEBUG_INTERFACE_HOLD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_DEBUG_INTERFACE_HOLD_SHIFT)) & USBPHY_DEBUG_CLR_DEBUG_INTERFACE_HOLD_MASK) +#define USBPHY_DEBUG_CLR_HSTPULLDOWN_MASK (0xCU) +#define USBPHY_DEBUG_CLR_HSTPULLDOWN_SHIFT (2U) +#define USBPHY_DEBUG_CLR_HSTPULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_HSTPULLDOWN_SHIFT)) & USBPHY_DEBUG_CLR_HSTPULLDOWN_MASK) +#define USBPHY_DEBUG_CLR_ENHSTPULLDOWN_MASK (0x30U) +#define USBPHY_DEBUG_CLR_ENHSTPULLDOWN_SHIFT (4U) +#define USBPHY_DEBUG_CLR_ENHSTPULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_ENHSTPULLDOWN_SHIFT)) & USBPHY_DEBUG_CLR_ENHSTPULLDOWN_MASK) +#define USBPHY_DEBUG_CLR_RSVD0_MASK (0xC0U) +#define USBPHY_DEBUG_CLR_RSVD0_SHIFT (6U) +#define USBPHY_DEBUG_CLR_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_RSVD0_SHIFT)) & USBPHY_DEBUG_CLR_RSVD0_MASK) +#define USBPHY_DEBUG_CLR_TX2RXCOUNT_MASK (0xF00U) +#define USBPHY_DEBUG_CLR_TX2RXCOUNT_SHIFT (8U) +#define USBPHY_DEBUG_CLR_TX2RXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_TX2RXCOUNT_SHIFT)) & USBPHY_DEBUG_CLR_TX2RXCOUNT_MASK) +#define USBPHY_DEBUG_CLR_ENTX2RXCOUNT_MASK (0x1000U) +#define USBPHY_DEBUG_CLR_ENTX2RXCOUNT_SHIFT (12U) +#define USBPHY_DEBUG_CLR_ENTX2RXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_ENTX2RXCOUNT_SHIFT)) & USBPHY_DEBUG_CLR_ENTX2RXCOUNT_MASK) +#define USBPHY_DEBUG_CLR_RSVD1_MASK (0xE000U) +#define USBPHY_DEBUG_CLR_RSVD1_SHIFT (13U) +#define USBPHY_DEBUG_CLR_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_RSVD1_SHIFT)) & USBPHY_DEBUG_CLR_RSVD1_MASK) +#define USBPHY_DEBUG_CLR_SQUELCHRESETCOUNT_MASK (0x1F0000U) +#define USBPHY_DEBUG_CLR_SQUELCHRESETCOUNT_SHIFT (16U) +#define USBPHY_DEBUG_CLR_SQUELCHRESETCOUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_SQUELCHRESETCOUNT_SHIFT)) & USBPHY_DEBUG_CLR_SQUELCHRESETCOUNT_MASK) +#define USBPHY_DEBUG_CLR_RSVD2_MASK (0xE00000U) +#define USBPHY_DEBUG_CLR_RSVD2_SHIFT (21U) +#define USBPHY_DEBUG_CLR_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_RSVD2_SHIFT)) & USBPHY_DEBUG_CLR_RSVD2_MASK) +#define USBPHY_DEBUG_CLR_ENSQUELCHRESET_MASK (0x1000000U) +#define USBPHY_DEBUG_CLR_ENSQUELCHRESET_SHIFT (24U) +#define USBPHY_DEBUG_CLR_ENSQUELCHRESET(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_ENSQUELCHRESET_SHIFT)) & USBPHY_DEBUG_CLR_ENSQUELCHRESET_MASK) +#define USBPHY_DEBUG_CLR_SQUELCHRESETLENGTH_MASK (0x1E000000U) +#define USBPHY_DEBUG_CLR_SQUELCHRESETLENGTH_SHIFT (25U) +#define USBPHY_DEBUG_CLR_SQUELCHRESETLENGTH(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_SQUELCHRESETLENGTH_SHIFT)) & USBPHY_DEBUG_CLR_SQUELCHRESETLENGTH_MASK) +#define USBPHY_DEBUG_CLR_HOST_RESUME_DEBUG_MASK (0x20000000U) +#define USBPHY_DEBUG_CLR_HOST_RESUME_DEBUG_SHIFT (29U) +#define USBPHY_DEBUG_CLR_HOST_RESUME_DEBUG(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_HOST_RESUME_DEBUG_SHIFT)) & USBPHY_DEBUG_CLR_HOST_RESUME_DEBUG_MASK) +#define USBPHY_DEBUG_CLR_CLKGATE_MASK (0x40000000U) +#define USBPHY_DEBUG_CLR_CLKGATE_SHIFT (30U) +#define USBPHY_DEBUG_CLR_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_CLKGATE_SHIFT)) & USBPHY_DEBUG_CLR_CLKGATE_MASK) +#define USBPHY_DEBUG_CLR_RSVD3_MASK (0x80000000U) +#define USBPHY_DEBUG_CLR_RSVD3_SHIFT (31U) +#define USBPHY_DEBUG_CLR_RSVD3(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_RSVD3_SHIFT)) & USBPHY_DEBUG_CLR_RSVD3_MASK) +/*! @} */ + +/*! @name DEBUG_TOG - USB PHY Debug Register */ +/*! @{ */ +#define USBPHY_DEBUG_TOG_OTGIDPIOLOCK_MASK (0x1U) +#define USBPHY_DEBUG_TOG_OTGIDPIOLOCK_SHIFT (0U) +#define USBPHY_DEBUG_TOG_OTGIDPIOLOCK(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_OTGIDPIOLOCK_SHIFT)) & USBPHY_DEBUG_TOG_OTGIDPIOLOCK_MASK) +#define USBPHY_DEBUG_TOG_DEBUG_INTERFACE_HOLD_MASK (0x2U) +#define USBPHY_DEBUG_TOG_DEBUG_INTERFACE_HOLD_SHIFT (1U) +#define USBPHY_DEBUG_TOG_DEBUG_INTERFACE_HOLD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_DEBUG_INTERFACE_HOLD_SHIFT)) & USBPHY_DEBUG_TOG_DEBUG_INTERFACE_HOLD_MASK) +#define USBPHY_DEBUG_TOG_HSTPULLDOWN_MASK (0xCU) +#define USBPHY_DEBUG_TOG_HSTPULLDOWN_SHIFT (2U) +#define USBPHY_DEBUG_TOG_HSTPULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_HSTPULLDOWN_SHIFT)) & USBPHY_DEBUG_TOG_HSTPULLDOWN_MASK) +#define USBPHY_DEBUG_TOG_ENHSTPULLDOWN_MASK (0x30U) +#define USBPHY_DEBUG_TOG_ENHSTPULLDOWN_SHIFT (4U) +#define USBPHY_DEBUG_TOG_ENHSTPULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_ENHSTPULLDOWN_SHIFT)) & USBPHY_DEBUG_TOG_ENHSTPULLDOWN_MASK) +#define USBPHY_DEBUG_TOG_RSVD0_MASK (0xC0U) +#define USBPHY_DEBUG_TOG_RSVD0_SHIFT (6U) +#define USBPHY_DEBUG_TOG_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_RSVD0_SHIFT)) & USBPHY_DEBUG_TOG_RSVD0_MASK) +#define USBPHY_DEBUG_TOG_TX2RXCOUNT_MASK (0xF00U) +#define USBPHY_DEBUG_TOG_TX2RXCOUNT_SHIFT (8U) +#define USBPHY_DEBUG_TOG_TX2RXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_TX2RXCOUNT_SHIFT)) & USBPHY_DEBUG_TOG_TX2RXCOUNT_MASK) +#define USBPHY_DEBUG_TOG_ENTX2RXCOUNT_MASK (0x1000U) +#define USBPHY_DEBUG_TOG_ENTX2RXCOUNT_SHIFT (12U) +#define USBPHY_DEBUG_TOG_ENTX2RXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_ENTX2RXCOUNT_SHIFT)) & USBPHY_DEBUG_TOG_ENTX2RXCOUNT_MASK) +#define USBPHY_DEBUG_TOG_RSVD1_MASK (0xE000U) +#define USBPHY_DEBUG_TOG_RSVD1_SHIFT (13U) +#define USBPHY_DEBUG_TOG_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_RSVD1_SHIFT)) & USBPHY_DEBUG_TOG_RSVD1_MASK) +#define USBPHY_DEBUG_TOG_SQUELCHRESETCOUNT_MASK (0x1F0000U) +#define USBPHY_DEBUG_TOG_SQUELCHRESETCOUNT_SHIFT (16U) +#define USBPHY_DEBUG_TOG_SQUELCHRESETCOUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_SQUELCHRESETCOUNT_SHIFT)) & USBPHY_DEBUG_TOG_SQUELCHRESETCOUNT_MASK) +#define USBPHY_DEBUG_TOG_RSVD2_MASK (0xE00000U) +#define USBPHY_DEBUG_TOG_RSVD2_SHIFT (21U) +#define USBPHY_DEBUG_TOG_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_RSVD2_SHIFT)) & USBPHY_DEBUG_TOG_RSVD2_MASK) +#define USBPHY_DEBUG_TOG_ENSQUELCHRESET_MASK (0x1000000U) +#define USBPHY_DEBUG_TOG_ENSQUELCHRESET_SHIFT (24U) +#define USBPHY_DEBUG_TOG_ENSQUELCHRESET(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_ENSQUELCHRESET_SHIFT)) & USBPHY_DEBUG_TOG_ENSQUELCHRESET_MASK) +#define USBPHY_DEBUG_TOG_SQUELCHRESETLENGTH_MASK (0x1E000000U) +#define USBPHY_DEBUG_TOG_SQUELCHRESETLENGTH_SHIFT (25U) +#define USBPHY_DEBUG_TOG_SQUELCHRESETLENGTH(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_SQUELCHRESETLENGTH_SHIFT)) & USBPHY_DEBUG_TOG_SQUELCHRESETLENGTH_MASK) +#define USBPHY_DEBUG_TOG_HOST_RESUME_DEBUG_MASK (0x20000000U) +#define USBPHY_DEBUG_TOG_HOST_RESUME_DEBUG_SHIFT (29U) +#define USBPHY_DEBUG_TOG_HOST_RESUME_DEBUG(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_HOST_RESUME_DEBUG_SHIFT)) & USBPHY_DEBUG_TOG_HOST_RESUME_DEBUG_MASK) +#define USBPHY_DEBUG_TOG_CLKGATE_MASK (0x40000000U) +#define USBPHY_DEBUG_TOG_CLKGATE_SHIFT (30U) +#define USBPHY_DEBUG_TOG_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_CLKGATE_SHIFT)) & USBPHY_DEBUG_TOG_CLKGATE_MASK) +#define USBPHY_DEBUG_TOG_RSVD3_MASK (0x80000000U) +#define USBPHY_DEBUG_TOG_RSVD3_SHIFT (31U) +#define USBPHY_DEBUG_TOG_RSVD3(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_RSVD3_SHIFT)) & USBPHY_DEBUG_TOG_RSVD3_MASK) +/*! @} */ + +/*! @name DEBUG0_STATUS - UTMI Debug Status Register 0 */ +/*! @{ */ +#define USBPHY_DEBUG0_STATUS_LOOP_BACK_FAIL_COUNT_MASK (0xFFFFU) +#define USBPHY_DEBUG0_STATUS_LOOP_BACK_FAIL_COUNT_SHIFT (0U) +#define USBPHY_DEBUG0_STATUS_LOOP_BACK_FAIL_COUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_STATUS_LOOP_BACK_FAIL_COUNT_SHIFT)) & USBPHY_DEBUG0_STATUS_LOOP_BACK_FAIL_COUNT_MASK) +#define USBPHY_DEBUG0_STATUS_UTMI_RXERROR_FAIL_COUNT_MASK (0x3FF0000U) +#define USBPHY_DEBUG0_STATUS_UTMI_RXERROR_FAIL_COUNT_SHIFT (16U) +#define USBPHY_DEBUG0_STATUS_UTMI_RXERROR_FAIL_COUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_STATUS_UTMI_RXERROR_FAIL_COUNT_SHIFT)) & USBPHY_DEBUG0_STATUS_UTMI_RXERROR_FAIL_COUNT_MASK) +#define USBPHY_DEBUG0_STATUS_SQUELCH_COUNT_MASK (0xFC000000U) +#define USBPHY_DEBUG0_STATUS_SQUELCH_COUNT_SHIFT (26U) +#define USBPHY_DEBUG0_STATUS_SQUELCH_COUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_STATUS_SQUELCH_COUNT_SHIFT)) & USBPHY_DEBUG0_STATUS_SQUELCH_COUNT_MASK) +/*! @} */ + +/*! @name DEBUG1 - UTMI Debug Status Register 1 */ +/*! @{ */ +#define USBPHY_DEBUG1_RSVD0_MASK (0x1FFFU) +#define USBPHY_DEBUG1_RSVD0_SHIFT (0U) +#define USBPHY_DEBUG1_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_RSVD0_SHIFT)) & USBPHY_DEBUG1_RSVD0_MASK) +#define USBPHY_DEBUG1_ENTAILADJVD_MASK (0x6000U) +#define USBPHY_DEBUG1_ENTAILADJVD_SHIFT (13U) +#define USBPHY_DEBUG1_ENTAILADJVD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_ENTAILADJVD_SHIFT)) & USBPHY_DEBUG1_ENTAILADJVD_MASK) +#define USBPHY_DEBUG1_RSVD1_MASK (0xFFFF8000U) +#define USBPHY_DEBUG1_RSVD1_SHIFT (15U) +#define USBPHY_DEBUG1_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_RSVD1_SHIFT)) & USBPHY_DEBUG1_RSVD1_MASK) +/*! @} */ + +/*! @name DEBUG1_SET - UTMI Debug Status Register 1 */ +/*! @{ */ +#define USBPHY_DEBUG1_SET_RSVD0_MASK (0x1FFFU) +#define USBPHY_DEBUG1_SET_RSVD0_SHIFT (0U) +#define USBPHY_DEBUG1_SET_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_SET_RSVD0_SHIFT)) & USBPHY_DEBUG1_SET_RSVD0_MASK) +#define USBPHY_DEBUG1_SET_ENTAILADJVD_MASK (0x6000U) +#define USBPHY_DEBUG1_SET_ENTAILADJVD_SHIFT (13U) +#define USBPHY_DEBUG1_SET_ENTAILADJVD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_SET_ENTAILADJVD_SHIFT)) & USBPHY_DEBUG1_SET_ENTAILADJVD_MASK) +#define USBPHY_DEBUG1_SET_RSVD1_MASK (0xFFFF8000U) +#define USBPHY_DEBUG1_SET_RSVD1_SHIFT (15U) +#define USBPHY_DEBUG1_SET_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_SET_RSVD1_SHIFT)) & USBPHY_DEBUG1_SET_RSVD1_MASK) +/*! @} */ + +/*! @name DEBUG1_CLR - UTMI Debug Status Register 1 */ +/*! @{ */ +#define USBPHY_DEBUG1_CLR_RSVD0_MASK (0x1FFFU) +#define USBPHY_DEBUG1_CLR_RSVD0_SHIFT (0U) +#define USBPHY_DEBUG1_CLR_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_CLR_RSVD0_SHIFT)) & USBPHY_DEBUG1_CLR_RSVD0_MASK) +#define USBPHY_DEBUG1_CLR_ENTAILADJVD_MASK (0x6000U) +#define USBPHY_DEBUG1_CLR_ENTAILADJVD_SHIFT (13U) +#define USBPHY_DEBUG1_CLR_ENTAILADJVD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_CLR_ENTAILADJVD_SHIFT)) & USBPHY_DEBUG1_CLR_ENTAILADJVD_MASK) +#define USBPHY_DEBUG1_CLR_RSVD1_MASK (0xFFFF8000U) +#define USBPHY_DEBUG1_CLR_RSVD1_SHIFT (15U) +#define USBPHY_DEBUG1_CLR_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_CLR_RSVD1_SHIFT)) & USBPHY_DEBUG1_CLR_RSVD1_MASK) +/*! @} */ + +/*! @name DEBUG1_TOG - UTMI Debug Status Register 1 */ +/*! @{ */ +#define USBPHY_DEBUG1_TOG_RSVD0_MASK (0x1FFFU) +#define USBPHY_DEBUG1_TOG_RSVD0_SHIFT (0U) +#define USBPHY_DEBUG1_TOG_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_TOG_RSVD0_SHIFT)) & USBPHY_DEBUG1_TOG_RSVD0_MASK) +#define USBPHY_DEBUG1_TOG_ENTAILADJVD_MASK (0x6000U) +#define USBPHY_DEBUG1_TOG_ENTAILADJVD_SHIFT (13U) +#define USBPHY_DEBUG1_TOG_ENTAILADJVD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_TOG_ENTAILADJVD_SHIFT)) & USBPHY_DEBUG1_TOG_ENTAILADJVD_MASK) +#define USBPHY_DEBUG1_TOG_RSVD1_MASK (0xFFFF8000U) +#define USBPHY_DEBUG1_TOG_RSVD1_SHIFT (15U) +#define USBPHY_DEBUG1_TOG_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_TOG_RSVD1_SHIFT)) & USBPHY_DEBUG1_TOG_RSVD1_MASK) +/*! @} */ + +/*! @name VERSION - UTMI RTL Version */ +/*! @{ */ +#define USBPHY_VERSION_STEP_MASK (0xFFFFU) +#define USBPHY_VERSION_STEP_SHIFT (0U) +#define USBPHY_VERSION_STEP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_VERSION_STEP_SHIFT)) & USBPHY_VERSION_STEP_MASK) +#define USBPHY_VERSION_MINOR_MASK (0xFF0000U) +#define USBPHY_VERSION_MINOR_SHIFT (16U) +#define USBPHY_VERSION_MINOR(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_VERSION_MINOR_SHIFT)) & USBPHY_VERSION_MINOR_MASK) +#define USBPHY_VERSION_MAJOR_MASK (0xFF000000U) +#define USBPHY_VERSION_MAJOR_SHIFT (24U) +#define USBPHY_VERSION_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_VERSION_MAJOR_SHIFT)) & USBPHY_VERSION_MAJOR_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group USBPHY_Register_Masks */ + + +/* USBPHY - Peripheral instance base addresses */ +/** Peripheral USBPHY1 base address */ +#define USBPHY1_BASE (0x400D9000u) +/** Peripheral USBPHY1 base pointer */ +#define USBPHY1 ((USBPHY_Type *)USBPHY1_BASE) +/** Peripheral USBPHY2 base address */ +#define USBPHY2_BASE (0x400DA000u) +/** Peripheral USBPHY2 base pointer */ +#define USBPHY2 ((USBPHY_Type *)USBPHY2_BASE) +/** Array initializer of USBPHY peripheral base addresses */ +#define USBPHY_BASE_ADDRS { 0u, USBPHY1_BASE, USBPHY2_BASE } +/** Array initializer of USBPHY peripheral base pointers */ +#define USBPHY_BASE_PTRS { (USBPHY_Type *)0u, USBPHY1, USBPHY2 } +/** Interrupt vectors for the USBPHY peripheral type */ +#define USBPHY_IRQS { NotAvail_IRQn, USB_PHY1_IRQn, USB_PHY2_IRQn } +/* Backward compatibility */ +#define USBPHY_CTRL_ENDEVPLUGINDET_MASK USBPHY_CTRL_ENDEVPLUGINDETECT_MASK +#define USBPHY_CTRL_ENDEVPLUGINDET_SHIFT USBPHY_CTRL_ENDEVPLUGINDETECT_SHIFT +#define USBPHY_CTRL_ENDEVPLUGINDET(x) USBPHY_CTRL_ENDEVPLUGINDETECT(x) +#define USBPHY_TX_TXCAL45DM_MASK USBPHY_TX_TXCAL45DN_MASK +#define USBPHY_TX_TXCAL45DM_SHIFT USBPHY_TX_TXCAL45DN_SHIFT +#define USBPHY_TX_TXCAL45DM(x) USBPHY_TX_TXCAL45DN(x) + + +/*! + * @} + */ /* end of group USBPHY_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- USB_ANALOG Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup USB_ANALOG_Peripheral_Access_Layer USB_ANALOG Peripheral Access Layer + * @{ + */ + +/** USB_ANALOG - Register Layout Typedef */ +typedef struct { + uint8_t RESERVED_0[416]; + struct { /* offset: 0x1A0, array step: 0x60 */ + __IO uint32_t VBUS_DETECT; /**< USB VBUS Detect Register, array offset: 0x1A0, array step: 0x60 */ + __IO uint32_t VBUS_DETECT_SET; /**< USB VBUS Detect Register, array offset: 0x1A4, array step: 0x60 */ + __IO uint32_t VBUS_DETECT_CLR; /**< USB VBUS Detect Register, array offset: 0x1A8, array step: 0x60 */ + __IO uint32_t VBUS_DETECT_TOG; /**< USB VBUS Detect Register, array offset: 0x1AC, array step: 0x60 */ + __IO uint32_t CHRG_DETECT; /**< USB Charger Detect Register, array offset: 0x1B0, array step: 0x60 */ + __IO uint32_t CHRG_DETECT_SET; /**< USB Charger Detect Register, array offset: 0x1B4, array step: 0x60 */ + __IO uint32_t CHRG_DETECT_CLR; /**< USB Charger Detect Register, array offset: 0x1B8, array step: 0x60 */ + __IO uint32_t CHRG_DETECT_TOG; /**< USB Charger Detect Register, array offset: 0x1BC, array step: 0x60 */ + __I uint32_t VBUS_DETECT_STAT; /**< USB VBUS Detect Status Register, array offset: 0x1C0, array step: 0x60 */ + uint8_t RESERVED_0[12]; + __I uint32_t CHRG_DETECT_STAT; /**< USB Charger Detect Status Register, array offset: 0x1D0, array step: 0x60 */ + uint8_t RESERVED_1[28]; + __IO uint32_t MISC; /**< USB Misc Register, array offset: 0x1F0, array step: 0x60 */ + __IO uint32_t MISC_SET; /**< USB Misc Register, array offset: 0x1F4, array step: 0x60 */ + __IO uint32_t MISC_CLR; /**< USB Misc Register, array offset: 0x1F8, array step: 0x60 */ + __IO uint32_t MISC_TOG; /**< USB Misc Register, array offset: 0x1FC, array step: 0x60 */ + } INSTANCE[2]; + __I uint32_t DIGPROG; /**< Chip Silicon Version, offset: 0x260 */ +} USB_ANALOG_Type; + +/* ---------------------------------------------------------------------------- + -- USB_ANALOG Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup USB_ANALOG_Register_Masks USB_ANALOG Register Masks + * @{ + */ + +/*! @name VBUS_DETECT - USB VBUS Detect Register */ +/*! @{ */ +#define USB_ANALOG_VBUS_DETECT_VBUSVALID_THRESH_MASK (0x7U) +#define USB_ANALOG_VBUS_DETECT_VBUSVALID_THRESH_SHIFT (0U) +/*! VBUSVALID_THRESH + * 0b000..4.0V + * 0b001..4.1V + * 0b010..4.2V + * 0b011..4.3V + * 0b100..4.4V (default) + * 0b101..4.5V + * 0b110..4.6V + * 0b111..4.7V + */ +#define USB_ANALOG_VBUS_DETECT_VBUSVALID_THRESH(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_VBUS_DETECT_VBUSVALID_THRESH_SHIFT)) & USB_ANALOG_VBUS_DETECT_VBUSVALID_THRESH_MASK) +#define USB_ANALOG_VBUS_DETECT_VBUSVALID_PWRUP_CMPS_MASK (0x100000U) +#define USB_ANALOG_VBUS_DETECT_VBUSVALID_PWRUP_CMPS_SHIFT (20U) +#define USB_ANALOG_VBUS_DETECT_VBUSVALID_PWRUP_CMPS(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_VBUS_DETECT_VBUSVALID_PWRUP_CMPS_SHIFT)) & USB_ANALOG_VBUS_DETECT_VBUSVALID_PWRUP_CMPS_MASK) +#define USB_ANALOG_VBUS_DETECT_DISCHARGE_VBUS_MASK (0x4000000U) +#define USB_ANALOG_VBUS_DETECT_DISCHARGE_VBUS_SHIFT (26U) +#define USB_ANALOG_VBUS_DETECT_DISCHARGE_VBUS(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_VBUS_DETECT_DISCHARGE_VBUS_SHIFT)) & USB_ANALOG_VBUS_DETECT_DISCHARGE_VBUS_MASK) +#define USB_ANALOG_VBUS_DETECT_CHARGE_VBUS_MASK (0x8000000U) +#define USB_ANALOG_VBUS_DETECT_CHARGE_VBUS_SHIFT (27U) +#define USB_ANALOG_VBUS_DETECT_CHARGE_VBUS(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_VBUS_DETECT_CHARGE_VBUS_SHIFT)) & USB_ANALOG_VBUS_DETECT_CHARGE_VBUS_MASK) +/*! @} */ + +/* The count of USB_ANALOG_VBUS_DETECT */ +#define USB_ANALOG_VBUS_DETECT_COUNT (2U) + +/*! @name VBUS_DETECT_SET - USB VBUS Detect Register */ +/*! @{ */ +#define USB_ANALOG_VBUS_DETECT_SET_VBUSVALID_THRESH_MASK (0x7U) +#define USB_ANALOG_VBUS_DETECT_SET_VBUSVALID_THRESH_SHIFT (0U) +/*! VBUSVALID_THRESH + * 0b000..4.0V + * 0b001..4.1V + * 0b010..4.2V + * 0b011..4.3V + * 0b100..4.4V (default) + * 0b101..4.5V + * 0b110..4.6V + * 0b111..4.7V + */ +#define USB_ANALOG_VBUS_DETECT_SET_VBUSVALID_THRESH(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_VBUS_DETECT_SET_VBUSVALID_THRESH_SHIFT)) & USB_ANALOG_VBUS_DETECT_SET_VBUSVALID_THRESH_MASK) +#define USB_ANALOG_VBUS_DETECT_SET_VBUSVALID_PWRUP_CMPS_MASK (0x100000U) +#define USB_ANALOG_VBUS_DETECT_SET_VBUSVALID_PWRUP_CMPS_SHIFT (20U) +#define USB_ANALOG_VBUS_DETECT_SET_VBUSVALID_PWRUP_CMPS(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_VBUS_DETECT_SET_VBUSVALID_PWRUP_CMPS_SHIFT)) & USB_ANALOG_VBUS_DETECT_SET_VBUSVALID_PWRUP_CMPS_MASK) +#define USB_ANALOG_VBUS_DETECT_SET_DISCHARGE_VBUS_MASK (0x4000000U) +#define USB_ANALOG_VBUS_DETECT_SET_DISCHARGE_VBUS_SHIFT (26U) +#define USB_ANALOG_VBUS_DETECT_SET_DISCHARGE_VBUS(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_VBUS_DETECT_SET_DISCHARGE_VBUS_SHIFT)) & USB_ANALOG_VBUS_DETECT_SET_DISCHARGE_VBUS_MASK) +#define USB_ANALOG_VBUS_DETECT_SET_CHARGE_VBUS_MASK (0x8000000U) +#define USB_ANALOG_VBUS_DETECT_SET_CHARGE_VBUS_SHIFT (27U) +#define USB_ANALOG_VBUS_DETECT_SET_CHARGE_VBUS(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_VBUS_DETECT_SET_CHARGE_VBUS_SHIFT)) & USB_ANALOG_VBUS_DETECT_SET_CHARGE_VBUS_MASK) +/*! @} */ + +/* The count of USB_ANALOG_VBUS_DETECT_SET */ +#define USB_ANALOG_VBUS_DETECT_SET_COUNT (2U) + +/*! @name VBUS_DETECT_CLR - USB VBUS Detect Register */ +/*! @{ */ +#define USB_ANALOG_VBUS_DETECT_CLR_VBUSVALID_THRESH_MASK (0x7U) +#define USB_ANALOG_VBUS_DETECT_CLR_VBUSVALID_THRESH_SHIFT (0U) +/*! VBUSVALID_THRESH + * 0b000..4.0V + * 0b001..4.1V + * 0b010..4.2V + * 0b011..4.3V + * 0b100..4.4V (default) + * 0b101..4.5V + * 0b110..4.6V + * 0b111..4.7V + */ +#define USB_ANALOG_VBUS_DETECT_CLR_VBUSVALID_THRESH(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_VBUS_DETECT_CLR_VBUSVALID_THRESH_SHIFT)) & USB_ANALOG_VBUS_DETECT_CLR_VBUSVALID_THRESH_MASK) +#define USB_ANALOG_VBUS_DETECT_CLR_VBUSVALID_PWRUP_CMPS_MASK (0x100000U) +#define USB_ANALOG_VBUS_DETECT_CLR_VBUSVALID_PWRUP_CMPS_SHIFT (20U) +#define USB_ANALOG_VBUS_DETECT_CLR_VBUSVALID_PWRUP_CMPS(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_VBUS_DETECT_CLR_VBUSVALID_PWRUP_CMPS_SHIFT)) & USB_ANALOG_VBUS_DETECT_CLR_VBUSVALID_PWRUP_CMPS_MASK) +#define USB_ANALOG_VBUS_DETECT_CLR_DISCHARGE_VBUS_MASK (0x4000000U) +#define USB_ANALOG_VBUS_DETECT_CLR_DISCHARGE_VBUS_SHIFT (26U) +#define USB_ANALOG_VBUS_DETECT_CLR_DISCHARGE_VBUS(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_VBUS_DETECT_CLR_DISCHARGE_VBUS_SHIFT)) & USB_ANALOG_VBUS_DETECT_CLR_DISCHARGE_VBUS_MASK) +#define USB_ANALOG_VBUS_DETECT_CLR_CHARGE_VBUS_MASK (0x8000000U) +#define USB_ANALOG_VBUS_DETECT_CLR_CHARGE_VBUS_SHIFT (27U) +#define USB_ANALOG_VBUS_DETECT_CLR_CHARGE_VBUS(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_VBUS_DETECT_CLR_CHARGE_VBUS_SHIFT)) & USB_ANALOG_VBUS_DETECT_CLR_CHARGE_VBUS_MASK) +/*! @} */ + +/* The count of USB_ANALOG_VBUS_DETECT_CLR */ +#define USB_ANALOG_VBUS_DETECT_CLR_COUNT (2U) + +/*! @name VBUS_DETECT_TOG - USB VBUS Detect Register */ +/*! @{ */ +#define USB_ANALOG_VBUS_DETECT_TOG_VBUSVALID_THRESH_MASK (0x7U) +#define USB_ANALOG_VBUS_DETECT_TOG_VBUSVALID_THRESH_SHIFT (0U) +/*! VBUSVALID_THRESH + * 0b000..4.0V + * 0b001..4.1V + * 0b010..4.2V + * 0b011..4.3V + * 0b100..4.4V (default) + * 0b101..4.5V + * 0b110..4.6V + * 0b111..4.7V + */ +#define USB_ANALOG_VBUS_DETECT_TOG_VBUSVALID_THRESH(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_VBUS_DETECT_TOG_VBUSVALID_THRESH_SHIFT)) & USB_ANALOG_VBUS_DETECT_TOG_VBUSVALID_THRESH_MASK) +#define USB_ANALOG_VBUS_DETECT_TOG_VBUSVALID_PWRUP_CMPS_MASK (0x100000U) +#define USB_ANALOG_VBUS_DETECT_TOG_VBUSVALID_PWRUP_CMPS_SHIFT (20U) +#define USB_ANALOG_VBUS_DETECT_TOG_VBUSVALID_PWRUP_CMPS(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_VBUS_DETECT_TOG_VBUSVALID_PWRUP_CMPS_SHIFT)) & USB_ANALOG_VBUS_DETECT_TOG_VBUSVALID_PWRUP_CMPS_MASK) +#define USB_ANALOG_VBUS_DETECT_TOG_DISCHARGE_VBUS_MASK (0x4000000U) +#define USB_ANALOG_VBUS_DETECT_TOG_DISCHARGE_VBUS_SHIFT (26U) +#define USB_ANALOG_VBUS_DETECT_TOG_DISCHARGE_VBUS(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_VBUS_DETECT_TOG_DISCHARGE_VBUS_SHIFT)) & USB_ANALOG_VBUS_DETECT_TOG_DISCHARGE_VBUS_MASK) +#define USB_ANALOG_VBUS_DETECT_TOG_CHARGE_VBUS_MASK (0x8000000U) +#define USB_ANALOG_VBUS_DETECT_TOG_CHARGE_VBUS_SHIFT (27U) +#define USB_ANALOG_VBUS_DETECT_TOG_CHARGE_VBUS(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_VBUS_DETECT_TOG_CHARGE_VBUS_SHIFT)) & USB_ANALOG_VBUS_DETECT_TOG_CHARGE_VBUS_MASK) +/*! @} */ + +/* The count of USB_ANALOG_VBUS_DETECT_TOG */ +#define USB_ANALOG_VBUS_DETECT_TOG_COUNT (2U) + +/*! @name CHRG_DETECT - USB Charger Detect Register */ +/*! @{ */ +#define USB_ANALOG_CHRG_DETECT_CHK_CONTACT_MASK (0x40000U) +#define USB_ANALOG_CHRG_DETECT_CHK_CONTACT_SHIFT (18U) +/*! CHK_CONTACT - Check the contact of USB plug + * 0b0..Do not check the contact of USB plug. + * 0b1..Check whether the USB plug has been in contact with each other + */ +#define USB_ANALOG_CHRG_DETECT_CHK_CONTACT(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_CHRG_DETECT_CHK_CONTACT_SHIFT)) & USB_ANALOG_CHRG_DETECT_CHK_CONTACT_MASK) +#define USB_ANALOG_CHRG_DETECT_CHK_CHRG_B_MASK (0x80000U) +#define USB_ANALOG_CHRG_DETECT_CHK_CHRG_B_SHIFT (19U) +/*! CHK_CHRG_B - Check the charger connection + * 0b0..Check whether a charger (either a dedicated charger or a host charger) is connected to USB port. + * 0b1..Do not check whether a charger is connected to the USB port. + */ +#define USB_ANALOG_CHRG_DETECT_CHK_CHRG_B(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_CHRG_DETECT_CHK_CHRG_B_SHIFT)) & USB_ANALOG_CHRG_DETECT_CHK_CHRG_B_MASK) +#define USB_ANALOG_CHRG_DETECT_EN_B_MASK (0x100000U) +#define USB_ANALOG_CHRG_DETECT_EN_B_SHIFT (20U) +/*! EN_B + * 0b0..Enable the charger detector. + * 0b1..Disable the charger detector. + */ +#define USB_ANALOG_CHRG_DETECT_EN_B(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_CHRG_DETECT_EN_B_SHIFT)) & USB_ANALOG_CHRG_DETECT_EN_B_MASK) +/*! @} */ + +/* The count of USB_ANALOG_CHRG_DETECT */ +#define USB_ANALOG_CHRG_DETECT_COUNT (2U) + +/*! @name CHRG_DETECT_SET - USB Charger Detect Register */ +/*! @{ */ +#define USB_ANALOG_CHRG_DETECT_SET_CHK_CONTACT_MASK (0x40000U) +#define USB_ANALOG_CHRG_DETECT_SET_CHK_CONTACT_SHIFT (18U) +/*! CHK_CONTACT - Check the contact of USB plug + * 0b0..Do not check the contact of USB plug. + * 0b1..Check whether the USB plug has been in contact with each other + */ +#define USB_ANALOG_CHRG_DETECT_SET_CHK_CONTACT(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_CHRG_DETECT_SET_CHK_CONTACT_SHIFT)) & USB_ANALOG_CHRG_DETECT_SET_CHK_CONTACT_MASK) +#define USB_ANALOG_CHRG_DETECT_SET_CHK_CHRG_B_MASK (0x80000U) +#define USB_ANALOG_CHRG_DETECT_SET_CHK_CHRG_B_SHIFT (19U) +/*! CHK_CHRG_B - Check the charger connection + * 0b0..Check whether a charger (either a dedicated charger or a host charger) is connected to USB port. + * 0b1..Do not check whether a charger is connected to the USB port. + */ +#define USB_ANALOG_CHRG_DETECT_SET_CHK_CHRG_B(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_CHRG_DETECT_SET_CHK_CHRG_B_SHIFT)) & USB_ANALOG_CHRG_DETECT_SET_CHK_CHRG_B_MASK) +#define USB_ANALOG_CHRG_DETECT_SET_EN_B_MASK (0x100000U) +#define USB_ANALOG_CHRG_DETECT_SET_EN_B_SHIFT (20U) +/*! EN_B + * 0b0..Enable the charger detector. + * 0b1..Disable the charger detector. + */ +#define USB_ANALOG_CHRG_DETECT_SET_EN_B(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_CHRG_DETECT_SET_EN_B_SHIFT)) & USB_ANALOG_CHRG_DETECT_SET_EN_B_MASK) +/*! @} */ + +/* The count of USB_ANALOG_CHRG_DETECT_SET */ +#define USB_ANALOG_CHRG_DETECT_SET_COUNT (2U) + +/*! @name CHRG_DETECT_CLR - USB Charger Detect Register */ +/*! @{ */ +#define USB_ANALOG_CHRG_DETECT_CLR_CHK_CONTACT_MASK (0x40000U) +#define USB_ANALOG_CHRG_DETECT_CLR_CHK_CONTACT_SHIFT (18U) +/*! CHK_CONTACT - Check the contact of USB plug + * 0b0..Do not check the contact of USB plug. + * 0b1..Check whether the USB plug has been in contact with each other + */ +#define USB_ANALOG_CHRG_DETECT_CLR_CHK_CONTACT(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_CHRG_DETECT_CLR_CHK_CONTACT_SHIFT)) & USB_ANALOG_CHRG_DETECT_CLR_CHK_CONTACT_MASK) +#define USB_ANALOG_CHRG_DETECT_CLR_CHK_CHRG_B_MASK (0x80000U) +#define USB_ANALOG_CHRG_DETECT_CLR_CHK_CHRG_B_SHIFT (19U) +/*! CHK_CHRG_B - Check the charger connection + * 0b0..Check whether a charger (either a dedicated charger or a host charger) is connected to USB port. + * 0b1..Do not check whether a charger is connected to the USB port. + */ +#define USB_ANALOG_CHRG_DETECT_CLR_CHK_CHRG_B(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_CHRG_DETECT_CLR_CHK_CHRG_B_SHIFT)) & USB_ANALOG_CHRG_DETECT_CLR_CHK_CHRG_B_MASK) +#define USB_ANALOG_CHRG_DETECT_CLR_EN_B_MASK (0x100000U) +#define USB_ANALOG_CHRG_DETECT_CLR_EN_B_SHIFT (20U) +/*! EN_B + * 0b0..Enable the charger detector. + * 0b1..Disable the charger detector. + */ +#define USB_ANALOG_CHRG_DETECT_CLR_EN_B(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_CHRG_DETECT_CLR_EN_B_SHIFT)) & USB_ANALOG_CHRG_DETECT_CLR_EN_B_MASK) +/*! @} */ + +/* The count of USB_ANALOG_CHRG_DETECT_CLR */ +#define USB_ANALOG_CHRG_DETECT_CLR_COUNT (2U) + +/*! @name CHRG_DETECT_TOG - USB Charger Detect Register */ +/*! @{ */ +#define USB_ANALOG_CHRG_DETECT_TOG_CHK_CONTACT_MASK (0x40000U) +#define USB_ANALOG_CHRG_DETECT_TOG_CHK_CONTACT_SHIFT (18U) +/*! CHK_CONTACT - Check the contact of USB plug + * 0b0..Do not check the contact of USB plug. + * 0b1..Check whether the USB plug has been in contact with each other + */ +#define USB_ANALOG_CHRG_DETECT_TOG_CHK_CONTACT(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_CHRG_DETECT_TOG_CHK_CONTACT_SHIFT)) & USB_ANALOG_CHRG_DETECT_TOG_CHK_CONTACT_MASK) +#define USB_ANALOG_CHRG_DETECT_TOG_CHK_CHRG_B_MASK (0x80000U) +#define USB_ANALOG_CHRG_DETECT_TOG_CHK_CHRG_B_SHIFT (19U) +/*! CHK_CHRG_B - Check the charger connection + * 0b0..Check whether a charger (either a dedicated charger or a host charger) is connected to USB port. + * 0b1..Do not check whether a charger is connected to the USB port. + */ +#define USB_ANALOG_CHRG_DETECT_TOG_CHK_CHRG_B(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_CHRG_DETECT_TOG_CHK_CHRG_B_SHIFT)) & USB_ANALOG_CHRG_DETECT_TOG_CHK_CHRG_B_MASK) +#define USB_ANALOG_CHRG_DETECT_TOG_EN_B_MASK (0x100000U) +#define USB_ANALOG_CHRG_DETECT_TOG_EN_B_SHIFT (20U) +/*! EN_B + * 0b0..Enable the charger detector. + * 0b1..Disable the charger detector. + */ +#define USB_ANALOG_CHRG_DETECT_TOG_EN_B(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_CHRG_DETECT_TOG_EN_B_SHIFT)) & USB_ANALOG_CHRG_DETECT_TOG_EN_B_MASK) +/*! @} */ + +/* The count of USB_ANALOG_CHRG_DETECT_TOG */ +#define USB_ANALOG_CHRG_DETECT_TOG_COUNT (2U) + +/*! @name VBUS_DETECT_STAT - USB VBUS Detect Status Register */ +/*! @{ */ +#define USB_ANALOG_VBUS_DETECT_STAT_SESSEND_MASK (0x1U) +#define USB_ANALOG_VBUS_DETECT_STAT_SESSEND_SHIFT (0U) +#define USB_ANALOG_VBUS_DETECT_STAT_SESSEND(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_VBUS_DETECT_STAT_SESSEND_SHIFT)) & USB_ANALOG_VBUS_DETECT_STAT_SESSEND_MASK) +#define USB_ANALOG_VBUS_DETECT_STAT_BVALID_MASK (0x2U) +#define USB_ANALOG_VBUS_DETECT_STAT_BVALID_SHIFT (1U) +#define USB_ANALOG_VBUS_DETECT_STAT_BVALID(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_VBUS_DETECT_STAT_BVALID_SHIFT)) & USB_ANALOG_VBUS_DETECT_STAT_BVALID_MASK) +#define USB_ANALOG_VBUS_DETECT_STAT_AVALID_MASK (0x4U) +#define USB_ANALOG_VBUS_DETECT_STAT_AVALID_SHIFT (2U) +#define USB_ANALOG_VBUS_DETECT_STAT_AVALID(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_VBUS_DETECT_STAT_AVALID_SHIFT)) & USB_ANALOG_VBUS_DETECT_STAT_AVALID_MASK) +#define USB_ANALOG_VBUS_DETECT_STAT_VBUS_VALID_MASK (0x8U) +#define USB_ANALOG_VBUS_DETECT_STAT_VBUS_VALID_SHIFT (3U) +#define USB_ANALOG_VBUS_DETECT_STAT_VBUS_VALID(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_VBUS_DETECT_STAT_VBUS_VALID_SHIFT)) & USB_ANALOG_VBUS_DETECT_STAT_VBUS_VALID_MASK) +/*! @} */ + +/* The count of USB_ANALOG_VBUS_DETECT_STAT */ +#define USB_ANALOG_VBUS_DETECT_STAT_COUNT (2U) + +/*! @name CHRG_DETECT_STAT - USB Charger Detect Status Register */ +/*! @{ */ +#define USB_ANALOG_CHRG_DETECT_STAT_PLUG_CONTACT_MASK (0x1U) +#define USB_ANALOG_CHRG_DETECT_STAT_PLUG_CONTACT_SHIFT (0U) +/*! PLUG_CONTACT + * 0b0..The USB plug has not made contact. + * 0b1..The USB plug has made good contact. + */ +#define USB_ANALOG_CHRG_DETECT_STAT_PLUG_CONTACT(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_CHRG_DETECT_STAT_PLUG_CONTACT_SHIFT)) & USB_ANALOG_CHRG_DETECT_STAT_PLUG_CONTACT_MASK) +#define USB_ANALOG_CHRG_DETECT_STAT_CHRG_DETECTED_MASK (0x2U) +#define USB_ANALOG_CHRG_DETECT_STAT_CHRG_DETECTED_SHIFT (1U) +/*! CHRG_DETECTED + * 0b0..The USB port is not connected to a charger. + * 0b1..A charger (either a dedicated charger or a host charger) is connected to the USB port. + */ +#define USB_ANALOG_CHRG_DETECT_STAT_CHRG_DETECTED(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_CHRG_DETECT_STAT_CHRG_DETECTED_SHIFT)) & USB_ANALOG_CHRG_DETECT_STAT_CHRG_DETECTED_MASK) +#define USB_ANALOG_CHRG_DETECT_STAT_DM_STATE_MASK (0x4U) +#define USB_ANALOG_CHRG_DETECT_STAT_DM_STATE_SHIFT (2U) +#define USB_ANALOG_CHRG_DETECT_STAT_DM_STATE(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_CHRG_DETECT_STAT_DM_STATE_SHIFT)) & USB_ANALOG_CHRG_DETECT_STAT_DM_STATE_MASK) +#define USB_ANALOG_CHRG_DETECT_STAT_DP_STATE_MASK (0x8U) +#define USB_ANALOG_CHRG_DETECT_STAT_DP_STATE_SHIFT (3U) +#define USB_ANALOG_CHRG_DETECT_STAT_DP_STATE(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_CHRG_DETECT_STAT_DP_STATE_SHIFT)) & USB_ANALOG_CHRG_DETECT_STAT_DP_STATE_MASK) +/*! @} */ + +/* The count of USB_ANALOG_CHRG_DETECT_STAT */ +#define USB_ANALOG_CHRG_DETECT_STAT_COUNT (2U) + +/*! @name MISC - USB Misc Register */ +/*! @{ */ +#define USB_ANALOG_MISC_HS_USE_EXTERNAL_R_MASK (0x1U) +#define USB_ANALOG_MISC_HS_USE_EXTERNAL_R_SHIFT (0U) +#define USB_ANALOG_MISC_HS_USE_EXTERNAL_R(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_MISC_HS_USE_EXTERNAL_R_SHIFT)) & USB_ANALOG_MISC_HS_USE_EXTERNAL_R_MASK) +#define USB_ANALOG_MISC_EN_DEGLITCH_MASK (0x2U) +#define USB_ANALOG_MISC_EN_DEGLITCH_SHIFT (1U) +#define USB_ANALOG_MISC_EN_DEGLITCH(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_MISC_EN_DEGLITCH_SHIFT)) & USB_ANALOG_MISC_EN_DEGLITCH_MASK) +#define USB_ANALOG_MISC_EN_CLK_UTMI_MASK (0x40000000U) +#define USB_ANALOG_MISC_EN_CLK_UTMI_SHIFT (30U) +#define USB_ANALOG_MISC_EN_CLK_UTMI(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_MISC_EN_CLK_UTMI_SHIFT)) & USB_ANALOG_MISC_EN_CLK_UTMI_MASK) +/*! @} */ + +/* The count of USB_ANALOG_MISC */ +#define USB_ANALOG_MISC_COUNT (2U) + +/*! @name MISC_SET - USB Misc Register */ +/*! @{ */ +#define USB_ANALOG_MISC_SET_HS_USE_EXTERNAL_R_MASK (0x1U) +#define USB_ANALOG_MISC_SET_HS_USE_EXTERNAL_R_SHIFT (0U) +#define USB_ANALOG_MISC_SET_HS_USE_EXTERNAL_R(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_MISC_SET_HS_USE_EXTERNAL_R_SHIFT)) & USB_ANALOG_MISC_SET_HS_USE_EXTERNAL_R_MASK) +#define USB_ANALOG_MISC_SET_EN_DEGLITCH_MASK (0x2U) +#define USB_ANALOG_MISC_SET_EN_DEGLITCH_SHIFT (1U) +#define USB_ANALOG_MISC_SET_EN_DEGLITCH(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_MISC_SET_EN_DEGLITCH_SHIFT)) & USB_ANALOG_MISC_SET_EN_DEGLITCH_MASK) +#define USB_ANALOG_MISC_SET_EN_CLK_UTMI_MASK (0x40000000U) +#define USB_ANALOG_MISC_SET_EN_CLK_UTMI_SHIFT (30U) +#define USB_ANALOG_MISC_SET_EN_CLK_UTMI(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_MISC_SET_EN_CLK_UTMI_SHIFT)) & USB_ANALOG_MISC_SET_EN_CLK_UTMI_MASK) +/*! @} */ + +/* The count of USB_ANALOG_MISC_SET */ +#define USB_ANALOG_MISC_SET_COUNT (2U) + +/*! @name MISC_CLR - USB Misc Register */ +/*! @{ */ +#define USB_ANALOG_MISC_CLR_HS_USE_EXTERNAL_R_MASK (0x1U) +#define USB_ANALOG_MISC_CLR_HS_USE_EXTERNAL_R_SHIFT (0U) +#define USB_ANALOG_MISC_CLR_HS_USE_EXTERNAL_R(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_MISC_CLR_HS_USE_EXTERNAL_R_SHIFT)) & USB_ANALOG_MISC_CLR_HS_USE_EXTERNAL_R_MASK) +#define USB_ANALOG_MISC_CLR_EN_DEGLITCH_MASK (0x2U) +#define USB_ANALOG_MISC_CLR_EN_DEGLITCH_SHIFT (1U) +#define USB_ANALOG_MISC_CLR_EN_DEGLITCH(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_MISC_CLR_EN_DEGLITCH_SHIFT)) & USB_ANALOG_MISC_CLR_EN_DEGLITCH_MASK) +#define USB_ANALOG_MISC_CLR_EN_CLK_UTMI_MASK (0x40000000U) +#define USB_ANALOG_MISC_CLR_EN_CLK_UTMI_SHIFT (30U) +#define USB_ANALOG_MISC_CLR_EN_CLK_UTMI(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_MISC_CLR_EN_CLK_UTMI_SHIFT)) & USB_ANALOG_MISC_CLR_EN_CLK_UTMI_MASK) +/*! @} */ + +/* The count of USB_ANALOG_MISC_CLR */ +#define USB_ANALOG_MISC_CLR_COUNT (2U) + +/*! @name MISC_TOG - USB Misc Register */ +/*! @{ */ +#define USB_ANALOG_MISC_TOG_HS_USE_EXTERNAL_R_MASK (0x1U) +#define USB_ANALOG_MISC_TOG_HS_USE_EXTERNAL_R_SHIFT (0U) +#define USB_ANALOG_MISC_TOG_HS_USE_EXTERNAL_R(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_MISC_TOG_HS_USE_EXTERNAL_R_SHIFT)) & USB_ANALOG_MISC_TOG_HS_USE_EXTERNAL_R_MASK) +#define USB_ANALOG_MISC_TOG_EN_DEGLITCH_MASK (0x2U) +#define USB_ANALOG_MISC_TOG_EN_DEGLITCH_SHIFT (1U) +#define USB_ANALOG_MISC_TOG_EN_DEGLITCH(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_MISC_TOG_EN_DEGLITCH_SHIFT)) & USB_ANALOG_MISC_TOG_EN_DEGLITCH_MASK) +#define USB_ANALOG_MISC_TOG_EN_CLK_UTMI_MASK (0x40000000U) +#define USB_ANALOG_MISC_TOG_EN_CLK_UTMI_SHIFT (30U) +#define USB_ANALOG_MISC_TOG_EN_CLK_UTMI(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_MISC_TOG_EN_CLK_UTMI_SHIFT)) & USB_ANALOG_MISC_TOG_EN_CLK_UTMI_MASK) +/*! @} */ + +/* The count of USB_ANALOG_MISC_TOG */ +#define USB_ANALOG_MISC_TOG_COUNT (2U) + +/*! @name DIGPROG - Chip Silicon Version */ +/*! @{ */ +#define USB_ANALOG_DIGPROG_SILICON_REVISION_MASK (0xFFFFFFFFU) +#define USB_ANALOG_DIGPROG_SILICON_REVISION_SHIFT (0U) +/*! SILICON_REVISION + * 0b00000000011010100000000000000001..Silicon revision 1.1 + */ +#define USB_ANALOG_DIGPROG_SILICON_REVISION(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_DIGPROG_SILICON_REVISION_SHIFT)) & USB_ANALOG_DIGPROG_SILICON_REVISION_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group USB_ANALOG_Register_Masks */ + + +/* USB_ANALOG - Peripheral instance base addresses */ +/** Peripheral USB_ANALOG base address */ +#define USB_ANALOG_BASE (0x400D8000u) +/** Peripheral USB_ANALOG base pointer */ +#define USB_ANALOG ((USB_ANALOG_Type *)USB_ANALOG_BASE) +/** Array initializer of USB_ANALOG peripheral base addresses */ +#define USB_ANALOG_BASE_ADDRS { USB_ANALOG_BASE } +/** Array initializer of USB_ANALOG peripheral base pointers */ +#define USB_ANALOG_BASE_PTRS { USB_ANALOG } + +/*! + * @} + */ /* end of group USB_ANALOG_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- USDHC Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup USDHC_Peripheral_Access_Layer USDHC Peripheral Access Layer + * @{ + */ + +/** USDHC - Register Layout Typedef */ +typedef struct { + __IO uint32_t DS_ADDR; /**< DMA System Address, offset: 0x0 */ + __IO uint32_t BLK_ATT; /**< Block Attributes, offset: 0x4 */ + __IO uint32_t CMD_ARG; /**< Command Argument, offset: 0x8 */ + __IO uint32_t CMD_XFR_TYP; /**< Command Transfer Type, offset: 0xC */ + __I uint32_t CMD_RSP0; /**< Command Response0, offset: 0x10 */ + __I uint32_t CMD_RSP1; /**< Command Response1, offset: 0x14 */ + __I uint32_t CMD_RSP2; /**< Command Response2, offset: 0x18 */ + __I uint32_t CMD_RSP3; /**< Command Response3, offset: 0x1C */ + __IO uint32_t DATA_BUFF_ACC_PORT; /**< Data Buffer Access Port, offset: 0x20 */ + __I uint32_t PRES_STATE; /**< Present State, offset: 0x24 */ + __IO uint32_t PROT_CTRL; /**< Protocol Control, offset: 0x28 */ + __IO uint32_t SYS_CTRL; /**< System Control, offset: 0x2C */ + __IO uint32_t INT_STATUS; /**< Interrupt Status, offset: 0x30 */ + __IO uint32_t INT_STATUS_EN; /**< Interrupt Status Enable, offset: 0x34 */ + __IO uint32_t INT_SIGNAL_EN; /**< Interrupt Signal Enable, offset: 0x38 */ + __IO uint32_t AUTOCMD12_ERR_STATUS; /**< Auto CMD12 Error Status, offset: 0x3C */ + __IO uint32_t HOST_CTRL_CAP; /**< Host Controller Capabilities, offset: 0x40 */ + __IO uint32_t WTMK_LVL; /**< Watermark Level, offset: 0x44 */ + __IO uint32_t MIX_CTRL; /**< Mixer Control, offset: 0x48 */ + uint8_t RESERVED_0[4]; + __O uint32_t FORCE_EVENT; /**< Force Event, offset: 0x50 */ + __I uint32_t ADMA_ERR_STATUS; /**< ADMA Error Status Register, offset: 0x54 */ + __IO uint32_t ADMA_SYS_ADDR; /**< ADMA System Address, offset: 0x58 */ + uint8_t RESERVED_1[4]; + __IO uint32_t DLL_CTRL; /**< DLL (Delay Line) Control, offset: 0x60 */ + __I uint32_t DLL_STATUS; /**< DLL Status, offset: 0x64 */ + __IO uint32_t CLK_TUNE_CTRL_STATUS; /**< CLK Tuning Control and Status, offset: 0x68 */ + uint8_t RESERVED_2[84]; + __IO uint32_t VEND_SPEC; /**< Vendor Specific Register, offset: 0xC0 */ + __IO uint32_t MMC_BOOT; /**< MMC Boot Register, offset: 0xC4 */ + __IO uint32_t VEND_SPEC2; /**< Vendor Specific 2 Register, offset: 0xC8 */ + __IO uint32_t TUNING_CTRL; /**< Tuning Control Register, offset: 0xCC */ +} USDHC_Type; + +/* ---------------------------------------------------------------------------- + -- USDHC Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup USDHC_Register_Masks USDHC Register Masks + * @{ + */ + +/*! @name DS_ADDR - DMA System Address */ +/*! @{ */ +#define USDHC_DS_ADDR_DS_ADDR_MASK (0xFFFFFFFFU) +#define USDHC_DS_ADDR_DS_ADDR_SHIFT (0U) +#define USDHC_DS_ADDR_DS_ADDR(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DS_ADDR_DS_ADDR_SHIFT)) & USDHC_DS_ADDR_DS_ADDR_MASK) +/*! @} */ + +/*! @name BLK_ATT - Block Attributes */ +/*! @{ */ +#define USDHC_BLK_ATT_BLKSIZE_MASK (0x1FFFU) +#define USDHC_BLK_ATT_BLKSIZE_SHIFT (0U) +/*! BLKSIZE - Block Size + * 0b1000000000000..4096 Bytes + * 0b0100000000000..2048 Bytes + * 0b0001000000000..512 Bytes + * 0b0000111111111..511 Bytes + * 0b0000000000100..4 Bytes + * 0b0000000000011..3 Bytes + * 0b0000000000010..2 Bytes + * 0b0000000000001..1 Byte + * 0b0000000000000..No data transfer + */ +#define USDHC_BLK_ATT_BLKSIZE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_BLK_ATT_BLKSIZE_SHIFT)) & USDHC_BLK_ATT_BLKSIZE_MASK) +#define USDHC_BLK_ATT_BLKCNT_MASK (0xFFFF0000U) +#define USDHC_BLK_ATT_BLKCNT_SHIFT (16U) +/*! BLKCNT - Block Count + * 0b1111111111111111..65535 blocks + * 0b0000000000000010..2 blocks + * 0b0000000000000001..1 block + * 0b0000000000000000..Stop Count + */ +#define USDHC_BLK_ATT_BLKCNT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_BLK_ATT_BLKCNT_SHIFT)) & USDHC_BLK_ATT_BLKCNT_MASK) +/*! @} */ + +/*! @name CMD_ARG - Command Argument */ +/*! @{ */ +#define USDHC_CMD_ARG_CMDARG_MASK (0xFFFFFFFFU) +#define USDHC_CMD_ARG_CMDARG_SHIFT (0U) +#define USDHC_CMD_ARG_CMDARG(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_ARG_CMDARG_SHIFT)) & USDHC_CMD_ARG_CMDARG_MASK) +/*! @} */ + +/*! @name CMD_XFR_TYP - Command Transfer Type */ +/*! @{ */ +#define USDHC_CMD_XFR_TYP_RSPTYP_MASK (0x30000U) +#define USDHC_CMD_XFR_TYP_RSPTYP_SHIFT (16U) +/*! RSPTYP - Response Type Select + * 0b00..No Response + * 0b01..Response Length 136 + * 0b10..Response Length 48 + * 0b11..Response Length 48, check Busy after response + */ +#define USDHC_CMD_XFR_TYP_RSPTYP(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_XFR_TYP_RSPTYP_SHIFT)) & USDHC_CMD_XFR_TYP_RSPTYP_MASK) +#define USDHC_CMD_XFR_TYP_CCCEN_MASK (0x80000U) +#define USDHC_CMD_XFR_TYP_CCCEN_SHIFT (19U) +/*! CCCEN - Command CRC Check Enable + * 0b1..Enable + * 0b0..Disable + */ +#define USDHC_CMD_XFR_TYP_CCCEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_XFR_TYP_CCCEN_SHIFT)) & USDHC_CMD_XFR_TYP_CCCEN_MASK) +#define USDHC_CMD_XFR_TYP_CICEN_MASK (0x100000U) +#define USDHC_CMD_XFR_TYP_CICEN_SHIFT (20U) +/*! CICEN - Command Index Check Enable + * 0b1..Enable + * 0b0..Disable + */ +#define USDHC_CMD_XFR_TYP_CICEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_XFR_TYP_CICEN_SHIFT)) & USDHC_CMD_XFR_TYP_CICEN_MASK) +#define USDHC_CMD_XFR_TYP_DPSEL_MASK (0x200000U) +#define USDHC_CMD_XFR_TYP_DPSEL_SHIFT (21U) +/*! DPSEL - Data Present Select + * 0b1..Data Present + * 0b0..No Data Present + */ +#define USDHC_CMD_XFR_TYP_DPSEL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_XFR_TYP_DPSEL_SHIFT)) & USDHC_CMD_XFR_TYP_DPSEL_MASK) +#define USDHC_CMD_XFR_TYP_CMDTYP_MASK (0xC00000U) +#define USDHC_CMD_XFR_TYP_CMDTYP_SHIFT (22U) +/*! CMDTYP - Command Type + * 0b11..Abort CMD12, CMD52 for writing I/O Abort in CCCR + * 0b10..Resume CMD52 for writing Function Select in CCCR + * 0b01..Suspend CMD52 for writing Bus Suspend in CCCR + * 0b00..Normal Other commands + */ +#define USDHC_CMD_XFR_TYP_CMDTYP(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_XFR_TYP_CMDTYP_SHIFT)) & USDHC_CMD_XFR_TYP_CMDTYP_MASK) +#define USDHC_CMD_XFR_TYP_CMDINX_MASK (0x3F000000U) +#define USDHC_CMD_XFR_TYP_CMDINX_SHIFT (24U) +#define USDHC_CMD_XFR_TYP_CMDINX(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_XFR_TYP_CMDINX_SHIFT)) & USDHC_CMD_XFR_TYP_CMDINX_MASK) +/*! @} */ + +/*! @name CMD_RSP0 - Command Response0 */ +/*! @{ */ +#define USDHC_CMD_RSP0_CMDRSP0_MASK (0xFFFFFFFFU) +#define USDHC_CMD_RSP0_CMDRSP0_SHIFT (0U) +#define USDHC_CMD_RSP0_CMDRSP0(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_RSP0_CMDRSP0_SHIFT)) & USDHC_CMD_RSP0_CMDRSP0_MASK) +/*! @} */ + +/*! @name CMD_RSP1 - Command Response1 */ +/*! @{ */ +#define USDHC_CMD_RSP1_CMDRSP1_MASK (0xFFFFFFFFU) +#define USDHC_CMD_RSP1_CMDRSP1_SHIFT (0U) +#define USDHC_CMD_RSP1_CMDRSP1(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_RSP1_CMDRSP1_SHIFT)) & USDHC_CMD_RSP1_CMDRSP1_MASK) +/*! @} */ + +/*! @name CMD_RSP2 - Command Response2 */ +/*! @{ */ +#define USDHC_CMD_RSP2_CMDRSP2_MASK (0xFFFFFFFFU) +#define USDHC_CMD_RSP2_CMDRSP2_SHIFT (0U) +#define USDHC_CMD_RSP2_CMDRSP2(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_RSP2_CMDRSP2_SHIFT)) & USDHC_CMD_RSP2_CMDRSP2_MASK) +/*! @} */ + +/*! @name CMD_RSP3 - Command Response3 */ +/*! @{ */ +#define USDHC_CMD_RSP3_CMDRSP3_MASK (0xFFFFFFFFU) +#define USDHC_CMD_RSP3_CMDRSP3_SHIFT (0U) +#define USDHC_CMD_RSP3_CMDRSP3(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_RSP3_CMDRSP3_SHIFT)) & USDHC_CMD_RSP3_CMDRSP3_MASK) +/*! @} */ + +/*! @name DATA_BUFF_ACC_PORT - Data Buffer Access Port */ +/*! @{ */ +#define USDHC_DATA_BUFF_ACC_PORT_DATCONT_MASK (0xFFFFFFFFU) +#define USDHC_DATA_BUFF_ACC_PORT_DATCONT_SHIFT (0U) +#define USDHC_DATA_BUFF_ACC_PORT_DATCONT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DATA_BUFF_ACC_PORT_DATCONT_SHIFT)) & USDHC_DATA_BUFF_ACC_PORT_DATCONT_MASK) +/*! @} */ + +/*! @name PRES_STATE - Present State */ +/*! @{ */ +#define USDHC_PRES_STATE_CIHB_MASK (0x1U) +#define USDHC_PRES_STATE_CIHB_SHIFT (0U) +/*! CIHB - Command Inhibit (CMD) + * 0b1..Cannot issue command + * 0b0..Can issue command using only CMD line + */ +#define USDHC_PRES_STATE_CIHB(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_CIHB_SHIFT)) & USDHC_PRES_STATE_CIHB_MASK) +#define USDHC_PRES_STATE_CDIHB_MASK (0x2U) +#define USDHC_PRES_STATE_CDIHB_SHIFT (1U) +/*! CDIHB - Command Inhibit (DATA) + * 0b1..Cannot issue command which uses the DATA line + * 0b0..Can issue command which uses the DATA line + */ +#define USDHC_PRES_STATE_CDIHB(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_CDIHB_SHIFT)) & USDHC_PRES_STATE_CDIHB_MASK) +#define USDHC_PRES_STATE_DLA_MASK (0x4U) +#define USDHC_PRES_STATE_DLA_SHIFT (2U) +/*! DLA - Data Line Active + * 0b1..DATA Line Active + * 0b0..DATA Line Inactive + */ +#define USDHC_PRES_STATE_DLA(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_DLA_SHIFT)) & USDHC_PRES_STATE_DLA_MASK) +#define USDHC_PRES_STATE_SDSTB_MASK (0x8U) +#define USDHC_PRES_STATE_SDSTB_SHIFT (3U) +/*! SDSTB - SD Clock Stable + * 0b1..Clock is stable. + * 0b0..Clock is changing frequency and not stable. + */ +#define USDHC_PRES_STATE_SDSTB(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_SDSTB_SHIFT)) & USDHC_PRES_STATE_SDSTB_MASK) +#define USDHC_PRES_STATE_IPGOFF_MASK (0x10U) +#define USDHC_PRES_STATE_IPGOFF_SHIFT (4U) +/*! IPGOFF - IPG_CLK Gated Off Internally + * 0b1..IPG_CLK is gated off. + * 0b0..IPG_CLK is active. + */ +#define USDHC_PRES_STATE_IPGOFF(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_IPGOFF_SHIFT)) & USDHC_PRES_STATE_IPGOFF_MASK) +#define USDHC_PRES_STATE_HCKOFF_MASK (0x20U) +#define USDHC_PRES_STATE_HCKOFF_SHIFT (5U) +/*! HCKOFF - HCLK Gated Off Internally + * 0b1..HCLK is gated off. + * 0b0..HCLK is active. + */ +#define USDHC_PRES_STATE_HCKOFF(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_HCKOFF_SHIFT)) & USDHC_PRES_STATE_HCKOFF_MASK) +#define USDHC_PRES_STATE_PEROFF_MASK (0x40U) +#define USDHC_PRES_STATE_PEROFF_SHIFT (6U) +/*! PEROFF - IPG_PERCLK Gated Off Internally + * 0b1..IPG_PERCLK is gated off. + * 0b0..IPG_PERCLK is active. + */ +#define USDHC_PRES_STATE_PEROFF(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_PEROFF_SHIFT)) & USDHC_PRES_STATE_PEROFF_MASK) +#define USDHC_PRES_STATE_SDOFF_MASK (0x80U) +#define USDHC_PRES_STATE_SDOFF_SHIFT (7U) +/*! SDOFF - SD Clock Gated Off Internally + * 0b1..SD Clock is gated off. + * 0b0..SD Clock is active. + */ +#define USDHC_PRES_STATE_SDOFF(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_SDOFF_SHIFT)) & USDHC_PRES_STATE_SDOFF_MASK) +#define USDHC_PRES_STATE_WTA_MASK (0x100U) +#define USDHC_PRES_STATE_WTA_SHIFT (8U) +/*! WTA - Write Transfer Active + * 0b1..Transferring data + * 0b0..No valid data + */ +#define USDHC_PRES_STATE_WTA(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_WTA_SHIFT)) & USDHC_PRES_STATE_WTA_MASK) +#define USDHC_PRES_STATE_RTA_MASK (0x200U) +#define USDHC_PRES_STATE_RTA_SHIFT (9U) +/*! RTA - Read Transfer Active + * 0b1..Transferring data + * 0b0..No valid data + */ +#define USDHC_PRES_STATE_RTA(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_RTA_SHIFT)) & USDHC_PRES_STATE_RTA_MASK) +#define USDHC_PRES_STATE_BWEN_MASK (0x400U) +#define USDHC_PRES_STATE_BWEN_SHIFT (10U) +/*! BWEN - Buffer Write Enable + * 0b1..Write enable + * 0b0..Write disable + */ +#define USDHC_PRES_STATE_BWEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_BWEN_SHIFT)) & USDHC_PRES_STATE_BWEN_MASK) +#define USDHC_PRES_STATE_BREN_MASK (0x800U) +#define USDHC_PRES_STATE_BREN_SHIFT (11U) +/*! BREN - Buffer Read Enable + * 0b1..Read enable + * 0b0..Read disable + */ +#define USDHC_PRES_STATE_BREN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_BREN_SHIFT)) & USDHC_PRES_STATE_BREN_MASK) +#define USDHC_PRES_STATE_RTR_MASK (0x1000U) +#define USDHC_PRES_STATE_RTR_SHIFT (12U) +/*! RTR - Re-Tuning Request (only for SD3.0 SDR104 mode and EMMC HS200 mode) + * 0b1..Sampling clock needs re-tuning + * 0b0..Fixed or well tuned sampling clock + */ +#define USDHC_PRES_STATE_RTR(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_RTR_SHIFT)) & USDHC_PRES_STATE_RTR_MASK) +#define USDHC_PRES_STATE_TSCD_MASK (0x8000U) +#define USDHC_PRES_STATE_TSCD_SHIFT (15U) +/*! TSCD - Tape Select Change Done + * 0b1..Delay cell select change is finished. + * 0b0..Delay cell select change is not finished. + */ +#define USDHC_PRES_STATE_TSCD(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_TSCD_SHIFT)) & USDHC_PRES_STATE_TSCD_MASK) +#define USDHC_PRES_STATE_CINST_MASK (0x10000U) +#define USDHC_PRES_STATE_CINST_SHIFT (16U) +/*! CINST - Card Inserted + * 0b1..Card Inserted + * 0b0..Power on Reset or No Card + */ +#define USDHC_PRES_STATE_CINST(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_CINST_SHIFT)) & USDHC_PRES_STATE_CINST_MASK) +#define USDHC_PRES_STATE_CDPL_MASK (0x40000U) +#define USDHC_PRES_STATE_CDPL_SHIFT (18U) +/*! CDPL - Card Detect Pin Level + * 0b1..Card present (CD_B = 0) + * 0b0..No card present (CD_B = 1) + */ +#define USDHC_PRES_STATE_CDPL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_CDPL_SHIFT)) & USDHC_PRES_STATE_CDPL_MASK) +#define USDHC_PRES_STATE_WPSPL_MASK (0x80000U) +#define USDHC_PRES_STATE_WPSPL_SHIFT (19U) +/*! WPSPL - Write Protect Switch Pin Level + * 0b1..Write enabled (WP = 0) + * 0b0..Write protected (WP = 1) + */ +#define USDHC_PRES_STATE_WPSPL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_WPSPL_SHIFT)) & USDHC_PRES_STATE_WPSPL_MASK) +#define USDHC_PRES_STATE_CLSL_MASK (0x800000U) +#define USDHC_PRES_STATE_CLSL_SHIFT (23U) +#define USDHC_PRES_STATE_CLSL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_CLSL_SHIFT)) & USDHC_PRES_STATE_CLSL_MASK) +#define USDHC_PRES_STATE_DLSL_MASK (0xFF000000U) +#define USDHC_PRES_STATE_DLSL_SHIFT (24U) +/*! DLSL - DATA[7:0] Line Signal Level + * 0b00000111..Data 7 line signal level + * 0b00000110..Data 6 line signal level + * 0b00000101..Data 5 line signal level + * 0b00000100..Data 4 line signal level + * 0b00000011..Data 3 line signal level + * 0b00000010..Data 2 line signal level + * 0b00000001..Data 1 line signal level + * 0b00000000..Data 0 line signal level + */ +#define USDHC_PRES_STATE_DLSL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_DLSL_SHIFT)) & USDHC_PRES_STATE_DLSL_MASK) +/*! @} */ + +/*! @name PROT_CTRL - Protocol Control */ +/*! @{ */ +#define USDHC_PROT_CTRL_LCTL_MASK (0x1U) +#define USDHC_PROT_CTRL_LCTL_SHIFT (0U) +/*! LCTL - LED Control + * 0b1..LED on + * 0b0..LED off + */ +#define USDHC_PROT_CTRL_LCTL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_LCTL_SHIFT)) & USDHC_PROT_CTRL_LCTL_MASK) +#define USDHC_PROT_CTRL_DTW_MASK (0x6U) +#define USDHC_PROT_CTRL_DTW_SHIFT (1U) +/*! DTW - Data Transfer Width + * 0b10..8-bit mode + * 0b01..4-bit mode + * 0b00..1-bit mode + * 0b11..Reserved + */ +#define USDHC_PROT_CTRL_DTW(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_DTW_SHIFT)) & USDHC_PROT_CTRL_DTW_MASK) +#define USDHC_PROT_CTRL_D3CD_MASK (0x8U) +#define USDHC_PROT_CTRL_D3CD_SHIFT (3U) +/*! D3CD - DATA3 as Card Detection Pin + * 0b1..DATA3 as Card Detection Pin + * 0b0..DATA3 does not monitor Card Insertion + */ +#define USDHC_PROT_CTRL_D3CD(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_D3CD_SHIFT)) & USDHC_PROT_CTRL_D3CD_MASK) +#define USDHC_PROT_CTRL_EMODE_MASK (0x30U) +#define USDHC_PROT_CTRL_EMODE_SHIFT (4U) +/*! EMODE - Endian Mode + * 0b00..Big Endian Mode + * 0b01..Half Word Big Endian Mode + * 0b10..Little Endian Mode + * 0b11..Reserved + */ +#define USDHC_PROT_CTRL_EMODE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_EMODE_SHIFT)) & USDHC_PROT_CTRL_EMODE_MASK) +#define USDHC_PROT_CTRL_CDTL_MASK (0x40U) +#define USDHC_PROT_CTRL_CDTL_SHIFT (6U) +/*! CDTL - Card Detect Test Level + * 0b1..Card Detect Test Level is 1, card inserted + * 0b0..Card Detect Test Level is 0, no card inserted + */ +#define USDHC_PROT_CTRL_CDTL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_CDTL_SHIFT)) & USDHC_PROT_CTRL_CDTL_MASK) +#define USDHC_PROT_CTRL_CDSS_MASK (0x80U) +#define USDHC_PROT_CTRL_CDSS_SHIFT (7U) +/*! CDSS - Card Detect Signal Selection + * 0b1..Card Detection Test Level is selected (for test purpose). + * 0b0..Card Detection Level is selected (for normal purpose). + */ +#define USDHC_PROT_CTRL_CDSS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_CDSS_SHIFT)) & USDHC_PROT_CTRL_CDSS_MASK) +#define USDHC_PROT_CTRL_DMASEL_MASK (0x300U) +#define USDHC_PROT_CTRL_DMASEL_SHIFT (8U) +/*! DMASEL - DMA Select + * 0b00..No DMA or Simple DMA is selected + * 0b01..ADMA1 is selected + * 0b10..ADMA2 is selected + * 0b11..reserved + */ +#define USDHC_PROT_CTRL_DMASEL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_DMASEL_SHIFT)) & USDHC_PROT_CTRL_DMASEL_MASK) +#define USDHC_PROT_CTRL_SABGREQ_MASK (0x10000U) +#define USDHC_PROT_CTRL_SABGREQ_SHIFT (16U) +/*! SABGREQ - Stop At Block Gap Request + * 0b1..Stop + * 0b0..Transfer + */ +#define USDHC_PROT_CTRL_SABGREQ(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_SABGREQ_SHIFT)) & USDHC_PROT_CTRL_SABGREQ_MASK) +#define USDHC_PROT_CTRL_CREQ_MASK (0x20000U) +#define USDHC_PROT_CTRL_CREQ_SHIFT (17U) +/*! CREQ - Continue Request + * 0b1..Restart + * 0b0..No effect + */ +#define USDHC_PROT_CTRL_CREQ(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_CREQ_SHIFT)) & USDHC_PROT_CTRL_CREQ_MASK) +#define USDHC_PROT_CTRL_RWCTL_MASK (0x40000U) +#define USDHC_PROT_CTRL_RWCTL_SHIFT (18U) +/*! RWCTL - Read Wait Control + * 0b1..Enable Read Wait Control, and assert Read Wait without stopping SD Clock at block gap when SABGREQ bit is set + * 0b0..Disable Read Wait Control, and stop SD Clock at block gap when SABGREQ bit is set + */ +#define USDHC_PROT_CTRL_RWCTL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_RWCTL_SHIFT)) & USDHC_PROT_CTRL_RWCTL_MASK) +#define USDHC_PROT_CTRL_IABG_MASK (0x80000U) +#define USDHC_PROT_CTRL_IABG_SHIFT (19U) +/*! IABG - Interrupt At Block Gap + * 0b1..Enabled + * 0b0..Disabled + */ +#define USDHC_PROT_CTRL_IABG(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_IABG_SHIFT)) & USDHC_PROT_CTRL_IABG_MASK) +#define USDHC_PROT_CTRL_RD_DONE_NO_8CLK_MASK (0x100000U) +#define USDHC_PROT_CTRL_RD_DONE_NO_8CLK_SHIFT (20U) +#define USDHC_PROT_CTRL_RD_DONE_NO_8CLK(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_RD_DONE_NO_8CLK_SHIFT)) & USDHC_PROT_CTRL_RD_DONE_NO_8CLK_MASK) +#define USDHC_PROT_CTRL_WECINT_MASK (0x1000000U) +#define USDHC_PROT_CTRL_WECINT_SHIFT (24U) +/*! WECINT - Wakeup Event Enable On Card Interrupt + * 0b1..Enable + * 0b0..Disable + */ +#define USDHC_PROT_CTRL_WECINT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_WECINT_SHIFT)) & USDHC_PROT_CTRL_WECINT_MASK) +#define USDHC_PROT_CTRL_WECINS_MASK (0x2000000U) +#define USDHC_PROT_CTRL_WECINS_SHIFT (25U) +/*! WECINS - Wakeup Event Enable On SD Card Insertion + * 0b1..Enable + * 0b0..Disable + */ +#define USDHC_PROT_CTRL_WECINS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_WECINS_SHIFT)) & USDHC_PROT_CTRL_WECINS_MASK) +#define USDHC_PROT_CTRL_WECRM_MASK (0x4000000U) +#define USDHC_PROT_CTRL_WECRM_SHIFT (26U) +/*! WECRM - Wakeup Event Enable On SD Card Removal + * 0b1..Enable + * 0b0..Disable + */ +#define USDHC_PROT_CTRL_WECRM(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_WECRM_SHIFT)) & USDHC_PROT_CTRL_WECRM_MASK) +#define USDHC_PROT_CTRL_BURST_LEN_EN_MASK (0x38000000U) +#define USDHC_PROT_CTRL_BURST_LEN_EN_SHIFT (27U) +/*! BURST_LEN_EN - BURST length enable for INCR, INCR4 / INCR8 / INCR16, INCR4-WRAP / INCR8-WRAP / INCR16-WRAP + * 0bxx1..Burst length is enabled for INCR + * 0bx1x..Burst length is enabled for INCR4 / INCR8 / INCR16 + * 0b1xx..Burst length is enabled for INCR4-WRAP / INCR8-WRAP / INCR16-WRAP + */ +#define USDHC_PROT_CTRL_BURST_LEN_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_BURST_LEN_EN_SHIFT)) & USDHC_PROT_CTRL_BURST_LEN_EN_MASK) +#define USDHC_PROT_CTRL_NON_EXACT_BLK_RD_MASK (0x40000000U) +#define USDHC_PROT_CTRL_NON_EXACT_BLK_RD_SHIFT (30U) +/*! NON_EXACT_BLK_RD - NON_EXACT_BLK_RD + * 0b1..The block read is non-exact block read. Host driver needs to issue abort command to terminate this multi-block read. + * 0b0..The block read is exact block read. Host driver doesn't need to issue abort command to terminate this multi-block read. + */ +#define USDHC_PROT_CTRL_NON_EXACT_BLK_RD(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_NON_EXACT_BLK_RD_SHIFT)) & USDHC_PROT_CTRL_NON_EXACT_BLK_RD_MASK) +/*! @} */ + +/*! @name SYS_CTRL - System Control */ +/*! @{ */ +#define USDHC_SYS_CTRL_DVS_MASK (0xF0U) +#define USDHC_SYS_CTRL_DVS_SHIFT (4U) +/*! DVS - Divisor + * 0b0000..Divide-by-1 + * 0b0001..Divide-by-2 + * 0b1110..Divide-by-15 + * 0b1111..Divide-by-16 + */ +#define USDHC_SYS_CTRL_DVS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_DVS_SHIFT)) & USDHC_SYS_CTRL_DVS_MASK) +#define USDHC_SYS_CTRL_SDCLKFS_MASK (0xFF00U) +#define USDHC_SYS_CTRL_SDCLKFS_SHIFT (8U) +#define USDHC_SYS_CTRL_SDCLKFS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_SDCLKFS_SHIFT)) & USDHC_SYS_CTRL_SDCLKFS_MASK) +#define USDHC_SYS_CTRL_DTOCV_MASK (0xF0000U) +#define USDHC_SYS_CTRL_DTOCV_SHIFT (16U) +/*! DTOCV - Data Timeout Counter Value + * 0b1111..SDCLK x 2 29 + * 0b1110..SDCLK x 2 28 + * 0b1101..SDCLK x 2 27 + * 0b0001..SDCLK x 2 15 + * 0b0000..SDCLK x 2 14 + */ +#define USDHC_SYS_CTRL_DTOCV(x) (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_DTOCV_SHIFT)) & USDHC_SYS_CTRL_DTOCV_MASK) +#define USDHC_SYS_CTRL_IPP_RST_N_MASK (0x800000U) +#define USDHC_SYS_CTRL_IPP_RST_N_SHIFT (23U) +#define USDHC_SYS_CTRL_IPP_RST_N(x) (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_IPP_RST_N_SHIFT)) & USDHC_SYS_CTRL_IPP_RST_N_MASK) +#define USDHC_SYS_CTRL_RSTA_MASK (0x1000000U) +#define USDHC_SYS_CTRL_RSTA_SHIFT (24U) +/*! RSTA - Software Reset For ALL + * 0b1..Reset + * 0b0..No Reset + */ +#define USDHC_SYS_CTRL_RSTA(x) (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_RSTA_SHIFT)) & USDHC_SYS_CTRL_RSTA_MASK) +#define USDHC_SYS_CTRL_RSTC_MASK (0x2000000U) +#define USDHC_SYS_CTRL_RSTC_SHIFT (25U) +/*! RSTC - Software Reset For CMD Line + * 0b1..Reset + * 0b0..No Reset + */ +#define USDHC_SYS_CTRL_RSTC(x) (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_RSTC_SHIFT)) & USDHC_SYS_CTRL_RSTC_MASK) +#define USDHC_SYS_CTRL_RSTD_MASK (0x4000000U) +#define USDHC_SYS_CTRL_RSTD_SHIFT (26U) +/*! RSTD - Software Reset For DATA Line + * 0b1..Reset + * 0b0..No Reset + */ +#define USDHC_SYS_CTRL_RSTD(x) (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_RSTD_SHIFT)) & USDHC_SYS_CTRL_RSTD_MASK) +#define USDHC_SYS_CTRL_INITA_MASK (0x8000000U) +#define USDHC_SYS_CTRL_INITA_SHIFT (27U) +#define USDHC_SYS_CTRL_INITA(x) (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_INITA_SHIFT)) & USDHC_SYS_CTRL_INITA_MASK) +#define USDHC_SYS_CTRL_RSTT_MASK (0x10000000U) +#define USDHC_SYS_CTRL_RSTT_SHIFT (28U) +#define USDHC_SYS_CTRL_RSTT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_RSTT_SHIFT)) & USDHC_SYS_CTRL_RSTT_MASK) +/*! @} */ + +/*! @name INT_STATUS - Interrupt Status */ +/*! @{ */ +#define USDHC_INT_STATUS_CC_MASK (0x1U) +#define USDHC_INT_STATUS_CC_SHIFT (0U) +/*! CC - Command Complete + * 0b1..Command complete + * 0b0..Command not complete + */ +#define USDHC_INT_STATUS_CC(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_CC_SHIFT)) & USDHC_INT_STATUS_CC_MASK) +#define USDHC_INT_STATUS_TC_MASK (0x2U) +#define USDHC_INT_STATUS_TC_SHIFT (1U) +/*! TC - Transfer Complete + * 0b1..Transfer complete + * 0b0..Transfer not complete + */ +#define USDHC_INT_STATUS_TC(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_TC_SHIFT)) & USDHC_INT_STATUS_TC_MASK) +#define USDHC_INT_STATUS_BGE_MASK (0x4U) +#define USDHC_INT_STATUS_BGE_SHIFT (2U) +/*! BGE - Block Gap Event + * 0b1..Transaction stopped at block gap + * 0b0..No block gap event + */ +#define USDHC_INT_STATUS_BGE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_BGE_SHIFT)) & USDHC_INT_STATUS_BGE_MASK) +#define USDHC_INT_STATUS_DINT_MASK (0x8U) +#define USDHC_INT_STATUS_DINT_SHIFT (3U) +/*! DINT - DMA Interrupt + * 0b1..DMA Interrupt is generated + * 0b0..No DMA Interrupt + */ +#define USDHC_INT_STATUS_DINT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_DINT_SHIFT)) & USDHC_INT_STATUS_DINT_MASK) +#define USDHC_INT_STATUS_BWR_MASK (0x10U) +#define USDHC_INT_STATUS_BWR_SHIFT (4U) +/*! BWR - Buffer Write Ready + * 0b1..Ready to write buffer: + * 0b0..Not ready to write buffer + */ +#define USDHC_INT_STATUS_BWR(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_BWR_SHIFT)) & USDHC_INT_STATUS_BWR_MASK) +#define USDHC_INT_STATUS_BRR_MASK (0x20U) +#define USDHC_INT_STATUS_BRR_SHIFT (5U) +/*! BRR - Buffer Read Ready + * 0b1..Ready to read buffer + * 0b0..Not ready to read buffer + */ +#define USDHC_INT_STATUS_BRR(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_BRR_SHIFT)) & USDHC_INT_STATUS_BRR_MASK) +#define USDHC_INT_STATUS_CINS_MASK (0x40U) +#define USDHC_INT_STATUS_CINS_SHIFT (6U) +/*! CINS - Card Insertion + * 0b1..Card inserted + * 0b0..Card state unstable or removed + */ +#define USDHC_INT_STATUS_CINS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_CINS_SHIFT)) & USDHC_INT_STATUS_CINS_MASK) +#define USDHC_INT_STATUS_CRM_MASK (0x80U) +#define USDHC_INT_STATUS_CRM_SHIFT (7U) +/*! CRM - Card Removal + * 0b1..Card removed + * 0b0..Card state unstable or inserted + */ +#define USDHC_INT_STATUS_CRM(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_CRM_SHIFT)) & USDHC_INT_STATUS_CRM_MASK) +#define USDHC_INT_STATUS_CINT_MASK (0x100U) +#define USDHC_INT_STATUS_CINT_SHIFT (8U) +/*! CINT - Card Interrupt + * 0b1..Generate Card Interrupt + * 0b0..No Card Interrupt + */ +#define USDHC_INT_STATUS_CINT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_CINT_SHIFT)) & USDHC_INT_STATUS_CINT_MASK) +#define USDHC_INT_STATUS_RTE_MASK (0x1000U) +#define USDHC_INT_STATUS_RTE_SHIFT (12U) +/*! RTE - Re-Tuning Event: (only for SD3.0 SDR104 mode and EMMC HS200 mode) + * 0b1..Re-Tuning should be performed + * 0b0..Re-Tuning is not required + */ +#define USDHC_INT_STATUS_RTE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_RTE_SHIFT)) & USDHC_INT_STATUS_RTE_MASK) +#define USDHC_INT_STATUS_TP_MASK (0x4000U) +#define USDHC_INT_STATUS_TP_SHIFT (14U) +#define USDHC_INT_STATUS_TP(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_TP_SHIFT)) & USDHC_INT_STATUS_TP_MASK) +#define USDHC_INT_STATUS_CTOE_MASK (0x10000U) +#define USDHC_INT_STATUS_CTOE_SHIFT (16U) +/*! CTOE - Command Timeout Error + * 0b1..Time out + * 0b0..No Error + */ +#define USDHC_INT_STATUS_CTOE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_CTOE_SHIFT)) & USDHC_INT_STATUS_CTOE_MASK) +#define USDHC_INT_STATUS_CCE_MASK (0x20000U) +#define USDHC_INT_STATUS_CCE_SHIFT (17U) +/*! CCE - Command CRC Error + * 0b1..CRC Error Generated. + * 0b0..No Error + */ +#define USDHC_INT_STATUS_CCE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_CCE_SHIFT)) & USDHC_INT_STATUS_CCE_MASK) +#define USDHC_INT_STATUS_CEBE_MASK (0x40000U) +#define USDHC_INT_STATUS_CEBE_SHIFT (18U) +/*! CEBE - Command End Bit Error + * 0b1..End Bit Error Generated + * 0b0..No Error + */ +#define USDHC_INT_STATUS_CEBE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_CEBE_SHIFT)) & USDHC_INT_STATUS_CEBE_MASK) +#define USDHC_INT_STATUS_CIE_MASK (0x80000U) +#define USDHC_INT_STATUS_CIE_SHIFT (19U) +/*! CIE - Command Index Error + * 0b1..Error + * 0b0..No Error + */ +#define USDHC_INT_STATUS_CIE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_CIE_SHIFT)) & USDHC_INT_STATUS_CIE_MASK) +#define USDHC_INT_STATUS_DTOE_MASK (0x100000U) +#define USDHC_INT_STATUS_DTOE_SHIFT (20U) +/*! DTOE - Data Timeout Error + * 0b1..Time out + * 0b0..No Error + */ +#define USDHC_INT_STATUS_DTOE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_DTOE_SHIFT)) & USDHC_INT_STATUS_DTOE_MASK) +#define USDHC_INT_STATUS_DCE_MASK (0x200000U) +#define USDHC_INT_STATUS_DCE_SHIFT (21U) +/*! DCE - Data CRC Error + * 0b1..Error + * 0b0..No Error + */ +#define USDHC_INT_STATUS_DCE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_DCE_SHIFT)) & USDHC_INT_STATUS_DCE_MASK) +#define USDHC_INT_STATUS_DEBE_MASK (0x400000U) +#define USDHC_INT_STATUS_DEBE_SHIFT (22U) +/*! DEBE - Data End Bit Error + * 0b1..Error + * 0b0..No Error + */ +#define USDHC_INT_STATUS_DEBE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_DEBE_SHIFT)) & USDHC_INT_STATUS_DEBE_MASK) +#define USDHC_INT_STATUS_AC12E_MASK (0x1000000U) +#define USDHC_INT_STATUS_AC12E_SHIFT (24U) +/*! AC12E - Auto CMD12 Error + * 0b1..Error + * 0b0..No Error + */ +#define USDHC_INT_STATUS_AC12E(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_AC12E_SHIFT)) & USDHC_INT_STATUS_AC12E_MASK) +#define USDHC_INT_STATUS_TNE_MASK (0x4000000U) +#define USDHC_INT_STATUS_TNE_SHIFT (26U) +#define USDHC_INT_STATUS_TNE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_TNE_SHIFT)) & USDHC_INT_STATUS_TNE_MASK) +#define USDHC_INT_STATUS_DMAE_MASK (0x10000000U) +#define USDHC_INT_STATUS_DMAE_SHIFT (28U) +/*! DMAE - DMA Error + * 0b1..Error + * 0b0..No Error + */ +#define USDHC_INT_STATUS_DMAE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_DMAE_SHIFT)) & USDHC_INT_STATUS_DMAE_MASK) +/*! @} */ + +/*! @name INT_STATUS_EN - Interrupt Status Enable */ +/*! @{ */ +#define USDHC_INT_STATUS_EN_CCSEN_MASK (0x1U) +#define USDHC_INT_STATUS_EN_CCSEN_SHIFT (0U) +/*! CCSEN - Command Complete Status Enable + * 0b1..Enabled + * 0b0..Masked + */ +#define USDHC_INT_STATUS_EN_CCSEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CCSEN_SHIFT)) & USDHC_INT_STATUS_EN_CCSEN_MASK) +#define USDHC_INT_STATUS_EN_TCSEN_MASK (0x2U) +#define USDHC_INT_STATUS_EN_TCSEN_SHIFT (1U) +/*! TCSEN - Transfer Complete Status Enable + * 0b1..Enabled + * 0b0..Masked + */ +#define USDHC_INT_STATUS_EN_TCSEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_TCSEN_SHIFT)) & USDHC_INT_STATUS_EN_TCSEN_MASK) +#define USDHC_INT_STATUS_EN_BGESEN_MASK (0x4U) +#define USDHC_INT_STATUS_EN_BGESEN_SHIFT (2U) +/*! BGESEN - Block Gap Event Status Enable + * 0b1..Enabled + * 0b0..Masked + */ +#define USDHC_INT_STATUS_EN_BGESEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_BGESEN_SHIFT)) & USDHC_INT_STATUS_EN_BGESEN_MASK) +#define USDHC_INT_STATUS_EN_DINTSEN_MASK (0x8U) +#define USDHC_INT_STATUS_EN_DINTSEN_SHIFT (3U) +/*! DINTSEN - DMA Interrupt Status Enable + * 0b1..Enabled + * 0b0..Masked + */ +#define USDHC_INT_STATUS_EN_DINTSEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_DINTSEN_SHIFT)) & USDHC_INT_STATUS_EN_DINTSEN_MASK) +#define USDHC_INT_STATUS_EN_BWRSEN_MASK (0x10U) +#define USDHC_INT_STATUS_EN_BWRSEN_SHIFT (4U) +/*! BWRSEN - Buffer Write Ready Status Enable + * 0b1..Enabled + * 0b0..Masked + */ +#define USDHC_INT_STATUS_EN_BWRSEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_BWRSEN_SHIFT)) & USDHC_INT_STATUS_EN_BWRSEN_MASK) +#define USDHC_INT_STATUS_EN_BRRSEN_MASK (0x20U) +#define USDHC_INT_STATUS_EN_BRRSEN_SHIFT (5U) +/*! BRRSEN - Buffer Read Ready Status Enable + * 0b1..Enabled + * 0b0..Masked + */ +#define USDHC_INT_STATUS_EN_BRRSEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_BRRSEN_SHIFT)) & USDHC_INT_STATUS_EN_BRRSEN_MASK) +#define USDHC_INT_STATUS_EN_CINSSEN_MASK (0x40U) +#define USDHC_INT_STATUS_EN_CINSSEN_SHIFT (6U) +/*! CINSSEN - Card Insertion Status Enable + * 0b1..Enabled + * 0b0..Masked + */ +#define USDHC_INT_STATUS_EN_CINSSEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CINSSEN_SHIFT)) & USDHC_INT_STATUS_EN_CINSSEN_MASK) +#define USDHC_INT_STATUS_EN_CRMSEN_MASK (0x80U) +#define USDHC_INT_STATUS_EN_CRMSEN_SHIFT (7U) +/*! CRMSEN - Card Removal Status Enable + * 0b1..Enabled + * 0b0..Masked + */ +#define USDHC_INT_STATUS_EN_CRMSEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CRMSEN_SHIFT)) & USDHC_INT_STATUS_EN_CRMSEN_MASK) +#define USDHC_INT_STATUS_EN_CINTSEN_MASK (0x100U) +#define USDHC_INT_STATUS_EN_CINTSEN_SHIFT (8U) +/*! CINTSEN - Card Interrupt Status Enable + * 0b1..Enabled + * 0b0..Masked + */ +#define USDHC_INT_STATUS_EN_CINTSEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CINTSEN_SHIFT)) & USDHC_INT_STATUS_EN_CINTSEN_MASK) +#define USDHC_INT_STATUS_EN_RTESEN_MASK (0x1000U) +#define USDHC_INT_STATUS_EN_RTESEN_SHIFT (12U) +/*! RTESEN - Re-Tuning Event Status Enable + * 0b1..Enabled + * 0b0..Masked + */ +#define USDHC_INT_STATUS_EN_RTESEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_RTESEN_SHIFT)) & USDHC_INT_STATUS_EN_RTESEN_MASK) +#define USDHC_INT_STATUS_EN_TPSEN_MASK (0x4000U) +#define USDHC_INT_STATUS_EN_TPSEN_SHIFT (14U) +/*! TPSEN - Tuning Pass Status Enable + * 0b1..Enabled + * 0b0..Masked + */ +#define USDHC_INT_STATUS_EN_TPSEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_TPSEN_SHIFT)) & USDHC_INT_STATUS_EN_TPSEN_MASK) +#define USDHC_INT_STATUS_EN_CTOESEN_MASK (0x10000U) +#define USDHC_INT_STATUS_EN_CTOESEN_SHIFT (16U) +/*! CTOESEN - Command Timeout Error Status Enable + * 0b1..Enabled + * 0b0..Masked + */ +#define USDHC_INT_STATUS_EN_CTOESEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CTOESEN_SHIFT)) & USDHC_INT_STATUS_EN_CTOESEN_MASK) +#define USDHC_INT_STATUS_EN_CCESEN_MASK (0x20000U) +#define USDHC_INT_STATUS_EN_CCESEN_SHIFT (17U) +/*! CCESEN - Command CRC Error Status Enable + * 0b1..Enabled + * 0b0..Masked + */ +#define USDHC_INT_STATUS_EN_CCESEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CCESEN_SHIFT)) & USDHC_INT_STATUS_EN_CCESEN_MASK) +#define USDHC_INT_STATUS_EN_CEBESEN_MASK (0x40000U) +#define USDHC_INT_STATUS_EN_CEBESEN_SHIFT (18U) +/*! CEBESEN - Command End Bit Error Status Enable + * 0b1..Enabled + * 0b0..Masked + */ +#define USDHC_INT_STATUS_EN_CEBESEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CEBESEN_SHIFT)) & USDHC_INT_STATUS_EN_CEBESEN_MASK) +#define USDHC_INT_STATUS_EN_CIESEN_MASK (0x80000U) +#define USDHC_INT_STATUS_EN_CIESEN_SHIFT (19U) +/*! CIESEN - Command Index Error Status Enable + * 0b1..Enabled + * 0b0..Masked + */ +#define USDHC_INT_STATUS_EN_CIESEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CIESEN_SHIFT)) & USDHC_INT_STATUS_EN_CIESEN_MASK) +#define USDHC_INT_STATUS_EN_DTOESEN_MASK (0x100000U) +#define USDHC_INT_STATUS_EN_DTOESEN_SHIFT (20U) +/*! DTOESEN - Data Timeout Error Status Enable + * 0b1..Enabled + * 0b0..Masked + */ +#define USDHC_INT_STATUS_EN_DTOESEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_DTOESEN_SHIFT)) & USDHC_INT_STATUS_EN_DTOESEN_MASK) +#define USDHC_INT_STATUS_EN_DCESEN_MASK (0x200000U) +#define USDHC_INT_STATUS_EN_DCESEN_SHIFT (21U) +/*! DCESEN - Data CRC Error Status Enable + * 0b1..Enabled + * 0b0..Masked + */ +#define USDHC_INT_STATUS_EN_DCESEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_DCESEN_SHIFT)) & USDHC_INT_STATUS_EN_DCESEN_MASK) +#define USDHC_INT_STATUS_EN_DEBESEN_MASK (0x400000U) +#define USDHC_INT_STATUS_EN_DEBESEN_SHIFT (22U) +/*! DEBESEN - Data End Bit Error Status Enable + * 0b1..Enabled + * 0b0..Masked + */ +#define USDHC_INT_STATUS_EN_DEBESEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_DEBESEN_SHIFT)) & USDHC_INT_STATUS_EN_DEBESEN_MASK) +#define USDHC_INT_STATUS_EN_AC12ESEN_MASK (0x1000000U) +#define USDHC_INT_STATUS_EN_AC12ESEN_SHIFT (24U) +/*! AC12ESEN - Auto CMD12 Error Status Enable + * 0b1..Enabled + * 0b0..Masked + */ +#define USDHC_INT_STATUS_EN_AC12ESEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_AC12ESEN_SHIFT)) & USDHC_INT_STATUS_EN_AC12ESEN_MASK) +#define USDHC_INT_STATUS_EN_TNESEN_MASK (0x4000000U) +#define USDHC_INT_STATUS_EN_TNESEN_SHIFT (26U) +/*! TNESEN - Tuning Error Status Enable + * 0b1..Enabled + * 0b0..Masked + */ +#define USDHC_INT_STATUS_EN_TNESEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_TNESEN_SHIFT)) & USDHC_INT_STATUS_EN_TNESEN_MASK) +#define USDHC_INT_STATUS_EN_DMAESEN_MASK (0x10000000U) +#define USDHC_INT_STATUS_EN_DMAESEN_SHIFT (28U) +/*! DMAESEN - DMA Error Status Enable + * 0b1..Enabled + * 0b0..Masked + */ +#define USDHC_INT_STATUS_EN_DMAESEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_DMAESEN_SHIFT)) & USDHC_INT_STATUS_EN_DMAESEN_MASK) +/*! @} */ + +/*! @name INT_SIGNAL_EN - Interrupt Signal Enable */ +/*! @{ */ +#define USDHC_INT_SIGNAL_EN_CCIEN_MASK (0x1U) +#define USDHC_INT_SIGNAL_EN_CCIEN_SHIFT (0U) +/*! CCIEN - Command Complete Interrupt Enable + * 0b1..Enabled + * 0b0..Masked + */ +#define USDHC_INT_SIGNAL_EN_CCIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CCIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CCIEN_MASK) +#define USDHC_INT_SIGNAL_EN_TCIEN_MASK (0x2U) +#define USDHC_INT_SIGNAL_EN_TCIEN_SHIFT (1U) +/*! TCIEN - Transfer Complete Interrupt Enable + * 0b1..Enabled + * 0b0..Masked + */ +#define USDHC_INT_SIGNAL_EN_TCIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_TCIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_TCIEN_MASK) +#define USDHC_INT_SIGNAL_EN_BGEIEN_MASK (0x4U) +#define USDHC_INT_SIGNAL_EN_BGEIEN_SHIFT (2U) +/*! BGEIEN - Block Gap Event Interrupt Enable + * 0b1..Enabled + * 0b0..Masked + */ +#define USDHC_INT_SIGNAL_EN_BGEIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_BGEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_BGEIEN_MASK) +#define USDHC_INT_SIGNAL_EN_DINTIEN_MASK (0x8U) +#define USDHC_INT_SIGNAL_EN_DINTIEN_SHIFT (3U) +/*! DINTIEN - DMA Interrupt Enable + * 0b1..Enabled + * 0b0..Masked + */ +#define USDHC_INT_SIGNAL_EN_DINTIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_DINTIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_DINTIEN_MASK) +#define USDHC_INT_SIGNAL_EN_BWRIEN_MASK (0x10U) +#define USDHC_INT_SIGNAL_EN_BWRIEN_SHIFT (4U) +/*! BWRIEN - Buffer Write Ready Interrupt Enable + * 0b1..Enabled + * 0b0..Masked + */ +#define USDHC_INT_SIGNAL_EN_BWRIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_BWRIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_BWRIEN_MASK) +#define USDHC_INT_SIGNAL_EN_BRRIEN_MASK (0x20U) +#define USDHC_INT_SIGNAL_EN_BRRIEN_SHIFT (5U) +/*! BRRIEN - Buffer Read Ready Interrupt Enable + * 0b1..Enabled + * 0b0..Masked + */ +#define USDHC_INT_SIGNAL_EN_BRRIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_BRRIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_BRRIEN_MASK) +#define USDHC_INT_SIGNAL_EN_CINSIEN_MASK (0x40U) +#define USDHC_INT_SIGNAL_EN_CINSIEN_SHIFT (6U) +/*! CINSIEN - Card Insertion Interrupt Enable + * 0b1..Enabled + * 0b0..Masked + */ +#define USDHC_INT_SIGNAL_EN_CINSIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CINSIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CINSIEN_MASK) +#define USDHC_INT_SIGNAL_EN_CRMIEN_MASK (0x80U) +#define USDHC_INT_SIGNAL_EN_CRMIEN_SHIFT (7U) +/*! CRMIEN - Card Removal Interrupt Enable + * 0b1..Enabled + * 0b0..Masked + */ +#define USDHC_INT_SIGNAL_EN_CRMIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CRMIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CRMIEN_MASK) +#define USDHC_INT_SIGNAL_EN_CINTIEN_MASK (0x100U) +#define USDHC_INT_SIGNAL_EN_CINTIEN_SHIFT (8U) +/*! CINTIEN - Card Interrupt Interrupt Enable + * 0b1..Enabled + * 0b0..Masked + */ +#define USDHC_INT_SIGNAL_EN_CINTIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CINTIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CINTIEN_MASK) +#define USDHC_INT_SIGNAL_EN_RTEIEN_MASK (0x1000U) +#define USDHC_INT_SIGNAL_EN_RTEIEN_SHIFT (12U) +/*! RTEIEN - Re-Tuning Event Interrupt Enable + * 0b1..Enabled + * 0b0..Masked + */ +#define USDHC_INT_SIGNAL_EN_RTEIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_RTEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_RTEIEN_MASK) +#define USDHC_INT_SIGNAL_EN_TPIEN_MASK (0x4000U) +#define USDHC_INT_SIGNAL_EN_TPIEN_SHIFT (14U) +/*! TPIEN - Tuning Pass Interrupt Enable + * 0b1..Enabled + * 0b0..Masked + */ +#define USDHC_INT_SIGNAL_EN_TPIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_TPIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_TPIEN_MASK) +#define USDHC_INT_SIGNAL_EN_CTOEIEN_MASK (0x10000U) +#define USDHC_INT_SIGNAL_EN_CTOEIEN_SHIFT (16U) +/*! CTOEIEN - Command Timeout Error Interrupt Enable + * 0b1..Enabled + * 0b0..Masked + */ +#define USDHC_INT_SIGNAL_EN_CTOEIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CTOEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CTOEIEN_MASK) +#define USDHC_INT_SIGNAL_EN_CCEIEN_MASK (0x20000U) +#define USDHC_INT_SIGNAL_EN_CCEIEN_SHIFT (17U) +/*! CCEIEN - Command CRC Error Interrupt Enable + * 0b1..Enabled + * 0b0..Masked + */ +#define USDHC_INT_SIGNAL_EN_CCEIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CCEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CCEIEN_MASK) +#define USDHC_INT_SIGNAL_EN_CEBEIEN_MASK (0x40000U) +#define USDHC_INT_SIGNAL_EN_CEBEIEN_SHIFT (18U) +/*! CEBEIEN - Command End Bit Error Interrupt Enable + * 0b1..Enabled + * 0b0..Masked + */ +#define USDHC_INT_SIGNAL_EN_CEBEIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CEBEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CEBEIEN_MASK) +#define USDHC_INT_SIGNAL_EN_CIEIEN_MASK (0x80000U) +#define USDHC_INT_SIGNAL_EN_CIEIEN_SHIFT (19U) +/*! CIEIEN - Command Index Error Interrupt Enable + * 0b1..Enabled + * 0b0..Masked + */ +#define USDHC_INT_SIGNAL_EN_CIEIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CIEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CIEIEN_MASK) +#define USDHC_INT_SIGNAL_EN_DTOEIEN_MASK (0x100000U) +#define USDHC_INT_SIGNAL_EN_DTOEIEN_SHIFT (20U) +/*! DTOEIEN - Data Timeout Error Interrupt Enable + * 0b1..Enabled + * 0b0..Masked + */ +#define USDHC_INT_SIGNAL_EN_DTOEIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_DTOEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_DTOEIEN_MASK) +#define USDHC_INT_SIGNAL_EN_DCEIEN_MASK (0x200000U) +#define USDHC_INT_SIGNAL_EN_DCEIEN_SHIFT (21U) +/*! DCEIEN - Data CRC Error Interrupt Enable + * 0b1..Enabled + * 0b0..Masked + */ +#define USDHC_INT_SIGNAL_EN_DCEIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_DCEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_DCEIEN_MASK) +#define USDHC_INT_SIGNAL_EN_DEBEIEN_MASK (0x400000U) +#define USDHC_INT_SIGNAL_EN_DEBEIEN_SHIFT (22U) +/*! DEBEIEN - Data End Bit Error Interrupt Enable + * 0b1..Enabled + * 0b0..Masked + */ +#define USDHC_INT_SIGNAL_EN_DEBEIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_DEBEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_DEBEIEN_MASK) +#define USDHC_INT_SIGNAL_EN_AC12EIEN_MASK (0x1000000U) +#define USDHC_INT_SIGNAL_EN_AC12EIEN_SHIFT (24U) +/*! AC12EIEN - Auto CMD12 Error Interrupt Enable + * 0b1..Enabled + * 0b0..Masked + */ +#define USDHC_INT_SIGNAL_EN_AC12EIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_AC12EIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_AC12EIEN_MASK) +#define USDHC_INT_SIGNAL_EN_TNEIEN_MASK (0x4000000U) +#define USDHC_INT_SIGNAL_EN_TNEIEN_SHIFT (26U) +/*! TNEIEN - Tuning Error Interrupt Enable + * 0b1..Enabled + * 0b0..Masked + */ +#define USDHC_INT_SIGNAL_EN_TNEIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_TNEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_TNEIEN_MASK) +#define USDHC_INT_SIGNAL_EN_DMAEIEN_MASK (0x10000000U) +#define USDHC_INT_SIGNAL_EN_DMAEIEN_SHIFT (28U) +/*! DMAEIEN - DMA Error Interrupt Enable + * 0b1..Enable + * 0b0..Masked + */ +#define USDHC_INT_SIGNAL_EN_DMAEIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_DMAEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_DMAEIEN_MASK) +/*! @} */ + +/*! @name AUTOCMD12_ERR_STATUS - Auto CMD12 Error Status */ +/*! @{ */ +#define USDHC_AUTOCMD12_ERR_STATUS_AC12NE_MASK (0x1U) +#define USDHC_AUTOCMD12_ERR_STATUS_AC12NE_SHIFT (0U) +/*! AC12NE - Auto CMD12 Not Executed + * 0b1..Not executed + * 0b0..Executed + */ +#define USDHC_AUTOCMD12_ERR_STATUS_AC12NE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_AUTOCMD12_ERR_STATUS_AC12NE_SHIFT)) & USDHC_AUTOCMD12_ERR_STATUS_AC12NE_MASK) +#define USDHC_AUTOCMD12_ERR_STATUS_AC12TOE_MASK (0x2U) +#define USDHC_AUTOCMD12_ERR_STATUS_AC12TOE_SHIFT (1U) +/*! AC12TOE - Auto CMD12 / 23 Timeout Error + * 0b1..Time out + * 0b0..No error + */ +#define USDHC_AUTOCMD12_ERR_STATUS_AC12TOE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_AUTOCMD12_ERR_STATUS_AC12TOE_SHIFT)) & USDHC_AUTOCMD12_ERR_STATUS_AC12TOE_MASK) +#define USDHC_AUTOCMD12_ERR_STATUS_AC12EBE_MASK (0x4U) +#define USDHC_AUTOCMD12_ERR_STATUS_AC12EBE_SHIFT (2U) +/*! AC12EBE - Auto CMD12 / 23 End Bit Error + * 0b1..End Bit Error Generated + * 0b0..No error + */ +#define USDHC_AUTOCMD12_ERR_STATUS_AC12EBE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_AUTOCMD12_ERR_STATUS_AC12EBE_SHIFT)) & USDHC_AUTOCMD12_ERR_STATUS_AC12EBE_MASK) +#define USDHC_AUTOCMD12_ERR_STATUS_AC12CE_MASK (0x8U) +#define USDHC_AUTOCMD12_ERR_STATUS_AC12CE_SHIFT (3U) +/*! AC12CE - Auto CMD12 / 23 CRC Error + * 0b1..CRC Error Met in Auto CMD12/23 Response + * 0b0..No CRC error + */ +#define USDHC_AUTOCMD12_ERR_STATUS_AC12CE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_AUTOCMD12_ERR_STATUS_AC12CE_SHIFT)) & USDHC_AUTOCMD12_ERR_STATUS_AC12CE_MASK) +#define USDHC_AUTOCMD12_ERR_STATUS_AC12IE_MASK (0x10U) +#define USDHC_AUTOCMD12_ERR_STATUS_AC12IE_SHIFT (4U) +/*! AC12IE - Auto CMD12 / 23 Index Error + * 0b1..Error, the CMD index in response is not CMD12/23 + * 0b0..No error + */ +#define USDHC_AUTOCMD12_ERR_STATUS_AC12IE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_AUTOCMD12_ERR_STATUS_AC12IE_SHIFT)) & USDHC_AUTOCMD12_ERR_STATUS_AC12IE_MASK) +#define USDHC_AUTOCMD12_ERR_STATUS_CNIBAC12E_MASK (0x80U) +#define USDHC_AUTOCMD12_ERR_STATUS_CNIBAC12E_SHIFT (7U) +/*! CNIBAC12E - Command Not Issued By Auto CMD12 Error + * 0b1..Not Issued + * 0b0..No error + */ +#define USDHC_AUTOCMD12_ERR_STATUS_CNIBAC12E(x) (((uint32_t)(((uint32_t)(x)) << USDHC_AUTOCMD12_ERR_STATUS_CNIBAC12E_SHIFT)) & USDHC_AUTOCMD12_ERR_STATUS_CNIBAC12E_MASK) +#define USDHC_AUTOCMD12_ERR_STATUS_EXECUTE_TUNING_MASK (0x400000U) +#define USDHC_AUTOCMD12_ERR_STATUS_EXECUTE_TUNING_SHIFT (22U) +#define USDHC_AUTOCMD12_ERR_STATUS_EXECUTE_TUNING(x) (((uint32_t)(((uint32_t)(x)) << USDHC_AUTOCMD12_ERR_STATUS_EXECUTE_TUNING_SHIFT)) & USDHC_AUTOCMD12_ERR_STATUS_EXECUTE_TUNING_MASK) +#define USDHC_AUTOCMD12_ERR_STATUS_SMP_CLK_SEL_MASK (0x800000U) +#define USDHC_AUTOCMD12_ERR_STATUS_SMP_CLK_SEL_SHIFT (23U) +/*! SMP_CLK_SEL - Sample Clock Select + * 0b1..Tuned clock is used to sample data + * 0b0..Fixed clock is used to sample data + */ +#define USDHC_AUTOCMD12_ERR_STATUS_SMP_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_AUTOCMD12_ERR_STATUS_SMP_CLK_SEL_SHIFT)) & USDHC_AUTOCMD12_ERR_STATUS_SMP_CLK_SEL_MASK) +/*! @} */ + +/*! @name HOST_CTRL_CAP - Host Controller Capabilities */ +/*! @{ */ +#define USDHC_HOST_CTRL_CAP_SDR50_SUPPORT_MASK (0x1U) +#define USDHC_HOST_CTRL_CAP_SDR50_SUPPORT_SHIFT (0U) +#define USDHC_HOST_CTRL_CAP_SDR50_SUPPORT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_SDR50_SUPPORT_SHIFT)) & USDHC_HOST_CTRL_CAP_SDR50_SUPPORT_MASK) +#define USDHC_HOST_CTRL_CAP_SDR104_SUPPORT_MASK (0x2U) +#define USDHC_HOST_CTRL_CAP_SDR104_SUPPORT_SHIFT (1U) +#define USDHC_HOST_CTRL_CAP_SDR104_SUPPORT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_SDR104_SUPPORT_SHIFT)) & USDHC_HOST_CTRL_CAP_SDR104_SUPPORT_MASK) +#define USDHC_HOST_CTRL_CAP_DDR50_SUPPORT_MASK (0x4U) +#define USDHC_HOST_CTRL_CAP_DDR50_SUPPORT_SHIFT (2U) +#define USDHC_HOST_CTRL_CAP_DDR50_SUPPORT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_DDR50_SUPPORT_SHIFT)) & USDHC_HOST_CTRL_CAP_DDR50_SUPPORT_MASK) +#define USDHC_HOST_CTRL_CAP_TIME_COUNT_RETUNING_MASK (0xF00U) +#define USDHC_HOST_CTRL_CAP_TIME_COUNT_RETUNING_SHIFT (8U) +#define USDHC_HOST_CTRL_CAP_TIME_COUNT_RETUNING(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_TIME_COUNT_RETUNING_SHIFT)) & USDHC_HOST_CTRL_CAP_TIME_COUNT_RETUNING_MASK) +#define USDHC_HOST_CTRL_CAP_USE_TUNING_SDR50_MASK (0x2000U) +#define USDHC_HOST_CTRL_CAP_USE_TUNING_SDR50_SHIFT (13U) +/*! USE_TUNING_SDR50 - Use Tuning for SDR50 + * 0b1..SDR50 requires tuning + * 0b0..SDR does not require tuning + */ +#define USDHC_HOST_CTRL_CAP_USE_TUNING_SDR50(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_USE_TUNING_SDR50_SHIFT)) & USDHC_HOST_CTRL_CAP_USE_TUNING_SDR50_MASK) +#define USDHC_HOST_CTRL_CAP_RETUNING_MODE_MASK (0xC000U) +#define USDHC_HOST_CTRL_CAP_RETUNING_MODE_SHIFT (14U) +/*! RETUNING_MODE - Retuning Mode + * 0b00..Mode 1 + * 0b01..Mode 2 + * 0b10..Mode 3 + * 0b11..Reserved + */ +#define USDHC_HOST_CTRL_CAP_RETUNING_MODE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_RETUNING_MODE_SHIFT)) & USDHC_HOST_CTRL_CAP_RETUNING_MODE_MASK) +#define USDHC_HOST_CTRL_CAP_MBL_MASK (0x70000U) +#define USDHC_HOST_CTRL_CAP_MBL_SHIFT (16U) +/*! MBL - Max Block Length + * 0b000..512 bytes + * 0b001..1024 bytes + * 0b010..2048 bytes + * 0b011..4096 bytes + */ +#define USDHC_HOST_CTRL_CAP_MBL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_MBL_SHIFT)) & USDHC_HOST_CTRL_CAP_MBL_MASK) +#define USDHC_HOST_CTRL_CAP_ADMAS_MASK (0x100000U) +#define USDHC_HOST_CTRL_CAP_ADMAS_SHIFT (20U) +/*! ADMAS - ADMA Support + * 0b1..Advanced DMA Supported + * 0b0..Advanced DMA Not supported + */ +#define USDHC_HOST_CTRL_CAP_ADMAS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_ADMAS_SHIFT)) & USDHC_HOST_CTRL_CAP_ADMAS_MASK) +#define USDHC_HOST_CTRL_CAP_HSS_MASK (0x200000U) +#define USDHC_HOST_CTRL_CAP_HSS_SHIFT (21U) +/*! HSS - High Speed Support + * 0b1..High Speed Supported + * 0b0..High Speed Not Supported + */ +#define USDHC_HOST_CTRL_CAP_HSS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_HSS_SHIFT)) & USDHC_HOST_CTRL_CAP_HSS_MASK) +#define USDHC_HOST_CTRL_CAP_DMAS_MASK (0x400000U) +#define USDHC_HOST_CTRL_CAP_DMAS_SHIFT (22U) +/*! DMAS - DMA Support + * 0b1..DMA Supported + * 0b0..DMA not supported + */ +#define USDHC_HOST_CTRL_CAP_DMAS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_DMAS_SHIFT)) & USDHC_HOST_CTRL_CAP_DMAS_MASK) +#define USDHC_HOST_CTRL_CAP_SRS_MASK (0x800000U) +#define USDHC_HOST_CTRL_CAP_SRS_SHIFT (23U) +/*! SRS - Suspend / Resume Support + * 0b1..Supported + * 0b0..Not supported + */ +#define USDHC_HOST_CTRL_CAP_SRS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_SRS_SHIFT)) & USDHC_HOST_CTRL_CAP_SRS_MASK) +#define USDHC_HOST_CTRL_CAP_VS33_MASK (0x1000000U) +#define USDHC_HOST_CTRL_CAP_VS33_SHIFT (24U) +/*! VS33 - Voltage Support 3.3V + * 0b1..3.3V supported + * 0b0..3.3V not supported + */ +#define USDHC_HOST_CTRL_CAP_VS33(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_VS33_SHIFT)) & USDHC_HOST_CTRL_CAP_VS33_MASK) +#define USDHC_HOST_CTRL_CAP_VS30_MASK (0x2000000U) +#define USDHC_HOST_CTRL_CAP_VS30_SHIFT (25U) +/*! VS30 - Voltage Support 3.0 V + * 0b1..3.0V supported + * 0b0..3.0V not supported + */ +#define USDHC_HOST_CTRL_CAP_VS30(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_VS30_SHIFT)) & USDHC_HOST_CTRL_CAP_VS30_MASK) +#define USDHC_HOST_CTRL_CAP_VS18_MASK (0x4000000U) +#define USDHC_HOST_CTRL_CAP_VS18_SHIFT (26U) +/*! VS18 - Voltage Support 1.8 V + * 0b1..1.8V supported + * 0b0..1.8V not supported + */ +#define USDHC_HOST_CTRL_CAP_VS18(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_VS18_SHIFT)) & USDHC_HOST_CTRL_CAP_VS18_MASK) +/*! @} */ + +/*! @name WTMK_LVL - Watermark Level */ +/*! @{ */ +#define USDHC_WTMK_LVL_RD_WML_MASK (0xFFU) +#define USDHC_WTMK_LVL_RD_WML_SHIFT (0U) +#define USDHC_WTMK_LVL_RD_WML(x) (((uint32_t)(((uint32_t)(x)) << USDHC_WTMK_LVL_RD_WML_SHIFT)) & USDHC_WTMK_LVL_RD_WML_MASK) +#define USDHC_WTMK_LVL_RD_BRST_LEN_MASK (0x1F00U) +#define USDHC_WTMK_LVL_RD_BRST_LEN_SHIFT (8U) +#define USDHC_WTMK_LVL_RD_BRST_LEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_WTMK_LVL_RD_BRST_LEN_SHIFT)) & USDHC_WTMK_LVL_RD_BRST_LEN_MASK) +#define USDHC_WTMK_LVL_WR_WML_MASK (0xFF0000U) +#define USDHC_WTMK_LVL_WR_WML_SHIFT (16U) +#define USDHC_WTMK_LVL_WR_WML(x) (((uint32_t)(((uint32_t)(x)) << USDHC_WTMK_LVL_WR_WML_SHIFT)) & USDHC_WTMK_LVL_WR_WML_MASK) +#define USDHC_WTMK_LVL_WR_BRST_LEN_MASK (0x1F000000U) +#define USDHC_WTMK_LVL_WR_BRST_LEN_SHIFT (24U) +#define USDHC_WTMK_LVL_WR_BRST_LEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_WTMK_LVL_WR_BRST_LEN_SHIFT)) & USDHC_WTMK_LVL_WR_BRST_LEN_MASK) +/*! @} */ + +/*! @name MIX_CTRL - Mixer Control */ +/*! @{ */ +#define USDHC_MIX_CTRL_DMAEN_MASK (0x1U) +#define USDHC_MIX_CTRL_DMAEN_SHIFT (0U) +/*! DMAEN - DMA Enable + * 0b1..Enable + * 0b0..Disable + */ +#define USDHC_MIX_CTRL_DMAEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_DMAEN_SHIFT)) & USDHC_MIX_CTRL_DMAEN_MASK) +#define USDHC_MIX_CTRL_BCEN_MASK (0x2U) +#define USDHC_MIX_CTRL_BCEN_SHIFT (1U) +/*! BCEN - Block Count Enable + * 0b1..Enable + * 0b0..Disable + */ +#define USDHC_MIX_CTRL_BCEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_BCEN_SHIFT)) & USDHC_MIX_CTRL_BCEN_MASK) +#define USDHC_MIX_CTRL_AC12EN_MASK (0x4U) +#define USDHC_MIX_CTRL_AC12EN_SHIFT (2U) +/*! AC12EN - Auto CMD12 Enable + * 0b1..Enable + * 0b0..Disable + */ +#define USDHC_MIX_CTRL_AC12EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_AC12EN_SHIFT)) & USDHC_MIX_CTRL_AC12EN_MASK) +#define USDHC_MIX_CTRL_DDR_EN_MASK (0x8U) +#define USDHC_MIX_CTRL_DDR_EN_SHIFT (3U) +#define USDHC_MIX_CTRL_DDR_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_DDR_EN_SHIFT)) & USDHC_MIX_CTRL_DDR_EN_MASK) +#define USDHC_MIX_CTRL_DTDSEL_MASK (0x10U) +#define USDHC_MIX_CTRL_DTDSEL_SHIFT (4U) +/*! DTDSEL - Data Transfer Direction Select + * 0b1..Read (Card to Host) + * 0b0..Write (Host to Card) + */ +#define USDHC_MIX_CTRL_DTDSEL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_DTDSEL_SHIFT)) & USDHC_MIX_CTRL_DTDSEL_MASK) +#define USDHC_MIX_CTRL_MSBSEL_MASK (0x20U) +#define USDHC_MIX_CTRL_MSBSEL_SHIFT (5U) +/*! MSBSEL - Multi / Single Block Select + * 0b1..Multiple Blocks + * 0b0..Single Block + */ +#define USDHC_MIX_CTRL_MSBSEL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_MSBSEL_SHIFT)) & USDHC_MIX_CTRL_MSBSEL_MASK) +#define USDHC_MIX_CTRL_NIBBLE_POS_MASK (0x40U) +#define USDHC_MIX_CTRL_NIBBLE_POS_SHIFT (6U) +#define USDHC_MIX_CTRL_NIBBLE_POS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_NIBBLE_POS_SHIFT)) & USDHC_MIX_CTRL_NIBBLE_POS_MASK) +#define USDHC_MIX_CTRL_AC23EN_MASK (0x80U) +#define USDHC_MIX_CTRL_AC23EN_SHIFT (7U) +#define USDHC_MIX_CTRL_AC23EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_AC23EN_SHIFT)) & USDHC_MIX_CTRL_AC23EN_MASK) +#define USDHC_MIX_CTRL_EXE_TUNE_MASK (0x400000U) +#define USDHC_MIX_CTRL_EXE_TUNE_SHIFT (22U) +/*! EXE_TUNE - Execute Tuning: (Only used for SD3.0, SDR104 mode and EMMC HS200 mode) + * 0b1..Execute Tuning + * 0b0..Not Tuned or Tuning Completed + */ +#define USDHC_MIX_CTRL_EXE_TUNE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_EXE_TUNE_SHIFT)) & USDHC_MIX_CTRL_EXE_TUNE_MASK) +#define USDHC_MIX_CTRL_SMP_CLK_SEL_MASK (0x800000U) +#define USDHC_MIX_CTRL_SMP_CLK_SEL_SHIFT (23U) +/*! SMP_CLK_SEL - SMP_CLK_SEL + * 0b1..Tuned clock is used to sample data / cmd + * 0b0..Fixed clock is used to sample data / cmd + */ +#define USDHC_MIX_CTRL_SMP_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_SMP_CLK_SEL_SHIFT)) & USDHC_MIX_CTRL_SMP_CLK_SEL_MASK) +#define USDHC_MIX_CTRL_AUTO_TUNE_EN_MASK (0x1000000U) +#define USDHC_MIX_CTRL_AUTO_TUNE_EN_SHIFT (24U) +/*! AUTO_TUNE_EN - Auto Tuning Enable (Only used for SD3.0, SDR104 mode and and EMMC HS200 mode) + * 0b1..Enable auto tuning + * 0b0..Disable auto tuning + */ +#define USDHC_MIX_CTRL_AUTO_TUNE_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_AUTO_TUNE_EN_SHIFT)) & USDHC_MIX_CTRL_AUTO_TUNE_EN_MASK) +#define USDHC_MIX_CTRL_FBCLK_SEL_MASK (0x2000000U) +#define USDHC_MIX_CTRL_FBCLK_SEL_SHIFT (25U) +/*! FBCLK_SEL - Feedback Clock Source Selection (Only used for SD3.0, SDR104 mode and EMMC HS200 mode) + * 0b1..Feedback clock comes from the ipp_card_clk_out + * 0b0..Feedback clock comes from the loopback CLK + */ +#define USDHC_MIX_CTRL_FBCLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_FBCLK_SEL_SHIFT)) & USDHC_MIX_CTRL_FBCLK_SEL_MASK) +/*! @} */ + +/*! @name FORCE_EVENT - Force Event */ +/*! @{ */ +#define USDHC_FORCE_EVENT_FEVTAC12NE_MASK (0x1U) +#define USDHC_FORCE_EVENT_FEVTAC12NE_SHIFT (0U) +#define USDHC_FORCE_EVENT_FEVTAC12NE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTAC12NE_SHIFT)) & USDHC_FORCE_EVENT_FEVTAC12NE_MASK) +#define USDHC_FORCE_EVENT_FEVTAC12TOE_MASK (0x2U) +#define USDHC_FORCE_EVENT_FEVTAC12TOE_SHIFT (1U) +#define USDHC_FORCE_EVENT_FEVTAC12TOE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTAC12TOE_SHIFT)) & USDHC_FORCE_EVENT_FEVTAC12TOE_MASK) +#define USDHC_FORCE_EVENT_FEVTAC12CE_MASK (0x4U) +#define USDHC_FORCE_EVENT_FEVTAC12CE_SHIFT (2U) +#define USDHC_FORCE_EVENT_FEVTAC12CE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTAC12CE_SHIFT)) & USDHC_FORCE_EVENT_FEVTAC12CE_MASK) +#define USDHC_FORCE_EVENT_FEVTAC12EBE_MASK (0x8U) +#define USDHC_FORCE_EVENT_FEVTAC12EBE_SHIFT (3U) +#define USDHC_FORCE_EVENT_FEVTAC12EBE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTAC12EBE_SHIFT)) & USDHC_FORCE_EVENT_FEVTAC12EBE_MASK) +#define USDHC_FORCE_EVENT_FEVTAC12IE_MASK (0x10U) +#define USDHC_FORCE_EVENT_FEVTAC12IE_SHIFT (4U) +#define USDHC_FORCE_EVENT_FEVTAC12IE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTAC12IE_SHIFT)) & USDHC_FORCE_EVENT_FEVTAC12IE_MASK) +#define USDHC_FORCE_EVENT_FEVTCNIBAC12E_MASK (0x80U) +#define USDHC_FORCE_EVENT_FEVTCNIBAC12E_SHIFT (7U) +#define USDHC_FORCE_EVENT_FEVTCNIBAC12E(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTCNIBAC12E_SHIFT)) & USDHC_FORCE_EVENT_FEVTCNIBAC12E_MASK) +#define USDHC_FORCE_EVENT_FEVTCTOE_MASK (0x10000U) +#define USDHC_FORCE_EVENT_FEVTCTOE_SHIFT (16U) +#define USDHC_FORCE_EVENT_FEVTCTOE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTCTOE_SHIFT)) & USDHC_FORCE_EVENT_FEVTCTOE_MASK) +#define USDHC_FORCE_EVENT_FEVTCCE_MASK (0x20000U) +#define USDHC_FORCE_EVENT_FEVTCCE_SHIFT (17U) +#define USDHC_FORCE_EVENT_FEVTCCE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTCCE_SHIFT)) & USDHC_FORCE_EVENT_FEVTCCE_MASK) +#define USDHC_FORCE_EVENT_FEVTCEBE_MASK (0x40000U) +#define USDHC_FORCE_EVENT_FEVTCEBE_SHIFT (18U) +#define USDHC_FORCE_EVENT_FEVTCEBE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTCEBE_SHIFT)) & USDHC_FORCE_EVENT_FEVTCEBE_MASK) +#define USDHC_FORCE_EVENT_FEVTCIE_MASK (0x80000U) +#define USDHC_FORCE_EVENT_FEVTCIE_SHIFT (19U) +#define USDHC_FORCE_EVENT_FEVTCIE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTCIE_SHIFT)) & USDHC_FORCE_EVENT_FEVTCIE_MASK) +#define USDHC_FORCE_EVENT_FEVTDTOE_MASK (0x100000U) +#define USDHC_FORCE_EVENT_FEVTDTOE_SHIFT (20U) +#define USDHC_FORCE_EVENT_FEVTDTOE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTDTOE_SHIFT)) & USDHC_FORCE_EVENT_FEVTDTOE_MASK) +#define USDHC_FORCE_EVENT_FEVTDCE_MASK (0x200000U) +#define USDHC_FORCE_EVENT_FEVTDCE_SHIFT (21U) +#define USDHC_FORCE_EVENT_FEVTDCE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTDCE_SHIFT)) & USDHC_FORCE_EVENT_FEVTDCE_MASK) +#define USDHC_FORCE_EVENT_FEVTDEBE_MASK (0x400000U) +#define USDHC_FORCE_EVENT_FEVTDEBE_SHIFT (22U) +#define USDHC_FORCE_EVENT_FEVTDEBE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTDEBE_SHIFT)) & USDHC_FORCE_EVENT_FEVTDEBE_MASK) +#define USDHC_FORCE_EVENT_FEVTAC12E_MASK (0x1000000U) +#define USDHC_FORCE_EVENT_FEVTAC12E_SHIFT (24U) +#define USDHC_FORCE_EVENT_FEVTAC12E(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTAC12E_SHIFT)) & USDHC_FORCE_EVENT_FEVTAC12E_MASK) +#define USDHC_FORCE_EVENT_FEVTTNE_MASK (0x4000000U) +#define USDHC_FORCE_EVENT_FEVTTNE_SHIFT (26U) +#define USDHC_FORCE_EVENT_FEVTTNE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTTNE_SHIFT)) & USDHC_FORCE_EVENT_FEVTTNE_MASK) +#define USDHC_FORCE_EVENT_FEVTDMAE_MASK (0x10000000U) +#define USDHC_FORCE_EVENT_FEVTDMAE_SHIFT (28U) +#define USDHC_FORCE_EVENT_FEVTDMAE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTDMAE_SHIFT)) & USDHC_FORCE_EVENT_FEVTDMAE_MASK) +#define USDHC_FORCE_EVENT_FEVTCINT_MASK (0x80000000U) +#define USDHC_FORCE_EVENT_FEVTCINT_SHIFT (31U) +#define USDHC_FORCE_EVENT_FEVTCINT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTCINT_SHIFT)) & USDHC_FORCE_EVENT_FEVTCINT_MASK) +/*! @} */ + +/*! @name ADMA_ERR_STATUS - ADMA Error Status Register */ +/*! @{ */ +#define USDHC_ADMA_ERR_STATUS_ADMAES_MASK (0x3U) +#define USDHC_ADMA_ERR_STATUS_ADMAES_SHIFT (0U) +#define USDHC_ADMA_ERR_STATUS_ADMAES(x) (((uint32_t)(((uint32_t)(x)) << USDHC_ADMA_ERR_STATUS_ADMAES_SHIFT)) & USDHC_ADMA_ERR_STATUS_ADMAES_MASK) +#define USDHC_ADMA_ERR_STATUS_ADMALME_MASK (0x4U) +#define USDHC_ADMA_ERR_STATUS_ADMALME_SHIFT (2U) +/*! ADMALME - ADMA Length Mismatch Error + * 0b1..Error + * 0b0..No Error + */ +#define USDHC_ADMA_ERR_STATUS_ADMALME(x) (((uint32_t)(((uint32_t)(x)) << USDHC_ADMA_ERR_STATUS_ADMALME_SHIFT)) & USDHC_ADMA_ERR_STATUS_ADMALME_MASK) +#define USDHC_ADMA_ERR_STATUS_ADMADCE_MASK (0x8U) +#define USDHC_ADMA_ERR_STATUS_ADMADCE_SHIFT (3U) +/*! ADMADCE - ADMA Descriptor Error + * 0b1..Error + * 0b0..No Error + */ +#define USDHC_ADMA_ERR_STATUS_ADMADCE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_ADMA_ERR_STATUS_ADMADCE_SHIFT)) & USDHC_ADMA_ERR_STATUS_ADMADCE_MASK) +/*! @} */ + +/*! @name ADMA_SYS_ADDR - ADMA System Address */ +/*! @{ */ +#define USDHC_ADMA_SYS_ADDR_ADS_ADDR_MASK (0xFFFFFFFCU) +#define USDHC_ADMA_SYS_ADDR_ADS_ADDR_SHIFT (2U) +#define USDHC_ADMA_SYS_ADDR_ADS_ADDR(x) (((uint32_t)(((uint32_t)(x)) << USDHC_ADMA_SYS_ADDR_ADS_ADDR_SHIFT)) & USDHC_ADMA_SYS_ADDR_ADS_ADDR_MASK) +/*! @} */ + +/*! @name DLL_CTRL - DLL (Delay Line) Control */ +/*! @{ */ +#define USDHC_DLL_CTRL_DLL_CTRL_ENABLE_MASK (0x1U) +#define USDHC_DLL_CTRL_DLL_CTRL_ENABLE_SHIFT (0U) +#define USDHC_DLL_CTRL_DLL_CTRL_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_ENABLE_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_ENABLE_MASK) +#define USDHC_DLL_CTRL_DLL_CTRL_RESET_MASK (0x2U) +#define USDHC_DLL_CTRL_DLL_CTRL_RESET_SHIFT (1U) +#define USDHC_DLL_CTRL_DLL_CTRL_RESET(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_RESET_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_RESET_MASK) +#define USDHC_DLL_CTRL_DLL_CTRL_SLV_FORCE_UPD_MASK (0x4U) +#define USDHC_DLL_CTRL_DLL_CTRL_SLV_FORCE_UPD_SHIFT (2U) +#define USDHC_DLL_CTRL_DLL_CTRL_SLV_FORCE_UPD(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_SLV_FORCE_UPD_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_SLV_FORCE_UPD_MASK) +#define USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET0_MASK (0x78U) +#define USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET0_SHIFT (3U) +#define USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET0(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET0_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET0_MASK) +#define USDHC_DLL_CTRL_DLL_CTRL_GATE_UPDATE_MASK (0x80U) +#define USDHC_DLL_CTRL_DLL_CTRL_GATE_UPDATE_SHIFT (7U) +#define USDHC_DLL_CTRL_DLL_CTRL_GATE_UPDATE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_GATE_UPDATE_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_GATE_UPDATE_MASK) +#define USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_MASK (0x100U) +#define USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_SHIFT (8U) +#define USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_MASK) +#define USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_VAL_MASK (0xFE00U) +#define USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_VAL_SHIFT (9U) +#define USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_VAL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_VAL_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_VAL_MASK) +#define USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET1_MASK (0x70000U) +#define USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET1_SHIFT (16U) +#define USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET1(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET1_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET1_MASK) +#define USDHC_DLL_CTRL_DLL_CTRL_SLV_UPDATE_INT_MASK (0xFF00000U) +#define USDHC_DLL_CTRL_DLL_CTRL_SLV_UPDATE_INT_SHIFT (20U) +#define USDHC_DLL_CTRL_DLL_CTRL_SLV_UPDATE_INT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_SLV_UPDATE_INT_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_SLV_UPDATE_INT_MASK) +#define USDHC_DLL_CTRL_DLL_CTRL_REF_UPDATE_INT_MASK (0xF0000000U) +#define USDHC_DLL_CTRL_DLL_CTRL_REF_UPDATE_INT_SHIFT (28U) +#define USDHC_DLL_CTRL_DLL_CTRL_REF_UPDATE_INT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_REF_UPDATE_INT_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_REF_UPDATE_INT_MASK) +/*! @} */ + +/*! @name DLL_STATUS - DLL Status */ +/*! @{ */ +#define USDHC_DLL_STATUS_DLL_STS_SLV_LOCK_MASK (0x1U) +#define USDHC_DLL_STATUS_DLL_STS_SLV_LOCK_SHIFT (0U) +#define USDHC_DLL_STATUS_DLL_STS_SLV_LOCK(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_STATUS_DLL_STS_SLV_LOCK_SHIFT)) & USDHC_DLL_STATUS_DLL_STS_SLV_LOCK_MASK) +#define USDHC_DLL_STATUS_DLL_STS_REF_LOCK_MASK (0x2U) +#define USDHC_DLL_STATUS_DLL_STS_REF_LOCK_SHIFT (1U) +#define USDHC_DLL_STATUS_DLL_STS_REF_LOCK(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_STATUS_DLL_STS_REF_LOCK_SHIFT)) & USDHC_DLL_STATUS_DLL_STS_REF_LOCK_MASK) +#define USDHC_DLL_STATUS_DLL_STS_SLV_SEL_MASK (0x1FCU) +#define USDHC_DLL_STATUS_DLL_STS_SLV_SEL_SHIFT (2U) +#define USDHC_DLL_STATUS_DLL_STS_SLV_SEL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_STATUS_DLL_STS_SLV_SEL_SHIFT)) & USDHC_DLL_STATUS_DLL_STS_SLV_SEL_MASK) +#define USDHC_DLL_STATUS_DLL_STS_REF_SEL_MASK (0xFE00U) +#define USDHC_DLL_STATUS_DLL_STS_REF_SEL_SHIFT (9U) +#define USDHC_DLL_STATUS_DLL_STS_REF_SEL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_STATUS_DLL_STS_REF_SEL_SHIFT)) & USDHC_DLL_STATUS_DLL_STS_REF_SEL_MASK) +/*! @} */ + +/*! @name CLK_TUNE_CTRL_STATUS - CLK Tuning Control and Status */ +/*! @{ */ +#define USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_POST_MASK (0xFU) +#define USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_POST_SHIFT (0U) +#define USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_POST(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_POST_SHIFT)) & USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_POST_MASK) +#define USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_OUT_MASK (0xF0U) +#define USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_OUT_SHIFT (4U) +#define USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_OUT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_OUT_SHIFT)) & USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_OUT_MASK) +#define USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_PRE_MASK (0x7F00U) +#define USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_PRE_SHIFT (8U) +#define USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_PRE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_PRE_SHIFT)) & USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_PRE_MASK) +#define USDHC_CLK_TUNE_CTRL_STATUS_NXT_ERR_MASK (0x8000U) +#define USDHC_CLK_TUNE_CTRL_STATUS_NXT_ERR_SHIFT (15U) +#define USDHC_CLK_TUNE_CTRL_STATUS_NXT_ERR(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CLK_TUNE_CTRL_STATUS_NXT_ERR_SHIFT)) & USDHC_CLK_TUNE_CTRL_STATUS_NXT_ERR_MASK) +#define USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_POST_MASK (0xF0000U) +#define USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_POST_SHIFT (16U) +#define USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_POST(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_POST_SHIFT)) & USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_POST_MASK) +#define USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_OUT_MASK (0xF00000U) +#define USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_OUT_SHIFT (20U) +#define USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_OUT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_OUT_SHIFT)) & USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_OUT_MASK) +#define USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_PRE_MASK (0x7F000000U) +#define USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_PRE_SHIFT (24U) +#define USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_PRE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_PRE_SHIFT)) & USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_PRE_MASK) +#define USDHC_CLK_TUNE_CTRL_STATUS_PRE_ERR_MASK (0x80000000U) +#define USDHC_CLK_TUNE_CTRL_STATUS_PRE_ERR_SHIFT (31U) +#define USDHC_CLK_TUNE_CTRL_STATUS_PRE_ERR(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CLK_TUNE_CTRL_STATUS_PRE_ERR_SHIFT)) & USDHC_CLK_TUNE_CTRL_STATUS_PRE_ERR_MASK) +/*! @} */ + +/*! @name VEND_SPEC - Vendor Specific Register */ +/*! @{ */ +#define USDHC_VEND_SPEC_VSELECT_MASK (0x2U) +#define USDHC_VEND_SPEC_VSELECT_SHIFT (1U) +/*! VSELECT - Voltage Selection + * 0b1..Change the voltage to low voltage range, around 1.8 V + * 0b0..Change the voltage to high voltage range, around 3.0 V + */ +#define USDHC_VEND_SPEC_VSELECT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC_VSELECT_SHIFT)) & USDHC_VEND_SPEC_VSELECT_MASK) +#define USDHC_VEND_SPEC_CONFLICT_CHK_EN_MASK (0x4U) +#define USDHC_VEND_SPEC_CONFLICT_CHK_EN_SHIFT (2U) +/*! CONFLICT_CHK_EN - Conflict check enable. + * 0b0..Conflict check disable + * 0b1..Conflict check enable + */ +#define USDHC_VEND_SPEC_CONFLICT_CHK_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC_CONFLICT_CHK_EN_SHIFT)) & USDHC_VEND_SPEC_CONFLICT_CHK_EN_MASK) +#define USDHC_VEND_SPEC_AC12_WR_CHKBUSY_EN_MASK (0x8U) +#define USDHC_VEND_SPEC_AC12_WR_CHKBUSY_EN_SHIFT (3U) +/*! AC12_WR_CHKBUSY_EN - AC12_WR_CHKBUSY_EN + * 0b0..Do not check busy after auto CMD12 for write data packet + * 0b1..Check busy after auto CMD12 for write data packet + */ +#define USDHC_VEND_SPEC_AC12_WR_CHKBUSY_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC_AC12_WR_CHKBUSY_EN_SHIFT)) & USDHC_VEND_SPEC_AC12_WR_CHKBUSY_EN_MASK) +#define USDHC_VEND_SPEC_FRC_SDCLK_ON_MASK (0x100U) +#define USDHC_VEND_SPEC_FRC_SDCLK_ON_SHIFT (8U) +/*! FRC_SDCLK_ON - FRC_SDCLK_ON + * 0b0..CLK active or inactive is fully controlled by the hardware. + * 0b1..Force CLK active. + */ +#define USDHC_VEND_SPEC_FRC_SDCLK_ON(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC_FRC_SDCLK_ON_SHIFT)) & USDHC_VEND_SPEC_FRC_SDCLK_ON_MASK) +#define USDHC_VEND_SPEC_CRC_CHK_DIS_MASK (0x8000U) +#define USDHC_VEND_SPEC_CRC_CHK_DIS_SHIFT (15U) +/*! CRC_CHK_DIS - CRC Check Disable + * 0b0..Check CRC16 for every read data packet and check CRC bits for every write data packet + * 0b1..Ignore CRC16 check for every read data packet and ignore CRC bits check for every write data packet + */ +#define USDHC_VEND_SPEC_CRC_CHK_DIS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC_CRC_CHK_DIS_SHIFT)) & USDHC_VEND_SPEC_CRC_CHK_DIS_MASK) +#define USDHC_VEND_SPEC_CMD_BYTE_EN_MASK (0x80000000U) +#define USDHC_VEND_SPEC_CMD_BYTE_EN_SHIFT (31U) +/*! CMD_BYTE_EN - CMD_BYTE_EN + * 0b0..Disable + * 0b1..Enable + */ +#define USDHC_VEND_SPEC_CMD_BYTE_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC_CMD_BYTE_EN_SHIFT)) & USDHC_VEND_SPEC_CMD_BYTE_EN_MASK) +/*! @} */ + +/*! @name MMC_BOOT - MMC Boot Register */ +/*! @{ */ +#define USDHC_MMC_BOOT_DTOCV_ACK_MASK (0xFU) +#define USDHC_MMC_BOOT_DTOCV_ACK_SHIFT (0U) +/*! DTOCV_ACK - DTOCV_ACK + * 0b0000..SDCLK x 2^14 + * 0b0001..SDCLK x 2^15 + * 0b0010..SDCLK x 2^16 + * 0b0011..SDCLK x 2^17 + * 0b0100..SDCLK x 2^18 + * 0b0101..SDCLK x 2^19 + * 0b0110..SDCLK x 2^20 + * 0b0111..SDCLK x 2^21 + * 0b1110..SDCLK x 2^28 + * 0b1111..SDCLK x 2^29 + */ +#define USDHC_MMC_BOOT_DTOCV_ACK(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MMC_BOOT_DTOCV_ACK_SHIFT)) & USDHC_MMC_BOOT_DTOCV_ACK_MASK) +#define USDHC_MMC_BOOT_BOOT_ACK_MASK (0x10U) +#define USDHC_MMC_BOOT_BOOT_ACK_SHIFT (4U) +/*! BOOT_ACK - BOOT_ACK + * 0b0..No ack + * 0b1..Ack + */ +#define USDHC_MMC_BOOT_BOOT_ACK(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MMC_BOOT_BOOT_ACK_SHIFT)) & USDHC_MMC_BOOT_BOOT_ACK_MASK) +#define USDHC_MMC_BOOT_BOOT_MODE_MASK (0x20U) +#define USDHC_MMC_BOOT_BOOT_MODE_SHIFT (5U) +/*! BOOT_MODE - BOOT_MODE + * 0b0..Normal boot + * 0b1..Alternative boot + */ +#define USDHC_MMC_BOOT_BOOT_MODE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MMC_BOOT_BOOT_MODE_SHIFT)) & USDHC_MMC_BOOT_BOOT_MODE_MASK) +#define USDHC_MMC_BOOT_BOOT_EN_MASK (0x40U) +#define USDHC_MMC_BOOT_BOOT_EN_SHIFT (6U) +/*! BOOT_EN - BOOT_EN + * 0b0..Fast boot disable + * 0b1..Fast boot enable + */ +#define USDHC_MMC_BOOT_BOOT_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MMC_BOOT_BOOT_EN_SHIFT)) & USDHC_MMC_BOOT_BOOT_EN_MASK) +#define USDHC_MMC_BOOT_AUTO_SABG_EN_MASK (0x80U) +#define USDHC_MMC_BOOT_AUTO_SABG_EN_SHIFT (7U) +#define USDHC_MMC_BOOT_AUTO_SABG_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MMC_BOOT_AUTO_SABG_EN_SHIFT)) & USDHC_MMC_BOOT_AUTO_SABG_EN_MASK) +#define USDHC_MMC_BOOT_DISABLE_TIME_OUT_MASK (0x100U) +#define USDHC_MMC_BOOT_DISABLE_TIME_OUT_SHIFT (8U) +/*! DISABLE_TIME_OUT - Disable Time Out + * 0b0..Enable time out + * 0b1..Disable time out + */ +#define USDHC_MMC_BOOT_DISABLE_TIME_OUT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MMC_BOOT_DISABLE_TIME_OUT_SHIFT)) & USDHC_MMC_BOOT_DISABLE_TIME_OUT_MASK) +#define USDHC_MMC_BOOT_BOOT_BLK_CNT_MASK (0xFFFF0000U) +#define USDHC_MMC_BOOT_BOOT_BLK_CNT_SHIFT (16U) +#define USDHC_MMC_BOOT_BOOT_BLK_CNT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MMC_BOOT_BOOT_BLK_CNT_SHIFT)) & USDHC_MMC_BOOT_BOOT_BLK_CNT_MASK) +/*! @} */ + +/*! @name VEND_SPEC2 - Vendor Specific 2 Register */ +/*! @{ */ +#define USDHC_VEND_SPEC2_CARD_INT_D3_TEST_MASK (0x8U) +#define USDHC_VEND_SPEC2_CARD_INT_D3_TEST_SHIFT (3U) +/*! CARD_INT_D3_TEST - Card Interrupt Detection Test + * 0b0..Check the card interrupt only when DATA3 is high. + * 0b1..Check the card interrupt by ignoring the status of DATA3. + */ +#define USDHC_VEND_SPEC2_CARD_INT_D3_TEST(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC2_CARD_INT_D3_TEST_SHIFT)) & USDHC_VEND_SPEC2_CARD_INT_D3_TEST_MASK) +#define USDHC_VEND_SPEC2_TUNING_8bit_EN_MASK (0x10U) +#define USDHC_VEND_SPEC2_TUNING_8bit_EN_SHIFT (4U) +#define USDHC_VEND_SPEC2_TUNING_8bit_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC2_TUNING_8bit_EN_SHIFT)) & USDHC_VEND_SPEC2_TUNING_8bit_EN_MASK) +#define USDHC_VEND_SPEC2_TUNING_1bit_EN_MASK (0x20U) +#define USDHC_VEND_SPEC2_TUNING_1bit_EN_SHIFT (5U) +#define USDHC_VEND_SPEC2_TUNING_1bit_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC2_TUNING_1bit_EN_SHIFT)) & USDHC_VEND_SPEC2_TUNING_1bit_EN_MASK) +#define USDHC_VEND_SPEC2_TUNING_CMD_EN_MASK (0x40U) +#define USDHC_VEND_SPEC2_TUNING_CMD_EN_SHIFT (6U) +/*! TUNING_CMD_EN - TUNING_CMD_EN + * 0b0..Auto tuning circuit does not check the CMD line. + * 0b1..Auto tuning circuit checks the CMD line. + */ +#define USDHC_VEND_SPEC2_TUNING_CMD_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC2_TUNING_CMD_EN_SHIFT)) & USDHC_VEND_SPEC2_TUNING_CMD_EN_MASK) +#define USDHC_VEND_SPEC2_ACMD23_ARGU2_EN_MASK (0x1000U) +#define USDHC_VEND_SPEC2_ACMD23_ARGU2_EN_SHIFT (12U) +/*! ACMD23_ARGU2_EN - Argument2 register enable for ACMD23 + * 0b1..Argument2 register enable for ACMD23 sharing with SDMA system address register. Default is enable. + * 0b0..Disable + */ +#define USDHC_VEND_SPEC2_ACMD23_ARGU2_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC2_ACMD23_ARGU2_EN_SHIFT)) & USDHC_VEND_SPEC2_ACMD23_ARGU2_EN_MASK) +#define USDHC_VEND_SPEC2_PART_DLL_DEBUG_MASK (0x2000U) +#define USDHC_VEND_SPEC2_PART_DLL_DEBUG_SHIFT (13U) +#define USDHC_VEND_SPEC2_PART_DLL_DEBUG(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC2_PART_DLL_DEBUG_SHIFT)) & USDHC_VEND_SPEC2_PART_DLL_DEBUG_MASK) +#define USDHC_VEND_SPEC2_BUS_RST_MASK (0x4000U) +#define USDHC_VEND_SPEC2_BUS_RST_SHIFT (14U) +#define USDHC_VEND_SPEC2_BUS_RST(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC2_BUS_RST_SHIFT)) & USDHC_VEND_SPEC2_BUS_RST_MASK) +/*! @} */ + +/*! @name TUNING_CTRL - Tuning Control Register */ +/*! @{ */ +#define USDHC_TUNING_CTRL_TUNING_START_TAP_MASK (0xFFU) +#define USDHC_TUNING_CTRL_TUNING_START_TAP_SHIFT (0U) +#define USDHC_TUNING_CTRL_TUNING_START_TAP(x) (((uint32_t)(((uint32_t)(x)) << USDHC_TUNING_CTRL_TUNING_START_TAP_SHIFT)) & USDHC_TUNING_CTRL_TUNING_START_TAP_MASK) +#define USDHC_TUNING_CTRL_TUNING_COUNTER_MASK (0xFF00U) +#define USDHC_TUNING_CTRL_TUNING_COUNTER_SHIFT (8U) +#define USDHC_TUNING_CTRL_TUNING_COUNTER(x) (((uint32_t)(((uint32_t)(x)) << USDHC_TUNING_CTRL_TUNING_COUNTER_SHIFT)) & USDHC_TUNING_CTRL_TUNING_COUNTER_MASK) +#define USDHC_TUNING_CTRL_TUNING_STEP_MASK (0x70000U) +#define USDHC_TUNING_CTRL_TUNING_STEP_SHIFT (16U) +#define USDHC_TUNING_CTRL_TUNING_STEP(x) (((uint32_t)(((uint32_t)(x)) << USDHC_TUNING_CTRL_TUNING_STEP_SHIFT)) & USDHC_TUNING_CTRL_TUNING_STEP_MASK) +#define USDHC_TUNING_CTRL_TUNING_WINDOW_MASK (0x700000U) +#define USDHC_TUNING_CTRL_TUNING_WINDOW_SHIFT (20U) +#define USDHC_TUNING_CTRL_TUNING_WINDOW(x) (((uint32_t)(((uint32_t)(x)) << USDHC_TUNING_CTRL_TUNING_WINDOW_SHIFT)) & USDHC_TUNING_CTRL_TUNING_WINDOW_MASK) +#define USDHC_TUNING_CTRL_STD_TUNING_EN_MASK (0x1000000U) +#define USDHC_TUNING_CTRL_STD_TUNING_EN_SHIFT (24U) +#define USDHC_TUNING_CTRL_STD_TUNING_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_TUNING_CTRL_STD_TUNING_EN_SHIFT)) & USDHC_TUNING_CTRL_STD_TUNING_EN_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group USDHC_Register_Masks */ + + +/* USDHC - Peripheral instance base addresses */ +/** Peripheral USDHC1 base address */ +#define USDHC1_BASE (0x402C0000u) +/** Peripheral USDHC1 base pointer */ +#define USDHC1 ((USDHC_Type *)USDHC1_BASE) +/** Peripheral USDHC2 base address */ +#define USDHC2_BASE (0x402C4000u) +/** Peripheral USDHC2 base pointer */ +#define USDHC2 ((USDHC_Type *)USDHC2_BASE) +/** Array initializer of USDHC peripheral base addresses */ +#define USDHC_BASE_ADDRS { 0u, USDHC1_BASE, USDHC2_BASE } +/** Array initializer of USDHC peripheral base pointers */ +#define USDHC_BASE_PTRS { (USDHC_Type *)0u, USDHC1, USDHC2 } +/** Interrupt vectors for the USDHC peripheral type */ +#define USDHC_IRQS { NotAvail_IRQn, USDHC1_IRQn, USDHC2_IRQn } + +/*! + * @} + */ /* end of group USDHC_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- WDOG Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup WDOG_Peripheral_Access_Layer WDOG Peripheral Access Layer + * @{ + */ + +/** WDOG - Register Layout Typedef */ +typedef struct { + __IO uint16_t WCR; /**< Watchdog Control Register, offset: 0x0 */ + __IO uint16_t WSR; /**< Watchdog Service Register, offset: 0x2 */ + __I uint16_t WRSR; /**< Watchdog Reset Status Register, offset: 0x4 */ + __IO uint16_t WICR; /**< Watchdog Interrupt Control Register, offset: 0x6 */ + __IO uint16_t WMCR; /**< Watchdog Miscellaneous Control Register, offset: 0x8 */ +} WDOG_Type; + +/* ---------------------------------------------------------------------------- + -- WDOG Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup WDOG_Register_Masks WDOG Register Masks + * @{ + */ + +/*! @name WCR - Watchdog Control Register */ +/*! @{ */ +#define WDOG_WCR_WDZST_MASK (0x1U) +#define WDOG_WCR_WDZST_SHIFT (0U) +/*! WDZST - WDZST + * 0b0..Continue timer operation (Default). + * 0b1..Suspend the watchdog timer. + */ +#define WDOG_WCR_WDZST(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WCR_WDZST_SHIFT)) & WDOG_WCR_WDZST_MASK) +#define WDOG_WCR_WDBG_MASK (0x2U) +#define WDOG_WCR_WDBG_SHIFT (1U) +/*! WDBG - WDBG + * 0b0..Continue WDOG timer operation (Default). + * 0b1..Suspend the watchdog timer. + */ +#define WDOG_WCR_WDBG(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WCR_WDBG_SHIFT)) & WDOG_WCR_WDBG_MASK) +#define WDOG_WCR_WDE_MASK (0x4U) +#define WDOG_WCR_WDE_SHIFT (2U) +/*! WDE - WDE + * 0b0..Disable the Watchdog (Default). + * 0b1..Enable the Watchdog. + */ +#define WDOG_WCR_WDE(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WCR_WDE_SHIFT)) & WDOG_WCR_WDE_MASK) +#define WDOG_WCR_WDT_MASK (0x8U) +#define WDOG_WCR_WDT_SHIFT (3U) +/*! WDT - WDT + * 0b0..No effect on WDOG_B (Default). + * 0b1..Assert WDOG_B upon a Watchdog Time-out event. + */ +#define WDOG_WCR_WDT(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WCR_WDT_SHIFT)) & WDOG_WCR_WDT_MASK) +#define WDOG_WCR_SRS_MASK (0x10U) +#define WDOG_WCR_SRS_SHIFT (4U) +/*! SRS - SRS + * 0b0..Assert system reset signal. + * 0b1..No effect on the system (Default). + */ +#define WDOG_WCR_SRS(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WCR_SRS_SHIFT)) & WDOG_WCR_SRS_MASK) +#define WDOG_WCR_WDA_MASK (0x20U) +#define WDOG_WCR_WDA_SHIFT (5U) +/*! WDA - WDA + * 0b0..Assert WDOG_B output. + * 0b1..No effect on system (Default). + */ +#define WDOG_WCR_WDA(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WCR_WDA_SHIFT)) & WDOG_WCR_WDA_MASK) +#define WDOG_WCR_SRE_MASK (0x40U) +#define WDOG_WCR_SRE_SHIFT (6U) +/*! SRE - software reset extension, an option way to generate software reset + * 0b0..using original way to generate software reset (default) + * 0b1..using new way to generate software reset. + */ +#define WDOG_WCR_SRE(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WCR_SRE_SHIFT)) & WDOG_WCR_SRE_MASK) +#define WDOG_WCR_WDW_MASK (0x80U) +#define WDOG_WCR_WDW_SHIFT (7U) +/*! WDW - WDW + * 0b0..Continue WDOG timer operation (Default). + * 0b1..Suspend WDOG timer operation. + */ +#define WDOG_WCR_WDW(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WCR_WDW_SHIFT)) & WDOG_WCR_WDW_MASK) +#define WDOG_WCR_WT_MASK (0xFF00U) +#define WDOG_WCR_WT_SHIFT (8U) +/*! WT - WT + * 0b00000000..- 0.5 Seconds (Default). + * 0b00000001..- 1.0 Seconds. + * 0b00000010..- 1.5 Seconds. + * 0b00000011..- 2.0 Seconds. + * 0b11111111..- 128 Seconds. + */ +#define WDOG_WCR_WT(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WCR_WT_SHIFT)) & WDOG_WCR_WT_MASK) +/*! @} */ + +/*! @name WSR - Watchdog Service Register */ +/*! @{ */ +#define WDOG_WSR_WSR_MASK (0xFFFFU) +#define WDOG_WSR_WSR_SHIFT (0U) +/*! WSR - WSR + * 0b0101010101010101..Write to the Watchdog Service Register (WDOG_WSR). + * 0b1010101010101010..Write to the Watchdog Service Register (WDOG_WSR). + */ +#define WDOG_WSR_WSR(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WSR_WSR_SHIFT)) & WDOG_WSR_WSR_MASK) +/*! @} */ + +/*! @name WRSR - Watchdog Reset Status Register */ +/*! @{ */ +#define WDOG_WRSR_SFTW_MASK (0x1U) +#define WDOG_WRSR_SFTW_SHIFT (0U) +/*! SFTW - SFTW + * 0b0..Reset is not the result of a software reset. + * 0b1..Reset is the result of a software reset. + */ +#define WDOG_WRSR_SFTW(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WRSR_SFTW_SHIFT)) & WDOG_WRSR_SFTW_MASK) +#define WDOG_WRSR_TOUT_MASK (0x2U) +#define WDOG_WRSR_TOUT_SHIFT (1U) +/*! TOUT - TOUT + * 0b0..Reset is not the result of a WDOG timeout. + * 0b1..Reset is the result of a WDOG timeout. + */ +#define WDOG_WRSR_TOUT(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WRSR_TOUT_SHIFT)) & WDOG_WRSR_TOUT_MASK) +#define WDOG_WRSR_POR_MASK (0x10U) +#define WDOG_WRSR_POR_SHIFT (4U) +/*! POR - POR + * 0b0..Reset is not the result of a power on reset. + * 0b1..Reset is the result of a power on reset. + */ +#define WDOG_WRSR_POR(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WRSR_POR_SHIFT)) & WDOG_WRSR_POR_MASK) +/*! @} */ + +/*! @name WICR - Watchdog Interrupt Control Register */ +/*! @{ */ +#define WDOG_WICR_WICT_MASK (0xFFU) +#define WDOG_WICR_WICT_SHIFT (0U) +/*! WICT - WICT + * 0b00000000..WICT[7:0] = Time duration between interrupt and time-out is 0 seconds. + * 0b00000001..WICT[7:0] = Time duration between interrupt and time-out is 0.5 seconds. + * 0b00000100..WICT[7:0] = Time duration between interrupt and time-out is 2 seconds (Default). + * 0b11111111..WICT[7:0] = Time duration between interrupt and time-out is 127.5 seconds. + */ +#define WDOG_WICR_WICT(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WICR_WICT_SHIFT)) & WDOG_WICR_WICT_MASK) +#define WDOG_WICR_WTIS_MASK (0x4000U) +#define WDOG_WICR_WTIS_SHIFT (14U) +/*! WTIS - WTIS + * 0b0..No interrupt has occurred (Default). + * 0b1..Interrupt has occurred + */ +#define WDOG_WICR_WTIS(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WICR_WTIS_SHIFT)) & WDOG_WICR_WTIS_MASK) +#define WDOG_WICR_WIE_MASK (0x8000U) +#define WDOG_WICR_WIE_SHIFT (15U) +/*! WIE - WIE + * 0b0..Disable Interrupt (Default). + * 0b1..Enable Interrupt. + */ +#define WDOG_WICR_WIE(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WICR_WIE_SHIFT)) & WDOG_WICR_WIE_MASK) +/*! @} */ + +/*! @name WMCR - Watchdog Miscellaneous Control Register */ +/*! @{ */ +#define WDOG_WMCR_PDE_MASK (0x1U) +#define WDOG_WMCR_PDE_SHIFT (0U) +/*! PDE - PDE + * 0b0..Power Down Counter of WDOG is disabled. + * 0b1..Power Down Counter of WDOG is enabled (Default). + */ +#define WDOG_WMCR_PDE(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WMCR_PDE_SHIFT)) & WDOG_WMCR_PDE_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group WDOG_Register_Masks */ + + +/* WDOG - Peripheral instance base addresses */ +/** Peripheral WDOG1 base address */ +#define WDOG1_BASE (0x400B8000u) +/** Peripheral WDOG1 base pointer */ +#define WDOG1 ((WDOG_Type *)WDOG1_BASE) +/** Peripheral WDOG2 base address */ +#define WDOG2_BASE (0x400D0000u) +/** Peripheral WDOG2 base pointer */ +#define WDOG2 ((WDOG_Type *)WDOG2_BASE) +/** Array initializer of WDOG peripheral base addresses */ +#define WDOG_BASE_ADDRS { 0u, WDOG1_BASE, WDOG2_BASE } +/** Array initializer of WDOG peripheral base pointers */ +#define WDOG_BASE_PTRS { (WDOG_Type *)0u, WDOG1, WDOG2 } +/** Interrupt vectors for the WDOG peripheral type */ +#define WDOG_IRQS { NotAvail_IRQn, WDOG1_IRQn, WDOG2_IRQn } + +/*! + * @} + */ /* end of group WDOG_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- XBARA Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup XBARA_Peripheral_Access_Layer XBARA Peripheral Access Layer + * @{ + */ + +/** XBARA - Register Layout Typedef */ +typedef struct { + __IO uint16_t SEL0; /**< Crossbar A Select Register 0, offset: 0x0 */ + __IO uint16_t SEL1; /**< Crossbar A Select Register 1, offset: 0x2 */ + __IO uint16_t SEL2; /**< Crossbar A Select Register 2, offset: 0x4 */ + __IO uint16_t SEL3; /**< Crossbar A Select Register 3, offset: 0x6 */ + __IO uint16_t SEL4; /**< Crossbar A Select Register 4, offset: 0x8 */ + __IO uint16_t SEL5; /**< Crossbar A Select Register 5, offset: 0xA */ + __IO uint16_t SEL6; /**< Crossbar A Select Register 6, offset: 0xC */ + __IO uint16_t SEL7; /**< Crossbar A Select Register 7, offset: 0xE */ + __IO uint16_t SEL8; /**< Crossbar A Select Register 8, offset: 0x10 */ + __IO uint16_t SEL9; /**< Crossbar A Select Register 9, offset: 0x12 */ + __IO uint16_t SEL10; /**< Crossbar A Select Register 10, offset: 0x14 */ + __IO uint16_t SEL11; /**< Crossbar A Select Register 11, offset: 0x16 */ + __IO uint16_t SEL12; /**< Crossbar A Select Register 12, offset: 0x18 */ + __IO uint16_t SEL13; /**< Crossbar A Select Register 13, offset: 0x1A */ + __IO uint16_t SEL14; /**< Crossbar A Select Register 14, offset: 0x1C */ + __IO uint16_t SEL15; /**< Crossbar A Select Register 15, offset: 0x1E */ + __IO uint16_t SEL16; /**< Crossbar A Select Register 16, offset: 0x20 */ + __IO uint16_t SEL17; /**< Crossbar A Select Register 17, offset: 0x22 */ + __IO uint16_t SEL18; /**< Crossbar A Select Register 18, offset: 0x24 */ + __IO uint16_t SEL19; /**< Crossbar A Select Register 19, offset: 0x26 */ + __IO uint16_t SEL20; /**< Crossbar A Select Register 20, offset: 0x28 */ + __IO uint16_t SEL21; /**< Crossbar A Select Register 21, offset: 0x2A */ + __IO uint16_t SEL22; /**< Crossbar A Select Register 22, offset: 0x2C */ + __IO uint16_t SEL23; /**< Crossbar A Select Register 23, offset: 0x2E */ + __IO uint16_t SEL24; /**< Crossbar A Select Register 24, offset: 0x30 */ + __IO uint16_t SEL25; /**< Crossbar A Select Register 25, offset: 0x32 */ + __IO uint16_t SEL26; /**< Crossbar A Select Register 26, offset: 0x34 */ + __IO uint16_t SEL27; /**< Crossbar A Select Register 27, offset: 0x36 */ + __IO uint16_t SEL28; /**< Crossbar A Select Register 28, offset: 0x38 */ + __IO uint16_t SEL29; /**< Crossbar A Select Register 29, offset: 0x3A */ + __IO uint16_t SEL30; /**< Crossbar A Select Register 30, offset: 0x3C */ + __IO uint16_t SEL31; /**< Crossbar A Select Register 31, offset: 0x3E */ + __IO uint16_t SEL32; /**< Crossbar A Select Register 32, offset: 0x40 */ + __IO uint16_t SEL33; /**< Crossbar A Select Register 33, offset: 0x42 */ + __IO uint16_t SEL34; /**< Crossbar A Select Register 34, offset: 0x44 */ + __IO uint16_t SEL35; /**< Crossbar A Select Register 35, offset: 0x46 */ + __IO uint16_t SEL36; /**< Crossbar A Select Register 36, offset: 0x48 */ + __IO uint16_t SEL37; /**< Crossbar A Select Register 37, offset: 0x4A */ + __IO uint16_t SEL38; /**< Crossbar A Select Register 38, offset: 0x4C */ + __IO uint16_t SEL39; /**< Crossbar A Select Register 39, offset: 0x4E */ + __IO uint16_t SEL40; /**< Crossbar A Select Register 40, offset: 0x50 */ + __IO uint16_t SEL41; /**< Crossbar A Select Register 41, offset: 0x52 */ + __IO uint16_t SEL42; /**< Crossbar A Select Register 42, offset: 0x54 */ + __IO uint16_t SEL43; /**< Crossbar A Select Register 43, offset: 0x56 */ + __IO uint16_t SEL44; /**< Crossbar A Select Register 44, offset: 0x58 */ + __IO uint16_t SEL45; /**< Crossbar A Select Register 45, offset: 0x5A */ + __IO uint16_t SEL46; /**< Crossbar A Select Register 46, offset: 0x5C */ + __IO uint16_t SEL47; /**< Crossbar A Select Register 47, offset: 0x5E */ + __IO uint16_t SEL48; /**< Crossbar A Select Register 48, offset: 0x60 */ + __IO uint16_t SEL49; /**< Crossbar A Select Register 49, offset: 0x62 */ + __IO uint16_t SEL50; /**< Crossbar A Select Register 50, offset: 0x64 */ + __IO uint16_t SEL51; /**< Crossbar A Select Register 51, offset: 0x66 */ + __IO uint16_t SEL52; /**< Crossbar A Select Register 52, offset: 0x68 */ + __IO uint16_t SEL53; /**< Crossbar A Select Register 53, offset: 0x6A */ + __IO uint16_t SEL54; /**< Crossbar A Select Register 54, offset: 0x6C */ + __IO uint16_t SEL55; /**< Crossbar A Select Register 55, offset: 0x6E */ + __IO uint16_t SEL56; /**< Crossbar A Select Register 56, offset: 0x70 */ + __IO uint16_t SEL57; /**< Crossbar A Select Register 57, offset: 0x72 */ + __IO uint16_t SEL58; /**< Crossbar A Select Register 58, offset: 0x74 */ + __IO uint16_t SEL59; /**< Crossbar A Select Register 59, offset: 0x76 */ + __IO uint16_t SEL60; /**< Crossbar A Select Register 60, offset: 0x78 */ + __IO uint16_t SEL61; /**< Crossbar A Select Register 61, offset: 0x7A */ + __IO uint16_t SEL62; /**< Crossbar A Select Register 62, offset: 0x7C */ + __IO uint16_t SEL63; /**< Crossbar A Select Register 63, offset: 0x7E */ + __IO uint16_t SEL64; /**< Crossbar A Select Register 64, offset: 0x80 */ + __IO uint16_t SEL65; /**< Crossbar A Select Register 65, offset: 0x82 */ + __IO uint16_t CTRL0; /**< Crossbar A Control Register 0, offset: 0x84 */ + __IO uint16_t CTRL1; /**< Crossbar A Control Register 1, offset: 0x86 */ +} XBARA_Type; + +/* ---------------------------------------------------------------------------- + -- XBARA Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup XBARA_Register_Masks XBARA Register Masks + * @{ + */ + +/*! @name SEL0 - Crossbar A Select Register 0 */ +/*! @{ */ +#define XBARA_SEL0_SEL0_MASK (0x7FU) +#define XBARA_SEL0_SEL0_SHIFT (0U) +#define XBARA_SEL0_SEL0(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL0_SEL0_SHIFT)) & XBARA_SEL0_SEL0_MASK) +#define XBARA_SEL0_SEL1_MASK (0x7F00U) +#define XBARA_SEL0_SEL1_SHIFT (8U) +#define XBARA_SEL0_SEL1(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL0_SEL1_SHIFT)) & XBARA_SEL0_SEL1_MASK) +/*! @} */ + +/*! @name SEL1 - Crossbar A Select Register 1 */ +/*! @{ */ +#define XBARA_SEL1_SEL2_MASK (0x7FU) +#define XBARA_SEL1_SEL2_SHIFT (0U) +#define XBARA_SEL1_SEL2(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL1_SEL2_SHIFT)) & XBARA_SEL1_SEL2_MASK) +#define XBARA_SEL1_SEL3_MASK (0x7F00U) +#define XBARA_SEL1_SEL3_SHIFT (8U) +#define XBARA_SEL1_SEL3(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL1_SEL3_SHIFT)) & XBARA_SEL1_SEL3_MASK) +/*! @} */ + +/*! @name SEL2 - Crossbar A Select Register 2 */ +/*! @{ */ +#define XBARA_SEL2_SEL4_MASK (0x7FU) +#define XBARA_SEL2_SEL4_SHIFT (0U) +#define XBARA_SEL2_SEL4(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL2_SEL4_SHIFT)) & XBARA_SEL2_SEL4_MASK) +#define XBARA_SEL2_SEL5_MASK (0x7F00U) +#define XBARA_SEL2_SEL5_SHIFT (8U) +#define XBARA_SEL2_SEL5(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL2_SEL5_SHIFT)) & XBARA_SEL2_SEL5_MASK) +/*! @} */ + +/*! @name SEL3 - Crossbar A Select Register 3 */ +/*! @{ */ +#define XBARA_SEL3_SEL6_MASK (0x7FU) +#define XBARA_SEL3_SEL6_SHIFT (0U) +#define XBARA_SEL3_SEL6(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL3_SEL6_SHIFT)) & XBARA_SEL3_SEL6_MASK) +#define XBARA_SEL3_SEL7_MASK (0x7F00U) +#define XBARA_SEL3_SEL7_SHIFT (8U) +#define XBARA_SEL3_SEL7(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL3_SEL7_SHIFT)) & XBARA_SEL3_SEL7_MASK) +/*! @} */ + +/*! @name SEL4 - Crossbar A Select Register 4 */ +/*! @{ */ +#define XBARA_SEL4_SEL8_MASK (0x7FU) +#define XBARA_SEL4_SEL8_SHIFT (0U) +#define XBARA_SEL4_SEL8(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL4_SEL8_SHIFT)) & XBARA_SEL4_SEL8_MASK) +#define XBARA_SEL4_SEL9_MASK (0x7F00U) +#define XBARA_SEL4_SEL9_SHIFT (8U) +#define XBARA_SEL4_SEL9(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL4_SEL9_SHIFT)) & XBARA_SEL4_SEL9_MASK) +/*! @} */ + +/*! @name SEL5 - Crossbar A Select Register 5 */ +/*! @{ */ +#define XBARA_SEL5_SEL10_MASK (0x7FU) +#define XBARA_SEL5_SEL10_SHIFT (0U) +#define XBARA_SEL5_SEL10(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL5_SEL10_SHIFT)) & XBARA_SEL5_SEL10_MASK) +#define XBARA_SEL5_SEL11_MASK (0x7F00U) +#define XBARA_SEL5_SEL11_SHIFT (8U) +#define XBARA_SEL5_SEL11(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL5_SEL11_SHIFT)) & XBARA_SEL5_SEL11_MASK) +/*! @} */ + +/*! @name SEL6 - Crossbar A Select Register 6 */ +/*! @{ */ +#define XBARA_SEL6_SEL12_MASK (0x7FU) +#define XBARA_SEL6_SEL12_SHIFT (0U) +#define XBARA_SEL6_SEL12(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL6_SEL12_SHIFT)) & XBARA_SEL6_SEL12_MASK) +#define XBARA_SEL6_SEL13_MASK (0x7F00U) +#define XBARA_SEL6_SEL13_SHIFT (8U) +#define XBARA_SEL6_SEL13(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL6_SEL13_SHIFT)) & XBARA_SEL6_SEL13_MASK) +/*! @} */ + +/*! @name SEL7 - Crossbar A Select Register 7 */ +/*! @{ */ +#define XBARA_SEL7_SEL14_MASK (0x7FU) +#define XBARA_SEL7_SEL14_SHIFT (0U) +#define XBARA_SEL7_SEL14(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL7_SEL14_SHIFT)) & XBARA_SEL7_SEL14_MASK) +#define XBARA_SEL7_SEL15_MASK (0x7F00U) +#define XBARA_SEL7_SEL15_SHIFT (8U) +#define XBARA_SEL7_SEL15(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL7_SEL15_SHIFT)) & XBARA_SEL7_SEL15_MASK) +/*! @} */ + +/*! @name SEL8 - Crossbar A Select Register 8 */ +/*! @{ */ +#define XBARA_SEL8_SEL16_MASK (0x7FU) +#define XBARA_SEL8_SEL16_SHIFT (0U) +#define XBARA_SEL8_SEL16(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL8_SEL16_SHIFT)) & XBARA_SEL8_SEL16_MASK) +#define XBARA_SEL8_SEL17_MASK (0x7F00U) +#define XBARA_SEL8_SEL17_SHIFT (8U) +#define XBARA_SEL8_SEL17(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL8_SEL17_SHIFT)) & XBARA_SEL8_SEL17_MASK) +/*! @} */ + +/*! @name SEL9 - Crossbar A Select Register 9 */ +/*! @{ */ +#define XBARA_SEL9_SEL18_MASK (0x7FU) +#define XBARA_SEL9_SEL18_SHIFT (0U) +#define XBARA_SEL9_SEL18(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL9_SEL18_SHIFT)) & XBARA_SEL9_SEL18_MASK) +#define XBARA_SEL9_SEL19_MASK (0x7F00U) +#define XBARA_SEL9_SEL19_SHIFT (8U) +#define XBARA_SEL9_SEL19(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL9_SEL19_SHIFT)) & XBARA_SEL9_SEL19_MASK) +/*! @} */ + +/*! @name SEL10 - Crossbar A Select Register 10 */ +/*! @{ */ +#define XBARA_SEL10_SEL20_MASK (0x7FU) +#define XBARA_SEL10_SEL20_SHIFT (0U) +#define XBARA_SEL10_SEL20(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL10_SEL20_SHIFT)) & XBARA_SEL10_SEL20_MASK) +#define XBARA_SEL10_SEL21_MASK (0x7F00U) +#define XBARA_SEL10_SEL21_SHIFT (8U) +#define XBARA_SEL10_SEL21(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL10_SEL21_SHIFT)) & XBARA_SEL10_SEL21_MASK) +/*! @} */ + +/*! @name SEL11 - Crossbar A Select Register 11 */ +/*! @{ */ +#define XBARA_SEL11_SEL22_MASK (0x7FU) +#define XBARA_SEL11_SEL22_SHIFT (0U) +#define XBARA_SEL11_SEL22(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL11_SEL22_SHIFT)) & XBARA_SEL11_SEL22_MASK) +#define XBARA_SEL11_SEL23_MASK (0x7F00U) +#define XBARA_SEL11_SEL23_SHIFT (8U) +#define XBARA_SEL11_SEL23(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL11_SEL23_SHIFT)) & XBARA_SEL11_SEL23_MASK) +/*! @} */ + +/*! @name SEL12 - Crossbar A Select Register 12 */ +/*! @{ */ +#define XBARA_SEL12_SEL24_MASK (0x7FU) +#define XBARA_SEL12_SEL24_SHIFT (0U) +#define XBARA_SEL12_SEL24(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL12_SEL24_SHIFT)) & XBARA_SEL12_SEL24_MASK) +#define XBARA_SEL12_SEL25_MASK (0x7F00U) +#define XBARA_SEL12_SEL25_SHIFT (8U) +#define XBARA_SEL12_SEL25(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL12_SEL25_SHIFT)) & XBARA_SEL12_SEL25_MASK) +/*! @} */ + +/*! @name SEL13 - Crossbar A Select Register 13 */ +/*! @{ */ +#define XBARA_SEL13_SEL26_MASK (0x7FU) +#define XBARA_SEL13_SEL26_SHIFT (0U) +#define XBARA_SEL13_SEL26(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL13_SEL26_SHIFT)) & XBARA_SEL13_SEL26_MASK) +#define XBARA_SEL13_SEL27_MASK (0x7F00U) +#define XBARA_SEL13_SEL27_SHIFT (8U) +#define XBARA_SEL13_SEL27(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL13_SEL27_SHIFT)) & XBARA_SEL13_SEL27_MASK) +/*! @} */ + +/*! @name SEL14 - Crossbar A Select Register 14 */ +/*! @{ */ +#define XBARA_SEL14_SEL28_MASK (0x7FU) +#define XBARA_SEL14_SEL28_SHIFT (0U) +#define XBARA_SEL14_SEL28(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL14_SEL28_SHIFT)) & XBARA_SEL14_SEL28_MASK) +#define XBARA_SEL14_SEL29_MASK (0x7F00U) +#define XBARA_SEL14_SEL29_SHIFT (8U) +#define XBARA_SEL14_SEL29(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL14_SEL29_SHIFT)) & XBARA_SEL14_SEL29_MASK) +/*! @} */ + +/*! @name SEL15 - Crossbar A Select Register 15 */ +/*! @{ */ +#define XBARA_SEL15_SEL30_MASK (0x7FU) +#define XBARA_SEL15_SEL30_SHIFT (0U) +#define XBARA_SEL15_SEL30(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL15_SEL30_SHIFT)) & XBARA_SEL15_SEL30_MASK) +#define XBARA_SEL15_SEL31_MASK (0x7F00U) +#define XBARA_SEL15_SEL31_SHIFT (8U) +#define XBARA_SEL15_SEL31(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL15_SEL31_SHIFT)) & XBARA_SEL15_SEL31_MASK) +/*! @} */ + +/*! @name SEL16 - Crossbar A Select Register 16 */ +/*! @{ */ +#define XBARA_SEL16_SEL32_MASK (0x7FU) +#define XBARA_SEL16_SEL32_SHIFT (0U) +#define XBARA_SEL16_SEL32(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL16_SEL32_SHIFT)) & XBARA_SEL16_SEL32_MASK) +#define XBARA_SEL16_SEL33_MASK (0x7F00U) +#define XBARA_SEL16_SEL33_SHIFT (8U) +#define XBARA_SEL16_SEL33(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL16_SEL33_SHIFT)) & XBARA_SEL16_SEL33_MASK) +/*! @} */ + +/*! @name SEL17 - Crossbar A Select Register 17 */ +/*! @{ */ +#define XBARA_SEL17_SEL34_MASK (0x7FU) +#define XBARA_SEL17_SEL34_SHIFT (0U) +#define XBARA_SEL17_SEL34(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL17_SEL34_SHIFT)) & XBARA_SEL17_SEL34_MASK) +#define XBARA_SEL17_SEL35_MASK (0x7F00U) +#define XBARA_SEL17_SEL35_SHIFT (8U) +#define XBARA_SEL17_SEL35(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL17_SEL35_SHIFT)) & XBARA_SEL17_SEL35_MASK) +/*! @} */ + +/*! @name SEL18 - Crossbar A Select Register 18 */ +/*! @{ */ +#define XBARA_SEL18_SEL36_MASK (0x7FU) +#define XBARA_SEL18_SEL36_SHIFT (0U) +#define XBARA_SEL18_SEL36(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL18_SEL36_SHIFT)) & XBARA_SEL18_SEL36_MASK) +#define XBARA_SEL18_SEL37_MASK (0x7F00U) +#define XBARA_SEL18_SEL37_SHIFT (8U) +#define XBARA_SEL18_SEL37(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL18_SEL37_SHIFT)) & XBARA_SEL18_SEL37_MASK) +/*! @} */ + +/*! @name SEL19 - Crossbar A Select Register 19 */ +/*! @{ */ +#define XBARA_SEL19_SEL38_MASK (0x7FU) +#define XBARA_SEL19_SEL38_SHIFT (0U) +#define XBARA_SEL19_SEL38(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL19_SEL38_SHIFT)) & XBARA_SEL19_SEL38_MASK) +#define XBARA_SEL19_SEL39_MASK (0x7F00U) +#define XBARA_SEL19_SEL39_SHIFT (8U) +#define XBARA_SEL19_SEL39(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL19_SEL39_SHIFT)) & XBARA_SEL19_SEL39_MASK) +/*! @} */ + +/*! @name SEL20 - Crossbar A Select Register 20 */ +/*! @{ */ +#define XBARA_SEL20_SEL40_MASK (0x7FU) +#define XBARA_SEL20_SEL40_SHIFT (0U) +#define XBARA_SEL20_SEL40(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL20_SEL40_SHIFT)) & XBARA_SEL20_SEL40_MASK) +#define XBARA_SEL20_SEL41_MASK (0x7F00U) +#define XBARA_SEL20_SEL41_SHIFT (8U) +#define XBARA_SEL20_SEL41(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL20_SEL41_SHIFT)) & XBARA_SEL20_SEL41_MASK) +/*! @} */ + +/*! @name SEL21 - Crossbar A Select Register 21 */ +/*! @{ */ +#define XBARA_SEL21_SEL42_MASK (0x7FU) +#define XBARA_SEL21_SEL42_SHIFT (0U) +#define XBARA_SEL21_SEL42(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL21_SEL42_SHIFT)) & XBARA_SEL21_SEL42_MASK) +#define XBARA_SEL21_SEL43_MASK (0x7F00U) +#define XBARA_SEL21_SEL43_SHIFT (8U) +#define XBARA_SEL21_SEL43(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL21_SEL43_SHIFT)) & XBARA_SEL21_SEL43_MASK) +/*! @} */ + +/*! @name SEL22 - Crossbar A Select Register 22 */ +/*! @{ */ +#define XBARA_SEL22_SEL44_MASK (0x7FU) +#define XBARA_SEL22_SEL44_SHIFT (0U) +#define XBARA_SEL22_SEL44(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL22_SEL44_SHIFT)) & XBARA_SEL22_SEL44_MASK) +#define XBARA_SEL22_SEL45_MASK (0x7F00U) +#define XBARA_SEL22_SEL45_SHIFT (8U) +#define XBARA_SEL22_SEL45(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL22_SEL45_SHIFT)) & XBARA_SEL22_SEL45_MASK) +/*! @} */ + +/*! @name SEL23 - Crossbar A Select Register 23 */ +/*! @{ */ +#define XBARA_SEL23_SEL46_MASK (0x7FU) +#define XBARA_SEL23_SEL46_SHIFT (0U) +#define XBARA_SEL23_SEL46(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL23_SEL46_SHIFT)) & XBARA_SEL23_SEL46_MASK) +#define XBARA_SEL23_SEL47_MASK (0x7F00U) +#define XBARA_SEL23_SEL47_SHIFT (8U) +#define XBARA_SEL23_SEL47(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL23_SEL47_SHIFT)) & XBARA_SEL23_SEL47_MASK) +/*! @} */ + +/*! @name SEL24 - Crossbar A Select Register 24 */ +/*! @{ */ +#define XBARA_SEL24_SEL48_MASK (0x7FU) +#define XBARA_SEL24_SEL48_SHIFT (0U) +#define XBARA_SEL24_SEL48(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL24_SEL48_SHIFT)) & XBARA_SEL24_SEL48_MASK) +#define XBARA_SEL24_SEL49_MASK (0x7F00U) +#define XBARA_SEL24_SEL49_SHIFT (8U) +#define XBARA_SEL24_SEL49(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL24_SEL49_SHIFT)) & XBARA_SEL24_SEL49_MASK) +/*! @} */ + +/*! @name SEL25 - Crossbar A Select Register 25 */ +/*! @{ */ +#define XBARA_SEL25_SEL50_MASK (0x7FU) +#define XBARA_SEL25_SEL50_SHIFT (0U) +#define XBARA_SEL25_SEL50(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL25_SEL50_SHIFT)) & XBARA_SEL25_SEL50_MASK) +#define XBARA_SEL25_SEL51_MASK (0x7F00U) +#define XBARA_SEL25_SEL51_SHIFT (8U) +#define XBARA_SEL25_SEL51(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL25_SEL51_SHIFT)) & XBARA_SEL25_SEL51_MASK) +/*! @} */ + +/*! @name SEL26 - Crossbar A Select Register 26 */ +/*! @{ */ +#define XBARA_SEL26_SEL52_MASK (0x7FU) +#define XBARA_SEL26_SEL52_SHIFT (0U) +#define XBARA_SEL26_SEL52(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL26_SEL52_SHIFT)) & XBARA_SEL26_SEL52_MASK) +#define XBARA_SEL26_SEL53_MASK (0x7F00U) +#define XBARA_SEL26_SEL53_SHIFT (8U) +#define XBARA_SEL26_SEL53(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL26_SEL53_SHIFT)) & XBARA_SEL26_SEL53_MASK) +/*! @} */ + +/*! @name SEL27 - Crossbar A Select Register 27 */ +/*! @{ */ +#define XBARA_SEL27_SEL54_MASK (0x7FU) +#define XBARA_SEL27_SEL54_SHIFT (0U) +#define XBARA_SEL27_SEL54(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL27_SEL54_SHIFT)) & XBARA_SEL27_SEL54_MASK) +#define XBARA_SEL27_SEL55_MASK (0x7F00U) +#define XBARA_SEL27_SEL55_SHIFT (8U) +#define XBARA_SEL27_SEL55(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL27_SEL55_SHIFT)) & XBARA_SEL27_SEL55_MASK) +/*! @} */ + +/*! @name SEL28 - Crossbar A Select Register 28 */ +/*! @{ */ +#define XBARA_SEL28_SEL56_MASK (0x7FU) +#define XBARA_SEL28_SEL56_SHIFT (0U) +#define XBARA_SEL28_SEL56(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL28_SEL56_SHIFT)) & XBARA_SEL28_SEL56_MASK) +#define XBARA_SEL28_SEL57_MASK (0x7F00U) +#define XBARA_SEL28_SEL57_SHIFT (8U) +#define XBARA_SEL28_SEL57(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL28_SEL57_SHIFT)) & XBARA_SEL28_SEL57_MASK) +/*! @} */ + +/*! @name SEL29 - Crossbar A Select Register 29 */ +/*! @{ */ +#define XBARA_SEL29_SEL58_MASK (0x7FU) +#define XBARA_SEL29_SEL58_SHIFT (0U) +#define XBARA_SEL29_SEL58(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL29_SEL58_SHIFT)) & XBARA_SEL29_SEL58_MASK) +#define XBARA_SEL29_SEL59_MASK (0x7F00U) +#define XBARA_SEL29_SEL59_SHIFT (8U) +#define XBARA_SEL29_SEL59(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL29_SEL59_SHIFT)) & XBARA_SEL29_SEL59_MASK) +/*! @} */ + +/*! @name SEL30 - Crossbar A Select Register 30 */ +/*! @{ */ +#define XBARA_SEL30_SEL60_MASK (0x7FU) +#define XBARA_SEL30_SEL60_SHIFT (0U) +#define XBARA_SEL30_SEL60(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL30_SEL60_SHIFT)) & XBARA_SEL30_SEL60_MASK) +#define XBARA_SEL30_SEL61_MASK (0x7F00U) +#define XBARA_SEL30_SEL61_SHIFT (8U) +#define XBARA_SEL30_SEL61(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL30_SEL61_SHIFT)) & XBARA_SEL30_SEL61_MASK) +/*! @} */ + +/*! @name SEL31 - Crossbar A Select Register 31 */ +/*! @{ */ +#define XBARA_SEL31_SEL62_MASK (0x7FU) +#define XBARA_SEL31_SEL62_SHIFT (0U) +#define XBARA_SEL31_SEL62(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL31_SEL62_SHIFT)) & XBARA_SEL31_SEL62_MASK) +#define XBARA_SEL31_SEL63_MASK (0x7F00U) +#define XBARA_SEL31_SEL63_SHIFT (8U) +#define XBARA_SEL31_SEL63(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL31_SEL63_SHIFT)) & XBARA_SEL31_SEL63_MASK) +/*! @} */ + +/*! @name SEL32 - Crossbar A Select Register 32 */ +/*! @{ */ +#define XBARA_SEL32_SEL64_MASK (0x7FU) +#define XBARA_SEL32_SEL64_SHIFT (0U) +#define XBARA_SEL32_SEL64(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL32_SEL64_SHIFT)) & XBARA_SEL32_SEL64_MASK) +#define XBARA_SEL32_SEL65_MASK (0x7F00U) +#define XBARA_SEL32_SEL65_SHIFT (8U) +#define XBARA_SEL32_SEL65(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL32_SEL65_SHIFT)) & XBARA_SEL32_SEL65_MASK) +/*! @} */ + +/*! @name SEL33 - Crossbar A Select Register 33 */ +/*! @{ */ +#define XBARA_SEL33_SEL66_MASK (0x7FU) +#define XBARA_SEL33_SEL66_SHIFT (0U) +#define XBARA_SEL33_SEL66(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL33_SEL66_SHIFT)) & XBARA_SEL33_SEL66_MASK) +#define XBARA_SEL33_SEL67_MASK (0x7F00U) +#define XBARA_SEL33_SEL67_SHIFT (8U) +#define XBARA_SEL33_SEL67(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL33_SEL67_SHIFT)) & XBARA_SEL33_SEL67_MASK) +/*! @} */ + +/*! @name SEL34 - Crossbar A Select Register 34 */ +/*! @{ */ +#define XBARA_SEL34_SEL68_MASK (0x7FU) +#define XBARA_SEL34_SEL68_SHIFT (0U) +#define XBARA_SEL34_SEL68(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL34_SEL68_SHIFT)) & XBARA_SEL34_SEL68_MASK) +#define XBARA_SEL34_SEL69_MASK (0x7F00U) +#define XBARA_SEL34_SEL69_SHIFT (8U) +#define XBARA_SEL34_SEL69(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL34_SEL69_SHIFT)) & XBARA_SEL34_SEL69_MASK) +/*! @} */ + +/*! @name SEL35 - Crossbar A Select Register 35 */ +/*! @{ */ +#define XBARA_SEL35_SEL70_MASK (0x7FU) +#define XBARA_SEL35_SEL70_SHIFT (0U) +#define XBARA_SEL35_SEL70(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL35_SEL70_SHIFT)) & XBARA_SEL35_SEL70_MASK) +#define XBARA_SEL35_SEL71_MASK (0x7F00U) +#define XBARA_SEL35_SEL71_SHIFT (8U) +#define XBARA_SEL35_SEL71(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL35_SEL71_SHIFT)) & XBARA_SEL35_SEL71_MASK) +/*! @} */ + +/*! @name SEL36 - Crossbar A Select Register 36 */ +/*! @{ */ +#define XBARA_SEL36_SEL72_MASK (0x7FU) +#define XBARA_SEL36_SEL72_SHIFT (0U) +#define XBARA_SEL36_SEL72(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL36_SEL72_SHIFT)) & XBARA_SEL36_SEL72_MASK) +#define XBARA_SEL36_SEL73_MASK (0x7F00U) +#define XBARA_SEL36_SEL73_SHIFT (8U) +#define XBARA_SEL36_SEL73(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL36_SEL73_SHIFT)) & XBARA_SEL36_SEL73_MASK) +/*! @} */ + +/*! @name SEL37 - Crossbar A Select Register 37 */ +/*! @{ */ +#define XBARA_SEL37_SEL74_MASK (0x7FU) +#define XBARA_SEL37_SEL74_SHIFT (0U) +#define XBARA_SEL37_SEL74(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL37_SEL74_SHIFT)) & XBARA_SEL37_SEL74_MASK) +#define XBARA_SEL37_SEL75_MASK (0x7F00U) +#define XBARA_SEL37_SEL75_SHIFT (8U) +#define XBARA_SEL37_SEL75(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL37_SEL75_SHIFT)) & XBARA_SEL37_SEL75_MASK) +/*! @} */ + +/*! @name SEL38 - Crossbar A Select Register 38 */ +/*! @{ */ +#define XBARA_SEL38_SEL76_MASK (0x7FU) +#define XBARA_SEL38_SEL76_SHIFT (0U) +#define XBARA_SEL38_SEL76(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL38_SEL76_SHIFT)) & XBARA_SEL38_SEL76_MASK) +#define XBARA_SEL38_SEL77_MASK (0x7F00U) +#define XBARA_SEL38_SEL77_SHIFT (8U) +#define XBARA_SEL38_SEL77(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL38_SEL77_SHIFT)) & XBARA_SEL38_SEL77_MASK) +/*! @} */ + +/*! @name SEL39 - Crossbar A Select Register 39 */ +/*! @{ */ +#define XBARA_SEL39_SEL78_MASK (0x7FU) +#define XBARA_SEL39_SEL78_SHIFT (0U) +#define XBARA_SEL39_SEL78(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL39_SEL78_SHIFT)) & XBARA_SEL39_SEL78_MASK) +#define XBARA_SEL39_SEL79_MASK (0x7F00U) +#define XBARA_SEL39_SEL79_SHIFT (8U) +#define XBARA_SEL39_SEL79(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL39_SEL79_SHIFT)) & XBARA_SEL39_SEL79_MASK) +/*! @} */ + +/*! @name SEL40 - Crossbar A Select Register 40 */ +/*! @{ */ +#define XBARA_SEL40_SEL80_MASK (0x7FU) +#define XBARA_SEL40_SEL80_SHIFT (0U) +#define XBARA_SEL40_SEL80(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL40_SEL80_SHIFT)) & XBARA_SEL40_SEL80_MASK) +#define XBARA_SEL40_SEL81_MASK (0x7F00U) +#define XBARA_SEL40_SEL81_SHIFT (8U) +#define XBARA_SEL40_SEL81(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL40_SEL81_SHIFT)) & XBARA_SEL40_SEL81_MASK) +/*! @} */ + +/*! @name SEL41 - Crossbar A Select Register 41 */ +/*! @{ */ +#define XBARA_SEL41_SEL82_MASK (0x7FU) +#define XBARA_SEL41_SEL82_SHIFT (0U) +#define XBARA_SEL41_SEL82(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL41_SEL82_SHIFT)) & XBARA_SEL41_SEL82_MASK) +#define XBARA_SEL41_SEL83_MASK (0x7F00U) +#define XBARA_SEL41_SEL83_SHIFT (8U) +#define XBARA_SEL41_SEL83(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL41_SEL83_SHIFT)) & XBARA_SEL41_SEL83_MASK) +/*! @} */ + +/*! @name SEL42 - Crossbar A Select Register 42 */ +/*! @{ */ +#define XBARA_SEL42_SEL84_MASK (0x7FU) +#define XBARA_SEL42_SEL84_SHIFT (0U) +#define XBARA_SEL42_SEL84(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL42_SEL84_SHIFT)) & XBARA_SEL42_SEL84_MASK) +#define XBARA_SEL42_SEL85_MASK (0x7F00U) +#define XBARA_SEL42_SEL85_SHIFT (8U) +#define XBARA_SEL42_SEL85(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL42_SEL85_SHIFT)) & XBARA_SEL42_SEL85_MASK) +/*! @} */ + +/*! @name SEL43 - Crossbar A Select Register 43 */ +/*! @{ */ +#define XBARA_SEL43_SEL86_MASK (0x7FU) +#define XBARA_SEL43_SEL86_SHIFT (0U) +#define XBARA_SEL43_SEL86(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL43_SEL86_SHIFT)) & XBARA_SEL43_SEL86_MASK) +#define XBARA_SEL43_SEL87_MASK (0x7F00U) +#define XBARA_SEL43_SEL87_SHIFT (8U) +#define XBARA_SEL43_SEL87(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL43_SEL87_SHIFT)) & XBARA_SEL43_SEL87_MASK) +/*! @} */ + +/*! @name SEL44 - Crossbar A Select Register 44 */ +/*! @{ */ +#define XBARA_SEL44_SEL88_MASK (0x7FU) +#define XBARA_SEL44_SEL88_SHIFT (0U) +#define XBARA_SEL44_SEL88(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL44_SEL88_SHIFT)) & XBARA_SEL44_SEL88_MASK) +#define XBARA_SEL44_SEL89_MASK (0x7F00U) +#define XBARA_SEL44_SEL89_SHIFT (8U) +#define XBARA_SEL44_SEL89(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL44_SEL89_SHIFT)) & XBARA_SEL44_SEL89_MASK) +/*! @} */ + +/*! @name SEL45 - Crossbar A Select Register 45 */ +/*! @{ */ +#define XBARA_SEL45_SEL90_MASK (0x7FU) +#define XBARA_SEL45_SEL90_SHIFT (0U) +#define XBARA_SEL45_SEL90(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL45_SEL90_SHIFT)) & XBARA_SEL45_SEL90_MASK) +#define XBARA_SEL45_SEL91_MASK (0x7F00U) +#define XBARA_SEL45_SEL91_SHIFT (8U) +#define XBARA_SEL45_SEL91(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL45_SEL91_SHIFT)) & XBARA_SEL45_SEL91_MASK) +/*! @} */ + +/*! @name SEL46 - Crossbar A Select Register 46 */ +/*! @{ */ +#define XBARA_SEL46_SEL92_MASK (0x7FU) +#define XBARA_SEL46_SEL92_SHIFT (0U) +#define XBARA_SEL46_SEL92(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL46_SEL92_SHIFT)) & XBARA_SEL46_SEL92_MASK) +#define XBARA_SEL46_SEL93_MASK (0x7F00U) +#define XBARA_SEL46_SEL93_SHIFT (8U) +#define XBARA_SEL46_SEL93(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL46_SEL93_SHIFT)) & XBARA_SEL46_SEL93_MASK) +/*! @} */ + +/*! @name SEL47 - Crossbar A Select Register 47 */ +/*! @{ */ +#define XBARA_SEL47_SEL94_MASK (0x7FU) +#define XBARA_SEL47_SEL94_SHIFT (0U) +#define XBARA_SEL47_SEL94(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL47_SEL94_SHIFT)) & XBARA_SEL47_SEL94_MASK) +#define XBARA_SEL47_SEL95_MASK (0x7F00U) +#define XBARA_SEL47_SEL95_SHIFT (8U) +#define XBARA_SEL47_SEL95(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL47_SEL95_SHIFT)) & XBARA_SEL47_SEL95_MASK) +/*! @} */ + +/*! @name SEL48 - Crossbar A Select Register 48 */ +/*! @{ */ +#define XBARA_SEL48_SEL96_MASK (0x7FU) +#define XBARA_SEL48_SEL96_SHIFT (0U) +#define XBARA_SEL48_SEL96(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL48_SEL96_SHIFT)) & XBARA_SEL48_SEL96_MASK) +#define XBARA_SEL48_SEL97_MASK (0x7F00U) +#define XBARA_SEL48_SEL97_SHIFT (8U) +#define XBARA_SEL48_SEL97(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL48_SEL97_SHIFT)) & XBARA_SEL48_SEL97_MASK) +/*! @} */ + +/*! @name SEL49 - Crossbar A Select Register 49 */ +/*! @{ */ +#define XBARA_SEL49_SEL98_MASK (0x7FU) +#define XBARA_SEL49_SEL98_SHIFT (0U) +#define XBARA_SEL49_SEL98(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL49_SEL98_SHIFT)) & XBARA_SEL49_SEL98_MASK) +#define XBARA_SEL49_SEL99_MASK (0x7F00U) +#define XBARA_SEL49_SEL99_SHIFT (8U) +#define XBARA_SEL49_SEL99(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL49_SEL99_SHIFT)) & XBARA_SEL49_SEL99_MASK) +/*! @} */ + +/*! @name SEL50 - Crossbar A Select Register 50 */ +/*! @{ */ +#define XBARA_SEL50_SEL100_MASK (0x7FU) +#define XBARA_SEL50_SEL100_SHIFT (0U) +#define XBARA_SEL50_SEL100(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL50_SEL100_SHIFT)) & XBARA_SEL50_SEL100_MASK) +#define XBARA_SEL50_SEL101_MASK (0x7F00U) +#define XBARA_SEL50_SEL101_SHIFT (8U) +#define XBARA_SEL50_SEL101(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL50_SEL101_SHIFT)) & XBARA_SEL50_SEL101_MASK) +/*! @} */ + +/*! @name SEL51 - Crossbar A Select Register 51 */ +/*! @{ */ +#define XBARA_SEL51_SEL102_MASK (0x7FU) +#define XBARA_SEL51_SEL102_SHIFT (0U) +#define XBARA_SEL51_SEL102(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL51_SEL102_SHIFT)) & XBARA_SEL51_SEL102_MASK) +#define XBARA_SEL51_SEL103_MASK (0x7F00U) +#define XBARA_SEL51_SEL103_SHIFT (8U) +#define XBARA_SEL51_SEL103(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL51_SEL103_SHIFT)) & XBARA_SEL51_SEL103_MASK) +/*! @} */ + +/*! @name SEL52 - Crossbar A Select Register 52 */ +/*! @{ */ +#define XBARA_SEL52_SEL104_MASK (0x7FU) +#define XBARA_SEL52_SEL104_SHIFT (0U) +#define XBARA_SEL52_SEL104(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL52_SEL104_SHIFT)) & XBARA_SEL52_SEL104_MASK) +#define XBARA_SEL52_SEL105_MASK (0x7F00U) +#define XBARA_SEL52_SEL105_SHIFT (8U) +#define XBARA_SEL52_SEL105(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL52_SEL105_SHIFT)) & XBARA_SEL52_SEL105_MASK) +/*! @} */ + +/*! @name SEL53 - Crossbar A Select Register 53 */ +/*! @{ */ +#define XBARA_SEL53_SEL106_MASK (0x7FU) +#define XBARA_SEL53_SEL106_SHIFT (0U) +#define XBARA_SEL53_SEL106(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL53_SEL106_SHIFT)) & XBARA_SEL53_SEL106_MASK) +#define XBARA_SEL53_SEL107_MASK (0x7F00U) +#define XBARA_SEL53_SEL107_SHIFT (8U) +#define XBARA_SEL53_SEL107(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL53_SEL107_SHIFT)) & XBARA_SEL53_SEL107_MASK) +/*! @} */ + +/*! @name SEL54 - Crossbar A Select Register 54 */ +/*! @{ */ +#define XBARA_SEL54_SEL108_MASK (0x7FU) +#define XBARA_SEL54_SEL108_SHIFT (0U) +#define XBARA_SEL54_SEL108(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL54_SEL108_SHIFT)) & XBARA_SEL54_SEL108_MASK) +#define XBARA_SEL54_SEL109_MASK (0x7F00U) +#define XBARA_SEL54_SEL109_SHIFT (8U) +#define XBARA_SEL54_SEL109(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL54_SEL109_SHIFT)) & XBARA_SEL54_SEL109_MASK) +/*! @} */ + +/*! @name SEL55 - Crossbar A Select Register 55 */ +/*! @{ */ +#define XBARA_SEL55_SEL110_MASK (0x7FU) +#define XBARA_SEL55_SEL110_SHIFT (0U) +#define XBARA_SEL55_SEL110(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL55_SEL110_SHIFT)) & XBARA_SEL55_SEL110_MASK) +#define XBARA_SEL55_SEL111_MASK (0x7F00U) +#define XBARA_SEL55_SEL111_SHIFT (8U) +#define XBARA_SEL55_SEL111(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL55_SEL111_SHIFT)) & XBARA_SEL55_SEL111_MASK) +/*! @} */ + +/*! @name SEL56 - Crossbar A Select Register 56 */ +/*! @{ */ +#define XBARA_SEL56_SEL112_MASK (0x7FU) +#define XBARA_SEL56_SEL112_SHIFT (0U) +#define XBARA_SEL56_SEL112(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL56_SEL112_SHIFT)) & XBARA_SEL56_SEL112_MASK) +#define XBARA_SEL56_SEL113_MASK (0x7F00U) +#define XBARA_SEL56_SEL113_SHIFT (8U) +#define XBARA_SEL56_SEL113(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL56_SEL113_SHIFT)) & XBARA_SEL56_SEL113_MASK) +/*! @} */ + +/*! @name SEL57 - Crossbar A Select Register 57 */ +/*! @{ */ +#define XBARA_SEL57_SEL114_MASK (0x7FU) +#define XBARA_SEL57_SEL114_SHIFT (0U) +#define XBARA_SEL57_SEL114(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL57_SEL114_SHIFT)) & XBARA_SEL57_SEL114_MASK) +#define XBARA_SEL57_SEL115_MASK (0x7F00U) +#define XBARA_SEL57_SEL115_SHIFT (8U) +#define XBARA_SEL57_SEL115(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL57_SEL115_SHIFT)) & XBARA_SEL57_SEL115_MASK) +/*! @} */ + +/*! @name SEL58 - Crossbar A Select Register 58 */ +/*! @{ */ +#define XBARA_SEL58_SEL116_MASK (0x7FU) +#define XBARA_SEL58_SEL116_SHIFT (0U) +#define XBARA_SEL58_SEL116(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL58_SEL116_SHIFT)) & XBARA_SEL58_SEL116_MASK) +#define XBARA_SEL58_SEL117_MASK (0x7F00U) +#define XBARA_SEL58_SEL117_SHIFT (8U) +#define XBARA_SEL58_SEL117(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL58_SEL117_SHIFT)) & XBARA_SEL58_SEL117_MASK) +/*! @} */ + +/*! @name SEL59 - Crossbar A Select Register 59 */ +/*! @{ */ +#define XBARA_SEL59_SEL118_MASK (0x7FU) +#define XBARA_SEL59_SEL118_SHIFT (0U) +#define XBARA_SEL59_SEL118(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL59_SEL118_SHIFT)) & XBARA_SEL59_SEL118_MASK) +#define XBARA_SEL59_SEL119_MASK (0x7F00U) +#define XBARA_SEL59_SEL119_SHIFT (8U) +#define XBARA_SEL59_SEL119(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL59_SEL119_SHIFT)) & XBARA_SEL59_SEL119_MASK) +/*! @} */ + +/*! @name SEL60 - Crossbar A Select Register 60 */ +/*! @{ */ +#define XBARA_SEL60_SEL120_MASK (0x7FU) +#define XBARA_SEL60_SEL120_SHIFT (0U) +#define XBARA_SEL60_SEL120(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL60_SEL120_SHIFT)) & XBARA_SEL60_SEL120_MASK) +#define XBARA_SEL60_SEL121_MASK (0x7F00U) +#define XBARA_SEL60_SEL121_SHIFT (8U) +#define XBARA_SEL60_SEL121(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL60_SEL121_SHIFT)) & XBARA_SEL60_SEL121_MASK) +/*! @} */ + +/*! @name SEL61 - Crossbar A Select Register 61 */ +/*! @{ */ +#define XBARA_SEL61_SEL122_MASK (0x7FU) +#define XBARA_SEL61_SEL122_SHIFT (0U) +#define XBARA_SEL61_SEL122(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL61_SEL122_SHIFT)) & XBARA_SEL61_SEL122_MASK) +#define XBARA_SEL61_SEL123_MASK (0x7F00U) +#define XBARA_SEL61_SEL123_SHIFT (8U) +#define XBARA_SEL61_SEL123(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL61_SEL123_SHIFT)) & XBARA_SEL61_SEL123_MASK) +/*! @} */ + +/*! @name SEL62 - Crossbar A Select Register 62 */ +/*! @{ */ +#define XBARA_SEL62_SEL124_MASK (0x7FU) +#define XBARA_SEL62_SEL124_SHIFT (0U) +#define XBARA_SEL62_SEL124(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL62_SEL124_SHIFT)) & XBARA_SEL62_SEL124_MASK) +#define XBARA_SEL62_SEL125_MASK (0x7F00U) +#define XBARA_SEL62_SEL125_SHIFT (8U) +#define XBARA_SEL62_SEL125(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL62_SEL125_SHIFT)) & XBARA_SEL62_SEL125_MASK) +/*! @} */ + +/*! @name SEL63 - Crossbar A Select Register 63 */ +/*! @{ */ +#define XBARA_SEL63_SEL126_MASK (0x7FU) +#define XBARA_SEL63_SEL126_SHIFT (0U) +#define XBARA_SEL63_SEL126(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL63_SEL126_SHIFT)) & XBARA_SEL63_SEL126_MASK) +#define XBARA_SEL63_SEL127_MASK (0x7F00U) +#define XBARA_SEL63_SEL127_SHIFT (8U) +#define XBARA_SEL63_SEL127(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL63_SEL127_SHIFT)) & XBARA_SEL63_SEL127_MASK) +/*! @} */ + +/*! @name SEL64 - Crossbar A Select Register 64 */ +/*! @{ */ +#define XBARA_SEL64_SEL128_MASK (0x7FU) +#define XBARA_SEL64_SEL128_SHIFT (0U) +#define XBARA_SEL64_SEL128(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL64_SEL128_SHIFT)) & XBARA_SEL64_SEL128_MASK) +#define XBARA_SEL64_SEL129_MASK (0x7F00U) +#define XBARA_SEL64_SEL129_SHIFT (8U) +#define XBARA_SEL64_SEL129(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL64_SEL129_SHIFT)) & XBARA_SEL64_SEL129_MASK) +/*! @} */ + +/*! @name SEL65 - Crossbar A Select Register 65 */ +/*! @{ */ +#define XBARA_SEL65_SEL130_MASK (0x7FU) +#define XBARA_SEL65_SEL130_SHIFT (0U) +#define XBARA_SEL65_SEL130(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL65_SEL130_SHIFT)) & XBARA_SEL65_SEL130_MASK) +#define XBARA_SEL65_SEL131_MASK (0x7F00U) +#define XBARA_SEL65_SEL131_SHIFT (8U) +#define XBARA_SEL65_SEL131(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL65_SEL131_SHIFT)) & XBARA_SEL65_SEL131_MASK) +/*! @} */ + +/*! @name CTRL0 - Crossbar A Control Register 0 */ +/*! @{ */ +#define XBARA_CTRL0_DEN0_MASK (0x1U) +#define XBARA_CTRL0_DEN0_SHIFT (0U) +/*! DEN0 - DMA Enable for XBAR_OUT0 + * 0b0..DMA disabled + * 0b1..DMA enabled + */ +#define XBARA_CTRL0_DEN0(x) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL0_DEN0_SHIFT)) & XBARA_CTRL0_DEN0_MASK) +#define XBARA_CTRL0_IEN0_MASK (0x2U) +#define XBARA_CTRL0_IEN0_SHIFT (1U) +/*! IEN0 - Interrupt Enable for XBAR_OUT0 + * 0b0..Interrupt disabled + * 0b1..Interrupt enabled + */ +#define XBARA_CTRL0_IEN0(x) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL0_IEN0_SHIFT)) & XBARA_CTRL0_IEN0_MASK) +#define XBARA_CTRL0_EDGE0_MASK (0xCU) +#define XBARA_CTRL0_EDGE0_SHIFT (2U) +/*! EDGE0 - Active edge for edge detection on XBAR_OUT0 + * 0b00..STS0 never asserts + * 0b01..STS0 asserts on rising edges of XBAR_OUT0 + * 0b10..STS0 asserts on falling edges of XBAR_OUT0 + * 0b11..STS0 asserts on rising and falling edges of XBAR_OUT0 + */ +#define XBARA_CTRL0_EDGE0(x) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL0_EDGE0_SHIFT)) & XBARA_CTRL0_EDGE0_MASK) +#define XBARA_CTRL0_STS0_MASK (0x10U) +#define XBARA_CTRL0_STS0_SHIFT (4U) +/*! STS0 - Edge detection status for XBAR_OUT0 + * 0b0..Active edge not yet detected on XBAR_OUT0 + * 0b1..Active edge detected on XBAR_OUT0 + */ +#define XBARA_CTRL0_STS0(x) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL0_STS0_SHIFT)) & XBARA_CTRL0_STS0_MASK) +#define XBARA_CTRL0_DEN1_MASK (0x100U) +#define XBARA_CTRL0_DEN1_SHIFT (8U) +/*! DEN1 - DMA Enable for XBAR_OUT1 + * 0b0..DMA disabled + * 0b1..DMA enabled + */ +#define XBARA_CTRL0_DEN1(x) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL0_DEN1_SHIFT)) & XBARA_CTRL0_DEN1_MASK) +#define XBARA_CTRL0_IEN1_MASK (0x200U) +#define XBARA_CTRL0_IEN1_SHIFT (9U) +/*! IEN1 - Interrupt Enable for XBAR_OUT1 + * 0b0..Interrupt disabled + * 0b1..Interrupt enabled + */ +#define XBARA_CTRL0_IEN1(x) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL0_IEN1_SHIFT)) & XBARA_CTRL0_IEN1_MASK) +#define XBARA_CTRL0_EDGE1_MASK (0xC00U) +#define XBARA_CTRL0_EDGE1_SHIFT (10U) +/*! EDGE1 - Active edge for edge detection on XBAR_OUT1 + * 0b00..STS1 never asserts + * 0b01..STS1 asserts on rising edges of XBAR_OUT1 + * 0b10..STS1 asserts on falling edges of XBAR_OUT1 + * 0b11..STS1 asserts on rising and falling edges of XBAR_OUT1 + */ +#define XBARA_CTRL0_EDGE1(x) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL0_EDGE1_SHIFT)) & XBARA_CTRL0_EDGE1_MASK) +#define XBARA_CTRL0_STS1_MASK (0x1000U) +#define XBARA_CTRL0_STS1_SHIFT (12U) +/*! STS1 - Edge detection status for XBAR_OUT1 + * 0b0..Active edge not yet detected on XBAR_OUT1 + * 0b1..Active edge detected on XBAR_OUT1 + */ +#define XBARA_CTRL0_STS1(x) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL0_STS1_SHIFT)) & XBARA_CTRL0_STS1_MASK) +/*! @} */ + +/*! @name CTRL1 - Crossbar A Control Register 1 */ +/*! @{ */ +#define XBARA_CTRL1_DEN2_MASK (0x1U) +#define XBARA_CTRL1_DEN2_SHIFT (0U) +/*! DEN2 - DMA Enable for XBAR_OUT2 + * 0b0..DMA disabled + * 0b1..DMA enabled + */ +#define XBARA_CTRL1_DEN2(x) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL1_DEN2_SHIFT)) & XBARA_CTRL1_DEN2_MASK) +#define XBARA_CTRL1_IEN2_MASK (0x2U) +#define XBARA_CTRL1_IEN2_SHIFT (1U) +/*! IEN2 - Interrupt Enable for XBAR_OUT2 + * 0b0..Interrupt disabled + * 0b1..Interrupt enabled + */ +#define XBARA_CTRL1_IEN2(x) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL1_IEN2_SHIFT)) & XBARA_CTRL1_IEN2_MASK) +#define XBARA_CTRL1_EDGE2_MASK (0xCU) +#define XBARA_CTRL1_EDGE2_SHIFT (2U) +/*! EDGE2 - Active edge for edge detection on XBAR_OUT2 + * 0b00..STS2 never asserts + * 0b01..STS2 asserts on rising edges of XBAR_OUT2 + * 0b10..STS2 asserts on falling edges of XBAR_OUT2 + * 0b11..STS2 asserts on rising and falling edges of XBAR_OUT2 + */ +#define XBARA_CTRL1_EDGE2(x) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL1_EDGE2_SHIFT)) & XBARA_CTRL1_EDGE2_MASK) +#define XBARA_CTRL1_STS2_MASK (0x10U) +#define XBARA_CTRL1_STS2_SHIFT (4U) +/*! STS2 - Edge detection status for XBAR_OUT2 + * 0b0..Active edge not yet detected on XBAR_OUT2 + * 0b1..Active edge detected on XBAR_OUT2 + */ +#define XBARA_CTRL1_STS2(x) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL1_STS2_SHIFT)) & XBARA_CTRL1_STS2_MASK) +#define XBARA_CTRL1_DEN3_MASK (0x100U) +#define XBARA_CTRL1_DEN3_SHIFT (8U) +/*! DEN3 - DMA Enable for XBAR_OUT3 + * 0b0..DMA disabled + * 0b1..DMA enabled + */ +#define XBARA_CTRL1_DEN3(x) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL1_DEN3_SHIFT)) & XBARA_CTRL1_DEN3_MASK) +#define XBARA_CTRL1_IEN3_MASK (0x200U) +#define XBARA_CTRL1_IEN3_SHIFT (9U) +/*! IEN3 - Interrupt Enable for XBAR_OUT3 + * 0b0..Interrupt disabled + * 0b1..Interrupt enabled + */ +#define XBARA_CTRL1_IEN3(x) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL1_IEN3_SHIFT)) & XBARA_CTRL1_IEN3_MASK) +#define XBARA_CTRL1_EDGE3_MASK (0xC00U) +#define XBARA_CTRL1_EDGE3_SHIFT (10U) +/*! EDGE3 - Active edge for edge detection on XBAR_OUT3 + * 0b00..STS3 never asserts + * 0b01..STS3 asserts on rising edges of XBAR_OUT3 + * 0b10..STS3 asserts on falling edges of XBAR_OUT3 + * 0b11..STS3 asserts on rising and falling edges of XBAR_OUT3 + */ +#define XBARA_CTRL1_EDGE3(x) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL1_EDGE3_SHIFT)) & XBARA_CTRL1_EDGE3_MASK) +#define XBARA_CTRL1_STS3_MASK (0x1000U) +#define XBARA_CTRL1_STS3_SHIFT (12U) +/*! STS3 - Edge detection status for XBAR_OUT3 + * 0b0..Active edge not yet detected on XBAR_OUT3 + * 0b1..Active edge detected on XBAR_OUT3 + */ +#define XBARA_CTRL1_STS3(x) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL1_STS3_SHIFT)) & XBARA_CTRL1_STS3_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group XBARA_Register_Masks */ + + +/* XBARA - Peripheral instance base addresses */ +/** Peripheral XBARA1 base address */ +#define XBARA1_BASE (0x403BC000u) +/** Peripheral XBARA1 base pointer */ +#define XBARA1 ((XBARA_Type *)XBARA1_BASE) +/** Array initializer of XBARA peripheral base addresses */ +#define XBARA_BASE_ADDRS { XBARA1_BASE } +/** Array initializer of XBARA peripheral base pointers */ +#define XBARA_BASE_PTRS { XBARA1 } + +/*! + * @} + */ /* end of group XBARA_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- XBARB Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup XBARB_Peripheral_Access_Layer XBARB Peripheral Access Layer + * @{ + */ + +/** XBARB - Register Layout Typedef */ +typedef struct { + __IO uint16_t SEL0; /**< Crossbar B Select Register 0, offset: 0x0 */ + __IO uint16_t SEL1; /**< Crossbar B Select Register 1, offset: 0x2 */ + __IO uint16_t SEL2; /**< Crossbar B Select Register 2, offset: 0x4 */ + __IO uint16_t SEL3; /**< Crossbar B Select Register 3, offset: 0x6 */ + __IO uint16_t SEL4; /**< Crossbar B Select Register 4, offset: 0x8 */ + __IO uint16_t SEL5; /**< Crossbar B Select Register 5, offset: 0xA */ + __IO uint16_t SEL6; /**< Crossbar B Select Register 6, offset: 0xC */ + __IO uint16_t SEL7; /**< Crossbar B Select Register 7, offset: 0xE */ +} XBARB_Type; + +/* ---------------------------------------------------------------------------- + -- XBARB Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup XBARB_Register_Masks XBARB Register Masks + * @{ + */ + +/*! @name SEL0 - Crossbar B Select Register 0 */ +/*! @{ */ +#define XBARB_SEL0_SEL0_MASK (0x3FU) +#define XBARB_SEL0_SEL0_SHIFT (0U) +#define XBARB_SEL0_SEL0(x) (((uint16_t)(((uint16_t)(x)) << XBARB_SEL0_SEL0_SHIFT)) & XBARB_SEL0_SEL0_MASK) +#define XBARB_SEL0_SEL1_MASK (0x3F00U) +#define XBARB_SEL0_SEL1_SHIFT (8U) +#define XBARB_SEL0_SEL1(x) (((uint16_t)(((uint16_t)(x)) << XBARB_SEL0_SEL1_SHIFT)) & XBARB_SEL0_SEL1_MASK) +/*! @} */ + +/*! @name SEL1 - Crossbar B Select Register 1 */ +/*! @{ */ +#define XBARB_SEL1_SEL2_MASK (0x3FU) +#define XBARB_SEL1_SEL2_SHIFT (0U) +#define XBARB_SEL1_SEL2(x) (((uint16_t)(((uint16_t)(x)) << XBARB_SEL1_SEL2_SHIFT)) & XBARB_SEL1_SEL2_MASK) +#define XBARB_SEL1_SEL3_MASK (0x3F00U) +#define XBARB_SEL1_SEL3_SHIFT (8U) +#define XBARB_SEL1_SEL3(x) (((uint16_t)(((uint16_t)(x)) << XBARB_SEL1_SEL3_SHIFT)) & XBARB_SEL1_SEL3_MASK) +/*! @} */ + +/*! @name SEL2 - Crossbar B Select Register 2 */ +/*! @{ */ +#define XBARB_SEL2_SEL4_MASK (0x3FU) +#define XBARB_SEL2_SEL4_SHIFT (0U) +#define XBARB_SEL2_SEL4(x) (((uint16_t)(((uint16_t)(x)) << XBARB_SEL2_SEL4_SHIFT)) & XBARB_SEL2_SEL4_MASK) +#define XBARB_SEL2_SEL5_MASK (0x3F00U) +#define XBARB_SEL2_SEL5_SHIFT (8U) +#define XBARB_SEL2_SEL5(x) (((uint16_t)(((uint16_t)(x)) << XBARB_SEL2_SEL5_SHIFT)) & XBARB_SEL2_SEL5_MASK) +/*! @} */ + +/*! @name SEL3 - Crossbar B Select Register 3 */ +/*! @{ */ +#define XBARB_SEL3_SEL6_MASK (0x3FU) +#define XBARB_SEL3_SEL6_SHIFT (0U) +#define XBARB_SEL3_SEL6(x) (((uint16_t)(((uint16_t)(x)) << XBARB_SEL3_SEL6_SHIFT)) & XBARB_SEL3_SEL6_MASK) +#define XBARB_SEL3_SEL7_MASK (0x3F00U) +#define XBARB_SEL3_SEL7_SHIFT (8U) +#define XBARB_SEL3_SEL7(x) (((uint16_t)(((uint16_t)(x)) << XBARB_SEL3_SEL7_SHIFT)) & XBARB_SEL3_SEL7_MASK) +/*! @} */ + +/*! @name SEL4 - Crossbar B Select Register 4 */ +/*! @{ */ +#define XBARB_SEL4_SEL8_MASK (0x3FU) +#define XBARB_SEL4_SEL8_SHIFT (0U) +#define XBARB_SEL4_SEL8(x) (((uint16_t)(((uint16_t)(x)) << XBARB_SEL4_SEL8_SHIFT)) & XBARB_SEL4_SEL8_MASK) +#define XBARB_SEL4_SEL9_MASK (0x3F00U) +#define XBARB_SEL4_SEL9_SHIFT (8U) +#define XBARB_SEL4_SEL9(x) (((uint16_t)(((uint16_t)(x)) << XBARB_SEL4_SEL9_SHIFT)) & XBARB_SEL4_SEL9_MASK) +/*! @} */ + +/*! @name SEL5 - Crossbar B Select Register 5 */ +/*! @{ */ +#define XBARB_SEL5_SEL10_MASK (0x3FU) +#define XBARB_SEL5_SEL10_SHIFT (0U) +#define XBARB_SEL5_SEL10(x) (((uint16_t)(((uint16_t)(x)) << XBARB_SEL5_SEL10_SHIFT)) & XBARB_SEL5_SEL10_MASK) +#define XBARB_SEL5_SEL11_MASK (0x3F00U) +#define XBARB_SEL5_SEL11_SHIFT (8U) +#define XBARB_SEL5_SEL11(x) (((uint16_t)(((uint16_t)(x)) << XBARB_SEL5_SEL11_SHIFT)) & XBARB_SEL5_SEL11_MASK) +/*! @} */ + +/*! @name SEL6 - Crossbar B Select Register 6 */ +/*! @{ */ +#define XBARB_SEL6_SEL12_MASK (0x3FU) +#define XBARB_SEL6_SEL12_SHIFT (0U) +#define XBARB_SEL6_SEL12(x) (((uint16_t)(((uint16_t)(x)) << XBARB_SEL6_SEL12_SHIFT)) & XBARB_SEL6_SEL12_MASK) +#define XBARB_SEL6_SEL13_MASK (0x3F00U) +#define XBARB_SEL6_SEL13_SHIFT (8U) +#define XBARB_SEL6_SEL13(x) (((uint16_t)(((uint16_t)(x)) << XBARB_SEL6_SEL13_SHIFT)) & XBARB_SEL6_SEL13_MASK) +/*! @} */ + +/*! @name SEL7 - Crossbar B Select Register 7 */ +/*! @{ */ +#define XBARB_SEL7_SEL14_MASK (0x3FU) +#define XBARB_SEL7_SEL14_SHIFT (0U) +#define XBARB_SEL7_SEL14(x) (((uint16_t)(((uint16_t)(x)) << XBARB_SEL7_SEL14_SHIFT)) & XBARB_SEL7_SEL14_MASK) +#define XBARB_SEL7_SEL15_MASK (0x3F00U) +#define XBARB_SEL7_SEL15_SHIFT (8U) +#define XBARB_SEL7_SEL15(x) (((uint16_t)(((uint16_t)(x)) << XBARB_SEL7_SEL15_SHIFT)) & XBARB_SEL7_SEL15_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group XBARB_Register_Masks */ + + +/* XBARB - Peripheral instance base addresses */ +/** Peripheral XBARB2 base address */ +#define XBARB2_BASE (0x403C0000u) +/** Peripheral XBARB2 base pointer */ +#define XBARB2 ((XBARB_Type *)XBARB2_BASE) +/** Peripheral XBARB3 base address */ +#define XBARB3_BASE (0x403C4000u) +/** Peripheral XBARB3 base pointer */ +#define XBARB3 ((XBARB_Type *)XBARB3_BASE) +/** Array initializer of XBARB peripheral base addresses */ +#define XBARB_BASE_ADDRS { 0u, 0u, XBARB2_BASE, XBARB3_BASE } +/** Array initializer of XBARB peripheral base pointers */ +#define XBARB_BASE_PTRS { (XBARB_Type *)0u, (XBARB_Type *)0u, XBARB2, XBARB3 } + +/*! + * @} + */ /* end of group XBARB_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- XTALOSC24M Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup XTALOSC24M_Peripheral_Access_Layer XTALOSC24M Peripheral Access Layer + * @{ + */ + +/** XTALOSC24M - Register Layout Typedef */ +typedef struct { + uint8_t RESERVED_0[336]; + __IO uint32_t MISC0; /**< Miscellaneous Register 0, offset: 0x150 */ + __IO uint32_t MISC0_SET; /**< Miscellaneous Register 0, offset: 0x154 */ + __IO uint32_t MISC0_CLR; /**< Miscellaneous Register 0, offset: 0x158 */ + __IO uint32_t MISC0_TOG; /**< Miscellaneous Register 0, offset: 0x15C */ + uint8_t RESERVED_1[272]; + __IO uint32_t LOWPWR_CTRL; /**< XTAL OSC (LP) Control Register, offset: 0x270 */ + __IO uint32_t LOWPWR_CTRL_SET; /**< XTAL OSC (LP) Control Register, offset: 0x274 */ + __IO uint32_t LOWPWR_CTRL_CLR; /**< XTAL OSC (LP) Control Register, offset: 0x278 */ + __IO uint32_t LOWPWR_CTRL_TOG; /**< XTAL OSC (LP) Control Register, offset: 0x27C */ + uint8_t RESERVED_2[32]; + __IO uint32_t OSC_CONFIG0; /**< XTAL OSC Configuration 0 Register, offset: 0x2A0 */ + __IO uint32_t OSC_CONFIG0_SET; /**< XTAL OSC Configuration 0 Register, offset: 0x2A4 */ + __IO uint32_t OSC_CONFIG0_CLR; /**< XTAL OSC Configuration 0 Register, offset: 0x2A8 */ + __IO uint32_t OSC_CONFIG0_TOG; /**< XTAL OSC Configuration 0 Register, offset: 0x2AC */ + __IO uint32_t OSC_CONFIG1; /**< XTAL OSC Configuration 1 Register, offset: 0x2B0 */ + __IO uint32_t OSC_CONFIG1_SET; /**< XTAL OSC Configuration 1 Register, offset: 0x2B4 */ + __IO uint32_t OSC_CONFIG1_CLR; /**< XTAL OSC Configuration 1 Register, offset: 0x2B8 */ + __IO uint32_t OSC_CONFIG1_TOG; /**< XTAL OSC Configuration 1 Register, offset: 0x2BC */ + __IO uint32_t OSC_CONFIG2; /**< XTAL OSC Configuration 2 Register, offset: 0x2C0 */ + __IO uint32_t OSC_CONFIG2_SET; /**< XTAL OSC Configuration 2 Register, offset: 0x2C4 */ + __IO uint32_t OSC_CONFIG2_CLR; /**< XTAL OSC Configuration 2 Register, offset: 0x2C8 */ + __IO uint32_t OSC_CONFIG2_TOG; /**< XTAL OSC Configuration 2 Register, offset: 0x2CC */ +} XTALOSC24M_Type; + +/* ---------------------------------------------------------------------------- + -- XTALOSC24M Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup XTALOSC24M_Register_Masks XTALOSC24M Register Masks + * @{ + */ + +/*! @name MISC0 - Miscellaneous Register 0 */ +/*! @{ */ +#define XTALOSC24M_MISC0_REFTOP_PWD_MASK (0x1U) +#define XTALOSC24M_MISC0_REFTOP_PWD_SHIFT (0U) +#define XTALOSC24M_MISC0_REFTOP_PWD(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_REFTOP_PWD_SHIFT)) & XTALOSC24M_MISC0_REFTOP_PWD_MASK) +#define XTALOSC24M_MISC0_REFTOP_SELFBIASOFF_MASK (0x8U) +#define XTALOSC24M_MISC0_REFTOP_SELFBIASOFF_SHIFT (3U) +/*! REFTOP_SELFBIASOFF + * 0b0..Uses coarse bias currents for startup + * 0b1..Uses bandgap-based bias currents for best performance. + */ +#define XTALOSC24M_MISC0_REFTOP_SELFBIASOFF(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_REFTOP_SELFBIASOFF_SHIFT)) & XTALOSC24M_MISC0_REFTOP_SELFBIASOFF_MASK) +#define XTALOSC24M_MISC0_REFTOP_VBGADJ_MASK (0x70U) +#define XTALOSC24M_MISC0_REFTOP_VBGADJ_SHIFT (4U) +/*! REFTOP_VBGADJ + * 0b000..Nominal VBG + * 0b001..VBG+0.78% + * 0b010..VBG+1.56% + * 0b011..VBG+2.34% + * 0b100..VBG-0.78% + * 0b101..VBG-1.56% + * 0b110..VBG-2.34% + * 0b111..VBG-3.12% + */ +#define XTALOSC24M_MISC0_REFTOP_VBGADJ(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_REFTOP_VBGADJ_SHIFT)) & XTALOSC24M_MISC0_REFTOP_VBGADJ_MASK) +#define XTALOSC24M_MISC0_REFTOP_VBGUP_MASK (0x80U) +#define XTALOSC24M_MISC0_REFTOP_VBGUP_SHIFT (7U) +#define XTALOSC24M_MISC0_REFTOP_VBGUP(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_REFTOP_VBGUP_SHIFT)) & XTALOSC24M_MISC0_REFTOP_VBGUP_MASK) +#define XTALOSC24M_MISC0_STOP_MODE_CONFIG_MASK (0xC00U) +#define XTALOSC24M_MISC0_STOP_MODE_CONFIG_SHIFT (10U) +/*! STOP_MODE_CONFIG + * 0b00..All analog except rtc powered down on stop mode assertion. XtalOsc=on, RCOsc=off; + * 0b01..Certain analog functions such as certain regulators left up. XtalOsc=on, RCOsc=off; + * 0b10..XtalOsc=off, RCOsc=on, Old BG=on, New BG=off. + * 0b11..XtalOsc=off, RCOsc=on, Old BG=off, New BG=on. + */ +#define XTALOSC24M_MISC0_STOP_MODE_CONFIG(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_STOP_MODE_CONFIG_SHIFT)) & XTALOSC24M_MISC0_STOP_MODE_CONFIG_MASK) +#define XTALOSC24M_MISC0_DISCON_HIGH_SNVS_MASK (0x1000U) +#define XTALOSC24M_MISC0_DISCON_HIGH_SNVS_SHIFT (12U) +/*! DISCON_HIGH_SNVS + * 0b0..Turn on the switch + * 0b1..Turn off the switch + */ +#define XTALOSC24M_MISC0_DISCON_HIGH_SNVS(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_DISCON_HIGH_SNVS_SHIFT)) & XTALOSC24M_MISC0_DISCON_HIGH_SNVS_MASK) +#define XTALOSC24M_MISC0_OSC_I_MASK (0x6000U) +#define XTALOSC24M_MISC0_OSC_I_SHIFT (13U) +/*! OSC_I + * 0b00..Nominal + * 0b01..Decrease current by 12.5% + * 0b10..Decrease current by 25.0% + * 0b11..Decrease current by 37.5% + */ +#define XTALOSC24M_MISC0_OSC_I(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_OSC_I_SHIFT)) & XTALOSC24M_MISC0_OSC_I_MASK) +#define XTALOSC24M_MISC0_OSC_XTALOK_MASK (0x8000U) +#define XTALOSC24M_MISC0_OSC_XTALOK_SHIFT (15U) +#define XTALOSC24M_MISC0_OSC_XTALOK(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_OSC_XTALOK_SHIFT)) & XTALOSC24M_MISC0_OSC_XTALOK_MASK) +#define XTALOSC24M_MISC0_OSC_XTALOK_EN_MASK (0x10000U) +#define XTALOSC24M_MISC0_OSC_XTALOK_EN_SHIFT (16U) +#define XTALOSC24M_MISC0_OSC_XTALOK_EN(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_OSC_XTALOK_EN_SHIFT)) & XTALOSC24M_MISC0_OSC_XTALOK_EN_MASK) +#define XTALOSC24M_MISC0_CLKGATE_CTRL_MASK (0x2000000U) +#define XTALOSC24M_MISC0_CLKGATE_CTRL_SHIFT (25U) +/*! CLKGATE_CTRL + * 0b0..Allow the logic to automatically gate the clock when the XTAL is powered down. + * 0b1..Prevent the logic from ever gating off the clock. + */ +#define XTALOSC24M_MISC0_CLKGATE_CTRL(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_CLKGATE_CTRL_SHIFT)) & XTALOSC24M_MISC0_CLKGATE_CTRL_MASK) +#define XTALOSC24M_MISC0_CLKGATE_DELAY_MASK (0x1C000000U) +#define XTALOSC24M_MISC0_CLKGATE_DELAY_SHIFT (26U) +/*! CLKGATE_DELAY + * 0b000..0.5ms + * 0b001..1.0ms + * 0b010..2.0ms + * 0b011..3.0ms + * 0b100..4.0ms + * 0b101..5.0ms + * 0b110..6.0ms + * 0b111..7.0ms + */ +#define XTALOSC24M_MISC0_CLKGATE_DELAY(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_CLKGATE_DELAY_SHIFT)) & XTALOSC24M_MISC0_CLKGATE_DELAY_MASK) +#define XTALOSC24M_MISC0_RTC_XTAL_SOURCE_MASK (0x20000000U) +#define XTALOSC24M_MISC0_RTC_XTAL_SOURCE_SHIFT (29U) +/*! RTC_XTAL_SOURCE + * 0b0..Internal ring oscillator + * 0b1..RTC_XTAL + */ +#define XTALOSC24M_MISC0_RTC_XTAL_SOURCE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_RTC_XTAL_SOURCE_SHIFT)) & XTALOSC24M_MISC0_RTC_XTAL_SOURCE_MASK) +#define XTALOSC24M_MISC0_XTAL_24M_PWD_MASK (0x40000000U) +#define XTALOSC24M_MISC0_XTAL_24M_PWD_SHIFT (30U) +#define XTALOSC24M_MISC0_XTAL_24M_PWD(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_XTAL_24M_PWD_SHIFT)) & XTALOSC24M_MISC0_XTAL_24M_PWD_MASK) +#define XTALOSC24M_MISC0_VID_PLL_PREDIV_MASK (0x80000000U) +#define XTALOSC24M_MISC0_VID_PLL_PREDIV_SHIFT (31U) +/*! VID_PLL_PREDIV + * 0b0..Divide by 1 + * 0b1..Divide by 2 + */ +#define XTALOSC24M_MISC0_VID_PLL_PREDIV(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_VID_PLL_PREDIV_SHIFT)) & XTALOSC24M_MISC0_VID_PLL_PREDIV_MASK) +/*! @} */ + +/*! @name MISC0_SET - Miscellaneous Register 0 */ +/*! @{ */ +#define XTALOSC24M_MISC0_SET_REFTOP_PWD_MASK (0x1U) +#define XTALOSC24M_MISC0_SET_REFTOP_PWD_SHIFT (0U) +#define XTALOSC24M_MISC0_SET_REFTOP_PWD(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_SET_REFTOP_PWD_SHIFT)) & XTALOSC24M_MISC0_SET_REFTOP_PWD_MASK) +#define XTALOSC24M_MISC0_SET_REFTOP_SELFBIASOFF_MASK (0x8U) +#define XTALOSC24M_MISC0_SET_REFTOP_SELFBIASOFF_SHIFT (3U) +/*! REFTOP_SELFBIASOFF + * 0b0..Uses coarse bias currents for startup + * 0b1..Uses bandgap-based bias currents for best performance. + */ +#define XTALOSC24M_MISC0_SET_REFTOP_SELFBIASOFF(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_SET_REFTOP_SELFBIASOFF_SHIFT)) & XTALOSC24M_MISC0_SET_REFTOP_SELFBIASOFF_MASK) +#define XTALOSC24M_MISC0_SET_REFTOP_VBGADJ_MASK (0x70U) +#define XTALOSC24M_MISC0_SET_REFTOP_VBGADJ_SHIFT (4U) +/*! REFTOP_VBGADJ + * 0b000..Nominal VBG + * 0b001..VBG+0.78% + * 0b010..VBG+1.56% + * 0b011..VBG+2.34% + * 0b100..VBG-0.78% + * 0b101..VBG-1.56% + * 0b110..VBG-2.34% + * 0b111..VBG-3.12% + */ +#define XTALOSC24M_MISC0_SET_REFTOP_VBGADJ(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_SET_REFTOP_VBGADJ_SHIFT)) & XTALOSC24M_MISC0_SET_REFTOP_VBGADJ_MASK) +#define XTALOSC24M_MISC0_SET_REFTOP_VBGUP_MASK (0x80U) +#define XTALOSC24M_MISC0_SET_REFTOP_VBGUP_SHIFT (7U) +#define XTALOSC24M_MISC0_SET_REFTOP_VBGUP(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_SET_REFTOP_VBGUP_SHIFT)) & XTALOSC24M_MISC0_SET_REFTOP_VBGUP_MASK) +#define XTALOSC24M_MISC0_SET_STOP_MODE_CONFIG_MASK (0xC00U) +#define XTALOSC24M_MISC0_SET_STOP_MODE_CONFIG_SHIFT (10U) +/*! STOP_MODE_CONFIG + * 0b00..All analog except rtc powered down on stop mode assertion. XtalOsc=on, RCOsc=off; + * 0b01..Certain analog functions such as certain regulators left up. XtalOsc=on, RCOsc=off; + * 0b10..XtalOsc=off, RCOsc=on, Old BG=on, New BG=off. + * 0b11..XtalOsc=off, RCOsc=on, Old BG=off, New BG=on. + */ +#define XTALOSC24M_MISC0_SET_STOP_MODE_CONFIG(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_SET_STOP_MODE_CONFIG_SHIFT)) & XTALOSC24M_MISC0_SET_STOP_MODE_CONFIG_MASK) +#define XTALOSC24M_MISC0_SET_DISCON_HIGH_SNVS_MASK (0x1000U) +#define XTALOSC24M_MISC0_SET_DISCON_HIGH_SNVS_SHIFT (12U) +/*! DISCON_HIGH_SNVS + * 0b0..Turn on the switch + * 0b1..Turn off the switch + */ +#define XTALOSC24M_MISC0_SET_DISCON_HIGH_SNVS(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_SET_DISCON_HIGH_SNVS_SHIFT)) & XTALOSC24M_MISC0_SET_DISCON_HIGH_SNVS_MASK) +#define XTALOSC24M_MISC0_SET_OSC_I_MASK (0x6000U) +#define XTALOSC24M_MISC0_SET_OSC_I_SHIFT (13U) +/*! OSC_I + * 0b00..Nominal + * 0b01..Decrease current by 12.5% + * 0b10..Decrease current by 25.0% + * 0b11..Decrease current by 37.5% + */ +#define XTALOSC24M_MISC0_SET_OSC_I(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_SET_OSC_I_SHIFT)) & XTALOSC24M_MISC0_SET_OSC_I_MASK) +#define XTALOSC24M_MISC0_SET_OSC_XTALOK_MASK (0x8000U) +#define XTALOSC24M_MISC0_SET_OSC_XTALOK_SHIFT (15U) +#define XTALOSC24M_MISC0_SET_OSC_XTALOK(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_SET_OSC_XTALOK_SHIFT)) & XTALOSC24M_MISC0_SET_OSC_XTALOK_MASK) +#define XTALOSC24M_MISC0_SET_OSC_XTALOK_EN_MASK (0x10000U) +#define XTALOSC24M_MISC0_SET_OSC_XTALOK_EN_SHIFT (16U) +#define XTALOSC24M_MISC0_SET_OSC_XTALOK_EN(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_SET_OSC_XTALOK_EN_SHIFT)) & XTALOSC24M_MISC0_SET_OSC_XTALOK_EN_MASK) +#define XTALOSC24M_MISC0_SET_CLKGATE_CTRL_MASK (0x2000000U) +#define XTALOSC24M_MISC0_SET_CLKGATE_CTRL_SHIFT (25U) +/*! CLKGATE_CTRL + * 0b0..Allow the logic to automatically gate the clock when the XTAL is powered down. + * 0b1..Prevent the logic from ever gating off the clock. + */ +#define XTALOSC24M_MISC0_SET_CLKGATE_CTRL(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_SET_CLKGATE_CTRL_SHIFT)) & XTALOSC24M_MISC0_SET_CLKGATE_CTRL_MASK) +#define XTALOSC24M_MISC0_SET_CLKGATE_DELAY_MASK (0x1C000000U) +#define XTALOSC24M_MISC0_SET_CLKGATE_DELAY_SHIFT (26U) +/*! CLKGATE_DELAY + * 0b000..0.5ms + * 0b001..1.0ms + * 0b010..2.0ms + * 0b011..3.0ms + * 0b100..4.0ms + * 0b101..5.0ms + * 0b110..6.0ms + * 0b111..7.0ms + */ +#define XTALOSC24M_MISC0_SET_CLKGATE_DELAY(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_SET_CLKGATE_DELAY_SHIFT)) & XTALOSC24M_MISC0_SET_CLKGATE_DELAY_MASK) +#define XTALOSC24M_MISC0_SET_RTC_XTAL_SOURCE_MASK (0x20000000U) +#define XTALOSC24M_MISC0_SET_RTC_XTAL_SOURCE_SHIFT (29U) +/*! RTC_XTAL_SOURCE + * 0b0..Internal ring oscillator + * 0b1..RTC_XTAL + */ +#define XTALOSC24M_MISC0_SET_RTC_XTAL_SOURCE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_SET_RTC_XTAL_SOURCE_SHIFT)) & XTALOSC24M_MISC0_SET_RTC_XTAL_SOURCE_MASK) +#define XTALOSC24M_MISC0_SET_XTAL_24M_PWD_MASK (0x40000000U) +#define XTALOSC24M_MISC0_SET_XTAL_24M_PWD_SHIFT (30U) +#define XTALOSC24M_MISC0_SET_XTAL_24M_PWD(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_SET_XTAL_24M_PWD_SHIFT)) & XTALOSC24M_MISC0_SET_XTAL_24M_PWD_MASK) +#define XTALOSC24M_MISC0_SET_VID_PLL_PREDIV_MASK (0x80000000U) +#define XTALOSC24M_MISC0_SET_VID_PLL_PREDIV_SHIFT (31U) +/*! VID_PLL_PREDIV + * 0b0..Divide by 1 + * 0b1..Divide by 2 + */ +#define XTALOSC24M_MISC0_SET_VID_PLL_PREDIV(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_SET_VID_PLL_PREDIV_SHIFT)) & XTALOSC24M_MISC0_SET_VID_PLL_PREDIV_MASK) +/*! @} */ + +/*! @name MISC0_CLR - Miscellaneous Register 0 */ +/*! @{ */ +#define XTALOSC24M_MISC0_CLR_REFTOP_PWD_MASK (0x1U) +#define XTALOSC24M_MISC0_CLR_REFTOP_PWD_SHIFT (0U) +#define XTALOSC24M_MISC0_CLR_REFTOP_PWD(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_CLR_REFTOP_PWD_SHIFT)) & XTALOSC24M_MISC0_CLR_REFTOP_PWD_MASK) +#define XTALOSC24M_MISC0_CLR_REFTOP_SELFBIASOFF_MASK (0x8U) +#define XTALOSC24M_MISC0_CLR_REFTOP_SELFBIASOFF_SHIFT (3U) +/*! REFTOP_SELFBIASOFF + * 0b0..Uses coarse bias currents for startup + * 0b1..Uses bandgap-based bias currents for best performance. + */ +#define XTALOSC24M_MISC0_CLR_REFTOP_SELFBIASOFF(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_CLR_REFTOP_SELFBIASOFF_SHIFT)) & XTALOSC24M_MISC0_CLR_REFTOP_SELFBIASOFF_MASK) +#define XTALOSC24M_MISC0_CLR_REFTOP_VBGADJ_MASK (0x70U) +#define XTALOSC24M_MISC0_CLR_REFTOP_VBGADJ_SHIFT (4U) +/*! REFTOP_VBGADJ + * 0b000..Nominal VBG + * 0b001..VBG+0.78% + * 0b010..VBG+1.56% + * 0b011..VBG+2.34% + * 0b100..VBG-0.78% + * 0b101..VBG-1.56% + * 0b110..VBG-2.34% + * 0b111..VBG-3.12% + */ +#define XTALOSC24M_MISC0_CLR_REFTOP_VBGADJ(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_CLR_REFTOP_VBGADJ_SHIFT)) & XTALOSC24M_MISC0_CLR_REFTOP_VBGADJ_MASK) +#define XTALOSC24M_MISC0_CLR_REFTOP_VBGUP_MASK (0x80U) +#define XTALOSC24M_MISC0_CLR_REFTOP_VBGUP_SHIFT (7U) +#define XTALOSC24M_MISC0_CLR_REFTOP_VBGUP(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_CLR_REFTOP_VBGUP_SHIFT)) & XTALOSC24M_MISC0_CLR_REFTOP_VBGUP_MASK) +#define XTALOSC24M_MISC0_CLR_STOP_MODE_CONFIG_MASK (0xC00U) +#define XTALOSC24M_MISC0_CLR_STOP_MODE_CONFIG_SHIFT (10U) +/*! STOP_MODE_CONFIG + * 0b00..All analog except rtc powered down on stop mode assertion. XtalOsc=on, RCOsc=off; + * 0b01..Certain analog functions such as certain regulators left up. XtalOsc=on, RCOsc=off; + * 0b10..XtalOsc=off, RCOsc=on, Old BG=on, New BG=off. + * 0b11..XtalOsc=off, RCOsc=on, Old BG=off, New BG=on. + */ +#define XTALOSC24M_MISC0_CLR_STOP_MODE_CONFIG(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_CLR_STOP_MODE_CONFIG_SHIFT)) & XTALOSC24M_MISC0_CLR_STOP_MODE_CONFIG_MASK) +#define XTALOSC24M_MISC0_CLR_DISCON_HIGH_SNVS_MASK (0x1000U) +#define XTALOSC24M_MISC0_CLR_DISCON_HIGH_SNVS_SHIFT (12U) +/*! DISCON_HIGH_SNVS + * 0b0..Turn on the switch + * 0b1..Turn off the switch + */ +#define XTALOSC24M_MISC0_CLR_DISCON_HIGH_SNVS(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_CLR_DISCON_HIGH_SNVS_SHIFT)) & XTALOSC24M_MISC0_CLR_DISCON_HIGH_SNVS_MASK) +#define XTALOSC24M_MISC0_CLR_OSC_I_MASK (0x6000U) +#define XTALOSC24M_MISC0_CLR_OSC_I_SHIFT (13U) +/*! OSC_I + * 0b00..Nominal + * 0b01..Decrease current by 12.5% + * 0b10..Decrease current by 25.0% + * 0b11..Decrease current by 37.5% + */ +#define XTALOSC24M_MISC0_CLR_OSC_I(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_CLR_OSC_I_SHIFT)) & XTALOSC24M_MISC0_CLR_OSC_I_MASK) +#define XTALOSC24M_MISC0_CLR_OSC_XTALOK_MASK (0x8000U) +#define XTALOSC24M_MISC0_CLR_OSC_XTALOK_SHIFT (15U) +#define XTALOSC24M_MISC0_CLR_OSC_XTALOK(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_CLR_OSC_XTALOK_SHIFT)) & XTALOSC24M_MISC0_CLR_OSC_XTALOK_MASK) +#define XTALOSC24M_MISC0_CLR_OSC_XTALOK_EN_MASK (0x10000U) +#define XTALOSC24M_MISC0_CLR_OSC_XTALOK_EN_SHIFT (16U) +#define XTALOSC24M_MISC0_CLR_OSC_XTALOK_EN(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_CLR_OSC_XTALOK_EN_SHIFT)) & XTALOSC24M_MISC0_CLR_OSC_XTALOK_EN_MASK) +#define XTALOSC24M_MISC0_CLR_CLKGATE_CTRL_MASK (0x2000000U) +#define XTALOSC24M_MISC0_CLR_CLKGATE_CTRL_SHIFT (25U) +/*! CLKGATE_CTRL + * 0b0..Allow the logic to automatically gate the clock when the XTAL is powered down. + * 0b1..Prevent the logic from ever gating off the clock. + */ +#define XTALOSC24M_MISC0_CLR_CLKGATE_CTRL(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_CLR_CLKGATE_CTRL_SHIFT)) & XTALOSC24M_MISC0_CLR_CLKGATE_CTRL_MASK) +#define XTALOSC24M_MISC0_CLR_CLKGATE_DELAY_MASK (0x1C000000U) +#define XTALOSC24M_MISC0_CLR_CLKGATE_DELAY_SHIFT (26U) +/*! CLKGATE_DELAY + * 0b000..0.5ms + * 0b001..1.0ms + * 0b010..2.0ms + * 0b011..3.0ms + * 0b100..4.0ms + * 0b101..5.0ms + * 0b110..6.0ms + * 0b111..7.0ms + */ +#define XTALOSC24M_MISC0_CLR_CLKGATE_DELAY(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_CLR_CLKGATE_DELAY_SHIFT)) & XTALOSC24M_MISC0_CLR_CLKGATE_DELAY_MASK) +#define XTALOSC24M_MISC0_CLR_RTC_XTAL_SOURCE_MASK (0x20000000U) +#define XTALOSC24M_MISC0_CLR_RTC_XTAL_SOURCE_SHIFT (29U) +/*! RTC_XTAL_SOURCE + * 0b0..Internal ring oscillator + * 0b1..RTC_XTAL + */ +#define XTALOSC24M_MISC0_CLR_RTC_XTAL_SOURCE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_CLR_RTC_XTAL_SOURCE_SHIFT)) & XTALOSC24M_MISC0_CLR_RTC_XTAL_SOURCE_MASK) +#define XTALOSC24M_MISC0_CLR_XTAL_24M_PWD_MASK (0x40000000U) +#define XTALOSC24M_MISC0_CLR_XTAL_24M_PWD_SHIFT (30U) +#define XTALOSC24M_MISC0_CLR_XTAL_24M_PWD(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_CLR_XTAL_24M_PWD_SHIFT)) & XTALOSC24M_MISC0_CLR_XTAL_24M_PWD_MASK) +#define XTALOSC24M_MISC0_CLR_VID_PLL_PREDIV_MASK (0x80000000U) +#define XTALOSC24M_MISC0_CLR_VID_PLL_PREDIV_SHIFT (31U) +/*! VID_PLL_PREDIV + * 0b0..Divide by 1 + * 0b1..Divide by 2 + */ +#define XTALOSC24M_MISC0_CLR_VID_PLL_PREDIV(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_CLR_VID_PLL_PREDIV_SHIFT)) & XTALOSC24M_MISC0_CLR_VID_PLL_PREDIV_MASK) +/*! @} */ + +/*! @name MISC0_TOG - Miscellaneous Register 0 */ +/*! @{ */ +#define XTALOSC24M_MISC0_TOG_REFTOP_PWD_MASK (0x1U) +#define XTALOSC24M_MISC0_TOG_REFTOP_PWD_SHIFT (0U) +#define XTALOSC24M_MISC0_TOG_REFTOP_PWD(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_TOG_REFTOP_PWD_SHIFT)) & XTALOSC24M_MISC0_TOG_REFTOP_PWD_MASK) +#define XTALOSC24M_MISC0_TOG_REFTOP_SELFBIASOFF_MASK (0x8U) +#define XTALOSC24M_MISC0_TOG_REFTOP_SELFBIASOFF_SHIFT (3U) +/*! REFTOP_SELFBIASOFF + * 0b0..Uses coarse bias currents for startup + * 0b1..Uses bandgap-based bias currents for best performance. + */ +#define XTALOSC24M_MISC0_TOG_REFTOP_SELFBIASOFF(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_TOG_REFTOP_SELFBIASOFF_SHIFT)) & XTALOSC24M_MISC0_TOG_REFTOP_SELFBIASOFF_MASK) +#define XTALOSC24M_MISC0_TOG_REFTOP_VBGADJ_MASK (0x70U) +#define XTALOSC24M_MISC0_TOG_REFTOP_VBGADJ_SHIFT (4U) +/*! REFTOP_VBGADJ + * 0b000..Nominal VBG + * 0b001..VBG+0.78% + * 0b010..VBG+1.56% + * 0b011..VBG+2.34% + * 0b100..VBG-0.78% + * 0b101..VBG-1.56% + * 0b110..VBG-2.34% + * 0b111..VBG-3.12% + */ +#define XTALOSC24M_MISC0_TOG_REFTOP_VBGADJ(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_TOG_REFTOP_VBGADJ_SHIFT)) & XTALOSC24M_MISC0_TOG_REFTOP_VBGADJ_MASK) +#define XTALOSC24M_MISC0_TOG_REFTOP_VBGUP_MASK (0x80U) +#define XTALOSC24M_MISC0_TOG_REFTOP_VBGUP_SHIFT (7U) +#define XTALOSC24M_MISC0_TOG_REFTOP_VBGUP(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_TOG_REFTOP_VBGUP_SHIFT)) & XTALOSC24M_MISC0_TOG_REFTOP_VBGUP_MASK) +#define XTALOSC24M_MISC0_TOG_STOP_MODE_CONFIG_MASK (0xC00U) +#define XTALOSC24M_MISC0_TOG_STOP_MODE_CONFIG_SHIFT (10U) +/*! STOP_MODE_CONFIG + * 0b00..All analog except rtc powered down on stop mode assertion. XtalOsc=on, RCOsc=off; + * 0b01..Certain analog functions such as certain regulators left up. XtalOsc=on, RCOsc=off; + * 0b10..XtalOsc=off, RCOsc=on, Old BG=on, New BG=off. + * 0b11..XtalOsc=off, RCOsc=on, Old BG=off, New BG=on. + */ +#define XTALOSC24M_MISC0_TOG_STOP_MODE_CONFIG(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_TOG_STOP_MODE_CONFIG_SHIFT)) & XTALOSC24M_MISC0_TOG_STOP_MODE_CONFIG_MASK) +#define XTALOSC24M_MISC0_TOG_DISCON_HIGH_SNVS_MASK (0x1000U) +#define XTALOSC24M_MISC0_TOG_DISCON_HIGH_SNVS_SHIFT (12U) +/*! DISCON_HIGH_SNVS + * 0b0..Turn on the switch + * 0b1..Turn off the switch + */ +#define XTALOSC24M_MISC0_TOG_DISCON_HIGH_SNVS(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_TOG_DISCON_HIGH_SNVS_SHIFT)) & XTALOSC24M_MISC0_TOG_DISCON_HIGH_SNVS_MASK) +#define XTALOSC24M_MISC0_TOG_OSC_I_MASK (0x6000U) +#define XTALOSC24M_MISC0_TOG_OSC_I_SHIFT (13U) +/*! OSC_I + * 0b00..Nominal + * 0b01..Decrease current by 12.5% + * 0b10..Decrease current by 25.0% + * 0b11..Decrease current by 37.5% + */ +#define XTALOSC24M_MISC0_TOG_OSC_I(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_TOG_OSC_I_SHIFT)) & XTALOSC24M_MISC0_TOG_OSC_I_MASK) +#define XTALOSC24M_MISC0_TOG_OSC_XTALOK_MASK (0x8000U) +#define XTALOSC24M_MISC0_TOG_OSC_XTALOK_SHIFT (15U) +#define XTALOSC24M_MISC0_TOG_OSC_XTALOK(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_TOG_OSC_XTALOK_SHIFT)) & XTALOSC24M_MISC0_TOG_OSC_XTALOK_MASK) +#define XTALOSC24M_MISC0_TOG_OSC_XTALOK_EN_MASK (0x10000U) +#define XTALOSC24M_MISC0_TOG_OSC_XTALOK_EN_SHIFT (16U) +#define XTALOSC24M_MISC0_TOG_OSC_XTALOK_EN(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_TOG_OSC_XTALOK_EN_SHIFT)) & XTALOSC24M_MISC0_TOG_OSC_XTALOK_EN_MASK) +#define XTALOSC24M_MISC0_TOG_CLKGATE_CTRL_MASK (0x2000000U) +#define XTALOSC24M_MISC0_TOG_CLKGATE_CTRL_SHIFT (25U) +/*! CLKGATE_CTRL + * 0b0..Allow the logic to automatically gate the clock when the XTAL is powered down. + * 0b1..Prevent the logic from ever gating off the clock. + */ +#define XTALOSC24M_MISC0_TOG_CLKGATE_CTRL(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_TOG_CLKGATE_CTRL_SHIFT)) & XTALOSC24M_MISC0_TOG_CLKGATE_CTRL_MASK) +#define XTALOSC24M_MISC0_TOG_CLKGATE_DELAY_MASK (0x1C000000U) +#define XTALOSC24M_MISC0_TOG_CLKGATE_DELAY_SHIFT (26U) +/*! CLKGATE_DELAY + * 0b000..0.5ms + * 0b001..1.0ms + * 0b010..2.0ms + * 0b011..3.0ms + * 0b100..4.0ms + * 0b101..5.0ms + * 0b110..6.0ms + * 0b111..7.0ms + */ +#define XTALOSC24M_MISC0_TOG_CLKGATE_DELAY(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_TOG_CLKGATE_DELAY_SHIFT)) & XTALOSC24M_MISC0_TOG_CLKGATE_DELAY_MASK) +#define XTALOSC24M_MISC0_TOG_RTC_XTAL_SOURCE_MASK (0x20000000U) +#define XTALOSC24M_MISC0_TOG_RTC_XTAL_SOURCE_SHIFT (29U) +/*! RTC_XTAL_SOURCE + * 0b0..Internal ring oscillator + * 0b1..RTC_XTAL + */ +#define XTALOSC24M_MISC0_TOG_RTC_XTAL_SOURCE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_TOG_RTC_XTAL_SOURCE_SHIFT)) & XTALOSC24M_MISC0_TOG_RTC_XTAL_SOURCE_MASK) +#define XTALOSC24M_MISC0_TOG_XTAL_24M_PWD_MASK (0x40000000U) +#define XTALOSC24M_MISC0_TOG_XTAL_24M_PWD_SHIFT (30U) +#define XTALOSC24M_MISC0_TOG_XTAL_24M_PWD(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_TOG_XTAL_24M_PWD_SHIFT)) & XTALOSC24M_MISC0_TOG_XTAL_24M_PWD_MASK) +#define XTALOSC24M_MISC0_TOG_VID_PLL_PREDIV_MASK (0x80000000U) +#define XTALOSC24M_MISC0_TOG_VID_PLL_PREDIV_SHIFT (31U) +/*! VID_PLL_PREDIV + * 0b0..Divide by 1 + * 0b1..Divide by 2 + */ +#define XTALOSC24M_MISC0_TOG_VID_PLL_PREDIV(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_TOG_VID_PLL_PREDIV_SHIFT)) & XTALOSC24M_MISC0_TOG_VID_PLL_PREDIV_MASK) +/*! @} */ + +/*! @name LOWPWR_CTRL - XTAL OSC (LP) Control Register */ +/*! @{ */ +#define XTALOSC24M_LOWPWR_CTRL_RC_OSC_EN_MASK (0x1U) +#define XTALOSC24M_LOWPWR_CTRL_RC_OSC_EN_SHIFT (0U) +/*! RC_OSC_EN + * 0b0..Use XTAL OSC to source the 24MHz clock + * 0b1..Use RC OSC + */ +#define XTALOSC24M_LOWPWR_CTRL_RC_OSC_EN(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_RC_OSC_EN_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_RC_OSC_EN_MASK) +#define XTALOSC24M_LOWPWR_CTRL_OSC_SEL_MASK (0x10U) +#define XTALOSC24M_LOWPWR_CTRL_OSC_SEL_SHIFT (4U) +/*! OSC_SEL + * 0b0..XTAL OSC + * 0b1..RC OSC + */ +#define XTALOSC24M_LOWPWR_CTRL_OSC_SEL(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_OSC_SEL_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_OSC_SEL_MASK) +#define XTALOSC24M_LOWPWR_CTRL_LPBG_SEL_MASK (0x20U) +#define XTALOSC24M_LOWPWR_CTRL_LPBG_SEL_SHIFT (5U) +/*! LPBG_SEL + * 0b0..Normal power bandgap + * 0b1..Low power bandgap + */ +#define XTALOSC24M_LOWPWR_CTRL_LPBG_SEL(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_LPBG_SEL_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_LPBG_SEL_MASK) +#define XTALOSC24M_LOWPWR_CTRL_LPBG_TEST_MASK (0x40U) +#define XTALOSC24M_LOWPWR_CTRL_LPBG_TEST_SHIFT (6U) +#define XTALOSC24M_LOWPWR_CTRL_LPBG_TEST(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_LPBG_TEST_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_LPBG_TEST_MASK) +#define XTALOSC24M_LOWPWR_CTRL_REFTOP_IBIAS_OFF_MASK (0x80U) +#define XTALOSC24M_LOWPWR_CTRL_REFTOP_IBIAS_OFF_SHIFT (7U) +#define XTALOSC24M_LOWPWR_CTRL_REFTOP_IBIAS_OFF(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_REFTOP_IBIAS_OFF_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_REFTOP_IBIAS_OFF_MASK) +#define XTALOSC24M_LOWPWR_CTRL_L1_PWRGATE_MASK (0x100U) +#define XTALOSC24M_LOWPWR_CTRL_L1_PWRGATE_SHIFT (8U) +#define XTALOSC24M_LOWPWR_CTRL_L1_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_L1_PWRGATE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_L1_PWRGATE_MASK) +#define XTALOSC24M_LOWPWR_CTRL_L2_PWRGATE_MASK (0x200U) +#define XTALOSC24M_LOWPWR_CTRL_L2_PWRGATE_SHIFT (9U) +#define XTALOSC24M_LOWPWR_CTRL_L2_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_L2_PWRGATE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_L2_PWRGATE_MASK) +#define XTALOSC24M_LOWPWR_CTRL_CPU_PWRGATE_MASK (0x400U) +#define XTALOSC24M_LOWPWR_CTRL_CPU_PWRGATE_SHIFT (10U) +#define XTALOSC24M_LOWPWR_CTRL_CPU_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_CPU_PWRGATE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_CPU_PWRGATE_MASK) +#define XTALOSC24M_LOWPWR_CTRL_DISPLAY_PWRGATE_MASK (0x800U) +#define XTALOSC24M_LOWPWR_CTRL_DISPLAY_PWRGATE_SHIFT (11U) +#define XTALOSC24M_LOWPWR_CTRL_DISPLAY_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_DISPLAY_PWRGATE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_DISPLAY_PWRGATE_MASK) +#define XTALOSC24M_LOWPWR_CTRL_RCOSC_CG_OVERRIDE_MASK (0x2000U) +#define XTALOSC24M_LOWPWR_CTRL_RCOSC_CG_OVERRIDE_SHIFT (13U) +#define XTALOSC24M_LOWPWR_CTRL_RCOSC_CG_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_RCOSC_CG_OVERRIDE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_RCOSC_CG_OVERRIDE_MASK) +#define XTALOSC24M_LOWPWR_CTRL_XTALOSC_PWRUP_DELAY_MASK (0xC000U) +#define XTALOSC24M_LOWPWR_CTRL_XTALOSC_PWRUP_DELAY_SHIFT (14U) +/*! XTALOSC_PWRUP_DELAY + * 0b00..0.25ms + * 0b01..0.5ms + * 0b10..1ms + * 0b11..2ms + */ +#define XTALOSC24M_LOWPWR_CTRL_XTALOSC_PWRUP_DELAY(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_XTALOSC_PWRUP_DELAY_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_XTALOSC_PWRUP_DELAY_MASK) +#define XTALOSC24M_LOWPWR_CTRL_XTALOSC_PWRUP_STAT_MASK (0x10000U) +#define XTALOSC24M_LOWPWR_CTRL_XTALOSC_PWRUP_STAT_SHIFT (16U) +/*! XTALOSC_PWRUP_STAT + * 0b0..Not stable + * 0b1..Stable and ready to use + */ +#define XTALOSC24M_LOWPWR_CTRL_XTALOSC_PWRUP_STAT(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_XTALOSC_PWRUP_STAT_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_XTALOSC_PWRUP_STAT_MASK) +#define XTALOSC24M_LOWPWR_CTRL_MIX_PWRGATE_MASK (0x20000U) +#define XTALOSC24M_LOWPWR_CTRL_MIX_PWRGATE_SHIFT (17U) +#define XTALOSC24M_LOWPWR_CTRL_MIX_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_MIX_PWRGATE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_MIX_PWRGATE_MASK) +#define XTALOSC24M_LOWPWR_CTRL_GPU_PWRGATE_MASK (0x40000U) +#define XTALOSC24M_LOWPWR_CTRL_GPU_PWRGATE_SHIFT (18U) +#define XTALOSC24M_LOWPWR_CTRL_GPU_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_GPU_PWRGATE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_GPU_PWRGATE_MASK) +/*! @} */ + +/*! @name LOWPWR_CTRL_SET - XTAL OSC (LP) Control Register */ +/*! @{ */ +#define XTALOSC24M_LOWPWR_CTRL_SET_RC_OSC_EN_MASK (0x1U) +#define XTALOSC24M_LOWPWR_CTRL_SET_RC_OSC_EN_SHIFT (0U) +/*! RC_OSC_EN + * 0b0..Use XTAL OSC to source the 24MHz clock + * 0b1..Use RC OSC + */ +#define XTALOSC24M_LOWPWR_CTRL_SET_RC_OSC_EN(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_SET_RC_OSC_EN_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_SET_RC_OSC_EN_MASK) +#define XTALOSC24M_LOWPWR_CTRL_SET_OSC_SEL_MASK (0x10U) +#define XTALOSC24M_LOWPWR_CTRL_SET_OSC_SEL_SHIFT (4U) +/*! OSC_SEL + * 0b0..XTAL OSC + * 0b1..RC OSC + */ +#define XTALOSC24M_LOWPWR_CTRL_SET_OSC_SEL(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_SET_OSC_SEL_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_SET_OSC_SEL_MASK) +#define XTALOSC24M_LOWPWR_CTRL_SET_LPBG_SEL_MASK (0x20U) +#define XTALOSC24M_LOWPWR_CTRL_SET_LPBG_SEL_SHIFT (5U) +/*! LPBG_SEL + * 0b0..Normal power bandgap + * 0b1..Low power bandgap + */ +#define XTALOSC24M_LOWPWR_CTRL_SET_LPBG_SEL(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_SET_LPBG_SEL_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_SET_LPBG_SEL_MASK) +#define XTALOSC24M_LOWPWR_CTRL_SET_LPBG_TEST_MASK (0x40U) +#define XTALOSC24M_LOWPWR_CTRL_SET_LPBG_TEST_SHIFT (6U) +#define XTALOSC24M_LOWPWR_CTRL_SET_LPBG_TEST(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_SET_LPBG_TEST_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_SET_LPBG_TEST_MASK) +#define XTALOSC24M_LOWPWR_CTRL_SET_REFTOP_IBIAS_OFF_MASK (0x80U) +#define XTALOSC24M_LOWPWR_CTRL_SET_REFTOP_IBIAS_OFF_SHIFT (7U) +#define XTALOSC24M_LOWPWR_CTRL_SET_REFTOP_IBIAS_OFF(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_SET_REFTOP_IBIAS_OFF_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_SET_REFTOP_IBIAS_OFF_MASK) +#define XTALOSC24M_LOWPWR_CTRL_SET_L1_PWRGATE_MASK (0x100U) +#define XTALOSC24M_LOWPWR_CTRL_SET_L1_PWRGATE_SHIFT (8U) +#define XTALOSC24M_LOWPWR_CTRL_SET_L1_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_SET_L1_PWRGATE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_SET_L1_PWRGATE_MASK) +#define XTALOSC24M_LOWPWR_CTRL_SET_L2_PWRGATE_MASK (0x200U) +#define XTALOSC24M_LOWPWR_CTRL_SET_L2_PWRGATE_SHIFT (9U) +#define XTALOSC24M_LOWPWR_CTRL_SET_L2_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_SET_L2_PWRGATE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_SET_L2_PWRGATE_MASK) +#define XTALOSC24M_LOWPWR_CTRL_SET_CPU_PWRGATE_MASK (0x400U) +#define XTALOSC24M_LOWPWR_CTRL_SET_CPU_PWRGATE_SHIFT (10U) +#define XTALOSC24M_LOWPWR_CTRL_SET_CPU_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_SET_CPU_PWRGATE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_SET_CPU_PWRGATE_MASK) +#define XTALOSC24M_LOWPWR_CTRL_SET_DISPLAY_PWRGATE_MASK (0x800U) +#define XTALOSC24M_LOWPWR_CTRL_SET_DISPLAY_PWRGATE_SHIFT (11U) +#define XTALOSC24M_LOWPWR_CTRL_SET_DISPLAY_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_SET_DISPLAY_PWRGATE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_SET_DISPLAY_PWRGATE_MASK) +#define XTALOSC24M_LOWPWR_CTRL_SET_RCOSC_CG_OVERRIDE_MASK (0x2000U) +#define XTALOSC24M_LOWPWR_CTRL_SET_RCOSC_CG_OVERRIDE_SHIFT (13U) +#define XTALOSC24M_LOWPWR_CTRL_SET_RCOSC_CG_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_SET_RCOSC_CG_OVERRIDE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_SET_RCOSC_CG_OVERRIDE_MASK) +#define XTALOSC24M_LOWPWR_CTRL_SET_XTALOSC_PWRUP_DELAY_MASK (0xC000U) +#define XTALOSC24M_LOWPWR_CTRL_SET_XTALOSC_PWRUP_DELAY_SHIFT (14U) +/*! XTALOSC_PWRUP_DELAY + * 0b00..0.25ms + * 0b01..0.5ms + * 0b10..1ms + * 0b11..2ms + */ +#define XTALOSC24M_LOWPWR_CTRL_SET_XTALOSC_PWRUP_DELAY(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_SET_XTALOSC_PWRUP_DELAY_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_SET_XTALOSC_PWRUP_DELAY_MASK) +#define XTALOSC24M_LOWPWR_CTRL_SET_XTALOSC_PWRUP_STAT_MASK (0x10000U) +#define XTALOSC24M_LOWPWR_CTRL_SET_XTALOSC_PWRUP_STAT_SHIFT (16U) +/*! XTALOSC_PWRUP_STAT + * 0b0..Not stable + * 0b1..Stable and ready to use + */ +#define XTALOSC24M_LOWPWR_CTRL_SET_XTALOSC_PWRUP_STAT(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_SET_XTALOSC_PWRUP_STAT_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_SET_XTALOSC_PWRUP_STAT_MASK) +#define XTALOSC24M_LOWPWR_CTRL_SET_MIX_PWRGATE_MASK (0x20000U) +#define XTALOSC24M_LOWPWR_CTRL_SET_MIX_PWRGATE_SHIFT (17U) +#define XTALOSC24M_LOWPWR_CTRL_SET_MIX_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_SET_MIX_PWRGATE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_SET_MIX_PWRGATE_MASK) +#define XTALOSC24M_LOWPWR_CTRL_SET_GPU_PWRGATE_MASK (0x40000U) +#define XTALOSC24M_LOWPWR_CTRL_SET_GPU_PWRGATE_SHIFT (18U) +#define XTALOSC24M_LOWPWR_CTRL_SET_GPU_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_SET_GPU_PWRGATE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_SET_GPU_PWRGATE_MASK) +/*! @} */ + +/*! @name LOWPWR_CTRL_CLR - XTAL OSC (LP) Control Register */ +/*! @{ */ +#define XTALOSC24M_LOWPWR_CTRL_CLR_RC_OSC_EN_MASK (0x1U) +#define XTALOSC24M_LOWPWR_CTRL_CLR_RC_OSC_EN_SHIFT (0U) +/*! RC_OSC_EN + * 0b0..Use XTAL OSC to source the 24MHz clock + * 0b1..Use RC OSC + */ +#define XTALOSC24M_LOWPWR_CTRL_CLR_RC_OSC_EN(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_CLR_RC_OSC_EN_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_CLR_RC_OSC_EN_MASK) +#define XTALOSC24M_LOWPWR_CTRL_CLR_OSC_SEL_MASK (0x10U) +#define XTALOSC24M_LOWPWR_CTRL_CLR_OSC_SEL_SHIFT (4U) +/*! OSC_SEL + * 0b0..XTAL OSC + * 0b1..RC OSC + */ +#define XTALOSC24M_LOWPWR_CTRL_CLR_OSC_SEL(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_CLR_OSC_SEL_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_CLR_OSC_SEL_MASK) +#define XTALOSC24M_LOWPWR_CTRL_CLR_LPBG_SEL_MASK (0x20U) +#define XTALOSC24M_LOWPWR_CTRL_CLR_LPBG_SEL_SHIFT (5U) +/*! LPBG_SEL + * 0b0..Normal power bandgap + * 0b1..Low power bandgap + */ +#define XTALOSC24M_LOWPWR_CTRL_CLR_LPBG_SEL(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_CLR_LPBG_SEL_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_CLR_LPBG_SEL_MASK) +#define XTALOSC24M_LOWPWR_CTRL_CLR_LPBG_TEST_MASK (0x40U) +#define XTALOSC24M_LOWPWR_CTRL_CLR_LPBG_TEST_SHIFT (6U) +#define XTALOSC24M_LOWPWR_CTRL_CLR_LPBG_TEST(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_CLR_LPBG_TEST_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_CLR_LPBG_TEST_MASK) +#define XTALOSC24M_LOWPWR_CTRL_CLR_REFTOP_IBIAS_OFF_MASK (0x80U) +#define XTALOSC24M_LOWPWR_CTRL_CLR_REFTOP_IBIAS_OFF_SHIFT (7U) +#define XTALOSC24M_LOWPWR_CTRL_CLR_REFTOP_IBIAS_OFF(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_CLR_REFTOP_IBIAS_OFF_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_CLR_REFTOP_IBIAS_OFF_MASK) +#define XTALOSC24M_LOWPWR_CTRL_CLR_L1_PWRGATE_MASK (0x100U) +#define XTALOSC24M_LOWPWR_CTRL_CLR_L1_PWRGATE_SHIFT (8U) +#define XTALOSC24M_LOWPWR_CTRL_CLR_L1_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_CLR_L1_PWRGATE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_CLR_L1_PWRGATE_MASK) +#define XTALOSC24M_LOWPWR_CTRL_CLR_L2_PWRGATE_MASK (0x200U) +#define XTALOSC24M_LOWPWR_CTRL_CLR_L2_PWRGATE_SHIFT (9U) +#define XTALOSC24M_LOWPWR_CTRL_CLR_L2_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_CLR_L2_PWRGATE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_CLR_L2_PWRGATE_MASK) +#define XTALOSC24M_LOWPWR_CTRL_CLR_CPU_PWRGATE_MASK (0x400U) +#define XTALOSC24M_LOWPWR_CTRL_CLR_CPU_PWRGATE_SHIFT (10U) +#define XTALOSC24M_LOWPWR_CTRL_CLR_CPU_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_CLR_CPU_PWRGATE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_CLR_CPU_PWRGATE_MASK) +#define XTALOSC24M_LOWPWR_CTRL_CLR_DISPLAY_PWRGATE_MASK (0x800U) +#define XTALOSC24M_LOWPWR_CTRL_CLR_DISPLAY_PWRGATE_SHIFT (11U) +#define XTALOSC24M_LOWPWR_CTRL_CLR_DISPLAY_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_CLR_DISPLAY_PWRGATE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_CLR_DISPLAY_PWRGATE_MASK) +#define XTALOSC24M_LOWPWR_CTRL_CLR_RCOSC_CG_OVERRIDE_MASK (0x2000U) +#define XTALOSC24M_LOWPWR_CTRL_CLR_RCOSC_CG_OVERRIDE_SHIFT (13U) +#define XTALOSC24M_LOWPWR_CTRL_CLR_RCOSC_CG_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_CLR_RCOSC_CG_OVERRIDE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_CLR_RCOSC_CG_OVERRIDE_MASK) +#define XTALOSC24M_LOWPWR_CTRL_CLR_XTALOSC_PWRUP_DELAY_MASK (0xC000U) +#define XTALOSC24M_LOWPWR_CTRL_CLR_XTALOSC_PWRUP_DELAY_SHIFT (14U) +/*! XTALOSC_PWRUP_DELAY + * 0b00..0.25ms + * 0b01..0.5ms + * 0b10..1ms + * 0b11..2ms + */ +#define XTALOSC24M_LOWPWR_CTRL_CLR_XTALOSC_PWRUP_DELAY(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_CLR_XTALOSC_PWRUP_DELAY_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_CLR_XTALOSC_PWRUP_DELAY_MASK) +#define XTALOSC24M_LOWPWR_CTRL_CLR_XTALOSC_PWRUP_STAT_MASK (0x10000U) +#define XTALOSC24M_LOWPWR_CTRL_CLR_XTALOSC_PWRUP_STAT_SHIFT (16U) +/*! XTALOSC_PWRUP_STAT + * 0b0..Not stable + * 0b1..Stable and ready to use + */ +#define XTALOSC24M_LOWPWR_CTRL_CLR_XTALOSC_PWRUP_STAT(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_CLR_XTALOSC_PWRUP_STAT_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_CLR_XTALOSC_PWRUP_STAT_MASK) +#define XTALOSC24M_LOWPWR_CTRL_CLR_MIX_PWRGATE_MASK (0x20000U) +#define XTALOSC24M_LOWPWR_CTRL_CLR_MIX_PWRGATE_SHIFT (17U) +#define XTALOSC24M_LOWPWR_CTRL_CLR_MIX_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_CLR_MIX_PWRGATE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_CLR_MIX_PWRGATE_MASK) +#define XTALOSC24M_LOWPWR_CTRL_CLR_GPU_PWRGATE_MASK (0x40000U) +#define XTALOSC24M_LOWPWR_CTRL_CLR_GPU_PWRGATE_SHIFT (18U) +#define XTALOSC24M_LOWPWR_CTRL_CLR_GPU_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_CLR_GPU_PWRGATE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_CLR_GPU_PWRGATE_MASK) +/*! @} */ + +/*! @name LOWPWR_CTRL_TOG - XTAL OSC (LP) Control Register */ +/*! @{ */ +#define XTALOSC24M_LOWPWR_CTRL_TOG_RC_OSC_EN_MASK (0x1U) +#define XTALOSC24M_LOWPWR_CTRL_TOG_RC_OSC_EN_SHIFT (0U) +/*! RC_OSC_EN + * 0b0..Use XTAL OSC to source the 24MHz clock + * 0b1..Use RC OSC + */ +#define XTALOSC24M_LOWPWR_CTRL_TOG_RC_OSC_EN(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_TOG_RC_OSC_EN_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_TOG_RC_OSC_EN_MASK) +#define XTALOSC24M_LOWPWR_CTRL_TOG_OSC_SEL_MASK (0x10U) +#define XTALOSC24M_LOWPWR_CTRL_TOG_OSC_SEL_SHIFT (4U) +/*! OSC_SEL + * 0b0..XTAL OSC + * 0b1..RC OSC + */ +#define XTALOSC24M_LOWPWR_CTRL_TOG_OSC_SEL(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_TOG_OSC_SEL_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_TOG_OSC_SEL_MASK) +#define XTALOSC24M_LOWPWR_CTRL_TOG_LPBG_SEL_MASK (0x20U) +#define XTALOSC24M_LOWPWR_CTRL_TOG_LPBG_SEL_SHIFT (5U) +/*! LPBG_SEL + * 0b0..Normal power bandgap + * 0b1..Low power bandgap + */ +#define XTALOSC24M_LOWPWR_CTRL_TOG_LPBG_SEL(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_TOG_LPBG_SEL_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_TOG_LPBG_SEL_MASK) +#define XTALOSC24M_LOWPWR_CTRL_TOG_LPBG_TEST_MASK (0x40U) +#define XTALOSC24M_LOWPWR_CTRL_TOG_LPBG_TEST_SHIFT (6U) +#define XTALOSC24M_LOWPWR_CTRL_TOG_LPBG_TEST(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_TOG_LPBG_TEST_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_TOG_LPBG_TEST_MASK) +#define XTALOSC24M_LOWPWR_CTRL_TOG_REFTOP_IBIAS_OFF_MASK (0x80U) +#define XTALOSC24M_LOWPWR_CTRL_TOG_REFTOP_IBIAS_OFF_SHIFT (7U) +#define XTALOSC24M_LOWPWR_CTRL_TOG_REFTOP_IBIAS_OFF(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_TOG_REFTOP_IBIAS_OFF_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_TOG_REFTOP_IBIAS_OFF_MASK) +#define XTALOSC24M_LOWPWR_CTRL_TOG_L1_PWRGATE_MASK (0x100U) +#define XTALOSC24M_LOWPWR_CTRL_TOG_L1_PWRGATE_SHIFT (8U) +#define XTALOSC24M_LOWPWR_CTRL_TOG_L1_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_TOG_L1_PWRGATE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_TOG_L1_PWRGATE_MASK) +#define XTALOSC24M_LOWPWR_CTRL_TOG_L2_PWRGATE_MASK (0x200U) +#define XTALOSC24M_LOWPWR_CTRL_TOG_L2_PWRGATE_SHIFT (9U) +#define XTALOSC24M_LOWPWR_CTRL_TOG_L2_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_TOG_L2_PWRGATE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_TOG_L2_PWRGATE_MASK) +#define XTALOSC24M_LOWPWR_CTRL_TOG_CPU_PWRGATE_MASK (0x400U) +#define XTALOSC24M_LOWPWR_CTRL_TOG_CPU_PWRGATE_SHIFT (10U) +#define XTALOSC24M_LOWPWR_CTRL_TOG_CPU_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_TOG_CPU_PWRGATE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_TOG_CPU_PWRGATE_MASK) +#define XTALOSC24M_LOWPWR_CTRL_TOG_DISPLAY_PWRGATE_MASK (0x800U) +#define XTALOSC24M_LOWPWR_CTRL_TOG_DISPLAY_PWRGATE_SHIFT (11U) +#define XTALOSC24M_LOWPWR_CTRL_TOG_DISPLAY_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_TOG_DISPLAY_PWRGATE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_TOG_DISPLAY_PWRGATE_MASK) +#define XTALOSC24M_LOWPWR_CTRL_TOG_RCOSC_CG_OVERRIDE_MASK (0x2000U) +#define XTALOSC24M_LOWPWR_CTRL_TOG_RCOSC_CG_OVERRIDE_SHIFT (13U) +#define XTALOSC24M_LOWPWR_CTRL_TOG_RCOSC_CG_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_TOG_RCOSC_CG_OVERRIDE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_TOG_RCOSC_CG_OVERRIDE_MASK) +#define XTALOSC24M_LOWPWR_CTRL_TOG_XTALOSC_PWRUP_DELAY_MASK (0xC000U) +#define XTALOSC24M_LOWPWR_CTRL_TOG_XTALOSC_PWRUP_DELAY_SHIFT (14U) +/*! XTALOSC_PWRUP_DELAY + * 0b00..0.25ms + * 0b01..0.5ms + * 0b10..1ms + * 0b11..2ms + */ +#define XTALOSC24M_LOWPWR_CTRL_TOG_XTALOSC_PWRUP_DELAY(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_TOG_XTALOSC_PWRUP_DELAY_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_TOG_XTALOSC_PWRUP_DELAY_MASK) +#define XTALOSC24M_LOWPWR_CTRL_TOG_XTALOSC_PWRUP_STAT_MASK (0x10000U) +#define XTALOSC24M_LOWPWR_CTRL_TOG_XTALOSC_PWRUP_STAT_SHIFT (16U) +/*! XTALOSC_PWRUP_STAT + * 0b0..Not stable + * 0b1..Stable and ready to use + */ +#define XTALOSC24M_LOWPWR_CTRL_TOG_XTALOSC_PWRUP_STAT(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_TOG_XTALOSC_PWRUP_STAT_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_TOG_XTALOSC_PWRUP_STAT_MASK) +#define XTALOSC24M_LOWPWR_CTRL_TOG_MIX_PWRGATE_MASK (0x20000U) +#define XTALOSC24M_LOWPWR_CTRL_TOG_MIX_PWRGATE_SHIFT (17U) +#define XTALOSC24M_LOWPWR_CTRL_TOG_MIX_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_TOG_MIX_PWRGATE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_TOG_MIX_PWRGATE_MASK) +#define XTALOSC24M_LOWPWR_CTRL_TOG_GPU_PWRGATE_MASK (0x40000U) +#define XTALOSC24M_LOWPWR_CTRL_TOG_GPU_PWRGATE_SHIFT (18U) +#define XTALOSC24M_LOWPWR_CTRL_TOG_GPU_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_TOG_GPU_PWRGATE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_TOG_GPU_PWRGATE_MASK) +/*! @} */ + +/*! @name OSC_CONFIG0 - XTAL OSC Configuration 0 Register */ +/*! @{ */ +#define XTALOSC24M_OSC_CONFIG0_START_MASK (0x1U) +#define XTALOSC24M_OSC_CONFIG0_START_SHIFT (0U) +#define XTALOSC24M_OSC_CONFIG0_START(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_START_SHIFT)) & XTALOSC24M_OSC_CONFIG0_START_MASK) +#define XTALOSC24M_OSC_CONFIG0_ENABLE_MASK (0x2U) +#define XTALOSC24M_OSC_CONFIG0_ENABLE_SHIFT (1U) +#define XTALOSC24M_OSC_CONFIG0_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_ENABLE_SHIFT)) & XTALOSC24M_OSC_CONFIG0_ENABLE_MASK) +#define XTALOSC24M_OSC_CONFIG0_BYPASS_MASK (0x4U) +#define XTALOSC24M_OSC_CONFIG0_BYPASS_SHIFT (2U) +#define XTALOSC24M_OSC_CONFIG0_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_BYPASS_SHIFT)) & XTALOSC24M_OSC_CONFIG0_BYPASS_MASK) +#define XTALOSC24M_OSC_CONFIG0_INVERT_MASK (0x8U) +#define XTALOSC24M_OSC_CONFIG0_INVERT_SHIFT (3U) +#define XTALOSC24M_OSC_CONFIG0_INVERT(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_INVERT_SHIFT)) & XTALOSC24M_OSC_CONFIG0_INVERT_MASK) +#define XTALOSC24M_OSC_CONFIG0_RC_OSC_PROG_MASK (0xFF0U) +#define XTALOSC24M_OSC_CONFIG0_RC_OSC_PROG_SHIFT (4U) +#define XTALOSC24M_OSC_CONFIG0_RC_OSC_PROG(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_RC_OSC_PROG_SHIFT)) & XTALOSC24M_OSC_CONFIG0_RC_OSC_PROG_MASK) +#define XTALOSC24M_OSC_CONFIG0_HYST_PLUS_MASK (0xF000U) +#define XTALOSC24M_OSC_CONFIG0_HYST_PLUS_SHIFT (12U) +#define XTALOSC24M_OSC_CONFIG0_HYST_PLUS(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_HYST_PLUS_SHIFT)) & XTALOSC24M_OSC_CONFIG0_HYST_PLUS_MASK) +#define XTALOSC24M_OSC_CONFIG0_HYST_MINUS_MASK (0xF0000U) +#define XTALOSC24M_OSC_CONFIG0_HYST_MINUS_SHIFT (16U) +#define XTALOSC24M_OSC_CONFIG0_HYST_MINUS(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_HYST_MINUS_SHIFT)) & XTALOSC24M_OSC_CONFIG0_HYST_MINUS_MASK) +#define XTALOSC24M_OSC_CONFIG0_RC_OSC_PROG_CUR_MASK (0xFF000000U) +#define XTALOSC24M_OSC_CONFIG0_RC_OSC_PROG_CUR_SHIFT (24U) +#define XTALOSC24M_OSC_CONFIG0_RC_OSC_PROG_CUR(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_RC_OSC_PROG_CUR_SHIFT)) & XTALOSC24M_OSC_CONFIG0_RC_OSC_PROG_CUR_MASK) +/*! @} */ + +/*! @name OSC_CONFIG0_SET - XTAL OSC Configuration 0 Register */ +/*! @{ */ +#define XTALOSC24M_OSC_CONFIG0_SET_START_MASK (0x1U) +#define XTALOSC24M_OSC_CONFIG0_SET_START_SHIFT (0U) +#define XTALOSC24M_OSC_CONFIG0_SET_START(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_SET_START_SHIFT)) & XTALOSC24M_OSC_CONFIG0_SET_START_MASK) +#define XTALOSC24M_OSC_CONFIG0_SET_ENABLE_MASK (0x2U) +#define XTALOSC24M_OSC_CONFIG0_SET_ENABLE_SHIFT (1U) +#define XTALOSC24M_OSC_CONFIG0_SET_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_SET_ENABLE_SHIFT)) & XTALOSC24M_OSC_CONFIG0_SET_ENABLE_MASK) +#define XTALOSC24M_OSC_CONFIG0_SET_BYPASS_MASK (0x4U) +#define XTALOSC24M_OSC_CONFIG0_SET_BYPASS_SHIFT (2U) +#define XTALOSC24M_OSC_CONFIG0_SET_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_SET_BYPASS_SHIFT)) & XTALOSC24M_OSC_CONFIG0_SET_BYPASS_MASK) +#define XTALOSC24M_OSC_CONFIG0_SET_INVERT_MASK (0x8U) +#define XTALOSC24M_OSC_CONFIG0_SET_INVERT_SHIFT (3U) +#define XTALOSC24M_OSC_CONFIG0_SET_INVERT(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_SET_INVERT_SHIFT)) & XTALOSC24M_OSC_CONFIG0_SET_INVERT_MASK) +#define XTALOSC24M_OSC_CONFIG0_SET_RC_OSC_PROG_MASK (0xFF0U) +#define XTALOSC24M_OSC_CONFIG0_SET_RC_OSC_PROG_SHIFT (4U) +#define XTALOSC24M_OSC_CONFIG0_SET_RC_OSC_PROG(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_SET_RC_OSC_PROG_SHIFT)) & XTALOSC24M_OSC_CONFIG0_SET_RC_OSC_PROG_MASK) +#define XTALOSC24M_OSC_CONFIG0_SET_HYST_PLUS_MASK (0xF000U) +#define XTALOSC24M_OSC_CONFIG0_SET_HYST_PLUS_SHIFT (12U) +#define XTALOSC24M_OSC_CONFIG0_SET_HYST_PLUS(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_SET_HYST_PLUS_SHIFT)) & XTALOSC24M_OSC_CONFIG0_SET_HYST_PLUS_MASK) +#define XTALOSC24M_OSC_CONFIG0_SET_HYST_MINUS_MASK (0xF0000U) +#define XTALOSC24M_OSC_CONFIG0_SET_HYST_MINUS_SHIFT (16U) +#define XTALOSC24M_OSC_CONFIG0_SET_HYST_MINUS(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_SET_HYST_MINUS_SHIFT)) & XTALOSC24M_OSC_CONFIG0_SET_HYST_MINUS_MASK) +#define XTALOSC24M_OSC_CONFIG0_SET_RC_OSC_PROG_CUR_MASK (0xFF000000U) +#define XTALOSC24M_OSC_CONFIG0_SET_RC_OSC_PROG_CUR_SHIFT (24U) +#define XTALOSC24M_OSC_CONFIG0_SET_RC_OSC_PROG_CUR(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_SET_RC_OSC_PROG_CUR_SHIFT)) & XTALOSC24M_OSC_CONFIG0_SET_RC_OSC_PROG_CUR_MASK) +/*! @} */ + +/*! @name OSC_CONFIG0_CLR - XTAL OSC Configuration 0 Register */ +/*! @{ */ +#define XTALOSC24M_OSC_CONFIG0_CLR_START_MASK (0x1U) +#define XTALOSC24M_OSC_CONFIG0_CLR_START_SHIFT (0U) +#define XTALOSC24M_OSC_CONFIG0_CLR_START(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_CLR_START_SHIFT)) & XTALOSC24M_OSC_CONFIG0_CLR_START_MASK) +#define XTALOSC24M_OSC_CONFIG0_CLR_ENABLE_MASK (0x2U) +#define XTALOSC24M_OSC_CONFIG0_CLR_ENABLE_SHIFT (1U) +#define XTALOSC24M_OSC_CONFIG0_CLR_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_CLR_ENABLE_SHIFT)) & XTALOSC24M_OSC_CONFIG0_CLR_ENABLE_MASK) +#define XTALOSC24M_OSC_CONFIG0_CLR_BYPASS_MASK (0x4U) +#define XTALOSC24M_OSC_CONFIG0_CLR_BYPASS_SHIFT (2U) +#define XTALOSC24M_OSC_CONFIG0_CLR_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_CLR_BYPASS_SHIFT)) & XTALOSC24M_OSC_CONFIG0_CLR_BYPASS_MASK) +#define XTALOSC24M_OSC_CONFIG0_CLR_INVERT_MASK (0x8U) +#define XTALOSC24M_OSC_CONFIG0_CLR_INVERT_SHIFT (3U) +#define XTALOSC24M_OSC_CONFIG0_CLR_INVERT(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_CLR_INVERT_SHIFT)) & XTALOSC24M_OSC_CONFIG0_CLR_INVERT_MASK) +#define XTALOSC24M_OSC_CONFIG0_CLR_RC_OSC_PROG_MASK (0xFF0U) +#define XTALOSC24M_OSC_CONFIG0_CLR_RC_OSC_PROG_SHIFT (4U) +#define XTALOSC24M_OSC_CONFIG0_CLR_RC_OSC_PROG(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_CLR_RC_OSC_PROG_SHIFT)) & XTALOSC24M_OSC_CONFIG0_CLR_RC_OSC_PROG_MASK) +#define XTALOSC24M_OSC_CONFIG0_CLR_HYST_PLUS_MASK (0xF000U) +#define XTALOSC24M_OSC_CONFIG0_CLR_HYST_PLUS_SHIFT (12U) +#define XTALOSC24M_OSC_CONFIG0_CLR_HYST_PLUS(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_CLR_HYST_PLUS_SHIFT)) & XTALOSC24M_OSC_CONFIG0_CLR_HYST_PLUS_MASK) +#define XTALOSC24M_OSC_CONFIG0_CLR_HYST_MINUS_MASK (0xF0000U) +#define XTALOSC24M_OSC_CONFIG0_CLR_HYST_MINUS_SHIFT (16U) +#define XTALOSC24M_OSC_CONFIG0_CLR_HYST_MINUS(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_CLR_HYST_MINUS_SHIFT)) & XTALOSC24M_OSC_CONFIG0_CLR_HYST_MINUS_MASK) +#define XTALOSC24M_OSC_CONFIG0_CLR_RC_OSC_PROG_CUR_MASK (0xFF000000U) +#define XTALOSC24M_OSC_CONFIG0_CLR_RC_OSC_PROG_CUR_SHIFT (24U) +#define XTALOSC24M_OSC_CONFIG0_CLR_RC_OSC_PROG_CUR(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_CLR_RC_OSC_PROG_CUR_SHIFT)) & XTALOSC24M_OSC_CONFIG0_CLR_RC_OSC_PROG_CUR_MASK) +/*! @} */ + +/*! @name OSC_CONFIG0_TOG - XTAL OSC Configuration 0 Register */ +/*! @{ */ +#define XTALOSC24M_OSC_CONFIG0_TOG_START_MASK (0x1U) +#define XTALOSC24M_OSC_CONFIG0_TOG_START_SHIFT (0U) +#define XTALOSC24M_OSC_CONFIG0_TOG_START(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_TOG_START_SHIFT)) & XTALOSC24M_OSC_CONFIG0_TOG_START_MASK) +#define XTALOSC24M_OSC_CONFIG0_TOG_ENABLE_MASK (0x2U) +#define XTALOSC24M_OSC_CONFIG0_TOG_ENABLE_SHIFT (1U) +#define XTALOSC24M_OSC_CONFIG0_TOG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_TOG_ENABLE_SHIFT)) & XTALOSC24M_OSC_CONFIG0_TOG_ENABLE_MASK) +#define XTALOSC24M_OSC_CONFIG0_TOG_BYPASS_MASK (0x4U) +#define XTALOSC24M_OSC_CONFIG0_TOG_BYPASS_SHIFT (2U) +#define XTALOSC24M_OSC_CONFIG0_TOG_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_TOG_BYPASS_SHIFT)) & XTALOSC24M_OSC_CONFIG0_TOG_BYPASS_MASK) +#define XTALOSC24M_OSC_CONFIG0_TOG_INVERT_MASK (0x8U) +#define XTALOSC24M_OSC_CONFIG0_TOG_INVERT_SHIFT (3U) +#define XTALOSC24M_OSC_CONFIG0_TOG_INVERT(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_TOG_INVERT_SHIFT)) & XTALOSC24M_OSC_CONFIG0_TOG_INVERT_MASK) +#define XTALOSC24M_OSC_CONFIG0_TOG_RC_OSC_PROG_MASK (0xFF0U) +#define XTALOSC24M_OSC_CONFIG0_TOG_RC_OSC_PROG_SHIFT (4U) +#define XTALOSC24M_OSC_CONFIG0_TOG_RC_OSC_PROG(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_TOG_RC_OSC_PROG_SHIFT)) & XTALOSC24M_OSC_CONFIG0_TOG_RC_OSC_PROG_MASK) +#define XTALOSC24M_OSC_CONFIG0_TOG_HYST_PLUS_MASK (0xF000U) +#define XTALOSC24M_OSC_CONFIG0_TOG_HYST_PLUS_SHIFT (12U) +#define XTALOSC24M_OSC_CONFIG0_TOG_HYST_PLUS(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_TOG_HYST_PLUS_SHIFT)) & XTALOSC24M_OSC_CONFIG0_TOG_HYST_PLUS_MASK) +#define XTALOSC24M_OSC_CONFIG0_TOG_HYST_MINUS_MASK (0xF0000U) +#define XTALOSC24M_OSC_CONFIG0_TOG_HYST_MINUS_SHIFT (16U) +#define XTALOSC24M_OSC_CONFIG0_TOG_HYST_MINUS(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_TOG_HYST_MINUS_SHIFT)) & XTALOSC24M_OSC_CONFIG0_TOG_HYST_MINUS_MASK) +#define XTALOSC24M_OSC_CONFIG0_TOG_RC_OSC_PROG_CUR_MASK (0xFF000000U) +#define XTALOSC24M_OSC_CONFIG0_TOG_RC_OSC_PROG_CUR_SHIFT (24U) +#define XTALOSC24M_OSC_CONFIG0_TOG_RC_OSC_PROG_CUR(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_TOG_RC_OSC_PROG_CUR_SHIFT)) & XTALOSC24M_OSC_CONFIG0_TOG_RC_OSC_PROG_CUR_MASK) +/*! @} */ + +/*! @name OSC_CONFIG1 - XTAL OSC Configuration 1 Register */ +/*! @{ */ +#define XTALOSC24M_OSC_CONFIG1_COUNT_RC_TRG_MASK (0xFFFU) +#define XTALOSC24M_OSC_CONFIG1_COUNT_RC_TRG_SHIFT (0U) +#define XTALOSC24M_OSC_CONFIG1_COUNT_RC_TRG(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG1_COUNT_RC_TRG_SHIFT)) & XTALOSC24M_OSC_CONFIG1_COUNT_RC_TRG_MASK) +#define XTALOSC24M_OSC_CONFIG1_COUNT_RC_CUR_MASK (0xFFF00000U) +#define XTALOSC24M_OSC_CONFIG1_COUNT_RC_CUR_SHIFT (20U) +#define XTALOSC24M_OSC_CONFIG1_COUNT_RC_CUR(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG1_COUNT_RC_CUR_SHIFT)) & XTALOSC24M_OSC_CONFIG1_COUNT_RC_CUR_MASK) +/*! @} */ + +/*! @name OSC_CONFIG1_SET - XTAL OSC Configuration 1 Register */ +/*! @{ */ +#define XTALOSC24M_OSC_CONFIG1_SET_COUNT_RC_TRG_MASK (0xFFFU) +#define XTALOSC24M_OSC_CONFIG1_SET_COUNT_RC_TRG_SHIFT (0U) +#define XTALOSC24M_OSC_CONFIG1_SET_COUNT_RC_TRG(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG1_SET_COUNT_RC_TRG_SHIFT)) & XTALOSC24M_OSC_CONFIG1_SET_COUNT_RC_TRG_MASK) +#define XTALOSC24M_OSC_CONFIG1_SET_COUNT_RC_CUR_MASK (0xFFF00000U) +#define XTALOSC24M_OSC_CONFIG1_SET_COUNT_RC_CUR_SHIFT (20U) +#define XTALOSC24M_OSC_CONFIG1_SET_COUNT_RC_CUR(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG1_SET_COUNT_RC_CUR_SHIFT)) & XTALOSC24M_OSC_CONFIG1_SET_COUNT_RC_CUR_MASK) +/*! @} */ + +/*! @name OSC_CONFIG1_CLR - XTAL OSC Configuration 1 Register */ +/*! @{ */ +#define XTALOSC24M_OSC_CONFIG1_CLR_COUNT_RC_TRG_MASK (0xFFFU) +#define XTALOSC24M_OSC_CONFIG1_CLR_COUNT_RC_TRG_SHIFT (0U) +#define XTALOSC24M_OSC_CONFIG1_CLR_COUNT_RC_TRG(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG1_CLR_COUNT_RC_TRG_SHIFT)) & XTALOSC24M_OSC_CONFIG1_CLR_COUNT_RC_TRG_MASK) +#define XTALOSC24M_OSC_CONFIG1_CLR_COUNT_RC_CUR_MASK (0xFFF00000U) +#define XTALOSC24M_OSC_CONFIG1_CLR_COUNT_RC_CUR_SHIFT (20U) +#define XTALOSC24M_OSC_CONFIG1_CLR_COUNT_RC_CUR(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG1_CLR_COUNT_RC_CUR_SHIFT)) & XTALOSC24M_OSC_CONFIG1_CLR_COUNT_RC_CUR_MASK) +/*! @} */ + +/*! @name OSC_CONFIG1_TOG - XTAL OSC Configuration 1 Register */ +/*! @{ */ +#define XTALOSC24M_OSC_CONFIG1_TOG_COUNT_RC_TRG_MASK (0xFFFU) +#define XTALOSC24M_OSC_CONFIG1_TOG_COUNT_RC_TRG_SHIFT (0U) +#define XTALOSC24M_OSC_CONFIG1_TOG_COUNT_RC_TRG(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG1_TOG_COUNT_RC_TRG_SHIFT)) & XTALOSC24M_OSC_CONFIG1_TOG_COUNT_RC_TRG_MASK) +#define XTALOSC24M_OSC_CONFIG1_TOG_COUNT_RC_CUR_MASK (0xFFF00000U) +#define XTALOSC24M_OSC_CONFIG1_TOG_COUNT_RC_CUR_SHIFT (20U) +#define XTALOSC24M_OSC_CONFIG1_TOG_COUNT_RC_CUR(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG1_TOG_COUNT_RC_CUR_SHIFT)) & XTALOSC24M_OSC_CONFIG1_TOG_COUNT_RC_CUR_MASK) +/*! @} */ + +/*! @name OSC_CONFIG2 - XTAL OSC Configuration 2 Register */ +/*! @{ */ +#define XTALOSC24M_OSC_CONFIG2_COUNT_1M_TRG_MASK (0xFFFU) +#define XTALOSC24M_OSC_CONFIG2_COUNT_1M_TRG_SHIFT (0U) +#define XTALOSC24M_OSC_CONFIG2_COUNT_1M_TRG(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG2_COUNT_1M_TRG_SHIFT)) & XTALOSC24M_OSC_CONFIG2_COUNT_1M_TRG_MASK) +#define XTALOSC24M_OSC_CONFIG2_ENABLE_1M_MASK (0x10000U) +#define XTALOSC24M_OSC_CONFIG2_ENABLE_1M_SHIFT (16U) +#define XTALOSC24M_OSC_CONFIG2_ENABLE_1M(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG2_ENABLE_1M_SHIFT)) & XTALOSC24M_OSC_CONFIG2_ENABLE_1M_MASK) +#define XTALOSC24M_OSC_CONFIG2_MUX_1M_MASK (0x20000U) +#define XTALOSC24M_OSC_CONFIG2_MUX_1M_SHIFT (17U) +#define XTALOSC24M_OSC_CONFIG2_MUX_1M(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG2_MUX_1M_SHIFT)) & XTALOSC24M_OSC_CONFIG2_MUX_1M_MASK) +#define XTALOSC24M_OSC_CONFIG2_CLK_1M_ERR_FL_MASK (0x80000000U) +#define XTALOSC24M_OSC_CONFIG2_CLK_1M_ERR_FL_SHIFT (31U) +#define XTALOSC24M_OSC_CONFIG2_CLK_1M_ERR_FL(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG2_CLK_1M_ERR_FL_SHIFT)) & XTALOSC24M_OSC_CONFIG2_CLK_1M_ERR_FL_MASK) +/*! @} */ + +/*! @name OSC_CONFIG2_SET - XTAL OSC Configuration 2 Register */ +/*! @{ */ +#define XTALOSC24M_OSC_CONFIG2_SET_COUNT_1M_TRG_MASK (0xFFFU) +#define XTALOSC24M_OSC_CONFIG2_SET_COUNT_1M_TRG_SHIFT (0U) +#define XTALOSC24M_OSC_CONFIG2_SET_COUNT_1M_TRG(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG2_SET_COUNT_1M_TRG_SHIFT)) & XTALOSC24M_OSC_CONFIG2_SET_COUNT_1M_TRG_MASK) +#define XTALOSC24M_OSC_CONFIG2_SET_ENABLE_1M_MASK (0x10000U) +#define XTALOSC24M_OSC_CONFIG2_SET_ENABLE_1M_SHIFT (16U) +#define XTALOSC24M_OSC_CONFIG2_SET_ENABLE_1M(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG2_SET_ENABLE_1M_SHIFT)) & XTALOSC24M_OSC_CONFIG2_SET_ENABLE_1M_MASK) +#define XTALOSC24M_OSC_CONFIG2_SET_MUX_1M_MASK (0x20000U) +#define XTALOSC24M_OSC_CONFIG2_SET_MUX_1M_SHIFT (17U) +#define XTALOSC24M_OSC_CONFIG2_SET_MUX_1M(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG2_SET_MUX_1M_SHIFT)) & XTALOSC24M_OSC_CONFIG2_SET_MUX_1M_MASK) +#define XTALOSC24M_OSC_CONFIG2_SET_CLK_1M_ERR_FL_MASK (0x80000000U) +#define XTALOSC24M_OSC_CONFIG2_SET_CLK_1M_ERR_FL_SHIFT (31U) +#define XTALOSC24M_OSC_CONFIG2_SET_CLK_1M_ERR_FL(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG2_SET_CLK_1M_ERR_FL_SHIFT)) & XTALOSC24M_OSC_CONFIG2_SET_CLK_1M_ERR_FL_MASK) +/*! @} */ + +/*! @name OSC_CONFIG2_CLR - XTAL OSC Configuration 2 Register */ +/*! @{ */ +#define XTALOSC24M_OSC_CONFIG2_CLR_COUNT_1M_TRG_MASK (0xFFFU) +#define XTALOSC24M_OSC_CONFIG2_CLR_COUNT_1M_TRG_SHIFT (0U) +#define XTALOSC24M_OSC_CONFIG2_CLR_COUNT_1M_TRG(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG2_CLR_COUNT_1M_TRG_SHIFT)) & XTALOSC24M_OSC_CONFIG2_CLR_COUNT_1M_TRG_MASK) +#define XTALOSC24M_OSC_CONFIG2_CLR_ENABLE_1M_MASK (0x10000U) +#define XTALOSC24M_OSC_CONFIG2_CLR_ENABLE_1M_SHIFT (16U) +#define XTALOSC24M_OSC_CONFIG2_CLR_ENABLE_1M(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG2_CLR_ENABLE_1M_SHIFT)) & XTALOSC24M_OSC_CONFIG2_CLR_ENABLE_1M_MASK) +#define XTALOSC24M_OSC_CONFIG2_CLR_MUX_1M_MASK (0x20000U) +#define XTALOSC24M_OSC_CONFIG2_CLR_MUX_1M_SHIFT (17U) +#define XTALOSC24M_OSC_CONFIG2_CLR_MUX_1M(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG2_CLR_MUX_1M_SHIFT)) & XTALOSC24M_OSC_CONFIG2_CLR_MUX_1M_MASK) +#define XTALOSC24M_OSC_CONFIG2_CLR_CLK_1M_ERR_FL_MASK (0x80000000U) +#define XTALOSC24M_OSC_CONFIG2_CLR_CLK_1M_ERR_FL_SHIFT (31U) +#define XTALOSC24M_OSC_CONFIG2_CLR_CLK_1M_ERR_FL(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG2_CLR_CLK_1M_ERR_FL_SHIFT)) & XTALOSC24M_OSC_CONFIG2_CLR_CLK_1M_ERR_FL_MASK) +/*! @} */ + +/*! @name OSC_CONFIG2_TOG - XTAL OSC Configuration 2 Register */ +/*! @{ */ +#define XTALOSC24M_OSC_CONFIG2_TOG_COUNT_1M_TRG_MASK (0xFFFU) +#define XTALOSC24M_OSC_CONFIG2_TOG_COUNT_1M_TRG_SHIFT (0U) +#define XTALOSC24M_OSC_CONFIG2_TOG_COUNT_1M_TRG(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG2_TOG_COUNT_1M_TRG_SHIFT)) & XTALOSC24M_OSC_CONFIG2_TOG_COUNT_1M_TRG_MASK) +#define XTALOSC24M_OSC_CONFIG2_TOG_ENABLE_1M_MASK (0x10000U) +#define XTALOSC24M_OSC_CONFIG2_TOG_ENABLE_1M_SHIFT (16U) +#define XTALOSC24M_OSC_CONFIG2_TOG_ENABLE_1M(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG2_TOG_ENABLE_1M_SHIFT)) & XTALOSC24M_OSC_CONFIG2_TOG_ENABLE_1M_MASK) +#define XTALOSC24M_OSC_CONFIG2_TOG_MUX_1M_MASK (0x20000U) +#define XTALOSC24M_OSC_CONFIG2_TOG_MUX_1M_SHIFT (17U) +#define XTALOSC24M_OSC_CONFIG2_TOG_MUX_1M(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG2_TOG_MUX_1M_SHIFT)) & XTALOSC24M_OSC_CONFIG2_TOG_MUX_1M_MASK) +#define XTALOSC24M_OSC_CONFIG2_TOG_CLK_1M_ERR_FL_MASK (0x80000000U) +#define XTALOSC24M_OSC_CONFIG2_TOG_CLK_1M_ERR_FL_SHIFT (31U) +#define XTALOSC24M_OSC_CONFIG2_TOG_CLK_1M_ERR_FL(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG2_TOG_CLK_1M_ERR_FL_SHIFT)) & XTALOSC24M_OSC_CONFIG2_TOG_CLK_1M_ERR_FL_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group XTALOSC24M_Register_Masks */ + + +/* XTALOSC24M - Peripheral instance base addresses */ +/** Peripheral XTALOSC24M base address */ +#define XTALOSC24M_BASE (0x400D8000u) +/** Peripheral XTALOSC24M base pointer */ +#define XTALOSC24M ((XTALOSC24M_Type *)XTALOSC24M_BASE) +/** Array initializer of XTALOSC24M peripheral base addresses */ +#define XTALOSC24M_BASE_ADDRS { XTALOSC24M_BASE } +/** Array initializer of XTALOSC24M peripheral base pointers */ +#define XTALOSC24M_BASE_PTRS { XTALOSC24M } + +/*! + * @} + */ /* end of group XTALOSC24M_Peripheral_Access_Layer */ + + +/* +** End of section using anonymous unions +*/ + +#if defined(__ARMCC_VERSION) + #if (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic pop + #else + #pragma pop + #endif +#elif defined(__CWCC__) + #pragma pop +#elif defined(__GNUC__) + /* leave anonymous unions enabled */ +#elif defined(__IAR_SYSTEMS_ICC__) + #pragma language=default +#else + #error Not supported compiler type +#endif + +/*! + * @} + */ /* end of group Peripheral_access_layer */ + + +/* ---------------------------------------------------------------------------- + -- Macros for use with bit field definitions (xxx_SHIFT, xxx_MASK). + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup Bit_Field_Generic_Macros Macros for use with bit field definitions (xxx_SHIFT, xxx_MASK). + * @{ + */ + +#if defined(__ARMCC_VERSION) + #if (__ARMCC_VERSION >= 6010050) + #pragma clang system_header + #endif +#elif defined(__IAR_SYSTEMS_ICC__) + #pragma system_include +#endif + +/** + * @brief Mask and left-shift a bit field value for use in a register bit range. + * @param field Name of the register bit field. + * @param value Value of the bit field. + * @return Masked and shifted value. + */ +#define NXP_VAL2FLD(field, value) (((value) << (field ## _SHIFT)) & (field ## _MASK)) +/** + * @brief Mask and right-shift a register value to extract a bit field value. + * @param field Name of the register bit field. + * @param value Value of the register. + * @return Masked and shifted bit field value. + */ +#define NXP_FLD2VAL(field, value) (((value) & (field ## _MASK)) >> (field ## _SHIFT)) + +/*! + * @} + */ /* end of group Bit_Field_Generic_Macros */ + + +/* ---------------------------------------------------------------------------- + -- SDK Compatibility + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup SDK_Compatibility_Symbols SDK Compatibility + * @{ + */ + +/* No SDK compatibility issues. */ + +/*! + * @} + */ /* end of group SDK_Compatibility_Symbols */ + + +#endif /* _MIMXRT1052_H_ */ + diff --git a/Ubiquitous/XiZi/board/xidatong/third_party_driver/include/MIMXRT1052_features.h b/Ubiquitous/XiZi/board/xidatong/third_party_driver/include/MIMXRT1052_features.h new file mode 100755 index 0000000..f78522d --- /dev/null +++ b/Ubiquitous/XiZi/board/xidatong/third_party_driver/include/MIMXRT1052_features.h @@ -0,0 +1,627 @@ +/* +** ################################################################### +** Version: rev. 1.1, 2018-11-16 +** Build: b181120 +** +** Abstract: +** Chip specific module features. +** +** Copyright 2016 Freescale Semiconductor, Inc. +** Copyright 2016-2018 NXP +** All rights reserved. +** +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** Revisions: +** - rev. 0.1 (2017-01-10) +** Initial version. +** - rev. 1.0 (2018-09-21) +** Update interrupt vector table and dma request source. +** Update register BEE_ADDR_OFFSET1's bitfield name to ADDR_OFFSET1. +** Split GPIO_COMBINED_IRQS to GPIO_COMBINED_LOW_IRQS and GPIO_COMBINED_HIGH_IRQS. +** - rev. 1.1 (2018-11-16) +** Update feature files to align with IMXRT1050RM Rev.1. +** +** ################################################################### +*/ + +#ifndef _MIMXRT1052_FEATURES_H_ +#define _MIMXRT1052_FEATURES_H_ + +/* SOC module features */ + +/* @brief ADC availability on the SoC. */ +#define FSL_FEATURE_SOC_ADC_COUNT (2) +/* @brief AIPSTZ availability on the SoC. */ +#define FSL_FEATURE_SOC_AIPSTZ_COUNT (4) +/* @brief AOI availability on the SoC. */ +#define FSL_FEATURE_SOC_AOI_COUNT (2) +/* @brief CCM availability on the SoC. */ +#define FSL_FEATURE_SOC_CCM_COUNT (1) +/* @brief CCM_ANALOG availability on the SoC. */ +#define FSL_FEATURE_SOC_CCM_ANALOG_COUNT (1) +/* @brief CMP availability on the SoC. */ +#define FSL_FEATURE_SOC_CMP_COUNT (4) +/* @brief CSI availability on the SoC. */ +#define FSL_FEATURE_SOC_CSI_COUNT (1) +/* @brief DCDC availability on the SoC. */ +#define FSL_FEATURE_SOC_DCDC_COUNT (1) +/* @brief DCP availability on the SoC. */ +#define FSL_FEATURE_SOC_DCP_COUNT (1) +/* @brief DMAMUX availability on the SoC. */ +#define FSL_FEATURE_SOC_DMAMUX_COUNT (1) +/* @brief EDMA availability on the SoC. */ +#define FSL_FEATURE_SOC_EDMA_COUNT (1) +/* @brief ENC availability on the SoC. */ +#define FSL_FEATURE_SOC_ENC_COUNT (4) +/* @brief ENET availability on the SoC. */ +#define FSL_FEATURE_SOC_ENET_COUNT (1) +/* @brief EWM availability on the SoC. */ +#define FSL_FEATURE_SOC_EWM_COUNT (1) +/* @brief FLEXCAN availability on the SoC. */ +#define FSL_FEATURE_SOC_FLEXCAN_COUNT (2) +/* @brief FLEXIO availability on the SoC. */ +#define FSL_FEATURE_SOC_FLEXIO_COUNT (2) +/* @brief FLEXRAM availability on the SoC. */ +#define FSL_FEATURE_SOC_FLEXRAM_COUNT (1) +/* @brief FLEXSPI availability on the SoC. */ +#define FSL_FEATURE_SOC_FLEXSPI_COUNT (1) +/* @brief GPC availability on the SoC. */ +#define FSL_FEATURE_SOC_GPC_COUNT (1) +/* @brief GPT availability on the SoC. */ +#define FSL_FEATURE_SOC_GPT_COUNT (2) +/* @brief I2S availability on the SoC. */ +#define FSL_FEATURE_SOC_I2S_COUNT (3) +/* @brief IGPIO availability on the SoC. */ +#define FSL_FEATURE_SOC_IGPIO_COUNT (5) +/* @brief IOMUXC availability on the SoC. */ +#define FSL_FEATURE_SOC_IOMUXC_COUNT (1) +/* @brief IOMUXC_GPR availability on the SoC. */ +#define FSL_FEATURE_SOC_IOMUXC_GPR_COUNT (1) +/* @brief IOMUXC_SNVS availability on the SoC. */ +#define FSL_FEATURE_SOC_IOMUXC_SNVS_COUNT (1) +/* @brief KPP availability on the SoC. */ +#define FSL_FEATURE_SOC_KPP_COUNT (1) +/* @brief LCDIF availability on the SoC. */ +#define FSL_FEATURE_SOC_LCDIF_COUNT (1) +/* @brief LPI2C availability on the SoC. */ +#define FSL_FEATURE_SOC_LPI2C_COUNT (4) +/* @brief LPSPI availability on the SoC. */ +#define FSL_FEATURE_SOC_LPSPI_COUNT (4) +/* @brief LPUART availability on the SoC. */ +#define FSL_FEATURE_SOC_LPUART_COUNT (8) +/* @brief OCOTP availability on the SoC. */ +#define FSL_FEATURE_SOC_OCOTP_COUNT (1) +/* @brief PIT availability on the SoC. */ +#define FSL_FEATURE_SOC_PIT_COUNT (1) +/* @brief PMU availability on the SoC. */ +#define FSL_FEATURE_SOC_PMU_COUNT (1) +/* @brief PWM availability on the SoC. */ +#define FSL_FEATURE_SOC_PWM_COUNT (4) +/* @brief PXP availability on the SoC. */ +#define FSL_FEATURE_SOC_PXP_COUNT (1) +/* @brief ROMC availability on the SoC. */ +#define FSL_FEATURE_SOC_ROMC_COUNT (1) +/* @brief SEMC availability on the SoC. */ +#define FSL_FEATURE_SOC_SEMC_COUNT (1) +/* @brief SNVS availability on the SoC. */ +#define FSL_FEATURE_SOC_SNVS_COUNT (1) +/* @brief SPDIF availability on the SoC. */ +#define FSL_FEATURE_SOC_SPDIF_COUNT (1) +/* @brief SRC availability on the SoC. */ +#define FSL_FEATURE_SOC_SRC_COUNT (1) +/* @brief TEMPMON availability on the SoC. */ +#define FSL_FEATURE_SOC_TEMPMON_COUNT (1) +/* @brief TMR availability on the SoC. */ +#define FSL_FEATURE_SOC_TMR_COUNT (4) +/* @brief TRNG availability on the SoC. */ +#define FSL_FEATURE_SOC_TRNG_COUNT (1) +/* @brief TSC availability on the SoC. */ +#define FSL_FEATURE_SOC_TSC_COUNT (1) +/* @brief USBHS availability on the SoC. */ +#define FSL_FEATURE_SOC_USBHS_COUNT (2) +/* @brief USBNC availability on the SoC. */ +#define FSL_FEATURE_SOC_USBNC_COUNT (2) +/* @brief USBPHY availability on the SoC. */ +#define FSL_FEATURE_SOC_USBPHY_COUNT (2) +/* @brief USDHC availability on the SoC. */ +#define FSL_FEATURE_SOC_USDHC_COUNT (2) +/* @brief WDOG availability on the SoC. */ +#define FSL_FEATURE_SOC_WDOG_COUNT (2) +/* @brief XBARA availability on the SoC. */ +#define FSL_FEATURE_SOC_XBARA_COUNT (1) +/* @brief XBARB availability on the SoC. */ +#define FSL_FEATURE_SOC_XBARB_COUNT (2) +/* @brief XTALOSC24M availability on the SoC. */ +#define FSL_FEATURE_SOC_XTALOSC24M_COUNT (1) + +/* ADC module features */ + +/* @brief Remove Hardware Trigger feature. */ +#define FSL_FEATURE_ADC_SUPPORT_HARDWARE_TRIGGER_REMOVE (0) +/* @brief Remove ALT Clock selection feature. */ +#define FSL_FEATURE_ADC_SUPPORT_ALTCLK_REMOVE (1) +/* @brief Conversion control count (related to number of registers HCn and Rn). */ +#define FSL_FEATURE_ADC_CONVERSION_CONTROL_COUNT (8) + +/* ADC_ETC module features */ + +/* @brief Has DMA model control(bit field CTRL[DMA_MODE_SEL]). */ +#define FSL_FEATURE_ADC_ETC_HAS_CTRL_DMA_MODE_SEL (1) + +/* AOI module features */ + +/* @brief Maximum value of input mux. */ +#define FSL_FEATURE_AOI_MODULE_INPUTS (4) +/* @brief Number of events related to number of registers AOIx_BFCRT01n/AOIx_BFCRT23n. */ +#define FSL_FEATURE_AOI_EVENT_COUNT (4) + +/* FLEXCAN module features */ + +/* @brief Message buffer size */ +#define FSL_FEATURE_FLEXCAN_HAS_MESSAGE_BUFFER_MAX_NUMBERn(x) (64) +/* @brief Has doze mode support (register bit field MCR[DOZE]). */ +#define FSL_FEATURE_FLEXCAN_HAS_DOZE_MODE_SUPPORT (0) +/* @brief Insatnce has doze mode support (register bit field MCR[DOZE]). */ +#define FSL_FEATURE_FLEXCAN_INSTANCE_HAS_DOZE_MODE_SUPPORTn(x) (0) +/* @brief Has a glitch filter on the receive pin (register bit field MCR[WAKSRC]). */ +#define FSL_FEATURE_FLEXCAN_HAS_GLITCH_FILTER (1) +/* @brief Has extended interrupt mask and flag register (register IMASK2, IFLAG2). */ +#define FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER (1) +/* @brief Instance has extended bit timing register (register CBT). */ +#define FSL_FEATURE_FLEXCAN_INSTANCE_HAS_EXTENDED_TIMING_REGISTERn(x) (0) +/* @brief Has a receive FIFO DMA feature (register bit field MCR[DMA]). */ +#define FSL_FEATURE_FLEXCAN_HAS_RX_FIFO_DMA (0) +/* @brief Instance has a receive FIFO DMA feature (register bit field MCR[DMA]). */ +#define FSL_FEATURE_FLEXCAN_INSTANCE_HAS_RX_FIFO_DMAn(x) (0) +/* @brief Remove CAN Engine Clock Source Selection from unsupported part. */ +#define FSL_FEATURE_FLEXCAN_SUPPORT_ENGINE_CLK_SEL_REMOVE (1) +/* @brief Instance remove CAN Engine Clock Source Selection from unsupported part. */ +#define FSL_FEATURE_FLEXCAN_INSTANCE_SUPPORT_ENGINE_CLK_SEL_REMOVEn(x) (1) +/* @brief Is affected by errata with ID 5641 (Module does not transmit a message that is enabled to be transmitted at a specific moment during the arbitration process). */ +#define FSL_FEATURE_FLEXCAN_HAS_ERRATA_5641 (0) +/* @brief Is affected by errata with ID 5829 (FlexCAN: FlexCAN does not transmit a message that is enabled to be transmitted in a specific moment during the arbitration process). */ +#define FSL_FEATURE_FLEXCAN_HAS_ERRATA_5829 (1) +/* @brief Is affected by errata with ID 6032 (FlexCAN: A frame with wrong ID or payload is transmitted into the CAN bus when the Message Buffer under transmission is either aborted or deactivated while the CAN bus is in the Bus Idle state). */ +#define FSL_FEATURE_FLEXCAN_HAS_ERRATA_6032 (1) +/* @brief Is affected by errata with ID 9595 (FlexCAN: Corrupt frame possible if the Freeze Mode or the Low-Power Mode are entered during a Bus-Off state). */ +#define FSL_FEATURE_FLEXCAN_HAS_ERRATA_9595 (1) +/* @brief Has CAN with Flexible Data rate (CAN FD) protocol. */ +#define FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE (0) +/* @brief CAN instance support Flexible Data rate (CAN FD) protocol. */ +#define FSL_FEATURE_FLEXCAN_INSTANCE_HAS_FLEXIBLE_DATA_RATEn(x) (0) +/* @brief Has extra MB interrupt or common one. */ +#define FSL_FEATURE_FLEXCAN_HAS_EXTRA_MB_INT (1) + +/* CMP module features */ + +/* @brief Has Trigger mode in CMP (register bit field CR1[TRIGM]). */ +#define FSL_FEATURE_CMP_HAS_TRIGGER_MODE (0) +/* @brief Has Window mode in CMP (register bit field CR1[WE]). */ +#define FSL_FEATURE_CMP_HAS_WINDOW_MODE (1) +/* @brief Has External sample supported in CMP (register bit field CR1[SE]). */ +#define FSL_FEATURE_CMP_HAS_EXTERNAL_SAMPLE_SUPPORT (1) +/* @brief Has DMA support in CMP (register bit field SCR[DMAEN]). */ +#define FSL_FEATURE_CMP_HAS_DMA (1) +/* @brief Has Pass Through mode in CMP (register bit field MUXCR[PSTM]). */ +#define FSL_FEATURE_CMP_HAS_PASS_THROUGH_MODE (0) +/* @brief Has DAC Test function in CMP (register DACTEST). */ +#define FSL_FEATURE_CMP_HAS_DAC_TEST (0) + +/* EDMA module features */ + +/* @brief Number of DMA channels (related to number of registers TCD, DCHPRI, bit fields ERQ[ERQn], EEI[EEIn], INT[INTn], ERR[ERRn], HRS[HRSn] and bit field widths ES[ERRCHN], CEEI[CEEI], SEEI[SEEI], CERQ[CERQ], SERQ[SERQ], CDNE[CDNE], SSRT[SSRT], CERR[CERR], CINT[CINT], TCDn_CITER_ELINKYES[LINKCH], TCDn_CSR[MAJORLINKCH], TCDn_BITER_ELINKYES[LINKCH]). (Valid only for eDMA modules.) */ +#define FSL_FEATURE_EDMA_MODULE_CHANNEL (32) +/* @brief Total number of DMA channels on all modules. */ +#define FSL_FEATURE_EDMA_DMAMUX_CHANNELS (32) +/* @brief Number of DMA channel groups (register bit fields CR[ERGA], CR[GRPnPRI], ES[GPE], DCHPRIn[GRPPRI]). (Valid only for eDMA modules.) */ +#define FSL_FEATURE_EDMA_CHANNEL_GROUP_COUNT (1) +/* @brief Has DMA_Error interrupt vector. */ +#define FSL_FEATURE_EDMA_HAS_ERROR_IRQ (1) +/* @brief Number of DMA channels with asynchronous request capability (register EARS). (Valid only for eDMA modules.) */ +#define FSL_FEATURE_EDMA_ASYNCHRO_REQUEST_CHANNEL_COUNT (32) + +/* DMAMUX module features */ + +/* @brief Number of DMA channels (related to number of register CHCFGn). */ +#define FSL_FEATURE_DMAMUX_MODULE_CHANNEL (32) +/* @brief Total number of DMA channels on all modules. */ +#define FSL_FEATURE_DMAMUX_DMAMUX_CHANNELS (FSL_FEATURE_SOC_DMAMUX_COUNT * 32) +/* @brief Has the periodic trigger capability for the triggered DMA channel (register bit CHCFG0[TRIG]). */ +#define FSL_FEATURE_DMAMUX_HAS_TRIG (1) +/* @brief Has DMA Channel Always ON function (register bit CHCFG0[A_ON]). */ +#define FSL_FEATURE_DMAMUX_HAS_A_ON (1) + +/* ENET module features */ + +/* @brief Support Interrupt Coalesce */ +#define FSL_FEATURE_ENET_HAS_INTERRUPT_COALESCE (1) +/* @brief Queue Size. */ +#define FSL_FEATURE_ENET_QUEUE (1) +/* @brief Has AVB Support. */ +#define FSL_FEATURE_ENET_HAS_AVB (0) +/* @brief Has Timer Pulse Width control. */ +#define FSL_FEATURE_ENET_HAS_TIMER_PWCONTROL (1) +/* @brief Has Extend MDIO Support. */ +#define FSL_FEATURE_ENET_HAS_EXTEND_MDIO (1) +/* @brief Has Additional 1588 Timer Channel Interrupt. */ +#define FSL_FEATURE_ENET_HAS_ADD_1588_TIMER_CHN_INT (0) + +/* EWM module features */ + +/* @brief Has clock select (register CLKCTRL). */ +#define FSL_FEATURE_EWM_HAS_CLOCK_SELECT (1) +/* @brief Has clock prescaler (register CLKPRESCALER). */ +#define FSL_FEATURE_EWM_HAS_PRESCALER (1) + +/* FLEXIO module features */ + +/* @brief Has Shifter Status Register (FLEXIO_SHIFTSTAT) */ +#define FSL_FEATURE_FLEXIO_HAS_SHIFTER_STATUS (1) +/* @brief Has Pin Data Input Register (FLEXIO_PIN) */ +#define FSL_FEATURE_FLEXIO_HAS_PIN_STATUS (1) +/* @brief Has Shifter Buffer N Nibble Byte Swapped Register (FLEXIO_SHIFTBUFNBSn) */ +#define FSL_FEATURE_FLEXIO_HAS_SHFT_BUFFER_NIBBLE_BYTE_SWAP (1) +/* @brief Has Shifter Buffer N Half Word Swapped Register (FLEXIO_SHIFTBUFHWSn) */ +#define FSL_FEATURE_FLEXIO_HAS_SHFT_BUFFER_HALF_WORD_SWAP (1) +/* @brief Has Shifter Buffer N Nibble Swapped Register (FLEXIO_SHIFTBUFNISn) */ +#define FSL_FEATURE_FLEXIO_HAS_SHFT_BUFFER_NIBBLE_SWAP (1) +/* @brief Supports Shifter State Mode (FLEXIO_SHIFTCTLn[SMOD]) */ +#define FSL_FEATURE_FLEXIO_HAS_STATE_MODE (1) +/* @brief Supports Shifter Logic Mode (FLEXIO_SHIFTCTLn[SMOD]) */ +#define FSL_FEATURE_FLEXIO_HAS_LOGIC_MODE (1) +/* @brief Supports paralle width (FLEXIO_SHIFTCFGn[PWIDTH]) */ +#define FSL_FEATURE_FLEXIO_HAS_PARALLEL_WIDTH (1) +/* @brief Reset value of the FLEXIO_VERID register */ +#define FSL_FEATURE_FLEXIO_VERID_RESET_VALUE (0x1010001) +/* @brief Reset value of the FLEXIO_PARAM register */ +#define FSL_FEATURE_FLEXIO_PARAM_RESET_VALUE (0x2200404) + +/* FLEXRAM module features */ + +/* @brief Bank size */ +#define FSL_FEATURE_FLEXRAM_INTERNAL_RAM_BANK_SIZE (32768) +/* @brief Total Bank numbers */ +#define FSL_FEATURE_FLEXRAM_INTERNAL_RAM_TOTAL_BANK_NUMBERS (16) + +/* FLEXSPI module features */ + +/* @brief FlexSPI AHB buffer count */ +#define FSL_FEATURE_FLEXSPI_AHB_BUFFER_COUNTn(x) (4) +/* @brief FlexSPI has no data learn. */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_DATA_LEARN (1) + +/* GPC module features */ + +/* @brief Has DVFS0 Change Request. */ +#define FSL_FEATURE_GPC_HAS_CNTR_DVFS0CR (0) +/* @brief Has GPC interrupt/event masking. */ +#define FSL_FEATURE_GPC_HAS_CNTR_GPCIRQM (0) +/* @brief Has L2 cache power control. */ +#define FSL_FEATURE_GPC_HAS_CNTR_L2PGE (0) +/* @brief Has FLEXRAM PDRAM0(bank1-7) power control. */ +#define FSL_FEATURE_GPC_HAS_CNTR_PDRAM0PGE (1) +/* @brief Has VADC power control. */ +#define FSL_FEATURE_GPC_HAS_CNTR_VADC (0) +/* @brief Has Display power control. */ +#define FSL_FEATURE_GPC_HAS_CNTR_DISPLAY (0) +/* @brief Supports IRQ 0-31. */ +#define FSL_FEATURE_GPC_HAS_IRQ_0_31 (1) + +/* IGPIO module features */ + +/* @brief Has data register set DR_SET. */ +#define FSL_FEATURE_IGPIO_HAS_DR_SET (1) +/* @brief Has data register clear DR_CLEAR. */ +#define FSL_FEATURE_IGPIO_HAS_DR_CLEAR (1) +/* @brief Has data register toggle DR_TOGGLE. */ +#define FSL_FEATURE_IGPIO_HAS_DR_TOGGLE (1) + +/* LCDIF module features */ + +/* @brief LCDIF does not support alpha support. */ +#define FSL_FEATURE_LCDIF_HAS_NO_AS (1) +/* @brief LCDIF does not support output reset pin to LCD panel. */ +#define FSL_FEATURE_LCDIF_HAS_NO_RESET_PIN (1) +/* @brief LCDIF supports LUT. */ +#define FSL_FEATURE_LCDIF_HAS_LUT (1) + +/* LPI2C module features */ + +/* @brief Has separate DMA RX and TX requests. */ +#define FSL_FEATURE_LPI2C_HAS_SEPARATE_DMA_RX_TX_REQn(x) (0) +/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ +#define FSL_FEATURE_LPI2C_FIFO_SIZEn(x) (4) + +/* LPSPI module features */ + +/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ +#define FSL_FEATURE_LPSPI_FIFO_SIZEn(x) (16) +/* @brief Has separate DMA RX and TX requests. */ +#define FSL_FEATURE_LPSPI_HAS_SEPARATE_DMA_RX_TX_REQn(x) (1) + +/* LPUART module features */ + +/* @brief Has receive FIFO overflow detection (bit field CFIFO[RXOFE]). */ +#define FSL_FEATURE_LPUART_HAS_IRQ_EXTENDED_FUNCTIONS (0) +/* @brief Has low power features (can be enabled in wait mode via register bit C1[DOZEEN] or CTRL[DOZEEN] if the registers are 32-bit wide). */ +#define FSL_FEATURE_LPUART_HAS_LOW_POWER_UART_SUPPORT (1) +/* @brief Has extended data register ED (or extra flags in the DATA register if the registers are 32-bit wide). */ +#define FSL_FEATURE_LPUART_HAS_EXTENDED_DATA_REGISTER_FLAGS (1) +/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ +#define FSL_FEATURE_LPUART_HAS_FIFO (1) +/* @brief Has 32-bit register MODIR */ +#define FSL_FEATURE_LPUART_HAS_MODIR (1) +/* @brief Hardware flow control (RTS, CTS) is supported. */ +#define FSL_FEATURE_LPUART_HAS_MODEM_SUPPORT (1) +/* @brief Infrared (modulation) is supported. */ +#define FSL_FEATURE_LPUART_HAS_IR_SUPPORT (1) +/* @brief 2 bits long stop bit is available. */ +#define FSL_FEATURE_LPUART_HAS_STOP_BIT_CONFIG_SUPPORT (1) +/* @brief If 10-bit mode is supported. */ +#define FSL_FEATURE_LPUART_HAS_10BIT_DATA_SUPPORT (1) +/* @brief If 7-bit mode is supported. */ +#define FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT (1) +/* @brief Baud rate fine adjustment is available. */ +#define FSL_FEATURE_LPUART_HAS_BAUD_RATE_FINE_ADJUST_SUPPORT (0) +/* @brief Baud rate oversampling is available (has bit fields C4[OSR], C5[BOTHEDGE], C5[RESYNCDIS] or BAUD[OSR], BAUD[BOTHEDGE], BAUD[RESYNCDIS] if the registers are 32-bit wide). */ +#define FSL_FEATURE_LPUART_HAS_BAUD_RATE_OVER_SAMPLING_SUPPORT (1) +/* @brief Baud rate oversampling is available. */ +#define FSL_FEATURE_LPUART_HAS_RX_RESYNC_SUPPORT (1) +/* @brief Baud rate oversampling is available. */ +#define FSL_FEATURE_LPUART_HAS_BOTH_EDGE_SAMPLING_SUPPORT (1) +/* @brief Peripheral type. */ +#define FSL_FEATURE_LPUART_IS_SCI (1) +/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ +#define FSL_FEATURE_LPUART_FIFO_SIZEn(x) (4) +/* @brief Maximal data width without parity bit. */ +#define FSL_FEATURE_LPUART_MAX_DATA_WIDTH_WITH_NO_PARITY (10) +/* @brief Maximal data width with parity bit. */ +#define FSL_FEATURE_LPUART_MAX_DATA_WIDTH_WITH_PARITY (9) +/* @brief Supports two match addresses to filter incoming frames. */ +#define FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING (1) +/* @brief Has transmitter/receiver DMA enable bits C5[TDMAE]/C5[RDMAE] (or BAUD[TDMAE]/BAUD[RDMAE] if the registers are 32-bit wide). */ +#define FSL_FEATURE_LPUART_HAS_DMA_ENABLE (1) +/* @brief Has transmitter/receiver DMA select bits C4[TDMAS]/C4[RDMAS], resp. C5[TDMAS]/C5[RDMAS] if IS_SCI = 0. */ +#define FSL_FEATURE_LPUART_HAS_DMA_SELECT (0) +/* @brief Data character bit order selection is supported (bit field S2[MSBF] or STAT[MSBF] if the registers are 32-bit wide). */ +#define FSL_FEATURE_LPUART_HAS_BIT_ORDER_SELECT (1) +/* @brief Has smart card (ISO7816 protocol) support and no improved smart card support. */ +#define FSL_FEATURE_LPUART_HAS_SMART_CARD_SUPPORT (0) +/* @brief Has improved smart card (ISO7816 protocol) support. */ +#define FSL_FEATURE_LPUART_HAS_IMPROVED_SMART_CARD_SUPPORT (0) +/* @brief Has local operation network (CEA709.1-B protocol) support. */ +#define FSL_FEATURE_LPUART_HAS_LOCAL_OPERATION_NETWORK_SUPPORT (0) +/* @brief Has 32-bit registers (BAUD, STAT, CTRL, DATA, MATCH, MODIR) instead of 8-bit (BDH, BDL, C1, S1, D, etc.). */ +#define FSL_FEATURE_LPUART_HAS_32BIT_REGISTERS (1) +/* @brief Lin break detect available (has bit BAUD[LBKDIE]). */ +#define FSL_FEATURE_LPUART_HAS_LIN_BREAK_DETECT (1) +/* @brief UART stops in Wait mode available (has bit C1[UARTSWAI]). */ +#define FSL_FEATURE_LPUART_HAS_WAIT_MODE_OPERATION (0) +/* @brief Has separate DMA RX and TX requests. */ +#define FSL_FEATURE_LPUART_HAS_SEPARATE_DMA_RX_TX_REQn(x) (1) +/* @brief Has separate RX and TX interrupts. */ +#define FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ (0) +/* @brief Has LPAURT_PARAM. */ +#define FSL_FEATURE_LPUART_HAS_PARAM (1) +/* @brief Has LPUART_VERID. */ +#define FSL_FEATURE_LPUART_HAS_VERID (1) +/* @brief Has LPUART_GLOBAL. */ +#define FSL_FEATURE_LPUART_HAS_GLOBAL (1) +/* @brief Has LPUART_PINCFG. */ +#define FSL_FEATURE_LPUART_HAS_PINCFG (1) + +/* interrupt module features */ + +/* @brief Lowest interrupt request number. */ +#define FSL_FEATURE_INTERRUPT_IRQ_MIN (-14) +/* @brief Highest interrupt request number. */ +#define FSL_FEATURE_INTERRUPT_IRQ_MAX (151) + +/* OCOTP module features */ + +/* No feature definitions */ + +/* PIT module features */ + +/* @brief Number of channels (related to number of registers LDVALn, CVALn, TCTRLn, TFLGn). */ +#define FSL_FEATURE_PIT_TIMER_COUNT (4) +/* @brief Has lifetime timer (related to existence of registers LTMR64L and LTMR64H). */ +#define FSL_FEATURE_PIT_HAS_LIFETIME_TIMER (1) +/* @brief Has chain mode (related to existence of register bit field TCTRLn[CHN]). */ +#define FSL_FEATURE_PIT_HAS_CHAIN_MODE (1) +/* @brief Has shared interrupt handler (has not individual interrupt handler for each channel). */ +#define FSL_FEATURE_PIT_HAS_SHARED_IRQ_HANDLER (1) +/* @brief Has timer enable control. */ +#define FSL_FEATURE_PIT_HAS_MDIS (1) + +/* PMU module features */ + +/* @brief PMU supports lower power control. */ +#define FSL_FEATURE_PMU_HAS_LOWPWR_CTRL (0) + +/* PWM module features */ + +/* @brief Number of each EflexPWM module channels (outputs). */ +#define FSL_FEATURE_PWM_CHANNEL_COUNT (12U) +/* @brief Number of EflexPWM module A channels (outputs). */ +#define FSL_FEATURE_PWM_CHANNELA_COUNT (4U) +/* @brief Number of EflexPWM module B channels (outputs). */ +#define FSL_FEATURE_PWM_CHANNELB_COUNT (4U) +/* @brief Number of EflexPWM module X channels (outputs). */ +#define FSL_FEATURE_PWM_CHANNELX_COUNT (4U) +/* @brief Number of each EflexPWM module compare channels interrupts. */ +#define FSL_FEATURE_PWM_CMP_INT_HANDLER_COUNT (4U) +/* @brief Number of each EflexPWM module reload channels interrupts. */ +#define FSL_FEATURE_PWM_RELOAD_INT_HANDLER_COUNT (4U) +/* @brief Number of each EflexPWM module capture channels interrupts. */ +#define FSL_FEATURE_PWM_CAP_INT_HANDLER_COUNT (1U) +/* @brief Number of each EflexPWM module reload error channels interrupts. */ +#define FSL_FEATURE_PWM_RERR_INT_HANDLER_COUNT (1U) +/* @brief Number of each EflexPWM module fault channels interrupts. */ +#define FSL_FEATURE_PWM_FAULT_INT_HANDLER_COUNT (1U) +/* @brief Number of submodules in each EflexPWM module. */ +#define FSL_FEATURE_PWM_SUBMODULE_COUNT (4U) + +/* PXP module features */ + +/* @brief PXP module has dither engine. */ +#define FSL_FEATURE_PXP_HAS_DITHER (0) +/* @brief PXP module supports repeat run */ +#define FSL_FEATURE_PXP_HAS_EN_REPEAT (1) +/* @brief PXP doesn't have CSC */ +#define FSL_FEATURE_PXP_HAS_NO_CSC2 (1) +/* @brief PXP doesn't have LUT */ +#define FSL_FEATURE_PXP_HAS_NO_LUT (1) + +/* RTWDOG module features */ + +/* @brief Watchdog is available. */ +#define FSL_FEATURE_RTWDOG_HAS_WATCHDOG (1) +/* @brief RTWDOG_CNT can be 32-bit written. */ +#define FSL_FEATURE_RTWDOG_HAS_32BIT_ACCESS (1) + +/* SAI module features */ + +/* @brief Receive/transmit FIFO size in item count (register bit fields TCSR[FRDE], TCSR[FRIE], TCSR[FRF], TCR1[TFW], RCSR[FRDE], RCSR[FRIE], RCSR[FRF], RCR1[RFW], registers TFRn, RFRn). */ +#define FSL_FEATURE_SAI_FIFO_COUNT (32) +/* @brief Receive/transmit channel number (register bit fields TCR3[TCE], RCR3[RCE], registers TDRn and RDRn). */ +#define FSL_FEATURE_SAI_CHANNEL_COUNT (4) +/* @brief Maximum words per frame (register bit fields TCR3[WDFL], TCR4[FRSZ], TMR[TWM], RCR3[WDFL], RCR4[FRSZ], RMR[RWM]). */ +#define FSL_FEATURE_SAI_MAX_WORDS_PER_FRAME (32) +/* @brief Has support of combining multiple data channel FIFOs into single channel FIFO (register bit fields TCR3[CFR], TCR4[FCOMB], TFR0[WCP], TFR1[WCP], RCR3[CFR], RCR4[FCOMB], RFR0[RCP], RFR1[RCP]). */ +#define FSL_FEATURE_SAI_HAS_FIFO_COMBINE_MODE (1) +/* @brief Has packing of 8-bit and 16-bit data into each 32-bit FIFO word (register bit fields TCR4[FPACK], RCR4[FPACK]). */ +#define FSL_FEATURE_SAI_HAS_FIFO_PACKING (1) +/* @brief Configures when the SAI will continue transmitting after a FIFO error has been detected (register bit fields TCR4[FCONT], RCR4[FCONT]). */ +#define FSL_FEATURE_SAI_HAS_FIFO_FUNCTION_AFTER_ERROR (1) +/* @brief Configures if the frame sync is generated internally, a frame sync is only generated when the FIFO warning flag is clear or continuously (register bit fields TCR4[ONDEM], RCR4[ONDEM]). */ +#define FSL_FEATURE_SAI_HAS_ON_DEMAND_MODE (1) +/* @brief Simplified bit clock source and asynchronous/synchronous mode selection (register bit fields TCR2[CLKMODE], RCR2[CLKMODE]), in comparison with the exclusively implemented TCR2[SYNC,BCS,BCI,MSEL], RCR2[SYNC,BCS,BCI,MSEL]. */ +#define FSL_FEATURE_SAI_HAS_CLOCKING_MODE (0) +/* @brief Has register for configuration of the MCLK divide ratio (register bit fields MDR[FRACT], MDR[DIVIDE]). */ +#define FSL_FEATURE_SAI_HAS_MCLKDIV_REGISTER (0) +/* @brief Interrupt source number */ +#define FSL_FEATURE_SAI_INT_SOURCE_NUM (2) +/* @brief Has register of MCR. */ +#define FSL_FEATURE_SAI_HAS_MCR (0) +/* @brief Has bit field MICS of the MCR register. */ +#define FSL_FEATURE_SAI_HAS_NO_MCR_MICS (1) +/* @brief Has register of MDR */ +#define FSL_FEATURE_SAI_HAS_MDR (0) +/* @brief Has support the BCLK bypass mode when BCLK = MCLK. */ +#define FSL_FEATURE_SAI_HAS_BCLK_BYPASS (0) + +/* SEMC module features */ + +/* @brief Has WDH time in NOR controller (register bit field NORCR2[WDH]). */ +#define FSL_FEATURE_SEMC_HAS_NOR_WDH_TIME (1) +/* @brief Has WDS time in NOR controller (register bit field NORCR2[WDS]).) */ +#define FSL_FEATURE_SEMC_HAS_NOR_WDS_TIME (1) + +/* SNVS module features */ + +/* @brief Has Secure Real Time Counter Enabled and Valid (bit field LPCR[SRTC_ENV]). */ +#define FSL_FEATURE_SNVS_HAS_SRTC (1) + +/* SRC module features */ + +/* @brief There is MASK_WDOG3_RST bit in SCR register. */ +#define FSL_FEATURE_SRC_HAS_SCR_MASK_WDOG3_RST (1) +/* @brief There is MIX_RST_STRCH bit in SCR register. */ +#define FSL_FEATURE_SRC_HAS_SCR_MIX_RST_STRCH (0) +/* @brief There is DBG_RST_MSK_PG bit in SCR register. */ +#define FSL_FEATURE_SRC_HAS_SCR_DBG_RST_MSK_PG (1) +/* @brief There is WDOG3_RST_OPTN bit in SCR register. */ +#define FSL_FEATURE_SRC_HAS_SCR_WDOG3_RST_OPTN (0) +/* @brief There is CORES_DBG_RST bit in SCR register. */ +#define FSL_FEATURE_SRC_HAS_SCR_CORES_DBG_RST (0) +/* @brief There is MTSR bit in SCR register. */ +#define FSL_FEATURE_SRC_HAS_SCR_MTSR (0) +/* @brief There is CORE0_DBG_RST bit in SCR register. */ +#define FSL_FEATURE_SRC_HAS_SCR_CORE0_DBG_RST (1) +/* @brief There is CORE0_RST bit in SCR register. */ +#define FSL_FEATURE_SRC_HAS_SCR_CORE0_RST (1) +/* @brief There is LOCKUP_RST bit in SCR register. */ +#define FSL_FEATURE_SRC_HAS_SCR_LOCKUP_RST (0) +/* @brief There is SWRC bit in SCR register. */ +#define FSL_FEATURE_SRC_HAS_SCR_SWRC (0) +/* @brief There is EIM_RST bit in SCR register. */ +#define FSL_FEATURE_SRC_HAS_SCR_EIM_RST (0) +/* @brief There is LUEN bit in SCR register. */ +#define FSL_FEATURE_SRC_HAS_SCR_LUEN (0) +/* @brief There is no WRBC bit in SCR register. */ +#define FSL_FEATURE_SRC_HAS_NO_SCR_WRBC (1) +/* @brief There is no WRE bit in SCR register. */ +#define FSL_FEATURE_SRC_HAS_NO_SCR_WRE (1) +/* @brief There is SISR register. */ +#define FSL_FEATURE_SRC_HAS_SISR (0) +/* @brief There is RESET_OUT bit in SRSR register. */ +#define FSL_FEATURE_SRC_HAS_SRSR_RESET_OUT (0) +/* @brief There is WDOG3_RST_B bit in SRSR register. */ +#define FSL_FEATURE_SRC_HAS_SRSR_WDOG3_RST_B (1) +/* @brief There is SW bit in SRSR register. */ +#define FSL_FEATURE_SRC_HAS_SRSR_SW (0) +/* @brief There is IPP_USER_RESET_B bit in SRSR register. */ +#define FSL_FEATURE_SRC_HAS_SRSR_IPP_USER_RESET_B (1) +/* @brief There is SNVS bit in SRSR register. */ +#define FSL_FEATURE_SRC_HAS_SRSR_SNVS (0) +/* @brief There is CSU_RESET_B bit in SRSR register. */ +#define FSL_FEATURE_SRC_HAS_SRSR_CSU_RESET_B (1) +/* @brief There is LOCKUP bit in SRSR register. */ +#define FSL_FEATURE_SRC_HAS_SRSR_LOCKUP (0) +/* @brief There is LOCKUP_SYSRESETREQ bit in SRSR register. */ +#define FSL_FEATURE_SRC_HAS_SRSR_LOCKUP_SYSRESETREQ (1) +/* @brief There is POR bit in SRSR register. */ +#define FSL_FEATURE_SRC_HAS_SRSR_POR (0) +/* @brief There is IPP_RESET_B bit in SRSR register. */ +#define FSL_FEATURE_SRC_HAS_SRSR_IPP_RESET_B (1) +/* @brief There is no WBI bit in SCR register. */ +#define FSL_FEATURE_SRC_HAS_NO_SRSR_WBI (1) + +/* SCB module features */ + +/* @brief L1 ICACHE line size in byte. */ +#define FSL_FEATURE_L1ICACHE_LINESIZE_BYTE (32) +/* @brief L1 DCACHE line size in byte. */ +#define FSL_FEATURE_L1DCACHE_LINESIZE_BYTE (32) + +/* TRNG module features */ + +/* @brief TRNG has no TRNG_ACC bitfield. */ +#define FSL_FEATURE_TRNG_HAS_NO_TRNG_ACC (1) + +/* USBHS module features */ + +/* @brief EHCI module instance count */ +#define FSL_FEATURE_USBHS_EHCI_COUNT (2) +/* @brief Number of endpoints supported */ +#define FSL_FEATURE_USBHS_ENDPT_COUNT (8) + +/* USDHC module features */ + +/* @brief Has external DMA support (VEND_SPEC[EXT_DMA_EN]) */ +#define FSL_FEATURE_USDHC_HAS_EXT_DMA (0) +/* @brief Has HS400 mode (MIX_CTRL[HS400_MODE]) */ +#define FSL_FEATURE_USDHC_HAS_HS400_MODE (0) +/* @brief Has SDR50 support (HOST_CTRL_CAP[SDR50_SUPPORT]) */ +#define FSL_FEATURE_USDHC_HAS_SDR50_MODE (1) +/* @brief Has SDR104 support (HOST_CTRL_CAP[SDR104_SUPPORT]) */ +#define FSL_FEATURE_USDHC_HAS_SDR104_MODE (1) + +/* XBARA module features */ + +/* @brief DMA_CH_MUX_REQ_30. */ +#define FSL_FEATURE_XBARA_OUTPUT_DMA_CH_MUX_REQ_30 (1) +/* @brief DMA_CH_MUX_REQ_31. */ +#define FSL_FEATURE_XBARA_OUTPUT_DMA_CH_MUX_REQ_31 (1) +/* @brief DMA_CH_MUX_REQ_94. */ +#define FSL_FEATURE_XBARA_OUTPUT_DMA_CH_MUX_REQ_94 (1) +/* @brief DMA_CH_MUX_REQ_95. */ +#define FSL_FEATURE_XBARA_OUTPUT_DMA_CH_MUX_REQ_95 (1) + +#endif /* _MIMXRT1052_FEATURES_H_ */ + diff --git a/Ubiquitous/XiZi/board/xidatong/third_party_driver/include/connect_ch438.h b/Ubiquitous/XiZi/board/xidatong/third_party_driver/include/connect_ch438.h new file mode 100755 index 0000000..2944ed0 --- /dev/null +++ b/Ubiquitous/XiZi/board/xidatong/third_party_driver/include/connect_ch438.h @@ -0,0 +1,273 @@ +/* +* Copyright (c) 2020 AIIT XUOS Lab +* XiUOS is licensed under Mulan PSL v2. +* You can use this software according to the terms and conditions of the Mulan PSL v2. +* You may obtain a copy of Mulan PSL v2 at: +* http://license.coscl.org.cn/MulanPSL2 +* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, +* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, +* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. +* See the Mulan PSL v2 for more details. +*/ + +/** +* @file connect_ch438.h +* @brief define imxrt1052-board ch438 function and struct +* @version 2.0 +* @author AIIT XUOS Lab +* @date 2022-03-15 +*/ + +#ifndef CONNECT_CH438_H +#define CONNECT_CH438_H + +#include +#include +#include + +#define CH438_BUFFSIZE 255 + +/******************************************************************************************/ + +/* chip definition */ +/* CH438serial port0 register address */ + +#define REG_RBR0_ADDR 0x00 /* serial port0receive buffer register address */ +#define REG_THR0_ADDR 0x00 /* serial port0send hold register address */ +#define REG_IER0_ADDR 0x01 /* serial port0interrupt enable register address */ +#define REG_IIR0_ADDR 0x02 /* serial port0interrupt identifies register address */ +#define REG_FCR0_ADDR 0x02 /* serial port0FIFO controls register address */ +#define REG_LCR0_ADDR 0x03 /* serial port0circuit control register address */ +#define REG_MCR0_ADDR 0x04 /* serial port0MODEM controls register address */ +#define REG_LSR0_ADDR 0x05 /* serial port0line status register address */ +#define REG_MSR0_ADDR 0x06 /* serial port0address of MODEM status register */ +#define REG_SCR0_ADDR 0x07 /* serial port0the user can define the register address */ +#define REG_DLL0_ADDR 0x00 /* Baud rate divisor latch low 8-bit byte address */ +#define REG_DLM0_ADDR 0x01 /* Baud rate divisor latch high 8-bit byte address */ + +/* CH438serial port1 register address */ + +#define REG_RBR1_ADDR 0x10 /* serial port1receive buffer register address */ +#define REG_THR1_ADDR 0x10 /* serial port1send hold register address */ +#define REG_IER1_ADDR 0x11 /* serial port1interrupt enable register address */ +#define REG_IIR1_ADDR 0x12 /* serial port1interrupt identifies register address */ +#define REG_FCR1_ADDR 0x12 /* serial port1FIFO controls register address */ +#define REG_LCR1_ADDR 0x13 /* serial port1circuit control register address */ +#define REG_MCR1_ADDR 0x14 /* serial port1MODEM controls register address */ +#define REG_LSR1_ADDR 0x15 /* serial port1line status register address */ +#define REG_MSR1_ADDR 0x16 /* serial port1address of MODEM status register */ +#define REG_SCR1_ADDR 0x17 /* serial port1the user can define the register address */ +#define REG_DLL1_ADDR 0x10 /* Baud rate divisor latch low 8-bit byte address */ +#define REG_DLM1_ADDR 0x11 /* Baud rate divisor latch high 8-bit byte address */ + + +/* CH438serial port2 register address */ + +#define REG_RBR2_ADDR 0x20 /* serial port2receive buffer register address */ +#define REG_THR2_ADDR 0x20 /* serial port2send hold register address */ +#define REG_IER2_ADDR 0x21 /* serial port2interrupt enable register address */ +#define REG_IIR2_ADDR 0x22 /* serial port2interrupt identifies register address */ +#define REG_FCR2_ADDR 0x22 /* serial port2FIFO controls register address */ +#define REG_LCR2_ADDR 0x23 /* serial port2circuit control register address */ +#define REG_MCR2_ADDR 0x24 /* serial port2MODEM controls register address */ +#define REG_LSR2_ADDR 0x25 /* serial port2line status register address */ +#define REG_MSR2_ADDR 0x26 /* serial port2address of MODEM status register */ +#define REG_SCR2_ADDR 0x27 /* serial port2the user can define the register address */ +#define REG_DLL2_ADDR 0x20 /* Baud rate divisor latch low 8-bit byte address */ +#define REG_DLM2_ADDR 0x21 /* Baud rate divisor latch high 8-bit byte address */ + + + +/* CH438serial port3 register address */ + +#define REG_RBR3_ADDR 0x30 /* serial port3receive buffer register address */ +#define REG_THR3_ADDR 0x30 /* serial port3send hold register address */ +#define REG_IER3_ADDR 0x31 /* serial port3interrupt enable register address */ +#define REG_IIR3_ADDR 0x32 /* serial port3interrupt identifies register address */ +#define REG_FCR3_ADDR 0x32 /* serial port3FIFO controls register address */ +#define REG_LCR3_ADDR 0x33 /* serial port3circuit control register address */ +#define REG_MCR3_ADDR 0x34 /* serial port3MODEM controls register address */ +#define REG_LSR3_ADDR 0x35 /* serial port3line status register address */ +#define REG_MSR3_ADDR 0x36 /* serial port3address of MODEM status register */ +#define REG_SCR3_ADDR 0x37 /* serial port3the user can define the register address */ +#define REG_DLL3_ADDR 0x30 /* Baud rate divisor latch low 8-bit byte address */ +#define REG_DLM3_ADDR 0x31 /* Baud rate divisor latch high 8-bit byte address */ + + +/* CH438serial port4 register address */ + +#define REG_RBR4_ADDR 0x08 /* serial port4receive buffer register address */ +#define REG_THR4_ADDR 0x08 /* serial port4send hold register address */ +#define REG_IER4_ADDR 0x09 /* serial port4interrupt enable register address */ +#define REG_IIR4_ADDR 0x0A /* serial port4interrupt identifies register address */ +#define REG_FCR4_ADDR 0x0A /* serial port4FIFO controls register address */ +#define REG_LCR4_ADDR 0x0B /* serial port4circuit control register address */ +#define REG_MCR4_ADDR 0x0C /* serial port4MODEM controls register address */ +#define REG_LSR4_ADDR 0x0D /* serial port4line status register address */ +#define REG_MSR4_ADDR 0x0E /* serial port4address of MODEM status register */ +#define REG_SCR4_ADDR 0x0F /* serial port4the user can define the register address */ +#define REG_DLL4_ADDR 0x08 /* Baud rate divisor latch low 8-bit byte address */ +#define REG_DLM4_ADDR 0x09 /* Baud rate divisor latch high 8-bit byte address */ + + + +/* CH438serial port5 register address */ + +#define REG_RBR5_ADDR 0x18 /* serial port5receive buffer register address */ +#define REG_THR5_ADDR 0x18 /* serial port5send hold register address */ +#define REG_IER5_ADDR 0x19 /* serial port5interrupt enable register address */ +#define REG_IIR5_ADDR 0x1A /* serial port5interrupt identifies register address */ +#define REG_FCR5_ADDR 0x1A /* serial port5FIFO controls register address */ +#define REG_LCR5_ADDR 0x1B /* serial port5circuit control register address */ +#define REG_MCR5_ADDR 0x1C /* serial port5MODEM controls register address */ +#define REG_LSR5_ADDR 0x1D /* serial port5line status register address */ +#define REG_MSR5_ADDR 0x1E /* serial port5address of MODEM status register */ +#define REG_SCR5_ADDR 0x1F /* serial port5the user can define the register address */ +#define REG_DLL5_ADDR 0x18 /* Baud rate divisor latch low 8-bit byte address */ +#define REG_DLM5_ADDR 0x19 /* Baud rate divisor latch high 8-bit byte address */ + + +/* CH438serial port6 register address */ + +#define REG_RBR6_ADDR 0x28 /* serial port6receive buffer register address */ +#define REG_THR6_ADDR 0x28 /* serial port6send hold register address */ +#define REG_IER6_ADDR 0x29 /* serial port6interrupt enable register address */ +#define REG_IIR6_ADDR 0x2A /* serial port6interrupt identifies register address */ +#define REG_FCR6_ADDR 0x2A /* serial port6FIFO controls register address */ +#define REG_LCR6_ADDR 0x2B /* serial port6circuit control register address */ +#define REG_MCR6_ADDR 0x2C /* serial port6MODEM controls register address */ +#define REG_LSR6_ADDR 0x2D /* serial port6line status register address */ +#define REG_MSR6_ADDR 0x2E /* serial port6address of MODEM status register */ +#define REG_SCR6_ADDR 0x2F /* serial port6the user can define the register address */ +#define REG_DLL6_ADDR 0x28 /* Baud rate divisor latch low 8-bit byte address */ +#define REG_DLM6_ADDR 0x29 /* Baud rate divisor latch high 8-bit byte address */ + + +/* CH438serial port7 register address */ + +#define REG_RBR7_ADDR 0x38 /* serial port7receive buffer register address */ +#define REG_THR7_ADDR 0x38 /* serial port7send hold register address */ +#define REG_IER7_ADDR 0x39 /* serial port7interrupt enable register address */ +#define REG_IIR7_ADDR 0x3A /* serial port7interrupt identifies register address */ +#define REG_FCR7_ADDR 0x3A /* serial port7FIFO controls register address */ +#define REG_LCR7_ADDR 0x3B /* serial port7circuit control register address */ +#define REG_MCR7_ADDR 0x3C /* serial port7MODEM controls register address */ +#define REG_LSR7_ADDR 0x3D /* serial port7line status register address */ +#define REG_MSR7_ADDR 0x3E /* serial port7address of MODEM status register */ +#define REG_SCR7_ADDR 0x3F /* serial port7the user can define the register address */ +#define REG_DLL7_ADDR 0x38 /* Baud rate divisor latch low 8-bit byte address */ +#define REG_DLM7_ADDR 0x39 /* Baud rate divisor latch high 8-bit byte address */ + + +#define REG_SSR_ADDR 0x4F /* pecial status register address */ + + +/* IER register bit */ + +#define BIT_IER_RESET 0x80 /* The bit is 1 soft reset serial port */ +#define BIT_IER_LOWPOWER 0x40 /* The bit is 1 close serial port internal reference clock */ +#define BIT_IER_SLP 0x20 /* serial port0 is SLP, 1 close clock vibrator */ +#define BIT_IER1_CK2X 0x20 /* serial port1 is CK2X, 1 force the external clock signal after 2 times as internal reference clock */ +#define BIT_IER_IEMODEM 0x08 /* The bit is 1 allows MODEM input status to interrupt */ +#define BIT_IER_IELINES 0x04 /* The bit is 1 allow receiving line status to be interrupted */ +#define BIT_IER_IETHRE 0x02 /* The bit is 1 allows the send hold register to break in mid-air */ +#define BIT_IER_IERECV 0x01 /* The bit is 1 allows receiving data interrupts */ + +/* IIR register bit */ + +#define BIT_IIR_FIFOENS1 0x80 +#define BIT_IIR_FIFOENS0 0x40 /* The two is 1 said use FIFO */ + +/* Interrupt type: 0001 has no interrupt, 0110 receiving line status is interrupted, 0100 receiving data can be interrupted, +1100 received data timeout interrupt, 0010THR register air interrupt, 0000MODEM input change interrupt */ +#define BIT_IIR_IID3 0x08 +#define BIT_IIR_IID2 0x04 +#define BIT_IIR_IID1 0x02 +#define BIT_IIR_NOINT 0x01 + +/* FCR register bit */ + +/* Trigger point: 00 corresponds to 1 byte, 01 corresponds to 16 bytes, 10 corresponds to 64 bytes, 11 corresponds to 112 bytes */ +#define BIT_FCR_RECVTG1 0x80 /* Set the trigger point for FIFO interruption and automatic hardware flow control */ +#define BIT_FCR_RECVTG0 0x40 /* Set the trigger point for FIFO interruption and automatic hardware flow control */ + +#define BIT_FCR_TFIFORST 0x04 /* The bit is 1 empty the data sent in FIFO */ +#define BIT_FCR_RFIFORST 0x02 /* The bit is 1 empty the data sent in FIFO */ +#define BIT_FCR_FIFOEN 0x01 /* The bit is 1 use FIFO, 0 disable FIFO */ + +/* LCR register bit */ + +#define BIT_LCR_DLAB 0x80 /* To access DLL, DLM, 0 to access RBR/THR/IER */ +#define BIT_LCR_BREAKEN 0x40 /* 1 forces a BREAK line interval*/ + +/* Set the check format: when PAREN is 1, 00 odd check, 01 even check, 10 MARK (set 1), 11 blank (SPACE, clear 0) */ +#define BIT_LCR_PARMODE1 0x20 /* Sets the parity bit format */ +#define BIT_LCR_PARMODE0 0x10 /* Sets the parity bit format */ + +#define BIT_LCR_PAREN 0x08 /* A value of 1 allows you to generate and receive parity bits when sending */ +#define BIT_LCR_STOPBIT 0x04 /* If is 1, then two stop bits, is 0, a stop bit */ + +/* Set word length: 00 for 5 data bits, 01 for 6 data bits, 10 for 7 data bits and 11 for 8 data bits */ +#define BIT_LCR_WORDSZ1 0x02 /* Set the word length length */ +#define BIT_LCR_WORDSZ0 0x01 + +/* MCR register bit */ + +#define BIT_MCR_AFE 0x20 /* For 1 allows automatic flow control of CTS and RTS hardware */ +#define BIT_MCR_LOOP 0x10 /* Is the test mode of 1 enabling internal loop */ +#define BIT_MCR_OUT2 0x08 /* 1 Allows an interrupt request for the serial port output */ +#define BIT_MCR_OUT1 0x04 /* The MODEM control bit defined for the user */ +#define BIT_MCR_RTS 0x02 /* The bit is 1 RTS pin output effective */ +#define BIT_MCR_DTR 0x01 /* The bit is 1 DTR pin output effective */ + +/* LSR register bit */ + +#define BIT_LSR_RFIFOERR 0x80 /* 1 said There is at least one error in receiving FIFO */ +#define BIT_LSR_TEMT 0x40 /* 1 said THR and TSR are empty */ +#define BIT_LSR_THRE 0x20 /* 1 said THR is empty*/ +#define BIT_LSR_BREAKINT 0x10 /* The bit is 1 said the BREAK line interval was detected*/ +#define BIT_LSR_FRAMEERR 0x08 /* The bit is 1 said error reading data frame */ +#define BIT_LSR_PARERR 0x04 /* The bit is 1 said parity error */ +#define BIT_LSR_OVERR 0x02 /* 1 said receive FIFO buffer overflow */ +#define BIT_LSR_DATARDY 0x01 /* The bit is 1 said receive data received in FIFO */ + +/* MSR register bit */ + +#define BIT_MSR_DCD 0x80 /* The bit is 1 said DCD pin effective */ +#define BIT_MSR_RI 0x40 /* The bit is 1 said RI pin effective */ +#define BIT_MSR_DSR 0x20 /* The bit is 1 said DSR pin effective */ +#define BIT_MSR_CTS 0x10 /* The bit is 1 said CTS pin effective */ +#define BIT_MSR_DDCD 0x08 /* The bit is 1 said DCD pin The input state has changed */ +#define BIT_MSR_TERI 0x04 /* The bit is 1 said RI pin The input state has changed */ +#define BIT_MSR_DDSR 0x02 /* The bit is 1 said DSR pin The input state has changed */ +#define BIT_MSR_DCTS 0x01 /* The bit is 1 said CTS pin The input state has changed */ + +/* Interrupt status code */ + +#define INT_NOINT 0x01 /* There is no interruption */ +#define INT_THR_EMPTY 0x02 /* THR empty interruption */ +#define INT_RCV_OVERTIME 0x0C /* Receive timeout interrupt */ +#define INT_RCV_SUCCESS 0x04 /* Interrupts are available to receive data */ +#define INT_RCV_LINES 0x06 /* Receiving line status interrupted */ +#define INT_MODEM_CHANGE 0x00 /* MODEM input changes interrupt */ + +#define CH438_IIR_FIFOS_ENABLED 0xC0 /* use FIFO */ + +#define Fpclk 1843200 /* Define the internal clock frequency */ + +#define CH438_D0_PIN IMXRT_GET_PIN(1, 25) +#define CH438_D1_PIN IMXRT_GET_PIN(1, 24) +#define CH438_D2_PIN IMXRT_GET_PIN(1, 20) +#define CH438_D3_PIN IMXRT_GET_PIN(1, 21) +#define CH438_D4_PIN IMXRT_GET_PIN(1, 31) +#define CH438_D5_PIN IMXRT_GET_PIN(1, 28) +#define CH438_D6_PIN IMXRT_GET_PIN(1, 30) +#define CH438_D7_PIN IMXRT_GET_PIN(1, 29) +#define CH438_NWR_PIN IMXRT_GET_PIN(3, 4) +#define CH438_NRD_PIN IMXRT_GET_PIN(3, 5) +#define CH438_ALE_PIN IMXRT_GET_PIN(3, 2) +#define CH438_INT_PIN IMXRT_GET_PIN(3, 3) + +int Imxrt1052HwCh438Init(void); + +#endif diff --git a/Ubiquitous/XiZi/board/xidatong/third_party_driver/include/connect_ethernet.h b/Ubiquitous/XiZi/board/xidatong/third_party_driver/include/connect_ethernet.h new file mode 100755 index 0000000..376c004 --- /dev/null +++ b/Ubiquitous/XiZi/board/xidatong/third_party_driver/include/connect_ethernet.h @@ -0,0 +1,39 @@ +/* +* Copyright (c) 2021 AIIT XUOS Lab +* XiUOS is licensed under Mulan PSL v2. +* You can use this software according to the terms and conditions of the Mulan PSL v2. +* You may obtain a copy of Mulan PSL v2 at: +* http://license.coscl.org.cn/MulanPSL2 +* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, +* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, +* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. +* See the Mulan PSL v2 for more details. +*/ + +/** +* @file connect_ethernet.h +* @brief Adapted network software protocol stack and hardware operation functions +* @version 1.0 +* @author AIIT XUOS Lab +* @date 2021-12-7 +*/ + +#ifndef __CONNECT_ETHERNET_H_ +#define __CONNECT_ETHERNET_H_ + +#ifdef __cplusplus + extern "C" { +#endif + + +#ifndef sourceClock +#define sourceClock CLOCK_GetFreq(kCLOCK_CoreSysClk) +#endif + + +#ifdef __cplusplus +} +#endif + +#endif + diff --git a/Ubiquitous/XiZi/board/xidatong/third_party_driver/include/connect_gpio.h b/Ubiquitous/XiZi/board/xidatong/third_party_driver/include/connect_gpio.h new file mode 100644 index 0000000..f9da70b --- /dev/null +++ b/Ubiquitous/XiZi/board/xidatong/third_party_driver/include/connect_gpio.h @@ -0,0 +1,38 @@ +/* +* Copyright (c) 2022 AIIT XUOS Lab +* XiUOS is licensed under Mulan PSL v2. +* You can use this software according to the terms and conditions of the Mulan PSL v2. +* You may obtain a copy of Mulan PSL v2 at: +* http://license.coscl.org.cn/MulanPSL2 +* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, +* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, +* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. +* See the Mulan PSL v2 for more details. +*/ + +/** +* @file connect_gpio.h +* @brief define imxrt1052-board gpio function and struct +* @version 2.0 +* @author AIIT XUOS Lab +* @date 2022-03-15 +*/ + +#ifndef __CONNECT_GPIO_H_ +#define __CONNECT_GPIO_H_ + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +#define IMXRT_GET_PIN(PORTx, PIN) (32 * (PORTx - 1) + (PIN & 31)) /* PORTx:1,2,3,4,5 */ + +int Imxrt1052HwGpioInit(void); + +#ifdef __cplusplus +} +#endif + +#endif \ No newline at end of file diff --git a/Ubiquitous/XiZi/board/xidatong/third_party_driver/include/connect_sdio.h b/Ubiquitous/XiZi/board/xidatong/third_party_driver/include/connect_sdio.h new file mode 100644 index 0000000..f76b1a4 --- /dev/null +++ b/Ubiquitous/XiZi/board/xidatong/third_party_driver/include/connect_sdio.h @@ -0,0 +1,44 @@ +/* +* Copyright (c) 2020 AIIT XUOS Lab +* XiUOS is licensed under Mulan PSL v2. +* You can use this software according to the terms and conditions of the Mulan PSL v2. +* You may obtain a copy of Mulan PSL v2 at: +* http://license.coscl.org.cn/MulanPSL2 +* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, +* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, +* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. +* See the Mulan PSL v2 for more details. +*/ + +/** +* @file connect_sdio.h +* @brief define imxrt1052-board sdio function and struct +* @version 2.0 +* @author AIIT XUOS Lab +* @date 2022-03-15 +*/ + +#ifndef CONNECT_SDIO_H +#define CONNECT_SDIO_H + +#include +#include +#include +#include +#include +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +#define SD_CARD_STACK_SIZE 2048 + +int Imxrt1052HwSdioInit(void); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/Ubiquitous/XiZi/board/xidatong/third_party_driver/include/connect_uart.h b/Ubiquitous/XiZi/board/xidatong/third_party_driver/include/connect_uart.h new file mode 100644 index 0000000..4b4c947 --- /dev/null +++ b/Ubiquitous/XiZi/board/xidatong/third_party_driver/include/connect_uart.h @@ -0,0 +1,42 @@ +/* +* Copyright (c) 2020 AIIT XUOS Lab +* XiUOS is licensed under Mulan PSL v2. +* You can use this software according to the terms and conditions of the Mulan PSL v2. +* You may obtain a copy of Mulan PSL v2 at: +* http://license.coscl.org.cn/MulanPSL2 +* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, +* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, +* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. +* See the Mulan PSL v2 for more details. +*/ + +/** +* @file connect_uart.h +* @brief define imxrt1052-board usart function and struct +* @version 2.0 +* @author AIIT XUOS Lab +* @date 2022-03-15 +*/ + +#ifndef CONNECT_UART_H +#define CONNECT_UART_H + +#include + +#ifdef __cplusplus +extern "C" { +#endif + + + +#define KERNEL_CONSOLE_BUS_NAME SERIAL_BUS_NAME_1 +#define KERNEL_CONSOLE_DRV_NAME SERIAL_DRV_NAME_1 +#define KERNEL_CONSOLE_DEVICE_NAME SERIAL_1_DEVICE_NAME_0 + +int Imxrt1052HwUartInit(void); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/Ubiquitous/XiZi/board/xidatong/third_party_driver/include/connect_usb.h b/Ubiquitous/XiZi/board/xidatong/third_party_driver/include/connect_usb.h new file mode 100644 index 0000000..9736f50 --- /dev/null +++ b/Ubiquitous/XiZi/board/xidatong/third_party_driver/include/connect_usb.h @@ -0,0 +1,53 @@ +/* +* Copyright (c) 2020 AIIT XUOS Lab +* XiUOS is licensed under Mulan PSL v2. +* You can use this software according to the terms and conditions of the Mulan PSL v2. +* You may obtain a copy of Mulan PSL v2 at: +* http://license.coscl.org.cn/MulanPSL2 +* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, +* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, +* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. +* See the Mulan PSL v2 for more details. +*/ + +/** +* @file connect_usb.h +* @brief define imxrt1052-board usb function and struct +* @version 2.0 +* @author AIIT XUOS Lab +* @date 2022-03-15 +*/ + +#ifndef CONNECT_USB_H +#define CONNECT_USB_H + +#include +#include +#include +#include +#include +#include +#include + +#if defined(FS_VFS) +#include +#endif + +#ifdef __cplusplus +extern "C" { +#endif + +#define CONTROLLER_ID kUSB_ControllerEhci1 +#define USB_HOST_INTERRUPT_PRIORITY (3U) + +#define USB_HOST_STACK_SIZE 4096 + +#define USB_SINGLE_BLOCK_SIZE 512 + +int Imxrt1052HwUsbHostInit(void); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/Ubiquitous/XiZi/board/xidatong/third_party_driver/include/enet_ethernetif.h b/Ubiquitous/XiZi/board/xidatong/third_party_driver/include/enet_ethernetif.h new file mode 100755 index 0000000..8416d75 --- /dev/null +++ b/Ubiquitous/XiZi/board/xidatong/third_party_driver/include/enet_ethernetif.h @@ -0,0 +1,192 @@ +/* + * Copyright (c) 2001-2003 Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Adam Dunkels + * + */ + +/* + * Copyright (c) 2013-2016, Freescale Semiconductor, Inc. + * Copyright 2016-2019 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +/** + * @file enet_ethernetif.h + * @brief ethernet drivers + * @version 1.0 + * @author AIIT XUOS Lab + * @date 2021.11.11 + */ + + +#ifndef ENET_ETHERNETIF_H +#define ENET_ETHERNETIF_H + +#include "lwip/err.h" +#include "lwip/netif.h" +#include "fsl_enet.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ +#ifndef ENET_RXBD_NUM + #define ENET_RXBD_NUM (5) +#endif +#ifndef ENET_TXBD_NUM +#if defined(FSL_FEATURE_SOC_LPC_ENET_COUNT) && (FSL_FEATURE_SOC_LPC_ENET_COUNT > 0) + #define ENET_TXBD_NUM (5) +#else + #define ENET_TXBD_NUM (3) +#endif +#endif +#ifndef ENET_RXBUFF_SIZE +#if defined(FSL_FEATURE_SOC_LPC_ENET_COUNT) && (FSL_FEATURE_SOC_LPC_ENET_COUNT > 0) + #define ENET_RXBUFF_SIZE (ENET_FRAME_MAX_FRAMELEN + ETH_PAD_SIZE) +#else + #define ENET_RXBUFF_SIZE ENET_FRAME_MAX_FRAMELEN +#endif +#endif + +#ifndef ENET_TXBUFF_SIZE + #define ENET_TXBUFF_SIZE (ENET_FRAME_MAX_FRAMELEN) +#endif + +#define ENET_TIMEOUT (0xFFFU) + +/* ENET IRQ priority. Used in FreeRTOS. */ +/* Interrupt priorities. */ +#ifdef __CA7_REV +#ifndef ENET_PRIORITY + #define ENET_PRIORITY (21U) +#endif +#ifndef ENET_1588_PRIORITY + #define ENET_1588_PRIORITY (20U) +#endif +#else +#ifndef ENET_PRIORITY + #define ENET_PRIORITY (15U)//(6U) +#endif +#ifndef ENET_1588_PRIORITY + #define ENET_1588_PRIORITY (5U) +#endif +#endif + +/* Defines Ethernet Autonegotiation Timeout during initialization. + * Set it to 0 to disable the waiting. */ +#ifndef ENET_ATONEGOTIATION_TIMEOUT + #define ENET_ATONEGOTIATION_TIMEOUT (0xFFFU) +#endif + +/* Define those to better describe your network interface. */ +#define IFNAME0 'e' +#define IFNAME1 'n' + +#if defined(FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL) && FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL + #if defined(FSL_FEATURE_L2CACHE_LINESIZE_BYTE) \ + && ((!defined(FSL_SDK_DISBLE_L2CACHE_PRESENT)) || (FSL_SDK_DISBLE_L2CACHE_PRESENT == 0)) + #if defined(FSL_FEATURE_L1DCACHE_LINESIZE_BYTE) + #define FSL_CACHE_LINESIZE_MAX MAX(FSL_FEATURE_L1DCACHE_LINESIZE_BYTE, FSL_FEATURE_L2CACHE_LINESIZE_BYTE) + #define FSL_ENET_BUFF_ALIGNMENT MAX(ENET_BUFF_ALIGNMENT, FSL_CACHE_LINESIZE_MAX) + #else + #define FSL_ENET_BUFF_ALIGNMENT MAX(ENET_BUFF_ALIGNMENT, FSL_FEATURE_L2CACHE_LINESIZE_BYTE) + #endif + #elif defined(FSL_FEATURE_L1DCACHE_LINESIZE_BYTE) + #define FSL_ENET_BUFF_ALIGNMENT MAX(ENET_BUFF_ALIGNMENT, FSL_FEATURE_L1DCACHE_LINESIZE_BYTE) + #else + #define FSL_ENET_BUFF_ALIGNMENT ENET_BUFF_ALIGNMENT + #endif +#else + #define FSL_ENET_BUFF_ALIGNMENT ENET_BUFF_ALIGNMENT +#endif + +#define ENET_RING_NUM 1U + +typedef uint8_t rx_buffer_t[SDK_SIZEALIGN(ENET_RXBUFF_SIZE, FSL_ENET_BUFF_ALIGNMENT)]; +typedef uint8_t tx_buffer_t[SDK_SIZEALIGN(ENET_TXBUFF_SIZE, FSL_ENET_BUFF_ALIGNMENT)]; + +#if (defined(FSL_FEATURE_SOC_LPC_ENET_COUNT) && (FSL_FEATURE_SOC_LPC_ENET_COUNT > 0)) +typedef struct mem_range +{ + uint32_t start; + uint32_t end; +} mem_range_t; +#endif /* FSL_FEATURE_SOC_LPC_ENET_COUNT */ + +/** + * Helper struct to hold data for configuration of ethernet interface. + */ +typedef struct ethernetif_config +{ + uint32_t phyAddress; + clock_name_t clockName; + uint8_t macAddress[NETIF_MAX_HWADDR_LEN]; +#if (defined(FSL_FEATURE_SOC_LPC_ENET_COUNT) && (FSL_FEATURE_SOC_LPC_ENET_COUNT > 0)) + const mem_range_t *non_dma_memory; +#endif /* FSL_FEATURE_SOC_LPC_ENET_COUNT */ +} ethernetif_config_t; + +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus */ + +/** + * This function should be passed as a parameter to netif_add() + * if you initialize the first ENET interface. + */ +err_t ethernetif0_init(struct netif *netif); + +#if (defined(FSL_FEATURE_SOC_ENET_COUNT) && (FSL_FEATURE_SOC_ENET_COUNT > 1)) \ + || (defined(FSL_FEATURE_SOC_LPC_ENET_COUNT) && (FSL_FEATURE_SOC_LPC_ENET_COUNT > 1)) +/** + * This function should be passed as a parameter to netif_add() + * if you initialize the second ENET interface. + */ +err_t ethernetif1_init(struct netif *netif); +#endif /* FSL_FEATURE_SOC_*_ENET_COUNT */ + +/** + * This function should be called when a packet is ready to be read + * from the interface. + * It is used by bare-metal applications. + * + * @param netif the lwip network interface structure for this ethernetif + */ +void ethernetif_input( struct netif *netif); + +void ETH_BSP_Config(void); + +int32 lwip_obtain_semaphore(struct netif *netif); + +#if defined(__cplusplus) +} +#endif /* __cplusplus */ + +#endif /* ENET_ETHERNETIF_H */ diff --git a/Ubiquitous/XiZi/board/xidatong/third_party_driver/include/enet_ethernetif_priv.h b/Ubiquitous/XiZi/board/xidatong/third_party_driver/include/enet_ethernetif_priv.h new file mode 100755 index 0000000..5594667 --- /dev/null +++ b/Ubiquitous/XiZi/board/xidatong/third_party_driver/include/enet_ethernetif_priv.h @@ -0,0 +1,82 @@ +/* + * Copyright 2019 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +/** + * @file enet_ethernetif_priv.h + * @brief ethernet drivers + * @version 1.0 + * @author AIIT XUOS Lab + * @date 2021.11.11 + */ + + +#ifndef ENET_ETHERNETIF_PRIV_H +#define ENET_ETHERNETIF_PRIV_H + +#include "lwip/err.h" + +struct ethernetif; + +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus */ + +err_t ethernetif_init(struct netif *netif, struct ethernetif *ethernetif, + const uint8_t enetIdx, + const ethernetif_config_t *ethernetifConfig); + +void ethernetif_enet_init(struct netif *netif, struct ethernetif *ethernetif, + const ethernetif_config_t *ethernetifConfig); + +void ethernetif_phy_init(struct ethernetif *ethernetif, + const ethernetif_config_t *ethernetifConfig, + enet_config_t *config); + +ENET_Type **ethernetif_enet_ptr(struct ethernetif *ethernetif); + +#if LWIP_IPV4 && LWIP_IGMP +err_t ethernetif_igmp_mac_filter(struct netif *netif, const ip4_addr_t *group, + enum netif_mac_filter_action action); +#endif + +#if LWIP_IPV6 && LWIP_IPV6_MLD +err_t ethernetif_mld_mac_filter(struct netif *netif, const ip6_addr_t *group, + enum netif_mac_filter_action action); +#endif + +/** + * Should allocate a pbuf and transfer the bytes of the incoming + * packet from the interface into the pbuf. + * + * @param netif the lwip network interface structure for this ethernetif + * @return a pbuf filled with the received packet (including MAC header) + * NULL on memory error + */ +struct pbuf *ethernetif_linkinput(struct netif *netif); + +/** + * This function should do the actual transmission of the packet. The packet is + * contained in the pbuf that is passed to the function. This pbuf + * might be chained. + * + * @param netif the lwip network interface structure for this ethernetif + * @param p the MAC packet to send (e.g. IP packet including MAC addresses and type) + * @return ERR_OK if the packet could be sent + * an err_t value if the packet couldn't be sent + * + * @note Returning ERR_MEM here if a DMA queue of your MAC is full can lead to + * strange results. You might consider waiting for space in the DMA queue + * to become available since the stack doesn't retry to send a packet + * dropped because of memory failure (except for the TCP timers). + */ +err_t ethernetif_linkoutput(struct netif *netif, struct pbuf *p); + +#if defined(__cplusplus) +} +#endif /* __cplusplus */ + +#endif /* ENET_ETHERNETIF_PRIV_H */ diff --git a/Ubiquitous/XiZi/board/xidatong/third_party_driver/include/fsl_cache.h b/Ubiquitous/XiZi/board/xidatong/third_party_driver/include/fsl_cache.h new file mode 100755 index 0000000..e5f67ed --- /dev/null +++ b/Ubiquitous/XiZi/board/xidatong/third_party_driver/include/fsl_cache.h @@ -0,0 +1,476 @@ +/* + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +/** + * @file fsl_cache.h + * @brief cache drivers + * @version 2.0 + * @author AIIT XUOS Lab + * @date 2022-03-15 + */ + +#ifndef _FSL_CACHE_H_ +#define _FSL_CACHE_H_ + +#include "fsl_common.h" + +/*! + * @addtogroup cache + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @name Driver version */ +/*@{*/ +/*! @brief cache driver version 2.0.1. */ +#define FSL_CACHE_DRIVER_VERSION (MAKE_VERSION(2, 0, 1)) +/*@}*/ + +#if defined(FSL_FEATURE_SOC_L2CACHEC_COUNT) && FSL_FEATURE_SOC_L2CACHEC_COUNT +#ifndef FSL_SDK_DISBLE_L2CACHE_PRESENT +#define FSL_SDK_DISBLE_L2CACHE_PRESENT 0 +#endif +#endif /* FSL_FEATURE_SOC_L2CACHEC_COUNT */ +/******************************************************************************* + * Definitions + ******************************************************************************/ +#if defined(FSL_FEATURE_SOC_L2CACHEC_COUNT) && FSL_FEATURE_SOC_L2CACHEC_COUNT + +/*! @brief Number of level 2 cache controller ways. */ +typedef enum _l2cache_way_num +{ + kL2CACHE_8ways = 0, /*!< 8 ways. */ +#if defined(FSL_FEATURE_L2CACHE_SUPPORT_16_WAY_ASSOCIATIVITY) && FSL_FEATURE_L2CACHE_SUPPORT_16_WAY_ASSOCIATIVITY + kL2CACHE_16ways /*!< 16 ways. */ +#endif /* FSL_FEATURE_L2CACHE_SUPPORT_16_WAY_ASSOCIATIVITY */ +} l2cache_way_num_t; + +/*! @brief Level 2 cache controller way size. */ +typedef enum _l2cache_way_size +{ + kL2CACHE_16KBSize = 1, /*!< 16 KB way size. */ + kL2CACHE_32KBSize = 2, /*!< 32 KB way size. */ + kL2CACHE_64KBSize = 3, /*!< 64 KB way size. */ + kL2CACHE_128KBSize = 4, /*!< 128 KB way size. */ + kL2CACHE_256KBSize = 5, /*!< 256 KB way size. */ + kL2CACHE_512KBSize = 6 /*!< 512 KB way size. */ +} l2cache_way_size; + +/*! @brief Level 2 cache controller replacement policy. */ +typedef enum _l2cache_replacement +{ + kL2CACHE_Pseudorandom = 0U, /*!< Peseudo-random replacement policy using an lfsr. */ + kL2CACHE_Roundrobin /*!< Round-robin replacemnt policy. */ +} l2cache_replacement_t; + +/*! @brief Level 2 cache controller force write allocate options. */ +typedef enum _l2cache_writealloc +{ + kL2CACHE_UseAwcache = 0, /*!< Use AWCAHE attribute for the write allocate. */ + kL2CACHE_NoWriteallocate, /*!< Force no write allocate. */ + kL2CACHE_forceWriteallocate /*!< Force write allocate when write misses. */ +} l2cache_writealloc_t; + +/*! @brief Level 2 cache controller tag/data ram latency. */ +typedef enum _l2cache_latency +{ + kL2CACHE_1CycleLate = 0, /*!< 1 cycle of latency. */ + kL2CACHE_2CycleLate, /*!< 2 cycle of latency. */ + kL2CACHE_3CycleLate, /*!< 3 cycle of latency. */ + kL2CACHE_4CycleLate, /*!< 4 cycle of latency. */ + kL2CACHE_5CycleLate, /*!< 5 cycle of latency. */ + kL2CACHE_6CycleLate, /*!< 6 cycle of latency. */ + kL2CACHE_7CycleLate, /*!< 7 cycle of latency. */ + kL2CACHE_8CycleLate /*!< 8 cycle of latency. */ +} l2cache_latency_t; + +/*! @brief Level 2 cache controller tag/data ram latency configure structure. */ +typedef struct _l2cache_latency_config +{ + l2cache_latency_t tagWriteLate; /*!< Tag write latency. */ + l2cache_latency_t tagReadLate; /*!< Tag Read latency. */ + l2cache_latency_t tagSetupLate; /*!< Tag setup latency. */ + l2cache_latency_t dataWriteLate; /*!< Data write latency. */ + l2cache_latency_t dataReadLate; /*!< Data Read latency. */ + l2cache_latency_t dataSetupLate; /*!< Data setup latency. */ +} L2cache_latency_config_t; + +/*! @brief Level 2 cache controller configure structure. */ +typedef struct _l2cache_config +{ + /* ------------------------ l2 cachec basic settings ---------------------------- */ + l2cache_way_num_t wayNum; /*!< The number of ways. */ + l2cache_way_size waySize; /*!< The way size = Cache Ram size / wayNum. */ + l2cache_replacement_t repacePolicy; /*!< Replacemnet policy. */ + /* ------------------------ tag/data ram latency settings ----------------------- */ + L2cache_latency_config_t *lateConfig; /*!< Tag/data latency configure. Set NUll if not required. */ + /* ------------------------ Prefetch enable settings ---------------------------- */ + bool istrPrefetchEnable; /*!< Instruction prefetch enable. */ + bool dataPrefetchEnable; /*!< Data prefetch enable. */ + /* ------------------------ Non-secure access settings -------------------------- */ + bool nsLockdownEnable; /*!< None-secure lockdown enable. */ + /* ------------------------ other settings -------------------------------------- */ + l2cache_writealloc_t writeAlloc; /*!< Write allcoate force option. */ +} l2cache_config_t; +#endif /* FSL_FEATURE_SOC_L2CACHEC_COUNT */ +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @name Control for cortex-m7 L1 cache + *@{ + */ + +/*! + * @brief Enables cortex-m7 L1 instruction cache. + * + */ +static inline void L1CACHE_EnableICache(void) +{ + SCB_EnableICache(); +} + +/*! + * @brief Disables cortex-m7 L1 instruction cache. + * + */ +static inline void L1CACHE_DisableICache(void) +{ + SCB_DisableICache(); +} + +/*! + * @brief Invalidate cortex-m7 L1 instruction cache. + * + */ +static inline void L1CACHE_InvalidateICache(void) +{ + SCB_InvalidateICache(); +} + +/*! + * @brief Invalidate cortex-m7 L1 instruction cache by range. + * + * @param address The start address of the memory to be invalidated. + * @param size_byte The memory size. + * @note The start address and size_byte should be 32-byte(FSL_FEATURE_L1ICACHE_LINESIZE_BYTE) aligned. + * The startAddr here will be forced to align to L1 I-cache line size if + * startAddr is not aligned. For the size_byte, application should make sure the + * alignment or make sure the right operation order if the size_byte is not aligned. + */ +void L1CACHE_InvalidateICacheByRange(uint32_t address, uint32_t size_byte); + +/*! + * @brief Enables cortex-m7 L1 data cache. + * + */ +static inline void L1CACHE_EnableDCache(void) +{ + SCB_EnableDCache(); +} + +/*! + * @brief Disables cortex-m7 L1 data cache. + * + */ +static inline void L1CACHE_DisableDCache(void) +{ + SCB_DisableDCache(); +} + +/*! + * @brief Invalidates cortex-m7 L1 data cache. + * + */ +static inline void L1CACHE_InvalidateDCache(void) +{ + SCB_InvalidateDCache(); +} + +/*! + * @brief Cleans cortex-m7 L1 data cache. + * + */ +static inline void L1CACHE_CleanDCache(void) +{ + SCB_CleanDCache(); +} + +/*! + * @brief Cleans and Invalidates cortex-m7 L1 data cache. + * + */ +static inline void L1CACHE_CleanInvalidateDCache(void) +{ + SCB_CleanInvalidateDCache(); +} + +/*! + * @brief Invalidates cortex-m7 L1 data cache by range. + * + * @param address The start address of the memory to be invalidated. + * @param size_byte The memory size. + * @note The start address and size_byte should be 32-byte(FSL_FEATURE_L1DCACHE_LINESIZE_BYTE) aligned. + * The startAddr here will be forced to align to L1 D-cache line size if + * startAddr is not aligned. For the size_byte, application should make sure the + * alignment or make sure the right operation order if the size_byte is not aligned. + */ +static inline void L1CACHE_InvalidateDCacheByRange(uint32_t address, uint32_t size_byte) +{ + uint32_t startAddr = address & (uint32_t) ~(FSL_FEATURE_L1DCACHE_LINESIZE_BYTE - 1); + uint32_t size = size_byte + address - startAddr; + + SCB_InvalidateDCache_by_Addr((uint32_t *)startAddr, size); +} + +/*! + * @brief Cleans cortex-m7 L1 data cache by range. + * + * @param address The start address of the memory to be cleaned. + * @param size_byte The memory size. + * @note The start address and size_byte should be 32-byte(FSL_FEATURE_L1DCACHE_LINESIZE_BYTE) aligned. + * The startAddr here will be forced to align to L1 D-cache line size if + * startAddr is not aligned. For the size_byte, application should make sure the + * alignment or make sure the right operation order if the size_byte is not aligned. + */ +static inline void L1CACHE_CleanDCacheByRange(uint32_t address, uint32_t size_byte) +{ + uint32_t startAddr = address & (uint32_t) ~(FSL_FEATURE_L1DCACHE_LINESIZE_BYTE - 1); + uint32_t size = size_byte + address - startAddr; + + SCB_CleanDCache_by_Addr((uint32_t *)startAddr, size); +} + +/*! + * @brief Cleans and Invalidates cortex-m7 L1 data cache by range. + * + * @param address The start address of the memory to be clean and invalidated. + * @param size_byte The memory size. + * @note The start address and size_byte should be 32-byte(FSL_FEATURE_L1DCACHE_LINESIZE_BYTE) aligned. + * The startAddr here will be forced to align to L1 D-cache line size if + * startAddr is not aligned. For the size_byte, application should make sure the + * alignment or make sure the right operation order if the size_byte is not aligned. + */ +static inline void L1CACHE_CleanInvalidateDCacheByRange(uint32_t address, uint32_t size_byte) +{ + uint32_t startAddr = address & (uint32_t) ~(FSL_FEATURE_L1DCACHE_LINESIZE_BYTE - 1); + uint32_t size = size_byte + address - startAddr; + + SCB_CleanInvalidateDCache_by_Addr((uint32_t *)startAddr, size); +} +/*@}*/ + +#if defined(FSL_FEATURE_SOC_L2CACHEC_COUNT) && FSL_FEATURE_SOC_L2CACHEC_COUNT +/*! + * @name Control for L2 pl310 cache + *@{ + */ + +/*! + * @brief Initializes the level 2 cache controller module. + * + * @param config Pointer to configuration structure. See "l2cache_config_t". + */ +void L2CACHE_Init(l2cache_config_t *config); + +/*! + * @brief Gets an available default settings for the cache controller. + * + * This function initializes the cache controller configuration structure with default settings. + * The default values are: + * @code + * config->waysNum = kL2CACHE_8ways; + * config->waySize = kL2CACHE_32KbSize; + * config->repacePolicy = kL2CACHE_Roundrobin; + * config->lateConfig = NULL; + * config->istrPrefetchEnable = false; + * config->dataPrefetchEnable = false; + * config->nsLockdownEnable = false; + * config->writeAlloc = kL2CACHE_UseAwcache; + * @endcode + * @param config Pointer to the configuration structure. + */ +void L2CACHE_GetDefaultConfig(l2cache_config_t *config); + +/*! + * @brief Enables the level 2 cache controller. + * This function enables the cache controller. Must be written using a secure access. + * If write with a Non-secure access will cause a DECERR response. + * + */ +void L2CACHE_Enable(void); + +/*! + * @brief Disables the level 2 cache controller. + * This function disables the cache controller. Must be written using a secure access. + * If write with a Non-secure access will cause a DECERR response. + * + */ +void L2CACHE_Disable(void); + +/*! + * @brief Invalidates the Level 2 cache. + * This function invalidates all entries in cache. + * + */ +void L2CACHE_Invalidate(void); + +/*! + * @brief Invalidates the Level 2 cache lines in the range of two physical addresses. + * This function invalidates all cache lines between two physical addresses. + * + * @param address The start address of the memory to be invalidated. + * @param size_byte The memory size. + * @note The start address and size_byte should be 32-byte(FSL_FEATURE_L2CACHE_LINESIZE_BYTE) aligned. + * The startAddr here will be forced to align to L2 line size if startAddr + * is not aligned. For the size_byte, application should make sure the + * alignment or make sure the right operation order if the size_byte is not aligned. + */ +void L2CACHE_InvalidateByRange(uint32_t address, uint32_t size_byte); + +/*! + * @brief Cleans the level 2 cache controller. + * This function cleans all entries in the level 2 cache controller. + * + */ +void L2CACHE_Clean(void); + +/*! + * @brief Cleans the Level 2 cache lines in the range of two physical addresses. + * This function cleans all cache lines between two physical addresses. + * + * @param address The start address of the memory to be cleaned. + * @param size_byte The memory size. + * @note The start address and size_byte should be 32-byte(FSL_FEATURE_L2CACHE_LINESIZE_BYTE) aligned. + * The startAddr here will be forced to align to L2 line size if startAddr + * is not aligned. For the size_byte, application should make sure the + * alignment or make sure the right operation order if the size_byte is not aligned. + */ +void L2CACHE_CleanByRange(uint32_t address, uint32_t size_byte); + +/*! + * @brief Cleans and invalidates the level 2 cache controller. + * This function cleans and invalidates all entries in the level 2 cache controller. + * + */ +void L2CACHE_CleanInvalidate(void); + +/*! + * @brief Cleans and invalidates the Level 2 cache lines in the range of two physical addresses. + * This function cleans and invalidates all cache lines between two physical addresses. + * + * @param address The start address of the memory to be cleaned and invalidated. + * @param size_byte The memory size. + * @note The start address and size_byte should be 32-byte(FSL_FEATURE_L2CACHE_LINESIZE_BYTE) aligned. + * The startAddr here will be forced to align to L2 line size if startAddr + * is not aligned. For the size_byte, application should make sure the + * alignment or make sure the right operation order if the size_byte is not aligned. + */ +void L2CACHE_CleanInvalidateByRange(uint32_t address, uint32_t size_byte); + +/*! + * @brief Enables or disables to lock down the data and instruction by way. + * This function locks down the cached instruction/data by way and prevent the adresses from + * being allocated and prevent dara from being evicted out of the level 2 cache. + * But the normal cache maintenance operations that invalidate, clean or clean + * and validate cache contents affect the locked-down cache lines as normal. + * + * @param masterId The master id, range from 0 ~ 7. + * @param mask The ways to be enabled or disabled to lockdown. + * each bit in value is related to each way of the cache. for example: + * value: bit 0 ------ way 0. + * value: bit 1 ------ way 1. + * -------------------------- + * value: bit 15 ------ way 15. + * Note: please make sure the value setting is align with your supported ways. + * @param enable True enable the lockdown, false to disable the lockdown. + */ +void L2CACHE_LockdownByWayEnable(uint32_t masterId, uint32_t mask, bool enable); + +/*@}*/ +#endif /* FSL_FEATURE_SOC_L2CACHEC_COUNT */ + +/*! + * @name Unified Cache Control for all caches (cortex-m7 L1 cache + l2 pl310) + * Mainly used for many drivers for easy cache operation. + *@{ + */ + +/*! + * @brief Invalidates all instruction caches by range. + * + * Both cortex-m7 L1 cache line and L2 PL310 cache line length is 32-byte. + * + * @param address The physical address. + * @param size_byte size of the memory to be invalidated. + * @note address and size should be aligned to cache line size + * 32-Byte due to the cache operation unit is one cache line. The startAddr here will be forced + * to align to the cache line size if startAddr is not aligned. For the size_byte, application should + * make sure the alignment or make sure the right operation order if the size_byte is not aligned. + */ +void ICACHE_InvalidateByRange(uint32_t address, uint32_t size_byte); + +/*! + * @brief Invalidates all data caches by range. + * + * Both cortex-m7 L1 cache line and L2 PL310 cache line length is 32-byte. + * + * @param address The physical address. + * @param size_byte size of the memory to be invalidated. + * @note address and size should be aligned to cache line size + * 32-Byte due to the cache operation unit is one cache line. The startAddr here will be forced + * to align to the cache line size if startAddr is not aligned. For the size_byte, application should + * make sure the alignment or make sure the right operation order if the size_byte is not aligned. + */ +void DCACHE_InvalidateByRange(uint32_t address, uint32_t size_byte); + +/*! + * @brief Cleans all data caches by range. + * + * Both cortex-m7 L1 cache line and L2 PL310 cache line length is 32-byte. + * + * @param address The physical address. + * @param size_byte size of the memory to be cleaned. + * @note address and size should be aligned to cache line size + * 32-Byte due to the cache operation unit is one cache line. The startAddr here will be forced + * to align to the cache line size if startAddr is not aligned. For the size_byte, application should + * make sure the alignment or make sure the right operation order if the size_byte is not aligned. + */ +void DCACHE_CleanByRange(uint32_t address, uint32_t size_byte); + +/*! + * @brief Cleans and Invalidates all data caches by range. + * + * Both cortex-m7 L1 cache line and L2 PL310 cache line length is 32-byte. + * + * @param address The physical address. + * @param size_byte size of the memory to be cleaned and invalidated. + * @note address and size should be aligned to cache line size + * 32-Byte due to the cache operation unit is one cache line. The startAddr here will be forced + * to align to the cache line size if startAddr is not aligned. For the size_byte, application should + * make sure the alignment or make sure the right operation order if the size_byte is not aligned. + */ +void DCACHE_CleanInvalidateByRange(uint32_t address, uint32_t size_byte); + +/*@}*/ + +#if defined(__cplusplus) +} +#endif + +/*! @}*/ + +#endif /* _FSL_CACHE_H_*/ diff --git a/Ubiquitous/XiZi/board/xidatong/third_party_driver/include/fsl_clock.h b/Ubiquitous/XiZi/board/xidatong/third_party_driver/include/fsl_clock.h new file mode 100755 index 0000000..3dfefed --- /dev/null +++ b/Ubiquitous/XiZi/board/xidatong/third_party_driver/include/fsl_clock.h @@ -0,0 +1,1568 @@ +/* + * Copyright 2017 - 2019 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +/** + * @file fsl_clock.h + * @brief clock drivers + * @version 2.0 + * @author AIIT XUOS Lab + * @date 2022-03-15 + */ + +#ifndef _FSL_CLOCK_H_ +#define _FSL_CLOCK_H_ + +#include "fsl_common.h" + +/*! @addtogroup clock */ +/*! @{ */ + +/*! @file */ + +/******************************************************************************* + * Configurations + ******************************************************************************/ + +/*! @brief Configure whether driver controls clock + * + * When set to 0, peripheral drivers will enable clock in initialize function + * and disable clock in de-initialize function. When set to 1, peripheral + * driver will not control the clock, application could control the clock out of + * the driver. + * + * @note All drivers share this feature switcher. If it is set to 1, application + * should handle clock enable and disable for all drivers. + */ +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)) +#define FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL 0 +#endif + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @name Driver version */ +/*@{*/ +/*! @brief CLOCK driver version 2.2.0. */ +#define FSL_CLOCK_DRIVER_VERSION (MAKE_VERSION(2, 2, 0)) + +/* Definition for delay API in clock driver, users can redefine it to the real application. */ +#ifndef SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY +#define SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY (600000000UL) +#endif + +/* analog pll definition */ +#define CCM_ANALOG_PLL_BYPASS_SHIFT (16U) +#define CCM_ANALOG_PLL_BYPASS_CLK_SRC_MASK (0xC000U) +#define CCM_ANALOG_PLL_BYPASS_CLK_SRC_SHIFT (14U) + +/*@}*/ + +/*! + * @brief CCM registers offset. + */ +#define CCSR_OFFSET 0x0C +#define CBCDR_OFFSET 0x14 +#define CBCMR_OFFSET 0x18 +#define CSCMR1_OFFSET 0x1C +#define CSCMR2_OFFSET 0x20 +#define CSCDR1_OFFSET 0x24 +#define CDCDR_OFFSET 0x30 +#define CSCDR2_OFFSET 0x38 +#define CSCDR3_OFFSET 0x3C +#define CACRR_OFFSET 0x10 +#define CS1CDR_OFFSET 0x28 +#define CS2CDR_OFFSET 0x2C + +/*! + * @brief CCM Analog registers offset. + */ +#define PLL_ARM_OFFSET 0x00 +#define PLL_SYS_OFFSET 0x30 +#define PLL_USB1_OFFSET 0x10 +#define PLL_AUDIO_OFFSET 0x70 +#define PLL_VIDEO_OFFSET 0xA0 +#define PLL_ENET_OFFSET 0xE0 +#define PLL_USB2_OFFSET 0x20 + +#define CCM_TUPLE(reg, shift, mask, busyShift) \ + (int)((reg & 0xFFU) | ((shift) << 8U) | ((((mask) >> (shift)) & 0x1FFFU) << 13U) | ((busyShift) << 26U)) +#define CCM_TUPLE_REG(base, tuple) (*((volatile uint32_t *)(((uint32_t)(base)) + ((tuple)&0xFFU)))) +#define CCM_TUPLE_SHIFT(tuple) (((tuple) >> 8U) & 0x1FU) +#define CCM_TUPLE_MASK(tuple) ((uint32_t)((((tuple) >> 13U) & 0x1FFFU) << ((((tuple) >> 8U) & 0x1FU)))) +#define CCM_TUPLE_BUSY_SHIFT(tuple) (((tuple) >> 26U) & 0x3FU) + +#define CCM_NO_BUSY_WAIT (0x20U) + +/*! + * @brief CCM ANALOG tuple macros to map corresponding registers and bit fields. + */ +#define CCM_ANALOG_TUPLE(reg, shift) (((reg & 0xFFFU) << 16U) | (shift)) +#define CCM_ANALOG_TUPLE_SHIFT(tuple) (((uint32_t)tuple) & 0x1FU) +#define CCM_ANALOG_TUPLE_REG_OFF(base, tuple, off) \ + (*((volatile uint32_t *)((uint32_t)base + (((uint32_t)tuple >> 16U) & 0xFFFU) + off))) +#define CCM_ANALOG_TUPLE_REG(base, tuple) CCM_ANALOG_TUPLE_REG_OFF(base, tuple, 0U) + +/*! + * @brief clock1PN frequency. + */ +#define CLKPN_FREQ 0U + +/*! @brief External XTAL (24M OSC/SYSOSC) clock frequency. + * + * The XTAL (24M OSC/SYSOSC) clock frequency in Hz, when the clock is setup, use the + * function CLOCK_SetXtalFreq to set the value in to clock driver. For example, + * if XTAL is 24MHz, + * @code + * CLOCK_InitExternalClk(false); // Setup the 24M OSC/SYSOSC + * CLOCK_SetXtalFreq(240000000); // Set the XTAL value to clock driver. + * @endcode + */ +extern volatile uint32_t g_xtalFreq; + +/*! @brief External RTC XTAL (32K OSC) clock frequency. + * + * The RTC XTAL (32K OSC) clock frequency in Hz, when the clock is setup, use the + * function CLOCK_SetRtcXtalFreq to set the value in to clock driver. + */ +extern volatile uint32_t g_rtcXtalFreq; + +/* For compatible with other platforms */ +#define CLOCK_SetXtal0Freq CLOCK_SetXtalFreq +#define CLOCK_SetXtal32Freq CLOCK_SetRtcXtalFreq + +/*! @brief Clock ip name array for ADC. */ +#define ADC_CLOCKS \ + { \ + kCLOCK_IpInvalid, kCLOCK_Adc1, kCLOCK_Adc2 \ + } + +/*! @brief Clock ip name array for AOI. */ +#define AOI_CLOCKS \ + { \ + kCLOCK_IpInvalid, kCLOCK_Aoi1, kCLOCK_Aoi2 \ + } + +/*! @brief Clock ip name array for BEE. */ +#define BEE_CLOCKS \ + { \ + kCLOCK_Bee \ + } + +/*! @brief Clock ip name array for CMP. */ +#define CMP_CLOCKS \ + { \ + kCLOCK_IpInvalid, kCLOCK_Acmp1, kCLOCK_Acmp2, kCLOCK_Acmp3, kCLOCK_Acmp4 \ + } + +/*! @brief Clock ip name array for CSI. */ +#define CSI_CLOCKS \ + { \ + kCLOCK_Csi \ + } + +/*! @brief Clock ip name array for DCDC. */ +#define DCDC_CLOCKS \ + { \ + kCLOCK_Dcdc \ + } + +/*! @brief Clock ip name array for DCP. */ +#define DCP_CLOCKS \ + { \ + kCLOCK_Dcp \ + } + +/*! @brief Clock ip name array for DMAMUX_CLOCKS. */ +#define DMAMUX_CLOCKS \ + { \ + kCLOCK_Dma \ + } + +/*! @brief Clock ip name array for DMA. */ +#define EDMA_CLOCKS \ + { \ + kCLOCK_Dma \ + } + +/*! @brief Clock ip name array for ENC. */ +#define ENC_CLOCKS \ + { \ + kCLOCK_IpInvalid, kCLOCK_Enc1, kCLOCK_Enc2, kCLOCK_Enc3, kCLOCK_Enc4 \ + } + +/*! @brief Clock ip name array for ENET. */ +#define ENET_CLOCKS \ + { \ + kCLOCK_Enet \ + } + +/*! @brief Clock ip name array for EWM. */ +#define EWM_CLOCKS \ + { \ + kCLOCK_Ewm0 \ + } + +/*! @brief Clock ip name array for FLEXCAN. */ +#define FLEXCAN_CLOCKS \ + { \ + kCLOCK_IpInvalid, kCLOCK_Can1, kCLOCK_Can2 \ + } + +/*! @brief Clock ip name array for FLEXCAN Peripheral clock. */ +#define FLEXCAN_PERIPH_CLOCKS \ + { \ + kCLOCK_IpInvalid, kCLOCK_Can1S, kCLOCK_Can2S \ + } + +/*! @brief Clock ip name array for FLEXIO. */ +#define FLEXIO_CLOCKS \ + { \ + kCLOCK_IpInvalid, kCLOCK_Flexio1, kCLOCK_Flexio2 \ + } + +/*! @brief Clock ip name array for FLEXRAM. */ +#define FLEXRAM_CLOCKS \ + { \ + kCLOCK_FlexRam \ + } + +/*! @brief Clock ip name array for FLEXSPI. */ +#define FLEXSPI_CLOCKS \ + { \ + kCLOCK_FlexSpi \ + } + +/*! @brief Clock ip name array for FLEXSPI EXSC. */ +#define FLEXSPI_EXSC_CLOCKS \ + { \ + kCLOCK_FlexSpiExsc \ + } + +/*! @brief Clock ip name array for GPIO. */ +#define GPIO_CLOCKS \ + { \ + kCLOCK_IpInvalid, kCLOCK_Gpio1, kCLOCK_Gpio2, kCLOCK_Gpio3, kCLOCK_Gpio4, kCLOCK_Gpio5 \ + } + +/*! @brief Clock ip name array for GPT. */ +#define GPT_CLOCKS \ + { \ + kCLOCK_IpInvalid, kCLOCK_Gpt1, kCLOCK_Gpt2 \ + } + +/*! @brief Clock ip name array for KPP. */ +#define KPP_CLOCKS \ + { \ + kCLOCK_Kpp \ + } + +/*! @brief Clock ip name array for LCDIF. */ +#define LCDIF_CLOCKS \ + { \ + kCLOCK_Lcd \ + } + +/*! @brief Clock ip name array for LCDIF PIXEL. */ +#define LCDIF_PERIPH_CLOCKS \ + { \ + kCLOCK_LcdPixel \ + } + +/*! @brief Clock ip name array for LPI2C. */ +#define LPI2C_CLOCKS \ + { \ + kCLOCK_IpInvalid, kCLOCK_Lpi2c1, kCLOCK_Lpi2c2, kCLOCK_Lpi2c3, kCLOCK_Lpi2c4 \ + } + +/*! @brief Clock ip name array for LPSPI. */ +#define LPSPI_CLOCKS \ + { \ + kCLOCK_IpInvalid, kCLOCK_Lpspi1, kCLOCK_Lpspi2, kCLOCK_Lpspi3, kCLOCK_Lpspi4 \ + } + +/*! @brief Clock ip name array for LPUART. */ +#define LPUART_CLOCKS \ + { \ + kCLOCK_IpInvalid, kCLOCK_Lpuart1, kCLOCK_Lpuart2, kCLOCK_Lpuart3, kCLOCK_Lpuart4, kCLOCK_Lpuart5, \ + kCLOCK_Lpuart6, kCLOCK_Lpuart7, kCLOCK_Lpuart8 \ + } + +/*! @brief Clock ip name array for MQS. */ +#define MQS_CLOCKS \ + { \ + kCLOCK_Mqs \ + } + +/*! @brief Clock ip name array for OCRAM EXSC. */ +#define OCRAM_EXSC_CLOCKS \ + { \ + kCLOCK_OcramExsc \ + } + +/*! @brief Clock ip name array for PIT. */ +#define PIT_CLOCKS \ + { \ + kCLOCK_Pit \ + } + +/*! @brief Clock ip name array for PWM. */ +#define PWM_CLOCKS \ + { \ + {kCLOCK_IpInvalid, kCLOCK_IpInvalid, kCLOCK_IpInvalid, kCLOCK_IpInvalid}, \ + {kCLOCK_Pwm1, kCLOCK_Pwm1, kCLOCK_Pwm1, kCLOCK_Pwm1}, \ + {kCLOCK_Pwm2, kCLOCK_Pwm2, kCLOCK_Pwm2, kCLOCK_Pwm2}, \ + {kCLOCK_Pwm3, kCLOCK_Pwm3, kCLOCK_Pwm3, kCLOCK_Pwm3}, \ + { \ + kCLOCK_Pwm4, kCLOCK_Pwm4, kCLOCK_Pwm4, kCLOCK_Pwm4 \ + } \ + } + +/*! @brief Clock ip name array for PXP. */ +#define PXP_CLOCKS \ + { \ + kCLOCK_Pxp \ + } + +/*! @brief Clock ip name array for RTWDOG. */ +#define RTWDOG_CLOCKS \ + { \ + kCLOCK_Wdog3 \ + } + +/*! @brief Clock ip name array for SAI. */ +#define SAI_CLOCKS \ + { \ + kCLOCK_IpInvalid, kCLOCK_Sai1, kCLOCK_Sai2, kCLOCK_Sai3 \ + } + +/*! @brief Clock ip name array for SEMC. */ +#define SEMC_CLOCKS \ + { \ + kCLOCK_Semc \ + } + +/*! @brief Clock ip name array for SEMC EXSC. */ +#define SEMC_EXSC_CLOCKS \ + { \ + kCLOCK_SemcExsc \ + } + +/*! @brief Clock ip name array for QTIMER. */ +#define TMR_CLOCKS \ + { \ + kCLOCK_IpInvalid, kCLOCK_Timer1, kCLOCK_Timer2, kCLOCK_Timer3, kCLOCK_Timer4 \ + } + +/*! @brief Clock ip name array for TRNG. */ +#define TRNG_CLOCKS \ + { \ + kCLOCK_Trng \ + } + +/*! @brief Clock ip name array for TSC. */ +#define TSC_CLOCKS \ + { \ + kCLOCK_Tsc \ + } + +/*! @brief Clock ip name array for WDOG. */ +#define WDOG_CLOCKS \ + { \ + kCLOCK_IpInvalid, kCLOCK_Wdog1, kCLOCK_Wdog2 \ + } + +/*! @brief Clock ip name array for USDHC. */ +#define USDHC_CLOCKS \ + { \ + kCLOCK_IpInvalid, kCLOCK_Usdhc1, kCLOCK_Usdhc2 \ + } + +/*! @brief Clock ip name array for SPDIF. */ +#define SPDIF_CLOCKS \ + { \ + kCLOCK_Spdif \ + } + +/*! @brief Clock ip name array for XBARA. */ +#define XBARA_CLOCKS \ + { \ + kCLOCK_Xbar1 \ + } + +/*! @brief Clock ip name array for XBARB. */ +#define XBARB_CLOCKS \ + { \ + kCLOCK_IpInvalid, kCLOCK_IpInvalid, kCLOCK_Xbar2, kCLOCK_Xbar3 \ + } + +/*! @brief Clock name used to get clock frequency. */ +typedef enum _clock_name +{ + kCLOCK_CpuClk = 0x0U, /*!< CPU clock */ + kCLOCK_AhbClk = 0x1U, /*!< AHB clock */ + kCLOCK_SemcClk = 0x2U, /*!< SEMC clock */ + kCLOCK_IpgClk = 0x3U, /*!< IPG clock */ + kCLOCK_PerClk = 0x4U, /*!< PER clock */ + + kCLOCK_OscClk = 0x5U, /*!< OSC clock selected by PMU_LOWPWR_CTRL[OSC_SEL]. */ + kCLOCK_RtcClk = 0x6U, /*!< RTC clock. (RTCCLK) */ + + kCLOCK_ArmPllClk = 0x7U, /*!< ARMPLLCLK. */ + + kCLOCK_Usb1PllClk = 0x8U, /*!< USB1PLLCLK. */ + kCLOCK_Usb1PllPfd0Clk = 0x9U, /*!< USB1PLLPDF0CLK. */ + kCLOCK_Usb1PllPfd1Clk = 0xAU, /*!< USB1PLLPFD1CLK. */ + kCLOCK_Usb1PllPfd2Clk = 0xBU, /*!< USB1PLLPFD2CLK. */ + kCLOCK_Usb1PllPfd3Clk = 0xCU, /*!< USB1PLLPFD3CLK. */ + + kCLOCK_Usb2PllClk = 0xDU, /*!< USB2PLLCLK. */ + + kCLOCK_SysPllClk = 0xEU, /*!< SYSPLLCLK. */ + kCLOCK_SysPllPfd0Clk = 0xFU, /*!< SYSPLLPDF0CLK. */ + kCLOCK_SysPllPfd1Clk = 0x10U, /*!< SYSPLLPFD1CLK. */ + kCLOCK_SysPllPfd2Clk = 0x11U, /*!< SYSPLLPFD2CLK. */ + kCLOCK_SysPllPfd3Clk = 0x12U, /*!< SYSPLLPFD3CLK. */ + + kCLOCK_EnetPll0Clk = 0x13U, /*!< Enet PLLCLK ref_enetpll0. */ + kCLOCK_EnetPll1Clk = 0x14U, /*!< Enet PLLCLK ref_enetpll1. */ + + kCLOCK_AudioPllClk = 0x15U, /*!< Audio PLLCLK. */ + kCLOCK_VideoPllClk = 0x16U, /*!< Video PLLCLK. */ +} clock_name_t; + +#define kCLOCK_CoreSysClk kCLOCK_CpuClk /*!< For compatible with other platforms without CCM. */ +#define CLOCK_GetCoreSysClkFreq CLOCK_GetCpuClkFreq /*!< For compatible with other platforms without CCM. */ + +/*! + * @brief CCM CCGR gate control for each module independently. + */ +typedef enum _clock_ip_name +{ + kCLOCK_IpInvalid = -1, + + /* CCM CCGR0 */ + kCLOCK_Aips_tz1 = (0U << 8U) | CCM_CCGR0_CG0_SHIFT, /*!< CCGR0, CG0 */ + kCLOCK_Aips_tz2 = (0U << 8U) | CCM_CCGR0_CG1_SHIFT, /*!< CCGR0, CG1 */ + kCLOCK_Mqs = (0U << 8U) | CCM_CCGR0_CG2_SHIFT, /*!< CCGR0, CG2 */ + kCLOCK_FlexSpiExsc = (0U << 8U) | CCM_CCGR0_CG3_SHIFT, /*!< CCGR0, CG3 */ + kCLOCK_Sim_M_Main = (0U << 8U) | CCM_CCGR0_CG4_SHIFT, /*!< CCGR0, CG4 */ + kCLOCK_Dcp = (0U << 8U) | CCM_CCGR0_CG5_SHIFT, /*!< CCGR0, CG5 */ + kCLOCK_Lpuart3 = (0U << 8U) | CCM_CCGR0_CG6_SHIFT, /*!< CCGR0, CG6 */ + kCLOCK_Can1 = (0U << 8U) | CCM_CCGR0_CG7_SHIFT, /*!< CCGR0, CG7 */ + kCLOCK_Can1S = (0U << 8U) | CCM_CCGR0_CG8_SHIFT, /*!< CCGR0, CG8 */ + kCLOCK_Can2 = (0U << 8U) | CCM_CCGR0_CG9_SHIFT, /*!< CCGR0, CG9 */ + kCLOCK_Can2S = (0U << 8U) | CCM_CCGR0_CG10_SHIFT, /*!< CCGR0, CG10 */ + kCLOCK_Trace = (0U << 8U) | CCM_CCGR0_CG11_SHIFT, /*!< CCGR0, CG11 */ + kCLOCK_Gpt2 = (0U << 8U) | CCM_CCGR0_CG12_SHIFT, /*!< CCGR0, CG12 */ + kCLOCK_Gpt2S = (0U << 8U) | CCM_CCGR0_CG13_SHIFT, /*!< CCGR0, CG13 */ + kCLOCK_Lpuart2 = (0U << 8U) | CCM_CCGR0_CG14_SHIFT, /*!< CCGR0, CG14 */ + kCLOCK_Gpio2 = (0U << 8U) | CCM_CCGR0_CG15_SHIFT, /*!< CCGR0, CG15 */ + + /* CCM CCGR1 */ + kCLOCK_Lpspi1 = (1U << 8U) | CCM_CCGR1_CG0_SHIFT, /*!< CCGR1, CG0 */ + kCLOCK_Lpspi2 = (1U << 8U) | CCM_CCGR1_CG1_SHIFT, /*!< CCGR1, CG1 */ + kCLOCK_Lpspi3 = (1U << 8U) | CCM_CCGR1_CG2_SHIFT, /*!< CCGR1, CG2 */ + kCLOCK_Lpspi4 = (1U << 8U) | CCM_CCGR1_CG3_SHIFT, /*!< CCGR1, CG3 */ + kCLOCK_Adc2 = (1U << 8U) | CCM_CCGR1_CG4_SHIFT, /*!< CCGR1, CG4 */ + kCLOCK_Enet = (1U << 8U) | CCM_CCGR1_CG5_SHIFT, /*!< CCGR1, CG5 */ + kCLOCK_Pit = (1U << 8U) | CCM_CCGR1_CG6_SHIFT, /*!< CCGR1, CG6 */ + kCLOCK_Aoi2 = (1U << 8U) | CCM_CCGR1_CG7_SHIFT, /*!< CCGR1, CG7 */ + kCLOCK_Adc1 = (1U << 8U) | CCM_CCGR1_CG8_SHIFT, /*!< CCGR1, CG8 */ + kCLOCK_SemcExsc = (1U << 8U) | CCM_CCGR1_CG9_SHIFT, /*!< CCGR1, CG9 */ + kCLOCK_Gpt1 = (1U << 8U) | CCM_CCGR1_CG10_SHIFT, /*!< CCGR1, CG10 */ + kCLOCK_Gpt1S = (1U << 8U) | CCM_CCGR1_CG11_SHIFT, /*!< CCGR1, CG11 */ + kCLOCK_Lpuart4 = (1U << 8U) | CCM_CCGR1_CG12_SHIFT, /*!< CCGR1, CG12 */ + kCLOCK_Gpio1 = (1U << 8U) | CCM_CCGR1_CG13_SHIFT, /*!< CCGR1, CG13 */ + kCLOCK_Csu = (1U << 8U) | CCM_CCGR1_CG14_SHIFT, /*!< CCGR1, CG14 */ + kCLOCK_Gpio5 = (1U << 8U) | CCM_CCGR1_CG15_SHIFT, /*!< CCGR1, CG15 */ + + /* CCM CCGR2 */ + kCLOCK_OcramExsc = (2U << 8U) | CCM_CCGR2_CG0_SHIFT, /*!< CCGR2, CG0 */ + kCLOCK_Csi = (2U << 8U) | CCM_CCGR2_CG1_SHIFT, /*!< CCGR2, CG1 */ + kCLOCK_IomuxcSnvs = (2U << 8U) | CCM_CCGR2_CG2_SHIFT, /*!< CCGR2, CG2 */ + kCLOCK_Lpi2c1 = (2U << 8U) | CCM_CCGR2_CG3_SHIFT, /*!< CCGR2, CG3 */ + kCLOCK_Lpi2c2 = (2U << 8U) | CCM_CCGR2_CG4_SHIFT, /*!< CCGR2, CG4 */ + kCLOCK_Lpi2c3 = (2U << 8U) | CCM_CCGR2_CG5_SHIFT, /*!< CCGR2, CG5 */ + kCLOCK_Ocotp = (2U << 8U) | CCM_CCGR2_CG6_SHIFT, /*!< CCGR2, CG6 */ + kCLOCK_Xbar3 = (2U << 8U) | CCM_CCGR2_CG7_SHIFT, /*!< CCGR2, CG7 */ + kCLOCK_Ipmux1 = (2U << 8U) | CCM_CCGR2_CG8_SHIFT, /*!< CCGR2, CG8 */ + kCLOCK_Ipmux2 = (2U << 8U) | CCM_CCGR2_CG9_SHIFT, /*!< CCGR2, CG9 */ + kCLOCK_Ipmux3 = (2U << 8U) | CCM_CCGR2_CG10_SHIFT, /*!< CCGR2, CG10 */ + kCLOCK_Xbar1 = (2U << 8U) | CCM_CCGR2_CG11_SHIFT, /*!< CCGR2, CG11 */ + kCLOCK_Xbar2 = (2U << 8U) | CCM_CCGR2_CG12_SHIFT, /*!< CCGR2, CG12 */ + kCLOCK_Gpio3 = (2U << 8U) | CCM_CCGR2_CG13_SHIFT, /*!< CCGR2, CG13 */ + kCLOCK_Lcd = (2U << 8U) | CCM_CCGR2_CG14_SHIFT, /*!< CCGR2, CG14 */ + kCLOCK_Pxp = (2U << 8U) | CCM_CCGR2_CG15_SHIFT, /*!< CCGR2, CG15 */ + + /* CCM CCGR3 */ + kCLOCK_Flexio2 = (3U << 8U) | CCM_CCGR3_CG0_SHIFT, /*!< CCGR3, CG0 */ + kCLOCK_Lpuart5 = (3U << 8U) | CCM_CCGR3_CG1_SHIFT, /*!< CCGR3, CG1 */ + kCLOCK_Semc = (3U << 8U) | CCM_CCGR3_CG2_SHIFT, /*!< CCGR3, CG2 */ + kCLOCK_Lpuart6 = (3U << 8U) | CCM_CCGR3_CG3_SHIFT, /*!< CCGR3, CG3 */ + kCLOCK_Aoi1 = (3U << 8U) | CCM_CCGR3_CG4_SHIFT, /*!< CCGR3, CG4 */ + kCLOCK_LcdPixel = (3U << 8U) | CCM_CCGR3_CG5_SHIFT, /*!< CCGR3, CG5 */ + kCLOCK_Gpio4 = (3U << 8U) | CCM_CCGR3_CG6_SHIFT, /*!< CCGR3, CG6 */ + kCLOCK_Ewm0 = (3U << 8U) | CCM_CCGR3_CG7_SHIFT, /*!< CCGR3, CG7 */ + kCLOCK_Wdog1 = (3U << 8U) | CCM_CCGR3_CG8_SHIFT, /*!< CCGR3, CG8 */ + kCLOCK_FlexRam = (3U << 8U) | CCM_CCGR3_CG9_SHIFT, /*!< CCGR3, CG9 */ + kCLOCK_Acmp1 = (3U << 8U) | CCM_CCGR3_CG10_SHIFT, /*!< CCGR3, CG10 */ + kCLOCK_Acmp2 = (3U << 8U) | CCM_CCGR3_CG11_SHIFT, /*!< CCGR3, CG11 */ + kCLOCK_Acmp3 = (3U << 8U) | CCM_CCGR3_CG12_SHIFT, /*!< CCGR3, CG12 */ + kCLOCK_Acmp4 = (3U << 8U) | CCM_CCGR3_CG13_SHIFT, /*!< CCGR3, CG13 */ + kCLOCK_Ocram = (3U << 8U) | CCM_CCGR3_CG14_SHIFT, /*!< CCGR3, CG14 */ + kCLOCK_IomuxcSnvsGpr = (3U << 8U) | CCM_CCGR3_CG15_SHIFT, /*!< CCGR3, CG15 */ + + /* CCM CCGR4 */ + kCLOCK_Iomuxc = (4U << 8U) | CCM_CCGR4_CG1_SHIFT, /*!< CCGR4, CG1 */ + kCLOCK_IomuxcGpr = (4U << 8U) | CCM_CCGR4_CG2_SHIFT, /*!< CCGR4, CG2 */ + kCLOCK_Bee = (4U << 8U) | CCM_CCGR4_CG3_SHIFT, /*!< CCGR4, CG3 */ + kCLOCK_SimM7 = (4U << 8U) | CCM_CCGR4_CG4_SHIFT, /*!< CCGR4, CG4 */ + kCLOCK_Tsc = (4U << 8U) | CCM_CCGR4_CG5_SHIFT, /*!< CCGR4, CG5 */ + kCLOCK_SimM = (4U << 8U) | CCM_CCGR4_CG6_SHIFT, /*!< CCGR4, CG6 */ + kCLOCK_SimEms = (4U << 8U) | CCM_CCGR4_CG7_SHIFT, /*!< CCGR4, CG7 */ + kCLOCK_Pwm1 = (4U << 8U) | CCM_CCGR4_CG8_SHIFT, /*!< CCGR4, CG8 */ + kCLOCK_Pwm2 = (4U << 8U) | CCM_CCGR4_CG9_SHIFT, /*!< CCGR4, CG9 */ + kCLOCK_Pwm3 = (4U << 8U) | CCM_CCGR4_CG10_SHIFT, /*!< CCGR4, CG10 */ + kCLOCK_Pwm4 = (4U << 8U) | CCM_CCGR4_CG11_SHIFT, /*!< CCGR4, CG11 */ + kCLOCK_Enc1 = (4U << 8U) | CCM_CCGR4_CG12_SHIFT, /*!< CCGR4, CG12 */ + kCLOCK_Enc2 = (4U << 8U) | CCM_CCGR4_CG13_SHIFT, /*!< CCGR4, CG13 */ + kCLOCK_Enc3 = (4U << 8U) | CCM_CCGR4_CG14_SHIFT, /*!< CCGR4, CG14 */ + kCLOCK_Enc4 = (4U << 8U) | CCM_CCGR4_CG15_SHIFT, /*!< CCGR4, CG15 */ + + /* CCM CCGR5 */ + kCLOCK_Rom = (5U << 8U) | CCM_CCGR5_CG0_SHIFT, /*!< CCGR5, CG0 */ + kCLOCK_Flexio1 = (5U << 8U) | CCM_CCGR5_CG1_SHIFT, /*!< CCGR5, CG1 */ + kCLOCK_Wdog3 = (5U << 8U) | CCM_CCGR5_CG2_SHIFT, /*!< CCGR5, CG2 */ + kCLOCK_Dma = (5U << 8U) | CCM_CCGR5_CG3_SHIFT, /*!< CCGR5, CG3 */ + kCLOCK_Kpp = (5U << 8U) | CCM_CCGR5_CG4_SHIFT, /*!< CCGR5, CG4 */ + kCLOCK_Wdog2 = (5U << 8U) | CCM_CCGR5_CG5_SHIFT, /*!< CCGR5, CG5 */ + kCLOCK_Aips_tz4 = (5U << 8U) | CCM_CCGR5_CG6_SHIFT, /*!< CCGR5, CG6 */ + kCLOCK_Spdif = (5U << 8U) | CCM_CCGR5_CG7_SHIFT, /*!< CCGR5, CG7 */ + kCLOCK_SimMain = (5U << 8U) | CCM_CCGR5_CG8_SHIFT, /*!< CCGR5, CG8 */ + kCLOCK_Sai1 = (5U << 8U) | CCM_CCGR5_CG9_SHIFT, /*!< CCGR5, CG9 */ + kCLOCK_Sai2 = (5U << 8U) | CCM_CCGR5_CG10_SHIFT, /*!< CCGR5, CG10 */ + kCLOCK_Sai3 = (5U << 8U) | CCM_CCGR5_CG11_SHIFT, /*!< CCGR5, CG11 */ + kCLOCK_Lpuart1 = (5U << 8U) | CCM_CCGR5_CG12_SHIFT, /*!< CCGR5, CG12 */ + kCLOCK_Lpuart7 = (5U << 8U) | CCM_CCGR5_CG13_SHIFT, /*!< CCGR5, CG13 */ + kCLOCK_SnvsHp = (5U << 8U) | CCM_CCGR5_CG14_SHIFT, /*!< CCGR5, CG14 */ + kCLOCK_SnvsLp = (5U << 8U) | CCM_CCGR5_CG15_SHIFT, /*!< CCGR5, CG15 */ + + /* CCM CCGR6 */ + kCLOCK_UsbOh3 = (6U << 8U) | CCM_CCGR6_CG0_SHIFT, /*!< CCGR6, CG0 */ + kCLOCK_Usdhc1 = (6U << 8U) | CCM_CCGR6_CG1_SHIFT, /*!< CCGR6, CG1 */ + kCLOCK_Usdhc2 = (6U << 8U) | CCM_CCGR6_CG2_SHIFT, /*!< CCGR6, CG2 */ + kCLOCK_Dcdc = (6U << 8U) | CCM_CCGR6_CG3_SHIFT, /*!< CCGR6, CG3 */ + kCLOCK_Ipmux4 = (6U << 8U) | CCM_CCGR6_CG4_SHIFT, /*!< CCGR6, CG4 */ + kCLOCK_FlexSpi = (6U << 8U) | CCM_CCGR6_CG5_SHIFT, /*!< CCGR6, CG5 */ + kCLOCK_Trng = (6U << 8U) | CCM_CCGR6_CG6_SHIFT, /*!< CCGR6, CG6 */ + kCLOCK_Lpuart8 = (6U << 8U) | CCM_CCGR6_CG7_SHIFT, /*!< CCGR6, CG7 */ + kCLOCK_Timer4 = (6U << 8U) | CCM_CCGR6_CG8_SHIFT, /*!< CCGR6, CG8 */ + kCLOCK_Aips_tz3 = (6U << 8U) | CCM_CCGR6_CG9_SHIFT, /*!< CCGR6, CG9 */ + kCLOCK_SimPer = (6U << 8U) | CCM_CCGR6_CG10_SHIFT, /*!< CCGR6, CG10 */ + kCLOCK_Anadig = (6U << 8U) | CCM_CCGR6_CG11_SHIFT, /*!< CCGR6, CG11 */ + kCLOCK_Lpi2c4 = (6U << 8U) | CCM_CCGR6_CG12_SHIFT, /*!< CCGR6, CG12 */ + kCLOCK_Timer1 = (6U << 8U) | CCM_CCGR6_CG13_SHIFT, /*!< CCGR6, CG13 */ + kCLOCK_Timer2 = (6U << 8U) | CCM_CCGR6_CG14_SHIFT, /*!< CCGR6, CG14 */ + kCLOCK_Timer3 = (6U << 8U) | CCM_CCGR6_CG15_SHIFT, /*!< CCGR6, CG15 */ + +} clock_ip_name_t; + +/*! @brief OSC 24M sorce select */ +typedef enum _clock_osc +{ + kCLOCK_RcOsc = 0U, /*!< On chip OSC. */ + kCLOCK_XtalOsc = 1U, /*!< 24M Xtal OSC */ +} clock_osc_t; + +/*! @brief Clock gate value */ +typedef enum _clock_gate_value +{ + kCLOCK_ClockNotNeeded = 0U, /*!< Clock is off during all modes. */ + kCLOCK_ClockNeededRun = 1U, /*!< Clock is on in run mode, but off in WAIT and STOP modes */ + kCLOCK_ClockNeededRunWait = 3U, /*!< Clock is on during all modes, except STOP mode */ +} clock_gate_value_t; + +/*! @brief System clock mode */ +typedef enum _clock_mode_t +{ + kCLOCK_ModeRun = 0U, /*!< Remain in run mode. */ + kCLOCK_ModeWait = 1U, /*!< Transfer to wait mode. */ + kCLOCK_ModeStop = 2U, /*!< Transfer to stop mode. */ +} clock_mode_t; + +/*! + * @brief MUX control names for clock mux setting. + * + * These constants define the mux control names for clock mux setting.\n + * - 0:7: REG offset to CCM_BASE in bytes. + * - 8:15: Root clock setting bit field shift. + * - 16:31: Root clock setting bit field width. + */ +typedef enum _clock_mux +{ + kCLOCK_Pll3SwMux = CCM_TUPLE(CCSR_OFFSET, + CCM_CCSR_PLL3_SW_CLK_SEL_SHIFT, + CCM_CCSR_PLL3_SW_CLK_SEL_MASK, + CCM_NO_BUSY_WAIT), /*!< pll3_sw_clk mux name */ + + kCLOCK_PeriphMux = CCM_TUPLE(CBCDR_OFFSET, + CCM_CBCDR_PERIPH_CLK_SEL_SHIFT, + CCM_CBCDR_PERIPH_CLK_SEL_MASK, + CCM_CDHIPR_PERIPH_CLK_SEL_BUSY_SHIFT), /*!< periph mux name */ + kCLOCK_SemcAltMux = CCM_TUPLE(CBCDR_OFFSET, + CCM_CBCDR_SEMC_ALT_CLK_SEL_SHIFT, + CCM_CBCDR_SEMC_ALT_CLK_SEL_MASK, + CCM_NO_BUSY_WAIT), /*!< semc mux name */ + kCLOCK_SemcMux = CCM_TUPLE(CBCDR_OFFSET, + CCM_CBCDR_SEMC_CLK_SEL_SHIFT, + CCM_CBCDR_SEMC_CLK_SEL_MASK, + CCM_NO_BUSY_WAIT), /*!< semc mux name */ + + kCLOCK_PrePeriphMux = CCM_TUPLE(CBCMR_OFFSET, + CCM_CBCMR_PRE_PERIPH_CLK_SEL_SHIFT, + CCM_CBCMR_PRE_PERIPH_CLK_SEL_MASK, + CCM_NO_BUSY_WAIT), /*!< pre-periph mux name */ + kCLOCK_TraceMux = CCM_TUPLE(CBCMR_OFFSET, + CCM_CBCMR_TRACE_CLK_SEL_SHIFT, + CCM_CBCMR_TRACE_CLK_SEL_MASK, + CCM_NO_BUSY_WAIT), /*!< trace mux name */ + kCLOCK_PeriphClk2Mux = CCM_TUPLE(CBCMR_OFFSET, + CCM_CBCMR_PERIPH_CLK2_SEL_SHIFT, + CCM_CBCMR_PERIPH_CLK2_SEL_MASK, + CCM_NO_BUSY_WAIT), /*!< periph clock2 mux name */ + kCLOCK_LpspiMux = CCM_TUPLE(CBCMR_OFFSET, + CCM_CBCMR_LPSPI_CLK_SEL_SHIFT, + CCM_CBCMR_LPSPI_CLK_SEL_MASK, + CCM_NO_BUSY_WAIT), /*!< lpspi mux name */ + + kCLOCK_FlexspiMux = CCM_TUPLE(CSCMR1_OFFSET, + CCM_CSCMR1_FLEXSPI_CLK_SEL_SHIFT, + CCM_CSCMR1_FLEXSPI_CLK_SEL_MASK, + CCM_NO_BUSY_WAIT), /*!< flexspi mux name */ + kCLOCK_Usdhc2Mux = CCM_TUPLE(CSCMR1_OFFSET, + CCM_CSCMR1_USDHC2_CLK_SEL_SHIFT, + CCM_CSCMR1_USDHC2_CLK_SEL_MASK, + CCM_NO_BUSY_WAIT), /*!< usdhc2 mux name */ + kCLOCK_Usdhc1Mux = CCM_TUPLE(CSCMR1_OFFSET, + CCM_CSCMR1_USDHC1_CLK_SEL_SHIFT, + CCM_CSCMR1_USDHC1_CLK_SEL_MASK, + CCM_NO_BUSY_WAIT), /*!< usdhc1 mux name */ + kCLOCK_Sai3Mux = CCM_TUPLE(CSCMR1_OFFSET, + CCM_CSCMR1_SAI3_CLK_SEL_SHIFT, + CCM_CSCMR1_SAI3_CLK_SEL_MASK, + CCM_NO_BUSY_WAIT), /*!< sai3 mux name */ + kCLOCK_Sai2Mux = CCM_TUPLE(CSCMR1_OFFSET, + CCM_CSCMR1_SAI2_CLK_SEL_SHIFT, + CCM_CSCMR1_SAI2_CLK_SEL_MASK, + CCM_NO_BUSY_WAIT), /*!< sai2 mux name */ + kCLOCK_Sai1Mux = CCM_TUPLE(CSCMR1_OFFSET, + CCM_CSCMR1_SAI1_CLK_SEL_SHIFT, + CCM_CSCMR1_SAI1_CLK_SEL_MASK, + CCM_NO_BUSY_WAIT), /*!< sai1 mux name */ + kCLOCK_PerclkMux = CCM_TUPLE(CSCMR1_OFFSET, + CCM_CSCMR1_PERCLK_CLK_SEL_SHIFT, + CCM_CSCMR1_PERCLK_CLK_SEL_MASK, + CCM_NO_BUSY_WAIT), /*!< perclk mux name */ + + kCLOCK_Flexio2Mux = CCM_TUPLE(CSCMR2_OFFSET, + CCM_CSCMR2_FLEXIO2_CLK_SEL_SHIFT, + CCM_CSCMR2_FLEXIO2_CLK_SEL_MASK, + CCM_NO_BUSY_WAIT), /*!< flexio2 mux name */ + kCLOCK_CanMux = CCM_TUPLE(CSCMR2_OFFSET, + CCM_CSCMR2_CAN_CLK_SEL_SHIFT, + CCM_CSCMR2_CAN_CLK_SEL_MASK, + CCM_NO_BUSY_WAIT), /*!< can mux name */ + + kCLOCK_UartMux = CCM_TUPLE(CSCDR1_OFFSET, + CCM_CSCDR1_UART_CLK_SEL_SHIFT, + CCM_CSCDR1_UART_CLK_SEL_MASK, + CCM_NO_BUSY_WAIT), /*!< uart mux name */ + + kCLOCK_SpdifMux = CCM_TUPLE(CDCDR_OFFSET, + CCM_CDCDR_SPDIF0_CLK_SEL_SHIFT, + CCM_CDCDR_SPDIF0_CLK_SEL_MASK, + CCM_NO_BUSY_WAIT), /*!< spdif mux name */ + kCLOCK_Flexio1Mux = CCM_TUPLE(CDCDR_OFFSET, + CCM_CDCDR_FLEXIO1_CLK_SEL_SHIFT, + CCM_CDCDR_FLEXIO1_CLK_SEL_MASK, + CCM_NO_BUSY_WAIT), /*!< flexio1 mux name */ + + kCLOCK_Lpi2cMux = CCM_TUPLE(CSCDR2_OFFSET, + CCM_CSCDR2_LPI2C_CLK_SEL_SHIFT, + CCM_CSCDR2_LPI2C_CLK_SEL_MASK, + CCM_NO_BUSY_WAIT), /*!< lpi2c mux name */ + kCLOCK_LcdifPreMux = CCM_TUPLE(CSCDR2_OFFSET, + CCM_CSCDR2_LCDIF_PRE_CLK_SEL_SHIFT, + CCM_CSCDR2_LCDIF_PRE_CLK_SEL_MASK, + CCM_NO_BUSY_WAIT), /*!< lcdif pre mux name */ + + kCLOCK_CsiMux = CCM_TUPLE(CSCDR3_OFFSET, + CCM_CSCDR3_CSI_CLK_SEL_SHIFT, + CCM_CSCDR3_CSI_CLK_SEL_MASK, + CCM_NO_BUSY_WAIT), /*!< csi mux name */ +} clock_mux_t; + +/*! + * @brief DIV control names for clock div setting. + * + * These constants define div control names for clock div setting.\n + * - 0:7: REG offset to CCM_BASE in bytes. + * - 8:15: Root clock setting bit field shift. + * - 16:31: Root clock setting bit field width. + */ +typedef enum _clock_div +{ + kCLOCK_ArmDiv = CCM_TUPLE(CACRR_OFFSET, + CCM_CACRR_ARM_PODF_SHIFT, + CCM_CACRR_ARM_PODF_MASK, + CCM_CDHIPR_ARM_PODF_BUSY_SHIFT), /*!< core div name */ + + kCLOCK_PeriphClk2Div = CCM_TUPLE(CBCDR_OFFSET, + CCM_CBCDR_PERIPH_CLK2_PODF_SHIFT, + CCM_CBCDR_PERIPH_CLK2_PODF_MASK, + CCM_NO_BUSY_WAIT), /*!< periph clock2 div name */ + kCLOCK_SemcDiv = CCM_TUPLE(CBCDR_OFFSET, + CCM_CBCDR_SEMC_PODF_SHIFT, + CCM_CBCDR_SEMC_PODF_MASK, + CCM_CDHIPR_SEMC_PODF_BUSY_SHIFT), /*!< semc div name */ + kCLOCK_AhbDiv = CCM_TUPLE(CBCDR_OFFSET, + CCM_CBCDR_AHB_PODF_SHIFT, + CCM_CBCDR_AHB_PODF_MASK, + CCM_CDHIPR_AHB_PODF_BUSY_SHIFT), /*!< ahb div name */ + kCLOCK_IpgDiv = CCM_TUPLE( + CBCDR_OFFSET, CCM_CBCDR_IPG_PODF_SHIFT, CCM_CBCDR_IPG_PODF_MASK, CCM_NO_BUSY_WAIT), /*!< ipg div name */ + + kCLOCK_LpspiDiv = CCM_TUPLE( + CBCMR_OFFSET, CCM_CBCMR_LPSPI_PODF_SHIFT, CCM_CBCMR_LPSPI_PODF_MASK, CCM_NO_BUSY_WAIT), /*!< lpspi div name */ + kCLOCK_LcdifDiv = CCM_TUPLE( + CBCMR_OFFSET, CCM_CBCMR_LCDIF_PODF_SHIFT, CCM_CBCMR_LCDIF_PODF_MASK, CCM_NO_BUSY_WAIT), /*!< lcdif div name */ + + kCLOCK_FlexspiDiv = CCM_TUPLE(CSCMR1_OFFSET, + CCM_CSCMR1_FLEXSPI_PODF_SHIFT, + CCM_CSCMR1_FLEXSPI_PODF_MASK, + CCM_NO_BUSY_WAIT), /*!< flexspi div name */ + kCLOCK_PerclkDiv = CCM_TUPLE(CSCMR1_OFFSET, + CCM_CSCMR1_PERCLK_PODF_SHIFT, + CCM_CSCMR1_PERCLK_PODF_MASK, + CCM_NO_BUSY_WAIT), /*!< perclk div name */ + + kCLOCK_CanDiv = CCM_TUPLE(CSCMR2_OFFSET, + CCM_CSCMR2_CAN_CLK_PODF_SHIFT, + CCM_CSCMR2_CAN_CLK_PODF_MASK, + CCM_NO_BUSY_WAIT), /*!< can div name */ + + kCLOCK_TraceDiv = CCM_TUPLE(CSCDR1_OFFSET, + CCM_CSCDR1_TRACE_PODF_SHIFT, + CCM_CSCDR1_TRACE_PODF_MASK, + CCM_NO_BUSY_WAIT), /*!< trace div name */ + kCLOCK_Usdhc2Div = CCM_TUPLE(CSCDR1_OFFSET, + CCM_CSCDR1_USDHC2_PODF_SHIFT, + CCM_CSCDR1_USDHC2_PODF_MASK, + CCM_NO_BUSY_WAIT), /*!< usdhc2 div name */ + kCLOCK_Usdhc1Div = CCM_TUPLE(CSCDR1_OFFSET, + CCM_CSCDR1_USDHC1_PODF_SHIFT, + CCM_CSCDR1_USDHC1_PODF_MASK, + CCM_NO_BUSY_WAIT), /*!< usdhc1 div name */ + kCLOCK_UartDiv = CCM_TUPLE(CSCDR1_OFFSET, + CCM_CSCDR1_UART_CLK_PODF_SHIFT, + CCM_CSCDR1_UART_CLK_PODF_MASK, + CCM_NO_BUSY_WAIT), /*!< uart div name */ + + kCLOCK_Flexio2Div = CCM_TUPLE(CS1CDR_OFFSET, + CCM_CS1CDR_FLEXIO2_CLK_PODF_SHIFT, + CCM_CS1CDR_FLEXIO2_CLK_PODF_MASK, + CCM_NO_BUSY_WAIT), /*!< flexio2 pre div name */ + kCLOCK_Sai3PreDiv = CCM_TUPLE(CS1CDR_OFFSET, + CCM_CS1CDR_SAI3_CLK_PRED_SHIFT, + CCM_CS1CDR_SAI3_CLK_PRED_MASK, + CCM_NO_BUSY_WAIT), /*!< sai3 pre div name */ + kCLOCK_Sai3Div = CCM_TUPLE(CS1CDR_OFFSET, + CCM_CS1CDR_SAI3_CLK_PODF_SHIFT, + CCM_CS1CDR_SAI3_CLK_PODF_MASK, + CCM_NO_BUSY_WAIT), /*!< sai3 div name */ + kCLOCK_Flexio2PreDiv = CCM_TUPLE(CS1CDR_OFFSET, + CCM_CS1CDR_FLEXIO2_CLK_PRED_SHIFT, + CCM_CS1CDR_FLEXIO2_CLK_PRED_MASK, + CCM_NO_BUSY_WAIT), /*!< sai3 pre div name */ + kCLOCK_Sai1PreDiv = CCM_TUPLE(CS1CDR_OFFSET, + CCM_CS1CDR_SAI1_CLK_PRED_SHIFT, + CCM_CS1CDR_SAI1_CLK_PRED_MASK, + CCM_NO_BUSY_WAIT), /*!< sai1 pre div name */ + kCLOCK_Sai1Div = CCM_TUPLE(CS1CDR_OFFSET, + CCM_CS1CDR_SAI1_CLK_PODF_SHIFT, + CCM_CS1CDR_SAI1_CLK_PODF_MASK, + CCM_NO_BUSY_WAIT), /*!< sai1 div name */ + + kCLOCK_Sai2PreDiv = CCM_TUPLE(CS2CDR_OFFSET, + CCM_CS2CDR_SAI2_CLK_PRED_SHIFT, + CCM_CS2CDR_SAI2_CLK_PRED_MASK, + CCM_NO_BUSY_WAIT), /*!< sai2 pre div name */ + kCLOCK_Sai2Div = CCM_TUPLE(CS2CDR_OFFSET, + CCM_CS2CDR_SAI2_CLK_PODF_SHIFT, + CCM_CS2CDR_SAI2_CLK_PODF_MASK, + CCM_NO_BUSY_WAIT), /*!< sai2 div name */ + + kCLOCK_Spdif0PreDiv = CCM_TUPLE(CDCDR_OFFSET, + CCM_CDCDR_SPDIF0_CLK_PRED_SHIFT, + CCM_CDCDR_SPDIF0_CLK_PRED_MASK, + CCM_NO_BUSY_WAIT), /*!< spdif pre div name */ + kCLOCK_Spdif0Div = CCM_TUPLE(CDCDR_OFFSET, + CCM_CDCDR_SPDIF0_CLK_PODF_SHIFT, + CCM_CDCDR_SPDIF0_CLK_PODF_MASK, + CCM_NO_BUSY_WAIT), /*!< spdif div name */ + kCLOCK_Flexio1PreDiv = CCM_TUPLE(CDCDR_OFFSET, + CCM_CDCDR_FLEXIO1_CLK_PRED_SHIFT, + CCM_CDCDR_FLEXIO1_CLK_PRED_MASK, + CCM_NO_BUSY_WAIT), /*!< flexio1 pre div name */ + kCLOCK_Flexio1Div = CCM_TUPLE(CDCDR_OFFSET, + CCM_CDCDR_FLEXIO1_CLK_PODF_SHIFT, + CCM_CDCDR_FLEXIO1_CLK_PODF_MASK, + CCM_NO_BUSY_WAIT), /*!< flexio1 div name */ + + kCLOCK_Lpi2cDiv = CCM_TUPLE(CSCDR2_OFFSET, + CCM_CSCDR2_LPI2C_CLK_PODF_SHIFT, + CCM_CSCDR2_LPI2C_CLK_PODF_MASK, + CCM_NO_BUSY_WAIT), /*!< lpi2c div name */ + kCLOCK_LcdifPreDiv = CCM_TUPLE(CSCDR2_OFFSET, + CCM_CSCDR2_LCDIF_PRED_SHIFT, + CCM_CSCDR2_LCDIF_PRED_MASK, + CCM_NO_BUSY_WAIT), /*!< lcdif pre div name */ + + kCLOCK_CsiDiv = CCM_TUPLE( + CSCDR3_OFFSET, CCM_CSCDR3_CSI_PODF_SHIFT, CCM_CSCDR3_CSI_PODF_MASK, CCM_NO_BUSY_WAIT), /*!< csi div name */ +} clock_div_t; + +/*! @brief USB clock source definition. */ +typedef enum _clock_usb_src +{ + kCLOCK_Usb480M = 0, /*!< Use 480M. */ + kCLOCK_UsbSrcUnused = (int)0xFFFFFFFFU, /*!< Used when the function does not + care the clock source. */ +} clock_usb_src_t; + +/*! @brief Source of the USB HS PHY. */ +typedef enum _clock_usb_phy_src +{ + kCLOCK_Usbphy480M = 0, /*!< Use 480M. */ +} clock_usb_phy_src_t; + +/*!@brief PLL clock source, bypass cloco source also */ +enum _clock_pll_clk_src +{ + kCLOCK_PllClkSrc24M = 0U, /*!< Pll clock source 24M */ + kCLOCK_PllSrcClkPN = 1U, /*!< Pll clock source CLK1_P and CLK1_N */ +}; + +/*! @brief PLL configuration for ARM */ +typedef struct _clock_arm_pll_config +{ + uint32_t loopDivider; /*!< PLL loop divider. Valid range for divider value: 54-108. Fout=Fin*loopDivider/2. */ + uint8_t src; /*!< Pll clock source, reference _clock_pll_clk_src */ +} clock_arm_pll_config_t; + +/*! @brief PLL configuration for USB */ +typedef struct _clock_usb_pll_config +{ + uint8_t loopDivider; /*!< PLL loop divider. + 0 - Fout=Fref*20; + 1 - Fout=Fref*22 */ + uint8_t src; /*!< Pll clock source, reference _clock_pll_clk_src */ + +} clock_usb_pll_config_t; + +/*! @brief PLL configuration for System */ +typedef struct _clock_sys_pll_config +{ + uint8_t loopDivider; /*!< PLL loop divider. Intended to be 1 (528M). + 0 - Fout=Fref*20; + 1 - Fout=Fref*22 */ + uint32_t numerator; /*!< 30 bit numerator of fractional loop divider.*/ + uint32_t denominator; /*!< 30 bit denominator of fractional loop divider */ + uint8_t src; /*!< Pll clock source, reference _clock_pll_clk_src */ + uint16_t ss_stop; /*!< Stop value to get frequency change. */ + uint8_t ss_enable; /*!< Enable spread spectrum modulation */ + uint16_t ss_step; /*!< Step value to get frequency change step. */ + +} clock_sys_pll_config_t; + +/*! @brief PLL configuration for AUDIO and VIDEO */ +typedef struct _clock_audio_pll_config +{ + uint8_t loopDivider; /*!< PLL loop divider. Valid range for DIV_SELECT divider value: 27~54. */ + uint8_t postDivider; /*!< Divider after the PLL, should only be 1, 2, 4, 8, 16. */ + uint32_t numerator; /*!< 30 bit numerator of fractional loop divider.*/ + uint32_t denominator; /*!< 30 bit denominator of fractional loop divider */ + uint8_t src; /*!< Pll clock source, reference _clock_pll_clk_src */ +} clock_audio_pll_config_t; + +/*! @brief PLL configuration for AUDIO and VIDEO */ +typedef struct _clock_video_pll_config +{ + uint8_t loopDivider; /*!< PLL loop divider. Valid range for DIV_SELECT divider value: 27~54. */ + uint8_t postDivider; /*!< Divider after the PLL, should only be 1, 2, 4, 8, 16. */ + uint32_t numerator; /*!< 30 bit numerator of fractional loop divider.*/ + uint32_t denominator; /*!< 30 bit denominator of fractional loop divider */ + uint8_t src; /*!< Pll clock source, reference _clock_pll_clk_src */ + +} clock_video_pll_config_t; + +/*! @brief PLL configuration for ENET */ +typedef struct _clock_enet_pll_config +{ + bool enableClkOutput; /*!< Power on and enable PLL clock output for ENET0 (ref_enetpll0). */ + + bool enableClkOutput25M; /*!< Power on and enable PLL clock output for ENET1 (ref_enetpll1). */ + uint8_t loopDivider; /*!< Controls the frequency of the ENET0 reference clock. + b00 25MHz + b01 50MHz + b10 100MHz (not 50% duty cycle) + b11 125MHz */ + uint8_t src; /*!< Pll clock source, reference _clock_pll_clk_src */ + +} clock_enet_pll_config_t; + +/*! @brief PLL name */ +typedef enum _clock_pll +{ + kCLOCK_PllArm = CCM_ANALOG_TUPLE(PLL_ARM_OFFSET, CCM_ANALOG_PLL_ARM_ENABLE_SHIFT), /*!< PLL ARM */ + kCLOCK_PllSys = CCM_ANALOG_TUPLE(PLL_SYS_OFFSET, CCM_ANALOG_PLL_SYS_ENABLE_SHIFT), /*!< PLL SYS */ + kCLOCK_PllUsb1 = CCM_ANALOG_TUPLE(PLL_USB1_OFFSET, CCM_ANALOG_PLL_USB1_ENABLE_SHIFT), /*!< PLL USB1 */ + kCLOCK_PllAudio = CCM_ANALOG_TUPLE(PLL_AUDIO_OFFSET, CCM_ANALOG_PLL_AUDIO_ENABLE_SHIFT), /*!< PLL Audio */ + kCLOCK_PllVideo = CCM_ANALOG_TUPLE(PLL_VIDEO_OFFSET, CCM_ANALOG_PLL_VIDEO_ENABLE_SHIFT), /*!< PLL Video */ + + kCLOCK_PllEnet = CCM_ANALOG_TUPLE(PLL_ENET_OFFSET, CCM_ANALOG_PLL_ENET_ENABLE_SHIFT), /*!< PLL Enet0 */ + + kCLOCK_PllEnet25M = CCM_ANALOG_TUPLE(PLL_ENET_OFFSET, CCM_ANALOG_PLL_ENET_ENET_25M_REF_EN_SHIFT), /*!< PLL Enet1 */ + + kCLOCK_PllUsb2 = CCM_ANALOG_TUPLE(PLL_USB2_OFFSET, CCM_ANALOG_PLL_USB2_ENABLE_SHIFT), /*!< PLL USB2 */ + +} clock_pll_t; + +/*! @brief PLL PFD name */ +typedef enum _clock_pfd +{ + kCLOCK_Pfd0 = 0U, /*!< PLL PFD0 */ + kCLOCK_Pfd1 = 1U, /*!< PLL PFD1 */ + kCLOCK_Pfd2 = 2U, /*!< PLL PFD2 */ + kCLOCK_Pfd3 = 3U, /*!< PLL PFD3 */ +} clock_pfd_t; + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus */ + +/*! + * @brief Set CCM MUX node to certain value. + * + * @param mux Which mux node to set, see \ref clock_mux_t. + * @param value Clock mux value to set, different mux has different value range. + */ +static inline void CLOCK_SetMux(clock_mux_t mux, uint32_t value) +{ + uint32_t busyShift; + + busyShift = CCM_TUPLE_BUSY_SHIFT(mux); + CCM_TUPLE_REG(CCM, mux) = (CCM_TUPLE_REG(CCM, mux) & (~CCM_TUPLE_MASK(mux))) | + (((uint32_t)((value) << CCM_TUPLE_SHIFT(mux))) & CCM_TUPLE_MASK(mux)); + + assert(busyShift <= CCM_NO_BUSY_WAIT); + + /* Clock switch need Handshake? */ + if (CCM_NO_BUSY_WAIT != busyShift) + { + /* Wait until CCM internal handshake finish. */ + while (CCM->CDHIPR & (1U << busyShift)) + { + } + } +} + +/*! + * @brief Get CCM MUX value. + * + * @param mux Which mux node to get, see \ref clock_mux_t. + * @return Clock mux value. + */ +static inline uint32_t CLOCK_GetMux(clock_mux_t mux) +{ + return (CCM_TUPLE_REG(CCM, mux) & CCM_TUPLE_MASK(mux)) >> CCM_TUPLE_SHIFT(mux); +} + +/*! + * @brief Set CCM DIV node to certain value. + * + * @param divider Which div node to set, see \ref clock_div_t. + * @param value Clock div value to set, different divider has different value range. + */ +static inline void CLOCK_SetDiv(clock_div_t divider, uint32_t value) +{ + uint32_t busyShift; + + busyShift = CCM_TUPLE_BUSY_SHIFT(divider); + CCM_TUPLE_REG(CCM, divider) = (CCM_TUPLE_REG(CCM, divider) & (~CCM_TUPLE_MASK(divider))) | + (((uint32_t)((value) << CCM_TUPLE_SHIFT(divider))) & CCM_TUPLE_MASK(divider)); + + assert(busyShift <= CCM_NO_BUSY_WAIT); + + /* Clock switch need Handshake? */ + if (CCM_NO_BUSY_WAIT != busyShift) + { + /* Wait until CCM internal handshake finish. */ + while (CCM->CDHIPR & (1U << busyShift)) + { + } + } +} + +/*! + * @brief Get CCM DIV node value. + * + * @param divider Which div node to get, see \ref clock_div_t. + */ +static inline uint32_t CLOCK_GetDiv(clock_div_t divider) +{ + return ((CCM_TUPLE_REG(CCM, divider) & CCM_TUPLE_MASK(divider)) >> CCM_TUPLE_SHIFT(divider)); +} + +/*! + * @brief Control the clock gate for specific IP. + * + * @param name Which clock to enable, see \ref clock_ip_name_t. + * @param value Clock gate value to set, see \ref clock_gate_value_t. + */ +static inline void CLOCK_ControlGate(clock_ip_name_t name, clock_gate_value_t value) +{ + uint32_t index = ((uint32_t)name) >> 8U; + uint32_t shift = ((uint32_t)name) & 0x1FU; + volatile uint32_t *reg; + + assert(index <= 6); + + reg = ((volatile uint32_t *)&CCM->CCGR0) + index; + *reg = ((*reg) & ~(3U << shift)) | (((uint32_t)value) << shift); +} + +/*! + * @brief Enable the clock for specific IP. + * + * @param name Which clock to enable, see \ref clock_ip_name_t. + */ +static inline void CLOCK_EnableClock(clock_ip_name_t name) +{ + CLOCK_ControlGate(name, kCLOCK_ClockNeededRunWait); +} + +/*! + * @brief Disable the clock for specific IP. + * + * @param name Which clock to disable, see \ref clock_ip_name_t. + */ +static inline void CLOCK_DisableClock(clock_ip_name_t name) +{ + CLOCK_ControlGate(name, kCLOCK_ClockNotNeeded); +} + +/*! + * @brief Setting the low power mode that system will enter on next assertion of dsm_request signal. + * + * @param mode Which mode to enter, see \ref clock_mode_t. + */ +static inline void CLOCK_SetMode(clock_mode_t mode) +{ + CCM->CLPCR = (CCM->CLPCR & ~CCM_CLPCR_LPM_MASK) | CCM_CLPCR_LPM((uint32_t)mode); +} + +/*! + * @brief Gets the OSC clock frequency. + * + * This function will return the external XTAL OSC frequency if it is selected as the source of OSC, + * otherwise internal 24MHz RC OSC frequency will be returned. + * + * @param osc OSC type to get frequency. + * + * @return Clock frequency; If the clock is invalid, returns 0. + */ +static inline uint32_t CLOCK_GetOscFreq(void) +{ + return (XTALOSC24M->LOWPWR_CTRL & XTALOSC24M_LOWPWR_CTRL_OSC_SEL_MASK) ? 24000000UL : g_xtalFreq; +} + +/*! + * @brief Gets the AHB clock frequency. + * + * @return The AHB clock frequency value in hertz. + */ +uint32_t CLOCK_GetAhbFreq(void); + +/*! + * @brief Gets the SEMC clock frequency. + * + * @return The SEMC clock frequency value in hertz. + */ +uint32_t CLOCK_GetSemcFreq(void); + +/*! + * @brief Gets the IPG clock frequency. + * + * @return The IPG clock frequency value in hertz. + */ +uint32_t CLOCK_GetIpgFreq(void); + +/*! + * @brief Gets the PER clock frequency. + * + * @return The PER clock frequency value in hertz. + */ +uint32_t CLOCK_GetPerClkFreq(void); + +/*! + * @brief Gets the clock frequency for a specific clock name. + * + * This function checks the current clock configurations and then calculates + * the clock frequency for a specific clock name defined in clock_name_t. + * + * @param clockName Clock names defined in clock_name_t + * @return Clock frequency value in hertz + */ +uint32_t CLOCK_GetFreq(clock_name_t name); + +/*! + * @brief Get the CCM CPU/core/system frequency. + * + * @return Clock frequency; If the clock is invalid, returns 0. + */ +static inline uint32_t CLOCK_GetCpuClkFreq(void) +{ + return CLOCK_GetFreq(kCLOCK_CpuClk); +} + +/*! + * @name OSC operations + * @{ + */ + +/*! + * @brief Initialize the external 24MHz clock. + * + * This function supports two modes: + * 1. Use external crystal oscillator. + * 2. Bypass the external crystal oscillator, using input source clock directly. + * + * After this function, please call @ref CLOCK_SetXtal0Freq to inform clock driver + * the external clock frequency. + * + * @param bypassXtalOsc Pass in true to bypass the external crystal oscillator. + * @note This device does not support bypass external crystal oscillator, so + * the input parameter should always be false. + */ +void CLOCK_InitExternalClk(bool bypassXtalOsc); + +/*! + * @brief Deinitialize the external 24MHz clock. + * + * This function disables the external 24MHz clock. + * + * After this function, please call @ref CLOCK_SetXtal0Freq to set external clock + * frequency to 0. + */ +void CLOCK_DeinitExternalClk(void); + +/*! + * @brief Switch the OSC. + * + * This function switches the OSC source for SoC. + * + * @param osc OSC source to switch to. + */ +void CLOCK_SwitchOsc(clock_osc_t osc); + +/*! + * @brief Gets the RTC clock frequency. + * + * @return Clock frequency; If the clock is invalid, returns 0. + */ +static inline uint32_t CLOCK_GetRtcFreq(void) +{ + return 32768U; +} + +/*! + * @brief Set the XTAL (24M OSC) frequency based on board setting. + * + * @param freq The XTAL input clock frequency in Hz. + */ +static inline void CLOCK_SetXtalFreq(uint32_t freq) +{ + g_xtalFreq = freq; +} + +/*! + * @brief Set the RTC XTAL (32K OSC) frequency based on board setting. + * + * @param freq The RTC XTAL input clock frequency in Hz. + */ +static inline void CLOCK_SetRtcXtalFreq(uint32_t freq) +{ + g_rtcXtalFreq = freq; +} + +/*! + * @brief Initialize the RC oscillator 24MHz clock. + */ +void CLOCK_InitRcOsc24M(void); + +/*! + * @brief Power down the RCOSC 24M clock. + */ +void CLOCK_DeinitRcOsc24M(void); +/* @} */ + +/*! @brief Enable USB HS clock. + * + * This function only enables the access to USB HS prepheral, upper layer + * should first call the @ref CLOCK_EnableUsbhs0PhyPllClock to enable the PHY + * clock to use USB HS. + * + * @param src USB HS does not care about the clock source, here must be @ref kCLOCK_UsbSrcUnused. + * @param freq USB HS does not care about the clock source, so this parameter is ignored. + * @retval true The clock is set successfully. + * @retval false The clock source is invalid to get proper USB HS clock. + */ +bool CLOCK_EnableUsbhs0Clock(clock_usb_src_t src, uint32_t freq); + +/*! @brief Enable USB HS clock. + * + * This function only enables the access to USB HS prepheral, upper layer + * should first call the @ref CLOCK_EnableUsbhs0PhyPllClock to enable the PHY + * clock to use USB HS. + * + * @param src USB HS does not care about the clock source, here must be @ref kCLOCK_UsbSrcUnused. + * @param freq USB HS does not care about the clock source, so this parameter is ignored. + * @retval true The clock is set successfully. + * @retval false The clock source is invalid to get proper USB HS clock. + */ +bool CLOCK_EnableUsbhs1Clock(clock_usb_src_t src, uint32_t freq); + +/*! @brief Disable USB HS PHY PLL clock. + * + * This function disables USB HS PHY PLL clock. + */ +void CLOCK_DisableUsbhs1PhyPllClock(void); + +/* @} */ + +/*! + * @name PLL/PFD operations + * @{ + */ +/*! + * @brief PLL bypass setting + * + * @param base CCM_ANALOG base pointer. + * @param pll PLL control name (see @ref ccm_analog_pll_control_t enumeration) + * @param bypass Bypass the PLL. + * - true: Bypass the PLL. + * - false:Not bypass the PLL. + */ +static inline void CLOCK_SetPllBypass(CCM_ANALOG_Type *base, clock_pll_t pll, bool bypass) +{ + if (bypass) + { + CCM_ANALOG_TUPLE_REG_OFF(base, pll, 4U) = 1U << CCM_ANALOG_PLL_BYPASS_SHIFT; + } + else + { + CCM_ANALOG_TUPLE_REG_OFF(base, pll, 8U) = 1U << CCM_ANALOG_PLL_BYPASS_SHIFT; + } +} + +/*! + * @brief Check if PLL is bypassed + * + * @param base CCM_ANALOG base pointer. + * @param pll PLL control name (see @ref ccm_analog_pll_control_t enumeration) + * @return PLL bypass status. + * - true: The PLL is bypassed. + * - false: The PLL is not bypassed. + */ +static inline bool CLOCK_IsPllBypassed(CCM_ANALOG_Type *base, clock_pll_t pll) +{ + return (bool)(CCM_ANALOG_TUPLE_REG(base, pll) & (1U << CCM_ANALOG_PLL_BYPASS_SHIFT)); +} + +/*! + * @brief Check if PLL is enabled + * + * @param base CCM_ANALOG base pointer. + * @param pll PLL control name (see @ref ccm_analog_pll_control_t enumeration) + * @return PLL bypass status. + * - true: The PLL is enabled. + * - false: The PLL is not enabled. + */ +static inline bool CLOCK_IsPllEnabled(CCM_ANALOG_Type *base, clock_pll_t pll) +{ + return (bool)(CCM_ANALOG_TUPLE_REG(base, pll) & (1U << CCM_ANALOG_TUPLE_SHIFT(pll))); +} + +/*! + * @brief PLL bypass clock source setting. + * Note: change the bypass clock source also change the pll reference clock source. + * + * @param base CCM_ANALOG base pointer. + * @param pll PLL control name (see @ref ccm_analog_pll_control_t enumeration) + * @param src Bypass clock source, reference _clock_pll_bypass_clk_src. + */ +static inline void CLOCK_SetPllBypassRefClkSrc(CCM_ANALOG_Type *base, clock_pll_t pll, uint32_t src) +{ + CCM_ANALOG_TUPLE_REG(base, pll) |= (CCM_ANALOG_TUPLE_REG(base, pll) & (~CCM_ANALOG_PLL_BYPASS_CLK_SRC_MASK)) | src; +} + +/*! + * @brief Get PLL bypass clock value, it is PLL reference clock actually. + * If CLOCK1_P,CLOCK1_N is choose as the pll bypass clock source, please implement the CLKPN_FREQ define, otherwise 0 + * will be returned. + * @param base CCM_ANALOG base pointer. + * @param pll PLL control name (see @ref ccm_analog_pll_control_t enumeration) + * @retval bypass reference clock frequency value. + */ +static inline uint32_t CLOCK_GetPllBypassRefClk(CCM_ANALOG_Type *base, clock_pll_t pll) +{ + return (((CCM_ANALOG_TUPLE_REG(base, pll) & CCM_ANALOG_PLL_BYPASS_CLK_SRC_MASK) >> + CCM_ANALOG_PLL_BYPASS_CLK_SRC_SHIFT) == kCLOCK_PllClkSrc24M) ? + CLOCK_GetOscFreq() : + CLKPN_FREQ; +} + +/*! + * @brief Initialize the ARM PLL. + * + * This function initialize the ARM PLL with specific settings + * + * @param config configuration to set to PLL. + */ +void CLOCK_InitArmPll(const clock_arm_pll_config_t *config); + +/*! + * @brief De-initialize the ARM PLL. + */ +void CLOCK_DeinitArmPll(void); + +/*! + * @brief Initialize the System PLL. + * + * This function initializes the System PLL with specific settings + * + * @param config Configuration to set to PLL. + */ +void CLOCK_InitSysPll(const clock_sys_pll_config_t *config); + +/*! + * @brief De-initialize the System PLL. + */ +void CLOCK_DeinitSysPll(void); + +/*! + * @brief Initialize the USB1 PLL. + * + * This function initializes the USB1 PLL with specific settings + * + * @param config Configuration to set to PLL. + */ +void CLOCK_InitUsb1Pll(const clock_usb_pll_config_t *config); + +/*! + * @brief Deinitialize the USB1 PLL. + */ +void CLOCK_DeinitUsb1Pll(void); + +/*! + * @brief Initialize the USB2 PLL. + * + * This function initializes the USB2 PLL with specific settings + * + * @param config Configuration to set to PLL. + */ +void CLOCK_InitUsb2Pll(const clock_usb_pll_config_t *config); + +/*! + * @brief Deinitialize the USB2 PLL. + */ +void CLOCK_DeinitUsb2Pll(void); + +/*! + * @brief Initializes the Audio PLL. + * + * This function initializes the Audio PLL with specific settings + * + * @param config Configuration to set to PLL. + */ +void CLOCK_InitAudioPll(const clock_audio_pll_config_t *config); + +/*! + * @brief De-initialize the Audio PLL. + */ +void CLOCK_DeinitAudioPll(void); + +/*! + * @brief Initialize the video PLL. + * + * This function configures the Video PLL with specific settings + * + * @param config configuration to set to PLL. + */ +void CLOCK_InitVideoPll(const clock_video_pll_config_t *config); + +/*! + * @brief De-initialize the Video PLL. + */ +void CLOCK_DeinitVideoPll(void); +/*! + * @brief Initialize the ENET PLL. + * + * This function initializes the ENET PLL with specific settings. + * + * @param config Configuration to set to PLL. + */ +void CLOCK_InitEnetPll(const clock_enet_pll_config_t *config); + +/*! + * @brief Deinitialize the ENET PLL. + * + * This function disables the ENET PLL. + */ +void CLOCK_DeinitEnetPll(void); + +/*! + * @brief Get current PLL output frequency. + * + * This function get current output frequency of specific PLL + * + * @param pll pll name to get frequency. + * @return The PLL output frequency in hertz. + */ +uint32_t CLOCK_GetPllFreq(clock_pll_t pll); + +/*! + * @brief Initialize the System PLL PFD. + * + * This function initializes the System PLL PFD. During new value setting, + * the clock output is disabled to prevent glitch. + * + * @param pfd Which PFD clock to enable. + * @param pfdFrac The PFD FRAC value. + * @note It is recommended that PFD settings are kept between 12-35. + */ +void CLOCK_InitSysPfd(clock_pfd_t pfd, uint8_t pfdFrac); + +/*! + * @brief De-initialize the System PLL PFD. + * + * This function disables the System PLL PFD. + * + * @param pfd Which PFD clock to disable. + */ +void CLOCK_DeinitSysPfd(clock_pfd_t pfd); + +/*! + * @brief Initialize the USB1 PLL PFD. + * + * This function initializes the USB1 PLL PFD. During new value setting, + * the clock output is disabled to prevent glitch. + * + * @param pfd Which PFD clock to enable. + * @param pfdFrac The PFD FRAC value. + * @note It is recommended that PFD settings are kept between 12-35. + */ +void CLOCK_InitUsb1Pfd(clock_pfd_t pfd, uint8_t pfdFrac); + +/*! + * @brief De-initialize the USB1 PLL PFD. + * + * This function disables the USB1 PLL PFD. + * + * @param pfd Which PFD clock to disable. + */ +void CLOCK_DeinitUsb1Pfd(clock_pfd_t pfd); + +/*! + * @brief Get current System PLL PFD output frequency. + * + * This function get current output frequency of specific System PLL PFD + * + * @param pfd pfd name to get frequency. + * @return The PFD output frequency in hertz. + */ +uint32_t CLOCK_GetSysPfdFreq(clock_pfd_t pfd); + +/*! + * @brief Get current USB1 PLL PFD output frequency. + * + * This function get current output frequency of specific USB1 PLL PFD + * + * @param pfd pfd name to get frequency. + * @return The PFD output frequency in hertz. + */ +uint32_t CLOCK_GetUsb1PfdFreq(clock_pfd_t pfd); + +/*! @brief Enable USB HS PHY PLL clock. + * + * This function enables the internal 480MHz USB PHY PLL clock. + * + * @param src USB HS PHY PLL clock source. + * @param freq The frequency specified by src. + * @retval true The clock is set successfully. + * @retval false The clock source is invalid to get proper USB HS clock. + */ +bool CLOCK_EnableUsbhs0PhyPllClock(clock_usb_phy_src_t src, uint32_t freq); + +/*! @brief Disable USB HS PHY PLL clock. + * + * This function disables USB HS PHY PLL clock. + */ +void CLOCK_DisableUsbhs0PhyPllClock(void); + +/*! @brief Enable USB HS PHY PLL clock. + * + * This function enables the internal 480MHz USB PHY PLL clock. + * + * @param src USB HS PHY PLL clock source. + * @param freq The frequency specified by src. + * @retval true The clock is set successfully. + * @retval false The clock source is invalid to get proper USB HS clock. + */ +bool CLOCK_EnableUsbhs1PhyPllClock(clock_usb_phy_src_t src, uint32_t freq); + +/*! @brief Disable USB HS PHY PLL clock. + * + * This function disables USB HS PHY PLL clock. + */ +void CLOCK_DisableUsbhs1PhyPllClock(void); + +/*! + * @brief Use DWT to delay at least for some time. + * Please note that, this API will calculate the microsecond period with the maximum + * supported CPU frequency, so this API will only delay for at least the given microseconds, if precise + * delay count was needed, please implement a new timer count to achieve this function. + * + * @param delay_us Delay time in unit of microsecond. + */ +void SDK_DelayAtLeastUs(uint32_t delay_us); + +/* @} */ + +#if defined(__cplusplus) +} +#endif /* __cplusplus */ + +/*! @} */ + +#endif /* _FSL_CLOCK_H_ */ diff --git a/Ubiquitous/XiZi/board/xidatong/third_party_driver/include/fsl_common.h b/Ubiquitous/XiZi/board/xidatong/third_party_driver/include/fsl_common.h new file mode 100755 index 0000000..6d07932 --- /dev/null +++ b/Ubiquitous/XiZi/board/xidatong/third_party_driver/include/fsl_common.h @@ -0,0 +1,593 @@ +/* + * Copyright (c) 2015-2016, Freescale Semiconductor, Inc. + * Copyright 2016-2018 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +/** + * @file fsl_common.h + * @brief common drivers header + * @version 2.0 + * @author AIIT XUOS Lab + * @date 2022-03-15 + */ + +#ifndef _FSL_COMMON_H_ +#define _FSL_COMMON_H_ + +#include +#include +#include +#include +#include + +#if defined(__ICCARM__) +#include +#endif + +#include "fsl_device_registers.h" + +/*! + * @addtogroup ksdk_common + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @brief Construct a status code value from a group and code number. */ +#define MAKE_STATUS(group, code) ((((group)*100) + (code))) + +/*! @brief Construct the version number for drivers. */ +#define MAKE_VERSION(major, minor, bugfix) (((major) << 16) | ((minor) << 8) | (bugfix)) + +/*! @name Driver version */ +/*@{*/ +/*! @brief common driver version 2.0.1. */ +#define FSL_COMMON_DRIVER_VERSION (MAKE_VERSION(2, 0, 1)) +/*@}*/ + +/* Debug console type definition. */ +#define DEBUG_CONSOLE_DEVICE_TYPE_NONE 0U /*!< No debug console. */ +#define DEBUG_CONSOLE_DEVICE_TYPE_UART 1U /*!< Debug console based on UART. */ +#define DEBUG_CONSOLE_DEVICE_TYPE_LPUART 2U /*!< Debug console based on LPUART. */ +#define DEBUG_CONSOLE_DEVICE_TYPE_LPSCI 3U /*!< Debug console based on LPSCI. */ +#define DEBUG_CONSOLE_DEVICE_TYPE_USBCDC 4U /*!< Debug console based on USBCDC. */ +#define DEBUG_CONSOLE_DEVICE_TYPE_FLEXCOMM 5U /*!< Debug console based on FLEXCOMM. */ +#define DEBUG_CONSOLE_DEVICE_TYPE_IUART 6U /*!< Debug console based on i.MX UART. */ +#define DEBUG_CONSOLE_DEVICE_TYPE_VUSART 7U /*!< Debug console based on LPC_VUSART. */ +#define DEBUG_CONSOLE_DEVICE_TYPE_MINI_USART 8U /*!< Debug console based on LPC_USART. */ +#define DEBUG_CONSOLE_DEVICE_TYPE_SWO 9U /*!< Debug console based on SWO. */ + +/*! @brief Status group numbers. */ +enum _status_groups +{ + kStatusGroup_Generic = 0, /*!< Group number for generic status codes. */ + kStatusGroup_FLASH = 1, /*!< Group number for FLASH status codes. */ + kStatusGroup_LPSPI = 4, /*!< Group number for LPSPI status codes. */ + kStatusGroup_FLEXIO_SPI = 5, /*!< Group number for FLEXIO SPI status codes. */ + kStatusGroup_DSPI = 6, /*!< Group number for DSPI status codes. */ + kStatusGroup_FLEXIO_UART = 7, /*!< Group number for FLEXIO UART status codes. */ + kStatusGroup_FLEXIO_I2C = 8, /*!< Group number for FLEXIO I2C status codes. */ + kStatusGroup_LPI2C = 9, /*!< Group number for LPI2C status codes. */ + kStatusGroup_UART = 10, /*!< Group number for UART status codes. */ + kStatusGroup_I2C = 11, /*!< Group number for UART status codes. */ + kStatusGroup_LPSCI = 12, /*!< Group number for LPSCI status codes. */ + kStatusGroup_LPUART = 13, /*!< Group number for LPUART status codes. */ + kStatusGroup_SPI = 14, /*!< Group number for SPI status code.*/ + kStatusGroup_XRDC = 15, /*!< Group number for XRDC status code.*/ + kStatusGroup_SEMA42 = 16, /*!< Group number for SEMA42 status code.*/ + kStatusGroup_SDHC = 17, /*!< Group number for SDHC status code */ + kStatusGroup_SDMMC = 18, /*!< Group number for SDMMC status code */ + kStatusGroup_SAI = 19, /*!< Group number for SAI status code */ + kStatusGroup_MCG = 20, /*!< Group number for MCG status codes. */ + kStatusGroup_SCG = 21, /*!< Group number for SCG status codes. */ + kStatusGroup_SDSPI = 22, /*!< Group number for SDSPI status codes. */ + kStatusGroup_FLEXIO_I2S = 23, /*!< Group number for FLEXIO I2S status codes */ + kStatusGroup_FLEXIO_MCULCD = 24, /*!< Group number for FLEXIO LCD status codes */ + kStatusGroup_FLASHIAP = 25, /*!< Group number for FLASHIAP status codes */ + kStatusGroup_FLEXCOMM_I2C = 26, /*!< Group number for FLEXCOMM I2C status codes */ + kStatusGroup_I2S = 27, /*!< Group number for I2S status codes */ + kStatusGroup_IUART = 28, /*!< Group number for IUART status codes */ + kStatusGroup_CSI = 29, /*!< Group number for CSI status codes */ + kStatusGroup_MIPI_DSI = 30, /*!< Group number for MIPI DSI status codes */ + kStatusGroup_SDRAMC = 35, /*!< Group number for SDRAMC status codes. */ + kStatusGroup_POWER = 39, /*!< Group number for POWER status codes. */ + kStatusGroup_ENET = 40, /*!< Group number for ENET status codes. */ + kStatusGroup_PHY = 41, /*!< Group number for PHY status codes. */ + kStatusGroup_TRGMUX = 42, /*!< Group number for TRGMUX status codes. */ + kStatusGroup_SMARTCARD = 43, /*!< Group number for SMARTCARD status codes. */ + kStatusGroup_LMEM = 44, /*!< Group number for LMEM status codes. */ + kStatusGroup_QSPI = 45, /*!< Group number for QSPI status codes. */ + kStatusGroup_DMA = 50, /*!< Group number for DMA status codes. */ + kStatusGroup_EDMA = 51, /*!< Group number for EDMA status codes. */ + kStatusGroup_DMAMGR = 52, /*!< Group number for DMAMGR status codes. */ + kStatusGroup_FLEXCAN = 53, /*!< Group number for FlexCAN status codes. */ + kStatusGroup_LTC = 54, /*!< Group number for LTC status codes. */ + kStatusGroup_FLEXIO_CAMERA = 55, /*!< Group number for FLEXIO CAMERA status codes. */ + kStatusGroup_LPC_SPI = 56, /*!< Group number for LPC_SPI status codes. */ + kStatusGroup_LPC_USART = 57, /*!< Group number for LPC_USART status codes. */ + kStatusGroup_DMIC = 58, /*!< Group number for DMIC status codes. */ + kStatusGroup_SDIF = 59, /*!< Group number for SDIF status codes.*/ + kStatusGroup_SPIFI = 60, /*!< Group number for SPIFI status codes. */ + kStatusGroup_OTP = 61, /*!< Group number for OTP status codes. */ + kStatusGroup_MCAN = 62, /*!< Group number for MCAN status codes. */ + kStatusGroup_CAAM = 63, /*!< Group number for CAAM status codes. */ + kStatusGroup_ECSPI = 64, /*!< Group number for ECSPI status codes. */ + kStatusGroup_USDHC = 65, /*!< Group number for USDHC status codes.*/ + kStatusGroup_LPC_I2C = 66, /*!< Group number for LPC_I2C status codes.*/ + kStatusGroup_DCP = 67, /*!< Group number for DCP status codes.*/ + kStatusGroup_MSCAN = 68, /*!< Group number for MSCAN status codes.*/ + kStatusGroup_ESAI = 69, /*!< Group number for ESAI status codes. */ + kStatusGroup_FLEXSPI = 70, /*!< Group number for FLEXSPI status codes. */ + kStatusGroup_MMDC = 71, /*!< Group number for MMDC status codes. */ + kStatusGroup_PDM = 72, /*!< Group number for MIC status codes. */ + kStatusGroup_SDMA = 73, /*!< Group number for SDMA status codes. */ + kStatusGroup_ICS = 74, /*!< Group number for ICS status codes. */ + kStatusGroup_SPDIF = 75, /*!< Group number for SPDIF status codes. */ + kStatusGroup_LPC_MINISPI = 76, /*!< Group number for LPC_MINISPI status codes. */ + kStatusGroup_HASHCRYPT = 77, /*!< Group number for Hashcrypt status codes */ + kStatusGroup_LPC_SPI_SSP = 78, /*!< Group number for LPC_SPI_SSP status codes. */ + kStatusGroup_LPC_I2C_1 = 97, /*!< Group number for LPC_I2C_1 status codes. */ + kStatusGroup_NOTIFIER = 98, /*!< Group number for NOTIFIER status codes. */ + kStatusGroup_DebugConsole = 99, /*!< Group number for debug console status codes. */ + kStatusGroup_SEMC = 100, /*!< Group number for SEMC status codes. */ + kStatusGroup_ApplicationRangeStart = 101, /*!< Starting number for application groups. */ + kStatusGroup_IAP = 102, /*!< Group number for IAP status codes */ + + kStatusGroup_HAL_GPIO = 121, /*!< Group number for HAL GPIO status codes. */ + kStatusGroup_HAL_UART = 122, /*!< Group number for HAL UART status codes. */ + kStatusGroup_HAL_TIMER = 123, /*!< Group number for HAL TIMER status codes. */ + kStatusGroup_HAL_SPI = 124, /*!< Group number for HAL SPI status codes. */ + kStatusGroup_HAL_I2C = 125, /*!< Group number for HAL I2C status codes. */ + kStatusGroup_HAL_FLASH = 126, /*!< Group number for HAL FLASH status codes. */ + kStatusGroup_HAL_PWM = 127, /*!< Group number for HAL PWM status codes. */ + kStatusGroup_HAL_RNG = 128, /*!< Group number for HAL RNG status codes. */ + kStatusGroup_TIMERMANAGER = 135, /*!< Group number for TiMER MANAGER status codes. */ + kStatusGroup_SERIALMANAGER = 136, /*!< Group number for SERIAL MANAGER status codes. */ + kStatusGroup_LED = 137, /*!< Group number for LED status codes. */ + kStatusGroup_BUTTON = 138, /*!< Group number for BUTTON status codes. */ + kStatusGroup_EXTERN_EEPROM = 139, /*!< Group number for EXTERN EEPROM status codes. */ + kStatusGroup_SHELL = 140, /*!< Group number for SHELL status codes. */ + kStatusGroup_MEM_MANAGER = 141, /*!< Group number for MEM MANAGER status codes. */ + kStatusGroup_LIST = 142, /*!< Group number for List status codes. */ + kStatusGroup_OSA = 143, /*!< Group number for OSA status codes. */ + kStatusGroup_COMMON_TASK = 144, /*!< Group number for Common task status codes. */ + kStatusGroup_MSG = 145, /*!< Group number for messaging status codes. */ +}; + +/*! @brief Generic status return codes. */ +enum _generic_status +{ + kStatus_Success = MAKE_STATUS(kStatusGroup_Generic, 0), + kStatus_Fail = MAKE_STATUS(kStatusGroup_Generic, 1), + kStatus_ReadOnly = MAKE_STATUS(kStatusGroup_Generic, 2), + kStatus_OutOfRange = MAKE_STATUS(kStatusGroup_Generic, 3), + kStatus_InvalidArgument = MAKE_STATUS(kStatusGroup_Generic, 4), + kStatus_Timeout = MAKE_STATUS(kStatusGroup_Generic, 5), + kStatus_NoTransferInProgress = MAKE_STATUS(kStatusGroup_Generic, 6), +}; + +/*! @brief Type used for all status and error return values. */ +typedef int32_t status_t; + +/* + * The fsl_clock.h is included here because it needs MAKE_VERSION/MAKE_STATUS/status_t + * defined in previous of this file. + */ +#include "fsl_clock.h" + +/* + * Chip level peripheral reset API, for MCUs that implement peripheral reset control external to a peripheral + */ +#if ((defined(FSL_FEATURE_SOC_SYSCON_COUNT) && (FSL_FEATURE_SOC_SYSCON_COUNT > 0)) || \ + (defined(FSL_FEATURE_SOC_ASYNC_SYSCON_COUNT) && (FSL_FEATURE_SOC_ASYNC_SYSCON_COUNT > 0))) +#include "fsl_reset.h" +#endif + +/* + * Macro guard for whether to use default weak IRQ implementation in drivers + */ +#ifndef FSL_DRIVER_TRANSFER_DOUBLE_WEAK_IRQ +#define FSL_DRIVER_TRANSFER_DOUBLE_WEAK_IRQ 1 +#endif + +/*! @name Min/max macros */ +/* @{ */ +#if !defined(MIN) +#define MIN(a, b) ((a) < (b) ? (a) : (b)) +#endif + +#if !defined(MAX) +#define MAX(a, b) ((a) > (b) ? (a) : (b)) +#endif +/* @} */ + +/*! @brief Computes the number of elements in an array. */ +#if !defined(ARRAY_SIZE) +#define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0])) +#endif + +/*! @name UINT16_MAX/UINT32_MAX value */ +/* @{ */ +#if !defined(UINT16_MAX) +#define UINT16_MAX ((uint16_t)-1) +#endif + +#if !defined(UINT32_MAX) +#define UINT32_MAX ((uint32_t)-1) +#endif +/* @} */ + +/*! @name Timer utilities */ +/* @{ */ +/*! Macro to convert a microsecond period to raw count value */ +#define USEC_TO_COUNT(us, clockFreqInHz) (uint64_t)((uint64_t)us * clockFreqInHz / 1000000U) +/*! Macro to convert a raw count value to microsecond */ +#define COUNT_TO_USEC(count, clockFreqInHz) (uint64_t)((uint64_t)count * 1000000U / clockFreqInHz) + +/*! Macro to convert a millisecond period to raw count value */ +#define MSEC_TO_COUNT(ms, clockFreqInHz) (uint64_t)((uint64_t)ms * clockFreqInHz / 1000U) +/*! Macro to convert a raw count value to millisecond */ +#define COUNT_TO_MSEC(count, clockFreqInHz) (uint64_t)((uint64_t)count * 1000U / clockFreqInHz) +/* @} */ + +/*! @name Alignment variable definition macros */ +/* @{ */ +#if (defined(__ICCARM__)) +/** + * Workaround to disable MISRA C message suppress warnings for IAR compiler. + * http://supp.iar.com/Support/?note=24725 + */ +_Pragma("diag_suppress=Pm120") +#define SDK_PRAGMA(x) _Pragma(#x) + _Pragma("diag_error=Pm120") +/*! Macro to define a variable with alignbytes alignment */ +#define SDK_ALIGN(var, alignbytes) SDK_PRAGMA(data_alignment = alignbytes) var +/*! Macro to define a variable with L1 d-cache line size alignment */ +#if defined(FSL_FEATURE_L1DCACHE_LINESIZE_BYTE) +#define SDK_L1DCACHE_ALIGN(var) SDK_PRAGMA(data_alignment = FSL_FEATURE_L1DCACHE_LINESIZE_BYTE) var +#endif +/*! Macro to define a variable with L2 cache line size alignment */ +#if defined(FSL_FEATURE_L2CACHE_LINESIZE_BYTE) +#define SDK_L2CACHE_ALIGN(var) SDK_PRAGMA(data_alignment = FSL_FEATURE_L2CACHE_LINESIZE_BYTE) var +#endif +#elif defined(__CC_ARM) || defined(__ARMCC_VERSION) +/*! Macro to define a variable with alignbytes alignment */ +#define SDK_ALIGN(var, alignbytes) __attribute__((aligned(alignbytes))) var +/*! Macro to define a variable with L1 d-cache line size alignment */ +#if defined(FSL_FEATURE_L1DCACHE_LINESIZE_BYTE) +#define SDK_L1DCACHE_ALIGN(var) __attribute__((aligned(FSL_FEATURE_L1DCACHE_LINESIZE_BYTE))) var +#endif +/*! Macro to define a variable with L2 cache line size alignment */ +#if defined(FSL_FEATURE_L2CACHE_LINESIZE_BYTE) +#define SDK_L2CACHE_ALIGN(var) __attribute__((aligned(FSL_FEATURE_L2CACHE_LINESIZE_BYTE))) var +#endif +#elif defined(__GNUC__) +/*! Macro to define a variable with alignbytes alignment */ +#define SDK_ALIGN(var, alignbytes) var __attribute__((aligned(alignbytes))) +/*! Macro to define a variable with L1 d-cache line size alignment */ +#if defined(FSL_FEATURE_L1DCACHE_LINESIZE_BYTE) +#define SDK_L1DCACHE_ALIGN(var) var __attribute__((aligned(FSL_FEATURE_L1DCACHE_LINESIZE_BYTE))) +#endif +/*! Macro to define a variable with L2 cache line size alignment */ +#if defined(FSL_FEATURE_L2CACHE_LINESIZE_BYTE) +#define SDK_L2CACHE_ALIGN(var) var __attribute__((aligned(FSL_FEATURE_L2CACHE_LINESIZE_BYTE))) +#endif +#else +#error Toolchain not supported +#define SDK_ALIGN(var, alignbytes) var +#if defined(FSL_FEATURE_L1DCACHE_LINESIZE_BYTE) +#define SDK_L1DCACHE_ALIGN(var) var +#endif +#if defined(FSL_FEATURE_L2CACHE_LINESIZE_BYTE) +#define SDK_L2CACHE_ALIGN(var) var +#endif +#endif + +/*! Macro to change a value to a given size aligned value */ +#define SDK_SIZEALIGN(var, alignbytes) \ + ((unsigned int)((var) + ((alignbytes)-1)) & (unsigned int)(~(unsigned int)((alignbytes)-1))) +/* @} */ + +/*! @name Non-cacheable region definition macros */ +/* For initialized non-zero non-cacheable variables, please using "AT_NONCACHEABLE_SECTION_INIT(var) ={xx};" or + * "AT_NONCACHEABLE_SECTION_ALIGN_INIT(var) ={xx};" in your projects to define them, for zero-inited non-cacheable variables, + * please using "AT_NONCACHEABLE_SECTION(var);" or "AT_NONCACHEABLE_SECTION_ALIGN(var);" to define them, these zero-inited variables + * will be initialized to zero in system startup. + */ +/* @{ */ +#if (defined(__ICCARM__)) +#if ((!(defined(FSL_FEATURE_HAS_NO_NONCACHEABLE_SECTION) && FSL_FEATURE_HAS_NO_NONCACHEABLE_SECTION)) && defined(FSL_FEATURE_L1ICACHE_LINESIZE_BYTE)) +#define AT_NONCACHEABLE_SECTION(var) var @"NonCacheable" +#define AT_NONCACHEABLE_SECTION_ALIGN(var, alignbytes) SDK_PRAGMA(data_alignment = alignbytes) var @"NonCacheable" +#define AT_NONCACHEABLE_SECTION_INIT(var) var @"NonCacheable.init" +#define AT_NONCACHEABLE_SECTION_ALIGN_INIT(var, alignbytes) SDK_PRAGMA(data_alignment = alignbytes) var @"NonCacheable.init" +#else +#define AT_NONCACHEABLE_SECTION(var) var +#define AT_NONCACHEABLE_SECTION_ALIGN(var, alignbytes) SDK_PRAGMA(data_alignment = alignbytes) var +#define AT_NONCACHEABLE_SECTION_INIT(var) var +#define AT_NONCACHEABLE_SECTION_ALIGN_INIT(var, alignbytes) SDK_PRAGMA(data_alignment = alignbytes) var +#endif +#elif(defined(__CC_ARM) || defined(__ARMCC_VERSION)) +#if ((!(defined(FSL_FEATURE_HAS_NO_NONCACHEABLE_SECTION) && FSL_FEATURE_HAS_NO_NONCACHEABLE_SECTION)) && defined(FSL_FEATURE_L1ICACHE_LINESIZE_BYTE)) +#define AT_NONCACHEABLE_SECTION(var) __attribute__((section("NonCacheable"), zero_init)) var +#define AT_NONCACHEABLE_SECTION_ALIGN(var, alignbytes) \ + __attribute__((section("NonCacheable"), zero_init)) __attribute__((aligned(alignbytes))) var +#define AT_NONCACHEABLE_SECTION_INIT(var) __attribute__((section("NonCacheable.init"))) var +#define AT_NONCACHEABLE_SECTION_ALIGN_INIT(var, alignbytes) \ + __attribute__((section("NonCacheable.init"))) __attribute__((aligned(alignbytes))) var +#else +#define AT_NONCACHEABLE_SECTION(var) var +#define AT_NONCACHEABLE_SECTION_ALIGN(var, alignbytes) __attribute__((aligned(alignbytes))) var +#define AT_NONCACHEABLE_SECTION_INIT(var) var +#define AT_NONCACHEABLE_SECTION_ALIGN_INIT(var, alignbytes) __attribute__((aligned(alignbytes))) var +#endif +#elif(defined(__GNUC__)) +/* For GCC, when the non-cacheable section is required, please define "__STARTUP_INITIALIZE_NONCACHEDATA" + * in your projects to make sure the non-cacheable section variables will be initialized in system startup. + */ +#if ((!(defined(FSL_FEATURE_HAS_NO_NONCACHEABLE_SECTION) && FSL_FEATURE_HAS_NO_NONCACHEABLE_SECTION)) && defined(FSL_FEATURE_L1ICACHE_LINESIZE_BYTE)) +#define AT_NONCACHEABLE_SECTION_INIT(var) __attribute__((section("NonCacheable.init"))) var +#define AT_NONCACHEABLE_SECTION_ALIGN_INIT(var, alignbytes) \ + __attribute__((section("NonCacheable.init"))) var __attribute__((aligned(alignbytes))) +#define AT_NONCACHEABLE_SECTION(var) __attribute__((section("NonCacheable,\"aw\",%nobits @"))) var +#define AT_NONCACHEABLE_SECTION_ALIGN(var, alignbytes) \ + __attribute__((section("NonCacheable,\"aw\",%nobits @"))) var __attribute__((aligned(alignbytes))) +#else +#define AT_NONCACHEABLE_SECTION(var) var +#define AT_NONCACHEABLE_SECTION_ALIGN(var, alignbytes) var __attribute__((aligned(alignbytes))) +#define AT_NONCACHEABLE_SECTION_INIT(var) var +#define AT_NONCACHEABLE_SECTION_ALIGN_INIT(var, alignbytes) var __attribute__((aligned(alignbytes))) +#endif +#else +#error Toolchain not supported. +#define AT_NONCACHEABLE_SECTION(var) var +#define AT_NONCACHEABLE_SECTION_ALIGN(var, alignbytes) var +#define AT_NONCACHEABLE_SECTION_INIT(var) var +#define AT_NONCACHEABLE_SECTION_ALIGN_INIT(var, alignbytes) var +#endif +/* @} */ + +/*! @name Time sensitive region */ +/* @{ */ +#if defined(FSL_SDK_DRIVER_QUICK_ACCESS_ENABLE) && FSL_SDK_DRIVER_QUICK_ACCESS_ENABLE +#if (defined(__ICCARM__)) +#define AT_QUICKACCESS_SECTION_CODE(func) func @"CodeQuickAccess" +#define AT_QUICKACCESS_SECTION_DATA(func) func @"DataQuickAccess" +#elif(defined(__CC_ARM) || defined(__ARMCC_VERSION)) +#define AT_QUICKACCESS_SECTION_CODE(func) __attribute__((section("CodeQuickAccess"))) func +#define AT_QUICKACCESS_SECTION_DATA(func) __attribute__((section("DataQuickAccess"))) func +#elif(defined(__GNUC__)) +#define AT_QUICKACCESS_SECTION_CODE(func) __attribute__((section("CodeQuickAccess"))) func +#define AT_QUICKACCESS_SECTION_DATA(func) __attribute__((section("DataQuickAccess"))) func +#else +#error Toolchain not supported. +#endif /* defined(__ICCARM__) */ +#else +#if (defined(__ICCARM__)) +#define AT_QUICKACCESS_SECTION_CODE(func) func +#define AT_QUICKACCESS_SECTION_DATA(func) func +#elif(defined(__CC_ARM) || defined(__ARMCC_VERSION)) +#define AT_QUICKACCESS_SECTION_CODE(func) func +#define AT_QUICKACCESS_SECTION_DATA(func) func +#elif(defined(__GNUC__)) +#define AT_QUICKACCESS_SECTION_CODE(func) func +#define AT_QUICKACCESS_SECTION_DATA(func) func +#else +#error Toolchain not supported. +#endif +#endif /* __FSL_SDK_DRIVER_QUICK_ACCESS_ENABLE */ +/* @} */ + +/*! @name Ram Function */ +#if (defined(__ICCARM__)) +#define RAMFUNCTION_SECTION_CODE(func) func @"RamFunction" +#elif(defined(__CC_ARM) || defined(__ARMCC_VERSION)) +#define RAMFUNCTION_SECTION_CODE(func) __attribute__((section("RamFunction"))) func +#elif(defined(__GNUC__)) +#define RAMFUNCTION_SECTION_CODE(func) __attribute__((section("RamFunction"))) func +#else +#error Toolchain not supported. +#endif /* defined(__ICCARM__) */ +/* @} */ +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) + extern "C" +{ +#endif + + /*! + * @brief Enable specific interrupt. + * + * Enable LEVEL1 interrupt. For some devices, there might be multiple interrupt + * levels. For example, there are NVIC and intmux. Here the interrupts connected + * to NVIC are the LEVEL1 interrupts, because they are routed to the core directly. + * The interrupts connected to intmux are the LEVEL2 interrupts, they are routed + * to NVIC first then routed to core. + * + * This function only enables the LEVEL1 interrupts. The number of LEVEL1 interrupts + * is indicated by the feature macro FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS. + * + * @param interrupt The IRQ number. + * @retval kStatus_Success Interrupt enabled successfully + * @retval kStatus_Fail Failed to enable the interrupt + */ + static inline status_t EnableIRQ(IRQn_Type interrupt) + { + if (NotAvail_IRQn == interrupt) + { + return kStatus_Fail; + } + +#if defined(FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS) && (FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS > 0) + if (interrupt >= FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS) + { + return kStatus_Fail; + } +#endif + +#if defined(__GIC_PRIO_BITS) + GIC_EnableIRQ(interrupt); +#else + NVIC_EnableIRQ(interrupt); +#endif + return kStatus_Success; + } + + /*! + * @brief Disable specific interrupt. + * + * Disable LEVEL1 interrupt. For some devices, there might be multiple interrupt + * levels. For example, there are NVIC and intmux. Here the interrupts connected + * to NVIC are the LEVEL1 interrupts, because they are routed to the core directly. + * The interrupts connected to intmux are the LEVEL2 interrupts, they are routed + * to NVIC first then routed to core. + * + * This function only disables the LEVEL1 interrupts. The number of LEVEL1 interrupts + * is indicated by the feature macro FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS. + * + * @param interrupt The IRQ number. + * @retval kStatus_Success Interrupt disabled successfully + * @retval kStatus_Fail Failed to disable the interrupt + */ + static inline status_t DisableIRQ(IRQn_Type interrupt) + { + if (NotAvail_IRQn == interrupt) + { + return kStatus_Fail; + } + +#if defined(FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS) && (FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS > 0) + if (interrupt >= FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS) + { + return kStatus_Fail; + } +#endif + +#if defined(__GIC_PRIO_BITS) + GIC_DisableIRQ(interrupt); +#else + NVIC_DisableIRQ(interrupt); +#endif + return kStatus_Success; + } + + /*! + * @brief Disable the global IRQ + * + * Disable the global interrupt and return the current primask register. User is required to provided the primask + * register for the EnableGlobalIRQ(). + * + * @return Current primask value. + */ + static inline uint32_t DisableGlobalIRQ(void) + { +#if defined(CPSR_I_Msk) + uint32_t cpsr = __get_CPSR() & CPSR_I_Msk; + + __disable_irq(); + + return cpsr; +#else + uint32_t regPrimask = __get_PRIMASK(); + + __disable_irq(); + + return regPrimask; +#endif + } + + /*! + * @brief Enable the global IRQ + * + * Set the primask register with the provided primask value but not just enable the primask. The idea is for the + * convenience of integration of RTOS. some RTOS get its own management mechanism of primask. User is required to + * use the EnableGlobalIRQ() and DisableGlobalIRQ() in pair. + * + * @param primask value of primask register to be restored. The primask value is supposed to be provided by the + * DisableGlobalIRQ(). + */ + static inline void EnableGlobalIRQ(uint32_t primask) + { +#if defined(CPSR_I_Msk) + __set_CPSR((__get_CPSR() & ~CPSR_I_Msk) | primask); +#else + __set_PRIMASK(primask); +#endif + } + +#if defined(ENABLE_RAM_VECTOR_TABLE) + /*! + * @brief install IRQ handler + * + * @param irq IRQ number + * @param irqHandler IRQ handler address + * @return The old IRQ handler address + */ + uint32_t InstallIRQHandler(IRQn_Type irq, uint32_t irqHandler); +#endif /* ENABLE_RAM_VECTOR_TABLE. */ + +#if (defined(FSL_FEATURE_SOC_SYSCON_COUNT) && (FSL_FEATURE_SOC_SYSCON_COUNT > 0)) + /*! + * @brief Enable specific interrupt for wake-up from deep-sleep mode. + * + * Enable the interrupt for wake-up from deep sleep mode. + * Some interrupts are typically used in sleep mode only and will not occur during + * deep-sleep mode because relevant clocks are stopped. However, it is possible to enable + * those clocks (significantly increasing power consumption in the reduced power mode), + * making these wake-ups possible. + * + * @note This function also enables the interrupt in the NVIC (EnableIRQ() is called internaly). + * + * @param interrupt The IRQ number. + */ + void EnableDeepSleepIRQ(IRQn_Type interrupt); + + /*! + * @brief Disable specific interrupt for wake-up from deep-sleep mode. + * + * Disable the interrupt for wake-up from deep sleep mode. + * Some interrupts are typically used in sleep mode only and will not occur during + * deep-sleep mode because relevant clocks are stopped. However, it is possible to enable + * those clocks (significantly increasing power consumption in the reduced power mode), + * making these wake-ups possible. + * + * @note This function also disables the interrupt in the NVIC (DisableIRQ() is called internaly). + * + * @param interrupt The IRQ number. + */ + void DisableDeepSleepIRQ(IRQn_Type interrupt); +#endif /* FSL_FEATURE_SOC_SYSCON_COUNT */ + + /*! + * @brief Allocate memory with given alignment and aligned size. + * + * This is provided to support the dynamically allocated memory + * used in cache-able region. + * @param size The length required to malloc. + * @param alignbytes The alignment size. + * @retval The allocated memory. + */ + void *SDK_Malloc(size_t size, size_t alignbytes); + + /*! + * @brief Free memory. + * + * @param ptr The memory to be release. + */ + void SDK_Free(void *ptr); + +#if defined(__cplusplus) +} +#endif + +/*! @} */ + +#endif /* _FSL_COMMON_H_ */ diff --git a/Ubiquitous/XiZi/board/xidatong/third_party_driver/include/fsl_device_registers.h b/Ubiquitous/XiZi/board/xidatong/third_party_driver/include/fsl_device_registers.h new file mode 100755 index 0000000..c16a90f --- /dev/null +++ b/Ubiquitous/XiZi/board/xidatong/third_party_driver/include/fsl_device_registers.h @@ -0,0 +1,44 @@ +/* + * Copyright 2014-2016 Freescale Semiconductor, Inc. + * Copyright 2016-2018 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +/** + * @file fsl_device_registers.h + * @brief device register function + * @version 2.0 + * @author AIIT XUOS Lab + * @date 2022-03-15 + */ + +#ifndef __FSL_DEVICE_REGISTERS_H__ +#define __FSL_DEVICE_REGISTERS_H__ + +/* + * Include the cpu specific register header files. + * + * The CPU macro should be declared in the project or makefile. + */ +#if (defined(CPU_MIMXRT1052CVJ5B) || defined(CPU_MIMXRT1052CVL5B) || defined(CPU_MIMXRT1052DVJ6B) || \ + defined(CPU_MIMXRT1052DVL6B)) + +#define MIMXRT1052_SERIES + +/* CMSIS-style register definitions */ +#include "MIMXRT1052.h" +/* CPU specific feature definitions */ +#include "MIMXRT1052_features.h" + +#else + #error "No valid CPU defined!" +#endif + +#endif /* __FSL_DEVICE_REGISTERS_H__ */ + +/******************************************************************************* + * EOF + ******************************************************************************/ diff --git a/Ubiquitous/XiZi/board/xidatong/third_party_driver/include/fsl_enet.h b/Ubiquitous/XiZi/board/xidatong/third_party_driver/include/fsl_enet.h new file mode 100755 index 0000000..35e7676 --- /dev/null +++ b/Ubiquitous/XiZi/board/xidatong/third_party_driver/include/fsl_enet.h @@ -0,0 +1,1617 @@ +/* + * Copyright (c) 2015 - 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2019 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +/** + * @file fsl_enet.h + * @brief ethernet drivers + * @version 2.0 + * @author AIIT XUOS Lab + * @date 2022-03-15 + */ + +#ifndef _FSL_ENET_H_ +#define _FSL_ENET_H_ + +#include "fsl_common.h" +#if defined(FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET) && FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET +#include "fsl_memory.h" +#endif +/*! + * @addtogroup enet + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @name Driver version */ +/*@{*/ +/*! @brief Defines the driver version. */ +#define FSL_ENET_DRIVER_VERSION (MAKE_VERSION(2, 2, 4)) /*!< Version 2.2.4. */ +/*@}*/ + +/*! @name ENET DESCRIPTOR QUEUE */ +/*@{*/ +/*! @brief Defines the queue number. */ +#ifndef FSL_FEATURE_ENET_QUEUE +#define FSL_FEATURE_ENET_QUEUE 1 /* Singal queue for previous IP. */ +#endif +/*@}*/ + +/*! @name Control and status region bit masks of the receive buffer descriptor. */ +/*@{*/ +#define ENET_BUFFDESCRIPTOR_RX_EMPTY_MASK 0x8000U /*!< Empty bit mask. */ +#define ENET_BUFFDESCRIPTOR_RX_SOFTOWNER1_MASK 0x4000U /*!< Software owner one mask. */ +#define ENET_BUFFDESCRIPTOR_RX_WRAP_MASK 0x2000U /*!< Next buffer descriptor is the start address. */ +#define ENET_BUFFDESCRIPTOR_RX_SOFTOWNER2_Mask 0x1000U /*!< Software owner two mask. */ +#define ENET_BUFFDESCRIPTOR_RX_LAST_MASK 0x0800U /*!< Last BD of the frame mask. */ +#define ENET_BUFFDESCRIPTOR_RX_MISS_MASK 0x0100U /*!< Received because of the promiscuous mode. */ +#define ENET_BUFFDESCRIPTOR_RX_BROADCAST_MASK 0x0080U /*!< Broadcast packet mask. */ +#define ENET_BUFFDESCRIPTOR_RX_MULTICAST_MASK 0x0040U /*!< Multicast packet mask. */ +#define ENET_BUFFDESCRIPTOR_RX_LENVLIOLATE_MASK 0x0020U /*!< Length violation mask. */ +#define ENET_BUFFDESCRIPTOR_RX_NOOCTET_MASK 0x0010U /*!< Non-octet aligned frame mask. */ +#define ENET_BUFFDESCRIPTOR_RX_CRC_MASK 0x0004U /*!< CRC error mask. */ +#define ENET_BUFFDESCRIPTOR_RX_OVERRUN_MASK 0x0002U /*!< FIFO overrun mask. */ +#define ENET_BUFFDESCRIPTOR_RX_TRUNC_MASK 0x0001U /*!< Frame is truncated mask. */ +/*@}*/ + +/*! @name Control and status bit masks of the transmit buffer descriptor. */ +/*@{*/ +#define ENET_BUFFDESCRIPTOR_TX_READY_MASK 0x8000U /*!< Ready bit mask. */ +#define ENET_BUFFDESCRIPTOR_TX_SOFTOWENER1_MASK 0x4000U /*!< Software owner one mask. */ +#define ENET_BUFFDESCRIPTOR_TX_WRAP_MASK 0x2000U /*!< Wrap buffer descriptor mask. */ +#define ENET_BUFFDESCRIPTOR_TX_SOFTOWENER2_MASK 0x1000U /*!< Software owner two mask. */ +#define ENET_BUFFDESCRIPTOR_TX_LAST_MASK 0x0800U /*!< Last BD of the frame mask. */ +#define ENET_BUFFDESCRIPTOR_TX_TRANMITCRC_MASK 0x0400U /*!< Transmit CRC mask. */ +/*@}*/ + +/* Extended control regions for enhanced buffer descriptors. */ +#ifdef ENET_ENHANCEDBUFFERDESCRIPTOR_MODE +/*! @name First extended control region bit masks of the receive buffer descriptor. */ +/*@{*/ +#define ENET_BUFFDESCRIPTOR_RX_IPV4_MASK 0x0001U /*!< Ipv4 frame mask. */ +#define ENET_BUFFDESCRIPTOR_RX_IPV6_MASK 0x0002U /*!< Ipv6 frame mask. */ +#define ENET_BUFFDESCRIPTOR_RX_VLAN_MASK 0x0004U /*!< VLAN frame mask. */ +#define ENET_BUFFDESCRIPTOR_RX_PROTOCOLCHECKSUM_MASK 0x0010U /*!< Protocol checksum error mask. */ +#define ENET_BUFFDESCRIPTOR_RX_IPHEADCHECKSUM_MASK 0x0020U /*!< IP header checksum error mask. */ +/*@}*/ + +/*! @name Second extended control region bit masks of the receive buffer descriptor. */ +/*@{*/ +#define ENET_BUFFDESCRIPTOR_RX_INTERRUPT_MASK 0x0080U /*!< BD interrupt mask. */ +#define ENET_BUFFDESCRIPTOR_RX_UNICAST_MASK 0x0100U /*!< Unicast frame mask. */ +#define ENET_BUFFDESCRIPTOR_RX_COLLISION_MASK 0x0200U /*!< BD collision mask. */ +#define ENET_BUFFDESCRIPTOR_RX_PHYERR_MASK 0x0400U /*!< PHY error mask. */ +#define ENET_BUFFDESCRIPTOR_RX_MACERR_MASK 0x8000U /*!< Mac error mask. */ +/*@}*/ + +/*! @name First extended control region bit masks of the transmit buffer descriptor. */ +/*@{*/ +#define ENET_BUFFDESCRIPTOR_TX_ERR_MASK 0x8000U /*!< Transmit error mask. */ +#define ENET_BUFFDESCRIPTOR_TX_UNDERFLOWERR_MASK 0x2000U /*!< Underflow error mask. */ +#define ENET_BUFFDESCRIPTOR_TX_EXCCOLLISIONERR_MASK 0x1000U /*!< Excess collision error mask. */ +#define ENET_BUFFDESCRIPTOR_TX_FRAMEERR_MASK 0x0800U /*!< Frame error mask. */ +#define ENET_BUFFDESCRIPTOR_TX_LATECOLLISIONERR_MASK 0x0400U /*!< Late collision error mask. */ +#define ENET_BUFFDESCRIPTOR_TX_OVERFLOWERR_MASK 0x0200U /*!< Overflow error mask. */ +#define ENET_BUFFDESCRIPTOR_TX_TIMESTAMPERR_MASK 0x0100U /*!< Timestamp error mask. */ +/*@}*/ + +/*! @name Second extended control region bit masks of the transmit buffer descriptor. */ +/*@{*/ +#define ENET_BUFFDESCRIPTOR_TX_INTERRUPT_MASK 0x4000U /*!< Interrupt mask. */ +#define ENET_BUFFDESCRIPTOR_TX_TIMESTAMP_MASK 0x2000U /*!< Timestamp flag mask. */ +#if defined(FSL_FEATURE_ENET_HAS_AVB) && FSL_FEATURE_ENET_HAS_AVB +#define ENET_BUFFDESCRIPTOR_TX_USETXLAUNCHTIME_MASK 0x0100U /*!< Use the transmit launch time. */ +#define ENET_BUFFDESCRIPTOR_TX_FRAMETYPE_MASK 0x00F0U /*!< Frame type mask. */ +#define ENET_BUFFDESCRIPTOR_TX_FRAMETYPE_SHIFT 4U /*!< Frame type shift. */ +#define ENET_BD_FTYPE(n) ((n << ENET_BUFFDESCRIPTOR_TX_FRAMETYPE_SHIFT) & ENET_BUFFDESCRIPTOR_TX_FRAMETYPE_MASK) +#endif /* FSL_FEATURE_ENET_HAS_AVB */ +/*@}*/ +#endif /* ENET_ENHANCEDBUFFERDESCRIPTOR_MODE */ + +/*! @brief Defines the receive error status flag mask. */ +#define ENET_BUFFDESCRIPTOR_RX_ERR_MASK \ + (ENET_BUFFDESCRIPTOR_RX_TRUNC_MASK | ENET_BUFFDESCRIPTOR_RX_OVERRUN_MASK | \ + ENET_BUFFDESCRIPTOR_RX_LENVLIOLATE_MASK | ENET_BUFFDESCRIPTOR_RX_NOOCTET_MASK | ENET_BUFFDESCRIPTOR_RX_CRC_MASK) +#ifdef ENET_ENHANCEDBUFFERDESCRIPTOR_MODE +#define ENET_BUFFDESCRIPTOR_RX_EXT_ERR_MASK \ + (ENET_BUFFDESCRIPTOR_RX_MACERR_MASK | ENET_BUFFDESCRIPTOR_RX_PHYERR_MASK | ENET_BUFFDESCRIPTOR_RX_COLLISION_MASK) +#endif + +/*! @name Defines some Ethernet parameters. */ +/*@{*/ +#define ENET_FRAME_MAX_FRAMELEN 1518U /*!< Default maximum Ethernet frame size. */ + +#define ENET_FIFO_MIN_RX_FULL 5U /*!< ENET minimum receive FIFO full. */ +#define ENET_RX_MIN_BUFFERSIZE 256U /*!< ENET minimum buffer size. */ +#define ENET_PHY_MAXADDRESS (ENET_MMFR_PA_MASK >> ENET_MMFR_PA_SHIFT) +#if FSL_FEATURE_ENET_QUEUE > 1 +#define ENET_TX_INTERRUPT \ + (kENET_TxFrameInterrupt | kENET_TxBufferInterrupt | kENET_TxFrame1Interrupt | kENET_TxBuffer1Interrupt | \ + kENET_TxFrame2Interrupt | kENET_TxBuffer2Interrupt) +#define ENET_RX_INTERRUPT \ + (kENET_RxFrameInterrupt | kENET_RxBufferInterrupt | kENET_RxFrame1Interrupt | kENET_RxBuffer1Interrupt | \ + kENET_RxFrame2Interrupt | kENET_RxBuffer2Interrupt) +#else +#define ENET_TX_INTERRUPT (kENET_TxFrameInterrupt | kENET_TxBufferInterrupt) +#define ENET_RX_INTERRUPT (kENET_RxFrameInterrupt | kENET_RxBufferInterrupt) +#endif /* FSL_FEATURE_ENET_QUEUE > 1 */ +#define ENET_TS_INTERRUPT (kENET_TsTimerInterrupt | kENET_TsAvailInterrupt) +#define ENET_ERR_INTERRUPT \ + (kENET_BabrInterrupt | kENET_BabtInterrupt | kENET_EBusERInterrupt | kENET_LateCollisionInterrupt | \ + kENET_RetryLimitInterrupt | kENET_UnderrunInterrupt | kENET_PayloadRxInterrupt) +#define ENET_ERR_INTERRUPT \ + (kENET_BabrInterrupt | kENET_BabtInterrupt | kENET_EBusERInterrupt | kENET_LateCollisionInterrupt | \ + kENET_RetryLimitInterrupt | kENET_UnderrunInterrupt | kENET_PayloadRxInterrupt) +/*@}*/ + +/*! @brief Defines the status return codes for transaction. */ +enum _enet_status +{ + kStatus_ENET_RxFrameError = MAKE_STATUS(kStatusGroup_ENET, 0U), /*!< A frame received but data error happen. */ + kStatus_ENET_RxFrameFail = MAKE_STATUS(kStatusGroup_ENET, 1U), /*!< Failed to receive a frame. */ + kStatus_ENET_RxFrameEmpty = MAKE_STATUS(kStatusGroup_ENET, 2U), /*!< No frame arrive. */ + kStatus_ENET_TxFrameOverLen = MAKE_STATUS(kStatusGroup_ENET, 3U), /*!< Tx frame over length. */ + kStatus_ENET_TxFrameBusy = MAKE_STATUS(kStatusGroup_ENET, 4U), /*!< Tx buffer descriptors are under process. */ + kStatus_ENET_TxFrameFail = MAKE_STATUS(kStatusGroup_ENET, 5U) /*!< Transmit frame fail. */ +#ifdef ENET_ENHANCEDBUFFERDESCRIPTOR_MODE + , + kStatus_ENET_PtpTsRingFull = MAKE_STATUS(kStatusGroup_ENET, 6U), /*!< Timestamp ring full. */ + kStatus_ENET_PtpTsRingEmpty = MAKE_STATUS(kStatusGroup_ENET, 7U) /*!< Timestamp ring empty. */ +#endif /* ENET_ENHANCEDBUFFERDESCRIPTOR_MODE */ +}; + +/*! @brief Defines the MII/RMII/RGMII mode for data interface between the MAC and the PHY. */ +typedef enum _enet_mii_mode +{ + kENET_MiiMode = 0U, /*!< MII mode for data interface. */ + kENET_RmiiMode = 1U, /*!< RMII mode for data interface. */ +#if defined(FSL_FEATURE_ENET_HAS_AVB) && FSL_FEATURE_ENET_HAS_AVB + kENET_RgmiiMode = 2U /*!< RGMII mode for data interface. */ +#endif /* FSL_FEATURE_ENET_HAS_AVB */ +} enet_mii_mode_t; + +/*! @brief Defines the 10/100/1000 Mbps speed for the MII data interface. + * + * Notice: "kENET_MiiSpeed1000M" only supported when mii mode is "kENET_RgmiiMode". + */ +typedef enum _enet_mii_speed +{ + kENET_MiiSpeed10M = 0U, /*!< Speed 10 Mbps. */ + kENET_MiiSpeed100M = 1U, /*!< Speed 100 Mbps. */ +#if defined(FSL_FEATURE_ENET_HAS_AVB) && FSL_FEATURE_ENET_HAS_AVB + kENET_MiiSpeed1000M = 2U /*!< Speed 1000M bps. */ +#endif /* FSL_FEATURE_ENET_HAS_AVB */ +} enet_mii_speed_t; + +/*! @brief Defines the half or full duplex for the MII data interface. */ +typedef enum _enet_mii_duplex +{ + kENET_MiiHalfDuplex = 0U, /*!< Half duplex mode. */ + kENET_MiiFullDuplex /*!< Full duplex mode. */ +} enet_mii_duplex_t; + +/*! @brief Define the MII opcode for normal MDIO_CLAUSES_22 Frame. */ +typedef enum _enet_mii_write +{ + kENET_MiiWriteNoCompliant = 0U, /*!< Write frame operation, but not MII-compliant. */ + kENET_MiiWriteValidFrame /*!< Write frame operation for a valid MII management frame. */ +} enet_mii_write_t; + +/*! @brief Defines the read operation for the MII management frame. */ +typedef enum _enet_mii_read +{ + kENET_MiiReadValidFrame = 2U, /*!< Read frame operation for a valid MII management frame. */ + kENET_MiiReadNoCompliant = 3U /*!< Read frame operation, but not MII-compliant. */ +} enet_mii_read_t; + +#if defined(FSL_FEATURE_ENET_HAS_EXTEND_MDIO) && FSL_FEATURE_ENET_HAS_EXTEND_MDIO +/*! @brief Define the MII opcode for extended MDIO_CLAUSES_45 Frame. */ +typedef enum _enet_mii_extend_opcode +{ + kENET_MiiAddrWrite_C45 = 0U, /*!< Address Write operation. */ + kENET_MiiWriteFrame_C45 = 1U, /*!< Write frame operation for a valid MII management frame. */ + kENET_MiiReadFrame_C45 = 3U /*!< Read frame operation for a valid MII management frame. */ +} enet_mii_extend_opcode; +#endif /* FSL_FEATURE_ENET_HAS_EXTEND_MDIO */ + +/*! @brief Defines a special configuration for ENET MAC controller. + * + * These control flags are provided for special user requirements. + * Normally, these control flags are unused for ENET initialization. + * For special requirements, set the flags to + * macSpecialConfig in the enet_config_t. + * The kENET_ControlStoreAndFwdDisable is used to disable the FIFO store + * and forward. FIFO store and forward means that the FIFO read/send is started + * when a complete frame is stored in TX/RX FIFO. If this flag is set, + * configure rxFifoFullThreshold and txFifoWatermark + * in the enet_config_t. + */ +typedef enum _enet_special_control_flag +{ + kENET_ControlFlowControlEnable = 0x0001U, /*!< Enable ENET flow control: pause frame. */ + kENET_ControlRxPayloadCheckEnable = 0x0002U, /*!< Enable ENET receive payload length check. */ + kENET_ControlRxPadRemoveEnable = 0x0004U, /*!< Padding is removed from received frames. */ + kENET_ControlRxBroadCastRejectEnable = 0x0008U, /*!< Enable broadcast frame reject. */ + kENET_ControlMacAddrInsert = 0x0010U, /*!< Enable MAC address insert. */ + kENET_ControlStoreAndFwdDisable = 0x0020U, /*!< Enable FIFO store and forward. */ + kENET_ControlSMIPreambleDisable = 0x0040U, /*!< Enable SMI preamble. */ + kENET_ControlPromiscuousEnable = 0x0080U, /*!< Enable promiscuous mode. */ + kENET_ControlMIILoopEnable = 0x0100U, /*!< Enable ENET MII loop back. */ + kENET_ControlVLANTagEnable = 0x0200U, /*!< Enable normal VLAN (single vlan tag). */ +#if defined(FSL_FEATURE_ENET_HAS_AVB) && FSL_FEATURE_ENET_HAS_AVB + kENET_ControlSVLANEnable = 0x0400U, /*!< Enable S-VLAN. */ + kENET_ControlVLANUseSecondTag = 0x0800U /*!< Enable extracting the second vlan tag for further processing. */ +#endif /* FSL_FEATURE_ENET_HAS_AVB */ +} enet_special_control_flag_t; + +/*! @brief List of interrupts supported by the peripheral. This + * enumeration uses one-bot encoding to allow a logical OR of multiple + * members. Members usually map to interrupt enable bits in one or more + * peripheral registers. + */ +typedef enum _enet_interrupt_enable +{ + kENET_BabrInterrupt = ENET_EIR_BABR_MASK, /*!< Babbling receive error interrupt source */ + kENET_BabtInterrupt = ENET_EIR_BABT_MASK, /*!< Babbling transmit error interrupt source */ + kENET_GraceStopInterrupt = ENET_EIR_GRA_MASK, /*!< Graceful stop complete interrupt source */ + kENET_TxFrameInterrupt = ENET_EIR_TXF_MASK, /*!< TX FRAME interrupt source */ + kENET_TxBufferInterrupt = ENET_EIR_TXB_MASK, /*!< TX BUFFER interrupt source */ + kENET_RxFrameInterrupt = ENET_EIR_RXF_MASK, /*!< RX FRAME interrupt source */ + kENET_RxBufferInterrupt = ENET_EIR_RXB_MASK, /*!< RX BUFFER interrupt source */ + kENET_MiiInterrupt = ENET_EIR_MII_MASK, /*!< MII interrupt source */ + kENET_EBusERInterrupt = ENET_EIR_EBERR_MASK, /*!< Ethernet bus error interrupt source */ + kENET_LateCollisionInterrupt = ENET_EIR_LC_MASK, /*!< Late collision interrupt source */ + kENET_RetryLimitInterrupt = ENET_EIR_RL_MASK, /*!< Collision Retry Limit interrupt source */ + kENET_UnderrunInterrupt = ENET_EIR_UN_MASK, /*!< Transmit FIFO underrun interrupt source */ + kENET_PayloadRxInterrupt = ENET_EIR_PLR_MASK, /*!< Payload Receive error interrupt source */ + kENET_WakeupInterrupt = ENET_EIR_WAKEUP_MASK, /*!< WAKEUP interrupt source */ +#if FSL_FEATURE_ENET_QUEUE > 1 + kENET_RxFlush2Interrupt = ENET_EIR_RXFLUSH_2_MASK, /*!< Rx DMA ring2 flush indication. */ + kENET_RxFlush1Interrupt = ENET_EIR_RXFLUSH_1_MASK, /*!< Rx DMA ring1 flush indication. */ + kENET_RxFlush0Interrupt = ENET_EIR_RXFLUSH_0_MASK, /*!< RX DMA ring0 flush indication. */ + kENET_TxFrame2Interrupt = ENET_EIR_TXF2_MASK, /*!< Tx frame interrupt for Tx ring/class 2. */ + kENET_TxBuffer2Interrupt = ENET_EIR_TXB2_MASK, /*!< Tx buffer interrupt for Tx ring/class 2. */ + kENET_RxFrame2Interrupt = ENET_EIR_RXF2_MASK, /*!< Rx frame interrupt for Rx ring/class 2. */ + kENET_RxBuffer2Interrupt = ENET_EIR_RXB2_MASK, /*!< Rx buffer interrupt for Rx ring/class 2. */ + kENET_TxFrame1Interrupt = ENET_EIR_TXF1_MASK, /*!< Tx frame interrupt for Tx ring/class 1. */ + kENET_TxBuffer1Interrupt = ENET_EIR_TXB1_MASK, /*!< Tx buffer interrupt for Tx ring/class 1. */ + kENET_RxFrame1Interrupt = ENET_EIR_RXF1_MASK, /*!< Rx frame interrupt for Rx ring/class 1. */ + kENET_RxBuffer1Interrupt = ENET_EIR_RXB1_MASK, /*!< Rx buffer interrupt for Rx ring/class 1. */ +#endif /* FSL_FEATURE_ENET_QUEUE > 1 */ + kENET_TsAvailInterrupt = ENET_EIR_TS_AVAIL_MASK, /*!< TS AVAIL interrupt source for PTP */ + kENET_TsTimerInterrupt = ENET_EIR_TS_TIMER_MASK /*!< TS WRAP interrupt source for PTP */ +} enet_interrupt_enable_t; + +/*! @brief Defines the common interrupt event for callback use. */ +typedef enum _enet_event +{ + kENET_RxEvent, /*!< Receive event. */ + kENET_TxEvent, /*!< Transmit event. */ + kENET_ErrEvent, /*!< Error event: BABR/BABT/EBERR/LC/RL/UN/PLR . */ + kENET_WakeUpEvent, /*!< Wake up from sleep mode event. */ + kENET_TimeStampEvent, /*!< Time stamp event. */ + kENET_TimeStampAvailEvent /*!< Time stamp available event.*/ +} enet_event_t; + +#if defined(FSL_FEATURE_ENET_HAS_AVB) && FSL_FEATURE_ENET_HAS_AVB +/*! @brief Defines certain idle slope for bandwidth fraction. */ +typedef enum _enet_idle_slope +{ + kENET_IdleSlope1 = 1U, /*!< The bandwidth fraction is about 0.002. */ + kENET_IdleSlope2 = 2U, /*!< The bandwidth fraction is about 0.003. */ + kENET_IdleSlope4 = 4U, /*!< The bandwidth fraction is about 0.008. */ + kENET_IdleSlope8 = 8U, /*!< The bandwidth fraction is about 0.02. */ + kENET_IdleSlope16 = 16U, /*!< The bandwidth fraction is about 0.03. */ + kENET_IdleSlope32 = 32U, /*!< The bandwidth fraction is about 0.06. */ + kENET_IdleSlope64 = 64U, /*!< The bandwidth fraction is about 0.11. */ + kENET_IdleSlope128 = 128U, /*!< The bandwidth fraction is about 0.20. */ + kENET_IdleSlope256 = 256U, /*!< The bandwidth fraction is about 0.33. */ + kENET_IdleSlope384 = 384U, /*!< The bandwidth fraction is about 0.43. */ + kENET_IdleSlope512 = 512U, /*!< The bandwidth fraction is about 0.50. */ + kENET_IdleSlope640 = 640U, /*!< The bandwidth fraction is about 0.56. */ + kENET_IdleSlope768 = 768U, /*!< The bandwidth fraction is about 0.60. */ + kENET_IdleSlope896 = 896U, /*!< The bandwidth fraction is about 0.64. */ + kENET_IdleSlope1024 = 1024U, /*!< The bandwidth fraction is about 0.67. */ + kENET_IdleSlope1152 = 1152U, /*!< The bandwidth fraction is about 0.69. */ + kENET_IdleSlope1280 = 1280U, /*!< The bandwidth fraction is about 0.71. */ + kENET_IdleSlope1408 = 1408U, /*!< The bandwidth fraction is about 0.73. */ + kENET_IdleSlope1536 = 1536U /*!< The bandwidth fraction is about 0.75. */ +} enet_idle_slope_t; +#endif /* FSL_FEATURE_ENET_HAS_AVB */ + +/*! @brief Defines the transmit accelerator configuration. */ +typedef enum _enet_tx_accelerator +{ + kENET_TxAccelIsShift16Enabled = ENET_TACC_SHIFT16_MASK, /*!< Transmit FIFO shift-16. */ + kENET_TxAccelIpCheckEnabled = ENET_TACC_IPCHK_MASK, /*!< Insert IP header checksum. */ + kENET_TxAccelProtoCheckEnabled = ENET_TACC_PROCHK_MASK /*!< Insert protocol checksum. */ +} enet_tx_accelerator_t; + +/*! @brief Defines the receive accelerator configuration. */ +typedef enum _enet_rx_accelerator +{ + kENET_RxAccelPadRemoveEnabled = ENET_RACC_PADREM_MASK, /*!< Padding removal for short IP frames. */ + kENET_RxAccelIpCheckEnabled = ENET_RACC_IPDIS_MASK, /*!< Discard with wrong IP header checksum. */ + kENET_RxAccelProtoCheckEnabled = ENET_RACC_PRODIS_MASK, /*!< Discard with wrong protocol checksum. */ + kENET_RxAccelMacCheckEnabled = ENET_RACC_LINEDIS_MASK, /*!< Discard with Mac layer errors. */ + kENET_RxAccelisShift16Enabled = ENET_RACC_SHIFT16_MASK /*!< Receive FIFO shift-16. */ +} enet_rx_accelerator_t; + +#ifdef ENET_ENHANCEDBUFFERDESCRIPTOR_MODE +/*! @brief Defines the ENET PTP message related constant. */ +typedef enum _enet_ptp_event_type +{ + kENET_PtpEventMsgType = 3U, /*!< PTP event message type. */ + kENET_PtpSrcPortIdLen = 10U, /*!< PTP message sequence id length. */ + kENET_PtpEventPort = 319U, /*!< PTP event port number. */ + kENET_PtpGnrlPort = 320U /*!< PTP general port number. */ +} enet_ptp_event_type_t; + +/*! @brief Defines the IEEE 1588 PTP timer channel numbers. */ +typedef enum _enet_ptp_timer_channel +{ + kENET_PtpTimerChannel1 = 0U, /*!< IEEE 1588 PTP timer Channel 1. */ + kENET_PtpTimerChannel2, /*!< IEEE 1588 PTP timer Channel 2. */ + kENET_PtpTimerChannel3, /*!< IEEE 1588 PTP timer Channel 3. */ + kENET_PtpTimerChannel4 /*!< IEEE 1588 PTP timer Channel 4. */ +} enet_ptp_timer_channel_t; + +/*! @brief Defines the capture or compare mode for IEEE 1588 PTP timer channels. */ +typedef enum _enet_ptp_timer_channel_mode +{ + kENET_PtpChannelDisable = 0U, /*!< Disable timer channel. */ + kENET_PtpChannelRisingCapture = 1U, /*!< Input capture on rising edge. */ + kENET_PtpChannelFallingCapture = 2U, /*!< Input capture on falling edge. */ + kENET_PtpChannelBothCapture = 3U, /*!< Input capture on both edges. */ + kENET_PtpChannelSoftCompare = 4U, /*!< Output compare software only. */ + kENET_PtpChannelToggleCompare = 5U, /*!< Toggle output on compare. */ + kENET_PtpChannelClearCompare = 6U, /*!< Clear output on compare. */ + kENET_PtpChannelSetCompare = 7U, /*!< Set output on compare. */ + kENET_PtpChannelClearCompareSetOverflow = 10U, /*!< Clear output on compare, set output on overflow. */ + kENET_PtpChannelSetCompareClearOverflow = 11U, /*!< Set output on compare, clear output on overflow. */ + kENET_PtpChannelPulseLowonCompare = 14U, /*!< Pulse output low on compare for one IEEE 1588 clock cycle. */ + kENET_PtpChannelPulseHighonCompare = 15U /*!< Pulse output high on compare for one IEEE 1588 clock cycle. */ +} enet_ptp_timer_channel_mode_t; +#endif /* ENET_ENHANCEDBUFFERDESCRIPTOR_MODE */ + +/*! @brief Defines the receive buffer descriptor structure for the little endian system.*/ +typedef struct _enet_rx_bd_struct +{ + uint16_t length; /*!< Buffer descriptor data length. */ + uint16_t control; /*!< Buffer descriptor control and status. */ + uint8_t *buffer; /*!< Data buffer pointer. */ +#ifdef ENET_ENHANCEDBUFFERDESCRIPTOR_MODE + uint16_t controlExtend0; /*!< Extend buffer descriptor control0. */ + uint16_t controlExtend1; /*!< Extend buffer descriptor control1. */ + uint16_t payloadCheckSum; /*!< Internal payload checksum. */ + uint8_t headerLength; /*!< Header length. */ + uint8_t protocolTyte; /*!< Protocol type. */ + uint16_t reserved0; + uint16_t controlExtend2; /*!< Extend buffer descriptor control2. */ + uint32_t timestamp; /*!< Timestamp. */ + uint16_t reserved1; + uint16_t reserved2; + uint16_t reserved3; + uint16_t reserved4; +#endif /* ENET_ENHANCEDBUFFERDESCRIPTOR_MODE */ +} enet_rx_bd_struct_t; + +/*! @brief Defines the enhanced transmit buffer descriptor structure for the little endian system. */ +typedef struct _enet_tx_bd_struct +{ + uint16_t length; /*!< Buffer descriptor data length. */ + uint16_t control; /*!< Buffer descriptor control and status. */ + uint8_t *buffer; /*!< Data buffer pointer. */ +#ifdef ENET_ENHANCEDBUFFERDESCRIPTOR_MODE + uint16_t controlExtend0; /*!< Extend buffer descriptor control0. */ + uint16_t controlExtend1; /*!< Extend buffer descriptor control1. */ +#if defined(FSL_FEATURE_ENET_HAS_AVB) && FSL_FEATURE_ENET_HAS_AVB + int8_t *txLaunchTime; /*!< Transmit launch time. */ +#else + uint16_t reserved0; + uint16_t reserved1; +#endif /* FSL_FEATURE_ENET_HAS_AVB */ + uint16_t reserved2; + uint16_t controlExtend2; /*!< Extend buffer descriptor control2. */ + uint32_t timestamp; /*!< Timestamp. */ + uint16_t reserved3; + uint16_t reserved4; + uint16_t reserved5; + uint16_t reserved6; +#endif /* ENET_ENHANCEDBUFFERDESCRIPTOR_MODE */ +} enet_tx_bd_struct_t; + +/*! @brief Defines the ENET data error statistics structure. */ +typedef struct _enet_data_error_stats +{ + uint32_t statsRxLenGreaterErr; /*!< Receive length greater than RCR[MAX_FL]. */ + uint32_t statsRxAlignErr; /*!< Receive non-octet alignment/ */ + uint32_t statsRxFcsErr; /*!< Receive CRC error. */ + uint32_t statsRxOverRunErr; /*!< Receive over run. */ + uint32_t statsRxTruncateErr; /*!< Receive truncate. */ +#ifdef ENET_ENHANCEDBUFFERDESCRIPTOR_MODE + uint32_t statsRxProtocolChecksumErr; /*!< Receive protocol checksum error. */ + uint32_t statsRxIpHeadChecksumErr; /*!< Receive IP header checksum error. */ + uint32_t statsRxMacErr; /*!< Receive Mac error. */ + uint32_t statsRxPhyErr; /*!< Receive PHY error. */ + uint32_t statsRxCollisionErr; /*!< Receive collision. */ + uint32_t statsTxErr; /*!< The error happen when transmit the frame. */ + uint32_t statsTxFrameErr; /*!< The transmit frame is error. */ + uint32_t statsTxOverFlowErr; /*!< Transmit overflow. */ + uint32_t statsTxLateCollisionErr; /*!< Transmit late collision. */ + uint32_t statsTxExcessCollisionErr; /*!< Transmit excess collision.*/ + uint32_t statsTxUnderFlowErr; /*!< Transmit under flow error. */ + uint32_t statsTxTsErr; /*!< Transmit time stamp error. */ +#endif /* ENET_ENHANCEDBUFFERDESCRIPTOR_MODE */ +} enet_data_error_stats_t; + +/*! @brief Defines the receive buffer descriptor configuration structure. + * + * Note that for the internal DMA requirements, the buffers have a corresponding alignment requirements. + * 1. The aligned receive and transmit buffer size must be evenly divisible by ENET_BUFF_ALIGNMENT. + * when the data buffers are in cacheable region when cache is enabled, all those size should be + * aligned to the maximum value of "ENET_BUFF_ALIGNMENT" and the cache line size. + * 2. The aligned transmit and receive buffer descriptor start address must be at + * least 64 bit aligned. However, it's recommended to be evenly divisible by ENET_BUFF_ALIGNMENT. + * buffer descriptors should be put in non-cacheable region when cache is enabled. + * 3. The aligned transmit and receive data buffer start address must be evenly divisible by ENET_BUFF_ALIGNMENT. + * Receive buffers should be continuous with the total size equal to "rxBdNumber * rxBuffSizeAlign". + * Transmit buffers should be continuous with the total size equal to "txBdNumber * txBuffSizeAlign". + * when the data buffers are in cacheable region when cache is enabled, all those size should be + * aligned to the maximum value of "ENET_BUFF_ALIGNMENT" and the cache line size. + */ +typedef struct _enet_buffer_config +{ + uint16_t rxBdNumber; /*!< Receive buffer descriptor number. */ + uint16_t txBdNumber; /*!< Transmit buffer descriptor number. */ + uint32_t rxBuffSizeAlign; /*!< Aligned receive data buffer size. */ + uint32_t txBuffSizeAlign; /*!< Aligned transmit data buffer size. */ + volatile enet_rx_bd_struct_t + *rxBdStartAddrAlign; /*!< Aligned receive buffer descriptor start address: should be non-cacheable. */ + volatile enet_tx_bd_struct_t + *txBdStartAddrAlign; /*!< Aligned transmit buffer descriptor start address: should be non-cacheable. */ + uint8_t *rxBufferAlign; /*!< Receive data buffer start address. */ + uint8_t *txBufferAlign; /*!< Transmit data buffer start address. */ +} enet_buffer_config_t; + +#ifdef ENET_ENHANCEDBUFFERDESCRIPTOR_MODE +/*! @brief Defines the ENET PTP time stamp structure. */ +typedef struct _enet_ptp_time +{ + uint64_t second; /*!< Second. */ + uint32_t nanosecond; /*!< Nanosecond. */ +} enet_ptp_time_t; + +/*! @brief Defines the structure for the ENET PTP message data and timestamp data.*/ +typedef struct _enet_ptp_time_data +{ + uint8_t version; /*!< PTP version. */ + uint8_t sourcePortId[kENET_PtpSrcPortIdLen]; /*!< PTP source port ID. */ + uint16_t sequenceId; /*!< PTP sequence ID. */ + uint8_t messageType; /*!< PTP message type. */ + enet_ptp_time_t timeStamp; /*!< PTP timestamp. */ +} enet_ptp_time_data_t; + +/*! @brief Defines the ENET PTP ring buffer structure for the PTP message timestamp store.*/ +typedef struct _enet_ptp_time_data_ring +{ + uint32_t front; /*!< The first index of the ring. */ + uint32_t end; /*!< The end index of the ring. */ + uint32_t size; /*!< The size of the ring. */ + enet_ptp_time_data_t *ptpTsData; /*!< PTP message data structure. */ +} enet_ptp_time_data_ring_t; + +/*! @brief Defines the ENET PTP configuration structure. */ +typedef struct _enet_ptp_config +{ + uint8_t ptpTsRxBuffNum; /*!< Receive 1588 timestamp buffer number*/ + uint8_t ptpTsTxBuffNum; /*!< Transmit 1588 timestamp buffer number*/ + enet_ptp_time_data_t *rxPtpTsData; /*!< The start address of 1588 receive timestamp buffers */ + enet_ptp_time_data_t *txPtpTsData; /*!< The start address of 1588 transmit timestamp buffers */ + enet_ptp_timer_channel_t channel; /*!< Used for ERRATA_2579: the PTP 1588 timer channel for time interrupt. */ + uint32_t ptp1588ClockSrc_Hz; /*!< The clock source of the PTP 1588 timer. */ +} enet_ptp_config_t; +#endif /* ENET_ENHANCEDBUFFERDESCRIPTOR_MODE */ + +#if defined(FSL_FEATURE_ENET_HAS_INTERRUPT_COALESCE) && FSL_FEATURE_ENET_HAS_INTERRUPT_COALESCE +/*! @brief Defines the interrupt coalescing configure structure. */ +typedef struct _enet_intcoalesce_config +{ + uint8_t txCoalesceFrameCount[FSL_FEATURE_ENET_QUEUE]; /*!< Transmit interrupt coalescing frame count threshold. */ + uint16_t txCoalesceTimeCount[FSL_FEATURE_ENET_QUEUE]; /*!< Transmit interrupt coalescing timer count threshold. */ + uint8_t rxCoalesceFrameCount[FSL_FEATURE_ENET_QUEUE]; /*!< Receive interrupt coalescing frame count threshold. */ + uint16_t rxCoalesceTimeCount[FSL_FEATURE_ENET_QUEUE]; /*!< Receive interrupt coalescing timer count threshold. */ +} enet_intcoalesce_config_t; +#endif /* FSL_FEATURE_ENET_HAS_INTERRUPT_COALESCE */ + +#if defined(FSL_FEATURE_ENET_HAS_AVB) && FSL_FEATURE_ENET_HAS_AVB +/*! @brief Defines the ENET AVB Configure structure. + * + * This is used for to configure the extended ring 1 and ring 2. + * 1. The classification match format is (CMP3 << 12) | (CMP2 << 8) | (CMP1 << 4) | CMP0. + * composed of four 3-bit compared VLAN priority field cmp0~cmp3, cm0 ~ cmp3 are used in parallel. + * + * If CMP1,2,3 are not unused, please set them to the same value as CMP0. + * 2. The idleSlope is used to calculate the Band Width fraction, BW fraction = 1 / (1 + 512/idleSlope). + * For avb configuration, the BW fraction of Class 1 and Class 2 combined must not exceed 0.75. + */ +typedef struct _enet_avb_config +{ + uint16_t rxClassifyMatch[FSL_FEATURE_ENET_QUEUE - 1]; /*!< The classification match value for the ring. */ + enet_idle_slope_t idleSlope[FSL_FEATURE_ENET_QUEUE - 1]; /*!< The idle slope for certian bandwidth fraction. */ +} enet_avb_config_t; +#endif /* FSL_FEATURE_ENET_HAS_AVB */ + +/*! @brief Defines the basic configuration structure for the ENET device. + * + * Note: + * 1. macSpecialConfig is used for a special control configuration, A logical OR of + * "enet_special_control_flag_t". For a special configuration for MAC, + * set this parameter to 0. + * 2. txWatermark is used for a cut-through operation. It is in steps of 64 bytes: + * 0/1 - 64 bytes written to TX FIFO before transmission of a frame begins. + * 2 - 128 bytes written to TX FIFO .... + * 3 - 192 bytes written to TX FIFO .... + * The maximum of txWatermark is 0x2F - 4032 bytes written to TX FIFO .... + * txWatermark allows minimizing the transmit latency to set the txWatermark to 0 or 1 + * or for larger bus access latency 3 or larger due to contention for the system bus. + * 3. rxFifoFullThreshold is similar to the txWatermark for cut-through operation in RX. + * It is in 64-bit words. The minimum is ENET_FIFO_MIN_RX_FULL and the maximum is 0xFF. + * If the end of the frame is stored in FIFO and the frame size if smaller than the + * txWatermark, the frame is still transmitted. The rule is the + * same for rxFifoFullThreshold in the receive direction. + * 4. When "kENET_ControlFlowControlEnable" is set in the macSpecialConfig, ensure + * that the pauseDuration, rxFifoEmptyThreshold, and rxFifoStatEmptyThreshold + * are set for flow control enabled case. + * 5. When "kENET_ControlStoreAndFwdDisabled" is set in the macSpecialConfig, ensure + * that the rxFifoFullThreshold and txFifoWatermark are set for store and forward disable. + * 6. The rxAccelerConfig and txAccelerConfig default setting with 0 - accelerator + * are disabled. The "enet_tx_accelerator_t" and "enet_rx_accelerator_t" are + * recommended to be used to enable the transmit and receive accelerator. + * After the accelerators are enabled, the store and forward feature should be enabled. + * As a result, kENET_ControlStoreAndFwdDisabled should not be set. + * 7. The intCoalesceCfg can be used in the rx or tx enabled cases to decrese the CPU loading. + */ +typedef struct _enet_config +{ + uint32_t macSpecialConfig; /*!< Mac special configuration. A logical OR of "enet_special_control_flag_t". */ + uint32_t interrupt; /*!< Mac interrupt source. A logical OR of "enet_interrupt_enable_t". */ + uint16_t rxMaxFrameLen; /*!< Receive maximum frame length. */ + enet_mii_mode_t miiMode; /*!< MII mode. */ + enet_mii_speed_t miiSpeed; /*!< MII Speed. */ + enet_mii_duplex_t miiDuplex; /*!< MII duplex. */ + uint8_t rxAccelerConfig; /*!< Receive accelerator, A logical OR of "enet_rx_accelerator_t". */ + uint8_t txAccelerConfig; /*!< Transmit accelerator, A logical OR of "enet_rx_accelerator_t". */ + uint16_t pauseDuration; /*!< For flow control enabled case: Pause duration. */ + uint8_t rxFifoEmptyThreshold; /*!< For flow control enabled case: when RX FIFO level reaches this value, + it makes MAC generate XOFF pause frame. */ +#if defined(FSL_FEATURE_ENET_HAS_RECEIVE_STATUS_THRESHOLD) && FSL_FEATURE_ENET_HAS_RECEIVE_STATUS_THRESHOLD + uint8_t rxFifoStatEmptyThreshold; /*!< For flow control enabled case: number of frames in the receive FIFO, + independent of size, that can be accept. If the limit is reached, reception + continues and a pause frame is triggered. */ +#endif /* FSL_FEATURE_ENET_HAS_RECEIVE_STATUS_THRESHOLD */ + uint8_t rxFifoFullThreshold; /*!< For store and forward disable case, the data required in RX FIFO to notify + the MAC receive ready status. */ + uint8_t txFifoWatermark; /*!< For store and forward disable case, the data required in TX FIFO + before a frame transmit start. */ +#if defined(FSL_FEATURE_ENET_HAS_INTERRUPT_COALESCE) && FSL_FEATURE_ENET_HAS_INTERRUPT_COALESCE + enet_intcoalesce_config_t *intCoalesceCfg; /* If the interrupt coalsecence is not required in the ring n(0,1,2), + please set to NULL. */ +#endif /* FSL_FEATURE_ENET_HAS_INTERRUPT_COALESCE */ + uint8_t ringNum; /*!< Number of used rings. default with 1 -- single ring. */ +} enet_config_t; + +/* Forward declaration of the handle typedef. */ +typedef struct _enet_handle enet_handle_t; + +/*! @brief ENET callback function. */ +#if FSL_FEATURE_ENET_QUEUE > 1 +typedef void (*enet_callback_t)( + ENET_Type *base, enet_handle_t *handle, uint32_t ringId, enet_event_t event, void *userData); +#else +typedef void (*enet_callback_t)(ENET_Type *base, enet_handle_t *handle, enet_event_t event, void *userData); +#endif /* FSL_FEATURE_ENET_QUEUE > 1 */ + +/*! @brief Defines the ENET handler structure. */ +struct _enet_handle +{ + volatile enet_rx_bd_struct_t + *rxBdBase[FSL_FEATURE_ENET_QUEUE]; /*!< Receive buffer descriptor base address pointer. */ + volatile enet_rx_bd_struct_t + *rxBdCurrent[FSL_FEATURE_ENET_QUEUE]; /*!< The current available receive buffer descriptor pointer. */ + volatile enet_tx_bd_struct_t + *txBdBase[FSL_FEATURE_ENET_QUEUE]; /*!< Transmit buffer descriptor base address pointer. */ + volatile enet_tx_bd_struct_t + *txBdCurrent[FSL_FEATURE_ENET_QUEUE]; /*!< The current available transmit buffer descriptor pointer. */ + uint32_t rxBuffSizeAlign[FSL_FEATURE_ENET_QUEUE]; /*!< Receive buffer size alignment. */ + uint32_t txBuffSizeAlign[FSL_FEATURE_ENET_QUEUE]; /*!< Transmit buffer size alignment. */ + uint8_t ringNum; /*!< Number of used rings. */ + enet_callback_t callback; /*!< Callback function. */ + void *userData; /*!< Callback function parameter.*/ +#ifdef ENET_ENHANCEDBUFFERDESCRIPTOR_MODE + volatile enet_tx_bd_struct_t + *txBdDirtyStatic[FSL_FEATURE_ENET_QUEUE]; /*!< The dirty transmit buffer descriptor for error static update. */ + volatile enet_tx_bd_struct_t + *txBdDirtyTime[FSL_FEATURE_ENET_QUEUE]; /*!< The dirty transmit buffer descriptor for time stamp update. */ + uint64_t msTimerSecond; /*!< The second for Master PTP timer .*/ + enet_ptp_time_data_ring_t rxPtpTsDataRing; /*!< Receive PTP 1588 time stamp data ring buffer. */ + enet_ptp_time_data_ring_t txPtpTsDataRing; /*!< Transmit PTP 1588 time stamp data ring buffer. */ +#endif /* ENET_ENHANCEDBUFFERDESCRIPTOR_MODE */ +}; + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @name Initialization and De-initialization + * @{ + */ + +/*! + * @brief Gets the ENET default configuration structure. + * + * The purpose of this API is to get the default ENET MAC controller + * configure structure for ENET_Init(). User may use the initialized + * structure unchanged in ENET_Init(), or modify some fields of the + * structure before calling ENET_Init(). + * Example: + @code + enet_config_t config; + ENET_GetDefaultConfig(&config); + @endcode + * @param config The ENET mac controller configuration structure pointer. + */ +void ENET_GetDefaultConfig(enet_config_t *config); + +/*! + * @brief Initializes the ENET module. + * + * This function ungates the module clock and initializes it with the ENET configuration. + * + * @param base ENET peripheral base address. + * @param handle ENET handler pointer. + * @param config ENET mac configuration structure pointer. + * The "enet_config_t" type mac configuration return from ENET_GetDefaultConfig + * can be used directly. It is also possible to verify the Mac configuration using other methods. + * @param bufferConfig ENET buffer configuration structure pointer. + * The buffer configuration should be prepared for ENET Initialization. + * It is the start address of "ringNum" enet_buffer_config structures. + * To support added multi-ring features in some soc and compatible with the previous + * enet driver version. For single ring supported, this bufferConfig is a buffer + * configure structure pointer, for multi-ring supported and used case, this bufferConfig + * pointer should be a buffer configure structure array pointer. + * @param macAddr ENET mac address of Ethernet device. This MAC address should be + * provided. + * @param srcClock_Hz The internal module clock source for MII clock. + * + * @note ENET has two buffer descriptors legacy buffer descriptors and + * enhanced IEEE 1588 buffer descriptors. The legacy descriptor is used by default. To + * use the IEEE 1588 feature, use the enhanced IEEE 1588 buffer descriptor + * by defining "ENET_ENHANCEDBUFFERDESCRIPTOR_MODE" and calling ENET_Ptp1588Configure() + * to configure the 1588 feature and related buffers after calling ENET_Init(). + */ +void ENET_Init(ENET_Type *base, + enet_handle_t *handle, + const enet_config_t *config, + const enet_buffer_config_t *bufferConfig, + uint8_t *macAddr, + uint32_t srcClock_Hz); +/*! + * @brief Deinitializes the ENET module. + + * This function gates the module clock, clears ENET interrupts, and disables the ENET module. + * + * @param base ENET peripheral base address. + */ +void ENET_Deinit(ENET_Type *base); + +/*! + * @brief Resets the ENET module. + * + * This function restores the ENET module to reset state. + * Note that this function sets all registers to + * reset state. As a result, the ENET module can't work after calling this function. + * + * @param base ENET peripheral base address. + */ +static inline void ENET_Reset(ENET_Type *base) +{ + base->ECR |= ENET_ECR_RESET_MASK; +} + +/* @} */ + +/*! + * @name MII interface operation + * @{ + */ + +/*! + * @brief Sets the ENET MII speed and duplex. + * + * This API is provided to dynamically change the speed and dulpex for MAC. + * + * @param base ENET peripheral base address. + * @param speed The speed of the RMII mode. + * @param duplex The duplex of the RMII mode. + */ +void ENET_SetMII(ENET_Type *base, enet_mii_speed_t speed, enet_mii_duplex_t duplex); + +/*! + * @brief Sets the ENET SMI(serial management interface)- MII management interface. + * + * @param base ENET peripheral base address. + * @param srcClock_Hz This is the ENET module clock frequency. Normally it's the system clock. See clock distribution. + * @param isPreambleDisabled The preamble disable flag. + * - true Enables the preamble. + * - false Disables the preamble. + */ +void ENET_SetSMI(ENET_Type *base, uint32_t srcClock_Hz, bool isPreambleDisabled); + +/*! + * @brief Gets the ENET SMI- MII management interface configuration. + * + * This API is used to get the SMI configuration to check whether the MII management + * interface has been set. + * + * @param base ENET peripheral base address. + * @return The SMI setup status true or false. + */ +static inline bool ENET_GetSMI(ENET_Type *base) +{ + return (0 != (base->MSCR & 0x7E)); +} + +/*! + * @brief Reads data from the PHY register through an SMI interface. + * + * @param base ENET peripheral base address. + * @return The data read from PHY + */ +static inline uint32_t ENET_ReadSMIData(ENET_Type *base) +{ + return (uint32_t)((base->MMFR & ENET_MMFR_DATA_MASK) >> ENET_MMFR_DATA_SHIFT); +} + +/*! + * @brief Starts an SMI (Serial Management Interface) read command. + * + * Used for standard IEEE802.3 MDIO Clause 22 format. + * + * @param base ENET peripheral base address. + * @param phyAddr The PHY address. + * @param phyReg The PHY register. Range from 0 ~ 31. + * @param operation The read operation. + */ +void ENET_StartSMIRead(ENET_Type *base, uint32_t phyAddr, uint32_t phyReg, enet_mii_read_t operation); + +/*! + * @brief Starts an SMI write command. + * + * Used for standard IEEE802.3 MDIO Clause 22 format. + * + * @param base ENET peripheral base address. + * @param phyAddr The PHY address. + * @param phyReg The PHY register. Range from 0 ~ 31. + * @param operation The write operation. + * @param data The data written to PHY. + */ +void ENET_StartSMIWrite(ENET_Type *base, uint32_t phyAddr, uint32_t phyReg, enet_mii_write_t operation, uint32_t data); + +#if defined(FSL_FEATURE_ENET_HAS_EXTEND_MDIO) && FSL_FEATURE_ENET_HAS_EXTEND_MDIO +/*! + * @brief Starts the extended IEEE802.3 Clause 45 MDIO format SMI read command. + * + * @param base ENET peripheral base address. + * @param phyAddr The PHY address. + * @param phyReg The PHY register. For MDIO IEEE802.3 Clause 45, + * the phyReg is a 21-bits combination of the devaddr (5 bits device address) + * and the regAddr (16 bits phy register): phyReg = (devaddr << 16) | regAddr. + */ +void ENET_StartExtC45SMIRead(ENET_Type *base, uint32_t phyAddr, uint32_t phyReg); + +/*! + * @brief Starts the extended IEEE802.3 Clause 45 MDIO format SMI write command. + * + * @param base ENET peripheral base address. + * @param phyAddr The PHY address. + * @param phyReg The PHY register. For MDIO IEEE802.3 Clause 45, + * the phyReg is a 21-bits combination of the devaddr (5 bits device address) + * and the regAddr (16 bits phy register): phyReg = (devaddr << 16) | regAddr. + * @param data The data written to PHY. + */ +void ENET_StartExtC45SMIWrite(ENET_Type *base, uint32_t phyAddr, uint32_t phyReg, uint32_t data); +#endif /* FSL_FEATURE_ENET_HAS_EXTEND_MDIO */ + +#if defined(FSL_FEATURE_ENET_HAS_AVB) && FSL_FEATURE_ENET_HAS_AVB +/*! + * @brief Control the usage of the delayed tx/rx RGMII clock. + * + * @param base ENET peripheral base address. + * @param txEnabled Enable or disable to generate the delayed version of RGMII_TXC. + * @param rxEnabled Enable or disable to use the delayed version of RGMII_RXC. + */ + +static inline void ENET_SetRGMIIClockDelay(ENET_Type *base, bool txEnabled, bool rxEnabled) +{ + uint32_t ecrReg = base->ECR; + + /* Set for transmit clock delay. */ + if (txEnabled) + { + ecrReg |= ENET_ECR_TXC_DLY_MASK; + } + else + { + ecrReg &= ~ENET_ECR_TXC_DLY_MASK; + } + + /* Set for receive clock delay. */ + if (rxEnabled) + { + ecrReg |= ENET_ECR_RXC_DLY_MASK; + } + else + { + ecrReg &= ~ENET_ECR_RXC_DLY_MASK; + } +} +#endif /* FSL_FEATURE_ENET_HAS_AVB */ + /* @} */ + +/*! + * @name MAC Address Filter + * @{ + */ + +/*! + * @brief Sets the ENET module Mac address. + * + * @param base ENET peripheral base address. + * @param macAddr The six-byte Mac address pointer. + * The pointer is allocated by application and input into the API. + */ +void ENET_SetMacAddr(ENET_Type *base, uint8_t *macAddr); + +/*! + * @brief Gets the ENET module Mac address. + * + * @param base ENET peripheral base address. + * @param macAddr The six-byte Mac address pointer. + * The pointer is allocated by application and input into the API. + */ +void ENET_GetMacAddr(ENET_Type *base, uint8_t *macAddr); + +/*! + * @brief Adds the ENET device to a multicast group. + * + * @param base ENET peripheral base address. + * @param address The six-byte multicast group address which is provided by application. + */ +void ENET_AddMulticastGroup(ENET_Type *base, uint8_t *address); + +/*! + * @brief Moves the ENET device from a multicast group. + * + * @param base ENET peripheral base address. + * @param address The six-byte multicast group address which is provided by application. + */ +void ENET_LeaveMulticastGroup(ENET_Type *base, uint8_t *address); + +/* @} */ + +/*! + * @name Other basic operation + * @{ + */ + +#ifdef ENET_ENHANCEDBUFFERDESCRIPTOR_MODE +#if defined(FSL_FEATURE_ENET_HAS_AVB) && FSL_FEATURE_ENET_HAS_AVB +/*! + * @brief Sets the ENET AVB feature. + * + * ENET AVB feature configuration, set the Receive classification match and transmit + * bandwidth. This API is called when the AVB feature is required. + * + * Note: The AVB frames transmission scheme is credit-based tx scheme and it's only supported + * with the Enhanced buffer descriptors. so the AVB configuration should only done with + * Enhanced buffer descriptor. so when the AVB feature is required, please make sure the + * the "ENET_ENHANCEDBUFFERDESCRIPTOR_MODE" is defined. + * + * @param base ENET peripheral base address. + * @param handle ENET handler pointer. + * @param config The ENET AVB feature configuration structure. + */ +void ENET_AVBConfigure(ENET_Type *base, enet_handle_t *handle, const enet_avb_config_t *config); +#endif /* FSL_FEATURE_ENET_HAS_AVB */ +#endif /* ENET_ENHANCEDBUFFERDESCRIPTOR_MODE */ + +/*! + * @brief Activates ENET read or receive. + * + * This function is to active the enet read process. It is + * used for single descriptor ring/queue. + * + * @param base ENET peripheral base address. + * + * @note This must be called after the MAC configuration and + * state are ready. It must be called after the ENET_Init() and + * ENET_Ptp1588Configure(). This should be called when the ENET receive required. + */ +static inline void ENET_ActiveRead(ENET_Type *base) +{ + base->RDAR = ENET_RDAR_RDAR_MASK; +} + +#if FSL_FEATURE_ENET_QUEUE > 1 +/*! + * @brief Activates ENET read or receive for multiple-queue/ring. + * + * This function is to active the enet read process. It is + * used for extended multiple descriptor rings/queues. + * + * @param base ENET peripheral base address. + * + * @note This must be called after the MAC configuration and + * state are ready. It must be called after the ENET_Init() and + * ENET_Ptp1588Configure(). This should be called when the ENET receive required. + */ +static inline void ENET_ActiveReadMultiRing(ENET_Type *base) +{ + base->RDAR = ENET_RDAR_RDAR_MASK; + base->RDAR1 = ENET_RDAR1_RDAR_MASK; + base->RDAR2 = ENET_RDAR2_RDAR_MASK; +} +#endif /* FSL_FEATURE_ENET_QUEUE > 1 */ + +/*! + * @brief Enables/disables the MAC to enter sleep mode. + * This function is used to set the MAC enter sleep mode. + * When entering sleep mode, the magic frame wakeup interrupt should be enabled + * to wake up MAC from the sleep mode and reset it to normal mode. + * + * @param base ENET peripheral base address. + * @param enable True enable sleep mode, false disable sleep mode. + */ +static inline void ENET_EnableSleepMode(ENET_Type *base, bool enable) +{ + if (enable) + { + /* When this field is set, MAC enters sleep mode. */ + base->ECR |= ENET_ECR_SLEEP_MASK | ENET_ECR_MAGICEN_MASK; + } + else + { /* MAC exits sleep mode. */ + base->ECR &= ~(ENET_ECR_SLEEP_MASK | ENET_ECR_MAGICEN_MASK); + } +} + +/*! + * @brief Gets ENET transmit and receive accelerator functions from MAC controller. + * + * @param base ENET peripheral base address. + * @param txAccelOption The transmit accelerator option. The "enet_tx_accelerator_t" is + * recommended to be used to as the mask to get the exact the accelerator option. + * @param rxAccelOption The receive accelerator option. The "enet_rx_accelerator_t" is + * recommended to be used to as the mask to get the exact the accelerator option. + */ +static inline void ENET_GetAccelFunction(ENET_Type *base, uint32_t *txAccelOption, uint32_t *rxAccelOption) +{ + assert(txAccelOption); + assert(txAccelOption); + + *txAccelOption = base->TACC; + *rxAccelOption = base->RACC; +} + +/* @} */ + +/*! + * @name Interrupts. + * @{ + */ + +/*! + * @brief Enables the ENET interrupt. + * + * This function enables the ENET interrupt according to the provided mask. The mask + * is a logical OR of enumeration members. See @ref enet_interrupt_enable_t. + * For example, to enable the TX frame interrupt and RX frame interrupt, do the following. + * @code + * ENET_EnableInterrupts(ENET, kENET_TxFrameInterrupt | kENET_RxFrameInterrupt); + * @endcode + * + * @param base ENET peripheral base address. + * @param mask ENET interrupts to enable. This is a logical OR of the + * enumeration :: enet_interrupt_enable_t. + */ +static inline void ENET_EnableInterrupts(ENET_Type *base, uint32_t mask) +{ + base->EIMR |= mask; +} + +/*! + * @brief Disables the ENET interrupt. + * + * This function disables the ENET interrupts according to the provided mask. The mask + * is a logical OR of enumeration members. See @ref enet_interrupt_enable_t. + * For example, to disable the TX frame interrupt and RX frame interrupt, do the following. + * @code + * ENET_DisableInterrupts(ENET, kENET_TxFrameInterrupt | kENET_RxFrameInterrupt); + * @endcode + * + * @param base ENET peripheral base address. + * @param mask ENET interrupts to disable. This is a logical OR of the + * enumeration :: enet_interrupt_enable_t. + */ +static inline void ENET_DisableInterrupts(ENET_Type *base, uint32_t mask) +{ + base->EIMR &= ~mask; +} + +/*! + * @brief Gets the ENET interrupt status flag. + * + * @param base ENET peripheral base address. + * @return The event status of the interrupt source. This is the logical OR of members + * of the enumeration :: enet_interrupt_enable_t. + */ +static inline uint32_t ENET_GetInterruptStatus(ENET_Type *base) +{ + return base->EIR; +} + +/*! + * @brief Clears the ENET interrupt events status flag. + * + * This function clears enabled ENET interrupts according to the provided mask. The mask + * is a logical OR of enumeration members. See the @ref enet_interrupt_enable_t. + * For example, to clear the TX frame interrupt and RX frame interrupt, do the following. + * @code + * ENET_ClearInterruptStatus(ENET, kENET_TxFrameInterrupt | kENET_RxFrameInterrupt); + * @endcode + * + * @param base ENET peripheral base address. + * @param mask ENET interrupt source to be cleared. + * This is the logical OR of members of the enumeration :: enet_interrupt_enable_t. + */ +static inline void ENET_ClearInterruptStatus(ENET_Type *base, uint32_t mask) +{ + base->EIR = mask; +} +/* @} */ + +/*! + * @name Transactional operation + * @{ + */ + +/*! + * @brief Sets the callback function. + * This API is provided for the application callback required case when ENET + * interrupt is enabled. This API should be called after calling ENET_Init. + * + * @param handle ENET handler pointer. Should be provided by application. + * @param callback The ENET callback function. + * @param userData The callback function parameter. + */ +void ENET_SetCallback(enet_handle_t *handle, enet_callback_t callback, void *userData); + +/*! + * @brief Gets the error statistics of a received frame for ENET single ring. + * + * This API must be called after the ENET_GetRxFrameSize and before the ENET_ReadFrame(). + * If the ENET_GetRxFrameSize returns kStatus_ENET_RxFrameError, + * the ENET_GetRxErrBeforeReadFrame can be used to get the exact error statistics. + * This is an example. + * @code + * status = ENET_GetRxFrameSize(&g_handle, &length); + * if (status == kStatus_ENET_RxFrameError) + * { + * // Get the error information of the received frame. + * ENET_GetRxErrBeforeReadFrame(&g_handle, &eErrStatic); + * // update the receive buffer. + * ENET_ReadFrame(EXAMPLE_ENET, &g_handle, NULL, 0); + * } + * @endcode + * @param handle The ENET handler structure pointer. This is the same handler pointer used in the ENET_Init. + * @param eErrorStatic The error statistics structure pointer. + */ +void ENET_GetRxErrBeforeReadFrame(enet_handle_t *handle, enet_data_error_stats_t *eErrorStatic); + +#ifdef ENET_ENHANCEDBUFFERDESCRIPTOR_MODE +/*! + * @brief Gets the ENET transmit frame statistics after the data send for single ring. + * + * This interface gets the error statistics of the transmit frame. + * Because the error information is reported by the uDMA after the data delivery, this interface + * should be called after the data transmit API. It is recommended to call this function on + * transmit interrupt handler. After calling the ENET_SendFrame, the + * transmit interrupt notifies the transmit completion. + * + * @param handle The PTP handler pointer. This is the same handler pointer used in the ENET_Init. + * @param eErrorStatic The error statistics structure pointer. + * @return The execute status. + */ +status_t ENET_GetTxErrAfterSendFrame(enet_handle_t *handle, enet_data_error_stats_t *eErrorStatic); +#endif /* ENET_ENHANCEDBUFFERDESCRIPTOR_MODE */ + +/*! + * @brief Gets the size of the read frame for single ring. + * + * This function gets a received frame size from the ENET buffer descriptors. + * @note The FCS of the frame is automatically removed by MAC and the size is the length without the FCS. + * After calling ENET_GetRxFrameSize, ENET_ReadFrame() should be called to update the + * receive buffers If the result is not "kStatus_ENET_RxFrameEmpty". + * + * @param handle The ENET handler structure. This is the same handler pointer used in the ENET_Init. + * @param length The length of the valid frame received. + * @retval kStatus_ENET_RxFrameEmpty No frame received. Should not call ENET_ReadFrame to read frame. + * @retval kStatus_ENET_RxFrameError Data error happens. ENET_ReadFrame should be called with NULL data + * and NULL length to update the receive buffers. + * @retval kStatus_Success Receive a frame Successfully then the ENET_ReadFrame + * should be called with the right data buffer and the captured data length input. + */ +status_t ENET_GetRxFrameSize(enet_handle_t *handle, uint32_t *length); + +/*! + * @brief Reads a frame from the ENET device for single ring. + * This function reads a frame (both the data and the length) from the ENET buffer descriptors. + * The ENET_GetRxFrameSize should be used to get the size of the prepared data buffer. + * This is an example: + * @code + * uint32_t length; + * enet_handle_t g_handle; + * //Get the received frame size firstly. + * status = ENET_GetRxFrameSize(&g_handle, &length); + * if (length != 0) + * { + * //Allocate memory here with the size of "length" + * uint8_t *data = memory allocate interface; + * if (!data) + * { + * ENET_ReadFrame(ENET, &g_handle, NULL, 0); + * //Add the console warning log. + * } + * else + * { + * status = ENET_ReadFrame(ENET, &g_handle, data, length); + * //Call stack input API to deliver the data to stack + * } + * } + * else if (status == kStatus_ENET_RxFrameError) + * { + * //Update the received buffer when a error frame is received. + * ENET_ReadFrame(ENET, &g_handle, NULL, 0); + * } + * @endcode + * @param base ENET peripheral base address. + * @param handle The ENET handler structure. This is the same handler pointer used in the ENET_Init. + * @param data The data buffer provided by user to store the frame which memory size should be at least "length". + * @param length The size of the data buffer which is still the length of the received frame. + * @return The execute status, successful or failure. + */ +status_t ENET_ReadFrame(ENET_Type *base, enet_handle_t *handle, uint8_t *data, uint32_t length); + +/*! + * @brief Transmits an ENET frame for single ring. + * @note The CRC is automatically appended to the data. Input the data + * to send without the CRC. + * + * + * @param base ENET peripheral base address. + * @param handle The ENET handler pointer. This is the same handler pointer used in the ENET_Init. + * @param data The data buffer provided by user to be send. + * @param length The length of the data to be send. + * @retval kStatus_Success Send frame succeed. + * @retval kStatus_ENET_TxFrameBusy Transmit buffer descriptor is busy under transmission. + * The transmit busy happens when the data send rate is over the MAC capacity. + * The waiting mechanism is recommended to be added after each call return with + * kStatus_ENET_TxFrameBusy. + */ +status_t ENET_SendFrame(ENET_Type *base, enet_handle_t *handle, const uint8_t *data, uint32_t length); + +#if FSL_FEATURE_ENET_QUEUE > 1 +/*! + * @brief Gets the error statistics of received frame for extended multi-ring. + * + * This API must be called after the ENET_GetRxFrameSizeMultiRing and before the ENET_ReadFrameMultiRing(). + * If the ENET_GetRxFrameSizeMultiRing returns kStatus_ENET_RxFrameError, + * the ENET_GetRxErrBeforeReadFrameMultiRing can be used to get the exact error statistics. + * + * @param handle The ENET handler structure pointer. This is the same handler pointer used in the ENET_Init. + * @param eErrorStatic The error statistics structure pointer. + * @param ringId The ring index, range from 0 ~ FSL_FEATURE_ENET_QUEUE - 1. + */ +void ENET_GetRxErrBeforeReadFrameMultiRing(enet_handle_t *handle, + enet_data_error_stats_t *eErrorStatic, + uint32_t ringId); + +/*! + * @brief Transmits an ENET frame for extended multi-ring. + * @note The CRC is automatically appended to the data. Input the data + * to send without the CRC. + * + * In this API, multiple-ring are mainly used for extended avb frames are supported. + * The transmit scheme for avb frames is the credit-based scheme, the AVB class A, AVB class B + * and the non-AVB frame are transmitted in ring 1, ring 2 and ring 0 independently. + * So application should care about the transmit ring index when use multiple-ring transmission. + * + * @param base ENET peripheral base address. + * @param handle The ENET handler pointer. This is the same handler pointer used in the ENET_Init. + * @param data The data buffer provided by user to be send. + * @param length The length of the data to be send. + * @param ringId The ring index for transmission. + * @retval kStatus_Success Send frame succeed. + * @retval kStatus_ENET_TxFrameBusy Transmit buffer descriptor is busy under transmission. + * The transmit busy happens when the data send rate is over the MAC capacity. + * The waiting mechanism is recommended to be added after each call return with + * kStatus_ENET_TxFrameBusy. + */ +status_t ENET_SendFrameMultiRing( + ENET_Type *base, enet_handle_t *handle, uint8_t *data, uint32_t length, uint32_t ringId); + +#ifdef ENET_ENHANCEDBUFFERDESCRIPTOR_MODE +/*! + * @brief Gets the ENET transmit frame statistics after the data send for extended multi-ring. + * + * This interface gets the error statistics of the transmit frame. + * Because the error information is reported by the uDMA after the data delivery, this interface + * should be called after the data transmit API and shall be called by transmit interrupt handler. + * After calling the ENET_SendFrame, the transmit interrupt notifies the transmit completion. + * + * @param handle The PTP handler pointer. This is the same handler pointer used in the ENET_Init. + * @param eErrorStatic The error statistics structure pointer. + * @param ringId The ring index. + * @return The execute status. + */ +status_t ENET_GetTxErrAfterSendFrameMultiRing(enet_handle_t *handle, + enet_data_error_stats_t *eErrorStatic, + uint32_t ringId); +#endif /* ENET_ENHANCEDBUFFERDESCRIPTOR_MODE */ + +/*! + * @brief Gets the size of the read frame for extended mutli-ring. + * + * This function gets a received frame size from the ENET buffer descriptors. + * @note The FCS of the frame is automatically removed by MAC and the size is the length without the FCS. + * After calling ENET_GetRxFrameSizeMultiRing, ENET_ReadFrameMultiRing() should be called to update the + * receive buffers If the result is not "kStatus_ENET_RxFrameEmpty". The usage is + * the same to the single ring, refer to ENET_GetRxFrameSize. + * + * @param handle The ENET handler structure. This is the same handler pointer used in the ENET_Init. + * @param length The length of the valid frame received. + * @param ringId The ring index or ring number; + * @retval kStatus_ENET_RxFrameEmpty No frame received. Should not call ENET_ReadFrameMultiRing to read frame. + * @retval kStatus_ENET_RxFrameError Data error happens. ENET_ReadFrameMultiRing should be called with NULL data + * and NULL length to update the receive buffers. + * @retval kStatus_Success Receive a frame Successfully then the ENET_ReadFrame + * should be called with the right data buffer and the captured data length input. + */ +status_t ENET_GetRxFrameSizeMultiRing(enet_handle_t *handle, uint32_t *length, uint32_t ringId); + +/*! + * @brief Reads a frame from the ENET device for multi-ring. + * + * This function reads a frame (both the data and the length) from the ENET buffer descriptors. + * The ENET_GetRxFrameSizeMultiRing should be used to get the size of the prepared data buffer. + * This usage is the same as the single ring, refer to ENET_ReadFrame. + + * @param base ENET peripheral base address. + * @param handle The ENET handler structure. This is the same handler pointer used in the ENET_Init. + * @param data The data buffer provided by user to store the frame which memory size should be at least "length". + * @param length The size of the data buffer which is still the length of the received frame. + * @param ringId The ring index or ring number; + * @return The execute status, successful or failure. + */ +status_t ENET_ReadFrameMultiRing( + ENET_Type *base, enet_handle_t *handle, uint8_t *data, uint32_t length, uint32_t ringId); + +/*! + * @brief The transmit IRQ handler. + * + * @param base ENET peripheral base address. + * @param handle The ENET handler pointer. + * @param ringId The ring id or ring number. + */ +void ENET_TransmitIRQHandler(ENET_Type *base, enet_handle_t *handle, uint32_t ringId); + +/*! + * @brief The receive IRQ handler. + * + * @param base ENET peripheral base address. + * @param handle The ENET handler pointer. + * @param ringId The ring id or ring number. + */ +void ENET_ReceiveIRQHandler(ENET_Type *base, enet_handle_t *handle, uint32_t ringId); + +/*! + * @brief the common IRQ handler for the tx/rx irq handler. + * + * This is used for the combined tx/rx interrupt for multi-ring (frame 1). + * + * @param base ENET peripheral base address. + */ +void ENET_CommonFrame1IRQHandler(ENET_Type *base); + +/*! + * @brief the common IRQ handler for the tx/rx irq handler. + * + * This is used for the combined tx/rx interrupt for multi-ring (frame 2). + * + * @param base ENET peripheral base address. + */ +void ENET_CommonFrame2IRQHandler(ENET_Type *base); +#else +/*! + * @brief The transmit IRQ handler. + * + * @param base ENET peripheral base address. + * @param handle The ENET handler pointer. + */ +void ENET_TransmitIRQHandler(ENET_Type *base, enet_handle_t *handle); + +/*! + * @brief The receive IRQ handler. + * + * @param base ENET peripheral base address. + * @param handle The ENET handler pointer. + */ +void ENET_ReceiveIRQHandler(ENET_Type *base, enet_handle_t *handle); +#endif /* FSL_FEATURE_ENET_QUEUE > 1 */ + +/*! + * @brief Some special IRQ handler including the error, mii, wakeup irq handler. + * + * @param base ENET peripheral base address. + * @param handle The ENET handler pointer. + */ +void ENET_ErrorIRQHandler(ENET_Type *base, enet_handle_t *handle); + +/*! + * @brief the common IRQ handler for the tx/rx/error etc irq handler. + * + * This is used for the combined tx/rx/error interrupt for single/mutli-ring (frame 0). + * + * @param base ENET peripheral base address. + */ +void ENET_CommonFrame0IRQHandler(ENET_Type *base); +/* @} */ + +#ifdef ENET_ENHANCEDBUFFERDESCRIPTOR_MODE +/*! + * @name ENET PTP 1588 function operation + * @{ + */ + +/*! + * @brief Configures the ENET PTP IEEE 1588 feature with the basic configuration. + * The function sets the clock for PTP 1588 timer and enables + * time stamp interrupts and transmit interrupts for PTP 1588 features. + * This API should be called when the 1588 feature is enabled + * or the ENET_ENHANCEDBUFFERDESCRIPTOR_MODE is defined. + * ENET_Init should be called before calling this API. + * + * @note The PTP 1588 time-stamp second increase though time-stamp interrupt handler + * and the transmit time-stamp store is done through transmit interrupt handler. + * As a result, the TS interrupt and TX interrupt are enabled when you call this API. + * + * @param base ENET peripheral base address. + * @param handle ENET handler pointer. + * @param ptpConfig The ENET PTP1588 configuration. + */ +void ENET_Ptp1588Configure(ENET_Type *base, enet_handle_t *handle, enet_ptp_config_t *ptpConfig); + +/*! + * @brief Starts the ENET PTP 1588 Timer. + * This function is used to initialize the PTP timer. After the PTP starts, + * the PTP timer starts running. + * + * @param base ENET peripheral base address. + * @param ptpClkSrc The clock source of the PTP timer. + */ +void ENET_Ptp1588StartTimer(ENET_Type *base, uint32_t ptpClkSrc); + +/*! + * @brief Stops the ENET PTP 1588 Timer. + * This function is used to stops the ENET PTP timer. + * + * @param base ENET peripheral base address. + */ +static inline void ENET_Ptp1588StopTimer(ENET_Type *base) +{ + /* Disable PTP timer and reset the timer. */ + base->ATCR &= ~ENET_ATCR_EN_MASK; + base->ATCR |= ENET_ATCR_RESTART_MASK; +} + +/*! + * @brief Adjusts the ENET PTP 1588 timer. + * + * @param base ENET peripheral base address. + * @param corrIncrease The correction increment value. This value is added every time the correction + * timer expires. A value less than the PTP timer frequency(1/ptpClkSrc) slows down the timer, + * a value greater than the 1/ptpClkSrc speeds up the timer. + * @param corrPeriod The PTP timer correction counter wrap-around value. This defines after how + * many timer clock the correction counter should be reset and trigger a correction + * increment on the timer. A value of 0 disables the correction counter and no correction occurs. + */ +void ENET_Ptp1588AdjustTimer(ENET_Type *base, uint32_t corrIncrease, uint32_t corrPeriod); + +/*! + * @brief Sets the ENET PTP 1588 timer channel mode. + * + * @param base ENET peripheral base address. + * @param channel The ENET PTP timer channel number. + * @param mode The PTP timer channel mode, see "enet_ptp_timer_channel_mode_t". + * @param intEnable Enables or disables the interrupt. + */ +static inline void ENET_Ptp1588SetChannelMode(ENET_Type *base, + enet_ptp_timer_channel_t channel, + enet_ptp_timer_channel_mode_t mode, + bool intEnable) +{ + uint32_t tcrReg = 0; + + tcrReg = ENET_TCSR_TMODE(mode) | (intEnable ? ENET_TCSR_TIE_MASK : 0); + + /* Disable channel mode first. */ + base->CHANNEL[channel].TCSR = 0; + base->CHANNEL[channel].TCSR = tcrReg; +} + +#if defined(FSL_FEATURE_ENET_HAS_TIMER_PWCONTROL) && FSL_FEATURE_ENET_HAS_TIMER_PWCONTROL +/*! + * @brief Sets ENET PTP 1588 timer channel mode pulse width. + * + * For the input "mode" in ENET_Ptp1588SetChannelMode, the kENET_PtpChannelPulseLowonCompare + * kENET_PtpChannelPulseHighonCompare only support the pulse width for one 1588 clock. + * this function is extended for control the pulse width from 1 to 32 1588 clock cycles. + * so call this function if you need to set the timer channel mode for + * kENET_PtpChannelPulseLowonCompare or kENET_PtpChannelPulseHighonCompare + * with pulse width more than one 1588 clock, + * + * @param base ENET peripheral base address. + * @param channel The ENET PTP timer channel number. + * @param isOutputLow True --- timer channel is configured for output compare + * pulse output low. + * false --- timer channel is configured for output compare + * pulse output high. + * @param pulseWidth The pulse width control value, range from 0 ~ 31. + * 0 --- pulse width is one 1588 clock cycle. + * 31 --- pulse width is thirty two 1588 clock cycles. + * @param intEnable Enables or disables the interrupt. + */ +static inline void ENET_Ptp1588SetChannelOutputPulseWidth( + ENET_Type *base, enet_ptp_timer_channel_t channel, bool isOutputLow, uint8_t pulseWidth, bool intEnable) +{ + uint32_t tcrReg; + + tcrReg = ENET_TCSR_TIE(intEnable) | ENET_TCSR_TPWC(pulseWidth); + + if (isOutputLow) + { + tcrReg |= ENET_TCSR_TMODE(kENET_PtpChannelPulseLowonCompare); + } + else + { + tcrReg |= ENET_TCSR_TMODE(kENET_PtpChannelPulseHighonCompare); + } + + /* Disable channel mode first. */ + base->CHANNEL[channel].TCSR = 0; + base->CHANNEL[channel].TCSR = tcrReg; +} +#endif /* FSL_FEATURE_ENET_HAS_TIMER_PWCONTROL */ + +/*! + * @brief Sets the ENET PTP 1588 timer channel comparison value. + * + * @param base ENET peripheral base address. + * @param channel The PTP timer channel, see "enet_ptp_timer_channel_t". + * @param cmpValue The compare value for the compare setting. + */ +static inline void ENET_Ptp1588SetChannelCmpValue(ENET_Type *base, enet_ptp_timer_channel_t channel, uint32_t cmpValue) +{ + base->CHANNEL[channel].TCCR = cmpValue; +} + +/*! + * @brief Gets the ENET PTP 1588 timer channel status. + * + * @param base ENET peripheral base address. + * @param channel The IEEE 1588 timer channel number. + * @return True or false, Compare or capture operation status + */ +static inline bool ENET_Ptp1588GetChannelStatus(ENET_Type *base, enet_ptp_timer_channel_t channel) +{ + return (0 != (base->CHANNEL[channel].TCSR & ENET_TCSR_TF_MASK)); +} + +/*! + * @brief Clears the ENET PTP 1588 timer channel status. + * + * @param base ENET peripheral base address. + * @param channel The IEEE 1588 timer channel number. + */ +static inline void ENET_Ptp1588ClearChannelStatus(ENET_Type *base, enet_ptp_timer_channel_t channel) +{ + base->CHANNEL[channel].TCSR |= ENET_TCSR_TF_MASK; + base->TGSR = (1U << channel); +} + +/*! + * @brief Gets the current ENET time from the PTP 1588 timer. + * + * @param base ENET peripheral base address. + * @param handle The ENET state pointer. This is the same state pointer used in the ENET_Init. + * @param ptpTime The PTP timer structure. + */ +void ENET_Ptp1588GetTimer(ENET_Type *base, enet_handle_t *handle, enet_ptp_time_t *ptpTime); + +/*! + * @brief Sets the ENET PTP 1588 timer to the assigned time. + * + * @param base ENET peripheral base address. + * @param handle The ENET state pointer. This is the same state pointer used in the ENET_Init. + * @param ptpTime The timer to be set to the PTP timer. + */ +void ENET_Ptp1588SetTimer(ENET_Type *base, enet_handle_t *handle, enet_ptp_time_t *ptpTime); + +/*! + * @brief The IEEE 1588 PTP time stamp interrupt handler. + * + * @param base ENET peripheral base address. + * @param handle The ENET state pointer. This is the same state pointer used in the ENET_Init. + */ +void ENET_Ptp1588TimerIRQHandler(ENET_Type *base, enet_handle_t *handle); + +/*! + * @brief Gets the time stamp of the received frame. + * + * This function is used for PTP stack to get the timestamp captured by the ENET driver. + * + * @param handle The ENET handler pointer.This is the same state pointer used in + * ENET_Init. + * @param ptpTimeData The special PTP timestamp data for search the receive timestamp. + * @retval kStatus_Success Get 1588 timestamp success. + * @retval kStatus_ENET_PtpTsRingEmpty 1588 timestamp ring empty. + * @retval kStatus_ENET_PtpTsRingFull 1588 timestamp ring full. + */ +status_t ENET_GetRxFrameTime(enet_handle_t *handle, enet_ptp_time_data_t *ptpTimeData); + +/*! + * @brief Gets the time stamp of the transmit frame. + * + * This function is used for PTP stack to get the timestamp captured by the ENET driver. + * + * @param handle The ENET handler pointer.This is the same state pointer used in + * ENET_Init. + * @param ptpTimeData The special PTP timestamp data for search the receive timestamp. + * @retval kStatus_Success Get 1588 timestamp success. + * @retval kStatus_ENET_PtpTsRingEmpty 1588 timestamp ring empty. + * @retval kStatus_ENET_PtpTsRingFull 1588 timestamp ring full. + */ +status_t ENET_GetTxFrameTime(enet_handle_t *handle, enet_ptp_time_data_t *ptpTimeData); +#endif /* ENET_ENHANCEDBUFFERDESCRIPTOR_MODE */ +/* @} */ + +#if defined(__cplusplus) +} +#endif + +/*! @}*/ + +#endif /* _FSL_ENET_H_ */ diff --git a/Ubiquitous/XiZi/board/xidatong/third_party_driver/include/fsl_gpio.h b/Ubiquitous/XiZi/board/xidatong/third_party_driver/include/fsl_gpio.h new file mode 100755 index 0000000..94cff82 --- /dev/null +++ b/Ubiquitous/XiZi/board/xidatong/third_party_driver/include/fsl_gpio.h @@ -0,0 +1,350 @@ +/* + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +/** + * @file fsl_gpio.h + * @brief gpio drivers + * @version 2.0 + * @author AIIT XUOS Lab + * @date 2022-03-15 + */ + +#ifndef _FSL_GPIO_H_ +#define _FSL_GPIO_H_ + +#include "fsl_common.h" + +/*! + * @addtogroup gpio_driver + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @name Driver version */ +/*@{*/ +/*! @brief GPIO driver version 2.0.1. */ +#define FSL_GPIO_DRIVER_VERSION (MAKE_VERSION(2, 0, 1)) +/*@}*/ + +/*! @brief GPIO direction definition. */ +typedef enum _gpio_pin_direction +{ + kGPIO_DigitalInput = 0U, /*!< Set current pin as digital input.*/ + kGPIO_DigitalOutput = 1U, /*!< Set current pin as digital output.*/ +} gpio_pin_direction_t; + +/*! @brief GPIO interrupt mode definition. */ +typedef enum _gpio_interrupt_mode +{ + kGPIO_NoIntmode = 0U, /*!< Set current pin general IO functionality.*/ + kGPIO_IntLowLevel = 1U, /*!< Set current pin interrupt is low-level sensitive.*/ + kGPIO_IntHighLevel = 2U, /*!< Set current pin interrupt is high-level sensitive.*/ + kGPIO_IntRisingEdge = 3U, /*!< Set current pin interrupt is rising-edge sensitive.*/ + kGPIO_IntFallingEdge = 4U, /*!< Set current pin interrupt is falling-edge sensitive.*/ + kGPIO_IntRisingOrFallingEdge = 5U, /*!< Enable the edge select bit to override the ICR register's configuration.*/ +} gpio_interrupt_mode_t; + +/*! @brief GPIO Init structure definition. */ +typedef struct _gpio_pin_config +{ + gpio_pin_direction_t direction; /*!< Specifies the pin direction. */ + uint8_t outputLogic; /*!< Set a default output logic, which has no use in input */ + gpio_interrupt_mode_t + interruptMode; /*!< Specifies the pin interrupt mode, a value of @ref gpio_interrupt_mode_t. */ +} gpio_pin_config_t; + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @name GPIO Initialization and Configuration functions + * @{ + */ + +/*! + * @brief Initializes the GPIO peripheral according to the specified + * parameters in the initConfig. + * + * @param base GPIO base pointer. + * @param pin Specifies the pin number + * @param initConfig pointer to a @ref gpio_pin_config_t structure that + * contains the configuration information. + */ +void GPIO_PinInit(GPIO_Type *base, uint32_t pin, const gpio_pin_config_t *Config); +/*@}*/ + +/*! + * @name GPIO Reads and Write Functions + * @{ + */ + +/*! + * @brief Sets the output level of the individual GPIO pin to logic 1 or 0. + * + * @param base GPIO base pointer. + * @param pin GPIO port pin number. + * @param output GPIOpin output logic level. + * - 0: corresponding pin output low-logic level. + * - 1: corresponding pin output high-logic level. + */ +void GPIO_PinWrite(GPIO_Type *base, uint32_t pin, uint8_t output); + +/*! + * @brief Sets the output level of the individual GPIO pin to logic 1 or 0. + * @deprecated Do not use this function. It has been superceded by @ref GPIO_PinWrite. + */ +static inline void GPIO_WritePinOutput(GPIO_Type *base, uint32_t pin, uint8_t output) +{ + GPIO_PinWrite(base, pin, output); +} + +/*! + * @brief Sets the output level of the multiple GPIO pins to the logic 1. + * + * @param base GPIO peripheral base pointer (GPIO1, GPIO2, GPIO3, and so on.) + * @param mask GPIO pin number macro + */ +static inline void GPIO_PortSet(GPIO_Type *base, uint32_t mask) +{ +#if (defined(FSL_FEATURE_IGPIO_HAS_DR_SET) && (FSL_FEATURE_IGPIO_HAS_DR_SET == 1)) + base->DR_SET = mask; +#else + base->DR |= mask; +#endif /* FSL_FEATURE_IGPIO_HAS_DR_SET */ +} + +/*! + * @brief Sets the output level of the multiple GPIO pins to the logic 1. + * @deprecated Do not use this function. It has been superceded by @ref GPIO_PortSet. + */ +static inline void GPIO_SetPinsOutput(GPIO_Type *base, uint32_t mask) +{ + GPIO_PortSet(base, mask); +} + +/*! + * @brief Sets the output level of the multiple GPIO pins to the logic 0. + * + * @param base GPIO peripheral base pointer (GPIO1, GPIO2, GPIO3, and so on.) + * @param mask GPIO pin number macro + */ +static inline void GPIO_PortClear(GPIO_Type *base, uint32_t mask) +{ +#if (defined(FSL_FEATURE_IGPIO_HAS_DR_CLEAR) && (FSL_FEATURE_IGPIO_HAS_DR_CLEAR == 1)) + base->DR_CLEAR = mask; +#else + base->DR &= ~mask; +#endif /* FSL_FEATURE_IGPIO_HAS_DR_CLEAR */ +} + +/*! + * @brief Sets the output level of the multiple GPIO pins to the logic 0. + * @deprecated Do not use this function. It has been superceded by @ref GPIO_PortClear. + */ +static inline void GPIO_ClearPinsOutput(GPIO_Type *base, uint32_t mask) +{ + GPIO_PortClear(base, mask); +} + +/*! + * @brief Reverses the current output logic of the multiple GPIO pins. + * + * @param base GPIO peripheral base pointer (GPIO1, GPIO2, GPIO3, and so on.) + * @param mask GPIO pin number macro + */ +static inline void GPIO_PortToggle(GPIO_Type *base, uint32_t mask) +{ +#if (defined(FSL_FEATURE_IGPIO_HAS_DR_TOGGLE) && (FSL_FEATURE_IGPIO_HAS_DR_TOGGLE == 1)) + base->DR_TOGGLE = mask; +#endif /* FSL_FEATURE_IGPIO_HAS_DR_TOGGLE */ +} + +/*! + * @brief Reads the current input value of the GPIO port. + * + * @param base GPIO base pointer. + * @param pin GPIO port pin number. + * @retval GPIO port input value. + */ +static inline uint32_t GPIO_PinRead(GPIO_Type *base, uint32_t pin) +{ + assert(pin < 32); + + return (((base->DR) >> pin) & 0x1U); +} + +/*! + * @brief Reads the current input value of the GPIO port. + * @deprecated Do not use this function. It has been superceded by @ref GPIO_PinRead. + */ +static inline uint32_t GPIO_ReadPinInput(GPIO_Type *base, uint32_t pin) +{ + return GPIO_PinRead(base, pin); +} +/*@}*/ + +/*! + * @name GPIO Reads Pad Status Functions + * @{ + */ + +/*! +* @brief Reads the current GPIO pin pad status. +* +* @param base GPIO base pointer. +* @param pin GPIO port pin number. +* @retval GPIO pin pad status value. +*/ +static inline uint8_t GPIO_PinReadPadStatus(GPIO_Type *base, uint32_t pin) +{ + assert(pin < 32); + + return (uint8_t)(((base->PSR) >> pin) & 0x1U); +} + +/*! +* @brief Reads the current GPIO pin pad status. +* @deprecated Do not use this function. It has been superceded by @ref GPIO_PinReadPadStatus. +*/ +static inline uint8_t GPIO_ReadPadStatus(GPIO_Type *base, uint32_t pin) +{ + return GPIO_PinReadPadStatus(base, pin); +} + +/*@}*/ + +/*! + * @name Interrupts and flags management functions + * @{ + */ + +/*! + * @brief Sets the current pin interrupt mode. + * + * @param base GPIO base pointer. + * @param pin GPIO port pin number. + * @param pininterruptMode pointer to a @ref gpio_interrupt_mode_t structure + * that contains the interrupt mode information. + */ +void GPIO_PinSetInterruptConfig(GPIO_Type *base, uint32_t pin, gpio_interrupt_mode_t pinInterruptMode); + +/*! + * @brief Sets the current pin interrupt mode. + * @deprecated Do not use this function. It has been superceded by @ref GPIO_PinSetInterruptConfig. + */ +static inline void GPIO_SetPinInterruptConfig(GPIO_Type *base, uint32_t pin, gpio_interrupt_mode_t pinInterruptMode) +{ + GPIO_PinSetInterruptConfig(base, pin, pinInterruptMode); +} + +/*! + * @brief Enables the specific pin interrupt. + * + * @param base GPIO base pointer. + * @param mask GPIO pin number macro. + */ +static inline void GPIO_PortEnableInterrupts(GPIO_Type *base, uint32_t mask) +{ + base->IMR |= mask; +} + +/*! + * @brief Enables the specific pin interrupt. + * + * @param base GPIO base pointer. + * @param mask GPIO pin number macro. + */ +static inline void GPIO_EnableInterrupts(GPIO_Type *base, uint32_t mask) +{ + GPIO_PortEnableInterrupts(base, mask); +} + +/*! + * @brief Disables the specific pin interrupt. + * + * @param base GPIO base pointer. + * @param mask GPIO pin number macro. + */ +static inline void GPIO_PortDisableInterrupts(GPIO_Type *base, uint32_t mask) +{ + base->IMR &= ~mask; +} + +/*! + * @brief Disables the specific pin interrupt. + * @deprecated Do not use this function. It has been superceded by @ref GPIO_PortDisableInterrupts. + */ +static inline void GPIO_DisableInterrupts(GPIO_Type *base, uint32_t mask) +{ + GPIO_PortDisableInterrupts(base, mask); +} + +/*! + * @brief Reads individual pin interrupt status. + * + * @param base GPIO base pointer. + * @retval current pin interrupt status flag. + */ +static inline uint32_t GPIO_PortGetInterruptFlags(GPIO_Type *base) +{ + return base->ISR; +} + +/*! + * @brief Reads individual pin interrupt status. + * + * @param base GPIO base pointer. + * @retval current pin interrupt status flag. + */ +static inline uint32_t GPIO_GetPinsInterruptFlags(GPIO_Type *base) +{ + return GPIO_PortGetInterruptFlags(base); +} + +/*! + * @brief Clears pin interrupt flag. Status flags are cleared by + * writing a 1 to the corresponding bit position. + * + * @param base GPIO base pointer. + * @param mask GPIO pin number macro. + */ +static inline void GPIO_PortClearInterruptFlags(GPIO_Type *base, uint32_t mask) +{ + base->ISR = mask; +} + +/*! + * @brief Clears pin interrupt flag. Status flags are cleared by + * writing a 1 to the corresponding bit position. + * + * @param base GPIO base pointer. + * @param mask GPIO pin number macro. + */ +static inline void GPIO_ClearPinsInterruptFlags(GPIO_Type *base, uint32_t mask) +{ + GPIO_PortClearInterruptFlags(base, mask); +} +/*@}*/ + +#if defined(__cplusplus) +} +#endif + +/*! + * @} + */ + +#endif /* _FSL_GPIO_H_*/ diff --git a/Ubiquitous/XiZi/board/xidatong/third_party_driver/include/fsl_iomuxc.h b/Ubiquitous/XiZi/board/xidatong/third_party_driver/include/fsl_iomuxc.h new file mode 100755 index 0000000..9ec600f --- /dev/null +++ b/Ubiquitous/XiZi/board/xidatong/third_party_driver/include/fsl_iomuxc.h @@ -0,0 +1,1248 @@ +/* + * Copyright 2016 Freescale Semiconductor, Inc. + * Copyright 2016-2018 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +/** + * @file fsl_iomuxc.h + * @brief io mux drivers + * @version 2.0 + * @author AIIT XUOS Lab + * @date 2022-03-15 + */ + +#ifndef _FSL_IOMUXC_H_ +#define _FSL_IOMUXC_H_ + +#include "fsl_common.h" + +/*! + * @addtogroup iomuxc_driver + * @{ + */ + +/*! @file */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.iomuxc" +#endif + +/*! @name Driver version */ +/*@{*/ +/*! @brief IOMUXC driver version 2.0.0. */ +#define FSL_IOMUXC_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) +/*@}*/ + +/*! @name Pin function ID */ +/*@{*/ +/*! @brief The pin function ID is a tuple of */ +#define IOMUXC_SNVS_WAKEUP_GPIO5_IO00 0x400A8000U, 0x5U, 0, 0, 0x400A8018U +#define IOMUXC_SNVS_WAKEUP_NMI_GLUE_NMI 0x400A8000U, 0x7U, 0x401F8568U, 0x1U, 0x400A8018U + +#define IOMUXC_SNVS_PMIC_ON_REQ_SNVS_LP_PMIC_ON_REQ 0x400A8004U, 0x0U, 0, 0, 0x400A801CU +#define IOMUXC_SNVS_PMIC_ON_REQ_GPIO5_IO01 0x400A8004U, 0x5U, 0, 0, 0x400A801CU + +#define IOMUXC_SNVS_PMIC_STBY_REQ_CCM_PMIC_VSTBY_REQ 0x400A8008U, 0x0U, 0, 0, 0x400A8020U +#define IOMUXC_SNVS_PMIC_STBY_REQ_GPIO5_IO02 0x400A8008U, 0x5U, 0, 0, 0x400A8020U + +#define IOMUXC_SNVS_TEST_MODE 0, 0, 0, 0, 0x400A800CU + +#define IOMUXC_SNVS_POR_B 0, 0, 0, 0, 0x400A8010U + +#define IOMUXC_SNVS_ONOFF 0, 0, 0, 0, 0x400A8014U + +#define IOMUXC_GPIO_EMC_00_SEMC_DATA00 0x401F8014U, 0x0U, 0, 0, 0x401F8204U +#define IOMUXC_GPIO_EMC_00_FLEXPWM4_PWMA00 0x401F8014U, 0x1U, 0x401F8494U, 0x0U, 0x401F8204U +#define IOMUXC_GPIO_EMC_00_LPSPI2_SCK 0x401F8014U, 0x2U, 0x401F8500U, 0x1U, 0x401F8204U +#define IOMUXC_GPIO_EMC_00_XBAR1_XBAR_IN02 0x401F8014U, 0x3U, 0x401F860CU, 0x0U, 0x401F8204U +#define IOMUXC_GPIO_EMC_00_FLEXIO1_FLEXIO00 0x401F8014U, 0x4U, 0, 0, 0x401F8204U +#define IOMUXC_GPIO_EMC_00_GPIO4_IO00 0x401F8014U, 0x5U, 0, 0, 0x401F8204U + +#define IOMUXC_GPIO_EMC_01_SEMC_DATA01 0x401F8018U, 0x0U, 0, 0, 0x401F8208U +#define IOMUXC_GPIO_EMC_01_FLEXPWM4_PWMB00 0x401F8018U, 0x1U, 0, 0, 0x401F8208U +#define IOMUXC_GPIO_EMC_01_LPSPI2_PCS0 0x401F8018U, 0x2U, 0x401F84FCU, 0x1U, 0x401F8208U +#define IOMUXC_GPIO_EMC_01_XBAR1_IN03 0x401F8018U, 0x3U, 0x401F8610U, 0x0U, 0x401F8208U +#define IOMUXC_GPIO_EMC_01_FLEXIO1_FLEXIO01 0x401F8018U, 0x4U, 0, 0, 0x401F8208U +#define IOMUXC_GPIO_EMC_01_GPIO4_IO01 0x401F8018U, 0x5U, 0, 0, 0x401F8208U + +#define IOMUXC_GPIO_EMC_02_SEMC_DATA02 0x401F801CU, 0x0U, 0, 0, 0x401F820CU +#define IOMUXC_GPIO_EMC_02_FLEXPWM4_PWMA01 0x401F801CU, 0x1U, 0x401F8498U, 0x0U, 0x401F820CU +#define IOMUXC_GPIO_EMC_02_LPSPI2_SDO 0x401F801CU, 0x2U, 0x401F8508U, 0x1U, 0x401F820CU +#define IOMUXC_GPIO_EMC_02_XBAR1_INOUT04 0x401F801CU, 0x3U, 0x401F8614U, 0x0U, 0x401F820CU +#define IOMUXC_GPIO_EMC_02_FLEXIO1_FLEXIO02 0x401F801CU, 0x4U, 0, 0, 0x401F820CU +#define IOMUXC_GPIO_EMC_02_GPIO4_IO02 0x401F801CU, 0x5U, 0, 0, 0x401F820CU + +#define IOMUXC_GPIO_EMC_03_SEMC_DATA03 0x401F8020U, 0x0U, 0, 0, 0x401F8210U +#define IOMUXC_GPIO_EMC_03_FLEXPWM4_PWMB01 0x401F8020U, 0x1U, 0, 0, 0x401F8210U +#define IOMUXC_GPIO_EMC_03_LPSPI2_SDI 0x401F8020U, 0x2U, 0x401F8504U, 0x1U, 0x401F8210U +#define IOMUXC_GPIO_EMC_03_XBAR1_INOUT05 0x401F8020U, 0x3U, 0x401F8618U, 0x0U, 0x401F8210U +#define IOMUXC_GPIO_EMC_03_FLEXIO1_FLEXIO03 0x401F8020U, 0x4U, 0, 0, 0x401F8210U +#define IOMUXC_GPIO_EMC_03_GPIO4_IO03 0x401F8020U, 0x5U, 0, 0, 0x401F8210U + +#define IOMUXC_GPIO_EMC_04_SEMC_DATA04 0x401F8024U, 0x0U, 0, 0, 0x401F8214U +#define IOMUXC_GPIO_EMC_04_FLEXPWM4_PWMA02 0x401F8024U, 0x1U, 0x401F849CU, 0x0U, 0x401F8214U +#define IOMUXC_GPIO_EMC_04_SAI2_TX_DATA 0x401F8024U, 0x2U, 0, 0, 0x401F8214U +#define IOMUXC_GPIO_EMC_04_XBAR1_INOUT06 0x401F8024U, 0x3U, 0x401F861CU, 0x0U, 0x401F8214U +#define IOMUXC_GPIO_EMC_04_FLEXIO1_FLEXIO04 0x401F8024U, 0x4U, 0, 0, 0x401F8214U +#define IOMUXC_GPIO_EMC_04_GPIO4_IO04 0x401F8024U, 0x5U, 0, 0, 0x401F8214U + +#define IOMUXC_GPIO_EMC_05_SEMC_DATA05 0x401F8028U, 0x0U, 0, 0, 0x401F8218U +#define IOMUXC_GPIO_EMC_05_FLEXPWM4_PWMB02 0x401F8028U, 0x1U, 0, 0, 0x401F8218U +#define IOMUXC_GPIO_EMC_05_SAI2_TX_SYNC 0x401F8028U, 0x2U, 0x401F85C4U, 0x0U, 0x401F8218U +#define IOMUXC_GPIO_EMC_05_XBAR1_INOUT07 0x401F8028U, 0x3U, 0x401F8620U, 0x0U, 0x401F8218U +#define IOMUXC_GPIO_EMC_05_FLEXIO1_FLEXIO05 0x401F8028U, 0x4U, 0, 0, 0x401F8218U +#define IOMUXC_GPIO_EMC_05_GPIO4_IO05 0x401F8028U, 0x5U, 0, 0, 0x401F8218U + +#define IOMUXC_GPIO_EMC_06_SEMC_DATA06 0x401F802CU, 0x0U, 0, 0, 0x401F821CU +#define IOMUXC_GPIO_EMC_06_FLEXPWM2_PWMA00 0x401F802CU, 0x1U, 0x401F8478U, 0x0U, 0x401F821CU +#define IOMUXC_GPIO_EMC_06_SAI2_TX_BCLK 0x401F802CU, 0x2U, 0x401F85C0U, 0x0U, 0x401F821CU +#define IOMUXC_GPIO_EMC_06_XBAR1_INOUT08 0x401F802CU, 0x3U, 0x401F8624U, 0x0U, 0x401F821CU +#define IOMUXC_GPIO_EMC_06_FLEXIO1_FLEXIO06 0x401F802CU, 0x4U, 0, 0, 0x401F821CU +#define IOMUXC_GPIO_EMC_06_GPIO4_IO06 0x401F802CU, 0x5U, 0, 0, 0x401F821CU + +#define IOMUXC_GPIO_EMC_07_SEMC_DATA07 0x401F8030U, 0x0U, 0, 0, 0x401F8220U +#define IOMUXC_GPIO_EMC_07_FLEXPWM2_PWMB00 0x401F8030U, 0x1U, 0x401F8488U, 0x0U, 0x401F8220U +#define IOMUXC_GPIO_EMC_07_SAI2_MCLK 0x401F8030U, 0x2U, 0x401F85B0U, 0x0U, 0x401F8220U +#define IOMUXC_GPIO_EMC_07_XBAR1_INOUT09 0x401F8030U, 0x3U, 0x401F8628U, 0x0U, 0x401F8220U +#define IOMUXC_GPIO_EMC_07_FLEXIO1_FLEXIO07 0x401F8030U, 0x4U, 0, 0, 0x401F8220U +#define IOMUXC_GPIO_EMC_07_GPIO4_IO07 0x401F8030U, 0x5U, 0, 0, 0x401F8220U + +#define IOMUXC_GPIO_EMC_08_SEMC_DM00 0x401F8034U, 0x0U, 0, 0, 0x401F8224U +#define IOMUXC_GPIO_EMC_08_FLEXPWM2_PWMA01 0x401F8034U, 0x1U, 0x401F847CU, 0x0U, 0x401F8224U +#define IOMUXC_GPIO_EMC_08_SAI2_RX_DATA 0x401F8034U, 0x2U, 0x401F85B8U, 0x0U, 0x401F8224U +#define IOMUXC_GPIO_EMC_08_XBAR1_INOUT17 0x401F8034U, 0x3U, 0x401F862CU, 0x0U, 0x401F8224U +#define IOMUXC_GPIO_EMC_08_FLEXIO1_FLEXIO08 0x401F8034U, 0x4U, 0, 0, 0x401F8224U +#define IOMUXC_GPIO_EMC_08_GPIO4_IO08 0x401F8034U, 0x5U, 0, 0, 0x401F8224U + +#define IOMUXC_GPIO_EMC_09_SEMC_ADDR00 0x401F8038U, 0x0U, 0, 0, 0x401F8228U +#define IOMUXC_GPIO_EMC_09_FLEXPWM2_PWMB01 0x401F8038U, 0x1U, 0x401F848CU, 0x0U, 0x401F8228U +#define IOMUXC_GPIO_EMC_09_SAI2_RX_SYNC 0x401F8038U, 0x2U, 0x401F85BCU, 0x0U, 0x401F8228U +#define IOMUXC_GPIO_EMC_09_FLEXCAN2_TX 0x401F8038U, 0x3U, 0, 0, 0x401F8228U +#define IOMUXC_GPIO_EMC_09_FLEXIO1_FLEXIO09 0x401F8038U, 0x4U, 0, 0, 0x401F8228U +#define IOMUXC_GPIO_EMC_09_GPIO4_IO09 0x401F8038U, 0x5U, 0, 0, 0x401F8228U + +#define IOMUXC_GPIO_EMC_10_SEMC_ADDR01 0x401F803CU, 0x0U, 0, 0, 0x401F822CU +#define IOMUXC_GPIO_EMC_10_FLEXPWM2_PWMA02 0x401F803CU, 0x1U, 0x401F8480U, 0x0U, 0x401F822CU +#define IOMUXC_GPIO_EMC_10_SAI2_RX_BCLK 0x401F803CU, 0x2U, 0x401F85B4U, 0x0U, 0x401F822CU +#define IOMUXC_GPIO_EMC_10_FLEXCAN2_RX 0x401F803CU, 0x3U, 0x401F8450U, 0x0U, 0x401F822CU +#define IOMUXC_GPIO_EMC_10_FLEXIO1_FLEXIO10 0x401F803CU, 0x4U, 0, 0, 0x401F822CU +#define IOMUXC_GPIO_EMC_10_GPIO4_IO10 0x401F803CU, 0x5U, 0, 0, 0x401F822CU + +#define IOMUXC_GPIO_EMC_11_SEMC_ADDR02 0x401F8040U, 0x0U, 0, 0, 0x401F8230U +#define IOMUXC_GPIO_EMC_11_FLEXPWM2_PWMB02 0x401F8040U, 0x1U, 0x401F8490U, 0x0U, 0x401F8230U +#define IOMUXC_GPIO_EMC_11_LPI2C4_SDA 0x401F8040U, 0x2U, 0x401F84E8U, 0x0U, 0x401F8230U +#define IOMUXC_GPIO_EMC_11_USDHC2_RESET_B 0x401F8040U, 0x3U, 0, 0, 0x401F8230U +#define IOMUXC_GPIO_EMC_11_FLEXIO1_FLEXIO11 0x401F8040U, 0x4U, 0, 0, 0x401F8230U +#define IOMUXC_GPIO_EMC_11_GPIO4_IO11 0x401F8040U, 0x5U, 0, 0, 0x401F8230U + +#define IOMUXC_GPIO_EMC_12_SEMC_ADDR03 0x401F8044U, 0x0U, 0, 0, 0x401F8234U +#define IOMUXC_GPIO_EMC_12_XBAR1_IN24 0x401F8044U, 0x1U, 0x401F8640U, 0x0U, 0x401F8234U +#define IOMUXC_GPIO_EMC_12_LPI2C4_SCL 0x401F8044U, 0x2U, 0x401F84E4U, 0x0U, 0x401F8234U +#define IOMUXC_GPIO_EMC_12_USDHC1_WP 0x401F8044U, 0x3U, 0x401F85D8U, 0x0U, 0x401F8234U +#define IOMUXC_GPIO_EMC_12_FLEXPWM1_PWMA03 0x401F8044U, 0x4U, 0x401F8454U, 0x1U, 0x401F8234U +#define IOMUXC_GPIO_EMC_12_GPIO4_IO12 0x401F8044U, 0x5U, 0, 0, 0x401F8234U + +#define IOMUXC_GPIO_EMC_13_SEMC_ADDR04 0x401F8048U, 0x0U, 0, 0, 0x401F8238U +#define IOMUXC_GPIO_EMC_13_XBAR1_IN25 0x401F8048U, 0x1U, 0x401F8650U, 0x1U, 0x401F8238U +#define IOMUXC_GPIO_EMC_13_LPUART3_TX 0x401F8048U, 0x2U, 0x401F853CU, 0x1U, 0x401F8238U +#define IOMUXC_GPIO_EMC_13_MQS_RIGHT 0x401F8048U, 0x3U, 0, 0, 0x401F8238U +#define IOMUXC_GPIO_EMC_13_FLEXPWM1_PWMB03 0x401F8048U, 0x4U, 0x401F8464U, 0x1U, 0x401F8238U +#define IOMUXC_GPIO_EMC_13_GPIO4_IO13 0x401F8048U, 0x5U, 0, 0, 0x401F8238U + +#define IOMUXC_GPIO_EMC_14_SEMC_ADDR05 0x401F804CU, 0x0U, 0, 0, 0x401F823CU +#define IOMUXC_GPIO_EMC_14_XBAR1_INOUT19 0x401F804CU, 0x1U, 0x401F8654U, 0x0U, 0x401F823CU +#define IOMUXC_GPIO_EMC_14_LPUART3_RX 0x401F804CU, 0x2U, 0x401F8538U, 0x1U, 0x401F823CU +#define IOMUXC_GPIO_EMC_14_MQS_LEFT 0x401F804CU, 0x3U, 0, 0, 0x401F823CU +#define IOMUXC_GPIO_EMC_14_LPSPI2_PCS1 0x401F804CU, 0x4U, 0, 0, 0x401F823CU +#define IOMUXC_GPIO_EMC_14_GPIO4_IO14 0x401F804CU, 0x5U, 0, 0, 0x401F823CU + +#define IOMUXC_GPIO_EMC_15_SEMC_ADDR06 0x401F8050U, 0x0U, 0, 0, 0x401F8240U +#define IOMUXC_GPIO_EMC_15_XBAR1_IN20 0x401F8050U, 0x1U, 0x401F8634U, 0x0U, 0x401F8240U +#define IOMUXC_GPIO_EMC_15_LPUART3_CTS_B 0x401F8050U, 0x2U, 0x401F8534U, 0x0U, 0x401F8240U +#define IOMUXC_GPIO_EMC_15_SPDIF_OUT 0x401F8050U, 0x3U, 0, 0, 0x401F8240U +#define IOMUXC_GPIO_EMC_15_QTIMER3_TIMER0 0x401F8050U, 0x4U, 0x401F857CU, 0x0U, 0x401F8240U +#define IOMUXC_GPIO_EMC_15_GPIO4_IO15 0x401F8050U, 0x5U, 0, 0, 0x401F8240U + +#define IOMUXC_GPIO_EMC_16_SEMC_ADDR07 0x401F8054U, 0x0U, 0, 0, 0x401F8244U +#define IOMUXC_GPIO_EMC_16_XBAR1_IN21 0x401F8054U, 0x1U, 0x401F8658U, 0x0U, 0x401F8244U +#define IOMUXC_GPIO_EMC_16_LPUART3_RTS_B 0x401F8054U, 0x2U, 0, 0, 0x401F8244U +#define IOMUXC_GPIO_EMC_16_SPDIF_IN 0x401F8054U, 0x3U, 0x401F85C8U, 0x1U, 0x401F8244U +#define IOMUXC_GPIO_EMC_16_QTIMER3_TIMER1 0x401F8054U, 0x4U, 0x401F8580U, 0x1U, 0x401F8244U +#define IOMUXC_GPIO_EMC_16_GPIO4_IO16 0x401F8054U, 0x5U, 0, 0, 0x401F8244U + +#define IOMUXC_GPIO_EMC_17_SEMC_ADDR08 0x401F8058U, 0x0U, 0, 0, 0x401F8248U +#define IOMUXC_GPIO_EMC_17_FLEXPWM4_PWMA03 0x401F8058U, 0x1U, 0x401F84A0U, 0x0U, 0x401F8248U +#define IOMUXC_GPIO_EMC_17_LPUART4_CTS_B 0x401F8058U, 0x2U, 0, 0, 0x401F8248U +#define IOMUXC_GPIO_EMC_17_FLEXCAN1_TX 0x401F8058U, 0x3U, 0, 0, 0x401F8248U +#define IOMUXC_GPIO_EMC_17_QTIMER3_TIMER2 0x401F8058U, 0x4U, 0x401F8584U, 0x0U, 0x401F8248U +#define IOMUXC_GPIO_EMC_17_GPIO4_IO17 0x401F8058U, 0x5U, 0, 0, 0x401F8248U + +#define IOMUXC_GPIO_EMC_18_SEMC_ADDR09 0x401F805CU, 0x0U, 0, 0, 0x401F824CU +#define IOMUXC_GPIO_EMC_18_FLEXPWM4_PWMB03 0x401F805CU, 0x1U, 0, 0, 0x401F824CU +#define IOMUXC_GPIO_EMC_18_LPUART4_RTS_B 0x401F805CU, 0x2U, 0, 0, 0x401F824CU +#define IOMUXC_GPIO_EMC_18_FLEXCAN1_RX 0x401F805CU, 0x3U, 0x401F844CU, 0x1U, 0x401F824CU +#define IOMUXC_GPIO_EMC_18_QTIMER3_TIMER3 0x401F805CU, 0x4U, 0x401F8588U, 0x0U, 0x401F824CU +#define IOMUXC_GPIO_EMC_18_GPIO4_IO18 0x401F805CU, 0x5U, 0, 0, 0x401F824CU +#define IOMUXC_GPIO_EMC_18_SNVS_VIO_5_CTL 0x401F805CU, 0x6U, 0, 0, 0x401F824CU + +#define IOMUXC_GPIO_EMC_19_SEMC_ADDR11 0x401F8060U, 0x0U, 0, 0, 0x401F8250U +#define IOMUXC_GPIO_EMC_19_FLEXPWM2_PWMA03 0x401F8060U, 0x1U, 0x401F8474U, 0x1U, 0x401F8250U +#define IOMUXC_GPIO_EMC_19_LPUART4_TX 0x401F8060U, 0x2U, 0x401F8544U, 0x1U, 0x401F8250U +#define IOMUXC_GPIO_EMC_19_ENET_RDATA01 0x401F8060U, 0x3U, 0x401F8438U, 0x0U, 0x401F8250U +#define IOMUXC_GPIO_EMC_19_QTIMER2_TIMER0 0x401F8060U, 0x4U, 0x401F856CU, 0x0U, 0x401F8250U +#define IOMUXC_GPIO_EMC_19_GPIO4_IO19 0x401F8060U, 0x5U, 0, 0, 0x401F8250U +#define IOMUXC_GPIO_EMC_19_SNVS_VIO_5 0x401F8060U, 0x6U, 0, 0, 0x401F8250U + +#define IOMUXC_GPIO_EMC_20_SEMC_ADDR12 0x401F8064U, 0x0U, 0, 0, 0x401F8254U +#define IOMUXC_GPIO_EMC_20_FLEXPWM2_PWMB03 0x401F8064U, 0x1U, 0x401F8484U, 0x1U, 0x401F8254U +#define IOMUXC_GPIO_EMC_20_LPUART4_RX 0x401F8064U, 0x2U, 0x401F8540U, 0x1U, 0x401F8254U +#define IOMUXC_GPIO_EMC_20_ENET_RDATA00 0x401F8064U, 0x3U, 0x401F8434U, 0x0U, 0x401F8254U +#define IOMUXC_GPIO_EMC_20_QTIMER2_TIMER1 0x401F8064U, 0x4U, 0x401F8570U, 0x0U, 0x401F8254U +#define IOMUXC_GPIO_EMC_20_GPIO4_IO20 0x401F8064U, 0x5U, 0, 0, 0x401F8254U + +#define IOMUXC_GPIO_EMC_21_SEMC_BA0 0x401F8068U, 0x0U, 0, 0, 0x401F8258U +#define IOMUXC_GPIO_EMC_21_FLEXPWM3_PWMA03 0x401F8068U, 0x1U, 0, 0, 0x401F8258U +#define IOMUXC_GPIO_EMC_21_LPI2C3_SDA 0x401F8068U, 0x2U, 0x401F84E0U, 0x0U, 0x401F8258U +#define IOMUXC_GPIO_EMC_21_ENET_TDATA01 0x401F8068U, 0x3U, 0, 0, 0x401F8258U +#define IOMUXC_GPIO_EMC_21_QTIMER2_TIMER2 0x401F8068U, 0x4U, 0x401F8574U, 0x0U, 0x401F8258U +#define IOMUXC_GPIO_EMC_21_GPIO4_IO21 0x401F8068U, 0x5U, 0, 0, 0x401F8258U + +#define IOMUXC_GPIO_EMC_22_SEMC_BA1 0x401F806CU, 0x0U, 0, 0, 0x401F825CU +#define IOMUXC_GPIO_EMC_22_FLEXPWM3_PWMB03 0x401F806CU, 0x1U, 0, 0, 0x401F825CU +#define IOMUXC_GPIO_EMC_22_LPI2C3_SCL 0x401F806CU, 0x2U, 0x401F84DCU, 0x0U, 0x401F825CU +#define IOMUXC_GPIO_EMC_22_ENET_TDATA00 0x401F806CU, 0x3U, 0, 0, 0x401F825CU +#define IOMUXC_GPIO_EMC_22_QTIMER2_TIMER3 0x401F806CU, 0x4U, 0x401F8578U, 0x0U, 0x401F825CU +#define IOMUXC_GPIO_EMC_22_GPIO4_IO22 0x401F806CU, 0x5U, 0, 0, 0x401F825CU + +#define IOMUXC_GPIO_EMC_23_SEMC_ADDR10 0x401F8070U, 0x0U, 0, 0, 0x401F8260U +#define IOMUXC_GPIO_EMC_23_FLEXPWM1_PWMA00 0x401F8070U, 0x1U, 0x401F8458U, 0x0U, 0x401F8260U +#define IOMUXC_GPIO_EMC_23_LPUART5_TX 0x401F8070U, 0x2U, 0x401F854CU, 0x0U, 0x401F8260U +#define IOMUXC_GPIO_EMC_23_ENET_RX_EN 0x401F8070U, 0x3U, 0x401F843CU, 0x0U, 0x401F8260U +#define IOMUXC_GPIO_EMC_23_GPT1_CAPTURE2 0x401F8070U, 0x4U, 0, 0, 0x401F8260U +#define IOMUXC_GPIO_EMC_23_GPIO4_IO23 0x401F8070U, 0x5U, 0, 0, 0x401F8260U + +#define IOMUXC_GPIO_EMC_24_SEMC_CAS 0x401F8074U, 0x0U, 0, 0, 0x401F8264U +#define IOMUXC_GPIO_EMC_24_FLEXPWM1_PWMB00 0x401F8074U, 0x1U, 0x401F8468U, 0x0U, 0x401F8264U +#define IOMUXC_GPIO_EMC_24_LPUART5_RX 0x401F8074U, 0x2U, 0x401F8548U, 0x0U, 0x401F8264U +#define IOMUXC_GPIO_EMC_24_ENET_TX_EN 0x401F8074U, 0x3U, 0, 0, 0x401F8264U +#define IOMUXC_GPIO_EMC_24_GPT1_CAPTURE1 0x401F8074U, 0x4U, 0, 0, 0x401F8264U +#define IOMUXC_GPIO_EMC_24_GPIO4_IO24 0x401F8074U, 0x5U, 0, 0, 0x401F8264U + +#define IOMUXC_GPIO_EMC_25_SEMC_RAS 0x401F8078U, 0x0U, 0, 0, 0x401F8268U +#define IOMUXC_GPIO_EMC_25_FLEXPWM1_PWMA01 0x401F8078U, 0x1U, 0x401F845CU, 0x0U, 0x401F8268U +#define IOMUXC_GPIO_EMC_25_LPUART6_TX 0x401F8078U, 0x2U, 0x401F8554U, 0x0U, 0x401F8268U +#define IOMUXC_GPIO_EMC_25_ENET_TX_CLK 0x401F8078U, 0x3U, 0x401F8448U, 0x0U, 0x401F8268U +#define IOMUXC_GPIO_EMC_25_ENET_REF_CLK 0x401F8078U, 0x4U, 0x401F842CU, 0x0U, 0x401F8268U +#define IOMUXC_GPIO_EMC_25_GPIO4_IO25 0x401F8078U, 0x5U, 0, 0, 0x401F8268U + +#define IOMUXC_GPIO_EMC_26_SEMC_CLK 0x401F807CU, 0x0U, 0, 0, 0x401F826CU +#define IOMUXC_GPIO_EMC_26_FLEXPWM1_PWMB01 0x401F807CU, 0x1U, 0x401F846CU, 0x0U, 0x401F826CU +#define IOMUXC_GPIO_EMC_26_LPUART6_RX 0x401F807CU, 0x2U, 0x401F8550U, 0x0U, 0x401F826CU +#define IOMUXC_GPIO_EMC_26_ENET_RX_ER 0x401F807CU, 0x3U, 0x401F8440U, 0x0U, 0x401F826CU +#define IOMUXC_GPIO_EMC_26_FLEXIO1_FLEXIO12 0x401F807CU, 0x4U, 0, 0, 0x401F826CU +#define IOMUXC_GPIO_EMC_26_GPIO4_IO26 0x401F807CU, 0x5U, 0, 0, 0x401F826CU + +#define IOMUXC_GPIO_EMC_27_SEMC_CKE 0x401F8080U, 0x0U, 0, 0, 0x401F8270U +#define IOMUXC_GPIO_EMC_27_FLEXPWM1_PWMA02 0x401F8080U, 0x1U, 0x401F8460U, 0x0U, 0x401F8270U +#define IOMUXC_GPIO_EMC_27_LPUART5_RTS_B 0x401F8080U, 0x2U, 0, 0, 0x401F8270U +#define IOMUXC_GPIO_EMC_27_LPSPI1_SCK 0x401F8080U, 0x3U, 0x401F84F0U, 0x0U, 0x401F8270U +#define IOMUXC_GPIO_EMC_27_FLEXIO1_FLEXIO13 0x401F8080U, 0x4U, 0, 0, 0x401F8270U +#define IOMUXC_GPIO_EMC_27_GPIO4_IO27 0x401F8080U, 0x5U, 0, 0, 0x401F8270U + +#define IOMUXC_GPIO_EMC_28_SEMC_WE 0x401F8084U, 0x0U, 0, 0, 0x401F8274U +#define IOMUXC_GPIO_EMC_28_FLEXPWM1_PWMB02 0x401F8084U, 0x1U, 0x401F8470U, 0x0U, 0x401F8274U +#define IOMUXC_GPIO_EMC_28_LPUART5_CTS_B 0x401F8084U, 0x2U, 0, 0, 0x401F8274U +#define IOMUXC_GPIO_EMC_28_LPSPI1_SDO 0x401F8084U, 0x3U, 0x401F84F8U, 0x0U, 0x401F8274U +#define IOMUXC_GPIO_EMC_28_FLEXIO1_FLEXIO14 0x401F8084U, 0x4U, 0, 0, 0x401F8274U +#define IOMUXC_GPIO_EMC_28_GPIO4_IO28 0x401F8084U, 0x5U, 0, 0, 0x401F8274U + +#define IOMUXC_GPIO_EMC_29_SEMC_CS0 0x401F8088U, 0x0U, 0, 0, 0x401F8278U +#define IOMUXC_GPIO_EMC_29_FLEXPWM3_PWMA00 0x401F8088U, 0x1U, 0, 0, 0x401F8278U +#define IOMUXC_GPIO_EMC_29_LPUART6_RTS_B 0x401F8088U, 0x2U, 0, 0, 0x401F8278U +#define IOMUXC_GPIO_EMC_29_LPSPI1_SDI 0x401F8088U, 0x3U, 0x401F84F4U, 0x0U, 0x401F8278U +#define IOMUXC_GPIO_EMC_29_FLEXIO1_FLEXIO15 0x401F8088U, 0x4U, 0, 0, 0x401F8278U +#define IOMUXC_GPIO_EMC_29_GPIO4_IO29 0x401F8088U, 0x5U, 0, 0, 0x401F8278U + +#define IOMUXC_GPIO_EMC_30_SEMC_DATA08 0x401F808CU, 0x0U, 0, 0, 0x401F827CU +#define IOMUXC_GPIO_EMC_30_FLEXPWM3_PWMB00 0x401F808CU, 0x1U, 0, 0, 0x401F827CU +#define IOMUXC_GPIO_EMC_30_LPUART6_CTS_B 0x401F808CU, 0x2U, 0, 0, 0x401F827CU +#define IOMUXC_GPIO_EMC_30_LPSPI1_PCS0 0x401F808CU, 0x3U, 0x401F84ECU, 0x1U, 0x401F827CU +#define IOMUXC_GPIO_EMC_30_CSI_DATA23 0x401F808CU, 0x4U, 0, 0, 0x401F827CU +#define IOMUXC_GPIO_EMC_30_GPIO4_IO30 0x401F808CU, 0x5U, 0, 0, 0x401F827CU + +#define IOMUXC_GPIO_EMC_31_SEMC_DATA09 0x401F8090U, 0x0U, 0, 0, 0x401F8280U +#define IOMUXC_GPIO_EMC_31_FLEXPWM3_PWMA01 0x401F8090U, 0x1U, 0, 0, 0x401F8280U +#define IOMUXC_GPIO_EMC_31_LPUART7_TX 0x401F8090U, 0x2U, 0x401F855CU, 0x1U, 0x401F8280U +#define IOMUXC_GPIO_EMC_31_LPSPI1_PCS1 0x401F8090U, 0x3U, 0, 0, 0x401F8280U +#define IOMUXC_GPIO_EMC_31_CSI_DATA22 0x401F8090U, 0x4U, 0, 0, 0x401F8280U +#define IOMUXC_GPIO_EMC_31_GPIO4_IO31 0x401F8090U, 0x5U, 0, 0, 0x401F8280U + +#define IOMUXC_GPIO_EMC_32_SEMC_DATA10 0x401F8094U, 0x0U, 0, 0, 0x401F8284U +#define IOMUXC_GPIO_EMC_32_FLEXPWM3_PWMB01 0x401F8094U, 0x1U, 0, 0, 0x401F8284U +#define IOMUXC_GPIO_EMC_32_LPUART7_RX 0x401F8094U, 0x2U, 0x401F8558U, 0x1U, 0x401F8284U +#define IOMUXC_GPIO_EMC_32_CCM_PMIC_RDY 0x401F8094U, 0x3U, 0x401F83FCU, 0x4U, 0x401F8284U +#define IOMUXC_GPIO_EMC_32_CSI_DATA21 0x401F8094U, 0x4U, 0, 0, 0x401F8284U +#define IOMUXC_GPIO_EMC_32_GPIO3_IO18 0x401F8094U, 0x5U, 0, 0, 0x401F8284U + +#define IOMUXC_GPIO_EMC_33_SEMC_DATA11 0x401F8098U, 0x0U, 0, 0, 0x401F8288U +#define IOMUXC_GPIO_EMC_33_FLEXPWM3_PWMA02 0x401F8098U, 0x1U, 0, 0, 0x401F8288U +#define IOMUXC_GPIO_EMC_33_USDHC1_RESET_B 0x401F8098U, 0x2U, 0, 0, 0x401F8288U +#define IOMUXC_GPIO_EMC_33_SAI3_RX_DATA 0x401F8098U, 0x3U, 0, 0, 0x401F8288U +#define IOMUXC_GPIO_EMC_33_CSI_DATA20 0x401F8098U, 0x4U, 0, 0, 0x401F8288U +#define IOMUXC_GPIO_EMC_33_GPIO3_IO19 0x401F8098U, 0x5U, 0, 0, 0x401F8288U + +#define IOMUXC_GPIO_EMC_34_SEMC_DATA12 0x401F809CU, 0x0U, 0, 0, 0x401F828CU +#define IOMUXC_GPIO_EMC_34_FLEXPWM3_PWMB02 0x401F809CU, 0x1U, 0, 0, 0x401F828CU +#define IOMUXC_GPIO_EMC_34_USDHC1_VSELECT 0x401F809CU, 0x2U, 0, 0, 0x401F828CU +#define IOMUXC_GPIO_EMC_34_SAI3_RX_SYNC 0x401F809CU, 0x3U, 0, 0, 0x401F828CU +#define IOMUXC_GPIO_EMC_34_CSI_DATA19 0x401F809CU, 0x4U, 0, 0, 0x401F828CU +#define IOMUXC_GPIO_EMC_34_GPIO3_IO20 0x401F809CU, 0x5U, 0, 0, 0x401F828CU + +#define IOMUXC_GPIO_EMC_35_SEMC_DATA13 0x401F80A0U, 0x0U, 0, 0, 0x401F8290U +#define IOMUXC_GPIO_EMC_35_XBAR1_INOUT18 0x401F80A0U, 0x1U, 0x401F8630U, 0x0U, 0x401F8290U +#define IOMUXC_GPIO_EMC_35_GPT1_COMPARE1 0x401F80A0U, 0x2U, 0, 0, 0x401F8290U +#define IOMUXC_GPIO_EMC_35_SAI3_RX_BCLK 0x401F80A0U, 0x3U, 0, 0, 0x401F8290U +#define IOMUXC_GPIO_EMC_35_CSI_DATA18 0x401F80A0U, 0x4U, 0, 0, 0x401F8290U +#define IOMUXC_GPIO_EMC_35_GPIO3_IO21 0x401F80A0U, 0x5U, 0, 0, 0x401F8290U +#define IOMUXC_GPIO_EMC_35_USDHC1_CD_B 0x401F80A0U, 0x6U, 0x401F85D4U, 0x0U, 0x401F8290U + +#define IOMUXC_GPIO_EMC_36_SEMC_DATA14 0x401F80A4U, 0x0U, 0, 0, 0x401F8294U +#define IOMUXC_GPIO_EMC_36_XBAR1_IN22 0x401F80A4U, 0x1U, 0x401F8638U, 0x0U, 0x401F8294U +#define IOMUXC_GPIO_EMC_36_GPT1_COMPARE2 0x401F80A4U, 0x2U, 0, 0, 0x401F8294U +#define IOMUXC_GPIO_EMC_36_SAI3_TX_DATA 0x401F80A4U, 0x3U, 0, 0, 0x401F8294U +#define IOMUXC_GPIO_EMC_36_CSI_DATA17 0x401F80A4U, 0x4U, 0, 0, 0x401F8294U +#define IOMUXC_GPIO_EMC_36_GPIO3_IO22 0x401F80A4U, 0x5U, 0, 0, 0x401F8294U +#define IOMUXC_GPIO_EMC_36_USDHC1_WP 0x401F80A4U, 0x6U, 0x401F85D8U, 0x1U, 0x401F8294U + +#define IOMUXC_GPIO_EMC_37_SEMC_DATA15 0x401F80A8U, 0x0U, 0, 0, 0x401F8298U +#define IOMUXC_GPIO_EMC_37_XBAR1_IN23 0x401F80A8U, 0x1U, 0x401F863CU, 0x0U, 0x401F8298U +#define IOMUXC_GPIO_EMC_37_GPT1_COMPARE3 0x401F80A8U, 0x2U, 0, 0, 0x401F8298U +#define IOMUXC_GPIO_EMC_37_SAI3_MCLK 0x401F80A8U, 0x3U, 0, 0, 0x401F8298U +#define IOMUXC_GPIO_EMC_37_CSI_DATA16 0x401F80A8U, 0x4U, 0, 0, 0x401F8298U +#define IOMUXC_GPIO_EMC_37_GPIO3_IO23 0x401F80A8U, 0x5U, 0, 0, 0x401F8298U +#define IOMUXC_GPIO_EMC_37_USDHC2_WP 0x401F80A8U, 0x6U, 0x401F8608U, 0x0U, 0x401F8298U + +#define IOMUXC_GPIO_EMC_38_SEMC_DM01 0x401F80ACU, 0x0U, 0, 0, 0x401F829CU +#define IOMUXC_GPIO_EMC_38_FLEXPWM1_PWMA03 0x401F80ACU, 0x1U, 0x401F8454U, 0x2U, 0x401F829CU +#define IOMUXC_GPIO_EMC_38_LPUART8_TX 0x401F80ACU, 0x2U, 0x401F8564U, 0x2U, 0x401F829CU +#define IOMUXC_GPIO_EMC_38_SAI3_TX_BCLK 0x401F80ACU, 0x3U, 0, 0, 0x401F829CU +#define IOMUXC_GPIO_EMC_38_CSI_FIELD 0x401F80ACU, 0x4U, 0, 0, 0x401F829CU +#define IOMUXC_GPIO_EMC_38_GPIO3_IO24 0x401F80ACU, 0x5U, 0, 0, 0x401F829CU +#define IOMUXC_GPIO_EMC_38_USDHC2_VSELECT 0x401F80ACU, 0x6U, 0, 0, 0x401F829CU + +#define IOMUXC_GPIO_EMC_39_SEMC_DQS 0x401F80B0U, 0x0U, 0, 0, 0x401F82A0U +#define IOMUXC_GPIO_EMC_39_FLEXPWM1_PWMB03 0x401F80B0U, 0x1U, 0x401F8464U, 0x2U, 0x401F82A0U +#define IOMUXC_GPIO_EMC_39_LPUART8_RX 0x401F80B0U, 0x2U, 0x401F8560U, 0x2U, 0x401F82A0U +#define IOMUXC_GPIO_EMC_39_SAI3_TX_SYNC 0x401F80B0U, 0x3U, 0, 0, 0x401F82A0U +#define IOMUXC_GPIO_EMC_39_WDOG1_WDOG_B 0x401F80B0U, 0x4U, 0, 0, 0x401F82A0U +#define IOMUXC_GPIO_EMC_39_GPIO3_IO25 0x401F80B0U, 0x5U, 0, 0, 0x401F82A0U +#define IOMUXC_GPIO_EMC_39_USDHC2_CD_B 0x401F80B0U, 0x6U, 0x401F85E0U, 0x1U, 0x401F82A0U + +#define IOMUXC_GPIO_EMC_40_SEMC_RDY 0x401F80B4U, 0x0U, 0, 0, 0x401F82A4U +#define IOMUXC_GPIO_EMC_40_GPT2_CAPTURE2 0x401F80B4U, 0x1U, 0, 0, 0x401F82A4U +#define IOMUXC_GPIO_EMC_40_LPSPI1_PCS2 0x401F80B4U, 0x2U, 0, 0, 0x401F82A4U +#define IOMUXC_GPIO_EMC_40_USB_OTG2_OC 0x401F80B4U, 0x3U, 0x401F85CCU, 0x1U, 0x401F82A4U +#define IOMUXC_GPIO_EMC_40_ENET_MDC 0x401F80B4U, 0x4U, 0, 0, 0x401F82A4U +#define IOMUXC_GPIO_EMC_40_GPIO3_IO26 0x401F80B4U, 0x5U, 0, 0, 0x401F82A4U +#define IOMUXC_GPIO_EMC_40_USDHC2_RESET_B 0x401F80B4U, 0x6U, 0, 0, 0x401F82A4U + +#define IOMUXC_GPIO_EMC_41_SEMC_CSX00 0x401F80B8U, 0x0U, 0, 0, 0x401F82A8U +#define IOMUXC_GPIO_EMC_41_GPT2_CAPTURE1 0x401F80B8U, 0x1U, 0, 0, 0x401F82A8U +#define IOMUXC_GPIO_EMC_41_LPSPI1_PCS3 0x401F80B8U, 0x2U, 0, 0, 0x401F82A8U +#define IOMUXC_GPIO_EMC_41_USB_OTG2_PWR 0x401F80B8U, 0x3U, 0, 0, 0x401F82A8U +#define IOMUXC_GPIO_EMC_41_ENET_MDIO 0x401F80B8U, 0x4U, 0x401F8430U, 0x1U, 0x401F82A8U +#define IOMUXC_GPIO_EMC_41_GPIO3_IO27 0x401F80B8U, 0x5U, 0, 0, 0x401F82A8U +#define IOMUXC_GPIO_EMC_41_USDHC1_VSELECT 0x401F80B8U, 0x6U, 0, 0, 0x401F82A8U + +#define IOMUXC_GPIO_AD_B0_00_FLEXPWM2_PWMA03 0x401F80BCU, 0x0U, 0x401F8474U, 0x2U, 0x401F82ACU +#define IOMUXC_GPIO_AD_B0_00_XBAR1_INOUT14 0x401F80BCU, 0x1U, 0x401F8644U, 0x0U, 0x401F82ACU +#define IOMUXC_GPIO_AD_B0_00_REF_CLK_32K 0x401F80BCU, 0x2U, 0, 0, 0x401F82ACU +#define IOMUXC_GPIO_AD_B0_00_USB_OTG2_ID 0x401F80BCU, 0x3U, 0x401F83F8U, 0x0U, 0x401F82ACU +#define IOMUXC_GPIO_AD_B0_00_LPI2C1_SCLS 0x401F80BCU, 0x4U, 0, 0, 0x401F82ACU +#define IOMUXC_GPIO_AD_B0_00_GPIO1_IO00 0x401F80BCU, 0x5U, 0, 0, 0x401F82ACU +#define IOMUXC_GPIO_AD_B0_00_USDHC1_RESET_B 0x401F80BCU, 0x6U, 0, 0, 0x401F82ACU +#define IOMUXC_GPIO_AD_B0_00_LPSPI3_SCK 0x401F80BCU, 0x7U, 0x401F8510U, 0x0U, 0x401F82ACU + +#define IOMUXC_GPIO_AD_B0_01_FLEXPWM2_PWMB03 0x401F80C0U, 0x0U, 0x401F8484U, 0x2U, 0x401F82B0U +#define IOMUXC_GPIO_AD_B0_01_XBAR1_INOUT15 0x401F80C0U, 0x1U, 0x401F8648U, 0x0U, 0x401F82B0U +#define IOMUXC_GPIO_AD_B0_01_REF_CLK_24M 0x401F80C0U, 0x2U, 0, 0, 0x401F82B0U +#define IOMUXC_GPIO_AD_B0_01_USB_OTG1_ID 0x401F80C0U, 0x3U, 0x401F83F4U, 0x0U, 0x401F82B0U +#define IOMUXC_GPIO_AD_B0_01_LPI2C1_SDAS 0x401F80C0U, 0x4U, 0, 0, 0x401F82B0U +#define IOMUXC_GPIO_AD_B0_01_GPIO1_IO01 0x401F80C0U, 0x5U, 0, 0, 0x401F82B0U +#define IOMUXC_GPIO_AD_B0_01_EWM_OUT_B 0x401F80C0U, 0x6U, 0, 0, 0x401F82B0U +#define IOMUXC_GPIO_AD_B0_01_LPSPI3_SDO 0x401F80C0U, 0x7U, 0x401F8518U, 0x0U, 0x401F82B0U + +#define IOMUXC_GPIO_AD_B0_02_FLEXCAN2_TX 0x401F80C4U, 0x0U, 0, 0, 0x401F82B4U +#define IOMUXC_GPIO_AD_B0_02_XBAR1_INOUT16 0x401F80C4U, 0x1U, 0x401F864CU, 0x0U, 0x401F82B4U +#define IOMUXC_GPIO_AD_B0_02_LPUART6_TX 0x401F80C4U, 0x2U, 0x401F8554U, 0x1U, 0x401F82B4U +#define IOMUXC_GPIO_AD_B0_02_USB_OTG1_PWR 0x401F80C4U, 0x3U, 0, 0, 0x401F82B4U +#define IOMUXC_GPIO_AD_B0_02_FLEXPWM1_PWMX00 0x401F80C4U, 0x4U, 0, 0, 0x401F82B4U +#define IOMUXC_GPIO_AD_B0_02_GPIO1_IO02 0x401F80C4U, 0x5U, 0, 0, 0x401F82B4U +#define IOMUXC_GPIO_AD_B0_02_LPI2C1_HREQ 0x401F80C4U, 0x6U, 0, 0, 0x401F82B4U +#define IOMUXC_GPIO_AD_B0_02_LPSPI3_SDI 0x401F80C4U, 0x7U, 0x401F8514U, 0x0U, 0x401F82B4U + +#define IOMUXC_GPIO_AD_B0_03_FLEXCAN2_RX 0x401F80C8U, 0x0U, 0x401F8450U, 0x1U, 0x401F82B8U +#define IOMUXC_GPIO_AD_B0_03_XBAR1_INOUT17 0x401F80C8U, 0x1U, 0x401F862CU, 0x1U, 0x401F82B8U +#define IOMUXC_GPIO_AD_B0_03_LPUART6_RX 0x401F80C8U, 0x2U, 0x401F8550U, 0x1U, 0x401F82B8U +#define IOMUXC_GPIO_AD_B0_03_USB_OTG1_OC 0x401F80C8U, 0x3U, 0x401F85D0U, 0x0U, 0x401F82B8U +#define IOMUXC_GPIO_AD_B0_03_FLEXPWM1_PWMX01 0x401F80C8U, 0x4U, 0, 0, 0x401F82B8U +#define IOMUXC_GPIO_AD_B0_03_GPIO1_IO03 0x401F80C8U, 0x5U, 0, 0, 0x401F82B8U +#define IOMUXC_GPIO_AD_B0_03_REF_CLK_24M 0x401F80C8U, 0x6U, 0, 0, 0x401F82B8U +#define IOMUXC_GPIO_AD_B0_03_LPSPI3_PCS0 0x401F80C8U, 0x7U, 0x401F850CU, 0x0U, 0x401F82B8U + +#define IOMUXC_GPIO_AD_B0_04_SRC_BOOT_MODE00 0x401F80CCU, 0x0U, 0, 0, 0x401F82BCU +#define IOMUXC_GPIO_AD_B0_04_MQS_RIGHT 0x401F80CCU, 0x1U, 0, 0, 0x401F82BCU +#define IOMUXC_GPIO_AD_B0_04_ENET_TX_DATA03 0x401F80CCU, 0x2U, 0, 0, 0x401F82BCU +#define IOMUXC_GPIO_AD_B0_04_SAI2_TX_SYNC 0x401F80CCU, 0x3U, 0x401F85C4U, 0x1U, 0x401F82BCU +#define IOMUXC_GPIO_AD_B0_04_CSI_DATA09 0x401F80CCU, 0x4U, 0x401F841CU, 0x1U, 0x401F82BCU +#define IOMUXC_GPIO_AD_B0_04_GPIO1_IO04 0x401F80CCU, 0x5U, 0, 0, 0x401F82BCU +#define IOMUXC_GPIO_AD_B0_04_PIT_TRIGGER00 0x401F80CCU, 0x6U, 0, 0, 0x401F82BCU +#define IOMUXC_GPIO_AD_B0_04_LPSPI3_PCS1 0x401F80CCU, 0x7U, 0, 0, 0x401F82BCU + +#define IOMUXC_GPIO_AD_B0_05_SRC_BOOT_MODE01 0x401F80D0U, 0x0U, 0, 0, 0x401F82C0U +#define IOMUXC_GPIO_AD_B0_05_MQS_LEFT 0x401F80D0U, 0x1U, 0, 0, 0x401F82C0U +#define IOMUXC_GPIO_AD_B0_05_ENET_TX_DATA02 0x401F80D0U, 0x2U, 0, 0, 0x401F82C0U +#define IOMUXC_GPIO_AD_B0_05_SAI2_TX_BCLK 0x401F80D0U, 0x3U, 0x401F85C0U, 0x1U, 0x401F82C0U +#define IOMUXC_GPIO_AD_B0_05_CSI_DATA08 0x401F80D0U, 0x4U, 0x401F8418U, 0x1U, 0x401F82C0U +#define IOMUXC_GPIO_AD_B0_05_GPIO1_IO05 0x401F80D0U, 0x5U, 0, 0, 0x401F82C0U +#define IOMUXC_GPIO_AD_B0_05_XBAR1_INOUT17 0x401F80D0U, 0x6U, 0x401F862CU, 0x2U, 0x401F82C0U +#define IOMUXC_GPIO_AD_B0_05_LPSPI3_PCS2 0x401F80D0U, 0x7U, 0, 0, 0x401F82C0U + +#define IOMUXC_GPIO_AD_B0_06_JTAG_TMS 0x401F80D4U, 0x0U, 0, 0, 0x401F82C4U +#define IOMUXC_GPIO_AD_B0_06_GPT2_COMPARE1 0x401F80D4U, 0x1U, 0, 0, 0x401F82C4U +#define IOMUXC_GPIO_AD_B0_06_ENET_RX_CLK 0x401F80D4U, 0x2U, 0, 0, 0x401F82C4U +#define IOMUXC_GPIO_AD_B0_06_SAI2_RX_BCLK 0x401F80D4U, 0x3U, 0x401F85B4U, 0x1U, 0x401F82C4U +#define IOMUXC_GPIO_AD_B0_06_CSI_DATA07 0x401F80D4U, 0x4U, 0x401F8414U, 0x1U, 0x401F82C4U +#define IOMUXC_GPIO_AD_B0_06_GPIO1_IO06 0x401F80D4U, 0x5U, 0, 0, 0x401F82C4U +#define IOMUXC_GPIO_AD_B0_06_XBAR1_INOUT18 0x401F80D4U, 0x6U, 0x401F8630U, 0x1U, 0x401F82C4U +#define IOMUXC_GPIO_AD_B0_06_LPSPI3_PCS3 0x401F80D4U, 0x7U, 0, 0, 0x401F82C4U + +#define IOMUXC_GPIO_AD_B0_07_JTAG_TCK 0x401F80D8U, 0x0U, 0, 0, 0x401F82C8U +#define IOMUXC_GPIO_AD_B0_07_GPT2_COMPARE2 0x401F80D8U, 0x1U, 0, 0, 0x401F82C8U +#define IOMUXC_GPIO_AD_B0_07_ENET_TX_ER 0x401F80D8U, 0x2U, 0, 0, 0x401F82C8U +#define IOMUXC_GPIO_AD_B0_07_SAI2_RX_SYNC 0x401F80D8U, 0x3U, 0x401F85BCU, 0x1U, 0x401F82C8U +#define IOMUXC_GPIO_AD_B0_07_CSI_DATA06 0x401F80D8U, 0x4U, 0x401F8410U, 0x1U, 0x401F82C8U +#define IOMUXC_GPIO_AD_B0_07_GPIO1_IO07 0x401F80D8U, 0x5U, 0, 0, 0x401F82C8U +#define IOMUXC_GPIO_AD_B0_07_XBAR1_INOUT19 0x401F80D8U, 0x6U, 0x401F8654U, 0x1U, 0x401F82C8U +#define IOMUXC_GPIO_AD_B0_07_ENET_1588_EVENT3_OUT 0x401F80D8U, 0x7U, 0, 0, 0x401F82C8U + +#define IOMUXC_GPIO_AD_B0_08_JTAG_MOD 0x401F80DCU, 0x0U, 0, 0, 0x401F82CCU +#define IOMUXC_GPIO_AD_B0_08_GPT2_COMPARE3 0x401F80DCU, 0x1U, 0, 0, 0x401F82CCU +#define IOMUXC_GPIO_AD_B0_08_ENET_RX_DATA03 0x401F80DCU, 0x2U, 0, 0, 0x401F82CCU +#define IOMUXC_GPIO_AD_B0_08_SAI2_RX_DATA 0x401F80DCU, 0x3U, 0x401F85B8U, 0x1U, 0x401F82CCU +#define IOMUXC_GPIO_AD_B0_08_CSI_DATA05 0x401F80DCU, 0x4U, 0x401F840CU, 0x1U, 0x401F82CCU +#define IOMUXC_GPIO_AD_B0_08_GPIO1_IO08 0x401F80DCU, 0x5U, 0, 0, 0x401F82CCU +#define IOMUXC_GPIO_AD_B0_08_XBAR1_IN20 0x401F80DCU, 0x6U, 0x401F8634U, 0x1U, 0x401F82CCU +#define IOMUXC_GPIO_AD_B0_08_ENET_1588_EVENT3_IN 0x401F80DCU, 0x7U, 0, 0, 0x401F82CCU + +#define IOMUXC_GPIO_AD_B0_09_JTAG_TDI 0x401F80E0U, 0x0U, 0, 0, 0x401F82D0U +#define IOMUXC_GPIO_AD_B0_09_FLEXPWM2_PWMA03 0x401F80E0U, 0x1U, 0x401F8474U, 0x3U, 0x401F82D0U +#define IOMUXC_GPIO_AD_B0_09_ENET_RX_DATA02 0x401F80E0U, 0x2U, 0, 0, 0x401F82D0U +#define IOMUXC_GPIO_AD_B0_09_SAI2_TX_DATA 0x401F80E0U, 0x3U, 0, 0, 0x401F82D0U +#define IOMUXC_GPIO_AD_B0_09_CSI_DATA04 0x401F80E0U, 0x4U, 0x401F8408U, 0x1U, 0x401F82D0U +#define IOMUXC_GPIO_AD_B0_09_GPIO1_IO09 0x401F80E0U, 0x5U, 0, 0, 0x401F82D0U +#define IOMUXC_GPIO_AD_B0_09_XBAR1_IN21 0x401F80E0U, 0x6U, 0x401F8658U, 0x1U, 0x401F82D0U +#define IOMUXC_GPIO_AD_B0_09_GPT2_CLK 0x401F80E0U, 0x7U, 0, 0, 0x401F82D0U + +#define IOMUXC_GPIO_AD_B0_10_JTAG_TDO 0x401F80E4U, 0x0U, 0, 0, 0x401F82D4U +#define IOMUXC_GPIO_AD_B0_10_FLEXPWM1_PWMA03 0x401F80E4U, 0x1U, 0x401F8454U, 0x3U, 0x401F82D4U +#define IOMUXC_GPIO_AD_B0_10_ENET_CRS 0x401F80E4U, 0x2U, 0, 0, 0x401F82D4U +#define IOMUXC_GPIO_AD_B0_10_SAI2_MCLK 0x401F80E4U, 0x3U, 0x401F85B0U, 0x1U, 0x401F82D4U +#define IOMUXC_GPIO_AD_B0_10_CSI_DATA03 0x401F80E4U, 0x4U, 0x401F8404U, 0x1U, 0x401F82D4U +#define IOMUXC_GPIO_AD_B0_10_GPIO1_IO10 0x401F80E4U, 0x5U, 0, 0, 0x401F82D4U +#define IOMUXC_GPIO_AD_B0_10_XBAR1_IN22 0x401F80E4U, 0x6U, 0x401F8638U, 0x1U, 0x401F82D4U +#define IOMUXC_GPIO_AD_B0_10_ENET_1588_EVENT0_OUT 0x401F80E4U, 0x7U, 0, 0, 0x401F82D4U + +#define IOMUXC_GPIO_AD_B0_11_JTAG_TRSTB 0x401F80E8U, 0x0U, 0, 0, 0x401F82D8U +#define IOMUXC_GPIO_AD_B0_11_FLEXPWM1_PWMB03 0x401F80E8U, 0x1U, 0x401F8464U, 0x3U, 0x401F82D8U +#define IOMUXC_GPIO_AD_B0_11_ENET_COL 0x401F80E8U, 0x2U, 0, 0, 0x401F82D8U +#define IOMUXC_GPIO_AD_B0_11_WDOG1_WDOG_B 0x401F80E8U, 0x3U, 0, 0, 0x401F82D8U +#define IOMUXC_GPIO_AD_B0_11_CSI_DATA02 0x401F80E8U, 0x4U, 0x401F8400U, 0x1U, 0x401F82D8U +#define IOMUXC_GPIO_AD_B0_11_GPIO1_IO11 0x401F80E8U, 0x5U, 0, 0, 0x401F82D8U +#define IOMUXC_GPIO_AD_B0_11_XBAR1_IN23 0x401F80E8U, 0x6U, 0x401F863CU, 0x1U, 0x401F82D8U +#define IOMUXC_GPIO_AD_B0_11_ENET_1588_EVENT0_IN 0x401F80E8U, 0x7U, 0x401F8444U, 0x1U, 0x401F82D8U + +#define IOMUXC_GPIO_AD_B0_12_LPI2C4_SCL 0x401F80ECU, 0x0U, 0x401F84E4U, 0x1U, 0x401F82DCU +#define IOMUXC_GPIO_AD_B0_12_CCM_PMIC_READY 0x401F80ECU, 0x1U, 0x401F83FCU, 0x1U, 0x401F82DCU +#define IOMUXC_GPIO_AD_B0_12_LPUART1_TX 0x401F80ECU, 0x2U, 0, 0, 0x401F82DCU +#define IOMUXC_GPIO_AD_B0_12_WDOG2_WDOG_B 0x401F80ECU, 0x3U, 0, 0, 0x401F82DCU +#define IOMUXC_GPIO_AD_B0_12_FLEXPWM1_PWMX02 0x401F80ECU, 0x4U, 0, 0, 0x401F82DCU +#define IOMUXC_GPIO_AD_B0_12_GPIO1_IO12 0x401F80ECU, 0x5U, 0, 0, 0x401F82DCU +#define IOMUXC_GPIO_AD_B0_12_ENET_1588_EVENT1_OUT 0x401F80ECU, 0x6U, 0, 0, 0x401F82DCU +#define IOMUXC_GPIO_AD_B0_12_NMI_GLUE_NMI 0x401F80ECU, 0x7U, 0x401F8568U, 0x0U, 0x401F82DCU + +#define IOMUXC_GPIO_AD_B0_13_LPI2C4_SDA 0x401F80F0U, 0x0U, 0x401F84E8U, 0x1U, 0x401F82E0U +#define IOMUXC_GPIO_AD_B0_13_GPT1_CLK 0x401F80F0U, 0x1U, 0, 0, 0x401F82E0U +#define IOMUXC_GPIO_AD_B0_13_LPUART1_RX 0x401F80F0U, 0x2U, 0, 0, 0x401F82E0U +#define IOMUXC_GPIO_AD_B0_13_EWM_OUT_B 0x401F80F0U, 0x3U, 0, 0, 0x401F82E0U +#define IOMUXC_GPIO_AD_B0_13_FLEXPWM1_PWMX03 0x401F80F0U, 0x4U, 0, 0, 0x401F82E0U +#define IOMUXC_GPIO_AD_B0_13_GPIO1_IO13 0x401F80F0U, 0x5U, 0, 0, 0x401F82E0U +#define IOMUXC_GPIO_AD_B0_13_ENET_1588_EVENT1_IN 0x401F80F0U, 0x6U, 0, 0, 0x401F82E0U +#define IOMUXC_GPIO_AD_B0_13_REF_CLK_24M 0x401F80F0U, 0x7U, 0, 0, 0x401F82E0U + +#define IOMUXC_GPIO_AD_B0_14_USB_OTG2_OC 0x401F80F4U, 0x0U, 0x401F85CCU, 0x0U, 0x401F82E4U +#define IOMUXC_GPIO_AD_B0_14_XBAR1_IN24 0x401F80F4U, 0x1U, 0x401F8640U, 0x1U, 0x401F82E4U +#define IOMUXC_GPIO_AD_B0_14_LPUART1_CTS_B 0x401F80F4U, 0x2U, 0, 0, 0x401F82E4U +#define IOMUXC_GPIO_AD_B0_14_ENET_1588_EVENT0_OUT 0x401F80F4U, 0x3U, 0, 0, 0x401F82E4U +#define IOMUXC_GPIO_AD_B0_14_CSI_VSYNC 0x401F80F4U, 0x4U, 0x401F8428U, 0x0U, 0x401F82E4U +#define IOMUXC_GPIO_AD_B0_14_GPIO1_IO14 0x401F80F4U, 0x5U, 0, 0, 0x401F82E4U +#define IOMUXC_GPIO_AD_B0_14_FLEXCAN2_TX 0x401F80F4U, 0x6U, 0, 0, 0x401F82E4U + +#define IOMUXC_GPIO_AD_B0_15_USB_OTG2_PWR 0x401F80F8U, 0x0U, 0, 0, 0x401F82E8U +#define IOMUXC_GPIO_AD_B0_15_XBAR1_IN25 0x401F80F8U, 0x1U, 0x401F8650U, 0x0U, 0x401F82E8U +#define IOMUXC_GPIO_AD_B0_15_LPUART1_RTS_B 0x401F80F8U, 0x2U, 0, 0, 0x401F82E8U +#define IOMUXC_GPIO_AD_B0_15_ENET_1588_EVENT0_IN 0x401F80F8U, 0x3U, 0x401F8444U, 0x0U, 0x401F82E8U +#define IOMUXC_GPIO_AD_B0_15_CSI_HSYNC 0x401F80F8U, 0x4U, 0x401F8420U, 0x0U, 0x401F82E8U +#define IOMUXC_GPIO_AD_B0_15_GPIO1_IO15 0x401F80F8U, 0x5U, 0, 0, 0x401F82E8U +#define IOMUXC_GPIO_AD_B0_15_FLEXCAN2_RX 0x401F80F8U, 0x6U, 0x401F8450U, 0x2U, 0x401F82E8U +#define IOMUXC_GPIO_AD_B0_15_WDOG1_WDOG_RST_B_DEB 0x401F80F8U, 0x7U, 0, 0, 0x401F82E8U + +#define IOMUXC_GPIO_AD_B1_00_USB_OTG2_ID 0x401F80FCU, 0x0U, 0x401F83F8U, 0x1U, 0x401F82ECU +#define IOMUXC_GPIO_AD_B1_00_QTIMER3_TIMER0 0x401F80FCU, 0x1U, 0x401F857CU, 0x1U, 0x401F82ECU +#define IOMUXC_GPIO_AD_B1_00_LPUART2_CTS_B 0x401F80FCU, 0x2U, 0, 0, 0x401F82ECU +#define IOMUXC_GPIO_AD_B1_00_LPI2C1_SCL 0x401F80FCU, 0x3U, 0x401F84CCU, 0x1U, 0x401F82ECU +#define IOMUXC_GPIO_AD_B1_00_WDOG1_B 0x401F80FCU, 0x4U, 0, 0, 0x401F82ECU +#define IOMUXC_GPIO_AD_B1_00_GPIO1_IO16 0x401F80FCU, 0x5U, 0, 0, 0x401F82ECU +#define IOMUXC_GPIO_AD_B1_00_USDHC1_WP 0x401F80FCU, 0x6U, 0x401F85D8U, 0x2U, 0x401F82ECU +#define IOMUXC_GPIO_AD_B1_00_KPP_ROW07 0x401F80FCU, 0x7U, 0, 0, 0x401F82ECU + +#define IOMUXC_GPIO_AD_B1_01_USB_OTG1_PWR 0x401F8100U, 0x0U, 0, 0, 0x401F82F0U +#define IOMUXC_GPIO_AD_B1_01_QTIMER3_TIMER1 0x401F8100U, 0x1U, 0x401F8580U, 0x0U, 0x401F82F0U +#define IOMUXC_GPIO_AD_B1_01_LPUART2_RTS_B 0x401F8100U, 0x2U, 0, 0, 0x401F82F0U +#define IOMUXC_GPIO_AD_B1_01_LPI2C1_SDA 0x401F8100U, 0x3U, 0x401F84D0U, 0x1U, 0x401F82F0U +#define IOMUXC_GPIO_AD_B1_01_CCM_PMIC_READY 0x401F8100U, 0x4U, 0x401F83FCU, 0x2U, 0x401F82F0U +#define IOMUXC_GPIO_AD_B1_01_GPIO1_IO17 0x401F8100U, 0x5U, 0, 0, 0x401F82F0U +#define IOMUXC_GPIO_AD_B1_01_USDHC1_VSELECT 0x401F8100U, 0x6U, 0, 0, 0x401F82F0U +#define IOMUXC_GPIO_AD_B1_01_KPP_COL07 0x401F8100U, 0x7U, 0, 0, 0x401F82F0U + +#define IOMUXC_GPIO_AD_B1_02_USB_OTG1_ID 0x401F8104U, 0x0U, 0x401F83F4U, 0x1U, 0x401F82F4U +#define IOMUXC_GPIO_AD_B1_02_QTIMER3_TIMER2 0x401F8104U, 0x1U, 0x401F8584U, 0x1U, 0x401F82F4U +#define IOMUXC_GPIO_AD_B1_02_LPUART2_TX 0x401F8104U, 0x2U, 0x401F8530U, 0x1U, 0x401F82F4U +#define IOMUXC_GPIO_AD_B1_02_SPDIF_OUT 0x401F8104U, 0x3U, 0, 0, 0x401F82F4U +#define IOMUXC_GPIO_AD_B1_02_ENET_1588_EVENT2_OUT 0x401F8104U, 0x4U, 0, 0, 0x401F82F4U +#define IOMUXC_GPIO_AD_B1_02_GPIO1_IO18 0x401F8104U, 0x5U, 0, 0, 0x401F82F4U +#define IOMUXC_GPIO_AD_B1_02_USDHC1_CD_B 0x401F8104U, 0x6U, 0x401F85D4U, 0x1U, 0x401F82F4U +#define IOMUXC_GPIO_AD_B1_02_KPP_ROW06 0x401F8104U, 0x7U, 0, 0, 0x401F82F4U + +#define IOMUXC_GPIO_AD_B1_03_USB_OTG1_OC 0x401F8108U, 0x0U, 0x401F85D0U, 0x1U, 0x401F82F8U +#define IOMUXC_GPIO_AD_B1_03_QTIMER3_TIMER3 0x401F8108U, 0x1U, 0x401F8588U, 0x1U, 0x401F82F8U +#define IOMUXC_GPIO_AD_B1_03_LPUART2_RX 0x401F8108U, 0x2U, 0x401F852CU, 0x1U, 0x401F82F8U +#define IOMUXC_GPIO_AD_B1_03_SPDIF_IN 0x401F8108U, 0x3U, 0x401F85C8U, 0x0U, 0x401F82F8U +#define IOMUXC_GPIO_AD_B1_03_ENET_1588_EVENT2_IN 0x401F8108U, 0x4U, 0, 0, 0x401F82F8U +#define IOMUXC_GPIO_AD_B1_03_GPIO1_IO19 0x401F8108U, 0x5U, 0, 0, 0x401F82F8U +#define IOMUXC_GPIO_AD_B1_03_USDHC2_CD_B 0x401F8108U, 0x6U, 0x401F85E0U, 0x0U, 0x401F82F8U +#define IOMUXC_GPIO_AD_B1_03_KPP_COL06 0x401F8108U, 0x7U, 0, 0, 0x401F82F8U + +#define IOMUXC_GPIO_AD_B1_04_FLEXSPIB_DATA03 0x401F810CU, 0x0U, 0x401F84C4U, 0x1U, 0x401F82FCU +#define IOMUXC_GPIO_AD_B1_04_ENET_MDC 0x401F810CU, 0x1U, 0, 0, 0x401F82FCU +#define IOMUXC_GPIO_AD_B1_04_LPUART3_CTS_B 0x401F810CU, 0x2U, 0x401F8534U, 0x1U, 0x401F82FCU +#define IOMUXC_GPIO_AD_B1_04_SPDIF_SR_CLK 0x401F810CU, 0x3U, 0, 0, 0x401F82FCU +#define IOMUXC_GPIO_AD_B1_04_CSI_PIXCLK 0x401F810CU, 0x4U, 0x401F8424U, 0x0U, 0x401F82FCU +#define IOMUXC_GPIO_AD_B1_04_GPIO1_IO20 0x401F810CU, 0x5U, 0, 0, 0x401F82FCU +#define IOMUXC_GPIO_AD_B1_04_USDHC2_DATA0 0x401F810CU, 0x6U, 0x401F85E8U, 0x1U, 0x401F82FCU +#define IOMUXC_GPIO_AD_B1_04_KPP_ROW05 0x401F810CU, 0x7U, 0, 0, 0x401F82FCU + +#define IOMUXC_GPIO_AD_B1_05_FLEXSPIB_DATA02 0x401F8110U, 0x0U, 0x401F84C0U, 0x1U, 0x401F8300U +#define IOMUXC_GPIO_AD_B1_05_ENET_MDIO 0x401F8110U, 0x1U, 0x401F8430U, 0x0U, 0x401F8300U +#define IOMUXC_GPIO_AD_B1_05_LPUART3_RTS_B 0x401F8110U, 0x2U, 0, 0, 0x401F8300U +#define IOMUXC_GPIO_AD_B1_05_SPDIF_OUT 0x401F8110U, 0x3U, 0, 0, 0x401F8300U +#define IOMUXC_GPIO_AD_B1_05_CSI_MCLK 0x401F8110U, 0x4U, 0, 0, 0x401F8300U +#define IOMUXC_GPIO_AD_B1_05_GPIO1_IO21 0x401F8110U, 0x5U, 0, 0, 0x401F8300U +#define IOMUXC_GPIO_AD_B1_05_USDHC2_DATA1 0x401F8110U, 0x6U, 0x401F85ECU, 0x1U, 0x401F8300U +#define IOMUXC_GPIO_AD_B1_05_KPP_COL05 0x401F8110U, 0x7U, 0, 0, 0x401F8300U + +#define IOMUXC_GPIO_AD_B1_06_FLEXSPIB_DATA01 0x401F8114U, 0x0U, 0x401F84BCU, 0x1U, 0x401F8304U +#define IOMUXC_GPIO_AD_B1_06_LPI2C3_SDA 0x401F8114U, 0x1U, 0x401F84E0U, 0x2U, 0x401F8304U +#define IOMUXC_GPIO_AD_B1_06_LPUART3_TX 0x401F8114U, 0x2U, 0x401F853CU, 0x0U, 0x401F8304U +#define IOMUXC_GPIO_AD_B1_06_SPDIF_LOCK 0x401F8114U, 0x3U, 0, 0, 0x401F8304U +#define IOMUXC_GPIO_AD_B1_06_CSI_VSYNC 0x401F8114U, 0x4U, 0x401F8428U, 0x1U, 0x401F8304U +#define IOMUXC_GPIO_AD_B1_06_GPIO1_IO22 0x401F8114U, 0x5U, 0, 0, 0x401F8304U +#define IOMUXC_GPIO_AD_B1_06_USDHC2_DATA2 0x401F8114U, 0x6U, 0x401F85F0U, 0x1U, 0x401F8304U +#define IOMUXC_GPIO_AD_B1_06_KPP_ROW04 0x401F8114U, 0x7U, 0, 0, 0x401F8304U + +#define IOMUXC_GPIO_AD_B1_07_FLEXSPIB_DATA00 0x401F8118U, 0x0U, 0x401F84B8U, 0x1U, 0x401F8308U +#define IOMUXC_GPIO_AD_B1_07_LPI2C3_SCL 0x401F8118U, 0x1U, 0x401F84DCU, 0x2U, 0x401F8308U +#define IOMUXC_GPIO_AD_B1_07_LPUART3_RX 0x401F8118U, 0x2U, 0x401F8538U, 0x0U, 0x401F8308U +#define IOMUXC_GPIO_AD_B1_07_SPDIF_EXT_CLK 0x401F8118U, 0x3U, 0, 0, 0x401F8308U +#define IOMUXC_GPIO_AD_B1_07_CSI_HSYNC 0x401F8118U, 0x4U, 0x401F8420U, 0x1U, 0x401F8308U +#define IOMUXC_GPIO_AD_B1_07_GPIO1_IO23 0x401F8118U, 0x5U, 0, 0, 0x401F8308U +#define IOMUXC_GPIO_AD_B1_07_USDHC2_DATA3 0x401F8118U, 0x6U, 0x401F85F4U, 0x1U, 0x401F8308U +#define IOMUXC_GPIO_AD_B1_07_KPP_COL04 0x401F8118U, 0x7U, 0, 0, 0x401F8308U + +#define IOMUXC_GPIO_AD_B1_08_FLEXSPIA_SS1_B 0x401F811CU, 0x0U, 0, 0, 0x401F830CU +#define IOMUXC_GPIO_AD_B1_08_FLEXPWM4_PWMA00 0x401F811CU, 0x1U, 0x401F8494U, 0x1U, 0x401F830CU +#define IOMUXC_GPIO_AD_B1_08_FLEXCAN1_TX 0x401F811CU, 0x2U, 0, 0, 0x401F830CU +#define IOMUXC_GPIO_AD_B1_08_CCM_PMIC_READY 0x401F811CU, 0x3U, 0x401F83FCU, 0x3U, 0x401F830CU +#define IOMUXC_GPIO_AD_B1_08_CSI_DATA09 0x401F811CU, 0x4U, 0x401F841CU, 0x0U, 0x401F830CU +#define IOMUXC_GPIO_AD_B1_08_GPIO1_IO24 0x401F811CU, 0x5U, 0, 0, 0x401F830CU +#define IOMUXC_GPIO_AD_B1_08_USDHC2_CMD 0x401F811CU, 0x6U, 0x401F85E4U, 0x1U, 0x401F830CU +#define IOMUXC_GPIO_AD_B1_08_KPP_ROW03 0x401F811CU, 0x7U, 0, 0, 0x401F830CU + +#define IOMUXC_GPIO_AD_B1_09_FLEXSPIA_DQS 0x401F8120U, 0x0U, 0x401F84A4U, 0x1U, 0x401F8310U +#define IOMUXC_GPIO_AD_B1_09_FLEXPWM4_PWMA01 0x401F8120U, 0x1U, 0x401F8498U, 0x1U, 0x401F8310U +#define IOMUXC_GPIO_AD_B1_09_FLEXCAN1_RX 0x401F8120U, 0x2U, 0x401F844CU, 0x2U, 0x401F8310U +#define IOMUXC_GPIO_AD_B1_09_SAI1_MCLK 0x401F8120U, 0x3U, 0x401F858CU, 0x1U, 0x401F8310U +#define IOMUXC_GPIO_AD_B1_09_CSI_DATA08 0x401F8120U, 0x4U, 0x401F8418U, 0x0U, 0x401F8310U +#define IOMUXC_GPIO_AD_B1_09_GPIO1_IO25 0x401F8120U, 0x5U, 0, 0, 0x401F8310U +#define IOMUXC_GPIO_AD_B1_09_USDHC2_CLK 0x401F8120U, 0x6U, 0x401F85DCU, 0x1U, 0x401F8310U +#define IOMUXC_GPIO_AD_B1_09_KPP_COL03 0x401F8120U, 0x7U, 0, 0, 0x401F8310U + +#define IOMUXC_GPIO_AD_B1_10_FLEXSPIA_DATA03 0x401F8124U, 0x0U, 0x401F84B4U, 0x1U, 0x401F8314U +#define IOMUXC_GPIO_AD_B1_10_WDOG1_B 0x401F8124U, 0x1U, 0, 0, 0x401F8314U +#define IOMUXC_GPIO_AD_B1_10_LPUART8_TX 0x401F8124U, 0x2U, 0x401F8564U, 0x1U, 0x401F8314U +#define IOMUXC_GPIO_AD_B1_10_SAI1_RX_SYNC 0x401F8124U, 0x3U, 0x401F85A4U, 0x1U, 0x401F8314U +#define IOMUXC_GPIO_AD_B1_10_CSI_DATA07 0x401F8124U, 0x4U, 0x401F8414U, 0x0U, 0x401F8314U +#define IOMUXC_GPIO_AD_B1_10_GPIO1_IO26 0x401F8124U, 0x5U, 0, 0, 0x401F8314U +#define IOMUXC_GPIO_AD_B1_10_USDHC2_WP 0x401F8124U, 0x6U, 0x401F8608U, 0x1U, 0x401F8314U +#define IOMUXC_GPIO_AD_B1_10_KPP_ROW02 0x401F8124U, 0x7U, 0, 0, 0x401F8314U + +#define IOMUXC_GPIO_AD_B1_11_FLEXSPIA_DATA02 0x401F8128U, 0x0U, 0x401F84B0U, 0x1U, 0x401F8318U +#define IOMUXC_GPIO_AD_B1_11_EWM_OUT_B 0x401F8128U, 0x1U, 0, 0, 0x401F8318U +#define IOMUXC_GPIO_AD_B1_11_LPUART8_RX 0x401F8128U, 0x2U, 0x401F8560U, 0x1U, 0x401F8318U +#define IOMUXC_GPIO_AD_B1_11_SAI1_RX_BCLK 0x401F8128U, 0x3U, 0x401F8590U, 0x1U, 0x401F8318U +#define IOMUXC_GPIO_AD_B1_11_CSI_DATA06 0x401F8128U, 0x4U, 0x401F8410U, 0x0U, 0x401F8318U +#define IOMUXC_GPIO_AD_B1_11_GPIO1_IO27 0x401F8128U, 0x5U, 0, 0, 0x401F8318U +#define IOMUXC_GPIO_AD_B1_11_USDHC2_RESET_B 0x401F8128U, 0x6U, 0, 0, 0x401F8318U +#define IOMUXC_GPIO_AD_B1_11_KPP_COL02 0x401F8128U, 0x7U, 0, 0, 0x401F8318U + +#define IOMUXC_GPIO_AD_B1_12_FLEXSPIA_DATA01 0x401F812CU, 0x0U, 0x401F84ACU, 0x1U, 0x401F831CU +#define IOMUXC_GPIO_AD_B1_12_ACMP_OUT00 0x401F812CU, 0x1U, 0, 0, 0x401F831CU +#define IOMUXC_GPIO_AD_B1_12_LPSPI3_PCS0 0x401F812CU, 0x2U, 0x401F850CU, 0x1U, 0x401F831CU +#define IOMUXC_GPIO_AD_B1_12_SAI1_RX_DATA00 0x401F812CU, 0x3U, 0x401F8594U, 0x1U, 0x401F831CU +#define IOMUXC_GPIO_AD_B1_12_CSI_DATA05 0x401F812CU, 0x4U, 0x401F840CU, 0x0U, 0x401F831CU +#define IOMUXC_GPIO_AD_B1_12_GPIO1_IO28 0x401F812CU, 0x5U, 0, 0, 0x401F831CU +#define IOMUXC_GPIO_AD_B1_12_USDHC2_DATA4 0x401F812CU, 0x6U, 0x401F85F8U, 0x1U, 0x401F831CU +#define IOMUXC_GPIO_AD_B1_12_KPP_ROW01 0x401F812CU, 0x7U, 0, 0, 0x401F831CU + +#define IOMUXC_GPIO_AD_B1_13_FLEXSPIA_DATA00 0x401F8130U, 0x0U, 0x401F84A8U, 0x1U, 0x401F8320U +#define IOMUXC_GPIO_AD_B1_13_ACMP_OUT01 0x401F8130U, 0x1U, 0, 0, 0x401F8320U +#define IOMUXC_GPIO_AD_B1_13_LPSPI3_SDI 0x401F8130U, 0x2U, 0x401F8514U, 0x1U, 0x401F8320U +#define IOMUXC_GPIO_AD_B1_13_SAI1_TX_DATA00 0x401F8130U, 0x3U, 0, 0, 0x401F8320U +#define IOMUXC_GPIO_AD_B1_13_CSI_DATA04 0x401F8130U, 0x4U, 0x401F8408U, 0x0U, 0x401F8320U +#define IOMUXC_GPIO_AD_B1_13_GPIO1_IO29 0x401F8130U, 0x5U, 0, 0, 0x401F8320U +#define IOMUXC_GPIO_AD_B1_13_USDHC2_DATA5 0x401F8130U, 0x6U, 0x401F85FCU, 0x1U, 0x401F8320U +#define IOMUXC_GPIO_AD_B1_13_KPP_COL01 0x401F8130U, 0x7U, 0, 0, 0x401F8320U + +#define IOMUXC_GPIO_AD_B1_14_FLEXSPIA_SCLK 0x401F8134U, 0x0U, 0x401F84C8U, 0x1U, 0x401F8324U +#define IOMUXC_GPIO_AD_B1_14_ACMP_OUT02 0x401F8134U, 0x1U, 0, 0, 0x401F8324U +#define IOMUXC_GPIO_AD_B1_14_LPSPI3_SDO 0x401F8134U, 0x2U, 0x401F8518U, 0x1U, 0x401F8324U +#define IOMUXC_GPIO_AD_B1_14_SAI1_TX_BCLK 0x401F8134U, 0x3U, 0x401F85A8U, 0x1U, 0x401F8324U +#define IOMUXC_GPIO_AD_B1_14_CSI_DATA03 0x401F8134U, 0x4U, 0x401F8404U, 0x0U, 0x401F8324U +#define IOMUXC_GPIO_AD_B1_14_GPIO1_IO30 0x401F8134U, 0x5U, 0, 0, 0x401F8324U +#define IOMUXC_GPIO_AD_B1_14_USDHC2_DATA6 0x401F8134U, 0x6U, 0x401F8600U, 0x1U, 0x401F8324U +#define IOMUXC_GPIO_AD_B1_14_KPP_ROW00 0x401F8134U, 0x7U, 0, 0, 0x401F8324U + +#define IOMUXC_GPIO_AD_B1_15_FLEXSPIA_SS0_B 0x401F8138U, 0x0U, 0, 0, 0x401F8328U +#define IOMUXC_GPIO_AD_B1_15_ACMP_OUT03 0x401F8138U, 0x1U, 0, 0, 0x401F8328U +#define IOMUXC_GPIO_AD_B1_15_LPSPI3_SCK 0x401F8138U, 0x2U, 0, 0, 0x401F8328U +#define IOMUXC_GPIO_AD_B1_15_SAI1_TX_SYNC 0x401F8138U, 0x3U, 0x401F85ACU, 0x1U, 0x401F8328U +#define IOMUXC_GPIO_AD_B1_15_CSI_DATA02 0x401F8138U, 0x4U, 0x401F8400U, 0x0U, 0x401F8328U +#define IOMUXC_GPIO_AD_B1_15_GPIO1_IO31 0x401F8138U, 0x5U, 0, 0, 0x401F8328U +#define IOMUXC_GPIO_AD_B1_15_USDHC2_DATA7 0x401F8138U, 0x6U, 0x401F8604U, 0x1U, 0x401F8328U +#define IOMUXC_GPIO_AD_B1_15_KPP_COL00 0x401F8138U, 0x7U, 0, 0, 0x401F8328U + +#define IOMUXC_GPIO_B0_00_LCD_CLK 0x401F813CU, 0x0U, 0, 0, 0x401F832CU +#define IOMUXC_GPIO_B0_00_QTIMER1_TIMER0 0x401F813CU, 0x1U, 0, 0, 0x401F832CU +#define IOMUXC_GPIO_B0_00_MQS_RIGHT 0x401F813CU, 0x2U, 0, 0, 0x401F832CU +#define IOMUXC_GPIO_B0_00_LPSPI4_PCS0 0x401F813CU, 0x3U, 0x401F851CU, 0x0U, 0x401F832CU +#define IOMUXC_GPIO_B0_00_FLEXIO2_FLEXIO00 0x401F813CU, 0x4U, 0, 0, 0x401F832CU +#define IOMUXC_GPIO_B0_00_GPIO2_IO00 0x401F813CU, 0x5U, 0, 0, 0x401F832CU +#define IOMUXC_GPIO_B0_00_SEMC_CSX01 0x401F813CU, 0x6U, 0, 0, 0x401F832CU + +#define IOMUXC_GPIO_B0_01_LCD_ENABLE 0x401F8140U, 0x0U, 0, 0, 0x401F8330U +#define IOMUXC_GPIO_B0_01_QTIMER1_TIMER1 0x401F8140U, 0x1U, 0, 0, 0x401F8330U +#define IOMUXC_GPIO_B0_01_MQS_LEFT 0x401F8140U, 0x2U, 0, 0, 0x401F8330U +#define IOMUXC_GPIO_B0_01_LPSPI4_SDI 0x401F8140U, 0x3U, 0x401F8524U, 0x0U, 0x401F8330U +#define IOMUXC_GPIO_B0_01_FLEXIO2_FLEXIO01 0x401F8140U, 0x4U, 0, 0, 0x401F8330U +#define IOMUXC_GPIO_B0_01_GPIO2_IO01 0x401F8140U, 0x5U, 0, 0, 0x401F8330U +#define IOMUXC_GPIO_B0_01_SEMC_CSX02 0x401F8140U, 0x6U, 0, 0, 0x401F8330U + +#define IOMUXC_GPIO_B0_02_LCD_HSYNC 0x401F8144U, 0x0U, 0, 0, 0x401F8334U +#define IOMUXC_GPIO_B0_02_QTIMER1_TIMER2 0x401F8144U, 0x1U, 0, 0, 0x401F8334U +#define IOMUXC_GPIO_B0_02_FLEXCAN1_TX 0x401F8144U, 0x2U, 0, 0, 0x401F8334U +#define IOMUXC_GPIO_B0_02_LPSPI4_SDO 0x401F8144U, 0x3U, 0x401F8528U, 0x0U, 0x401F8334U +#define IOMUXC_GPIO_B0_02_FLEXIO2_FLEXIO02 0x401F8144U, 0x4U, 0, 0, 0x401F8334U +#define IOMUXC_GPIO_B0_02_GPIO2_IO02 0x401F8144U, 0x5U, 0, 0, 0x401F8334U +#define IOMUXC_GPIO_B0_02_SEMC_CSX03 0x401F8144U, 0x6U, 0, 0, 0x401F8334U + +#define IOMUXC_GPIO_B0_03_LCD_VSYNC 0x401F8148U, 0x0U, 0, 0, 0x401F8338U +#define IOMUXC_GPIO_B0_03_QTIMER2_TIMER0 0x401F8148U, 0x1U, 0x401F856CU, 0x1U, 0x401F8338U +#define IOMUXC_GPIO_B0_03_FLEXCAN1_RX 0x401F8148U, 0x2U, 0x401F844CU, 0x3U, 0x401F8338U +#define IOMUXC_GPIO_B0_03_LPSPI4_SCK 0x401F8148U, 0x3U, 0x401F8520U, 0x0U, 0x401F8338U +#define IOMUXC_GPIO_B0_03_FLEXIO2_FLEXIO03 0x401F8148U, 0x4U, 0, 0, 0x401F8338U +#define IOMUXC_GPIO_B0_03_GPIO2_IO03 0x401F8148U, 0x5U, 0, 0, 0x401F8338U +#define IOMUXC_GPIO_B0_03_WDOG2_RESET_B_DEB 0x401F8148U, 0x6U, 0, 0, 0x401F8338U + +#define IOMUXC_GPIO_B0_04_LCD_DATA00 0x401F814CU, 0x0U, 0, 0, 0x401F833CU +#define IOMUXC_GPIO_B0_04_QTIMER2_TIMER1 0x401F814CU, 0x1U, 0x401F8570U, 0x1U, 0x401F833CU +#define IOMUXC_GPIO_B0_04_LPI2C2_SCL 0x401F814CU, 0x2U, 0x401F84D4U, 0x1U, 0x401F833CU +#define IOMUXC_GPIO_B0_04_ARM_CM7_TRACE00 0x401F814CU, 0x3U, 0, 0, 0x401F833CU +#define IOMUXC_GPIO_B0_04_FLEXIO2_FLEXIO04 0x401F814CU, 0x4U, 0, 0, 0x401F833CU +#define IOMUXC_GPIO_B0_04_GPIO2_IO04 0x401F814CU, 0x5U, 0, 0, 0x401F833CU +#define IOMUXC_GPIO_B0_04_SRC_BOOT_CFG00 0x401F814CU, 0x6U, 0, 0, 0x401F833CU + +#define IOMUXC_GPIO_B0_05_LCD_DATA01 0x401F8150U, 0x0U, 0, 0, 0x401F8340U +#define IOMUXC_GPIO_B0_05_QTIMER2_TIMER2 0x401F8150U, 0x1U, 0x401F8574U, 0x1U, 0x401F8340U +#define IOMUXC_GPIO_B0_05_LPI2C2_SDA 0x401F8150U, 0x2U, 0x401F84D8U, 0x1U, 0x401F8340U +#define IOMUXC_GPIO_B0_05_ARM_CM7_TRACE01 0x401F8150U, 0x3U, 0, 0, 0x401F8340U +#define IOMUXC_GPIO_B0_05_FLEXIO2_FLEXIO05 0x401F8150U, 0x4U, 0, 0, 0x401F8340U +#define IOMUXC_GPIO_B0_05_GPIO2_IO05 0x401F8150U, 0x5U, 0, 0, 0x401F8340U +#define IOMUXC_GPIO_B0_05_SRC_BOOT_CFG01 0x401F8150U, 0x6U, 0, 0, 0x401F8340U + +#define IOMUXC_GPIO_B0_06_LCD_DATA02 0x401F8154U, 0x0U, 0, 0, 0x401F8344U +#define IOMUXC_GPIO_B0_06_QTIMER3_TIMER0 0x401F8154U, 0x1U, 0x401F857CU, 0x2U, 0x401F8344U +#define IOMUXC_GPIO_B0_06_FLEXPWM2_PWMA00 0x401F8154U, 0x2U, 0x401F8478U, 0x1U, 0x401F8344U +#define IOMUXC_GPIO_B0_06_ARM_CM7_TRACE02 0x401F8154U, 0x3U, 0, 0, 0x401F8344U +#define IOMUXC_GPIO_B0_06_FLEXIO2_FLEXIO06 0x401F8154U, 0x4U, 0, 0, 0x401F8344U +#define IOMUXC_GPIO_B0_06_GPIO2_IO06 0x401F8154U, 0x5U, 0, 0, 0x401F8344U +#define IOMUXC_GPIO_B0_06_SRC_BOOT_CFG02 0x401F8154U, 0x6U, 0, 0, 0x401F8344U + +#define IOMUXC_GPIO_B0_07_LCD_DATA03 0x401F8158U, 0x0U, 0, 0, 0x401F8348U +#define IOMUXC_GPIO_B0_07_QTIMER3_TIMER1 0x401F8158U, 0x1U, 0x401F8580U, 0x2U, 0x401F8348U +#define IOMUXC_GPIO_B0_07_FLEXPWM2_PWMB00 0x401F8158U, 0x2U, 0x401F8488U, 0x1U, 0x401F8348U +#define IOMUXC_GPIO_B0_07_ARM_CM7_TRACE03 0x401F8158U, 0x3U, 0, 0, 0x401F8348U +#define IOMUXC_GPIO_B0_07_FLEXIO2_FLEXIO07 0x401F8158U, 0x4U, 0, 0, 0x401F8348U +#define IOMUXC_GPIO_B0_07_GPIO2_IO07 0x401F8158U, 0x5U, 0, 0, 0x401F8348U +#define IOMUXC_GPIO_B0_07_SRC_BOOT_CFG03 0x401F8158U, 0x6U, 0, 0, 0x401F8348U + +#define IOMUXC_GPIO_B0_08_LCD_DATA04 0x401F815CU, 0x0U, 0, 0, 0x401F834CU +#define IOMUXC_GPIO_B0_08_QTIMER3_TIMER2 0x401F815CU, 0x1U, 0x401F8584U, 0x2U, 0x401F834CU +#define IOMUXC_GPIO_B0_08_FLEXPWM2_PWMA01 0x401F815CU, 0x2U, 0x401F847CU, 0x1U, 0x401F834CU +#define IOMUXC_GPIO_B0_08_LPUART3_TX 0x401F815CU, 0x3U, 0x401F853CU, 0x2U, 0x401F834CU +#define IOMUXC_GPIO_B0_08_FLEXIO2_FLEXIO08 0x401F815CU, 0x4U, 0, 0, 0x401F834CU +#define IOMUXC_GPIO_B0_08_GPIO2_IO08 0x401F815CU, 0x5U, 0, 0, 0x401F834CU +#define IOMUXC_GPIO_B0_08_SRC_BOOT_CFG04 0x401F815CU, 0x6U, 0, 0, 0x401F834CU + +#define IOMUXC_GPIO_B0_09_LCD_DATA05 0x401F8160U, 0x0U, 0, 0, 0x401F8350U +#define IOMUXC_GPIO_B0_09_QTIMER4_TIMER0 0x401F8160U, 0x1U, 0, 0, 0x401F8350U +#define IOMUXC_GPIO_B0_09_FLEXPWM2_PWMB01 0x401F8160U, 0x2U, 0x401F848CU, 0x1U, 0x401F8350U +#define IOMUXC_GPIO_B0_09_LPUART3_RX 0x401F8160U, 0x3U, 0x401F8538U, 0x2U, 0x401F8350U +#define IOMUXC_GPIO_B0_09_FLEXIO2_FLEXIO09 0x401F8160U, 0x4U, 0, 0, 0x401F8350U +#define IOMUXC_GPIO_B0_09_GPIO2_IO09 0x401F8160U, 0x5U, 0, 0, 0x401F8350U +#define IOMUXC_GPIO_B0_09_SRC_BOOT_CFG05 0x401F8160U, 0x6U, 0, 0, 0x401F8350U + +#define IOMUXC_GPIO_B0_10_LCD_DATA06 0x401F8164U, 0x0U, 0, 0, 0x401F8354U +#define IOMUXC_GPIO_B0_10_QTIMER4_TIMER1 0x401F8164U, 0x1U, 0, 0, 0x401F8354U +#define IOMUXC_GPIO_B0_10_FLEXPWM2_PWMA02 0x401F8164U, 0x2U, 0x401F8480U, 0x1U, 0x401F8354U +#define IOMUXC_GPIO_B0_10_SAI1_TX_DATA03 0x401F8164U, 0x3U, 0x401F8598U, 0x1U, 0x401F8354U +#define IOMUXC_GPIO_B0_10_FLEXIO2_FLEXIO10 0x401F8164U, 0x4U, 0, 0, 0x401F8354U +#define IOMUXC_GPIO_B0_10_GPIO2_IO10 0x401F8164U, 0x5U, 0, 0, 0x401F8354U +#define IOMUXC_GPIO_B0_10_SRC_BOOT_CFG06 0x401F8164U, 0x6U, 0, 0, 0x401F8354U + +#define IOMUXC_GPIO_B0_11_LCD_DATA07 0x401F8168U, 0x0U, 0, 0, 0x401F8358U +#define IOMUXC_GPIO_B0_11_QTIMER4_TIMER2 0x401F8168U, 0x1U, 0, 0, 0x401F8358U +#define IOMUXC_GPIO_B0_11_FLEXPWM2_PWMB02 0x401F8168U, 0x2U, 0x401F8490U, 0x1U, 0x401F8358U +#define IOMUXC_GPIO_B0_11_SAI1_TX_DATA02 0x401F8168U, 0x3U, 0x401F859CU, 0x1U, 0x401F8358U +#define IOMUXC_GPIO_B0_11_FLEXIO2_FLEXIO11 0x401F8168U, 0x4U, 0, 0, 0x401F8358U +#define IOMUXC_GPIO_B0_11_GPIO2_IO11 0x401F8168U, 0x5U, 0, 0, 0x401F8358U +#define IOMUXC_GPIO_B0_11_SRC_BOOT_CFG07 0x401F8168U, 0x6U, 0, 0, 0x401F8358U + +#define IOMUXC_GPIO_B0_12_LCD_DATA08 0x401F816CU, 0x0U, 0, 0, 0x401F835CU +#define IOMUXC_GPIO_B0_12_XBAR1_INOUT10 0x401F816CU, 0x1U, 0, 0, 0x401F835CU +#define IOMUXC_GPIO_B0_12_ARM_CM7_TRACE_CLK 0x401F816CU, 0x2U, 0, 0, 0x401F835CU +#define IOMUXC_GPIO_B0_12_SAI1_TX_DATA01 0x401F816CU, 0x3U, 0x401F85A0U, 0x1U, 0x401F835CU +#define IOMUXC_GPIO_B0_12_FLEXIO2_FLEXIO12 0x401F816CU, 0x4U, 0, 0, 0x401F835CU +#define IOMUXC_GPIO_B0_12_GPIO2_IO12 0x401F816CU, 0x5U, 0, 0, 0x401F835CU +#define IOMUXC_GPIO_B0_12_SRC_BOOT_CFG08 0x401F816CU, 0x6U, 0, 0, 0x401F835CU + +#define IOMUXC_GPIO_B0_13_LCD_DATA09 0x401F8170U, 0x0U, 0, 0, 0x401F8360U +#define IOMUXC_GPIO_B0_13_XBAR1_INOUT11 0x401F8170U, 0x1U, 0, 0, 0x401F8360U +#define IOMUXC_GPIO_B0_13_ARM_CM7_TRACE_SWO 0x401F8170U, 0x2U, 0, 0, 0x401F8360U +#define IOMUXC_GPIO_B0_13_SAI1_MCLK 0x401F8170U, 0x3U, 0x401F858CU, 0x2U, 0x401F8360U +#define IOMUXC_GPIO_B0_13_FLEXIO2_FLEXIO13 0x401F8170U, 0x4U, 0, 0, 0x401F8360U +#define IOMUXC_GPIO_B0_13_GPIO2_IO13 0x401F8170U, 0x5U, 0, 0, 0x401F8360U +#define IOMUXC_GPIO_B0_13_SRC_BOOT_CFG09 0x401F8170U, 0x6U, 0, 0, 0x401F8360U + +#define IOMUXC_GPIO_B0_14_LCD_DATA10 0x401F8174U, 0x0U, 0, 0, 0x401F8364U +#define IOMUXC_GPIO_B0_14_XBAR1_INOUT12 0x401F8174U, 0x1U, 0, 0, 0x401F8364U +#define IOMUXC_GPIO_B0_14_ARM_CM7_TXEV 0x401F8174U, 0x2U, 0, 0, 0x401F8364U +#define IOMUXC_GPIO_B0_14_SAI1_RX_SYNC 0x401F8174U, 0x3U, 0x401F85A4U, 0x2U, 0x401F8364U +#define IOMUXC_GPIO_B0_14_FLEXIO2_FLEXIO14 0x401F8174U, 0x4U, 0, 0, 0x401F8364U +#define IOMUXC_GPIO_B0_14_GPIO2_IO14 0x401F8174U, 0x5U, 0, 0, 0x401F8364U +#define IOMUXC_GPIO_B0_14_SRC_BOOT_CFG10 0x401F8174U, 0x6U, 0, 0, 0x401F8364U + +#define IOMUXC_GPIO_B0_15_LCD_DATA11 0x401F8178U, 0x0U, 0, 0, 0x401F8368U +#define IOMUXC_GPIO_B0_15_XBAR1_INOUT13 0x401F8178U, 0x1U, 0, 0, 0x401F8368U +#define IOMUXC_GPIO_B0_15_ARM_CM7_RXEV 0x401F8178U, 0x2U, 0, 0, 0x401F8368U +#define IOMUXC_GPIO_B0_15_SAI1_RX_BCLK 0x401F8178U, 0x3U, 0x401F8590U, 0x2U, 0x401F8368U +#define IOMUXC_GPIO_B0_15_FLEXIO2_FLEXIO15 0x401F8178U, 0x4U, 0, 0, 0x401F8368U +#define IOMUXC_GPIO_B0_15_GPIO2_IO15 0x401F8178U, 0x5U, 0, 0, 0x401F8368U +#define IOMUXC_GPIO_B0_15_SRC_BOOT_CFG11 0x401F8178U, 0x6U, 0, 0, 0x401F8368U + +#define IOMUXC_GPIO_B1_00_LCD_DATA12 0x401F817CU, 0x0U, 0, 0, 0x401F836CU +#define IOMUXC_GPIO_B1_00_XBAR1_INOUT14 0x401F817CU, 0x1U, 0x401F8644U, 0x1U, 0x401F836CU +#define IOMUXC_GPIO_B1_00_LPUART4_TX 0x401F817CU, 0x2U, 0x401F8544U, 0x2U, 0x401F836CU +#define IOMUXC_GPIO_B1_00_SAI1_RX_DATA00 0x401F817CU, 0x3U, 0x401F8594U, 0x2U, 0x401F836CU +#define IOMUXC_GPIO_B1_00_FLEXIO2_FLEXIO16 0x401F817CU, 0x4U, 0, 0, 0x401F836CU +#define IOMUXC_GPIO_B1_00_GPIO2_IO16 0x401F817CU, 0x5U, 0, 0, 0x401F836CU +#define IOMUXC_GPIO_B1_00_FLEXPWM1_PWMA03 0x401F817CU, 0x6U, 0x401F8454U, 0x4U, 0x401F836CU + +#define IOMUXC_GPIO_B1_01_LCD_DATA13 0x401F8180U, 0x0U, 0, 0, 0x401F8370U +#define IOMUXC_GPIO_B1_01_XBAR1_INOUT15 0x401F8180U, 0x1U, 0x401F8648U, 0x1U, 0x401F8370U +#define IOMUXC_GPIO_B1_01_LPUART4_RX 0x401F8180U, 0x2U, 0x401F8540U, 0x2U, 0x401F8370U +#define IOMUXC_GPIO_B1_01_SAI1_TX_DATA00 0x401F8180U, 0x3U, 0, 0, 0x401F8370U +#define IOMUXC_GPIO_B1_01_FLEXIO2_FLEXIO17 0x401F8180U, 0x4U, 0, 0, 0x401F8370U +#define IOMUXC_GPIO_B1_01_GPIO2_IO17 0x401F8180U, 0x5U, 0, 0, 0x401F8370U +#define IOMUXC_GPIO_B1_01_FLEXPWM1_PWMB03 0x401F8180U, 0x6U, 0x401F8464U, 0x4U, 0x401F8370U + +#define IOMUXC_GPIO_B1_02_LCD_DATA14 0x401F8184U, 0x0U, 0, 0, 0x401F8374U +#define IOMUXC_GPIO_B1_02_XBAR1_INOUT16 0x401F8184U, 0x1U, 0x401F864CU, 0x1U, 0x401F8374U +#define IOMUXC_GPIO_B1_02_LPSPI4_PCS2 0x401F8184U, 0x2U, 0, 0, 0x401F8374U +#define IOMUXC_GPIO_B1_02_SAI1_TX_BCLK 0x401F8184U, 0x3U, 0x401F85A8U, 0x2U, 0x401F8374U +#define IOMUXC_GPIO_B1_02_FLEXIO2_FLEXIO18 0x401F8184U, 0x4U, 0, 0, 0x401F8374U +#define IOMUXC_GPIO_B1_02_GPIO2_IO18 0x401F8184U, 0x5U, 0, 0, 0x401F8374U +#define IOMUXC_GPIO_B1_02_FLEXPWM2_PWMA03 0x401F8184U, 0x6U, 0x401F8474U, 0x4U, 0x401F8374U + +#define IOMUXC_GPIO_B1_03_LCD_DATA15 0x401F8188U, 0x0U, 0, 0, 0x401F8378U +#define IOMUXC_GPIO_B1_03_XBAR1_INOUT17 0x401F8188U, 0x1U, 0x401F862CU, 0x3U, 0x401F8378U +#define IOMUXC_GPIO_B1_03_LPSPI4_PCS1 0x401F8188U, 0x2U, 0, 0, 0x401F8378U +#define IOMUXC_GPIO_B1_03_SAI1_TX_SYNC 0x401F8188U, 0x3U, 0x401F85ACU, 0x2U, 0x401F8378U +#define IOMUXC_GPIO_B1_03_FLEXIO2_FLEXIO19 0x401F8188U, 0x4U, 0, 0, 0x401F8378U +#define IOMUXC_GPIO_B1_03_GPIO2_IO19 0x401F8188U, 0x5U, 0, 0, 0x401F8378U +#define IOMUXC_GPIO_B1_03_FLEXPWM2_PWMB03 0x401F8188U, 0x6U, 0x401F8484U, 0x3U, 0x401F8378U + +#define IOMUXC_GPIO_B1_04_LCD_DATA16 0x401F818CU, 0x0U, 0, 0, 0x401F837CU +#define IOMUXC_GPIO_B1_04_LPSPI4_PCS0 0x401F818CU, 0x1U, 0x401F851CU, 0x1U, 0x401F837CU +#define IOMUXC_GPIO_B1_04_CSI_DATA15 0x401F818CU, 0x2U, 0, 0, 0x401F837CU +#define IOMUXC_GPIO_B1_04_ENET_RX_DATA00 0x401F818CU, 0x3U, 0x401F8434U, 0x1U, 0x401F837CU +#define IOMUXC_GPIO_B1_04_FLEXIO2_FLEXIO20 0x401F818CU, 0x4U, 0, 0, 0x401F837CU +#define IOMUXC_GPIO_B1_04_GPIO2_IO20 0x401F818CU, 0x5U, 0, 0, 0x401F837CU + +#define IOMUXC_GPIO_B1_05_LCD_DATA17 0x401F8190U, 0x0U, 0, 0, 0x401F8380U +#define IOMUXC_GPIO_B1_05_LPSPI4_SDI 0x401F8190U, 0x1U, 0x401F8524U, 0x1U, 0x401F8380U +#define IOMUXC_GPIO_B1_05_CSI_DATA14 0x401F8190U, 0x2U, 0, 0, 0x401F8380U +#define IOMUXC_GPIO_B1_05_ENET_RX_DATA01 0x401F8190U, 0x3U, 0x401F8438U, 0x1U, 0x401F8380U +#define IOMUXC_GPIO_B1_05_FLEXIO2_FLEXIO21 0x401F8190U, 0x4U, 0, 0, 0x401F8380U +#define IOMUXC_GPIO_B1_05_GPIO2_IO21 0x401F8190U, 0x5U, 0, 0, 0x401F8380U + +#define IOMUXC_GPIO_B1_06_LCD_DATA18 0x401F8194U, 0x0U, 0, 0, 0x401F8384U +#define IOMUXC_GPIO_B1_06_LPSPI4_SDO 0x401F8194U, 0x1U, 0x401F8528U, 0x1U, 0x401F8384U +#define IOMUXC_GPIO_B1_06_CSI_DATA13 0x401F8194U, 0x2U, 0, 0, 0x401F8384U +#define IOMUXC_GPIO_B1_06_ENET_RX_EN 0x401F8194U, 0x3U, 0x401F843CU, 0x1U, 0x401F8384U +#define IOMUXC_GPIO_B1_06_FLEXIO2_FLEXIO22 0x401F8194U, 0x4U, 0, 0, 0x401F8384U +#define IOMUXC_GPIO_B1_06_GPIO2_IO22 0x401F8194U, 0x5U, 0, 0, 0x401F8384U + +#define IOMUXC_GPIO_B1_07_LCD_DATA19 0x401F8198U, 0x0U, 0, 0, 0x401F8388U +#define IOMUXC_GPIO_B1_07_LPSPI4_SCK 0x401F8198U, 0x1U, 0x401F8520U, 0x1U, 0x401F8388U +#define IOMUXC_GPIO_B1_07_CSI_DATA12 0x401F8198U, 0x2U, 0, 0, 0x401F8388U +#define IOMUXC_GPIO_B1_07_ENET_TX_DATA00 0x401F8198U, 0x3U, 0, 0, 0x401F8388U +#define IOMUXC_GPIO_B1_07_FLEXIO2_FLEXIO23 0x401F8198U, 0x4U, 0, 0, 0x401F8388U +#define IOMUXC_GPIO_B1_07_GPIO2_IO23 0x401F8198U, 0x5U, 0, 0, 0x401F8388U + +#define IOMUXC_GPIO_B1_08_LCD_DATA20 0x401F819CU, 0x0U, 0, 0, 0x401F838CU +#define IOMUXC_GPIO_B1_08_QTIMER1_TIMER3 0x401F819CU, 0x1U, 0, 0, 0x401F838CU +#define IOMUXC_GPIO_B1_08_CSI_DATA11 0x401F819CU, 0x2U, 0, 0, 0x401F838CU +#define IOMUXC_GPIO_B1_08_ENET_TX_DATA01 0x401F819CU, 0x3U, 0, 0, 0x401F838CU +#define IOMUXC_GPIO_B1_08_FLEXIO2_FLEXIO24 0x401F819CU, 0x4U, 0, 0, 0x401F838CU +#define IOMUXC_GPIO_B1_08_GPIO2_IO24 0x401F819CU, 0x5U, 0, 0, 0x401F838CU +#define IOMUXC_GPIO_B1_08_FLEXCAN2_TX 0x401F819CU, 0x6U, 0, 0, 0x401F838CU + +#define IOMUXC_GPIO_B1_09_LCD_DATA21 0x401F81A0U, 0x0U, 0, 0, 0x401F8390U +#define IOMUXC_GPIO_B1_09_QTIMER2_TIMER3 0x401F81A0U, 0x1U, 0x401F8578U, 0x1U, 0x401F8390U +#define IOMUXC_GPIO_B1_09_CSI_DATA10 0x401F81A0U, 0x2U, 0, 0, 0x401F8390U +#define IOMUXC_GPIO_B1_09_ENET_TX_EN 0x401F81A0U, 0x3U, 0, 0, 0x401F8390U +#define IOMUXC_GPIO_B1_09_FLEXIO2_FLEXIO25 0x401F81A0U, 0x4U, 0, 0, 0x401F8390U +#define IOMUXC_GPIO_B1_09_GPIO2_IO25 0x401F81A0U, 0x5U, 0, 0, 0x401F8390U +#define IOMUXC_GPIO_B1_09_FLEXCAN2_RX 0x401F81A0U, 0x6U, 0x401F8450U, 0x3U, 0x401F8390U + +#define IOMUXC_GPIO_B1_10_LCD_DATA22 0x401F81A4U, 0x0U, 0, 0, 0x401F8394U +#define IOMUXC_GPIO_B1_10_QTIMER3_TIMER3 0x401F81A4U, 0x1U, 0x401F8588U, 0x2U, 0x401F8394U +#define IOMUXC_GPIO_B1_10_CSI_DATA00 0x401F81A4U, 0x2U, 0, 0, 0x401F8394U +#define IOMUXC_GPIO_B1_10_ENET_TX_CLK 0x401F81A4U, 0x3U, 0x401F8448U, 0x1U, 0x401F8394U +#define IOMUXC_GPIO_B1_10_FLEXIO2_FLEXIO26 0x401F81A4U, 0x4U, 0, 0, 0x401F8394U +#define IOMUXC_GPIO_B1_10_GPIO2_IO26 0x401F81A4U, 0x5U, 0, 0, 0x401F8394U +#define IOMUXC_GPIO_B1_10_ENET_REF_CLK 0x401F81A4U, 0x6U, 0x401F842CU, 0x1U, 0x401F8394U + +#define IOMUXC_GPIO_B1_11_LCD_DATA23 0x401F81A8U, 0x0U, 0, 0, 0x401F8398U +#define IOMUXC_GPIO_B1_11_QTIMER4_TIMER3 0x401F81A8U, 0x1U, 0, 0, 0x401F8398U +#define IOMUXC_GPIO_B1_11_CSI_DATA01 0x401F81A8U, 0x2U, 0, 0, 0x401F8398U +#define IOMUXC_GPIO_B1_11_ENET_RX_ER 0x401F81A8U, 0x3U, 0x401F8440U, 0x1U, 0x401F8398U +#define IOMUXC_GPIO_B1_11_FLEXIO2_FLEXIO27 0x401F81A8U, 0x4U, 0, 0, 0x401F8398U +#define IOMUXC_GPIO_B1_11_GPIO2_IO27 0x401F81A8U, 0x5U, 0, 0, 0x401F8398U +#define IOMUXC_GPIO_B1_11_LPSPI4_PCS3 0x401F81A8U, 0x6U, 0, 0, 0x401F8398U + +#define IOMUXC_GPIO_B1_12_LPUART5_TX 0x401F81ACU, 0x1U, 0x401F854CU, 0x1U, 0x401F839CU +#define IOMUXC_GPIO_B1_12_CSI_PIXCLK 0x401F81ACU, 0x2U, 0x401F8424U, 0x1U, 0x401F839CU +#define IOMUXC_GPIO_B1_12_ENET_1588_EVENT0_IN 0x401F81ACU, 0x3U, 0x401F8444U, 0x2U, 0x401F839CU +#define IOMUXC_GPIO_B1_12_FLEXIO2_FLEXIO28 0x401F81ACU, 0x4U, 0, 0, 0x401F839CU +#define IOMUXC_GPIO_B1_12_GPIO2_IO28 0x401F81ACU, 0x5U, 0, 0, 0x401F839CU +#define IOMUXC_GPIO_B1_12_USDHC1_CD_B 0x401F81ACU, 0x6U, 0x401F85D4U, 0x2U, 0x401F839CU + +#define IOMUXC_GPIO_B1_13_WDOG1_B 0x401F81B0U, 0x0U, 0, 0, 0x401F83A0U +#define IOMUXC_GPIO_B1_13_LPUART5_RX 0x401F81B0U, 0x1U, 0x401F8548U, 0x1U, 0x401F83A0U +#define IOMUXC_GPIO_B1_13_CSI_VSYNC 0x401F81B0U, 0x2U, 0x401F8428U, 0x2U, 0x401F83A0U +#define IOMUXC_GPIO_B1_13_ENET_1588_EVENT0_OUT 0x401F81B0U, 0x3U, 0, 0, 0x401F83A0U +#define IOMUXC_GPIO_B1_13_FLEXIO2_FLEXIO29 0x401F81B0U, 0x4U, 0, 0, 0x401F83A0U +#define IOMUXC_GPIO_B1_13_GPIO2_IO29 0x401F81B0U, 0x5U, 0, 0, 0x401F83A0U +#define IOMUXC_GPIO_B1_13_USDHC1_WP 0x401F81B0U, 0x6U, 0x401F85D8U, 0x3U, 0x401F83A0U + +#define IOMUXC_GPIO_B1_14_ENET_MDC 0x401F81B4U, 0x0U, 0, 0, 0x401F83A4U +#define IOMUXC_GPIO_B1_14_FLEXPWM4_PWMA02 0x401F81B4U, 0x1U, 0x401F849CU, 0x1U, 0x401F83A4U +#define IOMUXC_GPIO_B1_14_CSI_HSYNC 0x401F81B4U, 0x2U, 0x401F8420U, 0x2U, 0x401F83A4U +#define IOMUXC_GPIO_B1_14_XBAR1_IN02 0x401F81B4U, 0x3U, 0x401F860CU, 0x1U, 0x401F83A4U +#define IOMUXC_GPIO_B1_14_FLEXIO2_FLEXIO30 0x401F81B4U, 0x4U, 0, 0, 0x401F83A4U +#define IOMUXC_GPIO_B1_14_GPIO2_IO30 0x401F81B4U, 0x5U, 0, 0, 0x401F83A4U +#define IOMUXC_GPIO_B1_14_USDHC1_VSELECT 0x401F81B4U, 0x6U, 0, 0, 0x401F83A4U + +#define IOMUXC_GPIO_B1_15_ENET_MDIO 0x401F81B8U, 0x0U, 0x401F8430U, 0x2U, 0x401F83A8U +#define IOMUXC_GPIO_B1_15_FLEXPWM4_PWMA03 0x401F81B8U, 0x1U, 0x401F84A0U, 0x1U, 0x401F83A8U +#define IOMUXC_GPIO_B1_15_CSI_MCLK 0x401F81B8U, 0x2U, 0, 0, 0x401F83A8U +#define IOMUXC_GPIO_B1_15_XBAR1_IN03 0x401F81B8U, 0x3U, 0x401F8610U, 0x1U, 0x401F83A8U +#define IOMUXC_GPIO_B1_15_FLEXIO2_FLEXIO31 0x401F81B8U, 0x4U, 0, 0, 0x401F83A8U +#define IOMUXC_GPIO_B1_15_GPIO2_IO31 0x401F81B8U, 0x5U, 0, 0, 0x401F83A8U +#define IOMUXC_GPIO_B1_15_USDHC1_RESET_B 0x401F81B8U, 0x6U, 0, 0, 0x401F83A8U + +#define IOMUXC_GPIO_SD_B0_00_USDHC1_CMD 0x401F81BCU, 0x0U, 0, 0, 0x401F83ACU +#define IOMUXC_GPIO_SD_B0_00_FLEXPWM1_PWMA00 0x401F81BCU, 0x1U, 0x401F8458U, 0x1U, 0x401F83ACU +#define IOMUXC_GPIO_SD_B0_00_LPI2C3_SCL 0x401F81BCU, 0x2U, 0x401F84DCU, 0x1U, 0x401F83ACU +#define IOMUXC_GPIO_SD_B0_00_XBAR1_INOUT04 0x401F81BCU, 0x3U, 0x401F8614U, 0x1U, 0x401F83ACU +#define IOMUXC_GPIO_SD_B0_00_LPSPI1_SCK 0x401F81BCU, 0x4U, 0x401F84F0U, 0x1U, 0x401F83ACU +#define IOMUXC_GPIO_SD_B0_00_GPIO3_IO12 0x401F81BCU, 0x5U, 0, 0, 0x401F83ACU +#define IOMUXC_GPIO_SD_B0_00_FLEXSPIA_SS1_B 0x401F81BCU, 0x6U, 0, 0, 0x401F83ACU + +#define IOMUXC_GPIO_SD_B0_01_USDHC1_CLK 0x401F81C0U, 0x0U, 0, 0, 0x401F83B0U +#define IOMUXC_GPIO_SD_B0_01_FLEXPWM1_PWMB00 0x401F81C0U, 0x1U, 0x401F8468U, 0x1U, 0x401F83B0U +#define IOMUXC_GPIO_SD_B0_01_LPI2C3_SDA 0x401F81C0U, 0x2U, 0x401F84E0U, 0x1U, 0x401F83B0U +#define IOMUXC_GPIO_SD_B0_01_XBAR1_INOUT05 0x401F81C0U, 0x3U, 0x401F8618U, 0x1U, 0x401F83B0U +#define IOMUXC_GPIO_SD_B0_01_LPSPI1_PCS0 0x401F81C0U, 0x4U, 0x401F84ECU, 0x0U, 0x401F83B0U +#define IOMUXC_GPIO_SD_B0_01_GPIO3_IO13 0x401F81C0U, 0x5U, 0, 0, 0x401F83B0U +#define IOMUXC_GPIO_SD_B0_01_FLEXSPIB_SS1_B 0x401F81C0U, 0x6U, 0, 0, 0x401F83B0U + +#define IOMUXC_GPIO_SD_B0_02_USDHC1_DATA0 0x401F81C4U, 0x0U, 0, 0, 0x401F83B4U +#define IOMUXC_GPIO_SD_B0_02_FLEXPWM1_PWMA01 0x401F81C4U, 0x1U, 0x401F845CU, 0x1U, 0x401F83B4U +#define IOMUXC_GPIO_SD_B0_02_LPUART8_CTS_B 0x401F81C4U, 0x2U, 0, 0, 0x401F83B4U +#define IOMUXC_GPIO_SD_B0_02_XBAR1_INOUT06 0x401F81C4U, 0x3U, 0x401F861CU, 0x1U, 0x401F83B4U +#define IOMUXC_GPIO_SD_B0_02_LPSPI1_SDO 0x401F81C4U, 0x4U, 0x401F84F8U, 0x1U, 0x401F83B4U +#define IOMUXC_GPIO_SD_B0_02_GPIO3_IO14 0x401F81C4U, 0x5U, 0, 0, 0x401F83B4U + +#define IOMUXC_GPIO_SD_B0_03_USDHC1_DATA1 0x401F81C8U, 0x0U, 0, 0, 0x401F83B8U +#define IOMUXC_GPIO_SD_B0_03_FLEXPWM1_PWMB01 0x401F81C8U, 0x1U, 0x401F846CU, 0x1U, 0x401F83B8U +#define IOMUXC_GPIO_SD_B0_03_LPUART8_RTS_B 0x401F81C8U, 0x2U, 0, 0, 0x401F83B8U +#define IOMUXC_GPIO_SD_B0_03_XBAR1_INOUT07 0x401F81C8U, 0x3U, 0x401F8620U, 0x1U, 0x401F83B8U +#define IOMUXC_GPIO_SD_B0_03_LPSPI1_SDI 0x401F81C8U, 0x4U, 0x401F84F4U, 0x1U, 0x401F83B8U +#define IOMUXC_GPIO_SD_B0_03_GPIO3_IO15 0x401F81C8U, 0x5U, 0, 0, 0x401F83B8U + +#define IOMUXC_GPIO_SD_B0_04_USDHC1_DATA2 0x401F81CCU, 0x0U, 0, 0, 0x401F83BCU +#define IOMUXC_GPIO_SD_B0_04_FLEXPWM1_PWMA02 0x401F81CCU, 0x1U, 0x401F8460U, 0x1U, 0x401F83BCU +#define IOMUXC_GPIO_SD_B0_04_LPUART8_TX 0x401F81CCU, 0x2U, 0x401F8564U, 0x0U, 0x401F83BCU +#define IOMUXC_GPIO_SD_B0_04_XBAR1_INOUT08 0x401F81CCU, 0x3U, 0x401F8624U, 0x1U, 0x401F83BCU +#define IOMUXC_GPIO_SD_B0_04_FLEXSPIB_SS0_B 0x401F81CCU, 0x4U, 0, 0, 0x401F83BCU +#define IOMUXC_GPIO_SD_B0_04_GPIO3_IO16 0x401F81CCU, 0x5U, 0, 0, 0x401F83BCU +#define IOMUXC_GPIO_SD_B0_04_CCM_CLKO1 0x401F81CCU, 0x6U, 0, 0, 0x401F83BCU + +#define IOMUXC_GPIO_SD_B0_05_USDHC1_DATA3 0x401F81D0U, 0x0U, 0, 0, 0x401F83C0U +#define IOMUXC_GPIO_SD_B0_05_FLEXPWM1_PWMB02 0x401F81D0U, 0x1U, 0x401F8470U, 0x1U, 0x401F83C0U +#define IOMUXC_GPIO_SD_B0_05_LPUART8_RX 0x401F81D0U, 0x2U, 0x401F8560U, 0x0U, 0x401F83C0U +#define IOMUXC_GPIO_SD_B0_05_XBAR1_INOUT09 0x401F81D0U, 0x3U, 0x401F8628U, 0x1U, 0x401F83C0U +#define IOMUXC_GPIO_SD_B0_05_FLEXSPIB_DQS 0x401F81D0U, 0x4U, 0, 0, 0x401F83C0U +#define IOMUXC_GPIO_SD_B0_05_GPIO3_IO17 0x401F81D0U, 0x5U, 0, 0, 0x401F83C0U +#define IOMUXC_GPIO_SD_B0_05_CCM_CLKO2 0x401F81D0U, 0x6U, 0, 0, 0x401F83C0U + +#define IOMUXC_GPIO_SD_B1_00_USDHC2_DATA3 0x401F81D4U, 0x0U, 0x401F85F4U, 0x0U, 0x401F83C4U +#define IOMUXC_GPIO_SD_B1_00_FLEXSPIB_DATA03 0x401F81D4U, 0x1U, 0x401F84C4U, 0x0U, 0x401F83C4U +#define IOMUXC_GPIO_SD_B1_00_FLEXPWM1_PWMA03 0x401F81D4U, 0x2U, 0x401F8454U, 0x0U, 0x401F83C4U +#define IOMUXC_GPIO_SD_B1_00_SAI1_TX_DATA03 0x401F81D4U, 0x3U, 0x401F8598U, 0x0U, 0x401F83C4U +#define IOMUXC_GPIO_SD_B1_00_LPUART4_TX 0x401F81D4U, 0x4U, 0x401F8544U, 0x0U, 0x401F83C4U +#define IOMUXC_GPIO_SD_B1_00_GPIO3_IO00 0x401F81D4U, 0x5U, 0, 0, 0x401F83C4U + +#define IOMUXC_GPIO_SD_B1_01_USDHC2_DATA2 0x401F81D8U, 0x0U, 0x401F85F0U, 0x0U, 0x401F83C8U +#define IOMUXC_GPIO_SD_B1_01_FLEXSPIB_DATA02 0x401F81D8U, 0x1U, 0x401F84C0U, 0x0U, 0x401F83C8U +#define IOMUXC_GPIO_SD_B1_01_FLEXPWM1_PWMB03 0x401F81D8U, 0x2U, 0x401F8464U, 0x0U, 0x401F83C8U +#define IOMUXC_GPIO_SD_B1_01_SAI1_TX_DATA02 0x401F81D8U, 0x3U, 0x401F859CU, 0x0U, 0x401F83C8U +#define IOMUXC_GPIO_SD_B1_01_LPUART4_RX 0x401F81D8U, 0x4U, 0x401F8540U, 0x0U, 0x401F83C8U +#define IOMUXC_GPIO_SD_B1_01_GPIO3_IO01 0x401F81D8U, 0x5U, 0, 0, 0x401F83C8U + +#define IOMUXC_GPIO_SD_B1_02_USDHC2_DATA1 0x401F81DCU, 0x0U, 0x401F85ECU, 0x0U, 0x401F83CCU +#define IOMUXC_GPIO_SD_B1_02_FLEXSPIB_DATA01 0x401F81DCU, 0x1U, 0x401F84BCU, 0x0U, 0x401F83CCU +#define IOMUXC_GPIO_SD_B1_02_FLEXPWM2_PWMA03 0x401F81DCU, 0x2U, 0x401F8474U, 0x0U, 0x401F83CCU +#define IOMUXC_GPIO_SD_B1_02_SAI1_TX_DATA01 0x401F81DCU, 0x3U, 0x401F85A0U, 0x0U, 0x401F83CCU +#define IOMUXC_GPIO_SD_B1_02_FLEXCAN1_TX 0x401F81DCU, 0x4U, 0, 0, 0x401F83CCU +#define IOMUXC_GPIO_SD_B1_02_GPIO3_IO02 0x401F81DCU, 0x5U, 0, 0, 0x401F83CCU +#define IOMUXC_GPIO_SD_B1_02_CCM_WAIT 0x401F81DCU, 0x6U, 0, 0, 0x401F83CCU + +#define IOMUXC_GPIO_SD_B1_03_USDHC2_DATA0 0x401F81E0U, 0x0U, 0x401F85E8U, 0x0U, 0x401F83D0U +#define IOMUXC_GPIO_SD_B1_03_FLEXSPIB_DATA00 0x401F81E0U, 0x1U, 0x401F84B8U, 0x0U, 0x401F83D0U +#define IOMUXC_GPIO_SD_B1_03_FLEXPWM2_PWMB03 0x401F81E0U, 0x2U, 0x401F8484U, 0x0U, 0x401F83D0U +#define IOMUXC_GPIO_SD_B1_03_SAI1_MCLK 0x401F81E0U, 0x3U, 0x401F858CU, 0x0U, 0x401F83D0U +#define IOMUXC_GPIO_SD_B1_03_FLEXCAN1_RX 0x401F81E0U, 0x4U, 0x401F844CU, 0x0U, 0x401F83D0U +#define IOMUXC_GPIO_SD_B1_03_GPIO3_IO03 0x401F81E0U, 0x5U, 0, 0, 0x401F83D0U +#define IOMUXC_GPIO_SD_B1_03_CCM_PMIC_READY 0x401F81E0U, 0x6U, 0x401F83FCU, 0x0U, 0x401F83D0U + +#define IOMUXC_GPIO_SD_B1_04_USDHC2_CLK 0x401F81E4U, 0x0U, 0x401F85DCU, 0x0U, 0x401F83D4U +#define IOMUXC_GPIO_SD_B1_04_FLEXSPIB_SCLK 0x401F81E4U, 0x1U, 0, 0, 0x401F83D4U +#define IOMUXC_GPIO_SD_B1_04_LPI2C1_SCL 0x401F81E4U, 0x2U, 0x401F84CCU, 0x0U, 0x401F83D4U +#define IOMUXC_GPIO_SD_B1_04_SAI1_RX_SYNC 0x401F81E4U, 0x3U, 0x401F85A4U, 0x0U, 0x401F83D4U +#define IOMUXC_GPIO_SD_B1_04_FLEXSPIA_SS1_B 0x401F81E4U, 0x4U, 0, 0, 0x401F83D4U +#define IOMUXC_GPIO_SD_B1_04_GPIO3_IO04 0x401F81E4U, 0x5U, 0, 0, 0x401F83D4U +#define IOMUXC_GPIO_SD_B1_04_CCM_STOP 0x401F81E4U, 0x6U, 0, 0, 0x401F83D4U + +#define IOMUXC_GPIO_SD_B1_05_USDHC2_CMD 0x401F81E8U, 0x0U, 0x401F85E4U, 0x0U, 0x401F83D8U +#define IOMUXC_GPIO_SD_B1_05_FLEXSPIA_DQS 0x401F81E8U, 0x1U, 0x401F84A4U, 0x0U, 0x401F83D8U +#define IOMUXC_GPIO_SD_B1_05_LPI2C1_SDA 0x401F81E8U, 0x2U, 0x401F84D0U, 0x0U, 0x401F83D8U +#define IOMUXC_GPIO_SD_B1_05_SAI1_RX_BCLK 0x401F81E8U, 0x3U, 0x401F8590U, 0x0U, 0x401F83D8U +#define IOMUXC_GPIO_SD_B1_05_FLEXSPIB_SS0_B 0x401F81E8U, 0x4U, 0, 0, 0x401F83D8U +#define IOMUXC_GPIO_SD_B1_05_GPIO3_IO05 0x401F81E8U, 0x5U, 0, 0, 0x401F83D8U + +#define IOMUXC_GPIO_SD_B1_06_USDHC2_RESET_B 0x401F81ECU, 0x0U, 0, 0, 0x401F83DCU +#define IOMUXC_GPIO_SD_B1_06_FLEXSPIA_SS0_B 0x401F81ECU, 0x1U, 0, 0, 0x401F83DCU +#define IOMUXC_GPIO_SD_B1_06_LPUART7_CTS_B 0x401F81ECU, 0x2U, 0, 0, 0x401F83DCU +#define IOMUXC_GPIO_SD_B1_06_SAI1_RX_DATA00 0x401F81ECU, 0x3U, 0x401F8594U, 0x0U, 0x401F83DCU +#define IOMUXC_GPIO_SD_B1_06_LPSPI2_PCS0 0x401F81ECU, 0x4U, 0x401F84FCU, 0x0U, 0x401F83DCU +#define IOMUXC_GPIO_SD_B1_06_GPIO3_IO06 0x401F81ECU, 0x5U, 0, 0, 0x401F83DCU + +#define IOMUXC_GPIO_SD_B1_07_SEMC_CSX01 0x401F81F0U, 0x0U, 0, 0, 0x401F83E0U +#define IOMUXC_GPIO_SD_B1_07_FLEXSPIA_SCLK 0x401F81F0U, 0x1U, 0x401F84C8U, 0x0U, 0x401F83E0U +#define IOMUXC_GPIO_SD_B1_07_LPUART7_RTS_B 0x401F81F0U, 0x2U, 0, 0, 0x401F83E0U +#define IOMUXC_GPIO_SD_B1_07_SAI1_TX_DATA00 0x401F81F0U, 0x3U, 0, 0, 0x401F83E0U +#define IOMUXC_GPIO_SD_B1_07_LPSPI2_SCK 0x401F81F0U, 0x4U, 0x401F8500U, 0x0U, 0x401F83E0U +#define IOMUXC_GPIO_SD_B1_07_GPIO3_IO07 0x401F81F0U, 0x5U, 0, 0, 0x401F83E0U + +#define IOMUXC_GPIO_SD_B1_08_USDHC2_DATA4 0x401F81F4U, 0x0U, 0x401F85F8U, 0x0U, 0x401F83E4U +#define IOMUXC_GPIO_SD_B1_08_FLEXSPIA_DATA00 0x401F81F4U, 0x1U, 0x401F84A8U, 0x0U, 0x401F83E4U +#define IOMUXC_GPIO_SD_B1_08_LPUART7_TX 0x401F81F4U, 0x2U, 0x401F855CU, 0x0U, 0x401F83E4U +#define IOMUXC_GPIO_SD_B1_08_SAI1_TX_BCLK 0x401F81F4U, 0x3U, 0x401F85A8U, 0x0U, 0x401F83E4U +#define IOMUXC_GPIO_SD_B1_08_LPSPI2_SD0 0x401F81F4U, 0x4U, 0x401F8508U, 0x0U, 0x401F83E4U +#define IOMUXC_GPIO_SD_B1_08_GPIO3_IO08 0x401F81F4U, 0x5U, 0, 0, 0x401F83E4U +#define IOMUXC_GPIO_SD_B1_08_SEMC_CSX02 0x401F81F4U, 0x6U, 0, 0, 0x401F83E4U + +#define IOMUXC_GPIO_SD_B1_09_USDHC2_DATA5 0x401F81F8U, 0x0U, 0x401F85FCU, 0x0U, 0x401F83E8U +#define IOMUXC_GPIO_SD_B1_09_FLEXSPIA_DATA01 0x401F81F8U, 0x1U, 0x401F84ACU, 0x0U, 0x401F83E8U +#define IOMUXC_GPIO_SD_B1_09_LPUART7_RX 0x401F81F8U, 0x2U, 0x401F8558U, 0x0U, 0x401F83E8U +#define IOMUXC_GPIO_SD_B1_09_SAI1_TX_SYNC 0x401F81F8U, 0x3U, 0x401F85ACU, 0x0U, 0x401F83E8U +#define IOMUXC_GPIO_SD_B1_09_LPSPI2_SDI 0x401F81F8U, 0x4U, 0x401F8504U, 0x0U, 0x401F83E8U +#define IOMUXC_GPIO_SD_B1_09_GPIO3_IO09 0x401F81F8U, 0x5U, 0, 0, 0x401F83E8U + +#define IOMUXC_GPIO_SD_B1_10_USDHC2_DATA6 0x401F81FCU, 0x0U, 0x401F8600U, 0x0U, 0x401F83ECU +#define IOMUXC_GPIO_SD_B1_10_FLEXSPIA_DATA02 0x401F81FCU, 0x1U, 0x401F84B0U, 0x0U, 0x401F83ECU +#define IOMUXC_GPIO_SD_B1_10_LPUART2_RX 0x401F81FCU, 0x2U, 0x401F852CU, 0x0U, 0x401F83ECU +#define IOMUXC_GPIO_SD_B1_10_LPI2C2_SDA 0x401F81FCU, 0x3U, 0x401F84D8U, 0x0U, 0x401F83ECU +#define IOMUXC_GPIO_SD_B1_10_LPSPI2_PCS2 0x401F81FCU, 0x4U, 0, 0, 0x401F83ECU +#define IOMUXC_GPIO_SD_B1_10_GPIO3_IO10 0x401F81FCU, 0x5U, 0, 0, 0x401F83ECU + +#define IOMUXC_GPIO_SD_B1_11_USDHC2_DATA7 0x401F8200U, 0x0U, 0x401F8604U, 0x0U, 0x401F83F0U +#define IOMUXC_GPIO_SD_B1_11_FLEXSPIA_DATA03 0x401F8200U, 0x1U, 0x401F84B4U, 0x0U, 0x401F83F0U +#define IOMUXC_GPIO_SD_B1_11_LPUART2_TX 0x401F8200U, 0x2U, 0x401F8530U, 0x0U, 0x401F83F0U +#define IOMUXC_GPIO_SD_B1_11_LPI2C2_SCL 0x401F8200U, 0x3U, 0x401F84D4U, 0x0U, 0x401F83F0U +#define IOMUXC_GPIO_SD_B1_11_LPSPI2_PCS3 0x401F8200U, 0x4U, 0, 0, 0x401F83F0U +#define IOMUXC_GPIO_SD_B1_11_GPIO3_IO11 0x401F8200U, 0x5U, 0, 0, 0x401F83F0U + +#define IOMUXC_GPR_SAIMCLK_LOWBITMASK (0x7U) +#define IOMUXC_GPR_SAIMCLK_HIGHBITMASK (0x3U) + +typedef enum _iomuxc_gpr_mode +{ + kIOMUXC_GPR_GlobalInterruptRequest = IOMUXC_GPR_GPR1_GINT_MASK, + kIOMUXC_GPR_ENET1RefClkMode = IOMUXC_GPR_GPR1_ENET1_CLK_SEL_MASK, + kIOMUXC_GPR_USBExposureMode = IOMUXC_GPR_GPR1_USB_EXP_MODE_MASK, + kIOMUXC_GPR_ENET1TxClkOutputDir = IOMUXC_GPR_GPR1_ENET1_TX_CLK_DIR_MASK, + kIOMUXC_GPR_SAI1MClkOutputDir = IOMUXC_GPR_GPR1_SAI1_MCLK_DIR_MASK, + kIOMUXC_GPR_SAI2MClkOutputDir = IOMUXC_GPR_GPR1_SAI2_MCLK_DIR_MASK, + kIOMUXC_GPR_SAI3MClkOutputDir = IOMUXC_GPR_GPR1_SAI3_MCLK_DIR_MASK, + kIOMUXC_GPR_ExcMonitorSlavErrResponse = IOMUXC_GPR_GPR1_EXC_MON_MASK, + kIOMUXC_GPR_ENETIpgClkOn = IOMUXC_GPR_GPR1_ENET_IPG_CLK_S_EN_MASK, + kIOMUXC_GPR_AHBClockEnable = (int)IOMUXC_GPR_GPR1_CM7_FORCE_HCLK_EN_MASK, +} iomuxc_gpr_mode_t; + +typedef enum _iomuxc_gpr_saimclk +{ + kIOMUXC_GPR_SAI1MClk1Sel = IOMUXC_GPR_GPR1_SAI1_MCLK1_SEL_SHIFT, + kIOMUXC_GPR_SAI1MClk2Sel = IOMUXC_GPR_GPR1_SAI1_MCLK2_SEL_SHIFT, + kIOMUXC_GPR_SAI1MClk3Sel = IOMUXC_GPR_GPR1_SAI1_MCLK3_SEL_SHIFT, + kIOMUXC_GPR_SAI2MClk3Sel = IOMUXC_GPR_GPR1_SAI2_MCLK3_SEL_SHIFT, + kIOMUXC_GPR_SAI3MClk3Sel = IOMUXC_GPR_GPR1_SAI3_MCLK3_SEL_SHIFT, +} iomuxc_gpr_saimclk_t; + +typedef enum _iomuxc_mqs_pwm_oversample_rate +{ + kIOMUXC_MqsPwmOverSampleRate32 = 0, /* MQS PWM over sampling rate 32. */ + kIOMUXC_MqsPwmOverSampleRate64 = 1 /* MQS PWM over sampling rate 64. */ +} iomuxc_mqs_pwm_oversample_rate_t; + +/*@}*/ + +#if defined(__cplusplus) +extern "C" { +#endif /*_cplusplus */ + +/*! @name Configuration */ +/*@{*/ + +/*! + * @brief Sets the IOMUXC pin mux mode. + * @note The first five parameters can be filled with the pin function ID macros. + * + * This is an example to set the PTA6 as the lpuart0_tx: + * @code + * IOMUXC_SetPinMux(IOMUXC_PTA6_LPUART0_TX, 0); + * @endcode + * + * This is an example to set the PTA0 as GPIOA0: + * @code + * IOMUXC_SetPinMux(IOMUXC_PTA0_GPIOA0, 0); + * @endcode + * + * @param muxRegister The pin mux register. + * @param muxMode The pin mux mode. + * @param inputRegister The select input register. + * @param inputDaisy The input daisy. + * @param configRegister The config register. + * @param inputOnfield Software input on field. + */ +static inline void IOMUXC_SetPinMux(uint32_t muxRegister, + uint32_t muxMode, + uint32_t inputRegister, + uint32_t inputDaisy, + uint32_t configRegister, + uint32_t inputOnfield) +{ + *((volatile uint32_t *)muxRegister) = + IOMUXC_SW_MUX_CTL_PAD_MUX_MODE(muxMode) | IOMUXC_SW_MUX_CTL_PAD_SION(inputOnfield); + + if (inputRegister) + { + *((volatile uint32_t *)inputRegister) = inputDaisy; + } +} + +/*! + * @brief Sets the IOMUXC pin configuration. + * @note The previous five parameters can be filled with the pin function ID macros. + * + * This is an example to set pin configuration for IOMUXC_PTA3_LPI2C0_SCLS: + * @code + * IOMUXC_SetPinConfig(IOMUXC_PTA3_LPI2C0_SCLS,IOMUXC_SW_PAD_CTL_PAD_PUS_MASK|IOMUXC_SW_PAD_CTL_PAD_PUS(2U)) + * @endcode + * + * @param muxRegister The pin mux register. + * @param muxMode The pin mux mode. + * @param inputRegister The select input register. + * @param inputDaisy The input daisy. + * @param configRegister The config register. + * @param configValue The pin config value. + */ +static inline void IOMUXC_SetPinConfig(uint32_t muxRegister, + uint32_t muxMode, + uint32_t inputRegister, + uint32_t inputDaisy, + uint32_t configRegister, + uint32_t configValue) +{ + if (configRegister) + { + *((volatile uint32_t *)configRegister) = configValue; + } +} + +/*! + * @brief Sets IOMUXC general configuration for some mode. + * + * @param base The IOMUXC GPR base address. + * @param mode The mode for setting. the mode is the logical OR of "iomuxc_gpr_mode" + * @param enable True enable false disable. + */ +static inline void IOMUXC_EnableMode(IOMUXC_GPR_Type *base, uint32_t mode, bool enable) +{ + mode &= ~(IOMUXC_GPR_GPR1_SAI1_MCLK1_SEL_MASK | IOMUXC_GPR_GPR1_SAI1_MCLK2_SEL_MASK | + IOMUXC_GPR_GPR1_SAI1_MCLK3_SEL_MASK | IOMUXC_GPR_GPR1_SAI2_MCLK3_SEL_MASK | + IOMUXC_GPR_GPR1_SAI3_MCLK3_SEL_MASK); + + if (enable) + { + base->GPR1 |= mode; + } + else + { + base->GPR1 &= ~mode; + } +} + +/*! + * @brief Sets IOMUXC general configuration for SAI MCLK selection. + * + * @param base The IOMUXC GPR base address. + * @param mclk The SAI MCLK. + * @param clkSrc The clock source. Take refer to register setting details for the clock source in RM. + */ +static inline void IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR_Type *base, iomuxc_gpr_saimclk_t mclk, uint8_t clkSrc) +{ + uint32_t gpr; + + if (mclk > kIOMUXC_GPR_SAI1MClk2Sel) + { + gpr = base->GPR1 & ~(IOMUXC_GPR_SAIMCLK_HIGHBITMASK << mclk); + base->GPR1 = ((clkSrc & IOMUXC_GPR_SAIMCLK_HIGHBITMASK) << mclk) | gpr; + } + else + { + gpr = base->GPR1 & ~(IOMUXC_GPR_SAIMCLK_LOWBITMASK << mclk); + base->GPR1 = ((clkSrc & IOMUXC_GPR_SAIMCLK_LOWBITMASK) << mclk) | gpr; + } +} + +/*! + * @brief Enters or exit MQS software reset. + * + * @param base The IOMUXC GPR base address. + * @param enable Enter or exit MQS software reset. + */ +static inline void IOMUXC_MQSEnterSoftwareReset(IOMUXC_GPR_Type *base, bool enable) +{ + if (enable) + { + base->GPR2 |= IOMUXC_GPR_GPR2_MQS_SW_RST_MASK; + } + else + { + base->GPR2 &= ~IOMUXC_GPR_GPR2_MQS_SW_RST_MASK; + } +} + +/*! + * @brief Enables or disables MQS. + * + * @param base The IOMUXC GPR base address. + * @param enable Enable or disable the MQS. + */ +static inline void IOMUXC_MQSEnable(IOMUXC_GPR_Type *base, bool enable) +{ + if (enable) + { + base->GPR2 |= IOMUXC_GPR_GPR2_MQS_EN_MASK; + } + else + { + base->GPR2 &= ~IOMUXC_GPR_GPR2_MQS_EN_MASK; + } +} + +/*! + * @brief Configure MQS PWM oversampling rate compared with mclk and divider ratio control for mclk from hmclk. + * + * @param base The IOMUXC GPR base address. + * @param rate The MQS PWM oversampling rate, refer to "iomuxc_mqs_pwm_oversample_rate_t". + * @param divider The divider ratio control for mclk from hmclk. mclk freq = 1 /(divider + 1) * hmclk freq. + */ + +static inline void IOMUXC_MQSConfig(IOMUXC_GPR_Type *base, iomuxc_mqs_pwm_oversample_rate_t rate, uint8_t divider) +{ + uint32_t gpr = base->GPR2 & ~(IOMUXC_GPR_GPR2_MQS_OVERSAMPLE_MASK | IOMUXC_GPR_GPR2_MQS_CLK_DIV_MASK); + + base->GPR2 = gpr | IOMUXC_GPR_GPR2_MQS_OVERSAMPLE(rate) | IOMUXC_GPR_GPR2_MQS_CLK_DIV(divider); +} + +/*@}*/ + +#if defined(__cplusplus) +} +#endif /*_cplusplus */ + +/*! @}*/ + +#endif /* _FSL_IOMUXC_H_ */ diff --git a/Ubiquitous/XiZi/board/xidatong/third_party_driver/include/fsl_lpi2c.h b/Ubiquitous/XiZi/board/xidatong/third_party_driver/include/fsl_lpi2c.h new file mode 100755 index 0000000..d2523cc --- /dev/null +++ b/Ubiquitous/XiZi/board/xidatong/third_party_driver/include/fsl_lpi2c.h @@ -0,0 +1,1280 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * Copyright 2016-2019 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +/** + * @file fsl_lpi2c.h + * @brief support imxrt1052-board i2c driver + * @version 2.0 + * @author AIIT XUOS Lab + * @date 2022-03-15 + */ + +#ifndef _FSL_LPI2C_H_ +#define _FSL_LPI2C_H_ + +#include +#include "fsl_device_registers.h" +#include "fsl_common.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! + * @addtogroup lpi2c + * @{ + */ + +/*! @name Driver version */ +/*@{*/ +/*! @brief LPI2C driver version 2.1.9. */ +#define FSL_LPI2C_DRIVER_VERSION (MAKE_VERSION(2, 1, 9)) +/*@}*/ + +/*! @brief Timeout times for waiting flag. */ +#ifndef LPI2C_WAIT_TIMEOUT +#define LPI2C_WAIT_TIMEOUT 0U /* Define to zero means keep waiting until the flag is assert/deassert. */ +#endif + +/*! @brief LPI2C status return codes. */ +enum _lpi2c_status +{ + kStatus_LPI2C_Busy = MAKE_STATUS(kStatusGroup_LPI2C, 0), /*!< The master is already performing a transfer. */ + kStatus_LPI2C_Idle = MAKE_STATUS(kStatusGroup_LPI2C, 1), /*!< The slave driver is idle. */ + kStatus_LPI2C_Nak = MAKE_STATUS(kStatusGroup_LPI2C, 2), /*!< The slave device sent a NAK in response to a byte. */ + kStatus_LPI2C_FifoError = MAKE_STATUS(kStatusGroup_LPI2C, 3), /*!< FIFO under run or overrun. */ + kStatus_LPI2C_BitError = MAKE_STATUS(kStatusGroup_LPI2C, 4), /*!< Transferred bit was not seen on the bus. */ + kStatus_LPI2C_ArbitrationLost = MAKE_STATUS(kStatusGroup_LPI2C, 5), /*!< Arbitration lost error. */ + kStatus_LPI2C_PinLowTimeout = + MAKE_STATUS(kStatusGroup_LPI2C, 6), /*!< SCL or SDA were held low longer than the timeout. */ + kStatus_LPI2C_NoTransferInProgress = + MAKE_STATUS(kStatusGroup_LPI2C, 7), /*!< Attempt to abort a transfer when one is not in progress. */ + kStatus_LPI2C_DmaRequestFail = MAKE_STATUS(kStatusGroup_LPI2C, 8), /*!< DMA request failed. */ + kStatus_LPI2C_Timeout = MAKE_STATUS(kStatusGroup_LPI2C, 9), /*!< Timeout poling status flags. */ +}; + +/*! @} */ + +/*! + * @addtogroup lpi2c_master_driver + * @{ + */ + +/*! + * @brief LPI2C master peripheral flags. + * + * The following status register flags can be cleared: + * - #kLPI2C_MasterEndOfPacketFlag + * - #kLPI2C_MasterStopDetectFlag + * - #kLPI2C_MasterNackDetectFlag + * - #kLPI2C_MasterArbitrationLostFlag + * - #kLPI2C_MasterFifoErrFlag + * - #kLPI2C_MasterPinLowTimeoutFlag + * - #kLPI2C_MasterDataMatchFlag + * + * All flags except #kLPI2C_MasterBusyFlag and #kLPI2C_MasterBusBusyFlag can be enabled as + * interrupts. + * + * @note These enums are meant to be OR'd together to form a bit mask. + */ +enum _lpi2c_master_flags +{ + kLPI2C_MasterTxReadyFlag = LPI2C_MSR_TDF_MASK, /*!< Transmit data flag */ + kLPI2C_MasterRxReadyFlag = LPI2C_MSR_RDF_MASK, /*!< Receive data flag */ + kLPI2C_MasterEndOfPacketFlag = LPI2C_MSR_EPF_MASK, /*!< End Packet flag */ + kLPI2C_MasterStopDetectFlag = LPI2C_MSR_SDF_MASK, /*!< Stop detect flag */ + kLPI2C_MasterNackDetectFlag = LPI2C_MSR_NDF_MASK, /*!< NACK detect flag */ + kLPI2C_MasterArbitrationLostFlag = LPI2C_MSR_ALF_MASK, /*!< Arbitration lost flag */ + kLPI2C_MasterFifoErrFlag = LPI2C_MSR_FEF_MASK, /*!< FIFO error flag */ + kLPI2C_MasterPinLowTimeoutFlag = LPI2C_MSR_PLTF_MASK, /*!< Pin low timeout flag */ + kLPI2C_MasterDataMatchFlag = LPI2C_MSR_DMF_MASK, /*!< Data match flag */ + kLPI2C_MasterBusyFlag = LPI2C_MSR_MBF_MASK, /*!< Master busy flag */ + kLPI2C_MasterBusBusyFlag = LPI2C_MSR_BBF_MASK /*!< Bus busy flag */ +}; + +/*! @brief Direction of master and slave transfers. */ +typedef enum _lpi2c_direction +{ + kLPI2C_Write = 0U, /*!< Master transmit. */ + kLPI2C_Read = 1U /*!< Master receive. */ +} lpi2c_direction_t; + +/*! @brief LPI2C pin configuration. */ +typedef enum _lpi2c_master_pin_config +{ + kLPI2C_2PinOpenDrain = 0x0U, /*!< LPI2C Configured for 2-pin open drain mode */ + kLPI2C_2PinOutputOnly = 0x1U, /*!< LPI2C Configured for 2-pin output only mode (ultra-fast mode) */ + kLPI2C_2PinPushPull = 0x2U, /*!< LPI2C Configured for 2-pin push-pull mode */ + kLPI2C_4PinPushPull = 0x3U, /*!< LPI2C Configured for 4-pin push-pull mode */ + kLPI2C_2PinOpenDrainWithSeparateSlave = + 0x4U, /*!< LPI2C Configured for 2-pin open drain mode with separate LPI2C slave */ + kLPI2C_2PinOutputOnlyWithSeparateSlave = + 0x5U, /*!< LPI2C Configured for 2-pin output only mode(ultra-fast mode) with separate LPI2C slave */ + kLPI2C_2PinPushPullWithSeparateSlave = + 0x6U, /*!< LPI2C Configured for 2-pin push-pull mode with separate LPI2C slave */ + kLPI2C_4PinPushPullWithInvertedOutput = 0x7U /*!< LPI2C Configured for 4-pin push-pull mode(inverted outputs) */ +} lpi2c_master_pin_config_t; + +/*! @brief LPI2C master host request selection. */ +typedef enum _lpi2c_host_request_source +{ + kLPI2C_HostRequestExternalPin = 0x0U, /*!< Select the LPI2C_HREQ pin as the host request input */ + kLPI2C_HostRequestInputTrigger = 0x1U, /*!< Select the input trigger as the host request input */ +} lpi2c_host_request_source_t; + +/*! @brief LPI2C master host request pin polarity configuration. */ +typedef enum _lpi2c_host_request_polarity +{ + kLPI2C_HostRequestPinActiveLow = 0x0U, /*!< Configure the LPI2C_HREQ pin active low */ + kLPI2C_HostRequestPinActiveHigh = 0x1U /*!< Configure the LPI2C_HREQ pin active high */ +} lpi2c_host_request_polarity_t; + +/*! + * @brief Structure with settings to initialize the LPI2C master module. + * + * This structure holds configuration settings for the LPI2C peripheral. To initialize this + * structure to reasonable defaults, call the LPI2C_MasterGetDefaultConfig() function and + * pass a pointer to your configuration structure instance. + * + * The configuration structure can be made constant so it resides in flash. + */ +typedef struct _lpi2c_master_config +{ + bool enableMaster; /*!< Whether to enable master mode. */ + bool enableDoze; /*!< Whether master is enabled in doze mode. */ + bool debugEnable; /*!< Enable transfers to continue when halted in debug mode. */ + bool ignoreAck; /*!< Whether to ignore ACK/NACK. */ + lpi2c_master_pin_config_t pinConfig; /*!< The pin configuration option. */ + uint32_t baudRate_Hz; /*!< Desired baud rate in Hertz. */ + uint32_t busIdleTimeout_ns; /*!< Bus idle timeout in nanoseconds. Set to 0 to disable. */ + uint32_t pinLowTimeout_ns; /*!< Pin low timeout in nanoseconds. Set to 0 to disable. */ + uint8_t sdaGlitchFilterWidth_ns; /*!< Width in nanoseconds of glitch filter on SDA pin. Set to 0 to disable. */ + uint8_t sclGlitchFilterWidth_ns; /*!< Width in nanoseconds of glitch filter on SCL pin. Set to 0 to disable. */ + struct + { + bool enable; /*!< Enable host request. */ + lpi2c_host_request_source_t source; /*!< Host request source. */ + lpi2c_host_request_polarity_t polarity; /*!< Host request pin polarity. */ + } hostRequest; /*!< Host request options. */ +} lpi2c_master_config_t; + +/*! @brief LPI2C master data match configuration modes. */ +typedef enum _lpi2c_data_match_config_mode +{ + kLPI2C_MatchDisabled = 0x0U, /*!< LPI2C Match Disabled */ + kLPI2C_1stWordEqualsM0OrM1 = 0x2U, /*!< LPI2C Match Enabled and 1st data word equals MATCH0 OR MATCH1 */ + kLPI2C_AnyWordEqualsM0OrM1 = 0x3U, /*!< LPI2C Match Enabled and any data word equals MATCH0 OR MATCH1 */ + kLPI2C_1stWordEqualsM0And2ndWordEqualsM1 = + 0x4U, /*!< LPI2C Match Enabled and 1st data word equals MATCH0, 2nd data equals MATCH1 */ + kLPI2C_AnyWordEqualsM0AndNextWordEqualsM1 = + 0x5U, /*!< LPI2C Match Enabled and any data word equals MATCH0, next data equals MATCH1 */ + kLPI2C_1stWordAndM1EqualsM0AndM1 = + 0x6U, /*!< LPI2C Match Enabled and 1st data word and MATCH0 equals MATCH0 and MATCH1 */ + kLPI2C_AnyWordAndM1EqualsM0AndM1 = + 0x7U /*!< LPI2C Match Enabled and any data word and MATCH0 equals MATCH0 and MATCH1 */ +} lpi2c_data_match_config_mode_t; + +/*! @brief LPI2C master data match configuration structure. */ +typedef struct _lpi2c_match_config +{ + lpi2c_data_match_config_mode_t matchMode; /*!< Data match configuration setting. */ + bool rxDataMatchOnly; /*!< When set to true, received data is ignored until a successful match. */ + uint32_t match0; /*!< Match value 0. */ + uint32_t match1; /*!< Match value 1. */ +} lpi2c_data_match_config_t; + +/* Forward declaration of the transfer descriptor and handle typedefs. */ +typedef struct _lpi2c_master_transfer lpi2c_master_transfer_t; +typedef struct _lpi2c_master_handle lpi2c_master_handle_t; + +/*! + * @brief Master completion callback function pointer type. + * + * This callback is used only for the non-blocking master transfer API. Specify the callback you wish to use + * in the call to LPI2C_MasterTransferCreateHandle(). + * + * @param base The LPI2C peripheral base address. + * @param completionStatus Either #kStatus_Success or an error code describing how the transfer completed. + * @param userData Arbitrary pointer-sized value passed from the application. + */ +typedef void (*lpi2c_master_transfer_callback_t)(LPI2C_Type *base, + lpi2c_master_handle_t *handle, + status_t completionStatus, + void *userData); + +/*! + * @brief Transfer option flags. + * + * @note These enumerations are intended to be OR'd together to form a bit mask of options for + * the #_lpi2c_master_transfer::flags field. + */ +enum _lpi2c_master_transfer_flags +{ + kLPI2C_TransferDefaultFlag = 0x00U, /*!< Transfer starts with a start signal, stops with a stop signal. */ + kLPI2C_TransferNoStartFlag = 0x01U, /*!< Don't send a start condition, address, and sub address */ + kLPI2C_TransferRepeatedStartFlag = 0x02U, /*!< Send a repeated start condition */ + kLPI2C_TransferNoStopFlag = 0x04U, /*!< Don't send a stop condition. */ +}; + +/*! + * @brief Non-blocking transfer descriptor structure. + * + * This structure is used to pass transaction parameters to the LPI2C_MasterTransferNonBlocking() API. + */ +struct _lpi2c_master_transfer +{ + uint32_t flags; /*!< Bit mask of options for the transfer. See enumeration #_lpi2c_master_transfer_flags for + available options. Set to 0 or #kLPI2C_TransferDefaultFlag for normal transfers. */ + uint16_t slaveAddress; /*!< The 7-bit slave address. */ + lpi2c_direction_t direction; /*!< Either #kLPI2C_Read or #kLPI2C_Write. */ + uint32_t subaddress; /*!< Sub address. Transferred MSB first. */ + size_t subaddressSize; /*!< Length of sub address to send in bytes. Maximum size is 4 bytes. */ + void *data; /*!< Pointer to data to transfer. */ + size_t dataSize; /*!< Number of bytes to transfer. */ +}; + +/*! + * @brief Driver handle for master non-blocking APIs. + * @note The contents of this structure are private and subject to change. + */ +struct _lpi2c_master_handle +{ + uint8_t state; /*!< Transfer state machine current state. */ + uint16_t remainingBytes; /*!< Remaining byte count in current state. */ + uint8_t *buf; /*!< Buffer pointer for current state. */ + uint16_t commandBuffer[7]; /*!< LPI2C command sequence. */ + lpi2c_master_transfer_t transfer; /*!< Copy of the current transfer info. */ + lpi2c_master_transfer_callback_t completionCallback; /*!< Callback function pointer. */ + void *userData; /*!< Application data passed to callback. */ +}; + +/*! @} */ + +/*! + * @addtogroup lpi2c_slave_driver + * @{ + */ + +/*! + * @brief LPI2C slave peripheral flags. + * + * The following status register flags can be cleared: + * - #kLPI2C_SlaveRepeatedStartDetectFlag + * - #kLPI2C_SlaveStopDetectFlag + * - #kLPI2C_SlaveBitErrFlag + * - #kLPI2C_SlaveFifoErrFlag + * + * All flags except #kLPI2C_SlaveBusyFlag and #kLPI2C_SlaveBusBusyFlag can be enabled as + * interrupts. + * + * @note These enumerations are meant to be OR'd together to form a bit mask. + */ +enum _lpi2c_slave_flags +{ + kLPI2C_SlaveTxReadyFlag = LPI2C_SSR_TDF_MASK, /*!< Transmit data flag */ + kLPI2C_SlaveRxReadyFlag = LPI2C_SSR_RDF_MASK, /*!< Receive data flag */ + kLPI2C_SlaveAddressValidFlag = LPI2C_SSR_AVF_MASK, /*!< Address valid flag */ + kLPI2C_SlaveTransmitAckFlag = LPI2C_SSR_TAF_MASK, /*!< Transmit ACK flag */ + kLPI2C_SlaveRepeatedStartDetectFlag = LPI2C_SSR_RSF_MASK, /*!< Repeated start detect flag */ + kLPI2C_SlaveStopDetectFlag = LPI2C_SSR_SDF_MASK, /*!< Stop detect flag */ + kLPI2C_SlaveBitErrFlag = LPI2C_SSR_BEF_MASK, /*!< Bit error flag */ + kLPI2C_SlaveFifoErrFlag = LPI2C_SSR_FEF_MASK, /*!< FIFO error flag */ + kLPI2C_SlaveAddressMatch0Flag = LPI2C_SSR_AM0F_MASK, /*!< Address match 0 flag */ + kLPI2C_SlaveAddressMatch1Flag = LPI2C_SSR_AM1F_MASK, /*!< Address match 1 flag */ + kLPI2C_SlaveGeneralCallFlag = LPI2C_SSR_GCF_MASK, /*!< General call flag */ + kLPI2C_SlaveBusyFlag = LPI2C_SSR_SBF_MASK, /*!< Master busy flag */ + kLPI2C_SlaveBusBusyFlag = LPI2C_SSR_BBF_MASK, /*!< Bus busy flag */ +}; + +/*! @brief LPI2C slave address match options. */ +typedef enum _lpi2c_slave_address_match +{ + kLPI2C_MatchAddress0 = 0U, /*!< Match only address 0. */ + kLPI2C_MatchAddress0OrAddress1 = 2U, /*!< Match either address 0 or address 1. */ + kLPI2C_MatchAddress0ThroughAddress1 = 6U, /*!< Match a range of slave addresses from address 0 through address 1. */ +} lpi2c_slave_address_match_t; + +/*! + * @brief Structure with settings to initialize the LPI2C slave module. + * + * This structure holds configuration settings for the LPI2C slave peripheral. To initialize this + * structure to reasonable defaults, call the LPI2C_SlaveGetDefaultConfig() function and + * pass a pointer to your configuration structure instance. + * + * The configuration structure can be made constant so it resides in flash. + */ +typedef struct _lpi2c_slave_config +{ + bool enableSlave; /*!< Enable slave mode. */ + uint8_t address0; /*!< Slave's 7-bit address. */ + uint8_t address1; /*!< Alternate slave 7-bit address. */ + lpi2c_slave_address_match_t addressMatchMode; /*!< Address matching options. */ + bool filterDozeEnable; /*!< Enable digital glitch filter in doze mode. */ + bool filterEnable; /*!< Enable digital glitch filter. */ + bool enableGeneralCall; /*!< Enable general call address matching. */ + struct + { + bool enableAck; /*!< Enables SCL clock stretching during slave-transmit address byte(s) + and slave-receiver address and data byte(s) to allow software to + write the Transmit ACK Register before the ACK or NACK is transmitted. + Clock stretching occurs when transmitting the 9th bit. When + enableAckSCLStall is enabled, there is no need to set either + enableRxDataSCLStall or enableAddressSCLStall. */ + bool enableTx; /*!< Enables SCL clock stretching when the transmit data flag is set + during a slave-transmit transfer. */ + bool enableRx; /*!< Enables SCL clock stretching when receive data flag is set during + a slave-receive transfer. */ + bool enableAddress; /*!< Enables SCL clock stretching when the address valid flag is asserted. */ + } sclStall; + bool ignoreAck; /*!< Continue transfers after a NACK is detected. */ + bool enableReceivedAddressRead; /*!< Enable reading the address received address as the first byte of data. */ + uint32_t sdaGlitchFilterWidth_ns; /*!< Width in nanoseconds of the digital filter on the SDA signal. */ + uint32_t sclGlitchFilterWidth_ns; /*!< Width in nanoseconds of the digital filter on the SCL signal. */ + uint32_t dataValidDelay_ns; /*!< Width in nanoseconds of the data valid delay. */ + uint32_t clockHoldTime_ns; /*!< Width in nanoseconds of the clock hold time. */ +} lpi2c_slave_config_t; + +/*! + * @brief Set of events sent to the callback for non blocking slave transfers. + * + * These event enumerations are used for two related purposes. First, a bit mask created by OR'ing together + * events is passed to LPI2C_SlaveTransferNonBlocking() in order to specify which events to enable. + * Then, when the slave callback is invoked, it is passed the current event through its @a transfer + * parameter. + * + * @note These enumerations are meant to be OR'd together to form a bit mask of events. + */ +typedef enum _lpi2c_slave_transfer_event +{ + kLPI2C_SlaveAddressMatchEvent = 0x01U, /*!< Received the slave address after a start or repeated start. */ + kLPI2C_SlaveTransmitEvent = 0x02U, /*!< Callback is requested to provide data to transmit + (slave-transmitter role). */ + kLPI2C_SlaveReceiveEvent = 0x04U, /*!< Callback is requested to provide a buffer in which to place received + data (slave-receiver role). */ + kLPI2C_SlaveTransmitAckEvent = 0x08U, /*!< Callback needs to either transmit an ACK or NACK. */ + kLPI2C_SlaveRepeatedStartEvent = 0x10U, /*!< A repeated start was detected. */ + kLPI2C_SlaveCompletionEvent = 0x20U, /*!< A stop was detected, completing the transfer. */ + + /*! Bit mask of all available events. */ + kLPI2C_SlaveAllEvents = kLPI2C_SlaveAddressMatchEvent | kLPI2C_SlaveTransmitEvent | kLPI2C_SlaveReceiveEvent | + kLPI2C_SlaveTransmitAckEvent | kLPI2C_SlaveRepeatedStartEvent | kLPI2C_SlaveCompletionEvent, +} lpi2c_slave_transfer_event_t; + +/*! @brief LPI2C slave transfer structure */ +typedef struct _lpi2c_slave_transfer +{ + lpi2c_slave_transfer_event_t event; /*!< Reason the callback is being invoked. */ + uint8_t receivedAddress; /*!< Matching address send by master. */ + uint8_t *data; /*!< Transfer buffer */ + size_t dataSize; /*!< Transfer size */ + status_t completionStatus; /*!< Success or error code describing how the transfer completed. Only applies for + #kLPI2C_SlaveCompletionEvent. */ + size_t transferredCount; /*!< Number of bytes actually transferred since start or last repeated start. */ +} lpi2c_slave_transfer_t; + +/* Forward declaration. */ +typedef struct _lpi2c_slave_handle lpi2c_slave_handle_t; + +/*! + * @brief Slave event callback function pointer type. + * + * This callback is used only for the slave non-blocking transfer API. To install a callback, + * use the LPI2C_SlaveSetCallback() function after you have created a handle. + * + * @param base Base address for the LPI2C instance on which the event occurred. + * @param transfer Pointer to transfer descriptor containing values passed to and/or from the callback. + * @param userData Arbitrary pointer-sized value passed from the application. + */ +typedef void (*lpi2c_slave_transfer_callback_t)(LPI2C_Type *base, lpi2c_slave_transfer_t *transfer, void *userData); + +/*! + * @brief LPI2C slave handle structure. + * @note The contents of this structure are private and subject to change. + */ +struct _lpi2c_slave_handle +{ + lpi2c_slave_transfer_t transfer; /*!< LPI2C slave transfer copy. */ + bool isBusy; /*!< Whether transfer is busy. */ + bool wasTransmit; /*!< Whether the last transfer was a transmit. */ + uint32_t eventMask; /*!< Mask of enabled events. */ + uint32_t transferredCount; /*!< Count of bytes transferred. */ + lpi2c_slave_transfer_callback_t callback; /*!< Callback function called at transfer event. */ + void *userData; /*!< Callback parameter passed to callback. */ +}; + +/*! @} */ + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @addtogroup lpi2c_master_driver + * @{ + */ + +/*! @name Initialization and deinitialization */ +/*@{*/ + +/*! + * @brief Provides a default configuration for the LPI2C master peripheral. + * + * This function provides the following default configuration for the LPI2C master peripheral: + * @code + * masterConfig->enableMaster = true; + * masterConfig->debugEnable = false; + * masterConfig->ignoreAck = false; + * masterConfig->pinConfig = kLPI2C_2PinOpenDrain; + * masterConfig->baudRate_Hz = 100000U; + * masterConfig->busIdleTimeout_ns = 0; + * masterConfig->pinLowTimeout_ns = 0; + * masterConfig->sdaGlitchFilterWidth_ns = 0; + * masterConfig->sclGlitchFilterWidth_ns = 0; + * masterConfig->hostRequest.enable = false; + * masterConfig->hostRequest.source = kLPI2C_HostRequestExternalPin; + * masterConfig->hostRequest.polarity = kLPI2C_HostRequestPinActiveHigh; + * @endcode + * + * After calling this function, you can override any settings in order to customize the configuration, + * prior to initializing the master driver with LPI2C_MasterInit(). + * + * @param[out] masterConfig User provided configuration structure for default values. Refer to #lpi2c_master_config_t. + */ +void LPI2C_MasterGetDefaultConfig(lpi2c_master_config_t *masterConfig); + +/*! + * @brief Initializes the LPI2C master peripheral. + * + * This function enables the peripheral clock and initializes the LPI2C master peripheral as described by the user + * provided configuration. A software reset is performed prior to configuration. + * + * @param base The LPI2C peripheral base address. + * @param masterConfig User provided peripheral configuration. Use LPI2C_MasterGetDefaultConfig() to get a set of + * defaults + * that you can override. + * @param sourceClock_Hz Frequency in Hertz of the LPI2C functional clock. Used to calculate the baud rate divisors, + * filter widths, and timeout periods. + */ +void LPI2C_MasterInit(LPI2C_Type *base, const lpi2c_master_config_t *masterConfig, uint32_t sourceClock_Hz); + +/*! + * @brief Deinitializes the LPI2C master peripheral. + * + * This function disables the LPI2C master peripheral and gates the clock. It also performs a software + * reset to restore the peripheral to reset conditions. + * + * @param base The LPI2C peripheral base address. + */ +void LPI2C_MasterDeinit(LPI2C_Type *base); + +/*! + * @brief Configures LPI2C master data match feature. + * + * @param base The LPI2C peripheral base address. + * @param config Settings for the data match feature. + */ +void LPI2C_MasterConfigureDataMatch(LPI2C_Type *base, const lpi2c_data_match_config_t *config); + +/* Not static so it can be used from fsl_lpi2c_edma.c. */ +status_t LPI2C_MasterCheckAndClearError(LPI2C_Type *base, uint32_t status); + +/* Not static so it can be used from fsl_lpi2c_edma.c. */ +status_t LPI2C_CheckForBusyBus(LPI2C_Type *base); + +/*! + * @brief Performs a software reset. + * + * Restores the LPI2C master peripheral to reset conditions. + * + * @param base The LPI2C peripheral base address. + */ +static inline void LPI2C_MasterReset(LPI2C_Type *base) +{ + base->MCR = LPI2C_MCR_RST_MASK; + base->MCR = 0; +} + +/*! + * @brief Enables or disables the LPI2C module as master. + * + * @param base The LPI2C peripheral base address. + * @param enable Pass true to enable or false to disable the specified LPI2C as master. + */ +static inline void LPI2C_MasterEnable(LPI2C_Type *base, bool enable) +{ + base->MCR = (base->MCR & ~LPI2C_MCR_MEN_MASK) | LPI2C_MCR_MEN(enable); +} + +/*@}*/ + +/*! @name Status */ +/*@{*/ + +/*! + * @brief Gets the LPI2C master status flags. + * + * A bit mask with the state of all LPI2C master status flags is returned. For each flag, the corresponding bit + * in the return value is set if the flag is asserted. + * + * @param base The LPI2C peripheral base address. + * @return State of the status flags: + * - 1: related status flag is set. + * - 0: related status flag is not set. + * @see _lpi2c_master_flags + */ +static inline uint32_t LPI2C_MasterGetStatusFlags(LPI2C_Type *base) +{ + return base->MSR; +} + +/*! + * @brief Clears the LPI2C master status flag state. + * + * The following status register flags can be cleared: + * - #kLPI2C_MasterEndOfPacketFlag + * - #kLPI2C_MasterStopDetectFlag + * - #kLPI2C_MasterNackDetectFlag + * - #kLPI2C_MasterArbitrationLostFlag + * - #kLPI2C_MasterFifoErrFlag + * - #kLPI2C_MasterPinLowTimeoutFlag + * - #kLPI2C_MasterDataMatchFlag + * + * Attempts to clear other flags has no effect. + * + * @param base The LPI2C peripheral base address. + * @param statusMask A bitmask of status flags that are to be cleared. The mask is composed of + * #_lpi2c_master_flags enumerators OR'd together. You may pass the result of a previous call to + * LPI2C_MasterGetStatusFlags(). + * @see _lpi2c_master_flags. + */ +static inline void LPI2C_MasterClearStatusFlags(LPI2C_Type *base, uint32_t statusMask) +{ + base->MSR = statusMask; +} + +/*@}*/ + +/*! @name Interrupts */ +/*@{*/ + +/*! + * @brief Enables the LPI2C master interrupt requests. + * + * All flags except #kLPI2C_MasterBusyFlag and #kLPI2C_MasterBusBusyFlag can be enabled as + * interrupts. + * + * @param base The LPI2C peripheral base address. + * @param interruptMask Bit mask of interrupts to enable. See #_lpi2c_master_flags for the set + * of constants that should be OR'd together to form the bit mask. + */ +static inline void LPI2C_MasterEnableInterrupts(LPI2C_Type *base, uint32_t interruptMask) +{ + base->MIER |= interruptMask; +} + +/*! + * @brief Disables the LPI2C master interrupt requests. + * + * All flags except #kLPI2C_MasterBusyFlag and #kLPI2C_MasterBusBusyFlag can be enabled as + * interrupts. + * + * @param base The LPI2C peripheral base address. + * @param interruptMask Bit mask of interrupts to disable. See #_lpi2c_master_flags for the set + * of constants that should be OR'd together to form the bit mask. + */ +static inline void LPI2C_MasterDisableInterrupts(LPI2C_Type *base, uint32_t interruptMask) +{ + base->MIER &= ~interruptMask; +} + +/*! + * @brief Returns the set of currently enabled LPI2C master interrupt requests. + * + * @param base The LPI2C peripheral base address. + * @return A bitmask composed of #_lpi2c_master_flags enumerators OR'd together to indicate the + * set of enabled interrupts. + */ +static inline uint32_t LPI2C_MasterGetEnabledInterrupts(LPI2C_Type *base) +{ + return base->MIER; +} + +/*@}*/ + +/*! @name DMA control */ +/*@{*/ + +/*! + * @brief Enables or disables LPI2C master DMA requests. + * + * @param base The LPI2C peripheral base address. + * @param enableTx Enable flag for transmit DMA request. Pass true for enable, false for disable. + * @param enableRx Enable flag for receive DMA request. Pass true for enable, false for disable. + */ +static inline void LPI2C_MasterEnableDMA(LPI2C_Type *base, bool enableTx, bool enableRx) +{ + base->MDER = LPI2C_MDER_TDDE(enableTx) | LPI2C_MDER_RDDE(enableRx); +} + +/*! + * @brief Gets LPI2C master transmit data register address for DMA transfer. + * + * @param base The LPI2C peripheral base address. + * @return The LPI2C Master Transmit Data Register address. + */ +static inline uint32_t LPI2C_MasterGetTxFifoAddress(LPI2C_Type *base) +{ + return (uint32_t)&base->MTDR; +} + +/*! + * @brief Gets LPI2C master receive data register address for DMA transfer. + * + * @param base The LPI2C peripheral base address. + * @return The LPI2C Master Receive Data Register address. + */ +static inline uint32_t LPI2C_MasterGetRxFifoAddress(LPI2C_Type *base) +{ + return (uint32_t)&base->MRDR; +} + +/*@}*/ + +/*! @name FIFO control */ +/*@{*/ + +/*! + * @brief Sets the watermarks for LPI2C master FIFOs. + * + * @param base The LPI2C peripheral base address. + * @param txWords Transmit FIFO watermark value in words. The #kLPI2C_MasterTxReadyFlag flag is set whenever + * the number of words in the transmit FIFO is equal or less than @a txWords. Writing a value equal or + * greater than the FIFO size is truncated. + * @param rxWords Receive FIFO watermark value in words. The #kLPI2C_MasterRxReadyFlag flag is set whenever + * the number of words in the receive FIFO is greater than @a rxWords. Writing a value equal or greater + * than the FIFO size is truncated. + */ +static inline void LPI2C_MasterSetWatermarks(LPI2C_Type *base, size_t txWords, size_t rxWords) +{ + base->MFCR = LPI2C_MFCR_TXWATER(txWords) | LPI2C_MFCR_RXWATER(rxWords); +} + +/*! + * @brief Gets the current number of words in the LPI2C master FIFOs. + * + * @param base The LPI2C peripheral base address. + * @param[out] txCount Pointer through which the current number of words in the transmit FIFO is returned. + * Pass NULL if this value is not required. + * @param[out] rxCount Pointer through which the current number of words in the receive FIFO is returned. + * Pass NULL if this value is not required. + */ +static inline void LPI2C_MasterGetFifoCounts(LPI2C_Type *base, size_t *rxCount, size_t *txCount) +{ + if (txCount) + { + *txCount = (base->MFSR & LPI2C_MFSR_TXCOUNT_MASK) >> LPI2C_MFSR_TXCOUNT_SHIFT; + } + if (rxCount) + { + *rxCount = (base->MFSR & LPI2C_MFSR_RXCOUNT_MASK) >> LPI2C_MFSR_RXCOUNT_SHIFT; + } +} + +/*@}*/ + +/*! @name Bus operations */ +/*@{*/ + +/*! + * @brief Sets the I2C bus frequency for master transactions. + * + * The LPI2C master is automatically disabled and re-enabled as necessary to configure the baud + * rate. Do not call this function during a transfer, or the transfer is aborted. + * + * @note Please note that the second parameter is the clock frequency of LPI2C module, the third + * parameter means user configured bus baudrate, this implementation is different from other I2C drivers + * which use baudrate configuration as second parameter and source clock frequency as third parameter. + * + * @param base The LPI2C peripheral base address. + * @param sourceClock_Hz LPI2C functional clock frequency in Hertz. + * @param baudRate_Hz Requested bus frequency in Hertz. + */ +void LPI2C_MasterSetBaudRate(LPI2C_Type *base, uint32_t sourceClock_Hz, uint32_t baudRate_Hz); + +/*! + * @brief Returns whether the bus is idle. + * + * Requires the master mode to be enabled. + * + * @param base The LPI2C peripheral base address. + * @retval true Bus is busy. + * @retval false Bus is idle. + */ +static inline bool LPI2C_MasterGetBusIdleState(LPI2C_Type *base) +{ + return (base->MSR & LPI2C_MSR_BBF_MASK) >> LPI2C_MSR_BBF_SHIFT; +} + +/*! + * @brief Sends a START signal and slave address on the I2C bus. + * + * This function is used to initiate a new master mode transfer. First, the bus state is checked to ensure + * that another master is not occupying the bus. Then a START signal is transmitted, followed by the + * 7-bit address specified in the @a address parameter. Note that this function does not actually wait + * until the START and address are successfully sent on the bus before returning. + * + * @param base The LPI2C peripheral base address. + * @param address 7-bit slave device address, in bits [6:0]. + * @param dir Master transfer direction, either #kLPI2C_Read or #kLPI2C_Write. This parameter is used to set + * the R/w bit (bit 0) in the transmitted slave address. + * @retval #kStatus_Success START signal and address were successfully enqueued in the transmit FIFO. + * @retval #kStatus_LPI2C_Busy Another master is currently utilizing the bus. + */ +status_t LPI2C_MasterStart(LPI2C_Type *base, uint8_t address, lpi2c_direction_t dir); + +/*! + * @brief Sends a repeated START signal and slave address on the I2C bus. + * + * This function is used to send a Repeated START signal when a transfer is already in progress. Like + * LPI2C_MasterStart(), it also sends the specified 7-bit address. + * + * @note This function exists primarily to maintain compatible APIs between LPI2C and I2C drivers, + * as well as to better document the intent of code that uses these APIs. + * + * @param base The LPI2C peripheral base address. + * @param address 7-bit slave device address, in bits [6:0]. + * @param dir Master transfer direction, either #kLPI2C_Read or #kLPI2C_Write. This parameter is used to set + * the R/w bit (bit 0) in the transmitted slave address. + * @retval #kStatus_Success Repeated START signal and address were successfully enqueued in the transmit FIFO. + * @retval #kStatus_LPI2C_Busy Another master is currently utilizing the bus. + */ +static inline status_t LPI2C_MasterRepeatedStart(LPI2C_Type *base, uint8_t address, lpi2c_direction_t dir) +{ + return LPI2C_MasterStart(base, address, dir); +} + +/*! + * @brief Performs a polling send transfer on the I2C bus. + * + * Sends up to @a txSize number of bytes to the previously addressed slave device. The slave may + * reply with a NAK to any byte in order to terminate the transfer early. If this happens, this + * function returns #kStatus_LPI2C_Nak. + * + * @param base The LPI2C peripheral base address. + * @param txBuff The pointer to the data to be transferred. + * @param txSize The length in bytes of the data to be transferred. + * @retval #kStatus_Success Data was sent successfully. + * @retval #kStatus_LPI2C_Busy Another master is currently utilizing the bus. + * @retval #kStatus_LPI2C_Nak The slave device sent a NAK in response to a byte. + * @retval #kStatus_LPI2C_FifoError FIFO under run or over run. + * @retval #kStatus_LPI2C_ArbitrationLost Arbitration lost error. + * @retval #kStatus_LPI2C_PinLowTimeout SCL or SDA were held low longer than the timeout. + */ +status_t LPI2C_MasterSend(LPI2C_Type *base, void *txBuff, size_t txSize); + +/*! + * @brief Performs a polling receive transfer on the I2C bus. + * + * @param base The LPI2C peripheral base address. + * @param rxBuff The pointer to the data to be transferred. + * @param rxSize The length in bytes of the data to be transferred. + * @retval #kStatus_Success Data was received successfully. + * @retval #kStatus_LPI2C_Busy Another master is currently utilizing the bus. + * @retval #kStatus_LPI2C_Nak The slave device sent a NAK in response to a byte. + * @retval #kStatus_LPI2C_FifoError FIFO under run or overrun. + * @retval #kStatus_LPI2C_ArbitrationLost Arbitration lost error. + * @retval #kStatus_LPI2C_PinLowTimeout SCL or SDA were held low longer than the timeout. + */ +status_t LPI2C_MasterReceive(LPI2C_Type *base, void *rxBuff, size_t rxSize); + +/*! + * @brief Sends a STOP signal on the I2C bus. + * + * This function does not return until the STOP signal is seen on the bus, or an error occurs. + * + * @param base The LPI2C peripheral base address. + * @retval #kStatus_Success The STOP signal was successfully sent on the bus and the transaction terminated. + * @retval #kStatus_LPI2C_Busy Another master is currently utilizing the bus. + * @retval #kStatus_LPI2C_Nak The slave device sent a NAK in response to a byte. + * @retval #kStatus_LPI2C_FifoError FIFO under run or overrun. + * @retval #kStatus_LPI2C_ArbitrationLost Arbitration lost error. + * @retval #kStatus_LPI2C_PinLowTimeout SCL or SDA were held low longer than the timeout. + */ +status_t LPI2C_MasterStop(LPI2C_Type *base); + +/*! + * @brief Performs a master polling transfer on the I2C bus. + * + * @note The API does not return until the transfer succeeds or fails due + * to error happens during transfer. + * + * @param base The LPI2C peripheral base address. + * @param transfer Pointer to the transfer structure. + * @retval #kStatus_Success Data was received successfully. + * @retval #kStatus_LPI2C_Busy Another master is currently utilizing the bus. + * @retval #kStatus_LPI2C_Nak The slave device sent a NAK in response to a byte. + * @retval #kStatus_LPI2C_FifoError FIFO under run or overrun. + * @retval #kStatus_LPI2C_ArbitrationLost Arbitration lost error. + * @retval #kStatus_LPI2C_PinLowTimeout SCL or SDA were held low longer than the timeout. + */ +status_t LPI2C_MasterTransferBlocking(LPI2C_Type *base, lpi2c_master_transfer_t *transfer); + +/*@}*/ + +/*! @name Non-blocking */ +/*@{*/ + +/*! + * @brief Creates a new handle for the LPI2C master non-blocking APIs. + * + * The creation of a handle is for use with the non-blocking APIs. Once a handle + * is created, there is not a corresponding destroy handle. If the user wants to + * terminate a transfer, the LPI2C_MasterTransferAbort() API shall be called. + * + * + * @note The function also enables the NVIC IRQ for the input LPI2C. Need to notice + * that on some SoCs the LPI2C IRQ is connected to INTMUX, in this case user needs to + * enable the associated INTMUX IRQ in application. + * + * @param base The LPI2C peripheral base address. + * @param[out] handle Pointer to the LPI2C master driver handle. + * @param callback User provided pointer to the asynchronous callback function. + * @param userData User provided pointer to the application callback data. + */ +void LPI2C_MasterTransferCreateHandle(LPI2C_Type *base, + lpi2c_master_handle_t *handle, + lpi2c_master_transfer_callback_t callback, + void *userData); + +/*! + * @brief Performs a non-blocking transaction on the I2C bus. + * + * @param base The LPI2C peripheral base address. + * @param handle Pointer to the LPI2C master driver handle. + * @param transfer The pointer to the transfer descriptor. + * @retval #kStatus_Success The transaction was started successfully. + * @retval #kStatus_LPI2C_Busy Either another master is currently utilizing the bus, or a non-blocking + * transaction is already in progress. + */ +status_t LPI2C_MasterTransferNonBlocking(LPI2C_Type *base, + lpi2c_master_handle_t *handle, + lpi2c_master_transfer_t *transfer); + +/*! + * @brief Returns number of bytes transferred so far. + * @param base The LPI2C peripheral base address. + * @param handle Pointer to the LPI2C master driver handle. + * @param[out] count Number of bytes transferred so far by the non-blocking transaction. + * @retval #kStatus_Success + * @retval #kStatus_NoTransferInProgress There is not a non-blocking transaction currently in progress. + */ +status_t LPI2C_MasterTransferGetCount(LPI2C_Type *base, lpi2c_master_handle_t *handle, size_t *count); + +/*! + * @brief Terminates a non-blocking LPI2C master transmission early. + * + * @note It is not safe to call this function from an IRQ handler that has a higher priority than the + * LPI2C peripheral's IRQ priority. + * + * @param base The LPI2C peripheral base address. + * @param handle Pointer to the LPI2C master driver handle. + * @retval #kStatus_Success A transaction was successfully aborted. + * @retval #kStatus_LPI2C_Idle There is not a non-blocking transaction currently in progress. + */ +void LPI2C_MasterTransferAbort(LPI2C_Type *base, lpi2c_master_handle_t *handle); + +/*@}*/ + +/*! @name IRQ handler */ +/*@{*/ + +/*! + * @brief Reusable routine to handle master interrupts. + * @note This function does not need to be called unless you are reimplementing the + * nonblocking API's interrupt handler routines to add special functionality. + * @param base The LPI2C peripheral base address. + * @param handle Pointer to the LPI2C master driver handle. + */ +void LPI2C_MasterTransferHandleIRQ(LPI2C_Type *base, lpi2c_master_handle_t *handle); + +/*@}*/ + +/*! @} */ + +/*! + * @addtogroup lpi2c_slave_driver + * @{ + */ + +/*! @name Slave initialization and deinitialization */ +/*@{*/ + +/*! + * @brief Provides a default configuration for the LPI2C slave peripheral. + * + * This function provides the following default configuration for the LPI2C slave peripheral: + * @code + * slaveConfig->enableSlave = true; + * slaveConfig->address0 = 0U; + * slaveConfig->address1 = 0U; + * slaveConfig->addressMatchMode = kLPI2C_MatchAddress0; + * slaveConfig->filterDozeEnable = true; + * slaveConfig->filterEnable = true; + * slaveConfig->enableGeneralCall = false; + * slaveConfig->sclStall.enableAck = false; + * slaveConfig->sclStall.enableTx = true; + * slaveConfig->sclStall.enableRx = true; + * slaveConfig->sclStall.enableAddress = true; + * slaveConfig->ignoreAck = false; + * slaveConfig->enableReceivedAddressRead = false; + * slaveConfig->sdaGlitchFilterWidth_ns = 0; + * slaveConfig->sclGlitchFilterWidth_ns = 0; + * slaveConfig->dataValidDelay_ns = 0; + * slaveConfig->clockHoldTime_ns = 0; + * @endcode + * + * After calling this function, override any settings to customize the configuration, + * prior to initializing the master driver with LPI2C_SlaveInit(). Be sure to override at least the @a + * address0 member of the configuration structure with the desired slave address. + * + * @param[out] slaveConfig User provided configuration structure that is set to default values. Refer to + * #lpi2c_slave_config_t. + */ +void LPI2C_SlaveGetDefaultConfig(lpi2c_slave_config_t *slaveConfig); + +/*! + * @brief Initializes the LPI2C slave peripheral. + * + * This function enables the peripheral clock and initializes the LPI2C slave peripheral as described by the user + * provided configuration. + * + * @param base The LPI2C peripheral base address. + * @param slaveConfig User provided peripheral configuration. Use LPI2C_SlaveGetDefaultConfig() to get a set of defaults + * that you can override. + * @param sourceClock_Hz Frequency in Hertz of the LPI2C functional clock. Used to calculate the filter widths, + * data valid delay, and clock hold time. + */ +void LPI2C_SlaveInit(LPI2C_Type *base, const lpi2c_slave_config_t *slaveConfig, uint32_t sourceClock_Hz); + +/*! + * @brief Deinitializes the LPI2C slave peripheral. + * + * This function disables the LPI2C slave peripheral and gates the clock. It also performs a software + * reset to restore the peripheral to reset conditions. + * + * @param base The LPI2C peripheral base address. + */ +void LPI2C_SlaveDeinit(LPI2C_Type *base); + +/*! + * @brief Performs a software reset of the LPI2C slave peripheral. + * + * @param base The LPI2C peripheral base address. + */ +static inline void LPI2C_SlaveReset(LPI2C_Type *base) +{ + base->SCR = LPI2C_SCR_RST_MASK; + base->SCR = 0; +} + +/*! + * @brief Enables or disables the LPI2C module as slave. + * + * @param base The LPI2C peripheral base address. + * @param enable Pass true to enable or false to disable the specified LPI2C as slave. + */ +static inline void LPI2C_SlaveEnable(LPI2C_Type *base, bool enable) +{ + base->SCR = (base->SCR & ~LPI2C_SCR_SEN_MASK) | LPI2C_SCR_SEN(enable); +} + +/*@}*/ + +/*! @name Slave status */ +/*@{*/ + +/*! + * @brief Gets the LPI2C slave status flags. + * + * A bit mask with the state of all LPI2C slave status flags is returned. For each flag, the corresponding bit + * in the return value is set if the flag is asserted. + * + * @param base The LPI2C peripheral base address. + * @return State of the status flags: + * - 1: related status flag is set. + * - 0: related status flag is not set. + * @see _lpi2c_slave_flags + */ +static inline uint32_t LPI2C_SlaveGetStatusFlags(LPI2C_Type *base) +{ + return base->SSR; +} + +/*! + * @brief Clears the LPI2C status flag state. + * + * The following status register flags can be cleared: + * - #kLPI2C_SlaveRepeatedStartDetectFlag + * - #kLPI2C_SlaveStopDetectFlag + * - #kLPI2C_SlaveBitErrFlag + * - #kLPI2C_SlaveFifoErrFlag + * + * Attempts to clear other flags has no effect. + * + * @param base The LPI2C peripheral base address. + * @param statusMask A bitmask of status flags that are to be cleared. The mask is composed of + * #_lpi2c_slave_flags enumerators OR'd together. You may pass the result of a previous call to + * LPI2C_SlaveGetStatusFlags(). + * @see _lpi2c_slave_flags. + */ +static inline void LPI2C_SlaveClearStatusFlags(LPI2C_Type *base, uint32_t statusMask) +{ + base->SSR = statusMask; +} + +/*@}*/ + +/*! @name Slave interrupts */ +/*@{*/ + +/*! + * @brief Enables the LPI2C slave interrupt requests. + * + * All flags except #kLPI2C_SlaveBusyFlag and #kLPI2C_SlaveBusBusyFlag can be enabled as + * interrupts. + * + * @param base The LPI2C peripheral base address. + * @param interruptMask Bit mask of interrupts to enable. See #_lpi2c_slave_flags for the set + * of constants that should be OR'd together to form the bit mask. + */ +static inline void LPI2C_SlaveEnableInterrupts(LPI2C_Type *base, uint32_t interruptMask) +{ + base->SIER |= interruptMask; +} + +/*! + * @brief Disables the LPI2C slave interrupt requests. + * + * All flags except #kLPI2C_SlaveBusyFlag and #kLPI2C_SlaveBusBusyFlag can be enabled as + * interrupts. + * + * @param base The LPI2C peripheral base address. + * @param interruptMask Bit mask of interrupts to disable. See #_lpi2c_slave_flags for the set + * of constants that should be OR'd together to form the bit mask. + */ +static inline void LPI2C_SlaveDisableInterrupts(LPI2C_Type *base, uint32_t interruptMask) +{ + base->SIER &= ~interruptMask; +} + +/*! + * @brief Returns the set of currently enabled LPI2C slave interrupt requests. + * @param base The LPI2C peripheral base address. + * @return A bitmask composed of #_lpi2c_slave_flags enumerators OR'd together to indicate the + * set of enabled interrupts. + */ +static inline uint32_t LPI2C_SlaveGetEnabledInterrupts(LPI2C_Type *base) +{ + return base->SIER; +} + +/*@}*/ + +/*! @name Slave DMA control */ +/*@{*/ + +/*! + * @brief Enables or disables the LPI2C slave peripheral DMA requests. + * + * @param base The LPI2C peripheral base address. + * @param enableAddressValid Enable flag for the address valid DMA request. Pass true for enable, false for disable. + * The address valid DMA request is shared with the receive data DMA request. + * @param enableRx Enable flag for the receive data DMA request. Pass true for enable, false for disable. + * @param enableTx Enable flag for the transmit data DMA request. Pass true for enable, false for disable. + */ +static inline void LPI2C_SlaveEnableDMA(LPI2C_Type *base, bool enableAddressValid, bool enableRx, bool enableTx) +{ + base->SDER = (base->SDER & ~(LPI2C_SDER_AVDE_MASK | LPI2C_SDER_RDDE_MASK | LPI2C_SDER_TDDE_MASK)) | + LPI2C_SDER_AVDE(enableAddressValid) | LPI2C_SDER_RDDE(enableRx) | LPI2C_SDER_TDDE(enableTx); +} + +/*@}*/ + +/*! @name Slave bus operations */ +/*@{*/ + +/*! + * @brief Returns whether the bus is idle. + * + * Requires the slave mode to be enabled. + * + * @param base The LPI2C peripheral base address. + * @retval true Bus is busy. + * @retval false Bus is idle. + */ +static inline bool LPI2C_SlaveGetBusIdleState(LPI2C_Type *base) +{ + return (base->SSR & LPI2C_SSR_BBF_MASK) >> LPI2C_SSR_BBF_SHIFT; +} + +/*! + * @brief Transmits either an ACK or NAK on the I2C bus in response to a byte from the master. + * + * Use this function to send an ACK or NAK when the #kLPI2C_SlaveTransmitAckFlag is asserted. This + * only happens if you enable the sclStall.enableAck field of the ::lpi2c_slave_config_t configuration + * structure used to initialize the slave peripheral. + * + * @param base The LPI2C peripheral base address. + * @param ackOrNack Pass true for an ACK or false for a NAK. + */ +static inline void LPI2C_SlaveTransmitAck(LPI2C_Type *base, bool ackOrNack) +{ + base->STAR = LPI2C_STAR_TXNACK(!ackOrNack); +} + +/*! + * @brief Returns the slave address sent by the I2C master. + * + * This function should only be called if the #kLPI2C_SlaveAddressValidFlag is asserted. + * + * @param base The LPI2C peripheral base address. + * @return The 8-bit address matched by the LPI2C slave. Bit 0 contains the R/w direction bit, and + * the 7-bit slave address is in the upper 7 bits. + */ +static inline uint32_t LPI2C_SlaveGetReceivedAddress(LPI2C_Type *base) +{ + return base->SASR & LPI2C_SASR_RADDR_MASK; +} + +/*! + * @brief Performs a polling send transfer on the I2C bus. + * + * @param base The LPI2C peripheral base address. + * @param txBuff The pointer to the data to be transferred. + * @param txSize The length in bytes of the data to be transferred. + * @param[out] actualTxSize + * @return Error or success status returned by API. + */ +status_t LPI2C_SlaveSend(LPI2C_Type *base, void *txBuff, size_t txSize, size_t *actualTxSize); + +/*! + * @brief Performs a polling receive transfer on the I2C bus. + * + * @param base The LPI2C peripheral base address. + * @param rxBuff The pointer to the data to be transferred. + * @param rxSize The length in bytes of the data to be transferred. + * @param[out] actualRxSize + * @return Error or success status returned by API. + */ +status_t LPI2C_SlaveReceive(LPI2C_Type *base, void *rxBuff, size_t rxSize, size_t *actualRxSize); + +/*@}*/ + +/*! @name Slave non-blocking */ +/*@{*/ + +/*! + * @brief Creates a new handle for the LPI2C slave non-blocking APIs. + * + * The creation of a handle is for use with the non-blocking APIs. Once a handle + * is created, there is not a corresponding destroy handle. If the user wants to + * terminate a transfer, the LPI2C_SlaveTransferAbort() API shall be called. + * + * @note The function also enables the NVIC IRQ for the input LPI2C. Need to notice + * that on some SoCs the LPI2C IRQ is connected to INTMUX, in this case user needs to + * enable the associated INTMUX IRQ in application. + + * @param base The LPI2C peripheral base address. + * @param[out] handle Pointer to the LPI2C slave driver handle. + * @param callback User provided pointer to the asynchronous callback function. + * @param userData User provided pointer to the application callback data. + */ +void LPI2C_SlaveTransferCreateHandle(LPI2C_Type *base, + lpi2c_slave_handle_t *handle, + lpi2c_slave_transfer_callback_t callback, + void *userData); + +/*! + * @brief Starts accepting slave transfers. + * + * Call this API after calling I2C_SlaveInit() and LPI2C_SlaveTransferCreateHandle() to start processing + * transactions driven by an I2C master. The slave monitors the I2C bus and pass events to the + * callback that was passed into the call to LPI2C_SlaveTransferCreateHandle(). The callback is always invoked + * from the interrupt context. + * + * The set of events received by the callback is customizable. To do so, set the @a eventMask parameter to + * the OR'd combination of #lpi2c_slave_transfer_event_t enumerators for the events you wish to receive. + * The #kLPI2C_SlaveTransmitEvent and #kLPI2C_SlaveReceiveEvent events are always enabled and do not need + * to be included in the mask. Alternatively, you can pass 0 to get a default set of only the transmit and + * receive events that are always enabled. In addition, the #kLPI2C_SlaveAllEvents constant is provided as + * a convenient way to enable all events. + * + * @param base The LPI2C peripheral base address. + * @param handle Pointer to #lpi2c_slave_handle_t structure which stores the transfer state. + * @param eventMask Bit mask formed by OR'ing together #lpi2c_slave_transfer_event_t enumerators to specify + * which events to send to the callback. Other accepted values are 0 to get a default set of + * only the transmit and receive events, and #kLPI2C_SlaveAllEvents to enable all events. + * + * @retval #kStatus_Success Slave transfers were successfully started. + * @retval #kStatus_LPI2C_Busy Slave transfers have already been started on this handle. + */ +status_t LPI2C_SlaveTransferNonBlocking(LPI2C_Type *base, lpi2c_slave_handle_t *handle, uint32_t eventMask); + +/*! + * @brief Gets the slave transfer status during a non-blocking transfer. + * @param base The LPI2C peripheral base address. + * @param handle Pointer to i2c_slave_handle_t structure. + * @param[out] count Pointer to a value to hold the number of bytes transferred. May be NULL if the count is not + * required. + * @retval #kStatus_Success + * @retval #kStatus_NoTransferInProgress + */ +status_t LPI2C_SlaveTransferGetCount(LPI2C_Type *base, lpi2c_slave_handle_t *handle, size_t *count); + +/*! + * @brief Aborts the slave non-blocking transfers. + * @note This API could be called at any time to stop slave for handling the bus events. + * @param base The LPI2C peripheral base address. + * @param handle Pointer to #lpi2c_slave_handle_t structure which stores the transfer state. + * @retval #kStatus_Success + * @retval #kStatus_LPI2C_Idle + */ +void LPI2C_SlaveTransferAbort(LPI2C_Type *base, lpi2c_slave_handle_t *handle); + +/*@}*/ + +/*! @name Slave IRQ handler */ +/*@{*/ + +/*! + * @brief Reusable routine to handle slave interrupts. + * @note This function does not need to be called unless you are reimplementing the + * non blocking API's interrupt handler routines to add special functionality. + * @param base The LPI2C peripheral base address. + * @param handle Pointer to #lpi2c_slave_handle_t structure which stores the transfer state. + */ +void LPI2C_SlaveTransferHandleIRQ(LPI2C_Type *base, lpi2c_slave_handle_t *handle); + +/*@}*/ + +/*! @} */ + +void I2cHardwareInit(void); +status_t I2cHardwareWrite(LPI2C_Type* base, uint16_t slave_addr, uint32_t sub_addr, uint8_t* buf, uint16_t size); +status_t I2cHardwareRead(LPI2C_Type* base, uint16_t slave_addr, uint32_t sub_addr, uint8_t* buf, uint16_t size); + + +#if defined(__cplusplus) +} +#endif + +#endif /* _FSL_LPI2C_H_ */ diff --git a/Ubiquitous/XiZi/board/xidatong/third_party_driver/include/fsl_lpuart.h b/Ubiquitous/XiZi/board/xidatong/third_party_driver/include/fsl_lpuart.h new file mode 100755 index 0000000..acc4713 --- /dev/null +++ b/Ubiquitous/XiZi/board/xidatong/third_party_driver/include/fsl_lpuart.h @@ -0,0 +1,864 @@ +/* + * Copyright (c) 2015-2016, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +/** + * @file fsl_lpuart.h + * @brief fsl uart drivers + * @version 2.0 + * @author AIIT XUOS Lab + * @date 2022-03-15 + */ + +#ifndef _FSL_LPUART_H_ +#define _FSL_LPUART_H_ + +#include "fsl_common.h" + +/*! + * @addtogroup lpuart_driver + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @name Driver version */ +/*@{*/ +/*! @brief LPUART driver version 2.2.6. */ +#define FSL_LPUART_DRIVER_VERSION (MAKE_VERSION(2, 2, 6)) +/*@}*/ + +/*! @brief Error codes for the LPUART driver. */ +enum _lpuart_status +{ + kStatus_LPUART_TxBusy = MAKE_STATUS(kStatusGroup_LPUART, 0), /*!< TX busy */ + kStatus_LPUART_RxBusy = MAKE_STATUS(kStatusGroup_LPUART, 1), /*!< RX busy */ + kStatus_LPUART_TxIdle = MAKE_STATUS(kStatusGroup_LPUART, 2), /*!< LPUART transmitter is idle. */ + kStatus_LPUART_RxIdle = MAKE_STATUS(kStatusGroup_LPUART, 3), /*!< LPUART receiver is idle. */ + kStatus_LPUART_TxWatermarkTooLarge = MAKE_STATUS(kStatusGroup_LPUART, 4), /*!< TX FIFO watermark too large */ + kStatus_LPUART_RxWatermarkTooLarge = MAKE_STATUS(kStatusGroup_LPUART, 5), /*!< RX FIFO watermark too large */ + kStatus_LPUART_FlagCannotClearManually = MAKE_STATUS(kStatusGroup_LPUART, 6), /*!< Some flag can't manually clear */ + kStatus_LPUART_Error = MAKE_STATUS(kStatusGroup_LPUART, 7), /*!< Error happens on LPUART. */ + kStatus_LPUART_RxRingBufferOverrun = + MAKE_STATUS(kStatusGroup_LPUART, 8), /*!< LPUART RX software ring buffer overrun. */ + kStatus_LPUART_RxHardwareOverrun = MAKE_STATUS(kStatusGroup_LPUART, 9), /*!< LPUART RX receiver overrun. */ + kStatus_LPUART_NoiseError = MAKE_STATUS(kStatusGroup_LPUART, 10), /*!< LPUART noise error. */ + kStatus_LPUART_FramingError = MAKE_STATUS(kStatusGroup_LPUART, 11), /*!< LPUART framing error. */ + kStatus_LPUART_ParityError = MAKE_STATUS(kStatusGroup_LPUART, 12), /*!< LPUART parity error. */ + kStatus_LPUART_BaudrateNotSupport = + MAKE_STATUS(kStatusGroup_LPUART, 13), /*!< Baudrate is not support in current clock source */ + kStatus_LPUART_IdleLineDetected = MAKE_STATUS(kStatusGroup_LPUART, 14), /*!< IDLE flag. */ +}; + +/*! @brief LPUART parity mode. */ +typedef enum _lpuart_parity_mode +{ + kLPUART_ParityDisabled = 0x0U, /*!< Parity disabled */ + kLPUART_ParityEven = 0x2U, /*!< Parity enabled, type even, bit setting: PE|PT = 10 */ + kLPUART_ParityOdd = 0x3U, /*!< Parity enabled, type odd, bit setting: PE|PT = 11 */ +} lpuart_parity_mode_t; + +/*! @brief LPUART data bits count. */ +typedef enum _lpuart_data_bits +{ + kLPUART_EightDataBits = 0x0U, /*!< Eight data bit */ +#if defined(FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT) && FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT + kLPUART_SevenDataBits = 0x1U, /*!< Seven data bit */ +#endif +} lpuart_data_bits_t; + +/*! @brief LPUART stop bit count. */ +typedef enum _lpuart_stop_bit_count +{ + kLPUART_OneStopBit = 0U, /*!< One stop bit */ + kLPUART_TwoStopBit = 1U, /*!< Two stop bits */ +} lpuart_stop_bit_count_t; + +#if defined(FSL_FEATURE_LPUART_HAS_MODEM_SUPPORT) && FSL_FEATURE_LPUART_HAS_MODEM_SUPPORT +/*! @brief LPUART transmit CTS source. */ +typedef enum _lpuart_transmit_cts_source +{ + kLPUART_CtsSourcePin = 0U, /*!< CTS resource is the LPUART_CTS pin. */ + kLPUART_CtsSourceMatchResult = 1U, /*!< CTS resource is the match result. */ +} lpuart_transmit_cts_source_t; + +/*! @brief LPUART transmit CTS configure. */ +typedef enum _lpuart_transmit_cts_config +{ + kLPUART_CtsSampleAtStart = 0U, /*!< CTS input is sampled at the start of each character. */ + kLPUART_CtsSampleAtIdle = 1U, /*!< CTS input is sampled when the transmitter is idle */ +} lpuart_transmit_cts_config_t; +#endif + +/*! @brief LPUART idle flag type defines when the receiver starts counting. */ +typedef enum _lpuart_idle_type_select +{ + kLPUART_IdleTypeStartBit = 0U, /*!< Start counting after a valid start bit. */ + kLPUART_IdleTypeStopBit = 1U, /*!< Start counting after a stop bit. */ +} lpuart_idle_type_select_t; + +/*! @brief LPUART idle detected configuration. + * This structure defines the number of idle characters that must be received before + * the IDLE flag is set. + */ +typedef enum _lpuart_idle_config +{ + kLPUART_IdleCharacter1 = 0U, /*!< the number of idle characters. */ + kLPUART_IdleCharacter2 = 1U, /*!< the number of idle characters. */ + kLPUART_IdleCharacter4 = 2U, /*!< the number of idle characters. */ + kLPUART_IdleCharacter8 = 3U, /*!< the number of idle characters. */ + kLPUART_IdleCharacter16 = 4U, /*!< the number of idle characters. */ + kLPUART_IdleCharacter32 = 5U, /*!< the number of idle characters. */ + kLPUART_IdleCharacter64 = 6U, /*!< the number of idle characters. */ + kLPUART_IdleCharacter128 = 7U, /*!< the number of idle characters. */ +} lpuart_idle_config_t; + +/*! + * @brief LPUART interrupt configuration structure, default settings all disabled. + * + * This structure contains the settings for all LPUART interrupt configurations. + */ +enum _lpuart_interrupt_enable +{ +#if defined(FSL_FEATURE_LPUART_HAS_LIN_BREAK_DETECT) && FSL_FEATURE_LPUART_HAS_LIN_BREAK_DETECT + kLPUART_LinBreakInterruptEnable = (LPUART_BAUD_LBKDIE_MASK >> 8), /*!< LIN break detect. */ +#endif + kLPUART_RxActiveEdgeInterruptEnable = (LPUART_BAUD_RXEDGIE_MASK >> 8), /*!< Receive Active Edge. */ + kLPUART_TxDataRegEmptyInterruptEnable = (LPUART_CTRL_TIE_MASK), /*!< Transmit data register empty. */ + kLPUART_TransmissionCompleteInterruptEnable = (LPUART_CTRL_TCIE_MASK), /*!< Transmission complete. */ + kLPUART_RxDataRegFullInterruptEnable = (LPUART_CTRL_RIE_MASK), /*!< Receiver data register full. */ + kLPUART_IdleLineInterruptEnable = (LPUART_CTRL_ILIE_MASK), /*!< Idle line. */ + kLPUART_RxOverrunInterruptEnable = (LPUART_CTRL_ORIE_MASK), /*!< Receiver Overrun. */ + kLPUART_NoiseErrorInterruptEnable = (LPUART_CTRL_NEIE_MASK), /*!< Noise error flag. */ + kLPUART_FramingErrorInterruptEnable = (LPUART_CTRL_FEIE_MASK), /*!< Framing error flag. */ + kLPUART_ParityErrorInterruptEnable = (LPUART_CTRL_PEIE_MASK), /*!< Parity error flag. */ +#if defined(FSL_FEATURE_LPUART_HAS_FIFO) && FSL_FEATURE_LPUART_HAS_FIFO + kLPUART_TxFifoOverflowInterruptEnable = (LPUART_FIFO_TXOFE_MASK >> 8), /*!< Transmit FIFO Overflow. */ + kLPUART_RxFifoUnderflowInterruptEnable = (LPUART_FIFO_RXUFE_MASK >> 8), /*!< Receive FIFO Underflow. */ +#endif +}; + +/*! + * @brief LPUART status flags. + * + * This provides constants for the LPUART status flags for use in the LPUART functions. + */ +enum _lpuart_flags +{ + kLPUART_TxDataRegEmptyFlag = + (LPUART_STAT_TDRE_MASK), /*!< Transmit data register empty flag, sets when transmit buffer is empty */ + kLPUART_TransmissionCompleteFlag = + (LPUART_STAT_TC_MASK), /*!< Transmission complete flag, sets when transmission activity complete */ + kLPUART_RxDataRegFullFlag = + (LPUART_STAT_RDRF_MASK), /*!< Receive data register full flag, sets when the receive data buffer is full */ + kLPUART_IdleLineFlag = (LPUART_STAT_IDLE_MASK), /*!< Idle line detect flag, sets when idle line detected */ + kLPUART_RxOverrunFlag = (LPUART_STAT_OR_MASK), /*!< Receive Overrun, sets when new data is received before data is + read from receive register */ + kLPUART_NoiseErrorFlag = (LPUART_STAT_NF_MASK), /*!< Receive takes 3 samples of each received bit. If any of these + samples differ, noise flag sets */ + kLPUART_FramingErrorFlag = + (LPUART_STAT_FE_MASK), /*!< Frame error flag, sets if logic 0 was detected where stop bit expected */ + kLPUART_ParityErrorFlag = (LPUART_STAT_PF_MASK), /*!< If parity enabled, sets upon parity error detection */ +#if defined(FSL_FEATURE_LPUART_HAS_LIN_BREAK_DETECT) && FSL_FEATURE_LPUART_HAS_LIN_BREAK_DETECT + kLPUART_LinBreakFlag = + (int)(LPUART_STAT_LBKDIF_MASK), /*!< LIN break detect interrupt flag, sets when LIN break char + detected and LIN circuit enabled */ +#endif + kLPUART_RxActiveEdgeFlag = + (LPUART_STAT_RXEDGIF_MASK), /*!< Receive pin active edge interrupt flag, sets when active edge detected */ + kLPUART_RxActiveFlag = + (LPUART_STAT_RAF_MASK), /*!< Receiver Active Flag (RAF), sets at beginning of valid start bit */ +#if defined(FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING) && FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING + kLPUART_DataMatch1Flag = LPUART_STAT_MA1F_MASK, /*!< The next character to be read from LPUART_DATA matches MA1*/ + kLPUART_DataMatch2Flag = LPUART_STAT_MA2F_MASK, /*!< The next character to be read from LPUART_DATA matches MA2*/ +#endif +#if defined(FSL_FEATURE_LPUART_HAS_EXTENDED_DATA_REGISTER_FLAGS) && FSL_FEATURE_LPUART_HAS_EXTENDED_DATA_REGISTER_FLAGS + kLPUART_NoiseErrorInRxDataRegFlag = + (LPUART_DATA_NOISY_MASK >> 10), /*!< NOISY bit, sets if noise detected in current data word */ + kLPUART_ParityErrorInRxDataRegFlag = + (LPUART_DATA_PARITYE_MASK >> 10), /*!< PARITYE bit, sets if noise detected in current data word */ +#endif +#if defined(FSL_FEATURE_LPUART_HAS_FIFO) && FSL_FEATURE_LPUART_HAS_FIFO + kLPUART_TxFifoEmptyFlag = (LPUART_FIFO_TXEMPT_MASK >> 16), /*!< TXEMPT bit, sets if transmit buffer is empty */ + kLPUART_RxFifoEmptyFlag = (LPUART_FIFO_RXEMPT_MASK >> 16), /*!< RXEMPT bit, sets if receive buffer is empty */ + kLPUART_TxFifoOverflowFlag = + (LPUART_FIFO_TXOF_MASK >> 16), /*!< TXOF bit, sets if transmit buffer overflow occurred */ + kLPUART_RxFifoUnderflowFlag = + (LPUART_FIFO_RXUF_MASK >> 16), /*!< RXUF bit, sets if receive buffer underflow occurred */ +#endif +}; + +/*! @brief LPUART configuration structure. */ +typedef struct _lpuart_config +{ + uint32_t baudRate_Bps; /*!< LPUART baud rate */ + lpuart_parity_mode_t parityMode; /*!< Parity mode, disabled (default), even, odd */ + lpuart_data_bits_t dataBitsCount; /*!< Data bits count, eight (default), seven */ + bool isMsb; /*!< Data bits order, LSB (default), MSB */ +#if defined(FSL_FEATURE_LPUART_HAS_STOP_BIT_CONFIG_SUPPORT) && FSL_FEATURE_LPUART_HAS_STOP_BIT_CONFIG_SUPPORT + lpuart_stop_bit_count_t stopBitCount; /*!< Number of stop bits, 1 stop bit (default) or 2 stop bits */ +#endif +#if defined(FSL_FEATURE_LPUART_HAS_FIFO) && FSL_FEATURE_LPUART_HAS_FIFO + uint8_t txFifoWatermark; /*!< TX FIFO watermark */ + uint8_t rxFifoWatermark; /*!< RX FIFO watermark */ +#endif +#if defined(FSL_FEATURE_LPUART_HAS_MODEM_SUPPORT) && FSL_FEATURE_LPUART_HAS_MODEM_SUPPORT + bool enableRxRTS; /*!< RX RTS enable */ + bool enableTxCTS; /*!< TX CTS enable */ + lpuart_transmit_cts_source_t txCtsSource; /*!< TX CTS source */ + lpuart_transmit_cts_config_t txCtsConfig; /*!< TX CTS configure */ +#endif + lpuart_idle_type_select_t rxIdleType; /*!< RX IDLE type. */ + lpuart_idle_config_t rxIdleConfig; /*!< RX IDLE configuration. */ + bool enableTx; /*!< Enable TX */ + bool enableRx; /*!< Enable RX */ +} lpuart_config_t; + +/*! @brief LPUART transfer structure. */ +typedef struct _lpuart_transfer +{ + uint8_t *data; /*!< The buffer of data to be transfer.*/ + size_t dataSize; /*!< The byte count to be transfer. */ +} lpuart_transfer_t; + +/* Forward declaration of the handle typedef. */ +typedef struct _lpuart_handle lpuart_handle_t; + +/*! @brief LPUART transfer callback function. */ +typedef void (*lpuart_transfer_callback_t)(LPUART_Type *base, lpuart_handle_t *handle, status_t status, void *userData); + +/*! @brief LPUART handle structure. */ +struct _lpuart_handle +{ + uint8_t *volatile txData; /*!< Address of remaining data to send. */ + volatile size_t txDataSize; /*!< Size of the remaining data to send. */ + size_t txDataSizeAll; /*!< Size of the data to send out. */ + uint8_t *volatile rxData; /*!< Address of remaining data to receive. */ + volatile size_t rxDataSize; /*!< Size of the remaining data to receive. */ + size_t rxDataSizeAll; /*!< Size of the data to receive. */ + + uint8_t *rxRingBuffer; /*!< Start address of the receiver ring buffer. */ + size_t rxRingBufferSize; /*!< Size of the ring buffer. */ + volatile uint16_t rxRingBufferHead; /*!< Index for the driver to store received data into ring buffer. */ + volatile uint16_t rxRingBufferTail; /*!< Index for the user to get data from the ring buffer. */ + + lpuart_transfer_callback_t callback; /*!< Callback function. */ + void *userData; /*!< LPUART callback function parameter.*/ + + volatile uint8_t txState; /*!< TX transfer state. */ + volatile uint8_t rxState; /*!< RX transfer state. */ + +#if defined(FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT) && FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT + bool isSevenDataBits; /*!< Seven data bits flag. */ +#endif +}; + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif /* _cplusplus */ + +#if defined(FSL_FEATURE_LPUART_HAS_GLOBAL) && FSL_FEATURE_LPUART_HAS_GLOBAL + +/*! + * @name Software Reset + * @{ + */ + +/*! + * @brief Resets the LPUART using software. + * + * This function resets all internal logic and registers except the Global Register. + * Remains set until cleared by software. + * + * @param base LPUART peripheral base address. + */ +static inline void LPUART_SoftwareReset(LPUART_Type *base) +{ + base->GLOBAL |= LPUART_GLOBAL_RST_MASK; + base->GLOBAL &= ~LPUART_GLOBAL_RST_MASK; +} +/* @} */ +#endif /*FSL_FEATURE_LPUART_HAS_GLOBAL*/ + +/*! + * @name Initialization and deinitialization + * @{ + */ + +/*! + * @brief Initializes an LPUART instance with the user configuration structure and the peripheral clock. + * + * This function configures the LPUART module with user-defined settings. Call the LPUART_GetDefaultConfig() function + * to configure the configuration structure and get the default configuration. + * The example below shows how to use this API to configure the LPUART. + * @code + * lpuart_config_t lpuartConfig; + * lpuartConfig.baudRate_Bps = 115200U; + * lpuartConfig.parityMode = kLPUART_ParityDisabled; + * lpuartConfig.dataBitsCount = kLPUART_EightDataBits; + * lpuartConfig.isMsb = false; + * lpuartConfig.stopBitCount = kLPUART_OneStopBit; + * lpuartConfig.txFifoWatermark = 0; + * lpuartConfig.rxFifoWatermark = 1; + * LPUART_Init(LPUART1, &lpuartConfig, 20000000U); + * @endcode + * + * @param base LPUART peripheral base address. + * @param config Pointer to a user-defined configuration structure. + * @param srcClock_Hz LPUART clock source frequency in HZ. + * @retval kStatus_LPUART_BaudrateNotSupport Baudrate is not support in current clock source. + * @retval kStatus_Success LPUART initialize succeed + */ +status_t LPUART_Init(LPUART_Type *base, const lpuart_config_t *config, uint32_t srcClock_Hz); + +/*! + * @brief Deinitializes a LPUART instance. + * + * This function waits for transmit to complete, disables TX and RX, and disables the LPUART clock. + * + * @param base LPUART peripheral base address. + */ +void LPUART_Deinit(LPUART_Type *base); + +/*! + * @brief Gets the default configuration structure. + * + * This function initializes the LPUART configuration structure to a default value. The default + * values are: + * lpuartConfig->baudRate_Bps = 115200U; + * lpuartConfig->parityMode = kLPUART_ParityDisabled; + * lpuartConfig->dataBitsCount = kLPUART_EightDataBits; + * lpuartConfig->isMsb = false; + * lpuartConfig->stopBitCount = kLPUART_OneStopBit; + * lpuartConfig->txFifoWatermark = 0; + * lpuartConfig->rxFifoWatermark = 1; + * lpuartConfig->rxIdleType = kLPUART_IdleTypeStartBit; + * lpuartConfig->rxIdleConfig = kLPUART_IdleCharacter1; + * lpuartConfig->enableTx = false; + * lpuartConfig->enableRx = false; + * + * @param config Pointer to a configuration structure. + */ +void LPUART_GetDefaultConfig(lpuart_config_t *config); + +/*! + * @brief Sets the LPUART instance baudrate. + * + * This function configures the LPUART module baudrate. This function is used to update + * the LPUART module baudrate after the LPUART module is initialized by the LPUART_Init. + * @code + * LPUART_SetBaudRate(LPUART1, 115200U, 20000000U); + * @endcode + * + * @param base LPUART peripheral base address. + * @param baudRate_Bps LPUART baudrate to be set. + * @param srcClock_Hz LPUART clock source frequency in HZ. + * @retval kStatus_LPUART_BaudrateNotSupport Baudrate is not supported in the current clock source. + * @retval kStatus_Success Set baudrate succeeded. + */ +status_t LPUART_SetBaudRate(LPUART_Type *base, uint32_t baudRate_Bps, uint32_t srcClock_Hz); + +/* @} */ + +/*! + * @name Status + * @{ + */ + +/*! + * @brief Gets LPUART status flags. + * + * This function gets all LPUART status flags. The flags are returned as the logical + * OR value of the enumerators @ref _lpuart_flags. To check for a specific status, + * compare the return value with enumerators in the @ref _lpuart_flags. + * For example, to check whether the TX is empty: + * @code + * if (kLPUART_TxDataRegEmptyFlag & LPUART_GetStatusFlags(LPUART1)) + * { + * ... + * } + * @endcode + * + * @param base LPUART peripheral base address. + * @return LPUART status flags which are ORed by the enumerators in the _lpuart_flags. + */ +uint32_t LPUART_GetStatusFlags(LPUART_Type *base); + +/*! + * @brief Clears status flags with a provided mask. + * + * This function clears LPUART status flags with a provided mask. Automatically cleared flags + * can't be cleared by this function. + * Flags that can only cleared or set by hardware are: + * kLPUART_TxDataRegEmptyFlag, kLPUART_TransmissionCompleteFlag, kLPUART_RxDataRegFullFlag, + * kLPUART_RxActiveFlag, kLPUART_NoiseErrorInRxDataRegFlag, kLPUART_ParityErrorInRxDataRegFlag, + * kLPUART_TxFifoEmptyFlag,kLPUART_RxFifoEmptyFlag + * Note: This API should be called when the Tx/Rx is idle, otherwise it takes no effects. + * + * @param base LPUART peripheral base address. + * @param mask the status flags to be cleared. The user can use the enumerators in the + * _lpuart_status_flag_t to do the OR operation and get the mask. + * @return 0 succeed, others failed. + * @retval kStatus_LPUART_FlagCannotClearManually The flag can't be cleared by this function but + * it is cleared automatically by hardware. + * @retval kStatus_Success Status in the mask are cleared. + */ +status_t LPUART_ClearStatusFlags(LPUART_Type *base, uint32_t mask); + +/* @} */ + +/*! + * @name Interrupts + * @{ + */ + +/*! + * @brief Enables LPUART interrupts according to a provided mask. + * + * This function enables the LPUART interrupts according to a provided mask. The mask + * is a logical OR of enumeration members. See the @ref _lpuart_interrupt_enable. + * This examples shows how to enable TX empty interrupt and RX full interrupt: + * @code + * LPUART_EnableInterrupts(LPUART1,kLPUART_TxDataRegEmptyInterruptEnable | kLPUART_RxDataRegFullInterruptEnable); + * @endcode + * + * @param base LPUART peripheral base address. + * @param mask The interrupts to enable. Logical OR of @ref _uart_interrupt_enable. + */ +void LPUART_EnableInterrupts(LPUART_Type *base, uint32_t mask); + +/*! + * @brief Disables LPUART interrupts according to a provided mask. + * + * This function disables the LPUART interrupts according to a provided mask. The mask + * is a logical OR of enumeration members. See @ref _lpuart_interrupt_enable. + * This example shows how to disable the TX empty interrupt and RX full interrupt: + * @code + * LPUART_DisableInterrupts(LPUART1,kLPUART_TxDataRegEmptyInterruptEnable | kLPUART_RxDataRegFullInterruptEnable); + * @endcode + * + * @param base LPUART peripheral base address. + * @param mask The interrupts to disable. Logical OR of @ref _lpuart_interrupt_enable. + */ +void LPUART_DisableInterrupts(LPUART_Type *base, uint32_t mask); + +/*! + * @brief Gets enabled LPUART interrupts. + * + * This function gets the enabled LPUART interrupts. The enabled interrupts are returned + * as the logical OR value of the enumerators @ref _lpuart_interrupt_enable. To check + * a specific interrupt enable status, compare the return value with enumerators + * in @ref _lpuart_interrupt_enable. + * For example, to check whether the TX empty interrupt is enabled: + * @code + * uint32_t enabledInterrupts = LPUART_GetEnabledInterrupts(LPUART1); + * + * if (kLPUART_TxDataRegEmptyInterruptEnable & enabledInterrupts) + * { + * ... + * } + * @endcode + * + * @param base LPUART peripheral base address. + * @return LPUART interrupt flags which are logical OR of the enumerators in @ref _lpuart_interrupt_enable. + */ +uint32_t LPUART_GetEnabledInterrupts(LPUART_Type *base); + +#if defined(FSL_FEATURE_LPUART_HAS_DMA_ENABLE) && FSL_FEATURE_LPUART_HAS_DMA_ENABLE +/*! + * @brief Gets the LPUART data register address. + * + * This function returns the LPUART data register address, which is mainly used by the DMA/eDMA. + * + * @param base LPUART peripheral base address. + * @return LPUART data register addresses which are used both by the transmitter and receiver. + */ +static inline uint32_t LPUART_GetDataRegisterAddress(LPUART_Type *base) +{ + return (uint32_t) & (base->DATA); +} + +/*! + * @brief Enables or disables the LPUART transmitter DMA request. + * + * This function enables or disables the transmit data register empty flag, STAT[TDRE], to generate DMA requests. + * + * @param base LPUART peripheral base address. + * @param enable True to enable, false to disable. + */ +static inline void LPUART_EnableTxDMA(LPUART_Type *base, bool enable) +{ + if (enable) + { + base->BAUD |= LPUART_BAUD_TDMAE_MASK; + } + else + { + base->BAUD &= ~LPUART_BAUD_TDMAE_MASK; + } +} + +/*! + * @brief Enables or disables the LPUART receiver DMA. + * + * This function enables or disables the receiver data register full flag, STAT[RDRF], to generate DMA requests. + * + * @param base LPUART peripheral base address. + * @param enable True to enable, false to disable. + */ +static inline void LPUART_EnableRxDMA(LPUART_Type *base, bool enable) +{ + if (enable) + { + base->BAUD |= LPUART_BAUD_RDMAE_MASK; + } + else + { + base->BAUD &= ~LPUART_BAUD_RDMAE_MASK; + } +} + +/* @} */ +#endif /* FSL_FEATURE_LPUART_HAS_DMA_ENABLE */ + +/*! + * @name Bus Operations + * @{ + */ + +/*! + * @brief Get the LPUART instance from peripheral base address. + * + * @param base LPUART peripheral base address. + * @return LPUART instance. + */ +uint32_t LPUART_GetInstance(LPUART_Type *base); + +/*! + * @brief Enables or disables the LPUART transmitter. + * + * This function enables or disables the LPUART transmitter. + * + * @param base LPUART peripheral base address. + * @param enable True to enable, false to disable. + */ +static inline void LPUART_EnableTx(LPUART_Type *base, bool enable) +{ + if (enable) + { + base->CTRL |= LPUART_CTRL_TE_MASK; + } + else + { + base->CTRL &= ~LPUART_CTRL_TE_MASK; + } +} + +/*! + * @brief Enables or disables the LPUART receiver. + * + * This function enables or disables the LPUART receiver. + * + * @param base LPUART peripheral base address. + * @param enable True to enable, false to disable. + */ +static inline void LPUART_EnableRx(LPUART_Type *base, bool enable) +{ + if (enable) + { + base->CTRL |= LPUART_CTRL_RE_MASK; + } + else + { + base->CTRL &= ~LPUART_CTRL_RE_MASK; + } +} + +/*! + * @brief Writes to the transmitter register. + * + * This function writes data to the transmitter register directly. The upper layer must + * ensure that the TX register is empty or that the TX FIFO has room before calling this function. + * + * @param base LPUART peripheral base address. + * @param data Data write to the TX register. + */ +static inline void LPUART_WriteByte(LPUART_Type *base, uint8_t data) +{ + base->DATA = data; +} + +/*! + * @brief Reads the receiver register. + * + * This function reads data from the receiver register directly. The upper layer must + * ensure that the receiver register is full or that the RX FIFO has data before calling this function. + * + * @param base LPUART peripheral base address. + * @return Data read from data register. + */ +static inline uint8_t LPUART_ReadByte(LPUART_Type *base) +{ +#if defined(FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT) && FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT + uint32_t ctrl = base->CTRL; + bool isSevenDataBits = + ((ctrl & LPUART_CTRL_M7_MASK) || + ((!(ctrl & LPUART_CTRL_M7_MASK)) && (!(ctrl & LPUART_CTRL_M_MASK)) && (ctrl & LPUART_CTRL_PE_MASK))); + + if (isSevenDataBits) + { + return (base->DATA & 0x7F); + } + else + { + return base->DATA; + } +#else + return base->DATA; +#endif +} + +/*! + * @brief Writes to the transmitter register using a blocking method. + * + * This function polls the transmitter register, waits for the register to be empty or for TX FIFO to have + * room, and writes data to the transmitter buffer. + * + * @note This function does not check whether all data has been sent out to the bus. + * Before disabling the transmitter, check the kLPUART_TransmissionCompleteFlag to ensure that the transmit is + * finished. + * + * @param base LPUART peripheral base address. + * @param data Start address of the data to write. + * @param length Size of the data to write. + */ +void LPUART_WriteBlocking(LPUART_Type *base, const uint8_t *data, size_t length); + +/*! +* @brief Reads the receiver data register using a blocking method. + * + * This function polls the receiver register, waits for the receiver register full or receiver FIFO + * has data, and reads data from the TX register. + * + * @param base LPUART peripheral base address. + * @param data Start address of the buffer to store the received data. + * @param length Size of the buffer. + * @retval kStatus_LPUART_RxHardwareOverrun Receiver overrun happened while receiving data. + * @retval kStatus_LPUART_NoiseError Noise error happened while receiving data. + * @retval kStatus_LPUART_FramingError Framing error happened while receiving data. + * @retval kStatus_LPUART_ParityError Parity error happened while receiving data. + * @retval kStatus_Success Successfully received all data. + */ +status_t LPUART_ReadBlocking(LPUART_Type *base, uint8_t *data, size_t length); + +/* @} */ + +/*! + * @name Transactional + * @{ + */ + +/*! + * @brief Initializes the LPUART handle. + * + * This function initializes the LPUART handle, which can be used for other LPUART + * transactional APIs. Usually, for a specified LPUART instance, + * call this API once to get the initialized handle. + * + * The LPUART driver supports the "background" receiving, which means that user can set up + * an RX ring buffer optionally. Data received is stored into the ring buffer even when the + * user doesn't call the LPUART_TransferReceiveNonBlocking() API. If there is already data received + * in the ring buffer, the user can get the received data from the ring buffer directly. + * The ring buffer is disabled if passing NULL as @p ringBuffer. + * + * @param base LPUART peripheral base address. + * @param handle LPUART handle pointer. + * @param callback Callback function. + * @param userData User data. + */ +void LPUART_TransferCreateHandle(LPUART_Type *base, + lpuart_handle_t *handle, + lpuart_transfer_callback_t callback, + void *userData); +/*! + * @brief Transmits a buffer of data using the interrupt method. + * + * This function send data using an interrupt method. This is a non-blocking function, which + * returns directly without waiting for all data written to the transmitter register. When + * all data is written to the TX register in the ISR, the LPUART driver calls the callback + * function and passes the @ref kStatus_LPUART_TxIdle as status parameter. + * + * @note The kStatus_LPUART_TxIdle is passed to the upper layer when all data are written + * to the TX register. However, there is no check to ensure that all the data sent out. Before disabling the TX, + * check the kLPUART_TransmissionCompleteFlag to ensure that the transmit is finished. + * + * @param base LPUART peripheral base address. + * @param handle LPUART handle pointer. + * @param xfer LPUART transfer structure, see #lpuart_transfer_t. + * @retval kStatus_Success Successfully start the data transmission. + * @retval kStatus_LPUART_TxBusy Previous transmission still not finished, data not all written to the TX register. + * @retval kStatus_InvalidArgument Invalid argument. + */ +status_t LPUART_TransferSendNonBlocking(LPUART_Type *base, lpuart_handle_t *handle, lpuart_transfer_t *xfer); + +/*! + * @brief Sets up the RX ring buffer. + * + * This function sets up the RX ring buffer to a specific UART handle. + * + * When the RX ring buffer is used, data received is stored into the ring buffer even when + * the user doesn't call the UART_TransferReceiveNonBlocking() API. If there is already data received + * in the ring buffer, the user can get the received data from the ring buffer directly. + * + * @note When using RX ring buffer, one byte is reserved for internal use. In other + * words, if @p ringBufferSize is 32, then only 31 bytes are used for saving data. + * + * @param base LPUART peripheral base address. + * @param handle LPUART handle pointer. + * @param ringBuffer Start address of ring buffer for background receiving. Pass NULL to disable the ring buffer. + * @param ringBufferSize size of the ring buffer. + */ +void LPUART_TransferStartRingBuffer(LPUART_Type *base, + lpuart_handle_t *handle, + uint8_t *ringBuffer, + size_t ringBufferSize); + +/*! + * @brief Aborts the background transfer and uninstalls the ring buffer. + * + * This function aborts the background transfer and uninstalls the ring buffer. + * + * @param base LPUART peripheral base address. + * @param handle LPUART handle pointer. + */ +void LPUART_TransferStopRingBuffer(LPUART_Type *base, lpuart_handle_t *handle); + +/*! + * @brief Get the length of received data in RX ring buffer. + * + * @param handle LPUART handle pointer. + * @return Length of received data in RX ring buffer. + */ +size_t LPUART_TransferGetRxRingBufferLength(LPUART_Type *base, lpuart_handle_t *handle); + +/*! + * @brief Aborts the interrupt-driven data transmit. + * + * This function aborts the interrupt driven data sending. The user can get the remainBtyes to find out + * how many bytes are not sent out. + * + * @param base LPUART peripheral base address. + * @param handle LPUART handle pointer. + */ +void LPUART_TransferAbortSend(LPUART_Type *base, lpuart_handle_t *handle); + +/*! + * @brief Gets the number of bytes that have been written to the LPUART transmitter register. + * + * This function gets the number of bytes that have been written to LPUART TX + * register by an interrupt method. + * + * @param base LPUART peripheral base address. + * @param handle LPUART handle pointer. + * @param count Send bytes count. + * @retval kStatus_NoTransferInProgress No send in progress. + * @retval kStatus_InvalidArgument Parameter is invalid. + * @retval kStatus_Success Get successfully through the parameter \p count; + */ +status_t LPUART_TransferGetSendCount(LPUART_Type *base, lpuart_handle_t *handle, uint32_t *count); + +/*! + * @brief Receives a buffer of data using the interrupt method. + * + * This function receives data using an interrupt method. This is a non-blocking function + * which returns without waiting to ensure that all data are received. + * If the RX ring buffer is used and not empty, the data in the ring buffer is copied and + * the parameter @p receivedBytes shows how many bytes are copied from the ring buffer. + * After copying, if the data in the ring buffer is not enough for read, the receive + * request is saved by the LPUART driver. When the new data arrives, the receive request + * is serviced first. When all data is received, the LPUART driver notifies the upper layer + * through a callback function and passes a status parameter @ref kStatus_UART_RxIdle. + * For example, the upper layer needs 10 bytes but there are only 5 bytes in ring buffer. + * The 5 bytes are copied to xfer->data, which returns with the + * parameter @p receivedBytes set to 5. For the remaining 5 bytes, the newly arrived data is + * saved from xfer->data[5]. When 5 bytes are received, the LPUART driver notifies the upper layer. + * If the RX ring buffer is not enabled, this function enables the RX and RX interrupt + * to receive data to xfer->data. When all data is received, the upper layer is notified. + * + * @param base LPUART peripheral base address. + * @param handle LPUART handle pointer. + * @param xfer LPUART transfer structure, see #uart_transfer_t. + * @param receivedBytes Bytes received from the ring buffer directly. + * @retval kStatus_Success Successfully queue the transfer into the transmit queue. + * @retval kStatus_LPUART_RxBusy Previous receive request is not finished. + * @retval kStatus_InvalidArgument Invalid argument. + */ +status_t LPUART_TransferReceiveNonBlocking(LPUART_Type *base, + lpuart_handle_t *handle, + lpuart_transfer_t *xfer, + size_t *receivedBytes); + +/*! + * @brief Aborts the interrupt-driven data receiving. + * + * This function aborts the interrupt-driven data receiving. The user can get the remainBytes to find out + * how many bytes not received yet. + * + * @param base LPUART peripheral base address. + * @param handle LPUART handle pointer. + */ +void LPUART_TransferAbortReceive(LPUART_Type *base, lpuart_handle_t *handle); + +/*! + * @brief Gets the number of bytes that have been received. + * + * This function gets the number of bytes that have been received. + * + * @param base LPUART peripheral base address. + * @param handle LPUART handle pointer. + * @param count Receive bytes count. + * @retval kStatus_NoTransferInProgress No receive in progress. + * @retval kStatus_InvalidArgument Parameter is invalid. + * @retval kStatus_Success Get successfully through the parameter \p count; + */ +status_t LPUART_TransferGetReceiveCount(LPUART_Type *base, lpuart_handle_t *handle, uint32_t *count); + +/*! + * @brief LPUART IRQ handle function. + * + * This function handles the LPUART transmit and receive IRQ request. + * + * @param base LPUART peripheral base address. + * @param handle LPUART handle pointer. + */ +void LPUART_TransferHandleIRQ(LPUART_Type *base, lpuart_handle_t *handle); + +/*! + * @brief LPUART Error IRQ handle function. + * + * This function handles the LPUART error IRQ request. + * + * @param base LPUART peripheral base address. + * @param handle LPUART handle pointer. + */ +void LPUART_TransferHandleErrorIRQ(LPUART_Type *base, lpuart_handle_t *handle); + +/* @} */ + +#if defined(__cplusplus) +} +#endif + +/*! @}*/ + +#endif /* _FSL_LPUART_H_ */ diff --git a/Ubiquitous/XiZi/board/xidatong/third_party_driver/include/fsl_semc.h b/Ubiquitous/XiZi/board/xidatong/third_party_driver/include/fsl_semc.h new file mode 100644 index 0000000..75704ea --- /dev/null +++ b/Ubiquitous/XiZi/board/xidatong/third_party_driver/include/fsl_semc.h @@ -0,0 +1,830 @@ +/* + * Copyright 2017-2018 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef _FSL_SEMC_H_ +#define _FSL_SEMC_H_ + +#include "fsl_common.h" + +/*! + * @addtogroup semc + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @name Driver version */ +/*@{*/ +/*! @brief SEMC driver version 2.0.4. */ +#define FSL_SEMC_DRIVER_VERSION (MAKE_VERSION(2, 0, 4)) +/*@}*/ + +/*! @brief SEMC status. */ +enum _semc_status +{ + kStatus_SEMC_InvalidDeviceType = MAKE_STATUS(kStatusGroup_SEMC, 0), + kStatus_SEMC_IpCommandExecutionError = MAKE_STATUS(kStatusGroup_SEMC, 1), + kStatus_SEMC_AxiCommandExecutionError = MAKE_STATUS(kStatusGroup_SEMC, 2), + kStatus_SEMC_InvalidMemorySize = MAKE_STATUS(kStatusGroup_SEMC, 3), + kStatus_SEMC_InvalidIpcmdDataSize = MAKE_STATUS(kStatusGroup_SEMC, 4), + kStatus_SEMC_InvalidAddressPortWidth = MAKE_STATUS(kStatusGroup_SEMC, 5), + kStatus_SEMC_InvalidDataPortWidth = MAKE_STATUS(kStatusGroup_SEMC, 6), + kStatus_SEMC_InvalidSwPinmuxSelection = MAKE_STATUS(kStatusGroup_SEMC, 7), + kStatus_SEMC_InvalidBurstLength = MAKE_STATUS(kStatusGroup_SEMC, 8), + kStatus_SEMC_InvalidColumnAddressBitWidth = MAKE_STATUS(kStatusGroup_SEMC, 9), + kStatus_SEMC_InvalidBaseAddress = MAKE_STATUS(kStatusGroup_SEMC, 10), + kStatus_SEMC_InvalidTimerSetting = MAKE_STATUS(kStatusGroup_SEMC, 11), +}; + +/*! @brief SEMC memory device type. */ +typedef enum _semc_mem_type +{ + kSEMC_MemType_SDRAM = 0, /*!< SDRAM */ + kSEMC_MemType_SRAM, /*!< SRAM */ + kSEMC_MemType_NOR, /*!< NOR */ + kSEMC_MemType_NAND, /*!< NAND */ + kSEMC_MemType_8080 /*!< 8080. */ +} semc_mem_type_t; + +/*! @brief SEMC WAIT/RDY polarity. */ +typedef enum _semc_waitready_polarity +{ + kSEMC_LowActive = 0, /*!< Low active. */ + kSEMC_HighActive, /*!< High active. */ +} semc_waitready_polarity_t; + +/*! @brief SEMC SDRAM Chip selection . */ +typedef enum _semc_sdram_cs +{ + kSEMC_SDRAM_CS0 = 0, /*!< SEMC SDRAM CS0. */ + kSEMC_SDRAM_CS1, /*!< SEMC SDRAM CS1. */ + kSEMC_SDRAM_CS2, /*!< SEMC SDRAM CS2. */ + kSEMC_SDRAM_CS3 /*!< SEMC SDRAM CS3. */ +} semc_sdram_cs_t; + +/*! @brief SEMC NAND device type. */ +typedef enum _semc_nand_access_type +{ + kSEMC_NAND_ACCESS_BY_AXI = 0, + kSEMC_NAND_ACCESS_BY_IPCMD, +} semc_nand_access_type_t; + +/*! @brief SEMC interrupts . */ +typedef enum _semc_interrupt_enable +{ + kSEMC_IPCmdDoneInterrupt = SEMC_INTEN_IPCMDDONEEN_MASK, /*!< Ip command done interrupt. */ + kSEMC_IPCmdErrInterrupt = SEMC_INTEN_IPCMDERREN_MASK, /*!< Ip command error interrupt. */ + kSEMC_AXICmdErrInterrupt = SEMC_INTEN_AXICMDERREN_MASK, /*!< AXI command error interrupt. */ + kSEMC_AXIBusErrInterrupt = SEMC_INTEN_AXIBUSERREN_MASK /*!< AXI bus error interrupt. */ +} semc_interrupt_enable_t; + +/*! @brief SEMC IP command data size in bytes. */ +typedef enum _semc_ipcmd_datasize +{ + kSEMC_IPcmdDataSize_1bytes = 1, /*!< The IP command data size 1 byte. */ + kSEMC_IPcmdDataSize_2bytes, /*!< The IP command data size 2 byte. */ + kSEMC_IPcmdDataSize_3bytes, /*!< The IP command data size 3 byte. */ + kSEMC_IPcmdDataSize_4bytes /*!< The IP command data size 4 byte. */ +} semc_ipcmd_datasize_t; + +/*! @brief SEMC auto-refresh timing. */ +typedef enum _semc_refresh_time +{ + kSEMC_RefreshThreeClocks = 0x0U, /*!< The refresh timing with three bus clocks. */ + kSEMC_RefreshSixClocks, /*!< The refresh timing with six bus clocks. */ + kSEMC_RefreshNineClocks /*!< The refresh timing with nine bus clocks. */ +} semc_refresh_time_t; + +/*! @brief CAS latency */ +typedef enum _semc_caslatency +{ + kSEMC_LatencyOne = 1, /*!< Latency 1. */ + kSEMC_LatencyTwo, /*!< Latency 2. */ + kSEMC_LatencyThree, /*!< Latency 3. */ +} semc_caslatency_t; + +/*! @brief SEMC sdram column address bit number. */ +typedef enum _semc_sdram_column_bit_num +{ + kSEMC_SdramColunm_12bit = 0x0U, /*!< 12 bit. */ + kSEMC_SdramColunm_11bit, /*!< 11 bit. */ + kSEMC_SdramColunm_10bit, /*!< 10 bit. */ + kSEMC_SdramColunm_9bit, /*!< 9 bit. */ +} semc_sdram_column_bit_num_t; + +/*! @brief SEMC sdram burst length. */ +typedef enum _semc_sdram_burst_len +{ + kSEMC_Sdram_BurstLen1 = 0, /*!< Burst length 1*/ + kSEMC_Sdram_BurstLen2, /*!< Burst length 2*/ + kSEMC_Sdram_BurstLen4, /*!< Burst length 4*/ + kSEMC_Sdram_BurstLen8 /*!< Burst length 8*/ +} sem_sdram_burst_len_t; + +/*! @brief SEMC nand column address bit number. */ +typedef enum _semc_nand_column_bit_num +{ + kSEMC_NandColum_16bit = 0x0U, /*!< 16 bit. */ + kSEMC_NandColum_15bit, /*!< 15 bit. */ + kSEMC_NandColum_14bit, /*!< 14 bit. */ + kSEMC_NandColum_13bit, /*!< 13 bit. */ + kSEMC_NandColum_12bit, /*!< 12 bit. */ + kSEMC_NandColum_11bit, /*!< 11 bit. */ + kSEMC_NandColum_10bit, /*!< 10 bit. */ + kSEMC_NandColum_9bit, /*!< 9 bit. */ +} semc_nand_column_bit_num_t; + +/*! @brief SEMC nand burst length. */ +typedef enum _semc_nand_burst_len +{ + kSEMC_Nand_BurstLen1 = 0, /*!< Burst length 1*/ + kSEMC_Nand_BurstLen2, /*!< Burst length 2*/ + kSEMC_Nand_BurstLen4, /*!< Burst length 4*/ + kSEMC_Nand_BurstLen8, /*!< Burst length 8*/ + kSEMC_Nand_BurstLen16, /*!< Burst length 16*/ + kSEMC_Nand_BurstLen32, /*!< Burst length 32*/ + kSEMC_Nand_BurstLen64 /*!< Burst length 64*/ +} sem_nand_burst_len_t; + +/*! @brief SEMC nor/sram column address bit number. */ +typedef enum _semc_norsram_column_bit_num +{ + kSEMC_NorColum_12bit = 0x0U, /*!< 12 bit. */ + kSEMC_NorColum_11bit, /*!< 11 bit. */ + kSEMC_NorColum_10bit, /*!< 10 bit. */ + kSEMC_NorColum_9bit, /*!< 9 bit. */ + kSEMC_NorColum_8bit, /*!< 8 bit. */ + kSEMC_NorColum_7bit, /*!< 7 bit. */ + kSEMC_NorColum_6bit, /*!< 6 bit. */ + kSEMC_NorColum_5bit, /*!< 5 bit. */ + kSEMC_NorColum_4bit, /*!< 4 bit. */ + kSEMC_NorColum_3bit, /*!< 3 bit. */ + kSEMC_NorColum_2bit /*!< 2 bit. */ +} semc_norsram_column_bit_num_t; + +/*! @brief SEMC nor/sram burst length. */ +typedef enum _semc_norsram_burst_len +{ + kSEMC_Nor_BurstLen1 = 0, /*!< Burst length 1*/ + kSEMC_Nor_BurstLen2, /*!< Burst length 2*/ + kSEMC_Nor_BurstLen4, /*!< Burst length 4*/ + kSEMC_Nor_BurstLen8, /*!< Burst length 8*/ + kSEMC_Nor_BurstLen16, /*!< Burst length 16*/ + kSEMC_Nor_BurstLen32, /*!< Burst length 32*/ + kSEMC_Nor_BurstLen64 /*!< Burst length 64*/ +} sem_norsram_burst_len_t; + +/*! @brief SEMC dbi column address bit number. */ +typedef enum _semc_dbi_column_bit_num +{ + kSEMC_Dbi_Colum_12bit = 0x0U, /*!< 12 bit. */ + kSEMC_Dbi_Colum_11bit, /*!< 11 bit. */ + kSEMC_Dbi_Colum_10bit, /*!< 10 bit. */ + kSEMC_Dbi_Colum_9bit, /*!< 9 bit. */ + kSEMC_Dbi_Colum_8bit, /*!< 8 bit. */ + kSEMC_Dbi_Colum_7bit, /*!< 7 bit. */ + kSEMC_Dbi_Colum_6bit, /*!< 6 bit. */ + kSEMC_Dbi_Colum_5bit, /*!< 5 bit. */ + kSEMC_Dbi_Colum_4bit, /*!< 4 bit. */ + kSEMC_Dbi_Colum_3bit, /*!< 3 bit. */ + kSEMC_Dbi_Colum_2bit /*!< 2 bit. */ +} semc_dbi_column_bit_num_t; + +/*! @brief SEMC dbi burst length. */ +typedef enum _semc_dbi_burst_len +{ + kSEMC_Dbi_BurstLen1 = 0, /*!< Burst length 1*/ + kSEMC_Dbi_BurstLen2, /*!< Burst length 2*/ + kSEMC_Dbi_Dbi_BurstLen4, /*!< Burst length 4*/ + kSEMC_Dbi_BurstLen8, /*!< Burst length 8*/ + kSEMC_Dbi_BurstLen16, /*!< Burst length 16*/ + kSEMC_Dbi_BurstLen32, /*!< Burst length 32*/ + kSEMC_Dbi_BurstLen64 /*!< Burst length 64*/ +} sem_dbi_burst_len_t; + +/*! @brief SEMC IOMUXC. */ +typedef enum _semc_iomux_pin +{ + kSEMC_MUXA8 = SEMC_IOCR_MUX_A8_SHIFT, /*!< MUX A8 pin. */ + kSEMC_MUXCSX0 = SEMC_IOCR_MUX_CSX0_SHIFT, /*!< MUX CSX0 pin */ + kSEMC_MUXCSX1 = SEMC_IOCR_MUX_CSX1_SHIFT, /*!< MUX CSX1 Pin.*/ + kSEMC_MUXCSX2 = SEMC_IOCR_MUX_CSX2_SHIFT, /*!< MUX CSX2 Pin. */ + kSEMC_MUXCSX3 = SEMC_IOCR_MUX_CSX3_SHIFT, /*!< MUX CSX3 Pin. */ + kSEMC_MUXRDY = SEMC_IOCR_MUX_RDY_SHIFT /*!< MUX RDY pin. */ +} semc_iomux_pin; + +/*! @brief SEMC NOR/PSRAM Address bit 27 A27. */ +typedef enum _semc_iomux_nora27_pin +{ + kSEMC_MORA27_NONE = 0, /*!< No NOR/SRAM A27 pin. */ + kSEMC_NORA27_MUXCSX3 = SEMC_IOCR_MUX_CSX3_SHIFT, /*!< MUX CSX3 Pin. */ + kSEMC_NORA27_MUXRDY = SEMC_IOCR_MUX_RDY_SHIFT /*!< MUX RDY pin. */ +} semc_iomux_nora27_pin; + +/*! @brief SEMC port size. */ +typedef enum _semc_port_size +{ + kSEMC_PortSize8Bit = 0, /*!< 8-Bit port size. */ + kSEMC_PortSize16Bit /*!< 16-Bit port size. */ +} smec_port_size_t; + +/*! @brief SEMC address mode. */ +typedef enum _semc_addr_mode +{ + kSEMC_AddrDataMux = 0, /*!< SEMC address/data mux mode. */ + kSEMC_AdvAddrdataMux, /*!< Advanced address/data mux mode. */ + kSEMC_AddrDataNonMux /*!< Address/data non-mux mode. */ +} semc_addr_mode_t; + +/*! @brief SEMC DQS read strobe mode. */ +typedef enum _semc_dqs_mode +{ + kSEMC_Loopbackinternal = 0, /*!< Dummy read strobe loopbacked internally. */ + kSEMC_Loopbackdqspad, /*!< Dummy read strobe loopbacked from DQS pad. */ +} semc_dqs_mode_t; + +/*! @brief SEMC ADV signal active polarity. */ +typedef enum _semc_adv_polarity +{ + kSEMC_AdvActiveLow = 0, /*!< Adv active low. */ + kSEMC_AdvActivehigh, /*!< Adv active low. */ +} semc_adv_polarity_t; + +/*! @brief SEMC RDY signal active polarity. */ +typedef enum _semc_rdy_polarity +{ + kSEMC_RdyActiveLow = 0, /*!< Adv active low. */ + kSEMC_RdyActivehigh, /*!< Adv active low. */ +} semc_rdy_polarity_t; + +/*! @brief SEMC IP command for NAND: address mode. */ +typedef enum _semc_ipcmd_nand_addrmode +{ + kSEMC_NANDAM_ColumnRow = 0x0U, /*!< Address mode: column and row address(5Byte-CA0/CA1/RA0/RA1/RA2). */ + kSEMC_NANDAM_ColumnCA0, /*!< Address mode: column address only(1 Byte-CA0). */ + kSEMC_NANDAM_ColumnCA0CA1, /*!< Address mode: column address only(2 Byte-CA0/CA1). */ + kSEMC_NANDAM_RawRA0, /*!< Address mode: row address only(1 Byte-RA0). */ + kSEMC_NANDAM_RawRA0RA1, /*!< Address mode: row address only(2 Byte-RA0/RA1). */ + kSEMC_NANDAM_RawRA0RA1RA2 /*!< Address mode: row address only(3 Byte-RA0). */ +} semc_ipcmd_nand_addrmode_t; + +/*! @brief SEMC IP command for NAND： command mode. */ +typedef enum _semc_ipcmd_nand_cmdmode +{ + kSEMC_NANDCM_Command = 0x2U, /*!< command. */ + kSEMC_NANDCM_CommandHold, /*!< Command hold. */ + kSEMC_NANDCM_CommandAddress, /*!< Command address. */ + kSEMC_NANDCM_CommandAddressHold, /*!< Command address hold. */ + kSEMC_NANDCM_CommandAddressRead, /*!< Command address read. */ + kSEMC_NANDCM_CommandAddressWrite, /*!< Command address write. */ + kSEMC_NANDCM_CommandRead, /*!< Command read. */ + kSEMC_NANDCM_CommandWrite, /*!< Command write. */ + kSEMC_NANDCM_Read, /*!< Read. */ + kSEMC_NANDCM_Write /*!< Write. */ +} semc_ipcmd_nand_cmdmode_t; + +/*! @brief SEMC NAND address option. */ +typedef enum _semc_nand_address_option +{ + kSEMC_NandAddrOption_5byte_CA2RA3 = 0U, /*!< CA0+CA1+RA0+RA1+RA2 */ + kSEMC_NandAddrOption_4byte_CA2RA2 = 2U, /*!< CA0+CA1+RA0+RA1 */ + kSEMC_NandAddrOption_3byte_CA2RA1 = 4U, /*!< CA0+CA1+RA0 */ + kSEMC_NandAddrOption_4byte_CA1RA3 = 1U, /*!< CA0+RA0+RA1+RA2 */ + kSEMC_NandAddrOption_3byte_CA1RA2 = 3U, /*!< CA0+RA0+RA1 */ + kSEMC_NandAddrOption_2byte_CA1RA1 = 7U, /*!< CA0+RA0 */ +} semc_nand_address_option_t; + +/*! @brief SEMC IP command for NOR. */ +typedef enum _semc_ipcmd_nor_dbi +{ + kSEMC_NORDBICM_Read = 0x2U, /*!< NOR read. */ + kSEMC_NORDBICM_Write /*!< NOR write. */ +} semc_ipcmd_nor_dbi_t; + +/*! @brief SEMC IP command for SRAM. */ +typedef enum _semc_ipcmd_sram +{ + kSEMC_SRAMCM_ArrayRead = 0x2U, /*!< SRAM memory array read. */ + kSEMC_SRAMCM_ArrayWrite, /*!< SRAM memory array write. */ + kSEMC_SRAMCM_RegRead, /*!< SRAM memory register read. */ + kSEMC_SRAMCM_RegWrite /*!< SRAM memory register write. */ +} semc_ipcmd_sram_t; + +/*! @brief SEMC IP command for SDARM. */ +typedef enum _semc_ipcmd_sdram +{ + kSEMC_SDRAMCM_Read = 0x8U, /*!< SDRAM memory read. */ + kSEMC_SDRAMCM_Write, /*!< SDRAM memory write. */ + kSEMC_SDRAMCM_Modeset, /*!< SDRAM MODE SET. */ + kSEMC_SDRAMCM_Active, /*!< SDRAM active. */ + kSEMC_SDRAMCM_AutoRefresh, /*!< SDRAM auto-refresh. */ + kSEMC_SDRAMCM_SelfRefresh, /*!< SDRAM self-refresh. */ + kSEMC_SDRAMCM_Precharge, /*!< SDRAM precharge. */ + kSEMC_SDRAMCM_Prechargeall /*!< SDRAM precharge all. */ +} semc_ipcmd_sdram_t; + +/*! @brief SEMC SDRAM configuration structure. + * + * 1. The memory size in the configuration is in the unit of KB. So memsize_kbytes + * should be set as 2^2, 2^3, 2^4 .etc which is base 2KB exponential function. + * Take refer to BR0~BR3 register in RM for details. + * 2. The prescalePeriod_N16Cycle is in unit of 16 clock cycle. It is a exception for prescaleTimer_n16cycle = 0, + * it means the prescaler timer period is 256 * 16 clock cycles. For precalerIf precalerTimer_n16cycle not equal to 0, + * The prescaler timer period is prescalePeriod_N16Cycle * 16 clock cycles. + * idleTimeout_NprescalePeriod, refreshUrgThreshold_NprescalePeriod, refreshPeriod_NprescalePeriod are + * similar to prescalePeriod_N16Cycle. + * + */ +typedef struct _semc_sdram_config +{ + semc_iomux_pin csxPinMux; /*!< CS pin mux. The kSEMC_MUXA8 is not valid in sdram pin mux setting. */ + uint32_t address; /*!< The base address. */ + uint32_t memsize_kbytes; /*!< The memory size in unit of kbytes. */ + smec_port_size_t portSize; /*!< Port size. */ + sem_sdram_burst_len_t burstLen; /*!< Burst length. */ + semc_sdram_column_bit_num_t columnAddrBitNum; /*!< Column address bit number. */ + semc_caslatency_t casLatency; /*!< CAS latency. */ + uint8_t tPrecharge2Act_Ns; /*!< Precharge to active wait time in unit of nanosecond. */ + uint8_t tAct2ReadWrite_Ns; /*!< Act to read/write wait time in unit of nanosecond. */ + uint8_t tRefreshRecovery_Ns; /*!< Refresh recovery time in unit of nanosecond. */ + uint8_t tWriteRecovery_Ns; /*!< write recovery time in unit of nanosecond. */ + uint8_t tCkeOff_Ns; /*!< CKE off minimum time in unit of nanosecond. */ + uint8_t tAct2Prechage_Ns; /*!< Active to precharge in unit of nanosecond. */ + uint8_t tSelfRefRecovery_Ns; /*!< Self refresh recovery time in unit of nanosecond. */ + uint8_t tRefresh2Refresh_Ns; /*!< Refresh to refresh wait time in unit of nanosecond. */ + uint8_t tAct2Act_Ns; /*!< Active to active wait time in unit of nanosecond. */ + uint32_t tPrescalePeriod_Ns; /*!< Prescaler timer period should not be larger than 256 * 16 * clock cycle. */ + uint32_t tIdleTimeout_Ns; /*!< Idle timeout in unit of prescale time period. */ + uint32_t refreshPeriod_nsPerRow; /*!< Refresh timer period like 64ms * 1000000/8192 . */ + uint32_t refreshUrgThreshold; /*!< Refresh urgent threshold. */ + uint8_t refreshBurstLen; /*!< Refresh burst length. */ +} semc_sdram_config_t; + +/*! @brief SEMC NAND device timing configuration structure. */ +typedef struct _semc_nand_timing_config +{ + uint8_t tCeSetup_Ns; /*!< CE setup time: tCS. */ + uint8_t tCeHold_Ns; /*!< CE hold time: tCH. */ + uint8_t tCeInterval_Ns; /*!< CE interval time:tCEITV. */ + uint8_t tWeLow_Ns; /*!< WE low time: tWP. */ + uint8_t tWeHigh_Ns; /*!< WE high time: tWH. */ + uint8_t tReLow_Ns; /*!< RE low time: tRP. */ + uint8_t tReHigh_Ns; /*!< RE high time: tREH. */ + uint8_t tTurnAround_Ns; /*!< Turnaround time for async mode: tTA. */ + uint8_t tWehigh2Relow_Ns; /*!< WE# high to RE# wait time: tWHR. */ + uint8_t tRehigh2Welow_Ns; /*!< RE# high to WE# low wait time: tRHW. */ + uint8_t tAle2WriteStart_Ns; /*!< ALE to write start wait time: tADL. */ + uint8_t tReady2Relow_Ns; /*!< Ready to RE# low min wait time: tRR. */ + uint8_t tWehigh2Busy_Ns; /*!< WE# high to busy wait time: tWB. */ +} semc_nand_timing_config_t; + +/*! @brief SEMC NAND configuration structure. */ +typedef struct _semc_nand_config +{ + semc_iomux_pin cePinMux; /*!< The CE pin mux setting. The kSEMC_MUXRDY is not valid for CE pin setting. */ + uint32_t axiAddress; /*!< The base address for AXI nand. */ + uint32_t axiMemsize_kbytes; /*!< The memory size in unit of kbytes for AXI nand. */ + uint32_t ipgAddress; /*!< The base address for IPG nand . */ + uint32_t ipgMemsize_kbytes; /*!< The memory size in unit of kbytes for IPG nand. */ + semc_rdy_polarity_t rdyactivePolarity; /*!< Wait ready polarity. */ + bool edoModeEnabled; /*!< EDO mode enabled. */ + semc_nand_column_bit_num_t columnAddrBitNum; /*!< Column address bit number. */ + semc_nand_address_option_t arrayAddrOption; /*!< Address option. */ + sem_nand_burst_len_t burstLen; /*!< Burst length. */ + smec_port_size_t portSize; /*!< Port size. */ + semc_nand_timing_config_t *timingConfig; /*!< SEMC nand timing configuration. */ +} semc_nand_config_t; + +/*! @brief SEMC NOR configuration structure. */ +typedef struct _semc_nor_config +{ + semc_iomux_pin cePinMux; /*!< The CE# pin mux setting. */ + semc_iomux_nora27_pin addr27; /*!< The Addr bit 27 pin mux setting. */ + uint32_t address; /*!< The base address. */ + uint32_t memsize_kbytes; /*!< The memory size in unit of kbytes. */ + uint8_t addrPortWidth; /*!< The address port width. */ + semc_rdy_polarity_t rdyactivePolarity; /*!< Wait ready polarity. */ + semc_adv_polarity_t advActivePolarity; /*!< ADV# polarity. */ + semc_norsram_column_bit_num_t columnAddrBitNum; /*!< Column address bit number. */ + semc_addr_mode_t addrMode; /*!< Address mode. */ + sem_norsram_burst_len_t burstLen; /*!< Burst length. */ + smec_port_size_t portSize; /*!< Port size. */ + uint8_t tCeSetup_Ns; /*!< The CE setup time. */ + uint8_t tCeHold_Ns; /*!< The CE hold time. */ + uint8_t tCeInterval_Ns; /*!< CE interval minimum time. */ + uint8_t tAddrSetup_Ns; /*!< The address setup time. */ + uint8_t tAddrHold_Ns; /*!< The address hold time. */ + uint8_t tWeLow_Ns; /*!< WE low time for async mode. */ + uint8_t tWeHigh_Ns; /*!< WE high time for async mode. */ + uint8_t tReLow_Ns; /*!< RE low time for async mode. */ + uint8_t tReHigh_Ns; /*!< RE high time for async mode. */ + uint8_t tTurnAround_Ns; /*!< Turnaround time for async mode. */ + uint8_t tAddr2WriteHold_Ns; /*!< Address to write data hold time for async mode. */ +#if defined(FSL_FEATURE_SEMC_HAS_NOR_WDS_TIME) && (FSL_FEATURE_SEMC_HAS_NOR_WDS_TIME) + uint8_t tWriteSetup_Ns; /*!< Write data setup time for sync mode.*/ +#endif +#if defined(FSL_FEATURE_SEMC_HAS_NOR_WDH_TIME) && (FSL_FEATURE_SEMC_HAS_NOR_WDH_TIME) + uint8_t tWriteHold_Ns; /*!< Write hold time for sync mode. */ +#endif + uint8_t latencyCount; /*!< Latency count for sync mode. */ + uint8_t readCycle; /*!< Read cycle time for sync mode. */ +} semc_nor_config_t; + +/*! @brief SEMC SRAM configuration structure. */ +typedef struct _semc_sram_config +{ + semc_iomux_pin cePinMux; /*!< The CE# pin mux setting. */ + semc_iomux_nora27_pin addr27; /*!< The Addr bit 27 pin mux setting. */ + uint32_t address; /*!< The base address. */ + uint32_t memsize_kbytes; /*!< The memory size in unit of kbytes. */ + uint8_t addrPortWidth; /*!< The address port width. */ + semc_adv_polarity_t advActivePolarity; /*!< ADV# polarity 1: active high, 0: active low. */ + semc_addr_mode_t addrMode; /*!< Address mode. */ + sem_norsram_burst_len_t burstLen; /*!< Burst length. */ + smec_port_size_t portSize; /*!< Port size. */ + uint8_t tCeSetup_Ns; /*!< The CE setup time. */ + uint8_t tCeHold_Ns; /*!< The CE hold time. */ + uint8_t tCeInterval_Ns; /*!< CE interval minimum time. */ + uint8_t tAddrSetup_Ns; /*!< The address setup time. */ + uint8_t tAddrHold_Ns; /*!< The address hold time. */ + uint8_t tWeLow_Ns; /*!< WE low time for async mode. */ + uint8_t tWeHigh_Ns; /*!< WE high time for async mode. */ + uint8_t tReLow_Ns; /*!< RE low time for async mode. */ + uint8_t tReHigh_Ns; /*!< RE high time for async mode. */ + uint8_t tTurnAround_Ns; /*!< Turnaround time for async mode. */ + uint8_t tAddr2WriteHold_Ns; /*!< Address to write data hold time for async mode. */ + uint8_t tWriteSetup_Ns; /*!< Write data setup time for sync mode.*/ + uint8_t tWriteHold_Ns; /*!< Write hold time for sync mode. */ + uint8_t latencyCount; /*!< Latency count for sync mode. */ + uint8_t readCycle; /*!< Read cycle time for sync mode. */ +} semc_sram_config_t; + +/*! @brief SEMC DBI configuration structure. */ +typedef struct _semc_dbi_config +{ + semc_iomux_pin csxPinMux; /*!< The CE# pin mux. */ + uint32_t address; /*!< The base address. */ + uint32_t memsize_kbytes; /*!< The memory size in unit of 4kbytes. */ + semc_dbi_column_bit_num_t columnAddrBitNum; /*!< Column address bit number. */ + sem_dbi_burst_len_t burstLen; /*!< Burst length. */ + smec_port_size_t portSize; /*!< Port size. */ + uint8_t tCsxSetup_Ns; /*!< The CSX setup time. */ + uint8_t tCsxHold_Ns; /*!< The CSX hold time. */ + uint8_t tWexLow_Ns; /*!< WEX low time. */ + uint8_t tWexHigh_Ns; /*!< WEX high time. */ + uint8_t tRdxLow_Ns; /*!< RDX low time. */ + uint8_t tRdxHigh_Ns; /*!< RDX high time. */ + uint8_t tCsxInterval_Ns; /*!< Write data setup time.*/ +} semc_dbi_config_t; + +/*! @brief SEMC AXI queue a weight setting structure. */ +typedef struct _semc_queuea_weight_struct +{ + uint32_t qos : 4; /*!< weight of qos for queue 0 . */ + uint32_t aging : 4; /*!< weight of aging for queue 0.*/ + uint32_t slaveHitSwith : 8; /*!< weight of read/write switch for queue 0.*/ + uint32_t slaveHitNoswitch : 8; /*!< weight of read/write no switch for queue 0 .*/ +} semc_queuea_weight_struct_t; + +/*! @brief SEMC AXI queue a weight setting union. */ +typedef union _semc_queuea_weight +{ + semc_queuea_weight_struct_t queueaConfig; /*!< Structure configuration for queueA. */ + uint32_t queueaValue; /*!< Configuration value for queueA which could directly write to the reg. */ +} semc_queuea_weight_t; + +/*! @brief SEMC AXI queue b weight setting structure. */ +typedef struct _semc_queueb_weight_struct +{ + uint32_t qos : 4; /*!< weight of qos for queue 1. */ + uint32_t aging : 4; /*!< weight of aging for queue 1.*/ + uint32_t slaveHitSwith : 8; /*!< weight of read/write switch for queue 1.*/ + uint32_t weightPagehit : 8; /*!< weight of page hit for queue 1 only .*/ + uint32_t bankRotation : 8; /*!< weight of bank rotation for queue 1 only .*/ +} semc_queueb_weight_struct_t; + +/*! @brief SEMC AXI queue b weight setting union. */ +typedef union _semc_queueb_weight +{ + semc_queueb_weight_struct_t queuebConfig; /*!< Structure configuration for queueB. */ + uint32_t queuebValue; /*!< Configuration value for queueB which could directly write to the reg. */ +} semc_queueb_weight_t; + +/*! @brief SEMC AXI queue weight setting. */ +typedef struct _semc_axi_queueweight +{ + semc_queuea_weight_t queueaWeight; /*!< Weight settings for queue a. */ + semc_queueb_weight_t queuebWeight; /*!< Weight settings for queue b. */ +} semc_axi_queueweight_t; + +/*! + * @brief SEMC configuration structure. + * + * busTimeoutCycles: when busTimeoutCycles is zero, the bus timeout cycle is + * 255*1024. otherwise the bus timeout cycles is busTimeoutCycles*1024. + * cmdTimeoutCycles: is used for command execution timeout cycles. it's + * similar to the busTimeoutCycles. + */ +typedef struct _semc_config_t +{ + semc_dqs_mode_t dqsMode; /*!< Dummy read strobe mode: use enum in "semc_dqs_mode_t". */ + uint8_t cmdTimeoutCycles; /*!< Command execution timeout cycles. */ + uint8_t busTimeoutCycles; /*!< Bus timeout cycles. */ + semc_axi_queueweight_t queueWeight; /*!< AXI queue weight. */ +} semc_config_t; + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @name SEMC Initialization and De-initialization + * @{ + */ + +/*! + * @brief Gets the SEMC default basic configuration structure. + * + * The purpose of this API is to get the default SEMC + * configure structure for SEMC_Init(). User may use the initialized + * structure unchanged in SEMC_Init(), or modify some fields of the + * structure before calling SEMC_Init(). + * Example: + @code + semc_config_t config; + SEMC_GetDefaultConfig(&config); + @endcode + * @param config The SEMC configuration structure pointer. + */ +void SEMC_GetDefaultConfig(semc_config_t *config); + +/*! + * @brief Initializes SEMC. + * This function ungates the SEMC clock and initializes SEMC. + * This function must be called before calling any other SEMC driver functions. + * + * @param base SEMC peripheral base address. + * @param configure The SEMC configuration structure pointer. + */ +void SEMC_Init(SEMC_Type *base, semc_config_t *configure); + +/*! + * @brief Deinitializes the SEMC module and gates the clock. + * + * This function gates the SEMC clock. As a result, the SEMC module doesn't work after + * calling this function, for some IDE, calling this API may cause the next downloading + * operation failed. so, please call this API cautiously. Additional, users can + * using "#define FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL (1)" to disable the clock control + * operation in drivers. + * + * @param base SEMC peripheral base address. + */ +void SEMC_Deinit(SEMC_Type *base); + +/* @} */ + +/*! + * @name SEMC Configuration Operation For Each Memory Type + * @{ + */ + +/*! + * @brief Configures SDRAM controller in SEMC. + * + * @param base SEMC peripheral base address. + * @param cs The chip selection. + * @param config The sdram configuration. + * @param clkSrc_Hz The SEMC clock frequency. + */ +status_t SEMC_ConfigureSDRAM(SEMC_Type *base, semc_sdram_cs_t cs, semc_sdram_config_t *config, uint32_t clkSrc_Hz); + +/*! + * @brief Configures NAND controller in SEMC. + * + * @param base SEMC peripheral base address. + * @param config The nand configuration. + * @param clkSrc_Hz The SEMC clock frequency. + */ +status_t SEMC_ConfigureNAND(SEMC_Type *base, semc_nand_config_t *config, uint32_t clkSrc_Hz); + +/*! + * @brief Configures NOR controller in SEMC. + * + * @param base SEMC peripheral base address. + * @param config The nor configuration. + * @param clkSrc_Hz The SEMC clock frequency. + */ +status_t SEMC_ConfigureNOR(SEMC_Type *base, semc_nor_config_t *config, uint32_t clkSrc_Hz); + +/*! + * @brief Configures SRAM controller in SEMC. + * + * @param base SEMC peripheral base address. + * @param config The sram configuration. + * @param clkSrc_Hz The SEMC clock frequency. + */ +status_t SEMC_ConfigureSRAM(SEMC_Type *base, semc_sram_config_t *config, uint32_t clkSrc_Hz); + +/*! + * @brief Configures DBI controller in SEMC. + * + * @param base SEMC peripheral base address. + * @param config The dbi configuration. + * @param clkSrc_Hz The SEMC clock frequency. + */ +status_t SEMC_ConfigureDBI(SEMC_Type *base, semc_dbi_config_t *config, uint32_t clkSrc_Hz); + +/* @} */ + +/*! + * @name SEMC Interrupt Operation + * @{ + */ + +/*! + * @brief Enables the SEMC interrupt. + * + * This function enables the SEMC interrupts according to the provided mask. The mask + * is a logical OR of enumeration members. See @ref semc_interrupt_enable_t. + * For example, to enable the IP command done and error interrupt, do the following. + * @code + * SEMC_EnableInterrupts(ENET, kSEMC_IPCmdDoneInterrupt | kSEMC_IPCmdErrInterrupt); + * @endcode + * + * @param base SEMC peripheral base address. + * @param mask SEMC interrupts to enable. This is a logical OR of the + * enumeration :: semc_interrupt_enable_t. + */ +static inline void SEMC_EnableInterrupts(SEMC_Type *base, uint32_t mask) +{ + base->INTEN |= mask; +} + +/*! + * @brief Disables the SEMC interrupt. + * + * This function disables the SEMC interrupts according to the provided mask. The mask + * is a logical OR of enumeration members. See @ref semc_interrupt_enable_t. + * For example, to disable the IP command done and error interrupt, do the following. + * @code + * SEMC_DisableInterrupts(ENET, kSEMC_IPCmdDoneInterrupt | kSEMC_IPCmdErrInterrupt); + * @endcode + * + * @param base SEMC peripheral base address. + * @param mask SEMC interrupts to disable. This is a logical OR of the + * enumeration :: semc_interrupt_enable_t. + */ +static inline void SEMC_DisableInterrupts(SEMC_Type *base, uint32_t mask) +{ + base->INTEN &= ~mask; +} + +/*! + * @brief Gets the SEMC status. + * + * This function gets the SEMC interrupts event status. + * User can use the a logical OR of enumeration member as a mask. + * See @ref semc_interrupt_enable_t. + * + * @param base SEMC peripheral base address. + * @return status flag, use status flag in semc_interrupt_enable_t to get the related status. + */ +static inline bool SEMC_GetStatusFlag(SEMC_Type *base) +{ + return base->INTR; +} + +/*! + * @brief Clears the SEMC status flag state. + * + * The following status register flags can be cleared SEMC interrupt status. + * + * @param base SEMC base pointer + * @param mask The status flag mask, a logical OR of enumeration member @ref semc_interrupt_enable_t. + */ +static inline void SEMC_ClearStatusFlags(SEMC_Type *base, uint32_t mask) +{ + base->INTR |= mask; +} + +/* @} */ + +/*! + * @name SEMC Memory Access Operation + * @{ + */ + +/*! + * @brief Check if SEMC is in idle. + * + * @param base SEMC peripheral base address. + * @return True SEMC is in idle, false is not in idle. + */ +static inline bool SEMC_IsInIdle(SEMC_Type *base) +{ + return (base->STS0 & SEMC_STS0_IDLE_MASK) ? true : false; +} + +/*! + * @brief SEMC IP command access. + * + * @param base SEMC peripheral base address. + * @param type SEMC memory type. refer to "semc_mem_type_t" + * @param address SEMC device address. + * @param command SEMC IP command. + * For NAND device, we should use the SEMC_BuildNandIPCommand to get the right nand command. + * For NOR/DBI device, take refer to "semc_ipcmd_nor_dbi_t". + * For SRAM device, take refer to "semc_ipcmd_sram_t". + * For SDRAM device, take refer to "semc_ipcmd_sdram_t". + * @param write Data for write access. + * @param read Data pointer for read data out. + */ +status_t SEMC_SendIPCommand( + SEMC_Type *base, semc_mem_type_t type, uint32_t address, uint16_t command, uint32_t write, uint32_t *read); + +/*! + * @brief Build SEMC IP command for NAND. + * + * This function build SEMC NAND IP command. The command is build of user command code, + * SEMC address mode and SEMC command mode. + * + * @param userCommand NAND device normal command. + * @param addrMode NAND address mode. Refer to "semc_ipcmd_nand_addrmode_t". + * @param cmdMode NAND command mode. Refer to "semc_ipcmd_nand_cmdmode_t". + */ +static inline uint16_t SEMC_BuildNandIPCommand(uint8_t userCommand, + semc_ipcmd_nand_addrmode_t addrMode, + semc_ipcmd_nand_cmdmode_t cmdMode) +{ + return (uint16_t)((uint16_t)userCommand << 8) | (uint16_t)(addrMode << 4) | ((uint8_t)cmdMode & 0x0Fu); +} + +/*! + * @brief Check if the NAND device is ready. + * + * @param base SEMC peripheral base address. + * @return True NAND is ready, false NAND is not ready. + */ +static inline bool SEMC_IsNandReady(SEMC_Type *base) +{ + return (base->STS0 & SEMC_STS0_NARDY_MASK) ? true : false; +} + +/*! + * @brief SEMC NAND device memory write through IP command. + * + * @param base SEMC peripheral base address. + * @param address SEMC NAND device address. + * @param data Data for write access. + * @param size_bytes Data length. + */ +status_t SEMC_IPCommandNandWrite(SEMC_Type *base, uint32_t address, uint8_t *data, uint32_t size_bytes); + +/*! + * @brief SEMC NAND device memory read through IP command. + * + * @param base SEMC peripheral base address. + * @param address SEMC NAND device address. + * @param data Data pointer for data read out. + * @param size_bytes Data length. + */ +status_t SEMC_IPCommandNandRead(SEMC_Type *base, uint32_t address, uint8_t *data, uint32_t size_bytes); + +/*! + * @brief SEMC NOR device memory write through IP command. + * + * @param base SEMC peripheral base address. + * @param address SEMC NOR device address. + * @param data Data for write access. + * @param size_bytes Data length. + */ +status_t SEMC_IPCommandNorWrite(SEMC_Type *base, uint32_t address, uint8_t *data, uint32_t size_bytes); + +/*! + * @brief SEMC NOR device memory read through IP command. + * + * @param base SEMC peripheral base address. + * @param address SEMC NOR device address. + * @param data Data pointer for data read out. + * @param size_bytes Data length. + */ +status_t SEMC_IPCommandNorRead(SEMC_Type *base, uint32_t address, uint8_t *data, uint32_t size_bytes); + +/* @} */ + +#if defined(__cplusplus) +} +#endif + +/*! @}*/ + +#endif /* _FSL_SEMC_H_*/ diff --git a/Ubiquitous/XiZi/board/xidatong/third_party_driver/include/fsl_usdhc.h b/Ubiquitous/XiZi/board/xidatong/third_party_driver/include/fsl_usdhc.h new file mode 100644 index 0000000..e9da48b --- /dev/null +++ b/Ubiquitous/XiZi/board/xidatong/third_party_driver/include/fsl_usdhc.h @@ -0,0 +1,1502 @@ +/* + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +/** + * @file fsl_usdhc.h + * @brief fsl usdhc drivers + * @version 2.0 + * @author AIIT XUOS Lab + * @date 2022-03-15 + */ + +#ifndef _FSL_USDHC_H_ +#define _FSL_USDHC_H_ + +#include "fsl_common.h" + +/*! + * @addtogroup usdhc + * @{ + */ + +/****************************************************************************** + * Definitions. + *****************************************************************************/ + +/*! @name Driver version */ +/*@{*/ +/*! @brief Driver version 2.2.8. */ +#define FSL_USDHC_DRIVER_VERSION (MAKE_VERSION(2U, 2U, 8U)) +/*@}*/ + +/*! @brief Maximum block count can be set one time */ +#define USDHC_MAX_BLOCK_COUNT (USDHC_BLK_ATT_BLKCNT_MASK >> USDHC_BLK_ATT_BLKCNT_SHIFT) + +/*! @brief USDHC status */ +enum _usdhc_status +{ + kStatus_USDHC_BusyTransferring = MAKE_STATUS(kStatusGroup_USDHC, 0U), /*!< Transfer is on-going */ + kStatus_USDHC_PrepareAdmaDescriptorFailed = MAKE_STATUS(kStatusGroup_USDHC, 1U), /*!< Set DMA descriptor failed */ + kStatus_USDHC_SendCommandFailed = MAKE_STATUS(kStatusGroup_USDHC, 2U), /*!< Send command failed */ + kStatus_USDHC_TransferDataFailed = MAKE_STATUS(kStatusGroup_USDHC, 3U), /*!< Transfer data failed */ + kStatus_USDHC_DMADataAddrNotAlign = MAKE_STATUS(kStatusGroup_USDHC, 4U), /*!< data address not align */ + kStatus_USDHC_ReTuningRequest = MAKE_STATUS(kStatusGroup_USDHC, 5U), /*!< re-tuning request */ + kStatus_USDHC_TuningError = MAKE_STATUS(kStatusGroup_USDHC, 6U), /*!< tuning error */ + kStatus_USDHC_NotSupport = MAKE_STATUS(kStatusGroup_USDHC, 7U), /*!< not support */ +}; + +/*! @brief Host controller capabilities flag mask */ +enum _usdhc_capability_flag +{ + kUSDHC_SupportAdmaFlag = USDHC_HOST_CTRL_CAP_ADMAS_MASK, /*!< Support ADMA */ + kUSDHC_SupportHighSpeedFlag = USDHC_HOST_CTRL_CAP_HSS_MASK, /*!< Support high-speed */ + kUSDHC_SupportDmaFlag = USDHC_HOST_CTRL_CAP_DMAS_MASK, /*!< Support DMA */ + kUSDHC_SupportSuspendResumeFlag = USDHC_HOST_CTRL_CAP_SRS_MASK, /*!< Support suspend/resume */ + kUSDHC_SupportV330Flag = USDHC_HOST_CTRL_CAP_VS33_MASK, /*!< Support voltage 3.3V */ + kUSDHC_SupportV300Flag = USDHC_HOST_CTRL_CAP_VS30_MASK, /*!< Support voltage 3.0V */ + kUSDHC_SupportV180Flag = USDHC_HOST_CTRL_CAP_VS18_MASK, /*!< Support voltage 1.8V */ + /* Put additional two flags in HTCAPBLT_MBL's position. */ + kUSDHC_Support4BitFlag = (USDHC_HOST_CTRL_CAP_MBL_SHIFT << 0U), /*!< Support 4 bit mode */ + kUSDHC_Support8BitFlag = (USDHC_HOST_CTRL_CAP_MBL_SHIFT << 1U), /*!< Support 8 bit mode */ + /* sd version 3.0 new feature */ + kUSDHC_SupportDDR50Flag = USDHC_HOST_CTRL_CAP_DDR50_SUPPORT_MASK, /*!< support DDR50 mode */ + +#if defined(FSL_FEATURE_USDHC_HAS_SDR104_MODE) && (!FSL_FEATURE_USDHC_HAS_SDR104_MODE) + kUSDHC_SupportSDR104Flag = 0, /*!< not support SDR104 mode */ +#else + kUSDHC_SupportSDR104Flag = USDHC_HOST_CTRL_CAP_SDR104_SUPPORT_MASK, /*!< support SDR104 mode */ +#endif +#if defined(FSL_FEATURE_USDHC_HAS_SDR50_MODE) && (!FSL_FEATURE_USDHC_HAS_SDR50_MODE) + kUSDHC_SupportSDR50Flag = 0U, /*!< not support SDR50 mode */ +#else + kUSDHC_SupportSDR50Flag = USDHC_HOST_CTRL_CAP_SDR50_SUPPORT_MASK, /*!< support SDR50 mode */ +#endif +}; + +/*! @brief Wakeup event mask */ +enum _usdhc_wakeup_event +{ + kUSDHC_WakeupEventOnCardInt = USDHC_PROT_CTRL_WECINT_MASK, /*!< Wakeup on card interrupt */ + kUSDHC_WakeupEventOnCardInsert = USDHC_PROT_CTRL_WECINS_MASK, /*!< Wakeup on card insertion */ + kUSDHC_WakeupEventOnCardRemove = USDHC_PROT_CTRL_WECRM_MASK, /*!< Wakeup on card removal */ + + kUSDHC_WakeupEventsAll = (kUSDHC_WakeupEventOnCardInt | kUSDHC_WakeupEventOnCardInsert | + kUSDHC_WakeupEventOnCardRemove), /*!< All wakeup events */ +}; + +/*! @brief Reset type mask */ +enum _usdhc_reset +{ + kUSDHC_ResetAll = USDHC_SYS_CTRL_RSTA_MASK, /*!< Reset all except card detection */ + kUSDHC_ResetCommand = USDHC_SYS_CTRL_RSTC_MASK, /*!< Reset command line */ + kUSDHC_ResetData = USDHC_SYS_CTRL_RSTD_MASK, /*!< Reset data line */ + +#if defined(FSL_FEATURE_USDHC_HAS_SDR50_MODE) && (!FSL_FEATURE_USDHC_HAS_SDR50_MODE) + kUSDHC_ResetTuning = 0U, /*!< no reset tuning circuit bit */ +#else + kUSDHC_ResetTuning = USDHC_SYS_CTRL_RSTT_MASK, /*!< reset tuning circuit */ +#endif + + kUSDHC_ResetsAll = + (kUSDHC_ResetAll | kUSDHC_ResetCommand | kUSDHC_ResetData | kUSDHC_ResetTuning), /*!< All reset types */ +}; + +/*! @brief Transfer flag mask */ +enum _usdhc_transfer_flag +{ + kUSDHC_EnableDmaFlag = USDHC_MIX_CTRL_DMAEN_MASK, /*!< Enable DMA */ + + kUSDHC_CommandTypeSuspendFlag = (USDHC_CMD_XFR_TYP_CMDTYP(1U)), /*!< Suspend command */ + kUSDHC_CommandTypeResumeFlag = (USDHC_CMD_XFR_TYP_CMDTYP(2U)), /*!< Resume command */ + kUSDHC_CommandTypeAbortFlag = (USDHC_CMD_XFR_TYP_CMDTYP(3U)), /*!< Abort command */ + + kUSDHC_EnableBlockCountFlag = USDHC_MIX_CTRL_BCEN_MASK, /*!< Enable block count */ + kUSDHC_EnableAutoCommand12Flag = USDHC_MIX_CTRL_AC12EN_MASK, /*!< Enable auto CMD12 */ + kUSDHC_DataReadFlag = USDHC_MIX_CTRL_DTDSEL_MASK, /*!< Enable data read */ + kUSDHC_MultipleBlockFlag = USDHC_MIX_CTRL_MSBSEL_MASK, /*!< Multiple block data read/write */ + kUSDHC_EnableAutoCommand23Flag = USDHC_MIX_CTRL_AC23EN_MASK, /*!< Enable auto CMD23 */ + + kUSDHC_ResponseLength136Flag = USDHC_CMD_XFR_TYP_RSPTYP(1U), /*!< 136 bit response length */ + kUSDHC_ResponseLength48Flag = USDHC_CMD_XFR_TYP_RSPTYP(2U), /*!< 48 bit response length */ + kUSDHC_ResponseLength48BusyFlag = USDHC_CMD_XFR_TYP_RSPTYP(3U), /*!< 48 bit response length with busy status */ + + kUSDHC_EnableCrcCheckFlag = USDHC_CMD_XFR_TYP_CCCEN_MASK, /*!< Enable CRC check */ + kUSDHC_EnableIndexCheckFlag = USDHC_CMD_XFR_TYP_CICEN_MASK, /*!< Enable index check */ + kUSDHC_DataPresentFlag = USDHC_CMD_XFR_TYP_DPSEL_MASK, /*!< Data present flag */ +}; + +/*! @brief Present status flag mask */ +enum _usdhc_present_status_flag +{ + kUSDHC_CommandInhibitFlag = USDHC_PRES_STATE_CIHB_MASK, /*!< Command inhibit */ + kUSDHC_DataInhibitFlag = USDHC_PRES_STATE_CDIHB_MASK, /*!< Data inhibit */ + kUSDHC_DataLineActiveFlag = USDHC_PRES_STATE_DLA_MASK, /*!< Data line active */ + kUSDHC_SdClockStableFlag = USDHC_PRES_STATE_SDSTB_MASK, /*!< SD bus clock stable */ + kUSDHC_WriteTransferActiveFlag = USDHC_PRES_STATE_WTA_MASK, /*!< Write transfer active */ + kUSDHC_ReadTransferActiveFlag = USDHC_PRES_STATE_RTA_MASK, /*!< Read transfer active */ + kUSDHC_BufferWriteEnableFlag = USDHC_PRES_STATE_BWEN_MASK, /*!< Buffer write enable */ + kUSDHC_BufferReadEnableFlag = USDHC_PRES_STATE_BREN_MASK, /*!< Buffer read enable */ + +#if defined(FSL_FEATURE_USDHC_HAS_SDR50_MODE) && (!FSL_FEATURE_USDHC_HAS_SDR50_MODE) + kUSDHC_DelaySettingFinishedFlag = 0U, /*!< not support */ + kUSDHC_ReTuningRequestFlag = 0U, /*!< not support */ +#else + kUSDHC_ReTuningRequestFlag = USDHC_PRES_STATE_RTR_MASK, /*!< re-tuning request flag ,only used for SDR104 mode */ + kUSDHC_DelaySettingFinishedFlag = USDHC_PRES_STATE_TSCD_MASK, /*!< delay setting finished flag */ +#endif + + kUSDHC_CardInsertedFlag = USDHC_PRES_STATE_CINST_MASK, /*!< Card inserted */ + kUSDHC_CommandLineLevelFlag = USDHC_PRES_STATE_CLSL_MASK, /*!< Command line signal level */ + + kUSDHC_Data0LineLevelFlag = 1U << USDHC_PRES_STATE_DLSL_SHIFT, /*!< Data0 line signal level */ + kUSDHC_Data1LineLevelFlag = 1U << (USDHC_PRES_STATE_DLSL_SHIFT + 1U), /*!< Data1 line signal level */ + kUSDHC_Data2LineLevelFlag = 1U << (USDHC_PRES_STATE_DLSL_SHIFT + 2U), /*!< Data2 line signal level */ + kUSDHC_Data3LineLevelFlag = 1U << (USDHC_PRES_STATE_DLSL_SHIFT + 3U), /*!< Data3 line signal level */ + kUSDHC_Data4LineLevelFlag = 1U << (USDHC_PRES_STATE_DLSL_SHIFT + 4U), /*!< Data4 line signal level */ + kUSDHC_Data5LineLevelFlag = 1U << (USDHC_PRES_STATE_DLSL_SHIFT + 5U), /*!< Data5 line signal level */ + kUSDHC_Data6LineLevelFlag = 1U << (USDHC_PRES_STATE_DLSL_SHIFT + 6U), /*!< Data6 line signal level */ + kUSDHC_Data7LineLevelFlag = (int)(1U << (USDHC_PRES_STATE_DLSL_SHIFT + 7U)), /*!< Data7 line signal level */ +}; + +/*! @brief Interrupt status flag mask */ +enum _usdhc_interrupt_status_flag +{ + kUSDHC_CommandCompleteFlag = USDHC_INT_STATUS_CC_MASK, /*!< Command complete */ + kUSDHC_DataCompleteFlag = USDHC_INT_STATUS_TC_MASK, /*!< Data complete */ + kUSDHC_BlockGapEventFlag = USDHC_INT_STATUS_BGE_MASK, /*!< Block gap event */ + kUSDHC_DmaCompleteFlag = USDHC_INT_STATUS_DINT_MASK, /*!< DMA interrupt */ + kUSDHC_BufferWriteReadyFlag = USDHC_INT_STATUS_BWR_MASK, /*!< Buffer write ready */ + kUSDHC_BufferReadReadyFlag = USDHC_INT_STATUS_BRR_MASK, /*!< Buffer read ready */ + kUSDHC_CardInsertionFlag = USDHC_INT_STATUS_CINS_MASK, /*!< Card inserted */ + kUSDHC_CardRemovalFlag = USDHC_INT_STATUS_CRM_MASK, /*!< Card removed */ + kUSDHC_CardInterruptFlag = USDHC_INT_STATUS_CINT_MASK, /*!< Card interrupt */ + +#if defined(FSL_FEATURE_USDHC_HAS_SDR50_MODE) && (!FSL_FEATURE_USDHC_HAS_SDR50_MODE) + kUSDHC_ReTuningEventFlag = 0U, /*!< Re-Tuning event,only for SD3.0 SDR104 mode */ + kUSDHC_TuningPassFlag = 0U, /*!< SDR104 mode tuning pass flag */ + kUSDHC_TuningErrorFlag = 0U, /*!< SDR104 tuning error flag */ +#else + kUSDHC_ReTuningEventFlag = USDHC_INT_STATUS_RTE_MASK, /*!< Re-Tuning event,only for SD3.0 SDR104 mode */ + kUSDHC_TuningPassFlag = USDHC_INT_STATUS_TP_MASK, /*!< SDR104 mode tuning pass flag */ + kUSDHC_TuningErrorFlag = USDHC_INT_STATUS_TNE_MASK, /*!< SDR104 tuning error flag */ +#endif + + kUSDHC_CommandTimeoutFlag = USDHC_INT_STATUS_CTOE_MASK, /*!< Command timeout error */ + kUSDHC_CommandCrcErrorFlag = USDHC_INT_STATUS_CCE_MASK, /*!< Command CRC error */ + kUSDHC_CommandEndBitErrorFlag = USDHC_INT_STATUS_CEBE_MASK, /*!< Command end bit error */ + kUSDHC_CommandIndexErrorFlag = USDHC_INT_STATUS_CIE_MASK, /*!< Command index error */ + kUSDHC_DataTimeoutFlag = USDHC_INT_STATUS_DTOE_MASK, /*!< Data timeout error */ + kUSDHC_DataCrcErrorFlag = USDHC_INT_STATUS_DCE_MASK, /*!< Data CRC error */ + kUSDHC_DataEndBitErrorFlag = USDHC_INT_STATUS_DEBE_MASK, /*!< Data end bit error */ + kUSDHC_AutoCommand12ErrorFlag = USDHC_INT_STATUS_AC12E_MASK, /*!< Auto CMD12 error */ + kUSDHC_DmaErrorFlag = USDHC_INT_STATUS_DMAE_MASK, /*!< DMA error */ + + kUSDHC_CommandErrorFlag = (kUSDHC_CommandTimeoutFlag | kUSDHC_CommandCrcErrorFlag | kUSDHC_CommandEndBitErrorFlag | + kUSDHC_CommandIndexErrorFlag), /*!< Command error */ + kUSDHC_DataErrorFlag = (kUSDHC_DataTimeoutFlag | kUSDHC_DataCrcErrorFlag | kUSDHC_DataEndBitErrorFlag | + kUSDHC_AutoCommand12ErrorFlag), /*!< Data error */ + kUSDHC_ErrorFlag = (kUSDHC_CommandErrorFlag | kUSDHC_DataErrorFlag | kUSDHC_DmaErrorFlag), /*!< All error */ + kUSDHC_DataFlag = (kUSDHC_DataCompleteFlag | kUSDHC_DmaCompleteFlag | kUSDHC_BufferWriteReadyFlag | + kUSDHC_BufferReadReadyFlag | kUSDHC_DataErrorFlag | kUSDHC_DmaErrorFlag), /*!< Data interrupts */ + kUSDHC_CommandFlag = (kUSDHC_CommandErrorFlag | kUSDHC_CommandCompleteFlag), /*!< Command interrupts */ + kUSDHC_CardDetectFlag = (kUSDHC_CardInsertionFlag | kUSDHC_CardRemovalFlag), /*!< Card detection interrupts */ + kUSDHC_SDR104TuningFlag = (kUSDHC_TuningErrorFlag | kUSDHC_TuningPassFlag | kUSDHC_ReTuningEventFlag), + + kUSDHC_AllInterruptFlags = (kUSDHC_BlockGapEventFlag | kUSDHC_CardInterruptFlag | kUSDHC_CommandFlag | + kUSDHC_DataFlag | kUSDHC_ErrorFlag | kUSDHC_SDR104TuningFlag), /*!< All flags mask */ +}; + +/*! @brief Auto CMD12 error status flag mask */ +enum _usdhc_auto_command12_error_status_flag +{ + kUSDHC_AutoCommand12NotExecutedFlag = USDHC_AUTOCMD12_ERR_STATUS_AC12NE_MASK, /*!< Not executed error */ + kUSDHC_AutoCommand12TimeoutFlag = USDHC_AUTOCMD12_ERR_STATUS_AC12TOE_MASK, /*!< Timeout error */ + kUSDHC_AutoCommand12EndBitErrorFlag = USDHC_AUTOCMD12_ERR_STATUS_AC12EBE_MASK, /*!< End bit error */ + kUSDHC_AutoCommand12CrcErrorFlag = USDHC_AUTOCMD12_ERR_STATUS_AC12CE_MASK, /*!< CRC error */ + kUSDHC_AutoCommand12IndexErrorFlag = USDHC_AUTOCMD12_ERR_STATUS_AC12IE_MASK, /*!< Index error */ + kUSDHC_AutoCommand12NotIssuedFlag = USDHC_AUTOCMD12_ERR_STATUS_CNIBAC12E_MASK, /*!< Not issued error */ +}; + +/*! @brief standard tuning flag */ +enum _usdhc_standard_tuning +{ +#if defined(FSL_FEATURE_USDHC_HAS_SDR50_MODE) && (!FSL_FEATURE_USDHC_HAS_SDR50_MODE) + kUSDHC_ExecuteTuning = 0U, /*!< not support */ + kUSDHC_TuningSampleClockSel = 0U, /*!< not support */ +#else + kUSDHC_ExecuteTuning = USDHC_AUTOCMD12_ERR_STATUS_EXECUTE_TUNING_MASK, /*!< used to start tuning procedure */ + kUSDHC_TuningSampleClockSel = USDHC_AUTOCMD12_ERR_STATUS_SMP_CLK_SEL_MASK, /*!< when std_tuning_en bit is set, this + bit is used select sampleing clock */ +#endif +}; + +/*! @brief ADMA error status flag mask */ +enum _usdhc_adma_error_status_flag +{ + kUSDHC_AdmaLenghMismatchFlag = USDHC_ADMA_ERR_STATUS_ADMALME_MASK, /*!< Length mismatch error */ + kUSDHC_AdmaDescriptorErrorFlag = USDHC_ADMA_ERR_STATUS_ADMADCE_MASK, /*!< Descriptor error */ +}; + +/*! + * @brief ADMA error state + * + * This state is the detail state when ADMA error has occurred. + */ +enum _usdhc_adma_error_state +{ + kUSDHC_AdmaErrorStateStopDma = + 0x00U, /*!< Stop DMA, previous location set in the ADMA system address is error address */ + kUSDHC_AdmaErrorStateFetchDescriptor = + 0x01U, /*!< Fetch descriptor, current location set in the ADMA system address is error address */ + kUSDHC_AdmaErrorStateChangeAddress = 0x02U, /*!< Change address, no DMA error is occurred */ + kUSDHC_AdmaErrorStateTransferData = + 0x03U, /*!< Transfer data, previous location set in the ADMA system address is error address */ + kUSDHC_AdmaErrorStateInvalidLength = 0x04U, /*!< Invalid length in ADMA descriptor */ + kUSDHC_AdmaErrorStateInvalidDescriptor = 0x08U, /*!< Invalid descriptor fetched by ADMA */ + + kUSDHC_AdmaErrorState = kUSDHC_AdmaErrorStateInvalidLength | kUSDHC_AdmaErrorStateInvalidDescriptor | + kUSDHC_AdmaErrorStateFetchDescriptor, /*!< ADMA error state */ +}; + +/*! @brief Force event bit position */ +enum _usdhc_force_event +{ + kUSDHC_ForceEventAutoCommand12NotExecuted = USDHC_FORCE_EVENT_FEVTAC12NE_MASK, /*!< Auto CMD12 not executed error */ + kUSDHC_ForceEventAutoCommand12Timeout = USDHC_FORCE_EVENT_FEVTAC12TOE_MASK, /*!< Auto CMD12 timeout error */ + kUSDHC_ForceEventAutoCommand12CrcError = USDHC_FORCE_EVENT_FEVTAC12CE_MASK, /*!< Auto CMD12 CRC error */ + kUSDHC_ForceEventEndBitError = USDHC_FORCE_EVENT_FEVTAC12EBE_MASK, /*!< Auto CMD12 end bit error */ + kUSDHC_ForceEventAutoCommand12IndexError = USDHC_FORCE_EVENT_FEVTAC12IE_MASK, /*!< Auto CMD12 index error */ + kUSDHC_ForceEventAutoCommand12NotIssued = USDHC_FORCE_EVENT_FEVTCNIBAC12E_MASK, /*!< Auto CMD12 not issued error */ + kUSDHC_ForceEventCommandTimeout = USDHC_FORCE_EVENT_FEVTCTOE_MASK, /*!< Command timeout error */ + kUSDHC_ForceEventCommandCrcError = USDHC_FORCE_EVENT_FEVTCCE_MASK, /*!< Command CRC error */ + kUSDHC_ForceEventCommandEndBitError = USDHC_FORCE_EVENT_FEVTCEBE_MASK, /*!< Command end bit error */ + kUSDHC_ForceEventCommandIndexError = USDHC_FORCE_EVENT_FEVTCIE_MASK, /*!< Command index error */ + kUSDHC_ForceEventDataTimeout = USDHC_FORCE_EVENT_FEVTDTOE_MASK, /*!< Data timeout error */ + kUSDHC_ForceEventDataCrcError = USDHC_FORCE_EVENT_FEVTDCE_MASK, /*!< Data CRC error */ + kUSDHC_ForceEventDataEndBitError = USDHC_FORCE_EVENT_FEVTDEBE_MASK, /*!< Data end bit error */ + kUSDHC_ForceEventAutoCommand12Error = USDHC_FORCE_EVENT_FEVTAC12E_MASK, /*!< Auto CMD12 error */ + kUSDHC_ForceEventCardInt = (int)USDHC_FORCE_EVENT_FEVTCINT_MASK, /*!< Card interrupt */ + kUSDHC_ForceEventDmaError = USDHC_FORCE_EVENT_FEVTDMAE_MASK, /*!< Dma error */ +#if defined(FSL_FEATURE_USDHC_HAS_SDR50_MODE) && (!FSL_FEATURE_USDHC_HAS_SDR50_MODE) + kUSDHC_ForceEventTuningError = 0U, /*!< not support */ +#else + kUSDHC_ForceEventTuningError = USDHC_FORCE_EVENT_FEVTTNE_MASK, /*!< Tuning error */ +#endif + + kUSDHC_ForceEventsAll = + (int)(USDHC_FORCE_EVENT_FEVTAC12NE_MASK | USDHC_FORCE_EVENT_FEVTAC12TOE_MASK | + USDHC_FORCE_EVENT_FEVTAC12CE_MASK | USDHC_FORCE_EVENT_FEVTAC12EBE_MASK | + USDHC_FORCE_EVENT_FEVTAC12IE_MASK | USDHC_FORCE_EVENT_FEVTCNIBAC12E_MASK | + USDHC_FORCE_EVENT_FEVTCTOE_MASK | USDHC_FORCE_EVENT_FEVTCCE_MASK | USDHC_FORCE_EVENT_FEVTCEBE_MASK | + USDHC_FORCE_EVENT_FEVTCIE_MASK | USDHC_FORCE_EVENT_FEVTDTOE_MASK | USDHC_FORCE_EVENT_FEVTDCE_MASK | + USDHC_FORCE_EVENT_FEVTDEBE_MASK | USDHC_FORCE_EVENT_FEVTAC12E_MASK | USDHC_FORCE_EVENT_FEVTCINT_MASK | + USDHC_FORCE_EVENT_FEVTDMAE_MASK | kUSDHC_ForceEventTuningError), /*!< All force event flags mask */ +}; + +/*! @brief Data transfer width */ +typedef enum _usdhc_data_bus_width +{ + kUSDHC_DataBusWidth1Bit = 0U, /*!< 1-bit mode */ + kUSDHC_DataBusWidth4Bit = 1U, /*!< 4-bit mode */ + kUSDHC_DataBusWidth8Bit = 2U, /*!< 8-bit mode */ +} usdhc_data_bus_width_t; + +/*! @brief Endian mode */ +typedef enum _usdhc_endian_mode +{ + kUSDHC_EndianModeBig = 0U, /*!< Big endian mode */ + kUSDHC_EndianModeHalfWordBig = 1U, /*!< Half word big endian mode */ + kUSDHC_EndianModeLittle = 2U, /*!< Little endian mode */ +} usdhc_endian_mode_t; + +/*! @brief DMA mode */ +typedef enum _usdhc_dma_mode +{ + kUSDHC_DmaModeSimple = 0U, /*!< external DMA */ + kUSDHC_DmaModeAdma1 = 1U, /*!< ADMA1 is selected */ + kUSDHC_DmaModeAdma2 = 2U, /*!< ADMA2 is selected */ + kUSDHC_ExternalDMA = 3U, /*!< external dma mode select */ +} usdhc_dma_mode_t; + +/*! @brief SDIO control flag mask */ +enum _usdhc_sdio_control_flag +{ + kUSDHC_StopAtBlockGapFlag = USDHC_PROT_CTRL_SABGREQ_MASK, /*!< Stop at block gap */ + kUSDHC_ReadWaitControlFlag = USDHC_PROT_CTRL_RWCTL_MASK, /*!< Read wait control */ + kUSDHC_InterruptAtBlockGapFlag = USDHC_PROT_CTRL_IABG_MASK, /*!< Interrupt at block gap */ + kUSDHC_ReadDoneNo8CLK = USDHC_PROT_CTRL_RD_DONE_NO_8CLK_MASK, /*!< read done without 8 clk for block gap */ + kUSDHC_ExactBlockNumberReadFlag = USDHC_PROT_CTRL_NON_EXACT_BLK_RD_MASK, /*!< Exact block number read */ +}; + +/*! @brief MMC card boot mode */ +typedef enum _usdhc_boot_mode +{ + kUSDHC_BootModeNormal = 0U, /*!< Normal boot */ + kUSDHC_BootModeAlternative = 1U, /*!< Alternative boot */ +} usdhc_boot_mode_t; + +/*! @brief The command type */ +typedef enum _usdhc_card_command_type +{ + kCARD_CommandTypeNormal = 0U, /*!< Normal command */ + kCARD_CommandTypeSuspend = 1U, /*!< Suspend command */ + kCARD_CommandTypeResume = 2U, /*!< Resume command */ + kCARD_CommandTypeAbort = 3U, /*!< Abort command */ + kCARD_CommandTypeEmpty = 4U, /*!< Empty command */ +} usdhc_card_command_type_t; + +/*! + * @brief The command response type. + * + * Define the command response type from card to host controller. + */ +typedef enum _usdhc_card_response_type +{ + kCARD_ResponseTypeNone = 0U, /*!< Response type: none */ + kCARD_ResponseTypeR1 = 1U, /*!< Response type: R1 */ + kCARD_ResponseTypeR1b = 2U, /*!< Response type: R1b */ + kCARD_ResponseTypeR2 = 3U, /*!< Response type: R2 */ + kCARD_ResponseTypeR3 = 4U, /*!< Response type: R3 */ + kCARD_ResponseTypeR4 = 5U, /*!< Response type: R4 */ + kCARD_ResponseTypeR5 = 6U, /*!< Response type: R5 */ + kCARD_ResponseTypeR5b = 7U, /*!< Response type: R5b */ + kCARD_ResponseTypeR6 = 8U, /*!< Response type: R6 */ + kCARD_ResponseTypeR7 = 9U, /*!< Response type: R7 */ +} usdhc_card_response_type_t; + +/*! @brief The alignment size for ADDRESS filed in ADMA1's descriptor */ +#define USDHC_ADMA1_ADDRESS_ALIGN (4096U) +/*! @brief The alignment size for LENGTH field in ADMA1's descriptor */ +#define USDHC_ADMA1_LENGTH_ALIGN (4096U) +/*! @brief The alignment size for ADDRESS field in ADMA2's descriptor */ +#define USDHC_ADMA2_ADDRESS_ALIGN (4U) +/*! @brief The alignment size for LENGTH filed in ADMA2's descriptor */ +#define USDHC_ADMA2_LENGTH_ALIGN (4U) + +/* ADMA1 descriptor table + * |------------------------|---------|--------------------------| + * | Address/page field |Reserved | Attribute | + * |------------------------|---------|--------------------------| + * |31 12|11 6|05 |04 |03|02 |01 |00 | + * |------------------------|---------|----|----|--|---|---|-----| + * | address or data length | 000000 |Act2|Act1| 0|Int|End|Valid| + * |------------------------|---------|----|----|--|---|---|-----| + * + * + * |------|------|-----------------|-------|-------------| + * | Act2 | Act1 | Comment | 31-28 | 27 - 12 | + * |------|------|-----------------|---------------------| + * | 0 | 0 | No op | Don't care | + * |------|------|-----------------|-------|-------------| + * | 0 | 1 | Set data length | 0000 | Data Length | + * |------|------|-----------------|-------|-------------| + * | 1 | 0 | Transfer data | Data address | + * |------|------|-----------------|---------------------| + * | 1 | 1 | Link descriptor | Descriptor address | + * |------|------|-----------------|---------------------| + */ +/*! @brief The bit shift for ADDRESS filed in ADMA1's descriptor */ +#define USDHC_ADMA1_DESCRIPTOR_ADDRESS_SHIFT (12U) +/*! @brief The bit mask for ADDRESS field in ADMA1's descriptor */ +#define USDHC_ADMA1_DESCRIPTOR_ADDRESS_MASK (0xFFFFFU) +/*! @brief The bit shift for LENGTH filed in ADMA1's descriptor */ +#define USDHC_ADMA1_DESCRIPTOR_LENGTH_SHIFT (12U) +/*! @brief The mask for LENGTH field in ADMA1's descriptor */ +#define USDHC_ADMA1_DESCRIPTOR_LENGTH_MASK (0xFFFFU) +/*! @brief The maximum value of LENGTH filed in ADMA1's descriptor + * Since the ADMA1 support max transfer size is 65535 which is not divisible by + * 4096, so to make sure a large data load transfer(>64KB) continuously(require the data + * address should be alwawys align with 4096), software will set the maximum data length + * for ADMA1 to (64 - 4)KB. + */ +#define USDHC_ADMA1_DESCRIPTOR_MAX_LENGTH_PER_ENTRY (USDHC_ADMA1_DESCRIPTOR_LENGTH_MASK + 1U - 4096U) + +/*! @brief The mask for the control/status field in ADMA1 descriptor */ +enum _usdhc_adma1_descriptor_flag +{ + kUSDHC_Adma1DescriptorValidFlag = (1U << 0U), /*!< Valid flag */ + kUSDHC_Adma1DescriptorEndFlag = (1U << 1U), /*!< End flag */ + kUSDHC_Adma1DescriptorInterrupFlag = (1U << 2U), /*!< Interrupt flag */ + kUSDHC_Adma1DescriptorActivity1Flag = (1U << 4U), /*!< Activity 1 flag */ + kUSDHC_Adma1DescriptorActivity2Flag = (1U << 5U), /*!< Activity 2 flag */ + kUSDHC_Adma1DescriptorTypeNop = (kUSDHC_Adma1DescriptorValidFlag), /*!< No operation */ + kUSDHC_Adma1DescriptorTypeTransfer = + (kUSDHC_Adma1DescriptorActivity2Flag | kUSDHC_Adma1DescriptorValidFlag), /*!< Transfer data */ + kUSDHC_Adma1DescriptorTypeLink = (kUSDHC_Adma1DescriptorActivity1Flag | kUSDHC_Adma1DescriptorActivity2Flag | + kUSDHC_Adma1DescriptorValidFlag), /*!< Link descriptor */ + kUSDHC_Adma1DescriptorTypeSetLength = + (kUSDHC_Adma1DescriptorActivity1Flag | kUSDHC_Adma1DescriptorValidFlag), /*!< Set data length */ +}; + +/* ADMA2 descriptor table + * |----------------|---------------|-------------|--------------------------| + * | Address field | Length | Reserved | Attribute | + * |----------------|---------------|-------------|--------------------------| + * |63 32|31 16|15 06|05 |04 |03|02 |01 |00 | + * |----------------|---------------|-------------|----|----|--|---|---|-----| + * | 32-bit address | 16-bit length | 0000000000 |Act2|Act1| 0|Int|End|Valid| + * |----------------|---------------|-------------|----|----|--|---|---|-----| + * + * + * | Act2 | Act1 | Comment | Operation | + * |------|------|-----------------|-------------------------------------------------------------------| + * | 0 | 0 | No op | Don't care | + * |------|------|-----------------|-------------------------------------------------------------------| + * | 0 | 1 | Reserved | Read this line and go to next one | + * |------|------|-----------------|-------------------------------------------------------------------| + * | 1 | 0 | Transfer data | Transfer data with address and length set in this descriptor line | + * |------|------|-----------------|-------------------------------------------------------------------| + * | 1 | 1 | Link descriptor | Link to another descriptor | + * |------|------|-----------------|-------------------------------------------------------------------| + */ +/*! @brief The bit shift for LENGTH field in ADMA2's descriptor */ +#define USDHC_ADMA2_DESCRIPTOR_LENGTH_SHIFT (16U) +/*! @brief The bit mask for LENGTH field in ADMA2's descriptor */ +#define USDHC_ADMA2_DESCRIPTOR_LENGTH_MASK (0xFFFFU) +/*! @brief The maximum value of LENGTH field in ADMA2's descriptor */ +#define USDHC_ADMA2_DESCRIPTOR_MAX_LENGTH_PER_ENTRY (USDHC_ADMA2_DESCRIPTOR_LENGTH_MASK - 3U) + +/*! @brief ADMA1 descriptor control and status mask */ +enum _usdhc_adma2_descriptor_flag +{ + kUSDHC_Adma2DescriptorValidFlag = (1U << 0U), /*!< Valid flag */ + kUSDHC_Adma2DescriptorEndFlag = (1U << 1U), /*!< End flag */ + kUSDHC_Adma2DescriptorInterruptFlag = (1U << 2U), /*!< Interrupt flag */ + kUSDHC_Adma2DescriptorActivity1Flag = (1U << 4U), /*!< Activity 1 mask */ + kUSDHC_Adma2DescriptorActivity2Flag = (1U << 5U), /*!< Activity 2 mask */ + + kUSDHC_Adma2DescriptorTypeNop = (kUSDHC_Adma2DescriptorValidFlag), /*!< No operation */ + kUSDHC_Adma2DescriptorTypeReserved = + (kUSDHC_Adma2DescriptorActivity1Flag | kUSDHC_Adma2DescriptorValidFlag), /*!< Reserved */ + kUSDHC_Adma2DescriptorTypeTransfer = + (kUSDHC_Adma2DescriptorActivity2Flag | kUSDHC_Adma2DescriptorValidFlag), /*!< Transfer type */ + kUSDHC_Adma2DescriptorTypeLink = (kUSDHC_Adma2DescriptorActivity1Flag | kUSDHC_Adma2DescriptorActivity2Flag | + kUSDHC_Adma2DescriptorValidFlag), /*!< Link type */ +}; + +/*! @brief ADMA descriptor configuration flag */ +enum _usdhc_adma_flag +{ + kUSDHC_AdmaDescriptorSingleFlag = + 0U, /*!< try to finish the transfer in a single ADMA descriptor, if transfer size is bigger than one + ADMA descriptor's ability, new another descriptor for data transfer */ + kUSDHC_AdmaDescriptorMultipleFlag = 1U, /*!< create multiple ADMA descriptor within the ADMA table, this is used for + mmc boot mode specifically, which need + to modify the ADMA descriptor on the fly, so the flag should be used + combine with stop at block gap feature */ +}; + +/*! @brief dma transfer burst len config. */ +typedef enum _usdhc_burst_len +{ + kUSDHC_EnBurstLenForINCR = 0x01U, /*!< enable burst len for INCR */ + kUSDHC_EnBurstLenForINCR4816 = 0x02U, /*!< enable burst len for INCR4/INCR8/INCR16 */ + kUSDHC_EnBurstLenForINCR4816WRAP = 0x04U, /*!< enable burst len for INCR4/8/16 WRAP */ +} usdhc_burst_len_t; + +/*! @brief transfer data type definition. */ +enum _usdhc_transfer_data_type +{ + kUSDHC_TransferDataNormal = 0U, /*!< transfer normal read/write data */ + kUSDHC_TransferDataTuning = 1U, /*!< transfer tuning data */ + kUSDHC_TransferDataBoot = 2U, /*!< transfer boot data */ + kUSDHC_TransferDataBootcontinous = 3U, /*!< transfer boot data continous */ +}; + +/*! @brief Defines the adma1 descriptor structure. */ +typedef uint32_t usdhc_adma1_descriptor_t; + +/*! @brief Defines the ADMA2 descriptor structure. */ +typedef struct _usdhc_adma2_descriptor +{ + uint32_t attribute; /*!< The control and status field */ + const uint32_t *address; /*!< The address field */ +} usdhc_adma2_descriptor_t; + +/*! + * @brief USDHC capability information. + * + * Defines a structure to save the capability information of USDHC. + */ +typedef struct _usdhc_capability +{ + uint32_t sdVersion; /*!< support SD card/sdio version */ + uint32_t mmcVersion; /*!< support emmc card version */ + uint32_t maxBlockLength; /*!< Maximum block length united as byte */ + uint32_t maxBlockCount; /*!< Maximum block count can be set one time */ + uint32_t flags; /*!< Capability flags to indicate the support information(_usdhc_capability_flag) */ +} usdhc_capability_t; + +/*! @brief Data structure to configure the MMC boot feature */ +typedef struct _usdhc_boot_config +{ + uint32_t ackTimeoutCount; /*!< Timeout value for the boot ACK. The available range is 0 ~ 15. */ + usdhc_boot_mode_t bootMode; /*!< Boot mode selection. */ + uint32_t blockCount; /*!< Stop at block gap value of automatic mode. Available range is 0 ~ 65535. */ + size_t blockSize; /*!< Block size */ + bool enableBootAck; /*!< Enable or disable boot ACK */ + bool enableAutoStopAtBlockGap; /*!< Enable or disable auto stop at block gap function in boot period */ +} usdhc_boot_config_t; + +/*! @brief Data structure to initialize the USDHC */ +typedef struct _usdhc_config +{ + uint32_t dataTimeout; /*!< Data timeout value */ + usdhc_endian_mode_t endianMode; /*!< Endian mode */ + uint8_t readWatermarkLevel; /*!< Watermark level for DMA read operation. Available range is 1 ~ 128. */ + uint8_t writeWatermarkLevel; /*!< Watermark level for DMA write operation. Available range is 1 ~ 128. */ + uint8_t readBurstLen; /*!< Read burst len */ + uint8_t writeBurstLen; /*!< Write burst len */ +} usdhc_config_t; + +/*! + * @brief Card data descriptor + * + * Defines a structure to contain data-related attribute. 'enableIgnoreError' is used for the case that upper card + * driver + * want to ignore the error event to read/write all the data not to stop read/write immediately when error event + * happen for example bus testing procedure for MMC card. + */ +typedef struct _usdhc_data +{ + bool enableAutoCommand12; /*!< Enable auto CMD12 */ + bool enableAutoCommand23; /*!< Enable auto CMD23 */ + bool enableIgnoreError; /*!< Enable to ignore error event to read/write all the data */ + uint8_t dataType; /*!< this is used to distinguish the normal/tuning/boot data */ + size_t blockSize; /*!< Block size */ + uint32_t blockCount; /*!< Block count */ + uint32_t *rxData; /*!< Buffer to save data read */ + const uint32_t *txData; /*!< Data buffer to write */ +} usdhc_data_t; + +/*! + * @brief Card command descriptor + * + * Define card command-related attribute. + */ +typedef struct _usdhc_command +{ + uint32_t index; /*!< Command index */ + uint32_t argument; /*!< Command argument */ + usdhc_card_command_type_t type; /*!< Command type */ + usdhc_card_response_type_t responseType; /*!< Command response type */ + uint32_t response[4U]; /*!< Response for this command */ + uint32_t responseErrorFlags; /*!< response error flag, the flag which need to check + the command reponse*/ + uint32_t flags; /*!< Cmd flags */ +} usdhc_command_t; + +/*! @brief ADMA configuration */ +typedef struct _usdhc_adma_config +{ + usdhc_dma_mode_t dmaMode; /*!< DMA mode */ + + usdhc_burst_len_t burstLen; /*!< burst len config */ + + uint32_t *admaTable; /*!< ADMA table address, can't be null if transfer way is ADMA1/ADMA2 */ + uint32_t admaTableWords; /*!< ADMA table length united as words, can't be 0 if transfer way is ADMA1/ADMA2 */ +} usdhc_adma_config_t; + +/*! @brief Transfer state */ +typedef struct _usdhc_transfer +{ + usdhc_data_t *data; /*!< Data to transfer */ + usdhc_command_t *command; /*!< Command to send */ +} usdhc_transfer_t; + +/*! @brief USDHC handle typedef */ +typedef struct _usdhc_handle usdhc_handle_t; + +/*! @brief USDHC callback functions. */ +typedef struct _usdhc_transfer_callback +{ + void (*CardInserted)(USDHC_Type *base, + void *userData); /*!< Card inserted occurs when DAT3/CD pin is for card detect */ + void (*CardRemoved)(USDHC_Type *base, void *userData); /*!< Card removed occurs */ + void (*SdioInterrupt)(USDHC_Type *base, void *userData); /*!< SDIO card interrupt occurs */ + void (*BlockGap)(USDHC_Type *base, void *userData); /*!< stopped at block gap event */ + void (*TransferComplete)(USDHC_Type *base, + usdhc_handle_t *handle, + status_t status, + void *userData); /*!< Transfer complete callback */ + void (*ReTuning)(USDHC_Type *base, void *userData); /*!< handle the re-tuning */ +} usdhc_transfer_callback_t; + +/*! + * @brief USDHC handle + * + * Defines the structure to save the USDHC state information and callback function. The detailed interrupt status when + * sending a command or transfering data can be obtained from the interruptFlags field by using the mask defined in + * usdhc_interrupt_flag_t. + * + * @note All the fields except interruptFlags and transferredWords must be allocated by the user. + */ +struct _usdhc_handle +{ + /* Transfer parameter */ + usdhc_data_t *volatile data; /*!< Data to transfer */ + usdhc_command_t *volatile command; /*!< Command to send */ + + /* Transfer status */ + volatile uint32_t transferredWords; /*!< Words transferred by DATAPORT way */ + + /* Callback functions */ + usdhc_transfer_callback_t callback; /*!< Callback function */ + void *userData; /*!< Parameter for transfer complete callback */ +}; + +/*! @brief USDHC transfer function. */ +typedef status_t (*usdhc_transfer_function_t)(USDHC_Type *base, usdhc_transfer_t *content); + +/*! @brief USDHC host descriptor */ +typedef struct _usdhc_host +{ + USDHC_Type *base; /*!< USDHC peripheral base address */ + uint32_t sourceClock_Hz; /*!< USDHC source clock frequency united in Hz */ + usdhc_config_t config; /*!< USDHC configuration */ + usdhc_capability_t capability; /*!< USDHC capability information */ + usdhc_transfer_function_t transfer; /*!< USDHC transfer function */ +} usdhc_host_t; + +/************************************************************************************************* + * API + ************************************************************************************************/ +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @name Initialization and deinitialization + * @{ + */ + +/*! + * @brief USDHC module initialization function. + * + * Configures the USDHC according to the user configuration. + * + * Example: + @code + usdhc_config_t config; + config.cardDetectDat3 = false; + config.endianMode = kUSDHC_EndianModeLittle; + config.dmaMode = kUSDHC_DmaModeAdma2; + config.readWatermarkLevel = 128U; + config.writeWatermarkLevel = 128U; + USDHC_Init(USDHC, &config); + @endcode + * + * @param base USDHC peripheral base address. + * @param config USDHC configuration information. + * @retval kStatus_Success Operate successfully. + */ +void USDHC_Init(USDHC_Type *base, const usdhc_config_t *config); + +/*! + * @brief Deinitializes the USDHC. + * + * @param base USDHC peripheral base address. + */ +void USDHC_Deinit(USDHC_Type *base); + +/*! + * @brief Resets the USDHC. + * + * @param base USDHC peripheral base address. + * @param mask The reset type mask(_usdhc_reset). + * @param timeout Timeout for reset. + * @retval true Reset successfully. + * @retval false Reset failed. + */ +bool USDHC_Reset(USDHC_Type *base, uint32_t mask, uint32_t timeout); + +/* @} */ + +/*! + * @name DMA Control + * @{ + */ + +/*! + * @brief Sets the DMA descriptor table configuration. + * A high level DMA descriptor configuration function. + * @param base USDHC peripheral base address. + * @param adma configuration + * @param data Data descriptor + * @param flags ADAM descriptor flag, used to indicate to create multiple or single descriptor, please + * reference _usdhc_adma_flag + * @retval kStatus_OutOfRange ADMA descriptor table length isn't enough to describe data. + * @retval kStatus_Success Operate successfully. + */ +status_t USDHC_SetAdmaTableConfig(USDHC_Type *base, + usdhc_adma_config_t *dmaConfig, + usdhc_data_t *dataConfig, + uint32_t flags); + +/*! + * @brief Internal DMA configuration. + * This function is used to config the USDHC DMA related registers. + * @param base USDHC peripheral base address. + * @param adma configuration + * @param dataAddr transfer data address, a simple DMA parameter, if ADMA is used, leave it to NULL. + * @param enAutoCmd23 flag to indicate Auto CMD23 is enable or not, a simple DMA parameter,if ADMA is used, leave it + * to false. + * @retval kStatus_OutOfRange ADMA descriptor table length isn't enough to describe data. + * @retval kStatus_Success Operate successfully. + */ +status_t USDHC_SetInternalDmaConfig(USDHC_Type *base, + usdhc_adma_config_t *dmaConfig, + const uint32_t *dataAddr, + bool enAutoCmd23); + +/*! + * @brief Sets the ADMA2 descriptor table configuration. + * + * @param admaTable Adma table address. + * @param admaTableWords Adma table length. + * @param dataBufferAddr Data buffer address. + * @param dataBytes Data Data length. + * @param flags ADAM descriptor flag, used to indicate to create multiple or single descriptor, please + * reference _usdhc_adma_flag. + * @retval kStatus_OutOfRange ADMA descriptor table length isn't enough to describe data. + * @retval kStatus_Success Operate successfully. + */ +status_t USDHC_SetADMA2Descriptor( + uint32_t *admaTable, uint32_t admaTableWords, const uint32_t *dataBufferAddr, uint32_t dataBytes, uint32_t flags); + +/*! + * @brief Sets the ADMA1 descriptor table configuration. + * + * @param admaTable Adma table address. + * @param admaTableWords Adma table length. + * @param dataBufferAddr Data buffer address. + * @param dataBytes Data length. + * @param flags ADAM descriptor flag, used to indicate to create multiple or single descriptor, please + * reference _usdhc_adma_flag. + * @retval kStatus_OutOfRange ADMA descriptor table length isn't enough to describe data. + * @retval kStatus_Success Operate successfully. + */ +status_t USDHC_SetADMA1Descriptor( + uint32_t *admaTable, uint32_t admaTableWords, const uint32_t *dataBufferAddr, uint32_t dataBytes, uint32_t flags); + +/*! + * @brief enable internal DMA. + * + * @param base USDHC peripheral base address. + * @param enable enable or disable flag + */ +static inline void USDHC_EnableInternalDMA(USDHC_Type *base, bool enable) +{ + if (enable) + { + base->MIX_CTRL |= USDHC_MIX_CTRL_DMAEN_MASK; + } + else + { + base->MIX_CTRL &= ~USDHC_MIX_CTRL_DMAEN_MASK; + base->PROT_CTRL &= ~USDHC_PROT_CTRL_DMASEL_MASK; + } +} + +/* @} */ + +/*! + * @name Interrupts + * @{ + */ + +/*! + * @brief Enables the interrupt status. + * + * @param base USDHC peripheral base address. + * @param mask Interrupt status flags mask(_usdhc_interrupt_status_flag). + */ +static inline void USDHC_EnableInterruptStatus(USDHC_Type *base, uint32_t mask) +{ + base->INT_STATUS_EN |= mask; +} + +/*! + * @brief Disables the interrupt status. + * + * @param base USDHC peripheral base address. + * @param mask The interrupt status flags mask(_usdhc_interrupt_status_flag). + */ +static inline void USDHC_DisableInterruptStatus(USDHC_Type *base, uint32_t mask) +{ + base->INT_STATUS_EN &= ~mask; +} + +/*! + * @brief Enables the interrupt signal corresponding to the interrupt status flag. + * + * @param base USDHC peripheral base address. + * @param mask The interrupt status flags mask(_usdhc_interrupt_status_flag). + */ +static inline void USDHC_EnableInterruptSignal(USDHC_Type *base, uint32_t mask) +{ + base->INT_SIGNAL_EN |= mask; +} + +/*! + * @brief Disables the interrupt signal corresponding to the interrupt status flag. + * + * @param base USDHC peripheral base address. + * @param mask The interrupt status flags mask(_usdhc_interrupt_status_flag). + */ +static inline void USDHC_DisableInterruptSignal(USDHC_Type *base, uint32_t mask) +{ + base->INT_SIGNAL_EN &= ~mask; +} + +/* @} */ + +/*! + * @name Status + * @{ + */ + +/*! + * @brief Gets the enabled interrupt status. + * + * @param base USDHC peripheral base address. + * @return Current interrupt status flags mask(_usdhc_interrupt_status_flag). + */ +static inline uint32_t USDHC_GetEnabledInterruptStatusFlags(USDHC_Type *base) +{ + return (base->INT_STATUS) & (base->INT_SIGNAL_EN); +} + +/*! + * @brief Gets the current interrupt status. + * + * @param base USDHC peripheral base address. + * @return Current interrupt status flags mask(_usdhc_interrupt_status_flag). + */ +static inline uint32_t USDHC_GetInterruptStatusFlags(USDHC_Type *base) +{ + return base->INT_STATUS; +} + +/*! + * @brief Clears a specified interrupt status. + * write 1 clears + * @param base USDHC peripheral base address. + * @param mask The interrupt status flags mask(_usdhc_interrupt_status_flag). + */ +static inline void USDHC_ClearInterruptStatusFlags(USDHC_Type *base, uint32_t mask) +{ + base->INT_STATUS = mask; +} + +/*! + * @brief Gets the status of auto command 12 error. + * + * @param base USDHC peripheral base address. + * @return Auto command 12 error status flags mask(_usdhc_auto_command12_error_status_flag). + */ +static inline uint32_t USDHC_GetAutoCommand12ErrorStatusFlags(USDHC_Type *base) +{ + return base->AUTOCMD12_ERR_STATUS; +} + +/*! + * @brief Gets the status of the ADMA error. + * + * @param base USDHC peripheral base address. + * @return ADMA error status flags mask(_usdhc_adma_error_status_flag). + */ +static inline uint32_t USDHC_GetAdmaErrorStatusFlags(USDHC_Type *base) +{ + return base->ADMA_ERR_STATUS & 0xFU; +} + +/*! + * @brief Gets a present status. + * + * This function gets the present USDHC's status except for an interrupt status and an error status. + * + * @param base USDHC peripheral base address. + * @return Present USDHC's status flags mask(_usdhc_present_status_flag). + */ +static inline uint32_t USDHC_GetPresentStatusFlags(USDHC_Type *base) +{ + return base->PRES_STATE; +} + +/* @} */ + +/*! + * @name Bus Operations + * @{ + */ + +/*! + * @brief Gets the capability information. + * + * @param base USDHC peripheral base address. + * @param capability Structure to save capability information. + */ +void USDHC_GetCapability(USDHC_Type *base, usdhc_capability_t *capability); + +/*! + * @brief force the card clock on. + * + * @param base USDHC peripheral base address. + * @param enable/disable flag. + */ +static inline void USDHC_ForceClockOn(USDHC_Type *base, bool enable) +{ + if (enable) + { + base->VEND_SPEC |= USDHC_VEND_SPEC_FRC_SDCLK_ON_MASK; + } + else + { + base->VEND_SPEC &= ~USDHC_VEND_SPEC_FRC_SDCLK_ON_MASK; + } +} + +/*! + * @brief Sets the SD bus clock frequency. + * + * @param base USDHC peripheral base address. + * @param srcClock_Hz USDHC source clock frequency united in Hz. + * @param busClock_Hz SD bus clock frequency united in Hz. + * + * @return The nearest frequency of busClock_Hz configured to SD bus. + */ +uint32_t USDHC_SetSdClock(USDHC_Type *base, uint32_t srcClock_Hz, uint32_t busClock_Hz); + +/*! + * @brief Sends 80 clocks to the card to set it to the active state. + * + * This function must be called each time the card is inserted to ensure that the card can receive the command + * correctly. + * + * @param base USDHC peripheral base address. + * @param timeout Timeout to initialize card. + * @retval true Set card active successfully. + * @retval false Set card active failed. + */ +bool USDHC_SetCardActive(USDHC_Type *base, uint32_t timeout); + +/*! + * @brief trigger a hardware reset. + * + * @param base USDHC peripheral base address. + * @param 1 or 0 level + */ +static inline void USDHC_AssertHardwareReset(USDHC_Type *base, bool high) +{ + if (high) + { + base->SYS_CTRL |= USDHC_SYS_CTRL_IPP_RST_N_MASK; + } + else + { + base->SYS_CTRL &= ~USDHC_SYS_CTRL_IPP_RST_N_MASK; + } +} + +/*! + * @brief Sets the data transfer width. + * + * @param base USDHC peripheral base address. + * @param width Data transfer width. + */ +static inline void USDHC_SetDataBusWidth(USDHC_Type *base, usdhc_data_bus_width_t width) +{ + base->PROT_CTRL = ((base->PROT_CTRL & ~USDHC_PROT_CTRL_DTW_MASK) | USDHC_PROT_CTRL_DTW(width)); +} + +/*! + * @brief Fills the data port. + * + * This function is used to implement the data transfer by Data Port instead of DMA. + * + * @param base USDHC peripheral base address. + * @param data The data about to be sent. + */ +static inline void USDHC_WriteData(USDHC_Type *base, uint32_t data) +{ + base->DATA_BUFF_ACC_PORT = data; +} + +/*! + * @brief Retrieves the data from the data port. + * + * This function is used to implement the data transfer by Data Port instead of DMA. + * + * @param base USDHC peripheral base address. + * @return The data has been read. + */ +static inline uint32_t USDHC_ReadData(USDHC_Type *base) +{ + return base->DATA_BUFF_ACC_PORT; +} + +/*! + * @brief send command function + * + * @param base USDHC peripheral base address. + * @param command configuration + */ +void USDHC_SendCommand(USDHC_Type *base, usdhc_command_t *command); + +/*! + * @brief Enables or disables a wakeup event in low-power mode. + * + * @param base USDHC peripheral base address. + * @param mask Wakeup events mask(_usdhc_wakeup_event). + * @param enable True to enable, false to disable. + */ +static inline void USDHC_EnableWakeupEvent(USDHC_Type *base, uint32_t mask, bool enable) +{ + if (enable) + { + base->PROT_CTRL |= mask; + } + else + { + base->PROT_CTRL &= ~mask; + } +} + +/*! + * @brief detect card insert status. + * + * @param base USDHC peripheral base address. + * @param enable/disable flag + */ +static inline void USDHC_CardDetectByData3(USDHC_Type *base, bool enable) +{ + if (enable) + { + base->PROT_CTRL |= USDHC_PROT_CTRL_D3CD_MASK; + } + else + { + base->PROT_CTRL &= ~USDHC_PROT_CTRL_D3CD_MASK; + } +} + +/*! + * @brief detect card insert status. + * + * @param base USDHC peripheral base address. + */ +static inline bool USDHC_DetectCardInsert(USDHC_Type *base) +{ + return (base->PRES_STATE & kUSDHC_CardInsertedFlag) ? true : false; +} + +/*! + * @brief Enables or disables the SDIO card control. + * + * @param base USDHC peripheral base address. + * @param mask SDIO card control flags mask(_usdhc_sdio_control_flag). + * @param enable True to enable, false to disable. + */ +static inline void USDHC_EnableSdioControl(USDHC_Type *base, uint32_t mask, bool enable) +{ + if (enable) + { + base->PROT_CTRL |= mask; + } + else + { + base->PROT_CTRL &= ~mask; + } +} + +/*! + * @brief Restarts a transaction which has stopped at the block GAP for the SDIO card. + * + * @param base USDHC peripheral base address. + */ +static inline void USDHC_SetContinueRequest(USDHC_Type *base) +{ + base->PROT_CTRL |= USDHC_PROT_CTRL_CREQ_MASK; +} + +/*! + * @brief Request stop at block gap function. + * + * @param base USDHC peripheral base address. + * @param enable true to stop at block gap, false to normal transfer + */ +static inline void USDHC_RequestStopAtBlockGap(USDHC_Type *base, bool enable) +{ + if (enable) + { + base->PROT_CTRL |= USDHC_PROT_CTRL_SABGREQ_MASK; + } + else + { + base->PROT_CTRL &= ~USDHC_PROT_CTRL_SABGREQ_MASK; + } +} + +/*! + * @brief Configures the MMC boot feature. + * + * Example: + @code + usdhc_boot_config_t config; + config.ackTimeoutCount = 4; + config.bootMode = kUSDHC_BootModeNormal; + config.blockCount = 5; + config.enableBootAck = true; + config.enableBoot = true; + config.enableAutoStopAtBlockGap = true; + USDHC_SetMmcBootConfig(USDHC, &config); + @endcode + * + * @param base USDHC peripheral base address. + * @param config The MMC boot configuration information. + */ +void USDHC_SetMmcBootConfig(USDHC_Type *base, const usdhc_boot_config_t *config); + +/*! + * @brief Enables or disables the mmc boot mode. + * + * @param base USDHC peripheral base address. + * @param enable True to enable, false to disable. + */ +static inline void USDHC_EnableMmcBoot(USDHC_Type *base, bool enable) +{ + if (enable) + { + base->MMC_BOOT |= USDHC_MMC_BOOT_BOOT_EN_MASK; + } + else + { + base->MMC_BOOT &= ~USDHC_MMC_BOOT_BOOT_EN_MASK; + } +} + +/*! + * @brief Forces generating events according to the given mask. + * + * @param base USDHC peripheral base address. + * @param mask The force events bit posistion (_usdhc_force_event). + */ +static inline void USDHC_SetForceEvent(USDHC_Type *base, uint32_t mask) +{ + base->FORCE_EVENT = mask; +} + +/*! + * @brief select the usdhc output voltage + * + * @param base USDHC peripheral base address. + * @param true 1.8V, false 3.0V + */ +static inline void UDSHC_SelectVoltage(USDHC_Type *base, bool en18v) +{ + if (en18v) + { + base->VEND_SPEC |= USDHC_VEND_SPEC_VSELECT_MASK; + } + else + { + base->VEND_SPEC &= ~USDHC_VEND_SPEC_VSELECT_MASK; + } +} + +#if defined(FSL_FEATURE_USDHC_HAS_SDR50_MODE) && (FSL_FEATURE_USDHC_HAS_SDR50_MODE) +/*! + * @brief check the SDR50 mode request tuning bit + * When this bit set, user should call USDHC_StandardTuning function + * @param base USDHC peripheral base address. + */ +static inline bool USDHC_RequestTuningForSDR50(USDHC_Type *base) +{ + return base->HOST_CTRL_CAP & USDHC_HOST_CTRL_CAP_USE_TUNING_SDR50_MASK ? true : false; +} + +/*! + * @brief check the request re-tuning bit + * When this bit is set, user should do manual tuning or standard tuning function + * @param base USDHC peripheral base address. + */ +static inline bool USDHC_RequestReTuning(USDHC_Type *base) +{ + return base->PRES_STATE & USDHC_PRES_STATE_RTR_MASK ? true : false; +} + +/*! + * @brief the SDR104 mode auto tuning enable and disable + * This function should call after tuning function execute pass, auto tuning will handle + * by hardware + * @param base USDHC peripheral base address. + * @param enable/disable flag + */ +static inline void USDHC_EnableAutoTuning(USDHC_Type *base, bool enable) +{ + if (enable) + { + base->MIX_CTRL |= USDHC_MIX_CTRL_AUTO_TUNE_EN_MASK; + } + else + { + base->MIX_CTRL &= ~USDHC_MIX_CTRL_AUTO_TUNE_EN_MASK; + } +} + +/*! + * @brief the config the re-tuning timer for mode 1 and mode 3 + * This timer is used for standard tuning auto re-tuning, + * @param base USDHC peripheral base address. + * @param timer counter value + */ +static inline void USDHC_SetRetuningTimer(USDHC_Type *base, uint32_t counter) +{ + base->HOST_CTRL_CAP &= ~USDHC_HOST_CTRL_CAP_TIME_COUNT_RETUNING_MASK; + base->HOST_CTRL_CAP |= USDHC_HOST_CTRL_CAP_TIME_COUNT_RETUNING(counter); +} + +/*! + * @brief the auto tuning enbale for CMD/DATA line + * + * @param base USDHC peripheral base address. + */ +void USDHC_EnableAutoTuningForCmdAndData(USDHC_Type *base); + +/*! + * @brief manual tuning trigger or abort + * User should handle the tuning cmd and find the boundary of the delay + * then calucate a average value which will be config to the CLK_TUNE_CTRL_STATUS + * This function should called before USDHC_AdjustDelayforSDR104 function + * @param base USDHC peripheral base address. + * @param tuning enable flag + */ +void USDHC_EnableManualTuning(USDHC_Type *base, bool enable); + +/*! + * @brief the SDR104 mode delay setting adjust + * This function should called after USDHC_ManualTuningForSDR104 + * @param base USDHC peripheral base address. + * @param delay setting configuration + * @retval kStatus_Fail config the delay setting fail + * @retval kStatus_Success config the delay setting success + */ +status_t USDHC_AdjustDelayForManualTuning(USDHC_Type *base, uint32_t delay); + +/*! + * @brief the enable standard tuning function + * The standard tuning window and tuning counter use the default config + * tuning cmd is send by the software, user need to check the tuning result + * can be used for SDR50,SDR104,HS200 mode tuning + * @param base USDHC peripheral base address. + * @param tuning start tap + * @param tuning step + * @param enable/disable flag + */ +void USDHC_EnableStandardTuning(USDHC_Type *base, uint32_t tuningStartTap, uint32_t step, bool enable); + +/*! + * @brief Get execute std tuning status + * + * @param base USDHC peripheral base address. + */ +static inline uint32_t USDHC_GetExecuteStdTuningStatus(USDHC_Type *base) +{ + return (base->AUTOCMD12_ERR_STATUS & USDHC_AUTOCMD12_ERR_STATUS_EXECUTE_TUNING_MASK); +} + +/*! + * @brief check std tuning result + * + * @param base USDHC peripheral base address. + */ +static inline uint32_t USDHC_CheckStdTuningResult(USDHC_Type *base) +{ + return (base->AUTOCMD12_ERR_STATUS & USDHC_AUTOCMD12_ERR_STATUS_SMP_CLK_SEL_MASK); +} + +/*! + * @brief check tuning error + * + * @param base USDHC peripheral base address. + */ +static inline uint32_t USDHC_CheckTuningError(USDHC_Type *base) +{ + return (base->CLK_TUNE_CTRL_STATUS & + (USDHC_CLK_TUNE_CTRL_STATUS_NXT_ERR_MASK | USDHC_CLK_TUNE_CTRL_STATUS_PRE_ERR_MASK)); +} + +#endif +/*! + * @brief the enable/disable DDR mode + * + * @param base USDHC peripheral base address. + * @param enable/disable flag + * @param nibble position + */ +void USDHC_EnableDDRMode(USDHC_Type *base, bool enable, uint32_t nibblePos); + +/*! + * @brief the enable/disable HS400 mode + * + * @param base USDHC peripheral base address. + * @param enable/disable flag + */ +#if FSL_FEATURE_USDHC_HAS_HS400_MODE +static inline void USDHC_EnableHS400Mode(USDHC_Type *base, bool enable) +{ + if (enable) + { + base->MIX_CTRL |= USDHC_MIX_CTRL_HS400_MODE_MASK; + } + else + { + base->MIX_CTRL &= ~USDHC_MIX_CTRL_HS400_MODE_MASK; + } +} + +/*! + * @brief reset the strobe DLL + * + * @param base USDHC peripheral base address. + */ +static inline void USDHC_ResetStrobeDLL(USDHC_Type *base) +{ + base->STROBE_DLL_CTRL |= USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_RESET_MASK; +} + +/*! + * @brief enable/disable the strobe DLL + * + * @param base USDHC peripheral base address. + * @param enable/disable flag + */ +static inline void USDHC_EnableStrobeDLL(USDHC_Type *base, bool enable) +{ + if (enable) + { + base->STROBE_DLL_CTRL |= USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_ENABLE_MASK; + } + else + { + base->STROBE_DLL_CTRL &= ~USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_ENABLE_MASK; + } +} + +/*! + * @brief config the strobe DLL delay target and update interval + * + * @param base USDHC peripheral base address. + * @param delay target + * @param update interval + */ +static inline void USDHC_ConfigStrobeDLL(USDHC_Type *base, uint32_t delayTarget, uint32_t updateInterval) +{ + base->STROBE_DLL_CTRL &= (USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_UPDATE_INT_MASK | + USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_DLY_TARGET_MASK); + + base->STROBE_DLL_CTRL |= USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_UPDATE_INT(updateInterval) | + USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_DLY_TARGET(delayTarget); +} + +/*! + * @brief get the strobe DLL status + * + * @param base USDHC peripheral base address. + */ +static inline uint32_t USDHC_GetStrobeDLLStatus(USDHC_Type *base) +{ + return base->STROBE_DLL_STATUS; +} + +#endif + +/* @} */ + +/*! + * @name Transactional + * @{ + */ + +/*! + * @brief Transfers the command/data using a blocking method. + * + * This function waits until the command response/data is received or the USDHC encounters an error by polling the + * status + * flag. + * The application must not call this API in multiple threads at the same time. Because of that this API doesn't + * support the re-entry mechanism. + * + * @note There is no need to call the API 'USDHC_TransferCreateHandle' when calling this API. + * + * @param base USDHC peripheral base address. + * @param adma configuration + * @param transfer Transfer content. + * @retval kStatus_InvalidArgument Argument is invalid. + * @retval kStatus_USDHC_PrepareAdmaDescriptorFailed Prepare ADMA descriptor failed. + * @retval kStatus_USDHC_SendCommandFailed Send command failed. + * @retval kStatus_USDHC_TransferDataFailed Transfer data failed. + * @retval kStatus_Success Operate successfully. + */ +status_t USDHC_TransferBlocking(USDHC_Type *base, usdhc_adma_config_t *dmaConfig, usdhc_transfer_t *transfer); + +/*! + * @brief Creates the USDHC handle. + * + * @param base USDHC peripheral base address. + * @param handle USDHC handle pointer. + * @param callback Structure pointer to contain all callback functions. + * @param userData Callback function parameter. + */ +void USDHC_TransferCreateHandle(USDHC_Type *base, + usdhc_handle_t *handle, + const usdhc_transfer_callback_t *callback, + void *userData); + +/*! + * @brief Transfers the command/data using an interrupt and an asynchronous method. + * + * This function sends a command and data and returns immediately. It doesn't wait the transfer complete or + * encounter an error. The application must not call this API in multiple threads at the same time. Because of that + * this API doesn't support the re-entry mechanism. + * + * @note Call the API 'USDHC_TransferCreateHandle' when calling this API. + * + * @param base USDHC peripheral base address. + * @param handle USDHC handle. + * @param adma configuration. + * @param transfer Transfer content. + * @retval kStatus_InvalidArgument Argument is invalid. + * @retval kStatus_USDHC_BusyTransferring Busy transferring. + * @retval kStatus_USDHC_PrepareAdmaDescriptorFailed Prepare ADMA descriptor failed. + * @retval kStatus_Success Operate successfully. + */ +status_t USDHC_TransferNonBlocking(USDHC_Type *base, + usdhc_handle_t *handle, + usdhc_adma_config_t *dmaConfig, + usdhc_transfer_t *transfer); + +/*! + * @brief IRQ handler for the USDHC. + * + * This function deals with the IRQs on the given host controller. + * + * @param base USDHC peripheral base address. + * @param handle USDHC handle. + */ +void USDHC_TransferHandleIRQ(USDHC_Type *base, usdhc_handle_t *handle); + +/* @} */ + +#if defined(__cplusplus) +} +#endif +/*! @} */ + +#endif /* _FSL_USDHC_H_*/ diff --git a/Ubiquitous/XiZi/board/xidatong/third_party_driver/include/system_MIMXRT1052.h b/Ubiquitous/XiZi/board/xidatong/third_party_driver/include/system_MIMXRT1052.h new file mode 100755 index 0000000..74941f9 --- /dev/null +++ b/Ubiquitous/XiZi/board/xidatong/third_party_driver/include/system_MIMXRT1052.h @@ -0,0 +1,127 @@ +/* +** ################################################################### +** Processors: MIMXRT1052CVJ5B +** MIMXRT1052CVL5B +** MIMXRT1052DVJ6B +** MIMXRT1052DVL6B +** +** Compilers: Freescale C/C++ for Embedded ARM +** GNU C Compiler +** IAR ANSI C/C++ Compiler for ARM +** Keil ARM C/C++ Compiler +** MCUXpresso Compiler +** +** Reference manual: IMXRT1050RM Rev.2.1, 12/2018 +** Version: rev. 1.2, 2018-11-27 +** Build: b181205 +** +** Abstract: +** Provides a system configuration function and a global variable that +** contains the system frequency. It configures the device and initializes +** the oscillator (PLL) that is part of the microcontroller device. +** +** Copyright 2016 Freescale Semiconductor, Inc. +** Copyright 2016-2018 NXP +** All rights reserved. +** +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** Revisions: +** - rev. 0.1 (2017-01-10) +** Initial version. +** - rev. 1.0 (2018-09-21) +** Update interrupt vector table and dma request source. +** Update register BEE_ADDR_OFFSET1's bitfield name to ADDR_OFFSET1. +** Split GPIO_COMBINED_IRQS to GPIO_COMBINED_LOW_IRQS and GPIO_COMBINED_HIGH_IRQS. +** - rev. 1.1 (2018-11-16) +** Update header files to align with IMXRT1050RM Rev.1. +** - rev. 1.2 (2018-11-27) +** Update header files to align with IMXRT1050RM Rev.2.1. +** +** ################################################################### +*/ + +/*! + * @file MIMXRT1052 + * @version 1.2 + * @date 2018-11-27 + * @brief Device specific configuration file for MIMXRT1052 (header file) + * + * Provides a system configuration function and a global variable that contains + * the system frequency. It configures the device and initializes the oscillator + * (PLL) that is part of the microcontroller device. + */ + +#ifndef _SYSTEM_MIMXRT1052_H_ +#define _SYSTEM_MIMXRT1052_H_ /**< Symbol preventing repeated inclusion */ + +#ifdef __cplusplus +extern "C" { +#endif + +#include + + +#ifndef DISABLE_WDOG + #define DISABLE_WDOG 1 +#endif + +/* Define clock source values */ + +#define CPU_XTAL_CLK_HZ 24000000UL /* Value of the external crystal or oscillator clock frequency in Hz */ + +#define CPU_CLK1_HZ 0UL /* Value of the CLK1 (select the CLK1_N/CLK1_P as source) frequency in Hz */ + /* If CLOCK1_P,CLOCK1_N is choose as the pll bypass clock source, please implement the CLKPN_FREQ define, otherwise 0 will be returned. */ + +#define DEFAULT_SYSTEM_CLOCK 528000000UL /* Default System clock value */ + + +/** + * @brief System clock frequency (core clock) + * + * The system clock frequency supplied to the SysTick timer and the processor + * core clock. This variable can be used by the user application to setup the + * SysTick timer or configure other parameters. It may also be used by debugger to + * query the frequency of the debug timer or configure the trace clock speed + * SystemCoreClock is initialized with a correct predefined value. + */ +extern uint32_t SystemCoreClock; + +/** + * @brief Setup the microcontroller system. + * + * Typically this function configures the oscillator (PLL) that is part of the + * microcontroller device. For systems with variable clock speed it also updates + * the variable SystemCoreClock. SystemInit is called from startup_device file. + */ +void SystemInit (void); + +/** + * @brief Updates the SystemCoreClock variable. + * + * It must be called whenever the core clock is changed during program + * execution. SystemCoreClockUpdate() evaluates the clock register settings and calculates + * the current core clock. + */ +void SystemCoreClockUpdate (void); + +/** + * @brief SystemInit function hook. + * + * This weak function allows to call specific initialization code during the + * SystemInit() execution.This can be used when an application specific code needs + * to be called as close to the reset entry as possible (for example the Multicore + * Manager MCMGR_EarlyInit() function call). + * NOTE: No global r/w variables can be used in this hook function because the + * initialization of these variables happens after this function. + */ +void SystemInitHook (void); + +#ifdef __cplusplus +} +#endif + +#endif /* _SYSTEM_MIMXRT1052_H_ */ diff --git a/Ubiquitous/XiZi/board/xidatong/third_party_driver/sdio/Kconfig b/Ubiquitous/XiZi/board/xidatong/third_party_driver/sdio/Kconfig new file mode 100644 index 0000000..c2ceb30 --- /dev/null +++ b/Ubiquitous/XiZi/board/xidatong/third_party_driver/sdio/Kconfig @@ -0,0 +1,24 @@ +if BSP_USING_SDIO + config SDIO_BUS_NAME + string "sdio bus name" + default "sdio" + + config SDIO_DRIVER_NAME + string "sdio driver name" + default "sdio_drv" + + config SDIO_DEVICE_NAME + string "sdio device name" + default "sdio_dev" + + config MOUNT_SDCARD_FS + bool "mount cd card file system" + default n + select MOUNT_SDCARD + + if MOUNT_SDCARD_FS + config MOUNT_SDCARD_FS_TYPE + int "choose file system type : FATFS(0) LWEXT4(3)" + default 0 + endif +endif diff --git a/Ubiquitous/XiZi/board/xidatong/third_party_driver/sdio/Makefile b/Ubiquitous/XiZi/board/xidatong/third_party_driver/sdio/Makefile new file mode 100644 index 0000000..7e45190 --- /dev/null +++ b/Ubiquitous/XiZi/board/xidatong/third_party_driver/sdio/Makefile @@ -0,0 +1,5 @@ +SRC_DIR := sdmmc + +SRC_FILES := connect_sdio.c + +include $(KERNEL_ROOT)/compiler.mk diff --git a/Ubiquitous/XiZi/board/xidatong/third_party_driver/sdio/connect_sdio.c b/Ubiquitous/XiZi/board/xidatong/third_party_driver/sdio/connect_sdio.c new file mode 100644 index 0000000..841ed2f --- /dev/null +++ b/Ubiquitous/XiZi/board/xidatong/third_party_driver/sdio/connect_sdio.c @@ -0,0 +1,455 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +/** +* @file connect_sdio.c +* @brief support sdio function using bus driver framework on xidatong board +* @version 2.0 +* @author AIIT XUOS Lab +* @date 2022-01-24 +*/ + +/************************************************* +File name: connect_sdio.c +Description: support imxrt1052-board sd card configure and sdio bus register function +Others: take SDK_2.6.1_MIMXRT1052xxxxB/boards/evkbimxrt1050/driver_examples/sdcard/polling/sdcard_polling.c for references +History: +1. Date: 2022-01-24 +Author: AIIT XUOS Lab +Modification: +1. support imxrt1052-board sdio configure, write and read +2. support imxrt1052-board sdio bus device and driver register +*************************************************/ + +#include + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +#define SDCARD_POWER_CTRL_FUNCTION_EXIST + +/*! @brief Data block count accessed in card */ +#define DATA_BLOCK_COUNT (5U) +/*! @brief Start data block number accessed in card */ +#define DATA_BLOCK_START (2U) +/*! @brief Data buffer size. */ +#define DATA_BUFFER_SIZE (FSL_SDMMC_DEFAULT_BLOCK_SIZE * DATA_BLOCK_COUNT) + +#define BOARD_USDHC_SDCARD_POWER_CONTROL(state) \ + (GPIO_PinWrite(BOARD_SD_POWER_RESET_GPIO, BOARD_SD_POWER_RESET_GPIO_PIN, state)) + +/******************************************************************************* + * Prototypes + ******************************************************************************/ +static void BoardPowerOffSdCard(void); +static void BoardPowerOnSdCard(void); + +/*! + * @brief printf the card information log. + * + * @param card Card descriptor. + */ +static void CardInformationLog(sd_card_t *card); + +/******************************************************************************* + * Variables + ******************************************************************************/ + +/* @brief decription about the read/write buffer + * The size of the read/write buffer should be a multiple of 512, since SDHC/SDXC card uses 512-byte fixed + * block length and this driver example is enabled with a SDHC/SDXC card.If you are using a SDSC card, you + * can define the block length by yourself if the card supports partial access. + * The address of the read/write buffer should align to the specific DMA data buffer address align value if + * DMA transfer is used, otherwise the buffer address is not important. + * At the same time buffer address/size should be aligned to the cache line size if cache is supported. + */ +/*! @brief Data written to the card */ +SDK_ALIGN(uint8_t g_data_write[SDK_SIZEALIGN(DATA_BUFFER_SIZE, SDMMC_DATA_BUFFER_ALIGN_CACHE)], + MAX(SDMMC_DATA_BUFFER_ALIGN_CACHE, SDMMCHOST_DMA_BUFFER_ADDR_ALIGN)); +/*! @brief Data read from the card */ +SDK_ALIGN(uint8_t g_data_read[SDK_SIZEALIGN(DATA_BUFFER_SIZE, SDMMC_DATA_BUFFER_ALIGN_CACHE)], + MAX(SDMMC_DATA_BUFFER_ALIGN_CACHE, SDMMCHOST_DMA_BUFFER_ADDR_ALIGN)); + +/*! @brief SDMMC host detect card configuration */ +static const sdmmchost_detect_card_t s_sdcard_detect = { +#ifndef BOARD_SD_DETECT_TYPE + .cdType = kSDMMCHOST_DetectCardByGpioCD, +#else + .cdType = BOARD_SD_DETECT_TYPE, +#endif + .cdTimeOut_ms = (~0U), +}; + +/*! @brief SDMMC card power control configuration */ +#if defined SDCARD_POWER_CTRL_FUNCTION_EXIST +static const sdmmchost_pwr_card_t s_sdcard_pwr_ctrl = { + .powerOn = BoardPowerOnSdCard, + .powerOnDelay_ms = 0U, + .powerOff = BoardPowerOffSdCard, + .powerOffDelay_ms = 0U, +}; +#endif + +/*! @brief SDMMC card power control configuration */ +#if defined SDCARD_SWITCH_VOLTAGE_FUNCTION_EXIST +static const sdmmchost_card_switch_voltage_func_t s_sdcard_voltage_switch = { + .cardSignalLine1V8 = BOARD_USDHC_Switch_VoltageTo1V8, + .cardSignalLine3V3 = BOARD_USDHC_Switch_VoltageTo3V3, +}; +#endif + +/*! @brief Card descriptor. */ +static sd_card_t g_sd; +static int sd_lock = -1; + +static void BoardUSDHCClockConfiguration(void) +{ + CLOCK_InitSysPll(&sysPllConfig_BOARD_BootClockRUN); + /*configure system pll PFD0 fractional divider to 24, output clock is 528MHZ * 18 / 24 = 396 MHZ*/ + CLOCK_InitSysPfd(kCLOCK_Pfd0, 24U); + /* Configure USDHC clock source and divider */ + CLOCK_SetDiv(kCLOCK_Usdhc1Div, 0U); + CLOCK_SetMux(kCLOCK_Usdhc1Mux, 1U); +} + +static void BoardPowerOffSdCard(void) +{ + /* + Do nothing here. + + SD card will not be detected correctly if the card VDD is power off, + the reason is caused by card VDD supply to the card detect circuit, this issue is exist on EVK board rev A1 and + A2. + + If power off function is not implemented after soft reset and prior to SD Host initialization without + remove/insert card, + a UHS-I card may not reach its highest speed mode during the second card initialization. + Application can avoid this issue by toggling the SD_VDD (GPIO) before the SD host initialization. + */ +} + +static void BoardPowerOnSdCard(void) +{ + BOARD_USDHC_SDCARD_POWER_CONTROL(1); +} + +static void CardInformationLog(sd_card_t *card) +{ + NULL_PARAM_CHECK(card); + + KPrintf("\r\nCard size %d * %d bytes\r\n", card->blockCount, card->blockSize); + KPrintf("\r\nWorking condition:\r\n"); + if (card->operationVoltage == kCARD_OperationVoltage330V) { + KPrintf("\r\n Voltage : 3.3V\r\n"); + } else if (card->operationVoltage == kCARD_OperationVoltage180V) { + KPrintf("\r\n Voltage : 1.8V\r\n"); + } + + if (card->currentTiming == kSD_TimingSDR12DefaultMode) { + if (card->operationVoltage == kCARD_OperationVoltage330V) { + KPrintf("\r\n Timing mode: Default mode\r\n"); + } else if (card->operationVoltage == kCARD_OperationVoltage180V) { + KPrintf("\r\n Timing mode: SDR12 mode\r\n"); + } + } else if (card->currentTiming == kSD_TimingSDR25HighSpeedMode) { + if (card->operationVoltage == kCARD_OperationVoltage180V) { + KPrintf("\r\n Timing mode: SDR25\r\n"); + } else { + KPrintf("\r\n Timing mode: High Speed\r\n"); + } + } else if (card->currentTiming == kSD_TimingSDR50Mode) { + KPrintf("\r\n Timing mode: SDR50\r\n"); + } else if (card->currentTiming == kSD_TimingSDR104Mode) { + KPrintf("\r\n Timing mode: SDR104\r\n"); + } else if (card->currentTiming == kSD_TimingDDR50Mode) { + KPrintf("\r\n Timing mode: DDR50\r\n"); + } + + KPrintf("\r\n Freq : %d HZ\r\n", card->busClock_Hz); +} + +static uint32 SdioConfigure(void *drv, struct BusConfigureInfo *configure_info) +{ + NULL_PARAM_CHECK(drv); + NULL_PARAM_CHECK(configure_info); + + if (configure_info->configure_cmd == OPER_BLK_GETGEOME) { + NULL_PARAM_CHECK(configure_info->private_data); + struct DeviceBlockArrange *args = (struct DeviceBlockArrange *)configure_info->private_data; + + args->size_perbank = g_sd.blockSize; + args->block_size = g_sd.blockSize; + args->bank_num = g_sd.blockCount; + } + + return EOK; +} + +static uint32 SdioOpen(void *dev) +{ + NULL_PARAM_CHECK(dev); + + if(sd_lock >= 0) { + KSemaphoreDelete(sd_lock); + } + sd_lock = KSemaphoreCreate(1); + if (sd_lock < 0){ + return ERROR; + } + + return EOK; +} + +static uint32 SdioClose(void *dev) +{ + NULL_PARAM_CHECK(dev); + + KSemaphoreDelete(sd_lock); + + return EOK; +} + +static uint32 SdioRead(void *dev, struct BusBlockReadParam *read_param) +{ + uint8 ret = EOK; + uint32 sector = read_param->pos; + uint32 block_num = read_param->size; + uint8 *read_buffer = (uint8 *)read_param->buffer; + + KSemaphoreObtain(sd_lock, WAITING_FOREVER); + + if (kStatus_Success != SD_ReadBlocks(&g_sd, read_buffer, sector, block_num)) { + KPrintf("Read multiple data blocks failed.\r\n"); + return 0; + } + + KSemaphoreAbandon(sd_lock); + + return read_param->size; +} + +static uint32 SdioWrite(void *dev, struct BusBlockWriteParam *write_param) +{ + uint8 ret = EOK; + uint32 sector = write_param->pos; + uint32 block_num = write_param->size; + const uint8 *write_buffer = (uint8 *)write_param->buffer; + + KSemaphoreObtain(sd_lock, WAITING_FOREVER); + + if (kStatus_Success != SD_WriteBlocks(&g_sd, write_buffer, sector, block_num)) { + KPrintf("Write multiple data blocks failed.\r\n"); + return 0; + } + + KSemaphoreAbandon(sd_lock); + + return write_param->size; +} + +static int SdioControl(struct HardwareDev *dev, struct HalDevBlockParam *block_param) +{ + NULL_PARAM_CHECK(dev); + + if (OPER_BLK_GETGEOME == block_param->cmd) { + block_param->dev_block.size_perbank = g_sd.blockSize; + block_param->dev_block.block_size = g_sd.blockSize; + block_param->dev_block.bank_num = g_sd.blockCount; + } + + return EOK; +} + +static struct SdioDevDone dev_done = +{ + SdioOpen, + SdioClose, + SdioWrite, + SdioRead, +}; + +#if defined(FS_VFS) && defined(MOUNT_SDCARD_FS) +#include + +/** + * @description: Mount SD card + * @return 0 + */ +static int MountSDCardFs(enum FilesystemType fs_type) +{ + if (MountFilesystem(SDIO_BUS_NAME, SDIO_DEVICE_NAME, SDIO_DRIVER_NAME, fs_type, "/") == 0) + KPrintf("Sd card mount to '/'"); + else + KPrintf("Sd card mount to '/' failed!"); + + return 0; +} +#endif + +static void SdCardAttach(void) +{ + bool is_read_only; + static sd_card_t *card = &g_sd; + + KPrintf("\r\nCard inserted.\r\n"); + /* reset host once card re-plug in */ + SD_HostReset(&(card->host)); + /* power on the card */ + SD_PowerOnCard(card->host.base, card->usrParam.pwr); + KPrintf("Power on done\n"); + + /* Init card. */ + if (SD_CardInit(card)) { + KPrintf("\r\nSD card init failed.\r\n"); + return; + } + + /* card information log */ + CardInformationLog(card); + + /* Check if card is readonly. */ + is_read_only = SD_CheckReadOnly(card); + +#ifdef MOUNT_SDCARD_FS + /*mount file system*/ + MountSDCardFs(MOUNT_SDCARD_FS_TYPE); +#endif +} + +static void SdCardDetach(void) +{ + /*unmount file system*/ + KPrintf("\r\nCard detect extracted.\r\n"); + +#ifdef MOUNT_SDCARD_FS + UnmountFileSystem("/"); +#endif +} + +static uint8 SdCardReadCd(void) +{ + BusType pin; + + pin = BusFind(PIN_BUS_NAME); + + pin->owner_haldev = BusFindDevice(pin, PIN_DEVICE_NAME); + + struct PinStat PinStat; + + struct BusBlockReadParam read_param; + read_param.buffer = (void *)&PinStat; + + PinStat.pin = IMXRT_GET_PIN(2, 28); + + return BusDevReadData(pin->owner_haldev, &read_param); +} + +static void SdCardTask(void* parameter) +{ + static int sd_card_status = 0; + + while (1) { + if (!SdCardReadCd()) { + if (!sd_card_status) { + SdCardAttach(); + sd_card_status = 1; + } + } else { + if (sd_card_status) { + SdCardDetach(); + sd_card_status = 0; + } + } + } +} + +#ifdef MOUNT_SDCARD +int MountSDCard() +{ + int sd_card_task = 0; + sd_card_task = KTaskCreate("sd_card", SdCardTask, NONE, + SD_CARD_STACK_SIZE, 8); + if(sd_card_task < 0) { + KPrintf("sd_card_task create failed ...%s %d.\n", __FUNCTION__,__LINE__); + return ERROR; + } + + StartupKTask(sd_card_task); + + return EOK; +} +#endif + +int Imxrt1052HwSdioInit(void) +{ + x_err_t ret = EOK; + + static struct SdioBus sdio_bus; + static struct SdioDriver sdio_drv; + static struct SdioHardwareDevice sdio_dev; + static sd_card_t *card = &g_sd; + + memset(&sdio_bus, 0, sizeof(struct SdioBus)); + memset(&sdio_drv, 0, sizeof(struct SdioDriver)); + memset(&sdio_dev, 0, sizeof(struct SdioHardwareDevice)); + + BoardUSDHCClockConfiguration(); + + card->host.base = SD_HOST_BASEADDR; + card->host.sourceClock_Hz = SD_HOST_CLK_FREQ; + + /* card detect type */ + card->usrParam.cd = &s_sdcard_detect; + +#if defined SDCARD_POWER_CTRL_FUNCTION_EXIST + card->usrParam.pwr = &s_sdcard_pwr_ctrl; +#endif + +#if defined DEMO_SDCARD_SWITCH_VOLTAGE_FUNCTION_EXIST + card->usrParam.cardVoltage = &s_sdcard_voltage_switch; +#endif + + /* SD host init function */ + if (SD_HostInit(card) != kStatus_Success) { + KPrintf("\r\nSD host init fail\r\n"); + return ERROR; + } + + ret = SdioBusInit(&sdio_bus, SDIO_BUS_NAME); + if (ret != EOK) { + KPrintf("Sdio bus init error %d\n", ret); + return ERROR; + } + + ret = SdioDriverInit(&sdio_drv, SDIO_DRIVER_NAME); + if (ret != EOK) { + KPrintf("Sdio driver init error %d\n", ret); + return ERROR; + } + ret = SdioDriverAttachToBus(SDIO_DRIVER_NAME, SDIO_BUS_NAME); + if (ret != EOK) { + KPrintf("Sdio driver attach error %d\n", ret); + return ERROR; + } + + sdio_dev.dev_done = &dev_done; + sdio_dev.haldev.dev_block_control = SdioControl; + ret = SdioDeviceRegister(&sdio_dev, SDIO_DEVICE_NAME); + if (ret != EOK) { + KPrintf("Sdio device register error %d\n", ret); + return ERROR; + } + ret = SdioDeviceAttachToBus(SDIO_DEVICE_NAME, SDIO_BUS_NAME); + if (ret != EOK) { + KPrintf("Sdio device register error %d\n", ret); + return ERROR; + } + + return ret; +} diff --git a/Ubiquitous/XiZi/board/xidatong/third_party_driver/semc/Kconfig b/Ubiquitous/XiZi/board/xidatong/third_party_driver/semc/Kconfig new file mode 100644 index 0000000..f081299 --- /dev/null +++ b/Ubiquitous/XiZi/board/xidatong/third_party_driver/semc/Kconfig @@ -0,0 +1,9 @@ +config BSP_USING_EXTSRAM + bool "config semc extern sram" + default n + select MEM_EXTERN_SRAM + if BSP_USING_EXTSRAM + config EXTSRAM_MAX_NUM + int "config extsram chip num" + default 4 + endif diff --git a/Ubiquitous/XiZi/board/xidatong/third_party_driver/semc/Makefile b/Ubiquitous/XiZi/board/xidatong/third_party_driver/semc/Makefile new file mode 100644 index 0000000..6438aa6 --- /dev/null +++ b/Ubiquitous/XiZi/board/xidatong/third_party_driver/semc/Makefile @@ -0,0 +1,3 @@ +SRC_FILES := connect_semc.c fsl_semc.c semc_externsdram_test.c + +include $(KERNEL_ROOT)/compiler.mk diff --git a/Ubiquitous/XiZi/board/xidatong/third_party_driver/semc/connect_semc.c b/Ubiquitous/XiZi/board/xidatong/third_party_driver/semc/connect_semc.c new file mode 100644 index 0000000..2477fb2 --- /dev/null +++ b/Ubiquitous/XiZi/board/xidatong/third_party_driver/semc/connect_semc.c @@ -0,0 +1,57 @@ +#include "fsl_semc.h" +#include "clock_config.h" +#include + +#define EXAMPLE_SEMC SEMC +#define EXAMPLE_SEMC_START_ADDRESS (0x80000000U) +#define EXAMPLE_SEMC_CLK_FREQ CLOCK_GetFreq(kCLOCK_SemcClk) +#define SEMC_SRAM_SIZE (32 * 1024 * 1024) + +status_t BOARD_InitSEMC(void) +{ + semc_config_t config; + semc_sdram_config_t sdramconfig; + uint32_t clockFrq = EXAMPLE_SEMC_CLK_FREQ; + + /* Initializes the MAC configure structure to zero. */ + memset(&config, 0, sizeof(semc_config_t)); + memset(&sdramconfig, 0, sizeof(semc_sdram_config_t)); + + /* Initialize SEMC. */ + SEMC_GetDefaultConfig(&config); + config.dqsMode = kSEMC_Loopbackdqspad; /* For more accurate timing. */ + SEMC_Init(SEMC, &config); + + /* Configure SDRAM. */ + sdramconfig.csxPinMux = kSEMC_MUXCSX0; + sdramconfig.address = 0x80000000; + sdramconfig.memsize_kbytes = 32 * 1024; /* 32MB = 32*1024*1KBytes*/ + sdramconfig.portSize = kSEMC_PortSize16Bit; + sdramconfig.burstLen = kSEMC_Sdram_BurstLen8; + sdramconfig.columnAddrBitNum = kSEMC_SdramColunm_9bit; + sdramconfig.casLatency = kSEMC_LatencyThree; + sdramconfig.tPrecharge2Act_Ns = 18; /* Trp 18ns */ + sdramconfig.tAct2ReadWrite_Ns = 18; /* Trcd 18ns */ + sdramconfig.tRefreshRecovery_Ns = 67; /* Use the maximum of the (Trfc , Txsr). */ + sdramconfig.tWriteRecovery_Ns = 12; /* 12ns */ + sdramconfig.tCkeOff_Ns = + 42; /* The minimum cycle of SDRAM CLK off state. CKE is off in self refresh at a minimum period tRAS.*/ + sdramconfig.tAct2Prechage_Ns = 42; /* Tras 42ns */ + sdramconfig.tSelfRefRecovery_Ns = 67; + sdramconfig.tRefresh2Refresh_Ns = 60; + sdramconfig.tAct2Act_Ns = 60; + sdramconfig.tPrescalePeriod_Ns = 160 * (1000000000 / clockFrq); + sdramconfig.refreshPeriod_nsPerRow = 64 * 1000000 / 8192; /* 64ms/8192 */ + sdramconfig.refreshUrgThreshold = sdramconfig.refreshPeriod_nsPerRow; + sdramconfig.refreshBurstLen = 1; + return SEMC_ConfigureSDRAM(SEMC, kSEMC_SDRAM_CS0, &sdramconfig, clockFrq); +} + +#ifdef BSP_USING_EXTSRAM +int ExtSramInit(void) +{ + extern void ExtSramInitBoardMemory(void *start_phy_address, void *end_phy_address, uint8 extsram_idx); + ExtSramInitBoardMemory((void*)(EXAMPLE_SEMC_START_ADDRESS), (void*)((EXAMPLE_SEMC_START_ADDRESS + SEMC_SRAM_SIZE)), kSEMC_SDRAM_CS0); + return 0; +} +#endif \ No newline at end of file diff --git a/Ubiquitous/XiZi/board/xidatong/third_party_driver/semc/semc_externsdram_test.c b/Ubiquitous/XiZi/board/xidatong/third_party_driver/semc/semc_externsdram_test.c new file mode 100644 index 0000000..c09b6dc --- /dev/null +++ b/Ubiquitous/XiZi/board/xidatong/third_party_driver/semc/semc_externsdram_test.c @@ -0,0 +1,180 @@ +/* + * Copyright 2017 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#include "board.h" + +#define EXAMPLE_SEMC_START_ADDRESS (0x80000000U) + +#define SEMC_EXAMPLE_DATALEN (0x1000U) + +/******************************************************************************* + * Prototypes + ******************************************************************************/ +static void SEMC_SDRAMReadWrite32Bit(void); +static void SEMC_SDRAMReadWrite16Bit(void); +static void SEMC_SDRAMReadWrite8Bit(void); +/******************************************************************************* + * Variables + ******************************************************************************/ + +uint32_t sdram_writeBuffer[SEMC_EXAMPLE_DATALEN]; +uint32_t sdram_readBuffer[SEMC_EXAMPLE_DATALEN]; + +/*! + * @brief Main function + */ +int semc_externsram_test(void) +{ + KPrintf("\r\n SEMC SDRAM Example Start!\r\n"); + + /* 32Bit data read and write. */ + SEMC_SDRAMReadWrite32Bit(); + /* 16Bit data read and write. */ + SEMC_SDRAMReadWrite16Bit(); + /* 8Bit data read and write. */ + SEMC_SDRAMReadWrite8Bit(); + + KPrintf("\r\n SEMC SDRAM Example End.\r\n"); + +} +SHELL_EXPORT_CMD(SHELL_CMD_PERMISSION(0)|SHELL_CMD_TYPE(SHELL_TYPE_CMD_FUNC)|SHELL_CMD_PARAM_NUM(0),semc_externsram_test, semc_externsram_test, semc_externsram_test ); + +void SEMC_SDRAMReadWrite32Bit(void) +{ + uint32_t index; + uint32_t datalen = SEMC_EXAMPLE_DATALEN; + uint32_t *sdram = (uint32_t *)EXAMPLE_SEMC_START_ADDRESS; /* SDRAM start address. */ + int result = 0; + + KPrintf("\r\n SEMC SDRAM Memory 32 bit Write Start, Start Address 0x%x, Data Length %d !\r\n", sdram, datalen); + /* Prepare data and write to SDRAM. */ + for (index = 0; index < datalen; index++) + { + sdram_writeBuffer[index] = index; + sdram[index] = sdram_writeBuffer[index]; + } + + KPrintf("\r\n SEMC SDRAM Read 32 bit Data Start, Start Address 0x%x, Data Length %d !\r\n", sdram, datalen); + /* Read data from the SDRAM. */ + for (index = 0; index < datalen; index++) + { + sdram_readBuffer[index] = sdram[index]; + } + + KPrintf("\r\n SEMC SDRAM 32 bit Data Write and Read Compare Start!\r\n"); + /* Compare the two buffers. */ + while (datalen--) + { + if (sdram_writeBuffer[datalen] != sdram_readBuffer[datalen]) + { + result = -1; + break; + } + } + + if (result < 0) + { + KPrintf("\r\n SEMC SDRAM 32 bit Data Write and Read Compare Failed!\r\n"); + } + else + { + KPrintf("\r\n SEMC SDRAM 32 bit Data Write and Read Compare Succeed!\r\n"); + } +} + +static void SEMC_SDRAMReadWrite16Bit(void) +{ + uint32_t index; + uint32_t datalen = SEMC_EXAMPLE_DATALEN; + uint16_t *sdram = (uint16_t *)EXAMPLE_SEMC_START_ADDRESS; /* SDRAM start address. */ + int result = 0; + + KPrintf("\r\n SEMC SDRAM Memory 16 bit Write Start, Start Address 0x%x, Data Length %d !\r\n", sdram, datalen); + + memset(sdram_writeBuffer, 0, sizeof(sdram_writeBuffer)); + memset(sdram_readBuffer, 0, sizeof(sdram_readBuffer)); + + /* Prepare data and write to SDRAM. */ + for (index = 0; index < datalen; index++) + { + sdram_writeBuffer[index] = index % 0xFFFF; + sdram[index] = sdram_writeBuffer[index]; + } + + KPrintf("\r\n SEMC SDRAM Read 16 bit Data Start, Start Address 0x%x, Data Length %d !\r\n", sdram, datalen); + /* Read data from the SDRAM. */ + for (index = 0; index < datalen; index++) + { + sdram_readBuffer[index] = sdram[index]; + } + + KPrintf("\r\n SEMC SDRAM 16 bit Data Write and Read Compare Start!\r\n"); + /* Compare the two buffers. */ + while (datalen--) + { + if (sdram_writeBuffer[datalen] != sdram_readBuffer[datalen]) + { + result = -1; + break; + } + } + + if (result < 0) + { + KPrintf("\r\n SEMC SDRAM 16 bit Data Write and Read Compare Failed!\r\n"); + } + else + { + KPrintf("\r\n SEMC SDRAM 16 bit Data Write and Read Compare Succeed!\r\n"); + } +} + +static void SEMC_SDRAMReadWrite8Bit(void) +{ + uint32_t index; + uint32_t datalen = SEMC_EXAMPLE_DATALEN; + uint8_t *sdram = (uint8_t *)EXAMPLE_SEMC_START_ADDRESS; /* SDRAM start address. */ + int result = 0; + + KPrintf("\r\n SEMC SDRAM Memory 8 bit Write Start, Start Address 0x%x, Data Length %d !\r\n", sdram, datalen); + + memset(sdram_writeBuffer, 0, sizeof(sdram_writeBuffer)); + memset(sdram_readBuffer, 0, sizeof(sdram_readBuffer)); + + /* Prepare data and write to SDRAM. */ + for (index = 0; index < datalen; index++) + { + sdram_writeBuffer[index] = index % 0x100; + sdram[index] = sdram_writeBuffer[index]; + } + + KPrintf("\r\n SEMC SDRAM Read 8 bit Data Start, Start Address 0x%x, Data Length %d !\r\n", sdram, datalen); + /* Read data from the SDRAM. */ + for (index = 0; index < datalen; index++) + { + sdram_readBuffer[index] = sdram[index]; + } + + KPrintf("\r\n SEMC SDRAM 8 bit Data Write and Read Compare Start!\r\n"); + /* Compare the two buffers. */ + while (datalen--) + { + if (sdram_writeBuffer[datalen] != sdram_readBuffer[datalen]) + { + result = -1; + break; + } + } + + if (result < 0) + { + KPrintf("\r\n SEMC SDRAM 8 bit Data Write and Read Compare Failed!\r\n"); + } + else + { + KPrintf("\r\n SEMC SDRAM 8 bit Data Write and Read Compare Succeed!\r\n"); + } +} diff --git a/Ubiquitous/XiZi/board/xidatong/third_party_driver/uart/Kconfig b/Ubiquitous/XiZi/board/xidatong/third_party_driver/uart/Kconfig new file mode 100644 index 0000000..93c86b3 --- /dev/null +++ b/Ubiquitous/XiZi/board/xidatong/third_party_driver/uart/Kconfig @@ -0,0 +1,29 @@ +config BSP_USING_LPUART1 +bool "Enable LPUART1" +default y +if BSP_USING_LPUART1 + config SERIAL_BUS_NAME_1 + string "serial bus 1 name" + default "uart1" + config SERIAL_DRV_NAME_1 + string "serial bus 1 driver name" + default "uart1_drv" + config SERIAL_1_DEVICE_NAME_0 + string "serial bus 1 device name" + default "uart1_dev1" +endif + +config BSP_USING_LPUART2 +bool "Enable LPUART2" +default y +if BSP_USING_LPUART2 + config SERIAL_BUS_NAME_2 + string "serial bus 2 name" + default "uart2" + config SERIAL_DRV_NAME_2 + string "serial bus 2 driver name" + default "uart2_drv" + config SERIAL_2_DEVICE_NAME_0 + string "serial bus 2 device name" + default "uart2_dev2" +endif diff --git a/Ubiquitous/XiZi/board/xidatong/third_party_driver/uart/Makefile b/Ubiquitous/XiZi/board/xidatong/third_party_driver/uart/Makefile new file mode 100644 index 0000000..1631643 --- /dev/null +++ b/Ubiquitous/XiZi/board/xidatong/third_party_driver/uart/Makefile @@ -0,0 +1,3 @@ +SRC_FILES := connect_uart.c fsl_lpuart.c + +include $(KERNEL_ROOT)/compiler.mk diff --git a/Ubiquitous/XiZi/board/xidatong/third_party_driver/usb/Kconfig b/Ubiquitous/XiZi/board/xidatong/third_party_driver/usb/Kconfig new file mode 100644 index 0000000..a1f439c --- /dev/null +++ b/Ubiquitous/XiZi/board/xidatong/third_party_driver/usb/Kconfig @@ -0,0 +1,15 @@ +config BSP_USING_NXP_USBH + bool "Using usb host by NXP library" + default n + if BSP_USING_NXP_USBH + config USB_BUS_NAME + string "usb bus name" + default "usb" + config USB_DRIVER_NAME + string "usb bus driver name" + default "usb_drv" + config USB_DEVICE_NAME + string "usb bus device name" + default "usb_dev" + endif + diff --git a/Ubiquitous/XiZi/board/xidatong/third_party_driver/usb/Makefile b/Ubiquitous/XiZi/board/xidatong/third_party_driver/usb/Makefile new file mode 100644 index 0000000..01f068d --- /dev/null +++ b/Ubiquitous/XiZi/board/xidatong/third_party_driver/usb/Makefile @@ -0,0 +1,5 @@ +SRC_DIR := nxp_usb_driver + +SRC_FILES := connect_usb.c + +include $(KERNEL_ROOT)/compiler.mk diff --git a/Ubiquitous/XiZi/board/xidatong/third_party_driver/usb/connect_usb.c b/Ubiquitous/XiZi/board/xidatong/third_party_driver/usb/connect_usb.c new file mode 100644 index 0000000..536e52d --- /dev/null +++ b/Ubiquitous/XiZi/board/xidatong/third_party_driver/usb/connect_usb.c @@ -0,0 +1,296 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +/** +* @file connect_usb.c +* @brief support usb host function using bus driver framework on xidatong board +* @version 2.0 +* @author AIIT XUOS Lab +* @date 2022-02-09 +*/ + +/************************************************* +File name: connect_usb.c +Description: support imxrt1052-board usb host configure and sdio bus register function +Others: take SDK_2.6.1_MIMXRT1052xxxxB/boards/evkbimxrt1050/usb_examples/usb_host_msd_command for references +History: +1. Date: 2022-02-09 +Author: AIIT XUOS Lab +Modification: +1. support imxrt1052-board usb host configure, write and read +2. support imxrt1052-board usb host bus device and driver register +*************************************************/ +#include +#include + +#define BSP_USING_NXP_USBH +#ifdef BSP_USING_NXP_USBH + +/*! @brief USB host msd command instance global variable */ +extern usb_host_msd_command_instance_t g_MsdCommandInstance; +usb_host_handle g_HostHandle; + +extern usb_status_t USB_HostMsdReadApi(usb_host_msd_command_instance_t *msdCommandInstance, uint8_t *buffer, uint32_t pos, uint32_t block_size, uint32_t block_num); +extern usb_status_t USB_HostMsdWriteApi(usb_host_msd_command_instance_t *msdCommandInstance, const uint8_t *buffer, uint32_t pos, uint32_t block_size, uint32_t block_num); + +//USB HOST ISR +void UsbOtg2IrqHandler(int irqn, void *arg) +{ + + DisableIRQ(USB2_IRQn); + + USB_HostEhciIsrFunction(g_HostHandle); + EnableIRQ(USB2_IRQn); + +} +DECLARE_HW_IRQ(USB2_IRQn, UsbOtg2IrqHandler, NONE); + +void UsbHostClockInit(void) +{ + usb_phy_config_struct_t phyConfig = { + BOARD_USB_PHY_D_CAL, + BOARD_USB_PHY_TXCAL45DP, + BOARD_USB_PHY_TXCAL45DM, + }; + + if (CONTROLLER_ID == kUSB_ControllerEhci0) { + CLOCK_EnableUsbhs0PhyPllClock(kCLOCK_Usbphy480M, 480000000U); + CLOCK_EnableUsbhs0Clock(kCLOCK_Usb480M, 480000000U); + } else { + CLOCK_EnableUsbhs1PhyPllClock(kCLOCK_Usbphy480M, 480000000U); + CLOCK_EnableUsbhs1Clock(kCLOCK_Usb480M, 480000000U); + } + USB_EhciPhyInit(CONTROLLER_ID, BOARD_XTAL0_CLK_HZ, &phyConfig); +} + +void UsbHostIsrEnable(void) +{ + uint8_t irqNumber; + + uint8_t usbHOSTEhciIrq[] = USBHS_IRQS; + irqNumber = usbHOSTEhciIrq[CONTROLLER_ID - kUSB_ControllerEhci0]; +/* USB_HOST_CONFIG_EHCI */ + +/* Install isr, set priority, and enable IRQ. */ + NVIC_SetPriority((IRQn_Type)irqNumber, USB_HOST_INTERRUPT_PRIORITY); + EnableIRQ((IRQn_Type)irqNumber); +} + +void UsbHostTaskFn(void *param) +{ + USB_HostEhciTaskFunction(param); +} + +/*! + * @brief USB isr function. + */ +static usb_status_t UsbHostEvent(usb_device_handle deviceHandle, + usb_host_configuration_handle configurationHandle, + uint32_t eventCode) +{ + usb_status_t status = kStatus_USB_Success; + switch (eventCode) + { + case kUSB_HostEventAttach: + KPrintf("usb device attached\n"); + status = USB_HostMsdEvent(deviceHandle, configurationHandle, eventCode); + break; + + case kUSB_HostEventNotSupported: + KPrintf("device not supported.\r\n"); + break; + + case kUSB_HostEventEnumerationDone: + status = USB_HostMsdEvent(deviceHandle, configurationHandle, eventCode); + break; + + case kUSB_HostEventDetach: + KPrintf("usb device detached\n"); + status = USB_HostMsdEvent(deviceHandle, configurationHandle, eventCode); + break; + + default: + break; + } + return status; +} + +static void UsbHostApplicationInit(void) +{ + usb_status_t status = kStatus_USB_Success; + + UsbHostClockInit(); + + status = USB_HostInit(CONTROLLER_ID, &g_HostHandle, UsbHostEvent); + if (status != kStatus_USB_Success) { + KPrintf("host init error\r\n"); + return; + } + UsbHostIsrEnable(); + + KPrintf("host init done\r\n"); +} + +#if defined(FS_VFS) +void UsbMountFileSystem() +{ + if (MountFilesystem(USB_BUS_NAME, USB_DEVICE_NAME, USB_DRIVER_NAME, FSTYPE_FATFS, UDISK_MOUNTPOINT) == 0) + KPrintf("Mount FAT on Udisk successful.\n"); + else + KPrintf("Mount FAT on Udisk failed.\n"); +} + +void UsbUnmountFileSystem() +{ + UnmountFileSystem(UDISK_MOUNTPOINT); +} +#endif + +static uint32 UsbHostOpen(void *dev) +{ + return EOK; +} + +static uint32 UsbHostClose(void *dev) +{ + return EOK; +} + +static uint32 UsbHostRead(void *dev, struct BusBlockReadParam *read_param) +{ + usb_status_t status; + + status = USB_HostMsdReadApi(&g_MsdCommandInstance, (uint8 *)read_param->buffer, read_param->pos, USB_SINGLE_BLOCK_SIZE, read_param->size); + if (kStatus_USB_Success == status) { + return read_param->size; + } + + return 0; +} + +static uint32 UsbHostWrite(void *dev, struct BusBlockWriteParam *write_param) +{ + usb_status_t status; + + status = USB_HostMsdWriteApi(&g_MsdCommandInstance, (const uint8 *)write_param->buffer, write_param->pos, USB_SINGLE_BLOCK_SIZE, write_param->size); + if (kStatus_USB_Success == status) { + return write_param->size; + } + + return 0; +} + +/*manage the usb device operations*/ +static const struct UsbDevDone dev_done = +{ + .open = UsbHostOpen, + .close = UsbHostClose, + .write = UsbHostWrite, + .read = UsbHostRead, +}; + +static void UsbHostTask(void* parameter) +{ + while (1) { + UsbHostTaskFn(g_HostHandle); + USB_HostMsdTask(&g_MsdCommandInstance); + } +} + +/*Init usb host bus、driver*/ +static int BoardUsbBusInit(struct UsbBus *usb_bus, struct UsbDriver *usb_driver) +{ + x_err_t ret = EOK; + + /*Init the usb bus */ + ret = UsbBusInit(usb_bus, USB_BUS_NAME); + if (EOK != ret) { + KPrintf("board_usb_init UsbBusInit error %d\n", ret); + return ERROR; + } + + /*Init the usb driver*/ + ret = UsbDriverInit(usb_driver, USB_DRIVER_NAME); + if (EOK != ret){ + KPrintf("board_usb_init UsbDriverInit error %d\n", ret); + return ERROR; + } + + /*Attach the usb driver to the usb bus*/ + ret = UsbDriverAttachToBus(USB_DRIVER_NAME, USB_BUS_NAME); + if (EOK != ret) { + KPrintf("board_usb_init USEDriverAttachToBus error %d\n", ret); + return ERROR; + } + + return ret; +} + +/*Attach the usb device to the usb bus*/ +static int BoardUsbDevBend(void) +{ + x_err_t ret = EOK; + static struct UsbHardwareDevice usb_device; + memset(&usb_device, 0, sizeof(struct UsbHardwareDevice)); + + usb_device.dev_done = &dev_done; + + ret = USBDeviceRegister(&usb_device, NONE, USB_DEVICE_NAME); + if (EOK != ret) { + KPrintf("USBDeviceRegister device %s error %d\n", USB_DEVICE_NAME, ret); + return ERROR; + } + + ret = USBDeviceAttachToBus(USB_DEVICE_NAME, USB_BUS_NAME); + if (EOK != ret) { + KPrintf("USBDeviceAttachToBus device %s error %d\n", USB_DEVICE_NAME, ret); + return ERROR; + } + + return ret; +} + +/*RT1052 BOARD USB INIT*/ +int Imxrt1052HwUsbHostInit(void) +{ + x_err_t ret = EOK; + int32 usb_host_task = 0; + + static struct UsbBus usb_bus; + memset(&usb_bus, 0, sizeof(struct UsbBus)); + + static struct UsbDriver usb_driver; + memset(&usb_driver, 0, sizeof(struct UsbDriver)); + + UsbHostApplicationInit(); + + ret = BoardUsbBusInit(&usb_bus, &usb_driver); + if (EOK != ret) { + KPrintf("BoardUsbBusInit error ret %u\n", ret); + return ERROR; + } + + ret = BoardUsbDevBend(); + if (EOK != ret) { + KPrintf("BoardUsbDevBend error ret %u\n", ret); + return ERROR; + } + + usb_host_task = KTaskCreate("usbh", UsbHostTask, NONE, + USB_HOST_STACK_SIZE, 8); + if(usb_host_task < 0) { + KPrintf("usb_host_task create failed ...%s %d.\n", __FUNCTION__,__LINE__); + return ERROR; + } + + StartupKTask(usb_host_task); + + return ret; +} + +#endif diff --git a/Ubiquitous/XiZi/board/xidatong/xip/Makefile b/Ubiquitous/XiZi/board/xidatong/xip/Makefile new file mode 100755 index 0000000..e27f955 --- /dev/null +++ b/Ubiquitous/XiZi/board/xidatong/xip/Makefile @@ -0,0 +1,3 @@ +SRC_FILES := fsl_flexspi_nor_boot.c fsl_flexspi_nor_flash.c + +include $(KERNEL_ROOT)/compiler.mk diff --git a/Ubiquitous/XiZi/board/xidatong/xip/fsl_flexspi_nor_boot.c b/Ubiquitous/XiZi/board/xidatong/xip/fsl_flexspi_nor_boot.c new file mode 100644 index 0000000..503d568 --- /dev/null +++ b/Ubiquitous/XiZi/board/xidatong/xip/fsl_flexspi_nor_boot.c @@ -0,0 +1,1149 @@ +/* + * Copyright 2017 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/** +* @file fsl_flexspi_nor_boot.c +* @brief support to register flexspi image vector table +* @version 2.0 +* @author AIIT XUOS Lab +* @date 2022-03-22 +*/ + +#include "fsl_flexspi_nor_boot.h" + +#if defined(__CC_ARM) || defined(__GNUC__) + __attribute__((section(".boot_hdr.ivt"))) +#elif defined(__ICCARM__) +#pragma location=".boot_hdr.ivt" +#endif + +const ivt image_vector_table = { + IVT_HEADER, /* IVT Header */ + 0x60002000, /* Image Entry Function */ + IVT_RSVD, /* Reserved = 0 */ + (uint32_t)DCD_ADDRESS, /* Address where DCD information is stored */ + (uint32_t)BOOT_DATA_ADDRESS, /* Address where BOOT Data Structure is stored */ + (uint32_t)&image_vector_table, /* Pointer to IVT Self (absolute address */ + (uint32_t)CSF_ADDRESS, /* Address where CSF file is stored */ + IVT_RSVD /* Reserved = 0 */ +}; + +#if defined(__CC_ARM) || defined(__GNUC__) + __attribute__((section(".boot_hdr.boot_data"))) +#elif defined(__ICCARM__) +#pragma location=".boot_hdr.boot_data" +#endif + +const BOOT_DATA_T boot_data = { + FLASH_BASE, /* boot start location */ + (FLASH_END-FLASH_BASE), /* size */ + PLUGIN_FLAG, /* Plugin flag*/ + 0xFFFFFFFF /* empty - extra data word */ +}; + +#if defined(__CC_ARM) || defined(__GNUC__) + __attribute__((section(".boot_hdr.dcd_data"))) +#elif defined(__ICCARM__) +#pragma location=".boot_hdr.dcd_data" +#endif + +const uint8_t dcd_sdram[1072] = { + /*0000*/ 0xD2, + 0x04, + 0x30, + 0x41, + 0xCC, + 0x03, + 0xAC, + 0x04, + 0x40, + 0x0F, + 0xC0, + 0x68, + 0xFF, + 0xFF, + 0xFF, + 0xFF, + /*0010*/ 0x40, + 0x0F, + 0xC0, + 0x6C, + 0xFF, + 0xFF, + 0xFF, + 0xFF, + 0x40, + 0x0F, + 0xC0, + 0x70, + 0xFF, + 0xFF, + 0xFF, + 0xFF, + /*0020*/ 0x40, + 0x0F, + 0xC0, + 0x74, + 0xFF, + 0xFF, + 0xFF, + 0xFF, + 0x40, + 0x0F, + 0xC0, + 0x78, + 0xFF, + 0xFF, + 0xFF, + 0xFF, + /*0030*/ 0x40, + 0x0F, + 0xC0, + 0x7C, + 0xFF, + 0xFF, + 0xFF, + 0xFF, + 0x40, + 0x0F, + 0xC0, + 0x80, + 0xFF, + 0xFF, + 0xFF, + 0xFF, + /*0040*/ 0x40, + 0x0D, + 0x80, + 0x30, + 0x00, + 0x00, + 0x20, + 0x01, + 0x40, + 0x0D, + 0x81, + 0x00, + 0x00, + 0x1D, + 0x00, + 0x00, + /*0050*/ 0x40, + 0x0F, + 0xC0, + 0x14, + 0x00, + 0x01, + 0x0D, + 0x40, + 0x40, + 0x1F, + 0x80, + 0x14, + 0x00, + 0x00, + 0x00, + 0x00, + /*0060*/ 0x40, + 0x1F, + 0x80, + 0x18, + 0x00, + 0x00, + 0x00, + 0x00, + 0x40, + 0x1F, + 0x80, + 0x1C, + 0x00, + 0x00, + 0x00, + 0x00, + /*0070*/ 0x40, + 0x1F, + 0x80, + 0x20, + 0x00, + 0x00, + 0x00, + 0x00, + 0x40, + 0x1F, + 0x80, + 0x24, + 0x00, + 0x00, + 0x00, + 0x00, + /*0080*/ 0x40, + 0x1F, + 0x80, + 0x28, + 0x00, + 0x00, + 0x00, + 0x00, + 0x40, + 0x1F, + 0x80, + 0x2C, + 0x00, + 0x00, + 0x00, + 0x00, + /*0090*/ 0x40, + 0x1F, + 0x80, + 0x30, + 0x00, + 0x00, + 0x00, + 0x00, + 0x40, + 0x1F, + 0x80, + 0x34, + 0x00, + 0x00, + 0x00, + 0x00, + /*00a0*/ 0x40, + 0x1F, + 0x80, + 0x38, + 0x00, + 0x00, + 0x00, + 0x00, + 0x40, + 0x1F, + 0x80, + 0x3C, + 0x00, + 0x00, + 0x00, + 0x00, + /*00b0*/ 0x40, + 0x1F, + 0x80, + 0x40, + 0x00, + 0x00, + 0x00, + 0x00, + 0x40, + 0x1F, + 0x80, + 0x44, + 0x00, + 0x00, + 0x00, + 0x00, + /*00c0*/ 0x40, + 0x1F, + 0x80, + 0x48, + 0x00, + 0x00, + 0x00, + 0x00, + 0x40, + 0x1F, + 0x80, + 0x4C, + 0x00, + 0x00, + 0x00, + 0x00, + /*00d0*/ 0x40, + 0x1F, + 0x80, + 0x50, + 0x00, + 0x00, + 0x00, + 0x00, + 0x40, + 0x1F, + 0x80, + 0x54, + 0x00, + 0x00, + 0x00, + 0x00, + /*00e0*/ 0x40, + 0x1F, + 0x80, + 0x58, + 0x00, + 0x00, + 0x00, + 0x00, + 0x40, + 0x1F, + 0x80, + 0x5C, + 0x00, + 0x00, + 0x00, + 0x00, + /*00f0*/ 0x40, + 0x1F, + 0x80, + 0x60, + 0x00, + 0x00, + 0x00, + 0x00, + 0x40, + 0x1F, + 0x80, + 0x64, + 0x00, + 0x00, + 0x00, + 0x00, + /*0100*/ 0x40, + 0x1F, + 0x80, + 0x68, + 0x00, + 0x00, + 0x00, + 0x00, + 0x40, + 0x1F, + 0x80, + 0x6C, + 0x00, + 0x00, + 0x00, + 0x00, + /*0110*/ 0x40, + 0x1F, + 0x80, + 0x70, + 0x00, + 0x00, + 0x00, + 0x00, + 0x40, + 0x1F, + 0x80, + 0x74, + 0x00, + 0x00, + 0x00, + 0x00, + /*0120*/ 0x40, + 0x1F, + 0x80, + 0x78, + 0x00, + 0x00, + 0x00, + 0x00, + 0x40, + 0x1F, + 0x80, + 0x7C, + 0x00, + 0x00, + 0x00, + 0x00, + /*0130*/ 0x40, + 0x1F, + 0x80, + 0x80, + 0x00, + 0x00, + 0x00, + 0x00, + 0x40, + 0x1F, + 0x80, + 0x84, + 0x00, + 0x00, + 0x00, + 0x00, + /*0140*/ 0x40, + 0x1F, + 0x80, + 0x88, + 0x00, + 0x00, + 0x00, + 0x00, + 0x40, + 0x1F, + 0x80, + 0x8C, + 0x00, + 0x00, + 0x00, + 0x00, + /*0150*/ 0x40, + 0x1F, + 0x80, + 0x90, + 0x00, + 0x00, + 0x00, + 0x00, + 0x40, + 0x1F, + 0x80, + 0x94, + 0x00, + 0x00, + 0x00, + 0x00, + /*0160*/ 0x40, + 0x1F, + 0x80, + 0x98, + 0x00, + 0x00, + 0x00, + 0x00, + 0x40, + 0x1F, + 0x80, + 0x9C, + 0x00, + 0x00, + 0x00, + 0x00, + /*0170*/ 0x40, + 0x1F, + 0x80, + 0xA0, + 0x00, + 0x00, + 0x00, + 0x00, + 0x40, + 0x1F, + 0x80, + 0xA4, + 0x00, + 0x00, + 0x00, + 0x00, + /*0180*/ 0x40, + 0x1F, + 0x80, + 0xA8, + 0x00, + 0x00, + 0x00, + 0x00, + 0x40, + 0x1F, + 0x80, + 0xAC, + 0x00, + 0x00, + 0x00, + 0x00, + /*0190*/ 0x40, + 0x1F, + 0x80, + 0xB0, + 0x00, + 0x00, + 0x00, + 0x10, + 0x40, + 0x1F, + 0x80, + 0xB4, + 0x00, + 0x00, + 0x00, + 0x00, + /*01a0*/ 0x40, + 0x1F, + 0x80, + 0xB8, + 0x00, + 0x00, + 0x00, + 0x00, + 0x40, + 0x1F, + 0x82, + 0x04, + 0x00, + 0x01, + 0x10, + 0xF9, + /*01b0*/ 0x40, + 0x1F, + 0x82, + 0x08, + 0x00, + 0x01, + 0x10, + 0xF9, + 0x40, + 0x1F, + 0x82, + 0x0C, + 0x00, + 0x01, + 0x10, + 0xF9, + /*01c0*/ 0x40, + 0x1F, + 0x82, + 0x10, + 0x00, + 0x01, + 0x10, + 0xF9, + 0x40, + 0x1F, + 0x82, + 0x14, + 0x00, + 0x01, + 0x10, + 0xF9, + /*01d0*/ 0x40, + 0x1F, + 0x82, + 0x18, + 0x00, + 0x01, + 0x10, + 0xF9, + 0x40, + 0x1F, + 0x82, + 0x1C, + 0x00, + 0x01, + 0x10, + 0xF9, + /*01e0*/ 0x40, + 0x1F, + 0x82, + 0x20, + 0x00, + 0x01, + 0x10, + 0xF9, + 0x40, + 0x1F, + 0x82, + 0x24, + 0x00, + 0x01, + 0x10, + 0xF9, + /*01f0*/ 0x40, + 0x1F, + 0x82, + 0x28, + 0x00, + 0x01, + 0x10, + 0xF9, + 0x40, + 0x1F, + 0x82, + 0x2C, + 0x00, + 0x01, + 0x10, + 0xF9, + /*0200*/ 0x40, + 0x1F, + 0x82, + 0x30, + 0x00, + 0x01, + 0x10, + 0xF9, + 0x40, + 0x1F, + 0x82, + 0x34, + 0x00, + 0x01, + 0x10, + 0xF9, + /*0210*/ 0x40, + 0x1F, + 0x82, + 0x38, + 0x00, + 0x01, + 0x10, + 0xF9, + 0x40, + 0x1F, + 0x82, + 0x3C, + 0x00, + 0x01, + 0x10, + 0xF9, + /*0220*/ 0x40, + 0x1F, + 0x82, + 0x40, + 0x00, + 0x01, + 0x10, + 0xF9, + 0x40, + 0x1F, + 0x82, + 0x44, + 0x00, + 0x01, + 0x10, + 0xF9, + /*0230*/ 0x40, + 0x1F, + 0x82, + 0x48, + 0x00, + 0x01, + 0x10, + 0xF9, + 0x40, + 0x1F, + 0x82, + 0x4C, + 0x00, + 0x01, + 0x10, + 0xF9, + /*0240*/ 0x40, + 0x1F, + 0x82, + 0x50, + 0x00, + 0x01, + 0x10, + 0xF9, + 0x40, + 0x1F, + 0x82, + 0x54, + 0x00, + 0x01, + 0x10, + 0xF9, + /*0250*/ 0x40, + 0x1F, + 0x82, + 0x58, + 0x00, + 0x01, + 0x10, + 0xF9, + 0x40, + 0x1F, + 0x82, + 0x5C, + 0x00, + 0x01, + 0x10, + 0xF9, + /*0260*/ 0x40, + 0x1F, + 0x82, + 0x60, + 0x00, + 0x01, + 0x10, + 0xF9, + 0x40, + 0x1F, + 0x82, + 0x64, + 0x00, + 0x01, + 0x10, + 0xF9, + /*0270*/ 0x40, + 0x1F, + 0x82, + 0x68, + 0x00, + 0x01, + 0x10, + 0xF9, + 0x40, + 0x1F, + 0x82, + 0x6C, + 0x00, + 0x01, + 0x10, + 0xF9, + /*0280*/ 0x40, + 0x1F, + 0x82, + 0x70, + 0x00, + 0x01, + 0x10, + 0xF9, + 0x40, + 0x1F, + 0x82, + 0x74, + 0x00, + 0x01, + 0x10, + 0xF9, + /*0290*/ 0x40, + 0x1F, + 0x82, + 0x78, + 0x00, + 0x01, + 0x10, + 0xF9, + 0x40, + 0x1F, + 0x82, + 0x7C, + 0x00, + 0x01, + 0x10, + 0xF9, + /*02a0*/ 0x40, + 0x1F, + 0x82, + 0x80, + 0x00, + 0x01, + 0x10, + 0xF9, + 0x40, + 0x1F, + 0x82, + 0x84, + 0x00, + 0x01, + 0x10, + 0xF9, + /*02b0*/ 0x40, + 0x1F, + 0x82, + 0x88, + 0x00, + 0x01, + 0x10, + 0xF9, + 0x40, + 0x1F, + 0x82, + 0x8C, + 0x00, + 0x01, + 0x10, + 0xF9, + /*02c0*/ 0x40, + 0x1F, + 0x82, + 0x90, + 0x00, + 0x01, + 0x10, + 0xF9, + 0x40, + 0x1F, + 0x82, + 0x94, + 0x00, + 0x01, + 0x10, + 0xF9, + /*02d0*/ 0x40, + 0x1F, + 0x82, + 0x98, + 0x00, + 0x01, + 0x10, + 0xF9, + 0x40, + 0x1F, + 0x82, + 0x9C, + 0x00, + 0x01, + 0x10, + 0xF9, + /*02e0*/ 0x40, + 0x1F, + 0x82, + 0xA0, + 0x00, + 0x01, + 0x10, + 0xF9, + 0x40, + 0x1F, + 0x82, + 0xA4, + 0x00, + 0x01, + 0x10, + 0xF9, + /*02f0*/ 0x40, + 0x1F, + 0x82, + 0xA8, + 0x00, + 0x01, + 0x10, + 0xF9, + 0x40, + 0x2F, + 0x00, + 0x00, + 0x10, + 0x00, + 0x00, + 0x04, + /*0300*/ 0x40, + 0x2F, + 0x00, + 0x08, + 0x00, + 0x03, + 0x05, + 0x24, + 0x40, + 0x2F, + 0x00, + 0x0C, + 0x06, + 0x03, + 0x05, + 0x24, + /*0310*/ 0x40, + 0x2F, + 0x00, + 0x10, + 0x80, + 0x00, + 0x00, + 0x1B, + 0x40, + 0x2F, + 0x00, + 0x14, + 0x82, + 0x00, + 0x00, + 0x1B, + /*0320*/ 0x40, + 0x2F, + 0x00, + 0x18, + 0x84, + 0x00, + 0x00, + 0x1B, + 0x40, + 0x2F, + 0x00, + 0x1C, + 0x86, + 0x00, + 0x00, + 0x1B, + /*0330*/ 0x40, + 0x2F, + 0x00, + 0x20, + 0x90, + 0x00, + 0x00, + 0x21, + 0x40, + 0x2F, + 0x00, + 0x24, + 0xA0, + 0x00, + 0x00, + 0x19, + /*0340*/ 0x40, + 0x2F, + 0x00, + 0x28, + 0xA8, + 0x00, + 0x00, + 0x17, + 0x40, + 0x2F, + 0x00, + 0x2C, + 0xA9, + 0x00, + 0x00, + 0x1B, + /*0350*/ 0x40, + 0x2F, + 0x00, + 0x30, + 0x00, + 0x00, + 0x00, + 0x21, + 0x40, + 0x2F, + 0x00, + 0x04, + 0x00, + 0x00, + 0x79, + 0xA8, + /*0360*/ 0x40, + 0x2F, + 0x00, + 0x40, + 0x00, + 0x00, + 0x0F, + 0x31, + 0x40, + 0x2F, + 0x00, + 0x44, + 0x00, + 0x65, + 0x29, + 0x22, + /*0370*/ 0x40, + 0x2F, + 0x00, + 0x48, + 0x00, + 0x01, + 0x09, + 0x20, + 0x40, + 0x2F, + 0x00, + 0x4C, + 0x50, + 0x21, + 0x0A, + 0x08, + /*0380*/ 0x40, + 0x2F, + 0x00, + 0x80, + 0x00, + 0x00, + 0x00, + 0x21, + 0x40, + 0x2F, + 0x00, + 0x84, + 0x00, + 0x88, + 0x88, + 0x88, + /*0390*/ 0x40, + 0x2F, + 0x00, + 0x94, + 0x00, + 0x00, + 0x00, + 0x02, + 0x40, + 0x2F, + 0x00, + 0x98, + 0x00, + 0x00, + 0x00, + 0x00, + /*03a0*/ 0x40, + 0x2F, + 0x00, + 0x90, + 0x80, + 0x00, + 0x00, + 0x00, + 0x40, + 0x2F, + 0x00, + 0x9C, + 0xA5, + 0x5A, + 0x00, + 0x0F, + /*03b0*/ 0xCF, + 0x00, + 0x0C, + 0x1C, + 0x40, + 0x2F, + 0x00, + 0x3C, + 0x00, + 0x00, + 0x00, + 0x01, + 0xCC, + 0x00, + 0x14, + 0x04, + /*03c0*/ 0x40, + 0x2F, + 0x00, + 0x90, + 0x80, + 0x00, + 0x00, + 0x00, + 0x40, + 0x2F, + 0x00, + 0x9C, + 0xA5, + 0x5A, + 0x00, + 0x0C, + /*03d0*/ 0xCF, + 0x00, + 0x0C, + 0x1C, + 0x40, + 0x2F, + 0x00, + 0x3C, + 0x00, + 0x00, + 0x00, + 0x01, + 0xCC, + 0x00, + 0x14, + 0x04, + /*03e0*/ 0x40, + 0x2F, + 0x00, + 0x90, + 0x80, + 0x00, + 0x00, + 0x00, + 0x40, + 0x2F, + 0x00, + 0x9C, + 0xA5, + 0x5A, + 0x00, + 0x0C, + /*03f0*/ 0xCF, + 0x00, + 0x0C, + 0x1C, + 0x40, + 0x2F, + 0x00, + 0x3C, + 0x00, + 0x00, + 0x00, + 0x01, + 0xCC, + 0x00, + 0x1C, + 0x04, + /*0400*/ 0x40, + 0x2F, + 0x00, + 0xA0, + 0x00, + 0x00, + 0x00, + 0x33, + 0x40, + 0x2F, + 0x00, + 0x90, + 0x80, + 0x00, + 0x00, + 0x00, + /*0410*/ 0x40, + 0x2F, + 0x00, + 0x9C, + 0xA5, + 0x5A, + 0x00, + 0x0A, + 0xCF, + 0x00, + 0x0C, + 0x1C, + 0x40, + 0x2F, + 0x00, + 0x3C, + /*0420*/ 0x00, + 0x00, + 0x00, + 0x01, + 0xCC, + 0x00, + 0x0C, + 0x04, + 0x40, + 0x2F, + 0x00, + 0x4C, + 0x50, + 0x07, + 0x0A, + 0x09, +}; diff --git a/Ubiquitous/XiZi/board/xidatong/xip/fsl_flexspi_nor_boot.h b/Ubiquitous/XiZi/board/xidatong/xip/fsl_flexspi_nor_boot.h new file mode 100644 index 0000000..b6677b2 --- /dev/null +++ b/Ubiquitous/XiZi/board/xidatong/xip/fsl_flexspi_nor_boot.h @@ -0,0 +1,123 @@ +/* + * Copyright 2017 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/** +* @file fsl_flexspi_nor_boot.h +* @brief support to register flexspi image vector table +* @version 2.0 +* @author AIIT XUOS Lab +* @date 2022-03-22 +*/ + +#ifndef _QUADSPI_BOOT_H_ +#define _QUADSPI_BOOT_H_ + +#include + +/************************************* + * IVT Data + *************************************/ +typedef struct _ivt_ { + /** @ref hdr with tag #HAB_TAG_IVT, length and HAB version fields + * (see @ref data) + */ + uint32_t hdr; + /** Absolute address of the first instruction to execute from the + * image + */ + uint32_t entry; + /** Reserved in this version of HAB: should be NULL. */ + uint32_t reserved1; + /** Absolute address of the image DCD: may be NULL. */ + uint32_t dcd; + /** Absolute address of the Boot Data: may be NULL, but not interpreted + * any further by HAB + */ + uint32_t boot_data; + /** Absolute address of the IVT.*/ + uint32_t self; + /** Absolute address of the image CSF.*/ + uint32_t csf; + /** Reserved in this version of HAB: should be zero. */ + uint32_t reserved2; +} ivt; + +#define IVT_MAJOR_VERSION 0x4 +#define IVT_MAJOR_VERSION_SHIFT 0x4 +#define IVT_MAJOR_VERSION_MASK 0xF +#define IVT_MINOR_VERSION 0x1 +#define IVT_MINOR_VERSION_SHIFT 0x0 +#define IVT_MINOR_VERSION_MASK 0xF + +#define IVT_VERSION(major, minor) \ + ((((major) & IVT_MAJOR_VERSION_MASK) << IVT_MAJOR_VERSION_SHIFT) | \ + (((minor) & IVT_MINOR_VERSION_MASK) << IVT_MINOR_VERSION_SHIFT)) + +#define IVT_TAG_HEADER (0xD1) /**< Image Vector Table */ +#define IVT_SIZE 0x2000 +#define IVT_PAR IVT_VERSION(IVT_MAJOR_VERSION, IVT_MINOR_VERSION) + +#define IVT_HEADER (IVT_TAG_HEADER | (IVT_SIZE << 8) | (IVT_PAR << 24)) +#define IVT_RSVD (uint32_t)(0x00000000) + + +/************************************* + * Boot Data + *************************************/ +typedef struct _boot_data_ { + uint32_t start; /* boot start location */ + uint32_t size; /* size */ + uint32_t plugin; /* plugin flag - 1 if downloaded application is plugin */ + uint32_t placeholder; /* placehoder to make even 0x10 size */ +}BOOT_DATA_T; + + +/************************************* + * DCD Data + *************************************/ +#define DCD_TAG_HEADER (0xD2) +#define DCD_TAG_HEADER_SHIFT (24) +#define DCD_VERSION (0x40) +#define DCD_ARRAY_SIZE 1 + +#define FLASH_BASE 0x60000000 +#define FLASH_END 0x7F7FFFFF +#define SCLK 1 + +#define DCD_ADDRESS dcd_sdram +#define BOOT_DATA_ADDRESS &boot_data +#define CSF_ADDRESS 0 +#define PLUGIN_FLAG (uint32_t)0 + +/* External Variables */ +//extern const uint8_t dcd_sdram[1044]; +extern const uint8_t dcd_sdram[1072]; +extern const BOOT_DATA_T boot_data; + +#endif diff --git a/Ubiquitous/XiZi/board/xidatong/xip/fsl_flexspi_nor_flash.c b/Ubiquitous/XiZi/board/xidatong/xip/fsl_flexspi_nor_flash.c new file mode 100644 index 0000000..c5cc52d --- /dev/null +++ b/Ubiquitous/XiZi/board/xidatong/xip/fsl_flexspi_nor_flash.c @@ -0,0 +1,88 @@ +/* + * Copyright 2017 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/** +* @file fsl_flexspi_nor_flash.c +* @brief support to define flexspi flash config +* @version 2.0 +* @author AIIT XUOS Lab +* @date 2022-03-22 +*/ + +#include "fsl_flexspi_nor_flash.h" + +/******************************************************************************* + * Code + ******************************************************************************/ +#if defined(__CC_ARM) || defined(__GNUC__) + __attribute__((section(".boot_hdr.conf"))) +#elif defined(__ICCARM__) +#pragma location=".boot_hdr.conf" +#endif + +const flexspi_nor_config_t Qspiflash_config = +{ + .memConfig = + { + .tag = FLEXSPI_CFG_BLK_TAG, + .version = FLEXSPI_CFG_BLK_VERSION, + .readSampleClkSrc = kFlexSPIReadSampleClk_LoopbackInternally, + .csHoldTime = 3u, + .csSetupTime = 3u, + .deviceModeCfgEnable = true, + .deviceModeType = 1,//Quad Enable command + .deviceModeSeq.seqNum = 1, + .deviceModeSeq.seqId = 4, + .deviceModeArg = 0x000200,//Set QE + .deviceType = kFlexSpiDeviceType_SerialNOR, + .sflashPadType = kSerialFlash_4Pads, + .serialClkFreq = kFlexSpiSerialClk_60MHz,//80MHz for Winbond, 100MHz for GD, 133MHz for ISSI + .sflashA1Size = 16u * 1024u * 1024u,//4MBytes + .dataValidTime = {16u, 16u}, + .lookupTable = + { +// //Fast Read Sequence +// [0] = FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x0B, RADDR_SDR, FLEXSPI_1PAD, 0x18), +// [1] = FLEXSPI_LUT_SEQ(DUMMY_SDR, FLEXSPI_1PAD, 0x08, READ_SDR, FLEXSPI_1PAD, 0x08), +// [2] = FLEXSPI_LUT_SEQ(JMP_ON_CS, 0, 0, 0, 0, 0), + //Quad Input/output read sequence + [0] = FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0xEB, RADDR_SDR, FLEXSPI_4PAD, 0x18), + [1] = FLEXSPI_LUT_SEQ(DUMMY_SDR, FLEXSPI_4PAD, 0x06, READ_SDR, FLEXSPI_4PAD, 0x04), + [2] = FLEXSPI_LUT_SEQ(0, 0, 0, 0, 0, 0), + //Read Status + [1*4] = FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x05, READ_SDR, FLEXSPI_1PAD, 0x04), + //Write Enable + [3*4] = FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x06, STOP, 0, 0), + //Write status + [4*4] = FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x01, WRITE_SDR, FLEXSPI_1PAD, 0x2), + }, + }, + .pageSize = 256u, + .sectorSize = 4u * 1024u, +}; diff --git a/Ubiquitous/XiZi/board/xidatong/xip/fsl_flexspi_nor_flash.h b/Ubiquitous/XiZi/board/xidatong/xip/fsl_flexspi_nor_flash.h new file mode 100644 index 0000000..73d4547 --- /dev/null +++ b/Ubiquitous/XiZi/board/xidatong/xip/fsl_flexspi_nor_flash.h @@ -0,0 +1,303 @@ +/* + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * + * Redistribution and use in source and binary forms, with or without + * modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this + * list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, + * this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of Freescale Semiconductor, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/** +* @file fsl_flexspi_nor_flash.h +* @brief support to define flexspi flash config +* @version 2.0 +* @author AIIT XUOS Lab +* @date 2022-03-22 +*/ + +#ifndef __FLEXSPI_NOR_FLASH_H__ +#define __FLEXSPI_NOR_FLASH_H__ + +#include +#include +#include "fsl_common.h" + +/* FLEXSPI memory config block related defintions */ +#define FLEXSPI_CFG_BLK_TAG (0x42464346UL) // ascii "FCFB" Big Endian +#define FLEXSPI_CFG_BLK_VERSION (0x56010400UL) // V1.4.0 +#define FLEXSPI_CFG_BLK_SIZE (512) + +/* FLEXSPI Feature related definitions */ +#define FLEXSPI_FEATURE_HAS_PARALLEL_MODE 1 + +/* Lookup table related defintions */ +#define CMD_INDEX_READ 0 +#define CMD_INDEX_READSTATUS 1 +#define CMD_INDEX_WRITEENABLE 2 +#define CMD_INDEX_WRITE 4 + +#define CMD_LUT_SEQ_IDX_READ 0 +#define CMD_LUT_SEQ_IDX_READSTATUS 1 +#define CMD_LUT_SEQ_IDX_WRITEENABLE 3 +#define CMD_LUT_SEQ_IDX_WRITE 9 + +#define CMD_SDR 0x01 +#define CMD_DDR 0x21 +#define RADDR_SDR 0x02 +#define RADDR_DDR 0x22 +#define CADDR_SDR 0x03 +#define CADDR_DDR 0x23 +#define MODE1_SDR 0x04 +#define MODE1_DDR 0x24 +#define MODE2_SDR 0x05 +#define MODE2_DDR 0x25 +#define MODE4_SDR 0x06 +#define MODE4_DDR 0x26 +#define MODE8_SDR 0x07 +#define MODE8_DDR 0x27 +#define WRITE_SDR 0x08 +#define WRITE_DDR 0x28 +#define READ_SDR 0x09 +#define READ_DDR 0x29 +#define LEARN_SDR 0x0A +#define LEARN_DDR 0x2A +#define DATSZ_SDR 0x0B +#define DATSZ_DDR 0x2B +#define DUMMY_SDR 0x0C +#define DUMMY_DDR 0x2C +#define DUMMY_RWDS_SDR 0x0D +#define DUMMY_RWDS_DDR 0x2D +#define JMP_ON_CS 0x1F +#define STOP 0 + +#define FLEXSPI_1PAD 0 +#define FLEXSPI_2PAD 1 +#define FLEXSPI_4PAD 2 +#define FLEXSPI_8PAD 3 + +#define FLEXSPI_LUT_SEQ(cmd0, pad0, op0, cmd1, pad1, op1) \ + (FLEXSPI_LUT_OPERAND0(op0) | FLEXSPI_LUT_NUM_PADS0(pad0) | FLEXSPI_LUT_OPCODE0(cmd0) | FLEXSPI_LUT_OPERAND1(op1) | \ + FLEXSPI_LUT_NUM_PADS1(pad1) | FLEXSPI_LUT_OPCODE1(cmd1)) + +//!@brief Definitions for FlexSPI Serial Clock Frequency +typedef enum _FlexSpiSerialClockFreq +{ + kFlexSpiSerialClk_30MHz = 1, + kFlexSpiSerialClk_50MHz = 2, + kFlexSpiSerialClk_60MHz = 3, + kFlexSpiSerialClk_75MHz = 4, + kFlexSpiSerialClk_80MHz = 5, + kFlexSpiSerialClk_100MHz = 6, + kFlexSpiSerialClk_133MHz = 7, + kFlexSpiSerialClk_166MHz = 8, + kFlexSpiSerialClk_200MHz = 9, +} flexspi_serial_clk_freq_t; + +//!@brief FlexSPI clock configuration type +enum +{ + kFlexSpiClk_SDR, //!< Clock configure for SDR mode + kFlexSpiClk_DDR, //!< Clock configurat for DDR mode +}; + +//!@brief FlexSPI Read Sample Clock Source definition +typedef enum _FlashReadSampleClkSource +{ + kFlexSPIReadSampleClk_LoopbackInternally = 0, + kFlexSPIReadSampleClk_LoopbackFromDqsPad = 1, + kFlexSPIReadSampleClk_LoopbackFromSckPad = 2, + kFlexSPIReadSampleClk_ExternalInputFromDqsPad = 3, +} flexspi_read_sample_clk_t; + + +//!@brief Misc feature bit definitions +enum +{ + kFlexSpiMiscOffset_DiffClkEnable = 0, //!< Bit for Differential clock enable + kFlexSpiMiscOffset_Ck2Enable = 1, //!< Bit for CK2 enable + kFlexSpiMiscOffset_ParallelEnable = 2, //!< Bit for Parallel mode enable + kFlexSpiMiscOffset_WordAddressableEnable = 3, //!< Bit for Word Addressable enable + kFlexSpiMiscOffset_SafeConfigFreqEnable = 4, //!< Bit for Safe Configuration Frequency enable + kFlexSpiMiscOffset_PadSettingOverrideEnable = 5, //!< Bit for Pad setting override enable + kFlexSpiMiscOffset_DdrModeEnable = 6, //!< Bit for DDR clock confiuration indication. +}; + +//!@brief Flash Type Definition +enum +{ + kFlexSpiDeviceType_SerialNOR = 1, //!< Flash devices are Serial NOR + kFlexSpiDeviceType_SerialNAND = 2, //!< Flash devices are Serial NAND + kFlexSpiDeviceType_SerialRAM = 3, //!< Flash devices are Serial RAM/HyperFLASH + kFlexSpiDeviceType_MCP_NOR_NAND = 0x12, //!< Flash device is MCP device, A1 is Serial NOR, A2 is Serial NAND + kFlexSpiDeviceType_MCP_NOR_RAM = 0x13, //!< Flash deivce is MCP device, A1 is Serial NOR, A2 is Serial RAMs +}; + +//!@brief Flash Pad Definitions +enum +{ + kSerialFlash_1Pad = 1, + kSerialFlash_2Pads = 2, + kSerialFlash_4Pads = 4, + kSerialFlash_8Pads = 8, +}; + +//!@brief FlexSPI LUT Sequence structure +typedef struct _lut_sequence +{ + uint8_t seqNum; //!< Sequence Number, valid number: 1-16 + uint8_t seqId; //!< Sequence Index, valid number: 0-15 + uint16_t reserved; +} flexspi_lut_seq_t; + +//!@brief Flash Configuration Command Type +enum +{ + kDeviceConfigCmdType_Generic, //!< Generic command, for example: configure dummy cycles, drive strength, etc + kDeviceConfigCmdType_QuadEnable, //!< Quad Enable command + kDeviceConfigCmdType_Spi2Xpi, //!< Switch from SPI to DPI/QPI/OPI mode + kDeviceConfigCmdType_Xpi2Spi, //!< Switch from DPI/QPI/OPI to SPI mode + kDeviceConfigCmdType_Spi2NoCmd, //!< Switch to 0-4-4/0-8-8 mode + kDeviceConfigCmdType_Reset, //!< Reset device command +}; + +//!@brief FlexSPI Memory Configuration Block +typedef struct _FlexSPIConfig +{ + uint32_t tag; //!< [0x000-0x003] Tag, fixed value 0x42464346UL + uint32_t version; //!< [0x004-0x007] Version,[31:24] -'V', [23:16] - Major, [15:8] - Minor, [7:0] - bugfix + uint32_t reserved0; //!< [0x008-0x00b] Reserved for future use + uint8_t readSampleClkSrc; //!< [0x00c-0x00c] Read Sample Clock Source, valid value: 0/1/3 + uint8_t csHoldTime; //!< [0x00d-0x00d] CS hold time, default value: 3 + uint8_t csSetupTime; //!< [0x00e-0x00e] CS setup time, default value: 3 + uint8_t columnAddressWidth; //!< [0x00f-0x00f] Column Address with, for HyperBus protocol, it is fixed to 3, For + //! Serial NAND, need to refer to datasheet + uint8_t deviceModeCfgEnable; //!< [0x010-0x010] Device Mode Configure enable flag, 1 - Enable, 0 - Disable + uint8_t deviceModeType; //!< [0x011-0x011] Specify the configuration command type:Quad Enable, DPI/QPI/OPI switch, + //! Generic configuration, etc. + uint16_t waitTimeCfgCommands; //!< [0x012-0x013] Wait time for all configuration commands, unit: 100us, Used for + //! DPI/QPI/OPI switch or reset command + flexspi_lut_seq_t deviceModeSeq; //!< [0x014-0x017] Device mode sequence info, [7:0] - LUT sequence id, [15:8] - LUt + //! sequence number, [31:16] Reserved + uint32_t deviceModeArg; //!< [0x018-0x01b] Argument/Parameter for device configuration + uint8_t configCmdEnable; //!< [0x01c-0x01c] Configure command Enable Flag, 1 - Enable, 0 - Disable + uint8_t configModeType[3]; //!< [0x01d-0x01f] Configure Mode Type, similar as deviceModeTpe + flexspi_lut_seq_t + configCmdSeqs[3]; //!< [0x020-0x02b] Sequence info for Device Configuration command, similar as deviceModeSeq + uint32_t reserved1; //!< [0x02c-0x02f] Reserved for future use + uint32_t configCmdArgs[3]; //!< [0x030-0x03b] Arguments/Parameters for device Configuration commands + uint32_t reserved2; //!< [0x03c-0x03f] Reserved for future use + uint32_t controllerMiscOption; //!< [0x040-0x043] Controller Misc Options, see Misc feature bit definitions for more + //! details + uint8_t deviceType; //!< [0x044-0x044] Device Type: See Flash Type Definition for more details + uint8_t sflashPadType; //!< [0x045-0x045] Serial Flash Pad Type: 1 - Single, 2 - Dual, 4 - Quad, 8 - Octal + uint8_t serialClkFreq; //!< [0x046-0x046] Serial Flash Frequencey, device specific definitions, See System Boot + //! Chapter for more details + uint8_t lutCustomSeqEnable; //!< [0x047-0x047] LUT customization Enable, it is required if the program/erase cannot + //! be done using 1 LUT sequence, currently, only applicable to HyperFLASH + uint32_t reserved3[2]; //!< [0x048-0x04f] Reserved for future use + uint32_t sflashA1Size; //!< [0x050-0x053] Size of Flash connected to A1 + uint32_t sflashA2Size; //!< [0x054-0x057] Size of Flash connected to A2 + uint32_t sflashB1Size; //!< [0x058-0x05b] Size of Flash connected to B1 + uint32_t sflashB2Size; //!< [0x05c-0x05f] Size of Flash connected to B2 + uint32_t csPadSettingOverride; //!< [0x060-0x063] CS pad setting override value + uint32_t sclkPadSettingOverride; //!< [0x064-0x067] SCK pad setting override value + uint32_t dataPadSettingOverride; //!< [0x068-0x06b] data pad setting override value + uint32_t dqsPadSettingOverride; //!< [0x06c-0x06f] DQS pad setting override value + uint32_t timeoutInMs; //!< [0x070-0x073] Timeout threshold for read status command + uint32_t commandInterval; //!< [0x074-0x077] CS deselect interval between two commands + uint16_t dataValidTime[2]; //!< [0x078-0x07b] CLK edge to data valid time for PORT A and PORT B, in terms of 0.1ns + uint16_t busyOffset; //!< [0x07c-0x07d] Busy offset, valid value: 0-31 + uint16_t busyBitPolarity; //!< [0x07e-0x07f] Busy flag polarity, 0 - busy flag is 1 when flash device is busy, 1 - + //! busy flag is 0 when flash device is busy + uint32_t lookupTable[64]; //!< [0x080-0x17f] Lookup table holds Flash command sequences + flexspi_lut_seq_t lutCustomSeq[12]; //!< [0x180-0x1af] Customizable LUT Sequences + uint32_t reserved4[4]; //!< [0x1b0-0x1bf] Reserved for future use +} flexspi_mem_config_t; + +/* */ +#define NOR_CMD_INDEX_READ CMD_INDEX_READ //!< 0 +#define NOR_CMD_INDEX_READSTATUS CMD_INDEX_READSTATUS //!< 1 +#define NOR_CMD_INDEX_WRITEENABLE CMD_INDEX_WRITEENABLE //!< 2 +#define NOR_CMD_INDEX_ERASESECTOR 3 //!< 3 +#define NOR_CMD_INDEX_PAGEPROGRAM CMD_INDEX_WRITE //!< 4 +#define NOR_CMD_INDEX_CHIPERASE 5 //!< 5 +#define NOR_CMD_INDEX_DUMMY 6 //!< 6 +#define NOR_CMD_INDEX_ERASEBLOCK 7 //!< 7 + +#define NOR_CMD_LUT_SEQ_IDX_READ CMD_LUT_SEQ_IDX_READ //!< 0 READ LUT sequence id in lookupTable stored in config block +#define NOR_CMD_LUT_SEQ_IDX_READSTATUS \ + CMD_LUT_SEQ_IDX_READSTATUS //!< 1 Read Status LUT sequence id in lookupTable stored in config block +#define NOR_CMD_LUT_SEQ_IDX_READSTATUS_XPI \ + 2 //!< 2 Read status DPI/QPI/OPI sequence id in lookupTable stored in config block +#define NOR_CMD_LUT_SEQ_IDX_WRITEENABLE \ + CMD_LUT_SEQ_IDX_WRITEENABLE //!< 3 Write Enable sequence id in lookupTable stored in config block +#define NOR_CMD_LUT_SEQ_IDX_WRITEENABLE_XPI \ + 4 //!< 4 Write Enable DPI/QPI/OPI sequence id in lookupTable stored in config block +#define NOR_CMD_LUT_SEQ_IDX_ERASESECTOR 5 //!< 5 Erase Sector sequence id in lookupTable stored in config block +#define NOR_CMD_LUT_SEQ_IDX_ERASEBLOCK 8 //!< 8 Erase Block sequence id in lookupTable stored in config block +#define NOR_CMD_LUT_SEQ_IDX_PAGEPROGRAM \ + CMD_LUT_SEQ_IDX_WRITE //!< 9 Program sequence id in lookupTable stored in config block +#define NOR_CMD_LUT_SEQ_IDX_CHIPERASE 11 //!< 11 Chip Erase sequence in lookupTable id stored in config block +#define NOR_CMD_LUT_SEQ_IDX_READ_SFDP 13 //!< 13 Read SFDP sequence in lookupTable id stored in config block +#define NOR_CMD_LUT_SEQ_IDX_RESTORE_NOCMD \ + 14 //!< 14 Restore 0-4-4/0-8-8 mode sequence id in lookupTable stored in config block +#define NOR_CMD_LUT_SEQ_IDX_EXIT_NOCMD \ + 15 //!< 15 Exit 0-4-4/0-8-8 mode sequence id in lookupTable stored in config blobk + + +/* + * Serial NOR configuration block + */ +typedef struct _flexspi_nor_config +{ + flexspi_mem_config_t memConfig; //!< Common memory configuration info via FlexSPI + uint32_t pageSize; //!< Page size of Serial NOR + uint32_t sectorSize; //!< Sector size of Serial NOR + uint8_t ipcmdSerialClkFreq; //!< Clock frequency for IP command + uint8_t isUniformBlockSize; //!< Sector/Block size is the same + uint8_t reserved0[2]; //!< Reserved for future use + uint8_t serialNorType; //!< Serial NOR Flash type: 0/1/2/3 + uint8_t needExitNoCmdMode; //!< Need to exit NoCmd mode before other IP command + uint8_t halfClkForNonReadCmd; //!< Half the Serial Clock for non-read command: true/false + uint8_t needRestoreNoCmdMode; //!< Need to Restore NoCmd mode after IP commmand execution + uint32_t blockSize; //!< Block size + uint32_t reserve2[11]; //!< Reserved for future use +} flexspi_nor_config_t; + +#ifdef __cplusplus +extern "C" { +#endif + +#ifdef __cplusplus +} +#endif + +#endif // __FLEXSPI_NOR_FLASH_H__ diff --git a/Ubiquitous/XiZi/compiler.mk b/Ubiquitous/XiZi/compiler.mk new file mode 100644 index 0000000..61727b4 --- /dev/null +++ b/Ubiquitous/XiZi/compiler.mk @@ -0,0 +1,101 @@ +SRC_DIR_TEMP :=$(SRC_DIR) +SRC_DIR:= + +CUR_DIR :=$(shell pwd) + +CFLAGS += $(CPPPATHS) +AFLAGS += $(CPPPATHS) +CXXFLAGS += $(CPPPATHS) + +CFLAGS += $(DEFINES) +AFLAGS += $(DEFINES) +CXXFLAGS += $(DEFINES) +BUILD_DIR := $(KERNEL_ROOT)/build +APP_DIR := Ubiquitous/XiZi + + +.PHONY:COMPILER +COMPILER: + @if [ "${SRC_DIR_TEMP}" != "" ]; then \ + for dir in $(SRC_DIR_TEMP);do \ + $(MAKE) -C $$dir; \ + done; \ + fi + @/bin/echo -n $(OBJS) " " >> $(KERNEL_ROOT)/build/make.obj + + +################################################ +define add_c_file +$(eval COBJ := $(1:%.c=%.o)) \ +$(eval COBJ := $(subst $(subst $(APP_DIR),,$(KERNEL_ROOT)),,$(COBJ))) \ +$(eval LOCALC := $(addprefix $(BUILD_DIR)/,$(COBJ))) \ +$(eval OBJS += $(LOCALC)) \ +$(if $(strip $(LOCALC)),$(eval $(LOCALC): $(1) + @if [ ! -d $$(@D) ]; then mkdir -p $$(@D); fi + @echo cc $$< + @/bin/echo -n $(dir $(LOCALC)) >>$(KERNEL_ROOT)/build/make.dep + @$(CROSS_COMPILE)gcc -MM $$(CFLAGS) -c $$< >>$(KERNEL_ROOT)/build/make.dep + @$(CROSS_COMPILE)gcc $$(CFLAGS) -c $$< -o $$@)) +endef + +define add_cpp_file +$(eval COBJ := $(1:%.cpp=%.o)) \ +$(eval COBJ := $(subst $(subst $(APP_DIR),,$(KERNEL_ROOT)),,$(COBJ))) \ +$(eval LOCALCPP := $(addprefix $(BUILD_DIR)/,$(COBJ))) \ +$(eval OBJS += $(LOCALCPP)) \ +$(if $(strip $(LOCALCPP)),$(eval $(LOCALCPP): $(1) + @if [ ! -d $$(@D) ]; then mkdir -p $$(@D); fi + @echo cc $$< + @/bin/echo -n $(dir $(LOCALCPP)) >>$(KERNEL_ROOT)/build/make.dep + @$(CROSS_COMPILE)g++ -MM $$(CXXFLAGS) -c $$< >>$(KERNEL_ROOT)/build/make.dep + @$(CROSS_COMPILE)g++ $$(CXXFLAGS) -c $$< -o $$@)) +endef + +define add_cc_file +$(eval COBJ := $(1:%.cc=%.o)) \ +$(eval COBJ := $(subst $(subst $(APP_DIR),,$(KERNEL_ROOT)),,$(COBJ))) \ +$(eval LOCALCPP := $(addprefix $(BUILD_DIR)/,$(COBJ))) \ +$(eval OBJS += $(LOCALCPP)) \ +$(if $(strip $(LOCALCPP)),$(eval $(LOCALCPP): $(1) + @if [ ! -d $$(@D) ]; then mkdir -p $$(@D); fi + @echo cc $$< + @/bin/echo -n $(dir $(LOCALCPP)) >>$(KERNEL_ROOT)/build/make.dep + @$(CROSS_COMPILE)g++ -MM $$(CXXFLAGS) -c $$< >>$(KERNEL_ROOT)/build/make.dep + @$(CROSS_COMPILE)g++ $$(CXXFLAGS) -c $$< -o $$@)) +endef + +define add_S_file +$(eval SOBJ := $(1:%.S=%.o)) \ +$(eval SOBJ := $(subst $(subst $(APP_DIR),,$(KERNEL_ROOT)),,$(SOBJ))) \ +$(eval LOCALS := $(addprefix $(BUILD_DIR)/,$(SOBJ))) \ +$(eval OBJS += $(LOCALS)) \ +$(if $(strip $(LOCALS)),$(eval $(LOCALS): $(1) + @if [ ! -d $$(@D) ]; then mkdir -p $$(@D); fi + @echo cc $$< + @/bin/echo -n $(dir $(LOCALC)) >>$(KERNEL_ROOT)/build/make.dep + @$(CROSS_COMPILE)gcc -MM $$(CFLAGS) -c $$< >>$(KERNEL_ROOT)/build/make.dep + @$(CROSS_COMPILE)gcc $$(AFLAGS) -c $$< -o $$@)) +endef + + + + +SRCS := $(strip $(filter %.c,$(SRC_FILES))) +$(if $(SRCS),$(foreach f,$(SRCS),$(call add_c_file,$(addprefix $(CUR_DIR)/,$(f))))) + +SRCS := $(strip $(filter %.cpp,$(SRC_FILES))) +$(if $(SRCS),$(foreach f,$(SRCS),$(call add_cpp_file,$(addprefix $(CUR_DIR)/,$(f))))) + +SRCS := $(strip $(filter %.cc,$(SRC_FILES))) +$(if $(SRCS),$(foreach f,$(SRCS),$(call add_cc_file,$(addprefix $(CUR_DIR)/,$(f))))) + +SRCS := $(strip $(filter %.S,$(SRC_FILES))) +$(if $(SRCS),$(foreach f,$(SRCS),$(call add_S_file,$(addprefix $(CUR_DIR)/,$(f))))) + + + +COMPILER:$(OBJS) + + + +-include $(KERNEL_ROOT)/build/make.dep diff --git a/Ubiquitous/XiZi/fs/Kconfig b/Ubiquitous/XiZi/fs/Kconfig new file mode 100644 index 0000000..4670355 --- /dev/null +++ b/Ubiquitous/XiZi/fs/Kconfig @@ -0,0 +1,36 @@ +menu "File system" + +menuconfig FS_VFS + bool "Using device virtual file system" + select KERNEL_MUTEX + default y + help + The device file system is a light weight virtual file system. + +if FS_VFS + source "$KERNEL_DIR/fs/iot-devicefile/Kconfig" + + config FS_VFS_FATFS + bool "Using FATFS file system" + default y + if FS_VFS_FATFS + source "$KERNEL_DIR/fs/fatfs/Kconfig" + endif + + config FS_CH376 + bool "Using CH376 file system" + default n + if FS_CH376 + source "$KERNEL_DIR/fs/compatibility_ch376/Kconfig" + endif + + config FS_LWEXT4 + bool "Using LWEXT4 file system" + default n + if FS_LWEXT4 + source "$KERNEL_DIR/fs/lwext4/Kconfig" + endif + +endif + +endmenu diff --git a/Ubiquitous/XiZi/fs/Makefile b/Ubiquitous/XiZi/fs/Makefile new file mode 100644 index 0000000..d7075e5 --- /dev/null +++ b/Ubiquitous/XiZi/fs/Makefile @@ -0,0 +1,19 @@ +SRC_DIR := + +ifeq ($(CONFIG_FS_VFS),y) + SRC_DIR += shared iot-devicefile + + ifeq ($(CONFIG_FS_VFS_FATFS),y) + SRC_DIR += fatfs + endif + + ifeq ($(CONFIG_FS_CH376),y) + SRC_DIR += compatibility_ch376 + endif + + ifeq ($(CONFIG_FS_LWEXT4),y) + SRC_DIR += lwext4 + endif +endif + +include $(KERNEL_ROOT)/compiler.mk diff --git a/Ubiquitous/XiZi/fs/compatibility_ch376/Kconfig b/Ubiquitous/XiZi/fs/compatibility_ch376/Kconfig new file mode 100644 index 0000000..e69de29 diff --git a/Ubiquitous/XiZi/fs/compatibility_ch376/Makefile b/Ubiquitous/XiZi/fs/compatibility_ch376/Makefile new file mode 100644 index 0000000..236e97b --- /dev/null +++ b/Ubiquitous/XiZi/fs/compatibility_ch376/Makefile @@ -0,0 +1,3 @@ +SRC_FILES := ch376fs.c + +include $(KERNEL_ROOT)/compiler.mk diff --git a/Ubiquitous/XiZi/fs/compatibility_ch376/ch376fs.c b/Ubiquitous/XiZi/fs/compatibility_ch376/ch376fs.c new file mode 100644 index 0000000..8543da6 --- /dev/null +++ b/Ubiquitous/XiZi/fs/compatibility_ch376/ch376fs.c @@ -0,0 +1,644 @@ +/* +* Copyright (c) 2020 AIIT XUOS Lab +* XiUOS is licensed under Mulan PSL v2. +* You can use this software according to the terms and conditions of the Mulan PSL v2. +* You may obtain a copy of Mulan PSL v2 at: +* http://license.coscl.org.cn/MulanPSL2 +* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, +* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, +* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. +* See the Mulan PSL v2 for more details. +*/ + +/** + * @file ch376fs.c + * @brief CH376 file system implementation + * @version 1.0 + * @author AIIT XUOS Lab + * @date 2021.03.18 + */ + +#include + +#define CMD_RESET_ALL 0x05 +#define CMD_CHECK_EXIST 0x06 +#define CMD_GET_FILE_SIZE 0x0C +#define CMD_SET_FILE_SIZE 0x0D +#define CMD_SET_USB_MODE 0x15 +#define CMD_RD_USB_DATA0 0x27 +#define CMD_WR_REQ_DATA 0x2D +#define CMD_SET_FILE_NAME 0x2F +#define CMD_DISK_CONNECT 0x30 +#define CMD_DISK_MOUNT 0x31 +#define CMD_FILE_OPEN 0x32 +#define CMD_FILE_ENUM_GO 0x33 +#define CMD_FILE_CREATE 0x34 +#define CMD_FILE_ERASE 0x35 +#define CMD_FILE_CLOSE 0x36 +#define CMD_DIR_INFO_READ 0x37 +#define CMD_BYTE_LOCATE 0x39 +#define CMD_BYTE_READ 0x3A +#define CMD_BYTE_RD_GO 0x3B +#define CMD_BYTE_WRITE 0x3C +#define CMD_BYTE_WR_GO 0x3D +#define CMD_DIR_CREATE 0x40 +#define CMD_WRITE_VAR32 0x0D + +#define USB_INT_SUCCESS 0x14 +#define USB_INT_DISK_READ 0x1D +#define USB_INT_DISK_WRITE 0x1E + +#define ERR_OPEN_DIR 0x41 +#define ERR_MISS_FILE 0x42 +#define ERR_FOUND_NAME 0x43 +#define ERR_FILE_CLOSE 0xB4 + +/* The flag bit for whether the folder was first opened */ +static uint8 dir_flag = 0; + +/* Save the read directory information */ +static struct Ch376FatDirInfo dir; + +/* Send the command */ +static struct BusConfigureInfo cfg; + +/* Command following parameters */ +static uint8 cmd; +static struct BusBlockWriteParam write_cmd = { + 0, + &cmd, + 1, +}; + +/* Reply to command */ +static uint8 reply; +static struct BusBlockReadParam read_reply = { + 0, + &reply, + 1, + 1, +}; + +/** + * @description: Set file or directory path + * @param bus - CH376 device bus + * @param name - path name + */ +static void SetFileName(BusType bus, uint8* name) +{ + cfg.configure_cmd = CMD_SET_FILE_NAME; + BusDrvConfigure(bus->owner_driver, &cfg); + + cmd = *name; + BusDevWriteData(bus->owner_haldev, &write_cmd); + while (cmd) { + name++; + cmd = *name; + if((cmd == 0x5c) || (cmd == 0x2f)) + cmd = 0; + BusDevWriteData(bus->owner_haldev, &write_cmd); + } +} + +/** + * @description: Back to the root directory + * @param bus - CH376 device bus + */ +static void OpenRoot(BusType bus) +{ + SetFileName(bus, "/"); + cfg.configure_cmd = CMD_FILE_OPEN; + BusDrvConfigure(bus->owner_driver, &cfg); + BusDevReadData(bus->owner_haldev, &read_reply); +} + +/** + * @description: Open file + * @param fdp - file descriptor + * @param path - path name + * @return success: EOK, failure: -ERROR + */ +static int Ch376fsOpen(struct FileDescriptor *fdp, const char *path) +{ + uint32 len, idx; + idx = 0; + len = strlen(path); + char buff[len + 1]; + strncpy(buff, path, len); + buff[len] = 0; + + for (int i = 0; i < len; i++) { + if (buff[i] == '/') { + buff[i] = 0; + SetFileName(fdp->mntp->bus, &buff[idx]); + idx = i + 1; + cfg.configure_cmd = CMD_FILE_OPEN; + BusDrvConfigure(fdp->mntp->bus->owner_driver, &cfg); + BusDevReadData(fdp->mntp->bus->owner_haldev, &read_reply); + switch (reply) { + case USB_INT_SUCCESS: + case ERR_OPEN_DIR: + break; + + case ERR_MISS_FILE: + OpenRoot(fdp->mntp->bus); + return -ERROR; + + default: + return -ERROR; + } + } + } + SetFileName(fdp->mntp->bus, &buff[idx]); + cfg.configure_cmd = CMD_FILE_OPEN; + BusDrvConfigure(fdp->mntp->bus->owner_driver, &cfg); + BusDevReadData(fdp->mntp->bus->owner_haldev, &read_reply); + switch (reply) { + case USB_INT_SUCCESS: + case ERR_OPEN_DIR: + return EOK; + + case ERR_MISS_FILE: + cfg.configure_cmd = CMD_FILE_CREATE; + BusDrvConfigure(fdp->mntp->bus->owner_driver, &cfg); + BusDevReadData(fdp->mntp->bus->owner_haldev, &read_reply); + return EOK; + + default: + return -ERROR; + } +} + +/** + * @description: Close file + * @param fdp - file descriptor + * @return success: EOK, failure: -ERROR + */ +static int Ch376fsClose(struct FileDescriptor *fdp) +{ + cfg.configure_cmd = CMD_FILE_CLOSE; + BusDrvConfigure(fdp->mntp->bus->owner_driver, &cfg); + cmd = 0x01; + BusDevWriteData(fdp->mntp->bus->owner_haldev, &write_cmd); + BusDevReadData(fdp->mntp->bus->owner_haldev, &read_reply); + if (reply == USB_INT_SUCCESS) { + OpenRoot(fdp->mntp->bus); + return EOK; + } + + return -ERROR; +} + +/** + * @description: Read file + * @param fdp - file descriptor + * @param dst - store the read data + * @param len - need data length + * @return length of data + */ +static ssize_t Ch376fsRead(struct FileDescriptor *fdp, void *dst, size_t len) +{ + ssize_t size = 0; + uint8 buff[PARAM_LEN]; + struct BusBlockReadParam read_param; + read_param.pos = 0; + read_param.buffer = buff; + + cfg.configure_cmd = CMD_BYTE_READ; + BusDrvConfigure(fdp->mntp->bus->owner_driver, &cfg); + cmd = (uint8)len; + BusDevWriteData(fdp->mntp->bus->owner_haldev, &write_cmd); + cmd = (uint8)(len >> 8); + BusDevWriteData(fdp->mntp->bus->owner_haldev, &write_cmd); + + while (1) { + BusDevReadData(fdp->mntp->bus->owner_haldev, &read_reply); + + switch (reply) { + case USB_INT_SUCCESS: + return size; + + case USB_INT_DISK_READ: + cfg.configure_cmd = CMD_RD_USB_DATA0; + BusDrvConfigure(fdp->mntp->bus->owner_driver, &cfg); + BusDevReadData(fdp->mntp->bus->owner_haldev, &read_param); + memcpy(dst + size, &buff[1], buff[0]); + size += buff[0]; + cfg.configure_cmd = CMD_BYTE_RD_GO; + BusDrvConfigure(fdp->mntp->bus->owner_driver, &cfg); + break; + + default: + return -ERROR; + } + } +} + +/** + * @description: Write file + * @param fdp - file descriptor + * @param src - store the write data + * @param len - write data length + * @return success: EOK, failure: -ERROR + */ +static ssize_t Ch376fsWrite(struct FileDescriptor *fdp, const void *src, size_t len) +{ + struct BusBlockWriteParam write_param; + char WriteBuff[len], temp[len]; + write_param.pos = 0; + write_param.buffer = WriteBuff; + size_t size = 0; + + memcpy(temp, src, len); + + cfg.configure_cmd = CMD_BYTE_WRITE; + BusDrvConfigure(fdp->mntp->bus->owner_driver, &cfg); + cmd = (uint8)len; + BusDevWriteData(fdp->mntp->bus->owner_haldev, &write_cmd); + cmd = (uint8)(len >> 8); + BusDevWriteData(fdp->mntp->bus->owner_haldev, &write_cmd); + + while (1) { + BusDevReadData(fdp->mntp->bus->owner_haldev, &read_reply); + + switch (reply) { + case USB_INT_SUCCESS: + return EOK; + + case USB_INT_DISK_WRITE: + cfg.configure_cmd = CMD_WR_REQ_DATA; + BusDrvConfigure(fdp->mntp->bus->owner_driver, &cfg); + BusDevReadData(fdp->mntp->bus->owner_haldev, &read_reply); + strncpy(WriteBuff, &temp[size], reply); + write_param.size = reply; + BusDevWriteData(fdp->mntp->bus->owner_haldev, &write_param); + size += reply; + + cfg.configure_cmd = CMD_BYTE_WR_GO; + BusDrvConfigure(fdp->mntp->bus->owner_driver, &cfg); + break; + + default: + return -ERROR; + } + } +} + +/** + * @description: Moves pointer to end of file + * @param fdp - file descriptor + * @param offset - the old offset + * @param whence - moving position + * @param new_offset - the new offset + * @return success: EOK, failure: -ERROR + */ +static int Ch376fsSeek(struct FileDescriptor *fdp, off_t offset, int whence, off_t *new_offset) +{ + cfg.configure_cmd = CMD_BYTE_LOCATE; + BusDrvConfigure(fdp->mntp->bus->owner_driver, &cfg); + + uint8 i = 4; + cmd = 0xFF; + while (i--) + BusDevWriteData(fdp->mntp->bus->owner_haldev, &write_cmd); + BusDevReadData(fdp->mntp->bus->owner_haldev, &read_reply); + if(reply == USB_INT_SUCCESS) + return EOK; + + return -ERROR; +} + +/** + * @description: Open directory + * @param fdp - file descriptor + * @param path - directory path name + * @return success: EOK, failure: -ERROR + */ +static int Ch376fsOpenDir(struct FileDescriptor *fdp, const char *path) +{ + uint32 len, idx; + idx = 0; + len = strlen(path); + char buff[len + 1]; + strncpy(buff, path, len); + buff[len] = 0; + + dir_flag = 0; + + for (int i = 0; i < len; i++) { + if(buff[i] == '/') { + buff[i] = 0; + SetFileName(fdp->mntp->bus, &buff[idx]); + idx = i + 1; + cfg.configure_cmd = CMD_FILE_OPEN; + BusDrvConfigure(fdp->mntp->bus->owner_driver, &cfg); + BusDevReadData(fdp->mntp->bus->owner_haldev, &read_reply); + switch (reply) { + case USB_INT_SUCCESS: + case ERR_OPEN_DIR: + break; + + case ERR_MISS_FILE: + OpenRoot(fdp->mntp->bus); + return -ERROR; + + default: + return -ERROR; + } + } + } + SetFileName(fdp->mntp->bus, &buff[idx]); + cfg.configure_cmd = CMD_FILE_OPEN; + BusDrvConfigure(fdp->mntp->bus->owner_driver, &cfg); + BusDevReadData(fdp->mntp->bus->owner_haldev, &read_reply); + switch (reply) { + case USB_INT_SUCCESS: + case ERR_OPEN_DIR: + return EOK; + + case ERR_MISS_FILE: + OpenRoot(fdp->mntp->bus); + return -ERROR; + + default: + return -ERROR; + } +} + +/** + * @description: Close directory + * @param fdp - file descriptor + * @return success: EOK, failure: -ERROR + */ +static int Ch376fsCloseDir(struct FileDescriptor *fdp) +{ + cfg.configure_cmd = CMD_FILE_CLOSE; + BusDrvConfigure(fdp->mntp->bus->owner_driver, &cfg); + cmd = 0x01; + BusDevWriteData(fdp->mntp->bus->owner_haldev, &write_cmd); + BusDevReadData(fdp->mntp->bus->owner_haldev, &read_reply); + dir_flag = 0; + if ((reply == ERR_FILE_CLOSE) || (reply == USB_INT_SUCCESS)) { + OpenRoot(fdp->mntp->bus); + return EOK; + } + + return -ERROR; +} + +/** + * @description: Read directory + * @param fdp - file descriptor + * @param dirent - transmit directory info + * @return success: EOK, failure: -ERROR + */ +static int Ch376fsReadDir(struct FileDescriptor *fdp, struct dirent *dirent) +{ + memset(&dir, 0, sizeof(dir)); + struct BusBlockReadParam read_param; + read_param.pos = 0; + read_param.buffer = &dir; + + if (dir_flag == 0) { + char seek[2]; + seek[0] = '*'; + seek[1] = 0x00; + + dir_flag = 1; + + SetFileName(fdp->mntp->bus, seek); + + cfg.configure_cmd = CMD_FILE_OPEN; + BusDrvConfigure(fdp->mntp->bus->owner_driver, &cfg); + goto __exit; + } + + cfg.configure_cmd = CMD_FILE_ENUM_GO; + BusDrvConfigure(fdp->mntp->bus->owner_driver, &cfg); + +__exit: + + BusDevReadData(fdp->mntp->bus->owner_haldev, &read_reply); + switch (reply) { + case USB_INT_DISK_READ: + cfg.configure_cmd = CMD_RD_USB_DATA0; + BusDrvConfigure(fdp->mntp->bus->owner_driver, &cfg); + BusDevReadData(fdp->mntp->bus->owner_haldev, &read_param); + dir.dir_attr = 0; + strncpy(dirent->d_name, dir.dir_name, 11); + return EOK; + + case ERR_MISS_FILE: + memset(dirent->d_name, 0, strlen(dirent->d_name)); + return EOK; + + default: + return -ERROR; + } +} + +/** + * @description: Create directory + * @param mp - mount point + * @param path - directory path name + * @return success: EOK, failure: -ERROR + */ +static int Ch376fsCreateDir(struct MountPoint *mp, const char *path) +{ + uint32 len, idx; + len = strlen(path); + idx = 0; + char buff[len + 1]; + strncpy(buff, path, len); + buff[len] = 0; + + for (int i = 0; i < len; i++) { + if (buff[i] == '/') { + buff[i] = 0; + SetFileName(mp->bus, &buff[idx]); + idx = i + 1; + cfg.configure_cmd = CMD_FILE_OPEN; + BusDrvConfigure(mp->bus->owner_driver, &cfg); + BusDevReadData(mp->bus->owner_haldev, &read_reply); + switch (reply) { + case USB_INT_SUCCESS: + case ERR_OPEN_DIR: + break; + + case ERR_MISS_FILE: + cfg.configure_cmd = CMD_DIR_CREATE; + BusDrvConfigure(mp->bus->owner_driver, &cfg); + BusDevReadData(mp->bus->owner_haldev, &read_reply); + break; + + default: + return ERROR; + } + } + } + + SetFileName(mp->bus, &buff[idx]); + cfg.configure_cmd = CMD_DIR_CREATE; + BusDrvConfigure(mp->bus->owner_driver, &cfg); + BusDevReadData(mp->bus->owner_haldev, &read_reply); + switch (reply) { + case USB_INT_SUCCESS: + break; + + case ERR_FOUND_NAME: + KPrintf("File of the same name exists\n"); + break; + + default: + return ERROR; + } + + OpenRoot(mp->bus); + + return EOK; +} + +/** + * @description: Create directory + * @param mp - mount point + * @param path - file path name + * @param buf - file state info + * @return EOK + */ +static int Ch376fsStat(struct MountPoint *mp, const char *path, struct FileStat *buf) +{ + strncpy(buf->name, dir.dir_name, strlen(dir.dir_name)); + if(dir.dir_ntres == 0x10) + buf->type = FTYPE_DIR; + else if(dir.dir_ntres == 0x20) + buf->type = FTYPE_FILE; + buf->size = dir.dir_file_size >> 8; + buf->mtime = 1580486400; + return EOK; +} + +/** + * @description: Mount CH376 file system + * @param mp - mount point + * @return success: EOK, failure: -ERROR + */ +static int Ch376fsMount(struct MountPoint *mp) +{ + cfg.configure_cmd = CMD_CHECK_EXIST; + BusDrvConfigure(mp->bus->owner_driver, &cfg); + cmd = 0x55; + BusDevWriteData(mp->bus->owner_haldev, &write_cmd); + BusDevReadData(mp->bus->owner_haldev, &read_reply); + if(reply != 0xAA) + goto __exit; + + cfg.configure_cmd = CMD_SET_USB_MODE; + BusDrvConfigure(mp->bus->owner_driver, &cfg); + if (mp->bus->bus_type == TYPE_SDIO_BUS) + cmd = 0x03; + else if (mp->bus->bus_type == TYPE_USB_BUS) + cmd = 0x06; + BusDevWriteData(mp->bus->owner_haldev, &write_cmd); + BusDevReadData(mp->bus->owner_haldev, &read_reply); + if(reply != 0x51) + goto __exit; + + cfg.configure_cmd = CMD_DISK_MOUNT; + BusDrvConfigure(mp->bus->owner_driver, &cfg); + BusDevReadData(mp->bus->owner_haldev, &read_reply); + if(reply != 0x14) + goto __exit; + + return EOK; + +__exit: + return -ERROR; +} + +/** + * @description: Unlink file + * @param mp - mount point + * @param path - file path name + * @return success: EOK, failure: -ERROR + */ +static int Ch376fsUnlink(struct MountPoint *mp, const char *path) +{ + uint32 len, idx; + idx = 0; + len = strlen(path); + char buff[len + 1]; + strncpy(buff, path, len); + buff[len] = 0; + + for (int i = 0; i < len; i++) { + if (buff[i] == '/') { + buff[i] = 0; + SetFileName(mp->bus, &buff[idx]); + idx = i + 1; + cfg.configure_cmd = CMD_FILE_OPEN; + BusDrvConfigure(mp->bus->owner_driver, &cfg); + BusDevReadData(mp->bus->owner_haldev, &read_reply); + switch (reply) { + case USB_INT_SUCCESS: + case ERR_OPEN_DIR: + break; + + case ERR_MISS_FILE: + default: + OpenRoot(mp->bus); + return -ERROR; + } + } + } + SetFileName(mp->bus, &buff[idx]); + cfg.configure_cmd = CMD_FILE_OPEN; + BusDrvConfigure(mp->bus->owner_driver, &cfg); + BusDevReadData(mp->bus->owner_haldev, &read_reply); + switch (reply) { + case USB_INT_SUCCESS: + case ERR_OPEN_DIR: + cfg.configure_cmd = CMD_FILE_ERASE; + BusDrvConfigure(mp->bus->owner_driver, &cfg); + BusDevReadData(mp->bus->owner_haldev, &read_reply); + OpenRoot(mp->bus); + return EOK; + + case ERR_MISS_FILE: + default: + OpenRoot(mp->bus); + return -ERROR; + } +} + +static struct Filesystem ch376fs = { + .open = Ch376fsOpen, + .close = Ch376fsClose, + .read = Ch376fsRead, + .write = Ch376fsWrite, + .seek = Ch376fsSeek, + .tell = NONE, + .truncate = NONE, + .sync = NONE, + .ioctl = NONE, + .poll = NONE, + .opendir = Ch376fsOpenDir, + .closedir = Ch376fsCloseDir, + .readdir = Ch376fsReadDir, + .seekdir = NULL, + .mount = Ch376fsMount, + .unmount = NONE, + .unlink = Ch376fsUnlink, + .rename = NONE, + .mkdir = Ch376fsCreateDir, + .stat = Ch376fsStat, + .statvfs = NONE, +}; + +/** + * @description: Init CH376 file system + * @return success: EOK, failure: other + */ +int Ch376fsInit() +{ + return RegisterFilesystem(FSTYPE_CH376, &ch376fs); +} diff --git a/Ubiquitous/XiZi/fs/compatibility_ch376/ch376fs.h b/Ubiquitous/XiZi/fs/compatibility_ch376/ch376fs.h new file mode 100644 index 0000000..aea9265 --- /dev/null +++ b/Ubiquitous/XiZi/fs/compatibility_ch376/ch376fs.h @@ -0,0 +1,49 @@ +/* +* Copyright (c) 2020 AIIT XUOS Lab +* XiUOS is licensed under Mulan PSL v2. +* You can use this software according to the terms and conditions of the Mulan PSL v2. +* You may obtain a copy of Mulan PSL v2 at: +* http://license.coscl.org.cn/MulanPSL2 +* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, +* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, +* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. +* See the Mulan PSL v2 for more details. +*/ + +/** + * @file ch376fs.h + * @brief CH376 file system define + * @version 1.0 + * @author AIIT XUOS Lab + * @date 2021.03.18 + */ + +#ifndef __INC_CH376FS_H__ +#define __INC_CH376FS_H__ + +#include + +#if defined(FS_VFS) +#include +#endif + +#define PARAM_LEN 256 + +/* CH376 file system directory info */ +struct Ch376FatDirInfo +{ + uint8 dir_name[11]; + uint8 dir_attr; + uint8 dir_ntres; + uint8 dir_crt_time_tenth; + uint16 dir_crt_time; + uint16 dir_crt_date; + uint16 dir_lst_acc_date; + uint16 dir_fst_clus_hi; + uint16 dir_wrt_time; + uint16 dir_wrt_date; + uint16 dir_fst_clus_lo; + uint32 dir_file_size; +}; + +#endif diff --git a/Ubiquitous/XiZi/fs/iot-devicefile/Kconfig b/Ubiquitous/XiZi/fs/iot-devicefile/Kconfig new file mode 100644 index 0000000..13341d0 --- /dev/null +++ b/Ubiquitous/XiZi/fs/iot-devicefile/Kconfig @@ -0,0 +1,6 @@ + config VFS_USING_WORKDIR + bool "Using work dir for FS_VFS" + default y + config FS_VFS_DEVFS + bool "Using dev object for FS_VFS" + default y \ No newline at end of file diff --git a/Ubiquitous/XiZi/fs/iot-devicefile/Makefile b/Ubiquitous/XiZi/fs/iot-devicefile/Makefile new file mode 100644 index 0000000..cc13824 --- /dev/null +++ b/Ubiquitous/XiZi/fs/iot-devicefile/Makefile @@ -0,0 +1,5 @@ +SRC_FILES := iot-devicefile.c + + +include $(KERNEL_ROOT)/compiler.mk + diff --git a/Ubiquitous/XiZi/fs/iot-devicefile/iot-devicefile.c b/Ubiquitous/XiZi/fs/iot-devicefile/iot-devicefile.c new file mode 100644 index 0000000..eda0b7e --- /dev/null +++ b/Ubiquitous/XiZi/fs/iot-devicefile/iot-devicefile.c @@ -0,0 +1,148 @@ +#include +#include +#include +#include + +static void GetBusName(const char *path, char *bus_name) +{ + uint8 i = 0; + for (; i < strlen(path); i++) { + if (path[i] == '_') { + bus_name[i] = '\0'; + break; + } + + bus_name[i] = path[i]; + } +} + +static void GetDrvName(char *bus_name, char *drv_name) +{ + snprintf(drv_name, strlen(bus_name) + 5, "%s_drv", bus_name); +} + +static int DevicefileOpen(struct FileDescriptor *fdp, const char *path) +{ + int ret; + BusType bus_id; + char bus_name[NAME_NUM_MAX], drv_name[NAME_NUM_MAX]; + + GetBusName(path, bus_name); + GetDrvName(bus_name, drv_name); + + bus_id = BusFind(bus_name); + if (bus_id == NULL) + return -ENODEV; + bus_id->owner_driver = BusFindDriver(bus_id, drv_name); + bus_id->owner_haldev = BusFindDevice(bus_id, path); + + bus_id->match(bus_id->owner_driver, bus_id->owner_haldev); + + fdp->data = bus_id; + + ret = BusDevOpen(bus_id->owner_haldev); + + if (ret < 0) { + fdp->data = NULL; + return -EIO; + } + + return 0; +} + +static int DevicefileClose(struct FileDescriptor *fdp) +{ + int ret; + BusType bus_id; + + NULL_PARAM_CHECK(fdp); + NULL_PARAM_CHECK(fdp->data); + bus_id = (BusType)fdp->data; + + ret = BusDevClose(bus_id->owner_haldev); + + if (ret == 0) { + fdp->data = NULL; + return 0; + } + + return -EIO; +} + +static ssize_t DevicefileRead(struct FileDescriptor *fdp, void *dst, size_t len) +{ + int ret; + BusType bus_id; + + NULL_PARAM_CHECK(fdp); + NULL_PARAM_CHECK(fdp->data); + bus_id = (BusType)fdp->data; + struct BusBlockReadParam param; + memset(¶m, 0, sizeof(struct BusBlockReadParam)); + param.size = len; + param.buffer = dst; + param.pos = fdp->pos; + + ret = BusDevReadData(bus_id->owner_haldev, ¶m); + fdp->pos += param.read_length; + + return param.read_length; +} + +static ssize_t DevicefileWrite(struct FileDescriptor *fdp, const void *src, size_t len) +{ + int ret; + BusType bus_id; + + NULL_PARAM_CHECK(fdp); + NULL_PARAM_CHECK(fdp->data); + bus_id = (BusType)fdp->data; + struct BusBlockWriteParam param; + memset(¶m, 0, sizeof(struct BusBlockWriteParam)); + param.size = len; + param.buffer = src; + param.pos = fdp->pos; + + ret = BusDevWriteData(bus_id->owner_haldev, ¶m); + fdp->pos += ret; + + return ret; +} + +static int DevicefileIoctl(struct FileDescriptor *fdp, int cmd, void *args) +{ + int ret; + BusType bus_id; + + NULL_PARAM_CHECK(fdp); + NULL_PARAM_CHECK(fdp->data); + bus_id = (BusType)fdp->data; + struct BusConfigureInfo param; + param.configure_cmd = cmd; + param.private_data = args; + + ret = BusDrvConfigure(bus_id->owner_driver, ¶m); + + return ret; +} + +static int DevicefileMount(struct MountPoint *mp) +{ + return 0; +} + +static struct Filesystem devicefile_fs = { + .open = DevicefileOpen, + .close = DevicefileClose, + .read = DevicefileRead, + .write = DevicefileWrite, + .ioctl = DevicefileIoctl, + .mount = DevicefileMount, +}; + +int DevicefileInit() +{ + RegisterFilesystem(FSTYPE_IOTDEVICEFILE, &devicefile_fs); + + return 0; +} diff --git a/Ubiquitous/XiZi/kernel/Kconfig b/Ubiquitous/XiZi/kernel/Kconfig new file mode 100644 index 0000000..48ac755 --- /dev/null +++ b/Ubiquitous/XiZi/kernel/Kconfig @@ -0,0 +1,322 @@ +menu "Kernel feature" + + menu "separate compile(choose none for compile once)" + config SEPARATE_COMPILE + bool + default n + + config COMPILER_APP + bool "only compile application" + default n + select USER_APPLICATION + select SEPARATE_COMPILE + choice + prompt "select the startup site of APP " + default APP_STARTUP_FROM_FLASH + + config APP_STARTUP_FROM_SDCARD + bool "app start from sd card" + + config APP_STARTUP_FROM_FLASH + bool "app start from flash" + endchoice + + + config COMPILER_KERNEL + bool "only compile kernel" + default n + select SEPARATE_COMPILE + endmenu + + menu "Memory Management" + config KERNEL_MEMBLOCK + bool "Using gather block" + default n + config MEM_ALIGN_SIZE + int "Alignment size for CPU architecture data access" + default 8 + help + Alignment size for CPU architecture data access + + config MEM_EXTERN_SRAM + bool "Using extern memory" + default n + + config MM_PAGE_SIZE + int "Config memory page size" + default 4096 + help + config memory page size + menu "Using small memory allocator" + config KERNEL_SMALL_MEM_ALLOC + bool "Using small memory allocator" + default y + if KERNEL_SMALL_MEM_ALLOC + config SMALL_NUMBER_32B + int "Config 32B small memory number" + range 1 256 + default 64 + config SMALL_NUMBER_64B + int "Config 64B small memory number" + range 1 128 + default 32 + endif + endmenu + endmenu + + menu "Task feature" + config USER_APPLICATION + bool "start system application" + default y + + config TASK_ISOLATION + bool "Enable task isolation" + default n + select SEPARATE_COMPILE + select COMPILER_APP + select COMPILER_KERNEL + help + Enable task isolation + + menu "Inter-Task communication" + config KERNEL_SEMAPHORE + bool "Enable semaphore" + default y + + config KERNEL_MUTEX + bool "Enable mutex" + default y + + config KERNEL_EVENT + bool "Enable event" + default y + + config KERNEL_MESSAGEQUEUE + bool "Enable message queue" + default y + + config KERNEL_SOFTTIMER + bool "Enable softtimer " + select KERNEL_WORKQUEUE + default y + endmenu + + choice + prompt "Scheduler Policy Set" + default SCHED_POLICY_RR_REMAINSLICE + + config SCHED_POLICY_RR_REMAINSLICE + bool "config scheduler policy as RR REMAINSLICE" + + config SCHED_POLICY_RR + bool "config scheduler policy as RR " + + config SCHED_POLICY_FIFO + bool "config scheduler policy as FIFO" + endchoice + + choice + prompt "The maximal level value of priority of task" + default KTASK_PRIORITY_32 + + config KTASK_PRIORITY_8 + bool "8" + + config KTASK_PRIORITY_32 + bool "32" + + config KTASK_PRIORITY_256 + bool "256" + endchoice + + config KTASK_PRIORITY_MAX + int + default 8 if KTASK_PRIORITY_8 + default 32 if KTASK_PRIORITY_32 + default 256 if KTASK_PRIORITY_256 + + config TICK_PER_SECOND + int "Tick frequency, Hz" + range 10 1000 + default 100 + help + System's tick frequency, Hz. + + config KERNEL_STACK_OVERFLOW_CHECK + bool "Using stack overflow checking" + default y + help + Enable task stack overflow checking. The stack overflow is checking when + each task switch. + + config IDLE_KTASK_STACKSIZE + int "The stack size of idle task" + default 1024 + + config ZOMBIE_KTASK_STACKSIZE + int "The stack size of zombie_recycle task" + default 2048 + + endmenu + + menu "Kernel Console" + config KERNEL_CONSOLE + bool "config enable console" + default y + + if KERNEL_CONSOLE + config KERNEL_BANNER + bool "config system banner print" + default y + + config KERNEL_CONSOLEBUF_SIZE + int "default buffer size for console log printf" + default 128 + endif + endmenu + + menu "Kernel Hook" + menuconfig KERNEL_HOOK + bool "Enable system hook" + default n + help + Enable the hook function when system running, such as idle task hook, + task context switch etc. + + if KERNEL_HOOK + menuconfig KERNEL_IDLE_HOOK + bool "Enable IDLE Task hook" + default y + + if KERNEL_IDLE_HOOK + config IDEL_HOOK_LIST_SIZE + int "The max size of idle hook list" + default 4 + range 1 16 + help + The system has a hook list. This is the hook list size. + endif + endif + endmenu + + source "$KERNEL_DIR/tool/shell/Kconfig" + + menu "Kernel data structure Manage" + menuconfig KERNEL_QUEUEMANAGE + bool "Config Kernel Queue Manage" + default y + + if KERNEL_QUEUEMANAGE + config KERNEL_WORKQUEUE + bool "Config kernel work queue" + default y + + if KERNEL_WORKQUEUE + config WORKQUEUE_KTASK_STACKSIZE + int "The stack size for workqueue task" + default 2048 + + config WORKQUEUE_KTASK_PRIORITY + int + default 6 if KTASK_PRIORITY_8 + default 23 if KTASK_PRIORITY_32 + default 128 if KTASK_PRIORITY_256 + config QUEUE_MAX + int "Config the max queue length" + default 16 + endif + + config KERNEL_WAITQUEUE + bool "Config kernel wait queue" + default y + + config KERNEL_DATAQUEUE + bool "Config kernel data queue" + default y + endif + + config KERNEL_CIRCULAR_AREA + bool "Config Kernel Circular Area" + default n + + config KERNEL_AVL_TREE + bool "Config Kernel AVL Tree" + default n + endmenu + + menu "Kernel components init" + menuconfig KERNEL_COMPONENTS_INIT + bool "Use components automatically initialization" + default y + + if KERNEL_COMPONENTS_INIT + config ENV_INIT_KTASK_STACK_SIZE + int "Set env init task stack size" + default 8192 + + menuconfig KERNEL_USER_MAIN + bool "The main() function as user entry function" + default y + endif + endmenu + + config NAME_NUM_MAX + int "The maximal size of kernel object name" + range 2 32 + default 32 + help + Each kernel object, such as task has a name, + the NAME_NUM_MAX is the maximal size of this name. + + menuconfig KERNEL_DEBUG + bool "Enable debugging features" + default n + + if KERNEL_DEBUG + config DEBUG_INIT_CONFIG + bool "Enable debugging of components initialization" + default y + + config KDYN_LOG_DBG + bool "Enable DYNAMIC [DBG] LOG" + default y + + config DBG_INIT + int + default 1 if DEBUG_INIT_CONFIG + endif + + menuconfig ARCH_SMP + bool "Enable SMP(Symmetric multiprocessing)" + default n + help + This option should be selected by machines which have an SMP- + capable CPU. + The only effect of this option is to make the SMP-related + options available to the user for configuration. + + config CPU_NUMBERS + int "Number of CPUs" + default 2 + depends on ARCH_SMP + help + Number of CPUs in the system + menu "hash table config" + menuconfig ID_HTABLE_SIZE + int "ID hash table size" + range 1 256 + default 16 + help + Size of the hash table that ID manager uses internally + menuconfig ID_NUM_MAX + int "ID num max" + range 16 256 + default 128 + help + max num of the ID manager + endmenu + + +source "$KERNEL_DIR/kernel/kernel_test/Kconfig" + +endmenu diff --git a/Ubiquitous/XiZi/kernel/Makefile b/Ubiquitous/XiZi/kernel/Makefile new file mode 100644 index 0000000..8f0e3c7 --- /dev/null +++ b/Ubiquitous/XiZi/kernel/Makefile @@ -0,0 +1,9 @@ +SRC_DIR := thread memory + +ifeq ($(CONFIG_KERNEL_TEST), y) + SRC_DIR += kernel_test +endif + +SRC_DIR +=kernel_service + +include $(KERNEL_ROOT)/compiler.mk diff --git a/Ubiquitous/XiZi/kernel/include/user_api.h b/Ubiquitous/XiZi/kernel/include/user_api.h new file mode 100644 index 0000000..b804f06 --- /dev/null +++ b/Ubiquitous/XiZi/kernel/include/user_api.h @@ -0,0 +1,247 @@ +/* + * Copyright (c) 2020 AIIT XUOS Lab + * XiUOS is licensed under Mulan PSL v2. + * You can use this software according to the terms and conditions of the Mulan PSL v2. + * You may obtain a copy of Mulan PSL v2 at: + * http://license.coscl.org.cn/MulanPSL2 + * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, + * EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, + * MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. + * See the Mulan PSL v2 for more details. + */ + +/** +* @file: user_api.h +* @brief: the priviate user api for application +* @version: 1.0 +* @author: AIIT XUOS Lab +* @date: 2020/4/20 +* +*/ + +#ifndef XS_USER_API_H +#define XS_USER_API_H + + +// #include + +#include +#include "../../../kernel/include/xs_service.h" +#include "../../../kernel/include/xs_base.h" +#include +#include +#include "../../../arch/kswitch.h" +#include + + +#ifdef SEPARATE_COMPILE + +#define TASK_INFO 1 +#define MEM_INFO 2 +#define SEM_INFO 3 +#define EVENT_INFO 4 +#define MUTEX_INFO 5 +#define MEMPOOL_INFO 6 +#define MSGQUEUE_INFO 7 +#define DEVICE_INFO 8 +#define TIMER_INFO 9 + +int UserPrintInfo(unsigned long i); + +struct utask +{ + char name[NAME_NUM_MAX]; + void *func_entry; + void *func_param; + int32_t stack_size; + uint8_t prio; +}; +typedef struct utask UtaskType; + +typedef void DIR; + +int32_t UserTaskCreate(UtaskType utask); + +x_err_t UserTaskStartup(int32_t id); +x_err_t UserTaskDelete(int32_t id); +void UserTaskQuit(void); +x_err_t UserTaskDelay(int32_t ms); +x_err_t UserGetTaskName(int32_t id ,char *name); +int32_t UserGetTaskID(void); +uint8_t UserGetTaskStat(int32_t id); + +#ifdef ARCH_SMP +x_err_t UserTaskCoreCombine(int32_t id,uint8_t core_id); +x_err_t UserTaskCoreUnCombine(int32_t id); +uint8_t UserGetTaskCombinedCore(int32_t id); +uint8_t UserGetTaskRunningCore(int32_t id); +#endif + +x_err_t UserGetTaskErrorstatus(int32_t id); +uint8_t UserGetTaskPriority(int32_t id); + + +void *UserMalloc(size_t size); +void *UserRealloc(void *pointer, size_t size); +void *UserCalloc(size_t count, size_t size); +void UserFree(void *pointer); + +#ifdef KERNEL_MUTEX +int32_t UserMutexCreate(); +void UserMutexDelete(int32_t mutex); +int32_t UserMutexObtain(int32_t mutex, int32_t wait_time); +int32_t UserMutexAbandon(int32_t mutex); +#endif + + +#ifdef KERNEL_SEMAPHORE +typedef int32 sem_t; +sem_t UserSemaphoreCreate(uint16_t val); +x_err_t UserSemaphoreDelete(sem_t sem); +x_err_t UserSemaphoreObtain(sem_t sem, int32_t wait_time); +x_err_t UserSemaphoreAbandon(sem_t sem); +x_err_t UserSemaphoreSetValue(sem_t sem, uint16_t val); +#endif + + +#ifdef KERNEL_EVENT +typedef int32 EventIdType; +EventIdType UserEventCreate(uint8_t flag); +void UserEventDelete(EventIdType event); +x_err_t UserEventTrigger(EventIdType event, uint32_t set); +x_err_t UserEventProcess(EventIdType event, uint32_t set, uint8_t option, + int32_t wait_time, uint32_t *Recved); +x_err_t UserEventReinit(EventIdType event); +#endif + + +#ifdef KERNEL_MESSAGEQUEUE +int32_t UserMsgQueueCreate(size_t msg_size, size_t max_msgs); +x_err_t UserMsgQueueDelete(int32_t mq ); +x_err_t UserMsgQueueSendwait(int32_t mq, const void *buffer, + size_t size, int32_t wait_time); +x_err_t UserMsgQueueSend(int32_t mq, const void *buffer, size_t size); +x_err_t UserMsgQueueUrgentSend(int32_t mq, const void *buffer, size_t size); +x_err_t UserMsgQueueRecv(int32_t mq, void *buffer, size_t size,int32_t wait_time); +x_err_t UserMsgQueueReinit(int32_t mq); +#endif + +int open(const char *path, int flags, ...); +int read(int fd, void *buf, size_t len); +int write(int fd, const void *buf, size_t len); +int close(int fd); +int ioctl(int fd, int cmd, void *args); +off_t lseek(int fd, off_t offset, int whence); +int rename(const char *from, const char *to); +int unlink(const char *path); +int stat(const char *path, struct stat *buf); +int fstat(int fd, struct stat *buf); +int fsync(int fd); +int ftruncate(int fd, off_t length); + +int mkdir(const char *path, mode_t mode); +DIR *opendir(const char *path); +int closedir(DIR *dirp); +struct dirent *readdir(DIR *dirp); +int rmdir(const char *path); +int chdir(const char *path); +char *getcwd(char *buf, size_t size); +long telldir(DIR *dirp); +void seekdir(DIR *dirp, off_t offset); +void rewinddir(DIR *dirp); + +#ifdef FS_VFS +struct statfs { + size_t f_bsize; + size_t f_blocks; + size_t f_bfree; +}; + +int statfs(const char *path, struct statfs *buf); +#endif + +int Userprintf(const char *fmt, ...); + +#define printf Userprintf + +#else + +#ifdef FS_VFS +#include +#endif + +struct utask +{ + char name[NAME_NUM_MAX]; + void *func_entry; + void *func_param; + int32_t stack_size; + uint8_t prio; +}; +typedef struct utask UtaskType; +int32_t UserTaskCreate(UtaskType utask); + +#define UserTaskStartup StartupKTask +#define UserTaskDelete KTaskDelete +#define UserTaskQuit KTaskQuit +#define UserTaskDelay MdelayKTask + +x_err_t UserGetTaskName(int32_t id ,char *name); +int32_t UserGetTaskID(void); +uint8_t UserGetTaskStat(int32_t id); + +#ifdef ARCH_SMP +#define UserTaskCoreCombine KTaskCoreCombine +#define UserTaskCoreUnCombine KTaskCoreUnCombine + +uint8_t UserGetTaskCombinedCore(int32_t id); +uint8_t UserGetTaskRunningCore(int32_t id); +#endif + +x_err_t UserGetTaskErrorstatus(int32_t id); +uint8_t UserGetTaskPriority(int32_t id); + +#define UserMalloc x_malloc +#define UserRealloc x_realloc +#define UserCalloc x_calloc +#define UserFree x_free + +#ifdef KERNEL_MUTEX +#define UserMutexCreate KMutexCreate +#define UserMutexDelete KMutexDelete +#define UserMutexObtain KMutexObtain +#define UserMutexAbandon KMutexAbandon +#endif + + +#ifdef KERNEL_SEMAPHORE +#define UserSemaphoreCreate KSemaphoreCreate +#define UserSemaphoreDelete KSemaphoreDelete +#define UserSemaphoreObtain KSemaphoreObtain +#define UserSemaphoreAbandon KSemaphoreAbandon +#define UserSemaphoreSetValue KSemaphoreSetValue +#endif + +#ifdef KERNEL_EVENT +#define UserEventCreate KEventCreate +#define UserEventDelete KEventDelete +#define UserEventTrigger KEventTrigger +#define UserEventProcess KEventProcess +#endif + +#ifdef KERNEL_MESSAGEQUEUE +#define UserMsgQueueCreate KCreateMsgQueue +#define UserMsgQueueDelete KDeleteMsgQueue +#define UserMsgQueueSendwait KMsgQueueSendwait +#define UserMsgQueueSend KMsgQueueSend +#define UserMsgQueueUrgentSend KMsgQueueUrgentSend +#define UserMsgQueueRecv KMsgQueueRecv +#define UserMsgQueueReinit KMsgQueueReinit +#endif + +#define UserPrintf KPrintf + + +#endif + +#endif \ No newline at end of file diff --git a/Ubiquitous/XiZi/kernel/include/xizi.h b/Ubiquitous/XiZi/kernel/include/xizi.h new file mode 100644 index 0000000..ab021ce --- /dev/null +++ b/Ubiquitous/XiZi/kernel/include/xizi.h @@ -0,0 +1,50 @@ +/* +* Copyright (c) 2020 AIIT XUOS Lab +* XiUOS is licensed under Mulan PSL v2. +* You can use this software according to the terms and conditions of the Mulan PSL v2. +* You may obtain a copy of Mulan PSL v2 at: +* http://license.coscl.org.cn/MulanPSL2 +* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, +* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, +* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. +* See the Mulan PSL v2 for more details. +*/ + +/** +* @file: xizi.h +* @brief: all header files of kernel +* @version: 1.0 +* @author: AIIT XUOS Lab +* @date: 2020/3/10 +* +*/ + +#ifndef XIZI_H +#define XIZI_H + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#endif diff --git a/Ubiquitous/XiZi/kernel/include/xs_assign.h b/Ubiquitous/XiZi/kernel/include/xs_assign.h new file mode 100644 index 0000000..18633dc --- /dev/null +++ b/Ubiquitous/XiZi/kernel/include/xs_assign.h @@ -0,0 +1,138 @@ +/* +* Copyright (c) 2020 AIIT XUOS Lab +* XiUOS is licensed under Mulan PSL v2. +* You can use this software according to the terms and conditions of the Mulan PSL v2. +* You may obtain a copy of Mulan PSL v2 at: +* http://license.coscl.org.cn/MulanPSL2 +* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, +* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, +* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. +* See the Mulan PSL v2 for more details. +*/ + +/** +* @file: xs_assign.h +* @brief: function declaration and structure defintion of system assign +* @version: 1.0 +* @author: AIIT XUOS Lab +* @date: 2020/3/10 +* +*/ + +#ifndef XS_ASSIGN_H +#define XS_ASSIGN_H + +#include +#include +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +#define MERGE_FLAG(src, flag) (*(src) |= flag) +#define CLEAR_FLAG(src, flag) (*(src) &= ~flag) + +extern struct Assign Assign; + +struct PriorityReadyVectorDone +{ + void (*init)(struct OsAssignReadyVector *ready_vector); + void (*insert)(struct TaskDescriptor *task); + void (*remove)(struct TaskDescriptor *task); +}; + +#ifdef ARCH_SMP +struct smp_assign_done +{ + x_ubase (*GetHighest)(void); + struct TaskDescriptor* (*select)(void); + void (*SwitchToNew)(struct TaskDescriptor* old_task, struct TaskDescriptor* new_task); + void (*SwitchToFirst)(struct TaskDescriptor* task); + void (*SetSystemTask)(struct TaskDescriptor* task); + void (*SmpInit)(void); +}; +struct Assign +{ + struct OsAssignReadyVector os_assign_read_vector; + struct OsAssignReadyVector smp_os_assign_ready_rector[CPU_NUMBERS]; + struct TaskDescriptor *smp_os_running_task[CPU_NUMBERS]; + + struct PriorityReadyVectorDone *ready_vector_done; + struct smp_assign_done *smp_assign_done; + + uint8 current_priority[CPU_NUMBERS]; + uint16 assign_lock[CPU_NUMBERS]; +}; + +void SwitchKtaskContext(x_ubase from, x_ubase to, struct TaskDescriptor *to_task); +void SwitchKtaskContextTo(x_ubase to, struct TaskDescriptor *to_task); +void HwInterruptcontextSwitch( x_ubase from, x_ubase to,struct TaskDescriptor *to_task , void *context); + +#else +struct Assign +{ + struct OsAssignReadyVector os_assign_read_vector; + struct TaskDescriptor *os_running_task; + + struct PriorityReadyVectorDone *ready_vector_done; + + uint8 current_priority; +}; + +void SwitchKtaskContext(x_ubase from, x_ubase to , struct TaskDescriptor *to_task); +void SwitchKtaskContextTo(x_ubase to, struct TaskDescriptor *to_task); +void HwInterruptcontextSwitch( x_ubase from, x_ubase to, struct TaskDescriptor *to_task ,void *context); +#endif + +void KTaskInsertToReadyVector(struct TaskDescriptor *task); +int PrioCaculate(uint32 bitmap); +void SysInitOsAssign(void); +void ResetCriticalAreaLock(void ); +void StartupOsAssign(void); +x_base CriticalAreaLock(void); +void CriticalAreaUnLock(x_base lock); +uint16 GetOsAssignLockLevel(void); +int32 JudgeAssignReadyBitmapIsEmpty(struct OsAssignReadyVector *ready_vector); +void OsAssignReadyVectorInit(struct OsAssignReadyVector *ready_vector); +void AssignPolicyInsert(struct TaskDescriptor *task, struct OsAssignReadyVector* ready_table); +struct TaskDescriptor * ChooseTaskWithHighestPrio(struct OsAssignReadyVector *ready_vector); + +#ifdef KERNEL_STACK_OVERFLOW_CHECK +void _KTaskOsAssignStackCheck(struct TaskDescriptor *task); +#endif + +#ifdef ARCH_SMP +extern HwSpinlock AssignSpinLock; +#define DO_KTASK_ASSIGN \ + do \ + { \ + NOT_IN_CRITICAL_AREA; \ + x_base lock; \ + lock = DISABLE_INTERRUPT(); \ + HwLockSpinlock(&AssignSpinLock); \ + KTaskOsAssign(); \ + HwUnlockSpinlock(&AssignSpinLock); \ + ENABLE_INTERRUPT(lock); \ + } while (0); + +#else + +#define DO_KTASK_ASSIGN \ + do \ + { \ + NOT_IN_CRITICAL_AREA; \ + x_base lock; \ + lock = DISABLE_INTERRUPT(); \ + KTaskOsAssign(); \ + ENABLE_INTERRUPT(lock); \ + } while (0); + +#endif + +#ifdef __cplusplus +} +#endif + +#endif \ No newline at end of file diff --git a/Ubiquitous/XiZi/kernel/include/xs_avltree.h b/Ubiquitous/XiZi/kernel/include/xs_avltree.h new file mode 100644 index 0000000..d6b0ad2 --- /dev/null +++ b/Ubiquitous/XiZi/kernel/include/xs_avltree.h @@ -0,0 +1,66 @@ +/* +* Copyright (c) 2020 AIIT XUOS Lab +* XiUOS is licensed under Mulan PSL v2. +* You can use this software according to the terms and conditions of the Mulan PSL v2. +* You may obtain a copy of Mulan PSL v2 at: +* http://license.coscl.org.cn/MulanPSL2 +* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, +* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, +* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. +* See the Mulan PSL v2 for more details. +*/ + +/** +* @file: xs_avltree.h +* @brief: function declaration and structure defintion of avl tree +* @version: 1.0 +* @author: AIIT XUOS Lab +* @date: 2020/4/20 +* +*/ + +#ifndef AVL_TREE_H +#define AVL_TREE_H + +#include + +#ifdef __cplusplus +extern "C" { +#endif +#ifdef KERNEL_AVL_TREE +struct AvlNode +{ + int32 data; + uint32 height; + + struct AvlNode *left; + struct AvlNode *right; +}; + +typedef struct AvlNode *AvlNodeType; + +#ifndef AVL_MAX +#define AVL_MAX(a, b) ((a) > (b) ? (a) : (b)) +#endif + +#ifndef AVL_ABS +#define AVL_ABS(a) ((a > 0) ? (a) : (-a)) +#endif + +/*This function will insert data to the avl tree*/ +AvlNodeType AvlTreeInsertNode(AvlNodeType avl_node, int32 data); + +/*This function will delete data from the avl tree*/ +AvlNodeType AvlTreeDeleteNode(AvlNodeType avl_node, int32 data); + +/*This function will modify certain data of the avl tree*/ +AvlNodeType AvlNodeModifyNode(AvlNodeType avl_node, int32 src_data, int32 dst_data); + +/*This function will return the avl node which has the data*/ +AvlNodeType AvlNodeSearchNode(AvlNodeType avl_node, int32 data); +#endif +#ifdef __cplusplus +} +#endif + +#endif diff --git a/Ubiquitous/XiZi/kernel/include/xs_banner.h b/Ubiquitous/XiZi/kernel/include/xs_banner.h new file mode 100644 index 0000000..6b3108a --- /dev/null +++ b/Ubiquitous/XiZi/kernel/include/xs_banner.h @@ -0,0 +1,29 @@ +/* +* Copyright (c) 2020 AIIT XUOS Lab +* XiUOS is licensed under Mulan PSL v2. +* You can use this software according to the terms and conditions of the Mulan PSL v2. +* You may obtain a copy of Mulan PSL v2 at: +* http://license.coscl.org.cn/MulanPSL2 +* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, +* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, +* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. +* See the Mulan PSL v2 for more details. +*/ + +/** +* @file: xs_banner.h +* @brief: function declaration of system banner +* @version: 1.0 +* @author: AIIT XUOS Lab +* @date: 2020/4/20 +* +*/ + +#ifndef XS_BANNER_H +#define XS_BANNER_H + +#include + +void ShowBanner(void); + +#endif diff --git a/Ubiquitous/XiZi/kernel/include/xs_base.h b/Ubiquitous/XiZi/kernel/include/xs_base.h new file mode 100644 index 0000000..89699a0 --- /dev/null +++ b/Ubiquitous/XiZi/kernel/include/xs_base.h @@ -0,0 +1,133 @@ +/* +* Copyright (c) 2020 AIIT XUOS Lab +* XiUOS is licensed under Mulan PSL v2. +* You can use this software according to the terms and conditions of the Mulan PSL v2. +* You may obtain a copy of Mulan PSL v2 at: +* http://license.coscl.org.cn/MulanPSL2 +* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, +* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, +* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. +* See the Mulan PSL v2 for more details. +*/ + +/** +* @file: xs_base.h +* @brief: basic data type defintions +* @version: 1.0 +* @author: AIIT XUOS Lab +* @date: 2020/3/10 +* +*/ + +#ifndef XS_BASE_H +#define XS_BASE_H + +/* import board special configuration */ +#include + +#ifdef __cplusplus +extern "C" { +#endif + +#if 0 + +/* the basic types of date*/ +#ifdef ARCH_CPU_64BIT +typedef unsigned long int size_t; +typedef signed long int ssize_t; +#else + typedef unsigned int size_t; +typedef signed int ssize_t; +#endif + +#endif + + +#ifndef CONFIG_ARCH_DATA_TYPE +typedef signed char int8; +typedef signed short int16; +typedef signed int int32; +typedef unsigned char uint8; +typedef unsigned short uint16; +typedef unsigned int uint32; + +#ifdef ARCH_CPU_64BIT +typedef signed long int64; +typedef unsigned long uint64; +#else +typedef signed long long int64; +typedef unsigned long long uint64; +#endif +#endif + +typedef int x_bool; +typedef long x_base; +typedef unsigned long x_ubase; + +typedef x_base x_err_t; +typedef uint32 x_time_t; +typedef uint32 x_ticks_t; +typedef x_base x_flag_t; +typedef x_ubase x_size_t; +typedef x_ubase x_dev_t; +typedef x_base x_OffPos; + +#define RET_TRUE 1 +#define RET_FALSE 0 + +#define UINT8_SIZE_MAX 0xff +#define UINT16_SIZE_MAX 0xffff +#define UINT32_SIZE_MAX 0xffffffff +#define TICK_SIZE_MAX UINT32_SIZE_MAX + + +/* the type of components*/ +#define Cmpt_KindN_Null 0 +#define Cmpt_KindN_Task 1 +#define Cmpt_KindN_Semaphore 2 +#define Cmpt_KindN_Mutex 3 +#define Cmpt_KindN_Event 4 +#define Cmpt_KindN_MessageQueue 5 +#define Cmpt_KindN_MemPool 6 +#define Cmpt_KindN_Timer 7 +#define Cmpt_KindN_Bus 8 +#define Cmpt_KindN_Static 0x80 + + +/* the type of error */ +#define EOK 0 +#define ERROR 1 +#define ETIMEOUT 2 +#define EFULL 3 +#define EEMPTY 4 +#define ENOMEMORY 5 +#define ENONESYS 6 +#define EDEV_BUSY 7 +#define EPIO 8 +#define EINTER 9 +#define EINVALED 10 +#define INVALID_TASK_ERROR 11 + + + +#define ALIGN_MEN_UP(size, align) ((((size) + (align) - 1) /(align))*(align)) +#define ALIGN_MEN_DOWN(size, align) ((size)/(align)*(align)) +#define NONE (0) + +#ifndef SECTION + #if defined(__GNUC__) + #define SECTION(x) __attribute__((section(x))) + #else + #define SECTION(x) + #endif +#endif + +#define WAITING_FOREVER -1 + +void KPrintf(const char *fmt, ...); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/Ubiquitous/XiZi/kernel/include/xs_circular_area.h b/Ubiquitous/XiZi/kernel/include/xs_circular_area.h new file mode 100644 index 0000000..56cd297 --- /dev/null +++ b/Ubiquitous/XiZi/kernel/include/xs_circular_area.h @@ -0,0 +1,88 @@ +/* +* Copyright (c) 2020 AIIT XUOS Lab +* XiUOS is licensed under Mulan PSL v2. +* You can use this software according to the terms and conditions of the Mulan PSL v2. +* You may obtain a copy of Mulan PSL v2 at: +* http://license.coscl.org.cn/MulanPSL2 +* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, +* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, +* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. +* See the Mulan PSL v2 for more details. +*/ + +/** +* @file: xs_circular_area.h +* @brief: function declaration and structure defintion of circular area +* @version: 1.0 +* @author: AIIT XUOS Lab +* @date: 2020/4/20 +* +*/ + +#ifndef CIRCULAR_AREA_H +#define CIRCULAR_AREA_H + +#include + +#ifdef __cplusplus +extern "C" { +#endif +#ifdef KERNEL_CIRCULAR_AREA +typedef struct CircularArea *CircularAreaType; + +struct CircularAreaOps +{ + uint32 (*read) (CircularAreaType circular_area, uint8 *output_buffer, uint32 data_length); + uint32 (*write) (CircularAreaType circular_area, uint8 *input_buffer, uint32 data_length, x_bool b_force); + void (*release) (CircularAreaType circular_area); + void (*reset) (CircularAreaType circular_area); +}; + +struct CircularArea +{ + uint8 *data_buffer; + + uint8 readidx; + uint8 writeidx; + + uint8 *p_head; + uint8 *p_tail; + + uint32 area_length; + x_bool b_status; + + struct CircularAreaOps *CircularAreaOperations; +}; + +/*This function will return whether the circular_area is full or not*/ +x_bool CircularAreaIsFull(CircularAreaType circular_area); + +/*This function will return whether the circular_area is empty or not*/ +x_bool CircularAreaIsEmpty(CircularAreaType circular_area); + +/*This function will reset the circular_area and set the descriptor to default*/ +void CircularAreaReset(CircularAreaType circular_area); + +/*This function will release the circular_area descriptor and free the memory*/ +void CircularAreaRelease(CircularAreaType circular_area); + +/*This function will read data from the circular_area*/ +uint32 CircularAreaRead(CircularAreaType circular_area, uint8 *output_buffer, uint32 data_length); + +/*This function will write data to the circular_area*/ +uint32 CircularAreaWrite(CircularAreaType circular_area, uint8 *input_buffer, uint32 data_length, x_bool b_force); + +/*This function will get the circual_area max length*/ +uint32 CircularAreaGetMaxLength(CircularAreaType circular_area); + +/*This function will get the data length of the circular_area*/ +uint32 CircularAreaGetDataLength(CircularAreaType circular_area); + +/*This function will initialize the circular_area*/ +CircularAreaType CircularAreaInit(uint32 circular_area_length); +#endif +#ifdef __cplusplus +} +#endif + +#endif diff --git a/Ubiquitous/XiZi/kernel/include/xs_dataqueue.h b/Ubiquitous/XiZi/kernel/include/xs_dataqueue.h new file mode 100644 index 0000000..9136eed --- /dev/null +++ b/Ubiquitous/XiZi/kernel/include/xs_dataqueue.h @@ -0,0 +1,69 @@ +/* +* Copyright (c) 2020 AIIT XUOS Lab +* XiUOS is licensed under Mulan PSL v2. +* You can use this software according to the terms and conditions of the Mulan PSL v2. +* You may obtain a copy of Mulan PSL v2 at: +* http://license.coscl.org.cn/MulanPSL2 +* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, +* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, +* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. +* See the Mulan PSL v2 for more details. +*/ + +/** +* @file: xs_dataqueue.h +* @brief: function declaration and structure defintion of circular area +* @version: 1.0 +* @author: AIIT XUOS Lab +* @date: 2020/4/20 +* +*/ + +#ifndef DATAQUEUE_H +#define DATAQUEUE_H + +#include +#include +#include +#include + +typedef struct +{ + const void *data; ///< data pointer + x_size_t length; ///< data length +}DataElemType; + +typedef struct +{ + uint16 front; + uint16 rear; + uint16 max_len; + DataElemType *base; + + int sem_blank; + int sem_data; +}DataQueueType; + +x_err_t InitDataqueue(DataQueueType *p_queue, uint16 NodeNumber); +x_err_t PushDataqueue(DataQueueType *queue,const void *StartAddr, x_size_t DataSize, int32 timeout); +x_err_t PopDataqueue(DataQueueType *queue, const void **StartAddr, x_size_t *size, int32 timeout); +x_err_t DataqueuePeak(DataQueueType *queue, const void **StartAddr, x_size_t *size); +void DeInitDataqueue(DataQueueType *p_queue); + +typedef struct +{ + x_err_t (*InitDataqueue)(DataQueueType *p_queue, uint16 NodeNumber); + x_err_t (*PushDataqueue)(DataQueueType *queue, + const void *StartAddr, + x_size_t DataSize, + int32 timeout); + x_err_t (*PopDataqueue)(DataQueueType *queue, + const void **StartAddr, + x_size_t *size, + int32 timeout); + x_err_t (*DataqueuePeak)(DataQueueType *queue, + const void **StartAddr, + x_size_t *size); + void (*DeInitDataqueue)(DataQueueType *p_queue); +} DataQueueDoneType; +#endif diff --git a/Ubiquitous/XiZi/kernel/include/xs_delay.h b/Ubiquitous/XiZi/kernel/include/xs_delay.h new file mode 100644 index 0000000..eaef346 --- /dev/null +++ b/Ubiquitous/XiZi/kernel/include/xs_delay.h @@ -0,0 +1,46 @@ +/* +* Copyright (c) 2020 AIIT XUOS Lab +* XiUOS is licensed under Mulan PSL v2. +* You can use this software according to the terms and conditions of the Mulan PSL v2. +* You may obtain a copy of Mulan PSL v2 at: +* http://license.coscl.org.cn/MulanPSL2 +* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, +* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, +* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. +* See the Mulan PSL v2 for more details. +*/ + +/** +* @file: xs_delay.h +* @brief: function declaration and structure defintion of delay +* @version: 1.0 +* @author: AIIT XUOS Lab +* @date: 2020/3/11 +* +*/ + +#ifndef XS_DELAY_H +#define XS_DELAY_H + +#include +#include +#include +#include + +#define TASK_DELAY_INACTIVE 0 +#define TASK_DELAY_ACTIVE 1 + +struct Delay +{ + struct TaskDescriptor *task; + x_ticks_t ticks; + uint8 status; + DoubleLinklistType link; +}; +typedef struct Delay *DelayType; + +x_err_t KTaskSetDelay(struct TaskDescriptor *task, x_ticks_t ticks); +x_err_t KTaskUnSetDelay(struct TaskDescriptor *task); +void CheckTaskDelay(void); + +#endif \ No newline at end of file diff --git a/Ubiquitous/XiZi/kernel/include/xs_event.h b/Ubiquitous/XiZi/kernel/include/xs_event.h new file mode 100644 index 0000000..a765bac --- /dev/null +++ b/Ubiquitous/XiZi/kernel/include/xs_event.h @@ -0,0 +1,66 @@ +/* + * Copyright (c) 2020 AIIT XUOS Lab + * XiUOS is licensed under Mulan PSL v2. + * You can use this software according to the terms and conditions of the Mulan PSL v2. + * You may obtain a copy of Mulan PSL v2 at: + * http://license.coscl.org.cn/MulanPSL2 + * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, + * EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, + * MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. + * See the Mulan PSL v2 for more details. + */ + +/** +* @file: xs_event.h +* @brief: function declaration and structure defintion of event +* @version: 1.0 +* @author: AIIT XUOS Lab +* @date: 2020/3/10 +* +*/ + +#ifndef XS_EVENT_H +#define XS_EVENT_H + +#include +#include +#include +#include +#include + +#ifdef KERNEL_EVENT + +#define EVENT_EVENTS_MASK 0x1FFFFFFF +#define EVENT_OPTIONS_MASK 0x7 + +#define EVENT_AND (1 << 0) +#define EVENT_OR (1 << 1) +#define EVENT_AUTOCLEAN (1 << 2) + +typedef int32 EventIdType; + +struct Event +{ + struct IdNode id; + uint32 options : 3; + uint32 events : 29; + + DoubleLinklistType pend_list; + DoubleLinklistType link; +}; + +typedef struct +{ + int32 (*EventCreate)(uint32 options); + void (*EventDelete)(struct Event *event); + int32 (*EventTrigger)(struct Event *event, uint32 events); + int32 (*EventProcess)(struct Event *event, uint32 events, uint32 options, int32 msec, uint32 *processed); +} EventDoneType; + +int32 KEventCreate(uint32 options); +void KEventDelete(int32 id); +int32 KEventTrigger(int32 id, uint32 events); +int32 KEventProcess(int32 id, uint32 events, uint32 options, int32 msec, uint32 *processed); + +#endif +#endif diff --git a/Ubiquitous/XiZi/kernel/include/xs_hook.h b/Ubiquitous/XiZi/kernel/include/xs_hook.h new file mode 100644 index 0000000..0180a66 --- /dev/null +++ b/Ubiquitous/XiZi/kernel/include/xs_hook.h @@ -0,0 +1,103 @@ +/* + * Copyright (c) 2020 AIIT XUOS Lab + * XiUOS is licensed under Mulan PSL v2. + * You can use this software according to the terms and conditions of the Mulan PSL v2. + * You may obtain a copy of Mulan PSL v2 at: + * http://license.coscl.org.cn/MulanPSL2 + * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, + * EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, + * MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. + * See the Mulan PSL v2 for more details. + */ + +/** +* @file: xs_hook.h +* @brief: function declaration and structure defintion of hook +* @version: 1.0 +* @author: AIIT XUOS Lab +* @date: 2020/4/20 +* +*/ + +#ifndef XS_HOOK_H +#define XS_HOOK_H + +#include +#include +#include +#include + +#ifdef KERNEL_HOOK +#define HOOK(function, argv) \ + do { if ((function) != NONE) function argv; } while (0) +#else +#define HOOK(function, argv) +#endif + +#define REGISTER_HOOK(hook, function) \ + { if ((function) != NONE) hook = function ; } + +#define UNREGISTER_HOOK(hook) \ + { hook = NONE ; } + +struct AssignHook +{ + void (*hook_Assign)(KTaskDescriptorType from, KTaskDescriptorType to); +}; + +struct TaskHook +{ + void (*hook_TaskCreate) (KTaskDescriptorType task); + void (*hook_TaskSuspend)(KTaskDescriptorType task); + void (*hook_TaskResume) (KTaskDescriptorType task); + +}; + +struct MemHook +{ + void (*hook_Malloc)(void *ptr, x_size_t size); + void (*hook_Free)(void *ptr); +#ifdef KERNEL_MEMBLOCK + void (*hook_GmAlloc)(struct MemGather *gm, void *date_ptr); + void (*hook_GmFree)(struct MemGather *gm, void *date_ptr); +#endif +}; + +struct TimerHook +{ + void (*hook_TimerEnter)(struct Timer *timer); + void (*hook_TimerExit)(struct Timer *timer); +}; + +struct IsrHook +{ + void (*hook_IsrEnter)(void); + void (*hook_IsrLeave)(void); +}; + +struct IdleHook +{ + void (*hook_Idle)(void); +}; + +struct TestHook +{ + void (*hook_test)(const char *buf); +}; + +struct KernelHook +{ + struct AssignHook assign; + struct TaskHook task; + struct MemHook mem; + struct TimerHook timer; + struct IsrHook isr; + struct IdleHook idle; + struct TestHook test; + +}; +extern struct KernelHook hook; + +int hook_init(void); + +#endif diff --git a/Ubiquitous/XiZi/kernel/include/xs_id.h b/Ubiquitous/XiZi/kernel/include/xs_id.h new file mode 100644 index 0000000..840287f --- /dev/null +++ b/Ubiquitous/XiZi/kernel/include/xs_id.h @@ -0,0 +1,66 @@ +/* +* Copyright (c) 2020 AIIT XUOS Lab +* XiUOS is licensed under Mulan PSL v2. +* You can use this software according to the terms and conditions of the Mulan PSL v2. +* You may obtain a copy of Mulan PSL v2 at: +* http://license.coscl.org.cn/MulanPSL2 +* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, +* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, +* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. +* See the Mulan PSL v2 for more details. +*/ + +/** +* @file: xs_id.h +* @brief: function declaration and structure defintion of id manager +* @version: 1.0 +* @author: AIIT XUOS Lab +* @date: 2020/4/20 +* +*/ + +#ifndef XS_ID_H +#define XS_ID_H + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +struct IdNode +{ + uint16 id; + DoubleLinklistType link; +}; + +struct IdManager +{ + uint16 id_max; + uint16 hoffset; + + uint8 *id_map; + DoubleLinklistType *htable; +}; + + + +#define DECLARE_ID_MANAGER(_name, _id_max) \ +uint8 __id_map_##_name[((_id_max) + 7) / 8]; \ +DoubleLinklistType __htable_##_name[(_id_max) < ID_HTABLE_SIZE ? (_id_max) : ID_HTABLE_SIZE]; \ +struct IdManager _name = { \ + .id_max = _id_max, \ + .hoffset = (_id_max) < ID_HTABLE_SIZE ? (_id_max) : ID_HTABLE_SIZE, \ + .id_map = __id_map_##_name, \ + .htable = __htable_##_name \ +}; + +int IdInsertObj(struct IdManager *manager, struct IdNode *idnode); +struct IdNode *IdGetObj(struct IdManager *manager, uint16 id); +void IdRemoveObj(struct IdManager *manager, uint16 id); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/Ubiquitous/XiZi/kernel/include/xs_init.h b/Ubiquitous/XiZi/kernel/include/xs_init.h new file mode 100644 index 0000000..09e8131 --- /dev/null +++ b/Ubiquitous/XiZi/kernel/include/xs_init.h @@ -0,0 +1,53 @@ +/* +* Copyright (c) 2020 AIIT XUOS Lab +* XiUOS is licensed under Mulan PSL v2. +* You can use this software according to the terms and conditions of the Mulan PSL v2. +* You may obtain a copy of Mulan PSL v2 at: +* http://license.coscl.org.cn/MulanPSL2 +* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, +* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, +* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. +* See the Mulan PSL v2 for more details. +*/ + +/** +* @file: xs_init.h +* @brief: init function declaration of components +* @version: 1.0 +* @author: AIIT XUOS Lab +* @date: 2020/3/10 +* +*/ + +#ifndef XS_INIT_H +#define XS_INIT_H + +typedef int (*InitFnType)(void); +struct InitSequenceDesc +{ + const char* fn_name; + const InitFnType fn; +}; + +#ifdef KERNEL_COMPONENTS_INIT +void InitCmpts(void); +#endif + + +extern int VfsInit(void); +extern int WorkSysWorkQueueInit(void); +extern int FlashW25qxxSpiDeviceInit(void); +extern int LoraSx12xxSpiDeviceInit(void); +extern int FatfsInit(void); +extern int Ch376fsInit(void); +extern int Lwext4Init(void); +extern int LibcSystemInit(void); +extern int RtcNtpSyncInit(void); +extern int MountSDCard(void); +extern int MountUSB(void); +extern int DfsMountTable(void); +extern int userShellInit(void); +extern int STM32USBHostRegister(void); +extern int WorkSysWorkQueueInit(void); + +#endif diff --git a/Ubiquitous/XiZi/kernel/include/xs_isolation.h b/Ubiquitous/XiZi/kernel/include/xs_isolation.h new file mode 100644 index 0000000..22f56f5 --- /dev/null +++ b/Ubiquitous/XiZi/kernel/include/xs_isolation.h @@ -0,0 +1,63 @@ +/** +* Copyright (c) 2020 AIIT XUOS Lab +* XiUOS is licensed under Mulan PSL v2. +* You can use this software according to the terms and conditions of the Mulan PSL v2. +* You may obtain a copy of Mulan PSL v2 at: +* http://license.coscl.org.cn/MulanPSL2 +* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, +* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, +* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. +* See the Mulan PSL v2 for more details. +*/ + +/** +* @file: xs_isolation.h +* @brief: The macro and callback functions definitions for memory protect +* @version: 1.0 +* @author: AIIT XUOS Lab +* @date: 2020/4/14 +* +*/ + +#ifndef MEMORY_PROTECT_H +#define MEMORY_PROTECT_H + +#include + +#ifdef TASK_ISOLATION +#include +#include + +#if defined(ARCH_ARM) && defined(SURPORT_MPU) +#include +extern struct Mpu *isolation ; +#define MOMERY_PROTECT_ENABLE +#endif + +#if defined(ARCH_RISCV) && defined(SURPORT_PMP) +#include +extern struct Pmp *isolation ; +#define MOMERY_PROTECT_ENABLE +#endif + +#define REGION_TYPE_CODE (1) +#define REGION_TYPE_DATA (2) +#define REGION_TYPE_BSS (3) +#define REGION_TYPE_HEAP (4) + +struct MemoryAccessLimit { + void (* Enable)( uint32_t option); + void (* Disable)(void); + x_err_t (* Init)(void **mem_access); + x_err_t (* InitIsolation)(void **mem_access, x_ubase stack_start , size_t stack_size); + x_err_t (* AddRegion)(void *mem_access, x_ubase start , size_t size , uint8_t region_type ); + x_err_t (* ClearRegion)(void *mem_access, x_ubase addr); + void (* Load)(void *mem_access); + void (* Free)(void *mem_access); + x_bool (* FaultHandle)(void *mem_access, x_ubase addr); +}; + +extern struct MemoryAccessLimit mem_access ; + +#endif +#endif \ No newline at end of file diff --git a/Ubiquitous/XiZi/kernel/include/xs_isr.h b/Ubiquitous/XiZi/kernel/include/xs_isr.h new file mode 100644 index 0000000..9d987d7 --- /dev/null +++ b/Ubiquitous/XiZi/kernel/include/xs_isr.h @@ -0,0 +1,98 @@ +/* +* Copyright (c) 2020 AIIT XUOS Lab +* XiUOS is licensed under Mulan PSL v2. +* You can use this software according to the terms and conditions of the Mulan PSL v2. +* You may obtain a copy of Mulan PSL v2 at: +* http://license.coscl.org.cn/MulanPSL2 +* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, +* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, +* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. +* See the Mulan PSL v2 for more details. +*/ + +/** +* @file: xs_isr.h +* @brief: function declaration and structure defintion of isr +* @version: 1.0 +* @author: AIIT XUOS Lab +* @date: 2020/3/10 +* +*/ + +#ifndef XS_ISR_H +#define XS_ISR_H + +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + + +#define DECLARE_HW_IRQ(_irq_num, _handler, _arg) \ + const uint32 __irq_desc_idx_##_handler SECTION(".isrtbl.idx") = _irq_num + ARCH_IRQ_NUM_OFFSET ; \ + const struct IrqDesc __irq_desc_##_handler SECTION(".isrtbl") = { \ + .handler = _handler, \ + .param = _arg, \ + } + +typedef void (*IsrHandlerType)(int vector, void *param); + +struct IrqDesc +{ + IsrHandlerType handler; + void *param; + +#ifdef CONFIG_INTERRUPT_INFO + char name[NAME_NUM_MAX]; + uint32 counter; +#endif +}; + +struct IsrDone +{ + x_bool (*isInIsr)(); + int32 (*registerIrq)(uint32 irq_num, IsrHandlerType handler, void *arg); + int32 (*freeIrq)(uint32 irq_num); + int32 (*enableIrq)(uint32 irq_num); + int32 (*disableIrq)(uint32 irq_num); + void (*handleIrq)(uint32 irq_num); + uint16 (*getCounter)() ; + void (*incCounter)(); + void (*decCounter)(); + uint8 (*getSwitchTrigerFlag)(); + void (*setSwitchTrigerFlag)(); + void (*clearSwitchTrigerFlag)(); +}; + +struct InterruptServiceRoutines { + +#ifdef ARCH_SMP + volatile uint16 isr_count[CPU_NUMBERS]; + volatile uint8 isr_switch_trigger_flag[CPU_NUMBERS]; +#else + volatile uint16 isr_count ; + volatile uint8 isr_switch_trigger_flag; +#endif + struct IrqDesc irq_table[ARCH_MAX_IRQ_NUM]; + struct IsrDone *done; +}; + +extern struct InterruptServiceRoutines isrManager ; + +x_base DisableLocalInterrupt(); +void EnableLocalInterrupt(x_base level); + +#define DISABLE_INTERRUPT DisableLocalInterrupt +#define ENABLE_INTERRUPT EnableLocalInterrupt + +void SysInitIsrManager(); +void InitHwinterrupt(void); + + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/Ubiquitous/XiZi/kernel/include/xs_kdbg.h b/Ubiquitous/XiZi/kernel/include/xs_kdbg.h new file mode 100644 index 0000000..dcb75ce --- /dev/null +++ b/Ubiquitous/XiZi/kernel/include/xs_kdbg.h @@ -0,0 +1,162 @@ +/* +* Copyright (c) 2020 AIIT XUOS Lab +* XiUOS is licensed under Mulan PSL v2. +* You can use this software according to the terms and conditions of the Mulan PSL v2. +* You may obtain a copy of Mulan PSL v2 at: +* http://license.coscl.org.cn/MulanPSL2 +* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, +* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, +* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. +* See the Mulan PSL v2 for more details. +*/ + +/** +* @file: xs_kdbg.h +* @brief: function declaration and structure defintion of kernel debug +* @version: 1.0 +* @author: AIIT XUOS Lab +* @date: 2020/4/20 +* +*/ + +#ifndef XS_KDBG_H +#define XS_KDBG_H + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +#ifdef KERNEL_DEBUG + +/*Kernel Section Debug Define*/ +#define KDBG_MEM 0 +#define KDBG_MEMHEAP 0 +#define KDBG_SCHED 0 +#define KDBG_KTASK 0 +#define KDBG_SOFTTIMER 0 +#define KDBG_IRQ 0 +#define KDBG_IPC 0 +#define KDBG_HOOK 0 + +#define SYS_KDEBUG_LOG(section, information) \ + do \ + { \ + if(section) { \ + KPrintf information; \ + } \ + }while (0) + +#define KDYN_NONE 0 +#define KDYN_DBG 1 +#define KDYN_ERROR 2 +#define KDYN_WARNING 3 + +#ifdef KDYN_LOG_DBG +#define DBG(args, ...) KDYNAMIC_LOG(KDYN_DBG, args, ##__VA_ARGS__) +#define SYS_ERR(args, ...) KDYNAMIC_LOG(KDYN_ERROR, args, ##__VA_ARGS__) +#define SYS_WARN(args, ...) KDYNAMIC_LOG(KDYN_WARNING, args, ##__VA_ARGS__) +#else +#define DBG(args, ...) KDYNAMIC_LOG(KDYN_NONE, args, ##__VA_ARGS__) +#define SYS_ERR(args, ...) KDYNAMIC_LOG(KDYN_ERROR, args, ##__VA_ARGS__) +#define SYS_WARN(args, ...) KDYNAMIC_LOG(KDYN_WARNING, args, ##__VA_ARGS__) +#endif + +#define KDYNAMIC_LOG(level, args, ...) \ + do \ + { \ + switch(level) \ + { \ + case KDYN_NONE: \ + break; \ + case KDYN_DBG: \ + KPrintf("[DBG]"); \ + KPrintf(args, ##__VA_ARGS__); \ + break; \ + case KDYN_ERROR: \ + KPrintf("[ERR]"); \ + KPrintf(args, ##__VA_ARGS__); \ + break; \ + case KDYN_WARNING: \ + KPrintf("[WARN]"); \ + KPrintf(args, ##__VA_ARGS__); \ + break; \ + default: \ + break; \ + } \ + }while (0) + +#define NULL_PARAM_CHECK(param) \ + do \ + { \ + if(param == NONE) { \ + KPrintf("PARAM CHECK FAILED ...%s %d %s is NULL.\n",__FUNCTION__,__LINE__,#param); \ + while(RET_TRUE); \ + } \ + }while (0) + +#define CHECK(TRUE_CONDITION) \ + do \ + { \ + if(!(TRUE_CONDITION)) { \ + KPrintf("%s CHECK condition is false at line[%d] of [%s] func.\n",#TRUE_CONDITION,__LINE__,__FUNCTION__);\ + while(RET_TRUE); \ + } \ + } while(0) + + +#define KDEBUG_NOT_IN_INTERRUPT \ + do \ + { \ + x_base level; \ + level = DISABLE_INTERRUPT(); \ + if (isrManager.done->getCounter() != 0) \ + { \ + KPrintf("Function[%s] is not supported in ISR\n", __FUNCTION__); \ + CHECK(0); \ + } \ + ENABLE_INTERRUPT(level); \ + } while (0) + +#define KDEBUG_IN_KTASK_CONTEXT \ + do \ + { \ + x_base level; \ + level = DISABLE_INTERRUPT(); \ + if (GetKTaskDescriptor() == NONE) \ + { \ + KPrintf("Function[%s] is not supported before task assign\n", __FUNCTION__); \ + CHECK(0); \ + } \ + KDEBUG_NOT_IN_INTERRUPT; \ + ENABLE_INTERRUPT(level); \ + } while (0) + +#define NOT_IN_CRITICAL_AREA \ + do { \ + if(GetOsAssignLockLevel() != 0){ \ + KPrintf("Function[%s] is not supported switch in critical area.\n", __FUNCTION__); \ + CHECK(0); \ + } \ + } while (0) + +#else + +#define SYS_KDEBUG_LOG(section, information) +#define DBG(args, ...) +#define SYS_ERR(args, ...) +#define SYS_WARN(args, ...) +#define NULL_PARAM_CHECK(param) +#define CHECK(TRUE_CONDITION) +#define KDEBUG_NOT_IN_INTERRUPT +#define KDEBUG_IN_KTASK_CONTEXT +#define NOT_IN_CRITICAL_AREA + +#endif + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/Ubiquitous/XiZi/kernel/include/xs_kdevice.h b/Ubiquitous/XiZi/kernel/include/xs_kdevice.h new file mode 100644 index 0000000..c3d2bf3 --- /dev/null +++ b/Ubiquitous/XiZi/kernel/include/xs_kdevice.h @@ -0,0 +1,100 @@ +/* +* Copyright (c) 2020 AIIT XUOS Lab +* XiUOS is licensed under Mulan PSL v2. +* You can use this software according to the terms and conditions of the Mulan PSL v2. +* You may obtain a copy of Mulan PSL v2 at: +* http://license.coscl.org.cn/MulanPSL2 +* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, +* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, +* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. +* See the Mulan PSL v2 for more details. +*/ + +/** +* @file: xs_kdevice.h +* @brief: macor and structure defintion of kdevice +* @version: 1.0 +* @author: AIIT XUOS Lab +* @date: 2020/4/20 +* +*/ + +#ifndef XS_KDEVICE_H +#define XS_KDEVICE_H + +/* import board special configuration */ +#include +#include + +#ifdef TOOL_SHELL +#include "shell.h" +#else +#define SHELL_EXPORT_CMD(_attr, _name, _func, _desc) +#endif + +#ifdef __cplusplus +extern "C" { +#endif + +#define OSIGN_OPER_CLOSE (0U << 0) +#define OSIGN_OPER_RDONLY (1U << 0) +#define OSIGN_OPER_WRONLY (1U << 1) +#define OSIGN_OPER_RDWR (OSIGN_OPER_WRONLY| OSIGN_OPER_RDONLY ) +#define OSIGN_OPER_OPEN (1U << 3) +#define OSIGN_OPER_MASK 0xf0f + +#define SIGN_OPER_DEACTIVATE (0U << 0) +#define SIGN_OPER_RDONLY (1U << 0) +#define SIGN_OPER_WRONLY (1U << 1) +#define SIGN_OPER_RDWR (SIGN_OPER_RDONLY|SIGN_OPER_WRONLY) +#define SIGN_OPER_REMOVABLE (1U << 2) +#define SIGN_OPER_STANDALONE (1U << 3) +#define SIGN_OPER_ACTIVATED (1U << 4) +#define SIGN_OPER_SUSPENDED (1U << 5) +#define SIGN_OPER_STREAM (1U << 6) +#define SIGN_OPER_INT_RX (1U << 8) +#define SIGN_OPER_DMA_RX (1U << 9) +#define SIGN_OPER_INT_TX (1U << 10) +#define SIGN_OPER_DMA_TX (1U << 11) + +enum SIGN_OPER +{ + OPER_RESUME = 0x01, + OPER_SUSPEND = 0x02, + OPER_CONFIG = 0x03, + OPER_SET_INT = 0x10, + OPER_CLR_INT = 0x11, + OPER_GET_INT = 0x12, + OPER_CHAR_STREAM = 0x10, + OPER_BLK_GETGEOME = 0x10, + OPER_BLK_SYNC = 0x11, + OPER_BLK_ERASE = 0x12, + OPER_BLK_AUTOREFRESH = 0x13, + OPER_NETIF_GETMAC = 0x10, + OPER_MTD_FORMAT = 0x10, + OPER_RTC_GET_TIME = 0x10, + OPER_RTC_SET_TIME = 0x11, + OPER_RTC_GET_ALARM = 0x12, + OPER_RTC_SET_ALARM = 0x13, +}; + +struct DeviceBlockArrange +{ + uint32 bank_num; + uint32 size_perbank; + uint32 block_size; + uint16 bank_start; + uint16 bank_end; +}; + +struct DeviceBlockAddr +{ + uint32_t start; + uint32_t end; +}; + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/Ubiquitous/XiZi/kernel/include/xs_klist.h b/Ubiquitous/XiZi/kernel/include/xs_klist.h new file mode 100644 index 0000000..3234bf6 --- /dev/null +++ b/Ubiquitous/XiZi/kernel/include/xs_klist.h @@ -0,0 +1,121 @@ +/* +* Copyright (c) 2020 AIIT XUOS Lab +* XiUOS is licensed under Mulan PSL v2. +* You can use this software according to the terms and conditions of the Mulan PSL v2. +* You may obtain a copy of Mulan PSL v2 at: +* http://license.coscl.org.cn/MulanPSL2 +* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, +* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, +* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. +* See the Mulan PSL v2 for more details. +*/ + +/** +* @file: xs_klist.h +* @brief: function declaration and structure defintion of linklist +* @version: 1.0 +* @author: AIIT XUOS Lab +* @date: 2020/3/2 +* +*/ + +#ifndef XS_KLIST_H +#define XS_KLIST_H + +#include +#include "libc.h" + +#ifdef __cplusplus +extern "C" { +#endif + +#define LINKLIST_FLAG_FIFO 0x00 +#define LINKLIST_FLAG_PRIO 0x01 + +typedef struct SysDoubleLinklistNode +{ + struct SysDoubleLinklistNode *node_next; + struct SysDoubleLinklistNode *node_prev; +} DoubleLinklistType; + +// Single List +typedef struct SingleLinklistNode +{ + struct SingleLinklistNode *node_next; +} SysSingleLinklistType; + + +#define CONTAINER_OF(item, type, member) \ + ((type *)((char *)(item) - (unsigned long)(&((type *)0)->member))) + + +#define DOUBLE_LINKLIST_OBJ_INIT(obj) { &(obj), &(obj) } + +void InitDoubleLinkList(DoubleLinklistType *linklist_head); +void DoubleLinkListInsertNodeAfter(DoubleLinklistType *linklist, DoubleLinklistType *linklist_node); +void DoubleLinkListInsertNodeBefore(DoubleLinklistType *linklist, DoubleLinklistType *linklist_node); +void DoubleLinkListRmNode(DoubleLinklistType *linklist_node); +int IsDoubleLinkListEmpty(const DoubleLinklistType *linklist); +struct SysDoubleLinklistNode *DoubleLinkListGetHead(const DoubleLinklistType *linklist); +struct SysDoubleLinklistNode *DoubleLinkListGetNext(const DoubleLinklistType *linklist, + const struct SysDoubleLinklistNode *linklist_node); +unsigned int DoubleLinkListLenGet(const DoubleLinklistType *linklist); + +#define SYS_DOUBLE_LINKLIST_ENTRY(item, type, member) \ + CONTAINER_OF(item, type, member) + +#define DOUBLE_LINKLIST_FOR_EACH(item, head) \ + for (item = (head)->node_next; item != (head); item = item->node_next) + +#define DOUBLE_LINKLIST_FOR_EACH_SAFE(item, node_next, head) \ + for (item = (head)->node_next, node_next = item->node_next; item != (head); \ + item = node_next, node_next = item->node_next) + +#define DOUBLE_LINKLIST_FOR_EACH_ENTRY(item, head, member) \ + for (item = SYS_DOUBLE_LINKLIST_ENTRY((head)->node_next, typeof(*item), member); \ + &item->member != (head); \ + item = SYS_DOUBLE_LINKLIST_ENTRY(item->member.node_next, typeof(*item), member)) + +#define DOUBLE_LINKLIST_FOR_EACH_ENTRY_SAFE(item, node_next, head, member) \ + for (item = SYS_DOUBLE_LINKLIST_ENTRY((head)->node_next, typeof(*item), member), \ + node_next = SYS_DOUBLE_LINKLIST_ENTRY(item->member.node_next, typeof(*item), member); \ + &item->member != (head); \ + item = node_next, node_next = SYS_DOUBLE_LINKLIST_ENTRY(node_next->member.node_next, typeof(*node_next), member)) + +#define DOUBLE_LINKLIST_FIRST_ENTRY(ptr, type, member) \ + SYS_DOUBLE_LINKLIST_ENTRY((ptr)->node_next, type, member) + +#define SYS_SINGLE_LINKLIST_OBJ_INIT(obj) { NONE } + +void InitSingleLinkList(SysSingleLinklistType *linklist); +void AppendSingleLinkList(SysSingleLinklistType *linklist, SysSingleLinklistType *linklist_node); +void SingleLinkListNodeInsert(SysSingleLinklistType *linklist, SysSingleLinklistType *linklist_node); +unsigned int SingleLinkListGetLen(const SysSingleLinklistType *linklist); +SysSingleLinklistType *SingleLinkListRmNode(SysSingleLinklistType *linklist, SysSingleLinklistType *linklist_node); +SysSingleLinklistType *SingleLinkListGetFirstNode(SysSingleLinklistType *linklist); +SysSingleLinklistType *SingleLinkListGetTailNode(SysSingleLinklistType *linklist); +SysSingleLinklistType *SingleLinkListGetNextNode(SysSingleLinklistType *linklist_node); +int IsSingleLinkListEmpty(SysSingleLinklistType *linklist); + +#define SYS_SINGLE_LINKLIST_ENTRY(node, type, member) \ + CONTAINER_OF(node, type, member) + +#define SINGLE_LINKLIST_FOR_EACH(item, head) \ + for (item = (head)->node_next; item != NONE; item = item->node_next) + +#define SINGLE_LINKLIST_FOR_EACH_ENTRY(item, head, member) \ + for (item = SYS_SINGLE_LINKLIST_ENTRY((head)->node_next, typeof(*item), member); \ + &item->member != (NONE); \ + item = SYS_SINGLE_LINKLIST_ENTRY(item->member.node_next, typeof(*item), member)) + +#define SINGLE_LINKLIST_FIRST_ENTRY(ptr, type, member) \ + SYS_SINGLE_LINKLIST_ENTRY((ptr)->node_next, type, member) + +#define SINGLE_LINKLIST_TAIL_ENTRY(ptr, type, member) \ + SYS_SINGLE_LINKLIST_ENTRY(SingleLinkListGetTailNode(ptr), type, member) + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/Ubiquitous/XiZi/kernel/include/xs_ktask.h b/Ubiquitous/XiZi/kernel/include/xs_ktask.h new file mode 100644 index 0000000..8e99199 --- /dev/null +++ b/Ubiquitous/XiZi/kernel/include/xs_ktask.h @@ -0,0 +1,223 @@ +/* + * Copyright (c) 2020 AIIT XUOS Lab + * XiUOS is licensed under Mulan PSL v2. + * You can use this software according to the terms and conditions of the Mulan PSL v2. + * You may obtain a copy of Mulan PSL v2 at: + * http://license.coscl.org.cn/MulanPSL2 + * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, + * EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, + * MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. + * See the Mulan PSL v2 for more details. + */ + +/** +* @file: xs_ktask.h +* @brief: function declaration and structure defintion of kernel task +* @version: 1.0 +* @author: AIIT XUOS Lab +* @date: 2020/3/10 +* +*/ + +#ifndef XS_KTASK_H +#define XS_KTASK_H + +#include +#include +#include +#include +#include +#include + +#ifdef __cplusplus + extern "C" { +#endif + +#define KTASK_LOWEST_PRIORITY 0 +#define KTASK_INIT 0x00 +#define KTASK_READY 0x01 +#define KTASK_SUSPEND 0x02 +#define KTASK_RUNNING 0x03 +#define KTASK_CLOSE 0x04 +#define KTASK_STAT_MASK 0x07 + +#define KTASK_MAX_ADVANCE_PROCESS_TIME 0x1 ///< task max advance process times +#define UNCOMBINE_CPU_CORE CPU_NUMBERS + +#ifdef ARCH_SMP + +#define CPU_MASK ((1 << CPU_NUMBERS) - 1) /**< All CPUs mask bit. */ + +#ifndef ASSIGN_IPI +#define ASSIGN_IPI 0 +#endif + +#endif + +struct TaskBaseInfo { + char name[NAME_NUM_MAX]; ///< task name + void *func_entry; ///< task function entry + void *func_param; ///< task parameter + uint8 origin_prio; ///< task init priority + uint32 stack_depth; ///< task stack size + void *stack_start; ///< task stack start address +}; +typedef struct TaskBaseInfo TaskBaseInfoType; + +struct TaskDyncSchedMember { + uint8 stat; ///< task stat + uint8 advance_cnt; ///< total time slice advance process count + uint8 cur_prio; ///< task current priority + x_ubase origin_timeslice; ///< task init timeslice + x_ubase rest_timeslice; ///< task remaining timeslice +#ifdef SEPARATE_COMPILE + uint8 isolation_flag; ///< task isolation flag + void *isolation; ///< task isolation pointer + uint8 isolation_status; +#if defined(ARCH_ARM) + uint32_t svc_return; +#endif +#endif + + DoubleLinklistType sched_link; ///< task sched list +#if KTASK_PRIORITY_MAX > 32 + uint8 bitmap_offset; + uint8 bitmap_row; +#endif + uint32 bitmap_column; + DelayType delay; +}; +typedef struct TaskDyncSchedMember TaskDyncSchedMembeType; + +#ifdef ARCH_SMP +struct TaskSmpInfo { + uint8 combined_coreid; ///< task bind core id + uint8 runing_coreid; ///< task running core id + uint16 critical_lock_cnt; ///< critical lock count +}; +typedef struct TaskSmpInfo TaskSmpInfoType; +#endif + +struct TaskDescriptor +{ + void *stack_point; ///< stack point + TaskDyncSchedMembeType task_dync_sched_member; ///< task dynamic sched member + TaskBaseInfoType task_base_info; ///< task base information +#ifdef ARCH_SMP + TaskSmpInfoType task_smp_info; ///< dual core information +#endif + +#if defined(KERNEL_EVENT) + uint32 event_id_trigger : 29 ; ///< event ops (event trigger ) + uint32 event_mode : 3; ///< event mode (AND/OR/AUTOCLEAN) +#endif + + x_err_t exstatus; ///< exception status + DoubleLinklistType link; ///< manage list + struct IdNode id; ///< task id + struct KTaskDone *Done; +}; +typedef struct TaskDescriptor *KTaskDescriptorType; + +struct OsAssignReadyVector { + DoubleLinklistType priority_ready_vector[KTASK_PRIORITY_MAX]; + uint32 priority_ready_group; +#if KTASK_PRIORITY_MAX > 32 + /* Maximum priority level, 256 */ + uint8 ready_vector[32]; +#endif + x_ubase highest_prio; +}; + +struct KTaskDone +{ + int32 (*init)(KTaskDescriptorType task, + const char *name, + void (*entry)(void *parameter), + void *parameter, + uint32 stack_size, + uint8 priority); + + x_err_t (*start)(KTaskDescriptorType task); + x_err_t (*Delete)(KTaskDescriptorType task); + x_err_t (*delay)(KTaskDescriptorType task, x_ticks_t ticks); + x_err_t (*mdelay)(KTaskDescriptorType task,uint32 ms); + x_err_t (*prioset)(KTaskDescriptorType task, uint8 prio); +#ifdef ARCH_SMP + x_err_t (*combine)(KTaskDescriptorType task, uint8 coreid); + x_err_t (*uncombine)(KTaskDescriptorType task); +#endif + x_err_t (*suspend)(KTaskDescriptorType task); + x_err_t (*wake)(KTaskDescriptorType task); +}; +int32 KTaskCreate(const char *name, + + void (*entry)(void *parameter), + void *parameter, + uint32 stack_size, + uint8 priority); +void KTaskQuit(void); + +#ifdef SEPARATE_COMPILE +int UTaskSearch(void); +int32 UTaskCreate(const char *name, + void (*entry)(void *parameter), + void *parameter, + uint32 stack_size, + uint8 priority); + +#endif + +void KUpdateExstatus(x_err_t no); +int *KObtainExstatus(void); +#if !defined(LIB_NEWLIB) && !defined(_WIN32) +#ifndef errno +#define errno *KObtainExstatus() +#endif +#endif + +KTaskDescriptorType GetKTaskDescriptor(void); +KTaskDescriptorType KTaskSearch(char *name); +x_err_t StartupKTask(int32 id); +x_err_t KTaskDelete(int32 id); +x_err_t YieldOsAssign(void); +x_err_t DelayKTask(x_ticks_t tick); +x_err_t MdelayKTask(uint32 ms); +x_err_t KTaskPrioSet(int32 id, uint8 prio); +x_err_t KTaskCoreCombine(int32 id, uint8 coreid); +x_err_t KTaskCoreUnCombine(int32 id); +x_err_t SuspendKTask(int32 id); +x_err_t KTaskWakeup(int32 id); +void KTaskTimeout(void *parameter); +void InitIdleKTask(void); +void IdleKTaskExec(void); +KTaskDescriptorType GetIdleKTaskDescripter(void); +void KTaskOsAssign(void); +void KTaskOsAssignRemoveKTask(struct TaskDescriptor *task); + +#if defined (SCHED_POLICY_FIFO) +void FifoTaskTimesliceInit(struct TaskDescriptor *task); +void FifoReadyVectorInsert(struct TaskDescriptor *task, struct OsAssignReadyVector* ready_table); +void FifoTaskTimesliceUpdate(); +#elif defined (SCHED_POLICY_RR) +void RoundRobinTaskTimesliceInit(struct TaskDescriptor *task); +void RoundRobinReadyVectorInsert(struct TaskDescriptor *task, struct OsAssignReadyVector* ready_table); +void RoundRobinTaskTimesliceUpdate(struct TaskDescriptor *task); +#elif defined (SCHED_POLICY_RR_REMAINSLICE) +void RoundRobinRemainTaskTimesliceInit(struct TaskDescriptor *task); +void RoundRobinRemainReadyVectorInsert(struct TaskDescriptor *task, struct OsAssignReadyVector* ready_table); +void RoundRobinRemainTaskTimesliceUpdate(struct TaskDescriptor *task); +#endif + +x_err_t LinklistSuspend(DoubleLinklistType *list,struct TaskDescriptor *task,uint8 flag); +x_err_t LinklistResume(DoubleLinklistType *list); +x_err_t LinklistResumeAll(DoubleLinklistType *list); +void HwSendIpi(int ipi_vector, unsigned int cpu_mask); +void KTaskIdDelete(int32 id); +struct TaskDescriptor *GetTaskWithIdnodeInfo(int32 id); + +#ifdef __cplusplus + } +#endif + +#endif diff --git a/Ubiquitous/XiZi/kernel/include/xs_ktask_stat.h b/Ubiquitous/XiZi/kernel/include/xs_ktask_stat.h new file mode 100644 index 0000000..8f9c8f3 --- /dev/null +++ b/Ubiquitous/XiZi/kernel/include/xs_ktask_stat.h @@ -0,0 +1,44 @@ +/* +* Copyright (c) 2020 AIIT XUOS Lab +* XiUOS is licensed under Mulan PSL v2. +* You can use this software according to the terms and conditions of the Mulan PSL v2. +* You may obtain a copy of Mulan PSL v2 at: +* http://license.coscl.org.cn/MulanPSL2 +* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, +* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, +* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. +* See the Mulan PSL v2 for more details. +*/ + +/** +* @file: xs_ktask_stat.h +* @brief: function declaration of task stat +* @version: 1.0 +* @author: AIIT XUOS Lab +* @date: 2020/3/10 +* +*/ + +#ifndef XS_KTASK_STAT_H +#define XS_KTASK_STAT_H + +#include +#include +#include + +void KTaskStateSet(KTaskDescriptorType task, uint8 stat); +void KTaskStatSetAsInit(KTaskDescriptorType task); +void KTaskStatSetAsReady(KTaskDescriptorType task); +void KTaskStatSetAsSuspend(KTaskDescriptorType task); +void KTaskStatSetAsRunning(KTaskDescriptorType task); +void KTaskStatSetAsClose(KTaskDescriptorType task); +uint8 KTaskStatGet(KTaskDescriptorType task); +bool JudgeKTaskStatIsInit(KTaskDescriptorType task); +bool JudgeKTaskStatIsReady(KTaskDescriptorType task); +bool JudgeKTaskStatIsSuspend(KTaskDescriptorType task); +bool JudgeKTaskStatIsRunning(KTaskDescriptorType task); +bool JudgeKTaskStatIsClose(KTaskDescriptorType task); + +#endif + + diff --git a/Ubiquitous/XiZi/kernel/include/xs_ktick.h b/Ubiquitous/XiZi/kernel/include/xs_ktick.h new file mode 100644 index 0000000..faaf195 --- /dev/null +++ b/Ubiquitous/XiZi/kernel/include/xs_ktick.h @@ -0,0 +1,32 @@ +/* +* Copyright (c) 2020 AIIT XUOS Lab +* XiUOS is licensed under Mulan PSL v2. +* You can use this software according to the terms and conditions of the Mulan PSL v2. +* You may obtain a copy of Mulan PSL v2 at: +* http://license.coscl.org.cn/MulanPSL2 +* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, +* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, +* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. +* See the Mulan PSL v2 for more details. +*/ + +/** +* @file: xs_ktick.h +* @brief: function declaration of kernel tick +* @version: 1.0 +* @author: AIIT XUOS Lab +* @date: 2020/3/2 +* +*/ + +#ifndef XS_KTICK_H +#define XS_KTICK_H + +#include + +x_ticks_t CurrentTicksGain(void); +void TickAndTaskTimesliceUpdate(void); +x_ticks_t CalculteTickFromTimeMs(uint32 ms); +uint32 CalculteTimeMsFromTick(x_ticks_t ticks); + +#endif diff --git a/Ubiquitous/XiZi/kernel/include/xs_memory.h b/Ubiquitous/XiZi/kernel/include/xs_memory.h new file mode 100644 index 0000000..0d9c9f9 --- /dev/null +++ b/Ubiquitous/XiZi/kernel/include/xs_memory.h @@ -0,0 +1,110 @@ +/* +* Copyright (c) 2020 AIIT XUOS Lab +* XiUOS is licensed under Mulan PSL v2. +* You can use this software according to the terms and conditions of the Mulan PSL v2. +* You may obtain a copy of Mulan PSL v2 at: +* http://license.coscl.org.cn/MulanPSL2 +* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, +* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, +* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. +* See the Mulan PSL v2 for more details. +*/ + +/** +* @file: xs_memory.h +* @brief: function declaration and structure defintion of memory +* @version: 1.0 +* @author: AIIT XUOS Lab +* @date: 2020/3/2 +* +*/ + +#ifndef XS_MEMORY_H +#define XS_MEMORY_H + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +#ifndef MM_PAGE_SIZE +#define MM_PAGE_SIZE 4096 +#endif + +#define MM_PAGE_MASK (MM_PAGE_SIZE - 1) +#define MM_PAGE_BITS 12 + +/* Set static memory block */ +#ifndef SMALL_NUMBER_32B +#define SMALL_NUMBER_32B (0) /* Calculate the numbers of SIZEOF_32B blocks*/ +#endif + +#ifndef SMALL_NUMBER_64B +#define SMALL_NUMBER_64B (0) /* Calculate the numbers of SIZEOF_64B blocks*/ +#endif + +#ifndef KERNEL_MALLOC +#define KERNEL_MALLOC(sz) x_malloc(sz) +#endif + +#ifndef KERNEL_FREE +#define KERNEL_FREE(ptr) x_free(ptr) +#endif + +#ifndef KERNEL_REALLOC +#define KERNEL_REALLOC(ptr, size) x_realloc(ptr, size) +#endif + +#ifdef KERNEL_MEMBLOCK +struct MemGather +{ + char m_name[NAME_NUM_MAX]; + uint8 m_kind; + uint8 m_sign; + + DoubleLinklistType m_link; + + void *m_start_address; + x_size_t m_size; + x_size_t one_block_size; + uint8 *m_block_link; + + x_size_t block_total_number; + x_size_t block_free_number; + DoubleLinklistType wait_task; +}; +typedef struct MemGather *GatherMemType; + +x_err_t InitMemGather(struct MemGather *gm_handler, const char *gm_name, void *begin_address, x_size_t gm_size, x_size_t one_block_size); +x_err_t RemoveMemGather(struct MemGather *gm_handler); +GatherMemType CreateMemGather(const char *gm_name, x_size_t block_number, x_size_t one_block_size); +x_err_t DeleteMemGather(GatherMemType gm_handler); +void *AllocBlockMemGather(GatherMemType gm_handler, int32 wait_time); +void FreeBlockMemGather(void *data_block); +#endif + +void InitBoardMemory(void *begin_addr, void *end_addr); +#ifdef MEM_EXTERN_SRAM +void ExtSramInitBoardMemory(void *start_phy_address, void *end_phy_address, uint8 extsram_idx); +#endif +void *x_malloc(x_size_t nbytes); +void x_free(void *ptr); +void *x_realloc(void *ptr, x_size_t nbytes); +void *x_calloc(x_size_t count, x_size_t size); + +#ifdef USER_APPLICATION +void UserInitBoardMemory(void *begin_addr, void *end_addr); +void *x_umalloc(x_size_t nbytes); +void x_ufree(void *ptr); +void *x_urealloc(void *ptr, x_size_t nbytes); +void *x_ucalloc(x_size_t count, x_size_t size); +#endif + +void MemoryInfo(uint32 *total, uint32 *used, uint32 *max_used); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/Ubiquitous/XiZi/kernel/include/xs_msg.h b/Ubiquitous/XiZi/kernel/include/xs_msg.h new file mode 100644 index 0000000..39f9f95 --- /dev/null +++ b/Ubiquitous/XiZi/kernel/include/xs_msg.h @@ -0,0 +1,67 @@ +/* + * Copyright (c) 2020 AIIT XUOS Lab + * XiUOS is licensed under Mulan PSL v2. + * You can use this software according to the terms and conditions of the Mulan PSL v2. + * You may obtain a copy of Mulan PSL v2 at: + * http://license.coscl.org.cn/MulanPSL2 + * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, + * EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, + * MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. + * See the Mulan PSL v2 for more details. + */ + +/** +* @file: xs_msg.h +* @brief: function declaration and structure defintion of message queue +* @version: 1.0 +* @author: AIIT XUOS Lab +* @date: 2020/3/2 +* +*/ + +#ifndef XS_MSG_H +#define XS_MSG_H + +#include +#include +#include +#include + +#ifdef KERNEL_MESSAGEQUEUE + +struct MsgQueue +{ + struct IdNode id; + void *msg_buf; + uint16 index; + uint16 num_msgs; + uint16 each_len; + uint16 max_msgs; + + DoubleLinklistType send_pend_list; + DoubleLinklistType recv_pend_list; + DoubleLinklistType link; + struct MsgQueueDone *Done; +}; +typedef struct MsgQueue *MsgQueueType; + +struct MsgQueueDone +{ + x_err_t (*init)(struct MsgQueue *mq, x_size_t msg_size, x_size_t max_msgs ); + x_err_t (*urgensend)(struct MsgQueue *mq, const void *buffer, x_size_t size); + x_err_t (*send)(struct MsgQueue *mq, const void *buffer, x_size_t size,int32 timeout); + x_err_t (*recv)(struct MsgQueue *mq, void *buffer, x_size_t size, int32 timeout); + x_err_t (*reinit)(struct MsgQueue *mq); + x_err_t (*Delete)(struct MsgQueue *mq); +}; + +int32 KCreateMsgQueue( x_size_t msg_size, x_size_t max_msgs ); +x_err_t KMsgQueueSendwait(int32 id, const void *buffer, x_size_t size, int32 timeout); +x_err_t KMsgQueueUrgentSend(int32 id, const void *buffer, x_size_t size); +x_err_t KMsgQueueSend(int32 id, const void *buffer, x_size_t size); +x_err_t KMsgQueueRecv(int32 id, void *buffer, x_size_t size, int32 timeout); +x_err_t KMsgQueueReinit(int32 id); +x_err_t KDeleteMsgQueue(int32 id); +#endif + +#endif diff --git a/Ubiquitous/XiZi/kernel/include/xs_mutex.h b/Ubiquitous/XiZi/kernel/include/xs_mutex.h new file mode 100644 index 0000000..683e6da --- /dev/null +++ b/Ubiquitous/XiZi/kernel/include/xs_mutex.h @@ -0,0 +1,56 @@ +/* + * Copyright (c) 2020 AIIT XUOS Lab + * XiUOS is licensed under Mulan PSL v2. + * You can use this software according to the terms and conditions of the Mulan PSL v2. + * You may obtain a copy of Mulan PSL v2 at: + * http://license.coscl.org.cn/MulanPSL2 + * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, + * EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, + * MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. + * See the Mulan PSL v2 for more details. + */ + +/** +* @file: xs_mutex.h +* @brief: function declaration and structure defintion of mutex +* @version: 1.0 +* @author: AIIT XUOS Lab +* @date: 2020/3/10 +* +*/ + +#ifndef XS_MUTEX_H +#define XS_MUTEX_H + +#include +#include +#include +#include +#include + +#ifdef KERNEL_MUTEX + +struct Mutex { + struct IdNode id; + uint16 val; + uint8 recursive_cnt; + uint8 origin_prio; + struct TaskDescriptor *holder; + DoubleLinklistType pend_list; + DoubleLinklistType link; +}; + +typedef struct { + int32 (*MutexCreate)(); + void (*MutexDelete)(struct Mutex *mutex); + int32 (*MutexObtain)(struct Mutex *mutex, int32 wait_time); + int32 (*MutexAbandon)(struct Mutex *mutex); +} MutexDoneType; + +int32 KMutexCreate(); +void KMutexDelete(int32 id); +int32 KMutexObtain(int32 id, int32 wait_time); +int32 KMutexAbandon(int32 id); +#endif + +#endif diff --git a/Ubiquitous/XiZi/kernel/include/xs_poll.h b/Ubiquitous/XiZi/kernel/include/xs_poll.h new file mode 100644 index 0000000..2256343 --- /dev/null +++ b/Ubiquitous/XiZi/kernel/include/xs_poll.h @@ -0,0 +1,60 @@ +/* +* Copyright (c) 2020 AIIT XUOS Lab +* XiUOS is licensed under Mulan PSL v2. +* You can use this software according to the terms and conditions of the Mulan PSL v2. +* You may obtain a copy of Mulan PSL v2 at: +* http://license.coscl.org.cn/MulanPSL2 +* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, +* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, +* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. +* See the Mulan PSL v2 for more details. +*/ + +/** +* @file: xs_pool.h +* @brief: function declaration and structure defintion of poll +* @version: 1.0 +* @author: AIIT XUOS Lab +* @date: 2020/4/20 +* +*/ + +#ifndef XS_POLL_H +#define XS_POLL_H + +#include +#include +#include + +typedef unsigned long NfdsType; + +#if !defined(POLLIN) && !defined(POLLOUT) + +#define POLLIN 0x001 +#define POLLOUT 0x002 +#define POLLERR 0x004 +#define POLLHUP 0x008 +#define POLLNVAL 0x010 + +#define POLLMASK_DEFAULT (POLLIN | POLLOUT ) + +struct pollfd +{ + int fd; + short events; + short revents; +}; +#endif +struct Pollreq; +typedef void (*poll_queue_proc)(WaitQueueType *, struct Pollreq *); +typedef struct Pollreq +{ + poll_queue_proc _proc; + short _key; +} pollreqType; + +void PollAdd(WaitQueueType *wq, pollreqType *req); +#ifndef poll +int poll(struct pollfd *fds, NfdsType nfds, int timeout); +#endif +#endif diff --git a/Ubiquitous/XiZi/kernel/include/xs_queue_manager.h b/Ubiquitous/XiZi/kernel/include/xs_queue_manager.h new file mode 100644 index 0000000..f7ae011 --- /dev/null +++ b/Ubiquitous/XiZi/kernel/include/xs_queue_manager.h @@ -0,0 +1,47 @@ +/* +* Copyright (c) 2020 AIIT XUOS Lab +* XiUOS is licensed under Mulan PSL v2. +* You can use this software according to the terms and conditions of the Mulan PSL v2. +* You may obtain a copy of Mulan PSL v2 at: +* http://license.coscl.org.cn/MulanPSL2 +* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, +* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, +* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. +* See the Mulan PSL v2 for more details. +*/ + +/** +* @file: xs_queue_manager.h +* @brief: function declaration and structure defintion of queue manager +* @version: 1.0 +* @author: AIIT XUOS Lab +* @date: 2020/4/20 +* +*/ + +#ifndef XS_QUEUE_MANAGER_H +#define XS_QUEUE_MANAGER_H + +#include + +#ifndef QUEUE_MAX +#define QUEUE_MAX 16 +#endif + +typedef struct +{ + void *property; + void *done; +} queue; + +enum QUEUE_TYPE +{ + DATA_QUEUE = 1, + WORK_QUEUE, + WAIT_QUEUE, +}; + +extern void *g_queue_done[]; +extern void QueuemanagerDoneRegister(); + +#endif \ No newline at end of file diff --git a/Ubiquitous/XiZi/kernel/include/xs_sem.h b/Ubiquitous/XiZi/kernel/include/xs_sem.h new file mode 100644 index 0000000..e7cae4f --- /dev/null +++ b/Ubiquitous/XiZi/kernel/include/xs_sem.h @@ -0,0 +1,57 @@ +/* + * Copyright (c) 2020 AIIT XUOS Lab + * XiUOS is licensed under Mulan PSL v2. + * You can use this software according to the terms and conditions of the Mulan PSL v2. + * You may obtain a copy of Mulan PSL v2 at: + * http://license.coscl.org.cn/MulanPSL2 + * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, + * EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, + * MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. + * See the Mulan PSL v2 for more details. + */ + +/** +* @file: xs_sem.h +* @brief: function declaration and structure defintion of sem +* @version: 1.0 +* @author: AIIT XUOS Lab +* @date: 2020/3/12 +* +*/ + +#ifndef XS_SEM_H +#define XS_SEM_H + +#include +#include +#include +#include +#include + +#ifdef KERNEL_SEMAPHORE + +struct Semaphore +{ + struct IdNode id; + uint16 value; + + DoubleLinklistType pend_list; + DoubleLinklistType link; +}; + +typedef struct { + int32 (*SemaphoreCreate)(uint16 val); + void (*SemaphoreDelete)(struct Semaphore *sem); + int32 (*SemaphoreObtain)(struct Semaphore *sem, int32 wait_time); + int32 (*SemaphoreAbandon)(struct Semaphore *sem); + int32 (*SemaphoreSetValue)(struct Semaphore *sem, uint16 val); +} SemaphoreDoneType; + +int32 KSemaphoreCreate(uint16 val); +void KSemaphoreDelete(int32 id); +int32 KSemaphoreObtain(int32 id, int32 wait_time); +int32 KSemaphoreAbandon(int32 id); +int32 KSemaphoreSetValue(int32 id, uint16 val); + +#endif +#endif diff --git a/Ubiquitous/XiZi/kernel/include/xs_service.h b/Ubiquitous/XiZi/kernel/include/xs_service.h new file mode 100644 index 0000000..d213f9f --- /dev/null +++ b/Ubiquitous/XiZi/kernel/include/xs_service.h @@ -0,0 +1,116 @@ +/* + * Copyright (c) 2020 AIIT XUOS Lab + * XiUOS is licensed under Mulan PSL v2. + * You can use this software according to the terms and conditions of the Mulan PSL v2. + * You may obtain a copy of Mulan PSL v2 at: + * http://license.coscl.org.cn/MulanPSL2 + * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, + * EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, + * MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. + * See the Mulan PSL v2 for more details. + */ + +/** +* @file: xs_service.h +* @brief: maroc and switch table definition of kernel switch +* @version: 1.0 +* @author: AIIT XUOS Lab +* @date: 2020/3/10 +* +*/ + +#ifndef XS_SERVICE_H +#define XS_SERVICE_H +#include +#include "xs_base.h" + +#ifdef SEPARATE_COMPILE +// #include + +enum KernelServiceEnum +{ + KS_USER_PRINT_INFO = 0, + KS_USER_TASK_CREATE , + KS_USER_TASK_STARTUP , + KS_USER_TASK_DELETE, + KS_USER_TASK_SEARCH, + KS_USER_TASK_EXECEXIT, + KS_USER_TASK_CORE_COMBINE, + KS_USER_TASK_CORE_UNCOMBINE, + KS_USER_TASK_DELAY, + KS_USER_GET_TASK_NAME, + KS_USER_GET_TASK_ID, + KS_USER_GET_TASK_STAT, + KS_USER_GET_TASK_COMBINEED_CORE, + KS_USER_GET_TASK_RUNNING_CORE, + KS_USER_GET_TASK_ERROR_STATUS, + KS_USER_GET_TASK_PRIORITY, + + KS_USER_MALLOC, + KS_USER_FREE, + + KS_USER_MUTEX_CREATE, + KS_USER_MUTEX_DELETE, + KS_USER_MUTEX_OBTAIN, + KS_USER_MUTEX_ABANDON, + + KS_USER_SEMAPHORE_CREATE, + KS_USER_SEMAPHORE_DELETE, + KS_USER_SEMAPHORE_OBTAIN, + KS_USER_SEMAPHORE_ABANDON, + KS_USER_SEMAPHORE_SETVALUE, + + + KS_USER_EVENT_CREATE, + KS_USER_EVENT_DELETE, + KS_USER_EVENT_TRIGGER, + KS_USER_EVENT_PROCESS, + + KS_USER_MSGQUEUE_CREATE, + KS_USER_MSGQUEUE_DELETE, + KS_USER_MSGQUEUE_SENDWAIT, + KS_USER_MSGQUEUE_SEND, + KS_USER_MSGQUEUE_URGENTSEND, + KS_USER_MSGQUEUE_RECV, + KS_USER_MSGQUEUE_REINIT, + + KS_USER_OPEN, + KS_USER_READ, + KS_USER_WRITE, + KS_USER_CLOSE, + KS_USER_IOCTL, + KS_USER_LSEEK, + KS_USER_RENAME, + KS_USER_UNLINK, + KS_USER_STAT, + KS_USER_FS_STAT, + KS_USER_FS_SYNC, + KS_USER_FTRUNCATE, + KS_USER_MKDIR, + KS_USER_OPENDIR, + KS_USER_CLOSEDIR, + KS_USER_READDIR, + KS_USER_RMDIR, + KS_USER_CHDIR, + KS_USER_GETCWD, + KS_USER_TELLDIR, + KS_USER_SEEKDIR, + KS_USER_REWIND_DIR, + KS_USER_STAT_FS, + + KS_USER_END + + }; +#define SERVICETABLE ((struct KernelService*)SERVICE_TABLE_ADDRESS) +#endif + +typedef uintptr_t (*kservice)(uint32_t knum,uintptr_t *param,uint8_t param_num); +struct KernelService +{ + const kservice fun; + const uint8_t param_num; +}; + +extern struct KernelService g_service_table[] ; + +#endif \ No newline at end of file diff --git a/Ubiquitous/XiZi/kernel/include/xs_spinlock.h b/Ubiquitous/XiZi/kernel/include/xs_spinlock.h new file mode 100644 index 0000000..636d5ea --- /dev/null +++ b/Ubiquitous/XiZi/kernel/include/xs_spinlock.h @@ -0,0 +1,107 @@ +/* +* Copyright (c) 2020 AIIT XUOS Lab +* XiUOS is licensed under Mulan PSL v2. +* You can use this software according to the terms and conditions of the Mulan PSL v2. +* You may obtain a copy of Mulan PSL v2 at: +* http://license.coscl.org.cn/MulanPSL2 +* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, +* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, +* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. +* See the Mulan PSL v2 for more details. +*/ + +/** +* @file: xs_service.h +* @brief: maroc and switch table definition of kernel switch +* @version: 1.0 +* @author: AIIT XUOS Lab +* @date: 2020/3/2 +* +*/ + +#ifndef XS_SPINLOCK_H +#define XS_SPINLOCK_H + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +#ifdef ARCH_SMP + +typedef union +{ + unsigned long slock; + struct __arch_tickets + { + unsigned short owner; + unsigned short next; + } tickets; +} HwSpinlock; + +struct SpinLock +{ + HwSpinlock lock; +}; + +struct SpinLockfileOps +{ //define spin lock + struct SpinLock node_lock; //last spin lock node struct + void (*SPinLock)(struct SpinLockfileOps *spinlock); + void (*UnlockSpinLock)(struct SpinLockfileOps *spinlock); + void (*UnlockSpinLockIrqRestore)(struct SpinLockfileOps *spinlock, x_base level); + x_base (*SpinLockIrqSave)(struct SpinLockfileOps *spinlock); +}; + +extern struct SpinLockfileOps spinlock; +extern HwSpinlock _CriticalLock; + +void InitHwSpinlock(HwSpinlock *lock); +void HwLockSpinlock(HwSpinlock *lock); +void HwUnlockSpinlock(HwSpinlock *lock); +int GetCpuId(void); + +#define HW_SPIN_LOCK_INITIALIZER(lockname) {0} +#define HW_SPIN_LOCK_UNLOCKED(lockname) (HwSpinlock) HW_SPIN_LOCK_INITIALIZER(lockname) +#define DEFINE_SPINLOCK(x) HwSpinlock x = HW_SPIN_LOCK_UNLOCKED(x) +#define DECLARE_SPINLOCK(x) + +void StartupSecondaryCpu(void); +void ExecSecondaryCpuIdleKtask(void); + +#else + +#define HwLockSpinlock(lock) *(lock) = DISABLE_INTERRUPT() +#define HwUnlockSpinlock(lock) ENABLE_INTERRUPT(*(lock)) + +#endif + + + +#ifdef ARCH_SMP +struct SpinLock; + +void InitSpinLock(struct SpinLockfileOps * spinlock); +void _SpinLock(struct SpinLockfileOps * spinlock); +void _UnlockSpinLock(struct SpinLockfileOps * spinlock); +x_base _SpinLockIrqSave(struct SpinLockfileOps * spinlock); +void _UnlockSpinLockIrqRestore(struct SpinLockfileOps * spinlock, x_base level); + +#else +#define InitSpinLock(lock) /* nothing */ +#define SpinLock(lock) CriticalAreaLock() +#define UnlockSpinLock(lock) CriticalAreaUnLock() +#define SpinLockIrqSave(lock) DISABLE_INTERRUPT() +#define UnlockSpinLockIrqRestore(lock, level) ENABLE_INTERRUPT(level) + +#endif + + + + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/Ubiquitous/XiZi/kernel/include/xs_timer.h b/Ubiquitous/XiZi/kernel/include/xs_timer.h new file mode 100644 index 0000000..88a6064 --- /dev/null +++ b/Ubiquitous/XiZi/kernel/include/xs_timer.h @@ -0,0 +1,87 @@ +/* + * Copyright (c) 2020 AIIT XUOS Lab + * XiUOS is licensed under Mulan PSL v2. + * You can use this software according to the terms and conditions of the Mulan PSL v2. + * You may obtain a copy of Mulan PSL v2 at: + * http://license.coscl.org.cn/MulanPSL2 + * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, + * EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, + * MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. + * See the Mulan PSL v2 for more details. + */ + +/** +* @file: xs_timer.h +* @brief: function declaration and structure defintion of timer +* @version: 1.0 +* @author: AIIT XUOS Lab +* @date: 2020/3/10 +* +*/ + +#ifndef XS_TIMER_H +#define XS_TIMER_H + +#include +#include +#include +#include +#include + +#define TIMER_TRIGGER_ONCE (1 << 0) +#define TIMER_TRIGGER_PERIODIC (1 << 1) + +#define TIMER_ACTIVE_FALSE (1 << 0) +#define TIMER_ACTIVE_TRUE (1 << 1) + + +struct Timer +{ + struct IdNode id_node; + char name[NAME_NUM_MAX]; + uint8 active_status; + uint8 trigger_mode; + void (*func_callback)(void *param); + void *param; + x_ticks_t origin_timeslice; + x_ticks_t deadline_timeslice; + DoubleLinklistType link; + DoubleLinklistType sortlist; + uint8 prio; + struct Work * t_work; + struct TimerDone* done; +}; +typedef struct Timer *TimerType; + +struct TimerDone +{ + void (*Init)(struct Timer *timer, + const char *name, + void (*timeout)(void *parameter), + void *parameter, + x_ticks_t time, + uint8 trigger_mode); + + x_err_t (*Delete)(TimerType timer); + x_err_t (*StartRun)(TimerType timer); + x_err_t (*QuitRun)(TimerType timer); + x_err_t (*Modify)(TimerType timer, x_ticks_t ticks); +}; + +int32 KCreateTimer(const char *name, + void (*timeout)(void *parameter), + void *parameter, + x_ticks_t time, + uint8 trigger_mode); +x_err_t KDeleteTimer(int32 timer_id); +x_err_t KTimerStartRun(int32 timer_id); +x_err_t KTimerQuitRun(int32 timer_id); +x_err_t KTimerModify(int32 timer_id, x_ticks_t ticks); +x_err_t KTimerAssignMemberRun(int32 timer_id, x_ticks_t ticks); + +TimerType KGetTimer(int32 id); +int32 KGetTimerID(TimerType timer); +x_ticks_t TimerNextTimeoutTick(void); +void CheckTimerList(void); + +#endif diff --git a/Ubiquitous/XiZi/kernel/include/xs_waitqueue.h b/Ubiquitous/XiZi/kernel/include/xs_waitqueue.h new file mode 100644 index 0000000..468cbb6 --- /dev/null +++ b/Ubiquitous/XiZi/kernel/include/xs_waitqueue.h @@ -0,0 +1,66 @@ +/* +* Copyright (c) 2020 AIIT XUOS Lab +* XiUOS is licensed under Mulan PSL v2. +* You can use this software according to the terms and conditions of the Mulan PSL v2. +* You may obtain a copy of Mulan PSL v2 at: +* http://license.coscl.org.cn/MulanPSL2 +* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, +* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, +* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. +* See the Mulan PSL v2 for more details. +*/ + +/** +* @file: xs_waitqueue.h +* @brief: function declaration and structure defintion of waitqueue +* @version: 1.0 +* @author: AIIT XUOS Lab +* @date: 2020/4/20 +* +*/ + +#ifndef XS_WAITQUEUE_H +#define XS_WAITQUEUE_H + +#include +#include +#include + +#define WQ_FLAG_CLEAN 0x00 +#define WQ_FLAG_WAKEUP 0x01 + +struct WaitQueue +{ + DoubleLinklistType block_threads_list; +}; +typedef struct WaitQueue WaitQueueType; + +struct WaitqueueNode; +typedef int (*wqueue_func_t)(struct WaitqueueNode *wait, void *key); + +struct WaitqueueNode +{ + KTaskDescriptorType polling_task; + DoubleLinklistType list; + wqueue_func_t cb; + x_ticks_t deadline_tick; + uint32 key; +}; +typedef struct WaitqueueNode WaitqueueNodeType; + +void InitWqueue(WaitQueueType *queue); +void WqueueAdd(WaitQueueType *queue, struct WaitqueueNode *node); +void WqueueRemove(struct WaitqueueNode *node); +int WqueueWait(WaitQueueType *queue, x_ticks_t tick); +void WakeupWqueue(WaitQueueType *queue, void *key); + +typedef struct +{ + void (*InitWqueue)(WaitQueueType *queue); + void (*WqueueAdd)(WaitQueueType *queue, WaitqueueNodeType *node); + void (*WqueueRemove)(WaitqueueNodeType *node); + int (*WqueueWait)(WaitQueueType *queue, x_ticks_t tick); + void (*WakeupWqueue)(WaitQueueType *queue, void *key); +} WaitQueueDoneType; + +#endif diff --git a/Ubiquitous/XiZi/kernel/include/xs_workqueue.h b/Ubiquitous/XiZi/kernel/include/xs_workqueue.h new file mode 100644 index 0000000..16a20bc --- /dev/null +++ b/Ubiquitous/XiZi/kernel/include/xs_workqueue.h @@ -0,0 +1,66 @@ +/* +* Copyright (c) 2020 AIIT XUOS Lab +* XiUOS is licensed under Mulan PSL v2. +* You can use this software according to the terms and conditions of the Mulan PSL v2. +* You may obtain a copy of Mulan PSL v2 at: +* http://license.coscl.org.cn/MulanPSL2 +* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, +* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, +* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. +* See the Mulan PSL v2 for more details. +*/ + +/** +* @file: xs_workqueue.h +* @brief: function declaration and structure defintion of workqueue +* @version: 1.0 +* @author: AIIT XUOS Lab +* @date: 2020/4/20 +* +*/ + +#ifndef XS_WORKQUEUE_H +#define XS_WORKQUEUE_H + +#include +#include +#include + +#define MAX_WORK_QUEUE 32 + +struct Work +{ + void (*cb_func)(struct Work *work, void *work_data); + void *cb_param; +}; + +typedef struct +{ + int front; + int rear; + struct Work* base; + int32 task; +}WorkqueueType; + +typedef struct +{ + WorkqueueType* p_queue; + struct Work* p_work; + int32 p_timer; +}WorkTimerParamType; + +WorkqueueType *CreateWorkQueue(const char *name, uint16 stack_size, uint8 priority); +void WorkInit(struct Work *work, void (*work_func)(struct Work *work,void *work_data), void *work_data); +x_err_t WorkSubmit(WorkqueueType* sys_workq, struct Work *work, x_ticks_t time); +x_err_t WorkSubmit_immediate(WorkqueueType* sys_workq, struct Work *work); +int WorkSysWorkQueueInit(void); + +typedef struct +{ + WorkqueueType *(*CreateWorkQueue)(const char *name, uint16 stack_size, uint8 priority); + void (*WorkInit)(struct Work *work, void (*work_func)(struct Work *work, void *work_data), void *work_data); + x_err_t (*WorkSubmit)(WorkqueueType *sys_workq, struct Work *work, x_ticks_t time); + x_err_t (*WorkSubmit_immediate)(WorkqueueType *sys_workq, struct Work *work); +} WorkQueueDoneType; + +#endif diff --git a/Ubiquitous/XiZi/kernel/kernel_service/Makefile b/Ubiquitous/XiZi/kernel/kernel_service/Makefile new file mode 100644 index 0000000..76f8162 --- /dev/null +++ b/Ubiquitous/XiZi/kernel/kernel_service/Makefile @@ -0,0 +1,4 @@ + +SRC_FILES := xs_service.c + +include $(KERNEL_ROOT)/compiler.mk \ No newline at end of file diff --git a/Ubiquitous/XiZi/kernel/kernel_service/xs_service.c b/Ubiquitous/XiZi/kernel/kernel_service/xs_service.c new file mode 100644 index 0000000..d24a1ee --- /dev/null +++ b/Ubiquitous/XiZi/kernel/kernel_service/xs_service.c @@ -0,0 +1,723 @@ + +/* +* Copyright (c) 2020 AIIT XUOS Lab +* XiUOS is licensed under Mulan PSL v2. +* You can use this software according to the terms and conditions of the Mulan PSL v2. +* You may obtain a copy of Mulan PSL v2 at: +* http://license.coscl.org.cn/MulanPSL2 +* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, +* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, +* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. +* See the Mulan PSL v2 for more details. +*/ + +/** +* @file: xs_service.c +* @brief: this file is provided for kernel switch of userapi +* @version: 1.0 +* @author: AIIT XUOS Lab +* @date: 2020/3/8 +* +*/ +#include +#include +#include +#include +#include +#include +#include +#include + +#ifdef FS_VFS +#include +#endif +#ifdef TASK_ISOLATION +#include +#endif + +#ifdef SEPARATE_COMPILE +extern long ShowTask(void); +extern void ShowMemory(void); +extern long ShowSem(void); +extern long ShowEvent(void); +extern long ShowMutex(void); +//extern long ShowGatherMem(void); +extern long ShowMsgQueue(void); +//extern long showdevice(void); +extern long ShowTimer(void); +uintptr_t KsPrintInfo(uint32_t knum,uintptr_t *param, uint8_t num ) +{ + uintptr_t arg = param[0]; + uintptr_t ret = arg; + struct TaskDescriptor *tid = NONE; + KPrintf("ecall from user mode : arg: %d\n", arg ); + switch (arg) + { + case 1: +#ifdef TOOL_SHELL + ShowTask(); +#endif + break; + case 2: + ShowMemory(); + break; + case 3: +#ifdef KERNEL_SEMAPHORE + //ShowSem(); +#endif + break; + case 4: +#ifdef KERNEL_EVENT + ShowEvent(); +#endif + break; + case 5: +#ifdef KERNEL_MUTEX + ShowMutex(); +#endif + break; + case 6: + //ShowGatherMem(); + break; + case 7: +#ifdef KERNEL_MESSAGEQUEUE + ShowMsgQueue(); +#endif + break; + case 8: + //showdevice(); + break; + case 9: +#ifdef KERNEL_SOFTTIMER + ShowTimer(); +#endif + break; + default: + KPrintf("unsurport \n"); + break; + } + return ret; +} + +uintptr_t KsTaskCreate(uint32_t knum,uintptr_t *param, uint8_t num) +{ + return (uintptr_t) UTaskCreate((char *)(param[0]), (void *)(param[1]),(void *)(param[2]),(uint32)(param[3]),(uint8)(param[4])); + +} + +uintptr_t KsStartupTask(uint32_t knum,uintptr_t *param, uint8_t num) +{ + x_err_t ret ; + int32 id = (int32)(param[0]); + ret = StartupKTask(id); + return (uintptr_t)ret; +} + +uintptr_t KsTaskDelete(uint32_t knum,uintptr_t *param, uint8_t num) +{ + x_err_t ret ; + ret = KTaskDelete((int32) (param[0])); + return (uintptr_t)ret; +} + +uintptr_t KsUserTaskSerach(uint32_t knum,uintptr_t *param, uint8_t num ) +{ + return (uintptr_t)UTaskSearch(); +} + +extern void KTaskQuit(void); +uintptr_t KsTaskQuit(uint32_t knum,uintptr_t *param, uint8_t num ) +{ + KTaskQuit(); + return 0; +} + +uintptr_t KsTaskCoreCombine(uint32_t knum,uintptr_t *param, uint8_t num ) +{ + x_err_t ret = EOK ; + int32 id; +#ifdef ARCH_SMP + if( param[0] == NONE){ + id = GetKTaskDescriptor()->id.id; + }else{ + id = (int32 )(param[0]); + } + ret = KTaskCoreCombine(id, (uint8)(param[1])); +#endif + return (uintptr_t)ret; +} + +uintptr_t KsTaskCoreUnCombine(uint32_t knum,uintptr_t *param, uint8_t num ) +{ + x_err_t ret = EOK; + int32 id; +#ifdef ARCH_SMP + KTaskDescriptorType tid; + if( param[0] == NONE){ + id = GetKTaskDescriptor()->id.id; + }else{ + id = (int32 )(param[0]); + } + ret = KTaskCoreUnCombine(id); +#endif + return (uintptr_t)ret; +} + +uintptr_t KsMdelayTask(uint32_t knum,uintptr_t *param, uint8_t num ) +{ + x_err_t ret ; + ret = MdelayKTask((int32)(param[0])); + return (uintptr_t)ret; +} + +uintptr_t KsGetTaskID(uint32_t knum,uintptr_t *param, uint8_t num ) +{ + return (uintptr_t)GetKTaskDescriptor()->id.id; +} + +uintptr_t KsGetTaskName(uint32_t knum,uintptr_t *param, uint8_t num ) +{ + KTaskDescriptorType task ; + uint8_t *buf = (uint8_t *)(param[1]); + task = GetTaskWithIdnodeInfo( (int32)(param[0])); + if ( task == NONE ) + return -ERROR; + + strncpy(buf, task->task_base_info.name, NAME_NUM_MAX); + return EOK; +} + +uintptr_t KsGetTaskStat(uint32_t knum,uintptr_t *param, uint8_t num ) +{ + KTaskDescriptorType task ; + task = GetTaskWithIdnodeInfo( (int32)(param[0])); + return (uintptr_t)task->task_dync_sched_member.stat; +} + +uintptr_t KsGetTaskCombinedCore(uint32_t knum,uintptr_t *param, uint8_t num ) +{ +#ifdef ARCH_SMP + KTaskDescriptorType task ; + task = GetTaskWithIdnodeInfo( (int32)(param[0])); + return (uintptr_t)task->task_smp_info.combined_coreid; +#else + return (uintptr_t)0; +#endif +} + +uintptr_t KsGetTaskRunningCore(uint32_t knum,uintptr_t *param, uint8_t num ) +{ +#ifdef ARCH_SMP + KTaskDescriptorType task ; + task = GetTaskWithIdnodeInfo( (int32)(param[0])); + return (uintptr_t)task->task_smp_info.runing_coreid; +#else + return (uintptr_t)0; +#endif +} + +uintptr_t KsGetTaskErrorstatus(uint32_t knum,uintptr_t *param, uint8_t num ) +{ + KTaskDescriptorType task ; + task = GetTaskWithIdnodeInfo( (int32)(param[0])); + return (uintptr_t)task->exstatus; +} + +uintptr_t KsGetTaskPriority (uint32_t knum,uintptr_t *param, uint8_t num ) +{ + KTaskDescriptorType task ; + task = GetTaskWithIdnodeInfo( (int32)(param[0])); + return (uintptr_t)task->task_dync_sched_member.cur_prio; +} + +uintptr_t KsMalloc(uint32_t knum,uintptr_t *param, uint8_t num ) +{ + uintptr_t *ret = (uintptr_t *)x_umalloc( (x_size_t)param[0]); +#ifdef MOMERY_PROTECT_ENABLE + if( mem_access.AddRegion && ret != NONE){ + struct TaskDescriptor *task; + task = GetKTaskDescriptor(); + mem_access.AddRegion(task->task_dync_sched_member.isolation, (x_ubase)ret , (x_size_t)param[0] , REGION_TYPE_HEAP ); + } +#endif + return (uintptr_t)ret; +} + +uintptr_t KsFree(uint32_t knum,uintptr_t *param, uint8_t num ) +{ + x_ufree((void *)(param[0])); +#ifdef MOMERY_PROTECT_ENABLE + if(mem_access.ClearRegion){ + struct TaskDescriptor *task; + task = GetKTaskDescriptor(); + mem_access.ClearRegion(task->task_dync_sched_member.isolation, (x_ubase)param[0]); + } +#endif + return 0; +} +#ifdef KERNEL_MUTEX +uintptr_t KsCreateMutex(uint32_t knum,uintptr_t *param, uint8_t num ) +{ + int32 ret; + ret = KMutexCreate(); + return (uintptr_t)ret; +} + +uintptr_t KsDeleteMutex(uint32_t knum,uintptr_t *param, uint8_t num ) +{ + x_err_t ret = EOK; + KMutexDelete((int32)(param[0])); + return (uintptr_t)ret; +} + +uintptr_t KsMutexObtain(uint32_t knum,uintptr_t *param, uint8_t num ) +{ + x_err_t ret ; + ret = KMutexObtain((int32)(param[0]),(int32)(param[1])); + return (uintptr_t)ret; +} + +uintptr_t KsMutexAbandon(uint32_t knum,uintptr_t *param, uint8_t num ) +{ + x_err_t ret ; + ret = KMutexAbandon((int32)(param[0])); + return (uintptr_t)ret; +} +#endif +#ifdef KERNEL_SEMAPHORE +uintptr_t KsCreateSemaphore(uint32_t knum,uintptr_t *param, uint8_t num) +{ + int32 ret; + ret = KSemaphoreCreate((uint16)param[0]); + return (uintptr_t)ret ; +} + +uintptr_t KsDeleteSemaphore(uint32_t knum,uintptr_t *param, uint8_t num ) +{ + KSemaphoreDelete((int32)(param[0])); + return 0; +} + +uintptr_t KsSemaphoreObtain(uint32_t knum,uintptr_t *param, uint8_t num ) +{ + x_err_t ret ; + ret = KSemaphoreObtain((int32)(param[0]),(int32)(param[1])); + return (uintptr_t)ret; +} + +uintptr_t KsSemaphoreAbandon(uint32_t knum,uintptr_t *param, uint8_t num ) +{ + x_err_t ret ; + ret = KSemaphoreAbandon((int32)(param[0])); + return (uintptr_t)ret; +} + +uintptr_t KsSemaphoreSetValue(uint32_t knum,uintptr_t *param, uint8_t num ) +{ + x_err_t ret ; + ret = KSemaphoreSetValue((int32)(param[0]),(uint16)(param[1])); + return (uintptr_t)ret; +} +#endif + +#ifdef KERNEL_EVENT +uintptr_t KsCreateEvent(uint32_t knum,uintptr_t *param, uint8_t num ) +{ + EventIdType ret; + ret = KEventCreate((uint8)(param[0])); + return (uintptr_t)ret; +} + +uintptr_t KsDeleteEvent(uint32_t knum,uintptr_t *param, uint8_t num ) +{ + x_err_t ret = 0; + KEventDelete((EventIdType)(param[0])); + return (uintptr_t)ret; +} + +uintptr_t KsEventTrigger(uint32_t knum,uintptr_t *param, uint8_t num ) +{ + x_err_t ret; + ret = KEventTrigger((EventIdType)(param[0]), (uint32)(param[1])); + return (uintptr_t)ret; +} + +uintptr_t KsEventProcess(uint32_t knum,uintptr_t *param, uint8_t num ) +{ + x_err_t ret; + ret = KEventProcess((EventIdType)(param[0]), (uint32)(param[1]), (uint8)(param[2]), (int32)(param[3]), (uint32 *)(param[4]) ); + return (uintptr_t)ret; +} + +#endif + +#ifdef KERNEL_MESSAGEQUEUE +uintptr_t KsCreateMsgQueue(uint32_t knum,uintptr_t *param, uint8_t num ) +{ + int32 ret; + ret = KCreateMsgQueue((int32)(param[0]), (x_size_t)(param[1]) ); + return (uintptr_t)ret; +} + +uintptr_t KsDeleteMsgQueue(uint32_t knum,uintptr_t *param, uint8_t num ) +{ + x_err_t ret; + ret = KDeleteMsgQueue((int32)(param[0]) ); + return (uintptr_t)ret; +} + +uintptr_t KsMsgQueueSendwait(uint32_t knum,uintptr_t *param, uint8_t num ) +{ + x_err_t ret; + ret = KMsgQueueSendwait((int32)(param[0]), (const void *)(param[1]), (x_size_t)(param[2]), (int32)(param[3]) ); + return (uintptr_t)ret; +} + +uintptr_t KsMsgQueueSend(uint32_t knum,uintptr_t *param, uint8_t num ) +{ + x_err_t ret; + ret = KMsgQueueSend((int32)(param[0]), (const void *)(param[1]), (x_size_t)(param[2]) ); + return (uintptr_t)ret; +} + +uintptr_t KsMsgQueueUrgentSend(uint32_t knum,uintptr_t *param, uint8_t num ) +{ + x_err_t ret; + ret = KMsgQueueUrgentSend((int32)(param[0]), (const void *)(param[1]), (x_size_t)(param[2]) ); + return (uintptr_t)ret; +} + +uintptr_t KsMsgQueueRecv(uint32_t knum,uintptr_t *param, uint8_t num ) +{ + x_err_t ret; + ret = KMsgQueueRecv((int32)(param[0]), (void *)(param[1]), (x_size_t)(param[2]), (int32)(param[3]) ); + return (uintptr_t)ret; +} + +uintptr_t KsMsgQueueReinit(uint32_t knum,uintptr_t *param, uint8_t num ) +{ + x_err_t ret; + ret = KMsgQueueReinit((int32)(param[0]) ); + return (uintptr_t)ret; +} +#endif +/* fs posix*/ + +#ifdef FS_VFS +uintptr_t KsOpen(uint32_t knum,uintptr_t *param, uint8_t num ) +{ + int ret; + ret = open((const char *)(param[0]), (int)(param[1]), (mode_t)(param[2])); + return (uintptr_t)ret; +} + +uintptr_t KsRead(uint32_t knum,uintptr_t *param, uint8_t num ) +{ + int ret; + ret = read((int)(param[0]), (void *)(param[1]), (size_t)(param[2]) ); + return (uintptr_t)ret; +} + +uintptr_t KsWrite(uint32_t knum,uintptr_t *param, uint8_t num ) +{ + int ret; + ret = write((int)(param[0]), (const void *)(param[1]), (size_t)(param[2])); + return (uintptr_t)ret; +} + +uintptr_t KsClose(uint32_t knum,uintptr_t *param, uint8_t num ) +{ + int ret; + ret = close((int)(param[0])); + return (uintptr_t)ret; +} + +uintptr_t KsIoctl(uint32_t knum,uintptr_t *param, uint8_t num ) +{ + int ret; + ret = ioctl((int)(param[0]), (int)(param[1]), (void *)(param[2])); + return (uintptr_t)ret; +} + +uintptr_t KsLseek(uint32_t knum,uintptr_t *param, uint8_t num ) +{ + off_t ret; + ret = lseek((int)(param[0]), (off_t)(param[1]), (int)(param[2]) ); + return (uintptr_t)ret; +} + +uintptr_t KsRename(uint32_t knum,uintptr_t *param, uint8_t num ) +{ + int ret; + ret = rename((const char *)(param[0]), (const char *)(param[1]) ); + return (uintptr_t)ret; +} + +uintptr_t KsUnlink(uint32_t knum,uintptr_t *param, uint8_t num ) +{ + int ret; + ret = unlink((const char *)(param[0]) ); + return (uintptr_t)ret; +} + +uintptr_t KsStat(uint32_t knum,uintptr_t *param, uint8_t num ) +{ + int ret; + ret = stat((const char *)(param[0]), (struct stat *)(param[1])); + return (uintptr_t)ret; +} + +uintptr_t KsFstat(uint32_t knum,uintptr_t *param, uint8_t num ) +{ + int ret; + ret = fstat((int)(param[0]), (struct stat *)(param[1])); + return (uintptr_t)ret; +} + +uintptr_t KsFsync(uint32_t knum,uintptr_t *param, uint8_t num ) +{ + int ret; + ret = fsync((int)(param[0])); + return (uintptr_t)ret; +} + +uintptr_t KsFtruncate(uint32_t knum,uintptr_t *param, uint8_t num ) +{ + int ret; + ret = ftruncate((int)(param[0]), (off_t)(param[1])); + return (uintptr_t)ret; +} + +uintptr_t KsMkdir(uint32_t knum,uintptr_t *param, uint8_t num ) +{ + int ret; + ret = mkdir((const char *)(param[0]), (mode_t)(param[1])); + return (uintptr_t)ret; +} + +uintptr_t KsOpendir(uint32_t knum,uintptr_t *param, uint8_t num ) +{ + DIR *ret; + ret = opendir((const char *)(param[0]) ); + return (uintptr_t)ret; +} + +uintptr_t KsClosedir(uint32_t knum,uintptr_t *param, uint8_t num ) +{ + int ret; + ret = closedir((DIR *)(param[0]) ); + return (uintptr_t)ret; +} + +uintptr_t KsReaddir(uint32_t knum,uintptr_t *param, uint8_t num ) +{ + struct dirent *ret; + ret = readdir((DIR *)(param[0])); + return (uintptr_t)ret; +} + +uintptr_t KsRmdir(uint32_t knum,uintptr_t *param, uint8_t num ) +{ + int ret; + ret = rmdir((const char *)(param[0])); + return (uintptr_t)ret; +} + +uintptr_t KsChdir(uint32_t knum,uintptr_t *param, uint8_t num ) +{ + int ret; + ret = chdir((const char *)(param[0])); + return (uintptr_t)ret; +} + +uintptr_t KsGetcwd(uint32_t knum,uintptr_t *param, uint8_t num ) +{ + char *ret; + ret = getcwd((char *)(param[0]), (size_t)(param[1])); + return (uintptr_t)ret; +} + +uintptr_t KsTelldir(uint32_t knum,uintptr_t *param, uint8_t num ) +{ + long ret = 0; + //ret = telldir((DIR *)(param[0])); + return (uintptr_t)ret; +} + +uintptr_t KsSeekdir(uint32_t knum,uintptr_t *param, uint8_t num ) +{ + seekdir((DIR *)(param[0]), (off_t)(param[1])); + return 0; +} + +uintptr_t KsRewinddir(uint32_t knum,uintptr_t *param, uint8_t num ) +{ + rewinddir((DIR *)(param[0])); + return 0; +} + +uintptr_t KsStatfs(uint32_t knum,uintptr_t *param, uint8_t num ) +{ + int ret; + ret = statfs((const char *)(param[0]), (struct statfs *)(param[1])); + return (uintptr_t)ret; +} +#endif + +struct KernelService g_service_table[256] __attribute__ ((section (".g_service_table"))) = +{ + [KS_USER_PRINT_INFO] = { KsPrintInfo, 1 }, + + /*************** Task ************/ + [KS_USER_TASK_CREATE] = { KsTaskCreate, 5 }, + [KS_USER_TASK_STARTUP] = { KsStartupTask, 1 }, + [KS_USER_TASK_DELETE] = { KsTaskDelete, 1 }, + [KS_USER_TASK_SEARCH] = { KsUserTaskSerach, 0 }, + [KS_USER_TASK_EXECEXIT] = { KsTaskQuit, 0 }, + [KS_USER_TASK_CORE_COMBINE] = { KsTaskCoreCombine, 2 }, + [KS_USER_TASK_CORE_UNCOMBINE] = { KsTaskCoreUnCombine, 1 }, + [KS_USER_TASK_DELAY] = { KsMdelayTask, 1 }, + [KS_USER_GET_TASK_NAME] = { KsGetTaskName, 2 }, + [KS_USER_GET_TASK_ID] = { KsGetTaskID, 0 }, + [KS_USER_GET_TASK_STAT] = { KsGetTaskStat, 1 }, + [KS_USER_GET_TASK_COMBINEED_CORE] = { KsGetTaskCombinedCore, 1 }, + [KS_USER_GET_TASK_RUNNING_CORE] = { KsGetTaskRunningCore, 1 }, + [KS_USER_GET_TASK_ERROR_STATUS] = { KsGetTaskErrorstatus, 1 }, + [KS_USER_GET_TASK_PRIORITY] = { KsGetTaskPriority, 1 }, + + /*************** Memory ************/ + [KS_USER_MALLOC] = { KsMalloc, 1 }, + [KS_USER_FREE] = { KsFree, 1 }, +#ifdef KERNEL_MUTEX + /*************** Mutex ************/ + [KS_USER_MUTEX_CREATE] = { KsCreateMutex, 0 }, + [KS_USER_MUTEX_DELETE] = { KsDeleteMutex, 1 }, + [KS_USER_MUTEX_OBTAIN] = { KsMutexObtain, 2 }, + [KS_USER_MUTEX_ABANDON] = { KsMutexAbandon, 1 }, +#endif +#ifdef KERNEL_SEMAPHORE + /*************** Semaphore ************/ + [KS_USER_SEMAPHORE_CREATE] = { KsCreateSemaphore, 1 }, + [KS_USER_SEMAPHORE_DELETE] = { KsDeleteSemaphore, 1 }, + [KS_USER_SEMAPHORE_OBTAIN] = { KsSemaphoreObtain, 2 }, + [KS_USER_SEMAPHORE_ABANDON] = { KsSemaphoreAbandon, 1 }, + [KS_USER_SEMAPHORE_SETVALUE] = { KsSemaphoreSetValue, 2 }, +#endif + /*************** Event ************/ +#ifdef KERNEL_EVENT + [KS_USER_EVENT_CREATE] = { KsCreateEvent, 1 }, + [KS_USER_EVENT_DELETE] = { KsDeleteEvent, 1 }, + [KS_USER_EVENT_TRIGGER] = { KsEventTrigger, 2 }, + [KS_USER_EVENT_PROCESS] = { KsEventProcess, 5 }, +#endif +#ifdef KERNEL_MESSAGEQUEUE + /*************** Msg queue ************/ + [KS_USER_MSGQUEUE_CREATE] = { KsCreateMsgQueue, 2 }, + [KS_USER_MSGQUEUE_DELETE] = { KsDeleteMsgQueue, 1 }, + [KS_USER_MSGQUEUE_SENDWAIT] = { KsMsgQueueSendwait, 4 }, + [KS_USER_MSGQUEUE_SEND] = { KsMsgQueueSend, 3 }, + [KS_USER_MSGQUEUE_URGENTSEND] = { KsMsgQueueUrgentSend, 3 }, + [KS_USER_MSGQUEUE_RECV] = { KsMsgQueueRecv, 4 }, + [KS_USER_MSGQUEUE_REINIT] = { KsMsgQueueReinit, 1 }, +#endif +#ifdef FS_VFS + /*************** fs poxix ************/ + [KS_USER_OPEN] = { KsOpen , 3 }, + [KS_USER_READ] = { KsRead , 3 }, + [KS_USER_WRITE] = { KsWrite , 3 }, + [KS_USER_CLOSE] = { KsClose , 1 }, + [KS_USER_IOCTL] = { KsIoctl , 3 }, + [KS_USER_LSEEK] = { KsLseek , 3 }, + [KS_USER_RENAME] = { KsRename , 2 }, + [KS_USER_UNLINK] = { KsUnlink , 1 }, + [KS_USER_STAT] = { KsStat , 2 }, + [KS_USER_FS_STAT] = { KsFstat , 2 }, + [KS_USER_FS_SYNC] = { KsFsync , 1 }, + [KS_USER_FTRUNCATE] = { KsFtruncate , 2 }, + [KS_USER_MKDIR] = { KsMkdir , 2 }, + [KS_USER_OPENDIR] = { KsOpendir , 1 }, + [KS_USER_CLOSEDIR] = { KsClosedir , 1 }, + [KS_USER_READDIR] = { KsReaddir , 1 }, + [KS_USER_RMDIR] = { KsRmdir , 1 }, + [KS_USER_CHDIR] = { KsChdir , 1 }, + [KS_USER_GETCWD] = { KsGetcwd, 2 }, + [KS_USER_TELLDIR] = { KsTelldir, 1 }, + [KS_USER_SEEKDIR] = { KsSeekdir, 2 }, + [KS_USER_REWIND_DIR] = { KsRewinddir, 1 }, + [KS_USER_STAT_FS] = { KsStatfs, 2 }, +#endif + [KS_USER_END ... 255] = {NONE, 0} + +}; +#else +struct utask +{ + char name[NAME_NUM_MAX]; + void *func_entry; + void *func_param; + int32_t stack_size; + uint8_t prio; +}; +typedef struct utask UtaskType; +int32_t UserTaskCreate(UtaskType utask) +{ + return KTaskCreate(utask.name, utask.func_entry, utask.func_param,utask.stack_size,utask.prio); +} + +x_err_t UserGetTaskName(int32_t id ,char *name) +{ + KTaskDescriptorType task ; + uint8_t *buf = (uint8_t *)(name); + task = GetTaskWithIdnodeInfo(id); + if ( task == NONE ) + return -ERROR; + + strncpy(buf, task->task_base_info.name, NAME_NUM_MAX); + return EOK; +} + +int32_t UserGetTaskID(void) +{ + return (uintptr_t)GetKTaskDescriptor()->id.id; +} + +uint8_t UserGetTaskStat(int32_t id) +{ + KTaskDescriptorType task ; + task = GetTaskWithIdnodeInfo(id); + return (uintptr_t)task->task_dync_sched_member.stat; +} + +#ifdef ARCH_SMP +uint8_t UserGetTaskCombinedCore(int32_t id) +{ + KTaskDescriptorType task ; + task = GetTaskWithIdnodeInfo(id); + return (uintptr_t)task->task_smp_info.combined_coreid; +} + +uint8_t UserGetTaskRunningCore(int32_t id) +{ + KTaskDescriptorType task ; + task = GetTaskWithIdnodeInfo(id); + return (uintptr_t)task->task_smp_info.runing_coreid; +} +#endif + +x_err_t UserGetTaskErrorstatus(int32_t id) +{ + KTaskDescriptorType task ; + task = GetTaskWithIdnodeInfo(id); + return (uintptr_t)task->exstatus; +} + +uint8_t UserGetTaskPriority(int32_t id) +{ + KTaskDescriptorType task ; + task = GetTaskWithIdnodeInfo(id); + return (uintptr_t)task->task_dync_sched_member.cur_prio; +} + +long occupy_g_service_table __attribute__ ((section (".g_service_table"))) = 0; + +#endif \ No newline at end of file diff --git a/Ubiquitous/XiZi/kernel/kernel_test/Kconfig b/Ubiquitous/XiZi/kernel/kernel_test/Kconfig new file mode 100644 index 0000000..7203305 --- /dev/null +++ b/Ubiquitous/XiZi/kernel/kernel_test/Kconfig @@ -0,0 +1,62 @@ +menuconfig KERNEL_TEST + bool "Enable kernel test function " + default n + + if KERNEL_TEST + config KERNEL_TEST_AVLTREE + bool "Config test avl tree" + default n + select KERNEL_AVL_TREE + config KERNEL_TEST_CRICULAR_AREA + bool "Config test Circular area" + default n + select KERNEL_CIRCULAR_AREA + config KERNEL_TEST_MEM + bool "Config test mem" + default n + select KERNEL_MEMBLOCK + config KERNEL_TEST_TIMER + bool "Config test timer" + default n + config KERNEL_TEST_IWG + bool "Config test iwg" + default n + select BSP_USING_WDT + config KERNEL_TEST_REALTIME + bool "Config test realtime" + default n + config KERNEL_TEST_DBG + bool "Config test dbg" + default n + select KERNEL_DEBUG + config KERNEL_TEST_SCHED + bool "Config test sched" + default n + config KERNEL_TEST_RTC + bool "Config test rtc" + default n + config KERNEL_TEST_SERIAL + bool "Config test serial" + default n + config KERNEL_TEST_HWTIMER + bool "Config test hwtimer" + default n + config KERNEL_TEST_CAN + bool "Config test can" + default n + config KERNEL_TEST_TOUCH + bool "Config test touch" + default n + config KERNEL_TEST_LCD + bool "Config test lcd" + default n + config KERNEL_TEST_CH438 + bool "Config test ch438" + default n + config KERNEL_TEST_I2C + bool "Config test i2c" + default n + config KERNEL_TEST_RISC_CAN + bool "Config test riscv can " + default n + endif diff --git a/Ubiquitous/XiZi/kernel/kernel_test/Makefile b/Ubiquitous/XiZi/kernel/kernel_test/Makefile new file mode 100644 index 0000000..d8d5899 --- /dev/null +++ b/Ubiquitous/XiZi/kernel/kernel_test/Makefile @@ -0,0 +1,91 @@ +SRC_FILES := test_main.c test_fpu.c + +ifeq ($(CONFIG_KERNEL_TEST_SEM),y) + SRC_FILES += test_sem.c +endif + +ifeq ($(CONFIG_KERNEL_TEST_MUTEX),y) + SRC_FILES += test_mutex.c +endif + +ifeq ($(CONFIG_KERNEL_TEST_EVENT),y) + SRC_FILES += test_event.c +endif + +ifeq ($(CONFIG_KERNEL_TEST_MSG),y) + SRC_FILES += test_mq.c +endif + +ifeq ($(CONFIG_KERNEL_TEST_AVLTREE),y) + SRC_FILES += test_avltree.c +endif + +ifeq ($(CONFIG_KERNEL_TEST_CRICULAR_AREA),y) + SRC_FILES += test_circulararea.c +endif + +ifeq ($(CONFIG_KERNEL_TEST_TOUCH),y) + SRC_FILES += test_touch.c +endif + +ifeq ($(CONFIG_KERNEL_TEST_MEM),y) + SRC_FILES += test_mem.c + SRC_FILES += test_gatherblock.c +ifeq ($(CONFIG_MEM_EXTERN_SRAM),y) + SRC_FILES += extsram_test.c +endif +endif + +ifeq ($(CONFIG_KERNEL_TEST_TIMER),y) + SRC_FILES += test_timer.c +endif + +ifeq ($(CONFIG_KERNEL_TEST_IWG),y) + SRC_FILES += test_iwg.c +endif + +ifeq ($(CONFIG_KERNEL_TEST_CAN),y) + SRC_FILES += test_can.c +endif + +ifeq ($(CONFIG_KERNEL_TEST_REALTIME),y) + SRC_FILES += test_realtime.c +endif + +ifeq ($(CONFIG_KERNEL_TEST_DBG),y) + SRC_FILES += test_dbg.c +endif + +ifeq ($(CONFIG_KERNEL_TEST_SCHED),y) + SRC_FILES += test_threadsched.c +endif + +ifeq ($(CONFIG_KERNEL_TEST_RTC),y) + SRC_FILES += test_rtc.c +endif + +ifeq ($(CONFIG_KERNEL_TEST_SERIAL),y) + SRC_FILES += test_serial.c +endif + +ifeq ($(CONFIG_KERNEL_TEST_HWTIMER),y) + SRC_FILES += test_hwtimer.c +endif + +ifeq ($(CONFIG_KERNEL_TEST_LCD),y) + SRC_FILES += test_lcd.c +endif + +ifeq ($(CONFIG_KERNEL_TEST_CH438),y) + SRC_FILES += test_ch438.c +endif + +ifeq ($(CONFIG_KERNEL_TEST_I2C),y) + SRC_FILES += test_i2c.c +endif + +ifeq ($(CONFIG_KERNEL_TEST_RISC_CAN),y) + SRC_FILES += riscv_test_can.c +endif + +include $(KERNEL_ROOT)/compiler.mk diff --git a/Ubiquitous/XiZi/kernel/kernel_test/extsram_test.c b/Ubiquitous/XiZi/kernel/kernel_test/extsram_test.c new file mode 100644 index 0000000..f1988ab --- /dev/null +++ b/Ubiquitous/XiZi/kernel/kernel_test/extsram_test.c @@ -0,0 +1,85 @@ +#include +#include + +/* parameters for sram peripheral */ +// /* stm32f4 Bank3:0X68000000 */ +// #define SRAM_BANK_ADDR ((uint32_t)0X68000000) + +/* OK-1052 semc:0X80000000 */ +#define SRAM_BANK_ADDR ((uint32_t)0X80000000) +/* data width: 8, 16, 32 */ +#define SRAM_DATA_WIDTH 16 + +// /* sram size */ +// #define SRAM_SIZE ((uint32_t)0x00100000) +/* sram size */ +#define SRAM_SIZE ((uint32_t)0x2000000) + +int sram_test(void) +{ + int i = 0; + uint32_t start_time = 0, time_cast = 0; +#if SRAM_DATA_WIDTH == 8 + char data_width = 1; + uint8_t data = 0; +#elif SRAM_DATA_WIDTH == 16 + char data_width = 2; + uint16_t data = 0; +#else + char data_width = 4; + uint32_t data = 0; +#endif + + /* write data */ + KPrintf("Writing the %ld bytes data, waiting....", SRAM_SIZE); + start_time = CurrentTicksGain(); + for (i = 0; i < SRAM_SIZE / data_width; i++) + { +#if SRAM_DATA_WIDTH == 8 + *(volatile uint8_t *)(SRAM_BANK_ADDR + i * data_width) = (uint8_t)0x55; +#elif SRAM_DATA_WIDTH == 16 + *(volatile uint16_t *)(SRAM_BANK_ADDR + i * data_width) = (uint16_t)0x5555; +#else + *(volatile uint32_t *)(SRAM_BANK_ADDR + i * data_width) = (uint32_t)0x55555555; +#endif + } + time_cast = CurrentTicksGain() - start_time; + KPrintf("Write data success, total time: %d.%03dS.\n", time_cast / TICK_PER_SECOND, + time_cast % TICK_PER_SECOND / ((TICK_PER_SECOND * 1 + 999) / 1000)); + + /* read data */ + KPrintf("start Reading and verifying data, waiting....\n"); + for (i = 0; i < SRAM_SIZE / data_width; i++) + { +#if SRAM_DATA_WIDTH == 8 + data = *(volatile uint8_t *)(SRAM_BANK_ADDR + i * data_width); + if (data != 0x55) + { + KPrintf("SRAM test failed!"); + break; + } +#elif SRAM_DATA_WIDTH == 16 + data = *(volatile uint16_t *)(SRAM_BANK_ADDR + i * data_width); + if (data != 0x5555) + { + KPrintf("SRAM test failed! data = 0x%x\n",data); + break; + } +#else + data = *(volatile uint32_t *)(SRAM_BANK_ADDR + i * data_width); + if (data != 0x55555555) + { + KPrintf("SRAM test failed!"); + break; + } +#endif + } + + if (i >= SRAM_SIZE / data_width) + { + KPrintf("SRAM test success!\n"); + } + + return 0; +} +SHELL_EXPORT_CMD(SHELL_CMD_PERMISSION(0)|SHELL_CMD_TYPE(SHELL_TYPE_CMD_FUNC)|SHELL_CMD_PARAM_NUM(0),sram_test, sram_test, sram_test ); diff --git a/Ubiquitous/XiZi/kernel/kernel_test/riscv_test_can.c b/Ubiquitous/XiZi/kernel/kernel_test/riscv_test_can.c new file mode 100644 index 0000000..8cea430 --- /dev/null +++ b/Ubiquitous/XiZi/kernel/kernel_test/riscv_test_can.c @@ -0,0 +1,127 @@ +/* +* Copyright (c) 2020 AIIT XUOS Lab +* XiUOS is licensed under Mulan PSL v2. +* You can use this software according to the terms and conditions of the Mulan PSL v2. +* You may obtain a copy of Mulan PSL v2 at: +* http://license.coscl.org.cn/MulanPSL2 +* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, +* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, +* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. +* See the Mulan PSL v2 for more details. +*/ + +/** +* @file riscv_test_can.c +* @brief support to test can function on aiit-riscv64-board +* @version 1.0 +* @author AIIT XUOS Lab +* @date 2021-04-24 +*/ + +#include + +#ifdef BOARD_AIIT_RISCV_EVB + +#include +#include +#include "board.h" +#include "connect_ch438.h" + +static struct Bus *bus; +static struct HardwareDev *dev; +static struct Driver *drv; + +static int32 Timer = NONE; + +static uint8 idx = 0; + +static void Ch438Read(void *parameter) +{ + uint8 rev_len; + uint8 ext_uart_no = 3; + static uint8 dat,i,count; + + struct BusBlockReadParam read_param; + static uint8 Ch438Buff[8][BUFFSIZE]; + + while (1) + { + read_param.buffer = Ch438Buff[3]; + rev_len = BusDevReadData(dev, &read_param); + + for(count = 0 ;count < rev_len ;count++) + { + KPrintf("%#2x ",Ch438Buff[3][count]); + KPrintf("\n"); + } + + for(i=0;i +#include +#include +#include + +static char string[] = { 1, 2, 3, 4, 5, 6, 7, 8, 9}; +static AvlNodeType g_avlnode; + +static AvlNodeType create_tree(AvlNodeType avl_node) +{ + uint32 i = 0; + uint32 string_len = strlen(string); + + for(i = 0; i < string_len; i ++) + { + KPrintf("avl_node %8p data %d\n", avl_node, string[i]); + avl_node = AvlTreeInsertNode(avl_node, string[i]); + } + + return avl_node; +} + +static AvlNodeType DeleteNode(AvlNodeType avl_node, int32 data) +{ + avl_node = AvlTreeDeleteNode(avl_node, data); + + return avl_node; +} + +static AvlNodeType DeleteTree(AvlNodeType avl_node) +{ + uint32 i = 0; + uint32 string_len = strlen(string); + + for(i = 0; i < string_len; i ++) + { + avl_node = AvlTreeDeleteNode(avl_node, string[i]); + } + + return avl_node; +} + +static AvlNodeType InsertNode(AvlNodeType avl_node, int32 data) +{ + avl_node = AvlTreeInsertNode(avl_node, data); + + return avl_node; +} + +static AvlNodeType SearchNode(AvlNodeType avl_node, int32 data) +{ + AvlNodeType dst_node; + dst_node = AvlNodeSearchNode(avl_node, data); + + return dst_node; +} + +static AvlNodeType ModyfiNode(AvlNodeType avl_node, int32 src_data, int32 dst_data) +{ + AvlNodeType dst_node; + dst_node = AvlNodeModifyNode(avl_node, src_data, dst_data); + + return dst_node; +} + +static void PrintfRootnode(void) +{ + KPrintf("g_avlnode %8p data %d left %8p data %d right %8p data %d\n", + g_avlnode, g_avlnode->data, g_avlnode->left, g_avlnode->left->data, g_avlnode->right, g_avlnode->right->data); + + KPrintf("g_avlnode left %8p data %d left %8p data %d right %8p data %d\n", + g_avlnode->left, g_avlnode->left->data, g_avlnode->left->left, g_avlnode->left->left->data, g_avlnode->left->right, g_avlnode->left->right->data); + + KPrintf("g_avlnode right %8p data %d left %8p data %d right %8p data %d\n", + g_avlnode->right, g_avlnode->right->data, g_avlnode->right->left, g_avlnode->right->left->data, g_avlnode->right->right, g_avlnode->right->right->data); +} + +static void InorderPrintftree(AvlNodeType avl_node) +{ + if(avl_node) + { + if(avl_node->left) + { + InorderPrintftree(avl_node->left); + } + + KPrintf("%d ", avl_node->data); + + if(avl_node->right) + { + InorderPrintftree(avl_node->right); + } + } + else + { + KPrintf("nil \n"); + } +} + +static uint32 TestAvltree(int argc, char *argv[]) +{ + if(0 == argc) + { + KPrintf("TestAvltree needs parameters. Just return\n"); + return EOK; + } + + if(0 == strcmp("-c", argv[1])) + { + g_avlnode = create_tree(g_avlnode); + if(NONE == g_avlnode) + { + KPrintf("TestAvltree g_avlnode create failed!\n"); + return ERROR; + } + + PrintfRootnode(); + InorderPrintftree(g_avlnode); + } + else if(0 == strcmp("-d", argv[1])) + { + if(3 == argc) + { + int32 data = atoi(argv[2]); + + g_avlnode = DeleteNode(g_avlnode, data); + + PrintfRootnode(); + InorderPrintftree(g_avlnode); + } + else if(2 == argc) + { + g_avlnode = DeleteTree(g_avlnode); + + PrintfRootnode(); + InorderPrintftree(g_avlnode); + } + } + else if(0 == strcmp("-i", argv[1])) + { + if(3 == argc) + { + int32 data = atoi(argv[2]); + + g_avlnode = InsertNode(g_avlnode, data); + + PrintfRootnode(); + InorderPrintftree(g_avlnode); + } + } + else if(0 == strcmp("-s", argv[1])) + { + if(3 == argc) + { + int32 data = atoi(argv[2]); + + AvlNodeType dst_node = SearchNode(g_avlnode, data); + + KPrintf("find data %dx%d node %8p\n", dst_node->data, data, dst_node); + PrintfRootnode(); + } + } + else if(0 == strcmp("-m", argv[1])) + { + if(4 == argc) + { + int32 src_data = atoi(argv[2]); + int32 dst_data = atoi(argv[3]); + + g_avlnode = ModyfiNode(g_avlnode, src_data, dst_data); + + PrintfRootnode(); + InorderPrintftree(g_avlnode); + } + } + + return EOK; +} +SHELL_EXPORT_CMD(SHELL_CMD_PERMISSION(0)|SHELL_CMD_TYPE(SHELL_TYPE_CMD_MAIN)|SHELL_CMD_PARAM_NUM(4), + TestAvltree, TestAvltree, Test the AVL tree Function); diff --git a/Ubiquitous/XiZi/kernel/kernel_test/test_can.c b/Ubiquitous/XiZi/kernel/kernel_test/test_can.c new file mode 100644 index 0000000..2f20ac8 --- /dev/null +++ b/Ubiquitous/XiZi/kernel/kernel_test/test_can.c @@ -0,0 +1,169 @@ +/* +* Copyright (c) 2020 AIIT XUOS Lab +* XiUOS is licensed under Mulan PSL v2. +* You can use this software according to the terms and conditions of the Mulan PSL v2. +* You may obtain a copy of Mulan PSL v2 at: +* http://license.coscl.org.cn/MulanPSL2 +* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, +* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, +* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. +* See the Mulan PSL v2 for more details. +*/ + +/** +* @file test_can.c +* @brief support to test can function +* @version 1.0 +* @author AIIT XUOS Lab +* @date 2021-04-24 +*/ + +#include "bus_can.h" +#include "dev_can.h" + + +uint8 buf[8] = {0x33,0x55,0x77,0x99,0x66,0x44,0x88,0x11}; +uint8 rx_buf[8]; +struct BusBlockWriteParam cfx = { + .pos = 0, + .buffer = buf, + .size = 8 +}; + + +uint8 rx_buf[8] = {0}; +struct BusBlockReadParam read_param = { + .pos = 0, + .buffer =rx_buf , + .read_length =0 +}; + + + static struct CanDriverConfigure can_defconfig = { + .tsjw = 0, + .tbs2 = 5 , + .tbs1 = 6, + .brp = 6, + .mode = 0 +}; + +struct BusConfigureInfo configure_info ={ + .configure_cmd = 0, + .private_data = &can_defconfig +}; + + + + static int _CanTestSend(const char *bus_name, const char *driver_name, const char *device_name0) +{ + int i; + struct Bus *bus; + struct Driver *driver, *bus_driver; + struct HardwareDev *device0, *device1; + struct HardwareDev *bus_device0; + + if(bus_name) + { + bus = BusFind(bus_name); + KPrintf("##test bus %p##\n", bus); + } + + if(driver_name) + { + driver = CanDriverFind(driver_name, TYPE_CAN_DRV); + bus_driver = BusFindDriver(bus, driver_name); + KPrintf("##test driver %p bus_driver %p##\n", driver, bus_driver); + } + + if(device_name0) + { + device0 = CanDeviceFind(device_name0, TYPE_CAN_DEV); + bus_device0 = BusFindDevice(bus, device_name0); + KPrintf("####test device0 %p bus_device0 %p####\n", device0, bus_device0); + KPrintf("####test device0 private %p\n", device0->private_data); + } + + BusDrvConfigure(bus_driver, &configure_info); + + while(1) + { + BusDevWriteData(device0, &cfx); + uint8 * buf =(uint8 *) cfx.buffer; + KPrintf("send:"); + for(i = 0;iprivate_data); + } + + BusDrvConfigure(bus_driver, &configure_info); + + while(1) + { + len = BusDevReadData(bus_device0,&read_param); + if(0 != len) + { + for(i = 0; i +#include +#include "board.h" +#include "connect_ch438.h" + +#if defined BOARD_AIIT_RISCV_EVB +#define EXT_UART_NO 2 +#elif defined BOARD_STM32F407_EVB +#define EXT_UART_NO 4 +#endif + +#define DATA_BUFF_SIZE 255 + +static struct Bus *bus; +static struct HardwareDev *dev; +static struct Driver *drv; + + +static void Ch438Read(void *parameter) +{ + uint8 RevLen; + uint8 ext_uart_no = EXT_UART_NO; + uint8 i; + uint16 vol, cur, pwr; + + struct BusBlockReadParam read_param; + static uint8 Ch438Buff[8][DATA_BUFF_SIZE]; + + while (1) + { + MdelayKTask(100); + + read_param.buffer = Ch438Buff[ext_uart_no]; + RevLen = BusDevReadData(dev, &read_param); + + vol = ((uint16)Ch438Buff[ext_uart_no][3] << 8) | Ch438Buff[ext_uart_no][4]; + cur = ((uint16)Ch438Buff[ext_uart_no][5] << 8) | Ch438Buff[ext_uart_no][6]; + pwr = ((uint16)Ch438Buff[ext_uart_no][7] << 8) | Ch438Buff[ext_uart_no][8]; + KPrintf("Board voltage : %d.%d V current : %d mA power : %d.%03d W\n", vol/10, vol%10, cur, pwr/1000, pwr%1000); + + for(i = 0 ; i < DATA_BUFF_SIZE; i ++) { + Ch438Buff[ext_uart_no][i] = 0; + } + } +} + +static void Ch438Write(void *parameter) +{ + x_err_t result; + uint8 MeterInstruction[8] = {0x01, 0x04, 0x00, 0x00, 0x00, 0x03, 0xB0, 0x0B}; + struct BusBlockWriteParam write_param; + + write_param.buffer = MeterInstruction; + write_param.size = 8; + + while (1) + { + MdelayKTask(1000); + KPrintf("\n"); + BusDevWriteData(dev, &write_param); + } +} + +static void TestCh438Init(void) +{ + x_err_t flag; + + struct BusConfigureInfo configure_info; + + bus = BusFind(CH438_BUS_NAME); + drv = BusFindDriver(bus, CH438_DRIVER_NAME); + +#if defined BOARD_AIIT_RISCV_EVB + dev = BusFindDevice(bus, CH438_DEVICE_NAME_2); +#elif defined BOARD_STM32F407_EVB + dev = BusFindDevice(bus, CH438_DEVICE_NAME_4); +#endif + + struct SerialCfgParam serial_cfg; + memset(&serial_cfg, 0, sizeof(struct SerialCfgParam)); + configure_info.configure_cmd = OPE_INT; + configure_info.private_data = (void *)&serial_cfg; + + serial_cfg.data_cfg.port_configure = PORT_CFG_INIT; + + serial_cfg.data_cfg.ext_uart_no = EXT_UART_NO; + serial_cfg.data_cfg.serial_baud_rate = 9600; + BusDrvConfigure(drv, &configure_info); + + int32 task_CH438_read = KTaskCreate("task_CH438_read", Ch438Read, NONE, 2048, 10); + flag = StartupKTask(task_CH438_read); + if (flag != EOK) { + KPrintf("StartupKTask task_CH438_read failed .\n"); + return ; + } + + int32 task_CH438_write = KTaskCreate("task_CH438_write", Ch438Write, NONE, 2048, 10); + flag = StartupKTask(task_CH438_write); + if (flag != EOK) { + KPrintf("StartupKTask task_CH438_write failed .\n"); + return ; + } +} + +void TestCh438(void) +{ + TestCh438Init(); + MdelayKTask(500); +} +SHELL_EXPORT_CMD(SHELL_CMD_PERMISSION(0)|SHELL_CMD_TYPE(SHELL_TYPE_CMD_MAIN), + TestCh438, TestCh438, TestCh438 ); diff --git a/Ubiquitous/XiZi/kernel/kernel_test/test_circulararea.c b/Ubiquitous/XiZi/kernel/kernel_test/test_circulararea.c new file mode 100644 index 0000000..b9f141c --- /dev/null +++ b/Ubiquitous/XiZi/kernel/kernel_test/test_circulararea.c @@ -0,0 +1,160 @@ +/* +* Copyright (c) 2020 AIIT XUOS Lab +* XiUOS is licensed under Mulan PSL v2. +* You can use this software according to the terms and conditions of the Mulan PSL v2. +* You may obtain a copy of Mulan PSL v2 at: +* http://license.coscl.org.cn/MulanPSL2 +* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, +* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, +* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. +* See the Mulan PSL v2 for more details. +*/ + +/** +* @file TestCirculararea.c +* @brief support to test circular area function +* @version 1.0 +* @author AIIT XUOS Lab +* @date 2021-04-24 +*/ + +#include +#include +#ifdef KERNEL_CIRCULAR_AREA + +#define READ_LENGTH 2 +#define Write_LENGTH 3 +#define CIRCULARAREA_LENGTH 8 + +static struct CircularArea *g_circular_area; +static int8 test_string[] = "Aiit-XiuOs"; + +static int32 task_caread; +static int32 task_cawrite; + +int data_lock = -1; + +static void CircularArea_ReadTsk_Entry(void *parameter) +{ + uint8 i; + uint8 read_string[8] = {0}; + uint8 read_cnt = 0; + + while(read_cnt < 30) + { + KMutexObtain(data_lock, WAITING_FOREVER); + + if(EOK == g_circular_area->CircularAreaOperations->read(g_circular_area, read_string, READ_LENGTH)){ + for(i = 0; i < READ_LENGTH; i ++){ + KPrintf("Read data i %u ch %c rdidx %u wridx %u\n", i, read_string[i], g_circular_area->readidx, g_circular_area->writeidx); + } + + #ifdef Test_Dbg + KPrintf("Read TSK writeidx %u readidx %u status %u len %u\n", + g_circular_area->writeidx, + g_circular_area->readidx, + g_circular_area->b_status, + CircularAreaGetDataLength(g_circular_area)); + #endif + } + + read_cnt++; + MdelayKTask(500); + + KMutexAbandon(data_lock); + } + + KMutexDelete(data_lock); + KTaskDelete(task_caread); + g_circular_area->CircularAreaOperations->release(g_circular_area); +} + +static void CircularAreaWriteTskEntry(void *parameter) +{ + uint8 i; + uint8 write_cnt = 0; + uint8 string_length = strlen(test_string); + static uint32 single_write_length = 0; + + while(write_cnt < 30) + { + KMutexObtain(data_lock, WAITING_FOREVER); + + uint8 write_string[CIRCULARAREA_LENGTH] = {0}; + if((write_cnt % string_length + Write_LENGTH) > string_length){ + memcpy(write_string, &test_string[write_cnt % string_length], string_length - write_cnt % string_length); + memcpy(&write_string[string_length - write_cnt % string_length], test_string, Write_LENGTH - string_length + write_cnt % string_length); + } + else{ + memcpy(write_string, &test_string[write_cnt % string_length], Write_LENGTH); + } + + if(EOK == g_circular_area->CircularAreaOperations->write(g_circular_area, write_string, Write_LENGTH, 0)) + { + for(i = 0; i < Write_LENGTH; i ++) { + KPrintf("Write data i %d ch %c rdidx %u wridx %u\n", i, write_string[i], g_circular_area->readidx, g_circular_area->writeidx); + } + write_cnt += (g_circular_area->writeidx - single_write_length + CIRCULARAREA_LENGTH) % CIRCULARAREA_LENGTH; + single_write_length = g_circular_area->writeidx; + } + + #ifdef Test_Dbg + KPrintf("Write TSK writeidx %u readidx %u status %u len %u\n", + g_circular_area->writeidx, + g_circular_area->readidx, + g_circular_area->b_status, + CircularAreaGetDataLength(g_circular_area)); + #endif + MdelayKTask(500); + + KMutexAbandon(data_lock); + } + + KTaskDelete(task_cawrite); +} + +static uint32 TestCirculararea(void) +{ + x_err_t flag; + + g_circular_area = CircularAreaInit(CIRCULARAREA_LENGTH); + if(g_circular_area){ + KPrintf("CircularAreaInit done buffer 0x%8p length %u phead 0x%8p ptail 0x%8p wridx %u rdidx %u\n", + g_circular_area->data_buffer, g_circular_area->area_length, + g_circular_area->p_head, g_circular_area->p_tail, + g_circular_area->writeidx, g_circular_area->readidx); + } + else{ + KPrintf("CircularAreaInit failed!Just return\n"); + CircularAreaRelease(g_circular_area); + return ERROR; + } + + data_lock = KMutexCreate(); + if (data_lock < 0){ + KPrintf("data_lock creat failed.\n"); + g_circular_area->CircularAreaOperations->release(g_circular_area); + return ERROR; + } + + task_caread = KTaskCreate("task_caread", CircularArea_ReadTsk_Entry, NONE, 2048, 10); + flag = StartupKTask(task_caread); + if (EOK != flag){ + KPrintf("CircularArea_Test StartupKTask task_caread failed!\n"); + g_circular_area->CircularAreaOperations->release(g_circular_area); + return ERROR; + } + + task_cawrite = KTaskCreate("task_cawrite", CircularAreaWriteTskEntry, NONE, 2048, 10); + flag = StartupKTask(task_cawrite); + if (EOK != flag){ + KPrintf("CircularArea_Test StartupKTask task_cawrite failed!\n"); + g_circular_area->CircularAreaOperations->release(g_circular_area); + return ERROR; + } + + return EOK; +} +SHELL_EXPORT_CMD(SHELL_CMD_PERMISSION(0)|SHELL_CMD_TYPE(SHELL_TYPE_CMD_FUNC)|SHELL_CMD_PARAM_NUM(0), + TestCirculararea, TestCirculararea, Test the Circular Area Function); +#endif \ No newline at end of file diff --git a/Ubiquitous/XiZi/kernel/kernel_test/test_dbg.c b/Ubiquitous/XiZi/kernel/kernel_test/test_dbg.c new file mode 100644 index 0000000..6624094 --- /dev/null +++ b/Ubiquitous/XiZi/kernel/kernel_test/test_dbg.c @@ -0,0 +1,40 @@ +/* +* Copyright (c) 2020 AIIT XUOS Lab +* XiUOS is licensed under Mulan PSL v2. +* You can use this software according to the terms and conditions of the Mulan PSL v2. +* You may obtain a copy of Mulan PSL v2 at: +* http://license.coscl.org.cn/MulanPSL2 +* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, +* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, +* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. +* See the Mulan PSL v2 for more details. +*/ + +/** +* @file TestDbg.c +* @brief support to test dbg function +* @version 1.0 +* @author AIIT XUOS Lab +* @date 2021-04-24 +*/ + +#include + +#define KDBG_TEST1 1 +#define KDBG_TEST2 0 + +static uint32 TestDbg(void) +{ + x_err_t flag; + + SYS_WARN("TestDbg function 1!\n"); + SYS_ERR("TestDbg function 2!\n"); + DBG("TestDbg function 3!\n"); + + SYS_KDEBUG_LOG(KDBG_TEST1, ("TestDbg kernel function 1!\n")); + SYS_KDEBUG_LOG(KDBG_TEST2, ("TestDbg kernel function 2!\n")); + + return EOK; +} +SHELL_EXPORT_CMD(SHELL_CMD_PERMISSION(0)|SHELL_CMD_TYPE(SHELL_TYPE_CMD_FUNC)|SHELL_CMD_PARAM_NUM(0), + TestDbg, TestDbg, Test the log debug Function); diff --git a/Ubiquitous/XiZi/kernel/kernel_test/test_fpu.c b/Ubiquitous/XiZi/kernel/kernel_test/test_fpu.c new file mode 100644 index 0000000..450a867 --- /dev/null +++ b/Ubiquitous/XiZi/kernel/kernel_test/test_fpu.c @@ -0,0 +1,35 @@ +/* +* Copyright (c) 2020 AIIT XUOS Lab +* XiUOS is licensed under Mulan PSL v2. +* You can use this software according to the terms and conditions of the Mulan PSL v2. +* You may obtain a copy of Mulan PSL v2 at: +* http://license.coscl.org.cn/MulanPSL2 +* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, +* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, +* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. +* See the Mulan PSL v2 for more details. +*/ + +/** +* @file test_fpu.c +* @brief support to test touch function +* @version 1.0 +* @author AIIT XUOS Lab +* @date 2022-01-11 +*/ +#include +void FpuTest(void) +{ + float i = 8.25; + KPrintf("float i = 8.25 ['i %s 8' && 'i %s 9']\n",i > 8 ? ">" : "<",i < 9 ? "<" : ">"); + float add = i + 5.1; + KPrintf("float add(13.35) = i + 5.1 ['add %s 13' && 'add %s 14']\n",add > 13 ? ">" : "<",add < 14 ? "<" : ">"); + float sub = i - 5.1; + KPrintf("float sub(3.15) = i - 5.1 ['sub %s 3' && 'sub %s 4']\n",sub > 3 ? ">" : "<",sub < 4 ? "<" : ">"); + float mul = i * 5.1; + KPrintf("float mul(42.075) = i * 5.1 ['mul %s 42' && 'mul %s 43']\n",mul > 42 ? ">" : "<",mul < 43 ? "<" : ">"); + float div = i / 5.1; + KPrintf("float div(1.617) = i / 5.1 ['div %s 1' && 'div %s 2']\n",div > 1 ? ">" : "<",div < 2 ? "<" : ">"); +} + +SHELL_EXPORT_CMD(SHELL_CMD_PERMISSION(0)|SHELL_CMD_TYPE(SHELL_TYPE_CMD_FUNC)|SHELL_CMD_PARAM_NUM(0),FpuTest, FpuTest, Close AC task ); \ No newline at end of file diff --git a/Ubiquitous/XiZi/kernel/kernel_test/test_gatherblock.c b/Ubiquitous/XiZi/kernel/kernel_test/test_gatherblock.c new file mode 100644 index 0000000..9fcee94 --- /dev/null +++ b/Ubiquitous/XiZi/kernel/kernel_test/test_gatherblock.c @@ -0,0 +1,570 @@ +/* +* Copyright (c) 2020 AIIT XUOS Lab +* XiUOS is licensed under Mulan PSL v2. +* You can use this software according to the terms and conditions of the Mulan PSL v2. +* You may obtain a copy of Mulan PSL v2 at: +* http://license.coscl.org.cn/MulanPSL2 +* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, +* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, +* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. +* See the Mulan PSL v2 for more details. +*/ + +/** +* @file test_gatherblock.c +* @brief support to test gather block function +* @version 1.0 +* @author AIIT XUOS Lab +* @date 2021-04-24 +*/ + +#include +#include + +extern long ShowGatherMem(void); +extern void ShowMemory(void); +extern void ShowBuddy(void); +/**************************single gatherblock test sample***********************************/ +static uint8 *ptr[30]; +static uint8 mempool[2048]; +static struct MemGather gm; +static GatherMemType gm_d; + +#define TASK_PRIORITY 25 +#define TASK_STACK_SIZE 2048 +#define TASK_TIMESLICE 5 + +/* thread control pointer */ +static int32 tid1; +static int32 tid2; + +/* task1 entry */ +static void Task1GmAlloc(void *parameter) +{ + int i; + for (i = 0 ; i < 30 ; i++){ + if (ptr[i] == NONE){ + /* alloc memory blocks for 50 times, if failed, suspend task1 and start task2 */ + if (0 == strncmp("static", parameter, strlen("static"))){ + ptr[i] = AllocBlockMemGather(&gm, WAITING_FOREVER); + if (ptr[i] != NONE) + KPrintf("task1: allocate No.%d from static gatherblock\n", i); + } + else{ + ptr[i] = AllocBlockMemGather(gm_d, WAITING_FOREVER); + if (ptr[i] != NONE) + KPrintf("task1: allocate No.%d from dynamic gatherblock\n", i); + } + } + } +} + + +/* task2 entry, its priority is lower than task1 */ +static void Task2GmRelease(void *parameter) +{ + int i; + KPrintf("task2 try to release block\n"); + for (i = 0; i < 30 ; i++){ + DelayKTask(10); + + /* release all memory blocks */ + if (ptr[i] != NONE){ + KPrintf("release block %d\n", i); + FreeBlockMemGather(ptr[i]); + ptr[i] = NONE; + } + } + if (0 == strncmp("static", parameter, strlen("static"))) { + KPrintf("**************** detach gatherblock test *****************\n"); + RemoveMemGather(&gm); + } else { + KPrintf("**************** delete gatherblock test *****************\n"); + DeleteMemGather(gm_d); + } +} + + +int SingleGatherblockTest(char * parameter) +{ + int i; + for (i = 0; i < 30; i ++) ptr[i] = NONE; + /* init memory blocks object */ + if(0 == strncmp("static", parameter, strlen("static"))){ + KPrintf("test static create gatherblock.\n"); + InitMemGather(&gm, "mp_s", &mempool[0], sizeof(mempool), 80); + ShowGatherMem(); + } + + if(0 == strncmp("dynamic", parameter, strlen("dynamic"))){ + KPrintf("test dynamic create gatherblock.\n"); + //FreeBlockMemGather(&mp, "mp1", &mempool[0], sizeof(mempool), 80); + gm_d = CreateMemGather("mp_d",20,80); + if(gm_d == NONE){ + KPrintf("%s: allocate failure.\n",__func__); + return -1; + } + + ShowGatherMem(); + } + /* create task1, alloc memory blocks */ + tid1 = KTaskCreate("task1", Task1GmAlloc, parameter, + TASK_STACK_SIZE, + TASK_PRIORITY); + if (tid1 >= 0){ + KPrintf("single test: task1 startup.\n"); + StartupKTask(tid1); + } + + /* create task2, release memory blocks */ + tid2 = KTaskCreate("task2", Task2GmRelease, parameter, + TASK_STACK_SIZE, + TASK_PRIORITY + 1); + if (tid2 >= 0){ + StartupKTask(tid2); + } + else{ + KPrintf("create task2 for release failure.\n"); + } + + return 0; +} +/**************************************************************************************/ + + +/**********************mutiple gatherblock test sample**************************************/ +struct MemGather s_gm1; +struct MemGather *d_gm1 = NONE; + +static uint8 mempool_gm1[1024]; + +#define MAX_SIZE 11 +#define TASK_PRIORITY 25 +#define TASK_STACK_SIZE 2048 +#define TASK_TIMESLICE 5 + +/* thread control pointer */ +static int32 m_tid1 = NONE; +static int32 m_tid2 = NONE; + +static uint8 *multiple_s_ptr[20]; +static uint8 *multiple_d_ptr[20]; + +void Task1AllocEntry(void *parameter){ + int index = 0; + for(int i=0;i<20;i++){ + + multiple_s_ptr[i] = AllocBlockMemGather(&s_gm1, WAITING_FOREVER); + if(multiple_s_ptr[i] != NONE){ + KPrintf("task1: allocate No.%d from static\n", i); + } + multiple_d_ptr[i] = AllocBlockMemGather(d_gm1, WAITING_FOREVER); + + if (ptr[i] != NONE) + KPrintf("task1: allocate No.%d from dynamic\n", i); + } +} + +void Task2FreeEntry(void *parameter){ + DelayKTask(100); + for(int i=0;i<20;i++){ + + DelayKTask(10); + if(multiple_s_ptr[i]){ + FreeBlockMemGather(multiple_s_ptr[i]); + KPrintf("task2: free No.%d of static\n", i); + } + DelayKTask(10); + if(multiple_d_ptr[i]){ + FreeBlockMemGather(multiple_d_ptr[i]); + + KPrintf("task2: free No.%d of dynamic\n", i); + } + } + KPrintf("**************** detach gatherblock test *****************\n"); + RemoveMemGather(&s_gm1); + KPrintf("**************** delete gatherblock test *****************\n"); + DeleteMemGather(d_gm1); +} + +int MultipleGatherblockTest(void) +{ + + KPrintf("****************mutiple gatherblock test start*****************\n"); + + for(int i=0;i<20;i++){ + multiple_s_ptr[i] = NONE; + multiple_d_ptr[i] = NONE; + } + + InitMemGather(&s_gm1, "m_gm_s1", &mempool_gm1[0], sizeof(mempool_gm1), 80); + + d_gm1 = CreateMemGather("m_gm_d1", MAX_SIZE, 80); + if (mempool_gm1 == NONE){ + KPrintf("create m_gm_d2 failed."); + CHECK(0); + } + ShowGatherMem(); + + /* create task1, alloc memory blocks */ + m_tid1 = KTaskCreate("task1_m", Task1AllocEntry, NONE, + TASK_STACK_SIZE, + TASK_PRIORITY); + if (m_tid1 >= 0){ + StartupKTask(m_tid1); + } + + /* create task2, release memory blocks */ + m_tid2 = KTaskCreate("task2_m", Task2FreeEntry, NONE, + TASK_STACK_SIZE, + TASK_PRIORITY + 1); + if (m_tid2 >= 0){ + StartupKTask(m_tid2); + } + else{ + KPrintf("create task2 for release failure.\n"); + } + + return 0; +} +/**************************************************************************************/ + +/* thread control pointer */ +static int32 l_tid1 = NONE; +static int32 l_tid2 = NONE; +struct MemGather *gm_l = NONE; +void *l_ptr[50]; + +void LTask1AllocEntry(void *parameter){ + int index = 0; + for(int i=0;i<50;i++){ + l_ptr[i] = AllocBlockMemGather(gm_l, WAITING_FOREVER); + if(l_ptr[i] != NONE){ + KPrintf("l_task1: allocate No.%d\n", i); + } + } +} + +void LTask2FreeEntry(void *parameter){ + DelayKTask(100); + for(int i=0;i<50;i++){ + DelayKTask(10); + if(l_ptr[i]){ + FreeBlockMemGather(l_ptr[i]); + KPrintf("l_task2: free No.%d\n", i); + } + } + KPrintf("**************** delete gatherblock test *****************\n"); + DeleteMemGather(gm_l); +} + + +void GatherblockLimitTest(char *name, int count, int blocksize){ + gm_l = CreateMemGather(name, count, blocksize); + if(gm_l == NONE){ + KPrintf("no memory.\n"); + return; + } + ShowBuddy(); + /* create task1, alloc memory blocks */ + l_tid1 = KTaskCreate("task1_l", LTask1AllocEntry, NONE, + TASK_STACK_SIZE, + TASK_PRIORITY); + if (l_tid1 >= 0){ + StartupKTask(l_tid1); + } + + /* create task2, release memory blocks */ + l_tid2 = KTaskCreate("task2_l", LTask2FreeEntry, NONE, + TASK_STACK_SIZE, + TASK_PRIORITY + 1); + if (l_tid2 >= 0){ + StartupKTask(l_tid2); + } +} + +#ifdef ARCH_ARM +#define CACHE_COUNT 1024 +#else +#define CACHE_COUNT 8000 +#endif + +struct MemGather *pools[CACHE_COUNT]; +void GatherblockLimitcountTest(char *name, int count, int blocksize, int poolcount){ + if(poolcount>CACHE_COUNT || poolcount<=0){ + KPrintf("type the poolcount between 0-%d\n",CACHE_COUNT); + return; + } + int index; + for(index=0;index < poolcount;index++){ + pools[index] = CreateMemGather(name, count, blocksize); + if(pools[index] == NONE){ + KPrintf("gatherblock allocation failure,count[%d],size[%d]\n", count, blocksize); + break; + } + KPrintf("gatherblock allocation,count[%d],size[%d]\n", count, blocksize); + } + ShowBuddy(); + + index--; + for(;index>=0;index--){ + DeleteMemGather(pools[index]); + } +} + + +/*****************************************************************/ +static int32 traverse_tid = NONE; +static struct MemGather *traverse_gm = NONE; + +void TraverseGmEntry(void *parameter){ + int count,size; + int limit_count, limit_size; + + for(count =1; count <= 30; count++){ + for(size = 1; ;size++){ + traverse_gm = CreateMemGather("hello",count,size); + if( traverse_gm == NONE ){ + KPrintf("gatherblock allocation failure,count[%d],size[%d]\n", count, size); + + if(count == 1) + limit_size = size; + break; + }else{ + DeleteMemGather(traverse_gm); + } + } + if(size ==1){ + limit_count = count; + break; + } + } + KPrintf("\n\n--------------------------- bound -----------------------------\n\n"); + KPrintf("\n\n--------------------------- over end -----------------------------\n\n"); +} + +#define TRAVERSE_TASK_PRIORITY 5 +void TraverseGmTest(){ + + traverse_tid = KTaskCreate("traverse_task", TraverseGmEntry, NONE, + TASK_STACK_SIZE , + TRAVERSE_TASK_PRIORITY); + if(traverse_tid >= 0){ + StartupKTask(traverse_tid); + }else{ + KPrintf("Fail.\n"); + } +} +/********************************************************************/ +/***************************test random read and write **************/ +static uint8 *random_ptr[50]; +static struct MemGather random_static_gm; +static GatherMemType random_dynamic_gm; +static uint8 dynamic_mempool[2048]; + +/* thread control pointer */ +static int32 random_tid1 = NONE; +static int32 random_tid2 = NONE; +/* task1 entry */ +int time_seed = 1; +char temp_parameter[40]; + +static void RandomTask1GmAlloc(void *parameter) +{ + int i; + int total=0; + time_seed++; + srand(time_seed); + char string[10]; + + while(total<40){ + i = rand()%40; + if (random_ptr[i] == NONE){ + /* alloc memory blocks for 50 times, if failed, suspend task1 and start task2 */ + if (0 == strncmp("static", temp_parameter, strlen("static"))){ + random_ptr[i] = AllocBlockMemGather(&random_static_gm, WAITING_FOREVER); + if (random_ptr[i] != NONE){ + itoa(i,string,10); + memcpy(random_ptr[i],string,sizeof(string)); + KPrintf("%s No.%d: %s\n",temp_parameter, i, random_ptr[i]); + } + }else{ + random_ptr[i] = AllocBlockMemGather(random_dynamic_gm, WAITING_FOREVER); + if (random_ptr[i] != NONE){ + itoa(i,string,10); + memcpy(random_ptr[i],string,sizeof(string)); + KPrintf("%s No.%d: %s\n", temp_parameter, i, random_ptr[i]); + } + } + total++; + } + } +} + + +/* task2 entry, its priority is lower than task1 */ +static void RandomTask2GmRelease(void *parameter) +{ + int i; + time_seed++; + srand(time_seed); + + + int total = 0; + + while(total<40){ + i = rand()%40; + + /* release all memory blocks */ + if (random_ptr[i] != NONE){ + DelayKTask(10); + KPrintf("release block %d: %s\n",i, random_ptr[i]); + FreeBlockMemGather(random_ptr[i]); + random_ptr[i] = NONE; + total++; + } + } + if (0 == strncmp("static", temp_parameter, strlen("static"))) { + KPrintf("**************** detach gatherblock test *****************\n"); + RemoveMemGather(&random_static_gm); + } else { + KPrintf("**************** delete gatherblock test *****************\n"); + DeleteMemGather(random_dynamic_gm); + } +} + + +int RandomAllocFreeTest(void *parameter) +{ + int i; + for (i = 0; i < 40; i ++) random_ptr[i] = NONE; + memcpy(temp_parameter,parameter, 10); + /* init memory block object */ + if(0 == strncmp("static", parameter, strlen("static"))){ + KPrintf("test static create gatherblock-%s.\n",parameter); + InitMemGather(&random_static_gm, "ran_mp_s", &dynamic_mempool[0], sizeof(dynamic_mempool), 80); + ShowGatherMem(); + }else{ + KPrintf("test dynamic create gatherblock.\n"); + random_dynamic_gm = CreateMemGather("ran_mp_d",40,80); + if(random_dynamic_gm == NONE){ + KPrintf("%s: allocate failure.\n",__func__); + return -1; + } + ShowGatherMem(); + } + /* create task1, alloc memory blocks */ + random_tid1 = KTaskCreate("r_task1", RandomTask1GmAlloc, parameter, + TASK_STACK_SIZE, + TASK_PRIORITY); + if (random_tid1 >= 0){ + StartupKTask(random_tid1); + } + + /* create task2, release memory blocks */ + random_tid2 = KTaskCreate("r_task2", RandomTask2GmRelease, parameter, + TASK_STACK_SIZE, + TASK_PRIORITY + 1); + if (random_tid2 >= 0){ + StartupKTask(random_tid2); + } + else{ + KPrintf("create task2 for release failure.\n"); + } + + return 0; +} + + +/********************************************************************/ +void TestGatherblockUsage(void) +{ + KPrintf("TestGatherblockUsage.\n"); + KPrintf("test_main gm -a --static, dynamic and multiple test.\n"); + KPrintf("test_main gm -s static/dynamic --test static create gatherblock to allocate and free.\n"); + KPrintf("test_main gm -m --test multiple gatherblock to allocate and free.\n"); + KPrintf("test_main gm count_size [count] [size] --create a gatherblock with typed count and size " + "to allocate and free.\n"); + KPrintf("test_main gm multiple_gms [count] [size] [gm_ns] --create multiple gatherblocks with typed count and \n"); + KPrintf(" size to allocate and free.\n"); + KPrintf("test_main gm traverse --traverse.\n"); + KPrintf("test_main gm -r static/dynamic --random allocate and free.\n"); + +} + +int TestGatherblock(char *argv[]) +{ + int ret = 0; + + if (NONE == argv || 0 == strncmp("-h", argv[0], strlen("-h")) || 0 == strncmp("usage", argv[0], strlen("usage"))) { + TestGatherblockUsage(); + return -EINVALED; + } + /**************** gatherblock auto test ******************/ + if (0 == strncmp("-a", argv[0], strlen("-a"))) { + ret = SingleGatherblockTest("static"); ///< static creat single gatherblock test + MdelayKTask(7000); + ret |= SingleGatherblockTest("dynamic"); ///< dynamic creat single gatherblock test + MdelayKTask(7000); + ret |= MultipleGatherblockTest(); + MdelayKTask(7000); + ret |= RandomAllocFreeTest("static"); + MdelayKTask(7000); + ret |= RandomAllocFreeTest("dynamic"); + goto out; + } + + /**************** single gatherblock test ****************/ + if (0 == strncmp("-s",argv[0],strlen("-s")) ) { + if (0 == strncmp("static",argv[1],strlen("static"))) { + ret = SingleGatherblockTest("static"); ///< static creat single gatherblock test + } else { + ret = SingleGatherblockTest("dynamic"); ///< dynamic creat single gatherblock test + } + goto out; + } + + /**************** mutiple gatherblock test ****************/ + if (0 == strncmp("-m",argv[0],strlen("-m")) ) { + ret = MultipleGatherblockTest(); + goto out; + } + /******************** limitation test **********************/ + if (0 == strncmp("count_size",argv[0],strlen("count_size")) ) { + int size = atoi(argv[2]); + int count = atoi(argv[1]); + GatherblockLimitTest("xsos",count,size); + ret = 1; + goto out; + } + + /******************** limitation test **********************/ + if (0 == strncmp("multiple_gms",argv[0],strlen("multiple_gms")) ) { + int size = atoi(argv[2]); + int count = atoi(argv[1]); + int poolnumber = atoi(argv[3]); + GatherblockLimitcountTest("xsos",count,size,poolnumber); + ret = 1; + goto out; + } + + /********************** traverse test **********************/ + if (0 == strncmp("traverse",argv[0],strlen("traverse")) ) { + TraverseGmTest(); + goto out; + } + + /**************** random alloc and free test ****************/ + if (0 == strncmp("-r",argv[0],strlen("-r")) ) { + ret = RandomAllocFreeTest(argv[1]); + goto out; + } + +out: + if (ret < 0) { + KPrintf("test gatherblock failed ret = %d.\n",ret); + return -ERROR; + } + return 0; +} + diff --git a/Ubiquitous/XiZi/kernel/kernel_test/test_hwtimer.c b/Ubiquitous/XiZi/kernel/kernel_test/test_hwtimer.c new file mode 100644 index 0000000..d9ec0e7 --- /dev/null +++ b/Ubiquitous/XiZi/kernel/kernel_test/test_hwtimer.c @@ -0,0 +1,74 @@ +/* +* Copyright (c) 2020 AIIT XUOS Lab +* XiUOS is licensed under Mulan PSL v2. +* You can use this software according to the terms and conditions of the Mulan PSL v2. +* You may obtain a copy of Mulan PSL v2 at: +* http://license.coscl.org.cn/MulanPSL2 +* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, +* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, +* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. +* See the Mulan PSL v2 for more details. +*/ + +/** +* @file test_hwtimer.c +* @brief support to test hwtimer function +* @version 1.0 +* @author AIIT XUOS Lab +* @date 2021-04-24 +*/ + +#include +#include +#include +#include + +#if defined (ARCH_ARM) +#define HWTIMER_BUS_NAME HWTIMER_BUS_NAME_2 +#define HWTIMER_DEVICE_NAME HWTIMER_2_DEVICE_NAME_2 +#elif defined (ARCH_RISCV) +#define HWTIMER_BUS_NAME HWTIMER_BUS_NAME_1 +#define HWTIMER_DEVICE_NAME HWTIMER_1_DEVICE_NAME_1 +#elif +#define HWTIMER_BUS_NAME +#define HWTIMER_DEVICE_NAME +#endif + +void TimeoutCb(void* param){ + KPrintf("resource_sample callback come ... \n"); +} + + + + + void HwtimerSample(void)//int argc, char *argv[] +{ + struct Bus * hwtimer_bus = BusFind(HWTIMER_BUS_NAME); + if (NULL == hwtimer_bus){ + KPrintf("hwtimer bus find failed !\n"); + return ; + } + + struct HardwareDev* dev = BusFindDevice(hwtimer_bus, HWTIMER_DEVICE_NAME); + struct HwtimerHardwareDevice* hwtimer_dev = (struct HwtimerHardwareDevice*)dev; + if (NULL == hwtimer_dev){ + KPrintf("hwtimer hwtimer_dev find failed !\n"); + return ; + } + + hwtimer_dev->hwtimer_param.repeat = 1; + hwtimer_dev->hwtimer_param.period_millisecond = 3000; + hwtimer_dev->hwtimer_param.cb_info.param = NULL; + hwtimer_dev->hwtimer_param.cb_info.timeout_callback = timeout_callback; + + BusDevOpen(dev); + + MdelayKTask(20000); + + KPrintf("close hwtimer...\n"); + BusDevClose(dev); + +} +/* export to shell cmd */ +SHELL_EXPORT_CMD(SHELL_CMD_PERMISSION(0)|SHELL_CMD_DISABLE_RETURN|SHELL_CMD_TYPE(SHELL_TYPE_CMD_MAIN), + HwtimerSample, HwtimerSample, HwtimerSample ); diff --git a/Ubiquitous/XiZi/kernel/kernel_test/test_i2c.c b/Ubiquitous/XiZi/kernel/kernel_test/test_i2c.c new file mode 100644 index 0000000..cd41074 --- /dev/null +++ b/Ubiquitous/XiZi/kernel/kernel_test/test_i2c.c @@ -0,0 +1,178 @@ +/* +* Copyright (c) 2020 AIIT XUOS Lab +* XiUOS is licensed under Mulan PSL v2. +* You can use this software according to the terms and conditions of the Mulan PSL v2. +* You may obtain a copy of Mulan PSL v2 at: +* http://license.coscl.org.cn/MulanPSL2 +* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, +* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, +* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. +* See the Mulan PSL v2 for more details. +*/ + +/** +* @file test_i2c.c +* @brief support to test i2c function +* @version 1.0 +* @author AIIT XUOS Lab +* @date 2021-04-24 +*/ + +#include +#include +#include + +/*********************************************************************************************************************************************************/ +/* + * function：I2C device sample support reading temperature and humidity sensor data and printfing on the terminal + * shell cmd：i2c_HS3000_sample i2c1 + * shell cmd param：i2c device name,if null means default i2c device name +*/ + +#define HS_I2C_BUS_NAME I2C_BUS_NAME_1 /* I2C bus name */ +#define HS_I2C_DEV_NAME I2C_1_DEVICE_NAME_0/* I2C device name */ +#define HS_I2C_DRV_NAME I2C_DRV_NAME_1 /* I2C driver name */ +#define ADDR 0x44 /* slave address */ + +static struct Bus *i2c_bus = NONE; /* I2C bus handle */ + +typedef struct Hs300xData +{ + int humi_high; + int humi_low; + int temp_high; + int temp_low; +}Hs300xDataType; + +Hs300xDataType g_hs300x_data; + +static x_err_t WriteReg(struct HardwareDev *dev) +{ + struct BusBlockWriteParam write_param; + + /* use I2C device API transfer data */ + if(1 == BusDevWriteData(dev, &write_param)) { + return EOK; + } + else{ + return -ERROR; + } +} + +/* read sensor register data */ +static x_err_t ReadRegs(struct HardwareDev *dev, uint8 len, uint8 *buf) +{ + struct BusBlockReadParam read_param; + + read_param.buffer = (void *)buf; + read_param.size = len; + + /* use I2C device API transfer data */ + if(1 == BusDevReadData(dev, &read_param)){ + return EOK; + } + else{ + return -ERROR; + } +} + +static void ReadTempHumi(float *cur_temp, float *cur_humi) +{ + uint8 temp[4],ret=0; + MdelayKTask(15); + ret = WriteReg(i2c_bus->owner_haldev); //reset + if(EOK != ret){ + KPrintf("ReadTempHumi WriteReg failed!\n"); + } + MdelayKTask(50); + ret = ReadRegs(i2c_bus->owner_haldev, 4, temp); /* get sensor data */ + if(EOK != ret){ + KPrintf("ReadTempHumi ReadRegs failed\n"); + } + + *cur_humi = ((temp[0] <<8 | temp[1] )& 0x3fff ) * 100.0 / ( (1 << 14) - 1); /* humidity data */ + + *cur_temp = ((temp[2] << 8 | temp[3]) >> 2) * 165.0 /( (1 << 14) - 1) - 40.0; /* temperature data */ +} + +static void HS3000Init(const char *bus_name, const char *dev_name, const char *drv_name) +{ + /* find I2C device and get I2C handle */ + i2c_bus = BusFind(bus_name); + if (NONE == i2c_bus){ + KPrintf("HS3000Init can't find %s bus!\n", bus_name); + } + else{ + KPrintf("HS3000Init find %s bus!\n", bus_name); + } + + i2c_bus->owner_haldev = BusFindDevice(i2c_bus, dev_name); + i2c_bus->owner_driver = BusFindDriver(i2c_bus, drv_name); + + if(i2c_bus->match(i2c_bus->owner_driver, i2c_bus->owner_haldev)){ + KPrintf("i2c match drv %s %p dev %s %p error\n", drv_name, i2c_bus->owner_driver, dev_name, i2c_bus->owner_haldev); + } + else{ + KPrintf("HS3000Init successfully!write %p read %p\n", + i2c_bus->owner_haldev->dev_done->write, + i2c_bus->owner_haldev->dev_done->read); + } +} + +void Hs300xInit(void) +{ + HS3000Init(HS_I2C_BUS_NAME, HS_I2C_DEV_NAME, HS_I2C_DRV_NAME); /* init sensor */ +} + +void Hs300xRead(Hs300xDataType *Hs300xDataType) +{ + float humidity = 0.0, temperature = 0.0; + ReadTempHumi(&temperature, &humidity); /* read temperature and humidity sensor data */ + Hs300xDataType->humi_high = (int)humidity; + Hs300xDataType->humi_low = (int)(humidity*10)%10; + if( temperature >= 0 ) { + Hs300xDataType->temp_high = (int)temperature; + Hs300xDataType->temp_low = (int)(temperature*10)%10; + } + else{ + Hs300xDataType->temp_high = (int)temperature; + Hs300xDataType->temp_low = (int)(-temperature*10)%10; + } +} + +void TskHs300xTest() +{ + memset(&g_hs300x_data, 0, sizeof(Hs300xDataType)); + KPrintf("Tsk create successfully!\n"); + + while(1) + { + Hs300xRead(&g_hs300x_data); + + KPrintf("HS300X:I2C humidity:%d.%d temperature:%d.%d\n", + g_hs300x_data.humi_high, + g_hs300x_data.humi_low, + g_hs300x_data.temp_high, + g_hs300x_data.temp_low); + + MdelayKTask(1000); + } + + return; +} + +void Hs300xI2cTest(void) +{ + Hs300xInit(); + MdelayKTask(1000); + + x_err_t flag; + int32 Tsk_hs300x = KTaskCreate("Tsk_hs300x", TskHs300xTest, NONE, 2048, 10); + flag = StartupKTask(Tsk_hs300x); + if (EOK != flag){ + KPrintf("Hs300xI2cTest StartupKTask failed!\n"); + return; + } +} +SHELL_EXPORT_CMD(SHELL_CMD_PERMISSION(0)|SHELL_CMD_TYPE(SHELL_TYPE_CMD_FUNC)|SHELL_CMD_PARAM_NUM(0), + Hs300xI2cTest, Hs300xI2cTest, Test the HS300X using I2C); diff --git a/Ubiquitous/XiZi/kernel/kernel_test/test_iwg.c b/Ubiquitous/XiZi/kernel/kernel_test/test_iwg.c new file mode 100644 index 0000000..e9121bb --- /dev/null +++ b/Ubiquitous/XiZi/kernel/kernel_test/test_iwg.c @@ -0,0 +1,67 @@ +/* +* Copyright (c) 2020 AIIT XUOS Lab +* XiUOS is licensed under Mulan PSL v2. +* You can use this software according to the terms and conditions of the Mulan PSL v2. +* You may obtain a copy of Mulan PSL v2 at: +* http://license.coscl.org.cn/MulanPSL2 +* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, +* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, +* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. +* See the Mulan PSL v2 for more details. +*/ + +/** +* @file TestIwg.c +* @brief support to test watchdog function +* @version 1.0 +* @author AIIT XUOS Lab +* @date 2021-04-24 +*/ + +#include +#include + +static BusType wdt; + +/** + * @description: Feed watchdog task function + */ +static void FeedWatchdog(void) +{ + while (1) + { + /* keep watchdog alive in idle task */ + struct BusConfigureInfo cfg; + cfg.configure_cmd = OPER_WDT_KEEPALIVE; + cfg.private_data = NONE; + BusDrvConfigure(wdt->owner_driver, &cfg); + KPrintf("feed the dog!\n "); + } +} + +/** + * @description: Watchdog test function + * @return success: EOK, failure: other + */ +int TestIwg(void) +{ + x_err_t res = EOK; + uint32 timeout = 1000; /* timeout time */ + + wdt = BusFind(WDT_BUS_NAME_0); + wdt->owner_driver = BusFindDriver(wdt, WDT_DRIVER_NAME_0); + wdt->owner_haldev = BusFindDevice(wdt, WDT_0_DEVICE_NAME_0); + + /* set watchdog timeout time */ + struct BusConfigureInfo cfg; + cfg.configure_cmd = OPER_WDT_SET_TIMEOUT; + cfg.private_data = &timeout; + res = BusDrvConfigure(wdt->owner_driver, &cfg); + KPrintf("feed the dog!\n"); + + int32 WdtTask = KTaskCreate("WdtTask", (void *)FeedWatchdog, NONE, 2048, 20); + res = StartupKTask(WdtTask); + + return res; +} +SHELL_EXPORT_CMD(SHELL_CMD_PERMISSION(0)|SHELL_CMD_TYPE(SHELL_TYPE_CMD_FUNC)|SHELL_CMD_PARAM_NUM(0),TestIwg, TestIwg, TestIwg ); diff --git a/Ubiquitous/XiZi/kernel/kernel_test/test_lcd.c b/Ubiquitous/XiZi/kernel/kernel_test/test_lcd.c new file mode 100644 index 0000000..32ddf04 --- /dev/null +++ b/Ubiquitous/XiZi/kernel/kernel_test/test_lcd.c @@ -0,0 +1,88 @@ +/* +* Copyright (c) 2020 AIIT XUOS Lab +* XiUOS is licensed under Mulan PSL v2. +* You can use this software according to the terms and conditions of the Mulan PSL v2. +* You may obtain a copy of Mulan PSL v2 at: +* http://license.coscl.org.cn/MulanPSL2 +* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, +* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, +* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. +* See the Mulan PSL v2 for more details. +*/ + +/** +* @file EnableLcd.c +* @brief support to test lcd function +* @version 1.0 +* @author AIIT XUOS Lab +* @date 2021-04-24 +*/ + +#include "bus_lcd.h" +#include "dev_lcd.h" + +static char *addr = "LCD Testing"; + +/** + * @description: Enable LCD function + * @param bus_name - LCD bus name + * @param driver_name - LCD driver name + * @param device_name - LCD device name + */ +static int EnableLcd(const char *bus_name, const char *driver_name, const char *device_name) +{ + struct Bus *bus; + struct Driver *driver, *bus_driver; + struct HardwareDev *device; + struct HardwareDev *bus_device; + + if (bus_name) { + KPrintf("##test find bus %s\n", bus_name); + bus = BusFind(bus_name); + KPrintf("##test bus %p##\n", bus); + } + + if (driver_name) { + KPrintf("##test find driver %s\n", driver_name); + driver = LcdDriverFind(driver_name, TYPE_LCD_DRV); + bus_driver = BusFindDriver(bus, driver_name); + KPrintf("##test driver %p bus_driver %p####\n", driver, bus_driver); + } + + if (device_name) { + KPrintf("##test find device %s\n", device_name); + device = LcdDeviceFind(device_name, TYPE_LCD_DEV); + bus_device = BusFindDevice(bus, device_name); + KPrintf("##test device %p bus_device %p##\n", device, bus_device); + } + + LcdWriteParam lcd_write_param; + lcd_write_param.type = 0; + lcd_write_param.string_info.x_pos = 60; + lcd_write_param.string_info.y_pos = 40; + lcd_write_param.string_info.width = 250; + lcd_write_param.string_info.height = 24; + lcd_write_param.string_info.font_size = 24; + lcd_write_param.string_info.addr = addr; + lcd_write_param.string_info.font_color = WHITE; + lcd_write_param.string_info.back_color = RED; + + struct BusBlockWriteParam write_param; + memset(&write_param, 0, sizeof(struct BusBlockWriteParam )); + + write_param.buffer = &lcd_write_param; + + while (1) { + BusDevWriteData(device, &write_param); + MdelayKTask(1000); + } +} + +/** + * @description: LCD test function + */ +void TestLcd(void) +{ + EnableLcd(LCD_BUS_NAME, LCD_DRV_NAME, LCD_DEVICE_NAME); +} +SHELL_EXPORT_CMD(SHELL_CMD_PERMISSION(0)|SHELL_CMD_TYPE(SHELL_TYPE_CMD_FUNC)|SHELL_CMD_PARAM_NUM(0),TestLcd, TestLcd, Test LCD); diff --git a/Ubiquitous/XiZi/kernel/kernel_test/test_main.c b/Ubiquitous/XiZi/kernel/kernel_test/test_main.c new file mode 100644 index 0000000..18d6f85 --- /dev/null +++ b/Ubiquitous/XiZi/kernel/kernel_test/test_main.c @@ -0,0 +1,130 @@ +/* +* Copyright (c) 2020 AIIT XUOS Lab +* XiUOS is licensed under Mulan PSL v2. +* You can use this software according to the terms and conditions of the Mulan PSL v2. +* You may obtain a copy of Mulan PSL v2 at: +* http://license.coscl.org.cn/MulanPSL2 +* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, +* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, +* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. +* See the Mulan PSL v2 for more details. +*/ + +/** +* @file TestMain.c +* @brief support to test function +* @version 1.0 +* @author AIIT XUOS Lab +* @date 2021-04-24 +*/ + +#include +#include +#define MAX_ITEM_NAME_LENGTH 16 +extern int TestIwg(void); + +int TestTmrD(void); +int TestTmrM(void); + +extern int TestTmr(int argc, char *argv[]); +extern int TestMem(int argc, char *argv[]); +extern int TestGatherblock(char *argv[]); +extern int TestTaskReadyAndSched(int argc, char *argv[]); +extern int TestRealtime(int argc, char * argv[]); + +void KernelTestusage(void) +{ + KPrintf("test usage.\n"); + KPrintf("e.g., TestMain -mem\n"); +} +struct TestSubitem +{ + char name[MAX_ITEM_NAME_LENGTH]; + int item; +}; + +enum TestItem +{ + USAGE = 0, /* usage idex */ + MEM, /* mem test item index */ + TIMER, /* timer test item index */ + GATHERBLOCK, + SCHED, /* task sched test */ + IWG, /* iwg test item index */ + REALTIME, + INVALID_ITEM, /* invalid index */ +}; + +static struct TestSubitem kernel_subitem[INVALID_ITEM] = +{ + { "-h", USAGE }, + { "-mem", MEM }, + { "-timer", TIMER}, + { "-gm", GATHERBLOCK}, + { "-sched", SCHED}, + { "-iwg", IWG}, + { "-realtime", REALTIME}, + +}; + +int TestMain(int argc, char*argv[]) +{ + char name[MAX_ITEM_NAME_LENGTH] = {0}; + int i = 0; + int item = -1; + + strncpy(name, argv[1], MAX_ITEM_NAME_LENGTH); ///< getting input name of test item + for(i = 0; i < INVALID_ITEM; i++) { + if(0 == strncmp(kernel_subitem[i].name, name, MAX_ITEM_NAME_LENGTH) ){ + item = kernel_subitem[i].item; + break; + } + } + + switch(item) + { + case USAGE: + KernelTestusage(); + break; + case MEM: +#ifdef KERNEL_TEST_MEM + if (argc > 2) + TestMem(argc-2,&argv[2]); +#endif + break; + case TIMER: +#ifdef KERNEL_TEST_TIMER + if (argc > 2) + TestTmr(argc-2,&argv[2]); +#endif + break; + case GATHERBLOCK: +#ifdef KERNEL_TEST_MEM + if (argc > 2) + TestGatherblock(&argv[2]); +#endif + break; + case SCHED: +#ifdef KERNEL_TEST_SCHED + if (argc > 2) + TestTaskReadyAndSched(argc-2, &argv[2]); +#endif + break; + case IWG: +#ifdef KERNEL_TEST_IWG + TestIwg(); +#endif + case REALTIME: +#ifdef KERNEL_TEST_REALTIME + if (argc > 2) + TestRealtime(argc-2, &argv[2]); +#endif + default: + break; + } + + return 0; +} + +SHELL_EXPORT_CMD(SHELL_CMD_PERMISSION(0)|SHELL_CMD_DISABLE_RETURN|SHELL_CMD_TYPE(SHELL_TYPE_CMD_MAIN), + TestMain, TestMain, test main sample ); diff --git a/Ubiquitous/XiZi/kernel/kernel_test/test_mem.c b/Ubiquitous/XiZi/kernel/kernel_test/test_mem.c new file mode 100644 index 0000000..55bf2bb --- /dev/null +++ b/Ubiquitous/XiZi/kernel/kernel_test/test_mem.c @@ -0,0 +1,451 @@ +/* +* Copyright (c) 2020 AIIT XUOS Lab +* XiUOS is licensed under Mulan PSL v2. +* You can use this software according to the terms and conditions of the Mulan PSL v2. +* You may obtain a copy of Mulan PSL v2 at: +* http://license.coscl.org.cn/MulanPSL2 +* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, +* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, +* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. +* See the Mulan PSL v2 for more details. +*/ + +/** +* @file TestMem.c +* @brief support to test mem function +* @version 1.0 +* @author AIIT XUOS Lab +* @date 2021-04-24 +*/ + +#include +#include + +extern void ShowMemory(void); +extern void ShowBuddy(void); + +/**************************test memory usage***********************************/ + +#include +#include + +#define TASK_PRIORITY 5 +#define TASK_STACK_SIZE 4096 +#define TASK_TIMESLICE 5 +#define MEM_TEST_NUMBER 23 + +int number_imm=0; +static int arr[]={0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22}; + +void Fimm(void *parameter) +{ + KPrintf("%s: task starts.\n",__func__); + int i=0; + unsigned long size; + char *ptr = NONE; + + srand(number_imm); + while (i<50) { + size = 1 << arr[rand() % MEM_TEST_NUMBER]; + ptr = x_malloc(size); + + if (ptr != NULL) { + KPrintf("alloc-memory: %d btye\n",size); + x_free(ptr); + KPrintf("free--memory: %d byte\n",size); + ptr=NONE; + } else { + KPrintf("try to get %d byte memory failed!\n",size); + return; + } + i++; + } + number_imm++; +} + +int FreeImmediatelly(void){ + + KPrintf("\033[32;1m***********test limitations*************\033[0m\n"); + KPrintf("allocation and free pointer immdiatetely. \n"); + + int32 tid; + tid = KTaskCreate("Fimm",Fimm,NONE,TASK_STACK_SIZE,TASK_PRIORITY); + + if (tid >= 0) + StartupKTask(tid); + return 0; +} + +static int num_FTillEnd=1; + +void FTillEnd(void *parameter) +{ + int i=0; + unsigned long size; + char *ptr[55]; + unsigned long arrsize[55]; + // srand((unsigned)time(NULL)*10); + srand(num_FTillEnd); + num_FTillEnd++; + + while (i<50) { + size = 1 << arr[rand() % MEM_TEST_NUMBER]; + ptr[i] = x_malloc(size); + arrsize[i]=size; + + if (ptr[i] != NULL) { + KPrintf("get memory: %d btye\n",size); + } else { + KPrintf("try to get %d byte memory failed!\n",size); + break; + } + i++; + } + i -= 1; + for( ; i>=0 ; i-- ) { + x_free(ptr[i]); + KPrintf("free memory: %d byte\n",arrsize[i]); + } + return; +} + +int FreeEnd(void) +{ + KPrintf("\033[32;1m***********test limitations*************\033[0m\n"); + KPrintf("-------allocation until no memory-------\n"); + + int32 tid; + tid = KTaskCreate("fend",FTillEnd,NONE,TASK_STACK_SIZE,TASK_PRIORITY); + + if (tid >= 0) + StartupKTask(tid); + return 0; +} + +#ifdef ARCH_ARM +#define MEM_GRIN_COUNT 1024 +#else +#define MEM_GRIN_COUNT 8000 +#endif + +char *ptr[MEM_GRIN_COUNT]; +unsigned int arr_grin[MEM_GRIN_COUNT]; + +extern void ShowBuddy(); +int FendGrin() +{ + KPrintf("\033[32;1m***********test limitations*************\033[0m\n"); + KPrintf("-------allocation for 1 byte with step 1-------\n"); + int i=0; + int tempvalue = 1; + + while( i< MEM_GRIN_COUNT) { + ptr[i] = x_malloc(tempvalue); + + if (ptr[i]) { + KPrintf("\033[32;1malloc memory [%d] ptr[%d] = 0x%x\033[0m\n",tempvalue,i,ptr[i]); + arr_grin[i] = tempvalue; + i++; + tempvalue++; + } else { + if (tempvalue == 60) + break; + tempvalue=60; + } + } + KPrintf("------------- limitation until [%d] -----------\n",i); + ShowBuddy(); + + DelayKTask(2000); + + i -= 1; + for ( ; i>=0 ; i-- ) { + x_free(ptr[i]); + KPrintf("free memory: %d byte\n",arr_grin[i]); + } + return 0; +} + +#ifdef ARCH_ARM +#define MEM_CACHE_COUNT 1024 +#else +#define MEM_CACHE_COUNT 8000 +#endif + +char *cache_ptr[MEM_CACHE_COUNT]; + +void TestCacheLimitation(int timers,int init) +{ + KPrintf("\033[32;1m******test small memory limit****\033[0m\n"); + int temp = init; + int index; + void *temp_ptr; + + timers = timers > MEM_CACHE_COUNT? MEM_CACHE_COUNT: timers; + + for (index = 1; index <= timers;index++) { + if (index&1) { + KPrintf("%d: x_malloc size [%d]. \n", index, temp); + cache_ptr[index] = x_malloc(temp); + } else { + KPrintf("%d: x_calloc size [%d]. \n", index, temp); + cache_ptr[index] = x_calloc(1,temp); + } + + if (cache_ptr[index] == NONE) { + KPrintf("%d: malloc or calloc failure. \n", index); + break; + } + + if ((index % 4) == 0) { + KPrintf("%d: x_realloc size [%d]. \n", index, temp+index); + temp_ptr = cache_ptr[index]; + cache_ptr[index] = x_realloc(cache_ptr[index], temp+index); + if (cache_ptr[index] == NONE) { + KPrintf("%d: x_realloc failure, roll back old pointer. \n", index); + cache_ptr[index] = temp_ptr; + } + } + + temp++; + temp %= 64; + temp = ((temp==0) ? (temp + 1) : temp); + } + ShowBuddy(); + + DelayKTask(1000); + + index--; + + for(; index > 0; index--){ + //KPrintf("free %d\n",index); + x_free(cache_ptr[index]); + } +} + +void UsageMem() +{ + KPrintf("%s: invalidate parameter\n",__func__); + KPrintf("%s: usage for memory \n",__func__); + KPrintf("%s: -s, test malloc allocation, e.g., test_main mem -s 64 \n",__func__); + KPrintf("%s: -c, test calloc allocation, e.g., test_main mem -c 64 \n",__func__); + KPrintf("%s: -r, test realloc allocation, e.g., test_main mem -r 64 80 \n",__func__); + KPrintf("%s: -Fimm, test limit allocation, e.g., test_main mem -Fimm \n",__func__); + KPrintf("%s: -fend, test limit allocation, e.g., test_main mem -fend \n",__func__); + KPrintf("%s: -grin, test limit allocation, e.g., test_main mem -grin \n",__func__); + KPrintf("%s: rw, test read and write opts, e.g., test_main mem rw 100 \"oldcontent\" \"newcontent\"\n",__func__); + KPrintf("%s: cache, test limit allocation, e.g., test_main mem cache 100 1,\n",__func__); + KPrintf("%s: allocate small mem for 100 timers started from 1. \n",__func__); + KPrintf("%s: exception, make exception, e.g., test_main mem exception 100\n",__func__); +} + +void TestMalloc(x_size_t size) +{ + KPrintf("\033[32;1m**********x_malloc & x_free***********\033[0m\n"); + KPrintf("the memory size is [%u] for allocation. \n", size); + KPrintf("-------------before x_malloc-----------\n"); + + ShowMemory(); + + void *ptr = x_malloc(size); + if (ptr) { + KPrintf("----------x_malloc successfully--------\n"); + ShowMemory(); + x_free(ptr); + KPrintf("-----------x_free successfully---------\n"); + ShowMemory(); + } else { + KPrintf("------------x_malloc failure-----------\n"); + } + KPrintf("****************** end *****************\n"); +} + +void TestReAlloc(x_size_t size_prev, x_size_t size_next) +{ + KPrintf("\033[32;1m**********x_realloc & x_free**********\033[0m\n"); + KPrintf("the memory size is [%u] for x_malloc. \n", size_prev); + KPrintf("-------------before x_malloc-----------\n"); + ShowMemory(); + + void *ptr = x_malloc(size_prev); + void *ptr2; + if (ptr) { + KPrintf("---------x_malloc successfully--------\n"); + ShowMemory(); + KPrintf("-----------before x_realloc-----------\n"); + KPrintf("the memory size is [%u] for x_malloc. \n", size_next); + ptr2 = x_realloc(ptr, size_next); + if (ptr2) { + KPrintf("-----------realloc successfully---------\n"); + ShowMemory(); + x_free(ptr2); + KPrintf("-----------x_free successfully---------\n"); + ShowMemory(); + } else { + KPrintf("-----------x_realloc failure-----------\n"); + if(size_next !=0) + x_free(ptr); + KPrintf("-----------x_free successfully---------\n"); + ShowMemory(); + } + } else { + KPrintf("-----------x_malloc failure------------\n"); + } + KPrintf("****************** end *****************\n"); +} + +void TestCalloc(x_size_t size) +{ + KPrintf("\033[32;1m**********x_calloc & x_free***********\033[0m\n"); + KPrintf("the memory size is [%u] for x_malloc. \n", size); + KPrintf("------------before x_calloc------------\n"); + ShowMemory(); + + void*ptr = x_calloc(1, size); + if (ptr) { + KPrintf("---------x_calloc successfully---------\n"); + ShowMemory(); + x_free(ptr); + KPrintf("----------x_free successfully----------\n"); + ShowMemory(); + } else { + KPrintf("------------x_calloc failure-----------\n"); + } + KPrintf("****************** end *****************\n"); +} + +void TestReadWrite(x_size_t size, char *raw_content, char *new_content) +{ + KPrintf("\033[32;1m**********read and write opts***********\033[0m\n"); + KPrintf("the memory size is [%u] for allocation. \n", size); + KPrintf("-------------before x_malloc-----------\n"); + int endposition; + + void *ptr = x_malloc(size); + if (ptr) { + KPrintf("----------x_malloc successfully--------\n"); + KPrintf("---------- show raw content --------\n"); + memcpy(ptr,raw_content, size > strlen(raw_content) ? strlen(raw_content): size); + endposition = size > strlen(raw_content) ? strlen(raw_content): size; + *((char*)ptr + endposition) = 0; + + KPrintf("raw content is [\033[41;1m%s\033[0m]\n",ptr); + KPrintf("----- write and show new content -----\n"); + memcpy(ptr,new_content, size > strlen(new_content)? strlen(new_content): size); + endposition = size>strlen(new_content)? strlen(new_content): size; + + *((char*)ptr + endposition) = 0; + DelayKTask(100); + + KPrintf("new content is [\033[41;1m%s\033[0m]\n",ptr); + x_free(ptr); + KPrintf("-----------x_free successfully---------\n"); + } else { + KPrintf("------------x_malloc failure-----------\n"); + } + KPrintf("\n------------------ end -----------------\n\n"); + + ptr = x_calloc(1,size); + if (ptr) { + KPrintf("----------x_calloc successfully--------\n"); + KPrintf("---------- show raw content --------\n"); + memcpy(ptr,raw_content,size > strlen(raw_content) ? strlen(raw_content): size); + endposition = size > strlen(raw_content) ? strlen(raw_content): size; + *((char*)ptr + endposition) = 0; + + KPrintf("raw content is [\033[41;1m%s\033[0m]\n",ptr); + KPrintf("----- write and show new content -----\n"); + memcpy(ptr,new_content,size > strlen(new_content) ? strlen(new_content): size); + endposition = size > strlen(new_content) ? strlen(new_content): size; + *((char*)ptr + endposition)=0; + + DelayKTask(100); + KPrintf("new content is [\033[41;1m%s\033[0m]\n",ptr); + x_free(ptr); + KPrintf("-----------x_free successfully---------\n"); + } else { + KPrintf("------------x_calloc failure-----------\n"); + } + KPrintf("****************** end *****************\n"); +} + +void TestException(x_size_t size) +{ + KPrintf("\033[32;1m**********test make exception***********\033[0m\n"); + KPrintf("the memory size is [%u] for allocation. \n", size); + + void*ptr = x_malloc(size); + if (ptr == NONE) { + KPrintf("------------x_malloc failure-----------\n"); + } else { + memset(ptr-8, 5, size+8); + x_free(ptr); + } + KPrintf("****************** end *****************\n"); +} + +int TestMem(int argc,char*argv[]) +{ + x_size_t size; + x_size_t newsize; + if (0 == strncmp("-h", argv[0], strlen("-h"))) { + UsageMem(); + } + + if (0 == strncmp("cache", argv[0], strlen("cache"))) { + if (argc == 2) { + size = atoi(argv[1]); + newsize =1; + } + + if(argc == 3) { + size = atoi(argv[1]); + newsize = atoi(argv[2]); + newsize = newsize==0 ? 1: newsize; + } + + TestCacheLimitation(size, newsize); + } + + if (0 == strncmp("-s", argv[0], strlen("-s"))) { + size = atoi(argv[1]); + TestMalloc(size); + } + + if (0 == strncmp("-r", argv[0], strlen("-r"))) { + size = atoi(argv[1]); + newsize = atoi(argv[2]); + TestReAlloc(size,newsize); + } + + if (0 == strncmp("-c", argv[0], strlen("-c"))) { + size = atoi(argv[1]); + TestCalloc(size); + } + + if (0 == strncmp("-Fimm", argv[0], strlen("-Fimm"))) { + FreeImmediatelly(); + } + + if (0 == strncmp("-fend", argv[0], strlen("-fend"))) { + FreeEnd(); + } + + if (0 == strncmp("-grin", argv[0], strlen("-grin"))) { + FendGrin(); + } + + if (0 == strncmp("rw", argv[0], strlen("rw"))) { + size = atoi(argv[1]); + TestReadWrite(size, argv[2], argv[3]); + } + + if (0 == strncmp("exception",argv[0],strlen("exception"))) { + size = atoi(argv[1]); + TestException(size); + } + + return 0; +} + +/************************** end ***********************************/ diff --git a/Ubiquitous/XiZi/kernel/kernel_test/test_realtime.c b/Ubiquitous/XiZi/kernel/kernel_test/test_realtime.c new file mode 100644 index 0000000..20630ef --- /dev/null +++ b/Ubiquitous/XiZi/kernel/kernel_test/test_realtime.c @@ -0,0 +1,351 @@ +/* +* Copyright (c) 2020 AIIT XUOS Lab +* XiUOS is licensed under Mulan PSL v2. +* You can use this software according to the terms and conditions of the Mulan PSL v2. +* You may obtain a copy of Mulan PSL v2 at: +* http://license.coscl.org.cn/MulanPSL2 +* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, +* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, +* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. +* See the Mulan PSL v2 for more details. +*/ + +/** +* @file TestRealtime.c +* @brief support to test realtime function +* @version 1.0 +* @author AIIT XUOS Lab +* @date 2021-04-24 +*/ + +#include +#include +#include + +extern unsigned int usleep(unsigned int seconds); +static BusType pin; + +#ifdef ARCH_ARM +#include +#define GPIO_C13 7 +#define GPIO_C2 17 + +void PinIrqIsr(void *args) +{ + *(volatile unsigned int *)0x40020818 = 0x2000; + + *(volatile unsigned int *)0x4002081a = 0x2000; +} + +int RealtimeIrqTest() +{ + struct PinParam testpin_1; + struct PinStat testpin_1_stat; + struct PinParam testpin_2; + int ret = 0; + + struct BusConfigureInfo configure_info_1; + struct BusConfigureInfo configure_info_2; + struct BusBlockWriteParam write_param_1; + + configure_info_1.configure_cmd = OPE_CFG; + configure_info_1.private_data = (void *)&testpin_1; + write_param_1.buffer = (void *)&testpin_1_stat; + + configure_info_2.configure_cmd = OPE_CFG; + configure_info_2.private_data = (void *)&testpin_2; + + KPrintf("%s irq test\n",__func__); + /* config test pin 1 as output*/ + testpin_1.cmd = GPIO_CONFIG_MODE; + testpin_1.pin = GPIO_C13; + testpin_1.mode = GPIO_CFG_OUTPUT; + + ret = BusDrvConfigure(pin->owner_driver, &configure_info_1); + if (ret != EOK) { + KPrintf("config testpin_1 %d failed!\n", GPIO_C13); + return -ERROR; + } + + /* set test pin 1 as high*/ + testpin_1_stat.pin = GPIO_C13; + testpin_1_stat.val = GPIO_LOW; + BusDevWriteData(pin->owner_haldev, &write_param_1); + + /* config test pin 2 as input*/ + testpin_2.cmd = GPIO_CONFIG_MODE; + testpin_2.pin = GPIO_C2; + testpin_2.mode = GPIO_CFG_INPUT; + + ret = BusDrvConfigure(pin->owner_driver, &configure_info_2); + if (ret != EOK) { + KPrintf("config testpin_2 %d input failed!\n", testpin_2.pin); + return -ERROR; + } + + testpin_2.cmd = GPIO_IRQ_REGISTER; + testpin_2.pin = GPIO_C2; + testpin_2.irq_set.irq_mode = GPIO_IRQ_EDGE_BOTH; + testpin_2.irq_set.hdr = PinIrqIsr; + testpin_2.irq_set.args = NONE; + + ret = BusDrvConfigure(pin->owner_driver, &configure_info_2); + if (ret != EOK) { + KPrintf("register testpin_2 %d irq failed!\n", testpin_2.pin); + return -ERROR; + } + + testpin_2.cmd = GPIO_IRQ_ENABLE; + testpin_2.pin = GPIO_C2; + + ret = BusDrvConfigure(pin->owner_driver, &configure_info_2); + if (ret != EOK) { + KPrintf("enable testpin_2 %d irq failed!\n", testpin_2.pin); + return -ERROR; + } + KPrintf("%s irq test\n",__func__); + + return 0; +} + +void RealtimeTaskSwitchTest() +{ + struct PinParam testpin_1; + struct PinStat testpin_1_stat; + int ret = 0; + + struct BusConfigureInfo configure_info_1; + struct BusBlockWriteParam write_param_1; + + configure_info_1.configure_cmd = OPE_CFG; + configure_info_1.private_data = (void *)&testpin_1; + write_param_1.buffer = (void *)&testpin_1_stat; + + /* config test pin 1 as output*/ + testpin_1.cmd = GPIO_CONFIG_MODE; + testpin_1.pin = GPIO_C13; + testpin_1.mode = GPIO_CFG_OUTPUT; + + ret = BusDrvConfigure(pin->owner_driver, &configure_info_1); + if (ret != EOK) { + KPrintf("config testpin_1 %d failed!\n", GPIO_C13); + return ; + } + + /* set test pin 1 as low*/ + testpin_1_stat.pin = GPIO_C13; + testpin_1_stat.val = GPIO_LOW; + BusDevWriteData(pin->owner_haldev, &write_param_1); + + while (RET_TRUE) { + DelayKTask(1); + } +} + +void GpioSpeedTest() +{ + struct PinParam testpin_1; + struct PinStat testpin_1_stat; + struct PinParam testpin_2; + int ret = 0; + + struct BusConfigureInfo configure_info_1; + struct BusConfigureInfo configure_info_2; + struct BusBlockWriteParam write_param_1; + + configure_info_1.configure_cmd = OPE_CFG; + configure_info_1.private_data = (void *)&testpin_1; + write_param_1.buffer = (void *)&testpin_1_stat; + + configure_info_2.configure_cmd = OPE_CFG; + configure_info_2.private_data = (void *)&testpin_2; + + /* config test pin 1 as output*/ + testpin_1.cmd = GPIO_CONFIG_MODE; + testpin_1.pin = GPIO_C13; + testpin_1.mode = GPIO_CFG_OUTPUT; + + ret = BusDrvConfigure(pin->owner_driver, &configure_info_1); + if (ret != EOK) { + KPrintf("config testpin_1 %d failed!\n", GPIO_C13); + return ; + } + + testpin_2.cmd = GPIO_CONFIG_MODE; + testpin_2.pin = GPIO_C2; + testpin_2.mode = GPIO_CFG_INPUT; + + ret = BusDrvConfigure(pin->owner_driver, &configure_info_2); + + /* set test pin 1 as low*/ + testpin_1_stat.pin = GPIO_C13; + testpin_1_stat.val = GPIO_LOW; + BusDevWriteData(pin->owner_haldev, &write_param_1); + + while (RET_TRUE) { + *(volatile unsigned int *)0x40020818 = 0x2000; + + *(volatile unsigned int*)0x4002081a = 0x2000; + } +} + +#else + +#define GPIO_18 18 +#define GPIO_19 19 + +void PinIrqIsr(void *args) +{ + *(volatile unsigned int *)0x3800100c |= 0x5; + + *(volatile unsigned int *)0x3800100c &= ~0x5; +} + +int RealtimeIrqTest() +{ + struct PinParam testpin_1; + struct PinStat testpin_1_stat; + struct PinParam testpin_2; + + struct BusConfigureInfo configure_info_1; + struct BusConfigureInfo configure_info_2; + struct BusBlockWriteParam write_param_1; + + configure_info_1.configure_cmd = OPE_CFG; + configure_info_1.private_data = (void *)&testpin_1; + write_param_1.buffer = (void *)&testpin_1_stat; + + configure_info_2.configure_cmd = OPE_CFG; + configure_info_2.private_data = (void *)&testpin_2; + + KPrintf("%s irq test\n",__func__); + /* config GPIO18 as output and set as low */ + testpin_1.cmd = GPIO_CONFIG_MODE; + testpin_1.pin = GPIO_18; + testpin_1.mode = GPIO_CFG_OUTPUT; + BusDrvConfigure(pin->owner_driver, &configure_info_1); + + testpin_1_stat.pin = GPIO_18; + testpin_1_stat.val = GPIO_LOW; + BusDevWriteData(pin->owner_haldev, &write_param_1); + + /* config GPIO18 as input */ + testpin_2.cmd = GPIO_CONFIG_MODE; + testpin_2.pin = GPIO_19; + testpin_2.mode = GPIO_CFG_INPUT; + BusDrvConfigure(pin->owner_driver, &configure_info_2); + + testpin_2.cmd = GPIO_IRQ_REGISTER; + testpin_2.pin = GPIO_19; + testpin_2.irq_set.irq_mode = GPIO_IRQ_EDGE_RISING; + testpin_2.irq_set.hdr = PinIrqIsr; + testpin_2.irq_set.args = NONE; + BusDrvConfigure(pin->owner_driver, &configure_info_2); + + testpin_2.cmd = GPIO_IRQ_ENABLE; + testpin_2.pin = GPIO_19; + BusDrvConfigure(pin->owner_driver, &configure_info_2); + + return 0; +} + +void RealtimeTaskSwitchTest() +{ + struct PinParam testpin_1; + struct PinStat testpin_1_stat; + + struct BusConfigureInfo configure_info_1; + struct BusBlockWriteParam write_param_1; + + configure_info_1.configure_cmd = OPE_CFG; + configure_info_1.private_data = (void *)&testpin_1; + write_param_1.buffer = (void *)&testpin_1_stat; + + testpin_1.cmd = GPIO_CONFIG_MODE; + testpin_1.pin = GPIO_18; + testpin_1.mode = GPIO_CFG_OUTPUT; + BusDrvConfigure(pin->owner_driver, &configure_info_1); + + testpin_1_stat.pin = GPIO_18; + testpin_1_stat.val = GPIO_LOW; + BusDevWriteData(pin->owner_haldev, &write_param_1); + + while (RET_TRUE) { + DelayKTask(10); + } +} + +void GpioSpeedTest() +{ + struct PinParam testpin_1; + struct PinStat testpin_1_stat; + + struct BusConfigureInfo configure_info_1; + struct BusBlockWriteParam write_param_1; + + configure_info_1.configure_cmd = OPE_CFG; + configure_info_1.private_data = (void *)&testpin_1; + write_param_1.buffer = (void *)&testpin_1_stat; + + testpin_1.cmd = GPIO_CONFIG_MODE; + testpin_1.pin = GPIO_18; + testpin_1.mode = GPIO_CFG_OUTPUT; + BusDrvConfigure(pin->owner_driver, &configure_info_1); + + testpin_1_stat.pin = GPIO_18; + testpin_1_stat.val = GPIO_LOW; + BusDevWriteData(pin->owner_haldev, &write_param_1); + + while (RET_TRUE) { + *(volatile unsigned int *)0x3800100c |= 0x5; + *(volatile unsigned int *)0x3800100c &= ~0x5; + } +} +#endif + +/********************************************************************/ +static void UsageHelp(void) +{ + KPrintf("TestRealtime.\n"); +} + +int TestRealtime(int argc, char * argv[]) +{ + int ret = 0; + struct BusConfigureInfo configure_info; + + if (NONE == argv || 0 == strncmp("-h", argv[0], strlen("-h")) || 0 == strncmp("usage", argv[0], strlen("usage"))) { + UsageHelp(); + return -EINVALED; + } + + pin = BusFind(PIN_BUS_NAME); + if (!pin) { + KPrintf("find %s failed!\n", PIN_BUS_NAME); + return -ERROR; + } + + pin->owner_driver = BusFindDriver(pin, PIN_DRIVER_NAME); + pin->owner_haldev = BusFindDevice(pin, PIN_DEVICE_NAME); + + configure_info.configure_cmd = OPE_INT; + ret = BusDrvConfigure(pin->owner_driver, &configure_info); + if (ret != EOK) { + KPrintf("initialize %s failed!\n", PIN_BUS_NAME); + return -ERROR; + } + + if (0 == strncmp("-irq",argv[0],strlen("-irq")) ) { + RealtimeIrqTest(); ///< static creat single sem test + } + + if (0 == strncmp("-task",argv[0],strlen("-task")) ) { + RealtimeTaskSwitchTest(); + } + + if (0 == strncmp("-gpio",argv[0],strlen("-gpio")) ) { + GpioSpeedTest(); + } + + return 0; +} diff --git a/Ubiquitous/XiZi/kernel/kernel_test/test_rtc.c b/Ubiquitous/XiZi/kernel/kernel_test/test_rtc.c new file mode 100644 index 0000000..bbc5ee5 --- /dev/null +++ b/Ubiquitous/XiZi/kernel/kernel_test/test_rtc.c @@ -0,0 +1,65 @@ +/* +* Copyright (c) 2020 AIIT XUOS Lab +* XiUOS is licensed under Mulan PSL v2. +* You can use this software according to the terms and conditions of the Mulan PSL v2. +* You may obtain a copy of Mulan PSL v2 at: +* http://license.coscl.org.cn/MulanPSL2 +* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, +* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, +* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. +* See the Mulan PSL v2 for more details. +*/ + +/** +* @file TestRtc.c +* @brief support to test rtc function +* @version 1.0 +* @author AIIT XUOS Lab +* @date 2021-04-24 +*/ + +#include +#include + +#ifdef RESOURCES_RTC + +static int TestRtc(int argc, char *argv[]) +{ + time_t now; + + struct RtcSetParam rtc_set_param; + + KPrintf("TestRtc cmd %s\n", argv[1]); + + if (0 == strcmp("-s", argv[1])) { + rtc_set_param.rtc_set_cmd = OPER_RTC_SET_TIME; + rtc_set_param.date_param.year = 2021; + rtc_set_param.date_param.month = 4; + rtc_set_param.date_param.day = 6; + rtc_set_param.time_param.hour = 16; + rtc_set_param.time_param.minute = 0; + rtc_set_param.time_param.second = 0; + + RtcDrvSetFunction(RTC_DRV_NAME, &rtc_set_param); + + rtc_set_param.rtc_set_cmd = OPER_RTC_GET_TIME; + rtc_set_param.time = &now; + + RtcDrvSetFunction(RTC_DRV_NAME, &rtc_set_param); + + KPrintf("%s\n", ctime(&now)); + } else if (0 == strcmp("-g", argv[1])) { + rtc_set_param.rtc_set_cmd = OPER_RTC_GET_TIME; + rtc_set_param.time = &now; + + RtcDrvSetFunction(RTC_DRV_NAME, &rtc_set_param); + + KPrintf("%s\n", ctime(&now)); + } + + return EOK; +} +SHELL_EXPORT_CMD(SHELL_CMD_PERMISSION(0)|SHELL_CMD_TYPE(SHELL_TYPE_CMD_MAIN)|SHELL_CMD_PARAM_NUM(4), + TestRtc, TestRtc, Test the RTC Function); + +#endif diff --git a/Ubiquitous/XiZi/kernel/kernel_test/test_serial.c b/Ubiquitous/XiZi/kernel/kernel_test/test_serial.c new file mode 100644 index 0000000..0045138 --- /dev/null +++ b/Ubiquitous/XiZi/kernel/kernel_test/test_serial.c @@ -0,0 +1,202 @@ +/* +* Copyright (c) 2020 AIIT XUOS Lab +* XiUOS is licensed under Mulan PSL v2. +* You can use this software according to the terms and conditions of the Mulan PSL v2. +* You may obtain a copy of Mulan PSL v2 at: +* http://license.coscl.org.cn/MulanPSL2 +* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, +* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, +* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. +* See the Mulan PSL v2 for more details. +*/ + +/** +* @file test_serial.c +* @brief support to test serial function +* @version 1.0 +* @author AIIT XUOS Lab +* @date 2021-04-24 +*/ + +#include +#include +#if defined (ARCH_RISCV) +#include +#elif defined(ARCH_ARM) +#include +#endif + +//#define TEST_POSIX + +#ifdef TEST_POSIX +#include "user_api.h" +#endif + +#ifdef RESOURCES_SERIAL + +static char test_str[] = "Hello AIIT!\r\n"; + +struct Bus *bus = NONE; +struct Driver *bus_driver = NONE; +struct HardwareDev *bus_device = NONE; + +#ifdef TEST_POSIX +static int uart3_fd = 0; +#endif +static int32 test_serial_task = 0; + +static void TestSerialRecvTask(void *parameter) +{ + int16 i = 0; + char recv_data = 0; +#ifdef TEST_POSIX + char data_buffer[128] = {0}; + char data_size = 0; +#endif + struct BusBlockReadParam read_param; + struct BusBlockWriteParam write_param; + memset(&read_param, 0, sizeof(struct BusBlockReadParam)); + memset(&write_param, 0, sizeof(struct BusBlockWriteParam)); + + + + while(RET_TRUE) { +#ifndef TEST_POSIX + read_param.size = 1; + read_param.buffer = &recv_data; + read_param.read_length = 0; + + KPrintf("ready to read data\n"); + BusDevReadData(bus_device, &read_param); + for (i = 0; i < read_param.read_length; i ++) { + KPrintf("TestSerialRecvTask i %d char 0x%x\n", i, recv_data); + } + + KPrintf("send data %c\n", recv_data); + write_param.buffer = &recv_data; + write_param.size = 1; + BusDevWriteData(bus_device, &write_param); +#else + memset(data_buffer, 0, 128); + data_size = read(uart3_fd, data_buffer, 128); + KPrintf("uart 3 data size %d data %s\n", data_size, data_buffer); +#endif + } +} + +static int SerialBusCheck(const char *bus_name, const char *driver_name, const char *device_name) +{ + int ret = EOK; +#ifndef TEST_POSIX + struct SerialBus *serial_bus = NONE; + struct SerialDriver *serial_driver = NONE; + struct SerialHardwareDevice *serial_device = NONE; + struct SerialCfgParam *serial_cfg_default = NONE; + struct SerialDevParam *serial_dev_param = NONE; + + struct BusConfigureInfo configure_info; + + if(bus_name) + { + KPrintf("####test find bus %s\n", bus_name); + bus = BusFind(bus_name); + serial_bus = (struct SerialBus *)bus; + KPrintf("####test find bus %8p serial_bus %8p\n", bus, serial_bus); + } + + if(driver_name) + { + KPrintf("####test find driver %s\n", driver_name); + bus_driver = BusFindDriver(bus, driver_name); + serial_driver = (struct SerialDriver *)bus_driver; + serial_cfg_default = (struct SerialCfgParam *)serial_driver->private_data; + KPrintf("####test bus_driver %8p serial_driver %8p done %8p serial_cfg_default %8p####\n", + bus_driver, serial_driver, serial_driver->drv_done, serial_cfg_default); + KPrintf("####hw cfg base 0x%x irq %d####\n", serial_cfg_default->hw_cfg.serial_register_base, serial_cfg_default->hw_cfg.serial_irq_interrupt); + KPrintf("####data cfg rate %u order %u size %u bits %u invert %u parity %u stop %u####\n", serial_cfg_default->data_cfg.serial_baud_rate, serial_cfg_default->data_cfg.serial_bit_order, serial_cfg_default->data_cfg.serial_buffer_size, + serial_cfg_default->data_cfg.serial_data_bits, serial_cfg_default->data_cfg.serial_invert_mode, serial_cfg_default->data_cfg.serial_parity_mode, serial_cfg_default->data_cfg.serial_stop_bits); + } + + if(device_name) + { + KPrintf("####test find device0 %s\n", device_name); + bus_device = BusFindDevice(bus, device_name); + serial_device = (struct SerialHardwareDevice *)bus_device; + serial_dev_param = (struct SerialDevParam *)bus_device->private_data; + KPrintf("####test bus_device %8p serial_dev %8p hwdone %8p devdone %8p####\n", + bus_device, serial_device, serial_device->hwdev_done, serial_device->haldev.dev_done); + KPrintf("####dev_param %8p work mode 0x%x set mode 0x%x stream mode 0x%x\n", + serial_dev_param, serial_dev_param->serial_work_mode, serial_dev_param->serial_set_mode, serial_dev_param->serial_stream_mode); + } + + //BusDevRecvCallback(bus_device, test_serial_callback); + + /*step 1: init bus_driver, change struct SerialCfgParam if necessary*/ + struct SerialCfgParam serial_cfg; + memset(&serial_cfg, 0, sizeof(struct SerialCfgParam)); + configure_info.configure_cmd = OPE_INT; + configure_info.private_data = &serial_cfg; + BusDrvConfigure(bus_driver, &configure_info); + KPrintf("BusDrvConfigure OPE_INT done\n"); + + /*step 2: match bus_driver with bus_device*/ + bus->match(bus_driver, bus_device); + + /*step 3: open bus_device, configure struct SerialDevParam if necessary*/ + serial_dev_param->serial_set_mode = 0; + serial_dev_param->serial_work_mode = SIGN_OPER_DMA_RX;//SIGN_OPER_INT_RX; + serial_dev_param->serial_stream_mode = SIGN_OPER_STREAM; + BusDevOpen(bus_device); + KPrintf("BusDevOpen done\n"); + + /*step 4: write serial data, configure struct BusBlockWriteParam*/ + struct BusBlockWriteParam write_param; + write_param.pos = 0; + write_param.buffer = (void *)test_str; + write_param.size = sizeof(test_str) - 1; + BusDevWriteData(bus_device, &write_param); + + //BusDevClose(bus_device); + //KPrintf("BusDevClose done\n"); +#else + uart3_fd = open("/dev/uart3_dev3", O_RDWR); + if (uart3_fd < 0) { + KPrintf("open fd error %d\n", uart3_fd); + } + KPrintf("open fd %d\n", uart3_fd); + + struct SerialDataCfg cfg; + cfg.serial_baud_rate = BAUD_RATE_115200; + cfg.serial_data_bits = DATA_BITS_8; + cfg.serial_stop_bits = STOP_BITS_1; + cfg.serial_buffer_size = 128; + cfg.serial_parity_mode = PARITY_NONE; + cfg.serial_bit_order = 0; + cfg.serial_invert_mode = 0; + cfg.ext_uart_no = 0; + cfg.port_configure = 0; + + if (ret != ioctl(uart3_fd, OPE_INT, &cfg)) { + KPrintf("ioctl fd error %d\n", ret); + } +#endif +} + +int TestSerial(void) +{ + /*use serial device 3 to test serial function*/ + SerialBusCheck(SERIAL_BUS_NAME_3, SERIAL_DRV_NAME_3, SERIAL_3_DEVICE_NAME_0); + + test_serial_task = KTaskCreate("TestSerialRecvTask", + TestSerialRecvTask, + NONE, + 2048, + 18); + StartupKTask(test_serial_task); + + return EOK; +} +SHELL_EXPORT_CMD(SHELL_CMD_PERMISSION(0)|SHELL_CMD_TYPE(SHELL_TYPE_CMD_MAIN), + TestSerial, TestSerial, TestSerial ); + +#endif diff --git a/Ubiquitous/XiZi/kernel/kernel_test/test_threadsched.c b/Ubiquitous/XiZi/kernel/kernel_test/test_threadsched.c new file mode 100644 index 0000000..54f7a5e --- /dev/null +++ b/Ubiquitous/XiZi/kernel/kernel_test/test_threadsched.c @@ -0,0 +1,199 @@ +/* +* Copyright (c) 2020 AIIT XUOS Lab +* XiUOS is licensed under Mulan PSL v2. +* You can use this software according to the terms and conditions of the Mulan PSL v2. +* You may obtain a copy of Mulan PSL v2 at: +* http://license.coscl.org.cn/MulanPSL2 +* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, +* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, +* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. +* See the Mulan PSL v2 for more details. +*/ + +/** +* @file test_threadsched.c +* @brief support to test thread sched function +* @version 1.0 +* @author AIIT XUOS Lab +* @date 2021-04-24 +*/ + +#include +#include +#include + +extern long ShowTask(void); +extern unsigned int msleep(uint64_t msec); + +static int32 tid1 = NONE; +static int32 tid2 = NONE; +static int32 tid3 = NONE; +static int32 tid4 = NONE; +static int32 tid5 = NONE; + +#define DYNAMIC_TASK_STACK_SIZE 3072 +#define PRIORITY 15 +static void Task1Entry(void *parameter) +{ + int cnt = 10; + DoubleLinklistType* node = NONE; + DoubleLinklistType* head = NONE; + struct TaskDescriptor *obj = NONE; + TaskDyncSchedMembeType *tmp = NONE; + register x_base level; + + #ifdef ARCH_SMP + if (0 == strncmp(parameter,"-b",strlen("-b"))) { ///< if tasks bind to cpu 0 + head = &(Assign.smp_os_assign_ready_rector[0].priority_ready_vector[PRIORITY]); + } else { + head = &(Assign.os_assign_read_vector.priority_ready_vector[PRIORITY]); + } + #else + head = &(Assign.os_assign_read_vector.priority_ready_vector[PRIORITY]); + #endif + while(cnt--) { +#ifdef TOOL_SHELL + ShowTask(); +#endif + KPrintf("\n"); + + DOUBLE_LINKLIST_FOR_EACH(node, head) { + tmp = SYS_DOUBLE_LINKLIST_ENTRY(node, struct TaskDyncSchedMember, sched_link); + obj =CONTAINER_OF(tmp,struct TaskDescriptor, task_dync_sched_member); + KPrintf("task ready table node name = %s node remaining_tick= %d node advance_cnt =%d\n",obj->task_base_info.name, + obj->task_dync_sched_member.rest_timeslice, obj->task_dync_sched_member.advance_cnt); + } +#ifdef ARCH_SMP +#ifdef SCHED_POLICY_FIFO + MdelayKTask(30); +#else + msleep(30); +#endif +#else +#ifdef ARCH_ARM + MdelayKTask(3); +#else + MdelayKTask(80); +#endif +#endif + } + KTaskDelete(tid2); + KTaskDelete(tid3); + KTaskDelete(tid4); + KTaskDelete(tid5); + +} + +static void Task2Entry(void *parameter) +{ + int i = 0; + while(RET_TRUE) { + i++; + } +} +static void Task3Entry(void *parameter) +{ + int i = 0; + while(RET_TRUE) { + i++; + } +} +static void Task4Entry(void *parameter) +{ + int i = 0; + while(RET_TRUE) { + i++; + } +} +static void Task5Entry(void *parameter) +{ + int i = 0; + while(RET_TRUE) { + i++; + } +} + +void DynamicTaskSchedTest(char* parm) +{ + char t_parm[4]; +#ifdef ARCH_SMP + if (0 == strncmp("-b", parm, strlen("-b")) || 0 == strncmp("-bind", parm, strlen("-bind"))){ + strncpy(t_parm,"-b", 4); + } +#endif + tid1 = KTaskCreate("d_tid1", + Task1Entry, + t_parm, + DYNAMIC_TASK_STACK_SIZE, + 16); + if (tid1 >= 0) + StartupKTask(tid1); + + tid2 = KTaskCreate("d_tid2", + Task2Entry, + "d_tid2", + 1024, + 15); +#ifdef ARCH_SMP + if (0 == strncmp("-b", parm, strlen("-b")) || 0 == strncmp("-bind", parm, strlen("-bind"))){ + KTaskCoreCombine(tid2, 0); + } +#endif + if (tid2 >= 0) + StartupKTask(tid2); + + tid3 = KTaskCreate("d_tid3", + Task3Entry, + "d_tid3", + 1024, + 15); +#ifdef ARCH_SMP + if (0 == strncmp("-b", parm, strlen("-b")) || 0 == strncmp("-bind", parm, strlen("-bind"))){ + KTaskCoreCombine(tid3, 0); + } +#endif + if (tid3 >= 0) + StartupKTask(tid3); + + tid4 = KTaskCreate("d_tid4", + Task4Entry, + "d_tid4", + 1024, + 15); +#ifdef ARCH_SMP + if (0 == strncmp("-b", parm, strlen("-b")) || 0 == strncmp("-bind", parm, strlen("-bind"))){ + KTaskCoreCombine(tid4, 0); + } +#endif + if (tid4 >= 0) + StartupKTask(tid4); + + tid5 = KTaskCreate("d_tid5", + Task5Entry, + "d_tid5", + 1024, + 15); + +#ifdef ARCH_SMP + if (0 == strncmp("-b", parm, strlen("-b")) || 0 == strncmp("-bind", parm, strlen("-bind"))){ + KTaskCoreCombine(tid5, 0); + } +#endif + if (tid5 >= 0) + StartupKTask(tid5); +} + +/********************************************************************/ +static void UsageHelp(void) +{ + KPrintf("test_task_ready_usage.\n"); +} + +int TestTaskReadyAndSched(int argc, char * argv[]) +{ + DynamicTaskSchedTest(argv[0]); + + return 0; +} + + diff --git a/Ubiquitous/XiZi/kernel/kernel_test/test_timer.c b/Ubiquitous/XiZi/kernel/kernel_test/test_timer.c new file mode 100644 index 0000000..5d5cca4 --- /dev/null +++ b/Ubiquitous/XiZi/kernel/kernel_test/test_timer.c @@ -0,0 +1,116 @@ +/* +* Copyright (c) 2020 AIIT XUOS Lab +* XiUOS is licensed under Mulan PSL v2. +* You can use this software according to the terms and conditions of the Mulan PSL v2. +* You may obtain a copy of Mulan PSL v2 at: +* http://license.coscl.org.cn/MulanPSL2 +* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, +* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, +* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. +* See the Mulan PSL v2 for more details. +*/ + +/** +* @file test_timer.c +* @brief support to test timer function +* @version 1.0 +* @author AIIT XUOS Lab +* @date 2021-04-24 +*/ + +#include + +extern long ShowTimer(void); +/*****************************************************************************************************************/ +/***********************************test create timer with dynamic style *****************************************/ + + +static int32 dynamic_timer1; +static int32 dynamic_timer2; +static int dynamic_cnt = 0; + + +static void DynamicTimeout1Entry(void *parameter) +{ + KPrintf("periodic timer is timeout %d\n", dynamic_cnt); + if (dynamic_cnt++>= 9){ + KTimerQuitRun(dynamic_timer1); + KPrintf("periodic timer was stopped! \n"); + } +} + +static void DynamicTimeout2Entry(void *parameter) +{ + KPrintf("one shot timer is timeout\n"); +} + +int TestDynamicTimer(void) +{ + dynamic_timer1 = KCreateTimer("d_tmr1", DynamicTimeout1Entry, + NONE, 10, + TIMER_TRIGGER_PERIODIC); + + if (dynamic_timer1 != NONE) KTimerStartRun(dynamic_timer1); + + dynamic_timer2 = KCreateTimer("d_tmr2", DynamicTimeout2Entry, + NONE, 30, + TIMER_TRIGGER_ONCE); + + if (dynamic_timer2 != NONE) KTimerStartRun(dynamic_timer2); + ShowTimer(); + return 0; +} + +int TestTmrD(void) +{ + KPrintf("test dynamic timer\n"); + TestDynamicTimer(); + return 0; +} + +/*******************************test mixed timers with dynamic and static style **********************************/ +static int32 mixed_timer_d; +static int32 test_delete_timer; + +static int num = 0; + + +static void MexedTimeout2Entry(void *parameter) +{ + KPrintf("mixed\n"); + KTimerQuitRun(mixed_timer_d); +} + +int TimerMix(void) +{ + mixed_timer_d = KCreateTimer("mix_t2", MexedTimeout2Entry, NONE, 30, TIMER_TRIGGER_ONCE); + + if (mixed_timer_d != NONE) KTimerStartRun(mixed_timer_d); + + test_delete_timer = KCreateTimer("del_t3", MexedTimeout2Entry, NONE, 30, TIMER_TRIGGER_ONCE); + ShowTimer(); + if(test_delete_timer != NONE) + KDeleteTimer(test_delete_timer); + + return 0; +} + +int TestTmrM(void) +{ + KPrintf("test mixed timer\n"); + TimerMix(); + return 0; +} + +int TestTmr(int argc, char*argv[]) { + + KPrintf("/******************************************** START **************************************************/\n"); + TestTmrD(); + MdelayKTask(4000); + KPrintf("/******************************************* boundary ************************************************/\n"); + TestTmrM(); + MdelayKTask(4000); + KPrintf("/********************************************* END **************************************************/\n"); + + return 0; +} diff --git a/Ubiquitous/XiZi/kernel/kernel_test/test_touch.c b/Ubiquitous/XiZi/kernel/kernel_test/test_touch.c new file mode 100644 index 0000000..9ded663 --- /dev/null +++ b/Ubiquitous/XiZi/kernel/kernel_test/test_touch.c @@ -0,0 +1,81 @@ +/* +* Copyright (c) 2020 AIIT XUOS Lab +* XiUOS is licensed under Mulan PSL v2. +* You can use this software according to the terms and conditions of the Mulan PSL v2. +* You may obtain a copy of Mulan PSL v2 at: +* http://license.coscl.org.cn/MulanPSL2 +* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, +* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, +* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. +* See the Mulan PSL v2 for more details. +*/ + +/** +* @file test_touch.c +* @brief support to test touch function +* @version 1.0 +* @author AIIT XUOS Lab +* @date 2021-04-24 +*/ + +#include "bus_touch.h" +#include "dev_touch.h" + +int TestTouch(const char *bus_name, const char *driver_name, const char *device_name0) +{ + struct Bus *bus; + struct Driver *driver, *bus_driver; + struct HardwareDev *device0; + struct HardwareDev *bus_device0; + struct TouchDataStandard datacfg; + + struct TouchDataStandard data ={0,0}; + + struct BusConfigureInfo configure_info = {0,&data}; + + struct BusBlockReadParam read_param; + memset(&read_param,0,sizeof(struct BusBlockReadParam )); + + read_param.buffer = &data; + + if(bus_name) + { + KPrintf("##test find bus %s\n", bus_name); + bus = BusFind(bus_name); + KPrintf("##test bus %p####\n", bus); + } + + if(driver_name) + { + KPrintf("##test find driver %s\n", driver_name); + driver = TouchDriverFind(driver_name, TYPE_TOUCH_DRV); + bus_driver = BusFindDriver(bus, driver_name); + KPrintf("##test driver %p bus_driver %p##\n", driver, bus_driver); + } + + if(device_name0) + { + KPrintf("##test find device0 %s\n", device_name0); + device0 = TouchDeviceFind(device_name0, TYPE_TOUCH_DEV); + KPrintf("device0 :%p\n", device0); + bus_device0 = BusFindDevice(bus, device_name0); + KPrintf("bus_device0 :%p\n", bus_device0); + } + KPrintf("ttt\n"); + BusDrvConfigure(bus_driver, &configure_info); + KPrintf("yyy\n"); + while(1) + { + BusDevReadData(bus_device0,&read_param); + KPrintf("dev.x= %8d *** dev.y= %8d \r\n",data.x,data.y); + MdelayKTask(100); + } + +} + +void TouchTest(void) +{ + TestTouch(TOUCH_BUS_NAME_1,TOUCH_DRV_NAME_1, TOUCH_1_DEVICE_NAME_0); +} + +SHELL_EXPORT_CMD(SHELL_CMD_PERMISSION(0)|SHELL_CMD_TYPE(SHELL_TYPE_CMD_FUNC)|SHELL_CMD_PARAM_NUM(0),TouchTest, TouchTest, Close AC task ); \ No newline at end of file diff --git a/Ubiquitous/XiZi/kernel/kernel_test/user_api.h b/Ubiquitous/XiZi/kernel/kernel_test/user_api.h new file mode 100644 index 0000000..aea1372 --- /dev/null +++ b/Ubiquitous/XiZi/kernel/kernel_test/user_api.h @@ -0,0 +1,237 @@ +/* +* Copyright (c) 2020 AIIT XUOS Lab +* XiUOS is licensed under Mulan PSL v2. +* You can use this software according to the terms and conditions of the Mulan PSL v2. +* You may obtain a copy of Mulan PSL v2 at: +* http://license.coscl.org.cn/MulanPSL2 +* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, +* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, +* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. +* See the Mulan PSL v2 for more details. +*/ + +/** +* @file user_api.h +* @brief define user api function and struct +* @version 1.0 +* @author AIIT XUOS Lab +* @date 2021-04-24 +*/ + +#ifndef __XS_USER_API_H__ +#define __XS_USER_API_H__ + +#include +#include + +#ifdef SEPARATE_COMPILE +#include +#include +#include +#if defined(FS_VFS) +#include +#ifndef TASK_ISOLATION +#include +#endif +#endif + +#include + +#define TASK_INFO 1 +#define MEM_INFO 2 +#define SEM_INFO 3 +#define EVENT_INFO 4 +#define MUTEX_INFO 5 +#define MEMPOOL_INFO 6 +#define MSGQUEUE_INFO 7 +#define DEVICE_INFO 8 +#define TIMER_INFO 9 + +int UserPrintInfo(unsigned long i); + +struct utask +{ + char name[NAME_NUM_MAX]; + void *func_entry; + void *func_param; + uint32 stack_size; + uint8 prio; +}; +typedef struct utask UtaskType; + +typedef void DIR; + +int32 UserTaskCreate(UtaskType utask); + +x_err_t UserTaskStartup(int32 id); +x_err_t UserTaskDelete(int32 id); +void UserTaskQuit(void); +x_err_t UserTaskDelay(int32 ms); +x_err_t UserGetTaskName(int32 id ,char *name); +int32 UserGetTaskID(void); +uint8 UserGetTaskStat(int32 id); + +#ifdef ARCH_SMP +x_err_t UserTaskCoreCombine(int32 id,uint8 core_id); +x_err_t UserTaskCoreUnCombine(int32 id); +uint8 UserGetTaskCombinedCore(int32 id); +uint8 UserGetTaskRunningCore(int32 id); +#endif + +x_err_t UserGetTaskErrorstatus(int32 id); +uint8 UserGetTaskPriority(int32 id); + + +void *UserMalloc(x_size_t size); +void *UserRealloc(void *pointer, x_size_t size); +void *UserCalloc(x_size_t count, x_size_t size); +void UserFree(void *pointer); + +#ifdef KERNEL_MUTEX +int32 UserMutexCreate(); +void UserMutexDelete(int32 mutex); +int32 UserMutexObtain(int32 mutex, int32 wait_time); +int32 UserMutexAbandon(int32 mutex); +#endif + + +#ifdef KERNEL_SEMAPHORE +typedef int32 sem_t; +sem_t UserSemaphoreCreate(uint16 val); +x_err_t UserSemaphoreDelete(sem_t sem); +x_err_t UserSemaphoreObtain(sem_t sem, int32 wait_time); +x_err_t UserSemaphoreAbandon(sem_t sem); +x_err_t UserSemaphoreSetValue(sem_t sem, uint16 val); +#endif + + +#ifdef KERNEL_EVENT +EventIdType UserEventCreate(uint8 flag); +void UserEventDelete(EventIdType event); +x_err_t UserEventTrigger(EventIdType event, uint32 set); +x_err_t UserEventProcess(EventIdType event, uint32 set, uint8 option, + int32 wait_time, uint32 *Recved); +x_err_t UserEventReinit(EventIdType event); +#endif + + +#ifdef KERNEL_MESSAGEQUEUE +int32 UserMsgQueueCreate(x_size_t msg_size, x_size_t max_msgs); +x_err_t UserMsgQueueDelete(int32 mq ); +x_err_t UserMsgQueueSendwait(int32 mq, const void *buffer, + x_size_t size, int32 wait_time); +x_err_t UserMsgQueueSend(int32 mq, const void *buffer, x_size_t size); +x_err_t UserMsgQueueUrgentSend(int32 mq, const void *buffer, x_size_t size); +x_err_t UserMsgQueueRecv(int32 mq, void *buffer, x_size_t size,int32 wait_time); +x_err_t UserMsgQueueReinit(int32 mq); +#endif + +int open(const char *path, int flags, ...); +int read(int fd, void *buf, size_t len); +int write(int fd, const void *buf, size_t len); +int close(int fd); +off_t lseek(int fd, off_t offset, int whence); +int rename(const char *from, const char *to); +int unlink(const char *path); +int stat(const char *path, struct stat *buf); +int fstat(int fd, struct stat *buf); +int fsync(int fd); +int ftruncate(int fd, off_t length); + +int mkdir(const char *path, mode_t mode); +DIR *opendir(const char *path); +int closedir(DIR *dirp); +struct dirent *readdir(DIR *dirp); +int rmdir(const char *path); +int chdir(const char *path); +char *getcwd(char *buf, size_t size); +long telldir(DIR *dirp); +void seekdir(DIR *dirp, off_t offset); +void rewinddir(DIR *dirp); + +#ifdef FS_VFS +struct statfs { + size_t f_bsize; + size_t f_blocks; + size_t f_bfree; +}; + +int statfs(const char *path, struct statfs *buf); +#endif + +int UserPrintf(const char *fmt, ...); + +#else +struct utask +{ + char name[NAME_NUM_MAX]; + void *func_entry; + void *func_param; + int32_t stack_size; + uint8_t prio; +}; +typedef struct utask UtaskType; +int32_t UserTaskCreate(UtaskType utask); + +#define UserTaskStartup StartupKTask +#define UserTaskDelete KTaskDelete +#define UserTaskQuit KTaskQuit +#define UserTaskDelay MdelayKTask + +x_err_t UserGetTaskName(int32_t id ,char *name); +int32_t UserGetTaskID(void); +uint8_t UserGetTaskStat(int32_t id); + +#ifdef ARCH_SMP +#define UserTaskCoreCombine KTaskCoreCombine +#define UserTaskCoreUnCombine KTaskCoreUnCombine + +uint8_t UserGetTaskCombinedCore(int32_t id); +uint8_t UserGetTaskRunningCore(int32_t id); +#endif + +x_err_t UserGetTaskErrorstatus(int32_t id); +uint8_t UserGetTaskPriority(int32_t id); + +#define UserMalloc x_malloc +#define UserRealloc x_realloc +#define UserCalloc x_calloc +#define UserFree x_free + +#ifdef KERNEL_MUTEX +#define UserMutexCreate KMutexCreate +#define UserMutexDelete KMutexDelete +#define UserMutexObtain KMutexObtain +#define UserMutexAbandon KMutexAbandon +#endif + + +#ifdef KERNEL_SEMAPHORE +#define UserSemaphoreCreate KSemaphoreCreate +#define UserSemaphoreDelete KSemaphoreDelete +#define UserSemaphoreObtain KSemaphoreObtain +#define UserSemaphoreAbandon KSemaphoreAbandon +#define UserSemaphoreSetValue KSemaphoreSetValue +#endif + +#ifdef KERNEL_EVENT +#define UserEventCreate KEventCreate +#define UserEventDelete KEventDelete +#define UserEventTrigger KEventTrigger +#define UserEventProcess KEventProcess +#endif + +#ifdef KERNEL_MESSAGEQUEUE +#define UserMsgQueueCreate KCreateMsgQueue +#define UserMsgQueueDelete KDeleteMsgQueue +#define UserMsgQueueSendwait KMsgQueueSendwait +#define UserMsgQueueSend KMsgQueueSend +#define UserMsgQueueUrgentSend KMsgQueueUrgentSend +#define UserMsgQueueRecv KMsgQueueRecv +#define UserMsgQueueReinit KMsgQueueReinit +#endif + +#define UserPrintf KPrintf +#endif + +#endif \ No newline at end of file diff --git a/Ubiquitous/XiZi/kernel/memory/Makefile b/Ubiquitous/XiZi/kernel/memory/Makefile new file mode 100644 index 0000000..26d3618 --- /dev/null +++ b/Ubiquitous/XiZi/kernel/memory/Makefile @@ -0,0 +1,11 @@ +SRC_FILES := byte_manage.c + +ifeq ($(CONFIG_KERNEL_MEMBLOCK),y) + SRC_FILES += gatherblock.c +endif + +ifeq ($(CONFIG_TASK_ISOLATION),y) + SRC_FILES += isolation.c +endif + +include $(KERNEL_ROOT)/compiler.mk diff --git a/Ubiquitous/XiZi/kernel/memory/byte_manage.c b/Ubiquitous/XiZi/kernel/memory/byte_manage.c new file mode 100644 index 0000000..1555979 --- /dev/null +++ b/Ubiquitous/XiZi/kernel/memory/byte_manage.c @@ -0,0 +1,1256 @@ +/* +* Copyright (c) 2020 AIIT XUOS Lab +* XiUOS is licensed under Mulan PSL v2. +* You can use this software according to the terms and conditions of the Mulan PSL v2. +* You may obtain a copy of Mulan PSL v2 at: +* http://license.coscl.org.cn/MulanPSL2 +* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, +* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, +* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. +* See the Mulan PSL v2 for more details. +*/ + +/** +* @file: byte_manage.c +* @brief: memory management file +* @version: 1.0 +* @author: AIIT XUOS Lab +* @date: 2020/3/8 +* +*/ + +#include +#include + +#define MEM_STATS + +/* Covert pointer to other structure */ +#define PTR2ALLOCNODE(pointer) (struct DynamicAllocNode *)(pointer) +#define PTR2FREENODE(pointer) (struct DynamicFreeNode *)(pointer) + +/* Calculate the size of AllocNode and FreeNode */ +#define SIZEOF_DYNAMICALLOCNODE_MEM (sizeof(struct DynamicAllocNode)) +#define SIZEOF_PTR_MEM (sizeof(struct DynamicFreeNode *)) +#define SIZEOF_XSFREENODE_MEM (SIZEOF_DYNAMICALLOCNODE_MEM + 2* SIZEOF_PTR_MEM) + +/* Set the limits of buddy memory */ +#define MEM_LOW_SHIFT (6) +#define MEM_HIGH_SHIFT (20) +#define MEM_LOW_RANGE (1 << MEM_LOW_SHIFT) +#define MEM_HIGH_RANGE (1 << MEM_HIGH_SHIFT) +#define MEM_LINKNRS (MEM_HIGH_SHIFT-MEM_LOW_SHIFT +1) + +/* These masks are used to get the flags and data field of memory blocks */ +#define STATIC_BLOCK_MASK 0x80000000 +#define DYNAMIC_BLOCK_MASK 0x40000000 +#define DYNAMIC_BLOCK_NO_EXTMEM_MASK DYNAMIC_BLOCK_MASK +// #define DYNAMIC_BLOCK_EXTMEM1_MASK 0x40010000 ///< dynamic memory block external SRAM 1 +// #define DYNAMIC_BLOCK_EXTMEM2_MASK 0x40020000 ///< dynamic memory block external SRAM 2 +// #define DYNAMIC_BLOCK_EXTMEM3_MASK 0x40030000 ///< dynamic memory block external SRAM 3 +// #define DYNAMIC_BLOCK_EXTMEM4_MASK 0x40040000 ///< dynamic memory block external SRAM 4 +#define DYNAMIC_BLOCK_EXTMEMn_MASK(n) (DYNAMIC_BLOCK_MASK | (0xFF & n) << 16) + +#define ALLOC_BLOCK_MASK 0xc0000000 +#define DYNAMIC_REMAINING_MASK 0x3fffffff + +#define SIZEOF_32B (32) +#define SIZEOF_64B (64) + +#define SMALL_SIZE_32B(ITEMSIZE) ((ITEMSIZE + SIZEOF_DYNAMICALLOCNODE_MEM) * SMALL_NUMBER_32B) /* Calculate the total size for SIZEOF_32B blocks*/ +#define SMALL_SIZE_64B(ITEMSIZE) ((ITEMSIZE + SIZEOF_DYNAMICALLOCNODE_MEM) * SMALL_NUMBER_64B) /* Calculate the total size for SIZEOF_64B blocks*/ + +/** + * The structure describes an allocated memory block from dynamic buddy memory. + */ +struct DynamicAllocNode +{ + x_size_t size; /* the size of dynamicAllocNode */ + uint32 prev_adj_size; /* the size of the previous adjacent node, (dynamic alloc node or dynamic free node */ + uint32 flag; /* |static_dynamic[32-24]|ext_sram[23-16]|res[15-8]|res[7-0]| */ +}; + +/** + * The structure describes a released memory block in dynamic buddy memory. + */ +struct DynamicFreeNode +{ + x_size_t size; /* the size of dynamicAllocNode */ + uint32 prev_adj_size; /* the size of the previous adjacent node, (dynamic alloc node or dynamic free node */ + uint32 flag; /* |static_dynamic_region_flag[32-24]|ext_sram_idx[23-16]|res[15-8]|res[7-0]| */ + + struct DynamicFreeNode *next; + struct DynamicFreeNode *prev; +}; + +/** + * The structure is the heart of Dynamic memory. + */ +struct DynamicBuddyMemory +{ + + x_ubase dynamic_buddy_start; + x_ubase dynamic_buddy_end; + x_ubase active_memory; + x_ubase max_ever_usedmem; + x_ubase static_memory; + uint64 mm_total_size; /* record the total size of dynamic buddy memory */ + + struct DynamicAllocNode *mm_dynamic_start[1]; /* record the start boundary of dynamic buddy memory */ + struct DynamicAllocNode *mm_dynamic_end[1]; /* record the end boundary of dynamic buddy memory */ + struct DynamicFreeNode mm_freenode_list[MEM_LINKNRS]; /* multiple lists */ + struct DynamicBuddyMemoryDone *done; +}; + +/** + * The structure is for static memory mangement, such as SIZEOF_32B and SIZEOF_64B + */ +struct segment +{ + x_size_t block_size; /* record the size of static memory block */ + uint8 * freelist; /* list for all free static memory blocks */ + int block_total_count; /* total static memory blocks */ + int block_free_count; /* the remaining count of static memory blocks */ + struct StaticMemoryDone *done; +}; +/** + * The index of static memory blocks + */ +enum { + MM_SEGMENT_32B=0, + MM_SEGMENT_64B, + MM_SMALL_SEGMENTS +}; + +/** + * The structure is the operation of dynamic alloc node. + */ +struct DynamicAllocNodeDone +{ + int (*JudgeStaticOrDynamic)(struct DynamicAllocNode *address); + int (*JudgeAllocated)(struct DynamicAllocNode *memory_ptr); +}; + +struct ByteMemory +{ + struct DynamicBuddyMemory dynamic_buddy_manager; /* the manager of dynamic buddy memory */ + struct segment static_manager[MM_SMALL_SEGMENTS]; /* the manager of static memory */ + struct DynamicAllocNodeDone *done; +}; + +/** + * The structure is the operation of static memory. + */ +struct StaticMemoryDone +{ + void (*init)(struct ByteMemory *byte_memory); + void* (*malloc)(struct ByteMemory *byte_memory, x_size_t size); + void (*release)(void *pointer); +}; + +/** + * The structure is the operation of dynamic memory. + */ +struct DynamicBuddyMemoryDone +{ + void (*init)(struct DynamicBuddyMemory *dynamic_buddy, x_ubase dynamic_buddy_start,x_ubase dynamic_buddy_size); + void* (*malloc)(struct DynamicBuddyMemory *dynamic_buddy, x_size_t size, uint32 extsram_mask); + void (*release)(struct ByteMemory *byte_memory, void *pointer); + int (*JudgeLegal)(struct DynamicBuddyMemory *dynamic_buddy, void *pointer); +}; + + +static struct ByteMemory ByteManager; + +#ifdef SEPARATE_COMPILE +static struct ByteMemory UserByteManager; +#endif + +#ifdef MEM_EXTERN_SRAM +static struct ByteMemory ExtByteManager[EXTSRAM_MAX_NUM] = {0}; +#endif +/** + * This function determines whether the address is valid. + * + * @param dynamic_buddy + * @param pointer the memory address + * + * @return valid return RET_TRUE; or invalid, return 0. + */ +static int JudgeValidAddressRange(struct DynamicBuddyMemory *dynamic_buddy, void *pointer) +{ + NULL_PARAM_CHECK(dynamic_buddy); + NULL_PARAM_CHECK(pointer); + + /* the given address is between the physical start address and physical end address */ + if(((struct DynamicAllocNode *)pointer > dynamic_buddy->mm_dynamic_start[0]) && ((struct DynamicAllocNode *)pointer < dynamic_buddy->mm_dynamic_end[0])) { + return RET_TRUE; + } + /* invalid address */ + return 0; +} + +/** + * This function judges whether the memory address is in static or dynamic memory. + * + * @param address the given memory address + * + * @return the memory type, 1 on static memory area; 0 on dynamic memory area + */ +static int SmallMemTypeAlloc(struct DynamicAllocNode *address) +{ + NULL_PARAM_CHECK(address); + + if(address->flag & STATIC_BLOCK_MASK) { + return RET_TRUE; + } + + return 0; +} + +/** + * This function judges whether the memory block is allocated. + * + * @param memory_ptr the memory block to be judged + * + * @return the result, 1 on allocated node; 0 on release node + */ +static int MmAllocNode(struct DynamicAllocNode *memory_ptr) +{ + NULL_PARAM_CHECK(memory_ptr); + + if(memory_ptr->flag & ALLOC_BLOCK_MASK) { + return RET_TRUE; + } + return 0; +} + +static struct DynamicAllocNodeDone NodeDone = { + SmallMemTypeAlloc, + MmAllocNode, +}; + +/** + * This function calculates the dynamic buddy mm_freenode_list according the give memory size. + * + * @param size the memory size + * + * @return the mm_freenode_list index + */ +static int CaculateBuddyIndex(x_size_t size) +{ + int ndx = 0; + + if (size < MEM_HIGH_RANGE) { + size >>= MEM_LOW_SHIFT; + for (; size > 1; ndx++, size /= 2); + } else { + ndx = MEM_LINKNRS - 1; + } + return ndx; +} + +/** + * This function inserts freenode into dynamic buddy memory. + * + * @param dynamic_buddy the heart dynamic memory structure + * @param release_node the node to be released to dynamic_buddy + */ +static void AddNewNodeIntoBuddy(struct DynamicBuddyMemory *dynamic_buddy, struct DynamicFreeNode *release_node) +{ + int ndx = 0; + struct DynamicFreeNode *nextFreeNode = NONE; + struct DynamicFreeNode *prevFreeNode = NONE; + + NULL_PARAM_CHECK(dynamic_buddy); + NULL_PARAM_CHECK(release_node); + + /* calculate the index value */ + ndx = CaculateBuddyIndex(release_node->size); + + /* find the most suitable location, which is sorted by size */ + for (prevFreeNode = &dynamic_buddy->mm_freenode_list[ndx], nextFreeNode = dynamic_buddy->mm_freenode_list[ndx].next; + nextFreeNode && nextFreeNode->size && nextFreeNode->size < release_node->size; + prevFreeNode = nextFreeNode, nextFreeNode = nextFreeNode->next); + + /* insert the release_node into the linklist */ + prevFreeNode->next = release_node; + release_node->prev = prevFreeNode; + release_node->next = nextFreeNode; + + if (nextFreeNode) { + nextFreeNode->prev = release_node; + } +} + +/** + * This function initializes the structure of dynamic buddy memory. + * + * @param dynamic_buddy the heart buddy structure + * @param dynamic_buddy_start the physical start address of dynamic memory + * @param dynamic_buddy_size the size of dynamic memory + */ +static void InitBuddy(struct DynamicBuddyMemory *dynamic_buddy, x_ubase dynamic_buddy_start,x_ubase dynamic_buddy_size) +{ + struct DynamicFreeNode *node = NONE; + + NULL_PARAM_CHECK(dynamic_buddy); + + /* record the dynamic memory size */ + dynamic_buddy->mm_total_size += (uint64)dynamic_buddy_size; + + /* record the start boundary of dynamic buddy memory */ + dynamic_buddy->mm_dynamic_start[0] = PTR2ALLOCNODE(dynamic_buddy_start); + dynamic_buddy->mm_dynamic_start[0]->size = SIZEOF_DYNAMICALLOCNODE_MEM; + dynamic_buddy->mm_dynamic_start[0]->prev_adj_size = 0; + dynamic_buddy->mm_dynamic_start[0]->flag = DYNAMIC_BLOCK_MASK; + + /* the initialized free node */ + node =(struct DynamicFreeNode *) ((x_ubase)dynamic_buddy_start + SIZEOF_DYNAMICALLOCNODE_MEM); + node->size=(dynamic_buddy_size - 2* SIZEOF_DYNAMICALLOCNODE_MEM); + node->prev_adj_size= SIZEOF_DYNAMICALLOCNODE_MEM; + node->flag= 0; + + /* record the end boundary of dynamic buddy memory */ + dynamic_buddy->mm_dynamic_end[0] = PTR2ALLOCNODE((x_ubase)dynamic_buddy_start + (x_ubase)dynamic_buddy_size - SIZEOF_DYNAMICALLOCNODE_MEM); + dynamic_buddy->mm_dynamic_end[0]->size = SIZEOF_DYNAMICALLOCNODE_MEM; + dynamic_buddy->mm_dynamic_end[0]->prev_adj_size = node->size; + dynamic_buddy->mm_dynamic_end[0]->flag = DYNAMIC_BLOCK_MASK; + + /* insert node into dynamic buddy memory */ + AddNewNodeIntoBuddy(dynamic_buddy,node); +} + +/** + * This function allocates dynamic memory from dynamic buddy memory. + * + * @param dynamic_buddy the heart dynamic buddy structure + * @param size the memory size to be allocated + * @param extsram_mask mask the memory region comes from ext sram + * + * @return pointer address on success; NULL on failure + */ +static void* BigMemMalloc(struct DynamicBuddyMemory *dynamic_buddy, x_size_t size, uint32 extsram_mask) +{ + int ndx = 0; + uint32 allocsize = 0; + void *result = NONE; + struct DynamicFreeNode *node = NONE; + + NULL_PARAM_CHECK(dynamic_buddy); + + /* calculate the real size */ + allocsize = size + SIZEOF_DYNAMICALLOCNODE_MEM; + /* if the size exceeds the upper limit, return MEM_LINKNRS - 1 */ + if (allocsize >= MEM_HIGH_RANGE) { + ndx = MEM_LINKNRS - 1; + } else { + /* convert the request size into a linklist index */ + ndx = CaculateBuddyIndex(allocsize); + } + + /* best-fit method */ + for (node = dynamic_buddy->mm_freenode_list[ndx].next; + (ndx < MEM_LINKNRS ) && (node->size < allocsize); + node = node->next) { + ndx++; + }; + /* get the best-fit freeNode */ + if (node && (node->size >= allocsize)) { + struct DynamicFreeNode *remainder; + struct DynamicFreeNode *next; + uint32 remaining; + + node->prev->next = node->next; + if (node->next) { + node->next->prev = node->prev; + } + + remaining = node->size - allocsize; + if (remaining >= MEM_LOW_RANGE){ + next = PTR2FREENODE(((char *)node) + node->size); + + /* create the remainder node */ + remainder = PTR2FREENODE(((char *)node) + allocsize); + remainder->size = remaining; + + remainder->prev_adj_size = allocsize; + remainder->flag = 0; + + /* adjust the size of the node */ + node->size = allocsize; + next->prev_adj_size = remaining; + + /* insert the remainder freeNode back into the dynamic buddy memory */ + AddNewNodeIntoBuddy(dynamic_buddy, remainder); + } + + /* handle the case of an exact size match */ + + node->flag = extsram_mask; + result = (void *)((char *)node + SIZEOF_DYNAMICALLOCNODE_MEM); + } + + /* failure allocation */ + if(result == NONE) { +#ifndef MEM_EXTERN_SRAM + KPrintf("%s: allocation failed, size %d.\n", __func__,allocsize); +#endif + return result; + } + +#ifdef MEM_STATS + /* statistic memory usage */ + dynamic_buddy->active_memory += node->size; + if(dynamic_buddy->active_memory > dynamic_buddy->max_ever_usedmem) + dynamic_buddy->max_ever_usedmem = dynamic_buddy->active_memory; +#endif + return result; +} + +/** + * This function will release dynamic memory. It is called by x_free function. + * + * @param pointer + */ +static void BigMemFree( struct ByteMemory *byte_memory, void *pointer) +{ + struct DynamicFreeNode *node = NONE; + struct DynamicFreeNode *prev = NONE; + struct DynamicFreeNode *next = NONE; + + NULL_PARAM_CHECK(byte_memory); + NULL_PARAM_CHECK(pointer); + + /* get the freeNode according the pointer address */ + node = PTR2FREENODE((char*)pointer - SIZEOF_DYNAMICALLOCNODE_MEM); + +#ifdef MEM_STATS + /* statistic memory information */ + byte_memory->dynamic_buddy_manager.active_memory -= node->size; +#endif + /* get the next sibling freeNode */ + next = PTR2FREENODE((char*)node+node->size); + + if(((next->flag & DYNAMIC_BLOCK_MASK) == 0)) { + struct DynamicAllocNode *andbeyond; + + andbeyond = PTR2ALLOCNODE((char*)next + next->size); + next->prev->next = next->next; + if(next->next) { + next->next->prev = next->prev; + } + + node->size += next->size; + andbeyond->prev_adj_size = node->size; + next = (struct DynamicFreeNode*)andbeyond; + } + /* get the prev sibling freeNode */ + prev = (struct DynamicFreeNode*)((char*)node - node->prev_adj_size ); + if((prev->flag & DYNAMIC_BLOCK_MASK)==0) { + + prev->prev->next=prev->next; + if(prev->next){ + prev->next->prev = prev->prev; + } + prev->size += node->size; + next->prev_adj_size = prev->size; + node = prev; + } + node->flag = 0; + + /* insert freeNode into dynamic buddy memory */ + AddNewNodeIntoBuddy(&byte_memory->dynamic_buddy_manager,node); +} + +static struct DynamicBuddyMemoryDone DynamicDone = { + InitBuddy, + BigMemMalloc, + BigMemFree, + JudgeValidAddressRange, +}; + +/** + * This function initializes the static segment struction. + * + * @param static_segment the static_segment to be initialized + */ +static void SmallMemInit(struct ByteMemory *byte_memory) +{ + register x_size_t offset = 0; + struct segment *item = NONE; + struct DynamicAllocNode *node = NONE; + + NULL_PARAM_CHECK(byte_memory); + + item = &byte_memory->static_manager[MM_SEGMENT_32B]; + + /* allocate memory zone for [32b] */ + item->freelist = byte_memory->dynamic_buddy_manager.done->malloc(&byte_memory->dynamic_buddy_manager, SMALL_SIZE_32B(SIZEOF_32B), DYNAMIC_BLOCK_NO_EXTMEM_MASK); + if(!item->freelist) { + KPrintf("%s: no memory for small memory[32B].\n",__func__); + item->block_free_count = 0; + return; + } + + /* initialize the attributes of static_segment_32B */ + item->block_size = SIZEOF_32B; + item->block_total_count = SMALL_NUMBER_32B; + item->block_free_count = SMALL_NUMBER_32B; + + for(offset = 0; offset < item->block_total_count; offset++) { + node = PTR2ALLOCNODE((char*)item->freelist + offset * (SIZEOF_32B + SIZEOF_DYNAMICALLOCNODE_MEM)); + node->size =(x_size_t) ((char*)item->freelist + (offset + 1) * (SIZEOF_32B + SIZEOF_DYNAMICALLOCNODE_MEM)); + node->flag = STATIC_BLOCK_MASK; + } + node->size = NONE; + + item = &byte_memory->static_manager[MM_SEGMENT_64B]; + + /* allocate memory zone for [64B] */ + item->freelist = byte_memory->dynamic_buddy_manager.done->malloc(&byte_memory->dynamic_buddy_manager, SMALL_SIZE_64B(SIZEOF_64B),DYNAMIC_BLOCK_NO_EXTMEM_MASK); + if(!item->freelist) { + KPrintf("%s: no memory for small memory[64B].\n",__func__); + return; + } + + /* initialize the attributes of static_segment_64B */ + item->block_size = SIZEOF_64B; + item->block_total_count = SMALL_NUMBER_64B; + item->block_free_count = SMALL_NUMBER_64B; + + for(offset = 0; offset < item->block_total_count; offset++) { + node = PTR2ALLOCNODE((char*)item->freelist + offset * (SIZEOF_64B + SIZEOF_DYNAMICALLOCNODE_MEM)); + node->size =(x_size_t) ((char*)item->freelist + (offset + 1) * (SIZEOF_64B + SIZEOF_DYNAMICALLOCNODE_MEM)); + node->flag = STATIC_BLOCK_MASK; + } + node->size = NONE; + +#ifdef MEM_STATS + /* statistic static memory information */ + byte_memory->dynamic_buddy_manager.static_memory = SMALL_SIZE_64B(SIZEOF_64B) + SMALL_SIZE_32B(SIZEOF_32B); +#endif +} + +/** + * + * This function will release the static memory block to static segment. + * + * @param pointer the memory to be released + */ +static void SmallMemFree(void *pointer) +{ + struct segment *static_segment = NONE; + struct DynamicAllocNode *node = NONE; + + NULL_PARAM_CHECK(pointer); + + /* get the allocNode */ + node = PTR2ALLOCNODE((char*)pointer-SIZEOF_DYNAMICALLOCNODE_MEM); + static_segment = (struct segment*)(x_size_t)node->size; + + /* update the statistic information of static_segment */ + node->size = (x_size_t)static_segment->freelist; + static_segment->freelist = (uint8 *)node; + static_segment->block_free_count++; + + /* parameter detection */ + CHECK(static_segment->block_free_count <= static_segment->block_total_count); +} + +/** + * This funcation allocates a static memory block from static segment. + * + * @param static_segment the heart static segment structure to allocate static memory + * @param size the size to be allocated + * + * @return pointer address on success; NULL on failure + */ +static void *SmallMemMalloc(struct ByteMemory *byte_memory, x_size_t size) +{ + uint8 i = 0; + void *result = NONE; + struct DynamicAllocNode *node = NONE; + struct segment *static_segment = NONE; + + NULL_PARAM_CHECK(byte_memory); + + if (size == SIZEOF_32B) + static_segment = &byte_memory->static_manager[0]; + else + static_segment = &byte_memory->static_manager[1]; + + /* current static segment has free static memory block */ + if(static_segment->block_free_count>0) { + /* get the head static memory block */ + result = static_segment->freelist; + node = PTR2ALLOCNODE(static_segment->freelist); + node->flag = STATIC_BLOCK_MASK; + + /* update the statistic information of static segment */ + static_segment->freelist = (uint8 *)(long)(node->size); + static_segment->block_free_count--; + node->size = (long)static_segment; + } + + if(result) { + /* return static memory block */ + return (char*)result + SIZEOF_DYNAMICALLOCNODE_MEM; + } + + /* the static memory block is exhausted, now turn to dynamic buddy memory for allocation. */ + result = byte_memory->dynamic_buddy_manager.done->malloc(&byte_memory->dynamic_buddy_manager, size, DYNAMIC_BLOCK_NO_EXTMEM_MASK); +#ifdef MEM_EXTERN_SRAM + if(NONE == result) { + for(i = 0; i < EXTSRAM_MAX_NUM; i++) { + if(NONE != ExtByteManager[i].done) { + result = ExtByteManager[i].dynamic_buddy_manager.done->malloc(&ExtByteManager[i].dynamic_buddy_manager, size, DYNAMIC_BLOCK_EXTMEMn_MASK(i + 1)); + if (result){ + CHECK(ExtByteManager[i].dynamic_buddy_manager.done->JudgeLegal(&ExtByteManager[i].dynamic_buddy_manager, ret - SIZEOF_DYNAMICALLOCNODE_MEM)); + break; + } + } + } + } +#endif + return result; +} + +static struct StaticMemoryDone StaticDone = { + SmallMemInit, + SmallMemMalloc, + SmallMemFree, +}; + +/** + * This function is provided to allocate memory block. + * + * @param size the memory size to be allocated + * + * @return pointer on success; NULL on failure + */ +void *x_malloc(x_size_t size) +{ + uint8 i = 0; + void *ret = NONE; + register x_base lock = 0; + + /* parameter detection */ + +#ifdef MEM_EXTERN_SRAM + /* parameter detection */ + if(size == 0 ){ + return NONE; + } + if((size > ByteManager.dynamic_buddy_manager.dynamic_buddy_end - ByteManager.dynamic_buddy_manager.dynamic_buddy_start - ByteManager.dynamic_buddy_manager.active_memory)){ + lock = CriticalAreaLock(); + /* alignment */ + size = ALIGN_MEN_UP(size, MEM_ALIGN_SIZE); + goto try_extmem; + } + +#else + /* parameter detection */ + if((size == 0) || (size > ByteManager.dynamic_buddy_manager.dynamic_buddy_end - ByteManager.dynamic_buddy_manager.dynamic_buddy_start - ByteManager.dynamic_buddy_manager.active_memory)) + return NONE; +#endif + /* hold lock before allocation */ + lock = CriticalAreaLock(); + /* alignment */ + size = ALIGN_MEN_UP(size, MEM_ALIGN_SIZE); + /* determine allocation operation from static segments or dynamic buddy memory */ +#ifdef KERNEL_SMALL_MEM_ALLOC + if(size <= SIZEOF_32B) { + ret = ByteManager.static_manager[0].done->malloc(&ByteManager,SIZEOF_32B); + } else if(size <= SIZEOF_64B) { + ret = ByteManager.static_manager[1].done->malloc(&ByteManager,SIZEOF_64B); + } else +#endif + { + ret = ByteManager.dynamic_buddy_manager.done->malloc(&ByteManager.dynamic_buddy_manager, size, DYNAMIC_BLOCK_NO_EXTMEM_MASK); + if(ret != NONE) + CHECK(ByteManager.dynamic_buddy_manager.done->JudgeLegal(&ByteManager.dynamic_buddy_manager, ret - SIZEOF_DYNAMICALLOCNODE_MEM)); + +#ifdef MEM_EXTERN_SRAM +try_extmem: + if(NONE == ret) { + for(i = 0; i < EXTSRAM_MAX_NUM; i++) { + if(NONE != ExtByteManager[i].done) { + ret = ExtByteManager[i].dynamic_buddy_manager.done->malloc(&ExtByteManager[i].dynamic_buddy_manager, size, DYNAMIC_BLOCK_EXTMEMn_MASK(i + 1)); + if (ret){ + CHECK(ExtByteManager[i].dynamic_buddy_manager.done->JudgeLegal(&ExtByteManager[i].dynamic_buddy_manager, ret - SIZEOF_DYNAMICALLOCNODE_MEM)); + break; + } + + } + } + } +#endif + } + /* release lock */ + CriticalAreaUnLock(lock); + return ret; +} + +/** + * This function is provided to re-allocate memory block. + * + * @param pointer the old memory pointer + * @param size the memory size to be re-allocated + * + * @return pointer on success; NULL on failure + */ +void *x_realloc(void *pointer, x_size_t size) +{ + x_size_t newsize = 0; + x_size_t oldsize = 0; + void *newmem = NONE; + struct DynamicAllocNode *oldnode = NONE; + + /* the given pointer is NULL */ + if (pointer == NONE) + return x_malloc(size); + + /* parameter detection */ + if (size == 0) { + x_free(pointer); + return NONE; + } + CHECK(ByteManager.dynamic_buddy_manager.done->JudgeLegal(&ByteManager.dynamic_buddy_manager,pointer)); + + /* alignment and calculate the real size */ + newsize = ALIGN_MEN_UP(size, MEM_ALIGN_SIZE); + newsize += SIZEOF_DYNAMICALLOCNODE_MEM; + + oldnode= PTR2ALLOCNODE((char*)pointer - SIZEOF_DYNAMICALLOCNODE_MEM); + CHECK(ByteManager.done->JudgeAllocated(oldnode)); + + /* achieve the old memory size */ + if(ByteManager.done->JudgeStaticOrDynamic(oldnode)) { + oldsize = ((struct segment*)(long)(oldnode->size))->block_size; + } else { + oldsize = oldnode->size - SIZEOF_DYNAMICALLOCNODE_MEM; + } + + /* allocate new memory */ + newmem = x_malloc(size); + if(newmem == NONE) { + return NONE; + } + + /* copy the old memory and then release old memory pointer */ + memcpy((char*)newmem, (char*) pointer,size > oldsize ? oldsize : size); + x_free(pointer); + + return newmem; +} + +/** + * This function will allocate memory blocks and then clear the memory. + * + * @param count the number of memory blocks + * @param size the size of a memory block + * + * @return pointer on success; NULL on failure + */ +void *x_calloc(x_size_t count, x_size_t size) +{ + void *p = NONE; + + /* parameter detection */ + if(count * size > ByteManager.dynamic_buddy_manager.dynamic_buddy_end - ByteManager.dynamic_buddy_manager.dynamic_buddy_start - ByteManager.dynamic_buddy_manager.active_memory) + return NONE; + + /* calls x_malloc to allocate count * size memory */ + p = x_malloc(count * size); + + /* zero the memory */ + if (p) + memset((char*)p, 0, count * size); + + return p; +} + +/** + * This function is provided to release memory block. + * + * @param pointer the memory to be released + */ +void x_free(void *pointer) +{ + x_base lock = 0; + struct DynamicAllocNode *node = NONE; + + /* parameter detection */ + if (pointer == NONE) + return ; + + CHECK(ByteManager.dynamic_buddy_manager.done->JudgeLegal(&ByteManager.dynamic_buddy_manager,pointer)); + + /* hold lock before release */ + lock = CriticalAreaLock(); + node = PTR2ALLOCNODE((char*)pointer-SIZEOF_DYNAMICALLOCNODE_MEM); + CHECK(ByteManager.done->JudgeAllocated(node)); + + /* judge release the memory block ro static_segment or dynamic buddy memory */ +#ifdef KERNEL_SMALL_MEM_ALLOC + if(node->flag & STATIC_BLOCK_MASK) { + ByteManager.static_manager->done->release(pointer); + } else +#endif + { +#ifdef MEM_EXTERN_SRAM + /* judge the pointer is not malloced from extern memory*/ + if(0 == (node->flag & 0xFF0000)) { + ByteManager.dynamic_buddy_manager.done->release(&ByteManager,pointer); + } + + /* judge the pointer is malloced from extern memory*/ + if(0 != (node->flag & 0xFF0000)) { + ExtByteManager[((node->flag & 0xFF0000) >> 16) - 1].dynamic_buddy_manager.done->release(&ExtByteManager[((node->flag & 0xFF0000) >> 16) - 1],pointer); + } +#else + ByteManager.dynamic_buddy_manager.done->release(&ByteManager,pointer); +#endif + } + /* release the lock */ + CriticalAreaUnLock(lock); +} + +#ifdef MEM_EXTERN_SRAM +/** + * This function initializes the dynamic buddy memory of extern sram. + * + * @param start_phy_address the start physical address for static and dynamic memory + * @param end_phy_address the end physical address for static and dynamic memory + * @param extsram_idx the idx of extsram chip + */ +void ExtSramInitBoardMemory(void *start_phy_address, void *end_phy_address, uint8 extsram_idx) +{ + register x_size_t offset = 0; + + NULL_PARAM_CHECK(start_phy_address); + NULL_PARAM_CHECK(end_phy_address); + + KDEBUG_NOT_IN_INTERRUPT; + struct DynamicBuddyMemory *uheap = &ExtByteManager[extsram_idx].dynamic_buddy_manager; + + /* align begin and end addr to page */ + ExtByteManager[extsram_idx].dynamic_buddy_manager.dynamic_buddy_start = ALIGN_MEN_UP((x_ubase)start_phy_address, MM_PAGE_SIZE); + ExtByteManager[extsram_idx].dynamic_buddy_manager.dynamic_buddy_end = ALIGN_MEN_DOWN((x_ubase)end_phy_address, MM_PAGE_SIZE); + KPrintf("%s: 0x%x-0x%x extsram_idx = %d\n",__func__,ExtByteManager[extsram_idx].dynamic_buddy_manager.dynamic_buddy_start,ExtByteManager[extsram_idx].dynamic_buddy_manager.dynamic_buddy_end, extsram_idx); + + /* parameter detection */ + if (ExtByteManager[extsram_idx].dynamic_buddy_manager.dynamic_buddy_start >= ExtByteManager[extsram_idx].dynamic_buddy_manager.dynamic_buddy_end) { + KPrintf("ExtSramInitBoardMemory, wrong address[0x%x - 0x%x]\n", + (x_ubase)start_phy_address, (x_ubase)end_phy_address); + return; + } + + uheap->mm_total_size = 0; + memset(uheap->mm_freenode_list, 0, SIZEOF_XSFREENODE_MEM * MEM_LINKNRS); + + /* initialize the freeNodeList */ + for (offset = 1; offset < MEM_LINKNRS; offset++) { + uheap->mm_freenode_list[offset - 1].next = &uheap->mm_freenode_list[offset]; + uheap->mm_freenode_list[offset].prev = &uheap->mm_freenode_list[offset - 1]; + } + + ExtByteManager[extsram_idx].dynamic_buddy_manager.done = &DynamicDone; + ExtByteManager[extsram_idx].done = &NodeDone; + + + /* dynamic buddy memory initialization */ + ExtByteManager[extsram_idx].dynamic_buddy_manager.done->init(&ExtByteManager[extsram_idx].dynamic_buddy_manager, ExtByteManager[extsram_idx].dynamic_buddy_manager.dynamic_buddy_start, ExtByteManager[extsram_idx].dynamic_buddy_manager.dynamic_buddy_end - ExtByteManager[extsram_idx].dynamic_buddy_manager.dynamic_buddy_start); +} +#endif + +/** + * This function initializes the static segments and dynamic buddy memory structures. + * + * @param start_phy_address the start physical address for static and dynamic memory + * @param end_phy_address the end physical address for static and dynamic memory + */ +void InitBoardMemory(void *start_phy_address, void *end_phy_address) +{ + register x_size_t offset = 0; + + NULL_PARAM_CHECK(start_phy_address); + NULL_PARAM_CHECK(end_phy_address); + + KDEBUG_NOT_IN_INTERRUPT; + struct DynamicBuddyMemory *mheap = &ByteManager.dynamic_buddy_manager; + + /* align begin and end addr to page */ + ByteManager.dynamic_buddy_manager.dynamic_buddy_start = ALIGN_MEN_UP((x_ubase)start_phy_address, MM_PAGE_SIZE); + ByteManager.dynamic_buddy_manager.dynamic_buddy_end = ALIGN_MEN_DOWN((x_ubase)end_phy_address, MM_PAGE_SIZE); + //KPrintf("%s: 0x%x-0x%x \n",__func__,ByteManager.dynamic_buddy_manager.dynamic_buddy_start,ByteManager.dynamic_buddy_manager.dynamic_buddy_end); + + /* parameter detection */ + if (ByteManager.dynamic_buddy_manager.dynamic_buddy_start >= ByteManager.dynamic_buddy_manager.dynamic_buddy_end) { + //KPrintf("InitBoardMemory, wrong address[0x%x - 0x%x]\n", (x_ubase)start_phy_address, (x_ubase)end_phy_address); + return; + } + + mheap->mm_total_size = 0; + memset(mheap->mm_freenode_list, 0, SIZEOF_XSFREENODE_MEM * MEM_LINKNRS); + + /* initialize the freeNodeList */ + for (offset = 1; offset < MEM_LINKNRS; offset++) { + mheap->mm_freenode_list[offset - 1].next = &mheap->mm_freenode_list[offset]; + mheap->mm_freenode_list[offset].prev = &mheap->mm_freenode_list[offset - 1]; + } + + ByteManager.dynamic_buddy_manager.done = &DynamicDone; + ByteManager.static_manager[MM_SEGMENT_32B].done = &StaticDone; + ByteManager.static_manager[MM_SEGMENT_64B].done = &StaticDone; + ByteManager.done = &NodeDone; + + + /* dynamic buddy memory initialization */ + ByteManager.dynamic_buddy_manager.done->init(&ByteManager.dynamic_buddy_manager, ByteManager.dynamic_buddy_manager.dynamic_buddy_start, ByteManager.dynamic_buddy_manager.dynamic_buddy_end - ByteManager.dynamic_buddy_manager.dynamic_buddy_start); + + /* dynamic static segments initialization */ +#ifdef KERNEL_SMALL_MEM_ALLOC + ByteManager.static_manager->done->init(&ByteManager); +#endif +} + +#ifdef SEPARATE_COMPILE + +/** + * This function is provided to allocate user memory block. + * + * @param size the memory size to be allocated + * + * @return pointer on success; NULL on failure + */ +void *x_umalloc(x_size_t size) +{ + uint8 i = 0; + void *ret = NONE; + register x_base lock = 0; + + +#ifdef MEM_EXTERN_SRAM + /* parameter detection */ + if(size == 0 ){ + return NONE; + } + if((size > ByteManager.dynamic_buddy_manager.dynamic_buddy_end - ByteManager.dynamic_buddy_manager.dynamic_buddy_start - ByteManager.dynamic_buddy_manager.active_memory)){ + lock = CriticalAreaLock(); + /* alignment */ + size = ALIGN_MEN_UP(size, MEM_ALIGN_SIZE); + goto try_extmem; + } + +#else + /* parameter detection */ + if((size == 0) || (size > UserByteManager.dynamic_buddy_manager.dynamic_buddy_end - UserByteManager.dynamic_buddy_manager.dynamic_buddy_start - UserByteManager.dynamic_buddy_manager.active_memory)) + return NONE; +#endif + + /* hold lock before allocation */ + lock = CriticalAreaLock(); + /* alignment */ + size = ALIGN_MEN_UP(size, MEM_ALIGN_SIZE); + ret = UserByteManager.dynamic_buddy_manager.done->malloc(&UserByteManager.dynamic_buddy_manager,size,DYNAMIC_BLOCK_NO_EXTMEM_MASK); + if(ret != NONE) + CHECK(UserByteManager.dynamic_buddy_manager.done->JudgeLegal(&UserByteManager.dynamic_buddy_manager, ret - SIZEOF_DYNAMICALLOCNODE_MEM)); + + +#ifdef MEM_EXTERN_SRAM +try_extmem: + if(NONE == ret) { + for(i = 0; i < EXTSRAM_MAX_NUM; i++) { + if(NONE != ExtByteManager[i].done) { + ret = ExtByteManager[i].dynamic_buddy_manager.done->malloc(&ExtByteManager[i].dynamic_buddy_manager, size, DYNAMIC_BLOCK_EXTMEMn_MASK(i + 1)); + if (ret) { + CHECK(ExtByteManager[i].dynamic_buddy_manager.done->JudgeLegal(&ExtByteManager[i].dynamic_buddy_manager, ret - SIZEOF_DYNAMICALLOCNODE_MEM)); + break; + } + } + } + } +#endif + /* release lock */ + CriticalAreaUnLock(lock); + return ret; +} + +/** + * This function is provided to re-allocate memory block. + * + * @param pointer the old memory pointer + * @param size the memory size to be re-allocated + * + * @return pointer on success; NULL on failure + */ +void *x_urealloc(void *pointer, x_size_t size) +{ + x_size_t newsize = 0; + x_size_t oldsize = 0; + void *newmem = NONE; + struct DynamicAllocNode *oldnode = NONE; + + /* the given pointer is NULL */ + if (pointer == NONE) + return x_umalloc(size); + + /* parameter detection */ + if (size == 0) { + x_ufree(pointer); + return NONE; + } + CHECK(UserByteManager.dynamic_buddy_manager.done->JudgeLegal(&UserByteManager.dynamic_buddy_manager,pointer)); + + /* alignment and calculate the real size */ + newsize = ALIGN_MEN_UP(size, MEM_ALIGN_SIZE); + newsize += SIZEOF_DYNAMICALLOCNODE_MEM; + + oldnode= PTR2ALLOCNODE((char*)pointer - SIZEOF_DYNAMICALLOCNODE_MEM); + CHECK(UserByteManager.done->JudgeAllocated(oldnode)); + + /* achieve the old memory size */ + if(UserByteManager.done->JudgeStaticOrDynamic(oldnode)) { + oldsize = ((struct segment*)(oldnode->size))->block_size; + } else { + oldsize = oldnode->size - SIZEOF_DYNAMICALLOCNODE_MEM; + } + + /* allocate new memory */ + newmem = x_umalloc(size); + if(newmem == NONE) { + return NONE; + } + + /* copy the old memory and then release old memory pointer */ + memcpy((char*)newmem, (char*) pointer,size > oldsize ? oldsize : size); + x_ufree(pointer); + + return newmem; +} + +/** + * This function will allocate memory blocks and then clear the memory. + * + * @param count the number of memory blocks + * @param size the size of a memory block + * + * @return pointer on success; NULL on failure + */ +void *x_ucalloc(x_size_t count, x_size_t size) +{ + void *p = NONE; + + /* parameter detection */ + if(count * size > UserByteManager.dynamic_buddy_manager.dynamic_buddy_end - UserByteManager.dynamic_buddy_manager.dynamic_buddy_start - UserByteManager.dynamic_buddy_manager.active_memory) + return NONE; + + /* calls x_malloc to allocate count * size memory */ + p = x_umalloc(count * size); + + /* zero the memory */ + if (p) + memset((char*)p, 0, count * size); + + return p; +} + +/** + * This function is provided to release memory block. + * + * @param pointer the memory to be released + */ +void x_ufree(void *pointer) +{ + x_base lock = 0; + struct DynamicAllocNode *node = NONE; + + /* parameter detection */ + if (pointer == NONE) + return ; + CHECK(UserByteManager.dynamic_buddy_manager.done->JudgeLegal(&UserByteManager.dynamic_buddy_manager,pointer)); + + /* hold lock before release */ + lock = CriticalAreaLock(); + node = PTR2ALLOCNODE((char*)pointer-SIZEOF_DYNAMICALLOCNODE_MEM); + CHECK(UserByteManager.done->JudgeAllocated(node)); + +#ifdef MEM_EXTERN_SRAM + /* judge the pointer is not malloced from extern memory*/ + if(0 == (node->flag & 0xFF0000)) { + UserByteManager.dynamic_buddy_manager.done->release(&ByteManager,pointer); + } + + /* judge the pointer is malloced from extern memory*/ + if(0 != (node->flag & 0xFF0000)) { + ExtByteManager[((node->flag & 0xFF0000) >> 16) - 1].dynamic_buddy_manager.done->release(&ExtByteManager[((node->flag & 0xFF0000) >> 16) - 1],pointer); + } + +#else + UserByteManager.dynamic_buddy_manager.done->release(&UserByteManager,pointer); +#endif + /* release the lock */ + CriticalAreaUnLock(lock); +} + +/** + * This function initializes the static segments and dynamic buddy memory structures. + * + * @param start_phy_address the start physical address for static and dynamic memory + * @param end_phy_address the end physical address for static and dynamic memory + */ +void UserInitBoardMemory(void *start_phy_address, void *end_phy_address) +{ + register x_size_t offset = 0; + + NULL_PARAM_CHECK(start_phy_address); + NULL_PARAM_CHECK(end_phy_address); + + KDEBUG_NOT_IN_INTERRUPT; + struct DynamicBuddyMemory *uheap = &UserByteManager.dynamic_buddy_manager; + + /* align begin and end addr to page */ + UserByteManager.dynamic_buddy_manager.dynamic_buddy_start = ALIGN_MEN_UP((x_ubase)start_phy_address, MM_PAGE_SIZE); + UserByteManager.dynamic_buddy_manager.dynamic_buddy_end = ALIGN_MEN_DOWN((x_ubase)end_phy_address, MM_PAGE_SIZE); + KPrintf("%s: 0x%x-0x%x \n",__func__,UserByteManager.dynamic_buddy_manager.dynamic_buddy_start,UserByteManager.dynamic_buddy_manager.dynamic_buddy_end); + + /* parameter detection */ + if (UserByteManager.dynamic_buddy_manager.dynamic_buddy_start >= UserByteManager.dynamic_buddy_manager.dynamic_buddy_end) { + KPrintf("InitBoardMemory, wrong address[0x%x - 0x%x]\n", + (x_ubase)start_phy_address, (x_ubase)end_phy_address); + return; + } + + uheap->mm_total_size = 0; + memset(uheap->mm_freenode_list, 0, SIZEOF_XSFREENODE_MEM * MEM_LINKNRS); + + /* initialize the freeNodeList */ + for (offset = 1; offset < MEM_LINKNRS; offset++) { + uheap->mm_freenode_list[offset - 1].next = &uheap->mm_freenode_list[offset]; + uheap->mm_freenode_list[offset].prev = &uheap->mm_freenode_list[offset - 1]; + } + + UserByteManager.dynamic_buddy_manager.done = &DynamicDone; + UserByteManager.done = &NodeDone; + + + /* dynamic buddy memory initialization */ + UserByteManager.dynamic_buddy_manager.done->init(&UserByteManager.dynamic_buddy_manager, UserByteManager.dynamic_buddy_manager.dynamic_buddy_start, UserByteManager.dynamic_buddy_manager.dynamic_buddy_end - UserByteManager.dynamic_buddy_manager.dynamic_buddy_start); + +} + +#endif + +#ifdef MEM_STATS + +/** + * This function obtains the statistic information about memory + * + * @param total_memory the total memory + * @param used_memory the meory being used + * @param max_used_memory the max allocated memory + */ +void MemoryInfo(uint32 *total_memory, uint32 *used_memory, uint32 *max_used_memory) +{ + if (NONE != total_memory) + *total_memory = ByteManager.dynamic_buddy_manager.dynamic_buddy_end - ByteManager.dynamic_buddy_manager.dynamic_buddy_start; + + if (NONE != used_memory) + *used_memory = ByteManager.dynamic_buddy_manager.active_memory; + + if (NONE != max_used_memory) + *max_used_memory = ByteManager.dynamic_buddy_manager.max_ever_usedmem; +} + +#ifdef TOOL_SHELL +#include + +void ShowBuddy(); +void ShowMemory(void); +/** + * This function will list the statistic information about memory. + */ +void ShowMemory(void) +{ + int i = 0; + KPrintf("total memory: %d\n", ByteManager.dynamic_buddy_manager.dynamic_buddy_end - ByteManager.dynamic_buddy_manager.dynamic_buddy_start); + KPrintf("used memory : %d\n", ByteManager.dynamic_buddy_manager.active_memory); + KPrintf("maximum allocated memory: %d\n", ByteManager.dynamic_buddy_manager.max_ever_usedmem); + KPrintf("total cache szie: %d, %d/%d[32B],%d/%d[64B]\n", ByteManager.dynamic_buddy_manager.static_memory,ByteManager.static_manager[0].block_free_count,SMALL_NUMBER_32B,ByteManager.static_manager[1].block_free_count,SMALL_NUMBER_64B); +#ifdef MEM_EXTERN_SRAM + for(i = 0; i < EXTSRAM_MAX_NUM; i++) { + if(NONE != ExtByteManager[i].done){ + KPrintf("\nlist extern sram[%d] memory information\n\n",i); + KPrintf("extern sram total memory: %d\n", ExtByteManager[i].dynamic_buddy_manager.dynamic_buddy_end - ExtByteManager[i].dynamic_buddy_manager.dynamic_buddy_start); + KPrintf("extern sram used memory : %d\n", ExtByteManager[i].dynamic_buddy_manager.active_memory); + KPrintf("extern sram maximum allocated memory: %d\n", ExtByteManager[i].dynamic_buddy_manager.max_ever_usedmem); + } + } +#endif + ShowBuddy(); +} +SHELL_EXPORT_CMD(SHELL_CMD_PERMISSION(0)|SHELL_CMD_TYPE(SHELL_TYPE_CMD_FUNC)|SHELL_CMD_PARAM_NUM(0), + ShowMemory,ShowMemory,list memory usage information); +/** + * This function will list the freeNodeList information on dynamic buddy memory. + */ +void ShowBuddy(void) +{ + + int i = 0; + int lock = 0; + struct DynamicFreeNode *debug = NONE; + + lock = CriticalAreaLock(); + KPrintf("\n\033[41;1mlist memory information\033[0m\n", __func__); + for(int level = 0; level < MEM_LINKNRS; level++) { + KPrintf("%s level [%d],memory size[2^%d] \n",__func__, level,level +6); + for (debug = &ByteManager.dynamic_buddy_manager.mm_freenode_list[level]; ; ) { + if(debug->next) + { + debug = debug->next; + + if(debug->size > 0) + KPrintf(" [current node %x,next node %x, size %u, flag %x]\n",debug, debug->next,debug->size,debug->flag); + else + KPrintf(" \n"); + } + if(debug->size == 0 || NONE == debug->next) + break; + }; + } + + +#ifdef MEM_EXTERN_SRAM + KPrintf("\n\033[41;1mlist extern memory information\033[0m\n"); + for(i = 0; i < EXTSRAM_MAX_NUM; i++) { + if(NONE != ExtByteManager[i].done){ + KPrintf("\nlist extern sram[%d] memory information\n\n",i); + for(int lev = 0; lev < MEM_LINKNRS; lev++) { + KPrintf("\n %s level [%d],memory size[2^%d] \n",__func__, lev,lev +6); + for (debug = & ExtByteManager[i].dynamic_buddy_manager.mm_freenode_list[lev]; ; ) { + if(debug->next) + { + debug = debug->next; + + if(debug->size > 0) + KPrintf(" [current node %x,next node %x, size %u, flag %x]\n",debug, debug->next,debug->size,debug->flag); + else + KPrintf(" \n"); + } + if(debug->size == 0 || NONE == debug->next) + break; + } + } + } + } + +#endif + CriticalAreaUnLock(lock); +} +SHELL_EXPORT_CMD(SHELL_CMD_PERMISSION(0)|SHELL_CMD_TYPE(SHELL_TYPE_CMD_FUNC)|SHELL_CMD_PARAM_NUM(0), +ShowBuddy,ShowBuddy,list memory usage information); +#endif +#endif + diff --git a/Ubiquitous/XiZi/kernel/memory/gatherblock.c b/Ubiquitous/XiZi/kernel/memory/gatherblock.c new file mode 100644 index 0000000..a4a0d48 --- /dev/null +++ b/Ubiquitous/XiZi/kernel/memory/gatherblock.c @@ -0,0 +1,414 @@ +/* +* Copyright (c) 2020 AIIT XUOS Lab +* XiUOS is licensed under Mulan PSL v2. +* You can use this software according to the terms and conditions of the Mulan PSL v2. +* You may obtain a copy of Mulan PSL v2 at: +* http://license.coscl.org.cn/MulanPSL2 +* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, +* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, +* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. +* See the Mulan PSL v2 for more details. +*/ + +/** +* @file: gatherblock.c +* @brief: block memory management file +* @version: 1.0 +* @author: AIIT XUOS Lab +* @date: 2020/3/8 +* +*/ + +#include +#include + +#ifdef KERNEL_MEMBLOCK + +/* a global list, which record all the gatherblocks*/ +DoubleLinklistType xiaoshan_memgather_head = {&xiaoshan_memgather_head, &xiaoshan_memgather_head}; + +/** + * This function initializes a gather block memory structure. + * + * @param gm_handler the gatherblock structure + * @param gm_name the name of gatherblock + * @param begin_address the start address of gatherblock + * @param gm_size the total size of gatherblock + * @param one_block_size one block size in gatherblock + * + * @return EOK + */ +x_err_t InitMemGather(struct MemGather *gm_handler, const char *gm_name, void *begin_address, x_size_t gm_size, x_size_t one_block_size) +{ + x_base lock = 0; + register x_size_t off_block = 0; + register x_base critical_value = 0; + uint8 *block_ptr = NONE; + struct SysDoubleLinklistNode *list_entry = NONE; + + /* parameter detection */ + NULL_PARAM_CHECK(gm_handler); + NULL_PARAM_CHECK(gm_name); + NULL_PARAM_CHECK(begin_address); + + CHECK(gm_size >= 1 && one_block_size >= 1); + + lock = CriticalAreaLock(); + + /* try to find gatherblock object */ + for (list_entry = xiaoshan_memgather_head.node_next; + list_entry != &(xiaoshan_memgather_head); + list_entry = list_entry->node_next) { + GatherMemType gm; + + gm = SYS_DOUBLE_LINKLIST_ENTRY(list_entry, struct MemGather, m_link); + if (gm) { + CHECK(gm != gm_handler); + } + } + CriticalAreaUnLock(lock); + + /* set the type attribute of gatherblock object */ + gm_handler->m_kind = Cmpt_KindN_Static; + /* set the name of gatherblock object */ + strncpy(gm_handler->m_name, gm_name, NAME_NUM_MAX); + + critical_value = CriticalAreaLock(); + + /* insert gatherblock object into the global list */ + DoubleLinkListInsertNodeAfter(&xiaoshan_memgather_head, &(gm_handler->m_link)); + + CriticalAreaUnLock(critical_value); + + /* initialize the other attributes of gatherblock object */ + gm_handler->m_start_address = begin_address; + gm_handler->m_size = ALIGN_MEN_DOWN(gm_size, MEM_ALIGN_SIZE); + one_block_size = ALIGN_MEN_UP(one_block_size, MEM_ALIGN_SIZE); + gm_handler->one_block_size = one_block_size; + gm_handler->block_total_number = gm_handler->m_size / (gm_handler->one_block_size + sizeof(uint8 *)); + gm_handler->block_free_number = gm_handler->block_total_number; + + InitDoubleLinkList(&(gm_handler->wait_task)); + + /* links all the blocks in gatherblock object */ + block_ptr = (uint8 *)gm_handler->m_start_address; + for (off_block = 0; off_block < gm_handler->block_total_number; off_block ++) { + *(uint8 **)(block_ptr + off_block * (one_block_size + sizeof(uint8 *))) = + (uint8 *)(block_ptr + (off_block + 1) * (one_block_size + sizeof(uint8 *))); + } + + *(uint8 **)(block_ptr + (off_block - 1) * (one_block_size + sizeof(uint8 *))) = + NONE; + + gm_handler->m_block_link = block_ptr; + + return EOK; +} + + + +/** + * This function will remove the gatherblock from the global list, which is created by MemGatherInit function + * + * @param gm_handler the gatherblock to be removed + * + * @return EOK + */ +x_err_t RemoveMemGather(struct MemGather *gm_handler) +{ + register x_ubase critical_value = 0; + struct TaskDescriptor *task = NONE; + + /* parameter detection */ + NULL_PARAM_CHECK(gm_handler); + + CHECK((gm_handler->m_kind & Cmpt_KindN_Static)!=0); + + /* resume all the suspend tasks on gatherblock object */ + while (!IsDoubleLinkListEmpty(&(gm_handler->wait_task))) { + critical_value = CriticalAreaLock(); + + task = SYS_DOUBLE_LINKLIST_ENTRY(gm_handler->wait_task.node_next, struct TaskDescriptor, task_dync_sched_member.sched_link); + task->exstatus = -ERROR; + + KTaskWakeup(task->id.id); + + CriticalAreaUnLock(critical_value); + } + + /* set the type attribute */ + gm_handler->m_kind = 0; + + critical_value = CriticalAreaLock(); + + /* remove the gatherblock object from the global links */ + DoubleLinkListRmNode(&(gm_handler->m_link)); + + CriticalAreaUnLock(critical_value); + + return EOK; +} + + +/** + * This function will create a gatherblock object. + * + * @param gm_name the name of gatherblock + * @param block_number the number of blocks in gatherblock + * @param one_block_size one block size + * + * @return EOK on success; NONE on failure + */ +GatherMemType CreateMemGather(const char *gm_name, x_size_t block_number, x_size_t one_block_size) +{ + + register x_size_t off_block = 0; + register x_base critical_value = 0; + uint8 *block_ptr = NONE; + struct MemGather *gm_handler = NONE; + + KDEBUG_NOT_IN_INTERRUPT; + + /* parameter detection */ + NULL_PARAM_CHECK(gm_name); + CHECK(block_number >= 1 && one_block_size >= 1); + + KDEBUG_NOT_IN_INTERRUPT; + + /* allocate memory for gatherblock object */ + gm_handler = (struct MemGather *)KERNEL_MALLOC(sizeof(struct MemGather)); + + if (NONE == gm_handler) + return NONE; + /* clear the gatherblock object */ + memset(gm_handler, 0x0, sizeof(struct MemGather)); + /* set the name attribute */ + strncpy(gm_handler->m_name, gm_name, NAME_NUM_MAX); + /* set the flag attribute */ + gm_handler->m_sign = 0; + + critical_value = CriticalAreaLock(); + + /* insert gatherblock object into the global list */ + DoubleLinkListInsertNodeAfter(&xiaoshan_memgather_head, &(gm_handler->m_link)); + + CriticalAreaUnLock(critical_value); + + /* set the other attributes of gatherblock object */ + one_block_size = ALIGN_MEN_UP(one_block_size, MEM_ALIGN_SIZE); + gm_handler->one_block_size = one_block_size; + gm_handler->m_size = (one_block_size + sizeof(uint8 *)) * block_number; + + /* allocate memory for gather blocks */ + gm_handler->m_start_address = x_malloc((one_block_size + sizeof(uint8 *)) * block_number); + if (NONE == gm_handler->m_start_address) { + gm_handler->m_kind = 0; + critical_value = CriticalAreaLock(); + + /* remove the gatherblock object from the global links */ + DoubleLinkListRmNode(&(gm_handler->m_link)); + + CriticalAreaUnLock(critical_value); + + /* release the memory for gather block structure */ + KERNEL_FREE(gm_handler); + + return NONE; + } + + gm_handler->block_total_number = block_number; + gm_handler->block_free_number = gm_handler->block_total_number; + + InitDoubleLinkList(&(gm_handler->wait_task)); + + /* links all the gather blocks */ + block_ptr = (uint8 *)gm_handler->m_start_address; + for (off_block = 0; off_block < gm_handler->block_total_number; off_block ++) { + *(uint8 **)(block_ptr + off_block * (one_block_size + sizeof(uint8 *))) + = block_ptr + (off_block + 1) * (one_block_size + sizeof(uint8 *)); + } + + *(uint8 **)(block_ptr + (off_block - 1) * (one_block_size + sizeof(uint8 *))) + = NONE; + + gm_handler->m_block_link = block_ptr; + + return gm_handler; +} + +/** + * This function will delete a gatherblock object, which is created by MemGatherCreate function. + * + * @param gm_handler the gatherblock object to be deleted + * + * @return EOK + */ +x_err_t DeleteMemGather(GatherMemType gm_handler) +{ + register x_ubase critical_value = 0; + struct TaskDescriptor *task = NONE; + + KDEBUG_NOT_IN_INTERRUPT; + + /* parameter detection */ + NULL_PARAM_CHECK(gm_handler); + CHECK(((gm_handler->m_kind & Cmpt_KindN_Static)==0)); + + /* resume all the suspend tasks on gatherblock object */ + while (!IsDoubleLinkListEmpty(&(gm_handler->wait_task))) { + critical_value = CriticalAreaLock(); + + task = SYS_DOUBLE_LINKLIST_ENTRY(gm_handler->wait_task.node_next, struct TaskDescriptor, task_dync_sched_member.sched_link); + task->exstatus = -ERROR; + + KTaskWakeup(task->id.id); + + CriticalAreaUnLock(critical_value); + } + + /* release the memory for gather blocks */ + x_free(gm_handler->m_start_address); + + gm_handler->m_kind = 0; + + critical_value = CriticalAreaLock(); + + /* remove the gatherblock object from the global links */ + DoubleLinkListRmNode(&(gm_handler->m_link)); + + CriticalAreaUnLock(critical_value); + + /* release the memory for gather block structure */ + KERNEL_FREE(gm_handler); + return EOK; +} + +/** + * This function will allocate a data block from gatherblock object + * + * @param gm_handler the gatherblock object to get data block + * @param msec waiting time ,millisecond + * + * @return block pointer on success; NONE on failure + */ +void *AllocBlockMemGather(GatherMemType gm_handler, int32 msec) +{ + int32 wait_time = 0; + uint32 before_sleep = 0; + register x_base critical_value = 0; + uint8 *block_ptr = NONE; + struct TaskDescriptor *task = NONE; + + /* parameter detection */ + NULL_PARAM_CHECK(gm_handler); + + /* get descriptor of task */ + task = GetKTaskDescriptor(); + wait_time = CalculteTickFromTimeMs(msec); + + critical_value = CriticalAreaLock(); + /* no free gatherblock*/ + while (0 == gm_handler->block_free_number) { + if (wait_time == 0) { + CriticalAreaUnLock(critical_value); + + KUpdateExstatus(ETIMEOUT); + + return NONE; + } + + KDEBUG_NOT_IN_INTERRUPT; + + task->exstatus = EOK; + + /* suspend current task */ + SuspendKTask(task->id.id); + DoubleLinkListInsertNodeAfter(&(gm_handler->wait_task), &(task->task_dync_sched_member.sched_link)); + + if (wait_time > 0) { + before_sleep = CurrentTicksGain(); + /* start the timer */ + KTaskSetDelay(task,wait_time); + } + + CriticalAreaUnLock(critical_value); + + /* schedule */ + DO_KTASK_ASSIGN; + + if (EOK != task->exstatus) + return NONE; + + if (wait_time > 0) { + wait_time -= CurrentTicksGain() - before_sleep; + if (wait_time < 0) + wait_time = 0; + } + critical_value = CriticalAreaLock(); + } + /* decrease the number of free gatherblocks */ + gm_handler->block_free_number--; + + block_ptr = gm_handler->m_block_link; + NULL_PARAM_CHECK(block_ptr); + + /* set the block_list attribute of gather_block structure */ + gm_handler->m_block_link = *(uint8 **)block_ptr; + + *(uint8 **)block_ptr = (uint8 *)gm_handler; + + CriticalAreaUnLock(critical_value); + + HOOK(hook.mem.hook_GmAlloc, (gm_handler, (uint8 *)(block_ptr + sizeof(uint8 *)))); + + return (uint8 *)(block_ptr + sizeof(uint8 *)); +} + +/** + * This function will release a data block to gatherblock object + * + * @param data_block the data block to be released + */ +void FreeBlockMemGather(void *data_block) +{ + uint8 **block_ptr; + register x_base critical_value = 0; + struct MemGather *gm_handler = NONE; + struct TaskDescriptor *task = NONE; + + /* parameter detection */ + NULL_PARAM_CHECK(data_block); + + /* get gatherblock structure */ + block_ptr = (uint8 **)((uint8 *)data_block - sizeof(uint8 *)); + gm_handler = (struct MemGather *)*block_ptr; + + HOOK(hook.mem.hook_GmFree, (gm_handler, data_block)); + + critical_value = CriticalAreaLock(); + + /* increase the number of gatherblocks */ + gm_handler->block_free_number ++; + + *block_ptr = gm_handler->m_block_link; + /* set the block_list attribute of gather_block object */ + gm_handler->m_block_link = (uint8 *)block_ptr; + + if (!IsDoubleLinkListEmpty(&(gm_handler->wait_task))) { + task = SYS_DOUBLE_LINKLIST_ENTRY(gm_handler->wait_task.node_next, struct TaskDescriptor, task_dync_sched_member.sched_link); + task->exstatus = EOK; + + /* resume a suspend task */ + KTaskWakeup(task->id.id); + + CriticalAreaUnLock(critical_value); + + DO_KTASK_ASSIGN; + + return; + } + + CriticalAreaUnLock(critical_value); +} +#endif + diff --git a/Ubiquitous/XiZi/kernel/memory/isolation.c b/Ubiquitous/XiZi/kernel/memory/isolation.c new file mode 100644 index 0000000..29708d5 --- /dev/null +++ b/Ubiquitous/XiZi/kernel/memory/isolation.c @@ -0,0 +1,59 @@ +/* +* Copyright (c) 2020 AIIT XUOS Lab +* XiUOS is licensed under Mulan PSL v2. +* You can use this software according to the terms and conditions of the Mulan PSL v2. +* You may obtain a copy of Mulan PSL v2 at: +* http://license.coscl.org.cn/MulanPSL2 +* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, +* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, +* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. +* See the Mulan PSL v2 for more details. +*/ + +/** +* @file: isolation.c +* @brief: memory access structure definitions of ARM/RISCV +* @version: 1.0 +* @author: AIIT XUOS Lab +* @date: 2020/3/15 +* +*/ + +#include + +#ifdef TASK_ISOLATION + +#if defined(ARCH_ARM) && defined(SURPORT_MPU) + +struct Mpu *isolation = NONE; +struct MemoryAccessLimit mem_access = { + .Enable = MpuEnable , + .Disable = MpuDisable , + .Init = MpuInit , + .InitIsolation = NONE, + .AddRegion = NONE, + .ClearRegion = NONE , + .Free = NONE, + .Load = MpuLoad, + .FaultHandle = NONE, +}; +#endif + +#if defined(ARCH_RISCV) && defined(SURPORT_PMP) + +struct Pmp *isolation = NONE; +struct MemoryAccessLimit mem_access = { + .Enable = NONE , + .Disable = NONE , + .Init = NONE , + .InitIsolation = PmpInitIsolation, + .AddRegion = PmpAddTorRegion, + .ClearRegion = PmpClearRegion , + .Free = PmpFree, + .Load = PmpLoad, + .FaultHandle = PmpAccessFaultHandle, +}; + +#endif + +#endif \ No newline at end of file diff --git a/Ubiquitous/XiZi/kernel/thread/CriticalArea.c b/Ubiquitous/XiZi/kernel/thread/CriticalArea.c new file mode 100644 index 0000000..f313e30 --- /dev/null +++ b/Ubiquitous/XiZi/kernel/thread/CriticalArea.c @@ -0,0 +1,147 @@ +/* +* Copyright (c) 2020 AIIT XUOS Lab +* XiUOS is licensed under Mulan PSL v2. +* You can use this software according to the terms and conditions of the Mulan PSL v2. +* You may obtain a copy of Mulan PSL v2 at: +* http://license.coscl.org.cn/MulanPSL2 +* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, +* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, +* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. +* See the Mulan PSL v2 for more details. +*/ + +/** +* @file: critical area.c +* @brief: the critical area lock functions definitions +* @version: 1.0 +* @author: AIIT XUOS Lab +* @date: 2020/3/15 +* +*/ + +#ifndef __CRITICAL__AREA__ +#define __CRITICAL__AREA__ + +#include +#include +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + + +#ifdef ARCH_SMP + HwSpinlock _CriticalLock; + +/** + * This function will do OsAssign lock. + * + * @return lock + */ +x_base CriticalAreaLock(void) +{ + x_base lock = 0; + + lock = DisableLocalInterrupt(); + + if (Assign.smp_os_running_task[GetCpuId()]) { + if (Assign.smp_os_running_task[GetCpuId()]->task_smp_info.critical_lock_cnt == 0) { + Assign.assign_lock[GetCpuId()] ++; + HwLockSpinlock(&_CriticalLock); + } + + Assign.smp_os_running_task[GetCpuId()]->task_smp_info.critical_lock_cnt ++; + } + return lock; +} + + + +/** + * This function will do OsAssign unlock. + * + * @return lock + */ +void CriticalAreaUnLock(x_base lock) +{ + if (Assign.smp_os_running_task[GetCpuId()]) { + if (Assign.smp_os_running_task[GetCpuId()]->task_smp_info.critical_lock_cnt > 0) { + Assign.smp_os_running_task[GetCpuId()]->task_smp_info.critical_lock_cnt --; + } + + if (Assign.smp_os_running_task[GetCpuId()]->task_smp_info.critical_lock_cnt == 0) { + if(Assign.assign_lock[GetCpuId()] > 0) + Assign.assign_lock[GetCpuId()]--; + HwUnlockSpinlock(&_CriticalLock); + } + } + + EnableLocalInterrupt(lock); +} + +/** + * This function will get critical lock level. + * + * @return critical lock level + */ +uint16 GetOsAssignLockLevel(void) +{ + return Assign.smp_os_running_task[GetCpuId()]->task_smp_info.critical_lock_cnt; +} + +#else + +#include + +static int16 KTaskOsAssignLockNest; + +/** + * This function will get critical lock level. + * + * @return critical lock level + */ +uint16 GetOsAssignLockLevel(void) { + return KTaskOsAssignLockNest; +} + +inline void ResetCriticalAreaLock(void ) { + KTaskOsAssignLockNest = 0; +} +/** + * This function will do OsAssign lock. + * + * @return lock + */ +x_base CriticalAreaLock(void) { + x_base lock; + + lock = DISABLE_INTERRUPT(); + + KTaskOsAssignLockNest ++; + + return lock; +} + +/** + * This function will do OsAssign unlock. + * + * @return lock + */ +void CriticalAreaUnLock(x_base lock) { + if (KTaskOsAssignLockNest >= 1) { + KTaskOsAssignLockNest --; + } + + ENABLE_INTERRUPT(lock); +} + +#endif + +#ifdef __cplusplus +} +#endif + + +#endif \ No newline at end of file diff --git a/Ubiquitous/XiZi/kernel/thread/Makefile b/Ubiquitous/XiZi/kernel/thread/Makefile new file mode 100644 index 0000000..21cb561 --- /dev/null +++ b/Ubiquitous/XiZi/kernel/thread/Makefile @@ -0,0 +1,78 @@ +SRC_FILES := tick.c kservicetask.c zombierecycle.c init.c lock.c idle.c linklist.c isr.c console.c ktask.c id.c CriticalArea.c bitmap.c delay.c double_link.c single_link.c assignstat.c ktask_stat.c + +ifeq ($(CONFIG_KERNEL_SEMAPHORE),y) + SRC_FILES += semaphore.c +endif + +ifeq ($(CONFIG_KERNEL_MUTEX),y) + SRC_FILES += mutex.c +endif + +ifeq ($(CONFIG_KERNEL_EVENT),y) + SRC_FILES += event.c +endif + +ifeq ($(CONFIG_KERNEL_MESSAGEQUEUE),y) + SRC_FILES += msgqueue.c +endif + +ifeq ($(CONFIG_KERNEL_SOFTTIMER),y) + SRC_FILES += softtimer.c +endif + +ifeq ($(CONFIG_KERNEL_BANNER),y) + SRC_FILES += banner.c +endif + +ifeq ($(CONFIG_KERNEL_HOOK),y) + SRC_FILES += hook.c +endif + +ifeq ($(CONFIG_KERNEL_QUEUEMANAGE),y) + SRC_FILES += queue_manager.c + + ifeq ($(CONFIG_KERNEL_WORKQUEUE),y) + SRC_FILES += workqueue.c + endif + + ifeq ($(CONFIG_KERNEL_WAITQUEUE),y) + SRC_FILES += waitqueue.c + endif + + ifeq ($(CONFIG_KERNEL_DATAQUEUE),y) + SRC_FILES += data_queue.c + endif +endif + +ifeq ($(CONFIG_KERNEL_CIRCULAR_AREA),y) + SRC_FILES += circular_area.c +endif + +ifeq ($(CONFIG_KERNEL_AVL_TREE),y) + SRC_FILES += avl_tree.c +endif + + +ifeq ($(CONFIG_ARCH_SMP),y) + SRC_FILES += smp_assign.c +else + SRC_FILES += assign.c +endif + +ifeq ($(CONFIG_SCHED_POLICY_RR),y) + SRC_FILES += assign_roundrobin.c +endif + +ifeq ($(CONFIG_SCHED_POLICY_FIFO),y) + SRC_FILES += assign_fifo.c +endif + +ifeq ($(CONFIG_SCHED_POLICY_RR_REMAINSLICE),y) + SRC_FILES += assign_roundrobinremain.c +endif + +ifeq ($(CONFIG_USER_APPLICATION),y) + SRC_FILES += appstartup.c +endif + +include $(KERNEL_ROOT)/compiler.mk diff --git a/Ubiquitous/XiZi/kernel/thread/appstartup.c b/Ubiquitous/XiZi/kernel/thread/appstartup.c new file mode 100644 index 0000000..78d0443 --- /dev/null +++ b/Ubiquitous/XiZi/kernel/thread/appstartup.c @@ -0,0 +1,177 @@ +/* +* Copyright (c) 2020 AIIT XUOS Lab +* XiUOS is licensed under Mulan PSL v2. +* You can use this software according to the terms and conditions of the Mulan PSL v2. +* You may obtain a copy of Mulan PSL v2 at: +* http://license.coscl.org.cn/MulanPSL2 +* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, +* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, +* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. +* See the Mulan PSL v2 for more details. +*/ + +/** +* @file: appstartup.c +* @brief: init application userspace and create main task +* @version: 1.0 +* @author: AIIT XUOS Lab +* @date: 2020/3/15 +* +*/ + +#include +#include +#ifdef TASK_ISOLATION +#include +#endif + +#ifdef APP_STARTUP_FROM_SDCARD +#include +#endif + +extern int main(void); +#ifdef USER_APPLICATION +#ifndef SEPARATE_COMPILE +void MainKTaskFunction(void *parameter) +{ +#if defined(__ICCARM__) || defined(__GNUC__) + main(); +#endif +} +#endif + +/** + * This function will create main application then startup it + * + * + */ +void CreateMainTask(void) +{ + int32 main = 0; + +#ifdef SEPARATE_COMPILE + KPrintf("Tip!!! Kernel is separated with application. main entry : 0x%08x \n",USERSPACE->us_entrypoint); + + main = UTaskCreate("main", (void*)USERSPACE->us_entrypoint, NONE, + MAIN_KTASK_STACK_SIZE, MAIN_KTASK_PRIORITY); + +#else + main = KTaskCreate("main", MainKTaskFunction, NONE, + MAIN_KTASK_STACK_SIZE, MAIN_KTASK_PRIORITY); + +#endif + + if(main < 0) { + KPrintf("main create failed ...%s %d.\n",__FUNCTION__,__LINE__); + return; + } + + StartupKTask(main); +} + +#ifdef SEPARATE_COMPILE +int InitUserspace(void) +{ +#ifdef APP_STARTUP_FROM_FLASH + uint8_t *src = NONE; + uint8_t *dest = NONE; + uint8_t *end = NONE; + + dest = (uint8_t *)USERSPACE->us_bssstart; + end = (uint8_t *)USERSPACE->us_bssend; + while (dest != end) { + *dest++ = 0; + } + + /* Initialize all of user-space .data */ + + src = (uint8_t *)USERSPACE->us_datasource; + dest = (uint8_t *)USERSPACE->us_datastart; + end = (uint8_t *)USERSPACE->us_dataend; + while (dest != end) { + *dest++ = *src++; + } +#ifndef TASK_ISOLATION + src = (uint8_t *)&g_service_table_start; + dest = (uint8_t *)SERVICE_TABLE_ADDRESS; + end = (uint8_t *)&g_service_table_end; + while (src != end) { + *dest++ = *src++; + } +#endif + + UserInitBoardMemory((void*)USER_MEMORY_START_ADDRESS, (void*)USER_MEMORY_END_ADDRESS); + +#ifdef MOMERY_PROTECT_ENABLE + if ( mem_access.Init != NONE){ + if(mem_access.Init( (void **)(&isolation)) == EOK) + mem_access.Load(isolation); + } +#endif + return EOK; +#endif + +#ifdef APP_STARTUP_FROM_SDCARD + int fd = 0; + char buf[1024] = {0}; + int len = 0; + int len_check = 0; + uint8_t *src = NONE; + uint8_t *dest = NONE; + uint8_t *end = NONE; +#ifndef FS_VFS + KPrintf("fs not enable!%s %d\n",__func__,__LINE__); + CHECK(0); +#endif + + fd = open(BOARD_APP_NAME,O_RDONLY ); + if(fd > 0) { + KPrintf("open app bin %s success.\n",BOARD_APP_NAME); + + dest = (uint8_t *)USERSPACE; + /* copy app to USERSPACE */ + while(RET_TRUE) { + memset(buf, 0 , 1024); + len = read(fd, buf, 1024); + KPrintf("read app bin len %d\n",len); + if(len > 0) { + memcpy(dest, buf, len); + dest = dest + len; + len_check = len_check + len; + } else { + break; + } + } + + if(len_check <= 0){ + return -ERROR; + } + + dest = (uint8_t *)USERSPACE->us_bssstart; + end = (uint8_t *)USERSPACE->us_bssend; + while (dest != end) { + *dest++ = 0; + } + + src = (uint8_t *)&g_service_table_start; + dest = (uint8_t *)SERVICE_TABLE_ADDRESS; + end = (uint8_t *)&g_service_table_end; + + while (src != end) { + *dest++ = *src++; + } + + close(fd); + + UserInitBoardMemory((void*)USER_MEMORY_START_ADDRESS, (void*)USER_MEMORY_END_ADDRESS); + + return EOK; + + } else { + KPrintf("open app bin %s failed.\n",BOARD_APP_NAME); + return -EEMPTY; + } +#endif +} +#endif +#endif \ No newline at end of file diff --git a/Ubiquitous/XiZi/kernel/thread/assign.c b/Ubiquitous/XiZi/kernel/thread/assign.c new file mode 100644 index 0000000..2bef0fe --- /dev/null +++ b/Ubiquitous/XiZi/kernel/thread/assign.c @@ -0,0 +1,389 @@ +/* +* Copyright (c) 2020 AIIT XUOS Lab +* XiUOS is licensed under Mulan PSL v2. +* You can use this software according to the terms and conditions of the Mulan PSL v2. +* You may obtain a copy of Mulan PSL v2 at: +* http://license.coscl.org.cn/MulanPSL2 +* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, +* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, +* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. +* See the Mulan PSL v2 for more details. +*/ + +/** +* @file: assign.c +* @brief: system scheduler of single cpu +* @version: 1.0 +* @author: AIIT XUOS Lab +* @date: 2020/3/15 +* +*/ + +#include +#include +#include +#include +#include + +struct Assign Assign; + +static struct PriorityReadyVectorDone SingleReadyVectorDone = +{ + OsAssignReadyVectorInit, + KTaskInsertToReadyVector, + KTaskOsAssignRemoveKTask, +}; + +/** + * task schedule function.getting the highest priority task then switching to it + */ +void KTaskOsAssign(void) +{ + + x_ubase highest_prio = 0; + int need_insert_from_task = 0; + struct TaskDescriptor *new_task = NONE; + struct TaskDescriptor *from_task = NONE; + + if(GetOsAssignLockLevel() >= 1) { + return; + } + + if( isrManager.done->isInIsr() ){ + isrManager.done->setSwitchTrigerFlag(); + return; + } + + /* if the bitmap is empty then do not switch */ + if(RET_TRUE == JudgeAssignReadyBitmapIsEmpty(&Assign.os_assign_read_vector)) { + return; + } + + highest_prio = Assign.os_assign_read_vector.highest_prio; + new_task = ChooseTaskWithHighestPrio(&Assign.os_assign_read_vector); + + if(RET_TRUE != JudgeKTaskStatIsRunning(Assign.os_running_task)) { + CHECK(NONE != new_task); + goto SWITCH; + } + + /* if the running task’ priority is the highest and this task is not be yield then do not switch */ + if(highest_prio < Assign.os_running_task->task_dync_sched_member.cur_prio) { + return; + } else { + need_insert_from_task = 1; + } + +SWITCH: + if (new_task != Assign.os_running_task) { + Assign.current_priority = (uint8)highest_prio; + from_task = Assign.os_running_task; + + HOOK(hook.assign.hook_Assign, (from_task, new_task)); + + if (need_insert_from_task) { + Assign.ready_vector_done->insert(from_task); + } + + Assign.ready_vector_done->remove(new_task); + KTaskStatSetAsRunning(new_task); + + SYS_KDEBUG_LOG(KDBG_SCHED, + ("[%d]switch to priority#%d " + "task:%.*s(sp:0x%08x), " + "from task:%.*s(sp: 0x%08x)\n", + isrManager.done->getCounter(), highest_prio, + NAME_NUM_MAX, new_task->task_base_info.name, new_task->stack_point, + NAME_NUM_MAX, from_task->task_base_info.name, from_task->stack_point)); + +#ifdef KERNEL_STACK_OVERFLOW_CHECK + _KTaskOsAssignStackCheck(new_task); +#endif + + + SwitchKtaskContext((x_ubase)&from_task->stack_point, + (x_ubase)&new_task->stack_point, new_task); + + } else { + Assign.ready_vector_done->remove(Assign.os_running_task); + KTaskStatSetAsRunning(Assign.os_running_task); + } + return; +} + +void KTaskOsAssignDoIrqSwitch(void *context) +{ + + x_ubase highest_prio = 0; + int need_insert_from_task = 0; + struct TaskDescriptor *new_task = NONE; + struct TaskDescriptor *from_task = NONE; + + if(GetOsAssignLockLevel() >= 1) { + return; + } + + if( isrManager.done->getSwitchTrigerFlag() == 0 ) { + return; + } + + isrManager.done->clearSwitchTrigerFlag(); + /* if the bitmap is empty then do not switch */ + if(RET_TRUE == JudgeAssignReadyBitmapIsEmpty(&Assign.os_assign_read_vector)) { + return; + } + + highest_prio = Assign.os_assign_read_vector.highest_prio; + new_task = ChooseTaskWithHighestPrio(&Assign.os_assign_read_vector); + + if(RET_TRUE != JudgeKTaskStatIsRunning(Assign.os_running_task)) { + CHECK(NONE != new_task); + goto SWITCH; + } + + /* if the running task’ priority is the highest and this task is not be yield then do not switch */ + if(highest_prio < Assign.os_running_task->task_dync_sched_member.cur_prio) { + return; + } else { + need_insert_from_task = 1; + } + +SWITCH: + + if (new_task != Assign.os_running_task) { + Assign.current_priority = (uint8)highest_prio; + from_task = Assign.os_running_task; + + HOOK(hook.assign.hook_Assign, (from_task, new_task)); + + if (need_insert_from_task) { + Assign.ready_vector_done->insert(from_task); + } + + Assign.ready_vector_done->remove(new_task); + KTaskStatSetAsRunning(new_task); + + SYS_KDEBUG_LOG(KDBG_SCHED, + ("[%d]switch to priority#%d " + "task:%.*s(sp:0x%08x), " + "from task:%.*s(sp: 0x%08x)\n", + isrManager.done->getCounter(), highest_prio, + NAME_NUM_MAX, new_task->task_base_info.name, new_task->stack_point, + NAME_NUM_MAX, from_task->task_base_info.name, from_task->stack_point)); + +#ifdef KERNEL_STACK_OVERFLOW_CHECK + _KTaskOsAssignStackCheck(new_task); +#endif + + + SYS_KDEBUG_LOG(KDBG_SCHED, ("switch in interrupt\n")); + HwInterruptcontextSwitch((x_ubase)&from_task->stack_point, + (x_ubase)&new_task->stack_point, new_task, context); + + } else { + Assign.ready_vector_done->remove(Assign.os_running_task); + KTaskStatSetAsRunning(Assign.os_running_task); + } +} + +void KTaskOsAssignAfterIrq(void *context) +{ + x_base lock = 0; + lock = DISABLE_INTERRUPT(); + KTaskOsAssignDoIrqSwitch(context); + ENABLE_INTERRUPT(lock); +} +/* + * insert a ready task to system ready table with READY state and remove it from suspend list + * + * @param task the task descriptor + * + */ +void KTaskInsertToReadyVector(struct TaskDescriptor *task) +{ + x_base lock = 0; + + NULL_PARAM_CHECK(task); + + lock = DISABLE_INTERRUPT(); + + KTaskStatSetAsReady(task); + AssignPolicyInsert(task, &Assign.os_assign_read_vector); + + SYS_KDEBUG_LOG(KDBG_SCHED, ("insert task[%.*s], the priority: %d\n", + NAME_NUM_MAX, task->task_base_info.name, task->task_dync_sched_member.cur_prio)); + +#if KTASK_PRIORITY_MAX > 32 + MERGE_FLAG(&Assign.os_assign_read_vector.ready_vector[task->task_dync_sched_member.bitmap_offset], task->task_dync_sched_member.bitmap_row); +#endif + MERGE_FLAG(&Assign.os_assign_read_vector.priority_ready_group, task->task_dync_sched_member.bitmap_column); + + ENABLE_INTERRUPT(lock); +} + +/* + * a task will be removed from ready table. + * + * @param task task descriptor + * + */ +void KTaskOsAssignRemoveKTask(struct TaskDescriptor *task) +{ + x_base lock = 0; + x_ubase number = 0; + x_ubase highest_priority = 0; + + NULL_PARAM_CHECK(task); + + lock = DISABLE_INTERRUPT(); + + SYS_KDEBUG_LOG(KDBG_SCHED, ("remove task[%.*s], the priority: %d\n", + NAME_NUM_MAX, task->task_base_info.name, + task->task_dync_sched_member.cur_prio)); + + DoubleLinkListRmNode(&(task->task_dync_sched_member.sched_link)); + + if (IsDoubleLinkListEmpty(&(Assign.os_assign_read_vector.priority_ready_vector[task->task_dync_sched_member.cur_prio]))) { +#if KTASK_PRIORITY_MAX > 32 + CLEAR_FLAG(&Assign.os_assign_read_vector.ready_vector[task->task_dync_sched_member.bitmap_offset], task->task_dync_sched_member.bitmap_row); + if (Assign.os_assign_read_vector.ready_vector[task->task_dync_sched_member.bitmap_offset] == 0) { + CLEAR_FLAG(&Assign.os_assign_read_vector.priority_ready_group, task->task_dync_sched_member.bitmap_column); + } + number = PrioCaculate(Assign.os_assign_read_vector.priority_ready_group); + highest_priority = (number * 8) + PrioCaculate(Assign.os_assign_read_vector.ready_vector[number]); +#else + CLEAR_FLAG(&Assign.os_assign_read_vector.priority_ready_group, task->task_dync_sched_member.bitmap_column); + highest_priority = PrioCaculate(Assign.os_assign_read_vector.priority_ready_group); +#endif + Assign.os_assign_read_vector.highest_prio = highest_priority; + } + + ENABLE_INTERRUPT(lock); +} + + +static inline void SwitchToFirstRunningTask(struct TaskDescriptor* task) +{ + NULL_PARAM_CHECK(task); + + Assign.ready_vector_done->remove(task); + KTaskStatSetAsRunning(task); + SwitchKtaskContextTo((x_ubase)&task->stack_point, task); +} + +static inline void SetSystemRunningTask(struct TaskDescriptor* task) +{ + NULL_PARAM_CHECK(task); + + Assign.os_running_task = task; +} + +/** + * This function will yield current task. + * + * @return EOK + */ + +x_err_t YieldOsAssign(void) +{ + x_base lock = 0; + x_ubase highest_prio = 0; + struct TaskDescriptor *new_task = NONE; + struct TaskDescriptor *from_task = NONE; + + lock = DISABLE_INTERRUPT(); + + if(GetOsAssignLockLevel() >= 1) { + ENABLE_INTERRUPT(lock); + goto __exit; + } + + if (isrManager.done->isInIsr()) { + ENABLE_INTERRUPT(lock); + goto __exit; + } + + /* if the bitmap is empty then do not switch */ + if(RET_TRUE == JudgeAssignReadyBitmapIsEmpty(&Assign.os_assign_read_vector)) { + ENABLE_INTERRUPT(lock); + return -ERROR; + } + + highest_prio = Assign.os_assign_read_vector.highest_prio; + new_task = ChooseTaskWithHighestPrio(&Assign.os_assign_read_vector); + + from_task = Assign.os_running_task; + + if(RET_TRUE != JudgeKTaskStatIsRunning(from_task)) { + CHECK(NONE != new_task); + } else { + Assign.ready_vector_done->insert(from_task); + } + + if (new_task != from_task) { + Assign.current_priority = (uint8)highest_prio; + + HOOK(hook.assign.hook_Assign, (from_task, new_task)); + + Assign.ready_vector_done->remove(new_task); + KTaskStatSetAsRunning(new_task); + + SYS_KDEBUG_LOG(KDBG_SCHED, + ("[%d]switch to priority#%d " + "task:%.*s(sp:0x%08x), " + "from task:%.*s(sp: 0x%08x)\n", + isrManager.done->getCounter(), highest_prio, + NAME_NUM_MAX, new_task->task_base_info.name, new_task->stack_point, + NAME_NUM_MAX, from_task->task_base_info.name, from_task->stack_point)); + +#ifdef KERNEL_STACK_OVERFLOW_CHECK + _KTaskOsAssignStackCheck(new_task); +#endif + + + SwitchKtaskContext((x_ubase)&from_task->stack_point, + (x_ubase)&new_task->stack_point, new_task); + + ENABLE_INTERRUPT(lock); + goto __exit; + } else { + Assign.ready_vector_done->remove(Assign.os_running_task); + KTaskStatSetAsRunning(Assign.os_running_task); + } + + ENABLE_INTERRUPT(lock); + +__exit: + return EOK; +} + +/** + * + * OsAssign startup function + * . + */ +void StartupOsAssign(void) +{ + struct TaskDescriptor *FirstRunningTask = NONE; + + FirstRunningTask = ChooseTaskWithHighestPrio(&Assign.os_assign_read_vector); + + SetSystemRunningTask(FirstRunningTask); + + SwitchToFirstRunningTask(FirstRunningTask); +} + +/** + * + * system OsAssign init function + */ +void SysInitOsAssign(void) +{ + SYS_KDEBUG_LOG(KDBG_SCHED, ("start Os Assign: max priority 0x%02x\n", + KTASK_PRIORITY_MAX)); + + Assign.ready_vector_done = &SingleReadyVectorDone; + Assign.ready_vector_done->init(&Assign.os_assign_read_vector); + + ResetCriticalAreaLock(); +} \ No newline at end of file diff --git a/Ubiquitous/XiZi/kernel/thread/assign_fifo.c b/Ubiquitous/XiZi/kernel/thread/assign_fifo.c new file mode 100644 index 0000000..9173083 --- /dev/null +++ b/Ubiquitous/XiZi/kernel/thread/assign_fifo.c @@ -0,0 +1,51 @@ +/* +* Copyright (c) 2020 AIIT XUOS Lab +* XiUOS is licensed under Mulan PSL v2. +* You can use this software according to the terms and conditions of the Mulan PSL v2. +* You may obtain a copy of Mulan PSL v2 at: +* http://license.coscl.org.cn/MulanPSL2 +* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, +* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, +* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. +* See the Mulan PSL v2 for more details. +*/ + +/** +* @file: assign_roundrobin.c +* @brief: ready table and timeslice functions definitions of fifo scheduler algorithm +* @version: 1.0 +* @author: AIIT XUOS Lab +* @date: 2020/3/15 +* +*/ + +#include + +#define NO_TIMESLICE (0) + +void FifoTaskTimesliceInit(struct TaskDescriptor *task) +{ + NULL_PARAM_CHECK(task); + + task->task_dync_sched_member.origin_timeslice = NO_TIMESLICE; + task->task_dync_sched_member.rest_timeslice = NO_TIMESLICE; +} + + +void FifoReadyVectorInsert(struct TaskDescriptor *task, struct OsAssignReadyVector* ready_table) +{ + DoubleLinklistType* tail = NONE; + + NULL_PARAM_CHECK(task); + NULL_PARAM_CHECK(ready_table); + + tail = ready_table->priority_ready_vector[task->task_dync_sched_member.cur_prio].node_prev; + DoubleLinkListInsertNodeAfter(tail, &(task->task_dync_sched_member.sched_link)); + +} + + +void FifoTaskTimesliceUpdate() +{ + return; +} diff --git a/Ubiquitous/XiZi/kernel/thread/assign_roundrobin.c b/Ubiquitous/XiZi/kernel/thread/assign_roundrobin.c new file mode 100644 index 0000000..61f8438 --- /dev/null +++ b/Ubiquitous/XiZi/kernel/thread/assign_roundrobin.c @@ -0,0 +1,56 @@ +/* +* Copyright (c) 2020 AIIT XUOS Lab +* XiUOS is licensed under Mulan PSL v2. +* You can use this software according to the terms and conditions of the Mulan PSL v2. +* You may obtain a copy of Mulan PSL v2 at: +* http://license.coscl.org.cn/MulanPSL2 +* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, +* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, +* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. +* See the Mulan PSL v2 for more details. +*/ + +/** +* @file: assign_roundrobin.c +* @brief: ready table and timeslice functions definitions of roundrobin scheduler algorithm +* @version: 1.0 +* @author: AIIT XUOS Lab +* @date: 2020/3/15 +* +*/ + +#include + +void RoundRobinTaskTimesliceInit(struct TaskDescriptor *task) +{ + NULL_PARAM_CHECK(task); + + task->task_dync_sched_member.origin_timeslice = 10; + task->task_dync_sched_member.rest_timeslice = 10; +} + +void RoundRobinReadyVectorInsert(struct TaskDescriptor *task, struct OsAssignReadyVector* ready_table) +{ + DoubleLinklistType* tail = NONE; + + NULL_PARAM_CHECK(task); + NULL_PARAM_CHECK(ready_table); + + tail = ready_table->priority_ready_vector[task->task_dync_sched_member.cur_prio].node_prev; + DoubleLinkListInsertNodeAfter(tail, &(task->task_dync_sched_member.sched_link)); + +} + +void RoundRobinTaskTimesliceUpdate(struct TaskDescriptor *task) +{ + NULL_PARAM_CHECK(task); + + -- task->task_dync_sched_member.rest_timeslice; + if (task->task_dync_sched_member.rest_timeslice == 0) + { + task->task_dync_sched_member.rest_timeslice = task->task_dync_sched_member.origin_timeslice; + + DO_KTASK_ASSIGN; + } +} + diff --git a/Ubiquitous/XiZi/kernel/thread/assign_roundrobinremain.c b/Ubiquitous/XiZi/kernel/thread/assign_roundrobinremain.c new file mode 100644 index 0000000..47d679c --- /dev/null +++ b/Ubiquitous/XiZi/kernel/thread/assign_roundrobinremain.c @@ -0,0 +1,79 @@ +/* +* Copyright (c) 2020 AIIT XUOS Lab +* XiUOS is licensed under Mulan PSL v2. +* You can use this software according to the terms and conditions of the Mulan PSL v2. +* You may obtain a copy of Mulan PSL v2 at: +* http://license.coscl.org.cn/MulanPSL2 +* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, +* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, +* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. +* See the Mulan PSL v2 for more details. +*/ + +/** +* @file: assign_roundrobin.c +* @brief: ready table and timeslice functions definitions of remain ticks first scheduler algorithm +* @version: 1.0 +* @author: AIIT XUOS Lab +* @date: 2020/3/15 +* +*/ + +#include + +void RoundRobinRemainTaskTimesliceInit(struct TaskDescriptor *task) +{ + NULL_PARAM_CHECK(task); + + task->task_dync_sched_member.origin_timeslice = 10; + task->task_dync_sched_member.rest_timeslice = 10; +} + + +void RoundRobinRemainReadyVectorInsert(struct TaskDescriptor *task, struct OsAssignReadyVector* ready_table) +{ + DoubleLinklistType* node = NONE; + DoubleLinklistType* tail = NONE; + struct TaskDescriptor *tmp = NONE; + + NULL_PARAM_CHECK(task); + NULL_PARAM_CHECK(ready_table); + + if ( task->task_dync_sched_member.advance_cnt < KTASK_MAX_ADVANCE_PROCESS_TIME ) { + DOUBLE_LINKLIST_FOR_EACH(node, &ready_table->priority_ready_vector[task->task_dync_sched_member.cur_prio]) { + tmp = SYS_DOUBLE_LINKLIST_ENTRY(node, struct TaskDescriptor, task_dync_sched_member.sched_link); + if (task->task_dync_sched_member.rest_timeslice < tmp->task_dync_sched_member.rest_timeslice) { + break; + } + } + + if ( node != &ready_table->priority_ready_vector[task->task_dync_sched_member.cur_prio]) { + DoubleLinkListInsertNodeBefore(node, &(task->task_dync_sched_member.sched_link)); + } else { + tail = ready_table->priority_ready_vector[task->task_dync_sched_member.cur_prio].node_prev; + DoubleLinkListInsertNodeAfter(tail, &(task->task_dync_sched_member.sched_link)); + } + } else { + tail = ready_table->priority_ready_vector[task->task_dync_sched_member.cur_prio].node_prev; + DoubleLinkListInsertNodeAfter(tail, &(task->task_dync_sched_member.sched_link)); + } + +} + +void RoundRobinRemainTaskTimesliceUpdate(struct TaskDescriptor *task) +{ + NULL_PARAM_CHECK(task); + + -- task->task_dync_sched_member.rest_timeslice; + if (task->task_dync_sched_member.rest_timeslice == 0) + { + if ( task->task_dync_sched_member.advance_cnt < KTASK_MAX_ADVANCE_PROCESS_TIME ) { + task->task_dync_sched_member.advance_cnt++; + } + + task->task_dync_sched_member.rest_timeslice = task->task_dync_sched_member.origin_timeslice; + + DO_KTASK_ASSIGN; + } +} + diff --git a/Ubiquitous/XiZi/kernel/thread/assignstat.c b/Ubiquitous/XiZi/kernel/thread/assignstat.c new file mode 100644 index 0000000..71e2192 --- /dev/null +++ b/Ubiquitous/XiZi/kernel/thread/assignstat.c @@ -0,0 +1,112 @@ +/* +* Copyright (c) 2020 AIIT XUOS Lab +* XiUOS is licensed under Mulan PSL v2. +* You can use this software according to the terms and conditions of the Mulan PSL v2. +* You may obtain a copy of Mulan PSL v2 at: +* http://license.coscl.org.cn/MulanPSL2 +* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, +* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, +* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. +* See the Mulan PSL v2 for more details. +*/ + +/** +* @file: assignstat.c +* @brief: check system read ready and task stack +* @version: 1.0 +* @author: AIIT XUOS Lab +* @date: 2020/3/15 +* +*/ + +#include + +#ifdef KERNEL_STACK_OVERFLOW_CHECK +/** + * a task stack check function + * + * @param task task descriptor + */ +void _KTaskOsAssignStackCheck(struct TaskDescriptor *task) +{ + NULL_PARAM_CHECK(task); + + if ((x_ubase)task->stack_point<= (x_ubase)task->task_base_info.stack_start || + (x_ubase)task->stack_point > + (x_ubase)task->task_base_info.stack_start + (x_ubase)task->task_base_info.stack_depth) { + + KPrintf("task name:%s id:%d stack overflow,sp %p stacktop %p stack depth 0x%x\n", task->task_base_info.name,task->id.id,task->stack_point,(uint32*)task->task_base_info.stack_start + task->task_base_info.stack_depth,task->task_base_info.stack_depth); + + while (1); + } +} +#endif + +int32 JudgeAssignReadyBitmapIsEmpty(struct OsAssignReadyVector *ready_vector) +{ + NULL_PARAM_CHECK(ready_vector); + return ((ready_vector->priority_ready_group == 0) ? RET_TRUE: 0); +} + +struct TaskDescriptor * ChooseTaskWithHighestPrio(struct OsAssignReadyVector *ready_vector) +{ + struct TaskDescriptor *target_task = NONE; + + NULL_PARAM_CHECK(ready_vector); + + target_task = SYS_DOUBLE_LINKLIST_ENTRY(ready_vector->priority_ready_vector[ready_vector->highest_prio].node_next, + struct TaskDescriptor, + task_dync_sched_member.sched_link); + + return target_task; +} + +void OsAssignReadyVectorInit(struct OsAssignReadyVector *ready_vector) +{ + register x_base prio = 0; + NULL_PARAM_CHECK(ready_vector); + + while(prio < KTASK_PRIORITY_MAX) + { + InitDoubleLinkList(&ready_vector->priority_ready_vector[prio]); + prio++; + } + ready_vector->highest_prio = 0; + ready_vector->priority_ready_group = 0; +#if KTASK_PRIORITY_MAX > 32 + memset(ready_vector->ready_vector, 0, sizeof(ready_vector->ready_vector)); +#endif +} + +/* + * This function will insert a task to system ready table according to sched policy(FIFO/RR/RR+remain timeslice) + * + * @param task task descriptor + * @param ready_table task ready_table + */ +void AssignPolicyInsert(struct TaskDescriptor *task, struct OsAssignReadyVector* ready_table) +{ + DoubleLinklistType* node = NONE; + DoubleLinklistType* tail = NONE; + struct TaskDescriptor *tmp = NONE; + + NULL_PARAM_CHECK(task); + NULL_PARAM_CHECK(ready_table); + +#if defined (SCHED_POLICY_FIFO) + FifoReadyVectorInsert(task, ready_table); +#elif defined (SCHED_POLICY_RR) + RoundRobinReadyVectorInsert(task, ready_table); +#elif defined (SCHED_POLICY_RR_REMAINSLICE) + RoundRobinRemainReadyVectorInsert(task, ready_table); +#endif + + if(NONE == task || NONE == ready_table) { + KPrintf("PARAM CHECK FAILED ...%s %d param is NULL.\n",__FUNCTION__,__LINE__); + return; + } + + if(task->task_dync_sched_member.cur_prio > ready_table->highest_prio) { + ready_table->highest_prio = task->task_dync_sched_member.cur_prio; + } +} \ No newline at end of file diff --git a/Ubiquitous/XiZi/kernel/thread/avl_tree.c b/Ubiquitous/XiZi/kernel/thread/avl_tree.c new file mode 100644 index 0000000..6b291fa --- /dev/null +++ b/Ubiquitous/XiZi/kernel/thread/avl_tree.c @@ -0,0 +1,369 @@ +/* +* Copyright (c) 2020 AIIT XUOS Lab +* XiUOS is licensed under Mulan PSL v2. +* You can use this software according to the terms and conditions of the Mulan PSL v2. +* You may obtain a copy of Mulan PSL v2 at: +* http://license.coscl.org.cn/MulanPSL2 +* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, +* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, +* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. +* See the Mulan PSL v2 for more details. +*/ + +/** +* @file: avl_tree.c +* @brief: avl_tree file +* @version: 1.0 +* @author: AIIT XUOS Lab +* @date: 2020/3/15 +* +*/ + +#include "xs_avltree.h" +#include +#include +#include +#include + +/** + * This function will return the node height of the avl tree + * + * @param avl_node avl tree node descriptor + * @return 0 + */ +static uint32 AvlTreeGetNodeHeight(AvlNodeType avl_node) +{ + if(avl_node) { + return AVL_MAX(AvlTreeGetNodeHeight(avl_node->left), AvlTreeGetNodeHeight(avl_node->right)) + 1; + } else { + return 0; + } +} + +/** + * This function will return the node balance factor of the avl tree + * + * @param avl_node avl tree node descriptor + */ +static int32 AvlTreeGetNodeBalanceFactor(AvlNodeType avl_node) +{ + if(avl_node) { + return AvlTreeGetNodeHeight(avl_node->left) - AvlTreeGetNodeHeight(avl_node->right); + } else { + return 0; + } +} + +/** + * This function will support right rotate to balance the avl tree(eg. LL case) + * + * @param avl_node avl tree node descriptor + * @return avl tree node + */ +static AvlNodeType AvlTreeSetRightRotate(AvlNodeType avl_node) +{ + NULL_PARAM_CHECK(avl_node); + + AvlNodeType new_node = avl_node->left; + + avl_node->left = new_node->right; + new_node->right = avl_node; + + new_node->height = AVL_MAX(AvlTreeGetNodeHeight(new_node->left), AvlTreeGetNodeHeight(new_node->right)) + 1; + avl_node->height = AVL_MAX(AvlTreeGetNodeHeight(avl_node->left), AvlTreeGetNodeHeight(avl_node->right)) + 1; + + return new_node; +} + +/** + * This function will support left rotate to balance the avl tree(eg. RR case) + * + * @param avl_node avl tree node descriptor + * @return avl tree node + */ +static AvlNodeType AvlTreeSetLeftRotate(AvlNodeType avl_node) +{ + NULL_PARAM_CHECK(avl_node); + + AvlNodeType new_node = avl_node->right; + + avl_node->right = new_node->left; + new_node->left = avl_node; + + new_node->height = AVL_MAX(AvlTreeGetNodeHeight(new_node->left), AvlTreeGetNodeHeight(new_node->right)) + 1; + avl_node->height = AVL_MAX(AvlTreeGetNodeHeight(avl_node->left), AvlTreeGetNodeHeight(avl_node->right)) + 1; + + return new_node; +} + +/** + * This function will support left and right rotate to balance the avl tree(eg. LR case) + * + * @param avl_node avl tree node descriptor + * @return avl tree node + */ +static AvlNodeType AvlTreeSetLRRotate(AvlNodeType avl_node) +{ + NULL_PARAM_CHECK(avl_node); + + AvlNodeType new_node = NONE; + AvlNodeType left_node = avl_node->left; + + /*step1 : Left rotate*/ + avl_node->left = AvlTreeSetLeftRotate(left_node); + + /*step2 : Right rotate*/ + new_node = AvlTreeSetRightRotate(avl_node); + + return new_node; +} + +/** + * This function will support right and left rotate to balance the avl tree(eg. RL case) + * + * @param avl_node avl tree node descriptor + * @return avl tree node + */ +static AvlNodeType AvlTreeSetRLRotate(AvlNodeType avl_node) +{ + NULL_PARAM_CHECK(avl_node); + + AvlNodeType new_node = NONE; + AvlNodeType right_node = avl_node->right; + + /*step1 : Right rotate*/ + avl_node->right = AvlTreeSetRightRotate(right_node); + + /*step2 : Left rotate*/ + new_node = AvlTreeSetLeftRotate(avl_node); + + return new_node; +} + +/** + * This function will balance the avl tree when inserting or deleting node + * + * @param avl_node avl tree node descriptor + * @return avl tree node + */ +static AvlNodeType AvlTreeBalance(AvlNodeType avl_node) +{ + if(avl_node) + { + AvlNodeType new_node = NONE; + uint32 avlnode_BF = AVL_ABS(AvlTreeGetNodeBalanceFactor(avl_node)); + + if(avlnode_BF > 1) { + if(AvlTreeGetNodeBalanceFactor(avl_node->left) > 0) { + /*LL case*/ + new_node = AvlTreeSetRightRotate(avl_node); + } else if(AvlTreeGetNodeBalanceFactor(avl_node->left) < 0) { + /*LR case*/ + new_node = AvlTreeSetLRRotate(avl_node); + } else if(AvlTreeGetNodeBalanceFactor(avl_node->right) < 0) { + /*RR case*/ + new_node = AvlTreeSetLeftRotate(avl_node); + } else if(AvlTreeGetNodeBalanceFactor(avl_node->right) > 0) { + /*RL case*/ + new_node = AvlTreeSetRLRotate(avl_node); + } + } else { + /*the avl tree is balanced, no need to rebalance*/ + new_node = avl_node; + } + + return new_node; + + } else { + return NONE; + } +} + +/** + * This function will insert data to the avl tree + * + * @param avl_node avl tree node descriptor + * @param data input data + */ +AvlNodeType AvlTreeInsertNode(AvlNodeType avl_node, int32 data) +{ + AvlNodeType new_node = NONE; + + if(NONE == avl_node) { + new_node = x_malloc(sizeof(struct AvlNode)); + if(NONE == new_node) { + KPrintf("AvlTreeInsertNode malloc AvlNode failed\n"); + x_free(new_node); + return NONE; + } + new_node->data = data; + new_node->left = NONE; + new_node->right = NONE; + new_node->height = 1; + avl_node = new_node; + } else if(data == avl_node->data) { + /*input data is already existed*/ + KPrintf("the input data is already existed. just return\n"); + return avl_node; + } else { + if(avl_node->data < data) { + avl_node->right = AvlTreeInsertNode(avl_node->right, data); + if(NONE == avl_node->right) { + KPrintf("AvlTreeInsertNode find right avl_node data failed\n"); + return NONE; + } + } else { + avl_node->left = AvlTreeInsertNode(avl_node->left, data); + if(NONE == avl_node->left) { + KPrintf("AvlTreeInsertNode find left avl_node data failed\n"); + return NONE; + } + } + } + + return AvlTreeBalance(avl_node); +} + +/** + * This function will find the pre node of the avl_node + * + * @param avl_node avl tree node descriptor + * @return avl tree node + */ +static AvlNodeType AvlTreeFindPreNode(AvlNodeType avl_node) +{ + NULL_PARAM_CHECK(avl_node); + + AvlNodeType pre_node = NONE; + + if(avl_node->left) { + if(avl_node->left->right) { + pre_node = avl_node->left->right; + while(pre_node->right) { + pre_node = pre_node->right; + } + } else { + pre_node = avl_node->left; + } + } else { + pre_node = avl_node; + } + + return pre_node; +} + +/** + * This function will delete a certain node, ultimate target is to find the leaf node + * + * @param avl_node avl tree node descriptor + * @param data delete data + * @return avl tree node + */ +static AvlNodeType AvlTreeDeleteLeafNode(AvlNodeType avl_node) +{ + AvlNodeType pre_node = NONE; + + if((NONE == avl_node->left) && (NONE == avl_node->right)) { + /*Leaf Node*/ + avl_node = NONE; + x_free(avl_node); + } else if(NONE == avl_node->left) { + /*Right child is Leaf Node*/ + avl_node->data = avl_node->right->data; + avl_node->right = NONE; + x_free(avl_node->right); + } else if(NONE == avl_node->right) { + /*Left child is Leaf Node*/ + avl_node->data = avl_node->left->data; + avl_node->left = NONE; + x_free(avl_node->left); + } else { + /*Find the pre node to replace the avl node, then delete the pre node*/ + pre_node = AvlTreeFindPreNode(avl_node); + if(pre_node) { + avl_node->data = pre_node->data; + avl_node->left = AvlTreeDeleteNode(avl_node->left, pre_node->data); + } + } + + return avl_node; +} + +/** + * This function will delete data from the avl tree + * + * @param avl_node avl tree node descriptor + * @param data delete data + */ +AvlNodeType AvlTreeDeleteNode(AvlNodeType avl_node, int32 data) +{ + if(avl_node) { + if(data == avl_node->data) { + avl_node = AvlTreeDeleteLeafNode(avl_node); + } else { + if(avl_node->data < data) { + avl_node->right = AvlTreeDeleteNode(avl_node->right, data); + } else { + avl_node->left = AvlTreeDeleteNode(avl_node->left, data); + } + } + + return AvlTreeBalance(avl_node); + } else { + KPrintf("AvlTreeDeleteNode cannot find the delete data\n"); + return NONE; + } +} + +/** + * This function will modify certain data of the avl tree + * + * @param avl_node avl tree node descriptor + * @param src_data src data + * @param dst_data dst data + */ +AvlNodeType AvlNodeModifyNode(AvlNodeType avl_node, int32 src_data, int32 dst_data) +{ + AvlNodeType dst_node = NONE; + + if(avl_node) { + /*Step1 : delete the src data node*/ + avl_node = AvlTreeDeleteNode(avl_node, src_data); + + /*Step2 : insert the dst data node*/ + dst_node = AvlTreeInsertNode(avl_node, dst_data); + + } else { + KPrintf("AvlNodeModifyNode cannot find the src data node\n"); + return NONE; + } + + return dst_node; +} + +/** + * This function will return the avl node which has the data + * + * @param avl_node avl tree node descriptor + * @param data data + */ +AvlNodeType AvlNodeSearchNode(AvlNodeType avl_node, int32 data) +{ + AvlNodeType dst_node = NONE; + + if(avl_node) { + if(data == avl_node->data) { + dst_node = avl_node; + KPrintf("AvlNodeSearchNode %d is existed return the node\n", avl_node->data); + } else if(avl_node->data < data) { + dst_node = AvlNodeSearchNode(avl_node->right, data); + } else { + dst_node = AvlNodeSearchNode(avl_node->left, data); + } + } else { + KPrintf("AvlNodeSearchNode avl_node is NONE.\n"); + return NONE; + } + + return dst_node; +} diff --git a/Ubiquitous/XiZi/kernel/thread/banner.c b/Ubiquitous/XiZi/kernel/thread/banner.c new file mode 100644 index 0000000..7c3d1de --- /dev/null +++ b/Ubiquitous/XiZi/kernel/thread/banner.c @@ -0,0 +1,50 @@ +/* +* Copyright (c) 2020 AIIT XUOS Lab +* XiUOS is licensed under Mulan PSL v2. +* You can use this software according to the terms and conditions of the Mulan PSL v2. +* You may obtain a copy of Mulan PSL v2 at: +* http://license.coscl.org.cn/MulanPSL2 +* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, +* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, +* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. +* See the Mulan PSL v2 for more details. +*/ + +/** +* @file: banner.c +* @brief: system banner +* @version: 1.0 +* @author: AIIT XUOS Lab +* @date: 2020/4/15 +* +*/ + +#include + +/** + * This function will show the version of XiZi + */ +void ShowBanner(void) +{ + KPrintf("*********************************************************************************************\n"); + KPrintf("AAAAAAA AAAAAAA IIIIIIII IIIIIIII IIIIIIIII TTTTTTTTTTTTTTT \n"); + KPrintf("A:::::A A:::::A I::::::I I::::::I II:::::::::II TT:::::::::::::::T \n"); + KPrintf("A:::::A A:::::A iiii I::::::I I::::::I II:::::::::::::II T:::::TTTTTT::::::T \n"); + KPrintf("A::::::A A::::::A i::::i II:::::I I:::::III:::::::III:::::::IT:::::T TTTTTTT\n"); + KPrintf("AAA:::::A A:::::AAA iiii I:::::I I:::::I I::::::I I::::::IT:::::T \n"); + KPrintf(" A:::::A A:::::A I:::::I I:::::I I:::::I I:::::IT:::::T \n"); + KPrintf(" A:::::A:::::A iiiiiii I:::::I I:::::I I:::::I I:::::I T::::TTTT \n"); + KPrintf(" A:::::::::A i:::::i I:::::I I:::::I I:::::I I:::::I TT::::::TTTTT \n"); + KPrintf(" A:::::::::A i::::i I:::::I I:::::I I:::::I I:::::I TTT::::::::TT \n"); + KPrintf(" A:::::A:::::A i::::i I:::::I I:::::I I:::::I I:::::I TTTTTT::::T \n"); + KPrintf(" A:::::A A:::::A i::::i I:::::I I:::::I I:::::I I:::::I T:::::T\n"); + KPrintf("AAA:::::A A:::::AAA i::::i I::::::I I::::::I I::::::I I::::::I T:::::T\n"); + KPrintf("A::::::A A::::::A i::::i I:::::::III:::::::I I:::::::III:::::::ITTTTTTT T:::::T\n"); + KPrintf("A:::::A A:::::A i::::i II:::::::::::::II II:::::::::::::II T::::::TTTTTT:::::T \n"); + KPrintf("A:::::A A:::::A i::::::i II:::::::::II II:::::::::II T:::::::::::::::TT \n"); + KPrintf("AAAAAAA AAAAAAA iiiiiiii IIIIIIIII IIIIIIIII TTTTTTTTTTTTTTT \n"); + KPrintf("*********************************************************************************************\n"); + KPrintf("*********************-----X Industrial Ubiquitous Operating System-----**********************\n"); + KPrintf("***************************2021 Copyright AIIT Ubiquitous-OS Team****************************\n"); + KPrintf("*********************************************************************************************\n"); +} \ No newline at end of file diff --git a/Ubiquitous/XiZi/kernel/thread/bitmap.c b/Ubiquitous/XiZi/kernel/thread/bitmap.c new file mode 100644 index 0000000..1c9b156 --- /dev/null +++ b/Ubiquitous/XiZi/kernel/thread/bitmap.c @@ -0,0 +1,66 @@ +/* +* Copyright (c) 2020 AIIT XUOS Lab +* XiUOS is licensed under Mulan PSL v2. +* You can use this software according to the terms and conditions of the Mulan PSL v2. +* You may obtain a copy of Mulan PSL v2 at: +* http://license.coscl.org.cn/MulanPSL2 +* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, +* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, +* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. +* See the Mulan PSL v2 for more details. +*/ + +/** +* @file: bitmap.c +* @brief: calculate the highest priority +* @version: 1.0 +* @author: AIIT XUOS Lab +* @date: 2020/3/15 +* +*/ + +#include + +const uint8 LeaderZeroCount[] = +{ + 8, 7, 6, 6, 5, 5, 5, 5, 4, 4, 4, 4, 4, 4, 4, 4, + 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, + 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, + 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, + 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, + 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, + 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, + 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +int PrioCaculate(uint32 bitmap) +{ + if (bitmap & 0xff000000) + { + return 31 - LeaderZeroCount[(bitmap & 0xff000000) >> 24]; + } + else if (bitmap & 0xff0000) + { + return 23 - LeaderZeroCount[(bitmap & 0xff0000) >> 16]; + } + else if (bitmap & 0xff00) + { + return 15 - LeaderZeroCount[(bitmap & 0xff00) >> 8]; + } + else if (bitmap & 0xff) + { + return 7 - LeaderZeroCount[bitmap & 0xff]; + } + else + { + return 0; + } +} diff --git a/Ubiquitous/XiZi/kernel/thread/circular_area.c b/Ubiquitous/XiZi/kernel/thread/circular_area.c new file mode 100644 index 0000000..92809e5 --- /dev/null +++ b/Ubiquitous/XiZi/kernel/thread/circular_area.c @@ -0,0 +1,279 @@ +/* +* Copyright (c) 2020 AIIT XUOS Lab +* XiUOS is licensed under Mulan PSL v2. +* You can use this software according to the terms and conditions of the Mulan PSL v2. +* You may obtain a copy of Mulan PSL v2 at: +* http://license.coscl.org.cn/MulanPSL2 +* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, +* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, +* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. +* See the Mulan PSL v2 for more details. +*/ + +/** +* @file: circular_area.c +* @brief: circular area file +* @version: 1.0 +* @author: AIIT XUOS Lab +* @date: 2020/3/15 +* +*/ + +#include "xs_circular_area.h" +#include +#include +#include +#include + +/** + * This function will return whether the circular_area is full or not + * + * @param circular_area CircularArea descriptor + */ +x_bool CircularAreaIsFull(CircularAreaType circular_area) +{ + NULL_PARAM_CHECK(circular_area); + + if((circular_area->readidx == circular_area->writeidx) && (circular_area->b_status)) { + KPrintf("the circular area is full\n"); + return RET_TRUE; + } else { + return RET_FALSE; + } +} + +/** + * This function will return whether the circular_area is empty or not + * + * @param circular_area CircularArea descriptor + */ +x_bool CircularAreaIsEmpty(CircularAreaType circular_area) +{ + NULL_PARAM_CHECK(circular_area); + + if((circular_area->readidx == circular_area->writeidx) && (!circular_area->b_status)) { + KPrintf("the circular area is empty\n"); + return RET_TRUE; + } else { + return RET_FALSE; + } +} + +/** + * This function will reset the circular_area and set the descriptor to default + * + * @param circular_area CircularArea descriptor + */ +void CircularAreaReset(CircularAreaType circular_area) +{ + circular_area->writeidx = 0; + circular_area->readidx = 0; + circular_area->b_status = RET_FALSE; +} + +/** + * This function will release the circular_area descriptor and free the memory + * + * @param circular_area CircularArea descriptor + */ +void CircularAreaRelease(CircularAreaType circular_area) +{ + circular_area->readidx = 0; + circular_area->writeidx = 0; + circular_area->p_head = NONE; + circular_area->p_tail = NONE; + circular_area->b_status = RET_FALSE; + circular_area->area_length = 0; + + x_free(circular_area->data_buffer); + x_free(circular_area); +} + +/** + * This function will get the circual_area max length + * + * @param circular_area CircularArea descriptor + */ +uint32 CircularAreaGetMaxLength(CircularAreaType circular_area) +{ + NULL_PARAM_CHECK(circular_area); + + return circular_area->area_length; +} + +/** + * This function will get the data length of the circular_area + * + * @param circular_area CircularArea descriptor + */ +uint32 CircularAreaGetDataLength(CircularAreaType circular_area) +{ + NULL_PARAM_CHECK(circular_area); + + if(CircularAreaIsFull(circular_area)) { + return circular_area->area_length; + } else { + return (circular_area->writeidx - circular_area->readidx + circular_area->area_length) % circular_area->area_length; + } +} + +/** + * This function will return whether it is need to divide the read data into two parts or not + * + * @param circular_area CircularArea descriptor + * @param data_length output data length + */ +static uint32 CircularAreaDivideRdData(CircularAreaType circular_area, uint32 data_length) +{ + NULL_PARAM_CHECK(circular_area); + + if(circular_area->readidx + data_length <= circular_area->area_length) { + return RET_FALSE; + } else { + return RET_TRUE; + } +} + +/** + * This function will return whether it is need to divide the write data into two parts or not + * + * @param circular_area CircularArea descriptor + * @param data_length input data length + */ +static uint32 CircularAreaDivideWrData(CircularAreaType circular_area, uint32 data_length) +{ + NULL_PARAM_CHECK(circular_area); + + if(circular_area->writeidx + data_length <= circular_area->area_length) { + return RET_FALSE; + } else { + return RET_TRUE; + } +} + +/** + * This function will read data from the circular_area + * + * @param circular_area CircularArea descriptor + * @param output_buffer output data buffer poniter + * @param data_length output data length + */ +uint32 CircularAreaRead(CircularAreaType circular_area, uint8 *output_buffer, uint32 data_length) +{ + NULL_PARAM_CHECK(circular_area); + NULL_PARAM_CHECK(output_buffer); + CHECK(data_length > 0); + + if(CircularAreaIsEmpty(circular_area)) { + return ERROR; + } + + data_length = (data_length > CircularAreaGetDataLength(circular_area)) ? CircularAreaGetDataLength(circular_area) : data_length; + + if(CircularAreaDivideRdData(circular_area, data_length)) { + uint32 read_len_up = circular_area->area_length - circular_area->readidx; + uint32 read_len_down = data_length - read_len_up; + + memcpy(output_buffer, &circular_area->data_buffer[circular_area->readidx], read_len_up); + memcpy(output_buffer + read_len_up, circular_area->p_head, read_len_down); + + circular_area->readidx = read_len_down; + } else { + memcpy(output_buffer, &circular_area->data_buffer[circular_area->readidx], data_length); + circular_area->readidx = (circular_area->readidx + data_length) % circular_area->area_length; + } + + circular_area->b_status = RET_FALSE; + + return EOK; +} + +/** + * This function will write data to the circular_area + * + * @param circular_area CircularArea descriptor + * @param input_buffer input data buffer poniter + * @param data_length input data length + * @param b_force whether to force to write data disregard the length limit + */ +uint32 CircularAreaWrite(CircularAreaType circular_area, uint8 *input_buffer, uint32 data_length, x_bool b_force) +{ + NULL_PARAM_CHECK(circular_area); + NULL_PARAM_CHECK(input_buffer); + CHECK(data_length > 0); + + if(CircularAreaIsFull(circular_area) && (!b_force)) { + return ERROR; + } + + uint32 write_data_length = circular_area->area_length - CircularAreaGetDataLength(circular_area); + data_length = (data_length > write_data_length) ? write_data_length : data_length; + + if(CircularAreaDivideWrData(circular_area, data_length)) { + uint32 write_len_up = circular_area->area_length - circular_area->writeidx; + uint32 write_len_down = data_length - write_len_up; + + memcpy(&circular_area->data_buffer[circular_area->writeidx], input_buffer, write_len_up); + memcpy(circular_area->p_head, input_buffer + write_len_up, write_len_down); + + circular_area->writeidx = write_len_down; + } else { + memcpy(&circular_area->data_buffer[circular_area->writeidx], input_buffer, data_length); + circular_area->writeidx = (circular_area->writeidx + data_length) % circular_area->area_length; + } + + circular_area->b_status = RET_TRUE; + + if(b_force) { + circular_area->readidx = circular_area->writeidx; + } + + return EOK; +} + +static struct CircularAreaOps CircularAreaOperations = +{ + CircularAreaRead, + CircularAreaWrite, + CircularAreaRelease, + CircularAreaReset, +}; + +/** + * This function will initialize the circular_area + * + * @param circular_area_length circular_area length + */ +CircularAreaType CircularAreaInit(uint32 circular_area_length) +{ + CHECK(circular_area_length > 0); + + circular_area_length = ALIGN_MEN_DOWN(circular_area_length, MEM_ALIGN_SIZE); + + CircularAreaType circular_area = x_malloc(sizeof(struct CircularArea)); + if(NONE == circular_area) { + KPrintf("CircularAreaInit malloc struct circular_area failed\n"); + x_free(circular_area); + return NONE; + } + + CircularAreaReset(circular_area); + + circular_area->data_buffer = x_malloc(circular_area_length); + if(NONE == circular_area->data_buffer) { + KPrintf("CircularAreaInit malloc circular_area data_buffer failed\n"); + x_free(circular_area->data_buffer); + return NONE; + } + + circular_area->p_head = circular_area->data_buffer; + circular_area->p_tail = circular_area->data_buffer + circular_area_length; + circular_area->area_length = circular_area_length; + + KPrintf("CircularAreaInit done p_head %8p p_tail %8p length %u\n", + circular_area->p_head, circular_area->p_tail, circular_area->area_length); + + circular_area->CircularAreaOperations = &CircularAreaOperations; + + return circular_area; +} diff --git a/Ubiquitous/XiZi/kernel/thread/console.c b/Ubiquitous/XiZi/kernel/thread/console.c new file mode 100644 index 0000000..6bdecbb --- /dev/null +++ b/Ubiquitous/XiZi/kernel/thread/console.c @@ -0,0 +1,685 @@ +/* +* Copyright (c) 2020 AIIT XUOS Lab +* XiUOS is licensed under Mulan PSL v2. +* You can use this software according to the terms and conditions of the Mulan PSL v2. +* You may obtain a copy of Mulan PSL v2 at: +* http://license.coscl.org.cn/MulanPSL2 +* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, +* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, +* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. +* See the Mulan PSL v2 for more details. +*/ + +/** +* @file: console.c +* @brief: console file +* @version: 1.0 +* @author: AIIT XUOS Lab +* @date: 2020/3/15 +* +*/ + + +#include +#include + +#if defined(KERNEL_CONSOLE) +static HardwareDevType _console = NONE; +#endif + +/** + * Obtain the console + * + */ +HardwareDevType ObtainConsole(void) +{ +#if defined(KERNEL_CONSOLE) + return _console; +#endif +} + +/** + * Setup a console + * + * + * @param name console device name + * + */ +void InstallConsole(const char *bus_name, const char *drv_name, const char *dev_name) +{ +#if defined(KERNEL_CONSOLE) + BusType console_bus; + DriverType console_drv = NONE; + HardwareDevType console = NONE; + struct SerialDevParam *serial_dev_param = NONE; + struct SerialCfgParam serial_cfg; + struct BusConfigureInfo configure_info; + + NULL_PARAM_CHECK(bus_name); + NULL_PARAM_CHECK(drv_name); + NULL_PARAM_CHECK(dev_name); + + console_bus = BusFind(bus_name); + console_drv = BusFindDriver(console_bus, drv_name); + console = BusFindDevice(console_bus, dev_name); + + if (console != NONE) { + if (_console != NONE) { + BusDevClose(_console); + } + + configure_info.configure_cmd = OPE_INT; + memset(&serial_cfg, 0, sizeof(struct SerialCfgParam)); + configure_info.private_data = &serial_cfg; + BusDrvConfigure(console_drv, &configure_info); + console_bus->match(console_drv, console); + + serial_dev_param = (struct SerialDevParam *)console->private_data; + serial_dev_param->serial_set_mode = 0; + serial_dev_param->serial_stream_mode = SIGN_OPER_STREAM; + BusDevOpen(console); + _console = console; + } else { + console = _console; + } +#endif +} + +#if defined(KERNEL_CONSOLE) + +static __inline x_bool IsDigit(char c) +{ + return ((unsigned)((c) - '0') < 10); +} + +static __inline unsigned int CharToNum(const char **s) +{ + unsigned int i = 0; + while (IsDigit(**s)) { + i = i * 10 + **s - '0'; + ++ *s; + } + + return i; +} + +#define ZEROPAD (1 << 0) +#define LEFT (1 << 1) +#define SIGN (1 << 2) +#define SPACE (1 << 3) +#define HASH (1 << 4) + +#define PRINTLONG (1 << 5) +#define PRINTLONGLONG (1 << 6) +#define PRINTSHORT (1 << 7) +#define PRINTCHAR (1 << 8) + +#define CAPITAL (1 << 9) + +static size_t LongToChar(char* str, unsigned long value, uint32 flags, int32 precision, uint8 base, int32 width, x_bool minus, int32 pointer, int32 size) +{ + char buff[KERNEL_CONSOLEBUF_SIZE/4] = {0}; + int32 length = 0; + + if(!value) + flags &= ~HASH; + + if(!(precision > 0) || value) { + do { + const char number = (char)(value % base); + if(number < 10) { + buff[length] = number + '0'; + } else { + if(flags & CAPITAL) + buff[length] = 'A' + number - 10; + else + buff[length] = 'a' + number - 10; + } + ++ length; + value /= base; + } while (value && (length < KERNEL_CONSOLEBUF_SIZE/4)); + } + + if(!(flags & LEFT)) { + if(width && (minus || (flags & (SIGN | SPACE | ZEROPAD)))) + -- width; + while((length < precision) && (length < KERNEL_CONSOLEBUF_SIZE/4)) + buff[length++] = '0'; + while((length < width) && (flags & ZEROPAD) && (length < KERNEL_CONSOLEBUF_SIZE/4)) + buff[length++] = '0'; + } + + if((flags & HASH) && ((base == 8) || (base == 16))) { + if(!(precision > 0) && length && ((length == precision) || (length == width))) { + -- length; + if(length && (base == 16)) + -- length; + } + switch (base) { + case 8: + buff[length++] = '0'; + break; + + case 16: + if(flags & CAPITAL) + { + buff[length++] = 'X'; + buff[length++] = '0'; + } + else + { + buff[length++] = 'x'; + buff[length++] = '0'; + } + break; + + default: + break; + } + } + + if(length < KERNEL_CONSOLEBUF_SIZE/4) { + if(minus) + buff[length++] = '-'; + else if(flags & SIGN) + buff[length++] = '+'; + else if(flags & SPACE) + buff[length++] = ' '; + } + + const int32 index = pointer; + + if(!(flags & LEFT) && !(flags & ZEROPAD) && (length < width)) { + for(int32 i = length; i < width; i++) { + str[pointer++] = ' '; + if(pointer >= size) { + str[size - 1] = '\0'; + return size; + } + } + } + + while (length) { + str[pointer++] = buff[--length]; + if(pointer >= size) { + str[size - 1] = '\0'; + return size; + } + } + + if(flags & LEFT) { + while (pointer - index < width) { + str[pointer++] = ' '; + if(pointer >= size) { + str[size - 1] = '\0'; + return size; + } + } + } + + return pointer; +} + +static size_t LonglongToChar(char* str, unsigned long long value, uint32 flags, int32 precision, uint8 base, int32 width, x_bool minus, int32 pointer, int32 size) +{ + char buff[KERNEL_CONSOLEBUF_SIZE/4] = {0}; + int32 length = 0; + + if(!value) + flags &= ~HASH; + + if(!(precision > 0) || value){ + do { + const char number = (char)(value % base); + if(number < 10) { + buff[length] = number + '0'; + } else { + if(flags & CAPITAL) + buff[length] = 'A' + number - 10; + else + buff[length] = 'a' + number - 10; + } + ++ length; + value /= base; + } while (value && (length < KERNEL_CONSOLEBUF_SIZE/4)); + } + + if(!(flags & LEFT)) { + if(width && (minus || (flags & (SIGN | SPACE | ZEROPAD)))) + -- width; + while((length < precision) && (length < KERNEL_CONSOLEBUF_SIZE/4)) + buff[length++] = '0'; + while((length < width) && (flags & ZEROPAD) && (length < KERNEL_CONSOLEBUF_SIZE/4)) + buff[length++] = '0'; + } + + if((flags & HASH) && ((base == 8) || (base == 16))) { + if(!(precision > 0) && length && ((length == precision) || (length == width))) { + -- length; + if(length && (base == 16)) + -- length; + } + switch (base) { + case 8: + buff[length++] = '0'; + break; + + case 16: + if(flags & CAPITAL) { + buff[length++] = 'X'; + buff[length++] = '0'; + } else { + buff[length++] = 'x'; + buff[length++] = '0'; + } + break; + + default: + break; + } + } + + if(length < KERNEL_CONSOLEBUF_SIZE/4) { + if(minus) + buff[length++] = '-'; + else if(flags & SIGN) + buff[length++] = '+'; + else if(flags & SPACE) + buff[length++] = ' '; + } + + const int32 index = pointer; + + if(!(flags & LEFT) && !(flags & ZEROPAD) && (length < width)) { + for(int32 i = length; i < width; i++) { + str[pointer++] = ' '; + if(pointer >= size) { + str[size - 1] = '\0'; + return size; + } + } + } + + while (length) { + str[pointer++] = buff[--length]; + if(pointer >= size) { + str[size - 1] = '\0'; + return size; + } + } + + if(flags & LEFT) { + while (pointer - index < width) { + str[pointer++] = ' '; + if(pointer >= size) { + str[size - 1] = '\0'; + return size; + } + } + } + + return pointer; +} + +int VsnPrintf(char *buf, int32 size, const char *fmt, va_list args) +{ + NULL_PARAM_CHECK(buf); + + int32 pointer = 0; + int32 len = 0; + int32 i = 0; + int32 width = 0; + int32 precision = 0; + uint32 flags = 0; + uint8 base = 0; + char c = 0; + char *str = NONE; + char *s = NONE; + + pointer = 0; + str = buf; + + while(*fmt) { + if (*fmt != '%') { + buf[pointer++] = *fmt; + if(pointer >= size) { + buf[size - 1] = '\0'; + return size - 1; + } + ++ fmt; + continue; + } + + flags = 0; + uint8 CheckFlags = 1; + + while (CheckFlags) { + ++ fmt; + switch (*fmt) { + case '0': + flags |= ZEROPAD; + break; + + case '-': + flags |= LEFT; + break; + + case '+': + flags |= SIGN; + break; + + case ' ': + flags |= SPACE; + break; + + case '#': + flags |= HASH; + break; + + default: + CheckFlags = 0; + break; + } + } + + width = -1; + if (IsDigit(*fmt)) + width = CharToNum(&fmt); + else if (*fmt == '*') { + width = va_arg(args, int); + if (width < 0) { + width = -width; + flags |= LEFT; + } + ++ fmt; + } + + precision = -1; + if (*fmt == '.') { + ++ fmt; + if (IsDigit(*fmt)) + precision = CharToNum(&fmt); + else if (*fmt == '*') { + precision = va_arg(args, int); + ++ fmt; + } + if (precision < 0) + precision = 0; + } + + if (*fmt == 'l') { + ++ fmt; + if (*fmt == 'l') { + flags |= PRINTLONGLONG; + ++ fmt; + } + else + flags |= PRINTLONG; + } + else if(*fmt == 'h') { + ++ fmt; + if (*fmt == 'h') { + flags |= PRINTCHAR; + ++ fmt; + } + else + flags |= PRINTSHORT; + } + + base = 10; + + switch (*fmt) { + case 'c': + if (!(flags & LEFT)) { + while (--width > 0) { + buf[pointer++] = ' '; + if(pointer >= size) + { + buf[size - 1] = '\0'; + return size - 1; + } + } + } + + c = (char)va_arg(args, int); + buf[pointer++] = c; + if(pointer >= size) { + buf[size - 1] = '\0'; + return size - 1; + } + + while (--width > 0) { + buf[pointer++] = ' '; + if(pointer >= size) { + buf[size - 1] = '\0'; + return size - 1; + } + } + break; + + case 's': + s = va_arg(args, char *); + if (!s) + s = "(NULL)"; + + len = strlen(s); + if (precision > 0 && len > precision) + len = precision; + + if (!(flags & LEFT)) { + while (len < width--) { + buf[pointer++] = ' '; + if(pointer >= size) { + buf[size - 1] = '\0'; + return size - 1; + } + } + } + + for (i = 0; i < len; ++ i) { + buf[pointer++] = *s; + if(pointer >= size) { + buf[size - 1] = '\0'; + return size - 1; + } + ++ s; + } + + while (len < width--) { + buf[pointer++] = ' '; + if(pointer >= size) { + buf[size - 1] = '\0'; + return size - 1; + } + } + break; + + case 'p': + width = sizeof(void *) * 2; + flags |= ZEROPAD | CAPITAL; + /* Determine the machine word length */ +#ifdef ARCH_CPU_64BIT + if(sizeof(long) == sizeof(long long)) + pointer = (long)LonglongToChar(buf, (unsigned long)va_arg(args, void*), flags, precision, 16, width, 0, pointer, size); + else +#endif + pointer = LongToChar(buf, (unsigned long)va_arg(args, void*), flags, precision, 16, width, 0, pointer, size); + + if(pointer >= size) { + buf[size - 1] = '\0'; + return size - 1; + } + break; + + case '%': + buf[pointer] = '%'; + ++ pointer; + break; + + case 'o': + flags &= ~SIGN; + base = 8; + if(flags & PRINTLONGLONG) + pointer = LonglongToChar(buf, va_arg(args, unsigned long long), flags, precision, base, width, 0, pointer, size); + else if(flags & PRINTLONG) + pointer = LongToChar(buf, va_arg(args, unsigned long), flags, precision, base, width, 0, pointer, size); + else { + if(flags & PRINTSHORT) { + const unsigned int value = (unsigned short int)va_arg(args, unsigned int); + pointer = LongToChar(buf, value, flags, precision, base, width, 0, pointer, size); + } else if(flags & PRINTCHAR) { + const unsigned int value = (unsigned char)va_arg(args, unsigned int); + pointer = LongToChar(buf, value, flags, precision, base, width, 0, pointer, size); + } else { + const unsigned int value = va_arg(args, unsigned int); + pointer = LongToChar(buf, value, flags, precision, base, width, 0, pointer, size); + } + } + + if(pointer >= size) { + buf[size - 1] = '\0'; + return size - 1; + } + break; + + case 'X': + flags |= CAPITAL; + case 'x': + flags &= ~SIGN; + base = 16; + + if(flags & PRINTLONGLONG) + pointer = LonglongToChar(buf, va_arg(args, unsigned long long), flags, precision, base, width, 0, pointer, size); + else if(flags & PRINTLONG) + pointer = LongToChar(buf, va_arg(args, unsigned long), flags, precision, base, width, 0, pointer, size); + else { + if(flags & PRINTSHORT) { + const unsigned int value = (unsigned short int)va_arg(args, unsigned int); + pointer = LongToChar(buf, value, flags, precision, base, width, 0, pointer, size); + } else if(flags & PRINTCHAR) { + const unsigned int value = (unsigned char)va_arg(args, unsigned int); + pointer = LongToChar(buf, value, flags, precision, base, width, 0, pointer, size); + } else { + const unsigned int value = va_arg(args, unsigned int); + pointer = LongToChar(buf, value, flags, precision, base, width, 0, pointer, size); + } + } + + if(pointer >= size) { + buf[size - 1] = '\0'; + return size - 1; + } + break; + + case 'u': + flags &= ~SIGN; + base = 10; + flags &= ~HASH; + if(flags & PRINTLONGLONG) + pointer = LonglongToChar(buf, va_arg(args, unsigned long long), flags, precision, base, width, 0, pointer, size); + else if(flags & PRINTLONG) + pointer = LongToChar(buf, va_arg(args, unsigned long), flags, precision, base, width, 0, pointer, size); + else { + if(flags & PRINTSHORT) { + const unsigned int value = (unsigned short int)va_arg(args, unsigned int); + pointer = LongToChar(buf, value, flags, precision, base, width, 0, pointer, size); + } else if(flags & PRINTCHAR) { + const unsigned int value = (unsigned char)va_arg(args, unsigned int); + pointer = LongToChar(buf, value, flags, precision, base, width, 0, pointer, size); + } else { + const unsigned int value = va_arg(args, unsigned int); + pointer = LongToChar(buf, value, flags, precision, base, width, 0, pointer, size); + } + } + + if(pointer >= size) { + buf[size - 1] = '\0'; + return size - 1; + } + break; + + case 'd': + case 'i': + base = 10; + flags &= ~HASH; + if(flags & PRINTLONGLONG) { + const long long value = va_arg(args, long long); + pointer = LonglongToChar(buf, (unsigned long long)(value > 0 ? value : 0 - value), flags, precision, base, width, (value < 0 ? 1 : 0), pointer, size); + } else if(flags & PRINTLONG) { + const long value = va_arg(args, long); + pointer = LongToChar(buf, (unsigned long)(value > 0 ? value : 0 - value), flags, precision, base, width, (value < 0 ? 1 : 0), pointer, size); + } else { + if(flags & PRINTSHORT) { + const int value = (short int)va_arg(args, int); + pointer = LongToChar(buf, (unsigned int)(value > 0 ? value : 0 - value), flags, precision, base, width, (value < 0 ? 1 : 0), pointer, size); + } else if(flags & PRINTCHAR) { + const int value = (char)va_arg(args, int); + pointer = LongToChar(buf, (unsigned int)(value > 0 ? value : 0 - value), flags, precision, base, width, (value < 0 ? 1 : 0), pointer, size); + } else { + const int value = va_arg(args, int); + pointer = LongToChar(buf, (unsigned int)(value > 0 ? value : 0 - value), flags, precision, base, width, (value < 0 ? 1 : 0), pointer, size); + } + } + + if(pointer >= size) { + buf[size - 1] = '\0'; + return size - 1; + } + break; + + default: + buf[pointer++] = '%'; + if(pointer >= size) { + buf[size - 1] = '\0'; + return size - 1; + } + + if (*fmt) { + buf[pointer++] = *fmt; + if(pointer >= size) { + buf[size - 1] = '\0'; + return size - 1; + } + } else { + -- fmt; + } + break; + } + ++ fmt; + } + + if(pointer > size) + pointer = size - 1; + buf[pointer] = '\0'; + + return pointer; +} + +#endif + +void KPrintf(const char *fmt, ...) +{ +#ifdef KERNEL_CONSOLE + if(_console != NONE) { + va_list args; + x_size_t length = 0; + static char logbuf[KERNEL_CONSOLEBUF_SIZE] = {0}; + + va_start(args, fmt); + + length = VsnPrintf(logbuf, sizeof(logbuf) - 1, fmt, args); + if (length > KERNEL_CONSOLEBUF_SIZE - 1) + length = KERNEL_CONSOLEBUF_SIZE - 1; + + struct BusBlockWriteParam write_param; + write_param.pos = 0; + write_param.buffer = (void *)logbuf; + write_param.size = length; + BusDevWriteData(_console, (void *)&write_param); + + va_end(args); + } +#endif +} + + diff --git a/Ubiquitous/XiZi/kernel/thread/data_queue.c b/Ubiquitous/XiZi/kernel/thread/data_queue.c new file mode 100644 index 0000000..c1cff36 --- /dev/null +++ b/Ubiquitous/XiZi/kernel/thread/data_queue.c @@ -0,0 +1,233 @@ +/* +* Copyright (c) 2020 AIIT XUOS Lab +* XiUOS is licensed under Mulan PSL v2. +* You can use this software according to the terms and conditions of the Mulan PSL v2. +* You may obtain a copy of Mulan PSL v2 at: +* http://license.coscl.org.cn/MulanPSL2 +* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, +* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, +* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. +* See the Mulan PSL v2 for more details. +*/ + +/** +* @file: data_queue.c +* @brief: data queue file +* @version: 1.0 +* @author: AIIT XUOS Lab +* @date: 2020/3/15 +* +*/ + +#include +#include + +/** + * This function allocates dynamic memory from dynamic buddy memory. + * + * @param p_queue dataqueue structure + * @param NodeNumber the number of dataqueue + * + * @return EOK on success; ERROR on failure + */ +x_err_t InitDataqueue(DataQueueType *p_queue, uint16 NodeNumber) +{ + x_base lock = 0; + + NULL_PARAM_CHECK(p_queue); + + KPrintf("InitDataqueue\n"); + + lock = CriticalAreaLock(); + do { + memset(p_queue, 0, sizeof(DataQueueType)); + p_queue->front = p_queue->rear = 0; + p_queue->max_len = NodeNumber; + p_queue->base = (DataElemType *)x_malloc(p_queue->max_len * sizeof(DataElemType)); + if (!p_queue->base) { + break; + } + + // The semaphore is initialized to len-1, because the full condition of the loop queue is real + 1 = = front, + // a vacancy is always wasted + p_queue->sem_blank = KSemaphoreCreate( p_queue->max_len - 1); + if (!p_queue->sem_blank) { + break; + } + + p_queue->sem_data = KSemaphoreCreate( 0); + if (!p_queue->sem_data) { + break; + } + + CriticalAreaUnLock(lock); + return EOK; + } while (0); + + CriticalAreaUnLock(lock); + DeInitDataqueue(p_queue); + return -ERROR; +} + +/** + * This function realses all dataqueue resource. + * + * @param p_queue dataqueue structure + * + */ + +void DeInitDataqueue(DataQueueType *p_queue) +{ + x_base lock = 0; + + NULL_PARAM_CHECK(p_queue); + + KPrintf("DeInitDataqueue\n"); + + lock = DISABLE_INTERRUPT(); + + if (p_queue->base) { + x_free(p_queue->base); + p_queue->base = NONE; + } + + if (p_queue->sem_blank) { + KSemaphoreDelete(p_queue->sem_blank); + p_queue->sem_blank = NONE; + } + + if (p_queue->sem_data) { + KSemaphoreDelete(p_queue->sem_data); + p_queue->sem_data = NONE; + } + ENABLE_INTERRUPT(lock); +} + +/** + * This function will push a data into dataqueue . + * + * @param p_queue dataqueue structure + * @param StartAddr the data needed to be pushed + * @param DataSize data size + * @param timeout timeout + * + * @return EOK on success; ERROR on failure + */ +x_err_t PushDataqueue(DataQueueType *p_queue, const void *StartAddr, x_size_t DataSize, int32 timeout) +{ + x_base lock = 0; + + NULL_PARAM_CHECK(p_queue); + NULL_PARAM_CHECK(StartAddr); + + KPrintf("PushDataqueue\n"); + + do { + if (WAITING_FOREVER == timeout) { + // block + KSemaphoreObtain(p_queue->sem_blank, WAITING_FOREVER); + break; + } else if (0 == timeout) { + // Nonblocking + if (EOK == KSemaphoreObtain(p_queue->sem_blank, 0)) { + break; + } else { + return -ERROR; + } + } + } while (0); + + lock = CriticalAreaLock(); + + if ((p_queue->rear + 1) % p_queue->max_len != p_queue->front) { + DataElemType *pElem = &(p_queue->base[p_queue->rear]); + pElem->data = StartAddr; + pElem->length = DataSize; + p_queue->rear = (p_queue->rear + 1) % p_queue->max_len; + } + CriticalAreaUnLock(lock); + + KSemaphoreAbandon(p_queue->sem_data); + return EOK; +} + +/** + * This function will pop a data from dataqueue . + * + * @param p_queue dataqueue structure + * @param StartAddr the data needed to be popped + * @param DataSize data size + * @param timeout timeout + * + * @return EOK on success; ERROR on failure + */ +x_err_t PopDataqueue(DataQueueType *p_queue, const void **StartAddr, x_size_t *size, int32 timeout) +{ + x_base lock = 0; + + NULL_PARAM_CHECK(p_queue); + + KPrintf("PopDataqueue\n"); + + do { + if (WAITING_FOREVER == timeout) { + // block + KSemaphoreObtain(p_queue->sem_data, WAITING_FOREVER); + break; + } else if (0 == timeout) { + // Nonblocking + if (EOK == KSemaphoreObtain(p_queue->sem_data, 0)) { + // Get success + break; + } else { + // Get failed, exit directly + return -ERROR; + } + } + } while (0); + + + lock = CriticalAreaLock(); + // Semaphore surplus, read data directly + if (p_queue->front != p_queue->rear) { + DataElemType *pElem = &(p_queue->base[p_queue->front]); + *StartAddr = pElem->data; + *size = pElem->length; + p_queue->front = (p_queue->front + 1) % p_queue->max_len; + } + CriticalAreaUnLock(lock); + + // Release data semaphore + KSemaphoreAbandon(p_queue->sem_blank); + return EOK; +} + +/** + * This function will get the first data of dataqueue . + * + * @param p_queue dataqueue structure + * @param StartAddr the data needed to be popped + * @param size data size + * + * @return EOK on success; ERROR on failure + */ +x_err_t DataqueuePeak(DataQueueType *p_queue, const void **StartAddr, x_size_t *size) +{ + x_base lock = 0; + + NULL_PARAM_CHECK(p_queue); + + KPrintf("DataqueuePeak\n"); + + if (p_queue->front != p_queue->rear) { + + lock = CriticalAreaLock(); + DataElemType *pElem = &(p_queue->base[p_queue->front]); + *StartAddr = pElem->data; + *size = pElem->length; + CriticalAreaUnLock(lock); + return EOK; + } else { + return -ERROR; + } +} \ No newline at end of file diff --git a/Ubiquitous/XiZi/kernel/thread/delay.c b/Ubiquitous/XiZi/kernel/thread/delay.c new file mode 100644 index 0000000..1cbdaba --- /dev/null +++ b/Ubiquitous/XiZi/kernel/thread/delay.c @@ -0,0 +1,150 @@ +/* +* Copyright (c) 2020 AIIT XUOS Lab +* XiUOS is licensed under Mulan PSL v2. +* You can use this software according to the terms and conditions of the Mulan PSL v2. +* You may obtain a copy of Mulan PSL v2 at: +* http://license.coscl.org.cn/MulanPSL2 +* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, +* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, +* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. +* See the Mulan PSL v2 for more details. +*/ + +/** +* @file: delay.c +* @brief: set task delay and check the timeout +* @version: 1.0 +* @author: AIIT XUOS Lab +* @date: 2020/3/15 +* +*/ + +#include +#include +#include +#include +#include +#include +#include + +DoubleLinklistType xiaoshan_delay_head = {&xiaoshan_delay_head, &xiaoshan_delay_head}; + +/** + * This function will delay a task with sone ticks. + * + * @param task the task needed to be delayed + * @param ticks delay timeout + * + * @return EOK on success; ENOMEMORY on failure + */ +x_err_t KTaskSetDelay(KTaskDescriptorType task, x_ticks_t ticks) +{ + x_base lock = 0; + struct Delay *delay = NONE; + struct Delay *dnode = NONE; + DoubleLinklistType *nodelink = NONE; + + NULL_PARAM_CHECK(task); + + if (task->task_dync_sched_member.delay == NONE) { + delay = (struct Delay *)x_malloc(sizeof(struct Delay)); + if (delay == NONE) + { + return -ENOMEMORY; + } + memset(delay, 0x0, sizeof(struct Delay)); + task->task_dync_sched_member.delay = delay; + } else { + delay = task->task_dync_sched_member.delay; + lock = CriticalAreaLock(); + if(delay->status == TASK_DELAY_ACTIVE){ + delay->status = TASK_DELAY_INACTIVE; + DoubleLinkListRmNode(&(delay->link)); + } + CriticalAreaUnLock(lock); + } + + delay->ticks = CurrentTicksGain() + ticks; + delay->task = task; + delay->status = TASK_DELAY_ACTIVE; + + lock = CriticalAreaLock(); + DOUBLE_LINKLIST_FOR_EACH(nodelink, &xiaoshan_delay_head) { + dnode =CONTAINER_OF(nodelink, struct Delay, link); + if (delay->ticks < dnode->ticks) { + DoubleLinkListInsertNodeBefore(nodelink, &delay->link); + + break; + } + } + + if (nodelink == &xiaoshan_delay_head) { + DoubleLinkListInsertNodeBefore(&xiaoshan_delay_head, &(delay->link)); + } + + CriticalAreaUnLock(lock); + + return EOK; +} + +/** + * This function will wakeup a task from delay list. + * + * @param task the task needed to be wakeup + * + * @return EOK + */ +x_err_t KTaskUnSetDelay(KTaskDescriptorType task) +{ + x_base lock = 0; + struct Delay *delay = NONE; + + NULL_PARAM_CHECK(task); + + delay = task->task_dync_sched_member.delay; + + if( delay != NONE && delay->status == TASK_DELAY_ACTIVE) { + lock = CriticalAreaLock(); + delay->status = TASK_DELAY_INACTIVE; + DoubleLinkListRmNode(&(delay->link)); + CriticalAreaUnLock(lock); + } + + return EOK; +} + + +void CheckTaskDelay(void) +{ + x_base level = 0; + x_ticks_t current_tick = 0; + struct Delay *node = NONE; + + SYS_KDEBUG_LOG(0, ("delay check enter\n")); + + current_tick = CurrentTicksGain(); + + level = CriticalAreaLock(); + + while (!IsDoubleLinkListEmpty(&xiaoshan_delay_head)) + { + node = SYS_DOUBLE_LINKLIST_ENTRY(xiaoshan_delay_head.node_next, + struct Delay, link); + + if ((current_tick - node->ticks) < TICK_SIZE_MAX / 2) + { + current_tick = CurrentTicksGain(); + SYS_KDEBUG_LOG(KDBG_SOFTTIMER, ("current tick: %d\n", current_tick)); + KTaskUnSetDelay(node->task); + CriticalAreaUnLock(level); + KTaskTimeout(node->task); + level = CriticalAreaLock(); + } + else + break; + } + + CriticalAreaUnLock(level); + + SYS_KDEBUG_LOG(0, ("delay check leave\n")); +} \ No newline at end of file diff --git a/Ubiquitous/XiZi/kernel/thread/double_link.c b/Ubiquitous/XiZi/kernel/thread/double_link.c new file mode 100644 index 0000000..7a8e0c2 --- /dev/null +++ b/Ubiquitous/XiZi/kernel/thread/double_link.c @@ -0,0 +1,132 @@ +/* +* Copyright (c) 2020 AIIT XUOS Lab +* XiUOS is licensed under Mulan PSL v2. +* You can use this software according to the terms and conditions of the Mulan PSL v2. +* You may obtain a copy of Mulan PSL v2 at: +* http://license.coscl.org.cn/MulanPSL2 +* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, +* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, +* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. +* See the Mulan PSL v2 for more details. +*/ + +/** +* @file: double_link.c +* @brief: functions definition of double linklist +* @version: 1.0 +* @author: AIIT XUOS Lab +* @date: 2020/3/15 +* +*/ + + +#include + +/** + * This function will init a linklist. + * + * @param linklist_head linklist node + */ +void InitDoubleLinkList(DoubleLinklistType *linklist_head) +{ + linklist_head->node_next = linklist_head; + linklist_head->node_prev = linklist_head; +} + +/** + * This function will insert a node into list after the node. + * + * @param linklist linklist node + * @param linklist_node the node needed to inserted + */ +void DoubleLinkListInsertNodeAfter(DoubleLinklistType *linklist, DoubleLinklistType *linklist_node) +{ + linklist->node_next->node_prev = linklist_node; + linklist_node->node_next = linklist->node_next; + + linklist->node_next = linklist_node; + linklist_node->node_prev = linklist; +} + +/** + * This function will insert a node into list after the node. + * + * @param linklist linklist node + * @param linklist_node the node needed to inserted + */ +void DoubleLinkListInsertNodeBefore(DoubleLinklistType *linklist, DoubleLinklistType *linklist_node) +{ + linklist->node_prev->node_next = linklist_node; + linklist_node->node_prev = linklist->node_prev; + + linklist->node_prev = linklist_node; + linklist_node->node_next = linklist; +} + +/** + * This function will remove a node from the list. + * + * @param linklist_node the node needed to removed + */ +void DoubleLinkListRmNode(DoubleLinklistType *linklist_node) +{ + linklist_node->node_next->node_prev = linklist_node->node_prev; + linklist_node->node_prev->node_next = linklist_node->node_next; + + linklist_node->node_next = linklist_node; + linklist_node->node_prev = linklist_node; +} + +/** + * This function will judge the list is empty. + * + * @param linklist the list head + * @return true + */ +int IsDoubleLinkListEmpty(const DoubleLinklistType *linklist) +{ + return linklist->node_next == linklist; +} + +/** + * This function will get the head of the list. + * + * @param linklist list head + * @return list head + */ +struct SysDoubleLinklistNode *DoubleLinkListGetHead(const DoubleLinklistType *linklist) +{ + return IsDoubleLinkListEmpty(linklist) ? NONE : linklist->node_next; +} + +/** + * This function will get the next node of the list head. + * + * @param linklist list head + * @param linklist_node list head + * @return next node of the list head + */ +struct SysDoubleLinklistNode *DoubleLinkListGetNext(const DoubleLinklistType *linklist, + const struct SysDoubleLinklistNode *linklist_node) +{ + return linklist_node->node_next == linklist ? NONE : linklist_node->node_next; +} + +/** + * This function will get length of the list. + * + * @param linklist list head + * @return length + */ +unsigned int DoubleLinkListLenGet(const DoubleLinklistType *linklist) +{ + unsigned int linklist_length = 0; + const DoubleLinklistType *tmp_node = linklist; + while (tmp_node->node_next != linklist) + { + tmp_node = tmp_node->node_next; + linklist_length ++; + } + + return linklist_length; +} \ No newline at end of file diff --git a/Ubiquitous/XiZi/kernel/thread/event.c b/Ubiquitous/XiZi/kernel/thread/event.c new file mode 100644 index 0000000..871486f --- /dev/null +++ b/Ubiquitous/XiZi/kernel/thread/event.c @@ -0,0 +1,302 @@ +/* +* Copyright (c) 2020 AIIT XUOS Lab +* XiUOS is licensed under Mulan PSL v2. +* You can use this software according to the terms and conditions of the Mulan PSL v2. +* You may obtain a copy of Mulan PSL v2 at: +* http://license.coscl.org.cn/MulanPSL2 +* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, +* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, +* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. +* See the Mulan PSL v2 for more details. +*/ + +/** +* @file: event.c +* @brief: event file +* @version: 1.0 +* @author: AIIT XUOS Lab +* @date: 2020/3/15 +* +*/ + +#include + +DECLARE_ID_MANAGER(k_event_id_manager, ID_NUM_MAX); +DoubleLinklistType k_event_list ={&k_event_list, &k_event_list}; + +static int32 _EventCreate(uint32 options) +{ + int32 id = 0; + x_base lock = 0; + struct Event *event = NONE; + + event = (struct Event *)x_malloc(sizeof(struct Event)); + if (event == NONE) + return -ENOMEMORY; + + memset(event, 0, sizeof(struct Event)); + lock = CriticalAreaLock(); + id = IdInsertObj(&k_event_id_manager, &event->id); + if (id < 0) { + CriticalAreaUnLock(lock); + x_free(event); + return -ENOMEMORY; + } + + event->options = options; + InitDoubleLinkList(&event->pend_list); + + DoubleLinkListInsertNodeAfter(&k_event_list, &event->link); + CriticalAreaUnLock(lock); + + return id; +} + +static void _EventDelete(struct Event *event) +{ + int resched = 0; + x_base lock = 0; + + NULL_PARAM_CHECK(event); + + if (!IsDoubleLinkListEmpty(&event->pend_list)) { + resched = 1; + LinklistResumeAll(&event->pend_list); + } + + lock = CriticalAreaLock(); + IdRemoveObj(&k_event_id_manager, event->id.id); + + DoubleLinkListRmNode(&event->link); + CriticalAreaUnLock(lock); + + x_free(event); + + if (resched) + DO_KTASK_ASSIGN; +} + +static int32 _EventTrigger(struct Event *event, uint32 events) +{ + x_bool resched; + x_ubase lock = 0; + x_base status = 0; + struct TaskDescriptor *task = NONE; + struct SysDoubleLinklistNode *n = NONE; + + NULL_PARAM_CHECK(event); + + if (events == 0) + return -ERROR; + + resched = RET_FALSE; + + lock = CriticalAreaLock(); + + event->events |= events; + + if (IsDoubleLinkListEmpty(&event->pend_list)) { + CriticalAreaUnLock(lock); + return EOK; + } + + n = event->pend_list.node_next; + while (n != &(event->pend_list)) { + task = SYS_DOUBLE_LINKLIST_ENTRY(n, struct TaskDescriptor, task_dync_sched_member.sched_link); + status = -ERROR; + if (task->event_mode & EVENT_AND) { + if ((task->event_id_trigger & (event->events & EVENT_EVENTS_MASK)) == task->event_id_trigger) + status = EOK; + } else if (task->event_mode & EVENT_OR) { + if (task->event_id_trigger & (event->events & EVENT_EVENTS_MASK)) { + task->event_id_trigger = task->event_id_trigger & (event->events & EVENT_EVENTS_MASK); + status = EOK; + } + } + + n = n->node_next; + + if (status == EOK) { + if (task->event_mode & EVENT_AUTOCLEAN) + event->events &= ~task->event_id_trigger; + + KTaskWakeup(task->id.id); + + resched = RET_TRUE; + } + } + + CriticalAreaUnLock(lock); + + if (resched == RET_TRUE) + DO_KTASK_ASSIGN; + + return EOK; +} + +static int32 _EventProcess(struct Event *event, uint32 events, uint32 options, int32 msec, uint32 *processed) +{ + + x_ubase lock = 0; + x_base status = 0; + int32 timeout = 0; + struct TaskDescriptor *task = NONE; + + KDEBUG_IN_KTASK_CONTEXT; + + NULL_PARAM_CHECK(event); + + if (events == 0) + return -ERROR; + + status = -ERROR; + task = GetKTaskDescriptor(); + task->exstatus = EOK; + + timeout = CalculteTickFromTimeMs(msec); + + lock = CriticalAreaLock(); + + if (options & EVENT_AND) { + if ((event->events & events) == events) + status = EOK; + } else if (options & EVENT_OR) { + if (event->events & events) + status = EOK; + } else { + CHECK(0); + } + + if (status == EOK) { + if (processed) + *processed = (event->events & events); + + if (options & EVENT_AUTOCLEAN) + event->events &= ~events; + } else if (timeout == 0) { + task->exstatus = -ETIMEOUT; + } else { + task->event_id_trigger = (events & EVENT_EVENTS_MASK); + task->event_mode = (options & EVENT_OPTIONS_MASK); + + LinklistSuspend(&(event->pend_list), task, event->options); + + if (timeout > 0) + KTaskSetDelay(task,timeout); + + CriticalAreaUnLock(lock); + + DO_KTASK_ASSIGN; + + if (task->exstatus != EOK) + return task->exstatus; + + lock = CriticalAreaLock(); + + if (processed) + *processed = task->event_id_trigger; + } + + CriticalAreaUnLock(lock); + + return task->exstatus; +} + +static EventDoneType done = { + .EventCreate = _EventCreate, + .EventDelete = _EventDelete, + .EventTrigger = _EventTrigger, + .EventProcess = _EventProcess, +}; + +static struct Event *FindEventById(int32 id) +{ + x_base lock = 0; + struct IdNode *idnode = NONE; + struct Event *event = NONE; + + if (id < 0) + return NONE; + lock = CriticalAreaLock(); + idnode = IdGetObj(&k_event_id_manager, id); + if (idnode == NONE) { + CriticalAreaUnLock(lock); + return NONE; + } + + event = CONTAINER_OF(idnode, struct Event, id); + CriticalAreaUnLock(lock); + + return event; +} + +/** + * This function will create a event. + * + * @param options the trigger way of event. + * + * @return id + */ +int32 KEventCreate(uint32 options) +{ + KDEBUG_NOT_IN_INTERRUPT; + + return done.EventCreate(options); +} + +/** + * This function will delete a event. + * + * @param id the id number of event. + * + * @return + */ +void KEventDelete(int32 id) +{ + KDEBUG_NOT_IN_INTERRUPT; + + struct Event *event = FindEventById(id); + + if (event == NONE) + return; + + done.EventDelete(event); +} +/** + * This function will trigger the event + * + * @param id the id number of event + * @param events trigger way & events flag + * + * @return EOK on success. + */ +int32 KEventTrigger(int32 id, uint32 events) +{ + KDEBUG_NOT_IN_INTERRUPT; + + struct Event *event = FindEventById(id); + + if (event == NONE) + return -ERROR; + + return done.EventTrigger(event, events); +} +/** + * This function will get the event and process this event + * + * @param id the id number of event + * @param events events flag + * @param options trigger way + * @param msec timeout + * @processed event processed flag + * + * @return EOK on success. + */ +int32 KEventProcess(int32 id, uint32 events, uint32 options, int32 msec, uint32 *processed) +{ + KDEBUG_NOT_IN_INTERRUPT; + + struct Event *event = FindEventById(id); + + return done.EventProcess(event, events, options, msec, processed); +} diff --git a/Ubiquitous/XiZi/kernel/thread/hook.c b/Ubiquitous/XiZi/kernel/thread/hook.c new file mode 100644 index 0000000..7bb0d41 --- /dev/null +++ b/Ubiquitous/XiZi/kernel/thread/hook.c @@ -0,0 +1,216 @@ +/* +* Copyright (c) 2020 AIIT XUOS Lab +* XiUOS is licensed under Mulan PSL v2. +* You can use this software according to the terms and conditions of the Mulan PSL v2. +* You may obtain a copy of Mulan PSL v2 at: +* http://license.coscl.org.cn/MulanPSL2 +* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, +* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, +* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. +* See the Mulan PSL v2 for more details. +*/ + +/** +* @file: hook.c +* @brief: the general interface functions of hook +* @version: 1.0 +* @author: AIIT XUOS Lab +* @date: 2020/3/20 +* +*/ + +#include +#include + +struct KernelHook hook; + +/** + * a hook function, it will run when switch task + * + * @param from task descriptor + * @param to task descriptor + */ +void AssignHook(KTaskDescriptorType from, KTaskDescriptorType to) +{ + SYS_KDEBUG_LOG(KDBG_HOOK, + ("HOOK: Function[%s], from task: %s, to task:%s\n",__func__,from->task_base_info.name,to->task_base_info.name)); + /* add your code */ +} + +/** + * + * This hook function will be run after task inited . + * + * @param task task descripter + * + * @note no blocked or suspend function. + */ +void TaskCreatehook(KTaskDescriptorType task) +{ + SYS_KDEBUG_LOG(KDBG_HOOK, + ("HOOK: Function[%s], Create task: %s\n",__func__,task->task_base_info.name)); + /* add your code */ +} + +/** + * + * This hook function will be run after task suspended . + * + * @param task descripter + * + * @note no blocked or suspend function. + */ +void TaskSuspendhook(KTaskDescriptorType task) +{ + SYS_KDEBUG_LOG(KDBG_HOOK, + ("HOOK: Function[%s], Suspend task: %s\n",__func__,task->task_base_info.name)); + /* add your code */ +} + +/** + * + * This hook function will be run after task resumed . + * + * @param task descripter + * + * @note no blocked or suspend function. + */ +void TaskResumehook(KTaskDescriptorType task) +{ + SYS_KDEBUG_LOG(KDBG_HOOK, + ("HOOK: Function[%s], Resume task: %s\n",__func__,task->task_base_info.name)); + /* add your code */ +} + +/** + * a MallocHook function. The MallocHook function will be run before a memory block is allocated from buddy-memory. + * + * @param ptr alloc mem point + * @param size alloc mem size + */ +void MemMallochook(void *ptr, x_size_t size) +{ + SYS_KDEBUG_LOG(KDBG_HOOK, + ("HOOK: Function[%s], Malloc memory: ptr:%p, size: %d\n",__func__,ptr,size)); + /* add your code */ +} + +/** + * a FreeHook function. The FreeHook function will be run after a memory block is freed to buddy-memory. + * + * @param ptr free mem point + */ +void MemFreehook(void *ptr) +{ + SYS_KDEBUG_LOG(KDBG_HOOK, + ("HOOK: Function[%s], Free memory: ptr:%p\n",__func__,ptr)); + /* add your code */ +} +#ifdef KERNEL_MEMBLOCK +/** + * a allocation hook function before a gatherblock allocation. + * + * @param gm the alloc hook function + * @param date_ptr mem point + */ +void GmAllocHook(struct MemGather *gm, void *date_ptr) +{ + /* add your code */ + return; +} + +/** + * a free hook function after a gatherblock release. + * + * @param gm the free hook function + * @param date_ptr mem point + */ +void GmFreeHook(struct MemGather *gm, void *date_ptr) +{ + /* add your code */ + return; +} +#endif +/** + * this hook function will run when the system interrupt + * + * @note no blocked or suspend. + */ +void IsrEnterHook(void) +{ + SYS_KDEBUG_LOG(KDBG_HOOK, + ("HOOK: Function[%s], Enter Isr\n",__func__)); + /* add your code */ +} + +/** + * this hook function will run when the system leave interrupt + * + * @note no blocked or suspend. + */ +void IsrLeaveHook(void) +{ + SYS_KDEBUG_LOG(KDBG_HOOK, + ("HOOK: Function[%s], Leave Isr\n",__func__)); + /* add your code */ +} + +void TimerEnterHook(struct Timer *timer) +{ + SYS_KDEBUG_LOG(KDBG_HOOK, + ("HOOK: Function[%s], Timer Enter\n",__func__)); + /* add your code */ +} + +void TimerExitHook(struct Timer *timer) +{ + SYS_KDEBUG_LOG(KDBG_HOOK, + ("HOOK: Function[%s], Timer Exit\n",__func__)); + /* add your code */ +} + +void IdleTaskHook(void) +{ + SYS_KDEBUG_LOG(KDBG_HOOK, + ("HOOK: Function[%s], Idle0 \n",__func__)); + /* add your code */ +} + + + +void testhook(const char *str) +{ + SYS_KDEBUG_LOG(KDBG_HOOK, + ("HOOK: Function[%s],Test: %s\n",__func__,str)); + /* add your code */ + return; +} + + +int hook_init(void) +{ + REGISTER_HOOK(hook.assign.hook_Assign,AssignHook); + + REGISTER_HOOK(hook.task.hook_TaskCreate,TaskCreatehook); + REGISTER_HOOK(hook.task.hook_TaskSuspend,TaskSuspendhook); + REGISTER_HOOK(hook.task.hook_TaskResume,TaskResumehook); + + REGISTER_HOOK(hook.mem.hook_Malloc,MemMallochook); + REGISTER_HOOK(hook.mem.hook_Free,MemFreehook); + +#ifdef KERNEL_MEMBLOCK + REGISTER_HOOK(hook.mem.hook_GmAlloc,GmAllocHook); + REGISTER_HOOK(hook.mem.hook_GmFree,GmFreeHook); +#endif + + REGISTER_HOOK(hook.timer.hook_TimerEnter,TimerEnterHook); + REGISTER_HOOK(hook.timer.hook_TimerExit,TimerExitHook); + + REGISTER_HOOK(hook.idle.hook_Idle,IdleTaskHook); + //REGISTER_HOOK(hook.idle[1].hook_Idle,IdleTask1Hook); + + REGISTER_HOOK(hook.isr.hook_IsrEnter,IsrEnterHook); + REGISTER_HOOK(hook.isr.hook_IsrLeave,IsrLeaveHook); + REGISTER_HOOK(hook.test.hook_test,testhook); + return EOK; +} \ No newline at end of file diff --git a/Ubiquitous/XiZi/kernel/thread/id.c b/Ubiquitous/XiZi/kernel/thread/id.c new file mode 100644 index 0000000..1ad7dd5 --- /dev/null +++ b/Ubiquitous/XiZi/kernel/thread/id.c @@ -0,0 +1,142 @@ +/* + * Copyright (c) 2020 AIIT XUOS Lab + * XiUOS is licensed under Mulan PSL v2. + * You can use this software according to the terms and conditions of the Mulan PSL v2. + * You may obtain a copy of Mulan PSL v2 at: + * http://license.coscl.org.cn/MulanPSL2 + * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, + * EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, + * MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. + * See the Mulan PSL v2 for more details. + */ + +/** +* @file: id.c +* @brief: the management with id for all kernel object +* @version: 1.0 +* @author: AIIT XUOS Lab +* @date: 2020/4/15 +* +*/ + +#include + +static int AllocId(struct IdManager *manager) +{ + int index = 0; + int end = 0; + int id = 0; + uint8 entry = 0; + + NULL_PARAM_CHECK(manager); + + end = (manager->id_max + 7) / 8; + + for (index = 0; index < end; index++) + if (manager->id_map[index] != 0xff) + break; + if (index == end) + return -1; + + id = index * 8; + entry = manager->id_map[index]; + while (entry & 0x1) { + id++; + entry >>= 1; + } + if (id >= manager->id_max) + return -1; + + manager->id_map[index] |= (0x1 << (id % 8)); + + return id; +} + +static void FreeId(struct IdManager *manager, uint16 id) +{ + NULL_PARAM_CHECK(manager); + + manager->id_map[id / 8] &= ~(0x1 << (id % 8)); +} + +static void InsertObj(struct IdManager *manager, struct IdNode *idnode) +{ + NULL_PARAM_CHECK(manager); + NULL_PARAM_CHECK(idnode); + + DoubleLinklistType *head = &manager->htable[idnode->id % manager->hoffset]; + + if (head->node_prev == NONE) + InitDoubleLinkList(head); + + DoubleLinkListInsertNodeAfter(head, &idnode->link); +} + +static struct IdNode *GetObj(struct IdManager *manager, uint16 id) +{ + NULL_PARAM_CHECK(manager); + + DoubleLinklistType *head = &manager->htable[id % manager->hoffset]; + DoubleLinklistType *node = NONE; + struct IdNode *idnode = NONE; + + if (head->node_prev == NONE) { + InitDoubleLinkList(head); + return NONE; + } + + DOUBLE_LINKLIST_FOR_EACH(node, head) { + idnode =CONTAINER_OF(node, struct IdNode, link); + if (idnode->id == id) + break; + idnode = NONE; + } + + return idnode; +} + +static struct IdNode *RemoveObj(struct IdManager *manager, struct IdNode *idnode) +{ + NULL_PARAM_CHECK(manager); + NULL_PARAM_CHECK(idnode); + + DoubleLinkListRmNode(&idnode->link); +} + +int IdInsertObj(struct IdManager *manager, struct IdNode *idnode) +{ + int id = 0; + + NULL_PARAM_CHECK(manager); + NULL_PARAM_CHECK(idnode); + + if ((id = AllocId(manager)) < 0) + return -1; + + idnode->id = id; + InsertObj(manager, idnode); + + return id; +} + +struct IdNode *IdGetObj(struct IdManager *manager, uint16 id) +{ + if (manager == NONE || id >= manager->id_max) + return NONE; + + return GetObj(manager, id); +} + +void IdRemoveObj(struct IdManager *manager, uint16 id) +{ + NULL_PARAM_CHECK(manager); + + struct IdNode *idnode = IdGetObj(manager, id); + + if (idnode == NONE) + return; + + FreeId(manager, idnode->id); + RemoveObj(manager, idnode); + idnode->id = -1; +} diff --git a/Ubiquitous/XiZi/kernel/thread/idle.c b/Ubiquitous/XiZi/kernel/thread/idle.c new file mode 100644 index 0000000..932ce41 --- /dev/null +++ b/Ubiquitous/XiZi/kernel/thread/idle.c @@ -0,0 +1,105 @@ +/* +* Copyright (c) 2020 AIIT XUOS Lab +* XiUOS is licensed under Mulan PSL v2. +* You can use this software according to the terms and conditions of the Mulan PSL v2. +* You may obtain a copy of Mulan PSL v2 at: +* http://license.coscl.org.cn/MulanPSL2 +* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, +* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, +* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. +* See the Mulan PSL v2 for more details. +*/ + +/** +* @file: idle.c +* @brief: idle file +* @version: 1.0 +* @author: AIIT XUOS Lab +* @date: 2020/3/15 +* +*/ + +#include +#include +#include + +#if defined (KERNEL_HOOK) +#ifndef KERNEL_IDLE_HOOK +#define KERNEL_IDLE_HOOK +#endif +#endif + +#ifndef IDLE_KTASK_STACKSIZE +#define IDLE_KTASK_STACKSIZE 256 +#endif + +#ifdef ARCH_SMP +#define CORE_NUM CPU_NUMBERS +#else +#define CORE_NUM 1 +#endif + + +static int32 idle[CORE_NUM]; +__attribute__((aligned(MEM_ALIGN_SIZE))) + +void RunningIntoLowPowerMode() +{ +#ifdef ARCH_ARM + // __asm volatile("WFI"); +#endif + +#ifdef ARCH_RISCV + asm volatile ("wfi"); +#endif +} + +static void IdleKTaskEntry(void *arg) +{ + while (1) { +#ifdef KERNEL_IDLE_HOOK + HOOK(hook.idle.hook_Idle,()); +#endif + RunningIntoLowPowerMode(); + } +} +/** + * + * init system idle task,then startup the idle task + * + */ +void InitIdleKTask(void) +{ + uint8 coreid = 0; + char ktaskidle[NAME_NUM_MAX] = {0}; + + for (coreid = 0; coreid < CORE_NUM; coreid++) { + sprintf(ktaskidle, "ktaskidle%d", coreid); + + idle[coreid] = KTaskCreate(ktaskidle,IdleKTaskEntry,NONE,IDLE_KTASK_STACKSIZE,KTASK_LOWEST_PRIORITY); + +#ifdef ARCH_SMP + KTaskCoreCombine(idle[coreid], coreid); +#endif + StartupKTask(idle[coreid]); + } +} + +/** + * + * This function will return the idle task descriptor + * + */ +KTaskDescriptorType GetIdleKTaskDescripter(void) +{ + KTaskDescriptorType idle_p = NONE; + +#ifdef ARCH_SMP + register int id = GetCpuId(); +#else + register int id = 0; +#endif + + idle_p = CONTAINER_OF(&idle[id], struct TaskDescriptor, id); + return idle_p; +} diff --git a/Ubiquitous/XiZi/kernel/thread/init.c b/Ubiquitous/XiZi/kernel/thread/init.c new file mode 100644 index 0000000..00e255d --- /dev/null +++ b/Ubiquitous/XiZi/kernel/thread/init.c @@ -0,0 +1,262 @@ +/* +* Copyright (c) 2020 AIIT XUOS Lab +* XiUOS is licensed under Mulan PSL v2. +* You can use this software according to the terms and conditions of the Mulan PSL v2. +* You may obtain a copy of Mulan PSL v2 at: +* http://license.coscl.org.cn/MulanPSL2 +* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, +* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, +* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. +* See the Mulan PSL v2 for more details. +*/ + +/** +* @file: init.c +* @brief: init file +* @version: 1.0 +* @author: AIIT XUOS Lab +* @date: 2020/3/15 +* +*/ + +#include +#include +#include +#include +#include +#include +#include + +#ifdef BSP_USING_USB +#include "connect_usb.h" +#endif + +#ifdef KERNEL_USER_MAIN +#ifndef MAIN_KTASK_STACK_SIZE +#define MAIN_KTASK_STACK_SIZE 2048 +#endif +#ifndef MAIN_KTASK_PRIORITY +#define MAIN_KTASK_PRIORITY (KTASK_PRIORITY_MAX / 3) +#endif +#endif + +extern void CreateKServiceKTask(void); +extern int main(void); +void InitBoardHardware(void); +extern int hook_init(void); +int CplusplusSystemInit(void); + +#ifdef KERNEL_COMPONENTS_INIT +#ifdef USER_APPLICATION +extern void CreateMainTask(void); +#ifdef SEPARATE_COMPILE +int InitUserspace(void); +#endif +#endif + +#ifndef ENV_INIT_KTASK_STACK_SIZE +#define ENV_INIT_KTASK_STACK_SIZE 8192 +#endif + +struct InitSequenceDesc prev_cmpts_init[] = +{ +#ifdef FS_VFS + { "vfs", VfsInit }, +#endif +#ifdef LIB_CPLUSPLUS + { "cplusplus_system", CplusplusSystemInit }, +#endif +#ifdef KERNEL_HOOK + { "hook", hook_init }, +#endif + { " NONE ", NONE }, +}; +struct InitSequenceDesc device_init[] = +{ +#ifdef KERNEL_WORKQUEUE + { "work sys workqueue", WorkSysWorkQueueInit }, +#endif + +#ifdef ARCH_ARM +#ifdef RESOURCES_SPI_SFUD + { "W25Qxx_spi", FlashW25qxxSpiDeviceInit}, +#endif +#endif + +#ifdef RESOURCES_SPI_LORA + {"LORA_spi", LoraSx12xxSpiDeviceInit}, +#endif + { " NONE ", NONE }, +}; +struct InitSequenceDesc components_init[] = +{ +#ifdef FS_VFS_FATFS + { "fatfs", FatfsInit }, +#endif +#ifdef FS_CH376 + { "ch376", Ch376fsInit }, +#endif +#ifdef FS_LWEXT4 + { "lwext4", Lwext4Init }, +#endif + { "libc_system", LibcSystemInit }, +#ifdef RTC_SYNC_USING_NTP + { "rtc_ntp_sync",RtcNtpSyncInit}, +#endif + { " NONE ", NONE }, +}; +struct InitSequenceDesc env_init[] = +{ +#ifdef BSP_USING_STM32_USBH + { "STM32USBHostRegister", STM32USBHostRegister }, + { "hw usb", Stm32HwUsbInit }, +#endif +#ifdef BSP_USING_NXP_USBH + { "nxp hw usb", Imxrt1052HwUsbHostInit }, +#endif +#ifdef MOUNT_SDCARD + { "MountSDCard", MountSDCard }, +#endif +#ifdef MOUNT_USB + { "MountUSB", MountUSB }, +#endif +#ifdef FS_VFS_MNTTABLE + { "DfsMountTable", DfsMountTable }, +#endif +#ifdef TOOL_SHELL + { "letter-shell system", userShellInit }, +#endif + { " NONE ", NONE }, +}; +struct InitSequenceDesc communication_init[] = +{ + { " NONE ", NONE }, +}; + +/** + * This function will init sub components + * @parm sub_components components type + * + */ +void _InitSubCmpts(struct InitSequenceDesc sub_cmpts[]) +{ + int i = 0; + int ret = 0; + for( i = 0; sub_cmpts[i].fn != NONE; i++ ) { + ret = sub_cmpts[i].fn(); + KPrintf("initialize %s %s\n",sub_cmpts[i].fn_name, ret == 0 ? "success" : "failed"); + } +} + +#ifdef KERNEL_COMPONENTS_INIT +void EnvInitKTask(void *parameter) +{ + x_base lock = 0; + lock = DISABLE_INTERRUPT(); + _InitSubCmpts(prev_cmpts_init); + _InitSubCmpts(device_init); + _InitSubCmpts(components_init); + _InitSubCmpts(env_init); + ENABLE_INTERRUPT(lock); + + _InitSubCmpts(communication_init); + +#ifdef ARCH_SMP + StartupSecondaryCpu(); +#endif + +#ifdef USER_APPLICATION +#ifdef SEPARATE_COMPILE + if(InitUserspace() == EOK) { + CreateMainTask(); + } +#else + CreateMainTask(); +#endif +#endif +} +#endif + +void CreateEnvInitTask(void) +{ + int32 env_init = 0; + + env_init = KTaskCreate("env_init", EnvInitKTask, NONE, + ENV_INIT_KTASK_STACK_SIZE, KTASK_PRIORITY_MAX - 1); + if(env_init < 0) { + KPrintf("env_init create failed ...%s %d.\n",__FUNCTION__,__LINE__); + return; + } + + StartupKTask(env_init); +} +#endif /* KERNEL_COMPONENTS_INIT */ + + +/** + * kernel startup function + * + * + */ +int XiUOSStartup(void) +{ + DISABLE_INTERRUPT(); + +#ifdef KERNEL_QUEUEMANAGE + QueuemanagerDoneRegister(); +#endif + +#ifdef KERNEL_BANNER + ShowBanner(); +#endif + + SysInitOsAssign(); + + CreateKServiceKTask(); + +#ifdef KERNEL_COMPONENTS_INIT + CreateEnvInitTask(); +#else + +#ifdef TOOL_SHELL + extern int userShellInit(void); + userShellInit(); +#endif + +#ifdef USER_APPLICATION +extern void CreateMainTask(void); +#ifdef SEPARATE_COMPILE +extern int InitUserspace(void); + + if(InitUserspace() == EOK) { + CreateMainTask(); + } +#else + CreateMainTask(); +#endif +#endif + +#endif + +#ifdef ARCH_SMP + HwLockSpinlock(&AssignSpinLock); +#endif + + StartupOsAssign(); + + return 0; +} + + +/* system entry */ +int entry(void) +{ + DISABLE_INTERRUPT(); + + /* system irq table must be inited before initialization of Hardware irq */ + SysInitIsrManager(); + + InitBoardHardware(); + XiUOSStartup(); + return 0; +} diff --git a/Ubiquitous/XiZi/kernel/thread/isr.c b/Ubiquitous/XiZi/kernel/thread/isr.c new file mode 100644 index 0000000..0317c56 --- /dev/null +++ b/Ubiquitous/XiZi/kernel/thread/isr.c @@ -0,0 +1,218 @@ +/* +* Copyright (c) 2020 AIIT XUOS Lab +* XiUOS is licensed under Mulan PSL v2. +* You can use this software according to the terms and conditions of the Mulan PSL v2. +* You may obtain a copy of Mulan PSL v2 at: +* http://license.coscl.org.cn/MulanPSL2 +* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, +* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, +* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. +* See the Mulan PSL v2 for more details. +*/ + +/** +* @file: isr.c +* @brief: the general management of system isr +* @version: 1.0 +* @author: AIIT XUOS Lab +* @date: 2020/3/15 +* +*/ + +#include +#include + +struct InterruptServiceRoutines isrManager = { 0} ; + +#ifdef ARCH_SMP +extern int GetCpuId(void); +#endif +/** + * This functionwill get the isr nest level. + * + * @return isr nest level + */ + uint16 GetIsrCounter() +{ + uint16 ret = 0; + +#ifdef ARCH_SMP + ret = isrManager.isr_count[GetCpuId()]; +#else + ret = isrManager.isr_count; +#endif + return ret; +} + + void IncIsrCounter() +{ +#ifdef ARCH_SMP + isrManager.isr_count[GetCpuId()] ++ ; +#else + isrManager.isr_count ++; +#endif + return ; +} + + void DecIsrCounter() +{ + +#ifdef ARCH_SMP + isrManager.isr_count[GetCpuId()] -- ; +#else + isrManager.isr_count --; +#endif + return ; +} + + x_bool IsInIsr() +{ +#ifdef ARCH_SMP + return ( isrManager.isr_count[GetCpuId()] != 0 ? RET_TRUE : RET_FALSE ) ; +#else + return ( isrManager.isr_count != 0 ? RET_TRUE : RET_FALSE ) ; +#endif + +} +/** + * This function will register a new irq. + * + * @param irq_num the number of the irq + * @param handler the callback of the interrupt + * @param arg param of thge callback + * + * @return EOK on success; ERROR on failure + */ +int32 RegisterHwIrq(uint32 irq_num, IsrHandlerType handler, void *arg) +{ + if (irq_num >= ARCH_MAX_IRQ_NUM ) + return -ERROR; + + struct IrqDesc *desc = &isrManager.irq_table[irq_num]; + + desc->handler = handler; + desc->param = arg; + + return EOK; +} +/** + * This function will free a irq. + * + * @param irq_num the number of the irq + * + * @return EOK on success; ERROR on failure + */ +int32 FreeHwIrq(uint32 irq_num) +{ + if (irq_num >= ARCH_MAX_IRQ_NUM ) + return -ERROR; + + memset(&isrManager.irq_table[irq_num], 0, sizeof(struct IrqDesc)); + + return EOK; +} + +/** + * This function will enable a irq. + * + * @param irq_num the number of the irq + * + * @return EOK on success; ERROR on failure + */ +int32 EnableHwIrq(uint32 irq_num) +{ + if (irq_num >= ARCH_MAX_IRQ_NUM ) + return -ERROR; + + return ArchEnableHwIrq(irq_num); +} +/** + * This function will disable a irq. + * + * @param irq_num the number of the irq + * + * @return EOK on success; ERROR on failure + */ + +int32 DisableHwIrq(uint32 irq_num) +{ + if (irq_num >= ARCH_MAX_IRQ_NUM ) + return -ERROR; + + return ArchDisableHwIrq(irq_num); +} + +/* called from arch-specific ISR wrapper */ +void IsrCommon(uint32 irq_num) +{ + struct IrqDesc *desc = &isrManager.irq_table[irq_num]; + + if (desc->handler == NONE) { + SYS_KDEBUG_LOG(KDBG_IRQ, ("Spurious interrupt: IRQ No. %d\n", irq_num)); + while (1) {} + } + desc->handler(irq_num, desc->param); + +} + + void SetIsrSwitchTrigerFlag() + { + +#ifdef ARCH_SMP + isrManager.isr_switch_trigger_flag[GetCpuId()] = 1; +#else + isrManager.isr_switch_trigger_flag = 1; +#endif + +} + + void ClearIsrSwitchTrigerFlag() + { + +#ifdef ARCH_SMP + isrManager.isr_switch_trigger_flag[GetCpuId()] = 0; +#else + isrManager.isr_switch_trigger_flag = 0; +#endif +} + + uint8 GetIsrSwitchTrigerFlag() + { + +#ifdef ARCH_SMP + return isrManager.isr_switch_trigger_flag[GetCpuId()]; +#else + return isrManager.isr_switch_trigger_flag ; +#endif + +} + +struct IsrDone isrDone = { + IsInIsr, + RegisterHwIrq , + FreeHwIrq, + EnableHwIrq, + DisableHwIrq, + IsrCommon, + GetIsrCounter, + IncIsrCounter, + DecIsrCounter, + GetIsrSwitchTrigerFlag, + SetIsrSwitchTrigerFlag, + ClearIsrSwitchTrigerFlag +} ; + +void SysInitIsrManager() +{ + extern int __isrtbl_idx_start; + extern int __isrtbl_start; + extern int __isrtbl_end; + memset(&isrManager,0,sizeof(struct InterruptServiceRoutines)); + isrManager.done = &isrDone; + + uint32 *index = (uint32 *)&__isrtbl_idx_start; + struct IrqDesc *desc = (struct IrqDesc *)&__isrtbl_start; + + while (desc != (struct IrqDesc *)&__isrtbl_end) + isrManager.irq_table[*index++] = *desc++; +} diff --git a/Ubiquitous/XiZi/kernel/thread/kservicetask.c b/Ubiquitous/XiZi/kernel/thread/kservicetask.c new file mode 100644 index 0000000..db218c3 --- /dev/null +++ b/Ubiquitous/XiZi/kernel/thread/kservicetask.c @@ -0,0 +1,46 @@ + +/* +* Copyright (c) 2020 AIIT XUOS Lab +* XiUOS is licensed under Mulan PSL v2. +* You can use this software according to the terms and conditions of the Mulan PSL v2. +* You may obtain a copy of Mulan PSL v2 at: +* http://license.coscl.org.cn/MulanPSL2 +* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, +* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, +* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. +* See the Mulan PSL v2 for more details. +*/ + +/** +* @file: kservicetask.c +* @brief: create service task for system +* @version: 1.0 +* @author: AIIT XUOS Lab +* @date: 2020/3/15 +* +*/ + +#include + +extern void ZombieTaskRecycleInit(void); +extern void InitIdleKTask(void); +void KSerciveKTaskIdle(void) +{ + InitIdleKTask(); +} + +void KServiceKTaskRecycle() +{ + ZombieTaskRecycleInit(); +} + +void CreateKServiceKTask(void) +{ + /* create zombie recycle task */ + KServiceKTaskRecycle(); + + /* create idle task */ + KSerciveKTaskIdle(); + +} + diff --git a/Ubiquitous/XiZi/kernel/thread/ktask.c b/Ubiquitous/XiZi/kernel/thread/ktask.c new file mode 100644 index 0000000..a06236b --- /dev/null +++ b/Ubiquitous/XiZi/kernel/thread/ktask.c @@ -0,0 +1,1156 @@ +/* +* Copyright (c) 2020 AIIT XUOS Lab +* XiUOS is licensed under Mulan PSL v2. +* You can use this software according to the terms and conditions of the Mulan PSL v2. +* You may obtain a copy of Mulan PSL v2 at: +* http://license.coscl.org.cn/MulanPSL2 +* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, +* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, +* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. +* See the Mulan PSL v2 for more details. +*/ + +/** +* @file: ktask.c +* @brief: ktask file +* @version: 1.0 +* @author: AIIT XUOS Lab +* @date: 2020/3/15 +* +*/ + +#include +#include +#include +#include +#include +#include +#ifdef TASK_ISOLATION +#include +#endif + +static volatile int __exstatus; + +extern DoubleLinklistType KTaskZombie; +extern int32 zombie_recycle; +extern uint8 KTaskStackSetup(struct TaskDescriptor *task); +extern int JudgeZombieKTaskIsNotEmpty(void); + +DoubleLinklistType xiaoshan_task_head ={&xiaoshan_task_head, &xiaoshan_task_head}; ///< global task manage list + +#if KTASK_PRIORITY_MAX > 32 +#define BITMAP_CACULATE_COLUMN_OFFSET(offset,n) (offset = n / 8) +#endif + +#define BITMAP_SETCOLUMN(column,offset) (column = (1 << offset)) +#define BITMAP_SETROW(row,offset) (row = (1 << offset)) +#define BITLOWMASK_3BIT (0x7) + + +DECLARE_ID_MANAGER(k_task_id_manager, ID_NUM_MAX); + +void KTaskIdDelete(int32 id) +{ + IdRemoveObj(&k_task_id_manager, id); +} + +inline struct TaskDescriptor *GetTaskWithIdnodeInfo(int32 id) +{ + struct TaskDescriptor *task = NONE; + struct IdNode *idnode = NONE; + x_base lock = 0; + + if (id < 0) + return NONE; + + lock = CriticalAreaLock(); + idnode = IdGetObj(&k_task_id_manager, id); + if (idnode == NONE){ + CriticalAreaUnLock(lock); + return NONE; + } + task =CONTAINER_OF(idnode, struct TaskDescriptor, id); + CriticalAreaUnLock(lock); + return task; +} + +static inline void __BitmapSiteMask(struct TaskDescriptor *task) +{ + NULL_PARAM_CHECK(task); + +#if KTASK_PRIORITY_MAX > 32 + BITMAP_CACULATE_COLUMN_OFFSET(task->task_dync_sched_member.bitmap_offset,task->task_dync_sched_member.cur_prio); + BITMAP_SETCOLUMN(task->task_dync_sched_member.bitmap_column,task->task_dync_sched_member.bitmap_offset); + BITMAP_SETROW(task->task_dync_sched_member.bitmap_row,(task->task_dync_sched_member.cur_prio & BITLOWMASK_3BIT)); +#else + BITMAP_SETCOLUMN(task->task_dync_sched_member.bitmap_column,task->task_dync_sched_member.cur_prio); +#endif + +} + +static inline void _KTaskResourceDelete(struct TaskDescriptor *task) +{ + NULL_PARAM_CHECK(task); + +#ifdef ARCH_SMP + HwLockSpinlock(&AssignSpinLock); +#endif + Assign.ready_vector_done->remove(task); +#ifdef ARCH_SMP + HwUnlockSpinlock(&AssignSpinLock); +#endif + KTaskStatSetAsClose(task); + + return; +} + +static inline x_err_t __JudgeKTaskIsIdleOrZombierecycle(KTaskDescriptorType task) +{ + NULL_PARAM_CHECK(task); + if(0 == strncmp(task->task_base_info.name,"ktaskidle0",strlen("ktaskidle0")) || + 0 == strncmp(task->task_base_info.name,"ktaskidle1",strlen("ktaskidle1")) || + 0 == strncmp(task->task_base_info.name,"ZombieRecycleKTask",strlen("ZombieRecycleKTask")) ) + { + return RET_TRUE; + } + + return EOK; +} + +/** + * find a task in manage list. + * + * @param name task name + * + * @note in interrupt status,this function is not permitted to call. + */ +KTaskDescriptorType KTaskSearch(char *name) +{ + x_base lock = 0; + KTaskDescriptorType temp_task = NONE; + struct SysDoubleLinklistNode *node = NONE; + + lock = CriticalAreaLock(); + + DOUBLE_LINKLIST_FOR_EACH(node,&xiaoshan_task_head) + { + temp_task = SYS_DOUBLE_LINKLIST_ENTRY(node, struct TaskDescriptor, link); + if (0 == strncmp(temp_task->task_base_info.name, name, NAME_NUM_MAX)) + { + CriticalAreaUnLock(lock); + return temp_task; + } + } + + CriticalAreaUnLock(lock); + + return NONE; +} + +/** + * This function will get a task descriptor + * + */ +KTaskDescriptorType GetKTaskDescriptor(void) +{ + x_base lock = 0; + KTaskDescriptorType task = NONE; + + lock = CriticalAreaLock(); +#ifdef ARCH_SMP + HwLockSpinlock(&AssignSpinLock); + if(Assign.smp_os_running_task[GetCpuId()] != NONE){ + task = Assign.smp_os_running_task[GetCpuId()]; + } + HwUnlockSpinlock(&AssignSpinLock); +#else + if(Assign.os_running_task != NONE){ + task = Assign.os_running_task; + } +#endif + + CriticalAreaUnLock(lock); + return task; +} + + +/** + * This function will delay current task running with some ticks. + * + * @param tick delay ticks + * + */ +x_err_t _DelayKTask(KTaskDescriptorType task, x_ticks_t ticks) +{ + x_base lock = 0; + + NULL_PARAM_CHECK(task); + + if (ticks == 0) { + KPrintf("Timeout ticks must be setted more than 0.\n"); + return -EINVALED; + } + + lock = CriticalAreaLock(); + SuspendKTask(task->id.id); + KTaskSetDelay(task,ticks); + CriticalAreaUnLock(lock); + + DO_KTASK_ASSIGN; + + if (task->exstatus == -ETIMEOUT) + task->exstatus = EOK; + + return EOK; +} + +/** + * This function will delay current task wite milliseconds. + * + * @param ms milliseconds of delay time + * + */ +x_err_t _MdelayKTask(KTaskDescriptorType task, uint32 ms) +{ + x_ticks_t ticks = 0; + + NULL_PARAM_CHECK(task); + + if (0 == ms) { + return -EINVALED; + } + + ticks = CalculteTickFromTimeMs(ms); + + return _DelayKTask(task, ticks); +} + + +/** + * This function sets the task's priority. + * + * @param id task id + * @param prio priority value + * + * @return EOK + */ +x_err_t _KTaskPrioSet(KTaskDescriptorType task, uint8 prio) +{ + extern long ShowTask(void); + x_base lock = 0; + int ret = EOK; + uint8 task_stat = 0; + + NULL_PARAM_CHECK(task); + lock = CriticalAreaLock(); + + if (0 == strncmp("ktaskidle",task->task_base_info.name, strlen("ktaskidle"))) + { + KPrintf("IDLE task [%s] is forbidden to change priority.\n",task->task_base_info.name); + CriticalAreaUnLock(lock); + return -ERROR; + } + task_stat = KTaskStatGet(task); + + switch(task_stat) + { + case KTASK_READY: +#ifdef ARCH_SMP + HwLockSpinlock(&AssignSpinLock); +#endif + task->task_dync_sched_member.cur_prio = prio; + Assign.ready_vector_done->remove(task); + __BitmapSiteMask(task); + Assign.ready_vector_done->insert(task); +#ifdef ARCH_SMP + HwUnlockSpinlock(&AssignSpinLock); +#endif + break; + case KTASK_INIT: + case KTASK_SUSPEND: + case KTASK_RUNNING: + task->task_dync_sched_member.cur_prio = prio; + __BitmapSiteMask(task); + break; + case KTASK_CLOSE: + KPrintf("the close stat task is forbidden to change priority.\n"); + + ret = EOK; + break; + default: + KPrintf("invalid stat task is forbidden to change priority.\n"); + ret = -EINVALED; + break; + } + CriticalAreaUnLock(lock); + + return ret; +} + +#ifdef ARCH_SMP +/** + * This function binds a task to cpu core. + * + * @param id task id + * @param coreid cpu core id + * + * @return EOK + */ +x_err_t _KTaskCoreCombine(KTaskDescriptorType task, uint8 coreid) +{ + x_base lock = 0; + int ret = EOK; + uint8 task_stat = 0; + + NULL_PARAM_CHECK(task); + + lock = CriticalAreaLock(); + task_stat = KTaskStatGet(task); + switch(task_stat) + { + case KTASK_READY: + HwLockSpinlock(&AssignSpinLock); + Assign.ready_vector_done->remove(task); + task->task_smp_info.combined_coreid = coreid > CPU_NUMBERS ? UNCOMBINE_CPU_CORE : coreid; + Assign.ready_vector_done->insert(task); + HwUnlockSpinlock(&AssignSpinLock); + break; + case KTASK_INIT: + case KTASK_SUSPEND: + task->task_smp_info.combined_coreid = coreid > CPU_NUMBERS ? UNCOMBINE_CPU_CORE : coreid; + break; + case KTASK_CLOSE: + case KTASK_RUNNING: + KPrintf("the CLOSE and RUNNING stat of task is forbidden to change cpu core.\n"); + ret = -ERROR; + break; + default: + KPrintf("%s invalid task stat.\n",__func__); + ret = -EINVALED; + break; + } + CriticalAreaUnLock(lock); + + return ret; +} + +/** + * This function unbinds a task with cpu core. + * + * @param id task id + * + * @return EOK + */ +x_err_t _KTaskCoreUnCombine(KTaskDescriptorType task) +{ + x_base lock = 0; + int ret = EOK; + uint8 task_stat = 0; + + NULL_PARAM_CHECK(task); + + lock = CriticalAreaLock(); + + if (0 == strncmp("ktaskidle",task->task_base_info.name, strlen("ktaskidle"))) + { + KPrintf("IDLE task is forbidden to uncombine cpu.\n"); + + CriticalAreaUnLock(lock); + return -ERROR; + } + + task_stat = KTaskStatGet(task); + switch(task_stat) + { + case KTASK_READY: + HwLockSpinlock(&AssignSpinLock); + Assign.ready_vector_done->remove(task); + task->task_smp_info.combined_coreid = UNCOMBINE_CPU_CORE; + Assign.ready_vector_done->insert(task); + HwUnlockSpinlock(&AssignSpinLock); + break; + case KTASK_INIT: + case KTASK_SUSPEND: + task->task_smp_info.combined_coreid = UNCOMBINE_CPU_CORE; + break; + case KTASK_CLOSE: + case KTASK_RUNNING: + KPrintf("the CLOSE and RUNNING stat of task is forbidden to change cpu core.\n"); + ret = -ERROR; + break; + default: + KPrintf("%s invalid task stat.\n",__func__); + ret = -EINVALED; + break; + } + CriticalAreaUnLock(lock); + + return ret; +} +#endif + + + +/** + * timeout function of task timer,this function removes the suspend task and add to ready queue + * then start a new schedule + * + * @param parameter arg for task timeout function + */ +void KTaskTimeout(void *parameter) +{ + x_base lock = 0; + struct TaskDescriptor *task = NONE; + + NULL_PARAM_CHECK(parameter); + + lock = CriticalAreaLock(); + + task = (struct TaskDescriptor *)parameter; + + if(RET_TRUE == JudgeKTaskStatIsSuspend(task)) { + task->exstatus = -ETIMEOUT; + DoubleLinkListRmNode(&(task->task_dync_sched_member.sched_link)); +#ifdef ARCH_SMP + HwLockSpinlock(&AssignSpinLock); +#endif + Assign.ready_vector_done->insert(task); +#ifdef ARCH_SMP + HwUnlockSpinlock(&AssignSpinLock); +#endif + CriticalAreaUnLock(lock); + DO_KTASK_ASSIGN; + } else { + CriticalAreaUnLock(lock); + } +} + + +/* + * update the exception status + * + */ +void KUpdateExstatus(x_err_t status) +{ + if (status < EOK || status >= INVALID_TASK_ERROR) { + KPrintf("Illegal status code %d\n", status); + return; + } + + if (isrManager.done->getCounter() == 0) { + KTaskDescriptorType CurrentTask; + CurrentTask = GetKTaskDescriptor(); + if (CurrentTask != NONE) { + CurrentTask->exstatus = -status; + } else { + __exstatus = -status; + return; + } + } else { + __exstatus = -status; + return; + } +} + + +/** + * obtain current exception status + * + */ +int *KObtainExstatus(void) +{ + if (isrManager.done->getCounter() == 0) { + KTaskDescriptorType CurrentTask; + CurrentTask = GetKTaskDescriptor(); + if (CurrentTask != NONE) { + return (int *) & (CurrentTask->exstatus); + } else { + return (int *)&__exstatus; + } + } else { + return (int *)&__exstatus; + } +} + +/** + * This function will resume a task. + * + * @param id task id + * + */ +x_err_t _KTaskWakeup(KTaskDescriptorType task) +{ + x_base lock = 0; + + NULL_PARAM_CHECK(task); + + if (RET_TRUE != JudgeKTaskStatIsSuspend(task)) { + SYS_KDEBUG_LOG(KDBG_KTASK, ("task stat must be suspend error stat is , %d\n", KTaskStatGet(task))); + return -ERROR; + } + + SYS_KDEBUG_LOG(KDBG_KTASK, ("wakeup task name: %s\n", task->task_base_info.name)); + + lock = CriticalAreaLock(); + + DoubleLinkListRmNode(&(task->task_dync_sched_member.sched_link)); + KTaskUnSetDelay(task); +#ifdef ARCH_SMP + HwLockSpinlock(&AssignSpinLock); +#endif + Assign.ready_vector_done->insert(task); +#ifdef ARCH_SMP + HwUnlockSpinlock(&AssignSpinLock); +#endif + CriticalAreaUnLock(lock); + + HOOK(hook.task.hook_TaskResume,(task)); + return EOK; +} + +/** + * This function will suspend a task. + * + * @param id task id + * + */ +x_err_t _SuspendKTask(KTaskDescriptorType task) +{ + x_base lock = 0; + + NULL_PARAM_CHECK(task); + + if (task != GetKTaskDescriptor()) { + SYS_KDEBUG_LOG(KDBG_KTASK, ("running task is forbidden to suspend the others.\n")); + return -ERROR; + } + + if(RET_TRUE != JudgeKTaskStatIsReady(task) && RET_TRUE != JudgeKTaskStatIsRunning(task)) { + SYS_KDEBUG_LOG(KDBG_KTASK, ("task stat 0x%2x is forbidden to suspend.\n", KTaskStatGet(task))); + return -ERROR; + } + + if(RET_TRUE == JudgeKTaskStatIsSuspend(task)) { + SYS_KDEBUG_LOG(KDBG_KTASK, ("task stat is already suspend.\n")); + return -ERROR; + } + + SYS_KDEBUG_LOG(KDBG_KTASK, ("suspend task name: %s\n", task->task_base_info.name)); + + lock = CriticalAreaLock(); +#ifdef ARCH_SMP + HwLockSpinlock(&AssignSpinLock); +#endif + Assign.ready_vector_done->remove(task); +#ifdef ARCH_SMP + HwUnlockSpinlock(&AssignSpinLock); +#endif + KTaskStateSet(task, KTASK_SUSPEND); + KTaskUnSetDelay(task); + + CriticalAreaUnLock(lock); + + HOOK(hook.task.hook_TaskSuspend,(task)); + return EOK; +} + +/** + * + * kernel task exit function,inster the task to defuction task. + * + */ +void KTaskQuit(void) +{ + x_base lock = 0; + struct TaskDescriptor *task = NONE; + + lock = CriticalAreaLock(); + task = GetKTaskDescriptor(); + if(NONE != task) { + + _KTaskResourceDelete(task); + + DoubleLinkListInsertNodeAfter(&KTaskZombie, &(task->task_dync_sched_member.sched_link)); + + if (JudgeZombieKTaskIsNotEmpty()) { + KTaskWakeup(zombie_recycle); + } + } + CriticalAreaUnLock(lock); + + DO_KTASK_ASSIGN; +} + +/** + * This function will insert task to ready queue then schedule + * + * @param id task id + * + */ +x_err_t _StartupKTask(KTaskDescriptorType task) +{ + x_base lock = 0; + + lock = CriticalAreaLock(); + + NULL_PARAM_CHECK(task); + + if(JudgeKTaskStatIsInit(task) != RET_TRUE) { + SYS_KDEBUG_LOG(KDBG_KTASK, ("task [%s] stat [%d] is not init\n", + task->task_base_info.name, task->task_dync_sched_member.stat)); + CriticalAreaUnLock(lock); + return -ERROR; + } + + task->task_dync_sched_member.cur_prio = task->task_base_info.origin_prio; + + __BitmapSiteMask(task); + + DoubleLinkListRmNode(&(task->task_dync_sched_member.sched_link)); + KTaskUnSetDelay(task); +#ifdef ARCH_SMP + HwLockSpinlock(&AssignSpinLock); +#endif + Assign.ready_vector_done->insert(task); +#ifdef ARCH_SMP + HwUnlockSpinlock(&AssignSpinLock); +#endif + CriticalAreaUnLock(lock); + + SYS_KDEBUG_LOG(KDBG_KTASK, ("task [%s] is ready to run,the priority is [%d]\n", + task->task_base_info.name, task->task_base_info.origin_prio)); + + if (GetKTaskDescriptor() != NONE) { + DO_KTASK_ASSIGN; + } + + return EOK; +} + +/** + * This function will remove a dynamic task out of the task manage list. + * + * @param id task id + * + */ +x_err_t _DeleteKTask(KTaskDescriptorType task) +{ + x_base lock = 0; + + NULL_PARAM_CHECK(task); + + if(RET_TRUE == __JudgeKTaskIsIdleOrZombierecycle(task)) { + KPrintf("idle or zombierecycle is not permitted to delete.\n"); + return -EINVALED; + } + + lock = CriticalAreaLock(); + + _KTaskResourceDelete(task); + + DoubleLinkListInsertNodeAfter(&KTaskZombie, &(task->task_dync_sched_member.sched_link)); + if (JudgeZombieKTaskIsNotEmpty()) { + KTaskWakeup(zombie_recycle); + } + CriticalAreaUnLock(lock); + + DO_KTASK_ASSIGN; + + return EOK; +} + +/** + * + * This function will init a kernel task's base info . + * + * @param task kernel task descripter + * @param name task name + * @param entry task process function + * @param parameter task arg + * @param stack_size task stack size + * @param priority task priority + * + */ +static x_err_t _KTaskBaseInfoParse(KTaskDescriptorType task, + const char *name, + void (*entry)(void *parameter), + void *parameter, + uint32 stack_depth, + uint8 priority) +{ + + NULL_PARAM_CHECK(task); + NULL_PARAM_CHECK(name); + NULL_PARAM_CHECK(entry); + + if (priority >= KTASK_PRIORITY_MAX) { + KPrintf("%s %d Invalid task priority[%d] set.\n",__func__,__LINE__,priority); + return -EINVALED; + } +#ifdef SEPARATE_COMPILE + if(1 == task->task_dync_sched_member.isolation_flag ) { + task->task_base_info.stack_start = (void *)x_umalloc(stack_depth); + } else +#endif + { + task->task_base_info.stack_start = (void *)KERNEL_MALLOC(stack_depth); + } + + + if (task->task_base_info.stack_start == NONE) { + KPrintf("%s %d malloc task %s stack depth %d failed.\n",__func__,__LINE__,name,stack_depth); + return -ENOMEMORY; + } + task->task_base_info.stack_depth = stack_depth; + + memset(task->task_base_info.stack_start, '#', task->task_base_info.stack_depth); + + strncpy(task->task_base_info.name, name, NAME_NUM_MAX); + task->task_base_info.func_entry = (void *)entry; + task->task_base_info.func_param = parameter; + task->task_base_info.origin_prio = priority; + + KTaskStackSetup(task); + + return EOK; + +} +/** + * + * This function will init a kernel task's dynamic member . + * + * @param task task descriptor + * @param tick task time slice + */ +static void _KTaskDyncMemberInit(KTaskDescriptorType task) +{ + NULL_PARAM_CHECK(task); + + InitDoubleLinkList(&(task->task_dync_sched_member.sched_link)); + + task->task_dync_sched_member.cur_prio = task->task_base_info.origin_prio; + task->task_dync_sched_member.bitmap_column = 0; +#if KTASK_PRIORITY_MAX > 32 + task->task_dync_sched_member.bitmap_offset = 0; + task->task_dync_sched_member.bitmap_row = 0; +#endif + +#if defined(SCHED_POLICY_FIFO) + FifoTaskTimesliceInit(task); +#elif defined (SCHED_POLICY_RR) + RoundRobinTaskTimesliceInit(task); +#elif defined (SCHED_POLICY_RR_REMAINSLICE) + RoundRobinRemainTaskTimesliceInit(task); +#endif + + task->task_dync_sched_member.advance_cnt = 0; + task->exstatus = EOK; + KTaskStatSetAsInit(task); + +} + +#ifdef ARCH_SMP +/** + * + * This function will init a kernel task's smp info . + * + * @param task task descriptor + */ +static void _KTaskSmpInfoInit(KTaskDescriptorType task) +{ + NULL_PARAM_CHECK(task); + + task->task_smp_info.combined_coreid = UNCOMBINE_CPU_CORE; + task->task_smp_info.runing_coreid = UNCOMBINE_CPU_CORE; + task->task_smp_info.critical_lock_cnt = 0; +} +#endif +/** + * + * This function init a kernel task in dynamic way . + * + * @param name task name + * @param parameter task process function + * @param parameter task arg + * @param stack_size task stack size + * @param priority task priority + * @param tick task time slice + */ +int32 _InitKTask(KTaskDescriptorType task, + const char *name, + void (*entry)(void *parameter), + void *parameter, + uint32 stack_depth, + uint8 priority) +{ + int32 ret = 0; + NULL_PARAM_CHECK(task); + + ret = _KTaskBaseInfoParse(task, name, entry, parameter, stack_depth, priority); + if (ret < 0) { + KPrintf("%s %d task %s baseinfo parse failed.\n",__func__,__LINE__,name); + return -ERROR; + } + + _KTaskDyncMemberInit(task); + +#ifdef ARCH_SMP + _KTaskSmpInfoInit(task); +#endif + return EOK; +} + +static struct KTaskDone Done = { + .init = _InitKTask, + .start = _StartupKTask, + .Delete = _DeleteKTask, + .delay = _DelayKTask, + .mdelay = _MdelayKTask, + .prioset = _KTaskPrioSet, +#ifdef ARCH_SMP + .combine = _KTaskCoreCombine, + .uncombine = _KTaskCoreUnCombine, +#endif + .suspend = _SuspendKTask, + .wake = _KTaskWakeup +}; + +/** + * + * This function init a kernel task in dynamic way . + * + * @param name task name + * @param parameter task process function + * @param parameter task arg + * @param stack_size task stack size + * @param priority task priority + * @param tick task time slice + * + * @return EOK on success; ERROR/ENOMEMORY on failure + */ +int32 KTaskCreate(const char *name, + void (*entry)(void *parameter), + void *parameter, + uint32 stack_depth, + uint8 priority) +{ + struct TaskDescriptor *task = NONE; + int32 id = 0; + x_base lock = 0; + + KDEBUG_NOT_IN_INTERRUPT; + task = (struct TaskDescriptor *)KERNEL_MALLOC(sizeof(struct TaskDescriptor)); + if (task == NONE) { + KPrintf("%s %d TaskDescriptor %s malloc failed.\n",__func__,__LINE__,name); + return -ENOMEMORY; + } + memset(task, 0x0, sizeof(struct TaskDescriptor)); + lock = CriticalAreaLock(); + id = IdInsertObj(&k_task_id_manager, &task->id); + if (id < 0) { + KPrintf("%s %d task id malloc failed.\n",__func__,__LINE__); + CriticalAreaUnLock(lock); + KERNEL_FREE(task); + return -ENOMEMORY; + } + + DoubleLinkListInsertNodeAfter(&xiaoshan_task_head, &(task->link)); + + task->Done = &Done; + CriticalAreaUnLock(lock); + + if( task->Done->init(task, name, entry, parameter, stack_depth, priority) == EOK ) { + HOOK(hook.task.hook_TaskCreate, (task)); + return id; + } else { + KPrintf("%s %d task init failed.\n",__func__,__LINE__); + lock = CriticalAreaLock(); + IdRemoveObj(&k_task_id_manager, id); + CriticalAreaUnLock(lock); + KERNEL_FREE(task); + return -ERROR; + } +} + +/** + * This function will insert task to ready queue then schedule + * + * @param id task id + * + * @return EOK on success; EINVALED on failure + */ +x_err_t StartupKTask(int32 id) +{ + struct TaskDescriptor *task = NONE; + + if(id < 0) { + return -EINVALED; + } + + task = GetTaskWithIdnodeInfo(id); + NULL_PARAM_CHECK(task); + + return task->Done->start(task); +} + +/** + * This function will remove a dynamic task out of the task manage list. + * + * @param id task id + * + * @return EOK on success; EINVALED on failure + */ +x_err_t KTaskDelete(int32 id) +{ + struct TaskDescriptor *task = NONE; + + if(id < 0) { + return -EINVALED; + } + + task = GetTaskWithIdnodeInfo(id); + NULL_PARAM_CHECK(task); + + return task->Done->Delete(task); +} + +/** + * This function will delay current task running with some ticks. + * + * @param tick delay ticks + * @return EOK on success; EINVALED/EEMPTY on failure + */ +x_err_t DelayKTask(x_ticks_t ticks) +{ + KTaskDescriptorType task = NONE; + + if (ticks == 0) { + KPrintf("Timeout ticks must be setted more than 0.\n"); + return -EINVALED; + } + + task = GetKTaskDescriptor(); + if (task == NONE) + { + return -EEMPTY; + } + return task->Done->delay(task, ticks); +} + +/** + * This function will delay current task wite milliseconds. + * + * @param ms milliseconds of delay time + * + * @return EOK on success; EINVALED/EEMPTY on failure + * + */ +x_err_t MdelayKTask(uint32 ms) +{ + KTaskDescriptorType task = NONE; + + if (0 == ms) { + return -EINVALED; + } + + task = GetKTaskDescriptor(); + if (task == NONE) + { + return -EEMPTY; + } + return task->Done->mdelay(task, ms); +} + +/** + * This function sets the task's priority. + * + * @param id task id + * @param prio priority value + * + * @return EOK + */ +x_err_t KTaskPrioSet(int32 id, uint8 prio) +{ + struct TaskDescriptor *task = NONE; + + task = GetTaskWithIdnodeInfo(id); + NULL_PARAM_CHECK(task); + + return task->Done->prioset(task, prio); +} + +#ifdef ARCH_SMP +/** + * This function binds a task to cpu core. + * + * @param id task id + * @param coreid cpu core id + * + * @return EOK + */ +x_err_t KTaskCoreCombine(int32 id, uint8 coreid) +{ + struct TaskDescriptor *task = NONE; + + task = GetTaskWithIdnodeInfo(id); + NULL_PARAM_CHECK(task); + + return task->Done->combine(task,coreid); +} + +/** + * This function unbinds a task with cpu core. + * + * @param id task id + * + * @return EOK + */ +x_err_t KTaskCoreUnCombine(int32 id) +{ + struct TaskDescriptor *task = NONE; + + task = GetTaskWithIdnodeInfo(id); + NULL_PARAM_CHECK(task); + + return task->Done->uncombine(task); +} +#endif +/** + * This function will suspend a task. + * + * @param id task id + * + * @return EOK + */ +x_err_t SuspendKTask(int32 id) +{ + struct TaskDescriptor *task = NONE; + + task = GetTaskWithIdnodeInfo(id); + NULL_PARAM_CHECK(task); + + return task->Done->suspend(task); +} + +/** + * This function will resume a task. + * + * @param id task id + * + * @return EOK + */ +x_err_t KTaskWakeup(int32 id) +{ + x_base lock = 0; + struct TaskDescriptor *task = NONE; + + task = GetTaskWithIdnodeInfo(id); + NULL_PARAM_CHECK(task); + + return task->Done->wake(task); +} + + +#ifdef SEPARATE_COMPILE +/** + * find the first user task in manage list. + * + * @param + * + * @note in interrupt status,this function is not permitted to call. + */ +int UTaskSearch(void) +{ + x_base lock = 0; + KTaskDescriptorType temp_task = NONE; + struct SysDoubleLinklistNode *node = NONE; + + lock = CriticalAreaLock(); + + DOUBLE_LINKLIST_FOR_EACH(node,&xiaoshan_task_head) + { + temp_task = SYS_DOUBLE_LINKLIST_ENTRY(node, struct TaskDescriptor, link); + if (1 == temp_task->task_dync_sched_member.isolation_flag) + { + CriticalAreaUnLock(lock); + return temp_task->id.id; + } + } + + CriticalAreaUnLock(lock); + + return -1; +} + +/** + * + * This function init a user task in dynamic way . + * + * @param name task name + * @param parameter task process function + * @param parameter task arg + * @param stack_size task stack size + * @param priority task priority + * @param tick task time slice + * + * @return EOK on success; ENOMEMORY/EEMPTY on failure + */ + +int32 UTaskCreate(const char *name, + void (*entry)(void *parameter), + void *parameter, + uint32 stack_depth, + uint8 priority) +{ + struct TaskDescriptor *task = NONE; + int32 id = 0; + x_base lock = 0; + + KDEBUG_NOT_IN_INTERRUPT; + KPrintf("create user task.\n"); + task = (struct TaskDescriptor *)KERNEL_MALLOC(sizeof(struct TaskDescriptor)); + if (task == NONE) + { + KPrintf("%s %d TaskDescriptor malloc failed.\n",__func__,__LINE__); + return -ENOMEMORY; + } + memset(task, 0x0, sizeof(struct TaskDescriptor)); + + task->task_dync_sched_member.isolation_flag = 1; + task->task_dync_sched_member.isolation_status = 0; + + lock = CriticalAreaLock(); + id = IdInsertObj(&k_task_id_manager, &task->id); + if (id < 0) { + KPrintf("%s %d task id malloc failed.\n",__func__,__LINE__); + CriticalAreaUnLock(lock); + KERNEL_FREE(task); + return -ENOMEMORY; + } + + DoubleLinkListInsertNodeAfter(&xiaoshan_task_head, &(task->link)); + + task->Done = &Done; + CriticalAreaUnLock(lock); + + if( task->Done->init(task, name, entry, parameter, stack_depth, priority) == EOK ) { + HOOK(hook.task.hook_TaskCreate, (task)); +#ifdef MOMERY_PROTECT_ENABLE +//setup pmp + if( mem_access.InitIsolation != NONE) + { + mem_access.InitIsolation(&task->task_dync_sched_member.isolation, (x_ubase)task->task_base_info.stack_start , task->task_base_info.stack_depth); + } +#endif + return id; + } else { + KPrintf("%s %d task init failed.\n",__func__,__LINE__); + lock = CriticalAreaLock(); + IdRemoveObj(&k_task_id_manager, id); + CriticalAreaUnLock(lock); + KERNEL_FREE(task); + return -ERROR; + } +} + +#endif diff --git a/Ubiquitous/XiZi/kernel/thread/ktask_stat.c b/Ubiquitous/XiZi/kernel/thread/ktask_stat.c new file mode 100644 index 0000000..89eff0f --- /dev/null +++ b/Ubiquitous/XiZi/kernel/thread/ktask_stat.c @@ -0,0 +1,105 @@ +/* +* Copyright (c) 2020 AIIT XUOS Lab +* XiUOS is licensed under Mulan PSL v2. +* You can use this software according to the terms and conditions of the Mulan PSL v2. +* You may obtain a copy of Mulan PSL v2 at: +* http://license.coscl.org.cn/MulanPSL2 +* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, +* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, +* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. +* See the Mulan PSL v2 for more details. +*/ + +/** +* @file: ktask_stat.c +* @brief: the stat function definition of task +* @version: 1.0 +* @author: AIIT XUOS Lab +* @date: 2020/3/15 +* +*/ + +#ifndef XS_KTASK_STAT_H +#define XS_KTASK_STAT_H + +#include +#include +#include +#include +#include + +void KTaskStateSet(KTaskDescriptorType task, uint8 stat) +{ + NULL_PARAM_CHECK(task); + task->task_dync_sched_member.stat = stat | (task->task_dync_sched_member.stat & ~KTASK_STAT_MASK); +} + +void KTaskStatSetAsInit(KTaskDescriptorType task) +{ + NULL_PARAM_CHECK(task); + KTaskStateSet(task, KTASK_INIT); +} + +void KTaskStatSetAsReady(KTaskDescriptorType task) +{ + NULL_PARAM_CHECK(task); + KTaskStateSet(task, KTASK_READY); +} + +void KTaskStatSetAsSuspend(KTaskDescriptorType task) +{ + NULL_PARAM_CHECK(task); + KTaskStateSet(task, KTASK_SUSPEND); +} + +void KTaskStatSetAsRunning(KTaskDescriptorType task) +{ + NULL_PARAM_CHECK(task); + KTaskStateSet(task, KTASK_RUNNING); +} + +void KTaskStatSetAsClose(KTaskDescriptorType task) +{ + NULL_PARAM_CHECK(task); + KTaskStateSet(task, KTASK_CLOSE); +} + +uint8 KTaskStatGet(KTaskDescriptorType task) +{ + NULL_PARAM_CHECK(task); + return task->task_dync_sched_member.stat & KTASK_STAT_MASK; +} + +bool JudgeKTaskStatIsInit(KTaskDescriptorType task) +{ + NULL_PARAM_CHECK(task); + return ((task->task_dync_sched_member.stat & KTASK_STAT_MASK) == KTASK_INIT); +} + +bool JudgeKTaskStatIsReady(KTaskDescriptorType task) +{ + NULL_PARAM_CHECK(task); + return ((task->task_dync_sched_member.stat & KTASK_STAT_MASK) == KTASK_READY); +} + +bool JudgeKTaskStatIsSuspend(KTaskDescriptorType task) +{ + NULL_PARAM_CHECK(task); + return ((task->task_dync_sched_member.stat & KTASK_STAT_MASK) == KTASK_SUSPEND); +} + +bool JudgeKTaskStatIsRunning(KTaskDescriptorType task) +{ + NULL_PARAM_CHECK(task); + return ((task->task_dync_sched_member.stat & KTASK_STAT_MASK) == KTASK_RUNNING); +} + +bool JudgeKTaskStatIsClose(KTaskDescriptorType task) +{ + NULL_PARAM_CHECK(task); + return ((task->task_dync_sched_member.stat & KTASK_STAT_MASK) == KTASK_CLOSE); +} + +#endif + + diff --git a/Ubiquitous/XiZi/kernel/thread/linklist.c b/Ubiquitous/XiZi/kernel/thread/linklist.c new file mode 100644 index 0000000..2d6a060 --- /dev/null +++ b/Ubiquitous/XiZi/kernel/thread/linklist.c @@ -0,0 +1,132 @@ +/* +* Copyright (c) 2020 AIIT XUOS Lab +* XiUOS is licensed under Mulan PSL v2. +* You can use this software according to the terms and conditions of the Mulan PSL v2. +* You may obtain a copy of Mulan PSL v2 at: +* http://license.coscl.org.cn/MulanPSL2 +* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, +* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, +* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. +* See the Mulan PSL v2 for more details. +*/ + +/** +* @file: linklist.c +* @brief: suspend and wakeup function of task +* @version: 1.0 +* @author: AIIT XUOS Lab +* @date: 2020/3/15 +* +*/ + +#include + +/** + * a task will be suspended to a pend list + * + * @param list suspend task list + * @param task the task descriptor need to be suspended + * @param flag suspend flag + * + */ + x_err_t LinklistSuspend(DoubleLinklistType *list, + struct TaskDescriptor *task, + uint8 flag) +{ + int32 ret = EOK; + x_ubase lock = 0; + DoubleLinklistType *node = NONE; + DoubleLinklistType *tail = NONE; + struct TaskDescriptor *tmp_task = NONE; + + NULL_PARAM_CHECK(list); + NULL_PARAM_CHECK(task); + + lock = CriticalAreaLock(); + + SuspendKTask(task->id.id); + switch (flag) + { + case LINKLIST_FLAG_FIFO: + DoubleLinkListInsertNodeBefore(list, &(task->task_dync_sched_member.sched_link)); + break; + + case LINKLIST_FLAG_PRIO: + DOUBLE_LINKLIST_FOR_EACH(node,list) + { + tmp_task = SYS_DOUBLE_LINKLIST_ENTRY(node, struct TaskDescriptor, task_dync_sched_member.sched_link); + if (task->task_dync_sched_member.cur_prio < tmp_task->task_dync_sched_member.cur_prio) + { + break; + } + } + if(node != list) { + DoubleLinkListInsertNodeBefore(&(tmp_task->task_dync_sched_member.sched_link), &(task->task_dync_sched_member.sched_link)); + } else { + tail = list->node_prev; + DoubleLinkListInsertNodeAfter(tail,&(task->task_dync_sched_member.sched_link)); + } + break; + + default: + ret = -EINVALED; + break; + } + CriticalAreaUnLock(lock); + return ret; +} + +/** + * resume the first task in the suspend list + * + * @param list task list + * + */ + x_err_t LinklistResume(DoubleLinklistType *list) +{ + x_ubase lock = 0; + struct TaskDescriptor *task = NONE; + + NULL_PARAM_CHECK(list); + + lock = CriticalAreaLock(); + + task = SYS_DOUBLE_LINKLIST_ENTRY(list->node_next, struct TaskDescriptor, task_dync_sched_member.sched_link); + SYS_KDEBUG_LOG(KDBG_IPC, ("resume task:%s\n", task->task_base_info.name)); + + KTaskWakeup(task->id.id); + + CriticalAreaUnLock(lock); + + return EOK; +} + +/** + * wakeup all the task in the suspend list + * + * @param list task list + * + */ + x_err_t LinklistResumeAll(DoubleLinklistType *list) +{ + x_ubase lock = 0; + struct TaskDescriptor *task = NONE; + DoubleLinklistType *node = NONE; + + NULL_PARAM_CHECK(list); + + lock = CriticalAreaLock(); + for(;;) { + node = list->node_next; + if(node != list) { + task = SYS_DOUBLE_LINKLIST_ENTRY(node, struct TaskDescriptor, task_dync_sched_member.sched_link); + task->exstatus = -ERROR; + KTaskWakeup(task->id.id); + } else { + break; + } + } + CriticalAreaUnLock(lock); + + return EOK; +} diff --git a/Ubiquitous/XiZi/kernel/thread/lock.c b/Ubiquitous/XiZi/kernel/thread/lock.c new file mode 100644 index 0000000..d91628d --- /dev/null +++ b/Ubiquitous/XiZi/kernel/thread/lock.c @@ -0,0 +1,110 @@ +/* +* Copyright (c) 2020 AIIT XUOS Lab +* XiUOS is licensed under Mulan PSL v2. +* You can use this software according to the terms and conditions of the Mulan PSL v2. +* You may obtain a copy of Mulan PSL v2 at: +* http://license.coscl.org.cn/MulanPSL2 +* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, +* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, +* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. +* See the Mulan PSL v2 for more details. +*/ + +/** +* @file: lock.c +* @brief: system spinlock file +* @version: 1.0 +* @author: AIIT XUOS Lab +* @date: 2020/3/15 +* +*/ + +#include +#include +#include + +#ifdef ARCH_SMP +struct SpinLockfileOps spinlock; +/* + * lock scheduler + */ +static void DisablePreempt(void) +{ + x_base lock = 0; + + lock = DisableLocalInterrupt(); + Assign.assign_lock[GetCpuId()] ++; + EnableLocalInterrupt(lock); +} + +/* + * enable scheduler + */ +static void EnablePreempt(void) +{ + x_base lock = 0; + + lock = DisableLocalInterrupt(); + Assign.assign_lock[GetCpuId()] --; + DO_KTASK_ASSIGN; + EnableLocalInterrupt(lock); +} + + void InitSpinLock( struct SpinLockfileOps * spinlock) +{ + InitHwSpinlock(&spinlock->node_lock.lock); + spinlock->SPinLock = _SpinLock; + spinlock->UnlockSpinLock =_UnlockSpinLock; + spinlock->UnlockSpinLockIrqRestore = _UnlockSpinLockIrqRestore; + spinlock->SpinLockIrqSave = _SpinLockIrqSave; + +} + +void _SpinLock(struct SpinLockfileOps * spinlock) +{ + DisablePreempt(); + HwLockSpinlock(&spinlock->node_lock.lock); +} + +void _UnlockSpinLock(struct SpinLockfileOps * spinlock) +{ + HwUnlockSpinlock(&spinlock->node_lock.lock); + EnablePreempt(); +} + +x_base _SpinLockIrqSave(struct SpinLockfileOps * spinlock) +{ + x_base lock = 0; + + DisablePreempt(); + + lock = DisableLocalInterrupt(); + HwLockSpinlock(&spinlock->node_lock.lock); + + return lock; +} + +void _UnlockSpinLockIrqRestore(struct SpinLockfileOps * spinlock, x_base lock) +{ + HwUnlockSpinlock(&spinlock->node_lock.lock); + EnableLocalInterrupt(lock); + + EnablePreempt(); +} +#endif +/** + * This function will restore the scheduler lock status + * + */ +void RestoreCpusLockStatus(struct TaskDescriptor *task) +{ +#ifdef ARCH_SMP + Assign.smp_os_running_task[GetCpuId()] = task; + HwUnlockSpinlock(&AssignSpinLock); +#else + Assign.os_running_task = task; +#endif +} + + + diff --git a/Ubiquitous/XiZi/kernel/thread/msgqueue.c b/Ubiquitous/XiZi/kernel/thread/msgqueue.c new file mode 100644 index 0000000..6a253dd --- /dev/null +++ b/Ubiquitous/XiZi/kernel/thread/msgqueue.c @@ -0,0 +1,497 @@ +/* +* Copyright (c) 2020 AIIT XUOS Lab +* XiUOS is licensed under Mulan PSL v2. +* You can use this software according to the terms and conditions of the Mulan PSL v2. +* You may obtain a copy of Mulan PSL v2 at: +* http://license.coscl.org.cn/MulanPSL2 +* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, +* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, +* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. +* See the Mulan PSL v2 for more details. +*/ + +/** +* @file: msgqueue.c +* @brief: msgqueue file +* @version: 1.0 +* @author: AIIT XUOS Lab +* @date: 2020/3/15 +* +*/ + +#include +#include + +DECLARE_ID_MANAGER(k_mq_id_manager, ID_NUM_MAX); +DoubleLinklistType k_mq_list = {&k_mq_list, &k_mq_list}; + +struct MqMessage +{ + struct MqMessage *next; +}; + +static struct MsgQueue *GetMsgQueueById(int32 id) +{ + x_base lock = 0; + struct MsgQueue *mq = NONE; + struct IdNode *idnode = NONE; + + if (id < 0 ) + return NONE; + + lock = CriticalAreaLock(); + idnode = IdGetObj(&k_mq_id_manager, id); + if (idnode == NONE){ + CriticalAreaUnLock(lock); + return NONE; + } + mq = CONTAINER_OF(idnode, struct MsgQueue, id); + CriticalAreaUnLock(lock); + return mq; +} + +static x_err_t _InitMsgQueue( struct MsgQueue *mq ,x_size_t msg_size, + x_size_t max_msgs ) +{ + x_base lock = 0; + + NULL_PARAM_CHECK(mq); + + mq->max_msgs = max_msgs; + mq->num_msgs = 0; + mq->each_len = ALIGN_MEN_UP(msg_size, MEM_ALIGN_SIZE); + mq->index = 0; + + InitDoubleLinkList(&mq->send_pend_list); + InitDoubleLinkList(&(mq->recv_pend_list)); + + mq->msg_buf = x_malloc( mq->each_len * mq->max_msgs); + if (mq->msg_buf == NONE) { + lock = CriticalAreaLock(); + DoubleLinkListRmNode(&(mq->link)); + CriticalAreaUnLock(lock); + KERNEL_FREE(mq); + return -ENOMEMORY; + } + + return EOK; +} + +static x_err_t _MsgQueueSend(struct MsgQueue *mq, + const void *buffer, + x_size_t size, + int32 msec) +{ + x_ubase lock = 0; + uint32 tick_delta = 0; + int32 timeout = 0; + uint8 *msg = NONE; + struct TaskDescriptor *task = NONE; + + NULL_PARAM_CHECK(mq); + NULL_PARAM_CHECK(buffer); + + if (size > mq->each_len) + return -ERROR; + + tick_delta = 0; + task = GetKTaskDescriptor(); + timeout = CalculteTickFromTimeMs(msec); + lock = CriticalAreaLock(); + if (mq->num_msgs >= mq->max_msgs && timeout == 0) { + CriticalAreaUnLock(lock); + return -EFULL; + } + + while(mq->num_msgs >= mq->max_msgs ) { + + task->exstatus = EOK; + if (timeout == 0) { + CriticalAreaUnLock(lock); + return -EFULL; + } + KDEBUG_IN_KTASK_CONTEXT; + LinklistSuspend(&(mq->send_pend_list), task, LINKLIST_FLAG_FIFO); + + if (timeout > 0) { + tick_delta = CurrentTicksGain(); + SYS_KDEBUG_LOG(KDBG_IPC, ("mq_send_wait: start timer of task:%s\n", + task->task_base_info.name)); + KTaskSetDelay(task,timeout); + } + + CriticalAreaUnLock(lock); + DO_KTASK_ASSIGN; + + if (task->exstatus != EOK) { + return task->exstatus; + } + + lock = CriticalAreaLock(); + + if (timeout > 0) { + tick_delta = CurrentTicksGain() - tick_delta; + timeout -= tick_delta; + if (timeout < 0) + timeout = 0; + } + } + + msg = mq->msg_buf + ( ( mq->index + mq->num_msgs ) % mq->max_msgs ) * mq->each_len ; + memcpy(msg, buffer, size); + mq->num_msgs ++; + if (!IsDoubleLinkListEmpty(&mq->recv_pend_list)) { + LinklistResume(&(mq->recv_pend_list)); + CriticalAreaUnLock(lock); + DO_KTASK_ASSIGN; + return EOK; + } + + CriticalAreaUnLock(lock); + return EOK; +} + +static x_err_t _MsgQueueUrgentSend(struct MsgQueue *mq, const void *buffer, x_size_t size) +{ + x_ubase lock = 0; + uint8 *msg = NONE; + + NULL_PARAM_CHECK(mq); + NULL_PARAM_CHECK(buffer); + + if (size > mq->each_len) + return -ERROR; + + lock = CriticalAreaLock(); + if (mq->num_msgs >= mq->max_msgs) { + CriticalAreaUnLock(lock); + return -EFULL; + } + + mq->index --; + if (mq->index < 0) + mq->index += mq->max_msgs; + + msg = mq->msg_buf + ( ( mq->index + mq->num_msgs ) % mq->max_msgs ) * mq->each_len ; + memcpy(msg , buffer, size); + mq->num_msgs ++; + if (!IsDoubleLinkListEmpty(&mq->send_pend_list)) { + LinklistResume(&(mq->send_pend_list)); + CriticalAreaUnLock(lock); + DO_KTASK_ASSIGN; + return EOK; + } + + CriticalAreaUnLock(lock); + + return EOK; +} + +static x_err_t _MsgQueueRecv(struct MsgQueue *mq, + void *buffer, + x_size_t size, + int32 msec) +{ + x_ubase lock = 0; + uint32 tick_delta = 0; + int32 timeout = 0; + struct MqMessage *msg = NONE; + struct TaskDescriptor *task = NONE; + + NULL_PARAM_CHECK(mq); + NULL_PARAM_CHECK(buffer); + + tick_delta = 0; + task = GetKTaskDescriptor(); + timeout = CalculteTickFromTimeMs(msec); + lock = CriticalAreaLock(); + + if (mq->index == 0 && timeout == 0) { + CriticalAreaUnLock(lock); + return -ETIMEOUT; + } + + for( ; mq->num_msgs <= 0 ; ) { + KDEBUG_IN_KTASK_CONTEXT; + + task->exstatus = EOK; + if (timeout == 0) { + CriticalAreaUnLock(lock); + task->exstatus = -ETIMEOUT; + return -ETIMEOUT; + } + + LinklistSuspend(&(mq->recv_pend_list), + task, + LINKLIST_FLAG_FIFO); + + if (timeout > 0) { + tick_delta = CurrentTicksGain(); + SYS_KDEBUG_LOG(KDBG_IPC, ("set task:%s to timer list\n", + task->task_base_info.name)); + KTaskSetDelay(task,timeout); + } + + CriticalAreaUnLock(lock); + + DO_KTASK_ASSIGN; + + if (task->exstatus != EOK) { + return task->exstatus; + } + + lock = CriticalAreaLock(); + + if (timeout > 0) { + tick_delta = CurrentTicksGain() - tick_delta; + timeout -= tick_delta; + if (timeout < 0) + timeout = 0; + } + } + + msg = mq->msg_buf + mq->index * mq->each_len; + mq->index = (mq->index + 1) % mq->max_msgs; + memcpy(buffer, msg , size > mq->each_len ? mq->each_len : size); + mq->num_msgs --; + + if (!IsDoubleLinkListEmpty(&(mq->send_pend_list))) { + LinklistResume(&(mq->send_pend_list)); + CriticalAreaUnLock(lock); + + DO_KTASK_ASSIGN; + return EOK; + } + + CriticalAreaUnLock(lock); + + return EOK; +} + +static x_err_t _MsgQueueReinit(struct MsgQueue *mq) +{ + x_ubase lock = 0; + + NULL_PARAM_CHECK(mq); + + lock = CriticalAreaLock(); + + LinklistResumeAll(&mq->send_pend_list); + LinklistResumeAll(&(mq->recv_pend_list)); + mq->index = 0; + mq->num_msgs = 0; + CriticalAreaUnLock(lock); + DO_KTASK_ASSIGN; + + return EOK; +} + +static x_err_t _DeleteMsgQueue(struct MsgQueue *mq) +{ + x_base lock = 0; + + NULL_PARAM_CHECK(mq); + + LinklistResumeAll(&(mq->send_pend_list)); + LinklistResumeAll(&(mq->recv_pend_list)); + KERNEL_FREE(mq->msg_buf); + + lock = CriticalAreaLock(); + IdRemoveObj(&k_mq_id_manager, mq->id.id); + DoubleLinkListRmNode(&(mq->link)); + CriticalAreaUnLock(lock); + KERNEL_FREE(mq); + + return EOK; +} + +static struct MsgQueueDone Done = { + .init = _InitMsgQueue , + .urgensend = _MsgQueueUrgentSend, + .send = _MsgQueueSend, + .recv = _MsgQueueRecv, + .reinit = _MsgQueueReinit, + .Delete = _DeleteMsgQueue +}; + +/** + * This function will create a msg queue. + * + * @param msg_size the length of the msg queue. + * @param max_msgs the max length of the msg queue. + * + * @return id on success;ENOMEMORY/ERROR on failure + */ +int32 KCreateMsgQueue(x_size_t msg_size, + x_size_t max_msgs) +{ + int32 id = 0; + x_base temp = 0; + x_base lock = 0; + struct MsgQueue *mq = NONE; + + mq = (struct MsgQueue *)x_malloc(sizeof(struct MsgQueue)); + if (mq == NONE) + return -ENOMEMORY; + memset(mq,0x0,sizeof(struct MsgQueue)); + + lock = CriticalAreaLock(); + id = IdInsertObj(&k_mq_id_manager, &mq->id); + CriticalAreaUnLock(lock); + if (id < 0) { + x_free(mq); + return -ENOMEMORY; + } + + lock = CriticalAreaLock(); + DoubleLinkListInsertNodeAfter(&k_mq_list, &mq->link); + CriticalAreaUnLock(lock); + mq->Done = &Done; + if( mq->Done->init(mq, msg_size,max_msgs) == EOK ) + return mq->id.id; + else + return -ERROR; +} + +/** + * This function will reset a event. + * + * @param id the id number of event. + * + * @return EOK on success;EINVALED on failure + */ +x_err_t KMsgQueueReinit(int32 id) +{ + struct MsgQueue *mq = NONE; + + if (id < 0) + return -EINVALED; + + mq = GetMsgQueueById(id); + if (mq != NONE) + return mq->Done->reinit(mq); + else + return -EINVALED; + +} + +/** + * receive message with some waiting time + * + * @param id the message id + * @param buffer message info + * @param size the size of buffer + * @param timeout time needed waiting + * + * @return EOK on success;EINVALED on failure + * + */ +x_err_t KMsgQueueRecv(int32 id, + void *buffer, + x_size_t size, + int32 timeout) +{ + struct MsgQueue *mq = NONE; + if (id < 0) + return -EINVALED; + + mq = GetMsgQueueById(id); + if (mq != NONE) + return mq->Done->recv(mq,buffer,size,timeout); + else + return -EINVALED; + +} + +/** + * a dynamic messagequeue will be deleted from the manage list + * + * @param id the message id + * + * @return EOK on success;EINVALED on failure + * + */ +x_err_t KDeleteMsgQueue(int32 id) +{ + struct MsgQueue *mq = NONE; + if (id < 0) + return -EINVALED; + + mq = GetMsgQueueById(id); + if (mq != NONE) + return mq->Done->Delete(mq); + else + return -EINVALED; +} + +/** + * send urgent message without waiting time, this message will be inserted to the head of the queue + * + * @param id the message id + * @param buffer message info + * @param size the size of buffer + * + * @return EOK on success;EINVALED on failure + * + */ +x_err_t KMsgQueueUrgentSend(int32 id, const void *buffer, x_size_t size) +{ + struct MsgQueue *mq = NONE; + + if (id < 0) + return -EINVALED; + + mq = GetMsgQueueById(id); + if (mq != NONE) + return mq->Done->urgensend(mq,buffer,size); + else + return -EINVALED; +} + +/** + * send message without waiting time,current suspend task will be resumed + * + * @param id the message id + * @param buffer message info + * @param size the size of buffer + * + * @return EOK on success;EINVALED on failure + * + */ +x_err_t KMsgQueueSend(int32 id, const void *buffer, x_size_t size) +{ + struct MsgQueue *mq = NONE; + + if (id < 0) + return -EINVALED; + + mq = GetMsgQueueById(id); + if (mq != NONE) + return mq->Done->send(mq,buffer,size,0); + else + return -EINVALED; +} +/** + * send message with waiting time,current suspend task will be resumed + * + * @param id the message id + * @param buffer message info + * @param size the size of buffer + * @param timeout waiting time + * + * @return EOK on success;EINVALED on failure + * + */ +x_err_t KMsgQueueSendwait(int32 id, const void *buffer, x_size_t size,int32 timeout) +{ + struct MsgQueue *mq = NONE; + + if (id < 0) + return -EINVALED; + + mq = GetMsgQueueById(id); + if (mq != NONE) + return mq->Done->send(mq,buffer,size,timeout); + else + return -EINVALED; +} diff --git a/Ubiquitous/XiZi/kernel/thread/mutex.c b/Ubiquitous/XiZi/kernel/thread/mutex.c new file mode 100644 index 0000000..88c1177 --- /dev/null +++ b/Ubiquitous/XiZi/kernel/thread/mutex.c @@ -0,0 +1,315 @@ +/* +* Copyright (c) 2020 AIIT XUOS Lab +* XiUOS is licensed under Mulan PSL v2. +* You can use this software according to the terms and conditions of the Mulan PSL v2. +* You may obtain a copy of Mulan PSL v2 at: +* http://license.coscl.org.cn/MulanPSL2 +* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, +* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, +* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. +* See the Mulan PSL v2 for more details. +*/ + +/** +* @file: mutex.c +* @brief: mutex file +* @version: 1.0 +* @author: AIIT XUOS Lab +* @date: 2020/3/15 +* +*/ + +#include + +DECLARE_ID_MANAGER(k_mutex_id_manager, ID_NUM_MAX); +DoubleLinklistType k_mutex_list ={&k_mutex_list, &k_mutex_list}; ///< global mutex manage list + +static int32 _MutexCreate() +{ + int32 id = 0; + x_base lock = 0; + struct Mutex *mutex = NONE; + + mutex = x_malloc(sizeof(struct Mutex)); + if (mutex == NONE) { + return -ENOMEMORY; + } + + memset(mutex, 0x0, sizeof(struct Mutex)); + lock = CriticalAreaLock(); + + id = IdInsertObj(&k_mutex_id_manager, &mutex->id); + if (id < 0) { + CriticalAreaUnLock(lock); + x_free(mutex); + return -ENOMEMORY; + } + + InitDoubleLinkList(&mutex->pend_list); + + mutex->val = 1; + mutex->holder = NONE; + mutex->origin_prio = 0xFF; + mutex->recursive_cnt = 0; + + DoubleLinkListInsertNodeAfter(&k_mutex_list, &mutex->link); + + CriticalAreaUnLock(lock); + + return id; +} + +static void _MutexDelete(struct Mutex *mutex) +{ + x_base lock = 0; + + NULL_PARAM_CHECK(mutex); + + LinklistResumeAll(&mutex->pend_list); + lock = CriticalAreaLock(); + IdRemoveObj(&k_mutex_id_manager, mutex->id.id); + + DoubleLinkListRmNode(&(mutex->link)); + CriticalAreaUnLock(lock); + x_free(mutex); +} + +static int32 _MutexObtain(struct Mutex *mutex, int32 msec) +{ + x_base lock = 0; + int32 wait_time = 0; + struct TaskDescriptor *task = NONE; + + NULL_PARAM_CHECK(mutex); + + task = GetKTaskDescriptor(); + wait_time = CalculteTickFromTimeMs(msec); + lock = CriticalAreaLock(); + + SYS_KDEBUG_LOG(KDBG_IPC, + ("mutex_take: current task %s, mutex value: %d, hold: %d\n", + task->task_base_info.name, mutex->val, mutex->recursive_cnt)); + + task->exstatus = EOK; + + if (mutex->holder == task) { + mutex->recursive_cnt++; + } else { + if (mutex->val > 0) { + mutex->val--; + mutex->holder = task; + mutex->origin_prio = task->task_dync_sched_member.cur_prio; + mutex->recursive_cnt++; + } else { + if (wait_time == 0) { + task->exstatus = -ETIMEOUT; + CriticalAreaUnLock(lock); + return -ETIMEOUT; + } else { + SYS_KDEBUG_LOG(KDBG_IPC, ("mutex_take: suspend task: %s\n", + task->task_base_info.name)); + + if (task->task_dync_sched_member.cur_prio > mutex->holder->task_dync_sched_member.cur_prio) + { + KTaskPrioSet(mutex->holder->id.id, task->task_dync_sched_member.cur_prio); + } + + LinklistSuspend(&(mutex->pend_list), task, LINKLIST_FLAG_PRIO); + + if (wait_time > 0) { + SYS_KDEBUG_LOG(KDBG_IPC, + ("mutex_take: start the timer of task:%s\n", + task->task_base_info.name)); + KTaskSetDelay(task,wait_time); + } + + CriticalAreaUnLock(lock); + + DO_KTASK_ASSIGN; + + if (task->exstatus != EOK) { + return task->exstatus; + } else { + lock = CriticalAreaLock(); + } + } + } + } + + CriticalAreaUnLock(lock); + + return EOK; +} + +static int32 _MutexAbandon(struct Mutex *mutex) +{ + int resched = 0; + x_base lock = 0; + struct TaskDescriptor *task = NONE; + + NULL_PARAM_CHECK(mutex); + + task = GetKTaskDescriptor(); + lock = CriticalAreaLock(); + + SYS_KDEBUG_LOG(KDBG_IPC, + ("mutex_release:current task %s, mutex value: %d, hold: %d\n", + task->task_base_info.name, mutex->val, mutex->recursive_cnt)); + + if (task != mutex->holder) { + task->exstatus = -ERROR; + CriticalAreaUnLock(lock); + return -ERROR; + } + + mutex->recursive_cnt --; + if (mutex->recursive_cnt == 0) { + if (mutex->origin_prio != mutex->holder->task_dync_sched_member.cur_prio) + { + KTaskPrioSet(mutex->holder->id.id, mutex->origin_prio); + } + + if (!IsDoubleLinkListEmpty(&mutex->pend_list)) { + task = SYS_DOUBLE_LINKLIST_ENTRY(mutex->pend_list.node_next, struct TaskDescriptor, task_dync_sched_member.sched_link); + SYS_KDEBUG_LOG(KDBG_IPC, ("mutex_release: resume task: %s\n", + task->task_base_info.name)); + + mutex->holder = task; + mutex->origin_prio = task->task_dync_sched_member.cur_prio; + mutex->recursive_cnt++; + + LinklistResume(&(mutex->pend_list)); + + resched = RET_TRUE; + } else { + mutex->val++; + mutex->holder = NONE; + mutex->origin_prio = 0xff; + } + } + + CriticalAreaUnLock(lock); + + if (resched == RET_TRUE) + DO_KTASK_ASSIGN; + + return EOK; +} + +static MutexDoneType done = { + .MutexCreate = _MutexCreate, + .MutexDelete = _MutexDelete, + .MutexObtain = _MutexObtain, + .MutexAbandon = _MutexAbandon, +}; + +/** + * a mutex will be inited in static way,then this mutex will be inserted to the manage list + * + * @param mutex the mutex descriptor + * @param name mutex name + * @param flag mutex flag + * + * @return EOK on success + * + */ +int32 KMutexCreate() +{ + KDEBUG_NOT_IN_INTERRUPT; + + return done.MutexCreate(); +} + +/** + * a dynamic mutex will be deleted from the manage list + * + * @param mutex mutex descriptor + * + */ +void KMutexDelete(int32 id) +{ + KDEBUG_NOT_IN_INTERRUPT; + + x_base lock = 0; + struct Mutex *mutex = NONE; + struct IdNode *idnode = NONE; + + if (id < 0) + return; + + lock = CriticalAreaLock(); + idnode = IdGetObj(&k_mutex_id_manager, id); + if (idnode == NONE) { + CriticalAreaUnLock(lock); + return; + } + + mutex =CONTAINER_OF(idnode, struct Mutex, id); + CriticalAreaUnLock(lock); + + done.MutexDelete(mutex); +} + +/** + * a mutex will be taken when mutex is available + * + * @param mutex mutex descriptor + * @param msec the time needed waiting + * + * @return EOK on success;ERROR on failure + * + */ +int32 KMutexObtain(int32 id, int32 msec) +{ + KDEBUG_IN_KTASK_CONTEXT; + + x_base lock = 0; + struct Mutex *mutex = NONE; + struct IdNode *idnode = NONE; + + if (id < 0) + return -ERROR; + + lock = CriticalAreaLock(); + idnode = IdGetObj(&k_mutex_id_manager, id); + if (idnode == NONE){ + CriticalAreaUnLock(lock); + return -ERROR; + } + + + mutex =CONTAINER_OF(idnode, struct Mutex, id); + CriticalAreaUnLock(lock); + + return done.MutexObtain(mutex, msec); +} + +/** + * release the mutex and resume corresponding suspended task + * + * @param mutex mutex descriptor + * + * @return EOK on success;ERROR on failure + */ +int32 KMutexAbandon(int32 id) +{ + KDEBUG_IN_KTASK_CONTEXT; + + x_base lock = 0; + struct Mutex *mutex = NONE; + struct IdNode *idnode = NONE; + + if (id < 0) + return -ERROR; + + lock = CriticalAreaLock(); + idnode = IdGetObj(&k_mutex_id_manager, id); + if (idnode == NONE) { + CriticalAreaUnLock(lock); + return -ERROR; + } + + mutex = CONTAINER_OF(idnode, struct Mutex, id); + CriticalAreaUnLock(lock); + return done.MutexAbandon(mutex); +} diff --git a/Ubiquitous/XiZi/kernel/thread/queue_manager.c b/Ubiquitous/XiZi/kernel/thread/queue_manager.c new file mode 100644 index 0000000..5a46db1 --- /dev/null +++ b/Ubiquitous/XiZi/kernel/thread/queue_manager.c @@ -0,0 +1,56 @@ +/* +* Copyright (c) 2020 AIIT XUOS Lab +* XiUOS is licensed under Mulan PSL v2. +* You can use this software according to the terms and conditions of the Mulan PSL v2. +* You may obtain a copy of Mulan PSL v2 at: +* http://license.coscl.org.cn/MulanPSL2 +* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, +* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, +* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. +* See the Mulan PSL v2 for more details. +*/ + +/** +* @file: queue_manager.c +* @brief: Unified management of queue +* @version: 1.0 +* @author: AIIT XUOS Lab +* @date: 2020/3/15 +* +*/ + +#include +#include +#include +#include + +#include + +void* g_queue_done[QUEUE_MAX]; + +void QueuemanagerDoneRegister() +{ + DataQueueDoneType* pdata_queue_done = (DataQueueDoneType*)x_malloc(sizeof(DataQueueDoneType)); + pdata_queue_done->InitDataqueue = InitDataqueue; + pdata_queue_done->PushDataqueue = PushDataqueue; + pdata_queue_done->PopDataqueue = PopDataqueue; + pdata_queue_done->DataqueuePeak = DataqueuePeak; + pdata_queue_done->DeInitDataqueue = DeInitDataqueue; + + WorkQueueDoneType* pwork_queue_done = (WorkQueueDoneType*)x_malloc(sizeof(WorkQueueDoneType)); + pwork_queue_done->CreateWorkQueue = CreateWorkQueue; + pwork_queue_done->WorkInit = WorkInit; + pwork_queue_done->WorkSubmit = WorkSubmit; + pwork_queue_done->WorkSubmit_immediate = WorkSubmit_immediate; + + WaitQueueDoneType* pwait_queue_done = (WaitQueueDoneType*)x_malloc(sizeof(WaitQueueDoneType)); + pwait_queue_done->InitWqueue = InitWqueue; + pwait_queue_done->WqueueAdd = WqueueAdd; + pwait_queue_done->WqueueRemove = WqueueRemove; + pwait_queue_done->WqueueWait = WqueueWait; + pwait_queue_done->WakeupWqueue = WakeupWqueue; + + g_queue_done[DATA_QUEUE] = pdata_queue_done; + g_queue_done[WORK_QUEUE] = pwork_queue_done; + g_queue_done[WAIT_QUEUE] = pwait_queue_done; +} \ No newline at end of file diff --git a/Ubiquitous/XiZi/kernel/thread/semaphore.c b/Ubiquitous/XiZi/kernel/thread/semaphore.c new file mode 100644 index 0000000..663e235 --- /dev/null +++ b/Ubiquitous/XiZi/kernel/thread/semaphore.c @@ -0,0 +1,327 @@ +/* + * Copyright (c) 2020 AIIT XUOS Lab + * XiUOS is licensed under Mulan PSL v2. + * You can use this software according to the terms and conditions of the Mulan PSL v2. + * You may obtain a copy of Mulan PSL v2 at: + * http://license.coscl.org.cn/MulanPSL2 + * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, + * EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, + * MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. + * See the Mulan PSL v2 for more details. + */ + +/** +* @file: semaphore.c +* @brief: semaphore file +* @version: 1.0 +* @author: AIIT XUOS Lab +* @date: 2020/3/15 +* +*/ + +#include + +#ifdef KDEBUG_NOT_IN_INTERRUPT +#undef KDEBUG_NOT_IN_INTERRUPT +#endif + +#define KDEBUG_NOT_IN_INTERRUPT + +DECLARE_ID_MANAGER(k_sem_id_manager, ID_NUM_MAX); +DoubleLinklistType k_sem_list = {&k_sem_list, &k_sem_list}; + +static int32 _SemaphoreCreate(uint16 val) +{ + int32 id = 0; + x_base lock = 0; + struct Semaphore *sem = NONE; + + sem = (struct Semaphore *)x_malloc(sizeof(struct Semaphore)); + if (sem == NONE) + return -ENOMEMORY; + + memset(sem, 0, sizeof(struct Semaphore)); + lock = CriticalAreaLock(); + id = IdInsertObj(&k_sem_id_manager, &sem->id); + if (id < 0) { + x_free(sem); + CriticalAreaUnLock(lock); + return -ENOMEMORY; + } + + sem->value = val; + InitDoubleLinkList(&sem->pend_list); + + + DoubleLinkListInsertNodeAfter(&k_sem_list, &sem->link); + CriticalAreaUnLock(lock); + + SYS_KDEBUG_LOG(KDBG_IPC, ("created semaphore: id %d, value %d\n", id, (int)val)); + + return id; +} + +static void _SemaphoreDelete(struct Semaphore *sem) +{ + int resched = 0; + x_base lock = 0; + + NULL_PARAM_CHECK(sem); + + SYS_KDEBUG_LOG(KDBG_IPC, ("deleted semaphore: id %d\n", (int)sem->id.id)); + lock = CriticalAreaLock(); + if (!IsDoubleLinkListEmpty(&sem->pend_list)) { + resched = 1; + LinklistResumeAll(&sem->pend_list); + } + + IdRemoveObj(&k_sem_id_manager, sem->id.id); + DoubleLinkListRmNode(&sem->link); + CriticalAreaUnLock(lock); + + x_free(sem); + + if (resched){ + DO_KTASK_ASSIGN; + } + +} + +static int32 _SemaphoreObtain(struct Semaphore *sem, int32 msec) +{ + int lock = 0; + int32 wait_time = 0; + struct TaskDescriptor *task = NONE; + + NULL_PARAM_CHECK(sem); + + wait_time = CalculteTickFromTimeMs(msec); + lock = CriticalAreaLock(); + + SYS_KDEBUG_LOG(KDBG_IPC, ("obtain semaphore: id %d, value %d, by task %s\n", + (int)sem->id.id, (int)sem->value, GetKTaskDescriptor()->task_base_info.name)); + + if (sem->value > 0) { + sem->value--; + CriticalAreaUnLock(lock); + return EOK; + } + + if (wait_time == 0) { + CriticalAreaUnLock(lock); + return -ETIMEOUT; + } + + task = GetKTaskDescriptor(); + task->exstatus = EOK; + + SYS_KDEBUG_LOG(KDBG_IPC, ("obtain semaphore: suspending task %s\n", + GetKTaskDescriptor()->task_base_info.name)); + + LinklistSuspend(&sem->pend_list, task, LINKLIST_FLAG_PRIO); + + if (wait_time > 0) { + KTaskSetDelay(task, wait_time); + } + + CriticalAreaUnLock(lock); + + + DO_KTASK_ASSIGN; + + return task->exstatus; +} + +static int32 _SemaphoreAbandon(struct Semaphore *sem) +{ + int lock = 0; + int resched = 0; + + NULL_PARAM_CHECK(sem); + + lock = CriticalAreaLock(); + + SYS_KDEBUG_LOG(KDBG_IPC, ("abandon semaphore: id %d, value %d, by task %s\n", + (int)sem->id.id, (int)sem->value, GetKTaskDescriptor()->task_base_info.name)); + + if (!IsDoubleLinkListEmpty(&sem->pend_list)) { + resched = 1; + LinklistResume(&sem->pend_list); + } else { + sem->value++; + } + + CriticalAreaUnLock(lock); + + if (resched){ + DO_KTASK_ASSIGN; + } + + return EOK; +} + +static int32 _SemaphoreSetValue(struct Semaphore *sem, uint16 val) +{ + int lock = 0; + int resched = 0; + + NULL_PARAM_CHECK(sem); + + lock = CriticalAreaLock(); + + SYS_KDEBUG_LOG(KDBG_IPC, ("set semaphore value: id %d, old value %d, new value %d, by task %s\n", + (int)sem->id.id, (int)sem->value, (int)val, GetKTaskDescriptor()->task_base_info.name)); + + if (sem->value == val) { + CriticalAreaUnLock(lock); + return EOK; + } + + if (!IsDoubleLinkListEmpty(&sem->pend_list)) { + resched = 1; + LinklistResumeAll(&sem->pend_list); + } + sem->value = val; + + CriticalAreaUnLock(lock); + + if (resched) + DO_KTASK_ASSIGN; + + return EOK; +} + +static SemaphoreDoneType done = { + .SemaphoreCreate = _SemaphoreCreate, + .SemaphoreDelete = _SemaphoreDelete, + .SemaphoreObtain = _SemaphoreObtain, + .SemaphoreAbandon = _SemaphoreAbandon, + .SemaphoreSetValue = _SemaphoreSetValue, +}; + +/** + * Create a new semaphore with specified initial value. + * + * @param val initial value + * @return id of the semaphore + */ +int32 KSemaphoreCreate(uint16 val) +{ + KDEBUG_NOT_IN_INTERRUPT; + + return done.SemaphoreCreate(val); +} + +/** + * Delete a semaphore and wakeup all pending tasks on it. + * + * @param id id of the semaphore to be deleted + */ +void KSemaphoreDelete(int32 id) +{ + x_base lock = 0; + struct Semaphore *sem = NONE; + struct IdNode *idnode = NONE; + + KDEBUG_NOT_IN_INTERRUPT; + + if (id < 0) + return; + lock = CriticalAreaLock(); + idnode = IdGetObj(&k_sem_id_manager, id); + if (idnode == NONE){ + CriticalAreaUnLock(lock); + return; + } + CriticalAreaUnLock(lock); + + sem = CONTAINER_OF(idnode, struct Semaphore, id); + done.SemaphoreDelete(sem); +} + +/** + * Obtain a semaphore when its value is greater than 0; pend on it otherwise. + * + * @param id id of the semaphore to be obtained + * @param msec wait time in millisecond + * @return EOK on success, error code on failure + */ +int32 KSemaphoreObtain(int32 id, int32 msec) +{ + KDEBUG_NOT_IN_INTERRUPT; + + x_base lock = 0; + struct Semaphore *sem = NONE; + struct IdNode *idnode = NONE; + + if (id < 0) + return -ERROR; + lock = CriticalAreaLock(); + idnode = IdGetObj(&k_sem_id_manager, id); + if (idnode == NONE){ + CriticalAreaUnLock(lock); + return -ERROR; + } + + sem =CONTAINER_OF(idnode, struct Semaphore, id); + CriticalAreaUnLock(lock); + return done.SemaphoreObtain(sem, msec); +} + +/** + * Abandon a semaphore and wakeup a pending task if any. + * + * @param id id of the semaphore to be abandoned + * @return EOK on success, error code on failure + */ +int32 KSemaphoreAbandon(int32 id) +{ + KDEBUG_NOT_IN_INTERRUPT; + + x_base lock = 0; + struct Semaphore *sem = NONE; + struct IdNode *idnode = NONE; + + if (id < 0) + return -ERROR; + lock = CriticalAreaLock(); + idnode = IdGetObj(&k_sem_id_manager, id); + if (idnode == NONE) { + CriticalAreaUnLock(lock); + return -ERROR; + } + + sem =CONTAINER_OF(idnode, struct Semaphore, id); + CriticalAreaUnLock(lock); + + return done.SemaphoreAbandon(sem); +} + +/** + * Set the value of a semaphore, wakeup all pending tasks if new value is positive. + * + * @param id id of the semaphore for which to set value + * @param val new value + * @return EOK on success, error code on failure + */ +int32 KSemaphoreSetValue(int32 id, uint16 val) +{ + KDEBUG_NOT_IN_INTERRUPT; + + x_base lock = 0; + struct Semaphore *sem = NONE; + struct IdNode *idnode = NONE; + + if (id < 0) + return -ERROR; + lock = CriticalAreaLock(); + idnode = IdGetObj(&k_sem_id_manager, id); + if (idnode == NONE) { + CriticalAreaUnLock(lock); + return -ERROR; + } + + sem = CONTAINER_OF(idnode, struct Semaphore, id); + CriticalAreaUnLock(lock); + return done.SemaphoreSetValue(sem, val); +} diff --git a/Ubiquitous/XiZi/kernel/thread/single_link.c b/Ubiquitous/XiZi/kernel/thread/single_link.c new file mode 100644 index 0000000..1798138 --- /dev/null +++ b/Ubiquitous/XiZi/kernel/thread/single_link.c @@ -0,0 +1,142 @@ +/* +* Copyright (c) 2020 AIIT XUOS Lab +* XiUOS is licensed under Mulan PSL v2. +* You can use this software according to the terms and conditions of the Mulan PSL v2. +* You may obtain a copy of Mulan PSL v2 at: +* http://license.coscl.org.cn/MulanPSL2 +* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, +* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, +* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. +* See the Mulan PSL v2 for more details. +*/ + +/** +* @file: single_link.c +* @brief: functions definition of single linklist +* @version: 1.0 +* @author: AIIT XUOS Lab +* @date: 2020/3/15 +* +*/ + +#include + +/** + * This function will init a linklist. + * + * @param linklist_head linklist node + */ +void InitSingleLinkList(SysSingleLinklistType *linklist) +{ + linklist->node_next = NONE; +} + +void AppendSingleLinkList(SysSingleLinklistType *linklist, SysSingleLinklistType *linklist_node) +{ + struct SingleLinklistNode *node; + + node = linklist; + while (node->node_next) node = node->node_next; + + node->node_next = linklist_node; + linklist_node->node_next = NONE; +} +/** + * This function will insert a node into list after the node. + * + * @param linklist linklist node + * @param linklist_node the node needed to inserted + */ + +void SingleLinkListNodeInsert(SysSingleLinklistType *linklist, SysSingleLinklistType *linklist_node) +{ + linklist_node->node_next = linklist->node_next; + linklist->node_next = linklist_node; +} + +/** + * This function will get length of the list. + * + * @param linklist list head + * @return length + */ + +unsigned int SingleLinkListGetLen(const SysSingleLinklistType *linklist) +{ + unsigned int length = 0; + const SysSingleLinklistType *tmp_list = linklist->node_next; + while (tmp_list != NONE) + { + tmp_list = tmp_list->node_next; + length ++; + } + + return length; +} + +/** + * This function will remove a node from the list. + * + * @param linklist_node the node needed to removed + */ + +SysSingleLinklistType *SingleLinkListRmNode(SysSingleLinklistType *linklist, SysSingleLinklistType *linklist_node) +{ + struct SingleLinklistNode *node = linklist; + while (node->node_next && node->node_next != linklist_node) node = node->node_next; + + if (node->node_next != (SysSingleLinklistType *)0){ + node->node_next = node->node_next->node_next; + } + + return linklist; +} + +/** + * This function will get the head of the list. + * + * @param linklist list head + * @return list head + */ +SysSingleLinklistType *SingleLinkListGetFirstNode(SysSingleLinklistType *linklist) +{ + return linklist->node_next; +} + +/** + * This function will get the tail node of the list. + * + * @param linklist list head + * @return list taile node + */ +SysSingleLinklistType *SingleLinkListGetTailNode(SysSingleLinklistType *linklist) +{ + while (linklist->node_next) linklist = linklist->node_next; + + return linklist; +} + +/** + * This function will get the next node of the list head. + * + * @param linklist list head + * @param linklist_node list head + * @return next node of the list head + */ + +SysSingleLinklistType *SingleLinkListGetNextNode(SysSingleLinklistType *linklist_node) +{ + return linklist_node->node_next; +} + +/** + * This function will judge the list is empty. + * + * @param linklist the list head + * @return true + */ + +int IsSingleLinkListEmpty(SysSingleLinklistType *linklist) +{ + return linklist->node_next == NONE; +} \ No newline at end of file diff --git a/Ubiquitous/XiZi/kernel/thread/smp_assign.c b/Ubiquitous/XiZi/kernel/thread/smp_assign.c new file mode 100644 index 0000000..8a063f4 --- /dev/null +++ b/Ubiquitous/XiZi/kernel/thread/smp_assign.c @@ -0,0 +1,487 @@ +/* +* Copyright (c) 2020 AIIT XUOS Lab +* XiUOS is licensed under Mulan PSL v2. +* You can use this software according to the terms and conditions of the Mulan PSL v2. +* You may obtain a copy of Mulan PSL v2 at: +* http://license.coscl.org.cn/MulanPSL2 +* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, +* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, +* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. +* See the Mulan PSL v2 for more details. +*/ + +/** +* @file: smp_assign.c +* @brief: system scheduler of multiple cpu +* @version: 1.0 +* @author: AIIT XUOS Lab +* @date: 2020/3/15 +* +*/ + +#include +#include +#include +#include +#include +#include + +struct Assign Assign; +HwSpinlock AssignSpinLock; + +static struct PriorityReadyVectorDone ready_vector_done = +{ + OsAssignReadyVectorInit, + KTaskInsertToReadyVector, + KTaskOsAssignRemoveKTask, +}; + +static inline x_ubase SmpGetReadyVectorHighestPrio(void) +{ + uint8 coreid = GetCpuId(); + + return ((Assign.os_assign_read_vector.highest_prio > Assign.smp_os_assign_ready_rector[coreid].highest_prio) ? Assign.os_assign_read_vector.highest_prio : Assign.smp_os_assign_ready_rector[coreid].highest_prio); +} + +/* + * get target highest priority task in ready queue + */ +static inline struct TaskDescriptor* SmpAssignTargetTaskSelect(void) +{ + + uint8 coreid = GetCpuId(); + + if (Assign.os_assign_read_vector.highest_prio > Assign.smp_os_assign_ready_rector[coreid].highest_prio) + { + return ChooseTaskWithHighestPrio(&Assign.os_assign_read_vector); + } + else + { + return ChooseTaskWithHighestPrio(&Assign.smp_os_assign_ready_rector[coreid]); + } +} + +static inline void SmpOsAssignSwtichToNewTask(struct TaskDescriptor* old_task, struct TaskDescriptor* new_task) +{ + NULL_PARAM_CHECK(old_task); + NULL_PARAM_CHECK(new_task); + + Assign.ready_vector_done->remove(new_task); + KTaskStatSetAsRunning(new_task); + +#ifdef USING_OVERFLOW_CHECK + _KTaskOsAssignStackCheck(new_task); +#endif + + SwitchKtaskContext((x_ubase)&old_task->stack_point, (x_ubase)&new_task->stack_point, new_task); +} + +static inline void SmpSwitchToFirstRunningTask(struct TaskDescriptor* task) +{ + NULL_PARAM_CHECK(task); + + Assign.ready_vector_done->remove(task); + KTaskStatSetAsRunning(task); + + SwitchKtaskContextTo((x_ubase)&task->stack_point, task); + +} + +static inline void SetSystemRunningTask(struct TaskDescriptor* task) +{ + NULL_PARAM_CHECK(task); + + task->task_smp_info.runing_coreid = GetCpuId(); +} + +static void SmpOsAssignInit(void) +{ + int coreid = 0; + while(coreid < CPU_NUMBERS) { + Assign.ready_vector_done->init(&Assign.smp_os_assign_ready_rector[coreid]); + Assign.smp_os_running_task[coreid] = NONE; + +#ifdef ARCH_SMP + isrManager.isr_switch_trigger_flag[coreid] = 0; +#else + isrManager.isr_switch_trigger_flag = 0; +#endif + Assign.current_priority[coreid] = KTASK_PRIORITY_MAX - 1; + Assign.assign_lock[coreid] = 0; + coreid++; + } +} + +struct smp_assign_done smp_assign_done = +{ + SmpGetReadyVectorHighestPrio, + SmpAssignTargetTaskSelect, + SmpOsAssignSwtichToNewTask, + SmpSwitchToFirstRunningTask, + SetSystemRunningTask, + SmpOsAssignInit, +}; + + + +/** + * task schedule function.getting the highest priority task then switching to it + */ +void KTaskOsAssign(void) +{ + x_base lock = 0; + int coreid = 0; + x_ubase highest_prio = 0; + struct TaskDescriptor *new_task = NONE; + struct TaskDescriptor *runningtask = NONE; + + coreid = GetCpuId(); + if (isrManager.done->isInIsr()) { + isrManager.done->setSwitchTrigerFlag(); + return; + } + + if(Assign.assign_lock[coreid] >= 1) { + return; + } + + runningtask = Assign.smp_os_running_task[coreid]; + + /* if the bitmap is empty then do not switch */ + if((RET_TRUE == JudgeAssignReadyBitmapIsEmpty(&Assign.os_assign_read_vector)) && + (RET_TRUE == JudgeAssignReadyBitmapIsEmpty(&Assign.smp_os_assign_ready_rector[coreid]))) { + return; + } + + highest_prio = Assign.smp_assign_done->GetHighest(); + new_task = Assign.smp_assign_done->select(); + + + if(RET_TRUE != JudgeKTaskStatIsRunning(runningtask)) { + CHECK(NONE != new_task); + goto SWITCH; + } + /* if the running task’ priority is the highest and this task is not be yield then do not switch */ + if(highest_prio < runningtask->task_dync_sched_member.cur_prio) { + return; + } else { + Assign.ready_vector_done->insert(runningtask); + } +SWITCH: + + new_task->task_smp_info.runing_coreid = coreid; + Assign.current_priority[coreid] = (uint8)highest_prio; + + HOOK(hook.assign.hook_Assign,(runningtask, new_task)); + + SYS_KDEBUG_LOG(KDBG_SCHED, + ("[%d]switch to priority#%d " + "task:%.*s(sp:0x%08x), " + "from task:%.*s(sp: 0x%08x)\n", + isrManager.done->getCounter(), highest_prio, + NAME_NUM_MAX, new_task->task_base_info.name, new_task->stack_point, + NAME_NUM_MAX, runningtask->task_base_info.name, runningtask->stack_point)); + + Assign.smp_assign_done->SwitchToNew(runningtask,new_task); +} + +/** + * task switch in IRQ context. + */ +void KTaskOsAssignDoIrqSwitch(void *context) +{ + int coreid = 0; + x_base lock = 0; + x_ubase highest_priority = 0; + struct TaskDescriptor *new_task = NONE; + struct TaskDescriptor *runningtask = NONE; + + coreid = GetCpuId(); + if ( isrManager.done->getSwitchTrigerFlag() == 0) { + return; + } + + if (Assign.assign_lock[coreid] >= 1 || isrManager.done->getCounter() != 0) { + return; + } + + + isrManager.done->clearSwitchTrigerFlag(); + + runningtask = Assign.smp_os_running_task[coreid]; + + if((RET_TRUE == JudgeAssignReadyBitmapIsEmpty(&Assign.os_assign_read_vector)) && + (RET_TRUE == JudgeAssignReadyBitmapIsEmpty(&Assign.smp_os_assign_ready_rector[coreid]))) { + return; + } + + highest_priority = Assign.smp_assign_done->GetHighest(); + new_task = Assign.smp_assign_done->select(); + + if (RET_TRUE == JudgeKTaskStatIsRunning(runningtask)) { + if (runningtask->task_dync_sched_member.cur_prio > highest_priority) { + new_task = runningtask; + } else { + Assign.ready_vector_done->insert(runningtask); + } + } + + new_task->task_smp_info.runing_coreid = coreid; + if (new_task != runningtask) { + Assign.current_priority[coreid] = (uint8)highest_priority; + HOOK(hook.assign.hook_Assign, (runningtask, new_task)); + Assign.ready_vector_done->remove(new_task); + KTaskStatSetAsRunning(new_task); + +#ifdef KERNEL_STACK_OVERFLOW_CHECK + _KTaskOsAssignStackCheck(new_task); +#endif + SYS_KDEBUG_LOG(KDBG_SCHED, ("switch in interrupt\n")); + + + HwInterruptcontextSwitch( (x_ubase)&runningtask->stack_point, + (x_ubase)&new_task->stack_point, new_task, context); + } +} +void KTaskOsAssignAfterIrq(void *context) +{ + x_base lock = 0; + lock = DISABLE_INTERRUPT(); + HwLockSpinlock(&AssignSpinLock); + KTaskOsAssignDoIrqSwitch(context); + HwUnlockSpinlock(&AssignSpinLock); + ENABLE_INTERRUPT(lock); +} + +static void UncombineInsert(struct TaskDescriptor *task) +{ + uint32 cpu_mask = 0; + + NULL_PARAM_CHECK(task); + +#if KTASK_PRIORITY_MAX > 32 + MERGE_FLAG(&Assign.os_assign_read_vector.ready_vector[task->task_dync_sched_member.bitmap_offset], task->task_dync_sched_member.bitmap_row); +#endif + MERGE_FLAG(&Assign.os_assign_read_vector.priority_ready_group, task->task_dync_sched_member.bitmap_column); + AssignPolicyInsert(task, &Assign.os_assign_read_vector); + cpu_mask = CPU_MASK ^ (1 << GetCpuId()); + HwSendIpi(ASSIGN_IPI, cpu_mask); +} + +static void ComnbineInsert(struct TaskDescriptor *task, int coreid) +{ + NULL_PARAM_CHECK(task); + +#if KTASK_PRIORITY_MAX > 32 + MERGE_FLAG(&Assign.smp_os_assign_ready_rector[coreid].ready_vector[task->task_dync_sched_member.bitmap_offset], task->task_dync_sched_member.bitmap_row); +#endif + MERGE_FLAG(&Assign.smp_os_assign_ready_rector[coreid].priority_ready_group, task->task_dync_sched_member.bitmap_column); + AssignPolicyInsert(task, &Assign.smp_os_assign_ready_rector[coreid]); + if (coreid != task->task_smp_info.combined_coreid) + { + uint32 cpu_mask; + cpu_mask = 1 << task->task_smp_info.combined_coreid; + HwSendIpi(ASSIGN_IPI, cpu_mask); + } +} + +/* + * insert a ready task to system ready table with READY state and remove it from suspend list + * + * @param task the task descriptor + * + */ +void KTaskInsertToReadyVector(struct TaskDescriptor *task) +{ + int coreid = 0; + + NULL_PARAM_CHECK(task); + + KTaskStatSetAsReady(task); + + coreid = task->task_smp_info.combined_coreid; + + switch (coreid) + { + case UNCOMBINE_CPU_CORE: + UncombineInsert(task); + break; + + default: + ComnbineInsert(task, coreid); + break; + } + + SYS_KDEBUG_LOG(KDBG_SCHED, ("insert task[%.*s], the priority: %d\n", + NAME_NUM_MAX, task->task_base_info.name, task->task_dync_sched_member.cur_prio)); + +} + +static void UncombineRemove(struct TaskDescriptor *task) +{ + register x_ubase number = 0; + register x_ubase highest_priority = 0; + + NULL_PARAM_CHECK(task); + + if (IsDoubleLinkListEmpty(&(Assign.os_assign_read_vector.priority_ready_vector[task->task_dync_sched_member.cur_prio]))) { +#if KTASK_PRIORITY_MAX > 32 + + CLEAR_FLAG(&Assign.os_assign_read_vector.ready_vector[task->task_dync_sched_member.bitmap_offset], task->task_dync_sched_member.bitmap_row); + if (Assign.os_assign_read_vector.ready_vector[task->task_dync_sched_member.bitmap_offset] == 0) { + CLEAR_FLAG(&Assign.os_assign_read_vector.priority_ready_group, task->task_dync_sched_member.bitmap_column); + } + number = PrioCaculate(Assign.os_assign_read_vector.priority_ready_group); + highest_priority = (number * 8) + PrioCaculate(Assign.os_assign_read_vector.ready_vector[number]); +#else + + + CLEAR_FLAG(&Assign.os_assign_read_vector.priority_ready_group, task->task_dync_sched_member.bitmap_column); + highest_priority = PrioCaculate(Assign.os_assign_read_vector.priority_ready_group); +#endif + Assign.os_assign_read_vector.highest_prio = highest_priority; + } +} + +static void CombineRemove(struct TaskDescriptor *task) +{ + register x_ubase number = 0; + register x_ubase highest_prio_on_core = 0; + uint8 combined_coreid = task->task_smp_info.combined_coreid; + + NULL_PARAM_CHECK(task); + + if (IsDoubleLinkListEmpty(&(Assign.smp_os_assign_ready_rector[combined_coreid].priority_ready_vector[task->task_dync_sched_member.cur_prio]))) { +#if KTASK_PRIORITY_MAX > 32 + CLEAR_FLAG(&Assign.smp_os_assign_ready_rector[combined_coreid].ready_vector[task->task_dync_sched_member.bitmap_offset], task->task_dync_sched_member.bitmap_row); + if (Assign.os_assign_read_vector.ready_vector[task->task_dync_sched_member.bitmap_offset] == 0) { + CLEAR_FLAG(&Assign.smp_os_assign_ready_rector[combined_coreid].priority_ready_group, task->task_dync_sched_member.bitmap_column); + } + number = PrioCaculate(Assign.smp_os_assign_ready_rector[combined_coreid].priority_ready_group); + highest_prio_on_core = (number * 8) + PrioCaculate(Assign.smp_os_assign_ready_rector[combined_coreid].ready_vector[number]); +#else + CLEAR_FLAG(&Assign.smp_os_assign_ready_rector[combined_coreid].priority_ready_group, task->task_dync_sched_member.bitmap_column); + highest_prio_on_core = PrioCaculate(Assign.smp_os_assign_ready_rector[combined_coreid].priority_ready_group); +#endif + Assign.smp_os_assign_ready_rector[combined_coreid].highest_prio = highest_prio_on_core; + } +} + +/* + * a task will be removed from ready table. + * + * @param task task descriptor + * + */ +void KTaskOsAssignRemoveKTask(struct TaskDescriptor *task) +{ + + NULL_PARAM_CHECK(task); + + SYS_KDEBUG_LOG(KDBG_SCHED, ("remove task[%.*s], the priority: %d\n", + NAME_NUM_MAX, task->task_base_info.name, + task->task_dync_sched_member.cur_prio)); + + DoubleLinkListRmNode(&(task->task_dync_sched_member.sched_link)); + switch (task->task_smp_info.combined_coreid) + { + case UNCOMBINE_CPU_CORE: + UncombineRemove(task); + break; + + default: + CombineRemove(task); + break; + } +} + +x_err_t YieldOsAssign(void) +{ + x_base lock = 0; + int coreid = 0; + x_ubase highest_prio = 0; + struct TaskDescriptor *new_task = NONE; + struct TaskDescriptor *runningtask = NONE; + + lock = DISABLE_INTERRUPT(); + HwLockSpinlock(&AssignSpinLock); + coreid = GetCpuId(); + runningtask = Assign.smp_os_running_task[coreid]; + + if (isrManager.done->getCounter()) { + HwUnlockSpinlock(&AssignSpinLock); + ENABLE_INTERRUPT(lock); + return -ERROR; + } + + if(Assign.assign_lock[coreid] >= 1) { + HwUnlockSpinlock(&AssignSpinLock); + ENABLE_INTERRUPT(lock); + return -ERROR; + } + /* if the bitmap is empty then do not switch */ + if((RET_TRUE == JudgeAssignReadyBitmapIsEmpty(&Assign.os_assign_read_vector)) && + (RET_TRUE == JudgeAssignReadyBitmapIsEmpty(&Assign.smp_os_assign_ready_rector[coreid]))) { + HwUnlockSpinlock(&AssignSpinLock); + ENABLE_INTERRUPT(lock); + return -ERROR; + } + + highest_prio = Assign.smp_assign_done->GetHighest(); + new_task = Assign.smp_assign_done->select(); + + if(RET_TRUE != JudgeKTaskStatIsRunning(runningtask)) { + CHECK(NONE != new_task); + } else { + Assign.ready_vector_done->insert(runningtask); + } + + new_task->task_smp_info.runing_coreid = coreid; + Assign.current_priority[coreid] = (uint8)highest_prio; + + HOOK(hook.assign.hook_Assign,(runningtask, new_task)); + + SYS_KDEBUG_LOG(KDBG_SCHED, + ("[%d]switch to priority#%d " + "task:%.*s(sp:0x%08x), " + "from task:%.*s(sp: 0x%08x)\n", + isrManager.done->getCounter(), highest_prio, + NAME_NUM_MAX, new_task->task_base_info.name, new_task->stack_point, + NAME_NUM_MAX, runningtask->task_base_info.name, runningtask->stack_point)); + + Assign.smp_assign_done->SwitchToNew(runningtask,new_task); + + ENABLE_INTERRUPT(lock); + + return EOK; +} + +/** + * + * OsAssign startup function + * . + */ +void StartupOsAssign(void) +{ + struct TaskDescriptor *FirstRunningTask = NONE; + + FirstRunningTask = Assign.smp_assign_done->select(); + Assign.smp_assign_done->SetSystemTask(FirstRunningTask); + Assign.smp_assign_done->SwitchToFirst(FirstRunningTask); +} + +/** + * + * system OsAssign init function + */ +void SysInitOsAssign(void) +{ + SYS_KDEBUG_LOG(KDBG_SCHED, ("start Os Assign: max priority 0x%02x\n", + KTASK_PRIORITY_MAX)); + + Assign.ready_vector_done = &ready_vector_done; + Assign.smp_assign_done = &smp_assign_done; + Assign.ready_vector_done->init(&Assign.os_assign_read_vector); + Assign.smp_assign_done->SmpInit(); + +} \ No newline at end of file diff --git a/Ubiquitous/XiZi/kernel/thread/softtimer.c b/Ubiquitous/XiZi/kernel/thread/softtimer.c new file mode 100644 index 0000000..244c49c --- /dev/null +++ b/Ubiquitous/XiZi/kernel/thread/softtimer.c @@ -0,0 +1,357 @@ +/* +* Copyright (c) 2020 AIIT XUOS Lab +* XiUOS is licensed under Mulan PSL v2. +* You can use this software according to the terms and conditions of the Mulan PSL v2. +* You may obtain a copy of Mulan PSL v2 at: +* http://license.coscl.org.cn/MulanPSL2 +* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, +* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, +* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. +* See the Mulan PSL v2 for more details. +*/ + +/** +* @file: softtimer.c +* @brief: softtimer file +* @version: 1.0 +* @author: AIIT XUOS Lab +* @date: 2020/3/15 +* +*/ + +#include + +DoubleLinklistType xiaoshan_timer_sort_head = {&xiaoshan_timer_sort_head, &xiaoshan_timer_sort_head}; +DoubleLinklistType k_timer_list = {&k_timer_list, &k_timer_list}; + +DECLARE_ID_MANAGER(k_softtimer_id_manager, ID_NUM_MAX); +extern queue *sys_workq; + +void _Init(struct Timer *timer, + const char *name, + void (*timeout)(void *parameter), + void *parameter, + x_ticks_t time, + uint8 trigger_mode) +{ + x_base lock = 0; + + NULL_PARAM_CHECK(timer); + + strncpy(timer->name, name, NAME_NUM_MAX); + + // insert to link + lock = CriticalAreaLock(); + DoubleLinkListInsertNodeAfter(&(k_timer_list), &(timer->link)); + CriticalAreaUnLock(lock); + + timer->trigger_mode = trigger_mode; + timer->active_status = TIMER_ACTIVE_FALSE; + timer->func_callback = timeout; + timer->param = parameter; + timer->deadline_timeslice = 0; + timer->origin_timeslice = time; + timer->prio = GetKTaskDescriptor()->task_base_info.origin_prio; +} + +x_err_t _Delete(TimerType timer) +{ + x_base lock = 0; + + NULL_PARAM_CHECK(timer); + + lock = CriticalAreaLock(); + + DoubleLinkListRmNode(&(timer->sortlist)); + DoubleLinkListRmNode(&(timer->link)); + + CriticalAreaUnLock(lock); + KERNEL_FREE(timer); + timer = NONE; + + return EOK; +} + +x_err_t _StartRun(TimerType timer) +{ + NULL_PARAM_CHECK(timer); + + x_base lock = CriticalAreaLock(); + timer->active_status = TIMER_ACTIVE_FALSE; + + CHECK(timer->origin_timeslice < TICK_SIZE_MAX / 2); + timer->deadline_timeslice = CurrentTicksGain() + timer->origin_timeslice; + timer->active_status = TIMER_ACTIVE_TRUE; + + DoubleLinklistType *pLink = NONE; + TimerType pNode = NONE; + + DOUBLE_LINKLIST_FOR_EACH(pLink, &xiaoshan_timer_sort_head) { + pNode = CONTAINER_OF(pLink, struct Timer, sortlist); + if (timer->deadline_timeslice < pNode->deadline_timeslice) { + DoubleLinkListInsertNodeBefore(pLink, &timer->sortlist); + + break; + } + } + if (pLink == &xiaoshan_timer_sort_head) { + DoubleLinkListInsertNodeBefore(&xiaoshan_timer_sort_head, &timer->sortlist); + } + + CriticalAreaUnLock(lock); + + return EOK; +} + +// Just stop working, don't x_free memory +x_err_t _QuitRun(TimerType timer) +{ + x_base lock = 0; + + NULL_PARAM_CHECK(timer); + + if (!(timer->active_status == TIMER_ACTIVE_TRUE)) + return -ERROR; + + lock = CriticalAreaLock(); + + timer->active_status = TIMER_ACTIVE_FALSE; + timer->deadline_timeslice = 0; + DoubleLinkListRmNode(&(timer->sortlist)); + + CriticalAreaUnLock(lock); + + return EOK; +} + +x_err_t _Modify(TimerType timer, x_ticks_t ticks) +{ + NULL_PARAM_CHECK(timer); + if (0 == ticks) { + KPrintf("timeout ticks must be setted more then 0.\n"); + return -EINVALED; + } + timer->origin_timeslice = ticks; + return EOK; +} + +static struct TimerDone Done = +{ + .Init = _Init, + .Delete = _Delete, + .StartRun = _StartRun, + .QuitRun = _QuitRun, + .Modify = _Modify, +}; + +/** + * This function will create a softtimer. + * + * @param name the length of the msg queue. + * @param timeout the callback of the timer. + * @param parameter the parameter of the callback function + * @param time the timeout time + * @param trigger_mode the trigger way of the timer + * + * @return id on success + */ + +int32 KCreateTimer(const char *name, + void (*timeout)(void *parameter), + void *parameter, + x_ticks_t time, + uint8 trigger_mode) +{ + struct Timer *timer = NONE; + + timer = (struct Timer *)x_malloc(sizeof(struct Timer)); + if (timer == NONE) { + return NONE; + } + memset(timer, 0x0, sizeof(struct Timer)); + + // Generate ID + int32 id = IdInsertObj(&k_softtimer_id_manager, &timer->id_node); + if (id < 0) { + x_free(timer); + return NONE; + } + + timer->done = &Done; + timer->done->Init(timer, name, timeout, parameter, time, trigger_mode); + + return id; +} + +/** + * This function will delete a timer. + * + * @param timer_id the id number of timer. + * + * @return + */ + +x_err_t KDeleteTimer(int32 timer_id) +{ + TimerType timer = KGetTimer(timer_id); + + timer->done->Delete(timer); +} + +/** + * This function will startup a timer. + * + * @param timer_id the id number of timer. + * + * @return + */ +x_err_t KTimerStartRun(int32 timer_id) +{ + TimerType timer = KGetTimer(timer_id); + + return timer->done->StartRun(timer); +} + +/** + * This function will stop a timer. + * + * @param timer_id the id number of timer. + * + * @return + */ +x_err_t KTimerQuitRun(int32 timer_id) +{ + TimerType timer = KGetTimer(timer_id); + + timer->done->QuitRun(timer); +} + +/** + * This function will modify the timeout of a timer. + * + * @param timer_id the id number of timer. + * @param ticks timeout ticks + * + * @return + */ +x_err_t KTimerModify(int32 timer_id, x_ticks_t ticks) +{ + TimerType timer = KGetTimer(timer_id); + + timer->done->Modify(timer, ticks); +} + +static void TimerCBEnter(void *param) +{ + struct Timer *t = (struct Timer *)param; + + t->func_callback(t->param); + x_free(t->t_work); +} + +void timer_work_func(struct Work *work, void *work_data) +{ + x_err_t flag; + struct Timer *t = work_data; + + int32 timer_work = KTaskCreate("timer_work_thr", TimerCBEnter, t, 2048, t->prio); + flag = StartupKTask(timer_work); + if (flag != EOK) { + KPrintf("timer create callback thread failed .\n"); + } + + return; +} + +void CheckTimerList(void) +{ + x_base lock = 0; + struct Timer *t = NONE; + x_ticks_t current_tick = 0; + + SYS_KDEBUG_LOG(KDBG_SOFTTIMER, ("timer check enter\n")); + + current_tick = CurrentTicksGain(); + + lock = CriticalAreaLock(); + + while (!IsDoubleLinkListEmpty(&xiaoshan_timer_sort_head)) { + t = SYS_DOUBLE_LINKLIST_ENTRY(xiaoshan_timer_sort_head.node_next, + struct Timer, sortlist); + + if ((current_tick - t->deadline_timeslice) < TICK_SIZE_MAX / 2) { + if (t->active_status == TIMER_ACTIVE_TRUE) { + DoubleLinkListRmNode(&t->sortlist); // Take it off the list first + + current_tick = CurrentTicksGain(); + + SYS_KDEBUG_LOG(KDBG_SOFTTIMER, ("current tick: %d\n", current_tick)); + + if (t->trigger_mode == TIMER_TRIGGER_PERIODIC) { + t->done->StartRun(t); // Periodic timer, re insert the appropriate position of the list + } else { + t->done->QuitRun(t); + } + + // Throw it to the task queue and start a new thread + t->t_work = x_malloc(sizeof(struct Work)); + + ((WorkQueueDoneType *)sys_workq->done)->WorkInit(t->t_work, timer_work_func, t); + CriticalAreaUnLock(lock); + ((WorkQueueDoneType *)sys_workq->done)->WorkSubmit((WorkqueueType *)sys_workq->property, t->t_work, 0); + lock = CriticalAreaLock(); + } else { + KPrintf("sortlist run unactive timer(%s), quit this timer\n", t->name); + } + } + else + break; + } + + CriticalAreaUnLock(lock); + + SYS_KDEBUG_LOG(KDBG_SOFTTIMER, ("timer check leave\n")); +} + +x_err_t KTimerAssignMemberRun(int32 timer_id, x_ticks_t ticks) +{ + TimerType timer = KGetTimer(timer_id); + + NULL_PARAM_CHECK(timer); + if (ticks == 0) { + KPrintf("Timeout ticks must be setted more than 0.\n"); + return -EINVALED; + } + timer->origin_timeslice = ticks; + + return timer->done->StartRun(timer); +} + +/** + * This function will get the timer with id. + * + * @param id the id number of timer. + * + * @return timer structrue + */ +TimerType KGetTimer(int32 id) +{ + x_base lock = 0; + TimerType timer = NONE; + + lock = CriticalAreaLock(); + struct IdNode *idnode = IdGetObj(&k_softtimer_id_manager, id); + if (idnode == NONE){ + CriticalAreaUnLock(lock); + return NONE; + } + + timer = CONTAINER_OF(idnode, struct Timer, id_node); + CriticalAreaUnLock(lock); + return timer; +} + +int32 KGetTimerID(TimerType timer) +{ + return timer->id_node.id; +} \ No newline at end of file diff --git a/Ubiquitous/XiZi/kernel/thread/tick.c b/Ubiquitous/XiZi/kernel/thread/tick.c new file mode 100644 index 0000000..49f75f3 --- /dev/null +++ b/Ubiquitous/XiZi/kernel/thread/tick.c @@ -0,0 +1,131 @@ +/* +* Copyright (c) 2020 AIIT XUOS Lab +* XiUOS is licensed under Mulan PSL v2. +* You can use this software according to the terms and conditions of the Mulan PSL v2. +* You may obtain a copy of Mulan PSL v2 at: +* http://license.coscl.org.cn/MulanPSL2 +* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, +* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, +* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. +* See the Mulan PSL v2 for more details. +*/ + +/** +* @file: tick.c +* @brief: system heartbeat_ticks update +* @version: 1.0 +* @author: AIIT XUOS Lab +* @date: 2020/3/15 +* +*/ + +#include +#include +#include + +extern void Time_Update_LwIP(void); + +#ifdef ARCH_SMP +static x_ticks_t heartbeat_ticks[CPU_NUMBERS] = {0}; +#else +static x_ticks_t heartbeat_ticks = 0; +#endif + +#ifdef ARCH_SMP +#define UPDATE_GLOBAL_HEARTBEAT() \ + do { \ + heartbeat_ticks[GetCpuId()]++; \ + } while(0); +#else +#define UPDATE_GLOBAL_HEARTBEAT() \ + do { \ + heartbeat_ticks ++; \ + } while(0); +#endif + +/** + * get haertbeat count + * + * @return CurrentTicks + */ +x_ticks_t CurrentTicksGain(void) +{ +#ifdef ARCH_SMP + return heartbeat_ticks[GetCpuId()]; +#else + return heartbeat_ticks; +#endif +} + +/** + * this function increases global systick in tick interrupt,and process task time slice + * + */ +void TickAndTaskTimesliceUpdate(void) +{ + struct TaskDescriptor *task = NONE; + + UPDATE_GLOBAL_HEARTBEAT(); + +#if defined(SCHED_POLICY_FIFO) + FifoTaskTimesliceUpdate(); +#elif defined (SCHED_POLICY_RR) + task = GetKTaskDescriptor(); + RoundRobinTaskTimesliceUpdate(task); +#elif defined (SCHED_POLICY_RR_REMAINSLICE) + task = GetKTaskDescriptor(); + if(task){ + RoundRobinRemainTaskTimesliceUpdate(task); + } +#endif + CheckTaskDelay(); +#ifdef KERNEL_SOFTTIMER + CheckTimerList(); +#endif +#ifdef BSP_USING_LWIP + Time_Update_LwIP(); +#endif + +} + +/** + * This function will convert ms to ticks. + * + * @param ms time need to be converted + * @return ticks + */ +#define MIN_TICKS 1 + +x_ticks_t CalculteTickFromTimeMs(uint32 ms) +{ + uint32 tmp = 0; + x_ticks_t ticks = 0; + + ticks = (uint32)(((uint64)(ms * TICK_PER_SECOND)) / 1000) ; + if (0 == ticks) { + ticks = MIN_TICKS; + } else { + tmp = (uint32)(((uint64)(ms * TICK_PER_SECOND)) % 1000); + + if(tmp >= 5 && tmp <= 9) { + ticks = ticks + MIN_TICKS; + } + } + + return ticks; +} + +/** + * This function will convert ticks to ms. + * + * @param ticks ticks need to be converted + * @return ms + */ +uint32 CalculteTimeMsFromTick(x_ticks_t ticks) +{ + uint32 ms = 0; + + ms = (uint32)(((uint64)(ticks * 1000)) / TICK_PER_SECOND); + + return ms; +} diff --git a/Ubiquitous/XiZi/kernel/thread/waitqueue.c b/Ubiquitous/XiZi/kernel/thread/waitqueue.c new file mode 100644 index 0000000..f4fa7b8 --- /dev/null +++ b/Ubiquitous/XiZi/kernel/thread/waitqueue.c @@ -0,0 +1,148 @@ +/* +* Copyright (c) 2020 AIIT XUOS Lab +* XiUOS is licensed under Mulan PSL v2. +* You can use this software according to the terms and conditions of the Mulan PSL v2. +* You may obtain a copy of Mulan PSL v2 at: +* http://license.coscl.org.cn/MulanPSL2 +* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, +* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, +* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. +* See the Mulan PSL v2 for more details. +*/ + +/** +* @file: waitqueue.c +* @brief: waitqueue file +* @version: 1.0 +* @author: AIIT XUOS Lab +* @date: 2020/3/15 +* +*/ + +#include + +#include +#include +#include +#include +/** + * This function will add a waitqueue node to the wait queue list + *@parm queue waitqueue descriptor + *@parm work the node need to be added + * + */ +void WqueueAdd(WaitQueueType *queue, struct WaitqueueNode *node) +{ + x_base lock = 0; + + NULL_PARAM_CHECK(queue); + NULL_PARAM_CHECK(node); + + lock = CriticalAreaLock(); + DoubleLinkListInsertNodeBefore(&(queue->block_threads_list), &(node->list)); + CriticalAreaUnLock(lock); +} +/** + * This function will remove a waitqueue node from the wait queue list + *@parm work the node need to be removed + * + */ +void WqueueRemove(struct WaitqueueNode *node) +{ + x_base lock = 0; + NULL_PARAM_CHECK(node); + + lock = CriticalAreaLock(); + DoubleLinkListRmNode(&(node->list)); + CriticalAreaUnLock(lock); +} + +/** + * This function restarts the suspended task of the queue + * @parm waitqueue pointer + * @parm the awake key + */ +void WakeupWqueue(WaitQueueType *queue, void *key) +{ + x_base lock = 0; + + NULL_PARAM_CHECK(queue); + NULL_PARAM_CHECK(key); + + lock = CriticalAreaLock(); + struct SysDoubleLinklistNode *node = NONE; + DOUBLE_LINKLIST_FOR_EACH(node, &(queue->block_threads_list)) { + struct WaitqueueNode *pEnter; + pEnter = SYS_DOUBLE_LINKLIST_ENTRY(node, struct WaitqueueNode, list); + if (pEnter->cb != NONE && pEnter->cb(pEnter, key) != 0) { + continue; + } else { + KTaskWakeup(pEnter->polling_task->id.id); + } + } + CriticalAreaUnLock(lock); + + if (node == &(queue->block_threads_list)) { + return; + } + + DO_KTASK_ASSIGN; +} +/** + * This function will suspend current task and start up a timer + * @parm queue waitqueue descriptor + * @parm msec waiting time + * + */ +int WqueueWait(WaitQueueType *queue, x_ticks_t tick) +{ + NULL_PARAM_CHECK(queue); + + if (tick == 0) + return 0; + + struct WaitqueueNode* pin_node = x_malloc(sizeof(struct WaitqueueNode)); + + // set timeout awake + if (tick != WAITING_FOREVER) { + pin_node->deadline_tick = CurrentTicksGain() + tick; + KTaskSetDelay(GetKTaskDescriptor(), tick); + } else { + pin_node->deadline_tick = 0; + } + + // init block node + pin_node->polling_task = GetKTaskDescriptor(); + pin_node->key = 0; + pin_node->cb = NONE; + pin_node->list.node_next = &pin_node->list; + pin_node->list.node_prev = &pin_node->list; + + // start block + x_base lock; + lock = CriticalAreaLock(); + WqueueAdd(queue, pin_node); + SuspendKTask(GetKTaskDescriptor()->id.id); + CriticalAreaUnLock(lock); + + DO_KTASK_ASSIGN; + + // end block, delete node + WqueueRemove(pin_node); + x_free(pin_node); + + return 0; +} + +/** + * This function will create a wait queue. + * + * @param queue queue waitqueue descriptor + * + */ +void InitWqueue(WaitQueueType *queue) +{ + NULL_PARAM_CHECK(queue); + + InitDoubleLinkList(&(queue->block_threads_list)); +} \ No newline at end of file diff --git a/Ubiquitous/XiZi/kernel/thread/workqueue.c b/Ubiquitous/XiZi/kernel/thread/workqueue.c new file mode 100644 index 0000000..d2d2d2b --- /dev/null +++ b/Ubiquitous/XiZi/kernel/thread/workqueue.c @@ -0,0 +1,183 @@ +/* +* Copyright (c) 2020 AIIT XUOS Lab +* XiUOS is licensed under Mulan PSL v2. +* You can use this software according to the terms and conditions of the Mulan PSL v2. +* You may obtain a copy of Mulan PSL v2 at: +* http://license.coscl.org.cn/MulanPSL2 +* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, +* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, +* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. +* See the Mulan PSL v2 for more details. +*/ + +/** +* @file: workqueue.c +* @brief: workqueue file +* @version: 1.0 +* @author: AIIT XUOS Lab +* @date: 2020/3/15 +* +*/ + +#include +#include +queue *sys_workq = NONE; + +static void WorkQueueKTaskEntry(void *parameter) +{ + x_base lock = 0; + WorkqueueType *p_queue = (WorkqueueType *)parameter; + + while (1) + { + lock = CriticalAreaLock(); + if (p_queue->front != p_queue->rear) { // The team is not empty + struct Work *work = &(p_queue->base[p_queue->front]); + + p_queue->front = (p_queue->front + 1) % MAX_WORK_QUEUE; + CriticalAreaUnLock(lock); + + if (work->cb_func) { + work->cb_func(work, work->cb_param); + } + } else { + CriticalAreaUnLock(lock); + + SuspendKTask(p_queue->task); + DO_KTASK_ASSIGN; + } + } +} + +void DeInitWorkQueue(WorkqueueType *p_queue) +{ + if (NONE != p_queue->task) { + KTaskDelete(p_queue->task); + } + + if (NONE != p_queue) { + if (NONE != p_queue->base) { + x_free(p_queue->base); + } + x_free(p_queue); + } +} + +WorkqueueType *CreateWorkQueue(const char *name, uint16 stack_size, uint8 priority) +{ + WorkqueueType *p_queue = NONE; + do { + p_queue = x_malloc(sizeof(WorkqueueType)); + + if (NONE == p_queue) { + KPrintf("CreateWorkQueue x_malloc(sizeof(WorkqueueType) failed\n"); + break; + } + + memset(p_queue, 0, sizeof(WorkqueueType)); + + p_queue->base = x_malloc(MAX_WORK_QUEUE * sizeof(struct Work)); + if (NONE == p_queue->base) { + KPrintf("CreateWorkQueue x_malloc(MAX_WORK_QUEUE * sizeof(struct Work) failed\n"); + break; + } + memset(p_queue->base, 0, MAX_WORK_QUEUE * sizeof(struct Work)); + + p_queue->front = p_queue->rear = 0; + + // start work thread + p_queue->task = KTaskCreate(name, WorkQueueKTaskEntry, p_queue, 2048, priority); + if (NONE == p_queue->task) { + KPrintf("CreateWorkQueue KTaskCreate failed\n"); + break; + } + StartupKTask(p_queue->task); + + return p_queue; + } while (0); + + DeInitWorkQueue(p_queue); + return NONE; +} + +void WorkInit(struct Work *work, void (*work_func)(struct Work *work, void *work_data), void *work_data) +{ + work->cb_func = work_func; + work->cb_param = work_data; +} + +void work_elem_timeout(void *in_param) +{ + WorkTimerParamType *param = (WorkTimerParamType *)in_param; + WorkSubmit_immediate(param->p_queue, param->p_work); +} + +x_err_t WorkSubmit_immediate(WorkqueueType *sys_workq, struct Work *work) +{ + x_base lock = CriticalAreaLock(); + + NULL_PARAM_CHECK(sys_workq); + NULL_PARAM_CHECK(work); + + // check queue is full + if ((sys_workq->rear + 1 + MAX_WORK_QUEUE) % MAX_WORK_QUEUE == sys_workq->front) { + CriticalAreaUnLock(lock); + return -ERROR; + } + // add to queue + sys_workq->base[sys_workq->rear].cb_func = work->cb_func; + sys_workq->base[sys_workq->rear].cb_param = work->cb_param; + sys_workq->rear = (sys_workq->rear + 1) % MAX_WORK_QUEUE; + + // awake work thread + KTaskWakeup(sys_workq->task); + CriticalAreaUnLock(lock); + DO_KTASK_ASSIGN; +} + +x_err_t WorkSubmit(WorkqueueType *sys_workq, struct Work *work, x_ticks_t time) +{ + NULL_PARAM_CHECK(sys_workq); + NULL_PARAM_CHECK(work); + + if (0 == time) { + WorkSubmit_immediate(sys_workq, work); + } else { + // init a timer, add to queue later + WorkTimerParamType *param = x_malloc(sizeof(WorkTimerParamType)); + param->p_queue = sys_workq; + param->p_work = work; + param->p_timer = KCreateTimer("wk_timer", work_elem_timeout, param, time, TIMER_TRIGGER_ONCE); + if (NONE == param->p_timer) { + KPrintf("WorkSubmit KCreateTimer failed \n"); + x_free(param); + return -ERROR; + } + KTimerStartRun(param->p_timer); + } + return EOK; +} + +/** + * This function will create a workqueue. + * + * @return EOK on success;ERROR on failure + */ +int WorkSysWorkQueueInit(void) +{ + if (sys_workq != NONE) + return 0; + + sys_workq = x_malloc(sizeof(queue)); + sys_workq->done = g_queue_done[WORK_QUEUE]; + sys_workq->property = ((WorkQueueDoneType*)sys_workq->done)->CreateWorkQueue("sys_work", WORKQUEUE_KTASK_STACKSIZE, + WORKQUEUE_KTASK_PRIORITY); + + if (sys_workq->property == NONE) { + KPrintf("log sys_workq create failed\n"); + } else { + KPrintf("log sys_workq create success\n"); + } + + return sys_workq->property == NONE ? ERROR : EOK; +} \ No newline at end of file diff --git a/Ubiquitous/XiZi/kernel/thread/zombierecycle.c b/Ubiquitous/XiZi/kernel/thread/zombierecycle.c new file mode 100644 index 0000000..cf74adc --- /dev/null +++ b/Ubiquitous/XiZi/kernel/thread/zombierecycle.c @@ -0,0 +1,94 @@ + +/* +* Copyright (c) 2020 AIIT XUOS Lab +* XiUOS is licensed under Mulan PSL v2. +* You can use this software according to the terms and conditions of the Mulan PSL v2. +* You may obtain a copy of Mulan PSL v2 at: +* http://license.coscl.org.cn/MulanPSL2 +* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, +* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, +* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. +* See the Mulan PSL v2 for more details. +*/ + +/** +* @file: zombierecycle.c +* @brief: a recycle task of system +* @version: 1.0 +* @author: AIIT XUOS Lab +* @date: 2020/3/15 +* +*/ + +#include +#ifdef TASK_ISOLATION +#include +#endif + +DoubleLinklistType KTaskZombie; + +#ifndef ZOMBIE_KTASK_STACKSIZE +#define ZOMBIE_KTASK_STACKSIZE 2048 +#endif + + int32 zombie_recycle; + +int JudgeZombieKTaskIsNotEmpty(void) +{ + return (IsDoubleLinkListEmpty(&KTaskZombie) ? 0 : RET_TRUE); +} + +static void ZombieKTaskEntry(void *parameter) +{ + x_base lock = 0; + KTaskDescriptorType task = NONE; + + while(RET_TRUE) + { + KDEBUG_NOT_IN_INTERRUPT; + lock = CriticalAreaLock(); + if (JudgeZombieKTaskIsNotEmpty()) { + task = SYS_DOUBLE_LINKLIST_ENTRY(KTaskZombie.node_next, struct TaskDescriptor, task_dync_sched_member.sched_link); + DoubleLinkListRmNode(&(task->task_dync_sched_member.sched_link)); + CriticalAreaUnLock(lock); +#ifdef SEPARATE_COMPILE + if(1 == task->task_dync_sched_member.isolation_flag ){ +#ifdef MOMERY_PROTECT_ENABLE + if(mem_access.Free) + mem_access.Free(task->task_dync_sched_member.isolation); +#endif + x_ufree(task->task_base_info.stack_start); + } else +#endif + { + KERNEL_FREE(task->task_base_info.stack_start); + } + + DoubleLinkListRmNode(&(task->link)); + + KTaskIdDelete(task->id.id); + + if(task->task_dync_sched_member.delay != NONE){ + KERNEL_FREE(task->task_dync_sched_member.delay); + } + KERNEL_FREE(task); + } else { + SuspendKTask(zombie_recycle); + CriticalAreaUnLock(lock); + DO_KTASK_ASSIGN; + } + } +} + +void ZombieTaskRecycleInit(void) +{ + InitDoubleLinkList(&KTaskZombie); + + zombie_recycle = KTaskCreate("ZombieRecycleKTask", + ZombieKTaskEntry, + NONE, + ZOMBIE_KTASK_STACKSIZE, + KTASK_PRIORITY_MAX - 1); + + StartupKTask(zombie_recycle); +} \ No newline at end of file diff --git a/Ubiquitous/XiZi/link.mk b/Ubiquitous/XiZi/link.mk new file mode 100644 index 0000000..ddaf43e --- /dev/null +++ b/Ubiquitous/XiZi/link.mk @@ -0,0 +1,10 @@ +OBJS := $(shell cat make.obj) + +$(TARGET): $(OBJS) + @echo ------------------------------------------------ + @echo link $(TARGET) + @$(CROSS_COMPILE)g++ -o $@ $($(LINK_FLAGS)) $(OBJS) -lc -lm + @echo ------------------------------------------------ + @$(CROSS_COMPILE)objcopy -O binary $@ XiZi_$(BOARD)$(COMPILE_TYPE).bin + @$(CROSS_COMPILE)size $@ + diff --git a/Ubiquitous/XiZi/mergebin.py b/Ubiquitous/XiZi/mergebin.py new file mode 100644 index 0000000..2b2f9c5 --- /dev/null +++ b/Ubiquitous/XiZi/mergebin.py @@ -0,0 +1,27 @@ +import os + +def mergeBinProccess( files, fileSaveName): + bin = b'' + startAddrLast = files[0][1] + fileSizeLast = 0 + for file, addr in files: + fillLen = addr - (startAddrLast + fileSizeLast) + if fillLen > 0: # fill 0xFF + fill = bytearray([0xFF for i in range(fillLen)]) + bin += fill + with open(file, "rb") as f: # add bin file content + bin += f.read() + startAddrLast = addr + fileSizeLast = os.path.getsize(file) + with open(fileSaveName, "wb") as f: + f.write(bin) + +if __name__ == '__main__': + file1 = r'./build/XiZi_kd233_kernel.bin' + file1_start_addr = 0 + file2 = r'./build/XiZi_kd233_app.bin' + file2_start_addr = 1024 * 1024 + 4096 + newfile = r'./build/XiZi_kd233.bin' + + file = [ [file1 , file1_start_addr] , [file2 , file2_start_addr] ] + mergeBinProccess(file, newfile) \ No newline at end of file diff --git a/Ubiquitous/XiZi/path_app.mk b/Ubiquitous/XiZi/path_app.mk new file mode 100644 index 0000000..e38c34c --- /dev/null +++ b/Ubiquitous/XiZi/path_app.mk @@ -0,0 +1,44 @@ + +export APPPATHS :=-I$(BSP_ROOT) \ + +APPPATHS += -I$(KERNEL_ROOT)/../../APP_Framework/Applications/general_functions/list \ + -I$(KERNEL_ROOT)/../../APP_Framework/lib/app_newlib/include \ + -I$(KERNEL_ROOT)/../../APP_Framework/Framework/sensor # + +ifeq ($(CONFIG_ADD_XIZI_FETURES), y) +APPPATHS += -I$(KERNEL_ROOT)/../../APP_Framework/Framework/transform_layer/xizi \ + -I$(KERNEL_ROOT)/../../APP_Framework/Framework/transform_layer/xizi/user_api/switch_api \ + -I$(KERNEL_ROOT)/../../APP_Framework/Framework/transform_layer/xizi/user_api/posix_support/include # +endif + +ifeq ($(CONFIG_SUPPORT_CONNECTION_FRAMEWORK), y) +APPPATHS += -I$(KERNEL_ROOT)/../../APP_Framework/Framework/connection # +endif + +ifeq ($(CONFIG_SUPPORT_KNOWING_FRAMEWORK), y) +APPPATHS += -I$(KERNEL_ROOT)/../../APP_Framework/Framework/knowing # +APPPATHS += -I$(KERNEL_ROOT)/../../APP_Framework/Framework/knowing/tensorflow-lite/tensorflow-lite-for-mcu/source # +APPPATHS += -I$(KERNEL_ROOT)/../../APP_Framework/Framework/knowing/tensorflow-lite/tensorflow-lite-for-mcu/source/third_party/gemmlowp # +APPPATHS += -I$(KERNEL_ROOT)/../../APP_Framework/Framework/knowing/tensorflow-lite/tensorflow-lite-for-mcu/source/third_party/flatbuffers/include # +APPPATHS += -I$(KERNEL_ROOT)/../../APP_Framework/Framework/knowing/tensorflow-lite/tensorflow-lite-for-mcu/source/third_party/ruy # +endif + +ifeq ($(CONFIG_SUPPORT_CONTROL_FRAMEWORK), y) +APPPATHS += -I$(KERNEL_ROOT)/../../APP_Framework/Framework/control # +APPPATHS += -I$(KERNEL_ROOT)/../../APP_Framework/Framework/control/plc/interoperability/opcua # +endif + +ifeq ($(CONFIG_CRYPTO), y) +APPPATHS += -I$(KERNEL_ROOT)/../../APP_Framework/Framework/security/crypto/include # +endif + +COMPILE_APP: + @$(eval CPPPATHS=$(APPPATHS)) + @echo $(SRC_APP_DIR) + @for dir in $(SRC_APP_DIR);do \ + $(MAKE) -C $$dir; \ + done + @cp link.mk build/Makefile + @$(MAKE) -C build COMPILE_TYPE="_app" TARGET=XiZi_$(BOARD)_app.elf LINK_FLAGS=APPLFLAGS + @rm build/Makefile build/make.obj + diff --git a/Ubiquitous/XiZi/path_kernel.mk b/Ubiquitous/XiZi/path_kernel.mk new file mode 100755 index 0000000..91a7f3e --- /dev/null +++ b/Ubiquitous/XiZi/path_kernel.mk @@ -0,0 +1,398 @@ + +export KERNELPATHS:= + +ifeq ($(BSP_ROOT),$(KERNEL_ROOT)/board/xidatong) +KERNELPATHS :=-I$(BSP_ROOT) \ + -I$(KERNEL_ROOT)/arch/arm/cortex-m7 \ + -I$(BSP_ROOT)/third_party_driver \ + -I$(BSP_ROOT)/third_party_driver/include \ + -I$(BSP_ROOT)/third_party_driver/sdio/sdmmc/inc \ + -I$(BSP_ROOT)/third_party_driver/sdio/sdmmc/port \ + -I$(BSP_ROOT)/third_party_driver/usb/nxp_usb_driver/host \ + -I$(BSP_ROOT)/third_party_driver/usb/nxp_usb_driver/host/class \ + -I$(BSP_ROOT)/third_party_driver/usb/nxp_usb_driver/include \ + -I$(BSP_ROOT)/third_party_driver/usb/nxp_usb_driver/osa \ + -I$(BSP_ROOT)/third_party_driver/usb/nxp_usb_driver/phy \ + -I$(BSP_ROOT)/third_party_driver/ethernet \ + -I$(BSP_ROOT)/third_party_driver/ethernet/lan8720 \ + -I$(BSP_ROOT)/third_party_driver/MIMXRT1052 \ + -I$(BSP_ROOT)/third_party_driver/MIMXRT1052/drivers \ + -I$(BSP_ROOT)/third_party_driver/CMSIS/Include \ + -I$(KERNEL_ROOT)/include \ + -I$(KERNEL_ROOT)/resources/ethernet/LwIP \ + -I$(KERNEL_ROOT)/resources/ethernet/LwIP/include \ + -I$(KERNEL_ROOT)/resources/ethernet/LwIP/include/compat \ + -I$(KERNEL_ROOT)/resources/ethernet/LwIP/include/lwip \ + -I$(KERNEL_ROOT)/resources/ethernet/LwIP/include/netif \ + -I$(KERNEL_ROOT)/resources/ethernet/LwIP/include/lwip/apps \ + -I$(KERNEL_ROOT)/resources/ethernet/LwIP/include/lwip/priv \ + -I$(KERNEL_ROOT)/resources/ethernet/LwIP/include/lwip/prot \ + -I$(KERNEL_ROOT)/resources/ethernet/LwIP/arch \ + -I$(KERNEL_ROOT)/resources/include \ + -I$(BSP_ROOT)/include \ + -I$(BSP_ROOT)/xip # +endif + +ifeq ($(BSP_ROOT),$(KERNEL_ROOT)/board/kd233) +KERNELPATHS :=-I$(BSP_ROOT) \ + -I$(BSP_ROOT)/include \ + -I$(BSP_ROOT)/third_party_driver/include \ + -I$(BSP_ROOT)/third_party_driver \ + -I$(BSP_ROOT)/third_party_driver/camera \ + -I$(BSP_ROOT)/third_party_driver/drivers \ + -I$(BSP_ROOT)/third_party_driver/lcd \ + -I$(KERNEL_ROOT)/include # +endif + +ifeq ($(BSP_ROOT),$(KERNEL_ROOT)/board/maix-go) +KERNELPATHS :=-I$(BSP_ROOT) \ + -I$(BSP_ROOT)/include \ + -I$(BSP_ROOT)/third_party_driver/include \ + -I$(BSP_ROOT)/third_party_driver \ + -I$(BSP_ROOT)/third_party_driver/camera \ + -I$(BSP_ROOT)/third_party_driver/drivers \ + -I$(BSP_ROOT)/third_party_driver/lcd \ + -I$(KERNEL_ROOT)/include # +endif + +ifeq ($(BSP_ROOT),$(KERNEL_ROOT)/board/stm32f407-st-discovery) +KERNELPATHS :=-I$(BSP_ROOT) \ + -I$(KERNEL_ROOT)/arch/arm/cortex-m4 \ + -I$(BSP_ROOT)/third_party_driver \ + -I$(BSP_ROOT)/third_party_driver/sdio \ + -I$(BSP_ROOT)/include \ + -I$(BSP_ROOT)/third_party_driver/include \ + -I$(BSP_ROOT)/third_party_driver/usb/STM32_USB_OTG_Driver/inc \ + -I$(KERNEL_ROOT)/include \ + -I$(KERNEL_ROOT)/resources/ethernet/LwIP \ + -I$(KERNEL_ROOT)/resources/ethernet/LwIP/include \ + -I$(KERNEL_ROOT)/resources/ethernet/LwIP/include/compat \ + -I$(KERNEL_ROOT)/resources/ethernet/LwIP/include/lwip \ + -I$(KERNEL_ROOT)/resources/ethernet/LwIP/include/netif \ + -I$(KERNEL_ROOT)/resources/ethernet/LwIP/include/lwip/apps \ + -I$(KERNEL_ROOT)/resources/ethernet/LwIP/include/lwip/priv \ + -I$(KERNEL_ROOT)/resources/ethernet/LwIP/include/lwip/prot \ + -I$(KERNEL_ROOT)/resources/ethernet/LwIP/arch \ + -I$(BSP_ROOT)/include # +endif + +ifeq ($(BSP_ROOT),$(KERNEL_ROOT)/board/aiit-arm32-board) +KERNELPATHS :=-I$(BSP_ROOT) \ + -I$(KERNEL_ROOT)/arch/arm/cortex-m4 \ + -I$(BSP_ROOT)/third_party_driver \ + -I$(BSP_ROOT)/third_party_driver \ + -I$(BSP_ROOT)/include \ + -I$(BSP_ROOT)/third_party_driver/include \ + -I$(BSP_ROOT)/third_party_driver/spi/third_party_spi_lora/inc \ + -I$(BSP_ROOT)/third_party_driver/spi/third_party_spi_lora/src/radio \ + -I$(BSP_ROOT)/third_party_driver/usb/STM32_USB_OTG_Driver/inc \ + -I$(KERNEL_ROOT)/include \ + -I$(BSP_ROOT)/include # +endif + +ifeq ($(BSP_ROOT),$(KERNEL_ROOT)/board/stm32f407zgt6) +KERNELPATHS :=-I$(BSP_ROOT) \ + -I$(KERNEL_ROOT)/arch/arm/cortex-m4 \ + -I$(BSP_ROOT)/third_party_driver \ + -I$(BSP_ROOT)/third_party_driver/sdio\ + -I$(BSP_ROOT)/include \ + -I$(BSP_ROOT)/third_party_driver/include \ + -I$(BSP_ROOT)/third_party_driver/usb/STM32_USB_OTG_Driver/inc \ + -I$(KERNEL_ROOT)/include \ + -I$(BSP_ROOT)/include # +endif + +ifeq ($(BSP_ROOT),$(KERNEL_ROOT)/board/gapuino) +KERNELPATHS :=-I$(BSP_ROOT) \ + -I$(BSP_ROOT)/third_party_driver \ + -I$(BSP_ROOT)/third_party_driver/include \ + -I$(KERNEL_ROOT)/include # +endif + +ifeq ($(BSP_ROOT),$(KERNEL_ROOT)/board/gd32vf103_rvstar) +KERNELPATHS :=-I$(BSP_ROOT) \ + -I$(KERNEL_ROOT)/arch/risc-v/gd32vf103_rvstar \ + -I$(BSP_ROOT)/include \ + -I$(BSP_ROOT)/third_party_driver \ + -I$(BSP_ROOT)/third_party_driver/include \ + -I$(KERNEL_ROOT)/include # +endif + +ifeq ($(BSP_ROOT),$(KERNEL_ROOT)/board/rv32m1_vega) +KERNELPATHS :=-I$(BSP_ROOT) \ + -I$(KERNEL_ROOT)/arch/risc-v/rv32m1_vega \ + -I$(BSP_ROOT)/include \ + -I$(BSP_ROOT)/third_party_driver \ + -I$(BSP_ROOT)/third_party_driver/include \ + -I$(KERNEL_ROOT)/include # +endif + +ifeq ($(BSP_ROOT),$(KERNEL_ROOT)/board/hifive1-rev-B) +KERNELPATHS :=-I$(BSP_ROOT) \ + -I$(BSP_ROOT)/third_party_driver \ + -I$(BSP_ROOT)/third_party_driver/include \ + -I$(BSP_ROOT)/third_party_driver/include/sifive \ + -I$(BSP_ROOT)/third_party_driver/include/sifive/devices \ + -I$(BSP_ROOT)/third_party_driver/fe300prci \ + -I$(BSP_ROOT)/third_party_driver/plic\ + -I$(KERNEL_ROOT)/include # +endif + +ifeq ($(BSP_ROOT),$(KERNEL_ROOT)/board/hifive1-emulator) +KERNELPATHS :=-I$(BSP_ROOT) \ + -I$(BSP_ROOT)/third_party_driver \ + -I$(BSP_ROOT)/third_party_driver/include \ + -I$(BSP_ROOT)/third_party_driver/include/sifive \ + -I$(BSP_ROOT)/third_party_driver/include/sifive/devices \ + -I$(BSP_ROOT)/third_party_driver/fe300prci \ + -I$(BSP_ROOT)/third_party_driver/plic\ + -I$(KERNEL_ROOT)/include # +endif + +ifeq ($(BSP_ROOT),$(KERNEL_ROOT)/board/k210-emulator) +KERNELPATHS :=-I$(BSP_ROOT) \ + -I$(BSP_ROOT)/third_party_driver \ + -I$(BSP_ROOT)/include \ + -I$(BSP_ROOT)/third_party_driver/include \ + -I$(BSP_ROOT)/third_party_driver/spi/third_party_spi_lora/inc \ + -I$(BSP_ROOT)/third_party_driver/spi/third_party_spi_lora/src/radio \ + -I$(BSP_ROOT)/third_party_driver/camera \ + -I$(BSP_ROOT)/third_party_driver/drivers \ + -I$(BSP_ROOT)/third_party_driver/lcd \ + -I$(KERNEL_ROOT)/include # +endif + +ifeq ($(BSP_ROOT),$(KERNEL_ROOT)/board/aiit-riscv64-board) +KERNELPATHS :=-I$(BSP_ROOT) \ + -I$(BSP_ROOT)/third_party_driver \ + -I$(BSP_ROOT)/include \ + -I$(BSP_ROOT)/third_party_driver/include \ + -I$(BSP_ROOT)/third_party_driver/spi/third_party_spi_lora/inc \ + -I$(BSP_ROOT)/third_party_driver/spi/third_party_spi_lora/src/radio \ + -I$(BSP_ROOT)/third_party_driver/camera \ + -I$(BSP_ROOT)/third_party_driver/drivers \ + -I$(BSP_ROOT)/third_party_driver/lcd \ + -I$(KERNEL_ROOT)/include # +endif + +ifeq ($(BSP_ROOT),$(KERNEL_ROOT)/board/cortex-m0-emulator) +KERNELPATHS :=-I$(BSP_ROOT) \ + -I$(KERNEL_ROOT)/arch/arm/cortex-m0 \ + -I$(BSP_ROOT)/third_party_driver \ + -I$(BSP_ROOT)/third_party_driver/Libraries/driverlib \ + -I$(BSP_ROOT)/third_party_driver/Libraries/ \ + -I$(BSP_ROOT)/third_party_driver/Libraries/inc \ + -I$(KERNEL_ROOT)/include \ + -I$(BSP_ROOT)/include # +endif + +ifeq ($(BSP_ROOT),$(KERNEL_ROOT)/board/cortex-m3-emulator) +KERNELPATHS :=-I$(BSP_ROOT) \ + -I$(KERNEL_ROOT)/arch/arm/cortex-m3 \ + -I$(BSP_ROOT)/third_party_driver \ + -I$(BSP_ROOT)/third_party_driver/Libraries/driverlib \ + -I$(BSP_ROOT)/third_party_driver/Libraries/ \ + -I$(BSP_ROOT)/third_party_driver/Libraries/inc \ + -I$(KERNEL_ROOT)/include \ + -I$(BSP_ROOT)/include # +endif + +ifeq ($(BSP_ROOT),$(KERNEL_ROOT)/board/cortex-m4-emulator) +KERNELPATHS :=-I$(BSP_ROOT) \ + -I$(KERNEL_ROOT)/arch/arm/cortex-m4 \ + -I$(BSP_ROOT)/third_party_driver \ + -I$(BSP_ROOT)/third_party_driver/sdio\ + -I$(BSP_ROOT)/include \ + -I$(BSP_ROOT)/third_party_driver/include \ + -I$(BSP_ROOT)/third_party_driver/usb/STM32_USB_OTG_Driver/inc \ + -I$(KERNEL_ROOT)/include \ + -I$(BSP_ROOT)/include # +endif + +ifeq ($(BSP_ROOT),$(KERNEL_ROOT)/board/ok1052-c) +KERNELPATHS :=-I$(BSP_ROOT) \ + -I$(KERNEL_ROOT)/arch/arm/cortex-m7 \ + -I$(BSP_ROOT)/third_party_driver \ + -I$(BSP_ROOT)/third_party_driver/include \ + -I$(BSP_ROOT)/third_party_driver/sdio/sdmmc/inc \ + -I$(BSP_ROOT)/third_party_driver/sdio/sdmmc/port \ + -I$(BSP_ROOT)/third_party_driver/usb/nxp_usb_driver/host \ + -I$(BSP_ROOT)/third_party_driver/usb/nxp_usb_driver/host/class \ + -I$(BSP_ROOT)/third_party_driver/usb/nxp_usb_driver/include \ + -I$(BSP_ROOT)/third_party_driver/usb/nxp_usb_driver/osa \ + -I$(BSP_ROOT)/third_party_driver/usb/nxp_usb_driver/phy \ + -I$(BSP_ROOT)/third_party_driver/ethernet \ + -I$(BSP_ROOT)/third_party_driver/ethernet/ksz8081 \ + -I$(BSP_ROOT)/third_party_driver/MIMXRT1052 \ + -I$(BSP_ROOT)/third_party_driver/MIMXRT1052/drivers \ + -I$(BSP_ROOT)/third_party_driver/CMSIS/Include \ + -I$(KERNEL_ROOT)/include \ + -I$(KERNEL_ROOT)/resources/ethernet/LwIP \ + -I$(KERNEL_ROOT)/resources/ethernet/LwIP/include \ + -I$(KERNEL_ROOT)/resources/ethernet/LwIP/include/compat \ + -I$(KERNEL_ROOT)/resources/ethernet/LwIP/include/lwip \ + -I$(KERNEL_ROOT)/resources/ethernet/LwIP/include/netif \ + -I$(KERNEL_ROOT)/resources/ethernet/LwIP/include/lwip/apps \ + -I$(KERNEL_ROOT)/resources/ethernet/LwIP/include/lwip/priv \ + -I$(KERNEL_ROOT)/resources/ethernet/LwIP/include/lwip/prot \ + -I$(KERNEL_ROOT)/resources/ethernet/LwIP/arch \ + -I$(KERNEL_ROOT)/resources/include \ + -I$(BSP_ROOT)/include \ + -I$(BSP_ROOT)/xip # +endif + +ifeq ($(BSP_ROOT),$(KERNEL_ROOT)/board/stm32f103-nano) +KERNELPATHS :=-I$(BSP_ROOT) \ + -I$(KERNEL_ROOT)/arch/arm/cortex-m3 \ + -I$(BSP_ROOT)/third_party_driver/include \ + -I$(BSP_ROOT)/third_party_driver/libraries/STM32F1xx_HAL/inc \ + -I$(BSP_ROOT)/third_party_driver/libraries/CMSIS \ + -I$(KERNEL_ROOT)/include \ + -I$(BSP_ROOT)/include # +endif + +ifeq ($(BSP_ROOT),$(KERNEL_ROOT)/board/nuvoton-m2354) +KERNELPATHS :=-I$(BSP_ROOT) \ + -I$(KERNEL_ROOT)/arch/arm/cortex-m23 \ + -I$(BSP_ROOT)/third_party_driver/include \ + -I$(BSP_ROOT)/third_party_driver/include/Drivers \ + -I$(BSP_ROOT)/third_party_driver/include/Regs \ + -I$(BSP_ROOT)/third_party_driver/include/NuUtils/inc \ + -I$(BSP_ROOT)/third_party_driver/common/NuClockConfig \ + -I$(BSP_ROOT)/third_party_driver/common/NuPinConfig \ + -I$(KERNEL_ROOT)/include \ + -I$(BSP_ROOT)/include # +endif + +KERNELPATHS += -I$(KERNEL_ROOT)/arch \ + -I$(KERNEL_ROOT)/arch/risc-v/shared/kernel_service # + +ifeq ($(CONFIG_FS_VFS), y) +KERNELPATHS +=-I$(KERNEL_ROOT)/fs/devfs \ + -I$(KERNEL_ROOT)/fs/fatfs \ + -I$(KERNEL_ROOT)/fs/shared/include # +endif + +ifeq ($(CONFIG_FS_CH376), y) +KERNELPATHS +=-I$(KERNEL_ROOT)/fs/compatibility_ch376 # +endif + +ifeq ($(CONFIG_TRANSFORM_LAYER_ATTRIUBUTE), y) +ifeq ($(CONFIG_ADD_XIZI_FETURES), y) +KERNELPATHS += -I$(KERNEL_ROOT)/../../APP_Framework/Framework/transform_layer/xizi/user_api/posix_support/include # +KERNELPATHS += -I$(KERNEL_ROOT)/../../APP_Framework/Framework/transform_layer/xizi # +endif + +ifeq ($(CONFIG_ADD_NUTTX_FETURES), y) +# +endif + +ifeq ($(CONFIG_ADD_RTTHREAD_FETURES), y) +# +endif + +endif + +KERNELPATHS += -I$(KERNEL_ROOT)/../../APP_Framework/Applications/general_functions/list # + +ifeq ($(CONFIG_SUPPORT_SENSOR_FRAMEWORK), y) +KERNELPATHS += -I$(KERNEL_ROOT)/../../APP_Framework/Framework/sensor # +endif + +ifeq ($(CONFIG_SUPPORT_CONNECTION_FRAMEWORK), y) +KERNELPATHS += -I$(KERNEL_ROOT)/../../APP_Framework/Framework/connection # +KERNELPATHS += -I$(KERNEL_ROOT)/../../APP_Framework/Framework/connection/zigbee # +endif + +ifeq ($(CONFIG_ADAPTER_HFA21_ETHERCAT), y) +KERNELPATHS += -I$(KERNEL_ROOT)/../../APP_Framework/Framework/connection/industrial_ethernet/ethercat # +endif + +ifeq ($(CONFIG_SUPPORT_KNOWING_FRAMEWORK), y) +KERNELPATHS += -I$(KERNEL_ROOT)/../../APP_Framework/Framework/knowing # +KERNELPATHS += -I$(KERNEL_ROOT)/../../APP_Framework/Framework/knowing/tensorflow-lite/tensorflow-lite-for-mcu/source # +KERNELPATHS += -I$(KERNEL_ROOT)/../../APP_Framework/Framework/knowing/tensorflow-lite/tensorflow-lite-for-mcu/source/third_party/gemmlowp # +KERNELPATHS += -I$(KERNEL_ROOT)/../../APP_Framework/Framework/knowing/tensorflow-lite/tensorflow-lite-for-mcu/source/third_party/flatbuffers/include # +KERNELPATHS += -I$(KERNEL_ROOT)/../../APP_Framework/Framework/knowing/tensorflow-lite/tensorflow-lite-for-mcu/source/third_party/ruy # +endif + +ifeq ($(CONFIG_LIB_LV),y) +KERNELPATHS += -I$(KERNEL_ROOT)/../../APP_Framework/lib/lvgl # +KERNELPATHS += -I$(KERNEL_ROOT)/../../APP_Framework/lib/lvgl/examples/porting # +endif + +ifeq ($(CONFIG_SUPPORT_CONTROL_FRAMEWORK), y) +KERNELPATHS += -I$(KERNEL_ROOT)/../../APP_Framework/Framework/control # +KERNELPATHS += -I$(KERNEL_ROOT)/../../APP_Framework/Framework/control/shared # +KERNELPATHS += -I$(KERNEL_ROOT)/../../APP_Framework/Framework/control/plc/interoperability/opcua # +KERNELPATHS += -I$(KERNEL_ROOT)/../../APP_Framework/Framework/control/plc/shared # +KERNELPATHS += -I$(KERNEL_ROOT)/../../APP_Framework/lib/cJSON +endif + +ifeq ($(CONFIG_CRYPTO), y) +KERNELPATHS += -I$(KERNEL_ROOT)/framework/security/crypto/include # +endif + +KERNELPATHS += -I$(KERNEL_ROOT)/resources/include # + +ifeq ($(CONFIG_RESOURCES_SPI), y) +KERNELPATHS +=-I$(KERNEL_ROOT)/resources/spi # + +ifeq ($(CONFIG_RESOURCES_SPI_SFUD),y) +KERNELPATHS += -I$(KERNEL_ROOT)/resources/spi/third_party_spi/SFUD/sfud/inc # +endif + +endif + +ifeq ($(CONFIG_TOOL_SHELL), y) +KERNELPATHS +=-I$(KERNEL_ROOT)/tool/shell/letter-shell \ + -I$(KERNEL_ROOT)/tool/shell/letter-shell/file_ext # +endif + + +ifeq ($(CONFIG_LIB_NEWLIB),y) +KERNELPATHS += -I$(KERNEL_ROOT)/lib/newlib/include # +endif + +ifeq ($(CONFIG_FS_LWEXT4),y) +KERNELPATHS += -I$(KERNEL_ROOT)/fs/lwext4/lwext4_submodule/blockdev/xiuos # +KERNELPATHS += -I$(KERNEL_ROOT)/fs/lwext4/lwext4_submodule/include # +KERNELPATHS += -I$(KERNEL_ROOT)/fs/lwext4/lwext4_submodule/include/misc +endif + + +ifeq ($(ARCH), risc-v) +KERNELPATHS +=-I$(KERNEL_ROOT)/arch/risc-v/shared +ifeq ($(MCU), k210) + KERNELPATHS +=-I$(KERNEL_ROOT)/arch/risc-v/k210 +endif +ifeq ($(MCU), FE310) + KERNELPATHS +=-I$(KERNEL_ROOT)/arch/risc-v/fe310 +endif +ifeq ($(MCU), GAP8) + KERNELPATHS +=-I$(KERNEL_ROOT)/arch/risc-v/gap8 +endif +ifeq ($(MCU), GD32VF103) + KERNELPATHS +=-I$(KERNEL_ROOT)/arch/risc-v/gd32vf103 +endif +endif + + +ifeq ($(ARCH), arm) +KERNELPATHS +=-I$(KERNEL_ROOT)/arch/arm/shared \ + -I$(KERNEL_ROOT)/lib/comlibc/common # +endif + + +KERNELPATHS += -I$(KERNEL_ROOT)/kernel/include # + + +COMPILE_KERNEL: + @$(eval CPPPATHS=$(KERNELPATHS)) + @for dir in $(SRC_KERNEL_DIR);do \ + $(MAKE) -C $$dir; \ + done + @cp link.mk build/Makefile + @$(MAKE) -C build COMPILE_TYPE="_kernel" TARGET=XiZi_$(BOARD)_kernel.elf LINK_FLAGS=LFLAGS + @rm build/Makefile build/make.obj + diff --git a/Ubiquitous/XiZi/resources/Kconfig b/Ubiquitous/XiZi/resources/Kconfig new file mode 100644 index 0000000..e41b96d --- /dev/null +++ b/Ubiquitous/XiZi/resources/Kconfig @@ -0,0 +1,165 @@ + +menuconfig RESOURCES_SERIAL + bool "Using SERIAL bus drivers" + default y + +if RESOURCES_SERIAL + config SERIAL_USING_DMA + bool "Enable SERIAL DMA mode" + default y + + config SERIAL_RB_BUFSZ + int "Set SERIAL RX buffer size" + default 128 +endif + +if BSP_USING_CAN + config RESOURCES_CAN + bool "Using CAN bus drivers" + default y +endif + +if BSP_USING_I2C + config RESOURCES_I2C + bool "Using I2C bus drivers" + default n +endif + +if BSP_USING_LCD + config RESOURCES_LCD + bool "Using LCD bus drivers" + default n +endif + +if BSP_USING_GPIO + config RESOURCES_PIN + bool "Using generic GPIO PIN bus drivers" + default n +endif + +if BSP_USING_RTC + menuconfig RESOURCES_RTC + bool "Using RTC bus drivers" + default n + + if RESOURCES_RTC + config USING_SOFT_RTC + bool "Using SOFT RTC" + default n + if USING_SOFT_RTC + config SOFT_RTC_BUS_NAME + string "soft rtc bus name" + default "srtc" + config SOFT_RTC_DRV_NAME + string "soft rtc bus driver name" + default "srtc_drv" + endif + endif +endif + +if BSP_USING_SDIO + config RESOURCES_SDIO + bool "Using SD/MMC card bus drivers" + default n +endif + +if BSP_USING_SPI + menuconfig RESOURCES_SPI + bool "Using SPI bus drivers" + default n + + if RESOURCES_SPI + menuconfig RESOURCES_SPI_SD + bool "Using SD/TF card driver with spi" + default n + if RESOURCES_SPI_SD + config SPI_SD_NAME + string "spi sd card 0 name" + default "sd0" + endif + + menuconfig RESOURCES_SPI_SFUD + bool "Using Serial Flash Universal Driver Lib" + default n + if RESOURCES_SPI_SFUD + config SFUD_USING_SFDP + bool "Using auto probe flash JEDEC SFDP parameter" + default y + + config SFUD_USING_FLASH_INFO_TABLE + bool "Using defined supported flash chip information table" + default n + + config SFUD_DEBUG_LOG + bool "Support SFUD debug log" + default y + endif + endif +endif + +if BSP_USING_HWTIMER + config RESOURCES_HWTIMER + bool "Using hardware timer bus drivers" + default n +endif + +if BSP_USING_TOUCH + config RESOURCES_TOUCH + bool "Using touch bus drivers" + default n +endif + +if BSP_USING_USB + menuconfig RESOURCES_USB + bool "Using USB bus drivers" + default n + + if RESOURCES_USB + config RESOURCES_USB_HOST + bool "Using USB host function" + default y + if RESOURCES_USB_HOST + config UDISK_MOUNTPOINT + string "Udisk mount dir" + default "/" + endif + config USBH_MSTORAGE + bool "usb use mass storage device" + default y + select FS_VFS + + config RESOURCES_USB_DEVICE + bool "Using USB device function" + default y + + if RESOURCES_USB_DEVICE + config USBD_THREAD_STACK_SZ + int "usb thread stack size" + default 4096 + endif + endif +endif + +if BSP_USING_LWIP + config RESOURCES_LWIP + bool "Using LwIP bus drivers" + default n +endif + +if BSP_USING_WDT + config RESOURCES_WDT + bool "Using Watch Dog bus drivers" + default n +endif + +if BSP_USING_ADC + config RESOURCES_ADC + bool "Using ADC bus drivers" + default n +endif + +if BSP_USING_DAC + config RESOURCES_DAC + bool "Using DAC bus drivers" + default n +endif diff --git a/Ubiquitous/XiZi/resources/Makefile b/Ubiquitous/XiZi/resources/Makefile new file mode 100644 index 0000000..3c10a79 --- /dev/null +++ b/Ubiquitous/XiZi/resources/Makefile @@ -0,0 +1,68 @@ +SRC_DIR := +SRC_FILES += bus.c + +ifeq ($(CONFIG_KERNEL_DEVICE),y) + SRC_FILES += device.c +endif + +ifeq ($(CONFIG_RESOURCES_CAN),y) + SRC_DIR += can +endif + +ifeq ($(CONFIG_RESOURCES_I2C),y) + SRC_DIR += i2c +endif + +ifeq ($(CONFIG_RESOURCES_LCD),y) + SRC_DIR += lcd +endif + +ifeq ($(CONFIG_RESOURCES_PIN),y) + SRC_DIR += pin +endif + +ifeq ($(CONFIG_RESOURCES_RTC),y) + SRC_DIR += rtc +endif + +ifeq ($(CONFIG_RESOURCES_SDIO),y) + SRC_DIR += sdio +endif + +ifeq ($(CONFIG_RESOURCES_SERIAL),y) + SRC_DIR += serial +endif + +ifeq ($(CONFIG_RESOURCES_SPI),y) + SRC_DIR += spi +endif + +ifeq ($(CONFIG_RESOURCES_HWTIMER),y) + SRC_DIR += timer +endif + +ifeq ($(CONFIG_RESOURCES_TOUCH),y) + SRC_DIR += touch +endif + +ifeq ($(CONFIG_RESOURCES_USB),y) + SRC_DIR += usb +endif + +ifeq ($(CONFIG_RESOURCES_LWIP),y) + SRC_DIR += ethernet +endif + +ifeq ($(CONFIG_RESOURCES_WDT),y) + SRC_DIR += watchdog +endif + +ifeq ($(CONFIG_RESOURCES_ADC),y) + SRC_DIR += adc +endif + +ifeq ($(CONFIG_RESOURCES_DAC),y) + SRC_DIR += dac +endif + +include $(KERNEL_ROOT)/compiler.mk diff --git a/Ubiquitous/XiZi/resources/adc/Makefile b/Ubiquitous/XiZi/resources/adc/Makefile new file mode 100644 index 0000000..32f1317 --- /dev/null +++ b/Ubiquitous/XiZi/resources/adc/Makefile @@ -0,0 +1,3 @@ +SRC_FILES += dev_adc.c drv_adc.c bus_adc.c + +include $(KERNEL_ROOT)/compiler.mk diff --git a/Ubiquitous/XiZi/resources/adc/bus_adc.c b/Ubiquitous/XiZi/resources/adc/bus_adc.c new file mode 100644 index 0000000..1ec0052 --- /dev/null +++ b/Ubiquitous/XiZi/resources/adc/bus_adc.c @@ -0,0 +1,123 @@ +/* +* Copyright (c) 2020 AIIT XUOS Lab +* XiUOS is licensed under Mulan PSL v2. +* You can use this software according to the terms and conditions of the Mulan PSL v2. +* You may obtain a copy of Mulan PSL v2 at: +* http://license.coscl.org.cn/MulanPSL2 +* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, +* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, +* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. +* See the Mulan PSL v2 for more details. +*/ + +/** +* @file bus_adc.c +* @brief register adc bus function using bus driver framework +* @version 1.1 +* @author AIIT XUOS Lab +* @date 2021-12-28 +*/ + +#include +#include + +/*Register the ADC BUS*/ +int AdcBusInit(struct AdcBus *adc_bus, const char *bus_name) +{ + NULL_PARAM_CHECK(adc_bus); + NULL_PARAM_CHECK(bus_name); + + x_err_t ret = EOK; + + if (BUS_INSTALL != adc_bus->bus.bus_state) { + strncpy(adc_bus->bus.bus_name, bus_name, NAME_NUM_MAX); + + adc_bus->bus.bus_type = TYPE_ADC_BUS; + adc_bus->bus.bus_state = BUS_INSTALL; + adc_bus->bus.private_data = adc_bus->private_data; + + ret = BusRegister(&adc_bus->bus); + if (EOK != ret) { + KPrintf("AdcBusInit BusRegister error %u\n", ret); + return ret; + } + } else { + KPrintf("AdcBusInit BusRegister bus has been register state%u\n", adc_bus->bus.bus_state); + } + + return ret; +} + +/*Register the ADC Driver*/ +int AdcDriverInit(struct AdcDriver *adc_driver, const char *driver_name) +{ + NULL_PARAM_CHECK(adc_driver); + NULL_PARAM_CHECK(driver_name); + + x_err_t ret = EOK; + + if (DRV_INSTALL != adc_driver->driver.driver_state) { + adc_driver->driver.driver_type = TYPE_ADC_DRV; + adc_driver->driver.driver_state = DRV_INSTALL; + + strncpy(adc_driver->driver.drv_name, driver_name, NAME_NUM_MAX); + + adc_driver->driver.configure = adc_driver->configure; + adc_driver->driver.private_data = adc_driver->private_data; + + ret = AdcDriverRegister(&adc_driver->driver); + if (EOK != ret) { + KPrintf("AdcDriverInit DriverRegister error %u\n", ret); + return ret; + } + } else { + KPrintf("AdcDriverInit DriverRegister driver has been register state%u\n", adc_driver->driver.driver_state); + } + + return ret; +} + +/*Release the ADC device*/ +int AdcReleaseBus(struct AdcBus *adc_bus) +{ + NULL_PARAM_CHECK(adc_bus); + + return BusRelease(&adc_bus->bus); +} + +/*Register the ADC Driver to the ADC BUS*/ +int AdcDriverAttachToBus(const char *drv_name, const char *bus_name) +{ + NULL_PARAM_CHECK(drv_name); + NULL_PARAM_CHECK(bus_name); + + x_err_t ret = EOK; + + struct Bus *bus; + struct Driver *driver; + + bus = BusFind(bus_name); + if (NONE == bus) { + KPrintf("AdcDriverAttachToBus find adc bus error!name %s\n", bus_name); + return ERROR; + } + + if (TYPE_ADC_BUS == bus->bus_type) { + driver = AdcDriverFind(drv_name, TYPE_ADC_DRV); + if (NONE == driver) { + KPrintf("AdcDriverAttachToBus find adc driver error!name %s\n", drv_name); + return ERROR; + } + + if (TYPE_ADC_DRV == driver->driver_type) { + ret = DriverRegisterToBus(bus, driver); + if (EOK != ret) { + KPrintf("AdcDriverAttachToBus DriverRegisterToBus error %u\n", ret); + return ERROR; + } + } + } + + return ret; +} + diff --git a/Ubiquitous/XiZi/resources/adc/dev_adc.c b/Ubiquitous/XiZi/resources/adc/dev_adc.c new file mode 100644 index 0000000..8921a95 --- /dev/null +++ b/Ubiquitous/XiZi/resources/adc/dev_adc.c @@ -0,0 +1,120 @@ +/* +* Copyright (c) 2020 AIIT XUOS Lab +* XiUOS is licensed under Mulan PSL v2. +* You can use this software according to the terms and conditions of the Mulan PSL v2. +* You may obtain a copy of Mulan PSL v2 at: +* http://license.coscl.org.cn/MulanPSL2 +* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, +* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, +* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. +* See the Mulan PSL v2 for more details. +*/ + +/** +* @file dev_adc.c +* @brief register adc dev function using bus driver framework +* @version 1.1 +* @author AIIT XUOS Lab +* @date 2021-12-28 +*/ + +#include +#include + +static DoubleLinklistType adcdev_linklist; + +/*Create the ADC device linklist*/ +static void AdcDeviceLinkInit() +{ + InitDoubleLinkList(&adcdev_linklist); +} + +/*Find the register ADC device*/ +HardwareDevType AdcDeviceFind(const char *dev_name, enum DevType dev_type) +{ + NULL_PARAM_CHECK(dev_name); + + struct HardwareDev *device = NONE; + + DoubleLinklistType *node = NONE; + DoubleLinklistType *head = &adcdev_linklist; + for (node = head->node_next; node != head; node = node->node_next) { + device = SYS_DOUBLE_LINKLIST_ENTRY(node, struct HardwareDev, dev_link); + if ((!strcmp(device->dev_name, dev_name)) && (dev_type == device->dev_type)) { + return device; + } + } + + KPrintf("AdcDeviceFind adcnot find the %s device.return NULL\n", dev_name); + return NONE; +} + +/*Register the ADC device*/ +int AdcDeviceRegister(struct AdcHardwareDevice *adc_device, void *adc_param, const char *device_name) +{ + NULL_PARAM_CHECK(adc_device); + NULL_PARAM_CHECK(device_name); + + x_err_t ret = EOK; + static x_bool dev_link_flag = RET_FALSE; + + if (!dev_link_flag) { + AdcDeviceLinkInit(); + dev_link_flag = RET_TRUE; + } + + if (DEV_INSTALL != adc_device->haldev.dev_state) { + strncpy(adc_device->haldev.dev_name, device_name, NAME_NUM_MAX); + adc_device->haldev.dev_type = TYPE_ADC_DEV; + adc_device->haldev.dev_state = DEV_INSTALL; + + adc_device->haldev.dev_done = (struct HalDevDone *)adc_device->adc_dev_done; + + adc_device->haldev.private_data = adc_param; + + DoubleLinkListInsertNodeAfter(&adcdev_linklist, &(adc_device->haldev.dev_link)); + } else { + KPrintf("AdcDeviceRegister device has been register state%u\n", adc_device->haldev.dev_state); + } + + return ret; +} + +/*Register the ADC Device to the ADC BUS*/ +int AdcDeviceAttachToBus(const char *dev_name, const char *bus_name) +{ + NULL_PARAM_CHECK(dev_name); + NULL_PARAM_CHECK(bus_name); + + x_err_t ret = EOK; + + struct Bus *bus; + struct HardwareDev *device; + + bus = BusFind(bus_name); + if (NONE == bus) { + KPrintf("AdcDeviceAttachToBus find adc bus error!name %s\n", bus_name); + return ERROR; + } + + if (TYPE_ADC_BUS == bus->bus_type) { + device = AdcDeviceFind(dev_name, TYPE_ADC_DEV); + + if (NONE == device) { + KPrintf("AdcDeviceAttachToBus find adc device error!name %s\n", dev_name); + return ERROR; + } + + if (TYPE_ADC_DEV == device->dev_type) { + ret = DeviceRegisterToBus(bus, device); + + if (EOK != ret) { + KPrintf("AdcDeviceAttachToBus DeviceRegisterToBus error %u\n", ret); + return ERROR; + } + } + } + + return EOK; +} + diff --git a/Ubiquitous/XiZi/resources/adc/drv_adc.c b/Ubiquitous/XiZi/resources/adc/drv_adc.c new file mode 100644 index 0000000..7c1c330 --- /dev/null +++ b/Ubiquitous/XiZi/resources/adc/drv_adc.c @@ -0,0 +1,70 @@ +/* +* Copyright (c) 2020 AIIT XUOS Lab +* XiUOS is licensed under Mulan PSL v2. +* You can use this software according to the terms and conditions of the Mulan PSL v2. +* You may obtain a copy of Mulan PSL v2 at: +* http://license.coscl.org.cn/MulanPSL2 +* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, +* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, +* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. +* See the Mulan PSL v2 for more details. +*/ + +/** +* @file drv_adc.c +* @brief register adc drv function using bus driver framework +* @version 1.1 +* @author AIIT XUOS Lab +* @date 2021-12-28 +*/ + +#include +#include + +static DoubleLinklistType adcdrv_linklist; + +/*Create the driver linklist*/ +static void AdcDrvLinkInit() +{ + InitDoubleLinkList(&adcdrv_linklist); +} + +/*Find the regiter driver*/ +DriverType AdcDriverFind(const char *drv_name, enum DriverType_e drv_type) +{ + NULL_PARAM_CHECK(drv_name); + + struct Driver *driver = NONE; + + DoubleLinklistType *node = NONE; + DoubleLinklistType *head = &adcdrv_linklist; + + for (node = head->node_next; node != head; node = node->node_next) { + driver = SYS_DOUBLE_LINKLIST_ENTRY(node, struct Driver, driver_link); + if ((!strcmp(driver->drv_name, drv_name)) && (drv_type == driver->driver_type)) { + return driver; + } + } + + KPrintf("AdcDriverFind cannot find the %s driver.return NULL\n", drv_name); + return NONE; +} + +/*Register the Driver, manage with the double linklist*/ +int AdcDriverRegister(struct Driver *driver) +{ + NULL_PARAM_CHECK(driver); + + x_err_t ret = EOK; + static x_bool driver_link_flag = RET_FALSE; + + if (!driver_link_flag) { + AdcDrvLinkInit(); + driver_link_flag = RET_TRUE; + } + + DoubleLinkListInsertNodeAfter(&adcdrv_linklist, &(driver->driver_link)); + + return ret; +} + diff --git a/Ubiquitous/XiZi/resources/bus.c b/Ubiquitous/XiZi/resources/bus.c new file mode 100644 index 0000000..31f87eb --- /dev/null +++ b/Ubiquitous/XiZi/resources/bus.c @@ -0,0 +1,432 @@ +/* +* Copyright (c) 2020 AIIT XUOS Lab +* XiUOS is licensed under Mulan PSL v2. +* You can use this software according to the terms and conditions of the Mulan PSL v2. +* You may obtain a copy of Mulan PSL v2 at: +* http://license.coscl.org.cn/MulanPSL2 +* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, +* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, +* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. +* See the Mulan PSL v2 for more details. +*/ + +/** +* @file bus.c +* @brief Support bus driver framework provide bus API version 1.0 +* @author AIIT XUOS Lab +* @date 2021-04-24 +*/ + +#include +#include + +DoubleLinklistType bus_linklist; + +/*Create the bus linklist*/ +static void BusLinkInit(struct Bus *bus) +{ + static uint8 bus_link_flag = RET_FALSE; + + if(!bus_link_flag) { + InitDoubleLinkList(&bus_linklist); + bus_link_flag = RET_TRUE; + bus->bus_link_flag = RET_TRUE; + } + + /*Create the driver of the bus linklist*/ + if(!bus->bus_drvlink_flag) { + InitDoubleLinkList(&bus->bus_drvlink); + bus->bus_drvlink_flag = RET_TRUE; + } + + /*Create the hardware device of the bus linklist*/ + if(!bus->bus_devlink_flag) { + InitDoubleLinkList(&bus->bus_devlink); + bus->bus_devlink_flag = RET_TRUE; + } +} + +static int BusMatchDrvDev(struct Driver *driver, struct HardwareDev *device) +{ + NULL_PARAM_CHECK(driver); + NULL_PARAM_CHECK(device); + + if(!strncmp(driver->owner_bus->bus_name, device->owner_bus->bus_name, NAME_NUM_MAX)) { + //KPrintf("BusMatchDrvDev match successfully, bus name %s\n", driver->owner_bus->bus_name); + + driver->private_data = device->private_data;//driver get the device param + device->owner_bus->owner_driver = driver; + driver->owner_bus->owner_haldev = device; + + return EOK; + } + + return ERROR; +} + +/** +* @Description: support to obtain bus for a certain dev if necessary, then configure and init its drv +* @param bus - bus pointer +* @param dev - dev pointer +* @param drv_name - drv name +* @param configure_info - BusConfigureInfo pointer +* @return successful:EOK,failed:ERROR +*/ +int DeviceObtainBus(struct Bus *bus, struct HardwareDev *dev, const char *drv_name, struct BusConfigureInfo *configure_info) +{ + NULL_PARAM_CHECK(bus); + NULL_PARAM_CHECK(dev); + + int32 ret = EOK; + + ret = KMutexObtain(bus->bus_lock, WAITING_FOREVER); + if(EOK != ret) { + KPrintf("DevObtainBus bus_lock error %d!\n", ret); + return ret; + } + + if(bus->owner_haldev != dev) { + struct Driver *drv = BusFindDriver(bus, drv_name); + + configure_info->configure_cmd = OPE_CFG; + drv->configure(drv, configure_info); + + configure_info->configure_cmd = OPE_INT; + drv->configure(drv, configure_info); + + bus->owner_haldev = dev; + } + + return ret; +} + +/** +* @Description: support to register bus pointer with linklist +* @param bus - bus pointer +* @return successful:EOK,failed:NONE +*/ +int BusRegister(struct Bus *bus) +{ + x_err_t ret = EOK; + NULL_PARAM_CHECK(bus); + + bus->match = BusMatchDrvDev; + + BusLinkInit(bus); + + bus->bus_lock = KMutexCreate(); + + DoubleLinkListInsertNodeAfter(&bus_linklist, &(bus->bus_link)); + + return ret; +} + +/** +* @Description: support to release bus pointer in linklist +* @param bus - bus pointer +* @return successful:EOK,failed:NONE +*/ +int BusRelease(struct Bus *bus) +{ + NULL_PARAM_CHECK(bus); + + KMutexAbandon(bus->bus_lock); + + bus->bus_cnt = 0; + bus->driver_cnt = 0; + bus->haldev_cnt = 0; + + bus->bus_link_flag = RET_FALSE; + bus->bus_drvlink_flag = RET_FALSE; + bus->bus_devlink_flag = RET_FALSE; + + return EOK; +} + +/** +* @Description: support to unregister bus pointer and delete its linklist node +* @param bus - bus pointer +* @return successful:EOK,failed:NONE +*/ +int BusUnregister(struct Bus *bus) +{ + NULL_PARAM_CHECK(bus); + + bus->bus_cnt--; + + DoubleLinkListRmNode(&(bus->bus_link)); + + return EOK; +} + +/** +* @Description: support to register driver pointer to bus pointer +* @param bus - bus pointer +* @param driver - driver pointer +* @return successful:EOK,failed:NONE +*/ +int DriverRegisterToBus(struct Bus *bus, struct Driver *driver) +{ + NULL_PARAM_CHECK(bus); + NULL_PARAM_CHECK(driver); + + driver->owner_bus = bus; + bus->driver_cnt++; + + DoubleLinkListInsertNodeAfter(&bus->bus_drvlink, &(driver->driver_link)); + + return EOK; +} + +/** +* @Description: support to register dev pointer to bus pointer +* @param bus - bus pointer +* @param device - device pointer +* @return successful:EOK,failed:NONE +*/ +int DeviceRegisterToBus(struct Bus *bus, struct HardwareDev *device) +{ + NULL_PARAM_CHECK(bus); + NULL_PARAM_CHECK(device); + + device->owner_bus = bus; + bus->haldev_cnt++; + + DoubleLinkListInsertNodeAfter(&bus->bus_devlink, &(device->dev_link)); + + return EOK; +} + +/** +* @Description: support to delete driver pointer from bus pointer +* @param bus - bus pointer +* @param driver - driver pointer +* @return successful:EOK,failed:NONE +*/ +int DriverDeleteFromBus(struct Bus *bus, struct Driver *driver) +{ + NULL_PARAM_CHECK(bus); + NULL_PARAM_CHECK(driver); + + bus->driver_cnt--; + + DoubleLinkListRmNode(&(driver->driver_link)); + + free(driver); + + return EOK; +} + +/** +* @Description: support to delete dev pointer from bus pointer +* @param bus - bus pointer +* @param device - device pointer +* @return successful:EOK,failed:NONE +*/ +int DeviceDeleteFromBus(struct Bus *bus, struct HardwareDev *device) +{ + NULL_PARAM_CHECK(bus); + NULL_PARAM_CHECK(device); + + bus->haldev_cnt--; + + DoubleLinkListRmNode(&(device->dev_link)); + + free(device); + + return EOK; +} + +/** +* @Description: support to find bus pointer by bus name +* @param bus_name - bus name +* @return successful:bus pointer,failed:NONE +*/ +BusType BusFind(const char *bus_name) +{ + struct Bus *bus = NONE; + + DoubleLinklistType *node = NONE; + DoubleLinklistType *head = &bus_linklist; + + for (node = head->node_next; node != head; node = node->node_next) + { + bus = SYS_DOUBLE_LINKLIST_ENTRY(node, struct Bus, bus_link); + if(!strcmp(bus->bus_name, bus_name)) { + return bus; + } + } + + KPrintf("BusFind cannot find the %s bus.return NULL\n", bus_name); + return NONE; +} + +/** +* @Description: support to find driver pointer of certain bus by driver name +* @param bus - bus pointer +* @param driver_name - driver name +* @return successful:EOK,failed:NONE +*/ +DriverType BusFindDriver(struct Bus *bus, const char *driver_name) +{ + NULL_PARAM_CHECK(bus); + struct Driver *driver = NONE; + + DoubleLinklistType *node = NONE; + DoubleLinklistType *head = &bus->bus_drvlink; + + for (node = head->node_next; node != head; node = node->node_next) + { + driver = SYS_DOUBLE_LINKLIST_ENTRY(node, struct Driver, driver_link); + if(!strcmp(driver->drv_name, driver_name)) { + return driver; + } + } + + KPrintf("BusFindDriver cannot find the %s driver.return NULL\n", driver_name); + return NONE; +} + +/** +* @Description: support to find device pointer of certain bus by device name +* @param bus - bus pointer +* @param device_name - device name +* @return successful:EOK,failed:NONE +*/ +HardwareDevType BusFindDevice(struct Bus *bus, const char *device_name) +{ + NULL_PARAM_CHECK(bus); + struct HardwareDev *device = NONE; + + DoubleLinklistType *node = NONE; + DoubleLinklistType *head = &bus->bus_devlink; + + for (node = head->node_next; node != head; node = node->node_next) + { + device = SYS_DOUBLE_LINKLIST_ENTRY(node, struct HardwareDev, dev_link); + + if(!strcmp(device->dev_name, device_name)) { + return device; + } + } + + KPrintf("BusFindDevice cannot find the %s device.return NULL\n", device_name); + return NONE; +} + +/** +* @Description: support to set dev receive function callback +* @param dev - dev pointer +* @param dev_recv_callback - callback function +* @return successful:EOK,failed:ERROR +*/ +uint32 BusDevRecvCallback(struct HardwareDev *dev, int (*dev_recv_callback) (void *dev, x_size_t length)) +{ + NULL_PARAM_CHECK(dev ); + + dev->dev_recv_callback = dev_recv_callback; + + return EOK; +} + +/** +* @Description: support to open dev +* @param dev - dev pointer +* @return successful:EOK,failed:ERROR +*/ +uint32 BusDevOpen(struct HardwareDev *dev) +{ + NULL_PARAM_CHECK(dev); + + x_err_t ret = EOK; + + if (dev->dev_done->open) { + ret = dev->dev_done->open(dev); + if(ret) { + KPrintf("BusDevOpen error ret %u\n", ret); + return ERROR; + } + } + + return ret; +} + +/** +* @Description: support to close dev +* @param dev - dev pointer +* @return successful:EOK,failed:ERROR +*/ +uint32 BusDevClose(struct HardwareDev *dev) +{ + NULL_PARAM_CHECK(dev); + + x_err_t ret = EOK; + + if (dev->dev_done->close) { + ret = dev->dev_done->close(dev); + if(ret) { + KPrintf("BusDevClose error ret %u\n", ret); + return ERROR; + } + } + + return ret; +} + +/** +* @Description: support to write data to dev +* @param dev - dev pointer +* @param write_param - BusBlockWriteParam +* @return successful:EOK,failed:NONE +*/ +uint32 BusDevWriteData(struct HardwareDev *dev, struct BusBlockWriteParam *write_param) +{ + NULL_PARAM_CHECK(dev); + + if (dev->dev_done->write) { + return dev->dev_done->write(dev, write_param); + } + + return EOK; +} + +/** +* @Description: support to read data from dev +* @param dev - dev pointer +* @param read_param - BusBlockReadParam +* @return successful:EOK,failed:NONE +*/ +uint32 BusDevReadData(struct HardwareDev *dev, struct BusBlockReadParam *read_param) +{ + NULL_PARAM_CHECK(dev); + + if (dev->dev_done->read) { + return dev->dev_done->read(dev, read_param); + } + + return EOK; +} + +/** +* @Description: support to configure drv, include OPE_CFG and OPE_INT +* @param drv - drv pointer +* @param configure_info - BusConfigureInfo +* @return successful:EOK,failed:NONE +*/ +uint32 BusDrvConfigure(struct Driver *drv, struct BusConfigureInfo *configure_info) +{ + NULL_PARAM_CHECK(drv); + NULL_PARAM_CHECK(configure_info); + + x_err_t ret = EOK; + + if (drv->configure) { + ret = drv->configure(drv, configure_info); + if(ret) { + KPrintf("BusDrvCfg error, ret %u\n", ret); + return ERROR; + } + } + + return ret; +} diff --git a/Ubiquitous/XiZi/resources/can/Makefile b/Ubiquitous/XiZi/resources/can/Makefile new file mode 100644 index 0000000..b001764 --- /dev/null +++ b/Ubiquitous/XiZi/resources/can/Makefile @@ -0,0 +1,5 @@ +SRC_FILES += dev_can.c drv_can.c bus_can.c + + + +include $(KERNEL_ROOT)/compiler.mk diff --git a/Ubiquitous/XiZi/resources/can/bus_can.c b/Ubiquitous/XiZi/resources/can/bus_can.c new file mode 100644 index 0000000..c9e4f44 --- /dev/null +++ b/Ubiquitous/XiZi/resources/can/bus_can.c @@ -0,0 +1,122 @@ +/* +* Copyright (c) 2020 AIIT XUOS Lab +* XiUOS is licensed under Mulan PSL v2. +* You can use this software according to the terms and conditions of the Mulan PSL v2. +* You may obtain a copy of Mulan PSL v2 at: +* http://license.coscl.org.cn/MulanPSL2 +* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, +* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, +* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. +* See the Mulan PSL v2 for more details. +*/ + +/** +* @file bus_can.c +* @brief register can bus function using bus driver framework +* @version 1.0 +* @author AIIT XUOS Lab +* @date 2021-04-24 +*/ + +#include +#include + +/*Register the CAN BUS*/ +int CanBusInit(struct CanBus *can_bus, const char *bus_name) +{ + NULL_PARAM_CHECK(can_bus); + NULL_PARAM_CHECK(bus_name); + + x_err_t ret = EOK; + + if (BUS_INSTALL != can_bus->bus.bus_state) { + strncpy(can_bus->bus.bus_name, bus_name, NAME_NUM_MAX); + + can_bus->bus.bus_type = TYPE_CAN_BUS; + can_bus->bus.bus_state = BUS_INSTALL; + can_bus->bus.private_data = can_bus->private_data; + + ret = BusRegister(&can_bus->bus); + if (EOK != ret) { + KPrintf("CanBusInit BusRegister error %u\n", ret); + return ret; + } + } else { + KPrintf("CanBusInit BusRegister bus has been register state%u\n", can_bus->bus.bus_state); + } + + return ret; +} + +/*Register the CAN Driver*/ +int CanDriverInit(struct CanDriver *can_driver, const char *driver_name) +{ + NULL_PARAM_CHECK(can_driver); + NULL_PARAM_CHECK(driver_name); + + x_err_t ret = EOK; + + if (DRV_INSTALL != can_driver->driver.driver_state) { + can_driver->driver.driver_type = TYPE_CAN_DRV; + can_driver->driver.driver_state = DRV_INSTALL; + + strncpy(can_driver->driver.drv_name, driver_name, NAME_NUM_MAX); + + can_driver->driver.configure = can_driver->configure; + can_driver->driver.private_data = can_driver->private_data; + + ret = CanDriverRegister(&can_driver->driver); + if (EOK != ret) { + KPrintf("CanDriverInit DriverRegister error %u\n", ret); + return ret; + } + } else { + KPrintf("CanDriverInit DriverRegister driver has been register state%u\n", can_driver->driver.driver_state); + } + + return ret; +} + +/*Release the CAN device*/ +int CanReleaseBus(struct CanBus *can_bus) +{ + NULL_PARAM_CHECK(can_bus); + + return BusRelease(&can_bus->bus); +} + +/*Register the CAN Driver to the CAN BUS*/ +int CanDriverAttachToBus(const char *drv_name, const char *bus_name) +{ + NULL_PARAM_CHECK(drv_name); + NULL_PARAM_CHECK(bus_name); + + x_err_t ret = EOK; + + struct Bus *bus; + struct Driver *driver; + + bus = BusFind(bus_name); + if (NONE == bus) { + KPrintf("CanDriverAttachToBus find can bus error!name %s\n", bus_name); + return ERROR; + } + + if (TYPE_CAN_BUS == bus->bus_type) { + driver = CanDriverFind(drv_name, TYPE_CAN_DRV); + if (NONE == driver) { + KPrintf("CanDriverAttachToBus find can driver error!name %s\n", drv_name); + return ERROR; + } + + if (TYPE_CAN_DRV == driver->driver_type) { + ret = DriverRegisterToBus(bus, driver); + if (EOK != ret) { + KPrintf("CanDriverAttachToBus DriverRegisterToBus error %u\n", ret); + return ERROR; + } + } + } + + return ret; +} diff --git a/Ubiquitous/XiZi/resources/can/dev_can.c b/Ubiquitous/XiZi/resources/can/dev_can.c new file mode 100644 index 0000000..1558b11 --- /dev/null +++ b/Ubiquitous/XiZi/resources/can/dev_can.c @@ -0,0 +1,119 @@ +/* +* Copyright (c) 2020 AIIT XUOS Lab +* XiUOS is licensed under Mulan PSL v2. +* You can use this software according to the terms and conditions of the Mulan PSL v2. +* You may obtain a copy of Mulan PSL v2 at: +* http://license.coscl.org.cn/MulanPSL2 +* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, +* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, +* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. +* See the Mulan PSL v2 for more details. +*/ + +/** +* @file dev_can.c +* @brief register can dev function using bus driver framework +* @version 1.0 +* @author AIIT XUOS Lab +* @date 2021-04-24 +*/ + +#include +#include + +static DoubleLinklistType candev_linklist; + +/*Create the CAN device linklist*/ +static void CanDeviceLinkInit() +{ + InitDoubleLinkList(&candev_linklist); +} + +/*Find the register CAN device*/ +HardwareDevType CanDeviceFind(const char *dev_name, enum DevType dev_type) +{ + NULL_PARAM_CHECK(dev_name); + + struct HardwareDev *device = NONE; + + DoubleLinklistType *node = NONE; + DoubleLinklistType *head = &candev_linklist; + for (node = head->node_next; node != head; node = node->node_next) { + device = SYS_DOUBLE_LINKLIST_ENTRY(node, struct HardwareDev, dev_link); + if ((!strcmp(device->dev_name, dev_name)) && (dev_type == device->dev_type)) { + return device; + } + } + + KPrintf("CanDeviceFind cannot find the %s device.return NULL\n", dev_name); + return NONE; +} + +/*Register the CAN device*/ +int CanDeviceRegister(struct CanHardwareDevice *can_device, void *can_param, const char *device_name) +{ + NULL_PARAM_CHECK(can_device); + NULL_PARAM_CHECK(device_name); + + x_err_t ret = EOK; + static x_bool dev_link_flag = RET_FALSE; + + if (!dev_link_flag) { + CanDeviceLinkInit(); + dev_link_flag = RET_TRUE; + } + + if (DEV_INSTALL != can_device->haldev.dev_state) { + strncpy(can_device->haldev.dev_name, device_name, NAME_NUM_MAX); + can_device->haldev.dev_type = TYPE_CAN_DEV; + can_device->haldev.dev_state = DEV_INSTALL; + + can_device->haldev.dev_done = (struct HalDevDone *)can_device->dev_done; + + can_device->haldev.private_data = can_param; + + DoubleLinkListInsertNodeAfter(&candev_linklist, &(can_device->haldev.dev_link)); + } else { + KPrintf("CanDeviceRegister device has been register state%u\n", can_device->haldev.dev_state); + } + + return ret; +} + +/*Register the CAN Device to the CAN BUS*/ +int CanDeviceAttachToBus(const char *dev_name, const char *bus_name) +{ + NULL_PARAM_CHECK(dev_name); + NULL_PARAM_CHECK(bus_name); + + x_err_t ret = EOK; + + struct Bus *bus; + struct HardwareDev *device; + + bus = BusFind(bus_name); + if (NONE == bus) { + KPrintf("CanDeviceAttachToBus find can bus error!name %s\n", bus_name); + return ERROR; + } + + if (TYPE_CAN_BUS == bus->bus_type) { + device = CanDeviceFind(dev_name, TYPE_CAN_DEV); + + if (NONE == device) { + KPrintf("CanDeviceAttachToBus find can device error!name %s\n", dev_name); + return ERROR; + } + + if (TYPE_CAN_DEV == device->dev_type) { + ret = DeviceRegisterToBus(bus, device); + + if (EOK != ret) { + KPrintf("CanDeviceAttachToBus DeviceRegisterToBus error %u\n", ret); + return ERROR; + } + } + } + + return EOK; +} diff --git a/Ubiquitous/XiZi/resources/can/drv_can.c b/Ubiquitous/XiZi/resources/can/drv_can.c new file mode 100644 index 0000000..de7859f --- /dev/null +++ b/Ubiquitous/XiZi/resources/can/drv_can.c @@ -0,0 +1,69 @@ +/* +* Copyright (c) 2020 AIIT XUOS Lab +* XiUOS is licensed under Mulan PSL v2. +* You can use this software according to the terms and conditions of the Mulan PSL v2. +* You may obtain a copy of Mulan PSL v2 at: +* http://license.coscl.org.cn/MulanPSL2 +* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, +* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, +* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. +* See the Mulan PSL v2 for more details. +*/ + +/** +* @file drv_can.c +* @brief register can drv function using bus driver framework +* @version 1.0 +* @author AIIT XUOS Lab +* @date 2021-04-24 +*/ + +#include +#include + +static DoubleLinklistType candrv_linklist; + +/*Create the driver linklist*/ +static void CanDrvLinkInit() +{ + InitDoubleLinkList(&candrv_linklist); +} + +/*Find the regiter driver*/ +DriverType CanDriverFind(const char *drv_name, enum DriverType_e drv_type) +{ + NULL_PARAM_CHECK(drv_name); + + struct Driver *driver = NONE; + + DoubleLinklistType *node = NONE; + DoubleLinklistType *head = &candrv_linklist; + + for (node = head->node_next; node != head; node = node->node_next) { + driver = SYS_DOUBLE_LINKLIST_ENTRY(node, struct Driver, driver_link); + if ((!strcmp(driver->drv_name, drv_name)) && (drv_type == driver->driver_type)) { + return driver; + } + } + + KPrintf("CanDriverFind cannot find the %s driver.return NULL\n", drv_name); + return NONE; +} + +/*Register the Driver, manage with the double linklist*/ +int CanDriverRegister(struct Driver *driver) +{ + NULL_PARAM_CHECK(driver); + + x_err_t ret = EOK; + static x_bool driver_link_flag = RET_FALSE; + + if (!driver_link_flag) { + CanDrvLinkInit(); + driver_link_flag = RET_TRUE; + } + + DoubleLinkListInsertNodeAfter(&candrv_linklist, &(driver->driver_link)); + + return ret; +} diff --git a/Ubiquitous/XiZi/resources/dac/Makefile b/Ubiquitous/XiZi/resources/dac/Makefile new file mode 100644 index 0000000..7b5fac0 --- /dev/null +++ b/Ubiquitous/XiZi/resources/dac/Makefile @@ -0,0 +1,3 @@ +SRC_FILES += dev_dac.c drv_dac.c bus_dac.c + +include $(KERNEL_ROOT)/compiler.mk diff --git a/Ubiquitous/XiZi/resources/dac/bus_dac.c b/Ubiquitous/XiZi/resources/dac/bus_dac.c new file mode 100644 index 0000000..ef29455 --- /dev/null +++ b/Ubiquitous/XiZi/resources/dac/bus_dac.c @@ -0,0 +1,122 @@ +/* +* Copyright (c) 2020 AIIT XUOS Lab +* XiUOS is licensed under Mulan PSL v2. +* You can use this software according to the terms and conditions of the Mulan PSL v2. +* You may obtain a copy of Mulan PSL v2 at: +* http://license.coscl.org.cn/MulanPSL2 +* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, +* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, +* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. +* See the Mulan PSL v2 for more details. +*/ + +/** +* @file bus_dac.c +* @brief register dac bus function using bus driver framework +* @version 2.0 +* @author AIIT XUOS Lab +* @date 2022-1-11 +*/ + +#include +#include + +/*Register the DAC BUS*/ +int DacBusInit(struct DacBus *dac_bus, const char *bus_name) +{ + NULL_PARAM_CHECK(dac_bus); + NULL_PARAM_CHECK(bus_name); + + x_err_t ret = EOK; + + if (BUS_INSTALL != dac_bus->bus.bus_state) { + strncpy(dac_bus->bus.bus_name, bus_name, NAME_NUM_MAX); + + dac_bus->bus.bus_type = TYPE_DAC_BUS; + dac_bus->bus.bus_state = BUS_INSTALL; + dac_bus->bus.private_data = dac_bus->private_data; + + ret = BusRegister(&dac_bus->bus); + if (EOK != ret) { + KPrintf("DacBusInit BusRegister error %u\n", ret); + return ret; + } + } else { + KPrintf("DacBusInit BusRegister bus has been register state%u\n", dac_bus->bus.bus_state); + } + + return ret; +} + +/*Register the DAC Driver*/ +int DacDriverInit(struct DacDriver *dac_driver, const char *driver_name) +{ + NULL_PARAM_CHECK(dac_driver); + NULL_PARAM_CHECK(driver_name); + + x_err_t ret = EOK; + + if (DRV_INSTALL != dac_driver->driver.driver_state) { + dac_driver->driver.driver_type = TYPE_DAC_DRV; + dac_driver->driver.driver_state = DRV_INSTALL; + + strncpy(dac_driver->driver.drv_name, driver_name, NAME_NUM_MAX); + + dac_driver->driver.configure = dac_driver->configure; + dac_driver->driver.private_data = dac_driver->private_data; + + ret = DacDriverRegister(&dac_driver->driver); + if (EOK != ret) { + KPrintf("DacDriverInit DriverRegister error %u\n", ret); + return ret; + } + } else { + KPrintf("DacDriverInit DriverRegister driver has been register state%u\n", dac_driver->driver.driver_state); + } + + return ret; +} + +/*Release the DAC device*/ +int DacReleaseBus(struct DacBus *dac_bus) +{ + NULL_PARAM_CHECK(dac_bus); + + return BusRelease(&dac_bus->bus); +} + +/*Register the DAC Driver to the DAC BUS*/ +int DacDriverAttachToBus(const char *drv_name, const char *bus_name) +{ + NULL_PARAM_CHECK(drv_name); + NULL_PARAM_CHECK(bus_name); + + x_err_t ret = EOK; + + struct Bus *bus; + struct Driver *driver; + + bus = BusFind(bus_name); + if (NONE == bus) { + KPrintf("DacDriverAttachToBus find dac bus error!name %s\n", bus_name); + return ERROR; + } + + if (TYPE_DAC_BUS == bus->bus_type) { + driver = DacDriverFind(drv_name, TYPE_DAC_DRV); + if (NONE == driver) { + KPrintf("DacDriverAttachToBus find dac driver error!name %s\n", drv_name); + return ERROR; + } + + if (TYPE_DAC_DRV == driver->driver_type) { + ret = DriverRegisterToBus(bus, driver); + if (EOK != ret) { + KPrintf("DacDriverAttachToBus DriverRegisterToBus error %u\n", ret); + return ERROR; + } + } + } + + return ret; +} diff --git a/Ubiquitous/XiZi/resources/dac/dev_dac.c b/Ubiquitous/XiZi/resources/dac/dev_dac.c new file mode 100644 index 0000000..ad342eb --- /dev/null +++ b/Ubiquitous/XiZi/resources/dac/dev_dac.c @@ -0,0 +1,119 @@ +/* +* Copyright (c) 2020 AIIT XUOS Lab +* XiUOS is licensed under Mulan PSL v2. +* You can use this software according to the terms and conditions of the Mulan PSL v2. +* You may obtain a copy of Mulan PSL v2 at: +* http://license.coscl.org.cn/MulanPSL2 +* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, +* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, +* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. +* See the Mulan PSL v2 for more details. +*/ + +/** +* @file dev_dac.c +* @brief register dac dev function using bus driver framework +* @version 1.1 +* @author AIIT XUOS Lab +* @date 2021-12-28 +*/ + +#include +#include + +static DoubleLinklistType dacdev_linklist; + +/*Create the DAC device linklist*/ +static void DacDeviceLinkInit() +{ + InitDoubleLinkList(&dacdev_linklist); +} + +/*Find the register DAC device*/ +HardwareDevType DacDeviceFind(const char *dev_name, enum DevType dev_type) +{ + NULL_PARAM_CHECK(dev_name); + + struct HardwareDev *device = NONE; + + DoubleLinklistType *node = NONE; + DoubleLinklistType *head = &dacdev_linklist; + for (node = head->node_next; node != head; node = node->node_next) { + device = SYS_DOUBLE_LINKLIST_ENTRY(node, struct HardwareDev, dev_link); + if ((!strcmp(device->dev_name, dev_name)) && (dev_type == device->dev_type)) { + return device; + } + } + + KPrintf("DacDeviceFind dacnot find the %s device.return NULL\n", dev_name); + return NONE; +} + +/*Register the DAC device*/ +int DacDeviceRegister(struct DacHardwareDevice *dac_device, void *dac_param, const char *device_name) +{ + NULL_PARAM_CHECK(dac_device); + NULL_PARAM_CHECK(device_name); + + x_err_t ret = EOK; + static x_bool dev_link_flag = RET_FALSE; + + if (!dev_link_flag) { + DacDeviceLinkInit(); + dev_link_flag = RET_TRUE; + } + + if (DEV_INSTALL != dac_device->haldev.dev_state) { + strncpy(dac_device->haldev.dev_name, device_name, NAME_NUM_MAX); + dac_device->haldev.dev_type = TYPE_DAC_DEV; + dac_device->haldev.dev_state = DEV_INSTALL; + + dac_device->haldev.dev_done = (struct HalDevDone *)dac_device->dac_dev_done; + + dac_device->haldev.private_data = dac_param; + + DoubleLinkListInsertNodeAfter(&dacdev_linklist, &(dac_device->haldev.dev_link)); + } else { + KPrintf("DacDeviceRegister device has been register state%u\n", dac_device->haldev.dev_state); + } + + return ret; +} + +/*Register the DAC Device to the DAC BUS*/ +int DacDeviceAttachToBus(const char *dev_name, const char *bus_name) +{ + NULL_PARAM_CHECK(dev_name); + NULL_PARAM_CHECK(bus_name); + + x_err_t ret = EOK; + + struct Bus *bus; + struct HardwareDev *device; + + bus = BusFind(bus_name); + if (NONE == bus) { + KPrintf("DacDeviceAttachToBus find dac bus error!name %s\n", bus_name); + return ERROR; + } + + if (TYPE_DAC_BUS == bus->bus_type) { + device = DacDeviceFind(dev_name, TYPE_DAC_DEV); + + if (NONE == device) { + KPrintf("DacDeviceAttachToBus find dac device error!name %s\n", dev_name); + return ERROR; + } + + if (TYPE_DAC_DEV == device->dev_type) { + ret = DeviceRegisterToBus(bus, device); + + if (EOK != ret) { + KPrintf("DacDeviceAttachToBus DeviceRegisterToBus error %u\n", ret); + return ERROR; + } + } + } + + return EOK; +} diff --git a/Ubiquitous/XiZi/resources/dac/drv_dac.c b/Ubiquitous/XiZi/resources/dac/drv_dac.c new file mode 100644 index 0000000..19347cb --- /dev/null +++ b/Ubiquitous/XiZi/resources/dac/drv_dac.c @@ -0,0 +1,69 @@ +/* +* Copyright (c) 2020 AIIT XUOS Lab +* XiUOS is licensed under Mulan PSL v2. +* You can use this software according to the terms and conditions of the Mulan PSL v2. +* You may obtain a copy of Mulan PSL v2 at: +* http://license.coscl.org.cn/MulanPSL2 +* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, +* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, +* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. +* See the Mulan PSL v2 for more details. +*/ + +/** +* @file drv_dac.c +* @brief register dac drv function using bus driver framework +* @version 2.0 +* @author AIIT XUOS Lab +* @date 2022-1-11 +*/ + +#include +#include + +static DoubleLinklistType dacdrv_linklist; + +/*Create the driver linklist*/ +static void DacDrvLinkInit() +{ + InitDoubleLinkList(&dacdrv_linklist); +} + +/*Find the regiter driver*/ +DriverType DacDriverFind(const char *drv_name, enum DriverType_e drv_type) +{ + NULL_PARAM_CHECK(drv_name); + + struct Driver *driver = NONE; + + DoubleLinklistType *node = NONE; + DoubleLinklistType *head = &dacdrv_linklist; + + for (node = head->node_next; node != head; node = node->node_next) { + driver = SYS_DOUBLE_LINKLIST_ENTRY(node, struct Driver, driver_link); + if ((!strcmp(driver->drv_name, drv_name)) && (drv_type == driver->driver_type)) { + return driver; + } + } + + KPrintf("DacDriverFind cannot find the %s driver.return NULL\n", drv_name); + return NONE; +} + +/*Register the Driver, manage with the double linklist*/ +int DacDriverRegister(struct Driver *driver) +{ + NULL_PARAM_CHECK(driver); + + x_err_t ret = EOK; + static x_bool driver_link_flag = RET_FALSE; + + if (!driver_link_flag) { + DacDrvLinkInit(); + driver_link_flag = RET_TRUE; + } + + DoubleLinkListInsertNodeAfter(&dacdrv_linklist, &(driver->driver_link)); + + return ret; +} diff --git a/Ubiquitous/XiZi/resources/ethernet/Makefile b/Ubiquitous/XiZi/resources/ethernet/Makefile new file mode 100644 index 0000000..7173fa1 --- /dev/null +++ b/Ubiquitous/XiZi/resources/ethernet/Makefile @@ -0,0 +1,3 @@ +SRC_DIR += LwIP cmd_lwip + +include $(KERNEL_ROOT)/compiler.mk diff --git a/Ubiquitous/XiZi/resources/i2c/Makefile b/Ubiquitous/XiZi/resources/i2c/Makefile new file mode 100644 index 0000000..5af536c --- /dev/null +++ b/Ubiquitous/XiZi/resources/i2c/Makefile @@ -0,0 +1,5 @@ +SRC_FILES += dev_i2c.c drv_i2c.c bus_i2c.c + + + +include $(KERNEL_ROOT)/compiler.mk diff --git a/Ubiquitous/XiZi/resources/i2c/bus_i2c.c b/Ubiquitous/XiZi/resources/i2c/bus_i2c.c new file mode 100644 index 0000000..deeb4ad --- /dev/null +++ b/Ubiquitous/XiZi/resources/i2c/bus_i2c.c @@ -0,0 +1,123 @@ +/* +* Copyright (c) 2020 AIIT XUOS Lab +* XiUOS is licensed under Mulan PSL v2. +* You can use this software according to the terms and conditions of the Mulan PSL v2. +* You may obtain a copy of Mulan PSL v2 at: +* http://license.coscl.org.cn/MulanPSL2 +* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, +* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, +* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. +* See the Mulan PSL v2 for more details. +*/ + +/** +* @file bus_i2c.c +* @brief register i2c bus function using bus driver framework +* @version 1.0 +* @author AIIT XUOS Lab +* @date 2021-04-24 +*/ + +#include +#include + +/*Register the I2C BUS*/ +int I2cBusInit(struct I2cBus *i2c_bus, const char *bus_name) +{ + NULL_PARAM_CHECK(i2c_bus); + NULL_PARAM_CHECK(bus_name); + + x_err_t ret = EOK; + + if (BUS_INSTALL != i2c_bus->bus.bus_state) { + strncpy(i2c_bus->bus.bus_name, bus_name, NAME_NUM_MAX); + + i2c_bus->bus.bus_type = TYPE_I2C_BUS; + i2c_bus->bus.bus_state = BUS_INSTALL; + i2c_bus->bus.private_data = i2c_bus->private_data; + + ret = BusRegister(&i2c_bus->bus); + if (EOK != ret) { + KPrintf("I2cBusInit BusRegister error %u\n", ret); + return ret; + } + } else { + KPrintf("I2cBusInit BusRegister bus has been register state%u\n", i2c_bus->bus.bus_state); + } + + return ret; +} + +/*Register the I2C Driver*/ +int I2cDriverInit(struct I2cDriver *i2c_driver, const char *driver_name) +{ + NULL_PARAM_CHECK(i2c_driver); + NULL_PARAM_CHECK(driver_name); + + x_err_t ret = EOK; + + if (DRV_INSTALL != i2c_driver->driver.driver_state) { + i2c_driver->driver.driver_type = TYPE_I2C_DRV; + i2c_driver->driver.driver_state = DRV_INSTALL; + + strncpy(i2c_driver->driver.drv_name, driver_name, NAME_NUM_MAX); + + i2c_driver->driver.private_data = i2c_driver->private_data; + + i2c_driver->driver.configure = i2c_driver->configure; + + ret = I2cDriverRegister(&i2c_driver->driver); + if (EOK != ret) { + KPrintf("I2cDriverInit DriverRegister error %u\n", ret); + return ret; + } + } else { + KPrintf("I2cDriverInit DriverRegister driver has been register state%u\n", i2c_driver->driver.driver_state); + } + + return ret; +} + +/*Release the I2C device*/ +int I2cReleaseBus(struct I2cBus *i2c_bus) +{ + NULL_PARAM_CHECK(i2c_bus); + + return BusRelease(&i2c_bus->bus); +} + +/*Register the I2C Driver to the I2C BUS*/ +int I2cDriverAttachToBus(const char *drv_name, const char *bus_name) +{ + NULL_PARAM_CHECK(drv_name); + NULL_PARAM_CHECK(bus_name); + + x_err_t ret = EOK; + + struct Bus *bus; + struct Driver *driver; + + bus = BusFind(bus_name); + if (NONE == bus) { + KPrintf("I2cDriverAttachToBus find i2c bus error!name %s\n", bus_name); + return ERROR; + } + + if (TYPE_I2C_BUS == bus->bus_type) { + driver = I2cDriverFind(drv_name, TYPE_I2C_DRV); + if (NONE == driver) { + KPrintf("I2cDriverAttachToBus find i2c driver error!name %s\n", drv_name); + return ERROR; + } + + if (TYPE_I2C_DRV == driver->driver_type) { + ret = DriverRegisterToBus(bus, driver); + if (EOK != ret) { + KPrintf("I2cDriverAttachToBus DriverRegisterToBus error %u\n", ret); + return ERROR; + } + } + } + + return ret; +} diff --git a/Ubiquitous/XiZi/resources/i2c/dev_i2c.c b/Ubiquitous/XiZi/resources/i2c/dev_i2c.c new file mode 100644 index 0000000..48e0f21 --- /dev/null +++ b/Ubiquitous/XiZi/resources/i2c/dev_i2c.c @@ -0,0 +1,180 @@ +/* +* Copyright (c) 2020 AIIT XUOS Lab +* XiUOS is licensed under Mulan PSL v2. +* You can use this software according to the terms and conditions of the Mulan PSL v2. +* You may obtain a copy of Mulan PSL v2 at: +* http://license.coscl.org.cn/MulanPSL2 +* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, +* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, +* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. +* See the Mulan PSL v2 for more details. +*/ + +/** +* @file dev_i2c.c +* @brief register i2c dev function using bus driver framework +* @version 1.0 +* @author AIIT XUOS Lab +* @date 2021-04-24 +*/ + +#include +#include + +static DoubleLinklistType i2cdev_linklist; + +/*Create the I2C device linklist*/ +static void I2cDeviceLinkInit() +{ + InitDoubleLinkList(&i2cdev_linklist); +} + +static uint32 I2cDeviceWrite(void *dev, struct BusBlockWriteParam *write_param) +{ + NULL_PARAM_CHECK(dev); + NULL_PARAM_CHECK(write_param); + + uint32 ret; + + struct I2cHardwareDevice *i2c_dev = (struct I2cHardwareDevice *)dev; + struct I2cDataStandard i2c_msg; + + i2c_msg.addr = i2c_dev->i2c_dev_addr; + i2c_msg.flags = I2C_WR; + + i2c_msg.buf = (uint8 *)x_malloc(write_param->size); + memcpy(i2c_msg.buf, write_param->buffer, write_param->size); + + i2c_msg.len = write_param->size; + i2c_msg.retries = 10; + i2c_msg.next = NONE; + + ret = i2c_dev->i2c_dev_done->dev_write(i2c_dev, &i2c_msg); + + x_free(i2c_msg.buf); + + return ret; +} + +static uint32 I2cDeviceRead(void *dev, struct BusBlockReadParam *read_param) +{ + NULL_PARAM_CHECK(dev); + NULL_PARAM_CHECK(read_param); + + struct I2cHardwareDevice *i2c_dev = (struct I2cHardwareDevice *)dev; + struct I2cDataStandard i2c_msg_write, i2c_msg_read; + + i2c_msg_write.addr = i2c_dev->i2c_dev_addr; + i2c_msg_write.flags = I2C_WR; + i2c_msg_write.buf = NONE; + i2c_msg_write.len = 0; + i2c_msg_write.retries = 10; + i2c_msg_write.next = NONE; + + i2c_dev->i2c_dev_done->dev_write(i2c_dev, &i2c_msg_write); + + i2c_msg_read.addr = i2c_dev->i2c_dev_addr; + i2c_msg_read.flags = I2C_RD; + i2c_msg_read.buf = read_param->buffer; + i2c_msg_read.len = read_param->size; + i2c_msg_read.retries = 10; + i2c_msg_read.next = NONE; + + return i2c_dev->i2c_dev_done->dev_read(i2c_dev, &i2c_msg_read); +} + +static const struct HalDevDone dev_done = +{ + .open = NONE, + .close = NONE, + .write = I2cDeviceWrite, + .read = I2cDeviceRead, +}; + +/*Find the register I2C device*/ +HardwareDevType I2cDeviceFind(const char *dev_name, enum DevType dev_type) +{ + NULL_PARAM_CHECK(dev_name); + + struct HardwareDev *device = NONE; + + DoubleLinklistType *node = NONE; + DoubleLinklistType *head = &i2cdev_linklist; + + for (node = head->node_next; node != head; node = node->node_next) { + device = SYS_DOUBLE_LINKLIST_ENTRY(node, struct HardwareDev, dev_link); + if ((!strcmp(device->dev_name, dev_name)) && (dev_type == device->dev_type)) { + return device; + } + } + + KPrintf("I2cDeviceFind cannot find the %s device.return NULL\n", dev_name); + return NONE; +} + +/*Register the I2C device*/ +int I2cDeviceRegister(struct I2cHardwareDevice *i2c_device, void *i2c_param, const char *device_name) +{ + NULL_PARAM_CHECK(i2c_device); + NULL_PARAM_CHECK(device_name); + + x_err_t ret = EOK; + static x_bool dev_link_flag = RET_FALSE; + + if (!dev_link_flag) { + I2cDeviceLinkInit(); + dev_link_flag = RET_TRUE; + } + + if (DEV_INSTALL != i2c_device->haldev.dev_state) { + strncpy(i2c_device->haldev.dev_name, device_name, NAME_NUM_MAX); + i2c_device->haldev.dev_type = TYPE_I2C_DEV; + i2c_device->haldev.dev_state = DEV_INSTALL; + + i2c_device->haldev.dev_done = &dev_done; + + i2c_device->haldev.private_data = i2c_param; + + DoubleLinkListInsertNodeAfter(&i2cdev_linklist, &(i2c_device->haldev.dev_link)); + } else { + KPrintf("I2cDeviceRegister device has been register state%u\n", i2c_device->haldev.dev_state); + } + + return ret; +} + +/*Register the I2C Device to the I2C BUS*/ +int I2cDeviceAttachToBus(const char *dev_name, const char *bus_name) +{ + NULL_PARAM_CHECK(dev_name); + NULL_PARAM_CHECK(bus_name); + + x_err_t ret = EOK; + + struct Bus *bus; + struct HardwareDev *device; + + bus = BusFind(bus_name); + if (NONE == bus) { + KPrintf("I2cDeviceAttachToBus find i2c bus error!name %s\n", bus_name); + return ERROR; + } + + if (TYPE_I2C_BUS == bus->bus_type) { + device = I2cDeviceFind(dev_name, TYPE_I2C_DEV); + if (NONE == device) { + KPrintf("I2cDeviceAttachToBus find i2c device error!name %s\n", dev_name); + return ERROR; + } + + if (TYPE_I2C_DEV == device->dev_type) { + ret = DeviceRegisterToBus(bus, device); + if (EOK != ret) { + KPrintf("I2cDeviceAttachToBus DeviceRegisterToBus error %u\n", ret); + return ERROR; + } + } + } + + return EOK; +} diff --git a/Ubiquitous/XiZi/resources/i2c/drv_i2c.c b/Ubiquitous/XiZi/resources/i2c/drv_i2c.c new file mode 100644 index 0000000..c9533cb --- /dev/null +++ b/Ubiquitous/XiZi/resources/i2c/drv_i2c.c @@ -0,0 +1,69 @@ +/* +* Copyright (c) 2020 AIIT XUOS Lab +* XiUOS is licensed under Mulan PSL v2. +* You can use this software according to the terms and conditions of the Mulan PSL v2. +* You may obtain a copy of Mulan PSL v2 at: +* http://license.coscl.org.cn/MulanPSL2 +* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, +* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, +* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. +* See the Mulan PSL v2 for more details. +*/ + +/** +* @file drv_i2c.c +* @brief register i2c drv function using bus driver framework +* @version 1.0 +* @author AIIT XUOS Lab +* @date 2021-04-24 +*/ + +#include +#include + +static DoubleLinklistType i2cdrv_linklist; + +/*Create the driver linklist*/ +static void I2cDrvLinkInit() +{ + InitDoubleLinkList(&i2cdrv_linklist); +} + +/*Find the regiter driver*/ +DriverType I2cDriverFind(const char *drv_name, enum DriverType_e drv_type) +{ + NULL_PARAM_CHECK(drv_name); + + struct Driver *driver = NONE; + + DoubleLinklistType *node = NONE; + DoubleLinklistType *head = &i2cdrv_linklist; + + for (node = head->node_next; node != head; node = node->node_next) { + driver = SYS_DOUBLE_LINKLIST_ENTRY(node, struct Driver, driver_link); + if ((!strcmp(driver->drv_name, drv_name)) && (drv_type == driver->driver_type)) { + return driver; + } + } + + KPrintf("I2cDriverFind cannot find the %s driver.return NULL\n", drv_name); + return NONE; +} + +/*Register the Driver, manage with the double linklist*/ +int I2cDriverRegister(struct Driver *driver) +{ + NULL_PARAM_CHECK(driver); + + x_err_t ret = EOK; + static x_bool driver_link_flag = RET_FALSE; + + if (!driver_link_flag) { + I2cDrvLinkInit(); + driver_link_flag = RET_TRUE; + } + + DoubleLinkListInsertNodeAfter(&i2cdrv_linklist, &(driver->driver_link)); + + return ret; +} diff --git a/Ubiquitous/XiZi/resources/include/bus.h b/Ubiquitous/XiZi/resources/include/bus.h new file mode 100644 index 0000000..967d3a5 --- /dev/null +++ b/Ubiquitous/XiZi/resources/include/bus.h @@ -0,0 +1,273 @@ +/* +* Copyright (c) 2020 AIIT XUOS Lab +* XiUOS is licensed under Mulan PSL v2. +* You can use this software according to the terms and conditions of the Mulan PSL v2. +* You may obtain a copy of Mulan PSL v2 at: +* http://license.coscl.org.cn/MulanPSL2 +* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, +* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, +* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. +* See the Mulan PSL v2 for more details. +*/ + +/** +* @file bus.h +* @brief define bus driver framework function and common API +* @version 1.0 +* @author AIIT XUOS Lab +* @date 2021-04-24 +*/ + +#ifndef BUS_H +#define BUS_H + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +#define OPE_INT 0x0000 +#define OPE_CFG 0x0001 + +#define OPER_WDT_SET_TIMEOUT 0x0002 +#define OPER_WDT_KEEPALIVE 0x0003 + +typedef struct Bus *BusType; +typedef struct HardwareDev *HardwareDevType; +typedef struct Driver *DriverType; + +/* need to add new bus type in ../tool/shell/letter-shell/cmd.c, ensure ShowBus cmd supported*/ +enum BusType_e +{ + TYPE_I2C_BUS = 0, + TYPE_SPI_BUS, + TYPE_HWTIMER_BUS, + TYPE_USB_BUS, + TYPE_CAN_BUS, + TYPE_WDT_BUS, + TYPE_SDIO_BUS, + TYPE_TOUCH_BUS, + TYPE_LCD_BUS, + TYPE_PIN_BUS, + TYPE_RTC_BUS, + TYPE_SERIAL_BUS, + TYPE_ADC_BUS, + TYPE_DAC_BUS, + TYPE_BUS_END, +}; + +enum BusState +{ + BUS_INIT = 0, + BUS_INSTALL, + BUS_UNINSTALL, +}; + +enum DevType +{ + TYPE_I2C_DEV = 0, + TYPE_SPI_DEV, + TYPE_HWTIMER_DEV, + TYPE_USB_DEV, + TYPE_CAN_DEV, + TYPE_WDT_DEV, + TYPE_SDIO_DEV, + TYPE_TOUCH_DEV, + TYPE_LCD_DEV, + TYPE_PIN_DEV, + TYPE_RTC_DEV, + TYPE_SERIAL_DEV, + TYPE_ADC_DEV, + TYPE_DAC_DEV, + TYPE_DEV_END, +}; + +enum DevState +{ + DEV_INIT = 0, + DEV_INSTALL, + DEV_UNINSTALL, +}; + +enum DriverType_e +{ + TYPE_I2C_DRV = 0, + TYPE_SPI_DRV, + TYPE_HWTIMER_DRV, + TYPE_USB_DRV, + TYPE_CAN_DRV, + TYPE_WDT_DRV, + TYPE_SDIO_DRV, + TYPE_TOUCH_DRV, + TYPE_LCD_DRV, + TYPE_PIN_DRV, + TYPE_RTC_DRV, + TYPE_SERIAL_DRV, + TYPE_ADC_DRV, + TYPE_DAC_DRV, + TYPE_DRV_END, +}; + +enum DriverState +{ + DRV_INIT = 0, + DRV_INSTALL, + DRV_UNINSTALL, +}; + +struct BusConfigureInfo +{ + int configure_cmd; + void *private_data; +}; + +struct BusBlockReadParam +{ + x_OffPos pos; + void* buffer; + x_size_t size; + x_size_t read_length; +}; + +struct BusBlockWriteParam +{ + x_OffPos pos; + const void* buffer; + x_size_t size; +}; + +struct HalDevBlockParam +{ + uint32 cmd; + struct DeviceBlockArrange dev_block; + struct DeviceBlockAddr *dev_addr; +}; + +struct HalDevDone +{ + uint32 (*open) (void *dev); + uint32 (*close) (void *dev); + uint32 (*write) (void *dev, struct BusBlockWriteParam *write_param); + uint32 (*read) (void *dev, struct BusBlockReadParam *read_param); +}; + +struct HardwareDev +{ + int8 dev_name[NAME_NUM_MAX]; + enum DevType dev_type; + enum DevState dev_state; + + const struct HalDevDone *dev_done; + + int (*dev_recv_callback) (void *dev, x_size_t length); + int (*dev_block_control) (struct HardwareDev *dev, struct HalDevBlockParam *block_param); + + struct Bus *owner_bus; + void *private_data; + + int32 dev_sem; + + DoubleLinklistType dev_link; +}; + +struct Driver +{ + int8 drv_name[NAME_NUM_MAX]; + enum DriverType_e driver_type; + enum DriverState driver_state; + + uint32 (*configure)(void *drv, struct BusConfigureInfo *configure_info); + + struct Bus *owner_bus; + void *private_data; + + DoubleLinklistType driver_link; +}; + +struct Bus +{ + int8 bus_name[NAME_NUM_MAX]; + enum BusType_e bus_type; + enum BusState bus_state; + + int32 (*match)(struct Driver *driver, struct HardwareDev *device); + + int bus_lock; + + struct HardwareDev *owner_haldev; + struct Driver *owner_driver; + + void *private_data; + + /*manage the drv of the bus*/ + uint8 driver_cnt; + uint8 bus_drvlink_flag; + DoubleLinklistType bus_drvlink; + + /*manage the dev of the bus*/ + uint8 haldev_cnt; + uint8 bus_devlink_flag; + DoubleLinklistType bus_devlink; + + uint8 bus_cnt; + uint8 bus_link_flag; + DoubleLinklistType bus_link; +}; + +/*Register the BUS,manage with the double linklist*/ +int BusRegister(struct Bus *bus); + +/*Release the BUS framework*/ +int BusRelease(struct Bus *bus); + +/*Unregister a certain kind of BUS*/ +int BusUnregister(struct Bus *bus); + +/*Register the driver to the bus*/ +int DriverRegisterToBus(struct Bus *bus, struct Driver *driver); + +/*Register the device to the bus*/ +int DeviceRegisterToBus(struct Bus *bus, struct HardwareDev *device); + +/*Delete the driver from the bus*/ +int DriverDeleteFromBus(struct Bus *bus, struct Driver *driver); + +/*Delete the device from the bus*/ +int DeviceDeleteFromBus(struct Bus *bus, struct HardwareDev *device); + +/*Find the bus with bus name*/ +BusType BusFind(const char *bus_name); + +/*Find the driver of cetain bus*/ +DriverType BusFindDriver(struct Bus *bus, const char *driver_name); + +/*Find the device of certain bus*/ +HardwareDevType BusFindDevice(struct Bus *bus, const char *device_name); + +/*Dev receive data callback function*/ +uint32 BusDevRecvCallback(struct HardwareDev *dev, int (*dev_recv_callback) (void *dev, x_size_t length)); + +/*Open the device of the bus*/ +uint32 BusDevOpen(struct HardwareDev *dev); + +/*Close the device of the bus*/ +uint32 BusDevClose(struct HardwareDev *dev); + +/*Write data to the device*/ +uint32 BusDevWriteData(struct HardwareDev *dev, struct BusBlockWriteParam *write_param); + +/*Read data from the device*/ +uint32 BusDevReadData(struct HardwareDev *dev, struct BusBlockReadParam *read_param); + +/*Configure the driver of the bus*/ +uint32 BusDrvConfigure(struct Driver *drv, struct BusConfigureInfo *configure_info); + +/*Obtain the bus using a certain dev*/ +int DeviceObtainBus(struct Bus *bus, struct HardwareDev *dev, const char *drv_name, struct BusConfigureInfo *configure_info); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/Ubiquitous/XiZi/resources/include/bus_adc.h b/Ubiquitous/XiZi/resources/include/bus_adc.h new file mode 100644 index 0000000..42636b5 --- /dev/null +++ b/Ubiquitous/XiZi/resources/include/bus_adc.h @@ -0,0 +1,67 @@ +/* +* Copyright (c) 2020 AIIT XUOS Lab +* XiUOS is licensed under Mulan PSL v2. +* You can use this software according to the terms and conditions of the Mulan PSL v2. +* You may obtain a copy of Mulan PSL v2 at: +* http://license.coscl.org.cn/MulanPSL2 +* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, +* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, +* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. +* See the Mulan PSL v2 for more details. +*/ + +/** +* @file bus_adc.h +* @brief define adc bus and drv function using bus driver framework +* @version 1.1 +* @author AIIT XUOS Lab +* @date 2021-12-28 +*/ + +#ifndef BUS_ADC_H +#define BUS_ADC_H + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +struct AdcDriver +{ + struct Driver driver; + uint32 (*configure) (void *drv, struct BusConfigureInfo *configure_info); + + void *private_data; +}; + +struct AdcBus +{ + struct Bus bus; + + void *private_data; +}; + +/*Register the ADC bus*/ +int AdcBusInit(struct AdcBus *adc_bus, const char *bus_name); + +/*Register the ADC driver*/ +int AdcDriverInit(struct AdcDriver *adc_driver, const char *driver_name); + +/*Release the ADC device*/ +int AdcReleaseBus(struct AdcBus *adc_bus); + +/*Register the ADC driver to the ADC bus*/ +int AdcDriverAttachToBus(const char *drv_name, const char *bus_name); + +/*Register the driver, manage with the double linklist*/ +int AdcDriverRegister(struct Driver *driver); + +/*Find the register driver*/ +DriverType AdcDriverFind(const char *drv_name, enum DriverType_e drv_type); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/Ubiquitous/XiZi/resources/include/bus_can.h b/Ubiquitous/XiZi/resources/include/bus_can.h new file mode 100644 index 0000000..65ce674 --- /dev/null +++ b/Ubiquitous/XiZi/resources/include/bus_can.h @@ -0,0 +1,67 @@ +/* +* Copyright (c) 2020 AIIT XUOS Lab +* XiUOS is licensed under Mulan PSL v2. +* You can use this software according to the terms and conditions of the Mulan PSL v2. +* You may obtain a copy of Mulan PSL v2 at: +* http://license.coscl.org.cn/MulanPSL2 +* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, +* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, +* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. +* See the Mulan PSL v2 for more details. +*/ + +/** +* @file bus_can.h +* @brief define can bus and drv function using bus driver framework +* @version 1.0 +* @author AIIT XUOS Lab +* @date 2021-04-24 +*/ + +#ifndef BUS_CAN_H +#define BUS_CAN_H + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +struct CanDriver +{ + struct Driver driver; + uint32 (*configure) (void *drv, struct BusConfigureInfo *configure_info); + + void *private_data; +}; + +struct CanBus +{ + struct Bus bus; + + void *private_data; +}; + +/*Register the CAN bus*/ +int CanBusInit(struct CanBus *can_bus, const char *bus_name); + +/*Register the CAN driver*/ +int CanDriverInit(struct CanDriver *can_driver, const char *driver_name); + +/*Release the CAN device*/ +int CanReleaseBus(struct CanBus *can_bus); + +/*Register the CAN driver to the CAN bus*/ +int CanDriverAttachToBus(const char *drv_name, const char *bus_name); + +/*Register the driver, manage with the double linklist*/ +int CanDriverRegister(struct Driver *driver); + +/*Find the register driver*/ +DriverType CanDriverFind(const char *drv_name, enum DriverType_e drv_type); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/Ubiquitous/XiZi/resources/include/bus_dac.h b/Ubiquitous/XiZi/resources/include/bus_dac.h new file mode 100644 index 0000000..e87b963 --- /dev/null +++ b/Ubiquitous/XiZi/resources/include/bus_dac.h @@ -0,0 +1,67 @@ +/* +* Copyright (c) 2020 AIIT XUOS Lab +* XiUOS is licensed under Mulan PSL v2. +* You can use this software according to the terms and conditions of the Mulan PSL v2. +* You may obtain a copy of Mulan PSL v2 at: +* http://license.coscl.org.cn/MulanPSL2 +* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, +* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, +* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. +* See the Mulan PSL v2 for more details. +*/ + +/** +* @file bus_dac.h +* @brief define dac bus and drv function using bus driver framework +* @version 2.0 +* @author AIIT XUOS Lab +* @date 2022-1-11 +*/ + +#ifndef BUS_DAC_H +#define BUS_DAC_H + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +struct DacDriver +{ + struct Driver driver; + uint32 (*configure) (void *drv, struct BusConfigureInfo *configure_info); + + void *private_data; +}; + +struct DacBus +{ + struct Bus bus; + + void *private_data; +}; + +/*Register the DAC bus*/ +int DacBusInit(struct DacBus *dac_bus, const char *bus_name); + +/*Register the DAC driver*/ +int DacDriverInit(struct DacDriver *dac_driver, const char *driver_name); + +/*Release the DAC device*/ +int DacReleaseBus(struct DacBus *dac_bus); + +/*Register the DAC driver to the DAC bus*/ +int DacDriverAttachToBus(const char *drv_name, const char *bus_name); + +/*Register the driver, manage with the double linklist*/ +int DacDriverRegister(struct Driver *driver); + +/*Find the register driver*/ +DriverType DacDriverFind(const char *drv_name, enum DriverType_e drv_type); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/Ubiquitous/XiZi/resources/include/bus_hwtimer.h b/Ubiquitous/XiZi/resources/include/bus_hwtimer.h new file mode 100644 index 0000000..d2b81b2 --- /dev/null +++ b/Ubiquitous/XiZi/resources/include/bus_hwtimer.h @@ -0,0 +1,65 @@ +/* +* Copyright (c) 2020 AIIT XUOS Lab +* XiUOS is licensed under Mulan PSL v2. +* You can use this software according to the terms and conditions of the Mulan PSL v2. +* You may obtain a copy of Mulan PSL v2 at: +* http://license.coscl.org.cn/MulanPSL2 +* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, +* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, +* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. +* See the Mulan PSL v2 for more details. +*/ + +/** +* @file bus_hwtimer.h +* @brief define hwtimer bus and drv function using bus driver framework +* @version 1.0 +* @author AIIT XUOS Lab +* @date 2021-04-24 +*/ + +#ifndef BUS_HWTIMER_H +#define BUS_HWTIMER_H + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +struct HwtimerDriver +{ + struct Driver driver; + uint32 (*configure) (void *drv, struct BusConfigureInfo *configure_info); +}; + +struct HwtimerBus +{ + struct Bus bus; + + void *private_data; +}; + +/*Register the hwtimer bus*/ +int HwtimerBusInit(struct HwtimerBus *hwtimer_bus, const char *bus_name); + +/*Register the hwtimer driver*/ +int HwtimerDriverInit(struct HwtimerDriver *hwtimer_driver, const char *driver_name); + +/*Release the hwtimer device*/ +int HwtimerReleaseBus(struct HwtimerBus *hwtimer_bus); + +/*Register the hwtimer driver to the hwtimer bus*/ +int HwtimerDriverAttachToBus(const char *drv_name, const char *bus_name); + +/*Register the driver, manage with the double linklist*/ +int HwtimerDriverRegister(struct Driver *driver); + +/*Find the register driver*/ +DriverType HwtimerDriverFind(const char *drv_name); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/Ubiquitous/XiZi/resources/include/bus_i2c.h b/Ubiquitous/XiZi/resources/include/bus_i2c.h new file mode 100644 index 0000000..8905b41 --- /dev/null +++ b/Ubiquitous/XiZi/resources/include/bus_i2c.h @@ -0,0 +1,92 @@ +/* +* Copyright (c) 2020 AIIT XUOS Lab +* XiUOS is licensed under Mulan PSL v2. +* You can use this software according to the terms and conditions of the Mulan PSL v2. +* You may obtain a copy of Mulan PSL v2 at: +* http://license.coscl.org.cn/MulanPSL2 +* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, +* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, +* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. +* See the Mulan PSL v2 for more details. +*/ + +/** +* @file bus_i2c.h +* @brief define i2c bus and drv function using bus driver framework +* @version 1.0 +* @author AIIT XUOS Lab +* @date 2021-04-24 +*/ + +#ifndef BUS_I2C_H +#define BUS_I2C_H + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +struct I2cHalDrvDone +{ + void *data; + void (*SetSdaState) (void *data, uint8 sda_state); + void (*SetSclState) (void *data, uint8 scl_state); + uint8 (*GetSdaState) (void *data); + uint8 (*GetSclState) (void *data); +#ifdef ARCH_RISCV + int (*udelay)(uint64 us); +#endif +#ifdef ARCH_ARM + int (*udelay)(uint32 us); +#endif + + uint32 delay_us; + uint32 timeout; +}; + +typedef struct +{ + uint8 i2c_sda_pin; + uint8 i2c_scl_pin; +}I2cBusParam; + +struct I2cDriver +{ + struct Driver driver; + + uint32 (*configure) (void *drv, struct BusConfigureInfo *configure_info); + + void *private_data; +}; + +struct I2cBus +{ + struct Bus bus; + + void *private_data; +}; + +/*Register the I2C bus*/ +int I2cBusInit(struct I2cBus *i2c_bus, const char *bus_name); + +/*Register the I2C driver*/ +int I2cDriverInit(struct I2cDriver *i2c_driver, const char *driver_name); + +/*Release the I2C device*/ +int I2cReleaseBus(struct I2cBus *i2c_bus); + +/*Register the I2C driver to the I2C bus*/ +int I2cDriverAttachToBus(const char *drv_name, const char *bus_name); + +/*Register the driver, manage with the double linklist*/ +int I2cDriverRegister(struct Driver *driver); + +/*Find the register driver*/ +DriverType I2cDriverFind(const char *drv_name, enum DriverType_e drv_type); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/Ubiquitous/XiZi/resources/include/bus_lcd.h b/Ubiquitous/XiZi/resources/include/bus_lcd.h new file mode 100644 index 0000000..efba5f3 --- /dev/null +++ b/Ubiquitous/XiZi/resources/include/bus_lcd.h @@ -0,0 +1,65 @@ +/* +* Copyright (c) 2020 AIIT XUOS Lab +* XiUOS is licensed under Mulan PSL v2. +* You can use this software according to the terms and conditions of the Mulan PSL v2. +* You may obtain a copy of Mulan PSL v2 at: +* http://license.coscl.org.cn/MulanPSL2 +* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, +* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, +* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. +* See the Mulan PSL v2 for more details. +*/ + +/** +* @file bus_lcd.h +* @brief define lcd bus and drv function using bus driver framework +* @version 1.0 +* @author AIIT XUOS Lab +* @date 2021-04-24 +*/ + +#ifndef BUS_LCD_H +#define BUS_LCD_H + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +struct LcdDriver +{ + struct Driver driver; + uint32 (*configure) (void *drv, struct BusConfigureInfo *configure_info); +}; + +struct LcdBus +{ + struct Bus bus; + + void *private_data; +}; + +/*Register the lcd bus*/ +int LcdBusInit(struct LcdBus *lcd_bus , const char *bus_name); + +/*Register the lcd driver*/ +int LcdDriverInit(struct LcdDriver *lcd_driver, const char *driver_name); + +/*Release the lcd device*/ +int LcdReleaseBus(struct LcdBus *lcd_bus ); + +/*Register the lcd driver to the lcd bus*/ +int LcdDriverAttachToBus(const char *drv_name, const char *bus_name); + +/*Register the driver, manage with the double linklist*/ +int LcdDriverRegister(struct Driver *driver); + +/*Find the register driver*/ +DriverType LcdDriverFind(const char *drv_name, enum DriverType_e drv_type); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/Ubiquitous/XiZi/resources/include/bus_pin.h b/Ubiquitous/XiZi/resources/include/bus_pin.h new file mode 100644 index 0000000..e0f2069 --- /dev/null +++ b/Ubiquitous/XiZi/resources/include/bus_pin.h @@ -0,0 +1,68 @@ +/* +* Copyright (c) 2020 AIIT XUOS Lab +* XiUOS is licensed under Mulan PSL v2. +* You can use this software according to the terms and conditions of the Mulan PSL v2. +* You may obtain a copy of Mulan PSL v2 at: +* http://license.coscl.org.cn/MulanPSL2 +* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, +* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, +* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. +* See the Mulan PSL v2 for more details. +*/ + +/** +* @file bus_pin.h +* @brief define pin bus and drv function using bus driver framework +* @version 1.0 +* @author AIIT XUOS Lab +* @date 2021-04-24 +*/ + +#ifndef BUS_PIN_H +#define BUS_PIN_H + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +struct PinDriver +{ + struct Driver driver; + uint32 (*configure) (void *drv, struct BusConfigureInfo *ConfigureInfo); +}; + +struct PinBus +{ + struct Bus bus; + + void *private_data; +}; + +/*Register the Pin bus*/ +int PinBusInit(struct PinBus *pin_bus, const char *bus_name); + +/*Register the Pin driver*/ +int PinDriverInit(struct PinDriver *pin_driver, const char *driver_name, void *data); + +/*Release the Pin device*/ +int PinReleaseBus(struct PinBus *pin_bus); + +/*Register the Pin driver to the Pin bus*/ +int PinDriverAttachToBus(const char *drv_name, const char *bus_name); + +/*Register the driver, manage with the double linklist*/ +int PinDriverRegister(struct Driver *driver); + +/*Find the register driver*/ +DriverType PinDriverFind(const char *drv_name, enum DriverType_e drv_type); + +/*Get the initialized Pin bus*/ +BusType PinBusInitGet(void); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/Ubiquitous/XiZi/resources/include/bus_rtc.h b/Ubiquitous/XiZi/resources/include/bus_rtc.h new file mode 100644 index 0000000..4f46fe4 --- /dev/null +++ b/Ubiquitous/XiZi/resources/include/bus_rtc.h @@ -0,0 +1,98 @@ +/* +* Copyright (c) 2020 AIIT XUOS Lab +* XiUOS is licensed under Mulan PSL v2. +* You can use this software according to the terms and conditions of the Mulan PSL v2. +* You may obtain a copy of Mulan PSL v2 at: +* http://license.coscl.org.cn/MulanPSL2 +* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, +* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, +* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. +* See the Mulan PSL v2 for more details. +*/ + +/** +* @file bus_rtc.h +* @brief define rtc bus and drv function using bus driver framework +* @version 1.0 +* @author AIIT XUOS Lab +* @date 2021-04-24 +*/ + +#ifndef BUS_RTC_H +#define BUS_RTC_H + +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +struct RtcDateParam +{ + uint32 year; + uint32 month; + uint32 day; +}; + +struct RtcTimeParam +{ + uint32 hour; + uint32 minute; + uint32 second; +}; + +struct RtcSetParam +{ + int rtc_set_cmd; + time_t *time; + struct RtcDateParam date_param; + struct RtcTimeParam time_param; +}; + +struct RtcDrvConfigureParam +{ + int rtc_operation_cmd; + time_t *time; +}; + +struct RtcDriver +{ + struct Driver driver; + + uint32 (*configure) (void *drv, struct BusConfigureInfo *configure_info); +}; + +struct RtcBus +{ + struct Bus bus; + + void *private_data; +}; + +/*Register the rtc bus*/ +int RtcBusInit(struct RtcBus *rtc_bus, const char *bus_name); + +/*Register the rtc driver*/ +int RtcDriverInit(struct RtcDriver *rtc_driver, const char *driver_name); + +/*Release the rtc device*/ +int RtcReleaseBus(struct RtcBus *rtc_bus); + +/*Register the rtc driver to the rtc bus*/ +int RtcDriverAttachToBus(const char *drv_name, const char *bus_name); + +/*Register the driver, manage with the double linklist*/ +int RtcDriverRegister(struct Driver *driver); + +/*Find the register driver*/ +DriverType RtcDriverFind(const char *drv_name, enum DriverType_e drv_type); + +/*Set Rtc time and date*/ +int RtcDrvSetFunction(char *driver_name, struct RtcSetParam *rtc_set_param); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/Ubiquitous/XiZi/resources/include/bus_sdio.h b/Ubiquitous/XiZi/resources/include/bus_sdio.h new file mode 100644 index 0000000..380feea --- /dev/null +++ b/Ubiquitous/XiZi/resources/include/bus_sdio.h @@ -0,0 +1,64 @@ +/* +* Copyright (c) 2020 AIIT XUOS Lab +* XiUOS is licensed under Mulan PSL v2. +* You can use this software according to the terms and conditions of the Mulan PSL v2. +* You may obtain a copy of Mulan PSL v2 at: +* http://license.coscl.org.cn/MulanPSL2 +* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, +* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, +* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. +* See the Mulan PSL v2 for more details. +*/ + +/** +* @file bus_sdio.h +* @brief define sdio bus and drv function using bus driver framework +* @version 1.0 +* @author AIIT XUOS Lab +* @date 2021-04-24 +*/ + +#ifndef BUS_SDIO_H +#define BUS_SDIO_H + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +struct SdioDriver +{ + struct Driver driver; + uint32 (*configure) (void *drv, struct BusConfigureInfo *configure_info); +}; + +struct SdioBus +{ + struct Bus bus; + void *private_data; +}; + +/*Register the sdio bus*/ +int SdioBusInit(struct SdioBus *sdio_bus, const char *bus_name); + +/*Register the sdio driver*/ +int SdioDriverInit(struct SdioDriver *sdio_driver, const char *driver_name); + +/*Release the sdio device*/ +int SdioReleaseBus(struct SdioBus *sdio_bus); + +/*Register the sdio driver to the sdio bus*/ +int SdioDriverAttachToBus(const char *drv_name, const char *bus_name); + +/*Register the driver, manage with the double linklist*/ +int SdioDriverRegister(struct Driver *driver); + +/*Find the register driver*/ +DriverType SdioDriverFind(const char *drv_name); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/Ubiquitous/XiZi/resources/include/bus_serial.h b/Ubiquitous/XiZi/resources/include/bus_serial.h new file mode 100644 index 0000000..bb2628d --- /dev/null +++ b/Ubiquitous/XiZi/resources/include/bus_serial.h @@ -0,0 +1,112 @@ +/* +* Copyright (c) 2020 AIIT XUOS Lab +* XiUOS is licensed under Mulan PSL v2. +* You can use this software according to the terms and conditions of the Mulan PSL v2. +* You may obtain a copy of Mulan PSL v2 at: +* http://license.coscl.org.cn/MulanPSL2 +* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, +* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, +* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. +* See the Mulan PSL v2 for more details. +*/ + +/** +* @file bus_serial.h +* @brief define serial bus and drv function using bus driver framework +* @version 1.0 +* @author AIIT XUOS Lab +* @date 2021-04-24 +*/ + +#ifndef BUS_SERIAL_H +#define BUS_SERIAL_H + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +enum ExtSerialPortConfigure +{ + PORT_CFG_INIT = 0, + PORT_CFG_PARITY_CHECK, + PORT_CFG_DISABLE, + PORT_CFG_DIV, +}; + +struct SerialDataCfg +{ + uint32 serial_baud_rate; + uint8 serial_data_bits; + uint8 serial_stop_bits; + uint8 serial_parity_mode; + uint8 serial_bit_order; + uint8 serial_invert_mode; + uint16 serial_buffer_size; + + uint8 ext_uart_no; + enum ExtSerialPortConfigure port_configure; +}; + +struct SerialHwCfg +{ + uint32 serial_register_base; + uint32 serial_irq_interrupt; + void *private_data; +}; + +struct SerialCfgParam +{ + struct SerialDataCfg data_cfg; + struct SerialHwCfg hw_cfg; +}; + +struct SerialDriver; + +struct SerialDrvDone +{ + uint32 (*init) (struct SerialDriver *serial_drv, struct BusConfigureInfo *configure_info); + uint32 (*configure) (struct SerialDriver *serial_drv, int serial_operation_cmd); +}; + +struct SerialDriver +{ + struct Driver driver; + const struct SerialDrvDone *drv_done; + + uint32 (*configure) (void *drv, struct BusConfigureInfo *configure_info); + + void *private_data; +}; + +struct SerialBus +{ + struct Bus bus; + + void *private_data; +}; + +/*Register the serial bus*/ +int SerialBusInit(struct SerialBus *serial_bus, const char *bus_name); + +/*Register the serial driver*/ +int SerialDriverInit(struct SerialDriver *serial_driver, const char *driver_name); + +/*Release the serial bus*/ +int SerialReleaseBus(struct SerialBus *serial_bus); + +/*Register the serial driver to the serial bus*/ +int SerialDriverAttachToBus(const char *drv_name, const char *bus_name); + +/*Register the driver, manage with the double linklist*/ +int SerialDriverRegister(struct Driver *driver); + +/*Find the regiter driver*/ +DriverType SerialDriverFind(const char *drv_name, enum DriverType_e drv_type); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/Ubiquitous/XiZi/resources/include/bus_spi.h b/Ubiquitous/XiZi/resources/include/bus_spi.h new file mode 100644 index 0000000..0439ad1 --- /dev/null +++ b/Ubiquitous/XiZi/resources/include/bus_spi.h @@ -0,0 +1,66 @@ +/* +* Copyright (c) 2020 AIIT XUOS Lab +* XiUOS is licensed under Mulan PSL v2. +* You can use this software according to the terms and conditions of the Mulan PSL v2. +* You may obtain a copy of Mulan PSL v2 at: +* http://license.coscl.org.cn/MulanPSL2 +* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, +* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, +* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. +* See the Mulan PSL v2 for more details. +*/ + +/** +* @file bus_spi.h +* @brief define spi bus and drv function using bus driver framework +* @version 1.0 +* @author AIIT XUOS Lab +* @date 2021-04-24 +*/ + +#ifndef BUS_SPI_H +#define BUS_SPI_H + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +struct SpiDriver +{ + struct Driver driver; + + uint32 (*configure) (void *drv, struct BusConfigureInfo *configure_info); +}; + +struct SpiBus +{ + struct Bus bus; + + void *private_data; +}; + +/*Register the spi bus*/ +int SpiBusInit(struct SpiBus *spi_bus, const char *bus_name); + +/*Register the spi driver*/ +int SpiDriverInit(struct SpiDriver *spi_driver, const char *driver_name); + +/*Release the spi device*/ +int SpiReleaseBus(struct SpiBus *spi_bus); + +/*Register the spi driver to the spi bus*/ +int SpiDriverAttachToBus(const char *drv_name, const char *bus_name); + +/*Register the driver, manage with the double linklist*/ +int SpiDriverRegister(struct Driver *driver); + +/*Find the register driver*/ +DriverType SpiDriverFind(const char *drv_name, enum DriverType_e drv_type); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/Ubiquitous/XiZi/resources/include/bus_touch.h b/Ubiquitous/XiZi/resources/include/bus_touch.h new file mode 100644 index 0000000..5376875 --- /dev/null +++ b/Ubiquitous/XiZi/resources/include/bus_touch.h @@ -0,0 +1,65 @@ +/* +* Copyright (c) 2020 AIIT XUOS Lab +* XiUOS is licensed under Mulan PSL v2. +* You can use this software according to the terms and conditions of the Mulan PSL v2. +* You may obtain a copy of Mulan PSL v2 at: +* http://license.coscl.org.cn/MulanPSL2 +* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, +* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, +* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. +* See the Mulan PSL v2 for more details. +*/ + +/** +* @file bus_touch.h +* @brief define touch bus and drv function using bus driver framework +* @version 1.0 +* @author AIIT XUOS Lab +* @date 2021-04-24 +*/ + +#ifndef BUS_TOUCH_H +#define BUS_TOUCH_H + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +struct TouchDriver +{ + struct Driver driver; + uint32 (*configure) (void *drv, struct BusConfigureInfo *configure_info); +}; + +struct TouchBus +{ + struct Bus bus; + + void *private_data; +}; + +/*Register the touch bus*/ +int TouchBusInit(struct TouchBus *touch_bus, const char *bus_name); + +/*Register the touch driver*/ +int TouchDriverInit(struct TouchDriver *touch_driver, const char *driver_name); + +/*Release the touch device*/ +int TouchReleaseBus(struct TouchBus *touch_bus); + +/*Register the touch driver to the touch bus*/ +int TouchDriverAttachToBus(const char *drv_name, const char *bus_name); + +/*Register the driver, manage with the double linklist*/ +int TouchDriverRegister(struct Driver *driver); + +/*Find the register driver*/ +DriverType TouchDriverFind(const char *drv_name, enum DriverType_e drv_type); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/Ubiquitous/XiZi/resources/include/bus_usb.h b/Ubiquitous/XiZi/resources/include/bus_usb.h new file mode 100644 index 0000000..fe8b0db --- /dev/null +++ b/Ubiquitous/XiZi/resources/include/bus_usb.h @@ -0,0 +1,68 @@ +/* +* Copyright (c) 2020 AIIT XUOS Lab +* XiUOS is licensed under Mulan PSL v2. +* You can use this software according to the terms and conditions of the Mulan PSL v2. +* You may obtain a copy of Mulan PSL v2 at: +* http://license.coscl.org.cn/MulanPSL2 +* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, +* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, +* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. +* See the Mulan PSL v2 for more details. +*/ + +/** +* @file bus_usb.h +* @brief define usb bus and drv function using bus driver framework +* @version 1.0 +* @author AIIT XUOS Lab +* @date 2021-04-24 +*/ + +#ifndef BUS_USB_H +#define BUS_USB_H + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +struct UsbDriver +{ + struct Driver driver; + + uint32 (*configure)(void *drv, struct BusConfigureInfo *configure_info); + + void *private_data; +}; + +struct UsbBus +{ + struct Bus bus; + + void *private_data; +}; + +/*Register the USB bus*/ +int UsbBusInit(struct UsbBus *usb_bus, const char *bus_name); + +/*Register the USB driver*/ +int UsbDriverInit(struct UsbDriver *usb_driver, const char *driver_name); + +/*Release the USB device*/ +int UsbReleaseBus(struct UsbBus *usb_bus); + +/*Register the USB driver to the USB bus*/ +int UsbDriverAttachToBus(const char *drv_name, const char *bus_name); + +/*Register the driver, manage with the double linklist*/ +int UsbDriverRegister(struct Driver *driver); + +/*Find the register driver*/ +DriverType UsbDriverFind(const char *drv_name, enum DriverType_e drv_type); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/Ubiquitous/XiZi/resources/include/bus_wdt.h b/Ubiquitous/XiZi/resources/include/bus_wdt.h new file mode 100644 index 0000000..c96c94b --- /dev/null +++ b/Ubiquitous/XiZi/resources/include/bus_wdt.h @@ -0,0 +1,66 @@ +/* +* Copyright (c) 2020 AIIT XUOS Lab +* XiUOS is licensed under Mulan PSL v2. +* You can use this software according to the terms and conditions of the Mulan PSL v2. +* You may obtain a copy of Mulan PSL v2 at: +* http://license.coscl.org.cn/MulanPSL2 +* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, +* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, +* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. +* See the Mulan PSL v2 for more details. +*/ + +/** +* @file bus_wdt.h +* @brief define wdt bus and drv function using bus driver framework +* @version 1.0 +* @author AIIT XUOS Lab +* @date 2021-04-24 +*/ + +#ifndef BUS_WDT_H +#define BUS_WDT_H + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +struct WdtDriver +{ + struct Driver driver; + uint32 (*configure) (void *drv, struct BusConfigureInfo *ConfigureInfo); + void *private_data; +}; + +struct WdtBus +{ + struct Bus bus; + + void *private_data; +}; + +/*Register the wdt bus*/ +int WdtBusInit(struct WdtBus *wdt_bus, const char *bus_name); + +/*Register the wdt driver*/ +int WdtDriverInit(struct WdtDriver *wdt_driver, const char *driver_name); + +/*Release the wdt device*/ +int WdtReleaseBus(struct WdtBus *wdt_bus); + +/*Register the wdt driver to the wdt bus*/ +int WdtDriverAttachToBus(const char *drv_name, const char *bus_name); + +/*Register the driver, manage with the double linklist*/ +int WdtDriverRegister(struct Driver *driver); + +/*Find the register driver*/ +DriverType WdtDriverFind(const char *drv_name); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/Ubiquitous/XiZi/resources/include/dev_adc.h b/Ubiquitous/XiZi/resources/include/dev_adc.h new file mode 100644 index 0000000..e1d2b51 --- /dev/null +++ b/Ubiquitous/XiZi/resources/include/dev_adc.h @@ -0,0 +1,61 @@ +/* +* Copyright (c) 2020 AIIT XUOS Lab +* XiUOS is licensed under Mulan PSL v2. +* You can use this software according to the terms and conditions of the Mulan PSL v2. +* You may obtain a copy of Mulan PSL v2 at: +* http://license.coscl.org.cn/MulanPSL2 +* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, +* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, +* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. +* See the Mulan PSL v2 for more details. +*/ + +/** +* @file dev_adc.h +* @brief define adc dev function using bus driver framework +* @version 1.1 +* @author AIIT XUOS Lab +* @date 2021-12-28 +*/ + +#ifndef DEV_ADC_H +#define DEV_ADC_H + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +struct AdcHardwareDevice; + +struct AdcDevDone +{ + uint32 (*open) (void *dev); + uint32 (*close) (void *dev); + uint32 (*write) (void *dev,struct BusBlockWriteParam *write_param); + uint32 (*read) (void *dev, struct BusBlockReadParam *read_param); +}; + +struct AdcHardwareDevice +{ + struct HardwareDev haldev; + const struct AdcDevDone *adc_dev_done; + + void *private_data; +}; + +/*Register the ADC device*/ +int AdcDeviceRegister(struct AdcHardwareDevice *adc_device, void *adc_param, const char *device_name); + +/*Register the ADC device to the ADC bus*/ +int AdcDeviceAttachToBus(const char *dev_name, const char *bus_name); + +/*Find the register ADC device*/ +HardwareDevType AdcDeviceFind(const char *dev_name, enum DevType dev_type); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/Ubiquitous/XiZi/resources/include/dev_can.h b/Ubiquitous/XiZi/resources/include/dev_can.h new file mode 100644 index 0000000..0900500 --- /dev/null +++ b/Ubiquitous/XiZi/resources/include/dev_can.h @@ -0,0 +1,79 @@ +/* +* Copyright (c) 2020 AIIT XUOS Lab +* XiUOS is licensed under Mulan PSL v2. +* You can use this software according to the terms and conditions of the Mulan PSL v2. +* You may obtain a copy of Mulan PSL v2 at: +* http://license.coscl.org.cn/MulanPSL2 +* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, +* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, +* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. +* See the Mulan PSL v2 for more details. +*/ + +/** +* @file dev_can.h +* @brief define can dev function using bus driver framework +* @version 1.0 +* @author AIIT XUOS Lab +* @date 2021-04-24 +*/ + +#ifndef DEV_CAN_H +#define DEV_CAN_H + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +struct CanDriverConfigure +{ + uint8 tsjw; + uint8 tbs2 ; + uint8 tbs1; + uint8 mode; + uint16 brp; +}; + +struct CanSendConfigure +{ + uint32 stdid; + uint32 exdid; + uint8 ide; + uint8 rtr; + uint8 data_lenth; + uint8 *data; +}; + +struct CanDevDone +{ + uint32 (*open) (void *dev); + uint32 (*close) (void *dev); + uint32 (*write) (void *dev,struct BusBlockWriteParam *write_param); + uint32 (*read) (void *dev, struct BusBlockReadParam *read_param); + +}; + +struct CanHardwareDevice +{ + struct HardwareDev haldev; + const struct CanDevDone *dev_done; + + void *private_data; +}; + +/*Register the CAN device*/ +int CanDeviceRegister(struct CanHardwareDevice *can_device, void *can_param, const char *device_name); + +/*Register the CAN device to the CAN bus*/ +int CanDeviceAttachToBus(const char *dev_name, const char *bus_name); + +/*Find the register CAN device*/ +HardwareDevType CanDeviceFind(const char *dev_name, enum DevType dev_type); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/Ubiquitous/XiZi/resources/include/dev_dac.h b/Ubiquitous/XiZi/resources/include/dev_dac.h new file mode 100644 index 0000000..d51bbcc --- /dev/null +++ b/Ubiquitous/XiZi/resources/include/dev_dac.h @@ -0,0 +1,61 @@ +/* +* Copyright (c) 2020 AIIT XUOS Lab +* XiUOS is licensed under Mulan PSL v2. +* You can use this software according to the terms and conditions of the Mulan PSL v2. +* You may obtain a copy of Mulan PSL v2 at: +* http://license.coscl.org.cn/MulanPSL2 +* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, +* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, +* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. +* See the Mulan PSL v2 for more details. +*/ + +/** +* @file dev_dac.h +* @brief define dac dev function using bus driver framework +* @version 2.0 +* @author AIIT XUOS Lab +* @date 2022-1-11 +*/ + +#ifndef DEV_DAC_H +#define DEV_DAC_H + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +struct DacHardwareDevice; + +struct DacDevDone +{ + uint32 (*open) (void *dev); + uint32 (*close) (void *dev); + uint32 (*write) (void *dev,struct BusBlockWriteParam *write_param); + uint32 (*read) (void *dev, struct BusBlockReadParam *read_param); +}; + +struct DacHardwareDevice +{ + struct HardwareDev haldev; + const struct DacDevDone *dac_dev_done; + + void *private_data; +}; + +/*Register the DAC device*/ +int DacDeviceRegister(struct DacHardwareDevice *dac_device, void *dac_param, const char *device_name); + +/*Register the DAC device to the DAC bus*/ +int DacDeviceAttachToBus(const char *dev_name, const char *bus_name); + +/*Find the register DAC device*/ +HardwareDevType DacDeviceFind(const char *dev_name, enum DevType dev_type); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/Ubiquitous/XiZi/resources/include/dev_hwtimer.h b/Ubiquitous/XiZi/resources/include/dev_hwtimer.h new file mode 100644 index 0000000..25baf75 --- /dev/null +++ b/Ubiquitous/XiZi/resources/include/dev_hwtimer.h @@ -0,0 +1,74 @@ +/* +* Copyright (c) 2020 AIIT XUOS Lab +* XiUOS is licensed under Mulan PSL v2. +* You can use this software according to the terms and conditions of the Mulan PSL v2. +* You may obtain a copy of Mulan PSL v2 at: +* http://license.coscl.org.cn/MulanPSL2 +* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, +* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, +* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. +* See the Mulan PSL v2 for more details. +*/ + +/** +* @file dev_hwtimer.h +* @brief define hwtimer dev function using bus driver framework +* @version 1.0 +* @author AIIT XUOS Lab +* @date 2021-04-24 +*/ + +#ifndef DEV_HWTIMER_H +#define DEV_HWTIMER_H + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +struct HwtimerCallBackInfo +{ + void (*timeout_callback) (void* param); + void *param; +}; + +struct HwtimerDeviceParam +{ + uint32 period_millisecond; + uint32 repeat; + struct HwtimerCallBackInfo cb_info; +}; + +struct HwtimerDevDone +{ + uint32 (*open) (void *dev); + uint32 (*close) (void *dev); + uint32 (*write) (void *dev,struct BusBlockWriteParam *write_param); + uint32 (*read) (void *dev, struct BusBlockReadParam *read_param); +}; + +struct HwtimerHardwareDevice +{ + struct HardwareDev haldev; + struct HwtimerDeviceParam hwtimer_param; + + const struct HwtimerDevDone *dev_done; + + void *private_data; +}; + +/*Register the hwtimer device*/ +int HwtimerDeviceRegister(struct HwtimerHardwareDevice *hwtimer_device, void *hwtimer_param, const char *device_name); + +/*Register the hwtimer device to the hwtimer bus*/ +int HwtimerDeviceAttachToBus(const char *dev_name, const char *bus_name); + +/*Find the register hwtimer device*/ +HardwareDevType HwtimerDeviceFind(const char *dev_name); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/Ubiquitous/XiZi/resources/include/dev_i2c.h b/Ubiquitous/XiZi/resources/include/dev_i2c.h new file mode 100644 index 0000000..9a3a227 --- /dev/null +++ b/Ubiquitous/XiZi/resources/include/dev_i2c.h @@ -0,0 +1,79 @@ +/* +* Copyright (c) 2020 AIIT XUOS Lab +* XiUOS is licensed under Mulan PSL v2. +* You can use this software according to the terms and conditions of the Mulan PSL v2. +* You may obtain a copy of Mulan PSL v2 at: +* http://license.coscl.org.cn/MulanPSL2 +* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, +* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, +* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. +* See the Mulan PSL v2 for more details. +*/ + +/** +* @file dev_i2c.h +* @brief define i2c dev function using bus driver framework +* @version 1.0 +* @author AIIT XUOS Lab +* @date 2021-04-24 +*/ + +#ifndef DEV_I2C_H +#define DEV_I2C_H + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +#define I2C_WR 0x0000 +#define I2C_RD (1u << 0) +#define I2C_ADDR_10BIT (1u << 2) +#define I2C_NO_START (1u << 4) +#define I2C_IGNORE_NACK (1u << 5) +#define I2C_NO_READ_ACK (1u << 6) + +struct I2cDataStandard +{ + uint16 addr; + uint16 flags; + uint16 len; + uint16 retries; + uint8 *buf; + + struct I2cDataStandard *next; +}; + +struct I2cHardwareDevice; + +struct I2cDevDone +{ + uint32 (*dev_open) (struct I2cHardwareDevice *i2c_device); + uint32 (*dev_close) (struct I2cHardwareDevice *i2c_device); + uint32 (*dev_write) (struct I2cHardwareDevice *i2c_device, struct I2cDataStandard *msg); + uint32 (*dev_read) (struct I2cHardwareDevice *i2c_device, struct I2cDataStandard *msg); +}; + +struct I2cHardwareDevice +{ + struct HardwareDev haldev; + const struct I2cDevDone *i2c_dev_done; + + uint16 i2c_dev_addr; +}; + +/*Register the I2C device*/ +int I2cDeviceRegister(struct I2cHardwareDevice *i2c_device, void *i2c_param, const char *device_name); + +/*Register the I2C device to the I2C bus*/ +int I2cDeviceAttachToBus(const char *dev_name, const char *bus_name); + +/*Find the register I2C device*/ +HardwareDevType I2cDeviceFind(const char *dev_name, enum DevType dev_type); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/Ubiquitous/XiZi/resources/include/dev_lcd.h b/Ubiquitous/XiZi/resources/include/dev_lcd.h new file mode 100644 index 0000000..7e940ca --- /dev/null +++ b/Ubiquitous/XiZi/resources/include/dev_lcd.h @@ -0,0 +1,113 @@ +/* +* Copyright (c) 2020 AIIT XUOS Lab +* XiUOS is licensed under Mulan PSL v2. +* You can use this software according to the terms and conditions of the Mulan PSL v2. +* You may obtain a copy of Mulan PSL v2 at: +* http://license.coscl.org.cn/MulanPSL2 +* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, +* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, +* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. +* See the Mulan PSL v2 for more details. +*/ + +/** +* @file dev_lcd.h +* @brief define lcd dev function using bus driver framework +* @version 1.0 +* @author AIIT XUOS Lab +* @date 2021-04-24 +*/ + +#ifndef DEV_LCD_H +#define DEV_LCD_H + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/*set the pen color*/ +#define WHITE 0xFFFF +#define BLACK 0x0000 +#define BLUE 0x001F +#define BRED 0xF81F +#define GRED 0xFFE0 +#define GBLUE 0x07FF +#define RED 0xF800 +#define MAGENTA 0xF81F +#define GREEN 0x07E0 +#define CYAN 0x7FFF +#define YELLOW 0xFFE0 +#define BROWN 0xBC40 +#define BRRED 0xFC07 +#define GRAY 0x8430 + +#define DARKBLUE 0x01CF//Navy blue +#define LIGHTBLUE 0x7D7C//Light blue +#define GRAYBLUE 0x5458//Gray blue +#define LIGHTGREEN 0x841F +#define LGRAY 0xC618 +#define LGRAYBLUE 0xA651 +#define LBBLUE 0x2B12 + +typedef struct +{ + uint16 x_pos; + uint16 y_pos; + uint16 width; + uint16 height; + uint8 font_size; + uint8 *addr; + uint16 font_color; + uint16 back_color; +}LcdStringParam; + +typedef struct +{ + uint16 x_startpos; + uint16 x_endpos; + uint16 y_startpos; + uint16 y_endpos; + void *pixel_color; +}LcdPixelParam; + +typedef struct +{ + char type;//0: string; 1 : dot + LcdPixelParam pixel_info; + LcdStringParam string_info; +}LcdWriteParam; + +struct LcdDevDone +{ + uint32 (*open) (void *dev); + uint32 (*close) (void *dev); + uint32 (*write) (void *dev, struct BusBlockWriteParam *write_param); + uint32 (*read) (void *dev, struct BusBlockReadParam *read_param); +}; + +struct LcdHardwareDevice +{ + struct HardwareDev haldev; + + const struct LcdDevDone *dev_done; + + void *private_data; +}; + +/*Register the lcd device*/ +int LcdDeviceRegister(struct LcdHardwareDevice *lcd_device, void *lcd_param, const char *device_name); + +/*Register the lcd device to the lcd bus*/ +int LcdDeviceAttachToBus(const char *dev_name, const char *bus_name); + +/*Find the register lcd device*/ +HardwareDevType LcdDeviceFind(const char *dev_name, enum DevType dev_type); + +#ifdef __cplusplus +} +#endif + + +#endif \ No newline at end of file diff --git a/Ubiquitous/XiZi/resources/include/dev_pin.h b/Ubiquitous/XiZi/resources/include/dev_pin.h new file mode 100644 index 0000000..ed9b2ce --- /dev/null +++ b/Ubiquitous/XiZi/resources/include/dev_pin.h @@ -0,0 +1,111 @@ +/* +* Copyright (c) 2020 AIIT XUOS Lab +* XiUOS is licensed under Mulan PSL v2. +* You can use this software according to the terms and conditions of the Mulan PSL v2. +* You may obtain a copy of Mulan PSL v2 at: +* http://license.coscl.org.cn/MulanPSL2 +* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, +* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, +* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. +* See the Mulan PSL v2 for more details. +*/ + +/** +* @file dev_pin.h +* @brief define pin dev function using bus driver framework +* @version 1.0 +* @author AIIT XUOS Lab +* @date 2021-04-24 +*/ + +#ifndef DEV_PIN_H +#define DEV_PIN_H + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +#define GPIO_LOW 0x00 +#define GPIO_HIGH 0x01 + +#define GPIO_CFG_OUTPUT 0x00 +#define GPIO_CFG_INPUT 0x01 +#define GPIO_CFG_INPUT_PULLUP 0x02 +#define GPIO_CFG_INPUT_PULLDOWN 0x03 +#define GPIO_CFG_OUTPUT_OD 0x04 + +#define GPIO_IRQ_EDGE_RISING 0x00 +#define GPIO_IRQ_EDGE_FALLING 0x01 +#define GPIO_IRQ_EDGE_BOTH 0x02 +#define GPIO_IRQ_LEVEL_HIGH 0x03 +#define GPIO_IRQ_LEVEL_LOW 0x04 + +#define GPIO_CONFIG_MODE 0xffffffff +#define GPIO_IRQ_REGISTER 0xfffffffe +#define GPIO_IRQ_FREE 0xfffffffd +#define GPIO_IRQ_DISABLE 0xfffffffc +#define GPIO_IRQ_ENABLE 0xfffffffb + +struct PinDevIrq +{ + int irq_mode;//< RISING/FALLING/HIGH/LOW + void (*hdr) (void *args);//< callback function + void *args;//< the params of callback function +}; + +struct PinParam +{ + int cmd;//< cmd:GPIO_CONFIG_MODE/GPIO_IRQ_REGISTER/GPIO_IRQ_FREE/GPIO_IRQ_DISABLE/GPIO_IRQ_ENABLE + x_base pin;//< pin number + int mode;//< pin mode: input/output + struct PinDevIrq irq_set;//< pin irq set + uint64 arg; +}; + +struct PinStat +{ + x_base pin;//< pin number + uint16 val;//< pin level +}; + +struct PinIrqHdr +{ + int16 pin; + uint16 mode; + void (*hdr) (void *args); + void *args; +}; + +struct PinDevDone +{ + uint32 (*open) (void *dev); + uint32 (*close) (void *dev); + uint32 (*write) (void *dev, struct BusBlockWriteParam *write_param); + uint32 (*read) (void *dev, struct BusBlockReadParam *read_param); +}; + +struct PinHardwareDevice +{ + struct HardwareDev haldev; + + const struct PinDevDone *dev_done; + + void *private_data; +}; + +/*Register the Pin device*/ +int PinDeviceRegister(struct PinHardwareDevice *pin_device, void *pin_param, const char *device_name); + +/*Register the Pin Device to the Pin bus*/ +int PinDeviceAttachToBus(const char *dev_name, const char *bus_name); + +/*Find the register Pin device*/ +HardwareDevType PinDeviceFind(const char *dev_name, enum DevType dev_type); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/Ubiquitous/XiZi/resources/include/dev_rtc.h b/Ubiquitous/XiZi/resources/include/dev_rtc.h new file mode 100644 index 0000000..0abbace --- /dev/null +++ b/Ubiquitous/XiZi/resources/include/dev_rtc.h @@ -0,0 +1,60 @@ +/* +* Copyright (c) 2020 AIIT XUOS Lab +* XiUOS is licensed under Mulan PSL v2. +* You can use this software according to the terms and conditions of the Mulan PSL v2. +* You may obtain a copy of Mulan PSL v2 at: +* http://license.coscl.org.cn/MulanPSL2 +* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, +* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, +* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. +* See the Mulan PSL v2 for more details. +*/ + +/** +* @file dev_rtc.h +* @brief define rtc dev function using bus driver framework +* @version 1.0 +* @author AIIT XUOS Lab +* @date 2021-04-24 +*/ + +#ifndef DEV_RTC_H +#define DEV_RTC_H + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +struct RtcDevDone +{ + uint32 (*open) (void *dev); + uint32 (*close) (void *dev); + uint32 (*write) (void *dev, struct BusBlockWriteParam *datacfg); + uint32 (*read) (void *dev, struct BusBlockReadParam *datacfg); +}; + +struct RtcHardwareDevice +{ + struct HardwareDev haldev; + + const struct RtcDevDone *dev_done; + + void *private_data; +}; + +/*Register the rtc device*/ +int RtcDeviceRegister(struct RtcHardwareDevice *rtc_device, void *rtc_param, const char *device_name); + +/*Register the rtc device to the rtc bus*/ +int RtcDeviceAttachToBus(const char *dev_name, const char *bus_name); + +/*Find the register rtc device*/ +HardwareDevType RtcDeviceFind(const char *dev_name, enum DevType dev_type); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/Ubiquitous/XiZi/resources/include/dev_sdio.h b/Ubiquitous/XiZi/resources/include/dev_sdio.h new file mode 100644 index 0000000..56945c5 --- /dev/null +++ b/Ubiquitous/XiZi/resources/include/dev_sdio.h @@ -0,0 +1,60 @@ +/* +* Copyright (c) 2020 AIIT XUOS Lab +* XiUOS is licensed under Mulan PSL v2. +* You can use this software according to the terms and conditions of the Mulan PSL v2. +* You may obtain a copy of Mulan PSL v2 at: +* http://license.coscl.org.cn/MulanPSL2 +* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, +* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, +* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. +* See the Mulan PSL v2 for more details. +*/ + +/** +* @file dev_sdio.h +* @brief define sdio dev function using bus driver framework +* @version 1.0 +* @author AIIT XUOS Lab +* @date 2021-04-24 +*/ + +#ifndef DEV_SDIO_H +#define DEV_SDIO_H + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +struct SdioDevDone +{ + uint32 (*open) (void *dev); + uint32 (*close) (void *dev); + uint32 (*write) (void *dev, struct BusBlockWriteParam *write_param); + uint32 (*read) (void *dev, struct BusBlockReadParam *read_param); +}; + +struct SdioHardwareDevice +{ + struct HardwareDev haldev; + + struct SdioDevDone *dev_done; + + void *private_data; +}; + +/*Register the sdio device*/ +int SdioDeviceRegister(struct SdioHardwareDevice *sdio_device, const char *device_name); + +/*Register the sdio device to the sdio bus*/ +int SdioDeviceAttachToBus(const char *dev_name, const char *bus_name); + +/*Find the register sdio device*/ +HardwareDevType SdioDeviceFind(const char *dev_name); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/Ubiquitous/XiZi/resources/include/dev_serial.h b/Ubiquitous/XiZi/resources/include/dev_serial.h new file mode 100644 index 0000000..146202f --- /dev/null +++ b/Ubiquitous/XiZi/resources/include/dev_serial.h @@ -0,0 +1,158 @@ +/* +* Copyright (c) 2020 AIIT XUOS Lab +* XiUOS is licensed under Mulan PSL v2. +* You can use this software according to the terms and conditions of the Mulan PSL v2. +* You may obtain a copy of Mulan PSL v2 at: +* http://license.coscl.org.cn/MulanPSL2 +* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, +* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, +* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. +* See the Mulan PSL v2 for more details. +*/ + +/** +* @file dev_serial.h +* @brief define serial dev function using bus driver framework +* @version 1.0 +* @author AIIT XUOS Lab +* @date 2021-04-24 +*/ + +#ifndef DEV_SERIAL_H +#define DEV_SERIAL_H + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +#define BAUD_RATE_2400 2400 +#define BAUD_RATE_4800 4800 +#define BAUD_RATE_9600 9600 +#define BAUD_RATE_19200 19200 +#define BAUD_RATE_38400 38400 +#define BAUD_RATE_57600 57600 +#define BAUD_RATE_115200 115200 +#define BAUD_RATE_230400 230400 +#define BAUD_RATE_460800 460800 +#define BAUD_RATE_921600 921600 +#define BAUD_RATE_2000000 2000000 +#define BAUD_RATE_3000000 3000000 + +#define DATA_BITS_5 5 +#define DATA_BITS_6 6 +#define DATA_BITS_7 7 +#define DATA_BITS_8 8 +#define DATA_BITS_9 9 + +#define STOP_BITS_1 1 +#define STOP_BITS_2 2 +#define STOP_BITS_3 3 +#define STOP_BITS_4 4 + +#define PARITY_NONE 1 +#define PARITY_ODD 2 +#define PARITY_EVEN 3 + +#define BIT_ORDER_LSB 1 +#define BIT_ORDER_MSB 2 + +#define NRZ_NORMAL 1 +#define NRZ_INVERTED 2 + +#ifndef SERIAL_RB_BUFSZ +#define SERIAL_RB_BUFSZ 128 +#endif + +#define SERIAL_EVENT_RX_IND 0x01 +#define SERIAL_event_id_tX_DONE 0x02 +#define SERIAL_EVENT_RX_DMADONE 0x03 +#define SERIAL_event_id_tX_DMADONE 0x04 +#define SERIAL_EVENT_RX_TIMEOUT 0x05 + +#define SERIAL_DMA_RX 0x01 +#define SERIAL_DMA_TX 0x02 +#define KEY_LENGTH 8 + +struct SerialTx +{ + int32 serial_txfifo_sem; + + x_bool serial_dma_enable; + queue serial_dma_queue; +}; + +struct SerialRx +{ + uint8 *serial_rx_buffer; + uint16 serial_send_num; + uint16 serial_recv_num; + x_bool serial_rx_full; + + x_bool serial_dma_enable; +}; + +struct SerialDataTransferParam +{ + struct SerialTx *serial_tx; + + struct SerialRx *serial_rx; +}; + +struct SerialDevParam +{ + uint8 ext_uart_no; + + uint16 serial_work_mode; + uint16 serial_set_mode; + uint16 serial_stream_mode; +}; + +struct SerialHardwareDevice; + +struct SerialHwDevDone +{ + int (*put_char) (struct SerialHardwareDevice *serial_dev, char c); + int (*get_char) (struct SerialHardwareDevice *serial_dev); + int (*dmatransfer) (struct SerialHardwareDevice *serial_dev, uint8 *buf, x_size_t size, int direction); +}; + +struct SerialDevDone +{ + uint32 (*open) (void *dev); + uint32 (*close) (void *dev); + uint32 (*write) (void *dev, struct BusBlockWriteParam *datacfg); + uint32 (*read) (void *dev, struct BusBlockReadParam *datacfg); +}; + +struct SerialHardwareDevice +{ + struct HardwareDev haldev; + struct SerialHwDevDone *hwdev_done; + + struct SerialDataTransferParam serial_fifo; + + uint32 ext_serial_mode; + const struct SerialDevDone *dev_done; + + void *private_data; +}; + +/*Register the serial device*/ +int SerialDeviceRegister(struct SerialHardwareDevice *serial_device, void *serial_param, const char *device_name); + +/*Register the serial device to the serial bus*/ +int SerialDeviceAttachToBus(const char *dev_name, const char *bus_name); + +/*Find the register serial device*/ +HardwareDevType SerialDeviceFind(const char *dev_name, enum DevType dev_type); + +/*Set serial isr function*/ +void SerialSetIsr(struct SerialHardwareDevice *serial_dev, int event); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/Ubiquitous/XiZi/resources/include/dev_spi.h b/Ubiquitous/XiZi/resources/include/dev_spi.h new file mode 100644 index 0000000..f0bb6fd --- /dev/null +++ b/Ubiquitous/XiZi/resources/include/dev_spi.h @@ -0,0 +1,139 @@ +/* +* Copyright (c) 2020 AIIT XUOS Lab +* XiUOS is licensed under Mulan PSL v2. +* You can use this software according to the terms and conditions of the Mulan PSL v2. +* You may obtain a copy of Mulan PSL v2 at: +* http://license.coscl.org.cn/MulanPSL2 +* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, +* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, +* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. +* See the Mulan PSL v2 for more details. +*/ + +/** +* @file dev_spi.h +* @brief define spi dev function using bus driver framework +* @version 1.0 +* @author AIIT XUOS Lab +* @date 2021-04-24 +*/ + +#ifndef DEV_SPI_H +#define DEV_SPI_H + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +#define SPI_MAX_CLOCK 40000000 +#define spi_device_max_num 4 + +#define SPI_LINE_CPHA (1<<0) +#define SPI_LINE_CPOL (1<<1) + +#define SPI_LSB (0<<2) +#define SPI_MSB (1<<2) + +#define SPI_MASTER (0<<3) +#define DEV_SPI_SLAVE (1<<3) + +#define SPI_MODE_0 (0 | 0) +#define SPI_MODE_1 (0 | SPI_LINE_CPHA) +#define SPI_MODE_2 (SPI_LINE_CPOL | 0) +#define SPI_MODE_3 (SPI_LINE_CPOL | SPI_LINE_CPHA) +#define SPI_MODE_MASK (SPI_LINE_CPHA | SPI_LINE_CPOL | SPI_MSB) + +#define SPI_CS_HIGH (1<<4) +#define SPI_NO_CS (1<<5) +#define SPI_3WIRE (1<<6) +#define SPI_READY (1<<7) + +struct SpiDataStandard +{ + uint8 spi_chip_select; + uint8 spi_cs_release; + + const uint8 *tx_buff; + uint32 tx_len; + + uint8 *rx_buff; + uint32 rx_len; + + uint32 length; + struct SpiDataStandard *next; +}; + +struct SpiMasterParam +{ + uint8 spi_work_mode;//CPOL CPHA + uint8 spi_frame_format;//frame format + uint8 spi_data_bit_width;//bit width + uint8 spi_data_endian;//little endian：0，big endian：1 + uint32 spi_maxfrequency;//work frequency +}; + +struct SpiDmaParam +{ + uint8 spi_master_id; + uint8 spi_dmac_txchannel; + uint8 spi_dmac_rxchannel; +}; + +struct SpiSlaveParam +{ + uint8 spi_slave_id; + uint8 spi_cs_gpio_pin; + uint8 spi_cs_select_id; +}; + +typedef struct +{ + struct SpiDmaParam *spi_dma_param; + + struct SpiSlaveParam *spi_slave_param; + + struct SpiMasterParam *spi_master_param; + +}SpiDeviceParam; + +struct SpiHardwareDevice; + +struct SpiDevDone +{ + uint32 (*dev_open) (struct SpiHardwareDevice *dev); + uint32 (*dev_close) (struct SpiHardwareDevice *dev); + uint32 (*dev_write) (struct SpiHardwareDevice *dev, struct SpiDataStandard *msg); + uint32 (*dev_read) (struct SpiHardwareDevice *dev, struct SpiDataStandard *msg); +}; + +struct SpiHardwareDevice +{ + struct HardwareDev haldev; + SpiDeviceParam spi_param; + + x_bool spi_dev_flag; + + const struct SpiDevDone *spi_dev_done; + + void *private_data; +}; + +/*Register the spi device*/ +int SpiDeviceRegister(struct SpiHardwareDevice *spi_device, void *spi_param, const char *device_name); + +/*Register the spi device to the spi bus*/ +int SpiDeviceAttachToBus(const char *dev_name, const char *bus_name); + +/*Find the register spi device*/ +HardwareDevType SpiDeviceFind(const char *dev_name, enum DevType dev_type); + +/*Configure the cs pin of spi dev*/ +int SpiDevConfigureCs(struct HardwareDev *dev, uint8 spi_chip_select, uint8 spi_cs_release); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/Ubiquitous/XiZi/resources/include/dev_touch.h b/Ubiquitous/XiZi/resources/include/dev_touch.h new file mode 100644 index 0000000..7b82da1 --- /dev/null +++ b/Ubiquitous/XiZi/resources/include/dev_touch.h @@ -0,0 +1,66 @@ +/* +* Copyright (c) 2020 AIIT XUOS Lab +* XiUOS is licensed under Mulan PSL v2. +* You can use this software according to the terms and conditions of the Mulan PSL v2. +* You may obtain a copy of Mulan PSL v2 at: +* http://license.coscl.org.cn/MulanPSL2 +* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, +* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, +* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. +* See the Mulan PSL v2 for more details. +*/ + +/** +* @file dev_touch.h +* @brief define touch dev function using bus driver framework +* @version 1.0 +* @author AIIT XUOS Lab +* @date 2021-04-24 +*/ + +#ifndef DEV_TOUCH_H +#define DEV_TOUCH_H + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +struct TouchDataStandard +{ + uint16 x; + uint16 y; +}; + +struct TouchDevDone +{ + uint32 (*open) (void *dev); + uint32 (*close) (void *dev); + uint32 (*write) (void *dev,struct BusBlockWriteParam *write_param); + uint32 (*read) (void *dev, struct BusBlockReadParam *read_param); +}; + +struct TouchHardwareDevice +{ + struct HardwareDev haldev; + + const struct TouchDevDone *dev_done; + + void *private_data; +}; + +/*Register the touch device*/ +int TouchDeviceRegister(struct TouchHardwareDevice *touch_device, void *touch_param, const char *device_name); + +/*Register the touch device to the touch bus*/ +int TouchDeviceAttachToBus(const char *dev_name, const char *bus_name); + +/*Find the register touch device*/ +HardwareDevType TouchDeviceFind(const char *dev_name, enum DevType dev_type); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/Ubiquitous/XiZi/resources/include/dev_usb.h b/Ubiquitous/XiZi/resources/include/dev_usb.h new file mode 100644 index 0000000..52fc9fc --- /dev/null +++ b/Ubiquitous/XiZi/resources/include/dev_usb.h @@ -0,0 +1,62 @@ +/* +* Copyright (c) 2020 AIIT XUOS Lab +* XiUOS is licensed under Mulan PSL v2. +* You can use this software according to the terms and conditions of the Mulan PSL v2. +* You may obtain a copy of Mulan PSL v2 at: +* http://license.coscl.org.cn/MulanPSL2 +* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, +* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, +* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. +* See the Mulan PSL v2 for more details. +*/ + +/** +* @file dev_usb.h +* @brief define usb dev function using bus driver framework +* @version 1.0 +* @author AIIT XUOS Lab +* @date 2021-04-24 +*/ + +#ifndef DEV_USB_H +#define DEV_USB_H + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +#define UDISK_USB_BUS_NAME USB_BUS_NAME +#define UDISK_USB_DEVICE_NAME USB_DEVICE_NAME + +struct UsbDevDone +{ + uint32 (*open) (void *dev); + uint32 (*close) (void *dev); + uint32 (*write) (void *dev, struct BusBlockWriteParam *write_param); + uint32 (*read) (void *dev, struct BusBlockReadParam *read_param); +}; + +struct UsbHardwareDevice +{ + struct HardwareDev haldev; + const struct UsbDevDone *dev_done; + + void *private_data; +}; + +/*Register the USB device*/ +int USBDeviceRegister(struct UsbHardwareDevice *usb_device, void *usb_param, const char *device_name); + +/*Register the USB device to the USB bus*/ +int USBDeviceAttachToBus(const char *dev_name, const char *bus_name); + +/*Find the register USB device*/ +HardwareDevType USBDeviceFind(const char *dev_name, enum DevType dev_type); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/Ubiquitous/XiZi/resources/include/dev_wdt.h b/Ubiquitous/XiZi/resources/include/dev_wdt.h new file mode 100644 index 0000000..b846afb --- /dev/null +++ b/Ubiquitous/XiZi/resources/include/dev_wdt.h @@ -0,0 +1,60 @@ +/* +* Copyright (c) 2020 AIIT XUOS Lab +* XiUOS is licensed under Mulan PSL v2. +* You can use this software according to the terms and conditions of the Mulan PSL v2. +* You may obtain a copy of Mulan PSL v2 at: +* http://license.coscl.org.cn/MulanPSL2 +* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, +* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, +* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. +* See the Mulan PSL v2 for more details. +*/ + +/** +* @file dev_wdt.h +* @brief define wdt dev function using bus driver framework +* @version 1.0 +* @author AIIT XUOS Lab +* @date 2021-04-24 +*/ + +#ifndef DEV_WDT_H +#define DEV_WDT_H + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +struct WdtDevDone +{ + uint32 (*open) (void *dev); + uint32 (*close) (void *dev); + uint32 (*write) (void *dev, struct BusBlockWriteParam *write_param); + uint32 (*read) (void *dev, struct BusBlockReadParam *read_param); +}; + +struct WdtHardwareDevice +{ + struct HardwareDev haldev; + + const struct WdtDevDone *dev_done; + + void *private_data; +}; + +/*Register the wdt device*/ +int WdtDeviceRegister(struct WdtHardwareDevice *wdt_device, const char *device_name); + +/*Register the wdt device to the wdt bus*/ +int WdtDeviceAttachToBus(const char *dev_name, const char *bus_name); + +/*Find the register wdt device*/ +HardwareDevType WdtDeviceFind(const char *dev_name); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/Ubiquitous/XiZi/resources/include/device.h b/Ubiquitous/XiZi/resources/include/device.h new file mode 100644 index 0000000..5c2d49a --- /dev/null +++ b/Ubiquitous/XiZi/resources/include/device.h @@ -0,0 +1,107 @@ +/* +* Copyright (c) 2020 AIIT XUOS Lab +* XiUOS is licensed under Mulan PSL v2. +* You can use this software according to the terms and conditions of the Mulan PSL v2. +* You may obtain a copy of Mulan PSL v2 at: +* http://license.coscl.org.cn/MulanPSL2 +* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, +* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, +* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. +* See the Mulan PSL v2 for more details. +*/ + +/** +* @file device.h +* @brief support to include RESOURCES of all drivers +* @version 1.0 +* @author AIIT XUOS Lab +* @date 2021-04-24 +*/ + +#ifndef DEVICE_H +#define DEVICE_H + +#include + +#include +#include +#include +#include +#include + +#ifdef RESOURCES_RTC +#include +#include +#endif + +#ifdef RESOURCES_SPI +#include +#include +#endif + +#ifdef RESOURCES_TOUCH +#include +#include +#endif + +#ifdef RESOURCES_LCD +#include +#include +#endif + +#ifdef RESOURCES_USB +#include +#include +#ifdef RESOURCES_USB_HOST +#include +#endif +#endif + +#ifdef RESOURCES_SERIAL +#include +#include +void InstallConsole(const char *bus_name, const char *drv_name, const char *dev_name); +HardwareDevType ObtainConsole(void); +#endif + +#ifdef RESOURCES_I2C +#include +#include +#endif + +#ifdef RESOURCES_WDT +#include +#include +#endif + +#ifdef RESOURCES_SDIO +#include +#include +#endif + +#ifdef RESOURCES_PIN +#include +#include +#endif + +#ifdef RESOURCES_CAN +#include +#include +#endif + +#ifdef RESOURCES_HWTIMER +#include +#include +#endif + +#ifdef RESOURCES_ADC +#include +#include +#endif + +#ifdef RESOURCES_DAC +#include +#include +#endif + +#endif diff --git a/Ubiquitous/XiZi/resources/include/flash_spi.h b/Ubiquitous/XiZi/resources/include/flash_spi.h new file mode 100644 index 0000000..f41d40d --- /dev/null +++ b/Ubiquitous/XiZi/resources/include/flash_spi.h @@ -0,0 +1,40 @@ +/* +* Copyright (c) 2020 AIIT XUOS Lab +* XiUOS is licensed under Mulan PSL v2. +* You can use this software according to the terms and conditions of the Mulan PSL v2. +* You may obtain a copy of Mulan PSL v2 at: +* http://license.coscl.org.cn/MulanPSL2 +* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, +* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, +* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. +* See the Mulan PSL v2 for more details. +*/ + +/** +* @file flash_spi.h +* @brief define spi-flash dev function using bus driver framework +* @version 1.0 +* @author AIIT XUOS Lab +* @date 2021-04-24 +*/ + +#ifndef FLASH_SPI_H +#define FLASH_SPI_H + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +SpiFlashDeviceType SpiFlashInit(char *bus_name, char *dev_name, char *drv_name, char *flash_name); + +uint32 SpiFlashRelease(SpiFlashDeviceType spi_flash_dev); + +sfud_flash_t SpiFlashFind(char *flash_name); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/Ubiquitous/XiZi/resources/include/sd_spi.h b/Ubiquitous/XiZi/resources/include/sd_spi.h new file mode 100644 index 0000000..387d26a --- /dev/null +++ b/Ubiquitous/XiZi/resources/include/sd_spi.h @@ -0,0 +1,155 @@ +/* +* Copyright (c) 2020 AIIT XUOS Lab +* XiUOS is licensed under Mulan PSL v2. +* You can use this software according to the terms and conditions of the Mulan PSL v2. +* You may obtain a copy of Mulan PSL v2 at: +* http://license.coscl.org.cn/MulanPSL2 +* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, +* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, +* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. +* See the Mulan PSL v2 for more details. +*/ + +/** +* @file sd_spi.h +* @brief define spi-sd dev function using bus driver framework +* @version 1.0 +* @author AIIT XUOS Lab +* @date 2021-04-24 +*/ + +#ifndef SD_SPI_H +#define SD_SPI_H + +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +#define SPI_SD_FREQUENCY 400000 +#define SPI_SD_TIMEOUT_NUM 100 +#define SD_CMD_RESPONE_LENGTH 5 +#define SD_CMD_CSD_LENGTH 16 +#define SD_BLOCK_LENGTH 512 + +#define SD_TIMEOUT(cnt, time) \ +do \ +{ \ + cnt++; \ + if(cnt >= time) \ + { \ + KPrintf("SD_TMEOUT %s %d\n", __FUNCTION__, __LINE__); \ + return ETIMEOUT; \ + } \ +}while(0) + +typedef struct SpiSdDevice *SpiSdDeviceType; + +typedef enum +{ + SD_CMD_0 = 0, + SD_CMD_1, + SD_CMD_8 = 8, + SD_CMD_9, + SD_CMD_12 = 12, + SD_CMD_16 = 16, + SD_CMD_17, + SD_CMD_18, + SD_ACMD_23 = 23, + SD_CMD_24, + SD_CMD_25, + SD_ACMD_41 = 41, + SD_CMD_55 = 55, + SD_CMD_58 = 58, +}SdCmd; + +typedef enum +{ + SD_RESPONE_1 = 1, + SD_RESPONE_1B, + SD_RESPONE_2, + SD_RESPONE_3, + SD_RESPONE_7, +}SdRespone; + +struct SdCmdParam +{ + SdCmd sd_cmd_type; + uint8 sd_cmd_crc; + uint32 sd_cmd_args; + SdRespone sd_respone_type; + uint8 sd_respone_data[SD_CMD_RESPONE_LENGTH]; +}; + +struct SdRespone1 +{ + uint8 sd_respone_r1; +}; + +struct SdRespone2 +{ + uint16 sd_respone_r2; +}; + +typedef enum +{ + SD_TYPE_UNKNOW = 0, + SD_TYPE_MMC, + SD_TYPE_V1, + SD_TYPE_V2, + SD_TYPE_SDHC, + SD_TYPE_SDXC, +}SdType; + +struct BlockDevParam +{ + uint32 sector_num; + uint32 sector_bytes; + uint32 block_size; +}; + +struct CSDRegData +{ + uint8 sd_csd_data[SD_CMD_CSD_LENGTH]; + uint8 sd_csd_structure; + uint32 sd_csd_csize; + uint8 sd_csd_csize_multi; + uint8 sd_csd_readbl_len; + uint8 sd_csd_transpeed; + uint8 sd_csd_sectorsize; + uint32 sd_csd_capacity; +}; + +struct SdDevParam +{ + SdType sd_type; + uint32 sd_spi_maxfreq; + + struct BlockDevParam block_param; + struct CSDRegData csd_data; +}; + +struct SdDevDone +{ + uint32 (*open) (void *dev); + uint32 (*close) (void *dev); + uint32 (*write) (void *dev, struct BusBlockWriteParam *write_param); + uint32 (*read) (void *dev, struct BusBlockReadParam *read_param); +}; + +struct SpiSdDevice +{ + struct SpiHardwareDevice *spi_dev; + struct SdDevParam sd_param; + struct SpiHardwareDevice sd_dev; +}; + +SpiSdDeviceType SpiSdInit(struct Bus *bus, const char *dev_name, const char *drv_name, const char *sd_name); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/Ubiquitous/XiZi/resources/include/stm32_usb_common.h b/Ubiquitous/XiZi/resources/include/stm32_usb_common.h new file mode 100644 index 0000000..eb9cf71 --- /dev/null +++ b/Ubiquitous/XiZi/resources/include/stm32_usb_common.h @@ -0,0 +1,574 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2012-10-01 Yi Qiu first version + * 2013-04-26 aozima add DEVICEQUALIFIER support. + * 2017-11-15 ZYH fix ep0 transform error + */ + +/** +* @file stm32_usb_common.h +* @brief define usb function and struct +* @version 1.0 +* @author AIIT XUOS Lab +* @date 2021-04-25 +*/ + +/************************************************* +File name: stm32_usb_common.h +Description: define usb function and common struct +Others: take RT-Thread v4.0.2/components/drivers/include/drivers/usb_common.h for references + https://github.com/RT-Thread/rt-thread/tree/v4.0.2 +History: +1. Date: 2021-04-25 +Author: AIIT XUOS Lab +Modification: +1. define usb common configure, function and struct +2. support bus driver framework +*************************************************/ + +#ifndef USB_COMMON_H +#define USB_COMMON_H + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +#define SYS_DEBUG_USB 0x00 +#define USB_DYNAMIC 0x00 + +#define USB_CLASS_DEVICE 0x00 +#define USB_CLASS_AUDIO 0x01 +#define USB_CLASS_CDC 0x02 +#define USB_CLASS_HID 0x03 +#define USB_CLASS_PHYSICAL 0x05 +#define USB_CLASS_IMAGE 0x06 +#define USB_CLASS_PRINTER 0x07 +#define USB_CLASS_MASS_STORAGE 0x08 +#define USB_CLASS_HUB 0x09 +#define USB_CLASS_CDC_DATA 0x0a +#define USB_CLASS_SMART_CARD 0x0b +#define USB_CLASS_SECURITY 0x0d +#define USB_CLASS_VIDEO 0x0e +#define USB_CLASS_HEALTHCARE 0x0f +#define USB_CLASS_DIAG_DEVICE 0xdc +#define USB_CLASS_WIRELESS 0xe0 +#define USB_CLASS_MISC 0xef +#define USB_CLASS_APP_SPECIFIC 0xfe +#define USB_CLASS_VEND_SPECIFIC 0xff + +#define USB_DESC_TYPE_DEVICE 0x01 +#define USB_DESC_TYPE_CONFIGURATION 0x02 +#define USB_DESC_TYPE_STRING 0x03 +#define USB_DESC_TYPE_INTERFACE 0x04 +#define USB_DESC_TYPE_ENDPOINT 0x05 +#define USB_DESC_TYPE_DEVICEQUALIFIER 0x06 +#define USB_DESC_TYPE_OTHERSPEED 0x07 +#define USB_DESC_TYPE_IAD 0x0b +#define USB_DESC_TYPE_HID 0x21 +#define USB_DESC_TYPE_REPORT 0x22 +#define USB_DESC_TYPE_PHYSICAL 0x23 +#define USB_DESC_TYPE_HUB 0x29 + +#define USB_DESC_LENGTH_DEVICE 0x12 +#define USB_DESC_LENGTH_CONFIG 0x9 +#define USB_DESC_LENGTH_IAD 0x8 +#define USB_DESC_LENGTH_STRING 0x4 +#define USB_DESC_LENGTH_INTERFACE 0x9 +#define USB_DESC_LENGTH_ENDPOINT 0x7 + +#define USB_REQ_TYPE_STANDARD 0x00 +#define USB_REQ_TYPE_CLASS 0x20 +#define USB_REQ_TYPE_VENDOR 0x40 +#define USB_REQ_TYPE_MASK 0x60 + +#define USB_REQ_TYPE_DIR_OUT 0x00 +#define USB_REQ_TYPE_DIR_IN 0x80 + +#define USB_REQ_TYPE_DEVICE 0x00 +#define USB_REQ_TYPE_INTERFACE 0x01 +#define USB_REQ_TYPE_ENDPOINT 0x02 +#define USB_REQ_TYPE_OTHER 0x03 +#define USB_REQ_TYPE_RECIPIENT_MASK 0x1f + +#define USB_FEATURE_ENDPOINT_HALT 0x00 +#define USB_FEATURE_DEV_REMOTE_WAKEUP 0x01 +#define USB_FEATURE_TEST_MODE 0x02 + +#define USB_REQ_GET_STATUS 0x00 +#define USB_REQ_CLEAR_FEATURE 0x01 +#define USB_REQ_SET_FEATURE 0x03 +#define USB_REQ_SET_ADDRESS 0x05 +#define USB_REQ_GET_DESCRIPTOR 0x06 +#define USB_REQ_SET_DESCRIPTOR 0x07 +#define USB_REQ_GET_CONFIGURATION 0x08 +#define USB_REQ_SET_CONFIGURATION 0x09 +#define USB_REQ_GET_INTERFACE 0x0A +#define USB_REQ_SET_INTERFACE 0x0B +#define USB_REQ_SYNCH_FRAME 0x0C +#define USB_REQ_SET_ENCRYPTION 0x0D +#define USB_REQ_GET_ENCRYPTION 0x0E +#define USB_REQ_RPIPE_ABORT 0x0E +#define USB_REQ_SET_HANDSHAKE 0x0F +#define USB_REQ_RPIPE_RESET 0x0F +#define USB_REQ_GET_HANDSHAKE 0x10 +#define USB_REQ_SET_CONNECTION 0x11 +#define USB_REQ_SET_SECURITY_DATA 0x12 +#define USB_REQ_GET_SECURITY_DATA 0x13 +#define USB_REQ_SET_WUSB_DATA 0x14 +#define USB_REQ_LOOPBACK_DATA_WRITE 0x15 +#define USB_REQ_LOOPBACK_DATA_READ 0x16 +#define USB_REQ_SET_INTERFACE_DS 0x17 + +#define USB_STRING_LANGID_INDEX 0x00 +#define USB_STRING_MANU_INDEX 0x01 +#define USB_STRING_PRODUCT_INDEX 0x02 +#define USB_STRING_SERIAL_INDEX 0x03 +#define USB_STRING_CONFIG_INDEX 0x04 +#define USB_STRING_INTERFACE_INDEX 0x05 +#define USB_STRING_OS_INDEX 0x06 +#define USB_STRING_MAX USB_STRING_OS_INDEX + +#define USB_STRING_OS "MSFT100A" + +#define USB_PID_OUT 0x01 +#define USB_PID_ACK 0x02 +#define USB_PID_DATA0 0x03 +#define USB_PID_SOF 0x05 +#define USB_PID_IN 0x09 +#define USB_PID_NACK 0x0A +#define USB_PID_DATA1 0x0B +#define USB_PID_PRE 0x0C +#define USB_PID_SETUP 0x0D +#define USB_PID_STALL 0x0E + +#define USB_EP_DESC_OUT 0x00 +#define USB_EP_DESC_IN 0x80 +#define USB_EP_DESC_NUM_MASK 0x0f + +#define USB_EP_ATTR_CONTROL 0x00 +#define USB_EP_ATTR_ISOC 0x01 +#define USB_EP_ATTR_BULK 0x02 +#define USB_EP_ATTR_INT 0x03 +#define USB_EP_ATTR_TYPE_MASK 0x03 + +#define USB_EPNO_MASK 0x7f +#define USB_DIR_OUT 0x00 +#define USB_DIR_IN 0x80 +#define USB_DIR_INOUT 0x40 +#define USB_DIR_MASK 0x80 + +#define ID_UNASSIGNED 0 +#define ID_ASSIGNED 1 + +#define RH_GET_PORT_STATUS 0 +#define RH_SET_PORT_STATUS 1 +#define RH_CLEAR_PORT_FEATURE 2 +#define RH_SET_PORT_FEATURE 3 + +#define USB_BUS_POWERED 0 +#define USB_SELF_POWERED 1 +#define USB_REMOTE_WAKEUP 1 +#define USB_EP_HALT 0 + + +#define PORT_FEAT_CONNECTION 0 +#define PORT_FEAT_ENABLE 1 +#define PORT_FEAT_SUSPEND 2 +#define PORT_FEAT_OVER_CURRENT 3 +#define PORT_FEAT_RESET 4 +#define PORT_FEAT_POWER 8 +#define PORT_FEAT_LOWSPEED 9 +#define PORT_FEAT_HIGHSPEED 10 +#define PORT_FEAT_C_CONNECTION 16 +#define PORT_FEAT_C_ENABLE 17 +#define PORT_FEAT_C_SUSPEND 18 +#define PORT_FEAT_C_OVER_CURRENT 19 +#define PORT_FEAT_C_RESET 20 + + +#define PORT_CCS 0x00000001UL +#define PORT_PES 0x00000002UL +#define PORT_PSS 0x00000004UL +#define PORT_POCI 0x00000008UL +#define PORT_PRS 0x00000010UL +#define PORT_PPS 0x00000100UL +#define PORT_LSDA 0x00000200UL +#define PORT_CCSC 0x00010000UL +#define PORT_PESC 0x00020000UL +#define PORT_PSSC 0x00040000UL +#define PORT_POCIC 0x00080000UL +#define PORT_PRSC 0x00100000UL + + +#define HUB_STATUS_LOCAL_POWER 0x0001 +#define HUB_STATUS_OVERCURRENT 0x0002 + +#define HUB_CHANGE_LOCAL_POWER 0x0001 +#define HUB_CHANGE_OVERCURRENT 0x0002 + +#define USB_EP_ATTR(attr) (attr & USB_EP_ATTR_TYPE_MASK) +#define USB_EP_DESC_NUM(addr) (addr & USB_EP_DESC_NUM_MASK) +#define USB_EP_DIR(addr) ((addr & USB_DIR_MASK)>>7) + +#define HID_REPORT_ID_KEYBOARD1 1 +#define HID_REPORT_ID_KEYBOARD2 2 +#define HID_REPORT_ID_KEYBOARD3 3 +#define HID_REPORT_ID_KEYBOARD4 7 +#define HID_REPORT_ID_MEDIA 4 +#define HID_REPORT_ID_GENERAL 5 +#define HID_REPORT_ID_MOUSE 6 + + +#ifndef USB_TIMEOUT_BASIC +#define USB_TIMEOUT_BASIC (TICK_PER_SECOND) +#endif +#ifndef USB_TIMEOUT_LONG +#define USB_TIMEOUT_LONG (TICK_PER_SECOND * 5) +#endif +#ifndef USB_DEBOUNCE_TIME +#define USB_DEBOUNCE_TIME (TICK_PER_SECOND / 5) +#endif + +#define uswap_32(x) \ + ((((x) & 0xff000000) >> 24) | \ + (((x) & 0x00ff0000) >> 8) | \ + (((x) & 0x0000ff00) << 8) | \ + (((x) & 0x000000ff) << 24)) + +#define Uswap8(x) \ + (((uint16)(*((uint8 *)(x)))) + \ + (((uint16)(*(((uint8 *)(x)) + 1))) << 8)) + +typedef void (*FuncCallback) (void *context); + +typedef enum +{ + USB_STATE_NOTATTACHED = 0, + USB_STATE_ATTACHED, + USB_STATE_POWERED, + USB_STATE_RECONNECTING, + USB_STATE_UNAUTHENTICATED, + USB_STATE_DEFAULT, + USB_STATE_ADDRESS, + USB_STATE_CONFIGURED, + USB_STATE_SUSPENDED +}UdeviceStatePointer; + +typedef enum +{ + STAGE_IDLE, + STAGE_SETUP, + STAGE_STATUS_IN, + STAGE_STATUS_OUT, + STAGE_DIN, + STAGE_DOUT +} Uep0StagePointer; + +#pragma pack(1) + +struct UsbDescriptor +{ + uint8 bLength; + uint8 type; +}; +typedef struct UsbDescriptor* UdescPointer; + +struct UdeviceDescriptor +{ + uint8 bLength; + uint8 type; + uint16 bcdUSB; + uint8 bDeviceClass; + uint8 bDeviceSubClass; + uint8 bDeviceProtocol; + uint8 bMaxPacketSize0; + uint16 idVendor; + uint16 idProduct; + uint16 bcdDevice; + uint8 iManufacturer; + uint8 iProduct; + uint8 iSerialNumber; + uint8 bNumConfigurations; +}; +typedef struct UdeviceDescriptor* UdevDescPointer; + +struct UconfigDescriptor +{ + uint8 bLength; + uint8 type; + uint16 wTotalLength; + uint8 bNumInterfaces; + uint8 bConfigurationValue; + uint8 iConfiguration; + uint8 bmAttributes; + uint8 MaxPower; + uint8 data[256]; +}; +typedef struct UconfigDescriptor* UcfgDescPointer; + +struct UinterfaceDescriptor +{ + uint8 bLength; + uint8 type; + uint8 bInterfaceNumber; + uint8 bAlternateSetting; + uint8 bNumEndpoints; + uint8 bInterfaceClass; + uint8 bInterfaceSubClass; + uint8 bInterfaceProtocol; + uint8 iInterface; +}; +typedef struct UinterfaceDescriptor* UintfDescPointer; + + +struct UiadDescriptor +{ + uint8 bLength; + uint8 bDescriptorType; + uint8 bFirstInterface; + uint8 bInterfaceCount; + uint8 bFunctionClass; + uint8 bFunctionSubClass; + uint8 bFunctionProtocol; + uint8 iFunction; +}; +typedef struct UiadDescriptor* UiadDescPointer; + +struct UendpointDescriptor +{ + uint8 bLength; + uint8 type; + uint8 bEndpointAddress; + uint8 bmAttributes; + uint16 wMaxPacketSize; + uint8 bInterval; +}; +typedef struct UendpointDescriptor* UepDescPointer; + +struct UstringDescriptor +{ + uint8 bLength; + uint8 type; + uint8 String[64]; +}; +typedef struct UstringDescriptor* UstrDescPointer; + +struct UhubDescriptor +{ + uint8 length; + uint8 type; + uint8 NumPorts; + uint16 characteristics; + uint8 PwronToGood; + uint8 current; + uint8 removable[8]; + uint8 PwrCtl[8]; +}; +typedef struct UhubDescriptor* UhubDescPointer; + + +struct UsbQualifierDescriptor +{ + uint8 bLength; + uint8 bDescriptorType; + + uint16 bcdUSB; + uint8 bDeviceClass; + uint8 bDeviceSubClass; + uint8 bDeviceProtocol; + uint8 bMaxPacketSize0; + uint8 bNumConfigurations; + uint8 bRESERVED; +} __attribute__ ((packed)); + +struct UsbOsHeaderCompIdDescriptor +{ + uint32 dwLength; + uint16 bcdVersion; + uint16 wIndex; + uint8 bCount; + uint8 reserved[7]; +}; +typedef struct UsbOsHeaderCompIdDescriptor * UsbOsHeaderDescPointer; + +struct UsbOsFunctionCompIdDescriptor +{ + DoubleLinklistType list; + uint8 bFirstInterfaceNumber; + uint8 reserved1; + uint8 compatibleID[8]; + uint8 subCompatibleID[8]; + uint8 reserved2[6]; +}; +typedef struct UsbOsFunctionCompIdDescriptor * UsbOsFuncCompIdDescPointer; + +struct UsbOsCompIdDescriptor +{ + struct UsbOsHeaderCompIdDescriptor HeadDesc; + DoubleLinklistType FuncDesc; +}; +typedef struct UsbOsCompIdDescriptor * UsbOsCompIdDescPointer; + +struct UsbOsPropertyHeader +{ + uint32 dwLength; + uint16 bcdVersion; + uint16 wIndex; + uint16 wCount; +}; +typedef struct UsbOsPropertyHeader * UsbOsPropertyHeaderPointer; +struct UsbOsProerty +{ + uint32 dwSize; + uint32 dwPropertyDataType; + uint16 wPropertyNameLength; + const char * bPropertyName; + uint32 dwPropertyDataLength; + const char * bPropertyData; +}; +typedef struct UsbOsProerty * UsbOsProertyPointer; + + +#define USB_OS_PROERTY_TYPE_REG_SZ 0x01UL +#define USB_OS_PROERTY_TYPE_REG_EXPAND_SZ 0x02UL +#define USB_OS_PROERTY_TYPE_REG_BINARY 0x03UL +#define USB_OS_PROERTY_TYPE_REG_DWORD_LITTLE_ENDIAN 0x04UL +#define USB_OS_PROERTY_TYPE_REG_DWORD_BIG_ENDIAN 0x05UL +#define USB_OS_PROERTY_TYPE_REG_LINK 0x06UL +#define USB_OS_PROERTY_TYPE_REG_MULTI_SZ 0x07UL + +#define USB_OS_PROERTY_DESC(PropertyDataType,PropertyName,PropertyData) \ +{\ + .dwSize = sizeof(struct UsbOsProerty)-sizeof(const char *)*2\ + +sizeof(PropertyName)*2+sizeof(PropertyData)*2,\ + .dwPropertyDataType = PropertyDataType,\ + .wPropertyNameLength = sizeof(PropertyName)*2,\ + .bPropertyName = PropertyName,\ + .dwPropertyDataLength = sizeof(PropertyData)*2,\ + .bPropertyData = PropertyData\ +} + + +#ifndef HID_SUB_DESCRIPTOR_MAX +#define HID_SUB_DESCRIPTOR_MAX 1 +#endif + +struct UhidDescriptor +{ + uint8 bLength; + uint8 type; + uint16 bcdHID; + uint8 bCountryCode; + uint8 bNumDescriptors; + struct HidDescriptorList + { + uint8 type; + uint16 wLength; + }Descriptor[HID_SUB_DESCRIPTOR_MAX]; +}; +typedef struct UhidDescriptor* UhidDescPointer; + +struct HidReport +{ + uint8 ReportId; + uint8 report[63]; + uint8 size; +}; +typedef struct HidReport* HidReportPointer; +extern void HIDReportReceived(HidReportPointer report); + +struct urequest +{ + uint8 RequestType; + uint8 bRequest; + uint16 wValue; + uint16 wIndex; + uint16 wLength; +}; +typedef struct urequest* UreqPointer; + +#ifndef MIN +#define MIN(a, b) ((a) < (b) ? (a) : (b)) +#endif +#ifndef MAX +#define MAX(a, b) ((a) > (b) ? (a) : (b)) +#endif + + +#define USBREQ_GET_MAX_LUN 0xfe +#define USBREQ_MASS_STORAGE_RESET 0xff + +#define SIZEOF_CSW 0x0d +#define SIZEOF_CBW 0x1f +#define SIZEOF_INQUIRY_CMD 0x24 +#define SIZEOF_MODE_SENSE_6 0x4 +#define SIZEOF_READ_CAPACITIES 0xc +#define SIZEOF_READ_CAPACITY 0x8 +#define SIZEOF_REQUEST_SENSE 0x12 + +#define CBWFLAGS_DIR_M 0x80 +#define CBWFLAGS_DIR_IN 0x80 +#define CBWFLAGS_DIR_OUT 0x00 + +#define SCSI_TEST_UNIT_READY 0x00 +#define SCSI_REQUEST_SENSE 0x03 +#define SCSI_INQUIRY_CMD 0x12 +#define SCSI_ALLOW_REMOVAL 0x1e +#define SCSI_MODE_SENSE_6 0x1a +#define SCSI_START_STOP 0x1b +#define SCSI_READ_CAPACITIES 0x23 +#define SCSI_READ_CAPACITY 0x25 +#define SCSI_READ_10 0x28 +#define SCSI_WRITE_10 0x2a +#define SCSI_VERIFY_10 0x2f + +#define CBW_SIGNATURE 0x43425355 +#define CSW_SIGNATURE 0x53425355 +#define CBW_TAG_VALUE 0x12345678 + +struct UstorageCbw +{ + uint32 signature; + uint32 tag; + uint32 XferLen; + uint8 dflags; + uint8 lun; + uint8 CbLen; + uint8 cb[16]; +}; +typedef struct UstorageCbw* UstorageCbwPointer; + +struct UstorageCsw +{ + uint32 signature; + uint32 tag; + int32 DataReside; + uint8 status; +}; +typedef struct UstorageCsw* UstorageCswPointer; + +#pragma pack() + + +#ifndef USBD_THREAD_STACK_SZ +#define USBD_THREAD_STACK_SZ 512 +#endif + + +#ifndef USBD_THREAD_PRIO +#define USBD_THREAD_PRIO 8 +#endif + + +#ifdef __cplusplus +} +#endif + +#endif \ No newline at end of file diff --git a/Ubiquitous/XiZi/resources/include/stm32_usb_host.h b/Ubiquitous/XiZi/resources/include/stm32_usb_host.h new file mode 100644 index 0000000..d30aa78 --- /dev/null +++ b/Ubiquitous/XiZi/resources/include/stm32_usb_host.h @@ -0,0 +1,289 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2011-3-12 Yi Qiu first version + */ + +/** +* @file stm32_usb_host.h +* @brief define usb host function and struct +* @version 1.0 +* @author AIIT XUOS Lab +* @date 2021-04-25 +*/ + +/************************************************* +File name: stm32_usb_host.h +Description: define usb host function and struct +Others: take RT-Thread v4.0.2/components/drivers/include/drivers/usb_host.h for references + https://github.com/RT-Thread/rt-thread/tree/v4.0.2 +History: +1. Date: 2021-04-25 +Author: AIIT XUOS Lab +Modification: +1. define usb host configure, function and struct +2. support bus driver framework +*************************************************/ + +#ifndef USB_HOST_H +#define USB_HOST_H + +#include + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +#ifdef ARCH_CPU_64BIT +typedef uint64 x_usb_format; +#else +typedef uint32 x_usb_format; +#endif + +#define USB_MAX_DEVICE 0x20 +#define USB_MAX_INTERFACE 0x08 +#define USB_HUB_PORT_NUM 0x04 +#define SIZEOF_USB_REQUEST 0x08 + +#define DEV_STATUS_IDLE 0x00 +#define DEV_STATUS_BUSY 0x01 +#define DEV_STATUS_ERROR 0x02 + +#define UPIPE_STATUS_OK 0x00 +#define UPIPE_STATUS_STALL 0x01 +#define UPIPE_STATUS_ERROR 0x02 + +#define USBH_PID_SETUP 0x00 +#define USBH_PID_DATA 0x01 + +struct uhcd; +struct uhintf; +struct uhub; +struct upipe; + +struct UclassDriver +{ + DoubleLinklistType list; + int ClassCode; + int subclass_code; + + x_err_t (*enable)(void* arg); + x_err_t (*disable)(void* arg); + + void* UserData; +}; +typedef struct UclassDriver* UcdPointer; + +struct uprotocal +{ + DoubleLinklistType list; + int ProId; + + x_err_t (*init)(void* arg); + x_err_t (*callback)(void* arg); +}; +typedef struct uprotocal* UprotocalPointer; + +struct uinstance +{ + struct UdeviceDescriptor DevDesc; + UcfgDescPointer CfgDesc; + struct uhcd *hcd; + + struct upipe * PipeEp0Out; + struct upipe * PipeEp0In; + DoubleLinklistType pipe; + + uint8 status; + uint8 type; + uint8 index; + uint8 address; + uint8 speed; + uint8 MaxPacketSize; + uint8 port; + + struct uhub* parent_hub; + struct uhintf* intf[USB_MAX_INTERFACE]; +}; +typedef struct uinstance* UinstPointer; + +struct uhintf +{ + struct uinstance* device; + UintfDescPointer IntfDesc; + + UcdPointer drv; + void *UserData; +}; + +struct upipe +{ + DoubleLinklistType list; + uint8 pipe_index; + uint32 status; + struct UendpointDescriptor ep; + UinstPointer inst; + FuncCallback callback; + void* UserData; +}; +typedef struct upipe* upipe_t; + +struct uhub +{ + struct UhubDescriptor HubDesc; + uint8 NumPorts; + uint32 PortStatus[USB_HUB_PORT_NUM]; + struct uinstance* child[USB_HUB_PORT_NUM]; + + x_bool IsRoothub; + + uint8 buffer[8]; + struct uinstance* self; + struct uhcd *hcd; +}; +typedef struct uhub* UhubPointer; + +struct uhcd_ops +{ + x_err_t (*reset_port) (uint8 port); + int (*pipe_xfer) (upipe_t pipe, uint8 token, void* buffer, int nbytes, int timeout); + x_err_t (*open_pipe) (upipe_t pipe); + x_err_t (*close_pipe) (upipe_t pipe); +}; +typedef struct uhcd_ops* uhcd_ops_t; +struct uhcd +{ + uhcd_ops_t ops; + uint8 NumPorts; + UhubPointer roothub; +}; +typedef struct uhcd* UhcdPointer; + +enum uhost_msg_type +{ + USB_MSG_CONNECT_CHANGE, + USB_MSG_CALLBACK, +}; +typedef enum uhost_msg_type uhost_msg_type; + +struct UhostMsg +{ + uhost_msg_type type; + union + { + struct uhub* hub; + struct + { + FuncCallback function; + void *context; + }cb; + }content; +}; +typedef struct UhostMsg* uhost_msg_t; + +/* usb host system interface */ +x_err_t UsbHostInit(struct uhcd *hcd); +void UsbhHubInit(struct uhcd *hcd); + +/* usb host core interface */ +struct uinstance* UsbhAllocInstance(UhcdPointer uhcd); +x_err_t UsbhAttatchInstance(struct uinstance* device); +x_err_t UsbhDetachInstance(struct uinstance* device); +x_err_t UsbhGetDescriptor(struct uinstance* device, uint8 type, void* buffer, int nbytes); +x_err_t UsbhSetConfigure(struct uinstance* device, int config); +x_err_t UsbhSetAddress(struct uinstance* device); +x_err_t UsbhSetInterface(struct uinstance* device, int intf); +x_err_t UsbhClearFeature(struct uinstance* device, int endpoint, int feature); +x_err_t UsbhGetInterfaceDescriptor(UcfgDescPointer CfgDesc, int num, UintfDescPointer* IntfDesc); +x_err_t UsbhGetEndpointDescriptor(UintfDescPointer IntfDesc, int num, UepDescPointer* EpDesc); + +/* usb class driver interface */ +x_err_t UsbhClassDriverInit(void); +x_err_t UsbhClassDriverRegister(UcdPointer drv); +x_err_t UsbhClassDriverUnregister(UcdPointer drv); +x_err_t UsbhClassDriverEnable(UcdPointer drv, void* args); +x_err_t UsbhClassDriverDisable(UcdPointer drv, void* args); +UcdPointer UsbhClassDriverFind(int ClassCode, int subclass_code); + +/* usb class driver implement */ +UcdPointer UsbhClassDriverHub(void); +UcdPointer UsbhClassDriverStorage(void); + +/* usb hub interface */ +x_err_t UsbhHubGetDescriptor(struct uinstance* device, uint8 *buffer, + x_size_t size); +x_err_t UsbhHubGetStatus(struct uinstance* device, uint32* buffer); +x_err_t UsbhHubGetPortStatus(UhubPointer uhub, uint16 port, + uint32* buffer); +x_err_t UsbhHubClearPortFeature(UhubPointer uhub, uint16 port, + uint16 feature); +x_err_t UsbhHubSetPortFeature(UhubPointer uhub, uint16 port, + uint16 feature); +x_err_t UsbhHubResetPort(UhubPointer uhub, uint16 port); +x_err_t UsbhEventSignal(struct UhostMsg* msg); + +void UsbhRootHubConnectHandler(struct uhcd *hcd, uint8 port, x_bool isHS); +void UsbhRootHubDisconnectHandler(struct uhcd *hcd, uint8 port); + +/* usb host controller driver interface */ +static __inline x_err_t usb_instance_add_pipe(UinstPointer inst, upipe_t pipe) +{ + NULL_PARAM_CHECK(inst); + NULL_PARAM_CHECK(pipe); + DoubleLinkListInsertNodeBefore(&inst->pipe, &pipe->list); + return EOK; +} +static __inline upipe_t UsbInstanceFindPipe(UinstPointer inst,uint8 ep_address) +{ + DoubleLinklistType * l; + for(l = inst->pipe.node_next;l != &inst->pipe;l = l->node_next) + { + if(SYS_DOUBLE_LINKLIST_ENTRY(l,struct upipe,list)->ep.bEndpointAddress == ep_address) + { + return SYS_DOUBLE_LINKLIST_ENTRY(l,struct upipe,list); + } + } + return NONE; +} +static __inline x_err_t UsbHcdAllocPipe(UhcdPointer hcd, upipe_t* pipe, UinstPointer inst, UepDescPointer ep) +{ + *pipe = (upipe_t)x_malloc(sizeof(struct upipe)); + if(*pipe == NONE) + { + return ERROR; + } + memset(*pipe,0,sizeof(struct upipe)); + (*pipe)->inst = inst; + memcpy(&(*pipe)->ep,ep,sizeof(struct UendpointDescriptor)); + return hcd->ops->open_pipe(*pipe); +} +static __inline void UsbPipeAddCallback(upipe_t pipe, FuncCallback callback) +{ + pipe->callback = callback; +} + +static __inline x_err_t UsbHcdFreePipe(UhcdPointer hcd, upipe_t pipe) +{ + NULL_PARAM_CHECK(pipe); + hcd->ops->close_pipe(pipe); + x_free(pipe); + return EOK; +} + +int UsbHcdPipeXfer(UhcdPointer hcd, upipe_t pipe, void* buffer, int nbytes, int timeout); +static __inline int UsbHcdSetupXfer(UhcdPointer hcd, upipe_t pipe, UreqPointer setup, int timeout) +{ + return hcd->ops->pipe_xfer(pipe, USBH_PID_SETUP, (void *)setup, 8, timeout); +} + +#ifdef __cplusplus +} +#endif + +#endif \ No newline at end of file diff --git a/Ubiquitous/XiZi/resources/lcd/Makefile b/Ubiquitous/XiZi/resources/lcd/Makefile new file mode 100644 index 0000000..c8cf880 --- /dev/null +++ b/Ubiquitous/XiZi/resources/lcd/Makefile @@ -0,0 +1,5 @@ +SRC_FILES += dev_lcd.c bus_lcd.c drv_lcd.c + + + +include $(KERNEL_ROOT)/compiler.mk \ No newline at end of file diff --git a/Ubiquitous/XiZi/resources/lcd/bus_lcd.c b/Ubiquitous/XiZi/resources/lcd/bus_lcd.c new file mode 100644 index 0000000..d3eace7 --- /dev/null +++ b/Ubiquitous/XiZi/resources/lcd/bus_lcd.c @@ -0,0 +1,118 @@ +/* +* Copyright (c) 2020 AIIT XUOS Lab +* XiUOS is licensed under Mulan PSL v2. +* You can use this software according to the terms and conditions of the Mulan PSL v2. +* You may obtain a copy of Mulan PSL v2 at: +* http://license.coscl.org.cn/MulanPSL2 +* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, +* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, +* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. +* See the Mulan PSL v2 for more details. +*/ + +/** +* @file bus_lcd.c +* @brief register lcd bus function using bus driver framework +* @version 1.0 +* @author AIIT XUOS Lab +* @date 2021-04-24 +*/ + +#include +#include + +int LcdBusInit(struct LcdBus *lcd_bus, const char *bus_name) +{ + NULL_PARAM_CHECK(lcd_bus); + NULL_PARAM_CHECK(bus_name); + + x_err_t ret = EOK; + + if (BUS_INSTALL != lcd_bus->bus.bus_state) { + strncpy(lcd_bus->bus.bus_name, bus_name, NAME_NUM_MAX); + + lcd_bus->bus.bus_type = TYPE_LCD_BUS; + lcd_bus->bus.bus_state = BUS_INSTALL; + lcd_bus->bus.private_data = lcd_bus->private_data; + + ret = BusRegister(&lcd_bus->bus); + if (EOK != ret) { + KPrintf("LCDBusInit BusRegister error %u\n", ret); + return ret; + } + } else { + KPrintf("LCDBusInit BusRegister bus has been register state%u\n", lcd_bus->bus.bus_state); + } + + return ret; +} + +int LcdDriverInit(struct LcdDriver *lcd_driver, const char *driver_name) +{ + NULL_PARAM_CHECK(lcd_driver); + NULL_PARAM_CHECK(driver_name); + + x_err_t ret = EOK; + + if (DRV_INSTALL != lcd_driver->driver.driver_state) { + lcd_driver->driver.driver_type = TYPE_LCD_DRV; + lcd_driver->driver.driver_state = DRV_INSTALL; + + strncpy(lcd_driver->driver.drv_name, driver_name, NAME_NUM_MAX); + + lcd_driver->driver.configure = lcd_driver->configure; + + ret = LcdDriverRegister(&lcd_driver->driver); + if (EOK != ret) { + KPrintf("LcdDriverInit DriverRegister error %u\n", ret); + return ret; + } + } else { + KPrintf("LcdDriverInit DriverRegister driver has been register state%u\n", lcd_driver->driver.driver_state); + } + + return ret; +} + +int LcdReleaseBus(struct LcdBus *lcd_bus) +{ + NULL_PARAM_CHECK(lcd_bus); + + return BusRelease(&lcd_bus->bus); +} + +int LcdDriverAttachToBus(const char *drv_name, const char *bus_name) +{ + NULL_PARAM_CHECK(drv_name); + NULL_PARAM_CHECK(bus_name); + + x_err_t ret = EOK; + + struct Bus *bus; + struct Driver *driver; + + bus = BusFind(bus_name); + if (NONE == bus) { + KPrintf("LcdDriverAttachToBus find lcd bus error!name %s\n", bus_name); + return ERROR; + } + + if (TYPE_LCD_BUS == bus->bus_type) { + driver = LcdDriverFind(drv_name, TYPE_LCD_DRV); + if (NONE == driver) { + KPrintf("LcdDriverAttachToBus find lcd driver error!name %s\n", drv_name); + return ERROR; + } + + if (TYPE_LCD_DRV == driver->driver_type) { + ret = DriverRegisterToBus(bus, driver); + if (EOK != ret) { + KPrintf("LcdDriverAttachToBus DriverRegisterToBus error %u\n", ret); + return ERROR; + } + } + } + + return ret; +} + diff --git a/Ubiquitous/XiZi/resources/lcd/dev_lcd.c b/Ubiquitous/XiZi/resources/lcd/dev_lcd.c new file mode 100644 index 0000000..6d70267 --- /dev/null +++ b/Ubiquitous/XiZi/resources/lcd/dev_lcd.c @@ -0,0 +1,115 @@ +/* +* Copyright (c) 2020 AIIT XUOS Lab +* XiUOS is licensed under Mulan PSL v2. +* You can use this software according to the terms and conditions of the Mulan PSL v2. +* You may obtain a copy of Mulan PSL v2 at: +* http://license.coscl.org.cn/MulanPSL2 +* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, +* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, +* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. +* See the Mulan PSL v2 for more details. +*/ + +/** +* @file dev_lcd.c +* @brief register lcd dev function using bus driver framework +* @version 1.0 +* @author AIIT XUOS Lab +* @date 2021-04-24 +*/ + +#include +#include + +static DoubleLinklistType lcddev_linklist; + +/*Create the lcd device linklist*/ +static void LcdDeviceLinkInit() +{ + InitDoubleLinkList(&lcddev_linklist); +} + +HardwareDevType LcdDeviceFind(const char *dev_name, enum DevType dev_type) +{ + NULL_PARAM_CHECK(dev_name); + + struct HardwareDev *device = NONE; + + DoubleLinklistType *node = NONE; + DoubleLinklistType *head = &lcddev_linklist; + + for (node = head->node_next; node != head; node = node->node_next) { + device = SYS_DOUBLE_LINKLIST_ENTRY(node, struct HardwareDev, dev_link); + if ((!strcmp(device->dev_name, dev_name)) && (dev_type == device->dev_type)) { + return device; + } + } + + KPrintf("LcdDeviceFind cannot find the %s device.return NULL\n", dev_name); + return NONE; +} + +int LcdDeviceRegister(struct LcdHardwareDevice *lcd_device, void *lcd_param, const char *device_name) +{ + NULL_PARAM_CHECK(lcd_device); + NULL_PARAM_CHECK(device_name); + + x_err_t ret = EOK; + static x_bool dev_link_flag = RET_FALSE; + + if (!dev_link_flag) { + LcdDeviceLinkInit(); + dev_link_flag = RET_TRUE; + } + + if (DEV_INSTALL != lcd_device->haldev.dev_state) { + strncpy(lcd_device->haldev.dev_name, device_name, NAME_NUM_MAX); + lcd_device->haldev.dev_type = TYPE_LCD_DEV; + lcd_device->haldev.dev_state = DEV_INSTALL; + + lcd_device->haldev.dev_done = (struct HalDevDone *)lcd_device->dev_done; + + lcd_device->haldev.private_data = lcd_param; + + DoubleLinkListInsertNodeAfter(&lcddev_linklist, &(lcd_device->haldev.dev_link)); + } else { + KPrintf("LcdDeviceRegister device has been register state%u\n", lcd_device->haldev.dev_state); + } + + return ret; +} + +int LcdDeviceAttachToBus(const char *dev_name, const char *bus_name) +{ + NULL_PARAM_CHECK(dev_name); + NULL_PARAM_CHECK(bus_name); + + x_err_t ret = EOK; + + struct Bus *bus; + struct HardwareDev *device; + + bus = BusFind(bus_name); + if (NONE == bus) { + KPrintf("LcdDeviceAttachToBus find lcd bus error!name %s\n", bus_name); + return ERROR; + } + + if (TYPE_LCD_BUS == bus->bus_type) { + device = LcdDeviceFind(dev_name, TYPE_LCD_DEV); + if (NONE == device) { + KPrintf("LcdDeviceAttachToBus find lcd device error!name %s\n", dev_name); + return ERROR; + } + + if (TYPE_LCD_DEV == device->dev_type) { + ret = DeviceRegisterToBus(bus, device); + if (EOK != ret) { + KPrintf("LcdDeviceAttachToBus DeviceRegisterToBus error %u\n", ret); + return ERROR; + } + } + } + + return EOK; +} diff --git a/Ubiquitous/XiZi/resources/lcd/drv_lcd.c b/Ubiquitous/XiZi/resources/lcd/drv_lcd.c new file mode 100644 index 0000000..fca9ba0 --- /dev/null +++ b/Ubiquitous/XiZi/resources/lcd/drv_lcd.c @@ -0,0 +1,67 @@ +/* +* Copyright (c) 2020 AIIT XUOS Lab +* XiUOS is licensed under Mulan PSL v2. +* You can use this software according to the terms and conditions of the Mulan PSL v2. +* You may obtain a copy of Mulan PSL v2 at: +* http://license.coscl.org.cn/MulanPSL2 +* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, +* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, +* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. +* See the Mulan PSL v2 for more details. +*/ + +/** +* @file drv_lcd.c +* @brief register lcd drv function using bus driver framework +* @version 1.0 +* @author AIIT XUOS Lab +* @date 2021-04-24 +*/ + +#include +#include + +static DoubleLinklistType lcddrv_linklist; + +/*Create the driver linklist*/ +static void LcdDrvLinkInit() +{ + InitDoubleLinkList(&lcddrv_linklist); +} + +DriverType LcdDriverFind(const char *drv_name, enum DriverType_e drv_type) +{ + NULL_PARAM_CHECK(drv_name); + + struct Driver *driver = NONE; + + DoubleLinklistType *node = NONE; + DoubleLinklistType *head = &lcddrv_linklist; + + for (node = head->node_next; node != head; node = node->node_next) { + driver = SYS_DOUBLE_LINKLIST_ENTRY(node, struct Driver, driver_link); + if ((!strcmp(driver->drv_name, drv_name)) && (drv_type == driver->driver_type)) { + return driver; + } + } + + KPrintf("LcdDriverFind cannot find the %s driver.return NULL\n", drv_name); + return NONE; +} + +int LcdDriverRegister(struct Driver *driver) +{ + NULL_PARAM_CHECK(driver); + + x_err_t ret = EOK; + static x_bool driver_link_flag = RET_FALSE; + + if (!driver_link_flag) { + LcdDrvLinkInit(); + driver_link_flag = RET_TRUE; + } + + DoubleLinkListInsertNodeAfter(&lcddrv_linklist, &(driver->driver_link)); + + return ret; +} diff --git a/Ubiquitous/XiZi/resources/pin/Makefile b/Ubiquitous/XiZi/resources/pin/Makefile new file mode 100644 index 0000000..9ec8b6e --- /dev/null +++ b/Ubiquitous/XiZi/resources/pin/Makefile @@ -0,0 +1,5 @@ +SRC_FILES +=bus_pin.c dev_pin.c drv_pin.c + + + +include $(KERNEL_ROOT)/compiler.mk diff --git a/Ubiquitous/XiZi/resources/pin/bus_pin.c b/Ubiquitous/XiZi/resources/pin/bus_pin.c new file mode 100644 index 0000000..1ddb9c5 --- /dev/null +++ b/Ubiquitous/XiZi/resources/pin/bus_pin.c @@ -0,0 +1,143 @@ +/* +* Copyright (c) 2020 AIIT XUOS Lab +* XiUOS is licensed under Mulan PSL v2. +* You can use this software according to the terms and conditions of the Mulan PSL v2. +* You may obtain a copy of Mulan PSL v2 at: +* http://license.coscl.org.cn/MulanPSL2 +* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, +* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, +* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. +* See the Mulan PSL v2 for more details. +*/ + +/** +* @file bus_pin.c +* @brief register pin bus function using bus driver framework +* @version 1.0 +* @author AIIT XUOS Lab +* @date 2021-04-24 +*/ + +#include +#include + +int PinBusInit(struct PinBus *pin_bus, const char *bus_name) +{ + NULL_PARAM_CHECK(pin_bus); + NULL_PARAM_CHECK(bus_name); + + x_err_t ret = EOK; + + if (BUS_INSTALL != pin_bus->bus.bus_state) { + strncpy(pin_bus->bus.bus_name, bus_name, NAME_NUM_MAX); + + pin_bus->bus.bus_type = TYPE_PIN_BUS; + pin_bus->bus.bus_state = BUS_INSTALL; + pin_bus->bus.private_data = pin_bus->private_data; + + ret = BusRegister(&pin_bus->bus); + if (EOK != ret) { + KPrintf("PinBusInit BusRegister error %u\n", ret); + return ret; + } + } else { + KPrintf("PinBusInit BusRegister bus has been register state%u\n", pin_bus->bus.bus_state); + } + + return ret; +} + +int PinDriverInit(struct PinDriver *pin_driver, const char *driver_name, void *data) +{ + NULL_PARAM_CHECK(pin_driver); + NULL_PARAM_CHECK(driver_name); + + x_err_t ret = EOK; + + if (DRV_INSTALL != pin_driver->driver.driver_state) { + pin_driver->driver.driver_type = TYPE_PIN_DRV; + pin_driver->driver.driver_state = DRV_INSTALL; + + strncpy(pin_driver->driver.drv_name, driver_name, NAME_NUM_MAX); + + pin_driver->driver.configure = pin_driver->configure; + pin_driver->driver.private_data = data; + + ret = PinDriverRegister(&pin_driver->driver); + if (EOK != ret) { + KPrintf("PinDriverInit DriverRegister error %u\n", ret); + return ret; + } + } else { + KPrintf("PinDriverInit DriverRegister driver has been register state%u\n", pin_driver->driver.driver_state); + } + + return ret; +} + +int PinReleaseBus(struct PinBus *pin_bus) +{ + NULL_PARAM_CHECK(pin_bus); + + return BusRelease(&pin_bus->bus); +} + +int PinDriverAttachToBus(const char *drv_name, const char *bus_name) +{ + NULL_PARAM_CHECK(drv_name); + NULL_PARAM_CHECK(bus_name); + + x_err_t ret = EOK; + + struct Bus *bus; + struct Driver *driver; + + bus = BusFind(bus_name); + if (NONE == bus) { + KPrintf("PinDriverAttachToBus find spi bus error!name %s\n", bus_name); + return ERROR; + } + + if (TYPE_PIN_BUS == bus->bus_type) { + driver = PinDriverFind(drv_name, TYPE_PIN_DRV); + if (NONE == driver) { + KPrintf("PinDriverAttachToBus find spi driver error!name %s\n", drv_name); + return ERROR; + } + + if (TYPE_PIN_DRV == driver->driver_type) { + ret = DriverRegisterToBus(bus, driver); + if (EOK != ret) { + KPrintf("PinDriverAttachToBus DriverRegisterToBus error %u\n", ret); + return ERROR; + } + } + } + + return ret; +} + +BusType PinBusInitGet(void) +{ + struct BusConfigureInfo configure_info; + BusType pin; + int ret = 0; + + pin = BusFind(PIN_BUS_NAME); + if (!pin) { + KPrintf("find %s failed!\n", PIN_BUS_NAME); + return NONE; + } + + pin->owner_driver = BusFindDriver(pin, PIN_DRIVER_NAME); + pin->owner_haldev = BusFindDevice(pin, PIN_DEVICE_NAME); + + configure_info.configure_cmd = OPE_INT; + ret = BusDrvConfigure(pin->owner_driver, &configure_info); + if (ret != EOK) { + KPrintf("initialize %s failed!\n", PIN_BUS_NAME); + return NONE; + } + + return pin; +} diff --git a/Ubiquitous/XiZi/resources/pin/dev_pin.c b/Ubiquitous/XiZi/resources/pin/dev_pin.c new file mode 100644 index 0000000..b76de1f --- /dev/null +++ b/Ubiquitous/XiZi/resources/pin/dev_pin.c @@ -0,0 +1,116 @@ +/* +* Copyright (c) 2020 AIIT XUOS Lab +* XiUOS is licensed under Mulan PSL v2. +* You can use this software according to the terms and conditions of the Mulan PSL v2. +* You may obtain a copy of Mulan PSL v2 at: +* http://license.coscl.org.cn/MulanPSL2 +* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, +* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, +* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. +* See the Mulan PSL v2 for more details. +*/ + +/** +* @file dev_pin.c +* @brief register pin dev function using bus driver framework +* @version 1.0 +* @author AIIT XUOS Lab +* @date 2021-04-24 +*/ + +#include +#include + +static DoubleLinklistType pindev_linklist; + +/*Create the Pin device linklist*/ +static void PinDeviceLinkInit() +{ + InitDoubleLinkList(&pindev_linklist); +} + +HardwareDevType PinDeviceFind(const char *dev_name, enum DevType DevType) +{ + NULL_PARAM_CHECK(dev_name); + + struct HardwareDev *device = NONE; + + DoubleLinklistType *node = NONE; + DoubleLinklistType *head = &pindev_linklist; + + for (node = head->node_next; node != head; node = node->node_next) { + device = SYS_DOUBLE_LINKLIST_ENTRY(node, struct HardwareDev, dev_link); + if ((!strcmp(device->dev_name, dev_name)) && (DevType == device->dev_type)) { + return device; + } + } + + KPrintf("PinDeviceFind cannot find the %s device.return NULL\n", dev_name); + return NONE; +} + +int PinDeviceRegister(struct PinHardwareDevice *pin_device, void *pin_param, const char *device_name) +{ + NULL_PARAM_CHECK(pin_device); + NULL_PARAM_CHECK(device_name); + + x_err_t ret = EOK; + static x_bool dev_link_flag = RET_FALSE; + + if (!dev_link_flag) { + PinDeviceLinkInit(); + dev_link_flag = RET_TRUE; + } + + if (DEV_INSTALL != pin_device->haldev.dev_state) { + strncpy(pin_device->haldev.dev_name, device_name, NAME_NUM_MAX); + pin_device->haldev.dev_type = TYPE_PIN_DEV; + pin_device->haldev.dev_state = DEV_INSTALL; + + pin_device->haldev.dev_done = (struct HalDevDone *)pin_device->dev_done; + + pin_device->haldev.private_data = pin_param; + + DoubleLinkListInsertNodeAfter(&pindev_linklist, &(pin_device->haldev.dev_link)); + } else { + KPrintf("PinDeviceRegister device has been register state%u\n", pin_device->haldev.dev_state); + } + + return ret; +} + +int PinDeviceAttachToBus(const char *dev_name, const char *bus_name) +{ + NULL_PARAM_CHECK(dev_name); + NULL_PARAM_CHECK(bus_name); + + x_err_t ret = EOK; + + struct Bus *bus; + struct HardwareDev *device; + + bus = BusFind(bus_name); + if (NONE == bus) { + KPrintf("PinDeviceAttachToBus find Pin bus error!name %s\n", bus_name); + return ERROR; + } + + if (TYPE_PIN_BUS == bus->bus_type) { + device = PinDeviceFind(dev_name, TYPE_PIN_DEV); + if (NONE == device) { + KPrintf("PinDeviceAttachToBus find Pin device error!name %s\n", dev_name); + return ERROR; + } + + if (TYPE_PIN_DEV == device->dev_type) { + ret = DeviceRegisterToBus(bus, device); + if (EOK != ret) { + KPrintf("PinDeviceAttachToBus DeviceRegisterToBus error %u\n", ret); + return ERROR; + } + } + } + + return EOK; +} + diff --git a/Ubiquitous/XiZi/resources/pin/drv_pin.c b/Ubiquitous/XiZi/resources/pin/drv_pin.c new file mode 100644 index 0000000..67b94b7 --- /dev/null +++ b/Ubiquitous/XiZi/resources/pin/drv_pin.c @@ -0,0 +1,67 @@ +/* +* Copyright (c) 2020 AIIT XUOS Lab +* XiUOS is licensed under Mulan PSL v2. +* You can use this software according to the terms and conditions of the Mulan PSL v2. +* You may obtain a copy of Mulan PSL v2 at: +* http://license.coscl.org.cn/MulanPSL2 +* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, +* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, +* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. +* See the Mulan PSL v2 for more details. +*/ + +/** +* @file drv_pin.c +* @brief register pin drv function using bus driver framework +* @version 1.0 +* @author AIIT XUOS Lab +* @date 2021-04-24 +*/ + +#include +#include + +static DoubleLinklistType pindrv_linklist; + +/*Create the driver linklist*/ +static void PinDrvLinkInit() +{ + InitDoubleLinkList(&pindrv_linklist); +} + +DriverType PinDriverFind(const char *drv_name, enum DriverType_e DrvType) +{ + NULL_PARAM_CHECK(drv_name); + + struct Driver *driver = NONE; + + DoubleLinklistType *node = NONE; + DoubleLinklistType *head = &pindrv_linklist; + + for (node = head->node_next; node != head; node = node->node_next) { + driver = SYS_DOUBLE_LINKLIST_ENTRY(node, struct Driver, driver_link); + if ((!strcmp(driver->drv_name, drv_name)) && (DrvType == driver->driver_type)) { + return driver; + } + } + + KPrintf("PinDriverFind cannot find the %s driver.return NULL\n", drv_name); + return NONE; +} + +int PinDriverRegister(struct Driver *driver) +{ + NULL_PARAM_CHECK(driver); + + x_err_t ret = EOK; + static x_bool driver_link_flag = RET_FALSE; + + if (!driver_link_flag) { + PinDrvLinkInit(); + driver_link_flag = RET_TRUE; + } + + DoubleLinkListInsertNodeAfter(&pindrv_linklist, &(driver->driver_link)); + + return ret; +} diff --git a/Ubiquitous/XiZi/resources/rtc/Makefile b/Ubiquitous/XiZi/resources/rtc/Makefile new file mode 100644 index 0000000..61ce556 --- /dev/null +++ b/Ubiquitous/XiZi/resources/rtc/Makefile @@ -0,0 +1,5 @@ +SRC_FILES += bus_rtc.c dev_rtc.c drv_rtc.c + + + +include $(KERNEL_ROOT)/compiler.mk diff --git a/Ubiquitous/XiZi/resources/rtc/bus_rtc.c b/Ubiquitous/XiZi/resources/rtc/bus_rtc.c new file mode 100644 index 0000000..567f40c --- /dev/null +++ b/Ubiquitous/XiZi/resources/rtc/bus_rtc.c @@ -0,0 +1,117 @@ +/* +* Copyright (c) 2020 AIIT XUOS Lab +* XiUOS is licensed under Mulan PSL v2. +* You can use this software according to the terms and conditions of the Mulan PSL v2. +* You may obtain a copy of Mulan PSL v2 at: +* http://license.coscl.org.cn/MulanPSL2 +* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, +* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, +* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. +* See the Mulan PSL v2 for more details. +*/ + +/** +* @file bus_rtc.c +* @brief register rtc bus function using bus driver framework +* @version 1.0 +* @author AIIT XUOS Lab +* @date 2021-04-24 +*/ + +#include +#include + +int RtcBusInit(struct RtcBus *rtc_bus, const char *bus_name) +{ + NULL_PARAM_CHECK(rtc_bus); + NULL_PARAM_CHECK(bus_name); + + x_err_t ret = EOK; + + if (BUS_INSTALL != rtc_bus->bus.bus_state) { + strncpy(rtc_bus->bus.bus_name, bus_name, NAME_NUM_MAX); + + rtc_bus->bus.bus_type = TYPE_RTC_BUS; + rtc_bus->bus.bus_state = BUS_INSTALL; + rtc_bus->bus.private_data = rtc_bus->private_data; + + ret = BusRegister(&rtc_bus->bus); + if (EOK != ret) { + KPrintf("RtcBusInit BusRegister error %u\n", ret); + return ret; + } + } else { + KPrintf("RtcBusInit BusRegister bus has been register state%u\n", rtc_bus->bus.bus_state); + } + + return ret; +} + +int RtcDriverInit(struct RtcDriver *rtc_driver, const char *driver_name) +{ + NULL_PARAM_CHECK(rtc_driver); + NULL_PARAM_CHECK(driver_name); + + x_err_t ret = EOK; + + if (DRV_INSTALL != rtc_driver->driver.driver_state) { + rtc_driver->driver.driver_type = TYPE_RTC_DRV; + rtc_driver->driver.driver_state = DRV_INSTALL; + + strncpy(rtc_driver->driver.drv_name, driver_name, NAME_NUM_MAX); + + rtc_driver->driver.configure = rtc_driver->configure; + + ret = RtcDriverRegister(&rtc_driver->driver); + if (EOK != ret) { + KPrintf("RtcDriverInit DriverRegister error %u\n", ret); + return ret; + } + } else { + KPrintf("RtcDriverInit DriverRegister driver has been register state%u\n", rtc_driver->driver.driver_state); + } + + return ret; +} + +int RtcReleaseBus(struct RtcBus *rtc_bus) +{ + NULL_PARAM_CHECK(rtc_bus); + + return BusRelease(&rtc_bus->bus); +} + +int RtcDriverAttachToBus(const char *drv_name, const char *bus_name) +{ + NULL_PARAM_CHECK(drv_name); + NULL_PARAM_CHECK(bus_name); + + x_err_t ret = EOK; + + struct Bus *bus; + struct Driver *driver; + + bus = BusFind(bus_name); + if (NONE == bus) { + KPrintf("RtcDriverAttachToBus find rtc bus error!name %s\n", bus_name); + return ERROR; + } + + if (TYPE_RTC_BUS == bus->bus_type) { + driver = RtcDriverFind(drv_name, TYPE_RTC_DRV); + if (NONE == driver) { + KPrintf("RtcDriverAttachToBus find rtc driver error!name %s\n", drv_name); + return ERROR; + } + + if (TYPE_RTC_DRV == driver->driver_type) { + ret = DriverRegisterToBus(bus, driver); + if (EOK != ret) { + KPrintf("RtcDriverAttachToBus DriverRegisterToBus error %u\n", ret); + return ERROR; + } + } + } + + return ret; +} diff --git a/Ubiquitous/XiZi/resources/rtc/dev_rtc.c b/Ubiquitous/XiZi/resources/rtc/dev_rtc.c new file mode 100644 index 0000000..e867b72 --- /dev/null +++ b/Ubiquitous/XiZi/resources/rtc/dev_rtc.c @@ -0,0 +1,115 @@ +/* +* Copyright (c) 2020 AIIT XUOS Lab +* XiUOS is licensed under Mulan PSL v2. +* You can use this software according to the terms and conditions of the Mulan PSL v2. +* You may obtain a copy of Mulan PSL v2 at: +* http://license.coscl.org.cn/MulanPSL2 +* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, +* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, +* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. +* See the Mulan PSL v2 for more details. +*/ + +/** +* @file dev_rtc.c +* @brief register rtc dev function using bus driver framework +* @version 1.0 +* @author AIIT XUOS Lab +* @date 2021-04-24 +*/ + +#include +#include + +static DoubleLinklistType rtcdev_linklist; + +/*Create the rtc device linklist*/ +static void RtcDeviceLinkInit() +{ + InitDoubleLinkList(&rtcdev_linklist); +} + +HardwareDevType RtcDeviceFind(const char *dev_name, enum DevType dev_type) +{ + NULL_PARAM_CHECK(dev_name); + + struct HardwareDev *device = NONE; + + DoubleLinklistType *node = NONE; + DoubleLinklistType *head = &rtcdev_linklist; + + for (node = head->node_next; node != head; node = node->node_next) { + device = SYS_DOUBLE_LINKLIST_ENTRY(node, struct HardwareDev, dev_link); + if ((!strcmp(device->dev_name, dev_name)) && (dev_type == device->dev_type)) { + return device; + } + } + + KPrintf("RtcDeviceFind cannot find the %s device.return NULL\n", dev_name); + return NONE; +} + +int RtcDeviceRegister(struct RtcHardwareDevice *rtc_device, void *rtc_param, const char *device_name) +{ + NULL_PARAM_CHECK(rtc_device); + NULL_PARAM_CHECK(device_name); + + x_err_t ret = EOK; + static x_bool dev_link_flag = RET_FALSE; + + if (!dev_link_flag) { + RtcDeviceLinkInit(); + dev_link_flag = RET_TRUE; + } + + if (DEV_INSTALL != rtc_device->haldev.dev_state) { + strncpy(rtc_device->haldev.dev_name, device_name, NAME_NUM_MAX); + rtc_device->haldev.dev_type = TYPE_RTC_DEV; + rtc_device->haldev.dev_state = DEV_INSTALL; + + rtc_device->haldev.dev_done = (struct HalDevDone *)rtc_device->dev_done; + + rtc_device->haldev.private_data = rtc_param; + + DoubleLinkListInsertNodeAfter(&rtcdev_linklist, &(rtc_device->haldev.dev_link)); + } else { + KPrintf("RtcDeviceRegister device has been register state%u\n", rtc_device->haldev.dev_state); + } + + return ret; +} + +int RtcDeviceAttachToBus(const char *dev_name, const char *bus_name) +{ + NULL_PARAM_CHECK(dev_name); + NULL_PARAM_CHECK(bus_name); + + x_err_t ret = EOK; + + struct Bus *bus; + struct HardwareDev *device; + + bus = BusFind(bus_name); + if (NONE == bus) { + KPrintf("RtcDeviceAttachToBus find rtc bus error!name %s\n", bus_name); + return ERROR; + } + + if (TYPE_RTC_BUS == bus->bus_type) { + device = RtcDeviceFind(dev_name, TYPE_RTC_DEV); + if (NONE == device) { + KPrintf("RtcDeviceAttachToBus find rtc device error!name %s\n", dev_name); + return ERROR; + } + + if (TYPE_RTC_DEV == device->dev_type) { + ret = DeviceRegisterToBus(bus, device); + if (EOK != ret) { + KPrintf("RtcDeviceAttachToBus DeviceRegisterToBus error %u\n", ret); + return ERROR; + } + } + } + + return EOK; +} diff --git a/Ubiquitous/XiZi/resources/rtc/drv_rtc.c b/Ubiquitous/XiZi/resources/rtc/drv_rtc.c new file mode 100644 index 0000000..bc4a188 --- /dev/null +++ b/Ubiquitous/XiZi/resources/rtc/drv_rtc.c @@ -0,0 +1,244 @@ +/* +* Copyright (c) 2020 AIIT XUOS Lab +* XiUOS is licensed under Mulan PSL v2. +* You can use this software according to the terms and conditions of the Mulan PSL v2. +* You may obtain a copy of Mulan PSL v2 at: +* http://license.coscl.org.cn/MulanPSL2 +* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, +* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, +* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. +* See the Mulan PSL v2 for more details. +*/ + +/** +* @file drv_rtc.c +* @brief register rtc drv function using bus driver framework +* @version 1.0 +* @author AIIT XUOS Lab +* @date 2021-04-24 +*/ + +#include +#include + +static DoubleLinklistType rtcdrv_linklist; + +/*Create the driver linklist*/ +static void RtcDrvLinkInit() +{ + InitDoubleLinkList(&rtcdrv_linklist); +} + +DriverType RtcDriverFind(const char *drv_name, enum DriverType_e drv_type) +{ + NULL_PARAM_CHECK(drv_name); + + struct Driver *driver = NONE; + + DoubleLinklistType *node = NONE; + DoubleLinklistType *head = &rtcdrv_linklist; + + for (node = head->node_next; node != head; node = node->node_next) { + driver = SYS_DOUBLE_LINKLIST_ENTRY(node, struct Driver, driver_link); + if ((!strcmp(driver->drv_name, drv_name)) && (drv_type == driver->driver_type)) { + return driver; + } + } + + KPrintf("RtcDriverFind cannot find the %s driver.return NULL\n", drv_name); + return NONE; +} + +int RtcDriverRegister(struct Driver *driver) +{ + NULL_PARAM_CHECK(driver); + + x_err_t ret = EOK; + static x_bool driver_link_flag = RET_FALSE; + + if (!driver_link_flag) { + RtcDrvLinkInit(); + driver_link_flag = RET_TRUE; + } + + DoubleLinkListInsertNodeAfter(&rtcdrv_linklist, &(driver->driver_link)); + + return ret; +} + +int RtcDrvSetFunction(char *driver_name, struct RtcSetParam *rtc_set_param) +{ + NULL_PARAM_CHECK(driver_name); + + x_err_t ret = EOK; + time_t now; + struct tm *tm_now; + struct tm tm_tmp; + x_base lock; + + struct Driver *driver; + struct BusConfigureInfo configure_info; + struct RtcDrvConfigureParam drv_param; + configure_info.private_data = &drv_param; + + driver = RtcDriverFind(driver_name, TYPE_RTC_DRV); + if (NONE == driver) { + KPrintf("RtcDrvSetFunction find rtc driver %s error\n", driver_name); + return ERROR; + } + + if (OPER_RTC_SET_TIME == rtc_set_param->rtc_set_cmd) { + now = time(NONE); + lock = CriticalAreaLock(); + tm_now = localtime(&now); + memcpy(&tm_tmp, tm_now, sizeof(struct tm)); + CriticalAreaUnLock(lock); + + tm_tmp.tm_year = rtc_set_param->date_param.year - 1900; + tm_tmp.tm_mon = rtc_set_param->date_param.month - 1; + tm_tmp.tm_mday = rtc_set_param->date_param.day; + tm_tmp.tm_hour = rtc_set_param->time_param.hour; + tm_tmp.tm_min = rtc_set_param->time_param.minute; + tm_tmp.tm_sec = rtc_set_param->time_param.second; + + now = mktime(&tm_tmp); + + drv_param.rtc_operation_cmd = OPER_RTC_SET_TIME; + drv_param.time = &now; + + ret = driver->configure(driver, &configure_info); + if (EOK != ret) { + KPrintf("RtcDrvSetFunction set time error %d\n", ret); + return ret; + } + } else if (OPER_RTC_GET_TIME == rtc_set_param->rtc_set_cmd) { + drv_param.rtc_operation_cmd = OPER_RTC_GET_TIME; + drv_param.time = rtc_set_param->time; + ret = driver->configure(driver, &configure_info); + if (EOK != ret) { + KPrintf("RtcDrvSetFunction set time error %d\n", ret); + return ret; + } + } + return EOK; +} + +#ifdef USING_SOFT_RTC + +static x_ticks_t SoftRtc_InitTick; +static time_t SoftRtc_InitTime; + +static int SoftRtcInitTime(struct tm *time, struct RtcDateParam *date_param, struct RtcTimeParam *time_param) +{ + NULL_PARAM_CHECK(time); + + time->tm_year = date_param->year - 1900; + time->tm_mon = date_param->month - 1; + time->tm_mday = date_param->day; + time->tm_hour = time_param->hour; + time->tm_min = time_param->minute; + time->tm_sec = time_param->second; + + return EOK; +} + +static uint32 SoftRtcConfigure(void *drv, struct BusConfigureInfo *configure_info) +{ + NULL_PARAM_CHECK(drv); + + struct RtcDriver *rtc_drv = (struct RtcDriver *)drv; + struct RtcDrvConfigureParam *drv_param = (struct RtcDrvConfigureParam *)configure_info->private_data; + + int cmd = drv_param->rtc_operation_cmd; + time_t *time = drv_param->time; + + switch(cmd) + { + case OPER_RTC_GET_TIME: + { + *time = SoftRtc_InitTime + (CurrentTicksGain() - SoftRtc_InitTick) / TICK_PER_SECOND; + break; + } + case OPER_RTC_SET_TIME: + { + SoftRtc_InitTime = *time - (CurrentTicksGain() - SoftRtc_InitTick) / TICK_PER_SECOND; + break; + } + } + + return EOK; +} + +static struct RtcDateParam date_param = +{ + .year = 2021, + .month = 1, + .day = 1, +}; + +static struct RtcTimeParam time_param = +{ + .hour = 0, + .minute = 0, + .second = 0, +}; + +static int SoftRtcBusInit(struct RtcBus *softrtc_bus, struct RtcDriver *softrtc_driver) +{ + x_err_t ret = EOK; + + /*Init the soft rtc bus */ + ret = RtcBusInit(softrtc_bus, SOFT_RTC_BUS_NAME); + if(EOK != ret) + { + KPrintf("SoftRtcBusInit RtcBusInit error %d\n", ret); + return ERROR; + } + + /*Init the soft rtc driver*/ + ret = RtcDriverInit(softrtc_driver, SOFT_RTC_DRV_NAME); + if(EOK != ret) + { + KPrintf("SoftRtcBusInit RtcDriverInit error %d\n", ret); + return ERROR; + } + + /*Attach the soft rtc driver to the soft rtc bus*/ + ret = RtcDriverAttachToBus(SOFT_RTC_DRV_NAME, SOFT_RTC_BUS_NAME); + if(EOK != ret) + { + KPrintf("SoftRtcBusInit RtcDriverAttachToBus error %d\n", ret); + return ERROR; + } + + return ret; +} + +int SoftRtcInit(void) +{ + x_err_t ret = EOK; + struct tm time; + + SoftRtcInitTime(&time, &date_param, &time_param); + + static struct RtcBus softrtc_bus; + memset(&softrtc_bus, 0, sizeof(struct RtcBus)); + + static struct RtcDriver softrtc_driver; + memset(&softrtc_driver, 0, sizeof(struct RtcDriver)); + + softrtc_driver.configure = &(SoftRtcConfigure); + + ret = SoftRtcBusInit(&softrtc_bus, &softrtc_driver); + if (EOK != ret) { + KPrintf("SoftRtcInit error ret %u\n", ret); + return ERROR; + } + + SoftRtc_InitTick = CurrentTicksGain(); + SoftRtc_InitTime = mktime(&time); + + return ret; +} + +#endif diff --git a/Ubiquitous/XiZi/resources/sdio/Makefile b/Ubiquitous/XiZi/resources/sdio/Makefile new file mode 100644 index 0000000..bbdb430 --- /dev/null +++ b/Ubiquitous/XiZi/resources/sdio/Makefile @@ -0,0 +1,5 @@ +SRC_FILES +=bus_sdio.c dev_sdio.c drv_sdio.c + + + +include $(KERNEL_ROOT)/compiler.mk diff --git a/Ubiquitous/XiZi/resources/sdio/bus_sdio.c b/Ubiquitous/XiZi/resources/sdio/bus_sdio.c new file mode 100644 index 0000000..f37d497 --- /dev/null +++ b/Ubiquitous/XiZi/resources/sdio/bus_sdio.c @@ -0,0 +1,117 @@ +/* +* Copyright (c) 2020 AIIT XUOS Lab +* XiUOS is licensed under Mulan PSL v2. +* You can use this software according to the terms and conditions of the Mulan PSL v2. +* You may obtain a copy of Mulan PSL v2 at: +* http://license.coscl.org.cn/MulanPSL2 +* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, +* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, +* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. +* See the Mulan PSL v2 for more details. +*/ + +/** +* @file bus_sdio.c +* @brief register sdio bus function using bus driver framework +* @version 1.0 +* @author AIIT XUOS Lab +* @date 2021-04-24 +*/ + +#include +#include + +int SdioBusInit(struct SdioBus *sdio_bus, const char *bus_name) +{ + NULL_PARAM_CHECK(sdio_bus); + NULL_PARAM_CHECK(bus_name); + + x_err_t ret = EOK; + + if (BUS_INSTALL != sdio_bus->bus.bus_state) { + strncpy(sdio_bus->bus.bus_name, bus_name, NAME_NUM_MAX); + + sdio_bus->bus.bus_type = TYPE_SDIO_BUS; + sdio_bus->bus.bus_state = BUS_INSTALL; + sdio_bus->bus.private_data = sdio_bus->private_data; + + ret = BusRegister(&sdio_bus->bus); + if (EOK != ret) { + KPrintf("SdioBusInit BusRegister error %u\n", ret); + return ret; + } + } else { + KPrintf("SdioBusInit BusRegister bus has been register state%u\n", sdio_bus->bus.bus_state); + } + + return ret; +} + +int SdioDriverInit(struct SdioDriver *sdio_driver, const char *driver_name) +{ + NULL_PARAM_CHECK(sdio_driver); + NULL_PARAM_CHECK(driver_name); + + x_err_t ret = EOK; + + if (DRV_INSTALL != sdio_driver->driver.driver_state) { + sdio_driver->driver.driver_type = TYPE_SDIO_DRV; + sdio_driver->driver.driver_state = DRV_INSTALL; + + strncpy(sdio_driver->driver.drv_name, driver_name, NAME_NUM_MAX); + + sdio_driver->driver.configure = sdio_driver->configure; + + ret = SdioDriverRegister(&sdio_driver->driver); + if (EOK != ret) { + KPrintf("SdioDriverInit DriverRegister error %u\n", ret); + return ret; + } + } else { + KPrintf("SdioDriverInit DriverRegister driver has been register state%u\n", sdio_driver->driver.driver_state); + } + + return ret; +} + +int SdioReleaseBus(struct SdioBus *sdio_bus) +{ + NULL_PARAM_CHECK(sdio_bus); + + return BusRelease(&sdio_bus->bus); +} + +int SdioDriverAttachToBus(const char *drv_name, const char *bus_name) +{ + NULL_PARAM_CHECK(drv_name); + NULL_PARAM_CHECK(bus_name); + + x_err_t ret = EOK; + + struct Bus *bus; + struct Driver *driver; + + bus = BusFind(bus_name); + if (NONE == bus) { + KPrintf("SdioDriverAttachToBus find sdio bus error!name %s\n", bus_name); + return ERROR; + } + + if (TYPE_SDIO_BUS == bus->bus_type) { + driver = SdioDriverFind(drv_name); + if (NONE == driver) { + KPrintf("SdioDriverAttachToBus find sdio driver error!name %s\n", drv_name); + return ERROR; + } + + if (TYPE_SDIO_DRV == driver->driver_type) { + ret = DriverRegisterToBus(bus, driver); + if (EOK != ret) { + KPrintf("SdioDriverAttachToBus DriverRegisterToBus error %u\n", ret); + return ERROR; + } + } + } + + return ret; +} diff --git a/Ubiquitous/XiZi/resources/sdio/dev_sdio.c b/Ubiquitous/XiZi/resources/sdio/dev_sdio.c new file mode 100644 index 0000000..b3e0fc5 --- /dev/null +++ b/Ubiquitous/XiZi/resources/sdio/dev_sdio.c @@ -0,0 +1,114 @@ +/* +* Copyright (c) 2020 AIIT XUOS Lab +* XiUOS is licensed under Mulan PSL v2. +* You can use this software according to the terms and conditions of the Mulan PSL v2. +* You may obtain a copy of Mulan PSL v2 at: +* http://license.coscl.org.cn/MulanPSL2 +* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, +* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, +* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. +* See the Mulan PSL v2 for more details. +*/ + +/** +* @file dev_sdio.c +* @brief register sdio dev function using bus driver framework +* @version 1.0 +* @author AIIT XUOS Lab +* @date 2021-04-24 +*/ + +#include +#include + +static DoubleLinklistType sdiodev_linklist; + +/*Create the sdio device linklist*/ +static void SdioDeviceLinkInit() +{ + InitDoubleLinkList(&sdiodev_linklist); +} + +HardwareDevType SdioDeviceFind(const char *dev_name) +{ + NULL_PARAM_CHECK(dev_name); + + struct HardwareDev *device = NONE; + + DoubleLinklistType *node = NONE; + DoubleLinklistType *head = &sdiodev_linklist; + + for (node = head->node_next; node != head; node = node->node_next) { + device = SYS_DOUBLE_LINKLIST_ENTRY(node, struct HardwareDev, dev_link); + if (!strcmp(device->dev_name, dev_name)) { + return device; + } + } + + KPrintf("SdioDeviceFind cannot find the %s device.return NULL\n", dev_name); + return NONE; +} + +int SdioDeviceRegister(struct SdioHardwareDevice *sdio_device, const char *device_name) +{ + NULL_PARAM_CHECK(sdio_device); + NULL_PARAM_CHECK(device_name); + + x_err_t ret = EOK; + static x_bool dev_link_flag = RET_FALSE; + + if (!dev_link_flag) { + SdioDeviceLinkInit(); + dev_link_flag = RET_TRUE; + } + + if (DEV_INSTALL != sdio_device->haldev.dev_state) { + strncpy(sdio_device->haldev.dev_name, device_name, NAME_NUM_MAX); + sdio_device->haldev.dev_type = TYPE_SDIO_DEV; + sdio_device->haldev.dev_state = DEV_INSTALL; + + sdio_device->haldev.dev_done = (struct HalDevDone *)sdio_device->dev_done; + sdio_device->haldev.private_data = sdio_device->private_data; + + DoubleLinkListInsertNodeAfter(&sdiodev_linklist, &(sdio_device->haldev.dev_link)); + } else { + KPrintf("SdioDeviceRegister device has been register state%u\n", sdio_device->haldev.dev_state); + } + + return ret; +} + +int SdioDeviceAttachToBus(const char *dev_name, const char *bus_name) +{ + NULL_PARAM_CHECK(dev_name); + NULL_PARAM_CHECK(bus_name); + + x_err_t ret = EOK; + + struct Bus *bus; + struct HardwareDev *device; + + bus = BusFind(bus_name); + if (NONE == bus) { + KPrintf("SdioDeviceAttachToBus find sdio bus error!name %s\n", bus_name); + return ERROR; + } + + if (TYPE_SDIO_BUS == bus->bus_type) { + device = SdioDeviceFind(dev_name); + if (NONE == device) { + KPrintf("SdioDeviceAttachToBus find sdio device error!name %s\n", dev_name); + return ERROR; + } + + if (TYPE_SDIO_DEV == device->dev_type) { + ret = DeviceRegisterToBus(bus, device); + if (EOK != ret) { + KPrintf("SdioDeviceAttachToBus DeviceRegisterToBus error %u\n", ret); + return ERROR; + } + } + } + + return EOK; +} diff --git a/Ubiquitous/XiZi/resources/sdio/drv_sdio.c b/Ubiquitous/XiZi/resources/sdio/drv_sdio.c new file mode 100644 index 0000000..483ed21 --- /dev/null +++ b/Ubiquitous/XiZi/resources/sdio/drv_sdio.c @@ -0,0 +1,67 @@ +/* +* Copyright (c) 2020 AIIT XUOS Lab +* XiUOS is licensed under Mulan PSL v2. +* You can use this software according to the terms and conditions of the Mulan PSL v2. +* You may obtain a copy of Mulan PSL v2 at: +* http://license.coscl.org.cn/MulanPSL2 +* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, +* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, +* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. +* See the Mulan PSL v2 for more details. +*/ + +/** +* @file drv_sdio.c +* @brief register sdio drv function using bus driver framework +* @version 1.0 +* @author AIIT XUOS Lab +* @date 2021-04-24 +*/ + +#include +#include + +static DoubleLinklistType sdiodrv_linklist; + +/*Create the driver linklist*/ +static void SdioDrvLinkInit() +{ + InitDoubleLinkList(&sdiodrv_linklist); +} + +DriverType SdioDriverFind(const char *drv_name) +{ + NULL_PARAM_CHECK(drv_name); + + struct Driver *driver = NONE; + + DoubleLinklistType *node = NONE; + DoubleLinklistType *head = &sdiodrv_linklist; + + for (node = head->node_next; node != head; node = node->node_next) { + driver = SYS_DOUBLE_LINKLIST_ENTRY(node, struct Driver, driver_link); + if (!strcmp(driver->drv_name, drv_name)) { + return driver; + } + } + + KPrintf("SdioDriverFind cannot find the %s driver.return NULL\n", drv_name); + return NONE; +} + +int SdioDriverRegister(struct Driver *driver) +{ + NULL_PARAM_CHECK(driver); + + x_err_t ret = EOK; + static x_bool driver_link_flag = RET_FALSE; + + if (!driver_link_flag) { + SdioDrvLinkInit(); + driver_link_flag = RET_TRUE; + } + + DoubleLinkListInsertNodeAfter(&sdiodrv_linklist, &(driver->driver_link)); + + return ret; +} diff --git a/Ubiquitous/XiZi/resources/serial/Makefile b/Ubiquitous/XiZi/resources/serial/Makefile new file mode 100644 index 0000000..faa7a69 --- /dev/null +++ b/Ubiquitous/XiZi/resources/serial/Makefile @@ -0,0 +1,3 @@ +SRC_FILES += bus_serial.c drv_serial.c dev_serial.c + +include $(KERNEL_ROOT)/compiler.mk diff --git a/Ubiquitous/XiZi/resources/serial/bus_serial.c b/Ubiquitous/XiZi/resources/serial/bus_serial.c new file mode 100644 index 0000000..52e2bab --- /dev/null +++ b/Ubiquitous/XiZi/resources/serial/bus_serial.c @@ -0,0 +1,117 @@ +/* +* Copyright (c) 2020 AIIT XUOS Lab +* XiUOS is licensed under Mulan PSL v2. +* You can use this software according to the terms and conditions of the Mulan PSL v2. +* You may obtain a copy of Mulan PSL v2 at: +* http://license.coscl.org.cn/MulanPSL2 +* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, +* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, +* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. +* See the Mulan PSL v2 for more details. +*/ + +/** +* @file bus_serial.c +* @brief register serial bus function using bus driver framework +* @version 1.0 +* @author AIIT XUOS Lab +* @date 2021-04-24 +*/ + +#include +#include + +int SerialBusInit(struct SerialBus *serial_bus, const char *bus_name) +{ + NULL_PARAM_CHECK(serial_bus); + NULL_PARAM_CHECK(bus_name); + + x_err_t ret = EOK; + + if (BUS_INSTALL != serial_bus->bus.bus_state) { + strncpy(serial_bus->bus.bus_name, bus_name, NAME_NUM_MAX); + + serial_bus->bus.bus_type = TYPE_SERIAL_BUS; + serial_bus->bus.bus_state = BUS_INSTALL; + serial_bus->bus.private_data = serial_bus->private_data; + + ret = BusRegister(&serial_bus->bus); + if (EOK != ret) { + KPrintf("serial BusInit BusRegister error %u\n", ret); + return ret; + } + } else { + KPrintf("SerialBusInit BusRegister bus has been register state%u\n", serial_bus->bus.bus_state); + } + + return ret; +} + +int SerialDriverInit(struct SerialDriver *serial_driver, const char *driver_name) +{ + NULL_PARAM_CHECK(serial_driver); + NULL_PARAM_CHECK(driver_name); + + x_err_t ret = EOK; + + if (DRV_INSTALL != serial_driver->driver.driver_state) { + serial_driver->driver.driver_type = TYPE_SERIAL_DRV; + serial_driver->driver.driver_state = DRV_INSTALL; + + strncpy(serial_driver->driver.drv_name, driver_name, NAME_NUM_MAX); + + serial_driver->driver.configure = serial_driver->configure; + + ret = SerialDriverRegister(&serial_driver->driver); + if (EOK != ret) { + KPrintf("SerialDriverInit DriverRegister error %u\n", ret); + return ret; + } + } else { + KPrintf("SerialDriverInit DriverRegister driver has been register state%u\n", serial_driver->driver.driver_state); + } + + return ret; +} + +int SerialReleaseBus(struct SerialBus *serial_bus) +{ + NULL_PARAM_CHECK(serial_bus); + + return BusRelease(&serial_bus->bus); +} + +int SerialDriverAttachToBus(const char *drv_name, const char *bus_name) +{ + NULL_PARAM_CHECK(drv_name); + NULL_PARAM_CHECK(bus_name); + + x_err_t ret = EOK; + + struct Bus *bus; + struct Driver *driver; + + bus = BusFind(bus_name); + if (NONE == bus) { + KPrintf("SerialDriverAttachToBus find serial bus error!name %s\n", bus_name); + return ERROR; + } + + if (TYPE_SERIAL_BUS == bus->bus_type) { + driver = SerialDriverFind(drv_name, TYPE_SERIAL_DRV); + if (NONE == driver) { + KPrintf("SerialDriverAttachToBus find serial driver error!name %s\n", drv_name); + return ERROR; + } + + if (TYPE_SERIAL_DRV == driver->driver_type) { + ret = DriverRegisterToBus(bus, driver); + if (EOK != ret) { + KPrintf("SerialDriverAttachToBus DriverRegisterToBus error %u\n", ret); + return ERROR; + } + } + } + + return ret; +} diff --git a/Ubiquitous/XiZi/resources/serial/dev_serial.c b/Ubiquitous/XiZi/resources/serial/dev_serial.c new file mode 100644 index 0000000..25c578c --- /dev/null +++ b/Ubiquitous/XiZi/resources/serial/dev_serial.c @@ -0,0 +1,875 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2006-03-13 bernard first version + * 2012-05-15 lgnq modified according bernard's implementation. + * 2012-05-28 bernard code cleanup + * 2012-11-23 bernard fix compiler warning. + * 2013-02-20 bernard use RT_SERIAL_RB_BUFSZ to define + * the size of ring buffer. + * 2014-07-10 bernard rewrite serial framework + * 2014-12-31 bernard use open_flag for poll_tx stream mode. + * 2015-05-19 Quintin fix DMA tx mod tx_dma->activated flag !=RT_FALSE BUG + * in open function. + * 2015-11-10 bernard fix the poll rx issue when there is no data. + * 2016-05-10 armink add fifo mode to DMA rx when serial->config.bufsz != 0. + * 2017-01-19 aubr.cool prevent change serial rx bufsz when serial is opened. + * 2017-11-07 JasonJia fix data bits error issue when using tcsetattr. + * 2017-11-15 JasonJia fix poll rx issue when data is full. + * add TCFLSH and FIONREAD support. + * 2018-12-08 Ernest Chen add DMA choice + * 2020-09-14 WillianChan add a line feed to the carriage return character + * when using interrupt tx + */ + +/** +* @file dev_serial.c +* @brief register serial dev function using bus driver framework +* @version 1.0 +* @author AIIT XUOS Lab +* @date 2021-04-24 +*/ + +/************************************************* +File name: dev_serial.c +Description: support serial dev INT and DMA configure、transfer data +Others: take RT-Thread v4.0.2/components/driver/serial/serial.c for references + https://github.com/RT-Thread/rt-thread/tree/v4.0.2 +History: +1. Date: 2021-04-24 +Author: AIIT XUOS Lab +Modification: +1. support serial dev register, configure, write and read +2. add bus driver framework support, include INT and DMA mode +*************************************************/ + +#include +#include + +static DoubleLinklistType serialdev_linklist; + +static int SerialWorkModeCheck(struct SerialDevParam *serial_dev_param) +{ + if (SIGN_OPER_INT_TX & serial_dev_param->serial_set_mode) { + if (SIGN_OPER_INT_TX & serial_dev_param->serial_work_mode) { + return EOK; + } else { + KPrintf("SerialWorkModeCheck set mode 0x%x work mode error 0x%x\n", + serial_dev_param->serial_set_mode, serial_dev_param->serial_work_mode); + return ERROR; + } + } else if (SIGN_OPER_INT_RX & serial_dev_param->serial_set_mode) { + if (SIGN_OPER_INT_RX & serial_dev_param->serial_work_mode) { + return EOK; + } else { + KPrintf("SerialWorkModeCheck set mode 0x%x work mode error 0x%x\n", + serial_dev_param->serial_set_mode, serial_dev_param->serial_work_mode); + return ERROR; + } + } else if (SIGN_OPER_DMA_TX & serial_dev_param->serial_set_mode) { + if (SIGN_OPER_DMA_TX & serial_dev_param->serial_work_mode) { + return EOK; + } else { + KPrintf("SerialWorkModeCheck set mode 0x%x work mode error 0x%x\n", + serial_dev_param->serial_set_mode, serial_dev_param->serial_work_mode); + return ERROR; + } + } else if (SIGN_OPER_DMA_RX & serial_dev_param->serial_set_mode) { + if (SIGN_OPER_DMA_RX & serial_dev_param->serial_work_mode) { + return EOK; + } else { + KPrintf("SerialWorkModeCheck set mode 0x%x work mode error 0x%x\n", + serial_dev_param->serial_set_mode, serial_dev_param->serial_work_mode); + return ERROR; + } + } else { + serial_dev_param->serial_set_mode = serial_dev_param->serial_work_mode; + return EOK; + } +} + +static inline int SerialDevIntWrite(struct SerialHardwareDevice *serial_dev, struct BusBlockWriteParam *write_param) +{ + NULL_PARAM_CHECK(serial_dev); + NULL_PARAM_CHECK(write_param); + + struct SerialHwDevDone *hwdev_done = serial_dev->hwdev_done; + const uint8 *write_data = (const uint8 *)write_param->buffer; + x_size_t write_length = write_param->size; + x_size_t len_result = 0; + + while (write_length) + { + if (EOK != hwdev_done->put_char(serial_dev, *(char *)write_data)) { + KSemaphoreObtain(serial_dev->serial_fifo.serial_tx->serial_txfifo_sem, WAITING_FOREVER); + continue; + } + + KPrintf("SerialDevIntWrite data %d write_length %u\n", *(char *)write_data, write_length); + len_result++; + write_data++; + write_length--; + } + + return len_result; +} + +static inline int SerialDevIntRead(struct SerialHardwareDevice *serial_dev, struct BusBlockReadParam *read_param) +{ + NULL_PARAM_CHECK(serial_dev); + NULL_PARAM_CHECK(read_param); + + struct SerialHwDevDone *hwdev_done = serial_dev->hwdev_done; + struct SerialCfgParam *serial_cfg = (struct SerialCfgParam *)serial_dev->private_data; + uint8 *read_data = (uint8 *)read_param->buffer; + x_size_t read_length = read_param->size; + + while (read_length) + { + uint8 get_char; + x_base lock; + + lock = CriticalAreaLock(); + + if (serial_dev->serial_fifo.serial_rx->serial_recv_num == serial_dev->serial_fifo.serial_rx->serial_send_num) { + if (RET_FALSE == serial_dev->serial_fifo.serial_rx->serial_rx_full) { + CriticalAreaUnLock(lock); + break; + } + } + + get_char = serial_dev->serial_fifo.serial_rx->serial_rx_buffer[serial_dev->serial_fifo.serial_rx->serial_recv_num]; + serial_dev->serial_fifo.serial_rx->serial_recv_num += 1; + if (serial_dev->serial_fifo.serial_rx->serial_recv_num >= serial_cfg->data_cfg.serial_buffer_size) { + serial_dev->serial_fifo.serial_rx->serial_recv_num = 0; + } + + if (RET_TRUE == serial_dev->serial_fifo.serial_rx->serial_rx_full) { + serial_dev->serial_fifo.serial_rx->serial_rx_full = RET_FALSE; + } + + CriticalAreaUnLock(lock); + + *read_data = get_char; + read_data++; + read_length--; + read_param->read_length++; + } + + return EOK; +} + +#ifdef SERIAL_USING_DMA +static inline int SerialDevDMAWrite(struct SerialHardwareDevice *serial_dev, struct BusBlockWriteParam *write_param) +{ + NULL_PARAM_CHECK(serial_dev); + NULL_PARAM_CHECK(write_param); + + x_err_t ret = EOK; + x_base lock; + + struct SerialHwDevDone *hwdev_done = serial_dev->hwdev_done; + const uint8 *write_data = (const uint8 *)write_param->buffer; + x_size_t write_length = write_param->size; + + ret = ((DataQueueDoneType*)serial_dev->serial_fifo.serial_tx->serial_dma_queue.done)->PushDataqueue((DataQueueType *)serial_dev->serial_fifo.serial_tx->serial_dma_queue.property, write_param->buffer, write_param->size, WAITING_FOREVER); + if (EOK != ret) { + KUpdateExstatus(ret); + return ERROR; + } + + lock = CriticalAreaLock(); + if (RET_FALSE == serial_dev->serial_fifo.serial_tx->serial_dma_enable) { + serial_dev->serial_fifo.serial_tx->serial_dma_enable = RET_TRUE; + CriticalAreaUnLock(lock); + + hwdev_done->dmatransfer(serial_dev, (uint8 *)write_data, write_length, SERIAL_DMA_TX); + } else { + CriticalAreaUnLock(lock); + } + + return write_length; +} + +static x_size_t SerialGetRxFifoLength(struct SerialHardwareDevice *serial_dev) +{ + NULL_PARAM_CHECK(serial_dev); + + x_size_t length; + struct SerialCfgParam *serial_cfg = (struct SerialCfgParam *)serial_dev->private_data; + + if (serial_dev->serial_fifo.serial_rx->serial_recv_num == serial_dev->serial_fifo.serial_rx->serial_send_num) { + if (serial_dev->serial_fifo.serial_rx->serial_rx_full) { + length = serial_cfg->data_cfg.serial_buffer_size; + } else { + length = 0; + } + } else { + if (serial_dev->serial_fifo.serial_rx->serial_recv_num > serial_dev->serial_fifo.serial_rx->serial_send_num) { + length = serial_cfg->data_cfg.serial_buffer_size - serial_dev->serial_fifo.serial_rx->serial_recv_num + serial_dev->serial_fifo.serial_rx->serial_send_num; + } else { + length = serial_dev->serial_fifo.serial_rx->serial_send_num - serial_dev->serial_fifo.serial_rx->serial_recv_num; + } + } +} + +static void SerialDmaRxSetRecvLength(struct SerialHardwareDevice *serial_dev, x_size_t length) +{ + CHECK(length <= SerialGetRxFifoLength(serial_dev)); + + struct SerialCfgParam *serial_cfg = (struct SerialCfgParam *)serial_dev->private_data; + + if ((serial_dev->serial_fifo.serial_rx->serial_rx_full) && (length)) { + serial_dev->serial_fifo.serial_rx->serial_rx_full = RET_FALSE; + } + + serial_dev->serial_fifo.serial_rx->serial_recv_num += length; + + if (serial_dev->serial_fifo.serial_rx->serial_recv_num >= serial_cfg->data_cfg.serial_buffer_size) { + serial_dev->serial_fifo.serial_rx->serial_recv_num %= serial_cfg->data_cfg.serial_buffer_size; + } +} + +static void SerialDmaRxSetSendLength(struct SerialHardwareDevice *serial_dev, x_size_t length) +{ + struct SerialCfgParam *serial_cfg = (struct SerialCfgParam *)serial_dev->private_data; + + if (serial_dev->serial_fifo.serial_rx->serial_recv_num > serial_dev->serial_fifo.serial_rx->serial_send_num) { + serial_dev->serial_fifo.serial_rx->serial_send_num += length; + if (serial_dev->serial_fifo.serial_rx->serial_recv_num <= serial_dev->serial_fifo.serial_rx->serial_send_num) { + if (serial_dev->serial_fifo.serial_rx->serial_send_num >= serial_cfg->data_cfg.serial_buffer_size) { + serial_dev->serial_fifo.serial_rx->serial_send_num %= serial_cfg->data_cfg.serial_buffer_size; + } + + serial_dev->serial_fifo.serial_rx->serial_rx_full = RET_TRUE; + } + } else { + serial_dev->serial_fifo.serial_rx->serial_send_num += length; + if (serial_dev->serial_fifo.serial_rx->serial_send_num >= serial_cfg->data_cfg.serial_buffer_size) { + serial_dev->serial_fifo.serial_rx->serial_send_num %= serial_cfg->data_cfg.serial_buffer_size; + + if (serial_dev->serial_fifo.serial_rx->serial_send_num >= serial_dev->serial_fifo.serial_rx->serial_recv_num) { + serial_dev->serial_fifo.serial_rx->serial_rx_full = RET_TRUE; + } + } + } + + if (RET_TRUE == serial_dev->serial_fifo.serial_rx->serial_rx_full) { + serial_dev->serial_fifo.serial_rx->serial_recv_num = serial_dev->serial_fifo.serial_rx->serial_send_num; + } +} + +static inline int SerialDevDMARead(struct SerialHardwareDevice *serial_dev, struct BusBlockReadParam *read_param) +{ + NULL_PARAM_CHECK(serial_dev); + NULL_PARAM_CHECK(read_param); + + x_err_t ret = EOK; + x_base lock; + + struct SerialHwDevDone *hwdev_done = serial_dev->hwdev_done; + struct SerialCfgParam *serial_cfg = (struct SerialCfgParam *)serial_dev->private_data; + uint8 *read_data = (uint8 *)read_param->buffer; + x_size_t read_length = read_param->size; + x_size_t read_dma_length; + x_size_t read_dma_size = SerialGetRxFifoLength(serial_dev); + + if (serial_cfg->data_cfg.serial_buffer_size) { + if(read_length < (int)read_dma_size) + read_dma_length = read_length; + else + read_dma_length = read_dma_size; + + if (serial_dev->serial_fifo.serial_rx->serial_recv_num + read_dma_length < serial_cfg->data_cfg.serial_buffer_size) { + memcpy(read_data, + serial_dev->serial_fifo.serial_rx->serial_rx_buffer + serial_dev->serial_fifo.serial_rx->serial_recv_num, read_dma_length); + } else { + memcpy(read_data, serial_dev->serial_fifo.serial_rx->serial_rx_buffer + serial_dev->serial_fifo.serial_rx->serial_recv_num, + serial_cfg->data_cfg.serial_buffer_size - serial_dev->serial_fifo.serial_rx->serial_recv_num); + memcpy(read_data + serial_cfg->data_cfg.serial_buffer_size - serial_dev->serial_fifo.serial_rx->serial_recv_num, + serial_dev->serial_fifo.serial_rx->serial_rx_buffer, read_dma_length + serial_dev->serial_fifo.serial_rx->serial_recv_num - serial_cfg->data_cfg.serial_buffer_size); + } + SerialDmaRxSetRecvLength(serial_dev, read_dma_length); + read_param->read_length = read_dma_length; + CriticalAreaUnLock(lock); + return EOK; + } else { + if (RET_FALSE == serial_dev->serial_fifo.serial_rx->serial_dma_enable) { + serial_dev->serial_fifo.serial_rx->serial_dma_enable = RET_TRUE; + hwdev_done->dmatransfer(serial_dev, read_data, read_length, SERIAL_DMA_RX); + } else { + ret = ERROR; + KUpdateExstatus(ret); + } + + CriticalAreaUnLock(lock); + return ret; + } +} +#endif + +static inline int SerialDevPollingWrite(struct SerialHardwareDevice *serial_dev, struct BusBlockWriteParam *write_param, uint16 serial_stream_mode) +{ + NULL_PARAM_CHECK(serial_dev); + NULL_PARAM_CHECK(write_param); + + struct SerialHwDevDone *hwdev_done = serial_dev->hwdev_done; + const uint8 *write_data = (const uint8 *)write_param->buffer; + x_size_t write_length = write_param->size; + x_size_t len_result = 0; + while (write_length) + { + if ((*write_data == '\n') && (SIGN_OPER_STREAM == serial_stream_mode)) { + hwdev_done->put_char(serial_dev, '\r'); + } + + hwdev_done->put_char(serial_dev, *write_data); + len_result++; + ++write_data; + --write_length; + } + + return len_result; +} + +static inline int SerialDevPollingRead(struct SerialHardwareDevice *serial_dev, struct BusBlockReadParam *read_param) +{ + NULL_PARAM_CHECK(serial_dev); + NULL_PARAM_CHECK(read_param); + + struct SerialHwDevDone *hwdev_done = serial_dev->hwdev_done; + uint8 *read_data = (uint8 *)read_param->buffer; + x_size_t read_length = read_param->size; + + uint8 get_char; + + while (read_length) + { + get_char = hwdev_done->get_char(serial_dev); + if (-ERROR == get_char) { + break; + } + + *read_data = get_char; + read_data++; + read_length--; + + if ('\n' == get_char) { + break; + } + } + + return EOK; +} + +static uint32 SerialDevOpen(void *dev) +{ + NULL_PARAM_CHECK(dev); + + int serial_operation_cmd; + struct SerialHardwareDevice *serial_dev = (struct SerialHardwareDevice *)dev; + struct Driver *drv = serial_dev->haldev.owner_bus->owner_driver; + struct SerialDriver *serial_drv = (struct SerialDriver *)drv; + struct SerialDevParam *serial_dev_param = (struct SerialDevParam *)serial_dev->haldev.private_data; + struct SerialCfgParam *serial_cfg = (struct SerialCfgParam *)serial_dev->private_data; + + if (EOK != SerialWorkModeCheck(serial_dev_param)) { + KPrintf("SerialDevOpen error!\n"); + return ERROR; + } + + if (NONE == serial_dev->serial_fifo.serial_rx) { + if (SIGN_OPER_INT_RX & serial_dev_param->serial_set_mode) { + serial_dev->serial_fifo.serial_rx = (struct SerialRx *)x_malloc(sizeof(struct SerialRx)); + if (NONE == serial_dev->serial_fifo.serial_rx) { + KPrintf("SerialDevOpen x_malloc serial_rx error\n"); + x_free(serial_dev->serial_fifo.serial_rx); + return ERROR; + } + + serial_dev->serial_fifo.serial_rx->serial_rx_buffer = (uint8 *)x_malloc(serial_cfg->data_cfg.serial_buffer_size); + if (NONE == serial_dev->serial_fifo.serial_rx->serial_rx_buffer) { + KPrintf("SerialDevOpen x_malloc serial_rx_buffer error\n"); + x_free(serial_dev->serial_fifo.serial_rx->serial_rx_buffer); + x_free(serial_dev->serial_fifo.serial_rx); + return ERROR; + } + + memset(serial_dev->serial_fifo.serial_rx->serial_rx_buffer, 0, serial_cfg->data_cfg.serial_buffer_size); + serial_dev->serial_fifo.serial_rx->serial_send_num = 0; + serial_dev->serial_fifo.serial_rx->serial_recv_num = 0; + serial_dev->serial_fifo.serial_rx->serial_rx_full = RET_FALSE; + serial_dev_param->serial_work_mode |= SIGN_OPER_INT_RX; + + serial_operation_cmd = OPER_SET_INT; + serial_drv->drv_done->configure(serial_drv, serial_operation_cmd); + } +#ifdef SERIAL_USING_DMA + else if (SIGN_OPER_DMA_RX & serial_dev_param->serial_set_mode) { + if (0 == serial_cfg->data_cfg.serial_buffer_size) { + serial_dev->serial_fifo.serial_rx = (struct SerialRx *)x_malloc(sizeof(struct SerialRx)); + if (NONE == serial_dev->serial_fifo.serial_rx) { + KPrintf("SerialDevOpen DMA buffer 0 x_malloc serial_rx error\n"); + x_free(serial_dev->serial_fifo.serial_rx); + return ERROR; + } + serial_dev->serial_fifo.serial_rx->serial_dma_enable = RET_FALSE; + serial_dev_param->serial_work_mode |= SIGN_OPER_DMA_RX; + } else { + serial_dev->serial_fifo.serial_rx = (struct SerialRx *)x_malloc(sizeof(struct SerialRx)); + if (NONE == serial_dev->serial_fifo.serial_rx) { + KPrintf("SerialDevOpen DMA x_malloc serial_rx error\n"); + x_free(serial_dev->serial_fifo.serial_rx); + return ERROR; + } + + serial_dev->serial_fifo.serial_rx->serial_rx_buffer = (uint8 *)x_malloc(serial_cfg->data_cfg.serial_buffer_size); + if (NONE == serial_dev->serial_fifo.serial_rx->serial_rx_buffer) { + KPrintf("SerialDevOpen DMA x_malloc serial_rx_buffer error\n"); + x_free(serial_dev->serial_fifo.serial_rx->serial_rx_buffer); + x_free(serial_dev->serial_fifo.serial_rx); + return ERROR; + } + + memset(serial_dev->serial_fifo.serial_rx->serial_rx_buffer, 0, serial_cfg->data_cfg.serial_buffer_size); + serial_dev->serial_fifo.serial_rx->serial_send_num = 0; + serial_dev->serial_fifo.serial_rx->serial_recv_num = 0; + serial_dev->serial_fifo.serial_rx->serial_rx_full = RET_FALSE; + serial_dev_param->serial_work_mode |= SIGN_OPER_DMA_RX; + + int serial_dma_operation = OPER_CONFIG; + serial_drv->drv_done->configure(serial_drv, serial_dma_operation); + } + } +#endif + else { + serial_dev->serial_fifo.serial_rx = NONE; + } + } else { + if (SIGN_OPER_INT_RX & serial_dev_param->serial_set_mode) { + serial_dev_param->serial_work_mode |= SIGN_OPER_INT_RX; + } +#ifdef SERIAL_USING_DMA + else if (SIGN_OPER_DMA_RX & serial_dev_param->serial_set_mode) { + serial_dev_param->serial_work_mode |= SIGN_OPER_DMA_RX; + } +#endif + } + + if (NONE == serial_dev->serial_fifo.serial_tx) { + if (SIGN_OPER_INT_TX & serial_dev_param->serial_set_mode) { + serial_dev->serial_fifo.serial_tx = (struct SerialTx *)x_malloc(sizeof(struct SerialTx)); + if (NONE == serial_dev->serial_fifo.serial_tx) { + KPrintf("SerialDevOpen x_malloc serial_tx error\n"); + x_free(serial_dev->serial_fifo.serial_tx); + return ERROR; + } + + serial_dev->serial_fifo.serial_tx->serial_txfifo_sem = KSemaphoreCreate(0); + serial_dev_param->serial_work_mode |= SIGN_OPER_INT_TX; + + serial_operation_cmd = OPER_SET_INT; + serial_drv->drv_done->configure(serial_drv, serial_operation_cmd); + } +#ifdef SERIAL_USING_DMA + else if (SIGN_OPER_DMA_TX & serial_dev_param->serial_set_mode) { + serial_dev->serial_fifo.serial_tx = (struct SerialTx *)x_malloc(sizeof(struct SerialTx)); + if (NONE == serial_dev->serial_fifo.serial_tx) { + KPrintf("SerialDevOpen DMA x_malloc serial_tx error\n"); + x_free(serial_dev->serial_fifo.serial_tx); + return ERROR; + } + + serial_dev->serial_fifo.serial_tx->serial_dma_enable = RET_FALSE; + serial_dev->serial_fifo.serial_tx->serial_dma_queue.done = g_queue_done[DATA_QUEUE]; + serial_dev->serial_fifo.serial_tx->serial_dma_queue.property = x_malloc(sizeof(DataQueueType)); + ((DataQueueDoneType*)serial_dev->serial_fifo.serial_tx->serial_dma_queue.done)->InitDataqueue((DataQueueType *)serial_dev->serial_fifo.serial_tx->serial_dma_queue.property, 8); + + serial_dev_param->serial_work_mode |= SIGN_OPER_DMA_TX; + serial_operation_cmd = OPER_CONFIG; + serial_drv->drv_done->configure(serial_drv, serial_operation_cmd); + } +#endif + else { + serial_dev->serial_fifo.serial_tx = NONE; + } + } else { + if (SIGN_OPER_INT_TX & serial_dev_param->serial_set_mode) { + serial_dev_param->serial_work_mode |= SIGN_OPER_INT_TX; + } +#ifdef SERIAL_USING_DMA + else if (SIGN_OPER_DMA_TX & serial_dev_param->serial_set_mode) { + serial_dev_param->serial_work_mode |= SIGN_OPER_DMA_TX; + } +#endif + } + + serial_dev->haldev.dev_sem = KSemaphoreCreate(0); + if (serial_dev->haldev.dev_sem < 0) { + KPrintf("SerialDevOpen create sem failed .\n"); + + if (serial_dev->serial_fifo.serial_rx->serial_rx_buffer) { + x_free(serial_dev->serial_fifo.serial_rx->serial_rx_buffer); + } + if (serial_dev->serial_fifo.serial_rx) { + x_free(serial_dev->serial_fifo.serial_rx); + } + if (serial_dev->serial_fifo.serial_tx) { + x_free(serial_dev->serial_fifo.serial_tx); + } + + return ERROR; + } + + return EOK; +} + +static uint32 SerialDevClose(void *dev) +{ + NULL_PARAM_CHECK(dev); + + int serial_operation_cmd = OPER_CLR_INT; + struct SerialHardwareDevice *serial_dev = (struct SerialHardwareDevice *)dev; + struct Driver *drv = serial_dev->haldev.owner_bus->owner_driver; + struct SerialDriver *serial_drv = (struct SerialDriver *)drv; + struct SerialDevParam *serial_dev_param = (struct SerialDevParam *)serial_dev->haldev.private_data; + struct SerialCfgParam *serial_cfg = (struct SerialCfgParam *)serial_dev->private_data; + + if (SIGN_OPER_INT_RX & serial_dev_param->serial_work_mode) { + NULL_PARAM_CHECK(serial_dev->serial_fifo.serial_rx->serial_rx_buffer); + NULL_PARAM_CHECK(serial_dev->serial_fifo.serial_rx); + x_free(serial_dev->serial_fifo.serial_rx->serial_rx_buffer); + x_free(serial_dev->serial_fifo.serial_rx); + + serial_drv->drv_done->configure(serial_drv, serial_operation_cmd); + } +#ifdef SERIAL_USING_DMA + else if (SIGN_OPER_DMA_RX & serial_dev_param->serial_work_mode) { + if(0 == serial_cfg->data_cfg.serial_buffer_size) + { + NULL_PARAM_CHECK(serial_dev->serial_fifo.serial_rx); + x_free(serial_dev->serial_fifo.serial_rx); + } else { + NULL_PARAM_CHECK(serial_dev->serial_fifo.serial_rx->serial_rx_buffer); + NULL_PARAM_CHECK(serial_dev->serial_fifo.serial_rx); + x_free(serial_dev->serial_fifo.serial_rx->serial_rx_buffer); + x_free(serial_dev->serial_fifo.serial_rx); + } + + serial_drv->drv_done->configure(serial_drv, serial_operation_cmd); + } +#endif + + if (SIGN_OPER_INT_TX & serial_dev_param->serial_work_mode) { + NULL_PARAM_CHECK(serial_dev->serial_fifo.serial_tx); + x_free(serial_dev->serial_fifo.serial_tx); + + serial_drv->drv_done->configure(serial_drv, serial_operation_cmd); + } +#ifdef SERIAL_USING_DMA + else if (SIGN_OPER_DMA_TX & serial_dev_param->serial_work_mode) { + NULL_PARAM_CHECK(serial_dev->serial_fifo.serial_tx); + x_free(serial_dev->serial_fifo.serial_tx); + + serial_drv->drv_done->configure(serial_drv, serial_operation_cmd); + } +#endif + + KSemaphoreDelete(serial_dev->haldev.dev_sem); + return EOK; +} + +static uint32 SerialDevWrite(void *dev, struct BusBlockWriteParam *write_param) +{ + NULL_PARAM_CHECK(dev); + NULL_PARAM_CHECK(write_param); + + x_err_t ret = EOK; + + struct SerialHardwareDevice *serial_dev = (struct SerialHardwareDevice *)dev; + struct SerialDevParam *serial_dev_param = (struct SerialDevParam *)serial_dev->haldev.private_data; + + if (serial_dev_param->serial_work_mode & SIGN_OPER_INT_TX) { + ret = SerialDevIntWrite(serial_dev, write_param); + if (ret < 0) { + KPrintf("SerialDevIntWrite error %d\n", ret); + return ERROR; + } + } +#ifdef SERIAL_USING_DMA + else if (serial_dev_param->serial_work_mode & SIGN_OPER_DMA_TX) { + ret = SerialDevDMAWrite(serial_dev, write_param); + if (ret < 0) { + KPrintf("SerialDevDMAWrite error %d\n", ret); + return ERROR; + } + } +#endif + else { + ret = SerialDevPollingWrite(serial_dev, write_param, serial_dev_param->serial_stream_mode); + if (ret < 0) { + KPrintf("SerialDevPollingWrite error %d\n", ret); + return ERROR; + } + } + + return ret; +} + +static uint32 SerialDevRead(void *dev, struct BusBlockReadParam *read_param) +{ + NULL_PARAM_CHECK(dev); + NULL_PARAM_CHECK(read_param); + + x_err_t ret = EOK; + + struct SerialHardwareDevice *serial_dev = (struct SerialHardwareDevice *)dev; + struct SerialDevParam *serial_dev_param = (struct SerialDevParam *)serial_dev->haldev.private_data; + + if (EOK == KSemaphoreObtain(serial_dev->haldev.dev_sem, WAITING_FOREVER)) { + if (serial_dev_param->serial_work_mode & SIGN_OPER_INT_RX) { + ret = SerialDevIntRead(serial_dev, read_param); + if (EOK != ret) { + KPrintf("SerialDevIntRead error %d\n", ret); + return ERROR; + } + } + #ifdef SERIAL_USING_DMA + else if (serial_dev_param->serial_work_mode & SIGN_OPER_DMA_RX) { + ret = SerialDevDMARead(serial_dev, read_param); + if (EOK != ret) { + KPrintf("SerialDevDMARead error %d\n", ret); + return ERROR; + } + } + #endif + else { + ret = SerialDevPollingRead(serial_dev, read_param); + if (EOK != ret) { + KPrintf("SerialDevPollingRead error %d\n", ret); + return ERROR; + } + } + } + return EOK; +} + +void SerialSetIsr(struct SerialHardwareDevice *serial_dev, int event) +{ + switch (event & 0xff) + { + case SERIAL_EVENT_RX_IND: + { + int get_char; + x_base lock; + + struct SerialHwDevDone *hwdev_done = serial_dev->hwdev_done; + struct SerialCfgParam *serial_cfg = (struct SerialCfgParam *)serial_dev->private_data; + + while (1) + { + get_char = hwdev_done->get_char(serial_dev); + if (-ERROR == get_char) { + break; + } + + lock = CriticalAreaLock(); + + serial_dev->serial_fifo.serial_rx->serial_rx_buffer[serial_dev->serial_fifo.serial_rx->serial_send_num] = (uint8)get_char; + serial_dev->serial_fifo.serial_rx->serial_send_num += 1; + if (serial_dev->serial_fifo.serial_rx->serial_send_num >= serial_cfg->data_cfg.serial_buffer_size) { + serial_dev->serial_fifo.serial_rx->serial_send_num = 0; + } + + if (serial_dev->serial_fifo.serial_rx->serial_send_num == serial_dev->serial_fifo.serial_rx->serial_recv_num) { + serial_dev->serial_fifo.serial_rx->serial_recv_num += 1; + serial_dev->serial_fifo.serial_rx->serial_rx_full = RET_TRUE; + if (serial_dev->serial_fifo.serial_rx->serial_recv_num >= serial_cfg->data_cfg.serial_buffer_size) { + serial_dev->serial_fifo.serial_rx->serial_recv_num = 0; + } + } + CriticalAreaUnLock(lock); + } + + x_size_t serial_rx_length; + + lock = CriticalAreaLock(); + if (serial_dev->serial_fifo.serial_rx->serial_recv_num > serial_dev->serial_fifo.serial_rx->serial_send_num) { + serial_rx_length = serial_cfg->data_cfg.serial_buffer_size - serial_dev->serial_fifo.serial_rx->serial_recv_num + serial_dev->serial_fifo.serial_rx->serial_send_num; + } else { + serial_rx_length = serial_dev->serial_fifo.serial_rx->serial_send_num - serial_dev->serial_fifo.serial_rx->serial_recv_num; + } + CriticalAreaUnLock(lock); + + if (serial_rx_length) { + if (serial_dev->haldev.dev_recv_callback) { + serial_dev->haldev.dev_recv_callback((void *)serial_dev, serial_rx_length); + } + + KSemaphoreAbandon(serial_dev->haldev.dev_sem); + } + break; + } + case SERIAL_event_id_tX_DONE: + { + KSemaphoreAbandon(serial_dev->serial_fifo.serial_tx->serial_txfifo_sem); + break; + } +#ifdef SERIAL_USING_DMA + case SERIAL_event_id_tX_DMADONE: + { + const void *data_ptr; + x_size_t DataSize; + const void *last_data_ptr; + + struct SerialHwDevDone *hwdev_done = serial_dev->hwdev_done; + + ((DataQueueDoneType*)serial_dev->serial_fifo.serial_tx->serial_dma_queue.done)->PopDataqueue((DataQueueType *)serial_dev->serial_fifo.serial_tx->serial_dma_queue.property, &last_data_ptr, &DataSize, 0); + if (EOK == ((DataQueueDoneType*)serial_dev->serial_fifo.serial_tx->serial_dma_queue.done)->DataqueuePeak((DataQueueType *)serial_dev->serial_fifo.serial_tx->serial_dma_queue.property, &data_ptr, &DataSize)) { + serial_dev->serial_fifo.serial_tx->serial_dma_enable = RET_TRUE; + hwdev_done->dmatransfer(serial_dev, (uint8 *)data_ptr, DataSize, SERIAL_DMA_TX); + } else { + serial_dev->serial_fifo.serial_tx->serial_dma_enable = RET_FALSE; + } + break; + } + case SERIAL_EVENT_RX_DMADONE: + { + int length; + x_base lock; + + struct SerialCfgParam *serial_cfg = (struct SerialCfgParam *)serial_dev->private_data; + + length = (event & (~0xff)) >> 8; + + if (serial_cfg->data_cfg.serial_buffer_size) { + lock = CriticalAreaLock(); + + SerialDmaRxSetSendLength(serial_dev, length); + + length = SerialGetRxFifoLength(serial_dev); + + CriticalAreaUnLock(lock); + if (serial_dev->haldev.dev_recv_callback) { + serial_dev->haldev.dev_recv_callback((void *)serial_dev, length); + } + KSemaphoreAbandon(serial_dev->haldev.dev_sem); + } else { + serial_dev->serial_fifo.serial_rx->serial_dma_enable = RET_FALSE; + if (serial_dev->haldev.dev_recv_callback) { + serial_dev->haldev.dev_recv_callback((void *)serial_dev, length); + } + KSemaphoreAbandon(serial_dev->haldev.dev_sem); + } + break; + } +#endif + } +} + +const struct SerialDevDone dev_done = +{ + .open = SerialDevOpen, + .close = SerialDevClose, + .write = SerialDevWrite, + .read = SerialDevRead, +}; + +/*Create the serial device linklist*/ +static void SerialDeviceLinkInit() +{ + InitDoubleLinkList(&serialdev_linklist); +} + +HardwareDevType SerialDeviceFind(const char *dev_name, enum DevType dev_type) +{ + NULL_PARAM_CHECK(dev_name); + + struct HardwareDev *device = NONE; + + DoubleLinklistType *node = NONE; + DoubleLinklistType *head = &serialdev_linklist; + + for (node = head->node_next; node != head; node = node->node_next) { + device = SYS_DOUBLE_LINKLIST_ENTRY(node, struct HardwareDev, dev_link); + if ((!strcmp(device->dev_name, dev_name)) && (dev_type == device->dev_type)) { + return device; + } + } + + KPrintf("SerialDeviceFind cannot find the %s device.return NULL\n", dev_name); + return NONE; +} + +int SerialDeviceRegister(struct SerialHardwareDevice *serial_device, void *serial_param, const char *device_name) +{ + NULL_PARAM_CHECK(serial_device); + NULL_PARAM_CHECK(device_name); + + x_err_t ret = EOK; + static x_bool dev_link_flag = RET_FALSE; + + if (!dev_link_flag) { + SerialDeviceLinkInit(); + dev_link_flag = RET_TRUE; + } + + if (DEV_INSTALL != serial_device->haldev.dev_state) { + strncpy(serial_device->haldev.dev_name, device_name, NAME_NUM_MAX); + serial_device->haldev.dev_type = TYPE_SERIAL_DEV; + serial_device->haldev.dev_state = DEV_INSTALL; + + if (serial_device->ext_serial_mode) { + serial_device->haldev.dev_done = (struct HalDevDone *)serial_device->dev_done; + } else { + serial_device->haldev.dev_done = (struct HalDevDone *)&dev_done; + } + + serial_device->private_data = serial_param; + + DoubleLinkListInsertNodeAfter(&serialdev_linklist, &(serial_device->haldev.dev_link)); + } else { + KPrintf("SerialDeviceRegister device has been register state%u\n", serial_device->haldev.dev_state); + } + + return ret; +} + +int SerialDeviceAttachToBus(const char *dev_name, const char *bus_name) +{ + NULL_PARAM_CHECK(dev_name); + NULL_PARAM_CHECK(bus_name); + + x_err_t ret = EOK; + + struct Bus *bus; + struct HardwareDev *device; + + bus = BusFind(bus_name); + if (NONE == bus) { + KPrintf("SerialDeviceAttachToBus find serial bus error!name %s\n", bus_name); + return ERROR; + } + + if (TYPE_SERIAL_BUS == bus->bus_type) { + device = SerialDeviceFind(dev_name, TYPE_SERIAL_DEV); + if (NONE == device) { + KPrintf("SerialDeviceAttachToBus find serial device error!name %s\n", dev_name); + return ERROR; + } + + if (TYPE_SERIAL_DEV == device->dev_type) { + ret = DeviceRegisterToBus(bus, device); + if (EOK != ret) { + KPrintf("SerialDeviceAttachToBus DeviceRegisterToBus error %u\n", ret); + return ERROR; + } + } + } + + return EOK; +} diff --git a/Ubiquitous/XiZi/resources/serial/drv_serial.c b/Ubiquitous/XiZi/resources/serial/drv_serial.c new file mode 100644 index 0000000..b0cf3a3 --- /dev/null +++ b/Ubiquitous/XiZi/resources/serial/drv_serial.c @@ -0,0 +1,68 @@ +/* +* Copyright (c) 2020 AIIT XUOS Lab +* XiUOS is licensed under Mulan PSL v2. +* You can use this software according to the terms and conditions of the Mulan PSL v2. +* You may obtain a copy of Mulan PSL v2 at: +* http://license.coscl.org.cn/MulanPSL2 +* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, +* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, +* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. +* See the Mulan PSL v2 for more details. +*/ + +/** +* @file drv_serial.c +* @brief register serial drv function using bus driver framework +* @version 1.0 +* @author AIIT XUOS Lab +* @date 2021-04-24 +*/ + +#include +#include + +static DoubleLinklistType serialdrv_linklist; + +/*Create the driver linklist*/ +static void SerialDrvLinkInit() +{ + InitDoubleLinkList(&serialdrv_linklist); +} + +DriverType SerialDriverFind(const char *drv_name, enum DriverType_e drv_type) +{ + NULL_PARAM_CHECK(drv_name); + + struct Driver *driver = NONE; + + DoubleLinklistType *node = NONE; + DoubleLinklistType *head = &serialdrv_linklist; + + for (node = head->node_next; node != head; node = node->node_next) { + driver = SYS_DOUBLE_LINKLIST_ENTRY(node, struct Driver, driver_link); + + if ((!strcmp(driver->drv_name, drv_name)) && (drv_type == driver->driver_type)) { + return driver; + } + } + + KPrintf("SerialDriverFind cannot find the %s driver.return NULL\n", drv_name); + return NONE; +} + +int SerialDriverRegister(struct Driver *driver) +{ + NULL_PARAM_CHECK(driver); + + x_err_t ret = EOK; + static x_bool driver_link_flag = RET_FALSE; + + if (!driver_link_flag) { + SerialDrvLinkInit(); + driver_link_flag = RET_TRUE; + } + + DoubleLinkListInsertNodeAfter(&serialdrv_linklist, &(driver->driver_link)); + + return ret; +} diff --git a/Ubiquitous/XiZi/resources/spi/Makefile b/Ubiquitous/XiZi/resources/spi/Makefile new file mode 100644 index 0000000..c7258bc --- /dev/null +++ b/Ubiquitous/XiZi/resources/spi/Makefile @@ -0,0 +1,16 @@ +SRC_FILES += dev_spi.c bus_spi.c drv_spi.c + +SRC_DIR := third_party_spi + +ifeq ($(CONFIG_RESOURCES_SPI_SD), y) + SRC_DIR += sd_card_spi +endif + +ifeq ($(CONFIG_RESOURCES_SPI_SFUD),y) + SRC_FILES += flash_spi.c +endif + +include $(KERNEL_ROOT)/compiler.mk + + + diff --git a/Ubiquitous/XiZi/resources/spi/bus_spi.c b/Ubiquitous/XiZi/resources/spi/bus_spi.c new file mode 100644 index 0000000..6aec604 --- /dev/null +++ b/Ubiquitous/XiZi/resources/spi/bus_spi.c @@ -0,0 +1,117 @@ +/* +* Copyright (c) 2020 AIIT XUOS Lab +* XiUOS is licensed under Mulan PSL v2. +* You can use this software according to the terms and conditions of the Mulan PSL v2. +* You may obtain a copy of Mulan PSL v2 at: +* http://license.coscl.org.cn/MulanPSL2 +* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, +* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, +* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. +* See the Mulan PSL v2 for more details. +*/ + +/** +* @file bus_spi.c +* @brief register spi bus function using bus driver framework +* @version 1.0 +* @author AIIT XUOS Lab +* @date 2021-04-24 +*/ + +#include +#include + +int SpiBusInit(struct SpiBus *spi_bus, const char *bus_name) +{ + NULL_PARAM_CHECK(spi_bus); + NULL_PARAM_CHECK(bus_name); + + x_err_t ret = EOK; + + if (BUS_INSTALL != spi_bus->bus.bus_state) { + strncpy(spi_bus->bus.bus_name, bus_name, NAME_NUM_MAX); + + spi_bus->bus.bus_type = TYPE_SPI_BUS; + spi_bus->bus.bus_state = BUS_INSTALL; + spi_bus->bus.private_data = spi_bus->private_data; + + ret = BusRegister(&spi_bus->bus); + if (EOK != ret) { + KPrintf("SpiBusInit BusRegister error %u\n", ret); + return ret; + } + } else { + KPrintf("SpiBusInit BusRegister bus has been register state%u\n", spi_bus->bus.bus_state); + } + + return ret; +} + +int SpiDriverInit(struct SpiDriver *spi_driver, const char *driver_name) +{ + NULL_PARAM_CHECK(spi_driver); + NULL_PARAM_CHECK(driver_name); + + x_err_t ret = EOK; + + if (DRV_INSTALL != spi_driver->driver.driver_state) { + spi_driver->driver.driver_type = TYPE_SPI_DRV; + spi_driver->driver.driver_state = DRV_INSTALL; + + strncpy(spi_driver->driver.drv_name, driver_name, NAME_NUM_MAX); + + spi_driver->driver.configure = spi_driver->configure; + + ret = SpiDriverRegister(&spi_driver->driver); + if (EOK != ret) { + KPrintf("SpiDriverInit DriverRegister error %u\n", ret); + return ret; + } + } else { + KPrintf("SpiDriverInit DriverRegister driver has been register state%u\n", spi_driver->driver.driver_state); + } + + return ret; +} + +int SpiReleaseBus(struct SpiBus *spi_bus) +{ + NULL_PARAM_CHECK(spi_bus); + + return BusRelease(&spi_bus->bus); +} + +int SpiDriverAttachToBus(const char *drv_name, const char *bus_name) +{ + NULL_PARAM_CHECK(drv_name); + NULL_PARAM_CHECK(bus_name); + + x_err_t ret = EOK; + + struct Bus *bus; + struct Driver *driver; + + bus = BusFind(bus_name); + if (NONE == bus) { + KPrintf("SpiDriverAttachToBus find spi bus error!name %s\n", bus_name); + return ERROR; + } + + if (TYPE_SPI_BUS == bus->bus_type) { + driver = SpiDriverFind(drv_name, TYPE_SPI_DRV); + if (NONE == driver) { + KPrintf("SpiDriverAttachToBus find spi driver error!name %s\n", drv_name); + return ERROR; + } + + if (TYPE_SPI_DRV == driver->driver_type) { + ret = DriverRegisterToBus(bus, driver); + if (EOK != ret) { + KPrintf("SpiDriverAttachToBus DriverRegisterToBus error %u\n", ret); + return ERROR; + } + } + } + + return ret; +} diff --git a/Ubiquitous/XiZi/resources/spi/dev_spi.c b/Ubiquitous/XiZi/resources/spi/dev_spi.c new file mode 100644 index 0000000..8e16da4 --- /dev/null +++ b/Ubiquitous/XiZi/resources/spi/dev_spi.c @@ -0,0 +1,235 @@ +/* +* Copyright (c) 2020 AIIT XUOS Lab +* XiUOS is licensed under Mulan PSL v2. +* You can use this software according to the terms and conditions of the Mulan PSL v2. +* You may obtain a copy of Mulan PSL v2 at: +* http://license.coscl.org.cn/MulanPSL2 +* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, +* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, +* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. +* See the Mulan PSL v2 for more details. +*/ + +/** +* @file dev_spi.c +* @brief register spi dev function using bus driver framework +* @version 1.0 +* @author AIIT XUOS Lab +* @date 2021-04-24 +*/ + +#include +#include + +static DoubleLinklistType spidev_linklist; + +/*Create the spi device linklist*/ +static void SpiDeviceLinkInit() +{ + InitDoubleLinkList(&spidev_linklist); +} + +static uint32 SpiDeviceOpen(void *dev) +{ + NULL_PARAM_CHECK(dev); + + SpiDevConfigureCs(dev, 1, 0); + + return EOK; +} + +static uint32 SpiDeviceClose(void *dev) +{ + NULL_PARAM_CHECK(dev); + + SpiDevConfigureCs(dev, 0, 1); + + return EOK; +} + +static uint32 SpiDeviceWrite(void *dev, struct BusBlockWriteParam *write_param) +{ + NULL_PARAM_CHECK(dev); + NULL_PARAM_CHECK(write_param); + + int ret; + struct SpiHardwareDevice *spi_dev = (struct SpiHardwareDevice *)dev; + struct SpiDataStandard *spi_msg; + + spi_msg = (struct SpiDataStandard *)x_malloc(sizeof(struct SpiDataStandard)); + if (NONE == spi_msg) { + KPrintf("SpiDeviceWrite x_malloc msg error\n"); + x_free(spi_msg); + return ERROR; + } + + //memset(spi_msg, 0, sizeof(struct SpiDataStandard)); + + spi_msg->tx_buff = (uint8 *)write_param->buffer; + spi_msg->rx_buff = NONE; + spi_msg->length = write_param->size; + spi_msg->spi_chip_select = 0; + spi_msg->spi_cs_release = 0; + spi_msg->next = NONE; + + ret = spi_dev->spi_dev_done->dev_write(spi_dev, spi_msg); + x_free(spi_msg); + + return ret; +} + +static uint32 SpiDeviceRead(void *dev, struct BusBlockReadParam *read_param) +{ + NULL_PARAM_CHECK(dev); + NULL_PARAM_CHECK(read_param); + + int ret; + struct SpiHardwareDevice *spi_dev = (struct SpiHardwareDevice *)dev; + struct SpiDataStandard *spi_msg; + + spi_msg = (struct SpiDataStandard *)x_malloc(sizeof(struct SpiDataStandard)); + if (NONE == spi_msg) { + KPrintf("SpiDeviceRead x_malloc msg error\n"); + x_free(spi_msg); + return ERROR; + } + + //memset(spi_msg, 0, sizeof(struct SpiDataStandard)); + + spi_msg->tx_buff = NONE; + spi_msg->rx_buff = (uint8 *)read_param->buffer; + spi_msg->length = read_param->size; + spi_msg->spi_chip_select = 0; + spi_msg->spi_cs_release = 0; + spi_msg->next = NONE; + + ret = spi_dev->spi_dev_done->dev_read(spi_dev, spi_msg); + x_free(spi_msg); + + return ret; +} + +static const struct HalDevDone dev_done = +{ + .open = SpiDeviceOpen, + .close = SpiDeviceClose, + .write = SpiDeviceWrite, + .read = SpiDeviceRead, +}; + +HardwareDevType SpiDeviceFind(const char *dev_name, enum DevType dev_type) +{ + NULL_PARAM_CHECK(dev_name); + + struct HardwareDev *device = NONE; + + DoubleLinklistType *node = NONE; + DoubleLinklistType *head = &spidev_linklist; + + for (node = head->node_next; node != head; node = node->node_next) { + device = SYS_DOUBLE_LINKLIST_ENTRY(node, struct HardwareDev, dev_link); + if ((!strcmp(device->dev_name, dev_name)) && (dev_type == device->dev_type)) { + return device; + } + } + + KPrintf("SpiDeviceFind cannot find the %s device.return NULL\n", dev_name); + return NONE; +} + +int SpiDeviceRegister(struct SpiHardwareDevice *spi_device, void *spi_param, const char *device_name) +{ + NULL_PARAM_CHECK(spi_device); + NULL_PARAM_CHECK(device_name); + + x_err_t ret = EOK; + static x_bool dev_link_flag = RET_FALSE; + + if (!dev_link_flag) { + SpiDeviceLinkInit(); + dev_link_flag = RET_TRUE; + } + + if (DEV_INSTALL != spi_device->haldev.dev_state) { + strncpy(spi_device->haldev.dev_name, device_name, NAME_NUM_MAX); + spi_device->haldev.dev_type = TYPE_SPI_DEV; + spi_device->haldev.dev_state = DEV_INSTALL; + + //only spi bus dev need to register dev_done + if (RET_TRUE != spi_device->spi_dev_flag) { + spi_device->haldev.dev_done = &dev_done; + } + + spi_device->haldev.private_data = spi_param; + + DoubleLinkListInsertNodeAfter(&spidev_linklist, &(spi_device->haldev.dev_link)); + } else { + KPrintf("SpiDeviceRegister device has been register state%u\n", spi_device->haldev.dev_state); + } + + return ret; +} + +int SpiDeviceAttachToBus(const char *dev_name, const char *bus_name) +{ + NULL_PARAM_CHECK(dev_name); + NULL_PARAM_CHECK(bus_name); + + x_err_t ret = EOK; + + struct Bus *bus; + struct HardwareDev *device; + + bus = BusFind(bus_name); + if (NONE == bus) { + KPrintf("SpiDeviceAttachToBus find spi bus error!name %s\n", bus_name); + return ERROR; + } + + if (TYPE_SPI_BUS == bus->bus_type) { + device = SpiDeviceFind(dev_name, TYPE_SPI_DEV); + if (NONE == device) { + KPrintf("SpiDeviceAttachToBus find spi device error!name %s\n", dev_name); + return ERROR; + } + + if (TYPE_SPI_DEV == device->dev_type) { + ret = DeviceRegisterToBus(bus, device); + if (EOK != ret) { + KPrintf("SpiDeviceAttachToBus DeviceRegisterToBus error %u\n", ret); + return ERROR; + } + } + } + + return EOK; +} + +int SpiDevConfigureCs(struct HardwareDev *dev, uint8 spi_chip_select, uint8 spi_cs_release) +{ + NULL_PARAM_CHECK(dev); + + int ret; + struct SpiHardwareDevice *spi_dev = (struct SpiHardwareDevice *)dev; + struct SpiDataStandard *msg; + + msg = (struct SpiDataStandard *)x_malloc(sizeof(struct SpiDataStandard)); + if (NONE == msg) { + KPrintf("SpiDevConfigureCs x_malloc msg error\n"); + x_free(msg); + return ERROR; + } + + //memset(msg, 0, sizeof(struct SpiDataStandard)); + msg->length = 0; + msg->rx_buff = NONE; + msg->tx_buff = NONE; + msg->next = NONE; + msg->spi_chip_select = spi_chip_select; + msg->spi_cs_release = spi_cs_release; + + ret = spi_dev->spi_dev_done->dev_write(spi_dev, msg); + + x_free(msg); + return ret; +} diff --git a/Ubiquitous/XiZi/resources/spi/drv_spi.c b/Ubiquitous/XiZi/resources/spi/drv_spi.c new file mode 100644 index 0000000..7dc1508 --- /dev/null +++ b/Ubiquitous/XiZi/resources/spi/drv_spi.c @@ -0,0 +1,67 @@ +/* +* Copyright (c) 2020 AIIT XUOS Lab +* XiUOS is licensed under Mulan PSL v2. +* You can use this software according to the terms and conditions of the Mulan PSL v2. +* You may obtain a copy of Mulan PSL v2 at: +* http://license.coscl.org.cn/MulanPSL2 +* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, +* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, +* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. +* See the Mulan PSL v2 for more details. +*/ + +/** +* @file drv_spi.c +* @brief register spi drv function using bus driver framework +* @version 1.0 +* @author AIIT XUOS Lab +* @date 2021-04-24 +*/ + +#include +#include + +static DoubleLinklistType spidrv_linklist; + +/*Create the driver linklist*/ +static void SpiDrvLinkInit() +{ + InitDoubleLinkList(&spidrv_linklist); +} + +DriverType SpiDriverFind(const char *drv_name, enum DriverType_e drv_type) +{ + NULL_PARAM_CHECK(drv_name); + + struct Driver *driver = NONE; + + DoubleLinklistType *node = NONE; + DoubleLinklistType *head = &spidrv_linklist; + + for (node = head->node_next; node != head; node = node->node_next) { + driver = SYS_DOUBLE_LINKLIST_ENTRY(node, struct Driver, driver_link); + if ((!strcmp(driver->drv_name, drv_name)) && (drv_type == driver->driver_type)) { + return driver; + } + } + + KPrintf("SpiDriverFind cannot find the %s driver.return NULL\n", drv_name); + return NONE; +} + +int SpiDriverRegister(struct Driver *driver) +{ + NULL_PARAM_CHECK(driver); + + x_err_t ret = EOK; + static x_bool driver_link_flag = RET_FALSE; + + if (!driver_link_flag) { + SpiDrvLinkInit(); + driver_link_flag = RET_TRUE; + } + + DoubleLinkListInsertNodeAfter(&spidrv_linklist, &(driver->driver_link)); + + return ret; +} diff --git a/Ubiquitous/XiZi/resources/spi/flash_spi.c b/Ubiquitous/XiZi/resources/spi/flash_spi.c new file mode 100644 index 0000000..c9a5b91 --- /dev/null +++ b/Ubiquitous/XiZi/resources/spi/flash_spi.c @@ -0,0 +1,368 @@ +/* +* Copyright (c) 2020 AIIT XUOS Lab +* XiUOS is licensed under Mulan PSL v2. +* You can use this software according to the terms and conditions of the Mulan PSL v2. +* You may obtain a copy of Mulan PSL v2 at: +* http://license.coscl.org.cn/MulanPSL2 +* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, +* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, +* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. +* See the Mulan PSL v2 for more details. +*/ + +/** +* @file flash_spi.c +* @brief support spi-flash dev function using spi bus driver framework +* @version 1.0 +* @author AIIT XUOS Lab +* @date 2021-04-24 +*/ + +#include +#include +#include + +/** + * This function supports to write data to the flash. + * + * @param dev flash dev descriptor + * @param write_param flash dev write datacfg param + */ +static uint32 SpiFlashWrite(void *dev, struct BusBlockWriteParam *write_param) +{ + NULL_PARAM_CHECK(dev); + NULL_PARAM_CHECK(write_param); + + x_err_t ret = EOK; + + x_OffPos pos; + x_size_t size; + const uint8 *write_buffer; + + sfud_flash *sfud_flash_dev; + + SpiFlashDeviceType spi_flash_dev; + HardwareDevType haldev = (struct HardwareDev *)dev; + struct SpiHardwareDevice *flash_dev; + + struct BusBlockWriteParam *flash_write_param = (struct BusBlockWriteParam *)write_param->buffer; + + flash_dev = CONTAINER_OF(haldev, struct SpiHardwareDevice, haldev); + spi_flash_dev = CONTAINER_OF(flash_dev, struct SpiFlashDevice, flash_dev); + sfud_flash_dev = (sfud_flash *)spi_flash_dev->flash_param.flash_private_data; + + pos = flash_write_param->pos;// * spi_flash_dev->flash_param.flash_block_param.sector_bytes; + size = flash_write_param->size;// * spi_flash_dev->flash_param.flash_block_param.sector_bytes; + write_buffer = (uint8 *)flash_write_param->buffer; + + KPrintf("flash write pos %u sector_bytes %u size %u\n", + flash_write_param->pos, + spi_flash_dev->flash_param.flash_block_param.sector_bytes, + flash_write_param->size); + + ret = sfud_erase_write(sfud_flash_dev, pos, size, write_buffer); + if (SFUD_SUCCESS != ret) { + KPrintf("SpiFlashWrite error %d pos %d size %d buffer %p\n", ret, pos, size, write_buffer); + return ERROR; + } + + haldev->owner_bus->owner_haldev = haldev; + + return ret; +} + +/** + * This function supports to read data from the flash. + * + * @param dev flash dev descriptor + * @param read_param flash dev read datacfg param + */ +static uint32 SpiFlashRead(void *dev, struct BusBlockReadParam *read_param) +{ + NULL_PARAM_CHECK(dev); + NULL_PARAM_CHECK(read_param); + + x_err_t ret = EOK; + x_OffPos pos; + x_size_t size; + uint8 *read_buffer; + + sfud_flash *sfud_flash_dev; + + SpiFlashDeviceType spi_flash_dev; + HardwareDevType haldev = (struct HardwareDev *)dev; + struct SpiHardwareDevice *flash_dev; + + struct BusBlockReadParam *flash_read_param = (struct BusBlockReadParam *)read_param->buffer; + + flash_dev = CONTAINER_OF(haldev, struct SpiHardwareDevice, haldev); + spi_flash_dev = CONTAINER_OF(flash_dev, struct SpiFlashDevice, flash_dev); + sfud_flash_dev = (sfud_flash *)spi_flash_dev->flash_param.flash_private_data; + + pos = flash_read_param->pos;// * spi_flash_dev->flash_param.flash_block_param.sector_bytes; + size = flash_read_param->size;// * spi_flash_dev->flash_param.flash_block_param.sector_bytes; + read_buffer = (uint8 *)flash_read_param->buffer; + + ret = sfud_read(sfud_flash_dev, pos, size, read_buffer); + if (SFUD_SUCCESS != ret) { + KPrintf("SpiFlashRead error %d pos %d size %d buffer %p\n", ret, pos, size, read_buffer); + return ERROR; + } + + flash_read_param->read_length = flash_read_param->size; + read_param->read_length = flash_read_param->size; + + haldev->owner_bus->owner_haldev = haldev; + + KPrintf("SpiFlashRead read buffer done\n"); + + return ret; +} + +/** + * This function supports to get block data from the flash dev. + * + * @param dev flash dev descriptor + * @param block_param flash dev read datacfg param + */ +static int SpiFlashControl(struct HardwareDev *dev, struct HalDevBlockParam *block_param) +{ + NULL_PARAM_CHECK(dev); + NULL_PARAM_CHECK(block_param); + + x_err_t ret = EOK; + x_size_t size; + uint32_t addr; + + sfud_flash *sfud_flash_dev; + + SpiFlashDeviceType spi_flash_dev; + struct SpiHardwareDevice *flash_dev; + + flash_dev = CONTAINER_OF(dev, struct SpiHardwareDevice, haldev); + spi_flash_dev = CONTAINER_OF(flash_dev, struct SpiFlashDevice, flash_dev); + sfud_flash_dev = (sfud_flash *)spi_flash_dev->flash_param.flash_private_data; + + if (OPER_BLK_GETGEOME == block_param->cmd) { + block_param->dev_block.size_perbank = spi_flash_dev->flash_param.flash_block_param.sector_bytes; + block_param->dev_block.block_size = spi_flash_dev->flash_param.flash_block_param.block_size; + block_param->dev_block.bank_num = spi_flash_dev->flash_param.flash_block_param.sector_num; + } else if (OPER_BLK_ERASE == block_param->cmd) { + NULL_PARAM_CHECK(block_param->dev_addr); + if (block_param->dev_addr->start > block_param->dev_addr->end) { + KPrintf("SpiFlashControl erase start %u > end %u addr\n", block_param->dev_addr->start, block_param->dev_addr->end); + return ERROR; + } else if (block_param->dev_addr->start == block_param->dev_addr->end) { + block_param->dev_addr->end++; + } + + addr = block_param->dev_addr->start * spi_flash_dev->flash_param.flash_block_param.sector_bytes; + size = (block_param->dev_addr->end - block_param->dev_addr->start)* spi_flash_dev->flash_param.flash_block_param.sector_bytes; + + ret = sfud_erase(sfud_flash_dev, addr, size); + if (SFUD_SUCCESS != ret) { + KPrintf("SpiFlashControl erase error %d addr %p size %d\n", ret, addr, size); + return ERROR; + } + } else { + KPrintf("SpiFlashControl do not suppot the cmd 0x%x\n", block_param->cmd); + } + + return ret; +} + +static uint32 FlashSpiConfigure(SpiFlashDeviceType spi_flash_dev) +{ + NULL_PARAM_CHECK(spi_flash_dev); + + x_err_t ret = EOK; + + struct Driver *spi_drv = spi_flash_dev->spi_dev->haldev.owner_bus->owner_driver; + + struct BusConfigureInfo configure_info; + struct SpiMasterParam spi_master_param; + spi_master_param.spi_data_bit_width = 8; + spi_master_param.spi_work_mode = SPI_MODE_0 | SPI_MSB; + spi_master_param.spi_maxfrequency = SPI_FLASH_FREQUENCY; + spi_master_param.spi_data_endian = 0; + + ret = spi_flash_dev->spi_dev->haldev.owner_bus->match(spi_drv, &spi_flash_dev->spi_dev->haldev); + if (EOK != ret) { + KPrintf("FLASH SPI dev match spi drv error!\n"); + return ret; + } + + configure_info.configure_cmd = OPE_CFG; + configure_info.private_data = (void *)&spi_master_param; + ret = BusDrvConfigure(spi_drv, &configure_info); + if (ret) { + KPrintf("spi drv OPE_CFG error drv %8p cfg %8p\n", spi_drv, &spi_master_param); + return ERROR; + } + + configure_info.configure_cmd = OPE_INT; + ret = BusDrvConfigure(spi_drv, &configure_info); + if (ret) { + KPrintf("spi drv OPE_INT error drv %8p\n", spi_drv); + return ERROR; + } + + return ret; +} + +/** + * This function supports to find sfud_flash descriptor by flash_name + * + * @param flash_name flash dev name + */ +sfud_flash_t SpiFlashFind(char *flash_name) +{ + NULL_PARAM_CHECK(flash_name); + + HardwareDevType haldev = SpiDeviceFind(flash_name, TYPE_SPI_DEV); + if (NONE == haldev) { + KPrintf("SpiFlashFind %s error! \n", flash_name); + return NONE; + } + + struct SpiHardwareDevice *flash_dev = CONTAINER_OF(haldev, struct SpiHardwareDevice, haldev); + + SpiFlashDeviceType spi_flash_dev = CONTAINER_OF(flash_dev, struct SpiFlashDevice, flash_dev); + + sfud_flash_t sfud_flash_dev = (sfud_flash_t)spi_flash_dev->flash_param.flash_private_data; + + return sfud_flash_dev; +} + +static const struct FlashDevDone flash_done = +{ + .open = NONE, + .close = NONE, + .write = SpiFlashWrite, + .read = SpiFlashRead, +}; + +/** + * This function supports to init spi_flash_dev and sfud_flash descriptor + * + * @param bus_name spi bus name + * @param dev_name spi dev name + * @param drv_name spi drv name + * @param flash_name flash dev name + */ +SpiFlashDeviceType SpiFlashInit(char *bus_name, char *dev_name, char *drv_name, char *flash_name) +{ + NULL_PARAM_CHECK(dev_name); + NULL_PARAM_CHECK(drv_name); + NULL_PARAM_CHECK(flash_name); + NULL_PARAM_CHECK(bus_name); + + x_err_t ret; + + HardwareDevType haldev = SpiDeviceFind(dev_name, TYPE_SPI_DEV); + if (NONE == haldev) { + KPrintf("SpiFlashInit find spi haldev %s error! \n", dev_name); + return NONE; + } + + SpiFlashDeviceType spi_flash_dev = (SpiFlashDeviceType)malloc(sizeof(struct SpiFlashDevice)); + if (NONE == spi_flash_dev) { + KPrintf("SpiFlashInit malloc spi_flash_dev failed\n"); + free(spi_flash_dev); + return NONE; + } + + sfud_flash *sfud_flash_dev = (sfud_flash_t)malloc(sizeof(sfud_flash)); + if (NONE == sfud_flash_dev) { + KPrintf("SpiFlashInit malloc sfud_flash_dev failed\n"); + free(spi_flash_dev); + free(sfud_flash_dev); + return NONE; + } + + memset(spi_flash_dev, 0, sizeof(struct SpiFlashDevice)); + memset(sfud_flash_dev, 0, sizeof(sfud_flash)); + + spi_flash_dev->spi_dev = CONTAINER_OF(haldev, struct SpiHardwareDevice, haldev); + + spi_flash_dev->flash_dev.spi_dev_flag = RET_TRUE; + spi_flash_dev->flash_param.flash_private_data = (void *)sfud_flash_dev; + spi_flash_dev->flash_dev.haldev.dev_done = (struct HalDevDone *)&flash_done; + spi_flash_dev->flash_dev.haldev.dev_block_control = SpiFlashControl; + + spi_flash_dev->spi_dev->haldev.owner_bus->owner_driver = SpiDriverFind(drv_name, TYPE_SPI_DRV); + if (NONE == spi_flash_dev->spi_dev->haldev.owner_bus->owner_driver) { + KPrintf("SpiFlashInit find spi driver %s error! \n", drv_name); + free(spi_flash_dev); + free(sfud_flash_dev); + return NONE; + } + + ret = FlashSpiConfigure(spi_flash_dev); + if (EOK != ret) { + KPrintf("SpiFlashInit configure failed\n"); + free(spi_flash_dev); + free(sfud_flash_dev); + return NONE; + } + + sfud_flash_dev->name = flash_name; + sfud_flash_dev->user_data = (void *)spi_flash_dev; + + sfud_flash_dev->spi.name = dev_name; + sfud_flash_dev->spi.user_data = (void *)sfud_flash_dev; + + ret = sfud_device_init(sfud_flash_dev); + if (SFUD_SUCCESS != ret) { + KPrintf("sfud_device_init failed %d\n", ret); + free(spi_flash_dev); + free(sfud_flash_dev); + return NONE; + } + + spi_flash_dev->flash_param.flash_block_param.block_size = sfud_flash_dev->chip.erase_gran; + spi_flash_dev->flash_param.flash_block_param.sector_bytes = sfud_flash_dev->chip.erase_gran; + spi_flash_dev->flash_param.flash_block_param.sector_num = sfud_flash_dev->chip.capacity / sfud_flash_dev->chip.erase_gran; + + ret = SpiDeviceRegister(&spi_flash_dev->flash_dev, NONE, flash_name); + if (EOK != ret) { + KPrintf("SpiFlashInit SpiDeviceRegister device %s error %d\n", flash_name, ret); + free(spi_flash_dev); + free(sfud_flash_dev); + return NONE; + } + + ret = SpiDeviceAttachToBus(flash_name, bus_name); + if (EOK != ret) { + KPrintf("SpiFlashInit SpiDeviceAttachToBus device %s error %d\n", flash_name, ret); + free(spi_flash_dev); + free(sfud_flash_dev); + return NONE; + } + + spi_flash_dev->flash_lock = KMutexCreate(); + + return spi_flash_dev; +} + +/** + * This function supports to release spi_flash_dev and sfud_flash descriptor + * + * @param spi_flash_dev spi flash descriptor + */ +uint32 SpiFlashRelease(SpiFlashDeviceType spi_flash_dev) +{ + NULL_PARAM_CHECK(spi_flash_dev); + + x_err_t ret; + sfud_flash *sfud_flash_dev = (sfud_flash_t)spi_flash_dev->flash_param.flash_private_data; + + DeviceDeleteFromBus(spi_flash_dev->flash_dev.haldev.owner_bus, &spi_flash_dev->flash_dev.haldev); + + KMutexDelete(spi_flash_dev->flash_lock); + + free(sfud_flash_dev); + free(spi_flash_dev); + + return EOK; +} diff --git a/Ubiquitous/XiZi/resources/timer/Makefile b/Ubiquitous/XiZi/resources/timer/Makefile new file mode 100644 index 0000000..df8d3aa --- /dev/null +++ b/Ubiquitous/XiZi/resources/timer/Makefile @@ -0,0 +1,3 @@ +SRC_FILES := bus_hwtimer.c dev_hwtimer.c drv_hwtimer.c + +include $(KERNEL_ROOT)/compiler.mk diff --git a/Ubiquitous/XiZi/resources/timer/bus_hwtimer.c b/Ubiquitous/XiZi/resources/timer/bus_hwtimer.c new file mode 100644 index 0000000..c3ec117 --- /dev/null +++ b/Ubiquitous/XiZi/resources/timer/bus_hwtimer.c @@ -0,0 +1,117 @@ +/* +* Copyright (c) 2020 AIIT XUOS Lab +* XiUOS is licensed under Mulan PSL v2. +* You can use this software according to the terms and conditions of the Mulan PSL v2. +* You may obtain a copy of Mulan PSL v2 at: +* http://license.coscl.org.cn/MulanPSL2 +* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, +* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, +* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. +* See the Mulan PSL v2 for more details. +*/ + +/** +* @file bus_hwtimer.c +* @brief register hwtimer bus function using bus driver framework +* @version 1.0 +* @author AIIT XUOS Lab +* @date 2021-04-24 +*/ + +#include +#include + +int HwtimerBusInit(struct HwtimerBus *hwtimer_bus, const char *bus_name) +{ + NULL_PARAM_CHECK(hwtimer_bus); + NULL_PARAM_CHECK(bus_name); + + x_err_t ret = EOK; + + if (BUS_INSTALL != hwtimer_bus->bus.bus_state) { + strncpy(hwtimer_bus->bus.bus_name, bus_name, NAME_NUM_MAX); + + hwtimer_bus->bus.bus_type = TYPE_HWTIMER_BUS; + hwtimer_bus->bus.bus_state = BUS_INSTALL; + hwtimer_bus->bus.private_data = hwtimer_bus->private_data; + + ret = BusRegister(&hwtimer_bus->bus); + if (EOK != ret) { + KPrintf("HwtimerBusInit BusRegister error %u\n", ret); + return ret; + } + } else { + KPrintf("HwtimerBusInit BusRegister bus has been register state%u\n", hwtimer_bus->bus.bus_state); + } + + return ret; +} + +int HwtimerDriverInit(struct HwtimerDriver *hwtimer_driver, const char *driver_name) +{ + NULL_PARAM_CHECK(hwtimer_driver); + NULL_PARAM_CHECK(driver_name); + + x_err_t ret = EOK; + + if (DRV_INSTALL != hwtimer_driver->driver.driver_state) { + hwtimer_driver->driver.driver_type = TYPE_HWTIMER_DRV; + hwtimer_driver->driver.driver_state = DRV_INSTALL; + + strncpy(hwtimer_driver->driver.drv_name, driver_name, NAME_NUM_MAX); + + hwtimer_driver->driver.configure = hwtimer_driver->configure; + + ret = HwtimerDriverRegister(&hwtimer_driver->driver); + if (EOK != ret) { + KPrintf("HwtimerDriverInit DriverRegister error %u\n", ret); + return ret; + } + } else { + KPrintf("HwtimerDriverInit DriverRegister driver has been register state%u\n", hwtimer_driver->driver.driver_state); + } + + return ret; +} + +int HwtimerReleaseBus(struct HwtimerBus *hwtimer_bus) +{ + NULL_PARAM_CHECK(hwtimer_bus); + + return BusRelease(&hwtimer_bus->bus); +} + +int HwtimerDriverAttachToBus(const char *drv_name, const char *bus_name) +{ + NULL_PARAM_CHECK(drv_name); + NULL_PARAM_CHECK(bus_name); + + x_err_t ret = EOK; + + struct Bus *bus; + struct Driver *driver; + + bus = BusFind(bus_name); + if (NONE == bus) { + KPrintf("HwtimerDriverAttachToBus find hwtimer bus error!name %s\n", bus_name); + return ERROR; + } + + if (TYPE_HWTIMER_BUS == bus->bus_type) { + driver = HwtimerDriverFind(drv_name); + if (NONE == driver) { + KPrintf("HwtimerDriverAttachToBus find hwtimer driver error!name %s\n", drv_name); + return ERROR; + } + + if (TYPE_HWTIMER_DRV == driver->driver_type) { + ret = DriverRegisterToBus(bus, driver); + if (EOK != ret) { + KPrintf("HwtimerDriverAttachToBus DriverRegisterToBus error %u\n", ret); + return ERROR; + } + } + } + + return ret; +} diff --git a/Ubiquitous/XiZi/resources/timer/dev_hwtimer.c b/Ubiquitous/XiZi/resources/timer/dev_hwtimer.c new file mode 100644 index 0000000..5a9b530 --- /dev/null +++ b/Ubiquitous/XiZi/resources/timer/dev_hwtimer.c @@ -0,0 +1,115 @@ +/* +* Copyright (c) 2020 AIIT XUOS Lab +* XiUOS is licensed under Mulan PSL v2. +* You can use this software according to the terms and conditions of the Mulan PSL v2. +* You may obtain a copy of Mulan PSL v2 at: +* http://license.coscl.org.cn/MulanPSL2 +* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, +* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, +* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. +* See the Mulan PSL v2 for more details. +*/ + +/** +* @file dev_hwtimer.c +* @brief register hwtimer dev function using bus driver framework +* @version 1.0 +* @author AIIT XUOS Lab +* @date 2021-04-24 +*/ + +#include +#include + +static DoubleLinklistType hwtimerdev_linklist; + +/*Create the hwtimer device linklist*/ +static void HwtimerDeviceLinkInit() +{ + InitDoubleLinkList(&hwtimerdev_linklist); +} + +HardwareDevType HwtimerDeviceFind(const char *dev_name) +{ + NULL_PARAM_CHECK(dev_name); + + struct HardwareDev *device = NONE; + + DoubleLinklistType *node = NONE; + DoubleLinklistType *head = &hwtimerdev_linklist; + + for (node = head->node_next; node != head; node = node->node_next) { + device = SYS_DOUBLE_LINKLIST_ENTRY(node, struct HardwareDev, dev_link); + if (!strcmp(device->dev_name, dev_name)) { + return device; + } + } + + KPrintf("HwtimerDeviceFind cannot find the %s device.return NULL\n", dev_name); + return NONE; +} + +int HwtimerDeviceRegister(struct HwtimerHardwareDevice *hwtimer_device, void *hwtimer_param, const char *device_name) +{ + NULL_PARAM_CHECK(hwtimer_device); + NULL_PARAM_CHECK(device_name); + + x_err_t ret = EOK; + static x_bool dev_link_flag = RET_FALSE; + + if (!dev_link_flag) { + HwtimerDeviceLinkInit(); + dev_link_flag = RET_TRUE; + } + + if (DEV_INSTALL != hwtimer_device->haldev.dev_state) { + strncpy(hwtimer_device->haldev.dev_name, device_name, NAME_NUM_MAX); + hwtimer_device->haldev.dev_type = TYPE_HWTIMER_DEV; + hwtimer_device->haldev.dev_state = DEV_INSTALL; + + hwtimer_device->haldev.dev_done = (struct HalDevDone *)hwtimer_device->dev_done; + + hwtimer_device->haldev.private_data = hwtimer_param; + + DoubleLinkListInsertNodeAfter(&hwtimerdev_linklist, &(hwtimer_device->haldev.dev_link)); + } else { + KPrintf("HwtimerDeviceRegister device has been register state%u\n", hwtimer_device->haldev.dev_state); + } + + return ret; +} + +int HwtimerDeviceAttachToBus(const char *dev_name, const char *bus_name) +{ + NULL_PARAM_CHECK(dev_name); + NULL_PARAM_CHECK(bus_name); + + x_err_t ret = EOK; + + struct Bus *bus; + struct HardwareDev *device; + + bus = BusFind(bus_name); + if (NONE == bus) { + KPrintf("HwtimerDeviceAttachToBus find hwtimer bus error!name %s\n", bus_name); + return ERROR; + } + + if (TYPE_HWTIMER_BUS == bus->bus_type) { + device = HwtimerDeviceFind(dev_name); + if (NONE == device) { + KPrintf("HwtimerDeviceAttachToBus find hwtimer device error!name %s\n", dev_name); + return ERROR; + } + + if (TYPE_HWTIMER_DEV == device->dev_type) { + ret = DeviceRegisterToBus(bus, device); + if (EOK != ret) { + KPrintf("HwtimerDeviceAttachToBus DeviceRegisterToBus error %u\n", ret); + return ERROR; + } + } + } + + return EOK; +} diff --git a/Ubiquitous/XiZi/resources/timer/drv_hwtimer.c b/Ubiquitous/XiZi/resources/timer/drv_hwtimer.c new file mode 100644 index 0000000..df38e39 --- /dev/null +++ b/Ubiquitous/XiZi/resources/timer/drv_hwtimer.c @@ -0,0 +1,67 @@ +/* +* Copyright (c) 2020 AIIT XUOS Lab +* XiUOS is licensed under Mulan PSL v2. +* You can use this software according to the terms and conditions of the Mulan PSL v2. +* You may obtain a copy of Mulan PSL v2 at: +* http://license.coscl.org.cn/MulanPSL2 +* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, +* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, +* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. +* See the Mulan PSL v2 for more details. +*/ + +/** +* @file drv_hwtimer.c +* @brief register hwtimer drv function using bus driver framework +* @version 1.0 +* @author AIIT XUOS Lab +* @date 2021-04-24 +*/ + +#include +#include + +static DoubleLinklistType hwtimerdrv_linklist; + +/*Create the driver linklist*/ +static void HwtimerDrvLinkInit() +{ + InitDoubleLinkList(&hwtimerdrv_linklist); +} + +DriverType HwtimerDriverFind(const char *drv_name) +{ + NULL_PARAM_CHECK(drv_name); + + struct Driver *driver = NONE; + + DoubleLinklistType *node = NONE; + DoubleLinklistType *head = &hwtimerdrv_linklist; + + for (node = head->node_next; node != head; node = node->node_next) { + driver = SYS_DOUBLE_LINKLIST_ENTRY(node, struct Driver, driver_link); + if (!strcmp(driver->drv_name, drv_name)) { + return driver; + } + } + + KPrintf("HwtimerDriverFind cannot find the %s driver.return NULL\n", drv_name); + return NONE; +} + +int HwtimerDriverRegister(struct Driver *driver) +{ + NULL_PARAM_CHECK(driver); + + x_err_t ret = EOK; + static x_bool driver_link_flag = RET_FALSE; + + if (!driver_link_flag) { + HwtimerDrvLinkInit(); + driver_link_flag = RET_TRUE; + } + + DoubleLinkListInsertNodeAfter(&hwtimerdrv_linklist, &(driver->driver_link)); + + return ret; +} diff --git a/Ubiquitous/XiZi/resources/touch/Makefile b/Ubiquitous/XiZi/resources/touch/Makefile new file mode 100644 index 0000000..7af595e --- /dev/null +++ b/Ubiquitous/XiZi/resources/touch/Makefile @@ -0,0 +1,5 @@ +SRC_FILES += drv_touch.c dev_touch.c bus_touch.c + + + +include $(KERNEL_ROOT)/compiler.mk diff --git a/Ubiquitous/XiZi/resources/touch/bus_touch.c b/Ubiquitous/XiZi/resources/touch/bus_touch.c new file mode 100644 index 0000000..ad178a5 --- /dev/null +++ b/Ubiquitous/XiZi/resources/touch/bus_touch.c @@ -0,0 +1,117 @@ +/* +* Copyright (c) 2020 AIIT XUOS Lab +* XiUOS is licensed under Mulan PSL v2. +* You can use this software according to the terms and conditions of the Mulan PSL v2. +* You may obtain a copy of Mulan PSL v2 at: +* http://license.coscl.org.cn/MulanPSL2 +* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, +* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, +* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. +* See the Mulan PSL v2 for more details. +*/ + +/** +* @file bus_touch.c +* @brief register touch bus function using bus driver framework +* @version 1.0 +* @author AIIT XUOS Lab +* @date 2021-04-24 +*/ + +#include +#include + +int TouchBusInit(struct TouchBus *touch_bus, const char *bus_name) +{ + NULL_PARAM_CHECK(touch_bus); + NULL_PARAM_CHECK(bus_name); + + x_err_t ret = EOK; + + if (BUS_INSTALL != touch_bus->bus.bus_state) { + strncpy(touch_bus->bus.bus_name, bus_name, NAME_NUM_MAX); + + touch_bus->bus.bus_type = TYPE_TOUCH_BUS; + touch_bus->bus.bus_state = BUS_INSTALL; + touch_bus->bus.private_data = touch_bus->private_data; + + ret = BusRegister(&touch_bus->bus); + if (EOK != ret) { + KPrintf("touchBusInit BusRegister error %u\n", ret); + return ret; + } + } else { + KPrintf("touchBusInit BusRegister bus has been register state%u\n", touch_bus->bus.bus_state); + } + + return ret; +} + +int TouchDriverInit(struct TouchDriver *touch_driver, const char *driver_name) +{ + NULL_PARAM_CHECK(touch_driver); + NULL_PARAM_CHECK(driver_name); + + x_err_t ret = EOK; + + if (DRV_INSTALL != touch_driver->driver.driver_state) { + touch_driver->driver.driver_type = TYPE_TOUCH_DRV; + touch_driver->driver.driver_state = DRV_INSTALL; + + strncpy(touch_driver->driver.drv_name, driver_name, NAME_NUM_MAX); + + touch_driver->driver.configure =touch_driver->configure; + + ret = TouchDriverRegister(&touch_driver->driver); + if (EOK != ret) { + KPrintf("TouchDriverInit DriverRegister error %u\n", ret); + return ret; + } + } else { + KPrintf("TouchDriverInit DriverRegister driver has been register state%u\n", touch_driver->driver.driver_state); + } + + return ret; +} + +int TouchReleaseBus(struct TouchBus *touch_bus) +{ + NULL_PARAM_CHECK(touch_bus); + + return BusRelease(&touch_bus->bus); +} + +int TouchDriverAttachToBus(const char *drv_name, const char *bus_name) +{ + NULL_PARAM_CHECK(drv_name); + NULL_PARAM_CHECK(bus_name); + + x_err_t ret = EOK; + + struct Bus *bus; + struct Driver *driver; + + bus = BusFind(bus_name); + if (NONE == bus) { + KPrintf("TouchDriverAttachToBus find touch bus error!name %s\n", bus_name); + return ERROR; + } + + if (TYPE_TOUCH_BUS == bus->bus_type) { + driver = TouchDriverFind(drv_name, TYPE_TOUCH_DRV); + if (NONE == driver) { + KPrintf("TouchDriverAttachToBus find touch driver error!name %s\n", drv_name); + return ERROR; + } + + if (TYPE_TOUCH_DRV == driver->driver_type) { + ret = DriverRegisterToBus(bus, driver); + if (EOK != ret) { + KPrintf("TouchDriverAttachToBus DriverRegisterToBus error %u\n", ret); + return ERROR; + } + } + } + + return ret; +} diff --git a/Ubiquitous/XiZi/resources/touch/dev_touch.c b/Ubiquitous/XiZi/resources/touch/dev_touch.c new file mode 100644 index 0000000..71a7869 --- /dev/null +++ b/Ubiquitous/XiZi/resources/touch/dev_touch.c @@ -0,0 +1,116 @@ +/* +* Copyright (c) 2020 AIIT XUOS Lab +* XiUOS is licensed under Mulan PSL v2. +* You can use this software according to the terms and conditions of the Mulan PSL v2. +* You may obtain a copy of Mulan PSL v2 at: +* http://license.coscl.org.cn/MulanPSL2 +* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, +* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, +* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. +* See the Mulan PSL v2 for more details. +*/ + +/** +* @file dev_touch.c +* @brief register touch dev function using bus driver framework +* @version 1.0 +* @author AIIT XUOS Lab +* @date 2021-04-24 +*/ + +#include +#include + +static DoubleLinklistType touchdev_linklist; + +/*Create the touch device linklist*/ +static void TouchDeviceLinkInit() +{ + InitDoubleLinkList(&touchdev_linklist); +} + +HardwareDevType TouchDeviceFind(const char *dev_name, enum DevType dev_type) +{ + NULL_PARAM_CHECK(dev_name); + + struct HardwareDev *device = NONE; + + DoubleLinklistType *node = NONE; + DoubleLinklistType *head = &touchdev_linklist; + + for (node = head->node_next; node != head; node = node->node_next){ + device = SYS_DOUBLE_LINKLIST_ENTRY(node, struct HardwareDev, dev_link); + if ((!strcmp(device->dev_name, dev_name)) && (dev_type == device->dev_type)) { + return device; + } + } + + KPrintf("TouchDeviceFind cannot find the %s device.return NULL\n", dev_name); + return NONE; +} + +int TouchDeviceRegister(struct TouchHardwareDevice *touch_device, void *touch_param, const char *device_name) +{ + NULL_PARAM_CHECK(touch_device); + NULL_PARAM_CHECK(device_name); + + x_err_t ret = EOK; + + static x_bool dev_link_flag = RET_FALSE; + + if (!dev_link_flag) { + TouchDeviceLinkInit(); + dev_link_flag = RET_TRUE; + } + + if (DEV_INSTALL != touch_device->haldev.dev_state) { + strncpy(touch_device->haldev.dev_name, device_name, NAME_NUM_MAX); + touch_device->haldev.dev_type = TYPE_TOUCH_DEV; + touch_device->haldev.dev_state = DEV_INSTALL; + + touch_device->haldev.dev_done = (struct HalDevDone *)touch_device->dev_done; + + touch_device->haldev.private_data = touch_param; + + DoubleLinkListInsertNodeAfter(&touchdev_linklist, &(touch_device->haldev.dev_link)); + } else { + KPrintf("TouchDeviceRegister device has been register state%u\n", touch_device->haldev.dev_state); + } + + return ret; +} + +int TouchDeviceAttachToBus(const char *dev_name, const char *bus_name) +{ + NULL_PARAM_CHECK(dev_name); + NULL_PARAM_CHECK(bus_name); + + x_err_t ret = EOK; + + struct Bus *bus; + struct HardwareDev *device; + + bus = BusFind(bus_name); + if (NONE == bus) { + KPrintf("TouchDeviceAttachToBus find touch bus error!name %s\n", bus_name); + return ERROR; + } + + if (TYPE_TOUCH_BUS == bus->bus_type) { + device = TouchDeviceFind(dev_name, TYPE_TOUCH_DEV); + if (NONE == device) { + KPrintf("TouchDeviceAttachToBus find TOUCH device error!name %s\n", dev_name); + return ERROR; + } + + if (TYPE_TOUCH_DEV == device->dev_type) { + ret = DeviceRegisterToBus(bus, device); + if (EOK != ret) { + KPrintf("TouchDeviceAttachToBus DeviceRegisterToBus error %u\n", ret); + return ERROR; + } + } + } + + return EOK; +} diff --git a/Ubiquitous/XiZi/resources/touch/drv_touch.c b/Ubiquitous/XiZi/resources/touch/drv_touch.c new file mode 100644 index 0000000..e2d1078 --- /dev/null +++ b/Ubiquitous/XiZi/resources/touch/drv_touch.c @@ -0,0 +1,67 @@ +/* +* Copyright (c) 2020 AIIT XUOS Lab +* XiUOS is licensed under Mulan PSL v2. +* You can use this software according to the terms and conditions of the Mulan PSL v2. +* You may obtain a copy of Mulan PSL v2 at: +* http://license.coscl.org.cn/MulanPSL2 +* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, +* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, +* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. +* See the Mulan PSL v2 for more details. +*/ + +/** +* @file drv_touch.c +* @brief register touch drv function using bus driver framework +* @version 1.0 +* @author AIIT XUOS Lab +* @date 2021-04-24 +*/ + +#include +#include + +static DoubleLinklistType touchdrv_linklist; + +/*Create the driver linklist*/ +static void TouchDrvLinkInit() +{ + InitDoubleLinkList(&touchdrv_linklist); +} + +DriverType TouchDriverFind(const char *drv_name, enum DriverType_e drv_type) +{ + NULL_PARAM_CHECK(drv_name); + + struct Driver *driver = NONE; + + DoubleLinklistType *node = NONE; + DoubleLinklistType *head = &touchdrv_linklist; + + for (node = head->node_next; node != head; node = node->node_next) { + driver = SYS_DOUBLE_LINKLIST_ENTRY(node, struct Driver, driver_link); + if ((!strcmp(driver->drv_name, drv_name)) && (drv_type == driver->driver_type)) { + return driver; + } + } + + KPrintf("TouchDriverFind cannot find the %s driver.return NULL\n", drv_name); + return NONE; +} + +int TouchDriverRegister(struct Driver *driver) +{ + NULL_PARAM_CHECK(driver); + + x_err_t ret = EOK; + static x_bool driver_link_flag = RET_FALSE; + + if (!driver_link_flag) { + TouchDrvLinkInit(); + driver_link_flag = RET_TRUE; + } + + DoubleLinkListInsertNodeAfter(&touchdrv_linklist, &(driver->driver_link)); + + return ret; +} diff --git a/Ubiquitous/XiZi/resources/usb/Makefile b/Ubiquitous/XiZi/resources/usb/Makefile new file mode 100644 index 0000000..b7bea24 --- /dev/null +++ b/Ubiquitous/XiZi/resources/usb/Makefile @@ -0,0 +1,4 @@ +SRC_DIR := third_party_usb +SRC_FILES += dev_usb.c drv_usb.c bus_usb.c + +include $(KERNEL_ROOT)/compiler.mk diff --git a/Ubiquitous/XiZi/resources/usb/bus_usb.c b/Ubiquitous/XiZi/resources/usb/bus_usb.c new file mode 100644 index 0000000..9702ec1 --- /dev/null +++ b/Ubiquitous/XiZi/resources/usb/bus_usb.c @@ -0,0 +1,125 @@ +/* +* Copyright (c) 2020 AIIT XUOS Lab +* XiUOS is licensed under Mulan PSL v2. +* You can use this software according to the terms and conditions of the Mulan PSL v2. +* You may obtain a copy of Mulan PSL v2 at: +* http://license.coscl.org.cn/MulanPSL2 +* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, +* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, +* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. +* See the Mulan PSL v2 for more details. +*/ + +/** +* @file bus_usb.c +* @brief register usb bus function using bus driver framework +* @version 1.0 +* @author AIIT XUOS Lab +* @date 2021-04-24 +*/ + +#include +#include + +/*Register the USB BUS*/ +int UsbBusInit(struct UsbBus *usb_bus, const char *bus_name) +{ + NULL_PARAM_CHECK(usb_bus); + NULL_PARAM_CHECK(bus_name); + + x_err_t ret = EOK; + + if (BUS_INSTALL != usb_bus->bus.bus_state) { + strncpy(usb_bus->bus.bus_name, bus_name, NAME_NUM_MAX); + + usb_bus->bus.bus_type = TYPE_USB_BUS; + usb_bus->bus.bus_state = BUS_INSTALL; + usb_bus->bus.private_data = usb_bus->private_data; + + ret = BusRegister(&usb_bus->bus); + if (EOK != ret) { + KPrintf("UsbBusInit BusRegister error %u\n", ret); + return ret; + } + } else { + KPrintf("UsbBusInit BusRegister bus has been register state%u\n", usb_bus->bus.bus_state); + } + + return ret; +} + +/*Register the USB Driver*/ +int UsbDriverInit(struct UsbDriver *usb_driver, const char *driver_name) +{ + NULL_PARAM_CHECK(usb_driver); + NULL_PARAM_CHECK(driver_name); + + x_err_t ret = EOK; + + if (DRV_INSTALL != usb_driver->driver.driver_state) { + usb_driver->driver.driver_type = TYPE_USB_DRV; + usb_driver->driver.driver_state = DRV_INSTALL; + + strncpy(usb_driver->driver.drv_name, driver_name, NAME_NUM_MAX); + + usb_driver->driver.configure = usb_driver->configure; + + usb_driver->driver.private_data = usb_driver->private_data; + + ret = UsbDriverRegister(&usb_driver->driver); + if (EOK != ret) { + KPrintf("UsbDriverInit DriverRegister error %u\n", ret); + return ret; + } + } else { + KPrintf("UsbDriverInit DriverRegister driver has been register state%u\n", usb_driver->driver.driver_state); + } + + return ret; +} + +/*Release the USB device*/ +int UsbReleaseBus(struct UsbBus *usb_bus) +{ + NULL_PARAM_CHECK(usb_bus); + + return BusRelease(&usb_bus->bus); +} + +/*Register the USB Driver to the USB BUS*/ +int UsbDriverAttachToBus(const char *drv_name, const char *bus_name) +{ + NULL_PARAM_CHECK(drv_name); + NULL_PARAM_CHECK(bus_name); + + x_err_t ret = EOK; + + struct Bus *bus; + struct Driver *driver; + + bus = BusFind(bus_name); + if (NONE == bus) { + KPrintf("UsbDriverAttachToBus find usb bus error!name %s\n", bus_name); + return ERROR; + } + + if (TYPE_USB_BUS == bus->bus_type) { + driver = UsbDriverFind(drv_name, TYPE_USB_DRV); + if (NONE == driver) { + KPrintf("UsbDriverAttachToBus find usb driver error!name %s\n", drv_name); + return ERROR; + } + + if (TYPE_USB_DRV == driver->driver_type) { + ret = DriverRegisterToBus(bus, driver); + if (EOK != ret) { + KPrintf("UsbDriverAttachToBus DriverRegisterToBus error %u\n", ret); + return ERROR; + } + } + } + + return ret; +} + + diff --git a/Ubiquitous/XiZi/resources/usb/dev_usb.c b/Ubiquitous/XiZi/resources/usb/dev_usb.c new file mode 100644 index 0000000..baa6dda --- /dev/null +++ b/Ubiquitous/XiZi/resources/usb/dev_usb.c @@ -0,0 +1,118 @@ +/* +* Copyright (c) 2020 AIIT XUOS Lab +* XiUOS is licensed under Mulan PSL v2. +* You can use this software according to the terms and conditions of the Mulan PSL v2. +* You may obtain a copy of Mulan PSL v2 at: +* http://license.coscl.org.cn/MulanPSL2 +* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, +* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, +* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. +* See the Mulan PSL v2 for more details. +*/ + +/** +* @file dev_usb.c +* @brief register usb dev function using bus driver framework +* @version 1.0 +* @author AIIT XUOS Lab +* @date 2021-04-24 +*/ + +#include +#include + +static DoubleLinklistType usbdev_linklist; + +/*Create the usb device linklist*/ +static void USBDeviceLinkInit() +{ + InitDoubleLinkList(&usbdev_linklist); +} + +/*Find the register USB device*/ +HardwareDevType USBDeviceFind(const char *dev_name, enum DevType dev_type) +{ + NULL_PARAM_CHECK(dev_name); + + struct HardwareDev *device = NONE; + + DoubleLinklistType *node = NONE; + DoubleLinklistType *head = &usbdev_linklist; + + for (node = head->node_next; node != head; node = node->node_next) { + device = SYS_DOUBLE_LINKLIST_ENTRY(node, struct HardwareDev, dev_link); + if ((!strcmp(device->dev_name, dev_name)) && (dev_type == device->dev_type)) { + return device; + } + } + + KPrintf("USBDeviceFind cannot find the %s device.return NULL\n", dev_name); + return NONE; +} + +/*Register the USB device*/ +int USBDeviceRegister(struct UsbHardwareDevice *usb_device, void *usb_param, const char *device_name) +{ + NULL_PARAM_CHECK(usb_device); + NULL_PARAM_CHECK(device_name); + + x_err_t ret = EOK; + static x_bool dev_link_flag = RET_FALSE; + + if (!dev_link_flag) { + USBDeviceLinkInit(); + dev_link_flag = RET_TRUE; + } + + if (DEV_INSTALL != usb_device->haldev.dev_state) { + strncpy(usb_device->haldev.dev_name, device_name, NAME_NUM_MAX); + usb_device->haldev.dev_type = TYPE_USB_DEV; + usb_device->haldev.dev_state = DEV_INSTALL; + + usb_device->haldev.dev_done = (struct HalDevDone *)usb_device->dev_done; + + usb_device->haldev.private_data = usb_param; + + DoubleLinkListInsertNodeAfter(&usbdev_linklist, &(usb_device->haldev.dev_link)); + } else { + KPrintf("USBDeviceRegister device has been register state%u\n", usb_device->haldev.dev_state); + } + + return ret; +} + +/*Register the USB Device to the USB BUS*/ +int USBDeviceAttachToBus(const char *dev_name, const char *bus_name) +{ + NULL_PARAM_CHECK(dev_name); + NULL_PARAM_CHECK(bus_name); + + x_err_t ret = EOK; + + struct Bus *bus; + struct HardwareDev *device; + + bus = BusFind(bus_name); + if (NONE == bus) { + KPrintf("USBDeviceAttachToBus find usb bus error!name %s\n", bus_name); + return ERROR; + } + + if (TYPE_USB_BUS == bus->bus_type) { + device = USBDeviceFind(dev_name, TYPE_USB_DEV); + if (NONE == device) { + KPrintf("USBDeviceAttachToBus find usb device error!name %s\n", dev_name); + return ERROR; + } + + if (TYPE_USB_DEV == device->dev_type) { + ret = DeviceRegisterToBus(bus, device); + if (EOK != ret) { + KPrintf("usbDeviceAttachToBus DeviceRegisterToBus error %u\n", ret); + return ERROR; + } + } + } + + return EOK; +} diff --git a/Ubiquitous/XiZi/resources/usb/drv_usb.c b/Ubiquitous/XiZi/resources/usb/drv_usb.c new file mode 100644 index 0000000..28095b4 --- /dev/null +++ b/Ubiquitous/XiZi/resources/usb/drv_usb.c @@ -0,0 +1,69 @@ +/* +* Copyright (c) 2020 AIIT XUOS Lab +* XiUOS is licensed under Mulan PSL v2. +* You can use this software according to the terms and conditions of the Mulan PSL v2. +* You may obtain a copy of Mulan PSL v2 at: +* http://license.coscl.org.cn/MulanPSL2 +* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, +* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, +* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. +* See the Mulan PSL v2 for more details. +*/ + +/** +* @file drv_usb.c +* @brief register usb drv function using bus driver framework +* @version 1.0 +* @author AIIT XUOS Lab +* @date 2021-04-24 +*/ + +#include +#include + +static DoubleLinklistType usbdrv_linklist; + +/*Create the driver linklist*/ +static void UsbDrvLinkInit() +{ + InitDoubleLinkList(&usbdrv_linklist); +} + +/*Find the regiter driver*/ +DriverType UsbDriverFind(const char *drv_name, enum DriverType_e drv_type) +{ + NULL_PARAM_CHECK(drv_name); + + struct Driver *driver = NONE; + + DoubleLinklistType *node = NONE; + DoubleLinklistType *head = &usbdrv_linklist; + + for (node = head->node_next; node != head; node = node->node_next) { + driver = SYS_DOUBLE_LINKLIST_ENTRY(node, struct Driver, driver_link); + if ((!strcmp(driver->drv_name, drv_name)) && (drv_type == driver->driver_type)) { + return driver; + } + } + + KPrintf("UsbDriverFind cannot find the %s driver.return NULL\n", drv_name); + return NONE; +} + +/*Register the Driver, manage with the double linklist*/ +int UsbDriverRegister(struct Driver *driver) +{ + NULL_PARAM_CHECK(driver); + + x_err_t ret = EOK; + static x_bool driver_link_flag = RET_FALSE; + + if (!driver_link_flag) { + UsbDrvLinkInit(); + driver_link_flag = RET_TRUE; + } + + DoubleLinkListInsertNodeAfter(&usbdrv_linklist, &(driver->driver_link)); + + return ret; +} diff --git a/Ubiquitous/XiZi/resources/watchdog/Makefile b/Ubiquitous/XiZi/resources/watchdog/Makefile new file mode 100644 index 0000000..c75e078 --- /dev/null +++ b/Ubiquitous/XiZi/resources/watchdog/Makefile @@ -0,0 +1,5 @@ +SRC_FILES +=bus_wdt.c dev_wdt.c drv_wdt.c + + + +include $(KERNEL_ROOT)/compiler.mk diff --git a/Ubiquitous/XiZi/resources/watchdog/bus_wdt.c b/Ubiquitous/XiZi/resources/watchdog/bus_wdt.c new file mode 100644 index 0000000..48b53b3 --- /dev/null +++ b/Ubiquitous/XiZi/resources/watchdog/bus_wdt.c @@ -0,0 +1,117 @@ +/* +* Copyright (c) 2020 AIIT XUOS Lab +* XiUOS is licensed under Mulan PSL v2. +* You can use this software according to the terms and conditions of the Mulan PSL v2. +* You may obtain a copy of Mulan PSL v2 at: +* http://license.coscl.org.cn/MulanPSL2 +* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, +* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, +* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. +* See the Mulan PSL v2 for more details. +*/ + +/** +* @file bus_wdt.c +* @brief register wdt bus function using bus driver framework +* @version 1.0 +* @author AIIT XUOS Lab +* @date 2021-04-24 +*/ + +#include +#include + +int WdtBusInit(struct WdtBus *wdt_bus, const char *bus_name) +{ + NULL_PARAM_CHECK(wdt_bus); + NULL_PARAM_CHECK(bus_name); + + x_err_t ret = EOK; + + if (BUS_INSTALL != wdt_bus->bus.bus_state) { + strncpy(wdt_bus->bus.bus_name, bus_name, NAME_NUM_MAX); + + wdt_bus->bus.bus_type = TYPE_WDT_BUS; + wdt_bus->bus.bus_state = BUS_INSTALL; + wdt_bus->bus.private_data = wdt_bus->private_data; + + ret = BusRegister(&wdt_bus->bus); + if (EOK != ret) { + KPrintf("WdtBusInit BusRegister error %u\n", ret); + return ret; + } + } else { + KPrintf("WdtBusInit BusRegister bus has been register state%u\n", wdt_bus->bus.bus_state); + } + + return ret; +} + +int WdtDriverInit(struct WdtDriver *wdt_driver, const char *driver_name) +{ + NULL_PARAM_CHECK(wdt_driver); + NULL_PARAM_CHECK(driver_name); + + x_err_t ret = EOK; + + if (DRV_INSTALL != wdt_driver->driver.driver_state) { + wdt_driver->driver.driver_type = TYPE_WDT_DRV; + wdt_driver->driver.driver_state = DRV_INSTALL; + + strncpy(wdt_driver->driver.drv_name, driver_name, NAME_NUM_MAX); + + wdt_driver->driver.configure = wdt_driver->configure; + + ret = WdtDriverRegister(&wdt_driver->driver); + if (EOK != ret) { + KPrintf("WdtDriverInit DriverRegister error %u\n", ret); + return ret; + } + } else { + KPrintf("WdtDriverInit DriverRegister driver has been register state%u\n", wdt_driver->driver.driver_state); + } + + return ret; +} + +int WdtReleaseBus(struct WdtBus *wdt_bus) +{ + NULL_PARAM_CHECK(wdt_bus); + + return BusRelease(&wdt_bus->bus); +} + +int WdtDriverAttachToBus(const char *drv_name, const char *bus_name) +{ + NULL_PARAM_CHECK(drv_name); + NULL_PARAM_CHECK(bus_name); + + x_err_t ret = EOK; + + struct Bus *bus; + struct Driver *driver; + + bus = BusFind(bus_name); + if (NONE == bus) { + KPrintf("WdtDriverAttachToBus find watchdog bus error!name %s\n", bus_name); + return ERROR; + } + + if (TYPE_WDT_BUS == bus->bus_type) { + driver = WdtDriverFind(drv_name); + if (NONE == driver) { + KPrintf("WdtDriverAttachToBus find watchdog driver error!name %s\n", drv_name); + return ERROR; + } + + if (TYPE_WDT_DRV == driver->driver_type) { + ret = DriverRegisterToBus(bus, driver); + if (EOK != ret) { + KPrintf("WdtDriverAttachToBus DriverRegisterToBus error %u\n", ret); + return ERROR; + } + } + } + + return ret; +} diff --git a/Ubiquitous/XiZi/resources/watchdog/dev_wdt.c b/Ubiquitous/XiZi/resources/watchdog/dev_wdt.c new file mode 100644 index 0000000..7648f0a --- /dev/null +++ b/Ubiquitous/XiZi/resources/watchdog/dev_wdt.c @@ -0,0 +1,113 @@ +/* +* Copyright (c) 2020 AIIT XUOS Lab +* XiUOS is licensed under Mulan PSL v2. +* You can use this software according to the terms and conditions of the Mulan PSL v2. +* You may obtain a copy of Mulan PSL v2 at: +* http://license.coscl.org.cn/MulanPSL2 +* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, +* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, +* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. +* See the Mulan PSL v2 for more details. +*/ + +/** +* @file dev_wdt.c +* @brief register wdt dev function using bus driver framework +* @version 1.0 +* @author AIIT XUOS Lab +* @date 2021-04-24 +*/ + +#include +#include + +static DoubleLinklistType wdtdev_linklist; + +/*Create the wdt device linklist*/ +static void WdtDeviceLinkInit() +{ + InitDoubleLinkList(&wdtdev_linklist); +} + +HardwareDevType WdtDeviceFind(const char *dev_name) +{ + NULL_PARAM_CHECK(dev_name); + + struct HardwareDev *device = NONE; + + DoubleLinklistType *node = NONE; + DoubleLinklistType *head = &wdtdev_linklist; + + for (node = head->node_next; node != head; node = node->node_next) { + device = SYS_DOUBLE_LINKLIST_ENTRY(node, struct HardwareDev, dev_link); + if (!strcmp(device->dev_name, dev_name)) { + return device; + } + } + + KPrintf("WdtDeviceFind cannot find the %s device.return NULL\n", dev_name); + return NONE; +} + +int WdtDeviceRegister(struct WdtHardwareDevice *wdt_device, const char *device_name) +{ + NULL_PARAM_CHECK(wdt_device); + NULL_PARAM_CHECK(device_name); + + x_err_t ret = EOK; + static x_bool dev_link_flag = RET_FALSE; + + if (!dev_link_flag) { + WdtDeviceLinkInit(); + dev_link_flag = RET_TRUE; + } + + if (DEV_INSTALL != wdt_device->haldev.dev_state) { + strncpy(wdt_device->haldev.dev_name, device_name, NAME_NUM_MAX); + wdt_device->haldev.dev_type = TYPE_WDT_DEV; + wdt_device->haldev.dev_state = DEV_INSTALL; + + wdt_device->haldev.dev_done = (struct HalDevDone *)wdt_device->dev_done; + + DoubleLinkListInsertNodeAfter(&wdtdev_linklist, &(wdt_device->haldev.dev_link)); + } else { + KPrintf("WdtDeviceRegister device has been register state%u\n", wdt_device->haldev.dev_state); + } + + return ret; +} + +int WdtDeviceAttachToBus(const char *dev_name, const char *bus_name) +{ + NULL_PARAM_CHECK(dev_name); + NULL_PARAM_CHECK(bus_name); + + x_err_t ret = EOK; + + struct Bus *bus; + struct HardwareDev *device; + + bus = BusFind(bus_name); + if (NONE == bus) { + KPrintf("WdtDeviceAttachToBus find wdt bus error!name %s\n", bus_name); + return ERROR; + } + + if (TYPE_WDT_BUS == bus->bus_type) { + device = WdtDeviceFind(dev_name); + if (NONE == device) { + KPrintf("WdtDeviceAttachToBus find wdt device error!name %s\n", dev_name); + return ERROR; + } + + if (TYPE_WDT_DEV == device->dev_type) { + ret = DeviceRegisterToBus(bus, device); + if (EOK != ret) { + KPrintf("WdtDeviceAttachToBus DeviceRegisterToBus error %u\n", ret); + return ERROR; + } + } + } + + return EOK; +} diff --git a/Ubiquitous/XiZi/resources/watchdog/drv_wdt.c b/Ubiquitous/XiZi/resources/watchdog/drv_wdt.c new file mode 100644 index 0000000..5856883 --- /dev/null +++ b/Ubiquitous/XiZi/resources/watchdog/drv_wdt.c @@ -0,0 +1,67 @@ +/* +* Copyright (c) 2020 AIIT XUOS Lab +* XiUOS is licensed under Mulan PSL v2. +* You can use this software according to the terms and conditions of the Mulan PSL v2. +* You may obtain a copy of Mulan PSL v2 at: +* http://license.coscl.org.cn/MulanPSL2 +* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, +* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, +* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. +* See the Mulan PSL v2 for more details. +*/ + +/** +* @file drv_wdt.c +* @brief register wdt drv function using bus driver framework +* @version 1.0 +* @author AIIT XUOS Lab +* @date 2021-04-24 +*/ + +#include +#include + +static DoubleLinklistType wdtdrv_linklist; + +/*Create the driver linklist*/ +static void WdtDrvLinkInit() +{ + InitDoubleLinkList(&wdtdrv_linklist); +} + +DriverType WdtDriverFind(const char *drv_name) +{ + NULL_PARAM_CHECK(drv_name); + + struct Driver *driver = NONE; + + DoubleLinklistType *node = NONE; + DoubleLinklistType *head = &wdtdrv_linklist; + + for (node = head->node_next; node != head; node = node->node_next) { + driver = SYS_DOUBLE_LINKLIST_ENTRY(node, struct Driver, driver_link); + if (!strcmp(driver->drv_name, drv_name)) { + return driver; + } + } + + KPrintf("WdtDriverFind cannot find the %s driver.return NULL\n", drv_name); + return NONE; +} + +int WdtDriverRegister(struct Driver *driver) +{ + NULL_PARAM_CHECK(driver); + + x_err_t ret = EOK; + static x_bool driver_link_flag = RET_FALSE; + + if (!driver_link_flag) { + WdtDrvLinkInit(); + driver_link_flag = RET_TRUE; + } + + DoubleLinkListInsertNodeAfter(&wdtdrv_linklist, &(driver->driver_link)); + + return ret; +} diff --git a/Ubiquitous/XiZi/tool/Makefile b/Ubiquitous/XiZi/tool/Makefile new file mode 100644 index 0000000..998131f --- /dev/null +++ b/Ubiquitous/XiZi/tool/Makefile @@ -0,0 +1,7 @@ +SRC_DIR := + +ifeq ($(CONFIG_TOOL_SHELL),y) + SRC_DIR += shell +endif + +include $(KERNEL_ROOT)/compiler.mk diff --git a/Ubiquitous/XiZi/tool/hosttools/generate_kselector.py b/Ubiquitous/XiZi/tool/hosttools/generate_kselector.py new file mode 100755 index 0000000..8f74a12 --- /dev/null +++ b/Ubiquitous/XiZi/tool/hosttools/generate_kselector.py @@ -0,0 +1,73 @@ +#! /usr/bin/python3 + +import os + +ubiquitous_dir = os.environ.get('UBIQUITOUS_ROOT') +bsp_dir = os.environ.get('BSP_ROOT') +kernel_names = [] + +def get_kernel_names(): + for d in os.scandir(ubiquitous_dir): + if d.is_dir() and d.name!= "feature_yaml": + kernel_names.append(d.name) + +def generate_features(): + with open(f"{ubiquitous_dir}/Kselector_features","w") as f: + # f.write("") + pass + +def generate_params(): + with open(f"{ubiquitous_dir}/Kselector_params","w") as f: + # f.write("") + pass + +def generate(): + get_kernel_names() + generate_features() + generate_params() + + template = r""" +mainmenu "Ubiquitous Kernel Selector" + +config BSP_DIR + string + option env="BSP_ROOT" + default "." + +config KERNEL_DIR + string + option env="KERNEL_ROOT" + default "../.." + +config UBIQUITOUS_DIR + string + option env="UBIQUITOUS_ROOT" + default "../../.." + +source "$UBIQUITOUS_DIR/Kselector_features" + +source "$UBIQUITOUS_DIR/Kselector_params" + +config MANUALLY_SELECT + bool "Manually select a kernel" + default n +if MANUALLY_SELECT +menu "Required Kernel" +choice + prompt "Select OS Kernel" + default SELECT_XIUOS + + """ + + for kernel_name in kernel_names: + template += f"\tconfig SELECT_{kernel_name.upper()}\n" + template += f'\t\tbool "select {kernel_name}"\n' + + # the last `\n` is very important, otherwise, it cannot be recognized as valid Kconfig file + template += "endchoice\nendmenu\nendif\n" + + with open(f"{bsp_dir}/Kselector", "w") as f: + f.write(template) + +if __name__ == '__main__': + generate() \ No newline at end of file diff --git a/Ubiquitous/XiZi/tool/hosttools/kernel_selector.py b/Ubiquitous/XiZi/tool/hosttools/kernel_selector.py new file mode 100755 index 0000000..428ee99 --- /dev/null +++ b/Ubiquitous/XiZi/tool/hosttools/kernel_selector.py @@ -0,0 +1,159 @@ +#! /usr/bin/python3 +# this script builds a decision tree to select suitable kernels from developers' preferences +from __future__ import annotations +from typing import TypeVar, Generic, Tuple, Optional +import os +import yaml +try: + from yaml import CLoader as Loader +except ImportError: + from yaml import Loader + +ubiquitous_dir = os.environ.get('UBIQUITOUS_ROOT') +kernel_dir = os.environ.get('KERNEL_ROOT') + +YAMLS_PATH = f"{ubiquitous_dir}/feature_yaml/" +REQUIREMENT_PATH = f"{kernel_dir}/requirement.yaml" + +COMPONENT_KEY = "Feature" +PARAMETER_KEY = "Parameter" +MANUAL_KEY = "Kernel" + +# tree node for kernel features +V = TypeVar("V") +class TreeNode(Generic[V]): + def __init__(self, depth: int, name: str, value: V): + self.depth = depth + self.name = name + self.value = value + self.children = dict() + + def __repr__(self): + res = f"L{self.depth}: name {self.name} - value {self.value} - {len(self.children)} children\n" + for c in self.children: + # recursively build representation + res += self.children[c].__repr__() + return res + + def node_number(self): + if len(self.children) == 0: + return 1 + number = 1 + for c in self.children: + number += self.children[c].node_number() + return number + + +# this class should be constructed from the yaml file +class Kernel: + def __init__(self, name, feature_yaml: dict): + self.name = name + self.features_root: Optional[TreeNode[bool]] = None + self.parameters_root: Optional[TreeNode[int]] = None + self.extract_components(feature_yaml) + self.extract_parameters(feature_yaml) + + def __repr__(self): + return f"{self.name}\nFeature Tree:\n{self.features_root}Parameter Tree:\n{self.parameters_root}\n" + + def extract_components(self, feature_yaml: dict): + self.features_root = TreeNode(0, COMPONENT_KEY, True) + for k,v in feature_yaml[COMPONENT_KEY].items(): + node = TreeNode(1, k, v) + if k in feature_yaml: + self.build_sub_tree(2, node, feature_yaml) + self.features_root.children[k] = node + + def build_sub_tree(self, depth, node: TreeNode[bool], feature_yaml: dict): + if feature_yaml[node.name] is None: + return + for k,v in feature_yaml[node.name].items(): + child = TreeNode(depth, k, v) + if child.name in feature_yaml: + self.build_sub_tree(depth+1, child, feature_yaml) + node.children[k] = child + + def extract_parameters(self, feature_yaml: dict): + self.parameters_root = TreeNode(0, PARAMETER_KEY, 0) + for k,v in feature_yaml[PARAMETER_KEY].items(): + child = TreeNode(1, k, v) + self.parameters_root.children[k] = child + + def check(self, requirements_root, root) -> Tuple[bool, int]: + distance = 0 + q = list() + q.append((requirements_root, root)) + while len(q) > 0: + (r_node, s_node) = q.pop() + for c in r_node.children: + if c in s_node.children and self.compare(c, s_node.children[c].value, r_node.children[c].value): + q.append((r_node.children[c], s_node.children[c])) + distance += (r_node.children[c].value - s_node.children[c].value)**2 + else: + return False, distance + return True, distance + + def compare(self, name, v1, v2): + if name.endswith("GREATER_THAN"): + return v1 >= v2 + elif name.endswith("LESS_THAN"): + return v1 <= v2 + else: + return v1 == v2 + +# load the requirements from the yaml file +def load_required_features()->dict: + with open(REQUIREMENT_PATH, 'r') as f: + content = f.read() + feature_yaml = yaml.load(content, Loader=Loader) + print(feature_yaml) + return feature_yaml + +# load kernel yamls from ubiquitous directory and build Kernel class +def load_kernel_features()->list[Kernel]: + kernels = {} + for file_name in os.listdir(YAMLS_PATH): + kernel_name = file_name.rstrip(".yaml") + with open(os.path.join(YAMLS_PATH, file_name), 'r') as f: + content = f.read() + feature_yaml = yaml.load(content, Loader=Loader) + kernels[kernel_name] = Kernel(kernel_name, feature_yaml) + return kernels + +# recommend a suitable kernel according to the requirement +def select_kernel(requirement: dict, kernels: dict[Kernel]) -> str: + selected = None + selected_node_number = 0 + selected_distance = 0 + requirement = Kernel("requirement", requirement) + for name, kernel in kernels.items(): + # here should be a tree matching algorithm + # requirement trees (both features and parameters) + # should be subtrees of the recommended kernel + pass_features, _ = kernel.check(requirement.features_root, kernel.features_root) + pass_parameters, distance = kernel.check(requirement.parameters_root, kernel.parameters_root) + print(name, pass_features, pass_parameters, distance) + if pass_features and pass_parameters: + if selected is None: + selected = kernel + selected_node_number = kernel.features_root.node_number() + selected_node_number = distance + else: + node_number = kernel.features_root.node_number() + if selected_node_number > node_number or (selected_node_number == node_number and selected_distance > distance): + selected = kernel + selected_node_number = kernel.features_root.node_number() + selected_node_number = distance + if selected is None: + return "Cannot find suitable kernel" + else: + return selected.name + +if __name__ == "__main__": + requirement = load_required_features() + if MANUAL_KEY in requirement: + selected = list(requirement[MANUAL_KEY].keys())[0][7:] + else: + kernels = load_kernel_features() + selected = select_kernel(requirement, kernels) + print(f"Selected kernel is: {selected}") \ No newline at end of file diff --git a/Ubiquitous/XiZi/tool/hosttools/kernel_selector.sh b/Ubiquitous/XiZi/tool/hosttools/kernel_selector.sh new file mode 100755 index 0000000..eb8bd3d --- /dev/null +++ b/Ubiquitous/XiZi/tool/hosttools/kernel_selector.sh @@ -0,0 +1,73 @@ +#!/bin/bash +# use this script to read the `.feature file` generated from `kconfig-mconf `, which further parse Kfeature to build the menu +# this script will genearte a more structured yaml file, +# the json file would further be sent to a decision tree for kernel selection. + +VERSION=0.1.0 + +function generate_requirement_file() +{ + local SELECTOR_NAME=${1} + + # destination file using file descriptor 8 + exec 8>${2} + + echo -ne "version: ${VERSION}\n" >&8 + + EMPTY_LINE='true' + + while read LN + do + LINE=`echo $LN | sed 's/[ \t\r\n]*$//g'` + + if [ -z "$LINE" ]; then + continue + fi + + if [ '#' = ${LINE:0:1} ]; then + if [ ${#LINE} -eq 1 ]; then + # empty line + if $EMPTY_LINE; then + continue + fi + echo >&8 + EMPTY_LINE='true' + continue + fi + + if echo -ne "$LINE" | egrep '^# Required' >/dev/null 2>/dev/null; then + # the key in yaml + echo -ne "${LINE:11}:\n" >&8 + else + LINE=${LINE:1} + echo -ne "# ${LINE}\n" >&8 + fi + + EMPTY_LINE='false' + else + EMPTY_LINE='false' + + OLD_IFS="$IFS" + IFS='=' + REQUIREMENTS=($LINE) + IFS="$OLD_IFS" + + if [ ${#REQUIREMENTS[@]} -ge 2 ]; then + if echo -ne "$REQUIREMENTS[0]" | egrep '^CONFIG_' >/dev/null 2>/dev/null; then + REQUIREMENTS[0]="${REQUIREMENTS[0]:7}" + fi + + if [ "${REQUIREMENTS[1]}" = 'y' ]; then + echo -ne " ${REQUIREMENTS[0]}: true\n" >&8 + else + echo -ne " ${REQUIREMENTS[0]}: ${LINE#*=}\n" >&8 + fi + fi + fi + + done < $SELECTOR_NAME + + exec 8<&- +} + +generate_requirement_file $1 $BSP_ROOT/requirement.yaml diff --git a/Ubiquitous/XiZi/tool/hosttools/xsconfig.sh b/Ubiquitous/XiZi/tool/hosttools/xsconfig.sh new file mode 100755 index 0000000..b51a159 --- /dev/null +++ b/Ubiquitous/XiZi/tool/hosttools/xsconfig.sh @@ -0,0 +1,91 @@ +#!/bin/bash +# Tring to create rtcnofig.h from .config +HEADER_STR=XS_CONFIG_H__ + + +function is_pkg_special_config() +{ + echo -ne $1 | egrep '^PKG_|_PATH$|_VER$' >/dev/null 2>/dev/null +} + +function is_config() +{ + echo -ne $1 | egrep '^XS_' >/dev/null 2>/dev/null +} + +function make_config_h() +{ + local CONFIG_NAME=${1} + + # destination file using file descriptor 8 + exec 8>${2} + + echo -ne "#ifndef ${HEADER_STR}\n" >&8 + echo -ne "#define ${HEADER_STR}\n\n" >&8 + + EMPTY_LINE='true' + + while read LN + do + LINE=`echo $LN | sed 's/[ \t\r\n]*$//g'` + + if [ -z "$LINE" ]; then + continue + fi + + if [ '#' = ${LINE:0:1} ]; then + if [ ${#LINE} -eq 1 ]; then + if $EMPTY_LINE; then + continue + fi + echo >&8 + EMPTY_LINE='true' + continue + fi + + if echo -ne "$LINE" | egrep '^# CONFIG_' >/dev/null 2>/dev/null; then + LINE=`printf ' %s' ${LINE:9}` + else + LINE=${LINE:1} + echo -ne "/* ${LINE} */\n" >&8 + fi + + EMPTY_LINE='false' + else + EMPTY_LINE='false' + + OLD_IFS="$IFS" + IFS='=' + SETTINGS=($LINE) + IFS="$OLD_IFS" + + if [ ${#SETTINGS[@]} -ge 2 ]; then + if echo -ne "$SETTINGS[0]" | egrep '^CONFIG_' >/dev/null 2>/dev/null; then + SETTINGS[0]="${SETTINGS[0]:7}" + fi + + if is_pkg_special_config "${SETTINGS[0]}"; then + continue + fi + +# echo "DBG---: ${SETTINGS[@]}, ${SETTINGS[*]}" + if [ "${SETTINGS[1]}" = 'y' ]; then + echo -ne "#define ${SETTINGS[0]}\n" >&8 + else + echo -ne "#define ${SETTINGS[0]} ${LINE#*=}\n" >&8 + fi + fi + fi + + done < $CONFIG_NAME + + if [ -f xsconfig_project.h ]; then + echo -ne "#include \"xsconfig_project.h\"\n" >&8 + fi + + echo -ne "\n#endif\n" >&8 + exec 8<&- +} + +make_config_h $1 $BSP_ROOT/xsconfig.h + diff --git a/Ubiquitous/XiZi/tool/scripts/connect_kd233.sh b/Ubiquitous/XiZi/tool/scripts/connect_kd233.sh new file mode 100755 index 0000000..975ae4e --- /dev/null +++ b/Ubiquitous/XiZi/tool/scripts/connect_kd233.sh @@ -0,0 +1,14 @@ +#!/bin/sh +# +#BOARD=kd233 +TTY_PORT=/dev/ttyUSB${1} +BAUDRATE=115200 +#needed for USB-TypeC port, but not for raw uart(TX/RX) +OTHER_OPT='--dtr=0 --rts=0' + +python3 -m serial.tools.miniterm \ +--raw \ +${OTHER_OPT} \ +--filter colorize \ +${TTY_PORT} \ +${BAUDRATE} diff --git a/Ubiquitous/XiZi/tool/scripts/flash_kd233.sh b/Ubiquitous/XiZi/tool/scripts/flash_kd233.sh new file mode 100755 index 0000000..9afd3aa --- /dev/null +++ b/Ubiquitous/XiZi/tool/scripts/flash_kd233.sh @@ -0,0 +1,9 @@ +#!/bin/sh +# +BOARD=kd233 +TTY_PORT=/dev/ttyUSB${1} +BIN=build/XiUOS_k210.bin + +kflash -B ${BOARD} \ +-p ${TTY_PORT} \ +-t ${BIN} diff --git a/Ubiquitous/XiZi/tool/shell/Kconfig b/Ubiquitous/XiZi/tool/shell/Kconfig new file mode 100644 index 0000000..19c3fe9 --- /dev/null +++ b/Ubiquitous/XiZi/tool/shell/Kconfig @@ -0,0 +1,96 @@ +menu "Command shell" + +menuconfig TOOL_SHELL + bool "Enable letter-shell function" + default y + +if TOOL_SHELL + config SHELL_ENTER_CR + bool + config SHELL_ENTER_LF + bool + + choice + prompt "Set shell end-of-line markers :" + default SHELL_ENTER_CR_AND_LF + + config SHELL_ENTER_CR_AND_LF + bool "Using CR And LF as end-of-line markers" + select SHELL_ENTER_CR + select SHELL_ENTER_LF + + config SHELL_ENTER_CRLF + bool "Using CRLF as end-of-line markers" + endchoice + + menu "Set shell user control" + config SHELL_DEFAULT_USER + string "Set default user's name" + default "letter" + + config SHELL_DEFAULT_USER_PASSWORD + string "Set default user's password(none for unnecessary)" + default "" + + config SHELL_LOCK_TIMEOUT + int "Set the lock time(ms) if password isn't none." + default 10000 + endmenu + + menu "Set shell config param" + config SHELL_TASK_STACK_SIZE + int "Set the stack size for shell " + default 4096 + + config SHELL_TASK_PRIORITY + int + default 5 if KTASK_PRIORITY_8 + default 20 if KTASK_PRIORITY_32 + default 120 if KTASK_PRIORITY_256 + + config SHELL_MAX_NUMBER + int "Set the max shell count" + default 5 + + config SHELL_PARAMETER_MAX_NUMBER + int "Set the max number of parameter" + default 8 + help + The max number of parameter in shell. We support up to eight including command name. + + config SHELL_HISTORY_MAX_NUMBER + int "Set the max number of command history" + default 5 + + config SHELL_PRINT_BUFFER + int "Set the max number of print buffer" + default 128 + endmenu + + config SHELL_HELP_SHOW_PERMISSION + bool "Enable the function of showing permission" + default y + help + Show Command and Variable Permission in Shell + + config SHELL_HELP_LIST_USER + bool "List all users " + default n + help + List all users in shell + + config SHELL_HELP_LIST_VAR + bool "List all variable " + default y + help + List all variable in shell + + config SHELL_HELP_LIST_KEY + bool "List all keys " + default n + help + List all keys in shell + +endif + +endmenu diff --git a/Ubiquitous/XiZi/tool/shell/Makefile b/Ubiquitous/XiZi/tool/shell/Makefile new file mode 100644 index 0000000..f45467e --- /dev/null +++ b/Ubiquitous/XiZi/tool/shell/Makefile @@ -0,0 +1,3 @@ +SRC_DIR := letter-shell + +include $(KERNEL_ROOT)/compiler.mk diff --git a/Ubiquitous/XiZi/tool/shell/letter-shell/LICENSE b/Ubiquitous/XiZi/tool/shell/letter-shell/LICENSE new file mode 100644 index 0000000..229cea0 --- /dev/null +++ b/Ubiquitous/XiZi/tool/shell/letter-shell/LICENSE @@ -0,0 +1,21 @@ +MIT License + +Copyright (c) 2019 Letter + +Permission is hereby granted, free of charge, to any person obtaining a copy +of this software and associated documentation files (the "Software"), to deal +in the Software without restriction, including without limitation the rights +to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +copies of the Software, and to permit persons to whom the Software is +furnished to do so, subject to the following conditions: + +The above copyright notice and this permission notice shall be included in all +copies or substantial portions of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +SOFTWARE. diff --git a/Ubiquitous/XiZi/tool/shell/letter-shell/Makefile b/Ubiquitous/XiZi/tool/shell/letter-shell/Makefile new file mode 100644 index 0000000..24f7df0 --- /dev/null +++ b/Ubiquitous/XiZi/tool/shell/letter-shell/Makefile @@ -0,0 +1,7 @@ +SRC_FILES := shell.c shell_ext.c shell_port.c cmd.c + +ifeq ($(CONFIG_FS_VFS), y) +SRC_DIR += file_ext +endif + +include $(KERNEL_ROOT)/compiler.mk diff --git a/Ubiquitous/XiZi/tool/shell/letter-shell/README.md b/Ubiquitous/XiZi/tool/shell/letter-shell/README.md new file mode 100644 index 0000000..1c306c2 --- /dev/null +++ b/Ubiquitous/XiZi/tool/shell/letter-shell/README.md @@ -0,0 +1,215 @@ +# letter shell 3.0 + + +![version](https://img.shields.io/badge/version-3.0.5-brightgreen.svg) +![standard](https://img.shields.io/badge/standard-c99-brightgreen.svg) +![build](https://img.shields.io/badge/build-2020.08.23-brightgreen.svg) +![license](https://img.shields.io/badge/license-MIT-brightgreen.svg) + +一个功能强大的嵌入式shell + +## 简介 + +[letter shell 3.0](https://github.com/NevermindZZT/letter-shell/tree/shell3.0)是一个C语言编写的，可以嵌入在程序中的嵌入式shell，主要面向嵌入式设备，以C语言函数为运行单位，可以通过命令行调用，运行程序中的函数 + +该移植适配了Xiuos操作系统，并进行了精简。 + +原始版本的使用说明可参考[Letter shell 3.0 全新出发](https://nevermindzzt.github.io/2020/01/19/Letter%20shell%203.0%E5%85%A8%E6%96%B0%E5%87%BA%E5%8F%91/) + +## 功能 + +- 命令自动补全 +- 快捷键功能定义 +- 命令权限管理 +- 用户管理 +- 变量支持 +- 文件系统的支持 + +## 配置选项() + +1. 配置宏 + + 下面列出了用于配置shell的宏，在使用前，可用menuconfig进行配置 + + + | 宏 | 意义 | + | - | - | + | TOOL_SHELL | 是否开启shell(默认y) | + | | | + | SHELL_HELP_LIST_USER | 是否在输入命令列表中列出用户 | + | SHELL_HELP_LIST_VAR | 是否在输入命令列表中列出变量 | + | SHELL_HELP_LIST_KEY | 是否在输入命令列表中列出按键 | + | SHELL_ENTER_LF | 使用LF作为命令行回车触发 | + | SHELL_ENTER_CR | 使用CR作为命令行回车触发 | + | SHELL_ENTER_CRLF | 使用CRLF作为命令行回车触发 | + | SHELL_COMMAND_MAX_LENGTH | shell命令最大长度 | + | SHELL_PARAMETER_MAX_NUMBER | shell命令参数最大数量 | + | SHELL_HISTORY_MAX_NUMBER | 历史命令记录数量 | + | SHELL_MAX_NUMBER | 管理的最大shell数量 | + | SHELL_DEFAULT_USER | shell默认用户 | + | SHELL_DEFAULT_USER_PASSWORD | 默认用户密码 | + | SHELL_LOCK_TIMEOUT | shell自动锁定超时 | + +## 使用方式 + +### 命令定义 + +letter shell 3.0将可执行的函数定义，变量定义统一归为命令定义，使用相同的结构储存，查找和执行 + +#### 定义方式 + +letter shell 的命令导出方式支持在函数体外部，采用定义常量的方式定义命令，例如`SHELL_EXPORT_CMD(SHELL_CMD_PERMISSION(0)|SHELL_CMD_TYPE (SHELL_TYPE_CMD_MAIN)|SHELL_CMD_DISABLE_RETURN,help, shellHelp, show command info\r\nhelp [cmd]);` + +letter shell 的命令表方式只支持在shell_cmd_list.c源文件的shellCommandList数据结构中添加命令，例如`SHELL_CMD_ITEM(SHELL_CMD_PERMISSION(0)|SHELL_CMD_TYPE(SHELL_TYPE_CMD_MAIN)|SHELL_CMD_DISABLE_RETURN,help, shellHelp, show command info\r\nhelp [cmd]),` + +#### 命令导出宏 + +letter shell 3.0对可执行命令提供了一个宏，用于进行命令导出。 + +对可执行命令定义使用宏`SHELL_EXPORT_CMD`定义可执行命令，宏定义如下 + +```C +/** + * @brief shell 命令定义 + * + * @param _attr 命令属性 + * @param _name 命令名 + * @param _func 命令函数 + * @param _desc 命令描述 + */ +#define SHELL_EXPORT_CMD(_attr, _name, _func, _desc) \ + const char shellCmd##_name[] = #_name; \ + const char shellDesc##_name[] = #_desc; \ + const ShellCommand \ + shellCommand##_name SECTION("shellCommand") = \ + { \ + .attr.value = _attr, \ + .data.cmd.name = shellCmd##_name, \ + .data.cmd.function = (int (*)())_func, \ + .data.cmd.desc = shellDesc##_name \ + } +``` + +#### 命令属性字段说明 + +在命令定义中，有一个`attr`字段，表示该命令的属性，具体定义为 + +```C +union +{ + struct + { + unsigned char permission : 8; /**< command权限 */ + ShellCommandType type : 4; /**< command类型 */ + unsigned char enableUnchecked : 1; /**< 在未校验密码的情况下可用 */ + unsigned char readOnly : 1; /**< 只读 */ + unsigned char reserve : 1; /**< 保留 */ + unsigned char paramNum : 4; /**< 参数数量 */ + } attrs; + int value; +} attr; +``` + +在定义命令时，需要给定这些值，可以通过宏快速声明: + +```c +SHELL_CMD_PERMISSION(permission) + +SHELL_CMD_TYPE(type) + +SHELL_CMD_ENABLE_UNCHECKED + +SHELL_CMD_DISABLE_RETURN + +SHELL_CMD_READ_ONLY + +SHELL_CMD_PARAM_NUM(num) +``` + +### 命令导出时，函数参数形式 + +letter shell 3.0同时支持两种形式的函数定义方式，形如main函数定义的`func(int argc, char *agrv[])`以及形如普通C函数的定义`func(int i, char *str, ...)`，两种函数定义方式适用于不同的场景 + +#### main函数形式 + +使用此方式，一个函数定义的例子如下： + +```C +int func(int argc, char *agrv[]) +{ + printf("%dparameter(s)\r\n", argc); + for (char i = 1; i < argc; i++) + { + printf("%s\r\n", argv[i]); + } +} +SHELL_EXPORT_CMD(SHELL_CMD_PERMISSION(0)|SHELL_CMD_TYPE(SHELL_TYPE_CMD_MAIN), func, func, test); +``` + +终端调用 + +```sh +letter:/$ func "hello world" +2 parameter(s) +hello world +``` + +#### 普通C函数形式 + +使用此方式，shell会自动对参数进行转化处理，目前支持二进制，八进制，十进制，十六进制整形，字符，字符串的自动处理，例子如下： + +```C +int func(int i, char ch, char *str) +{ + printf("input int: %d, char: %c, string: %s\r\n", i, ch, str); +} +SHELL_EXPORT_CMD(SHELL_CMD_PERMISSION(0)|SHELL_CMD_TYPE(SHELL_TYPE_CMD_FUNC), func, func, test); +``` + +终端调用 + +```sh +letter:/$ func 666 'A' "hello world" +input int: 666, char: A, string: hello world +``` + +### 变量定义 + +letter shell 3.0支持导出变量，通过命令行查看，设置以及使用变量的值 + +- 导出变量 + + 变量导出使用`SHELL_EXPORT_VAR`宏，支持整形(char, short, int)，字符串，指针以及节点变量，变量导出需要使用引用的方式，如果不允许对变量进行修改，在属性中添加`SHELL_CMD_READ_ONLY` + + ```C + int varInt = 0; + SHELL_EXPORT_VAR(SHELL_CMD_PERMISSION(0)|SHELL_CMD_TYPE(SHELL_TYPE_VAR_INT), varInt, &varInt, test); + + char str[] = "test string"; + SHELL_EXPORT_VAR(SHELL_CMD_PERMISSION(0)|SHELL_CMD_TYPE(SHELL_TYPE_VAR_STRING), varStr, str, test); + + Log log; + SHELL_EXPORT_VAR(SHELL_CMD_PERMISSION(0)|SHELL_CMD_TYPE(SHELL_TYPE_VAR_POINT), log, &log, test); + ``` +- 查看变量 + + 在命令行直接输入导出的变量名即可查看变量当前的值 + + ```sh + letter:/$ varInt + varInt = 0, 0x00000000 + + letter:/$ varStr + varStr = "test string" + ``` +- 修改变量 + + 使用`setVar`命令修改变量的值，对于字符串型变量，请确认字符串有分配足够的空间，指针类型的变量不可修改 + + ```sh + letter:/$ setVar varInt 45678 + varInt = 45678, 0x0000b26e + + letter:/$ setVar varStr "hello" + varStr = "hello" + ``` diff --git a/Ubiquitous/XiZi/tool/shell/letter-shell/cmd.c b/Ubiquitous/XiZi/tool/shell/letter-shell/cmd.c new file mode 100644 index 0000000..f3a4b60 --- /dev/null +++ b/Ubiquitous/XiZi/tool/shell/letter-shell/cmd.c @@ -0,0 +1,550 @@ +/* + * Copyright (c) 2020 AIIT XUOS Lab + * XiUOS is licensed under Mulan PSL v2. + * You can use this software according to the terms and conditions of the Mulan PSL v2. + * You may obtain a copy of Mulan PSL v2 at: + * http://license.coscl.org.cn/MulanPSL2 + * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, + * EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, + * MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. + * See the Mulan PSL v2 for more details. +*/ + +#include +#include "shell.h" +#include +#include +#include + +long Hello(void) +{ + KPrintf("Hello World!\n"); + + return 0; +} +SHELL_EXPORT_CMD(SHELL_CMD_PERMISSION(0)|SHELL_CMD_TYPE(SHELL_TYPE_CMD_FUNC)|SHELL_CMD_PARAM_NUM(0)|SHELL_CMD_DISABLE_RETURN, Hello, Hello, show Hello World information); + +extern void ShowBanner(void); +long ShowVersion(void) +{ + ShowBanner(); + + return 0; +} +SHELL_EXPORT_CMD(SHELL_CMD_PERMISSION(0)|SHELL_CMD_TYPE(SHELL_TYPE_CMD_FUNC)|SHELL_CMD_PARAM_NUM(0)|SHELL_CMD_DISABLE_RETURN, ShowVersion, ShowVersion, show XiZi version information); + +static __inline void PrintSpace(int len) +{ + while (len--) KPrintf(" "); +} + +extern DoubleLinklistType xiaoshan_task_head; + +#ifdef KERNEL_SEMAPHORE +extern DoubleLinklistType k_sem_list; +#endif + +#ifdef KERNEL_MUTEX +extern DoubleLinklistType k_mutex_list; +#endif + +#ifdef KERNEL_EVENT +extern DoubleLinklistType k_event_list; +#endif + +#ifdef KERNEL_MESSAGEQUEUE +extern DoubleLinklistType k_mq_list; +#endif + +#ifdef KERNEL_SOFTTIMER +extern DoubleLinklistType k_timer_list; +#endif + +#ifdef KERNEL_MEMBLOCK +extern DoubleLinklistType xiaoshan_memgather_head; +#endif + +extern DoubleLinklistType bus_linklist; + +long ShowTask(void) +{ + int k = 0; + x_ubase lock = 0; + uint8 stat = 0; + uint8 *ptr = NONE; + const char *item_title = "TASK"; + struct TaskDescriptor *task = NONE; + DoubleLinklistType *nodelink = NONE; + + KPrintf("*************************************************************************************************\n"); +#ifdef ARCH_SMP + for(k = 0;k < CPU_NUMBERS; k++){ + KPrintf(" CPU[%d] CURRENT RUNNING TASK[ %s ] PRI[ %d ] \n",k,Assign.smp_os_running_task[k]->task_base_info.name,Assign.smp_os_running_task[k]->task_dync_sched_member.cur_prio); + } +#else + KPrintf(" CURRENT RUNNING TASK[ %s ] PRI[ %d ]\n",Assign.os_running_task->task_base_info.name,Assign.os_running_task->task_dync_sched_member.cur_prio); +#endif + +#ifdef SCHED_POLICY_RR_REMAINSLICE + KPrintf(" SCHED POLICY [ RR_REMAINSLICE ]\n"); +#endif +#ifdef SCHED_POLICY_RR + KPrintf(" SCHED POLICY [ RR ]\n"); +#endif +#ifdef SCHED_POLICY_FIFO + KPrintf(" SCHED POLICY [ FIFO ]\n"); +#endif + + KPrintf("*************************************************************************************************\n"); +#ifndef SCHED_POLICY_FIFO +#ifdef ARCH_SMP + KPrintf(" STAT ID %-*.s PRI CORE STACK_DEPTH USED LEFT_TICKS ERROR_STAT\n", NAME_NUM_MAX, item_title); +#else + KPrintf(" STAT ID %-*.s PRI STACK_DEPTH USED LEFT_TICKS ERROR_STAT\n", NAME_NUM_MAX, item_title); +#endif +#else +#ifdef ARCH_SMP + KPrintf(" STAT ID %-*.s PRI CORE STACK_DEPTH USED ERROR_STAT\n", NAME_NUM_MAX, item_title); +#else + KPrintf(" STAT ID %-*.s PRI STACK_DEPTH USED ERROR_STAT\n", NAME_NUM_MAX, item_title); +#endif +#endif + + lock = CriticalAreaLock(); + DOUBLE_LINKLIST_FOR_EACH(nodelink, &xiaoshan_task_head) { + task = CONTAINER_OF(nodelink, struct TaskDescriptor, link); + if(NONE != task) { + stat = KTaskStatGet(task); + if (stat == KTASK_READY) KPrintf(" READY "); + else if (stat == KTASK_SUSPEND) KPrintf(" SUSPEND"); + else if (stat == KTASK_INIT) KPrintf(" INIT "); + else if (stat == KTASK_CLOSE) KPrintf(" CLOSE "); + else if (stat == KTASK_RUNNING) KPrintf(" RUNNING"); + +#ifdef ARCH_SMP + KPrintf("%3d %-*.*s %3d %3d ", task->id.id,NAME_NUM_MAX, NAME_NUM_MAX, task->task_base_info.name, task->task_dync_sched_member.cur_prio,task->task_smp_info.runing_coreid ); + +#else + KPrintf("%3d %-*.*s %3d ", task->id.id,NAME_NUM_MAX, NAME_NUM_MAX, task->task_base_info.name, task->task_dync_sched_member.cur_prio); +#endif + +#ifndef SCHED_POLICY_FIFO + ptr = (uint8 *)task->task_base_info.stack_start; + while (*ptr == '#')ptr ++; + + KPrintf(" %-10d%d%% %-10d%04d\n", + task->task_base_info.stack_depth, + (task->task_base_info.stack_depth - ((x_ubase) ptr - (x_ubase) task->task_base_info.stack_start)) * 100 / task->task_base_info.stack_depth, + task->task_dync_sched_member.rest_timeslice, task->exstatus); + +#else + ptr = (uint8 *)task->task_base_info.stack_start; + while (*ptr == '#')ptr ++; + + KPrintf(" %-10d%d%% %04d\n", + task->task_base_info.stack_depth, + (task->task_base_info.stack_depth - ((x_ubase) ptr - (x_ubase) task->task_base_info.stack_start)) * 100 / task->task_base_info.stack_depth, task->exstatus); + +#endif + } + + } + CriticalAreaUnLock(lock); + + KPrintf("*************************************************************************************************\n"); + + return 0; +} +SHELL_EXPORT_CMD(SHELL_CMD_PERMISSION(0)|SHELL_CMD_TYPE(SHELL_TYPE_CMD_FUNC)|SHELL_CMD_PARAM_NUM(0)|SHELL_CMD_DISABLE_RETURN, ShowTask, ShowTask, show task information in XiZi); + +static void GetSuspendedTask(struct SysDoubleLinklistNode *list) +{ + struct TaskDescriptor *task = NONE; + DoubleLinklistType *nodelink = NONE; + DOUBLE_LINKLIST_FOR_EACH(nodelink, list){ + task = CONTAINER_OF(nodelink, struct TaskDescriptor, task_dync_sched_member.sched_link); + if(NONE != task) { + KPrintf("%s | ", task->task_base_info.name); + } + } +} + +#ifdef KERNEL_SEMAPHORE + +long ShowSem(void) +{ + x_base lock = 0; + struct Semaphore *sem = NONE; + DoubleLinklistType *nodelink = NONE; + + KPrintf("******************************************************************\n"); + KPrintf(" SEM_ID VALUE SUSPEND_TASK\n"); + + lock = CriticalAreaLock(); + DOUBLE_LINKLIST_FOR_EACH(nodelink, &k_sem_list) { + sem = CONTAINER_OF(nodelink, struct Semaphore, link); + if(NONE != sem) { + if (!IsDoubleLinkListEmpty(&sem->pend_list)) { + KPrintf(" %-8d%-8d :", sem->id.id, sem->value); + GetSuspendedTask(&(sem->pend_list)); + KPrintf("\n"); + } else { + KPrintf(" %-8d%-8d NONE\n", sem->id.id, sem->value); + } + } + } + CriticalAreaUnLock(lock); + KPrintf("******************************************************************\n"); + + return 0; +} +SHELL_EXPORT_CMD(SHELL_CMD_PERMISSION(0)|SHELL_CMD_TYPE(SHELL_TYPE_CMD_FUNC)|SHELL_CMD_PARAM_NUM(0)|SHELL_CMD_DISABLE_RETURN, ShowSem, ShowSem, show sem information in XiZi); + +#endif + +#ifdef KERNEL_EVENT + +long ShowEvent(void) +{ + x_base lock = 0; + struct Event *event = NONE; + DoubleLinklistType *nodelink = NONE; + + KPrintf("******************************************************************\n"); + KPrintf(" EVENT_ID OPTIONS EVENTS SUSPEND_TASK\n"); + + lock = CriticalAreaLock(); + DOUBLE_LINKLIST_FOR_EACH(nodelink, &k_event_list) { + event = CONTAINER_OF(nodelink, struct Event, link); + if(NONE != event) { + if (!IsDoubleLinkListEmpty(&event->pend_list)) { + KPrintf(" %-8d0x%-8x0x%-12x", event->id.id, event->options, event->events); + GetSuspendedTask(&(event->pend_list)); + KPrintf("\n"); + } else { + KPrintf(" %-8d0x%-8x0x%-12x NONE\n", event->id.id, event->options, event->events); + } + } + } + CriticalAreaUnLock(lock); + KPrintf("******************************************************************\n"); + return 0; +} +SHELL_EXPORT_CMD(SHELL_CMD_PERMISSION(0)|SHELL_CMD_TYPE(SHELL_TYPE_CMD_FUNC)|SHELL_CMD_PARAM_NUM(0)|SHELL_CMD_DISABLE_RETURN, ShowEvent, ShowEvent, show event information in XiZi); + +#endif +#ifdef KERNEL_MUTEX +long ShowMutex(void) +{ + x_base lock = 0; + struct Mutex *mutex = NONE; + DoubleLinklistType *nodelink = NONE; + + KPrintf("******************************************************************\n"); + KPrintf("MUTEX_ID HOLDER RECRUSIVE_CNT SUSPEND_TASK\n"); + + lock = CriticalAreaLock(); + DOUBLE_LINKLIST_FOR_EACH(nodelink, &k_mutex_list) { + mutex = CONTAINER_OF(nodelink, struct Mutex, link); + if(NONE != mutex) { + if (!IsDoubleLinkListEmpty(&mutex->pend_list)) { + KPrintf(" %-8d%-10s%-12d", mutex->id.id, (mutex->holder == NONE ?"NONE":(mutex->holder->task_base_info.name)), mutex->recursive_cnt); + GetSuspendedTask(&(mutex->pend_list)); + KPrintf("\n"); + } else { + KPrintf(" %-8d%-10s%-12d NONE\n", mutex->id.id, (mutex->holder == NONE ?"NONE":(mutex->holder->task_base_info.name)), mutex->recursive_cnt); + } + } + } + CriticalAreaUnLock(lock); + KPrintf("******************************************************************\n"); + + return 0; +} +SHELL_EXPORT_CMD(SHELL_CMD_PERMISSION(0)|SHELL_CMD_TYPE(SHELL_TYPE_CMD_FUNC)|SHELL_CMD_PARAM_NUM(0)|SHELL_CMD_DISABLE_RETURN, ShowMutex, ShowMutex, show mutex information in XiZi); +#endif + +#ifdef KERNEL_MESSAGEQUEUE +long ShowMsgQueue(void) +{ + x_base lock = 0; + struct MsgQueue *msgq = NONE; + DoubleLinklistType *nodelink = NONE; + + KPrintf("****************************************************************************************\n"); + KPrintf(" MSG_ID NUM_MSGS EACH_LEN MAX_MSGS %-32s%s\n","SEND_SUSPEND_TASK","RECV_SUSPEND_TASK"); + + lock = CriticalAreaLock(); + DOUBLE_LINKLIST_FOR_EACH(nodelink, &k_mq_list) { + msgq = CONTAINER_OF(nodelink, struct MsgQueue, link); + if(NONE != msgq) { + KPrintf(" %-8d%-8d%-8d%-8d", msgq->id.id, msgq->num_msgs, msgq->each_len,msgq->max_msgs); + if (!IsDoubleLinkListEmpty(&msgq->send_pend_list)) { + GetSuspendedTask(&(msgq->send_pend_list)); + } else { + PrintSpace(32); + } + + if (!IsDoubleLinkListEmpty(&msgq->recv_pend_list)){ + GetSuspendedTask(&(msgq->recv_pend_list)); + } + + KPrintf("\n"); + } + } + CriticalAreaUnLock(lock); + KPrintf("****************************************************************************************\n"); + + return 0; +} + +SHELL_EXPORT_CMD(SHELL_CMD_PERMISSION(0)|SHELL_CMD_TYPE(SHELL_TYPE_CMD_FUNC)|SHELL_CMD_PARAM_NUM(0)|SHELL_CMD_DISABLE_RETURN, ShowMsgQueue, ShowMsgQueue, show msg queue information in XiZi); + +#endif + +#ifdef KERNEL_MEMBLOCK +long ShowGatherMem(void) +{ + x_base lock = 0; + struct MemGather *mg = NONE; + DoubleLinklistType *nodelink = NONE; + + KPrintf("****************************************************************************************\n"); + KPrintf("GATHERMEM BLOCK TOTAL FREE SUSPEND_TASK\n"); + + lock = CriticalAreaLock(); + DOUBLE_LINKLIST_FOR_EACH(nodelink, &xiaoshan_memgather_head) { + mg = CONTAINER_OF(nodelink, struct MemGather, m_link); + if(NONE != mg) { + if (!IsDoubleLinkListEmpty(&mg->wait_task)) { + KPrintf(" %-8s%-6d%-6d%-6d :", + mg->m_name, + mg->one_block_size, + mg->block_total_number, + mg->block_free_number); + GetSuspendedTask(&(mg->wait_task)); + KPrintf("\n"); + } else { + KPrintf(" %-8s%-6d%-6d%-6d NONE\n", + mg->m_name, + mg->one_block_size, + mg->block_total_number, + mg->block_free_number); + } + } + } + CriticalAreaUnLock(lock); + KPrintf("****************************************************************************************\n"); + + return 0; +} + +SHELL_EXPORT_CMD(SHELL_CMD_PERMISSION(0)|SHELL_CMD_TYPE(SHELL_TYPE_CMD_FUNC)|SHELL_CMD_PARAM_NUM(0)|SHELL_CMD_DISABLE_RETURN, ShowGatherMem, ShowGatherMem, show mem block information in XiZi); + +#endif +#ifdef KERNEL_SOFTTIMER +long ShowTimer(void) +{ + x_base lock = 0; + struct Timer *timer = NONE; + DoubleLinklistType *nodelink = NONE; + + KPrintf("****************************************************************************************\n"); + KPrintf(" TIMER_ID NAME STATUS PERIODIC DEADLINE\n"); + + lock = CriticalAreaLock(); + DOUBLE_LINKLIST_FOR_EACH(nodelink, &k_timer_list) { + timer = CONTAINER_OF(nodelink, struct Timer, link); + if(NONE != timer) { + KPrintf(" %-8d%-8s%-10s%-10d%d\n", timer->id_node.id, timer->name, (timer->active_status == TIMER_ACTIVE_TRUE ? "active" : "unactive"),timer->origin_timeslice,timer->deadline_timeslice); + } + } + CriticalAreaUnLock(lock); + KPrintf("****************************************************************************************\n"); + + return 0; +} + +SHELL_EXPORT_CMD(SHELL_CMD_PERMISSION(0)|SHELL_CMD_TYPE(SHELL_TYPE_CMD_FUNC)|SHELL_CMD_PARAM_NUM(0)|SHELL_CMD_DISABLE_RETURN, ShowTimer, ShowTimer, show timer information in XiZi); +#endif + +static char *const bus_type_str[] = +{ + "I2C_BUS", + "SPI_BUS", + "HWT_BUS", + "USB_BUS", + "CAN_BUS", + "WDT_BUS", + "SDIO_BUS", + "TOUCH_BUS", + "LCD_BUS", + "PIN_BUS", + "RTC_BUS", + "SERIAL_BUS", + "ADC_BUS", + "DAC_BUS", + "Unknown" +}; + +static DriverType ShowBusFindDriver(struct Bus *bus) +{ + struct Driver *driver = NONE; + + DoubleLinklistType *node = NONE; + DoubleLinklistType *head = &bus->bus_drvlink; + + for(node = head->node_next; node != head; node = node->node_next) { + driver = SYS_DOUBLE_LINKLIST_ENTRY(node, struct Driver, driver_link); + return driver; + } + return NONE; +} + +long ShowBus(void) +{ + BusType bus; + DriverType driver; + HardwareDevType device; + + DoubleLinklistType *bus_node = NONE; + DoubleLinklistType *bus_head = &bus_linklist; + + int i = 0; + int dev_cnt, maxlen; + const char *item_type = "bus_type"; + const char *item_name_0 = "bus_name"; + const char *item_name_1 = "drv_name"; + const char *item_name_2 = "dev_name"; + const char *item_cnt = "cnt"; + + KPrintf(" %-15s%-15s%-15s%-15s%-20s\n", item_type, item_name_0, item_name_1, item_name_2, item_cnt); + maxlen = 65; + while (i < maxlen) { + i++; + if (maxlen == i) { + KPrintf("-\n"); + } else { + KPrintf("-"); + } + } + + bus_node = bus_head->node_next; + + do + { + bus = SYS_DOUBLE_LINKLIST_ENTRY(bus_node, struct Bus, bus_link); + if (bus) { + KPrintf("%s", " "); + KPrintf("%-15s%-15s", + bus_type_str[bus->bus_type], + bus->bus_name); + + driver = ShowBusFindDriver(bus); + + if (driver) { + KPrintf("%-15s", driver->drv_name); + } else { + KPrintf("%-15s", "nil"); + } + + if (bus->haldev_cnt) { + DoubleLinklistType *dev_node = NONE; + DoubleLinklistType *dev_head = &bus->bus_devlink; + + dev_node = dev_head->node_next; + dev_cnt = 1; + while (dev_node != dev_head) { + device = SYS_DOUBLE_LINKLIST_ENTRY(dev_node, struct HardwareDev, dev_link); + + if (1 == dev_cnt) { + if (device) { + KPrintf("%-16s%-4d\n", device->dev_name, dev_cnt); + } else { + KPrintf("%-16s%-4d\n", "nil", dev_cnt); + } + } else { + KPrintf("%46s", " "); + if (device) { + KPrintf("%-16s%-4d\n", device->dev_name, dev_cnt); + } else { + KPrintf("%-16s%-4d\n", "nil", dev_cnt); + } + } + dev_cnt++; + dev_node = dev_node->node_next; + } + } else { + KPrintf("\n"); + } + } + bus_node = bus_node->node_next; + } + while (bus_node != bus_head); + + return 0; +} + +SHELL_EXPORT_CMD(SHELL_CMD_PERMISSION(0)|SHELL_CMD_TYPE(SHELL_TYPE_CMD_FUNC)|SHELL_CMD_PARAM_NUM(1)|SHELL_CMD_DISABLE_RETURN,ShowBus, ShowBus, show bus information in XiZi); + +#ifdef RESOURCES_RTC +#include "bus_rtc.h" +static void SetDateAndTime(char argc, char **argv) +{ + if (1 == argc) { + time_t now; + + now = time(NONE); + KPrintf("%s", ctime(&now)); + } else if (argc >= 7) { + struct RtcSetParam rtc_set_param; + + rtc_set_param.rtc_set_cmd = OPER_RTC_SET_TIME; + uint16 year; + uint8 month, day, hour, min, sec; + year = atoi(argv[1]); + month = atoi(argv[2]); + day = atoi(argv[3]); + hour = atoi(argv[4]); + min = atoi(argv[5]); + sec = atoi(argv[6]); + if (year > 2099 || year < 2000) { + KPrintf("year is out of range [2000-2099]\n"); + return; + } + if (month == 0 || month > 12) { + KPrintf("month is out of range [1-12]\n"); + return; + } + if (day == 0 || day > 31) { + KPrintf("day is out of range [1-31]\n"); + return; + } + if (hour > 23) { + KPrintf("hour is out of range [0-23]\n"); + return; + } + if (min > 59) { + KPrintf("minute is out of range [0-59]\n"); + return; + } + if (sec > 59) { + KPrintf("second is out of range [0-59]\n"); + return; + } + + rtc_set_param.date_param.year = year; + rtc_set_param.date_param.month = month; + rtc_set_param.date_param.day = day; + rtc_set_param.time_param.hour = hour; + rtc_set_param.time_param.minute = min; + rtc_set_param.time_param.second = sec; + + RtcDrvSetFunction(RTC_DRV_NAME, &rtc_set_param); + } else { + KPrintf("only support input [year month day hour min sec]\n"); + } +} +SHELL_EXPORT_CMD(SHELL_CMD_PERMISSION(0)|SHELL_CMD_TYPE(SHELL_TYPE_CMD_MAIN)|SHELL_CMD_PARAM_NUM(9), SetDateAndTime, SetDateAndTime, set date and time using rtc function); + +#endif diff --git a/Ubiquitous/XiZi/tool/shell/letter-shell/file_ext/Makefile b/Ubiquitous/XiZi/tool/shell/letter-shell/file_ext/Makefile new file mode 100644 index 0000000..f07bbe6 --- /dev/null +++ b/Ubiquitous/XiZi/tool/shell/letter-shell/file_ext/Makefile @@ -0,0 +1,5 @@ +SRC_FILES := shell_fs.c bunzip2.c bzip2.c gunzip.c gzip.c tar.c unzip.c utility.c msh_file.c + +SRC_DIR := bzlib + +include $(KERNEL_ROOT)/compiler.mk diff --git a/Ubiquitous/XiZi/tool/shell/letter-shell/file_ext/bunzip2.c b/Ubiquitous/XiZi/tool/shell/letter-shell/file_ext/bunzip2.c new file mode 100644 index 0000000..3168745 --- /dev/null +++ b/Ubiquitous/XiZi/tool/shell/letter-shell/file_ext/bunzip2.c @@ -0,0 +1,656 @@ +/* + * Copyright (c) 2020 AIIT XUOS Lab + * XiUOS is licensed under Mulan PSL v2. + * You can use this software according to the terms and conditions of the Mulan PSL v2. + * You may obtain a copy of Mulan PSL v2 at: + * http://license.coscl.org.cn/MulanPSL2 + * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, + * EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, + * MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. + * See the Mulan PSL v2 for more details. +*/ + +#include + +#if defined(FS_VFS) && defined(TOOL_SHELL) + +#include +#include +#include +#include +#include +#include "utility.h" + + +#define MAX_GROUPS 6 +#define GROUP_SIZE 50 +#define MAX_HUFCODE_BITS 20 +#define MAX_SYMBOLS 258 +#define SYMBOL_RUNA 0 +#define SYMBOL_RUNB 1 + +#define BZIP2_MAGIC ('B' + 'Z' * 256) + +#define IOBUF_SIZE 4096 + +#define RET_ERROR -1 +#define RET_LASTBLOCK -2 + + +struct GroupData { + int32_t limit[MAX_HUFCODE_BITS+1], base[MAX_HUFCODE_BITS], permute[MAX_SYMBOLS]; + int minLen, maxLen; +}; + + +typedef struct BunZipData { + + uint32_t inbufBitCount, inbufBits; + int in_fd, out_fd, inbufCount, inbufPos; + uint8_t *inbuf; + + int writeCopies, writePos, writeRunCountdown, writeCount; + int writeCurrent; + + uint32_t headerCRC, totalCRC, writeCRC; + + uint32_t *dbuf; + uint32_t dbufSize; + + uint32_t crc32Table[256]; + uint8_t selectors[32768]; + struct GroupData groups[MAX_GROUPS]; +} BunZipData_t; + + +static int GetBits(BunZipData_t *bd, int bits_wanted, uint32_t *bits) +{ + uint32_t b = 0; + + int bit_count = bd->inbufBitCount; + + while (bit_count < bits_wanted) { + + if (bd->inbufPos == bd->inbufCount) { + bd->inbufCount = read(bd->in_fd, bd->inbuf, IOBUF_SIZE); + if (bd->inbufCount <= 0) + return -1; + bd->inbufPos = 0; + } + + if (bit_count >= 24) { + b = bd->inbufBits & ((1U << bit_count) - 1); + bits_wanted -= bit_count; + b <<= bits_wanted; + bit_count = 0; + } + + bd->inbufBits = (bd->inbufBits << 8) | bd->inbuf[bd->inbufPos++]; + bit_count += 8; + } + + bit_count -= bits_wanted; + bd->inbufBitCount = bit_count; + b |= (bd->inbufBits >> bit_count) & ((1 << bits_wanted) - 1); + *bits = b; + + return 0; +} + +static int GetNextBlock(BunZipData_t *bd) +{ + int groupCount, selector, + i, j, symCount, symTotal, nSelectors, byteCount[256]; + uint8_t uc, symToByte[256], mtfSymbol[256], *selectors; + uint32_t *dbuf; + uint32_t origPtr, t; + uint32_t dbufCount, runPos; + uint32_t runCnt = runCnt; + uint32_t tmp; + + dbuf = bd->dbuf; + selectors = bd->selectors; + + if (GetBits(bd, 24, (uint32_t *)&i) < 0) + return RET_ERROR; + if (GetBits(bd, 24, (uint32_t *)&j) < 0) + return RET_ERROR; + if (GetBits(bd, 32, &bd->headerCRC) < 0) + return RET_ERROR; + if ((i == 0x177245) && (j == 0x385090)) + return RET_LASTBLOCK; + if ((i != 0x314159) || (j != 0x265359)) + return RET_ERROR; + + if (GetBits(bd, 1, &tmp) < 0) + return RET_ERROR; + if (tmp) + return RET_ERROR; + if (GetBits(bd, 24, (uint32_t *)&origPtr) < 0) + return RET_ERROR; + if (origPtr > bd->dbufSize) + return RET_ERROR; + + symTotal = 0; + i = 0; + if (GetBits(bd, 16, &t) < 0) + return RET_ERROR; + do { + if (t & (1 << 15)) { + uint32_t inner_map; + if (GetBits(bd, 16, &inner_map) < 0) + return RET_ERROR; + do { + if (inner_map & (1 << 15)) + symToByte[symTotal++] = i; + inner_map <<= 1; + i++; + } while (i & 15); + i -= 16; + } + t <<= 1; + i += 16; + } while (i < 256); + + if (GetBits(bd, 3, (uint32_t *)&groupCount) < 0) + return RET_ERROR; + if (groupCount < 2 || groupCount > MAX_GROUPS) + return RET_ERROR; + + + for (i = 0; i < groupCount; i++) + mtfSymbol[i] = i; + if (GetBits(bd, 15, (uint32_t *)&nSelectors) < 0) + return RET_ERROR; + if (!nSelectors) + return RET_ERROR; + for (i = 0; i < nSelectors; i++) { + uint8_t tmp_byte; + + int n = 0; + while (GetBits(bd, 1, &tmp) == 0 && tmp) { + n++; + if (n >= groupCount) + return RET_ERROR; + } + + tmp_byte = mtfSymbol[n]; + while (--n >= 0) + mtfSymbol[n + 1] = mtfSymbol[n]; + mtfSymbol[0] = selectors[i] = tmp_byte; + } + + + symCount = symTotal + 2; + for (j = 0; j < groupCount; j++) { + uint8_t length[MAX_SYMBOLS]; + + uint32_t temp[MAX_HUFCODE_BITS+1]; + struct GroupData *hufGroup; + int32_t *base, *limit; + int minLen, maxLen, pp, len_m1; + + + if (GetBits(bd, 5, (uint32_t *)&len_m1) < 0) + return RET_ERROR; + len_m1 -= 1; + for (i = 0; i < symCount; i++) { + for (;;) { + int two_bits; + if ((uint32_t)len_m1 > (MAX_HUFCODE_BITS - 1)) + return RET_ERROR; + + if (GetBits(bd, 2, (uint32_t *)&two_bits) < 0) + return RET_ERROR; + if (two_bits < 2) { + bd->inbufBitCount++; + break; + } + + len_m1 += (((two_bits+1) & 2) - 1); + } + length[i] = len_m1 + 1; + } + + minLen = maxLen = length[0]; + for (i = 1; i < symCount; i++) { + if (length[i] > maxLen) + maxLen = length[i]; + else if (length[i] < minLen) + minLen = length[i]; + } + + hufGroup = bd->groups + j; + hufGroup->minLen = minLen; + hufGroup->maxLen = maxLen; + + base = &hufGroup->base[0] - 1; + limit = &hufGroup->limit[0] - 1; + + pp = 0; + for (i = minLen; i <= maxLen; i++) { + int k; + temp[i] = limit[i] = 0; + for (k = 0; k < symCount; k++) + if (length[k] == i) + hufGroup->permute[pp++] = k; + } + + for (i = 0; i < symCount; i++) + temp[length[i]]++; + + pp = t = 0; + for (i = minLen; i < maxLen;) { + uint32_t temp_i = temp[i]; + + pp += temp_i; + + limit[i] = (pp << (maxLen - i)) - 1; + pp <<= 1; + t += temp_i; + base[++i] = pp - t; + } + limit[maxLen] = pp + temp[maxLen] - 1; + limit[maxLen+1] = INT32_MAX; + base[minLen] = 0; + } + + for (i = 0; i < 256; i++) { + byteCount[i] = 0; + mtfSymbol[i] = (uint8_t)i; + } + + runPos = dbufCount = selector = 0; + for (;;) { + struct GroupData *hufGroup; + int *base, *limit; + int nextSym; + uint8_t ngrp; + + symCount = GROUP_SIZE - 1; + if (selector >= nSelectors) + return RET_ERROR; + ngrp = selectors[selector++]; + if (ngrp >= groupCount) + return RET_ERROR; + hufGroup = bd->groups + ngrp; + base = (int *)hufGroup->base - 1; + limit = (int *)hufGroup->limit - 1; + + continue_this_group: + + if (1) { + + int new_cnt; + while ((new_cnt = bd->inbufBitCount - hufGroup->maxLen) < 0) { + + if (bd->inbufPos == bd->inbufCount) { + if (GetBits(bd, hufGroup->maxLen, (uint32_t *)&nextSym) < 0) + return RET_ERROR; + goto got_huff_bits; + } + bd->inbufBits = (bd->inbufBits << 8) | bd->inbuf[bd->inbufPos++]; + bd->inbufBitCount += 8; + }; + bd->inbufBitCount = new_cnt; + nextSym = (bd->inbufBits >> new_cnt) & ((1 << hufGroup->maxLen) - 1); + got_huff_bits: ; + } else { + if (GetBits(bd, hufGroup->maxLen, (uint32_t *)&nextSym) < 0) + return RET_ERROR; + } + + i = hufGroup->minLen; + while (nextSym > limit[i]) + ++i; + j = hufGroup->maxLen - i; + if (j < 0) + return RET_ERROR; + bd->inbufBitCount += j; + + + nextSym = (nextSym >> j) - base[i]; + if ((unsigned)nextSym >= MAX_SYMBOLS) + return RET_ERROR; + nextSym = hufGroup->permute[nextSym]; + + + if ((unsigned)nextSym <= SYMBOL_RUNB) { + + + if (runPos == 0) { + runPos = 1; + runCnt = 0; + } + + runCnt += (runPos << nextSym); + if (runPos < bd->dbufSize) runPos <<= 1; + goto end_of_huffman_loop; + } + + if (runPos != 0) { + uint8_t tmp_byte; + if (dbufCount + runCnt > bd->dbufSize) + return RET_ERROR; + tmp_byte = symToByte[mtfSymbol[0]]; + byteCount[tmp_byte] += runCnt; + while ((int)--runCnt >= 0) + dbuf[dbufCount++] = (uint32_t)tmp_byte; + runPos = 0; + } + + if (nextSym > symTotal) + break; + if (dbufCount >= bd->dbufSize) + return RET_ERROR; + i = nextSym - 1; + uc = mtfSymbol[i]; + + do { + mtfSymbol[i] = mtfSymbol[i - 1]; + } while (--i); + mtfSymbol[0] = uc; + uc = symToByte[uc]; + + byteCount[uc]++; + dbuf[dbufCount++] = (uint32_t)uc; + + end_of_huffman_loop: + if (--symCount >= 0) goto continue_this_group; + } + + j = 0; + for (i = 0; i < 256; i++) { + int tmp_count = j + byteCount[i]; + byteCount[i] = j; + j = tmp_count; + } + + for (i = 0; i < dbufCount; i++) { + uint8_t tmp_byte = (uint8_t)dbuf[i]; + int tmp_count = byteCount[tmp_byte]; + dbuf[tmp_count] |= (i << 8); + byteCount[tmp_byte] = tmp_count + 1; + } + + if (dbufCount) { + uint32_t tmp; + if ((int)origPtr >= dbufCount) + return RET_ERROR; + tmp = dbuf[origPtr]; + bd->writeCurrent = (uint8_t)tmp; + bd->writePos = (tmp >> 8); + bd->writeRunCountdown = 5; + } + bd->writeCount = dbufCount; + + return 0; +} + +static int ReadBunzip(BunZipData_t *bd, char *outbuf, int len) +{ + const uint32_t *dbuf; + int pos, current, previous; + uint32_t CRC; + + + if (bd->writeCount < 0) + return bd->writeCount; + + dbuf = bd->dbuf; + + + pos = bd->writePos; + current = bd->writeCurrent; + CRC = bd->writeCRC; + + + if (bd->writeCopies) { + + dec_writeCopies: + + --bd->writeCopies; + + for (;;) { + + + if (--len < 0) { + + goto outbuf_full; + } + + + *outbuf++ = current; + CRC = (CRC << 8) ^ bd->crc32Table[(CRC >> 24) ^ current]; + + + if (bd->writeCopies) { + + goto dec_writeCopies; + } + decode_next_byte: + if (--bd->writeCount < 0) + break; + + previous = current; + pos = dbuf[pos]; + current = (uint8_t)pos; + pos >>= 8; + + if (--bd->writeRunCountdown != 0) { + if (current != previous) + bd->writeRunCountdown = 4; + } else { + + bd->writeCopies = current; + current = previous; + bd->writeRunCountdown = 5; + + + if (!bd->writeCopies) goto decode_next_byte; + + + --bd->writeCopies; + } + } + + + bd->writeCRC = CRC = ~CRC; + bd->totalCRC = ((bd->totalCRC << 1) | (bd->totalCRC >> 31)) ^ CRC; + + if (CRC != bd->headerCRC) { + bd->totalCRC = bd->headerCRC + 1; + return RET_LASTBLOCK; + } + } + + { + int r = GetNextBlock(bd); + if (r) { + bd->writeCount = r; + return (r != RET_LASTBLOCK) ? r : len; + } + } + + CRC = ~0; + pos = bd->writePos; + current = bd->writeCurrent; + goto decode_next_byte; + + outbuf_full: + bd->writePos = pos; + bd->writeCurrent = current; + bd->writeCRC = CRC; + + bd->writeCopies++; + + return 0; +} + +static void Crc32FilltableBigEndian(uint32_t *crc_table) +{ + uint32_t polynomial = 0x04c11db7; + uint32_t c; + unsigned i, j; + + for (i = 0; i < 256; i++) { + c = i << 24; + for (j = 8; j; j--) { + c = (c & 0x80000000) ? ((c << 1) ^ polynomial) : (c << 1); + } + *crc_table++ = c; + } +} + +static int StartBunzip(BunZipData_t **bdp, int in_fd, + const void *inbuf, int len) +{ + BunZipData_t *bd; + uint32_t i; + enum { + BZh0 = ('B' << 24) + ('Z' << 16) + ('h' << 8) + '0', + h0 = ('h' << 8) + '0', + }; + + i = sizeof(BunZipData_t); + if (in_fd != -1) + i += IOBUF_SIZE; + + bd = *bdp = malloc(i); + if (bd == NULL) + return RET_ERROR; + memset(bd, 0, sizeof(*bd)); + + bd->in_fd = in_fd; + if (in_fd == -1) { + bd->inbuf = (void *)inbuf; + } else { + bd->inbuf = (uint8_t *)(bd + 1); + memcpy(bd->inbuf, inbuf, len); + } + bd->inbufCount = len; + + Crc32FilltableBigEndian(bd->crc32Table); + + if (GetBits(bd, 16, (uint32_t *)&i) < 0) + return RET_ERROR; + if ((unsigned)(i - h0 - 1) >= 9) + return RET_ERROR; + + bd->dbufSize = 100000 * (i - h0); + + bd->dbuf = malloc(bd->dbufSize * sizeof(bd->dbuf[0])); + if (!bd->dbuf) { + free(bd); + return RET_ERROR; + } + return 0; +} + +int Bzip2Decompress(char *file_name) +{ + BunZipData_t *bd; + char *out_buf; + int i; + uint32_t len; + int in_fd, out_fd; + uint16_t magic; + int ret = 0; + + if ((in_fd = open(file_name, O_RDONLY)) < 0) + return RET_ERROR; + + if (TruncateExtension(file_name, ".bz2") < 0) { + ret = RET_ERROR; + goto close_in_fd; + } + if ((out_fd = open(file_name, O_WRONLY | O_CREAT | O_TRUNC)) < 0) { + ret = RET_ERROR; + goto close_in_fd; + } + + if ((out_buf = malloc(IOBUF_SIZE)) == NULL) { + ret = RET_ERROR; + goto close_out_fd; + } + + if (read(in_fd, &magic, 2) != 2 || magic != BZIP2_MAGIC) { + ret = -1; + goto free_out_buf; + } + + len = 0; + while (1) { + i = StartBunzip(&bd, in_fd, out_buf + 2, len); + if (i == 0) { + while (1) { + i = ReadBunzip(bd, out_buf, IOBUF_SIZE); + if (i < 0) + break; + i = IOBUF_SIZE - i; + if (i == 0) + break; + if (write(out_fd, out_buf, i) != i) { + ret = RET_ERROR; + goto free_bd; + } + } + } + + if (i != 0 && i != RET_LASTBLOCK) + break; + if (bd->headerCRC != bd->totalCRC) + break; + + i = 0; + + len = bd->inbufCount - bd->inbufPos; + memcpy(out_buf, &bd->inbuf[bd->inbufPos], len); + if (len < 2) { + if (read(in_fd, out_buf + len, 2 - len) != 2 - len) + break; + len = 2; + } + if (*(uint16_t *)out_buf != BZIP2_MAGIC) + break; + free(bd->dbuf); + free(bd); + len -=2; + } + +free_bd: + free(bd->dbuf); + free(bd); +free_out_buf: + free(out_buf); +close_out_fd: + close(out_fd); +close_in_fd: + close(in_fd); + + return ret; +} + +void Bunzip2PrintUsage() +{ + KPrintf("Usage: bunzip2 [FILES]....\n"); + KPrintf("File names MUST end with the .bz2 extension\n"); +} + +int bunzip2(int argc, char **argv) +{ + if (argc < 2) { + Bunzip2PrintUsage(); + return 0; + } + + for (int i = 1; i < argc; i++) + if (Bzip2Decompress(argv[i]) < 0) + KPrintf("Operation failed: %s\n", argv[i]); + + return 0; +} + + + +#endif diff --git a/Ubiquitous/XiZi/tool/shell/letter-shell/file_ext/bzip2.c b/Ubiquitous/XiZi/tool/shell/letter-shell/file_ext/bzip2.c new file mode 100644 index 0000000..90a7d52 --- /dev/null +++ b/Ubiquitous/XiZi/tool/shell/letter-shell/file_ext/bzip2.c @@ -0,0 +1,162 @@ +/* + * Copyright (c) 2020 AIIT XUOS Lab + * XiUOS is licensed under Mulan PSL v2. + * You can use this software according to the terms and conditions of the Mulan PSL v2. + * You may obtain a copy of Mulan PSL v2 at: + * http://license.coscl.org.cn/MulanPSL2 + * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, + * EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, + * MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. + * See the Mulan PSL v2 for more details. +*/ + +#include + +#if defined(FS_VFS) && defined(TOOL_SHELL) + +#include +#include +#include +#include +#include +#include +#include "bzlib/bzlib.h" +#include "utility.h" + +#define IOBUF_SIZE 8192 + +char *in_buf, *out_buf; + + +static int BzWrite(BzStream *stream, int ReadSize, int out_fd) + +{ + stream->avail_in = ReadSize; + stream->next_in = in_buf; + + while (1) { + stream->avail_out = IOBUF_SIZE; + stream->next_out = out_buf; + + int ret = BZ2BzCompress(stream, + ReadSize > 0 ? BZ_RUN : BZ_FINISH); + + if (ret != BZ_RUN_OK && ret != BZ_FINISH_OK && + ret != BZ_STREAM_END) + return -1; + + int out_buf_cnt = IOBUF_SIZE - stream->avail_out; + if (out_buf_cnt) { + int written_size = write(out_fd, out_buf, out_buf_cnt); + if (written_size != out_buf_cnt) + return -1; + } + + if (ret == BZ_STREAM_END || (ReadSize > 0 && stream->avail_in == 0)) + break; + } + + return 0; +} + +int Bzip2Compress(char *file_name) +{ + int ret = 0; + char *bz_file_name; + struct stat statbuf; + int in_fd, out_fd; + BzStream stream; + + if ((in_fd = open(file_name, O_RDONLY)) < 0) + return -1; + if (fstat(in_fd, &statbuf) < 0 || !S_ISREG(statbuf.st_mode)) { + ret = -1; + goto close_in_fd; + } + + if ((bz_file_name = malloc(strlen(file_name) + 5)) == NULL) { + ret = -1; + goto close_in_fd; + } + strcpy(bz_file_name, file_name); + strcat(bz_file_name, ".bz2"); + + if ((out_fd = open(bz_file_name, O_WRONLY | O_CREAT | O_TRUNC)) < 0) { + ret = -1; + goto free_bz_file_name; + } + + if ((in_buf = malloc(2 * IOBUF_SIZE)) == NULL) { + ret = -1; + goto close_out_fd; + } + out_buf = in_buf + IOBUF_SIZE; + + memset(&stream, 0, sizeof(BzStream)); + BZ2BzCompressInit(&stream, 1); + + while (1) { + int ReadSize = read(in_fd, in_buf, IOBUF_SIZE); + if (ReadSize < 0) { + ret = -1; + break; + } + + ret = BzWrite(&stream, ReadSize, out_fd); + if (ReadSize == 0 || ret < 0) + + break; + } + + BZ2BzCompressEnd(&stream); + + free(in_buf); +close_out_fd: + close(out_fd); +free_bz_file_name: + free(bz_file_name); +close_in_fd: + close(in_fd); + + return ret; +} + +static void Bzip2PrintUsage() +{ + KPrintf("Usage: bzip2 [OPTIONS]... [FILES]...\n"); + KPrintf("Supported option flags:\n"); + KPrintf(" d decompress bzip2 file(s)\n"); +} + +extern int Bzip2Decompress(char *file_name); + +int bzip2(int argc, char **argv) +{ + int (*bzip2_func)(char *file_name) = Bzip2Compress; + if (argc == 1) { + Bzip2PrintUsage(); + return 0; + } + + if (argv[1][0] == '-') { + if (strcmp(argv[1], "-b") != 0) { + KPrintf("Bad options\n"); + Bzip2PrintUsage(); + return 0; + } + bzip2_func = Bzip2Decompress; + argv++; + argc--; + } + + for (int i = 1; i < argc; i++) + if (bzip2_func(argv[i]) < 0) { + KPrintf("Operation failed\n"); + break; + } + + return 0; +} + + +#endif diff --git a/Ubiquitous/XiZi/tool/shell/letter-shell/file_ext/bzip2.h b/Ubiquitous/XiZi/tool/shell/letter-shell/file_ext/bzip2.h new file mode 100644 index 0000000..fb9a4c4 --- /dev/null +++ b/Ubiquitous/XiZi/tool/shell/letter-shell/file_ext/bzip2.h @@ -0,0 +1,18 @@ +/* + * Copyright (c) 2020 AIIT XUOS Lab + * XiUOS is licensed under Mulan PSL v2. + * You can use this software according to the terms and conditions of the Mulan PSL v2. + * You may obtain a copy of Mulan PSL v2 at: + * http://license.coscl.org.cn/MulanPSL2 + * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, + * EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, + * MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. + * See the Mulan PSL v2 for more details. +*/ + +#ifndef __INC_BZIP2_H__ +#define __INC_BZIP2_H__ + +int Bzip2Compress(char *file_name); + +#endif diff --git a/Ubiquitous/XiZi/tool/shell/letter-shell/file_ext/bzlib/Makefile b/Ubiquitous/XiZi/tool/shell/letter-shell/file_ext/bzlib/Makefile new file mode 100644 index 0000000..2109f1b --- /dev/null +++ b/Ubiquitous/XiZi/tool/shell/letter-shell/file_ext/bzlib/Makefile @@ -0,0 +1,5 @@ +SRC_FILES := blocksort.c bzlib.c compress.c huffman.c + + + +include $(KERNEL_ROOT)/compiler.mk diff --git a/Ubiquitous/XiZi/tool/shell/letter-shell/file_ext/bzlib/blocksort.c b/Ubiquitous/XiZi/tool/shell/letter-shell/file_ext/bzlib/blocksort.c new file mode 100644 index 0000000..9792b5a --- /dev/null +++ b/Ubiquitous/XiZi/tool/shell/letter-shell/file_ext/bzlib/blocksort.c @@ -0,0 +1,838 @@ +/* ------------------------------------------------------------------ +This file is part of bzip2/libbzip2, a program and library for +lossless, block-sorting data compression. + +bzip2/libbzip2 version 1.0.4 of 20 December 2006 +Copyright (C) 1996-2006 Julian Seward + +Please read the WARNING, DISCLAIMER and PATENTS sections in the +README file. + +This program is released under the terms of the license contained +in the file LICENSE. +------------------------------------------------------------------ */ + +#include +#include +#include "bzlib_private.h" + +#define MSWAP(zz1, zz2) { \ + int32_t zztmp = zz1; \ + zz1 = zz2; \ + zz2 = zztmp; \ + } + +static void mvswap(uint32_t* ptr, int32_t zzp1, int32_t zzp2, int32_t zzn) +{ + while (zzn > 0) { + MSWAP(ptr[zzp1], ptr[zzp2]); + zzp1++; + zzp2++; + zzn--; + } +} + +static inline int32_t mmin(int32_t a, int32_t b) +{ + return (a < b) ? a : b; +} + +static inline void FallbackSimpleSort(uint32_t* fmap, + uint32_t* eclass, + int32_t lo, + int32_t hi) +{ + int32_t i, j, tmp; + uint32_t ec_tmp; + + if (lo == hi) return; + + if (hi - lo > 3) { + for (i = hi-4; i >= lo; i--) { + tmp = fmap[i]; + ec_tmp = eclass[tmp]; + for (j = i+4; j <= hi && ec_tmp > eclass[fmap[j]]; j += 4) + fmap[j-4] = fmap[j]; + fmap[j-4] = tmp; + } + } + + for (i = hi-1; i >= lo; i--) { + tmp = fmap[i]; + ec_tmp = eclass[tmp]; + for (j = i+1; j <= hi && ec_tmp > eclass[fmap[j]]; j++) + fmap[j-1] = fmap[j]; + fmap[j-1] = tmp; + } +} + + +#define FPUSH(lz,hz) { \ + stackLo[sp] = lz; \ + stackHi[sp] = hz; \ + sp++; \ + } + +#define FPOP(lz,hz) { \ + sp--; \ + lz = stackLo[sp]; \ + hz = stackHi[sp]; \ + } + +#define FALLBACK_QSORT_SMALL_THRESH 10 +#define FALLBACK_QSORT_STACK_SIZE 100 + +static void FallbackQSort3(uint32_t* fmap, + uint32_t* eclass, + int32_t loSt, + int32_t hiSt) +{ + int32_t sp; + uint32_t r; + int32_t stackLo[FALLBACK_QSORT_STACK_SIZE]; + int32_t stackHi[FALLBACK_QSORT_STACK_SIZE]; + + r = 0; + + sp = 0; + FPUSH(loSt, hiSt); + + while (sp > 0) { + int32_t unLo, unHi, ltLo, gtHi, n, m; + int32_t lo, hi; + uint32_t med; + uint32_t r3; + + ASSERTH(sp < FALLBACK_QSORT_STACK_SIZE - 1, 1004); + + FPOP(lo, hi); + if (hi - lo < FALLBACK_QSORT_SMALL_THRESH) { + FallbackSimpleSort(fmap, eclass, lo, hi); + continue; + } + + r = ((r * 7621) + 1) % 32768; + r3 = r % 3; + if (r3 == 0) + med = eclass[fmap[lo]]; + else if (r3 == 1) + med = eclass[fmap[(lo+hi)>>1]]; + else + med = eclass[fmap[hi]]; + + unLo = ltLo = lo; + unHi = gtHi = hi; + + while (1) { + while (1) { + if (unLo > unHi) break; + n = (int32_t)eclass[fmap[unLo]] - (int32_t)med; + if (n == 0) { + MSWAP(fmap[unLo], fmap[ltLo]); + ltLo++; + unLo++; + continue; + } + if (n > 0) break; + unLo++; + } + while (1) { + if (unLo > unHi) break; + n = (int32_t)eclass[fmap[unHi]] - (int32_t)med; + if (n == 0) { + MSWAP(fmap[unHi], fmap[gtHi]); + gtHi--; unHi--; + continue; + } + if (n < 0) break; + unHi--; + } + if (unLo > unHi) break; + MSWAP(fmap[unLo], fmap[unHi]); unLo++; unHi--; + } + + ASSERTD(unHi == unLo-1, "fallbackQSort3(2)"); + + if (gtHi < ltLo) continue; + + n = mmin(ltLo-lo, unLo-ltLo); mvswap(fmap, lo, unLo-n, n); + m = mmin(hi-gtHi, gtHi-unHi); mvswap(fmap, unLo, hi-m+1, m); + + n = lo + unLo - ltLo - 1; + m = hi - (gtHi - unHi) + 1; + + if (n - lo > hi - m) { + FPUSH(lo, n); + FPUSH(m, hi); + } else { + FPUSH(m, hi); + FPUSH(lo, n); + } + } +} + +#undef FPUSH +#undef FPOP +#undef FALLBACK_QSORT_SMALL_THRESH +#undef FALLBACK_QSORT_STACK_SIZE + + +#define SET_BH(zz) bhtab[(zz) >> 5] |= (1 << ((zz) & 31)) +#define CLEAR_BH(zz) bhtab[(zz) >> 5] &= ~(1 << ((zz) & 31)) +#define ISSET_BH(zz) (bhtab[(zz) >> 5] & (1 << ((zz) & 31))) +#define WORD_BH(zz) bhtab[(zz) >> 5] +#define UNALIGNED_BH(zz) ((zz) & 0x01f) + +static void FallbackSort(EState* state) +{ + int32_t ftab[257]; + int32_t ftabCopy[256]; + int32_t H, i, j, k, l, r, cc, cc1; + int32_t nNotDone; + int32_t nBhtab; + + uint32_t *const fmap = state->arr1; + uint32_t *const eclass = state->arr2; +#define ECLASS8 ((uint8_t*)eclass) + uint32_t *const bhtab = state->ftab; + const int32_t nblock = state->nblock; + + + for (i = 0; i < 257; i++) ftab[i] = 0; + for (i = 0; i < nblock; i++) ftab[ECLASS8[i]]++; + for (i = 0; i < 256; i++) ftabCopy[i] = ftab[i]; + + j = ftab[0]; + for (i = 1; i < 257; i++) { + j += ftab[i]; + ftab[i] = j; + } + + for (i = 0; i < nblock; i++) { + j = ECLASS8[i]; + k = ftab[j] - 1; + ftab[j] = k; + fmap[k] = i; + } + + nBhtab = 2 + ((uint32_t)nblock / 32); + for (i = 0; i < nBhtab; i++) bhtab[i] = 0; + for (i = 0; i < 256; i++) SET_BH(ftab[i]); + + for (i = 0; i < 32; i++) { + SET_BH(nblock + 2*i); + CLEAR_BH(nblock + 2*i + 1); + } + + H = 1; + while (1) { + j = 0; + for (i = 0; i < nblock; i++) { + if (ISSET_BH(i)) + j = i; + k = fmap[i] - H; + if (k < 0) + k += nblock; + eclass[k] = j; + } + + nNotDone = 0; + r = -1; + while (1) { + + k = r + 1; + while (ISSET_BH(k) && UNALIGNED_BH(k)) + k++; + if (ISSET_BH(k)) { + while (WORD_BH(k) == 0xffffffff) k += 32; + while (ISSET_BH(k)) k++; + } + l = k - 1; + if (l >= nblock) + break; + while (!ISSET_BH(k) && UNALIGNED_BH(k)) + k++; + if (!ISSET_BH(k)) { + while (WORD_BH(k) == 0x00000000) k += 32; + while (!ISSET_BH(k)) k++; + } + r = k - 1; + if (r >= nblock) + break; + + if (r > l) { + nNotDone += (r - l + 1); + FallbackQSort3(fmap, eclass, l, r); + + cc = -1; + for (i = l; i <= r; i++) { + cc1 = eclass[fmap[i]]; + if (cc != cc1) { + SET_BH(i); + cc = cc1; + } + } + } + } + + H *= 2; + if (H > nblock || nNotDone == 0) + break; + } + + j = 0; + for (i = 0; i < nblock; i++) { + while (ftabCopy[j] == 0) + j++; + ftabCopy[j]--; + ECLASS8[fmap[i]] = (uint8_t)j; + } + ASSERTH(j < 256, 1005); +#undef ECLASS8 +} + +#undef SET_BH +#undef CLEAR_BH +#undef ISSET_BH +#undef WORD_BH +#undef UNALIGNED_BH + +static int MainGtU(EState* state, + uint32_t i1, + uint32_t i2) +{ + int32_t k; + uint8_t c1, c2; + uint16_t s1, s2; + + uint8_t *const block = state->block; + uint16_t *const quadrant = state->quadrant; + const int32_t nblock = state->nblock; + + +#if BZIP2_SPEED >= 1 + +#define TIMES_8(code) \ + code; code; code; code; \ + code; code; code; code; +#define TIMES_12(code) \ + code; code; code; code; \ + code; code; code; code; \ + code; code; code; code; + +#else + +#define TIMES_8(code) { \ + int nn = 8; \ + do { \ + code; \ + } while (--nn); \ + } +#define TIMES_12(code) { \ + int nn = 12; \ + do { \ + code; \ + } while (--nn); \ + } + +#endif + + ASSERTD(i1 != i2, "mainGtU"); + TIMES_12( + c1 = block[i1]; c2 = block[i2]; + if (c1 != c2) return (c1 > c2); + i1++; i2++; + ) + + k = nblock + 8; + + do { + TIMES_8( + c1 = block[i1]; c2 = block[i2]; + if (c1 != c2) return (c1 > c2); + s1 = quadrant[i1]; s2 = quadrant[i2]; + if (s1 != s2) return (s1 > s2); + i1++; i2++; + ) + + if (i1 >= nblock) i1 -= nblock; + if (i2 >= nblock) i2 -= nblock; + + state->budget--; + k -= 8; + } while (k >= 0); + + return FALSE; +} +#undef TIMES_8 +#undef TIMES_12 + +static +const uint32_t incs[14] = { + 1, 4, 13, 40, 121, 364, 1093, 3280, + 9841, 29524, 88573, 265720, + 797161, 2391484 +}; + +static void MainSimpleSort(EState* state, + int32_t lo, + int32_t hi, + int32_t d) +{ + uint32_t *const ptr = state->ptr; + + int hp = 0; + { + int bigN = hi - lo; + if (bigN <= 0) + return; + while (incs[hp] <= bigN) + hp++; + hp--; + } + + for (; hp >= 0; hp--) { + int32_t i; + unsigned h; + + h = incs[hp]; + i = lo + h; + while (1) { + unsigned j; + unsigned v; + + if (i > hi) break; + v = ptr[i]; + j = i; + while (MainGtU(state, ptr[j-h]+d, v+d)) { + ptr[j] = ptr[j-h]; + j = j - h; + if (j <= (lo + h - 1)) break; + } + ptr[j] = v; + i++; + +#if BZIP2_SPEED >= 3 + if (i > hi) break; + v = ptr[i]; + j = i; + while (MainGtU(state, ptr[j-h]+d, v+d)) { + ptr[j] = ptr[j-h]; + j = j - h; + if (j <= (lo + h - 1)) break; + } + ptr[j] = v; + i++; + if (i > hi) break; + v = ptr[i]; + j = i; + while (MainGtU(state, ptr[j-h]+d, v+d)) { + ptr[j] = ptr[j-h]; + j = j - h; + if (j <= (lo + h - 1)) break; + } + ptr[j] = v; + i++; +#endif + if (state->budget < 0) return; + } + } +} + + +static inline uint8_t mmed3(uint8_t a, uint8_t b, uint8_t c) +{ + uint8_t t; + if (a > b) { + t = a; + a = b; + b = t; + } + if (b > c) { + b = c; + if (a > b) + b = a; + } + return b; +} + +#define MPUSH(lz,hz,dz) { \ + stackLo[sp] = lz; \ + stackHi[sp] = hz; \ + stackD [sp] = dz; \ + sp++; \ + } + +#define MPOP(lz,hz,dz) { \ + sp--; \ + lz = stackLo[sp]; \ + hz = stackHi[sp]; \ + dz = stackD [sp]; \ + } + +#define MNEXTSIZE(az) (nextHi[az] - nextLo[az]) + +#define MNEXTSWAP(az,bz) { \ + int32_t tz; \ + tz = nextLo[az]; nextLo[az] = nextLo[bz]; nextLo[bz] = tz; \ + tz = nextHi[az]; nextHi[az] = nextHi[bz]; nextHi[bz] = tz; \ + tz = nextD [az]; nextD [az] = nextD [bz]; nextD [bz] = tz; \ + } + +#define MAIN_QSORT_SMALL_THRESH 20 +#define MAIN_QSORT_DEPTH_THRESH (BZ_N_RADIX + BZ_N_QSORT) +#define MAIN_QSORT_STACK_SIZE 100 + +static void MainQSort3(EState* state, + int32_t loSt, + int32_t hiSt + ) +{ + enum { dSt = BZ_N_RADIX }; + int32_t unLo, unHi, ltLo, gtHi, n, m, med; + int32_t sp, lo, hi, d; + + int32_t stackLo[MAIN_QSORT_STACK_SIZE]; + int32_t stackHi[MAIN_QSORT_STACK_SIZE]; + int32_t stackD [MAIN_QSORT_STACK_SIZE]; + + int32_t nextLo[3]; + int32_t nextHi[3]; + int32_t nextD [3]; + + uint32_t *const ptr = state->ptr; + uint8_t *const block = state->block; + + sp = 0; + MPUSH(loSt, hiSt, dSt); + + while (sp > 0) { + ASSERTH(sp < MAIN_QSORT_STACK_SIZE - 2, 1001); + + MPOP(lo, hi, d); + if (hi - lo < MAIN_QSORT_SMALL_THRESH + || d > MAIN_QSORT_DEPTH_THRESH + ) { + MainSimpleSort(state, lo, hi, d); + if (state->budget < 0) + return; + continue; + } + med = (int32_t) mmed3(block[ptr[lo ] + d], + block[ptr[hi ] + d], + block[ptr[(lo+hi) >> 1] + d]); + + unLo = ltLo = lo; + unHi = gtHi = hi; + + while (1) { + while (1) { + if (unLo > unHi) + break; + n = ((int32_t)block[ptr[unLo]+d]) - med; + if (n == 0) { + MSWAP(ptr[unLo], ptr[ltLo]); + ltLo++; + unLo++; + continue; + } + if (n > 0) break; + unLo++; + } + while (1) { + if (unLo > unHi) + break; + n = ((int32_t)block[ptr[unHi]+d]) - med; + if (n == 0) { + MSWAP(ptr[unHi], ptr[gtHi]); + gtHi--; + unHi--; + continue; + } + if (n < 0) break; + unHi--; + } + if (unLo > unHi) + break; + MSWAP(ptr[unLo], ptr[unHi]); + unLo++; + unHi--; + } + + ASSERTD(unHi == unLo-1, "mainQSort3(2)"); + + if (gtHi < ltLo) { + MPUSH(lo, hi, d + 1); + continue; + } + + n = mmin(ltLo-lo, unLo-ltLo); mvswap(ptr, lo, unLo-n, n); + m = mmin(hi-gtHi, gtHi-unHi); mvswap(ptr, unLo, hi-m+1, m); + + n = lo + unLo - ltLo - 1; + m = hi - (gtHi - unHi) + 1; + + nextLo[0] = lo; nextHi[0] = n; nextD[0] = d; + nextLo[1] = m; nextHi[1] = hi; nextD[1] = d; + nextLo[2] = n+1; nextHi[2] = m-1; nextD[2] = d+1; + + if (MNEXTSIZE(0) < MNEXTSIZE(1)) MNEXTSWAP(0, 1); + if (MNEXTSIZE(1) < MNEXTSIZE(2)) MNEXTSWAP(1, 2); + if (MNEXTSIZE(0) < MNEXTSIZE(1)) MNEXTSWAP(0, 1); + + ASSERTD (MNEXTSIZE(0) >= MNEXTSIZE(1), "mainQSort3(8)"); + ASSERTD (MNEXTSIZE(1) >= MNEXTSIZE(2), "mainQSort3(9)"); + + MPUSH(nextLo[0], nextHi[0], nextD[0]); + MPUSH(nextLo[1], nextHi[1], nextD[1]); + MPUSH(nextLo[2], nextHi[2], nextD[2]); + } +} + +#undef MPUSH +#undef MPOP +#undef MNEXTSIZE +#undef MNEXTSWAP +#undef MAIN_QSORT_SMALL_THRESH +#undef MAIN_QSORT_DEPTH_THRESH +#undef MAIN_QSORT_STACK_SIZE + + +#define BIGFREQ(b) (ftab[((b)+1) << 8] - ftab[(b) << 8]) +#define SETMASK (1 << 21) +#define CLEARMASK (~(SETMASK)) + +static void MainSort(EState* state) +{ + int32_t i, j; + Bool bigDone[256]; + uint8_t runningOrder[256]; + +#define COPYSTART (state->mainSort__copyStart) +#define COPYEND (state->mainSort__copyEnd) + + uint32_t *const ptr = state->ptr; + uint8_t *const block = state->block; + uint32_t *const ftab = state->ftab; + const int32_t nblock = state->nblock; + uint16_t *const quadrant = state->quadrant; + + memset(ftab, 0, 65537 * sizeof(ftab[0])); + + j = block[0] << 8; + i = nblock - 1; + +#if BZIP2_SPEED >= 2 + for (; i >= 3; i -= 4) { + quadrant[i] = 0; + j = (j >> 8) | (((unsigned)block[i]) << 8); + ftab[j]++; + quadrant[i-1] = 0; + j = (j >> 8) | (((unsigned)block[i-1]) << 8); + ftab[j]++; + quadrant[i-2] = 0; + j = (j >> 8) | (((unsigned)block[i-2]) << 8); + ftab[j]++; + quadrant[i-3] = 0; + j = (j >> 8) | (((unsigned)block[i-3]) << 8); + ftab[j]++; + } +#endif + for (; i >= 0; i--) { + quadrant[i] = 0; + j = (j >> 8) | (((unsigned)block[i]) << 8); + ftab[j]++; + } + + for (i = 0; i < BZ_N_OVERSHOOT; i++) { + block [nblock+i] = block[i]; + quadrant[nblock+i] = 0; + } + + j = ftab[0]; + for (i = 1; i <= 65536; i++) { + j += ftab[i]; + ftab[i] = j; + } + + { + unsigned s; + s = block[0] << 8; + i = nblock - 1; +#if BZIP2_SPEED >= 2 + for (; i >= 3; i -= 4) { + s = (s >> 8) | (block[i] << 8); + j = ftab[s] - 1; + ftab[s] = j; + ptr[j] = i; + s = (s >> 8) | (block[i-1] << 8); + j = ftab[s] - 1; + ftab[s] = j; + ptr[j] = i-1; + s = (s >> 8) | (block[i-2] << 8); + j = ftab[s] - 1; + ftab[s] = j; + ptr[j] = i-2; + s = (s >> 8) | (block[i-3] << 8); + j = ftab[s] - 1; + ftab[s] = j; + ptr[j] = i-3; + } +#endif + for (; i >= 0; i--) { + s = (s >> 8) | (block[i] << 8); + j = ftab[s] - 1; + ftab[s] = j; + ptr[j] = i; + } + } + + for (i = 0; i <= 255; i++) { + bigDone [i] = FALSE; + runningOrder[i] = i; + } + + { + unsigned h = 364; + + do { + + h = (h * 171) >> 9; + for (i = h; i <= 255; i++) { + unsigned vv, jh; + vv = runningOrder[i]; + j = i; + while (jh = j - h, BIGFREQ(runningOrder[jh]) > BIGFREQ(vv)) { + runningOrder[j] = runningOrder[jh]; + j = jh; + if (j < h) + break; + } + runningOrder[j] = vv; + } + } while (h != 1); + } + + + for (i = 0; ; i++) { + unsigned ss; + + ss = runningOrder[i]; + + + for (j = 0; j <= 255; j++) { + if (j != ss) { + unsigned sb; + sb = (ss << 8) + j; + if (!(ftab[sb] & SETMASK)) { + int32_t lo = ftab[sb] ; + int32_t hi = (ftab[sb+1] & CLEARMASK) - 1; + if (hi > lo) { + MainQSort3(state, lo, hi ); + if (state->budget < 0) return; + } + } + ftab[sb] |= SETMASK; + } + } + + ASSERTH(!bigDone[ss], 1006); + + { + for (j = 0; j <= 255; j++) { + COPYSTART[j] = ftab[(j << 8) + ss] & CLEARMASK; + COPYEND [j] = (ftab[(j << 8) + ss + 1] & CLEARMASK) - 1; + } + for (j = ftab[ss << 8] & CLEARMASK; j < COPYSTART[ss]; j++) { + unsigned c1; + int32_t k; + k = ptr[j] - 1; + if (k < 0) + k += nblock; + c1 = block[k]; + if (!bigDone[c1]) + ptr[COPYSTART[c1]++] = k; + } + for (j = (ftab[(ss+1) << 8] & CLEARMASK) - 1; j > COPYEND[ss]; j--) { + unsigned c1; + int32_t k; + k = ptr[j]-1; + if (k < 0) + k += nblock; + c1 = block[k]; + if (!bigDone[c1]) + ptr[COPYEND[c1]--] = k; + } + } + + + ASSERTH((COPYSTART[ss]-1 == COPYEND[ss]) \ + || (COPYSTART[ss] == 0 && COPYEND[ss] == nblock-1), 1007); + + for (j = 0; j <= 255; j++) + ftab[(j << 8) + ss] |= SETMASK; + + if (i == 255) + break; + + bigDone[ss] = TRUE; + + { + unsigned bbStart = ftab[ss << 8] & CLEARMASK; + unsigned bbSize = (ftab[(ss+1) << 8] & CLEARMASK) - bbStart; + unsigned shifts = 0; + + while ((bbSize >> shifts) > 65534) shifts++; + + for (j = bbSize-1; j >= 0; j--) { + unsigned a2update = ptr[bbStart + j]; + uint16_t qVal = (uint16_t)(j >> shifts); + quadrant[a2update] = qVal; + if (a2update < BZ_N_OVERSHOOT) + quadrant[a2update + nblock] = qVal; + } + ASSERTH(((bbSize-1) >> shifts) <= 65535, 1002); + } + } +#undef runningOrder +#undef COPYSTART +#undef COPYEND +} + +#undef BIGFREQ +#undef SETMASK +#undef CLEARMASK + +int32_t BZ2BlockSort(EState* state) +{ + enum { wfact = 30 }; + unsigned i; + int32_t origPtr = origPtr; + + if (state->nblock >= 10000) { + i = state->nblock + BZ_N_OVERSHOOT; + if (i & 1) + i++; + state->quadrant = (uint16_t*) &(state->block[i]); + + state->budget = state->nblock * ((wfact-1) / 3); + MainSort(state); + if (state->budget >= 0) + goto good; + } + FallbackSort(state); + good: + +#if BZ_LIGHT_DEBUG + origPtr = -1; +#endif + for (i = 0; i < state->nblock; i++) { + if (state->ptr[i] == 0) { + origPtr = i; + break; + } + } + + ASSERTH(origPtr != -1, 1003); + return origPtr; +} diff --git a/Ubiquitous/XiZi/tool/shell/letter-shell/file_ext/bzlib/bzlib.c b/Ubiquitous/XiZi/tool/shell/letter-shell/file_ext/bzlib/bzlib.c new file mode 100644 index 0000000..a4f7c4d --- /dev/null +++ b/Ubiquitous/XiZi/tool/shell/letter-shell/file_ext/bzlib/bzlib.c @@ -0,0 +1,338 @@ +/* ------------------------------------------------------------------ +This file is part of bzip2/libbzip2, a program and library for +lossless, block-sorting data compression. + +bzip2/libbzip2 version 1.0.4 of 20 December 2006 +Copyright (C) 1996-2006 Julian Seward + +Please read the WARNING, DISCLAIMER and PATENTS sections in the +README file. + +This program is released under the terms of the license contained +in the file LICENSE. +------------------------------------------------------------------ */ + +#include + +#if defined(FS_VFS) && defined(TOOL_SHELL) + +#include +#include +#include +#include "bzlib_private.h" + +uint32_t BZ2_crc32Table[256] = { + + 0x00000000L, 0x04c11db7L, 0x09823b6eL, 0x0d4326d9L, + 0x130476dcL, 0x17c56b6bL, 0x1a864db2L, 0x1e475005L, + 0x2608edb8L, 0x22c9f00fL, 0x2f8ad6d6L, 0x2b4bcb61L, + 0x350c9b64L, 0x31cd86d3L, 0x3c8ea00aL, 0x384fbdbdL, + 0x4c11db70L, 0x48d0c6c7L, 0x4593e01eL, 0x4152fda9L, + 0x5f15adacL, 0x5bd4b01bL, 0x569796c2L, 0x52568b75L, + 0x6a1936c8L, 0x6ed82b7fL, 0x639b0da6L, 0x675a1011L, + 0x791d4014L, 0x7ddc5da3L, 0x709f7b7aL, 0x745e66cdL, + 0x9823b6e0L, 0x9ce2ab57L, 0x91a18d8eL, 0x95609039L, + 0x8b27c03cL, 0x8fe6dd8bL, 0x82a5fb52L, 0x8664e6e5L, + 0xbe2b5b58L, 0xbaea46efL, 0xb7a96036L, 0xb3687d81L, + 0xad2f2d84L, 0xa9ee3033L, 0xa4ad16eaL, 0xa06c0b5dL, + 0xd4326d90L, 0xd0f37027L, 0xddb056feL, 0xd9714b49L, + 0xc7361b4cL, 0xc3f706fbL, 0xceb42022L, 0xca753d95L, + 0xf23a8028L, 0xf6fb9d9fL, 0xfbb8bb46L, 0xff79a6f1L, + 0xe13ef6f4L, 0xe5ffeb43L, 0xe8bccd9aL, 0xec7dd02dL, + 0x34867077L, 0x30476dc0L, 0x3d044b19L, 0x39c556aeL, + 0x278206abL, 0x23431b1cL, 0x2e003dc5L, 0x2ac12072L, + 0x128e9dcfL, 0x164f8078L, 0x1b0ca6a1L, 0x1fcdbb16L, + 0x018aeb13L, 0x054bf6a4L, 0x0808d07dL, 0x0cc9cdcaL, + 0x7897ab07L, 0x7c56b6b0L, 0x71159069L, 0x75d48ddeL, + 0x6b93dddbL, 0x6f52c06cL, 0x6211e6b5L, 0x66d0fb02L, + 0x5e9f46bfL, 0x5a5e5b08L, 0x571d7dd1L, 0x53dc6066L, + 0x4d9b3063L, 0x495a2dd4L, 0x44190b0dL, 0x40d816baL, + 0xaca5c697L, 0xa864db20L, 0xa527fdf9L, 0xa1e6e04eL, + 0xbfa1b04bL, 0xbb60adfcL, 0xb6238b25L, 0xb2e29692L, + 0x8aad2b2fL, 0x8e6c3698L, 0x832f1041L, 0x87ee0df6L, + 0x99a95df3L, 0x9d684044L, 0x902b669dL, 0x94ea7b2aL, + 0xe0b41de7L, 0xe4750050L, 0xe9362689L, 0xedf73b3eL, + 0xf3b06b3bL, 0xf771768cL, 0xfa325055L, 0xfef34de2L, + 0xc6bcf05fL, 0xc27dede8L, 0xcf3ecb31L, 0xcbffd686L, + 0xd5b88683L, 0xd1799b34L, 0xdc3abdedL, 0xd8fba05aL, + 0x690ce0eeL, 0x6dcdfd59L, 0x608edb80L, 0x644fc637L, + 0x7a089632L, 0x7ec98b85L, 0x738aad5cL, 0x774bb0ebL, + 0x4f040d56L, 0x4bc510e1L, 0x46863638L, 0x42472b8fL, + 0x5c007b8aL, 0x58c1663dL, 0x558240e4L, 0x51435d53L, + 0x251d3b9eL, 0x21dc2629L, 0x2c9f00f0L, 0x285e1d47L, + 0x36194d42L, 0x32d850f5L, 0x3f9b762cL, 0x3b5a6b9bL, + 0x0315d626L, 0x07d4cb91L, 0x0a97ed48L, 0x0e56f0ffL, + 0x1011a0faL, 0x14d0bd4dL, 0x19939b94L, 0x1d528623L, + 0xf12f560eL, 0xf5ee4bb9L, 0xf8ad6d60L, 0xfc6c70d7L, + 0xe22b20d2L, 0xe6ea3d65L, 0xeba91bbcL, 0xef68060bL, + 0xd727bbb6L, 0xd3e6a601L, 0xdea580d8L, 0xda649d6fL, + 0xc423cd6aL, 0xc0e2d0ddL, 0xcda1f604L, 0xc960ebb3L, + 0xbd3e8d7eL, 0xb9ff90c9L, 0xb4bcb610L, 0xb07daba7L, + 0xae3afba2L, 0xaafbe615L, 0xa7b8c0ccL, 0xa379dd7bL, + 0x9b3660c6L, 0x9ff77d71L, 0x92b45ba8L, 0x9675461fL, + 0x8832161aL, 0x8cf30badL, 0x81b02d74L, 0x857130c3L, + 0x5d8a9099L, 0x594b8d2eL, 0x5408abf7L, 0x50c9b640L, + 0x4e8ee645L, 0x4a4ffbf2L, 0x470cdd2bL, 0x43cdc09cL, + 0x7b827d21L, 0x7f436096L, 0x7200464fL, 0x76c15bf8L, + 0x68860bfdL, 0x6c47164aL, 0x61043093L, 0x65c52d24L, + 0x119b4be9L, 0x155a565eL, 0x18197087L, 0x1cd86d30L, + 0x029f3d35L, 0x065e2082L, 0x0b1d065bL, 0x0fdc1becL, + 0x3793a651L, 0x3352bbe6L, 0x3e119d3fL, 0x3ad08088L, + 0x2497d08dL, 0x2056cd3aL, 0x2d15ebe3L, 0x29d4f654L, + 0xc5a92679L, 0xc1683bceL, 0xcc2b1d17L, 0xc8ea00a0L, + 0xd6ad50a5L, 0xd26c4d12L, 0xdf2f6bcbL, 0xdbee767cL, + 0xe3a1cbc1L, 0xe760d676L, 0xea23f0afL, 0xeee2ed18L, + 0xf0a5bd1dL, 0xf464a0aaL, 0xf9278673L, 0xfde69bc4L, + 0x89b8fd09L, 0x8d79e0beL, 0x803ac667L, 0x84fbdbd0L, + 0x9abc8bd5L, 0x9e7d9662L, 0x933eb0bbL, 0x97ffad0cL, + 0xafb010b1L, 0xab710d06L, 0xa6322bdfL, 0xa2f33668L, + 0xbcb4666dL, 0xb8757bdaL, 0xb5365d03L, 0xb1f740b4L +}; + +#if BZ_LIGHT_DEBUG +static +void BzAssertFail(int errcode) +{ + bb_error_msg_and_die("internal error %d", errcode); +} +#endif + +static +void PrepareNewBlock(EState* s) +{ + int i; + s->nblock = 0; + BZ_INITIALISE_CRC(s->blockCRC); + for (i = 0; i < 256; i++) + s->inUse[i] = 0; + s->blockNo++; +} + +static void InitRL(EState* s) +{ + s->state_in_ch = 256; + s->state_in_len = 0; +} + + +static int IsEmptyRL(EState* s) +{ + return (s->state_in_ch >= 256 || s->state_in_len <= 0); +} + +void BZ2BzCompressInit(BzStream *strm, int blockSize100k) +{ + unsigned n; + EState* s; + + s = malloc(sizeof(EState)); + memset(s, 0, sizeof(EState)); + s->strm = strm; + + n = 100000 * blockSize100k; + s->arr1 = malloc(n * sizeof(uint32_t)); + s->mtfv = (uint16_t*)s->arr1; + s->ptr = (uint32_t*)s->arr1; + s->arr2 = malloc((n + BZ_N_OVERSHOOT) * sizeof(uint32_t)); + s->block = (uint8_t*)s->arr2; + s->ftab = malloc(65537 * sizeof(uint32_t)); + + s->state = BZ_S_INPUT; + s->mode = BZ_M_RUNNING; + s->blockSize100k = blockSize100k; + s->nblockMAX = n - 19; + + strm->state = s; + strm->total_out = 0; + InitRL(s); + PrepareNewBlock(s); +} + +static void AddPairToBlock(EState* s) +{ + int32_t i; + uint8_t ch = (uint8_t)(s->state_in_ch); + for (i = 0; i < s->state_in_len; i++) { + BZ_UPDATE_CRC(s->blockCRC, ch); + } + s->inUse[s->state_in_ch] = 1; + switch (s->state_in_len) { + case 3: + s->block[s->nblock] = (uint8_t)ch; s->nblock++; + case 2: + s->block[s->nblock] = (uint8_t)ch; s->nblock++; + case 1: + s->block[s->nblock] = (uint8_t)ch; s->nblock++; + break; + default: + s->inUse[s->state_in_len - 4] = 1; + s->block[s->nblock] = (uint8_t)ch; s->nblock++; + s->block[s->nblock] = (uint8_t)ch; s->nblock++; + s->block[s->nblock] = (uint8_t)ch; s->nblock++; + s->block[s->nblock] = (uint8_t)ch; s->nblock++; + s->block[s->nblock] = (uint8_t)(s->state_in_len - 4); + s->nblock++; + break; + } +} + +static void FlushRL(EState* s) +{ + if (s->state_in_ch < 256) AddPairToBlock(s); + InitRL(s); +} + +#define ADD_CHAR_TO_BLOCK(zs, zchh0) { \ + uint32_t zchh = (uint32_t)(zchh0); \ + if (zchh != zs->state_in_ch && zs->state_in_len == 1) { \ + uint8_t ch = (uint8_t)(zs->state_in_ch); \ + BZ_UPDATE_CRC(zs->blockCRC, ch); \ + zs->inUse[zs->state_in_ch] = 1; \ + zs->block[zs->nblock] = (uint8_t)ch; \ + zs->nblock++; \ + zs->state_in_ch = zchh; \ + } else \ + if (zchh != zs->state_in_ch || zs->state_in_len == 255) { \ + if (zs->state_in_ch < 256) \ + AddPairToBlock(zs); \ + zs->state_in_ch = zchh; \ + zs->state_in_len = 1; \ + } else { \ + zs->state_in_len++; \ + } \ + } + + +static void CopyInputUntilStop(EState* s) +{ +#ifdef SAME_CODE_AS_BELOW + if (s->mode == BZ_M_RUNNING) { + while (1) { + if (s->strm->avail_in == 0) break; + if (s->nblock >= s->nblockMAX) break; + ADD_CHAR_TO_BLOCK(s, (uint32_t)(*(uint8_t*)(s->strm->next_in))); + s->strm->next_in++; + s->strm->avail_in--; + } + } else +#endif + { + while (1) { + if (s->strm->avail_in == 0) break; + if (s->nblock >= s->nblockMAX) break; + ADD_CHAR_TO_BLOCK(s, *(uint8_t*)(s->strm->next_in)); + s->strm->next_in++; + s->strm->avail_in--; + } + } +} + +static void CopyOutputUntilStop(EState* s) +{ + while (1) { + if (s->strm->avail_out == 0) break; + if (s->state_out_pos >= s->posZ) break; + *(s->strm->next_out) = *s->state_out_pos++; + s->strm->avail_out--; + s->strm->next_out++; + s->strm->total_out++; + } +} + +static void HandleCompress(BzStream *strm) +{ + EState* s = strm->state; + + while (1) { + if (s->state == BZ_S_OUTPUT) { + CopyOutputUntilStop(s); + if (s->state_out_pos < s->posZ) break; + if (s->mode == BZ_M_FINISHING + && s->strm->avail_in == 0 + && IsEmptyRL(s)) + break; + PrepareNewBlock(s); + s->state = BZ_S_INPUT; +#ifdef FLUSH_IS_UNUSED + if (s->mode == BZ_M_FLUSHING + && s->avail_in_expect == 0 + && IsEmptyRL(s)) + break; +#endif + } + + if (s->state == BZ_S_INPUT) { + CopyInputUntilStop(s); + if (s->mode != BZ_M_RUNNING && s->strm->avail_in == 0) { + FlushRL(s); + BZ2CompressBlock(s, (s->mode == BZ_M_FINISHING)); + s->state = BZ_S_OUTPUT; + } else + if (s->nblock >= s->nblockMAX) { + BZ2CompressBlock(s, 0); + s->state = BZ_S_OUTPUT; + } else + if (s->strm->avail_in == 0) { + break; + } + } + } +} + + +int BZ2BzCompress(BzStream *strm, int action) +{ + EState* s; + + s = strm->state; + + switch (s->mode) { + case BZ_M_RUNNING: + if (action == BZ_RUN) { + HandleCompress(strm); + return BZ_RUN_OK; + } +#ifdef FLUSH_IS_UNUSED + else + if (action == BZ_FLUSH) { + s->mode = BZ_M_FLUSHING; + goto case_BZ_M_FLUSHING; + } +#endif + else{ + s->mode = BZ_M_FINISHING; + goto case_BZ_M_FINISHING; + } + +#ifdef FLUSH_IS_UNUSED + case_BZ_M_FLUSHING: + case BZ_M_FLUSHING: + HandleCompress(strm); + if (s->avail_in_expect > 0 || !IsEmptyRL(s) || s->state_out_pos < s->posZ) + return BZ_FLUSH_OK; + s->mode = BZ_M_RUNNING; + return BZ_RUN_OK; +#endif + + case_BZ_M_FINISHING: + default: + + HandleCompress(strm); + if (s->strm->avail_in > 0 || !IsEmptyRL(s) || s->state_out_pos < s->posZ) + return BZ_FINISH_OK; + return BZ_STREAM_END; + } +} + +void BZ2BzCompressEnd(BzStream *strm) +{ + EState* s; + + s = strm->state; + free(s->arr1); + free(s->arr2); + free(s->ftab); + free(s); +} + +#endif diff --git a/Ubiquitous/XiZi/tool/shell/letter-shell/file_ext/bzlib/bzlib.h b/Ubiquitous/XiZi/tool/shell/letter-shell/file_ext/bzlib/bzlib.h new file mode 100644 index 0000000..3a53257 --- /dev/null +++ b/Ubiquitous/XiZi/tool/shell/letter-shell/file_ext/bzlib/bzlib.h @@ -0,0 +1,47 @@ +/* ------------------------------------------------------------------ +This file is part of bzip2/libbzip2, a program and library for +lossless, block-sorting data compression. + +bzip2/libbzip2 version 1.0.4 of 20 December 2006 +Copyright (C) 1996-2006 Julian Seward + +Please read the WARNING, DISCLAIMER and PATENTS sections in the +README file. + +This program is released under the terms of the license contained +in the file LICENSE. +------------------------------------------------------------------ */ + +#define BZ_RUN 0 +#define BZ_FLUSH 1 +#define BZ_FINISH 2 + +#define BZ_OK 0 +#define BZ_RUN_OK 1 +#define BZ_FLUSH_OK 2 +#define BZ_FINISH_OK 3 +#define BZ_STREAM_END 4 +#define BZ_SEQUENCE_ERROR (-1) +#define BZ_PARAM_ERROR (-2) +#define BZ_MEM_ERROR (-3) +#define BZ_DATA_ERROR (-4) +#define BZ_DATA_ERROR_MAGIC (-5) +#define BZ_IO_ERROR (-6) +#define BZ_UNEXPECTED_EOF (-7) +#define BZ_OUTBUFF_FULL (-8) +#define BZ_CONFIG_ERROR (-9) + +typedef struct BzStream { + void *state; + char *next_in; + char *next_out; + unsigned avail_in; + unsigned avail_out; + unsigned long long total_out; +} BzStream; + + +void BZ2BzCompressInit(BzStream *strm, int blockSize100k); +int BZ2BzCompress(BzStream *strm, int action); +void BZ2BzCompressEnd(BzStream *strm); + diff --git a/Ubiquitous/XiZi/tool/shell/letter-shell/file_ext/bzlib/bzlib_private.h b/Ubiquitous/XiZi/tool/shell/letter-shell/file_ext/bzlib/bzlib_private.h new file mode 100644 index 0000000..486f24f --- /dev/null +++ b/Ubiquitous/XiZi/tool/shell/letter-shell/file_ext/bzlib/bzlib_private.h @@ -0,0 +1,165 @@ +/* ------------------------------------------------------------------ +This file is part of bzip2/libbzip2, a program and library for +lossless, block-sorting data compression. + +bzip2/libbzip2 version 1.0.4 of 20 December 2006 +Copyright (C) 1996-2006 Julian Seward + +Please read the WARNING, DISCLAIMER and PATENTS sections in the +README file. + +This program is released under the terms of the license contained +in the file LICENSE. +------------------------------------------------------------------ */ + +#include +#include "bzlib.h" + +typedef unsigned char Bool; + +#define TRUE ((Bool)1) +#define FALSE ((Bool)0) + +#if BZ_LIGHT_DEBUG +static void BzAssertFail(int errcode) NORETURN; +#define ASSERTH(cond, errcode) do { \ + if (!(cond)) \ + BzAssertFail(errcode); \ + } while (0) +#else +#define ASSERTH(cond, msg) do { } while (0) +#endif + +#if BZ_DEBUG +#define ASSERTD(cond, msg) do { \ + if (!(cond)) \ + bb_error_msg_and_die("(debug build): internal error %s", msg); \ + } while (0) +#else +#define ASSERTD(cond, msg) do { } while (0) +#endif + +#define BZ_HDR_B 0x42 +#define BZ_HDR_Z 0x5a +#define BZ_HDR_H 0x68 +#define BZ_HDR_0 0x30 + +#define BZ_HDR_BZH0 0x425a6830 + + +#define BZ_MAX_ALPHA_SIZE 258 +#define BZ_MAX_CODE_LEN 23 + +#define BZ_RUNA 0 +#define BZ_RUNB 1 + +#define BZ_N_GROUPS 6 +#define BZ_G_SIZE 50 +#define BZ_N_ITERS 4 + +#define BZ_MAX_SELECTORS (2 + (900000 / BZ_G_SIZE)) + + +extern uint32_t BZ2_crc32Table[256]; + +#define BZ_INITIALISE_CRC(crcVar) { \ + crcVar = 0xffffffffL; \ + } + +#define BZ_FINALISE_CRC(crcVar) { \ + crcVar = ~(crcVar); \ + } + +#define BZ_UPDATE_CRC(crcVar,cha) { \ + crcVar = (crcVar << 8) ^ \ + BZ2_crc32Table[(crcVar >> 24) ^ \ + ((uint8_t)cha)]; \ + } + + +#define BZ_M_IDLE 1 +#define BZ_M_RUNNING 2 +#define BZ_M_FLUSHING 3 +#define BZ_M_FINISHING 4 + +#define BZ_S_OUTPUT 1 +#define BZ_S_INPUT 2 + +#define BZ_N_RADIX 2 +#define BZ_N_QSORT 12 +#define BZ_N_SHELL 18 +#define BZ_N_OVERSHOOT (BZ_N_RADIX + BZ_N_QSORT + BZ_N_SHELL + 2) + + + +typedef struct EState { + BzStream *strm; + + uint8_t mode; + uint8_t state; + + uint8_t blockSize100k; + + uint32_t *arr1; + uint32_t *arr2; + uint32_t *ftab; + + uint16_t *quadrant; + int32_t budget; + + uint32_t *ptr; + uint8_t *block; + uint16_t *mtfv; + uint8_t *zbits; + + uint32_t state_in_ch; + int32_t state_in_len; + + int32_t nblock; + int32_t nblockMAX; + uint8_t *posZ; + uint8_t *state_out_pos; + + uint32_t bsBuff; + int32_t bsLive; + + uint32_t blockCRC; + uint32_t combinedCRC; + + int32_t blockNo; + + int32_t nMTF; + + int32_t nInUse; + Bool inUse[256] __attribute__((__aligned__(sizeof(long)))); + uint8_t unseqToSeq[256]; + + int32_t mtfFreq [BZ_MAX_ALPHA_SIZE]; + uint8_t selector [BZ_MAX_SELECTORS]; + uint8_t selectorMtf[BZ_MAX_SELECTORS]; + + uint8_t len[BZ_N_GROUPS][BZ_MAX_ALPHA_SIZE]; + + int32_t sendMTFValues__code [BZ_N_GROUPS][BZ_MAX_ALPHA_SIZE]; + int32_t sendMTFValues__rfreq[BZ_N_GROUPS][BZ_MAX_ALPHA_SIZE]; +#if BZIP2_SPEED >= 5 + uint32_t sendMTFValues__len_pack[BZ_MAX_ALPHA_SIZE][4]; +#endif + int32_t BZ2_hbMakeCodeLengths__heap [BZ_MAX_ALPHA_SIZE + 2]; + int32_t BZ2_hbMakeCodeLengths__weight[BZ_MAX_ALPHA_SIZE * 2]; + int32_t BZ2_hbMakeCodeLengths__parent[BZ_MAX_ALPHA_SIZE * 2]; + + int32_t mainSort__copyStart[256]; + int32_t mainSort__copyEnd[256]; +} EState; + +int32_t BZ2BlockSort(EState*); + +void BZ2CompressBlock(EState*, int); + +void BZ2BsInitWrite(EState*); + +void BZ2HbAssignCodes(int32_t*, uint8_t*, int32_t, int32_t, int32_t); + +void BZ2HbMakeCodeLengths(EState*, uint8_t*, int32_t*, int32_t, int32_t); + diff --git a/Ubiquitous/XiZi/tool/shell/letter-shell/file_ext/bzlib/compress.c b/Ubiquitous/XiZi/tool/shell/letter-shell/file_ext/bzlib/compress.c new file mode 100644 index 0000000..c906b37 --- /dev/null +++ b/Ubiquitous/XiZi/tool/shell/letter-shell/file_ext/bzlib/compress.c @@ -0,0 +1,577 @@ +/* ------------------------------------------------------------------ +This file is part of bzip2/libbzip2, a program and library for +lossless, block-sorting data compression. + +bzip2/libbzip2 version 1.0.4 of 20 December 2006 +Copyright (C) 1996-2006 Julian Seward + +Please read the WARNING, DISCLAIMER and PATENTS sections in the +README file. + +This program is released under the terms of the license contained +in the file LICENSE. +------------------------------------------------------------------ */ + +#include + +#if defined(FS_VFS) && defined(TOOL_SHELL) + +#include +#include "bzlib_private.h" + +#if BZIP2_SPEED >= 5 +# define ALWAYS_INLINE_5 ALWAYS_INLINE +#else +# define ALWAYS_INLINE_5 +#endif + +void BZ2BsInitWrite(EState* s) +{ + s->bsLive = 0; + s->bsBuff = 0; +} + +static void BsFinishWrite(EState* s) +{ + while (s->bsLive > 0) { + *s->posZ++ = (uint8_t)(s->bsBuff >> 24); + s->bsBuff <<= 8; + s->bsLive -= 8; + } +} + +static ALWAYS_INLINE_5 +void bsW(EState* s, int32_t n, uint32_t v) +{ + while (s->bsLive >= 8) { + *s->posZ++ = (uint8_t)(s->bsBuff >> 24); + s->bsBuff <<= 8; + s->bsLive -= 8; + } + s->bsBuff |= (v << (32 - s->bsLive - n)); + s->bsLive += n; +} + +static +ALWAYS_INLINE_5 +void bsW16(EState* s, uint32_t v) +{ + while (s->bsLive >= 8) { + *s->posZ++ = (uint8_t)(s->bsBuff >> 24); + s->bsBuff <<= 8; + s->bsLive -= 8; + } + s->bsBuff |= (v << (16 - s->bsLive)); + s->bsLive += 16; +} + +static inline void bsW1_1(EState* s) +{ + if (s->bsLive >= 8) { + *s->posZ++ = (uint8_t)(s->bsBuff >> 24); + s->bsBuff <<= 8; + s->bsLive -= 8; + } + s->bsBuff |= (1 << (31 - s->bsLive)); + s->bsLive += 1; +} +static +ALWAYS_INLINE_5 +void bsW1_0(EState* s) +{ + if (s->bsLive >= 8) { + *s->posZ++ = (uint8_t)(s->bsBuff >> 24); + s->bsBuff <<= 8; + s->bsLive -= 8; + } + s->bsLive += 1; +} + +static inline void bsPutU16(EState* s, unsigned u) +{ + bsW16(s, u); +} + +static +void bsPutU32(EState* s, unsigned u) +{ + bsW16(s, (u >> 16) & 0xffff); + bsW16(s, u & 0xffff); +} + +static +void MakeMapsE(EState* s) +{ + int i; + unsigned cnt = 0; + for (i = 0; i < 256; i++) { + if (s->inUse[i]) { + s->unseqToSeq[i] = cnt; + cnt++; + } + } + s->nInUse = cnt; +} + +static +#if defined __i386__ +NOINLINE +#endif +int InnerLoop(uint8_t *yy, uint8_t ll_i) +{ + register uint8_t rtmp; + register uint8_t* ryy_j; + rtmp = yy[1]; + yy[1] = yy[0]; + ryy_j = &(yy[1]); + while (ll_i != rtmp) { + register uint8_t rtmp2; + ryy_j++; + rtmp2 = rtmp; + rtmp = *ryy_j; + *ryy_j = rtmp2; + } + yy[0] = rtmp; + return ryy_j - &(yy[0]); +} +static void GenerateMTFValues(EState* s) +{ + uint8_t yy[256]; + int i; + int zPend; + int32_t wr; + + uint32_t* ptr = s->ptr; + + MakeMapsE(s); + + wr = 0; + zPend = 0; + for (i = 0; i <= s->nInUse+1; i++) + s->mtfFreq[i] = 0; + + for (i = 0; i < s->nInUse; i++) + yy[i] = (uint8_t) i; + + for (i = 0; i < s->nblock; i++) { + uint8_t ll_i = ll_i; + int32_t j; + + ASSERTD(wr <= i, "generateMTFValues(1)"); + j = ptr[i] - 1; + if (j < 0) + j += s->nblock; + ll_i = s->unseqToSeq[s->block[j]]; + ASSERTD(ll_i < s->nInUse, "generateMTFValues(2a)"); + + if (yy[0] == ll_i) { + zPend++; + continue; + } + + if (zPend > 0) { + process_zPend: + zPend--; + while (1) { +#if 0 + if (zPend & 1) { + s->mtfv[wr] = BZ_RUNB; wr++; + s->mtfFreq[BZ_RUNB]++; + } else { + s->mtfv[wr] = BZ_RUNA; wr++; + s->mtfFreq[BZ_RUNA]++; + } +#else + unsigned run = zPend & 1; + s->mtfv[wr] = run; + wr++; + s->mtfFreq[run]++; +#endif + zPend -= 2; + if (zPend < 0) + break; + zPend = (unsigned)zPend / 2; + } + if (i < 0) + goto end; + zPend = 0; + } + j = InnerLoop(yy, ll_i); + s->mtfv[wr] = j+1; + wr++; + s->mtfFreq[j+1]++; + } + + i = -1; + if (zPend > 0) + goto process_zPend; + end: + s->mtfv[wr] = s->nInUse+1; + wr++; + s->mtfFreq[s->nInUse+1]++; + + s->nMTF = wr; +} + +#define BZ_LESSER_ICOST 0 +#define BZ_GREATER_ICOST 15 + +static void SendMTFValues(EState* s) +{ + int32_t t, i; + unsigned iter; + unsigned gs; + int32_t alphaSize; + unsigned nSelectors, selCtr; + int32_t nGroups; + +#define CODE sendMTFValues__code +#define RFREQ sendMTFValues__rfreq +#define LEN_PACK sendMTFValues__len_pack + + unsigned cost[BZ_N_GROUPS]; + + uint16_t* mtfv = s->mtfv; + + alphaSize = s->nInUse + 2; + for (t = 0; t < BZ_N_GROUPS; t++) { + unsigned v; + for (v = 0; v < alphaSize; v++) + s->len[t][v] = BZ_GREATER_ICOST; + } + + ASSERTH(s->nMTF > 0, 3001); + nGroups = 2; + nGroups += (s->nMTF >= 200); + nGroups += (s->nMTF >= 600); + nGroups += (s->nMTF >= 1200); + nGroups += (s->nMTF >= 2400); + + { + unsigned nPart, remF; + + nPart = nGroups; + remF = s->nMTF; + gs = 0; + while (nPart > 0) { + unsigned v; + unsigned ge; + unsigned tFreq, aFreq; + + tFreq = remF / nPart; + ge = gs; + aFreq = 0; + while (aFreq < tFreq && ge < alphaSize) { + aFreq += s->mtfFreq[ge++]; + } + ge--; + + if (ge > gs + && nPart != nGroups && nPart != 1 + && ((nGroups - nPart) % 2 == 1) + ) { + aFreq -= s->mtfFreq[ge]; + ge--; + } + + for (v = 0; v < alphaSize; v++) + if (v >= gs && v <= ge) + s->len[nPart-1][v] = BZ_LESSER_ICOST; + else + s->len[nPart-1][v] = BZ_GREATER_ICOST; + + nPart--; + gs = ge + 1; + remF -= aFreq; + } + } + + for (iter = 0; iter < BZ_N_ITERS; iter++) { + for (t = 0; t < nGroups; t++) { + unsigned v; + for (v = 0; v < alphaSize; v++) + s->RFREQ[t][v] = 0; + } + +#if BZIP2_SPEED >= 5 + if (nGroups == 6) { + unsigned v; + for (v = 0; v < alphaSize; v++) { + s->LEN_PACK[v][0] = (s->len[1][v] << 16) | s->len[0][v]; + s->LEN_PACK[v][1] = (s->len[3][v] << 16) | s->len[2][v]; + s->LEN_PACK[v][2] = (s->len[5][v] << 16) | s->len[4][v]; + } + } +#endif + nSelectors = 0; + gs = 0; + while (1) { + unsigned ge; + unsigned bt, bc; + + if (gs >= s->nMTF) + break; + ge = gs + BZ_G_SIZE - 1; + if (ge >= s->nMTF) + ge = s->nMTF-1; + + for (t = 0; t < nGroups; t++) + cost[t] = 0; +#if BZIP2_SPEED >= 5 + if (nGroups == 6 && 50 == ge-gs+1) { + register uint32_t cost01, cost23, cost45; + register uint16_t icv; + cost01 = cost23 = cost45 = 0; +#define BZ_ITER(nn) \ + icv = mtfv[gs+(nn)]; \ + cost01 += s->LEN_PACK[icv][0]; \ + cost23 += s->LEN_PACK[icv][1]; \ + cost45 += s->LEN_PACK[icv][2]; + + BZ_ITER(0); BZ_ITER(1); BZ_ITER(2); BZ_ITER(3); BZ_ITER(4); + BZ_ITER(5); BZ_ITER(6); BZ_ITER(7); BZ_ITER(8); BZ_ITER(9); + BZ_ITER(10); BZ_ITER(11); BZ_ITER(12); BZ_ITER(13); BZ_ITER(14); + BZ_ITER(15); BZ_ITER(16); BZ_ITER(17); BZ_ITER(18); BZ_ITER(19); + BZ_ITER(20); BZ_ITER(21); BZ_ITER(22); BZ_ITER(23); BZ_ITER(24); + BZ_ITER(25); BZ_ITER(26); BZ_ITER(27); BZ_ITER(28); BZ_ITER(29); + BZ_ITER(30); BZ_ITER(31); BZ_ITER(32); BZ_ITER(33); BZ_ITER(34); + BZ_ITER(35); BZ_ITER(36); BZ_ITER(37); BZ_ITER(38); BZ_ITER(39); + BZ_ITER(40); BZ_ITER(41); BZ_ITER(42); BZ_ITER(43); BZ_ITER(44); + BZ_ITER(45); BZ_ITER(46); BZ_ITER(47); BZ_ITER(48); BZ_ITER(49); +#undef BZ_ITER + cost[0] = cost01 & 0xffff; cost[1] = cost01 >> 16; + cost[2] = cost23 & 0xffff; cost[3] = cost23 >> 16; + cost[4] = cost45 & 0xffff; cost[5] = cost45 >> 16; + } else +#endif + { + for (i = gs; i <= ge; i++) { + unsigned icv = mtfv[i]; + for (t = 0; t < nGroups; t++) + cost[t] += s->len[t][icv]; + } + } + bc = cost[0]; + bt = 0; + for (t = 1; t < nGroups; t++) { + if (cost[t] < bc) { + bc = cost[t]; + bt = t; + } + } + s->selector[nSelectors] = bt; + nSelectors++; + +#if BZIP2_SPEED >= 4 + if (nGroups == 6 && 50 == ge-gs+1) { +#define BZ_ITUR(nn) s->RFREQ[bt][mtfv[gs + (nn)]]++ + BZ_ITUR(0); BZ_ITUR(1); BZ_ITUR(2); BZ_ITUR(3); BZ_ITUR(4); + BZ_ITUR(5); BZ_ITUR(6); BZ_ITUR(7); BZ_ITUR(8); BZ_ITUR(9); + BZ_ITUR(10); BZ_ITUR(11); BZ_ITUR(12); BZ_ITUR(13); BZ_ITUR(14); + BZ_ITUR(15); BZ_ITUR(16); BZ_ITUR(17); BZ_ITUR(18); BZ_ITUR(19); + BZ_ITUR(20); BZ_ITUR(21); BZ_ITUR(22); BZ_ITUR(23); BZ_ITUR(24); + BZ_ITUR(25); BZ_ITUR(26); BZ_ITUR(27); BZ_ITUR(28); BZ_ITUR(29); + BZ_ITUR(30); BZ_ITUR(31); BZ_ITUR(32); BZ_ITUR(33); BZ_ITUR(34); + BZ_ITUR(35); BZ_ITUR(36); BZ_ITUR(37); BZ_ITUR(38); BZ_ITUR(39); + BZ_ITUR(40); BZ_ITUR(41); BZ_ITUR(42); BZ_ITUR(43); BZ_ITUR(44); + BZ_ITUR(45); BZ_ITUR(46); BZ_ITUR(47); BZ_ITUR(48); BZ_ITUR(49); +#undef BZ_ITUR + gs = ge + 1; + } else +#endif + { + while (gs <= ge) { + s->RFREQ[bt][mtfv[gs]]++; + gs++; + } + } + } + + for (t = 0; t < nGroups; t++) + BZ2HbMakeCodeLengths(s, &(s->len[t][0]), &(s->RFREQ[t][0]), alphaSize, 17 ); + } + + ASSERTH(nGroups < 8, 3002); + ASSERTH(nSelectors < 32768 && nSelectors <= (2 + (900000 / BZ_G_SIZE)), 3003); + + { + uint8_t pos[BZ_N_GROUPS], ll_i, tmp2, tmp; + + for (i = 0; i < nGroups; i++) + pos[i] = i; + for (i = 0; i < nSelectors; i++) { + unsigned j; + ll_i = s->selector[i]; + j = 0; + tmp = pos[j]; + while (ll_i != tmp) { + j++; + tmp2 = tmp; + tmp = pos[j]; + pos[j] = tmp2; + } + pos[0] = tmp; + s->selectorMtf[i] = j; + } + } + + for (t = 0; t < nGroups; t++) { + unsigned minLen = 32; + unsigned maxLen = 0; + for (i = 0; i < alphaSize; i++) { + if (s->len[t][i] > maxLen) maxLen = s->len[t][i]; + if (s->len[t][i] < minLen) minLen = s->len[t][i]; + } + ASSERTH(!(maxLen > 17), 3004); + ASSERTH(!(minLen < 1), 3005); + BZ2HbAssignCodes(&(s->CODE[t][0]), &(s->len[t][0]), minLen, maxLen, alphaSize); + } + + { + int inUse16 = 0; + for (i = 0; i < 16; i++) { + if (sizeof(long) <= 4) { + inUse16 = inUse16*2 + + ((*(uint32_t*)&(s->inUse[i * 16 + 0]) + | *(uint32_t*)&(s->inUse[i * 16 + 4]) + | *(uint32_t*)&(s->inUse[i * 16 + 8]) + | *(uint32_t*)&(s->inUse[i * 16 + 12])) != 0); + } else { + inUse16 = inUse16*2 + + ((*(uint64_t*)&(s->inUse[i * 16 + 0]) + | *(uint64_t*)&(s->inUse[i * 16 + 8])) != 0); + } + } + + bsW16(s, inUse16); + + inUse16 <<= (sizeof(int)*8 - 16); + for (i = 0; i < 16; i++) { + if (inUse16 < 0) { + unsigned v16 = 0; + unsigned j; + for (j = 0; j < 16; j++) + v16 = v16*2 + s->inUse[i * 16 + j]; + bsW16(s, v16); + } + inUse16 <<= 1; + } + } + + bsW(s, 3, nGroups); + bsW(s, 15, nSelectors); + for (i = 0; i < nSelectors; i++) { + unsigned j; + for (j = 0; j < s->selectorMtf[i]; j++) + bsW1_1(s); + bsW1_0(s); + } + + for (t = 0; t < nGroups; t++) { + unsigned curr = s->len[t][0]; + bsW(s, 5, curr); + for (i = 0; i < alphaSize; i++) { + while (curr < s->len[t][i]) { bsW(s, 2, 2); curr++; } + while (curr > s->len[t][i]) { bsW(s, 2, 3); curr--; } + bsW1_0(s); + } + } + + selCtr = 0; + gs = 0; + while (1) { + unsigned ge; + + if (gs >= s->nMTF) + break; + ge = gs + BZ_G_SIZE - 1; + if (ge >= s->nMTF) + ge = s->nMTF-1; + ASSERTH(s->selector[selCtr] < nGroups, 3006); + +#if 0 + if (nGroups == 6 && 50 == ge-gs+1) { + uint16_t mtfv_i; + uint8_t* s_len_sel_selCtr = &(s->len[s->selector[selCtr]][0]); + int32_t* s_code_sel_selCtr = &(s->CODE[s->selector[selCtr]][0]); +#define BZ_ITAH(nn) \ + mtfv_i = mtfv[gs+(nn)]; \ + bsW(s, s_len_sel_selCtr[mtfv_i], s_code_sel_selCtr[mtfv_i]) + BZ_ITAH(0); BZ_ITAH(1); BZ_ITAH(2); BZ_ITAH(3); BZ_ITAH(4); + BZ_ITAH(5); BZ_ITAH(6); BZ_ITAH(7); BZ_ITAH(8); BZ_ITAH(9); + BZ_ITAH(10); BZ_ITAH(11); BZ_ITAH(12); BZ_ITAH(13); BZ_ITAH(14); + BZ_ITAH(15); BZ_ITAH(16); BZ_ITAH(17); BZ_ITAH(18); BZ_ITAH(19); + BZ_ITAH(20); BZ_ITAH(21); BZ_ITAH(22); BZ_ITAH(23); BZ_ITAH(24); + BZ_ITAH(25); BZ_ITAH(26); BZ_ITAH(27); BZ_ITAH(28); BZ_ITAH(29); + BZ_ITAH(30); BZ_ITAH(31); BZ_ITAH(32); BZ_ITAH(33); BZ_ITAH(34); + BZ_ITAH(35); BZ_ITAH(36); BZ_ITAH(37); BZ_ITAH(38); BZ_ITAH(39); + BZ_ITAH(40); BZ_ITAH(41); BZ_ITAH(42); BZ_ITAH(43); BZ_ITAH(44); + BZ_ITAH(45); BZ_ITAH(46); BZ_ITAH(47); BZ_ITAH(48); BZ_ITAH(49); +#undef BZ_ITAH + gs = ge+1; + } else +#endif + { + uint8_t* s_len_sel_selCtr = &(s->len [s->selector[selCtr]][0]); + int32_t* s_code_sel_selCtr = &(s->CODE[s->selector[selCtr]][0]); + while (gs <= ge) { + bsW(s, + s_len_sel_selCtr[mtfv[gs]], + s_code_sel_selCtr[mtfv[gs]] + ); + gs++; + } + } + selCtr++; + } + ASSERTH(selCtr == nSelectors, 3007); +#undef CODE +#undef RFREQ +#undef LEN_PACK +} + +void BZ2CompressBlock(EState* s, int is_last_block) +{ + int32_t origPtr = origPtr; + + if (s->nblock > 0) { + BZ_FINALISE_CRC(s->blockCRC); + s->combinedCRC = (s->combinedCRC << 1) | (s->combinedCRC >> 31); + s->combinedCRC ^= s->blockCRC; + if (s->blockNo > 1) + s->posZ = s->zbits; + + origPtr = BZ2BlockSort(s); + } + + s->zbits = &((uint8_t*)s->arr2)[s->nblock]; + s->posZ = s->zbits; + s->state_out_pos = s->zbits; + + if (s->blockNo == 1) { + BZ2BsInitWrite(s); + bsPutU32(s, BZ_HDR_BZH0 + s->blockSize100k); + } + + if (s->nblock > 0) { + bsPutU32(s, 0x31415926); + bsPutU16(s, 0x5359); + + bsPutU32(s, s->blockCRC); + + bsW1_0(s); + + bsW(s, 24, origPtr); + GenerateMTFValues(s); + SendMTFValues(s); + } + + if (is_last_block) { + bsPutU32(s, 0x17724538); + bsPutU16(s, 0x5090); + bsPutU32(s, s->combinedCRC); + BsFinishWrite(s); + } +} + +#endif diff --git a/Ubiquitous/XiZi/tool/shell/letter-shell/file_ext/bzlib/huffman.c b/Ubiquitous/XiZi/tool/shell/letter-shell/file_ext/bzlib/huffman.c new file mode 100644 index 0000000..7debfb1 --- /dev/null +++ b/Ubiquitous/XiZi/tool/shell/letter-shell/file_ext/bzlib/huffman.c @@ -0,0 +1,179 @@ +/* ------------------------------------------------------------------ +This file is part of bzip2/libbzip2, a program and library for +lossless, block-sorting data compression. + +bzip2/libbzip2 version 1.0.4 of 20 December 2006 +Copyright (C) 1996-2006 Julian Seward + +Please read the WARNING, DISCLAIMER and PATENTS sections in the +README file. + +This program is released under the terms of the license contained +in the file LICENSE. +------------------------------------------------------------------ */ + +#include + +#if defined(FS_VFS) && defined(TOOL_SHELL) + +#include "bzlib_private.h" + +#define WEIGHTOF(zz0) ((zz0) & 0xffffff00) +#define DEPTHOF(zz1) ((zz1) & 0x000000ff) +#define MYMAX(zz2,zz3) ((zz2) > (zz3) ? (zz2) : (zz3)) + +#define ADDWEIGHTS(zw1,zw2) \ + (WEIGHTOF(zw1)+WEIGHTOF(zw2)) | \ + (1 + MYMAX(DEPTHOF(zw1),DEPTHOF(zw2))) + +#define UPHEAP(z) { \ + int32_t zz, tmp; \ + zz = z; \ + tmp = HEAP[zz]; \ + while (WEIGHT[tmp] < WEIGHT[HEAP[zz >> 1]]) { \ + HEAP[zz] = HEAP[zz >> 1]; \ + zz >>= 1; \ + } \ + HEAP[zz] = tmp; \ + } + +#if BZIP2_SPEED >= 1 + +#define DOWNHEAP1(heap, weight, Heap) { \ + int32_t zz, yy, tmp; \ + zz = 1; \ + tmp = heap[zz]; \ + while (1) { \ + yy = zz << 1; \ + if (yy > nHeap) \ + break; \ + if (yy < nHeap \ + && weight[heap[yy+1]] < weight[heap[yy]]) \ + yy++; \ + if (weight[tmp] < weight[heap[yy]]) \ + break; \ + heap[zz] = heap[yy]; \ + zz = yy; \ + } \ + heap[zz] = tmp; \ + } + +#else + +static void DOWNHEAP1(int32_t *heap, int32_t *weight, int32_t nHeap) +{ + int32_t zz, yy, tmp; + zz = 1; + tmp = heap[zz]; + while (1) { + yy = zz << 1; + if (yy > nHeap) + break; + if (yy < nHeap + && weight[heap[yy + 1]] < weight[heap[yy]]) + yy++; + if (weight[tmp] < weight[heap[yy]]) + break; + heap[zz] = heap[yy]; + zz = yy; + } + heap[zz] = tmp; +} + +#endif + +void BZ2HbMakeCodeLengths(EState *s, + uint8_t *len, + int32_t *freq, + int32_t alphaSize, + int32_t maxLen) +{ + int32_t nNodes, nHeap, n1, n2, i, j, k; + Bool tooLong; + +#define HEAP (s->BZ2_hbMakeCodeLengths__heap) +#define WEIGHT (s->BZ2_hbMakeCodeLengths__weight) +#define PARENT (s->BZ2_hbMakeCodeLengths__parent) + + for (i = 0; i < alphaSize; i++) + WEIGHT[i+1] = (freq[i] == 0 ? 1 : freq[i]) << 8; + + while (1) { + nNodes = alphaSize; + nHeap = 0; + + HEAP[0] = 0; + WEIGHT[0] = 0; + PARENT[0] = -2; + + for (i = 1; i <= alphaSize; i++) { + PARENT[i] = -1; + nHeap++; + HEAP[nHeap] = i; + UPHEAP(nHeap); + } + + ASSERTH(nHeap < (BZ_MAX_ALPHA_SIZE+2), 2001); + + while (nHeap > 1) { + n1 = HEAP[1]; HEAP[1] = HEAP[nHeap]; nHeap--; DOWNHEAP1(HEAP, WEIGHT, nHeap); + n2 = HEAP[1]; HEAP[1] = HEAP[nHeap]; nHeap--; DOWNHEAP1(HEAP, WEIGHT, nHeap); + nNodes++; + PARENT[n1] = PARENT[n2] = nNodes; + WEIGHT[nNodes] = ADDWEIGHTS(WEIGHT[n1], WEIGHT[n2]); + PARENT[nNodes] = -1; + nHeap++; + HEAP[nHeap] = nNodes; + UPHEAP(nHeap); + } + + ASSERTH(nNodes < (BZ_MAX_ALPHA_SIZE * 2), 2002); + + tooLong = FALSE; + for (i = 1; i <= alphaSize; i++) { + j = 0; + k = i; + while (PARENT[k] >= 0) { + k = PARENT[k]; + j++; + } + len[i-1] = j; + if (j > maxLen) + tooLong = TRUE; + } + + if (!tooLong) + break; + + for (i = 1; i <= alphaSize; i++) { + j = WEIGHT[i] >> 8; + j = 1 + (j / 2); + WEIGHT[i] = j << 8; + } + } +#undef HEAP +#undef WEIGHT +#undef PARENT +} + +void BZ2HbAssignCodes(int32_t *code, + uint8_t *length, + int32_t minLen, + int32_t maxLen, + int32_t alphaSize) +{ + int32_t n, vec, i; + + vec = 0; + for (n = minLen; n <= maxLen; n++) { + for (i = 0; i < alphaSize; i++) { + if (length[i] == n) { + code[i] = vec; + vec++; + } + } + vec <<= 1; + } +} + +#endif diff --git a/Ubiquitous/XiZi/tool/shell/letter-shell/file_ext/gunzip.c b/Ubiquitous/XiZi/tool/shell/letter-shell/file_ext/gunzip.c new file mode 100644 index 0000000..89fb017 --- /dev/null +++ b/Ubiquitous/XiZi/tool/shell/letter-shell/file_ext/gunzip.c @@ -0,0 +1,1025 @@ +/* + * Copyright (c) 2020 AIIT XUOS Lab + * XiUOS is licensed under Mulan PSL v2. + * You can use this software according to the terms and conditions of the Mulan PSL v2. + * You may obtain a copy of Mulan PSL v2 at: + * http://license.coscl.org.cn/MulanPSL2 + * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, + * EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, + * MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. + * See the Mulan PSL v2 for more details. +*/ + +#include + +#if defined(FS_VFS) && defined(TOOL_SHELL) + +#include +#include +#include +#include +#include +#include +#include "utility.h" + +#define USE_HEAP_MEM + +struct globals { + uint32_t crc32; + + int in_fd; + int out_fd; + size_t outcnt; + size_t outbuf_cnt; + + unsigned char window[GUNZIP_WSIZE]; + unsigned char bytebuffer[GUNZIP_BYTEBUFFER_MAX]; + uint32_t bytebuffer_offset; + uint32_t bytebuffer_size; + uint32_t to_read; + + uint32_t bi_buf; + uint32_t bi_valid; + + + uint32_t inflate_codes_ml; + uint32_t inflate_codes_md; + uint32_t inflate_codes_bb; + uint32_t inflate_codes_k; + uint32_t inflate_codes_w; + uint32_t inflate_codes_bl; + uint32_t inflate_codes_bd; + uint32_t inflate_codes_nn; + uint32_t inflate_codes_dd; + huft_t *inflate_codes_tl; + huft_t *inflate_codes_td; + + int resume_copy; + + + int method; + int need_another_block; + int eof; + + uint32_t inflate_stored_n; + uint32_t inflate_stored_b; + uint32_t inflate_stored_k; + uint32_t inflate_stored_w; +}; + +#ifdef USE_HEAP_MEM +static struct globals *glbp; +#define GLB (*glbp) +#else +struct globals GLB; +#endif + +static const uint16_t mask_bits[] = { + 0x0000, 0x0001, 0x0003, 0x0007, 0x000f, 0x001f, 0x003f, 0x007f, 0x00ff, + 0x01ff, 0x03ff, 0x07ff, 0x0fff, 0x1fff, 0x3fff, 0x7fff, 0xffff +}; + +static const uint16_t cplens[] = { + 3, 4, 5, 6, 7, 8, 9, 10, 11, 13, 15, 17, 19, 23, 27, 31, 35, 43, 51, 59, + 67, 83, 99, 115, 131, 163, 195, 227, 258, 0, 0 +}; + +static const uint8_t cplext[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 2, 2, 2, 2, 3, 3, 3, 3, 4, 4, 4, 4, 5, + 5, 5, 5, 0, 99, 99 +}; + +static const uint16_t cpdist[] = { + 1, 2, 3, 4, 5, 7, 9, 13, 17, 25, 33, 49, 65, 97, 129, 193, 257, 385, 513, + 769, 1025, 1537, 2049, 3073, 4097, 6145, 8193, 12289, 16385, 24577 +}; + + +static const uint8_t cpdext[] = { + 0, 0, 0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 10, 10, + 11, 11, 12, 12, 13, 13 +}; + +static const uint8_t border[] = { + 16, 17, 18, 0, 8, 7, 9, 6, 10, 5, 11, 4, 12, 3, 13, 2, 14, 1, 15 +}; + +static void InitInflateCodes(uint32_t bl, uint32_t bd) +{ + GLB.inflate_codes_bl = bl; + GLB.inflate_codes_bd = bd; + GLB.inflate_codes_bb = GLB.bi_buf; + GLB.inflate_codes_k = GLB.bi_valid; + GLB.inflate_codes_w = GLB.outbuf_cnt; + GLB.inflate_codes_ml = mask_bits[bl]; + GLB.inflate_codes_md = mask_bits[bd]; +} + +static int InflateCodes(); + +static void HuftFree(huft_t *p) +{ + huft_t *q; + + while (p) { + q = (--p)->t; + free(p); + p = q; + } +} + +static int HuftBuild(const uint32_t *b, const uint32_t n, + const uint32_t s, const uint16_t *d, + const unsigned char *e, huft_t **t, uint32_t *m) +{ + uint32_t a; + uint32_t c[BMAX + 1]; + uint32_t eob_len; + uint32_t f; + int g; + int htl; + uint32_t i; + uint32_t j; + int k; + const uint32_t *p; + huft_t *q; + huft_t r; + huft_t *u[BMAX]; + uint32_t v[NMAX + 1]; + int ws[BMAX + 1]; + int w; + uint32_t x[BMAX + 1]; + uint32_t *xp; + int y; + uint32_t z; + + eob_len = n > 256 ? b[256] : BMAX; + + *t = NULL; + + memset(c, 0, sizeof(c)); + p = b; + i = n; + do { + c[*p]++; + p++; + } while (--i); + if (c[0] == n) { + q = malloc(3 * sizeof(*q)); + memset(q, 0, 3 * sizeof(*q)); + q[1].e = 99; + q[1].b = 1; + q[2].e = 99; + q[2].b = 1; + *t = q + 1; + *m = 1; + return 0; + } + + for (j = 1; (j <= BMAX) && (c[j] == 0); j++) + continue; + k = j; + for (i = BMAX; (c[i] == 0) && i; i--) + continue; + g = i; + *m = (*m < j) ? j : ((*m > i) ? i : *m); + + for (y = 1 << j; j < i; j++, y <<= 1) { + y -= c[j]; + if (y < 0) + return -1; + } + y -= c[i]; + if (y < 0) + return -1; + c[i] += y; + + x[1] = j = 0; + p = c + 1; + xp = x + 2; + while (--i) { + j += *p++; + *xp++ = j; + } + + memset(v, 0xff, sizeof(v)); + p = b; + i = 0; + do { + j = *p++; + if (j != 0) { + v[x[j]++] = i; + } + } while (++i < n); + + x[0] = i = 0; + p = v; + htl = -1; + w = ws[0] = 0; + u[0] = NULL; + q = NULL; + z = 0; + + for (; k <= g; k++) { + a = c[k]; + while (a--) { + + while (k > ws[htl + 1]) { + w = ws[++htl]; + + z = g - w; + z = z > *m ? *m : z; + j = k - w; + f = 1 << j; + if (f > a + 1) { + f -= a + 1; + xp = c + k; + while (++j < z) { + f <<= 1; + if (f <= *++xp) { + break; + } + f -= *xp; + } + } + j = (w + j > eob_len && w < eob_len) ? eob_len - w : j; + z = 1 << j; + ws[htl+1] = w + j; + + q = malloc((z + 1) * sizeof(huft_t)); + memset(q, 0, (z + 1) * sizeof(huft_t)); + *t = q + 1; + t = &(q->t); + u[htl] = ++q; + + + if (htl) { + x[htl] = i; + r.b = (unsigned char)(w - ws[htl - 1]); + r.e = (unsigned char)(16 + j); + r.t = q; + j = (i & ((1 << w) - 1)) >> ws[htl - 1]; + u[htl - 1][j] = r; + } + } + + r.b = (unsigned char)(k - w); + if (*p == 0xffffffff) { + r.e = 99; + } else if (*p < s) { + r.e = (unsigned char)(*p < 256 ? 16 : 15); + r.n = (unsigned short)(*p++); + } else { + r.e = (unsigned char)e[*p - s]; + r.n = d[*p++ - s]; + } + + f = 1 << (k - w); + for (j = i >> w; j < z; j += f) { + q[j] = r; + } + + for (j = 1 << (k - 1); i & j; j >>= 1) { + i ^= j; + } + i ^= j; + + while ((i & ((1 << w) - 1)) != x[htl]) { + w = ws[--htl]; + } + } + } + *m = ws[1]; + + return y != 0 && g != 1 ? -1 : 0; +} + +int FillBitBuffer(uint32_t *bitbuffer, uint32_t *current_len, + uint32_t required_len) +{ + while (*current_len < required_len) { + if (GLB.bytebuffer_offset >= GLB.bytebuffer_size) { + + uint32_t size = GUNZIP_BYTEBUFFER_MAX - 4; + if (GLB.to_read >= 0 && GLB.to_read < size) + size = GLB.to_read; + + GLB.bytebuffer_size = read(GLB.in_fd, &GLB.bytebuffer[4], size); + if (GLB.bytebuffer_size == 0) { + + return -1; + } + if (GLB.to_read >= 0) + GLB.to_read -= GLB.bytebuffer_size; + GLB.bytebuffer_size += 4; + GLB.bytebuffer_offset = 4; + } + *bitbuffer |= (uint32_t)GLB.bytebuffer[GLB.bytebuffer_offset] + << *current_len; + GLB.bytebuffer_offset++; + *current_len += 8; + } + + return 0; +} + + +static int InflateBlock() +{ + uint32_t ll[286 + 30]; + uint32_t t; + uint32_t b; + uint32_t k; + + b = GLB.bi_buf; + k = GLB.bi_valid; + + if (FillBitBuffer(&b, &k, 1) < 0) + return -1; + GLB.eof = b & 1; + b >>= 1; + k -= 1; + + + if (FillBitBuffer(&b, &k, 2) < 0) + return -1; + t = b & 0x3; + b >>= 2; + k -= 2; + + GLB.bi_buf = b; + GLB.bi_valid = k; + + switch (t) { + case 0: { + + uint32_t n; + uint32_t b_stored; + uint32_t k_stored; + + b_stored = GLB.bi_buf; + k_stored = GLB.bi_valid; + + n = k_stored & 0x7; + b_stored >>= n; + k_stored -= n; + + if (FillBitBuffer(&b_stored, &k_stored, 16) < 0) + return -1; + n = b_stored & 0xffff; + b_stored >>= 16; + k_stored -= 16; + + if (FillBitBuffer(&b_stored, &k_stored, 16) < 0) + return -1; + if (n != ((~b_stored) & 0xffff)) + return -1; + b_stored >>= 16; + k_stored -= 16; + + GLB.inflate_stored_n = n; + GLB.inflate_stored_b = b_stored; + GLB.inflate_stored_k = k_stored; + + return STORED; + } + case 1: { + + int i; + uint32_t bl; + uint32_t bd; + + for (i = 0; i < 144; i++) + ll[i] = 8; + for (; i < 256; i++) + ll[i] = 9; + for (; i < 280; i++) + ll[i] = 7; + for (; i < 288; i++) + ll[i] = 8; + bl = 7; + HuftBuild(ll, 288, 257, cplens, cplext, + &GLB.inflate_codes_tl, &bl); + + for (i = 0; i < 30; i++) + ll[i] = 5; + bd = 5; + HuftBuild(ll, 30, 0, cpdist, cpdext, + &GLB.inflate_codes_td, &bd); + InitInflateCodes(bl, bd); + + return CODES; + } + case 2: { + + int dbits = 6; + int lbits = 9; + + huft_t *td; + uint32_t i; + uint32_t j; + uint32_t l; + uint32_t m; + uint32_t n; + uint32_t bl; + uint32_t bd; + uint32_t nb; + uint32_t nl; + uint32_t nd; + uint32_t b_dynamic; + uint32_t k_dynamic; + + b_dynamic = GLB.bi_buf; + k_dynamic = GLB.bi_valid; + + + if (FillBitBuffer(&b_dynamic, &k_dynamic, 5) < 0) + return -1; + nl = 257 + (b_dynamic & 0x1f); + b_dynamic >>= 5; + k_dynamic -= 5; + + if (FillBitBuffer(&b_dynamic, &k_dynamic, 5) < 0) + return -1; + nd = 1 + (b_dynamic & 0x1f); + b_dynamic >>= 5; + k_dynamic -= 5; + + if (FillBitBuffer(&b_dynamic, &k_dynamic, 4) < 0) + return -1; + nb = 4 + (b_dynamic & 0xf); + b_dynamic >>= 4; + k_dynamic -= 4; + + if (nl > 286 || nd > 30) + return -1; + + for (j = 0; j < nb; j++) { + if (FillBitBuffer(&b_dynamic, &k_dynamic, 3) < 0) + return -1; + ll[border[j]] = b_dynamic & 0x7; + b_dynamic >>= 3; + k_dynamic -= 3; + } + for (; j < 19; j++) + ll[border[j]] = 0; + + bl = 7; + i = HuftBuild(ll, 19, 19, NULL, NULL, + &GLB.inflate_codes_tl, &bl); + if (i < 0) + return -1; + + n = nl + nd; + m = mask_bits[bl]; + i = l = 0; + while (i < n) { + if (FillBitBuffer(&b_dynamic, &k_dynamic, bl) < 0) + return -1; + td = GLB.inflate_codes_tl + (b_dynamic & m); + j = td->b; + b_dynamic >>= j; + k_dynamic -= j; + j = td->n; + if (j < 16) { + ll[i++] = l = j; + } else if (j == 16) { + if (FillBitBuffer(&b_dynamic, &k_dynamic, 2) < 0) + return -1; + j = 3 + (b_dynamic & 3); + b_dynamic >>= 2; + k_dynamic -= 2; + if (i + j > n) + return -1; + while (j--) { + ll[i++] = l; + } + } else if (j == 17) { + if (FillBitBuffer(&b_dynamic, &k_dynamic, 3) < 0) + return -1; + j = 3 + (b_dynamic & 7); + b_dynamic >>= 3; + k_dynamic -= 3; + if (i + j > n) + return -1; + while (j--) { + ll[i++] = 0; + } + l = 0; + } else { + if (FillBitBuffer(&b_dynamic, &k_dynamic, 7) < 0) + return -1; + j = 11 + ((unsigned) b_dynamic & 0x7f); + b_dynamic >>= 7; + k_dynamic -= 7; + if ((unsigned) i + j > n) + return -1; + while (j--) + ll[i++] = 0; + l = 0; + } + } + + HuftFree(GLB.inflate_codes_tl); + + GLB.bi_buf = b_dynamic; + GLB.bi_valid = k_dynamic; + + bl = lbits; + i = HuftBuild(ll, nl, 257, cplens, cplext, + &GLB.inflate_codes_tl, &bl); + if (i < 0) + return -1; + bd = dbits; + i = HuftBuild(ll + nl, nd, 0, cpdist, cpdext, + &GLB.inflate_codes_td, &bd); + if (i < 0) + return -1; + + InitInflateCodes(bl, bd); + + return CODES; + } + default: + return -1; + } +} + +static int InflateStored() +{ + while (GLB.inflate_stored_n--) { + if (FillBitBuffer(&GLB.inflate_stored_b, + &GLB.inflate_stored_k, 8) < 0) + return -1; + GLB.window[GLB.inflate_stored_w++] = + (unsigned char)GLB.inflate_stored_b; + GLB.inflate_stored_b >>= 8; + GLB.inflate_stored_k -= 8; + if (GLB.inflate_stored_w == GUNZIP_WSIZE) { + GLB.outbuf_cnt = GLB.inflate_stored_w; + GLB.inflate_stored_w = 0; + return 1; + } + } + + GLB.outbuf_cnt = GLB.inflate_stored_w; + GLB.bi_buf = GLB.inflate_stored_b; + GLB.bi_valid = GLB.inflate_stored_k; + return 0; +} + +static int InflateCodes() +{ + unsigned e; + huft_t *t; + + if (GLB.resume_copy) + goto do_copy; + + while (1) { + if (FillBitBuffer(&GLB.inflate_codes_bb, + &GLB.inflate_codes_k,GLB.inflate_codes_bl) < 0) + return -1; + t = GLB.inflate_codes_tl + + (GLB.inflate_codes_bb & GLB.inflate_codes_ml); + e = t->e; + if (e > 16) + do { + if (e == 99) + return -1; + GLB.inflate_codes_bb >>= t->b; + GLB.inflate_codes_k -= t->b; + e -= 16; + if (FillBitBuffer(&GLB.inflate_codes_bb, + &GLB.inflate_codes_k, e) < 0) + return -1; + t = t->t + (GLB.inflate_codes_bb & mask_bits[e]); + e = t->e; + } while (e > 16); + GLB.inflate_codes_bb >>= t->b; + GLB.inflate_codes_k -= t->b; + if (e == 16) { + GLB.window[GLB.inflate_codes_w++] = (unsigned char)t->n; + if (GLB.inflate_codes_w == GUNZIP_WSIZE) { + GLB.outbuf_cnt = GLB.inflate_codes_w; + GLB.inflate_codes_w = 0; + return 1; + } + } else { + if (e == 15) + break; + + if (FillBitBuffer(&GLB.inflate_codes_bb, + &GLB.inflate_codes_k, e) < 0) + return -1; + GLB.inflate_codes_nn = t->n + + (GLB.inflate_codes_bb & mask_bits[e]); + GLB.inflate_codes_bb >>= e; + GLB.inflate_codes_k -= e; + + if (FillBitBuffer(&GLB.inflate_codes_bb, + &GLB.inflate_codes_k, GLB.inflate_codes_bd) < 0) + return -1; + t = GLB.inflate_codes_td + + (GLB.inflate_codes_bb & GLB.inflate_codes_md); + e = t->e; + if (e > 16) + do { + if (e == 99) + return -1; + GLB.inflate_codes_bb >>= t->b; + GLB.inflate_codes_k -= t->b; + e -= 16; + if (FillBitBuffer(&GLB.inflate_codes_bb, + &GLB.inflate_codes_k, e) < 0) + return -1; + t = t->t + (GLB.inflate_codes_bb & mask_bits[e]); + e = t->e; + } while (e > 16); + GLB.inflate_codes_bb >>= t->b; + GLB.inflate_codes_k -= t->b; + if (FillBitBuffer(&GLB.inflate_codes_bb, + &GLB.inflate_codes_k, e) < 0) + return -1; + GLB.inflate_codes_dd = GLB.inflate_codes_w - t->n - + (GLB.inflate_codes_bb & mask_bits[e]); + GLB.inflate_codes_bb >>= e; + GLB.inflate_codes_k -= e; + +do_copy: + do { + uint32_t delta; + + GLB.inflate_codes_dd &= GUNZIP_WSIZE - 1; + e = GUNZIP_WSIZE - + (GLB.inflate_codes_dd > GLB.inflate_codes_w ? + GLB.inflate_codes_dd : GLB.inflate_codes_w); + delta = GLB.inflate_codes_w > GLB.inflate_codes_dd ? + GLB.inflate_codes_w - GLB.inflate_codes_dd : + GLB.inflate_codes_dd - GLB.inflate_codes_w; + if (e > GLB.inflate_codes_nn) + e = GLB.inflate_codes_nn; + GLB.inflate_codes_nn -= e; + + if (delta >= e) { + memcpy(GLB.window + GLB.inflate_codes_w, + GLB.window + GLB.inflate_codes_dd, e); + GLB.inflate_codes_w += e; + GLB.inflate_codes_dd += e; + } else { + do { + GLB.window[GLB.inflate_codes_w++] = + GLB.window[GLB.inflate_codes_dd++]; + } while (--e); + } + if (GLB.inflate_codes_w == GUNZIP_WSIZE) { + GLB.outbuf_cnt = GLB.inflate_codes_w; + GLB.resume_copy = (GLB.inflate_codes_nn != 0); + + GLB.inflate_codes_w = 0; + return 1; + } + } while (GLB.inflate_codes_nn); + GLB.resume_copy = 0; + } + } + + GLB.outbuf_cnt = GLB.inflate_codes_w; + GLB.bi_buf = GLB.inflate_codes_bb; + GLB.bi_valid = GLB.inflate_codes_k; + + HuftFree(GLB.inflate_codes_tl); + HuftFree(GLB.inflate_codes_td); + GLB.inflate_codes_tl = NULL; + GLB.inflate_codes_td = NULL; + + return 0; +} + +static void UpdateCrc32(unsigned char *buf, size_t len) +{ + for (int i = 0; i < len; i++) { + GLB.crc32 = GLB.crc32 ^ buf[i]; + for (int j = 0; j < 8; j++) + GLB.crc32 = (GLB.crc32 >> 1) ^ + (0xedb88320 & -(GLB.crc32 & 1)); + } +} + +static int InflateGetNextWindow() +{ + while (1) { + int ret; + + if (GLB.need_another_block) { + if (GLB.eof) { + UpdateCrc32(GLB.window, GLB.outbuf_cnt); + GLB.eof = 0; + return 0; + } + GLB.method = InflateBlock(); + GLB.need_another_block = 0; + } + + switch (GLB.method) { + case STORED: + ret = InflateStored(); + break; + case CODES: + ret = InflateCodes(); + break; + default: + return -1; + } + if (ret < 0) + return -1; + if (ret == 1) { + UpdateCrc32(GLB.window, GLB.outbuf_cnt); + return 1; + } + GLB.need_another_block = 1; + } +} + +static inline int FlushOutbuf() +{ + int written_size = write(GLB.out_fd, GLB.window, GLB.outbuf_cnt); + int ret = written_size == GLB.outbuf_cnt ? 0 : -1; + GLB.outcnt += written_size; + GLB.outbuf_cnt = 0; + + return ret; +} + +static int inflate() +{ + + GLB.crc32 = ~0; + GLB.outcnt = 0; + GLB.outbuf_cnt = 0; + GLB.method = -1; + GLB.need_another_block = 1; + GLB.resume_copy = 0; + GLB.bi_buf = 0; + GLB.bi_valid = 0; + + while (1) { + int ret = InflateGetNextWindow(); + if (ret < 0) + return -1; + if (FlushOutbuf() < 0) + return -1; + if (ret == 0) + break; + } + + if (GLB.bi_valid >= 8) { + GLB.bytebuffer_offset--; + GLB.bytebuffer[GLB.bytebuffer_offset] = GLB.bi_buf & 0xff; + GLB.bi_buf >>= 8; + GLB.bi_valid -= 8; + } + + return 0; +} + +static int FillByteBuffer(int n) +{ + int count = GLB.bytebuffer_size - GLB.bytebuffer_offset; + + if (count < n) { + memmove(GLB.bytebuffer, + &GLB.bytebuffer[GLB.bytebuffer_offset], count); + GLB.bytebuffer_offset = 0; + GLB.bytebuffer_size = read(GLB.in_fd, + &GLB.bytebuffer[count], GUNZIP_BYTEBUFFER_MAX - count); + if ((int)GLB.bytebuffer_size < 0) + return -1; + GLB.bytebuffer_size += count; + if (GLB.bytebuffer_size < n) + return -1; + } + + return 0; +} + +static uint16_t BufferRead16() +{ + uint16_t res; + + res = GLB.bytebuffer[GLB.bytebuffer_offset]; + res |= GLB.bytebuffer[GLB.bytebuffer_offset + 1] << 8; + GLB.bytebuffer_offset += 2; + + return res; +} + +static uint32_t BufferRead32() +{ + uint32_t res; + + res = GLB.bytebuffer[GLB.bytebuffer_offset]; + res |= (uint32_t)GLB.bytebuffer[GLB.bytebuffer_offset + 1] << 8; + res |= (uint32_t)GLB.bytebuffer[GLB.bytebuffer_offset + 2] << 16; + res |= (uint32_t)GLB.bytebuffer[GLB.bytebuffer_offset + 3] << 24; + GLB.bytebuffer_offset += 4; + + return res; +} + +int InflateUnzip(int zip_fd, int dst_fd, uint32_t cmpsize, + uint32_t ucmpsize, uint32_t crc32) { + int ret = 0; + +#ifdef USE_HEAP_MEM + glbp = malloc(sizeof(struct globals)); + if (glbp == NULL) { + KPrintf("Memory too small\n"); + return -1; + } +#endif + memset(&GLB, 0, sizeof(struct globals)); + GLB.to_read = cmpsize; + GLB.bytebuffer_offset = 4; + GLB.in_fd = zip_fd; + GLB.out_fd = dst_fd; + + if ((ret = inflate()) < 0) + goto free_glbp; + ret = ucmpsize == GLB.outcnt && ~crc32 == GLB.crc32; + +free_glbp: +#ifdef USE_HEAP_MEM + free(glbp); +#endif + + return ret; +} + +static int GunzipCheckFooter() +{ + int crc32, length; + + if (FillByteBuffer(8) < 0) + return -1; + + crc32 = BufferRead32(); + length = BufferRead32(); + if (~GLB.crc32 != crc32 || length != GLB.outcnt) + return -1; + + return 0; +} + +static int GunzipCheckHeader() +{ + GzipHdr_t hdr; + + if (FillByteBuffer(8) < 0) + return -1; + memcpy(&hdr, &GLB.bytebuffer[GLB.bytebuffer_offset], 8); + GLB.bytebuffer_offset += 8; + + if (hdr.gz_method != 8) + return -1; + + if (hdr.flags & 0x04) { + uint16_t extra_len; + + extra_len = BufferRead16(); + if (FillByteBuffer(extra_len) < 0) + return -1; + GLB.bytebuffer_offset += extra_len; + } + + if (hdr.flags & 0x18) { + while (1) { + do { + if (FillByteBuffer(1) < 0) + return -1; + } while (GLB.bytebuffer[GLB.bytebuffer_offset++] != 0); + if ((hdr.flags & 0x18) != 0x18) + break; + hdr.flags &= ~0x18; + } + } + + if (hdr.flags & 0x02) { + if (FillByteBuffer(2) < 0) + return -1; + GLB.bytebuffer_offset += 2; + } + + return 0; +} + +static int GunzipCheckMagic() +{ + uint16_t magic; + + if (FillByteBuffer(2) < 0) + return -1; + + magic = BufferRead16(); + if (magic != 0x8b1f) + return -1; + + return 0; +} + +int GzipDecompress(char *file_name) +{ + int ret = 0; + +#ifdef USE_HEAP_MEM + glbp = malloc(sizeof(struct globals)); + if (glbp == NULL) { + KPrintf("Memory too small\n"); + return -1; + } +#endif + memset(&GLB, 0, sizeof(struct globals)); + GLB.to_read = -1; + + if ((GLB.in_fd = open(file_name, O_RDONLY)) < 0) { + ret = -1; + goto free_glbp; + } + + if (TruncateExtension(file_name, ".gz") < 0) { + KPrintf("Invalid extension: %s\n", file_name); + ret = -1; + goto close_in_fd; + } + + if ((GLB.out_fd = open(file_name, O_WRONLY | O_CREAT | O_TRUNC)) < 0) { + ret = -1; + goto close_in_fd; + } + strcat(file_name, ".gz"); + + if (GunzipCheckMagic() < 0) { + KPrintf("Invalid magic number: %s\n", file_name); + ret = -1; + goto close_out_fd; + } + +again: + if (GunzipCheckHeader() < 0) { + KPrintf("Invalid header: %s\n", file_name); + ret = -1; + goto close_out_fd; + } + + if ((inflate()) < 0) { + ret = -1; + goto close_out_fd; + } + + if (GunzipCheckFooter() < 0) { + KPrintf("Invalid footer (checksum or length): %s\n", file_name); + ret = -1; + } + + if (GunzipCheckMagic() == 0) + goto again; + +close_out_fd: + close(GLB.out_fd); +close_in_fd: + close(GLB.in_fd); +free_glbp: +#ifdef USE_HEAP_MEM + free(glbp); +#endif + + return ret; +} + +static void GunzipPrintUsage() +{ + KPrintf("Usage: gunzip [FILEs]...\n"); + KPrintf("File names MUST end with the .gz extension\n"); +} + +int gunzip(int argc, char **argv) +{ + int ret = 0; + + if (argc < 2) { + GunzipPrintUsage(); + return 0; + } + + for (int i = 1; i < argc; i++) + if (GzipDecompress(argv[i]) < 0) + ret = -1; + + if (ret < 0) + KPrintf("Failed to extract (some) file(s)\n"); + + return 0; +} + + +#endif diff --git a/Ubiquitous/XiZi/tool/shell/letter-shell/file_ext/gunzip.h b/Ubiquitous/XiZi/tool/shell/letter-shell/file_ext/gunzip.h new file mode 100644 index 0000000..6c5c52b --- /dev/null +++ b/Ubiquitous/XiZi/tool/shell/letter-shell/file_ext/gunzip.h @@ -0,0 +1,48 @@ +/* + * Copyright (c) 2020 AIIT XUOS Lab + * XiUOS is licensed under Mulan PSL v2. + * You can use this software according to the terms and conditions of the Mulan PSL v2. + * You may obtain a copy of Mulan PSL v2 at: + * http://license.coscl.org.cn/MulanPSL2 + * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, + * EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, + * MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. + * See the Mulan PSL v2 for more details. +*/ + +#ifndef __INC_GUNZIP_H__ +#define __INC_GUNZIP_H__ + +typedef struct GzipHdr { + uint8_t gz_method; + uint8_t flags; + uint32_t mtime; + uint8_t extra_flags; + uint8_t os_flags; +} __attribute__((packed)) GzipHdr_t; + + +typedef struct huft { + unsigned char e; + unsigned char b; + union { + uint16_t n; + struct huft *t; + }; +} huft_t; + +#define GUNZIP_WSIZE (1 << 15) +#define GUNZIP_BYTEBUFFER_MAX (1 << 14) + +#define BMAX 16 +#define NMAX 288 + +enum methods { + STORED = 1, + CODES, +}; + +int InflateUnzip(int zip_fd, int dst_fd, uint32_t cmpsize, + uint32_t ucmpsize, uint32_t crc32); + +#endif diff --git a/Ubiquitous/XiZi/tool/shell/letter-shell/file_ext/gzip.c b/Ubiquitous/XiZi/tool/shell/letter-shell/file_ext/gzip.c new file mode 100644 index 0000000..961754c --- /dev/null +++ b/Ubiquitous/XiZi/tool/shell/letter-shell/file_ext/gzip.c @@ -0,0 +1,1020 @@ +/* + * Copyright (c) 2020 AIIT XUOS Lab + * XiUOS is licensed under Mulan PSL v2. + * You can use this software according to the terms and conditions of the Mulan PSL v2. + * You may obtain a copy of Mulan PSL v2 at: + * http://license.coscl.org.cn/MulanPSL2 + * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, + * EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, + * MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. + * See the Mulan PSL v2 for more details. +*/ + +#include + +#if defined(FS_VFS) && defined(TOOL_SHELL) + +#include +#include +#include +#include +#include +#include +#include "utility.h" + + +#define USE_HEAP_MEM + +static const uint8_t extra_lbits[LENGTH_CODES] = { + 0, 0, 0, 0, 0, 0, 0, + 0, 1, 1, 1, 1, 2, 2, + 2, 2, 3, 3, 3, 3, 4, + 4, 4, 4, 5, 5, 5, 5, + 0, +}; + +static const uint8_t extra_dbits[D_CODES] = { + 0, 0, 0, 0, 1, 1, 2, + 2, 3, 3, 4, 4, 5, 5, + 6, 6, 7, 7, 8, 8, 9, + 9, 10, 10, 11, 11, 12, + 12, 13, 13, +}; + +static const uint8_t extra_blbits[BL_CODES] = { + 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, + 0, 0, 2, 3, 7, +}; + +static const uint8_t bl_order[BL_CODES] = { + 16, 17, 18, 0, 8, 7, 9, + 6, 10, 5, 11, 4, 12, 3, + 13, 2, 14, 1, 15, +}; + +struct globals { + unsigned char window[2 * WSIZE]; + unsigned char l_buf[LIT_BUFSIZE]; + uint16_t d_buf[DIST_BUFSIZE]; + unsigned char flag_buf[LIT_BUFSIZE / 8]; + unsigned char outbuf[OUTBUF_SIZE]; + uint16_t prev[2 * WSIZE]; +#define HEAD (GLB.prev + WSIZE) + + uint32_t bi_buf; + uint32_t bi_valid; +#define BUF_SIZE 32 + + unsigned char flags; + unsigned char flag_bit; + + int last_lit; + int last_dist; + int last_flags; + + int in_fd, out_fd; + uint32_t crc32; + int block_start; + int ins_h; + int prev_length; + int strstart; + int match_start; + int lookahead; + int incnt; + int outcnt; + int eofile; + + uint16_t heap[HEAP_SIZE]; + int heap_len; + int heap_max; + + + CtDate_t dyn_ltree[HEAP_SIZE]; + CtDate_t dyn_dtree[2 * D_CODES + 1]; + CtDate_t static_ltree[L_CODES + 2]; + CtDate_t static_dtree[D_CODES]; + CtDate_t bl_tree[2 * BL_CODES + 1]; + + TreeDesc_t l_desc; + TreeDesc_t d_desc; + TreeDesc_t bl_desc; + + uint16_t bl_count[MAX_BITS + 1]; + + unsigned char depth[2 * L_CODES + 1]; + + unsigned char length_code[MAX_MATCH - MIN_MATCH + 1]; + int base_length[LENGTH_CODES]; + + unsigned char dist_code[512]; + int base_dist[D_CODES]; + + int opt_len; + int static_len; +}; +#ifdef USE_HEAP_MEM +static struct globals *glbp; +#define GLB (*glbp) +#else +struct globals GLB; +#endif + +static void FlushOutbuf() +{ + write(GLB.out_fd, GLB.outbuf, GLB.outcnt); + GLB.outcnt = 0; +} + +static inline void output8(unsigned char u8) +{ + GLB.outbuf[GLB.outcnt++] = u8; + if (GLB.outcnt == OUTBUF_SIZE) + FlushOutbuf(); +} + +static inline void output16(uint32_t u16) +{ + output8(u16); + output8(u16 >> 8); +} + +static inline void output32(uint32_t u32) +{ + output16(u32); + output16(u32 >> 16); +} + +static void UpdateCrc32(unsigned char *buf, size_t len) +{ + for (int i = 0; i < len; i++) { + GLB.crc32 = GLB.crc32 ^ buf[i]; + for (int j = 0; j < 8; j++) + GLB.crc32 = (GLB.crc32 >> 1) ^ + (0xedb88320 & -(GLB.crc32 & 1)); + } +} + +static size_t ReadFile(void *buf, size_t size) +{ + size_t ReadSize; + + ReadSize = read(GLB.in_fd, buf, size); + GLB.incnt += ReadSize; + UpdateCrc32(buf, ReadSize); + + + return ReadSize; +} + +static int LongestMatch(int curr_match) +{ + int chain_length = MAX_CHAIN_LEN; + unsigned char *str = &GLB.window[GLB.strstart]; + unsigned char *match; + int length; + int best_length = GLB.prev_length; + int limit = GLB.strstart > MAX_DIST ? GLB.strstart - MAX_DIST : 0; + + for (chain_length = MAX_CHAIN_LEN; curr_match > limit && chain_length > 0; + curr_match = GLB.prev[curr_match & WMASK], chain_length--) { + match = &GLB.window[curr_match]; + + if (match[best_length] != str[best_length] || match[0] != str[0] + || match[1] != str[1]) + continue; + + length = 2; + while (length < MAX_MATCH && match[length] == str[length]) + length++; + + if (length > best_length) { + GLB.match_start = curr_match; + best_length = length; + if (length >= MAX_MATCH) + break; + } + } + + return best_length; +} + +#define D_CODE(dist) ((dist) < 256 ? GLB.dist_code[dist] : \ + GLB.dist_code[256 + ((dist) >> 7)]) + +static int CtTally(int dist, int lc) +{ + GLB.l_buf[GLB.last_lit++] = lc; + + if (dist == 0) { + GLB.dyn_ltree[lc].freq++; + } else { + dist--; + + GLB.dyn_ltree[GLB.length_code[lc] + LITERALS + 1].freq++; + GLB.dyn_dtree[D_CODE(dist)].freq++; + + GLB.d_buf[GLB.last_dist++] = dist; + GLB.flags |= GLB.flag_bit; + } + GLB.flag_bit <<= 1; + + if ((GLB.last_lit & 0x7) == 0) { + GLB.flag_buf[GLB.last_flags++] = GLB.flags; + GLB.flags = 0; + GLB.flag_bit = 1; + } + + return (GLB.last_lit == LIT_BUFSIZE - 1 || + GLB.last_dist == DIST_BUFSIZE); +} + +static void SendBits(uint32_t value, int length) +{ + uint32_t new_buf; + + new_buf = GLB.bi_buf | (value << GLB.bi_valid); + + length += GLB.bi_valid; + + if (length >= BUF_SIZE) { + value >>= (BUF_SIZE - GLB.bi_valid); + output32(new_buf); + new_buf = value; + length -= BUF_SIZE; + } + GLB.bi_buf = new_buf; + GLB.bi_valid = length; +} + +#define SEND_CODE(c, tree) SendBits(tree[c].code, tree[c].len) + +static void CompressBlock(CtDate_t *ltree, CtDate_t *dtree) +{ + int dist; + int lc; + int lx = 0; + int dx = 0; + int fx = 0; + unsigned char flag = 0; + uint32_t code; + int extra; + + if (GLB.last_lit != 0) { + do { + if ((lx & 0x7) == 0) + flag = GLB.flag_buf[fx++]; + lc = GLB.l_buf[lx++]; + if ((flag & 1) == 0) { + SEND_CODE(lc, ltree); + } else { + code = GLB.length_code[lc]; + SEND_CODE(code + LITERALS + 1, ltree); + extra = extra_lbits[code]; + if (extra != 0) { + lc -= GLB.base_length[code]; + SendBits(lc, extra); + } + + dist = GLB.d_buf[dx++]; + code = D_CODE(dist); + SEND_CODE(code, dtree); + extra = extra_dbits[code]; + if (extra != 0) { + dist -= GLB.base_dist[code]; + SendBits(dist, extra); + } + } + flag >>= 1; + } while (lx < GLB.last_lit); + } + + SEND_CODE(END_BLOCK, ltree); +} + +static void SendTree(CtDate_t *tree, int max_code) +{ + int prevlen = -1; + int currlen; + int nextlen = tree[0].len; + int count = 0; + int max_count = 7; + int min_count = 4; + + if (nextlen == 0) { + max_count = 138; + min_count = 3; + } + + for (int n = 0; n <= max_code; n++) { + currlen = nextlen; + nextlen = tree[n + 1].len; + if (++count < max_count && currlen == nextlen) { + continue; + } else if (count < min_count) { + do { + SEND_CODE(currlen, GLB.bl_tree); + } while (--count); + } else if (currlen != 0) { + if (currlen != prevlen) { + SEND_CODE(currlen, GLB.bl_tree); + count--; + } + SEND_CODE(REP_3_6, GLB.bl_tree); + SendBits(count - 3, 2); + } else if (count <= 10) { + SEND_CODE(REPZ_3_10, GLB.bl_tree); + SendBits(count - 3, 3); + } else { + SEND_CODE(REPZ_11_138, GLB.bl_tree); + SendBits(count - 11, 7); + } + count = 0; + prevlen = currlen; + if (nextlen == 0) { + max_count = 138; + min_count = 3; + } else if (currlen == nextlen) { + max_count = 6; + min_count = 3; + } else { + max_count = 7; + min_count = 4; + } + } +} + + +static void SendAllTrees(int lcodes, int dcodes, int blcodes) +{ + SendBits(lcodes - 257, 5); + SendBits(dcodes - 1, 5); + SendBits(blcodes - 4, 4); + + for (int rank = 0; rank < blcodes; rank++) + SendBits(GLB.bl_tree[bl_order[rank]].len, 3); + + SendTree(GLB.dyn_ltree, lcodes - 1); + SendTree(GLB.dyn_dtree, dcodes - 1); +} + +static void BiWindup() +{ + uint32_t bits = GLB.bi_buf; + int cnt = GLB.bi_valid; + + while (cnt > 0) { + output8(bits); + bits >>= 8; + cnt -= 8; + } + GLB.bi_buf = 0; + GLB.bi_valid = 0; +} + +static void CopyBlock(unsigned char *buf, size_t len, int with_header) +{ + BiWindup(); + + if (with_header) { + uint32_t v = ((uint16_t)len | ((~len) << 16)); + output32(v); + } + + for (int i = 0; i < len; i++) + output8(buf[i]); +} + +static void ScanTree(CtDate_t *tree, int max_code) +{ + int n; + int prevlen = -1; + int currlen; + int nextlen = tree[0].len; + int count = 0; + int max_count = 7; + int min_count = 4; + + if (nextlen == 0) { + max_count = 138; + min_count = 3; + } + tree[max_code + 1].len = 0xffff; + + for (n = 0; n <= max_code; n++) { + currlen = nextlen; + nextlen = tree[n + 1].len; + if (++count < max_count && currlen == nextlen) + continue; + + if (count < min_count) { + GLB.bl_tree[currlen].freq += count; + } else if (currlen != 0) { + if (currlen != prevlen) + GLB.bl_tree[currlen].freq++; + GLB.bl_tree[REP_3_6].freq++; + } else if (count <= 10) { + GLB.bl_tree[REPZ_3_10].freq++; + } else { + GLB.bl_tree[REPZ_11_138].freq++; + } + count = 0; + prevlen = currlen; + + max_count = 7; + min_count = 4; + if (nextlen == 0) { + max_count = 138; + min_count = 3; + } else if (currlen == nextlen) { + max_count = 6; + min_count = 3; + } + } +} + +#define NODE_SMALLER(tree, n, m) (tree[n].freq < tree[m].freq || \ + (tree[n].freq == tree[m].freq && \ + GLB.depth[n] <= GLB.depth[m])) + +static void HeapAdjust(CtDate_t *tree, int k) +{ + int v = GLB.heap[k]; + int j = k * 2; + + while (j <= GLB.heap_len) { + if (j < GLB.heap_len && + NODE_SMALLER(tree, GLB.heap[j + 1], GLB.heap[j])) + j++; + + if (NODE_SMALLER(tree, v, GLB.heap[j])) + break; + + GLB.heap[k] = GLB.heap[j]; + k = j; + j *= 2; + } + GLB.heap[k] = v; +} + +#define HEAP_POP(tree, top) do { \ + top = GLB.heap[1]; \ + GLB.heap[1] = GLB.heap[GLB.heap_len--]; \ + HeapAdjust(tree, 1); \ + } while (0) + +static void GenBitlen(TreeDesc_t *desc) +{ + CtDate_t *tree = desc->dyn_tree; + CtDate_t *stree = desc->static_tree; + const uint8_t *extra = desc->extra_bits; + int base = desc->extra_base; + int max_code = desc->max_code; + int max_length = desc->max_length; + int h; + int n, m; + int bits; + int xbits; + uint16_t f; + int overflow = 0; + + for (bits = 0; bits <= MAX_BITS; bits++) + GLB.bl_count[bits] = 0; + + tree[GLB.heap[GLB.heap_max]].len = 0; + for (h = GLB.heap_max + 1; h < HEAP_SIZE; h++) { + n = GLB.heap[h]; + bits = tree[tree[n].father].len + 1; + if (bits > max_length) { + bits = max_length; + overflow++; + } + tree[n].len = bits; + + if (n > max_code) + continue; + + GLB.bl_count[bits]++; + xbits = 0; + if (n >= base) + xbits = extra[n - base]; + f = tree[n].freq; + GLB.opt_len += f * (bits + xbits); + + if (stree) + GLB.static_len += f * (stree[n].len + xbits); + } + if (overflow == 0) + return; + + do { + bits = max_length - 1; + while (GLB.bl_count[bits] == 0) + bits--; + + GLB.bl_count[bits]--; + GLB.bl_count[bits + 1] += 2; + GLB.bl_count[max_length]--; + + overflow -= 2; + } while (overflow > 0); + + for (bits = max_length; bits > 0; bits--) { + n = GLB.bl_count[bits]; + while (n > 0) { + m = GLB.heap[--h]; + if (m > max_code) + continue; + if (tree[m].len != bits) { + GLB.opt_len += (int)(bits - tree[m].len) * + tree[m].freq; + tree[m].len = bits; + } + n--; + } + } +} + +static unsigned BiReverse (unsigned code, int len) +{ + unsigned ret = 0; + + while (1) { + ret |= code & 1; + if (--len == 0) + return ret; + code >>= 1; + ret <<= 1; + } +} + +static void GenCodes(CtDate_t * tree, int max_code) +{ + uint16_t next_code[MAX_BITS + 1]; + uint16_t code = 0; + int bits; + int n; + + for (bits = 1; bits <= MAX_BITS; bits++) + next_code[bits] = code = (code + GLB.bl_count[bits - 1]) << 1; + + for (n = 0; n <= max_code; n++) { + int len = tree[n].len; + + if (len == 0) + continue; + tree[n].code = BiReverse (next_code[len]++, len); + } +} + +static void BuildTree(TreeDesc_t *desc) +{ + CtDate_t *tree = desc->dyn_tree; + CtDate_t *stree = desc->static_tree; + int elems = desc->elems; + int m, n; + int max_code = -1; + int node = elems; + + GLB.heap_len = 0; + GLB.heap_max = HEAP_SIZE; + + for (n = 0; n < elems; n++) { + if (tree[n].freq != 0) { + GLB.heap[++GLB.heap_len] = max_code = n; + GLB.depth[n] = 0; + } else { + tree[n].len = 0; + } + } + + while (GLB.heap_len < 2) { + int new = GLB.heap[++GLB.heap_len] = (max_code < 2 ? + ++max_code : 0); + + tree[new].freq = 1; + GLB.depth[new] = 0; + GLB.opt_len--; + if (stree) + GLB.static_len -= stree[new].len; + } + desc->max_code = max_code; + + for (n = GLB.heap_len / 2; n >= 1; n--) + HeapAdjust(tree, n); + + do { + HEAP_POP(tree, n); + m = GLB.heap[1]; + + GLB.heap[--GLB.heap_max] = n; + GLB.heap[--GLB.heap_max] = m; + + tree[node].freq = tree[n].freq + tree[m].freq; + GLB.depth[node] = MAX(GLB.depth[n], GLB.depth[m]) + 1; + tree[n].father = tree[m].father = node; + + GLB.heap[1] = node++; + HeapAdjust(tree, 1); + } while (GLB.heap_len >= 2); + + GLB.heap[--GLB.heap_max] = GLB.heap[1]; + + GenBitlen(desc); + GenCodes(tree, max_code); +} + +static int BuildBlTree() +{ + int max_blindex; + + ScanTree(GLB.dyn_ltree, GLB.l_desc.max_code); + ScanTree(GLB.dyn_dtree, GLB.d_desc.max_code); + + BuildTree(&GLB.bl_desc); + + for (max_blindex = BL_CODES - 1; max_blindex >= 3; max_blindex--) + if (GLB.bl_tree[bl_order[max_blindex]].len != 0) + break; + + GLB.opt_len += 3 * (max_blindex + 1) + 5 + 5 + 4; + + return max_blindex; +} + +static void InitBlock(void) +{ + int n; + + for (n = 0; n < L_CODES; n++) + GLB.dyn_ltree[n].freq = 0; + for (n = 0; n < D_CODES; n++) + GLB.dyn_dtree[n].freq = 0; + for (n = 0; n < BL_CODES; n++) + GLB.bl_tree[n].freq = 0; + + GLB.dyn_ltree[END_BLOCK].freq = 1; + GLB.opt_len = GLB.static_len = 0; + GLB.last_lit = GLB.last_dist = GLB.last_flags = 0; + GLB.flags = 0; + GLB.flag_bit = 1; +} + +static void FlushBlock(unsigned char *buf, uint32_t stored_len, int eof) +{ + uint32_t opt_lenb, static_lenb; + int max_blindex; + + GLB.flag_buf[GLB.last_flags] = GLB.flags; + + BuildTree(&GLB.l_desc); + BuildTree(&GLB.d_desc); + + max_blindex = BuildBlTree(); + + opt_lenb = (GLB.opt_len + 3 + 7) >> 3; + static_lenb = (GLB.static_len + 3 + 7) >> 3; + if (static_lenb < opt_lenb) + opt_lenb = static_lenb; + if (stored_len + 4 <= opt_lenb && buf != NULL) { + SendBits((STORED_BLOCK << 1) + eof, 3); + CopyBlock(buf, stored_len, 1); + } else if (static_lenb == opt_lenb) { + SendBits((STATIC_TREES << 1) + eof, 3); + CompressBlock(GLB.static_ltree, GLB.static_dtree); + } else { + SendBits((DYN_TREES << 1) + eof, 3); + SendAllTrees(GLB.l_desc.max_code + 1, + GLB.d_desc.max_code + 1, max_blindex + 1); + CompressBlock(GLB.dyn_ltree, GLB.dyn_dtree); + } + + InitBlock(); + + if (eof) + BiWindup(); +} + +#define FLUSH_BLOCK(eof) FlushBlock( \ + GLB.block_start >= 0 \ + ? &GLB.window[GLB.block_start] \ + : NULL, \ + (uint32_t)GLB.strstart - GLB.block_start, \ + (eof) \ + ) + +static void FillWindow() +{ + uint32_t n, m; + uint32_t more = 2 * WSIZE - GLB.lookahead - GLB.strstart; + + if (more == (uint32_t)-1) { + more--; + } else if (GLB.strstart >= WSIZE + MAX_DIST) { + memcpy(GLB.window, &GLB.window[WSIZE], WSIZE); + + GLB.match_start -= WSIZE; + GLB.strstart -= WSIZE; + GLB.block_start -= WSIZE; + for (n = 0; n < HASH_SIZE; n++) { + m = HEAD[n]; + HEAD[n] = m >= WSIZE ? m - WSIZE : 0; + } + for (n = 0; n < WSIZE; n++) { + m = GLB.prev[n]; + GLB.prev[n] = m >= WSIZE ? m - WSIZE : 0; + } + more += WSIZE; + } + if (!GLB.eofile) { + n = ReadFile(GLB.window + GLB.strstart + + GLB.lookahead, more); + if (n == 0 || n == (unsigned) -1) + GLB.eofile = 1; + else + GLB.lookahead += n; + } +} + +static void FillWindowIfNeeded(void) +{ + while (GLB.lookahead < MIN_LOOKAHEAD && !GLB.eofile) + FillWindow(); +} + +#define UPDATE_HASH(h, c) (h = (((h) << HASH_SHIFT) ^ (c)) & HASH_MASK) + +#define INSERT_STRING(s, match_head) do { \ + UPDATE_HASH(GLB.ins_h, GLB.window[(s) + MIN_MATCH - 1]); \ + GLB.prev[(s) & WMASK] = HEAD[GLB.ins_h]; \ + match_head = HEAD[GLB.ins_h]; \ + HEAD[GLB.ins_h] = (s); \ + } while (0) + +static void deflate() +{ + int hash_head; + int prev_match; + int flush; + int match_available = 0; + int match_length = MIN_MATCH - 1; + + while (GLB.lookahead) { + INSERT_STRING(GLB.strstart, hash_head); + + GLB.prev_length = match_length; + prev_match = GLB.match_start; + match_length = MIN_MATCH - 1; + + if (hash_head && GLB.prev_length < MAX_LAZY_MATCH && + GLB.strstart - hash_head <= MAX_DIST) { + match_length = LongestMatch(hash_head); + if (match_length > GLB.lookahead) + match_length = GLB.lookahead; + + if (match_length == MIN_MATCH && + GLB.strstart - GLB.match_start > 4096) + match_length--; + } + + if (GLB.prev_length >= MIN_MATCH && + match_length <= GLB.prev_length) { + flush = CtTally(GLB.strstart - 1 - prev_match, + GLB.prev_length - MIN_MATCH); + + GLB.lookahead -= GLB.prev_length - 1; + for (GLB.prev_length -= 2; GLB.prev_length > 0; + GLB.prev_length--) { + GLB.strstart++; + INSERT_STRING(GLB.strstart, hash_head); + } + match_available = 0; + match_length = MIN_MATCH - 1; + GLB.strstart++; + if (flush) { + FLUSH_BLOCK(0); + GLB.block_start = GLB.strstart; + } + } else if (match_available) { + if (CtTally(0, GLB.window[GLB.strstart - 1])) { + FLUSH_BLOCK(0); + GLB.block_start = GLB.strstart; + } + GLB.strstart++; + GLB.lookahead--; + } else { + match_available = 1; + GLB.strstart++; + GLB.lookahead--; + } + + FillWindowIfNeeded(); + } + if (match_available) + CtTally(0, GLB.window[GLB.strstart - 1]); + + FLUSH_BLOCK(1); +} + +static void CtInit() +{ + int n; + int length; + int code; + int dist; + + length = 0; + for (code = 0; code < LENGTH_CODES - 1; code++) { + GLB.base_length[code] = length; + for (n = 0; n < (1 << extra_lbits[code]); n++) { + GLB.length_code[length++] = code; + } + } + + GLB.length_code[length - 1] = code; + + dist = 0; + for (code = 0; code < 16; code++) { + GLB.base_dist[code] = dist; + for (n = 0; n < (1 << extra_dbits[code]); n++) { + GLB.dist_code[dist++] = code; + } + } + dist >>= 7; + for (; code < D_CODES; code++) { + GLB.base_dist[code] = dist << 7; + for (n = 0; n < (1 << (extra_dbits[code] - 7)); n++) { + GLB.dist_code[256 + dist++] = code; + } + } + + n = 0; + while (n <= 143) + GLB.static_ltree[n++].len = 8; + while (n <= 255) + GLB.static_ltree[n++].len = 9; + while (n <= 279) + GLB.static_ltree[n++].len = 7; + while (n <= 287) + GLB.static_ltree[n++].len = 8; + GLB.bl_count[7] = 279 - 255; + GLB.bl_count[8] = (143 + 1) + (287 - 279); + GLB.bl_count[9] = 255 - 143; + + GenCodes((CtDate_t *)GLB.static_ltree, L_CODES + 1); + + for (n = 0; n < D_CODES; n++) { + GLB.static_dtree[n].len = 5; + GLB.static_dtree[n].code = BiReverse (n, 5); + } + + InitBlock(); +} + +static void LmInit() +{ + unsigned j; + + memset(HEAD, 0, (1 << HASH_BITS) * sizeof(*HEAD)); + + GLB.lookahead = ReadFile(GLB.window, + sizeof(int) <= 2 ? (unsigned) WSIZE : 2 * WSIZE); + + if (GLB.lookahead == 0 || GLB.lookahead == (unsigned) -1) { + GLB.eofile = 1; + GLB.lookahead = 0; + return; + } + + FillWindowIfNeeded(); + + for (j = 0; j < MIN_MATCH - 1; j++) + UPDATE_HASH(GLB.ins_h, GLB.window[j]); +} + +int GzipCompress(char *file_name) +{ + int ret = 0; + char *gz_file_name; + struct stat statbuf; + +#ifdef USE_HEAP_MEM + glbp = malloc(sizeof(struct globals)); + if (glbp == NULL) { + KPrintf("Memory too small\n"); + return -1; + } +#endif + + memset(&GLB, 0, sizeof(struct globals)); + + if ((GLB.in_fd = open(file_name, O_RDONLY)) < 0) { + ret = -1; + goto free_glbp; + } + + fstat(GLB.in_fd, &statbuf); + if (!S_ISREG(statbuf.st_mode)) { + ret = -1; + goto free_glbp; + } + + if ((gz_file_name = malloc(strlen(file_name) + 4)) == NULL) { + ret = -1; + goto close_in_fd; + } + strcpy(gz_file_name, file_name); + strcat(gz_file_name, ".gz"); + + if ((GLB.out_fd = + open(gz_file_name, O_WRONLY | O_CREAT | O_TRUNC)) < 0) { + ret = -1; + goto free_gz_file_name; + } + + GLB.crc32 = ~0; + GLB.l_desc.dyn_tree = GLB.dyn_ltree; + GLB.l_desc.static_tree = GLB.static_ltree; + GLB.l_desc.extra_bits = extra_lbits; + GLB.l_desc.extra_base = LITERALS + 1; + GLB.l_desc.elems = L_CODES; + GLB.l_desc.max_length = MAX_BITS; + GLB.d_desc.dyn_tree = GLB.dyn_dtree; + GLB.d_desc.static_tree = GLB.static_dtree; + GLB.d_desc.extra_bits = extra_dbits; + GLB.d_desc.elems = D_CODES; + GLB.d_desc.max_length = MAX_BITS; + GLB.bl_desc.dyn_tree = GLB.bl_tree; + GLB.bl_desc.extra_bits = extra_blbits, + GLB.bl_desc.elems = BL_CODES; + GLB.bl_desc.max_length = MAX_BL_BITS; + CtInit(); + LmInit(); + + output32(0x00088b1f); + output32(0x0); + output16(0x2 | 0x300); + FlushOutbuf(); + + deflate(); + + output32(~GLB.crc32); + output32(GLB.incnt); + FlushOutbuf(); + + if (GLB.incnt != statbuf.st_size) + ret = -1; + + close(GLB.out_fd); +free_gz_file_name: + free(gz_file_name); +close_in_fd: + close(GLB.in_fd); +free_glbp: +#ifdef USE_HEAP_MEM + free(glbp); +#endif + + return ret; +} + +extern int GzipDecompress(char *file_name); + +static void GzipPrintUsage() +{ + KPrintf("Usage: gzip [OPTIONS]... [FILES]...\n"); + KPrintf("Supported option flags:\n"); + KPrintf(" d decompress gzip file(s)\n"); +} + +int gzip(int argc, char **argv) +{ + int (*gzip_func)(char *file_name) = GzipCompress; + + if (argc < 2) { + GzipPrintUsage(); + return 0; + } + + if (argv[1][0] == '-') { + if (strlen(argv[1]) != 2 || argv[1][1] != 'd') { + KPrintf("Bad options\n"); + GzipPrintUsage(); + return 0; + } + gzip_func = GzipDecompress; + argv++; + argc--; + } + + for (int i = 1; i < argc; i++) + if (gzip_func(argv[i]) < 0) { + KPrintf("Operation failed\n"); + break; + } + + return 0; +} + + +#endif diff --git a/Ubiquitous/XiZi/tool/shell/letter-shell/file_ext/gzip.h b/Ubiquitous/XiZi/tool/shell/letter-shell/file_ext/gzip.h new file mode 100644 index 0000000..c92362d --- /dev/null +++ b/Ubiquitous/XiZi/tool/shell/letter-shell/file_ext/gzip.h @@ -0,0 +1,90 @@ +/* + * Copyright (c) 2020 AIIT XUOS Lab + * XiUOS is licensed under Mulan PSL v2. + * You can use this software according to the terms and conditions of the Mulan PSL v2. + * You may obtain a copy of Mulan PSL v2 at: + * http://license.coscl.org.cn/MulanPSL2 + * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, + * EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, + * MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. + * See the Mulan PSL v2 for more details. +*/ + +#ifndef __INC_GZIP_H__ +#define __INC_GZIP_H__ + +#include + +#define WSIZE (1 << 15) +#define OUTBUF_SIZE (1 << 14) +#define WMASK (WSIZE - 1) + +#define LIT_BUFSIZE WSIZE +#define DIST_BUFSIZE LIT_BUFSIZE + +#define MIN_MATCH 3 +#define MAX_MATCH 258 + +#define MIN_LOOKAHEAD (MAX_MATCH + MIN_MATCH + 1) +#define MAX_CHAIN_LEN 4096 +#define MAX_LAZY_MATCH MAX_MATCH +#define MAX_DIST (WSIZE - MIN_LOOKAHEAD) + +#define HASH_BITS 15 +#define HASH_SIZE (1 << HASH_BITS) +#define HASH_MASK (HASH_SIZE - 1) +#define HASH_SHIFT ((HASH_BITS + MIN_MATCH - 1) / MIN_MATCH) + +#define MAX_BITS 15 + +#define MAX_BL_BITS 7 + +#define LENGTH_CODES 29 + +#define LITERALS 256 + +#define END_BLOCK 256 + +#define L_CODES (LITERALS + 1 + LENGTH_CODES) + +#define D_CODES 30 + +#define BL_CODES 19 + +#define STORED_BLOCK 0 +#define STATIC_TREES 1 +#define DYN_TREES 2 + +typedef struct CtDate +{ + union { + uint16_t freq; + uint16_t code; + }; + union { + uint16_t father; + uint16_t len; + }; +} CtDate_t; + + +typedef struct TreeDesc { + CtDate_t *dyn_tree; + CtDate_t *static_tree; + const uint8_t *extra_bits; + int extra_base; + int elems; + int max_length; + int max_code; +} TreeDesc_t; + +#define HEAP_SIZE (2 * L_CODES + 1) + + +#define REP_3_6 16 + +#define REPZ_3_10 17 + +#define REPZ_11_138 18 + +#endif diff --git a/Ubiquitous/XiZi/tool/shell/letter-shell/file_ext/msh_file.c b/Ubiquitous/XiZi/tool/shell/letter-shell/file_ext/msh_file.c new file mode 100644 index 0000000..5c5afa2 --- /dev/null +++ b/Ubiquitous/XiZi/tool/shell/letter-shell/file_ext/msh_file.c @@ -0,0 +1,601 @@ +/* + * Copyright (c) 2020 AIIT XUOS Lab + * XiUOS is licensed under Mulan PSL v2. + * You can use this software according to the terms and conditions of the Mulan PSL v2. + * You may obtain a copy of Mulan PSL v2 at: + * http://license.coscl.org.cn/MulanPSL2 + * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, + * EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, + * MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. + * See the Mulan PSL v2 for more details. +*/ + +#include + +#if defined(TOOL_SHELL) && defined(FS_VFS) +#include "shell.h" +#include +#include +#include + +#include "utility.h" + +extern char working_dir[]; + +void ls(const char *path) +{ + DIR *dir; + struct dirent *dirent; + struct stat statbuf; + + if (path == NULL) { + path = strdup(working_dir); + if (path == NULL) + return; + } else { + path = (char *)path; + } + + if ((dir = opendir(path)) == NULL) { + KPrintf("Failed to open directory %s\n", path); + return; + } + + KPrintf("Directory: %s\n", path); + while ((dirent = readdir(dir)) != NULL) { + stat(dirent->d_name, &statbuf); + KPrintf("%-20s", dirent->d_name); + if (S_ISREG(statbuf.st_mode)) + KPrintf("%-25lu\n", (unsigned long)statbuf.st_size); + else + KPrintf("%-25s\n", ""); + } + + closedir(dir); +} + + +int cmd_ls(int argc, char **argv) +{ + if (argc == 1) + ls(working_dir); + else + ls(argv[1]); + + return 0; +} + +SHELL_EXPORT_CMD(SHELL_CMD_PERMISSION(0)|SHELL_CMD_TYPE(SHELL_TYPE_CMD_MAIN)|SHELL_CMD_DISABLE_RETURN, +ls,cmd_ls, List information about the FILES .); + +static int CopyRecursive(const char *from, const char *to, char *buf, + size_t buf_size) +{ + struct stat statbuf; + int ret; + + if (strcmp(from, to) == 0) + return 0; + + ret = stat(from, &statbuf); + if (ret < 0) { + KPrintf("Failed to read %s\n", from); + return -1; + } + + if (S_ISREG(statbuf.st_mode)) { + int fd_from, fd_to; + int size_read; + int total_size_written = 0; + + fd_from = open(from, O_RDONLY); + if (fd_from < 0) { + KPrintf("Failed to open %s\n", from); + return -1; + } + fd_to = open(to, O_WRONLY); + if (fd_to < 0) { + KPrintf("Failed to open %s\n", to); + close(fd_from); + return -1; + } + + while ((size_read = read(fd_from, buf, buf_size)) > 0) + total_size_written += write(fd_to, buf, size_read); + + close(fd_from); + close(fd_to); + + if (total_size_written != statbuf.st_size) { + KPrintf("Error copying %s to %s\n", from, to); + return -1; + } + + return 0; + } + + DIR *dirp; + struct dirent *dirent; + char *sub_from, *sub_to; + + ret = mkdir(to, 0777); + if (ret < 0) { + KPrintf("Failed to create directory %s\n", to); + return -1; + } + + dirp = opendir(from); + if (dirp == NULL) { + KPrintf("Failed to open directory %s\n", from); + return -1; + } + + ret = 0; + while ((dirent = readdir(dirp)) != NULL) { + sub_from = malloc(strlen(from) + strlen(dirent->d_name) + 2); + sub_to = malloc(strlen(to) + strlen(dirent->d_name) + 2); + if (sub_from == NULL || sub_to == NULL) { + KPrintf("Out of memory\n"); + ret = -1; + goto err; + } + + sprintf(sub_from, "%s/%s", from, dirent->d_name); + sprintf(sub_to, "%s/%s", to, dirent->d_name); + + if (CopyRecursive(sub_from, sub_to, buf, buf_size) < 0) { + ret = -1; + goto err; + } + + free(sub_from); + free(sub_to); + } + +err: + closedir(dirp); + free(sub_from); + free(sub_to); + + return ret; +} + +static int copy(const char *from, const char *to) +{ + struct stat statbuf; + char buf[128]; + char *abs_from, *abs_to; + int abs_from_len, abs_to_len; + char *last_name; + int last_name_len; + char *GetAbsolutePath(const char *path); + + abs_from = GetAbsolutePath(from); + abs_to = GetAbsolutePath(to); + if (abs_from == NULL || abs_to == NULL) + goto err; + + abs_from_len = strlen(abs_from); + abs_to_len = strlen(abs_to); + + last_name = abs_from + abs_from_len - 1; + while (*last_name != '/') + last_name--; + last_name_len = abs_from + abs_from_len - last_name; + + if (stat(abs_to, &statbuf) == 0) { + if (S_ISDIR(statbuf.st_mode)) { + if (strcmp(abs_to, "/") == 0) { + last_name++; + last_name_len--; + } + abs_to = realloc(abs_to, abs_to_len + last_name_len + 1); + if (abs_to == NULL) + goto err; + strcat(abs_to, last_name); + } else { + unlink(abs_to); + } + } + + return CopyRecursive(abs_from, abs_to, buf, sizeof(buf)) < 0; + +err: + free(abs_from); + free(abs_to); + + return -1; +} + +int CmdCp(int argc, char *argv[]) +{ + if (argc != 3) { + KPrintf("Usage: cp SOURCE DEST\n"); + KPrintf("Copy SOURCE to DEST\n"); + + return 0; + } + + copy(argv[1], argv[2]); + + return 0; +} + + +SHELL_EXPORT_CMD(SHELL_CMD_PERMISSION(0)|SHELL_CMD_TYPE(SHELL_TYPE_CMD_MAIN)|SHELL_CMD_DISABLE_RETURN, +cp,CmdCp, Copy source to dest.); + + +static void RmRecursive(char *file_name, int recursive) +{ + struct stat statbuf; + + if (stat(file_name, &statbuf) < 0) + return; + + if (recursive && S_ISDIR(statbuf.st_mode)) { + DIR *dir; + struct dirent *dirent; + + dir = opendir(file_name); + while ((dirent = readdir(dir)) != NULL) { + char *sub_file_name = malloc(strlen(file_name) + + strlen(dirent->d_name) + 2); + if (sub_file_name == NULL) { + KPrintf("Memory not enough\n"); + return; + } + sprintf(sub_file_name, "%s/%s", file_name, dirent->d_name); + RmRecursive(sub_file_name, recursive); + free(sub_file_name); + } + closedir(dir); + } + + unlink(file_name); +} + +int CmdMv(int argc, char *argv[]) +{ + if (argc != 3) { + KPrintf("Usage: mv SOURCE DEST\n"); + KPrintf("Move SOURCE to DESn"); + + return 0; + } + + if (rename(argv[1], argv[2]) != 0) + if (copy(argv[1], argv[2]) == 0) + RmRecursive(argv[1], 1); + + return 0; +} + +SHELL_EXPORT_CMD(SHELL_CMD_PERMISSION(0)|SHELL_CMD_TYPE(SHELL_TYPE_CMD_MAIN)|SHELL_CMD_DISABLE_RETURN, +mv,CmdMv, Move frome source to dest.); + + +void cat(const char *filename) +{ + int size; + char buf[128]; + int fd; + + if ((fd = open(filename, O_RDONLY)) < 0) { + KPrintf("Failed to open file %s\n", filename); + return; + } + + while ((size = read(fd, buf, 128)) > 0) + for (int i = 0; i < size; i++) + putchar(buf[i]); + + close(fd); +} + +int cmd_cat(int argc, char **argv) +{ + int index; + extern void cat(const char *filename); + + if (argc == 1) + { + KPrintf("Usage: cat [FILE]...\n"); + KPrintf("Concatenate FILE(s)\n"); + return 0; + } + + for (index = 1; index < argc; index ++) + { + cat(argv[index]); + } + + return 0; +} + + +SHELL_EXPORT_CMD(SHELL_CMD_PERMISSION(0)|SHELL_CMD_TYPE(SHELL_TYPE_CMD_MAIN)|SHELL_CMD_DISABLE_RETURN, +cat,cmd_cat,Concatenate FILE(s).); + +int cmd_rm(int argc, char **argv) +{ + int recursive = 0; + + if (argc == 1) { + KPrintf("Usage: rm FILE...\n"); + KPrintf("Remove (unlink) the FILE(s).\n"); + KPrintf("Suppported option flags:\n"); + KPrintf(" r recursively remove folders\n"); + return 0; + } + + if (argv[1][0] == '-') { + if (strcmp(argv[1], "-r") != 0) + KPrintf("Unknown options\n"); + recursive = 1; + argc--; + argv++; + } + + for (int i = 1; i < argc; i++) + RmRecursive(argv[i], recursive); + + return 0; +} + +SHELL_EXPORT_CMD(SHELL_CMD_PERMISSION(0)|SHELL_CMD_TYPE(SHELL_TYPE_CMD_MAIN)|SHELL_CMD_DISABLE_RETURN, +rm,cmd_rm,Remove (unlink) the File(s).); + +#ifdef VFS_USING_WORKDIR +int cmd_cd(int argc, char **argv) +{ + if (argc == 1) + { + KPrintf("%s\n", working_dir); + } + else if (argc == 2) + { + if (chdir(argv[1]) != 0) + { + KPrintf("No such directory: %s\n", argv[1]); + } + } + + return 0; +} + +SHELL_EXPORT_CMD(SHELL_CMD_PERMISSION(0)|SHELL_CMD_TYPE(SHELL_TYPE_CMD_MAIN)|SHELL_CMD_DISABLE_RETURN, +cd,cmd_cd, Chage the shell wroking directory.); + +int CmdPwd(int argc, char **argv) +{ + KPrintf("%s\n", working_dir); + return 0; +} + +SHELL_EXPORT_CMD(SHELL_CMD_PERMISSION(0)|SHELL_CMD_TYPE(SHELL_TYPE_CMD_MAIN)|SHELL_CMD_DISABLE_RETURN, +pwd,CmdPwd, print the name of the current working directory.); + +#endif + +int cmd_mkdir(int argc, char **argv) +{ + if (argc == 1) + { + KPrintf("Usage: mkdir [OPTION] DIRECTORY\n"); + KPrintf("Create the DIRECTORY, if they do not already exist.\n"); + } + else + { + mkdir(argv[1], 0); + } + + return 0; +} + +SHELL_EXPORT_CMD(SHELL_CMD_PERMISSION(0)|SHELL_CMD_TYPE(SHELL_TYPE_CMD_MAIN)|SHELL_CMD_DISABLE_RETURN, +mkdir,cmd_mkdir, Create a directory.); + +int cmd_df(int argc, char **argv) +{ + struct statfs buf; + char *path = argc < 2 ? "/" : argv[1]; + static char *unit[] = {"B", "KB", "MB", "GB"}; + uint64_t integer, decimal = 0; + int i; + + if (statfs(path, &buf) < 0) { + KPrintf("statfs failed: %s\n", path); + return -1; + } + + integer = (uint64_t)buf.f_bsize * buf.f_bfree; + for (i = 0; i < 4; i++) { + if (integer < 1024) + break; + decimal = (integer % 1024) * 10 / 1024; + integer /= 1024; + } + if (i >= 4) + i = 3; + + KPrintf("Free disk space: %d.%d %s " + "[ %d blocks, %d free blocks, %d bytes per block ]\n", + (int)integer, (int)decimal, unit[i], buf.f_blocks, buf.f_bfree, + buf.f_bsize); + + return 0; +} + +SHELL_EXPORT_CMD(SHELL_CMD_PERMISSION(0)|SHELL_CMD_TYPE(SHELL_TYPE_CMD_MAIN)|SHELL_CMD_DISABLE_RETURN, +df,cmd_df,disk free); + + +int cmd_echo(int argc, char** argv) +{ + if (argc == 2) + { + KPrintf("%s\n", argv[1]); + } + else if (argc == 3) + { + int fd; + + fd = open(argv[2], O_RDWR | O_APPEND | O_CREAT, 0); + if (fd >= 0) + { + write (fd, argv[1], strlen(argv[1])); + close(fd); + } + else + { + KPrintf("open file:%s failed!\n", argv[2]); + } + } + else + { + KPrintf("Usage: echo \"string\" [filename]\n"); + } + + return 0; +} + +SHELL_EXPORT_CMD(SHELL_CMD_PERMISSION(0)|SHELL_CMD_TYPE(SHELL_TYPE_CMD_MAIN)|SHELL_CMD_DISABLE_RETURN, +echo,cmd_echo,echo string to file.); + +static void FindRecursive(char *name, char *path) +{ + struct stat statbuf; + DIR *dir = opendir(path); + struct dirent *dirent; + + while ((dirent = readdir(dir)) != NULL) { + char *sub_path = malloc(strlen(path) + + strlen(dirent->d_name) + 2); + if (sub_path == NULL) { + KPrintf("Memory not enough\n"); + return; + } + sprintf(sub_path, "%s/%s", path, dirent->d_name); + if (stat(sub_path, &statbuf) < 0) { + KPrintf("Failed to access %s\n", sub_path); + free(sub_path); + continue; + } + if (strstr(dirent->d_name, name) != NULL) + KPrintf("%s\n", sub_path); + if (S_ISDIR(statbuf.st_mode)) + FindRecursive(name, sub_path); + free(sub_path); + } +} + +static void FindPrintUsage() +{ + KPrintf("Usage: find NAME PATH\n"); +} + +int cmd_find(int argc, char **argv) +{ + struct stat statbuf; + + if (argc != 3) { + FindPrintUsage(); + return 0; + } + + TruncateExtension(argv[2], "/"); + if (strcmp(argv[2], "/") == 0) + argv[2][0] = '\0'; + if (stat(argv[2], &statbuf) < 0 || !S_ISDIR(statbuf.st_mode)) { + KPrintf("No such directory: %s\n", argv[2]); + return 0; + } + + if (strstr(argv[1], "/") != NULL) { + KPrintf("Invalid file name: %s\n", argv[1]); + return 0; + } + + FindRecursive(argv[1], argv[2]); + return 0; +} + +SHELL_EXPORT_CMD(SHELL_CMD_PERMISSION(0)|SHELL_CMD_TYPE(SHELL_TYPE_CMD_MAIN)|SHELL_CMD_DISABLE_RETURN, +find,cmd_find,search file with given name in specified path.); + +int cmd_tar(int argc, char **argv) +{ + extern int tar(int argc, char **argv); + tar(argc, argv); + + return 0; +} + + +SHELL_EXPORT_CMD(SHELL_CMD_PERMISSION(0)|SHELL_CMD_TYPE(SHELL_TYPE_CMD_MAIN)|SHELL_CMD_DISABLE_RETURN, +tar,cmd_tar,create or extarct tar archive.); + + +int CmdGzip(int argc, char **argv) +{ + extern int gzip(int argc, char **argv); + gzip(argc, argv); + + return 0; +} + +SHELL_EXPORT_CMD( +SHELL_CMD_PERMISSION(0)|SHELL_CMD_TYPE(SHELL_TYPE_CMD_MAIN)|SHELL_CMD_DISABLE_RETURN, +gzip,CmdGzip, creat or extart gzip compressed files); + + +int CmdGunzip(int argc, char **argv) +{ + extern int gunzip(int argc, char **argv); + gunzip(argc, argv); + + return 0; +} + + +SHELL_EXPORT_CMD(SHELL_CMD_PERMISSION(0)|SHELL_CMD_TYPE(SHELL_TYPE_CMD_MAIN)|SHELL_CMD_DISABLE_RETURN, +gunzip,CmdGunzip,decompress gzip files.); + +int CmdUnzip(int argc, char **argv) +{ + extern int unzip(int argc, char **argv); + unzip(argc, argv); + + return 0; +} + +SHELL_EXPORT_CMD(SHELL_CMD_PERMISSION(0)|SHELL_CMD_TYPE(SHELL_TYPE_CMD_MAIN)|SHELL_CMD_DISABLE_RETURN, +unzip,CmdUnzip, decompress zip files.); + + +int cmd_bzip2(int argc, char **argv) +{ + extern int bzip2(int argc, char **argv); + bzip2(argc, argv); + + return 0; +} + + +SHELL_EXPORT_CMD(SHELL_CMD_PERMISSION(0)|SHELL_CMD_TYPE(SHELL_TYPE_CMD_MAIN)|SHELL_CMD_DISABLE_RETURN, +bzip2,cmd_bzip2,create or extract bzip2 compressed files.); + +int cmd_bunzip2(int argc, char **argv) +{ + extern int bunzip2(int argc, char **argv); + bunzip2(argc, argv); + + return 0; +} +SHELL_EXPORT_CMD(SHELL_CMD_PERMISSION(0)|SHELL_CMD_TYPE(SHELL_TYPE_CMD_MAIN)|SHELL_CMD_DISABLE_RETURN, +bunzip2,cmd_bunzip2,decompress bzip2 files.); + + +#endif + diff --git a/Ubiquitous/XiZi/tool/shell/letter-shell/file_ext/shell_fs.c b/Ubiquitous/XiZi/tool/shell/letter-shell/file_ext/shell_fs.c new file mode 100644 index 0000000..a2dac14 --- /dev/null +++ b/Ubiquitous/XiZi/tool/shell/letter-shell/file_ext/shell_fs.c @@ -0,0 +1,29 @@ +/** + * @file shell_fs.c + * @author Letter (nevermindzzt@gmail.com) + * @brief shell file system support + * @version 0.1 + * @date 2020-07-22 + * + * @copyright (c) 2020 Letter + * + */ +#include "shell_fs.h" +#include "shell.h" +#include "stdio.h" + + + +/** + * @brief init shell filesystem-suport component + * + * @param shellFs filesystem shell object + * @param pathBuffer path + * @param pathLen length of path + */ +void shellFsInit(ShellFs *shellFs, char *pathBuffer, size_t pathLen) +{ + shellFs->info.path = pathBuffer; + shellFs->info.pathLen = pathLen; + shellFs->getcwd(shellFs->info.path, pathLen); +} diff --git a/Ubiquitous/XiZi/tool/shell/letter-shell/file_ext/shell_fs.h b/Ubiquitous/XiZi/tool/shell/letter-shell/file_ext/shell_fs.h new file mode 100644 index 0000000..0d54327 --- /dev/null +++ b/Ubiquitous/XiZi/tool/shell/letter-shell/file_ext/shell_fs.h @@ -0,0 +1,38 @@ +/** + * @file shell_fs.h + * @author Letter (nevermindzzt@gmail.com) + * @brief shell file system support + * @version 0.1 + * @date 2020-07-22 + * + * @copyright (c) 2020 Letter + * + */ +#ifndef __SHELL_FS_H__ +#define __SHELL_FS_H__ + +#include "stddef.h" +#include "shell.h" + +#define SHELL_FS_VERSION "1.0.0" + +#define SHELL_COMPANION_ID_FS -1 + +#define SHELL_FS_LIST_FILE_BUFFER_MAX 4096 + + +typedef struct shell_fs +{ + char* (*getcwd)(char *, size_t); + int (*chdir)(const char *); + size_t (*listdir)(char *dir, char *buffer, size_t maxLen); + + struct { + char *path; + size_t pathLen; + } info; +} ShellFs; + +void shellFsInit(ShellFs *shellFs, char *pathBuffer, size_t pathLen); + +#endif diff --git a/Ubiquitous/XiZi/tool/shell/letter-shell/file_ext/tar.c b/Ubiquitous/XiZi/tool/shell/letter-shell/file_ext/tar.c new file mode 100644 index 0000000..5bf7b4b --- /dev/null +++ b/Ubiquitous/XiZi/tool/shell/letter-shell/file_ext/tar.c @@ -0,0 +1,467 @@ +/* + * Copyright (c) 2020 AIIT XUOS Lab + * XiUOS is licensed under Mulan PSL v2. + * You can use this software according to the terms and conditions of the Mulan PSL v2. + * You may obtain a copy of Mulan PSL v2 at: + * http://license.coscl.org.cn/MulanPSL2 + * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, + * EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, + * MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. + * See the Mulan PSL v2 for more details. +*/ + +#include + +#if defined(FS_VFS) && defined(TOOL_SHELL) + +#include +#include +#include +#include +#include +#include +#include "tar.h" +#include "utility.h" + +char *bytebuf; + +static void PrintOctal(char *str, int len, uint64_t value) +{ + char buf[32]; + char *cp; + int written_len; + + written_len = sprintf(buf, "%0*llo", len, value); + cp = buf + written_len - len; + + if (*cp == '0') + cp++; + + memcpy(str, cp, len); +} + +static uint64_t ScanOctal(char *str, int len) +{ + uint64_t ret = 0; + + for (int i = 0; i < len; i++) { + if (!isdigit(str[i])) + break; + if (str[i] > '7') + break; + ret = ret * 8 + str[i] - '0'; + } + + return ret; +} + +static void TarChecksumHeader(TarHdr_t *hdr) +{ + int chksum; + + memcpy(hdr->magic, TAR_MAGIC_STR, 6); + memcpy(hdr->version, "00", 2); + + memset(hdr->chksum, ' ', sizeof(hdr->chksum)); + chksum = 0; + for (int i = 0; i < sizeof(TarHdr_t); i++) + chksum += ((unsigned char *)hdr)[i]; + PrintOctal(hdr->chksum, sizeof(hdr->chksum), chksum); +} + +static int TarWriteHeader(int tar_fd, struct stat *tar_statbuf, + char *file_name, char *hdr_file_name, struct stat *statbuf) +{ + TarHdr_t hdr; + int written_len; + + memset(&hdr, 0, sizeof(TarHdr_t)); + + strncpy(hdr.name, hdr_file_name, sizeof(hdr.name)); + + PrintOctal(hdr.mode, sizeof(hdr.mode), statbuf->st_mode & 07777); + PrintOctal(hdr.uid, sizeof(hdr.uid), 1); + PrintOctal(hdr.gid, sizeof(hdr.gid), 1); + PrintOctal(hdr.mtime, sizeof(hdr.mtime), + statbuf->st_mtime >= 0 ? statbuf->st_mtime : 0); + + strcpy(hdr.uname, "rtthread"); + strcpy(hdr.gname, "rtthread"); + + if (S_ISDIR(statbuf->st_mode)) { + hdr.typeflag = TYPE_DIR; + if (strlen(hdr.name) < sizeof(hdr.name) - 1) + hdr.name[strlen(hdr.name)] = '/'; + } else if (S_ISREG(statbuf->st_mode)) { + hdr.typeflag = TYPE_REG; + + uint64_t size = statbuf->st_size; + if (size <= 0777777777777) + PrintOctal(hdr.size, sizeof(hdr.size), size); + else { + return -1; + } + } else { + return -1; + } + + TarChecksumHeader(&hdr); + + written_len = write(tar_fd, &hdr, sizeof(TarHdr_t)); + if (written_len != sizeof(TarHdr_t)) + return -1; + + return 0; +} + +static int TarWriteFileRecursive(int tar_fd, + struct stat *tar_statbuf, char *file_name, int verbose) +{ + char *hdr_file_name; + struct stat statbuf; + + hdr_file_name = RemoveUnsafePrefix(file_name); + if (hdr_file_name [0] == '\0') + return 0; + + stat(file_name, &statbuf); + + + if (TarWriteHeader(tar_fd, tar_statbuf, file_name, + hdr_file_name, &statbuf) < 0) + return -1; + + if (verbose) + KPrintf("%s\n", file_name); + + if (S_ISREG(statbuf.st_mode)) { + int fd; + size_t written_size = 0, copied_size; + + fd = open(file_name, O_RDONLY); + if (fd < 0) + return -1; + + while ((copied_size = read(fd, bytebuf, TAR_BLOCK_SIZE)) > 0) { + if (write(tar_fd, bytebuf, copied_size) != copied_size) { + copied_size = -1; + break; + } + written_size += copied_size; + } + if (copied_size < 0 || written_size != statbuf.st_size) { + close(fd); + return -1; + } + + copied_size = TAR_BLOCK_SIZE - (written_size % TAR_BLOCK_SIZE); + copied_size %= TAR_BLOCK_SIZE; + memset(bytebuf, 0, copied_size); + if (write(tar_fd, bytebuf, copied_size) != copied_size) { + close(fd); + return -1; + } + + close(fd); + } else { + DIR *dir; + struct dirent *dirent; + + dir = opendir(file_name); + if (dir == NULL) + return -1; + + while ((dirent = readdir(dir)) != NULL) { + char *sub_file_name; + int ret; + + sub_file_name = malloc(strlen(file_name) + + strlen(dirent->d_name) + 2); + if (sub_file_name == NULL) + return -1; + + sprintf(sub_file_name, "%s/%s", file_name, dirent->d_name); + ret = TarWriteFileRecursive(tar_fd, tar_statbuf, sub_file_name, verbose); + + free(sub_file_name); + + if (ret < 0) { + closedir(dir); + return -1; + } + } + closedir(dir); + } + + return 0; +} + +static int TarCreate(char *tar_name, int npaths, char **paths, int verbose) +{ + int tar_fd, written_size; + struct stat tar_statbuf; + + if (npaths == 0) + return 0; + + tar_fd = open(tar_name, O_WRONLY | O_CREAT | O_TRUNC); + if (tar_fd < 0) + return -1; + fstat(tar_fd, &tar_statbuf); + + for (int i = 0; i < npaths; i++) { + int len = strlen(paths[i]); + if (len > 1 && paths[i][len - 1] == '/') + paths[len - 1] = '\0'; + + if (TarWriteFileRecursive(tar_fd, &tar_statbuf, paths[i], verbose) < 0) { + close(tar_fd); + return -1; + } + } + + memset(bytebuf, 0, TAR_BLOCK_SIZE); + written_size = 0; + for (int i = 0; i < 2; i++) + written_size += write(tar_fd, bytebuf, TAR_BLOCK_SIZE); + + close(tar_fd); + + return written_size == 2 * TAR_BLOCK_SIZE ? 0 : -1; +} + +enum { + RET_SUCC = 0, + RET_EMPTY_HDR, + RET_EOF, +}; + +static int TarParseHeader(int tar_fd, int verbose) +{ + int ReadSize; + TarHdr_t hdr; + + + ReadSize = read(tar_fd, bytebuf, TAR_BLOCK_SIZE); + if (ReadSize == 0) + return RET_EOF; + if (ReadSize != TAR_BLOCK_SIZE) + return -1; + + memcpy(&hdr, bytebuf, TAR_BLOCK_SIZE); + + if (hdr.name[0] == '\0') + return RET_EMPTY_HDR; + + if (!IsPrefixedWith(hdr.magic, TAR_MAGIC_STR)) + return -1; + + int old_chksum = ScanOctal(hdr.chksum, sizeof(hdr.chksum)); + int correct_chksum = 0; + memset(hdr.chksum, ' ', sizeof(hdr.chksum)); + for (int i = 0; i < sizeof(TarHdr_t); i++) + correct_chksum += ((unsigned char *)&hdr)[i]; + if (old_chksum != correct_chksum) + return -1; + + if (hdr.typeflag != TYPE_REG && hdr.typeflag != TYPE_DIR) + return -1; + + char *file_name = RemoveUnsafePrefix(hdr.name); + + if (verbose) + KPrintf("%s\n", file_name); + + if (hdr.typeflag == TYPE_DIR) { + if (mkdir(file_name, 0777) < 0) + return -1; + return RET_SUCC; + } + + int size_to_write = ScanOctal(hdr.size, sizeof(hdr.size)); + int written_size; + + int fd = open(file_name, O_WRONLY | O_CREAT | O_TRUNC); + if (fd < 0) + return -1; + + while (size_to_write > 0) { + ReadSize = read(tar_fd, bytebuf, TAR_BLOCK_SIZE); + if (ReadSize != TAR_BLOCK_SIZE) { + close(fd); + return -1; + } + + written_size = write(fd, bytebuf, MIN(size_to_write, TAR_BLOCK_SIZE)); + if (written_size != MIN(size_to_write, TAR_BLOCK_SIZE)) { + close(fd); + return -1; + } + + size_to_write -= TAR_BLOCK_SIZE; + } + + close(fd); + + return RET_SUCC; +} + +static int TarExtract(char *tar_name, int verbose) +{ + int tar_fd, ret, empty_hdrs = 0; + struct stat tar_statbuf; + + if (stat(tar_name, &tar_statbuf) < 0) + return -1; + if (tar_statbuf.st_size % TAR_BLOCK_SIZE != 0) + return -1; + + tar_fd = open(tar_name, O_RDONLY); + if (tar_fd < 0) + return -1; + + while ((ret = TarParseHeader(tar_fd, verbose)) >= 0) { + if (ret == RET_EOF) { + ret = 0; + break; + } + if (ret == RET_EMPTY_HDR) { + empty_hdrs++; + if (empty_hdrs >= 2) { + ret = 0; + break; + } + } + else + empty_hdrs = 0; + } + close(tar_fd); + + return ret; +} + +void TarTruncateCmpExtension(char *file_name, int filter) +{ + switch (filter) { + case GZIP: + TruncateExtension(file_name, ".gz"); + break; + case BZIP2: + TruncateExtension(file_name, ".bz2"); + break; + } +} + +extern int GzipCompress(char *file_name); +extern int GzipDecompress(char *file_name); +extern int Bzip2Compress(char *file_name); +extern int Bzip2Decompress(char *file_name); + +static void TarPrintUsage() +{ + KPrintf("Usage: tar [OPTIONS]... [FILES]...\n"); + KPrintf("Supported option flags:\n"); + KPrintf(" c create a new tarball\n"); + KPrintf(" x extract files from an existing tarball\n"); + KPrintf(" f specify name of the tarball\n"); + KPrintf(" v show verbose status\n"); + KPrintf(" z filter the tarball through gzip\n"); + KPrintf(" j filter the tarball through bzip2\n"); +} + +int tar(int argc, char **argv) +{ + int flag_create = 0, flag_extract = 0, flag_file = 0, verbose = 0; + int filter = 0; + int ret = 0; + char *tar_name; + + if (argc < 2 || argv[1][0] != '-') { + TarPrintUsage(); + return 0; + } + + for (int i = 1; i < strlen(argv[1]); i++) + switch(argv[1][i]) { + case 'c': + flag_create = 1; + break; + case 'x': + flag_extract = 1; + break; + case 'f': + flag_file = 1; + break; + case 'z': + if (filter != 0) { + KPrintf("Bad options\n"); + return 0; + } + filter = GZIP; + break; + case 'j': + if (filter != 0) { + KPrintf("Bad options\n"); + return 0; + } + filter = BZIP2; + break; + case 'v': + verbose = 1; + break; + default: + KPrintf("Unknown option: %c\n", argv[1][i]); + return 0; + } + if (flag_create == flag_extract || flag_file == 0 || argc < 3) { + KPrintf("Bad options\n"); + TarPrintUsage(); + return 0; + } + + bytebuf = malloc(TAR_BLOCK_SIZE); + + tar_name = argv[2]; + if (flag_create) { + TarTruncateCmpExtension(tar_name, filter); + ret = TarCreate(tar_name, argc - 3, &argv[3], verbose); + if (ret == 0) { + switch (filter) { + case GZIP: + ret = GzipCompress(tar_name); + break; + case BZIP2: + ret = Bzip2Compress(tar_name); + break; + } + } + } else if (flag_extract) { + if (argc > 3) { + KPrintf("Too many arguments\n"); + ret = -1; + } else { + switch (filter) { + case GZIP: + ret = GzipDecompress(tar_name); + break; + case BZIP2: + ret = Bzip2Decompress(tar_name); + } + TarTruncateCmpExtension(tar_name, filter); + if (ret == 0) { + ret = TarExtract(tar_name, verbose); + } + } + } + + if (ret < 0) + KPrintf("Operation failed\n"); + + free(bytebuf); + + return 0; +} + + + +#endif diff --git a/Ubiquitous/XiZi/tool/shell/letter-shell/file_ext/tar.h b/Ubiquitous/XiZi/tool/shell/letter-shell/file_ext/tar.h new file mode 100644 index 0000000..498e9ad --- /dev/null +++ b/Ubiquitous/XiZi/tool/shell/letter-shell/file_ext/tar.h @@ -0,0 +1,59 @@ +/* + * Copyright (c) 2020 AIIT XUOS Lab + * XiUOS is licensed under Mulan PSL v2. + * You can use this software according to the terms and conditions of the Mulan PSL v2. + * You may obtain a copy of Mulan PSL v2 at: + * http://license.coscl.org.cn/MulanPSL2 + * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, + * EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, + * MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. + * See the Mulan PSL v2 for more details. +*/ + +#ifndef __INC_TAR_H__ +#define __INC_TAR_H__ + +#define TAR_BLOCK_SIZE 512 +#define TAR_FILE_NAME_LEN 100 +#define TAR_MAGIC_STR "ustar" + +#define ROUNDUP(a, align) (((a) + (align) - 1) & ~((align) - 1)) +#define MAX(a, b) ((a) > (b) ? (a) : (b)) +#define MIN(a, b) ((a) < (b) ? (a) : (b)) + +typedef struct TarHdr { + char name[TAR_FILE_NAME_LEN]; + char mode[8]; + char uid[8]; + char gid[8]; + char size[12]; + char mtime[12]; + char chksum[8]; + char typeflag; + char linkname[TAR_FILE_NAME_LEN]; + char magic[6]; + char version[2]; + char uname[32]; + char gname[32]; + char devmajor[8]; + char devminor[8]; + char prefix[155]; + char padding[12]; +} TarHdr_t; + +enum FileType { + TYPE_REG = '0', + TYPE_LNK = '1', + TYPE_SYM = '2', + TYPE_CHR = '3', + TYPE_BLK = '4', + TYPE_DIR = '5', + TYPE_FIFO = '6', +}; + +enum FilterType { + GZIP = 1, + BZIP2, +}; + +#endif diff --git a/Ubiquitous/XiZi/tool/shell/letter-shell/file_ext/unzip.c b/Ubiquitous/XiZi/tool/shell/letter-shell/file_ext/unzip.c new file mode 100644 index 0000000..4e66b31 --- /dev/null +++ b/Ubiquitous/XiZi/tool/shell/letter-shell/file_ext/unzip.c @@ -0,0 +1,283 @@ +/* + * Copyright (c) 2020 AIIT XUOS Lab + * XiUOS is licensed under Mulan PSL v2. + * You can use this software according to the terms and conditions of the Mulan PSL v2. + * You may obtain a copy of Mulan PSL v2 at: + * http://license.coscl.org.cn/MulanPSL2 + * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, + * EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, + * MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. + * See the Mulan PSL v2 for more details. +*/ + +#include + +#if defined(FS_VFS) && defined(TOOL_SHELL) + +#include +#include +#include +#include +#include +#include +#include "utility.h" +#include + +int zip_fd; + +static void ReadZipHdr(ZipHdr_t *zip_hdr) +{ + zip_hdr->version = read16Le(zip_fd); + zip_hdr->zip_flags = read16Le(zip_fd); + zip_hdr->method = read16Le(zip_fd); + zip_hdr->modtime = read16Le(zip_fd); + zip_hdr->moddate = read16Le(zip_fd); + zip_hdr->crc32 = read32Le(zip_fd); + zip_hdr->cmpsize = read32Le(zip_fd); + zip_hdr->ucmpsize = read32Le(zip_fd); + zip_hdr->filename_len = read16Le(zip_fd); + zip_hdr->extra_len = read16Le(zip_fd); +} + +static void ReadCdfHdr(CdfHdr_t *cdf_hdr) +{ + cdf_hdr->version_made_by = read16Le(zip_fd); + cdf_hdr->version_needed = read16Le(zip_fd); + cdf_hdr->cdf_flags = read16Le(zip_fd); + cdf_hdr->method = read16Le(zip_fd); + cdf_hdr->modtime = read16Le(zip_fd); + cdf_hdr->moddate = read16Le(zip_fd); + cdf_hdr->crc32 = read32Le(zip_fd); + cdf_hdr->cmpsize = read32Le(zip_fd); + cdf_hdr->ucmpsize = read32Le(zip_fd); + cdf_hdr->filename_len = read16Le(zip_fd); + cdf_hdr->extra_len = read16Le(zip_fd); + cdf_hdr->file_comment_len = read16Le(zip_fd); + cdf_hdr->disk_number_start = read16Le(zip_fd); + cdf_hdr->internal_attributes = read16Le(zip_fd); + cdf_hdr->external_attributes = read32Le(zip_fd); + cdf_hdr->local_header_offset = read32Le(zip_fd); +} + +static uint32_t FindCdfOffset() +{ + cde_t cde; + unsigned char *buf; + unsigned char *p; + size_t ReadSize; + off_t end; + uint32_t found = (uint32_t)-1; + + end = lseek(zip_fd, 0, SEEK_END); + if (end == -1) { + return (uint32_t)-1; + } + + buf = malloc(FIND_CDF_BUF_SIZE); + end = MAX(0, end - FIND_CDF_BUF_SIZE); + lseek(zip_fd, end, SEEK_SET); + ReadSize = read(zip_fd, buf, FIND_CDF_BUF_SIZE); + + p = buf; + while (p <= buf + ReadSize - sizeof(cde_t) - 4) { + if (*p != 'P') { + p++; + continue; + } + if (*(++p) != 'K') + continue; + if (*(++p) != 5) + continue; + if (*(++p) != 6) + continue; + memcpy(&cde, p + 1, sizeof(cde_t)); + char *tmp = (char *)&cde.cdf_offset; + uint32_t cdf_offset = 0; + for (int i = 0; i < 4; i++) + cdf_offset |= (uint32_t)tmp[i] << (i * 8); + if (cdf_offset < end + (p - buf)) + found = cdf_offset; + } + free(buf); + + return found; +} + +static uint32_t ReadNextCdf(uint32_t cdf_offset, CdfHdr_t *cdf_hdr) +{ + uint32_t magic; + + if (cdf_offset == (uint32_t)-1) + return (uint32_t)-1; + + lseek(zip_fd, cdf_offset, SEEK_SET); + + magic = read32Le(zip_fd); + if (magic == ZIP_CDE_MAGIC) + return 0; + + ReadCdfHdr(cdf_hdr); + cdf_offset += 4 + sizeof(CdfHdr_t) + + cdf_hdr->filename_len + + cdf_hdr->extra_len + + cdf_hdr->file_comment_len; + + return cdf_offset; +} + +static int CreateLeadingDir(char *path) { + int len = strlen(path); + char tmp; + struct stat statbuf; + + for (int i = 1; i < len; i++) + if (path[i] == '/') { + tmp = path[i]; + path[i] = '\0'; + if (stat(path, &statbuf) == 0 && S_ISDIR(statbuf.st_mode)) { + path[i] = tmp; + continue; + } + if (mkdir(path, 0777) < 0) { + path[i] = tmp; + return -1; + } + path[i] = tmp; + } + + return 0; +} + +static int ExtractUncompressedFile(int in_fd, int out_fd, uint32_t size) +{ + uint32_t size_read = 0; + uint32_t size_written = 0; + char *buf = malloc(512); + + if (buf == NULL) + return -1; + + while (size > 0) { + size_read = read(in_fd, buf, MIN(size, 512)); + size_written = write(out_fd, buf, size_read); + if (size_read != size_written) { + free(buf); + return -1; + } + size -= size_written; + } + free(buf); + + return 0; +} + +static int ExtractFile(ZipHdr_t *zip_hdr, int dst_fd) +{ + switch (zip_hdr->method) { + case 0: + return ExtractUncompressedFile(zip_fd, + dst_fd, zip_hdr->cmpsize); + case 8: + return InflateUnzip(zip_fd, dst_fd, zip_hdr->cmpsize, + zip_hdr->ucmpsize, zip_hdr->crc32); + default: + return -1; + } +} + +static int UnzipFile(char *path) +{ + int ret = 0; + uint32_t cdf_offset; + char *filename_buf = NULL; + + if ((zip_fd = open(path, O_RDONLY)) < 0) + return -1; + + cdf_offset = FindCdfOffset(); + if (cdf_offset == (uint32_t)-1) { + ret = -1; + } + while (1) { + if (cdf_offset == (uint32_t)-1) + break; + + CdfHdr_t cdf_hdr; + ZipHdr_t zip_hdr; + + cdf_offset = ReadNextCdf(cdf_offset, &cdf_hdr); + if (cdf_offset == 0) + break; + lseek(zip_fd, cdf_hdr.local_header_offset + 4, SEEK_SET); + ReadZipHdr(&zip_hdr); + if (zip_hdr.zip_flags & 0x8 || zip_hdr.zip_flags & 0x1) { + ret = -1; + break; + } + + if (filename_buf) + free(filename_buf); + filename_buf = malloc(zip_hdr.filename_len + 1); + if (filename_buf == NULL) { + ret = -1; + break; + } + read(zip_fd, filename_buf, zip_hdr.filename_len); + filename_buf[zip_hdr.filename_len] = '\0'; + lseek(zip_fd, zip_hdr.extra_len, SEEK_CUR); + + if (filename_buf[zip_hdr.filename_len - 1] == '/') { + KPrintf(" creating: %s\n", filename_buf); + if (CreateLeadingDir(filename_buf) < 0) { + ret = -1; + break; + } + lseek(zip_fd, zip_hdr.cmpsize, SEEK_SET); + } else { + if (CreateLeadingDir(filename_buf) < 0) { + ret = -1; + break; + } + int dst_fd = open(filename_buf, O_WRONLY | O_CREAT | O_TRUNC); + if (dst_fd < 0) { + ret = -1; + break; + } + KPrintf(" inflating: %s\n", filename_buf); + ExtractFile(&zip_hdr, dst_fd); + close(dst_fd); + } + } + if (filename_buf) + free(filename_buf); + + return ret; +} + +static void UnzipPrintUsage() +{ + KPrintf("Usage: unzip [FILES]...\n"); +} + +int unzip(int argc, char **argv) +{ + if (argc < 2) { + UnzipPrintUsage(); + return 0; + } + + for (int i = 1; i < argc; i++) { + if (!IsSuffixedWith(argv[i], ".zip")) { + KPrintf("Unvalid extension: %s\n", argv[i]); + continue; + } + KPrintf("Decompressing zip file: %s\n", argv[i]); + if (UnzipFile(argv[i]) < 0) + KPrintf("Unable to extract zip file: %s\n", argv[i]); + } + + return 0; +} + + +#endif diff --git a/Ubiquitous/XiZi/tool/shell/letter-shell/file_ext/unzip.h b/Ubiquitous/XiZi/tool/shell/letter-shell/file_ext/unzip.h new file mode 100644 index 0000000..9c878d5 --- /dev/null +++ b/Ubiquitous/XiZi/tool/shell/letter-shell/file_ext/unzip.h @@ -0,0 +1,70 @@ +/* + * Copyright (c) 2020 AIIT XUOS Lab + * XiUOS is licensed under Mulan PSL v2. + * You can use this software according to the terms and conditions of the Mulan PSL v2. + * You may obtain a copy of Mulan PSL v2 at: + * http://license.coscl.org.cn/MulanPSL2 + * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, + * EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, + * MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. + * See the Mulan PSL v2 for more details. +*/ + +#ifndef __INC_UNZIP_H__ +#define __INC_UNZIP_H__ + +#include + +typedef struct cde { + uint16_t this_disk_no; + uint16_t disk_with_cdf_no; + uint16_t cdf_entries_on_this_disk; + uint16_t cdf_entries_total; + uint32_t cdf_size; + uint32_t cdf_offset; +} cde_t; +char BUILD_BUG_CDE_SIZE[sizeof(cde_t) == 16 ? 0 : -1]; + +typedef struct ZipHdr { + uint16_t version; + uint16_t zip_flags; + uint16_t method; + uint16_t modtime; + uint16_t moddate; + uint32_t crc32 __attribute__ ((__packed__)); + uint32_t cmpsize __attribute__ ((__packed__)); + uint32_t ucmpsize __attribute__ ((__packed__)); + uint16_t filename_len; + uint16_t extra_len; +} __attribute__ ((__packed__)) ZipHdr_t; +char BUILD_BUG_ZIP_HDR_SIZE[sizeof(ZipHdr_t) == 26 ? 0 : -1]; + +typedef struct CdfHdr { + uint16_t version_made_by; + uint16_t version_needed; + uint16_t cdf_flags; + uint16_t method; + uint16_t modtime; + uint16_t moddate; + uint32_t crc32 __attribute__ ((__packed__)); + uint32_t cmpsize __attribute__ ((__packed__)); + uint32_t ucmpsize __attribute__ ((__packed__)); + uint16_t filename_len; + uint16_t extra_len; + uint16_t file_comment_len; + uint16_t disk_number_start; + uint16_t internal_attributes; + uint32_t external_attributes __attribute__ ((__packed__)); + uint32_t local_header_offset + __attribute__ ((__packed__)); +} __attribute__ ((__packed__)) CdfHdr_t; +char BUILD_BUG_CDF_HDR_SIZE[sizeof(CdfHdr_t) == 42 ? 0 : -1]; + +#define FIND_CDF_BUF_SIZE 1024 + +#define ZIP_FILEHEADER_MAGIC 0x04034b50 +#define ZIP_CDF_MAGIC 0x02014b50 +#define ZIP_CDE_MAGIC 0x06054b50 +#define ZIP_DD_MAGIC 0x08074b50 + +#endif diff --git a/Ubiquitous/XiZi/tool/shell/letter-shell/file_ext/utility.c b/Ubiquitous/XiZi/tool/shell/letter-shell/file_ext/utility.c new file mode 100644 index 0000000..f0f90c2 --- /dev/null +++ b/Ubiquitous/XiZi/tool/shell/letter-shell/file_ext/utility.c @@ -0,0 +1,121 @@ +/* + * Copyright (c) 2020 AIIT XUOS Lab + * XiUOS is licensed under Mulan PSL v2. + * You can use this software according to the terms and conditions of the Mulan PSL v2. + * You may obtain a copy of Mulan PSL v2 at: + * http://license.coscl.org.cn/MulanPSL2 + * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, + * EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, + * MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. + * See the Mulan PSL v2 for more details. +*/ + +#include + +#ifdef FS_VFS + +#include +#include +#include +#include "utility.h" + +int IsPrefixedWith(char *str, char *prefix) +{ + while (*prefix != '\0') { + if (*str != *prefix) + return 0; + str++; + prefix++; + } + return 1; +} + +char *RemoveUnsafePrefix(char *file_name) +{ + char *ret = file_name; + + while (1) { + if (*ret == '/') { + ret++; + continue; + } + if (IsPrefixedWith(ret, "/../" + 1)) { + ret += 3; + continue; + } + char *p = strstr(ret, "/../"); + if (!p) + break; + ret = p + 4; + } + + return ret; +} + +int IsSuffixedWith(char *file_name, char *suffix) +{ + int len = strlen(file_name); + int suff_len = strlen(suffix); + + return len > suff_len && + strcmp(&file_name[len - suff_len], suffix) == 0; +} + +int TruncateExtension(char *file_name, char *ext) +{ + int len = strlen(file_name); + int ext_len = strlen(ext); + + if (!IsSuffixedWith(file_name, ext)) + return -1; + + file_name[len - ext_len] = '\0'; + return 0; +} + +unsigned char read8(int fd) +{ + unsigned char ret; + + read(fd, &ret, 1); + + return ret; +} + +uint16_t read16Le(int fd) +{ + uint16_t ret = 0; + unsigned char buf[2]; + + read(fd, buf, 2); + for (int i = 0; i < 2; i++) + ret |= (uint16_t)buf[i] << (i * 8); + + return ret; +} + +uint32_t read32Le(int fd) +{ + uint32_t ret = 0; + unsigned char buf[4]; + + read(fd, buf, 4); + for (int i = 0; i < 4; i++) + ret |= (uint32_t)buf[i] << (i * 8); + + return ret; +} + +uint64_t read64Le(int fd) +{ + uint64_t ret = 0; + unsigned char buf[8]; + + read(fd, buf, 8); + for (int i = 0; i < 8; i++) + ret |= (uint32_t)buf[i] << (i * 8); + + return ret; +} + +#endif diff --git a/Ubiquitous/XiZi/tool/shell/letter-shell/file_ext/utility.h b/Ubiquitous/XiZi/tool/shell/letter-shell/file_ext/utility.h new file mode 100644 index 0000000..d2b4f6a --- /dev/null +++ b/Ubiquitous/XiZi/tool/shell/letter-shell/file_ext/utility.h @@ -0,0 +1,36 @@ +/* + * Copyright (c) 2020 AIIT XUOS Lab + * XiUOS is licensed under Mulan PSL v2. + * You can use this software according to the terms and conditions of the Mulan PSL v2. + * You may obtain a copy of Mulan PSL v2 at: + * http://license.coscl.org.cn/MulanPSL2 + * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, + * EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, + * MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. + * See the Mulan PSL v2 for more details. +*/ + +#ifndef __INC_UTILITY_H__ +#define __INC_UTILITY_H__ + +#include + +#ifndef MAX +#define MAX(a, b) ((a) > (b) ? (a) : (b)) +#endif + +#ifndef MIN +#define MIN(a, b) ((a) < (b) ? (a) : (b)) +#endif + +int IsPrefixedWith(char *str, char *prefix); +char *RemoveUnsafePrefix(char *file_name); +int IsSuffixedWith(char *file_name, char *suffix); +int TruncateExtension(char *file_name, char *ext); + +unsigned char read8(int fd); +uint16_t read16Le(int fd); +uint32_t read32Le(int fd); +uint64_t read64Le(int fd); + +#endif diff --git a/Ubiquitous/XiZi/tool/shell/letter-shell/shell.c b/Ubiquitous/XiZi/tool/shell/letter-shell/shell.c new file mode 100644 index 0000000..6a923ec --- /dev/null +++ b/Ubiquitous/XiZi/tool/shell/letter-shell/shell.c @@ -0,0 +1,1723 @@ +/** + * @file shell.c + * @author Letter (NevermindZZT@gmail.com) + * @version 3.0.0 + * @date 2019-12-30 + * + * @copyright (c) 2020 Letter + * + */ +/*change log: + Change Chinese comment to English comment +*/ + +#include "shell.h" +#include "string.h" +#include "stdio.h" +#include "stdarg.h" +#include "shell_ext.h" +#include +#ifdef FS_VFS +#include "iot-vfs.h" +#endif +#ifndef CommandDescSize +#define CommandDescSize 36 +#endif +/** + * @brief default user + */ +const char shellCmdDefaultUser[] = SHELL_DEFAULT_USER; +const char shellPasswordDefaultUser[] = SHELL_DEFAULT_USER_PASSWORD; +const char shellDesDefaultUser[] = "default user"; +const ShellCommand shellUserDefault SECTION("shellCommand") = +{ + .attr.value = SHELL_CMD_PERMISSION(0)|SHELL_CMD_TYPE(SHELL_TYPE_USER), + .data.user.name = shellCmdDefaultUser, + .data.user.password = shellPasswordDefaultUser, + .data.user.desc = shellDesDefaultUser +}; + + + + #if defined(__GNUC__) + extern const unsigned long _shell_command_start; + extern const unsigned long _shell_command_end; + #endif + +/** + * @brief shell Constant text index + */ +enum +{ + SHELL_TEXT_INFO, /**parser.length = 0; + shell->parser.cursor = 0; + shell->history.offset = 0; + shell->history.number = 0; + shell->history.record = 0; + shell->info.user = NULL; + shell->status.isChecked = 1; + + shell->parser.buffer = buffer; + shell->parser.bufferSize = size / (SHELL_HISTORY_MAX_NUMBER + 1); + for (short i = 0; i < SHELL_HISTORY_MAX_NUMBER; i++) + { + shell->history.item[i] = buffer + shell->parser.bufferSize * (i + 1); + } + + + + #if defined(__GNUC__) + shell->commandList.base = (ShellCommand *)(&_shell_command_start); + shell->commandList.count = ((unsigned long)(&_shell_command_end) + - (unsigned long)(&_shell_command_start)) + / sizeof(ShellCommand); + #else + #error not supported compiler, please use command table mode + #endif + + shellAdd(shell); + + shellSetUser(shell, shellSeekCommand(shell, + SHELL_DEFAULT_USER, + shell->commandList.base, + 0)); + + shellWriteCommandLine(shell, 1); +} + + +/** + * @brief Add shell + * + * @param shell shell + */ +static void shellAdd(Shell *shell) +{ + for (short i = 0; i < SHELL_MAX_NUMBER; i++) + { + if (shellList[i] == NULL) + { + shellList[i] = shell; + return; + } + } +} + + +/** + * @brief Get the current active shell + * + * @return Shell* Currently active shell object + */ +Shell* shellGetCurrent(void) +{ + for (short i = 0; i < SHELL_MAX_NUMBER; i++) + { + if (shellList[i] && shellList[i]->status.isActive) + { + return shellList[i]; + } + } + return NULL; +} + + +/** + * @brief Shell write characters + * + * @param shell shell + * @param data Character data + */ +static void shellWriteByte(Shell *shell, const char data) +{ + shell->write(data); +} + + +/** + * @brief shell Write string + * + * @param shell shell + * @param string String data + * + * @return unsigned short Number of characters written (include '\n') + */ +unsigned short shellWriteString(Shell *shell, const char *string) +{ + unsigned short count = 0; + CHECK(shell->write); + while(*string) + { + shell->write(*string ++); + count ++; + } + return count; +} + + +/** + * @brief Shell write command description string + * + * @param shell shell + * @param string String data + * + * @return unsigned short Number of characters written + */ +static unsigned short shellWriteCommandDesc(Shell *shell, const char *string) +{ + unsigned short count = 0; + CHECK(shell->write); + while(*string + && *string != '\r' + && *string != '\n' + && count < CommandDescSize) + { + shell->write(*string ++); + count ++; + if (count >= CommandDescSize && *(string + 1)) + { + shell->write('.'); + shell->write('.'); + shell->write('.'); + } + } + return count; +} + +#ifdef FS_VFS +extern char working_dir[]; +#endif +/** + * @brief Shell write new command line + * + * @param shell shell + * @param newline Bool ,Whether to write a line + * + */ +static void shellWriteCommandLine(Shell *shell, unsigned char newline) +{ + if (shell->status.isChecked) + { + if (newline) + { + shellWriteString(shell, "\r\n"); + } + shellWriteString(shell, shell->info.user->data.user.name); + shellWriteString(shell, ":"); +#ifdef FS_VFS + shellWriteString(shell,working_dir); +#endif + shellWriteString(shell, "$ "); + } + else + { + shellWriteString(shell, shellText[SHELL_TEXT_PASSWORD_HINT]); + } +} + + + + +/** + * @brief shell Check command permissions + * + * @param shell shell + * @param command ShellCommand + * + * @return signed char 0 The current user has the command authority + * @return signec char -1 The current user does not have the command authority + */ +signed char shellCheckPermission(Shell *shell, ShellCommand *command) +{ + return ((!command->attr.attrs.permission + || command->attr.attrs.type == SHELL_TYPE_USER + || (command->attr.attrs.permission + & shell->info.user->attr.attrs.permission)) + && (shell->status.isChecked + || command->attr.attrs.enableUnchecked)) + ? 0 : -1; +} + + +/** + * @brief int to hexadecimal string + * + * @param value int value + * @param buffer hexadecimal result + * + * @return signed char, data length after conversion + */ +signed char shellToHex(unsigned int value, char *buffer) +{ + char byte; + unsigned char i = 8; + buffer[8] = 0; + while (value) + { + byte = value & 0x0000000F; + buffer[--i] = (byte > 9) ? (byte + 87) : (byte + 48); + value >>= 4; + } + return 8 - i; +} + + +/** +* @brief int to decimal string + * + * @param value int value + * @param buffer decimal result + * + * @return signed char, data length after conversion + */ +signed char shellToDec(int value, char *buffer) +{ + unsigned char i = 11; + int v = value; + if (value < 0) + { + v = -value; + } + buffer[11] = 0; + while (v) + { + buffer[--i] = v % 10 + 48; + v /= 10; + } + if (value < 0) + { + buffer[--i] = '-'; + } + if (value == 0) { + buffer[--i] = '0'; + } + return 11 - i; +} + + +/** + * @brief shell string copy + * + * @param dest destination string + * @param src Source string + * @return Unsigned short ,String length + */ +static unsigned short shellStringCopy(char *dest, char* src) +{ + unsigned short count = 0; + while (*(src + count)) + { + *(dest + count) = *(src + count); + count++; + } + *(dest + count) = 0; + return count; +} + + +/** + * @brief Shell string comparison + * + * @param dest destination string + * @param src Source string + * @return unsigned short, Match length + */ +static unsigned short shellStringCompare(char* dest, char *src) +{ + unsigned short match = 0; + unsigned short i = 0; + + while (*(dest +i) && *(src + i)) + { + if (*(dest + i) != *(src +i)) + { + break; + } + match ++; + i++; + } + return match; +} + + +/** + * @brief shell get command name + * + * @param command command + * @return const char* ,Command name + */ +static const char* shellGetCommandName(ShellCommand *command) +{ + static char buffer[9]; + for (unsigned char i = 0; i < 9; i++) + { + buffer[i] = '0'; + } + if (command->attr.attrs.type <= SHELL_TYPE_CMD_FUNC) + { + return command->data.cmd.name; + } + else if (command->attr.attrs.type <= SHELL_TYPE_VAR_NODE) + { + return command->data.var.name; + } + else if (command->attr.attrs.type <= SHELL_TYPE_USER) + { + return command->data.user.name; + } + else + { + shellToHex(command->data.key.value, buffer); + return buffer; + } +} + + +/** + * @brief shell get command description + * + * @param command command + * @return const char* ,Command description + */ +static const char* shellGetCommandDesc(ShellCommand *command) +{ + if (command->attr.attrs.type <= SHELL_TYPE_CMD_FUNC) + { + return command->data.cmd.desc; + } + else if (command->attr.attrs.type <= SHELL_TYPE_VAR_NODE) + { + return command->data.var.desc; + } + else if (command->attr.attrs.type <= SHELL_TYPE_USER) + { + return command->data.user.desc; + } + else + { + return command->data.key.desc; + } +} + +/** + * @brief shell list items + * + * @param shell shell ojbect + * @param item ShellCommand item(func,user,key,variable...) + */ +void shellListItem(Shell *shell, ShellCommand *item) +{ + short spaceLength; + + spaceLength = 22 - shellWriteString(shell, shellGetCommandName(item)); + spaceLength = (spaceLength > 0) ? spaceLength : 4; + do { + shellWriteByte(shell, ' '); + } while (--spaceLength); + if (item->attr.attrs.type <= SHELL_TYPE_CMD_FUNC) + { + shellWriteString(shell, shellText[SHELL_TEXT_TYPE_CMD]); + } + else if (item->attr.attrs.type <= SHELL_TYPE_VAR_NODE) + { + shellWriteString(shell, shellText[SHELL_TEXT_TYPE_VAR]); + } + else if (item->attr.attrs.type <= SHELL_TYPE_USER) + { + shellWriteString(shell, shellText[SHELL_TEXT_TYPE_USER]); + } + else if (item->attr.attrs.type <= SHELL_TYPE_KEY) + { + shellWriteString(shell, shellText[SHELL_TEXT_TYPE_KEY]); + } + else + { + shellWriteString(shell, shellText[SHELL_TEXT_TYPE_NONE]); + } +#ifdef SHELL_HELP_SHOW_PERMISSION + shellWriteString(shell, " "); + for (signed char i = 7; i >= 0; i--) + { + shellWriteByte(shell, item->attr.attrs.permission & (1 << i) ? 'x' : '-'); + } +#endif + shellWriteString(shell, " "); + shellWriteCommandDesc(shell, shellGetCommandDesc(item)); + shellWriteString(shell, "\r\n"); +} + + +/** + * @brief shell lists all function commands + * + * @param shell shell + */ +void shellListCommand(Shell *shell) +{ + ShellCommand *base = (ShellCommand *)shell->commandList.base; + shellWriteString(shell, shellText[SHELL_TEXT_CMD_LIST]); + for (short i = 0; i < shell->commandList.count; i++) + { + if (base[i].attr.attrs.type <= SHELL_TYPE_CMD_FUNC + && shellCheckPermission(shell, &base[i]) == 0) + { + shellListItem(shell, &base[i]); + } + } +} + + +/** + * @brief shell list all variable + * + * @param shell shell + */ +void shellListVar(Shell *shell) +{ + ShellCommand *base = (ShellCommand *)shell->commandList.base; + shellWriteString(shell, shellText[SHELL_TEXT_VAR_LIST]); + for (short i = 0; i < shell->commandList.count; i++) + { + if (base[i].attr.attrs.type > SHELL_TYPE_CMD_FUNC + && base[i].attr.attrs.type <= SHELL_TYPE_VAR_NODE + && shellCheckPermission(shell, &base[i]) == 0) + { + shellListItem(shell, &base[i]); + } + } +} + + +/** + * @brief shell list all users + * + * @param shell shell + */ +void shellListUser(Shell *shell) +{ + ShellCommand *base = (ShellCommand *)shell->commandList.base; + shellWriteString(shell, shellText[SHELL_TEXT_USER_LIST]); + for (short i = 0; i < shell->commandList.count; i++) + { + if (base[i].attr.attrs.type > SHELL_TYPE_VAR_NODE + && base[i].attr.attrs.type <= SHELL_TYPE_USER + && shellCheckPermission(shell, &base[i]) == 0) + { + shellListItem(shell, &base[i]); + } + } +} + + +/** + * @brief shell list all keys + * + * @param shell shell + */ +void shellListKey(Shell *shell) +{ + ShellCommand *base = (ShellCommand *)shell->commandList.base; + shellWriteString(shell, shellText[SHELL_TEXT_KEY_LIST]); + for (short i = 0; i < shell->commandList.count; i++) + { + if (base[i].attr.attrs.type > SHELL_TYPE_USER + && base[i].attr.attrs.type <= SHELL_TYPE_KEY + && shellCheckPermission(shell, &base[i]) == 0) + { + shellListItem(shell, &base[i]); + } + } +} + + +/** + * @brief shell delete command line data + * + * @param shell shell + * @param length length of delete data + */ +void shellDeleteCommandLine(Shell *shell, unsigned char length) +{ + while (length--) + { + shellWriteString(shell, "\b \b"); + } +} + + +/** + * @brief shell clear command line data + * + * @param shell shell + */ +void shellClearCommandLine(Shell *shell) +{ + for (short i = shell->parser.length - shell->parser.cursor; i > 0; i--) + { + shellWriteByte(shell, ' '); + } + shellDeleteCommandLine(shell, shell->parser.length); +} + + +/** + * @brief shell Insert a character at the cursor position + * + * @param shell shell + * @param data charactoer + */ +void shellInsertByte(Shell *shell, char data) +{ + /* if data is too long to insert a character */ + if (shell->parser.length >= shell->parser.bufferSize - 1) + { + shellWriteString(shell, shellText[SHELL_TEXT_CMD_TOO_LONG]); + shellWriteCommandLine(shell, 1); + shellWriteString(shell, shell->parser.buffer); + return; + } + + /* insert character */ + if (shell->parser.cursor == shell->parser.length) + { + shell->parser.buffer[shell->parser.length++] = data; + shell->parser.buffer[shell->parser.length] = 0; + shell->parser.cursor++; + shellWriteByte(shell, data); + } + else if (shell->parser.cursor < shell->parser.length) + { + for (short i = shell->parser.length - shell->parser.cursor; i > 0; i--) + { + shell->parser.buffer[shell->parser.cursor + i] = + shell->parser.buffer[shell->parser.cursor + i - 1]; + } + shell->parser.buffer[shell->parser.cursor++] = data; + shell->parser.buffer[++shell->parser.length] = 0; + for (short i = shell->parser.cursor - 1; i < shell->parser.length; i++) + { + shellWriteByte(shell, shell->parser.buffer[i]); + } + for (short i = shell->parser.length - shell->parser.cursor; i > 0; i--) + { + shellWriteByte(shell, '\b'); + } + } +} + + +/** + * @brief shell delete character + * + * @param shell shell + * @param direction delete a character: + * {@code 1} Delete the character before the cursor + * {@code -1}Delete the character after the cursor + */ +void shellDeleteByte(Shell *shell, signed char direction) +{ + char offset = (direction == -1) ? 1 : 0; + + if ((shell->parser.cursor == 0 && direction == 1) + || (shell->parser.cursor == shell->parser.length && direction == -1)) + { + return; + } + if (shell->parser.cursor == shell->parser.length && direction == 1) + { + shell->parser.cursor--; + shell->parser.length--; + shell->parser.buffer[shell->parser.length] = 0; + shellDeleteCommandLine(shell, 1); + } + else + { + for (short i = offset; i < shell->parser.length - shell->parser.cursor; i++) + { + shell->parser.buffer[shell->parser.cursor + i - 1] = + shell->parser.buffer[shell->parser.cursor + i]; + } + shell->parser.length--; + if (!offset) + { + shell->parser.cursor--; + shellWriteByte(shell, '\b'); + } + shell->parser.buffer[shell->parser.length] = 0; + for (short i = shell->parser.cursor; i < shell->parser.length; i++) + { + shellWriteByte(shell, shell->parser.buffer[i]); + } + shellWriteByte(shell, ' '); + for (short i = shell->parser.length - shell->parser.cursor + 1; i > 0; i--) + { + shellWriteByte(shell, '\b'); + } + } +} + + +/** + * @brief shell Parsing parameters + * + * @param shell shell + */ +static void shellParserParam(Shell *shell) +{ + unsigned char quotes = 0; + unsigned char record = 1; + + for (short i = 0; i < SHELL_PARAMETER_MAX_NUMBER; i++) + { + shell->parser.param[i] = NULL; + } + + shell->parser.paramCount = 0; + for (unsigned short i = 0; i < shell->parser.length; i++) + { + if (quotes != 0 + || (shell->parser.buffer[i] != ' ' + && shell->parser.buffer[i] != 0)) + { + if (shell->parser.buffer[i] == '\"') + { + quotes = quotes ? 0 : 1; + } + if (record == 1) + { + if (shell->parser.paramCount < SHELL_PARAMETER_MAX_NUMBER) + { + shell->parser.param[shell->parser.paramCount++] = + &(shell->parser.buffer[i]); + } + record = 0; + } + if (shell->parser.buffer[i] == '\\' + && shell->parser.buffer[i + 1] != 0) + { + i++; + } + } + else + { + shell->parser.buffer[i] = 0; + record = 1; + } + } +} + + +/** + * @brief shell Remove the double quotes at the beginning and end of string parameters + * + * @param shell shell + */ +static void shellRemoveParamQuotes(Shell *shell) +{ + unsigned short paramLength; + for (unsigned short i = 0; i < shell->parser.paramCount; i++) + { + if (shell->parser.param[i][0] == '\"') + { + shell->parser.param[i][0] = 0; + shell->parser.param[i] = &shell->parser.param[i][1]; + } + paramLength = strlen(shell->parser.param[i]); + if (shell->parser.param[i][paramLength - 1] == '\"') + { + shell->parser.param[i][paramLength - 1] = 0; + } + } +} + + +/** + * @brief shell seeking command + * + * @param shell shell + * @param cmd command + * @param base command table base address + * @param compareLength Match string length + * @return ShellCommand* :find command + */ +ShellCommand* shellSeekCommand(Shell *shell, + const char *cmd, + ShellCommand *base, + unsigned short compareLength) +{ + const char *name; + unsigned short count = shell->commandList.count - + ((long)base - (long)shell->commandList.base) / sizeof(ShellCommand); + for (unsigned short i = 0; i < count; i++) + { + if (base[i].attr.attrs.type == SHELL_TYPE_KEY + || shellCheckPermission(shell, &base[i]) != 0) + { + continue; + } + name = shellGetCommandName(&base[i]); + if (!compareLength) + { + if (strncmp(cmd, name, strlen(cmd)) == 0) + { + return &base[i]; + } + } + else + { + if (strncmp(cmd, name, compareLength) == 0) + { + return &base[i]; + } + } + } + return NULL; +} + + +/** + * @brief shell Get variable value + * + * @param shell shell + * @param command command + * @return int value + */ +int shellGetVarValue(Shell *shell, ShellCommand *command) +{ + int value = 0; + switch (command->attr.attrs.type) + { + case SHELL_TYPE_VAR_INT: + value = *((int *)(command->data.var.value)); + break; + case SHELL_TYPE_VAR_SHORT: + value = *((short *)(command->data.var.value)); + break; + case SHELL_TYPE_VAR_CHAR: + value = *((char *)(command->data.var.value)); + break; + case SHELL_TYPE_VAR_STRING: + case SHELL_TYPE_VAR_POINT: + value = (long)(command->data.var.value); + break; + case SHELL_TYPE_VAR_NODE: + value = ((ShellNodeVarAttr *)command->data.var.value)->get ? + ((ShellNodeVarAttr *)command->data.var.value) + ->get(((ShellNodeVarAttr *)command->data.var.value)->var) : 0; + break; + default: + break; + } + return value; +} + + +/** + * @brief shell set variable value + * + * @param shell shell + * @param command command + * @param value value + * @return int value + */ +int shellSetVarValue(Shell *shell, ShellCommand *command, int value) +{ + if (command->attr.attrs.readOnly) + { + shellWriteString(shell, shellText[SHELL_TEXT_VAR_READ_ONLY_CANNOT_MODIFY]); + } + else + { + switch (command->attr.attrs.type) + { + case SHELL_TYPE_VAR_INT: + *((int *)(command->data.var.value)) = value; + break; + case SHELL_TYPE_VAR_SHORT: + *((short *)(command->data.var.value)) = value; + break; + case SHELL_TYPE_VAR_CHAR: + *((char *)(command->data.var.value)) = value; + break; + case SHELL_TYPE_VAR_STRING: + shellStringCopy(((char *)(command->data.var.value)), (char *)(long)value); + break; + case SHELL_TYPE_VAR_POINT: + shellWriteString(shell, shellText[SHELL_TEXT_POINT_CANNOT_MODIFY]); + break; + case SHELL_TYPE_VAR_NODE: + if (((ShellNodeVarAttr *)command->data.var.value)->set) + { + if (((ShellNodeVarAttr *)command->data.var.value)->var) + { + ((ShellNodeVarAttr *)command->data.var.value) + ->set(((ShellNodeVarAttr *)command->data.var.value)->var, value); + } + else + { + ((ShellNodeVarAttr *)command->data.var.value)->set(value); + } + } + break; + default: + break; + } + } + return shellShowVar(shell, command); +} + + +/** + * @brief shell print variable value + * + * @param shell shell + * @param command command + * @return int value + */ +static int shellShowVar(Shell *shell, ShellCommand *command) +{ + char buffer[12] = "00000000000"; + int value = shellGetVarValue(shell, command); + + shellWriteString(shell, command->data.var.name); + shellWriteString(shell, " = "); + + switch (command->attr.attrs.type) + { + case SHELL_TYPE_VAR_STRING: + shellWriteString(shell, "\""); + shellWriteString(shell, (char *)(long)value); + shellWriteString(shell, "\""); + break; + // case SHELL_TYPE_VAR_INT: + // case SHELL_TYPE_VAR_SHORT: + // case SHELL_TYPE_VAR_CHAR: + // case SHELL_TYPE_VAR_POINT: + default: + shellWriteString(shell, &buffer[11 - shellToDec(value, buffer)]); + shellWriteString(shell, ", 0x"); + for (short i = 0; i < 11; i++) + { + buffer[i] = '0'; + } + shellToHex(value, buffer); + shellWriteString(shell, buffer); + break; + } + + shellWriteString(shell, "\r\n"); + return value; +} + + +/** + * @brief shell set variable value + * + * @param name value name + * @param value value + * @return int value + */ +int shellSetVar(char *name, int value) +{ + Shell *shell = shellGetCurrent(); + if (shell == NULL) + { + return 0; + } + ShellCommand *command = shellSeekCommand(shell, + name, + shell->commandList.base, + 0); + if (!command) + { + shellWriteString(shell, shellText[SHELL_TEXT_VAR_NOT_FOUND]); + return 0; + } + if (command->attr.attrs.type < SHELL_TYPE_VAR_INT + || command->attr.attrs.type > SHELL_TYPE_VAR_NODE) + { + shellWriteString(shell, name); + shellWriteString(shell, shellText[SHELL_TEXT_NOT_VAR]); + return 0; + } + return shellSetVarValue(shell, command, value); +} +SHELL_EXPORT_CMD( +SHELL_CMD_PERMISSION(0)|SHELL_CMD_TYPE(SHELL_TYPE_CMD_FUNC)|SHELL_CMD_DISABLE_RETURN, +setVar, shellSetVar, set var); + + +/** + * @brief shell run command + * + * @param shell shell + * @param command command + * + * @return unsigned int command return value + */ +unsigned int shellRunCommand(Shell *shell, ShellCommand *command) +{ + int returnValue = 0; + shell->status.isActive = 1; + if (command->attr.attrs.type == SHELL_TYPE_CMD_MAIN) + { + shellRemoveParamQuotes(shell); + returnValue = command->data.cmd.function(shell->parser.paramCount, + shell->parser.param); + if (!command->attr.attrs.disableReturn) + { + shellWriteReturnValue(shell, returnValue); + } + } + else if (command->attr.attrs.type == SHELL_TYPE_CMD_FUNC) + { + returnValue = shellExtRun(shell, + command, + shell->parser.paramCount, + shell->parser.param); + if (!command->attr.attrs.disableReturn) + { + shellWriteReturnValue(shell, returnValue); + } + } + else if (command->attr.attrs.type >= SHELL_TYPE_VAR_INT + && command->attr.attrs.type <= SHELL_TYPE_VAR_NODE) + { + shellShowVar(shell, command); + } + else if (command->attr.attrs.type == SHELL_TYPE_USER) + { + shellSetUser(shell, command); + } + shell->status.isActive = 0; + + return returnValue; +} + + +/** + * @brief shell check password + * + * @param shell shell + */ +static void shellCheckPassword(Shell *shell) +{ + if (strcmp(shell->parser.buffer, shell->info.user->data.user.password) == 0) + { + shell->status.isChecked = 1; + shellWriteString(shell, shellText[SHELL_TEXT_INFO]); + } + else + { + shellWriteString(shell, shellText[SHELL_TEXT_PASSWORD_ERROR]); + } + shell->parser.length = 0; + shell->parser.cursor = 0; +} + + +/** + * @brief shell set user + * + * @param shell shell + * @param user user + */ +static void shellSetUser(Shell *shell, const ShellCommand *user) +{ + shell->info.user = user; + shell->status.isChecked = + ((user->data.user.password && strlen(user->data.user.password) != 0) + && (shell->parser.paramCount < 2 + || strcmp(user->data.user.password, shell->parser.param[1]) != 0)) + ? 0 : 1; + + if (shell->status.isChecked) + { + shellWriteString(shell, shellText[SHELL_TEXT_INFO]); + } +} + + +/** + * @brief shell write return value + * + * @param shell shell + * @param value value + */ +static void shellWriteReturnValue(Shell *shell, int value) +{ + char buffer[12] = "00000000000"; + shellWriteString(shell, "Return: "); + shellWriteString(shell, &buffer[11 - shellToDec(value, buffer)]); + shellWriteString(shell, ", 0x"); + for (short i = 0; i < 11; i++) + { + buffer[i] = '0'; + } + shellToHex(value, buffer); + shellWriteString(shell, buffer); + shellWriteString(shell, "\r\n"); +} + + +/** + * @brief shell add history + * + * @param shell shell + */ +static void shellHistoryAdd(Shell *shell) +{ + shell->history.offset = 0; + if (shell->history.number > 0 + && strcmp(shell->history.item[(shell->history.record == 0 ? + SHELL_HISTORY_MAX_NUMBER : shell->history.record) - 1], + shell->parser.buffer) == 0) + { + return; + } + if (shellStringCopy(shell->history.item[shell->history.record], + shell->parser.buffer) != 0) + { + shell->history.record++; + } + if (++shell->history.number > SHELL_HISTORY_MAX_NUMBER) + { + shell->history.number = SHELL_HISTORY_MAX_NUMBER; + } + if (shell->history.record >= SHELL_HISTORY_MAX_NUMBER) + { + shell->history.record = 0; + } +} + + +/** + * @brief shell history find + * + * @param shell shell + * @param dir directory:{@code <0}UP, {@code >0}Down + */ +static void shellHistory(Shell *shell, signed char dir) +{ + if (dir > 0) + { + if (shell->history.offset-- <= + -((shell->history.number > shell->history.record) ? + shell->history.number : shell->history.record)) + { + shell->history.offset = -((shell->history.number > shell->history.record) + ? shell->history.number : shell->history.record); + } + } + else if (dir < 0) + { + if (++shell->history.offset > 0) + { + shell->history.offset = 0; + return; + } + } + else + { + return; + } + shellClearCommandLine(shell); + if (shell->history.offset == 0) + { + shell->parser.cursor = shell->parser.length = 0; + } + else + { + if ((shell->parser.length = shellStringCopy(shell->parser.buffer, + shell->history.item[(shell->history.record + SHELL_HISTORY_MAX_NUMBER + + shell->history.offset) % SHELL_HISTORY_MAX_NUMBER])) == 0) + { + return; + } + shell->parser.cursor = shell->parser.length; + shellWriteString(shell, shell->parser.buffer); + } + +} + + +/** + * @brief shell normalinput + * + * @param shell shell + * @param data input character + */ +void shellNormalInput(Shell *shell, char data) +{ + shell->status.tabFlag = 0; + shellInsertByte(shell, data); +} + + +/** + * @brief shell run command + * + * @param shell shell + */ +void shellExec(Shell *shell) +{ + + if (shell->parser.length == 0) + { + return; + } + + shell->parser.buffer[shell->parser.length] = 0; + + if (shell->status.isChecked) + { + shellHistoryAdd(shell); + shellParserParam(shell); + shell->parser.length = shell->parser.cursor = 0; + if (shell->parser.paramCount == 0) + { + return; + } + shellWriteString(shell, "\r\n"); + + ShellCommand *command = shellSeekCommand(shell, + shell->parser.param[0], + shell->commandList.base, + 0); + if (command != NULL) + { + shellRunCommand(shell, command); + } + else + { + shellWriteString(shell, shellText[SHELL_TEXT_CMD_NOT_FOUND]); + } + } + else + { + shellCheckPassword(shell); + } +} + + +/** + * @brief shell Previous history + * + * @param shell shell + */ +void shellUp(Shell *shell) +{ + shellHistory(shell, 1); +} +SHELL_EXPORT_KEY(SHELL_CMD_PERMISSION(0), 0x1B5B4100, shellUp, up); + + +/** + * @brief shell Next + * + * @param shell shell + */ +void shellDown(Shell *shell) +{ + shellHistory(shell, -1); +} +SHELL_EXPORT_KEY(SHELL_CMD_PERMISSION(0), 0x1B5B4200, shellDown, down); + + +/** + * @brief shell input right key + * + * @param shell shell + */ +void shellRight(Shell *shell) +{ + if (shell->parser.cursor < shell->parser.length) + { + shellWriteByte(shell, shell->parser.buffer[shell->parser.cursor++]); + } +} +SHELL_EXPORT_KEY(SHELL_CMD_PERMISSION(0)|SHELL_CMD_ENABLE_UNCHECKED, +0x1B5B4300, shellRight, right); + + +/** + * @brief shell input left key + * + * @param shell shell + */ +void shellLeft(Shell *shell) +{ + if (shell->parser.cursor > 0) + { + shellWriteByte(shell, '\b'); + shell->parser.cursor--; + } +} +SHELL_EXPORT_KEY(SHELL_CMD_PERMISSION(0)|SHELL_CMD_ENABLE_UNCHECKED, +0x1B5B4400, shellLeft, left); + + +/** + * @brief shell Tab key function + * + * @param shell shell + */ +void shellTab(Shell *shell) +{ + unsigned short maxMatch = shell->parser.bufferSize; + unsigned short lastMatchIndex = 0; + unsigned short matchNum = 0; + unsigned short length; + + if (shell->parser.length == 0) + { + shellListCommand(shell); + shellWriteCommandLine(shell, 1); + } + else if (shell->parser.length > 0) + { + shell->parser.buffer[shell->parser.length] = 0; + ShellCommand *base = (ShellCommand *)shell->commandList.base; + for (short i = 0; i < shell->commandList.count; i++) + { + if (shellCheckPermission(shell, &base[i]) == 0 + && shellStringCompare(shell->parser.buffer, + (char *)shellGetCommandName(&base[i])) + == shell->parser.length) + { + if (matchNum != 0) + { + if (matchNum == 1) + { + shellWriteString(shell, "\r\n"); + } + shellListItem(shell, &base[lastMatchIndex]); + length = + shellStringCompare((char *)shellGetCommandName(&base[lastMatchIndex]), + (char *)shellGetCommandName(&base[i])); + maxMatch = (maxMatch > length) ? length : maxMatch; + } + lastMatchIndex = i; + matchNum++; + } + } + if (matchNum == 0) + { + return; + } + if (matchNum == 1) + { + shellClearCommandLine(shell); + } + if (matchNum != 0) + { + shell->parser.length = + shellStringCopy(shell->parser.buffer, + (char *)shellGetCommandName(&base[lastMatchIndex])); + } + if (matchNum > 1) + { + shellListItem(shell, &base[lastMatchIndex]); + shellWriteCommandLine(shell, 1); + shell->parser.length = maxMatch; + } + shell->parser.buffer[shell->parser.length] = 0; + shell->parser.cursor = shell->parser.length; + shellWriteString(shell, shell->parser.buffer); + } + + if (SHELL_GET_TICK()) + { + if (matchNum == 1 + && shell->status.tabFlag + && SHELL_GET_TICK() - shell->info.activeTime < 200) + { + shellClearCommandLine(shell); + for (short i = shell->parser.length; i >= 0; i--) + { + shell->parser.buffer[i + 5] = shell->parser.buffer[i]; + } + shellStringCopy(shell->parser.buffer, "help"); + shell->parser.buffer[4] = ' '; + shell->parser.length += 5; + shell->parser.cursor = shell->parser.length; + shellWriteString(shell, shell->parser.buffer); + } + else + { + shell->status.tabFlag = 1; + } + } +} +SHELL_EXPORT_KEY(SHELL_CMD_PERMISSION(0), 0x09000000, shellTab, tab); + + +/** + * @brief shell backspace + * + * @param shell shell + */ +void shellBackspace(Shell *shell) +{ + shellDeleteByte(shell, 1); +} +SHELL_EXPORT_KEY(SHELL_CMD_PERMISSION(0)|SHELL_CMD_ENABLE_UNCHECKED, +0x08000000, shellBackspace, backspace); +SHELL_EXPORT_KEY(SHELL_CMD_PERMISSION(0)|SHELL_CMD_ENABLE_UNCHECKED, +0x7F000000, shellBackspace, backspace); + + +/** + * @brief shell delet + * + * @param shell shell + */ +void shellDelete(Shell *shell) +{ + shellDeleteByte(shell, -1); +} +SHELL_EXPORT_KEY(SHELL_CMD_PERMISSION(0)|SHELL_CMD_ENABLE_UNCHECKED, +0x1B5B337E, shellDelete, delete); + + +/** + * @brief shell Enter key + * + * @param shell shell + */ +void shellEnter(Shell *shell) +{ + shellExec(shell); + shellWriteCommandLine(shell, 1); +} +#ifdef SHELL_ENTER_LF +SHELL_EXPORT_KEY(SHELL_CMD_PERMISSION(0)|SHELL_CMD_ENABLE_UNCHECKED, +0x0A000000, shellEnter, enter); +#endif +#ifdef SHELL_ENTER_CR +SHELL_EXPORT_KEY(SHELL_CMD_PERMISSION(0)|SHELL_CMD_ENABLE_UNCHECKED, +0x0D000000, shellEnter, enter); +#endif +#ifdef SHELL_ENTER_CRLF +SHELL_EXPORT_KEY(SHELL_CMD_PERMISSION(0)|SHELL_CMD_ENABLE_UNCHECKED, +0x0D0A0000, shellEnter, enter); +#endif + +/** + * @brief shell help + * + * @param argc Number of parameters + * @param argv parameter + */ +void shellHelp(int argc, char *argv[]) +{ + Shell *shell = shellGetCurrent(); + CHECK(shell); + if (argc == 1) + { + shellListCommand(shell); + } + else if (argc > 1) + { + ShellCommand *command = shellSeekCommand(shell, + argv[1], + shell->commandList.base, + 0); + shellWriteString(shell, shellText[SHELL_TEXT_HELP_HEADER]); + shellWriteString(shell, shellGetCommandName(command)); + shellWriteString(shell, "\r\n"); + shellWriteString(shell, shellGetCommandDesc(command)); + shellWriteString(shell, "\r\n"); + } +} +SHELL_EXPORT_CMD( +SHELL_CMD_PERMISSION(0)|SHELL_CMD_TYPE(SHELL_TYPE_CMD_MAIN)|SHELL_CMD_DISABLE_RETURN, +Help, shellHelp, show command info\r\nhelp [cmd]); + +/** + * @brief shell Input processing + * + * @param shell shell + * @param data input data + */ +void shellHandler(Shell *shell, char data) +{ + CHECK(data); + + +#if SHELL_LOCK_TIMEOUT > 0 + if (shell->info.user->data.user.password + && strlen(shell->info.user->data.user.password) != 0 + && SHELL_GET_TICK()) + { + if (SHELL_GET_TICK() - shell->info.activeTime > SHELL_LOCK_TIMEOUT) + { + shell->status.isChecked = 0; + } + } +#endif + /* Calculate the offset of the current byte in the key value according to the recorded key value */ + char keyByteOffset = 24; + int keyFilter = 0x00000000; + if ((shell->parser.keyValue & 0x0000FF00) != 0x00000000) + { + keyByteOffset = 0; + keyFilter = 0xFFFFFF00; + } + else if ((shell->parser.keyValue & 0x00FF0000) != 0x00000000) + { + keyByteOffset = 8; + keyFilter = 0xFFFF0000; + } + else if ((shell->parser.keyValue & 0xFF000000) != 0x00000000) + { + keyByteOffset = 16; + keyFilter = 0xFF000000; + } + + /* Traverse the Shell Command list and try to match the key value */ + ShellCommand *base = (ShellCommand *)shell->commandList.base; + for (short i = 0; i < shell->commandList.count; i++) + { + /* Determine whether it is a key definition and verify permissions */ + if (base[i].attr.attrs.type == SHELL_TYPE_KEY + && shellCheckPermission(shell, &(base[i])) == 0) + { + /* Match the entered byte with the key value */ + if ((base[i].data.key.value & keyFilter) == shell->parser.keyValue + && (base[i].data.key.value & (0xFF << keyByteOffset)) + == (data << keyByteOffset)) + { + shell->parser.keyValue |= data << keyByteOffset; + data = 0x00; + if (keyByteOffset == 0 + || (base[i].data.key.value & (0xFF << (keyByteOffset - 8))) + == 0x00000000) + { + if (base[i].data.key.function) + { + base[i].data.key.function(shell); + } + shell->parser.keyValue = 0x00000000; + break; + } + } + } + } + + if (data != 0x00) + { + shell->parser.keyValue = 0x00000000; + shellNormalInput(shell, data); + } + + if (SHELL_GET_TICK()) + { + shell->info.activeTime = SHELL_GET_TICK(); + } +} + + + + + +/** + * @brief shell task + * + * @param param parameter(shell) + * + */ +void shellTask(void *param) +{ + // KPrintf("this is in 1733"); + Shell *shell = (Shell *)param; + + /* One input key from the the keyboard/uart may consist of mutliple characters (e.g., arrow keys). */ + char data[KEY_LENGTH]; + int i; + char data_len; + + while(RET_TRUE) + { + if (shell->read) { + data_len = shell->read(data); + for (i = 0; i < data_len; i++) { + shellHandler(shell, data[i]); + } + } + } +} + + +/** + * @brief Output user list (shell call) + */ +void shellUsers(void) +{ + Shell *shell = shellGetCurrent(); + if (shell) + { + shellListUser(shell); + } +} +#ifdef SHELL_HELP_LIST_USER +SHELL_EXPORT_CMD( +SHELL_CMD_PERMISSION(0)|SHELL_CMD_TYPE(SHELL_TYPE_CMD_FUNC)|SHELL_CMD_DISABLE_RETURN, +users, shellUsers, list all user); +#endif + + +/** + * @brief Output variable list (shell call) + */ +void shellVars(void) +{ + Shell *shell = shellGetCurrent(); + if (shell) + { + shellListVar(shell); + } +} +#ifdef SHELL_HELP_LIST_VAR +SHELL_EXPORT_CMD( +SHELL_CMD_PERMISSION(0)|SHELL_CMD_TYPE(SHELL_TYPE_CMD_FUNC)|SHELL_CMD_DISABLE_RETURN, +vars, shellVars, list all var); +#endif + +/** + * @brief Output key list (shell call) + */ +void shellKeys(void) +{ + Shell *shell = shellGetCurrent(); + if (shell) + { + shellListKey(shell); + } +} +#ifdef SHELL_HELP_LIST_KEY +SHELL_EXPORT_CMD( +SHELL_CMD_PERMISSION(0)|SHELL_CMD_TYPE(SHELL_TYPE_CMD_FUNC)|SHELL_CMD_DISABLE_RETURN, +keys, shellKeys, list all key); +#endif +/** + * @brief Clear the console (shell call) + */ +void shellClear(void) +{ + Shell *shell = shellGetCurrent(); + if (shell) + { + shellWriteString(shell, shellText[SHELL_TEXT_CLEAR_CONSOLE]); + } +} +SHELL_EXPORT_CMD( +SHELL_CMD_PERMISSION(0)|SHELL_CMD_TYPE(SHELL_TYPE_CMD_FUNC)|SHELL_CMD_DISABLE_RETURN, +clear, shellClear, clear console); \ No newline at end of file diff --git a/Ubiquitous/XiZi/tool/shell/letter-shell/shell.h b/Ubiquitous/XiZi/tool/shell/letter-shell/shell.h new file mode 100644 index 0000000..75084d6 --- /dev/null +++ b/Ubiquitous/XiZi/tool/shell/letter-shell/shell.h @@ -0,0 +1,276 @@ +/** + * @file shell.h + * @author Letter (NevermindZZT@gmail.com) + * @brief letter shell + * @version 3.0.0 + * @date 2019-12-30 + * + * @copyright (c) 2020 Letter + * + */ + +#ifndef __SHELL_H__ +#define __SHELL_H__ + +#include "xsconfig.h" +#include "stdlib.h" + +#define SHELL_VERSION "3.0.5" /**< version */ + + +/** + * @brief get system time (ms) + * + * @note When this macro is not defined, + * you cannot use double-clicking the tab to complete the command help, + * and you cannot use the shell timeout lock + */ +#define SHELL_GET_TICK() CalculteTimeMsFromTick(CurrentTicksGain()) + + +/** + * @brief shell permitt + * + * @param permission permission level + */ +#define SHELL_CMD_PERMISSION(permission) \ + (permission & 0x000000FF) + +/** + * @brief shell COMMAND TYPE + * + * @param type type of command + */ +#define SHELL_CMD_TYPE(type) \ + ((type & 0x0000000F) << 8) + +/** + * @brief Enable command without verifying the password + */ +#define SHELL_CMD_ENABLE_UNCHECKED \ + (1 << 12) + +/** + * @brief Disable print return value + */ +#define SHELL_CMD_DISABLE_RETURN \ + (1 << 13) + +/** + * @brief Read-only attributes (only valid for variables) + */ +#define SHELL_CMD_READ_ONLY \ + (1 << 14) + +/** + * @brief Number of command parameters + */ +#define SHELL_CMD_PARAM_NUM(num) \ + ((num & 0x0000000F)) << 16 + + /** + * @brief shell Command definition + * + * @param _attr Command attributes + * @param _name Command name + * @param _func Command function + * @param _desc Command description + */ + #define SHELL_EXPORT_CMD(_attr, _name, _func, _desc) \ + const char shellCmd##_name[] = #_name; \ + const char shellDesc##_name[] = #_desc; \ + const ShellCommand \ + shellCommand##_name SECTION("shellCommand") = \ + { \ + .attr.value = _attr, \ + .data.cmd.name = shellCmd##_name, \ + .data.cmd.function = (int (*)())_func, \ + .data.cmd.desc = shellDesc##_name \ + } + + + /** + * @brief shell variable definition + * + * @param _attr Command attributes + * @param _name Command name + * @param _value Command function + * @param _desc Command description + */ + #define SHELL_EXPORT_VAR(_attr, _name, _value, _desc) \ + const char shellCmd##_name[] = #_name; \ + const char shellDesc##_name[] = #_desc; \ + const ShellCommand \ + shellVar##_name SECTION("shellCommand") = \ + { \ + .attr.value = _attr, \ + .data.var.name = shellCmd##_name, \ + .data.var.value = (void *)_value, \ + .data.var.desc = shellDesc##_name \ + } + + + + /** + * @brief shell Key definition + * + * @param _attr Key attributes + * @param _value Key value + * @param _func Key function + * @param _desc Key description + */ + #define SHELL_EXPORT_KEY(_attr, _value, _func, _desc) \ + const char shellDesc##_value[] = #_desc; \ + const ShellCommand \ + shellKey##_value SECTION("shellCommand") = \ + { \ + .attr.value = _attr|SHELL_CMD_TYPE(SHELL_TYPE_KEY), \ + .data.key.value = _value, \ + .data.key.function = (void (*)(Shell *))_func, \ + .data.key.desc = shellDesc##_value \ + } + + + +/** + * @brief shell command type + */ +typedef enum +{ + SHELL_TYPE_CMD_MAIN = 0, /**< main function form command */ + SHELL_TYPE_CMD_FUNC, /**< C function form command */ + SHELL_TYPE_VAR_INT, /**< int variable */ + SHELL_TYPE_VAR_SHORT, /**< short variable */ + SHELL_TYPE_VAR_CHAR, /**< char variable */ + SHELL_TYPE_VAR_STRING, /**< string variable */ + SHELL_TYPE_VAR_POINT, /**< point variable */ + SHELL_TYPE_VAR_NODE, /**< node variable*/ + SHELL_TYPE_USER, /**< user */ + SHELL_TYPE_KEY, /**< Key */ +} ShellCommandType; + + +/** + * @brief Shell definition + */ +typedef struct shell_def +{ + struct + { + const struct shell_command *user; /**< Current user */ + int activeTime; /**< shell activation time */ + char *path; /**< Current shell path */ + + } info; + struct + { + unsigned short length; /**< Input data length */ + unsigned short cursor; /**< Current cursor position */ + char *buffer; /**< Input buffer */ + char *param[SHELL_PARAMETER_MAX_NUMBER]; /**< parameter */ + unsigned short bufferSize; /**< Input buffer size */ + unsigned short paramCount; /**< Number of parameters */ + int keyValue; /**< Enter key value */ + } parser; + struct + { + char *item[SHELL_HISTORY_MAX_NUMBER]; /**< history record */ + unsigned short number; /**< Number of history records */ + unsigned short record; /**< Current record location */ + signed short offset; /**< Current history offset */ + } history; + struct + { + void *base; /**< Command table base address */ + unsigned short count; /**< Number of commands */ + } commandList; + struct + { + unsigned char isChecked : 1; /**< Password verification passed */ + unsigned char isActive : 1; /**< Current active Shell */ + unsigned char tabFlag : 1; /**< tab Flag */ + } status; + signed char (*read)(char *); /**< shell read function */ + void (*write)(const char); /**< shell write function */ +} Shell; + + +/** + * @brief shell command definition + */ +typedef struct shell_command +{ + union + { + struct + { + unsigned char permission : 8; /**< command permission */ + ShellCommandType type : 4; /**< command type*/ + unsigned char enableUnchecked : 1; /**< Enable when Unchecked */ + unsigned char disableReturn : 1; /**< Disable return value output */ + unsigned char readOnly : 1; /**< readOnly */ + unsigned char reserve : 1; /**< reserve*/ + unsigned char paramNum : 4; /**< Number of parameters */ + } attrs; + int value; + } attr; /**< attribution */ + union + { + struct + { + const char *name; /**< name */ + int (*function)(); /**< function */ + const char *desc; /**< Command description */ + } cmd; /**< Command definition */ + struct + { + const char *name; /**< varibale name */ + void *value; /**< value of variable */ + const char *desc; /**< Variable description */ + } var; /**< variable definition */ + struct + { + const char *name; /**< user name */ + const char *password; /**< user's password */ + const char *desc; /**< user's description */ + } user; /**< user definition */ + struct + { + int value; /**< key value */ + void (*function)(Shell *); /**< funciton for key */ + const char *desc; /**< key description */ + } key; /**< key definition */ + } data; +} ShellCommand; + +/** + * @brief Shell node variable attributes + */ +typedef struct +{ + void *var; /**< Variable reference */ + int (*get)(); /**< Variable get method */ + int (*set)(); /**< Variable set method */ +} ShellNodeVarAttr; + + +#define shellSetPath(_shell, _path) (_shell)->info.path = _path +#define shellGetPath(_shell) ((_shell)->info.path) +#define KEY_LENGTH 8 + +void shellInit(Shell *shell, char *buffer, unsigned short size); +unsigned short shellWriteString(Shell *shell, const char *string); +Shell* shellGetCurrent(void); +void shellHandler(Shell *shell, char data); +void shellTask(void *param); + + + + +signed char shellCompanionAdd(Shell *shell, int id, void *object); +signed char shellCompanionDel(Shell *shell, int id); +void *shellCompanionGet(Shell *shell, int id); + + +#endif + diff --git a/Ubiquitous/XiZi/tool/shell/letter-shell/shell_ext.c b/Ubiquitous/XiZi/tool/shell/letter-shell/shell_ext.c new file mode 100644 index 0000000..bfea74d --- /dev/null +++ b/Ubiquitous/XiZi/tool/shell/letter-shell/shell_ext.c @@ -0,0 +1,351 @@ +/** + * @file shell_ext.c + * @author Letter (NevermindZZT@gmail.com) + * @brief shell extensions + * @version 3.0.0 + * @date 2019-12-31 + * + * @copyright (c) 2019 Letter + * + */ + +#include "shell.h" +#include "shell_ext.h" + + +extern ShellCommand* shellSeekCommand(Shell *shell, + const char *cmd, + ShellCommand *base, + unsigned short compareLength); +extern int shellGetVarValue(Shell *shell, ShellCommand *command); + +/** + * @brief Judging the number base + * + * @param string Parameter string + * @return NUM_Type Base + */ +static NUM_Type shellExtNumType(char *string) +{ + char *p = string; + NUM_Type type = NUM_TYPE_INT; + + if ((*p == '0') && ((*(p + 1) == 'x') || (*(p + 1) == 'X'))) + { + type = NUM_TYPE_HEX; + } + else if ((*p == '0') && ((*(p + 1) == 'b') || (*(p + 1) == 'B'))) + { + type = NUM_TYPE_BIN; + } + else if (*p == '0') + { + type = NUM_TYPE_OCT; + } + + while (*p++) + { + if (*p == '.' && *(p + 1) != 0) + { + type = NUM_TYPE_FLOAT; + break; + } + } + + return type; +} + + +/** + * @brief character to number + * + * @param code character + * @return char number + */ +static char shellExtToNum(char code) +{ + if ((code >= '0') && (code <= '9')) + { + return code -'0'; + } + else if ((code >= 'a') && (code <= 'f')) + { + return code - 'a' + 10; + } + else if ((code >= 'A') && (code <= 'F')) + { + return code - 'A' + 10; + } + else + { + return 0; + } +} + + +/** + * @brief Parse character parameters + * + * @param string String parameter + * @return char Parsed character + */ +static char shellExtParseChar(char *string) +{ + char *p = string + 1; + char value = 0; + + if (*p == '\\') + { + switch (*(p + 1)) + { + case 'b': + value = '\b'; + break; + case 'r': + value = '\r'; + break; + case 'n': + value = '\n'; + break; + case 't': + value = '\t'; + break; + case '0': + value = 0; + break; + default: + value = *(p + 1); + break; + } + } + else + { + value = *p; + } + return value; +} + + +/** + * @brief Parse string parameters + * + * @param string String parameter + * @return char* Parsed string + */ +static char* shellExtParseString(char *string) +{ + char *p = string; + unsigned short index = 0; + + if (*string == '\"') + { + p = ++string; + } + + while (*p) + { + if (*p == '\\') + { + *(string + index) = shellExtParseChar(p - 1); + p++; + } + else if (*p == '\"') + { + *(string + index) = 0; + } + else + { + *(string + index) = *p; + } + p++; + index ++; + } + *(string + index) = 0; + return string; +} + + +/** + * @brief Parse numeric parameters + * + * @param string String parameter + * @return unsigned int Parsed number + */ +static unsigned int shellExtParseNumber(char *string) +{ + NUM_Type type = NUM_TYPE_INT; + char radix = 10; + char *p = string; + char offset = 0; + signed char sign = 1; + unsigned int valueInt = 0; + float valueFloat = 0.0; + unsigned int devide = 0; + + if (*string == '-') + { + sign = -1; + } + + type = shellExtNumType(string + ((sign == -1) ? 1 : 0)); + + switch ((char)type) + { + case NUM_TYPE_HEX: + radix = 16; + offset = 2; + break; + + case NUM_TYPE_OCT: + radix = 8; + offset = 1; + break; + + case NUM_TYPE_BIN: + radix = 2; + offset = 2; + break; + + default: + break; + } + + p = string + offset + ((sign == -1) ? 1 : 0); + + while (*p) + { + if (*p == '.') + { + devide = 1; + p++; + continue; + } + valueInt = valueInt * radix + shellExtToNum(*p); + devide *= 10; + p++; + } + if (type == NUM_TYPE_FLOAT && devide != 0) + { + valueFloat = (float)valueInt / devide * sign; + return *(unsigned int *)(&valueFloat); + } + else + { + return valueInt * sign; + } +} + + +/** + * @brief Analyze variable parameters + + * + * @param shell shell object + * @param var variable + * @return unsigned int variable value + */ +static unsigned int shellExtParseVar(Shell *shell, char *var) +{ + ShellCommand *command = shellSeekCommand(shell, + var + 1, + shell->commandList.base, + 0); + if (command) + { + return shellGetVarValue(shell, command); + } + else + { + return 0; + } +} + + +/** + * @brief Parsing parameters + * + * @param shell shell + * @param string parameter + * @return unsigned int Analysis result + */ +unsigned int shellExtParsePara(Shell *shell, char *string) +{ + if (*string == '\'' && *(string + 1)) + { + return (unsigned int)shellExtParseChar(string); + } + else if (*string == '-' || (*string >= '0' && *string <= '9')) + { + return (unsigned int)shellExtParseNumber(string); + } + else if (*string == '$' && *(string + 1)) + { + return shellExtParseVar(shell, string); + } + else if (*string) + { + return (unsigned long)shellExtParseString(string); + } + return 0; +} + + +/** + * @brief Excuting function + * + * @param shell shell + * @param command command + * @param argc Number of parameters + * @param argv parameter + * @return int return value + */ +int shellExtRun(Shell *shell, ShellCommand *command, int argc, char *argv[]) +{ + unsigned int params[8] = {0}; + int paramNum = command->attr.attrs.paramNum > (argc - 1) ? + command->attr.attrs.paramNum : (argc - 1); + for (int i = 0; i < argc - 1; i++) + { + params[i] = shellExtParsePara(shell, argv[i + 1]); + } + switch (paramNum) + { + case 0: + return command->data.cmd.function(); + // break; + case 1: + return command->data.cmd.function(params[0]); + // break; + case 2: + return command->data.cmd.function(params[0], params[1]); + // break; + case 3: + return command->data.cmd.function(params[0], params[1], + params[2]); + // break; + case 4: + return command->data.cmd.function(params[0], params[1], + params[2], params[3]); + // break; + case 5: + return command->data.cmd.function(params[0], params[1], + params[2], params[3], + params[4]); + // break; + case 6: + return command->data.cmd.function(params[0], params[1], + params[2], params[3], + params[4], params[5]); + // break; + case 7: + return command->data.cmd.function(params[0], params[1], + params[2], params[3], + params[4], params[5], + params[6]); + // break; + default: + return -1; + // break; + } +} + diff --git a/Ubiquitous/XiZi/tool/shell/letter-shell/shell_ext.h b/Ubiquitous/XiZi/tool/shell/letter-shell/shell_ext.h new file mode 100644 index 0000000..0a8a116 --- /dev/null +++ b/Ubiquitous/XiZi/tool/shell/letter-shell/shell_ext.h @@ -0,0 +1,33 @@ +/** + * @file shell_ext.h + * @author Letter (NevermindZZT@gmail.com) + * @brief shell extensions + * @version 3.0.0 + * @date 2019-12-31 + * + * @copyright (c) 2019 Letter + * + */ + +#ifndef __SHELL_EXT_H__ +#define __SHELL_EXT_H__ + +#include "shell.h" + +/** + * @brief type of number + * + */ +typedef enum +{ + NUM_TYPE_INT, /**< Decimal integer */ + NUM_TYPE_BIN, /**< Binary integer */ + NUM_TYPE_OCT, /**< Octal integer */ + NUM_TYPE_HEX, /**< Hexadecimal integer */ + NUM_TYPE_FLOAT /**< Floating point */ +} NUM_Type; + +unsigned int shellExtParsePara(Shell *shell, char *string); +int shellExtRun(Shell *shell, ShellCommand *command, int argc, char *argv[]); + +#endif diff --git a/Ubiquitous/XiZi/tool/shell/letter-shell/shell_port.c b/Ubiquitous/XiZi/tool/shell/letter-shell/shell_port.c new file mode 100644 index 0000000..661cfb6 --- /dev/null +++ b/Ubiquitous/XiZi/tool/shell/letter-shell/shell_port.c @@ -0,0 +1,130 @@ +/** + * @file shell_port.c + * @author Letter (NevermindZZT@gmail.com) + * @brief + * @version 0.1 + * @date 2019-02-22 + * + * @copyright (c) 2019 Letter + * + */ + +#include "xizi.h" +#include "shell.h" +#include "shell_fs.h" +#include +#ifdef FS_VFS +#include +#endif +#include +#include +#include "xsconfig.h" +#include + +Shell shell; +char *shellBuffer; +ShellFs shellFs; +char *shellPathBuffer; + +HardwareDevType console; + +/** + * @brief Shell write + * + * @param data write data + */ +void userShellWrite(char data) +{ + KPrintf("%c",data); +} + +/** + * @brief shell read + * + * @param data read data + * @return char read status + */ +signed char userShellRead(char *data) +{ + char read_length = 0; + struct BusBlockReadParam read_param; + read_param.read_length = 0; + read_param.size = 1; + read_param.buffer = data; + + BusDevReadData(console, &read_param); + + read_length = (char)read_param.read_length; + + return read_length; +} + +#ifdef SHELL_ENABLE_FILESYSTEM +/** + * @brief list file + * + * @param path path + * @param buffer result buffer + * @param maxLen the maximum buffer size + * @return size_t 0 + */ +size_t userShellListDir(char *path, char *buffer, size_t maxLen) +{ + DIR *dir; + struct dirent *ptr; + int i; + dir = opendir(path); + memset(buffer, 0, maxLen); + while((ptr = readdir(dir)) != NULL) + { + strcat(buffer, ptr->d_name); + strcat(buffer, "\t"); + } + closedir(dir); + return 0; +} +#endif + +/** + * @brief Initialize the shell + * + */ +int userShellInit(void) +{ + shellBuffer = x_malloc(512*sizeof(char)); + + +#ifdef SHELL_ENABLE_FILESYSTEM + shellPathBuffer = x_malloc(512*sizeof(char)); + shellPathBuffer[0] = '/'; + shellFs.getcwd = getcwd; + shellFs.chdir = chdir; + shellFs.listdir = userShellListDir; + shellFsInit(&shellFs, shellPathBuffer, 512); + shellSetPath(&shell, shellPathBuffer); +#endif + + shell.write = userShellWrite; + shell.read = userShellRead; + + console = ObtainConsole(); + + /*Open the serial device in interrupt receiving and polling sending mode */ + struct SerialDevParam *serial_dev_param = (struct SerialDevParam *)console->private_data; + serial_dev_param->serial_set_mode = 0; + serial_dev_param->serial_stream_mode = SIGN_OPER_STREAM; + BusDevOpen(console); + + shellInit(&shell, shellBuffer, 512); + int32 tid; + tid = KTaskCreate("letter-shell", + shellTask, &shell, + SHELL_TASK_STACK_SIZE, SHELL_TASK_PRIORITY); + + StartupKTask(tid); + return 0; +} + + + + diff --git a/Ubiquitous/XiZi/tool/shell/letter-shell/shell_port.h b/Ubiquitous/XiZi/tool/shell/letter-shell/shell_port.h new file mode 100644 index 0000000..7317523 --- /dev/null +++ b/Ubiquitous/XiZi/tool/shell/letter-shell/shell_port.h @@ -0,0 +1,21 @@ +/** + * @file shell_port.h + * @author Letter (NevermindZZT@gmail.com) + * @brief + * @version 0.1 + * @date 2019-02-22 + * + * @copyright (c) 2019 Letter + * + */ + +#ifndef __SHELL_PORT_H__ +#define __SHELL_PORT_H__ + +#include "serial.h" +#include "shell.h" + +extern Shell shell; + +int userShellInit(void); +#endif diff --git a/Ubiquitous/feature_yaml/Nuttx.yaml b/Ubiquitous/feature_yaml/Nuttx.yaml new file mode 100755 index 0000000..01879de --- /dev/null +++ b/Ubiquitous/feature_yaml/Nuttx.yaml @@ -0,0 +1,21 @@ +version: 0.1.0 +# Automatically generated file; DO NOT EDIT. +# Ubiquitous Kernel Selector + +Feature: + +# CONFIG_FS is not set + BUS: true + +BUS: + + USB: true +# CONFIG_SERIAL is not set + +Parameter: + + RAM_LESS_THAN: 20 + RAM_GREATER_THAN: 10000 + ROM_LESS_THAN: 10 + ROM_GREATER_THAN: 10000 + diff --git a/Ubiquitous/feature_yaml/RT_Thread.yaml b/Ubiquitous/feature_yaml/RT_Thread.yaml new file mode 100755 index 0000000..a1d1ce7 --- /dev/null +++ b/Ubiquitous/feature_yaml/RT_Thread.yaml @@ -0,0 +1,21 @@ +version: 0.1.0 +# Automatically generated file; DO NOT EDIT. +# Ubiquitous Kernel Selector + +Feature: + +# CONFIG_FS is not set + BUS: true + +BUS: + + USB: true +# CONFIG_SERIAL is not set + +Parameter: + + RAM_LESS_THAN: 5 + RAM_GREATER_THAN: 10000 + ROM_LESS_THAN: 5 + ROM_GREATER_THAN: 10000 + diff --git a/Ubiquitous/feature_yaml/XiZi.yaml b/Ubiquitous/feature_yaml/XiZi.yaml new file mode 100755 index 0000000..2e9c4b8 --- /dev/null +++ b/Ubiquitous/feature_yaml/XiZi.yaml @@ -0,0 +1,21 @@ +version: 0.1.0 +# Automatically generated file; DO NOT EDIT. +# Ubiquitous Kernel Selector + +Feature: + +# CONFIG_FS is not set + BUS: true + +BUS: + + USB: true +# CONFIG_SERIAL is not set + +Parameter: + + RAM_LESS_THAN: 3 + RAM_GREATER_THAN: 10000 + ROM_LESS_THAN: 10 + ROM_GREATER_THAN: 10000 + diff --git a/xiuos.tar b/xiuos.tar deleted file mode 100644 index 691e7f0..0000000 Binary files a/xiuos.tar and /dev/null differ