forked from XS-MLVP/UnityChipForXiangShan
49 lines
1.2 KiB
YAML
49 lines
1.2 KiB
YAML
PreDecode:
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- "wire currentIsRVC_0"
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- "wire currentIsRVC_1"
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- "wire currentIsRVC_2"
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- "wire currentIsRVC_3"
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- "wire currentIsRVC_4"
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- "wire currentIsRVC_5"
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- "wire currentIsRVC_6"
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- "wire currentIsRVC_7"
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- "wire currentIsRVC_8"
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- "wire currentIsRVC_9"
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- "wire currentIsRVC_10"
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- "wire currentIsRVC_11"
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- "wire currentIsRVC_12"
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- "wire currentIsRVC_13"
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- "wire currentIsRVC_14"
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- "wire currentIsRVC_15"
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- "wire validEnd_1"
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- "wire validEnd_2"
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- "wire h_validEnd_2"
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- "wire validEnd_3"
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- "wire h_validEnd_3"
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- "wire validEnd_4"
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- "wire h_validEnd_4"
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- "wire validEnd_5"
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- "wire h_validEnd_5"
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- "wire validEnd_6"
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- "wire h_validEnd_6"
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- "wire validEnd_7"
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- "wire h_validEnd_7"
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- "wire lastIsValidEnd_23"
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- "wire h_lastIsValidEnd_23"
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- "wire lastIsValidEnd_24"
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- "wire h_lastIsValidEnd_24"
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- "wire lastIsValidEnd_25"
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- "wire h_lastIsValidEnd_25"
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- "wire lastIsValidEnd_26"
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- "wire h_lastIsValidEnd_26"
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- "wire lastIsValidEnd_27"
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- "wire h_lastIsValidEnd_27"
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- "wire lastIsValidEnd_30"
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- "wire h_lastIsValidEnd_30"
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- "wire lastIsValidEnd_31"
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- "wire h_lastIsValidEnd_31"
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- "wire lastIsValidEnd_32"
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- "wire h_lastIsValidEnd_32"
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- "wire lastIsValidEnd_33"
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- "wire h_lastIsValidEnd_33"
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