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526 Commits

Author SHA1 Message Date
Rbb666 46fdeefb32 refactor(pic): dispatch NVIC IRQs through traps 2026-08-12 12:54:50 +08:00
Rbb666 1f23e3f270 fix(dm): route Cortex-M resets through power core 2026-08-12 12:54:50 +08:00
Rbb666 6b4f34204e feat(dm): support OFW on Cortex-M targets 
Add the ARM NVIC PIC driver, no-MMU I/O mapping, built-in FDT support, and Cortex-M CPU hooks required by the native RT-Thread device model.
 2026-08-12 12:54:50 +08:00
蒙蒙plus b1d51b4964 fix IAR build error 2026-06-02 18:05:02 +08:00
Evlers ad205d2bf3 [libcpu][arm][cortex-m33] allows rewrite to interrupt enable/disable api to support independent interrupts management 2026-05-19 16:34:34 +08:00
wdfk-prog e74547bbb3 feat(core): Add Cortex-M4 interrupt context helpers 2026-04-08 18:58:33 +08:00
AFWEF_147 2960935d2e fix(libcpu): correct arm mpu region validation precedence 2026-04-07 10:13:33 +08:00
AFWEF_147 21d223f089 fix(libcpu): validate arm irq vectors before masking 2026-04-07 10:07:41 +08:00
laidene 11a1348ed6 [docs][libcpu][arm][cortex-a] correct TLBIALL comments in start_gcc.S 2026-04-03 20:13:35 +08:00
wdfk-prog 05445c04e8 feat(core): Add 8-bit and 16-bit atomic operation support 2026-03-16 10:27:53 +08:00
wdfk-prog b7686b8d79 [libcpu][cortex-m7]Canonical alignment 2026-03-15 13:02:57 +08:00
theqengineer 85b656b14d chore: fix typo in components and libcpu 2026-02-13 21:54:59 +08:00
laidene 68a5c6a83b [libcpu][arm][cortex-a] Fixup mmu setup early 
Correct the starting virtual address of _reset alignment to 16MB
 2026-01-10 13:30:09 +08:00
laidene 9c60c5fb06 Update libcpu/arm/cortex-a/gic.c 2026-01-09 10:19:52 +08:00
laidene ff5c5eab6b [docs][libcpu][arm][cortex-a] add comment for gic.c 2026-01-09 10:19:52 +08:00
caicunjun a73f5d1032
[docs][libcpu][arm][cortex-a] add comment for mmu.h (#11104) 
* [docs][libcpu][arm][cortex-a] add comment for mmu.h

* [docs][libcpu][arm][cortex-a] beautify comment for mmu.h

* [docs][libcpu][arm][cortex-a] delete extra space at the end of lines
 2026-01-04 17:03:20 +08:00
caicunjun 71d802c415
[docs][libcpu][arm][cortex-a] update comment for start_gcc.S #11089 2025-12-26 21:04:23 +08:00
Copilot 30e1e5e9dc
Reorganize Group names in build system for clarity and IDE integration #10923 2025-11-16 11:40:53 +08:00
Copilot e525c38cb8
[libcpu][cortex-a] Refactor FPU stack initialization for maintainability (#10919) 
* Initial plan

* [libcpu][cortex-a] Improve FPU stack initialization implementation

Co-authored-by: BernardXiong <1241087+BernardXiong@users.noreply.github.com>

* [libcpu][cortex-a] Replace FPU init loop with rt_memset

Co-authored-by: BernardXiong <1241087+BernardXiong@users.noreply.github.com>

---------

Co-authored-by: copilot-swe-agent[bot] <198982749+Copilot@users.noreply.github.com>
Co-authored-by: BernardXiong <1241087+BernardXiong@users.noreply.github.com>
 2025-11-12 04:34:34 +08:00
Copilot c631b39317
[Components] Remove vbus component and realview-a8-vmm libcpu (#10863) 
* Initial plan

* Remove vbus component and related code

Co-authored-by: BernardXiong <1241087+BernardXiong@users.noreply.github.com>

---------

Co-authored-by: copilot-swe-agent[bot] <198982749+Copilot@users.noreply.github.com>
Co-authored-by: BernardXiong <1241087+BernardXiong@users.noreply.github.com>
 2025-11-07 17:03:05 +08:00
Yucai Liu c91a7f46f5 [libcpu/arm/cortex-m33]: Fix incorrect CPU architecture in GCC context switch 
The context_gcc.S file was incorrectly marked as cortex-m4 in both the
doxygen comment and .cpu directive, while the IAR and KEIL versions
correctly specify cortex-m33. This file uses ARMv8-M specific features
(PSPLIM register, TrustZone support) that are not available in Cortex-M4.

Changes:
- Update doxygen group from cortex-m4 to cortex-m33
- Change .cpu directive from cortex-m4 to cortex-m33
 2025-11-02 16:23:31 +08:00
Yonggang Luo 5ae232b6d0
bsp/w60x: fixes cppcheck: (#10781) 
[cpp_check.py 80 INFO] bsp/w60x/drivers/drv_rtc.c:58:11: error: Syntax Error: AST broken, binary operator '&=' doesn't have two operands. [internalAstError]

[cpp_check.py 80 INFO] libcpu/arm/s3c24x0/rtc.c:34:12: error: Expression 'RTCCON|=RTCCON|=0x01' depends on order of evaluation of side effects [unknownEvaluationOrder]
 2025-10-11 09:28:52 +08:00
Yonggang Luo 62bc4ba774 Remove rarely used rt_time_t 
next_delay should be rt_tick_t

Use time_t for RT_DEVICE_CTRL_RTC_GET_TIME
 2025-10-10 20:21:40 +08:00
R b b666 2b65a6f2a7
fix:Fixed compilation error for libcpu/cortex-m4. (#10756) 2025-09-28 16:08:02 +08:00
Rbb666 882d1958dd [libcpu][cortex-m33]Added HardFault_Handler to save floating point registers 2025-08-20 18:17:19 +08:00
Rbb666 990fc23628 [libcpu][cortex-m4]Added HardFault_Handler to save floating point registers. 2025-08-19 21:40:57 +08:00
R b b666 2f19ba6ce7
[libcpu ][cm3]The parameter passed to the unified rt_exception_hook is exception_stack. (#10619) 2025-08-19 21:15:47 +08:00
kurisaw 4f903298a2 libcpu/bsp: fix the M33 assembly syntax errors and fix the compilation error of bsp 2025-06-24 11:04:01 +08:00
Chen Wang 5c9f61879c
libcpu: cleanup undefined rt_hw_mmu_kernel_map_init (#10177) 
* libcpu: cleanup undefined rt_hw_mmu_kernel_map_init

rt_hw_mmu_kernel_map_init() is declared in header files but
no definition found, cleanup the code.

Signed-off-by: Chen Wang <unicorn_wang@outlook.com>

* bsp: allwinner: d1: remove calling of rt_hw_mmu_kernel_map_init

rt_hw_mmu_kernel_map_init is an undefined function, calling it
is meaningless.

Signed-off-by: Chen Wang <unicorn_wang@outlook.com>

---------

Signed-off-by: Chen Wang <unicorn_wang@outlook.com>
 2025-04-11 07:54:21 +08:00
CYFS b0e7cba9fd
[bsp][stm32][artpi]:fix artpi nano (#10122) 2025-03-18 22:55:13 +08:00
Rbb666 cb098c4eea [fix]Fix cm33 compilation problem when block is turned on 2025-03-17 19:13:34 +08:00
Meco Man 97b9cc5000 fix: add \n for addr2line hint 2025-01-08 17:54:46 -05:00
kurisaw 2c3ee65d7f rzn2l-rsk support studio 2024-12-04 10:11:04 +08:00
kurisaw 3f1a62cfe3 [libcpu][drivers] cortex-r52 abnormal takeover and software rtc naming change 2024-12-04 10:11:04 +08:00
GuEe-GUI 5dda65c21b [DM/FIXUP] add cortex-m23's cpuport.h 
Signed-off-by: GuEe-GUI <2991707448@qq.com>
 2024-11-20 16:11:10 +08:00
kurisaw 2241f4676b [libcpu][component] fixed the r52 kernel gcc context switch assembly 2024-11-06 16:09:52 +08:00
Yuqiang Wang b3d59050b0
[kernel] Specification interrupt nested level variable declaration type (#9568) 2024-10-23 17:08:29 -04:00
Evlers 8249e71bcc add readme files 2024-08-29 11:58:52 +08:00
Evlers 8c0f689452 [libcpu][arm][cortex-m4] allows rewrite to interrupt enable/disable api to support independent interrupts management 2024-08-29 11:58:52 +08:00
childerxxx d7914defdd Correct ".cpu cortex-m4" to ".cpu cortex-m7" 2024-07-11 20:42:50 +08:00
Shell 397cdcd132
[libcpu] discard rt_current_thread (#8976) 
* [libcpu] rv64: discard rt_current_thread

* arm: using rt_thread_self to fetch current TCB
 2024-05-26 22:00:17 +08:00
wirano 202bacb44d [cpu_cache] fix function replaced by macro 2024-04-18 20:40:55 -04:00
Meco Man a841091827 [libcpu] remove .asm files in cortex-r52 2024-04-18 20:32:47 -04:00
Rbb666 9a3172540f Delete unnecessary configurations in cortex-r52 2024-04-18 20:32:47 -04:00
Rbb666 1497a3117a
[bsp][renesas]Add cortex-r52 rzt2m adaptation 2024-04-10 20:47:53 -04:00
liYangYang 9a1996ef59
[bsp][art-pi-smart] 关闭内存对齐检查来避免数据访问异常 2024-03-29 21:43:57 -04:00
Shell 83e95bdff4
sync smart & dfs (#8672) 
Signed-off-by: xqyjlj <xqyjlj@126.com>
Signed-off-by: Shell <smokewood@qq.com>
Co-authored-by: xqyjlj <xqyjlj@126.com>
 2024-03-28 23:42:56 +08:00
zhangyan fad78950ea
[bsp/phytium]Adapter aarch64/aarch32 (#8580) 2024-03-13 18:07:03 +08:00
zhangyan 76202e2141
🎯 [libcpu/arm/cortex-a]修改arm/cortex-a启动方式，解决cortex-a开启SMP工作异常问题 (#8517) 
Co-authored-by: wangzongqiang <wangzongqiang1322@phytium.com.cn>
 2024-03-02 16:06:07 +08:00
Shell 71560bafb5
🎯 Sync smart & scheduler codes (#8537) 
Signed-off-by: Shell <smokewood@qq.com>
Co-authored-by: xqyjlj <xqyjlj@126.com>
 2024-02-23 17:49:15 +08:00