* [dm][clk] fixup the work flow of CLK
Add RT_CLK_F_SET_RATE_NO_REPARENT so clock providers can preserv
the currently selected parent during rate changes.
Round and re-read the effective clock rate after parent handling,
skip redundant gate toggles and hardware programming when
the target is already active, and fix error handling for parent-clock allocation failures.
Signed-off-by: GuEe-GUI <2991707448@qq.com>
* style: format code with clang-format
* style: format complete changed files with clang-format
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Signed-off-by: GuEe-GUI <2991707448@qq.com>
* [dm][phye] Add Mode/State and MIPI D-PHY timing helper
Extend the generic PHY framework with cached mode and submode state,
avoiding redundant hardware mode changes.
Add MIPI D-PHY default timing calculation helpers based on
pixel clock or lane high-speed clock, and expose the new API through rtdevice.h.
Signed-off-by: GuEe-GUI <2991707448@qq.com>
* style: format code with clang-format
* style: format complete changed files with clang-format
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Signed-off-by: GuEe-GUI <2991707448@qq.com>
Add rt_bus_probe_device() to retry driver matching for a registered
but unbound device. Use it when an OFW-created platform device
is requested again, while preserving native-bus ownership
for I2C, SPI, and other non-platform devices.
Also instantiate eligible child platform devices after a parent node is registered.
Signed-off-by: GuEe-GUI <2991707448@qq.com>
add serial v2 RX DMA event mode configuration for DMA-enabled builds
support STM32 UART RX DMA half/full transfer interrupt policy selection
validate RX DMA event mode before applying serial configuration
restore serial configuration when backend configure fails
1. Support DVFS and finsh cmd, there are 6 governors:
- conservative
- freedom
- performance
- powersave
- schedutil
2. Support DVFS for SCMI.
3. Port the Cooling device for DVFS.
4. Port the PM with DVFS.
Signed-off-by: GuEe-GUI <2991707448@qq.com>
1. version for v1.2
2. support packed queue
1. support MMIO/PCI over bus
2. new virtio queue api with dma/cpu sync
3. update for virtio device drivers:
- net
- block
- console
- input
- gpu
4. new virtio device drivers:
- 9p
- crypto
- rng
- scmi
- scsi
Signed-off-by: GuEe-GUI <2991707448@qq.com>
- add msh commands to inspect/operate power supplies and regulators
- expose snapshot/name helpers so shells and daemons can enumerate nodes safely
- add current support for regulator
- relax DM-only constraints in power/regulator stacks so basic builds work without DM/OFW
- solve the problem of enabling counting for regulator
* [components][clock_time] Refactor time subsystem around clock_time
Introduce the clock_time core with clock source/event separation, high-resolution scheduling, and boot-time helpers, plus clock_timer adapters for timer peripherals.
Remove legacy ktime/cputime/hwtimer implementations and migrate arch and BSP time paths to the new subsystem while keeping POSIX time integration functional.
Update drivers, Kconfig/SConscript wiring, documentation, and tests; add clock_time overview docs and align naming to clock_boottime/clock_hrtimer/clock_timer.
* [components][clock_time] Use BSP-provided clock timer frequency on riscv64
* [risc-v] Use runtime clock timer frequency for tick and delays
* [bsp] Add clock timer frequency hooks for riscv64 boards
* [bsp] Update Renesas RA driver doc clock_timer link
* [bsp] Sync zynqmp-r5-axu4ev rtconfig after config refresh
* [bsp][rk3500] Update rk3500 clock configuration
* [bsp][hpmicro] Add rt_hw_us_delay hook and update board delays
* [bsp][stm32l496-st-nucleo] enable clock_time for hwtimer sample in ci
* [bsp][hpmicro] Fix rtconfig include scope for hpm6750evk
Move rtconfig.h include outside the ENET_MULTIPLE_PORT guard for hpm6750evk and hpm6750evk2 so configuration macros are available regardless of ENET settings.
* [bsp][raspi3] select clock time for systimer
* [bsp][hpm5300evk] Trim trailing blank line
* [bsp][hpm5301evklite] Trim trailing blank line
* [bsp][hpm5e00evk] Trim trailing blank line
* [bsp][hpm6200evk] Trim trailing blank line
* [bsp][hpm6300evk] Trim trailing blank line
* [bsp][hpm6750evk] Trim trailing blank line
* [bsp][hpm6750evk2] Trim trailing blank line
* [bsp][hpm6750evkmini] Trim trailing blank line
* [bsp][hpm6800evk] Trim trailing blank line
* [bsp][hpm6e00evk] Trim trailing blank line
* [bsp][nxp] switch lpc178x to gcc and remove mcx timer source
* [bsp][stm32] fix the CONFIG_RT_USING_CLOCK_TIME issue.
* [docs][clock_time] add clock time documentation
* [docs][clock_time] Update clock time subsystem documentation
- Update device driver index to use correct page reference
- Clarify upper layer responsibilities in architecture overview
- Update README to describe POSIX/libc, Soft RTC, and device driver usage
- Refine architecture diagram with improved layout and color scheme
- Remove obsolete clock_timer.md file
* [kernel][utest] Trim trailing space
* [clock_time] Fix hrtimer wrap handling
* [clock_time] fix the static rt_inline issue
* [clock_time] fix the rt_clock_hrtimer_control result issue
The old CLK is can't link all hardware clock cell in system that the
API of layout such as 'set_parent' can't work as expected.
Some hareware clock cell need some flags to prevent some dangerous behaviors, eg:
When a clock cell is link to the PMU, the SoC will power-down if the cell is
disable.
The new CLK can do it, and make the CLK drivers implemented easier from
TRM/DataSheet.
Signed-off-by: GuEe-GUI <2991707448@qq.com>
Hardware spinlock modules provide hardware assistance for
synchronization and mutual exclusion between heterogeneous processors
and those not operating under a single, shared operating system.
Signed-off-by: GuEe-GUI <2991707448@qq.com>
* [DM][MISC] Make Kconfig(ADC/PWM) import for DM
* [Driver][MISC][ADC] Fixup ADC
1. Fixup error no.
2. Fixup type of control for args.
3. Fixup value no init.
* [Driver][MISC][PWM] Enable `rt_pwm_get` API
Signed-off-by: GuEe-GUI <2991707448@qq.com>
1. Add get id match data API.
2. Set I2C device name default before adding to bus.
3. Add Kconfig import for DM.
Signed-off-by: GuEe-GUI <2991707448@qq.com>
1. Fixup RT_DIV_ROUND_DOWN_ULL and RT_DIV_ROUND_UP_ULL, rt_do_div.
2. Support RT_DIV_ROUND_CLOSEST_ULL.
3. Make new DIV API.
Signed-off-by: GuEe-GUI <2991707448@qq.com>
* Append WT attribute.
* Change the API with pool size only.
* Add address mask for DMA
* Change DMA lock to mutex
* Add pause callback for DMA engine driver
* Add DMA Engine test
* Add ARM PL330 DMA Engine driver
Rbb666