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[bsp/n32]n32h760zil7-stb bsp修复完善，添加 n32h497zgl7-evb和n32h487zgl7-evb bsp (#11627) 

1、修改n32\n32gxx_lxx\n32g4frml-stb中的GCC启动文件bl entry
2、修复完善n32h760zil7-stb bsp，支持GCC环境、支持更多外设
3、添加n32h487zgl7-evb初版BSP
4、添加n32h497zgl7-evb初版BSP
5、删除n32g452xx这个bsp

---------

Co-authored-by: OnlyoutzZ <OnlyoutzZ+github[bot]@noreply.github.com>
This commit is contained in:
Onlyou_tzZ 2026-07-22 17:06:34 +08:00 committed by GitHub
parent 622c55248c
commit f08217a883
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GPG Key ID: B5690EEEBB952194
505 changed files with 45982 additions and 292468 deletions
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5
.github/ALL_BSP_COMPILE.json vendored
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@ -342,8 +342,9 @@
"n32/n32gxx_lxx/n32l43xrl-stb",
"n32/n32gxx_lxx/n32l436-evb",
"n32/n32gxx_lxx/n32wb45xl-evb",
"n32g452xx/n32g452xx-mini-system",
"n32/n32hxxx/n32h760zil7-stb",
"n32/n32hxxx/n32h760zil7-stb",
"n32/n32hxxx/n32h487zgl7-evb",
"n32/n32hxxx/n32h497zgl7-evb",
"apm32/apm32f103xe-minibroard",
"apm32/apm32f407ig-minibroard",
"apm32/apm32f407zg-evalboard",

36
bsp/README.md
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@ -317,21 +317,24 @@ This document is based on the RT-Thread mainline repository and categorizes the
#### 🟡 N32
| BSP Name | GPIO | UART | ADC | CAN | DAC | HWTimer | I2C | RTC | SPI | WDT |
| BSP Name | GPIO | UART | ADC | CAN | DAC | HWTimer | I2C | RTC | SPI | WDT | PWM |ENCODER | LPTIM | NAND | ETH | ON-Chip FLASH |
|----------|------|------|-----|-----|-----|---------|-----|-----|-----|-----|
| [n32g43xcl-stb](n32/n32gxx_lxx/n32g43xcl-stb) | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ |
| [n32g457gel-stb](n32/n32gxx_lxx/n32g457gel-stb) | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ |
| [n32g45xcl-stb](n32/n32gxx_lxx/n32g45xcl-stb) | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ |
| [n32g45xml-stb](n32/n32gxx_lxx/n32g45xml-stb) | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ |
| [n32g45xrl-stb](n32/n32gxx_lxx/n32g45xrl-stb) | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ |
| [n32g45xvl-stb](n32/n32gxx_lxx/n32g45xvl-stb) | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ |
| [n32g47rml-stb](n32/n32gxx_lxx/n32g47rml-stb) | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ |
| [n32l40xcl-stb](n32/n32gxx_lxx/n32l40xcl-stb) | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ |
| [n32l436-evb](n32/n32gxx_lxx/n32l436-evb) | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ |
| [n32l43xml-stb](n32/n32gxx_lxx/n32l43xml-stb) | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ |
| [n32l43xrl-stb](n32/n32gxx_lxx/n32l43xrl-stb) | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ |
| [n32wb45xl-evb](n32/n32gxx_lxx/n32wb45xl-evb) | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ |
| [n32h760zil7-stb](n32/n32hxxx/n32h760zil7-stb) | ✅ | ✅ | ✅ | - | - | - | ✅ | ✅ | ✅ | - |
| [n32g43xcl-stb](n32/n32gxx_lxx/n32g43xcl-stb) | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | - | - | - | - | - | - |
| [n32g457gel-stb](n32/n32gxx_lxx/n32g457gel-stb) | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | - | - | - | - | - | - |
| [n32g45xcl-stb](n32/n32gxx_lxx/n32g45xcl-stb) | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | - | - | - | - | - | - |
| [n32g45xml-stb](n32/n32gxx_lxx/n32g45xml-stb) | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | - | - | - | - | - | - |
| [n32g45xrl-stb](n32/n32gxx_lxx/n32g45xrl-stb) | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | - | - | - | - | - | - |
| [n32g45xvl-stb](n32/n32gxx_lxx/n32g45xvl-stb) | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | - | - | - | - | - | - |
| [n32g47rml-stb](n32/n32gxx_lxx/n32g47rml-stb) | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | - | - | - | - | - | - |
| [n32l40xcl-stb](n32/n32gxx_lxx/n32l40xcl-stb) | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | - | - | - | - | - | - |
| [n32l436-evb](n32/n32gxx_lxx/n32l436-evb) | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | - | - | - | - | - | - |
| [n32l43xml-stb](n32/n32gxx_lxx/n32l43xml-stb) | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | - | - | - | - | - | - |
| [n32l43xrl-stb](n32/n32gxx_lxx/n32l43xrl-stb) | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | - | - | - | - | - | - |
| [n32wb45xl-evb](n32/n32gxx_lxx/n32wb45xl-evb) | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | - | - | - | - | - | - |
| [n32h760zil7-stb](n32/n32hxxx/n32h760zil7-stb) | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ |
| [n32h497zgl7-evb](n32/n32hxxx/n32h497zgl7-evb) | ✅ | ✅ | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| [n32h487zgl7-evb](n32/n32hxxx/n32h487zgl7-evb) | ✅ | ✅ | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
#### 🟡 NRF5x
@ -420,11 +423,6 @@ This document is based on the RT-Thread mainline repository and categorizes the
| [swm320-mini](synwit/swm320-mini) | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ |
| [swm341-mini](synwit/swm341-mini) | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ |
#### ⚪ N32G452xx
| BSP Name | GPIO | UART | ADC | CAN | DAC | Flash | HWTimer | I2C | PWM | RTC | SDIO | SPI | WDT |
|----------|------|------|-----|-----|-----|-------|---------|-----|-----|-----|------|-----|-----|
| [n32g452xx-mini-system](n32g452xx/n32g452xx-mini-system) | ✅ | ✅ | ✅ | ✅ | - | ✅ | ✅ | ✅ | ✅ | - | ✅ | ✅ | ✅ |
#### ⚪ W60x
| BSP Name | GPIO | UART | ADC | Crypto | Flash | HWTimer | WDT | PWM | I2C | SPI |
|----------|------|------|-----|--------|-------|---------|-----|-----|-----|-----|

2
bsp/n32/n32gxx_lxx/libraries/N32G4FR_Firmware_Library/CMSIS/device/startup/startup_n32g4fr_gcc.s
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@ -72,7 +72,7 @@ LoopFillZerobss:
/* Call static constructors */
bl __libc_init_array
/* Call the application's entry point.*/
bl main
bl entry
bx lr
.size Reset_Handler, .-Reset_Handler

7
bsp/n32/n32hxxx/.clang-format-ignore
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@ -5,8 +5,5 @@
# 从 .ignore_format.yml 迁移的规则
/n32h760zil7-stb/board/Cube_Config/
/n32h760zil7-stb/board/Cube_Config/data/
/n32h760zil7-stb/board/Cube_Config/Driver/
/n32h760zil7-stb/board/Cube_Config/MDK-ARM/
/n32h760zil7-stb/board/Cube_Config/startup/
/n32h760zil7-stb/board/Cube_Config/USER/
/n32h487zgl7-evb/board/Cube_Config/
/n32h497zgl7-evb/board/Cube_Config/

10
bsp/n32/n32hxxx/libraries/Kconfig
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@ -6,4 +6,14 @@ config SOC_SERIES_N32H7xx
select ARCH_ARM_CORTEX_M7
select SOC_FAMILY_N32
config SOC_SERIES_N32H47x_48x
bool
select ARCH_ARM_CORTEX_M4
select SOC_FAMILY_N32
config SOC_SERIES_N32H49x
bool
select ARCH_ARM_CORTEX_M4
select SOC_FAMILY_N32

69
bsp/n32/n32hxxx/libraries/N32_Drivers/drivers/SConscript
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@ -12,24 +12,87 @@ if GetDepend(['RT_USING_PIN']):
src += ['drv_gpio.c']
if GetDepend(['RT_USING_SERIAL']):
src += ['drv_usart.c']
if GetDepend(['RT_USING_SERIAL_V2']):
src += ['drv_usart_v2.c']
else:
src += ['drv_usart.c']
if GetDepend(['BSP_USING_CLOCK_TIMER']):
src += ['drv_tim.c']
if GetDepend(['BSP_USING_PWM']):
src += ['drv_pwm.c', 'drv_tim.c']
if GetDepend(['RT_USING_SPI']):
src += ['drv_spi.c']
if GetDepend(['RT_USING_QSPI']):
src += ['drv_qspi.c']
if GetDepend(['RT_USING_I2C']):
if GetDepend('BSP_USING_HARD_I2C1') or GetDepend('BSP_USING_HARD_I2C2') or GetDepend('BSP_USING_HARD_I2C3') or GetDepend('BSP_USING_HARD_I2C4') or GetDepend('BSP_USING_HARD_I2C5') or GetDepend('BSP_USING_HARD_I2C6') or GetDepend('BSP_USING_HARD_I2C7') or GetDepend('BSP_USING_HARD_I2C8') or GetDepend('BSP_USING_HARD_I2C9') or GetDepend('BSP_USING_HARD_I2C10'):
src += ['drv_hard_i2c.c']
if GetDepend('BSP_USING_ONCHIP_RTC'):
src += ['drv_rtc.c']
if GetDepend(['BSP_USING_ETH', 'RT_USING_LWIP']):
src += ['drv_eth.c']
if GetDepend(['RT_USING_ADC']):
src += ['drv_adc.c']
if GetDepend(['RT_USING_DAC']):
src += ['drv_dac.c']
if GetDepend(['RT_USING_CAN']):
if GetDepend(['SOC_SERIES_N32H7xx']) or GetDepend(['SOC_SERIES_N32H47x_48x']) or GetDepend(['SOC_SERIES_N32H49x']):
src += ['drv_fdcan.c']
else:
src += ['drv_can.c']
if GetDepend(['RT_USING_PM']):
src += ['drv_pm.c']
if GetDepend(['BSP_USING_LPTIM']):
src += ['drv_lptim.c']
if GetDepend('BSP_USING_SDRAM'):
src += ['drv_sdram.c']
if GetDepend(['BSP_USING_NAND']):
src += ['drv_nand.c']
if GetDepend('BSP_USING_LCD'):
src += ['drv_lcd.c']
if GetDepend('BSP_USING_ONCHIP_RTC'):
src += ['drv_rtc.c']
if GetDepend(['BSP_USING_ON_CHIP_FLASH', 'SOC_SERIES_N32H49x']):
src += [os.path.join('drv_flash', 'drv_flash_h49x.c')]
if GetDepend(['BSP_USING_ON_CHIP_FLASH', 'SOC_SERIES_N32H47x_48x']):
src += [os.path.join('drv_flash', 'drv_flash_h47x_48x.c')]
if GetDepend(['BSP_USING_ON_CHIP_FLASH', 'SOC_SERIES_N32H7xx']):
src += [os.path.join('drv_flash', 'drv_flash_h7xx.c')]
if GetDepend(['BSP_USING_WDT']):
src += ['drv_wdt.c']
if GetDepend(['BSP_USING_SDIO']):
if GetDepend('SOC_SERIES_N32H7xx'):
src += ['drv_sdmmc.c']
else:
src += ['drv_sdio.c']
if GetDepend(['BSP_USING_PULSE_ENCODER']):
src += ['drv_pulse_encoder.c', 'drv_tim.c']
path += [os.path.join(cwd, 'config')]
if GetDepend('BSP_USING_ON_CHIP_FLASH'):
path += [os.path.join(cwd, 'drv_flash')]
group = DefineGroup('Drivers', src, depend = [''], CPPPATH = path)
Return('group')

201
bsp/n32/n32hxxx/libraries/N32_Drivers/drivers/config/h47x_48x/dma_config.h Normal file
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@ -0,0 +1,201 @@
/*
* Copyright (c) 2006-2025, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2026-04-07 ox-horse first version
*/
#ifndef __DMA_CONFIG_H__
#define __DMA_CONFIG_H__
#include <rtthread.h>
#ifdef __cplusplus
extern "C" {
#endif
/* DMA1 channel1 */
#if defined(BSP_UART1_RX_USING_DMA) && !defined(UART1_RX_DMA)
#define UART1_RX_DMA DMA1
#define UART1_RX_DMA_IRQHandler DMA1_Channel1_IRQHandler
#define UART1_RX_DMA_CHType DMA1_CH1
#define UART1_RX_DMA_IRQ DMA1_Channel1_IRQn
#define UART1_RX_DMA_RCC RCC_AHB_PERIPHEN_DMA1
#define UART1_RX_DMA_REQUEST DMA_REMAP_USART1_RX
#define UART1_RX_DMA_CHANNEL 1U
#endif
/* DMA1 channel2 */
#if defined(BSP_UART2_RX_USING_DMA) && !defined(UART2_RX_DMA)
#define UART2_RX_DMA DMA1
#define UART2_RX_DMA_IRQHandler DMA1_Channel2_IRQHandler
#define UART2_RX_DMA_CHType DMA1_CH2
#define UART2_RX_DMA_IRQ DMA1_Channel2_IRQn
#define UART2_RX_DMA_RCC RCC_AHB_PERIPHEN_DMA1
#define UART2_RX_DMA_REQUEST DMA_REMAP_USART2_RX
#define UART2_RX_DMA_CHANNEL 2U
#endif
/* DMA1 channel3 */
#if defined(BSP_UART3_RX_USING_DMA) && !defined(UART3_RX_DMA)
#define UART3_RX_DMA DMA1
#define UART3_RX_DMA_IRQHandler DMA1_Channel3_IRQHandler
#define UART3_RX_DMA_CHType DMA1_CH3
#define UART3_RX_DMA_IRQ DMA1_Channel3_IRQn
#define UART3_RX_DMA_RCC RCC_AHB_PERIPHEN_DMA1
#define UART3_RX_DMA_REQUEST DMA_REMAP_USART3_RX
#define UART3_RX_DMA_CHANNEL 3U
#endif
/* DMA1 channel4 */
#if defined(BSP_UART4_RX_USING_DMA) && !defined(UART4_RX_DMA)
#define UART4_RX_DMA DMA1
#define UART4_RX_DMA_IRQHandler DMA1_Channel4_IRQHandler
#define UART4_RX_DMA_CHType DMA1_CH4
#define UART4_RX_DMA_IRQ DMA1_Channel4_IRQn
#define UART4_RX_DMA_RCC RCC_AHB_PERIPHEN_DMA1
#define UART4_RX_DMA_REQUEST DMA_REMAP_USART4_RX
#define UART4_RX_DMA_CHANNEL 4U
#endif
/* DMA1 channel5 */
#if defined(BSP_UART5_RX_USING_DMA) && !defined(UART5_RX_DMA)
#define UART5_RX_DMA DMA1
#define UART5_RX_DMA_IRQHandler DMA1_Channel5_IRQHandler
#define UART5_RX_DMA_CHType DMA1_CH5
#define UART5_RX_DMA_IRQ DMA1_Channel5_IRQn
#define UART5_RX_DMA_RCC RCC_AHB_PERIPHEN_DMA1
#define UART5_RX_DMA_REQUEST DMA_REMAP_UART5_RX
#define UART5_RX_DMA_CHANNEL 5U
#endif
/* DMA1 channel6 */
#if defined(BSP_UART6_RX_USING_DMA) && !defined(UART6_RX_DMA)
#define UART6_RX_DMA DMA1
#define UART6_RX_DMA_IRQHandler DMA1_Channel6_IRQHandler
#define UART6_RX_DMA_CHType DMA1_CH6
#define UART6_RX_DMA_IRQ DMA1_Channel6_IRQn
#define UART6_RX_DMA_RCC RCC_AHB_PERIPHEN_DMA1
#define UART6_RX_DMA_REQUEST DMA_REMAP_UART6_RX
#define UART6_RX_DMA_CHANNEL 6U
#endif
/* DMA1 channel7 */
#if defined(BSP_UART7_RX_USING_DMA) && !defined(UART7_RX_DMA)
#define UART7_RX_DMA DMA1
#define UART7_RX_DMA_IRQHandler DMA1_Channel7_IRQHandler
#define UART7_RX_DMA_CHType DMA1_CH7
#define UART7_RX_DMA_IRQ DMA1_Channel7_IRQn
#define UART7_RX_DMA_RCC RCC_AHB_PERIPHEN_DMA1
#define UART7_RX_DMA_REQUEST DMA_REMAP_UART7_RX
#define UART7_RX_DMA_CHANNEL 7U
#endif
/* DMA1 channel8 */
#if defined(BSP_UART8_RX_USING_DMA) && !defined(UART8_RX_DMA)
#define UART8_RX_DMA DMA1
#define UART8_RX_DMA_IRQHandler DMA1_Channel8_IRQHandler
#define UART8_RX_DMA_CHType DMA1_CH8
#define UART8_RX_DMA_IRQ DMA1_Channel8_IRQn
#define UART8_RX_DMA_RCC RCC_AHB_PERIPHEN_DMA1
#define UART8_RX_DMA_REQUEST DMA_REMAP_UART8_RX
#define UART8_RX_DMA_CHANNEL 8U
#endif
/* DMA2 channel1 */
#if defined(BSP_UART1_TX_USING_DMA) && !defined(UART1_TX_DMA)
#define UART1_TX_DMA DMA2
#define UART1_TX_DMA_IRQHandler DMA2_Channel1_IRQHandler
#define UART1_TX_DMA_CHType DMA2_CH1
#define UART1_TX_DMA_IRQ DMA2_Channel1_IRQn
#define UART1_TX_DMA_RCC RCC_AHB_PERIPHEN_DMA2
#define UART1_TX_DMA_REQUEST DMA_REMAP_USART1_TX
#define UART1_TX_DMA_CHANNEL 1U
#endif
/* DMA2 channel2 */
#if defined(BSP_UART2_TX_USING_DMA) && !defined(UART2_TX_DMA)
#define UART2_TX_DMA DMA2
#define UART2_TX_DMA_IRQHandler DMA2_Channel2_IRQHandler
#define UART2_TX_DMA_CHType DMA2_CH2
#define UART2_TX_DMA_IRQ DMA2_Channel2_IRQn
#define UART2_TX_DMA_RCC RCC_AHB_PERIPHEN_DMA2
#define UART2_TX_DMA_REQUEST DMA_REMAP_USART2_TX
#define UART2_TX_DMA_CHANNEL 2U
#endif
/* DMA2 channel3 */
#if defined(BSP_UART3_TX_USING_DMA) && !defined(UART3_TX_DMA)
#define UART3_TX_DMA DMA2
#define I2C10_RX_DMA_IRQHandler DMA2_Channel3_IRQHandler
#define UART3_TX_DMA_CHType DMA2_CH3
#define UART3_TX_DMA_IRQ DMA2_Channel3_IRQn
#define UART3_TX_DMA_RCC RCC_AHB_PERIPHEN_DMA2
#define UART3_TX_DMA_REQUEST DMA_REMAP_USART3_TX
#define UART3_TX_DMA_CHANNEL 3U
#endif
/* DMA2 channel4 */
#if defined(BSP_UART4_TX_USING_DMA) && !defined(UART4_TX_DMA)
#define UART4_TX_DMA DMA2
#define UART4_TX_DMA_IRQHandler DMA2_Channel4_IRQHandler
#define UART4_TX_DMA_CHType DMA2_CH4
#define UART4_TX_DMA_IRQ DMA2_Channel4_IRQn
#define UART4_TX_DMA_RCC RCC_AHB_PERIPHEN_DMA2
#define UART4_TX_DMA_REQUEST DMA_REMAP_USART4_TX
#define UART4_TX_DMA_CHANNEL 4U
#endif
/* DMA2 channel5 */
#if defined(BSP_UART5_TX_USING_DMA) && !defined(UART5_TX_DMA)
#define UART5_TX_DMA DMA2
#define UART5_TX_DMA_IRQHandler DMA2_Channel5_IRQHandler
#define UART5_TX_DMA_CHType DMA2_CH5
#define UART5_TX_DMA_IRQ DMA2_Channel5_IRQn
#define UART5_TX_DMA_RCC RCC_AHB_PERIPHEN_DMA2
#define UART5_TX_DMA_REQUEST DMA_REMAP_UART5_TX
#define UART5_TX_DMA_CHANNEL 5U
#endif
/* DMA2 channel6 */
#if defined(BSP_UART6_TX_USING_DMA) && !defined(UART6_TX_DMA)
#define UART6_TX_DMA DMA2
#define UART6_TX_DMA_IRQHandler DMA2_Channel6_IRQHandler
#define UART6_TX_DMA_CHType DMA2_CH6
#define UART6_TX_DMA_IRQ DMA2_Channel6_IRQn
#define UART6_TX_DMA_RCC RCC_AHB_PERIPHEN_DMA2
#define UART6_TX_DMA_REQUEST DMA_REMAP_UART6_TX
#define UART6_TX_DMA_CHANNEL 6U
#endif
/* DMA2 channel7 */
#if defined(BSP_UART7_TX_USING_DMA) && !defined(UART7_TX_DMA)
#define UART7_TX_DMA DMA2
#define UART7_TX_DMA_IRQHandler DMA2_Channel7_IRQHandler
#define UART7_TX_DMA_CHType DMA2_CH7
#define UART7_TX_DMA_IRQ DMA2_Channel7_IRQn
#define UART7_TX_DMA_RCC RCC_AHB_PERIPHEN_DMA2
#define UART7_TX_DMA_REQUEST DMA_REMAP_UART7_TX
#define UART7_TX_DMA_CHANNEL 7U
#endif
/* DMA2 channel8 */
#if defined(BSP_UART8_TX_USING_DMA) && !defined(UART8_TX_DMA)
#define UART8_TX_DMA DMA2
#define UART8_TX_DMA_IRQHandler DMA2_Channel8_IRQHandler
#define UART8_TX_DMA_CHType DMA2_CH8
#define UART8_TX_DMA_IRQ DMA2_Channel8_IRQn
#define UART8_TX_DMA_RCC RCC_AHB_PERIPHEN_DMA2
#define UART8_TX_DMA_REQUEST DMA_REMAP_UART8_TX
#define UART8_TX_DMA_CHANNEL 8U
#endif
#ifdef __cplusplus
}
#endif
#endif /* __DMA_CONFIG_H__ */

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/*
* Copyright (c) 2006-2025, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2026-04-07 ox-horse first version
*/
#ifndef __UART_CONFIG_H__
#define __UART_CONFIG_H__
#include <rtthread.h>
#ifdef __cplusplus
extern "C" {
#endif
#if defined(BSP_USING_UART1)
#ifndef UART1_CONFIG
#define UART1_CONFIG \
{ \
.name = "uart1", \
.Instance = USART1, \
.irq_type = USART1_IRQn, \
.periph = RCC_APB2_PERIPH_USART1, \
.EnablePeriphClk = RCC_EnableAPB2PeriphClk, \
}
#endif /* UART1_CONFIG */
#endif /* BSP_USING_UART1 */
#if defined(BSP_UART1_RX_USING_DMA)
#if defined(UART1_RX_DMA)
#ifndef UART1_DMA_RX_CONFIG
#define UART1_DMA_RX_CONFIG \
{ \
.DMAy = UART1_RX_DMA, \
.DMAChx = UART1_RX_DMA_CHType, \
.dma_irq = UART1_RX_DMA_IRQ, \
.dma_rcc = UART1_RX_DMA_RCC, \
.request = UART1_RX_DMA_REQUEST, \
.channel = UART1_RX_DMA_CHANNEL, \
}
#endif /* UART1_DMA_RX_CONFIG */
#else
#error "The DMA resource is not available."
#endif /* UART1_RX_DMA */
#endif /* BSP_UART1_RX_USING_DMA */
#if defined(BSP_UART1_TX_USING_DMA)
#if defined(UART1_TX_DMA)
#ifndef UART1_DMA_TX_CONFIG
#define UART1_DMA_TX_CONFIG \
{ \
.DMAy = UART1_TX_DMA, \
.DMAChx = UART1_TX_DMA_CHType, \
.dma_irq = UART1_TX_DMA_IRQ, \
.dma_rcc = UART1_TX_DMA_RCC, \
.request = UART1_TX_DMA_REQUEST, \
.channel = UART1_TX_DMA_CHANNEL, \
}
#endif /* UART1_DMA_TX_CONFIG */
#else
#error "The DMA resource is not available."
#endif /* UART1_TX_DMA */
#endif /* BSP_UART1_TX_USING_DMA */
#if defined(BSP_USING_UART2)
#ifndef UART2_CONFIG
#define UART2_CONFIG \
{ \
.name = "uart2", \
.Instance = USART2, \
.irq_type = USART2_IRQn, \
.periph = RCC_APB1_PERIPH_USART2, \
.EnablePeriphClk = RCC_EnableAPB1PeriphClk, \
}
#endif /* UART2_CONFIG */
#endif /* BSP_USING_UART2 */
#if defined(BSP_UART2_RX_USING_DMA)
#if defined(UART2_RX_DMA)
#ifndef UART2_DMA_RX_CONFIG
#define UART2_DMA_RX_CONFIG \
{ \
.DMAy = UART2_RX_DMA, \
.DMAChx = UART2_RX_DMA_CHType, \
.dma_irq = UART2_RX_DMA_IRQ, \
.dma_rcc = UART2_RX_DMA_RCC, \
.request = UART2_RX_DMA_REQUEST, \
.channel = UART2_RX_DMA_CHANNEL, \
}
#endif /* UART2_DMA_RX_CONFIG */
#else
#error "The DMA resource is not available."
#endif /* UART2_RX_DMA */
#endif /* BSP_UART2_RX_USING_DMA */
#if defined(BSP_UART2_TX_USING_DMA)
#if defined(UART2_TX_DMA)
#ifndef UART2_DMA_TX_CONFIG
#define UART2_DMA_TX_CONFIG \
{ \
.DMAy = UART2_TX_DMA, \
.DMAChx = UART2_TX_DMA_CHType, \
.dma_irq = UART2_TX_DMA_IRQ, \
.dma_rcc = UART2_TX_DMA_RCC, \
.request = UART2_TX_DMA_REQUEST, \
.channel = UART2_TX_DMA_CHANNEL, \
}
#endif /* UART2_DMA_TX_CONFIG */
#else
#error "The DMA resource is not available."
#endif /* UART2_TX_DMA */
#endif /* BSP_UART2_TX_USING_DMA */
#if defined(BSP_USING_UART3)
#ifndef UART3_CONFIG
#define UART3_CONFIG \
{ \
.name = "uart3", \
.Instance = USART3, \
.irq_type = USART3_IRQn, \
.periph = RCC_APB1_PERIPH_USART3, \
.EnablePeriphClk = RCC_EnableAPB1PeriphClk, \
}
#endif /* UART3_CONFIG */
#endif /* BSP_USING_UART3 */
#if defined(BSP_UART3_RX_USING_DMA)
#if defined(UART3_RX_DMA)
#ifndef UART3_DMA_RX_CONFIG
#define UART3_DMA_RX_CONFIG \
{ \
.DMAy = UART3_RX_DMA, \
.DMAChx = UART3_RX_DMA_CHType, \
.dma_irq = UART3_RX_DMA_IRQ, \
.dma_rcc = UART3_RX_DMA_RCC, \
.request = UART3_RX_DMA_REQUEST, \
.channel = UART3_RX_DMA_CHANNEL, \
}
#endif /* UART3_DMA_RX_CONFIG */
#else
#error "The DMA resource is not available."
#endif /* UART3_RX_DMA */
#endif /* BSP_UART3_RX_USING_DMA */
#if defined(BSP_UART3_TX_USING_DMA)
#if defined(UART3_TX_DMA)
#ifndef UART3_DMA_TX_CONFIG
#define UART3_DMA_TX_CONFIG \
{ \
.DMAy = UART3_TX_DMA, \
.DMAChx = UART3_TX_DMA_CHType, \
.dma_irq = UART3_TX_DMA_IRQ, \
.dma_rcc = UART3_TX_DMA_RCC, \
.request = UART3_TX_DMA_REQUEST, \
.channel = UART3_TX_DMA_CHANNEL, \
}
#endif /* UART3_DMA_TX_CONFIG */
#else
#error "The DMA resource is not available."
#endif /* UART3_TX_DMA */
#endif /* BSP_UART3_TX_USING_DMA */
#if defined(BSP_USING_UART4)
#ifndef UART4_CONFIG
#define UART4_CONFIG \
{ \
.name = "uart4", \
.Instance = USART4, \
.irq_type = USART4_IRQn, \
.periph = RCC_APB2_PERIPH_USART4, \
.EnablePeriphClk = RCC_EnableAPB2PeriphClk, \
}
#endif /* UART4_CONFIG */
#endif /* BSP_USING_UART4 */
#if defined(BSP_UART4_RX_USING_DMA)
#if defined(UART4_RX_DMA)
#ifndef UART4_DMA_RX_CONFIG
#define UART4_DMA_RX_CONFIG \
{ \
.DMAy = UART4_RX_DMA, \
.DMAChx = UART4_RX_DMA_CHType, \
.dma_irq = UART4_RX_DMA_IRQ, \
.dma_rcc = UART4_RX_DMA_RCC, \
.request = UART4_RX_DMA_REQUEST, \
.channel = UART4_RX_DMA_CHANNEL, \
}
#endif /* UART4_DMA_RX_CONFIG */
#else
#error "The DMA resource is not available."
#endif /* UART4_RX_DMA */
#endif /* BSP_UART4_RX_USING_DMA */
#if defined(BSP_UART4_TX_USING_DMA)
#if defined(UART4_TX_DMA)
#ifndef UART4_DMA_TX_CONFIG
#define UART4_DMA_TX_CONFIG \
{ \
.DMAy = UART4_TX_DMA, \
.DMAChx = UART4_TX_DMA_CHType, \
.dma_irq = UART4_TX_DMA_IRQ, \
.dma_rcc = UART4_TX_DMA_RCC, \
.request = UART4_TX_DMA_REQUEST, \
.channel = UART4_TX_DMA_CHANNEL, \
}
#endif /* UART4_DMA_TX_CONFIG */
#else
#error "The DMA resource is not available."
#endif /* UART4_TX_DMA */
#endif /* BSP_UART4_TX_USING_DMA */
#if defined(BSP_USING_UART5)
#ifndef UART5_CONFIG
#define UART5_CONFIG \
{ \
.name = "uart5", \
.Instance = UART5, \
.irq_type = UART5_IRQn, \
.periph = RCC_APB1_PERIPH_UART5, \
.EnablePeriphClk = RCC_EnableAPB1PeriphClk, \
}
#endif /* UART5_CONFIG */
#endif /* BSP_USING_UART5 */
#if defined(BSP_UART5_RX_USING_DMA)
#if defined(UART5_RX_DMA)
#ifndef UART5_DMA_RX_CONFIG
#define UART5_DMA_RX_CONFIG \
{ \
.DMAy = UART5_RX_DMA, \
.DMAChx = UART5_RX_DMA_CHType, \
.dma_irq = UART5_RX_DMA_IRQ, \
.dma_rcc = UART5_RX_DMA_RCC, \
.request = UART5_RX_DMA_REQUEST, \
.channel = UART5_RX_DMA_CHANNEL, \
}
#endif /* UART5_DMA_RX_CONFIG */
#else
#error "The DMA resource is not available."
#endif /* UART5_RX_DMA */
#endif /* BSP_UART5_RX_USING_DMA */
#if defined(BSP_UART5_TX_USING_DMA)
#if defined(UART5_TX_DMA)
#ifndef UART5_DMA_TX_CONFIG
#define UART5_DMA_TX_CONFIG \
{ \
.DMAy = UART5_TX_DMA, \
.DMAChx = UART5_TX_DMA_CHType, \
.dma_irq = UART5_TX_DMA_IRQ, \
.dma_rcc = UART5_TX_DMA_RCC, \
.request = UART5_TX_DMA_REQUEST, \
.channel = UART5_TX_DMA_CHANNEL, \
}
#endif /* UART5_DMA_TX_CONFIG */
#else
#error "The DMA resource is not available."
#endif /* UART5_TX_DMA */
#endif /* BSP_UART5_TX_USING_DMA */
#if defined(BSP_USING_UART6)
#ifndef UART6_CONFIG
#define UART6_CONFIG \
{ \
.name = "uart6", \
.Instance = UART6, \
.irq_type = UART6_IRQn, \
.periph = RCC_APB2_PERIPH_UART6, \
.EnablePeriphClk = RCC_EnableAPB2PeriphClk, \
}
#endif /* UART6_CONFIG */
#endif /* BSP_USING_UART6 */
#if defined(BSP_UART6_RX_USING_DMA)
#if defined(UART6_RX_DMA)
#ifndef UART6_DMA_RX_CONFIG
#define UART6_DMA_RX_CONFIG \
{ \
.DMAy = UART6_RX_DMA, \
.DMAChx = UART6_RX_DMA_CHType, \
.dma_irq = UART6_RX_DMA_IRQ, \
.dma_rcc = UART6_RX_DMA_RCC, \
.request = UART6_RX_DMA_REQUEST, \
.channel = UART6_RX_DMA_CHANNEL, \
}
#endif /* UART6_DMA_RX_CONFIG */
#else
#error "The DMA resource is not available."
#endif /* UART6_RX_DMA */
#endif /* BSP_UART6_RX_USING_DMA */
#if defined(BSP_UART6_TX_USING_DMA)
#if defined(UART6_TX_DMA)
#ifndef UART6_DMA_TX_CONFIG
#define UART6_DMA_TX_CONFIG \
{ \
.DMAy = UART6_TX_DMA, \
.DMAChx = UART6_TX_DMA_CHType, \
.dma_irq = UART6_TX_DMA_IRQ, \
.dma_rcc = UART6_TX_DMA_RCC, \
.request = UART6_TX_DMA_REQUEST, \
.channel = UART6_TX_DMA_CHANNEL, \
}
#endif /* UART6_DMA_TX_CONFIG */
#else
#error "The DMA resource is not available."
#endif /* UART6_TX_DMA */
#endif /* BSP_UART6_TX_USING_DMA */
#if defined(BSP_USING_UART7)
#ifndef UART7_CONFIG
#define UART7_CONFIG \
{ \
.name = "uart7", \
.Instance = UART7, \
.irq_type = UART7_IRQn, \
.periph = RCC_APB2_PERIPH_UART7, \
.EnablePeriphClk = RCC_EnableAPB2PeriphClk, \
}
#endif /* UART7_CONFIG */
#endif /* BSP_USING_UART7 */
#if defined(BSP_UART7_RX_USING_DMA)
#if defined(UART7_RX_DMA)
#ifndef UART7_DMA_RX_CONFIG
#define UART7_DMA_RX_CONFIG \
{ \
.DMAy = UART7_RX_DMA, \
.DMAChx = UART7_RX_DMA_CHType, \
.dma_irq = UART7_RX_DMA_IRQ, \
.dma_rcc = UART7_RX_DMA_RCC, \
.request = UART7_RX_DMA_REQUEST, \
.channel = UART7_RX_DMA_CHANNEL, \
}
#endif /* UART7_DMA_RX_CONFIG */
#else
#error "The DMA resource is not available."
#endif /* UART7_RX_DMA */
#endif /* BSP_UART7_RX_USING_DMA */
#if defined(BSP_UART7_TX_USING_DMA)
#if defined(UART7_TX_DMA)
#ifndef UART7_DMA_TX_CONFIG
#define UART7_DMA_TX_CONFIG \
{ \
.DMAy = UART7_TX_DMA, \
.DMAChx = UART7_TX_DMA_CHType, \
.dma_irq = UART7_TX_DMA_IRQ, \
.dma_rcc = UART7_TX_DMA_RCC, \
.request = UART7_TX_DMA_REQUEST, \
.channel = UART7_TX_DMA_CHANNEL, \
}
#endif /* UART7_DMA_TX_CONFIG */
#else
#error "The DMA resource is not available."
#endif /* UART7_TX_DMA */
#endif /* BSP_UART7_TX_USING_DMA */
#if defined(BSP_USING_UART8)
#ifndef UART8_CONFIG
#define UART8_CONFIG \
{ \
.name = "uart8", \
.Instance = UART8, \
.irq_type = UART8_IRQn, \
.periph = RCC_APB1_PERIPH_UART8, \
.EnablePeriphClk = RCC_EnableAPB1PeriphClk, \
}
#endif /* UART8_CONFIG */
#endif /* BSP_USING_UART8 */
#if defined(BSP_UART8_RX_USING_DMA)
#if defined(UART8_RX_DMA)
#ifndef UART8_DMA_RX_CONFIG
#define UART8_DMA_RX_CONFIG \
{ \
.DMAy = UART8_RX_DMA, \
.DMAChx = UART8_RX_DMA_CHType, \
.dma_irq = UART8_RX_DMA_IRQ, \
.dma_rcc = UART8_RX_DMA_RCC, \
.request = UART8_RX_DMA_REQUEST, \
.channel = UART8_RX_DMA_CHANNEL, \
}
#endif /* UART8_DMA_RX_CONFIG */
#else
#error "The DMA resource is not available."
#endif /* UART8_RX_DMA */
#endif /* BSP_UART8_RX_USING_DMA */
#if defined(BSP_UART8_TX_USING_DMA)
#if defined(UART8_TX_DMA)
#ifndef UART8_DMA_TX_CONFIG
#define UART8_DMA_TX_CONFIG \
{ \
.DMAy = UART8_TX_DMA, \
.DMAChx = UART8_TX_DMA_CHType, \
.dma_irq = UART8_TX_DMA_IRQ, \
.dma_rcc = UART8_TX_DMA_RCC, \
.request = UART8_TX_DMA_REQUEST, \
.channel = UART8_TX_DMA_CHANNEL, \
}
#endif /* UART8_DMA_TX_CONFIG */
#else
#error "The DMA resource is not available."
#endif /* UART8_TX_DMA */
#endif /* BSP_UART8_TX_USING_DMA */
#ifdef __cplusplus
}
#endif
#endif /* __UART_CONFIG_H__ */

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/*
* Copyright (c) 2006-2025, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2026-04-07 ox-horse first version
*/
#ifndef __DMA_CONFIG_H__
#define __DMA_CONFIG_H__
#include <rtthread.h>
#ifdef __cplusplus
extern "C" {
#endif
/* DMA1 channel1 */
#if defined(BSP_UART1_RX_USING_DMA) && !defined(UART1_RX_DMA)
#define UART1_RX_DMA DMA1
#define UART1_RX_DMA_IRQHandler DMA1_Channel1_IRQHandler
#define UART1_RX_DMA_CHType DMA1_CH1
#define UART1_RX_DMA_IRQ DMA1_Channel1_IRQn
#define UART1_RX_DMA_RCC RCC_AHB_PERIPHEN_DMA1
#define UART1_RX_DMA_REQUEST DMA_REMAP_USART1_RX
#define UART1_RX_DMA_CHANNEL 1U
#endif
/* DMA1 channel2 */
#if defined(BSP_UART2_RX_USING_DMA) && !defined(UART2_RX_DMA)
#define UART2_RX_DMA DMA1
#define UART2_RX_DMA_IRQHandler DMA1_Channel2_IRQHandler
#define UART2_RX_DMA_CHType DMA1_CH2
#define UART2_RX_DMA_IRQ DMA1_Channel2_IRQn
#define UART2_RX_DMA_RCC RCC_AHB_PERIPHEN_DMA1
#define UART2_RX_DMA_REQUEST DMA_REMAP_USART2_RX
#define UART2_RX_DMA_CHANNEL 2U
#elif defined(BSP_I2C2_RX_USING_DMA) && !defined(I2C2_RX_DMA)
#define I2C2_RX_DMA DMA1
#define I2C2_RX_DMA_IRQHandler DMA1_Channel2_IRQHandler
#define I2C2_RX_DMA_CHType DMA1_CH2
#define I2C2_RX_DMA_IRQ DMA1_Channel2_IRQn
#define I2C2_RX_DMA_RCC RCC_AHB_PERIPHEN_DMA1
#define I2C2_RX_DMA_REQUEST DMA_REMAP_I2C2_RX
#define I2C2_RX_DMA_CHANNEL 2U
#endif
/* DMA1 channel3 */
#if defined(BSP_UART3_RX_USING_DMA) && !defined(UART3_RX_DMA)
#define UART3_RX_DMA DMA1
#define UART3_RX_DMA_IRQHandler DMA1_Channel3_IRQHandler
#define UART3_RX_DMA_CHType DMA1_CH3
#define UART3_RX_DMA_IRQ DMA1_Channel3_IRQn
#define UART3_RX_DMA_RCC RCC_AHB_PERIPHEN_DMA1
#define UART3_RX_DMA_REQUEST DMA_REMAP_USART3_RX
#define UART3_RX_DMA_CHANNEL 3U
#elif defined(BSP_I2C3_RX_USING_DMA) && !defined(I2C3_RX_DMA)
#define I2C3_RX_DMA DMA1
#define I2C3_RX_DMA_IRQHandler DMA1_Channel3_IRQHandler
#define I2C3_RX_DMA_CHType DMA1_CH3
#define I2C3_RX_DMA_IRQ DMA1_Channel3_IRQn
#define I2C3_RX_DMA_RCC RCC_AHB_PERIPHEN_DMA1
#define I2C3_RX_DMA_REQUEST DMA_REMAP_I2C3_RX
#define I2C3_RX_DMA_CHANNEL 3U
#endif
/* DMA1 channel4 */
#if defined(BSP_UART4_RX_USING_DMA) && !defined(UART4_RX_DMA)
#define UART4_RX_DMA DMA1
#define UART4_RX_DMA_IRQHandler DMA1_Channel4_IRQHandler
#define UART4_RX_DMA_CHType DMA1_CH4
#define UART4_RX_DMA_IRQ DMA1_Channel4_IRQn
#define UART4_RX_DMA_RCC RCC_AHB_PERIPHEN_DMA1
#define UART4_RX_DMA_REQUEST DMA_REMAP_USART4_RX
#define UART4_RX_DMA_CHANNEL 4U
#elif defined(BSP_SPI6_RX_USING_DMA) && !defined(SPI6_RX_DMA)
#define SPI6_RX_DMA DMA1
#define SPI6_RX_DMA_IRQHandler DMA1_Channel4_IRQHandler
#define SPI6_RX_DMA_CHType DMA1_CH4
#define SPI6_RX_DMA_IRQ DMA1_Channel4_IRQn
#define SPI6_RX_DMA_RCC RCC_AHB_PERIPHEN_DMA1
#define SPI6_RX_DMA_REQUEST DMA_REMAP_SPI6_RX
#define SPI6_RX_DMA_CHANNEL 4U
#elif defined(BSP_I2C4_RX_USING_DMA) && !defined(I2C4_RX_DMA)
#define I2C4_RX_DMA DMA1
#define I2C4_RX_DMA_IRQHandler DMA1_Channel4_IRQHandler
#define I2C4_RX_DMA_CHType DMA1_CH4
#define I2C4_RX_DMA_IRQ DMA1_Channel4_IRQn
#define I2C4_RX_DMA_RCC RCC_AHB_PERIPHEN_DMA1
#define I2C4_RX_DMA_REQUEST DMA_REMAP_I2C4_RX
#define I2C4_RX_DMA_CHANNEL 4U
#endif
/* DMA1 channel5 */
#if defined(BSP_UART5_RX_USING_DMA) && !defined(UART5_RX_DMA)
#define UART5_RX_DMA DMA1
#define UART5_RX_DMA_IRQHandler DMA1_Channel5_IRQHandler
#define UART5_RX_DMA_CHType DMA1_CH5
#define UART5_RX_DMA_IRQ DMA1_Channel5_IRQn
#define UART5_RX_DMA_RCC RCC_AHB_PERIPHEN_DMA1
#define UART5_RX_DMA_REQUEST DMA_REMAP_UART5_RX
#define UART5_RX_DMA_CHANNEL 5U
#elif defined(BSP_UART10_TX_USING_DMA) && !defined(UART10_TX_DMA)
#define UART10_TX_DMA DMA1
#define UART10_TX_DMA_IRQHandler DMA1_Channel5_IRQHandler
#define UART10_TX_DMA_CHType DMA1_CH5
#define UART10_TX_DMA_IRQ DMA1_Channel5_IRQn
#define UART10_TX_DMA_RCC RCC_AHB_PERIPHEN_DMA1
#define UART10_TX_DMA_REQUEST DMA_REMAP_UART10_TX
#define UART10_TX_DMA_CHANNEL 5U
#elif defined(BSP_SPI5_RX_USING_DMA) && !defined(SPI5_RX_DMA)
#define SPI5_RX_DMA DMA1
#define SPI5_RX_DMA_IRQHandler DMA1_Channel5_IRQHandler
#define SPI5_RX_DMA_CHType DMA1_CH5
#define SPI5_RX_DMA_IRQ DMA1_Channel5_IRQn
#define SPI5_RX_DMA_RCC RCC_AHB_PERIPHEN_DMA1
#define SPI5_RX_DMA_REQUEST DMA_REMAP_SPI5_RX
#define SPI5_RX_DMA_CHANNEL 5U
#endif
/* DMA1 channel6 */
#if defined(BSP_UART6_RX_USING_DMA) && !defined(UART6_RX_DMA)
#define UART6_RX_DMA DMA1
#define UART6_RX_DMA_IRQHandler DMA1_Channel6_IRQHandler
#define UART6_RX_DMA_CHType DMA1_CH6
#define UART6_RX_DMA_IRQ DMA1_Channel6_IRQn
#define UART6_RX_DMA_RCC RCC_AHB_PERIPHEN_DMA1
#define UART6_RX_DMA_REQUEST DMA_REMAP_UART6_RX
#define UART6_RX_DMA_CHANNEL 6U
#elif defined(BSP_UART9_TX_USING_DMA) && !defined(UART9_TX_DMA)
#define UART9_TX_DMA DMA1
#define UART9_TX_DMA_IRQHandler DMA1_Channel6_IRQHandler
#define UART9_TX_DMA_CHType DMA1_CH6
#define UART9_TX_DMA_IRQ DMA1_Channel6_IRQn
#define UART9_TX_DMA_RCC RCC_AHB_PERIPHEN_DMA1
#define UART9_TX_DMA_REQUEST DMA_REMAP_USART9_TX
#define UART9_TX_DMA_CHANNEL 6U
#elif defined(BSP_SPI4_RX_USING_DMA) && !defined(SPI4_RX_DMA)
#define SPI4_RX_DMA DMA1
#define SPI4_RX_DMA_IRQHandler DMA1_Channel6_IRQHandler
#define SPI4_RX_DMA_CHType DMA1_CH6
#define SPI4_RX_DMA_IRQ DMA1_Channel6_IRQn
#define SPI4_RX_DMA_RCC RCC_AHB_PERIPHEN_DMA1
#define SPI4_RX_DMA_REQUEST DMA_REMAP_SPI4_RX
#define SPI4_RX_DMA_CHANNEL 6U
#endif
/* DMA1 channel7 */
#if defined(BSP_UART7_RX_USING_DMA) && !defined(UART7_RX_DMA)
#define UART7_RX_DMA DMA1
#define UART7_RX_DMA_IRQHandler DMA1_Channel7_IRQHandler
#define UART7_RX_DMA_CHType DMA1_CH7
#define UART7_RX_DMA_IRQ DMA1_Channel7_IRQn
#define UART7_RX_DMA_RCC RCC_AHB_PERIPHEN_DMA1
#define UART7_RX_DMA_REQUEST DMA_REMAP_UART7_RX
#define UART7_RX_DMA_CHANNEL 7U
#elif defined(BSP_UART8_TX_USING_DMA) && !defined(UART8_TX_DMA)
#define UART8_TX_DMA DMA1
#define UART8_TX_DMA_IRQHandler DMA1_Channel7_IRQHandler
#define UART8_TX_DMA_CHType DMA1_CH7
#define UART8_TX_DMA_IRQ DMA1_Channel7_IRQn
#define UART8_TX_DMA_RCC RCC_AHB_PERIPHEN_DMA1
#define UART8_TX_DMA_REQUEST DMA_REMAP_UART8_TX
#define UART8_TX_DMA_CHANNEL 7U
#elif defined(BSP_SPI3_RX_USING_DMA) && !defined(SPI3_RX_DMA)
#define SPI3_RX_DMA DMA1
#define SPI3_RX_DMA_IRQHandler DMA1_Channel7_IRQHandler
#define SPI3_RX_DMA_CHType DMA1_CH7
#define SPI3_RX_DMA_IRQ DMA1_Channel7_IRQn
#define SPI3_RX_DMA_RCC RCC_AHB_PERIPHEN_DMA1
#define SPI3_RX_DMA_REQUEST DMA_REMAP_SPI3_I2S3_RX
#define SPI3_RX_DMA_CHANNEL 7U
#endif
/* DMA1 channel8 */
#if defined(BSP_UART8_RX_USING_DMA) && !defined(UART8_RX_DMA)
#define UART8_RX_DMA DMA1
#define UART8_RX_DMA_IRQHandler DMA1_Channel8_IRQHandler
#define UART8_RX_DMA_CHType DMA1_CH8
#define UART8_RX_DMA_IRQ DMA1_Channel8_IRQn
#define UART8_RX_DMA_RCC RCC_AHB_PERIPHEN_DMA1
#define UART8_RX_DMA_REQUEST DMA_REMAP_UART8_RX
#define UART8_RX_DMA_CHANNEL 8U
#elif defined(BSP_UART7_TX_USING_DMA) && !defined(UART7_TX_DMA)
#define UART7_TX_DMA DMA1
#define UART7_TX_DMA_IRQHandler DMA1_Channel8_IRQHandler
#define UART7_TX_DMA_CHType DMA1_CH8
#define UART7_TX_DMA_IRQ DMA1_Channel8_IRQn
#define UART7_TX_DMA_RCC RCC_AHB_PERIPHEN_DMA1
#define UART7_TX_DMA_REQUEST DMA_REMAP_UART7_TX
#define UART7_TX_DMA_CHANNEL 8U
#elif defined(BSP_SPI2_RX_USING_DMA) && !defined(SPI2_RX_DMA)
#define SPI2_RX_DMA DMA1
#define SPI2_RX_DMA_IRQHandler DMA1_Channel8_IRQHandler
#define SPI2_RX_DMA_CHType DMA1_CH8
#define SPI2_RX_DMA_IRQ DMA1_Channel8_IRQn
#define SPI2_RX_DMA_RCC RCC_AHB_PERIPHEN_DMA1
#define SPI2_RX_DMA_REQUEST DMA_REMAP_SPI2_I2S2_RX
#define SPI2_RX_DMA_CHANNEL 8U
#endif
/* DMA2 channel1 */
#if defined(BSP_UART9_RX_USING_DMA) && !defined(UART9_RX_DMA)
#define UART9_RX_DMA DMA2
#define UART9_RX_DMA_IRQHandler DMA2_Channel1_IRQHandler
#define UART9_RX_DMA_CHType DMA2_CH1
#define UART9_RX_DMA_IRQ DMA2_Channel1_IRQn
#define UART9_RX_DMA_RCC RCC_AHB_PERIPHEN_DMA2
#define UART9_RX_DMA_REQUEST DMA_REMAP_USART9_RX
#define UART9_RX_DMA_CHANNEL 1U
#elif defined(BSP_SPI1_RX_USING_DMA) && !defined(SPI1_RX_DMA)
#define SPI1_RX_DMA DMA2
#define SPI1_RX_DMA_IRQHandler DMA2_Channel1_IRQHandler
#define SPI1_RX_DMA_CHType DMA2_CH1
#define SPI1_RX_DMA_IRQ DMA2_Channel1_IRQn
#define SPI1_RX_DMA_RCC RCC_AHB_PERIPHEN_DMA2
#define SPI1_RX_DMA_REQUEST DMA_REMAP_SPI1_RX
#define SPI1_RX_DMA_CHANNEL 1U
#elif defined(BSP_I2C1_RX_USING_DMA) && !defined(I2C1_RX_DMA)
#define I2C1_RX_DMA DMA2
#define I2C1_RX_DMA_IRQHandler DMA2_Channel1_IRQHandler
#define I2C1_RX_DMA_CHType DMA2_CH1
#define I2C1_RX_DMA_IRQ DMA2_Channel1_IRQn
#define I2C1_RX_DMA_RCC RCC_AHB_PERIPHEN_DMA2
#define I2C1_RX_DMA_REQUEST DMA_REMAP_I2C1_RX
#define I2C1_RX_DMA_CHANNEL 1U
#endif
/* DMA2 channel2 */
#if defined(BSP_UART10_RX_USING_DMA) && !defined(UART10_RX_DMA)
#define UART10_RX_DMA DMA2
#define UART10_RX_DMA_IRQHandler DMA2_Channel2_IRQHandler
#define UART10_RX_DMA_CHType DMA2_CH2
#define UART10_RX_DMA_IRQ DMA2_Channel2_IRQn
#define UART10_RX_DMA_RCC RCC_AHB_PERIPHEN_DMA2
#define UART10_RX_DMA_REQUEST DMA_REMAP_UART10_RX
#define UART10_RX_DMA_CHANNEL 2U
#elif defined(BSP_USING_SDIO) && !defined(UART10_RX_DMA)
#define SDIO_RX_DMA DMA2
#define SDIO_TX_DMA DMA2
#define SDIO_RX_TX_DMA_IRQHandler DMA2_Channel2_IRQHandler
#define SDIO_TX_DMA_CHType DMA2_CH2
#define SDIO_RX_DMA_CHType DMA2_CH2
#define SDIO_TX_DMA_IRQ DMA2_Channel2_IRQn
#define SDIO_RX_DMA_IRQ DMA2_Channel2_IRQn
#define SDIO_TX_DMA_RCC RCC_AHB_PERIPHEN_DMA2
#define SDIO_RX_DMA_RCC RCC_AHB_PERIPHEN_DMA2
#define SDIO_TX_DMA_REQUEST DMA_REMAP_SDIO
#define SDIO_RX_DMA_REQUEST DMA_REMAP_SDIO
#define SDIO_TX_DMA_CHANNEL 2U
#define SDIO_RX_DMA_CHANNEL 2U
#endif
/* DMA2 channel3 */
#if defined(BSP_UART1_TX_USING_DMA) && !defined(UART1_TX_DMA)
#define UART1_TX_DMA DMA2
#define UART1_TX_DMA_IRQHandler DMA2_Channel3_IRQHandler
#define UART1_TX_DMA_CHType DMA2_CH3
#define UART1_TX_DMA_IRQ DMA2_Channel3_IRQn
#define UART1_TX_DMA_RCC RCC_AHB_PERIPHEN_DMA2
#define UART1_TX_DMA_REQUEST DMA_REMAP_USART1_TX
#define UART1_TX_DMA_CHANNEL 3U
#elif defined(BSP_SPI6_TX_USING_DMA) && !defined(SPI6_TX_DMA)
#define SPI6_TX_DMA DMA2
#define SPI6_TX_DMA_IRQHandler DMA2_Channel3_IRQHandler
#define SPI6_TX_DMA_CHType DMA2_CH3
#define SPI6_TX_DMA_IRQ DMA2_Channel3_IRQn
#define SPI6_TX_DMA_RCC RCC_AHB_PERIPHEN_DMA2
#define SPI6_TX_DMA_REQUEST DMA_REMAP_SPI6_TX
#define SPI6_TX_DMA_CHANNEL 3U
#elif defined(BSP_I2C1_TX_USING_DMA) && !defined(I2C1_TX_DMA)
#define I2C1_TX_DMA DMA2
#define I2C1_TX_DMA_IRQHandler DMA2_Channel3_IRQHandler
#define I2C1_TX_DMA_CHType DMA2_CH3
#define I2C1_TX_DMA_IRQ DMA2_Channel3_IRQn
#define I2C1_TX_DMA_RCC RCC_AHB_PERIPHEN_DMA2
#define I2C1_TX_DMA_REQUEST DMA_REMAP_I2C1_TX
#define I2C1_TX_DMA_CHANNEL 3U
#endif
/* DMA2 channel4 */
#if defined(BSP_UART2_TX_USING_DMA) && !defined(UART2_TX_DMA)
#define UART2_TX_DMA DMA2
#define UART2_TX_DMA_IRQHandler DMA2_Channel4_IRQHandler
#define UART2_TX_DMA_CHType DMA2_CH4
#define UART2_TX_DMA_IRQ DMA2_Channel4_IRQn
#define UART2_TX_DMA_RCC RCC_AHB_PERIPHEN_DMA2
#define UART2_TX_DMA_REQUEST DMA_REMAP_USART2_TX
#define UART2_TX_DMA_CHANNEL 4U
#elif defined(BSP_SPI5_TX_USING_DMA) && !defined(SPI5_TX_DMA)
#define SPI5_TX_DMA DMA2
#define SPI5_TX_DMA_IRQHandler DMA2_Channel4_IRQHandler
#define SPI5_TX_DMA_CHType DMA2_CH4
#define SPI5_TX_DMA_IRQ DMA2_Channel4_IRQn
#define SPI5_TX_DMA_RCC RCC_AHB_PERIPHEN_DMA2
#define SPI5_TX_DMA_REQUEST DMA_REMAP_SPI5_TX
#define SPI5_TX_DMA_CHANNEL 4U
#endif
/* DMA2 channel5 */
#if defined(BSP_UART3_TX_USING_DMA) && !defined(UART3_TX_DMA)
#define UART3_TX_DMA DMA2
#define UART3_TX_DMA_IRQHandler DMA2_Channel5_IRQHandler
#define UART3_TX_DMA_CHType DMA2_CH5
#define UART3_TX_DMA_IRQ DMA2_Channel5_IRQn
#define UART3_TX_DMA_RCC RCC_AHB_PERIPHEN_DMA2
#define UART3_TX_DMA_REQUEST DMA_REMAP_USART3_TX
#define UART3_TX_DMA_CHANNEL 5U
#elif defined(BSP_SPI4_TX_USING_DMA) && !defined(SPI4_TX_DMA)
#define SPI4_TX_DMA DMA2
#define SPI4_TX_DMA_IRQHandler DMA2_Channel5_IRQHandler
#define SPI4_TX_DMA_CHType DMA2_CH5
#define SPI4_TX_DMA_IRQ DMA2_Channel5_IRQn
#define SPI4_TX_DMA_RCC RCC_AHB_PERIPHEN_DMA2
#define SPI4_TX_DMA_REQUEST DMA_REMAP_SPI4_TX
#define SPI4_TX_DMA_CHANNEL 5U
#elif defined(BSP_I2C2_TX_USING_DMA) && !defined(I2C2_TX_DMA)
#define I2C2_TX_DMA DMA2
#define I2C2_TX_DMA_IRQHandler DMA2_Channel5_IRQHandler
#define I2C2_TX_DMA_CHType DMA2_CH5
#define I2C2_TX_DMA_IRQ DMA2_Channel5_IRQn
#define I2C2_TX_DMA_RCC RCC_AHB_PERIPHEN_DMA2
#define I2C2_TX_DMA_REQUEST DMA_REMAP_I2C2_TX
#define I2C2_TX_DMA_CHANNEL 5U
#endif
/* DMA2 channel6 */
#if defined(BSP_UART4_TX_USING_DMA) && !defined(UART4_TX_DMA)
#define UART4_TX_DMA DMA2
#define UART4_TX_DMA_IRQHandler DMA2_Channel6_IRQHandler
#define UART4_TX_DMA_CHType DMA2_CH6
#define UART4_TX_DMA_IRQ DMA2_Channel6_IRQn
#define UART4_TX_DMA_RCC RCC_AHB_PERIPHEN_DMA2
#define UART4_TX_DMA_REQUEST DMA_REMAP_USART4_TX
#define UART4_TX_DMA_CHANNEL 6U
#elif defined(BSP_SPI3_TX_USING_DMA) && !defined(SPI3_TX_DMA)
#define SPI3_TX_DMA DMA2
#define SPI3_TX_DMA_IRQHandler DMA2_Channel6_IRQHandler
#define SPI3_TX_DMA_CHType DMA2_CH6
#define SPI3_TX_DMA_IRQ DMA2_Channel6_IRQn
#define SPI3_TX_DMA_RCC RCC_AHB_PERIPHEN_DMA2
#define SPI3_TX_DMA_REQUEST DMA_REMAP_SPI3_I2S3_TX
#define SPI3_TX_DMA_CHANNEL 6U
#elif defined(BSP_I2C3_TX_USING_DMA) && !defined(I2C3_TX_DMA)
#define I2C3_TX_DMA DMA2
#define I2C3_TX_DMA_IRQHandler DMA2_Channel6_IRQHandler
#define I2C3_TX_DMA_CHType DMA2_CH6
#define I2C3_TX_DMA_IRQ DMA2_Channel6_IRQn
#define I2C3_TX_DMA_RCC RCC_AHB_PERIPHEN_DMA2
#define I2C3_TX_DMA_REQUEST DMA_REMAP_I2C3_TX
#define I2C3_TX_DMA_CHANNEL 6U
#endif
/* DMA2 channel7 */
#if defined(BSP_UART5_TX_USING_DMA) && !defined(UART5_TX_DMA)
#define UART5_TX_DMA DMA2
#define UART5_TX_DMA_IRQHandler DMA2_Channel7_IRQHandler
#define UART5_TX_DMA_CHType DMA2_CH7
#define UART5_TX_DMA_IRQ DMA2_Channel7_IRQn
#define UART5_TX_DMA_RCC RCC_AHB_PERIPHEN_DMA2
#define UART5_TX_DMA_REQUEST DMA_REMAP_UART5_TX
#define UART5_TX_DMA_CHANNEL 7U
#elif defined(BSP_SPI2_TX_USING_DMA) && !defined(SPI2_TX_DMA)
#define SPI2_TX_DMA DMA2
#define SPI2_TX_DMA_IRQHandler DMA2_Channel7_IRQHandler
#define SPI2_TX_DMA_CHType DMA2_CH7
#define SPI2_TX_DMA_IRQ DMA2_Channel7_IRQn
#define SPI2_TX_DMA_RCC RCC_AHB_PERIPHEN_DMA2
#define SPI2_TX_DMA_REQUEST DMA_REMAP_SPI2_I2S2_TX
#define SPI2_TX_DMA_CHANNEL 7U
#elif defined(BSP_I2C4_TX_USING_DMA) && !defined(I2C4_TX_DMA)
#define I2C4_TX_DMA DMA2
#define I2C4_TX_DMA_IRQHandler DMA2_Channel7_IRQHandler
#define I2C4_TX_DMA_CHType DMA2_CH7
#define I2C4_TX_DMA_IRQ DMA2_Channel7_IRQn
#define I2C4_TX_DMA_RCC RCC_AHB_PERIPHEN_DMA2
#define I2C4_TX_DMA_REQUEST DMA_REMAP_I2C4_TX
#define I2C4_TX_DMA_CHANNEL 7U
#endif
/* DMA2 channel8 */
#if defined(BSP_UART6_TX_USING_DMA) && !defined(UART6_TX_DMA)
#define UART6_TX_DMA DMA2
#define UART6_TX_DMA_IRQHandler DMA2_Channel8_IRQHandler
#define UART6_TX_DMA_CHType DMA2_CH8
#define UART6_TX_DMA_IRQ DMA2_Channel8_IRQn
#define UART6_TX_DMA_RCC RCC_AHB_PERIPHEN_DMA2
#define UART6_TX_DMA_REQUEST DMA_REMAP_UART6_TX
#define UART6_TX_DMA_CHANNEL 8U
#elif defined(BSP_SPI1_TX_USING_DMA) && !defined(SPI1_TX_DMA)
#define SPI1_TX_DMA DMA2
#define SPI1_TX_DMA_IRQHandler DMA2_Channel8_IRQHandler
#define SPI1_TX_DMA_CHType DMA2_CH8
#define SPI1_TX_DMA_IRQ DMA2_Channel8_IRQn
#define SPI1_TX_DMA_RCC RCC_AHB_PERIPHEN_DMA2
#define SPI1_TX_DMA_REQUEST DMA_REMAP_SPI1_TX
#define SPI1_TX_DMA_CHANNEL 8U
#endif
#ifdef __cplusplus
}
#endif
#endif /* __DMA_CONFIG_H__ */

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bsp/n32/n32hxxx/libraries/N32_Drivers/drivers/config/h49x/uart_config.h Normal file
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@ -0,0 +1,495 @@
/*
* Copyright (c) 2006-2025, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2026-04-07 ox-horse first version
*/
#ifndef __UART_CONFIG_H__
#define __UART_CONFIG_H__
#include <rtthread.h>
#ifdef __cplusplus
extern "C" {
#endif
#if defined(BSP_USING_UART1)
#ifndef UART1_CONFIG
#define UART1_CONFIG \
{ \
.name = "uart1", \
.Instance = USART1, \
.irq_type = USART1_IRQn, \
.periph = RCC_APB2_PERIPHEN_USART1, \
.EnablePeriphClk = RCC_EnableAPB2PeriphClk, \
}
#endif /* UART1_CONFIG */
#endif /* BSP_USING_UART1 */
#if defined(BSP_UART1_RX_USING_DMA)
#if defined(UART1_RX_DMA)
#ifndef UART1_DMA_RX_CONFIG
#define UART1_DMA_RX_CONFIG \
{ \
.DMAy = UART1_RX_DMA, \
.DMAChx = UART1_RX_DMA_CHType, \
.dma_irq = UART1_RX_DMA_IRQ, \
.dma_rcc = UART1_RX_DMA_RCC, \
.request = UART1_RX_DMA_REQUEST, \
.channel = UART1_RX_DMA_CHANNEL, \
}
#endif /* UART1_DMA_RX_CONFIG */
#else
#error "The DMA resource is not available."
#endif /* UART1_RX_DMA */
#endif /* BSP_UART1_RX_USING_DMA */
#if defined(BSP_UART1_TX_USING_DMA)
#if defined(UART1_TX_DMA)
#ifndef UART1_DMA_TX_CONFIG
#define UART1_DMA_TX_CONFIG \
{ \
.DMAy = UART1_TX_DMA, \
.DMAChx = UART1_TX_DMA_CHType, \
.dma_irq = UART1_TX_DMA_IRQ, \
.dma_rcc = UART1_TX_DMA_RCC, \
.request = UART1_TX_DMA_REQUEST, \
.channel = UART1_TX_DMA_CHANNEL, \
}
#endif /* UART1_DMA_TX_CONFIG */
#else
#error "The DMA resource is not available."
#endif /* UART1_TX_DMA */
#endif /* BSP_UART1_TX_USING_DMA */
#if defined(BSP_USING_UART2)
#ifndef UART2_CONFIG
#define UART2_CONFIG \
{ \
.name = "uart2", \
.Instance = USART2, \
.irq_type = USART2_IRQn, \
.periph = RCC_APB1_PERIPHEN_USART2, \
.EnablePeriphClk = RCC_EnableAPB1PeriphClk, \
}
#endif /* UART2_CONFIG */
#endif /* BSP_USING_UART2 */
#if defined(BSP_UART2_RX_USING_DMA)
#if defined(UART2_RX_DMA)
#ifndef UART2_DMA_RX_CONFIG
#define UART2_DMA_RX_CONFIG \
{ \
.DMAy = UART2_RX_DMA, \
.DMAChx = UART2_RX_DMA_CHType, \
.dma_irq = UART2_RX_DMA_IRQ, \
.dma_rcc = UART2_RX_DMA_RCC, \
.request = UART2_RX_DMA_REQUEST, \
.channel = UART2_RX_DMA_CHANNEL, \
}
#endif /* UART2_DMA_RX_CONFIG */
#else
#error "The DMA resource is not available."
#endif /* UART2_RX_DMA */
#endif /* BSP_UART2_RX_USING_DMA */
#if defined(BSP_UART2_TX_USING_DMA)
#if defined(UART2_TX_DMA)
#ifndef UART2_DMA_TX_CONFIG
#define UART2_DMA_TX_CONFIG \
{ \
.DMAy = UART2_TX_DMA, \
.DMAChx = UART2_TX_DMA_CHType, \
.dma_irq = UART2_TX_DMA_IRQ, \
.dma_rcc = UART2_TX_DMA_RCC, \
.request = UART2_TX_DMA_REQUEST, \
.channel = UART2_TX_DMA_CHANNEL, \
}
#endif /* UART2_DMA_TX_CONFIG */
#else
#error "The DMA resource is not available."
#endif /* UART2_TX_DMA */
#endif /* BSP_UART2_TX_USING_DMA */
#if defined(BSP_USING_UART3)
#ifndef UART3_CONFIG
#define UART3_CONFIG \
{ \
.name = "uart3", \
.Instance = USART3, \
.irq_type = USART3_IRQn, \
.periph = RCC_APB1_PERIPHEN_USART3, \
.EnablePeriphClk = RCC_EnableAPB1PeriphClk, \
}
#endif /* UART3_CONFIG */
#endif /* BSP_USING_UART3 */
#if defined(BSP_UART3_RX_USING_DMA)
#if defined(UART3_RX_DMA)
#ifndef UART3_DMA_RX_CONFIG
#define UART3_DMA_RX_CONFIG \
{ \
.DMAy = UART3_RX_DMA, \
.DMAChx = UART3_RX_DMA_CHType, \
.dma_irq = UART3_RX_DMA_IRQ, \
.dma_rcc = UART3_RX_DMA_RCC, \
.request = UART3_RX_DMA_REQUEST, \
.channel = UART3_RX_DMA_CHANNEL, \
}
#endif /* UART3_DMA_RX_CONFIG */
#else
#error "The DMA resource is not available."
#endif /* UART3_RX_DMA */
#endif /* BSP_UART3_RX_USING_DMA */
#if defined(BSP_UART3_TX_USING_DMA)
#if defined(UART3_TX_DMA)
#ifndef UART3_DMA_TX_CONFIG
#define UART3_DMA_TX_CONFIG \
{ \
.DMAy = UART3_TX_DMA, \
.DMAChx = UART3_TX_DMA_CHType, \
.dma_irq = UART3_TX_DMA_IRQ, \
.dma_rcc = UART3_TX_DMA_RCC, \
.request = UART3_TX_DMA_REQUEST, \
.channel = UART3_TX_DMA_CHANNEL, \
}
#endif /* UART3_DMA_TX_CONFIG */
#else
#error "The DMA resource is not available."
#endif /* UART3_TX_DMA */
#endif /* BSP_UART3_TX_USING_DMA */
#if defined(BSP_USING_UART4)
#ifndef UART4_CONFIG
#define UART4_CONFIG \
{ \
.name = "uart4", \
.Instance = USART4, \
.irq_type = USART4_IRQn, \
.periph = RCC_APB2_PERIPHEN_USART4, \
.EnablePeriphClk = RCC_EnableAPB2PeriphClk, \
}
#endif /* UART4_CONFIG */
#endif /* BSP_USING_UART4 */
#if defined(BSP_UART4_RX_USING_DMA)
#if defined(UART4_RX_DMA)
#ifndef UART4_DMA_RX_CONFIG
#define UART4_DMA_RX_CONFIG \
{ \
.DMAy = UART4_RX_DMA, \
.DMAChx = UART4_RX_DMA_CHType, \
.dma_irq = UART4_RX_DMA_IRQ, \
.dma_rcc = UART4_RX_DMA_RCC, \
.request = UART4_RX_DMA_REQUEST, \
.channel = UART4_RX_DMA_CHANNEL, \
}
#endif /* UART4_DMA_RX_CONFIG */
#else
#error "The DMA resource is not available."
#endif /* UART4_RX_DMA */
#endif /* BSP_UART4_RX_USING_DMA */
#if defined(BSP_UART4_TX_USING_DMA)
#if defined(UART4_TX_DMA)
#ifndef UART4_DMA_TX_CONFIG
#define UART4_DMA_TX_CONFIG \
{ \
.DMAy = UART4_TX_DMA, \
.DMAChx = UART4_TX_DMA_CHType, \
.dma_irq = UART4_TX_DMA_IRQ, \
.dma_rcc = UART4_TX_DMA_RCC, \
.request = UART4_TX_DMA_REQUEST, \
.channel = UART4_TX_DMA_CHANNEL, \
}
#endif /* UART4_DMA_TX_CONFIG */
#else
#error "The DMA resource is not available."
#endif /* UART4_TX_DMA */
#endif /* BSP_UART4_TX_USING_DMA */
#if defined(BSP_USING_UART5)
#ifndef UART5_CONFIG
#define UART5_CONFIG \
{ \
.name = "uart5", \
.Instance = UART5, \
.irq_type = UART5_IRQn, \
.periph = RCC_APB1_PERIPHEN_UART5, \
.EnablePeriphClk = RCC_EnableAPB1PeriphClk, \
}
#endif /* UART5_CONFIG */
#endif /* BSP_USING_UART5 */
#if defined(BSP_UART5_RX_USING_DMA)
#if defined(UART5_RX_DMA)
#ifndef UART5_DMA_RX_CONFIG
#define UART5_DMA_RX_CONFIG \
{ \
.DMAy = UART5_RX_DMA, \
.DMAChx = UART5_RX_DMA_CHType, \
.dma_irq = UART5_RX_DMA_IRQ, \
.dma_rcc = UART5_RX_DMA_RCC, \
.request = UART5_RX_DMA_REQUEST, \
.channel = UART5_RX_DMA_CHANNEL, \
}
#endif /* UART5_DMA_RX_CONFIG */
#else
#error "The DMA resource is not available."
#endif /* UART5_RX_DMA */
#endif /* BSP_UART5_RX_USING_DMA */
#if defined(BSP_UART5_TX_USING_DMA)
#if defined(UART5_TX_DMA)
#ifndef UART5_DMA_TX_CONFIG
#define UART5_DMA_TX_CONFIG \
{ \
.DMAy = UART5_TX_DMA, \
.DMAChx = UART5_TX_DMA_CHType, \
.dma_irq = UART5_TX_DMA_IRQ, \
.dma_rcc = UART5_TX_DMA_RCC, \
.request = UART5_TX_DMA_REQUEST, \
.channel = UART5_TX_DMA_CHANNEL, \
}
#endif /* UART5_DMA_TX_CONFIG */
#else
#error "The DMA resource is not available."
#endif /* UART5_TX_DMA */
#endif /* BSP_UART5_TX_USING_DMA */
#if defined(BSP_USING_UART6)
#ifndef UART6_CONFIG
#define UART6_CONFIG \
{ \
.name = "uart6", \
.Instance = UART6, \
.irq_type = UART6_IRQn, \
.periph = RCC_APB2_PERIPHEN_UART6, \
.EnablePeriphClk = RCC_EnableAPB2PeriphClk, \
}
#endif /* UART6_CONFIG */
#endif /* BSP_USING_UART6 */
#if defined(BSP_UART6_RX_USING_DMA)
#if defined(UART6_RX_DMA)
#ifndef UART6_DMA_RX_CONFIG
#define UART6_DMA_RX_CONFIG \
{ \
.DMAy = UART6_RX_DMA, \
.DMAChx = UART6_RX_DMA_CHType, \
.dma_irq = UART6_RX_DMA_IRQ, \
.dma_rcc = UART6_RX_DMA_RCC, \
.request = UART6_RX_DMA_REQUEST, \
.channel = UART6_RX_DMA_CHANNEL, \
}
#endif /* UART6_DMA_RX_CONFIG */
#else
#error "The DMA resource is not available."
#endif /* UART6_RX_DMA */
#endif /* BSP_UART6_RX_USING_DMA */
#if defined(BSP_UART6_TX_USING_DMA)
#if defined(UART6_TX_DMA)
#ifndef UART6_DMA_TX_CONFIG
#define UART6_DMA_TX_CONFIG \
{ \
.DMAy = UART6_TX_DMA, \
.DMAChx = UART6_TX_DMA_CHType, \
.dma_irq = UART6_TX_DMA_IRQ, \
.dma_rcc = UART6_TX_DMA_RCC, \
.request = UART6_TX_DMA_REQUEST, \
.channel = UART6_TX_DMA_CHANNEL, \
}
#endif /* UART6_DMA_TX_CONFIG */
#else
#error "The DMA resource is not available."
#endif /* UART6_TX_DMA */
#endif /* BSP_UART6_TX_USING_DMA */
#if defined(BSP_USING_UART7)
#ifndef UART7_CONFIG
#define UART7_CONFIG \
{ \
.name = "uart7", \
.Instance = UART7, \
.irq_type = UART7_IRQn, \
.periph = RCC_APB2_PERIPHEN_UART7, \
.EnablePeriphClk = RCC_EnableAPB2PeriphClk, \
}
#endif /* UART7_CONFIG */
#endif /* BSP_USING_UART7 */
#if defined(BSP_UART7_RX_USING_DMA)
#if defined(UART7_RX_DMA)
#ifndef UART7_DMA_RX_CONFIG
#define UART7_DMA_RX_CONFIG \
{ \
.DMAy = UART7_RX_DMA, \
.DMAChx = UART7_RX_DMA_CHType, \
.dma_irq = UART7_RX_DMA_IRQ, \
.dma_rcc = UART7_RX_DMA_RCC, \
.request = UART7_RX_DMA_REQUEST, \
.channel = UART7_RX_DMA_CHANNEL, \
}
#endif /* UART7_DMA_RX_CONFIG */
#else
#error "The DMA resource is not available."
#endif /* UART7_RX_DMA */
#endif /* BSP_UART7_RX_USING_DMA */
#if defined(BSP_UART7_TX_USING_DMA)
#if defined(UART7_TX_DMA)
#ifndef UART7_DMA_TX_CONFIG
#define UART7_DMA_TX_CONFIG \
{ \
.DMAy = UART7_TX_DMA, \
.DMAChx = UART7_TX_DMA_CHType, \
.dma_irq = UART7_TX_DMA_IRQ, \
.dma_rcc = UART7_TX_DMA_RCC, \
.request = UART7_TX_DMA_REQUEST, \
.channel = UART7_TX_DMA_CHANNEL, \
}
#endif /* UART7_DMA_TX_CONFIG */
#else
#error "The DMA resource is not available."
#endif /* UART7_TX_DMA */
#endif /* BSP_UART7_TX_USING_DMA */
#if defined(BSP_USING_UART8)
#ifndef UART8_CONFIG
#define UART8_CONFIG \
{ \
.name = "uart8", \
.Instance = UART8, \
.irq_type = UART8_IRQn, \
.periph = RCC_APB1_PERIPHEN_UART8, \
.EnablePeriphClk = RCC_EnableAPB1PeriphClk, \
}
#endif /* UART8_CONFIG */
#endif /* BSP_USING_UART8 */
#if defined(BSP_UART8_RX_USING_DMA)
#if defined(UART8_RX_DMA)
#ifndef UART8_DMA_RX_CONFIG
#define UART8_DMA_RX_CONFIG \
{ \
.DMAy = UART8_RX_DMA, \
.DMAChx = UART8_RX_DMA_CHType, \
.dma_irq = UART8_RX_DMA_IRQ, \
.dma_rcc = UART8_RX_DMA_RCC, \
.request = UART8_RX_DMA_REQUEST, \
.channel = UART8_RX_DMA_CHANNEL, \
}
#endif /* UART8_DMA_RX_CONFIG */
#else
#error "The DMA resource is not available."
#endif /* UART8_RX_DMA */
#endif /* BSP_UART8_RX_USING_DMA */
#if defined(BSP_UART8_TX_USING_DMA)
#if defined(UART8_TX_DMA)
#ifndef UART8_DMA_TX_CONFIG
#define UART8_DMA_TX_CONFIG \
{ \
.DMAy = UART8_TX_DMA, \
.DMAChx = UART8_TX_DMA_CHType, \
.dma_irq = UART8_TX_DMA_IRQ, \
.dma_rcc = UART8_TX_DMA_RCC, \
.request = UART8_TX_DMA_REQUEST, \
.channel = UART8_TX_DMA_CHANNEL, \
}
#endif /* UART8_DMA_TX_CONFIG */
#else
#error "The DMA resource is not available."
#endif /* UART8_TX_DMA */
#endif /* BSP_UART8_TX_USING_DMA */
#if defined(BSP_USING_UART9)
#ifndef UART9_CONFIG
#define UART9_CONFIG \
{ \
.name = "uart9", \
.Instance = USART9, \
.irq_type = USART9_IRQn, \
.periph = RCC_APB2_PERIPHEN_USART9, \
.EnablePeriphClk = RCC_EnableAPB2PeriphClk, \
}
#endif /* UART9_CONFIG */
#endif /* BSP_USING_UART9 */
#if defined(BSP_UART9_RX_USING_DMA)
#if defined(UART9_RX_DMA)
#ifndef UART9_DMA_RX_CONFIG
#define UART9_DMA_RX_CONFIG \
{ \
.DMAy = UART9_RX_DMA, \
.DMAChx = UART9_RX_DMA_CHType, \
.dma_irq = UART9_RX_DMA_IRQ, \
.dma_rcc = UART9_RX_DMA_RCC, \
.request = UART9_RX_DMA_REQUEST, \
.channel = UART9_RX_DMA_CHANNEL, \
}
#endif /* UART9_DMA_RX_CONFIG */
#else
#error "The DMA resource is not available."
#endif /* UART9_RX_DMA */
#endif /* BSP_UART9_RX_USING_DMA */
#if defined(BSP_UART9_TX_USING_DMA)
#if defined(UART9_TX_DMA)
#ifndef UART9_DMA_TX_CONFIG
#define UART9_DMA_TX_CONFIG \
{ \
.DMAy = UART9_TX_DMA, \
.DMAChx = UART9_TX_DMA_CHType, \
.dma_irq = UART9_TX_DMA_IRQ, \
.dma_rcc = UART9_TX_DMA_RCC, \
.request = UART9_TX_DMA_REQUEST, \
.channel = UART9_TX_DMA_CHANNEL, \
}
#endif /* UART9_DMA_TX_CONFIG */
#else
#error "The DMA resource is not available."
#endif /* UART9_TX_DMA */
#endif /* BSP_UART9_TX_USING_DMA */
#if defined(BSP_USING_UART10)
#ifndef UART10_CONFIG
#define UART10_CONFIG \
{ \
.name = "uart10", \
.Instance = URT10, \
.irq_type = UART10_IRQn, \
.periph = RCC_APB2_PERIPHEN_UART10, \
.EnablePeriphClk = RCC_EnableAPB2PeriphClk, \
}
#endif /* UART10_CONFIG */
#endif /* BSP_USING_UART10 */
#if defined(BSP_UART10_RX_USING_DMA)
#if defined(UART10_RX_DMA)
#ifndef UART10_DMA_RX_CONFIG
#define UART10_DMA_RX_CONFIG \
{ \
.DMAy = UART10_RX_DMA, \
.DMAChx = UART10_RX_DMA_CHType, \
.dma_irq = UART10_RX_DMA_IRQ, \
.dma_rcc = UART10_RX_DMA_RCC, \
.request = UART10_RX_DMA_REQUEST, \
.channel = UART10_RX_DMA_CHANNEL, \
}
#endif /* UART10_DMA_RX_CONFIG */
#else
#error "The DMA resource is not available."
#endif /* UART10_RX_DMA */
#endif /* BSP_UART10_RX_USING_DMA */
#if defined(BSP_UART10_TX_USING_DMA)
#if defined(UART10_TX_DMA)
#ifndef UART10_DMA_TX_CONFIG
#define UART10_DMA_TX_CONFIG \
{ \
.DMAy = UART10_TX_DMA, \
.DMAChx = UART10_TX_DMA_CHType, \
.dma_irq = UART10_TX_DMA_IRQ, \
.dma_rcc = UART10_TX_DMA_RCC, \
.request = UART10_TX_DMA_REQUEST, \
.channel = UART10_TX_DMA_CHANNEL, \
}
#endif /* UART10_DMA_TX_CONFIG */
#else
#error "The DMA resource is not available."
#endif /* UART10_TX_DMA */
#endif /* BSP_UART10_TX_USING_DMA */
#ifdef __cplusplus
}
#endif
#endif /* __UART_CONFIG_H__ */

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bsp/n32/n32hxxx/libraries/N32_Drivers/drivers/config/h7/dma_config.h
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@ -1,710 +0,0 @@
/*
* Copyright (c) 2006-2025, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2026-01-24 ox-horse first version
*/
#ifndef __DMA_CONFIG_H__
#define __DMA_CONFIG_H__
#include <rtthread.h>
#ifdef __cplusplus
extern "C" {
#endif
/* DMAMUX1 channel0 / DMA1 channel0 */
#if defined(BSP_UART1_RX_USING_DMA) && !defined(UART1_RX_DMA_INSTANCE)
#define UART1_RX_DMA_INSTANCE DMA1
#define UART1_RX_DMA_IRQHandler DMA1_Channel0_IRQHandler
#define UART1_RX_DMA_IRQ DMA1_Channel0_IRQn
#define UART1_RX_DMA_HANDSHAK DMA_CH_HARDWARE_HANDSHAKING_IF_0
#define UART1_RX_DMA_DMA_RCC RCC_AHB1_PERIPHEN_M7_DMA1
#define UART1_RX_DMA_DMA_CHANNEL DMA_CHANNEL_0
#define UART1_RX_DMA_DMAMUX_CHANNEL DMAMUX_CHANNEL_0
#define UART1_RX_DMA_DMAMUX_REQUEST DMAMUX1_REQUEST_USART1_RX
#elif defined(BSP_UART8_TX_USING_DMA) && !defined(UART8_TX_DMA_INSTANCE)
#define UART8_TX_DMA_INSTANCE DMA1
#define UART8_TX_DMA_IRQHandler DMA1_Channel0_IRQHandler
#define UART8_TX_DMA_IRQ DMA1_Channel0_IRQn
#define UART8_TX_DMA_HANDSHAK DMA_CH_HARDWARE_HANDSHAKING_IF_0
#define UART8_TX_DMA_DMA_RCC RCC_AHB1_PERIPHEN_M7_DMA1
#define UART8_TX_DMA_DMA_CHANNEL DMA_CHANNEL_0
#define UART8_TX_DMA_DMAMUX_CHANNEL DMAMUX_CHANNEL_0
#define UART8_TX_DMA_DMAMUX_REQUEST DMAMUX1_REQUEST_USART8_TX
#elif defined(BSP_I2C5_TX_USING_DMA) && !defined(I2C5_TX_DMA_INSTANCE)
#define I2C5_TX_DMA_INSTANCE DMA1
#define I2C5_TX_DMA_IRQHandler DMA1_Channel0_IRQHandler
#define I2C5_TX_DMA_IRQ DMA1_Channel0_IRQn
#define I2C5_TX_DMA_HANDSHAK DMA_CH_HARDWARE_HANDSHAKING_IF_0
#define I2C5_TX_DMA_DMA_RCC RCC_AHB1_PERIPHEN_M7_DMA1
#define I2C5_TX_DMA_DMA_CHANNEL DMA_CHANNEL_0
#define I2C5_TX_DMA_DMAMUX_CHANNEL DMAMUX_CHANNEL_0
#define I2C5_TX_DMA_DMAMUX_REQUEST DMAMUX1_REQUEST_I2C5_TX
#endif
/* DMAMUX1 channel1 / DMA1 channel1 */
#if defined(BSP_UART2_RX_USING_DMA) && !defined(UART2_RX_DMA_INSTANCE)
#define UART2_RX_DMA_INSTANCE DMA1
#define UART2_RX_DMA_IRQHandler DMA1_Channel1_IRQHandler
#define UART2_RX_DMA_IRQ DMA1_Channel1_IRQn
#define UART2_RX_DMA_HANDSHAK DMA_CH_HARDWARE_HANDSHAKING_IF_1
#define UART2_RX_DMA_DMA_RCC RCC_AHB1_PERIPHEN_M7_DMA1
#define UART2_RX_DMA_DMA_CHANNEL DMA_CHANNEL_1
#define UART2_RX_DMA_DMAMUX_CHANNEL DMAMUX_CHANNEL_1
#define UART2_RX_DMA_DMAMUX_REQUEST DMAMUX1_REQUEST_USART2_RX
#elif defined(BSP_UART9_TX_USING_DMA) && !defined(UART9_TX_DMA_INSTANCE)
#define UART9_TX_DMA_INSTANCE DMA1
#define UART9_TX_DMA_IRQHandler DMA1_Channel1_IRQHandler
#define UART9_TX_DMA_IRQ DMA1_Channel1_IRQn
#define UART9_TX_DMA_HANDSHAK DMA_CH_HARDWARE_HANDSHAKING_IF_1
#define UART9_TX_DMA_DMA_RCC RCC_AHB1_PERIPHEN_M7_DMA1
#define UART9_TX_DMA_DMA_CHANNEL DMA_CHANNEL_1
#define UART9_TX_DMA_DMAMUX_CHANNEL DMAMUX_CHANNEL_1
#define UART9_TX_DMA_DMAMUX_REQUEST DMAMUX1_REQUEST_UART9_TX
#elif defined(BSP_I2C6_TX_USING_DMA) && !defined(I2C6_TX_DMA_INSTANCE)
#define I2C6_TX_DMA_INSTANCE DMA1
#define I2C6_TX_DMA_IRQHandler DMA1_Channel1_IRQHandler
#define I2C6_TX_DMA_IRQ DMA1_Channel1_IRQn
#define I2C6_TX_DMA_HANDSHAK DMA_CH_HARDWARE_HANDSHAKING_IF_1
#define I2C6_TX_DMA_DMA_RCC RCC_AHB1_PERIPHEN_M7_DMA1
#define I2C6_TX_DMA_DMA_CHANNEL DMA_CHANNEL_1
#define I2C6_TX_DMA_DMAMUX_CHANNEL DMAMUX_CHANNEL_1
#define I2C6_TX_DMA_DMAMUX_REQUEST DMAMUX1_REQUEST_I2C6_TX
#endif
/* DMAMUX1 channel2 / DMA1 channel2 */
#if defined(BSP_UART3_RX_USING_DMA) && !defined(UART3_RX_DMA_INSTANCE)
#define UART3_RX_DMA_INSTANCE DMA1
#define UART3_RX_DMA_IRQHandler DMA1_Channel2_IRQHandler
#define UART3_RX_DMA_IRQ DMA1_Channel2_IRQn
#define UART3_RX_DMA_HANDSHAK DMA_CH_HARDWARE_HANDSHAKING_IF_2
#define UART3_RX_DMA_DMA_RCC RCC_AHB1_PERIPHEN_M7_DMA1
#define UART3_RX_DMA_DMA_CHANNEL DMA_CHANNEL_2
#define UART3_RX_DMA_DMAMUX_CHANNEL DMAMUX_CHANNEL_2
#define UART3_RX_DMA_DMAMUX_REQUEST DMAMUX1_REQUEST_USART3_RX
#elif defined(BSP_UART10_TX_USING_DMA) && !defined(UART10_TX_DMA_INSTANCE)
#define UART10_TX_DMA_INSTANCE DMA1
#define UART10_TX_DMA_IRQHandler DMA1_Channel2_IRQHandler
#define UART10_TX_DMA_IRQ DMA1_Channel2_IRQn
#define UART10_TX_DMA_HANDSHAK DMA_CH_HARDWARE_HANDSHAKING_IF_2
#define UART10_TX_DMA_DMA_RCC RCC_AHB1_PERIPHEN_M7_DMA1
#define UART10_TX_DMA_DMA_CHANNEL DMA_CHANNEL_2
#define UART10_TX_DMA_DMAMUX_CHANNEL DMAMUX_CHANNEL_2
#define UART10_TX_DMA_DMAMUX_REQUEST DMAMUX1_REQUEST_UART10_TX
#elif defined(BSP_I2C7_TX_USING_DMA) && !defined(I2C7_TX_DMA_INSTANCE)
#define I2C7_TX_DMA_INSTANCE DMA1
#define I2C7_TX_DMA_IRQHandler DMA1_Channel2_IRQHandler
#define I2C7_TX_DMA_IRQ DMA1_Channel2_IRQn
#define I2C7_TX_DMA_HANDSHAK DMA_CH_HARDWARE_HANDSHAKING_IF_2
#define I2C7_TX_DMA_DMA_RCC RCC_AHB1_PERIPHEN_M7_DMA1
#define I2C7_TX_DMA_DMA_CHANNEL DMA_CHANNEL_2
#define I2C7_TX_DMA_DMAMUX_CHANNEL DMAMUX_CHANNEL_2
#define I2C7_TX_DMA_DMAMUX_REQUEST DMAMUX1_REQUEST_I2C7_TX
#endif
/* DMAMUX1 channel3 / DMA1 channel3 */
#if defined(BSP_UART4_RX_USING_DMA) && !defined(UART4_RX_DMA_INSTANCE)
#define UART4_RX_DMA_INSTANCE DMA1
#define UART4_RX_DMA_IRQHandler DMA1_Channel3_IRQHandler
#define UART4_RX_DMA_IRQ DMA1_Channel3_IRQn
#define UART4_RX_DMA_HANDSHAK DMA_CH_HARDWARE_HANDSHAKING_IF_3
#define UART4_RX_DMA_DMA_RCC RCC_AHB1_PERIPHEN_M7_DMA1
#define UART4_RX_DMA_DMA_CHANNEL DMA_CHANNEL_3
#define UART4_RX_DMA_DMAMUX_CHANNEL DMAMUX_CHANNEL_3
#define UART4_RX_DMA_DMAMUX_REQUEST DMAMUX1_REQUEST_USART4_RX
#elif defined(BSP_UART11_TX_USING_DMA) && !defined(UART11_TX_DMA_INSTANCE)
#define UART11_TX_DMA_INSTANCE DMA1
#define UART11_TX_DMA_IRQHandler DMA1_Channel3_IRQHandler
#define UART11_TX_DMA_IRQ DMA1_Channel3_IRQn
#define UART11_TX_DMA_HANDSHAK DMA_CH_HARDWARE_HANDSHAKING_IF_3
#define UART11_TX_DMA_DMA_RCC RCC_AHB1_PERIPHEN_M7_DMA1
#define UART11_TX_DMA_DMA_CHANNEL DMA_CHANNEL_3
#define UART11_TX_DMA_DMAMUX_CHANNEL DMAMUX_CHANNEL_3
#define UART11_TX_DMA_DMAMUX_REQUEST DMAMUX1_REQUEST_UART11_TX
#elif defined(BSP_I2C8_TX_USING_DMA) && !defined(I2C8_TX_DMA_INSTANCE)
#define I2C8_TX_DMA_INSTANCE DMA1
#define I2C8_TX_DMA_IRQHandler DMA1_Channel3_IRQHandler
#define I2C8_TX_DMA_IRQ DMA1_Channel3_IRQn
#define I2C8_TX_DMA_HANDSHAK DMA_CH_HARDWARE_HANDSHAKING_IF_3
#define I2C8_TX_DMA_DMA_RCC RCC_AHB1_PERIPHEN_M7_DMA1
#define I2C8_TX_DMA_DMA_CHANNEL DMA_CHANNEL_3
#define I2C8_TX_DMA_DMAMUX_CHANNEL DMAMUX_CHANNEL_3
#define I2C8_TX_DMA_DMAMUX_REQUEST DMAMUX1_REQUEST_I2C8_TX
#endif
/* DMAMUX1 channel4 / DMA1 channel4 */
#if defined(BSP_UART5_RX_USING_DMA) && !defined(UART5_RX_DMA_INSTANCE)
#define UART5_RX_DMA_INSTANCE DMA1
#define UART5_RX_DMA_IRQHandler DMA1_Channel4_IRQHandler
#define UART5_RX_DMA_IRQ DMA1_Channel4_IRQn
#define UART5_RX_DMA_HANDSHAK DMA_CH_HARDWARE_HANDSHAKING_IF_4
#define UART5_RX_DMA_DMA_RCC RCC_AHB1_PERIPHEN_M7_DMA1
#define UART5_RX_DMA_DMA_CHANNEL DMA_CHANNEL_4
#define UART5_RX_DMA_DMAMUX_CHANNEL DMAMUX_CHANNEL_4
#define UART5_RX_DMA_DMAMUX_REQUEST DMAMUX1_REQUEST_USART5_RX
#elif defined(BSP_UART12_TX_USING_DMA) && !defined(UART12_TX_DMA_INSTANCE)
#define UART12_TX_DMA_INSTANCE DMA1
#define UART12_TX_DMA_IRQHandler DMA1_Channel4_IRQHandler
#define UART12_TX_DMA_IRQ DMA1_Channel4_IRQn
#define UART12_TX_DMA_HANDSHAK DMA_CH_HARDWARE_HANDSHAKING_IF_4
#define UART12_TX_DMA_DMA_RCC RCC_AHB1_PERIPHEN_M7_DMA1
#define UART12_TX_DMA_DMA_CHANNEL DMA_CHANNEL_4
#define UART12_TX_DMA_DMAMUX_CHANNEL DMAMUX_CHANNEL_4
#define UART12_TX_DMA_DMAMUX_REQUEST DMAMUX1_REQUEST_UART12_TX
#elif defined(BSP_I2C9_TX_USING_DMA) && !defined(I2C9_TX_DMA_INSTANCE)
#define I2C9_TX_DMA_INSTANCE DMA1
#define I2C9_TX_DMA_IRQHandler DMA1_Channel4_IRQHandler
#define I2C9_TX_DMA_IRQ DMA1_Channel4_IRQn
#define I2C9_TX_DMA_HANDSHAK DMA_CH_HARDWARE_HANDSHAKING_IF_4
#define I2C9_TX_DMA_DMA_RCC RCC_AHB1_PERIPHEN_M7_DMA1
#define I2C9_TX_DMA_DMA_CHANNEL DMA_CHANNEL_4
#define I2C9_TX_DMA_DMAMUX_CHANNEL DMAMUX_CHANNEL_4
#define I2C9_TX_DMA_DMAMUX_REQUEST DMAMUX1_REQUEST_I2C9_TX
#endif
/* DMAMUX1 channel5 / DMA1 channel5 */
#if defined(BSP_UART6_RX_USING_DMA) && !defined(UART6_RX_DMA_INSTANCE)
#define UART6_RX_DMA_INSTANCE DMA1
#define UART6_RX_DMA_IRQHandler DMA1_Channel5_IRQHandler
#define UART6_RX_DMA_IRQ DMA1_Channel5_IRQn
#define UART6_RX_DMA_HANDSHAK DMA_CH_HARDWARE_HANDSHAKING_IF_5
#define UART6_RX_DMA_DMA_RCC RCC_AHB1_PERIPHEN_M7_DMA1
#define UART6_RX_DMA_DMA_CHANNEL DMA_CHANNEL_5
#define UART6_RX_DMA_DMAMUX_CHANNEL DMAMUX_CHANNEL_5
#define UART6_RX_DMA_DMAMUX_REQUEST DMAMUX1_REQUEST_USART6_RX
#elif defined(BSP_UART13_TX_USING_DMA) && !defined(UART13_TX_DMA_INSTANCE)
#define UART13_TX_DMA_INSTANCE DMA1
#define UART13_TX_DMA_IRQHandler DMA1_Channel5_IRQHandler
#define UART13_TX_DMA_IRQ DMA1_Channel5_IRQn
#define UART13_TX_DMA_HANDSHAK DMA_CH_HARDWARE_HANDSHAKING_IF_5
#define UART13_TX_DMA_DMA_RCC RCC_AHB1_PERIPHEN_M7_DMA1
#define UART13_TX_DMA_DMA_CHANNEL DMA_CHANNEL_5
#define UART13_TX_DMA_DMAMUX_CHANNEL DMAMUX_CHANNEL_5
#define UART13_TX_DMA_DMAMUX_REQUEST DMAMUX1_REQUEST_UART13_TX
#elif defined(BSP_I2C10_TX_USING_DMA) && !defined(I2C10_TX_DMA_INSTANCE)
#define I2C10_TX_DMA_INSTANCE DMA1
#define I2C10_TX_DMA_IRQHandler DMA1_Channel5_IRQHandler
#define I2C10_TX_DMA_IRQ DMA1_Channel5_IRQn
#define I2C10_TX_DMA_HANDSHAK DMA_CH_HARDWARE_HANDSHAKING_IF_5
#define I2C10_TX_DMA_DMA_RCC RCC_AHB1_PERIPHEN_M7_DMA1
#define I2C10_TX_DMA_DMA_CHANNEL DMA_CHANNEL_5
#define I2C10_TX_DMA_DMAMUX_CHANNEL DMAMUX_CHANNEL_5
#define I2C10_TX_DMA_DMAMUX_REQUEST DMAMUX1_REQUEST_I2C10_TX
#endif
/* DMAMUX1 channel6 / DMA1 channel6 */
#if defined(BSP_UART7_RX_USING_DMA) && !defined(UART7_RX_DMA_INSTANCE)
#define UART7_RX_DMA_INSTANCE DMA1
#define UART7_RX_DMA_IRQHandler DMA1_Channel6_IRQHandler
#define UART7_RX_DMA_IRQ DMA1_Channel6_IRQn
#define UART7_RX_DMA_HANDSHAK DMA_CH_HARDWARE_HANDSHAKING_IF_6
#define UART7_RX_DMA_DMA_RCC RCC_AHB1_PERIPHEN_M7_DMA1
#define UART7_RX_DMA_DMA_CHANNEL DMA_CHANNEL_6
#define UART7_RX_DMA_DMAMUX_CHANNEL DMAMUX_CHANNEL_6
#define UART7_RX_DMA_DMAMUX_REQUEST DMAMUX1_REQUEST_USART7_RX
#elif defined(BSP_UART14_TX_USING_DMA) && !defined(UART14_TX_DMA_INSTANCE)
#define UART14_TX_DMA_INSTANCE DMA1
#define UART14_TX_DMA_IRQHandler DMA1_Channel6_IRQHandler
#define UART14_TX_DMA_IRQ DMA1_Channel6_IRQn
#define UART14_TX_DMA_HANDSHAK DMA_CH_HARDWARE_HANDSHAKING_IF_6
#define UART14_TX_DMA_DMA_RCC RCC_AHB1_PERIPHEN_M7_DMA1
#define UART14_TX_DMA_DMA_CHANNEL DMA_CHANNEL_6
#define UART14_TX_DMA_DMAMUX_CHANNEL DMAMUX_CHANNEL_6
#define UART14_TX_DMA_DMAMUX_REQUEST DMAMUX1_REQUEST_UART14_TX
#elif defined(BSP_SPI1_TX_USING_DMA) && !defined(SPI1_TX_DMA_INSTANCE)
#define SPI1_TX_DMA_INSTANCE DMA1
#define SPI1_TX_DMA_IRQHandler DMA1_Channel6_IRQHandler
#define SPI1_TX_DMA_IRQ DMA1_Channel6_IRQn
#define SPI1_TX_DMA_HANDSHAK DMA_CH_HARDWARE_HANDSHAKING_IF_6
#define SPI1_TX_DMA_DMA_RCC RCC_AHB1_PERIPHEN_M7_DMA1
#define SPI1_TX_DMA_DMA_CHANNEL DMA_CHANNEL_6
#define SPI1_TX_DMA_DMAMUX_CHANNEL DMAMUX_CHANNEL_6
#define SPI1_TX_DMA_DMAMUX_REQUEST DMAMUX1_REQUEST_SPI1_TX
#endif
/* DMAMUX1 channel7 / DMA1 channel7 */
#if defined(BSP_UART8_RX_USING_DMA) && !defined(UART8_RX_DMA_INSTANCE)
#define UART8_RX_DMA_INSTANCE DMA1
#define UART8_RX_DMA_IRQHandler DMA1_Channel7_IRQHandler
#define UART8_RX_DMA_IRQ DMA1_Channel7_IRQn
#define UART8_RX_DMA_HANDSHAK DMA_CH_HARDWARE_HANDSHAKING_IF_7
#define UART8_RX_DMA_DMA_RCC RCC_AHB1_PERIPHEN_M7_DMA1
#define UART8_RX_DMA_DMA_CHANNEL DMA_CHANNEL_7
#define UART8_RX_DMA_DMAMUX_CHANNEL DMAMUX_CHANNEL_7
#define UART8_RX_DMA_DMAMUX_REQUEST DMAMUX1_REQUEST_USART8_RX
#elif defined(BSP_UART15_TX_USING_DMA) && !defined(UART15_TX_DMA_INSTANCE)
#define UART15_TX_DMA_INSTANCE DMA1
#define UART15_TX_DMA_IRQHandler DMA1_Channel7_IRQHandler
#define UART15_TX_DMA_IRQ DMA1_Channel7_IRQn
#define UART15_TX_DMA_HANDSHAK DMA_CH_HARDWARE_HANDSHAKING_IF_7
#define UART15_TX_DMA_DMA_RCC RCC_AHB1_PERIPHEN_M7_DMA1
#define UART15_TX_DMA_DMA_CHANNEL DMA_CHANNEL_7
#define UART15_TX_DMA_DMAMUX_CHANNEL DMAMUX_CHANNEL_7
#define UART15_TX_DMA_DMAMUX_REQUEST DMAMUX1_REQUEST_UART15_TX
#elif defined(BSP_SPI2_TX_USING_DMA) && !defined(SPI2_TX_DMA_INSTANCE)
#define SPI2_TX_DMA_INSTANCE DMA1
#define SPI2_TX_DMA_IRQHandler DMA1_Channel7_IRQHandler
#define SPI2_TX_DMA_IRQ DMA1_Channel7_IRQn
#define SPI2_TX_DMA_HANDSHAK DMA_CH_HARDWARE_HANDSHAKING_IF_7
#define SPI2_TX_DMA_DMA_RCC RCC_AHB1_PERIPHEN_M7_DMA1
#define SPI2_TX_DMA_DMA_CHANNEL DMA_CHANNEL_7
#define SPI2_TX_DMA_DMAMUX_CHANNEL DMAMUX_CHANNEL_7
#define SPI2_TX_DMA_DMAMUX_REQUEST DMAMUX1_REQUEST_SPI2_TX
#endif
/* DMAMUX1 channel8 / DMA2 channel0 */
#if defined(BSP_UART9_RX_USING_DMA) && !defined(UART9_RX_DMA_INSTANCE)
#define UART9_RX_DMA_INSTANCE DMA2
#define UART9_RX_DMA_IRQHandler DMA2_Channel0_IRQHandler
#define UART9_RX_DMA_IRQ DMA2_Channel0_IRQn
#define UART9_RX_DMA_HANDSHAK DMA_CH_HARDWARE_HANDSHAKING_IF_0
#define UART9_RX_DMA_DMA_RCC RCC_AHB1_PERIPHEN_M7_DMA2
#define UART9_RX_DMA_DMA_CHANNEL DMA_CHANNEL_0
#define UART9_RX_DMA_DMAMUX_CHANNEL DMAMUX_CHANNEL_8
#define UART9_RX_DMA_DMAMUX_REQUEST DMAMUX1_REQUEST_UART9_RX
#elif defined(BSP_LPUART1_TX_USING_DMA) && !defined(LPUART1_TX_DMA_INSTANCE)
#define LPUART1_TX_DMA_INSTANCE DMA2
#define LPUART1_TX_DMA_IRQHandler DMA2_Channel0_IRQHandler
#define LPUART1_TX_DMA_IRQ DMA2_Channel0_IRQn
#define LPUART1_TX_DMA_HANDSHAK DMA_CH_HARDWARE_HANDSHAKING_IF_0
#define LPUART1_TX_DMA_DMA_RCC RCC_AHB1_PERIPHEN_M7_DMA2
#define LPUART1_TX_DMA_DMA_CHANNEL DMA_CHANNEL_0
#define LPUART1_TX_DMA_DMAMUX_CHANNEL DMAMUX_CHANNEL_8
#define LPUART1_TX_DMA_DMAMUX_REQUEST DMAMUX1_REQUEST_LPUART1_TX
#elif defined(BSP_SPI3_TX_USING_DMA) && !defined(SPI3_TX_DMA_INSTANCE)
#define SPI3_TX_DMA_INSTANCE DMA2
#define SPI3_TX_DMA_IRQHandler DMA2_Channel0_IRQHandler
#define SPI3_TX_DMA_IRQ DMA2_Channel0_IRQn
#define SPI3_TX_DMA_HANDSHAK DMA_CH_HARDWARE_HANDSHAKING_IF_0
#define SPI3_TX_DMA_DMA_RCC RCC_AHB1_PERIPHEN_M7_DMA2
#define SPI3_TX_DMA_DMA_CHANNEL DMA_CHANNEL_0
#define SPI3_TX_DMA_DMAMUX_CHANNEL DMAMUX_CHANNEL_8
#define SPI3_TX_DMA_DMAMUX_REQUEST DMAMUX1_REQUEST_SPI3_TX
#endif
/* DMAMUX1 channel9 / DMA2 channel1 */
#if defined(BSP_UART10_RX_USING_DMA) && !defined(UART10_RX_DMA_INSTANCE)
#define UART10_RX_DMA_INSTANCE DMA2
#define UART10_RX_DMA_IRQHandler DMA2_Channel1_IRQHandler
#define UART10_RX_DMA_IRQ DMA2_Channel1_IRQn
#define UART10_RX_DMA_HANDSHAK DMA_CH_HARDWARE_HANDSHAKING_IF_1
#define UART10_RX_DMA_DMA_RCC RCC_AHB1_PERIPHEN_M7_DMA2
#define UART10_RX_DMA_DMA_CHANNEL DMA_CHANNEL_1
#define UART10_RX_DMA_DMAMUX_CHANNEL DMAMUX_CHANNEL_9
#define UART10_RX_DMA_DMAMUX_REQUEST DMAMUX1_REQUEST_UART10_RX
#elif defined(BSP_LPUART2_TX_USING_DMA) && !defined(LPUART2_TX_DMA_INSTANCE)
#define LPUART2_TX_DMA_INSTANCE DMA2
#define LPUART2_TX_DMA_IRQHandler DMA2_Channel1_IRQHandler
#define LPUART2_TX_DMA_IRQ DMA2_Channel1_IRQn
#define LPUART2_TX_DMA_HANDSHAK DMA_CH_HARDWARE_HANDSHAKING_IF_1
#define LPUART2_TX_DMA_DMA_RCC RCC_AHB1_PERIPHEN_M7_DMA2
#define LPUART2_TX_DMA_DMA_CHANNEL DMA_CHANNEL_1
#define LPUART2_TX_DMA_DMAMUX_CHANNEL DMAMUX_CHANNEL_9
#define LPUART2_TX_DMA_DMAMUX_REQUEST DMAMUX1_REQUEST_LPUART2_TX
#elif defined(BSP_SPI4_TX_USING_DMA) && !defined(SPI4_TX_DMA_INSTANCE)
#define SPI4_TX_DMA_INSTANCE DMA2
#define SPI4_TX_DMA_IRQHandler DMA2_Channel1_IRQHandler
#define SPI4_TX_DMA_IRQ DMA2_Channel1_IRQn
#define SPI4_TX_DMA_HANDSHAK DMA_CH_HARDWARE_HANDSHAKING_IF_1
#define SPI4_TX_DMA_DMA_RCC RCC_AHB1_PERIPHEN_M7_DMA2
#define SPI4_TX_DMA_DMA_CHANNEL DMA_CHANNEL_1
#define SPI4_TX_DMA_DMAMUX_CHANNEL DMAMUX_CHANNEL_9
#define SPI4_TX_DMA_DMAMUX_REQUEST DMAMUX1_REQUEST_SPI4_TX
#endif
/* DMAMUX1 channel10 / DMA2 channel2 */
#if defined(BSP_I2C1_RX_USING_DMA) && !defined(I2C1_RX_DMA_INSTANCE)
#define I2C1_RX_DMA_INSTANCE DMA2
#define I2C1_RX_DMA_IRQHandler DMA2_Channel2_IRQHandler
#define I2C1_RX_DMA_IRQ DMA2_Channel2_IRQn
#define I2C1_RX_DMA_HANDSHAK DMA_CH_HARDWARE_HANDSHAKING_IF_2
#define I2C1_RX_DMA_DMA_RCC RCC_AHB1_PERIPHEN_M7_DMA2
#define I2C1_RX_DMA_DMA_CHANNEL DMA_CHANNEL_2
#define I2C1_RX_DMA_DMAMUX_CHANNEL DMAMUX_CHANNEL_10
#define I2C1_RX_DMA_DMAMUX_REQUEST DMAMUX1_REQUEST_I2C1_RX
#elif defined(BSP_UART11_RX_USING_DMA) && !defined(UART11_RX_DMA_INSTANCE)
#define UART11_RX_DMA_INSTANCE DMA2
#define UART11_RX_DMA_IRQHandler DMA2_Channel2_IRQHandler
#define UART11_RX_DMA_IRQ DMA2_Channel2_IRQn
#define UART11_RX_DMA_HANDSHAK DMA_CH_HARDWARE_HANDSHAKING_IF_2
#define UART11_RX_DMA_DMA_RCC RCC_AHB1_PERIPHEN_M7_DMA2
#define UART11_RX_DMA_DMA_CHANNEL DMA_CHANNEL_2
#define UART11_RX_DMA_DMAMUX_CHANNEL DMAMUX_CHANNEL_10
#define UART11_RX_DMA_DMAMUX_REQUEST DMAMUX1_REQUEST_UART11_RX
#elif defined(BSP_SPI5_TX_USING_DMA) && !defined(SPI5_TX_DMA_INSTANCE)
#define SPI5_TX_DMA_INSTANCE DMA2
#define SPI5_TX_DMA_IRQHandler DMA2_Channel2_IRQHandler
#define SPI5_TX_DMA_IRQ DMA2_Channel2_IRQn
#define SPI5_TX_DMA_HANDSHAK DMA_CH_HARDWARE_HANDSHAKING_IF_2
#define SPI5_TX_DMA_DMA_RCC RCC_AHB1_PERIPHEN_M7_DMA2
#define SPI5_TX_DMA_DMA_CHANNEL DMA_CHANNEL_2
#define SPI5_TX_DMA_DMAMUX_CHANNEL DMAMUX_CHANNEL_10
#define SPI5_TX_DMA_DMAMUX_REQUEST DMAMUX1_REQUEST_SPI5_TX
#endif
/* DMAMUX1 channel11 / DMA2 channel3 */
#if defined(BSP_I2C2_RX_USING_DMA) && !defined(I2C2_RX_DMA_INSTANCE)
#define I2C2_RX_DMA_INSTANCE DMA2
#define I2C2_RX_DMA_IRQHandler DMA2_Channel3_IRQHandler
#define I2C2_RX_DMA_IRQ DMA2_Channel3_IRQn
#define I2C2_RX_DMA_HANDSHAK DMA_CH_HARDWARE_HANDSHAKING_IF_3
#define I2C2_RX_DMA_DMA_RCC RCC_AHB1_PERIPHEN_M7_DMA2
#define I2C2_RX_DMA_DMA_CHANNEL DMA_CHANNEL_3
#define I2C2_RX_DMA_DMAMUX_CHANNEL DMAMUX_CHANNEL_11
#define I2C2_RX_DMA_DMAMUX_REQUEST DMAMUX1_REQUEST_I2C2_RX
#elif defined(BSP_UART12_RX_USING_DMA) && !defined(UART12_RX_DMA_INSTANCE)
#define UART12_RX_DMA_INSTANCE DMA2
#define UART12_RX_DMA_IRQHandler DMA2_Channel3_IRQHandler
#define UART12_RX_DMA_IRQ DMA2_Channel3_IRQn
#define UART12_RX_DMA_HANDSHAK DMA_CH_HARDWARE_HANDSHAKING_IF_3
#define UART12_RX_DMA_DMA_RCC RCC_AHB1_PERIPHEN_M7_DMA2
#define UART12_RX_DMA_DMA_CHANNEL DMA_CHANNEL_3
#define UART12_RX_DMA_DMAMUX_CHANNEL DMAMUX_CHANNEL_11
#define UART12_RX_DMA_DMAMUX_REQUEST DMAMUX1_REQUEST_UART12_RX
#elif defined(BSP_SPI6_TX_USING_DMA) && !defined(SPI6_TX_DMA_INSTANCE)
#define SPI6_TX_DMA_INSTANCE DMA2
#define SPI6_TX_DMA_IRQHandler DMA2_Channel3_IRQHandler
#define SPI6_TX_DMA_IRQ DMA2_Channel3_IRQn
#define SPI6_TX_DMA_HANDSHAK DMA_CH_HARDWARE_HANDSHAKING_IF_3
#define SPI6_TX_DMA_DMA_RCC RCC_AHB1_PERIPHEN_M7_DMA2
#define SPI6_TX_DMA_DMA_CHANNEL DMA_CHANNEL_3
#define SPI6_TX_DMA_DMAMUX_CHANNEL DMAMUX_CHANNEL_11
#define SPI6_TX_DMA_DMAMUX_REQUEST DMAMUX1_REQUEST_SPI6_TX
#endif
/* DMAMUX1 channel12 / DMA2 channel4 */
#if defined(BSP_I2C3_RX_USING_DMA) && !defined(I2C3_RX_DMA_INSTANCE)
#define I2C3_RX_DMA_INSTANCE DMA2
#define I2C3_RX_DMA_IRQHandler DMA2_Channel4_IRQHandler
#define I2C3_RX_DMA_IRQ DMA2_Channel4_IRQn
#define I2C3_RX_DMA_HANDSHAK DMA_CH_HARDWARE_HANDSHAKING_IF_4
#define I2C3_RX_DMA_DMA_RCC RCC_AHB1_PERIPHEN_M7_DMA2
#define I2C3_RX_DMA_DMA_CHANNEL DMA_CHANNEL_4
#define I2C3_RX_DMA_DMAMUX_CHANNEL DMAMUX_CHANNEL_12
#define I2C3_RX_DMA_DMAMUX_REQUEST DMAMUX1_REQUEST_I2C3_RX
#elif defined(BSP_UART13_RX_USING_DMA) && !defined(UART13_RX_DMA_INSTANCE)
#define UART13_RX_DMA_INSTANCE DMA2
#define UART13_RX_DMA_IRQHandler DMA2_Channel4_IRQHandler
#define UART13_RX_DMA_IRQ DMA2_Channel4_IRQn
#define UART13_RX_DMA_HANDSHAK DMA_CH_HARDWARE_HANDSHAKING_IF_4
#define UART13_RX_DMA_DMA_RCC RCC_AHB1_PERIPHEN_M7_DMA2
#define UART13_RX_DMA_DMA_CHANNEL DMA_CHANNEL_4
#define UART13_RX_DMA_DMAMUX_CHANNEL DMAMUX_CHANNEL_12
#define UART13_RX_DMA_DMAMUX_REQUEST DMAMUX1_REQUEST_UART13_RX
#elif defined(BSP_SPI7_TX_USING_DMA) && !defined(SPI7_TX_DMA_INSTANCE)
#define SPI7_TX_DMA_INSTANCE DMA2
#define SPI7_TX_DMA_IRQHandler DMA2_Channel4_IRQHandler
#define SPI7_TX_DMA_IRQ DMA2_Channel4_IRQn
#define SPI7_TX_DMA_HANDSHAK DMA_CH_HARDWARE_HANDSHAKING_IF_4
#define SPI7_TX_DMA_DMA_RCC RCC_AHB1_PERIPHEN_M7_DMA2
#define SPI7_TX_DMA_DMA_CHANNEL DMA_CHANNEL_4
#define SPI7_TX_DMA_DMAMUX_CHANNEL DMAMUX_CHANNEL_12
#define SPI7_TX_DMA_DMAMUX_REQUEST DMAMUX1_REQUEST_SPI7_TX
#endif
/* DMAMUX1 channel13 / DMA2 channel5 */
#if defined(BSP_I2C4_RX_USING_DMA) && !defined(I2C4_RX_DMA_INSTANCE)
#define I2C4_RX_DMA_INSTANCE DMA2
#define I2C4_RX_DMA_IRQHandler DMA2_Channel5_IRQHandler
#define I2C4_RX_DMA_IRQ DMA2_Channel5_IRQn
#define I2C4_RX_DMA_HANDSHAK DMA_CH_HARDWARE_HANDSHAKING_IF_5
#define I2C4_RX_DMA_DMA_RCC RCC_AHB1_PERIPHEN_M7_DMA2
#define I2C4_RX_DMA_DMA_CHANNEL DMA_CHANNEL_5
#define I2C4_RX_DMA_DMAMUX_CHANNEL DMAMUX_CHANNEL_13
#define I2C4_RX_DMA_DMAMUX_REQUEST DMAMUX1_REQUEST_I2C4_RX
#elif defined(BSP_UART14_RX_USING_DMA) && !defined(UART14_RX_DMA_INSTANCE)
#define UART14_RX_DMA_INSTANCE DMA2
#define UART14_RX_DMA_IRQHandler DMA2_Channel5_IRQHandler
#define UART14_RX_DMA_IRQ DMA2_Channel5_IRQn
#define UART14_RX_DMA_HANDSHAK DMA_CH_HARDWARE_HANDSHAKING_IF_5
#define UART14_RX_DMA_DMA_RCC RCC_AHB1_PERIPHEN_M7_DMA2
#define UART14_RX_DMA_DMA_CHANNEL DMA_CHANNEL_5
#define UART14_RX_DMA_DMAMUX_CHANNEL DMAMUX_CHANNEL_13
#define UART14_RX_DMA_DMAMUX_REQUEST DMAMUX1_REQUEST_UART14_RX
#elif defined(BSP_SPI1_RX_USING_DMA) && !defined(SPI1_RX_DMA_INSTANCE)
#define SPI1_RX_DMA_INSTANCE DMA2
#define SPI1_RX_DMA_IRQHandler DMA2_Channel5_IRQHandler
#define SPI1_RX_DMA_IRQ DMA2_Channel5_IRQn
#define SPI1_RX_DMA_HANDSHAK DMA_CH_HARDWARE_HANDSHAKING_IF_5
#define SPI1_RX_DMA_DMA_RCC RCC_AHB1_PERIPHEN_M7_DMA2
#define SPI1_RX_DMA_DMA_CHANNEL DMA_CHANNEL_5
#define SPI1_RX_DMA_DMAMUX_CHANNEL DMAMUX_CHANNEL_13
#define SPI1_RX_DMA_DMAMUX_REQUEST DMAMUX1_REQUEST_SPI1_RX
#endif
/* DMAMUX1 channel14 / DMA2 channel6 */
#if defined(BSP_I2C5_RX_USING_DMA) && !defined(I2C5_RX_DMA_INSTANCE)
#define I2C5_RX_DMA_INSTANCE DMA2
#define I2C5_RX_DMA_IRQHandler DMA2_Channel6_IRQHandler
#define I2C5_RX_DMA_IRQ DMA2_Channel6_IRQn
#define I2C5_RX_DMA_HANDSHAK DMA_CH_HARDWARE_HANDSHAKING_IF_6
#define I2C5_RX_DMA_DMA_RCC RCC_AHB1_PERIPHEN_M7_DMA2
#define I2C5_RX_DMA_DMA_CHANNEL DMA_CHANNEL_6
#define I2C5_RX_DMA_DMAMUX_CHANNEL DMAMUX_CHANNEL_14
#define I2C5_RX_DMA_DMAMUX_REQUEST DMAMUX1_REQUEST_I2C5_RX
#elif defined(BSP_UART15_RX_USING_DMA) && !defined(UART15_RX_DMA_INSTANCE)
#define UART15_RX_DMA_INSTANCE DMA2
#define UART15_RX_DMA_IRQHandler DMA2_Channel6_IRQHandler
#define UART15_RX_DMA_IRQ DMA2_Channel6_IRQn
#define UART15_RX_DMA_HANDSHAK DMA_CH_HARDWARE_HANDSHAKING_IF_6
#define UART15_RX_DMA_DMA_RCC RCC_AHB1_PERIPHEN_M7_DMA2
#define UART15_RX_DMA_DMA_CHANNEL DMA_CHANNEL_6
#define UART15_RX_DMA_DMAMUX_CHANNEL DMAMUX_CHANNEL_14
#define UART15_RX_DMA_DMAMUX_REQUEST DMAMUX1_REQUEST_UART15_RX
#elif defined(BSP_SPI2_RX_USING_DMA) && !defined(SPI2_RX_DMA_INSTANCE)
#define SPI2_RX_DMA_INSTANCE DMA2
#define SPI2_RX_DMA_IRQHandler DMA2_Channel6_IRQHandler
#define SPI2_RX_DMA_IRQ DMA2_Channel6_IRQn
#define SPI2_RX_DMA_HANDSHAK DMA_CH_HARDWARE_HANDSHAKING_IF_6
#define SPI2_RX_DMA_DMA_RCC RCC_AHB1_PERIPHEN_M7_DMA2
#define SPI2_RX_DMA_DMA_CHANNEL DMA_CHANNEL_6
#define SPI2_RX_DMA_DMAMUX_CHANNEL DMAMUX_CHANNEL_14
#define SPI2_RX_DMA_DMAMUX_REQUEST DMAMUX1_REQUEST_SPI2_RX
#endif
/* DMAMUX1 channel15 / DMA2 channel7 */
#if defined(BSP_I2C6_RX_USING_DMA) && !defined(I2C6_RX_DMA_INSTANCE)
#define I2C6_RX_DMA_INSTANCE DMA2
#define I2C6_RX_DMA_IRQHandler DMA2_Channel7_IRQHandler
#define I2C6_RX_DMA_IRQ DMA2_Channel7_IRQn
#define I2C6_RX_DMA_HANDSHAK DMA_CH_HARDWARE_HANDSHAKING_IF_7
#define I2C6_RX_DMA_DMA_RCC RCC_AHB1_PERIPHEN_M7_DMA2
#define I2C6_RX_DMA_DMA_CHANNEL DMA_CHANNEL_5
#define I2C6_RX_DMA_DMAMUX_CHANNEL DMAMUX_CHANNEL_15
#define I2C6_RX_DMA_DMAMUX_REQUEST DMAMUX1_REQUEST_I2C6_RX
#elif defined(BSP_LPUART1_RX_USING_DMA) && !defined(LPUART1_RX_DMA_INSTANCE)
#define LPUART1_RX_DMA_INSTANCE DMA2
#define LPUART1_RX_DMA_IRQHandler DMA2_Channel7_IRQHandler
#define LPUART1_RX_DMA_IRQ DMA2_Channel7_IRQn
#define LPUART1_RX_DMA_HANDSHAK DMA_CH_HARDWARE_HANDSHAKING_IF_7
#define LPUART1_RX_DMA_DMA_RCC RCC_AHB1_PERIPHEN_M7_DMA2
#define LPUART1_RX_DMA_DMA_CHANNEL DMA_CHANNEL_5
#define LPUART1_RX_DMA_DMAMUX_CHANNEL DMAMUX_CHANNEL_15
#define LPUART1_RX_DMA_DMAMUX_REQUEST DMAMUX1_REQUEST_LPUART1_RX
#elif defined(BSP_SPI3_RX_USING_DMA) && !defined(SPI3_RX_DMA_INSTANCE)
#define SPI3_RX_DMA_INSTANCE DMA2
#define SPI3_RX_DMA_IRQHandler DMA2_Channel7_IRQHandler
#define SPI3_RX_DMA_IRQ DMA2_Channel7_IRQn
#define SPI3_RX_DMA_HANDSHAK DMA_CH_HARDWARE_HANDSHAKING_IF_7
#define SPI3_RX_DMA_DMA_RCC RCC_AHB1_PERIPHEN_M7_DMA2
#define SPI3_RX_DMA_DMA_CHANNEL DMA_CHANNEL_5
#define SPI3_RX_DMA_DMAMUX_CHANNEL DMAMUX_CHANNEL_15
#define SPI3_RX_DMA_DMAMUX_REQUEST DMAMUX1_REQUEST_SPI3_RX
#endif
/* DMAMUX1 channel16 / DMA3 channel0 */
#if defined(BSP_I2C7_RX_USING_DMA) && !defined(I2C7_RX_DMA_INSTANCE)
#define I2C7_RX_DMA_INSTANCE DMA3
#define I2C7_RX_DMA_IRQHandler DMA3_Channel0_IRQHandler
#define I2C7_RX_DMA_IRQ DMA3_Channel0_IRQn
#define I2C7_RX_DMA_HANDSHAK DMA_CH_HARDWARE_HANDSHAKING_IF_0
#define I2C7_RX_DMA_DMA_RCC RCC_AHB1_PERIPHEN_M7_DMA3
#define I2C7_RX_DMA_DMA_CHANNEL DMA_CHANNEL_0
#define I2C7_RX_DMA_DMAMUX_CHANNEL DMAMUX_CHANNEL_16
#define I2C7_RX_DMA_DMAMUX_REQUEST DMAMUX1_REQUEST_I2C7_RX
#elif defined(BSP_LPUART2_RX_USING_DMA) && !defined(LPUART2_RX_DMA_INSTANCE)
#define LPUART2_RX_DMA_INSTANCE DMA3
#define LPUART2_RX_DMA_IRQHandler DMA3_Channel0_IRQHandler
#define LPUART2_RX_DMA_IRQ DMA3_Channel0_IRQn
#define LPUART2_RX_DMA_HANDSHAK DMA_CH_HARDWARE_HANDSHAKING_IF_0
#define LPUART2_RX_DMA_DMA_RCC RCC_AHB1_PERIPHEN_M7_DMA3
#define LPUART2_RX_DMA_DMA_CHANNEL DMA_CHANNEL_0
#define LPUART2_RX_DMA_DMAMUX_CHANNEL DMAMUX_CHANNEL_16
#define LPUART2_RX_DMA_DMAMUX_REQUEST DMAMUX1_REQUEST_LPUART2_RX
#elif defined(BSP_SPI4_RX_USING_DMA) && !defined(SPI4_RX_DMA_INSTANCE)
#define SPI4_RX_DMA_INSTANCE DMA3
#define SPI4_RX_DMA_IRQHandler DMA3_Channel0_IRQHandler
#define SPI4_RX_DMA_IRQ DMA3_Channel0_IRQn
#define SPI4_RX_DMA_HANDSHAK DMA_CH_HARDWARE_HANDSHAKING_IF_0
#define SPI4_RX_DMA_DMA_RCC RCC_AHB1_PERIPHEN_M7_DMA3
#define SPI4_RX_DMA_DMA_CHANNEL DMA_CHANNEL_0
#define SPI4_RX_DMA_DMAMUX_CHANNEL DMAMUX_CHANNEL_16
#define SPI4_RX_DMA_DMAMUX_REQUEST DMAMUX1_REQUEST_SPI4_RX
#endif
/* DMAMUX1 channel17 / DMA3 channel1 */
#if defined(BSP_I2C8_RX_USING_DMA) && !defined(I2C8_RX_DMA_INSTANCE)
#define I2C8_RX_DMA_INSTANCE DMA3
#define I2C8_RX_DMA_IRQHandler DMA3_Channel1_IRQHandler
#define I2C8_RX_DMA_IRQ DMA3_Channel1_IRQn
#define I2C8_RX_DMA_HANDSHAK DMA_CH_HARDWARE_HANDSHAKING_IF_1
#define I2C8_RX_DMA_DMA_RCC RCC_AHB1_PERIPHEN_M7_DMA3
#define I2C8_RX_DMA_DMA_CHANNEL DMA_CHANNEL_1
#define I2C8_RX_DMA_DMAMUX_CHANNEL DMAMUX_CHANNEL_17
#define I2C8_RX_DMA_DMAMUX_REQUEST DMAMUX1_REQUEST_I2C8_RX
#elif defined(BSP_UART1_TX_USING_DMA) && !defined(UART1_TX_DMA_INSTANCE)
#define UART1_TX_DMA_INSTANCE DMA3
#define UART1_TX_DMA_IRQHandler DMA3_Channel1_IRQHandler
#define UART1_TX_DMA_IRQ DMA3_Channel1_IRQn
#define UART1_TX_DMA_HANDSHAK DMA_CH_HARDWARE_HANDSHAKING_IF_1
#define UART1_TX_DMA_DMA_RCC RCC_AHB1_PERIPHEN_M7_DMA3
#define UART1_TX_DMA_DMA_CHANNEL DMA_CHANNEL_1
#define UART1_TX_DMA_DMAMUX_CHANNEL DMAMUX_CHANNEL_17
#define UART1_TX_DMA_DMAMUX_REQUEST DMAMUX1_REQUEST_USART1_TX
#elif defined(BSP_SPI5_RX_USING_DMA) && !defined(SPI5_RX_DMA_INSTANCE)
#define SPI5_RX_DMA_INSTANCE DMA3
#define SPI5_RX_DMA_IRQHandler DMA3_Channel1_IRQHandler
#define SPI5_RX_DMA_IRQ DMA3_Channel1_IRQn
#define SPI5_RX_DMA_HANDSHAK DMA_CH_HARDWARE_HANDSHAKING_IF_1
#define SPI5_RX_DMA_DMA_RCC RCC_AHB1_PERIPHEN_M7_DMA3
#define SPI5_RX_DMA_DMA_CHANNEL DMA_CHANNEL_1
#define SPI5_RX_DMA_DMAMUX_CHANNEL DMAMUX_CHANNEL_17
#define SPI5_RX_DMA_DMAMUX_REQUEST DMAMUX1_REQUEST_SPI5_RX
#endif
/* DMAMUX1 channel18 / DMA3 channel2 */
#if defined(BSP_I2C9_RX_USING_DMA) && !defined(I2C9_RX_DMA_INSTANCE)
#define I2C9_RX_DMA_INSTANCE DMA3
#define I2C9_RX_DMA_IRQHandler DMA3_Channel2_IRQHandler
#define I2C9_RX_DMA_IRQ DMA3_Channel2_IRQn
#define I2C9_RX_DMA_HANDSHAK DMA_CH_HARDWARE_HANDSHAKING_IF_2
#define I2C9_RX_DMA_DMA_RCC RCC_AHB1_PERIPHEN_M7_DMA3
#define I2C9_RX_DMA_DMA_CHANNEL DMA_CHANNEL_2
#define I2C9_RX_DMA_DMAMUX_CHANNEL DMAMUX_CHANNEL_18
#define I2C9_RX_DMA_DMAMUX_REQUEST DMAMUX1_REQUEST_I2C9_RX
#elif defined(BSP_UART2_TX_USING_DMA) && !defined(UART2_TX_DMA_INSTANCE)
#define UART2_TX_DMA_INSTANCE DMA3
#define UART2_TX_DMA_IRQHandler DMA3_Channel2_IRQHandler
#define UART2_TX_DMA_IRQ DMA3_Channel2_IRQn
#define UART2_TX_DMA_HANDSHAK DMA_CH_HARDWARE_HANDSHAKING_IF_2
#define UART2_TX_DMA_DMA_RCC RCC_AHB1_PERIPHEN_M7_DMA3
#define UART2_TX_DMA_DMA_CHANNEL DMA_CHANNEL_2
#define UART2_TX_DMA_DMAMUX_CHANNEL DMAMUX_CHANNEL_18
#define UART2_TX_DMA_DMAMUX_REQUEST DMAMUX1_REQUEST_USART2_TX
#elif defined(BSP_SPI6_RX_USING_DMA) && !defined(SPI6_RX_DMA_INSTANCE)
#define SPI6_RX_DMA_INSTANCE DMA3
#define SPI6_RX_DMA_IRQHandler DMA3_Channel2_IRQHandler
#define SPI6_RX_DMA_IRQ DMA3_Channel2_IRQn
#define SPI6_RX_DMA_HANDSHAK DMA_CH_HARDWARE_HANDSHAKING_IF_2
#define SPI6_RX_DMA_DMA_RCC RCC_AHB1_PERIPHEN_M7_DMA3
#define SPI6_RX_DMA_DMA_CHANNEL DMA_CHANNEL_2
#define SPI6_RX_DMA_DMAMUX_CHANNEL DMAMUX_CHANNEL_18
#define SPI6_RX_DMA_DMAMUX_REQUEST DMAMUX1_REQUEST_SPI6_RX
#endif
/* DMAMUX1 channel19 / DMA3 channel3 */
#if defined(BSP_I2C10_RX_USING_DMA) && !defined(I2C10_RX_DMA_INSTANCE)
#define I2C10_RX_DMA_INSTANCE DMA3
#define I2C10_RX_DMA_IRQHandler DMA3_Channel3_IRQHandler
#define I2C10_RX_DMA_IRQ DMA3_Channel3_IRQn
#define I2C10_RX_DMA_HANDSHAK DMA_CH_HARDWARE_HANDSHAKING_IF_3
#define I2C10_RX_DMA_DMA_RCC RCC_AHB1_PERIPHEN_M7_DMA3
#define I2C10_RX_DMA_DMA_CHANNEL DMA_CHANNEL_3
#define I2C10_RX_DMA_DMAMUX_CHANNEL DMAMUX_CHANNEL_19
#define I2C10_RX_DMA_DMAMUX_REQUEST DMAMUX1_REQUEST_I2C10_RX
#elif defined(BSP_UART3_TX_USING_DMA) && !defined(UART3_TX_DMA_INSTANCE)
#define UART3_TX_DMA_INSTANCE DMA3
#define UART3_TX_DMA_IRQHandler DMA3_Channel3_IRQHandler
#define UART3_TX_DMA_IRQ DMA3_Channel3_IRQn
#define UART3_TX_DMA_HANDSHAK DMA_CH_HARDWARE_HANDSHAKING_IF_3
#define UART3_TX_DMA_DMA_RCC RCC_AHB1_PERIPHEN_M7_DMA3
#define UART3_TX_DMA_DMA_CHANNEL DMA_CHANNEL_3
#define UART3_TX_DMA_DMAMUX_CHANNEL DMAMUX_CHANNEL_19
#define UART3_TX_DMA_DMAMUX_REQUEST DMAMUX1_REQUEST_USART3_TX
#elif defined(BSP_SPI7_RX_USING_DMA) && !defined(SPI7_RX_DMA_INSTANCE)
#define SPI7_RX_DMA_INSTANCE DMA3
#define SPI7_RX_DMA_IRQHandler DMA3_Channel3_IRQHandler
#define SPI7_RX_DMA_IRQ DMA3_Channel3_IRQn
#define SPI7_RX_DMA_HANDSHAK DMA_CH_HARDWARE_HANDSHAKING_IF_3
#define SPI7_RX_DMA_DMA_RCC RCC_AHB1_PERIPHEN_M7_DMA3
#define SPI7_RX_DMA_DMA_CHANNEL DMA_CHANNEL_3
#define SPI7_RX_DMA_DMAMUX_CHANNEL DMAMUX_CHANNEL_19
#define SPI7_RX_DMA_DMAMUX_REQUEST DMAMUX1_REQUEST_SPI7_RX
#endif
/* DMAMUX1 channel20 / DMA3 channel4 */
#if defined(BSP_I2C1_TX_USING_DMA) && !defined(I2C1_TX_DMA_INSTANCE)
#define I2C1_TX_DMA_INSTANCE DMA3
#define I2C1_TX_DMA_IRQHandler DMA3_Channel4_IRQHandler
#define I2C1_TX_DMA_IRQ DMA3_Channel4_IRQn
#define I2C1_TX_DMA_HANDSHAK DMA_CH_HARDWARE_HANDSHAKING_IF_4
#define I2C1_TX_DMA_DMA_RCC RCC_AHB1_PERIPHEN_M7_DMA3
#define I2C1_TX_DMA_DMA_CHANNEL DMA_CHANNEL_4
#define I2C1_TX_DMA_DMAMUX_CHANNEL DMAMUX_CHANNEL_20
#define I2C1_TX_DMA_DMAMUX_REQUEST DMAMUX1_REQUEST_I2C1_TX
#elif defined(BSP_UART4_TX_USING_DMA) && !defined(UART4_TX_DMA_INSTANCE)
#define UART4_TX_DMA_INSTANCE DMA3
#define UART4_TX_DMA_IRQHandler DMA3_Channel4_IRQHandler
#define UART4_TX_DMA_IRQ DMA3_Channel4_IRQn
#define UART4_TX_DMA_HANDSHAK DMA_CH_HARDWARE_HANDSHAKING_IF_4
#define UART4_TX_DMA_DMA_RCC RCC_AHB1_PERIPHEN_M7_DMA3
#define UART4_TX_DMA_DMA_CHANNEL DMA_CHANNEL_4
#define UART4_TX_DMA_DMAMUX_CHANNEL DMAMUX_CHANNEL_20
#define UART4_TX_DMA_DMAMUX_REQUEST DMAMUX1_REQUEST_USART4_TX
#endif
/* DMAMUX1 channel21 / DMA3 channel5 */
#if defined(BSP_I2C2_TX_USING_DMA) && !defined(I2C2_TX_DMA_INSTANCE)
#define I2C2_TX_DMA_INSTANCE DMA3
#define I2C2_TX_DMA_IRQHandler DMA3_Channel5_IRQHandler
#define I2C2_TX_DMA_IRQ DMA3_Channel5_IRQn
#define I2C2_TX_DMA_HANDSHAK DMA_CH_HARDWARE_HANDSHAKING_IF_5
#define I2C2_TX_DMA_DMA_RCC RCC_AHB1_PERIPHEN_M7_DMA3
#define I2C2_TX_DMA_DMA_CHANNEL DMA_CHANNEL_5
#define I2C2_TX_DMA_DMAMUX_CHANNEL DMAMUX_CHANNEL_21
#define I2C2_TX_DMA_DMAMUX_REQUEST DMAMUX1_REQUEST_I2C2_TX
#elif defined(BSP_UART5_TX_USING_DMA) && !defined(UART5_TX_DMA_INSTANCE)
#define UART5_TX_DMA_INSTANCE DMA3
#define UART5_TX_DMA_IRQHandler DMA3_Channel5_IRQHandler
#define UART5_TX_DMA_IRQ DMA3_Channel5_IRQn
#define UART5_TX_DMA_HANDSHAK DMA_CH_HARDWARE_HANDSHAKING_IF_5
#define UART5_TX_DMA_DMA_RCC RCC_AHB1_PERIPHEN_M7_DMA3
#define UART5_TX_DMA_DMA_CHANNEL DMA_CHANNEL_5
#define UART5_TX_DMA_DMAMUX_CHANNEL DMAMUX_CHANNEL_21
#define UART5_TX_DMA_DMAMUX_REQUEST DMAMUX1_REQUEST_USART5_TX
#endif
/* DMAMUX1 channel22 / DMA3 channel6 */
#if defined(BSP_I2C3_TX_USING_DMA) && !defined(I2C3_TX_DMA_INSTANCE)
#define I2C3_TX_DMA_INSTANCE DMA3
#define I2C3_TX_DMA_IRQHandler DMA3_Channel6_IRQHandler
#define I2C3_TX_DMA_IRQ DMA3_Channel6_IRQn
#define I2C3_TX_DMA_HANDSHAK DMA_CH_HARDWARE_HANDSHAKING_IF_6
#define I2C3_TX_DMA_DMA_RCC RCC_AHB1_PERIPHEN_M7_DMA3
#define I2C3_TX_DMA_DMA_CHANNEL DMA_CHANNEL_6
#define I2C3_TX_DMA_DMAMUX_CHANNEL DMAMUX_CHANNEL_22
#define I2C3_TX_DMA_DMAMUX_REQUEST DMAMUX1_REQUEST_I2C3_TX
#elif defined(BSP_UART6_TX_USING_DMA) && !defined(UART6_TX_DMA_INSTANCE)
#define UART6_TX_DMA_INSTANCE DMA3
#define UART6_TX_DMA_IRQHandler DMA3_Channel6_IRQHandler
#define UART6_TX_DMA_IRQ DMA3_Channel6_IRQn
#define UART6_TX_DMA_HANDSHAK DMA_CH_HARDWARE_HANDSHAKING_IF_6
#define UART6_TX_DMA_DMA_RCC RCC_AHB1_PERIPHEN_M7_DMA3
#define UART6_TX_DMA_DMA_CHANNEL DMA_CHANNEL_6
#define UART6_TX_DMA_DMAMUX_CHANNEL DMAMUX_CHANNEL_22
#define UART6_TX_DMA_DMAMUX_REQUEST DMAMUX1_REQUEST_USART6_TX
#endif
/* DMAMUX1 channel23 / DMA3 channel7 */
#if defined(BSP_I2C4_TX_USING_DMA) && !defined(I2C4_TX_DMA_INSTANCE)
#define I2C4_TX_DMA_INSTANCE DMA3
#define I2C4_TX_DMA_IRQHandler DMA3_Channel7_IRQHandler
#define I2C4_TX_DMA_IRQ DMA3_Channel7_IRQn
#define I2C4_TX_DMA_HANDSHAK DMA_CH_HARDWARE_HANDSHAKING_IF_7
#define I2C4_TX_DMA_DMA_RCC RCC_AHB1_PERIPHEN_M7_DMA3
#define I2C4_TX_DMA_DMA_CHANNEL DMA_CHANNEL_7
#define I2C4_TX_DMA_DMAMUX_CHANNEL DMAMUX_CHANNEL_23
#define I2C4_TX_DMA_DMAMUX_REQUEST DMAMUX1_REQUEST_I2C4_TX
#elif defined(BSP_UART7_TX_USING_DMA) && !defined(UART7_TX_DMA_INSTANCE)
#define UART7_TX_DMA_INSTANCE DMA3
#define UART7_TX_DMA_IRQHandler DMA3_Channel7_IRQHandler
#define UART7_TX_DMA_IRQ DMA3_Channel7_IRQn
#define UART7_TX_DMA_HANDSHAK DMA_CH_HARDWARE_HANDSHAKING_IF_7
#define UART7_TX_DMA_DMA_RCC RCC_AHB1_PERIPHEN_M7_DMA3
#define UART7_TX_DMA_DMA_CHANNEL DMA_CHANNEL_7
#define UART7_TX_DMA_DMAMUX_CHANNEL DMAMUX_CHANNEL_23
#define UART7_TX_DMA_DMAMUX_REQUEST DMAMUX1_REQUEST_USART7_TX
#endif
#ifdef __cplusplus
}
#endif
#endif /* __DMA_CONFIG_H__ */

310
bsp/n32/n32hxxx/libraries/N32_Drivers/drivers/config/h7/spi_config.h
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@ -1,310 +0,0 @@
/*
* Copyright (c) 2006-2025, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2026-01-24 ox-horse first version
*/
#ifndef __SPI_CONFIG_H__
#define __SPI_CONFIG_H__
#include <rtthread.h>
#ifdef __cplusplus
extern "C" {
#endif
#ifdef BSP_USING_SPI1
#ifndef SPI1_BUS_CONFIG
#define SPI1_BUS_CONFIG \
{ \
.SPIx = SPI1, \
.bus_name = "spi1", \
.irq_type = SPI1_IRQn, \
}
#endif /* SPI1_BUS_CONFIG */
#endif /* BSP_USING_SPI1 */
#ifdef BSP_SPI1_TX_USING_DMA
#ifndef SPI1_TX_DMA_CONFIG
#define SPI1_TX_DMA_CONFIG \
{ \
.Instance = SPI1_TX_DMA_INSTANCE, \
.dma_irq = SPI1_TX_DMA_IRQ, \
.HsInterface = SPI1_TX_DMA_HANDSHAK, \
.dma_rcc = SPI1_TX_DMA_DMA_RCC, \
.dma_channel = SPI1_TX_DMA_DMA_CHANNEL, \
.dmamux_channel = SPI1_TX_DMA_DMAMUX_CHANNEL, \
.dmamux_request = SPI1_TX_DMA_DMAMUX_REQUEST, \
}
#endif /* SPI1_TX_DMA_CONFIG */
#endif /* BSP_SPI1_TX_USING_DMA */
#ifdef BSP_SPI1_RX_USING_DMA
#ifndef SPI1_RX_DMA_CONFIG
#define SPI1_RX_DMA_CONFIG \
{ \
.Instance = SPI1_RX_DMA_INSTANCE, \
.dma_irq = SPI1_RX_DMA_IRQ, \
.HsInterface = SPI1_RX_DMA_HANDSHAK, \
.dma_rcc = SPI1_RX_DMA_DMA_RCC, \
.dma_channel = SPI1_RX_DMA_DMA_CHANNEL, \
.dmamux_channel = SPI1_RX_DMA_DMAMUX_CHANNEL, \
.dmamux_request = SPI1_RX_DMA_DMAMUX_REQUEST, \
}
#endif /* SPI1_RX_DMA_CONFIG */
#endif /* BSP_SPI1_RX_USING_DMA */
#ifdef BSP_USING_SPI2
#ifndef SPI2_BUS_CONFIG
#define SPI2_BUS_CONFIG \
{ \
.SPIx = SPI2, \
.bus_name = "spi2", \
.irq_type = SPI2_IRQn, \
}
#endif /* SPI2_BUS_CONFIG */
#endif /* BSP_USING_SPI2 */
#ifdef BSP_SPI2_TX_USING_DMA
#ifndef SPI2_TX_DMA_CONFIG
#define SPI2_TX_DMA_CONFIG \
{ \
.Instance = SPI2_TX_DMA_INSTANCE, \
.dma_irq = SPI2_TX_DMA_IRQ, \
.HsInterface = SPI2_TX_DMA_HANDSHAK, \
.dma_rcc = SPI2_TX_DMA_DMA_RCC, \
.dma_channel = SPI2_TX_DMA_DMA_CHANNEL, \
.dmamux_channel = SPI2_TX_DMA_DMAMUX_CHANNEL, \
.dmamux_request = SPI2_TX_DMA_DMAMUX_REQUEST, \
}
#endif /* SPI2_TX_DMA_CONFIG */
#endif /* BSP_SPI2_TX_USING_DMA */
#ifdef BSP_SPI2_RX_USING_DMA
#ifndef SPI2_RX_DMA_CONFIG
#define SPI2_RX_DMA_CONFIG \
{ \
.Instance = SPI2_RX_DMA_INSTANCE, \
.dma_irq = SPI2_RX_DMA_IRQ, \
.HsInterface = SPI2_RX_DMA_HANDSHAK, \
.dma_rcc = SPI2_RX_DMA_DMA_RCC, \
.dma_channel = SPI2_RX_DMA_DMA_CHANNEL, \
.dmamux_channel = SPI2_RX_DMA_DMAMUX_CHANNEL, \
.dmamux_request = SPI2_RX_DMA_DMAMUX_REQUEST, \
}
#endif /* SPI2_RX_DMA_CONFIG */
#endif /* BSP_SPI2_RX_USING_DMA */
#ifdef BSP_USING_SPI3
#ifndef SPI3_BUS_CONFIG
#define SPI3_BUS_CONFIG \
{ \
.SPIx = SPI3, \
.bus_name = "spi3", \
.irq_type = SPI3_IRQn, \
}
#endif /* SPI3_BUS_CONFIG */
#endif /* BSP_USING_SPI3 */
#ifdef BSP_SPI3_TX_USING_DMA
#ifndef SPI3_TX_DMA_CONFIG
#define SPI3_TX_DMA_CONFIG \
{ \
.Instance = SPI3_TX_DMA_INSTANCE, \
.dma_irq = SPI3_TX_DMA_IRQ, \
.HsInterface = SPI3_TX_DMA_HANDSHAK, \
.dma_rcc = SPI3_TX_DMA_DMA_RCC, \
.dma_channel = SPI3_TX_DMA_DMA_CHANNEL, \
.dmamux_channel = SPI3_TX_DMA_DMAMUX_CHANNEL, \
.dmamux_request = SPI3_TX_DMA_DMAMUX_REQUEST, \
}
#endif /* SPI3_TX_DMA_CONFIG */
#endif /* BSP_SPI3_TX_USING_DMA */
#ifdef BSP_SPI3_RX_USING_DMA
#ifndef SPI3_RX_DMA_CONFIG
#define SPI3_RX_DMA_CONFIG \
{ \
.Instance = SPI3_RX_DMA_INSTANCE, \
.dma_irq = SPI3_RX_DMA_IRQ, \
.HsInterface = SPI3_RX_DMA_HANDSHAK, \
.dma_rcc = SPI3_RX_DMA_DMA_RCC, \
.dma_channel = SPI3_RX_DMA_DMA_CHANNEL, \
.dmamux_channel = SPI3_RX_DMA_DMAMUX_CHANNEL, \
.dmamux_request = SPI3_RX_DMA_DMAMUX_REQUEST, \
}
#endif /* SPI3_RX_DMA_CONFIG */
#endif /* BSP_SPI3_RX_USING_DMA */
#ifdef BSP_USING_SPI4
#ifndef SPI4_BUS_CONFIG
#define SPI4_BUS_CONFIG \
{ \
.SPIx = SPI4, \
.bus_name = "spi4", \
.irq_type = SPI4_IRQn, \
}
#endif /* SPI4_BUS_CONFIG */
#endif /* BSP_USING_SPI4 */
#ifdef BSP_SPI4_TX_USING_DMA
#ifndef SPI4_TX_DMA_CONFIG
#define SPI4_TX_DMA_CONFIG \
{ \
.Instance = SPI4_TX_DMA_INSTANCE, \
.dma_irq = SPI4_TX_DMA_IRQ, \
.HsInterface = SPI4_TX_DMA_HANDSHAK, \
.dma_rcc = SPI4_TX_DMA_DMA_RCC, \
.dma_channel = SPI4_TX_DMA_DMA_CHANNEL, \
.dmamux_channel = SPI4_TX_DMA_DMAMUX_CHANNEL, \
.dmamux_request = SPI4_TX_DMA_DMAMUX_REQUEST, \
}
#endif /* SPI4_TX_DMA_CONFIG */
#endif /* BSP_SPI4_TX_USING_DMA */
#ifdef BSP_SPI4_RX_USING_DMA
#ifndef SPI4_RX_DMA_CONFIG
#define SPI4_RX_DMA_CONFIG \
{ \
.Instance = SPI4_RX_DMA_INSTANCE, \
.dma_irq = SPI4_RX_DMA_IRQ, \
.HsInterface = SPI4_RX_DMA_HANDSHAK, \
.dma_rcc = SPI4_RX_DMA_DMA_RCC, \
.dma_channel = SPI4_RX_DMA_DMA_CHANNEL, \
.dmamux_channel = SPI4_RX_DMA_DMAMUX_CHANNEL, \
.dmamux_request = SPI4_RX_DMA_DMAMUX_REQUEST, \
}
#endif /* SPI4_RX_DMA_CONFIG */
#endif /* BSP_SPI4_RX_USING_DMA */
#ifdef BSP_USING_SPI5
#ifndef SPI5_BUS_CONFIG
#define SPI5_BUS_CONFIG \
{ \
.SPIx = SPI5, \
.bus_name = "spi5", \
.irq_type = SPI5_IRQn, \
}
#endif /* SPI5_BUS_CONFIG */
#endif /* BSP_USING_SPI5 */
#ifdef BSP_SPI5_TX_USING_DMA
#ifndef SPI5_TX_DMA_CONFIG
#define SPI5_TX_DMA_CONFIG \
{ \
.Instance = SPI5_TX_DMA_INSTANCE, \
.dma_irq = SPI5_TX_DMA_IRQ, \
.HsInterface = SPI5_TX_DMA_HANDSHAK, \
.dma_rcc = SPI5_TX_DMA_DMA_RCC, \
.dma_channel = SPI5_TX_DMA_DMA_CHANNEL, \
.dmamux_channel = SPI5_TX_DMA_DMAMUX_CHANNEL, \
.dmamux_request = SPI5_TX_DMA_DMAMUX_REQUEST, \
}
#endif /* SPI5_TX_DMA_CONFIG */
#endif /* BSP_SPI5_TX_USING_DMA */
#ifdef BSP_SPI5_RX_USING_DMA
#ifndef SPI5_RX_DMA_CONFIG
#define SPI5_RX_DMA_CONFIG \
{ \
.Instance = SPI5_RX_DMA_INSTANCE, \
.dma_irq = SPI5_RX_DMA_IRQ, \
.HsInterface = SPI5_RX_DMA_HANDSHAK, \
.dma_rcc = SPI5_RX_DMA_DMA_RCC, \
.dma_channel = SPI5_RX_DMA_DMA_CHANNEL, \
.dmamux_channel = SPI5_RX_DMA_DMAMUX_CHANNEL, \
.dmamux_request = SPI5_RX_DMA_DMAMUX_REQUEST, \
}
#endif /* SPI5_RX_DMA_CONFIG */
#endif /* BSP_SPI5_RX_USING_DMA */
#ifdef BSP_USING_SPI6
#ifndef SPI6_BUS_CONFIG
#define SPI6_BUS_CONFIG \
{ \
.SPIx = SPI6, \
.bus_name = "spi6", \
.irq_type = SPI6_IRQn, \
}
#endif /* SPI6_BUS_CONFIG */
#endif /* BSP_USING_SPI6 */
#ifdef BSP_SPI6_TX_USING_DMA
#ifndef SPI6_TX_DMA_CONFIG
#define SPI6_TX_DMA_CONFIG \
{ \
.Instance = SPI6_TX_DMA_INSTANCE, \
.dma_irq = SPI6_TX_DMA_IRQ, \
.HsInterface = SPI6_TX_DMA_HANDSHAK, \
.dma_rcc = SPI6_TX_DMA_DMA_RCC, \
.dma_channel = SPI6_TX_DMA_DMA_CHANNEL, \
.dmamux_channel = SPI6_TX_DMA_DMAMUX_CHANNEL, \
.dmamux_request = SPI6_TX_DMA_DMAMUX_REQUEST, \
}
#endif /* SPI6_TX_DMA_CONFIG */
#endif /* BSP_SPI6_TX_USING_DMA */
#ifdef BSP_SPI6_RX_USING_DMA
#ifndef SPI6_RX_DMA_CONFIG
#define SPI6_RX_DMA_CONFIG \
{ \
.Instance = SPI6_RX_DMA_INSTANCE, \
.dma_irq = SPI6_RX_DMA_IRQ, \
.HsInterface = SPI6_RX_DMA_HANDSHAK, \
.dma_rcc = SPI6_RX_DMA_DMA_RCC, \
.dma_channel = SPI6_RX_DMA_DMA_CHANNEL, \
.dmamux_channel = SPI6_RX_DMA_DMAMUX_CHANNEL, \
.dmamux_request = SPI6_RX_DMA_DMAMUX_REQUEST, \
}
#endif /* SPI6_RX_DMA_CONFIG */
#endif /* BSP_SPI6_RX_USING_DMA */
#ifdef BSP_USING_SPI7
#ifndef SPI7_BUS_CONFIG
#define SPI7_BUS_CONFIG \
{ \
.SPIx = SPI7, \
.bus_name = "spi7", \
.irq_type = SPI7_IRQn, \
}
#endif /* SPI7_BUS_CONFIG */
#endif /* BSP_USING_SPI7 */
#ifdef BSP_SPI7_TX_USING_DMA
#ifndef SPI7_TX_DMA_CONFIG
#define SPI7_TX_DMA_CONFIG \
{ \
.Instance = SPI7_TX_DMA_INSTANCE, \
.dma_irq = SPI7_TX_DMA_IRQ, \
.HsInterface = SPI7_TX_DMA_HANDSHAK, \
.dma_rcc = SPI7_TX_DMA_DMA_RCC, \
.dma_channel = SPI7_TX_DMA_DMA_CHANNEL, \
.dmamux_channel = SPI7_TX_DMA_DMAMUX_CHANNEL, \
.dmamux_request = SPI7_TX_DMA_DMAMUX_REQUEST, \
}
#endif /* SPI7_TX_DMA_CONFIG */
#endif /* BSP_SPI7_TX_USING_DMA */
#ifdef BSP_SPI7_RX_USING_DMA
#ifndef SPI7_RX_DMA_CONFIG
#define SPI7_RX_DMA_CONFIG \
{ \
.Instance = SPI7_RX_DMA_INSTANCE, \
.dma_irq = SPI7_RX_DMA_IRQ, \
.HsInterface = SPI7_RX_DMA_HANDSHAK, \
.dma_rcc = SPI7_RX_DMA_DMA_RCC, \
.dma_channel = SPI7_RX_DMA_DMA_CHANNEL, \
.dmamux_channel = SPI7_RX_DMA_DMAMUX_CHANNEL, \
.dmamux_request = SPI7_RX_DMA_DMAMUX_REQUEST, \
}
#endif /* SPI7_RX_DMA_CONFIG */
#endif /* BSP_SPI7_RX_USING_DMA */
#ifdef __cplusplus
}
#endif
#endif /*__SPI_CONFIG_H__ */

832
bsp/n32/n32hxxx/libraries/N32_Drivers/drivers/config/h7/uart_config.h
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@ -1,832 +0,0 @@
/*
* Copyright (c) 2006-2025, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2026-01-24 ox-horse first version
*/
#ifndef __UART_CONFIG_H__
#define __UART_CONFIG_H__
#include <rtthread.h>
#ifdef __cplusplus
extern "C" {
#endif
#if defined(BSP_USING_UART1)
#ifndef UART1_CONFIG
#define UART1_CONFIG \
{ \
.name = "uart1", \
.Instance = USART1, \
.irq_type = USART1_IRQn, \
.periph = RCC_APB1_PERIPHEN_M7_USART1, \
.EnablePeriphClk = RCC_EnableAPB1PeriphClk3, \
}
#endif /* UART1_CONFIG */
#endif /* BSP_USING_UART1 */
#if defined(BSP_UART1_RX_USING_DMA)
#if defined(UART1_RX_DMA_INSTANCE)
#ifndef UART1_DMA_RX_CONFIG
#define UART1_DMA_RX_CONFIG \
{ \
.Instance = UART1_RX_DMA_INSTANCE, \
.dma_irq = UART1_RX_DMA_IRQ, \
.HsInterface = UART1_RX_DMA_HANDSHAK, \
.dma_rcc = UART1_RX_DMA_DMA_RCC, \
.dma_channel = UART1_RX_DMA_DMA_CHANNEL, \
.dmamux_channel = UART1_RX_DMA_DMAMUX_CHANNEL, \
.dmamux_request = UART1_RX_DMA_DMAMUX_REQUEST, \
}
#endif /* UART1_DMA_RX_CONFIG */
#else
#error "The DMA resource is not available."
#endif /* UART1_RX_DMA_INSTANCE */
#endif /* BSP_UART1_RX_USING_DMA */
#if defined(BSP_UART1_TX_USING_DMA)
#if defined(UART1_TX_DMA_INSTANCE)
#ifndef UART1_DMA_TX_CONFIG
#define UART1_DMA_TX_CONFIG \
{ \
.Instance = UART1_TX_DMA_INSTANCE, \
.dma_irq = UART1_TX_DMA_IRQ, \
.HsInterface = UART1_TX_DMA_HANDSHAK, \
.dma_rcc = UART1_TX_DMA_DMA_RCC, \
.dma_channel = UART1_TX_DMA_DMA_CHANNEL, \
.dmamux_channel = UART1_TX_DMA_DMAMUX_CHANNEL, \
.dmamux_request = UART1_TX_DMA_DMAMUX_REQUEST, \
}
#endif /* UART1_DMA_TX_CONFIG */
#else
#error "The DMA resource is not available."
#endif /* UART1_TX_DMA_INSTANCE */
#endif /* BSP_UART1_TX_USING_DMA */
#if defined(BSP_USING_UART2)
#ifndef UART2_CONFIG
#define UART2_CONFIG \
{ \
.name = "uart2", \
.Instance = USART2, \
.irq_type = USART2_IRQn, \
.periph = RCC_APB1_PERIPHEN_M7_USART2, \
.EnablePeriphClk = RCC_EnableAPB1PeriphClk3, \
}
#endif /* UART2_CONFIG */
#endif /* BSP_USING_UART2 */
#if defined(BSP_UART2_RX_USING_DMA)
#if defined(UART2_RX_DMA_INSTANCE)
#ifndef UART2_DMA_RX_CONFIG
#define UART2_DMA_RX_CONFIG \
{ \
.Instance = UART2_RX_DMA_INSTANCE, \
.dma_irq = UART2_RX_DMA_IRQ, \
.HsInterface = UART2_RX_DMA_HANDSHAK, \
.dma_rcc = UART2_RX_DMA_DMA_RCC, \
.dma_channel = UART2_RX_DMA_DMA_CHANNEL, \
.dmamux_channel = UART2_RX_DMA_DMAMUX_CHANNEL, \
.dmamux_request = UART2_RX_DMA_DMAMUX_REQUEST, \
}
#endif /* UART2_DMA_RX_CONFIG */
#else
#error "The DMA resource is not available."
#endif /* UART2_RX_DMA_INSTANCE */
#endif /* BSP_UART2_RX_USING_DMA */
#if defined(BSP_UART2_TX_USING_DMA)
#if defined(UART2_TX_DMA_INSTANCE)
#ifndef UART2_DMA_TX_CONFIG
#define UART2_DMA_TX_CONFIG \
{ \
.Instance = UART2_TX_DMA_INSTANCE, \
.dma_irq = UART2_TX_DMA_IRQ, \
.HsInterface = UART2_TX_DMA_HANDSHAK, \
.dma_rcc = UART2_TX_DMA_DMA_RCC, \
.dma_channel = UART2_TX_DMA_DMA_CHANNEL, \
.dmamux_channel = UART2_TX_DMA_DMAMUX_CHANNEL, \
.dmamux_request = UART2_TX_DMA_DMAMUX_REQUEST, \
}
#endif /* UART2_DMA_TX_CONFIG */
#else
#error "The DMA resource is not available."
#endif /* UART2_TX_DMA_INSTANCE */
#endif /* BSP_UART2_TX_USING_DMA */
#if defined(BSP_USING_UART3)
#ifndef UART3_CONFIG
#define UART3_CONFIG \
{ \
.name = "uart3", \
.Instance = USART3, \
.irq_type = USART3_IRQn, \
.periph = RCC_APB1_PERIPHEN_M7_USART3, \
.EnablePeriphClk = RCC_EnableAPB1PeriphClk3, \
}
#endif /* UART3_CONFIG */
#endif /* BSP_USING_UART3 */
#if defined(BSP_UART3_RX_USING_DMA)
#if defined(UART3_RX_DMA_INSTANCE)
#ifndef UART3_DMA_RX_CONFIG
#define UART3_DMA_RX_CONFIG \
{ \
.Instance = UART3_RX_DMA_INSTANCE, \
.dma_irq = UART3_RX_DMA_IRQ, \
.HsInterface = UART3_RX_DMA_HANDSHAK, \
.dma_rcc = UART3_RX_DMA_DMA_RCC, \
.dma_channel = UART3_RX_DMA_DMA_CHANNEL, \
.dmamux_channel = UART3_RX_DMA_DMAMUX_CHANNEL, \
.dmamux_request = UART3_RX_DMA_DMAMUX_REQUEST, \
}
#endif /* UART3_DMA_RX_CONFIG */
#else
#error "The DMA resource is not available."
#endif /* UART3_RX_DMA_INSTANCE */
#endif /* BSP_UART3_RX_USING_DMA */
#if defined(BSP_UART3_TX_USING_DMA)
#if defined(UART3_TX_DMA_INSTANCE)
#ifndef UART3_DMA_TX_CONFIG
#define UART3_DMA_TX_CONFIG \
{ \
.Instance = UART3_TX_DMA_INSTANCE, \
.dma_irq = UART3_TX_DMA_IRQ, \
.HsInterface = UART3_TX_DMA_HANDSHAK, \
.dma_rcc = UART3_TX_DMA_DMA_RCC, \
.dma_channel = UART3_TX_DMA_DMA_CHANNEL, \
.dmamux_channel = UART3_TX_DMA_DMAMUX_CHANNEL, \
.dmamux_request = UART3_TX_DMA_DMAMUX_REQUEST, \
}
#endif /* UART3_DMA_TX_CONFIG */
#else
#error "The DMA resource is not available."
#endif /* UART3_TX_DMA_INSTANCE */
#endif /* BSP_UART3_TX_USING_DMA */
#if defined(BSP_USING_UART4)
#ifndef UART4_CONFIG
#define UART4_CONFIG \
{ \
.name = "uart4", \
.Instance = USART4, \
.irq_type = USART4_IRQn, \
.periph = RCC_APB1_PERIPHEN_M7_USART4, \
.EnablePeriphClk = RCC_EnableAPB1PeriphClk3, \
}
#endif /* UART4_CONFIG */
#endif /* BSP_USING_UART4 */
#if defined(BSP_UART4_RX_USING_DMA)
#if defined(UART4_RX_DMA_INSTANCE)
#ifndef UART4_DMA_RX_CONFIG
#define UART4_DMA_RX_CONFIG \
{ \
.Instance = UART4_RX_DMA_INSTANCE, \
.dma_irq = UART4_RX_DMA_IRQ, \
.HsInterface = UART4_RX_DMA_HANDSHAK, \
.dma_rcc = UART4_RX_DMA_DMA_RCC, \
.dma_channel = UART4_RX_DMA_DMA_CHANNEL, \
.dmamux_channel = UART4_RX_DMA_DMAMUX_CHANNEL, \
.dmamux_request = UART4_RX_DMA_DMAMUX_REQUEST, \
}
#endif /* UART4_DMA_RX_CONFIG */
#else
#error "The DMA resource is not available."
#endif /* UART4_RX_DMA_INSTANCE */
#endif /* BSP_UART4_RX_USING_DMA */
#if defined(BSP_UART4_TX_USING_DMA)
#if defined(UART4_TX_DMA_INSTANCE)
#ifndef UART4_DMA_TX_CONFIG
#define UART4_DMA_TX_CONFIG \
{ \
.Instance = UART4_TX_DMA_INSTANCE, \
.dma_irq = UART4_TX_DMA_IRQ, \
.HsInterface = UART4_TX_DMA_HANDSHAK, \
.dma_rcc = UART4_TX_DMA_DMA_RCC, \
.dma_channel = UART4_TX_DMA_DMA_CHANNEL, \
.dmamux_channel = UART4_TX_DMA_DMAMUX_CHANNEL, \
.dmamux_request = UART4_TX_DMA_DMAMUX_REQUEST, \
}
#endif /* UART4_DMA_TX_CONFIG */
#else
#error "The DMA resource is not available."
#endif /* UART4_TX_DMA_INSTANCE */
#endif /* BSP_UART4_TX_USING_DMA */
#if defined(BSP_USING_UART5)
#ifndef UART5_CONFIG
#define UART5_CONFIG \
{ \
.name = "uart5", \
.Instance = USART5, \
.irq_type = USART5_IRQn, \
.periph = RCC_APB2_PERIPHEN_M7_USART5, \
.EnablePeriphClk = RCC_EnableAPB2PeriphClk3, \
}
#endif /* UART5_CONFIG */
#endif /* BSP_USING_UART5 */
#if defined(BSP_UART5_RX_USING_DMA)
#if defined(UART5_RX_DMA_INSTANCE)
#ifndef UART5_DMA_RX_CONFIG
#define UART5_DMA_RX_CONFIG \
{ \
.Instance = UART5_RX_DMA_INSTANCE, \
.dma_irq = UART5_RX_DMA_IRQ, \
.HsInterface = UART5_RX_DMA_HANDSHAK, \
.dma_rcc = UART5_RX_DMA_DMA_RCC, \
.dma_channel = UART5_RX_DMA_DMA_CHANNEL, \
.dmamux_channel = UART5_RX_DMA_DMAMUX_CHANNEL, \
.dmamux_request = UART5_RX_DMA_DMAMUX_REQUEST, \
}
#endif /* UART5_DMA_RX_CONFIG */
#else
#error "The DMA resource is not available."
#endif /* UART5_RX_DMA_INSTANCE */
#endif /* BSP_UART5_RX_USING_DMA */
#if defined(BSP_UART5_TX_USING_DMA)
#if defined(UART5_TX_DMA_INSTANCE)
#ifndef UART5_DMA_TX_CONFIG
#define UART5_DMA_TX_CONFIG \
{ \
.Instance = UART5_TX_DMA_INSTANCE, \
.dma_irq = UART5_TX_DMA_IRQ, \
.HsInterface = UART5_TX_DMA_HANDSHAK, \
.dma_rcc = UART5_TX_DMA_DMA_RCC, \
.dma_channel = UART5_TX_DMA_DMA_CHANNEL, \
.dmamux_channel = UART5_TX_DMA_DMAMUX_CHANNEL, \
.dmamux_request = UART5_TX_DMA_DMAMUX_REQUEST, \
}
#endif /* UART5_DMA_TX_CONFIG */
#else
#error "The DMA resource is not available."
#endif /* UART5_TX_DMA_INSTANCE */
#endif /* BSP_UART5_TX_USING_DMA */
#if defined(BSP_USING_UART6)
#ifndef UART6_CONFIG
#define UART6_CONFIG \
{ \
.name = "uart6", \
.Instance = USART6, \
.irq_type = USART6_IRQn, \
.periph = RCC_APB2_PERIPHEN_M7_USART6, \
.EnablePeriphClk = RCC_EnableAPB2PeriphClk3, \
}
#endif /* UART6_CONFIG */
#endif /* BSP_USING_UART6 */
#if defined(BSP_UART6_RX_USING_DMA)
#if defined(UART6_RX_DMA_INSTANCE)
#ifndef UART6_DMA_RX_CONFIG
#define UART6_DMA_RX_CONFIG \
{ \
.Instance = UART6_RX_DMA_INSTANCE, \
.dma_irq = UART6_RX_DMA_IRQ, \
.HsInterface = UART6_RX_DMA_HANDSHAK, \
.dma_rcc = UART6_RX_DMA_DMA_RCC, \
.dma_channel = UART6_RX_DMA_DMA_CHANNEL, \
.dmamux_channel = UART6_RX_DMA_DMAMUX_CHANNEL, \
.dmamux_request = UART6_RX_DMA_DMAMUX_REQUEST, \
}
#endif /* UART6_DMA_RX_CONFIG */
#else
#error "The DMA resource is not available."
#endif /* UART6_RX_DMA_INSTANCE */
#endif /* BSP_UART6_RX_USING_DMA */
#if defined(BSP_UART6_TX_USING_DMA)
#if defined(UART6_TX_DMA_INSTANCE)
#ifndef UART6_DMA_TX_CONFIG
#define UART6_DMA_TX_CONFIG \
{ \
.Instance = UART6_TX_DMA_INSTANCE, \
.dma_irq = UART6_TX_DMA_IRQ, \
.HsInterface = UART6_TX_DMA_HANDSHAK, \
.dma_rcc = UART6_TX_DMA_DMA_RCC, \
.dma_channel = UART6_TX_DMA_DMA_CHANNEL, \
.dmamux_channel = UART6_TX_DMA_DMAMUX_CHANNEL, \
.dmamux_request = UART6_TX_DMA_DMAMUX_REQUEST, \
}
#endif /* UART6_DMA_TX_CONFIG */
#else
#error "The DMA resource is not available."
#endif /* UART6_TX_DMA_INSTANCE */
#endif /* BSP_UART6_TX_USING_DMA */
#if defined(BSP_USING_UART7)
#ifndef UART7_CONFIG
#define UART7_CONFIG \
{ \
.name = "uart7", \
.Instance = USART7, \
.irq_type = USART7_IRQn, \
.periph = RCC_APB2_PERIPHEN_M7_USART7, \
.EnablePeriphClk = RCC_EnableAPB2PeriphClk3, \
}
#endif /* UART7_CONFIG */
#endif /* BSP_USING_UART7 */
#if defined(BSP_UART7_RX_USING_DMA)
#if defined(UART7_RX_DMA_INSTANCE)
#ifndef UART7_DMA_RX_CONFIG
#define UART7_DMA_RX_CONFIG \
{ \
.Instance = UART7_RX_DMA_INSTANCE, \
.dma_irq = UART7_RX_DMA_IRQ, \
.HsInterface = UART7_RX_DMA_HANDSHAK, \
.dma_rcc = UART7_RX_DMA_DMA_RCC, \
.dma_channel = UART7_RX_DMA_DMA_CHANNEL, \
.dmamux_channel = UART7_RX_DMA_DMAMUX_CHANNEL, \
.dmamux_request = UART7_RX_DMA_DMAMUX_REQUEST, \
}
#endif /* UART7_DMA_RX_CONFIG */
#else
#error "The DMA resource is not available."
#endif /* UART7_RX_DMA_INSTANCE */
#endif /* BSP_UART7_RX_USING_DMA */
#if defined(BSP_UART7_TX_USING_DMA)
#if defined(UART7_TX_DMA_INSTANCE)
#ifndef UART7_DMA_TX_CONFIG
#define UART7_DMA_TX_CONFIG \
{ \
.Instance = UART7_TX_DMA_INSTANCE, \
.dma_irq = UART7_TX_DMA_IRQ, \
.HsInterface = UART7_TX_DMA_HANDSHAK, \
.dma_rcc = UART7_TX_DMA_DMA_RCC, \
.dma_channel = UART7_TX_DMA_DMA_CHANNEL, \
.dmamux_channel = UART7_TX_DMA_DMAMUX_CHANNEL, \
.dmamux_request = UART7_TX_DMA_DMAMUX_REQUEST, \
}
#endif /* UART7_DMA_TX_CONFIG */
#else
#error "The DMA resource is not available."
#endif /* UART7_TX_DMA_INSTANCE */
#endif /* BSP_UART7_TX_USING_DMA */
#if defined(BSP_USING_UART8)
#ifndef UART8_CONFIG
#define UART8_CONFIG \
{ \
.name = "uart8", \
.Instance = USART8, \
.irq_type = USART8_IRQn, \
.periph = RCC_APB2_PERIPHEN_M7_USART8, \
.EnablePeriphClk = RCC_EnableAPB2PeriphClk3, \
}
#endif /* UART8_CONFIG */
#endif /* BSP_USING_UART8 */
#if defined(BSP_UART8_RX_USING_DMA)
#if defined(UART8_RX_DMA_INSTANCE)
#ifndef UART8_DMA_RX_CONFIG
#define UART8_DMA_RX_CONFIG \
{ \
.Instance = UART8_RX_DMA_INSTANCE, \
.dma_irq = UART8_RX_DMA_IRQ, \
.HsInterface = UART8_RX_DMA_HANDSHAK, \
.dma_rcc = UART8_RX_DMA_DMA_RCC, \
.dma_channel = UART8_RX_DMA_DMA_CHANNEL, \
.dmamux_channel = UART8_RX_DMA_DMAMUX_CHANNEL, \
.dmamux_request = UART8_RX_DMA_DMAMUX_REQUEST, \
}
#endif /* UART8_DMA_RX_CONFIG */
#else
#error "The DMA resource is not available."
#endif /* UART8_RX_DMA_INSTANCE */
#endif /* BSP_UART8_RX_USING_DMA */
#if defined(BSP_UART8_TX_USING_DMA)
#if defined(UART8_TX_DMA_INSTANCE)
#ifndef UART8_DMA_TX_CONFIG
#define UART8_DMA_TX_CONFIG \
{ \
.Instance = UART8_TX_DMA_INSTANCE, \
.dma_irq = UART8_TX_DMA_IRQ, \
.HsInterface = UART8_TX_DMA_HANDSHAK, \
.dma_rcc = UART8_TX_DMA_DMA_RCC, \
.dma_channel = UART8_TX_DMA_DMA_CHANNEL, \
.dmamux_channel = UART8_TX_DMA_DMAMUX_CHANNEL, \
.dmamux_request = UART8_TX_DMA_DMAMUX_REQUEST, \
}
#endif /* UART8_DMA_TX_CONFIG */
#else
#error "The DMA resource is not available."
#endif /* UART8_TX_DMA_INSTANCE */
#endif /* BSP_UART8_TX_USING_DMA */
#if defined(BSP_USING_UART9)
#ifndef UART9_CONFIG
#define UART9_CONFIG \
{ \
.name = "uart9", \
.Instance = UART9, \
.irq_type = UART9_IRQn, \
.periph = RCC_APB1_PERIPHEN_M7_UART9, \
.EnablePeriphClk = RCC_EnableAPB1PeriphClk3, \
}
#endif /* UART9_CONFIG */
#endif /* BSP_USING_UART9 */
#if defined(BSP_UART9_RX_USING_DMA)
#if defined(UART9_RX_DMA_INSTANCE)
#ifndef UART9_DMA_RX_CONFIG
#define UART9_DMA_RX_CONFIG \
{ \
.Instance = UART9_RX_DMA_INSTANCE, \
.dma_irq = UART9_RX_DMA_IRQ, \
.HsInterface = UART9_RX_DMA_HANDSHAK, \
.dma_rcc = UART9_RX_DMA_DMA_RCC, \
.dma_channel = UART9_RX_DMA_DMA_CHANNEL, \
.dmamux_channel = UART9_RX_DMA_DMAMUX_CHANNEL, \
.dmamux_request = UART9_RX_DMA_DMAMUX_REQUEST, \
}
#endif /* UART9_DMA_RX_CONFIG */
#else
#error "The DMA resource is not available."
#endif /* UART9_RX_DMA_INSTANCE */
#endif /* BSP_UART9_RX_USING_DMA */
#if defined(BSP_UART9_TX_USING_DMA)
#if defined(UART9_TX_DMA_INSTANCE)
#ifndef UART9_DMA_TX_CONFIG
#define UART9_DMA_TX_CONFIG \
{ \
.Instance = UART9_TX_DMA_INSTANCE, \
.dma_irq = UART9_TX_DMA_IRQ, \
.HsInterface = UART9_TX_DMA_HANDSHAK, \
.dma_rcc = UART9_TX_DMA_DMA_RCC, \
.dma_channel = UART9_TX_DMA_DMA_CHANNEL, \
.dmamux_channel = UART9_TX_DMA_DMAMUX_CHANNEL, \
.dmamux_request = UART9_TX_DMA_DMAMUX_REQUEST, \
}
#endif /* UART9_DMA_TX_CONFIG */
#else
#error "The DMA resource is not available."
#endif /* UART9_TX_DMA_INSTANCE */
#endif /* BSP_UART9_TX_USING_DMA */
#if defined(BSP_USING_UART10)
#ifndef UART10_CONFIG
#define UART10_CONFIG \
{ \
.name = "uart10", \
.Instance = UART10, \
.irq_type = UART10_IRQn, \
.periph = RCC_APB1_PERIPHEN_M7_UART10, \
.EnablePeriphClk = RCC_EnableAPB1PeriphClk3, \
}
#endif /* UART10_CONFIG */
#endif /* BSP_USING_UART10 */
#if defined(BSP_UART10_RX_USING_DMA)
#if defined(UART10_RX_DMA_INSTANCE)
#ifndef UART10_DMA_RX_CONFIG
#define UART10_DMA_RX_CONFIG \
{ \
.Instance = UART10_RX_DMA_INSTANCE, \
.dma_irq = UART10_RX_DMA_IRQ, \
.HsInterface = UART10_RX_DMA_HANDSHAK, \
.dma_rcc = UART10_RX_DMA_DMA_RCC, \
.dma_channel = UART10_RX_DMA_DMA_CHANNEL, \
.dmamux_channel = UART10_RX_DMA_DMAMUX_CHANNEL, \
.dmamux_request = UART10_RX_DMA_DMAMUX_REQUEST, \
}
#endif /* UART10_DMA_RX_CONFIG */
#else
#error "The DMA resource is not available."
#endif /* UART10_RX_DMA_INSTANCE */
#endif /* BSP_UART10_RX_USING_DMA */
#if defined(BSP_UART10_TX_USING_DMA)
#if defined(UART10_TX_DMA_INSTANCE)
#ifndef UART10_DMA_TX_CONFIG
#define UART10_DMA_TX_CONFIG \
{ \
.Instance = UART10_TX_DMA_INSTANCE, \
.dma_irq = UART10_TX_DMA_IRQ, \
.HsInterface = UART10_TX_DMA_HANDSHAK, \
.dma_rcc = UART10_TX_DMA_DMA_RCC, \
.dma_channel = UART10_TX_DMA_DMA_CHANNEL, \
.dmamux_channel = UART10_TX_DMA_DMAMUX_CHANNEL, \
.dmamux_request = UART10_TX_DMA_DMAMUX_REQUEST, \
}
#endif /* UART10_DMA_TX_CONFIG */
#else
#error "The DMA resource is not available."
#endif /* UART10_TX_DMA_INSTANCE */
#endif /* BSP_UART10_TX_USING_DMA */
#if defined(BSP_USING_UART11)
#ifndef UART11_CONFIG
#define UART11_CONFIG \
{ \
.name = "uart11", \
.Instance = UART11, \
.irq_type = UART11_IRQn, \
.periph = RCC_APB1_PERIPHEN_M7_UART11, \
.EnablePeriphClk = RCC_EnableAPB1PeriphClk3, \
}
#endif /* UART11_CONFIG */
#endif /* BSP_USING_UART11 */
#if defined(BSP_UART11_RX_USING_DMA)
#if defined(UART11_RX_DMA_INSTANCE)
#ifndef UART11_DMA_RX_CONFIG
#define UART11_DMA_RX_CONFIG \
{ \
.Instance = UART11_RX_DMA_INSTANCE, \
.dma_irq = UART11_RX_DMA_IRQ, \
.HsInterface = UART11_RX_DMA_HANDSHAK, \
.dma_rcc = UART11_RX_DMA_DMA_RCC, \
.dma_channel = UART11_RX_DMA_DMA_CHANNEL, \
.dmamux_channel = UART11_RX_DMA_DMAMUX_CHANNEL, \
.dmamux_request = UART11_RX_DMA_DMAMUX_REQUEST, \
}
#endif /* UART11_DMA_RX_CONFIG */
#else
#error "The DMA resource is not available."
#endif /* UART11_RX_DMA_INSTANCE */
#endif /* BSP_UART11_RX_USING_DMA */
#if defined(BSP_UART11_TX_USING_DMA)
#if defined(UART11_TX_DMA_INSTANCE)
#ifndef UART11_DMA_TX_CONFIG
#define UART11_DMA_TX_CONFIG \
{ \
.Instance = UART11_TX_DMA_INSTANCE, \
.dma_irq = UART11_TX_DMA_IRQ, \
.HsInterface = UART11_TX_DMA_HANDSHAK, \
.dma_rcc = UART11_TX_DMA_DMA_RCC, \
.dma_channel = UART11_TX_DMA_DMA_CHANNEL, \
.dmamux_channel = UART11_TX_DMA_DMAMUX_CHANNEL, \
.dmamux_request = UART11_TX_DMA_DMAMUX_REQUEST, \
}
#endif /* UART11_DMA_TX_CONFIG */
#else
#error "The DMA resource is not available."
#endif /* UART11_TX_DMA_INSTANCE */
#endif /* BSP_UART11_TX_USING_DMA */
#if defined(BSP_USING_UART12)
#ifndef UART12_CONFIG
#define UART12_CONFIG \
{ \
.name = "uart12", \
.Instance = UART12, \
.irq_type = UART12_IRQn, \
.periph = RCC_APB1_PERIPHEN_M7_UART12, \
.EnablePeriphClk = RCC_EnableAPB1PeriphClk3, \
}
#endif /* UART12_CONFIG */
#endif /* BSP_USING_UART12 */
#if defined(BSP_UART12_RX_USING_DMA)
#if defined(UART12_RX_DMA_INSTANCE)
#ifndef UART12_DMA_RX_CONFIG
#define UART12_DMA_RX_CONFIG \
{ \
.Instance = UART12_RX_DMA_INSTANCE, \
.dma_irq = UART12_RX_DMA_IRQ, \
.HsInterface = UART12_RX_DMA_HANDSHAK, \
.dma_rcc = UART12_RX_DMA_DMA_RCC, \
.dma_channel = UART12_RX_DMA_DMA_CHANNEL, \
.dmamux_channel = UART12_RX_DMA_DMAMUX_CHANNEL, \
.dmamux_request = UART12_RX_DMA_DMAMUX_REQUEST, \
}
#endif /* UART12_DMA_RX_CONFIG */
#else
#error "The DMA resource is not available."
#endif /* UART12_RX_DMA_INSTANCE */
#endif /* BSP_UART12_RX_USING_DMA */
#if defined(BSP_UART12_TX_USING_DMA)
#if defined(UART12_TX_DMA_INSTANCE)
#ifndef UART12_DMA_TX_CONFIG
#define UART12_DMA_TX_CONFIG \
{ \
.Instance = UART12_TX_DMA_INSTANCE, \
.dma_irq = UART12_TX_DMA_IRQ, \
.HsInterface = UART12_TX_DMA_HANDSHAK, \
.dma_rcc = UART12_TX_DMA_DMA_RCC, \
.dma_channel = UART12_TX_DMA_DMA_CHANNEL, \
.dmamux_channel = UART12_TX_DMA_DMAMUX_CHANNEL, \
.dmamux_request = UART12_TX_DMA_DMAMUX_REQUEST, \
}
#endif /* UART12_DMA_TX_CONFIG */
#else
#error "The DMA resource is not available."
#endif /* UART12_TX_DMA_INSTANCE */
#endif /* BSP_UART12_TX_USING_DMA */
#if defined(BSP_USING_UART13)
#ifndef UART13_CONFIG
#define UART13_CONFIG \
{ \
.name = "uart13", \
.Instance = UART13, \
.irq_type = UART13_IRQn, \
.periph = RCC_APB2_PERIPHEN_M7_UART13, \
.EnablePeriphClk = RCC_EnableAPB2PeriphClk3, \
}
#endif /* UART13_CONFIG */
#endif /* BSP_USING_UART13 */
#if defined(BSP_UART13_RX_USING_DMA)
#if defined(UART13_RX_DMA_INSTANCE)
#ifndef UART13_DMA_RX_CONFIG
#define UART13_DMA_RX_CONFIG \
{ \
.Instance = UART13_RX_DMA_INSTANCE, \
.dma_irq = UART13_RX_DMA_IRQ, \
.HsInterface = UART13_RX_DMA_HANDSHAK, \
.dma_rcc = UART13_RX_DMA_DMA_RCC, \
.dma_channel = UART13_RX_DMA_DMA_CHANNEL, \
.dmamux_channel = UART13_RX_DMA_DMAMUX_CHANNEL, \
.dmamux_request = UART13_RX_DMA_DMAMUX_REQUEST, \
}
#endif /* UART13_DMA_RX_CONFIG */
#else
#error "The DMA resource is not available."
#endif /* UART13_RX_DMA_INSTANCE */
#endif /* BSP_UART13_RX_USING_DMA */
#if defined(BSP_UART13_TX_USING_DMA)
#if defined(UART13_TX_DMA_INSTANCE)
#ifndef UART13_DMA_TX_CONFIG
#define UART13_DMA_TX_CONFIG \
{ \
.Instance = UART13_TX_DMA_INSTANCE, \
.dma_irq = UART13_TX_DMA_IRQ, \
.HsInterface = UART13_TX_DMA_HANDSHAK, \
.dma_rcc = UART13_TX_DMA_DMA_RCC, \
.dma_channel = UART13_TX_DMA_DMA_CHANNEL, \
.dmamux_channel = UART13_TX_DMA_DMAMUX_CHANNEL, \
.dmamux_request = UART13_TX_DMA_DMAMUX_REQUEST, \
}
#endif /* UART13_DMA_TX_CONFIG */
#else
#error "The DMA resource is not available."
#endif /* UART13_TX_DMA_INSTANCE */
#endif /* BSP_UART13_TX_USING_DMA */
#if defined(BSP_USING_UART14)
#ifndef UART14_CONFIG
#define UART14_CONFIG \
{ \
.name = "uart14", \
.Instance = UART14, \
.irq_type = UART14_IRQn, \
.periph = RCC_APB2_PERIPHEN_M7_UART14, \
.EnablePeriphClk = RCC_EnableAPB2PeriphClk3, \
}
#endif /* UART14_CONFIG */
#endif /* BSP_USING_UART14 */
#if defined(BSP_UART14_RX_USING_DMA)
#if defined(UART14_RX_DMA_INSTANCE)
#ifndef UART14_DMA_RX_CONFIG
#define UART14_DMA_RX_CONFIG \
{ \
.Instance = UART14_RX_DMA_INSTANCE, \
.dma_irq = UART14_RX_DMA_IRQ, \
.HsInterface = UART14_RX_DMA_HANDSHAK, \
.dma_rcc = UART14_RX_DMA_DMA_RCC, \
.dma_channel = UART14_RX_DMA_DMA_CHANNEL, \
.dmamux_channel = UART14_RX_DMA_DMAMUX_CHANNEL, \
.dmamux_request = UART14_RX_DMA_DMAMUX_REQUEST, \
}
#endif /* UART14_DMA_RX_CONFIG */
#else
#error "The DMA resource is not available."
#endif /* UART14_RX_DMA_INSTANCE */
#endif /* BSP_UART14_RX_USING_DMA */
#if defined(BSP_UART14_TX_USING_DMA)
#if defined(UART14_TX_DMA_INSTANCE)
#ifndef UART14_DMA_TX_CONFIG
#define UART14_DMA_TX_CONFIG \
{ \
.Instance = UART14_TX_DMA_INSTANCE, \
.dma_irq = UART14_TX_DMA_IRQ, \
.HsInterface = UART14_TX_DMA_HANDSHAK, \
.dma_rcc = UART14_TX_DMA_DMA_RCC, \
.dma_channel = UART14_TX_DMA_DMA_CHANNEL, \
.dmamux_channel = UART14_TX_DMA_DMAMUX_CHANNEL, \
.dmamux_request = UART14_TX_DMA_DMAMUX_REQUEST, \
}
#endif /* UART14_DMA_TX_CONFIG */
#else
#error "The DMA resource is not available."
#endif /* UART14_TX_DMA_INSTANCE */
#endif /* BSP_UART14_TX_USING_DMA */
#if defined(BSP_USING_UART15)
#ifndef UART15_CONFIG
#define UART15_CONFIG \
{ \
.name = "uart15", \
.Instance = UART15, \
.irq_type = UART15_IRQn, \
.periph = RCC_APB2_PERIPHEN_M7_UART15, \
.EnablePeriphClk = RCC_EnableAPB2PeriphClk3, \
}
#endif /* UART15_CONFIG */
#endif /* BSP_USING_UART15 */
#if defined(BSP_UART15_RX_USING_DMA)
#if defined(UART15_RX_DMA_INSTANCE)
#ifndef UART15_DMA_RX_CONFIG
#define UART15_DMA_RX_CONFIG \
{ \
.Instance = UART15_RX_DMA_INSTANCE, \
.dma_irq = UART15_RX_DMA_IRQ, \
.HsInterface = UART15_RX_DMA_HANDSHAK, \
.dma_rcc = UART15_RX_DMA_DMA_RCC, \
.dma_channel = UART15_RX_DMA_DMA_CHANNEL, \
.dmamux_channel = UART15_RX_DMA_DMAMUX_CHANNEL, \
.dmamux_request = UART15_RX_DMA_DMAMUX_REQUEST, \
}
#endif /* UART15_DMA_RX_CONFIG */
#else
#error "The DMA resource is not available."
#endif /* UART15_RX_DMA_INSTANCE */
#endif /* BSP_UART15_RX_USING_DMA */
#if defined(BSP_UART15_TX_USING_DMA)
#if defined(UART15_TX_DMA_INSTANCE)
#ifndef UART15_DMA_TX_CONFIG
#define UART15_DMA_TX_CONFIG \
{ \
.Instance = UART15_TX_DMA_INSTANCE, \
.dma_irq = UART15_TX_DMA_IRQ, \
.HsInterface = UART15_TX_DMA_HANDSHAK, \
.dma_rcc = UART15_TX_DMA_DMA_RCC, \
.dma_channel = UART15_TX_DMA_DMA_CHANNEL, \
.dmamux_channel = UART15_TX_DMA_DMAMUX_CHANNEL, \
.dmamux_request = UART15_TX_DMA_DMAMUX_REQUEST, \
}
#endif /* UART15_DMA_TX_CONFIG */
#else
#error "The DMA resource is not available."
#endif /* UART15_TX_DMA_INSTANCE */
#endif /* BSP_UART15_TX_USING_DMA */
#if defined(BSP_USING_LPUART1)
#ifndef LPUART1_CONFIG
#define LPUART1_CONFIG \
{ \
.name = "lpuart1", \
.Instance = LPUART1, \
.irq_type = LPUART1_IRQn, \
.periph = RCC_RD_PERIPHEN_M7_LPUART1, \
.EnablePeriphClk = RCC_EnableRDPeriphClk1, \
}
#endif /* LPUART1_CONFIG */
#endif /* BSP_USING_LPUART1 */
#if defined(BSP_LPUART1_RX_USING_DMA)
#ifndef LPUART1_DMA_RX_CONFIG
#define LPUART1_DMA_RX_CONFIG \
{ \
.Instance = LPUART1_RX_DMA_INSTANCE, \
.dma_irq = LPUART1_RX_DMA_IRQ, \
.HsInterface = LPUART1_RX_DMA_HANDSHAK, \
.dma_rcc = LPUART1_RX_DMA_DMA_RCC, \
.dma_channel = LPUART1_RX_DMA_DMA_CHANNEL, \
.dmamux_channel = LPUART1_RX_DMA_DMAMUX_CHANNEL, \
.dmamux_request = LPUART1_RX_DMA_DMAMUX_REQUEST, \
}
#endif /* LPUART1_DMA_RX_CONFIG */
#endif /* BSP_LPUART1_RX_USING_DMA */
#if defined(BSP_USING_LPUART2)
#ifndef LPUART2_CONFIG
#define LPUART2_CONFIG \
{ \
.name = "lpuart2", \
.Instance = LPUART2, \
.irq_type = LPUART2_IRQn, \
.periph = RCC_RD_PERIPHEN_M7_LPUART2, \
.EnablePeriphClk = RCC_EnableRDPeriphClk1, \
}
#endif /* LPUART2_CONFIG */
#endif /* BSP_USING_LPUART2 */
#if defined(BSP_LPUART2_RX_USING_DMA)
#ifndef LPUART2_DMA_RX_CONFIG
#define LPUART2_DMA_RX_CONFIG \
{ \
.Instance = LPUART2_RX_DMA_INSTANCE, \
.dma_irq = LPUART2_RX_DMA_IRQ, \
.HsInterface = LPUART2_RX_DMA_HANDSHAK, \
.dma_rcc = LPUART2_RX_DMA_DMA_RCC, \
.dma_channel = LPUART2_RX_DMA_DMA_CHANNEL, \
.dmamux_channel = LPUART2_RX_DMA_DMAMUX_CHANNEL, \
.dmamux_request = LPUART2_RX_DMA_DMAMUX_REQUEST, \
}
#endif /* LPUART2_DMA_RX_CONFIG */
#endif /* BSP_LPUART2_RX_USING_DMA */
#ifdef __cplusplus
}
#endif
#endif /* __UART_CONFIG_H__ */

108
bsp/n32/n32hxxx/libraries/N32_Drivers/drivers/config/h7/adc_config.h → bsp/n32/n32hxxx/libraries/N32_Drivers/drivers/config/h7xx/adc_config.h
View File

@ -19,72 +19,72 @@ extern "C" {
#ifdef BSP_USING_ADC1
#ifndef ADC1_CONFIG
#define ADC1_CONFIG \
{ \
.ADCx = ADC1, \
.AHB_periph = (RCC_AHB1_PERIPHEN_M7_ADC1SYS | RCC_AHB1_PERIPHEN_M7_ADC1BUS), \
.EnablePeriphClk = RCC_EnableAHB1PeriphClk1, \
.ADC_ClkMode = ADC_CTRL3_CKMOD_AHB, \
.Pll_CLK_source = RCC_ADCPLLCLK_SRC_PLL1B, \
.RCC_ADCPrescaler = RCC_AHB1DIV2_ADC1SYSDIV_DIV15, \
.Init.WorkMode = ADC_WORKMODE_INDEPENDENT, \
.Init.MultiChEn = DISABLE, \
.Init.ContinueConvEn = DISABLE, \
.Init.ExtTrigSelect = ADC_EXT_TRIG_REG_CONV_SOFTWARE, \
.Init.DataTransferMode = ADC_REG_DR_TRANSFER, \
.Init.DatAlign = ADC_DAT_ALIGN_R, \
.Init.ChsNumber = 1U, \
.Init.Resolution = ADC_DATA_RES_12BIT, \
.Rank = 1U, \
.ADC_SampleTime = ADC_SAMP_TIME_CYCLES_24, \
#define ADC1_CONFIG \
{ \
.ADCx = ADC1, \
.AHB_periph = (RCC_AHB1_PERIPHEN_M7_ADC1SYS | RCC_AHB1_PERIPHEN_M7_ADC1BUS), \
.EnablePeriphClk = RCC_EnableAHB1PeriphClk1, \
.ADC_ClkMode = ADC_CTRL3_CKMOD_AHB, \
.Pll_CLK_source = RCC_ADCPLLCLK_SRC_PLL1B, \
.RCC_ADCPrescaler = RCC_AHB1DIV2_ADC1SYSDIV_DIV15, \
.Init.WorkMode = ADC_WORKMODE_INDEPENDENT, \
.Init.MultiChEn = DISABLE, \
.Init.ContinueConvEn = DISABLE, \
.Init.ExtTrigSelect = ADC_EXT_TRIG_REG_CONV_SOFTWARE, \
.Init.DataTransferMode = ADC_REG_DR_TRANSFER, \
.Init.DatAlign = ADC_DAT_ALIGN_R, \
.Init.ChsNumber = 1U, \
.Init.Resolution = ADC_DATA_RES_12BIT, \
.Rank = 1U, \
.ADC_SampleTime = ADC_SAMP_TIME_CYCLES_24, \
}
#endif /* ADC1_CONFIG */
#endif /* BSP_USING_ADC1 */
#ifdef BSP_USING_ADC2
#ifndef ADC2_CONFIG
#define ADC2_CONFIG \
{ \
.ADCx = ADC2, \
.AHB_periph = (RCC_AHB1_PERIPHEN_M7_ADC2SYS | RCC_AHB1_PERIPHEN_M7_ADC2BUS), \
.EnablePeriphClk = RCC_EnableAHB1PeriphClk4, \
.ADC_ClkMode = ADC_CTRL3_CKMOD_AHB, \
.Pll_CLK_source = RCC_ADCPLLCLK_SRC_PLL1B, \
.RCC_ADCPrescaler = RCC_AHB1DIV2_ADC1SYSDIV_DIV15, \
.Init.WorkMode = ADC_WORKMODE_INDEPENDENT, \
.Init.MultiChEn = DISABLE, \
.Init.ContinueConvEn = DISABLE, \
.Init.ExtTrigSelect = ADC_EXT_TRIG_REG_CONV_SOFTWARE, \
.Init.DataTransferMode = ADC_REG_DR_TRANSFER, \
.Init.DatAlign = ADC_DAT_ALIGN_R, \
.Init.ChsNumber = 1U, \
.Init.Resolution = ADC_DATA_RES_12BIT, \
.Rank = 1U, \
.ADC_SampleTime = ADC_SAMP_TIME_CYCLES_24, \
#define ADC2_CONFIG \
{ \
.ADCx = ADC2, \
.AHB_periph = (RCC_AHB1_PERIPHEN_M7_ADC2SYS | RCC_AHB1_PERIPHEN_M7_ADC2BUS), \
.EnablePeriphClk = RCC_EnableAHB1PeriphClk4, \
.ADC_ClkMode = ADC_CTRL3_CKMOD_AHB, \
.Pll_CLK_source = RCC_ADCPLLCLK_SRC_PLL1B, \
.RCC_ADCPrescaler = RCC_AHB1DIV2_ADC1SYSDIV_DIV15, \
.Init.WorkMode = ADC_WORKMODE_INDEPENDENT, \
.Init.MultiChEn = DISABLE, \
.Init.ContinueConvEn = DISABLE, \
.Init.ExtTrigSelect = ADC_EXT_TRIG_REG_CONV_SOFTWARE, \
.Init.DataTransferMode = ADC_REG_DR_TRANSFER, \
.Init.DatAlign = ADC_DAT_ALIGN_R, \
.Init.ChsNumber = 1U, \
.Init.Resolution = ADC_DATA_RES_12BIT, \
.Rank = 1U, \
.ADC_SampleTime = ADC_SAMP_TIME_CYCLES_24, \
}
#endif /* ADC2_CONFIG */
#endif /* BSP_USING_ADC2 */
#ifdef BSP_USING_ADC3
#ifndef ADC3_CONFIG
#define ADC3_CONFIG \
{ \
.ADCx = ADC3, \
.AHB_periph = (RCC_AHB1_PERIPHEN_M7_ADC3SYS | RCC_AHB1_PERIPHEN_M7_ADC3BUS), \
.EnablePeriphClk = RCC_EnableAHB1PeriphClk4, \
.ADC_ClkMode = ADC_CTRL3_CKMOD_AHB, \
.Pll_CLK_source = RCC_ADCPLLCLK_SRC_PLL1B, \
.RCC_ADCPrescaler = RCC_AHB1DIV2_ADC1SYSDIV_DIV15, \
.Init.WorkMode = ADC_WORKMODE_INDEPENDENT, \
.Init.MultiChEn = DISABLE, \
.Init.ContinueConvEn = DISABLE, \
.Init.ExtTrigSelect = ADC_EXT_TRIG_REG_CONV_SOFTWARE, \
.Init.DataTransferMode = ADC_REG_DR_TRANSFER, \
.Init.DatAlign = ADC_DAT_ALIGN_R, \
.Init.ChsNumber = 1U, \
.Init.Resolution = ADC_DATA_RES_12BIT, \
.Rank = 1U, \
.ADC_SampleTime = ADC_SAMP_TIME_CYCLES_24, \
#define ADC3_CONFIG \
{ \
.ADCx = ADC3, \
.AHB_periph = (RCC_AHB1_PERIPHEN_M7_ADC3SYS | RCC_AHB1_PERIPHEN_M7_ADC3BUS), \
.EnablePeriphClk = RCC_EnableAHB1PeriphClk4, \
.ADC_ClkMode = ADC_CTRL3_CKMOD_AHB, \
.Pll_CLK_source = RCC_ADCPLLCLK_SRC_PLL1B, \
.RCC_ADCPrescaler = RCC_AHB1DIV2_ADC1SYSDIV_DIV15, \
.Init.WorkMode = ADC_WORKMODE_INDEPENDENT, \
.Init.MultiChEn = DISABLE, \
.Init.ContinueConvEn = DISABLE, \
.Init.ExtTrigSelect = ADC_EXT_TRIG_REG_CONV_SOFTWARE, \
.Init.DataTransferMode = ADC_REG_DR_TRANSFER, \
.Init.DatAlign = ADC_DAT_ALIGN_R, \
.Init.ChsNumber = 1U, \
.Init.Resolution = ADC_DATA_RES_12BIT, \
.Rank = 1U, \
.ADC_SampleTime = ADC_SAMP_TIME_CYCLES_24, \
}
#endif /* ADC3_CONFIG */
#endif /* BSP_USING_ADC3 */

126
bsp/n32/n32hxxx/libraries/N32_Drivers/drivers/config/h7xx/can_config.h Normal file
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@ -0,0 +1,126 @@
/*
* Copyright (c) 2006-2026, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2026-06-22 lin.qi first version
*/
#ifndef __CAN_CONFIG_H__
#define __CAN_CONFIG_H__
#include <rtthread.h>
#include "n32h7xx_fdcan.h"
#ifdef __cplusplus
extern "C" {
#endif
/**
*\*\name n32_fdcan_config.
*\*\brief FDCAN instance configuration structure.
*\*\note Clock and GPIO initialization are handled by CubeMX-generated code
*\*\ in n32h7xx_cfg.c (from Cube.ntfx). NVIC interrupt vector numbers
*\*\ are hardcoded in drv_fdcan.c per instance.
*/
struct n32_fdcan_config
{
const char *name; /**< device name */
FDCAN_Module *Instance; /**< FDCAN peripheral base address */
};
/*
* Hardware connection pairs on N32H760ZIL7-STB:
* FDCAN1 <-> FDCAN2
* FDCAN3 <-> FDCAN4
* FDCAN5 <-> FDCAN6
* FDCAN7 <-> FDCAN8
*/
#if defined(BSP_USING_FDCAN1)
#ifndef FDCAN1_CONFIG
#define FDCAN1_CONFIG \
{ \
.name = "fdcan1", \
.Instance = FDCAN1, \
}
#endif
#endif /* BSP_USING_FDCAN1 */
#if defined(BSP_USING_FDCAN2)
#ifndef FDCAN2_CONFIG
#define FDCAN2_CONFIG \
{ \
.name = "fdcan2", \
.Instance = FDCAN2, \
}
#endif
#endif /* BSP_USING_FDCAN2 */
#if defined(BSP_USING_FDCAN3)
#ifndef FDCAN3_CONFIG
#define FDCAN3_CONFIG \
{ \
.name = "fdcan3", \
.Instance = FDCAN3, \
}
#endif
#endif /* BSP_USING_FDCAN3 */
#if defined(BSP_USING_FDCAN4)
#ifndef FDCAN4_CONFIG
#define FDCAN4_CONFIG \
{ \
.name = "fdcan4", \
.Instance = FDCAN4, \
}
#endif
#endif /* BSP_USING_FDCAN4 */
#if defined(BSP_USING_FDCAN5)
#ifndef FDCAN5_CONFIG
#define FDCAN5_CONFIG \
{ \
.name = "fdcan5", \
.Instance = FDCAN5, \
}
#endif
#endif /* BSP_USING_FDCAN5 */
#if defined(BSP_USING_FDCAN6)
#ifndef FDCAN6_CONFIG
#define FDCAN6_CONFIG \
{ \
.name = "fdcan6", \
.Instance = FDCAN6, \
}
#endif
#endif /* BSP_USING_FDCAN6 */
#if defined(BSP_USING_FDCAN7)
#ifndef FDCAN7_CONFIG
#define FDCAN7_CONFIG \
{ \
.name = "fdcan7", \
.Instance = FDCAN7, \
}
#endif
#endif /* BSP_USING_FDCAN7 */
#if defined(BSP_USING_FDCAN8)
#ifndef FDCAN8_CONFIG
#define FDCAN8_CONFIG \
{ \
.name = "fdcan8", \
.Instance = FDCAN8, \
}
#endif
#endif /* BSP_USING_FDCAN8 */
#ifdef __cplusplus
}
#endif
#endif /* __CAN_CONFIG_H__ */

70
bsp/n32/n32hxxx/libraries/N32_Drivers/drivers/config/h7xx/dac_config.h Normal file
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@ -0,0 +1,70 @@
/*
* Copyright (c) 2006-2025, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2026-06-09 li.mengmeng first version
*/
#ifndef __DAC_CONFIG_H__
#define __DAC_CONFIG_H__
#include <rtthread.h>
#ifdef __cplusplus
extern "C" {
#endif
#ifdef BSP_USING_DAC1
#ifndef DAC1_CONFIG
#define DAC1_CONFIG \
{ \
.DACx = DAC1, \
.DAC_Module = DAC12, \
.periph_clk = RCC_APB1_PERIPHEN_M7_DAC12, \
.EnablePeriphClk = RCC_EnableAPB1PeriphClk2, \
.DAC_clk_pres = 150, \
.Init.DAC_Trigger = DAC_Trigger_Software, \
.Init.DAC_Trigger2 = DAC_Trigger2_Software, \
.Init.DAC_WaveGeneration = DAC_WaveGeneration_None, \
.Init.DAC_LFSRUnmask_TriangleAmplitude = DAC_LFSRUnmask_Bit0, \
.Init.DAC_OutputBuffer = DISABLE, \
.Init.DAC_TriggerEnable = ENABLE, \
.Init.DAC_ConnectOnChipPeripheral = DISABLE, \
.Init.DAC_ConnectExternalPin = ENABLE, \
.Init.DAC_DMADoubleDataMode = DISABLE, \
.Init.DAC_SignedFormat = DISABLE, \
}
#endif /* DAC1_CONFIG */
#endif /* BSP_USING_DAC1 */
#ifdef BSP_USING_DAC2
#ifndef DAC2_CONFIG
#define DAC2_CONFIG \
{ \
.DACx = DAC2, \
.DAC_Module = DAC12, \
.periph_clk = RCC_APB1_PERIPHEN_M7_DAC12, \
.EnablePeriphClk = RCC_EnableAPB1PeriphClk2, \
.DAC_clk_pres = 150, \
.Init.DAC_Trigger = DAC_Trigger_Software, \
.Init.DAC_Trigger2 = DAC_Trigger2_Software, \
.Init.DAC_WaveGeneration = DAC_WaveGeneration_None, \
.Init.DAC_LFSRUnmask_TriangleAmplitude = DAC_LFSRUnmask_Bit0, \
.Init.DAC_OutputBuffer = DISABLE, \
.Init.DAC_TriggerEnable = ENABLE, \
.Init.DAC_ConnectOnChipPeripheral = DISABLE, \
.Init.DAC_ConnectExternalPin = ENABLE, \
.Init.DAC_DMADoubleDataMode = DISABLE, \
.Init.DAC_SignedFormat = DISABLE, \
}
#endif /* DAC2_CONFIG */
#endif /* BSP_USING_DAC2 */
#ifdef __cplusplus
}
#endif
#endif /* __DAC_CONFIG_H__ */

709
bsp/n32/n32hxxx/libraries/N32_Drivers/drivers/config/h7xx/dma_config.h Normal file
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@ -0,0 +1,709 @@
/*
* Copyright (c) 2006-2025, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2026-01-24 ox-horse first version
*/
#ifndef __DMA_CONFIG_H__
#define __DMA_CONFIG_H__
#include <rtthread.h>
#ifdef __cplusplus
extern "C" {
#endif
/* DMAMUX1 channel0 / DMA1 channel0 */
#if defined(BSP_UART1_RX_USING_DMA) && !defined(UART1_RX_DMA_INSTANCE)
#define UART1_RX_DMA_INSTANCE DMA1
#define UART1_RX_DMA_IRQHandler DMA1_Channel0_IRQHandler
#define UART1_RX_DMA_IRQ DMA1_Channel0_IRQn
#define UART1_RX_DMA_HANDSHAK DMA_CH_HARDWARE_HANDSHAKING_IF_0
#define UART1_RX_DMA_DMA_RCC RCC_AHB1_PERIPHEN_M7_DMA1
#define UART1_RX_DMA_DMA_CHANNEL DMA_CHANNEL_0
#define UART1_RX_DMA_DMAMUX_CHANNEL DMAMUX_CHANNEL_0
#define UART1_RX_DMA_DMAMUX_REQUEST DMAMUX1_REQUEST_USART1_RX
#elif defined(BSP_UART8_TX_USING_DMA) && !defined(UART8_TX_DMA_INSTANCE)
#define UART8_TX_DMA_INSTANCE DMA1
#define UART8_TX_DMA_IRQHandler DMA1_Channel0_IRQHandler
#define UART8_TX_DMA_IRQ DMA1_Channel0_IRQn
#define UART8_TX_DMA_HANDSHAK DMA_CH_HARDWARE_HANDSHAKING_IF_0
#define UART8_TX_DMA_DMA_RCC RCC_AHB1_PERIPHEN_M7_DMA1
#define UART8_TX_DMA_DMA_CHANNEL DMA_CHANNEL_0
#define UART8_TX_DMA_DMAMUX_CHANNEL DMAMUX_CHANNEL_0
#define UART8_TX_DMA_DMAMUX_REQUEST DMAMUX1_REQUEST_USART8_TX
#elif defined(BSP_I2C5_TX_USING_DMA) && !defined(I2C5_TX_DMA_INSTANCE)
#define I2C5_TX_DMA_INSTANCE DMA1
#define I2C5_TX_DMA_IRQHandler DMA1_Channel0_IRQHandler
#define I2C5_TX_DMA_IRQ DMA1_Channel0_IRQn
#define I2C5_TX_DMA_HANDSHAK DMA_CH_HARDWARE_HANDSHAKING_IF_0
#define I2C5_TX_DMA_DMA_RCC RCC_AHB1_PERIPHEN_M7_DMA1
#define I2C5_TX_DMA_DMA_CHANNEL DMA_CHANNEL_0
#define I2C5_TX_DMA_DMAMUX_CHANNEL DMAMUX_CHANNEL_0
#define I2C5_TX_DMA_DMAMUX_REQUEST DMAMUX1_REQUEST_I2C5_TX
#endif
/* DMAMUX1 channel1 / DMA1 channel1 */
#if defined(BSP_UART2_RX_USING_DMA) && !defined(UART2_RX_DMA_INSTANCE)
#define UART2_RX_DMA_INSTANCE DMA1
#define UART2_RX_DMA_IRQHandler DMA1_Channel1_IRQHandler
#define UART2_RX_DMA_IRQ DMA1_Channel1_IRQn
#define UART2_RX_DMA_HANDSHAK DMA_CH_HARDWARE_HANDSHAKING_IF_1
#define UART2_RX_DMA_DMA_RCC RCC_AHB1_PERIPHEN_M7_DMA1
#define UART2_RX_DMA_DMA_CHANNEL DMA_CHANNEL_1
#define UART2_RX_DMA_DMAMUX_CHANNEL DMAMUX_CHANNEL_1
#define UART2_RX_DMA_DMAMUX_REQUEST DMAMUX1_REQUEST_USART2_RX
#elif defined(BSP_UART9_TX_USING_DMA) && !defined(UART9_TX_DMA_INSTANCE)
#define UART9_TX_DMA_INSTANCE DMA1
#define UART9_TX_DMA_IRQHandler DMA1_Channel1_IRQHandler
#define UART9_TX_DMA_IRQ DMA1_Channel1_IRQn
#define UART9_TX_DMA_HANDSHAK DMA_CH_HARDWARE_HANDSHAKING_IF_1
#define UART9_TX_DMA_DMA_RCC RCC_AHB1_PERIPHEN_M7_DMA1
#define UART9_TX_DMA_DMA_CHANNEL DMA_CHANNEL_1
#define UART9_TX_DMA_DMAMUX_CHANNEL DMAMUX_CHANNEL_1
#define UART9_TX_DMA_DMAMUX_REQUEST DMAMUX1_REQUEST_UART9_TX
#elif defined(BSP_I2C6_TX_USING_DMA) && !defined(I2C6_TX_DMA_INSTANCE)
#define I2C6_TX_DMA_INSTANCE DMA1
#define I2C6_TX_DMA_IRQHandler DMA1_Channel1_IRQHandler
#define I2C6_TX_DMA_IRQ DMA1_Channel1_IRQn
#define I2C6_TX_DMA_HANDSHAK DMA_CH_HARDWARE_HANDSHAKING_IF_1
#define I2C6_TX_DMA_DMA_RCC RCC_AHB1_PERIPHEN_M7_DMA1
#define I2C6_TX_DMA_DMA_CHANNEL DMA_CHANNEL_1
#define I2C6_TX_DMA_DMAMUX_CHANNEL DMAMUX_CHANNEL_1
#define I2C6_TX_DMA_DMAMUX_REQUEST DMAMUX1_REQUEST_I2C6_TX
#endif
/* DMAMUX1 channel2 / DMA1 channel2 */
#if defined(BSP_UART3_RX_USING_DMA) && !defined(UART3_RX_DMA_INSTANCE)
#define UART3_RX_DMA_INSTANCE DMA1
#define UART3_RX_DMA_IRQHandler DMA1_Channel2_IRQHandler
#define UART3_RX_DMA_IRQ DMA1_Channel2_IRQn
#define UART3_RX_DMA_HANDSHAK DMA_CH_HARDWARE_HANDSHAKING_IF_2
#define UART3_RX_DMA_DMA_RCC RCC_AHB1_PERIPHEN_M7_DMA1
#define UART3_RX_DMA_DMA_CHANNEL DMA_CHANNEL_2
#define UART3_RX_DMA_DMAMUX_CHANNEL DMAMUX_CHANNEL_2
#define UART3_RX_DMA_DMAMUX_REQUEST DMAMUX1_REQUEST_USART3_RX
#elif defined(BSP_UART10_TX_USING_DMA) && !defined(UART10_TX_DMA_INSTANCE)
#define UART10_TX_DMA_INSTANCE DMA1
#define UART10_TX_DMA_IRQHandler DMA1_Channel2_IRQHandler
#define UART10_TX_DMA_IRQ DMA1_Channel2_IRQn
#define UART10_TX_DMA_HANDSHAK DMA_CH_HARDWARE_HANDSHAKING_IF_2
#define UART10_TX_DMA_DMA_RCC RCC_AHB1_PERIPHEN_M7_DMA1
#define UART10_TX_DMA_DMA_CHANNEL DMA_CHANNEL_2
#define UART10_TX_DMA_DMAMUX_CHANNEL DMAMUX_CHANNEL_2
#define UART10_TX_DMA_DMAMUX_REQUEST DMAMUX1_REQUEST_UART10_TX
#elif defined(BSP_I2C7_TX_USING_DMA) && !defined(I2C7_TX_DMA_INSTANCE)
#define I2C7_TX_DMA_INSTANCE DMA1
#define I2C7_TX_DMA_IRQHandler DMA1_Channel2_IRQHandler
#define I2C7_TX_DMA_IRQ DMA1_Channel2_IRQn
#define I2C7_TX_DMA_HANDSHAK DMA_CH_HARDWARE_HANDSHAKING_IF_2
#define I2C7_TX_DMA_DMA_RCC RCC_AHB1_PERIPHEN_M7_DMA1
#define I2C7_TX_DMA_DMA_CHANNEL DMA_CHANNEL_2
#define I2C7_TX_DMA_DMAMUX_CHANNEL DMAMUX_CHANNEL_2
#define I2C7_TX_DMA_DMAMUX_REQUEST DMAMUX1_REQUEST_I2C7_TX
#endif
/* DMAMUX1 channel3 / DMA1 channel3 */
#if defined(BSP_UART4_RX_USING_DMA) && !defined(UART4_RX_DMA_INSTANCE)
#define UART4_RX_DMA_INSTANCE DMA1
#define UART4_RX_DMA_IRQHandler DMA1_Channel3_IRQHandler
#define UART4_RX_DMA_IRQ DMA1_Channel3_IRQn
#define UART4_RX_DMA_HANDSHAK DMA_CH_HARDWARE_HANDSHAKING_IF_3
#define UART4_RX_DMA_DMA_RCC RCC_AHB1_PERIPHEN_M7_DMA1
#define UART4_RX_DMA_DMA_CHANNEL DMA_CHANNEL_3
#define UART4_RX_DMA_DMAMUX_CHANNEL DMAMUX_CHANNEL_3
#define UART4_RX_DMA_DMAMUX_REQUEST DMAMUX1_REQUEST_USART4_RX
#elif defined(BSP_UART11_TX_USING_DMA) && !defined(UART11_TX_DMA_INSTANCE)
#define UART11_TX_DMA_INSTANCE DMA1
#define UART11_TX_DMA_IRQHandler DMA1_Channel3_IRQHandler
#define UART11_TX_DMA_IRQ DMA1_Channel3_IRQn
#define UART11_TX_DMA_HANDSHAK DMA_CH_HARDWARE_HANDSHAKING_IF_3
#define UART11_TX_DMA_DMA_RCC RCC_AHB1_PERIPHEN_M7_DMA1
#define UART11_TX_DMA_DMA_CHANNEL DMA_CHANNEL_3
#define UART11_TX_DMA_DMAMUX_CHANNEL DMAMUX_CHANNEL_3
#define UART11_TX_DMA_DMAMUX_REQUEST DMAMUX1_REQUEST_UART11_TX
#elif defined(BSP_I2C8_TX_USING_DMA) && !defined(I2C8_TX_DMA_INSTANCE)
#define I2C8_TX_DMA_INSTANCE DMA1
#define I2C8_TX_DMA_IRQHandler DMA1_Channel3_IRQHandler
#define I2C8_TX_DMA_IRQ DMA1_Channel3_IRQn
#define I2C8_TX_DMA_HANDSHAK DMA_CH_HARDWARE_HANDSHAKING_IF_3
#define I2C8_TX_DMA_DMA_RCC RCC_AHB1_PERIPHEN_M7_DMA1
#define I2C8_TX_DMA_DMA_CHANNEL DMA_CHANNEL_3
#define I2C8_TX_DMA_DMAMUX_CHANNEL DMAMUX_CHANNEL_3
#define I2C8_TX_DMA_DMAMUX_REQUEST DMAMUX1_REQUEST_I2C8_TX
#endif
/* DMAMUX1 channel4 / DMA1 channel4 */
#if defined(BSP_UART5_RX_USING_DMA) && !defined(UART5_RX_DMA_INSTANCE)
#define UART5_RX_DMA_INSTANCE DMA1
#define UART5_RX_DMA_IRQHandler DMA1_Channel4_IRQHandler
#define UART5_RX_DMA_IRQ DMA1_Channel4_IRQn
#define UART5_RX_DMA_HANDSHAK DMA_CH_HARDWARE_HANDSHAKING_IF_4
#define UART5_RX_DMA_DMA_RCC RCC_AHB1_PERIPHEN_M7_DMA1
#define UART5_RX_DMA_DMA_CHANNEL DMA_CHANNEL_4
#define UART5_RX_DMA_DMAMUX_CHANNEL DMAMUX_CHANNEL_4
#define UART5_RX_DMA_DMAMUX_REQUEST DMAMUX1_REQUEST_USART5_RX
#elif defined(BSP_UART12_TX_USING_DMA) && !defined(UART12_TX_DMA_INSTANCE)
#define UART12_TX_DMA_INSTANCE DMA1
#define UART12_TX_DMA_IRQHandler DMA1_Channel4_IRQHandler
#define UART12_TX_DMA_IRQ DMA1_Channel4_IRQn
#define UART12_TX_DMA_HANDSHAK DMA_CH_HARDWARE_HANDSHAKING_IF_4
#define UART12_TX_DMA_DMA_RCC RCC_AHB1_PERIPHEN_M7_DMA1
#define UART12_TX_DMA_DMA_CHANNEL DMA_CHANNEL_4
#define UART12_TX_DMA_DMAMUX_CHANNEL DMAMUX_CHANNEL_4
#define UART12_TX_DMA_DMAMUX_REQUEST DMAMUX1_REQUEST_UART12_TX
#elif defined(BSP_I2C9_TX_USING_DMA) && !defined(I2C9_TX_DMA_INSTANCE)
#define I2C9_TX_DMA_INSTANCE DMA1
#define I2C9_TX_DMA_IRQHandler DMA1_Channel4_IRQHandler
#define I2C9_TX_DMA_IRQ DMA1_Channel4_IRQn
#define I2C9_TX_DMA_HANDSHAK DMA_CH_HARDWARE_HANDSHAKING_IF_4
#define I2C9_TX_DMA_DMA_RCC RCC_AHB1_PERIPHEN_M7_DMA1
#define I2C9_TX_DMA_DMA_CHANNEL DMA_CHANNEL_4
#define I2C9_TX_DMA_DMAMUX_CHANNEL DMAMUX_CHANNEL_4
#define I2C9_TX_DMA_DMAMUX_REQUEST DMAMUX1_REQUEST_I2C9_TX
#endif
/* DMAMUX1 channel5 / DMA1 channel5 */
#if defined(BSP_UART6_RX_USING_DMA) && !defined(UART6_RX_DMA_INSTANCE)
#define UART6_RX_DMA_INSTANCE DMA1
#define UART6_RX_DMA_IRQHandler DMA1_Channel5_IRQHandler
#define UART6_RX_DMA_IRQ DMA1_Channel5_IRQn
#define UART6_RX_DMA_HANDSHAK DMA_CH_HARDWARE_HANDSHAKING_IF_5
#define UART6_RX_DMA_DMA_RCC RCC_AHB1_PERIPHEN_M7_DMA1
#define UART6_RX_DMA_DMA_CHANNEL DMA_CHANNEL_5
#define UART6_RX_DMA_DMAMUX_CHANNEL DMAMUX_CHANNEL_5
#define UART6_RX_DMA_DMAMUX_REQUEST DMAMUX1_REQUEST_USART6_RX
#elif defined(BSP_UART13_TX_USING_DMA) && !defined(UART13_TX_DMA_INSTANCE)
#define UART13_TX_DMA_INSTANCE DMA1
#define UART13_TX_DMA_IRQHandler DMA1_Channel5_IRQHandler
#define UART13_TX_DMA_IRQ DMA1_Channel5_IRQn
#define UART13_TX_DMA_HANDSHAK DMA_CH_HARDWARE_HANDSHAKING_IF_5
#define UART13_TX_DMA_DMA_RCC RCC_AHB1_PERIPHEN_M7_DMA1
#define UART13_TX_DMA_DMA_CHANNEL DMA_CHANNEL_5
#define UART13_TX_DMA_DMAMUX_CHANNEL DMAMUX_CHANNEL_5
#define UART13_TX_DMA_DMAMUX_REQUEST DMAMUX1_REQUEST_UART13_TX
#elif defined(BSP_I2C10_TX_USING_DMA) && !defined(I2C10_TX_DMA_INSTANCE)
#define I2C10_TX_DMA_INSTANCE DMA1
#define I2C10_TX_DMA_IRQHandler DMA1_Channel5_IRQHandler
#define I2C10_TX_DMA_IRQ DMA1_Channel5_IRQn
#define I2C10_TX_DMA_HANDSHAK DMA_CH_HARDWARE_HANDSHAKING_IF_5
#define I2C10_TX_DMA_DMA_RCC RCC_AHB1_PERIPHEN_M7_DMA1
#define I2C10_TX_DMA_DMA_CHANNEL DMA_CHANNEL_5
#define I2C10_TX_DMA_DMAMUX_CHANNEL DMAMUX_CHANNEL_5
#define I2C10_TX_DMA_DMAMUX_REQUEST DMAMUX1_REQUEST_I2C10_TX
#endif
/* DMAMUX1 channel6 / DMA1 channel6 */
#if defined(BSP_UART7_RX_USING_DMA) && !defined(UART7_RX_DMA_INSTANCE)
#define UART7_RX_DMA_INSTANCE DMA1
#define UART7_RX_DMA_IRQHandler DMA1_Channel6_IRQHandler
#define UART7_RX_DMA_IRQ DMA1_Channel6_IRQn
#define UART7_RX_DMA_HANDSHAK DMA_CH_HARDWARE_HANDSHAKING_IF_6
#define UART7_RX_DMA_DMA_RCC RCC_AHB1_PERIPHEN_M7_DMA1
#define UART7_RX_DMA_DMA_CHANNEL DMA_CHANNEL_6
#define UART7_RX_DMA_DMAMUX_CHANNEL DMAMUX_CHANNEL_6
#define UART7_RX_DMA_DMAMUX_REQUEST DMAMUX1_REQUEST_USART7_RX
#elif defined(BSP_UART14_TX_USING_DMA) && !defined(UART14_TX_DMA_INSTANCE)
#define UART14_TX_DMA_INSTANCE DMA1
#define UART14_TX_DMA_IRQHandler DMA1_Channel6_IRQHandler
#define UART14_TX_DMA_IRQ DMA1_Channel6_IRQn
#define UART14_TX_DMA_HANDSHAK DMA_CH_HARDWARE_HANDSHAKING_IF_6
#define UART14_TX_DMA_DMA_RCC RCC_AHB1_PERIPHEN_M7_DMA1
#define UART14_TX_DMA_DMA_CHANNEL DMA_CHANNEL_6
#define UART14_TX_DMA_DMAMUX_CHANNEL DMAMUX_CHANNEL_6
#define UART14_TX_DMA_DMAMUX_REQUEST DMAMUX1_REQUEST_UART14_TX
#elif defined(BSP_SPI1_TX_USING_DMA) && !defined(SPI1_TX_DMA_INSTANCE)
#define SPI1_TX_DMA_INSTANCE DMA1
#define SPI1_TX_DMA_IRQHandler DMA1_Channel6_IRQHandler
#define SPI1_TX_DMA_IRQ DMA1_Channel6_IRQn
#define SPI1_TX_DMA_HANDSHAK DMA_CH_HARDWARE_HANDSHAKING_IF_6
#define SPI1_TX_DMA_DMA_RCC RCC_AHB1_PERIPHEN_M7_DMA1
#define SPI1_TX_DMA_DMA_CHANNEL DMA_CHANNEL_6
#define SPI1_TX_DMA_DMAMUX_CHANNEL DMAMUX_CHANNEL_6
#define SPI1_TX_DMA_DMAMUX_REQUEST DMAMUX1_REQUEST_SPI1_TX
#endif
/* DMAMUX1 channel7 / DMA1 channel7 */
#if defined(BSP_UART8_RX_USING_DMA) && !defined(UART8_RX_DMA_INSTANCE)
#define UART8_RX_DMA_INSTANCE DMA1
#define UART8_RX_DMA_IRQHandler DMA1_Channel7_IRQHandler
#define UART8_RX_DMA_IRQ DMA1_Channel7_IRQn
#define UART8_RX_DMA_HANDSHAK DMA_CH_HARDWARE_HANDSHAKING_IF_7
#define UART8_RX_DMA_DMA_RCC RCC_AHB1_PERIPHEN_M7_DMA1
#define UART8_RX_DMA_DMA_CHANNEL DMA_CHANNEL_7
#define UART8_RX_DMA_DMAMUX_CHANNEL DMAMUX_CHANNEL_7
#define UART8_RX_DMA_DMAMUX_REQUEST DMAMUX1_REQUEST_USART8_RX
#elif defined(BSP_UART15_TX_USING_DMA) && !defined(UART15_TX_DMA_INSTANCE)
#define UART15_TX_DMA_INSTANCE DMA1
#define UART15_TX_DMA_IRQHandler DMA1_Channel7_IRQHandler
#define UART15_TX_DMA_IRQ DMA1_Channel7_IRQn
#define UART15_TX_DMA_HANDSHAK DMA_CH_HARDWARE_HANDSHAKING_IF_7
#define UART15_TX_DMA_DMA_RCC RCC_AHB1_PERIPHEN_M7_DMA1
#define UART15_TX_DMA_DMA_CHANNEL DMA_CHANNEL_7
#define UART15_TX_DMA_DMAMUX_CHANNEL DMAMUX_CHANNEL_7
#define UART15_TX_DMA_DMAMUX_REQUEST DMAMUX1_REQUEST_UART15_TX
#elif defined(BSP_SPI2_TX_USING_DMA) && !defined(SPI2_TX_DMA_INSTANCE)
#define SPI2_TX_DMA_INSTANCE DMA1
#define SPI2_TX_DMA_IRQHandler DMA1_Channel7_IRQHandler
#define SPI2_TX_DMA_IRQ DMA1_Channel7_IRQn
#define SPI2_TX_DMA_HANDSHAK DMA_CH_HARDWARE_HANDSHAKING_IF_7
#define SPI2_TX_DMA_DMA_RCC RCC_AHB1_PERIPHEN_M7_DMA1
#define SPI2_TX_DMA_DMA_CHANNEL DMA_CHANNEL_7
#define SPI2_TX_DMA_DMAMUX_CHANNEL DMAMUX_CHANNEL_7
#define SPI2_TX_DMA_DMAMUX_REQUEST DMAMUX1_REQUEST_SPI2_TX
#endif
/* DMAMUX1 channel8 / DMA2 channel0 */
#if defined(BSP_UART9_RX_USING_DMA) && !defined(UART9_RX_DMA_INSTANCE)
#define UART9_RX_DMA_INSTANCE DMA2
#define UART9_RX_DMA_IRQHandler DMA2_Channel0_IRQHandler
#define UART9_RX_DMA_IRQ DMA2_Channel0_IRQn
#define UART9_RX_DMA_HANDSHAK DMA_CH_HARDWARE_HANDSHAKING_IF_0
#define UART9_RX_DMA_DMA_RCC RCC_AHB1_PERIPHEN_M7_DMA2
#define UART9_RX_DMA_DMA_CHANNEL DMA_CHANNEL_0
#define UART9_RX_DMA_DMAMUX_CHANNEL DMAMUX_CHANNEL_8
#define UART9_RX_DMA_DMAMUX_REQUEST DMAMUX1_REQUEST_UART9_RX
#elif defined(BSP_LPUART1_TX_USING_DMA) && !defined(LPUART1_TX_DMA_INSTANCE)
#define LPUART1_TX_DMA_INSTANCE DMA2
#define LPUART1_TX_DMA_IRQHandler DMA2_Channel0_IRQHandler
#define LPUART1_TX_DMA_IRQ DMA2_Channel0_IRQn
#define LPUART1_TX_DMA_HANDSHAK DMA_CH_HARDWARE_HANDSHAKING_IF_0
#define LPUART1_TX_DMA_DMA_RCC RCC_AHB1_PERIPHEN_M7_DMA2
#define LPUART1_TX_DMA_DMA_CHANNEL DMA_CHANNEL_0
#define LPUART1_TX_DMA_DMAMUX_CHANNEL DMAMUX_CHANNEL_8
#define LPUART1_TX_DMA_DMAMUX_REQUEST DMAMUX1_REQUEST_LPUART1_TX
#elif defined(BSP_SPI3_TX_USING_DMA) && !defined(SPI3_TX_DMA_INSTANCE)
#define SPI3_TX_DMA_INSTANCE DMA2
#define SPI3_TX_DMA_IRQHandler DMA2_Channel0_IRQHandler
#define SPI3_TX_DMA_IRQ DMA2_Channel0_IRQn
#define SPI3_TX_DMA_HANDSHAK DMA_CH_HARDWARE_HANDSHAKING_IF_0
#define SPI3_TX_DMA_DMA_RCC RCC_AHB1_PERIPHEN_M7_DMA2
#define SPI3_TX_DMA_DMA_CHANNEL DMA_CHANNEL_0
#define SPI3_TX_DMA_DMAMUX_CHANNEL DMAMUX_CHANNEL_8
#define SPI3_TX_DMA_DMAMUX_REQUEST DMAMUX1_REQUEST_SPI3_TX
#endif
/* DMAMUX1 channel9 / DMA2 channel1 */
#if defined(BSP_UART10_RX_USING_DMA) && !defined(UART10_RX_DMA_INSTANCE)
#define UART10_RX_DMA_INSTANCE DMA2
#define UART10_RX_DMA_IRQHandler DMA2_Channel1_IRQHandler
#define UART10_RX_DMA_IRQ DMA2_Channel1_IRQn
#define UART10_RX_DMA_HANDSHAK DMA_CH_HARDWARE_HANDSHAKING_IF_1
#define UART10_RX_DMA_DMA_RCC RCC_AHB1_PERIPHEN_M7_DMA2
#define UART10_RX_DMA_DMA_CHANNEL DMA_CHANNEL_1
#define UART10_RX_DMA_DMAMUX_CHANNEL DMAMUX_CHANNEL_9
#define UART10_RX_DMA_DMAMUX_REQUEST DMAMUX1_REQUEST_UART10_RX
#elif defined(BSP_LPUART2_TX_USING_DMA) && !defined(LPUART2_TX_DMA_INSTANCE)
#define LPUART2_TX_DMA_INSTANCE DMA2
#define LPUART2_TX_DMA_IRQHandler DMA2_Channel1_IRQHandler
#define LPUART2_TX_DMA_IRQ DMA2_Channel1_IRQn
#define LPUART2_TX_DMA_HANDSHAK DMA_CH_HARDWARE_HANDSHAKING_IF_1
#define LPUART2_TX_DMA_DMA_RCC RCC_AHB1_PERIPHEN_M7_DMA2
#define LPUART2_TX_DMA_DMA_CHANNEL DMA_CHANNEL_1
#define LPUART2_TX_DMA_DMAMUX_CHANNEL DMAMUX_CHANNEL_9
#define LPUART2_TX_DMA_DMAMUX_REQUEST DMAMUX1_REQUEST_LPUART2_TX
#elif defined(BSP_SPI4_TX_USING_DMA) && !defined(SPI4_TX_DMA_INSTANCE)
#define SPI4_TX_DMA_INSTANCE DMA2
#define SPI4_TX_DMA_IRQHandler DMA2_Channel1_IRQHandler
#define SPI4_TX_DMA_IRQ DMA2_Channel1_IRQn
#define SPI4_TX_DMA_HANDSHAK DMA_CH_HARDWARE_HANDSHAKING_IF_1
#define SPI4_TX_DMA_DMA_RCC RCC_AHB1_PERIPHEN_M7_DMA2
#define SPI4_TX_DMA_DMA_CHANNEL DMA_CHANNEL_1
#define SPI4_TX_DMA_DMAMUX_CHANNEL DMAMUX_CHANNEL_9
#define SPI4_TX_DMA_DMAMUX_REQUEST DMAMUX1_REQUEST_SPI4_TX
#endif
/* DMAMUX1 channel10 / DMA2 channel2 */
#if defined(BSP_I2C1_RX_USING_DMA) && !defined(I2C1_RX_DMA_INSTANCE)
#define I2C1_RX_DMA_INSTANCE DMA2
#define I2C1_RX_DMA_IRQHandler DMA2_Channel2_IRQHandler
#define I2C1_RX_DMA_IRQ DMA2_Channel2_IRQn
#define I2C1_RX_DMA_HANDSHAK DMA_CH_HARDWARE_HANDSHAKING_IF_2
#define I2C1_RX_DMA_DMA_RCC RCC_AHB1_PERIPHEN_M7_DMA2
#define I2C1_RX_DMA_DMA_CHANNEL DMA_CHANNEL_2
#define I2C1_RX_DMA_DMAMUX_CHANNEL DMAMUX_CHANNEL_10
#define I2C1_RX_DMA_DMAMUX_REQUEST DMAMUX1_REQUEST_I2C1_RX
#elif defined(BSP_UART11_RX_USING_DMA) && !defined(UART11_RX_DMA_INSTANCE)
#define UART11_RX_DMA_INSTANCE DMA2
#define UART11_RX_DMA_IRQHandler DMA2_Channel2_IRQHandler
#define UART11_RX_DMA_IRQ DMA2_Channel2_IRQn
#define UART11_RX_DMA_HANDSHAK DMA_CH_HARDWARE_HANDSHAKING_IF_2
#define UART11_RX_DMA_DMA_RCC RCC_AHB1_PERIPHEN_M7_DMA2
#define UART11_RX_DMA_DMA_CHANNEL DMA_CHANNEL_2
#define UART11_RX_DMA_DMAMUX_CHANNEL DMAMUX_CHANNEL_10
#define UART11_RX_DMA_DMAMUX_REQUEST DMAMUX1_REQUEST_UART11_RX
#elif defined(BSP_SPI5_TX_USING_DMA) && !defined(SPI5_TX_DMA_INSTANCE)
#define SPI5_TX_DMA_INSTANCE DMA2
#define SPI5_TX_DMA_IRQHandler DMA2_Channel2_IRQHandler
#define SPI5_TX_DMA_IRQ DMA2_Channel2_IRQn
#define SPI5_TX_DMA_HANDSHAK DMA_CH_HARDWARE_HANDSHAKING_IF_2
#define SPI5_TX_DMA_DMA_RCC RCC_AHB1_PERIPHEN_M7_DMA2
#define SPI5_TX_DMA_DMA_CHANNEL DMA_CHANNEL_2
#define SPI5_TX_DMA_DMAMUX_CHANNEL DMAMUX_CHANNEL_10
#define SPI5_TX_DMA_DMAMUX_REQUEST DMAMUX1_REQUEST_SPI5_TX
#endif
/* DMAMUX1 channel11 / DMA2 channel3 */
#if defined(BSP_I2C2_RX_USING_DMA) && !defined(I2C2_RX_DMA_INSTANCE)
#define I2C2_RX_DMA_INSTANCE DMA2
#define I2C2_RX_DMA_IRQHandler DMA2_Channel3_IRQHandler
#define I2C2_RX_DMA_IRQ DMA2_Channel3_IRQn
#define I2C2_RX_DMA_HANDSHAK DMA_CH_HARDWARE_HANDSHAKING_IF_3
#define I2C2_RX_DMA_DMA_RCC RCC_AHB1_PERIPHEN_M7_DMA2
#define I2C2_RX_DMA_DMA_CHANNEL DMA_CHANNEL_3
#define I2C2_RX_DMA_DMAMUX_CHANNEL DMAMUX_CHANNEL_11
#define I2C2_RX_DMA_DMAMUX_REQUEST DMAMUX1_REQUEST_I2C2_RX
#elif defined(BSP_UART12_RX_USING_DMA) && !defined(UART12_RX_DMA_INSTANCE)
#define UART12_RX_DMA_INSTANCE DMA2
#define UART12_RX_DMA_IRQHandler DMA2_Channel3_IRQHandler
#define UART12_RX_DMA_IRQ DMA2_Channel3_IRQn
#define UART12_RX_DMA_HANDSHAK DMA_CH_HARDWARE_HANDSHAKING_IF_3
#define UART12_RX_DMA_DMA_RCC RCC_AHB1_PERIPHEN_M7_DMA2
#define UART12_RX_DMA_DMA_CHANNEL DMA_CHANNEL_3
#define UART12_RX_DMA_DMAMUX_CHANNEL DMAMUX_CHANNEL_11
#define UART12_RX_DMA_DMAMUX_REQUEST DMAMUX1_REQUEST_UART12_RX
#elif defined(BSP_SPI6_TX_USING_DMA) && !defined(SPI6_TX_DMA_INSTANCE)
#define SPI6_TX_DMA_INSTANCE DMA2
#define SPI6_TX_DMA_IRQHandler DMA2_Channel3_IRQHandler
#define SPI6_TX_DMA_IRQ DMA2_Channel3_IRQn
#define SPI6_TX_DMA_HANDSHAK DMA_CH_HARDWARE_HANDSHAKING_IF_3
#define SPI6_TX_DMA_DMA_RCC RCC_AHB1_PERIPHEN_M7_DMA2
#define SPI6_TX_DMA_DMA_CHANNEL DMA_CHANNEL_3
#define SPI6_TX_DMA_DMAMUX_CHANNEL DMAMUX_CHANNEL_11
#define SPI6_TX_DMA_DMAMUX_REQUEST DMAMUX1_REQUEST_SPI6_TX
#endif
/* DMAMUX1 channel12 / DMA2 channel4 */
#if defined(BSP_I2C3_RX_USING_DMA) && !defined(I2C3_RX_DMA_INSTANCE)
#define I2C3_RX_DMA_INSTANCE DMA2
#define I2C3_RX_DMA_IRQHandler DMA2_Channel4_IRQHandler
#define I2C3_RX_DMA_IRQ DMA2_Channel4_IRQn
#define I2C3_RX_DMA_HANDSHAK DMA_CH_HARDWARE_HANDSHAKING_IF_4
#define I2C3_RX_DMA_DMA_RCC RCC_AHB1_PERIPHEN_M7_DMA2
#define I2C3_RX_DMA_DMA_CHANNEL DMA_CHANNEL_4
#define I2C3_RX_DMA_DMAMUX_CHANNEL DMAMUX_CHANNEL_12
#define I2C3_RX_DMA_DMAMUX_REQUEST DMAMUX1_REQUEST_I2C3_RX
#elif defined(BSP_UART13_RX_USING_DMA) && !defined(UART13_RX_DMA_INSTANCE)
#define UART13_RX_DMA_INSTANCE DMA2
#define UART13_RX_DMA_IRQHandler DMA2_Channel4_IRQHandler
#define UART13_RX_DMA_IRQ DMA2_Channel4_IRQn
#define UART13_RX_DMA_HANDSHAK DMA_CH_HARDWARE_HANDSHAKING_IF_4
#define UART13_RX_DMA_DMA_RCC RCC_AHB1_PERIPHEN_M7_DMA2
#define UART13_RX_DMA_DMA_CHANNEL DMA_CHANNEL_4
#define UART13_RX_DMA_DMAMUX_CHANNEL DMAMUX_CHANNEL_12
#define UART13_RX_DMA_DMAMUX_REQUEST DMAMUX1_REQUEST_UART13_RX
#elif defined(BSP_SPI7_TX_USING_DMA) && !defined(SPI7_TX_DMA_INSTANCE)
#define SPI7_TX_DMA_INSTANCE DMA2
#define SPI7_TX_DMA_IRQHandler DMA2_Channel4_IRQHandler
#define SPI7_TX_DMA_IRQ DMA2_Channel4_IRQn
#define SPI7_TX_DMA_HANDSHAK DMA_CH_HARDWARE_HANDSHAKING_IF_4
#define SPI7_TX_DMA_DMA_RCC RCC_AHB1_PERIPHEN_M7_DMA2
#define SPI7_TX_DMA_DMA_CHANNEL DMA_CHANNEL_4
#define SPI7_TX_DMA_DMAMUX_CHANNEL DMAMUX_CHANNEL_12
#define SPI7_TX_DMA_DMAMUX_REQUEST DMAMUX1_REQUEST_SPI7_TX
#endif
/* DMAMUX1 channel13 / DMA2 channel5 */
#if defined(BSP_I2C4_RX_USING_DMA) && !defined(I2C4_RX_DMA_INSTANCE)
#define I2C4_RX_DMA_INSTANCE DMA2
#define I2C4_RX_DMA_IRQHandler DMA2_Channel5_IRQHandler
#define I2C4_RX_DMA_IRQ DMA2_Channel5_IRQn
#define I2C4_RX_DMA_HANDSHAK DMA_CH_HARDWARE_HANDSHAKING_IF_5
#define I2C4_RX_DMA_DMA_RCC RCC_AHB1_PERIPHEN_M7_DMA2
#define I2C4_RX_DMA_DMA_CHANNEL DMA_CHANNEL_5
#define I2C4_RX_DMA_DMAMUX_CHANNEL DMAMUX_CHANNEL_13
#define I2C4_RX_DMA_DMAMUX_REQUEST DMAMUX1_REQUEST_I2C4_RX
#elif defined(BSP_UART14_RX_USING_DMA) && !defined(UART14_RX_DMA_INSTANCE)
#define UART14_RX_DMA_INSTANCE DMA2
#define UART14_RX_DMA_IRQHandler DMA2_Channel5_IRQHandler
#define UART14_RX_DMA_IRQ DMA2_Channel5_IRQn
#define UART14_RX_DMA_HANDSHAK DMA_CH_HARDWARE_HANDSHAKING_IF_5
#define UART14_RX_DMA_DMA_RCC RCC_AHB1_PERIPHEN_M7_DMA2
#define UART14_RX_DMA_DMA_CHANNEL DMA_CHANNEL_5
#define UART14_RX_DMA_DMAMUX_CHANNEL DMAMUX_CHANNEL_13
#define UART14_RX_DMA_DMAMUX_REQUEST DMAMUX1_REQUEST_UART14_RX
#elif defined(BSP_SPI1_RX_USING_DMA) && !defined(SPI1_RX_DMA_INSTANCE)
#define SPI1_RX_DMA_INSTANCE DMA2
#define SPI1_RX_DMA_IRQHandler DMA2_Channel5_IRQHandler
#define SPI1_RX_DMA_IRQ DMA2_Channel5_IRQn
#define SPI1_RX_DMA_HANDSHAK DMA_CH_HARDWARE_HANDSHAKING_IF_5
#define SPI1_RX_DMA_DMA_RCC RCC_AHB1_PERIPHEN_M7_DMA2
#define SPI1_RX_DMA_DMA_CHANNEL DMA_CHANNEL_5
#define SPI1_RX_DMA_DMAMUX_CHANNEL DMAMUX_CHANNEL_13
#define SPI1_RX_DMA_DMAMUX_REQUEST DMAMUX1_REQUEST_SPI1_RX
#endif
/* DMAMUX1 channel14 / DMA2 channel6 */
#if defined(BSP_I2C5_RX_USING_DMA) && !defined(I2C5_RX_DMA_INSTANCE)
#define I2C5_RX_DMA_INSTANCE DMA2
#define I2C5_RX_DMA_IRQHandler DMA2_Channel6_IRQHandler
#define I2C5_RX_DMA_IRQ DMA2_Channel6_IRQn
#define I2C5_RX_DMA_HANDSHAK DMA_CH_HARDWARE_HANDSHAKING_IF_6
#define I2C5_RX_DMA_DMA_RCC RCC_AHB1_PERIPHEN_M7_DMA2
#define I2C5_RX_DMA_DMA_CHANNEL DMA_CHANNEL_6
#define I2C5_RX_DMA_DMAMUX_CHANNEL DMAMUX_CHANNEL_14
#define I2C5_RX_DMA_DMAMUX_REQUEST DMAMUX1_REQUEST_I2C5_RX
#elif defined(BSP_UART15_RX_USING_DMA) && !defined(UART15_RX_DMA_INSTANCE)
#define UART15_RX_DMA_INSTANCE DMA2
#define UART15_RX_DMA_IRQHandler DMA2_Channel6_IRQHandler
#define UART15_RX_DMA_IRQ DMA2_Channel6_IRQn
#define UART15_RX_DMA_HANDSHAK DMA_CH_HARDWARE_HANDSHAKING_IF_6
#define UART15_RX_DMA_DMA_RCC RCC_AHB1_PERIPHEN_M7_DMA2
#define UART15_RX_DMA_DMA_CHANNEL DMA_CHANNEL_6
#define UART15_RX_DMA_DMAMUX_CHANNEL DMAMUX_CHANNEL_14
#define UART15_RX_DMA_DMAMUX_REQUEST DMAMUX1_REQUEST_UART15_RX
#elif defined(BSP_SPI2_RX_USING_DMA) && !defined(SPI2_RX_DMA_INSTANCE)
#define SPI2_RX_DMA_INSTANCE DMA2
#define SPI2_RX_DMA_IRQHandler DMA2_Channel6_IRQHandler
#define SPI2_RX_DMA_IRQ DMA2_Channel6_IRQn
#define SPI2_RX_DMA_HANDSHAK DMA_CH_HARDWARE_HANDSHAKING_IF_6
#define SPI2_RX_DMA_DMA_RCC RCC_AHB1_PERIPHEN_M7_DMA2
#define SPI2_RX_DMA_DMA_CHANNEL DMA_CHANNEL_6
#define SPI2_RX_DMA_DMAMUX_CHANNEL DMAMUX_CHANNEL_14
#define SPI2_RX_DMA_DMAMUX_REQUEST DMAMUX1_REQUEST_SPI2_RX
#endif
/* DMAMUX1 channel15 / DMA2 channel7 */
#if defined(BSP_I2C6_RX_USING_DMA) && !defined(I2C6_RX_DMA_INSTANCE)
#define I2C6_RX_DMA_INSTANCE DMA2
#define I2C6_RX_DMA_IRQHandler DMA2_Channel7_IRQHandler
#define I2C6_RX_DMA_IRQ DMA2_Channel7_IRQn
#define I2C6_RX_DMA_HANDSHAK DMA_CH_HARDWARE_HANDSHAKING_IF_7
#define I2C6_RX_DMA_DMA_RCC RCC_AHB1_PERIPHEN_M7_DMA2
#define I2C6_RX_DMA_DMA_CHANNEL DMA_CHANNEL_5
#define I2C6_RX_DMA_DMAMUX_CHANNEL DMAMUX_CHANNEL_15
#define I2C6_RX_DMA_DMAMUX_REQUEST DMAMUX1_REQUEST_I2C6_RX
#elif defined(BSP_LPUART1_RX_USING_DMA) && !defined(LPUART1_RX_DMA_INSTANCE)
#define LPUART1_RX_DMA_INSTANCE DMA2
#define LPUART1_RX_DMA_IRQHandler DMA2_Channel7_IRQHandler
#define LPUART1_RX_DMA_IRQ DMA2_Channel7_IRQn
#define LPUART1_RX_DMA_HANDSHAK DMA_CH_HARDWARE_HANDSHAKING_IF_7
#define LPUART1_RX_DMA_DMA_RCC RCC_AHB1_PERIPHEN_M7_DMA2
#define LPUART1_RX_DMA_DMA_CHANNEL DMA_CHANNEL_5
#define LPUART1_RX_DMA_DMAMUX_CHANNEL DMAMUX_CHANNEL_15
#define LPUART1_RX_DMA_DMAMUX_REQUEST DMAMUX1_REQUEST_LPUART1_RX
#elif defined(BSP_SPI3_RX_USING_DMA) && !defined(SPI3_RX_DMA_INSTANCE)
#define SPI3_RX_DMA_INSTANCE DMA2
#define SPI3_RX_DMA_IRQHandler DMA2_Channel7_IRQHandler
#define SPI3_RX_DMA_IRQ DMA2_Channel7_IRQn
#define SPI3_RX_DMA_HANDSHAK DMA_CH_HARDWARE_HANDSHAKING_IF_7
#define SPI3_RX_DMA_DMA_RCC RCC_AHB1_PERIPHEN_M7_DMA2
#define SPI3_RX_DMA_DMA_CHANNEL DMA_CHANNEL_5
#define SPI3_RX_DMA_DMAMUX_CHANNEL DMAMUX_CHANNEL_15
#define SPI3_RX_DMA_DMAMUX_REQUEST DMAMUX1_REQUEST_SPI3_RX
#endif
/* DMAMUX1 channel16 / DMA3 channel0 */
#if defined(BSP_I2C7_RX_USING_DMA) && !defined(I2C7_RX_DMA_INSTANCE)
#define I2C7_RX_DMA_INSTANCE DMA3
#define I2C7_RX_DMA_IRQHandler DMA3_Channel0_IRQHandler
#define I2C7_RX_DMA_IRQ DMA3_Channel0_IRQn
#define I2C7_RX_DMA_HANDSHAK DMA_CH_HARDWARE_HANDSHAKING_IF_0
#define I2C7_RX_DMA_DMA_RCC RCC_AHB1_PERIPHEN_M7_DMA3
#define I2C7_RX_DMA_DMA_CHANNEL DMA_CHANNEL_0
#define I2C7_RX_DMA_DMAMUX_CHANNEL DMAMUX_CHANNEL_16
#define I2C7_RX_DMA_DMAMUX_REQUEST DMAMUX1_REQUEST_I2C7_RX
#elif defined(BSP_LPUART2_RX_USING_DMA) && !defined(LPUART2_RX_DMA_INSTANCE)
#define LPUART2_RX_DMA_INSTANCE DMA3
#define LPUART2_RX_DMA_IRQHandler DMA3_Channel0_IRQHandler
#define LPUART2_RX_DMA_IRQ DMA3_Channel0_IRQn
#define LPUART2_RX_DMA_HANDSHAK DMA_CH_HARDWARE_HANDSHAKING_IF_0
#define LPUART2_RX_DMA_DMA_RCC RCC_AHB1_PERIPHEN_M7_DMA3
#define LPUART2_RX_DMA_DMA_CHANNEL DMA_CHANNEL_0
#define LPUART2_RX_DMA_DMAMUX_CHANNEL DMAMUX_CHANNEL_16
#define LPUART2_RX_DMA_DMAMUX_REQUEST DMAMUX1_REQUEST_LPUART2_RX
#elif defined(BSP_SPI4_RX_USING_DMA) && !defined(SPI4_RX_DMA_INSTANCE)
#define SPI4_RX_DMA_INSTANCE DMA3
#define SPI4_RX_DMA_IRQHandler DMA3_Channel0_IRQHandler
#define SPI4_RX_DMA_IRQ DMA3_Channel0_IRQn
#define SPI4_RX_DMA_HANDSHAK DMA_CH_HARDWARE_HANDSHAKING_IF_0
#define SPI4_RX_DMA_DMA_RCC RCC_AHB1_PERIPHEN_M7_DMA3
#define SPI4_RX_DMA_DMA_CHANNEL DMA_CHANNEL_0
#define SPI4_RX_DMA_DMAMUX_CHANNEL DMAMUX_CHANNEL_16
#define SPI4_RX_DMA_DMAMUX_REQUEST DMAMUX1_REQUEST_SPI4_RX
#endif
/* DMAMUX1 channel17 / DMA3 channel1 */
#if defined(BSP_I2C8_RX_USING_DMA) && !defined(I2C8_RX_DMA_INSTANCE)
#define I2C8_RX_DMA_INSTANCE DMA3
#define I2C8_RX_DMA_IRQHandler DMA3_Channel1_IRQHandler
#define I2C8_RX_DMA_IRQ DMA3_Channel1_IRQn
#define I2C8_RX_DMA_HANDSHAK DMA_CH_HARDWARE_HANDSHAKING_IF_1
#define I2C8_RX_DMA_DMA_RCC RCC_AHB1_PERIPHEN_M7_DMA3
#define I2C8_RX_DMA_DMA_CHANNEL DMA_CHANNEL_1
#define I2C8_RX_DMA_DMAMUX_CHANNEL DMAMUX_CHANNEL_17
#define I2C8_RX_DMA_DMAMUX_REQUEST DMAMUX1_REQUEST_I2C8_RX
#elif defined(BSP_UART1_TX_USING_DMA) && !defined(UART1_TX_DMA_INSTANCE)
#define UART1_TX_DMA_INSTANCE DMA3
#define UART1_TX_DMA_IRQHandler DMA3_Channel1_IRQHandler
#define UART1_TX_DMA_IRQ DMA3_Channel1_IRQn
#define UART1_TX_DMA_HANDSHAK DMA_CH_HARDWARE_HANDSHAKING_IF_1
#define UART1_TX_DMA_DMA_RCC RCC_AHB1_PERIPHEN_M7_DMA3
#define UART1_TX_DMA_DMA_CHANNEL DMA_CHANNEL_1
#define UART1_TX_DMA_DMAMUX_CHANNEL DMAMUX_CHANNEL_17
#define UART1_TX_DMA_DMAMUX_REQUEST DMAMUX1_REQUEST_USART1_TX
#elif defined(BSP_SPI5_RX_USING_DMA) && !defined(SPI5_RX_DMA_INSTANCE)
#define SPI5_RX_DMA_INSTANCE DMA3
#define SPI5_RX_DMA_IRQHandler DMA3_Channel1_IRQHandler
#define SPI5_RX_DMA_IRQ DMA3_Channel1_IRQn
#define SPI5_RX_DMA_HANDSHAK DMA_CH_HARDWARE_HANDSHAKING_IF_1
#define SPI5_RX_DMA_DMA_RCC RCC_AHB1_PERIPHEN_M7_DMA3
#define SPI5_RX_DMA_DMA_CHANNEL DMA_CHANNEL_1
#define SPI5_RX_DMA_DMAMUX_CHANNEL DMAMUX_CHANNEL_17
#define SPI5_RX_DMA_DMAMUX_REQUEST DMAMUX1_REQUEST_SPI5_RX
#endif
/* DMAMUX1 channel18 / DMA3 channel2 */
#if defined(BSP_I2C9_RX_USING_DMA) && !defined(I2C9_RX_DMA_INSTANCE)
#define I2C9_RX_DMA_INSTANCE DMA3
#define I2C9_RX_DMA_IRQHandler DMA3_Channel2_IRQHandler
#define I2C9_RX_DMA_IRQ DMA3_Channel2_IRQn
#define I2C9_RX_DMA_HANDSHAK DMA_CH_HARDWARE_HANDSHAKING_IF_2
#define I2C9_RX_DMA_DMA_RCC RCC_AHB1_PERIPHEN_M7_DMA3
#define I2C9_RX_DMA_DMA_CHANNEL DMA_CHANNEL_2
#define I2C9_RX_DMA_DMAMUX_CHANNEL DMAMUX_CHANNEL_18
#define I2C9_RX_DMA_DMAMUX_REQUEST DMAMUX1_REQUEST_I2C9_RX
#elif defined(BSP_UART2_TX_USING_DMA) && !defined(UART2_TX_DMA_INSTANCE)
#define UART2_TX_DMA_INSTANCE DMA3
#define UART2_TX_DMA_IRQHandler DMA3_Channel2_IRQHandler
#define UART2_TX_DMA_IRQ DMA3_Channel2_IRQn
#define UART2_TX_DMA_HANDSHAK DMA_CH_HARDWARE_HANDSHAKING_IF_2
#define UART2_TX_DMA_DMA_RCC RCC_AHB1_PERIPHEN_M7_DMA3
#define UART2_TX_DMA_DMA_CHANNEL DMA_CHANNEL_2
#define UART2_TX_DMA_DMAMUX_CHANNEL DMAMUX_CHANNEL_18
#define UART2_TX_DMA_DMAMUX_REQUEST DMAMUX1_REQUEST_USART2_TX
#elif defined(BSP_SPI6_RX_USING_DMA) && !defined(SPI6_RX_DMA_INSTANCE)
#define SPI6_RX_DMA_INSTANCE DMA3
#define SPI6_RX_DMA_IRQHandler DMA3_Channel2_IRQHandler
#define SPI6_RX_DMA_IRQ DMA3_Channel2_IRQn
#define SPI6_RX_DMA_HANDSHAK DMA_CH_HARDWARE_HANDSHAKING_IF_2
#define SPI6_RX_DMA_DMA_RCC RCC_AHB1_PERIPHEN_M7_DMA3
#define SPI6_RX_DMA_DMA_CHANNEL DMA_CHANNEL_2
#define SPI6_RX_DMA_DMAMUX_CHANNEL DMAMUX_CHANNEL_18
#define SPI6_RX_DMA_DMAMUX_REQUEST DMAMUX1_REQUEST_SPI6_RX
#endif
/* DMAMUX1 channel19 / DMA3 channel3 */
#if defined(BSP_I2C10_RX_USING_DMA) && !defined(I2C10_RX_DMA_INSTANCE)
#define I2C10_RX_DMA_INSTANCE DMA3
#define I2C10_RX_DMA_IRQHandler DMA3_Channel3_IRQHandler
#define I2C10_RX_DMA_IRQ DMA3_Channel3_IRQn
#define I2C10_RX_DMA_HANDSHAK DMA_CH_HARDWARE_HANDSHAKING_IF_3
#define I2C10_RX_DMA_DMA_RCC RCC_AHB1_PERIPHEN_M7_DMA3
#define I2C10_RX_DMA_DMA_CHANNEL DMA_CHANNEL_3
#define I2C10_RX_DMA_DMAMUX_CHANNEL DMAMUX_CHANNEL_19
#define I2C10_RX_DMA_DMAMUX_REQUEST DMAMUX1_REQUEST_I2C10_RX
#elif defined(BSP_UART3_TX_USING_DMA) && !defined(UART3_TX_DMA_INSTANCE)
#define UART3_TX_DMA_INSTANCE DMA3
#define UART3_TX_DMA_IRQHandler DMA3_Channel3_IRQHandler
#define UART3_TX_DMA_IRQ DMA3_Channel3_IRQn
#define UART3_TX_DMA_HANDSHAK DMA_CH_HARDWARE_HANDSHAKING_IF_3
#define UART3_TX_DMA_DMA_RCC RCC_AHB1_PERIPHEN_M7_DMA3
#define UART3_TX_DMA_DMA_CHANNEL DMA_CHANNEL_3
#define UART3_TX_DMA_DMAMUX_CHANNEL DMAMUX_CHANNEL_19
#define UART3_TX_DMA_DMAMUX_REQUEST DMAMUX1_REQUEST_USART3_TX
#elif defined(BSP_SPI7_RX_USING_DMA) && !defined(SPI7_RX_DMA_INSTANCE)
#define SPI7_RX_DMA_INSTANCE DMA3
#define SPI7_RX_DMA_IRQHandler DMA3_Channel3_IRQHandler
#define SPI7_RX_DMA_IRQ DMA3_Channel3_IRQn
#define SPI7_RX_DMA_HANDSHAK DMA_CH_HARDWARE_HANDSHAKING_IF_3
#define SPI7_RX_DMA_DMA_RCC RCC_AHB1_PERIPHEN_M7_DMA3
#define SPI7_RX_DMA_DMA_CHANNEL DMA_CHANNEL_3
#define SPI7_RX_DMA_DMAMUX_CHANNEL DMAMUX_CHANNEL_19
#define SPI7_RX_DMA_DMAMUX_REQUEST DMAMUX1_REQUEST_SPI7_RX
#endif
/* DMAMUX1 channel20 / DMA3 channel4 */
#if defined(BSP_I2C1_TX_USING_DMA) && !defined(I2C1_TX_DMA_INSTANCE)
#define I2C1_TX_DMA_INSTANCE DMA3
#define I2C1_TX_DMA_IRQHandler DMA3_Channel4_IRQHandler
#define I2C1_TX_DMA_IRQ DMA3_Channel4_IRQn
#define I2C1_TX_DMA_HANDSHAK DMA_CH_HARDWARE_HANDSHAKING_IF_4
#define I2C1_TX_DMA_DMA_RCC RCC_AHB1_PERIPHEN_M7_DMA3
#define I2C1_TX_DMA_DMA_CHANNEL DMA_CHANNEL_4
#define I2C1_TX_DMA_DMAMUX_CHANNEL DMAMUX_CHANNEL_20
#define I2C1_TX_DMA_DMAMUX_REQUEST DMAMUX1_REQUEST_I2C1_TX
#elif defined(BSP_UART4_TX_USING_DMA) && !defined(UART4_TX_DMA_INSTANCE)
#define UART4_TX_DMA_INSTANCE DMA3
#define UART4_TX_DMA_IRQHandler DMA3_Channel4_IRQHandler
#define UART4_TX_DMA_IRQ DMA3_Channel4_IRQn
#define UART4_TX_DMA_HANDSHAK DMA_CH_HARDWARE_HANDSHAKING_IF_4
#define UART4_TX_DMA_DMA_RCC RCC_AHB1_PERIPHEN_M7_DMA3
#define UART4_TX_DMA_DMA_CHANNEL DMA_CHANNEL_4
#define UART4_TX_DMA_DMAMUX_CHANNEL DMAMUX_CHANNEL_20
#define UART4_TX_DMA_DMAMUX_REQUEST DMAMUX1_REQUEST_USART4_TX
#endif
/* DMAMUX1 channel21 / DMA3 channel5 */
#if defined(BSP_I2C2_TX_USING_DMA) && !defined(I2C2_TX_DMA_INSTANCE)
#define I2C2_TX_DMA_INSTANCE DMA3
#define I2C2_TX_DMA_IRQHandler DMA3_Channel5_IRQHandler
#define I2C2_TX_DMA_IRQ DMA3_Channel5_IRQn
#define I2C2_TX_DMA_HANDSHAK DMA_CH_HARDWARE_HANDSHAKING_IF_5
#define I2C2_TX_DMA_DMA_RCC RCC_AHB1_PERIPHEN_M7_DMA3
#define I2C2_TX_DMA_DMA_CHANNEL DMA_CHANNEL_5
#define I2C2_TX_DMA_DMAMUX_CHANNEL DMAMUX_CHANNEL_21
#define I2C2_TX_DMA_DMAMUX_REQUEST DMAMUX1_REQUEST_I2C2_TX
#elif defined(BSP_UART5_TX_USING_DMA) && !defined(UART5_TX_DMA_INSTANCE)
#define UART5_TX_DMA_INSTANCE DMA3
#define UART5_TX_DMA_IRQHandler DMA3_Channel5_IRQHandler
#define UART5_TX_DMA_IRQ DMA3_Channel5_IRQn
#define UART5_TX_DMA_HANDSHAK DMA_CH_HARDWARE_HANDSHAKING_IF_5
#define UART5_TX_DMA_DMA_RCC RCC_AHB1_PERIPHEN_M7_DMA3
#define UART5_TX_DMA_DMA_CHANNEL DMA_CHANNEL_5
#define UART5_TX_DMA_DMAMUX_CHANNEL DMAMUX_CHANNEL_21
#define UART5_TX_DMA_DMAMUX_REQUEST DMAMUX1_REQUEST_USART5_TX
#endif
/* DMAMUX1 channel22 / DMA3 channel6 */
#if defined(BSP_I2C3_TX_USING_DMA) && !defined(I2C3_TX_DMA_INSTANCE)
#define I2C3_TX_DMA_INSTANCE DMA3
#define I2C3_TX_DMA_IRQHandler DMA3_Channel6_IRQHandler
#define I2C3_TX_DMA_IRQ DMA3_Channel6_IRQn
#define I2C3_TX_DMA_HANDSHAK DMA_CH_HARDWARE_HANDSHAKING_IF_6
#define I2C3_TX_DMA_DMA_RCC RCC_AHB1_PERIPHEN_M7_DMA3
#define I2C3_TX_DMA_DMA_CHANNEL DMA_CHANNEL_6
#define I2C3_TX_DMA_DMAMUX_CHANNEL DMAMUX_CHANNEL_22
#define I2C3_TX_DMA_DMAMUX_REQUEST DMAMUX1_REQUEST_I2C3_TX
#elif defined(BSP_UART6_TX_USING_DMA) && !defined(UART6_TX_DMA_INSTANCE)
#define UART6_TX_DMA_INSTANCE DMA3
#define UART6_TX_DMA_IRQHandler DMA3_Channel6_IRQHandler
#define UART6_TX_DMA_IRQ DMA3_Channel6_IRQn
#define UART6_TX_DMA_HANDSHAK DMA_CH_HARDWARE_HANDSHAKING_IF_6
#define UART6_TX_DMA_DMA_RCC RCC_AHB1_PERIPHEN_M7_DMA3
#define UART6_TX_DMA_DMA_CHANNEL DMA_CHANNEL_6
#define UART6_TX_DMA_DMAMUX_CHANNEL DMAMUX_CHANNEL_22
#define UART6_TX_DMA_DMAMUX_REQUEST DMAMUX1_REQUEST_USART6_TX
#endif
/* DMAMUX1 channel23 / DMA3 channel7 */
#if defined(BSP_I2C4_TX_USING_DMA) && !defined(I2C4_TX_DMA_INSTANCE)
#define I2C4_TX_DMA_INSTANCE DMA3
#define I2C4_TX_DMA_IRQHandler DMA3_Channel7_IRQHandler
#define I2C4_TX_DMA_IRQ DMA3_Channel7_IRQn
#define I2C4_TX_DMA_HANDSHAK DMA_CH_HARDWARE_HANDSHAKING_IF_7
#define I2C4_TX_DMA_DMA_RCC RCC_AHB1_PERIPHEN_M7_DMA3
#define I2C4_TX_DMA_DMA_CHANNEL DMA_CHANNEL_7
#define I2C4_TX_DMA_DMAMUX_CHANNEL DMAMUX_CHANNEL_23
#define I2C4_TX_DMA_DMAMUX_REQUEST DMAMUX1_REQUEST_I2C4_TX
#elif defined(BSP_UART7_TX_USING_DMA) && !defined(UART7_TX_DMA_INSTANCE)
#define UART7_TX_DMA_INSTANCE DMA3
#define UART7_TX_DMA_IRQHandler DMA3_Channel7_IRQHandler
#define UART7_TX_DMA_IRQ DMA3_Channel7_IRQn
#define UART7_TX_DMA_HANDSHAK DMA_CH_HARDWARE_HANDSHAKING_IF_7
#define UART7_TX_DMA_DMA_RCC RCC_AHB1_PERIPHEN_M7_DMA3
#define UART7_TX_DMA_DMA_CHANNEL DMA_CHANNEL_7
#define UART7_TX_DMA_DMAMUX_CHANNEL DMAMUX_CHANNEL_23
#define UART7_TX_DMA_DMAMUX_REQUEST DMAMUX1_REQUEST_USART7_TX
#endif
#ifdef __cplusplus
}
#endif
#endif /* __DMA_CONFIG_H__ */

366
bsp/n32/n32hxxx/libraries/N32_Drivers/drivers/config/h7/i2c_hard_config.h → bsp/n32/n32hxxx/libraries/N32_Drivers/drivers/config/h7xx/i2c_hard_config.h
View File

@ -38,34 +38,33 @@ extern "C" {
#endif /* BSP_USING_HARD_I2C1 */
#ifdef BSP_I2C1_RX_USING_DMA
#ifndef I2C1_RX_DMA_CONFIG
#define I2C1_RX_DMA_CONFIG \
{ \
.Instance = I2C1_RX_DMA_INSTANCE, \
.dma_irq = I2C1_RX_DMA_IRQ, \
.HsInterface = I2C1_RX_DMA_HANDSHAK, \
.dma_rcc = I2C1_RX_DMA_DMA_RCC, \
.dma_channel = I2C1_RX_DMA_DMA_CHANNEL, \
.dmamux_channel = I2C1_RX_DMA_DMAMUX_CHANNEL, \
.dmamux_request = I2C1_RX_DMA_DMAMUX_REQUEST, \
#define I2C1_RX_DMA_CONFIG \
{ \
.Instance = I2C1_RX_DMA_INSTANCE, \
.dma_irq = I2C1_RX_DMA_IRQ, \
.HsInterface = I2C1_RX_DMA_HANDSHAK, \
.dma_rcc = I2C1_RX_DMA_DMA_RCC, \
.dma_channel = I2C1_RX_DMA_DMA_CHANNEL, \
.dmamux_channel = I2C1_RX_DMA_DMAMUX_CHANNEL, \
.dmamux_request = I2C1_RX_DMA_DMAMUX_REQUEST, \
}
#endif /* I2C1_RX_DMA_CONFIG */
#endif /* BSP_I2C1_RX_USING_DMA */
#ifdef BSP_I2C1_TX_USING_DMA
#ifndef I2C1_TX_DMA_CONFIG
#define I2C1_TX_DMA_CONFIG \
{ \
.Instance = I2C1_TX_DMA_INSTANCE, \
.dma_irq = I2C1_TX_DMA_IRQ, \
.HsInterface = I2C1_TX_DMA_HANDSHAK, \
.dma_rcc = I2C1_TX_DMA_DMA_RCC, \
.dma_channel = I2C1_TX_DMA_DMA_CHANNEL, \
.dmamux_channel = I2C1_TX_DMA_DMAMUX_CHANNEL, \
.dmamux_request = I2C1_TX_DMA_DMAMUX_REQUEST, \
#define I2C1_TX_DMA_CONFIG \
{ \
.Instance = I2C1_TX_DMA_INSTANCE, \
.dma_irq = I2C1_TX_DMA_IRQ, \
.HsInterface = I2C1_TX_DMA_HANDSHAK, \
.dma_rcc = I2C1_TX_DMA_DMA_RCC, \
.dma_channel = I2C1_TX_DMA_DMA_CHANNEL, \
.dmamux_channel = I2C1_TX_DMA_DMAMUX_CHANNEL, \
.dmamux_request = I2C1_TX_DMA_DMAMUX_REQUEST, \
}
#endif /* I2C1_TX_DMA_CONFIG */
#endif /* BSP_I2C1_TX_USING_DMA */
#ifdef BSP_USING_HARD_I2C2
#ifndef I2C2_BUS_CONFIG
#define I2C2_BUS_CONFIG \
@ -87,34 +86,33 @@ extern "C" {
#endif /* BSP_USING_HARD_I2C2 */
#ifdef BSP_I2C2_RX_USING_DMA
#ifndef I2C2_RX_DMA_CONFIG
#define I2C2_RX_DMA_CONFIG \
{ \
.Instance = I2C2_RX_DMA_INSTANCE, \
.dma_irq = I2C2_RX_DMA_IRQ, \
.HsInterface = I2C2_RX_DMA_HANDSHAK, \
.dma_rcc = I2C2_RX_DMA_DMA_RCC, \
.dma_channel = I2C2_RX_DMA_DMA_CHANNEL, \
.dmamux_channel = I2C2_RX_DMA_DMAMUX_CHANNEL, \
.dmamux_request = I2C2_RX_DMA_DMAMUX_REQUEST, \
#define I2C2_RX_DMA_CONFIG \
{ \
.Instance = I2C2_RX_DMA_INSTANCE, \
.dma_irq = I2C2_RX_DMA_IRQ, \
.HsInterface = I2C2_RX_DMA_HANDSHAK, \
.dma_rcc = I2C2_RX_DMA_DMA_RCC, \
.dma_channel = I2C2_RX_DMA_DMA_CHANNEL, \
.dmamux_channel = I2C2_RX_DMA_DMAMUX_CHANNEL, \
.dmamux_request = I2C2_RX_DMA_DMAMUX_REQUEST, \
}
#endif /* I2C2_RX_DMA_CONFIG */
#endif /* BSP_I2C2_RX_USING_DMA */
#ifdef BSP_I2C2_TX_USING_DMA
#ifndef I2C2_TX_DMA_CONFIG
#define I2C2_TX_DMA_CONFIG \
{ \
.Instance = I2C2_TX_DMA_INSTANCE, \
.dma_irq = I2C2_TX_DMA_IRQ, \
.HsInterface = I2C2_TX_DMA_HANDSHAK, \
.dma_rcc = I2C2_TX_DMA_DMA_RCC, \
.dma_channel = I2C2_TX_DMA_DMA_CHANNEL, \
.dmamux_channel = I2C2_TX_DMA_DMAMUX_CHANNEL, \
.dmamux_request = I2C2_TX_DMA_DMAMUX_REQUEST, \
#define I2C2_TX_DMA_CONFIG \
{ \
.Instance = I2C2_TX_DMA_INSTANCE, \
.dma_irq = I2C2_TX_DMA_IRQ, \
.HsInterface = I2C2_TX_DMA_HANDSHAK, \
.dma_rcc = I2C2_TX_DMA_DMA_RCC, \
.dma_channel = I2C2_TX_DMA_DMA_CHANNEL, \
.dmamux_channel = I2C2_TX_DMA_DMAMUX_CHANNEL, \
.dmamux_request = I2C2_TX_DMA_DMAMUX_REQUEST, \
}
#endif /* I2C2_TX_DMA_CONFIG */
#endif /* BSP_I2C2_TX_USING_DMA */
#ifdef BSP_USING_HARD_I2C3
#ifndef I2C3_BUS_CONFIG
#define I2C3_BUS_CONFIG \
@ -136,34 +134,33 @@ extern "C" {
#endif /* BSP_USING_HARD_I2C3 */
#ifdef BSP_I2C3_RX_USING_DMA
#ifndef I2C3_RX_DMA_CONFIG
#define I2C3_RX_DMA_CONFIG \
{ \
.Instance = I2C3_RX_DMA_INSTANCE, \
.dma_irq = I2C3_RX_DMA_IRQ, \
.HsInterface = I2C3_RX_DMA_HANDSHAK, \
.dma_rcc = I2C3_RX_DMA_DMA_RCC, \
.dma_channel = I2C3_RX_DMA_DMA_CHANNEL, \
.dmamux_channel = I2C3_RX_DMA_DMAMUX_CHANNEL, \
.dmamux_request = I2C3_RX_DMA_DMAMUX_REQUEST, \
#define I2C3_RX_DMA_CONFIG \
{ \
.Instance = I2C3_RX_DMA_INSTANCE, \
.dma_irq = I2C3_RX_DMA_IRQ, \
.HsInterface = I2C3_RX_DMA_HANDSHAK, \
.dma_rcc = I2C3_RX_DMA_DMA_RCC, \
.dma_channel = I2C3_RX_DMA_DMA_CHANNEL, \
.dmamux_channel = I2C3_RX_DMA_DMAMUX_CHANNEL, \
.dmamux_request = I2C3_RX_DMA_DMAMUX_REQUEST, \
}
#endif /* I2C3_RX_DMA_CONFIG */
#endif /* BSP_I2C3_RX_USING_DMA */
#ifdef BSP_I2C3_TX_USING_DMA
#ifndef I2C3_TX_DMA_CONFIG
#define I2C3_TX_DMA_CONFIG \
{ \
.Instance = I2C3_TX_DMA_INSTANCE, \
.dma_irq = I2C3_TX_DMA_IRQ, \
.HsInterface = I2C3_TX_DMA_HANDSHAK, \
.dma_rcc = I2C3_TX_DMA_DMA_RCC, \
.dma_channel = I2C3_TX_DMA_DMA_CHANNEL, \
.dmamux_channel = I2C3_TX_DMA_DMAMUX_CHANNEL, \
.dmamux_request = I2C3_TX_DMA_DMAMUX_REQUEST, \
#define I2C3_TX_DMA_CONFIG \
{ \
.Instance = I2C3_TX_DMA_INSTANCE, \
.dma_irq = I2C3_TX_DMA_IRQ, \
.HsInterface = I2C3_TX_DMA_HANDSHAK, \
.dma_rcc = I2C3_TX_DMA_DMA_RCC, \
.dma_channel = I2C3_TX_DMA_DMA_CHANNEL, \
.dmamux_channel = I2C3_TX_DMA_DMAMUX_CHANNEL, \
.dmamux_request = I2C3_TX_DMA_DMAMUX_REQUEST, \
}
#endif /* I2C3_TX_DMA_CONFIG */
#endif /* BSP_I2C3_TX_USING_DMA */
#ifdef BSP_USING_HARD_I2C4
#ifndef I2C4_BUS_CONFIG
#define I2C4_BUS_CONFIG \
@ -185,34 +182,33 @@ extern "C" {
#endif /* BSP_USING_HARD_I2C4 */
#ifdef BSP_I2C4_RX_USING_DMA
#ifndef I2C4_RX_DMA_CONFIG
#define I2C4_RX_DMA_CONFIG \
{ \
.Instance = I2C4_RX_DMA_INSTANCE, \
.dma_irq = I2C4_RX_DMA_IRQ, \
.HsInterface = I2C4_RX_DMA_HANDSHAK, \
.dma_rcc = I2C4_RX_DMA_DMA_RCC, \
.dma_channel = I2C4_RX_DMA_DMA_CHANNEL, \
.dmamux_channel = I2C4_RX_DMA_DMAMUX_CHANNEL, \
.dmamux_request = I2C4_RX_DMA_DMAMUX_REQUEST, \
#define I2C4_RX_DMA_CONFIG \
{ \
.Instance = I2C4_RX_DMA_INSTANCE, \
.dma_irq = I2C4_RX_DMA_IRQ, \
.HsInterface = I2C4_RX_DMA_HANDSHAK, \
.dma_rcc = I2C4_RX_DMA_DMA_RCC, \
.dma_channel = I2C4_RX_DMA_DMA_CHANNEL, \
.dmamux_channel = I2C4_RX_DMA_DMAMUX_CHANNEL, \
.dmamux_request = I2C4_RX_DMA_DMAMUX_REQUEST, \
}
#endif /* I2C4_RX_DMA_CONFIG */
#endif /* BSP_I2C4_RX_USING_DMA */
#ifdef BSP_I2C4_TX_USING_DMA
#ifndef I2C4_TX_DMA_CONFIG
#define I2C4_TX_DMA_CONFIG \
{ \
.Instance = I2C4_TX_DMA_INSTANCE, \
.dma_irq = I2C4_TX_DMA_IRQ, \
.HsInterface = I2C4_TX_DMA_HANDSHAK, \
.dma_rcc = I2C4_TX_DMA_DMA_RCC, \
.dma_channel = I2C4_TX_DMA_DMA_CHANNEL, \
.dmamux_channel = I2C4_TX_DMA_DMAMUX_CHANNEL, \
.dmamux_request = I2C4_TX_DMA_DMAMUX_REQUEST, \
#define I2C4_TX_DMA_CONFIG \
{ \
.Instance = I2C4_TX_DMA_INSTANCE, \
.dma_irq = I2C4_TX_DMA_IRQ, \
.HsInterface = I2C4_TX_DMA_HANDSHAK, \
.dma_rcc = I2C4_TX_DMA_DMA_RCC, \
.dma_channel = I2C4_TX_DMA_DMA_CHANNEL, \
.dmamux_channel = I2C4_TX_DMA_DMAMUX_CHANNEL, \
.dmamux_request = I2C4_TX_DMA_DMAMUX_REQUEST, \
}
#endif /* I2C4_TX_DMA_CONFIG */
#endif /* BSP_I2C4_TX_USING_DMA */
#ifdef BSP_USING_HARD_I2C5
#ifndef I2C5_BUS_CONFIG
#define I2C5_BUS_CONFIG \
@ -234,34 +230,33 @@ extern "C" {
#endif /* BSP_USING_HARD_I2C5 */
#ifdef BSP_I2C5_RX_USING_DMA
#ifndef I2C5_RX_DMA_CONFIG
#define I2C5_RX_DMA_CONFIG \
{ \
.Instance = I2C5_RX_DMA_INSTANCE, \
.dma_irq = I2C5_RX_DMA_IRQ, \
.HsInterface = I2C5_RX_DMA_HANDSHAK, \
.dma_rcc = I2C5_RX_DMA_DMA_RCC, \
.dma_channel = I2C5_RX_DMA_DMA_CHANNEL, \
.dmamux_channel = I2C5_RX_DMA_DMAMUX_CHANNEL, \
.dmamux_request = I2C5_RX_DMA_DMAMUX_REQUEST, \
#define I2C5_RX_DMA_CONFIG \
{ \
.Instance = I2C5_RX_DMA_INSTANCE, \
.dma_irq = I2C5_RX_DMA_IRQ, \
.HsInterface = I2C5_RX_DMA_HANDSHAK, \
.dma_rcc = I2C5_RX_DMA_DMA_RCC, \
.dma_channel = I2C5_RX_DMA_DMA_CHANNEL, \
.dmamux_channel = I2C5_RX_DMA_DMAMUX_CHANNEL, \
.dmamux_request = I2C5_RX_DMA_DMAMUX_REQUEST, \
}
#endif /* I2C5_RX_DMA_CONFIG */
#endif /* BSP_I2C5_RX_USING_DMA */
#ifdef BSP_I2C5_TX_USING_DMA
#ifndef I2C5_TX_DMA_CONFIG
#define I2C5_TX_DMA_CONFIG \
{ \
.Instance = I2C5_TX_DMA_INSTANCE, \
.dma_irq = I2C5_TX_DMA_IRQ, \
.HsInterface = I2C5_TX_DMA_HANDSHAK, \
.dma_rcc = I2C5_TX_DMA_DMA_RCC, \
.dma_channel = I2C5_TX_DMA_DMA_CHANNEL, \
.dmamux_channel = I2C5_TX_DMA_DMAMUX_CHANNEL, \
.dmamux_request = I2C5_TX_DMA_DMAMUX_REQUEST, \
#define I2C5_TX_DMA_CONFIG \
{ \
.Instance = I2C5_TX_DMA_INSTANCE, \
.dma_irq = I2C5_TX_DMA_IRQ, \
.HsInterface = I2C5_TX_DMA_HANDSHAK, \
.dma_rcc = I2C5_TX_DMA_DMA_RCC, \
.dma_channel = I2C5_TX_DMA_DMA_CHANNEL, \
.dmamux_channel = I2C5_TX_DMA_DMAMUX_CHANNEL, \
.dmamux_request = I2C5_TX_DMA_DMAMUX_REQUEST, \
}
#endif /* I2C5_TX_DMA_CONFIG */
#endif /* BSP_I2C5_TX_USING_DMA */
#ifdef BSP_USING_HARD_I2C6
#ifndef I2C6_BUS_CONFIG
#define I2C6_BUS_CONFIG \
@ -283,29 +278,29 @@ extern "C" {
#endif /* BSP_USING_HARD_I2C6 */
#ifdef BSP_I2C6_RX_USING_DMA
#ifndef I2C6_RX_DMA_CONFIG
#define I2C6_RX_DMA_CONFIG \
{ \
.Instance = I2C6_RX_DMA_INSTANCE, \
.dma_irq = I2C6_RX_DMA_IRQ, \
.HsInterface = I2C6_RX_DMA_HANDSHAK, \
.dma_rcc = I2C6_RX_DMA_DMA_RCC, \
.dma_channel = I2C6_RX_DMA_DMA_CHANNEL, \
.dmamux_channel = I2C6_RX_DMA_DMAMUX_CHANNEL, \
.dmamux_request = I2C6_RX_DMA_DMAMUX_REQUEST, \
#define I2C6_RX_DMA_CONFIG \
{ \
.Instance = I2C6_RX_DMA_INSTANCE, \
.dma_irq = I2C6_RX_DMA_IRQ, \
.HsInterface = I2C6_RX_DMA_HANDSHAK, \
.dma_rcc = I2C6_RX_DMA_DMA_RCC, \
.dma_channel = I2C6_RX_DMA_DMA_CHANNEL, \
.dmamux_channel = I2C6_RX_DMA_DMAMUX_CHANNEL, \
.dmamux_request = I2C6_RX_DMA_DMAMUX_REQUEST, \
}
#endif /* I2C6_RX_DMA_CONFIG */
#endif /* BSP_I2C6_RX_USING_DMA */
#ifdef BSP_I2C6_TX_USING_DMA
#ifndef I2C6_TX_DMA_CONFIG
#define I2C6_TX_DMA_CONFIG \
{ \
.Instance = I2C6_TX_DMA_INSTANCE, \
.dma_irq = I2C6_TX_DMA_IRQ, \
.HsInterface = I2C6_TX_DMA_HANDSHAK, \
.dma_rcc = I2C6_TX_DMA_DMA_RCC, \
.dma_channel = I2C6_TX_DMA_DMA_CHANNEL, \
.dmamux_channel = I2C6_TX_DMA_DMAMUX_CHANNEL, \
.dmamux_request = I2C6_TX_DMA_DMAMUX_REQUEST, \
#define I2C6_TX_DMA_CONFIG \
{ \
.Instance = I2C6_TX_DMA_INSTANCE, \
.dma_irq = I2C6_TX_DMA_IRQ, \
.HsInterface = I2C6_TX_DMA_HANDSHAK, \
.dma_rcc = I2C6_TX_DMA_DMA_RCC, \
.dma_channel = I2C6_TX_DMA_DMA_CHANNEL, \
.dmamux_channel = I2C6_TX_DMA_DMAMUX_CHANNEL, \
.dmamux_request = I2C6_TX_DMA_DMAMUX_REQUEST, \
}
#endif /* I2C6_TX_DMA_CONFIG */
#endif /* BSP_I2C6_TX_USING_DMA */
@ -331,34 +326,33 @@ extern "C" {
#endif /* BSP_USING_HARD_I2C7 */
#ifdef BSP_I2C7_RX_USING_DMA
#ifndef I2C7_RX_DMA_CONFIG
#define I2C7_RX_DMA_CONFIG \
{ \
.Instance = I2C7_RX_DMA_INSTANCE, \
.dma_irq = I2C7_RX_DMA_IRQ, \
.HsInterface = I2C7_RX_DMA_HANDSHAK, \
.dma_rcc = I2C7_RX_DMA_DMA_RCC, \
.dma_channel = I2C7_RX_DMA_DMA_CHANNEL, \
.dmamux_channel = I2C7_RX_DMA_DMAMUX_CHANNEL, \
.dmamux_request = I2C7_RX_DMA_DMAMUX_REQUEST, \
#define I2C7_RX_DMA_CONFIG \
{ \
.Instance = I2C7_RX_DMA_INSTANCE, \
.dma_irq = I2C7_RX_DMA_IRQ, \
.HsInterface = I2C7_RX_DMA_HANDSHAK, \
.dma_rcc = I2C7_RX_DMA_DMA_RCC, \
.dma_channel = I2C7_RX_DMA_DMA_CHANNEL, \
.dmamux_channel = I2C7_RX_DMA_DMAMUX_CHANNEL, \
.dmamux_request = I2C7_RX_DMA_DMAMUX_REQUEST, \
}
#endif /* I2C7_RX_DMA_CONFIG */
#endif /* BSP_I2C7_RX_USING_DMA */
#ifdef BSP_I2C7_TX_USING_DMA
#ifndef I2C7_TX_DMA_CONFIG
#define I2C7_TX_DMA_CONFIG \
{ \
.Instance = I2C7_TX_DMA_INSTANCE, \
.dma_irq = I2C7_TX_DMA_IRQ, \
.HsInterface = I2C7_TX_DMA_HANDSHAK, \
.dma_rcc = I2C7_TX_DMA_DMA_RCC, \
.dma_channel = I2C7_TX_DMA_DMA_CHANNEL, \
.dmamux_channel = I2C7_TX_DMA_DMAMUX_CHANNEL, \
.dmamux_request = I2C7_TX_DMA_DMAMUX_REQUEST, \
#define I2C7_TX_DMA_CONFIG \
{ \
.Instance = I2C7_TX_DMA_INSTANCE, \
.dma_irq = I2C7_TX_DMA_IRQ, \
.HsInterface = I2C7_TX_DMA_HANDSHAK, \
.dma_rcc = I2C7_TX_DMA_DMA_RCC, \
.dma_channel = I2C7_TX_DMA_DMA_CHANNEL, \
.dmamux_channel = I2C7_TX_DMA_DMAMUX_CHANNEL, \
.dmamux_request = I2C7_TX_DMA_DMAMUX_REQUEST, \
}
#endif /* I2C7_TX_DMA_CONFIG */
#endif /* BSP_I2C7_TX_USING_DMA */
#ifdef BSP_USING_HARD_I2C8
#ifndef I2C8_BUS_CONFIG
#define I2C8_BUS_CONFIG \
@ -380,34 +374,33 @@ extern "C" {
#endif /* BSP_USING_HARD_I2C8 */
#ifdef BSP_I2C8_RX_USING_DMA
#ifndef I2C8_RX_DMA_CONFIG
#define I2C8_RX_DMA_CONFIG \
{ \
.Instance = I2C8_RX_DMA_INSTANCE, \
.dma_irq = I2C8_RX_DMA_IRQ, \
.HsInterface = I2C8_RX_DMA_HANDSHAK, \
.dma_rcc = I2C8_RX_DMA_DMA_RCC, \
.dma_channel = I2C8_RX_DMA_DMA_CHANNEL, \
.dmamux_channel = I2C8_RX_DMA_DMAMUX_CHANNEL, \
.dmamux_request = I2C8_RX_DMA_DMAMUX_REQUEST, \
#define I2C8_RX_DMA_CONFIG \
{ \
.Instance = I2C8_RX_DMA_INSTANCE, \
.dma_irq = I2C8_RX_DMA_IRQ, \
.HsInterface = I2C8_RX_DMA_HANDSHAK, \
.dma_rcc = I2C8_RX_DMA_DMA_RCC, \
.dma_channel = I2C8_RX_DMA_DMA_CHANNEL, \
.dmamux_channel = I2C8_RX_DMA_DMAMUX_CHANNEL, \
.dmamux_request = I2C8_RX_DMA_DMAMUX_REQUEST, \
}
#endif /* I2C8_RX_DMA_CONFIG */
#endif /* BSP_I2C8_RX_USING_DMA */
#ifdef BSP_I2C8_TX_USING_DMA
#ifndef I2C8_TX_DMA_CONFIG
#define I2C8_TX_DMA_CONFIG \
{ \
.Instance = I2C8_TX_DMA_INSTANCE, \
.dma_irq = I2C8_TX_DMA_IRQ, \
.HsInterface = I2C8_TX_DMA_HANDSHAK, \
.dma_rcc = I2C8_TX_DMA_DMA_RCC, \
.dma_channel = I2C8_TX_DMA_DMA_CHANNEL, \
.dmamux_channel = I2C8_TX_DMA_DMAMUX_CHANNEL, \
.dmamux_request = I2C8_TX_DMA_DMAMUX_REQUEST, \
#define I2C8_TX_DMA_CONFIG \
{ \
.Instance = I2C8_TX_DMA_INSTANCE, \
.dma_irq = I2C8_TX_DMA_IRQ, \
.HsInterface = I2C8_TX_DMA_HANDSHAK, \
.dma_rcc = I2C8_TX_DMA_DMA_RCC, \
.dma_channel = I2C8_TX_DMA_DMA_CHANNEL, \
.dmamux_channel = I2C8_TX_DMA_DMAMUX_CHANNEL, \
.dmamux_request = I2C8_TX_DMA_DMAMUX_REQUEST, \
}
#endif /* I2C8_TX_DMA_CONFIG */
#endif /* BSP_I2C8_TX_USING_DMA */
#ifdef BSP_USING_HARD_I2C9
#ifndef I2C9_BUS_CONFIG
#define I2C9_BUS_CONFIG \
@ -429,34 +422,33 @@ extern "C" {
#endif /* BSP_USING_HARD_I2C9 */
#ifdef BSP_I2C9_RX_USING_DMA
#ifndef I2C9_RX_DMA_CONFIG
#define I2C9_RX_DMA_CONFIG \
{ \
.Instance = I2C9_RX_DMA_INSTANCE, \
.dma_irq = I2C9_RX_DMA_IRQ, \
.HsInterface = I2C9_RX_DMA_HANDSHAK, \
.dma_rcc = I2C9_RX_DMA_DMA_RCC, \
.dma_channel = I2C9_RX_DMA_DMA_CHANNEL, \
.dmamux_channel = I2C9_RX_DMA_DMAMUX_CHANNEL, \
.dmamux_request = I2C9_RX_DMA_DMAMUX_REQUEST, \
#define I2C9_RX_DMA_CONFIG \
{ \
.Instance = I2C9_RX_DMA_INSTANCE, \
.dma_irq = I2C9_RX_DMA_IRQ, \
.HsInterface = I2C9_RX_DMA_HANDSHAK, \
.dma_rcc = I2C9_RX_DMA_DMA_RCC, \
.dma_channel = I2C9_RX_DMA_DMA_CHANNEL, \
.dmamux_channel = I2C9_RX_DMA_DMAMUX_CHANNEL, \
.dmamux_request = I2C9_RX_DMA_DMAMUX_REQUEST, \
}
#endif /* I2C9_RX_DMA_CONFIG */
#endif /* BSP_I2C9_RX_USING_DMA */
#ifdef BSP_I2C9_TX_USING_DMA
#ifndef I2C9_TX_DMA_CONFIG
#define I2C9_TX_DMA_CONFIG \
{ \
.Instance = I2C9_TX_DMA_INSTANCE, \
.dma_irq = I2C9_TX_DMA_IRQ, \
.HsInterface = I2C9_TX_DMA_HANDSHAK, \
.dma_rcc = I2C9_TX_DMA_DMA_RCC, \
.dma_channel = I2C9_TX_DMA_DMA_CHANNEL, \
.dmamux_channel = I2C9_TX_DMA_DMAMUX_CHANNEL, \
.dmamux_request = I2C9_TX_DMA_DMAMUX_REQUEST, \
#define I2C9_TX_DMA_CONFIG \
{ \
.Instance = I2C9_TX_DMA_INSTANCE, \
.dma_irq = I2C9_TX_DMA_IRQ, \
.HsInterface = I2C9_TX_DMA_HANDSHAK, \
.dma_rcc = I2C9_TX_DMA_DMA_RCC, \
.dma_channel = I2C9_TX_DMA_DMA_CHANNEL, \
.dmamux_channel = I2C9_TX_DMA_DMAMUX_CHANNEL, \
.dmamux_request = I2C9_TX_DMA_DMAMUX_REQUEST, \
}
#endif /* I2C9_TX_DMA_CONFIG */
#endif /* BSP_I2C9_TX_USING_DMA */
#ifdef BSP_USING_HARD_I2C10
#ifndef I2C10_BUS_CONFIG
#define I2C10_BUS_CONFIG \
@ -478,29 +470,29 @@ extern "C" {
#endif /* BSP_USING_HARD_I2C10 */
#ifdef BSP_I2C10_RX_USING_DMA
#ifndef I2C10_RX_DMA_CONFIG
#define I2C10_RX_DMA_CONFIG \
{ \
.Instance = I2C10_RX_DMA_INSTANCE, \
.dma_irq = I2C10_RX_DMA_IRQ, \
.HsInterface = I2C10_RX_DMA_HANDSHAK, \
.dma_rcc = I2C10_RX_DMA_DMA_RCC, \
.dma_channel = I2C10_RX_DMA_DMA_CHANNEL, \
.dmamux_channel = I2C10_RX_DMA_DMAMUX_CHANNEL, \
.dmamux_request = I2C10_RX_DMA_DMAMUX_REQUEST, \
#define I2C10_RX_DMA_CONFIG \
{ \
.Instance = I2C10_RX_DMA_INSTANCE, \
.dma_irq = I2C10_RX_DMA_IRQ, \
.HsInterface = I2C10_RX_DMA_HANDSHAK, \
.dma_rcc = I2C10_RX_DMA_DMA_RCC, \
.dma_channel = I2C10_RX_DMA_DMA_CHANNEL, \
.dmamux_channel = I2C10_RX_DMA_DMAMUX_CHANNEL, \
.dmamux_request = I2C10_RX_DMA_DMAMUX_REQUEST, \
}
#endif /* I2C10_RX_DMA_CONFIG */
#endif /* BSP_I2C10_RX_USING_DMA */
#ifdef BSP_I2C10_TX_USING_DMA
#ifndef I2C10_TX_DMA_CONFIG
#define I2C10_TX_DMA_CONFIG \
#define I2C10_TX_DMA_CONFIG \
{ \
.Instance = I2C10_TX_DMA_INSTANCE, \
.dma_irq = I2C10_TX_DMA_IRQ, \
.HsInterface = I2C10_TX_DMA_HANDSHAK, \
.dma_rcc = I2C10_TX_DMA_DMA_RCC, \
.dma_channel = I2C10_TX_DMA_DMA_CHANNEL, \
.dmamux_channel = I2C10_TX_DMA_DMAMUX_CHANNEL, \
.dmamux_request = I2C10_TX_DMA_DMAMUX_REQUEST, \
.Instance = I2C10_TX_DMA_INSTANCE, \
.dma_irq = I2C10_TX_DMA_IRQ, \
.HsInterface = I2C10_TX_DMA_HANDSHAK, \
.dma_rcc = I2C10_TX_DMA_DMA_RCC, \
.dma_channel = I2C10_TX_DMA_DMA_CHANNEL, \
.dmamux_channel = I2C10_TX_DMA_DMAMUX_CHANNEL, \
.dmamux_request = I2C10_TX_DMA_DMAMUX_REQUEST, \
}
#endif /* I2C10_TX_DMA_CONFIG */
#endif /* BSP_I2C10_TX_USING_DMA */

89
bsp/n32/n32hxxx/libraries/N32_Drivers/drivers/config/h7xx/lptim_config.h Normal file
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@ -0,0 +1,89 @@
/*
* Copyright (c) 2006-2025, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2026-06-23 ox-horse first version
*/
#ifndef __LPTIM_CONFIG_H__
#define __LPTIM_CONFIG_H__
#include <rtthread.h>
#ifdef __cplusplus
extern "C" {
#endif
#ifndef LPTIM_DEV_INFO_CONFIG
#define LPTIM_DEV_INFO_CONFIG \
{ \
.maxfreq = 1000000, \
.minfreq = 3000, \
.maxcnt = 0xFFFF, \
.cntmode = CLOCK_TIMER_CNTMODE_UP, \
}
#endif /* LPTIM_DEV_INFO_CONFIG */
#ifdef BSP_USING_LPTIM1
#ifndef LPTIM1_CONFIG
#define LPTIM1_CONFIG \
{ \
.timer = LPTIM1, \
.tim_irqn = LPTIM1_WKUP_IRQn, \
.name = "lptim1", \
}
#endif /* LPTIM1_CONFIG */
#endif /* BSP_USING_LPTIM1 */
#ifdef BSP_USING_LPTIM2
#ifndef LPTIM2_CONFIG
#define LPTIM2_CONFIG \
{ \
.timer = LPTIM2, \
.tim_irqn = LPTIM2_WKUP_IRQn, \
.name = "lptim2", \
}
#endif /* LPTIM2_CONFIG */
#endif /* BSP_USING_LPTIM2 */
#ifdef BSP_USING_LPTIM3
#ifndef LPTIM3_CONFIG
#define LPTIM3_CONFIG \
{ \
.timer = LPTIM3, \
.tim_irqn = LPTIM3_WKUP_IRQn, \
.name = "lptim3", \
}
#endif /* LPTIM3_CONFIG */
#endif /* BSP_USING_LPTIM3 */
#ifdef BSP_USING_LPTIM4
#ifndef LPTIM4_CONFIG
#define LPTIM4_CONFIG \
{ \
.timer = LPTIM4, \
.tim_irqn = LPTIM4_WKUP_IRQn, \
.name = "lptim4", \
}
#endif /* LPTIM4_CONFIG */
#endif /* BSP_USING_LPTIM4 */
#ifdef BSP_USING_LPTIM5
#ifndef LPTIM5_CONFIG
#define LPTIM5_CONFIG \
{ \
.timer = LPTIM5, \
.tim_irqn = LPTIM5_WKUP_IRQn, \
.name = "lptim5", \
}
#endif /* LPTIM5_CONFIG */
#endif /* BSP_USING_LPTIM5 */
#ifdef __cplusplus
}
#endif
#endif /* __LPTIM_CONFIG_H__ */

178
bsp/n32/n32hxxx/libraries/N32_Drivers/drivers/config/h7xx/pulse_encoder_config.h Normal file
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@ -0,0 +1,178 @@
/*
* Copyright (c) 2006-2025, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2026-07-06 ox-horse first version
*/
#ifndef __PULSE_ENCODER_CONFIG_H__
#define __PULSE_ENCODER_CONFIG_H__
#include <rtthread.h>
#ifdef __cplusplus
extern "C" {
#endif
#ifdef BSP_USING_PULSE_ENCODER1
#ifndef PULSE_ENCODER1_CONFIG
#define PULSE_ENCODER1_CONFIG \
{ \
.timer = ATIM1, \
.tim_irqn = ATIM1_UP_IRQn, \
.name = "pulse1", \
}
#endif /* PULSE_ENCODER1_CONFIG */
#endif /* BSP_USING_PULSE_ENCODER1 */
#ifdef BSP_USING_PULSE_ENCODER2
#ifndef PULSE_ENCODER2_CONFIG
#define PULSE_ENCODER2_CONFIG \
{ \
.timer = ATIM2, \
.tim_irqn = ATIM2_UP_IRQn, \
.name = "pulse2", \
}
#endif /* PULSE_ENCODER2_CONFIG */
#endif /* BSP_USING_PULSE_ENCODER2 */
#ifdef BSP_USING_PULSE_ENCODER3
#ifndef PULSE_ENCODER3_CONFIG
#define PULSE_ENCODER3_CONFIG \
{ \
.timer = ATIM3, \
.tim_irqn = ATIM3_UP_IRQn, \
.name = "pulse3", \
}
#endif /* PULSE_ENCODER3_CONFIG */
#endif /* BSP_USING_PULSE_ENCODER3 */
#ifdef BSP_USING_PULSE_ENCODER4
#ifndef PULSE_ENCODER4_CONFIG
#define PULSE_ENCODER4_CONFIG \
{ \
.timer = ATIM4, \
.tim_irqn = ATIM4_UP_IRQn, \
.name = "pulse4", \
}
#endif /* PULSE_ENCODER4_CONFIG */
#endif /* BSP_USING_PULSE_ENCODER4 */
#ifdef BSP_USING_PULSE_ENCODER5
#ifndef PULSE_ENCODER5_CONFIG
#define PULSE_ENCODER5_CONFIG \
{ \
.timer = GTIMA1, \
.tim_irqn = GTIMA1_IRQn, \
.name = "pulse5", \
}
#endif /* PULSE_ENCODER5_CONFIG */
#endif /* BSP_USING_PULSE_ENCODER5 */
#ifdef BSP_USING_PULSE_ENCODER6
#ifndef PULSE_ENCODER6_CONFIG
#define PULSE_ENCODER6_CONFIG \
{ \
.timer = GTIMA2, \
.tim_irqn = GTIMA2_IRQn, \
.name = "pulse6", \
}
#endif /* PULSE_ENCODER6_CONFIG */
#endif /* BSP_USING_PULSE_ENCODER6 */
#ifdef BSP_USING_PULSE_ENCODER7
#ifndef PULSE_ENCODER7_CONFIG
#define PULSE_ENCODER7_CONFIG \
{ \
.timer = GTIMA3, \
.tim_irqn = GTIMA3_IRQn, \
.name = "pulse7", \
}
#endif /* PULSE_ENCODER7_CONFIG */
#endif /* BSP_USING_PULSE_ENCODER7 */
#ifdef BSP_USING_PULSE_ENCODER8
#ifndef PULSE_ENCODER8_CONFIG
#define PULSE_ENCODER8_CONFIG \
{ \
.timer = GTIMA4, \
.tim_irqn = GTIMA4_IRQn, \
.name = "pulse8", \
}
#endif /* PULSE_ENCODER8_CONFIG */
#endif /* BSP_USING_PULSE_ENCODER8 */
#ifdef BSP_USING_PULSE_ENCODER9
#ifndef PULSE_ENCODER9_CONFIG
#define PULSE_ENCODER9_CONFIG \
{ \
.timer = GTIMA5, \
.tim_irqn = GTIMA5_IRQn, \
.name = "pulse9", \
}
#endif /* PULSE_ENCODER9_CONFIG */
#endif /* BSP_USING_PULSE_ENCODER9 */
#ifdef BSP_USING_PULSE_ENCODER10
#ifndef PULSE_ENCODER10_CONFIG
#define PULSE_ENCODER10_CONFIG \
{ \
.timer = GTIMA6, \
.tim_irqn = GTIMA6_IRQn, \
.name = "pulse10", \
}
#endif /* PULSE_ENCODER10_CONFIG */
#endif /* BSP_USING_PULSE_ENCODER10 */
#ifdef BSP_USING_PULSE_ENCODER11
#ifndef PULSE_ENCODER11_CONFIG
#define PULSE_ENCODER11_CONFIG \
{ \
.timer = GTIMA7, \
.tim_irqn = GTIMA7_IRQn, \
.name = "pulse11", \
}
#endif /* PULSE_ENCODER11_CONFIG */
#endif /* BSP_USING_PULSE_ENCODER11 */
#ifdef BSP_USING_PULSE_ENCODER12
#ifndef PULSE_ENCODER12_CONFIG
#define PULSE_ENCODER12_CONFIG \
{ \
.timer = GTIMB1, \
.tim_irqn = GTIMB1_IRQn, \
.name = "pulse12", \
}
#endif /* PULSE_ENCODER12_CONFIG */
#endif /* BSP_USING_PULSE_ENCODER12 */
#ifdef BSP_USING_PULSE_ENCODER13
#ifndef PULSE_ENCODER13_CONFIG
#define PULSE_ENCODER13_CONFIG \
{ \
.timer = GTIMB2, \
.tim_irqn = GTIMB2_IRQn, \
.name = "pulse13", \
}
#endif /* PULSE_ENCODER13_CONFIG */
#endif /* BSP_USING_PULSE_ENCODER13 */
#ifdef BSP_USING_PULSE_ENCODER14
#ifndef PULSE_ENCODER14_CONFIG
#define PULSE_ENCODER14_CONFIG \
{ \
.timer = GTIMB3, \
.tim_irqn = GTIMB3_IRQn, \
.name = "pulse14", \
}
#endif /* PULSE_ENCODER14_CONFIG */
#endif /* BSP_USING_PULSE_ENCODER14 */
#ifdef __cplusplus
}
#endif
#endif /* __PULSE_ENCODER_CONFIG_H__ */

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/*
* Copyright (c) 2006-2025, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2026-06-23 ox-horse first version
*/
#ifndef __PWM_CONFIG_H__
#define __PWM_CONFIG_H__
#include <rtthread.h>
#ifdef __cplusplus
extern "C" {
#endif
#ifdef BSP_USING_PWM1
#ifndef PWM1_CONFIG
#define PWM1_CONFIG \
{ \
.timer = ATIM1, \
.name = "pwm1", \
.channel = 0 \
}
#endif /* PWM1_CONFIG */
#endif /* BSP_USING_PWM1 */
#ifdef BSP_USING_PWM2
#ifndef PWM2_CONFIG
#define PWM2_CONFIG \
{ \
.timer = ATIM2, \
.name = "pwm2", \
.channel = 0 \
}
#endif /* PWM2_CONFIG */
#endif /* BSP_USING_PWM2 */
#ifdef BSP_USING_PWM3
#ifndef PWM3_CONFIG
#define PWM3_CONFIG \
{ \
.timer = ATIM3, \
.name = "pwm3", \
.channel = 0 \
}
#endif /* PWM3_CONFIG */
#endif /* BSP_USING_PWM3 */
#ifdef BSP_USING_PWM4
#ifndef PWM4_CONFIG
#define PWM4_CONFIG \
{ \
.timer = ATIM4, \
.name = "pwm4", \
.channel = 0 \
}
#endif /* PWM4_CONFIG */
#endif /* BSP_USING_PWM4 */
#ifdef BSP_USING_PWM5
#ifndef PWM5_CONFIG
#define PWM5_CONFIG \
{ \
.timer = GTIMA1, \
.name = "pwm5", \
.channel = 0 \
}
#endif /* PWM5_CONFIG */
#endif /* BSP_USING_PWM5 */
#ifdef BSP_USING_PWM6
#ifndef PWM6_CONFIG
#define PWM6_CONFIG \
{ \
.timer = GTIMA2, \
.name = "pwm6", \
.channel = 0 \
}
#endif /* PWM6_CONFIG */
#endif /* BSP_USING_PWM6 */
#ifdef BSP_USING_PWM7
#ifndef PWM7_CONFIG
#define PWM7_CONFIG \
{ \
.timer = GTIMA3, \
.name = "pwm7", \
.channel = 0 \
}
#endif /* PWM7_CONFIG */
#endif /* BSP_USING_PWM7 */
#ifdef BSP_USING_PWM8
#ifndef PWM8_CONFIG
#define PWM8_CONFIG \
{ \
.timer = GTIMA4, \
.name = "pwm8", \
.channel = 0 \
}
#endif /* PWM8_CONFIG */
#endif /* BSP_USING_PWM8 */
#ifdef BSP_USING_PWM9
#ifndef PWM9_CONFIG
#define PWM9_CONFIG \
{ \
.timer = GTIMA5, \
.name = "pwm9", \
.channel = 0 \
}
#endif /* PWM9_CONFIG */
#endif /* BSP_USING_PWM9 */
#ifdef BSP_USING_PWM10
#ifndef PWM10_CONFIG
#define PWM10_CONFIG \
{ \
.timer = GTIMA6, \
.name = "pwm10", \
.channel = 0 \
}
#endif /* PWM10_CONFIG */
#endif /* BSP_USING_PWM10 */
#ifdef BSP_USING_PWM11
#ifndef PWM11_CONFIG
#define PWM11_CONFIG \
{ \
.timer = GTIMA7, \
.name = "pwm11", \
.channel = 0 \
}
#endif /* PWM11_CONFIG */
#endif /* BSP_USING_PWM11 */
#ifdef BSP_USING_PWM12
#ifndef PWM12_CONFIG
#define PWM12_CONFIG \
{ \
.timer = GTIMB1, \
.name = "pwm12", \
.channel = 0 \
}
#endif /* PWM12_CONFIG */
#endif /* BSP_USING_PWM12 */
#ifdef BSP_USING_PWM13
#ifndef PWM13_CONFIG
#define PWM13_CONFIG \
{ \
.timer = GTIMB2, \
.name = "pwm13", \
.channel = 0 \
}
#endif /* PWM13_CONFIG */
#endif /* BSP_USING_PWM13 */
#ifdef BSP_USING_PWM14
#ifndef PWM14_CONFIG
#define PWM14_CONFIG \
{ \
.timer = GTIMB3, \
.name = "pwm14", \
.channel = 0 \
}
#endif /* PWM14_CONFIG */
#endif /* BSP_USING_PWM14 */
#ifdef __cplusplus
}
#endif
#endif /* __PWM_CONFIG_H__ */

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/*
* Copyright (c) 2006-2025, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2026-01-24 ox-horse first version
*/
#ifndef __SPI_CONFIG_H__
#define __SPI_CONFIG_H__
#include <rtthread.h>
#ifdef __cplusplus
extern "C" {
#endif
#ifdef BSP_USING_SPI1
#ifndef SPI1_BUS_CONFIG
#define SPI1_BUS_CONFIG \
{ \
.SPIx = SPI1, \
.bus_name = "spi1", \
.irq_type = SPI1_IRQn, \
}
#endif /* SPI1_BUS_CONFIG */
#endif /* BSP_USING_SPI1 */
#ifdef BSP_SPI1_TX_USING_DMA
#ifndef SPI1_TX_DMA_CONFIG
#define SPI1_TX_DMA_CONFIG \
{ \
.Instance = SPI1_TX_DMA_INSTANCE, \
.dma_irq = SPI1_TX_DMA_IRQ, \
.HsInterface = SPI1_TX_DMA_HANDSHAK, \
.dma_rcc = SPI1_TX_DMA_DMA_RCC, \
.dma_channel = SPI1_TX_DMA_DMA_CHANNEL, \
.dmamux_channel = SPI1_TX_DMA_DMAMUX_CHANNEL, \
.dmamux_request = SPI1_TX_DMA_DMAMUX_REQUEST, \
}
#endif /* SPI1_TX_DMA_CONFIG */
#endif /* BSP_SPI1_TX_USING_DMA */
#ifdef BSP_SPI1_RX_USING_DMA
#ifndef SPI1_RX_DMA_CONFIG
#define SPI1_RX_DMA_CONFIG \
{ \
.Instance = SPI1_RX_DMA_INSTANCE, \
.dma_irq = SPI1_RX_DMA_IRQ, \
.HsInterface = SPI1_RX_DMA_HANDSHAK, \
.dma_rcc = SPI1_RX_DMA_DMA_RCC, \
.dma_channel = SPI1_RX_DMA_DMA_CHANNEL, \
.dmamux_channel = SPI1_RX_DMA_DMAMUX_CHANNEL, \
.dmamux_request = SPI1_RX_DMA_DMAMUX_REQUEST, \
}
#endif /* SPI1_RX_DMA_CONFIG */
#endif /* BSP_SPI1_RX_USING_DMA */
#ifdef BSP_USING_SPI2
#ifndef SPI2_BUS_CONFIG
#define SPI2_BUS_CONFIG \
{ \
.SPIx = SPI2, \
.bus_name = "spi2", \
.irq_type = SPI2_IRQn, \
}
#endif /* SPI2_BUS_CONFIG */
#endif /* BSP_USING_SPI2 */
#ifdef BSP_SPI2_TX_USING_DMA
#ifndef SPI2_TX_DMA_CONFIG
#define SPI2_TX_DMA_CONFIG \
{ \
.Instance = SPI2_TX_DMA_INSTANCE, \
.dma_irq = SPI2_TX_DMA_IRQ, \
.HsInterface = SPI2_TX_DMA_HANDSHAK, \
.dma_rcc = SPI2_TX_DMA_DMA_RCC, \
.dma_channel = SPI2_TX_DMA_DMA_CHANNEL, \
.dmamux_channel = SPI2_TX_DMA_DMAMUX_CHANNEL, \
.dmamux_request = SPI2_TX_DMA_DMAMUX_REQUEST, \
}
#endif /* SPI2_TX_DMA_CONFIG */
#endif /* BSP_SPI2_TX_USING_DMA */
#ifdef BSP_SPI2_RX_USING_DMA
#ifndef SPI2_RX_DMA_CONFIG
#define SPI2_RX_DMA_CONFIG \
{ \
.Instance = SPI2_RX_DMA_INSTANCE, \
.dma_irq = SPI2_RX_DMA_IRQ, \
.HsInterface = SPI2_RX_DMA_HANDSHAK, \
.dma_rcc = SPI2_RX_DMA_DMA_RCC, \
.dma_channel = SPI2_RX_DMA_DMA_CHANNEL, \
.dmamux_channel = SPI2_RX_DMA_DMAMUX_CHANNEL, \
.dmamux_request = SPI2_RX_DMA_DMAMUX_REQUEST, \
}
#endif /* SPI2_RX_DMA_CONFIG */
#endif /* BSP_SPI2_RX_USING_DMA */
#ifdef BSP_USING_SPI3
#ifndef SPI3_BUS_CONFIG
#define SPI3_BUS_CONFIG \
{ \
.SPIx = SPI3, \
.bus_name = "spi3", \
.irq_type = SPI3_IRQn, \
}
#endif /* SPI3_BUS_CONFIG */
#endif /* BSP_USING_SPI3 */
#ifdef BSP_SPI3_TX_USING_DMA
#ifndef SPI3_TX_DMA_CONFIG
#define SPI3_TX_DMA_CONFIG \
{ \
.Instance = SPI3_TX_DMA_INSTANCE, \
.dma_irq = SPI3_TX_DMA_IRQ, \
.HsInterface = SPI3_TX_DMA_HANDSHAK, \
.dma_rcc = SPI3_TX_DMA_DMA_RCC, \
.dma_channel = SPI3_TX_DMA_DMA_CHANNEL, \
.dmamux_channel = SPI3_TX_DMA_DMAMUX_CHANNEL, \
.dmamux_request = SPI3_TX_DMA_DMAMUX_REQUEST, \
}
#endif /* SPI3_TX_DMA_CONFIG */
#endif /* BSP_SPI3_TX_USING_DMA */
#ifdef BSP_SPI3_RX_USING_DMA
#ifndef SPI3_RX_DMA_CONFIG
#define SPI3_RX_DMA_CONFIG \
{ \
.Instance = SPI3_RX_DMA_INSTANCE, \
.dma_irq = SPI3_RX_DMA_IRQ, \
.HsInterface = SPI3_RX_DMA_HANDSHAK, \
.dma_rcc = SPI3_RX_DMA_DMA_RCC, \
.dma_channel = SPI3_RX_DMA_DMA_CHANNEL, \
.dmamux_channel = SPI3_RX_DMA_DMAMUX_CHANNEL, \
.dmamux_request = SPI3_RX_DMA_DMAMUX_REQUEST, \
}
#endif /* SPI3_RX_DMA_CONFIG */
#endif /* BSP_SPI3_RX_USING_DMA */
#ifdef BSP_USING_SPI4
#ifndef SPI4_BUS_CONFIG
#define SPI4_BUS_CONFIG \
{ \
.SPIx = SPI4, \
.bus_name = "spi4", \
.irq_type = SPI4_IRQn, \
}
#endif /* SPI4_BUS_CONFIG */
#endif /* BSP_USING_SPI4 */
#ifdef BSP_SPI4_TX_USING_DMA
#ifndef SPI4_TX_DMA_CONFIG
#define SPI4_TX_DMA_CONFIG \
{ \
.Instance = SPI4_TX_DMA_INSTANCE, \
.dma_irq = SPI4_TX_DMA_IRQ, \
.HsInterface = SPI4_TX_DMA_HANDSHAK, \
.dma_rcc = SPI4_TX_DMA_DMA_RCC, \
.dma_channel = SPI4_TX_DMA_DMA_CHANNEL, \
.dmamux_channel = SPI4_TX_DMA_DMAMUX_CHANNEL, \
.dmamux_request = SPI4_TX_DMA_DMAMUX_REQUEST, \
}
#endif /* SPI4_TX_DMA_CONFIG */
#endif /* BSP_SPI4_TX_USING_DMA */
#ifdef BSP_SPI4_RX_USING_DMA
#ifndef SPI4_RX_DMA_CONFIG
#define SPI4_RX_DMA_CONFIG \
{ \
.Instance = SPI4_RX_DMA_INSTANCE, \
.dma_irq = SPI4_RX_DMA_IRQ, \
.HsInterface = SPI4_RX_DMA_HANDSHAK, \
.dma_rcc = SPI4_RX_DMA_DMA_RCC, \
.dma_channel = SPI4_RX_DMA_DMA_CHANNEL, \
.dmamux_channel = SPI4_RX_DMA_DMAMUX_CHANNEL, \
.dmamux_request = SPI4_RX_DMA_DMAMUX_REQUEST, \
}
#endif /* SPI4_RX_DMA_CONFIG */
#endif /* BSP_SPI4_RX_USING_DMA */
#ifdef BSP_USING_SPI5
#ifndef SPI5_BUS_CONFIG
#define SPI5_BUS_CONFIG \
{ \
.SPIx = SPI5, \
.bus_name = "spi5", \
.irq_type = SPI5_IRQn, \
}
#endif /* SPI5_BUS_CONFIG */
#endif /* BSP_USING_SPI5 */
#ifdef BSP_SPI5_TX_USING_DMA
#ifndef SPI5_TX_DMA_CONFIG
#define SPI5_TX_DMA_CONFIG \
{ \
.Instance = SPI5_TX_DMA_INSTANCE, \
.dma_irq = SPI5_TX_DMA_IRQ, \
.HsInterface = SPI5_TX_DMA_HANDSHAK, \
.dma_rcc = SPI5_TX_DMA_DMA_RCC, \
.dma_channel = SPI5_TX_DMA_DMA_CHANNEL, \
.dmamux_channel = SPI5_TX_DMA_DMAMUX_CHANNEL, \
.dmamux_request = SPI5_TX_DMA_DMAMUX_REQUEST, \
}
#endif /* SPI5_TX_DMA_CONFIG */
#endif /* BSP_SPI5_TX_USING_DMA */
#ifdef BSP_SPI5_RX_USING_DMA
#ifndef SPI5_RX_DMA_CONFIG
#define SPI5_RX_DMA_CONFIG \
{ \
.Instance = SPI5_RX_DMA_INSTANCE, \
.dma_irq = SPI5_RX_DMA_IRQ, \
.HsInterface = SPI5_RX_DMA_HANDSHAK, \
.dma_rcc = SPI5_RX_DMA_DMA_RCC, \
.dma_channel = SPI5_RX_DMA_DMA_CHANNEL, \
.dmamux_channel = SPI5_RX_DMA_DMAMUX_CHANNEL, \
.dmamux_request = SPI5_RX_DMA_DMAMUX_REQUEST, \
}
#endif /* SPI5_RX_DMA_CONFIG */
#endif /* BSP_SPI5_RX_USING_DMA */
#ifdef BSP_USING_SPI6
#ifndef SPI6_BUS_CONFIG
#define SPI6_BUS_CONFIG \
{ \
.SPIx = SPI6, \
.bus_name = "spi6", \
.irq_type = SPI6_IRQn, \
}
#endif /* SPI6_BUS_CONFIG */
#endif /* BSP_USING_SPI6 */
#ifdef BSP_SPI6_TX_USING_DMA
#ifndef SPI6_TX_DMA_CONFIG
#define SPI6_TX_DMA_CONFIG \
{ \
.Instance = SPI6_TX_DMA_INSTANCE, \
.dma_irq = SPI6_TX_DMA_IRQ, \
.HsInterface = SPI6_TX_DMA_HANDSHAK, \
.dma_rcc = SPI6_TX_DMA_DMA_RCC, \
.dma_channel = SPI6_TX_DMA_DMA_CHANNEL, \
.dmamux_channel = SPI6_TX_DMA_DMAMUX_CHANNEL, \
.dmamux_request = SPI6_TX_DMA_DMAMUX_REQUEST, \
}
#endif /* SPI6_TX_DMA_CONFIG */
#endif /* BSP_SPI6_TX_USING_DMA */
#ifdef BSP_SPI6_RX_USING_DMA
#ifndef SPI6_RX_DMA_CONFIG
#define SPI6_RX_DMA_CONFIG \
{ \
.Instance = SPI6_RX_DMA_INSTANCE, \
.dma_irq = SPI6_RX_DMA_IRQ, \
.HsInterface = SPI6_RX_DMA_HANDSHAK, \
.dma_rcc = SPI6_RX_DMA_DMA_RCC, \
.dma_channel = SPI6_RX_DMA_DMA_CHANNEL, \
.dmamux_channel = SPI6_RX_DMA_DMAMUX_CHANNEL, \
.dmamux_request = SPI6_RX_DMA_DMAMUX_REQUEST, \
}
#endif /* SPI6_RX_DMA_CONFIG */
#endif /* BSP_SPI6_RX_USING_DMA */
#ifdef BSP_USING_SPI7
#ifndef SPI7_BUS_CONFIG
#define SPI7_BUS_CONFIG \
{ \
.SPIx = SPI7, \
.bus_name = "spi7", \
.irq_type = SPI7_IRQn, \
}
#endif /* SPI7_BUS_CONFIG */
#endif /* BSP_USING_SPI7 */
#ifdef BSP_SPI7_TX_USING_DMA
#ifndef SPI7_TX_DMA_CONFIG
#define SPI7_TX_DMA_CONFIG \
{ \
.Instance = SPI7_TX_DMA_INSTANCE, \
.dma_irq = SPI7_TX_DMA_IRQ, \
.HsInterface = SPI7_TX_DMA_HANDSHAK, \
.dma_rcc = SPI7_TX_DMA_DMA_RCC, \
.dma_channel = SPI7_TX_DMA_DMA_CHANNEL, \
.dmamux_channel = SPI7_TX_DMA_DMAMUX_CHANNEL, \
.dmamux_request = SPI7_TX_DMA_DMAMUX_REQUEST, \
}
#endif /* SPI7_TX_DMA_CONFIG */
#endif /* BSP_SPI7_TX_USING_DMA */
#ifdef BSP_SPI7_RX_USING_DMA
#ifndef SPI7_RX_DMA_CONFIG
#define SPI7_RX_DMA_CONFIG \
{ \
.Instance = SPI7_RX_DMA_INSTANCE, \
.dma_irq = SPI7_RX_DMA_IRQ, \
.HsInterface = SPI7_RX_DMA_HANDSHAK, \
.dma_rcc = SPI7_RX_DMA_DMA_RCC, \
.dma_channel = SPI7_RX_DMA_DMA_CHANNEL, \
.dmamux_channel = SPI7_RX_DMA_DMAMUX_CHANNEL, \
.dmamux_request = SPI7_RX_DMA_DMAMUX_REQUEST, \
}
#endif /* SPI7_RX_DMA_CONFIG */
#endif /* BSP_SPI7_RX_USING_DMA */
#ifdef __cplusplus
}
#endif
#endif /*__SPI_CONFIG_H__ */

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/*
* Copyright (c) 2006-2023, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2026-02-26 ox-horse first version
*/
#ifndef __TIM_CONFIG_H__
#define __TIM_CONFIG_H__
#include <rtthread.h>
#ifdef __cplusplus
extern "C" {
#endif
#ifndef TIM_DEV_INFO_CONFIG
#define TIM_DEV_INFO_CONFIG \
{ \
.maxfreq = 1000000, \
.minfreq = 3000, \
.maxcnt = 0xFFFF, \
.cntmode = CLOCK_TIMER_CNTMODE_UP, \
}
#endif /* TIM_DEV_INFO_CONFIG */
#ifdef BSP_USING_ATIM1
#ifndef ATIM1_CONFIG
#define ATIM1_CONFIG \
{ \
.timer = ATIM1, \
.tim_irqn = ATIM1_UP_IRQn, \
.name = "timer1", \
}
#endif /* ATIM1_CONFIG */
#endif /* BSP_USING_ATIM1 */
#ifdef BSP_USING_ATIM2
#ifndef ATIM2_CONFIG
#define ATIM2_CONFIG \
{ \
.timer = ATIM2, \
.tim_irqn = ATIM2_UP_IRQn, \
.name = "timer2", \
}
#endif /* ATIM2_CONFIG */
#endif /* BSP_USING_ATIM2 */
#ifdef BSP_USING_ATIM3
#ifndef ATIM3_CONFIG
#define ATIM3_CONFIG \
{ \
.timer = ATIM3, \
.tim_irqn = ATIM3_UP_IRQn, \
.name = "timer3", \
}
#endif /* ATIM3_CONFIG */
#endif /* BSP_USING_ATIM3 */
#ifdef BSP_USING_ATIM4
#ifndef ATIM4_CONFIG
#define ATIM4_CONFIG \
{ \
.timer = ATIM4, \
.tim_irqn = ATIM4_UP_IRQn, \
.name = "timer4", \
}
#endif /* ATIM4_CONFIG */
#endif /* BSP_USING_ATIM4 */
#ifdef BSP_USING_GTIMA1
#ifndef GTIMA1_CONFIG
#define GTIMA1_CONFIG \
{ \
.timer = GTIMA1, \
.tim_irqn = GTIMA1_IRQn, \
.name = "timer5", \
}
#endif /* GTIMA1_CONFIG */
#endif /* BSP_USING_GTIMA1 */
#ifdef BSP_USING_GTIMA2
#ifndef GTIMA2_CONFIG
#define GTIMA2_CONFIG \
{ \
.timer = GTIMA2, \
.tim_irqn = GTIMA2_IRQn, \
.name = "timer6", \
}
#endif /* GTIMA2_CONFIG */
#endif /* BSP_USING_GTIMA2 */
#ifdef BSP_USING_GTIMA3
#ifndef GTIMA3_CONFIG
#define GTIMA3_CONFIG \
{ \
.timer = GTIMA3, \
.tim_irqn = GTIMA3_IRQn, \
.name = "timer7", \
}
#endif /* GTIMA3_CONFIG */
#endif /* BSP_USING_GTIMA3 */
#ifdef BSP_USING_GTIMA4
#ifndef GTIMA4_CONFIG
#define GTIMA4_CONFIG \
{ \
.timer = GTIMA4, \
.tim_irqn = GTIMA4_IRQn, \
.name = "timer8", \
}
#endif /* GTIMA4_CONFIG */
#endif /* BSP_USING_GTIMA4 */
#ifdef BSP_USING_GTIMA5
#ifndef GTIMA5_CONFIG
#define GTIMA5_CONFIG \
{ \
.timer = GTIMA5, \
.tim_irqn = GTIMA5_IRQn, \
.name = "timer9", \
}
#endif /* GTIMA5_CONFIG */
#endif /* BSP_USING_GTIMA5 */
#ifdef BSP_USING_GTIMA6
#ifndef GTIMA6_CONFIG
#define GTIMA6_CONFIG \
{ \
.timer = GTIMA6, \
.tim_irqn = GTIMA6_IRQn, \
.name = "timer10", \
}
#endif /* GTIMA6_CONFIG */
#endif /* BSP_USING_GTIMA6 */
#ifdef BSP_USING_GTIMA7
#ifndef GTIMA7_CONFIG
#define GTIMA7_CONFIG \
{ \
.timer = GTIMA7, \
.tim_irqn = GTIMA7_IRQn, \
.name = "timer11", \
}
#endif /* GTIMA7_CONFIG */
#endif /* BSP_USING_GTIMA7 */
#ifdef BSP_USING_GTIMB1
#ifndef GTIMB1_CONFIG
#define GTIMB1_CONFIG \
{ \
.timer = GTIMB1, \
.tim_irqn = GTIMB1_IRQn, \
.name = "timer12", \
}
#endif /* GTIMB1_CONFIG */
#endif /* BSP_USING_GTIMB1 */
#ifdef BSP_USING_GTIMB2
#ifndef GTIMB2_CONFIG
#define GTIMB2_CONFIG \
{ \
.timer = GTIMB2, \
.tim_irqn = GTIMB2_IRQn, \
.name = "timer13", \
}
#endif /* GTIMB2_CONFIG */
#endif /* BSP_USING_GTIMB2 */
#ifdef BSP_USING_GTIMB3
#ifndef GTIMB3_CONFIG
#define GTIMB3_CONFIG \
{ \
.timer = GTIMB3, \
.tim_irqn = GTIMB3_IRQn, \
.name = "timer14", \
}
#endif /* GTIMB3_CONFIG */
#endif /* BSP_USING_GTIMB3 */
#ifdef BSP_USING_BTIM1
#ifndef BTIM1_CONFIG
#define BTIM1_CONFIG \
{ \
.timer = BTIM1, \
.tim_irqn = BTIM1_IRQn, \
.name = "timer15", \
}
#endif /* BTIM1_CONFIG */
#endif /* BSP_USING_BTIM1 */
#ifdef BSP_USING_BTIM2
#ifndef BTIM2_CONFIG
#define BTIM2_CONFIG \
{ \
.timer = BTIM2, \
.tim_irqn = BTIM2_IRQn, \
.name = "timer16", \
}
#endif /* BTIM2_CONFIG */
#endif /* BSP_USING_BTIM2 */
#ifdef BSP_USING_BTIM3
#ifndef BTIM3_CONFIG
#define BTIM3_CONFIG \
{ \
.timer = BTIM3, \
.tim_irqn = BTIM3_IRQn, \
.name = "timer17", \
}
#endif /* BTIM3_CONFIG */
#endif /* BSP_USING_BTIM3 */
#ifdef BSP_USING_BTIM4
#ifndef BTIM4_CONFIG
#define BTIM4_CONFIG \
{ \
.timer = BTIM4, \
.tim_irqn = BTIM4_IRQn, \
.name = "timer18", \
}
#endif /* BTIM4_CONFIG */
#endif /* BSP_USING_BTIM4 */
#ifdef __cplusplus
}
#endif
#endif /* __TIM_CONFIG_H__ */

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bsp/n32/n32hxxx/libraries/N32_Drivers/drivers/config/h7xx/uart_config.h Normal file
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@ -0,0 +1,814 @@
/*
* Copyright (c) 2006-2025, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2026-01-24 ox-horse first version
*/
#ifndef __UART_CONFIG_H__
#define __UART_CONFIG_H__
#include <rtthread.h>
#ifdef __cplusplus
extern "C" {
#endif
#if defined(BSP_USING_UART1)
#ifndef UART1_CONFIG
#define UART1_CONFIG \
{ \
.name = "uart1", \
.Instance = USART1, \
.irq_type = USART1_IRQn, \
.periph = RCC_APB1_PERIPHEN_M7_USART1, \
.EnablePeriphClk = RCC_EnableAPB1PeriphClk3, \
}
#endif /* UART1_CONFIG */
#endif /* BSP_USING_UART1 */
#if defined(BSP_UART1_RX_USING_DMA)
#if defined(UART1_RX_DMA_INSTANCE)
#ifndef UART1_DMA_RX_CONFIG
#define UART1_DMA_RX_CONFIG \
{ \
.Instance = UART1_RX_DMA_INSTANCE, \
.dma_irq = UART1_RX_DMA_IRQ, \
.HsInterface = UART1_RX_DMA_HANDSHAK, \
.dma_rcc = UART1_RX_DMA_DMA_RCC, \
.dma_channel = UART1_RX_DMA_DMA_CHANNEL, \
.dmamux_channel = UART1_RX_DMA_DMAMUX_CHANNEL, \
.dmamux_request = UART1_RX_DMA_DMAMUX_REQUEST, \
}
#endif /* UART1_DMA_RX_CONFIG */
#else
#error "The DMA resource is not available."
#endif /* UART1_RX_DMA_INSTANCE */
#endif /* BSP_UART1_RX_USING_DMA */
#if defined(BSP_UART1_TX_USING_DMA)
#if defined(UART1_TX_DMA_INSTANCE)
#ifndef UART1_DMA_TX_CONFIG
#define UART1_DMA_TX_CONFIG \
{ \
.Instance = UART1_TX_DMA_INSTANCE, \
.dma_irq = UART1_TX_DMA_IRQ, \
.HsInterface = UART1_TX_DMA_HANDSHAK, \
.dma_rcc = UART1_TX_DMA_DMA_RCC, \
.dma_channel = UART1_TX_DMA_DMA_CHANNEL, \
.dmamux_channel = UART1_TX_DMA_DMAMUX_CHANNEL, \
.dmamux_request = UART1_TX_DMA_DMAMUX_REQUEST, \
}
#endif /* UART1_DMA_TX_CONFIG */
#else
#error "The DMA resource is not available."
#endif /* UART1_TX_DMA_INSTANCE */
#endif /* BSP_UART1_TX_USING_DMA */
#if defined(BSP_USING_UART2)
#ifndef UART2_CONFIG
#define UART2_CONFIG \
{ \
.name = "uart2", \
.Instance = USART2, \
.irq_type = USART2_IRQn, \
.periph = RCC_APB1_PERIPHEN_M7_USART2, \
.EnablePeriphClk = RCC_EnableAPB1PeriphClk3, \
}
#endif /* UART2_CONFIG */
#endif /* BSP_USING_UART2 */
#if defined(BSP_UART2_RX_USING_DMA)
#if defined(UART2_RX_DMA_INSTANCE)
#ifndef UART2_DMA_RX_CONFIG
#define UART2_DMA_RX_CONFIG \
{ \
.Instance = UART2_RX_DMA_INSTANCE, \
.dma_irq = UART2_RX_DMA_IRQ, \
.HsInterface = UART2_RX_DMA_HANDSHAK, \
.dma_rcc = UART2_RX_DMA_DMA_RCC, \
.dma_channel = UART2_RX_DMA_DMA_CHANNEL, \
.dmamux_channel = UART2_RX_DMA_DMAMUX_CHANNEL, \
.dmamux_request = UART2_RX_DMA_DMAMUX_REQUEST, \
}
#endif /* UART2_DMA_RX_CONFIG */
#else
#error "The DMA resource is not available."
#endif /* UART2_RX_DMA_INSTANCE */
#endif /* BSP_UART2_RX_USING_DMA */
#if defined(BSP_UART2_TX_USING_DMA)
#if defined(UART2_TX_DMA_INSTANCE)
#ifndef UART2_DMA_TX_CONFIG
#define UART2_DMA_TX_CONFIG \
{ \
.Instance = UART2_TX_DMA_INSTANCE, \
.dma_irq = UART2_TX_DMA_IRQ, \
.HsInterface = UART2_TX_DMA_HANDSHAK, \
.dma_rcc = UART2_TX_DMA_DMA_RCC, \
.dma_channel = UART2_TX_DMA_DMA_CHANNEL, \
.dmamux_channel = UART2_TX_DMA_DMAMUX_CHANNEL, \
.dmamux_request = UART2_TX_DMA_DMAMUX_REQUEST, \
}
#endif /* UART2_DMA_TX_CONFIG */
#else
#error "The DMA resource is not available."
#endif /* UART2_TX_DMA_INSTANCE */
#endif /* BSP_UART2_TX_USING_DMA */
#if defined(BSP_USING_UART3)
#ifndef UART3_CONFIG
#define UART3_CONFIG \
{ \
.name = "uart3", \
.Instance = USART3, \
.irq_type = USART3_IRQn, \
.periph = RCC_APB1_PERIPHEN_M7_USART3, \
.EnablePeriphClk = RCC_EnableAPB1PeriphClk3, \
}
#endif /* UART3_CONFIG */
#endif /* BSP_USING_UART3 */
#if defined(BSP_UART3_RX_USING_DMA)
#if defined(UART3_RX_DMA_INSTANCE)
#ifndef UART3_DMA_RX_CONFIG
#define UART3_DMA_RX_CONFIG \
{ \
.Instance = UART3_RX_DMA_INSTANCE, \
.dma_irq = UART3_RX_DMA_IRQ, \
.HsInterface = UART3_RX_DMA_HANDSHAK, \
.dma_rcc = UART3_RX_DMA_DMA_RCC, \
.dma_channel = UART3_RX_DMA_DMA_CHANNEL, \
.dmamux_channel = UART3_RX_DMA_DMAMUX_CHANNEL, \
.dmamux_request = UART3_RX_DMA_DMAMUX_REQUEST, \
}
#endif /* UART3_DMA_RX_CONFIG */
#else
#error "The DMA resource is not available."
#endif /* UART3_RX_DMA_INSTANCE */
#endif /* BSP_UART3_RX_USING_DMA */
#if defined(BSP_UART3_TX_USING_DMA)
#if defined(UART3_TX_DMA_INSTANCE)
#ifndef UART3_DMA_TX_CONFIG
#define UART3_DMA_TX_CONFIG \
{ \
.Instance = UART3_TX_DMA_INSTANCE, \
.dma_irq = UART3_TX_DMA_IRQ, \
.HsInterface = UART3_TX_DMA_HANDSHAK, \
.dma_rcc = UART3_TX_DMA_DMA_RCC, \
.dma_channel = UART3_TX_DMA_DMA_CHANNEL, \
.dmamux_channel = UART3_TX_DMA_DMAMUX_CHANNEL, \
.dmamux_request = UART3_TX_DMA_DMAMUX_REQUEST, \
}
#endif /* UART3_DMA_TX_CONFIG */
#else
#error "The DMA resource is not available."
#endif /* UART3_TX_DMA_INSTANCE */
#endif /* BSP_UART3_TX_USING_DMA */
#if defined(BSP_USING_UART4)
#ifndef UART4_CONFIG
#define UART4_CONFIG \
{ \
.name = "uart4", \
.Instance = USART4, \
.irq_type = USART4_IRQn, \
.periph = RCC_APB1_PERIPHEN_M7_USART4, \
.EnablePeriphClk = RCC_EnableAPB1PeriphClk3, \
}
#endif /* UART4_CONFIG */
#endif /* BSP_USING_UART4 */
#if defined(BSP_UART4_RX_USING_DMA)
#if defined(UART4_RX_DMA_INSTANCE)
#ifndef UART4_DMA_RX_CONFIG
#define UART4_DMA_RX_CONFIG \
{ \
.Instance = UART4_RX_DMA_INSTANCE, \
.dma_irq = UART4_RX_DMA_IRQ, \
.HsInterface = UART4_RX_DMA_HANDSHAK, \
.dma_rcc = UART4_RX_DMA_DMA_RCC, \
.dma_channel = UART4_RX_DMA_DMA_CHANNEL, \
.dmamux_channel = UART4_RX_DMA_DMAMUX_CHANNEL, \
.dmamux_request = UART4_RX_DMA_DMAMUX_REQUEST, \
}
#endif /* UART4_DMA_RX_CONFIG */
#else
#error "The DMA resource is not available."
#endif /* UART4_RX_DMA_INSTANCE */
#endif /* BSP_UART4_RX_USING_DMA */
#if defined(BSP_UART4_TX_USING_DMA)
#if defined(UART4_TX_DMA_INSTANCE)
#ifndef UART4_DMA_TX_CONFIG
#define UART4_DMA_TX_CONFIG \
{ \
.Instance = UART4_TX_DMA_INSTANCE, \
.dma_irq = UART4_TX_DMA_IRQ, \
.HsInterface = UART4_TX_DMA_HANDSHAK, \
.dma_rcc = UART4_TX_DMA_DMA_RCC, \
.dma_channel = UART4_TX_DMA_DMA_CHANNEL, \
.dmamux_channel = UART4_TX_DMA_DMAMUX_CHANNEL, \
.dmamux_request = UART4_TX_DMA_DMAMUX_REQUEST, \
}
#endif /* UART4_DMA_TX_CONFIG */
#else
#error "The DMA resource is not available."
#endif /* UART4_TX_DMA_INSTANCE */
#endif /* BSP_UART4_TX_USING_DMA */
#if defined(BSP_USING_UART5)
#ifndef UART5_CONFIG
#define UART5_CONFIG \
{ \
.name = "uart5", \
.Instance = USART5, \
.irq_type = USART5_IRQn, \
.periph = RCC_APB2_PERIPHEN_M7_USART5, \
.EnablePeriphClk = RCC_EnableAPB2PeriphClk3, \
}
#endif /* UART5_CONFIG */
#endif /* BSP_USING_UART5 */
#if defined(BSP_UART5_RX_USING_DMA)
#if defined(UART5_RX_DMA_INSTANCE)
#ifndef UART5_DMA_RX_CONFIG
#define UART5_DMA_RX_CONFIG \
{ \
.Instance = UART5_RX_DMA_INSTANCE, \
.dma_irq = UART5_RX_DMA_IRQ, \
.HsInterface = UART5_RX_DMA_HANDSHAK, \
.dma_rcc = UART5_RX_DMA_DMA_RCC, \
.dma_channel = UART5_RX_DMA_DMA_CHANNEL, \
.dmamux_channel = UART5_RX_DMA_DMAMUX_CHANNEL, \
.dmamux_request = UART5_RX_DMA_DMAMUX_REQUEST, \
}
#endif /* UART5_DMA_RX_CONFIG */
#else
#error "The DMA resource is not available."
#endif /* UART5_RX_DMA_INSTANCE */
#endif /* BSP_UART5_RX_USING_DMA */
#if defined(BSP_UART5_TX_USING_DMA)
#if defined(UART5_TX_DMA_INSTANCE)
#ifndef UART5_DMA_TX_CONFIG
#define UART5_DMA_TX_CONFIG \
{ \
.Instance = UART5_TX_DMA_INSTANCE, \
.dma_irq = UART5_TX_DMA_IRQ, \
.HsInterface = UART5_TX_DMA_HANDSHAK, \
.dma_rcc = UART5_TX_DMA_DMA_RCC, \
.dma_channel = UART5_TX_DMA_DMA_CHANNEL, \
.dmamux_channel = UART5_TX_DMA_DMAMUX_CHANNEL, \
.dmamux_request = UART5_TX_DMA_DMAMUX_REQUEST, \
}
#endif /* UART5_DMA_TX_CONFIG */
#else
#error "The DMA resource is not available."
#endif /* UART5_TX_DMA_INSTANCE */
#endif /* BSP_UART5_TX_USING_DMA */
#if defined(BSP_USING_UART6)
#ifndef UART6_CONFIG
#define UART6_CONFIG \
{ \
.name = "uart6", \
.Instance = USART6, \
.irq_type = USART6_IRQn, \
.periph = RCC_APB2_PERIPHEN_M7_USART6, \
.EnablePeriphClk = RCC_EnableAPB2PeriphClk3, \
}
#endif /* UART6_CONFIG */
#endif /* BSP_USING_UART6 */
#if defined(BSP_UART6_RX_USING_DMA)
#if defined(UART6_RX_DMA_INSTANCE)
#ifndef UART6_DMA_RX_CONFIG
#define UART6_DMA_RX_CONFIG \
{ \
.Instance = UART6_RX_DMA_INSTANCE, \
.dma_irq = UART6_RX_DMA_IRQ, \
.HsInterface = UART6_RX_DMA_HANDSHAK, \
.dma_rcc = UART6_RX_DMA_DMA_RCC, \
.dma_channel = UART6_RX_DMA_DMA_CHANNEL, \
.dmamux_channel = UART6_RX_DMA_DMAMUX_CHANNEL, \
.dmamux_request = UART6_RX_DMA_DMAMUX_REQUEST, \
}
#endif /* UART6_DMA_RX_CONFIG */
#else
#error "The DMA resource is not available."
#endif /* UART6_RX_DMA_INSTANCE */
#endif /* BSP_UART6_RX_USING_DMA */
#if defined(BSP_UART6_TX_USING_DMA)
#if defined(UART6_TX_DMA_INSTANCE)
#ifndef UART6_DMA_TX_CONFIG
#define UART6_DMA_TX_CONFIG \
{ \
.Instance = UART6_TX_DMA_INSTANCE, \
.dma_irq = UART6_TX_DMA_IRQ, \
.HsInterface = UART6_TX_DMA_HANDSHAK, \
.dma_rcc = UART6_TX_DMA_DMA_RCC, \
.dma_channel = UART6_TX_DMA_DMA_CHANNEL, \
.dmamux_channel = UART6_TX_DMA_DMAMUX_CHANNEL, \
.dmamux_request = UART6_TX_DMA_DMAMUX_REQUEST, \
}
#endif /* UART6_DMA_TX_CONFIG */
#else
#error "The DMA resource is not available."
#endif /* UART6_TX_DMA_INSTANCE */
#endif /* BSP_UART6_TX_USING_DMA */
#if defined(BSP_USING_UART7)
#ifndef UART7_CONFIG
#define UART7_CONFIG \
{ \
.name = "uart7", \
.Instance = USART7, \
.irq_type = USART7_IRQn, \
.periph = RCC_APB2_PERIPHEN_M7_USART7, \
.EnablePeriphClk = RCC_EnableAPB2PeriphClk3, \
}
#endif /* UART7_CONFIG */
#endif /* BSP_USING_UART7 */
#if defined(BSP_UART7_RX_USING_DMA)
#if defined(UART7_RX_DMA_INSTANCE)
#ifndef UART7_DMA_RX_CONFIG
#define UART7_DMA_RX_CONFIG \
{ \
.Instance = UART7_RX_DMA_INSTANCE, \
.dma_irq = UART7_RX_DMA_IRQ, \
.HsInterface = UART7_RX_DMA_HANDSHAK, \
.dma_rcc = UART7_RX_DMA_DMA_RCC, \
.dma_channel = UART7_RX_DMA_DMA_CHANNEL, \
.dmamux_channel = UART7_RX_DMA_DMAMUX_CHANNEL, \
.dmamux_request = UART7_RX_DMA_DMAMUX_REQUEST, \
}
#endif /* UART7_DMA_RX_CONFIG */
#else
#error "The DMA resource is not available."
#endif /* UART7_RX_DMA_INSTANCE */
#endif /* BSP_UART7_RX_USING_DMA */
#if defined(BSP_UART7_TX_USING_DMA)
#if defined(UART7_TX_DMA_INSTANCE)
#ifndef UART7_DMA_TX_CONFIG
#define UART7_DMA_TX_CONFIG \
{ \
.Instance = UART7_TX_DMA_INSTANCE, \
.dma_irq = UART7_TX_DMA_IRQ, \
.HsInterface = UART7_TX_DMA_HANDSHAK, \
.dma_rcc = UART7_TX_DMA_DMA_RCC, \
.dma_channel = UART7_TX_DMA_DMA_CHANNEL, \
.dmamux_channel = UART7_TX_DMA_DMAMUX_CHANNEL, \
.dmamux_request = UART7_TX_DMA_DMAMUX_REQUEST, \
}
#endif /* UART7_DMA_TX_CONFIG */
#else
#error "The DMA resource is not available."
#endif /* UART7_TX_DMA_INSTANCE */
#endif /* BSP_UART7_TX_USING_DMA */
#if defined(BSP_USING_UART8)
#ifndef UART8_CONFIG
#define UART8_CONFIG \
{ \
.name = "uart8", \
.Instance = USART8, \
.irq_type = USART8_IRQn, \
.periph = RCC_APB2_PERIPHEN_M7_USART8, \
.EnablePeriphClk = RCC_EnableAPB2PeriphClk3, \
}
#endif /* UART8_CONFIG */
#endif /* BSP_USING_UART8 */
#if defined(BSP_UART8_RX_USING_DMA)
#if defined(UART8_RX_DMA_INSTANCE)
#ifndef UART8_DMA_RX_CONFIG
#define UART8_DMA_RX_CONFIG \
{ \
.Instance = UART8_RX_DMA_INSTANCE, \
.dma_irq = UART8_RX_DMA_IRQ, \
.HsInterface = UART8_RX_DMA_HANDSHAK, \
.dma_rcc = UART8_RX_DMA_DMA_RCC, \
.dma_channel = UART8_RX_DMA_DMA_CHANNEL, \
.dmamux_channel = UART8_RX_DMA_DMAMUX_CHANNEL, \
.dmamux_request = UART8_RX_DMA_DMAMUX_REQUEST, \
}
#endif /* UART8_DMA_RX_CONFIG */
#else
#error "The DMA resource is not available."
#endif /* UART8_RX_DMA_INSTANCE */
#endif /* BSP_UART8_RX_USING_DMA */
#if defined(BSP_UART8_TX_USING_DMA)
#if defined(UART8_TX_DMA_INSTANCE)
#ifndef UART8_DMA_TX_CONFIG
#define UART8_DMA_TX_CONFIG \
{ \
.Instance = UART8_TX_DMA_INSTANCE, \
.dma_irq = UART8_TX_DMA_IRQ, \
.HsInterface = UART8_TX_DMA_HANDSHAK, \
.dma_rcc = UART8_TX_DMA_DMA_RCC, \
.dma_channel = UART8_TX_DMA_DMA_CHANNEL, \
.dmamux_channel = UART8_TX_DMA_DMAMUX_CHANNEL, \
.dmamux_request = UART8_TX_DMA_DMAMUX_REQUEST, \
}
#endif /* UART8_DMA_TX_CONFIG */
#else
#error "The DMA resource is not available."
#endif /* UART8_TX_DMA_INSTANCE */
#endif /* BSP_UART8_TX_USING_DMA */
#if defined(BSP_USING_UART9)
#ifndef UART9_CONFIG
#define UART9_CONFIG \
{ \
.name = "uart9", \
.Instance = UART9, \
.irq_type = UART9_IRQn, \
.periph = RCC_APB1_PERIPHEN_M7_UART9, \
.EnablePeriphClk = RCC_EnableAPB1PeriphClk3, \
}
#endif /* UART9_CONFIG */
#endif /* BSP_USING_UART9 */
#if defined(BSP_UART9_RX_USING_DMA)
#if defined(UART9_RX_DMA_INSTANCE)
#ifndef UART9_DMA_RX_CONFIG
#define UART9_DMA_RX_CONFIG \
{ \
.Instance = UART9_RX_DMA_INSTANCE, \
.dma_irq = UART9_RX_DMA_IRQ, \
.HsInterface = UART9_RX_DMA_HANDSHAK, \
.dma_rcc = UART9_RX_DMA_DMA_RCC, \
.dma_channel = UART9_RX_DMA_DMA_CHANNEL, \
.dmamux_channel = UART9_RX_DMA_DMAMUX_CHANNEL, \
.dmamux_request = UART9_RX_DMA_DMAMUX_REQUEST, \
}
#endif /* UART9_DMA_RX_CONFIG */
#else
#error "The DMA resource is not available."
#endif /* UART9_RX_DMA_INSTANCE */
#endif /* BSP_UART9_RX_USING_DMA */
#if defined(BSP_UART9_TX_USING_DMA)
#if defined(UART9_TX_DMA_INSTANCE)
#ifndef UART9_DMA_TX_CONFIG
#define UART9_DMA_TX_CONFIG \
{ \
.Instance = UART9_TX_DMA_INSTANCE, \
.dma_irq = UART9_TX_DMA_IRQ, \
.HsInterface = UART9_TX_DMA_HANDSHAK, \
.dma_rcc = UART9_TX_DMA_DMA_RCC, \
.dma_channel = UART9_TX_DMA_DMA_CHANNEL, \
.dmamux_channel = UART9_TX_DMA_DMAMUX_CHANNEL, \
.dmamux_request = UART9_TX_DMA_DMAMUX_REQUEST, \
}
#endif /* UART9_DMA_TX_CONFIG */
#else
#error "The DMA resource is not available."
#endif /* UART9_TX_DMA_INSTANCE */
#endif /* BSP_UART9_TX_USING_DMA */
#if defined(BSP_USING_UART10)
#ifndef UART10_CONFIG
#define UART10_CONFIG \
{ \
.name = "uart10", \
.Instance = UART10, \
.irq_type = UART10_IRQn, \
.periph = RCC_APB1_PERIPHEN_M7_UART10, \
.EnablePeriphClk = RCC_EnableAPB1PeriphClk3, \
}
#endif /* UART10_CONFIG */
#endif /* BSP_USING_UART10 */
#if defined(BSP_UART10_RX_USING_DMA)
#if defined(UART10_RX_DMA_INSTANCE)
#ifndef UART10_DMA_RX_CONFIG
#define UART10_DMA_RX_CONFIG \
{ \
.Instance = UART10_RX_DMA_INSTANCE, \
.dma_irq = UART10_RX_DMA_IRQ, \
.HsInterface = UART10_RX_DMA_HANDSHAK, \
.dma_rcc = UART10_RX_DMA_DMA_RCC, \
.dma_channel = UART10_RX_DMA_DMA_CHANNEL, \
.dmamux_channel = UART10_RX_DMA_DMAMUX_CHANNEL, \
.dmamux_request = UART10_RX_DMA_DMAMUX_REQUEST, \
}
#endif /* UART10_DMA_RX_CONFIG */
#else
#error "The DMA resource is not available."
#endif /* UART10_RX_DMA_INSTANCE */
#endif /* BSP_UART10_RX_USING_DMA */
#if defined(BSP_UART10_TX_USING_DMA)
#if defined(UART10_TX_DMA_INSTANCE)
#ifndef UART10_DMA_TX_CONFIG
#define UART10_DMA_TX_CONFIG \
{ \
.Instance = UART10_TX_DMA_INSTANCE, \
.dma_irq = UART10_TX_DMA_IRQ, \
.HsInterface = UART10_TX_DMA_HANDSHAK, \
.dma_rcc = UART10_TX_DMA_DMA_RCC, \
.dma_channel = UART10_TX_DMA_DMA_CHANNEL, \
.dmamux_channel = UART10_TX_DMA_DMAMUX_CHANNEL, \
.dmamux_request = UART10_TX_DMA_DMAMUX_REQUEST, \
}
#endif /* UART10_DMA_TX_CONFIG */
#else
#error "The DMA resource is not available."
#endif /* UART10_TX_DMA_INSTANCE */
#endif /* BSP_UART10_TX_USING_DMA */
#if defined(BSP_USING_UART11)
#ifndef UART11_CONFIG
#define UART11_CONFIG \
{ \
.name = "uart11", \
.Instance = UART11, \
.irq_type = UART11_IRQn, \
.periph = RCC_APB1_PERIPHEN_M7_UART11, \
.EnablePeriphClk = RCC_EnableAPB1PeriphClk3, \
}
#endif /* UART11_CONFIG */
#endif /* BSP_USING_UART11 */
#if defined(BSP_UART11_RX_USING_DMA)
#if defined(UART11_RX_DMA_INSTANCE)
#ifndef UART11_DMA_RX_CONFIG
#define UART11_DMA_RX_CONFIG \
{ \
.Instance = UART11_RX_DMA_INSTANCE, \
.dma_irq = UART11_RX_DMA_IRQ, \
.HsInterface = UART11_RX_DMA_HANDSHAK, \
.dma_rcc = UART11_RX_DMA_DMA_RCC, \
.dma_channel = UART11_RX_DMA_DMA_CHANNEL, \
.dmamux_channel = UART11_RX_DMA_DMAMUX_CHANNEL, \
.dmamux_request = UART11_RX_DMA_DMAMUX_REQUEST, \
}
#endif /* UART11_DMA_RX_CONFIG */
#else
#error "The DMA resource is not available."
#endif /* UART11_RX_DMA_INSTANCE */
#endif /* BSP_UART11_RX_USING_DMA */
#if defined(BSP_UART11_TX_USING_DMA)
#if defined(UART11_TX_DMA_INSTANCE)
#ifndef UART11_DMA_TX_CONFIG
#define UART11_DMA_TX_CONFIG \
{ \
.Instance = UART11_TX_DMA_INSTANCE, \
.dma_irq = UART11_TX_DMA_IRQ, \
.HsInterface = UART11_TX_DMA_HANDSHAK, \
.dma_rcc = UART11_TX_DMA_DMA_RCC, \
.dma_channel = UART11_TX_DMA_DMA_CHANNEL, \
.dmamux_channel = UART11_TX_DMA_DMAMUX_CHANNEL, \
.dmamux_request = UART11_TX_DMA_DMAMUX_REQUEST, \
}
#endif /* UART11_DMA_TX_CONFIG */
#else
#error "The DMA resource is not available."
#endif /* UART11_TX_DMA_INSTANCE */
#endif /* BSP_UART11_TX_USING_DMA */
#if defined(BSP_USING_UART12)
#ifndef UART12_CONFIG
#define UART12_CONFIG \
{ \
.name = "uart12", \
.Instance = UART12, \
.irq_type = UART12_IRQn, \
.periph = RCC_APB1_PERIPHEN_M7_UART12, \
.EnablePeriphClk = RCC_EnableAPB1PeriphClk3, \
}
#endif /* UART12_CONFIG */
#endif /* BSP_USING_UART12 */
#if defined(BSP_UART12_RX_USING_DMA)
#if defined(UART12_RX_DMA_INSTANCE)
#ifndef UART12_DMA_RX_CONFIG
#define UART12_DMA_RX_CONFIG \
{ \
.Instance = UART12_RX_DMA_INSTANCE, \
.dma_irq = UART12_RX_DMA_IRQ, \
.HsInterface = UART12_RX_DMA_HANDSHAK, \
.dma_rcc = UART12_RX_DMA_DMA_RCC, \
.dma_channel = UART12_RX_DMA_DMA_CHANNEL, \
.dmamux_channel = UART12_RX_DMA_DMAMUX_CHANNEL, \
.dmamux_request = UART12_RX_DMA_DMAMUX_REQUEST, \
}
#endif /* UART12_DMA_RX_CONFIG */
#else
#error "The DMA resource is not available."
#endif /* UART12_RX_DMA_INSTANCE */
#endif /* BSP_UART12_RX_USING_DMA */
#if defined(BSP_UART12_TX_USING_DMA)
#if defined(UART12_TX_DMA_INSTANCE)
#ifndef UART12_DMA_TX_CONFIG
#define UART12_DMA_TX_CONFIG \
{ \
.Instance = UART12_TX_DMA_INSTANCE, \
.dma_irq = UART12_TX_DMA_IRQ, \
.HsInterface = UART12_TX_DMA_HANDSHAK, \
.dma_rcc = UART12_TX_DMA_DMA_RCC, \
.dma_channel = UART12_TX_DMA_DMA_CHANNEL, \
.dmamux_channel = UART12_TX_DMA_DMAMUX_CHANNEL, \
.dmamux_request = UART12_TX_DMA_DMAMUX_REQUEST, \
}
#endif /* UART12_DMA_TX_CONFIG */
#else
#error "The DMA resource is not available."
#endif /* UART12_TX_DMA_INSTANCE */
#endif /* BSP_UART12_TX_USING_DMA */
#if defined(BSP_USING_UART13)
#ifndef UART13_CONFIG
#define UART13_CONFIG \
{ \
.name = "uart13", \
.Instance = UART13, \
.irq_type = UART13_IRQn, \
.periph = RCC_APB2_PERIPHEN_M7_UART13, \
.EnablePeriphClk = RCC_EnableAPB2PeriphClk3, \
}
#endif /* UART13_CONFIG */
#endif /* BSP_USING_UART13 */
#if defined(BSP_UART13_RX_USING_DMA)
#if defined(UART13_RX_DMA_INSTANCE)
#ifndef UART13_DMA_RX_CONFIG
#define UART13_DMA_RX_CONFIG \
{ \
.Instance = UART13_RX_DMA_INSTANCE, \
.dma_irq = UART13_RX_DMA_IRQ, \
.HsInterface = UART13_RX_DMA_HANDSHAK, \
.dma_rcc = UART13_RX_DMA_DMA_RCC, \
.dma_channel = UART13_RX_DMA_DMA_CHANNEL, \
.dmamux_channel = UART13_RX_DMA_DMAMUX_CHANNEL, \
.dmamux_request = UART13_RX_DMA_DMAMUX_REQUEST, \
}
#endif /* UART13_DMA_RX_CONFIG */
#else
#error "The DMA resource is not available."
#endif /* UART13_RX_DMA_INSTANCE */
#endif /* BSP_UART13_RX_USING_DMA */
#if defined(BSP_UART13_TX_USING_DMA)
#if defined(UART13_TX_DMA_INSTANCE)
#ifndef UART13_DMA_TX_CONFIG
#define UART13_DMA_TX_CONFIG \
{ \
.Instance = UART13_TX_DMA_INSTANCE, \
.dma_irq = UART13_TX_DMA_IRQ, \
.HsInterface = UART13_TX_DMA_HANDSHAK, \
.dma_rcc = UART13_TX_DMA_DMA_RCC, \
.dma_channel = UART13_TX_DMA_DMA_CHANNEL, \
.dmamux_channel = UART13_TX_DMA_DMAMUX_CHANNEL, \
.dmamux_request = UART13_TX_DMA_DMAMUX_REQUEST, \
}
#endif /* UART13_DMA_TX_CONFIG */
#else
#error "The DMA resource is not available."
#endif /* UART13_TX_DMA_INSTANCE */
#endif /* BSP_UART13_TX_USING_DMA */
#if defined(BSP_USING_UART14)
#ifndef UART14_CONFIG
#define UART14_CONFIG \
{ \
.name = "uart14", \
.Instance = UART14, \
.irq_type = UART14_IRQn, \
.periph = RCC_APB2_PERIPHEN_M7_UART14, \
.EnablePeriphClk = RCC_EnableAPB2PeriphClk3, \
}
#endif /* UART14_CONFIG */
#endif /* BSP_USING_UART14 */
#if defined(BSP_UART14_RX_USING_DMA)
#if defined(UART14_RX_DMA_INSTANCE)
#ifndef UART14_DMA_RX_CONFIG
#define UART14_DMA_RX_CONFIG \
{ \
.Instance = UART14_RX_DMA_INSTANCE, \
.dma_irq = UART14_RX_DMA_IRQ, \
.HsInterface = UART14_RX_DMA_HANDSHAK, \
.dma_rcc = UART14_RX_DMA_DMA_RCC, \
.dma_channel = UART14_RX_DMA_DMA_CHANNEL, \
.dmamux_channel = UART14_RX_DMA_DMAMUX_CHANNEL, \
.dmamux_request = UART14_RX_DMA_DMAMUX_REQUEST, \
}
#endif /* UART14_DMA_RX_CONFIG */
#else
#error "The DMA resource is not available."
#endif /* UART14_RX_DMA_INSTANCE */
#endif /* BSP_UART14_RX_USING_DMA */
#if defined(BSP_UART14_TX_USING_DMA)
#if defined(UART14_TX_DMA_INSTANCE)
#ifndef UART14_DMA_TX_CONFIG
#define UART14_DMA_TX_CONFIG \
{ \
.Instance = UART14_TX_DMA_INSTANCE, \
.dma_irq = UART14_TX_DMA_IRQ, \
.HsInterface = UART14_TX_DMA_HANDSHAK, \
.dma_rcc = UART14_TX_DMA_DMA_RCC, \
.dma_channel = UART14_TX_DMA_DMA_CHANNEL, \
.dmamux_channel = UART14_TX_DMA_DMAMUX_CHANNEL, \
.dmamux_request = UART14_TX_DMA_DMAMUX_REQUEST, \
}
#endif /* UART14_DMA_TX_CONFIG */
#else
#error "The DMA resource is not available."
#endif /* UART14_TX_DMA_INSTANCE */
#endif /* BSP_UART14_TX_USING_DMA */
#if defined(BSP_USING_UART15)
#ifndef UART15_CONFIG
#define UART15_CONFIG \
{ \
.name = "uart15", \
.Instance = UART15, \
.irq_type = UART15_IRQn, \
.periph = RCC_APB2_PERIPHEN_M7_UART15, \
.EnablePeriphClk = RCC_EnableAPB2PeriphClk3, \
}
#endif /* UART15_CONFIG */
#endif /* BSP_USING_UART15 */
#if defined(BSP_UART15_RX_USING_DMA)
#if defined(UART15_RX_DMA_INSTANCE)
#ifndef UART15_DMA_RX_CONFIG
#define UART15_DMA_RX_CONFIG \
{ \
.Instance = UART15_RX_DMA_INSTANCE, \
.dma_irq = UART15_RX_DMA_IRQ, \
.HsInterface = UART15_RX_DMA_HANDSHAK, \
.dma_rcc = UART15_RX_DMA_DMA_RCC, \
.dma_channel = UART15_RX_DMA_DMA_CHANNEL, \
.dmamux_channel = UART15_RX_DMA_DMAMUX_CHANNEL, \
.dmamux_request = UART15_RX_DMA_DMAMUX_REQUEST, \
}
#endif /* UART15_DMA_RX_CONFIG */
#else
#error "The DMA resource is not available."
#endif /* UART15_RX_DMA_INSTANCE */
#endif /* BSP_UART15_RX_USING_DMA */
#if defined(BSP_UART15_TX_USING_DMA)
#if defined(UART15_TX_DMA_INSTANCE)
#ifndef UART15_DMA_TX_CONFIG
#define UART15_DMA_TX_CONFIG \
{ \
.Instance = UART15_TX_DMA_INSTANCE, \
.dma_irq = UART15_TX_DMA_IRQ, \
.HsInterface = UART15_TX_DMA_HANDSHAK, \
.dma_rcc = UART15_TX_DMA_DMA_RCC, \
.dma_channel = UART15_TX_DMA_DMA_CHANNEL, \
.dmamux_channel = UART15_TX_DMA_DMAMUX_CHANNEL, \
.dmamux_request = UART15_TX_DMA_DMAMUX_REQUEST, \
}
#endif /* UART15_DMA_TX_CONFIG */
#else
#error "The DMA resource is not available."
#endif /* UART15_TX_DMA_INSTANCE */
#endif /* BSP_UART15_TX_USING_DMA */
#if defined(BSP_USING_LPUART1)
#ifndef LPUART1_CONFIG
#define LPUART1_CONFIG \
{ \
.name = "lpuart1", \
.Instance = LPUART1, \
.irq_type = LPUART1_IRQn, \
.periph = RCC_RD_PERIPHEN_M7_LPUART1, \
.EnablePeriphClk = RCC_EnableRDPeriphClk1, \
}
#endif /* LPUART1_CONFIG */
#endif /* BSP_USING_LPUART1 */
#if defined(BSP_LPUART1_RX_USING_DMA)
#ifndef LPUART1_DMA_RX_CONFIG
#define LPUART1_DMA_RX_CONFIG \
{ \
.Instance = LPUART1_RX_DMA_INSTANCE, \
.dma_irq = LPUART1_RX_DMA_IRQ, \
.HsInterface = LPUART1_RX_DMA_HANDSHAK, \
.dma_rcc = LPUART1_RX_DMA_DMA_RCC, \
.dma_channel = LPUART1_RX_DMA_DMA_CHANNEL, \
.dmamux_channel = LPUART1_RX_DMA_DMAMUX_CHANNEL, \
.dmamux_request = LPUART1_RX_DMA_DMAMUX_REQUEST, \
}
#endif /* LPUART1_DMA_RX_CONFIG */
#endif /* BSP_LPUART1_RX_USING_DMA */
#if defined(BSP_USING_LPUART2)
#ifndef LPUART2_CONFIG
#define LPUART2_CONFIG \
{ \
.name = "lpuart2", \
.Instance = LPUART2, \
.irq_type = LPUART2_IRQn, \
.periph = RCC_RD_PERIPHEN_M7_LPUART2, \
.EnablePeriphClk = RCC_EnableRDPeriphClk1, \
}
#endif /* LPUART2_CONFIG */
#endif /* BSP_USING_LPUART2 */
#if defined(BSP_LPUART2_RX_USING_DMA)
#ifndef LPUART2_DMA_RX_CONFIG
#define LPUART2_DMA_RX_CONFIG \
{ \
.Instance = LPUART2_RX_DMA_INSTANCE, \
.dma_irq = LPUART2_RX_DMA_IRQ, \
.HsInterface = LPUART2_RX_DMA_HANDSHAK, \
.dma_rcc = LPUART2_RX_DMA_DMA_RCC, \
.dma_channel = LPUART2_RX_DMA_DMA_CHANNEL, \
.dmamux_channel = LPUART2_RX_DMA_DMAMUX_CHANNEL, \
.dmamux_request = LPUART2_RX_DMA_DMAMUX_REQUEST, \
}
#endif /* LPUART2_DMA_RX_CONFIG */
#endif /* BSP_LPUART2_RX_USING_DMA */
#ifdef __cplusplus
}
#endif
#endif /* __UART_CONFIG_H__ */

22
bsp/n32/n32hxxx/libraries/N32_Drivers/drivers/drv_config.h
View File

@ -20,11 +20,23 @@ extern "C" {
#if defined(SOC_SERIES_N32H7xx)
#include "h7/dma_config.h"
#include "h7/uart_config.h"
#include "h7/i2c_hard_config.h"
#include "h7/adc_config.h"
#include "h7/spi_config.h"
#include "h7xx/dma_config.h"
#include "h7xx/uart_config.h"
#include "h7xx/i2c_hard_config.h"
#include "h7xx/adc_config.h"
#include "h7xx/spi_config.h"
#include "h7xx/tim_config.h"
#include "h7xx/dac_config.h"
#include "h7xx/can_config.h"
#include "h7xx/pwm_config.h"
#include "h7xx/pulse_encoder_config.h"
#include "h7xx/lptim_config.h"
#elif defined(SOC_SERIES_N32H49x)
#include "h49x/dma_config.h"
#include "h49x/uart_config.h"
#elif defined(SOC_SERIES_N32H47x_48x)
#include "h47x_48x/dma_config.h"
#include "h47x_48x/uart_config.h"
#endif /* defined(SOC_SERIES_N32H7xx) */
#ifdef __cplusplus

168
bsp/n32/n32hxxx/libraries/N32_Drivers/drivers/drv_dac.c Normal file
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@ -0,0 +1,168 @@
/*
* Copyright (c) 2006-2025, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2026-01-24 ox-horse first version
* 2026-06-09 li.mengmeng port for N32H7xx
*/
#include <board.h>
#include <rtthread.h>
#if defined(BSP_USING_DAC1) || defined(BSP_USING_DAC2)
#include "n32h7xx_rcc.h"
#include "n32h7xx_dac.h"
#include "drv_config.h"
//#define DRV_DEBUG
#define LOG_TAG "drv.dac"
#include <drv_log.h>
typedef struct
{
DACX DACx;
DAC_Module *DAC_Module;
uint32_t periph_clk;
void (*EnablePeriphClk)(uint32_t periph, FunctionalState cmd);
uint32_t DAC_clk_pres;
GPIO_Module *GPIOx;
uint16_t GPIO_Pin;
uint32_t GPIO_RCC;
DAC_InitType Init;
} DAC_InitInfo_t;
static DAC_InitInfo_t dac_config[] = {
#ifdef BSP_USING_DAC1
DAC1_CONFIG,
#endif
#ifdef BSP_USING_DAC2
DAC2_CONFIG,
#endif
};
static struct n32_dac n32_dac_obj[sizeof(dac_config) / sizeof(dac_config[0])];
struct n32_dac
{
DAC_InitInfo_t DAC_Info;
struct rt_dac_device n32_dac_device;
};
static rt_err_t n32_dac_enabled(struct rt_dac_device *device, rt_uint32_t channel)
{
DAC_InitInfo_t *n32_dac_info;
RT_ASSERT(device != RT_NULL);
n32_dac_info = device->parent.user_data;
/* Enable DAC */
DAC_Enable(n32_dac_info->DACx, ENABLE);
return RT_EOK;
}
static rt_err_t n32_dac_disabled(struct rt_dac_device *device, rt_uint32_t channel)
{
DAC_InitInfo_t *n32_dac_info;
RT_ASSERT(device != RT_NULL);
n32_dac_info = device->parent.user_data;
/* Disable DAC */
DAC_Enable(n32_dac_info->DACx, DISABLE);
return RT_EOK;
}
static rt_uint8_t n32_dac_get_resolution(struct rt_dac_device *device)
{
RT_ASSERT(device != RT_NULL);
/* N32H7xx DAC supports 12-bit resolution */
return 12;
}
static rt_err_t n32_set_dac_value(struct rt_dac_device *device, rt_uint32_t channel, rt_uint32_t *value)
{
rt_uint16_t set_value;
DAC_InitInfo_t *n32_dac_info;
RT_ASSERT(device != RT_NULL);
RT_ASSERT(value != RT_NULL);
n32_dac_info = device->parent.user_data;
set_value = (rt_uint16_t)(*value);
if (set_value > 4095)
{
set_value = 4095;
}
/* Set DAC output data (12-bit right-aligned) */
DAC_SetData(n32_dac_info->DACx, DAC_ALIGN_R_12BIT, set_value);
/* Trigger software conversion */
DAC_SoftTrgEnable(n32_dac_info->DACx, ENABLE);
return RT_EOK;
}
static const struct rt_dac_ops n32_dac_ops = {
.disabled = n32_dac_disabled,
.enabled = n32_dac_enabled,
.convert = n32_set_dac_value,
.get_resolution = n32_dac_get_resolution,
};
static int n32_dac_init(void)
{
int result = RT_EOK;
char name_buf[5] = { 'd', 'a', 'c', '0', 0 };
int i = 0;
for (i = 0; i < sizeof(dac_config) / sizeof(dac_config[0]); i++)
{
n32_dac_obj[i].DAC_Info = dac_config[i];
/* Set device name */
name_buf[3] = '0';
if (n32_dac_obj[i].DAC_Info.DACx == DAC1)
name_buf[3] = '1';
else if (n32_dac_obj[i].DAC_Info.DACx == DAC2)
name_buf[3] = '2';
/* Enable DAC peripheral clock */
n32_dac_obj[i].DAC_Info.EnablePeriphClk(n32_dac_obj[i].DAC_Info.periph_clk, ENABLE);
/* Config DAC12 prescaler factor,DAC_CLK = 1M*/
DAC_ConfigClkPrescaler(n32_dac_obj[i].DAC_Info.DAC_Module, n32_dac_obj[i].DAC_Info.DAC_clk_pres);
DAC_SetHighFrequencyMode(n32_dac_obj[i].DAC_Info.DAC_Module, DAC_HIGH_FREQ_MODE_BELOW_160M);
/* Initialize DAC */
DAC_Init(n32_dac_obj[i].DAC_Info.DACx, &n32_dac_obj[i].DAC_Info.Init);
/* Register DAC device */
if (rt_hw_dac_register(&n32_dac_obj[i].n32_dac_device, name_buf, &n32_dac_ops, &n32_dac_obj[i].DAC_Info) == RT_EOK)
{
LOG_D("%s init success", name_buf);
}
else
{
LOG_E("%s register failed", name_buf);
result = -RT_ERROR;
}
}
return result;
}
INIT_DEVICE_EXPORT(n32_dac_init);
#endif /* BSP_USING_DACx */

15
bsp/n32/n32hxxx/libraries/N32_Drivers/drivers/drv_dma.h
View File

@ -18,7 +18,8 @@
extern "C" {
#endif
#define DMA_BLOCK_SIZE (4095)
#if defined(SOC_SERIES_N32H7xx)
#define DMA_BLOCK_SIZE (4095)
struct dma_config
{
@ -30,6 +31,18 @@ struct dma_config
rt_uint32_t dmamux_channel;
rt_uint32_t dmamux_request;
};
#elif defined(SOC_SERIES_N32H49x) || defined(SOC_SERIES_N32H47x_48x)
struct dma_config
{
DMA_Module *DMAy;
DMA_ChannelType *DMAChx;
IRQn_Type dma_irq;
rt_uint32_t dma_rcc;
rt_uint32_t request;
rt_uint32_t channel;
};
#endif
#ifdef __cplusplus
}

1023
bsp/n32/n32hxxx/libraries/N32_Drivers/drivers/drv_eth.c Normal file
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File diff suppressed because it is too large Load Diff

204
bsp/n32/n32hxxx/libraries/N32_Drivers/drivers/drv_eth.h Normal file
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@ -0,0 +1,204 @@
/*
* Copyright (c) 2006-2025, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2026-06-24 ox-horse first version
*/
#ifndef __DRV_ETH_H__
#define __DRV_ETH_H__
#include <rtthread.h>
#include <rthw.h>
#include <rtdevice.h>
#include <board.h>
#include "n32h7xx_eth.h"
#include "n32h7xx_rcc.h"
#include "n32h7xx_pwr.h"
#ifdef __cplusplus
extern "C" {
#endif
/* ======================= ETH Instance Selection ======================= */
#if defined(BSP_USING_ETH1)
#define ETH ETH1
#define ETH_RCC_ENABLE_AHB_PERIPHEN_CLK RCC_EnableAHB2PeriphClk2
#define ETH_RCC_AHB_PERIPHEN_CLK RCC_AHB2_PERIPHEN_M7_ETH1CLK
#define ETH_RCC_AHB_PERIPHEN (RCC_AHB2_PERIPHEN_M7_ETH1MAC | \
RCC_AHB2_PERIPHEN_M7_ETH1TX | \
RCC_AHB2_PERIPHEN_M7_ETH1RX)
#define ETH_GLOBAL_IRQ ETH1_IRQn
#define ETH_PWR_CTRL HSC1_ETH1_PWRCTRL
#define ETH_GLOBAL_IRQHANDLER ETH1_IRQHandler
#elif defined(BSP_USING_ETH2)
#define ETH ETH2
#define ETH_RCC_ENABLE_AHB_PERIPHEN_CLK RCC_EnableAHB1PeriphClk2
#define ETH_RCC_AHB_PERIPHEN_CLK RCC_AHB1_PERIPHEN_M7_ETH2CLK
#define ETH_RCC_AHB_PERIPHEN (RCC_AHB1_PERIPHEN_M7_ETH2MAC | \
RCC_AHB1_PERIPHEN_M7_ETH2TX | \
RCC_AHB1_PERIPHEN_M7_ETH2RX)
#define ETH_GLOBAL_IRQ ETH2_IRQn
#define ETH_PWR_CTRL HSC2_ETH2_PWRCTRL
#define ETH_GLOBAL_IRQHANDLER ETH2_IRQHandler
#endif /* BSP_USING_ETH1 / BSP_USING_ETH2 */
/* ======================= Media Interface Selection ======================= */
#if defined(ETH_INTERFACE_USING_GMII)
#define ETH_MEDIA_INTERFACE ETH_GMII_MODE
#elif defined(ETH_INTERFACE_USING_MII)
#define ETH_MEDIA_INTERFACE ETH_MII_MODE
#elif defined(ETH_INTERFACE_USING_RMII)
#define ETH_MEDIA_INTERFACE ETH_RMII_MODE
#else
#define ETH_MEDIA_INTERFACE ETH_GMII_MODE
#endif
/* ======================= Standard IEEE 802.3 PHY Registers ======================= */
#define PHY_BASIC_CONTROL_REG 0x00U
#define PHY_BASIC_STATUS_REG 0x01U
#define PHY_ID1_REG 0x02U
#define PHY_ID2_REG 0x03U
#define PHY_AUTONEG_ADVERTISE_REG 0x04U
#define PHY_AUTONEG_LINK_PARTNER 0x05U
#define PHY_GIGABIT_CONTROL_REG 0x09U /* 1000BASE-T Control Register */
#define PHY_GIGABIT_STATUS_REG 0x0AU /* 1000BASE-T Status Register */
/* Basic Control Register bits */
#define PHY_RESET_MASK (1 << 15)
#define PHY_LOOPBACK_MASK (1 << 14)
#define PHY_AUTO_NEGOTIATION_MASK (1 << 12)
#define PHY_POWER_DOWN_MASK (1 << 11)
#define PHY_RESTART_AUTONEG_MASK (1 << 9)
#define PHY_DUPLEX_MODE_MASK (1 << 8)
/* Basic Status Register bits */
#define PHY_100BASE_T4_MASK (1 << 15)
#define PHY_100BASE_TX_FD_MASK (1 << 14)
#define PHY_100BASE_TX_HD_MASK (1 << 13)
#define PHY_10BASE_T_FD_MASK (1 << 12)
#define PHY_10BASE_T_HD_MASK (1 << 11)
#define PHY_1000BASE_T_FD_MASK (1 << 10)
#define PHY_1000BASE_T_HD_MASK (1 << 9)
#define PHY_LINKED_STATUS_MASK (1 << 2)
#define PHY_AUTONEGO_COMPLETE_MASK (1 << 5)
/* ======================= DM9119INP PHY Specific Registers ======================= */
#ifdef PHY_USING_DM9119INP
/* DM9119INP is a Gigabit PHY supporting GMII/MII/RMII */
#define PHY_DM9119INP_ID1 0x006EU
#define PHY_DM9119INP_ID2 0x3212U
/* DM9119INP PHY Specific Status Register (0x11)
* bit[15:14] = 00 → 10M, 01 → 100M, 10 → 1000M
* bit[13] = 1 → Full-Duplex, 0 → Half-Duplex */
#define PHY_SDSR 0x11U
#define PHY_Status_SPEED_1000M(sr) (((sr) & (1 << 15)) != 0)
#define PHY_Status_SPEED_100M(sr) (((sr) & (1 << 14)) != 0)
#define PHY_Status_SPEED_10M(sr) (!PHY_Status_SPEED_1000M(sr) && !PHY_Status_SPEED_100M(sr))
#define PHY_Status_FULL_DUPLEX(sr) (((sr) & (1 << 13)) != 0)
/* DM9119INP PHY Specific Interrupt Registers
* 0x12 Interrupt Control, 0x13 Interrupt Status */
#define PHY_INTERRUPT_CTRL_REG 0x12U
#define PHY_INTERRUPT_FLAG_REG 0x13U
#define PHY_INTERRUPT_MASK_REG 0x12U
#define PHY_INT_MASK ((1 << 15) | (1 << 14) | (1 << 13) | (1 << 10))
#endif /* PHY_USING_DM9119INP */
/* ======================= YT8522H PHY Specific Registers ======================= */
#ifdef PHY_USING_YT8522H
/* YT8522H is a Fast Ethernet PHY supporting MII/RMII, up to 100M */
#define PHY_YT8522H_ID1 0x4F51U
#define PHY_YT8522H_ID2 0xE928U
/* YT8522H PHY Specific Status Register (0x11)
* bit[15:14] = 00 → 10M, 01 → 100M
* bit[13] = 1 → Full-Duplex, 0 → Half-Duplex */
#define PHY_SDSR 0x11U
#define PHY_Status_SPEED_100M(sr) (((sr) & (1 << 14)) != 0)
#define PHY_Status_SPEED_10M(sr) (!PHY_Status_SPEED_100M(sr))
#define PHY_Status_FULL_DUPLEX(sr) (((sr) & (1 << 13)) != 0)
/* YT8522H PHY Specific Interrupt Registers
* 0x12 Interrupt Control, 0x13 Interrupt Status
* bit15=Auto-Neg Fail, bit14=Speed Change, bit13=Duplex Change,
* bit11=Link Fail, bit10=Link Success */
#define PHY_INTERRUPT_CTRL_REG 0x12U
#define PHY_INTERRUPT_FLAG_REG 0x13U
#define PHY_INTERRUPT_MASK_REG 0x12U
#define PHY_INT_MASK ((1 << 15) | (1 << 14) | (1 << 13) | (1 << 11) | (1 << 10))
#endif /* PHY_USING_YT8522H */
/* ======================= RTL8211EG PHY Specific Registers ======================= */
#ifdef PHY_USING_RTL8211EG
/* RTL8211EG is a Gigabit PHY supporting GMII/MII/RMII */
#define PHY_RTL8211EG_ID1 0x001CU
#define PHY_RTL8211EG_ID2 0xC915U
/* RTL8211EG PHY Specific Status Register (0x11)
* bit[15:14] = 00 → 10M, 01 → 100M, 10 → 1000M
* bit[13] = 1 → Full-Duplex, 0 → Half-Duplex
* No unlock sequence needed — accessible via default register page. */
#define PHY_SDSR 0x11U
#define PHY_Status_SPEED_1000M(sr) (((sr) & (1 << 15)) != 0)
#define PHY_Status_SPEED_100M(sr) (((sr) & (1 << 14)) != 0)
#define PHY_Status_SPEED_10M(sr) (!PHY_Status_SPEED_1000M(sr) && !PHY_Status_SPEED_100M(sr))
#define PHY_Status_FULL_DUPLEX(sr) (((sr) & (1 << 13)) != 0)
/* RTL8211EG Interrupt Registers: 0x12 Control, 0x13 Status
* bit15=Auto-Neg Error, bit11=Auto-Neg Complete, bit10=Link Change */
#define PHY_INTERRUPT_CTRL_REG 0x12U
#define PHY_INTERRUPT_FLAG_REG 0x13U
#define PHY_INTERRUPT_MASK_REG 0x12U
#define PHY_INT_MASK ((1 << 15) | (1 << 11) | (1 << 10))
#endif /* PHY_USING_RTL8211EG */
/* ======================= Buffer & Descriptor Configuration ======================= */
#ifndef ETH_TX_DESC_NUMBER
#define ETH_TX_DESC_NUMBER ((uint32_t)4U)
#endif
#ifndef ETH_RX_DESC_NUMBER
#define ETH_RX_DESC_NUMBER ((uint32_t)4U)
#endif
/* ETH_MAX_PACKET_SIZE is defined in n32h7xx_eth.h (1528U) */
#define ETH_TX_BUF_SIZE (ETH_TX_DESC_NUMBER * ETH_MAX_PACKET_SIZE)
#define ETH_RX_BUF_SIZE (ETH_RX_DESC_NUMBER * ETH_MAX_PACKET_SIZE)
/* ======================= PHY Link Status Flags ======================= */
#define PHY_LINK (1 << 0)
#define PHY_10M (1 << 1)
#define PHY_100M (1 << 2)
#define PHY_1000M (1 << 3)
#define PHY_FULL_DUPLEX (1 << 4)
/* ---- test/monitoring accessors (enabled via DO_ETH_TEST) ---- */
#define DO_ETH_TEST 1
#if DO_ETH_TEST
rt_uint32_t n32_eth_get_speed(void);
rt_uint32_t n32_eth_get_duplex(void);
rt_uint8_t n32_eth_get_phy_addr(void);
void n32_eth_get_mac_addr(rt_uint8_t mac[6]);
const char *n32_eth_get_phy_name(void);
#endif /* DO_ETH_TEST */
#ifdef __cplusplus
}
#endif
#endif /* __DRV_ETH_H__ */

1488
bsp/n32/n32hxxx/libraries/N32_Drivers/drivers/drv_fdcan.c Normal file
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File diff suppressed because it is too large Load Diff

76
bsp/n32/n32hxxx/libraries/N32_Drivers/drivers/drv_fdcan.h Normal file
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@ -0,0 +1,76 @@
/*
* Copyright (c) 2006-2026, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2026-06-22 ox-horse first version - N32H7xx FDCAN driver
*/
#ifndef __DRV_FDCAN_H__
#define __DRV_FDCAN_H__
#include <rtdevice.h>
#include <rtthread.h>
#include <board.h>
#ifdef __cplusplus
extern "C" {
#endif
/**
*\*\name n32_fdcan_arb_timing.
*\*\brief FDCAN arbitration segment (nominal) baud rate timing entry.
*/
struct n32_fdcan_arb_timing
{
uint32_t baud_rate; /**< baud rate in bps */
uint16_t prescaler; /**< prescaler (1~512) */
uint8_t sjw; /**< synchronization jump width (1~128) */
uint16_t tseg1; /**< time segment 1 (2~256) */
uint8_t tseg2; /**< time segment 2 (2~128) */
};
/**
*\*\name n32_fdcan_data_timing.
*\*\brief FDCAN data segment baud rate timing entry (for CAN FD with BRS).
*/
struct n32_fdcan_data_timing
{
uint32_t baud_rate; /**< data phase baud rate in bps */
uint16_t prescaler; /**< data phase prescaler (1~32) */
uint8_t sjw; /**< data phase synchronization jump width (1~16) */
uint16_t tseg1; /**< data phase time segment 1 (1~32) */
uint8_t tseg2; /**< data phase time segment 2 (1~16) */
};
/**
*\*\name n32_fdcan.
*\*\brief N32 FDCAN device structure.
*\*\note GPIO pin initialization is handled by CubeMX-generated code
*\*\ in n32h7xx_cfg.c. This driver only handles peripheral configuration.
*/
struct n32_fdcan
{
const char *name; /**< device name */
FDCAN_Module *fdcan_x; /**< FDCAN peripheral base address (FDCAN1~FDCAN8) */
FDCAN_InitType init_struct; /**< FDCAN init parameters */
FDCAN_MsgRamType msg_ram; /**< Message RAM block config */
FDCAN_FilterType filter_cfg; /**< default filter configuration */
FDCAN_TxHeaderType tx_header; /**< TX header cache */
FDCAN_RxHeaderType rx_header; /**< RX header cache */
rt_uint32_t tx_pending_mask; /**< software mask of TX buffers with a pending request
(FDCAN_TX_BUFFER0<<i). Cleared when the ISR detects
TXBRP has gone to zero for that buffer, i.e. the
hardware finished/cancelled the transmission. */
struct rt_can_device device; /**< RT-Thread CAN device base */
};
int rt_hw_fdcan_init(void);
#ifdef __cplusplus
}
#endif
#endif /* __DRV_FDCAN_H__ */

119
bsp/n32g452xx/Libraries/rt_drivers/drv_flash.c → bsp/n32/n32hxxx/libraries/N32_Drivers/drivers/drv_flash/drv_flash_h7xx.c
View File

@ -1,40 +1,42 @@
/*
* Copyright (c) 2006-2023, RT-Thread Development Team
* Copyright (c) 2006-2025, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2021-08-20 breo.com first version
* Date Author Notes
* 2026-01-24 ox-horse first version
* 2026-06-16 li.mengmeng implement for N32H7xx
*/
#include <stddef.h>
#include <board.h>
#include <rtthread.h>
#include <rtconfig.h>
#include <rtdef.h>
#ifdef BSP_USING_ON_CHIP_FLASH
#include "drv_flash.h"
#include "drv_config.h"
#include "drv_flash_h7xx.h"
#include <board.h>
#include "n32h7xx_smu.h"
#if defined(RT_USING_FAL)
#include "fal.h"
#include "fal.h"
#endif
//#define DRV_DEBUG
#define LOG_TAG "drv.flash"
#define DRV_DEBUG
#define LOG_TAG "drv.flash"
#include <drv_log.h>
#define N32_FLASH_SECTOR_SIZE ((rt_uint32_t)0x1000) /* 4KB per erase sector */
#define N32_FLASH_PAGE_SIZE ((rt_uint32_t)0x1000) /* 4KB per page */
/**
* @brief Gets the page of a given address
* @param addr: address of the flash memory
* @param addr: Address of the FLASH Memory
* @retval The page of a given address
*/
static rt_uint32_t get_page(uint32_t addr)
static uint32_t GetPage(uint32_t addr)
{
rt_uint32_t page = 0;
page = RT_ALIGN_DOWN(addr, FLASH_PAGE_SIZE);
return page;
return RT_ALIGN_DOWN(addr, N32_FLASH_PAGE_SIZE);
}
/**
@ -59,7 +61,7 @@ int n32_flash_read(rt_uint32_t addr, rt_uint8_t *buf, size_t size)
for (i = 0; i < size; i++, buf++, addr++)
{
*buf = *(rt_uint8_t *) addr;
*buf = *(rt_uint8_t *)addr;
}
return size;
@ -67,8 +69,7 @@ int n32_flash_read(rt_uint32_t addr, rt_uint8_t *buf, size_t size)
/**
* Write data to flash.
* @note This operation's units is word.
* @note This operation must after erase. @see flash_erase.
* @note This operation must after erase. @see n32_flash_erase.
*
* @param addr flash address
* @param buf the write data buffer
@ -78,14 +79,8 @@ int n32_flash_read(rt_uint32_t addr, rt_uint8_t *buf, size_t size)
*/
int n32_flash_write(rt_uint32_t addr, const rt_uint8_t *buf, size_t size)
{
rt_err_t result = RT_EOK;
rt_uint32_t end_addr = addr + size;
if (addr % 4 != 0)
{
LOG_E("write addr must be 4-byte alignment");
return -RT_EINVAL;
}
rt_err_t result = RT_EOK;
rt_uint32_t end_addr = addr + size;
if ((end_addr) > N32_FLASH_END_ADDRESS)
{
@ -93,28 +88,15 @@ int n32_flash_write(rt_uint32_t addr, const rt_uint8_t *buf, size_t size)
return -RT_EINVAL;
}
FLASH_Unlock();
while (addr < end_addr)
if (size < 1)
{
if (FLASH_ProgramWord(addr, *((rt_uint32_t *)buf)) == FLASH_COMPL)
{
if (*(rt_uint32_t *)addr != *(rt_uint32_t *)buf)
{
result = -RT_ERROR;
break;
}
addr += 4;
buf += 4;
}
else
{
result = -RT_ERROR;
break;
}
return -RT_EINVAL;
}
FLASH_Lock();
if (SMU_WriteFlash(addr, (uint8_t *)buf, size) != FLASH_SUCCESS)
{
result = -RT_ERROR;
}
if (result != RT_EOK)
{
@ -125,9 +107,9 @@ int n32_flash_write(rt_uint32_t addr, const rt_uint8_t *buf, size_t size)
}
/**
* Erase data on flash .
* Erase data on flash.
* @note This operation is irreversible.
* @note This operation's units is different which on many chips.
* @note Erase unit is 4KB.
*
* @param addr flash address
* @param size erase bytes size
@ -136,39 +118,35 @@ int n32_flash_write(rt_uint32_t addr, const rt_uint8_t *buf, size_t size)
*/
int n32_flash_erase(rt_uint32_t addr, size_t size)
{
rt_err_t result = RT_EOK;
rt_err_t result = RT_EOK;
rt_uint32_t end_addr = addr + size;
rt_uint32_t page_addr = 0;
FLASH_Unlock();
rt_uint32_t erase_addr;
if ((end_addr) > N32_FLASH_END_ADDRESS)
{
LOG_E("erase outrange flash size! addr is (0x%p)", (void *)(addr + size));
LOG_E("ERROR: erase outrange flash size! addr is (0x%p)\n", (void *)(addr + size));
return -RT_EINVAL;
}
while (addr < end_addr)
{
page_addr = get_page(addr);
erase_addr = GetPage(addr);
if (FLASH_EraseOnePage(page_addr) != FLASH_COMPL)
while (erase_addr < end_addr)
{
if (SMU_EraseFlash(erase_addr) != FLASH_SUCCESS)
{
result = -RT_ERROR;
goto __exit;
}
addr += FLASH_PAGE_SIZE;
erase_addr += N32_FLASH_SECTOR_SIZE;
}
FLASH_Lock();
__exit:
if (result != RT_EOK)
{
return result;
}
LOG_D("erase done: addr (0x%p), size %d", (void *)addr, size);
return size;
}
@ -178,19 +156,7 @@ static int fal_flash_read(long offset, rt_uint8_t *buf, size_t size);
static int fal_flash_write(long offset, const rt_uint8_t *buf, size_t size);
static int fal_flash_erase(long offset, size_t size);
const struct fal_flash_dev n32_onchip_flash =
{
"onchip_flash",
N32_FLASH_START_ADRESS,
N32_FLASH_SIZE,
FLASH_PAGE_SIZE,
{
NULL,
fal_flash_read,
fal_flash_write,
fal_flash_erase
}
};
const struct fal_flash_dev n32_onchip_flash = { "onchip_flash", N32_FLASH_START_ADRESS, N32_FLASH_SIZE, N32_FLASH_SECTOR_SIZE, { NULL, fal_flash_read, fal_flash_write, fal_flash_erase } };
static int fal_flash_read(long offset, rt_uint8_t *buf, size_t size)
{
@ -207,5 +173,6 @@ static int fal_flash_erase(long offset, size_t size)
return n32_flash_erase(n32_onchip_flash.addr + offset, size);
}
#endif
#endif /* RT_USING_FAL */
#endif /* BSP_USING_ON_CHIP_FLASH */

14
bsp/n32g452xx/Libraries/rt_drivers/drv_flash.h → bsp/n32/n32hxxx/libraries/N32_Drivers/drivers/drv_flash/drv_flash_h7xx.h
View File

@ -1,19 +1,21 @@
/*
* Copyright (c) 2006-2023, RT-Thread Development Team
* Copyright (c) 2006-2025, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2021-08-20 breo.com first version
* Date Author Notes
* 2026-01-24 ox-horse first version
* 2026-06-16 li.mengmeng implement for N32H7xx
*/
#ifndef __DRV_FLASH_H__
#define __DRV_FLASH_H__
#ifndef __DRV_FLASH_H7XX_H__
#define __DRV_FLASH_H7XX_H__
#include <rtthread.h>
#include "rtdevice.h"
#include <rthw.h>
#include <drv_common.h>
#ifdef __cplusplus
extern "C" {
@ -27,4 +29,4 @@ int n32_flash_erase(rt_uint32_t addr, size_t size);
}
#endif
#endif /* __DRV_FLASH_H__ */
#endif /* __DRV_FLASH_H7XX_H__ */

108
bsp/n32/n32hxxx/libraries/N32_Drivers/drivers/drv_gpio.c
View File

@ -6,6 +6,7 @@
* Change Logs:
* Date Author Notes
* 2026-01-24 ox-horse first version
* 2026-04-07 ox-horse Add N32H49X and N32H47X_48X
*/
#include "drv_gpio.h"
@ -24,13 +25,21 @@
static uint32_t pin_irq_enable_mask = 0;
#if defined(GPIOK)
#define __N32_PORT_MAX 8u
#if defined(SOC_SERIES_N32H7xx)
#define __N32_PORT_MAX 8u
#endif
#elif defined(GPIOJ)
#define __N32_PORT_MAX 16u
#elif defined(GPIOI)
#define __N32_PORT_MAX 16u
#elif defined(GPIOH)
#define __N32_PORT_MAX 16u
#if defined(SOC_SERIES_N32H7xx)
#define __N32_PORT_MAX 16u
#elif defined(SOC_SERIES_N32H49x)
#define __N32_PORT_MAX 6u
#elif defined(SOC_SERIES_N32H47x_48x)
#define __N32_PORT_MAX 7u
#endif
#elif defined(GPIOG)
#define __N32_PORT_MAX 16u
#elif defined(GPIOF)
@ -362,8 +371,13 @@ static rt_err_t n32_pin_irq_enable(struct rt_device *device, rt_base_t pin,
irqmap = &pin_irq_map[irqindex];
/* EXTI Line Config */
#if defined(SOC_SERIES_N32H7xx)
GPIO_ConfigEXTILine(irqmap->exti_line, (PIN_NO(pin) * 11 + PIN_PORT(pin)));
#elif defined(SOC_SERIES_N32H49x) || defined(SOC_SERIES_N32H47x_48x)
// PA8-->Pin8--> PIN_PORT(1000)=0, PIN_NO(1000)=8
// PB1-->Pin17--> PIN_PORT(10001)=1, PIN_NO(10001)=1
GPIO_ConfigEXTILine(PIN_NO(pin), PIN_PORT(pin), PIN_NO(pin));
#endif
GPIO_InitStruct(&GPIO_InitStructure);
/* Configure GPIO_InitStructure */
GPIO_InitStructure.Pin = PIN_STPIN(pin);
@ -394,6 +408,9 @@ static rt_err_t n32_pin_irq_enable(struct rt_device *device, rt_base_t pin,
EXTI_InitStructure.EXTI_LineCmd = ENABLE;
EXTI_InitPeripheral(&EXTI_InitStructure);
/* Clear spurious pending bit caused by GPIO pull reconfiguration */
EXTI_ClrITPendBit(irqmap->exti_line);
NVIC_SetPriority(irqmap->irqno, NVIC_EncodePriority(NVIC_GetPriorityGrouping(), 5, 0));
NVIC_EnableIRQ(irqmap->irqno);
pin_irq_enable_mask |= irqmap->pinbit;
@ -462,6 +479,7 @@ rt_inline void pin_irq_hdr(int irqno)
void N32_GPIO_EXTI_Callback(uint16_t line_num)
{
#if defined(SOC_SERIES_N32H7xx)
if (pin_irq_hdr_tab[line_num].pin != -1 && EXTI_GetITStatus(line_num) != RESET)
{
/* Clear EXTI line pending bit */
@ -469,6 +487,18 @@ void N32_GPIO_EXTI_Callback(uint16_t line_num)
pin_irq_hdr(line_num);
}
#elif defined(SOC_SERIES_N32H49x) || defined(SOC_SERIES_N32H47x_48x)
{
rt_int32_t idx = bit2bitno(line_num);
if (idx >= 0 && idx < (rt_int32_t)ITEM_NUM(pin_irq_hdr_tab) && pin_irq_hdr_tab[idx].pin != -1 && EXTI_GetITStatus(line_num) != RESET)
{
/* Clear EXTI line pending bit */
EXTI_ClrITPendBit(line_num);
pin_irq_hdr(idx);
}
}
#endif
}
void EXTI0_IRQHandler(void)
@ -531,95 +561,139 @@ void EXTI15_10_IRQHandler(void)
int rt_hw_pin_init(void)
{
#ifdef AFIO
#if defined(SOC_SERIES_N32H7xx)
#if defined(AFIO)
RCC_EnableAHB5PeriphClk2(RCC_AHB5_PERIPHEN_M7_AFIO, ENABLE);
#if defined(SOC_N32H78X)
RCC_EnableAHB5PeriphClk2(RCC_AHB5_PERIPHEN_M4_AFIO, ENABLE);
#endif /* SOC_N32H78X */
#elif defined(SOC_SERIES_N32H49x)
RCC_EnableAPB2PeriphClk(RCC_APB2_PERIPHEN_AFIO, ENABLE);
#elif defined(SOC_SERIES_N32H47x_48x)
RCC_EnableAPB2PeriphClk(RCC_APB2_PERIPH_AFIO, ENABLE);
#endif
#endif /* AFIO */
#if defined(EXTI)
#ifdef EXTI
#if defined(SOC_SERIES_N32H7xx)
RCC_EnableAPB5PeriphClk2(RCC_APB5_PERIPHEN_EXTI, ENABLE);
#endif
#endif /* EXTI */
#if defined(GPIOA)
#ifdef GPIOA
#if defined(SOC_SERIES_N32H7xx)
RCC_EnableAHB5PeriphClk1(RCC_AHB5_PERIPHEN_M7_GPIOA, ENABLE);
#if defined(SOC_N32H78X)
RCC_EnableAHB5PeriphClk1(RCC_AHB5_PERIPHEN_M4_GPIOA, ENABLE);
#endif /* SOC_N32H78X */
#elif defined(SOC_SERIES_N32H49x) || defined(SOC_SERIES_N32H47x_48x)
RCC_EnableAHB1PeriphClk(RCC_AHB_PERIPHEN_GPIOA, ENABLE);
#endif
#endif /* GPIOA */
#if defined(GPIOB)
#ifdef GPIOB
#if defined(SOC_SERIES_N32H7xx)
RCC_EnableAHB5PeriphClk1(RCC_AHB5_PERIPHEN_M7_GPIOB, ENABLE);
#if defined(SOC_N32H78X)
RCC_EnableAHB5PeriphClk1(RCC_AHB5_PERIPHEN_M4_GPIOB, ENABLE);
#endif /* SOC_N32H78X */
#elif defined(SOC_SERIES_N32H49x) || defined(SOC_SERIES_N32H47x_48x)
RCC_EnableAHB1PeriphClk(RCC_AHB_PERIPHEN_GPIOB, ENABLE);
#endif
#endif /* GPIOB */
#if defined(GPIOC)
#ifdef GPIOC
#if defined(SOC_SERIES_N32H7xx)
RCC_EnableAHB5PeriphClk1(RCC_AHB5_PERIPHEN_M7_GPIOC, ENABLE);
#if defined(SOC_N32H78X)
RCC_EnableAHB5PeriphClk1(RCC_AHB5_PERIPHEN_M4_GPIOC, ENABLE);
#endif /* SOC_N32H78X */
#elif defined(SOC_SERIES_N32H49x) || defined(SOC_SERIES_N32H47x_48x)
RCC_EnableAHB1PeriphClk(RCC_AHB_PERIPHEN_GPIOC, ENABLE);
#endif
#endif /* GPIOC */
#if defined(GPIOD)
#ifdef GPIOD
#if defined(SOC_SERIES_N32H7xx)
RCC_EnableAHB5PeriphClk1(RCC_AHB5_PERIPHEN_M7_GPIOD, ENABLE);
#if defined(SOC_N32H78X)
RCC_EnableAHB5PeriphClk1(RCC_AHB5_PERIPHEN_M4_GPIOD, ENABLE);
#endif /* SOC_N32H78X */
#elif defined(SOC_SERIES_N32H49x) || defined(SOC_SERIES_N32H47x_48x)
RCC_EnableAHB1PeriphClk(RCC_AHB_PERIPHEN_GPIOD, ENABLE);
#endif
#endif /* GPIOD */
#if defined(GPIOE)
#ifdef GPIOE
#if defined(SOC_SERIES_N32H7xx)
RCC_EnableAHB5PeriphClk1(RCC_AHB5_PERIPHEN_M7_GPIOE, ENABLE);
#if defined(SOC_N32H78X)
RCC_EnableAHB5PeriphClk1(RCC_AHB5_PERIPHEN_M4_GPIOE, ENABLE);
#endif /* SOC_N32H78X */
#elif defined(SOC_SERIES_N32H49x) || defined(SOC_SERIES_N32H47x_48x)
RCC_EnableAHB1PeriphClk(RCC_AHB_PERIPHEN_GPIOE, ENABLE);
#endif
#endif /* GPIOE */
#if defined(GPIOF)
#ifdef GPIOF
#if defined(SOC_SERIES_N32H7xx)
RCC_EnableAHB5PeriphClk1(RCC_AHB5_PERIPHEN_M7_GPIOF, ENABLE);
#if defined(SOC_N32H78X)
RCC_EnableAHB5PeriphClk1(RCC_AHB5_PERIPHEN_M4_GPIOF, ENABLE);
#endif /* SOC_N32H78X */
#elif defined(SOC_SERIES_N32H49x) || defined(SOC_SERIES_N32H47x_48x)
RCC_EnableAHB1PeriphClk(RCC_AHB_PERIPHEN_GPIOF, ENABLE);
#endif
#endif /* GPIOF */
#if defined(GPIOG)
#ifdef GPIOG
#if defined(SOC_SERIES_N32H7xx)
RCC_EnableAHB5PeriphClk1(RCC_AHB5_PERIPHEN_M7_GPIOG, ENABLE);
#if defined(SOC_N32H78X)
RCC_EnableAHB5PeriphClk1(RCC_AHB5_PERIPHEN_M4_GPIOG, ENABLE);
#endif /* SOC_N32H78X */
#elif defined(SOC_SERIES_N32H49x) || defined(SOC_SERIES_N32H47x_48x)
RCC_EnableAHB1PeriphClk(RCC_AHB_PERIPHEN_GPIOG, ENABLE);
#endif
#endif /* GPIOG */
#if defined(GPIOH)
#ifdef GPIOH
#if defined(SOC_SERIES_N32H7xx)
RCC_EnableAHB5PeriphClk1(RCC_AHB5_PERIPHEN_M7_GPIOH, ENABLE);
#if defined(SOC_N32H78X)
RCC_EnableAHB5PeriphClk1(RCC_AHB5_PERIPHEN_M4_GPIOH, ENABLE);
#endif /* SOC_N32H78X */
#elif defined(SOC_SERIES_N32H49x) || defined(SOC_SERIES_N32H47x_48x)
RCC_EnableAHB1PeriphClk(RCC_AHB_PERIPHEN_GPIOH, ENABLE);
#endif
#endif /* GPIOH */
#if defined(GPIOI)
#ifdef GPIOI
#if defined(SOC_SERIES_N32H7xx)
RCC_EnableAHB5PeriphClk2(RCC_AHB5_PERIPHEN_M7_GPIOI, ENABLE);
#if defined(SOC_N32H78X)
RCC_EnableAHB5PeriphClk2(RCC_AHB5_PERIPHEN_M4_GPIOI, ENABLE);
#endif /* SOC_N32H78X */
#endif
#endif /* GPIOI */
#if defined(GPIOJ)
#ifdef GPIOJ
#if defined(SOC_SERIES_N32H7xx)
RCC_EnableAHB5PeriphClk2(RCC_AHB5_PERIPHEN_M7_GPIOJ, ENABLE);
#if defined(SOC_N32H78X)
RCC_EnableAHB5PeriphClk2(RCC_AHB5_PERIPHEN_M4_GPIOJ, ENABLE);
#endif /* SOC_N32H78X */
#endif
#endif /* GPIOJ */
#if defined(GPIOK)
#ifdef GPIOK
#if defined(SOC_SERIES_N32H7xx)
RCC_EnableAHB5PeriphClk2(RCC_AHB5_PERIPHEN_M7_GPIOK, ENABLE);
#if defined(SOC_N32H78X)
RCC_EnableAHB5PeriphClk2(RCC_AHB5_PERIPHEN_M4_GPIOK, ENABLE);
#endif /* SOC_N32H78X */
#endif
#endif /* defined(SOC_SERIES_N32H7xx) */
#endif /* GPIOK */
return rt_device_pin_register("pin", &_n32_pin_ops, RT_NULL);
}

4
bsp/n32/n32hxxx/libraries/N32_Drivers/drivers/drv_hard_i2c.c
View File

@ -262,8 +262,8 @@ static rt_err_t n32_i2c_init(struct n32_i2c *i2c_drv)
I2C_Configuration();
/* Disable IIC */
I2C_Enable(cfg->Instance, DISABLE);
/* Get IIC BUSTIM Register value */
BusTim_Reg = cfg->Instance->BUSTIM;
/* Get IIC BUSTM Register value */
BusTim_Reg = cfg->Instance->BUSTM;
if (BusTim_Reg == 0U)
{

8
bsp/n32/n32hxxx/libraries/N32_Drivers/drivers/drv_log.h
View File

@ -13,15 +13,15 @@
*/
#ifndef LOG_TAG
#define DBG_TAG "drv"
#define DBG_TAG "drv"
#else
#define DBG_TAG LOG_TAG
#define DBG_TAG LOG_TAG
#endif /* LOG_TAG */
#ifdef DRV_DEBUG
#define DBG_LVL DBG_LOG
#define DBG_LVL DBG_LOG
#else
#define DBG_LVL DBG_INFO
#define DBG_LVL DBG_INFO
#endif /* DRV_DEBUG */
#include <rtdbg.h>

512
bsp/n32/n32hxxx/libraries/N32_Drivers/drivers/drv_lptim.c Normal file
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@ -0,0 +1,512 @@
/*
* Copyright (c) 2006-2025 RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2026-06-23 ox-horse first version
*/
#include <board.h>
#include <drv_lptim.h>
#include <rtdevice.h>
#include "drv_config.h"
#include "n32h7xx_exti.h"
/*#define DRV_DEBUG*/
#define LOG_TAG "drv.lptim"
#include <drv_log.h>
#ifdef BSP_USING_LPTIM
#define LPTIM_REG_MAX_VALUE (0xFFFF)
enum
{
#ifdef BSP_USING_LPTIM1
LPTIM1_INDEX,
#endif
#ifdef BSP_USING_LPTIM2
LPTIM2_INDEX,
#endif
#ifdef BSP_USING_LPTIM3
LPTIM3_INDEX,
#endif
#ifdef BSP_USING_LPTIM4
LPTIM4_INDEX,
#endif
#ifdef BSP_USING_LPTIM5
LPTIM5_INDEX,
#endif
};
struct n32_hw_lptimer
{
rt_clock_timer_t time_device;
LPTIM_Module *timer;
IRQn_Type tim_irqn;
char *name;
};
static struct n32_hw_lptimer n32_hw_lptimer_obj[] = {
#ifdef BSP_USING_LPTIM1
LPTIM1_CONFIG,
#endif
#ifdef BSP_USING_LPTIM2
LPTIM2_CONFIG,
#endif
#ifdef BSP_USING_LPTIM3
LPTIM3_CONFIG,
#endif
#ifdef BSP_USING_LPTIM4
LPTIM4_CONFIG,
#endif
#ifdef BSP_USING_LPTIM5
LPTIM5_CONFIG,
#endif
};
/**
* Configure LPTIM clock source to LSI.
* Each LPTIM has a 4-bit clock selection field in RCC_RDSEL1 at different bit positions.
* LPTIM1: bits [31:28], LPTIM2: bits [27:24], LPTIM3: bits [23:20],
* LPTIM4: bits [19:16], LPTIM5: bits [15:12].
* LSI value = 0x1 shifted to the field position.
*/
static void n32_lptim_clock_source_config(LPTIM_Module *timer)
{
if (timer == LPTIM1)
{
RCC_ConfigLPTIM1Clk(RCC_LPTIMCLK_SRC_LSI);
}
else if (timer == LPTIM2)
{
RCC_ConfigLPTIM2Clk(RCC_LPTIMCLK_SRC_LSI);
}
else if (timer == LPTIM3)
{
RCC_ConfigLPTIM3Clk(RCC_LPTIMCLK_SRC_LSI);
}
else if (timer == LPTIM4)
{
RCC_ConfigLPTIM4Clk(RCC_LPTIMCLK_SRC_LSI);
}
else if (timer == LPTIM5)
{
RCC_ConfigLPTIM5Clk(RCC_LPTIMCLK_SRC_LSI);
}
}
/**
* Enable RD (Retention Domain) peripheral clock for the given LPTIM.
*/
static void n32_lptim_enable_clock(LPTIM_Module *timer)
{
if (timer == LPTIM1)
{
RCC_EnableRDPeriphClk1(RCC_RD_PERIPHEN_M7_LPTIM1 | RCC_RD_PERIPHEN_M4_LPTIM1 |
RCC_RD_PERIPHEN_M7_LPTIM1LP | RCC_RD_PERIPHEN_M4_LPTIM1LP,
ENABLE);
}
else if (timer == LPTIM2)
{
RCC_EnableRDPeriphClk1(RCC_RD_PERIPHEN_M7_LPTIM2 | RCC_RD_PERIPHEN_M4_LPTIM2 |
RCC_RD_PERIPHEN_M7_LPTIM2LP | RCC_RD_PERIPHEN_M4_LPTIM2LP,
ENABLE);
}
else if (timer == LPTIM3)
{
RCC_EnableRDPeriphClk1(RCC_RD_PERIPHEN_M7_LPTIM3 | RCC_RD_PERIPHEN_M4_LPTIM3 |
RCC_RD_PERIPHEN_M7_LPTIM3LP | RCC_RD_PERIPHEN_M4_LPTIM3LP,
ENABLE);
}
else if (timer == LPTIM4)
{
RCC_EnableRDPeriphClk1(RCC_RD_PERIPHEN_M7_LPTIM4 | RCC_RD_PERIPHEN_M4_LPTIM4 |
RCC_RD_PERIPHEN_M7_LPTIM4LP | RCC_RD_PERIPHEN_M4_LPTIM4LP,
ENABLE);
}
else if (timer == LPTIM5)
{
RCC_EnableRDPeriphClk1(RCC_RD_PERIPHEN_M7_LPTIM5 | RCC_RD_PERIPHEN_M4_LPTIM5 |
RCC_RD_PERIPHEN_M7_LPTIM5LP | RCC_RD_PERIPHEN_M4_LPTIM5LP,
ENABLE);
}
}
/**
* Get EXTI line for the given LPTIM.
* LPTIM1 -> EXTI 66, LPTIM2 -> EXTI 67, LPTIM3 -> EXTI 68,
* LPTIM4 -> EXTI 69, LPTIM5 -> EXTI 86
*/
static uint32_t n32_lptim_get_exti_line(LPTIM_Module *timer)
{
if (timer == LPTIM1)
return EXTI_LINE66;
else if (timer == LPTIM2)
return EXTI_LINE67;
else if (timer == LPTIM3)
return EXTI_LINE68;
else if (timer == LPTIM4)
return EXTI_LINE69;
else if (timer == LPTIM5)
return EXTI_LINE86;
else
return 0;
}
/**
* Configure EXTI interrupt line for LPTIM wakeup.
*/
static void n32_lptim_exti_config(LPTIM_Module *timer)
{
uint32_t exti_line = n32_lptim_get_exti_line(timer);
if (exti_line == 0)
return;
EXTI_InitType EXTI_InitStructure;
EXTI_InitStruct(&EXTI_InitStructure);
EXTI_InitStructure.EXTI_Line = exti_line;
EXTI_InitStructure.EXTI_LineCmd = ENABLE;
EXTI_InitStructure.EXTI_Mode = EXTI_Mode_Interrupt;
EXTI_InitStructure.EXTI_Trigger = EXTI_Trigger_Rising;
EXTI_InitPeripheral(&EXTI_InitStructure);
}
/**
* Clear EXTI pending bit for LPTIM wakeup.
*/
static void n32_lptim_clear_exti_flag(LPTIM_Module *timer)
{
uint32_t exti_line = n32_lptim_get_exti_line(timer);
if (exti_line != 0)
{
EXTI_ClrITPendBit(exti_line);
}
}
static const struct rt_clock_timer_info _info = LPTIM_DEV_INFO_CONFIG;
static void timer_init(struct rt_clock_timer_device *timer, rt_uint32_t state)
{
if (timer == RT_NULL)
{
LOG_E("init timer is NULL");
return;
}
if (state)
{
struct n32_hw_lptimer *tim_device = rt_container_of(timer, struct n32_hw_lptimer, time_device);
LPTIM_Module *lptim = tim_device->timer;
if (tim_device == RT_NULL)
{
LOG_E("start tim_device is NULL");
return;
}
if (lptim == RT_NULL)
{
LOG_E("start %s LPTIM is NULL", tim_device->name);
return;
}
/* Enable LSI clock for LPTIM */
RCC_EnableLsi(ENABLE);
/* Wait for LSI ready */
while (RCC_GetFlagStatus(RCC_FLAG_LSIRD) == RESET)
;
/* Select LSI as LPTIM clock source */
n32_lptim_clock_source_config(lptim);
/* Enable LPTIM peripheral clock */
n32_lptim_enable_clock(lptim);
/* Configure LPTIM */
LPTIM_InitType lptim_init;
LPTIM_StructInit(&lptim_init);
lptim_init.ClockSource = LPTIM_CLK_SOURCE_INTERNAL;
lptim_init.Prescaler = LPTIM_PRESCALER_DIV32;
if (LPTIM_Init(lptim, &lptim_init) != SUCCESS)
{
LOG_E("%s init failed", tim_device->name);
return;
}
/* Set registers update mode to immediate (same as STM32 LPTIM_UPDATE_IMMEDIATE) */
LPTIM_SetUpdateMode(lptim, LPTIM_UPDATE_MODE_IMMEDIATE);
/* Enable EXTI clock and configure EXTI line for LPTIM wakeup interrupt */
RCC_EnableAPB5PeriphClk2(RCC_APB5_PERIPHEN_EXTI, ENABLE);
n32_lptim_exti_config(lptim);
/* Configure NVIC */
NVIC_ClearPendingIRQ(tim_device->tim_irqn);
NVIC_SetPriority(tim_device->tim_irqn, NVIC_EncodePriority(NVIC_GetPriorityGrouping(), 0, 0));
NVIC_EnableIRQ(tim_device->tim_irqn);
LOG_D("%s init success", tim_device->name);
}
}
static rt_err_t timer_start(rt_clock_timer_t *timer, rt_uint32_t t, rt_clock_timer_mode_t opmode)
{
if (timer == RT_NULL)
{
LOG_E("start timer is NULL");
return -RT_EINVAL;
}
struct n32_hw_lptimer *tim_device = rt_container_of(timer, struct n32_hw_lptimer, time_device);
LPTIM_Module *lptim = tim_device->timer;
if (tim_device == RT_NULL)
{
LOG_E("start tim_device is NULL");
return -RT_EINVAL;
}
if (lptim == RT_NULL)
{
LOG_E("start %s LPTIM is NULL", tim_device->name);
return -RT_EINVAL;
}
/* Enable timeout function */
LPTIM_TimeoutCmd(lptim, ENABLE);
/* Enable compare match interrupt */
LPTIM_ConfigInt(lptim, LPTIM_COMP_MATCH_INT, ENABLE);
/* Enable LPTIM peripheral */
LPTIM_Cmd(lptim, ENABLE);
/* Set the auto-reload and compare values */
LPTIM_SetAutoReloadValue(lptim, LPTIM_REG_MAX_VALUE);
LPTIM_SetCompareValue(lptim, t);
/* Start counter in specified mode */
if (opmode == CLOCK_TIMER_MODE_ONESHOT)
{
LPTIM_StartCounter(lptim, LPTIM_OPERATING_MODE_ONESHOT);
}
else
{
LPTIM_StartCounter(lptim, LPTIM_OPERATING_MODE_CONTINUOUS);
}
LOG_D("start %s success, timeout=%d", tim_device->name, t);
return RT_EOK;
}
static void timer_stop(rt_clock_timer_t *timer)
{
if (timer == RT_NULL)
{
LOG_E("stop timer is NULL");
return;
}
struct n32_hw_lptimer *tim_device = rt_container_of(timer, struct n32_hw_lptimer, time_device);
LPTIM_Module *lptim = tim_device->timer;
if (tim_device == RT_NULL)
{
LOG_E("stop tim_device is NULL");
return;
}
if (lptim == RT_NULL)
{
LOG_E("stop %s LPTIM is NULL", tim_device->name);
return;
}
/* Disable timeout function and interrupt */
LPTIM_TimeoutCmd(lptim, DISABLE);
LPTIM_ConfigInt(lptim, LPTIM_COMP_MATCH_INT, DISABLE);
/* Disable LPTIM peripheral */
LPTIM_Cmd(lptim, DISABLE);
LOG_D("stop %s success", tim_device->name);
}
static rt_uint32_t timer_get_freq(LPTIM_Module *lptim)
{
/* Default configuration: LSI (32768 Hz) / DIV32 = 1024 Hz */
(void)lptim;
return 1024;
}
static rt_uint32_t timer_counter_get(rt_clock_timer_t *timer)
{
struct n32_hw_lptimer *tim_device = rt_container_of(timer, struct n32_hw_lptimer, time_device);
return LPTIM_GetCounterValue(tim_device->timer);
}
static rt_err_t timer_ctrl(rt_clock_timer_t *timer, rt_uint32_t cmd, void *arg)
{
if (timer == RT_NULL)
{
LOG_E("ctrl timer is NULL");
return -RT_EINVAL;
}
struct n32_hw_lptimer *tim_device = rt_container_of(timer, struct n32_hw_lptimer, time_device);
LPTIM_Module *lptim = tim_device->timer;
if (tim_device == RT_NULL)
{
LOG_E("ctrl tim_device is NULL");
return -RT_EINVAL;
}
if (lptim == RT_NULL)
{
LOG_E("ctrl %s LPTIM is NULL", tim_device->name);
return -RT_EINVAL;
}
rt_err_t result = RT_EOK;
switch (cmd)
{
case DRV_HW_LPTIMER_CTRL_GET_TICK_MAX:
{
*(rt_uint32_t *)arg = LPTIM_REG_MAX_VALUE;
break;
}
case DRV_HW_LPTIMER_CTRL_GET_FREQ:
{
*(rt_uint32_t *)arg = timer_get_freq(lptim);
break;
}
case DRV_HW_LPTIMER_CTRL_START:
{
result = timer_start(timer, *(rt_uint32_t *)arg, CLOCK_TIMER_MODE_ONESHOT);
break;
}
case DRV_HW_LPTIMER_CTRL_GET_COUNT:
{
*(rt_uint32_t *)arg = timer_counter_get(timer);
break;
}
default:
{
result = -RT_ENOSYS;
}
break;
}
return result;
}
/* IRQ Handlers for each LPTIM instance */
#ifdef BSP_USING_LPTIM1
void LPTIM1_WKUP_IRQHandler(void)
{
rt_interrupt_enter();
if (LPTIM_IsActiveIntStatus(n32_hw_lptimer_obj[LPTIM1_INDEX].timer, LPTIM_COMP_MATCH_STATUS))
{
LPTIM_ClearIntFlag(n32_hw_lptimer_obj[LPTIM1_INDEX].timer, LPTIM_COMP_MATCH_FLAG);
n32_lptim_clear_exti_flag(n32_hw_lptimer_obj[LPTIM1_INDEX].timer);
rt_clock_timer_isr(&n32_hw_lptimer_obj[LPTIM1_INDEX].time_device);
}
rt_interrupt_leave();
}
#endif
#ifdef BSP_USING_LPTIM2
void LPTIM2_WKUP_IRQHandler(void)
{
rt_interrupt_enter();
if (LPTIM_IsActiveIntStatus(n32_hw_lptimer_obj[LPTIM2_INDEX].timer, LPTIM_COMP_MATCH_STATUS))
{
LPTIM_ClearIntFlag(n32_hw_lptimer_obj[LPTIM2_INDEX].timer, LPTIM_COMP_MATCH_FLAG);
n32_lptim_clear_exti_flag(n32_hw_lptimer_obj[LPTIM2_INDEX].timer);
rt_clock_timer_isr(&n32_hw_lptimer_obj[LPTIM2_INDEX].time_device);
}
rt_interrupt_leave();
}
#endif
#ifdef BSP_USING_LPTIM3
void LPTIM3_WKUP_IRQHandler(void)
{
rt_interrupt_enter();
if (LPTIM_IsActiveIntStatus(n32_hw_lptimer_obj[LPTIM3_INDEX].timer, LPTIM_COMP_MATCH_STATUS))
{
LPTIM_ClearIntFlag(n32_hw_lptimer_obj[LPTIM3_INDEX].timer, LPTIM_COMP_MATCH_FLAG);
n32_lptim_clear_exti_flag(n32_hw_lptimer_obj[LPTIM3_INDEX].timer);
rt_clock_timer_isr(&n32_hw_lptimer_obj[LPTIM3_INDEX].time_device);
}
rt_interrupt_leave();
}
#endif
#ifdef BSP_USING_LPTIM4
void LPTIM4_WKUP_IRQHandler(void)
{
rt_interrupt_enter();
if (LPTIM_IsActiveIntStatus(n32_hw_lptimer_obj[LPTIM4_INDEX].timer, LPTIM_COMP_MATCH_STATUS))
{
LPTIM_ClearIntFlag(n32_hw_lptimer_obj[LPTIM4_INDEX].timer, LPTIM_COMP_MATCH_FLAG);
n32_lptim_clear_exti_flag(n32_hw_lptimer_obj[LPTIM4_INDEX].timer);
rt_clock_timer_isr(&n32_hw_lptimer_obj[LPTIM4_INDEX].time_device);
}
rt_interrupt_leave();
}
#endif
#ifdef BSP_USING_LPTIM5
void LPTIM5_WKUP_IRQHandler(void)
{
rt_interrupt_enter();
if (LPTIM_IsActiveIntStatus(n32_hw_lptimer_obj[LPTIM5_INDEX].timer, LPTIM_COMP_MATCH_STATUS))
{
LPTIM_ClearIntFlag(n32_hw_lptimer_obj[LPTIM5_INDEX].timer, LPTIM_COMP_MATCH_FLAG);
n32_lptim_clear_exti_flag(n32_hw_lptimer_obj[LPTIM5_INDEX].timer);
rt_clock_timer_isr(&n32_hw_lptimer_obj[LPTIM5_INDEX].time_device);
}
rt_interrupt_leave();
}
#endif
static const struct rt_clock_timer_ops _ops = {
.init = timer_init,
.start = timer_start,
.stop = timer_stop,
.count_get = timer_counter_get,
.control = timer_ctrl,
};
/**
* Register all enabled LPTIM instances as rt_clock_timer devices.
*/
static int n32_hw_lptim_init(void)
{
int i = 0;
int result = RT_EOK;
for (i = 0; i < sizeof(n32_hw_lptimer_obj) / sizeof(n32_hw_lptimer_obj[0]); i++)
{
n32_hw_lptimer_obj[i].time_device.info = &_info;
n32_hw_lptimer_obj[i].time_device.ops = &_ops;
if (rt_clock_timer_register(&n32_hw_lptimer_obj[i].time_device,
n32_hw_lptimer_obj[i].name, &n32_hw_lptimer_obj[i].timer) == RT_EOK)
{
LOG_D("%s register success", n32_hw_lptimer_obj[i].name);
}
else
{
LOG_E("%s register failed", n32_hw_lptimer_obj[i].name);
result = -RT_ERROR;
}
}
return result;
}
INIT_BOARD_EXPORT(n32_hw_lptim_init);
#endif /* BSP_USING_LPTIM */

25
bsp/n32/n32hxxx/libraries/N32_Drivers/drivers/drv_lptim.h Normal file
View File

@ -0,0 +1,25 @@
/*
* Copyright (c) 2006-2025 RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2026-06-23 ox-horse first version
*/
#ifndef __DRV_LPTIM_H__
#define __DRV_LPTIM_H__
#include <rtthread.h>
/* 0x20 - 0x3F udevice control commands */
typedef enum
{
DRV_HW_LPTIMER_CTRL_GET_TICK_MAX = 0x20, /* get the maximum tick value */
DRV_HW_LPTIMER_CTRL_GET_FREQ = 0X21, /* get the timer frequency */
DRV_HW_LPTIMER_CTRL_START = 0X22, /* set the timeout value */
DRV_HW_LPTIMER_CTRL_GET_COUNT = 0X23, /* get the current count value */
} drv_hw_lptimer_ctrl_t;
#endif /* __DRV_LPTIM_H__ */

589
bsp/n32/n32hxxx/libraries/N32_Drivers/drivers/drv_nand.c Normal file
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@ -0,0 +1,589 @@
/*
* Copyright (c) 2006-2026, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2026-07-10 ox-horse first version
*/
#include <rtconfig.h>
#ifdef BSP_USING_NAND
#include "femc_timing.h"
//#define DRV_DEBUG
#define LOG_TAG "drv.nand"
#include <drv_log.h>
#include <rtdevice.h>
#include <drivers/mtd_nand.h>
#if defined(SOC_SERIES_N32H7xx)
static FEMC_InitType NAND_InitStructure = { 0 };
/* NAND chip select and bank address derived from Kconfig */
#ifdef BSP_USING_NAND_BANK1
#define NAND_CHIP NAND_CHIP_1
#define NAND_BANK_ADDR ((uint32_t)0xA0000000)
#endif
#ifdef BSP_USING_NAND_BANK2
#define NAND_CHIP NAND_CHIP_2
#define NAND_BANK_ADDR ((uint32_t)0xB0000000)
#endif
#endif
static struct rt_mtd_nand_device _nand_dev;
/*
* FEMC AXI address layout for NAND access:
*
* [31:24] Chip select address
* [23:21] Number of address cycles (0..7)
* [20] End command valid
* [19] 0 = command phase, 1 = data phase
* [18:11] End command
* [10:3] Start command
* [2:0] Byte lane strobes (AXI standard)
*/
#define NAND_CMD_AREA ((uint32_t)0x00000000) /* bit19 = 0 */
#define NAND_DATA_AREA ((uint32_t)0x00080000) /* bit19 = 1 */
/*
* Address cycle count auto-derived from Kconfig NAND chip parameters.
*
* Total pages = pages_per_block * block_count.
* row_bits = ceil(log2(total_pages)), row_cycles = ceil(row_bits / 8).
*
* total_pages <= 65536 → 16-bit row, 2 row cycles
* total_pages <= 16777216 → 24-bit row, 3 row cycles
* total_pages > 16777216 → 32-bit row, 4 row cycles
*
* Read/Write: 2 column address cycles + row address cycles.
* Erase: row address cycles only (no column address).
* READ_ID: fixed at 1 address cycle per NAND standard.
*/
#define NAND_TOTAL_PAGES (BSP_NAND_PAGES_PER_BLOCK * BSP_NAND_BLOCK_COUNT)
#if NAND_TOTAL_PAGES <= 65536
#define NAND_ROW_ADDR_CYCLES 2
#elif NAND_TOTAL_PAGES <= 16777216
#define NAND_ROW_ADDR_CYCLES 3
#else
#define NAND_ROW_ADDR_CYCLES 4
#endif
#define NAND_RW_ADDR_CYCLES (2 + NAND_ROW_ADDR_CYCLES)
#define NAND_ERASE_ADDR_CYCLES NAND_ROW_ADDR_CYCLES
/* Encode cycle count into AXI address bits [23:21] */
#define NAND_ADDR_CYCLES(n) ((uint32_t)(n) << 21)
#define NAND_CMD_END_ENABLE ((uint32_t)0x00100000)
#define NAND_CMD_END_DISABLE ((uint32_t)0x00000000)
#define NAND_CLEAR_CS_ENABLE ((uint32_t)0x00200000)
#define NAND_CLEAR_CS_DISABLE ((uint32_t)0x00000000)
#define NAND_ECC_LAST_ENABLE ((uint32_t)0x00000400)
#define NAND_ECC_LAST_DISABLE ((uint32_t)0x00000000)
/* Standard NAND flash commands */
#define NAND_CMD_READ_1ST ((uint8_t)0x00)
#define NAND_CMD_READ_2ND ((uint8_t)0x30)
#define NAND_CMD_WRITE_1ST ((uint8_t)0x80)
#define NAND_CMD_WRITE_2ND ((uint8_t)0x10)
#define NAND_CMD_ERASE_1ST ((uint8_t)0x60)
#define NAND_CMD_ERASE_2ND ((uint8_t)0xD0)
#define NAND_CMD_READ_ID ((uint8_t)0x90)
#define NAND_CMD_STATUS ((uint8_t)0x70)
#define NAND_CMD_RESET ((uint8_t)0xFF)
/* NAND status bits */
#define NAND_STATUS_READY ((uint32_t)0x40)
#define NAND_STATUS_ERROR ((uint32_t)0x01)
/*
* FEMC uses Hamming code with 1-bit correction / 2-bit detection.
* Each 512-byte frame generates a 24-bit (3-byte) ECC value stored
* in the spare area.
*
* ECC bytes per page = (page_size / 512) * 3
*
* Example: page_size = 2048 -> ECC = 2048/512 * 3 = 12 bytes
* oob_size = 64 -> oob_free = 64 - 12 = 52 bytes
*/
#define NAND_ECC_SECTOR_SIZE 512
#define NAND_ECC_BYTES_PER_SECTOR 3
#define ECC_BYTES(page_size) ((page_size) / NAND_ECC_SECTOR_SIZE * NAND_ECC_BYTES_PER_SECTOR)
#define OOB_FREE(page, oob) ((oob) - ECC_BYTES(page))
static rt_err_t rt_nand_init(void)
{
#if defined(SOC_SERIES_N32H7xx)
/* FEMC Operating Mode for NAND Devices */
AFIO_ConfigFEMCNANDSRAM(FEMC_NAND_SEL);
FEMC_InitStruct(&NAND_InitStructure);
#ifdef BSP_USING_NAND_BUS_WIDTH_8B
NAND_InitStructure.ChipCfg.MemWidth = FEMC_MEMORY_WIDTH_8BIT;
#endif /* BSP_USING_NAND_BUS_WIDTH_8B */
#ifdef BSP_USING_NAND_BUS_WIDTH_16B
NAND_InitStructure.ChipCfg.MemWidth = FEMC_MEMORY_WIDTH_16BIT;
#endif /* BSP_USING_NAND_BUS_WIDTH_16B */
/* FEMC Nand Timing Configuration */
FEMC_Nnad_Timing_Config(&NAND_InitStructure.TimingCfg);
FEMC_Init(&NAND_InitStructure);
FEMC_SetCommand(NAND_CHIP, FEMC_CMD_UPDATEREGS, FEMC_CRE_POLARITY_LOW, 0);
if (FEMC_CheckChipStatus(NAND_CHIP, &NAND_InitStructure.ChipCfg) != SUCCESS)
{
LOG_E("femc nand initialization chip mode parameter check error!");
return -RT_ERROR;
}
if (FEMC_CheckTimingStatus(NAND_CHIP, &NAND_InitStructure.TimingCfg) != SUCCESS)
{
LOG_E("femc nand initialization timing parameter check error!");
return -RT_ERROR;
}
/* Reset NAND chip */
{
uint32_t reset_cmd;
reset_cmd = NAND_BANK_ADDR | NAND_ADDR_CYCLES(0) | NAND_CMD_END_DISABLE | NAND_CMD_AREA | (NAND_CMD_RESET << 3);
*((__IO uint16_t *)reset_cmd) = 0x0000;
}
#endif
return RT_EOK;
}
/*
* Wait for NAND operation to complete via FEMC busy flag.
*
* The FEMC_NAND_FLAG is set by hardware when the NAND R/B signal goes high
* (all NAND chips in the wired-AND busy line are ready).
*
* Uses rt_thread_delay() between polls to yield to the scheduler instead
* of a tight while-loop, preventing other threads from being starved.
*/
static rt_err_t nand_wait_busy(void)
{
rt_uint32_t timeout = 0x100000;
while (FEMC_GetFlag(FEMC_NAND_FLAG) != SET)
{
if (--timeout == 0)
{
return -RT_ETIMEOUT;
}
rt_thread_delay(rt_tick_from_millisecond(1));
}
FEMC_ClrFlag(FEMC_NAND_FLAG_CLEAR);
return RT_EOK;
}
/*
* Poll NAND status register until ready or timeout.
*
* Re-issues READ STATUS (0x70) on each poll iteration for maximum
* compatibility with different NAND chips (some chips require the
* command to be re-sent before each status read).
*
* Returns -RT_EIO if the error bit is set, -RT_ETIMEOUT on timeout.
*/
static rt_err_t nand_check_status(uint32_t bank_addr)
{
uint32_t timeout = 0x100000;
uint32_t cmd, stat_addr;
uint8_t status;
cmd = bank_addr | NAND_ADDR_CYCLES(0) | NAND_CMD_END_DISABLE | NAND_CMD_AREA | (NAND_CMD_STATUS << 3);
stat_addr = bank_addr | NAND_CLEAR_CS_ENABLE | NAND_CMD_END_DISABLE | NAND_DATA_AREA | NAND_ECC_LAST_DISABLE;
do
{
*((__IO uint8_t *)cmd) = 0x00;
status = *(__IO uint8_t *)(stat_addr);
if (status & NAND_STATUS_ERROR)
{
return -RT_EIO;
}
if (status & NAND_STATUS_READY)
{
return RT_EOK;
}
timeout--;
rt_thread_delay(rt_tick_from_millisecond(1));
} while (timeout);
return -RT_ETIMEOUT;
}
/*
* ===========================================================================
* MTD NAND Driver Operations
* ===========================================================================
*/
/*
* Read NAND flash ID.
* SDK reads 5 bytes, but rt_mtd_nand_read_id() returns only 32 bits.
* Pack bytes 1-4 (Device + 3rd + 4th + 5th), discard byte 0 (Maker ID).
* This matches the stm32mp1 convention in the RT-Thread codebase.
*/
static rt_err_t _read_id(struct rt_mtd_nand_device *device)
{
uint32_t cmd_addr, data_addr;
uint8_t id_bytes[5];
rt_uint32_t id;
cmd_addr = NAND_BANK_ADDR | NAND_ADDR_CYCLES(1) | NAND_CMD_END_DISABLE | NAND_CMD_AREA | (NAND_CMD_READ_ID << 3);
data_addr = NAND_BANK_ADDR | NAND_CLEAR_CS_DISABLE | NAND_CMD_END_DISABLE | NAND_DATA_AREA | NAND_ECC_LAST_DISABLE;
*((__IO uint8_t *)cmd_addr) = 0x00;
/* Read all 5 ID bytes */
for (uint8_t i = 0; i < 5; i++)
{
id_bytes[i] = *((__IO uint8_t *)data_addr);
}
LOG_D("NAND ID: %02X %02X %02X %02X %02X",
id_bytes[0], id_bytes[1], id_bytes[2], id_bytes[3], id_bytes[4]);
/* Pack bytes 1-4 into 32-bit return value (byte 0 = Maker ID, discarded) */
id = (rt_uint32_t)id_bytes[1] << 24;
id |= (rt_uint32_t)id_bytes[2] << 16;
id |= (rt_uint32_t)id_bytes[3] << 8;
id |= (rt_uint32_t)id_bytes[4];
return (rt_err_t)id;
}
/* read one page (data + spare) */
static rt_err_t _read_page(struct rt_mtd_nand_device *device,
rt_off_t page,
rt_uint8_t *data, rt_uint32_t data_len,
rt_uint8_t *spare, rt_uint32_t spare_len)
{
uint32_t cmd_addr, data_addr;
uint32_t row_addr, i;
row_addr = (uint32_t)page;
/* Clear any stale R/B flag before issuing the command */
FEMC_ClrFlag(FEMC_NAND_FLAG_CLEAR);
/* Command phase: READ_1ST + row address + READ_2ND */
cmd_addr = NAND_BANK_ADDR | NAND_ADDR_CYCLES(NAND_RW_ADDR_CYCLES) | NAND_CMD_END_ENABLE | NAND_CMD_AREA | (NAND_CMD_READ_2ND << 11) | (NAND_CMD_READ_1ST << 3);
*((__IO uint32_t *)cmd_addr) = row_addr << 16;
rt_err_t ret;
/* Wait for NAND to load the page into internal buffer */
ret = nand_wait_busy();
if (ret != RT_EOK)
{
LOG_E("read page %d busy timeout", (int)page);
return ret;
}
/*
* Data phase: 32-bit AXI access for efficiency, 8-bit for remainder.
*
* The AXI access width is independent of the NAND bus width —
* FEMC hardware handles the packing/unpacking transparently.
* Using 32-bit access reduces the number of AXI transactions by 4x
* compared to 8-bit, improving throughput on both 8-bit and 16-bit NAND.
*/
if (data && data_len)
{
uint32_t *p32;
uint32_t word_cnt;
data_addr = NAND_BANK_ADDR | NAND_CLEAR_CS_DISABLE | NAND_CMD_END_DISABLE | NAND_DATA_AREA | NAND_ECC_LAST_DISABLE;
/* 32-bit aligned bulk */
word_cnt = data_len / 4;
p32 = (uint32_t *)data;
for (i = 0; i < word_cnt; i++)
{
p32[i] = *((__IO uint32_t *)data_addr);
}
/* 8-bit remainder */
for (i = word_cnt * 4; i < data_len; i++)
{
data[i] = *((__IO uint8_t *)data_addr);
}
}
/* spare area read not implemented yet */
ret = nand_check_status(NAND_BANK_ADDR);
if (ret != RT_EOK)
{
LOG_E("read page %d status error %d", (int)page, ret);
}
return ret;
}
/* write one page (data + spare) */
static rt_err_t _write_page(struct rt_mtd_nand_device *device,
rt_off_t page,
const rt_uint8_t *data, rt_uint32_t data_len,
const rt_uint8_t *spare, rt_uint32_t spare_len)
{
uint32_t cmd_addr, data_addr;
uint32_t row_addr, i;
row_addr = (uint32_t)page;
/* Clear any stale R/B flag before issuing the command */
FEMC_ClrFlag(FEMC_NAND_FLAG_CLEAR);
/* Command phase: WRITE_1ST + row address */
cmd_addr = NAND_BANK_ADDR | NAND_ADDR_CYCLES(NAND_RW_ADDR_CYCLES) | NAND_CMD_END_DISABLE | NAND_CMD_AREA | (NAND_CMD_WRITE_1ST << 3);
*((__IO uint32_t *)cmd_addr) = row_addr << 16;
/*
* Data phase: 32-bit AXI access for efficiency, 8-bit for remainder.
* See _read_page for rationale.
*/
if (data && data_len)
{
uint32_t addr_no_end, addr_end;
uint32_t word_cnt, remain_start;
addr_no_end = NAND_BANK_ADDR | NAND_CLEAR_CS_DISABLE | NAND_CMD_END_DISABLE | NAND_DATA_AREA | (NAND_CMD_WRITE_2ND << 11) | NAND_ECC_LAST_DISABLE;
addr_end = NAND_BANK_ADDR | NAND_CLEAR_CS_ENABLE | NAND_CMD_END_ENABLE | NAND_DATA_AREA | (NAND_CMD_WRITE_2ND << 11) | NAND_ECC_LAST_DISABLE;
word_cnt = data_len / 4;
remain_start = word_cnt * 4;
/*
* 32-bit writes:
* - If no remainder, the last 32-bit word IS the last write overall → addr_end.
* - If there is a remainder, all 32-bit words are NOT the last → addr_no_end.
*/
if (remain_start == data_len)
{
/* No remainder: bulk - 1 with no_end, last word with end */
for (i = 0; i < word_cnt - 1; i++)
{
*((__IO uint32_t *)addr_no_end) = ((const uint32_t *)data)[i];
}
*((__IO uint32_t *)addr_end) = ((const uint32_t *)data)[word_cnt - 1];
}
else
{
/* Has remainder: all words with no_end */
for (i = 0; i < word_cnt; i++)
{
*((__IO uint32_t *)addr_no_end) = ((const uint32_t *)data)[i];
}
}
/*
* 8-bit remainder: last byte uses addr_end, preceding bytes use addr_no_end.
*/
for (i = remain_start; i + 1 < data_len; i++)
{
*((__IO uint8_t *)addr_no_end) = data[i];
}
if (remain_start < data_len)
{
*((__IO uint8_t *)addr_end) = data[data_len - 1];
}
}
else
{
data_addr = NAND_BANK_ADDR | NAND_CLEAR_CS_ENABLE | NAND_CMD_END_ENABLE | NAND_DATA_AREA | (NAND_CMD_WRITE_2ND << 11) | NAND_ECC_LAST_DISABLE;
*((__IO uint8_t *)data_addr) = 0x00;
}
/* spare area write not implemented yet */
rt_err_t ret;
/* Wait for program completion, then check status */
ret = nand_wait_busy();
if (ret != RT_EOK)
{
LOG_E("write page %d busy timeout", (int)page);
return ret;
}
ret = nand_check_status(NAND_BANK_ADDR);
if (ret != RT_EOK)
{
LOG_E("write page %d status error %d", (int)page, ret);
}
return ret;
}
/* move page (for garbage collection) */
static rt_err_t _move_page(struct rt_mtd_nand_device *device,
rt_off_t src_page, rt_off_t dst_page)
{
uint8_t *buf;
rt_err_t result;
buf = rt_malloc(device->page_size);
if (!buf)
{
return -RT_ENOMEM;
}
/* Read source page (main data only, spare not handled yet) */
result = _read_page(device, src_page, buf, device->page_size, RT_NULL, 0);
if (result != RT_EOK)
{
rt_free(buf);
return result;
}
/* Write to destination page */
result = _write_page(device, dst_page, buf, device->page_size, RT_NULL, 0);
rt_free(buf);
return result;
}
/* erase one block */
static rt_err_t _erase_block(struct rt_mtd_nand_device *device, rt_uint32_t block)
{
uint32_t cmd_addr;
uint32_t row_addr;
/*
* Convert block number to row address.
* The erase command only needs the block address (row address with
* page bits zeroed). The FEMC uses 2 address cycles for erase.
*/
row_addr = block * device->pages_per_block;
/* Clear any stale R/B flag before issuing the command */
FEMC_ClrFlag(FEMC_NAND_FLAG_CLEAR);
/* Command phase: ERASE_1ST (2 addr cycles) + ERASE_2ND */
cmd_addr = NAND_BANK_ADDR | NAND_ADDR_CYCLES(NAND_ERASE_ADDR_CYCLES) | NAND_CMD_END_ENABLE | NAND_CMD_AREA | (NAND_CMD_ERASE_2ND << 11) | (NAND_CMD_ERASE_1ST << 3);
/*
* Erase uses only row address cycles (no column address).
* FEMC consumes data bytes from LSB upward per address cycle,
* so row_addr goes into bits [15:0] without shifting.
* (Read/Write uses << 16 to put column=0 in [15:0] and row in [31:16].)
*/
*((__IO uint32_t *)cmd_addr) = row_addr;
rt_err_t ret;
/* Wait for erase completion, then check status */
ret = nand_wait_busy();
if (ret != RT_EOK)
{
LOG_E("erase block %d busy timeout", (int)block);
return ret;
}
ret = nand_check_status(NAND_BANK_ADDR);
if (ret != RT_EOK)
{
LOG_E("erase block %d status error %d", (int)block, ret);
}
return ret;
}
/*
* Check if a block is bad.
*
* Requires reading spare area (bad block marker at first byte of spare
* area of the first page). Spare area read is not yet implemented.
*/
static rt_err_t _check_block(struct rt_mtd_nand_device *device, rt_uint32_t block)
{
return -RT_ENOSYS;
}
/*
* Mark a block as bad.
*
* Requires writing spare area (bad block marker at first byte of spare
* area of the first page). Spare area write is not yet implemented.
*/
static rt_err_t _mark_badblock(struct rt_mtd_nand_device *device, rt_uint32_t block)
{
return -RT_ENOSYS;
}
static const struct rt_mtd_nand_driver_ops _nand_ops = {
_read_id,
_read_page,
_write_page,
_move_page,
_erase_block,
_check_block,
_mark_badblock,
};
int rt_hw_nand_init(void)
{
rt_err_t result;
/* Initialize FEMC hardware */
result = rt_nand_init();
if (result != RT_EOK)
{
return result;
}
_nand_dev.page_size = BSP_NAND_PAGE_SIZE;
_nand_dev.oob_size = BSP_NAND_OOB_SIZE;
/*
* oob_free: bytes in the spare area available for the upper layer.
*
* FEMC ECC (Hamming code, 1-bit correction / 2-bit detection) generates
* a 24-bit (3-byte) ECC value per 512-byte sector. See FEMC.md section 8.7.
*
* ecc_bytes = page_size / 512 * 3
* oob_free = oob_size - ecc_bytes
*
* The remaining oob_free bytes are available for bad block markers,
* wear-leveling metadata, and filesystem bookkeeping.
*/
_nand_dev.oob_free = OOB_FREE(BSP_NAND_PAGE_SIZE, BSP_NAND_OOB_SIZE);
_nand_dev.pages_per_block = BSP_NAND_PAGES_PER_BLOCK;
_nand_dev.plane_num = BSP_NAND_PLANE_NUM;
_nand_dev.block_start = 0;
_nand_dev.block_end = BSP_NAND_BLOCK_COUNT;
_nand_dev.block_total = _nand_dev.block_end - _nand_dev.block_start;
_nand_dev.ops = &_nand_ops;
_nand_dev.priv = RT_NULL;
result = rt_mtd_nand_register_device("nand0", &_nand_dev);
if (result != RT_EOK)
{
rt_device_unregister(&_nand_dev.parent);
return result;
}
return RT_EOK;
}
INIT_DEVICE_EXPORT(rt_hw_nand_init);
#endif /* BSP_USING_NAND */

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/*
* Copyright (c) 2006-2025, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2026-06-23 ox-horse first version
*/
#include <board.h>
#include "drv_config.h"
#ifdef RT_USING_PULSE_ENCODER
#include "drv_tim.h"
//#define DRV_DEBUG
#define LOG_TAG "drv.pulse_encoder"
#include <drv_log.h>
/* NOTE: A timer instance must NOT be enabled for both clock-timer (BSP_USING_ATIMx/GTIMx/BTIMx)
* and pulse-encoder (BSP_USING_PULSE_ENCODERx) simultaneously. The Kconfig should enforce
* mutual exclusivity, otherwise ISR symbol conflicts will occur at link time.
*/
#if !defined(BSP_USING_PULSE_ENCODER1) && !defined(BSP_USING_PULSE_ENCODER2) && !defined(BSP_USING_PULSE_ENCODER3) && !defined(BSP_USING_PULSE_ENCODER4) && !defined(BSP_USING_PULSE_ENCODER5) && !defined(BSP_USING_PULSE_ENCODER6) && !defined(BSP_USING_PULSE_ENCODER7) && !defined(BSP_USING_PULSE_ENCODER8) && !defined(BSP_USING_PULSE_ENCODER9) && !defined(BSP_USING_PULSE_ENCODER10) && !defined(BSP_USING_PULSE_ENCODER11) && !defined(BSP_USING_PULSE_ENCODER12) && !defined(BSP_USING_PULSE_ENCODER13) && !defined(BSP_USING_PULSE_ENCODER14)
#error "Please define at least one BSP_USING_PULSE_ENCODERx"
#endif
/* Auto-reload value for encoder mode. Using half of the 16-bit range
* allows for overflow tracking in both directions. */
#define AUTO_RELOAD_VALUE 0x7FFF
/*
* N32H7xx pulse encoder device mapping:
* ATIM1-4 -> pulse_encoder1-4 (advanced, with encoder support)
* GTIMA1-7 -> pulse_encoder5-11 (general purpose, A bus)
* GTIMB1-3 -> pulse_encoder12-14 (general purpose, B bus)
*
* BTIM1-4 (basic timers) do NOT support encoder mode.
*/
enum
{
#ifdef BSP_USING_PULSE_ENCODER1
PULSE_ENCODER1_INDEX,
#endif
#ifdef BSP_USING_PULSE_ENCODER2
PULSE_ENCODER2_INDEX,
#endif
#ifdef BSP_USING_PULSE_ENCODER3
PULSE_ENCODER3_INDEX,
#endif
#ifdef BSP_USING_PULSE_ENCODER4
PULSE_ENCODER4_INDEX,
#endif
#ifdef BSP_USING_PULSE_ENCODER5
PULSE_ENCODER5_INDEX,
#endif
#ifdef BSP_USING_PULSE_ENCODER6
PULSE_ENCODER6_INDEX,
#endif
#ifdef BSP_USING_PULSE_ENCODER7
PULSE_ENCODER7_INDEX,
#endif
#ifdef BSP_USING_PULSE_ENCODER8
PULSE_ENCODER8_INDEX,
#endif
#ifdef BSP_USING_PULSE_ENCODER9
PULSE_ENCODER9_INDEX,
#endif
#ifdef BSP_USING_PULSE_ENCODER10
PULSE_ENCODER10_INDEX,
#endif
#ifdef BSP_USING_PULSE_ENCODER11
PULSE_ENCODER11_INDEX,
#endif
#ifdef BSP_USING_PULSE_ENCODER12
PULSE_ENCODER12_INDEX,
#endif
#ifdef BSP_USING_PULSE_ENCODER13
PULSE_ENCODER13_INDEX,
#endif
#ifdef BSP_USING_PULSE_ENCODER14
PULSE_ENCODER14_INDEX,
#endif
};
struct n32_pulse_encoder_device
{
struct rt_pulse_encoder_device pulse_encoder;
TIM_Module *timer;
IRQn_Type tim_irqn;
rt_int32_t over_under_flowcount;
char *name;
};
static struct n32_pulse_encoder_device n32_pulse_encoder_obj[] = {
#ifdef BSP_USING_PULSE_ENCODER1
PULSE_ENCODER1_CONFIG,
#endif
#ifdef BSP_USING_PULSE_ENCODER2
PULSE_ENCODER2_CONFIG,
#endif
#ifdef BSP_USING_PULSE_ENCODER3
PULSE_ENCODER3_CONFIG,
#endif
#ifdef BSP_USING_PULSE_ENCODER4
PULSE_ENCODER4_CONFIG,
#endif
#ifdef BSP_USING_PULSE_ENCODER5
PULSE_ENCODER5_CONFIG,
#endif
#ifdef BSP_USING_PULSE_ENCODER6
PULSE_ENCODER6_CONFIG,
#endif
#ifdef BSP_USING_PULSE_ENCODER7
PULSE_ENCODER7_CONFIG,
#endif
#ifdef BSP_USING_PULSE_ENCODER8
PULSE_ENCODER8_CONFIG,
#endif
#ifdef BSP_USING_PULSE_ENCODER9
PULSE_ENCODER9_CONFIG,
#endif
#ifdef BSP_USING_PULSE_ENCODER10
PULSE_ENCODER10_CONFIG,
#endif
#ifdef BSP_USING_PULSE_ENCODER11
PULSE_ENCODER11_CONFIG,
#endif
#ifdef BSP_USING_PULSE_ENCODER12
PULSE_ENCODER12_CONFIG,
#endif
#ifdef BSP_USING_PULSE_ENCODER13
PULSE_ENCODER13_CONFIG,
#endif
#ifdef BSP_USING_PULSE_ENCODER14
PULSE_ENCODER14_CONFIG,
#endif
};
/**
* @brief Initialize the pulse encoder hardware.
*/
static rt_err_t pulse_encoder_init(struct rt_pulse_encoder_device *pulse_encoder)
{
struct n32_pulse_encoder_device *n32_device;
TIM_TimeBaseInitType TIM_TimeBaseStructure;
n32_device = (struct n32_pulse_encoder_device *)pulse_encoder;
/* Enable timer clock */
n32_tim_enable_clock(n32_device->timer);
/* Configure time base for encoder mode */
TIM_InitTimBaseStruct(&TIM_TimeBaseStructure);
TIM_TimeBaseStructure.Prescaler = 0;
TIM_TimeBaseStructure.CounterMode = TIM_CNT_MODE_UP;
TIM_TimeBaseStructure.Period = AUTO_RELOAD_VALUE;
TIM_TimeBaseStructure.ClkDiv = TIM_CLK_DIV1;
TIM_InitTimeBase(n32_device->timer, &TIM_TimeBaseStructure);
/* Limit update interrupt source to counter overflow/underflow only (URS equivalent) */
TIM_ConfigUpdateRequestIntSrc(n32_device->timer, TIM_UPDATE_SRC_REGULAR);
/* Configure encoder interface in quadrature mode (TI1 + TI2) */
TIM_ConfigEncoderInterface(n32_device->timer,
TIM_ENCODE_QUA_MODE_TI12,
TIM_IC_POLARITY_RISING,
TIM_IC_POLARITY_RISING);
/* Configure TI1 and TI2 input capture with filter */
ConfigTI1(n32_device->timer, TIM_IC_POLARITY_RISING, TIM_IC_SELECTION_DIRECTTI, 3);
ConfigTI2(n32_device->timer, TIM_IC_POLARITY_RISING, TIM_IC_SELECTION_DIRECTTI, 3);
/* Configure NVIC for update interrupt (overflow tracking) */
NVIC_SetPriority(n32_device->tim_irqn,
NVIC_EncodePriority(NVIC_GetPriorityGrouping(), 3, 0));
NVIC_EnableIRQ(n32_device->tim_irqn);
/* Clear update flag and enable update interrupt source */
TIM_ClearFlag(n32_device->timer, TIM_FLAG_UPDATE);
TIM_EnableUpdateEvt(n32_device->timer, ENABLE);
LOG_D("%s init success", n32_device->name);
return RT_EOK;
}
/**
* @brief Get the accumulated encoder count (handles 16-bit overflow).
*/
static rt_int32_t pulse_encoder_get_count(struct rt_pulse_encoder_device *pulse_encoder)
{
struct n32_pulse_encoder_device *n32_device;
n32_device = (struct n32_pulse_encoder_device *)pulse_encoder;
return (rt_int32_t)((rt_int16_t)TIM_GetCnt(n32_device->timer) + n32_device->over_under_flowcount * (AUTO_RELOAD_VALUE + 1));
}
/**
* @brief Clear the encoder count and overflow accumulator.
*/
static rt_err_t pulse_encoder_clear_count(struct rt_pulse_encoder_device *pulse_encoder)
{
struct n32_pulse_encoder_device *n32_device;
n32_device = (struct n32_pulse_encoder_device *)pulse_encoder;
n32_device->over_under_flowcount = 0;
TIM_SetCnt(n32_device->timer, 0);
return RT_EOK;
}
/**
* @brief Control the pulse encoder (enable/disable).
*/
static rt_err_t pulse_encoder_control(struct rt_pulse_encoder_device *pulse_encoder, rt_uint32_t cmd, void *args)
{
rt_err_t result;
struct n32_pulse_encoder_device *n32_device;
n32_device = (struct n32_pulse_encoder_device *)pulse_encoder;
result = RT_EOK;
switch (cmd)
{
case PULSE_ENCODER_CMD_ENABLE:
/* Enable update interrupt for overflow tracking */
TIM_ConfigInt(n32_device->timer, TIM_INT_UPDATE, ENABLE);
/* Enable timer counter */
TIM_Enable(n32_device->timer, ENABLE);
break;
case PULSE_ENCODER_CMD_DISABLE:
/* Disable update interrupt */
TIM_ConfigInt(n32_device->timer, TIM_INT_UPDATE, DISABLE);
/* Stop timer counter */
TIM_Enable(n32_device->timer, DISABLE);
break;
default:
result = -RT_ENOSYS;
break;
}
return result;
}
/**
* @brief ISR update handler: track overflow/underflow for 32-bit position accumulation.
*/
static void pulse_encoder_update_isr(struct n32_pulse_encoder_device *device)
{
/* TIM Update event (overflow/underflow) */
if (TIM_GetFlagStatus(device->timer, TIM_FLAG_UPDATE) != RESET)
{
TIM_ClearFlag(device->timer, TIM_FLAG_UPDATE);
/* Check counting direction */
if (TIM_GetFlagStatus(device->timer, TIM_DOWN_COUNTING) != RESET)
{
device->over_under_flowcount--;
}
else
{
device->over_under_flowcount++;
}
}
/* Capture compare 1 event */
if (TIM_GetFlagStatus(device->timer, TIM_FLAG_CC1) != RESET)
{
TIM_ClearFlag(device->timer, TIM_FLAG_CC1);
}
/* Capture compare 2 event */
if (TIM_GetFlagStatus(device->timer, TIM_FLAG_CC2) != RESET)
{
TIM_ClearFlag(device->timer, TIM_FLAG_CC2);
}
/* Capture compare 3 event */
if (TIM_GetFlagStatus(device->timer, TIM_FLAG_CC3) != RESET)
{
TIM_ClearFlag(device->timer, TIM_FLAG_CC3);
}
/* Capture compare 4 event */
if (TIM_GetFlagStatus(device->timer, TIM_FLAG_CC4) != RESET)
{
TIM_ClearFlag(device->timer, TIM_FLAG_CC4);
}
/* Break input event */
if (TIM_GetFlagStatus(device->timer, TIM_FLAG_BREAK) != RESET)
{
TIM_ClearFlag(device->timer, TIM_FLAG_BREAK);
}
/* Trigger detection event */
if (TIM_GetFlagStatus(device->timer, TIM_FLAG_TRIG) != RESET)
{
TIM_ClearFlag(device->timer, TIM_FLAG_TRIG);
}
/* Commutation event */
if (TIM_GetFlagStatus(device->timer, TIM_FLAG_COM) != RESET)
{
TIM_ClearFlag(device->timer, TIM_FLAG_COM);
}
}
/* ---- ISR Handlers ---- */
#ifdef BSP_USING_PULSE_ENCODER1
void ATIM1_UP_IRQHandler(void)
{
rt_interrupt_enter();
pulse_encoder_update_isr(&n32_pulse_encoder_obj[PULSE_ENCODER1_INDEX]);
rt_interrupt_leave();
}
#endif
#ifdef BSP_USING_PULSE_ENCODER2
void ATIM2_UP_IRQHandler(void)
{
rt_interrupt_enter();
pulse_encoder_update_isr(&n32_pulse_encoder_obj[PULSE_ENCODER2_INDEX]);
rt_interrupt_leave();
}
#endif
#ifdef BSP_USING_PULSE_ENCODER3
void ATIM3_UP_IRQHandler(void)
{
rt_interrupt_enter();
pulse_encoder_update_isr(&n32_pulse_encoder_obj[PULSE_ENCODER3_INDEX]);
rt_interrupt_leave();
}
#endif
#ifdef BSP_USING_PULSE_ENCODER4
void ATIM4_UP_IRQHandler(void)
{
rt_interrupt_enter();
pulse_encoder_update_isr(&n32_pulse_encoder_obj[PULSE_ENCODER4_INDEX]);
rt_interrupt_leave();
}
#endif
#ifdef BSP_USING_PULSE_ENCODER5
void GTIMA1_IRQHandler(void)
{
rt_interrupt_enter();
pulse_encoder_update_isr(&n32_pulse_encoder_obj[PULSE_ENCODER5_INDEX]);
rt_interrupt_leave();
}
#endif
#ifdef BSP_USING_PULSE_ENCODER6
void GTIMA2_IRQHandler(void)
{
rt_interrupt_enter();
pulse_encoder_update_isr(&n32_pulse_encoder_obj[PULSE_ENCODER6_INDEX]);
rt_interrupt_leave();
}
#endif
#ifdef BSP_USING_PULSE_ENCODER7
void GTIMA3_IRQHandler(void)
{
rt_interrupt_enter();
pulse_encoder_update_isr(&n32_pulse_encoder_obj[PULSE_ENCODER7_INDEX]);
rt_interrupt_leave();
}
#endif
#ifdef BSP_USING_PULSE_ENCODER8
void GTIMA4_IRQHandler(void)
{
rt_interrupt_enter();
pulse_encoder_update_isr(&n32_pulse_encoder_obj[PULSE_ENCODER8_INDEX]);
rt_interrupt_leave();
}
#endif
#ifdef BSP_USING_PULSE_ENCODER9
void GTIMA5_IRQHandler(void)
{
rt_interrupt_enter();
pulse_encoder_update_isr(&n32_pulse_encoder_obj[PULSE_ENCODER9_INDEX]);
rt_interrupt_leave();
}
#endif
#ifdef BSP_USING_PULSE_ENCODER10
void GTIMA6_IRQHandler(void)
{
rt_interrupt_enter();
pulse_encoder_update_isr(&n32_pulse_encoder_obj[PULSE_ENCODER10_INDEX]);
rt_interrupt_leave();
}
#endif
#ifdef BSP_USING_PULSE_ENCODER11
void GTIMA7_IRQHandler(void)
{
rt_interrupt_enter();
pulse_encoder_update_isr(&n32_pulse_encoder_obj[PULSE_ENCODER11_INDEX]);
rt_interrupt_leave();
}
#endif
#ifdef BSP_USING_PULSE_ENCODER12
void GTIMB1_IRQHandler(void)
{
rt_interrupt_enter();
pulse_encoder_update_isr(&n32_pulse_encoder_obj[PULSE_ENCODER12_INDEX]);
rt_interrupt_leave();
}
#endif
#ifdef BSP_USING_PULSE_ENCODER13
void GTIMB2_IRQHandler(void)
{
rt_interrupt_enter();
pulse_encoder_update_isr(&n32_pulse_encoder_obj[PULSE_ENCODER13_INDEX]);
rt_interrupt_leave();
}
#endif
#ifdef BSP_USING_PULSE_ENCODER14
void GTIMB3_IRQHandler(void)
{
rt_interrupt_enter();
pulse_encoder_update_isr(&n32_pulse_encoder_obj[PULSE_ENCODER14_INDEX]);
rt_interrupt_leave();
}
#endif
/* ---- Device Registration ---- */
static const struct rt_pulse_encoder_ops _ops = {
.init = pulse_encoder_init,
.get_count = pulse_encoder_get_count,
.clear_count = pulse_encoder_clear_count,
.control = pulse_encoder_control,
};
static int n32_pulse_encoder_init(void)
{
int i;
int result;
result = RT_EOK;
for (i = 0; i < sizeof(n32_pulse_encoder_obj) / sizeof(n32_pulse_encoder_obj[0]); i++)
{
n32_pulse_encoder_obj[i].pulse_encoder.type = AB_PHASE_PULSE_ENCODER;
n32_pulse_encoder_obj[i].pulse_encoder.ops = &_ops;
if (rt_device_pulse_encoder_register(&n32_pulse_encoder_obj[i].pulse_encoder,
n32_pulse_encoder_obj[i].name, RT_NULL) != RT_EOK)
{
LOG_E("%s register failed", n32_pulse_encoder_obj[i].name);
result = -RT_ERROR;
}
else
{
LOG_D("%s register success", n32_pulse_encoder_obj[i].name);
}
}
return result;
}
INIT_BOARD_EXPORT(n32_pulse_encoder_init);
#endif /* RT_USING_PULSE_ENCODER */

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/*
* Copyright (c) 2006-2025, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2026-06-23 ox-horse first version
*/
#include <board.h>
#include <rtthread.h>
#ifdef BSP_USING_PWM
#include "drv_config.h"
#include "drv_tim.h"
#include <drivers/dev_pwm.h>
//#define DRV_DEBUG
#define LOG_TAG "drv.pwm"
#include <drv_log.h>
#define MAX_PERIOD 65535
#define MIN_PERIOD 1
#define MIN_PULSE 1
/* All ATIM and GTIM timers on N32H7xx support 4 PWM output channels (CH1-CH4).
* BTIM1-4 are basic timers without PWM capability.
*
* PWM device naming:
* ATIM1-4 -> pwm1-4 (advanced, with complementary output)
* GTIMA1-7 -> pwm5-11 (general purpose, A bus)
* GTIMB1-3 -> pwm12-14 (general purpose, B bus, with complementary output)
*/
enum
{
#ifdef BSP_USING_PWM1
PWM1_INDEX,
#endif
#ifdef BSP_USING_PWM2
PWM2_INDEX,
#endif
#ifdef BSP_USING_PWM3
PWM3_INDEX,
#endif
#ifdef BSP_USING_PWM4
PWM4_INDEX,
#endif
#ifdef BSP_USING_PWM5
PWM5_INDEX,
#endif
#ifdef BSP_USING_PWM6
PWM6_INDEX,
#endif
#ifdef BSP_USING_PWM7
PWM7_INDEX,
#endif
#ifdef BSP_USING_PWM8
PWM8_INDEX,
#endif
#ifdef BSP_USING_PWM9
PWM9_INDEX,
#endif
#ifdef BSP_USING_PWM10
PWM10_INDEX,
#endif
#ifdef BSP_USING_PWM11
PWM11_INDEX,
#endif
#ifdef BSP_USING_PWM12
PWM12_INDEX,
#endif
#ifdef BSP_USING_PWM13
PWM13_INDEX,
#endif
#ifdef BSP_USING_PWM14
PWM14_INDEX,
#endif
};
struct n32_pwm
{
struct rt_device_pwm pwm_device;
TIM_Module *timer;
rt_uint8_t channel; /* bitmask: bit0=CH1, bit1=CH2, bit2=CH3, bit3=CH4 */
char *name;
};
static struct n32_pwm n32_pwm_obj[] = {
#ifdef BSP_USING_PWM1
PWM1_CONFIG,
#endif
#ifdef BSP_USING_PWM2
PWM2_CONFIG,
#endif
#ifdef BSP_USING_PWM3
PWM3_CONFIG,
#endif
#ifdef BSP_USING_PWM4
PWM4_CONFIG,
#endif
#ifdef BSP_USING_PWM5
PWM5_CONFIG,
#endif
#ifdef BSP_USING_PWM6
PWM6_CONFIG,
#endif
#ifdef BSP_USING_PWM7
PWM7_CONFIG,
#endif
#ifdef BSP_USING_PWM8
PWM8_CONFIG,
#endif
#ifdef BSP_USING_PWM9
PWM9_CONFIG,
#endif
#ifdef BSP_USING_PWM10
PWM10_CONFIG,
#endif
#ifdef BSP_USING_PWM11
PWM11_CONFIG,
#endif
#ifdef BSP_USING_PWM12
PWM12_CONFIG,
#endif
#ifdef BSP_USING_PWM13
PWM13_CONFIG,
#endif
#ifdef BSP_USING_PWM14
PWM14_CONFIG,
#endif
};
static rt_uint64_t tim_clock_get(TIM_Module *timer)
{
rt_uint32_t tim_div;
RCC_ClocksTypeDef RCC_Clocks;
n32_tim_ahbx_div_get(timer, &tim_div);
RCC_GetClocksFreqValue(&RCC_Clocks);
if ((timer == BTIM1) || (timer == BTIM2) || (timer == BTIM3) || (timer == BTIM4) || (timer == GTIMA4) || (timer == GTIMA5) || (timer == GTIMA6) || (timer == GTIMA7) || (timer == GTIMB1) || (timer == GTIMB2) || (timer == GTIMB3))
{
return (rt_uint64_t)RCC_Clocks.AHB1ClkFreq / tim_div;
}
else if ((timer == ATIM1) || (timer == ATIM2) || (timer == GTIMA1) || (timer == GTIMA2) || (timer == GTIMA3))
{
return (rt_uint64_t)RCC_Clocks.AHB2ClkFreq / tim_div;
}
else /* ATIM3, ATIM4 */
{
return (rt_uint64_t)RCC_Clocks.AHB5ClkFreq / tim_div;
}
}
static rt_err_t drv_pwm_control(struct rt_device_pwm *device, int cmd, void *arg);
static struct rt_pwm_ops drv_ops = {
drv_pwm_control
};
static rt_err_t drv_pwm_enable(struct n32_pwm *pwm, struct rt_pwm_configuration *configuration, rt_bool_t enable)
{
rt_uint32_t tim_ch = 0x04 * (configuration->channel - 1);
if (!configuration->complementary)
{
TIM_EnableCapCmpCh(pwm->timer, tim_ch,
enable ? TIM_CAP_CMP_ENABLE : TIM_CAP_CMP_DISABLE);
}
else
{
TIM_EnableCapCmpChN(pwm->timer, tim_ch,
enable ? TIM_CAP_CMP_N_ENABLE : TIM_CAP_CMP_N_DISABLE);
}
return RT_EOK;
}
static rt_err_t drv_pwm_get(struct n32_pwm *pwm, struct rt_pwm_configuration *configuration)
{
rt_uint64_t tim_clock;
rt_uint32_t period;
rt_uint32_t psc;
rt_uint32_t cmp = 0;
tim_clock = tim_clock_get(pwm->timer);
/* Convert to MHz for nanosecond calculation */
tim_clock /= 1000000UL;
period = TIM_GetAutoReload(pwm->timer) + 1;
psc = TIM_GetPrescaler(pwm->timer) + 1;
/* period (ns) = (ARR+1) * (PSC+1) * 1000 / tim_clock_MHz */
configuration->period = period * psc * 1000UL / tim_clock;
switch (configuration->channel)
{
case 1:
cmp = TIM_GetCap1(pwm->timer);
break;
case 2:
cmp = TIM_GetCap2(pwm->timer);
break;
case 3:
cmp = TIM_GetCap3(pwm->timer);
break;
case 4:
cmp = TIM_GetCap4(pwm->timer);
break;
default:
return -RT_EINVAL;
}
configuration->pulse = (cmp + 1) * psc * 1000UL / tim_clock;
return RT_EOK;
}
uint32_t temp;
static rt_err_t drv_pwm_set(struct n32_pwm *pwm, struct rt_pwm_configuration *configuration)
{
rt_uint32_t period, pulse;
rt_uint64_t tim_clock, psc;
/* Converts the channel number to the channel number of standard library */
rt_uint32_t tim_ch = 0x04 * (configuration->channel - 1);
tim_clock = tim_clock_get(pwm->timer);
temp = tim_clock;
/* Convert to MHz */
tim_clock /= 1000000UL;
/* Calculate period and prescaler from requested period (ns) */
period = (rt_uint64_t)configuration->period * tim_clock / 1000ULL;
psc = period / MAX_PERIOD + 1;
period = period / psc;
/* Set prescaler */
TIM_ConfigPrescaler(pwm->timer, (uint32_t)(psc - 1), TIM_PSC_RELOAD_MODE_UPDATE);
if (period < MIN_PERIOD)
{
period = MIN_PERIOD;
}
TIM_SetAutoReload(pwm->timer, period - 1);
/* Calculate pulse from requested pulse (ns) */
pulse = (rt_uint64_t)configuration->pulse * tim_clock / psc / 1000ULL;
if (pulse < MIN_PULSE)
{
pulse = MIN_PULSE;
}
else if (pulse >= period)
{
pulse = period;
}
/* Set compare value */
switch (configuration->channel)
{
case 1:
TIM_SetCmp1(pwm->timer, (uint16_t)pulse);
break;
case 2:
TIM_SetCmp2(pwm->timer, (uint16_t)pulse);
break;
case 3:
TIM_SetCmp3(pwm->timer, (uint16_t)pulse);
break;
case 4:
TIM_SetCmp4(pwm->timer, (uint16_t)pulse);
break;
default:
return -RT_EINVAL;
}
/* Generate update event to apply immediately */
TIM_GenerateEvent(pwm->timer, TIM_EVT_SRC_UPDATE);
return RT_EOK;
}
static rt_err_t drv_pwm_set_period(struct n32_pwm *pwm, struct rt_pwm_configuration *configuration)
{
rt_uint32_t period;
rt_uint64_t tim_clock, psc;
tim_clock = tim_clock_get(pwm->timer);
tim_clock /= 1000000UL;
period = (rt_uint64_t)configuration->period * tim_clock / 1000ULL;
psc = period / MAX_PERIOD + 1;
period = period / psc;
TIM_ConfigPrescaler(pwm->timer, (uint32_t)(psc - 1), TIM_PSC_RELOAD_MODE_UPDATE);
if (period < MIN_PERIOD)
{
period = MIN_PERIOD;
}
TIM_SetAutoReload(pwm->timer, period - 1);
return RT_EOK;
}
static rt_err_t drv_pwm_set_pulse(struct n32_pwm *pwm, struct rt_pwm_configuration *configuration)
{
rt_uint32_t period, pulse;
rt_uint64_t tim_clock;
tim_clock = tim_clock_get(pwm->timer);
tim_clock /= 1000000UL;
period = (TIM_GetAutoReload(pwm->timer) + 1) * (TIM_GetPrescaler(pwm->timer) + 1) * 1000UL / tim_clock;
pulse = (rt_uint64_t)configuration->pulse * (TIM_GetAutoReload(pwm->timer) + 1) / period;
if (pulse < MIN_PULSE)
{
pulse = MIN_PULSE;
}
else if (pulse > (rt_uint32_t)(TIM_GetAutoReload(pwm->timer) + 1))
{
pulse = TIM_GetAutoReload(pwm->timer) + 1;
}
switch (configuration->channel)
{
case 1:
TIM_SetCmp1(pwm->timer, (uint16_t)(pulse - 1));
break;
case 2:
TIM_SetCmp2(pwm->timer, (uint16_t)(pulse - 1));
break;
case 3:
TIM_SetCmp3(pwm->timer, (uint16_t)(pulse - 1));
break;
case 4:
TIM_SetCmp4(pwm->timer, (uint16_t)(pulse - 1));
break;
default:
return -RT_EINVAL;
}
return RT_EOK;
}
static rt_err_t drv_pwm_control(struct rt_device_pwm *device, int cmd, void *arg)
{
struct rt_pwm_configuration *configuration = (struct rt_pwm_configuration *)arg;
struct n32_pwm *pwm = (struct n32_pwm *)device->parent.user_data;
switch (cmd)
{
case PWM_CMD_ENABLE:
return drv_pwm_enable(pwm, configuration, RT_TRUE);
case PWM_CMD_DISABLE:
return drv_pwm_enable(pwm, configuration, RT_FALSE);
case PWM_CMD_SET:
return drv_pwm_set(pwm, configuration);
case PWM_CMD_SET_PERIOD:
return drv_pwm_set_period(pwm, configuration);
case PWM_CMD_SET_PULSE:
return drv_pwm_set_pulse(pwm, configuration);
case PWM_CMD_GET:
return drv_pwm_get(pwm, configuration);
default:
return -RT_EINVAL;
}
}
/**
* @brief Initialize a single PWM channel hardware.
*/
static void drv_pwm_channel_init(TIM_Module *timer, rt_uint32_t channel_idx, rt_uint32_t oc_mode)
{
OCInitType TIM_OCInitStructure;
TIM_InitOcStruct(&TIM_OCInitStructure);
TIM_OCInitStructure.OCMode = oc_mode;
TIM_OCInitStructure.OutputState = TIM_OUTPUT_STATE_ENABLE;
TIM_OCInitStructure.OutputNState = TIM_OUTPUT_NSTATE_DISABLE;
TIM_OCInitStructure.Pulse = 0;
TIM_OCInitStructure.OCPolarity = TIM_OC_POLARITY_HIGH;
TIM_OCInitStructure.OCNPolarity = TIM_OCN_POLARITY_HIGH;
TIM_OCInitStructure.OCIdleState = TIM_OC_IDLE_STATE_RESET;
TIM_OCInitStructure.OCNIdleState = TIM_OCN_IDLE_STATE_RESET;
switch (channel_idx)
{
case 0:
TIM_InitOc1(timer, &TIM_OCInitStructure);
TIM_ConfigOc1Preload(timer, TIM_OC_PRE_LOAD_ENABLE);
break;
case 1:
TIM_InitOc2(timer, &TIM_OCInitStructure);
TIM_ConfigOc2Preload(timer, TIM_OC_PRE_LOAD_ENABLE);
break;
case 2:
TIM_InitOc3(timer, &TIM_OCInitStructure);
TIM_ConfigOc3Preload(timer, TIM_OC_PRE_LOAD_ENABLE);
break;
case 3:
TIM_InitOc4(timer, &TIM_OCInitStructure);
TIM_ConfigOc4Preload(timer, TIM_OC_PRE_LOAD_ENABLE);
break;
default:
break;
}
}
/**
* @brief Hardware initialization for one PWM device.
*/
static rt_err_t n32_hw_pwm_init(struct n32_pwm *device)
{
rt_err_t result = RT_EOK;
TIM_TimeBaseInitType TIM_TimeBaseStructure;
rt_uint32_t i;
RT_ASSERT(device != RT_NULL);
/* Enable timer clock (M7 + M4 dual-core clock enable) */
n32_tim_enable_clock(device->timer);
/* Configure time base: default 1kHz, PWM mode */
TIM_InitTimBaseStruct(&TIM_TimeBaseStructure);
TIM_TimeBaseStructure.Period = 1000 - 1;
TIM_TimeBaseStructure.Prescaler = 0;
TIM_TimeBaseStructure.ClkDiv = TIM_CLK_DIV1;
TIM_TimeBaseStructure.CounterMode = TIM_CNT_MODE_UP;
TIM_TimeBaseStructure.RepetCnt = 0;
TIM_InitTimeBase(device->timer, &TIM_TimeBaseStructure);
/* Configure PWM output channels */
for (i = 0; i < 4; i++)
{
if (device->channel & (1 << i))
{
drv_pwm_channel_init(device->timer, i, TIM_OCMODE_PWM1);
}
}
/* Enable auto-reload preload */
TIM_ConfigArPreload(device->timer, ENABLE);
/* Enable main output for advanced timers (ATIM1-4, GTIMB1-3) */
if ((IS_ATIM1_4_DEVICE(device->timer)) || ((IS_GTIMB1_3_DEVICE(device->timer))))
{
TIM_EnableCtrlPwmOutputs(device->timer, ENABLE);
}
/* Enable timer counter */
TIM_Enable(device->timer, ENABLE);
LOG_D("%s init success", device->name);
return result;
}
/**
* @brief Parse BSP_USING_PWMx_CHy macros to set channel bitmask.
*/
static void n32_pwm_get_channel(void)
{
#ifdef BSP_USING_PWM1_CH1
n32_pwm_obj[PWM1_INDEX].channel |= 1 << 0;
#endif
#ifdef BSP_USING_PWM1_CH2
n32_pwm_obj[PWM1_INDEX].channel |= 1 << 1;
#endif
#ifdef BSP_USING_PWM1_CH3
n32_pwm_obj[PWM1_INDEX].channel |= 1 << 2;
#endif
#ifdef BSP_USING_PWM1_CH4
n32_pwm_obj[PWM1_INDEX].channel |= 1 << 3;
#endif
#ifdef BSP_USING_PWM2_CH1
n32_pwm_obj[PWM2_INDEX].channel |= 1 << 0;
#endif
#ifdef BSP_USING_PWM2_CH2
n32_pwm_obj[PWM2_INDEX].channel |= 1 << 1;
#endif
#ifdef BSP_USING_PWM2_CH3
n32_pwm_obj[PWM2_INDEX].channel |= 1 << 2;
#endif
#ifdef BSP_USING_PWM2_CH4
n32_pwm_obj[PWM2_INDEX].channel |= 1 << 3;
#endif
#ifdef BSP_USING_PWM3_CH1
n32_pwm_obj[PWM3_INDEX].channel |= 1 << 0;
#endif
#ifdef BSP_USING_PWM3_CH2
n32_pwm_obj[PWM3_INDEX].channel |= 1 << 1;
#endif
#ifdef BSP_USING_PWM3_CH3
n32_pwm_obj[PWM3_INDEX].channel |= 1 << 2;
#endif
#ifdef BSP_USING_PWM3_CH4
n32_pwm_obj[PWM3_INDEX].channel |= 1 << 3;
#endif
#ifdef BSP_USING_PWM4_CH1
n32_pwm_obj[PWM4_INDEX].channel |= 1 << 0;
#endif
#ifdef BSP_USING_PWM4_CH2
n32_pwm_obj[PWM4_INDEX].channel |= 1 << 1;
#endif
#ifdef BSP_USING_PWM4_CH3
n32_pwm_obj[PWM4_INDEX].channel |= 1 << 2;
#endif
#ifdef BSP_USING_PWM4_CH4
n32_pwm_obj[PWM4_INDEX].channel |= 1 << 3;
#endif
#ifdef BSP_USING_PWM5_CH1
n32_pwm_obj[PWM5_INDEX].channel |= 1 << 0;
#endif
#ifdef BSP_USING_PWM5_CH2
n32_pwm_obj[PWM5_INDEX].channel |= 1 << 1;
#endif
#ifdef BSP_USING_PWM5_CH3
n32_pwm_obj[PWM5_INDEX].channel |= 1 << 2;
#endif
#ifdef BSP_USING_PWM5_CH4
n32_pwm_obj[PWM5_INDEX].channel |= 1 << 3;
#endif
#ifdef BSP_USING_PWM6_CH1
n32_pwm_obj[PWM6_INDEX].channel |= 1 << 0;
#endif
#ifdef BSP_USING_PWM6_CH2
n32_pwm_obj[PWM6_INDEX].channel |= 1 << 1;
#endif
#ifdef BSP_USING_PWM6_CH3
n32_pwm_obj[PWM6_INDEX].channel |= 1 << 2;
#endif
#ifdef BSP_USING_PWM6_CH4
n32_pwm_obj[PWM6_INDEX].channel |= 1 << 3;
#endif
#ifdef BSP_USING_PWM7_CH1
n32_pwm_obj[PWM7_INDEX].channel |= 1 << 0;
#endif
#ifdef BSP_USING_PWM7_CH2
n32_pwm_obj[PWM7_INDEX].channel |= 1 << 1;
#endif
#ifdef BSP_USING_PWM7_CH3
n32_pwm_obj[PWM7_INDEX].channel |= 1 << 2;
#endif
#ifdef BSP_USING_PWM7_CH4
n32_pwm_obj[PWM7_INDEX].channel |= 1 << 3;
#endif
#ifdef BSP_USING_PWM8_CH1
n32_pwm_obj[PWM8_INDEX].channel |= 1 << 0;
#endif
#ifdef BSP_USING_PWM8_CH2
n32_pwm_obj[PWM8_INDEX].channel |= 1 << 1;
#endif
#ifdef BSP_USING_PWM8_CH3
n32_pwm_obj[PWM8_INDEX].channel |= 1 << 2;
#endif
#ifdef BSP_USING_PWM8_CH4
n32_pwm_obj[PWM8_INDEX].channel |= 1 << 3;
#endif
#ifdef BSP_USING_PWM9_CH1
n32_pwm_obj[PWM9_INDEX].channel |= 1 << 0;
#endif
#ifdef BSP_USING_PWM9_CH2
n32_pwm_obj[PWM9_INDEX].channel |= 1 << 1;
#endif
#ifdef BSP_USING_PWM9_CH3
n32_pwm_obj[PWM9_INDEX].channel |= 1 << 2;
#endif
#ifdef BSP_USING_PWM9_CH4
n32_pwm_obj[PWM9_INDEX].channel |= 1 << 3;
#endif
#ifdef BSP_USING_PWM10_CH1
n32_pwm_obj[PWM10_INDEX].channel |= 1 << 0;
#endif
#ifdef BSP_USING_PWM10_CH2
n32_pwm_obj[PWM10_INDEX].channel |= 1 << 1;
#endif
#ifdef BSP_USING_PWM10_CH3
n32_pwm_obj[PWM10_INDEX].channel |= 1 << 2;
#endif
#ifdef BSP_USING_PWM10_CH4
n32_pwm_obj[PWM10_INDEX].channel |= 1 << 3;
#endif
#ifdef BSP_USING_PWM11_CH1
n32_pwm_obj[PWM11_INDEX].channel |= 1 << 0;
#endif
#ifdef BSP_USING_PWM11_CH2
n32_pwm_obj[PWM11_INDEX].channel |= 1 << 1;
#endif
#ifdef BSP_USING_PWM11_CH3
n32_pwm_obj[PWM11_INDEX].channel |= 1 << 2;
#endif
#ifdef BSP_USING_PWM11_CH4
n32_pwm_obj[PWM11_INDEX].channel |= 1 << 3;
#endif
#ifdef BSP_USING_PWM12_CH1
n32_pwm_obj[PWM12_INDEX].channel |= 1 << 0;
#endif
#ifdef BSP_USING_PWM12_CH2
n32_pwm_obj[PWM12_INDEX].channel |= 1 << 1;
#endif
#ifdef BSP_USING_PWM12_CH3
n32_pwm_obj[PWM12_INDEX].channel |= 1 << 2;
#endif
#ifdef BSP_USING_PWM12_CH4
n32_pwm_obj[PWM12_INDEX].channel |= 1 << 3;
#endif
#ifdef BSP_USING_PWM13_CH1
n32_pwm_obj[PWM13_INDEX].channel |= 1 << 0;
#endif
#ifdef BSP_USING_PWM13_CH2
n32_pwm_obj[PWM13_INDEX].channel |= 1 << 1;
#endif
#ifdef BSP_USING_PWM13_CH3
n32_pwm_obj[PWM13_INDEX].channel |= 1 << 2;
#endif
#ifdef BSP_USING_PWM13_CH4
n32_pwm_obj[PWM13_INDEX].channel |= 1 << 3;
#endif
#ifdef BSP_USING_PWM14_CH1
n32_pwm_obj[PWM14_INDEX].channel |= 1 << 0;
#endif
#ifdef BSP_USING_PWM14_CH2
n32_pwm_obj[PWM14_INDEX].channel |= 1 << 1;
#endif
#ifdef BSP_USING_PWM14_CH3
n32_pwm_obj[PWM14_INDEX].channel |= 1 << 2;
#endif
#ifdef BSP_USING_PWM14_CH4
n32_pwm_obj[PWM14_INDEX].channel |= 1 << 3;
#endif
}
static int n32_pwm_init(void)
{
int i = 0;
int result = RT_EOK;
n32_pwm_get_channel();
for (i = 0; i < sizeof(n32_pwm_obj) / sizeof(n32_pwm_obj[0]); i++)
{
/* pwm init */
if (n32_hw_pwm_init(&n32_pwm_obj[i]) != RT_EOK)
{
LOG_E("%s init failed", n32_pwm_obj[i].name);
result = -RT_ERROR;
goto __exit;
}
else
{
LOG_D("%s init success", n32_pwm_obj[i].name);
/* register pwm device */
if (rt_device_pwm_register(&n32_pwm_obj[i].pwm_device, n32_pwm_obj[i].name, &drv_ops, &n32_pwm_obj[i]) == RT_EOK)
{
LOG_D("%s register success", n32_pwm_obj[i].name);
}
else
{
LOG_E("%s register failed", n32_pwm_obj[i].name);
result = -RT_ERROR;
}
}
}
__exit:
return result;
}
INIT_DEVICE_EXPORT(n32_pwm_init);
#endif /* BSP_USING_PWM */

892
bsp/n32/n32hxxx/libraries/N32_Drivers/drivers/drv_sdio.c Normal file
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@ -0,0 +1,892 @@
/*
* Copyright (c) 2006-2025, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2026-06-28 ox-horse first version
*/
#include "drv_sdio.h"
#include "rtdef.h"
#ifdef BSP_USING_SDIO
#define ALIGN(n) __attribute__((aligned(n)))
// #define DRV_DEBUG
#define LOG_TAG "drv.sdio"
#include <drv_log.h>
#include "board.h"
#include "drv_config.h"
static struct n32_sdio_config sdio_config = SDIO_BUS_CONFIG;
static struct n32_sdio_class sdio_obj;
static struct rt_mmcsd_host *host;
#define SDIO_TX_RX_COMPLETE_TIMEOUT_LOOPS (1000000)
#define RT_HW_SDIO_LOCK(_sdio) rt_mutex_take(&_sdio->mutex, RT_WAITING_FOREVER)
#define RT_HW_SDIO_UNLOCK(_sdio) rt_mutex_release(&_sdio->mutex);
struct sdio_pkg
{
struct rt_mmcsd_cmd *cmd;
void *buff;
rt_uint32_t flag;
};
struct rt_hw_sdio
{
struct rt_mmcsd_host *host;
struct n32_sdio_des sdio_des;
struct rt_event event;
struct rt_mutex mutex;
struct sdio_pkg *pkg;
};
ALIGN(SDIO_ALIGN_LEN)
static rt_uint8_t cache_buf[SDIO_BUFF_SIZE];
static rt_uint32_t n32_sdio_clk_get(struct n32_sdio *hw_sdio)
{
return SDIO_CLOCK_FREQ;
}
/**
* @brief this function get order from sdio.
* @param data
* @retval sdio order
*/
static int get_order(rt_uint32_t data)
{
int order = 0;
switch (data)
{
case 1:
order = 0;
break;
case 2:
order = 1;
break;
case 4:
order = 2;
break;
case 8:
order = 3;
break;
case 16:
order = 4;
break;
case 32:
order = 5;
break;
case 64:
order = 6;
break;
case 128:
order = 7;
break;
case 256:
order = 8;
break;
case 512:
order = 9;
break;
case 1024:
order = 10;
break;
case 2048:
order = 11;
break;
case 4096:
order = 12;
break;
case 8192:
order = 13;
break;
case 16384:
order = 14;
break;
default:
order = 0;
break;
}
return order;
}
/**
* @brief this function wait sdio completed.
* @param sdio rt_hw_sdio
* @retval none
*/
static void rt_hw_sdio_wait_completed(struct rt_hw_sdio *sdio)
{
rt_uint32_t status;
struct rt_mmcsd_cmd *cmd = sdio->pkg->cmd;
struct rt_mmcsd_data *data = cmd->data;
struct n32_sdio *hw_sdio = sdio->sdio_des.hw_sdio;
if (rt_event_recv(&sdio->event, 0xffffffff, RT_EVENT_FLAG_OR | RT_EVENT_FLAG_CLEAR,
rt_tick_from_millisecond(5000), &status) != RT_EOK)
{
LOG_E("wait completed timeout, cmd:%d, arg:0x%08x, rw:%c, len:%d",
cmd->cmd_code, cmd->arg,
data ? (data->flags & DATA_DIR_WRITE ? 'w' : 'r') : '-',
data ? data->blks * data->blksize : 0);
cmd->err = -RT_ETIMEOUT;
return;
}
if (sdio->pkg == RT_NULL)
{
return;
}
cmd->resp[0] = hw_sdio->resp1;
cmd->resp[1] = hw_sdio->resp2;
cmd->resp[2] = hw_sdio->resp3;
cmd->resp[3] = hw_sdio->resp4;
if (status & HW_SDIO_ERRORS)
{
if ((status & HW_SDIO_IT_CCRCFAIL) && (resp_type(cmd) & (RESP_R3 | RESP_R4)))
{
cmd->err = RT_EOK;
}
else
{
cmd->err = -RT_ERROR;
}
if (status & HW_SDIO_IT_CTIMEOUT)
{
cmd->err = -RT_ETIMEOUT;
}
if (status & HW_SDIO_IT_DCRCFAIL)
{
data->err = -RT_ERROR;
}
if (status & HW_SDIO_IT_DTIMEOUT)
{
data->err = -RT_ETIMEOUT;
}
if (cmd->err == RT_EOK)
{
LOG_D("sta:0x%08X [%08X %08X %08X %08X]", status, cmd->resp[0], cmd->resp[1], cmd->resp[2], cmd->resp[3]);
}
else
{
LOG_E("SDIO error: sta:0x%08x, cmd:%d, arg:0x%08x, rw:%c, len:%d, blksize:%d",
status,
cmd->cmd_code,
cmd->arg,
data ? (data->flags & DATA_DIR_WRITE ? 'w' : 'r') : '-',
data ? data->blks * data->blksize : 0,
data ? data->blksize : 0);
LOG_E("Error flags: %s%s%s%s%s%s",
status & HW_SDIO_IT_CCRCFAIL ? "CCRCFAIL " : "",
status & HW_SDIO_IT_DCRCFAIL ? "DCRCFAIL " : "",
status & HW_SDIO_IT_CTIMEOUT ? "CTIMEOUT " : "",
status & HW_SDIO_IT_DTIMEOUT ? "DTIMEOUT " : "",
status & HW_SDIO_IT_TXUNDERR ? "TXUNDERR " : "",
status & HW_SDIO_IT_RXOVERR ? "RXOVERR " : "");
}
}
else
{
cmd->err = RT_EOK;
LOG_D("sta:0x%08X [%08X %08X %08X %08X]", status, cmd->resp[0], cmd->resp[1], cmd->resp[2], cmd->resp[3]);
}
}
/**
* @brief this function transfer data by dma.
* @param sdio rt_hw_sdio
* @param pkg sdio package
* @retval none
*/
static void rt_hw_sdio_transfer_by_dma(struct rt_hw_sdio *sdio, struct sdio_pkg *pkg)
{
struct rt_mmcsd_data *data;
int size;
void *buff;
struct n32_sdio *hw_sdio;
if ((RT_NULL == pkg) || (RT_NULL == sdio))
{
LOG_E("rt_hw_sdio_transfer_by_dma invalid args");
return;
}
data = pkg->cmd->data;
if (RT_NULL == data)
{
LOG_E("rt_hw_sdio_transfer_by_dma invalid args");
return;
}
buff = pkg->buff;
if (RT_NULL == buff)
{
LOG_E("rt_hw_sdio_transfer_by_dma invalid args");
return;
}
hw_sdio = sdio->sdio_des.hw_sdio;
size = data->blks * data->blksize;
if (data->flags & DATA_DIR_WRITE)
{
sdio->sdio_des.txconfig((rt_uint32_t *)buff, (rt_uint32_t *)&hw_sdio->fifo, size);
hw_sdio->dctrl |= HW_SDIO_DMA_ENABLE;
}
else if (data->flags & DATA_DIR_READ)
{
sdio->sdio_des.rxconfig((rt_uint32_t *)&hw_sdio->fifo, (rt_uint32_t *)buff, size);
hw_sdio->dctrl |= HW_SDIO_DMA_ENABLE | HW_SDIO_DPSM_ENABLE;
}
}
/**
* @brief this function send command.
* @param sdio rt_hw_sdio
* @param pkg sdio package
* @retval none
*/
static void rt_hw_sdio_send_command(struct rt_hw_sdio *sdio, struct sdio_pkg *pkg)
{
struct rt_mmcsd_cmd *cmd = pkg->cmd;
struct rt_mmcsd_data *data = cmd->data;
struct n32_sdio *hw_sdio = sdio->sdio_des.hw_sdio;
rt_uint32_t reg_cmd;
/* save pkg */
sdio->pkg = pkg;
LOG_D("CMD:%d ARG:0x%08x RES:%s%s%s%s%s%s%s%s%s rw:%c len:%d blksize:%d",
cmd->cmd_code,
cmd->arg,
resp_type(cmd) == RESP_NONE ? "NONE" : "",
resp_type(cmd) == RESP_R1 ? "R1" : "",
resp_type(cmd) == RESP_R1B ? "R1B" : "",
resp_type(cmd) == RESP_R2 ? "R2" : "",
resp_type(cmd) == RESP_R3 ? "R3" : "",
resp_type(cmd) == RESP_R4 ? "R4" : "",
resp_type(cmd) == RESP_R5 ? "R5" : "",
resp_type(cmd) == RESP_R6 ? "R6" : "",
resp_type(cmd) == RESP_R7 ? "R7" : "",
data ? (data->flags & DATA_DIR_WRITE ? 'w' : 'r') : '-',
data ? data->blks * data->blksize : 0,
data ? data->blksize : 0);
/* config cmd reg */
reg_cmd = (cmd->cmd_code) << 8 | HW_SDIO_CPSM_ENABLE;
if (resp_type(cmd) == RESP_NONE)
reg_cmd |= HW_SDIO_RESPONSE_NO;
else if (resp_type(cmd) == RESP_R2)
reg_cmd |= HW_SDIO_RESPONSE_LONG;
else
reg_cmd |= HW_SDIO_RESPONSE_SHORT;
/* config data reg */
if (data != RT_NULL)
{
rt_uint32_t dir = 0;
rt_uint32_t size = data->blks * data->blksize;
int order;
hw_sdio->dctrl = 0;
hw_sdio->dtimer = HW_SDIO_DATATIMEOUT;
hw_sdio->dlen = size;
order = get_order(data->blksize);
dir = (data->flags & DATA_DIR_READ) ? HW_SDIO_TO_HOST : 0;
/* HW_SDIO_IO_ENABLE | */
hw_sdio->dctrl = (order << 8) | dir;
}
/* transfer config */
if (data != RT_NULL)
{
rt_hw_sdio_transfer_by_dma(sdio, pkg);
}
/* open irq */
hw_sdio->mask |= HW_SDIO_IT_CMDSENT | HW_SDIO_IT_CMDREND | HW_SDIO_ERRORS;
if (data != RT_NULL)
{
hw_sdio->mask |= HW_SDIO_IT_DATAEND;
}
/* send cmd */
hw_sdio->arg = cmd->arg;
hw_sdio->cmd = reg_cmd;
/* wait completed */
rt_hw_sdio_wait_completed(sdio);
/* waiting for data to be sent to completion */
if (data != RT_NULL)
{
volatile rt_uint32_t count = SDIO_TX_RX_COMPLETE_TIMEOUT_LOOPS;
while (count && (hw_sdio->sta & (HW_SDIO_IT_TXACT | HW_SDIO_IT_RXACT)))
{
count--;
}
if ((count == 0) || (hw_sdio->sta & HW_SDIO_ERRORS))
{
cmd->err = -RT_ERROR;
}
}
/* close irq, keep sdio irq */
hw_sdio->mask = hw_sdio->mask & HW_SDIO_IT_SDIOIT ? HW_SDIO_IT_SDIOIT : 0x00;
/* clear pkg */
sdio->pkg = RT_NULL;
}
/**
* @brief this function send sdio request.
* @param sdio rt_hw_sdio
* @param req request
* @retval none
*/
static void rt_hw_sdio_request(struct rt_mmcsd_host *host, struct rt_mmcsd_req *req)
{
struct sdio_pkg pkg;
struct rt_hw_sdio *sdio = host->private_data;
struct rt_mmcsd_data *data;
RT_HW_SDIO_LOCK(sdio);
if (req->cmd != RT_NULL)
{
memset(&pkg, 0, sizeof(pkg));
data = req->cmd->data;
pkg.cmd = req->cmd;
if (data != RT_NULL)
{
rt_uint32_t size = data->blks * data->blksize;
RT_ASSERT(size <= SDIO_BUFF_SIZE);
pkg.buff = data->buf;
if ((rt_uint32_t)data->buf & (SDIO_ALIGN_LEN - 1))
{
pkg.buff = cache_buf;
if (data->flags & DATA_DIR_WRITE)
{
rt_memcpy(cache_buf, data->buf, size);
}
}
}
rt_hw_sdio_send_command(sdio, &pkg);
if ((data != RT_NULL) && (data->flags & DATA_DIR_READ) && ((rt_uint32_t)data->buf & (SDIO_ALIGN_LEN - 1)))
{
rt_memcpy(data->buf, cache_buf, data->blksize * data->blks);
}
}
if (req->stop != RT_NULL)
{
memset(&pkg, 0, sizeof(pkg));
pkg.cmd = req->stop;
rt_hw_sdio_send_command(sdio, &pkg);
}
RT_HW_SDIO_UNLOCK(sdio);
mmcsd_req_complete(sdio->host);
}
/**
* @brief this function config sdio.
* @param host rt_mmcsd_host
* @param io_cfg rt_mmcsd_io_cfg
* @retval none
*/
static void rt_hw_sdio_iocfg(struct rt_mmcsd_host *host, struct rt_mmcsd_io_cfg *io_cfg)
{
rt_uint32_t clkcr, div, clk_src;
rt_uint32_t clk = io_cfg->clock;
struct rt_hw_sdio *sdio = host->private_data;
struct n32_sdio *hw_sdio = sdio->sdio_des.hw_sdio;
clk_src = sdio->sdio_des.clk_get(sdio->sdio_des.hw_sdio);
if (clk_src < 400 * 1000)
{
LOG_E("The clock rate is too low! rata:%d", clk_src);
return;
}
if (clk > host->freq_max)
clk = host->freq_max;
if (clk > clk_src)
{
LOG_W("Setting rate is greater than clock source rate.");
clk = clk_src;
}
LOG_D("clk:%d width:%s%s%s power:%s%s%s",
clk,
io_cfg->bus_width == MMCSD_BUS_WIDTH_8 ? "8" : "",
io_cfg->bus_width == MMCSD_BUS_WIDTH_4 ? "4" : "",
io_cfg->bus_width == MMCSD_BUS_WIDTH_1 ? "1" : "",
io_cfg->power_mode == MMCSD_POWER_OFF ? "OFF" : "",
io_cfg->power_mode == MMCSD_POWER_UP ? "UP" : "",
io_cfg->power_mode == MMCSD_POWER_ON ? "ON" : "");
RT_HW_SDIO_LOCK(sdio);
div = clk_src / (clk * 2);
if ((clk == 0) || (div == 0))
{
clkcr = 0;
}
else
{
if (div < 2)
{
div = 2;
}
else if (div > 0x1FF)
{
div = 0x1FF;
}
div -= 2;
clkcr = div | HW_SDIO_CLK_ENABLE;
}
if (io_cfg->bus_width == MMCSD_BUS_WIDTH_8)
{
clkcr |= HW_SDIO_BUSWIDE_8B;
}
else if (io_cfg->bus_width == MMCSD_BUS_WIDTH_4)
{
clkcr |= HW_SDIO_BUSWIDE_4B;
}
else
{
clkcr |= HW_SDIO_BUSWIDE_1B;
}
hw_sdio->clkcr = clkcr;
switch (io_cfg->power_mode)
{
case MMCSD_POWER_OFF:
hw_sdio->power = HW_SDIO_POWER_OFF;
break;
case MMCSD_POWER_UP:
hw_sdio->power = HW_SDIO_POWER_UP;
break;
case MMCSD_POWER_ON:
hw_sdio->power = HW_SDIO_POWER_ON;
break;
default:
LOG_W("unknown power_mode %d", io_cfg->power_mode);
break;
}
RT_HW_SDIO_UNLOCK(sdio);
}
/**
* @brief this function update sdio interrupt.
* @param host rt_mmcsd_host
* @param enable
* @retval none
*/
void rt_hw_sdio_irq_update(struct rt_mmcsd_host *host, rt_int32_t enable)
{
struct rt_hw_sdio *sdio = host->private_data;
struct n32_sdio *hw_sdio = sdio->sdio_des.hw_sdio;
if (enable)
{
LOG_D("enable sdio irq");
hw_sdio->mask |= HW_SDIO_IT_SDIOIT;
}
else
{
LOG_D("disable sdio irq");
hw_sdio->mask &= ~HW_SDIO_IT_SDIOIT;
}
}
/**
* @brief this function delect sdcard.
* @param host rt_mmcsd_host
* @retval 0x01
*/
static rt_int32_t rt_hw_sd_delect(struct rt_mmcsd_host *host)
{
LOG_D("try to detect device");
return 0x01;
}
/**
* @brief Handle SDIO error interrupt
* @param hw_sdio Pointer to SDIO hardware structure
* @retval 1 - Completed, 0 - Not completed
*/
static int handle_sdio_error(struct n32_sdio *hw_sdio)
{
hw_sdio->icr = HW_SDIO_ERRORS;
return 1;
}
/**
* @brief Handle command response end interrupt
* @param sdio Pointer to SDIO device structure
* @param hw_sdio Pointer to SDIO hardware structure
* @retval 1 - Completed, 0 - Not completed
*/
static int handle_cmdrend(struct rt_hw_sdio *sdio, struct n32_sdio *hw_sdio)
{
hw_sdio->icr = HW_SDIO_IT_CMDREND;
if (sdio->pkg != RT_NULL)
{
if (!sdio->pkg->cmd->data)
{
return 1;
}
else if ((sdio->pkg->cmd->data->flags & DATA_DIR_WRITE))
{
hw_sdio->dctrl |= HW_SDIO_DPSM_ENABLE;
}
}
return 0;
}
/**
* @brief Handle command transmission complete interrupt
* @param sdio Pointer to SDIO device structure
* @retval 1 - indicates completion, 0 - indicates not completed
*/
static int handle_cmdsent(struct rt_hw_sdio *sdio)
{
if (resp_type(sdio->pkg->cmd) == RESP_NONE)
{
return 1;
}
return 0;
}
/**
* @brief Handle data transfer complete interrupt
* @retval 1 - indicates completion
*/
static int handle_dataend(void)
{
return 1;
}
/**
* @brief Handle SDIO interrupt
* @param host Pointer to SDIO host structure
* @param hw_sdio Pointer to SDIO hardware structure
* @retval none
*/
static void handle_sdioit(struct rt_mmcsd_host *host, struct n32_sdio *hw_sdio)
{
hw_sdio->icr = HW_SDIO_IT_SDIOIT;
sdio_irq_wakeup(host);
}
/**
* @brief this function interrupt process function.
* @param host rt_mmcsd_host
* @retval none
*/
void rt_hw_sdio_irq_process(struct rt_mmcsd_host *host)
{
int complete = 0;
struct rt_hw_sdio *sdio = host->private_data;
struct n32_sdio *hw_sdio = sdio->sdio_des.hw_sdio;
rt_uint32_t intstatus = hw_sdio->sta;
if (intstatus & HW_SDIO_ERRORS)
{
complete = handle_sdio_error(hw_sdio);
}
else
{
if (intstatus & HW_SDIO_IT_CMDREND)
{
complete = handle_cmdrend(sdio, hw_sdio);
}
if (intstatus & HW_SDIO_IT_CMDSENT)
{
hw_sdio->icr = HW_SDIO_IT_CMDSENT;
if (handle_cmdsent(sdio))
{
complete = 1;
}
}
if (intstatus & HW_SDIO_IT_DATAEND)
{
hw_sdio->icr = HW_SDIO_IT_DATAEND;
complete = handle_dataend();
}
}
if ((intstatus & HW_SDIO_IT_SDIOIT) && (hw_sdio->mask & HW_SDIO_IT_SDIOIT))
{
handle_sdioit(host, hw_sdio);
}
if (complete)
{
hw_sdio->mask &= ~HW_SDIO_ERRORS;
rt_event_send(&sdio->event, intstatus);
}
}
static const struct rt_mmcsd_host_ops ops = {
rt_hw_sdio_request,
rt_hw_sdio_iocfg,
rt_hw_sd_delect,
rt_hw_sdio_irq_update,
};
/**
* @brief this function create mmcsd host.
* @param sdio_des n32_sdio_des
* @retval rt_mmcsd_host
*/
struct rt_mmcsd_host *sdio_host_create(struct n32_sdio_des *sdio_des)
{
struct rt_mmcsd_host *host;
struct rt_hw_sdio *sdio = RT_NULL;
if ((sdio_des == RT_NULL) || (sdio_des->txconfig == RT_NULL) || (sdio_des->rxconfig == RT_NULL))
{
LOG_E("L:%d F:%s %s %s %s",
(sdio_des == RT_NULL ? "sdio_des is NULL" : ""),
(sdio_des ? (sdio_des->txconfig ? "txconfig is NULL" : "") : ""),
(sdio_des ? (sdio_des->rxconfig ? "rxconfig is NULL" : "") : ""));
return RT_NULL;
}
sdio = rt_malloc(sizeof(struct rt_hw_sdio));
if (sdio == RT_NULL)
{
LOG_E("L:%d F:%s malloc rt_hw_sdio fail");
return RT_NULL;
}
rt_memset(sdio, 0, sizeof(struct rt_hw_sdio));
host = mmcsd_alloc_host();
if (host == RT_NULL)
{
LOG_E("L:%d F:%s mmcsd alloc host fail");
rt_free(sdio);
return RT_NULL;
}
rt_memcpy(&sdio->sdio_des, sdio_des, sizeof(struct n32_sdio_des));
sdio->sdio_des.hw_sdio = (sdio_des->hw_sdio == RT_NULL ? (struct n32_sdio *)SDIO_BASE_ADDRESS : sdio_des->hw_sdio);
sdio->sdio_des.clk_get = (sdio_des->clk_get == RT_NULL ? n32_sdio_clk_get : sdio_des->clk_get);
rt_event_init(&sdio->event, "sdio", RT_IPC_FLAG_FIFO);
rt_mutex_init(&sdio->mutex, "sdio", RT_IPC_FLAG_PRIO);
/* set host defautl attributes */
host->ops = &ops;
host->freq_min = 400 * 1000;
host->freq_max = SDIO_MAX_FREQ;
host->valid_ocr = 0X00FFFF80;/* the voltage range supported is 1.65v-3.6v */
#ifndef SDIO_USING_1_BIT
host->flags = MMCSD_BUSWIDTH_4 | MMCSD_MUTBLKWRITE | MMCSD_SUP_SDIO_IRQ;
#else
host->flags = MMCSD_MUTBLKWRITE | MMCSD_SUP_SDIO_IRQ;
#endif
host->max_seg_size = SDIO_BUFF_SIZE;
host->max_dma_segs = 1;
host->max_blk_size = 512;
host->max_blk_count = 512;
/* link up host and sdio */
sdio->host = host;
host->private_data = sdio;
rt_hw_sdio_irq_update(host, 1);
/* ready to change */
mmcsd_change(host);
return host;
}
/**
* @brief this function configures the dmatx.
* @param src: pointer to the source buffer
* @param dst: pointer to the destination buffer
* @param buffer_size: size of tx buffer
* @retval none
*/
void sd_lowlevel_dmatx_config(uint32_t *src, uint32_t *dst, uint32_t buffer_size)
{
sdio_obj.cfg = &sdio_config;
DMA_StructInit(&sdio_obj.dma.handle_tx);
/*!< DMA2 Channel2 disable */
DMA_EnableChannel(sdio_config.dma_tx.DMAChx, DISABLE);
DMA_DeInit(sdio_config.dma_tx.DMAChx);
/*!< DMA2 Channel2 Config */
sdio_obj.dma.handle_tx.PeriphAddr = (uint32_t)dst;
sdio_obj.dma.handle_tx.MemAddr = (uint32_t)src;
sdio_obj.dma.handle_tx.Direction = DMA_DIR_PERIPH_DST;
sdio_obj.dma.handle_tx.BufSize = buffer_size;
sdio_obj.dma.handle_tx.PeriphInc = DMA_PERIPH_INC_DISABLE;
sdio_obj.dma.handle_tx.MemoryInc = DMA_MEM_INC_ENABLE;
sdio_obj.dma.handle_tx.PeriphDataSize = DMA_PERIPH_DATA_WIDTH_WORD;
sdio_obj.dma.handle_tx.MemDataSize = DMA_MEM_DATA_WIDTH_WORD;
sdio_obj.dma.handle_tx.CircularMode = DMA_MODE_NORMAL;
sdio_obj.dma.handle_tx.Priority = DMA_PRIORITY_HIGH;
sdio_obj.dma.handle_tx.Mem2Mem = DMA_M2M_DISABLE;
DMA_Init(sdio_config.dma_tx.DMAChx, &sdio_obj.dma.handle_tx);
/* DMA channel remap */
DMA_RequestRemap(sdio_config.dma_tx.request, sdio_config.dma_tx.DMAChx, ENABLE);
/*!< SDIO DMA TX Channel enable */
DMA_EnableChannel(sdio_config.dma_tx.DMAChx, ENABLE);
}
/**
* @brief this function configures the dmarx.
* @param src: pointer to the source buffer
* @param dst: pointer to the destination buffer
* @param buffer_size: size of rx buffer
* @retval none
*/
void sd_lowlevel_dmarx_config(uint32_t *src, uint32_t *dst, uint32_t buffer_size)
{
sdio_obj.cfg = &sdio_config;
DMA_StructInit(&sdio_obj.dma.handle_rx);
/*!< DMA2 Channel2 disable */
DMA_EnableChannel(sdio_config.dma_rx.DMAChx, DISABLE);
DMA_DeInit(sdio_config.dma_rx.DMAChx);
/*!< DMA2 Channel2 Config */
sdio_obj.dma.handle_rx.PeriphAddr = (uint32_t)src;
sdio_obj.dma.handle_rx.MemAddr = (uint32_t)dst;
sdio_obj.dma.handle_rx.Direction = DMA_DIR_PERIPH_SRC;
sdio_obj.dma.handle_rx.BufSize = buffer_size;
sdio_obj.dma.handle_rx.PeriphInc = DMA_PERIPH_INC_DISABLE;
sdio_obj.dma.handle_rx.MemoryInc = DMA_MEM_INC_ENABLE;
sdio_obj.dma.handle_rx.PeriphDataSize = DMA_PERIPH_DATA_WIDTH_WORD;
sdio_obj.dma.handle_rx.MemDataSize = DMA_MEM_DATA_WIDTH_WORD;
sdio_obj.dma.handle_rx.CircularMode = DMA_MODE_NORMAL;
sdio_obj.dma.handle_rx.Priority = DMA_PRIORITY_HIGH;
sdio_obj.dma.handle_rx.Mem2Mem = DMA_M2M_DISABLE;
DMA_Init(sdio_config.dma_rx.DMAChx, &sdio_obj.dma.handle_rx);
/* DMA channel remap */
DMA_RequestRemap(sdio_config.dma_rx.request, sdio_config.dma_rx.DMAChx, ENABLE);
/*!< SDIO DMA RX Channel enable */
DMA_EnableChannel(sdio_config.dma_rx.DMAChx, ENABLE);
}
/**
* @brief this function get n32 sdio clock.
* @param hw_sdio: n32_sdio
* @retval ahb frequency
*/
static rt_uint32_t n32_sdio_clock_get(struct n32_sdio *hw_sdio)
{
RCC_ClocksType RCC_Clocks;
RCC_GetClocksFreqValue(&RCC_Clocks);
return RCC_Clocks.HclkFreq;
}
static rt_err_t dma_tx_config(rt_uint32_t *src, rt_uint32_t *dst, int size)
{
sd_lowlevel_dmatx_config((uint32_t *)src, (uint32_t *)dst, size / 4);
return RT_EOK;
}
static rt_err_t dma_rx_config(rt_uint32_t *src, rt_uint32_t *dst, int size)
{
sd_lowlevel_dmarx_config((uint32_t *)src, (uint32_t *)dst, size / 4);
return RT_EOK;
}
void SDIO_IRQHandler(void)
{
/* enter interrupt */
rt_interrupt_enter();
rt_hw_sdio_irq_process(host);
/* leave interrupt */
rt_interrupt_leave();
}
int rt_hw_sdio_init(void)
{
struct n32_sdio_des sdio_des;
/* Enable DMA clock */
RCC_EnableAHBPeriphClk(sdio_config.dma_tx.dma_rcc | sdio_config.dma_rx.dma_rcc, ENABLE);
uint32_t group = NVIC_GetPriorityGrouping();
rt_kprintf("Current Priority Group: %lu\n", group);
NVIC_SetPriority(SDIO_IRQn, NVIC_EncodePriority(NVIC_GetPriorityGrouping(), 1, 0));
NVIC_EnableIRQ(SDIO_IRQn);
sdio_des.clk_get = n32_sdio_clock_get;
sdio_des.hw_sdio = (struct n32_sdio *)SDCARD_INSTANCE;
sdio_des.rxconfig = dma_rx_config;
sdio_des.txconfig = dma_tx_config;
host = sdio_host_create(&sdio_des);
if (host == RT_NULL)
{
LOG_E("host create fail");
return -1;
}
return 0;
}
INIT_DEVICE_EXPORT(rt_hw_sdio_init);
void n32_mmcsd_change(void)
{
mmcsd_change(host);
}
#endif

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bsp/n32/n32hxxx/libraries/N32_Drivers/drivers/drv_sdio.h Normal file
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/*
* Copyright (c) 2006-2025, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2026-06-28 ox-horse first version
*/
#ifndef _DRV_SDIO_H
#define _DRV_SDIO_H
#include <rtthread.h>
#include "rtdevice.h"
#include <rthw.h>
#include <string.h>
#include "drv_dma.h"
#include "drv_config.h"
#define SDCARD_INSTANCE_TYPE SDIO_Module
#define SDCARD_INSTANCE SDIO
#define SDIO_BUFF_SIZE 4096
#define SDIO_ALIGN_LEN 32
#ifndef SDIO_MAX_FREQ
#define SDIO_MAX_FREQ (12 * 1000 * 1000)
#endif
#ifndef SDIO_BASE_ADDRESS
#define SDIO_BASE_ADDRESS SDIO_BASE
#endif
#ifndef SDIO_CLOCK_FREQ
#define SDIO_CLOCK_FREQ (48U * 1000 * 1000)
#endif
#ifndef SDIO_BUFF_SIZE
#define SDIO_BUFF_SIZE (4096)
#endif
#ifndef SDIO_ALIGN_LEN
#define SDIO_ALIGN_LEN (32)
#endif
#ifndef SDIO_MAX_FREQ
#define SDIO_MAX_FREQ (24 * 1000 * 1000)
#endif
#define HW_SDIO_IT_CCRCFAIL (0x01U << 0)
#define HW_SDIO_IT_DCRCFAIL (0x01U << 1)
#define HW_SDIO_IT_CTIMEOUT (0x01U << 2)
#define HW_SDIO_IT_DTIMEOUT (0x01U << 3)
#define HW_SDIO_IT_TXUNDERR (0x01U << 4)
#define HW_SDIO_IT_RXOVERR (0x01U << 5)
#define HW_SDIO_IT_CMDREND (0x01U << 6)
#define HW_SDIO_IT_CMDSENT (0x01U << 7)
#define HW_SDIO_IT_DATAEND (0x01U << 8)
#define HW_SDIO_IT_STBITERR (0x01U << 9)
#define HW_SDIO_IT_DBCKEND (0x01U << 10)
#define HW_SDIO_IT_CMDACT (0x01U << 11)
#define HW_SDIO_IT_TXACT (0x01U << 12)
#define HW_SDIO_IT_RXACT (0x01U << 13)
#define HW_SDIO_IT_TXFIFOHE (0x01U << 14)
#define HW_SDIO_IT_RXFIFOHF (0x01U << 15)
#define HW_SDIO_IT_TXFIFOF (0x01U << 16)
#define HW_SDIO_IT_RXFIFOF (0x01U << 17)
#define HW_SDIO_IT_TXFIFOE (0x01U << 18)
#define HW_SDIO_IT_RXFIFOE (0x01U << 19)
#define HW_SDIO_IT_TXDAVL (0x01U << 20)
#define HW_SDIO_IT_RXDAVL (0x01U << 21)
#define HW_SDIO_IT_SDIOIT (0x01U << 22)
#define HW_SDIO_ERRORS \
(HW_SDIO_IT_CCRCFAIL | HW_SDIO_IT_CTIMEOUT | \
HW_SDIO_IT_DCRCFAIL | HW_SDIO_IT_DTIMEOUT | \
HW_SDIO_IT_RXOVERR | HW_SDIO_IT_TXUNDERR)
#define HW_SDIO_POWER_OFF (0x00U)
#define HW_SDIO_POWER_UP (0x02U)
#define HW_SDIO_POWER_ON (0x03U)
#define HW_SDIO_FLOW_ENABLE (0x01U << 14)
#define HW_SDIO_BUSWIDE_1B (0x00U << 11)
#define HW_SDIO_BUSWIDE_4B (0x01U << 11)
#define HW_SDIO_BUSWIDE_8B (0x02U << 11)
#define HW_SDIO_BYPASS_ENABLE (0x01U << 10)
#define HW_SDIO_IDLE_ENABLE (0x01U << 9)
#define HW_SDIO_CLK_ENABLE (0x01U << 13)
#define HW_SDIO_SUSPEND_CMD (0x01U << 11)
#define HW_SDIO_CPSM_ENABLE (0x01U << 0)
#define HW_SDIO_WAIT_END (0x01U << 9)
#define HW_SDIO_WAIT_INT (0x01U << 8)
#define HW_SDIO_RESPONSE_NO (0x00U << 14)
#define HW_SDIO_RESPONSE_SHORT (0x01U << 14)
#define HW_SDIO_RESPONSE_LONG (0x03U << 14)
#define HW_SDIO_DATA_LEN_MASK (0x01FFFFFFU)
#define HW_SDIO_IO_ENABLE (0x01U << 11)
#define HW_SDIO_RWMOD_CK (0x01U << 10)
#define HW_SDIO_RWSTOP_ENABLE (0x01U << 9)
#define HW_SDIO_RWSTART_ENABLE (0x01U << 8)
#define HW_SDIO_DBLOCKSIZE_1 (0x00U << 4)
#define HW_SDIO_DBLOCKSIZE_2 (0x01U << 4)
#define HW_SDIO_DBLOCKSIZE_4 (0x02U << 4)
#define HW_SDIO_DBLOCKSIZE_8 (0x03U << 4)
#define HW_SDIO_DBLOCKSIZE_16 (0x04U << 4)
#define HW_SDIO_DBLOCKSIZE_32 (0x05U << 4)
#define HW_SDIO_DBLOCKSIZE_64 (0x06U << 4)
#define HW_SDIO_DBLOCKSIZE_128 (0x07U << 4)
#define HW_SDIO_DBLOCKSIZE_256 (0x08U << 4)
#define HW_SDIO_DBLOCKSIZE_512 (0x09U << 4)
#define HW_SDIO_DBLOCKSIZE_1024 (0x0AU << 4)
#define HW_SDIO_DBLOCKSIZE_2048 (0x0BU << 4)
#define HW_SDIO_DBLOCKSIZE_4096 (0x0CU << 4)
#define HW_SDIO_DBLOCKSIZE_8192 (0x0DU << 4)
#define HW_SDIO_DBLOCKSIZE_16384 (0x0EU << 4)
#define HW_SDIO_DMA_ENABLE (0x01U << 3)
#define HW_SDIO_STREAM_ENABLE (0x01U << 2)
#define HW_SDIO_TO_HOST (0x01U << 2)
#define HW_SDIO_DPSM_ENABLE (0x01U << 0)
#define HW_SDIO_DATATIMEOUT (0xF0000000U)
struct n32_sdio
{
volatile rt_uint32_t power;
volatile rt_uint32_t clkcr;
volatile rt_uint32_t arg;
volatile rt_uint32_t cmd;
volatile rt_uint32_t respcmd;
volatile rt_uint32_t resp1;
volatile rt_uint32_t resp2;
volatile rt_uint32_t resp3;
volatile rt_uint32_t resp4;
volatile rt_uint32_t dtimer;
volatile rt_uint32_t dlen;
volatile rt_uint32_t dctrl;
volatile rt_uint32_t dcount;
volatile rt_uint32_t sta;
volatile rt_uint32_t icr;
volatile rt_uint32_t mask;
volatile rt_uint32_t reserved0[2];
volatile rt_uint32_t fifocnt;
volatile rt_uint32_t reserved1[13];
volatile rt_uint32_t fifo;
};
typedef rt_err_t (*dma_txconfig)(rt_uint32_t *src, rt_uint32_t *dst, int size);
typedef rt_err_t (*dma_rxconfig)(rt_uint32_t *src, rt_uint32_t *dst, int size);
typedef rt_uint32_t (*sdio_clk_get)(struct n32_sdio *hw_sdio);
struct n32_sdio_des
{
struct n32_sdio *hw_sdio;
dma_txconfig txconfig;
dma_rxconfig rxconfig;
sdio_clk_get clk_get;
};
struct n32_sdio_config
{
SDCARD_INSTANCE_TYPE *sdio_x;
struct dma_config dma_rx, dma_tx;
};
/* n32 sdio dirver class */
struct n32_sdio_class
{
struct n32_sdio_des *des;
const struct n32_sdio_config *cfg;
struct rt_mmcsd_host host;
struct
{
DMA_InitType handle_rx;
DMA_InitType handle_tx;
} dma;
};
extern void n32_mmcsd_change(void);
#if defined(BSP_USING_SDIO)
#ifndef SDIO_BUS_CONFIG
#define SDIO_BUS_CONFIG \
{ \
.sdio_x = SDIO, \
.dma_rx = { \
.DMAy = SDIO_RX_DMA, \
.DMAChx = SDIO_TX_DMA_CHType, \
.dma_irq = SDIO_TX_DMA_IRQ, \
.dma_rcc = SDIO_TX_DMA_RCC, \
.request = SDIO_TX_DMA_REQUEST, \
.channel = SDIO_TX_DMA_CHANNEL \
}, \
.dma_tx = { \
.DMAy = SDIO_TX_DMA, \
.DMAChx = SDIO_RX_DMA_CHType, \
.dma_irq = SDIO_RX_DMA_IRQ, \
.dma_rcc = SDIO_RX_DMA_RCC, \
.request = SDIO_RX_DMA_REQUEST, \
.channel = SDIO_RX_DMA_CHANNEL \
} \
}
#endif
#endif /* SDIO_BUS_CONFIG */
#endif

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bsp/n32/n32hxxx/libraries/N32_Drivers/drivers/drv_tim.c Normal file
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/*
* Copyright (c) 2006-2025, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2026-02-26 ox-horse first version
*/
#include <rtdevice.h>
#include "drv_config.h"
//#define DRV_DEBUG
#define LOG_TAG "drv.tim"
#include <drv_log.h>
#if defined(BSP_USING_ATIM1) && !defined(ATIM1)
#error "A-timer1 doesn't exist in this N32 series, but you enabled the BSP_USING_ATIM1"
#endif
#if defined(BSP_USING_ATIM2) && !defined(ATIM2)
#error "A-timer2 doesn't exist in this N32 series, but you enabled the BSP_USING_ATIM2"
#endif
#if defined(BSP_USING_ATIM3) && !defined(ATIM3)
#error "A-timer3 doesn't exist in this N32 series, but you enabled the BSP_USING_ATIM3"
#endif
#if defined(BSP_USING_ATIM4) && !defined(ATIM4)
#error "A-timer4 doesn't exist in this N32 series, but you enabled the BSP_USING_ATIM4"
#endif
#if defined(BSP_USING_GTIMA1) && !defined(GTIMA1)
#error "G-timer-A1 doesn't exist in this N32 series, but you enabled the BSP_USING_GTIMA1"
#endif
#if defined(BSP_USING_GTIMA2) && !defined(GTIMA2)
#error "G-timer-A2 doesn't exist in this N32 series, but you enabled the BSP_USING_GTIMA2"
#endif
#if defined(BSP_USING_GTIMA3) && !defined(GTIMA3)
#error "G-timer-A3 doesn't exist in this N32 series, but you enabled the BSP_USING_GTIMA3"
#endif
#if defined(BSP_USING_GTIMA4) && !defined(GTIMA4)
#error "G-timer-A4 doesn't exist in this N32 series, but you enabled the BSP_USING_GTIMA4"
#endif
#if defined(BSP_USING_GTIMA5) && !defined(GTIMA5)
#error "G-timer-A5 doesn't exist in this N32 series, but you enabled the BSP_USING_GTIMA5"
#endif
#if defined(BSP_USING_GTIMA6) && !defined(GTIMA6)
#error "G-timer-A6 doesn't exist in this N32 series, but you enabled the BSP_USING_GTIMA6"
#endif
#if defined(BSP_USING_GTIMA7) && !defined(GTIMA7)
#error "G-timer-A7 doesn't exist in this N32 series, but you enabled the BSP_USING_GTIMA7"
#endif
#if defined(BSP_USING_GTIMB1) && !defined(GTIMB1)
#error "G-timer-B1 doesn't exist in this N32 series, but you enabled the BSP_USING_GTIMB1"
#endif
#if defined(BSP_USING_GTIMB2) && !defined(GTIMB2)
#error "G-timer-B2 doesn't exist in this N32 series, but you enabled the BSP_USING_GTIMB2"
#endif
#if defined(BSP_USING_GTIMB3) && !defined(GTIMB3)
#error "G-timer-B3 doesn't exist in this N32 series, but you enabled the BSP_USING_GTIMB3"
#endif
#if defined(BSP_USING_BTIM1) && !defined(BTIM1)
#error "B-timer1 doesn't exist in this N32 series, but you enabled the BSP_USING_BTIM1"
#endif
#if defined(BSP_USING_BTIM2) && !defined(BTIM2)
#error "B-timer2 doesn't exist in this N32 series, but you enabled the BSP_USING_BTIM2"
#endif
#if defined(BSP_USING_BTIM3) && !defined(BTIM3)
#error "B-timer3 doesn't exist in this N32 series, but you enabled the BSP_USING_BTIM3"
#endif
#if defined(BSP_USING_BTIM4) && !defined(BTIM4)
#error "B-timer4 doesn't exist in this N32 series, but you enabled the BSP_USING_BTIM4"
#endif
#define INT_MAX (0x7FFFFFFF)
static int int_pow(int x, int y)
{
if (y == 0)
return 1;
if (x == 0)
{
if (y > 0)
return 0;
else
return -1;
}
if (y < 0)
return -1;
int result = 1;
int base = x;
int exponent = y;
/* Fast exponentiation algorithm (binary exponentiation) */
while (exponent > 0)
{
/* Check for overflow */
if (result > INT_MAX / base)
return -1;
if (exponent % 2 == 1)
result *= base;
exponent /= 2;
if (exponent > 0)
{
if (base > INT_MAX / base)
return -1;
base *= base;
}
}
return result;
}
void n32_tim_ahbx_div_get(TIM_Module *timer, rt_uint32_t *div)
{
RT_ASSERT(timer != RT_NULL);
RT_ASSERT(div != RT_NULL);
*div = 1;
#if defined(SOC_SERIES_N32H7xx)
rt_uint8_t tim_div, i;
const rt_uint8_t div_group[] = { 0x00U, 0x04U, 0x05U, 0x06U, 0x07U };
if ((timer == BTIM1) || (timer == BTIM2) || (timer == BTIM3) || (timer == BTIM4))
{
tim_div = ((RCC->APB1DIV1 & RCC_APB1DIV1_APB1BTIMDIV) >> 24U);
}
else if ((timer == ATIM1) || (timer == ATIM2))
{
tim_div = ((RCC->APB2DIV1 & RCC_APB2DIV1_APB2ATIMDIV) >> 28U);
}
else if ((timer == ATIM3) || (timer == ATIM4))
{
tim_div = ((RCC->APB5DIV1 & RCC_APB5DIV1_APB5ATIMDIV) >> 28U);
}
else if ((timer == GTIMA1) || (timer == GTIMA2) || (timer == GTIMA3))
{
tim_div = ((RCC->APB2DIV1 & RCC_APB2DIV1_APB2GTIMDIV) >> 24U);
}
else
{
tim_div = ((RCC->APB1DIV1 & RCC_APB1DIV1_APB1GTIMDIV) >> 16U);
}
for (i = 0; i < 5U; i++)
{
if (div_group[i] == tim_div)
{
*div = int_pow(2, i);
break;
}
}
#endif /* defined(SOC_SERIES_N32H7xx) */
}
void n32_tim_enable_clock(TIM_Module *timer)
{
RT_ASSERT(timer != RT_NULL);
if (RT_FALSE)
;
#ifdef ATIM1
else if (timer == ATIM1)
{
RCC_EnableAPB2PeriphClk1(RCC_APB2_PERIPHEN_M7_ATIM1 | RCC_APB2_PERIPHEN_M4_ATIM1 | RCC_APB2_PERIPHEN_M7_ATIM1LP | RCC_APB2_PERIPHEN_M4_ATIM1LP, ENABLE);
}
#endif /* ATIM1 */
#ifdef ATIM2
else if (timer == ATIM2)
{
RCC_EnableAPB2PeriphClk1(RCC_APB2_PERIPHEN_M7_ATIM2 | RCC_APB2_PERIPHEN_M4_ATIM2 | RCC_APB2_PERIPHEN_M7_ATIM2LP | RCC_APB2_PERIPHEN_M4_ATIM2LP, ENABLE);
}
#endif /* ATIM2 */
#ifdef ATIM3
else if (timer == ATIM3)
{
RCC_EnableAPB5PeriphClk1(RCC_APB5_PERIPHEN_M7_ATIM3 | RCC_APB5_PERIPHEN_M4_ATIM3 | RCC_APB5_PERIPHEN_M7_ATIM3LP | RCC_APB5_PERIPHEN_M4_ATIM3LP, ENABLE);
}
#endif /* ATIM3 */
#ifdef ATIM4
else if (timer == ATIM4)
{
RCC_EnableAPB5PeriphClk1(RCC_APB5_PERIPHEN_M7_ATIM4 | RCC_APB5_PERIPHEN_M4_ATIM4 | RCC_APB5_PERIPHEN_M7_ATIM4LP | RCC_APB5_PERIPHEN_M4_ATIM4LP, ENABLE);
}
#endif /* ATIM4 */
#ifdef GTIMA1
else if (timer == GTIMA1)
{
RCC_EnableAPB2PeriphClk1(RCC_APB2_PERIPHEN_M7_GTIMA1 | RCC_APB2_PERIPHEN_M4_GTIMA1 | RCC_APB2_PERIPHEN_M7_GTIMA1LP | RCC_APB2_PERIPHEN_M4_GTIMA1LP, ENABLE);
}
#endif /* GTIMA1 */
#ifdef GTIMA2
else if (timer == GTIMA2)
{
RCC_EnableAPB2PeriphClk1(RCC_APB2_PERIPHEN_M7_GTIMA2 | RCC_APB2_PERIPHEN_M4_GTIMA2 | RCC_APB2_PERIPHEN_M7_GTIMA2LP | RCC_APB2_PERIPHEN_M4_GTIMA2LP, ENABLE);
}
#endif /* GTIMA2 */
#ifdef GTIMA3
else if (timer == GTIMA3)
{
RCC_EnableAPB2PeriphClk1(RCC_APB2_PERIPHEN_M7_GTIMA3 | RCC_APB2_PERIPHEN_M4_GTIMA3 | RCC_APB2_PERIPHEN_M7_GTIMA3LP | RCC_APB2_PERIPHEN_M4_GTIMA3LP, ENABLE);
}
#endif /* GTIMA3 */
#ifdef GTIMA4
else if (timer == GTIMA4)
{
RCC_EnableAPB1PeriphClk1(RCC_APB1_PERIPHEN_M7_GTIMA4 | RCC_APB1_PERIPHEN_M4_GTIMA4 | RCC_APB1_PERIPHEN_M7_GTIMA4LP | RCC_APB1_PERIPHEN_M4_GTIMA4LP, ENABLE);
}
#endif /* GTIMA4 */
#ifdef GTIMA5
else if (timer == GTIMA5)
{
RCC_EnableAPB1PeriphClk2(RCC_APB1_PERIPHEN_M7_GTIMA5 | RCC_APB1_PERIPHEN_M4_GTIMA5 | RCC_APB1_PERIPHEN_M7_GTIMA5LP | RCC_APB1_PERIPHEN_M4_GTIMA5LP, ENABLE);
}
#endif /* GTIMA5 */
#ifdef GTIMA6
else if (timer == GTIMA6)
{
RCC_EnableAPB1PeriphClk2(RCC_APB1_PERIPHEN_M7_GTIMA6 | RCC_APB1_PERIPHEN_M4_GTIMA6 | RCC_APB1_PERIPHEN_M7_GTIMA6LP | RCC_APB1_PERIPHEN_M4_GTIMA6LP, ENABLE);
}
#endif /* GTIMA6 */
#ifdef GTIMA7
else if (timer == GTIMA7)
{
RCC_EnableAPB1PeriphClk2(RCC_APB1_PERIPHEN_M7_GTIMA7 | RCC_APB1_PERIPHEN_M4_GTIMA7 | RCC_APB1_PERIPHEN_M7_GTIMA7LP | RCC_APB1_PERIPHEN_M4_GTIMA7LP, ENABLE);
}
#endif /* GTIMA7 */
#ifdef GTIMB1
else if (timer == GTIMB1)
{
RCC_EnableAPB1PeriphClk1(RCC_APB1_PERIPHEN_M7_GTIMB1 | RCC_APB1_PERIPHEN_M4_GTIMB1 | RCC_APB1_PERIPHEN_M7_GTIMB1LP | RCC_APB1_PERIPHEN_M4_GTIMB1LP, ENABLE);
}
#endif /* GTIMB1 */
#ifdef GTIMB2
else if (timer == GTIMB2)
{
RCC_EnableAPB1PeriphClk1(RCC_APB1_PERIPHEN_M7_GTIMB2 | RCC_APB1_PERIPHEN_M4_GTIMB2 | RCC_APB1_PERIPHEN_M7_GTIMB2LP | RCC_APB1_PERIPHEN_M4_GTIMB2LP, ENABLE);
}
#endif /* GTIMB2 */
#ifdef GTIMB3
else if (timer == GTIMB3)
{
RCC_EnableAPB1PeriphClk1(RCC_APB1_PERIPHEN_M7_GTIMB3 | RCC_APB1_PERIPHEN_M4_GTIMB3 | RCC_APB1_PERIPHEN_M7_GTIMB3LP | RCC_APB1_PERIPHEN_M4_GTIMB3LP, ENABLE);
}
#endif /* GTIMB3 */
#ifdef BTIM1
else if (timer == BTIM1)
{
RCC_EnableAPB1PeriphClk1(RCC_APB1_PERIPHEN_M7_BTIM1 | RCC_APB1_PERIPHEN_M4_BTIM1 | RCC_APB1_PERIPHEN_M7_BTIM1LP | RCC_APB1_PERIPHEN_M4_BTIM1LP, ENABLE);
}
#endif /* BTIM1 */
#ifdef BTIM2
else if (timer == BTIM2)
{
RCC_EnableAPB1PeriphClk1(RCC_APB1_PERIPHEN_M7_BTIM2 | RCC_APB1_PERIPHEN_M4_BTIM2 | RCC_APB1_PERIPHEN_M7_BTIM2LP | RCC_APB1_PERIPHEN_M4_BTIM2LP, ENABLE);
}
#endif /* BTIM2 */
#ifdef BTIM3
else if (timer == BTIM3)
{
RCC_EnableAPB1PeriphClk1(RCC_APB1_PERIPHEN_M7_BTIM3 | RCC_APB1_PERIPHEN_M4_BTIM3 | RCC_APB1_PERIPHEN_M7_BTIM3LP | RCC_APB1_PERIPHEN_M4_BTIM3LP, ENABLE);
}
#endif /* BTIM3 */
#ifdef BTIM4
else if (timer == BTIM4)
{
RCC_EnableAPB1PeriphClk1(RCC_APB1_PERIPHEN_M7_BTIM4 | RCC_APB1_PERIPHEN_M4_BTIM4 | RCC_APB1_PERIPHEN_M7_BTIM4LP | RCC_APB1_PERIPHEN_M4_BTIM4LP, ENABLE);
}
#endif /* BTIM4 */
else
{
RT_ASSERT(RT_TRUE);
}
}
#ifdef BSP_USING_CLOCK_TIMER
enum
{
#ifdef BSP_USING_ATIM1
TIM1_INDEX,
#endif
#ifdef BSP_USING_ATIM2
TIM2_INDEX,
#endif
#ifdef BSP_USING_ATIM3
TIM3_INDEX,
#endif
#ifdef BSP_USING_ATIM4
TIM4_INDEX,
#endif
#ifdef BSP_USING_GTIMA1
TIM5_INDEX,
#endif
#ifdef BSP_USING_GTIMA2
TIM6_INDEX,
#endif
#ifdef BSP_USING_GTIMA3
TIM7_INDEX,
#endif
#ifdef BSP_USING_GTIMA4
TIM8_INDEX,
#endif
#ifdef BSP_USING_GTIMA5
TIM9_INDEX,
#endif
#ifdef BSP_USING_GTIMA6
TIM10_INDEX,
#endif
#ifdef BSP_USING_GTIMA7
TIM11_INDEX,
#endif
#ifdef BSP_USING_GTIMB1
TIM12_INDEX,
#endif
#ifdef BSP_USING_GTIMB2
TIM13_INDEX,
#endif
#ifdef BSP_USING_GTIMB3
TIM14_INDEX,
#endif
#ifdef BSP_USING_BTIM1
TIM15_INDEX,
#endif
#ifdef BSP_USING_BTIM2
TIM16_INDEX,
#endif
#ifdef BSP_USING_BTIM3
TIM17_INDEX,
#endif
#ifdef BSP_USING_BTIM4
TIM18_INDEX,
#endif
};
struct n32_clock_timer
{
rt_clock_timer_t time_device;
TIM_Module *timer;
IRQn_Type tim_irqn;
char *name;
};
static struct n32_clock_timer n32_clock_timer_obj[] = {
#ifdef BSP_USING_ATIM1
ATIM1_CONFIG,
#endif
#ifdef BSP_USING_ATIM2
ATIM2_CONFIG,
#endif
#ifdef BSP_USING_ATIM3
ATIM3_CONFIG,
#endif
#ifdef BSP_USING_ATIM4
ATIM4_CONFIG,
#endif
#ifdef BSP_USING_GTIMA1
GTIMA1_CONFIG,
#endif
#ifdef BSP_USING_GTIMA2
GTIMA2_CONFIG,
#endif
#ifdef BSP_USING_GTIMA3
GTIMA3_CONFIG,
#endif
#ifdef BSP_USING_GTIMA4
GTIMA4_CONFIG,
#endif
#ifdef BSP_USING_GTIMA5
GTIMA5_CONFIG,
#endif
#ifdef BSP_USING_GTIMA6
GTIMA6_CONFIG,
#endif
#ifdef BSP_USING_GTIMA7
GTIMA7_CONFIG,
#endif
#ifdef BSP_USING_GTIMB1
GTIMB1_CONFIG,
#endif
#ifdef BSP_USING_GTIMB2
GTIMB2_CONFIG,
#endif
#ifdef BSP_USING_GTIMB3
GTIMB3_CONFIG,
#endif
#ifdef BSP_USING_BTIM1
BTIM1_CONFIG,
#endif
#ifdef BSP_USING_BTIM2
BTIM2_CONFIG,
#endif
#ifdef BSP_USING_BTIM3
BTIM3_CONFIG,
#endif
#ifdef BSP_USING_BTIM4
BTIM4_CONFIG,
#endif
};
static void timer_init(struct rt_clock_timer_device *timer, rt_uint32_t state)
{
uint32_t prescaler_value = 0;
rt_uint32_t tim_div;
struct n32_clock_timer *tim_device = RT_NULL;
RCC_ClocksTypeDef RCC_Clocks;
TIM_TimeBaseInitType TIM_TimeBaseStructure;
RT_ASSERT(timer != RT_NULL);
if (state)
{
tim_device = (struct n32_clock_timer *)timer;
/* time init */
#if defined(SOC_SERIES_N32H7xx)
n32_tim_ahbx_div_get(tim_device->timer, &tim_div);
RCC_GetClocksFreqValue(&RCC_Clocks);
if ((tim_device->timer == BTIM1) || (tim_device->timer == BTIM2) || (tim_device->timer == BTIM3) || (tim_device->timer == BTIM4))
{
prescaler_value = ((RCC_Clocks.AHB1ClkFreq / tim_div) / 10000U) - 1U;
}
else if ((tim_device->timer == ATIM1) || (tim_device->timer == ATIM2))
{
prescaler_value = ((RCC_Clocks.AHB2ClkFreq / tim_div) / 10000U) - 1U;
}
else if ((tim_device->timer == ATIM3) || (tim_device->timer == ATIM4))
{
prescaler_value = ((RCC_Clocks.AHB5ClkFreq / tim_div) / 10000U) - 1U;
}
else if ((tim_device->timer == GTIMA1) || (tim_device->timer == GTIMA2) || (tim_device->timer == GTIMA3))
{
prescaler_value = ((RCC_Clocks.AHB2ClkFreq / tim_div) / 10000U) - 1U;
}
else
{
prescaler_value = ((RCC_Clocks.AHB1ClkFreq / tim_div) / 10000U) - 1U;
}
#endif
/* Enable tim clock */
n32_tim_enable_clock(tim_device->timer);
TIM_InitTimBaseStruct(&TIM_TimeBaseStructure);
TIM_TimeBaseStructure.Period = 10000 - 1;
;
TIM_TimeBaseStructure.Prescaler = prescaler_value;
TIM_TimeBaseStructure.ClkDiv = TIM_CLK_DIV1;
if (timer->info->cntmode == CLOCK_TIMER_CNTMODE_UP)
{
TIM_TimeBaseStructure.CounterMode = TIM_CNT_MODE_UP;
}
else
{
TIM_TimeBaseStructure.CounterMode = TIM_CNT_MODE_DOWN;
}
TIM_InitTimeBase(tim_device->timer, &TIM_TimeBaseStructure);
/* set the TIMx priority */
NVIC_SetPriority(tim_device->tim_irqn, NVIC_EncodePriority(NVIC_GetPriorityGrouping(), 3, 0));
/* enable the TIMx Interrupt */
NVIC_EnableIRQ(tim_device->tim_irqn);
TIM_ClearFlag(tim_device->timer, TIM_FLAG_UPDATE);
LOG_D("%s init success", tim_device->name);
}
}
static rt_err_t timer_start(rt_clock_timer_t *timer, rt_uint32_t t, rt_clock_timer_mode_t opmode)
{
struct n32_clock_timer *tim_device = RT_NULL;
RT_ASSERT(timer != RT_NULL);
tim_device = (struct n32_clock_timer *)timer;
/* set tim cnt */
TIM_SetCnt(tim_device->timer, 0);
/* set tim arr */
TIM_SetAutoReload(tim_device->timer, t - 1U);
if (opmode == CLOCK_TIMER_MODE_ONESHOT)
{
/* set timer to single mode */
TIM_SelectOnePulseMode(tim_device->timer, TIM_OPMODE_SINGLE);
}
else
{
TIM_SelectOnePulseMode(tim_device->timer, TIM_OPMODE_REPET);
}
TIM_ConfigInt(tim_device->timer, TIM_INT_UPDATE, ENABLE);
TIM_Enable(tim_device->timer, ENABLE);
return RT_EOK;
}
static void timer_stop(rt_clock_timer_t *timer)
{
struct n32_clock_timer *tim_device = RT_NULL;
RT_ASSERT(timer != RT_NULL);
tim_device = (struct n32_clock_timer *)timer;
/* disable interrupt */
TIM_ConfigInt(tim_device->timer, TIM_INT_UPDATE, DISABLE);
/* stop timer */
TIM_Enable(tim_device->timer, DISABLE);
/* set tim cnt */
TIM_SetCnt(tim_device->timer, 0);
}
static rt_err_t timer_ctrl(rt_clock_timer_t *timer, rt_uint32_t cmd, void *arg)
{
struct n32_clock_timer *tim_device = RT_NULL;
rt_err_t result = -RT_ERROR;
uint32_t prescaler_value = 0;
rt_uint32_t tim_div;
RCC_ClocksTypeDef RCC_Clocks;
RT_ASSERT(timer != RT_NULL);
RT_ASSERT(arg != RT_NULL);
tim_device = (struct n32_clock_timer *)timer;
switch (cmd)
{
case CLOCK_TIMER_CTRL_FREQ_SET:
{
rt_uint32_t freq;
/* set timer frequence */
freq = *((rt_uint32_t *)arg);
#if defined(SOC_SERIES_N32H7xx)
n32_tim_ahbx_div_get(tim_device->timer, &tim_div);
RCC_GetClocksFreqValue(&RCC_Clocks);
if ((tim_device->timer == BTIM1) || (tim_device->timer == BTIM2) || (tim_device->timer == BTIM3) || (tim_device->timer == BTIM4))
{
prescaler_value = ((RCC_Clocks.AHB1ClkFreq / tim_div) / freq) - 1U;
}
else if ((tim_device->timer == ATIM1) || (tim_device->timer == ATIM2))
{
prescaler_value = ((RCC_Clocks.AHB2ClkFreq / tim_div) / freq) - 1U;
}
else if ((tim_device->timer == ATIM3) || (tim_device->timer == ATIM4))
{
prescaler_value = ((RCC_Clocks.AHB5ClkFreq / tim_div) / freq) - 1U;
}
else if ((tim_device->timer == GTIMA1) || (tim_device->timer == GTIMA2) || (tim_device->timer == GTIMA3))
{
prescaler_value = ((RCC_Clocks.AHB2ClkFreq / tim_div) / freq) - 1U;
}
else
{
prescaler_value = ((RCC_Clocks.AHB1ClkFreq / tim_div) / freq) - 1U;
}
/* Update frequency value */
TIM_ConfigPrescaler(tim_device->timer, prescaler_value, TIM_PSC_RELOAD_MODE_UPDATE);
#endif
result = RT_EOK;
}
break;
default:
{
result = -RT_EINVAL;
}
break;
}
return result;
}
static rt_uint32_t timer_counter_get(rt_clock_timer_t *timer)
{
struct n32_clock_timer *tim_device = RT_NULL;
RT_ASSERT(timer != RT_NULL);
tim_device = (struct n32_clock_timer *)timer;
return TIM_GetCnt(tim_device->timer);
}
static const struct rt_clock_timer_info _info = TIM_DEV_INFO_CONFIG;
static const struct rt_clock_timer_ops _ops = {
.init = timer_init,
.start = timer_start,
.stop = timer_stop,
.count_get = timer_counter_get,
.control = timer_ctrl,
};
#ifdef BSP_USING_ATIM1
void ATIM1_UP_IRQHandler(void)
{
/* enter interrupt */
rt_interrupt_enter();
TIM_ClrIntPendingBit(n32_clock_timer_obj[TIM1_INDEX].timer, TIM_INT_UPDATE);
rt_clock_timer_isr(&n32_clock_timer_obj[TIM1_INDEX].time_device);
/* leave interrupt */
rt_interrupt_leave();
}
#endif /* BSP_USING_ATIM1 */
#ifdef BSP_USING_ATIM2
void ATIM2_UP_IRQHandler(void)
{
/* enter interrupt */
rt_interrupt_enter();
TIM_ClrIntPendingBit(n32_clock_timer_obj[TIM2_INDEX].timer, TIM_INT_UPDATE);
rt_clock_timer_isr(&n32_clock_timer_obj[TIM2_INDEX].time_device);
/* leave interrupt */
rt_interrupt_leave();
}
#endif /* BSP_USING_ATIM2 */
#ifdef BSP_USING_ATIM3
void ATIM3_UP_IRQHandler(void)
{
/* enter interrupt */
rt_interrupt_enter();
TIM_ClrIntPendingBit(n32_clock_timer_obj[TIM3_INDEX].timer, TIM_INT_UPDATE);
rt_clock_timer_isr(&n32_clock_timer_obj[TIM3_INDEX].time_device);
/* leave interrupt */
rt_interrupt_leave();
}
#endif /* BSP_USING_ATIM3 */
#ifdef BSP_USING_ATIM4
void ATIM4_UP_IRQHandler(void)
{
/* enter interrupt */
rt_interrupt_enter();
TIM_ClrIntPendingBit(n32_clock_timer_obj[TIM4_INDEX].timer, TIM_INT_UPDATE);
rt_clock_timer_isr(&n32_clock_timer_obj[TIM4_INDEX].time_device);
/* leave interrupt */
rt_interrupt_leave();
}
#endif /* BSP_USING_ATIM4 */
#ifdef BSP_USING_GTIMA1
void GTIMA1_IRQHandler(void)
{
/* enter interrupt */
rt_interrupt_enter();
TIM_ClrIntPendingBit(n32_clock_timer_obj[TIM5_INDEX].timer, TIM_INT_UPDATE);
rt_clock_timer_isr(&n32_clock_timer_obj[TIM5_INDEX].time_device);
/* leave interrupt */
rt_interrupt_leave();
}
#endif /* BSP_USING_GTIMA1 */
#ifdef BSP_USING_GTIMA2
void GTIMA2_IRQHandler(void)
{
/* enter interrupt */
rt_interrupt_enter();
TIM_ClrIntPendingBit(n32_clock_timer_obj[TIM6_INDEX].timer, TIM_INT_UPDATE);
rt_clock_timer_isr(&n32_clock_timer_obj[TIM6_INDEX].time_device);
/* leave interrupt */
rt_interrupt_leave();
}
#endif /* BSP_USING_GTIMA2 */
#ifdef BSP_USING_GTIMA3
void GTIMA3_IRQHandler(void)
{
/* enter interrupt */
rt_interrupt_enter();
TIM_ClrIntPendingBit(n32_clock_timer_obj[TIM7_INDEX].timer, TIM_INT_UPDATE);
rt_clock_timer_isr(&n32_clock_timer_obj[TIM7_INDEX].time_device);
/* leave interrupt */
rt_interrupt_leave();
}
#endif /* BSP_USING_GTIMA3 */
#ifdef BSP_USING_GTIMA4
void GTIMA4_IRQHandler(void)
{
/* enter interrupt */
rt_interrupt_enter();
TIM_ClrIntPendingBit(n32_clock_timer_obj[TIM8_INDEX].timer, TIM_INT_UPDATE);
rt_clock_timer_isr(&n32_clock_timer_obj[TIM8_INDEX].time_device);
/* leave interrupt */
rt_interrupt_leave();
}
#endif /* BSP_USING_GTIMA4 */
#ifdef BSP_USING_GTIMA5
void GTIMA5_IRQHandler(void)
{
/* enter interrupt */
rt_interrupt_enter();
TIM_ClrIntPendingBit(n32_clock_timer_obj[TIM9_INDEX].timer, TIM_INT_UPDATE);
rt_clock_timer_isr(&n32_clock_timer_obj[TIM9_INDEX].time_device);
/* leave interrupt */
rt_interrupt_leave();
}
#endif /* BSP_USING_GTIMA5 */
#ifdef BSP_USING_GTIMA6
void GTIMA6_IRQHandler(void)
{
/* enter interrupt */
rt_interrupt_enter();
TIM_ClrIntPendingBit(n32_clock_timer_obj[TIM10_INDEX].timer, TIM_INT_UPDATE);
rt_clock_timer_isr(&n32_clock_timer_obj[TIM10_INDEX].time_device);
/* leave interrupt */
rt_interrupt_leave();
}
#endif /* BSP_USING_GTIMA6 */
#ifdef BSP_USING_GTIMA7
void GTIMA7_IRQHandler(void)
{
/* enter interrupt */
rt_interrupt_enter();
TIM_ClrIntPendingBit(n32_clock_timer_obj[TIM11_INDEX].timer, TIM_INT_UPDATE);
rt_clock_timer_isr(&n32_clock_timer_obj[TIM11_INDEX].time_device);
/* leave interrupt */
rt_interrupt_leave();
}
#endif /* BSP_USING_GTIMA7 */
#ifdef BSP_USING_GTIMB1
void GTIMB1_IRQHandler(void)
{
/* enter interrupt */
rt_interrupt_enter();
TIM_ClrIntPendingBit(n32_clock_timer_obj[TIM12_INDEX].timer, TIM_INT_UPDATE);
rt_clock_timer_isr(&n32_clock_timer_obj[TIM12_INDEX].time_device);
/* leave interrupt */
rt_interrupt_leave();
}
#endif /* BSP_USING_GTIMB1 */
#ifdef BSP_USING_GTIMB2
void GTIMB2_IRQHandler(void)
{
/* enter interrupt */
rt_interrupt_enter();
TIM_ClrIntPendingBit(n32_clock_timer_obj[TIM13_INDEX].timer, TIM_INT_UPDATE);
rt_clock_timer_isr(&n32_clock_timer_obj[TIM13_INDEX].time_device);
/* leave interrupt */
rt_interrupt_leave();
}
#endif /* BSP_USING_GTIMB2 */
#ifdef BSP_USING_GTIMB3
void GTIMB3_IRQHandler(void)
{
/* enter interrupt */
rt_interrupt_enter();
TIM_ClrIntPendingBit(n32_clock_timer_obj[TIM14_INDEX].timer, TIM_INT_UPDATE);
rt_clock_timer_isr(&n32_clock_timer_obj[TIM14_INDEX].time_device);
/* leave interrupt */
rt_interrupt_leave();
}
#endif /* BSP_USING_GTIMB3 */
#ifdef BSP_USING_BTIM1
void BTIM1_IRQHandler(void)
{
/* enter interrupt */
rt_interrupt_enter();
TIM_ClrIntPendingBit(n32_clock_timer_obj[TIM15_INDEX].timer, TIM_INT_UPDATE);
rt_clock_timer_isr(&n32_clock_timer_obj[TIM15_INDEX].time_device);
/* leave interrupt */
rt_interrupt_leave();
}
#endif /* BSP_USING_BTIM1 */
#ifdef BSP_USING_BTIM2
void BTIM2_IRQHandler(void)
{
/* enter interrupt */
rt_interrupt_enter();
TIM_ClrIntPendingBit(n32_clock_timer_obj[TIM16_INDEX].timer, TIM_INT_UPDATE);
rt_clock_timer_isr(&n32_clock_timer_obj[TIM16_INDEX].time_device);
/* leave interrupt */
rt_interrupt_leave();
}
#endif /* BSP_USING_BTIM2 */
#ifdef BSP_USING_BTIM3
void BTIM3_IRQHandler(void)
{
/* enter interrupt */
rt_interrupt_enter();
TIM_ClrIntPendingBit(n32_clock_timer_obj[TIM17_INDEX].timer, TIM_INT_UPDATE);
rt_clock_timer_isr(&n32_clock_timer_obj[TIM17_INDEX].time_device);
/* leave interrupt */
rt_interrupt_leave();
}
#endif /* BSP_USING_BTIM3 */
#ifdef BSP_USING_BTIM4
void BTIM4_IRQHandler(void)
{
/* enter interrupt */
rt_interrupt_enter();
TIM_ClrIntPendingBit(n32_clock_timer_obj[TIM18_INDEX].timer, TIM_INT_UPDATE);
rt_clock_timer_isr(&n32_clock_timer_obj[TIM18_INDEX].time_device);
/* leave interrupt */
rt_interrupt_leave();
}
#endif /* BSP_USING_BTIM4 */
static int n32_clock_timer_init(void)
{
rt_uint32_t i = 0;
int result = RT_EOK;
for (i = 0; i < sizeof(n32_clock_timer_obj) / sizeof(n32_clock_timer_obj[0]); i++)
{
n32_clock_timer_obj[i].time_device.info = &_info;
n32_clock_timer_obj[i].time_device.ops = &_ops;
if (rt_clock_timer_register(&n32_clock_timer_obj[i].time_device,
n32_clock_timer_obj[i].name, RT_NULL) == RT_EOK)
{
LOG_D("%s register success", n32_clock_timer_obj[i].name);
}
else
{
LOG_E("%s register failed", n32_clock_timer_obj[i].name);
result = -RT_ERROR;
}
}
return result;
}
INIT_BOARD_EXPORT(n32_clock_timer_init);
#endif /* BSP_USING_CLOCK_TIMER */

20
bsp/n32/n32hxxx/libraries/N32_Drivers/drivers/drv_tim.h Normal file
View File

@ -0,0 +1,20 @@
/*
* Copyright (c) 2006-2023, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2026-02-26 ox-horse first version
*/
#ifndef __DRV_TIM_H__
#define __DRV_TIM_H__
#include <rtdef.h>
#include <board.h>
void n32_tim_ahbx_div_get(TIM_Module *timer, rt_uint32_t *div);
void n32_tim_enable_clock(TIM_Module *timer);
#endif /* __DRV_TIM_H__ */

536
bsp/n32/n32hxxx/libraries/N32_Drivers/drivers/drv_usart.c
View File

@ -15,6 +15,8 @@
#ifdef RT_USING_SERIAL
#define BSP_N32_UART_V1_TX_TIMEOUT 2000
//#define DRV_DEBUG
#define LOG_TAG "drv.usart"
#include <drv_log.h>
@ -151,14 +153,16 @@ static void dma_recv_callback(struct rt_serial_device *serial, rt_uint8_t isr_fl
{
struct n32_uart *uart;
rt_base_t level;
rt_size_t recv_len, read_len;
rt_size_t recv_len = 0;
RT_ASSERT(serial != RT_NULL);
uart = rt_container_of(serial, struct n32_uart, serial);
level = rt_hw_interrupt_disable();
recv_len = 0;
#if defined(SOC_SERIES_N32H7xx)
rt_size_t read_len;
read_len = DMA_GetTransferredNumber(uart->config->dma_rx->Instance, uart->config->dma_rx->dma_channel);
switch (isr_flag)
@ -195,14 +199,60 @@ static void dma_recv_callback(struct rt_serial_device *serial, rt_uint8_t isr_fl
break;
}
#elif defined(SOC_SERIES_N32H49x) || defined(SOC_SERIES_N32H47x_48x)
uint16_t counter;
/* Get the remaining data count of the current DMA. */
counter = DMA_GetCurrDataCounter(uart->config->dma_rx->DMAChx);
switch (isr_flag)
{
case UART_RX_DMA_IT_IDLE_FLAG:
/* IDLE interrupt: usually indicates the end of a data frame */
/* Calculate received length: total size - remaining */
if (counter <= uart->dma.rx_dma.remaining_cnt)
{
recv_len = uart->dma.rx_dma.remaining_cnt - counter;
}
else
{
recv_len = serial->config.bufsz + uart->dma.rx_dma.remaining_cnt - counter;
}
break;
case UART_RX_DMA_IT_HT_FLAG:
/* Half-transfer interrupt: data reaches half of the buffer */
if (counter < uart->dma.rx_dma.remaining_cnt)
{
recv_len = uart->dma.rx_dma.remaining_cnt - counter;
}
break;
case UART_RX_DMA_IT_TC_FLAG:
/* Full-transfer interrupt: buffer is full */
if (counter >= uart->dma.rx_dma.remaining_cnt)
{
recv_len = serial->config.bufsz + uart->dma.rx_dma.remaining_cnt - counter;
}
break;
default:
break;
}
#endif
if (recv_len)
{
#if defined(SOC_SERIES_N32H49x) || defined(SOC_SERIES_N32H47x_48x)
/* Update the remaining count, used for calculating the difference in the next HT/TC */
uart->dma.rx_dma.remaining_cnt = counter;
#endif
rt_hw_serial_isr(serial, RT_SERIAL_EVENT_RX_DMADONE | (recv_len << 8));
}
rt_hw_interrupt_enable(level);
}
#if defined(BSP_UART1_RX_USING_DMA) || defined(BSP_UART2_RX_USING_DMA) || defined(BSP_UART3_RX_USING_DMA) || \
defined(BSP_UART4_RX_USING_DMA) || defined(BSP_UART5_RX_USING_DMA) || defined(BSP_UART6_RX_USING_DMA) || \
defined(BSP_UART7_RX_USING_DMA) || defined(BSP_UART8_RX_USING_DMA) || defined(BSP_UART9_RX_USING_DMA) || \
@ -222,6 +272,108 @@ static void uart_rx_dma_isr(struct n32_uart *uart_drv)
DMA_ClearChannelEventStatus(uart_drv->config->dma_rx->Instance, uart_drv->config->dma_rx->dma_channel, DMA_CH_EVENT_BLOCK_TRANSFER_COMPLETE);
}
}
#elif defined(SOC_SERIES_N32H49x) || defined(SOC_SERIES_N32H47x_48x)
DMA_Module *dma_module = (DMA_Module *)((uint32_t)uart_drv->config->dma_rx->DMAChx < DMA2_BASE ? DMA1 : DMA2);
uint32_t dma_int_ht = 0;
uint32_t dma_int_tc = 0;
/* Obtain the corresponding interrupt flag macro based on the channel (refer to the TX implementation) */
if (uart_drv->config->dma_rx->DMAChx == DMA1_CH1)
{
dma_int_ht = DMA_INT_HTX1;
dma_int_tc = DMA_INT_TXC1;
}
else if (uart_drv->config->dma_rx->DMAChx == DMA1_CH2)
{
dma_int_ht = DMA_INT_HTX2;
dma_int_tc = DMA_INT_TXC2;
}
else if (uart_drv->config->dma_rx->DMAChx == DMA1_CH3)
{
dma_int_ht = DMA_INT_HTX3;
dma_int_tc = DMA_INT_TXC3;
}
else if (uart_drv->config->dma_rx->DMAChx == DMA1_CH4)
{
dma_int_ht = DMA_INT_HTX4;
dma_int_tc = DMA_INT_TXC4;
}
else if (uart_drv->config->dma_rx->DMAChx == DMA1_CH5)
{
dma_int_ht = DMA_INT_HTX5;
dma_int_tc = DMA_INT_TXC5;
}
else if (uart_drv->config->dma_rx->DMAChx == DMA1_CH6)
{
dma_int_ht = DMA_INT_HTX6;
dma_int_tc = DMA_INT_TXC6;
}
else if (uart_drv->config->dma_rx->DMAChx == DMA1_CH7)
{
dma_int_ht = DMA_INT_HTX7;
dma_int_tc = DMA_INT_TXC7;
}
else if (uart_drv->config->dma_rx->DMAChx == DMA1_CH8)
{
dma_int_ht = DMA_INT_HTX8;
dma_int_tc = DMA_INT_TXC8;
}
else if (uart_drv->config->dma_rx->DMAChx == DMA2_CH1)
{
dma_int_ht = DMA_INT_HTX1;
dma_int_tc = DMA_INT_TXC1;
}
else if (uart_drv->config->dma_rx->DMAChx == DMA2_CH2)
{
dma_int_ht = DMA_INT_HTX2;
dma_int_tc = DMA_INT_TXC2;
}
else if (uart_drv->config->dma_rx->DMAChx == DMA2_CH3)
{
dma_int_ht = DMA_INT_HTX3;
dma_int_tc = DMA_INT_TXC3;
}
else if (uart_drv->config->dma_rx->DMAChx == DMA2_CH4)
{
dma_int_ht = DMA_INT_HTX4;
dma_int_tc = DMA_INT_TXC4;
}
else if (uart_drv->config->dma_rx->DMAChx == DMA2_CH5)
{
dma_int_ht = DMA_INT_HTX5;
dma_int_tc = DMA_INT_TXC5;
}
else if (uart_drv->config->dma_rx->DMAChx == DMA2_CH6)
{
dma_int_ht = DMA_INT_HTX6;
dma_int_tc = DMA_INT_TXC6;
}
else if (uart_drv->config->dma_rx->DMAChx == DMA2_CH7)
{
dma_int_ht = DMA_INT_HTX7;
dma_int_tc = DMA_INT_TXC7;
}
else if (uart_drv->config->dma_rx->DMAChx == DMA2_CH8)
{
dma_int_ht = DMA_INT_HTX8;
dma_int_tc = DMA_INT_TXC8;
}
/* Check half-transfer interrupt */
if (dma_int_ht != 0 && DMA_GetIntStatus(dma_int_ht, dma_module) == SET)
{
DMA_ClrIntPendingBit(dma_int_ht, dma_module);
dma_recv_callback(&uart_drv->serial, UART_RX_DMA_IT_HT_FLAG);
}
/* Check full-transfer interrupt */
if (dma_int_tc != 0 && DMA_GetIntStatus(dma_int_tc, dma_module) == SET)
{
DMA_ClrIntPendingBit(dma_int_tc, dma_module);
dma_recv_callback(&uart_drv->serial, UART_RX_DMA_IT_TC_FLAG);
}
#endif
}
#endif
@ -265,17 +417,65 @@ static void uart_tx_dma_isr(struct n32_uart *uart_drv)
}
}
}
#elif defined(SOC_SERIES_N32H49x) || defined(SOC_SERIES_N32H47x_48x)
DMA_Module *dma_module = (DMA_Module *)((uint32_t)uart_drv->config->dma_tx->DMAChx < DMA2_BASE ? DMA1 : DMA2);
uint32_t dma_int_tc = 0;
if (uart_drv->config->dma_tx->DMAChx == DMA1_CH1)
dma_int_tc = DMA_INT_TXC1;
else if (uart_drv->config->dma_tx->DMAChx == DMA1_CH2)
dma_int_tc = DMA_INT_TXC2;
else if (uart_drv->config->dma_tx->DMAChx == DMA1_CH3)
dma_int_tc = DMA_INT_TXC3;
else if (uart_drv->config->dma_tx->DMAChx == DMA1_CH4)
dma_int_tc = DMA_INT_TXC4;
else if (uart_drv->config->dma_tx->DMAChx == DMA1_CH5)
dma_int_tc = DMA_INT_TXC5;
else if (uart_drv->config->dma_tx->DMAChx == DMA1_CH6)
dma_int_tc = DMA_INT_TXC6;
else if (uart_drv->config->dma_tx->DMAChx == DMA1_CH7)
dma_int_tc = DMA_INT_TXC7;
else if (uart_drv->config->dma_tx->DMAChx == DMA1_CH8)
dma_int_tc = DMA_INT_TXC8;
else if (uart_drv->config->dma_tx->DMAChx == DMA2_CH1)
dma_int_tc = DMA_INT_TXC1;
else if (uart_drv->config->dma_tx->DMAChx == DMA2_CH2)
dma_int_tc = DMA_INT_TXC2;
else if (uart_drv->config->dma_tx->DMAChx == DMA2_CH3)
dma_int_tc = DMA_INT_TXC3;
else if (uart_drv->config->dma_tx->DMAChx == DMA2_CH4)
dma_int_tc = DMA_INT_TXC4;
else if (uart_drv->config->dma_tx->DMAChx == DMA2_CH5)
dma_int_tc = DMA_INT_TXC5;
else if (uart_drv->config->dma_tx->DMAChx == DMA2_CH6)
dma_int_tc = DMA_INT_TXC6;
else if (uart_drv->config->dma_tx->DMAChx == DMA2_CH7)
dma_int_tc = DMA_INT_TXC7;
else if (uart_drv->config->dma_tx->DMAChx == DMA2_CH8)
dma_int_tc = DMA_INT_TXC8;
if (dma_int_tc != 0 && DMA_GetIntStatus(dma_int_tc, dma_module) == SET)
{
DMA_ClrIntPendingBit(dma_int_tc, dma_module);
DMA_EnableChannel(uart_drv->config->dma_tx->DMAChx, DISABLE);
USART_EnableDMA(uart_drv->config->Instance, USART_DMAREQ_TX, DISABLE);
/* Notify the RT-Thread serial layer that transmission is complete */
rt_hw_serial_isr(&uart_drv->serial, RT_SERIAL_EVENT_TX_DMADONE);
}
#endif
rt_hw_interrupt_enable(level);
}
#endif /* RT_SERIAL_USING_DMA */
static void N32_UART_DMA_Config(struct rt_serial_device *serial, rt_ubase_t flag)
{
rt_size_t i = 0;
rt_err_t result = RT_EOK;
struct n32_uart *uart;
struct rt_serial_rx_fifo *rx_fifo = RT_NULL;
@ -283,6 +483,10 @@ static void N32_UART_DMA_Config(struct rt_serial_device *serial, rt_ubase_t flag
RT_ASSERT(flag == RT_DEVICE_FLAG_DMA_TX || flag == RT_DEVICE_FLAG_DMA_RX);
uart = rt_container_of(serial, struct n32_uart, serial);
#if defined(SOC_SERIES_N32H7xx)
rt_size_t i = 0;
rt_err_t result = RT_EOK;
/* DMA Initialize */
if (RT_DEVICE_FLAG_DMA_RX == flag)
{
@ -335,19 +539,98 @@ static void N32_UART_DMA_Config(struct rt_serial_device *serial, rt_ubase_t flag
/* enable uart irq */
NVIC_SetPriority(uart->config->irq_type, NVIC_EncodePriority(NVIC_GetPriorityGrouping(), 1, 0));
NVIC_EnableIRQ(uart->config->irq_type);
#elif defined(SOC_SERIES_N32H49x) || defined(SOC_SERIES_N32H47x_48x)
if (RT_DEVICE_FLAG_DMA_RX == flag)
{
/* If already initialized, return directly or only re-enable the interrupt/channel */
if (uart->dma.rx_dma_inited == RT_TRUE)
{
LOG_D("%s RX DMA already inited", uart->config->name);
DMA_EnableChannel(uart->config->dma_rx->DMAChx, ENABLE);
NVIC_EnableIRQ(uart->config->dma_rx->dma_irq);
return;
}
rx_fifo = (struct rt_serial_rx_fifo *)serial->serial_rx;
RT_ASSERT(rx_fifo != RT_NULL);
RT_ASSERT(rx_fifo->buffer != RT_NULL);
DMA_DeInit(uart->config->dma_rx->DMAChx);
uart->dma.RX_DMA_ChInitStr.MemAddr = (uint32_t)rx_fifo->buffer;
uart->dma.RX_DMA_ChInitStr.BufSize = serial->config.bufsz;
DMA_Init(uart->config->dma_rx->DMAChx, &uart->dma.RX_DMA_ChInitStr);
/* Configure DMA request mapping */
DMA_RequestRemap(uart->config->dma_rx->request, uart->config->dma_rx->DMAChx, ENABLE);
/* Enable DMA half-transfer and full-transfer interrupts */
DMA_ConfigInt(uart->config->dma_rx->DMAChx, DMA_INT_HTX, ENABLE);
DMA_ConfigInt(uart->config->dma_rx->DMAChx, DMA_INT_TXC, ENABLE);
NVIC_SetPriority(uart->config->dma_rx->dma_irq, NVIC_EncodePriority(NVIC_GetPriorityGrouping(), 1, 0));
NVIC_EnableIRQ(uart->config->dma_rx->dma_irq);
DMA_EnableChannel(uart->config->dma_rx->DMAChx, ENABLE);
USART_EnableDMA(uart->config->Instance, USART_DMAREQ_RX, ENABLE);
USART_ConfigInt(uart->config->Instance, USART_INT_IDLEF, ENABLE);
NVIC_SetPriority(uart->config->irq_type, NVIC_EncodePriority(NVIC_GetPriorityGrouping(), 2, 0));
NVIC_EnableIRQ(uart->config->irq_type);
/* Initialize the remaining count */
uart->dma.rx_dma.remaining_cnt = serial->config.bufsz;
/* Mark as initialized */
uart->dma.rx_dma_inited = RT_TRUE;
LOG_D("%s RX DMA config done", uart->config->name);
}
else if (RT_DEVICE_FLAG_DMA_TX == flag)
{
if (uart->dma.tx_dma_inited == RT_TRUE)
{
LOG_D("%s TX DMA already inited", uart->config->name);
return;
}
DMA_EnableChannel(uart->config->dma_tx->DMAChx, DISABLE);
DMA_DeInit(uart->config->dma_tx->DMAChx);
DMA_Init(uart->config->dma_tx->DMAChx, &uart->dma.TX_DMA_ChInitStr);
DMA_RequestRemap(uart->config->dma_tx->request, uart->config->dma_tx->DMAChx, ENABLE);
/* Enable DMA transfer complete interrupt (TC) */
DMA_ConfigInt(uart->config->dma_tx->DMAChx, DMA_INT_TXC, ENABLE);
NVIC_SetPriority(uart->config->dma_tx->dma_irq, NVIC_EncodePriority(NVIC_GetPriorityGrouping(), 2, 1));
NVIC_EnableIRQ(uart->config->dma_tx->dma_irq);
uart->dma.tx_dma_inited = RT_TRUE;
LOG_D("%s TX DMA config done", uart->config->name);
}
#endif
}
static rt_err_t UART_DMA_Transmit(struct n32_uart *uart)
{
rt_uint16_t send_length;
rt_size_t already_send_length;
const rt_uint8_t *send_buf = RT_NULL;
RT_ASSERT(uart != RT_NULL);
#if defined(SOC_SERIES_N32H7xx)
if (uart->dma.DMA_Tx_Init == RT_TRUE)
{
#if defined(SOC_SERIES_N32H7xx)
rt_size_t already_send_length;
/* DMA uses a single block, with a maximum of 4095 per block */
if (uart->dma.tx_dma.total_length > 4095U)
{
@ -392,14 +675,90 @@ static rt_err_t UART_DMA_Transmit(struct n32_uart *uart)
USART_Enable(uart->config->Instance, ENABLE);
}
#endif
}
else
{
LOG_E("UART TX DMA Mode, TX DMA did not complete initialization.");
return -RT_ERROR;
}
#elif defined(SOC_SERIES_N32H49x) || defined(SOC_SERIES_N32H47x_48x)
send_length = uart->dma.tx_dma.total_length;
send_buf = uart->dma.tx_dma.buf;
if (send_length == 0 || send_buf == RT_NULL)
{
return -RT_ERROR;
}
/* Disable DMA channels */
DMA_EnableChannel(uart->config->dma_tx->DMAChx, DISABLE);
/* Clear the previous transfer complete flag (to prevent false triggering). */
DMA_Module *dma_module = (DMA_Module *)((uint32_t)uart->config->dma_tx->DMAChx < DMA2_BASE ? DMA1 : DMA2);
uint32_t dma_flag_tc = 0;
/* Map the channel to the flag. */
if (uart->config->dma_tx->DMAChx == DMA1_CH1)
dma_flag_tc = DMA_FLAG_TC1;
else if (uart->config->dma_tx->DMAChx == DMA1_CH2)
dma_flag_tc = DMA_FLAG_TC2;
else if (uart->config->dma_tx->DMAChx == DMA1_CH3)
dma_flag_tc = DMA_FLAG_TC3;
else if (uart->config->dma_tx->DMAChx == DMA1_CH4)
dma_flag_tc = DMA_FLAG_TC4;
else if (uart->config->dma_tx->DMAChx == DMA1_CH5)
dma_flag_tc = DMA_FLAG_TC5;
else if (uart->config->dma_tx->DMAChx == DMA1_CH6)
dma_flag_tc = DMA_FLAG_TC6;
else if (uart->config->dma_tx->DMAChx == DMA1_CH7)
dma_flag_tc = DMA_FLAG_TC7;
else if (uart->config->dma_tx->DMAChx == DMA1_CH8)
dma_flag_tc = DMA_FLAG_TC8;
else if (uart->config->dma_tx->DMAChx == DMA2_CH1)
dma_flag_tc = DMA_FLAG_TC1;
else if (uart->config->dma_tx->DMAChx == DMA2_CH2)
dma_flag_tc = DMA_FLAG_TC2;
else if (uart->config->dma_tx->DMAChx == DMA2_CH3)
dma_flag_tc = DMA_FLAG_TC3;
else if (uart->config->dma_tx->DMAChx == DMA2_CH4)
dma_flag_tc = DMA_FLAG_TC4;
else if (uart->config->dma_tx->DMAChx == DMA2_CH5)
dma_flag_tc = DMA_FLAG_TC5;
else if (uart->config->dma_tx->DMAChx == DMA2_CH6)
dma_flag_tc = DMA_FLAG_TC6;
else if (uart->config->dma_tx->DMAChx == DMA2_CH7)
dma_flag_tc = DMA_FLAG_TC7;
else if (uart->config->dma_tx->DMAChx == DMA2_CH8)
dma_flag_tc = DMA_FLAG_TC8;
if (dma_flag_tc != 0)
{
DMA_ClearFlag(dma_flag_tc, dma_module);
}
uart->dma.TX_DMA_ChInitStr.MemAddr = (uint32_t)send_buf;
uart->dma.TX_DMA_ChInitStr.BufSize = send_length;
/* Re-initialize the DMA channel. */
DMA_DeInit(uart->config->dma_tx->DMAChx);
DMA_Init(uart->config->dma_tx->DMAChx, &uart->dma.TX_DMA_ChInitStr);
DMA_ConfigInt(uart->config->dma_tx->DMAChx, DMA_INT_TXC, ENABLE);
/* Clear the USART transmit complete flag. */
USART_ClrFlag(uart->config->Instance, USART_FLAG_TXC);
/* Enable the DMA channel. */
DMA_EnableChannel(uart->config->dma_tx->DMAChx, ENABLE);
/* Enable the USART DMA transmit request. */
USART_EnableDMA(uart->config->Instance, USART_DMAREQ_TX, ENABLE);
/* Ensure the USART is enabled. */
USART_Enable(uart->config->Instance, ENABLE);
#endif
return RT_EOK;
}
#endif /* RT_SERIAL_USING_DMA */
@ -451,9 +810,7 @@ static rt_err_t n32_configure(struct rt_serial_device *serial, struct serial_con
USART_InitStructure.BaudRate = cfg->baud_rate;
USART_InitStructure.Mode = USART_MODE_RX | USART_MODE_TX;
#if defined(SOC_SERIES_N32H7)
#ifdef USART_CTRL1_OSPM
#endif
USART_InitStructure.OverSampling = cfg->baud_rate > 5000000 ? USART_8OVER : USART_16OVER;
#else
USART_InitStructure.OverSampling = USART_16OVER;
@ -518,9 +875,14 @@ static rt_err_t n32_configure(struct rt_serial_device *serial, struct serial_con
}
#ifdef RT_SERIAL_USING_DMA
if (!(serial->parent.open_flag & RT_DEVICE_OFLAG_OPEN))
{
#if defined(SOC_SERIES_N32H7xx)
uart->dma.rx_dma.block_has_recv_cnt = 0;
#elif defined(SOC_SERIES_N32H49x) || defined(SOC_SERIES_N32H47x_48x)
uart->dma.rx_dma.remaining_cnt = cfg->bufsz;
#endif /* SOC_SERIES_N32H7xx */
}
#endif
@ -529,6 +891,7 @@ static rt_err_t n32_configure(struct rt_serial_device *serial, struct serial_con
USART_Enable(uart->config->Instance, ENABLE);
uart->DR_mask = n32_uart_get_mask(USART_InitStructure.WordLength, USART_InitStructure.Parity);
uart->tx_block_timeout = BSP_N32_UART_V1_TX_TIMEOUT;
return RT_EOK;
}
@ -537,6 +900,7 @@ static rt_err_t n32_configure(struct rt_serial_device *serial, struct serial_con
static rt_err_t n32_control(struct rt_serial_device *serial, int cmd, void *arg)
{
struct n32_uart *uart;
rt_uint32_t direction;
#ifdef RT_SERIAL_USING_DMA
rt_ubase_t ctrl_arg = (rt_ubase_t)arg;
#endif
@ -551,7 +915,11 @@ static rt_err_t n32_control(struct rt_serial_device *serial, int cmd, void *arg)
/* disable rx irq */
NVIC_DisableIRQ(uart->config->irq_type);
/* disable interrupt */
USART_ConfigInt(uart->config->Instance, USART_INT_RXDNE, DISABLE);
direction = (rt_uint32_t)arg;
if (direction == RT_DEVICE_FLAG_INT_RX)
{
USART_ConfigInt(uart->config->Instance, USART_INT_RXDNE, DISABLE);
}
#ifdef RT_SERIAL_USING_DMA
/* disable DMA */
@ -559,18 +927,28 @@ static rt_err_t n32_control(struct rt_serial_device *serial, int cmd, void *arg)
{
NVIC_DisableIRQ(uart->config->dma_rx->dma_irq);
#if defined(SOC_SERIES_N32H7xx)
DMA_ChannelCmd(uart->config->dma_rx->Instance, uart->config->dma_rx->dma_channel, DISABLE);
USART_EnableDMA(uart->config->Instance, USART_DMAREQ_RX, DISABLE);
rt_free(uart->dma.rx_dma.Read_LinkList);
uart->dma.rx_dma.Read_LinkList = RT_NULL;
#elif defined(SOC_SERIES_N32H49x) || defined(SOC_SERIES_N32H47x_48x)
DMA_EnableChannel(uart->config->dma_rx->DMAChx, DISABLE);
USART_EnableDMA(uart->config->Instance, USART_DMAREQ_RX, DISABLE);
#endif /* SOC_SERIES_N32H7xx */
}
else if (ctrl_arg == RT_DEVICE_FLAG_DMA_TX)
{
NVIC_DisableIRQ(uart->config->dma_tx->dma_irq);
DMA_ChannelCmd(uart->config->dma_rx->Instance, uart->config->dma_rx->dma_channel, DISABLE);
#if defined(SOC_SERIES_N32H7xx)
DMA_ChannelCmd(uart->config->dma_tx->Instance, uart->config->dma_tx->dma_channel, DISABLE);
#elif defined(SOC_SERIES_N32H49x) || defined(SOC_SERIES_N32H47x_48x)
DMA_EnableChannel(uart->config->dma_tx->DMAChx, DISABLE);
#endif /* SOC_SERIES_N32H7xx */
USART_EnableDMA(uart->config->Instance, USART_DMAREQ_TX, DISABLE);
}
@ -583,7 +961,11 @@ static rt_err_t n32_control(struct rt_serial_device *serial, int cmd, void *arg)
NVIC_SetPriority(uart->config->irq_type, NVIC_EncodePriority(NVIC_GetPriorityGrouping(), 1, 0));
NVIC_EnableIRQ(uart->config->irq_type);
/* enable interrupt */
USART_ConfigInt(uart->config->Instance, USART_INT_RXDNE, ENABLE);
direction = (rt_uint32_t)arg;
if (direction == RT_DEVICE_FLAG_INT_RX)
{
USART_ConfigInt(uart->config->Instance, USART_INT_RXDNE, ENABLE);
}
break;
#ifdef RT_SERIAL_USING_DMA
@ -598,6 +980,24 @@ static rt_err_t n32_control(struct rt_serial_device *serial, int cmd, void *arg)
uart->config->EnablePeriphClk(uart->config->periph, DISABLE);
break;
#if defined(SOC_SERIES_N32H49x) || defined(SOC_SERIES_N32H47x_48x)
case UART_CTRL_SET_BLOCK_TIMEOUT:
{
rt_uint32_t block_timeout = (rt_uint32_t)arg;
if (block_timeout > 0)
{
uart->tx_block_timeout = block_timeout;
}
else
{
return -RT_ERROR;
}
break;
}
#endif
default:
break;
}
return RT_EOK;
}
@ -608,6 +1008,7 @@ static int n32_putc(struct rt_serial_device *serial, char c)
RT_ASSERT(serial != RT_NULL);
uart = rt_container_of(serial, struct n32_uart, serial);
rt_uint32_t block_timeout = uart->tx_block_timeout;
/* Clear transmission complete flag */
if (USART_GetFlagStatus(uart->config->Instance, USART_FLAG_TXC) != RESET)
@ -616,11 +1017,10 @@ static int n32_putc(struct rt_serial_device *serial, char c)
/* Send data */
USART_SendData(uart->config->Instance, c);
while (USART_GetFlagStatus(uart->config->Instance, USART_FLAG_TXC) == RESET)
{
}
while ((USART_GetFlagStatus(uart->config->Instance, USART_FLAG_TXC) == RESET) && --block_timeout)
;
return 1;
return (block_timeout != 0) ? 1 : -1;
}
static int n32_getc(struct rt_serial_device *serial)
@ -655,10 +1055,15 @@ static rt_ssize_t n32_dma_transmit(struct rt_serial_device *serial, rt_uint8_t *
#ifdef RT_SERIAL_USING_DMA
if (RT_SERIAL_DMA_TX == direction)
{
#if defined(SOC_SERIES_N32H7xx)
uart->dma.tx_dma.record_length = size;
uart->dma.tx_dma.total_length = size;
uart->dma.tx_dma.already_send_length = 0U;
uart->dma.tx_dma.buf = buf;
#elif defined(SOC_SERIES_N32H49x) || defined(SOC_SERIES_N32H47x_48x)
uart->dma.tx_dma.total_length = size;
uart->dma.tx_dma.buf = buf;
#endif /* SOC_SERIES_N32H7xx */
/* start once data exchange in DMA mode */
UART_DMA_Transmit(uart);
@ -739,6 +1144,7 @@ void USART1_IRQHandler(void)
rt_interrupt_leave();
}
#if defined(RT_SERIAL_USING_DMA) && defined(BSP_UART1_RX_USING_DMA) && defined(UART1_RX_DMA_IRQHandler)
void UART1_RX_DMA_IRQHandler(void)
{
/* enter interrupt */
@ -765,6 +1171,7 @@ void UART1_TX_DMA_IRQHandler(void)
#endif /* BSP_USING_UART1 */
#if defined(BSP_USING_UART2)
void USART2_IRQHandler(void)
{
/* enter interrupt */
@ -876,7 +1283,12 @@ void UART4_TX_DMA_IRQHandler(void)
#endif /* BSP_USING_UART4 */
#if defined(BSP_USING_UART5)
#if defined(SOC_SERIES_N32H7xx)
void USART5_IRQHandler(void)
#elif defined(SOC_SERIES_N32H49x) || defined(SOC_SERIES_N32H47x_48x)
void UART5_IRQHandler(void)
#endif
{
/* enter interrupt */
rt_interrupt_enter();
@ -913,7 +1325,12 @@ void UART5_TX_DMA_IRQHandler(void)
#endif /* BSP_USING_UART5 */
#if defined(BSP_USING_UART6)
#if defined(SOC_SERIES_N32H7xx)
void USART6_IRQHandler(void)
#elif defined(SOC_SERIES_N32H49x) || defined(SOC_SERIES_N32H47x_48x)
void UART6_IRQHandler(void)
#endif
{
/* enter interrupt */
rt_interrupt_enter();
@ -950,7 +1367,12 @@ void UART6_TX_DMA_IRQHandler(void)
#endif /* BSP_USING_UART6 */
#if defined(BSP_USING_UART7)
#if defined(SOC_SERIES_N32H7xx)
void USART7_IRQHandler(void)
#elif defined(SOC_SERIES_N32H49x) || defined(SOC_SERIES_N32H47x_48x)
void UART7_IRQHandler(void)
#endif
{
/* enter interrupt */
rt_interrupt_enter();
@ -961,6 +1383,7 @@ void USART7_IRQHandler(void)
rt_interrupt_leave();
}
#if defined(RT_SERIAL_USING_DMA) && defined(BSP_UART7_RX_USING_DMA) && defined(UART7_RX_DMA_IRQHandler)
void UART7_RX_DMA_IRQHandler(void)
{
/* enter interrupt */
@ -987,7 +1410,11 @@ void UART7_TX_DMA_IRQHandler(void)
#endif /* BSP_USING_UART7 */
#if defined(BSP_USING_UART8)
#if defined(SOC_SERIES_N32H7xx)
void USART8_IRQHandler(void)
#elif defined(SOC_SERIES_N32H49x) || defined(SOC_SERIES_N32H47x_48x)
void UART8_IRQHandler(void)
#endif
{
/* enter interrupt */
rt_interrupt_enter();
@ -1024,7 +1451,11 @@ void UART8_TX_DMA_IRQHandler(void)
#endif /* BSP_USING_UART8 */
#if defined(BSP_USING_UART9)
#if defined(SOC_SERIES_N32H7xx)
void UART9_IRQHandler(void)
#elif defined(SOC_SERIES_N32H49x) || defined(SOC_SERIES_N32H47x_48x)
void USART9_IRQHandler(void)
#endif
{
/* enter interrupt */
rt_interrupt_enter();
@ -1495,8 +1926,6 @@ static void n32_uart_get_dma_config(void)
#endif
}
static const struct rt_uart_ops n32_uart_ops =
{
.configure = n32_configure,
@ -1521,6 +1950,11 @@ int rt_hw_usart_init(void)
uart_obj[i].serial.config = config;
#ifdef RT_SERIAL_USING_DMA
#if defined(SOC_SERIES_N32H49x) || defined(SOC_SERIES_N32H47x_48x)
uart_obj[i].dma.tx_dma_inited = RT_FALSE;
uart_obj[i].dma.rx_dma_inited = RT_FALSE;
#endif
if (uart_obj[i].uart_dma_flag & RT_DEVICE_FLAG_DMA_TX)
{
#if defined(SOC_SERIES_N32H7xx)
@ -1534,7 +1968,7 @@ int rt_hw_usart_init(void)
DMA_ChannelStructInit(&uart_obj[i].dma.TX_DMA_ChInitStr);
uart_obj[i].dma.TX_DMA_ChInitStr.IntEn = 0x1U;
uart_obj[i].dma.TX_DMA_ChInitStr.DstAddr = (uint32_t)&uart_obj[i].config->Instance->DAT;
uart_obj[i].dma.TX_DMA_ChInitStr.SrcAddr = NULL;
uart_obj[i].dma.TX_DMA_ChInitStr.SrcAddr = RT_NULL;
uart_obj[i].dma.TX_DMA_ChInitStr.SrcTfrWidth = DMA_CH_TRANSFER_WIDTH_8;
uart_obj[i].dma.TX_DMA_ChInitStr.DstTfrWidth = DMA_CH_TRANSFER_WIDTH_8;
uart_obj[i].dma.TX_DMA_ChInitStr.DstAddrCountMode = DMA_CH_ADDRESS_COUNT_MODE_NO_CHANGE;
@ -1545,7 +1979,7 @@ int rt_hw_usart_init(void)
uart_obj[i].dma.TX_DMA_ChInitStr.DstScatterEn = 0x0U;
uart_obj[i].dma.TX_DMA_ChInitStr.TfrTypeFlowCtrl = DMA_CH_TRANSFER_FLOW_M2P_DMA;
uart_obj[i].dma.TX_DMA_ChInitStr.BlkTfrSize = 0U;
uart_obj[i].dma.TX_DMA_ChInitStr.pLinkListItem = NULL;
uart_obj[i].dma.TX_DMA_ChInitStr.pLinkListItem = RT_NULL;
uart_obj[i].dma.TX_DMA_ChInitStr.SrcGatherInterval = 0x0U;
uart_obj[i].dma.TX_DMA_ChInitStr.SrcGatherCount = 0x0U;
uart_obj[i].dma.TX_DMA_ChInitStr.DstScatterInterval = 0x0U;
@ -1576,7 +2010,29 @@ int rt_hw_usart_init(void)
LOG_E("%s TX DMA channel initialization failed!", uart_obj[i].config->name);
return -RT_ERROR;
}
#endif
#elif defined(SOC_SERIES_N32H49x) || defined(SOC_SERIES_N32H47x_48x)
/* Configure the UART TX DMA for Transmission process */
/* Enable DMA clock */
RCC_EnableAHBPeriphClk(uart_obj[i].config->dma_tx->dma_rcc, ENABLE);
DMA_DeInit(uart_obj[i].config->dma_tx->DMAChx);
DMA_StructInit(&uart_obj[i].dma.TX_DMA_ChInitStr);
uart_obj[i].dma.TX_DMA_ChInitStr.PeriphAddr = (uint32_t)&uart_obj[i].config->Instance->DAT;
uart_obj[i].dma.TX_DMA_ChInitStr.MemAddr = RT_NULL;
uart_obj[i].dma.TX_DMA_ChInitStr.Direction = DMA_DIR_PERIPH_DST;
uart_obj[i].dma.TX_DMA_ChInitStr.BufSize = 0U;
uart_obj[i].dma.TX_DMA_ChInitStr.PeriphInc = DMA_PERIPH_INC_DISABLE;
uart_obj[i].dma.TX_DMA_ChInitStr.MemoryInc = DMA_MEM_INC_ENABLE;
uart_obj[i].dma.TX_DMA_ChInitStr.PeriphDataSize = DMA_PERIPH_DATA_WIDTH_BYTE;
uart_obj[i].dma.TX_DMA_ChInitStr.MemDataSize = DMA_MEM_DATA_WIDTH_BYTE;
uart_obj[i].dma.TX_DMA_ChInitStr.CircularMode = DMA_MODE_NORMAL;
uart_obj[i].dma.TX_DMA_ChInitStr.Priority = DMA_PRIORITY_VERY_HIGH;
uart_obj[i].dma.TX_DMA_ChInitStr.Mem2Mem = DMA_M2M_DISABLE;
DMA_Init(uart_obj[i].config->dma_tx->DMAChx, &uart_obj[i].dma.TX_DMA_ChInitStr);
#endif /* SOC_SERIES_N32H7xx */
}
if (uart_obj[i].uart_dma_flag & RT_DEVICE_FLAG_DMA_RX)
@ -1617,7 +2073,7 @@ int rt_hw_usart_init(void)
DMA_ChannelStructInit(&uart_obj[i].dma.RX_DMA_ChInitStr);
uart_obj[i].dma.RX_DMA_ChInitStr.IntEn = 0x1U;
uart_obj[i].dma.RX_DMA_ChInitStr.SrcAddr = (uint32_t)&uart_obj[i].config->Instance->DAT;
uart_obj[i].dma.RX_DMA_ChInitStr.DstAddr = NULL;
uart_obj[i].dma.RX_DMA_ChInitStr.DstAddr = RT_NULL;
uart_obj[i].dma.RX_DMA_ChInitStr.SrcTfrWidth = DMA_CH_TRANSFER_WIDTH_8;
uart_obj[i].dma.RX_DMA_ChInitStr.DstTfrWidth = DMA_CH_TRANSFER_WIDTH_8;
uart_obj[i].dma.RX_DMA_ChInitStr.DstAddrCountMode = DMA_CH_ADDRESS_COUNT_MODE_INCREMENT;
@ -1645,7 +2101,7 @@ int rt_hw_usart_init(void)
/* Link List Config */
uart_obj[i].dma.rx_dma.Read_LinkList[j].IntEn = 0x1U;
uart_obj[i].dma.rx_dma.Read_LinkList[j].SrcAddr = (uint32_t)&uart_obj[i].config->Instance->DAT;
uart_obj[i].dma.rx_dma.Read_LinkList[j].DstAddr = NULL;
uart_obj[i].dma.rx_dma.Read_LinkList[j].DstAddr = RT_NULL;
uart_obj[i].dma.rx_dma.Read_LinkList[j].SrcTfrWidth = DMA_CH_TRANSFER_WIDTH_8;
uart_obj[i].dma.rx_dma.Read_LinkList[j].DstTfrWidth = DMA_CH_TRANSFER_WIDTH_8;
uart_obj[i].dma.rx_dma.Read_LinkList[j].DstAddrCountMode = DMA_CH_ADDRESS_COUNT_MODE_INCREMENT;
@ -1678,17 +2134,35 @@ int rt_hw_usart_init(void)
/* DMA controller must be enabled before initializing the channel */
DMA_ControllerCmd(uart_obj[i].config->dma_rx->Instance, ENABLE);
#endif
#elif defined(SOC_SERIES_N32H49x) || defined(SOC_SERIES_N32H47x_48x)
/* Configure the UART RX DMA for Receive process */
/* Enable DMA clock */
RCC_EnableAHBPeriphClk(uart_obj[i].config->dma_rx->dma_rcc, ENABLE);
DMA_DeInit(uart_obj[i].config->dma_rx->DMAChx);
DMA_StructInit(&uart_obj[i].dma.RX_DMA_ChInitStr);
uart_obj[i].dma.RX_DMA_ChInitStr.PeriphAddr = (uint32_t)&uart_obj[i].config->Instance->DAT;
uart_obj[i].dma.RX_DMA_ChInitStr.MemAddr = RT_NULL;
uart_obj[i].dma.RX_DMA_ChInitStr.Direction = DMA_DIR_PERIPH_SRC;
uart_obj[i].dma.RX_DMA_ChInitStr.BufSize = 0U;
uart_obj[i].dma.RX_DMA_ChInitStr.PeriphInc = DMA_PERIPH_INC_DISABLE;
uart_obj[i].dma.RX_DMA_ChInitStr.MemoryInc = DMA_MEM_INC_ENABLE;
uart_obj[i].dma.RX_DMA_ChInitStr.PeriphDataSize = DMA_PERIPH_DATA_WIDTH_BYTE;
uart_obj[i].dma.RX_DMA_ChInitStr.MemDataSize = DMA_MEM_DATA_WIDTH_BYTE;
uart_obj[i].dma.RX_DMA_ChInitStr.CircularMode = DMA_MODE_CIRCULAR;
uart_obj[i].dma.RX_DMA_ChInitStr.Priority = DMA_PRIORITY_VERY_HIGH;
uart_obj[i].dma.RX_DMA_ChInitStr.Mem2Mem = DMA_M2M_DISABLE;
DMA_Init(uart_obj[i].config->dma_rx->DMAChx, &uart_obj[i].dma.RX_DMA_ChInitStr);
#endif /* SOC_SERIES_N32H7xx */
}
#endif /* RT_SERIAL_USING_DMA */
/* register UART device */
result = rt_hw_serial_register(&uart_obj[i].serial, uart_obj[i].config->name,
RT_DEVICE_FLAG_RDWR
| RT_DEVICE_FLAG_INT_RX
| RT_DEVICE_FLAG_INT_TX
| uart_obj[i].uart_dma_flag
, NULL);
RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX | RT_DEVICE_FLAG_INT_TX | uart_obj[i].uart_dma_flag, RT_NULL);
RT_ASSERT(result == RT_EOK);
}

37
bsp/n32/n32hxxx/libraries/N32_Drivers/drivers/drv_usart.h
View File

@ -19,8 +19,16 @@
int rt_hw_usart_init(void);
#define UART_RX_DMA_IT_IDLE_FLAG 0x00
#define UART_RX_DMA_IT_BLOCK_TC_FLAG 0x01
#if defined(SOC_SERIES_N32H7xx)
#define UART_RX_DMA_IT_IDLE_FLAG 0x00
#define UART_RX_DMA_IT_BLOCK_TC_FLAG 0x01
#elif defined(SOC_SERIES_N32H49x) || defined(SOC_SERIES_N32H47x_48x)
#define UART_RX_DMA_IT_IDLE_FLAG 0x00
#define UART_RX_DMA_IT_HT_FLAG 0x01
#define UART_RX_DMA_IT_TC_FLAG 0x02
#define UART_CTRL_SET_BLOCK_TIMEOUT 0x20
#endif
/* n32 config class */
struct n32_uart_config
@ -39,8 +47,10 @@ struct n32_uart
{
struct n32_uart_config *config;
rt_uint32_t DR_mask;
rt_uint32_t tx_block_timeout;
#ifdef RT_SERIAL_USING_DMA
#if defined(SOC_SERIES_N32H7xx)
struct
{
rt_bool_t DMA_Tx_Init;
@ -69,8 +79,29 @@ struct n32_uart
} rx_dma;
} dma;
#elif defined(SOC_SERIES_N32H49x) || defined(SOC_SERIES_N32H47x_48x)
struct
{
DMA_InitType TX_DMA_ChInitStr;
struct
{
rt_size_t total_length;
rt_uint8_t *buf;
} tx_dma;
#endif
rt_bool_t tx_dma_inited;
DMA_InitType RX_DMA_ChInitStr;
struct
{
rt_size_t remaining_cnt;
} rx_dma;
rt_bool_t rx_dma_inited;
} dma;
#endif /* SOC_SERIES_N32H7xx */
#endif /* RT_SERIAL_USING_DMA */
rt_uint16_t uart_dma_flag;
struct rt_serial_device serial;
};

180
bsp/n32/n32hxxx/libraries/N32_Drivers/drivers/drv_wdt.c Normal file
View File

@ -0,0 +1,180 @@
/*
* Copyright (c) 2006-2025, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2026-02-24 ox-horse first version
* 2026-06-16 li.mengmeng fix issues and add stop handler
*/
#include <board.h>
#include <rtthread.h>
#ifdef RT_USING_WDT
//#define DRV_DEBUG
#define LOG_TAG "drv.wdt"
#include <drv_log.h>
struct n32_wdt_obj
{
rt_watchdog_t watchdog;
IWDG_Module *IWDGx;
uint32_t IWDG_Clk;
void (*IWDGX_ClkCmd)(uint32_t periph, FunctionalState Cmd);
rt_uint32_t current_threshold_s;
rt_uint32_t Reload;
rt_uint16_t Prescaler;
rt_uint16_t is_start;
};
static struct n32_wdt_obj n32_wdt;
static struct rt_watchdog_ops ops;
static rt_uint32_t wdt_get_prescaler_factor(rt_uint16_t prescaler)
{
switch (prescaler)
{
case IWDG_PRESCALER_DIV4:
return 4;
case IWDG_PRESCALER_DIV8:
return 8;
case IWDG_PRESCALER_DIV16:
return 16;
case IWDG_PRESCALER_DIV32:
return 32;
case IWDG_PRESCALER_DIV64:
return 64;
case IWDG_PRESCALER_DIV128:
return 128;
case IWDG_PRESCALER_DIV256:
default:
return 256;
}
}
static rt_err_t wdt_init(rt_watchdog_t *wdt)
{
n32_wdt.IWDGX_ClkCmd(n32_wdt.IWDG_Clk, ENABLE);
return RT_EOK;
}
static rt_err_t wdt_control(rt_watchdog_t *wdt, int cmd, void *arg)
{
rt_uint32_t reload_value;
rt_uint32_t max_threshold_s;
rt_uint32_t prescaler_factor;
switch (cmd)
{
/* feed the watchdog */
case RT_DEVICE_CTRL_WDT_KEEPALIVE:
IWDG_ReloadKey(n32_wdt.IWDGx);
break;
/* set watchdog timeout */
case RT_DEVICE_CTRL_WDT_SET_TIMEOUT:
#if defined(LSI_VALUE)
if (n32_wdt.is_start)
{
LOG_W("IWDG is already running, cannot change timeout\n");
return -RT_EBUSY;
}
reload_value = (*(rt_uint32_t *)arg);
prescaler_factor = wdt_get_prescaler_factor(n32_wdt.Prescaler);
if (LSI_VALUE)
{
max_threshold_s = ((n32_wdt.Reload + 1U) * prescaler_factor) / LSI_VALUE;
if (reload_value > max_threshold_s)
{
LOG_W("wdg set timeout parameter too large, please less than %d-s\n", max_threshold_s);
return -RT_EINVAL;
}
else
{
n32_wdt.current_threshold_s = reload_value;
/* Calculate Reload Value */
reload_value = (reload_value * (LSI_VALUE / prescaler_factor)) - 1U;
/* Enable write access to IWDG_PR and IWDG_RLR registers */
IWDG_WriteConfig(n32_wdt.IWDGx, IWDG_WRITE_ENABLE);
/* Set IWDG PREDIV */
IWDG_SetPrescalerDiv(n32_wdt.IWDGx, n32_wdt.Prescaler);
/* Set Counter Reload Value */
IWDG_CntReload(n32_wdt.IWDGx, (uint16_t)reload_value);
/* Reload IWDG counter */
IWDG_ReloadKey(n32_wdt.IWDGx);
/* Disable write access to IWDG_PR and IWDG_RLR registers */
IWDG_WriteConfig(n32_wdt.IWDGx, IWDG_WRITE_DISABLE);
}
}
else
{
LOG_E("Please define the value of LSI_VALUE!");
}
#else
#error "Please define the value of LSI_VALUE!"
#endif
break;
case RT_DEVICE_CTRL_WDT_GET_TIMEOUT:
*(rt_uint32_t *)arg = n32_wdt.current_threshold_s;
break;
case RT_DEVICE_CTRL_WDT_START:
if (n32_wdt.is_start)
{
LOG_W("IWDG is already started\n");
return RT_EOK;
}
IWDG_Enable(n32_wdt.IWDGx);
n32_wdt.is_start = 1;
break;
case RT_DEVICE_CTRL_WDT_STOP:
LOG_W("IWDG cannot be stopped once started\n");
return -RT_ENOSYS;
default:
LOG_W("This command is not supported.");
return -RT_ERROR;
}
return RT_EOK;
}
int rt_wdt_init(void)
{
#if defined(SOC_SERIES_N32H7xx)
n32_wdt.IWDGx = IWDG1;
n32_wdt.IWDG_Clk = (RCC_APB5_PERIPHEN_IWDG1PCLK | RCC_APB5_PERIPHEN_IWDG1PCLKLP);
n32_wdt.IWDGX_ClkCmd = RCC_EnableAPB5PeriphClk2;
#endif
n32_wdt.Prescaler = IWDG_PRESCALER_DIV256;
n32_wdt.Reload = 0xFFFU;
n32_wdt.is_start = 0U;
ops.init = &wdt_init;
ops.control = &wdt_control;
n32_wdt.watchdog.ops = &ops;
/* register watchdog device */
if (rt_hw_watchdog_register(&n32_wdt.watchdog, "wdt", RT_DEVICE_FLAG_DEACTIVATE, RT_NULL) != RT_EOK)
{
LOG_E("wdt device register failed.");
return -RT_ERROR;
}
LOG_D("wdt device register success.");
return RT_EOK;
}
INIT_BOARD_EXPORT(rt_wdt_init);
#endif /* RT_USING_WDT */

8
bsp/n32/n32hxxx/libraries/N32_Drivers/drv_common.c
View File

@ -42,13 +42,21 @@ static uint32_t _systick_ms = 1;
/* SysTick configuration */
void rt_hw_systick_init(void)
{
#if defined(SOC_SERIES_N32H7xx)
RCC_ClocksTypeDef RCC_Clocks = { 0 };
#elif defined(SOC_SERIES_N32H47x_48x) || defined(SOC_SERIES_N32H49x)
RCC_ClocksType RCC_Clocks = { 0 };
#endif
/* Get clock frequency */
RCC_GetClocksFreqValue(&RCC_Clocks);
/* Set Systick */
#if defined(SOC_SERIES_N32H7xx)
SysTick_Config(RCC_Clocks.M7ClkFreq / RT_TICK_PER_SECOND);
#elif defined(SOC_SERIES_N32H47x_48x) || defined(SOC_SERIES_N32H49x)
SysTick_Config(RCC_Clocks.SysclkFreq / RT_TICK_PER_SECOND);
#endif
NVIC_SetPriorityGrouping(SCB_AIRCR_PRIGROUP3);
NVIC_SetPriority(SysTick_IRQn, 0xFF);

96
bsp/n32/n32hxxx/libraries/N32_Drivers/nano/drv_console.c
View File

@ -12,82 +12,152 @@
#include <rtthread.h>
#include <drv_common.h>
static USART_Module* USARTx;
static USART_Module *USARTx;
void rt_hw_console_init(void)
{
USART_InitType USART_InitStructure;
#if defined(SOC_SERIES_N32H7xx)
RCC_EnableAHB5PeriphClk2(RCC_AHB5_PERIPHEN_M7_AFIO, ENABLE);
#elif defined(SOC_SERIES_N32H49x)
RCC_EnableAPB2PeriphClk(RCC_APB2_PERIPHEN_AFIO, ENABLE);
#elif defined(SOC_SERIES_N32H47x_48x)
RCC_EnableAPB2PeriphClk(RCC_APB2_PERIPH_AFIO, ENABLE);
#endif
#ifdef USART1
if (rt_strcmp(RT_CONSOLE_DEVICE_NAME, "uart1") == 0)
{
#if defined(SOC_SERIES_N32H7xx)
RCC_EnableAPB1PeriphClk3(RCC_APB1_PERIPHEN_M7_USART1, ENABLE);
#elif defined(SOC_SERIES_N32H49x)
RCC_EnableAPB2PeriphClk(RCC_APB2_PERIPHEN_USART1, ENABLE);
#elif defined(SOC_SERIES_N32H47x_48x)
RCC_EnableAPB2PeriphClk(RCC_APB2_PERIPH_USART1, ENABLE);
#endif
USARTx = USART1;
}
#endif /* USART1 */
#ifdef USART2
else if (rt_strcmp(RT_CONSOLE_DEVICE_NAME, "uart2") == 0)
{
#if defined(SOC_SERIES_N32H7xx)
RCC_EnableAPB1PeriphClk3(RCC_APB1_PERIPHEN_M7_USART2, ENABLE);
#elif defined(SOC_SERIES_N32H49x)
RCC_EnableAPB1PeriphClk(RCC_APB1_PERIPHEN_USART2, ENABLE);
#elif defined(SOC_SERIES_N32H47x_48x)
RCC_EnableAPB1PeriphClk(RCC_APB1_PERIPH_USART2, ENABLE);
#endif
USARTx = USART2;
}
#endif /* USART2 */
#ifdef USART3
else if (rt_strcmp(RT_CONSOLE_DEVICE_NAME, "uart3") == 0)
{
#if defined(SOC_SERIES_N32H7xx)
RCC_EnableAPB1PeriphClk3(RCC_APB1_PERIPHEN_M7_USART3, ENABLE);
#elif defined(SOC_SERIES_N32H49x)
RCC_EnableAPB1PeriphClk(RCC_APB1_PERIPHEN_USART3, ENABLE);
#elif defined(SOC_SERIES_N32H47x_48x)
RCC_EnableAPB1PeriphClk(RCC_APB1_PERIPH_USART3, ENABLE);
#endif
USARTx = USART3;
}
#endif /* USART3 */
#ifdef USART4
else if (rt_strcmp(RT_CONSOLE_DEVICE_NAME, "uart4") == 0)
{
#if defined(SOC_SERIES_N32H7xx)
RCC_EnableAPB1PeriphClk3(RCC_APB1_PERIPHEN_M7_USART4, ENABLE);
#elif defined(SOC_SERIES_N32H49x)
RCC_EnableAPB2PeriphClk(RCC_APB2_PERIPHEN_USART4, ENABLE);
#elif defined(SOC_SERIES_N32H47x_48x)
RCC_EnableAPB2PeriphClk(RCC_APB2_PERIPH_USART4, ENABLE);
#endif
USARTx = USART4;
}
#endif /* USART4 */
#ifdef USART5
#if defined(USART5) || defined(UART5)
else if (rt_strcmp(RT_CONSOLE_DEVICE_NAME, "uart5") == 0)
{
#if defined(SOC_SERIES_N32H7xx)
RCC_EnableAPB2PeriphClk3(RCC_APB2_PERIPHEN_M7_USART5, ENABLE);
USARTx = USART5;
#elif defined(SOC_SERIES_N32H49x)
RCC_EnableAPB1PeriphClk(RCC_APB1_PERIPHEN_UART5, ENABLE);
USARTx = UART5;
#elif defined(SOC_SERIES_N32H47x_48x)
RCC_EnableAPB1PeriphClk(RCC_APB1_PERIPH_UART5, ENABLE);
USARTx = UART5;
#endif
}
#endif /* USART5 */
#ifdef USART6
#endif /* defined(USART5) || defined(UART5) */
#if defined(USART6) || defined(UART6)
else if (rt_strcmp(RT_CONSOLE_DEVICE_NAME, "uart6") == 0)
{
#if defined(SOC_SERIES_N32H7xx)
RCC_EnableAPB2PeriphClk3(RCC_APB2_PERIPHEN_M7_USART6, ENABLE);
USARTx = USART6;
#elif defined(SOC_SERIES_N32H49x)
RCC_EnableAPB2PeriphClk(RCC_APB2_PERIPHEN_UART6, ENABLE);
USARTx = UART6;
#elif defined(SOC_SERIES_N32H47x_48x)
RCC_EnableAPB2PeriphClk(RCC_APB2_PERIPH_UART6, ENABLE);
USARTx = UART6;
#endif
}
#endif /* USART6 */
#ifdef USART7
#endif /* defined(USART6) || defined(UART6) */
#if defined(USART7) || defined(UART7)
else if (rt_strcmp(RT_CONSOLE_DEVICE_NAME, "uart7") == 0)
{
#if defined(SOC_SERIES_N32H7xx)
RCC_EnableAPB2PeriphClk3(RCC_APB2_PERIPHEN_M7_USART7, ENABLE);
USARTx = USART7;
#elif defined(SOC_SERIES_N32H49x)
RCC_EnableAPB2PeriphClk(RCC_APB2_PERIPHEN_UART7, ENABLE);
USARTx = UART7;
#elif defined(SOC_SERIES_N32H47x_48x)
RCC_EnableAPB2PeriphClk(RCC_APB2_PERIPH_UART7, ENABLE);
USARTx = UART7;
#endif
}
#endif /* USART7 */
#ifdef USART8
#endif /* defined(USART7) || defined(UART7) */
#if defined(USART8) || defined(UART8)
else if (rt_strcmp(RT_CONSOLE_DEVICE_NAME, "uart8") == 0)
{
#if defined(SOC_SERIES_N32H7xx)
RCC_EnableAPB2PeriphClk3(RCC_APB2_PERIPHEN_M7_USART8, ENABLE);
USARTx = USART8;
#elif defined(SOC_SERIES_N32H49x)
RCC_EnableAPB1PeriphClk(RCC_APB1_PERIPHEN_UART8, ENABLE);
USARTx = UART8;
#elif defined(SOC_SERIES_N32H47x_48x)
RCC_EnableAPB1PeriphClk(RCC_APB1_PERIPH_UART8, ENABLE);
USARTx = UART8;
#endif
}
#endif /* USART8 */
#ifdef UART9
#endif /* defined(USART8) || defined(UART8) */
#if defined(USART9) || defined(UART9)
else if (rt_strcmp(RT_CONSOLE_DEVICE_NAME, "uart9") == 0)
{
#if defined(SOC_SERIES_N32H7xx)
RCC_EnableAPB1PeriphClk3(RCC_APB1_PERIPHEN_M7_UART9, ENABLE);
USARTx = UART9;
#elif defined(SOC_SERIES_N32H49x)
RCC_EnableAPB2PeriphClk(RCC_APB2_PERIPHEN_USART9, ENABLE);
USARTx = USART9;
#endif
}
#endif /* UART9 */
#endif /* defined(USART9) || defined(UART9) */
#ifdef UART10
else if (rt_strcmp(RT_CONSOLE_DEVICE_NAME, "uart10") == 0)
{
#if defined(SOC_SERIES_N32H7xx)
RCC_EnableAPB1PeriphClk3(RCC_APB1_PERIPHEN_M7_UART10, ENABLE);
#elif defined(SOC_SERIES_N32H49x)
RCC_EnableAPB2PeriphClk(RCC_APB2_PERIPHEN_UART10, ENABLE);
#endif
USARTx = UART10;
}
#endif /* UART10 */
@ -161,7 +231,7 @@ void rt_hw_console_output(const char *str)
while (USART_GetFlagStatus(USARTx, USART_FLAG_TXC) == RESET);
USART_SendData(USARTx, (uint8_t )(*(str + i)));
USART_SendData(USARTx, (uint8_t)(*(str + i)));
}
}

104
bsp/n32/n32hxxx/libraries/N32_Drivers/nano/drv_gpio.c
View File

@ -25,56 +25,88 @@ void rt_pin_mode(rt_uint64_t pin, rt_uint8_t mode)
mode == PIN_MODE_INPUT_PULLUP || mode == PIN_MODE_INPUT_PULLDOWN ||
mode == PIN_MODE_OUTPUT_OD);
switch((rt_ubase_t)GPIOx)
switch ((rt_ubase_t)GPIOx)
{
case (rt_ubase_t)GPIOA:
RCC_EnableAHB5PeriphClk1(RCC_AHB5_PERIPHEN_M7_GPIOA, ENABLE);
break;
case (rt_ubase_t)GPIOB:
RCC_EnableAHB5PeriphClk1(RCC_AHB5_PERIPHEN_M7_GPIOB, ENABLE);
break;
case (rt_ubase_t)GPIOC:
RCC_EnableAHB5PeriphClk1(RCC_AHB5_PERIPHEN_M7_GPIOC, ENABLE);
break;
case (rt_ubase_t)GPIOA:
#if defined(SOC_SERIES_N32H7xx)
RCC_EnableAHB5PeriphClk1(RCC_AHB5_PERIPHEN_M7_GPIOA, ENABLE);
#elif defined(SOC_SERIES_N32H49x) || defined(SOC_SERIES_N32H47x_48x)
RCC_EnableAHB1PeriphClk(RCC_AHB_PERIPHEN_GPIOA, ENABLE);
#endif
break;
case (rt_ubase_t)GPIOB:
#if defined(SOC_SERIES_N32H7xx)
RCC_EnableAHB5PeriphClk1(RCC_AHB5_PERIPHEN_M7_GPIOB, ENABLE);
#elif defined(SOC_SERIES_N32H49x) || defined(SOC_SERIES_N32H47x_48x)
RCC_EnableAHB1PeriphClk(RCC_AHB_PERIPHEN_GPIOB, ENABLE);
#endif
break;
case (rt_ubase_t)GPIOC:
#if defined(SOC_SERIES_N32H7xx)
RCC_EnableAHB5PeriphClk1(RCC_AHB5_PERIPHEN_M7_GPIOC, ENABLE);
#elif defined(SOC_SERIES_N32H49x) || defined(SOC_SERIES_N32H47x_48x)
RCC_EnableAHB1PeriphClk(RCC_AHB_PERIPHEN_GPIOC, ENABLE);
#endif
break;
#ifdef GPIOD
case (rt_ubase_t)GPIOD:
RCC_EnableAHB5PeriphClk1(RCC_AHB5_PERIPHEN_M7_GPIOD, ENABLE);
break;
case (rt_ubase_t)GPIOD:
#if defined(SOC_SERIES_N32H7xx)
RCC_EnableAHB5PeriphClk1(RCC_AHB5_PERIPHEN_M7_GPIOD, ENABLE);
#elif defined(SOC_SERIES_N32H49x) || defined(SOC_SERIES_N32H47x_48x)
RCC_EnableAHB1PeriphClk(RCC_AHB_PERIPHEN_GPIOD, ENABLE);
#endif
break;
#endif /* GPIOD */
#ifdef GPIOE
case (rt_ubase_t)GPIOE:
RCC_EnableAHB5PeriphClk1(RCC_AHB5_PERIPHEN_M7_GPIOE, ENABLE);
break;
case (rt_ubase_t)GPIOE:
#if defined(SOC_SERIES_N32H7xx)
RCC_EnableAHB5PeriphClk1(RCC_AHB5_PERIPHEN_M7_GPIOE, ENABLE);
#elif defined(SOC_SERIES_N32H49x) || defined(SOC_SERIES_N32H47x_48x)
RCC_EnableAHB1PeriphClk(RCC_AHB_PERIPHEN_GPIOE, ENABLE);
#endif
break;
#endif /* GPIOE */
#ifdef GPIOF
case (rt_ubase_t)GPIOF:
RCC_EnableAHB5PeriphClk1(RCC_AHB5_PERIPHEN_M7_GPIOF, ENABLE);
break;
case (rt_ubase_t)GPIOF:
#if defined(SOC_SERIES_N32H7xx)
RCC_EnableAHB5PeriphClk1(RCC_AHB5_PERIPHEN_M7_GPIOF, ENABLE);
#elif defined(SOC_SERIES_N32H49x) || defined(SOC_SERIES_N32H47x_48x)
RCC_EnableAHB1PeriphClk(RCC_AHB_PERIPHEN_GPIOF, ENABLE);
#endif
break;
#endif /* GPIOF */
#ifdef GPIOG
case (rt_ubase_t)GPIOG:
RCC_EnableAHB5PeriphClk1(RCC_AHB5_PERIPHEN_M7_GPIOG, ENABLE);
break;
case (rt_ubase_t)GPIOG:
#if defined(SOC_SERIES_N32H7xx)
RCC_EnableAHB5PeriphClk1(RCC_AHB5_PERIPHEN_M7_GPIOG, ENABLE);
#elif defined(SOC_SERIES_N32H49x) || defined(SOC_SERIES_N32H47x_48x)
RCC_EnableAHB1PeriphClk(RCC_AHB_PERIPHEN_GPIOG, ENABLE);
#endif
break;
#endif /* GPIOG */
#ifdef GPIOH
case (rt_ubase_t)GPIOH:
RCC_EnableAHB5PeriphClk1(RCC_AHB5_PERIPHEN_M7_GPIOH, ENABLE);
break;
case (rt_ubase_t)GPIOH:
#if defined(SOC_SERIES_N32H7xx)
RCC_EnableAHB5PeriphClk1(RCC_AHB5_PERIPHEN_M7_GPIOH, ENABLE);
#elif defined(SOC_SERIES_N32H49x) || defined(SOC_SERIES_N32H47x_48x)
RCC_EnableAHB1PeriphClk(RCC_AHB_PERIPHEN_GPIOH, ENABLE);
#endif
break;
#endif /* GPIOH */
#ifdef GPIOI
case (rt_ubase_t)GPIOI:
RCC_EnableAHB5PeriphClk2(RCC_AHB5_PERIPHEN_M7_GPIOI, ENABLE);
break;
case (rt_ubase_t)GPIOI:
RCC_EnableAHB5PeriphClk2(RCC_AHB5_PERIPHEN_M7_GPIOI, ENABLE);
break;
#endif /* GPIOI */
#ifdef GPIOj
case (rt_ubase_t)GPIOj:
RCC_EnableAHB5PeriphClk2(RCC_AHB5_PERIPHEN_M7_GPIOJ, ENABLE);
break;
case (rt_ubase_t)GPIOj:
RCC_EnableAHB5PeriphClk2(RCC_AHB5_PERIPHEN_M7_GPIOJ, ENABLE);
break;
#endif /* GPIOj */
#ifdef GPIOk
case (rt_ubase_t)GPIOk:
RCC_EnableAHB5PeriphClk2(RCC_AHB5_PERIPHEN_M7_GPIOK, ENABLE);
break;
case (rt_ubase_t)GPIOk:
RCC_EnableAHB5PeriphClk2(RCC_AHB5_PERIPHEN_M7_GPIOK, ENABLE);
break;
#endif /* GPIOk */
}
@ -122,7 +154,11 @@ void rt_pin_write(rt_uint64_t pin, rt_uint8_t value)
RT_ASSERT(value == PIN_LOW || value == PIN_HIGH);
#if defined(SOC_SERIES_N32H7xx)
GPIO_WriteBit(GPIOx, GPIO_Pin, ((value == PIN_LOW) ? Bit_RESET : Bit_SET));
#elif defined(SOC_SERIES_N32H49x) || defined(SOC_SERIES_N32H47x_48x)
GPIO_WriteBits(GPIOx, GPIO_Pin, ((value == PIN_LOW) ? Bit_RESET : Bit_SET));
#endif
}
rt_int8_t rt_pin_read(rt_uint64_t pin)

10
bsp/n32/n32hxxx/n32h487zgl7-evb/.ci/attachconfig/ci.attachconfig.yml Normal file
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@ -0,0 +1,10 @@
scons.args: &scons
scons_arg:
- '--strict'
# ------ nano ------
nano:
<<: *scons
kconfig:
- CONFIG_RT_USING_NANO=y

1507
bsp/n32/n32hxxx/n32h487zgl7-evb/.config Normal file
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File diff suppressed because it is too large Load Diff

41
bsp/n32/n32hxxx/n32h487zgl7-evb/.gitignore vendored Normal file
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@ -0,0 +1,41 @@
*.pyc
*.map
*.dblite
*.elf
*.bin
*.hex
*.axf
*.exe
*.pdb
*.idb
*.ilk
*.old
build
Debug
documentation/html
*~
*.o
*.obj
*.out
*.bak
*.dep
*.lib
*.i
*.d
.DS_Stor*
.config 3
.config 4
.config 5
Midea-X1
*.uimg
GPATH
GRTAGS
GTAGS
.vscode
JLinkLog.txt
JLinkSettings.ini
DebugConfig/
RTE/
settings/
*.uvguix*
cconfig.h

22
bsp/n32/n32hxxx/n32h487zgl7-evb/Kconfig Normal file
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@ -0,0 +1,22 @@
mainmenu "RT-Thread Configuration"
BSP_DIR := .
RTT_DIR := ../../../..
PKGS_DIR := packages
config SOC_N32H488ZEL7
bool
select SOC_SERIES_N32H47x_48x
select RT_USING_COMPONENTS_INIT
select RT_USING_USER_MAIN
default y
source "$(RTT_DIR)/Kconfig"
osource "$PKGS_DIR/Kconfig"
rsource "../libraries/Kconfig"
if !RT_USING_NANO
rsource "board/Kconfig"
endif

116
bsp/n32/n32hxxx/n32h487zgl7-evb/README.md Normal file
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@ -0,0 +1,116 @@
# N32H488ZEL7 开发板 BSP 说明
## 简介
本文档为 RT-Thread 开发团队为 N32H488ZEL7 开发板提供的 BSP (板级支持包) 说明。
主要内容如下：
- 开发板资源介绍
- BSP 快速上手
- 进阶使用方法
通过阅读快速上手章节开发者可以快速地上手该 BSP，将 RT-Thread 运行在开发板上。在进阶使用指南章节，将会介绍更多高级功能，帮助开发者利用 RT-Thread 驱动更多板载资源。
## 开发板介绍
N32H488ZEL7_EVB V1.1 是 Nsing 推出的一款基于 ARM Cortex-M4 内核的开发板，最高主频为 240Mhz，该开发板具有丰富的板载资源，可以充分发挥 N32H488 的芯片性能。
开发板外观如下图所示：
![board](figures/board.jpg)
该开发板常用 **板载资源** 如下：
- MCU：N32H488ZEL7，主频 240MHz，512KB FLASH ，160KB RAM
- 外部 PSRAM：IS66WV51216EBLL（FEMC）
- 外部 EEROM：AT24C02
- 外部 FLASH：W25Q128JVSIQTR（SPI）、P25Q40HA-SSH-IT（XSPI）、IS34ML01G081-TLI（FEMC-NAND）
- 常用外设
- LED：3个，LED1（PA3），LED2（PB4），LED3（PA8）
- 按键：4个，WKUP（兼具唤醒功能，PA0），KEY1（PC13），KEY2（PA15），KEY3（PC8）
- 常用接口：USB 转串口、CAN 接口、RS485 接口、LIN 接口、以太网接口
- 调试接口，标准 JTAG/SWD
## 外设支持
本 BSP 目前对外设的支持情况如下：
| **片上外设** | **支持情况** | **备注** |
| GPIO | 支持 | PA0, PA1... PH6 ---> PIN: 0, 1...118 |
| UART | 支持 | UART1/2/3, 如需使用该外设，请使用 Cube 重新配 |
## 使用说明
使用说明分为如下两个章节：
- 快速上手
本章节是为刚接触 RT-Thread 的新手准备的使用说明，遵循简单的步骤即可将 RT-Thread 操作系统运行在该开发板上，看到实验效果 。
- 进阶使用
本章节是为需要在 RT-Thread 操作系统上使用更多开发板资源的开发者准备的。通过使用 ENV 工具对 BSP 进行配置，可以开启更多板载资源，实现更多高级功能。
### 快速上手
本 BSP 为开发者提供 MDK5 和 IAR 工程，并且支持 GCC 开发环境。下面以 MDK5 开发环境为例，介绍如何将系统运行起来。
**请注意！！！**
在执行编译工作前请先打开ENV执行以下指令（该指令用于拉取必要的 STD 库及 CMSIS 库，否则无法通过编译）：
```bash
pkgs --update
```
#### 硬件连接
使用数据线连接开发板到 PC，打开电源开关。
#### 编译下载
双击 project.uvprojx 文件，打开 MDK5 工程，编译并下载程序到开发板。
> 工程默认配置使用 CMSIS-DAP 下载程序，在通过 USB 线连接开发板的基础上，点击下载按钮即可下载程序到开发板
#### 运行结果
下载程序成功之后，系统会自动运行，观察开发板上 LED1 的运行效果，LED1 会周期性闪烁。
连接开发板对应串口到 PC , 在终端工具里打开相应的串口（115200-8-1-N），复位设备后，可以看到 RT-Thread 的输出信息:
```bash
\ | /
- RT - Thread Operating System
/ | \ 5.3.0 build Jul 16 2026 11:18:41
2006 - 2024 Copyright by RT-Thread team
msh >
```
### 进阶使用
此 BSP 默认只开启了 GPIO 和 串口1 的功能，如果需使用更多高级功能，需要利用 ENV 工具对BSP 进行配置，步骤如下：
1. 在 bsp 下打开 env 工具。
2. 输入`menuconfig`命令配置工程，配置好之后保存退出。
3. 输入`pkgs --update`命令更新软件包。
4. 输入`scons --target=mdk5/iar` 命令重新生成工程。
## 注意事项
- 调试串口为串口 1 映射说明
PA9 ------> USART1_TX
PA10 ------> USART1_RX
## 联系人信息
维护人:
- [OnlyoutzZ](https://github.com/OnlyoutzZ)

3
bsp/n32g452xx/n32g452xx-mini-system/SConscript → bsp/n32/n32hxxx/n32h487zgl7-evb/SConscript Executable file → Normal file
View File

@ -1,12 +1,15 @@
# for module compiling
import os
Import('RTT_ROOT')
Import('env')
from building import *
cwd = GetCurrentDir()
objs = []
list = os.listdir(cwd)
env.Append(CPPDEFINES = ['N32H488'])
for d in list:
path = os.path.join(cwd, d)
if os.path.isfile(os.path.join(path, 'SConscript')):

74
bsp/n32/n32hxxx/n32h487zgl7-evb/SConstruct Normal file
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@ -0,0 +1,74 @@
import os
import sys
import rtconfig
if os.getenv('RTT_ROOT'):
RTT_ROOT = os.getenv('RTT_ROOT')
else:
RTT_ROOT = os.path.normpath(os.getcwd() + '/../../../..')
sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')]
try:
from building import *
except:
print('Cannot found RT-Thread root directory, please check RTT_ROOT')
print(RTT_ROOT)
exit(-1)
def bsp_pkg_check():
import subprocess
check_paths = [
os.path.join("packages", "CMSIS-Core-latest"),
os.path.join("packages", "n32h47x_48x_cmsis_driver-latest"),
os.path.join("packages", "n32h47x_48x_std_driver-latest")
]
need_update = not all(os.path.exists(p) for p in check_paths)
if need_update:
print("\n===============================================================================")
print("Dependency packages missing, please running 'pkgs --update'...")
print("If no packages are fetched, run 'pkgs --upgrade' first, then 'pkgs --update'...")
print("===============================================================================")
exit(1)
RegisterPreBuildingAction(bsp_pkg_check)
TARGET = 'rt-thread.' + rtconfig.TARGET_EXT
DefaultEnvironment(tools=[])
env = Environment(tools = ['mingw'],
AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS,
CC = rtconfig.CC, CFLAGS = rtconfig.CFLAGS,
AR = rtconfig.AR, ARFLAGS = '-rc',
CXX = rtconfig.CXX, CXXFLAGS = rtconfig.CXXFLAGS,
LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS)
env.PrependENVPath('PATH', rtconfig.EXEC_PATH)
if rtconfig.PLATFORM in ['iccarm']:
env.Replace(CCCOM = ['$CC $CFLAGS $CPPFLAGS $_CPPDEFFLAGS $_CPPINCFLAGS -o $TARGET $SOURCES'])
env.Replace(ARFLAGS = [''])
env.Replace(LINKCOM = env["LINKCOM"] + ' --map rt-thread.map')
Export('env')
Export('RTT_ROOT')
Export('rtconfig')
SDK_ROOT = os.path.abspath('./')
if os.path.exists(SDK_ROOT + '/libraries'):
libraries_path_prefix = SDK_ROOT + '/libraries'
else:
libraries_path_prefix = os.path.dirname(SDK_ROOT) + '/libraries'
# prepare building environment
objs = PrepareBuilding(env, RTT_ROOT, has_libcpu=False)
rtconfig.BSP_LIBRARY_TYPE = None
# include drivers
objs.extend(SConscript(os.path.join(libraries_path_prefix, 'N32_Drivers', 'SConscript'),variant_dir='build/libraries/N32_Drivers', duplicate=0))
# make a building
DoBuilding(TARGET, objs)

4
bsp/n32g452xx/n32g452xx-mini-system/applications/SConscript → bsp/n32/n32hxxx/n32h487zgl7-evb/applications/SConscript Executable file → Normal file
View File

@ -1,9 +1,9 @@
from building import *
import os
cwd = GetCurrentDir()
src = Glob('*.c')
cwd = GetCurrentDir()
CPPPATH = [cwd]
src = ['main.c']
group = DefineGroup('Applications', src, depend = [''], CPPPATH = CPPPATH)

33
bsp/n32/n32hxxx/n32h487zgl7-evb/applications/main.c Normal file
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@ -0,0 +1,33 @@
/*
* Copyright (c) 2006-2026, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2026-07-15 ox-horse first version
*/
#include <board.h>
#include <rtthread.h>
#include <drv_gpio.h>
#ifndef RT_USING_NANO
#include <rtdevice.h>
#endif /* RT_USING_NANO */
/* defined the LED1 pin: PA3 */
#define LED1_PIN GET_PIN(A, 3)
int main(void)
{
/* set LED1 pin mode to output */
rt_pin_mode(LED1_PIN, PIN_MODE_OUTPUT);
while (1)
{
rt_pin_write(LED1_PIN, PIN_HIGH);
rt_thread_mdelay(500);
rt_pin_write(LED1_PIN, PIN_LOW);
rt_thread_mdelay(500);
}
}

BIN
bsp/n32/n32hxxx/n32h487zgl7-evb/board/Cube_Config/Cube_Config.ntfx Normal file
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33
bsp/n32/n32hxxx/n32h487zgl7-evb/board/Cube_Config/USER/inc/n32h47x_48x_cfg.h Normal file
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@ -0,0 +1,33 @@
/**
* @file n32h47x_48x_cfg.h
* @author N32cube
*/
#ifndef __N32H47X_48X_CFG_H__
#define __N32H47X_48X_CFG_H__
#ifdef __cplusplus
extern "C" {
#endif
/* NTFx CODE START INCLUDE*/
#include "n32h47x_48x.h"
#include "n32h47x_48x_conf.h"
/* NTFx CODE END INCLUDE*/
/* NTFx CODE START Extern*/
extern void SysTick_Delayms(uint32_t Delayms);
extern void DMA_SetPerMemAddr(DMA_ChannelType* DMAChx, uint32_t periphAddr, uint32_t memAddr, uint32_t bufSize);
extern bool RCC_Configuration(void);
extern bool GPIO_Configuration(void);
extern bool NVIC_Configuration(void);
extern bool DMA_Configuration(void);
extern bool USART_Configuration(void);
/* NTFx CODE END Extern*/
#ifdef __cplusplus
}
#endif
#endif /* __N32H47X_48X_CFG_H__ */
/**
* @}
*/

265
bsp/n32/n32hxxx/n32h487zgl7-evb/board/Cube_Config/USER/src/n32h47x_48x_cfg.c Normal file
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@ -0,0 +1,265 @@
/**
* @file n32h47x_48x_cfg.c
* @author N32cube
*/
#include "n32h47x_48x_cfg.h"
/* NTFx CODE START */
__IO uint32_t mwTick;
void SysTick_Delayms(uint32_t Delayms)
{
uint32_t tickstart = mwTick;
uint32_t wait = Delayms;
/* Add 1 to guarantee minimum wait */
if (wait < 0xFFFFFFFFU)
{
wait += 1;
}
while ((mwTick - tickstart) < wait)
{
}
}
/**
*@name DMA_SetPerMemAddr.
*@brief Set peripher address and memory address of DMA
*@param DMAChx (The input parameters must be the following values):
* - DMA1_CH1
* - DMA1_CH2
* - DMA1_CH3
* - DMA1_CH4
* - DMA1_CH5
* - DMA1_CH6
* - DMA1_CH7
* - DMA1_CH8
* - DMA2_CH1
* - DMA2_CH2
* - DMA2_CH3
* - DMA2_CH4
* - DMA2_CH5
* - DMA2_CH6
* - DMA2_CH7
* - DMA2_CH8
*@param periphAddr peripher address
*@param memAddr memory address
*@param bufSize buff size
*@return status
*/
void DMA_SetPerMemAddr(DMA_ChannelType* DMAChx, uint32_t periphAddr, uint32_t memAddr, uint32_t bufSize)
{
/* DMAy Channelx TXNUM Configuration */
/* Write to DMAy Channelx TXNUM */
DMAChx->TXNUM = bufSize;
/* DMAy Channelx PADDR Configuration */
/* Write to DMAy Channelx PADDR */
DMAChx->PADDR = periphAddr;
/* DMAy Channelx MADDR Configuration */
/* Write to DMAy Channelx MADDR */
DMAChx->MADDR = memAddr;
}
/**
*@name RCC_InitSHRTPLL.
*@brief Initialze the SHRTPLL clock source and multiplication factor.
*@param SHRTPLL_source(SHRTPLL entry clock source):
* - RCC_SHRTPLL_SRC_HSI HSI oscillator clock selected as SHRTPLL clock entry
* - RCC_SHRTPLL_SRC_HSE HSE oscillator clock selected as SHRTPLL clock entry
*@param CLKF(SHRTPLL Multiple coefficient)
*@param CLKR(SHRTPLL division coefficient)
*@param BWTRIM(Bandwidth adjustment)
*@return none:
*note SHRTPLL = SHRTPLL_source*(CLKF[25:0]/16384)/(CLKR[5:0] +1)/4
*/
void RCC_InitSHRTPLL(uint32_t SHRTPLL_source, uint32_t CLKF, uint32_t CLKR, uint32_t BWTRIM)
{
uint32_t temp_value1, temp_value2, temp_value3;
/* Enable SHRTPLL module power */
RCC->SHRTPLLCTRL3 |= RCC_SHRTPLL_ENABLE;
/* Select Clock Source */
temp_value3 = RCC->SHRTPLLCTRL3;
temp_value3 &= RCC_SHRTPLL_SRC_MASK;
temp_value3 |= SHRTPLL_source;
RCC->SHRTPLLCTRL3 = temp_value3;
/* Configure the work mode to normal */
RCC->SHRTPLLCTRL1 &= (~RCC_SHRTPLLMODE_PD);
/* Enable Saturation and fraction accumulation function */
RCC->SHRTPLLCTRL1 |= (RCC_SHRTPLL_SATEN | RCC_SHRTPLL_FRACEN);
/* get the SHRTPLL value */
temp_value1 = RCC->SHRTPLLCTRL1;
temp_value2 = RCC->SHRTPLLCTRL2;
temp_value3 = RCC->SHRTPLLCTRL3;
/* Clear CLKF[25:0] bits */
temp_value1 &= RCC_SHRTPLL_CLKF_MASK;
/* Clear CLKR[5:0] bits */
temp_value2 &= RCC_SHRTPLL_CLKR_MASK;
/* Clear BWTRIM[11:0] bits */
temp_value3 &= RCC_SHRTPLL_BWTRIM_MASK;
/* Set CLKF[25:0] bits */
temp_value1 |= (uint32_t)CLKF;
/* Set CLKR[5:0] bits */
temp_value2 |= ((uint32_t)CLKR << 26);
/* Set BWTRIM[11:0] bits */
temp_value3 |= ((uint32_t)BWTRIM << 12);
/* Store the new value */
RCC->SHRTPLLCTRL1 = temp_value1;
RCC->SHRTPLLCTRL2 = temp_value2;
RCC->SHRTPLLCTRL3 = temp_value3;
/* Reset SHRTPLL */
RCC_EnableAHBPeriphReset(RCC_AHB_PERIPHRST_SHRTPLL);
}
/* NTFx CODE END */
/* NTFx CODE START */
/**
*@brief Initializes the clock tree
*@param null
*@return status
*/
bool RCC_Configuration(void)
{
ErrorStatus ClockStatus;
RCC_DeInit();
RCC_EnableHsi(ENABLE);
/* Wait till HSI is ready */
ClockStatus = RCC_WaitHsiStable();
if (ClockStatus != SUCCESS) return false;
RCC_ConfigPll(RCC_PLL_SRC_HSI, RCC_PLL_PRE_2, RCC_PLL_MUL_60, RCC_PLLOUT_DIV_1);
/* Enable PLL */
RCC_EnablePll(ENABLE);
/* Wait till PLL is ready */
while (RCC_GetFlagStatus(RCC_FLAG_PLLRDF) != SET);
RCC_ConfigHclk(RCC_SYSCLK_DIV1);
RCC_ConfigPclk2(RCC_HCLK_DIV2);
RCC_ConfigPclk1(RCC_HCLK_DIV2);
/* Disable Prefetch Buffer */
FLASH_PrefetchBufSet(FLASH_PrefetchBuf_DIS);
FLASH_iCacheCmd(FLASH_iCache_EN);
/* Flash wait state */
FLASH_SetLatency(FLASH_LATENCY_5);
/*config RNG clock*/
RCC_ConfigTrng1mClk(RCC_TRNG1MCLK_SRC_HSI, RCC_TRNG1MCLK_DIV8);
RCC_EnableTrng1mClk(ENABLE);
RCC_ConfigRngcClk(RCC_RNGCCLK_SYSCLK_DIV1);
/*config TRACE clock*/
RCC_ConfigTraceClk(RCC_TRACECLK_DIV1);
/* Select PLL as system clock source */
RCC_ConfigSysclk(RCC_SYSCLK_SRC_PLL);
/* Wait till PLL is used as system clock source */
while (RCC_GetSysclkSrc() != RCC_CFG_SCLKSTS_PLL) ;
/* Configure the SysTick to have interrupt in 1ms time basis*/
SysTick_Config(240000);
/* NTFx CODE END */
return true;
}
/* NTFx CODE START */
/**
*@brief Initializes the GPIO
*@param null
*@return status
*/
bool GPIO_Configuration(void)
{
GPIO_InitType GPIO_InitStructure;
GPIO_InitStruct(&GPIO_InitStructure);
/* Enable the GPIO clock*/
RCC_EnableAHB1PeriphClk(RCC_AHB_PERIPHEN_GPIOA | RCC_AHB_PERIPHEN_GPIOH, ENABLE);
RCC_EnableAPB2PeriphClk(RCC_APB2_PERIPH_AFIO, ENABLE);
/*Initialize AF_PP GPIO */
GPIO_InitStructure.GPIO_Mode = GPIO_MODE_AF_PP;
GPIO_InitStructure.GPIO_Pull = GPIO_PULL_UP;
GPIO_InitStructure.GPIO_Slew_Rate = GPIO_SLEW_RATE_SLOW;
GPIO_InitStructure.GPIO_Current = GPIO_DS_2mA;
GPIO_InitStructure.GPIO_Alternate = GPIO_AF5;
GPIO_InitStructure.Pin = GPIO_PIN_9;
GPIO_InitPeripheral(GPIOA, &GPIO_InitStructure);
/*Initialize input GPIO */
GPIO_InitStructure.GPIO_Mode = GPIO_MODE_INPUT;
GPIO_InitStructure.GPIO_Pull = GPIO_PULL_UP;
GPIO_InitStructure.GPIO_Alternate = GPIO_AF5;
GPIO_InitStructure.Pin = GPIO_PIN_10;
GPIO_InitPeripheral(GPIOA, &GPIO_InitStructure);
GPIO_ConfigPinRemap(0, 0, GPIO_RMP_SWJ_SWD);
/* NTFx CODE END */
return true;
}
/* NTFx CODE START */
/**
*@brief Initializes the NVIC
*@param null
*@return status
*/
bool NVIC_Configuration(void)
{
/*Configure the preemption priority and subpriority:
- 4 bits for pre-emption priority: possible value are 0..15
- 0 bits for subpriority: possible value are 0
- Lower values gives higher priority
*/
NVIC_PriorityGroupConfig(NVIC_PriorityGroup_4);
NVIC_SetPriority(SysTick_IRQn, NVIC_EncodePriority(4, 0, 0));
/* NTFx CODE END */
return true;
}
/* NTFx CODE START */
/**
*@brief Initializes the DMA
*@param null
*@return status
*/
bool DMA_Configuration(void)
{
/* NTFx CODE END */
return true;
}
/* NTFx CODE START */
/**
*@brief Initializes the USART
*@param null
*@return status
*/
bool USART_Configuration(void)
{
USART_InitType USART_InitStructure;
USART_StructInit(&USART_InitStructure);
/* Enable USART1 clock */
RCC_EnableAPB2PeriphClk(RCC_APB2_PERIPH_USART1, ENABLE);
/*********initialize the USART1************/
USART_DeInit(USART1);
USART_InitStructure.BaudRate = 115200;
USART_InitStructure.WordLength = USART_WL_8B;
USART_InitStructure.StopBits = USART_STPB_1;
USART_InitStructure.Parity = USART_PE_NO;
USART_InitStructure.HardwareFlowControl = USART_HFCTRL_NONE;
USART_InitStructure.Mode = USART_MODE_RX | USART_MODE_TX;
USART_InitStructure.OverSampling = USART_16OVER ;
/* Configure USART1 */
USART_Init(USART1, &USART_InitStructure);
/* Enable the USART1 */
USART_Enable(USART1, ENABLE);
/* NTFx CODE END */
return true;
}

71
bsp/n32/n32hxxx/n32h487zgl7-evb/board/Kconfig Normal file
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@ -0,0 +1,71 @@
menu "Hardware Drivers Config"
menu "Onboard Peripheral Drivers"
endmenu
menu "On-chip Peripheral Drivers"
config BSP_USING_GPIO
bool "Enable GPIO"
select RT_USING_PIN
default y
menuconfig BSP_USING_UART
bool "Enable UART"
default y
select RT_USING_SERIAL
if BSP_USING_UART
config BSP_USING_UART1
bool "Enable UART1"
default y
config BSP_UART1_RX_USING_DMA
bool "Enable UART1 RX DMA"
depends on BSP_USING_UART1 && RT_SERIAL_USING_DMA
default n
config BSP_UART1_TX_USING_DMA
bool "Enable UART1 TX DMA"
depends on BSP_USING_UART1 && RT_SERIAL_USING_DMA
default n
config BSP_USING_UART2
bool "Enable UART2"
default n
config BSP_UART2_RX_USING_DMA
bool "Enable UART2 RX DMA"
depends on BSP_USING_UART2 && RT_SERIAL_USING_DMA
default n
config BSP_UART2_TX_USING_DMA
bool "Enable UART2 TX DMA"
depends on BSP_USING_UART2 && RT_SERIAL_USING_DMA
default n
config BSP_USING_UART3
bool "Enable UART3"
default n
config BSP_UART3_RX_USING_DMA
bool "Enable UART3 RX DMA"
depends on BSP_USING_UART3 && RT_SERIAL_USING_DMA
default n
config BSP_UART3_TX_USING_DMA
bool "Enable UART3 TX DMA"
depends on BSP_USING_UART3 && RT_SERIAL_USING_DMA
default n
endif
source "$BSP_DIR/../libraries/N32_Drivers/drivers/Kconfig"
endmenu
menu "Board extended module Drivers"
endmenu
endmenu

27
bsp/n32/n32hxxx/n32h487zgl7-evb/board/SConscript Normal file
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@ -0,0 +1,27 @@
import os
from building import *
cwd = GetCurrentDir()
# add general drivers
src = Split('''
board.c
Cube_Config/USER/src/n32h47x_48x_cfg.c
''')
path = [cwd]
path += [os.path.join(cwd, 'Cube_Config', 'USER', 'inc')]
CPPDEFINES = ['N32H488', 'CORE_CM4']
group = DefineGroup('Drivers', src, depend = [''], CPPPATH = path, CPPDEFINES = CPPDEFINES)
# if os.path.isfile(os.path.join(cwd, "ports", 'SConscript')):
# group = group + SConscript(os.path.join("ports", 'SConscript'))
list = os.listdir(cwd)
for item in list:
if os.path.isfile(os.path.join(cwd, item, 'SConscript')):
group = group + SConscript(os.path.join(item, 'SConscript'))
Return('group')

27
bsp/n32/n32hxxx/n32h487zgl7-evb/board/board.c Normal file
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@ -0,0 +1,27 @@
/*
* Copyright (c) 2006-2026, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2026-04-03 ox-horse first version
*/
#include "board.h"
/**
* @brief System_Initialize
* @param None
* @retval None
*/
void System_Initialize(void)
{
/* Initialize system clock and enable Peripheral clock */
RCC_Configuration();
NVIC_PriorityGroupConfig(NVIC_PriorityGroup_2);
/* Config Peripheral GPIO */
GPIO_Configuration();
}

49
bsp/n32/n32hxxx/n32h487zgl7-evb/board/board.h Normal file
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@ -0,0 +1,49 @@
/*
* Copyright (c) 2006-2026, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2026-04-03 ox-horse first version
*/
#ifndef __BOARD_H__
#define __BOARD_H__
#include <rtthread.h>
#include "n32h47x_48x_cfg.h"
#include "drv_common.h"
#include "drv_gpio.h"
#ifdef __cplusplus
extern "C" {
#endif
#define N32_FLASH_START_ADRESS ((uint32_t)0x08000000)
#define N32_FLASH_SIZE (512 * 1024)
#define N32_FLASH_END_ADDRESS ((uint32_t)(N32_FLASH_START_ADRESS + N32_FLASH_SIZE))
#define N32_SRAM_SIZE (160)
#define N32_SRAM_END (0x20000000 + N32_SRAM_SIZE * 1024)
#if defined(__ARMCC_VERSION)
extern int Image$$RW_IRAM1$$ZI$$Limit;
#define HEAP_BEGIN (&Image$$RW_IRAM1$$ZI$$Limit)
#elif __ICCARM__
#pragma section = "CSTACK"
#define HEAP_BEGIN (__segment_end("CSTACK"))
#else
extern int __bss_end;
#define HEAP_BEGIN (&__bss_end)
#endif
#define HEAP_END N32_SRAM_END
void System_Initialize(void);
#ifdef __cplusplus
}
#endif
#endif

29
bsp/n32/n32hxxx/n32h487zgl7-evb/board/linker_scripts/link.icf Normal file
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@ -0,0 +1,29 @@
/*###ICF### Section handled by ICF editor, don't touch! ****/
/*-Editor annotation file-*/
/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
/*-Specials-*/
define symbol __ICFEDIT_intvec_start__ = 0x08000000;
/*-Memory Regions-*/
define symbol __ICFEDIT_region_ROM_start__ = 0x08000000;
define symbol __ICFEDIT_region_ROM_end__ = 0x0807FFFF;
define symbol __ICFEDIT_region_RAM1_start__ = 0x20000000;
define symbol __ICFEDIT_region_RAM1_end__ = 0x20028000;
/*-Sizes-*/
define symbol __ICFEDIT_size_cstack__ = 0x0400;
define symbol __ICFEDIT_size_heap__ = 0x000;
/**** End of ICF editor section. ###ICF###*/
define memory mem with size = 4G;
define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
define region RAM1_region = mem:[from __ICFEDIT_region_RAM1_start__ to __ICFEDIT_region_RAM1_end__];
define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
initialize by copy { readwrite };
do not initialize { section .noinit };
place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly };
place in RAM1_region { readwrite, last block CSTACK };

22
bsp/n32g452xx/n32g452xx-mini-system/board/linker_scripts/link.lds → bsp/n32/n32hxxx/n32h487zgl7-evb/board/linker_scripts/link.lds Executable file → Normal file
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@ -1,16 +1,15 @@
/*
* linker script for N32G452xx with GNU ld
* bernard.xiong 2009-10-14
* linker script for N32H48X with GNU ld
*/
/* Program Entry, set to mark it as "used" and avoid gc */
MEMORY
{
CODE (rx) : ORIGIN = 0x08000000, LENGTH = 256k /* 256KB flash */
DATA (rw) : ORIGIN = 0x20000000, LENGTH = 64k /* 64KB sram */
CODE (rx) : ORIGIN = 0x08000000, LENGTH = 512k /* 512KB flash */
RAM1 (rw) : ORIGIN = 0x20000000, LENGTH = 160k /* 160K sram */
}
ENTRY(Reset_Handler)
_system_stack_size = 0x200;
_system_stack_size = 0x400;
SECTIONS
{
@ -29,6 +28,12 @@ SECTIONS
*(.glue_7t)
*(.gnu.linkonce.t*)
/* section information for utest */
. = ALIGN(4);
__rt_utest_tc_tab_start = .;
KEEP(*(UtestTcTab))
__rt_utest_tc_tab_end = .;
/* section information for finsh shell */
. = ALIGN(4);
__fsymtab_start = .;
@ -54,6 +59,7 @@ SECTIONS
PROVIDE(__ctors_end__ = .);
. = ALIGN(4);
_etext = .;
} > CODE = 0
@ -88,7 +94,7 @@ SECTIONS
. = ALIGN(4);
/* This is used by the startup in order to initialize the .data secion */
_edata = . ;
} >DATA
} >RAM1
.stack :
{
@ -97,7 +103,7 @@ SECTIONS
. = . + _system_stack_size;
. = ALIGN(4);
_estack = .;
} >DATA
} >RAM1
__bss_start = .;
.bss :
@ -115,7 +121,7 @@ SECTIONS
_ebss = . ;
*(.bss.init)
} > DATA
} > RAM1
__bss_end = .;
_end = .;

6
bsp/n32g452xx/n32g452xx-mini-system/board/linker_scripts/link.sct → bsp/n32/n32hxxx/n32h487zgl7-evb/board/linker_scripts/link.sct Executable file → Normal file
View File

@ -2,13 +2,13 @@
; *** Scatter-Loading Description File generated by uVision ***
; *************************************************************
LR_IROM1 0x08000000 0x00040000 { ; load region size_region
ER_IROM1 0x08000000 0x00040000 { ; load address = execution address
LR_IROM1 0x08000000 0x00080000 { ; load region size_region
ER_IROM1 0x08000000 0x00080000 { ; load address = execution address
*.o (RESET, +First)
*(InRoot$$Sections)
.ANY (+RO)
}
RW_IRAM1 0x20000000 0x00014000 { ; RW data
RW_IRAM1 0x20000000 0x00028000 { ; RW data
.ANY (+RW +ZI)
}
}

19
bsp/n32/n32hxxx/n32h487zgl7-evb/board/ports/SConscript Normal file
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@ -0,0 +1,19 @@
import os
from building import *
objs = []
cwd = GetCurrentDir()
# add general drivers
src = []
path = [cwd]
CPPDEFINES = ['']
group = DefineGroup('Drivers', src, depend = [''], CPPPATH = path, CPPDEFINES = CPPDEFINES)
list = os.listdir(cwd)
for item in list:
if os.path.isfile(os.path.join(cwd, item, 'SConscript')):
group = group + SConscript(os.path.join(item, 'SConscript'))
Return('group')

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bsp/n32/n32hxxx/n32h487zgl7-evb/project.eww Normal file
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@ -0,0 +1,10 @@
<?xml version="1.0" encoding="iso-8859-1"?>
<workspace>
<project>
<path>$WS_DIR$\project.ewp</path>
</project>
<batchBuild/>
</workspace>

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447
bsp/n32/n32hxxx/n32h487zgl7-evb/rtconfig.h Normal file
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#ifndef RT_CONFIG_H__
#define RT_CONFIG_H__
#define SOC_N32H488ZEL7
/* RT-Thread Kernel */
/* klibc options */
/* rt_vsnprintf options */
/* end of rt_vsnprintf options */
/* rt_vsscanf options */
/* end of rt_vsscanf options */
/* rt_memset options */
/* end of rt_memset options */
/* rt_memcpy options */
/* end of rt_memcpy options */
/* rt_memmove options */
/* end of rt_memmove options */
/* rt_memcmp options */
/* end of rt_memcmp options */
/* rt_strstr options */
/* end of rt_strstr options */
/* rt_strcasecmp options */
/* end of rt_strcasecmp options */
/* rt_strncpy options */
/* end of rt_strncpy options */
/* rt_strcpy options */
/* end of rt_strcpy options */
/* rt_strncmp options */
/* end of rt_strncmp options */
/* rt_strcmp options */
/* end of rt_strcmp options */
/* rt_strlen options */
/* end of rt_strlen options */
/* rt_strnlen options */
/* end of rt_strnlen options */
/* end of klibc options */
#define RT_NAME_MAX 12
#define RT_CPUS_NR 1
#define RT_ALIGN_SIZE 8
#define RT_THREAD_PRIORITY_32
#define RT_THREAD_PRIORITY_MAX 32
#define RT_TICK_PER_SECOND 1000
#define RT_USING_OVERFLOW_CHECK
#define RT_USING_HOOK
#define RT_HOOK_USING_FUNC_PTR
#define RT_USING_IDLE_HOOK
#define RT_IDLE_HOOK_LIST_SIZE 4
#define IDLE_THREAD_STACK_SIZE 1024
/* kservice options */
/* end of kservice options */
#define RT_USING_DEBUG
#define RT_DEBUGING_ASSERT
#define RT_DEBUGING_COLOR
#define RT_DEBUGING_CONTEXT
/* Inter-Thread communication */
#define RT_USING_SEMAPHORE
#define RT_USING_MUTEX
#define RT_USING_EVENT
#define RT_USING_MAILBOX
#define RT_USING_MESSAGEQUEUE
/* end of Inter-Thread communication */
/* Memory Management */
#define RT_USING_MEMPOOL
#define RT_USING_MEMHEAP
#define RT_MEMHEAP_FAST_MODE
#define RT_USING_MEMHEAP_AS_HEAP
#define RT_USING_MEMHEAP_AUTO_BINDING
#define RT_USING_HEAP
/* end of Memory Management */
#define RT_USING_DEVICE
#define RT_USING_CONSOLE
#define RT_CONSOLEBUF_SIZE 512
#define RT_CONSOLE_DEVICE_NAME "uart1"
#define RT_USING_CONSOLE_OUTPUT_CTL
#define RT_VER_NUM 0x50300
#define RT_BACKTRACE_LEVEL_MAX_NR 32
/* end of RT-Thread Kernel */
#define RT_USING_HW_ATOMIC
#define ARCH_USING_HW_ATOMIC_8
#define ARCH_USING_HW_ATOMIC_16
#define RT_USING_CPU_FFS
#define ARCH_ARM
#define ARCH_ARM_CORTEX_M
#define ARCH_ARM_CORTEX_M4
/* RT-Thread Components */
#define RT_USING_COMPONENTS_INIT
#define RT_USING_USER_MAIN
#define RT_MAIN_THREAD_STACK_SIZE 2048
#define RT_MAIN_THREAD_PRIORITY 10
#define RT_USING_MSH
#define RT_USING_FINSH
#define FINSH_USING_MSH
#define FINSH_THREAD_NAME "tshell"
#define FINSH_THREAD_PRIORITY 20
#define FINSH_THREAD_STACK_SIZE 4096
#define FINSH_USING_HISTORY
#define FINSH_HISTORY_LINES 5
#define FINSH_USING_SYMTAB
#define FINSH_CMD_SIZE 80
#define MSH_USING_BUILT_IN_COMMANDS
#define FINSH_USING_DESCRIPTION
#define FINSH_ARG_MAX 10
#define FINSH_USING_OPTION_COMPLETION
/* DFS: device virtual file system */
/* end of DFS: device virtual file system */
/* Device Drivers */
#define RT_USING_DEVICE_IPC
#define RT_UNAMED_PIPE_NUMBER 64
#define RT_USING_SERIAL
#define RT_USING_SERIAL_V1
#define RT_SERIAL_USING_DMA
#define RT_SERIAL_RB_BUFSZ 512
#define RT_USING_PIN
/* end of Device Drivers */
/* C/C++ and POSIX layer */
/* ISO-ANSI C layer */
/* Timezone and Daylight Saving Time */
#define RT_LIBC_USING_LIGHT_TZ_DST
#define RT_LIBC_TZ_DEFAULT_HOUR 8
#define RT_LIBC_TZ_DEFAULT_MIN 0
#define RT_LIBC_TZ_DEFAULT_SEC 0
/* end of Timezone and Daylight Saving Time */
/* end of ISO-ANSI C layer */
/* POSIX (Portable Operating System Interface) layer */
/* Interprocess Communication (IPC) */
/* Socket is in the 'Network' category */
/* end of Interprocess Communication (IPC) */
/* end of POSIX (Portable Operating System Interface) layer */
/* end of C/C++ and POSIX layer */
/* Network */
/* end of Network */
/* Memory protection */
/* end of Memory protection */
/* Utilities */
/* end of Utilities */
/* Using USB legacy version */
/* end of Using USB legacy version */
/* end of RT-Thread Components */
/* RT-Thread Utestcases */
/* end of RT-Thread Utestcases */
/* RT-Thread online packages */
/* IoT - internet of things */
/* Wi-Fi */
/* Marvell WiFi */
/* end of Marvell WiFi */
/* Wiced WiFi */
/* end of Wiced WiFi */
/* CYW43012 WiFi */
/* end of CYW43012 WiFi */
/* BL808 WiFi */
/* end of BL808 WiFi */
/* CYW43439 WiFi */
/* end of CYW43439 WiFi */
/* end of Wi-Fi */
/* IoT Cloud */
/* end of IoT Cloud */
/* end of IoT - internet of things */
/* security packages */
/* end of security packages */
/* language packages */
/* JSON: JavaScript Object Notation, a lightweight data-interchange format */
/* end of JSON: JavaScript Object Notation, a lightweight data-interchange format */
/* XML: Extensible Markup Language */
/* end of XML: Extensible Markup Language */
/* end of language packages */
/* multimedia packages */
/* LVGL: powerful and easy-to-use embedded GUI library */
/* end of LVGL: powerful and easy-to-use embedded GUI library */
/* u8g2: a monochrome graphic library */
/* end of u8g2: a monochrome graphic library */
/* end of multimedia packages */
/* tools packages */
/* end of tools packages */
/* system packages */
/* enhanced kernel services */
/* end of enhanced kernel services */
/* acceleration: Assembly language or algorithmic acceleration packages */
/* end of acceleration: Assembly language or algorithmic acceleration packages */
/* CMSIS: ARM Cortex-M Microcontroller Software Interface Standard */
#define PKG_USING_CMSIS_CORE
#define PKG_USING_CMSIS_CORE_LATEST_VERSION
/* end of CMSIS: ARM Cortex-M Microcontroller Software Interface Standard */
/* Micrium: Micrium software products porting for RT-Thread */
/* end of Micrium: Micrium software products porting for RT-Thread */
/* end of system packages */
/* peripheral libraries and drivers */
/* HAL & SDK Drivers */
/* STM32 HAL & SDK Drivers */
/* end of STM32 HAL & SDK Drivers */
/* Infineon HAL Packages */
/* end of Infineon HAL Packages */
/* Kendryte SDK */
/* end of Kendryte SDK */
/* MM32 HAL & SDK Drivers */
/* end of MM32 HAL & SDK Drivers */
/* WCH HAL & SDK Drivers */
/* end of WCH HAL & SDK Drivers */
/* AT32 HAL & SDK Drivers */
/* end of AT32 HAL & SDK Drivers */
/* HC32 DDL Drivers */
/* end of HC32 DDL Drivers */
/* NXP HAL & SDK Drivers */
/* end of NXP HAL & SDK Drivers */
/* NUVOTON Drivers */
/* end of NUVOTON Drivers */
/* GD32 Drivers */
/* end of GD32 Drivers */
/* HPMicro SDK */
/* end of HPMicro SDK */
/* FT32 HAL & SDK Drivers */
/* end of FT32 HAL & SDK Drivers */
/* NOVOSNS Drivers */
/* end of NOVOSNS Drivers */
/* N32 Drivers */
#define PKG_USING_N32H47X_48X_STD_DRIVER
#define PKG_USING_N32H47X_48X_STD_DRIVER_LATEST_VERSION
#define PKG_USING_N32H47X_48X_CMSIS_DRIVER
#define PKG_USING_N32H47X_48X_CMSIS_DRIVER_LATEST_VERSION
/* end of N32 Drivers */
/* end of HAL & SDK Drivers */
/* sensors drivers */
/* end of sensors drivers */
/* touch drivers */
/* end of touch drivers */
/* end of peripheral libraries and drivers */
/* AI packages */
/* end of AI packages */
/* Signal Processing and Control Algorithm Packages */
/* end of Signal Processing and Control Algorithm Packages */
/* miscellaneous packages */
/* project laboratory */
/* end of project laboratory */
/* samples: kernel and components samples */
/* end of samples: kernel and components samples */
/* entertainment: terminal games and other interesting software packages */
/* end of entertainment: terminal games and other interesting software packages */
/* end of miscellaneous packages */
/* Arduino libraries */
/* Projects and Demos */
/* end of Projects and Demos */
/* Sensors */
/* end of Sensors */
/* Display */
/* end of Display */
/* Timing */
/* end of Timing */
/* Data Processing */
/* end of Data Processing */
/* Data Storage */
/* Communication */
/* end of Communication */
/* Device Control */
/* end of Device Control */
/* Other */
/* end of Other */
/* Signal IO */
/* end of Signal IO */
/* Uncategorized */
/* end of Arduino libraries */
/* end of RT-Thread online packages */
#define SOC_FAMILY_N32
#define SOC_SERIES_N32H47x_48x
/* Hardware Drivers Config */
/* Onboard Peripheral Drivers */
/* On-chip Peripheral Drivers */
#define BSP_USING_GPIO
#define BSP_USING_UART
#define BSP_USING_UART1
/* end of On-chip Peripheral Drivers */
/* Board extended module Drivers */
/* end of Hardware Drivers Config */
#endif

73
bsp/n32g452xx/n32g452xx-mini-system/rtconfig.py → bsp/n32/n32hxxx/n32h487zgl7-evb/rtconfig.py Executable file → Normal file
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@ -1,7 +1,5 @@
import os
print(os.path.abspath(__file__))
# toolchains options
ARCH='arm'
CPU='cortex-m4'
@ -14,25 +12,21 @@ if os.getenv('RTT_CC'):
CROSS_TOOL = os.getenv('RTT_CC')
if os.getenv('RTT_ROOT'):
RTT_ROOT = os.getenv('RTT_ROOT')
else:
RTT_ROOT = os.path.normpath(os.getcwd() + '/../../..')
# cross_tool provides the cross compiler
# EXEC_PATH is the compiler execute path, for example, CodeSourcery, Keil MDK, IAR
if os.getenv('RTT_EXEC_PATH'):
EXEC_PATH = os.getenv('RTT_EXEC_PATH')
if CROSS_TOOL == 'gcc':
PLATFORM = 'gcc'
if ('EXEC_PATH' in dir()) == False:
EXEC_PATH = r'/opt/gcc-arm-none-eabi-6_2-2016q4/bin'
EXEC_PATH = r'C:\Users\XXYYZZ'
elif CROSS_TOOL == 'keil':
PLATFORM = 'armcc'
if ('EXEC_PATH' in dir()) == False:
EXEC_PATH = r'C:/Keil_v5'
EXEC_PATH = r'C:/Keil_v5'
elif CROSS_TOOL == 'iar':
PLATFORM = 'iccarm'
if ('EXEC_PATH' in dir()) == False:
EXEC_PATH = r'C:/Program Files (x86)/IAR Systems/Embedded Workbench 8.3'
EXEC_PATH = r'C:/Program Files (x86)/IAR Systems/Embedded Workbench 8.3'
if os.getenv('RTT_EXEC_PATH'):
EXEC_PATH = os.getenv('RTT_EXEC_PATH')
BUILD = 'debug'
@ -63,7 +57,8 @@ if PLATFORM == 'gcc':
else:
CFLAGS += ' -O2'
CXXFLAGS = CFLAGS
CXXFLAGS = CFLAGS
CFLAGS += ' -std=c99'
POST_ACTION = OBJCPY + ' -O binary $TARGET rtthread.bin\n' + SIZE + ' $TARGET \n'
@ -94,6 +89,40 @@ elif PLATFORM == 'armcc':
else:
CFLAGS += ' -O2'
CXXFLAGS = CFLAGS
CFLAGS += ' -std=c99'
POST_ACTION = 'fromelf --bin $TARGET --output rtthread.bin \nfromelf -z $TARGET'
elif PLATFORM == 'armclang':
# toolchains
CC = 'armclang'
CXX = 'armclang'
AS = 'armasm'
AR = 'armar'
LINK = 'armlink'
TARGET_EXT = 'axf'
DEVICE = ' --cpu Cortex-M4.fp '
CFLAGS = ' --target=arm-arm-none-eabi -mcpu=cortex-m4 '
CFLAGS += ' -mcpu=cortex-m4 -mfpu=fpv4-sp-d16 '
CFLAGS += ' -mfloat-abi=hard -c -fno-rtti -funsigned-char -fshort-enums -fshort-wchar '
CFLAGS += ' -gdwarf-3 -ffunction-sections '
AFLAGS = DEVICE + ' --apcs=interwork '
LFLAGS = DEVICE + ' --info sizes --info totals --info unused --info veneers '
LFLAGS += ' --list rt-thread.map '
LFLAGS += r' --strict --scatter "board\linker_scripts\link.sct" '
CFLAGS += ' -I' + EXEC_PATH + '/ARM/ARMCLANG/include'
LFLAGS += ' --libpath=' + EXEC_PATH + '/ARM/ARMCLANG/lib'
EXEC_PATH += '/ARM/ARMCLANG/bin/'
if BUILD == 'debug':
CFLAGS += ' -g -O1' # armclang recommend
AFLAGS += ' -g'
else:
CFLAGS += ' -O2'
CXXFLAGS = CFLAGS
CFLAGS += ' -std=c99'
@ -144,7 +173,7 @@ elif PLATFORM == 'iccarm':
LFLAGS += ' --entry __iar_program_start'
CXXFLAGS = CFLAGS
EXEC_PATH = EXEC_PATH + '/arm/bin/'
POST_ACTION = 'ielftool --bin $TARGET rtthread.bin'
@ -154,19 +183,3 @@ def dist_handle(BSP_ROOT, dist_dir):
sys.path.append(os.path.join(os.path.dirname(BSP_ROOT), 'tools'))
from sdk_dist import dist_do_building
dist_do_building(BSP_ROOT, dist_dir)
print('ARCH =[%s]' %(ARCH ))
print('CPU =[%s]' %(CPU ))
print('CROSS_TOOL =[%s]' %(CROSS_TOOL))
print('RTT_ROOT =[%s]' %(RTT_ROOT ))
print('PLATFORM =[%s]' %(PLATFORM ))
print('EXEC_PATH =[%s]' %(EXEC_PATH ))
print('CC =[%s]' %(CC ))
print('AS =[%s]' %(AS ))
print('AR =[%s]' %(AR ))
print('LINK =[%s]' %(LINK ))
print('TARGET_EXT =[%s]' %(TARGET_EXT))
print('DEVICE =[%s]' %(DEVICE ))
print('CFLAGS =[%s]' %(CFLAGS ))
print('AFLAGS =[%s]' %(AFLAGS ))
print('LFLAGS =[%s]' %(LFLAGS ))

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bsp/n32/n32hxxx/n32h487zgl7-evb/template.ewp Normal file
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10
bsp/n32/n32hxxx/n32h487zgl7-evb/template.eww Normal file
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@ -0,0 +1,10 @@
<?xml version="1.0" encoding="iso-8859-1"?>
<workspace>
<project>
<path>$WS_DIR$\template.ewp</path>
</project>
<batchBuild/>
</workspace>

190
bsp/n32/n32hxxx/n32h487zgl7-evb/template.uvoptx Normal file
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@ -0,0 +1,190 @@
<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
<ProjectOpt xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_optx.xsd">
<SchemaVersion>1.0</SchemaVersion>
<Header>### uVision Project, (C) Keil Software</Header>
<Extensions>
<cExt>*.c</cExt>
<aExt>*.s*; *.src; *.a*</aExt>
<oExt>*.obj; *.o</oExt>
<lExt>*.lib</lExt>
<tExt>*.txt; *.h; *.inc; *.md</tExt>
<pExt>*.plm</pExt>
<CppX>*.cpp</CppX>
<nMigrate>0</nMigrate>
</Extensions>
<DaveTm>
<dwLowDateTime>0</dwLowDateTime>
<dwHighDateTime>0</dwHighDateTime>
</DaveTm>
<Target>
<TargetName>rt-thread</TargetName>
<ToolsetNumber>0x4</ToolsetNumber>
<ToolsetName>ARM-ADS</ToolsetName>
<TargetOption>
<CLKADS>12000000</CLKADS>
<OPTTT>
<gFlags>1</gFlags>
<BeepAtEnd>1</BeepAtEnd>
<RunSim>0</RunSim>
<RunTarget>1</RunTarget>
<RunAbUc>0</RunAbUc>
</OPTTT>
<OPTHX>
<HexSelection>1</HexSelection>
<FlashByte>65535</FlashByte>
<HexRangeLowAddress>0</HexRangeLowAddress>
<HexRangeHighAddress>0</HexRangeHighAddress>
<HexOffset>0</HexOffset>
</OPTHX>
<OPTLEX>
<PageWidth>79</PageWidth>
<PageLength>66</PageLength>
<TabStop>8</TabStop>
<ListingPath>.\build\keil\List\</ListingPath>
</OPTLEX>
<ListingPage>
<CreateCListing>1</CreateCListing>
<CreateAListing>1</CreateAListing>
<CreateLListing>1</CreateLListing>
<CreateIListing>0</CreateIListing>
<AsmCond>1</AsmCond>
<AsmSymb>1</AsmSymb>
<AsmXref>0</AsmXref>
<CCond>1</CCond>
<CCode>0</CCode>
<CListInc>0</CListInc>
<CSymb>0</CSymb>
<LinkerCodeListing>0</LinkerCodeListing>
</ListingPage>
<OPTXL>
<LMap>1</LMap>
<LComments>1</LComments>
<LGenerateSymbols>1</LGenerateSymbols>
<LLibSym>1</LLibSym>
<LLines>1</LLines>
<LLocSym>1</LLocSym>
<LPubSym>1</LPubSym>
<LXref>0</LXref>
<LExpSel>0</LExpSel>
</OPTXL>
<OPTFL>
<tvExp>1</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<IsCurrentTarget>1</IsCurrentTarget>
</OPTFL>
<CpuCode>255</CpuCode>
<DebugOpt>
<uSim>0</uSim>
<uTrg>1</uTrg>
<sLdApp>1</sLdApp>
<sGomain>1</sGomain>
<sRbreak>1</sRbreak>
<sRwatch>1</sRwatch>
<sRmem>1</sRmem>
<sRfunc>1</sRfunc>
<sRbox>1</sRbox>
<tLdApp>1</tLdApp>
<tGomain>1</tGomain>
<tRbreak>1</tRbreak>
<tRwatch>1</tRwatch>
<tRmem>1</tRmem>
<tRfunc>0</tRfunc>
<tRbox>1</tRbox>
<tRtrace>1</tRtrace>
<sRSysVw>1</sRSysVw>
<tRSysVw>1</tRSysVw>
<sRunDeb>0</sRunDeb>
<sLrtime>0</sLrtime>
<bEvRecOn>1</bEvRecOn>
<bSchkAxf>0</bSchkAxf>
<bTchkAxf>0</bTchkAxf>
<nTsel>3</nTsel>
<sDll></sDll>
<sDllPa></sDllPa>
<sDlgDll></sDlgDll>
<sDlgPa></sDlgPa>
<sIfile></sIfile>
<tDll></tDll>
<tDllPa></tDllPa>
<tDlgDll></tDlgDll>
<tDlgPa></tDlgPa>
<tIfile></tIfile>
<pMon>BIN\CMSIS_AGDI.dll</pMon>
</DebugOpt>
<TargetDriverDllRegistry>
<SetRegEntry>
<Number>0</Number>
<Key>CMSIS_AGDI</Key>
<Name>-X"Any" -UAny -O206 -S0 -C0 -P00000000 -N00("ARM CoreSight SW-DP") -D00(2BA01477) -L00(0) -TO65554 -TC10000000 -TT10000000 -TP20 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO7 -FD20000000 -FC3000 -FN1 -FF0N32H48x_512 -FS08000000 -FL080000 -FP0($$Device:N32H488ZE$Flash\N32H48x_512.FLM)</Name>
</SetRegEntry>
<SetRegEntry>
<Number>0</Number>
<Key>UL2CM3</Key>
<Name>UL2CM3(-S0 -C0 -P0 ) -FN1 -FC3000 -FD20000000 -FF0N32H48x_512 -FL080000 -FS08000000 -FP0($$Device:N32H488ZE$Flash\N32H48x_512.FLM)</Name>
</SetRegEntry>
<SetRegEntry>
<Number>0</Number>
<Key>JL2CM3</Key>
<Name>UL2CM3(-S0 -C0 -P0 ) -FN1 -FC3000 -FD20000000 -FF0N32H48x_512 -FL080000 -FS08000000 -FP0($$Device:N32H488ZE$Flash\N32H48x_512.FLM)</Name>
</SetRegEntry>
</TargetDriverDllRegistry>
<Breakpoint/>
<Tracepoint>
<THDelay>0</THDelay>
</Tracepoint>
<DebugFlag>
<trace>0</trace>
<periodic>0</periodic>
<aLwin>0</aLwin>
<aCover>0</aCover>
<aSer1>0</aSer1>
<aSer2>0</aSer2>
<aPa>0</aPa>
<viewmode>0</viewmode>
<vrSel>0</vrSel>
<aSym>0</aSym>
<aTbox>0</aTbox>
<AscS1>0</AscS1>
<AscS2>0</AscS2>
<AscS3>0</AscS3>
<aSer3>0</aSer3>
<eProf>0</eProf>
<aLa>0</aLa>
<aPa1>0</aPa1>
<AscS4>0</AscS4>
<aSer4>0</aSer4>
<StkLoc>0</StkLoc>
<TrcWin>0</TrcWin>
<newCpu>0</newCpu>
<uProt>0</uProt>
</DebugFlag>
<LintExecutable></LintExecutable>
<LintConfigFile></LintConfigFile>
<bLintAuto>0</bLintAuto>
<bAutoGenD>0</bAutoGenD>
<LntExFlags>0</LntExFlags>
<pMisraName></pMisraName>
<pszMrule></pszMrule>
<pSingCmds></pSingCmds>
<pMultCmds></pMultCmds>
<pMisraNamep></pMisraNamep>
<pszMrulep></pszMrulep>
<pSingCmdsp></pSingCmdsp>
<pMultCmdsp></pMultCmdsp>
</TargetOption>
</Target>
<Group>
<GroupName>Source Group 1</GroupName>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<cbSel>0</cbSel>
<RteFlg>0</RteFlg>
</Group>
</ProjectOpt>

51
bsp/n32g452xx/n32g452xx-mini-system/template.uvprojx → bsp/n32/n32hxxx/n32h487zgl7-evb/template.uvprojx Executable file → Normal file
View File

@ -7,22 +7,23 @@
<Targets>
<Target>
<TargetName>rtthread-n32</TargetName>
<TargetName>rt-thread</TargetName>
<ToolsetNumber>0x4</ToolsetNumber>
<ToolsetName>ARM-ADS</ToolsetName>
<pCCUsed>5060960::V5.06 update 7 (build 960)::.\ARMCC</pCCUsed>
<uAC6>0</uAC6>
<TargetOption>
<TargetCommonOption>
<Device>N32G452RCL7</Device>
<Device>N32H488ZE</Device>
<Vendor>Nationstech</Vendor>
<PackID>Nationstech.N32G45x_DFP.1.0.1</PackID>
<PackID>Nationstech.N32H48x_DFP.1.2.0</PackID>
<PackURL>http://www.keil.com/pack/</PackURL>
<Cpu>IRAM(0x20000000,0x24000) IROM(0x08000000,0x40000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE</Cpu>
<Cpu>IRAM(0x20000000,0x30000) IROM(0x08000000,0x80000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE</Cpu>
<FlashUtilSpec></FlashUtilSpec>
<StartupFile></StartupFile>
<FlashDriverDll>UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0N32G45x -FS08000000 -FL040000 -FP0($$Device:N32G452RCL7$Flash\N32G45x.FLM))</FlashDriverDll>
<FlashDriverDll>UL2CM3(-S0 -C0 -P0 -FD20000000 -FC3000 -FN1 -FF0N32H48x_512 -FS08000000 -FL080000 -FP0($$Device:N32H488ZE$Flash\N32H48x_512.FLM))</FlashDriverDll>
<DeviceId>0</DeviceId>
<RegisterFile>$$Device:N32G452RCL7$firmware\CMSIS\device\n32g45x.h</RegisterFile>
<RegisterFile>$$Device:N32H488ZE$firmware\CMSIS\device\n32h48x.h</RegisterFile>
<MemoryEnv></MemoryEnv>
<Cmp></Cmp>
<Asm></Asm>
@ -32,7 +33,7 @@
<SLE66CMisc></SLE66CMisc>
<SLE66AMisc></SLE66AMisc>
<SLE66LinkerMisc></SLE66LinkerMisc>
<SFDFile>$$Device:N32G452RCL7$svd\N32G452.svd</SFDFile>
<SFDFile>$$Device:N32H488ZE$svd\N32H488.svd</SFDFile>
<bCustSvd>0</bCustSvd>
<UseEnv>0</UseEnv>
<BinPath></BinPath>
@ -47,14 +48,14 @@
<NotGenerated>0</NotGenerated>
<InvalidFlash>1</InvalidFlash>
</TargetStatus>
<OutputDirectory>.\build\</OutputDirectory>
<OutputDirectory>.\build\keil\Obj\</OutputDirectory>
<OutputName>rt-thread</OutputName>
<CreateExecutable>1</CreateExecutable>
<CreateLib>0</CreateLib>
<CreateHexFile>0</CreateHexFile>
<CreateHexFile>1</CreateHexFile>
<DebugInformation>1</DebugInformation>
<BrowseInformation>0</BrowseInformation>
<ListingPath>.\build\</ListingPath>
<BrowseInformation>1</BrowseInformation>
<ListingPath>.\build\keil\List\</ListingPath>
<HexFormatSelection>1</HexFormatSelection>
<Merge32K>0</Merge32K>
<CreateBatchFile>0</CreateBatchFile>
@ -245,12 +246,12 @@
<IRAM>
<Type>0</Type>
<StartAddress>0x20000000</StartAddress>
<Size>0x24000</Size>
<Size>0x30000</Size>
</IRAM>
<IROM>
<Type>1</Type>
<StartAddress>0x8000000</StartAddress>
<Size>0x40000</Size>
<Size>0x80000</Size>
</IROM>
<XRAM>
<Type>0</Type>
@ -275,7 +276,7 @@
<OCR_RVCT4>
<Type>1</Type>
<StartAddress>0x8000000</StartAddress>
<Size>0x40000</Size>
<Size>0x80000</Size>
</OCR_RVCT4>
<OCR_RVCT5>
<Type>1</Type>
@ -300,7 +301,7 @@
<OCR_RVCT9>
<Type>0</Type>
<StartAddress>0x20000000</StartAddress>
<Size>0x24000</Size>
<Size>0x30000</Size>
</OCR_RVCT9>
<OCR_RVCT10>
<Type>0</Type>
@ -315,13 +316,13 @@
<Optim>1</Optim>
<oTime>0</oTime>
<SplitLS>0</SplitLS>
<OneElfS>0</OneElfS>
<OneElfS>1</OneElfS>
<Strict>0</Strict>
<EnumInt>0</EnumInt>
<PlainCh>0</PlainCh>
<Ropi>0</Ropi>
<Rwpi>0</Rwpi>
<wLevel>0</wLevel>
<wLevel>2</wLevel>
<uThumb>0</uThumb>
<uSurpInc>0</uSurpInc>
<uC99>1</uC99>
@ -351,7 +352,7 @@
<NoWarn>0</NoWarn>
<uSurpInc>0</uSurpInc>
<useXO>0</useXO>
<ClangAsOpt>1</ClangAsOpt>
<ClangAsOpt>4</ClangAsOpt>
<VariousControls>
<MiscControls></MiscControls>
<Define></Define>
@ -378,6 +379,11 @@
</LDads>
</TargetArmAds>
</TargetOption>
<Groups>
<Group>
<GroupName>Source Group 1</GroupName>
</Group>
</Groups>
</Target>
</Targets>
@ -387,13 +393,4 @@
<files/>
</RTE>
<LayerInfo>
<Layers>
<Layer>
<LayName>template</LayName>
<LayPrjMark>1</LayPrjMark>
</Layer>
</Layers>
</LayerInfo>
</Project>

10
bsp/n32/n32hxxx/n32h497zgl7-evb/.ci/attachconfig/ci.attachconfig.yml Normal file
View File

@ -0,0 +1,10 @@
scons.args: &scons
scons_arg:
- '--strict'
# ------ nano ------
nano:
<<: *scons
kconfig:
- CONFIG_RT_USING_NANO=y

133
bsp/n32g452xx/n32g452xx-mini-system/.config → bsp/n32/n32hxxx/n32h497zgl7-evb/.config
View File

@ -1,3 +1,4 @@
CONFIG_SOC_N32H497ZGL7=y
#
# RT-Thread Kernel
@ -109,6 +110,7 @@
CONFIG_RT_NAME_MAX=12
# CONFIG_RT_USING_ARCH_DATA_TYPE is not set
# CONFIG_RT_USING_NANO is not set
# CONFIG_RT_USING_SMART is not set
# CONFIG_RT_USING_AMP is not set
# CONFIG_RT_USING_SMP is not set
CONFIG_RT_CPUS_NR=1
@ -117,18 +119,15 @@ CONFIG_RT_ALIGN_SIZE=8
CONFIG_RT_THREAD_PRIORITY_32=y
# CONFIG_RT_THREAD_PRIORITY_256 is not set
CONFIG_RT_THREAD_PRIORITY_MAX=32
CONFIG_RT_TICK_PER_SECOND=100
CONFIG_RT_TICK_PER_SECOND=1000
CONFIG_RT_USING_OVERFLOW_CHECK=y
CONFIG_RT_USING_HOOK=y
CONFIG_RT_HOOK_USING_FUNC_PTR=y
# CONFIG_RT_USING_HOOKLIST is not set
CONFIG_RT_USING_IDLE_HOOK=y
CONFIG_RT_IDLE_HOOK_LIST_SIZE=4
CONFIG_IDLE_THREAD_STACK_SIZE=256
CONFIG_RT_USING_TIMER_SOFT=y
CONFIG_RT_TIMER_THREAD_PRIO=4
CONFIG_RT_TIMER_THREAD_STACK_SIZE=512
# CONFIG_RT_USING_TIMER_ALL_SOFT is not set
CONFIG_IDLE_THREAD_STACK_SIZE=1024
# CONFIG_RT_USING_TIMER_SOFT is not set
# CONFIG_RT_USING_CPU_USAGE_TRACER is not set
#
@ -160,11 +159,14 @@ CONFIG_RT_USING_MESSAGEQUEUE=y
# Memory Management
#
CONFIG_RT_USING_MEMPOOL=y
CONFIG_RT_USING_SMALL_MEM=y
# CONFIG_RT_USING_SMALL_MEM is not set
# CONFIG_RT_USING_SLAB is not set
# CONFIG_RT_USING_MEMHEAP is not set
CONFIG_RT_USING_SMALL_MEM_AS_HEAP=y
# CONFIG_RT_USING_MEMHEAP_AS_HEAP is not set
CONFIG_RT_USING_MEMHEAP=y
CONFIG_RT_MEMHEAP_FAST_MODE=y
# CONFIG_RT_MEMHEAP_BEST_MODE is not set
# CONFIG_RT_USING_SMALL_MEM_AS_HEAP is not set
CONFIG_RT_USING_MEMHEAP_AS_HEAP=y
CONFIG_RT_USING_MEMHEAP_AUTO_BINDING=y
# CONFIG_RT_USING_SLAB_AS_HEAP is not set
# CONFIG_RT_USING_USERHEAP is not set
# CONFIG_RT_USING_NOHEAP is not set
@ -178,7 +180,7 @@ CONFIG_RT_USING_DEVICE=y
# CONFIG_RT_USING_INTERRUPT_INFO is not set
# CONFIG_RT_USING_THREADSAFE_PRINTF is not set
CONFIG_RT_USING_CONSOLE=y
CONFIG_RT_CONSOLEBUF_SIZE=128
CONFIG_RT_CONSOLEBUF_SIZE=512
CONFIG_RT_CONSOLE_DEVICE_NAME="uart1"
CONFIG_RT_USING_CONSOLE_OUTPUT_CTL=y
CONFIG_RT_VER_NUM=0x50300
@ -186,6 +188,14 @@ CONFIG_RT_VER_NUM=0x50300
CONFIG_RT_BACKTRACE_LEVEL_MAX_NR=32
# end of RT-Thread Kernel
CONFIG_RT_USING_HW_ATOMIC=y
CONFIG_ARCH_USING_HW_ATOMIC_8=y
CONFIG_ARCH_USING_HW_ATOMIC_16=y
CONFIG_RT_USING_CPU_FFS=y
CONFIG_ARCH_ARM=y
CONFIG_ARCH_ARM_CORTEX_M=y
CONFIG_ARCH_ARM_CORTEX_M4=y
#
# RT-Thread Components
#
@ -233,14 +243,14 @@ CONFIG_RT_USING_SERIAL=y
CONFIG_RT_USING_SERIAL_V1=y
# CONFIG_RT_USING_SERIAL_V2 is not set
CONFIG_RT_SERIAL_USING_DMA=y
CONFIG_RT_SERIAL_RB_BUFSZ=64
CONFIG_RT_SERIAL_RB_BUFSZ=512
# CONFIG_RT_USING_SERIAL_BYPASS is not set
# CONFIG_RT_USING_CAN is not set
# CONFIG_RT_USING_ADC is not set
# CONFIG_RT_USING_CLOCK_TIME is not set
# CONFIG_RT_USING_I2C is not set
# CONFIG_RT_USING_PHY is not set
# CONFIG_RT_USING_PHY_V2 is not set
# CONFIG_RT_USING_ADC is not set
# CONFIG_RT_USING_DAC is not set
# CONFIG_RT_USING_NULL is not set
# CONFIG_RT_USING_ZERO is not set
@ -261,10 +271,10 @@ CONFIG_RT_SERIAL_RB_BUFSZ=64
# CONFIG_RT_USING_LCD is not set
# CONFIG_RT_USING_HWCRYPTO is not set
# CONFIG_RT_USING_WIFI is not set
# CONFIG_RT_USING_RPMSG is not set
# CONFIG_RT_USING_BLK is not set
# CONFIG_RT_USING_REGULATOR is not set
# CONFIG_RT_USING_POWER_SUPPLY is not set
# CONFIG_RT_USING_VIRTIO is not set
CONFIG_RT_USING_PIN=y
# CONFIG_RT_USING_CHERRYUSB is not set
# end of Device Drivers
@ -457,6 +467,7 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
# CONFIG_PKG_USING_ABUP_FOTA is not set
# CONFIG_PKG_USING_LIBCURL2RTT is not set
# CONFIG_PKG_USING_CAPNP is not set
# CONFIG_PKG_USING_ERPC is not set
# CONFIG_PKG_USING_AGILE_TELNET is not set
# CONFIG_PKG_USING_NMEALIB is not set
# CONFIG_PKG_USING_PDULIB is not set
@ -571,6 +582,7 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
# CONFIG_PKG_USING_VT100 is not set
# CONFIG_PKG_USING_QRCODE is not set
# CONFIG_PKG_USING_GUIENGINE is not set
# CONFIG_PKG_USING_PERSIMMON is not set
# CONFIG_PKG_USING_3GPP_AMRNB is not set
# end of multimedia packages
@ -624,6 +636,7 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
# CONFIG_PKG_USING_HASH_MATCH is not set
# CONFIG_PKG_USING_ARMV7M_DWT_TOOL is not set
# CONFIG_PKG_USING_VOFA_PLUS is not set
# CONFIG_PKG_USING_RT_TRACE is not set
# CONFIG_PKG_USING_ZDEBUG is not set
# CONFIG_PKG_USING_RVBACKTRACE is not set
# CONFIG_PKG_USING_HPATCHLITE is not set
@ -631,6 +644,7 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
# CONFIG_PKG_USING_UORB is not set
# CONFIG_PKG_USING_RT_TUNNEL is not set
# CONFIG_PKG_USING_VIRTUAL_TERMINAL is not set
# CONFIG_PKG_USING_FEE is not set
# end of tools packages
#
@ -658,7 +672,10 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
# CMSIS: ARM Cortex-M Microcontroller Software Interface Standard
#
# CONFIG_PKG_USING_CMSIS_5 is not set
# CONFIG_PKG_USING_CMSIS_CORE is not set
CONFIG_PKG_USING_CMSIS_CORE=y
CONFIG_PKG_CMSIS_CORE_PATH="/packages/system/CMSIS/CMSIS-Core"
CONFIG_PKG_USING_CMSIS_CORE_LATEST_VERSION=y
CONFIG_PKG_CMSIS_CORE_VER="latest"
# CONFIG_PKG_USING_CMSIS_NN is not set
# CONFIG_PKG_USING_CMSIS_RTOS1 is not set
# CONFIG_PKG_USING_CMSIS_RTOS2 is not set
@ -811,7 +828,21 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
# CONFIG_PKG_USING_NRFX is not set
# CONFIG_PKG_USING_RASPBERRYPI_PICO_RP2350_SDK is not set
# CONFIG_PKG_USING_RASPBERRYPI_PICO_SDK is not set
# CONFIG_PKG_USING_MM32 is not set
#
# MM32 HAL & SDK Drivers
#
# CONFIG_PKG_USING_MM32F103XX_CMSIS is not set
# CONFIG_PKG_USING_MM32F3270X_CMSIS is not set
# CONFIG_PKG_USING_MM32F5260X_CMSIS is not set
# CONFIG_PKG_USING_MM32L0XX_CMSIS is not set
# CONFIG_PKG_USING_MM32L3XX_CMSIS is not set
# CONFIG_PKG_USING_MM32F103XX_HAL_DRIVER is not set
# CONFIG_PKG_USING_MM32F3270X_HAL_DRIVER is not set
# CONFIG_PKG_USING_MM32F5260X_HAL_DRIVER is not set
# CONFIG_PKG_USING_MM32L0XX_HAL_DRIVER is not set
# CONFIG_PKG_USING_MM32L3XX_HAL_DRIVER is not set
# end of MM32 HAL & SDK Drivers
#
# WCH HAL & SDK Drivers
@ -899,6 +930,29 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
# CONFIG_PKG_USING_FT32F4_STD_DRIVER is not set
# CONFIG_PKG_USING_FT32F4_CMSIS_DRIVER is not set
# end of FT32 HAL & SDK Drivers
#
# NOVOSNS Drivers
#
# CONFIG_PKG_USING_NOVOSNS_SERIES_DRIVER is not set
# end of NOVOSNS Drivers
#
# N32 Drivers
#
# CONFIG_PKG_USING_N32H7XX_STD_DRIVER is not set
# CONFIG_PKG_USING_N32H7XX_CMSIS_DRIVER is not set
CONFIG_PKG_USING_N32H49X_STD_DRIVER=y
CONFIG_PKG_N32H49X_STD_DRIVER_PATH="/packages/peripherals/hal-sdk/n32/n32h49x_std_driver"
CONFIG_PKG_USING_N32H49X_STD_DRIVER_LATEST_VERSION=y
CONFIG_PKG_N32H49X_STD_DRIVER_VER="latest"
CONFIG_PKG_USING_N32H49X_CMSIS_DRIVER=y
CONFIG_PKG_N32H49X_CMSIS_DRIVER_PATH="/packages/peripherals/hal-sdk/n32/n32h49x_cmsis_driver"
CONFIG_PKG_USING_N32H49X_CMSIS_DRIVER_LATEST_VERSION=y
CONFIG_PKG_N32H49X_CMSIS_DRIVER_VER="latest"
# CONFIG_PKG_USING_N32H47X_48X_STD_DRIVER is not set
# CONFIG_PKG_USING_N32H47X_48X_CMSIS_DRIVER is not set
# end of N32 Drivers
# end of HAL & SDK Drivers
#
@ -1082,6 +1136,7 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
# CONFIG_PKG_USING_IRUART is not set
# CONFIG_PKG_USING_ST7305 is not set
# CONFIG_PKG_USING_TM1668 is not set
# CONFIG_PKG_USING_TCA9548A is not set
# CONFIG_PKG_USING_SPI_TOOLS is not set
# end of peripheral libraries and drivers
@ -1110,6 +1165,7 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
# CONFIG_PKG_USING_UKAL is not set
# CONFIG_PKG_USING_DIGITALCTRL is not set
# CONFIG_PKG_USING_KISSFFT is not set
# CONFIG_PKG_USING_CMSIS_DSP is not set
# end of Signal Processing and Control Algorithm Packages
#
@ -1144,6 +1200,7 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
# CONFIG_PKG_USING_DONUT is not set
# CONFIG_PKG_USING_COWSAY is not set
# CONFIG_PKG_USING_MORSE is not set
# CONFIG_PKG_USING_TINYSQUARE is not set
# end of entertainment: terminal games and other interesting software packages
# CONFIG_PKG_USING_LIBCSV is not set
@ -1181,6 +1238,7 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
# CONFIG_PKG_USING_QPARAM is not set
# CONFIG_PKG_USING_CorevMCU_CLI is not set
# CONFIG_PKG_USING_DRMP is not set
# CONFIG_PKG_USING_AUTOGEN_PARAMETER_MANAGER is not set
# end of miscellaneous packages
#
@ -1420,53 +1478,30 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
# end of Arduino libraries
# end of RT-Thread online packages
CONFIG_SOC_FAMILY_N32=y
CONFIG_SOC_SERIES_N32H49x=y
#
# Hardware Drivers Config
#
CONFIG_SOC_N32G452XX=y
#
# Onboard Peripheral Drivers
#
CONFIG_BSP_USING_UART=y
# end of Onboard Peripheral Drivers
#
# On-chip Peripheral Drivers
#
# CONFIG_N32G45X_PIN_NUMBERS_48 is not set
CONFIG_N32G45X_PIN_NUMBERS_64=y
# CONFIG_N32G45X_PIN_NUMBERS_100 is not set
# CONFIG_N32G45X_PIN_NUMBERS_128 is not set
CONFIG_N32G45X_PIN_NUMBERS=64
CONFIG_BSP_USING_GPIO=y
#
# Remap JTAG Port
#
# CONFIG_BSP_RMP_SW_JTAG_FULL_ENABLE is not set
# CONFIG_BSP_RMP_SW_JTAG_NO_NJTRST is not set
CONFIG_BSP_RMP_SW_JTAG_SW_ENABLE=y
# CONFIG_BSP_RMP_SW_JTAG_DISABLE is not set
# end of Remap JTAG Port
# CONFIG_BSP_USING_ON_CHIP_FLASH is not set
# CONFIG_BSP_USING_WDT is not set
CONFIG_BSP_USING_UART=y
CONFIG_BSP_USING_UART1=y
# CONFIG_BSP_USING_UART1_PIN_RMP is not set
CONFIG_BSP_USING_UART1_NO_RMP=y
# CONFIG_BSP_UART1_RX_USING_DMA is not set
# CONFIG_BSP_UART1_TX_USING_DMA is not set
# CONFIG_BSP_USING_UART2 is not set
# CONFIG_BSP_USING_UART3 is not set
# CONFIG_BSP_USING_UART4 is not set
# CONFIG_BSP_USING_UART5 is not set
# CONFIG_BSP_USING_UART6 is not set
# CONFIG_BSP_USING_UART7 is not set
# CONFIG_BSP_USING_PWM is not set
# CONFIG_BSP_USING_CLOCK_TIMER is not set
# CONFIG_BSP_USING_SPI is not set
# CONFIG_BSP_USING_I2C1 is not set
# CONFIG_BSP_USING_ADC is not set
# CONFIG_BSP_USING_CAN is not set
# CONFIG_BSP_USING_SDIO is not set
# end of On-chip Peripheral Drivers
#
# Board extended module Drivers
#
# end of Hardware Drivers Config

41
bsp/n32/n32hxxx/n32h497zgl7-evb/.gitignore vendored Normal file
View File

@ -0,0 +1,41 @@
*.pyc
*.map
*.dblite
*.elf
*.bin
*.hex
*.axf
*.exe
*.pdb
*.idb
*.ilk
*.old
build
Debug
documentation/html
*~
*.o
*.obj
*.out
*.bak
*.dep
*.lib
*.i
*.d
.DS_Stor*
.config 3
.config 4
.config 5
Midea-X1
*.uimg
GPATH
GRTAGS
GTAGS
.vscode
JLinkLog.txt
JLinkSettings.ini
DebugConfig/
RTE/
settings/
*.uvguix*
cconfig.h

22
bsp/n32/n32hxxx/n32h497zgl7-evb/Kconfig Normal file
View File

@ -0,0 +1,22 @@
mainmenu "RT-Thread Configuration"
BSP_DIR := .
RTT_DIR := ../../../..
PKGS_DIR := packages
config SOC_N32H497ZGL7
bool
select SOC_SERIES_N32H49x
select RT_USING_COMPONENTS_INIT
select RT_USING_USER_MAIN
default y
source "$(RTT_DIR)/Kconfig"
osource "$PKGS_DIR/Kconfig"
rsource "../libraries/Kconfig"
if !RT_USING_NANO
rsource "board/Kconfig"
endif

121
bsp/n32/n32hxxx/n32h497zgl7-evb/README.md Normal file
View File

@ -0,0 +1,121 @@
# N32H497ZGL7 开发板 BSP 说明
## 简介
本文档为 RT-Thread 开发团队为 N32H497ZGL7 开发板提供的 BSP (板级支持包) 说明。
主要内容如下：
- 开发板资源介绍
- BSP 快速上手
- 进阶使用方法
通过阅读快速上手章节开发者可以快速地上手该 BSP，将 RT-Thread 运行在开发板上。在进阶使用指南章节，将会介绍更多高级功能，帮助开发者利用 RT-Thread 驱动更多板载资源。
## 开发板介绍
N32H497ZGL7_EVB V1.0 是 Nsing 推出的一款基于 ARM Cortex-M4 内核的开发板，最高主频为 240Mhz，该开发板具有丰富的板载资源，可以充分发挥 N32H497 的芯片性能。
开发板外观如下图所示：
![board](figures/board.jpg)
该开发板常用 **板载资源** 如下：
- MCU：N32H497ZGL7，主频 240MHz，1024KB FLASH ，448KB RAM
- 外部 PSRAM：APS1604M-3SQR-SN（XSPI-PSRAM）
- 外部 SDRAM：M12L64164A-5TG2C
- 外部 EEROM：AT24C02
- 外部 FLASH：W25Q128JVSIQTR（SPI）、P25Q40HA-SSH-IT（XSPI）
- 常用外设
- LED：3个，LED1（PA3），LED2（PB3），LED3（PA8）
- 按键：4个，WKUP（兼具唤醒功能，PA0），KEY1（PC13），KEY2（PA15），KEY3
- 常用接口：USB 转串口、CAN 接口、RS485 接口、LIN 接口、以太网接口
- 调试接口，标准 JTAG/SWD
## 外设支持
本 BSP 目前对外设的支持情况如下：
| **片上外设** | **支持情况** | **备注** |
| GPIO | 支持 | PA0, PA1... PH5 ---> PIN: 0, 1...117 |
| UART | 支持 | UART1/2/3, 如需使用该外设，请使用 Cube 重新配 |
## 使用说明
使用说明分为如下两个章节：
- 快速上手
本章节是为刚接触 RT-Thread 的新手准备的使用说明，遵循简单的步骤即可将 RT-Thread 操作系统运行在该开发板上，看到实验效果 。
- 进阶使用
本章节是为需要在 RT-Thread 操作系统上使用更多开发板资源的开发者准备的。通过使用 ENV 工具对 BSP 进行配置，可以开启更多板载资源，实现更多高级功能。
### 快速上手
本 BSP 为开发者提供 MDK5 和 IAR 工程，并且支持 GCC 开发环境。下面以 MDK5 开发环境为例，介绍如何将系统运行起来。
**请注意！！！**
在执行编译工作前请先打开ENV执行以下指令（该指令用于拉取必要的 STD 库及 CMSIS 库，否则无法通过编译）：
```bash
pkgs --update
```
#### 硬件连接
使用数据线连接开发板到 PC，打开电源开关。
#### 编译下载
双击 project.uvprojx 文件，打开 MDK5 工程，编译并下载程序到开发板。
> 工程默认配置使用 CMSIS-DAP 下载程序，在通过 USB 线连接开发板的基础上，点击下载按钮即可下载程序到开发板
#### 运行结果
下载程序成功之后，系统会自动运行，观察开发板上 LED1 的运行效果，LED1 会周期性闪烁。
连接开发板对应串口到 PC , 在终端工具里打开相应的串口（115200-8-1-N），复位设备后，可以看到 RT-Thread 的输出信息:
```bash
\ | /
- RT - Thread Operating System
/ | \ 5.3.0 build Jul 16 2026 11:18:41
2006 - 2024 Copyright by RT-Thread team
msh >
```
### 进阶使用
此 BSP 默认只开启了 GPIO 和 串口1 的功能，如果需使用更多高级功能，需要利用 ENV 工具对BSP 进行配置，步骤如下：
1. 在 bsp 下打开 env 工具。
2. 输入`menuconfig`命令配置工程，配置好之后保存退出。
3. 输入`pkgs --update`命令更新软件包。
4. 输入`scons --target=mdk5/iar` 命令重新生成工程。
## 注意事项
- 调试串口为串口 1 映射说明
PA9 ------> USART1_TX
PA10 ------> USART1_RX
- 按键 KEY3 说明
若需要使用按键 KEY3，需要拔了 J43 跳线帽，使用杜邦线连接到 PB4
## 联系人信息
维护人:
- [OnlyoutzZ](https://github.com/OnlyoutzZ)

18
bsp/n32/n32hxxx/n32h497zgl7-evb/SConscript Normal file
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@ -0,0 +1,18 @@
# for module compiling
import os
Import('RTT_ROOT')
Import('env')
from building import *
cwd = GetCurrentDir()
objs = []
list = os.listdir(cwd)
env.Append(CPPDEFINES = ['N32H49x'])
for d in list:
path = os.path.join(cwd, d)
if os.path.isfile(os.path.join(path, 'SConscript')):
objs = objs + SConscript(os.path.join(d, 'SConscript'))
Return('objs')

74
bsp/n32/n32hxxx/n32h497zgl7-evb/SConstruct Normal file
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@ -0,0 +1,74 @@
import os
import sys
import rtconfig
if os.getenv('RTT_ROOT'):
RTT_ROOT = os.getenv('RTT_ROOT')
else:
RTT_ROOT = os.path.normpath(os.getcwd() + '/../../../..')
sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')]
try:
from building import *
except:
print('Cannot found RT-Thread root directory, please check RTT_ROOT')
print(RTT_ROOT)
exit(-1)
def bsp_pkg_check():
import subprocess
check_paths = [
os.path.join("packages", "CMSIS-Core-latest"),
os.path.join("packages", "n32h49x_cmsis_driver-latest"),
os.path.join("packages", "n32h49x_std_driver-latest")
]
need_update = not all(os.path.exists(p) for p in check_paths)
if need_update:
print("\n===============================================================================")
print("Dependency packages missing, please running 'pkgs --update'...")
print("If no packages are fetched, run 'pkgs --upgrade' first, then 'pkgs --update'...")
print("===============================================================================")
exit(1)
RegisterPreBuildingAction(bsp_pkg_check)
TARGET = 'rt-thread.' + rtconfig.TARGET_EXT
DefaultEnvironment(tools=[])
env = Environment(tools = ['mingw'],
AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS,
CC = rtconfig.CC, CFLAGS = rtconfig.CFLAGS,
AR = rtconfig.AR, ARFLAGS = '-rc',
CXX = rtconfig.CXX, CXXFLAGS = rtconfig.CXXFLAGS,
LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS)
env.PrependENVPath('PATH', rtconfig.EXEC_PATH)
if rtconfig.PLATFORM in ['iccarm']:
env.Replace(CCCOM = ['$CC $CFLAGS $CPPFLAGS $_CPPDEFFLAGS $_CPPINCFLAGS -o $TARGET $SOURCES'])
env.Replace(ARFLAGS = [''])
env.Replace(LINKCOM = env["LINKCOM"] + ' --map rt-thread.map')
Export('env')
Export('RTT_ROOT')
Export('rtconfig')
SDK_ROOT = os.path.abspath('./')
if os.path.exists(SDK_ROOT + '/libraries'):
libraries_path_prefix = SDK_ROOT + '/libraries'
else:
libraries_path_prefix = os.path.dirname(SDK_ROOT) + '/libraries'
# prepare building environment
objs = PrepareBuilding(env, RTT_ROOT, has_libcpu=False)
rtconfig.BSP_LIBRARY_TYPE = None
# include drivers
objs.extend(SConscript(os.path.join(libraries_path_prefix, 'N32_Drivers', 'SConscript'),variant_dir='build/libraries/N32_Drivers', duplicate=0))
# make a building
DoBuilding(TARGET, objs)

15
bsp/n32/n32hxxx/n32h497zgl7-evb/applications/SConscript Normal file
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@ -0,0 +1,15 @@
from building import *
import os
cwd = GetCurrentDir()
CPPPATH = [cwd]
src = ['main.c']
group = DefineGroup('Applications', src, depend = [''], CPPPATH = CPPPATH)
list = os.listdir(cwd)
for item in list:
if os.path.isfile(os.path.join(cwd, item, 'SConscript')):
group = group + SConscript(os.path.join(item, 'SConscript'))
Return('group')

33
bsp/n32/n32hxxx/n32h497zgl7-evb/applications/main.c Normal file
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@ -0,0 +1,33 @@
/*
* Copyright (c) 2006-2026, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2026-07-15 ox-horse first version
*/
#include <board.h>
#include <rtthread.h>
#include <drv_gpio.h>
#ifndef RT_USING_NANO
#include <rtdevice.h>
#endif /* RT_USING_NANO */
/* defined the LED1 pin: PA3 */
#define LED1_PIN GET_PIN(A, 3)
int main(void)
{
/* set LED1 pin mode to output */
rt_pin_mode(LED1_PIN, PIN_MODE_OUTPUT);
while (1)
{
rt_pin_write(LED1_PIN, PIN_HIGH);
rt_thread_mdelay(500);
rt_pin_write(LED1_PIN, PIN_LOW);
rt_thread_mdelay(500);
}
}

BIN
bsp/n32/n32hxxx/n32h497zgl7-evb/board/Cube_Config/Cube_Config.ntfx Normal file
View File

Binary file not shown.

30
bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/USER/inc/n32h76x_78x_cfg.h → bsp/n32/n32hxxx/n32h497zgl7-evb/board/Cube_Config/USER/inc/n32h49x_cfg.h
View File

@ -1,32 +1,32 @@
/**
* @file n32h76x_78x_cfg.h
* @file n32h49x_cfg.h
* @author N32cube
*/
#ifndef __N32H76X_78X_CFG_H__
#define __N32H76X_78X_CFG_H__
#ifndef __N32H49X_CFG_H__
#define __N32H49X_CFG_H__
#ifdef __cplusplus
extern "C" {
#endif
/* NTFx CODE START INCLUDE*/
#include "n32h76x_78x.h"
#include "n32h76x_78x_rcc.h"
#include "n32h49x.h"
#include "n32h49x_dbg.h"
#include "n32h49x_vrefbuf.h"
#include "n32h49x_flash.h"
#include "n32h49x_rcc.h"
#include "misc.h"
#include "n32h76x_78x_dma.h"
#include "n32h76x_78x_gpio.h"
#include "n32h76x_78x_usart.h"
#include "n32h76x_78x_pwr.h"
#include "n32h76x_78x_dmamux.h"
#include "n32h76x_78x_mdma.h"
#include "n32h49x_dma.h"
#include "n32h49x_gpio.h"
#include "n32h49x_usart.h"
/* NTFx CODE END INCLUDE*/
/* NTFx CODE START Extern*/
extern void SysTick_Delayms(uint32_t Delayms);
extern void DMA_SetPerMemAddr(DMA_ChannelType* DMAChx, uint32_t periphAddr,uint32_t memAddr,uint32_t bufSize );
extern void DMA_SetPerMemAddr(DMA_ChannelType* DMAChx, uint32_t periphAddr, uint32_t memAddr, uint32_t bufSize);
extern bool RCC_Configuration(void);
extern bool GPIO_Configuration(void);
extern bool NVIC_Configuration(void);
extern bool DMA_Configuration(void);
extern bool GPIO_Configuration(void);
extern bool USART_Configuration(void);
/* NTFx CODE END Extern*/
@ -34,7 +34,7 @@ extern bool USART_Configuration(void);
}
#endif
#endif /* __MAIN_H__ */
#endif /* __N32H49X_CFG_H__ */
/**
* @}
*/

211
bsp/n32/n32hxxx/n32h497zgl7-evb/board/Cube_Config/USER/src/n32h49x_cfg.c Normal file
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@ -0,0 +1,211 @@
/**
* @file n32h49x_cfg.c
* @author N32cube
*/
#include "n32h49x_cfg.h"
/* NTFx CODE START */
__IO uint32_t mwTick;
void SysTick_Delayms(uint32_t Delayms)
{
uint32_t tickstart = mwTick;
uint32_t wait = Delayms;
/* Add 1 to guarantee minimum wait */
if (wait < 0xFFFFFFFFU)
{
wait += 1;
}
while ((mwTick - tickstart) < wait)
{
}
}
/**
*@name DMA_SetPerMemAddr.
*@brief Set peripher address and memory address of DMA
*@param DMAChx (The input parameters must be the following values):
* - DMA1_CH1
* - DMA1_CH2
* - DMA1_CH3
* - DMA1_CH4
* - DMA1_CH5
* - DMA1_CH6
* - DMA1_CH7
* - DMA1_CH8
* - DMA2_CH1
* - DMA2_CH2
* - DMA2_CH3
* - DMA2_CH4
* - DMA2_CH5
* - DMA2_CH6
* - DMA2_CH7
* - DMA2_CH8
*@param periphAddr peripher address
*@param memAddr memory address
*@param bufSize buff size
*@return status
*/
void DMA_SetPerMemAddr(DMA_ChannelType* DMAChx, uint32_t periphAddr, uint32_t memAddr, uint32_t bufSize)
{
/* DMAy Channelx TXNUM Configuration */
/* Write to DMAy Channelx TXNUM */
DMAChx->TXNUM = bufSize;
/* DMAy Channelx PADDR Configuration */
/* Write to DMAy Channelx PADDR */
DMAChx->PADDR = periphAddr;
/* DMAy Channelx MADDR Configuration */
/* Write to DMAy Channelx MADDR */
DMAChx->MADDR = memAddr;
}
/* NTFx CODE END */
/* NTFx CODE START */
/**
*@brief Initializes the clock tree
*@param null
*@return status
*/
bool RCC_Configuration(void)
{
ErrorStatus ClockStatus;
RCC_DeInit();
RCC_EnableHsi(ENABLE);
/* Wait till HSI is ready */
ClockStatus = RCC_WaitHsiStable();
if (ClockStatus != SUCCESS) return false;
RCC_ConfigPll(RCC_PLL_SRC_HSI, RCC_PLL_PRE_2, RCC_PLL_MUL_60, RCC_PLLOUT_DIV_1);
/* Enable PLL */
RCC_EnablePll(ENABLE);
/* Wait till PLL is ready */
while (RCC_GetFlagStatus(RCC_FLAG_PLLRDF) != SET);
RCC_ConfigHclk(RCC_SYSCLK_DIV1);
RCC_ConfigPclk2(RCC_HCLK_DIV2);
RCC_ConfigPclk1(RCC_HCLK_DIV2);
RCC_ConfigPeriphClk(RCC_PERIPH_HCLK_DIV1);
/* Enable Prefetch Buffer */
FLASH_PrefetchBufSet(FLASH_PrefetchBuf_EN);
/* Flash wait state */
FLASH_SetLatency(FLASH_LATENCY_4);
/*config RNG clock*/
RCC_ConfigTrng1mClk(RCC_TRNG1MCLK_SRC_HSI, RCC_TRNG1MCLK_DIV8);
RCC_EnableTrng1mClk(ENABLE);
RCC_ConfigRngcClk(RCC_RNGCCLK_SYSCLK_DIV1);
/* Select PLL as system clock source */
RCC_ConfigSysclk(RCC_SYSCLK_SRC_PLL);
/* Wait till PLL is used as system clock source */
while (RCC_GetSysclkSrc() != RCC_CFG_SCLKSTS_PLL) ;
/* Configure the SysTick to have interrupt in 1ms time basis*/
SysTick_Config(240000);
/* NTFx CODE END */
return true;
}
/* NTFx CODE START */
/**
*@brief Initializes the GPIO
*@param null
*@return status
*/
bool GPIO_Configuration(void)
{
GPIO_InitType GPIO_InitStructure;
GPIO_InitStruct(&GPIO_InitStructure);
/* Enable the GPIO clock*/
RCC_EnableAHB1PeriphClk(RCC_AHB_PERIPHEN_GPIOH | RCC_AHB_PERIPHEN_GPIOA, ENABLE);
RCC_EnableAPB2PeriphClk(RCC_APB2_PERIPHEN_AFIO, ENABLE);
/*********Initialize USART1 GPIO function *********/
/********PA9->USART1.TX********/
/********PA10->USART1.RX********/
/*Initialize AF_PP GPIO */
GPIO_InitStructure.GPIO_Mode = GPIO_MODE_AF_PP;
GPIO_InitStructure.GPIO_Pull = GPIO_PULL_UP;
GPIO_InitStructure.GPIO_Slew_Rate = GPIO_SLEW_RATE_SLOW;
GPIO_InitStructure.GPIO_Current = GPIO_DS_2mA;
GPIO_InitStructure.GPIO_Alternate = GPIO_AF5;
GPIO_InitStructure.Pin = GPIO_PIN_9;
GPIO_InitPeripheral(GPIOA, &GPIO_InitStructure);
/*Initialize input GPIO */
GPIO_InitStructure.GPIO_Mode = GPIO_MODE_INPUT;
GPIO_InitStructure.GPIO_Pull = GPIO_PULL_UP;
GPIO_InitStructure.GPIO_Alternate = GPIO_AF5;
GPIO_InitStructure.Pin = GPIO_PIN_10;
GPIO_InitPeripheral(GPIOA, &GPIO_InitStructure);
GPIO_ConfigPinRemap(0, 0, GPIO_RMP_SWJ_SWD);
/* NTFx CODE END */
return true;
}
/* NTFx CODE START */
/**
*@brief Initializes the NVIC
*@param null
*@return status
*/
bool NVIC_Configuration(void)
{
/*Configure the preemption priority and subpriority:
- 4 bits for pre-emption priority: possible value are 0..15
- 0 bits for subpriority: possible value are 0
- Lower values gives higher priority
*/
NVIC_PriorityGroupConfig(NVIC_PriorityGroup_4);
NVIC_SetPriority(SysTick_IRQn, NVIC_EncodePriority(4, 15, 0));
/* NTFx CODE END */
return true;
}
/* NTFx CODE START */
/**
*@brief Initializes the DMA
*@param null
*@return status
*/
bool DMA_Configuration(void)
{
/* NTFx CODE END */
return true;
}
/* NTFx CODE START */
/**
*@brief Initializes the USART
*@param null
*@return status
*/
bool USART_Configuration(void)
{
USART_InitType USART_InitStructure;
USART_StructInit(&USART_InitStructure);
/* Enable USART1 clock */
RCC_EnableAPB2PeriphClk(RCC_APB2_PERIPHEN_USART1, ENABLE);
/*********initialize the USART1************/
USART_DeInit(USART1);
USART_InitStructure.BaudRate = 115200;
USART_InitStructure.WordLength = USART_WL_8B;
USART_InitStructure.StopBits = USART_STPB_1;
USART_InitStructure.Parity = USART_PE_NO;
USART_InitStructure.HardwareFlowControl = USART_HFCTRL_NONE;
USART_InitStructure.Mode = USART_MODE_RX | USART_MODE_TX;
USART_InitStructure.OverSampling = USART_16OVER ;
/* Configure USART1 */
USART_Init(USART1, &USART_InitStructure);
/* Enable the USART1 */
USART_Enable(USART1, ENABLE);
/* NTFx CODE END */
return true;
}

71
bsp/n32/n32hxxx/n32h497zgl7-evb/board/Kconfig Normal file
View File

@ -0,0 +1,71 @@
menu "Hardware Drivers Config"
menu "Onboard Peripheral Drivers"
endmenu
menu "On-chip Peripheral Drivers"
config BSP_USING_GPIO
bool "Enable GPIO"
select RT_USING_PIN
default y
menuconfig BSP_USING_UART
bool "Enable UART"
default y
select RT_USING_SERIAL
if BSP_USING_UART
config BSP_USING_UART1
bool "Enable UART1"
default y
config BSP_UART1_RX_USING_DMA
bool "Enable UART1 RX DMA"
depends on BSP_USING_UART1 && RT_SERIAL_USING_DMA
default n
config BSP_UART1_TX_USING_DMA
bool "Enable UART1 TX DMA"
depends on BSP_USING_UART1 && RT_SERIAL_USING_DMA
default n
config BSP_USING_UART2
bool "Enable UART2"
default n
config BSP_UART2_RX_USING_DMA
bool "Enable UART2 RX DMA"
depends on BSP_USING_UART2 && RT_SERIAL_USING_DMA
default n
config BSP_UART2_TX_USING_DMA
bool "Enable UART2 TX DMA"
depends on BSP_USING_UART2 && RT_SERIAL_USING_DMA
default n
config BSP_USING_UART3
bool "Enable UART3"
default n
config BSP_UART3_RX_USING_DMA
bool "Enable UART3 RX DMA"
depends on BSP_USING_UART3 && RT_SERIAL_USING_DMA
default n
config BSP_UART3_TX_USING_DMA
bool "Enable UART3 TX DMA"
depends on BSP_USING_UART3 && RT_SERIAL_USING_DMA
default n
endif
source "$BSP_DIR/../libraries/N32_Drivers/drivers/Kconfig"
endmenu
menu "Board extended module Drivers"
endmenu
endmenu

27
bsp/n32/n32hxxx/n32h497zgl7-evb/board/SConscript Normal file
View File

@ -0,0 +1,27 @@
import os
from building import *
cwd = GetCurrentDir()
# add general drivers
src = Split('''
board.c
Cube_Config/USER/src/n32h49x_cfg.c
''')
path = [cwd]
path += [os.path.join(cwd, 'Cube_Config', 'USER', 'inc')]
CPPDEFINES = ['N32H49x', 'CORE_CM4']
group = DefineGroup('Drivers', src, depend = [''], CPPPATH = path, CPPDEFINES = CPPDEFINES)
# if os.path.isfile(os.path.join(cwd, "ports", 'SConscript')):
# group = group + SConscript(os.path.join("ports", 'SConscript'))
list = os.listdir(cwd)
for item in list:
if os.path.isfile(os.path.join(cwd, item, 'SConscript')):
group = group + SConscript(os.path.join(item, 'SConscript'))
Return('group')

27
bsp/n32/n32hxxx/n32h497zgl7-evb/board/board.c Normal file
View File

@ -0,0 +1,27 @@
/*
* Copyright (c) 2006-2026, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2026-04-03 ox-horse first version
*/
#include "board.h"
/**
* @brief System_Initialize
* @param None
* @retval None
*/
void System_Initialize(void)
{
/* Initialize system clock and enable Peripheral clock */
RCC_Configuration();
NVIC_PriorityGroupConfig(NVIC_PriorityGroup_2);
/* Config Peripheral GPIO */
GPIO_Configuration();
}

55
bsp/n32/n32hxxx/n32h497zgl7-evb/board/board.h Normal file
View File

@ -0,0 +1,55 @@
/*
* Copyright (c) 2006-2026, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2026-04-03 ox-horse first version
*/
#ifndef __BOARD_H__
#define __BOARD_H__
#include <rtthread.h>
#include "n32h49x_cfg.h"
#include "n32h49x_exti.h"
#include "misc.h"
#include "n32h49x_dma.h"
#include "n32h49x_pwr.h"
#include "n32h49x_dbg.h"
#include "n32h49x_flash.h"
#include "drv_common.h"
#include "drv_gpio.h"
#ifdef __cplusplus
extern "C" {
#endif
#define N32_FLASH_START_ADRESS ((uint32_t)0x08000000)
#define N32_FLASH_SIZE (1024 * 1024)
#define N32_FLASH_END_ADDRESS ((uint32_t)(N32_FLASH_START_ADRESS + N32_FLASH_SIZE))
#define N32_SRAM_SIZE (448)
#define N32_SRAM_END (0x20000000 + N32_SRAM_SIZE * 1024)
#if defined(__ARMCC_VERSION)
extern int Image$$RW_IRAM1$$ZI$$Limit;
#define HEAP_BEGIN (&Image$$RW_IRAM1$$ZI$$Limit)
#elif __ICCARM__
#pragma section = "CSTACK"
#define HEAP_BEGIN (__segment_end("CSTACK"))
#else
extern int __bss_end;
#define HEAP_BEGIN (&__bss_end)
#endif
#define HEAP_END N32_SRAM_END
void System_Initialize(void);
#ifdef __cplusplus
}
#endif
#endif

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